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8c660648 | 1 | /* Instruction scheduling pass. |
a5cad800 | 2 | Copyright (C) 1992, 93-98, 1999 Free Software Foundation, Inc. |
8c660648 JL |
3 | Contributed by Michael Tiemann (tiemann@cygnus.com) Enhanced by, |
4 | and currently maintained by, Jim Wilson (wilson@cygnus.com) | |
5 | ||
6 | This file is part of GNU CC. | |
7 | ||
8 | GNU CC is free software; you can redistribute it and/or modify it | |
9 | under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 2, or (at your option) | |
11 | any later version. | |
12 | ||
13 | GNU CC is distributed in the hope that it will be useful, but | |
14 | WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
16 | General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with GNU CC; see the file COPYING. If not, write to the Free | |
20 | the Free Software Foundation, 59 Temple Place - Suite 330, | |
21 | Boston, MA 02111-1307, USA. */ | |
22 | ||
23 | ||
24 | /* Instruction scheduling pass. | |
25 | ||
26 | This pass implements list scheduling within basic blocks. It is | |
27 | run twice: (1) after flow analysis, but before register allocation, | |
28 | and (2) after register allocation. | |
29 | ||
30 | The first run performs interblock scheduling, moving insns between | |
31 | different blocks in the same "region", and the second runs only | |
32 | basic block scheduling. | |
33 | ||
34 | Interblock motions performed are useful motions and speculative | |
35 | motions, including speculative loads. Motions requiring code | |
36 | duplication are not supported. The identification of motion type | |
37 | and the check for validity of speculative motions requires | |
38 | construction and analysis of the function's control flow graph. | |
39 | The scheduler works as follows: | |
40 | ||
41 | We compute insn priorities based on data dependencies. Flow | |
42 | analysis only creates a fraction of the data-dependencies we must | |
43 | observe: namely, only those dependencies which the combiner can be | |
44 | expected to use. For this pass, we must therefore create the | |
45 | remaining dependencies we need to observe: register dependencies, | |
46 | memory dependencies, dependencies to keep function calls in order, | |
47 | and the dependence between a conditional branch and the setting of | |
48 | condition codes are all dealt with here. | |
49 | ||
50 | The scheduler first traverses the data flow graph, starting with | |
51 | the last instruction, and proceeding to the first, assigning values | |
52 | to insn_priority as it goes. This sorts the instructions | |
53 | topologically by data dependence. | |
54 | ||
55 | Once priorities have been established, we order the insns using | |
56 | list scheduling. This works as follows: starting with a list of | |
57 | all the ready insns, and sorted according to priority number, we | |
58 | schedule the insn from the end of the list by placing its | |
59 | predecessors in the list according to their priority order. We | |
60 | consider this insn scheduled by setting the pointer to the "end" of | |
61 | the list to point to the previous insn. When an insn has no | |
62 | predecessors, we either queue it until sufficient time has elapsed | |
63 | or add it to the ready list. As the instructions are scheduled or | |
64 | when stalls are introduced, the queue advances and dumps insns into | |
65 | the ready list. When all insns down to the lowest priority have | |
66 | been scheduled, the critical path of the basic block has been made | |
67 | as short as possible. The remaining insns are then scheduled in | |
68 | remaining slots. | |
69 | ||
70 | Function unit conflicts are resolved during forward list scheduling | |
71 | by tracking the time when each insn is committed to the schedule | |
72 | and from that, the time the function units it uses must be free. | |
73 | As insns on the ready list are considered for scheduling, those | |
74 | that would result in a blockage of the already committed insns are | |
75 | queued until no blockage will result. | |
76 | ||
77 | The following list shows the order in which we want to break ties | |
78 | among insns in the ready list: | |
79 | ||
80 | 1. choose insn with the longest path to end of bb, ties | |
81 | broken by | |
82 | 2. choose insn with least contribution to register pressure, | |
83 | ties broken by | |
84 | 3. prefer in-block upon interblock motion, ties broken by | |
85 | 4. prefer useful upon speculative motion, ties broken by | |
86 | 5. choose insn with largest control flow probability, ties | |
87 | broken by | |
88 | 6. choose insn with the least dependences upon the previously | |
89 | scheduled insn, or finally | |
2db45993 JL |
90 | 7 choose the insn which has the most insns dependent on it. |
91 | 8. choose insn with lowest UID. | |
8c660648 JL |
92 | |
93 | Memory references complicate matters. Only if we can be certain | |
94 | that memory references are not part of the data dependency graph | |
95 | (via true, anti, or output dependence), can we move operations past | |
96 | memory references. To first approximation, reads can be done | |
97 | independently, while writes introduce dependencies. Better | |
98 | approximations will yield fewer dependencies. | |
99 | ||
100 | Before reload, an extended analysis of interblock data dependences | |
101 | is required for interblock scheduling. This is performed in | |
102 | compute_block_backward_dependences (). | |
103 | ||
104 | Dependencies set up by memory references are treated in exactly the | |
105 | same way as other dependencies, by using LOG_LINKS backward | |
106 | dependences. LOG_LINKS are translated into INSN_DEPEND forward | |
107 | dependences for the purpose of forward list scheduling. | |
108 | ||
109 | Having optimized the critical path, we may have also unduly | |
110 | extended the lifetimes of some registers. If an operation requires | |
111 | that constants be loaded into registers, it is certainly desirable | |
112 | to load those constants as early as necessary, but no earlier. | |
113 | I.e., it will not do to load up a bunch of registers at the | |
114 | beginning of a basic block only to use them at the end, if they | |
115 | could be loaded later, since this may result in excessive register | |
116 | utilization. | |
117 | ||
118 | Note that since branches are never in basic blocks, but only end | |
119 | basic blocks, this pass will not move branches. But that is ok, | |
120 | since we can use GNU's delayed branch scheduling pass to take care | |
121 | of this case. | |
122 | ||
123 | Also note that no further optimizations based on algebraic | |
124 | identities are performed, so this pass would be a good one to | |
125 | perform instruction splitting, such as breaking up a multiply | |
126 | instruction into shifts and adds where that is profitable. | |
127 | ||
128 | Given the memory aliasing analysis that this pass should perform, | |
129 | it should be possible to remove redundant stores to memory, and to | |
130 | load values from registers instead of hitting memory. | |
131 | ||
132 | Before reload, speculative insns are moved only if a 'proof' exists | |
133 | that no exception will be caused by this, and if no live registers | |
134 | exist that inhibit the motion (live registers constraints are not | |
135 | represented by data dependence edges). | |
136 | ||
137 | This pass must update information that subsequent passes expect to | |
138 | be correct. Namely: reg_n_refs, reg_n_sets, reg_n_deaths, | |
3b413743 RH |
139 | reg_n_calls_crossed, and reg_live_length. Also, BLOCK_HEAD, |
140 | BLOCK_END. | |
8c660648 JL |
141 | |
142 | The information in the line number notes is carefully retained by | |
143 | this pass. Notes that refer to the starting and ending of | |
144 | exception regions are also carefully retained by this pass. All | |
145 | other NOTE insns are grouped in their same relative order at the | |
146 | beginning of basic blocks and regions that have been scheduled. | |
147 | ||
148 | The main entry point for this pass is schedule_insns(), called for | |
149 | each function. The work of the scheduler is organized in three | |
150 | levels: (1) function level: insns are subject to splitting, | |
151 | control-flow-graph is constructed, regions are computed (after | |
152 | reload, each region is of one block), (2) region level: control | |
153 | flow graph attributes required for interblock scheduling are | |
154 | computed (dominators, reachability, etc.), data dependences and | |
155 | priorities are computed, and (3) block level: insns in the block | |
156 | are actually scheduled. */ | |
157 | \f | |
8c660648 | 158 | #include "config.h" |
5835e573 | 159 | #include "system.h" |
01198c2f | 160 | #include "toplev.h" |
8c660648 JL |
161 | #include "rtl.h" |
162 | #include "basic-block.h" | |
163 | #include "regs.h" | |
49ad7cfa | 164 | #include "function.h" |
8c660648 JL |
165 | #include "hard-reg-set.h" |
166 | #include "flags.h" | |
167 | #include "insn-config.h" | |
168 | #include "insn-attr.h" | |
169 | #include "except.h" | |
487a6e06 | 170 | #include "toplev.h" |
79c9824e | 171 | #include "recog.h" |
8c660648 JL |
172 | |
173 | extern char *reg_known_equiv_p; | |
174 | extern rtx *reg_known_value; | |
175 | ||
176 | #ifdef INSN_SCHEDULING | |
177 | ||
8c660648 JL |
178 | /* target_units bitmask has 1 for each unit in the cpu. It should be |
179 | possible to compute this variable from the machine description. | |
63de6c74 | 180 | But currently it is computed by examining the insn list. Since |
8c660648 JL |
181 | this is only needed for visualization, it seems an acceptable |
182 | solution. (For understanding the mapping of bits to units, see | |
63de6c74 | 183 | definition of function_units[] in "insn-attrtab.c".) */ |
8c660648 | 184 | |
61822835 | 185 | static int target_units = 0; |
8c660648 JL |
186 | |
187 | /* issue_rate is the number of insns that can be scheduled in the same | |
188 | machine cycle. It can be defined in the config/mach/mach.h file, | |
189 | otherwise we set it to 1. */ | |
190 | ||
191 | static int issue_rate; | |
192 | ||
62d65906 JL |
193 | #ifndef ISSUE_RATE |
194 | #define ISSUE_RATE 1 | |
8c660648 JL |
195 | #endif |
196 | ||
cc132865 | 197 | /* sched-verbose controls the amount of debugging output the |
8c660648 JL |
198 | scheduler prints. It is controlled by -fsched-verbose-N: |
199 | N>0 and no -DSR : the output is directed to stderr. | |
200 | N>=10 will direct the printouts to stderr (regardless of -dSR). | |
201 | N=1: same as -dSR. | |
202 | N=2: bb's probabilities, detailed ready list info, unit/insn info. | |
203 | N=3: rtl at abort point, control-flow, regions info. | |
cc132865 | 204 | N=5: dependences info. */ |
8c660648 JL |
205 | |
206 | #define MAX_RGN_BLOCKS 10 | |
207 | #define MAX_RGN_INSNS 100 | |
208 | ||
8c660648 JL |
209 | static int sched_verbose_param = 0; |
210 | static int sched_verbose = 0; | |
8c660648 | 211 | |
63de6c74 | 212 | /* nr_inter/spec counts interblock/speculative motion for the function. */ |
8c660648 JL |
213 | static int nr_inter, nr_spec; |
214 | ||
215 | ||
63de6c74 | 216 | /* Debugging file. All printouts are sent to dump, which is always set, |
8c660648 JL |
217 | either to stderr, or to the dump listing file (-dRS). */ |
218 | static FILE *dump = 0; | |
219 | ||
220 | /* fix_sched_param() is called from toplev.c upon detection | |
221 | of the -fsched-***-N options. */ | |
222 | ||
223 | void | |
224 | fix_sched_param (param, val) | |
5f06c983 | 225 | const char *param, *val; |
8c660648 | 226 | { |
cc132865 | 227 | if (!strcmp (param, "verbose")) |
8c660648 | 228 | sched_verbose_param = atoi (val); |
8c660648 JL |
229 | else |
230 | warning ("fix_sched_param: unknown param: %s", param); | |
231 | } | |
232 | ||
233 | ||
234 | /* Arrays set up by scheduling for the same respective purposes as | |
235 | similar-named arrays set up by flow analysis. We work with these | |
236 | arrays during the scheduling pass so we can compare values against | |
237 | unscheduled code. | |
238 | ||
239 | Values of these arrays are copied at the end of this pass into the | |
240 | arrays set up by flow analysis. */ | |
241 | static int *sched_reg_n_calls_crossed; | |
242 | static int *sched_reg_live_length; | |
243 | static int *sched_reg_basic_block; | |
244 | ||
245 | /* We need to know the current block number during the post scheduling | |
246 | update of live register information so that we can also update | |
247 | REG_BASIC_BLOCK if a register changes blocks. */ | |
248 | static int current_block_num; | |
249 | ||
250 | /* Element N is the next insn that sets (hard or pseudo) register | |
251 | N within the current basic block; or zero, if there is no | |
252 | such insn. Needed for new registers which may be introduced | |
253 | by splitting insns. */ | |
254 | static rtx *reg_last_uses; | |
255 | static rtx *reg_last_sets; | |
28c95eff | 256 | static rtx *reg_last_clobbers; |
8c660648 | 257 | static regset reg_pending_sets; |
28c95eff | 258 | static regset reg_pending_clobbers; |
8c660648 JL |
259 | static int reg_pending_sets_all; |
260 | ||
261 | /* Vector indexed by INSN_UID giving the original ordering of the insns. */ | |
262 | static int *insn_luid; | |
263 | #define INSN_LUID(INSN) (insn_luid[INSN_UID (INSN)]) | |
264 | ||
265 | /* Vector indexed by INSN_UID giving each instruction a priority. */ | |
266 | static int *insn_priority; | |
267 | #define INSN_PRIORITY(INSN) (insn_priority[INSN_UID (INSN)]) | |
268 | ||
269 | static short *insn_costs; | |
270 | #define INSN_COST(INSN) insn_costs[INSN_UID (INSN)] | |
271 | ||
272 | /* Vector indexed by INSN_UID giving an encoding of the function units | |
273 | used. */ | |
274 | static short *insn_units; | |
275 | #define INSN_UNIT(INSN) insn_units[INSN_UID (INSN)] | |
276 | ||
63de6c74 MH |
277 | /* Vector indexed by INSN_UID giving each instruction a |
278 | register-weight. This weight is an estimation of the insn | |
279 | contribution to registers pressure. */ | |
8c660648 JL |
280 | static int *insn_reg_weight; |
281 | #define INSN_REG_WEIGHT(INSN) (insn_reg_weight[INSN_UID (INSN)]) | |
282 | ||
283 | /* Vector indexed by INSN_UID giving list of insns which | |
284 | depend upon INSN. Unlike LOG_LINKS, it represents forward dependences. */ | |
285 | static rtx *insn_depend; | |
286 | #define INSN_DEPEND(INSN) insn_depend[INSN_UID (INSN)] | |
287 | ||
288 | /* Vector indexed by INSN_UID. Initialized to the number of incoming | |
289 | edges in forward dependence graph (= number of LOG_LINKS). As | |
290 | scheduling procedes, dependence counts are decreased. An | |
291 | instruction moves to the ready list when its counter is zero. */ | |
292 | static int *insn_dep_count; | |
293 | #define INSN_DEP_COUNT(INSN) (insn_dep_count[INSN_UID (INSN)]) | |
294 | ||
295 | /* Vector indexed by INSN_UID giving an encoding of the blockage range | |
296 | function. The unit and the range are encoded. */ | |
297 | static unsigned int *insn_blockage; | |
298 | #define INSN_BLOCKAGE(INSN) insn_blockage[INSN_UID (INSN)] | |
299 | #define UNIT_BITS 5 | |
300 | #define BLOCKAGE_MASK ((1 << BLOCKAGE_BITS) - 1) | |
301 | #define ENCODE_BLOCKAGE(U, R) \ | |
f4b94256 | 302 | (((U) << BLOCKAGE_BITS \ |
8c660648 | 303 | | MIN_BLOCKAGE_COST (R)) << BLOCKAGE_BITS \ |
f4b94256 | 304 | | MAX_BLOCKAGE_COST (R)) |
8c660648 JL |
305 | #define UNIT_BLOCKED(B) ((B) >> (2 * BLOCKAGE_BITS)) |
306 | #define BLOCKAGE_RANGE(B) \ | |
307 | (((((B) >> BLOCKAGE_BITS) & BLOCKAGE_MASK) << (HOST_BITS_PER_INT / 2)) \ | |
5835e573 | 308 | | ((B) & BLOCKAGE_MASK)) |
8c660648 JL |
309 | |
310 | /* Encodings of the `<name>_unit_blockage_range' function. */ | |
311 | #define MIN_BLOCKAGE_COST(R) ((R) >> (HOST_BITS_PER_INT / 2)) | |
312 | #define MAX_BLOCKAGE_COST(R) ((R) & ((1 << (HOST_BITS_PER_INT / 2)) - 1)) | |
313 | ||
314 | #define DONE_PRIORITY -1 | |
315 | #define MAX_PRIORITY 0x7fffffff | |
316 | #define TAIL_PRIORITY 0x7ffffffe | |
317 | #define LAUNCH_PRIORITY 0x7f000001 | |
318 | #define DONE_PRIORITY_P(INSN) (INSN_PRIORITY (INSN) < 0) | |
319 | #define LOW_PRIORITY_P(INSN) ((INSN_PRIORITY (INSN) & 0x7f000000) == 0) | |
320 | ||
63de6c74 MH |
321 | /* Vector indexed by INSN_UID giving number of insns referring to this |
322 | insn. */ | |
8c660648 JL |
323 | static int *insn_ref_count; |
324 | #define INSN_REF_COUNT(INSN) (insn_ref_count[INSN_UID (INSN)]) | |
325 | ||
326 | /* Vector indexed by INSN_UID giving line-number note in effect for each | |
327 | insn. For line-number notes, this indicates whether the note may be | |
328 | reused. */ | |
329 | static rtx *line_note; | |
330 | #define LINE_NOTE(INSN) (line_note[INSN_UID (INSN)]) | |
331 | ||
332 | /* Vector indexed by basic block number giving the starting line-number | |
333 | for each basic block. */ | |
334 | static rtx *line_note_head; | |
335 | ||
336 | /* List of important notes we must keep around. This is a pointer to the | |
337 | last element in the list. */ | |
338 | static rtx note_list; | |
339 | ||
340 | /* Regsets telling whether a given register is live or dead before the last | |
341 | scheduled insn. Must scan the instructions once before scheduling to | |
342 | determine what registers are live or dead at the end of the block. */ | |
343 | static regset bb_live_regs; | |
344 | ||
345 | /* Regset telling whether a given register is live after the insn currently | |
346 | being scheduled. Before processing an insn, this is equal to bb_live_regs | |
347 | above. This is used so that we can find registers that are newly born/dead | |
348 | after processing an insn. */ | |
349 | static regset old_live_regs; | |
350 | ||
351 | /* The chain of REG_DEAD notes. REG_DEAD notes are removed from all insns | |
352 | during the initial scan and reused later. If there are not exactly as | |
353 | many REG_DEAD notes in the post scheduled code as there were in the | |
354 | prescheduled code then we trigger an abort because this indicates a bug. */ | |
355 | static rtx dead_notes; | |
356 | ||
357 | /* Queues, etc. */ | |
358 | ||
359 | /* An instruction is ready to be scheduled when all insns preceding it | |
360 | have already been scheduled. It is important to ensure that all | |
361 | insns which use its result will not be executed until its result | |
362 | has been computed. An insn is maintained in one of four structures: | |
363 | ||
364 | (P) the "Pending" set of insns which cannot be scheduled until | |
365 | their dependencies have been satisfied. | |
366 | (Q) the "Queued" set of insns that can be scheduled when sufficient | |
367 | time has passed. | |
368 | (R) the "Ready" list of unscheduled, uncommitted insns. | |
369 | (S) the "Scheduled" list of insns. | |
370 | ||
371 | Initially, all insns are either "Pending" or "Ready" depending on | |
372 | whether their dependencies are satisfied. | |
373 | ||
374 | Insns move from the "Ready" list to the "Scheduled" list as they | |
375 | are committed to the schedule. As this occurs, the insns in the | |
376 | "Pending" list have their dependencies satisfied and move to either | |
377 | the "Ready" list or the "Queued" set depending on whether | |
378 | sufficient time has passed to make them ready. As time passes, | |
379 | insns move from the "Queued" set to the "Ready" list. Insns may | |
380 | move from the "Ready" list to the "Queued" set if they are blocked | |
381 | due to a function unit conflict. | |
382 | ||
383 | The "Pending" list (P) are the insns in the INSN_DEPEND of the unscheduled | |
384 | insns, i.e., those that are ready, queued, and pending. | |
385 | The "Queued" set (Q) is implemented by the variable `insn_queue'. | |
386 | The "Ready" list (R) is implemented by the variables `ready' and | |
387 | `n_ready'. | |
388 | The "Scheduled" list (S) is the new insn chain built by this pass. | |
389 | ||
390 | The transition (R->S) is implemented in the scheduling loop in | |
391 | `schedule_block' when the best insn to schedule is chosen. | |
392 | The transition (R->Q) is implemented in `queue_insn' when an | |
38e01259 | 393 | insn is found to have a function unit conflict with the already |
8c660648 JL |
394 | committed insns. |
395 | The transitions (P->R and P->Q) are implemented in `schedule_insn' as | |
396 | insns move from the ready list to the scheduled list. | |
397 | The transition (Q->R) is implemented in 'queue_to_insn' as time | |
398 | passes or stalls are introduced. */ | |
399 | ||
400 | /* Implement a circular buffer to delay instructions until sufficient | |
401 | time has passed. INSN_QUEUE_SIZE is a power of two larger than | |
402 | MAX_BLOCKAGE and MAX_READY_COST computed by genattr.c. This is the | |
403 | longest time an isnsn may be queued. */ | |
404 | static rtx insn_queue[INSN_QUEUE_SIZE]; | |
405 | static int q_ptr = 0; | |
406 | static int q_size = 0; | |
407 | #define NEXT_Q(X) (((X)+1) & (INSN_QUEUE_SIZE-1)) | |
408 | #define NEXT_Q_AFTER(X, C) (((X)+C) & (INSN_QUEUE_SIZE-1)) | |
409 | ||
410 | /* Vector indexed by INSN_UID giving the minimum clock tick at which | |
411 | the insn becomes ready. This is used to note timing constraints for | |
412 | insns in the pending list. */ | |
413 | static int *insn_tick; | |
414 | #define INSN_TICK(INSN) (insn_tick[INSN_UID (INSN)]) | |
415 | ||
416 | /* Data structure for keeping track of register information | |
417 | during that register's life. */ | |
418 | ||
419 | struct sometimes | |
420 | { | |
421 | int regno; | |
422 | int live_length; | |
423 | int calls_crossed; | |
424 | }; | |
425 | ||
426 | /* Forward declarations. */ | |
427 | static void add_dependence PROTO ((rtx, rtx, enum reg_note)); | |
428 | static void remove_dependence PROTO ((rtx, rtx)); | |
429 | static rtx find_insn_list PROTO ((rtx, rtx)); | |
430 | static int insn_unit PROTO ((rtx)); | |
431 | static unsigned int blockage_range PROTO ((int, rtx)); | |
432 | static void clear_units PROTO ((void)); | |
433 | static int actual_hazard_this_instance PROTO ((int, int, rtx, int, int)); | |
434 | static void schedule_unit PROTO ((int, rtx, int)); | |
435 | static int actual_hazard PROTO ((int, rtx, int, int)); | |
436 | static int potential_hazard PROTO ((int, rtx, int)); | |
437 | static int insn_cost PROTO ((rtx, rtx, rtx)); | |
438 | static int priority PROTO ((rtx)); | |
439 | static void free_pending_lists PROTO ((void)); | |
440 | static void add_insn_mem_dependence PROTO ((rtx *, rtx *, rtx, rtx)); | |
441 | static void flush_pending_lists PROTO ((rtx, int)); | |
442 | static void sched_analyze_1 PROTO ((rtx, rtx)); | |
443 | static void sched_analyze_2 PROTO ((rtx, rtx)); | |
444 | static void sched_analyze_insn PROTO ((rtx, rtx, rtx)); | |
445 | static void sched_analyze PROTO ((rtx, rtx)); | |
5835e573 | 446 | static void sched_note_set PROTO ((rtx, int)); |
e1b6684c | 447 | static int rank_for_schedule PROTO ((const PTR, const PTR)); |
8c660648 JL |
448 | static void swap_sort PROTO ((rtx *, int)); |
449 | static void queue_insn PROTO ((rtx, int)); | |
450 | static int schedule_insn PROTO ((rtx, rtx *, int, int)); | |
451 | static void create_reg_dead_note PROTO ((rtx, rtx)); | |
452 | static void attach_deaths PROTO ((rtx, rtx, int)); | |
453 | static void attach_deaths_insn PROTO ((rtx)); | |
454 | static int new_sometimes_live PROTO ((struct sometimes *, int, int)); | |
455 | static void finish_sometimes_live PROTO ((struct sometimes *, int)); | |
5835e573 | 456 | static int schedule_block PROTO ((int, int)); |
5f06c983 | 457 | static char *safe_concat PROTO ((char *, char *, const char *)); |
cc4fe0e2 L |
458 | static int insn_issue_delay PROTO ((rtx)); |
459 | static int birthing_insn_p PROTO ((rtx)); | |
460 | static void adjust_priority PROTO ((rtx)); | |
8c660648 JL |
461 | |
462 | /* Mapping of insns to their original block prior to scheduling. */ | |
463 | static int *insn_orig_block; | |
464 | #define INSN_BLOCK(insn) (insn_orig_block[INSN_UID (insn)]) | |
465 | ||
466 | /* Some insns (e.g. call) are not allowed to move across blocks. */ | |
467 | static char *cant_move; | |
468 | #define CANT_MOVE(insn) (cant_move[INSN_UID (insn)]) | |
469 | ||
470 | /* Control flow graph edges are kept in circular lists. */ | |
471 | typedef struct | |
472 | { | |
473 | int from_block; | |
474 | int to_block; | |
475 | int next_in; | |
476 | int next_out; | |
477 | } | |
e881bb1b RH |
478 | haifa_edge; |
479 | static haifa_edge *edge_table; | |
8c660648 JL |
480 | |
481 | #define NEXT_IN(edge) (edge_table[edge].next_in) | |
482 | #define NEXT_OUT(edge) (edge_table[edge].next_out) | |
483 | #define FROM_BLOCK(edge) (edge_table[edge].from_block) | |
484 | #define TO_BLOCK(edge) (edge_table[edge].to_block) | |
485 | ||
63de6c74 MH |
486 | /* Number of edges in the control flow graph. (In fact, larger than |
487 | that by 1, since edge 0 is unused.) */ | |
8c660648 JL |
488 | static int nr_edges; |
489 | ||
63de6c74 | 490 | /* Circular list of incoming/outgoing edges of a block. */ |
8c660648 JL |
491 | static int *in_edges; |
492 | static int *out_edges; | |
493 | ||
494 | #define IN_EDGES(block) (in_edges[block]) | |
495 | #define OUT_EDGES(block) (out_edges[block]) | |
496 | ||
8c660648 JL |
497 | |
498 | ||
168cbdf9 | 499 | static int is_cfg_nonregular PROTO ((void)); |
a2e68776 JL |
500 | static int build_control_flow PROTO ((int_list_ptr *, int_list_ptr *, |
501 | int *, int *)); | |
8c660648 JL |
502 | static void new_edge PROTO ((int, int)); |
503 | ||
504 | ||
505 | /* A region is the main entity for interblock scheduling: insns | |
506 | are allowed to move between blocks in the same region, along | |
507 | control flow graph edges, in the 'up' direction. */ | |
508 | typedef struct | |
509 | { | |
63de6c74 MH |
510 | int rgn_nr_blocks; /* Number of blocks in region. */ |
511 | int rgn_blocks; /* cblocks in the region (actually index in rgn_bb_table). */ | |
8c660648 JL |
512 | } |
513 | region; | |
514 | ||
63de6c74 | 515 | /* Number of regions in the procedure. */ |
8c660648 JL |
516 | static int nr_regions; |
517 | ||
63de6c74 | 518 | /* Table of region descriptions. */ |
8c660648 JL |
519 | static region *rgn_table; |
520 | ||
63de6c74 | 521 | /* Array of lists of regions' blocks. */ |
8c660648 JL |
522 | static int *rgn_bb_table; |
523 | ||
524 | /* Topological order of blocks in the region (if b2 is reachable from | |
63de6c74 MH |
525 | b1, block_to_bb[b2] > block_to_bb[b1]). Note: A basic block is |
526 | always referred to by either block or b, while its topological | |
527 | order name (in the region) is refered to by bb. */ | |
8c660648 JL |
528 | static int *block_to_bb; |
529 | ||
530 | /* The number of the region containing a block. */ | |
531 | static int *containing_rgn; | |
532 | ||
533 | #define RGN_NR_BLOCKS(rgn) (rgn_table[rgn].rgn_nr_blocks) | |
534 | #define RGN_BLOCKS(rgn) (rgn_table[rgn].rgn_blocks) | |
535 | #define BLOCK_TO_BB(block) (block_to_bb[block]) | |
536 | #define CONTAINING_RGN(block) (containing_rgn[block]) | |
537 | ||
538 | void debug_regions PROTO ((void)); | |
539 | static void find_single_block_region PROTO ((void)); | |
a2e68776 JL |
540 | static void find_rgns PROTO ((int_list_ptr *, int_list_ptr *, |
541 | int *, int *, sbitmap *)); | |
8c660648 JL |
542 | static int too_large PROTO ((int, int *, int *)); |
543 | ||
544 | extern void debug_live PROTO ((int, int)); | |
545 | ||
546 | /* Blocks of the current region being scheduled. */ | |
547 | static int current_nr_blocks; | |
548 | static int current_blocks; | |
549 | ||
63de6c74 | 550 | /* The mapping from bb to block. */ |
8c660648 JL |
551 | #define BB_TO_BLOCK(bb) (rgn_bb_table[current_blocks + (bb)]) |
552 | ||
553 | ||
554 | /* Bit vectors and bitset operations are needed for computations on | |
555 | the control flow graph. */ | |
556 | ||
557 | typedef unsigned HOST_WIDE_INT *bitset; | |
558 | typedef struct | |
559 | { | |
63de6c74 MH |
560 | int *first_member; /* Pointer to the list start in bitlst_table. */ |
561 | int nr_members; /* The number of members of the bit list. */ | |
8c660648 JL |
562 | } |
563 | bitlst; | |
564 | ||
61822835 JL |
565 | static int bitlst_table_last; |
566 | static int bitlst_table_size; | |
8c660648 JL |
567 | static int *bitlst_table; |
568 | ||
569 | static char bitset_member PROTO ((bitset, int, int)); | |
570 | static void extract_bitlst PROTO ((bitset, int, bitlst *)); | |
571 | ||
63de6c74 | 572 | /* Target info declarations. |
8c660648 JL |
573 | |
574 | The block currently being scheduled is referred to as the "target" block, | |
575 | while other blocks in the region from which insns can be moved to the | |
576 | target are called "source" blocks. The candidate structure holds info | |
577 | about such sources: are they valid? Speculative? Etc. */ | |
578 | typedef bitlst bblst; | |
579 | typedef struct | |
580 | { | |
581 | char is_valid; | |
582 | char is_speculative; | |
583 | int src_prob; | |
584 | bblst split_bbs; | |
585 | bblst update_bbs; | |
586 | } | |
587 | candidate; | |
588 | ||
589 | static candidate *candidate_table; | |
590 | ||
591 | /* A speculative motion requires checking live information on the path | |
592 | from 'source' to 'target'. The split blocks are those to be checked. | |
593 | After a speculative motion, live information should be modified in | |
594 | the 'update' blocks. | |
595 | ||
63de6c74 MH |
596 | Lists of split and update blocks for each candidate of the current |
597 | target are in array bblst_table. */ | |
61822835 | 598 | static int *bblst_table, bblst_size, bblst_last; |
8c660648 JL |
599 | |
600 | #define IS_VALID(src) ( candidate_table[src].is_valid ) | |
601 | #define IS_SPECULATIVE(src) ( candidate_table[src].is_speculative ) | |
602 | #define SRC_PROB(src) ( candidate_table[src].src_prob ) | |
603 | ||
604 | /* The bb being currently scheduled. */ | |
61822835 | 605 | static int target_bb; |
8c660648 JL |
606 | |
607 | /* List of edges. */ | |
608 | typedef bitlst edgelst; | |
609 | ||
63de6c74 | 610 | /* Target info functions. */ |
8c660648 JL |
611 | static void split_edges PROTO ((int, int, edgelst *)); |
612 | static void compute_trg_info PROTO ((int)); | |
613 | void debug_candidate PROTO ((int)); | |
614 | void debug_candidates PROTO ((int)); | |
615 | ||
616 | ||
617 | /* Bit-set of bbs, where bit 'i' stands for bb 'i'. */ | |
618 | typedef bitset bbset; | |
619 | ||
620 | /* Number of words of the bbset. */ | |
61822835 | 621 | static int bbset_size; |
8c660648 JL |
622 | |
623 | /* Dominators array: dom[i] contains the bbset of dominators of | |
624 | bb i in the region. */ | |
61822835 | 625 | static bbset *dom; |
8c660648 | 626 | |
63de6c74 | 627 | /* bb 0 is the only region entry. */ |
8c660648 JL |
628 | #define IS_RGN_ENTRY(bb) (!bb) |
629 | ||
630 | /* Is bb_src dominated by bb_trg. */ | |
631 | #define IS_DOMINATED(bb_src, bb_trg) \ | |
632 | ( bitset_member (dom[bb_src], bb_trg, bbset_size) ) | |
633 | ||
634 | /* Probability: Prob[i] is a float in [0, 1] which is the probability | |
635 | of bb i relative to the region entry. */ | |
61822835 | 636 | static float *prob; |
8c660648 | 637 | |
63de6c74 | 638 | /* The probability of bb_src, relative to bb_trg. Note, that while the |
8c660648 JL |
639 | 'prob[bb]' is a float in [0, 1], this macro returns an integer |
640 | in [0, 100]. */ | |
641 | #define GET_SRC_PROB(bb_src, bb_trg) ((int) (100.0 * (prob[bb_src] / \ | |
642 | prob[bb_trg]))) | |
643 | ||
644 | /* Bit-set of edges, where bit i stands for edge i. */ | |
645 | typedef bitset edgeset; | |
646 | ||
647 | /* Number of edges in the region. */ | |
61822835 | 648 | static int rgn_nr_edges; |
8c660648 | 649 | |
63de6c74 | 650 | /* Array of size rgn_nr_edges. */ |
61822835 | 651 | static int *rgn_edges; |
8c660648 | 652 | |
63de6c74 | 653 | /* Number of words in an edgeset. */ |
61822835 | 654 | static int edgeset_size; |
8c660648 JL |
655 | |
656 | /* Mapping from each edge in the graph to its number in the rgn. */ | |
61822835 | 657 | static int *edge_to_bit; |
8c660648 JL |
658 | #define EDGE_TO_BIT(edge) (edge_to_bit[edge]) |
659 | ||
660 | /* The split edges of a source bb is different for each target | |
661 | bb. In order to compute this efficiently, the 'potential-split edges' | |
662 | are computed for each bb prior to scheduling a region. This is actually | |
663 | the split edges of each bb relative to the region entry. | |
664 | ||
665 | pot_split[bb] is the set of potential split edges of bb. */ | |
61822835 | 666 | static edgeset *pot_split; |
8c660648 JL |
667 | |
668 | /* For every bb, a set of its ancestor edges. */ | |
61822835 | 669 | static edgeset *ancestor_edges; |
8c660648 JL |
670 | |
671 | static void compute_dom_prob_ps PROTO ((int)); | |
672 | ||
673 | #define ABS_VALUE(x) (((x)<0)?(-(x)):(x)) | |
674 | #define INSN_PROBABILITY(INSN) (SRC_PROB (BLOCK_TO_BB (INSN_BLOCK (INSN)))) | |
675 | #define IS_SPECULATIVE_INSN(INSN) (IS_SPECULATIVE (BLOCK_TO_BB (INSN_BLOCK (INSN)))) | |
676 | #define INSN_BB(INSN) (BLOCK_TO_BB (INSN_BLOCK (INSN))) | |
677 | ||
63de6c74 | 678 | /* Parameters affecting the decision of rank_for_schedule(). */ |
8c660648 JL |
679 | #define MIN_DIFF_PRIORITY 2 |
680 | #define MIN_PROBABILITY 40 | |
681 | #define MIN_PROB_DIFF 10 | |
682 | ||
63de6c74 | 683 | /* Speculative scheduling functions. */ |
8c660648 JL |
684 | static int check_live_1 PROTO ((int, rtx)); |
685 | static void update_live_1 PROTO ((int, rtx)); | |
5835e573 KG |
686 | static int check_live PROTO ((rtx, int)); |
687 | static void update_live PROTO ((rtx, int)); | |
8c660648 JL |
688 | static void set_spec_fed PROTO ((rtx)); |
689 | static int is_pfree PROTO ((rtx, int, int)); | |
690 | static int find_conditional_protection PROTO ((rtx, int)); | |
691 | static int is_conditionally_protected PROTO ((rtx, int, int)); | |
692 | static int may_trap_exp PROTO ((rtx, int)); | |
ac957f13 | 693 | static int haifa_classify_insn PROTO ((rtx)); |
e009aaf3 | 694 | static int is_prisky PROTO ((rtx, int, int)); |
8c660648 JL |
695 | static int is_exception_free PROTO ((rtx, int, int)); |
696 | ||
697 | static char find_insn_mem_list PROTO ((rtx, rtx, rtx, rtx)); | |
698 | static void compute_block_forward_dependences PROTO ((int)); | |
699 | static void init_rgn_data_dependences PROTO ((int)); | |
700 | static void add_branch_dependences PROTO ((rtx, rtx)); | |
701 | static void compute_block_backward_dependences PROTO ((int)); | |
702 | void debug_dependencies PROTO ((void)); | |
703 | ||
704 | /* Notes handling mechanism: | |
705 | ========================= | |
706 | Generally, NOTES are saved before scheduling and restored after scheduling. | |
707 | The scheduler distinguishes between three types of notes: | |
708 | ||
709 | (1) LINE_NUMBER notes, generated and used for debugging. Here, | |
710 | before scheduling a region, a pointer to the LINE_NUMBER note is | |
711 | added to the insn following it (in save_line_notes()), and the note | |
712 | is removed (in rm_line_notes() and unlink_line_notes()). After | |
713 | scheduling the region, this pointer is used for regeneration of | |
714 | the LINE_NUMBER note (in restore_line_notes()). | |
715 | ||
716 | (2) LOOP_BEGIN, LOOP_END, SETJMP, EHREGION_BEG, EHREGION_END notes: | |
717 | Before scheduling a region, a pointer to the note is added to the insn | |
718 | that follows or precedes it. (This happens as part of the data dependence | |
719 | computation). After scheduling an insn, the pointer contained in it is | |
720 | used for regenerating the corresponding note (in reemit_notes). | |
721 | ||
722 | (3) All other notes (e.g. INSN_DELETED): Before scheduling a block, | |
723 | these notes are put in a list (in rm_other_notes() and | |
724 | unlink_other_notes ()). After scheduling the block, these notes are | |
725 | inserted at the beginning of the block (in schedule_block()). */ | |
726 | ||
727 | static rtx unlink_other_notes PROTO ((rtx, rtx)); | |
728 | static rtx unlink_line_notes PROTO ((rtx, rtx)); | |
729 | static void rm_line_notes PROTO ((int)); | |
730 | static void save_line_notes PROTO ((int)); | |
731 | static void restore_line_notes PROTO ((int)); | |
732 | static void rm_redundant_line_notes PROTO ((void)); | |
733 | static void rm_other_notes PROTO ((rtx, rtx)); | |
734 | static rtx reemit_notes PROTO ((rtx, rtx)); | |
735 | ||
736 | static void get_block_head_tail PROTO ((int, rtx *, rtx *)); | |
737 | ||
738 | static void find_pre_sched_live PROTO ((int)); | |
739 | static void find_post_sched_live PROTO ((int)); | |
740 | static void update_reg_usage PROTO ((void)); | |
c6a754f2 | 741 | static int queue_to_ready PROTO ((rtx [], int)); |
8c660648 | 742 | |
9a8b0889 | 743 | static void debug_ready_list PROTO ((rtx[], int)); |
cc4fe0e2 | 744 | static void init_target_units PROTO ((void)); |
8c660648 | 745 | static void insn_print_units PROTO ((rtx)); |
cc4fe0e2 L |
746 | static int get_visual_tbl_length PROTO ((void)); |
747 | static void init_block_visualization PROTO ((void)); | |
5f06c983 | 748 | static void print_block_visualization PROTO ((int, const char *)); |
8c660648 JL |
749 | static void visualize_scheduled_insns PROTO ((int, int)); |
750 | static void visualize_no_unit PROTO ((rtx)); | |
751 | static void visualize_stall_cycles PROTO ((int, int)); | |
752 | static void print_exp PROTO ((char *, rtx, int)); | |
753 | static void print_value PROTO ((char *, rtx, int)); | |
754 | static void print_pattern PROTO ((char *, rtx, int)); | |
755 | static void print_insn PROTO ((char *, rtx, int)); | |
756 | void debug_reg_vector PROTO ((regset)); | |
757 | ||
758 | static rtx move_insn1 PROTO ((rtx, rtx)); | |
759 | static rtx move_insn PROTO ((rtx, rtx)); | |
760 | static rtx group_leader PROTO ((rtx)); | |
761 | static int set_priorities PROTO ((int)); | |
762 | static void init_rtx_vector PROTO ((rtx **, rtx *, int, int)); | |
763 | static void schedule_region PROTO ((int)); | |
8c660648 JL |
764 | |
765 | #endif /* INSN_SCHEDULING */ | |
766 | \f | |
767 | #define SIZE_FOR_MODE(X) (GET_MODE_SIZE (GET_MODE (X))) | |
768 | ||
8c660648 JL |
769 | /* Add ELEM wrapped in an INSN_LIST with reg note kind DEP_TYPE to the |
770 | LOG_LINKS of INSN, if not already there. DEP_TYPE indicates the type | |
771 | of dependence that this link represents. */ | |
772 | ||
773 | static void | |
774 | add_dependence (insn, elem, dep_type) | |
775 | rtx insn; | |
776 | rtx elem; | |
777 | enum reg_note dep_type; | |
778 | { | |
779 | rtx link, next; | |
780 | ||
781 | /* Don't depend an insn on itself. */ | |
782 | if (insn == elem) | |
783 | return; | |
784 | ||
342d9c89 JL |
785 | /* We can get a dependency on deleted insns due to optimizations in |
786 | the register allocation and reloading or due to splitting. Any | |
787 | such dependency is useless and can be ignored. */ | |
788 | if (GET_CODE (elem) == NOTE) | |
789 | return; | |
790 | ||
8c660648 JL |
791 | /* If elem is part of a sequence that must be scheduled together, then |
792 | make the dependence point to the last insn of the sequence. | |
793 | When HAVE_cc0, it is possible for NOTEs to exist between users and | |
794 | setters of the condition codes, so we must skip past notes here. | |
795 | Otherwise, NOTEs are impossible here. */ | |
796 | ||
797 | next = NEXT_INSN (elem); | |
798 | ||
799 | #ifdef HAVE_cc0 | |
800 | while (next && GET_CODE (next) == NOTE) | |
801 | next = NEXT_INSN (next); | |
802 | #endif | |
803 | ||
804 | if (next && SCHED_GROUP_P (next) | |
805 | && GET_CODE (next) != CODE_LABEL) | |
806 | { | |
807 | /* Notes will never intervene here though, so don't bother checking | |
808 | for them. */ | |
809 | /* We must reject CODE_LABELs, so that we don't get confused by one | |
810 | that has LABEL_PRESERVE_P set, which is represented by the same | |
811 | bit in the rtl as SCHED_GROUP_P. A CODE_LABEL can never be | |
812 | SCHED_GROUP_P. */ | |
813 | while (NEXT_INSN (next) && SCHED_GROUP_P (NEXT_INSN (next)) | |
814 | && GET_CODE (NEXT_INSN (next)) != CODE_LABEL) | |
815 | next = NEXT_INSN (next); | |
816 | ||
817 | /* Again, don't depend an insn on itself. */ | |
818 | if (insn == next) | |
819 | return; | |
820 | ||
821 | /* Make the dependence to NEXT, the last insn of the group, instead | |
822 | of the original ELEM. */ | |
823 | elem = next; | |
824 | } | |
825 | ||
826 | #ifdef INSN_SCHEDULING | |
827 | /* (This code is guarded by INSN_SCHEDULING, otherwise INSN_BB is undefined.) | |
828 | No need for interblock dependences with calls, since | |
829 | calls are not moved between blocks. Note: the edge where | |
830 | elem is a CALL is still required. */ | |
831 | if (GET_CODE (insn) == CALL_INSN | |
832 | && (INSN_BB (elem) != INSN_BB (insn))) | |
833 | return; | |
834 | ||
835 | #endif | |
836 | ||
837 | /* Check that we don't already have this dependence. */ | |
838 | for (link = LOG_LINKS (insn); link; link = XEXP (link, 1)) | |
839 | if (XEXP (link, 0) == elem) | |
840 | { | |
841 | /* If this is a more restrictive type of dependence than the existing | |
842 | one, then change the existing dependence to this type. */ | |
843 | if ((int) dep_type < (int) REG_NOTE_KIND (link)) | |
844 | PUT_REG_NOTE_KIND (link, dep_type); | |
845 | return; | |
846 | } | |
847 | /* Might want to check one level of transitivity to save conses. */ | |
848 | ||
ebb7b10b RH |
849 | link = alloc_INSN_LIST (elem, LOG_LINKS (insn)); |
850 | LOG_LINKS (insn) = link; | |
851 | ||
8c660648 JL |
852 | /* Insn dependency, not data dependency. */ |
853 | PUT_REG_NOTE_KIND (link, dep_type); | |
8c660648 JL |
854 | } |
855 | ||
856 | /* Remove ELEM wrapped in an INSN_LIST from the LOG_LINKS | |
857 | of INSN. Abort if not found. */ | |
858 | ||
859 | static void | |
860 | remove_dependence (insn, elem) | |
861 | rtx insn; | |
862 | rtx elem; | |
863 | { | |
ebb7b10b | 864 | rtx prev, link, next; |
8c660648 JL |
865 | int found = 0; |
866 | ||
ebb7b10b | 867 | for (prev = 0, link = LOG_LINKS (insn); link; link = next) |
8c660648 | 868 | { |
ebb7b10b | 869 | next = XEXP (link, 1); |
8c660648 JL |
870 | if (XEXP (link, 0) == elem) |
871 | { | |
872 | if (prev) | |
ebb7b10b | 873 | XEXP (prev, 1) = next; |
8c660648 | 874 | else |
ebb7b10b | 875 | LOG_LINKS (insn) = next; |
5a4f6418 | 876 | free_INSN_LIST_node (link); |
ebb7b10b | 877 | |
8c660648 JL |
878 | found = 1; |
879 | } | |
6d8ccdbb JL |
880 | else |
881 | prev = link; | |
8c660648 JL |
882 | } |
883 | ||
884 | if (!found) | |
885 | abort (); | |
886 | return; | |
887 | } | |
888 | \f | |
889 | #ifndef INSN_SCHEDULING | |
890 | void | |
891 | schedule_insns (dump_file) | |
892 | FILE *dump_file; | |
893 | { | |
894 | } | |
895 | #else | |
896 | #ifndef __GNUC__ | |
897 | #define __inline | |
898 | #endif | |
899 | ||
cbb13457 MM |
900 | #ifndef HAIFA_INLINE |
901 | #define HAIFA_INLINE __inline | |
902 | #endif | |
903 | ||
8c660648 JL |
904 | /* Computation of memory dependencies. */ |
905 | ||
906 | /* The *_insns and *_mems are paired lists. Each pending memory operation | |
907 | will have a pointer to the MEM rtx on one list and a pointer to the | |
908 | containing insn on the other list in the same place in the list. */ | |
909 | ||
910 | /* We can't use add_dependence like the old code did, because a single insn | |
911 | may have multiple memory accesses, and hence needs to be on the list | |
912 | once for each memory access. Add_dependence won't let you add an insn | |
913 | to a list more than once. */ | |
914 | ||
915 | /* An INSN_LIST containing all insns with pending read operations. */ | |
916 | static rtx pending_read_insns; | |
917 | ||
918 | /* An EXPR_LIST containing all MEM rtx's which are pending reads. */ | |
919 | static rtx pending_read_mems; | |
920 | ||
921 | /* An INSN_LIST containing all insns with pending write operations. */ | |
922 | static rtx pending_write_insns; | |
923 | ||
924 | /* An EXPR_LIST containing all MEM rtx's which are pending writes. */ | |
925 | static rtx pending_write_mems; | |
926 | ||
927 | /* Indicates the combined length of the two pending lists. We must prevent | |
928 | these lists from ever growing too large since the number of dependencies | |
929 | produced is at least O(N*N), and execution time is at least O(4*N*N), as | |
930 | a function of the length of these pending lists. */ | |
931 | ||
932 | static int pending_lists_length; | |
933 | ||
8c660648 JL |
934 | /* The last insn upon which all memory references must depend. |
935 | This is an insn which flushed the pending lists, creating a dependency | |
936 | between it and all previously pending memory references. This creates | |
937 | a barrier (or a checkpoint) which no memory reference is allowed to cross. | |
938 | ||
939 | This includes all non constant CALL_INSNs. When we do interprocedural | |
940 | alias analysis, this restriction can be relaxed. | |
941 | This may also be an INSN that writes memory if the pending lists grow | |
942 | too large. */ | |
943 | ||
944 | static rtx last_pending_memory_flush; | |
945 | ||
946 | /* The last function call we have seen. All hard regs, and, of course, | |
947 | the last function call, must depend on this. */ | |
948 | ||
949 | static rtx last_function_call; | |
950 | ||
951 | /* The LOG_LINKS field of this is a list of insns which use a pseudo register | |
952 | that does not already cross a call. We create dependencies between each | |
953 | of those insn and the next call insn, to ensure that they won't cross a call | |
954 | after scheduling is done. */ | |
955 | ||
956 | static rtx sched_before_next_call; | |
957 | ||
958 | /* Pointer to the last instruction scheduled. Used by rank_for_schedule, | |
959 | so that insns independent of the last scheduled insn will be preferred | |
960 | over dependent instructions. */ | |
961 | ||
962 | static rtx last_scheduled_insn; | |
963 | ||
964 | /* Data structures for the computation of data dependences in a regions. We | |
965 | keep one copy of each of the declared above variables for each bb in the | |
966 | region. Before analyzing the data dependences for a bb, its variables | |
967 | are initialized as a function of the variables of its predecessors. When | |
968 | the analysis for a bb completes, we save the contents of each variable X | |
969 | to a corresponding bb_X[bb] variable. For example, pending_read_insns is | |
970 | copied to bb_pending_read_insns[bb]. Another change is that few | |
971 | variables are now a list of insns rather than a single insn: | |
972 | last_pending_memory_flash, last_function_call, reg_last_sets. The | |
973 | manipulation of these variables was changed appropriately. */ | |
974 | ||
975 | static rtx **bb_reg_last_uses; | |
976 | static rtx **bb_reg_last_sets; | |
28c95eff | 977 | static rtx **bb_reg_last_clobbers; |
8c660648 JL |
978 | |
979 | static rtx *bb_pending_read_insns; | |
980 | static rtx *bb_pending_read_mems; | |
981 | static rtx *bb_pending_write_insns; | |
982 | static rtx *bb_pending_write_mems; | |
983 | static int *bb_pending_lists_length; | |
984 | ||
985 | static rtx *bb_last_pending_memory_flush; | |
986 | static rtx *bb_last_function_call; | |
987 | static rtx *bb_sched_before_next_call; | |
988 | ||
63de6c74 | 989 | /* Functions for construction of the control flow graph. */ |
8c660648 JL |
990 | |
991 | /* Return 1 if control flow graph should not be constructed, 0 otherwise. | |
168cbdf9 | 992 | |
8c660648 | 993 | We decide not to build the control flow graph if there is possibly more |
168cbdf9 JL |
994 | than one entry to the function, if computed branches exist, of if we |
995 | have nonlocal gotos. */ | |
8c660648 | 996 | |
168cbdf9 | 997 | static int |
8c660648 JL |
998 | is_cfg_nonregular () |
999 | { | |
1000 | int b; | |
1001 | rtx insn; | |
1002 | RTX_CODE code; | |
1003 | ||
168cbdf9 JL |
1004 | /* If we have a label that could be the target of a nonlocal goto, then |
1005 | the cfg is not well structured. */ | |
e881bb1b | 1006 | if (nonlocal_goto_handler_labels) |
168cbdf9 | 1007 | return 1; |
8c660648 | 1008 | |
168cbdf9 | 1009 | /* If we have any forced labels, then the cfg is not well structured. */ |
8c660648 | 1010 | if (forced_labels) |
168cbdf9 | 1011 | return 1; |
8c660648 | 1012 | |
4d1d8045 BS |
1013 | /* If this function has a computed jump, then we consider the cfg |
1014 | not well structured. */ | |
1015 | if (current_function_has_computed_jump) | |
1016 | return 1; | |
1017 | ||
168cbdf9 JL |
1018 | /* If we have exception handlers, then we consider the cfg not well |
1019 | structured. ?!? We should be able to handle this now that flow.c | |
1020 | computes an accurate cfg for EH. */ | |
8c660648 | 1021 | if (exception_handler_labels) |
168cbdf9 | 1022 | return 1; |
8c660648 | 1023 | |
168cbdf9 JL |
1024 | /* If we have non-jumping insns which refer to labels, then we consider |
1025 | the cfg not well structured. */ | |
63de6c74 | 1026 | /* Check for labels referred to other thn by jumps. */ |
8c660648 | 1027 | for (b = 0; b < n_basic_blocks; b++) |
3b413743 | 1028 | for (insn = BLOCK_HEAD (b);; insn = NEXT_INSN (insn)) |
8c660648 JL |
1029 | { |
1030 | code = GET_CODE (insn); | |
1031 | if (GET_RTX_CLASS (code) == 'i') | |
1032 | { | |
1033 | rtx note; | |
1034 | ||
1035 | for (note = REG_NOTES (insn); note; note = XEXP (note, 1)) | |
1036 | if (REG_NOTE_KIND (note) == REG_LABEL) | |
168cbdf9 | 1037 | return 1; |
8c660648 JL |
1038 | } |
1039 | ||
3b413743 | 1040 | if (insn == BLOCK_END (b)) |
8c660648 JL |
1041 | break; |
1042 | } | |
1043 | ||
168cbdf9 | 1044 | /* All the tests passed. Consider the cfg well structured. */ |
8c660648 JL |
1045 | return 0; |
1046 | } | |
1047 | ||
5ece9746 JL |
1048 | /* Build the control flow graph and set nr_edges. |
1049 | ||
1050 | Instead of trying to build a cfg ourselves, we rely on flow to | |
168cbdf9 | 1051 | do it for us. Stamp out useless code (and bug) duplication. |
8c660648 | 1052 | |
168cbdf9 JL |
1053 | Return nonzero if an irregularity in the cfg is found which would |
1054 | prevent cross block scheduling. */ | |
1055 | ||
1056 | static int | |
a2e68776 JL |
1057 | build_control_flow (s_preds, s_succs, num_preds, num_succs) |
1058 | int_list_ptr *s_preds; | |
1059 | int_list_ptr *s_succs; | |
1060 | int *num_preds; | |
1061 | int *num_succs; | |
8c660648 | 1062 | { |
081f5e7e | 1063 | int i; |
5ece9746 | 1064 | int_list_ptr succ; |
168cbdf9 | 1065 | int unreachable; |
5ece9746 | 1066 | |
168cbdf9 JL |
1067 | /* Count the number of edges in the cfg. */ |
1068 | nr_edges = 0; | |
1069 | unreachable = 0; | |
1070 | for (i = 0; i < n_basic_blocks; i++) | |
1071 | { | |
1072 | nr_edges += num_succs[i]; | |
15ebe47d JL |
1073 | |
1074 | /* Unreachable loops with more than one basic block are detected | |
1075 | during the DFS traversal in find_rgns. | |
1076 | ||
1077 | Unreachable loops with a single block are detected here. This | |
1078 | test is redundant with the one in find_rgns, but it's much | |
1079 | cheaper to go ahead and catch the trivial case here. */ | |
a8afd67b JW |
1080 | if (num_preds[i] == 0 |
1081 | || (num_preds[i] == 1 && INT_LIST_VAL (s_preds[i]) == i)) | |
168cbdf9 JL |
1082 | unreachable = 1; |
1083 | } | |
1084 | ||
1085 | /* Account for entry/exit edges. */ | |
1086 | nr_edges += 2; | |
1087 | ||
3de90026 RH |
1088 | in_edges = (int *) xcalloc (n_basic_blocks, sizeof (int)); |
1089 | out_edges = (int *) xcalloc (n_basic_blocks, sizeof (int)); | |
1090 | edge_table = (haifa_edge *) xcalloc (nr_edges, sizeof (haifa_edge)); | |
168cbdf9 | 1091 | |
8c660648 JL |
1092 | nr_edges = 0; |
1093 | for (i = 0; i < n_basic_blocks; i++) | |
5ece9746 JL |
1094 | for (succ = s_succs[i]; succ; succ = succ->next) |
1095 | { | |
1096 | if (INT_LIST_VAL (succ) != EXIT_BLOCK) | |
1097 | new_edge (i, INT_LIST_VAL (succ)); | |
1098 | } | |
8c660648 | 1099 | |
63de6c74 | 1100 | /* Increment by 1, since edge 0 is unused. */ |
8c660648 JL |
1101 | nr_edges++; |
1102 | ||
168cbdf9 | 1103 | return unreachable; |
8c660648 JL |
1104 | } |
1105 | ||
1106 | ||
5ece9746 | 1107 | /* Record an edge in the control flow graph from SOURCE to TARGET. |
8c660648 | 1108 | |
5ece9746 JL |
1109 | In theory, this is redundant with the s_succs computed above, but |
1110 | we have not converted all of haifa to use information from the | |
1111 | integer lists. */ | |
8c660648 JL |
1112 | |
1113 | static void | |
1114 | new_edge (source, target) | |
1115 | int source, target; | |
1116 | { | |
1117 | int e, next_edge; | |
1118 | int curr_edge, fst_edge; | |
1119 | ||
63de6c74 | 1120 | /* Check for duplicates. */ |
8c660648 JL |
1121 | fst_edge = curr_edge = OUT_EDGES (source); |
1122 | while (curr_edge) | |
1123 | { | |
1124 | if (FROM_BLOCK (curr_edge) == source | |
1125 | && TO_BLOCK (curr_edge) == target) | |
1126 | { | |
1127 | return; | |
1128 | } | |
1129 | ||
1130 | curr_edge = NEXT_OUT (curr_edge); | |
1131 | ||
1132 | if (fst_edge == curr_edge) | |
1133 | break; | |
1134 | } | |
1135 | ||
1136 | e = ++nr_edges; | |
1137 | ||
1138 | FROM_BLOCK (e) = source; | |
1139 | TO_BLOCK (e) = target; | |
1140 | ||
1141 | if (OUT_EDGES (source)) | |
1142 | { | |
1143 | next_edge = NEXT_OUT (OUT_EDGES (source)); | |
1144 | NEXT_OUT (OUT_EDGES (source)) = e; | |
1145 | NEXT_OUT (e) = next_edge; | |
1146 | } | |
1147 | else | |
1148 | { | |
1149 | OUT_EDGES (source) = e; | |
1150 | NEXT_OUT (e) = e; | |
1151 | } | |
1152 | ||
1153 | if (IN_EDGES (target)) | |
1154 | { | |
1155 | next_edge = NEXT_IN (IN_EDGES (target)); | |
1156 | NEXT_IN (IN_EDGES (target)) = e; | |
1157 | NEXT_IN (e) = next_edge; | |
1158 | } | |
1159 | else | |
1160 | { | |
1161 | IN_EDGES (target) = e; | |
1162 | NEXT_IN (e) = e; | |
1163 | } | |
1164 | } | |
1165 | ||
1166 | ||
1167 | /* BITSET macros for operations on the control flow graph. */ | |
1168 | ||
63de6c74 | 1169 | /* Compute bitwise union of two bitsets. */ |
8c660648 JL |
1170 | #define BITSET_UNION(set1, set2, len) \ |
1171 | do { register bitset tp = set1, sp = set2; \ | |
1172 | register int i; \ | |
1173 | for (i = 0; i < len; i++) \ | |
1174 | *(tp++) |= *(sp++); } while (0) | |
1175 | ||
63de6c74 | 1176 | /* Compute bitwise intersection of two bitsets. */ |
8c660648 JL |
1177 | #define BITSET_INTER(set1, set2, len) \ |
1178 | do { register bitset tp = set1, sp = set2; \ | |
1179 | register int i; \ | |
1180 | for (i = 0; i < len; i++) \ | |
1181 | *(tp++) &= *(sp++); } while (0) | |
1182 | ||
63de6c74 | 1183 | /* Compute bitwise difference of two bitsets. */ |
8c660648 JL |
1184 | #define BITSET_DIFFER(set1, set2, len) \ |
1185 | do { register bitset tp = set1, sp = set2; \ | |
1186 | register int i; \ | |
1187 | for (i = 0; i < len; i++) \ | |
1188 | *(tp++) &= ~*(sp++); } while (0) | |
1189 | ||
63de6c74 | 1190 | /* Inverts every bit of bitset 'set'. */ |
8c660648 JL |
1191 | #define BITSET_INVERT(set, len) \ |
1192 | do { register bitset tmpset = set; \ | |
1193 | register int i; \ | |
1194 | for (i = 0; i < len; i++, tmpset++) \ | |
1195 | *tmpset = ~*tmpset; } while (0) | |
1196 | ||
1197 | /* Turn on the index'th bit in bitset set. */ | |
1198 | #define BITSET_ADD(set, index, len) \ | |
1199 | { \ | |
1200 | if (index >= HOST_BITS_PER_WIDE_INT * len) \ | |
1201 | abort (); \ | |
1202 | else \ | |
1203 | set[index/HOST_BITS_PER_WIDE_INT] |= \ | |
1204 | 1 << (index % HOST_BITS_PER_WIDE_INT); \ | |
1205 | } | |
1206 | ||
1207 | /* Turn off the index'th bit in set. */ | |
1208 | #define BITSET_REMOVE(set, index, len) \ | |
1209 | { \ | |
1210 | if (index >= HOST_BITS_PER_WIDE_INT * len) \ | |
1211 | abort (); \ | |
1212 | else \ | |
1213 | set[index/HOST_BITS_PER_WIDE_INT] &= \ | |
1214 | ~(1 << (index%HOST_BITS_PER_WIDE_INT)); \ | |
1215 | } | |
1216 | ||
1217 | ||
63de6c74 | 1218 | /* Check if the index'th bit in bitset set is on. */ |
8c660648 JL |
1219 | |
1220 | static char | |
1221 | bitset_member (set, index, len) | |
1222 | bitset set; | |
1223 | int index, len; | |
1224 | { | |
1225 | if (index >= HOST_BITS_PER_WIDE_INT * len) | |
1226 | abort (); | |
1227 | return (set[index / HOST_BITS_PER_WIDE_INT] & | |
1228 | 1 << (index % HOST_BITS_PER_WIDE_INT)) ? 1 : 0; | |
1229 | } | |
1230 | ||
1231 | ||
1232 | /* Translate a bit-set SET to a list BL of the bit-set members. */ | |
1233 | ||
1234 | static void | |
1235 | extract_bitlst (set, len, bl) | |
1236 | bitset set; | |
1237 | int len; | |
1238 | bitlst *bl; | |
1239 | { | |
1240 | int i, j, offset; | |
1241 | unsigned HOST_WIDE_INT word; | |
1242 | ||
63de6c74 | 1243 | /* bblst table space is reused in each call to extract_bitlst. */ |
8c660648 JL |
1244 | bitlst_table_last = 0; |
1245 | ||
1246 | bl->first_member = &bitlst_table[bitlst_table_last]; | |
1247 | bl->nr_members = 0; | |
1248 | ||
1249 | for (i = 0; i < len; i++) | |
1250 | { | |
1251 | word = set[i]; | |
1252 | offset = i * HOST_BITS_PER_WIDE_INT; | |
1253 | for (j = 0; word; j++) | |
1254 | { | |
1255 | if (word & 1) | |
1256 | { | |
1257 | bitlst_table[bitlst_table_last++] = offset; | |
1258 | (bl->nr_members)++; | |
1259 | } | |
1260 | word >>= 1; | |
1261 | ++offset; | |
1262 | } | |
1263 | } | |
1264 | ||
1265 | } | |
1266 | ||
1267 | ||
63de6c74 | 1268 | /* Functions for the construction of regions. */ |
8c660648 JL |
1269 | |
1270 | /* Print the regions, for debugging purposes. Callable from debugger. */ | |
1271 | ||
1272 | void | |
1273 | debug_regions () | |
1274 | { | |
1275 | int rgn, bb; | |
1276 | ||
1277 | fprintf (dump, "\n;; ------------ REGIONS ----------\n\n"); | |
1278 | for (rgn = 0; rgn < nr_regions; rgn++) | |
1279 | { | |
1280 | fprintf (dump, ";;\trgn %d nr_blocks %d:\n", rgn, | |
1281 | rgn_table[rgn].rgn_nr_blocks); | |
1282 | fprintf (dump, ";;\tbb/block: "); | |
1283 | ||
1284 | for (bb = 0; bb < rgn_table[rgn].rgn_nr_blocks; bb++) | |
1285 | { | |
1286 | current_blocks = RGN_BLOCKS (rgn); | |
1287 | ||
1288 | if (bb != BLOCK_TO_BB (BB_TO_BLOCK (bb))) | |
1289 | abort (); | |
1290 | ||
1291 | fprintf (dump, " %d/%d ", bb, BB_TO_BLOCK (bb)); | |
1292 | } | |
1293 | ||
1294 | fprintf (dump, "\n\n"); | |
1295 | } | |
1296 | } | |
1297 | ||
1298 | ||
1299 | /* Build a single block region for each basic block in the function. | |
1300 | This allows for using the same code for interblock and basic block | |
1301 | scheduling. */ | |
1302 | ||
1303 | static void | |
1304 | find_single_block_region () | |
1305 | { | |
1306 | int i; | |
1307 | ||
1308 | for (i = 0; i < n_basic_blocks; i++) | |
1309 | { | |
1310 | rgn_bb_table[i] = i; | |
1311 | RGN_NR_BLOCKS (i) = 1; | |
1312 | RGN_BLOCKS (i) = i; | |
1313 | CONTAINING_RGN (i) = i; | |
1314 | BLOCK_TO_BB (i) = 0; | |
1315 | } | |
1316 | nr_regions = n_basic_blocks; | |
1317 | } | |
1318 | ||
1319 | ||
1320 | /* Update number of blocks and the estimate for number of insns | |
1321 | in the region. Return 1 if the region is "too large" for interblock | |
1322 | scheduling (compile time considerations), otherwise return 0. */ | |
1323 | ||
1324 | static int | |
1325 | too_large (block, num_bbs, num_insns) | |
1326 | int block, *num_bbs, *num_insns; | |
1327 | { | |
1328 | (*num_bbs)++; | |
3b413743 RH |
1329 | (*num_insns) += (INSN_LUID (BLOCK_END (block)) - |
1330 | INSN_LUID (BLOCK_HEAD (block))); | |
cc132865 | 1331 | if ((*num_bbs > MAX_RGN_BLOCKS) || (*num_insns > MAX_RGN_INSNS)) |
8c660648 JL |
1332 | return 1; |
1333 | else | |
1334 | return 0; | |
1335 | } | |
1336 | ||
1337 | ||
1338 | /* Update_loop_relations(blk, hdr): Check if the loop headed by max_hdr[blk] | |
1339 | is still an inner loop. Put in max_hdr[blk] the header of the most inner | |
1340 | loop containing blk. */ | |
1341 | #define UPDATE_LOOP_RELATIONS(blk, hdr) \ | |
1342 | { \ | |
1343 | if (max_hdr[blk] == -1) \ | |
1344 | max_hdr[blk] = hdr; \ | |
1345 | else if (dfs_nr[max_hdr[blk]] > dfs_nr[hdr]) \ | |
a2e68776 | 1346 | RESET_BIT (inner, hdr); \ |
8c660648 JL |
1347 | else if (dfs_nr[max_hdr[blk]] < dfs_nr[hdr]) \ |
1348 | { \ | |
a2e68776 | 1349 | RESET_BIT (inner,max_hdr[blk]); \ |
8c660648 JL |
1350 | max_hdr[blk] = hdr; \ |
1351 | } \ | |
1352 | } | |
1353 | ||
1354 | ||
a2e68776 JL |
1355 | /* Find regions for interblock scheduling. |
1356 | ||
1357 | A region for scheduling can be: | |
1358 | ||
1359 | * A loop-free procedure, or | |
1360 | ||
1361 | * A reducible inner loop, or | |
1362 | ||
1363 | * A basic block not contained in any other region. | |
1364 | ||
1365 | ||
1366 | ?!? In theory we could build other regions based on extended basic | |
1367 | blocks or reverse extended basic blocks. Is it worth the trouble? | |
1368 | ||
1369 | Loop blocks that form a region are put into the region's block list | |
1370 | in topological order. | |
1371 | ||
1372 | This procedure stores its results into the following global (ick) variables | |
1373 | ||
1374 | * rgn_nr | |
1375 | * rgn_table | |
1376 | * rgn_bb_table | |
1377 | * block_to_bb | |
1378 | * containing region | |
1379 | ||
1380 | ||
1381 | We use dominator relationships to avoid making regions out of non-reducible | |
1382 | loops. | |
8c660648 | 1383 | |
a2e68776 JL |
1384 | This procedure needs to be converted to work on pred/succ lists instead |
1385 | of edge tables. That would simplify it somewhat. */ | |
8c660648 JL |
1386 | |
1387 | static void | |
a2e68776 JL |
1388 | find_rgns (s_preds, s_succs, num_preds, num_succs, dom) |
1389 | int_list_ptr *s_preds; | |
1390 | int_list_ptr *s_succs; | |
1391 | int *num_preds; | |
1392 | int *num_succs; | |
1393 | sbitmap *dom; | |
8c660648 JL |
1394 | { |
1395 | int *max_hdr, *dfs_nr, *stack, *queue, *degree; | |
a2e68776 | 1396 | char no_loops = 1; |
487a6e06 | 1397 | int node, child, loop_head, i, head, tail; |
8c660648 | 1398 | int count = 0, sp, idx = 0, current_edge = out_edges[0]; |
15ebe47d | 1399 | int num_bbs, num_insns, unreachable; |
8c660648 | 1400 | int too_large_failure; |
8c660648 | 1401 | |
a2e68776 JL |
1402 | /* Note if an edge has been passed. */ |
1403 | sbitmap passed; | |
1404 | ||
1405 | /* Note if a block is a natural loop header. */ | |
1406 | sbitmap header; | |
1407 | ||
1408 | /* Note if a block is an natural inner loop header. */ | |
1409 | sbitmap inner; | |
1410 | ||
1411 | /* Note if a block is in the block queue. */ | |
1412 | sbitmap in_queue; | |
1413 | ||
cc132865 JL |
1414 | /* Note if a block is in the block queue. */ |
1415 | sbitmap in_stack; | |
1416 | ||
a2e68776 JL |
1417 | /* Perform a DFS traversal of the cfg. Identify loop headers, inner loops |
1418 | and a mapping from block to its loop header (if the block is contained | |
1419 | in a loop, else -1). | |
1420 | ||
1421 | Store results in HEADER, INNER, and MAX_HDR respectively, these will | |
1422 | be used as inputs to the second traversal. | |
1423 | ||
1424 | STACK, SP and DFS_NR are only used during the first traversal. */ | |
1425 | ||
1426 | /* Allocate and initialize variables for the first traversal. */ | |
8c660648 JL |
1427 | max_hdr = (int *) alloca (n_basic_blocks * sizeof (int)); |
1428 | dfs_nr = (int *) alloca (n_basic_blocks * sizeof (int)); | |
52b7724b | 1429 | bzero ((char *) dfs_nr, n_basic_blocks * sizeof (int)); |
8c660648 | 1430 | stack = (int *) alloca (nr_edges * sizeof (int)); |
8c660648 | 1431 | |
a2e68776 JL |
1432 | inner = sbitmap_alloc (n_basic_blocks); |
1433 | sbitmap_ones (inner); | |
1434 | ||
1435 | header = sbitmap_alloc (n_basic_blocks); | |
1436 | sbitmap_zero (header); | |
8c660648 | 1437 | |
a2e68776 JL |
1438 | passed = sbitmap_alloc (nr_edges); |
1439 | sbitmap_zero (passed); | |
1440 | ||
1441 | in_queue = sbitmap_alloc (n_basic_blocks); | |
1442 | sbitmap_zero (in_queue); | |
8c660648 | 1443 | |
cc132865 JL |
1444 | in_stack = sbitmap_alloc (n_basic_blocks); |
1445 | sbitmap_zero (in_stack); | |
1446 | ||
8c660648 | 1447 | for (i = 0; i < n_basic_blocks; i++) |
a2e68776 | 1448 | max_hdr[i] = -1; |
8c660648 | 1449 | |
a2e68776 | 1450 | /* DFS traversal to find inner loops in the cfg. */ |
8c660648 | 1451 | |
8c660648 JL |
1452 | sp = -1; |
1453 | while (1) | |
1454 | { | |
a2e68776 | 1455 | if (current_edge == 0 || TEST_BIT (passed, current_edge)) |
8c660648 | 1456 | { |
a2e68776 | 1457 | /* We have reached a leaf node or a node that was already |
cc132865 | 1458 | processed. Pop edges off the stack until we find |
a2e68776 JL |
1459 | an edge that has not yet been processed. */ |
1460 | while (sp >= 0 | |
1461 | && (current_edge == 0 || TEST_BIT (passed, current_edge))) | |
8c660648 | 1462 | { |
a2e68776 | 1463 | /* Pop entry off the stack. */ |
8c660648 JL |
1464 | current_edge = stack[sp--]; |
1465 | node = FROM_BLOCK (current_edge); | |
1466 | child = TO_BLOCK (current_edge); | |
cc132865 JL |
1467 | RESET_BIT (in_stack, child); |
1468 | if (max_hdr[child] >= 0 && TEST_BIT (in_stack, max_hdr[child])) | |
8c660648 JL |
1469 | UPDATE_LOOP_RELATIONS (node, max_hdr[child]); |
1470 | current_edge = NEXT_OUT (current_edge); | |
1471 | } | |
1472 | ||
a2e68776 JL |
1473 | /* See if have finished the DFS tree traversal. */ |
1474 | if (sp < 0 && TEST_BIT (passed, current_edge)) | |
8c660648 | 1475 | break; |
a2e68776 JL |
1476 | |
1477 | /* Nope, continue the traversal with the popped node. */ | |
8c660648 JL |
1478 | continue; |
1479 | } | |
1480 | ||
a2e68776 | 1481 | /* Process a node. */ |
8c660648 | 1482 | node = FROM_BLOCK (current_edge); |
8c660648 | 1483 | child = TO_BLOCK (current_edge); |
cc132865 | 1484 | SET_BIT (in_stack, node); |
a2e68776 | 1485 | dfs_nr[node] = ++count; |
8c660648 | 1486 | |
cc132865 JL |
1487 | /* If the successor is in the stack, then we've found a loop. |
1488 | Mark the loop, if it is not a natural loop, then it will | |
1489 | be rejected during the second traversal. */ | |
1490 | if (TEST_BIT (in_stack, child)) | |
8c660648 JL |
1491 | { |
1492 | no_loops = 0; | |
a2e68776 | 1493 | SET_BIT (header, child); |
8c660648 | 1494 | UPDATE_LOOP_RELATIONS (node, child); |
a2e68776 | 1495 | SET_BIT (passed, current_edge); |
8c660648 JL |
1496 | current_edge = NEXT_OUT (current_edge); |
1497 | continue; | |
1498 | } | |
1499 | ||
a2e68776 JL |
1500 | /* If the child was already visited, then there is no need to visit |
1501 | it again. Just update the loop relationships and restart | |
1502 | with a new edge. */ | |
8c660648 JL |
1503 | if (dfs_nr[child]) |
1504 | { | |
cc132865 | 1505 | if (max_hdr[child] >= 0 && TEST_BIT (in_stack, max_hdr[child])) |
8c660648 | 1506 | UPDATE_LOOP_RELATIONS (node, max_hdr[child]); |
a2e68776 | 1507 | SET_BIT (passed, current_edge); |
8c660648 JL |
1508 | current_edge = NEXT_OUT (current_edge); |
1509 | continue; | |
1510 | } | |
1511 | ||
a2e68776 | 1512 | /* Push an entry on the stack and continue DFS traversal. */ |
8c660648 | 1513 | stack[++sp] = current_edge; |
a2e68776 | 1514 | SET_BIT (passed, current_edge); |
8c660648 | 1515 | current_edge = OUT_EDGES (child); |
50f71e6f JL |
1516 | |
1517 | /* This is temporary until haifa is converted to use rth's new | |
1518 | cfg routines which have true entry/exit blocks and the | |
1519 | appropriate edges from/to those blocks. | |
1520 | ||
1521 | Generally we update dfs_nr for a node when we process its | |
1522 | out edge. However, if the node has no out edge then we will | |
1523 | not set dfs_nr for that node. This can confuse the scheduler | |
1524 | into thinking that we have unreachable blocks, which in turn | |
1525 | disables cross block scheduling. | |
1526 | ||
1527 | So, if we have a node with no out edges, go ahead and mark it | |
1528 | as reachable now. */ | |
1529 | if (current_edge == 0) | |
1530 | dfs_nr[child] = ++count; | |
a2e68776 | 1531 | } |
8c660648 | 1532 | |
15ebe47d JL |
1533 | /* Another check for unreachable blocks. The earlier test in |
1534 | is_cfg_nonregular only finds unreachable blocks that do not | |
1535 | form a loop. | |
a2e68776 | 1536 | |
15ebe47d JL |
1537 | The DFS traversal will mark every block that is reachable from |
1538 | the entry node by placing a nonzero value in dfs_nr. Thus if | |
1539 | dfs_nr is zero for any block, then it must be unreachable. */ | |
1540 | unreachable = 0; | |
1541 | for (i = 0; i < n_basic_blocks; i++) | |
1542 | if (dfs_nr[i] == 0) | |
1543 | { | |
1544 | unreachable = 1; | |
1545 | break; | |
1546 | } | |
a2e68776 JL |
1547 | |
1548 | /* Gross. To avoid wasting memory, the second pass uses the dfs_nr array | |
1549 | to hold degree counts. */ | |
1550 | degree = dfs_nr; | |
8c660648 | 1551 | |
63de6c74 | 1552 | /* Compute the in-degree of every block in the graph. */ |
8c660648 | 1553 | for (i = 0; i < n_basic_blocks; i++) |
a2e68776 JL |
1554 | degree[i] = num_preds[i]; |
1555 | ||
15ebe47d JL |
1556 | /* Do not perform region scheduling if there are any unreachable |
1557 | blocks. */ | |
1558 | if (!unreachable) | |
8c660648 | 1559 | { |
15ebe47d JL |
1560 | if (no_loops) |
1561 | SET_BIT (header, 0); | |
8c660648 | 1562 | |
15ebe47d JL |
1563 | /* Second travsersal:find reducible inner loops and topologically sort |
1564 | block of each region. */ | |
8c660648 | 1565 | |
15ebe47d | 1566 | queue = (int *) alloca (n_basic_blocks * sizeof (int)); |
8c660648 | 1567 | |
cc132865 JL |
1568 | /* Find blocks which are inner loop headers. We still have non-reducible |
1569 | loops to consider at this point. */ | |
15ebe47d JL |
1570 | for (i = 0; i < n_basic_blocks; i++) |
1571 | { | |
1572 | if (TEST_BIT (header, i) && TEST_BIT (inner, i)) | |
1573 | { | |
1574 | int_list_ptr ps; | |
cc132865 JL |
1575 | int j; |
1576 | ||
1577 | /* Now check that the loop is reducible. We do this separate | |
1578 | from finding inner loops so that we do not find a reducible | |
63de6c74 | 1579 | loop which contains an inner non-reducible loop. |
cc132865 | 1580 | |
63de6c74 | 1581 | A simple way to find reducible/natural loops is to verify |
cc132865 JL |
1582 | that each block in the loop is dominated by the loop |
1583 | header. | |
1584 | ||
1585 | If there exists a block that is not dominated by the loop | |
1586 | header, then the block is reachable from outside the loop | |
1587 | and thus the loop is not a natural loop. */ | |
1588 | for (j = 0; j < n_basic_blocks; j++) | |
1589 | { | |
1590 | /* First identify blocks in the loop, except for the loop | |
1591 | entry block. */ | |
1592 | if (i == max_hdr[j] && i != j) | |
1593 | { | |
1594 | /* Now verify that the block is dominated by the loop | |
1595 | header. */ | |
1596 | if (!TEST_BIT (dom[j], i)) | |
1597 | break; | |
1598 | } | |
1599 | } | |
1600 | ||
63de6c74 MH |
1601 | /* If we exited the loop early, then I is the header of |
1602 | a non-reducible loop and we should quit processing it | |
1603 | now. */ | |
cc132865 JL |
1604 | if (j != n_basic_blocks) |
1605 | continue; | |
8c660648 | 1606 | |
cc132865 JL |
1607 | /* I is a header of an inner loop, or block 0 in a subroutine |
1608 | with no loops at all. */ | |
15ebe47d JL |
1609 | head = tail = -1; |
1610 | too_large_failure = 0; | |
1611 | loop_head = max_hdr[i]; | |
8c660648 | 1612 | |
15ebe47d | 1613 | /* Decrease degree of all I's successors for topological |
a59bfd78 | 1614 | ordering. */ |
15ebe47d JL |
1615 | for (ps = s_succs[i]; ps; ps = ps->next) |
1616 | if (INT_LIST_VAL (ps) != EXIT_BLOCK | |
1617 | && INT_LIST_VAL (ps) != ENTRY_BLOCK) | |
cc132865 | 1618 | --degree[INT_LIST_VAL(ps)]; |
a2e68776 | 1619 | |
15ebe47d JL |
1620 | /* Estimate # insns, and count # blocks in the region. */ |
1621 | num_bbs = 1; | |
3b413743 RH |
1622 | num_insns = (INSN_LUID (BLOCK_END (i)) |
1623 | - INSN_LUID (BLOCK_HEAD (i))); | |
8c660648 | 1624 | |
15ebe47d | 1625 | |
63de6c74 | 1626 | /* Find all loop latches (blocks with back edges to the loop |
15ebe47d JL |
1627 | header) or all the leaf blocks in the cfg has no loops. |
1628 | ||
1629 | Place those blocks into the queue. */ | |
1630 | if (no_loops) | |
1631 | { | |
1632 | for (j = 0; j < n_basic_blocks; j++) | |
1633 | /* Leaf nodes have only a single successor which must | |
1634 | be EXIT_BLOCK. */ | |
1635 | if (num_succs[j] == 1 | |
1636 | && INT_LIST_VAL (s_succs[j]) == EXIT_BLOCK) | |
8c660648 | 1637 | { |
15ebe47d JL |
1638 | queue[++tail] = j; |
1639 | SET_BIT (in_queue, j); | |
1640 | ||
1641 | if (too_large (j, &num_bbs, &num_insns)) | |
1642 | { | |
1643 | too_large_failure = 1; | |
1644 | break; | |
1645 | } | |
8c660648 | 1646 | } |
15ebe47d JL |
1647 | } |
1648 | else | |
8c660648 | 1649 | { |
15ebe47d | 1650 | int_list_ptr ps; |
a2e68776 | 1651 | |
15ebe47d | 1652 | for (ps = s_preds[i]; ps; ps = ps->next) |
8c660648 | 1653 | { |
15ebe47d | 1654 | node = INT_LIST_VAL (ps); |
8c660648 | 1655 | |
15ebe47d JL |
1656 | if (node == ENTRY_BLOCK || node == EXIT_BLOCK) |
1657 | continue; | |
1658 | ||
1659 | if (max_hdr[node] == loop_head && node != i) | |
8c660648 | 1660 | { |
15ebe47d JL |
1661 | /* This is a loop latch. */ |
1662 | queue[++tail] = node; | |
1663 | SET_BIT (in_queue, node); | |
1664 | ||
1665 | if (too_large (node, &num_bbs, &num_insns)) | |
1666 | { | |
1667 | too_large_failure = 1; | |
1668 | break; | |
1669 | } | |
8c660648 | 1670 | } |
15ebe47d | 1671 | |
8c660648 | 1672 | } |
8c660648 | 1673 | } |
8c660648 | 1674 | |
15ebe47d | 1675 | /* Now add all the blocks in the loop to the queue. |
a2e68776 JL |
1676 | |
1677 | We know the loop is a natural loop; however the algorithm | |
1678 | above will not always mark certain blocks as being in the | |
1679 | loop. Consider: | |
1680 | node children | |
1681 | a b,c | |
1682 | b c | |
1683 | c a,d | |
1684 | d b | |
1685 | ||
1686 | ||
1687 | The algorithm in the DFS traversal may not mark B & D as part | |
1688 | of the loop (ie they will not have max_hdr set to A). | |
1689 | ||
1690 | We know they can not be loop latches (else they would have | |
1691 | had max_hdr set since they'd have a backedge to a dominator | |
1692 | block). So we don't need them on the initial queue. | |
1693 | ||
1694 | We know they are part of the loop because they are dominated | |
1695 | by the loop header and can be reached by a backwards walk of | |
1696 | the edges starting with nodes on the initial queue. | |
1697 | ||
1698 | It is safe and desirable to include those nodes in the | |
1699 | loop/scheduling region. To do so we would need to decrease | |
1700 | the degree of a node if it is the target of a backedge | |
1701 | within the loop itself as the node is placed in the queue. | |
1702 | ||
1703 | We do not do this because I'm not sure that the actual | |
1704 | scheduling code will properly handle this case. ?!? */ | |
1705 | ||
15ebe47d | 1706 | while (head < tail && !too_large_failure) |
8c660648 | 1707 | { |
15ebe47d JL |
1708 | int_list_ptr ps; |
1709 | child = queue[++head]; | |
8c660648 | 1710 | |
15ebe47d | 1711 | for (ps = s_preds[child]; ps; ps = ps->next) |
8c660648 | 1712 | { |
15ebe47d | 1713 | node = INT_LIST_VAL (ps); |
8c660648 | 1714 | |
15ebe47d JL |
1715 | /* See discussion above about nodes not marked as in |
1716 | this loop during the initial DFS traversal. */ | |
1717 | if (node == ENTRY_BLOCK || node == EXIT_BLOCK | |
1718 | || max_hdr[node] != loop_head) | |
8c660648 | 1719 | { |
15ebe47d | 1720 | tail = -1; |
8c660648 JL |
1721 | break; |
1722 | } | |
15ebe47d JL |
1723 | else if (!TEST_BIT (in_queue, node) && node != i) |
1724 | { | |
1725 | queue[++tail] = node; | |
1726 | SET_BIT (in_queue, node); | |
1727 | ||
1728 | if (too_large (node, &num_bbs, &num_insns)) | |
1729 | { | |
1730 | too_large_failure = 1; | |
1731 | break; | |
1732 | } | |
1733 | } | |
8c660648 | 1734 | } |
8c660648 | 1735 | } |
8c660648 | 1736 | |
15ebe47d JL |
1737 | if (tail >= 0 && !too_large_failure) |
1738 | { | |
1739 | /* Place the loop header into list of region blocks. */ | |
1740 | degree[i] = -1; | |
1741 | rgn_bb_table[idx] = i; | |
1742 | RGN_NR_BLOCKS (nr_regions) = num_bbs; | |
1743 | RGN_BLOCKS (nr_regions) = idx++; | |
1744 | CONTAINING_RGN (i) = nr_regions; | |
1745 | BLOCK_TO_BB (i) = count = 0; | |
1746 | ||
63de6c74 MH |
1747 | /* Remove blocks from queue[] when their in degree |
1748 | becomes zero. Repeat until no blocks are left on the | |
1749 | list. This produces a topological list of blocks in | |
1750 | the region. */ | |
15ebe47d | 1751 | while (tail >= 0) |
8c660648 | 1752 | { |
15ebe47d JL |
1753 | int_list_ptr ps; |
1754 | ||
1755 | if (head < 0) | |
1756 | head = tail; | |
1757 | child = queue[head]; | |
1758 | if (degree[child] == 0) | |
1759 | { | |
1760 | degree[child] = -1; | |
1761 | rgn_bb_table[idx++] = child; | |
1762 | BLOCK_TO_BB (child) = ++count; | |
1763 | CONTAINING_RGN (child) = nr_regions; | |
1764 | queue[head] = queue[tail--]; | |
1765 | ||
1766 | for (ps = s_succs[child]; ps; ps = ps->next) | |
1767 | if (INT_LIST_VAL (ps) != ENTRY_BLOCK | |
1768 | && INT_LIST_VAL (ps) != EXIT_BLOCK) | |
1769 | --degree[INT_LIST_VAL (ps)]; | |
1770 | } | |
1771 | else | |
1772 | --head; | |
8c660648 | 1773 | } |
15ebe47d | 1774 | ++nr_regions; |
8c660648 | 1775 | } |
8c660648 JL |
1776 | } |
1777 | } | |
1778 | } | |
1779 | ||
a2e68776 JL |
1780 | /* Any block that did not end up in a region is placed into a region |
1781 | by itself. */ | |
8c660648 JL |
1782 | for (i = 0; i < n_basic_blocks; i++) |
1783 | if (degree[i] >= 0) | |
1784 | { | |
1785 | rgn_bb_table[idx] = i; | |
1786 | RGN_NR_BLOCKS (nr_regions) = 1; | |
1787 | RGN_BLOCKS (nr_regions) = idx++; | |
1788 | CONTAINING_RGN (i) = nr_regions++; | |
1789 | BLOCK_TO_BB (i) = 0; | |
1790 | } | |
1791 | ||
a2e68776 JL |
1792 | free (passed); |
1793 | free (header); | |
1794 | free (inner); | |
1795 | free (in_queue); | |
cc132865 | 1796 | free (in_stack); |
a2e68776 | 1797 | } |
8c660648 JL |
1798 | |
1799 | ||
63de6c74 | 1800 | /* Functions for regions scheduling information. */ |
8c660648 JL |
1801 | |
1802 | /* Compute dominators, probability, and potential-split-edges of bb. | |
1803 | Assume that these values were already computed for bb's predecessors. */ | |
1804 | ||
1805 | static void | |
1806 | compute_dom_prob_ps (bb) | |
1807 | int bb; | |
1808 | { | |
1809 | int nxt_in_edge, fst_in_edge, pred; | |
1810 | int fst_out_edge, nxt_out_edge, nr_out_edges, nr_rgn_out_edges; | |
1811 | ||
1812 | prob[bb] = 0.0; | |
1813 | if (IS_RGN_ENTRY (bb)) | |
1814 | { | |
1815 | BITSET_ADD (dom[bb], 0, bbset_size); | |
1816 | prob[bb] = 1.0; | |
1817 | return; | |
1818 | } | |
1819 | ||
1820 | fst_in_edge = nxt_in_edge = IN_EDGES (BB_TO_BLOCK (bb)); | |
1821 | ||
63de6c74 | 1822 | /* Intialize dom[bb] to '111..1'. */ |
8c660648 JL |
1823 | BITSET_INVERT (dom[bb], bbset_size); |
1824 | ||
1825 | do | |
1826 | { | |
1827 | pred = FROM_BLOCK (nxt_in_edge); | |
1828 | BITSET_INTER (dom[bb], dom[BLOCK_TO_BB (pred)], bbset_size); | |
1829 | ||
1830 | BITSET_UNION (ancestor_edges[bb], ancestor_edges[BLOCK_TO_BB (pred)], | |
1831 | edgeset_size); | |
1832 | ||
1833 | BITSET_ADD (ancestor_edges[bb], EDGE_TO_BIT (nxt_in_edge), edgeset_size); | |
1834 | ||
1835 | nr_out_edges = 1; | |
1836 | nr_rgn_out_edges = 0; | |
1837 | fst_out_edge = OUT_EDGES (pred); | |
1838 | nxt_out_edge = NEXT_OUT (fst_out_edge); | |
1839 | BITSET_UNION (pot_split[bb], pot_split[BLOCK_TO_BB (pred)], | |
1840 | edgeset_size); | |
1841 | ||
1842 | BITSET_ADD (pot_split[bb], EDGE_TO_BIT (fst_out_edge), edgeset_size); | |
1843 | ||
63de6c74 | 1844 | /* The successor doesn't belong in the region? */ |
8c660648 JL |
1845 | if (CONTAINING_RGN (TO_BLOCK (fst_out_edge)) != |
1846 | CONTAINING_RGN (BB_TO_BLOCK (bb))) | |
1847 | ++nr_rgn_out_edges; | |
1848 | ||
1849 | while (fst_out_edge != nxt_out_edge) | |
1850 | { | |
1851 | ++nr_out_edges; | |
63de6c74 | 1852 | /* The successor doesn't belong in the region? */ |
8c660648 JL |
1853 | if (CONTAINING_RGN (TO_BLOCK (nxt_out_edge)) != |
1854 | CONTAINING_RGN (BB_TO_BLOCK (bb))) | |
1855 | ++nr_rgn_out_edges; | |
1856 | BITSET_ADD (pot_split[bb], EDGE_TO_BIT (nxt_out_edge), edgeset_size); | |
1857 | nxt_out_edge = NEXT_OUT (nxt_out_edge); | |
1858 | ||
1859 | } | |
1860 | ||
63de6c74 MH |
1861 | /* Now nr_rgn_out_edges is the number of region-exit edges from |
1862 | pred, and nr_out_edges will be the number of pred out edges | |
1863 | not leaving the region. */ | |
8c660648 JL |
1864 | nr_out_edges -= nr_rgn_out_edges; |
1865 | if (nr_rgn_out_edges > 0) | |
1866 | prob[bb] += 0.9 * prob[BLOCK_TO_BB (pred)] / nr_out_edges; | |
1867 | else | |
1868 | prob[bb] += prob[BLOCK_TO_BB (pred)] / nr_out_edges; | |
1869 | nxt_in_edge = NEXT_IN (nxt_in_edge); | |
1870 | } | |
1871 | while (fst_in_edge != nxt_in_edge); | |
1872 | ||
1873 | BITSET_ADD (dom[bb], bb, bbset_size); | |
1874 | BITSET_DIFFER (pot_split[bb], ancestor_edges[bb], edgeset_size); | |
1875 | ||
1876 | if (sched_verbose >= 2) | |
1877 | fprintf (dump, ";; bb_prob(%d, %d) = %3d\n", bb, BB_TO_BLOCK (bb), (int) (100.0 * prob[bb])); | |
1878 | } /* compute_dom_prob_ps */ | |
1879 | ||
63de6c74 | 1880 | /* Functions for target info. */ |
8c660648 JL |
1881 | |
1882 | /* Compute in BL the list of split-edges of bb_src relatively to bb_trg. | |
1883 | Note that bb_trg dominates bb_src. */ | |
1884 | ||
1885 | static void | |
1886 | split_edges (bb_src, bb_trg, bl) | |
1887 | int bb_src; | |
1888 | int bb_trg; | |
1889 | edgelst *bl; | |
1890 | { | |
1891 | int es = edgeset_size; | |
1892 | edgeset src = (edgeset) alloca (es * sizeof (HOST_WIDE_INT)); | |
1893 | ||
1894 | while (es--) | |
1895 | src[es] = (pot_split[bb_src])[es]; | |
1896 | BITSET_DIFFER (src, pot_split[bb_trg], edgeset_size); | |
1897 | extract_bitlst (src, edgeset_size, bl); | |
1898 | } | |
1899 | ||
1900 | ||
1901 | /* Find the valid candidate-source-blocks for the target block TRG, compute | |
1902 | their probability, and check if they are speculative or not. | |
1903 | For speculative sources, compute their update-blocks and split-blocks. */ | |
1904 | ||
1905 | static void | |
1906 | compute_trg_info (trg) | |
1907 | int trg; | |
1908 | { | |
1909 | register candidate *sp; | |
1910 | edgelst el; | |
1911 | int check_block, update_idx; | |
1912 | int i, j, k, fst_edge, nxt_edge; | |
1913 | ||
63de6c74 | 1914 | /* Define some of the fields for the target bb as well. */ |
8c660648 JL |
1915 | sp = candidate_table + trg; |
1916 | sp->is_valid = 1; | |
1917 | sp->is_speculative = 0; | |
1918 | sp->src_prob = 100; | |
1919 | ||
1920 | for (i = trg + 1; i < current_nr_blocks; i++) | |
1921 | { | |
1922 | sp = candidate_table + i; | |
1923 | ||
1924 | sp->is_valid = IS_DOMINATED (i, trg); | |
1925 | if (sp->is_valid) | |
1926 | { | |
1927 | sp->src_prob = GET_SRC_PROB (i, trg); | |
1928 | sp->is_valid = (sp->src_prob >= MIN_PROBABILITY); | |
1929 | } | |
1930 | ||
1931 | if (sp->is_valid) | |
1932 | { | |
1933 | split_edges (i, trg, &el); | |
1934 | sp->is_speculative = (el.nr_members) ? 1 : 0; | |
1935 | if (sp->is_speculative && !flag_schedule_speculative) | |
1936 | sp->is_valid = 0; | |
1937 | } | |
1938 | ||
1939 | if (sp->is_valid) | |
1940 | { | |
1941 | sp->split_bbs.first_member = &bblst_table[bblst_last]; | |
1942 | sp->split_bbs.nr_members = el.nr_members; | |
1943 | for (j = 0; j < el.nr_members; bblst_last++, j++) | |
1944 | bblst_table[bblst_last] = | |
1945 | TO_BLOCK (rgn_edges[el.first_member[j]]); | |
1946 | sp->update_bbs.first_member = &bblst_table[bblst_last]; | |
1947 | update_idx = 0; | |
1948 | for (j = 0; j < el.nr_members; j++) | |
1949 | { | |
1950 | check_block = FROM_BLOCK (rgn_edges[el.first_member[j]]); | |
1951 | fst_edge = nxt_edge = OUT_EDGES (check_block); | |
1952 | do | |
1953 | { | |
1954 | for (k = 0; k < el.nr_members; k++) | |
1955 | if (EDGE_TO_BIT (nxt_edge) == el.first_member[k]) | |
1956 | break; | |
1957 | ||
1958 | if (k >= el.nr_members) | |
1959 | { | |
1960 | bblst_table[bblst_last++] = TO_BLOCK (nxt_edge); | |
1961 | update_idx++; | |
1962 | } | |
1963 | ||
1964 | nxt_edge = NEXT_OUT (nxt_edge); | |
1965 | } | |
1966 | while (fst_edge != nxt_edge); | |
1967 | } | |
1968 | sp->update_bbs.nr_members = update_idx; | |
1969 | ||
1970 | } | |
1971 | else | |
1972 | { | |
1973 | sp->split_bbs.nr_members = sp->update_bbs.nr_members = 0; | |
1974 | ||
1975 | sp->is_speculative = 0; | |
1976 | sp->src_prob = 0; | |
1977 | } | |
1978 | } | |
1979 | } /* compute_trg_info */ | |
1980 | ||
1981 | ||
1982 | /* Print candidates info, for debugging purposes. Callable from debugger. */ | |
1983 | ||
1984 | void | |
1985 | debug_candidate (i) | |
1986 | int i; | |
1987 | { | |
1988 | if (!candidate_table[i].is_valid) | |
1989 | return; | |
1990 | ||
1991 | if (candidate_table[i].is_speculative) | |
1992 | { | |
1993 | int j; | |
1994 | fprintf (dump, "src b %d bb %d speculative \n", BB_TO_BLOCK (i), i); | |
1995 | ||
1996 | fprintf (dump, "split path: "); | |
1997 | for (j = 0; j < candidate_table[i].split_bbs.nr_members; j++) | |
1998 | { | |
1999 | int b = candidate_table[i].split_bbs.first_member[j]; | |
2000 | ||
2001 | fprintf (dump, " %d ", b); | |
2002 | } | |
2003 | fprintf (dump, "\n"); | |
2004 | ||
2005 | fprintf (dump, "update path: "); | |
2006 | for (j = 0; j < candidate_table[i].update_bbs.nr_members; j++) | |
2007 | { | |
2008 | int b = candidate_table[i].update_bbs.first_member[j]; | |
2009 | ||
2010 | fprintf (dump, " %d ", b); | |
2011 | } | |
2012 | fprintf (dump, "\n"); | |
2013 | } | |
2014 | else | |
2015 | { | |
2016 | fprintf (dump, " src %d equivalent\n", BB_TO_BLOCK (i)); | |
2017 | } | |
2018 | } | |
2019 | ||
2020 | ||
2021 | /* Print candidates info, for debugging purposes. Callable from debugger. */ | |
2022 | ||
2023 | void | |
2024 | debug_candidates (trg) | |
2025 | int trg; | |
2026 | { | |
2027 | int i; | |
2028 | ||
2029 | fprintf (dump, "----------- candidate table: target: b=%d bb=%d ---\n", | |
2030 | BB_TO_BLOCK (trg), trg); | |
2031 | for (i = trg + 1; i < current_nr_blocks; i++) | |
2032 | debug_candidate (i); | |
2033 | } | |
2034 | ||
2035 | ||
63de6c74 | 2036 | /* Functions for speculative scheduing. */ |
8c660648 JL |
2037 | |
2038 | /* Return 0 if x is a set of a register alive in the beginning of one | |
2039 | of the split-blocks of src, otherwise return 1. */ | |
2040 | ||
2041 | static int | |
2042 | check_live_1 (src, x) | |
2043 | int src; | |
2044 | rtx x; | |
2045 | { | |
5835e573 | 2046 | register int i; |
8c660648 JL |
2047 | register int regno; |
2048 | register rtx reg = SET_DEST (x); | |
2049 | ||
2050 | if (reg == 0) | |
2051 | return 1; | |
2052 | ||
2053 | while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT | |
2054 | || GET_CODE (reg) == SIGN_EXTRACT | |
2055 | || GET_CODE (reg) == STRICT_LOW_PART) | |
2056 | reg = XEXP (reg, 0); | |
2057 | ||
c0222c21 DM |
2058 | if (GET_CODE (reg) == PARALLEL |
2059 | && GET_MODE (reg) == BLKmode) | |
2060 | { | |
2061 | register int i; | |
2062 | for (i = XVECLEN (reg, 0) - 1; i >= 0; i--) | |
2063 | if (check_live_1 (src, XVECEXP (reg, 0, i))) | |
2064 | return 1; | |
2065 | return 0; | |
2066 | } | |
2067 | ||
8c660648 JL |
2068 | if (GET_CODE (reg) != REG) |
2069 | return 1; | |
2070 | ||
2071 | regno = REGNO (reg); | |
2072 | ||
2073 | if (regno < FIRST_PSEUDO_REGISTER && global_regs[regno]) | |
2074 | { | |
63de6c74 | 2075 | /* Global registers are assumed live. */ |
8c660648 JL |
2076 | return 0; |
2077 | } | |
2078 | else | |
2079 | { | |
2080 | if (regno < FIRST_PSEUDO_REGISTER) | |
2081 | { | |
63de6c74 | 2082 | /* Check for hard registers. */ |
8c660648 JL |
2083 | int j = HARD_REGNO_NREGS (regno, GET_MODE (reg)); |
2084 | while (--j >= 0) | |
2085 | { | |
2086 | for (i = 0; i < candidate_table[src].split_bbs.nr_members; i++) | |
2087 | { | |
2088 | int b = candidate_table[src].split_bbs.first_member[i]; | |
2089 | ||
e881bb1b RH |
2090 | if (REGNO_REG_SET_P (BASIC_BLOCK (b)->global_live_at_start, |
2091 | regno + j)) | |
8c660648 JL |
2092 | { |
2093 | return 0; | |
2094 | } | |
2095 | } | |
2096 | } | |
2097 | } | |
2098 | else | |
2099 | { | |
63de6c74 | 2100 | /* Check for psuedo registers. */ |
8c660648 JL |
2101 | for (i = 0; i < candidate_table[src].split_bbs.nr_members; i++) |
2102 | { | |
2103 | int b = candidate_table[src].split_bbs.first_member[i]; | |
2104 | ||
e881bb1b | 2105 | if (REGNO_REG_SET_P (BASIC_BLOCK (b)->global_live_at_start, regno)) |
8c660648 JL |
2106 | { |
2107 | return 0; | |
2108 | } | |
2109 | } | |
2110 | } | |
2111 | } | |
2112 | ||
2113 | return 1; | |
2114 | } | |
2115 | ||
2116 | ||
2117 | /* If x is a set of a register R, mark that R is alive in the beginning | |
2118 | of every update-block of src. */ | |
2119 | ||
2120 | static void | |
2121 | update_live_1 (src, x) | |
2122 | int src; | |
2123 | rtx x; | |
2124 | { | |
5835e573 | 2125 | register int i; |
8c660648 JL |
2126 | register int regno; |
2127 | register rtx reg = SET_DEST (x); | |
2128 | ||
2129 | if (reg == 0) | |
2130 | return; | |
2131 | ||
2132 | while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT | |
2133 | || GET_CODE (reg) == SIGN_EXTRACT | |
2134 | || GET_CODE (reg) == STRICT_LOW_PART) | |
2135 | reg = XEXP (reg, 0); | |
2136 | ||
c0222c21 DM |
2137 | if (GET_CODE (reg) == PARALLEL |
2138 | && GET_MODE (reg) == BLKmode) | |
2139 | { | |
2140 | register int i; | |
2141 | for (i = XVECLEN (reg, 0) - 1; i >= 0; i--) | |
2142 | update_live_1 (src, XVECEXP (reg, 0, i)); | |
2143 | return; | |
2144 | } | |
2145 | ||
8c660648 JL |
2146 | if (GET_CODE (reg) != REG) |
2147 | return; | |
2148 | ||
2149 | /* Global registers are always live, so the code below does not apply | |
2150 | to them. */ | |
2151 | ||
2152 | regno = REGNO (reg); | |
2153 | ||
2154 | if (regno >= FIRST_PSEUDO_REGISTER || !global_regs[regno]) | |
2155 | { | |
2156 | if (regno < FIRST_PSEUDO_REGISTER) | |
2157 | { | |
2158 | int j = HARD_REGNO_NREGS (regno, GET_MODE (reg)); | |
2159 | while (--j >= 0) | |
2160 | { | |
2161 | for (i = 0; i < candidate_table[src].update_bbs.nr_members; i++) | |
2162 | { | |
2163 | int b = candidate_table[src].update_bbs.first_member[i]; | |
2164 | ||
e881bb1b RH |
2165 | SET_REGNO_REG_SET (BASIC_BLOCK (b)->global_live_at_start, |
2166 | regno + j); | |
8c660648 JL |
2167 | } |
2168 | } | |
2169 | } | |
2170 | else | |
2171 | { | |
2172 | for (i = 0; i < candidate_table[src].update_bbs.nr_members; i++) | |
2173 | { | |
2174 | int b = candidate_table[src].update_bbs.first_member[i]; | |
2175 | ||
e881bb1b | 2176 | SET_REGNO_REG_SET (BASIC_BLOCK (b)->global_live_at_start, regno); |
8c660648 JL |
2177 | } |
2178 | } | |
2179 | } | |
2180 | } | |
2181 | ||
2182 | ||
2183 | /* Return 1 if insn can be speculatively moved from block src to trg, | |
2184 | otherwise return 0. Called before first insertion of insn to | |
2185 | ready-list or before the scheduling. */ | |
2186 | ||
2187 | static int | |
5835e573 | 2188 | check_live (insn, src) |
8c660648 JL |
2189 | rtx insn; |
2190 | int src; | |
8c660648 | 2191 | { |
63de6c74 | 2192 | /* Find the registers set by instruction. */ |
8c660648 JL |
2193 | if (GET_CODE (PATTERN (insn)) == SET |
2194 | || GET_CODE (PATTERN (insn)) == CLOBBER) | |
2195 | return check_live_1 (src, PATTERN (insn)); | |
2196 | else if (GET_CODE (PATTERN (insn)) == PARALLEL) | |
2197 | { | |
2198 | int j; | |
2199 | for (j = XVECLEN (PATTERN (insn), 0) - 1; j >= 0; j--) | |
2200 | if ((GET_CODE (XVECEXP (PATTERN (insn), 0, j)) == SET | |
2201 | || GET_CODE (XVECEXP (PATTERN (insn), 0, j)) == CLOBBER) | |
2202 | && !check_live_1 (src, XVECEXP (PATTERN (insn), 0, j))) | |
2203 | return 0; | |
2204 | ||
2205 | return 1; | |
2206 | } | |
2207 | ||
2208 | return 1; | |
2209 | } | |
2210 | ||
2211 | ||
2212 | /* Update the live registers info after insn was moved speculatively from | |
2213 | block src to trg. */ | |
2214 | ||
2215 | static void | |
5835e573 | 2216 | update_live (insn, src) |
8c660648 | 2217 | rtx insn; |
5835e573 | 2218 | int src; |
8c660648 | 2219 | { |
63de6c74 | 2220 | /* Find the registers set by instruction. */ |
8c660648 JL |
2221 | if (GET_CODE (PATTERN (insn)) == SET |
2222 | || GET_CODE (PATTERN (insn)) == CLOBBER) | |
2223 | update_live_1 (src, PATTERN (insn)); | |
2224 | else if (GET_CODE (PATTERN (insn)) == PARALLEL) | |
2225 | { | |
2226 | int j; | |
2227 | for (j = XVECLEN (PATTERN (insn), 0) - 1; j >= 0; j--) | |
2228 | if (GET_CODE (XVECEXP (PATTERN (insn), 0, j)) == SET | |
2229 | || GET_CODE (XVECEXP (PATTERN (insn), 0, j)) == CLOBBER) | |
2230 | update_live_1 (src, XVECEXP (PATTERN (insn), 0, j)); | |
2231 | } | |
2232 | } | |
2233 | ||
2234 | /* Exception Free Loads: | |
2235 | ||
2236 | We define five classes of speculative loads: IFREE, IRISKY, | |
2237 | PFREE, PRISKY, and MFREE. | |
2238 | ||
2239 | IFREE loads are loads that are proved to be exception-free, just | |
2240 | by examining the load insn. Examples for such loads are loads | |
2241 | from TOC and loads of global data. | |
2242 | ||
2243 | IRISKY loads are loads that are proved to be exception-risky, | |
2244 | just by examining the load insn. Examples for such loads are | |
2245 | volatile loads and loads from shared memory. | |
2246 | ||
2247 | PFREE loads are loads for which we can prove, by examining other | |
2248 | insns, that they are exception-free. Currently, this class consists | |
2249 | of loads for which we are able to find a "similar load", either in | |
2250 | the target block, or, if only one split-block exists, in that split | |
2251 | block. Load2 is similar to load1 if both have same single base | |
2252 | register. We identify only part of the similar loads, by finding | |
2253 | an insn upon which both load1 and load2 have a DEF-USE dependence. | |
2254 | ||
2255 | PRISKY loads are loads for which we can prove, by examining other | |
2256 | insns, that they are exception-risky. Currently we have two proofs for | |
2257 | such loads. The first proof detects loads that are probably guarded by a | |
2258 | test on the memory address. This proof is based on the | |
2259 | backward and forward data dependence information for the region. | |
2260 | Let load-insn be the examined load. | |
2261 | Load-insn is PRISKY iff ALL the following hold: | |
2262 | ||
2263 | - insn1 is not in the same block as load-insn | |
2264 | - there is a DEF-USE dependence chain (insn1, ..., load-insn) | |
63de6c74 MH |
2265 | - test-insn is either a compare or a branch, not in the same block |
2266 | as load-insn | |
8c660648 JL |
2267 | - load-insn is reachable from test-insn |
2268 | - there is a DEF-USE dependence chain (insn1, ..., test-insn) | |
2269 | ||
2270 | This proof might fail when the compare and the load are fed | |
2271 | by an insn not in the region. To solve this, we will add to this | |
2272 | group all loads that have no input DEF-USE dependence. | |
2273 | ||
2274 | The second proof detects loads that are directly or indirectly | |
2275 | fed by a speculative load. This proof is affected by the | |
2276 | scheduling process. We will use the flag fed_by_spec_load. | |
2277 | Initially, all insns have this flag reset. After a speculative | |
2278 | motion of an insn, if insn is either a load, or marked as | |
2279 | fed_by_spec_load, we will also mark as fed_by_spec_load every | |
2280 | insn1 for which a DEF-USE dependence (insn, insn1) exists. A | |
2281 | load which is fed_by_spec_load is also PRISKY. | |
2282 | ||
2283 | MFREE (maybe-free) loads are all the remaining loads. They may be | |
2284 | exception-free, but we cannot prove it. | |
2285 | ||
2286 | Now, all loads in IFREE and PFREE classes are considered | |
2287 | exception-free, while all loads in IRISKY and PRISKY classes are | |
2288 | considered exception-risky. As for loads in the MFREE class, | |
2289 | these are considered either exception-free or exception-risky, | |
2290 | depending on whether we are pessimistic or optimistic. We have | |
2291 | to take the pessimistic approach to assure the safety of | |
2292 | speculative scheduling, but we can take the optimistic approach | |
2293 | by invoking the -fsched_spec_load_dangerous option. */ | |
2294 | ||
2295 | enum INSN_TRAP_CLASS | |
2296 | { | |
2297 | TRAP_FREE = 0, IFREE = 1, PFREE_CANDIDATE = 2, | |
2298 | PRISKY_CANDIDATE = 3, IRISKY = 4, TRAP_RISKY = 5 | |
2299 | }; | |
2300 | ||
2301 | #define WORST_CLASS(class1, class2) \ | |
2302 | ((class1 > class2) ? class1 : class2) | |
2303 | ||
63de6c74 MH |
2304 | /* Indexed by INSN_UID, and set if there's DEF-USE dependence between |
2305 | some speculatively moved load insn and this one. */ | |
8c660648 JL |
2306 | char *fed_by_spec_load; |
2307 | char *is_load_insn; | |
2308 | ||
2309 | /* Non-zero if block bb_to is equal to, or reachable from block bb_from. */ | |
2310 | #define IS_REACHABLE(bb_from, bb_to) \ | |
2311 | (bb_from == bb_to \ | |
2312 | || IS_RGN_ENTRY (bb_from) \ | |
2313 | || (bitset_member (ancestor_edges[bb_to], \ | |
2314 | EDGE_TO_BIT (IN_EDGES (BB_TO_BLOCK (bb_from))), \ | |
2315 | edgeset_size))) | |
2316 | #define FED_BY_SPEC_LOAD(insn) (fed_by_spec_load[INSN_UID (insn)]) | |
2317 | #define IS_LOAD_INSN(insn) (is_load_insn[INSN_UID (insn)]) | |
2318 | ||
63de6c74 | 2319 | /* Non-zero iff the address is comprised from at most 1 register. */ |
8c660648 JL |
2320 | #define CONST_BASED_ADDRESS_P(x) \ |
2321 | (GET_CODE (x) == REG \ | |
2322 | || ((GET_CODE (x) == PLUS || GET_CODE (x) == MINUS \ | |
2323 | || (GET_CODE (x) == LO_SUM)) \ | |
2324 | && (GET_CODE (XEXP (x, 0)) == CONST_INT \ | |
2325 | || GET_CODE (XEXP (x, 1)) == CONST_INT))) | |
2326 | ||
2327 | /* Turns on the fed_by_spec_load flag for insns fed by load_insn. */ | |
2328 | ||
2329 | static void | |
2330 | set_spec_fed (load_insn) | |
2331 | rtx load_insn; | |
2332 | { | |
2333 | rtx link; | |
2334 | ||
2335 | for (link = INSN_DEPEND (load_insn); link; link = XEXP (link, 1)) | |
2336 | if (GET_MODE (link) == VOIDmode) | |
2337 | FED_BY_SPEC_LOAD (XEXP (link, 0)) = 1; | |
2338 | } /* set_spec_fed */ | |
2339 | ||
63de6c74 MH |
2340 | /* On the path from the insn to load_insn_bb, find a conditional |
2341 | branch depending on insn, that guards the speculative load. */ | |
8c660648 JL |
2342 | |
2343 | static int | |
2344 | find_conditional_protection (insn, load_insn_bb) | |
2345 | rtx insn; | |
2346 | int load_insn_bb; | |
2347 | { | |
2348 | rtx link; | |
2349 | ||
63de6c74 | 2350 | /* Iterate through DEF-USE forward dependences. */ |
8c660648 JL |
2351 | for (link = INSN_DEPEND (insn); link; link = XEXP (link, 1)) |
2352 | { | |
2353 | rtx next = XEXP (link, 0); | |
2354 | if ((CONTAINING_RGN (INSN_BLOCK (next)) == | |
2355 | CONTAINING_RGN (BB_TO_BLOCK (load_insn_bb))) | |
2356 | && IS_REACHABLE (INSN_BB (next), load_insn_bb) | |
2357 | && load_insn_bb != INSN_BB (next) | |
2358 | && GET_MODE (link) == VOIDmode | |
2359 | && (GET_CODE (next) == JUMP_INSN | |
2360 | || find_conditional_protection (next, load_insn_bb))) | |
2361 | return 1; | |
2362 | } | |
2363 | return 0; | |
2364 | } /* find_conditional_protection */ | |
2365 | ||
2366 | /* Returns 1 if the same insn1 that participates in the computation | |
2367 | of load_insn's address is feeding a conditional branch that is | |
2368 | guarding on load_insn. This is true if we find a the two DEF-USE | |
2369 | chains: | |
2370 | insn1 -> ... -> conditional-branch | |
2371 | insn1 -> ... -> load_insn, | |
2372 | and if a flow path exist: | |
2373 | insn1 -> ... -> conditional-branch -> ... -> load_insn, | |
2374 | and if insn1 is on the path | |
2375 | region-entry -> ... -> bb_trg -> ... load_insn. | |
2376 | ||
2377 | Locate insn1 by climbing on LOG_LINKS from load_insn. | |
2378 | Locate the branch by following INSN_DEPEND from insn1. */ | |
2379 | ||
2380 | static int | |
2381 | is_conditionally_protected (load_insn, bb_src, bb_trg) | |
2382 | rtx load_insn; | |
2383 | int bb_src, bb_trg; | |
2384 | { | |
2385 | rtx link; | |
2386 | ||
2387 | for (link = LOG_LINKS (load_insn); link; link = XEXP (link, 1)) | |
2388 | { | |
2389 | rtx insn1 = XEXP (link, 0); | |
2390 | ||
63de6c74 | 2391 | /* Must be a DEF-USE dependence upon non-branch. */ |
8c660648 JL |
2392 | if (GET_MODE (link) != VOIDmode |
2393 | || GET_CODE (insn1) == JUMP_INSN) | |
2394 | continue; | |
2395 | ||
63de6c74 | 2396 | /* Must exist a path: region-entry -> ... -> bb_trg -> ... load_insn. */ |
8c660648 JL |
2397 | if (INSN_BB (insn1) == bb_src |
2398 | || (CONTAINING_RGN (INSN_BLOCK (insn1)) | |
2399 | != CONTAINING_RGN (BB_TO_BLOCK (bb_src))) | |
2400 | || (!IS_REACHABLE (bb_trg, INSN_BB (insn1)) | |
2401 | && !IS_REACHABLE (INSN_BB (insn1), bb_trg))) | |
2402 | continue; | |
2403 | ||
63de6c74 | 2404 | /* Now search for the conditional-branch. */ |
8c660648 JL |
2405 | if (find_conditional_protection (insn1, bb_src)) |
2406 | return 1; | |
2407 | ||
63de6c74 | 2408 | /* Recursive step: search another insn1, "above" current insn1. */ |
8c660648 JL |
2409 | return is_conditionally_protected (insn1, bb_src, bb_trg); |
2410 | } | |
2411 | ||
63de6c74 | 2412 | /* The chain does not exist. */ |
8c660648 JL |
2413 | return 0; |
2414 | } /* is_conditionally_protected */ | |
2415 | ||
2416 | /* Returns 1 if a clue for "similar load" 'insn2' is found, and hence | |
2417 | load_insn can move speculatively from bb_src to bb_trg. All the | |
2418 | following must hold: | |
2419 | ||
2420 | (1) both loads have 1 base register (PFREE_CANDIDATEs). | |
2421 | (2) load_insn and load1 have a def-use dependence upon | |
2422 | the same insn 'insn1'. | |
2423 | (3) either load2 is in bb_trg, or: | |
2424 | - there's only one split-block, and | |
2425 | - load1 is on the escape path, and | |
2426 | ||
2427 | From all these we can conclude that the two loads access memory | |
2428 | addresses that differ at most by a constant, and hence if moving | |
2429 | load_insn would cause an exception, it would have been caused by | |
2430 | load2 anyhow. */ | |
2431 | ||
2432 | static int | |
2433 | is_pfree (load_insn, bb_src, bb_trg) | |
2434 | rtx load_insn; | |
2435 | int bb_src, bb_trg; | |
2436 | { | |
2437 | rtx back_link; | |
2438 | register candidate *candp = candidate_table + bb_src; | |
2439 | ||
2440 | if (candp->split_bbs.nr_members != 1) | |
63de6c74 | 2441 | /* Must have exactly one escape block. */ |
8c660648 JL |
2442 | return 0; |
2443 | ||
2444 | for (back_link = LOG_LINKS (load_insn); | |
2445 | back_link; back_link = XEXP (back_link, 1)) | |
2446 | { | |
2447 | rtx insn1 = XEXP (back_link, 0); | |
2448 | ||
2449 | if (GET_MODE (back_link) == VOIDmode) | |
2450 | { | |
63de6c74 | 2451 | /* Found a DEF-USE dependence (insn1, load_insn). */ |
8c660648 JL |
2452 | rtx fore_link; |
2453 | ||
2454 | for (fore_link = INSN_DEPEND (insn1); | |
2455 | fore_link; fore_link = XEXP (fore_link, 1)) | |
2456 | { | |
2457 | rtx insn2 = XEXP (fore_link, 0); | |
2458 | if (GET_MODE (fore_link) == VOIDmode) | |
2459 | { | |
63de6c74 | 2460 | /* Found a DEF-USE dependence (insn1, insn2). */ |
ac957f13 | 2461 | if (haifa_classify_insn (insn2) != PFREE_CANDIDATE) |
63de6c74 | 2462 | /* insn2 not guaranteed to be a 1 base reg load. */ |
8c660648 JL |
2463 | continue; |
2464 | ||
2465 | if (INSN_BB (insn2) == bb_trg) | |
63de6c74 | 2466 | /* insn2 is the similar load, in the target block. */ |
8c660648 JL |
2467 | return 1; |
2468 | ||
2469 | if (*(candp->split_bbs.first_member) == INSN_BLOCK (insn2)) | |
63de6c74 | 2470 | /* insn2 is a similar load, in a split-block. */ |
8c660648 JL |
2471 | return 1; |
2472 | } | |
2473 | } | |
2474 | } | |
2475 | } | |
2476 | ||
63de6c74 | 2477 | /* Couldn't find a similar load. */ |
8c660648 JL |
2478 | return 0; |
2479 | } /* is_pfree */ | |
2480 | ||
2481 | /* Returns a class that insn with GET_DEST(insn)=x may belong to, | |
2482 | as found by analyzing insn's expression. */ | |
2483 | ||
2484 | static int | |
2485 | may_trap_exp (x, is_store) | |
2486 | rtx x; | |
2487 | int is_store; | |
2488 | { | |
2489 | enum rtx_code code; | |
2490 | ||
2491 | if (x == 0) | |
2492 | return TRAP_FREE; | |
2493 | code = GET_CODE (x); | |
2494 | if (is_store) | |
2495 | { | |
2496 | if (code == MEM) | |
2497 | return TRAP_RISKY; | |
2498 | else | |
2499 | return TRAP_FREE; | |
2500 | } | |
2501 | if (code == MEM) | |
2502 | { | |
63de6c74 | 2503 | /* The insn uses memory: a volatile load. */ |
8c660648 JL |
2504 | if (MEM_VOLATILE_P (x)) |
2505 | return IRISKY; | |
63de6c74 | 2506 | /* An exception-free load. */ |
8c660648 JL |
2507 | if (!may_trap_p (x)) |
2508 | return IFREE; | |
63de6c74 | 2509 | /* A load with 1 base register, to be further checked. */ |
8c660648 JL |
2510 | if (CONST_BASED_ADDRESS_P (XEXP (x, 0))) |
2511 | return PFREE_CANDIDATE; | |
63de6c74 | 2512 | /* No info on the load, to be further checked. */ |
8c660648 JL |
2513 | return PRISKY_CANDIDATE; |
2514 | } | |
2515 | else | |
2516 | { | |
6f7d635c | 2517 | const char *fmt; |
8c660648 JL |
2518 | int i, insn_class = TRAP_FREE; |
2519 | ||
63de6c74 | 2520 | /* Neither store nor load, check if it may cause a trap. */ |
8c660648 JL |
2521 | if (may_trap_p (x)) |
2522 | return TRAP_RISKY; | |
63de6c74 | 2523 | /* Recursive step: walk the insn... */ |
8c660648 JL |
2524 | fmt = GET_RTX_FORMAT (code); |
2525 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
2526 | { | |
2527 | if (fmt[i] == 'e') | |
2528 | { | |
2529 | int tmp_class = may_trap_exp (XEXP (x, i), is_store); | |
2530 | insn_class = WORST_CLASS (insn_class, tmp_class); | |
2531 | } | |
2532 | else if (fmt[i] == 'E') | |
2533 | { | |
2534 | int j; | |
2535 | for (j = 0; j < XVECLEN (x, i); j++) | |
2536 | { | |
2537 | int tmp_class = may_trap_exp (XVECEXP (x, i, j), is_store); | |
2538 | insn_class = WORST_CLASS (insn_class, tmp_class); | |
2539 | if (insn_class == TRAP_RISKY || insn_class == IRISKY) | |
2540 | break; | |
2541 | } | |
2542 | } | |
2543 | if (insn_class == TRAP_RISKY || insn_class == IRISKY) | |
2544 | break; | |
2545 | } | |
2546 | return insn_class; | |
2547 | } | |
2548 | } /* may_trap_exp */ | |
2549 | ||
2550 | ||
2551 | /* Classifies insn for the purpose of verifying that it can be | |
2552 | moved speculatively, by examining it's patterns, returning: | |
2553 | TRAP_RISKY: store, or risky non-load insn (e.g. division by variable). | |
2554 | TRAP_FREE: non-load insn. | |
2555 | IFREE: load from a globaly safe location. | |
2556 | IRISKY: volatile load. | |
2557 | PFREE_CANDIDATE, PRISKY_CANDIDATE: load that need to be checked for | |
2558 | being either PFREE or PRISKY. */ | |
2559 | ||
2560 | static int | |
ac957f13 | 2561 | haifa_classify_insn (insn) |
8c660648 JL |
2562 | rtx insn; |
2563 | { | |
2564 | rtx pat = PATTERN (insn); | |
2565 | int tmp_class = TRAP_FREE; | |
2566 | int insn_class = TRAP_FREE; | |
2567 | enum rtx_code code; | |
2568 | ||
2569 | if (GET_CODE (pat) == PARALLEL) | |
2570 | { | |
2571 | int i, len = XVECLEN (pat, 0); | |
2572 | ||
2573 | for (i = len - 1; i >= 0; i--) | |
2574 | { | |
2575 | code = GET_CODE (XVECEXP (pat, 0, i)); | |
2576 | switch (code) | |
2577 | { | |
2578 | case CLOBBER: | |
63de6c74 | 2579 | /* Test if it is a 'store'. */ |
8c660648 JL |
2580 | tmp_class = may_trap_exp (XEXP (XVECEXP (pat, 0, i), 0), 1); |
2581 | break; | |
2582 | case SET: | |
63de6c74 | 2583 | /* Test if it is a store. */ |
8c660648 JL |
2584 | tmp_class = may_trap_exp (SET_DEST (XVECEXP (pat, 0, i)), 1); |
2585 | if (tmp_class == TRAP_RISKY) | |
2586 | break; | |
63de6c74 | 2587 | /* Test if it is a load. */ |
8c660648 JL |
2588 | tmp_class = |
2589 | WORST_CLASS (tmp_class, | |
2590 | may_trap_exp (SET_SRC (XVECEXP (pat, 0, i)), 0)); | |
e0cd0770 JC |
2591 | break; |
2592 | case TRAP_IF: | |
2593 | tmp_class = TRAP_RISKY; | |
2594 | break; | |
8c660648 JL |
2595 | default:; |
2596 | } | |
2597 | insn_class = WORST_CLASS (insn_class, tmp_class); | |
2598 | if (insn_class == TRAP_RISKY || insn_class == IRISKY) | |
2599 | break; | |
2600 | } | |
2601 | } | |
2602 | else | |
2603 | { | |
2604 | code = GET_CODE (pat); | |
2605 | switch (code) | |
2606 | { | |
2607 | case CLOBBER: | |
63de6c74 | 2608 | /* Test if it is a 'store'. */ |
8c660648 JL |
2609 | tmp_class = may_trap_exp (XEXP (pat, 0), 1); |
2610 | break; | |
2611 | case SET: | |
63de6c74 | 2612 | /* Test if it is a store. */ |
8c660648 JL |
2613 | tmp_class = may_trap_exp (SET_DEST (pat), 1); |
2614 | if (tmp_class == TRAP_RISKY) | |
2615 | break; | |
63de6c74 | 2616 | /* Test if it is a load. */ |
8c660648 JL |
2617 | tmp_class = |
2618 | WORST_CLASS (tmp_class, | |
2619 | may_trap_exp (SET_SRC (pat), 0)); | |
e0cd0770 JC |
2620 | break; |
2621 | case TRAP_IF: | |
2622 | tmp_class = TRAP_RISKY; | |
2623 | break; | |
8c660648 JL |
2624 | default:; |
2625 | } | |
2626 | insn_class = tmp_class; | |
2627 | } | |
2628 | ||
2629 | return insn_class; | |
2630 | ||
ac957f13 | 2631 | } /* haifa_classify_insn */ |
8c660648 JL |
2632 | |
2633 | /* Return 1 if load_insn is prisky (i.e. if load_insn is fed by | |
2634 | a load moved speculatively, or if load_insn is protected by | |
2635 | a compare on load_insn's address). */ | |
2636 | ||
2637 | static int | |
2638 | is_prisky (load_insn, bb_src, bb_trg) | |
2639 | rtx load_insn; | |
2640 | int bb_src, bb_trg; | |
2641 | { | |
2642 | if (FED_BY_SPEC_LOAD (load_insn)) | |
2643 | return 1; | |
2644 | ||
2645 | if (LOG_LINKS (load_insn) == NULL) | |
63de6c74 | 2646 | /* Dependence may 'hide' out of the region. */ |
8c660648 JL |
2647 | return 1; |
2648 | ||
2649 | if (is_conditionally_protected (load_insn, bb_src, bb_trg)) | |
2650 | return 1; | |
2651 | ||
2652 | return 0; | |
2653 | } /* is_prisky */ | |
2654 | ||
2655 | /* Insn is a candidate to be moved speculatively from bb_src to bb_trg. | |
2656 | Return 1 if insn is exception-free (and the motion is valid) | |
2657 | and 0 otherwise. */ | |
2658 | ||
2659 | static int | |
2660 | is_exception_free (insn, bb_src, bb_trg) | |
2661 | rtx insn; | |
2662 | int bb_src, bb_trg; | |
2663 | { | |
ac957f13 | 2664 | int insn_class = haifa_classify_insn (insn); |
8c660648 | 2665 | |
63de6c74 | 2666 | /* Handle non-load insns. */ |
8c660648 JL |
2667 | switch (insn_class) |
2668 | { | |
2669 | case TRAP_FREE: | |
2670 | return 1; | |
2671 | case TRAP_RISKY: | |
2672 | return 0; | |
2673 | default:; | |
2674 | } | |
2675 | ||
63de6c74 | 2676 | /* Handle loads. */ |
8c660648 JL |
2677 | if (!flag_schedule_speculative_load) |
2678 | return 0; | |
2679 | IS_LOAD_INSN (insn) = 1; | |
2680 | switch (insn_class) | |
2681 | { | |
2682 | case IFREE: | |
2683 | return (1); | |
2684 | case IRISKY: | |
2685 | return 0; | |
2686 | case PFREE_CANDIDATE: | |
2687 | if (is_pfree (insn, bb_src, bb_trg)) | |
2688 | return 1; | |
63de6c74 | 2689 | /* Don't 'break' here: PFREE-candidate is also PRISKY-candidate. */ |
8c660648 JL |
2690 | case PRISKY_CANDIDATE: |
2691 | if (!flag_schedule_speculative_load_dangerous | |
2692 | || is_prisky (insn, bb_src, bb_trg)) | |
2693 | return 0; | |
2694 | break; | |
2695 | default:; | |
2696 | } | |
2697 | ||
2698 | return flag_schedule_speculative_load_dangerous; | |
2699 | } /* is_exception_free */ | |
2700 | ||
2701 | ||
2702 | /* Process an insn's memory dependencies. There are four kinds of | |
2703 | dependencies: | |
2704 | ||
2705 | (0) read dependence: read follows read | |
2706 | (1) true dependence: read follows write | |
2707 | (2) anti dependence: write follows read | |
2708 | (3) output dependence: write follows write | |
2709 | ||
2710 | We are careful to build only dependencies which actually exist, and | |
2711 | use transitivity to avoid building too many links. */ | |
2712 | \f | |
2713 | /* Return the INSN_LIST containing INSN in LIST, or NULL | |
2714 | if LIST does not contain INSN. */ | |
2715 | ||
cbb13457 | 2716 | HAIFA_INLINE static rtx |
8c660648 JL |
2717 | find_insn_list (insn, list) |
2718 | rtx insn; | |
2719 | rtx list; | |
2720 | { | |
2721 | while (list) | |
2722 | { | |
2723 | if (XEXP (list, 0) == insn) | |
2724 | return list; | |
2725 | list = XEXP (list, 1); | |
2726 | } | |
2727 | return 0; | |
2728 | } | |
2729 | ||
2730 | ||
63de6c74 MH |
2731 | /* Return 1 if the pair (insn, x) is found in (LIST, LIST1), or 0 |
2732 | otherwise. */ | |
8c660648 | 2733 | |
cbb13457 | 2734 | HAIFA_INLINE static char |
8c660648 JL |
2735 | find_insn_mem_list (insn, x, list, list1) |
2736 | rtx insn, x; | |
2737 | rtx list, list1; | |
2738 | { | |
2739 | while (list) | |
2740 | { | |
2741 | if (XEXP (list, 0) == insn | |
2742 | && XEXP (list1, 0) == x) | |
2743 | return 1; | |
2744 | list = XEXP (list, 1); | |
2745 | list1 = XEXP (list1, 1); | |
2746 | } | |
2747 | return 0; | |
2748 | } | |
2749 | ||
2750 | ||
2751 | /* Compute the function units used by INSN. This caches the value | |
2752 | returned by function_units_used. A function unit is encoded as the | |
2753 | unit number if the value is non-negative and the compliment of a | |
2754 | mask if the value is negative. A function unit index is the | |
2755 | non-negative encoding. */ | |
2756 | ||
cbb13457 | 2757 | HAIFA_INLINE static int |
8c660648 JL |
2758 | insn_unit (insn) |
2759 | rtx insn; | |
2760 | { | |
2761 | register int unit = INSN_UNIT (insn); | |
2762 | ||
2763 | if (unit == 0) | |
2764 | { | |
2765 | recog_memoized (insn); | |
2766 | ||
2767 | /* A USE insn, or something else we don't need to understand. | |
2768 | We can't pass these directly to function_units_used because it will | |
2769 | trigger a fatal error for unrecognizable insns. */ | |
2770 | if (INSN_CODE (insn) < 0) | |
2771 | unit = -1; | |
2772 | else | |
2773 | { | |
2774 | unit = function_units_used (insn); | |
2775 | /* Increment non-negative values so we can cache zero. */ | |
2776 | if (unit >= 0) | |
2777 | unit++; | |
2778 | } | |
2779 | /* We only cache 16 bits of the result, so if the value is out of | |
2780 | range, don't cache it. */ | |
2781 | if (FUNCTION_UNITS_SIZE < HOST_BITS_PER_SHORT | |
2782 | || unit >= 0 | |
77f3d48a | 2783 | || (unit & ~((1 << (HOST_BITS_PER_SHORT - 1)) - 1)) == 0) |
8c660648 JL |
2784 | INSN_UNIT (insn) = unit; |
2785 | } | |
2786 | return (unit > 0 ? unit - 1 : unit); | |
2787 | } | |
2788 | ||
2789 | /* Compute the blockage range for executing INSN on UNIT. This caches | |
2790 | the value returned by the blockage_range_function for the unit. | |
2791 | These values are encoded in an int where the upper half gives the | |
2792 | minimum value and the lower half gives the maximum value. */ | |
2793 | ||
cbb13457 | 2794 | HAIFA_INLINE static unsigned int |
8c660648 JL |
2795 | blockage_range (unit, insn) |
2796 | int unit; | |
2797 | rtx insn; | |
2798 | { | |
2799 | unsigned int blockage = INSN_BLOCKAGE (insn); | |
2800 | unsigned int range; | |
2801 | ||
79c9824e | 2802 | if ((int) UNIT_BLOCKED (blockage) != unit + 1) |
8c660648 JL |
2803 | { |
2804 | range = function_units[unit].blockage_range_function (insn); | |
2805 | /* We only cache the blockage range for one unit and then only if | |
2806 | the values fit. */ | |
2807 | if (HOST_BITS_PER_INT >= UNIT_BITS + 2 * BLOCKAGE_BITS) | |
2808 | INSN_BLOCKAGE (insn) = ENCODE_BLOCKAGE (unit + 1, range); | |
2809 | } | |
2810 | else | |
2811 | range = BLOCKAGE_RANGE (blockage); | |
2812 | ||
2813 | return range; | |
2814 | } | |
2815 | ||
2816 | /* A vector indexed by function unit instance giving the last insn to use | |
2817 | the unit. The value of the function unit instance index for unit U | |
2818 | instance I is (U + I * FUNCTION_UNITS_SIZE). */ | |
2819 | static rtx unit_last_insn[FUNCTION_UNITS_SIZE * MAX_MULTIPLICITY]; | |
2820 | ||
2821 | /* A vector indexed by function unit instance giving the minimum time when | |
2822 | the unit will unblock based on the maximum blockage cost. */ | |
2823 | static int unit_tick[FUNCTION_UNITS_SIZE * MAX_MULTIPLICITY]; | |
2824 | ||
2825 | /* A vector indexed by function unit number giving the number of insns | |
2826 | that remain to use the unit. */ | |
2827 | static int unit_n_insns[FUNCTION_UNITS_SIZE]; | |
2828 | ||
2829 | /* Reset the function unit state to the null state. */ | |
2830 | ||
2831 | static void | |
2832 | clear_units () | |
2833 | { | |
2834 | bzero ((char *) unit_last_insn, sizeof (unit_last_insn)); | |
2835 | bzero ((char *) unit_tick, sizeof (unit_tick)); | |
2836 | bzero ((char *) unit_n_insns, sizeof (unit_n_insns)); | |
2837 | } | |
2838 | ||
63de6c74 | 2839 | /* Return the issue-delay of an insn. */ |
8c660648 | 2840 | |
cbb13457 | 2841 | HAIFA_INLINE static int |
8c660648 JL |
2842 | insn_issue_delay (insn) |
2843 | rtx insn; | |
2844 | { | |
8c660648 JL |
2845 | int i, delay = 0; |
2846 | int unit = insn_unit (insn); | |
2847 | ||
63de6c74 | 2848 | /* Efficiency note: in fact, we are working 'hard' to compute a |
8c660648 JL |
2849 | value that was available in md file, and is not available in |
2850 | function_units[] structure. It would be nice to have this | |
2851 | value there, too. */ | |
2852 | if (unit >= 0) | |
2853 | { | |
2854 | if (function_units[unit].blockage_range_function && | |
2855 | function_units[unit].blockage_function) | |
2856 | delay = function_units[unit].blockage_function (insn, insn); | |
2857 | } | |
2858 | else | |
2859 | for (i = 0, unit = ~unit; unit; i++, unit >>= 1) | |
2860 | if ((unit & 1) != 0 && function_units[i].blockage_range_function | |
2861 | && function_units[i].blockage_function) | |
2862 | delay = MAX (delay, function_units[i].blockage_function (insn, insn)); | |
2863 | ||
2864 | return delay; | |
2865 | } | |
2866 | ||
2867 | /* Return the actual hazard cost of executing INSN on the unit UNIT, | |
2868 | instance INSTANCE at time CLOCK if the previous actual hazard cost | |
2869 | was COST. */ | |
2870 | ||
cbb13457 | 2871 | HAIFA_INLINE static int |
8c660648 JL |
2872 | actual_hazard_this_instance (unit, instance, insn, clock, cost) |
2873 | int unit, instance, clock, cost; | |
2874 | rtx insn; | |
2875 | { | |
63de6c74 | 2876 | int tick = unit_tick[instance]; /* Issue time of the last issued insn. */ |
8c660648 JL |
2877 | |
2878 | if (tick - clock > cost) | |
2879 | { | |
2880 | /* The scheduler is operating forward, so unit's last insn is the | |
2881 | executing insn and INSN is the candidate insn. We want a | |
2882 | more exact measure of the blockage if we execute INSN at CLOCK | |
2883 | given when we committed the execution of the unit's last insn. | |
2884 | ||
2885 | The blockage value is given by either the unit's max blockage | |
2886 | constant, blockage range function, or blockage function. Use | |
2887 | the most exact form for the given unit. */ | |
2888 | ||
2889 | if (function_units[unit].blockage_range_function) | |
2890 | { | |
2891 | if (function_units[unit].blockage_function) | |
2892 | tick += (function_units[unit].blockage_function | |
2893 | (unit_last_insn[instance], insn) | |
2894 | - function_units[unit].max_blockage); | |
2895 | else | |
2896 | tick += ((int) MAX_BLOCKAGE_COST (blockage_range (unit, insn)) | |
2897 | - function_units[unit].max_blockage); | |
2898 | } | |
2899 | if (tick - clock > cost) | |
2900 | cost = tick - clock; | |
2901 | } | |
2902 | return cost; | |
2903 | } | |
2904 | ||
2905 | /* Record INSN as having begun execution on the units encoded by UNIT at | |
2906 | time CLOCK. */ | |
2907 | ||
cbb13457 | 2908 | HAIFA_INLINE static void |
8c660648 JL |
2909 | schedule_unit (unit, insn, clock) |
2910 | int unit, clock; | |
2911 | rtx insn; | |
2912 | { | |
2913 | int i; | |
2914 | ||
2915 | if (unit >= 0) | |
2916 | { | |
2917 | int instance = unit; | |
2918 | #if MAX_MULTIPLICITY > 1 | |
2919 | /* Find the first free instance of the function unit and use that | |
2920 | one. We assume that one is free. */ | |
2921 | for (i = function_units[unit].multiplicity - 1; i > 0; i--) | |
2922 | { | |
2923 | if (!actual_hazard_this_instance (unit, instance, insn, clock, 0)) | |
2924 | break; | |
2925 | instance += FUNCTION_UNITS_SIZE; | |
2926 | } | |
2927 | #endif | |
2928 | unit_last_insn[instance] = insn; | |
2929 | unit_tick[instance] = (clock + function_units[unit].max_blockage); | |
2930 | } | |
2931 | else | |
2932 | for (i = 0, unit = ~unit; unit; i++, unit >>= 1) | |
2933 | if ((unit & 1) != 0) | |
2934 | schedule_unit (i, insn, clock); | |
2935 | } | |
2936 | ||
2937 | /* Return the actual hazard cost of executing INSN on the units encoded by | |
2938 | UNIT at time CLOCK if the previous actual hazard cost was COST. */ | |
2939 | ||
cbb13457 | 2940 | HAIFA_INLINE static int |
8c660648 JL |
2941 | actual_hazard (unit, insn, clock, cost) |
2942 | int unit, clock, cost; | |
2943 | rtx insn; | |
2944 | { | |
2945 | int i; | |
2946 | ||
2947 | if (unit >= 0) | |
2948 | { | |
2949 | /* Find the instance of the function unit with the minimum hazard. */ | |
2950 | int instance = unit; | |
2951 | int best_cost = actual_hazard_this_instance (unit, instance, insn, | |
2952 | clock, cost); | |
2953 | int this_cost; | |
2954 | ||
2955 | #if MAX_MULTIPLICITY > 1 | |
2956 | if (best_cost > cost) | |
2957 | { | |
2958 | for (i = function_units[unit].multiplicity - 1; i > 0; i--) | |
2959 | { | |
2960 | instance += FUNCTION_UNITS_SIZE; | |
2961 | this_cost = actual_hazard_this_instance (unit, instance, insn, | |
2962 | clock, cost); | |
2963 | if (this_cost < best_cost) | |
2964 | { | |
2965 | best_cost = this_cost; | |
2966 | if (this_cost <= cost) | |
2967 | break; | |
2968 | } | |
2969 | } | |
2970 | } | |
2971 | #endif | |
2972 | cost = MAX (cost, best_cost); | |
2973 | } | |
2974 | else | |
2975 | for (i = 0, unit = ~unit; unit; i++, unit >>= 1) | |
2976 | if ((unit & 1) != 0) | |
2977 | cost = actual_hazard (i, insn, clock, cost); | |
2978 | ||
2979 | return cost; | |
2980 | } | |
2981 | ||
2982 | /* Return the potential hazard cost of executing an instruction on the | |
2983 | units encoded by UNIT if the previous potential hazard cost was COST. | |
2984 | An insn with a large blockage time is chosen in preference to one | |
2985 | with a smaller time; an insn that uses a unit that is more likely | |
2986 | to be used is chosen in preference to one with a unit that is less | |
2987 | used. We are trying to minimize a subsequent actual hazard. */ | |
2988 | ||
cbb13457 | 2989 | HAIFA_INLINE static int |
8c660648 JL |
2990 | potential_hazard (unit, insn, cost) |
2991 | int unit, cost; | |
2992 | rtx insn; | |
2993 | { | |
2994 | int i, ncost; | |
2995 | unsigned int minb, maxb; | |
2996 | ||
2997 | if (unit >= 0) | |
2998 | { | |
2999 | minb = maxb = function_units[unit].max_blockage; | |
3000 | if (maxb > 1) | |
3001 | { | |
3002 | if (function_units[unit].blockage_range_function) | |
3003 | { | |
3004 | maxb = minb = blockage_range (unit, insn); | |
3005 | maxb = MAX_BLOCKAGE_COST (maxb); | |
3006 | minb = MIN_BLOCKAGE_COST (minb); | |
3007 | } | |
3008 | ||
3009 | if (maxb > 1) | |
3010 | { | |
3011 | /* Make the number of instructions left dominate. Make the | |
3012 | minimum delay dominate the maximum delay. If all these | |
3013 | are the same, use the unit number to add an arbitrary | |
3014 | ordering. Other terms can be added. */ | |
3015 | ncost = minb * 0x40 + maxb; | |
3016 | ncost *= (unit_n_insns[unit] - 1) * 0x1000 + unit; | |
3017 | if (ncost > cost) | |
3018 | cost = ncost; | |
3019 | } | |
3020 | } | |
3021 | } | |
3022 | else | |
3023 | for (i = 0, unit = ~unit; unit; i++, unit >>= 1) | |
3024 | if ((unit & 1) != 0) | |
3025 | cost = potential_hazard (i, insn, cost); | |
3026 | ||
3027 | return cost; | |
3028 | } | |
3029 | ||
3030 | /* Compute cost of executing INSN given the dependence LINK on the insn USED. | |
3031 | This is the number of cycles between instruction issue and | |
3032 | instruction results. */ | |
3033 | ||
cbb13457 | 3034 | HAIFA_INLINE static int |
8c660648 JL |
3035 | insn_cost (insn, link, used) |
3036 | rtx insn, link, used; | |
3037 | { | |
3038 | register int cost = INSN_COST (insn); | |
3039 | ||
3040 | if (cost == 0) | |
3041 | { | |
3042 | recog_memoized (insn); | |
3043 | ||
3044 | /* A USE insn, or something else we don't need to understand. | |
3045 | We can't pass these directly to result_ready_cost because it will | |
3046 | trigger a fatal error for unrecognizable insns. */ | |
3047 | if (INSN_CODE (insn) < 0) | |
3048 | { | |
3049 | INSN_COST (insn) = 1; | |
3050 | return 1; | |
3051 | } | |
3052 | else | |
3053 | { | |
3054 | cost = result_ready_cost (insn); | |
3055 | ||
3056 | if (cost < 1) | |
3057 | cost = 1; | |
3058 | ||
3059 | INSN_COST (insn) = cost; | |
3060 | } | |
3061 | } | |
3062 | ||
63de6c74 | 3063 | /* In this case estimate cost without caring how insn is used. */ |
8c660648 JL |
3064 | if (link == 0 && used == 0) |
3065 | return cost; | |
3066 | ||
3067 | /* A USE insn should never require the value used to be computed. This | |
3068 | allows the computation of a function's result and parameter values to | |
3069 | overlap the return and call. */ | |
3070 | recog_memoized (used); | |
3071 | if (INSN_CODE (used) < 0) | |
3072 | LINK_COST_FREE (link) = 1; | |
3073 | ||
3074 | /* If some dependencies vary the cost, compute the adjustment. Most | |
3075 | commonly, the adjustment is complete: either the cost is ignored | |
3076 | (in the case of an output- or anti-dependence), or the cost is | |
3077 | unchanged. These values are cached in the link as LINK_COST_FREE | |
3078 | and LINK_COST_ZERO. */ | |
3079 | ||
3080 | if (LINK_COST_FREE (link)) | |
197043f5 | 3081 | cost = 0; |
8c660648 JL |
3082 | #ifdef ADJUST_COST |
3083 | else if (!LINK_COST_ZERO (link)) | |
3084 | { | |
3085 | int ncost = cost; | |
3086 | ||
3087 | ADJUST_COST (used, link, insn, ncost); | |
197043f5 RH |
3088 | if (ncost < 1) |
3089 | { | |
3090 | LINK_COST_FREE (link) = 1; | |
3091 | ncost = 0; | |
3092 | } | |
8c660648 JL |
3093 | if (cost == ncost) |
3094 | LINK_COST_ZERO (link) = 1; | |
3095 | cost = ncost; | |
3096 | } | |
3097 | #endif | |
3098 | return cost; | |
3099 | } | |
3100 | ||
3101 | /* Compute the priority number for INSN. */ | |
3102 | ||
3103 | static int | |
3104 | priority (insn) | |
3105 | rtx insn; | |
3106 | { | |
3107 | int this_priority; | |
3108 | rtx link; | |
3109 | ||
3110 | if (GET_RTX_CLASS (GET_CODE (insn)) != 'i') | |
3111 | return 0; | |
3112 | ||
3113 | if ((this_priority = INSN_PRIORITY (insn)) == 0) | |
3114 | { | |
3115 | if (INSN_DEPEND (insn) == 0) | |
3116 | this_priority = insn_cost (insn, 0, 0); | |
3117 | else | |
3118 | for (link = INSN_DEPEND (insn); link; link = XEXP (link, 1)) | |
3119 | { | |
3120 | rtx next; | |
3121 | int next_priority; | |
3122 | ||
6d8ccdbb JL |
3123 | if (RTX_INTEGRATED_P (link)) |
3124 | continue; | |
3125 | ||
8c660648 JL |
3126 | next = XEXP (link, 0); |
3127 | ||
63de6c74 | 3128 | /* Critical path is meaningful in block boundaries only. */ |
8c660648 JL |
3129 | if (INSN_BLOCK (next) != INSN_BLOCK (insn)) |
3130 | continue; | |
3131 | ||
3132 | next_priority = insn_cost (insn, link, next) + priority (next); | |
3133 | if (next_priority > this_priority) | |
3134 | this_priority = next_priority; | |
3135 | } | |
3136 | INSN_PRIORITY (insn) = this_priority; | |
3137 | } | |
3138 | return this_priority; | |
3139 | } | |
3140 | \f | |
3141 | ||
3142 | /* Remove all INSN_LISTs and EXPR_LISTs from the pending lists and add | |
3143 | them to the unused_*_list variables, so that they can be reused. */ | |
3144 | ||
8c660648 JL |
3145 | static void |
3146 | free_pending_lists () | |
3147 | { | |
8c660648 JL |
3148 | if (current_nr_blocks <= 1) |
3149 | { | |
5a4f6418 AM |
3150 | free_INSN_LIST_list (&pending_read_insns); |
3151 | free_INSN_LIST_list (&pending_write_insns); | |
3152 | free_EXPR_LIST_list (&pending_read_mems); | |
3153 | free_EXPR_LIST_list (&pending_write_mems); | |
8c660648 JL |
3154 | } |
3155 | else | |
3156 | { | |
63de6c74 | 3157 | /* Interblock scheduling. */ |
8c660648 JL |
3158 | int bb; |
3159 | ||
3160 | for (bb = 0; bb < current_nr_blocks; bb++) | |
3161 | { | |
5a4f6418 AM |
3162 | free_INSN_LIST_list (&bb_pending_read_insns[bb]); |
3163 | free_INSN_LIST_list (&bb_pending_write_insns[bb]); | |
3164 | free_EXPR_LIST_list (&bb_pending_read_mems[bb]); | |
3165 | free_EXPR_LIST_list (&bb_pending_write_mems[bb]); | |
8c660648 JL |
3166 | } |
3167 | } | |
3168 | } | |
3169 | ||
3170 | /* Add an INSN and MEM reference pair to a pending INSN_LIST and MEM_LIST. | |
3171 | The MEM is a memory reference contained within INSN, which we are saving | |
3172 | so that we can do memory aliasing on it. */ | |
3173 | ||
3174 | static void | |
3175 | add_insn_mem_dependence (insn_list, mem_list, insn, mem) | |
3176 | rtx *insn_list, *mem_list, insn, mem; | |
3177 | { | |
3178 | register rtx link; | |
3179 | ||
ebb7b10b | 3180 | link = alloc_INSN_LIST (insn, *insn_list); |
8c660648 JL |
3181 | *insn_list = link; |
3182 | ||
ebb7b10b | 3183 | link = alloc_EXPR_LIST (VOIDmode, mem, *mem_list); |
8c660648 JL |
3184 | *mem_list = link; |
3185 | ||
3186 | pending_lists_length++; | |
3187 | } | |
3188 | \f | |
3189 | ||
3190 | /* Make a dependency between every memory reference on the pending lists | |
3191 | and INSN, thus flushing the pending lists. If ONLY_WRITE, don't flush | |
3192 | the read list. */ | |
3193 | ||
3194 | static void | |
3195 | flush_pending_lists (insn, only_write) | |
3196 | rtx insn; | |
3197 | int only_write; | |
3198 | { | |
3199 | rtx u; | |
3200 | rtx link; | |
3201 | ||
3202 | while (pending_read_insns && ! only_write) | |
3203 | { | |
3204 | add_dependence (insn, XEXP (pending_read_insns, 0), REG_DEP_ANTI); | |
3205 | ||
3206 | link = pending_read_insns; | |
3207 | pending_read_insns = XEXP (pending_read_insns, 1); | |
5a4f6418 | 3208 | free_INSN_LIST_node (link); |
8c660648 JL |
3209 | |
3210 | link = pending_read_mems; | |
3211 | pending_read_mems = XEXP (pending_read_mems, 1); | |
5a4f6418 | 3212 | free_EXPR_LIST_node (link); |
8c660648 JL |
3213 | } |
3214 | while (pending_write_insns) | |
3215 | { | |
3216 | add_dependence (insn, XEXP (pending_write_insns, 0), REG_DEP_ANTI); | |
3217 | ||
3218 | link = pending_write_insns; | |
3219 | pending_write_insns = XEXP (pending_write_insns, 1); | |
5a4f6418 | 3220 | free_INSN_LIST_node (link); |
8c660648 JL |
3221 | |
3222 | link = pending_write_mems; | |
3223 | pending_write_mems = XEXP (pending_write_mems, 1); | |
5a4f6418 | 3224 | free_EXPR_LIST_node (link); |
8c660648 JL |
3225 | } |
3226 | pending_lists_length = 0; | |
3227 | ||
63de6c74 | 3228 | /* last_pending_memory_flush is now a list of insns. */ |
8c660648 JL |
3229 | for (u = last_pending_memory_flush; u; u = XEXP (u, 1)) |
3230 | add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI); | |
3231 | ||
5a4f6418 | 3232 | free_INSN_LIST_list (&last_pending_memory_flush); |
ebb7b10b | 3233 | last_pending_memory_flush = alloc_INSN_LIST (insn, NULL_RTX); |
8c660648 JL |
3234 | } |
3235 | ||
355fca3e AB |
3236 | /* Analyze a single SET, CLOBBER, PRE_DEC, POST_DEC, PRE_INC or POST_INC |
3237 | rtx, X, creating all dependencies generated by the write to the | |
3238 | destination of X, and reads of everything mentioned. */ | |
8c660648 JL |
3239 | |
3240 | static void | |
3241 | sched_analyze_1 (x, insn) | |
3242 | rtx x; | |
3243 | rtx insn; | |
3244 | { | |
3245 | register int regno; | |
355fca3e | 3246 | register rtx dest = XEXP (x, 0); |
28c95eff | 3247 | enum rtx_code code = GET_CODE (x); |
8c660648 JL |
3248 | |
3249 | if (dest == 0) | |
3250 | return; | |
3251 | ||
c0222c21 DM |
3252 | if (GET_CODE (dest) == PARALLEL |
3253 | && GET_MODE (dest) == BLKmode) | |
3254 | { | |
3255 | register int i; | |
3256 | for (i = XVECLEN (dest, 0) - 1; i >= 0; i--) | |
3257 | sched_analyze_1 (XVECEXP (dest, 0, i), insn); | |
3258 | if (GET_CODE (x) == SET) | |
3259 | sched_analyze_2 (SET_SRC (x), insn); | |
3260 | return; | |
3261 | } | |
3262 | ||
8c660648 JL |
3263 | while (GET_CODE (dest) == STRICT_LOW_PART || GET_CODE (dest) == SUBREG |
3264 | || GET_CODE (dest) == ZERO_EXTRACT || GET_CODE (dest) == SIGN_EXTRACT) | |
3265 | { | |
3266 | if (GET_CODE (dest) == ZERO_EXTRACT || GET_CODE (dest) == SIGN_EXTRACT) | |
3267 | { | |
3268 | /* The second and third arguments are values read by this insn. */ | |
3269 | sched_analyze_2 (XEXP (dest, 1), insn); | |
3270 | sched_analyze_2 (XEXP (dest, 2), insn); | |
3271 | } | |
355fca3e | 3272 | dest = XEXP (dest, 0); |
8c660648 JL |
3273 | } |
3274 | ||
3275 | if (GET_CODE (dest) == REG) | |
3276 | { | |
3277 | register int i; | |
3278 | ||
3279 | regno = REGNO (dest); | |
3280 | ||
3281 | /* A hard reg in a wide mode may really be multiple registers. | |
3282 | If so, mark all of them just like the first. */ | |
3283 | if (regno < FIRST_PSEUDO_REGISTER) | |
3284 | { | |
3285 | i = HARD_REGNO_NREGS (regno, GET_MODE (dest)); | |
3286 | while (--i >= 0) | |
3287 | { | |
3288 | rtx u; | |
3289 | ||
3290 | for (u = reg_last_uses[regno + i]; u; u = XEXP (u, 1)) | |
3291 | add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI); | |
8c660648 JL |
3292 | |
3293 | for (u = reg_last_sets[regno + i]; u; u = XEXP (u, 1)) | |
3294 | add_dependence (insn, XEXP (u, 0), REG_DEP_OUTPUT); | |
3295 | ||
63de6c74 MH |
3296 | /* Clobbers need not be ordered with respect to one |
3297 | another, but sets must be ordered with respect to a | |
3298 | pending clobber. */ | |
28c95eff RH |
3299 | if (code == SET) |
3300 | { | |
5a4f6418 | 3301 | free_INSN_LIST_list (®_last_uses[regno + i]); |
28c95eff RH |
3302 | for (u = reg_last_clobbers[regno + i]; u; u = XEXP (u, 1)) |
3303 | add_dependence (insn, XEXP (u, 0), REG_DEP_OUTPUT); | |
3304 | SET_REGNO_REG_SET (reg_pending_sets, regno + i); | |
3305 | } | |
3306 | else | |
3307 | SET_REGNO_REG_SET (reg_pending_clobbers, regno + i); | |
8c660648 | 3308 | |
28c95eff RH |
3309 | /* Function calls clobber all call_used regs. */ |
3310 | if (global_regs[regno + i] | |
3311 | || (code == SET && call_used_regs[regno + i])) | |
8c660648 JL |
3312 | for (u = last_function_call; u; u = XEXP (u, 1)) |
3313 | add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI); | |
3314 | } | |
3315 | } | |
3316 | else | |
3317 | { | |
3318 | rtx u; | |
3319 | ||
3320 | for (u = reg_last_uses[regno]; u; u = XEXP (u, 1)) | |
3321 | add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI); | |
8c660648 JL |
3322 | |
3323 | for (u = reg_last_sets[regno]; u; u = XEXP (u, 1)) | |
3324 | add_dependence (insn, XEXP (u, 0), REG_DEP_OUTPUT); | |
3325 | ||
28c95eff | 3326 | if (code == SET) |
7399257b | 3327 | { |
5a4f6418 | 3328 | free_INSN_LIST_list (®_last_uses[regno]); |
7399257b RH |
3329 | for (u = reg_last_clobbers[regno]; u; u = XEXP (u, 1)) |
3330 | add_dependence (insn, XEXP (u, 0), REG_DEP_OUTPUT); | |
3331 | SET_REGNO_REG_SET (reg_pending_sets, regno); | |
3332 | } | |
28c95eff RH |
3333 | else |
3334 | SET_REGNO_REG_SET (reg_pending_clobbers, regno); | |
8c660648 JL |
3335 | |
3336 | /* Pseudos that are REG_EQUIV to something may be replaced | |
3337 | by that during reloading. We need only add dependencies for | |
3338 | the address in the REG_EQUIV note. */ | |
3339 | if (!reload_completed | |
3340 | && reg_known_equiv_p[regno] | |
3341 | && GET_CODE (reg_known_value[regno]) == MEM) | |
3342 | sched_analyze_2 (XEXP (reg_known_value[regno], 0), insn); | |
3343 | ||
3344 | /* Don't let it cross a call after scheduling if it doesn't | |
3345 | already cross one. */ | |
3346 | ||
3347 | if (REG_N_CALLS_CROSSED (regno) == 0) | |
3348 | for (u = last_function_call; u; u = XEXP (u, 1)) | |
3349 | add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI); | |
3350 | } | |
3351 | } | |
3352 | else if (GET_CODE (dest) == MEM) | |
3353 | { | |
3354 | /* Writing memory. */ | |
3355 | ||
3356 | if (pending_lists_length > 32) | |
3357 | { | |
3358 | /* Flush all pending reads and writes to prevent the pending lists | |
3359 | from getting any larger. Insn scheduling runs too slowly when | |
3360 | these lists get long. The number 32 was chosen because it | |
3361 | seems like a reasonable number. When compiling GCC with itself, | |
3362 | this flush occurs 8 times for sparc, and 10 times for m88k using | |
3363 | the number 32. */ | |
3364 | flush_pending_lists (insn, 0); | |
3365 | } | |
3366 | else | |
3367 | { | |
3368 | rtx u; | |
3369 | rtx pending, pending_mem; | |
3370 | ||
3371 | pending = pending_read_insns; | |
3372 | pending_mem = pending_read_mems; | |
3373 | while (pending) | |
3374 | { | |
87373fba RH |
3375 | if (anti_dependence (XEXP (pending_mem, 0), dest)) |
3376 | add_dependence (insn, XEXP (pending, 0), REG_DEP_ANTI); | |
8c660648 JL |
3377 | |
3378 | pending = XEXP (pending, 1); | |
3379 | pending_mem = XEXP (pending_mem, 1); | |
3380 | } | |
3381 | ||
3382 | pending = pending_write_insns; | |
3383 | pending_mem = pending_write_mems; | |
3384 | while (pending) | |
3385 | { | |
87373fba RH |
3386 | if (output_dependence (XEXP (pending_mem, 0), dest)) |
3387 | add_dependence (insn, XEXP (pending, 0), REG_DEP_OUTPUT); | |
8c660648 JL |
3388 | |
3389 | pending = XEXP (pending, 1); | |
3390 | pending_mem = XEXP (pending_mem, 1); | |
3391 | } | |
3392 | ||
3393 | for (u = last_pending_memory_flush; u; u = XEXP (u, 1)) | |
3394 | add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI); | |
3395 | ||
3396 | add_insn_mem_dependence (&pending_write_insns, &pending_write_mems, | |
3397 | insn, dest); | |
3398 | } | |
3399 | sched_analyze_2 (XEXP (dest, 0), insn); | |
3400 | } | |
3401 | ||
3402 | /* Analyze reads. */ | |
3403 | if (GET_CODE (x) == SET) | |
3404 | sched_analyze_2 (SET_SRC (x), insn); | |
3405 | } | |
3406 | ||
3407 | /* Analyze the uses of memory and registers in rtx X in INSN. */ | |
3408 | ||
3409 | static void | |
3410 | sched_analyze_2 (x, insn) | |
3411 | rtx x; | |
3412 | rtx insn; | |
3413 | { | |
3414 | register int i; | |
3415 | register int j; | |
3416 | register enum rtx_code code; | |
6f7d635c | 3417 | register const char *fmt; |
8c660648 JL |
3418 | |
3419 | if (x == 0) | |
3420 | return; | |
3421 | ||
3422 | code = GET_CODE (x); | |
3423 | ||
3424 | switch (code) | |
3425 | { | |
3426 | case CONST_INT: | |
3427 | case CONST_DOUBLE: | |
3428 | case SYMBOL_REF: | |
3429 | case CONST: | |
3430 | case LABEL_REF: | |
3431 | /* Ignore constants. Note that we must handle CONST_DOUBLE here | |
3432 | because it may have a cc0_rtx in its CONST_DOUBLE_CHAIN field, but | |
3433 | this does not mean that this insn is using cc0. */ | |
3434 | return; | |
3435 | ||
3436 | #ifdef HAVE_cc0 | |
3437 | case CC0: | |
3438 | { | |
3439 | rtx link, prev; | |
3440 | ||
3441 | /* User of CC0 depends on immediately preceding insn. */ | |
3442 | SCHED_GROUP_P (insn) = 1; | |
3443 | ||
3444 | /* There may be a note before this insn now, but all notes will | |
3445 | be removed before we actually try to schedule the insns, so | |
3446 | it won't cause a problem later. We must avoid it here though. */ | |
3447 | prev = prev_nonnote_insn (insn); | |
3448 | ||
3449 | /* Make a copy of all dependencies on the immediately previous insn, | |
3450 | and add to this insn. This is so that all the dependencies will | |
3451 | apply to the group. Remove an explicit dependence on this insn | |
3452 | as SCHED_GROUP_P now represents it. */ | |
3453 | ||
3454 | if (find_insn_list (prev, LOG_LINKS (insn))) | |
3455 | remove_dependence (insn, prev); | |
3456 | ||
3457 | for (link = LOG_LINKS (prev); link; link = XEXP (link, 1)) | |
3458 | add_dependence (insn, XEXP (link, 0), REG_NOTE_KIND (link)); | |
3459 | ||
3460 | return; | |
3461 | } | |
3462 | #endif | |
3463 | ||
3464 | case REG: | |
3465 | { | |
3466 | rtx u; | |
3467 | int regno = REGNO (x); | |
3468 | if (regno < FIRST_PSEUDO_REGISTER) | |
3469 | { | |
3470 | int i; | |
3471 | ||
3472 | i = HARD_REGNO_NREGS (regno, GET_MODE (x)); | |
3473 | while (--i >= 0) | |
3474 | { | |
3475 | reg_last_uses[regno + i] | |
ebb7b10b | 3476 | = alloc_INSN_LIST (insn, reg_last_uses[regno + i]); |
8c660648 JL |
3477 | |
3478 | for (u = reg_last_sets[regno + i]; u; u = XEXP (u, 1)) | |
3479 | add_dependence (insn, XEXP (u, 0), 0); | |
3480 | ||
28c95eff RH |
3481 | /* ??? This should never happen. */ |
3482 | for (u = reg_last_clobbers[regno + i]; u; u = XEXP (u, 1)) | |
3483 | add_dependence (insn, XEXP (u, 0), 0); | |
3484 | ||
8c660648 JL |
3485 | if ((call_used_regs[regno + i] || global_regs[regno + i])) |
3486 | /* Function calls clobber all call_used regs. */ | |
3487 | for (u = last_function_call; u; u = XEXP (u, 1)) | |
3488 | add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI); | |
3489 | } | |
3490 | } | |
3491 | else | |
3492 | { | |
63de6c74 MH |
3493 | reg_last_uses[regno] = alloc_INSN_LIST (insn, |
3494 | reg_last_uses[regno]); | |
8c660648 JL |
3495 | |
3496 | for (u = reg_last_sets[regno]; u; u = XEXP (u, 1)) | |
3497 | add_dependence (insn, XEXP (u, 0), 0); | |
3498 | ||
28c95eff RH |
3499 | /* ??? This should never happen. */ |
3500 | for (u = reg_last_clobbers[regno]; u; u = XEXP (u, 1)) | |
3501 | add_dependence (insn, XEXP (u, 0), 0); | |
3502 | ||
8c660648 JL |
3503 | /* Pseudos that are REG_EQUIV to something may be replaced |
3504 | by that during reloading. We need only add dependencies for | |
3505 | the address in the REG_EQUIV note. */ | |
3506 | if (!reload_completed | |
3507 | && reg_known_equiv_p[regno] | |
3508 | && GET_CODE (reg_known_value[regno]) == MEM) | |
3509 | sched_analyze_2 (XEXP (reg_known_value[regno], 0), insn); | |
3510 | ||
3511 | /* If the register does not already cross any calls, then add this | |
3512 | insn to the sched_before_next_call list so that it will still | |
3513 | not cross calls after scheduling. */ | |
3514 | if (REG_N_CALLS_CROSSED (regno) == 0) | |
3515 | add_dependence (sched_before_next_call, insn, REG_DEP_ANTI); | |
3516 | } | |
3517 | return; | |
3518 | } | |
3519 | ||
3520 | case MEM: | |
3521 | { | |
3522 | /* Reading memory. */ | |
3523 | rtx u; | |
3524 | rtx pending, pending_mem; | |
3525 | ||
3526 | pending = pending_read_insns; | |
3527 | pending_mem = pending_read_mems; | |
3528 | while (pending) | |
3529 | { | |
87373fba RH |
3530 | if (read_dependence (XEXP (pending_mem, 0), x)) |
3531 | add_dependence (insn, XEXP (pending, 0), REG_DEP_ANTI); | |
8c660648 JL |
3532 | |
3533 | pending = XEXP (pending, 1); | |
3534 | pending_mem = XEXP (pending_mem, 1); | |
3535 | } | |
3536 | ||
3537 | pending = pending_write_insns; | |
3538 | pending_mem = pending_write_mems; | |
3539 | while (pending) | |
3540 | { | |
87373fba RH |
3541 | if (true_dependence (XEXP (pending_mem, 0), VOIDmode, |
3542 | x, rtx_varies_p)) | |
3543 | add_dependence (insn, XEXP (pending, 0), 0); | |
8c660648 JL |
3544 | |
3545 | pending = XEXP (pending, 1); | |
3546 | pending_mem = XEXP (pending_mem, 1); | |
3547 | } | |
3548 | ||
3549 | for (u = last_pending_memory_flush; u; u = XEXP (u, 1)) | |
3550 | add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI); | |
3551 | ||
3552 | /* Always add these dependencies to pending_reads, since | |
3553 | this insn may be followed by a write. */ | |
3554 | add_insn_mem_dependence (&pending_read_insns, &pending_read_mems, | |
3555 | insn, x); | |
3556 | ||
3557 | /* Take advantage of tail recursion here. */ | |
3558 | sched_analyze_2 (XEXP (x, 0), insn); | |
3559 | return; | |
3560 | } | |
3561 | ||
e0cd0770 JC |
3562 | /* Force pending stores to memory in case a trap handler needs them. */ |
3563 | case TRAP_IF: | |
3564 | flush_pending_lists (insn, 1); | |
3565 | break; | |
3566 | ||
8c660648 JL |
3567 | case ASM_OPERANDS: |
3568 | case ASM_INPUT: | |
3569 | case UNSPEC_VOLATILE: | |
8c660648 JL |
3570 | { |
3571 | rtx u; | |
3572 | ||
3573 | /* Traditional and volatile asm instructions must be considered to use | |
3574 | and clobber all hard registers, all pseudo-registers and all of | |
3575 | memory. So must TRAP_IF and UNSPEC_VOLATILE operations. | |
3576 | ||
3577 | Consider for instance a volatile asm that changes the fpu rounding | |
3578 | mode. An insn should not be moved across this even if it only uses | |
3579 | pseudo-regs because it might give an incorrectly rounded result. */ | |
3580 | if (code != ASM_OPERANDS || MEM_VOLATILE_P (x)) | |
3581 | { | |
3582 | int max_reg = max_reg_num (); | |
3583 | for (i = 0; i < max_reg; i++) | |
3584 | { | |
3585 | for (u = reg_last_uses[i]; u; u = XEXP (u, 1)) | |
3586 | add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI); | |
5a4f6418 | 3587 | free_INSN_LIST_list (®_last_uses[i]); |
8c660648 | 3588 | |
8c660648 JL |
3589 | for (u = reg_last_sets[i]; u; u = XEXP (u, 1)) |
3590 | add_dependence (insn, XEXP (u, 0), 0); | |
28c95eff RH |
3591 | |
3592 | for (u = reg_last_clobbers[i]; u; u = XEXP (u, 1)) | |
3593 | add_dependence (insn, XEXP (u, 0), 0); | |
8c660648 JL |
3594 | } |
3595 | reg_pending_sets_all = 1; | |
3596 | ||
3597 | flush_pending_lists (insn, 0); | |
3598 | } | |
3599 | ||
3600 | /* For all ASM_OPERANDS, we must traverse the vector of input operands. | |
3601 | We can not just fall through here since then we would be confused | |
3602 | by the ASM_INPUT rtx inside ASM_OPERANDS, which do not indicate | |
3603 | traditional asms unlike their normal usage. */ | |
3604 | ||
3605 | if (code == ASM_OPERANDS) | |
3606 | { | |
3607 | for (j = 0; j < ASM_OPERANDS_INPUT_LENGTH (x); j++) | |
3608 | sched_analyze_2 (ASM_OPERANDS_INPUT (x, j), insn); | |
3609 | return; | |
3610 | } | |
3611 | break; | |
3612 | } | |
3613 | ||
3614 | case PRE_DEC: | |
3615 | case POST_DEC: | |
3616 | case PRE_INC: | |
3617 | case POST_INC: | |
3618 | /* These both read and modify the result. We must handle them as writes | |
3619 | to get proper dependencies for following instructions. We must handle | |
3620 | them as reads to get proper dependencies from this to previous | |
3621 | instructions. Thus we need to pass them to both sched_analyze_1 | |
3622 | and sched_analyze_2. We must call sched_analyze_2 first in order | |
3623 | to get the proper antecedent for the read. */ | |
3624 | sched_analyze_2 (XEXP (x, 0), insn); | |
3625 | sched_analyze_1 (x, insn); | |
3626 | return; | |
5835e573 KG |
3627 | |
3628 | default: | |
3629 | break; | |
8c660648 JL |
3630 | } |
3631 | ||
3632 | /* Other cases: walk the insn. */ | |
3633 | fmt = GET_RTX_FORMAT (code); | |
3634 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
3635 | { | |
3636 | if (fmt[i] == 'e') | |
3637 | sched_analyze_2 (XEXP (x, i), insn); | |
3638 | else if (fmt[i] == 'E') | |
3639 | for (j = 0; j < XVECLEN (x, i); j++) | |
3640 | sched_analyze_2 (XVECEXP (x, i, j), insn); | |
3641 | } | |
3642 | } | |
3643 | ||
3644 | /* Analyze an INSN with pattern X to find all dependencies. */ | |
3645 | ||
3646 | static void | |
3647 | sched_analyze_insn (x, insn, loop_notes) | |
3648 | rtx x, insn; | |
3649 | rtx loop_notes; | |
3650 | { | |
3651 | register RTX_CODE code = GET_CODE (x); | |
3652 | rtx link; | |
3653 | int maxreg = max_reg_num (); | |
3654 | int i; | |
3655 | ||
3656 | if (code == SET || code == CLOBBER) | |
3657 | sched_analyze_1 (x, insn); | |
3658 | else if (code == PARALLEL) | |
3659 | { | |
3660 | register int i; | |
3661 | for (i = XVECLEN (x, 0) - 1; i >= 0; i--) | |
3662 | { | |
3663 | code = GET_CODE (XVECEXP (x, 0, i)); | |
3664 | if (code == SET || code == CLOBBER) | |
3665 | sched_analyze_1 (XVECEXP (x, 0, i), insn); | |
3666 | else | |
3667 | sched_analyze_2 (XVECEXP (x, 0, i), insn); | |
3668 | } | |
3669 | } | |
3670 | else | |
3671 | sched_analyze_2 (x, insn); | |
3672 | ||
3673 | /* Mark registers CLOBBERED or used by called function. */ | |
3674 | if (GET_CODE (insn) == CALL_INSN) | |
3675 | for (link = CALL_INSN_FUNCTION_USAGE (insn); link; link = XEXP (link, 1)) | |
3676 | { | |
3677 | if (GET_CODE (XEXP (link, 0)) == CLOBBER) | |
3678 | sched_analyze_1 (XEXP (link, 0), insn); | |
3679 | else | |
3680 | sched_analyze_2 (XEXP (link, 0), insn); | |
3681 | } | |
3682 | ||
1f1ed00c JL |
3683 | /* If there is a {LOOP,EHREGION}_{BEG,END} note in the middle of a basic |
3684 | block, then we must be sure that no instructions are scheduled across it. | |
8c660648 JL |
3685 | Otherwise, the reg_n_refs info (which depends on loop_depth) would |
3686 | become incorrect. */ | |
3687 | ||
3688 | if (loop_notes) | |
3689 | { | |
3690 | int max_reg = max_reg_num (); | |
1f1ed00c | 3691 | int schedule_barrier_found = 0; |
8c660648 JL |
3692 | rtx link; |
3693 | ||
1f1ed00c JL |
3694 | /* Update loop_notes with any notes from this insn. Also determine |
3695 | if any of the notes on the list correspond to instruction scheduling | |
3696 | barriers (loop, eh & setjmp notes, but not range notes. */ | |
8c660648 JL |
3697 | link = loop_notes; |
3698 | while (XEXP (link, 1)) | |
1f1ed00c | 3699 | { |
54c3cf4b JL |
3700 | if (INTVAL (XEXP (link, 0)) == NOTE_INSN_LOOP_BEG |
3701 | || INTVAL (XEXP (link, 0)) == NOTE_INSN_LOOP_END | |
3702 | || INTVAL (XEXP (link, 0)) == NOTE_INSN_EH_REGION_BEG | |
3703 | || INTVAL (XEXP (link, 0)) == NOTE_INSN_EH_REGION_END | |
3704 | || INTVAL (XEXP (link, 0)) == NOTE_INSN_SETJMP) | |
1f1ed00c JL |
3705 | schedule_barrier_found = 1; |
3706 | ||
3707 | link = XEXP (link, 1); | |
3708 | } | |
8c660648 JL |
3709 | XEXP (link, 1) = REG_NOTES (insn); |
3710 | REG_NOTES (insn) = loop_notes; | |
1f1ed00c JL |
3711 | |
3712 | /* Add dependencies if a scheduling barrier was found. */ | |
3713 | if (schedule_barrier_found) | |
3714 | { | |
3715 | for (i = 0; i < max_reg; i++) | |
3716 | { | |
3717 | rtx u; | |
3718 | for (u = reg_last_uses[i]; u; u = XEXP (u, 1)) | |
3719 | add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI); | |
5a4f6418 | 3720 | free_INSN_LIST_list (®_last_uses[i]); |
1f1ed00c | 3721 | |
1f1ed00c JL |
3722 | for (u = reg_last_sets[i]; u; u = XEXP (u, 1)) |
3723 | add_dependence (insn, XEXP (u, 0), 0); | |
28c95eff RH |
3724 | |
3725 | for (u = reg_last_clobbers[i]; u; u = XEXP (u, 1)) | |
3726 | add_dependence (insn, XEXP (u, 0), 0); | |
1f1ed00c JL |
3727 | } |
3728 | reg_pending_sets_all = 1; | |
3729 | ||
3730 | flush_pending_lists (insn, 0); | |
3731 | } | |
3732 | ||
8c660648 JL |
3733 | } |
3734 | ||
63de6c74 | 3735 | /* Accumulate clobbers until the next set so that it will be output dependent |
28c95eff | 3736 | on all of them. At the next set we can clear the clobber list, since |
63de6c74 | 3737 | subsequent sets will be output dependent on it. */ |
8c660648 JL |
3738 | EXECUTE_IF_SET_IN_REG_SET (reg_pending_sets, 0, i, |
3739 | { | |
5a4f6418 AM |
3740 | free_INSN_LIST_list (®_last_sets[i]); |
3741 | free_INSN_LIST_list (®_last_clobbers[i]); | |
8c660648 | 3742 | reg_last_sets[i] |
ebb7b10b | 3743 | = alloc_INSN_LIST (insn, NULL_RTX); |
8c660648 | 3744 | }); |
28c95eff RH |
3745 | EXECUTE_IF_SET_IN_REG_SET (reg_pending_clobbers, 0, i, |
3746 | { | |
3747 | reg_last_clobbers[i] | |
63de6c74 MH |
3748 | = alloc_INSN_LIST (insn, |
3749 | reg_last_clobbers[i]); | |
28c95eff | 3750 | }); |
8c660648 | 3751 | CLEAR_REG_SET (reg_pending_sets); |
28c95eff | 3752 | CLEAR_REG_SET (reg_pending_clobbers); |
8c660648 JL |
3753 | |
3754 | if (reg_pending_sets_all) | |
3755 | { | |
3756 | for (i = 0; i < maxreg; i++) | |
ebb7b10b | 3757 | { |
5a4f6418 | 3758 | free_INSN_LIST_list (®_last_sets[i]); |
ebb7b10b RH |
3759 | reg_last_sets[i] = alloc_INSN_LIST (insn, NULL_RTX); |
3760 | } | |
8c660648 JL |
3761 | |
3762 | reg_pending_sets_all = 0; | |
3763 | } | |
3764 | ||
3765 | /* Handle function calls and function returns created by the epilogue | |
3766 | threading code. */ | |
3767 | if (GET_CODE (insn) == CALL_INSN || GET_CODE (insn) == JUMP_INSN) | |
3768 | { | |
3769 | rtx dep_insn; | |
3770 | rtx prev_dep_insn; | |
3771 | ||
3772 | /* When scheduling instructions, we make sure calls don't lose their | |
3773 | accompanying USE insns by depending them one on another in order. | |
3774 | ||
3775 | Also, we must do the same thing for returns created by the epilogue | |
3776 | threading code. Note this code works only in this special case, | |
3777 | because other passes make no guarantee that they will never emit | |
3778 | an instruction between a USE and a RETURN. There is such a guarantee | |
3779 | for USE instructions immediately before a call. */ | |
3780 | ||
3781 | prev_dep_insn = insn; | |
3782 | dep_insn = PREV_INSN (insn); | |
3783 | while (GET_CODE (dep_insn) == INSN | |
3784 | && GET_CODE (PATTERN (dep_insn)) == USE | |
3785 | && GET_CODE (XEXP (PATTERN (dep_insn), 0)) == REG) | |
3786 | { | |
3787 | SCHED_GROUP_P (prev_dep_insn) = 1; | |
3788 | ||
3789 | /* Make a copy of all dependencies on dep_insn, and add to insn. | |
3790 | This is so that all of the dependencies will apply to the | |
3791 | group. */ | |
3792 | ||
3793 | for (link = LOG_LINKS (dep_insn); link; link = XEXP (link, 1)) | |
3794 | add_dependence (insn, XEXP (link, 0), REG_NOTE_KIND (link)); | |
3795 | ||
3796 | prev_dep_insn = dep_insn; | |
3797 | dep_insn = PREV_INSN (dep_insn); | |
3798 | } | |
3799 | } | |
3800 | } | |
3801 | ||
3802 | /* Analyze every insn between HEAD and TAIL inclusive, creating LOG_LINKS | |
3803 | for every dependency. */ | |
3804 | ||
3805 | static void | |
3806 | sched_analyze (head, tail) | |
3807 | rtx head, tail; | |
3808 | { | |
3809 | register rtx insn; | |
3810 | register rtx u; | |
3811 | rtx loop_notes = 0; | |
3812 | ||
3813 | for (insn = head;; insn = NEXT_INSN (insn)) | |
3814 | { | |
3815 | if (GET_CODE (insn) == INSN || GET_CODE (insn) == JUMP_INSN) | |
3816 | { | |
87373fba RH |
3817 | /* Clear out the stale LOG_LINKS from flow. */ |
3818 | free_INSN_LIST_list (&LOG_LINKS (insn)); | |
3819 | ||
63de6c74 MH |
3820 | /* Make each JUMP_INSN a scheduling barrier for memory |
3821 | references. */ | |
062ae7ed JL |
3822 | if (GET_CODE (insn) == JUMP_INSN) |
3823 | last_pending_memory_flush | |
3824 | = alloc_INSN_LIST (insn, last_pending_memory_flush); | |
8c660648 JL |
3825 | sched_analyze_insn (PATTERN (insn), insn, loop_notes); |
3826 | loop_notes = 0; | |
3827 | } | |
3828 | else if (GET_CODE (insn) == CALL_INSN) | |
3829 | { | |
3830 | rtx x; | |
3831 | register int i; | |
3832 | ||
3833 | CANT_MOVE (insn) = 1; | |
3834 | ||
87373fba RH |
3835 | /* Clear out the stale LOG_LINKS from flow. */ |
3836 | free_INSN_LIST_list (&LOG_LINKS (insn)); | |
3837 | ||
8c660648 JL |
3838 | /* Any instruction using a hard register which may get clobbered |
3839 | by a call needs to be marked as dependent on this call. | |
3840 | This prevents a use of a hard return reg from being moved | |
3841 | past a void call (i.e. it does not explicitly set the hard | |
3842 | return reg). */ | |
3843 | ||
3844 | /* If this call is followed by a NOTE_INSN_SETJMP, then assume that | |
3845 | all registers, not just hard registers, may be clobbered by this | |
3846 | call. */ | |
3847 | ||
3848 | /* Insn, being a CALL_INSN, magically depends on | |
3849 | `last_function_call' already. */ | |
3850 | ||
3851 | if (NEXT_INSN (insn) && GET_CODE (NEXT_INSN (insn)) == NOTE | |
3852 | && NOTE_LINE_NUMBER (NEXT_INSN (insn)) == NOTE_INSN_SETJMP) | |
3853 | { | |
3854 | int max_reg = max_reg_num (); | |
3855 | for (i = 0; i < max_reg; i++) | |
3856 | { | |
3857 | for (u = reg_last_uses[i]; u; u = XEXP (u, 1)) | |
3858 | add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI); | |
5a4f6418 | 3859 | free_INSN_LIST_list (®_last_uses[i]); |
8c660648 | 3860 | |
8c660648 JL |
3861 | for (u = reg_last_sets[i]; u; u = XEXP (u, 1)) |
3862 | add_dependence (insn, XEXP (u, 0), 0); | |
28c95eff RH |
3863 | |
3864 | for (u = reg_last_clobbers[i]; u; u = XEXP (u, 1)) | |
3865 | add_dependence (insn, XEXP (u, 0), 0); | |
8c660648 JL |
3866 | } |
3867 | reg_pending_sets_all = 1; | |
3868 | ||
63de6c74 | 3869 | /* Add a pair of fake REG_NOTEs which we will later |
8c660648 JL |
3870 | convert back into a NOTE_INSN_SETJMP note. See |
3871 | reemit_notes for why we use a pair of NOTEs. */ | |
ebb7b10b RH |
3872 | REG_NOTES (insn) = alloc_EXPR_LIST (REG_DEAD, |
3873 | GEN_INT (0), | |
3874 | REG_NOTES (insn)); | |
3875 | REG_NOTES (insn) = alloc_EXPR_LIST (REG_DEAD, | |
3876 | GEN_INT (NOTE_INSN_SETJMP), | |
3877 | REG_NOTES (insn)); | |
8c660648 JL |
3878 | } |
3879 | else | |
3880 | { | |
3881 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
3882 | if (call_used_regs[i] || global_regs[i]) | |
3883 | { | |
3884 | for (u = reg_last_uses[i]; u; u = XEXP (u, 1)) | |
3885 | add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI); | |
8c660648 | 3886 | |
8c660648 JL |
3887 | for (u = reg_last_sets[i]; u; u = XEXP (u, 1)) |
3888 | add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI); | |
3889 | ||
c1cb76e9 | 3890 | SET_REGNO_REG_SET (reg_pending_clobbers, i); |
8c660648 JL |
3891 | } |
3892 | } | |
3893 | ||
3894 | /* For each insn which shouldn't cross a call, add a dependence | |
3895 | between that insn and this call insn. */ | |
3896 | x = LOG_LINKS (sched_before_next_call); | |
3897 | while (x) | |
3898 | { | |
3899 | add_dependence (insn, XEXP (x, 0), REG_DEP_ANTI); | |
3900 | x = XEXP (x, 1); | |
3901 | } | |
3902 | LOG_LINKS (sched_before_next_call) = 0; | |
3903 | ||
3904 | sched_analyze_insn (PATTERN (insn), insn, loop_notes); | |
3905 | loop_notes = 0; | |
3906 | ||
3907 | /* In the absence of interprocedural alias analysis, we must flush | |
3908 | all pending reads and writes, and start new dependencies starting | |
3909 | from here. But only flush writes for constant calls (which may | |
3910 | be passed a pointer to something we haven't written yet). */ | |
3911 | flush_pending_lists (insn, CONST_CALL_P (insn)); | |
3912 | ||
3913 | /* Depend this function call (actually, the user of this | |
3914 | function call) on all hard register clobberage. */ | |
3915 | ||
63de6c74 | 3916 | /* last_function_call is now a list of insns. */ |
5a4f6418 | 3917 | free_INSN_LIST_list(&last_function_call); |
ebb7b10b | 3918 | last_function_call = alloc_INSN_LIST (insn, NULL_RTX); |
8c660648 JL |
3919 | } |
3920 | ||
63de6c74 MH |
3921 | /* See comments on reemit_notes as to why we do this. |
3922 | ??? Actually, the reemit_notes just say what is done, not why. */ | |
6dfdecdb RH |
3923 | |
3924 | else if (GET_CODE (insn) == NOTE | |
3925 | && (NOTE_LINE_NUMBER (insn) == NOTE_INSN_RANGE_START | |
3926 | || NOTE_LINE_NUMBER (insn) == NOTE_INSN_RANGE_END)) | |
3927 | { | |
3928 | loop_notes = alloc_EXPR_LIST (REG_DEAD, NOTE_RANGE_INFO (insn), | |
3929 | loop_notes); | |
3930 | loop_notes = alloc_EXPR_LIST (REG_DEAD, | |
3931 | GEN_INT (NOTE_LINE_NUMBER (insn)), | |
3932 | loop_notes); | |
3933 | } | |
8c660648 JL |
3934 | else if (GET_CODE (insn) == NOTE |
3935 | && (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG | |
3936 | || NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_END | |
3937 | || NOTE_LINE_NUMBER (insn) == NOTE_INSN_EH_REGION_BEG | |
3938 | || NOTE_LINE_NUMBER (insn) == NOTE_INSN_EH_REGION_END | |
3939 | || (NOTE_LINE_NUMBER (insn) == NOTE_INSN_SETJMP | |
3940 | && GET_CODE (PREV_INSN (insn)) != CALL_INSN))) | |
3941 | { | |
ebb7b10b RH |
3942 | loop_notes = alloc_EXPR_LIST (REG_DEAD, |
3943 | GEN_INT (NOTE_BLOCK_NUMBER (insn)), | |
3944 | loop_notes); | |
3945 | loop_notes = alloc_EXPR_LIST (REG_DEAD, | |
3946 | GEN_INT (NOTE_LINE_NUMBER (insn)), | |
3947 | loop_notes); | |
8c660648 JL |
3948 | CONST_CALL_P (loop_notes) = CONST_CALL_P (insn); |
3949 | } | |
3950 | ||
3951 | if (insn == tail) | |
3952 | return; | |
3953 | } | |
3954 | abort (); | |
3955 | } | |
3956 | \f | |
3957 | /* Called when we see a set of a register. If death is true, then we are | |
3958 | scanning backwards. Mark that register as unborn. If nobody says | |
3959 | otherwise, that is how things will remain. If death is false, then we | |
3960 | are scanning forwards. Mark that register as being born. */ | |
3961 | ||
3962 | static void | |
5835e573 | 3963 | sched_note_set (x, death) |
8c660648 JL |
3964 | rtx x; |
3965 | int death; | |
3966 | { | |
3967 | register int regno; | |
3968 | register rtx reg = SET_DEST (x); | |
3969 | int subreg_p = 0; | |
3970 | ||
3971 | if (reg == 0) | |
3972 | return; | |
3973 | ||
c0222c21 DM |
3974 | if (GET_CODE (reg) == PARALLEL |
3975 | && GET_MODE (reg) == BLKmode) | |
3976 | { | |
3977 | register int i; | |
3978 | for (i = XVECLEN (reg, 0) - 1; i >= 0; i--) | |
3979 | sched_note_set (XVECEXP (reg, 0, i), death); | |
3980 | return; | |
3981 | } | |
3982 | ||
8c660648 JL |
3983 | while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == STRICT_LOW_PART |
3984 | || GET_CODE (reg) == SIGN_EXTRACT || GET_CODE (reg) == ZERO_EXTRACT) | |
3985 | { | |
3986 | /* Must treat modification of just one hardware register of a multi-reg | |
3987 | value or just a byte field of a register exactly the same way that | |
3988 | mark_set_1 in flow.c does, i.e. anything except a paradoxical subreg | |
3989 | does not kill the entire register. */ | |
3990 | if (GET_CODE (reg) != SUBREG | |
3991 | || REG_SIZE (SUBREG_REG (reg)) > REG_SIZE (reg)) | |
3992 | subreg_p = 1; | |
3993 | ||
3994 | reg = SUBREG_REG (reg); | |
3995 | } | |
3996 | ||
3997 | if (GET_CODE (reg) != REG) | |
3998 | return; | |
3999 | ||
4000 | /* Global registers are always live, so the code below does not apply | |
4001 | to them. */ | |
4002 | ||
4003 | regno = REGNO (reg); | |
4004 | if (regno >= FIRST_PSEUDO_REGISTER || !global_regs[regno]) | |
4005 | { | |
4006 | if (death) | |
4007 | { | |
4008 | /* If we only set part of the register, then this set does not | |
4009 | kill it. */ | |
4010 | if (subreg_p) | |
4011 | return; | |
4012 | ||
4013 | /* Try killing this register. */ | |
4014 | if (regno < FIRST_PSEUDO_REGISTER) | |
4015 | { | |
4016 | int j = HARD_REGNO_NREGS (regno, GET_MODE (reg)); | |
4017 | while (--j >= 0) | |
4018 | { | |
4019 | CLEAR_REGNO_REG_SET (bb_live_regs, regno + j); | |
4020 | } | |
4021 | } | |
4022 | else | |
4023 | { | |
4024 | /* Recompute REG_BASIC_BLOCK as we update all the other | |
4025 | dataflow information. */ | |
4026 | if (sched_reg_basic_block[regno] == REG_BLOCK_UNKNOWN) | |
4027 | sched_reg_basic_block[regno] = current_block_num; | |
4028 | else if (sched_reg_basic_block[regno] != current_block_num) | |
4029 | sched_reg_basic_block[regno] = REG_BLOCK_GLOBAL; | |
4030 | ||
4031 | CLEAR_REGNO_REG_SET (bb_live_regs, regno); | |
4032 | } | |
4033 | } | |
4034 | else | |
4035 | { | |
4036 | /* Make the register live again. */ | |
4037 | if (regno < FIRST_PSEUDO_REGISTER) | |
4038 | { | |
4039 | int j = HARD_REGNO_NREGS (regno, GET_MODE (reg)); | |
4040 | while (--j >= 0) | |
4041 | { | |
4042 | SET_REGNO_REG_SET (bb_live_regs, regno + j); | |
4043 | } | |
4044 | } | |
4045 | else | |
4046 | { | |
4047 | SET_REGNO_REG_SET (bb_live_regs, regno); | |
4048 | } | |
4049 | } | |
4050 | } | |
4051 | } | |
4052 | \f | |
4053 | /* Macros and functions for keeping the priority queue sorted, and | |
4054 | dealing with queueing and dequeueing of instructions. */ | |
4055 | ||
4056 | #define SCHED_SORT(READY, N_READY) \ | |
4057 | do { if ((N_READY) == 2) \ | |
4058 | swap_sort (READY, N_READY); \ | |
4059 | else if ((N_READY) > 2) \ | |
4060 | qsort (READY, N_READY, sizeof (rtx), rank_for_schedule); } \ | |
4061 | while (0) | |
4062 | ||
4063 | /* Returns a positive value if x is preferred; returns a negative value if | |
4064 | y is preferred. Should never return 0, since that will make the sort | |
4065 | unstable. */ | |
4066 | ||
4067 | static int | |
4068 | rank_for_schedule (x, y) | |
e1b6684c KG |
4069 | const PTR x; |
4070 | const PTR y; | |
8c660648 | 4071 | { |
01c7f350 MM |
4072 | rtx tmp = *(rtx *)y; |
4073 | rtx tmp2 = *(rtx *)x; | |
8c660648 | 4074 | rtx link; |
2db45993 | 4075 | int tmp_class, tmp2_class, depend_count1, depend_count2; |
8c660648 JL |
4076 | int val, priority_val, spec_val, prob_val, weight_val; |
4077 | ||
4078 | ||
63de6c74 | 4079 | /* Prefer insn with higher priority. */ |
8c660648 JL |
4080 | priority_val = INSN_PRIORITY (tmp2) - INSN_PRIORITY (tmp); |
4081 | if (priority_val) | |
4082 | return priority_val; | |
4083 | ||
63de6c74 | 4084 | /* Prefer an insn with smaller contribution to registers-pressure. */ |
8c660648 JL |
4085 | if (!reload_completed && |
4086 | (weight_val = INSN_REG_WEIGHT (tmp) - INSN_REG_WEIGHT (tmp2))) | |
4087 | return (weight_val); | |
4088 | ||
63de6c74 | 4089 | /* Some comparison make sense in interblock scheduling only. */ |
8c660648 JL |
4090 | if (INSN_BB (tmp) != INSN_BB (tmp2)) |
4091 | { | |
63de6c74 | 4092 | /* Prefer an inblock motion on an interblock motion. */ |
8c660648 JL |
4093 | if ((INSN_BB (tmp2) == target_bb) && (INSN_BB (tmp) != target_bb)) |
4094 | return 1; | |
4095 | if ((INSN_BB (tmp) == target_bb) && (INSN_BB (tmp2) != target_bb)) | |
4096 | return -1; | |
4097 | ||
63de6c74 | 4098 | /* Prefer a useful motion on a speculative one. */ |
8c660648 JL |
4099 | if ((spec_val = IS_SPECULATIVE_INSN (tmp) - IS_SPECULATIVE_INSN (tmp2))) |
4100 | return (spec_val); | |
4101 | ||
63de6c74 | 4102 | /* Prefer a more probable (speculative) insn. */ |
8c660648 JL |
4103 | prob_val = INSN_PROBABILITY (tmp2) - INSN_PROBABILITY (tmp); |
4104 | if (prob_val) | |
4105 | return (prob_val); | |
4106 | } | |
4107 | ||
63de6c74 | 4108 | /* Compare insns based on their relation to the last-scheduled-insn. */ |
8c660648 JL |
4109 | if (last_scheduled_insn) |
4110 | { | |
4111 | /* Classify the instructions into three classes: | |
4112 | 1) Data dependent on last schedule insn. | |
4113 | 2) Anti/Output dependent on last scheduled insn. | |
4114 | 3) Independent of last scheduled insn, or has latency of one. | |
4115 | Choose the insn from the highest numbered class if different. */ | |
4116 | link = find_insn_list (tmp, INSN_DEPEND (last_scheduled_insn)); | |
4117 | if (link == 0 || insn_cost (last_scheduled_insn, link, tmp) == 1) | |
4118 | tmp_class = 3; | |
4119 | else if (REG_NOTE_KIND (link) == 0) /* Data dependence. */ | |
4120 | tmp_class = 1; | |
4121 | else | |
4122 | tmp_class = 2; | |
4123 | ||
4124 | link = find_insn_list (tmp2, INSN_DEPEND (last_scheduled_insn)); | |
4125 | if (link == 0 || insn_cost (last_scheduled_insn, link, tmp2) == 1) | |
4126 | tmp2_class = 3; | |
4127 | else if (REG_NOTE_KIND (link) == 0) /* Data dependence. */ | |
4128 | tmp2_class = 1; | |
4129 | else | |
4130 | tmp2_class = 2; | |
4131 | ||
4132 | if ((val = tmp2_class - tmp_class)) | |
4133 | return val; | |
4134 | } | |
4135 | ||
2db45993 JL |
4136 | /* Prefer the insn which has more later insns that depend on it. |
4137 | This gives the scheduler more freedom when scheduling later | |
4138 | instructions at the expense of added register pressure. */ | |
4139 | depend_count1 = 0; | |
4140 | for (link = INSN_DEPEND (tmp); link; link = XEXP (link, 1)) | |
4141 | depend_count1++; | |
4142 | ||
4143 | depend_count2 = 0; | |
4144 | for (link = INSN_DEPEND (tmp2); link; link = XEXP (link, 1)) | |
4145 | depend_count2++; | |
4146 | ||
4147 | val = depend_count2 - depend_count1; | |
4148 | if (val) | |
4149 | return val; | |
4150 | ||
8c660648 JL |
4151 | /* If insns are equally good, sort by INSN_LUID (original insn order), |
4152 | so that we make the sort stable. This minimizes instruction movement, | |
4153 | thus minimizing sched's effect on debugging and cross-jumping. */ | |
4154 | return INSN_LUID (tmp) - INSN_LUID (tmp2); | |
4155 | } | |
4156 | ||
4157 | /* Resort the array A in which only element at index N may be out of order. */ | |
4158 | ||
cbb13457 | 4159 | HAIFA_INLINE static void |
8c660648 JL |
4160 | swap_sort (a, n) |
4161 | rtx *a; | |
4162 | int n; | |
4163 | { | |
4164 | rtx insn = a[n - 1]; | |
4165 | int i = n - 2; | |
4166 | ||
4167 | while (i >= 0 && rank_for_schedule (a + i, &insn) >= 0) | |
4168 | { | |
4169 | a[i + 1] = a[i]; | |
4170 | i -= 1; | |
4171 | } | |
4172 | a[i + 1] = insn; | |
4173 | } | |
4174 | ||
4175 | static int max_priority; | |
4176 | ||
4177 | /* Add INSN to the insn queue so that it can be executed at least | |
4178 | N_CYCLES after the currently executing insn. Preserve insns | |
4179 | chain for debugging purposes. */ | |
4180 | ||
cbb13457 | 4181 | HAIFA_INLINE static void |
8c660648 JL |
4182 | queue_insn (insn, n_cycles) |
4183 | rtx insn; | |
4184 | int n_cycles; | |
4185 | { | |
4186 | int next_q = NEXT_Q_AFTER (q_ptr, n_cycles); | |
ebb7b10b | 4187 | rtx link = alloc_INSN_LIST (insn, insn_queue[next_q]); |
8c660648 JL |
4188 | insn_queue[next_q] = link; |
4189 | q_size += 1; | |
4190 | ||
4191 | if (sched_verbose >= 2) | |
4192 | { | |
4193 | fprintf (dump, ";;\t\tReady-->Q: insn %d: ", INSN_UID (insn)); | |
4194 | ||
4195 | if (INSN_BB (insn) != target_bb) | |
4196 | fprintf (dump, "(b%d) ", INSN_BLOCK (insn)); | |
4197 | ||
4198 | fprintf (dump, "queued for %d cycles.\n", n_cycles); | |
4199 | } | |
4200 | ||
4201 | } | |
4202 | ||
4203 | /* Return nonzero if PAT is the pattern of an insn which makes a | |
4204 | register live. */ | |
4205 | ||
cbb13457 | 4206 | HAIFA_INLINE static int |
8c660648 JL |
4207 | birthing_insn_p (pat) |
4208 | rtx pat; | |
4209 | { | |
4210 | int j; | |
4211 | ||
4212 | if (reload_completed == 1) | |
4213 | return 0; | |
4214 | ||
4215 | if (GET_CODE (pat) == SET | |
c0222c21 DM |
4216 | && (GET_CODE (SET_DEST (pat)) == REG |
4217 | || (GET_CODE (SET_DEST (pat)) == PARALLEL | |
4218 | && GET_MODE (SET_DEST (pat)) == BLKmode))) | |
8c660648 JL |
4219 | { |
4220 | rtx dest = SET_DEST (pat); | |
c0222c21 | 4221 | int i; |
8c660648 JL |
4222 | |
4223 | /* It would be more accurate to use refers_to_regno_p or | |
c0222c21 DM |
4224 | reg_mentioned_p to determine when the dest is not live before this |
4225 | insn. */ | |
4226 | if (GET_CODE (dest) == REG) | |
4227 | { | |
4228 | i = REGNO (dest); | |
4229 | if (REGNO_REG_SET_P (bb_live_regs, i)) | |
4230 | return (REG_N_SETS (i) == 1); | |
4231 | } | |
4232 | else | |
4233 | { | |
4234 | for (i = XVECLEN (dest, 0) - 1; i >= 0; i--) | |
4235 | { | |
4236 | int regno = REGNO (SET_DEST (XVECEXP (dest, 0, i))); | |
4237 | if (REGNO_REG_SET_P (bb_live_regs, regno)) | |
4238 | return (REG_N_SETS (regno) == 1); | |
4239 | } | |
4240 | } | |
8c660648 JL |
4241 | return 0; |
4242 | } | |
4243 | if (GET_CODE (pat) == PARALLEL) | |
4244 | { | |
4245 | for (j = 0; j < XVECLEN (pat, 0); j++) | |
4246 | if (birthing_insn_p (XVECEXP (pat, 0, j))) | |
4247 | return 1; | |
4248 | } | |
4249 | return 0; | |
4250 | } | |
4251 | ||
4252 | /* PREV is an insn that is ready to execute. Adjust its priority if that | |
4253 | will help shorten register lifetimes. */ | |
4254 | ||
cbb13457 | 4255 | HAIFA_INLINE static void |
8c660648 JL |
4256 | adjust_priority (prev) |
4257 | rtx prev; | |
4258 | { | |
4259 | /* Trying to shorten register lives after reload has completed | |
4260 | is useless and wrong. It gives inaccurate schedules. */ | |
4261 | if (reload_completed == 0) | |
4262 | { | |
4263 | rtx note; | |
4264 | int n_deaths = 0; | |
4265 | ||
4266 | /* ??? This code has no effect, because REG_DEAD notes are removed | |
4267 | before we ever get here. */ | |
4268 | for (note = REG_NOTES (prev); note; note = XEXP (note, 1)) | |
4269 | if (REG_NOTE_KIND (note) == REG_DEAD) | |
4270 | n_deaths += 1; | |
4271 | ||
4272 | /* Defer scheduling insns which kill registers, since that | |
4273 | shortens register lives. Prefer scheduling insns which | |
4274 | make registers live for the same reason. */ | |
4275 | switch (n_deaths) | |
4276 | { | |
4277 | default: | |
4278 | INSN_PRIORITY (prev) >>= 3; | |
4279 | break; | |
4280 | case 3: | |
4281 | INSN_PRIORITY (prev) >>= 2; | |
4282 | break; | |
4283 | case 2: | |
4284 | case 1: | |
4285 | INSN_PRIORITY (prev) >>= 1; | |
4286 | break; | |
4287 | case 0: | |
4288 | if (birthing_insn_p (PATTERN (prev))) | |
4289 | { | |
4290 | int max = max_priority; | |
4291 | ||
4292 | if (max > INSN_PRIORITY (prev)) | |
4293 | INSN_PRIORITY (prev) = max; | |
4294 | } | |
4295 | break; | |
4296 | } | |
197043f5 RH |
4297 | } |
4298 | ||
4299 | /* That said, a target might have it's own reasons for adjusting | |
4300 | priority after reload. */ | |
8c660648 | 4301 | #ifdef ADJUST_PRIORITY |
197043f5 | 4302 | ADJUST_PRIORITY (prev); |
8c660648 | 4303 | #endif |
8c660648 JL |
4304 | } |
4305 | ||
4bdc8810 RH |
4306 | /* Clock at which the previous instruction was issued. */ |
4307 | static int last_clock_var; | |
4308 | ||
8c660648 JL |
4309 | /* INSN is the "currently executing insn". Launch each insn which was |
4310 | waiting on INSN. READY is a vector of insns which are ready to fire. | |
4311 | N_READY is the number of elements in READY. CLOCK is the current | |
4312 | cycle. */ | |
4313 | ||
4314 | static int | |
4315 | schedule_insn (insn, ready, n_ready, clock) | |
4316 | rtx insn; | |
4317 | rtx *ready; | |
4318 | int n_ready; | |
4319 | int clock; | |
4320 | { | |
4321 | rtx link; | |
4322 | int unit; | |
4323 | ||
4324 | unit = insn_unit (insn); | |
4325 | ||
4326 | if (sched_verbose >= 2) | |
4327 | { | |
63de6c74 MH |
4328 | fprintf (dump, ";;\t\t--> scheduling insn <<<%d>>> on unit ", |
4329 | INSN_UID (insn)); | |
8c660648 JL |
4330 | insn_print_units (insn); |
4331 | fprintf (dump, "\n"); | |
4332 | } | |
4333 | ||
4334 | if (sched_verbose && unit == -1) | |
4335 | visualize_no_unit (insn); | |
4336 | ||
4337 | if (MAX_BLOCKAGE > 1 || issue_rate > 1 || sched_verbose) | |
4338 | schedule_unit (unit, insn, clock); | |
4339 | ||
4340 | if (INSN_DEPEND (insn) == 0) | |
4341 | return n_ready; | |
4342 | ||
4343 | /* This is used by the function adjust_priority above. */ | |
4344 | if (n_ready > 0) | |
4345 | max_priority = MAX (INSN_PRIORITY (ready[0]), INSN_PRIORITY (insn)); | |
4346 | else | |
4347 | max_priority = INSN_PRIORITY (insn); | |
4348 | ||
4349 | for (link = INSN_DEPEND (insn); link != 0; link = XEXP (link, 1)) | |
4350 | { | |
4351 | rtx next = XEXP (link, 0); | |
4352 | int cost = insn_cost (insn, link, next); | |
4353 | ||
4354 | INSN_TICK (next) = MAX (INSN_TICK (next), clock + cost); | |
4355 | ||
4356 | if ((INSN_DEP_COUNT (next) -= 1) == 0) | |
4357 | { | |
4358 | int effective_cost = INSN_TICK (next) - clock; | |
4359 | ||
4360 | /* For speculative insns, before inserting to ready/queue, | |
63de6c74 | 4361 | check live, exception-free, and issue-delay. */ |
8c660648 JL |
4362 | if (INSN_BB (next) != target_bb |
4363 | && (!IS_VALID (INSN_BB (next)) | |
4364 | || CANT_MOVE (next) | |
4365 | || (IS_SPECULATIVE_INSN (next) | |
4366 | && (insn_issue_delay (next) > 3 | |
5835e573 | 4367 | || !check_live (next, INSN_BB (next)) |
8c660648 JL |
4368 | || !is_exception_free (next, INSN_BB (next), target_bb))))) |
4369 | continue; | |
4370 | ||
4371 | if (sched_verbose >= 2) | |
4372 | { | |
63de6c74 MH |
4373 | fprintf (dump, ";;\t\tdependences resolved: insn %d ", |
4374 | INSN_UID (next)); | |
8c660648 JL |
4375 | |
4376 | if (current_nr_blocks > 1 && INSN_BB (next) != target_bb) | |
4377 | fprintf (dump, "/b%d ", INSN_BLOCK (next)); | |
4378 | ||
197043f5 | 4379 | if (effective_cost < 1) |
8c660648 JL |
4380 | fprintf (dump, "into ready\n"); |
4381 | else | |
4382 | fprintf (dump, "into queue with cost=%d\n", effective_cost); | |
4383 | } | |
4384 | ||
4385 | /* Adjust the priority of NEXT and either put it on the ready | |
4386 | list or queue it. */ | |
4387 | adjust_priority (next); | |
197043f5 | 4388 | if (effective_cost < 1) |
8c660648 JL |
4389 | ready[n_ready++] = next; |
4390 | else | |
4391 | queue_insn (next, effective_cost); | |
4392 | } | |
4393 | } | |
4394 | ||
4bdc8810 RH |
4395 | /* Annotate the instruction with issue information -- TImode |
4396 | indicates that the instruction is expected not to be able | |
4397 | to issue on the same cycle as the previous insn. A machine | |
4398 | may use this information to decide how the instruction should | |
4399 | be aligned. */ | |
4400 | if (reload_completed && issue_rate > 1) | |
4401 | { | |
4402 | PUT_MODE (insn, clock > last_clock_var ? TImode : VOIDmode); | |
4403 | last_clock_var = clock; | |
4404 | } | |
4405 | ||
8c660648 JL |
4406 | return n_ready; |
4407 | } | |
4408 | ||
4409 | ||
4410 | /* Add a REG_DEAD note for REG to INSN, reusing a REG_DEAD note from the | |
4411 | dead_notes list. */ | |
4412 | ||
4413 | static void | |
4414 | create_reg_dead_note (reg, insn) | |
4415 | rtx reg, insn; | |
4416 | { | |
4417 | rtx link; | |
4418 | ||
4419 | /* The number of registers killed after scheduling must be the same as the | |
4420 | number of registers killed before scheduling. The number of REG_DEAD | |
4421 | notes may not be conserved, i.e. two SImode hard register REG_DEAD notes | |
4422 | might become one DImode hard register REG_DEAD note, but the number of | |
4423 | registers killed will be conserved. | |
4424 | ||
4425 | We carefully remove REG_DEAD notes from the dead_notes list, so that | |
4426 | there will be none left at the end. If we run out early, then there | |
4427 | is a bug somewhere in flow, combine and/or sched. */ | |
4428 | ||
4429 | if (dead_notes == 0) | |
4430 | { | |
4431 | if (current_nr_blocks <= 1) | |
4432 | abort (); | |
4433 | else | |
ebb7b10b | 4434 | link = alloc_EXPR_LIST (REG_DEAD, NULL_RTX, NULL_RTX); |
8c660648 JL |
4435 | } |
4436 | else | |
4437 | { | |
4438 | /* Number of regs killed by REG. */ | |
4439 | int regs_killed = (REGNO (reg) >= FIRST_PSEUDO_REGISTER ? 1 | |
4440 | : HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg))); | |
4441 | /* Number of regs killed by REG_DEAD notes taken off the list. */ | |
4442 | int reg_note_regs; | |
4443 | ||
4444 | link = dead_notes; | |
4445 | reg_note_regs = (REGNO (XEXP (link, 0)) >= FIRST_PSEUDO_REGISTER ? 1 | |
4446 | : HARD_REGNO_NREGS (REGNO (XEXP (link, 0)), | |
4447 | GET_MODE (XEXP (link, 0)))); | |
4448 | while (reg_note_regs < regs_killed) | |
4449 | { | |
4450 | link = XEXP (link, 1); | |
04029ca2 JL |
4451 | |
4452 | /* LINK might be zero if we killed more registers after scheduling | |
4453 | than before, and the last hard register we kill is actually | |
4454 | multiple hard regs. | |
4455 | ||
4456 | This is normal for interblock scheduling, so deal with it in | |
4457 | that case, else abort. */ | |
4458 | if (link == NULL_RTX && current_nr_blocks <= 1) | |
4459 | abort (); | |
4460 | else if (link == NULL_RTX) | |
ebb7b10b RH |
4461 | link = alloc_EXPR_LIST (REG_DEAD, gen_rtx_REG (word_mode, 0), |
4462 | NULL_RTX); | |
04029ca2 | 4463 | |
8c660648 JL |
4464 | reg_note_regs += (REGNO (XEXP (link, 0)) >= FIRST_PSEUDO_REGISTER ? 1 |
4465 | : HARD_REGNO_NREGS (REGNO (XEXP (link, 0)), | |
4466 | GET_MODE (XEXP (link, 0)))); | |
4467 | } | |
4468 | dead_notes = XEXP (link, 1); | |
4469 | ||
4470 | /* If we took too many regs kills off, put the extra ones back. */ | |
4471 | while (reg_note_regs > regs_killed) | |
4472 | { | |
4473 | rtx temp_reg, temp_link; | |
4474 | ||
38a448ca | 4475 | temp_reg = gen_rtx_REG (word_mode, 0); |
ebb7b10b | 4476 | temp_link = alloc_EXPR_LIST (REG_DEAD, temp_reg, dead_notes); |
8c660648 JL |
4477 | dead_notes = temp_link; |
4478 | reg_note_regs--; | |
4479 | } | |
4480 | } | |
4481 | ||
4482 | XEXP (link, 0) = reg; | |
4483 | XEXP (link, 1) = REG_NOTES (insn); | |
4484 | REG_NOTES (insn) = link; | |
4485 | } | |
4486 | ||
4487 | /* Subroutine on attach_deaths_insn--handles the recursive search | |
4488 | through INSN. If SET_P is true, then x is being modified by the insn. */ | |
4489 | ||
4490 | static void | |
4491 | attach_deaths (x, insn, set_p) | |
4492 | rtx x; | |
4493 | rtx insn; | |
4494 | int set_p; | |
4495 | { | |
4496 | register int i; | |
4497 | register int j; | |
4498 | register enum rtx_code code; | |
6f7d635c | 4499 | register const char *fmt; |
8c660648 JL |
4500 | |
4501 | if (x == 0) | |
4502 | return; | |
4503 | ||
4504 | code = GET_CODE (x); | |
4505 | ||
4506 | switch (code) | |
4507 | { | |
4508 | case CONST_INT: | |
4509 | case CONST_DOUBLE: | |
4510 | case LABEL_REF: | |
4511 | case SYMBOL_REF: | |
4512 | case CONST: | |
4513 | case CODE_LABEL: | |
4514 | case PC: | |
4515 | case CC0: | |
4516 | /* Get rid of the easy cases first. */ | |
4517 | return; | |
4518 | ||
4519 | case REG: | |
4520 | { | |
4521 | /* If the register dies in this insn, queue that note, and mark | |
4522 | this register as needing to die. */ | |
4523 | /* This code is very similar to mark_used_1 (if set_p is false) | |
4524 | and mark_set_1 (if set_p is true) in flow.c. */ | |
4525 | ||
4526 | register int regno; | |
4527 | int some_needed; | |
4528 | int all_needed; | |
4529 | ||
4530 | if (set_p) | |
4531 | return; | |
4532 | ||
4533 | regno = REGNO (x); | |
4534 | all_needed = some_needed = REGNO_REG_SET_P (old_live_regs, regno); | |
4535 | if (regno < FIRST_PSEUDO_REGISTER) | |
4536 | { | |
4537 | int n; | |
4538 | ||
4539 | n = HARD_REGNO_NREGS (regno, GET_MODE (x)); | |
4540 | while (--n > 0) | |
4541 | { | |
4542 | int needed = (REGNO_REG_SET_P (old_live_regs, regno + n)); | |
4543 | some_needed |= needed; | |
4544 | all_needed &= needed; | |
4545 | } | |
4546 | } | |
4547 | ||
4548 | /* If it wasn't live before we started, then add a REG_DEAD note. | |
4549 | We must check the previous lifetime info not the current info, | |
4550 | because we may have to execute this code several times, e.g. | |
4551 | once for a clobber (which doesn't add a note) and later | |
4552 | for a use (which does add a note). | |
4553 | ||
4554 | Always make the register live. We must do this even if it was | |
4555 | live before, because this may be an insn which sets and uses | |
4556 | the same register, in which case the register has already been | |
4557 | killed, so we must make it live again. | |
4558 | ||
4559 | Global registers are always live, and should never have a REG_DEAD | |
4560 | note added for them, so none of the code below applies to them. */ | |
4561 | ||
4562 | if (regno >= FIRST_PSEUDO_REGISTER || ! global_regs[regno]) | |
4563 | { | |
e4b8a413 JW |
4564 | /* Never add REG_DEAD notes for STACK_POINTER_REGNUM |
4565 | since it's always considered to be live. Similarly | |
4566 | for FRAME_POINTER_REGNUM if a frame pointer is needed | |
4567 | and for ARG_POINTER_REGNUM if it is fixed. */ | |
4568 | if (! (regno == FRAME_POINTER_REGNUM | |
4569 | && (! reload_completed || frame_pointer_needed)) | |
8c660648 | 4570 | #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM |
e4b8a413 JW |
4571 | && ! (regno == HARD_FRAME_POINTER_REGNUM |
4572 | && (! reload_completed || frame_pointer_needed)) | |
8c660648 JL |
4573 | #endif |
4574 | #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM | |
4575 | && ! (regno == ARG_POINTER_REGNUM && fixed_regs[regno]) | |
4576 | #endif | |
4577 | && regno != STACK_POINTER_REGNUM) | |
4578 | { | |
d6df9efb | 4579 | if (! all_needed && ! dead_or_set_p (insn, x)) |
8c660648 JL |
4580 | { |
4581 | /* Check for the case where the register dying partially | |
4582 | overlaps the register set by this insn. */ | |
4583 | if (regno < FIRST_PSEUDO_REGISTER | |
4584 | && HARD_REGNO_NREGS (regno, GET_MODE (x)) > 1) | |
4585 | { | |
4586 | int n = HARD_REGNO_NREGS (regno, GET_MODE (x)); | |
4587 | while (--n >= 0) | |
4588 | some_needed |= dead_or_set_regno_p (insn, regno + n); | |
4589 | } | |
4590 | ||
4591 | /* If none of the words in X is needed, make a REG_DEAD | |
4592 | note. Otherwise, we must make partial REG_DEAD | |
4593 | notes. */ | |
4594 | if (! some_needed) | |
4595 | create_reg_dead_note (x, insn); | |
4596 | else | |
4597 | { | |
4598 | int i; | |
4599 | ||
4600 | /* Don't make a REG_DEAD note for a part of a | |
4601 | register that is set in the insn. */ | |
4602 | for (i = HARD_REGNO_NREGS (regno, GET_MODE (x)) - 1; | |
4603 | i >= 0; i--) | |
4604 | if (! REGNO_REG_SET_P (old_live_regs, regno+i) | |
4605 | && ! dead_or_set_regno_p (insn, regno + i)) | |
38a448ca RH |
4606 | create_reg_dead_note (gen_rtx_REG (reg_raw_mode[regno + i], |
4607 | regno + i), | |
8c660648 JL |
4608 | insn); |
4609 | } | |
4610 | } | |
4611 | } | |
4612 | ||
4613 | if (regno < FIRST_PSEUDO_REGISTER) | |
4614 | { | |
4615 | int j = HARD_REGNO_NREGS (regno, GET_MODE (x)); | |
4616 | while (--j >= 0) | |
4617 | { | |
4618 | SET_REGNO_REG_SET (bb_live_regs, regno + j); | |
4619 | } | |
4620 | } | |
4621 | else | |
4622 | { | |
4623 | /* Recompute REG_BASIC_BLOCK as we update all the other | |
4624 | dataflow information. */ | |
4625 | if (sched_reg_basic_block[regno] == REG_BLOCK_UNKNOWN) | |
4626 | sched_reg_basic_block[regno] = current_block_num; | |
4627 | else if (sched_reg_basic_block[regno] != current_block_num) | |
4628 | sched_reg_basic_block[regno] = REG_BLOCK_GLOBAL; | |
4629 | ||
4630 | SET_REGNO_REG_SET (bb_live_regs, regno); | |
4631 | } | |
4632 | } | |
4633 | return; | |
4634 | } | |
4635 | ||
4636 | case MEM: | |
4637 | /* Handle tail-recursive case. */ | |
4638 | attach_deaths (XEXP (x, 0), insn, 0); | |
4639 | return; | |
4640 | ||
4641 | case SUBREG: | |
d6df9efb JL |
4642 | attach_deaths (SUBREG_REG (x), insn, |
4643 | set_p && ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))) | |
4644 | <= UNITS_PER_WORD) | |
4645 | || (GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))) | |
4646 | == GET_MODE_SIZE (GET_MODE ((x)))))); | |
4647 | return; | |
4648 | ||
8c660648 | 4649 | case STRICT_LOW_PART: |
d6df9efb | 4650 | attach_deaths (XEXP (x, 0), insn, 0); |
8c660648 JL |
4651 | return; |
4652 | ||
4653 | case ZERO_EXTRACT: | |
4654 | case SIGN_EXTRACT: | |
d6df9efb | 4655 | attach_deaths (XEXP (x, 0), insn, 0); |
8c660648 JL |
4656 | attach_deaths (XEXP (x, 1), insn, 0); |
4657 | attach_deaths (XEXP (x, 2), insn, 0); | |
4658 | return; | |
4659 | ||
c0222c21 DM |
4660 | case PARALLEL: |
4661 | if (set_p | |
4662 | && GET_MODE (x) == BLKmode) | |
4663 | { | |
4664 | for (i = XVECLEN (x, 0) - 1; i >= 0; i--) | |
4665 | attach_deaths (SET_DEST (XVECEXP (x, 0, i)), insn, 1); | |
4666 | return; | |
4667 | } | |
4668 | ||
63de6c74 | 4669 | /* Fallthrough. */ |
8c660648 JL |
4670 | default: |
4671 | /* Other cases: walk the insn. */ | |
4672 | fmt = GET_RTX_FORMAT (code); | |
4673 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
4674 | { | |
4675 | if (fmt[i] == 'e') | |
4676 | attach_deaths (XEXP (x, i), insn, 0); | |
4677 | else if (fmt[i] == 'E') | |
4678 | for (j = 0; j < XVECLEN (x, i); j++) | |
4679 | attach_deaths (XVECEXP (x, i, j), insn, 0); | |
4680 | } | |
4681 | } | |
4682 | } | |
4683 | ||
4684 | /* After INSN has executed, add register death notes for each register | |
4685 | that is dead after INSN. */ | |
4686 | ||
4687 | static void | |
4688 | attach_deaths_insn (insn) | |
4689 | rtx insn; | |
4690 | { | |
4691 | rtx x = PATTERN (insn); | |
4692 | register RTX_CODE code = GET_CODE (x); | |
4693 | rtx link; | |
4694 | ||
4695 | if (code == SET) | |
4696 | { | |
4697 | attach_deaths (SET_SRC (x), insn, 0); | |
4698 | ||
4699 | /* A register might die here even if it is the destination, e.g. | |
4700 | it is the target of a volatile read and is otherwise unused. | |
4701 | Hence we must always call attach_deaths for the SET_DEST. */ | |
4702 | attach_deaths (SET_DEST (x), insn, 1); | |
4703 | } | |
4704 | else if (code == PARALLEL) | |
4705 | { | |
4706 | register int i; | |
4707 | for (i = XVECLEN (x, 0) - 1; i >= 0; i--) | |
4708 | { | |
4709 | code = GET_CODE (XVECEXP (x, 0, i)); | |
4710 | if (code == SET) | |
4711 | { | |
4712 | attach_deaths (SET_SRC (XVECEXP (x, 0, i)), insn, 0); | |
4713 | ||
4714 | attach_deaths (SET_DEST (XVECEXP (x, 0, i)), insn, 1); | |
4715 | } | |
4716 | /* Flow does not add REG_DEAD notes to registers that die in | |
4717 | clobbers, so we can't either. */ | |
4718 | else if (code != CLOBBER) | |
4719 | attach_deaths (XVECEXP (x, 0, i), insn, 0); | |
4720 | } | |
4721 | } | |
4722 | /* If this is a CLOBBER, only add REG_DEAD notes to registers inside a | |
4723 | MEM being clobbered, just like flow. */ | |
4724 | else if (code == CLOBBER && GET_CODE (XEXP (x, 0)) == MEM) | |
4725 | attach_deaths (XEXP (XEXP (x, 0), 0), insn, 0); | |
4726 | /* Otherwise don't add a death note to things being clobbered. */ | |
4727 | else if (code != CLOBBER) | |
4728 | attach_deaths (x, insn, 0); | |
4729 | ||
4730 | /* Make death notes for things used in the called function. */ | |
4731 | if (GET_CODE (insn) == CALL_INSN) | |
4732 | for (link = CALL_INSN_FUNCTION_USAGE (insn); link; link = XEXP (link, 1)) | |
4733 | attach_deaths (XEXP (XEXP (link, 0), 0), insn, | |
4734 | GET_CODE (XEXP (link, 0)) == CLOBBER); | |
4735 | } | |
4736 | ||
63de6c74 | 4737 | /* Functions for handling of notes. */ |
8c660648 JL |
4738 | |
4739 | /* Delete notes beginning with INSN and put them in the chain | |
4740 | of notes ended by NOTE_LIST. | |
4741 | Returns the insn following the notes. */ | |
4742 | ||
4743 | static rtx | |
4744 | unlink_other_notes (insn, tail) | |
4745 | rtx insn, tail; | |
4746 | { | |
4747 | rtx prev = PREV_INSN (insn); | |
4748 | ||
4749 | while (insn != tail && GET_CODE (insn) == NOTE) | |
4750 | { | |
4751 | rtx next = NEXT_INSN (insn); | |
4752 | /* Delete the note from its current position. */ | |
4753 | if (prev) | |
4754 | NEXT_INSN (prev) = next; | |
4755 | if (next) | |
4756 | PREV_INSN (next) = prev; | |
4757 | ||
4758 | /* Don't save away NOTE_INSN_SETJMPs, because they must remain | |
4759 | immediately after the call they follow. We use a fake | |
4760 | (REG_DEAD (const_int -1)) note to remember them. | |
4761 | Likewise with NOTE_INSN_{LOOP,EHREGION}_{BEG, END}. */ | |
4762 | if (NOTE_LINE_NUMBER (insn) != NOTE_INSN_SETJMP | |
4763 | && NOTE_LINE_NUMBER (insn) != NOTE_INSN_LOOP_BEG | |
4764 | && NOTE_LINE_NUMBER (insn) != NOTE_INSN_LOOP_END | |
0dfa1860 MM |
4765 | && NOTE_LINE_NUMBER (insn) != NOTE_INSN_RANGE_START |
4766 | && NOTE_LINE_NUMBER (insn) != NOTE_INSN_RANGE_END | |
8c660648 JL |
4767 | && NOTE_LINE_NUMBER (insn) != NOTE_INSN_EH_REGION_BEG |
4768 | && NOTE_LINE_NUMBER (insn) != NOTE_INSN_EH_REGION_END) | |
4769 | { | |
4770 | /* Insert the note at the end of the notes list. */ | |
4771 | PREV_INSN (insn) = note_list; | |
4772 | if (note_list) | |
4773 | NEXT_INSN (note_list) = insn; | |
4774 | note_list = insn; | |
4775 | } | |
4776 | ||
4777 | insn = next; | |
4778 | } | |
4779 | return insn; | |
4780 | } | |
4781 | ||
4782 | /* Delete line notes beginning with INSN. Record line-number notes so | |
4783 | they can be reused. Returns the insn following the notes. */ | |
4784 | ||
4785 | static rtx | |
4786 | unlink_line_notes (insn, tail) | |
4787 | rtx insn, tail; | |
4788 | { | |
4789 | rtx prev = PREV_INSN (insn); | |
4790 | ||
4791 | while (insn != tail && GET_CODE (insn) == NOTE) | |
4792 | { | |
4793 | rtx next = NEXT_INSN (insn); | |
4794 | ||
4795 | if (write_symbols != NO_DEBUG && NOTE_LINE_NUMBER (insn) > 0) | |
4796 | { | |
4797 | /* Delete the note from its current position. */ | |
4798 | if (prev) | |
4799 | NEXT_INSN (prev) = next; | |
4800 | if (next) | |
4801 | PREV_INSN (next) = prev; | |
4802 | ||
4803 | /* Record line-number notes so they can be reused. */ | |
4804 | LINE_NOTE (insn) = insn; | |
4805 | } | |
4806 | else | |
4807 | prev = insn; | |
4808 | ||
4809 | insn = next; | |
4810 | } | |
4811 | return insn; | |
4812 | } | |
4813 | ||
4814 | /* Return the head and tail pointers of BB. */ | |
4815 | ||
cbb13457 | 4816 | HAIFA_INLINE static void |
8c660648 JL |
4817 | get_block_head_tail (bb, headp, tailp) |
4818 | int bb; | |
4819 | rtx *headp; | |
4820 | rtx *tailp; | |
4821 | { | |
4822 | ||
55d89719 TK |
4823 | rtx head; |
4824 | rtx tail; | |
8c660648 JL |
4825 | int b; |
4826 | ||
4827 | b = BB_TO_BLOCK (bb); | |
4828 | ||
4829 | /* HEAD and TAIL delimit the basic block being scheduled. */ | |
3b413743 RH |
4830 | head = BLOCK_HEAD (b); |
4831 | tail = BLOCK_END (b); | |
8c660648 JL |
4832 | |
4833 | /* Don't include any notes or labels at the beginning of the | |
4834 | basic block, or notes at the ends of basic blocks. */ | |
4835 | while (head != tail) | |
4836 | { | |
4837 | if (GET_CODE (head) == NOTE) | |
4838 | head = NEXT_INSN (head); | |
4839 | else if (GET_CODE (tail) == NOTE) | |
4840 | tail = PREV_INSN (tail); | |
4841 | else if (GET_CODE (head) == CODE_LABEL) | |
4842 | head = NEXT_INSN (head); | |
4843 | else | |
4844 | break; | |
4845 | } | |
4846 | ||
4847 | *headp = head; | |
4848 | *tailp = tail; | |
4849 | } | |
4850 | ||
4851 | /* Delete line notes from bb. Save them so they can be later restored | |
4852 | (in restore_line_notes ()). */ | |
4853 | ||
4854 | static void | |
4855 | rm_line_notes (bb) | |
4856 | int bb; | |
4857 | { | |
4858 | rtx next_tail; | |
4859 | rtx tail; | |
4860 | rtx head; | |
4861 | rtx insn; | |
4862 | ||
4863 | get_block_head_tail (bb, &head, &tail); | |
4864 | ||
4865 | if (head == tail | |
4866 | && (GET_RTX_CLASS (GET_CODE (head)) != 'i')) | |
4867 | return; | |
4868 | ||
4869 | next_tail = NEXT_INSN (tail); | |
4870 | for (insn = head; insn != next_tail; insn = NEXT_INSN (insn)) | |
4871 | { | |
4872 | rtx prev; | |
4873 | ||
4874 | /* Farm out notes, and maybe save them in NOTE_LIST. | |
4875 | This is needed to keep the debugger from | |
4876 | getting completely deranged. */ | |
4877 | if (GET_CODE (insn) == NOTE) | |
4878 | { | |
4879 | prev = insn; | |
4880 | insn = unlink_line_notes (insn, next_tail); | |
4881 | ||
4882 | if (prev == tail) | |
4883 | abort (); | |
4884 | if (prev == head) | |
4885 | abort (); | |
4886 | if (insn == next_tail) | |
4887 | abort (); | |
4888 | } | |
4889 | } | |
4890 | } | |
4891 | ||
4892 | /* Save line number notes for each insn in bb. */ | |
4893 | ||
4894 | static void | |
4895 | save_line_notes (bb) | |
4896 | int bb; | |
4897 | { | |
4898 | rtx head, tail; | |
4899 | rtx next_tail; | |
4900 | ||
4901 | /* We must use the true line number for the first insn in the block | |
4902 | that was computed and saved at the start of this pass. We can't | |
4903 | use the current line number, because scheduling of the previous | |
4904 | block may have changed the current line number. */ | |
4905 | ||
4906 | rtx line = line_note_head[BB_TO_BLOCK (bb)]; | |
4907 | rtx insn; | |
4908 | ||
4909 | get_block_head_tail (bb, &head, &tail); | |
4910 | next_tail = NEXT_INSN (tail); | |
4911 | ||
3b413743 | 4912 | for (insn = BLOCK_HEAD (BB_TO_BLOCK (bb)); |
8c660648 JL |
4913 | insn != next_tail; |
4914 | insn = NEXT_INSN (insn)) | |
4915 | if (GET_CODE (insn) == NOTE && NOTE_LINE_NUMBER (insn) > 0) | |
4916 | line = insn; | |
4917 | else | |
4918 | LINE_NOTE (insn) = line; | |
4919 | } | |
4920 | ||
4921 | ||
4922 | /* After bb was scheduled, insert line notes into the insns list. */ | |
4923 | ||
4924 | static void | |
4925 | restore_line_notes (bb) | |
4926 | int bb; | |
4927 | { | |
4928 | rtx line, note, prev, new; | |
4929 | int added_notes = 0; | |
4930 | int b; | |
4931 | rtx head, next_tail, insn; | |
4932 | ||
4933 | b = BB_TO_BLOCK (bb); | |
4934 | ||
3b413743 RH |
4935 | head = BLOCK_HEAD (b); |
4936 | next_tail = NEXT_INSN (BLOCK_END (b)); | |
8c660648 JL |
4937 | |
4938 | /* Determine the current line-number. We want to know the current | |
4939 | line number of the first insn of the block here, in case it is | |
4940 | different from the true line number that was saved earlier. If | |
4941 | different, then we need a line number note before the first insn | |
4942 | of this block. If it happens to be the same, then we don't want to | |
4943 | emit another line number note here. */ | |
4944 | for (line = head; line; line = PREV_INSN (line)) | |
4945 | if (GET_CODE (line) == NOTE && NOTE_LINE_NUMBER (line) > 0) | |
4946 | break; | |
4947 | ||
4948 | /* Walk the insns keeping track of the current line-number and inserting | |
4949 | the line-number notes as needed. */ | |
4950 | for (insn = head; insn != next_tail; insn = NEXT_INSN (insn)) | |
4951 | if (GET_CODE (insn) == NOTE && NOTE_LINE_NUMBER (insn) > 0) | |
4952 | line = insn; | |
4953 | /* This used to emit line number notes before every non-deleted note. | |
4954 | However, this confuses a debugger, because line notes not separated | |
4955 | by real instructions all end up at the same address. I can find no | |
4956 | use for line number notes before other notes, so none are emitted. */ | |
4957 | else if (GET_CODE (insn) != NOTE | |
4958 | && (note = LINE_NOTE (insn)) != 0 | |
4959 | && note != line | |
4960 | && (line == 0 | |
4961 | || NOTE_LINE_NUMBER (note) != NOTE_LINE_NUMBER (line) | |
4962 | || NOTE_SOURCE_FILE (note) != NOTE_SOURCE_FILE (line))) | |
4963 | { | |
4964 | line = note; | |
4965 | prev = PREV_INSN (insn); | |
4966 | if (LINE_NOTE (note)) | |
4967 | { | |
4968 | /* Re-use the original line-number note. */ | |
4969 | LINE_NOTE (note) = 0; | |
4970 | PREV_INSN (note) = prev; | |
4971 | NEXT_INSN (prev) = note; | |
4972 | PREV_INSN (insn) = note; | |
4973 | NEXT_INSN (note) = insn; | |
4974 | } | |
4975 | else | |
4976 | { | |
4977 | added_notes++; | |
4978 | new = emit_note_after (NOTE_LINE_NUMBER (note), prev); | |
4979 | NOTE_SOURCE_FILE (new) = NOTE_SOURCE_FILE (note); | |
4980 | RTX_INTEGRATED_P (new) = RTX_INTEGRATED_P (note); | |
4981 | } | |
4982 | } | |
4983 | if (sched_verbose && added_notes) | |
4984 | fprintf (dump, ";; added %d line-number notes\n", added_notes); | |
4985 | } | |
4986 | ||
4987 | /* After scheduling the function, delete redundant line notes from the | |
4988 | insns list. */ | |
4989 | ||
4990 | static void | |
4991 | rm_redundant_line_notes () | |
4992 | { | |
4993 | rtx line = 0; | |
4994 | rtx insn = get_insns (); | |
4995 | int active_insn = 0; | |
4996 | int notes = 0; | |
4997 | ||
4998 | /* Walk the insns deleting redundant line-number notes. Many of these | |
4999 | are already present. The remainder tend to occur at basic | |
5000 | block boundaries. */ | |
5001 | for (insn = get_last_insn (); insn; insn = PREV_INSN (insn)) | |
5002 | if (GET_CODE (insn) == NOTE && NOTE_LINE_NUMBER (insn) > 0) | |
5003 | { | |
5004 | /* If there are no active insns following, INSN is redundant. */ | |
5005 | if (active_insn == 0) | |
5006 | { | |
5007 | notes++; | |
5008 | NOTE_SOURCE_FILE (insn) = 0; | |
5009 | NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED; | |
5010 | } | |
5011 | /* If the line number is unchanged, LINE is redundant. */ | |
5012 | else if (line | |
5013 | && NOTE_LINE_NUMBER (line) == NOTE_LINE_NUMBER (insn) | |
5014 | && NOTE_SOURCE_FILE (line) == NOTE_SOURCE_FILE (insn)) | |
5015 | { | |
5016 | notes++; | |
5017 | NOTE_SOURCE_FILE (line) = 0; | |
5018 | NOTE_LINE_NUMBER (line) = NOTE_INSN_DELETED; | |
5019 | line = insn; | |
5020 | } | |
5021 | else | |
5022 | line = insn; | |
5023 | active_insn = 0; | |
5024 | } | |
5025 | else if (!((GET_CODE (insn) == NOTE | |
5026 | && NOTE_LINE_NUMBER (insn) == NOTE_INSN_DELETED) | |
5027 | || (GET_CODE (insn) == INSN | |
5028 | && (GET_CODE (PATTERN (insn)) == USE | |
5029 | || GET_CODE (PATTERN (insn)) == CLOBBER)))) | |
5030 | active_insn++; | |
5031 | ||
5032 | if (sched_verbose && notes) | |
5033 | fprintf (dump, ";; deleted %d line-number notes\n", notes); | |
5034 | } | |
5035 | ||
5036 | /* Delete notes between head and tail and put them in the chain | |
5037 | of notes ended by NOTE_LIST. */ | |
5038 | ||
5039 | static void | |
5040 | rm_other_notes (head, tail) | |
5041 | rtx head; | |
5042 | rtx tail; | |
5043 | { | |
5044 | rtx next_tail; | |
5045 | rtx insn; | |
5046 | ||
5047 | if (head == tail | |
5048 | && (GET_RTX_CLASS (GET_CODE (head)) != 'i')) | |
5049 | return; | |
5050 | ||
5051 | next_tail = NEXT_INSN (tail); | |
5052 | for (insn = head; insn != next_tail; insn = NEXT_INSN (insn)) | |
5053 | { | |
5054 | rtx prev; | |
5055 | ||
5056 | /* Farm out notes, and maybe save them in NOTE_LIST. | |
5057 | This is needed to keep the debugger from | |
5058 | getting completely deranged. */ | |
5059 | if (GET_CODE (insn) == NOTE) | |
5060 | { | |
5061 | prev = insn; | |
5062 | ||
5063 | insn = unlink_other_notes (insn, next_tail); | |
5064 | ||
5065 | if (prev == tail) | |
5066 | abort (); | |
5067 | if (prev == head) | |
5068 | abort (); | |
5069 | if (insn == next_tail) | |
5070 | abort (); | |
5071 | } | |
5072 | } | |
5073 | } | |
5074 | ||
5075 | /* Constructor for `sometimes' data structure. */ | |
5076 | ||
5077 | static int | |
5078 | new_sometimes_live (regs_sometimes_live, regno, sometimes_max) | |
5079 | struct sometimes *regs_sometimes_live; | |
5080 | int regno; | |
5081 | int sometimes_max; | |
5082 | { | |
5083 | register struct sometimes *p; | |
5084 | ||
5085 | /* There should never be a register greater than max_regno here. If there | |
5086 | is, it means that a define_split has created a new pseudo reg. This | |
5087 | is not allowed, since there will not be flow info available for any | |
5088 | new register, so catch the error here. */ | |
5089 | if (regno >= max_regno) | |
5090 | abort (); | |
5091 | ||
5092 | p = ®s_sometimes_live[sometimes_max]; | |
5093 | p->regno = regno; | |
5094 | p->live_length = 0; | |
5095 | p->calls_crossed = 0; | |
5096 | sometimes_max++; | |
5097 | return sometimes_max; | |
5098 | } | |
5099 | ||
5100 | /* Count lengths of all regs we are currently tracking, | |
5101 | and find new registers no longer live. */ | |
5102 | ||
5103 | static void | |
5104 | finish_sometimes_live (regs_sometimes_live, sometimes_max) | |
5105 | struct sometimes *regs_sometimes_live; | |
5106 | int sometimes_max; | |
5107 | { | |
5108 | int i; | |
5109 | ||
5110 | for (i = 0; i < sometimes_max; i++) | |
5111 | { | |
5112 | register struct sometimes *p = ®s_sometimes_live[i]; | |
5113 | int regno = p->regno; | |
5114 | ||
5115 | sched_reg_live_length[regno] += p->live_length; | |
5116 | sched_reg_n_calls_crossed[regno] += p->calls_crossed; | |
5117 | } | |
5118 | } | |
5119 | ||
63de6c74 | 5120 | /* Functions for computation of registers live/usage info. */ |
8c660648 | 5121 | |
e881bb1b | 5122 | /* It is assumed that prior to scheduling BASIC_BLOCK (b)->global_live_at_start |
8c660648 JL |
5123 | contains the registers that are alive at the entry to b. |
5124 | ||
5125 | Two passes follow: The first pass is performed before the scheduling | |
5126 | of a region. It scans each block of the region forward, computing | |
5127 | the set of registers alive at the end of the basic block and | |
5128 | discard REG_DEAD notes (done by find_pre_sched_live ()). | |
5129 | ||
5130 | The second path is invoked after scheduling all region blocks. | |
5131 | It scans each block of the region backward, a block being traversed | |
5132 | only after its succesors in the region. When the set of registers | |
5133 | live at the end of a basic block may be changed by the scheduling | |
5134 | (this may happen for multiple blocks region), it is computed as | |
5135 | the union of the registers live at the start of its succesors. | |
5136 | The last-use information is updated by inserting REG_DEAD notes. | |
5137 | (done by find_post_sched_live ()) */ | |
5138 | ||
5139 | /* Scan all the insns to be scheduled, removing register death notes. | |
5140 | Register death notes end up in DEAD_NOTES. | |
5141 | Recreate the register life information for the end of this basic | |
5142 | block. */ | |
5143 | ||
5144 | static void | |
5145 | find_pre_sched_live (bb) | |
5146 | int bb; | |
5147 | { | |
5148 | rtx insn, next_tail, head, tail; | |
5149 | int b = BB_TO_BLOCK (bb); | |
5150 | ||
5151 | get_block_head_tail (bb, &head, &tail); | |
e881bb1b | 5152 | COPY_REG_SET (bb_live_regs, BASIC_BLOCK (b)->global_live_at_start); |
8c660648 JL |
5153 | next_tail = NEXT_INSN (tail); |
5154 | ||
5155 | for (insn = head; insn != next_tail; insn = NEXT_INSN (insn)) | |
5156 | { | |
5157 | rtx prev, next, link; | |
5158 | int reg_weight = 0; | |
5159 | ||
5160 | /* Handle register life information. */ | |
5161 | if (GET_RTX_CLASS (GET_CODE (insn)) == 'i') | |
5162 | { | |
5163 | /* See if the register gets born here. */ | |
5164 | /* We must check for registers being born before we check for | |
5165 | registers dying. It is possible for a register to be born and | |
5166 | die in the same insn, e.g. reading from a volatile memory | |
5167 | location into an otherwise unused register. Such a register | |
5168 | must be marked as dead after this insn. */ | |
5169 | if (GET_CODE (PATTERN (insn)) == SET | |
5170 | || GET_CODE (PATTERN (insn)) == CLOBBER) | |
5171 | { | |
5835e573 | 5172 | sched_note_set (PATTERN (insn), 0); |
8c660648 JL |
5173 | reg_weight++; |
5174 | } | |
5175 | ||
5176 | else if (GET_CODE (PATTERN (insn)) == PARALLEL) | |
5177 | { | |
5178 | int j; | |
5179 | for (j = XVECLEN (PATTERN (insn), 0) - 1; j >= 0; j--) | |
5180 | if (GET_CODE (XVECEXP (PATTERN (insn), 0, j)) == SET | |
5181 | || GET_CODE (XVECEXP (PATTERN (insn), 0, j)) == CLOBBER) | |
5182 | { | |
5835e573 | 5183 | sched_note_set (XVECEXP (PATTERN (insn), 0, j), 0); |
8c660648 JL |
5184 | reg_weight++; |
5185 | } | |
5186 | ||
5187 | /* ??? This code is obsolete and should be deleted. It | |
5188 | is harmless though, so we will leave it in for now. */ | |
5189 | for (j = XVECLEN (PATTERN (insn), 0) - 1; j >= 0; j--) | |
5190 | if (GET_CODE (XVECEXP (PATTERN (insn), 0, j)) == USE) | |
5835e573 | 5191 | sched_note_set (XVECEXP (PATTERN (insn), 0, j), 0); |
8c660648 JL |
5192 | } |
5193 | ||
5194 | /* Each call cobbers (makes live) all call-clobbered regs | |
5195 | that are not global or fixed. Note that the function-value | |
5196 | reg is a call_clobbered reg. */ | |
5197 | if (GET_CODE (insn) == CALL_INSN) | |
5198 | { | |
5199 | int j; | |
5200 | for (j = 0; j < FIRST_PSEUDO_REGISTER; j++) | |
5201 | if (call_used_regs[j] && !global_regs[j] | |
5202 | && ! fixed_regs[j]) | |
5203 | { | |
5204 | SET_REGNO_REG_SET (bb_live_regs, j); | |
8c660648 JL |
5205 | } |
5206 | } | |
5207 | ||
5208 | /* Need to know what registers this insn kills. */ | |
5209 | for (prev = 0, link = REG_NOTES (insn); link; link = next) | |
5210 | { | |
5211 | next = XEXP (link, 1); | |
5212 | if ((REG_NOTE_KIND (link) == REG_DEAD | |
5213 | || REG_NOTE_KIND (link) == REG_UNUSED) | |
5214 | /* Verify that the REG_NOTE has a valid value. */ | |
5215 | && GET_CODE (XEXP (link, 0)) == REG) | |
5216 | { | |
5217 | register int regno = REGNO (XEXP (link, 0)); | |
5218 | ||
5219 | reg_weight--; | |
5220 | ||
5221 | /* Only unlink REG_DEAD notes; leave REG_UNUSED notes | |
5222 | alone. */ | |
5223 | if (REG_NOTE_KIND (link) == REG_DEAD) | |
5224 | { | |
5225 | if (prev) | |
5226 | XEXP (prev, 1) = next; | |
5227 | else | |
5228 | REG_NOTES (insn) = next; | |
5229 | XEXP (link, 1) = dead_notes; | |
5230 | dead_notes = link; | |
5231 | } | |
5232 | else | |
5233 | prev = link; | |
5234 | ||
5235 | if (regno < FIRST_PSEUDO_REGISTER) | |
5236 | { | |
5237 | int j = HARD_REGNO_NREGS (regno, | |
5238 | GET_MODE (XEXP (link, 0))); | |
5239 | while (--j >= 0) | |
5240 | { | |
5241 | CLEAR_REGNO_REG_SET (bb_live_regs, regno+j); | |
5242 | } | |
5243 | } | |
5244 | else | |
5245 | { | |
5246 | CLEAR_REGNO_REG_SET (bb_live_regs, regno); | |
5247 | } | |
5248 | } | |
5249 | else | |
5250 | prev = link; | |
5251 | } | |
5252 | } | |
5253 | ||
5254 | INSN_REG_WEIGHT (insn) = reg_weight; | |
5255 | } | |
5256 | } | |
5257 | ||
5258 | /* Update register life and usage information for block bb | |
5259 | after scheduling. Put register dead notes back in the code. */ | |
5260 | ||
5261 | static void | |
5262 | find_post_sched_live (bb) | |
5263 | int bb; | |
5264 | { | |
5265 | int sometimes_max; | |
5266 | int j, i; | |
5267 | int b; | |
5268 | rtx insn; | |
5269 | rtx head, tail, prev_head, next_tail; | |
5270 | ||
5271 | register struct sometimes *regs_sometimes_live; | |
5272 | ||
5273 | b = BB_TO_BLOCK (bb); | |
5274 | ||
63de6c74 | 5275 | /* Compute live regs at the end of bb as a function of its successors. */ |
8c660648 JL |
5276 | if (current_nr_blocks > 1) |
5277 | { | |
5278 | int e; | |
5279 | int first_edge; | |
5280 | ||
5281 | first_edge = e = OUT_EDGES (b); | |
5282 | CLEAR_REG_SET (bb_live_regs); | |
5283 | ||
5284 | if (e) | |
5285 | do | |
5286 | { | |
5287 | int b_succ; | |
5288 | ||
5289 | b_succ = TO_BLOCK (e); | |
e881bb1b RH |
5290 | IOR_REG_SET (bb_live_regs, |
5291 | BASIC_BLOCK (b_succ)->global_live_at_start); | |
8c660648 JL |
5292 | e = NEXT_OUT (e); |
5293 | } | |
5294 | while (e != first_edge); | |
5295 | } | |
5296 | ||
5297 | get_block_head_tail (bb, &head, &tail); | |
5298 | next_tail = NEXT_INSN (tail); | |
5299 | prev_head = PREV_INSN (head); | |
5300 | ||
7eea6443 JL |
5301 | EXECUTE_IF_SET_IN_REG_SET (bb_live_regs, FIRST_PSEUDO_REGISTER, i, |
5302 | { | |
5303 | sched_reg_basic_block[i] = REG_BLOCK_GLOBAL; | |
5304 | }); | |
8c660648 | 5305 | |
63de6c74 | 5306 | /* If the block is empty, same regs are alive at its end and its start. |
8c660648 JL |
5307 | since this is not guaranteed after interblock scheduling, make sure they |
5308 | are truly identical. */ | |
5309 | if (NEXT_INSN (prev_head) == tail | |
5310 | && (GET_RTX_CLASS (GET_CODE (tail)) != 'i')) | |
5311 | { | |
5312 | if (current_nr_blocks > 1) | |
e881bb1b | 5313 | COPY_REG_SET (BASIC_BLOCK (b)->global_live_at_start, bb_live_regs); |
8c660648 JL |
5314 | |
5315 | return; | |
5316 | } | |
5317 | ||
5318 | b = BB_TO_BLOCK (bb); | |
5319 | current_block_num = b; | |
5320 | ||
5321 | /* Keep track of register lives. */ | |
5322 | old_live_regs = ALLOCA_REG_SET (); | |
5323 | regs_sometimes_live | |
5324 | = (struct sometimes *) alloca (max_regno * sizeof (struct sometimes)); | |
5325 | sometimes_max = 0; | |
5326 | ||
63de6c74 | 5327 | /* Initiate "sometimes" data, starting with registers live at end. */ |
8c660648 JL |
5328 | sometimes_max = 0; |
5329 | COPY_REG_SET (old_live_regs, bb_live_regs); | |
5330 | EXECUTE_IF_SET_IN_REG_SET (bb_live_regs, 0, j, | |
5331 | { | |
5332 | sometimes_max | |
5333 | = new_sometimes_live (regs_sometimes_live, | |
5334 | j, sometimes_max); | |
5335 | }); | |
5336 | ||
63de6c74 | 5337 | /* Scan insns back, computing regs live info. */ |
8c660648 JL |
5338 | for (insn = tail; insn != prev_head; insn = PREV_INSN (insn)) |
5339 | { | |
5340 | /* First we kill registers set by this insn, and then we | |
5341 | make registers used by this insn live. This is the opposite | |
5342 | order used above because we are traversing the instructions | |
5343 | backwards. */ | |
5344 | ||
5345 | /* Strictly speaking, we should scan REG_UNUSED notes and make | |
5346 | every register mentioned there live, however, we will just | |
5347 | kill them again immediately below, so there doesn't seem to | |
5348 | be any reason why we bother to do this. */ | |
5349 | ||
5350 | /* See if this is the last notice we must take of a register. */ | |
5351 | if (GET_RTX_CLASS (GET_CODE (insn)) != 'i') | |
5352 | continue; | |
5353 | ||
5354 | if (GET_CODE (PATTERN (insn)) == SET | |
5355 | || GET_CODE (PATTERN (insn)) == CLOBBER) | |
5835e573 | 5356 | sched_note_set (PATTERN (insn), 1); |
8c660648 JL |
5357 | else if (GET_CODE (PATTERN (insn)) == PARALLEL) |
5358 | { | |
5359 | for (j = XVECLEN (PATTERN (insn), 0) - 1; j >= 0; j--) | |
5360 | if (GET_CODE (XVECEXP (PATTERN (insn), 0, j)) == SET | |
5361 | || GET_CODE (XVECEXP (PATTERN (insn), 0, j)) == CLOBBER) | |
5835e573 | 5362 | sched_note_set (XVECEXP (PATTERN (insn), 0, j), 1); |
8c660648 JL |
5363 | } |
5364 | ||
5365 | /* This code keeps life analysis information up to date. */ | |
5366 | if (GET_CODE (insn) == CALL_INSN) | |
5367 | { | |
5368 | register struct sometimes *p; | |
5369 | ||
5370 | /* A call kills all call used registers that are not | |
5371 | global or fixed, except for those mentioned in the call | |
5372 | pattern which will be made live again later. */ | |
5373 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
5374 | if (call_used_regs[i] && ! global_regs[i] | |
5375 | && ! fixed_regs[i]) | |
5376 | { | |
5377 | CLEAR_REGNO_REG_SET (bb_live_regs, i); | |
8c660648 JL |
5378 | } |
5379 | ||
5380 | /* Regs live at the time of a call instruction must not | |
5381 | go in a register clobbered by calls. Record this for | |
5382 | all regs now live. Note that insns which are born or | |
5383 | die in a call do not cross a call, so this must be done | |
5384 | after the killings (above) and before the births | |
5385 | (below). */ | |
5386 | p = regs_sometimes_live; | |
5387 | for (i = 0; i < sometimes_max; i++, p++) | |
5388 | if (REGNO_REG_SET_P (bb_live_regs, p->regno)) | |
5389 | p->calls_crossed += 1; | |
5390 | } | |
5391 | ||
5392 | /* Make every register used live, and add REG_DEAD notes for | |
5393 | registers which were not live before we started. */ | |
5394 | attach_deaths_insn (insn); | |
5395 | ||
5396 | /* Find registers now made live by that instruction. */ | |
5397 | EXECUTE_IF_AND_COMPL_IN_REG_SET (bb_live_regs, old_live_regs, 0, j, | |
5398 | { | |
5399 | sometimes_max | |
5400 | = new_sometimes_live (regs_sometimes_live, | |
5401 | j, sometimes_max); | |
5402 | }); | |
5403 | IOR_REG_SET (old_live_regs, bb_live_regs); | |
5404 | ||
5405 | /* Count lengths of all regs we are worrying about now, | |
5406 | and handle registers no longer live. */ | |
5407 | ||
5408 | for (i = 0; i < sometimes_max; i++) | |
5409 | { | |
5410 | register struct sometimes *p = ®s_sometimes_live[i]; | |
5411 | int regno = p->regno; | |
5412 | ||
5413 | p->live_length += 1; | |
5414 | ||
5415 | if (!REGNO_REG_SET_P (bb_live_regs, regno)) | |
5416 | { | |
5417 | /* This is the end of one of this register's lifetime | |
5418 | segments. Save the lifetime info collected so far, | |
5419 | and clear its bit in the old_live_regs entry. */ | |
5420 | sched_reg_live_length[regno] += p->live_length; | |
5421 | sched_reg_n_calls_crossed[regno] += p->calls_crossed; | |
5422 | CLEAR_REGNO_REG_SET (old_live_regs, p->regno); | |
5423 | ||
5424 | /* Delete the reg_sometimes_live entry for this reg by | |
5425 | copying the last entry over top of it. */ | |
5426 | *p = regs_sometimes_live[--sometimes_max]; | |
5427 | /* ...and decrement i so that this newly copied entry | |
5428 | will be processed. */ | |
5429 | i--; | |
5430 | } | |
5431 | } | |
5432 | } | |
5433 | ||
5434 | finish_sometimes_live (regs_sometimes_live, sometimes_max); | |
5435 | ||
e881bb1b | 5436 | /* In interblock scheduling, global_live_at_start may have changed. */ |
8c660648 | 5437 | if (current_nr_blocks > 1) |
e881bb1b | 5438 | COPY_REG_SET (BASIC_BLOCK (b)->global_live_at_start, bb_live_regs); |
8c660648 | 5439 | |
f187056f JL |
5440 | |
5441 | FREE_REG_SET (old_live_regs); | |
8c660648 JL |
5442 | } /* find_post_sched_live */ |
5443 | ||
5444 | /* After scheduling the subroutine, restore information about uses of | |
5445 | registers. */ | |
5446 | ||
5447 | static void | |
5448 | update_reg_usage () | |
5449 | { | |
5450 | int regno; | |
5451 | ||
5452 | if (n_basic_blocks > 0) | |
7eea6443 JL |
5453 | EXECUTE_IF_SET_IN_REG_SET (bb_live_regs, FIRST_PSEUDO_REGISTER, regno, |
5454 | { | |
5455 | sched_reg_basic_block[regno] | |
5456 | = REG_BLOCK_GLOBAL; | |
5457 | }); | |
8c660648 JL |
5458 | |
5459 | for (regno = 0; regno < max_regno; regno++) | |
5460 | if (sched_reg_live_length[regno]) | |
5461 | { | |
5462 | if (sched_verbose) | |
5463 | { | |
5464 | if (REG_LIVE_LENGTH (regno) > sched_reg_live_length[regno]) | |
5465 | fprintf (dump, | |
5466 | ";; register %d life shortened from %d to %d\n", | |
5467 | regno, REG_LIVE_LENGTH (regno), | |
5468 | sched_reg_live_length[regno]); | |
5469 | /* Negative values are special; don't overwrite the current | |
5470 | reg_live_length value if it is negative. */ | |
5471 | else if (REG_LIVE_LENGTH (regno) < sched_reg_live_length[regno] | |
5472 | && REG_LIVE_LENGTH (regno) >= 0) | |
5473 | fprintf (dump, | |
5474 | ";; register %d life extended from %d to %d\n", | |
5475 | regno, REG_LIVE_LENGTH (regno), | |
5476 | sched_reg_live_length[regno]); | |
5477 | ||
5478 | if (!REG_N_CALLS_CROSSED (regno) | |
5479 | && sched_reg_n_calls_crossed[regno]) | |
5480 | fprintf (dump, | |
5481 | ";; register %d now crosses calls\n", regno); | |
5482 | else if (REG_N_CALLS_CROSSED (regno) | |
5483 | && !sched_reg_n_calls_crossed[regno] | |
5484 | && REG_BASIC_BLOCK (regno) != REG_BLOCK_GLOBAL) | |
5485 | fprintf (dump, | |
5486 | ";; register %d no longer crosses calls\n", regno); | |
5487 | ||
5488 | if (REG_BASIC_BLOCK (regno) != sched_reg_basic_block[regno] | |
5489 | && sched_reg_basic_block[regno] != REG_BLOCK_UNKNOWN | |
5490 | && REG_BASIC_BLOCK(regno) != REG_BLOCK_UNKNOWN) | |
5491 | fprintf (dump, | |
5492 | ";; register %d changed basic block from %d to %d\n", | |
5493 | regno, REG_BASIC_BLOCK(regno), | |
5494 | sched_reg_basic_block[regno]); | |
5495 | ||
5496 | } | |
5497 | /* Negative values are special; don't overwrite the current | |
5498 | reg_live_length value if it is negative. */ | |
5499 | if (REG_LIVE_LENGTH (regno) >= 0) | |
5500 | REG_LIVE_LENGTH (regno) = sched_reg_live_length[regno]; | |
5501 | ||
5502 | if (sched_reg_basic_block[regno] != REG_BLOCK_UNKNOWN | |
5503 | && REG_BASIC_BLOCK(regno) != REG_BLOCK_UNKNOWN) | |
5504 | REG_BASIC_BLOCK(regno) = sched_reg_basic_block[regno]; | |
5505 | ||
5506 | /* We can't change the value of reg_n_calls_crossed to zero for | |
5507 | pseudos which are live in more than one block. | |
5508 | ||
5509 | This is because combine might have made an optimization which | |
e881bb1b | 5510 | invalidated global_live_at_start and reg_n_calls_crossed, |
8c660648 JL |
5511 | but it does not update them. If we update reg_n_calls_crossed |
5512 | here, the two variables are now inconsistent, and this might | |
5513 | confuse the caller-save code into saving a register that doesn't | |
5514 | need to be saved. This is only a problem when we zero calls | |
5515 | crossed for a pseudo live in multiple basic blocks. | |
5516 | ||
5517 | Alternatively, we could try to correctly update basic block live | |
5518 | at start here in sched, but that seems complicated. | |
5519 | ||
63de6c74 MH |
5520 | Note: it is possible that a global register became local, |
5521 | as result of interblock motion, but will remain marked as a | |
5522 | global register. */ | |
8c660648 JL |
5523 | if (sched_reg_n_calls_crossed[regno] |
5524 | || REG_BASIC_BLOCK (regno) != REG_BLOCK_GLOBAL) | |
5525 | REG_N_CALLS_CROSSED (regno) = sched_reg_n_calls_crossed[regno]; | |
5526 | ||
5527 | } | |
5528 | } | |
5529 | ||
63de6c74 | 5530 | /* Scheduling clock, modified in schedule_block() and queue_to_ready (). */ |
8c660648 JL |
5531 | static int clock_var; |
5532 | ||
5533 | /* Move insns that became ready to fire from queue to ready list. */ | |
5534 | ||
5535 | static int | |
5536 | queue_to_ready (ready, n_ready) | |
5537 | rtx ready[]; | |
5538 | int n_ready; | |
5539 | { | |
5540 | rtx insn; | |
5541 | rtx link; | |
5542 | ||
5543 | q_ptr = NEXT_Q (q_ptr); | |
5544 | ||
5545 | /* Add all pending insns that can be scheduled without stalls to the | |
5546 | ready list. */ | |
5547 | for (link = insn_queue[q_ptr]; link; link = XEXP (link, 1)) | |
5548 | { | |
5549 | ||
5550 | insn = XEXP (link, 0); | |
5551 | q_size -= 1; | |
5552 | ||
5553 | if (sched_verbose >= 2) | |
5554 | fprintf (dump, ";;\t\tQ-->Ready: insn %d: ", INSN_UID (insn)); | |
5555 | ||
5556 | if (sched_verbose >= 2 && INSN_BB (insn) != target_bb) | |
5557 | fprintf (dump, "(b%d) ", INSN_BLOCK (insn)); | |
5558 | ||
5559 | ready[n_ready++] = insn; | |
5560 | if (sched_verbose >= 2) | |
5561 | fprintf (dump, "moving to ready without stalls\n"); | |
5562 | } | |
5563 | insn_queue[q_ptr] = 0; | |
5564 | ||
5565 | /* If there are no ready insns, stall until one is ready and add all | |
5566 | of the pending insns at that point to the ready list. */ | |
5567 | if (n_ready == 0) | |
5568 | { | |
5569 | register int stalls; | |
5570 | ||
5571 | for (stalls = 1; stalls < INSN_QUEUE_SIZE; stalls++) | |
5572 | { | |
5573 | if ((link = insn_queue[NEXT_Q_AFTER (q_ptr, stalls)])) | |
5574 | { | |
5575 | for (; link; link = XEXP (link, 1)) | |
5576 | { | |
5577 | insn = XEXP (link, 0); | |
5578 | q_size -= 1; | |
5579 | ||
5580 | if (sched_verbose >= 2) | |
5581 | fprintf (dump, ";;\t\tQ-->Ready: insn %d: ", INSN_UID (insn)); | |
5582 | ||
5583 | if (sched_verbose >= 2 && INSN_BB (insn) != target_bb) | |
5584 | fprintf (dump, "(b%d) ", INSN_BLOCK (insn)); | |
5585 | ||
5586 | ready[n_ready++] = insn; | |
5587 | if (sched_verbose >= 2) | |
5588 | fprintf (dump, "moving to ready with %d stalls\n", stalls); | |
5589 | } | |
5590 | insn_queue[NEXT_Q_AFTER (q_ptr, stalls)] = 0; | |
5591 | ||
5592 | if (n_ready) | |
5593 | break; | |
5594 | } | |
5595 | } | |
5596 | ||
5597 | if (sched_verbose && stalls) | |
5598 | visualize_stall_cycles (BB_TO_BLOCK (target_bb), stalls); | |
5599 | q_ptr = NEXT_Q_AFTER (q_ptr, stalls); | |
5600 | clock_var += stalls; | |
5601 | } | |
5602 | return n_ready; | |
5603 | } | |
5604 | ||
63de6c74 | 5605 | /* Print the ready list for debugging purposes. Callable from debugger. */ |
8c660648 | 5606 | |
9a8b0889 | 5607 | static void |
8c660648 JL |
5608 | debug_ready_list (ready, n_ready) |
5609 | rtx ready[]; | |
5610 | int n_ready; | |
5611 | { | |
5612 | int i; | |
5613 | ||
5614 | for (i = 0; i < n_ready; i++) | |
5615 | { | |
5616 | fprintf (dump, " %d", INSN_UID (ready[i])); | |
5617 | if (current_nr_blocks > 1 && INSN_BB (ready[i]) != target_bb) | |
5618 | fprintf (dump, "/b%d", INSN_BLOCK (ready[i])); | |
5619 | } | |
5620 | fprintf (dump, "\n"); | |
5621 | } | |
5622 | ||
5623 | /* Print names of units on which insn can/should execute, for debugging. */ | |
5624 | ||
5625 | static void | |
5626 | insn_print_units (insn) | |
5627 | rtx insn; | |
5628 | { | |
5629 | int i; | |
5630 | int unit = insn_unit (insn); | |
5631 | ||
5632 | if (unit == -1) | |
5633 | fprintf (dump, "none"); | |
5634 | else if (unit >= 0) | |
5635 | fprintf (dump, "%s", function_units[unit].name); | |
5636 | else | |
5637 | { | |
5638 | fprintf (dump, "["); | |
5639 | for (i = 0, unit = ~unit; unit; i++, unit >>= 1) | |
5640 | if (unit & 1) | |
5641 | { | |
5642 | fprintf (dump, "%s", function_units[i].name); | |
5643 | if (unit != 1) | |
5644 | fprintf (dump, " "); | |
5645 | } | |
5646 | fprintf (dump, "]"); | |
5647 | } | |
5648 | } | |
5649 | ||
5650 | /* MAX_VISUAL_LINES is the maximum number of lines in visualization table | |
5651 | of a basic block. If more lines are needed, table is splitted to two. | |
5652 | n_visual_lines is the number of lines printed so far for a block. | |
5653 | visual_tbl contains the block visualization info. | |
5654 | vis_no_unit holds insns in a cycle that are not mapped to any unit. */ | |
5655 | #define MAX_VISUAL_LINES 100 | |
5656 | #define INSN_LEN 30 | |
5657 | int n_visual_lines; | |
5658 | char *visual_tbl; | |
5659 | int n_vis_no_unit; | |
5660 | rtx vis_no_unit[10]; | |
5661 | ||
63de6c74 | 5662 | /* Finds units that are in use in this fuction. Required only |
8c660648 JL |
5663 | for visualization. */ |
5664 | ||
5665 | static void | |
5666 | init_target_units () | |
5667 | { | |
5668 | rtx insn; | |
5669 | int unit; | |
5670 | ||
5671 | for (insn = get_last_insn (); insn; insn = PREV_INSN (insn)) | |
5672 | { | |
5673 | if (GET_RTX_CLASS (GET_CODE (insn)) != 'i') | |
5674 | continue; | |
5675 | ||
5676 | unit = insn_unit (insn); | |
5677 | ||
5678 | if (unit < 0) | |
5679 | target_units |= ~unit; | |
5680 | else | |
5681 | target_units |= (1 << unit); | |
5682 | } | |
5683 | } | |
5684 | ||
63de6c74 | 5685 | /* Return the length of the visualization table. */ |
8c660648 JL |
5686 | |
5687 | static int | |
5688 | get_visual_tbl_length () | |
5689 | { | |
5690 | int unit, i; | |
5691 | int n, n1; | |
5692 | char *s; | |
5693 | ||
63de6c74 | 5694 | /* Compute length of one field in line. */ |
8f04d345 | 5695 | s = (char *) alloca (INSN_LEN + 6); |
8c660648 JL |
5696 | sprintf (s, " %33s", "uname"); |
5697 | n1 = strlen (s); | |
5698 | ||
63de6c74 | 5699 | /* Compute length of one line. */ |
8c660648 JL |
5700 | n = strlen (";; "); |
5701 | n += n1; | |
5702 | for (unit = 0; unit < FUNCTION_UNITS_SIZE; unit++) | |
5703 | if (function_units[unit].bitmask & target_units) | |
5704 | for (i = 0; i < function_units[unit].multiplicity; i++) | |
5705 | n += n1; | |
5706 | n += n1; | |
5707 | n += strlen ("\n") + 2; | |
5708 | ||
63de6c74 | 5709 | /* Compute length of visualization string. */ |
8c660648 JL |
5710 | return (MAX_VISUAL_LINES * n); |
5711 | } | |
5712 | ||
63de6c74 | 5713 | /* Init block visualization debugging info. */ |
8c660648 JL |
5714 | |
5715 | static void | |
5716 | init_block_visualization () | |
5717 | { | |
5718 | strcpy (visual_tbl, ""); | |
5719 | n_visual_lines = 0; | |
5720 | n_vis_no_unit = 0; | |
5721 | } | |
5722 | ||
5723 | #define BUF_LEN 256 | |
5724 | ||
459b3825 MM |
5725 | static char * |
5726 | safe_concat (buf, cur, str) | |
5727 | char *buf; | |
5728 | char *cur; | |
5f06c983 | 5729 | const char *str; |
459b3825 | 5730 | { |
63de6c74 | 5731 | char *end = buf + BUF_LEN - 2; /* Leave room for null. */ |
459b3825 MM |
5732 | int c; |
5733 | ||
5734 | if (cur > end) | |
5735 | { | |
5736 | *end = '\0'; | |
5737 | return end; | |
5738 | } | |
5739 | ||
5740 | while (cur < end && (c = *str++) != '\0') | |
5741 | *cur++ = c; | |
5742 | ||
5743 | *cur = '\0'; | |
5744 | return cur; | |
5745 | } | |
5746 | ||
63de6c74 MH |
5747 | /* This recognizes rtx, I classified as expressions. These are always |
5748 | represent some action on values or results of other expression, that | |
5749 | may be stored in objects representing values. */ | |
8c660648 JL |
5750 | |
5751 | static void | |
5752 | print_exp (buf, x, verbose) | |
5753 | char *buf; | |
5754 | rtx x; | |
5755 | int verbose; | |
5756 | { | |
459b3825 | 5757 | char tmp[BUF_LEN]; |
5f06c983 | 5758 | const char *st[4]; |
459b3825 | 5759 | char *cur = buf; |
5f06c983 KG |
5760 | const char *fun = (char *)0; |
5761 | const char *sep; | |
459b3825 MM |
5762 | rtx op[4]; |
5763 | int i; | |
5764 | ||
5765 | for (i = 0; i < 4; i++) | |
5766 | { | |
5767 | st[i] = (char *)0; | |
5768 | op[i] = NULL_RTX; | |
5769 | } | |
8c660648 JL |
5770 | |
5771 | switch (GET_CODE (x)) | |
5772 | { | |
5773 | case PLUS: | |
459b3825 | 5774 | op[0] = XEXP (x, 0); |
f4b94256 RH |
5775 | if (GET_CODE (XEXP (x, 1)) == CONST_INT |
5776 | && INTVAL (XEXP (x, 1)) < 0) | |
5777 | { | |
5778 | st[1] = "-"; | |
5779 | op[1] = GEN_INT (-INTVAL (XEXP (x, 1))); | |
5780 | } | |
5781 | else | |
5782 | { | |
5783 | st[1] = "+"; | |
5784 | op[1] = XEXP (x, 1); | |
5785 | } | |
8c660648 JL |
5786 | break; |
5787 | case LO_SUM: | |
459b3825 MM |
5788 | op[0] = XEXP (x, 0); |
5789 | st[1] = "+low("; | |
5790 | op[1] = XEXP (x, 1); | |
5791 | st[2] = ")"; | |
8c660648 JL |
5792 | break; |
5793 | case MINUS: | |
459b3825 MM |
5794 | op[0] = XEXP (x, 0); |
5795 | st[1] = "-"; | |
5796 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5797 | break; |
5798 | case COMPARE: | |
459b3825 MM |
5799 | fun = "cmp"; |
5800 | op[0] = XEXP (x, 0); | |
5801 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5802 | break; |
5803 | case NEG: | |
459b3825 MM |
5804 | st[0] = "-"; |
5805 | op[0] = XEXP (x, 0); | |
8c660648 JL |
5806 | break; |
5807 | case MULT: | |
459b3825 MM |
5808 | op[0] = XEXP (x, 0); |
5809 | st[1] = "*"; | |
5810 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5811 | break; |
5812 | case DIV: | |
459b3825 MM |
5813 | op[0] = XEXP (x, 0); |
5814 | st[1] = "/"; | |
5815 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5816 | break; |
5817 | case UDIV: | |
459b3825 MM |
5818 | fun = "udiv"; |
5819 | op[0] = XEXP (x, 0); | |
5820 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5821 | break; |
5822 | case MOD: | |
459b3825 MM |
5823 | op[0] = XEXP (x, 0); |
5824 | st[1] = "%"; | |
5825 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5826 | break; |
5827 | case UMOD: | |
459b3825 MM |
5828 | fun = "umod"; |
5829 | op[0] = XEXP (x, 0); | |
5830 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5831 | break; |
5832 | case SMIN: | |
459b3825 MM |
5833 | fun = "smin"; |
5834 | op[0] = XEXP (x, 0); | |
5835 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5836 | break; |
5837 | case SMAX: | |
459b3825 MM |
5838 | fun = "smax"; |
5839 | op[0] = XEXP (x, 0); | |
5840 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5841 | break; |
5842 | case UMIN: | |
459b3825 MM |
5843 | fun = "umin"; |
5844 | op[0] = XEXP (x, 0); | |
5845 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5846 | break; |
5847 | case UMAX: | |
459b3825 MM |
5848 | fun = "umax"; |
5849 | op[0] = XEXP (x, 0); | |
5850 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5851 | break; |
5852 | case NOT: | |
459b3825 MM |
5853 | st[0] = "!"; |
5854 | op[0] = XEXP (x, 0); | |
8c660648 JL |
5855 | break; |
5856 | case AND: | |
459b3825 MM |
5857 | op[0] = XEXP (x, 0); |
5858 | st[1] = "&"; | |
5859 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5860 | break; |
5861 | case IOR: | |
459b3825 MM |
5862 | op[0] = XEXP (x, 0); |
5863 | st[1] = "|"; | |
5864 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5865 | break; |
5866 | case XOR: | |
459b3825 MM |
5867 | op[0] = XEXP (x, 0); |
5868 | st[1] = "^"; | |
5869 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5870 | break; |
5871 | case ASHIFT: | |
459b3825 MM |
5872 | op[0] = XEXP (x, 0); |
5873 | st[1] = "<<"; | |
5874 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5875 | break; |
5876 | case LSHIFTRT: | |
459b3825 MM |
5877 | op[0] = XEXP (x, 0); |
5878 | st[1] = " 0>>"; | |
5879 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5880 | break; |
5881 | case ASHIFTRT: | |
459b3825 MM |
5882 | op[0] = XEXP (x, 0); |
5883 | st[1] = ">>"; | |
5884 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5885 | break; |
5886 | case ROTATE: | |
459b3825 MM |
5887 | op[0] = XEXP (x, 0); |
5888 | st[1] = "<-<"; | |
5889 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5890 | break; |
5891 | case ROTATERT: | |
459b3825 MM |
5892 | op[0] = XEXP (x, 0); |
5893 | st[1] = ">->"; | |
5894 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5895 | break; |
5896 | case ABS: | |
459b3825 MM |
5897 | fun = "abs"; |
5898 | op[0] = XEXP (x, 0); | |
8c660648 JL |
5899 | break; |
5900 | case SQRT: | |
459b3825 MM |
5901 | fun = "sqrt"; |
5902 | op[0] = XEXP (x, 0); | |
8c660648 JL |
5903 | break; |
5904 | case FFS: | |
459b3825 MM |
5905 | fun = "ffs"; |
5906 | op[0] = XEXP (x, 0); | |
8c660648 JL |
5907 | break; |
5908 | case EQ: | |
459b3825 MM |
5909 | op[0] = XEXP (x, 0); |
5910 | st[1] = "=="; | |
5911 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5912 | break; |
5913 | case NE: | |
459b3825 MM |
5914 | op[0] = XEXP (x, 0); |
5915 | st[1] = "!="; | |
5916 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5917 | break; |
5918 | case GT: | |
459b3825 MM |
5919 | op[0] = XEXP (x, 0); |
5920 | st[1] = ">"; | |
5921 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5922 | break; |
5923 | case GTU: | |
459b3825 MM |
5924 | fun = "gtu"; |
5925 | op[0] = XEXP (x, 0); | |
5926 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5927 | break; |
5928 | case LT: | |
459b3825 MM |
5929 | op[0] = XEXP (x, 0); |
5930 | st[1] = "<"; | |
5931 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5932 | break; |
5933 | case LTU: | |
459b3825 MM |
5934 | fun = "ltu"; |
5935 | op[0] = XEXP (x, 0); | |
5936 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5937 | break; |
5938 | case GE: | |
459b3825 MM |
5939 | op[0] = XEXP (x, 0); |
5940 | st[1] = ">="; | |
5941 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5942 | break; |
5943 | case GEU: | |
459b3825 MM |
5944 | fun = "geu"; |
5945 | op[0] = XEXP (x, 0); | |
5946 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5947 | break; |
5948 | case LE: | |
459b3825 MM |
5949 | op[0] = XEXP (x, 0); |
5950 | st[1] = "<="; | |
5951 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5952 | break; |
5953 | case LEU: | |
459b3825 MM |
5954 | fun = "leu"; |
5955 | op[0] = XEXP (x, 0); | |
5956 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5957 | break; |
5958 | case SIGN_EXTRACT: | |
459b3825 MM |
5959 | fun = (verbose) ? "sign_extract" : "sxt"; |
5960 | op[0] = XEXP (x, 0); | |
5961 | op[1] = XEXP (x, 1); | |
5962 | op[2] = XEXP (x, 2); | |
8c660648 JL |
5963 | break; |
5964 | case ZERO_EXTRACT: | |
459b3825 MM |
5965 | fun = (verbose) ? "zero_extract" : "zxt"; |
5966 | op[0] = XEXP (x, 0); | |
5967 | op[1] = XEXP (x, 1); | |
5968 | op[2] = XEXP (x, 2); | |
8c660648 JL |
5969 | break; |
5970 | case SIGN_EXTEND: | |
459b3825 MM |
5971 | fun = (verbose) ? "sign_extend" : "sxn"; |
5972 | op[0] = XEXP (x, 0); | |
8c660648 JL |
5973 | break; |
5974 | case ZERO_EXTEND: | |
459b3825 MM |
5975 | fun = (verbose) ? "zero_extend" : "zxn"; |
5976 | op[0] = XEXP (x, 0); | |
8c660648 JL |
5977 | break; |
5978 | case FLOAT_EXTEND: | |
459b3825 MM |
5979 | fun = (verbose) ? "float_extend" : "fxn"; |
5980 | op[0] = XEXP (x, 0); | |
8c660648 JL |
5981 | break; |
5982 | case TRUNCATE: | |
459b3825 MM |
5983 | fun = (verbose) ? "trunc" : "trn"; |
5984 | op[0] = XEXP (x, 0); | |
8c660648 JL |
5985 | break; |
5986 | case FLOAT_TRUNCATE: | |
459b3825 MM |
5987 | fun = (verbose) ? "float_trunc" : "ftr"; |
5988 | op[0] = XEXP (x, 0); | |
8c660648 JL |
5989 | break; |
5990 | case FLOAT: | |
459b3825 MM |
5991 | fun = (verbose) ? "float" : "flt"; |
5992 | op[0] = XEXP (x, 0); | |
8c660648 JL |
5993 | break; |
5994 | case UNSIGNED_FLOAT: | |
459b3825 MM |
5995 | fun = (verbose) ? "uns_float" : "ufl"; |
5996 | op[0] = XEXP (x, 0); | |
8c660648 JL |
5997 | break; |
5998 | case FIX: | |
459b3825 MM |
5999 | fun = "fix"; |
6000 | op[0] = XEXP (x, 0); | |
8c660648 JL |
6001 | break; |
6002 | case UNSIGNED_FIX: | |
459b3825 MM |
6003 | fun = (verbose) ? "uns_fix" : "ufx"; |
6004 | op[0] = XEXP (x, 0); | |
8c660648 JL |
6005 | break; |
6006 | case PRE_DEC: | |
459b3825 MM |
6007 | st[0] = "--"; |
6008 | op[0] = XEXP (x, 0); | |
8c660648 JL |
6009 | break; |
6010 | case PRE_INC: | |
459b3825 MM |
6011 | st[0] = "++"; |
6012 | op[0] = XEXP (x, 0); | |
8c660648 JL |
6013 | break; |
6014 | case POST_DEC: | |
459b3825 MM |
6015 | op[0] = XEXP (x, 0); |
6016 | st[1] = "--"; | |
8c660648 JL |
6017 | break; |
6018 | case POST_INC: | |
459b3825 MM |
6019 | op[0] = XEXP (x, 0); |
6020 | st[1] = "++"; | |
8c660648 JL |
6021 | break; |
6022 | case CALL: | |
459b3825 MM |
6023 | st[0] = "call "; |
6024 | op[0] = XEXP (x, 0); | |
8c660648 JL |
6025 | if (verbose) |
6026 | { | |
459b3825 MM |
6027 | st[1] = " argc:"; |
6028 | op[1] = XEXP (x, 1); | |
8c660648 | 6029 | } |
8c660648 JL |
6030 | break; |
6031 | case IF_THEN_ELSE: | |
459b3825 MM |
6032 | st[0] = "{("; |
6033 | op[0] = XEXP (x, 0); | |
6034 | st[1] = ")?"; | |
6035 | op[1] = XEXP (x, 1); | |
6036 | st[2] = ":"; | |
6037 | op[2] = XEXP (x, 2); | |
6038 | st[3] = "}"; | |
8c660648 JL |
6039 | break; |
6040 | case TRAP_IF: | |
459b3825 MM |
6041 | fun = "trap_if"; |
6042 | op[0] = TRAP_CONDITION (x); | |
8c660648 JL |
6043 | break; |
6044 | case UNSPEC: | |
8c660648 JL |
6045 | case UNSPEC_VOLATILE: |
6046 | { | |
459b3825 MM |
6047 | cur = safe_concat (buf, cur, "unspec"); |
6048 | if (GET_CODE (x) == UNSPEC_VOLATILE) | |
6049 | cur = safe_concat (buf, cur, "/v"); | |
6050 | cur = safe_concat (buf, cur, "["); | |
6051 | sep = ""; | |
8c660648 JL |
6052 | for (i = 0; i < XVECLEN (x, 0); i++) |
6053 | { | |
459b3825 MM |
6054 | print_pattern (tmp, XVECEXP (x, 0, i), verbose); |
6055 | cur = safe_concat (buf, cur, sep); | |
6056 | cur = safe_concat (buf, cur, tmp); | |
6057 | sep = ","; | |
8c660648 | 6058 | } |
459b3825 MM |
6059 | cur = safe_concat (buf, cur, "] "); |
6060 | sprintf (tmp, "%d", XINT (x, 1)); | |
6061 | cur = safe_concat (buf, cur, tmp); | |
8c660648 JL |
6062 | } |
6063 | break; | |
6064 | default: | |
63de6c74 | 6065 | /* If (verbose) debug_rtx (x); */ |
53c0919d | 6066 | st[0] = GET_RTX_NAME (GET_CODE (x)); |
459b3825 MM |
6067 | break; |
6068 | } | |
6069 | ||
63de6c74 | 6070 | /* Print this as a function? */ |
459b3825 MM |
6071 | if (fun) |
6072 | { | |
6073 | cur = safe_concat (buf, cur, fun); | |
6074 | cur = safe_concat (buf, cur, "("); | |
6075 | } | |
6076 | ||
6077 | for (i = 0; i < 4; i++) | |
6078 | { | |
6079 | if (st[i]) | |
6080 | cur = safe_concat (buf, cur, st[i]); | |
6081 | ||
6082 | if (op[i]) | |
6083 | { | |
6084 | if (fun && i != 0) | |
6085 | cur = safe_concat (buf, cur, ","); | |
6086 | ||
6087 | print_value (tmp, op[i], verbose); | |
6088 | cur = safe_concat (buf, cur, tmp); | |
6089 | } | |
8c660648 | 6090 | } |
459b3825 MM |
6091 | |
6092 | if (fun) | |
6093 | cur = safe_concat (buf, cur, ")"); | |
6094 | } /* print_exp */ | |
8c660648 | 6095 | |
63de6c74 MH |
6096 | /* Prints rtxes, I customly classified as values. They're constants, |
6097 | registers, labels, symbols and memory accesses. */ | |
8c660648 JL |
6098 | |
6099 | static void | |
6100 | print_value (buf, x, verbose) | |
6101 | char *buf; | |
6102 | rtx x; | |
6103 | int verbose; | |
6104 | { | |
6105 | char t[BUF_LEN]; | |
459b3825 | 6106 | char *cur = buf; |
8c660648 JL |
6107 | |
6108 | switch (GET_CODE (x)) | |
6109 | { | |
6110 | case CONST_INT: | |
f4b94256 | 6111 | sprintf (t, HOST_WIDE_INT_PRINT_HEX, INTVAL (x)); |
459b3825 | 6112 | cur = safe_concat (buf, cur, t); |
8c660648 JL |
6113 | break; |
6114 | case CONST_DOUBLE: | |
459b3825 MM |
6115 | sprintf (t, "<0x%lx,0x%lx>", (long)XWINT (x, 2), (long)XWINT (x, 3)); |
6116 | cur = safe_concat (buf, cur, t); | |
8c660648 JL |
6117 | break; |
6118 | case CONST_STRING: | |
459b3825 MM |
6119 | cur = safe_concat (buf, cur, "\""); |
6120 | cur = safe_concat (buf, cur, XSTR (x, 0)); | |
6121 | cur = safe_concat (buf, cur, "\""); | |
8c660648 JL |
6122 | break; |
6123 | case SYMBOL_REF: | |
459b3825 MM |
6124 | cur = safe_concat (buf, cur, "`"); |
6125 | cur = safe_concat (buf, cur, XSTR (x, 0)); | |
6126 | cur = safe_concat (buf, cur, "'"); | |
8c660648 JL |
6127 | break; |
6128 | case LABEL_REF: | |
459b3825 MM |
6129 | sprintf (t, "L%d", INSN_UID (XEXP (x, 0))); |
6130 | cur = safe_concat (buf, cur, t); | |
8c660648 JL |
6131 | break; |
6132 | case CONST: | |
459b3825 MM |
6133 | print_value (t, XEXP (x, 0), verbose); |
6134 | cur = safe_concat (buf, cur, "const("); | |
6135 | cur = safe_concat (buf, cur, t); | |
6136 | cur = safe_concat (buf, cur, ")"); | |
8c660648 JL |
6137 | break; |
6138 | case HIGH: | |
459b3825 MM |
6139 | print_value (t, XEXP (x, 0), verbose); |
6140 | cur = safe_concat (buf, cur, "high("); | |
6141 | cur = safe_concat (buf, cur, t); | |
6142 | cur = safe_concat (buf, cur, ")"); | |
8c660648 JL |
6143 | break; |
6144 | case REG: | |
459b3825 MM |
6145 | if (REGNO (x) < FIRST_PSEUDO_REGISTER) |
6146 | { | |
6147 | int c = reg_names[ REGNO (x) ][0]; | |
6148 | if (c >= '0' && c <= '9') | |
6149 | cur = safe_concat (buf, cur, "%"); | |
6150 | ||
6151 | cur = safe_concat (buf, cur, reg_names[ REGNO (x) ]); | |
6152 | } | |
8c660648 | 6153 | else |
459b3825 MM |
6154 | { |
6155 | sprintf (t, "r%d", REGNO (x)); | |
6156 | cur = safe_concat (buf, cur, t); | |
6157 | } | |
8c660648 JL |
6158 | break; |
6159 | case SUBREG: | |
459b3825 MM |
6160 | print_value (t, SUBREG_REG (x), verbose); |
6161 | cur = safe_concat (buf, cur, t); | |
6b879bcc | 6162 | sprintf (t, "#%d", SUBREG_WORD (x)); |
459b3825 | 6163 | cur = safe_concat (buf, cur, t); |
8c660648 JL |
6164 | break; |
6165 | case SCRATCH: | |
459b3825 | 6166 | cur = safe_concat (buf, cur, "scratch"); |
8c660648 JL |
6167 | break; |
6168 | case CC0: | |
459b3825 | 6169 | cur = safe_concat (buf, cur, "cc0"); |
8c660648 JL |
6170 | break; |
6171 | case PC: | |
459b3825 | 6172 | cur = safe_concat (buf, cur, "pc"); |
8c660648 JL |
6173 | break; |
6174 | case MEM: | |
6175 | print_value (t, XEXP (x, 0), verbose); | |
459b3825 MM |
6176 | cur = safe_concat (buf, cur, "["); |
6177 | cur = safe_concat (buf, cur, t); | |
6178 | cur = safe_concat (buf, cur, "]"); | |
8c660648 JL |
6179 | break; |
6180 | default: | |
459b3825 MM |
6181 | print_exp (t, x, verbose); |
6182 | cur = safe_concat (buf, cur, t); | |
6183 | break; | |
8c660648 JL |
6184 | } |
6185 | } /* print_value */ | |
6186 | ||
63de6c74 | 6187 | /* The next step in insn detalization, its pattern recognition. */ |
8c660648 JL |
6188 | |
6189 | static void | |
6190 | print_pattern (buf, x, verbose) | |
6191 | char *buf; | |
6192 | rtx x; | |
6193 | int verbose; | |
6194 | { | |
6195 | char t1[BUF_LEN], t2[BUF_LEN], t3[BUF_LEN]; | |
6196 | ||
6197 | switch (GET_CODE (x)) | |
6198 | { | |
6199 | case SET: | |
6200 | print_value (t1, SET_DEST (x), verbose); | |
6201 | print_value (t2, SET_SRC (x), verbose); | |
6202 | sprintf (buf, "%s=%s", t1, t2); | |
6203 | break; | |
6204 | case RETURN: | |
6205 | sprintf (buf, "return"); | |
6206 | break; | |
6207 | case CALL: | |
6208 | print_exp (buf, x, verbose); | |
6209 | break; | |
6210 | case CLOBBER: | |
6211 | print_value (t1, XEXP (x, 0), verbose); | |
6212 | sprintf (buf, "clobber %s", t1); | |
6213 | break; | |
6214 | case USE: | |
6215 | print_value (t1, XEXP (x, 0), verbose); | |
6216 | sprintf (buf, "use %s", t1); | |
6217 | break; | |
6218 | case PARALLEL: | |
6219 | { | |
6220 | int i; | |
6221 | ||
6222 | sprintf (t1, "{"); | |
6223 | for (i = 0; i < XVECLEN (x, 0); i++) | |
6224 | { | |
6225 | print_pattern (t2, XVECEXP (x, 0, i), verbose); | |
6226 | sprintf (t3, "%s%s;", t1, t2); | |
6227 | strcpy (t1, t3); | |
6228 | } | |
6229 | sprintf (buf, "%s}", t1); | |
6230 | } | |
6231 | break; | |
6232 | case SEQUENCE: | |
6233 | { | |
6234 | int i; | |
6235 | ||
6236 | sprintf (t1, "%%{"); | |
6237 | for (i = 0; i < XVECLEN (x, 0); i++) | |
6238 | { | |
6239 | print_insn (t2, XVECEXP (x, 0, i), verbose); | |
6240 | sprintf (t3, "%s%s;", t1, t2); | |
6241 | strcpy (t1, t3); | |
6242 | } | |
6243 | sprintf (buf, "%s%%}", t1); | |
6244 | } | |
6245 | break; | |
6246 | case ASM_INPUT: | |
c4fa3460 | 6247 | sprintf (buf, "asm {%s}", XSTR (x, 0)); |
8c660648 JL |
6248 | break; |
6249 | case ADDR_VEC: | |
6250 | break; | |
6251 | case ADDR_DIFF_VEC: | |
6252 | print_value (buf, XEXP (x, 0), verbose); | |
6253 | break; | |
6254 | case TRAP_IF: | |
6255 | print_value (t1, TRAP_CONDITION (x), verbose); | |
6256 | sprintf (buf, "trap_if %s", t1); | |
6257 | break; | |
6258 | case UNSPEC: | |
6259 | { | |
6260 | int i; | |
6261 | ||
6262 | sprintf (t1, "unspec{"); | |
6263 | for (i = 0; i < XVECLEN (x, 0); i++) | |
6264 | { | |
6265 | print_pattern (t2, XVECEXP (x, 0, i), verbose); | |
6266 | sprintf (t3, "%s%s;", t1, t2); | |
6267 | strcpy (t1, t3); | |
6268 | } | |
6269 | sprintf (buf, "%s}", t1); | |
6270 | } | |
6271 | break; | |
6272 | case UNSPEC_VOLATILE: | |
6273 | { | |
6274 | int i; | |
6275 | ||
6276 | sprintf (t1, "unspec/v{"); | |
6277 | for (i = 0; i < XVECLEN (x, 0); i++) | |
6278 | { | |
6279 | print_pattern (t2, XVECEXP (x, 0, i), verbose); | |
6280 | sprintf (t3, "%s%s;", t1, t2); | |
6281 | strcpy (t1, t3); | |
6282 | } | |
6283 | sprintf (buf, "%s}", t1); | |
6284 | } | |
6285 | break; | |
6286 | default: | |
6287 | print_value (buf, x, verbose); | |
6288 | } | |
6289 | } /* print_pattern */ | |
6290 | ||
6291 | /* This is the main function in rtl visualization mechanism. It | |
6292 | accepts an rtx and tries to recognize it as an insn, then prints it | |
63de6c74 MH |
6293 | properly in human readable form, resembling assembler mnemonics. |
6294 | For every insn it prints its UID and BB the insn belongs too. | |
6295 | (Probably the last "option" should be extended somehow, since it | |
6296 | depends now on sched.c inner variables ...) */ | |
8c660648 JL |
6297 | |
6298 | static void | |
6299 | print_insn (buf, x, verbose) | |
6300 | char *buf; | |
6301 | rtx x; | |
6302 | int verbose; | |
6303 | { | |
6304 | char t[BUF_LEN]; | |
6305 | rtx insn = x; | |
6306 | ||
6307 | switch (GET_CODE (x)) | |
6308 | { | |
6309 | case INSN: | |
6310 | print_pattern (t, PATTERN (x), verbose); | |
6311 | if (verbose) | |
6312 | sprintf (buf, "b%d: i% 4d: %s", INSN_BB (x), | |
6313 | INSN_UID (x), t); | |
6314 | else | |
6315 | sprintf (buf, "%-4d %s", INSN_UID (x), t); | |
6316 | break; | |
6317 | case JUMP_INSN: | |
6318 | print_pattern (t, PATTERN (x), verbose); | |
6319 | if (verbose) | |
6320 | sprintf (buf, "b%d: i% 4d: jump %s", INSN_BB (x), | |
6321 | INSN_UID (x), t); | |
6322 | else | |
6323 | sprintf (buf, "%-4d %s", INSN_UID (x), t); | |
6324 | break; | |
6325 | case CALL_INSN: | |
6326 | x = PATTERN (insn); | |
6327 | if (GET_CODE (x) == PARALLEL) | |
6328 | { | |
6329 | x = XVECEXP (x, 0, 0); | |
6330 | print_pattern (t, x, verbose); | |
6331 | } | |
6332 | else | |
6333 | strcpy (t, "call <...>"); | |
6334 | if (verbose) | |
6335 | sprintf (buf, "b%d: i% 4d: %s", INSN_BB (insn), | |
6336 | INSN_UID (insn), t); | |
6337 | else | |
6338 | sprintf (buf, "%-4d %s", INSN_UID (insn), t); | |
6339 | break; | |
6340 | case CODE_LABEL: | |
6341 | sprintf (buf, "L%d:", INSN_UID (x)); | |
6342 | break; | |
6343 | case BARRIER: | |
6344 | sprintf (buf, "i% 4d: barrier", INSN_UID (x)); | |
6345 | break; | |
6346 | case NOTE: | |
6347 | if (NOTE_LINE_NUMBER (x) > 0) | |
6348 | sprintf (buf, "%4d note \"%s\" %d", INSN_UID (x), | |
6349 | NOTE_SOURCE_FILE (x), NOTE_LINE_NUMBER (x)); | |
6350 | else | |
6351 | sprintf (buf, "%4d %s", INSN_UID (x), | |
6352 | GET_NOTE_INSN_NAME (NOTE_LINE_NUMBER (x))); | |
6353 | break; | |
6354 | default: | |
6355 | if (verbose) | |
6356 | { | |
6357 | sprintf (buf, "Not an INSN at all\n"); | |
6358 | debug_rtx (x); | |
6359 | } | |
6360 | else | |
6361 | sprintf (buf, "i%-4d <What?>", INSN_UID (x)); | |
6362 | } | |
6363 | } /* print_insn */ | |
6364 | ||
63de6c74 | 6365 | /* Print visualization debugging info. */ |
8c660648 JL |
6366 | |
6367 | static void | |
6368 | print_block_visualization (b, s) | |
6369 | int b; | |
5f06c983 | 6370 | const char *s; |
8c660648 JL |
6371 | { |
6372 | int unit, i; | |
8c660648 | 6373 | |
63de6c74 | 6374 | /* Print header. */ |
8c660648 JL |
6375 | fprintf (dump, "\n;; ==================== scheduling visualization for block %d %s \n", b, s); |
6376 | ||
63de6c74 | 6377 | /* Print names of units. */ |
2f308fec | 6378 | fprintf (dump, ";; %-8s", "clock"); |
8c660648 JL |
6379 | for (unit = 0; unit < FUNCTION_UNITS_SIZE; unit++) |
6380 | if (function_units[unit].bitmask & target_units) | |
6381 | for (i = 0; i < function_units[unit].multiplicity; i++) | |
2f308fec RH |
6382 | fprintf (dump, " %-33s", function_units[unit].name); |
6383 | fprintf (dump, " %-8s\n", "no-unit"); | |
6384 | ||
6385 | fprintf (dump, ";; %-8s", "====="); | |
6386 | for (unit = 0; unit < FUNCTION_UNITS_SIZE; unit++) | |
6387 | if (function_units[unit].bitmask & target_units) | |
6388 | for (i = 0; i < function_units[unit].multiplicity; i++) | |
6389 | fprintf (dump, " %-33s", "=============================="); | |
6390 | fprintf (dump, " %-8s\n", "======="); | |
8c660648 | 6391 | |
63de6c74 | 6392 | /* Print insns in each cycle. */ |
8c660648 JL |
6393 | fprintf (dump, "%s\n", visual_tbl); |
6394 | } | |
6395 | ||
63de6c74 | 6396 | /* Print insns in the 'no_unit' column of visualization. */ |
8c660648 JL |
6397 | |
6398 | static void | |
6399 | visualize_no_unit (insn) | |
6400 | rtx insn; | |
6401 | { | |
6402 | vis_no_unit[n_vis_no_unit] = insn; | |
6403 | n_vis_no_unit++; | |
6404 | } | |
6405 | ||
6406 | /* Print insns scheduled in clock, for visualization. */ | |
6407 | ||
6408 | static void | |
6409 | visualize_scheduled_insns (b, clock) | |
6410 | int b, clock; | |
6411 | { | |
6412 | int i, unit; | |
6413 | ||
63de6c74 | 6414 | /* If no more room, split table into two. */ |
8c660648 JL |
6415 | if (n_visual_lines >= MAX_VISUAL_LINES) |
6416 | { | |
6417 | print_block_visualization (b, "(incomplete)"); | |
6418 | init_block_visualization (); | |
6419 | } | |
6420 | ||
6421 | n_visual_lines++; | |
6422 | ||
6423 | sprintf (visual_tbl + strlen (visual_tbl), ";; %-8d", clock); | |
6424 | for (unit = 0; unit < FUNCTION_UNITS_SIZE; unit++) | |
6425 | if (function_units[unit].bitmask & target_units) | |
6426 | for (i = 0; i < function_units[unit].multiplicity; i++) | |
6427 | { | |
6428 | int instance = unit + i * FUNCTION_UNITS_SIZE; | |
6429 | rtx insn = unit_last_insn[instance]; | |
6430 | ||
63de6c74 | 6431 | /* Print insns that still keep the unit busy. */ |
8c660648 JL |
6432 | if (insn && |
6433 | actual_hazard_this_instance (unit, instance, insn, clock, 0)) | |
6434 | { | |
6435 | char str[BUF_LEN]; | |
6436 | print_insn (str, insn, 0); | |
6437 | str[INSN_LEN] = '\0'; | |
6438 | sprintf (visual_tbl + strlen (visual_tbl), " %-33s", str); | |
6439 | } | |
6440 | else | |
6441 | sprintf (visual_tbl + strlen (visual_tbl), " %-33s", "------------------------------"); | |
6442 | } | |
6443 | ||
63de6c74 | 6444 | /* Print insns that are not assigned to any unit. */ |
8c660648 JL |
6445 | for (i = 0; i < n_vis_no_unit; i++) |
6446 | sprintf (visual_tbl + strlen (visual_tbl), " %-8d", | |
6447 | INSN_UID (vis_no_unit[i])); | |
6448 | n_vis_no_unit = 0; | |
6449 | ||
6450 | sprintf (visual_tbl + strlen (visual_tbl), "\n"); | |
6451 | } | |
6452 | ||
63de6c74 | 6453 | /* Print stalled cycles. */ |
8c660648 JL |
6454 | |
6455 | static void | |
6456 | visualize_stall_cycles (b, stalls) | |
6457 | int b, stalls; | |
6458 | { | |
6459 | int i; | |
6460 | ||
63de6c74 | 6461 | /* If no more room, split table into two. */ |
8c660648 JL |
6462 | if (n_visual_lines >= MAX_VISUAL_LINES) |
6463 | { | |
6464 | print_block_visualization (b, "(incomplete)"); | |
6465 | init_block_visualization (); | |
6466 | } | |
6467 | ||
6468 | n_visual_lines++; | |
6469 | ||
6470 | sprintf (visual_tbl + strlen (visual_tbl), ";; "); | |
6471 | for (i = 0; i < stalls; i++) | |
6472 | sprintf (visual_tbl + strlen (visual_tbl), "."); | |
6473 | sprintf (visual_tbl + strlen (visual_tbl), "\n"); | |
6474 | } | |
6475 | ||
63de6c74 | 6476 | /* move_insn1: Remove INSN from insn chain, and link it after LAST insn. */ |
8c660648 JL |
6477 | |
6478 | static rtx | |
6479 | move_insn1 (insn, last) | |
6480 | rtx insn, last; | |
6481 | { | |
6482 | NEXT_INSN (PREV_INSN (insn)) = NEXT_INSN (insn); | |
6483 | PREV_INSN (NEXT_INSN (insn)) = PREV_INSN (insn); | |
6484 | ||
6485 | NEXT_INSN (insn) = NEXT_INSN (last); | |
6486 | PREV_INSN (NEXT_INSN (last)) = insn; | |
6487 | ||
6488 | NEXT_INSN (last) = insn; | |
6489 | PREV_INSN (insn) = last; | |
6490 | ||
6491 | return insn; | |
6492 | } | |
6493 | ||
6494 | /* Search INSN for fake REG_DEAD note pairs for NOTE_INSN_SETJMP, | |
6495 | NOTE_INSN_{LOOP,EHREGION}_{BEG,END}; and convert them back into | |
6496 | NOTEs. The REG_DEAD note following first one is contains the saved | |
6497 | value for NOTE_BLOCK_NUMBER which is useful for | |
6498 | NOTE_INSN_EH_REGION_{BEG,END} NOTEs. LAST is the last instruction | |
6499 | output by the instruction scheduler. Return the new value of LAST. */ | |
6500 | ||
6501 | static rtx | |
6502 | reemit_notes (insn, last) | |
6503 | rtx insn; | |
6504 | rtx last; | |
6505 | { | |
6506 | rtx note, retval; | |
6507 | ||
6508 | retval = last; | |
6509 | for (note = REG_NOTES (insn); note; note = XEXP (note, 1)) | |
6510 | { | |
6511 | if (REG_NOTE_KIND (note) == REG_DEAD | |
6512 | && GET_CODE (XEXP (note, 0)) == CONST_INT) | |
6513 | { | |
6dfdecdb RH |
6514 | int note_type = INTVAL (XEXP (note, 0)); |
6515 | if (note_type == NOTE_INSN_SETJMP) | |
8c660648 | 6516 | { |
6dfdecdb | 6517 | retval = emit_note_after (NOTE_INSN_SETJMP, insn); |
8c660648 JL |
6518 | CONST_CALL_P (retval) = CONST_CALL_P (note); |
6519 | remove_note (insn, note); | |
6520 | note = XEXP (note, 1); | |
6521 | } | |
6dfdecdb RH |
6522 | else if (note_type == NOTE_INSN_RANGE_START |
6523 | || note_type == NOTE_INSN_RANGE_END) | |
6524 | { | |
6525 | last = emit_note_before (note_type, last); | |
6526 | remove_note (insn, note); | |
6527 | note = XEXP (note, 1); | |
6528 | NOTE_RANGE_INFO (last) = XEXP (note, 0); | |
6529 | } | |
8c660648 JL |
6530 | else |
6531 | { | |
19699da4 | 6532 | last = emit_note_before (note_type, last); |
8c660648 JL |
6533 | remove_note (insn, note); |
6534 | note = XEXP (note, 1); | |
6535 | NOTE_BLOCK_NUMBER (last) = INTVAL (XEXP (note, 0)); | |
6536 | } | |
6537 | remove_note (insn, note); | |
6538 | } | |
6539 | } | |
6540 | return retval; | |
6541 | } | |
6542 | ||
6543 | /* Move INSN, and all insns which should be issued before it, | |
c9e03727 JL |
6544 | due to SCHED_GROUP_P flag. Reemit notes if needed. |
6545 | ||
6546 | Return the last insn emitted by the scheduler, which is the | |
6547 | return value from the first call to reemit_notes. */ | |
8c660648 JL |
6548 | |
6549 | static rtx | |
6550 | move_insn (insn, last) | |
6551 | rtx insn, last; | |
6552 | { | |
c9e03727 | 6553 | rtx retval = NULL; |
8c660648 | 6554 | |
c9e03727 JL |
6555 | /* If INSN has SCHED_GROUP_P set, then issue it and any other |
6556 | insns with SCHED_GROUP_P set first. */ | |
8c660648 JL |
6557 | while (SCHED_GROUP_P (insn)) |
6558 | { | |
6559 | rtx prev = PREV_INSN (insn); | |
c9e03727 JL |
6560 | |
6561 | /* Move a SCHED_GROUP_P insn. */ | |
8c660648 | 6562 | move_insn1 (insn, last); |
c9e03727 JL |
6563 | /* If this is the first call to reemit_notes, then record |
6564 | its return value. */ | |
6565 | if (retval == NULL_RTX) | |
6566 | retval = reemit_notes (insn, insn); | |
6567 | else | |
6568 | reemit_notes (insn, insn); | |
8c660648 JL |
6569 | insn = prev; |
6570 | } | |
6571 | ||
c9e03727 | 6572 | /* Now move the first non SCHED_GROUP_P insn. */ |
8c660648 | 6573 | move_insn1 (insn, last); |
c9e03727 JL |
6574 | |
6575 | /* If this is the first call to reemit_notes, then record | |
6576 | its return value. */ | |
6577 | if (retval == NULL_RTX) | |
6578 | retval = reemit_notes (insn, insn); | |
6579 | else | |
6580 | reemit_notes (insn, insn); | |
6581 | ||
6582 | return retval; | |
8c660648 JL |
6583 | } |
6584 | ||
6585 | /* Return an insn which represents a SCHED_GROUP, which is | |
6586 | the last insn in the group. */ | |
6587 | ||
6588 | static rtx | |
6589 | group_leader (insn) | |
6590 | rtx insn; | |
6591 | { | |
6592 | rtx prev; | |
6593 | ||
6594 | do | |
6595 | { | |
6596 | prev = insn; | |
6597 | insn = next_nonnote_insn (insn); | |
6598 | } | |
6599 | while (insn && SCHED_GROUP_P (insn) && (GET_CODE (insn) != CODE_LABEL)); | |
6600 | ||
6601 | return prev; | |
6602 | } | |
6603 | ||
6604 | /* Use forward list scheduling to rearrange insns of block BB in region RGN, | |
6605 | possibly bringing insns from subsequent blocks in the same region. | |
6606 | Return number of insns scheduled. */ | |
6607 | ||
6608 | static int | |
5835e573 | 6609 | schedule_block (bb, rgn_n_insns) |
8c660648 | 6610 | int bb; |
8c660648 JL |
6611 | int rgn_n_insns; |
6612 | { | |
6613 | /* Local variables. */ | |
6614 | rtx insn, last; | |
6615 | rtx *ready; | |
8c660648 JL |
6616 | int n_ready = 0; |
6617 | int can_issue_more; | |
6618 | ||
63de6c74 | 6619 | /* Flow block of this bb. */ |
8c660648 JL |
6620 | int b = BB_TO_BLOCK (bb); |
6621 | ||
6622 | /* target_n_insns == number of insns in b before scheduling starts. | |
6623 | sched_target_n_insns == how many of b's insns were scheduled. | |
63de6c74 | 6624 | sched_n_insns == how many insns were scheduled in b. */ |
8c660648 JL |
6625 | int target_n_insns = 0; |
6626 | int sched_target_n_insns = 0; | |
6627 | int sched_n_insns = 0; | |
6628 | ||
6629 | #define NEED_NOTHING 0 | |
6630 | #define NEED_HEAD 1 | |
6631 | #define NEED_TAIL 2 | |
6632 | int new_needs; | |
6633 | ||
63de6c74 | 6634 | /* Head/tail info for this block. */ |
8c660648 JL |
6635 | rtx prev_head; |
6636 | rtx next_tail; | |
6637 | rtx head; | |
6638 | rtx tail; | |
6639 | int bb_src; | |
6640 | ||
484df988 JL |
6641 | /* We used to have code to avoid getting parameters moved from hard |
6642 | argument registers into pseudos. | |
8c660648 | 6643 | |
484df988 JL |
6644 | However, it was removed when it proved to be of marginal benefit |
6645 | and caused problems because schedule_block and compute_forward_dependences | |
6646 | had different notions of what the "head" insn was. */ | |
6647 | get_block_head_tail (bb, &head, &tail); | |
8c660648 | 6648 | |
1447b516 JL |
6649 | /* Interblock scheduling could have moved the original head insn from this |
6650 | block into a proceeding block. This may also cause schedule_block and | |
6651 | compute_forward_dependences to have different notions of what the | |
6652 | "head" insn was. | |
6653 | ||
6654 | If the interblock movement happened to make this block start with | |
6655 | some notes (LOOP, EH or SETJMP) before the first real insn, then | |
6656 | HEAD will have various special notes attached to it which must be | |
6657 | removed so that we don't end up with extra copies of the notes. */ | |
6658 | if (GET_RTX_CLASS (GET_CODE (head)) == 'i') | |
6659 | { | |
6660 | rtx note; | |
6661 | ||
6662 | for (note = REG_NOTES (head); note; note = XEXP (note, 1)) | |
6663 | if (REG_NOTE_KIND (note) == REG_DEAD | |
6664 | && GET_CODE (XEXP (note, 0)) == CONST_INT) | |
6665 | remove_note (head, note); | |
6666 | } | |
6667 | ||
8c660648 JL |
6668 | next_tail = NEXT_INSN (tail); |
6669 | prev_head = PREV_INSN (head); | |
6670 | ||
6671 | /* If the only insn left is a NOTE or a CODE_LABEL, then there is no need | |
6672 | to schedule this block. */ | |
6673 | if (head == tail | |
6674 | && (GET_RTX_CLASS (GET_CODE (head)) != 'i')) | |
6675 | return (sched_n_insns); | |
6676 | ||
63de6c74 | 6677 | /* Debug info. */ |
8c660648 JL |
6678 | if (sched_verbose) |
6679 | { | |
6680 | fprintf (dump, ";; ======================================================\n"); | |
6681 | fprintf (dump, | |
6682 | ";; -- basic block %d from %d to %d -- %s reload\n", | |
3b413743 | 6683 | b, INSN_UID (BLOCK_HEAD (b)), INSN_UID (BLOCK_END (b)), |
8c660648 JL |
6684 | (reload_completed ? "after" : "before")); |
6685 | fprintf (dump, ";; ======================================================\n"); | |
8c660648 JL |
6686 | fprintf (dump, "\n"); |
6687 | ||
6688 | visual_tbl = (char *) alloca (get_visual_tbl_length ()); | |
6689 | init_block_visualization (); | |
6690 | } | |
6691 | ||
63de6c74 | 6692 | /* Remove remaining note insns from the block, save them in |
8c660648 JL |
6693 | note_list. These notes are restored at the end of |
6694 | schedule_block (). */ | |
6695 | note_list = 0; | |
6696 | rm_other_notes (head, tail); | |
6697 | ||
6698 | target_bb = bb; | |
6699 | ||
63de6c74 | 6700 | /* Prepare current target block info. */ |
8c660648 JL |
6701 | if (current_nr_blocks > 1) |
6702 | { | |
63de6c74 MH |
6703 | candidate_table = (candidate *) alloca (current_nr_blocks |
6704 | * sizeof (candidate)); | |
8c660648 JL |
6705 | |
6706 | bblst_last = 0; | |
6707 | /* ??? It is not clear why bblst_size is computed this way. The original | |
6708 | number was clearly too small as it resulted in compiler failures. | |
6709 | Multiplying by the original number by 2 (to account for update_bbs | |
6710 | members) seems to be a reasonable solution. */ | |
6711 | /* ??? Or perhaps there is a bug somewhere else in this file? */ | |
6712 | bblst_size = (current_nr_blocks - bb) * rgn_nr_edges * 2; | |
6713 | bblst_table = (int *) alloca (bblst_size * sizeof (int)); | |
6714 | ||
6715 | bitlst_table_last = 0; | |
6716 | bitlst_table_size = rgn_nr_edges; | |
6717 | bitlst_table = (int *) alloca (rgn_nr_edges * sizeof (int)); | |
6718 | ||
6719 | compute_trg_info (bb); | |
6720 | } | |
6721 | ||
6722 | clear_units (); | |
6723 | ||
63de6c74 | 6724 | /* Allocate the ready list. */ |
8c660648 JL |
6725 | ready = (rtx *) alloca ((rgn_n_insns + 1) * sizeof (rtx)); |
6726 | ||
6727 | /* Print debugging information. */ | |
6728 | if (sched_verbose >= 5) | |
6729 | debug_dependencies (); | |
6730 | ||
6731 | ||
6732 | /* Initialize ready list with all 'ready' insns in target block. | |
6733 | Count number of insns in the target block being scheduled. */ | |
6734 | n_ready = 0; | |
6735 | for (insn = head; insn != next_tail; insn = NEXT_INSN (insn)) | |
6736 | { | |
6737 | rtx next; | |
6738 | ||
6739 | if (GET_RTX_CLASS (GET_CODE (insn)) != 'i') | |
6740 | continue; | |
6741 | next = NEXT_INSN (insn); | |
6742 | ||
6743 | if (INSN_DEP_COUNT (insn) == 0 | |
6744 | && (SCHED_GROUP_P (next) == 0 || GET_RTX_CLASS (GET_CODE (next)) != 'i')) | |
6745 | ready[n_ready++] = insn; | |
6746 | if (!(SCHED_GROUP_P (insn))) | |
6747 | target_n_insns++; | |
6748 | } | |
6749 | ||
6750 | /* Add to ready list all 'ready' insns in valid source blocks. | |
6751 | For speculative insns, check-live, exception-free, and | |
6752 | issue-delay. */ | |
6753 | for (bb_src = bb + 1; bb_src < current_nr_blocks; bb_src++) | |
6754 | if (IS_VALID (bb_src)) | |
6755 | { | |
6756 | rtx src_head; | |
6757 | rtx src_next_tail; | |
6758 | rtx tail, head; | |
6759 | ||
6760 | get_block_head_tail (bb_src, &head, &tail); | |
6761 | src_next_tail = NEXT_INSN (tail); | |
6762 | src_head = head; | |
6763 | ||
6764 | if (head == tail | |
6765 | && (GET_RTX_CLASS (GET_CODE (head)) != 'i')) | |
6766 | continue; | |
6767 | ||
6768 | for (insn = src_head; insn != src_next_tail; insn = NEXT_INSN (insn)) | |
6769 | { | |
6770 | if (GET_RTX_CLASS (GET_CODE (insn)) != 'i') | |
6771 | continue; | |
6772 | ||
6773 | if (!CANT_MOVE (insn) | |
6774 | && (!IS_SPECULATIVE_INSN (insn) | |
6775 | || (insn_issue_delay (insn) <= 3 | |
5835e573 | 6776 | && check_live (insn, bb_src) |
8c660648 JL |
6777 | && is_exception_free (insn, bb_src, target_bb)))) |
6778 | ||
6779 | { | |
6780 | rtx next; | |
6781 | ||
0d8b2ca1 RH |
6782 | /* Note that we havn't squirrled away the notes for |
6783 | blocks other than the current. So if this is a | |
6784 | speculative insn, NEXT might otherwise be a note. */ | |
6785 | next = next_nonnote_insn (insn); | |
8c660648 JL |
6786 | if (INSN_DEP_COUNT (insn) == 0 |
6787 | && (SCHED_GROUP_P (next) == 0 | |
6788 | || GET_RTX_CLASS (GET_CODE (next)) != 'i')) | |
6789 | ready[n_ready++] = insn; | |
6790 | } | |
6791 | } | |
6792 | } | |
6793 | ||
e4da5f6d MM |
6794 | #ifdef MD_SCHED_INIT |
6795 | MD_SCHED_INIT (dump, sched_verbose); | |
6796 | #endif | |
6797 | ||
63de6c74 | 6798 | /* No insns scheduled in this block yet. */ |
8c660648 JL |
6799 | last_scheduled_insn = 0; |
6800 | ||
8c660648 JL |
6801 | /* Q_SIZE is the total number of insns in the queue. */ |
6802 | q_ptr = 0; | |
6803 | q_size = 0; | |
4bdc8810 | 6804 | last_clock_var = 0; |
8c660648 JL |
6805 | bzero ((char *) insn_queue, sizeof (insn_queue)); |
6806 | ||
197043f5 RH |
6807 | /* Start just before the beginning of time. */ |
6808 | clock_var = -1; | |
6809 | ||
8c660648 JL |
6810 | /* We start inserting insns after PREV_HEAD. */ |
6811 | last = prev_head; | |
6812 | ||
6813 | /* Initialize INSN_QUEUE, LIST and NEW_NEEDS. */ | |
3b413743 | 6814 | new_needs = (NEXT_INSN (prev_head) == BLOCK_HEAD (b) |
8c660648 | 6815 | ? NEED_HEAD : NEED_NOTHING); |
3b413743 | 6816 | if (PREV_INSN (next_tail) == BLOCK_END (b)) |
8c660648 JL |
6817 | new_needs |= NEED_TAIL; |
6818 | ||
63de6c74 | 6819 | /* Loop until all the insns in BB are scheduled. */ |
8c660648 JL |
6820 | while (sched_target_n_insns < target_n_insns) |
6821 | { | |
6822 | int b1; | |
6823 | ||
8c660648 JL |
6824 | clock_var++; |
6825 | ||
6826 | /* Add to the ready list all pending insns that can be issued now. | |
6827 | If there are no ready insns, increment clock until one | |
6828 | is ready and add all pending insns at that point to the ready | |
6829 | list. */ | |
6830 | n_ready = queue_to_ready (ready, n_ready); | |
6831 | ||
6832 | if (n_ready == 0) | |
6833 | abort (); | |
6834 | ||
6835 | if (sched_verbose >= 2) | |
6836 | { | |
6837 | fprintf (dump, ";;\t\tReady list after queue_to_ready: "); | |
6838 | debug_ready_list (ready, n_ready); | |
6839 | } | |
6840 | ||
197043f5 | 6841 | /* Sort the ready list based on priority. */ |
8c660648 | 6842 | SCHED_SORT (ready, n_ready); |
197043f5 RH |
6843 | |
6844 | /* Allow the target to reorder the list, typically for | |
6845 | better instruction bundling. */ | |
e4da5f6d | 6846 | #ifdef MD_SCHED_REORDER |
197043f5 RH |
6847 | MD_SCHED_REORDER (dump, sched_verbose, ready, n_ready, clock_var, |
6848 | can_issue_more); | |
6849 | #else | |
6850 | can_issue_more = issue_rate; | |
e4da5f6d | 6851 | #endif |
8c660648 JL |
6852 | |
6853 | if (sched_verbose) | |
6854 | { | |
47312d84 | 6855 | fprintf (dump, "\n;;\tReady list (t =%3d): ", clock_var); |
8c660648 JL |
6856 | debug_ready_list (ready, n_ready); |
6857 | } | |
6858 | ||
197043f5 RH |
6859 | /* Issue insns from ready list. */ |
6860 | while (n_ready != 0 && can_issue_more) | |
8c660648 | 6861 | { |
197043f5 RH |
6862 | /* Select and remove the insn from the ready list. */ |
6863 | rtx insn = ready[--n_ready]; | |
8c660648 JL |
6864 | int cost = actual_hazard (insn_unit (insn), insn, clock_var, 0); |
6865 | ||
197043f5 | 6866 | if (cost >= 1) |
8c660648 JL |
6867 | { |
6868 | queue_insn (insn, cost); | |
197043f5 | 6869 | continue; |
8c660648 | 6870 | } |
4f64eaca | 6871 | |
197043f5 RH |
6872 | /* An interblock motion? */ |
6873 | if (INSN_BB (insn) != target_bb) | |
6874 | { | |
6875 | rtx temp; | |
8c660648 | 6876 | |
197043f5 RH |
6877 | if (IS_SPECULATIVE_INSN (insn)) |
6878 | { | |
6879 | if (!check_live (insn, INSN_BB (insn))) | |
6880 | continue; | |
6881 | update_live (insn, INSN_BB (insn)); | |
8c660648 | 6882 | |
197043f5 RH |
6883 | /* For speculative load, mark insns fed by it. */ |
6884 | if (IS_LOAD_INSN (insn) || FED_BY_SPEC_LOAD (insn)) | |
6885 | set_spec_fed (insn); | |
8c660648 | 6886 | |
197043f5 RH |
6887 | nr_spec++; |
6888 | } | |
6889 | nr_inter++; | |
8c660648 | 6890 | |
197043f5 RH |
6891 | temp = insn; |
6892 | while (SCHED_GROUP_P (temp)) | |
6893 | temp = PREV_INSN (temp); | |
4f64eaca | 6894 | |
197043f5 RH |
6895 | /* Update source block boundaries. */ |
6896 | b1 = INSN_BLOCK (temp); | |
6897 | if (temp == BLOCK_HEAD (b1) | |
6898 | && insn == BLOCK_END (b1)) | |
6899 | { | |
6900 | /* We moved all the insns in the basic block. | |
6901 | Emit a note after the last insn and update the | |
6902 | begin/end boundaries to point to the note. */ | |
6903 | emit_note_after (NOTE_INSN_DELETED, insn); | |
6904 | BLOCK_END (b1) = NEXT_INSN (insn); | |
6905 | BLOCK_HEAD (b1) = NEXT_INSN (insn); | |
8c660648 | 6906 | } |
197043f5 | 6907 | else if (insn == BLOCK_END (b1)) |
8c660648 | 6908 | { |
197043f5 RH |
6909 | /* We took insns from the end of the basic block, |
6910 | so update the end of block boundary so that it | |
6911 | points to the first insn we did not move. */ | |
6912 | BLOCK_END (b1) = PREV_INSN (temp); | |
8c660648 | 6913 | } |
197043f5 RH |
6914 | else if (temp == BLOCK_HEAD (b1)) |
6915 | { | |
6916 | /* We took insns from the start of the basic block, | |
6917 | so update the start of block boundary so that | |
6918 | it points to the first insn we did not move. */ | |
6919 | BLOCK_HEAD (b1) = NEXT_INSN (insn); | |
6920 | } | |
6921 | } | |
6922 | else | |
6923 | { | |
6924 | /* In block motion. */ | |
6925 | sched_target_n_insns++; | |
6926 | } | |
8c660648 | 6927 | |
197043f5 RH |
6928 | last_scheduled_insn = insn; |
6929 | last = move_insn (insn, last); | |
6930 | sched_n_insns++; | |
8c660648 | 6931 | |
e4da5f6d | 6932 | #ifdef MD_SCHED_VARIABLE_ISSUE |
197043f5 RH |
6933 | MD_SCHED_VARIABLE_ISSUE (dump, sched_verbose, insn, |
6934 | can_issue_more); | |
e4da5f6d | 6935 | #else |
197043f5 | 6936 | can_issue_more--; |
e4da5f6d | 6937 | #endif |
8c660648 | 6938 | |
197043f5 | 6939 | n_ready = schedule_insn (insn, ready, n_ready, clock_var); |
8c660648 | 6940 | |
197043f5 RH |
6941 | /* Close this block after scheduling its jump. */ |
6942 | if (GET_CODE (last_scheduled_insn) == JUMP_INSN) | |
6943 | break; | |
8c660648 JL |
6944 | } |
6945 | ||
197043f5 | 6946 | /* Debug info. */ |
8c660648 | 6947 | if (sched_verbose) |
197043f5 | 6948 | visualize_scheduled_insns (b, clock_var); |
8c660648 JL |
6949 | } |
6950 | ||
63de6c74 | 6951 | /* Debug info. */ |
8c660648 JL |
6952 | if (sched_verbose) |
6953 | { | |
6954 | fprintf (dump, ";;\tReady list (final): "); | |
6955 | debug_ready_list (ready, n_ready); | |
6956 | print_block_visualization (b, ""); | |
6957 | } | |
6958 | ||
6959 | /* Sanity check -- queue must be empty now. Meaningless if region has | |
cc132865 | 6960 | multiple bbs. */ |
8c660648 | 6961 | if (current_nr_blocks > 1) |
cc132865 JL |
6962 | if (!flag_schedule_interblock && q_size != 0) |
6963 | abort (); | |
8c660648 | 6964 | |
63de6c74 | 6965 | /* Update head/tail boundaries. */ |
8c660648 JL |
6966 | head = NEXT_INSN (prev_head); |
6967 | tail = last; | |
6968 | ||
8c660648 JL |
6969 | /* Restore-other-notes: NOTE_LIST is the end of a chain of notes |
6970 | previously found among the insns. Insert them at the beginning | |
6971 | of the insns. */ | |
6972 | if (note_list != 0) | |
6973 | { | |
6974 | rtx note_head = note_list; | |
6975 | ||
6976 | while (PREV_INSN (note_head)) | |
6977 | { | |
6978 | note_head = PREV_INSN (note_head); | |
6979 | } | |
6980 | ||
6981 | PREV_INSN (note_head) = PREV_INSN (head); | |
6982 | NEXT_INSN (PREV_INSN (head)) = note_head; | |
6983 | PREV_INSN (head) = note_list; | |
6984 | NEXT_INSN (note_list) = head; | |
6985 | head = note_head; | |
6986 | } | |
6987 | ||
63de6c74 | 6988 | /* Update target block boundaries. */ |
8c660648 | 6989 | if (new_needs & NEED_HEAD) |
3b413743 | 6990 | BLOCK_HEAD (b) = head; |
8c660648 JL |
6991 | |
6992 | if (new_needs & NEED_TAIL) | |
3b413743 | 6993 | BLOCK_END (b) = tail; |
8c660648 | 6994 | |
63de6c74 | 6995 | /* Debugging. */ |
8c660648 JL |
6996 | if (sched_verbose) |
6997 | { | |
6998 | fprintf (dump, ";; total time = %d\n;; new basic block head = %d\n", | |
3b413743 | 6999 | clock_var, INSN_UID (BLOCK_HEAD (b))); |
8c660648 | 7000 | fprintf (dump, ";; new basic block end = %d\n\n", |
3b413743 | 7001 | INSN_UID (BLOCK_END (b))); |
8c660648 JL |
7002 | } |
7003 | ||
7004 | return (sched_n_insns); | |
7005 | } /* schedule_block () */ | |
7006 | \f | |
7007 | ||
63de6c74 | 7008 | /* Print the bit-set of registers, S, callable from debugger. */ |
8c660648 JL |
7009 | |
7010 | extern void | |
7011 | debug_reg_vector (s) | |
7012 | regset s; | |
7013 | { | |
7014 | int regno; | |
7015 | ||
7016 | EXECUTE_IF_SET_IN_REG_SET (s, 0, regno, | |
7017 | { | |
7018 | fprintf (dump, " %d", regno); | |
7019 | }); | |
7020 | ||
7021 | fprintf (dump, "\n"); | |
7022 | } | |
7023 | ||
7024 | /* Use the backward dependences from LOG_LINKS to build | |
7025 | forward dependences in INSN_DEPEND. */ | |
7026 | ||
7027 | static void | |
7028 | compute_block_forward_dependences (bb) | |
7029 | int bb; | |
7030 | { | |
7031 | rtx insn, link; | |
7032 | rtx tail, head; | |
7033 | rtx next_tail; | |
7034 | enum reg_note dep_type; | |
7035 | ||
7036 | get_block_head_tail (bb, &head, &tail); | |
7037 | next_tail = NEXT_INSN (tail); | |
7038 | for (insn = head; insn != next_tail; insn = NEXT_INSN (insn)) | |
7039 | { | |
7040 | if (GET_RTX_CLASS (GET_CODE (insn)) != 'i') | |
7041 | continue; | |
7042 | ||
7043 | insn = group_leader (insn); | |
7044 | ||
7045 | for (link = LOG_LINKS (insn); link; link = XEXP (link, 1)) | |
7046 | { | |
7047 | rtx x = group_leader (XEXP (link, 0)); | |
7048 | rtx new_link; | |
7049 | ||
7050 | if (x != XEXP (link, 0)) | |
7051 | continue; | |
7052 | ||
63de6c74 | 7053 | /* Ignore dependences upon deleted insn. */ |
8c660648 JL |
7054 | if (GET_CODE (x) == NOTE || INSN_DELETED_P (x)) |
7055 | continue; | |
7056 | if (find_insn_list (insn, INSN_DEPEND (x))) | |
7057 | continue; | |
7058 | ||
ebb7b10b | 7059 | new_link = alloc_INSN_LIST (insn, INSN_DEPEND (x)); |
8c660648 JL |
7060 | |
7061 | dep_type = REG_NOTE_KIND (link); | |
7062 | PUT_REG_NOTE_KIND (new_link, dep_type); | |
7063 | ||
8c660648 JL |
7064 | INSN_DEPEND (x) = new_link; |
7065 | INSN_DEP_COUNT (insn) += 1; | |
7066 | } | |
7067 | } | |
7068 | } | |
7069 | ||
7070 | /* Initialize variables for region data dependence analysis. | |
63de6c74 | 7071 | n_bbs is the number of region blocks. */ |
8c660648 | 7072 | |
6d3352d9 | 7073 | __inline static void |
8c660648 JL |
7074 | init_rgn_data_dependences (n_bbs) |
7075 | int n_bbs; | |
7076 | { | |
7077 | int bb; | |
7078 | ||
63de6c74 | 7079 | /* Variables for which one copy exists for each block. */ |
8c660648 JL |
7080 | bzero ((char *) bb_pending_read_insns, n_bbs * sizeof (rtx)); |
7081 | bzero ((char *) bb_pending_read_mems, n_bbs * sizeof (rtx)); | |
7082 | bzero ((char *) bb_pending_write_insns, n_bbs * sizeof (rtx)); | |
7083 | bzero ((char *) bb_pending_write_mems, n_bbs * sizeof (rtx)); | |
7084 | bzero ((char *) bb_pending_lists_length, n_bbs * sizeof (rtx)); | |
7085 | bzero ((char *) bb_last_pending_memory_flush, n_bbs * sizeof (rtx)); | |
7086 | bzero ((char *) bb_last_function_call, n_bbs * sizeof (rtx)); | |
7087 | bzero ((char *) bb_sched_before_next_call, n_bbs * sizeof (rtx)); | |
7088 | ||
7089 | /* Create an insn here so that we can hang dependencies off of it later. */ | |
7090 | for (bb = 0; bb < n_bbs; bb++) | |
7091 | { | |
7092 | bb_sched_before_next_call[bb] = | |
38a448ca RH |
7093 | gen_rtx_INSN (VOIDmode, 0, NULL_RTX, NULL_RTX, |
7094 | NULL_RTX, 0, NULL_RTX, NULL_RTX); | |
8c660648 JL |
7095 | LOG_LINKS (bb_sched_before_next_call[bb]) = 0; |
7096 | } | |
7097 | } | |
7098 | ||
63de6c74 MH |
7099 | /* Add dependences so that branches are scheduled to run last in their |
7100 | block. */ | |
8c660648 JL |
7101 | |
7102 | static void | |
7103 | add_branch_dependences (head, tail) | |
7104 | rtx head, tail; | |
7105 | { | |
7106 | ||
7107 | rtx insn, last; | |
7108 | ||
7109 | /* For all branches, calls, uses, and cc0 setters, force them to remain | |
7110 | in order at the end of the block by adding dependencies and giving | |
7111 | the last a high priority. There may be notes present, and prev_head | |
7112 | may also be a note. | |
7113 | ||
7114 | Branches must obviously remain at the end. Calls should remain at the | |
7115 | end since moving them results in worse register allocation. Uses remain | |
7116 | at the end to ensure proper register allocation. cc0 setters remaim | |
7117 | at the end because they can't be moved away from their cc0 user. */ | |
7118 | insn = tail; | |
7119 | last = 0; | |
7120 | while (GET_CODE (insn) == CALL_INSN || GET_CODE (insn) == JUMP_INSN | |
7121 | || (GET_CODE (insn) == INSN | |
7122 | && (GET_CODE (PATTERN (insn)) == USE | |
7123 | #ifdef HAVE_cc0 | |
7124 | || sets_cc0_p (PATTERN (insn)) | |
7125 | #endif | |
7126 | )) | |
7127 | || GET_CODE (insn) == NOTE) | |
7128 | { | |
7129 | if (GET_CODE (insn) != NOTE) | |
7130 | { | |
7131 | if (last != 0 | |
7132 | && !find_insn_list (insn, LOG_LINKS (last))) | |
7133 | { | |
7134 | add_dependence (last, insn, REG_DEP_ANTI); | |
7135 | INSN_REF_COUNT (insn)++; | |
7136 | } | |
7137 | ||
7138 | CANT_MOVE (insn) = 1; | |
7139 | ||
7140 | last = insn; | |
326ee7a3 JL |
7141 | /* Skip over insns that are part of a group. |
7142 | Make each insn explicitly depend on the previous insn. | |
7143 | This ensures that only the group header will ever enter | |
7144 | the ready queue (and, when scheduled, will automatically | |
7145 | schedule the SCHED_GROUP_P block). */ | |
8c660648 | 7146 | while (SCHED_GROUP_P (insn)) |
326ee7a3 JL |
7147 | { |
7148 | rtx temp = prev_nonnote_insn (insn); | |
7149 | add_dependence (insn, temp, REG_DEP_ANTI); | |
7150 | insn = temp; | |
7151 | } | |
8c660648 JL |
7152 | } |
7153 | ||
7154 | /* Don't overrun the bounds of the basic block. */ | |
7155 | if (insn == head) | |
7156 | break; | |
7157 | ||
7158 | insn = PREV_INSN (insn); | |
7159 | } | |
7160 | ||
63de6c74 | 7161 | /* Make sure these insns are scheduled last in their block. */ |
8c660648 JL |
7162 | insn = last; |
7163 | if (insn != 0) | |
7164 | while (insn != head) | |
7165 | { | |
7166 | insn = prev_nonnote_insn (insn); | |
7167 | ||
7168 | if (INSN_REF_COUNT (insn) != 0) | |
7169 | continue; | |
7170 | ||
87373fba | 7171 | add_dependence (last, insn, REG_DEP_ANTI); |
8c660648 JL |
7172 | INSN_REF_COUNT (insn) = 1; |
7173 | ||
7174 | /* Skip over insns that are part of a group. */ | |
7175 | while (SCHED_GROUP_P (insn)) | |
7176 | insn = prev_nonnote_insn (insn); | |
7177 | } | |
7178 | } | |
7179 | ||
63de6c74 | 7180 | /* Compute backward dependences inside bb. In a multiple blocks region: |
8c660648 JL |
7181 | (1) a bb is analyzed after its predecessors, and (2) the lists in |
7182 | effect at the end of bb (after analyzing for bb) are inherited by | |
7183 | bb's successrs. | |
7184 | ||
7185 | Specifically for reg-reg data dependences, the block insns are | |
7186 | scanned by sched_analyze () top-to-bottom. Two lists are | |
63de6c74 | 7187 | maintained by sched_analyze (): reg_last_sets[] for register DEFs, |
8c660648 JL |
7188 | and reg_last_uses[] for register USEs. |
7189 | ||
7190 | When analysis is completed for bb, we update for its successors: | |
7191 | ; - DEFS[succ] = Union (DEFS [succ], DEFS [bb]) | |
7192 | ; - USES[succ] = Union (USES [succ], DEFS [bb]) | |
7193 | ||
7194 | The mechanism for computing mem-mem data dependence is very | |
7195 | similar, and the result is interblock dependences in the region. */ | |
7196 | ||
7197 | static void | |
7198 | compute_block_backward_dependences (bb) | |
7199 | int bb; | |
7200 | { | |
7201 | int b; | |
7202 | rtx x; | |
7203 | rtx head, tail; | |
7204 | int max_reg = max_reg_num (); | |
7205 | ||
7206 | b = BB_TO_BLOCK (bb); | |
7207 | ||
7208 | if (current_nr_blocks == 1) | |
7209 | { | |
7210 | reg_last_uses = (rtx *) alloca (max_reg * sizeof (rtx)); | |
7211 | reg_last_sets = (rtx *) alloca (max_reg * sizeof (rtx)); | |
28c95eff | 7212 | reg_last_clobbers = (rtx *) alloca (max_reg * sizeof (rtx)); |
8c660648 JL |
7213 | |
7214 | bzero ((char *) reg_last_uses, max_reg * sizeof (rtx)); | |
7215 | bzero ((char *) reg_last_sets, max_reg * sizeof (rtx)); | |
28c95eff | 7216 | bzero ((char *) reg_last_clobbers, max_reg * sizeof (rtx)); |
8c660648 JL |
7217 | |
7218 | pending_read_insns = 0; | |
7219 | pending_read_mems = 0; | |
7220 | pending_write_insns = 0; | |
7221 | pending_write_mems = 0; | |
7222 | pending_lists_length = 0; | |
7223 | last_function_call = 0; | |
7224 | last_pending_memory_flush = 0; | |
7225 | sched_before_next_call | |
38a448ca RH |
7226 | = gen_rtx_INSN (VOIDmode, 0, NULL_RTX, NULL_RTX, |
7227 | NULL_RTX, 0, NULL_RTX, NULL_RTX); | |
8c660648 JL |
7228 | LOG_LINKS (sched_before_next_call) = 0; |
7229 | } | |
7230 | else | |
7231 | { | |
7232 | reg_last_uses = bb_reg_last_uses[bb]; | |
7233 | reg_last_sets = bb_reg_last_sets[bb]; | |
28c95eff | 7234 | reg_last_clobbers = bb_reg_last_clobbers[bb]; |
8c660648 JL |
7235 | |
7236 | pending_read_insns = bb_pending_read_insns[bb]; | |
7237 | pending_read_mems = bb_pending_read_mems[bb]; | |
7238 | pending_write_insns = bb_pending_write_insns[bb]; | |
7239 | pending_write_mems = bb_pending_write_mems[bb]; | |
7240 | pending_lists_length = bb_pending_lists_length[bb]; | |
7241 | last_function_call = bb_last_function_call[bb]; | |
7242 | last_pending_memory_flush = bb_last_pending_memory_flush[bb]; | |
7243 | ||
7244 | sched_before_next_call = bb_sched_before_next_call[bb]; | |
7245 | } | |
7246 | ||
63de6c74 | 7247 | /* Do the analysis for this block. */ |
8c660648 JL |
7248 | get_block_head_tail (bb, &head, &tail); |
7249 | sched_analyze (head, tail); | |
7250 | add_branch_dependences (head, tail); | |
7251 | ||
7252 | if (current_nr_blocks > 1) | |
7253 | { | |
7254 | int e, first_edge; | |
7255 | int b_succ, bb_succ; | |
7256 | int reg; | |
7257 | rtx link_insn, link_mem; | |
7258 | rtx u; | |
7259 | ||
63de6c74 MH |
7260 | /* These lists should point to the right place, for correct |
7261 | freeing later. */ | |
8c660648 JL |
7262 | bb_pending_read_insns[bb] = pending_read_insns; |
7263 | bb_pending_read_mems[bb] = pending_read_mems; | |
7264 | bb_pending_write_insns[bb] = pending_write_insns; | |
7265 | bb_pending_write_mems[bb] = pending_write_mems; | |
7266 | ||
63de6c74 | 7267 | /* bb's structures are inherited by it's successors. */ |
8c660648 JL |
7268 | first_edge = e = OUT_EDGES (b); |
7269 | if (e > 0) | |
7270 | do | |
7271 | { | |
7272 | b_succ = TO_BLOCK (e); | |
7273 | bb_succ = BLOCK_TO_BB (b_succ); | |
7274 | ||
63de6c74 | 7275 | /* Only bbs "below" bb, in the same region, are interesting. */ |
8c660648 JL |
7276 | if (CONTAINING_RGN (b) != CONTAINING_RGN (b_succ) |
7277 | || bb_succ <= bb) | |
7278 | { | |
7279 | e = NEXT_OUT (e); | |
7280 | continue; | |
7281 | } | |
7282 | ||
7283 | for (reg = 0; reg < max_reg; reg++) | |
7284 | { | |
7285 | ||
63de6c74 | 7286 | /* reg-last-uses lists are inherited by bb_succ. */ |
8c660648 JL |
7287 | for (u = reg_last_uses[reg]; u; u = XEXP (u, 1)) |
7288 | { | |
63de6c74 MH |
7289 | if (find_insn_list (XEXP (u, 0), |
7290 | (bb_reg_last_uses[bb_succ])[reg])) | |
8c660648 JL |
7291 | continue; |
7292 | ||
7293 | (bb_reg_last_uses[bb_succ])[reg] | |
ebb7b10b RH |
7294 | = alloc_INSN_LIST (XEXP (u, 0), |
7295 | (bb_reg_last_uses[bb_succ])[reg]); | |
8c660648 JL |
7296 | } |
7297 | ||
63de6c74 | 7298 | /* reg-last-defs lists are inherited by bb_succ. */ |
8c660648 JL |
7299 | for (u = reg_last_sets[reg]; u; u = XEXP (u, 1)) |
7300 | { | |
63de6c74 MH |
7301 | if (find_insn_list (XEXP (u, 0), |
7302 | (bb_reg_last_sets[bb_succ])[reg])) | |
8c660648 JL |
7303 | continue; |
7304 | ||
7305 | (bb_reg_last_sets[bb_succ])[reg] | |
ebb7b10b RH |
7306 | = alloc_INSN_LIST (XEXP (u, 0), |
7307 | (bb_reg_last_sets[bb_succ])[reg]); | |
8c660648 | 7308 | } |
28c95eff RH |
7309 | |
7310 | for (u = reg_last_clobbers[reg]; u; u = XEXP (u, 1)) | |
7311 | { | |
63de6c74 MH |
7312 | if (find_insn_list (XEXP (u, 0), |
7313 | (bb_reg_last_clobbers[bb_succ])[reg])) | |
28c95eff RH |
7314 | continue; |
7315 | ||
7316 | (bb_reg_last_clobbers[bb_succ])[reg] | |
7317 | = alloc_INSN_LIST (XEXP (u, 0), | |
7318 | (bb_reg_last_clobbers[bb_succ])[reg]); | |
7319 | } | |
8c660648 JL |
7320 | } |
7321 | ||
63de6c74 | 7322 | /* Mem read/write lists are inherited by bb_succ. */ |
8c660648 JL |
7323 | link_insn = pending_read_insns; |
7324 | link_mem = pending_read_mems; | |
7325 | while (link_insn) | |
7326 | { | |
63de6c74 MH |
7327 | if (!(find_insn_mem_list (XEXP (link_insn, 0), |
7328 | XEXP (link_mem, 0), | |
8c660648 JL |
7329 | bb_pending_read_insns[bb_succ], |
7330 | bb_pending_read_mems[bb_succ]))) | |
7331 | add_insn_mem_dependence (&bb_pending_read_insns[bb_succ], | |
7332 | &bb_pending_read_mems[bb_succ], | |
7333 | XEXP (link_insn, 0), XEXP (link_mem, 0)); | |
7334 | link_insn = XEXP (link_insn, 1); | |
7335 | link_mem = XEXP (link_mem, 1); | |
7336 | } | |
7337 | ||
7338 | link_insn = pending_write_insns; | |
7339 | link_mem = pending_write_mems; | |
7340 | while (link_insn) | |
7341 | { | |
63de6c74 MH |
7342 | if (!(find_insn_mem_list (XEXP (link_insn, 0), |
7343 | XEXP (link_mem, 0), | |
8c660648 JL |
7344 | bb_pending_write_insns[bb_succ], |
7345 | bb_pending_write_mems[bb_succ]))) | |
7346 | add_insn_mem_dependence (&bb_pending_write_insns[bb_succ], | |
7347 | &bb_pending_write_mems[bb_succ], | |
7348 | XEXP (link_insn, 0), XEXP (link_mem, 0)); | |
7349 | ||
7350 | link_insn = XEXP (link_insn, 1); | |
7351 | link_mem = XEXP (link_mem, 1); | |
7352 | } | |
7353 | ||
63de6c74 | 7354 | /* last_function_call is inherited by bb_succ. */ |
8c660648 JL |
7355 | for (u = last_function_call; u; u = XEXP (u, 1)) |
7356 | { | |
63de6c74 MH |
7357 | if (find_insn_list (XEXP (u, 0), |
7358 | bb_last_function_call[bb_succ])) | |
8c660648 JL |
7359 | continue; |
7360 | ||
7361 | bb_last_function_call[bb_succ] | |
ebb7b10b RH |
7362 | = alloc_INSN_LIST (XEXP (u, 0), |
7363 | bb_last_function_call[bb_succ]); | |
8c660648 JL |
7364 | } |
7365 | ||
63de6c74 | 7366 | /* last_pending_memory_flush is inherited by bb_succ. */ |
8c660648 JL |
7367 | for (u = last_pending_memory_flush; u; u = XEXP (u, 1)) |
7368 | { | |
63de6c74 MH |
7369 | if (find_insn_list (XEXP (u, 0), |
7370 | bb_last_pending_memory_flush[bb_succ])) | |
8c660648 JL |
7371 | continue; |
7372 | ||
7373 | bb_last_pending_memory_flush[bb_succ] | |
ebb7b10b RH |
7374 | = alloc_INSN_LIST (XEXP (u, 0), |
7375 | bb_last_pending_memory_flush[bb_succ]); | |
8c660648 JL |
7376 | } |
7377 | ||
63de6c74 | 7378 | /* sched_before_next_call is inherited by bb_succ. */ |
8c660648 JL |
7379 | x = LOG_LINKS (sched_before_next_call); |
7380 | for (; x; x = XEXP (x, 1)) | |
7381 | add_dependence (bb_sched_before_next_call[bb_succ], | |
7382 | XEXP (x, 0), REG_DEP_ANTI); | |
7383 | ||
7384 | e = NEXT_OUT (e); | |
7385 | } | |
7386 | while (e != first_edge); | |
7387 | } | |
ebb7b10b | 7388 | |
63de6c74 | 7389 | /* Free up the INSN_LISTs. |
7eea6443 JL |
7390 | |
7391 | Note this loop is executed max_reg * nr_regions times. It's first | |
5a4f6418 AM |
7392 | implementation accounted for over 90% of the calls to free_INSN_LIST_list. |
7393 | The list was empty for the vast majority of those calls. On the PA, not | |
7394 | calling free_INSN_LIST_list in those cases improves -O2 compile times by | |
7eea6443 | 7395 | 3-5% on average. */ |
ebb7b10b RH |
7396 | for (b = 0; b < max_reg; ++b) |
7397 | { | |
28c95eff | 7398 | if (reg_last_clobbers[b]) |
5a4f6418 | 7399 | free_INSN_LIST_list (®_last_clobbers[b]); |
7eea6443 | 7400 | if (reg_last_sets[b]) |
5a4f6418 | 7401 | free_INSN_LIST_list (®_last_sets[b]); |
7eea6443 | 7402 | if (reg_last_uses[b]) |
5a4f6418 | 7403 | free_INSN_LIST_list (®_last_uses[b]); |
ebb7b10b RH |
7404 | } |
7405 | ||
7406 | /* Assert that we won't need bb_reg_last_* for this block anymore. */ | |
7407 | if (current_nr_blocks > 1) | |
7408 | { | |
7409 | bb_reg_last_uses[bb] = (rtx *) NULL_RTX; | |
7410 | bb_reg_last_sets[bb] = (rtx *) NULL_RTX; | |
28c95eff | 7411 | bb_reg_last_clobbers[bb] = (rtx *) NULL_RTX; |
ebb7b10b | 7412 | } |
8c660648 JL |
7413 | } |
7414 | ||
63de6c74 | 7415 | /* Print dependences for debugging, callable from debugger. */ |
8c660648 JL |
7416 | |
7417 | void | |
7418 | debug_dependencies () | |
7419 | { | |
7420 | int bb; | |
7421 | ||
7422 | fprintf (dump, ";; --------------- forward dependences: ------------ \n"); | |
7423 | for (bb = 0; bb < current_nr_blocks; bb++) | |
7424 | { | |
7425 | if (1) | |
7426 | { | |
7427 | rtx head, tail; | |
7428 | rtx next_tail; | |
7429 | rtx insn; | |
7430 | ||
7431 | get_block_head_tail (bb, &head, &tail); | |
7432 | next_tail = NEXT_INSN (tail); | |
7433 | fprintf (dump, "\n;; --- Region Dependences --- b %d bb %d \n", | |
7434 | BB_TO_BLOCK (bb), bb); | |
7435 | ||
7436 | fprintf (dump, ";; %7s%6s%6s%6s%6s%6s%11s%6s\n", | |
7437 | "insn", "code", "bb", "dep", "prio", "cost", "blockage", "units"); | |
7438 | fprintf (dump, ";; %7s%6s%6s%6s%6s%6s%11s%6s\n", | |
7439 | "----", "----", "--", "---", "----", "----", "--------", "-----"); | |
7440 | for (insn = head; insn != next_tail; insn = NEXT_INSN (insn)) | |
7441 | { | |
7442 | rtx link; | |
7443 | int unit, range; | |
7444 | ||
7445 | if (GET_RTX_CLASS (GET_CODE (insn)) != 'i') | |
7446 | { | |
7447 | int n; | |
7448 | fprintf (dump, ";; %6d ", INSN_UID (insn)); | |
7449 | if (GET_CODE (insn) == NOTE) | |
ebc25a17 MM |
7450 | { |
7451 | n = NOTE_LINE_NUMBER (insn); | |
7452 | if (n < 0) | |
7453 | fprintf (dump, "%s\n", GET_NOTE_INSN_NAME (n)); | |
7454 | else | |
7455 | fprintf (dump, "line %d, file %s\n", n, | |
7456 | NOTE_SOURCE_FILE (insn)); | |
7457 | } | |
7458 | else | |
4f64eaca | 7459 | fprintf (dump, " {%s}\n", GET_RTX_NAME (GET_CODE (insn))); |
8c660648 JL |
7460 | continue; |
7461 | } | |
7462 | ||
7463 | unit = insn_unit (insn); | |
7464 | range = (unit < 0 | |
7465 | || function_units[unit].blockage_range_function == 0) ? 0 : | |
7466 | function_units[unit].blockage_range_function (insn); | |
7467 | fprintf (dump, | |
7468 | ";; %s%5d%6d%6d%6d%6d%6d %3d -%3d ", | |
7469 | (SCHED_GROUP_P (insn) ? "+" : " "), | |
7470 | INSN_UID (insn), | |
7471 | INSN_CODE (insn), | |
7472 | INSN_BB (insn), | |
7473 | INSN_DEP_COUNT (insn), | |
7474 | INSN_PRIORITY (insn), | |
7475 | insn_cost (insn, 0, 0), | |
7476 | (int) MIN_BLOCKAGE_COST (range), | |
7477 | (int) MAX_BLOCKAGE_COST (range)); | |
7478 | insn_print_units (insn); | |
7479 | fprintf (dump, "\t: "); | |
7480 | for (link = INSN_DEPEND (insn); link; link = XEXP (link, 1)) | |
7481 | fprintf (dump, "%d ", INSN_UID (XEXP (link, 0))); | |
7482 | fprintf (dump, "\n"); | |
7483 | } | |
7484 | } | |
7485 | } | |
7486 | fprintf (dump, "\n"); | |
7487 | } | |
7488 | ||
63de6c74 | 7489 | /* Set_priorities: compute priority of each insn in the block. */ |
8c660648 JL |
7490 | |
7491 | static int | |
7492 | set_priorities (bb) | |
7493 | int bb; | |
7494 | { | |
7495 | rtx insn; | |
7496 | int n_insn; | |
7497 | ||
7498 | rtx tail; | |
7499 | rtx prev_head; | |
7500 | rtx head; | |
7501 | ||
7502 | get_block_head_tail (bb, &head, &tail); | |
7503 | prev_head = PREV_INSN (head); | |
7504 | ||
7505 | if (head == tail | |
7506 | && (GET_RTX_CLASS (GET_CODE (head)) != 'i')) | |
7507 | return 0; | |
7508 | ||
7509 | n_insn = 0; | |
7510 | for (insn = tail; insn != prev_head; insn = PREV_INSN (insn)) | |
7511 | { | |
7512 | ||
7513 | if (GET_CODE (insn) == NOTE) | |
7514 | continue; | |
7515 | ||
7516 | if (!(SCHED_GROUP_P (insn))) | |
7517 | n_insn++; | |
7518 | (void) priority (insn); | |
7519 | } | |
7520 | ||
7521 | return n_insn; | |
7522 | } | |
7523 | ||
7524 | /* Make each element of VECTOR point at an rtx-vector, | |
7525 | taking the space for all those rtx-vectors from SPACE. | |
7526 | SPACE is of type (rtx *), but it is really as long as NELTS rtx-vectors. | |
7527 | BYTES_PER_ELT is the number of bytes in one rtx-vector. | |
63de6c74 | 7528 | (this is the same as init_regset_vector () in flow.c) */ |
8c660648 JL |
7529 | |
7530 | static void | |
7531 | init_rtx_vector (vector, space, nelts, bytes_per_elt) | |
7532 | rtx **vector; | |
7533 | rtx *space; | |
7534 | int nelts; | |
7535 | int bytes_per_elt; | |
7536 | { | |
7537 | register int i; | |
7538 | register rtx *p = space; | |
7539 | ||
7540 | for (i = 0; i < nelts; i++) | |
7541 | { | |
7542 | vector[i] = p; | |
7543 | p += bytes_per_elt / sizeof (*p); | |
7544 | } | |
7545 | } | |
7546 | ||
7547 | /* Schedule a region. A region is either an inner loop, a loop-free | |
7548 | subroutine, or a single basic block. Each bb in the region is | |
7549 | scheduled after its flow predecessors. */ | |
7550 | ||
7551 | static void | |
7552 | schedule_region (rgn) | |
7553 | int rgn; | |
7554 | { | |
7555 | int bb; | |
7556 | int rgn_n_insns = 0; | |
7557 | int sched_rgn_n_insns = 0; | |
7558 | ||
63de6c74 | 7559 | /* Set variables for the current region. */ |
8c660648 JL |
7560 | current_nr_blocks = RGN_NR_BLOCKS (rgn); |
7561 | current_blocks = RGN_BLOCKS (rgn); | |
7562 | ||
7563 | reg_pending_sets = ALLOCA_REG_SET (); | |
28c95eff | 7564 | reg_pending_clobbers = ALLOCA_REG_SET (); |
8c660648 JL |
7565 | reg_pending_sets_all = 0; |
7566 | ||
63de6c74 | 7567 | /* Initializations for region data dependence analyisis. */ |
8c660648 JL |
7568 | if (current_nr_blocks > 1) |
7569 | { | |
7570 | rtx *space; | |
7571 | int maxreg = max_reg_num (); | |
7572 | ||
7573 | bb_reg_last_uses = (rtx **) alloca (current_nr_blocks * sizeof (rtx *)); | |
7574 | space = (rtx *) alloca (current_nr_blocks * maxreg * sizeof (rtx)); | |
7575 | bzero ((char *) space, current_nr_blocks * maxreg * sizeof (rtx)); | |
28c95eff RH |
7576 | init_rtx_vector (bb_reg_last_uses, space, current_nr_blocks, |
7577 | maxreg * sizeof (rtx *)); | |
8c660648 JL |
7578 | |
7579 | bb_reg_last_sets = (rtx **) alloca (current_nr_blocks * sizeof (rtx *)); | |
7580 | space = (rtx *) alloca (current_nr_blocks * maxreg * sizeof (rtx)); | |
7581 | bzero ((char *) space, current_nr_blocks * maxreg * sizeof (rtx)); | |
28c95eff RH |
7582 | init_rtx_vector (bb_reg_last_sets, space, current_nr_blocks, |
7583 | maxreg * sizeof (rtx *)); | |
7584 | ||
7585 | bb_reg_last_clobbers = | |
7586 | (rtx **) alloca (current_nr_blocks * sizeof (rtx *)); | |
7587 | space = (rtx *) alloca (current_nr_blocks * maxreg * sizeof (rtx)); | |
7588 | bzero ((char *) space, current_nr_blocks * maxreg * sizeof (rtx)); | |
7589 | init_rtx_vector (bb_reg_last_clobbers, space, current_nr_blocks, | |
7590 | maxreg * sizeof (rtx *)); | |
8c660648 JL |
7591 | |
7592 | bb_pending_read_insns = (rtx *) alloca (current_nr_blocks * sizeof (rtx)); | |
7593 | bb_pending_read_mems = (rtx *) alloca (current_nr_blocks * sizeof (rtx)); | |
28c95eff RH |
7594 | bb_pending_write_insns = |
7595 | (rtx *) alloca (current_nr_blocks * sizeof (rtx)); | |
8c660648 | 7596 | bb_pending_write_mems = (rtx *) alloca (current_nr_blocks * sizeof (rtx)); |
28c95eff RH |
7597 | bb_pending_lists_length = |
7598 | (int *) alloca (current_nr_blocks * sizeof (int)); | |
7599 | bb_last_pending_memory_flush = | |
7600 | (rtx *) alloca (current_nr_blocks * sizeof (rtx)); | |
8c660648 | 7601 | bb_last_function_call = (rtx *) alloca (current_nr_blocks * sizeof (rtx)); |
28c95eff RH |
7602 | bb_sched_before_next_call = |
7603 | (rtx *) alloca (current_nr_blocks * sizeof (rtx)); | |
8c660648 JL |
7604 | |
7605 | init_rgn_data_dependences (current_nr_blocks); | |
7606 | } | |
7607 | ||
63de6c74 | 7608 | /* Compute LOG_LINKS. */ |
8c660648 JL |
7609 | for (bb = 0; bb < current_nr_blocks; bb++) |
7610 | compute_block_backward_dependences (bb); | |
7611 | ||
63de6c74 | 7612 | /* Compute INSN_DEPEND. */ |
8c660648 JL |
7613 | for (bb = current_nr_blocks - 1; bb >= 0; bb--) |
7614 | compute_block_forward_dependences (bb); | |
7615 | ||
7616 | /* Delete line notes, compute live-regs at block end, and set priorities. */ | |
7617 | dead_notes = 0; | |
7618 | for (bb = 0; bb < current_nr_blocks; bb++) | |
7619 | { | |
7620 | if (reload_completed == 0) | |
7621 | find_pre_sched_live (bb); | |
7622 | ||
7623 | if (write_symbols != NO_DEBUG) | |
7624 | { | |
7625 | save_line_notes (bb); | |
7626 | rm_line_notes (bb); | |
7627 | } | |
7628 | ||
7629 | rgn_n_insns += set_priorities (bb); | |
7630 | } | |
7631 | ||
63de6c74 | 7632 | /* Compute interblock info: probabilities, split-edges, dominators, etc. */ |
8c660648 JL |
7633 | if (current_nr_blocks > 1) |
7634 | { | |
7635 | int i; | |
7636 | ||
7637 | prob = (float *) alloca ((current_nr_blocks) * sizeof (float)); | |
7638 | ||
7639 | bbset_size = current_nr_blocks / HOST_BITS_PER_WIDE_INT + 1; | |
7640 | dom = (bbset *) alloca (current_nr_blocks * sizeof (bbset)); | |
7641 | for (i = 0; i < current_nr_blocks; i++) | |
7642 | { | |
7643 | dom[i] = (bbset) alloca (bbset_size * sizeof (HOST_WIDE_INT)); | |
7644 | bzero ((char *) dom[i], bbset_size * sizeof (HOST_WIDE_INT)); | |
7645 | } | |
7646 | ||
63de6c74 | 7647 | /* Edge to bit. */ |
8c660648 JL |
7648 | rgn_nr_edges = 0; |
7649 | edge_to_bit = (int *) alloca (nr_edges * sizeof (int)); | |
7650 | for (i = 1; i < nr_edges; i++) | |
7651 | if (CONTAINING_RGN (FROM_BLOCK (i)) == rgn) | |
7652 | EDGE_TO_BIT (i) = rgn_nr_edges++; | |
7653 | rgn_edges = (int *) alloca (rgn_nr_edges * sizeof (int)); | |
7654 | ||
7655 | rgn_nr_edges = 0; | |
7656 | for (i = 1; i < nr_edges; i++) | |
7657 | if (CONTAINING_RGN (FROM_BLOCK (i)) == (rgn)) | |
7658 | rgn_edges[rgn_nr_edges++] = i; | |
7659 | ||
63de6c74 | 7660 | /* Split edges. */ |
8c660648 JL |
7661 | edgeset_size = rgn_nr_edges / HOST_BITS_PER_WIDE_INT + 1; |
7662 | pot_split = (edgeset *) alloca (current_nr_blocks * sizeof (edgeset)); | |
63de6c74 MH |
7663 | ancestor_edges = (edgeset *) alloca (current_nr_blocks |
7664 | * sizeof (edgeset)); | |
8c660648 JL |
7665 | for (i = 0; i < current_nr_blocks; i++) |
7666 | { | |
7667 | pot_split[i] = | |
7668 | (edgeset) alloca (edgeset_size * sizeof (HOST_WIDE_INT)); | |
7669 | bzero ((char *) pot_split[i], | |
7670 | edgeset_size * sizeof (HOST_WIDE_INT)); | |
7671 | ancestor_edges[i] = | |
7672 | (edgeset) alloca (edgeset_size * sizeof (HOST_WIDE_INT)); | |
7673 | bzero ((char *) ancestor_edges[i], | |
7674 | edgeset_size * sizeof (HOST_WIDE_INT)); | |
7675 | } | |
7676 | ||
63de6c74 | 7677 | /* Compute probabilities, dominators, split_edges. */ |
8c660648 JL |
7678 | for (bb = 0; bb < current_nr_blocks; bb++) |
7679 | compute_dom_prob_ps (bb); | |
7680 | } | |
7681 | ||
63de6c74 | 7682 | /* Now we can schedule all blocks. */ |
8c660648 JL |
7683 | for (bb = 0; bb < current_nr_blocks; bb++) |
7684 | { | |
5835e573 | 7685 | sched_rgn_n_insns += schedule_block (bb, rgn_n_insns); |
8c660648 JL |
7686 | |
7687 | #ifdef USE_C_ALLOCA | |
7688 | alloca (0); | |
7689 | #endif | |
7690 | } | |
7691 | ||
63de6c74 | 7692 | /* Sanity check: verify that all region insns were scheduled. */ |
cc132865 JL |
7693 | if (sched_rgn_n_insns != rgn_n_insns) |
7694 | abort (); | |
8c660648 | 7695 | |
63de6c74 | 7696 | /* Update register life and usage information. */ |
8c660648 JL |
7697 | if (reload_completed == 0) |
7698 | { | |
7699 | for (bb = current_nr_blocks - 1; bb >= 0; bb--) | |
7700 | find_post_sched_live (bb); | |
7701 | ||
7702 | if (current_nr_blocks <= 1) | |
63de6c74 MH |
7703 | /* Sanity check. There should be no REG_DEAD notes leftover |
7704 | at the end. In practice, this can occur as the result of | |
7705 | bugs in flow, combine.c, and/or sched.c. The values of the | |
7706 | REG_DEAD notes remaining are meaningless, because | |
7707 | dead_notes is just used as a free list. */ | |
8c660648 JL |
7708 | if (dead_notes != 0) |
7709 | abort (); | |
7710 | } | |
7711 | ||
63de6c74 | 7712 | /* Restore line notes. */ |
8c660648 JL |
7713 | if (write_symbols != NO_DEBUG) |
7714 | { | |
7715 | for (bb = 0; bb < current_nr_blocks; bb++) | |
7716 | restore_line_notes (bb); | |
7717 | } | |
7718 | ||
63de6c74 | 7719 | /* Done with this region. */ |
8c660648 | 7720 | free_pending_lists (); |
f187056f JL |
7721 | |
7722 | FREE_REG_SET (reg_pending_sets); | |
28c95eff | 7723 | FREE_REG_SET (reg_pending_clobbers); |
8c660648 JL |
7724 | } |
7725 | ||
8c660648 JL |
7726 | /* The one entry point in this file. DUMP_FILE is the dump file for |
7727 | this pass. */ | |
7728 | ||
7729 | void | |
7730 | schedule_insns (dump_file) | |
7731 | FILE *dump_file; | |
7732 | { | |
7733 | ||
7734 | int max_uid; | |
7735 | int b; | |
8c660648 JL |
7736 | rtx insn; |
7737 | int rgn; | |
7738 | ||
7739 | int luid; | |
7740 | ||
63de6c74 | 7741 | /* Disable speculative loads in their presence if cc0 defined. */ |
8c660648 JL |
7742 | #ifdef HAVE_cc0 |
7743 | flag_schedule_speculative_load = 0; | |
7744 | #endif | |
7745 | ||
7746 | /* Taking care of this degenerate case makes the rest of | |
7747 | this code simpler. */ | |
7748 | if (n_basic_blocks == 0) | |
7749 | return; | |
7750 | ||
63de6c74 | 7751 | /* Set dump and sched_verbose for the desired debugging output. If no |
8c660648 JL |
7752 | dump-file was specified, but -fsched-verbose-N (any N), print to stderr. |
7753 | For -fsched-verbose-N, N>=10, print everything to stderr. */ | |
7754 | sched_verbose = sched_verbose_param; | |
7755 | if (sched_verbose_param == 0 && dump_file) | |
7756 | sched_verbose = 1; | |
7757 | dump = ((sched_verbose_param >= 10 || !dump_file) ? stderr : dump_file); | |
7758 | ||
7759 | nr_inter = 0; | |
7760 | nr_spec = 0; | |
7761 | ||
63de6c74 | 7762 | /* Initialize issue_rate. */ |
62d65906 | 7763 | issue_rate = ISSUE_RATE; |
8c660648 | 7764 | |
63de6c74 | 7765 | /* Do the splitting first for all blocks. */ |
8c660648 | 7766 | for (b = 0; b < n_basic_blocks; b++) |
ca545bb5 | 7767 | split_block_insns (b, 1); |
8c660648 JL |
7768 | |
7769 | max_uid = (get_max_uid () + 1); | |
7770 | ||
ad85216e KG |
7771 | cant_move = xcalloc (max_uid, sizeof (char)); |
7772 | fed_by_spec_load = xcalloc (max_uid, sizeof (char)); | |
7773 | is_load_insn = xcalloc (max_uid, sizeof (char)); | |
8c660648 | 7774 | |
7c74b010 JW |
7775 | insn_orig_block = (int *) xmalloc (max_uid * sizeof (int)); |
7776 | insn_luid = (int *) xmalloc (max_uid * sizeof (int)); | |
8c660648 JL |
7777 | |
7778 | luid = 0; | |
7779 | for (b = 0; b < n_basic_blocks; b++) | |
3b413743 | 7780 | for (insn = BLOCK_HEAD (b);; insn = NEXT_INSN (insn)) |
8c660648 JL |
7781 | { |
7782 | INSN_BLOCK (insn) = b; | |
7783 | INSN_LUID (insn) = luid++; | |
7784 | ||
3b413743 | 7785 | if (insn == BLOCK_END (b)) |
8c660648 JL |
7786 | break; |
7787 | } | |
7788 | ||
63de6c74 | 7789 | /* After reload, remove inter-blocks dependences computed before reload. */ |
8c660648 JL |
7790 | if (reload_completed) |
7791 | { | |
7792 | int b; | |
7793 | rtx insn; | |
7794 | ||
7795 | for (b = 0; b < n_basic_blocks; b++) | |
3b413743 | 7796 | for (insn = BLOCK_HEAD (b);; insn = NEXT_INSN (insn)) |
8c660648 | 7797 | { |
c995fea1 | 7798 | rtx link, prev; |
8c660648 JL |
7799 | |
7800 | if (GET_RTX_CLASS (GET_CODE (insn)) == 'i') | |
7801 | { | |
c995fea1 RH |
7802 | prev = NULL_RTX; |
7803 | link = LOG_LINKS (insn); | |
7804 | while (link) | |
8c660648 JL |
7805 | { |
7806 | rtx x = XEXP (link, 0); | |
7807 | ||
7808 | if (INSN_BLOCK (x) != b) | |
c995fea1 RH |
7809 | { |
7810 | remove_dependence (insn, x); | |
7811 | link = prev ? XEXP (prev, 1) : LOG_LINKS (insn); | |
7812 | } | |
7813 | else | |
7814 | prev = link, link = XEXP (prev, 1); | |
8c660648 JL |
7815 | } |
7816 | } | |
7817 | ||
3b413743 | 7818 | if (insn == BLOCK_END (b)) |
8c660648 JL |
7819 | break; |
7820 | } | |
7821 | } | |
7822 | ||
7823 | nr_regions = 0; | |
7824 | rgn_table = (region *) alloca ((n_basic_blocks) * sizeof (region)); | |
7825 | rgn_bb_table = (int *) alloca ((n_basic_blocks) * sizeof (int)); | |
7826 | block_to_bb = (int *) alloca ((n_basic_blocks) * sizeof (int)); | |
7827 | containing_rgn = (int *) alloca ((n_basic_blocks) * sizeof (int)); | |
7828 | ||
63de6c74 | 7829 | /* Compute regions for scheduling. */ |
8c660648 JL |
7830 | if (reload_completed |
7831 | || n_basic_blocks == 1 | |
7832 | || !flag_schedule_interblock) | |
7833 | { | |
7834 | find_single_block_region (); | |
7835 | } | |
7836 | else | |
7837 | { | |
63de6c74 | 7838 | /* Verify that a 'good' control flow graph can be built. */ |
168cbdf9 | 7839 | if (is_cfg_nonregular ()) |
8c660648 JL |
7840 | { |
7841 | find_single_block_region (); | |
7842 | } | |
7843 | else | |
7844 | { | |
a2e68776 JL |
7845 | int_list_ptr *s_preds, *s_succs; |
7846 | int *num_preds, *num_succs; | |
7847 | sbitmap *dom, *pdom; | |
7848 | ||
7849 | s_preds = (int_list_ptr *) alloca (n_basic_blocks | |
7850 | * sizeof (int_list_ptr)); | |
7851 | s_succs = (int_list_ptr *) alloca (n_basic_blocks | |
7852 | * sizeof (int_list_ptr)); | |
7853 | num_preds = (int *) alloca (n_basic_blocks * sizeof (int)); | |
7854 | num_succs = (int *) alloca (n_basic_blocks * sizeof (int)); | |
7855 | dom = sbitmap_vector_alloc (n_basic_blocks, n_basic_blocks); | |
7856 | pdom = sbitmap_vector_alloc (n_basic_blocks, n_basic_blocks); | |
7857 | ||
7858 | /* The scheduler runs after flow; therefore, we can't blindly call | |
7859 | back into find_basic_blocks since doing so could invalidate the | |
e881bb1b | 7860 | info in global_live_at_start. |
a2e68776 JL |
7861 | |
7862 | Consider a block consisting entirely of dead stores; after life | |
7863 | analysis it would be a block of NOTE_INSN_DELETED notes. If | |
7864 | we call find_basic_blocks again, then the block would be removed | |
7865 | entirely and invalidate our the register live information. | |
7866 | ||
7867 | We could (should?) recompute register live information. Doing | |
7868 | so may even be beneficial. */ | |
7869 | ||
5d27de7d | 7870 | compute_preds_succs (s_preds, s_succs, num_preds, num_succs); |
a2e68776 | 7871 | |
63de6c74 MH |
7872 | /* Compute the dominators and post dominators. We don't |
7873 | currently use post dominators, but we should for | |
7874 | speculative motion analysis. */ | |
a2e68776 JL |
7875 | compute_dominators (dom, pdom, s_preds, s_succs); |
7876 | ||
168cbdf9 JL |
7877 | /* build_control_flow will return nonzero if it detects unreachable |
7878 | blocks or any other irregularity with the cfg which prevents | |
7879 | cross block scheduling. */ | |
a2e68776 | 7880 | if (build_control_flow (s_preds, s_succs, num_preds, num_succs) != 0) |
168cbdf9 JL |
7881 | find_single_block_region (); |
7882 | else | |
a2e68776 | 7883 | find_rgns (s_preds, s_succs, num_preds, num_succs, dom); |
8c660648 JL |
7884 | |
7885 | if (sched_verbose >= 3) | |
a2e68776 | 7886 | debug_regions (); |
8c660648 | 7887 | |
a2e68776 | 7888 | /* For now. This will move as more and more of haifa is converted |
63de6c74 | 7889 | to using the cfg code in flow.c. */ |
a2e68776 JL |
7890 | free_bb_mem (); |
7891 | free (dom); | |
7892 | free (pdom); | |
8c660648 JL |
7893 | } |
7894 | } | |
7895 | ||
7896 | /* Allocate data for this pass. See comments, above, | |
7c74b010 JW |
7897 | for what these vectors do. |
7898 | ||
7899 | We use xmalloc instead of alloca, because max_uid can be very large | |
7900 | when there is a lot of function inlining. If we used alloca, we could | |
7901 | exceed stack limits on some hosts for some inputs. */ | |
ad85216e KG |
7902 | insn_priority = (int *) xcalloc (max_uid, sizeof (int)); |
7903 | insn_reg_weight = (int *) xcalloc (max_uid, sizeof (int)); | |
7904 | insn_tick = (int *) xcalloc (max_uid, sizeof (int)); | |
7905 | insn_costs = (short *) xcalloc (max_uid, sizeof (short)); | |
7906 | insn_units = (short *) xcalloc (max_uid, sizeof (short)); | |
7907 | insn_blockage = (unsigned int *) xcalloc (max_uid, sizeof (unsigned int)); | |
7908 | insn_ref_count = (int *) xcalloc (max_uid, sizeof (int)); | |
8c660648 | 7909 | |
63de6c74 | 7910 | /* Allocate for forward dependencies. */ |
ad85216e KG |
7911 | insn_dep_count = (int *) xcalloc (max_uid, sizeof (int)); |
7912 | insn_depend = (rtx *) xcalloc (max_uid, sizeof (rtx)); | |
8c660648 JL |
7913 | |
7914 | if (reload_completed == 0) | |
7915 | { | |
7916 | int i; | |
7917 | ||
7918 | sched_reg_n_calls_crossed = (int *) alloca (max_regno * sizeof (int)); | |
7919 | sched_reg_live_length = (int *) alloca (max_regno * sizeof (int)); | |
7920 | sched_reg_basic_block = (int *) alloca (max_regno * sizeof (int)); | |
7921 | bb_live_regs = ALLOCA_REG_SET (); | |
7922 | bzero ((char *) sched_reg_n_calls_crossed, max_regno * sizeof (int)); | |
7923 | bzero ((char *) sched_reg_live_length, max_regno * sizeof (int)); | |
7924 | ||
7925 | for (i = 0; i < max_regno; i++) | |
7926 | sched_reg_basic_block[i] = REG_BLOCK_UNKNOWN; | |
7927 | } | |
7928 | else | |
7929 | { | |
7930 | sched_reg_n_calls_crossed = 0; | |
7931 | sched_reg_live_length = 0; | |
7932 | bb_live_regs = 0; | |
7933 | } | |
7934 | init_alias_analysis (); | |
7935 | ||
7936 | if (write_symbols != NO_DEBUG) | |
7937 | { | |
7938 | rtx line; | |
7939 | ||
ad85216e | 7940 | line_note = (rtx *) xcalloc (max_uid, sizeof (rtx)); |
8c660648 JL |
7941 | line_note_head = (rtx *) alloca (n_basic_blocks * sizeof (rtx)); |
7942 | bzero ((char *) line_note_head, n_basic_blocks * sizeof (rtx)); | |
7943 | ||
7944 | /* Save-line-note-head: | |
7945 | Determine the line-number at the start of each basic block. | |
7946 | This must be computed and saved now, because after a basic block's | |
7947 | predecessor has been scheduled, it is impossible to accurately | |
7948 | determine the correct line number for the first insn of the block. */ | |
7949 | ||
7950 | for (b = 0; b < n_basic_blocks; b++) | |
3b413743 | 7951 | for (line = BLOCK_HEAD (b); line; line = PREV_INSN (line)) |
8c660648 JL |
7952 | if (GET_CODE (line) == NOTE && NOTE_LINE_NUMBER (line) > 0) |
7953 | { | |
7954 | line_note_head[b] = line; | |
7955 | break; | |
7956 | } | |
7957 | } | |
7958 | ||
63de6c74 | 7959 | /* Find units used in this fuction, for visualization. */ |
8c660648 JL |
7960 | if (sched_verbose) |
7961 | init_target_units (); | |
7962 | ||
7963 | /* ??? Add a NOTE after the last insn of the last basic block. It is not | |
7964 | known why this is done. */ | |
7965 | ||
3b413743 | 7966 | insn = BLOCK_END (n_basic_blocks - 1); |
8c660648 JL |
7967 | if (NEXT_INSN (insn) == 0 |
7968 | || (GET_CODE (insn) != NOTE | |
7969 | && GET_CODE (insn) != CODE_LABEL | |
3b413743 RH |
7970 | /* Don't emit a NOTE if it would end up between an unconditional |
7971 | jump and a BARRIER. */ | |
8c660648 JL |
7972 | && !(GET_CODE (insn) == JUMP_INSN |
7973 | && GET_CODE (NEXT_INSN (insn)) == BARRIER))) | |
3b413743 | 7974 | emit_note_after (NOTE_INSN_DELETED, BLOCK_END (n_basic_blocks - 1)); |
8c660648 | 7975 | |
63de6c74 | 7976 | /* Schedule every region in the subroutine. */ |
8c660648 JL |
7977 | for (rgn = 0; rgn < nr_regions; rgn++) |
7978 | { | |
7979 | schedule_region (rgn); | |
7980 | ||
7981 | #ifdef USE_C_ALLOCA | |
7982 | alloca (0); | |
7983 | #endif | |
7984 | } | |
7985 | ||
7986 | /* Reposition the prologue and epilogue notes in case we moved the | |
7987 | prologue/epilogue insns. */ | |
7988 | if (reload_completed) | |
7989 | reposition_prologue_and_epilogue_notes (get_insns ()); | |
7990 | ||
63de6c74 | 7991 | /* Delete redundant line notes. */ |
8c660648 JL |
7992 | if (write_symbols != NO_DEBUG) |
7993 | rm_redundant_line_notes (); | |
7994 | ||
7995 | /* Update information about uses of registers in the subroutine. */ | |
7996 | if (reload_completed == 0) | |
7997 | update_reg_usage (); | |
7998 | ||
7999 | if (sched_verbose) | |
8000 | { | |
8001 | if (reload_completed == 0 && flag_schedule_interblock) | |
8002 | { | |
8003 | fprintf (dump, "\n;; Procedure interblock/speculative motions == %d/%d \n", | |
8004 | nr_inter, nr_spec); | |
8005 | } | |
8006 | else | |
8007 | { | |
8008 | if (nr_inter > 0) | |
8009 | abort (); | |
8010 | } | |
8011 | fprintf (dump, "\n\n"); | |
8012 | } | |
f187056f | 8013 | |
7c74b010 JW |
8014 | free (cant_move); |
8015 | free (fed_by_spec_load); | |
8016 | free (is_load_insn); | |
8017 | free (insn_orig_block); | |
8018 | free (insn_luid); | |
8019 | ||
8020 | free (insn_priority); | |
8021 | free (insn_reg_weight); | |
8022 | free (insn_tick); | |
8023 | free (insn_costs); | |
8024 | free (insn_units); | |
8025 | free (insn_blockage); | |
8026 | free (insn_ref_count); | |
8027 | ||
8028 | free (insn_dep_count); | |
8029 | free (insn_depend); | |
8030 | ||
8031 | if (write_symbols != NO_DEBUG) | |
8032 | free (line_note); | |
8033 | ||
f187056f JL |
8034 | if (bb_live_regs) |
8035 | FREE_REG_SET (bb_live_regs); | |
168cbdf9 JL |
8036 | |
8037 | if (edge_table) | |
8038 | { | |
8039 | free (edge_table); | |
8040 | edge_table = NULL; | |
8041 | } | |
8042 | ||
8043 | if (in_edges) | |
8044 | { | |
8045 | free (in_edges); | |
8046 | in_edges = NULL; | |
8047 | } | |
8048 | if (out_edges) | |
8049 | { | |
8050 | free (out_edges); | |
8051 | out_edges = NULL; | |
8052 | } | |
8c660648 JL |
8053 | } |
8054 | #endif /* INSN_SCHEDULING */ |