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8c660648 | 1 | /* Instruction scheduling pass. |
d050d723 JL |
2 | Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, |
3 | 1999, 2000 Free Software Foundation, Inc. | |
8c660648 JL |
4 | Contributed by Michael Tiemann (tiemann@cygnus.com) Enhanced by, |
5 | and currently maintained by, Jim Wilson (wilson@cygnus.com) | |
6 | ||
5d14e356 RK |
7 | This file is part of GNU CC. |
8 | ||
9 | GNU CC is free software; you can redistribute it and/or modify it | |
10 | under the terms of the GNU General Public License as published by the | |
11 | Free Software Foundation; either version 2, or (at your option) any | |
12 | later version. | |
13 | ||
14 | GNU CC is distributed in the hope that it will be useful, but WITHOUT | |
15 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
16 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
17 | for more details. | |
18 | ||
19 | You should have received a copy of the GNU General Public License | |
20 | along with GNU CC; see the file COPYING. If not, write to the Free | |
21 | the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA | |
22 | 02111-1307, USA. */ | |
8c660648 | 23 | |
8c660648 JL |
24 | /* Instruction scheduling pass. |
25 | ||
26 | This pass implements list scheduling within basic blocks. It is | |
27 | run twice: (1) after flow analysis, but before register allocation, | |
28 | and (2) after register allocation. | |
29 | ||
30 | The first run performs interblock scheduling, moving insns between | |
31 | different blocks in the same "region", and the second runs only | |
32 | basic block scheduling. | |
33 | ||
34 | Interblock motions performed are useful motions and speculative | |
35 | motions, including speculative loads. Motions requiring code | |
36 | duplication are not supported. The identification of motion type | |
37 | and the check for validity of speculative motions requires | |
38 | construction and analysis of the function's control flow graph. | |
39 | The scheduler works as follows: | |
40 | ||
41 | We compute insn priorities based on data dependencies. Flow | |
42 | analysis only creates a fraction of the data-dependencies we must | |
43 | observe: namely, only those dependencies which the combiner can be | |
44 | expected to use. For this pass, we must therefore create the | |
45 | remaining dependencies we need to observe: register dependencies, | |
46 | memory dependencies, dependencies to keep function calls in order, | |
47 | and the dependence between a conditional branch and the setting of | |
48 | condition codes are all dealt with here. | |
49 | ||
50 | The scheduler first traverses the data flow graph, starting with | |
51 | the last instruction, and proceeding to the first, assigning values | |
52 | to insn_priority as it goes. This sorts the instructions | |
53 | topologically by data dependence. | |
54 | ||
55 | Once priorities have been established, we order the insns using | |
56 | list scheduling. This works as follows: starting with a list of | |
57 | all the ready insns, and sorted according to priority number, we | |
58 | schedule the insn from the end of the list by placing its | |
59 | predecessors in the list according to their priority order. We | |
60 | consider this insn scheduled by setting the pointer to the "end" of | |
61 | the list to point to the previous insn. When an insn has no | |
62 | predecessors, we either queue it until sufficient time has elapsed | |
63 | or add it to the ready list. As the instructions are scheduled or | |
64 | when stalls are introduced, the queue advances and dumps insns into | |
65 | the ready list. When all insns down to the lowest priority have | |
66 | been scheduled, the critical path of the basic block has been made | |
67 | as short as possible. The remaining insns are then scheduled in | |
68 | remaining slots. | |
69 | ||
70 | Function unit conflicts are resolved during forward list scheduling | |
71 | by tracking the time when each insn is committed to the schedule | |
72 | and from that, the time the function units it uses must be free. | |
73 | As insns on the ready list are considered for scheduling, those | |
74 | that would result in a blockage of the already committed insns are | |
75 | queued until no blockage will result. | |
76 | ||
77 | The following list shows the order in which we want to break ties | |
78 | among insns in the ready list: | |
79 | ||
80 | 1. choose insn with the longest path to end of bb, ties | |
81 | broken by | |
82 | 2. choose insn with least contribution to register pressure, | |
83 | ties broken by | |
84 | 3. prefer in-block upon interblock motion, ties broken by | |
85 | 4. prefer useful upon speculative motion, ties broken by | |
86 | 5. choose insn with largest control flow probability, ties | |
87 | broken by | |
88 | 6. choose insn with the least dependences upon the previously | |
89 | scheduled insn, or finally | |
2db45993 JL |
90 | 7 choose the insn which has the most insns dependent on it. |
91 | 8. choose insn with lowest UID. | |
8c660648 JL |
92 | |
93 | Memory references complicate matters. Only if we can be certain | |
94 | that memory references are not part of the data dependency graph | |
95 | (via true, anti, or output dependence), can we move operations past | |
96 | memory references. To first approximation, reads can be done | |
97 | independently, while writes introduce dependencies. Better | |
98 | approximations will yield fewer dependencies. | |
99 | ||
100 | Before reload, an extended analysis of interblock data dependences | |
101 | is required for interblock scheduling. This is performed in | |
102 | compute_block_backward_dependences (). | |
103 | ||
104 | Dependencies set up by memory references are treated in exactly the | |
105 | same way as other dependencies, by using LOG_LINKS backward | |
106 | dependences. LOG_LINKS are translated into INSN_DEPEND forward | |
107 | dependences for the purpose of forward list scheduling. | |
108 | ||
109 | Having optimized the critical path, we may have also unduly | |
110 | extended the lifetimes of some registers. If an operation requires | |
111 | that constants be loaded into registers, it is certainly desirable | |
112 | to load those constants as early as necessary, but no earlier. | |
113 | I.e., it will not do to load up a bunch of registers at the | |
114 | beginning of a basic block only to use them at the end, if they | |
115 | could be loaded later, since this may result in excessive register | |
116 | utilization. | |
117 | ||
118 | Note that since branches are never in basic blocks, but only end | |
119 | basic blocks, this pass will not move branches. But that is ok, | |
120 | since we can use GNU's delayed branch scheduling pass to take care | |
121 | of this case. | |
122 | ||
123 | Also note that no further optimizations based on algebraic | |
124 | identities are performed, so this pass would be a good one to | |
125 | perform instruction splitting, such as breaking up a multiply | |
126 | instruction into shifts and adds where that is profitable. | |
127 | ||
128 | Given the memory aliasing analysis that this pass should perform, | |
129 | it should be possible to remove redundant stores to memory, and to | |
130 | load values from registers instead of hitting memory. | |
131 | ||
132 | Before reload, speculative insns are moved only if a 'proof' exists | |
133 | that no exception will be caused by this, and if no live registers | |
134 | exist that inhibit the motion (live registers constraints are not | |
135 | represented by data dependence edges). | |
136 | ||
137 | This pass must update information that subsequent passes expect to | |
138 | be correct. Namely: reg_n_refs, reg_n_sets, reg_n_deaths, | |
3b413743 RH |
139 | reg_n_calls_crossed, and reg_live_length. Also, BLOCK_HEAD, |
140 | BLOCK_END. | |
8c660648 JL |
141 | |
142 | The information in the line number notes is carefully retained by | |
143 | this pass. Notes that refer to the starting and ending of | |
144 | exception regions are also carefully retained by this pass. All | |
145 | other NOTE insns are grouped in their same relative order at the | |
146 | beginning of basic blocks and regions that have been scheduled. | |
147 | ||
148 | The main entry point for this pass is schedule_insns(), called for | |
149 | each function. The work of the scheduler is organized in three | |
150 | levels: (1) function level: insns are subject to splitting, | |
151 | control-flow-graph is constructed, regions are computed (after | |
152 | reload, each region is of one block), (2) region level: control | |
153 | flow graph attributes required for interblock scheduling are | |
154 | computed (dominators, reachability, etc.), data dependences and | |
155 | priorities are computed, and (3) block level: insns in the block | |
156 | are actually scheduled. */ | |
157 | \f | |
8c660648 | 158 | #include "config.h" |
5835e573 | 159 | #include "system.h" |
01198c2f | 160 | #include "toplev.h" |
8c660648 | 161 | #include "rtl.h" |
6baf1cc8 | 162 | #include "tm_p.h" |
efc9bd41 | 163 | #include "hard-reg-set.h" |
8c660648 JL |
164 | #include "basic-block.h" |
165 | #include "regs.h" | |
49ad7cfa | 166 | #include "function.h" |
8c660648 JL |
167 | #include "flags.h" |
168 | #include "insn-config.h" | |
169 | #include "insn-attr.h" | |
170 | #include "except.h" | |
487a6e06 | 171 | #include "toplev.h" |
79c9824e | 172 | #include "recog.h" |
8c660648 JL |
173 | |
174 | extern char *reg_known_equiv_p; | |
175 | extern rtx *reg_known_value; | |
176 | ||
177 | #ifdef INSN_SCHEDULING | |
178 | ||
8c660648 JL |
179 | /* target_units bitmask has 1 for each unit in the cpu. It should be |
180 | possible to compute this variable from the machine description. | |
63de6c74 | 181 | But currently it is computed by examining the insn list. Since |
8c660648 JL |
182 | this is only needed for visualization, it seems an acceptable |
183 | solution. (For understanding the mapping of bits to units, see | |
63de6c74 | 184 | definition of function_units[] in "insn-attrtab.c".) */ |
8c660648 | 185 | |
61822835 | 186 | static int target_units = 0; |
8c660648 JL |
187 | |
188 | /* issue_rate is the number of insns that can be scheduled in the same | |
189 | machine cycle. It can be defined in the config/mach/mach.h file, | |
190 | otherwise we set it to 1. */ | |
191 | ||
192 | static int issue_rate; | |
193 | ||
62d65906 JL |
194 | #ifndef ISSUE_RATE |
195 | #define ISSUE_RATE 1 | |
8c660648 JL |
196 | #endif |
197 | ||
cc132865 | 198 | /* sched-verbose controls the amount of debugging output the |
409f8483 | 199 | scheduler prints. It is controlled by -fsched-verbose=N: |
8c660648 JL |
200 | N>0 and no -DSR : the output is directed to stderr. |
201 | N>=10 will direct the printouts to stderr (regardless of -dSR). | |
202 | N=1: same as -dSR. | |
203 | N=2: bb's probabilities, detailed ready list info, unit/insn info. | |
204 | N=3: rtl at abort point, control-flow, regions info. | |
cc132865 | 205 | N=5: dependences info. */ |
8c660648 JL |
206 | |
207 | #define MAX_RGN_BLOCKS 10 | |
208 | #define MAX_RGN_INSNS 100 | |
209 | ||
8c660648 JL |
210 | static int sched_verbose_param = 0; |
211 | static int sched_verbose = 0; | |
8c660648 | 212 | |
63de6c74 | 213 | /* nr_inter/spec counts interblock/speculative motion for the function. */ |
8c660648 JL |
214 | static int nr_inter, nr_spec; |
215 | ||
63de6c74 | 216 | /* Debugging file. All printouts are sent to dump, which is always set, |
8c660648 JL |
217 | either to stderr, or to the dump listing file (-dRS). */ |
218 | static FILE *dump = 0; | |
219 | ||
220 | /* fix_sched_param() is called from toplev.c upon detection | |
409f8483 | 221 | of the -fsched-verbose=N option. */ |
8c660648 JL |
222 | |
223 | void | |
224 | fix_sched_param (param, val) | |
5f06c983 | 225 | const char *param, *val; |
8c660648 | 226 | { |
cc132865 | 227 | if (!strcmp (param, "verbose")) |
8c660648 | 228 | sched_verbose_param = atoi (val); |
8c660648 JL |
229 | else |
230 | warning ("fix_sched_param: unknown param: %s", param); | |
231 | } | |
232 | ||
e1306f49 BS |
233 | /* Describe state of dependencies used during sched_analyze phase. */ |
234 | struct deps | |
235 | { | |
236 | /* The *_insns and *_mems are paired lists. Each pending memory operation | |
237 | will have a pointer to the MEM rtx on one list and a pointer to the | |
238 | containing insn on the other list in the same place in the list. */ | |
239 | ||
240 | /* We can't use add_dependence like the old code did, because a single insn | |
241 | may have multiple memory accesses, and hence needs to be on the list | |
242 | once for each memory access. Add_dependence won't let you add an insn | |
243 | to a list more than once. */ | |
244 | ||
245 | /* An INSN_LIST containing all insns with pending read operations. */ | |
246 | rtx pending_read_insns; | |
247 | ||
248 | /* An EXPR_LIST containing all MEM rtx's which are pending reads. */ | |
249 | rtx pending_read_mems; | |
250 | ||
251 | /* An INSN_LIST containing all insns with pending write operations. */ | |
252 | rtx pending_write_insns; | |
253 | ||
254 | /* An EXPR_LIST containing all MEM rtx's which are pending writes. */ | |
255 | rtx pending_write_mems; | |
256 | ||
257 | /* Indicates the combined length of the two pending lists. We must prevent | |
258 | these lists from ever growing too large since the number of dependencies | |
259 | produced is at least O(N*N), and execution time is at least O(4*N*N), as | |
260 | a function of the length of these pending lists. */ | |
261 | int pending_lists_length; | |
262 | ||
263 | /* The last insn upon which all memory references must depend. | |
264 | This is an insn which flushed the pending lists, creating a dependency | |
265 | between it and all previously pending memory references. This creates | |
266 | a barrier (or a checkpoint) which no memory reference is allowed to cross. | |
267 | ||
268 | This includes all non constant CALL_INSNs. When we do interprocedural | |
269 | alias analysis, this restriction can be relaxed. | |
270 | This may also be an INSN that writes memory if the pending lists grow | |
271 | too large. */ | |
272 | rtx last_pending_memory_flush; | |
273 | ||
274 | /* The last function call we have seen. All hard regs, and, of course, | |
275 | the last function call, must depend on this. */ | |
276 | rtx last_function_call; | |
277 | ||
ef384380 RH |
278 | /* Used to keep post-call psuedo/hard reg movements together with |
279 | the call. */ | |
280 | int in_post_call_group_p; | |
281 | ||
282 | /* The LOG_LINKS field of this is a list of insns which use a pseudo | |
283 | register that does not already cross a call. We create | |
284 | dependencies between each of those insn and the next call insn, | |
285 | to ensure that they won't cross a call after scheduling is done. */ | |
e1306f49 BS |
286 | rtx sched_before_next_call; |
287 | ||
288 | /* Element N is the next insn that sets (hard or pseudo) register | |
289 | N within the current basic block; or zero, if there is no | |
290 | such insn. Needed for new registers which may be introduced | |
291 | by splitting insns. */ | |
292 | rtx *reg_last_uses; | |
293 | rtx *reg_last_sets; | |
294 | rtx *reg_last_clobbers; | |
295 | }; | |
8c660648 | 296 | |
8c660648 | 297 | static regset reg_pending_sets; |
28c95eff | 298 | static regset reg_pending_clobbers; |
8c660648 JL |
299 | static int reg_pending_sets_all; |
300 | ||
178b88b9 VM |
301 | /* To speed up the test for duplicate dependency links we keep a |
302 | record of dependencies created by add_dependence when the average | |
303 | number of instructions in a basic block is very large. | |
356edbd7 | 304 | |
aae0390e JL |
305 | Studies have shown that there is typically around 5 instructions between |
306 | branches for typical C code. So we can make a guess that the average | |
307 | basic block is approximately 5 instructions long; we will choose 100X | |
308 | the average size as a very large basic block. | |
7a403706 | 309 | |
178b88b9 VM |
310 | Each insn has associated bitmaps for its dependencies. Each bitmap |
311 | has enough entries to represent a dependency on any other insn in | |
312 | the insn chain. All bitmap for true dependencies cache is | |
313 | allocated then the rest two ones are also allocated. */ | |
356edbd7 | 314 | static sbitmap *true_dependency_cache; |
178b88b9 VM |
315 | static sbitmap *anti_dependency_cache; |
316 | static sbitmap *output_dependency_cache; | |
317 | ||
318 | /* To speed up checking consistency of formed forward insn | |
319 | dependencies we use the following cache. Another possible solution | |
320 | could be switching off checking duplication of insns in forward | |
321 | dependencies. */ | |
322 | #ifdef ENABLE_CHECKING | |
323 | static sbitmap *forward_dependency_cache; | |
324 | #endif | |
356edbd7 | 325 | |
f66d83e1 RH |
326 | /* Indexed by INSN_UID, the collection of all data associated with |
327 | a single instruction. */ | |
328 | ||
329 | struct haifa_insn_data | |
330 | { | |
331 | /* A list of insns which depend on the instruction. Unlike LOG_LINKS, | |
332 | it represents forward dependancies. */ | |
333 | rtx depend; | |
334 | ||
7a403706 | 335 | /* The line number note in effect for each insn. For line number |
f66d83e1 RH |
336 | notes, this indicates whether the note may be reused. */ |
337 | rtx line_note; | |
338 | ||
339 | /* Logical uid gives the original ordering of the insns. */ | |
340 | int luid; | |
341 | ||
342 | /* A priority for each insn. */ | |
343 | int priority; | |
344 | ||
345 | /* The number of incoming edges in the forward dependency graph. | |
346 | As scheduling proceds, counts are decreased. An insn moves to | |
347 | the ready queue when its counter reaches zero. */ | |
348 | int dep_count; | |
349 | ||
350 | /* An encoding of the blockage range function. Both unit and range | |
351 | are coded. */ | |
352 | unsigned int blockage; | |
353 | ||
354 | /* Number of instructions referring to this insn. */ | |
355 | int ref_count; | |
356 | ||
357 | /* The minimum clock tick at which the insn becomes ready. This is | |
358 | used to note timing constraints for the insns in the pending list. */ | |
359 | int tick; | |
360 | ||
361 | short cost; | |
362 | ||
363 | /* An encoding of the function units used. */ | |
364 | short units; | |
365 | ||
366 | /* This weight is an estimation of the insn's contribution to | |
367 | register pressure. */ | |
368 | short reg_weight; | |
369 | ||
370 | /* Some insns (e.g. call) are not allowed to move across blocks. */ | |
371 | unsigned int cant_move : 1; | |
372 | ||
373 | /* Set if there's DEF-USE dependance between some speculatively | |
374 | moved load insn and this one. */ | |
375 | unsigned int fed_by_spec_load : 1; | |
376 | unsigned int is_load_insn : 1; | |
377 | }; | |
378 | ||
379 | static struct haifa_insn_data *h_i_d; | |
380 | ||
381 | #define INSN_DEPEND(INSN) (h_i_d[INSN_UID (INSN)].depend) | |
382 | #define INSN_LUID(INSN) (h_i_d[INSN_UID (INSN)].luid) | |
383 | #define INSN_PRIORITY(INSN) (h_i_d[INSN_UID (INSN)].priority) | |
384 | #define INSN_DEP_COUNT(INSN) (h_i_d[INSN_UID (INSN)].dep_count) | |
385 | #define INSN_COST(INSN) (h_i_d[INSN_UID (INSN)].cost) | |
386 | #define INSN_UNIT(INSN) (h_i_d[INSN_UID (INSN)].units) | |
387 | #define INSN_REG_WEIGHT(INSN) (h_i_d[INSN_UID (INSN)].reg_weight) | |
388 | ||
389 | #define INSN_BLOCKAGE(INSN) (h_i_d[INSN_UID (INSN)].blockage) | |
390 | #define UNIT_BITS 5 | |
391 | #define BLOCKAGE_MASK ((1 << BLOCKAGE_BITS) - 1) | |
392 | #define ENCODE_BLOCKAGE(U, R) \ | |
393 | (((U) << BLOCKAGE_BITS \ | |
394 | | MIN_BLOCKAGE_COST (R)) << BLOCKAGE_BITS \ | |
395 | | MAX_BLOCKAGE_COST (R)) | |
396 | #define UNIT_BLOCKED(B) ((B) >> (2 * BLOCKAGE_BITS)) | |
8c660648 JL |
397 | #define BLOCKAGE_RANGE(B) \ |
398 | (((((B) >> BLOCKAGE_BITS) & BLOCKAGE_MASK) << (HOST_BITS_PER_INT / 2)) \ | |
5835e573 | 399 | | ((B) & BLOCKAGE_MASK)) |
8c660648 JL |
400 | |
401 | /* Encodings of the `<name>_unit_blockage_range' function. */ | |
402 | #define MIN_BLOCKAGE_COST(R) ((R) >> (HOST_BITS_PER_INT / 2)) | |
403 | #define MAX_BLOCKAGE_COST(R) ((R) & ((1 << (HOST_BITS_PER_INT / 2)) - 1)) | |
404 | ||
405 | #define DONE_PRIORITY -1 | |
406 | #define MAX_PRIORITY 0x7fffffff | |
407 | #define TAIL_PRIORITY 0x7ffffffe | |
408 | #define LAUNCH_PRIORITY 0x7f000001 | |
409 | #define DONE_PRIORITY_P(INSN) (INSN_PRIORITY (INSN) < 0) | |
410 | #define LOW_PRIORITY_P(INSN) ((INSN_PRIORITY (INSN) & 0x7f000000) == 0) | |
411 | ||
f66d83e1 RH |
412 | #define INSN_REF_COUNT(INSN) (h_i_d[INSN_UID (INSN)].ref_count) |
413 | #define LINE_NOTE(INSN) (h_i_d[INSN_UID (INSN)].line_note) | |
414 | #define INSN_TICK(INSN) (h_i_d[INSN_UID (INSN)].tick) | |
415 | #define CANT_MOVE(insn) (h_i_d[INSN_UID (insn)].cant_move) | |
416 | #define FED_BY_SPEC_LOAD(insn) (h_i_d[INSN_UID (insn)].fed_by_spec_load) | |
417 | #define IS_LOAD_INSN(insn) (h_i_d[INSN_UID (insn)].is_load_insn) | |
8c660648 JL |
418 | |
419 | /* Vector indexed by basic block number giving the starting line-number | |
420 | for each basic block. */ | |
421 | static rtx *line_note_head; | |
422 | ||
423 | /* List of important notes we must keep around. This is a pointer to the | |
424 | last element in the list. */ | |
425 | static rtx note_list; | |
426 | ||
8c660648 JL |
427 | /* Queues, etc. */ |
428 | ||
429 | /* An instruction is ready to be scheduled when all insns preceding it | |
430 | have already been scheduled. It is important to ensure that all | |
431 | insns which use its result will not be executed until its result | |
432 | has been computed. An insn is maintained in one of four structures: | |
433 | ||
434 | (P) the "Pending" set of insns which cannot be scheduled until | |
435 | their dependencies have been satisfied. | |
436 | (Q) the "Queued" set of insns that can be scheduled when sufficient | |
437 | time has passed. | |
438 | (R) the "Ready" list of unscheduled, uncommitted insns. | |
439 | (S) the "Scheduled" list of insns. | |
440 | ||
441 | Initially, all insns are either "Pending" or "Ready" depending on | |
442 | whether their dependencies are satisfied. | |
443 | ||
444 | Insns move from the "Ready" list to the "Scheduled" list as they | |
445 | are committed to the schedule. As this occurs, the insns in the | |
446 | "Pending" list have their dependencies satisfied and move to either | |
447 | the "Ready" list or the "Queued" set depending on whether | |
448 | sufficient time has passed to make them ready. As time passes, | |
449 | insns move from the "Queued" set to the "Ready" list. Insns may | |
450 | move from the "Ready" list to the "Queued" set if they are blocked | |
451 | due to a function unit conflict. | |
452 | ||
453 | The "Pending" list (P) are the insns in the INSN_DEPEND of the unscheduled | |
454 | insns, i.e., those that are ready, queued, and pending. | |
455 | The "Queued" set (Q) is implemented by the variable `insn_queue'. | |
456 | The "Ready" list (R) is implemented by the variables `ready' and | |
457 | `n_ready'. | |
458 | The "Scheduled" list (S) is the new insn chain built by this pass. | |
459 | ||
460 | The transition (R->S) is implemented in the scheduling loop in | |
461 | `schedule_block' when the best insn to schedule is chosen. | |
462 | The transition (R->Q) is implemented in `queue_insn' when an | |
38e01259 | 463 | insn is found to have a function unit conflict with the already |
8c660648 JL |
464 | committed insns. |
465 | The transitions (P->R and P->Q) are implemented in `schedule_insn' as | |
466 | insns move from the ready list to the scheduled list. | |
467 | The transition (Q->R) is implemented in 'queue_to_insn' as time | |
468 | passes or stalls are introduced. */ | |
469 | ||
470 | /* Implement a circular buffer to delay instructions until sufficient | |
471 | time has passed. INSN_QUEUE_SIZE is a power of two larger than | |
472 | MAX_BLOCKAGE and MAX_READY_COST computed by genattr.c. This is the | |
473 | longest time an isnsn may be queued. */ | |
474 | static rtx insn_queue[INSN_QUEUE_SIZE]; | |
475 | static int q_ptr = 0; | |
476 | static int q_size = 0; | |
477 | #define NEXT_Q(X) (((X)+1) & (INSN_QUEUE_SIZE-1)) | |
478 | #define NEXT_Q_AFTER(X, C) (((X)+C) & (INSN_QUEUE_SIZE-1)) | |
479 | ||
8c660648 | 480 | /* Forward declarations. */ |
3fe41456 | 481 | static void add_dependence PARAMS ((rtx, rtx, enum reg_note)); |
3fe41456 | 482 | static void remove_dependence PARAMS ((rtx, rtx)); |
3fe41456 | 483 | static rtx find_insn_list PARAMS ((rtx, rtx)); |
ef384380 | 484 | static void set_sched_group_p PARAMS ((rtx)); |
3fe41456 KG |
485 | static int insn_unit PARAMS ((rtx)); |
486 | static unsigned int blockage_range PARAMS ((int, rtx)); | |
487 | static void clear_units PARAMS ((void)); | |
488 | static int actual_hazard_this_instance PARAMS ((int, int, rtx, int, int)); | |
489 | static void schedule_unit PARAMS ((int, rtx, int)); | |
490 | static int actual_hazard PARAMS ((int, rtx, int, int)); | |
491 | static int potential_hazard PARAMS ((int, rtx, int)); | |
492 | static int insn_cost PARAMS ((rtx, rtx, rtx)); | |
493 | static int priority PARAMS ((rtx)); | |
494 | static void free_pending_lists PARAMS ((void)); | |
495 | static void add_insn_mem_dependence PARAMS ((struct deps *, rtx *, rtx *, rtx, | |
7a403706 | 496 | rtx)); |
3fe41456 KG |
497 | static void flush_pending_lists PARAMS ((struct deps *, rtx, int)); |
498 | static void sched_analyze_1 PARAMS ((struct deps *, rtx, rtx)); | |
499 | static void sched_analyze_2 PARAMS ((struct deps *, rtx, rtx)); | |
500 | static void sched_analyze_insn PARAMS ((struct deps *, rtx, rtx, rtx)); | |
501 | static void sched_analyze PARAMS ((struct deps *, rtx, rtx)); | |
502 | static int rank_for_schedule PARAMS ((const PTR, const PTR)); | |
503 | static void swap_sort PARAMS ((rtx *, int)); | |
504 | static void queue_insn PARAMS ((rtx, int)); | |
505 | static int schedule_insn PARAMS ((rtx, rtx *, int, int)); | |
506 | static void find_insn_reg_weight PARAMS ((int)); | |
507 | static int schedule_block PARAMS ((int, int)); | |
508 | static char *safe_concat PARAMS ((char *, char *, const char *)); | |
509 | static int insn_issue_delay PARAMS ((rtx)); | |
510 | static void adjust_priority PARAMS ((rtx)); | |
8c660648 | 511 | |
8c660648 JL |
512 | /* Control flow graph edges are kept in circular lists. */ |
513 | typedef struct | |
7a403706 KH |
514 | { |
515 | int from_block; | |
516 | int to_block; | |
517 | int next_in; | |
518 | int next_out; | |
519 | } | |
e881bb1b RH |
520 | haifa_edge; |
521 | static haifa_edge *edge_table; | |
8c660648 JL |
522 | |
523 | #define NEXT_IN(edge) (edge_table[edge].next_in) | |
524 | #define NEXT_OUT(edge) (edge_table[edge].next_out) | |
525 | #define FROM_BLOCK(edge) (edge_table[edge].from_block) | |
526 | #define TO_BLOCK(edge) (edge_table[edge].to_block) | |
527 | ||
63de6c74 MH |
528 | /* Number of edges in the control flow graph. (In fact, larger than |
529 | that by 1, since edge 0 is unused.) */ | |
8c660648 JL |
530 | static int nr_edges; |
531 | ||
63de6c74 | 532 | /* Circular list of incoming/outgoing edges of a block. */ |
8c660648 JL |
533 | static int *in_edges; |
534 | static int *out_edges; | |
535 | ||
536 | #define IN_EDGES(block) (in_edges[block]) | |
537 | #define OUT_EDGES(block) (out_edges[block]) | |
538 | ||
3fe41456 KG |
539 | static int is_cfg_nonregular PARAMS ((void)); |
540 | static int build_control_flow PARAMS ((struct edge_list *)); | |
541 | static void new_edge PARAMS ((int, int)); | |
8c660648 | 542 | |
8c660648 JL |
543 | /* A region is the main entity for interblock scheduling: insns |
544 | are allowed to move between blocks in the same region, along | |
545 | control flow graph edges, in the 'up' direction. */ | |
546 | typedef struct | |
7a403706 KH |
547 | { |
548 | int rgn_nr_blocks; /* Number of blocks in region. */ | |
549 | int rgn_blocks; /* cblocks in the region (actually index in rgn_bb_table). */ | |
550 | } | |
8c660648 JL |
551 | region; |
552 | ||
63de6c74 | 553 | /* Number of regions in the procedure. */ |
8c660648 JL |
554 | static int nr_regions; |
555 | ||
63de6c74 | 556 | /* Table of region descriptions. */ |
8c660648 JL |
557 | static region *rgn_table; |
558 | ||
63de6c74 | 559 | /* Array of lists of regions' blocks. */ |
8c660648 JL |
560 | static int *rgn_bb_table; |
561 | ||
562 | /* Topological order of blocks in the region (if b2 is reachable from | |
63de6c74 MH |
563 | b1, block_to_bb[b2] > block_to_bb[b1]). Note: A basic block is |
564 | always referred to by either block or b, while its topological | |
565 | order name (in the region) is refered to by bb. */ | |
8c660648 JL |
566 | static int *block_to_bb; |
567 | ||
568 | /* The number of the region containing a block. */ | |
569 | static int *containing_rgn; | |
570 | ||
571 | #define RGN_NR_BLOCKS(rgn) (rgn_table[rgn].rgn_nr_blocks) | |
572 | #define RGN_BLOCKS(rgn) (rgn_table[rgn].rgn_blocks) | |
573 | #define BLOCK_TO_BB(block) (block_to_bb[block]) | |
574 | #define CONTAINING_RGN(block) (containing_rgn[block]) | |
575 | ||
3fe41456 KG |
576 | void debug_regions PARAMS ((void)); |
577 | static void find_single_block_region PARAMS ((void)); | |
578 | static void find_rgns PARAMS ((struct edge_list *, sbitmap *)); | |
579 | static int too_large PARAMS ((int, int *, int *)); | |
8c660648 | 580 | |
3fe41456 | 581 | extern void debug_live PARAMS ((int, int)); |
8c660648 JL |
582 | |
583 | /* Blocks of the current region being scheduled. */ | |
584 | static int current_nr_blocks; | |
585 | static int current_blocks; | |
586 | ||
63de6c74 | 587 | /* The mapping from bb to block. */ |
8c660648 JL |
588 | #define BB_TO_BLOCK(bb) (rgn_bb_table[current_blocks + (bb)]) |
589 | ||
8c660648 JL |
590 | /* Bit vectors and bitset operations are needed for computations on |
591 | the control flow graph. */ | |
592 | ||
593 | typedef unsigned HOST_WIDE_INT *bitset; | |
594 | typedef struct | |
7a403706 KH |
595 | { |
596 | int *first_member; /* Pointer to the list start in bitlst_table. */ | |
597 | int nr_members; /* The number of members of the bit list. */ | |
598 | } | |
8c660648 JL |
599 | bitlst; |
600 | ||
61822835 JL |
601 | static int bitlst_table_last; |
602 | static int bitlst_table_size; | |
8c660648 JL |
603 | static int *bitlst_table; |
604 | ||
3fe41456 KG |
605 | static char bitset_member PARAMS ((bitset, int, int)); |
606 | static void extract_bitlst PARAMS ((bitset, int, int, bitlst *)); | |
8c660648 | 607 | |
63de6c74 | 608 | /* Target info declarations. |
8c660648 JL |
609 | |
610 | The block currently being scheduled is referred to as the "target" block, | |
611 | while other blocks in the region from which insns can be moved to the | |
612 | target are called "source" blocks. The candidate structure holds info | |
613 | about such sources: are they valid? Speculative? Etc. */ | |
614 | typedef bitlst bblst; | |
615 | typedef struct | |
7a403706 KH |
616 | { |
617 | char is_valid; | |
618 | char is_speculative; | |
619 | int src_prob; | |
620 | bblst split_bbs; | |
621 | bblst update_bbs; | |
622 | } | |
8c660648 JL |
623 | candidate; |
624 | ||
625 | static candidate *candidate_table; | |
626 | ||
627 | /* A speculative motion requires checking live information on the path | |
628 | from 'source' to 'target'. The split blocks are those to be checked. | |
629 | After a speculative motion, live information should be modified in | |
630 | the 'update' blocks. | |
631 | ||
63de6c74 MH |
632 | Lists of split and update blocks for each candidate of the current |
633 | target are in array bblst_table. */ | |
61822835 | 634 | static int *bblst_table, bblst_size, bblst_last; |
8c660648 JL |
635 | |
636 | #define IS_VALID(src) ( candidate_table[src].is_valid ) | |
637 | #define IS_SPECULATIVE(src) ( candidate_table[src].is_speculative ) | |
638 | #define SRC_PROB(src) ( candidate_table[src].src_prob ) | |
639 | ||
640 | /* The bb being currently scheduled. */ | |
61822835 | 641 | static int target_bb; |
8c660648 JL |
642 | |
643 | /* List of edges. */ | |
644 | typedef bitlst edgelst; | |
645 | ||
63de6c74 | 646 | /* Target info functions. */ |
3fe41456 KG |
647 | static void split_edges PARAMS ((int, int, edgelst *)); |
648 | static void compute_trg_info PARAMS ((int)); | |
649 | void debug_candidate PARAMS ((int)); | |
650 | void debug_candidates PARAMS ((int)); | |
8c660648 | 651 | |
8c660648 JL |
652 | /* Bit-set of bbs, where bit 'i' stands for bb 'i'. */ |
653 | typedef bitset bbset; | |
654 | ||
655 | /* Number of words of the bbset. */ | |
61822835 | 656 | static int bbset_size; |
8c660648 JL |
657 | |
658 | /* Dominators array: dom[i] contains the bbset of dominators of | |
659 | bb i in the region. */ | |
61822835 | 660 | static bbset *dom; |
8c660648 | 661 | |
63de6c74 | 662 | /* bb 0 is the only region entry. */ |
8c660648 JL |
663 | #define IS_RGN_ENTRY(bb) (!bb) |
664 | ||
665 | /* Is bb_src dominated by bb_trg. */ | |
666 | #define IS_DOMINATED(bb_src, bb_trg) \ | |
667 | ( bitset_member (dom[bb_src], bb_trg, bbset_size) ) | |
668 | ||
669 | /* Probability: Prob[i] is a float in [0, 1] which is the probability | |
670 | of bb i relative to the region entry. */ | |
61822835 | 671 | static float *prob; |
8c660648 | 672 | |
63de6c74 | 673 | /* The probability of bb_src, relative to bb_trg. Note, that while the |
8c660648 JL |
674 | 'prob[bb]' is a float in [0, 1], this macro returns an integer |
675 | in [0, 100]. */ | |
676 | #define GET_SRC_PROB(bb_src, bb_trg) ((int) (100.0 * (prob[bb_src] / \ | |
677 | prob[bb_trg]))) | |
678 | ||
679 | /* Bit-set of edges, where bit i stands for edge i. */ | |
680 | typedef bitset edgeset; | |
681 | ||
682 | /* Number of edges in the region. */ | |
61822835 | 683 | static int rgn_nr_edges; |
8c660648 | 684 | |
63de6c74 | 685 | /* Array of size rgn_nr_edges. */ |
61822835 | 686 | static int *rgn_edges; |
8c660648 | 687 | |
63de6c74 | 688 | /* Number of words in an edgeset. */ |
61822835 | 689 | static int edgeset_size; |
8c660648 | 690 | |
86133292 JL |
691 | /* Number of bits in an edgeset. */ |
692 | static int edgeset_bitsize; | |
693 | ||
8c660648 | 694 | /* Mapping from each edge in the graph to its number in the rgn. */ |
61822835 | 695 | static int *edge_to_bit; |
8c660648 JL |
696 | #define EDGE_TO_BIT(edge) (edge_to_bit[edge]) |
697 | ||
698 | /* The split edges of a source bb is different for each target | |
699 | bb. In order to compute this efficiently, the 'potential-split edges' | |
700 | are computed for each bb prior to scheduling a region. This is actually | |
701 | the split edges of each bb relative to the region entry. | |
702 | ||
703 | pot_split[bb] is the set of potential split edges of bb. */ | |
61822835 | 704 | static edgeset *pot_split; |
8c660648 JL |
705 | |
706 | /* For every bb, a set of its ancestor edges. */ | |
61822835 | 707 | static edgeset *ancestor_edges; |
8c660648 | 708 | |
3fe41456 | 709 | static void compute_dom_prob_ps PARAMS ((int)); |
8c660648 JL |
710 | |
711 | #define ABS_VALUE(x) (((x)<0)?(-(x)):(x)) | |
c88e8206 RH |
712 | #define INSN_PROBABILITY(INSN) (SRC_PROB (BLOCK_TO_BB (BLOCK_NUM (INSN)))) |
713 | #define IS_SPECULATIVE_INSN(INSN) (IS_SPECULATIVE (BLOCK_TO_BB (BLOCK_NUM (INSN)))) | |
714 | #define INSN_BB(INSN) (BLOCK_TO_BB (BLOCK_NUM (INSN))) | |
8c660648 | 715 | |
63de6c74 | 716 | /* Parameters affecting the decision of rank_for_schedule(). */ |
8c660648 JL |
717 | #define MIN_DIFF_PRIORITY 2 |
718 | #define MIN_PROBABILITY 40 | |
719 | #define MIN_PROB_DIFF 10 | |
720 | ||
63de6c74 | 721 | /* Speculative scheduling functions. */ |
3fe41456 KG |
722 | static int check_live_1 PARAMS ((int, rtx)); |
723 | static void update_live_1 PARAMS ((int, rtx)); | |
724 | static int check_live PARAMS ((rtx, int)); | |
725 | static void update_live PARAMS ((rtx, int)); | |
726 | static void set_spec_fed PARAMS ((rtx)); | |
727 | static int is_pfree PARAMS ((rtx, int, int)); | |
728 | static int find_conditional_protection PARAMS ((rtx, int)); | |
729 | static int is_conditionally_protected PARAMS ((rtx, int, int)); | |
730 | static int may_trap_exp PARAMS ((rtx, int)); | |
731 | static int haifa_classify_insn PARAMS ((rtx)); | |
732 | static int is_prisky PARAMS ((rtx, int, int)); | |
733 | static int is_exception_free PARAMS ((rtx, int, int)); | |
734 | ||
735 | static char find_insn_mem_list PARAMS ((rtx, rtx, rtx, rtx)); | |
736 | static void compute_block_forward_dependences PARAMS ((int)); | |
737 | static void add_branch_dependences PARAMS ((rtx, rtx)); | |
738 | static void compute_block_backward_dependences PARAMS ((int)); | |
739 | void debug_dependencies PARAMS ((void)); | |
8c660648 JL |
740 | |
741 | /* Notes handling mechanism: | |
742 | ========================= | |
743 | Generally, NOTES are saved before scheduling and restored after scheduling. | |
744 | The scheduler distinguishes between three types of notes: | |
745 | ||
746 | (1) LINE_NUMBER notes, generated and used for debugging. Here, | |
747 | before scheduling a region, a pointer to the LINE_NUMBER note is | |
748 | added to the insn following it (in save_line_notes()), and the note | |
749 | is removed (in rm_line_notes() and unlink_line_notes()). After | |
750 | scheduling the region, this pointer is used for regeneration of | |
751 | the LINE_NUMBER note (in restore_line_notes()). | |
752 | ||
753 | (2) LOOP_BEGIN, LOOP_END, SETJMP, EHREGION_BEG, EHREGION_END notes: | |
754 | Before scheduling a region, a pointer to the note is added to the insn | |
755 | that follows or precedes it. (This happens as part of the data dependence | |
756 | computation). After scheduling an insn, the pointer contained in it is | |
757 | used for regenerating the corresponding note (in reemit_notes). | |
758 | ||
759 | (3) All other notes (e.g. INSN_DELETED): Before scheduling a block, | |
760 | these notes are put in a list (in rm_other_notes() and | |
761 | unlink_other_notes ()). After scheduling the block, these notes are | |
762 | inserted at the beginning of the block (in schedule_block()). */ | |
763 | ||
3fe41456 KG |
764 | static rtx unlink_other_notes PARAMS ((rtx, rtx)); |
765 | static rtx unlink_line_notes PARAMS ((rtx, rtx)); | |
766 | static void rm_line_notes PARAMS ((int)); | |
767 | static void save_line_notes PARAMS ((int)); | |
768 | static void restore_line_notes PARAMS ((int)); | |
769 | static void rm_redundant_line_notes PARAMS ((void)); | |
770 | static void rm_other_notes PARAMS ((rtx, rtx)); | |
771 | static rtx reemit_notes PARAMS ((rtx, rtx)); | |
772 | ||
773 | static void get_block_head_tail PARAMS ((int, rtx *, rtx *)); | |
774 | static void get_bb_head_tail PARAMS ((int, rtx *, rtx *)); | |
775 | ||
7a403706 | 776 | static int queue_to_ready PARAMS ((rtx[], int)); |
3fe41456 KG |
777 | |
778 | static void debug_ready_list PARAMS ((rtx[], int)); | |
779 | static void init_target_units PARAMS ((void)); | |
780 | static void insn_print_units PARAMS ((rtx)); | |
781 | static int get_visual_tbl_length PARAMS ((void)); | |
782 | static void init_block_visualization PARAMS ((void)); | |
783 | static void print_block_visualization PARAMS ((int, const char *)); | |
784 | static void visualize_scheduled_insns PARAMS ((int, int)); | |
785 | static void visualize_no_unit PARAMS ((rtx)); | |
786 | static void visualize_stall_cycles PARAMS ((int, int)); | |
787 | static void print_exp PARAMS ((char *, rtx, int)); | |
788 | static void print_value PARAMS ((char *, rtx, int)); | |
789 | static void print_pattern PARAMS ((char *, rtx, int)); | |
790 | static void print_insn PARAMS ((char *, rtx, int)); | |
791 | void debug_reg_vector PARAMS ((regset)); | |
792 | ||
793 | static rtx move_insn1 PARAMS ((rtx, rtx)); | |
794 | static rtx move_insn PARAMS ((rtx, rtx)); | |
795 | static rtx group_leader PARAMS ((rtx)); | |
796 | static int set_priorities PARAMS ((int)); | |
797 | static void init_deps PARAMS ((struct deps *)); | |
798 | static void schedule_region PARAMS ((int)); | |
c6991660 | 799 | static void propagate_deps PARAMS ((int, struct deps *, int)); |
8c660648 JL |
800 | |
801 | #endif /* INSN_SCHEDULING */ | |
802 | \f | |
803 | #define SIZE_FOR_MODE(X) (GET_MODE_SIZE (GET_MODE (X))) | |
804 | ||
8c660648 JL |
805 | /* Add ELEM wrapped in an INSN_LIST with reg note kind DEP_TYPE to the |
806 | LOG_LINKS of INSN, if not already there. DEP_TYPE indicates the type | |
807 | of dependence that this link represents. */ | |
808 | ||
809 | static void | |
810 | add_dependence (insn, elem, dep_type) | |
811 | rtx insn; | |
812 | rtx elem; | |
813 | enum reg_note dep_type; | |
814 | { | |
815 | rtx link, next; | |
178b88b9 VM |
816 | int present_p; |
817 | enum reg_note present_dep_type; | |
8c660648 JL |
818 | |
819 | /* Don't depend an insn on itself. */ | |
820 | if (insn == elem) | |
821 | return; | |
822 | ||
342d9c89 JL |
823 | /* We can get a dependency on deleted insns due to optimizations in |
824 | the register allocation and reloading or due to splitting. Any | |
825 | such dependency is useless and can be ignored. */ | |
826 | if (GET_CODE (elem) == NOTE) | |
827 | return; | |
7a403706 | 828 | |
8c660648 JL |
829 | /* If elem is part of a sequence that must be scheduled together, then |
830 | make the dependence point to the last insn of the sequence. | |
831 | When HAVE_cc0, it is possible for NOTEs to exist between users and | |
832 | setters of the condition codes, so we must skip past notes here. | |
833 | Otherwise, NOTEs are impossible here. */ | |
ef384380 | 834 | next = next_nonnote_insn (elem); |
8c660648 JL |
835 | if (next && SCHED_GROUP_P (next) |
836 | && GET_CODE (next) != CODE_LABEL) | |
837 | { | |
838 | /* Notes will never intervene here though, so don't bother checking | |
839 | for them. */ | |
ef384380 | 840 | /* Hah! Wrong. */ |
8c660648 JL |
841 | /* We must reject CODE_LABELs, so that we don't get confused by one |
842 | that has LABEL_PRESERVE_P set, which is represented by the same | |
843 | bit in the rtl as SCHED_GROUP_P. A CODE_LABEL can never be | |
844 | SCHED_GROUP_P. */ | |
ef384380 RH |
845 | |
846 | rtx nnext; | |
847 | while ((nnext = next_nonnote_insn (next)) != NULL | |
848 | && SCHED_GROUP_P (nnext) | |
849 | && GET_CODE (nnext) != CODE_LABEL) | |
850 | next = nnext; | |
8c660648 JL |
851 | |
852 | /* Again, don't depend an insn on itself. */ | |
853 | if (insn == next) | |
854 | return; | |
855 | ||
856 | /* Make the dependence to NEXT, the last insn of the group, instead | |
857 | of the original ELEM. */ | |
858 | elem = next; | |
859 | } | |
860 | ||
178b88b9 | 861 | present_p = 1; |
8c660648 JL |
862 | #ifdef INSN_SCHEDULING |
863 | /* (This code is guarded by INSN_SCHEDULING, otherwise INSN_BB is undefined.) | |
864 | No need for interblock dependences with calls, since | |
865 | calls are not moved between blocks. Note: the edge where | |
866 | elem is a CALL is still required. */ | |
867 | if (GET_CODE (insn) == CALL_INSN | |
868 | && (INSN_BB (elem) != INSN_BB (insn))) | |
869 | return; | |
870 | ||
178b88b9 VM |
871 | /* If we already have a dependency for ELEM, then we do not need to |
872 | do anything. Avoiding the list walk below can cut compile times | |
873 | dramatically for some code. */ | |
874 | if (true_dependency_cache != NULL) | |
875 | { | |
876 | if (anti_dependency_cache == NULL || output_dependency_cache == NULL) | |
877 | abort (); | |
878 | if (TEST_BIT (true_dependency_cache[INSN_LUID (insn)], INSN_LUID (elem))) | |
879 | present_dep_type = 0; | |
880 | else if (TEST_BIT (anti_dependency_cache[INSN_LUID (insn)], | |
881 | INSN_LUID (elem))) | |
882 | present_dep_type = REG_DEP_ANTI; | |
883 | else if (TEST_BIT (output_dependency_cache[INSN_LUID (insn)], | |
884 | INSN_LUID (elem))) | |
885 | present_dep_type = REG_DEP_OUTPUT; | |
886 | else | |
887 | present_p = 0; | |
888 | if (present_p && (int) dep_type >= (int) present_dep_type) | |
889 | return; | |
890 | } | |
35c95c5a | 891 | #endif |
356edbd7 | 892 | |
8c660648 | 893 | /* Check that we don't already have this dependence. */ |
178b88b9 VM |
894 | if (present_p) |
895 | for (link = LOG_LINKS (insn); link; link = XEXP (link, 1)) | |
896 | if (XEXP (link, 0) == elem) | |
897 | { | |
898 | #ifdef INSN_SCHEDULING | |
899 | /* Clear corresponding cache entry because type of the link | |
900 | may be changed. */ | |
901 | if (true_dependency_cache != NULL) | |
902 | { | |
903 | if (REG_NOTE_KIND (link) == REG_DEP_ANTI) | |
904 | RESET_BIT (anti_dependency_cache[INSN_LUID (insn)], | |
905 | INSN_LUID (elem)); | |
906 | else if (REG_NOTE_KIND (link) == REG_DEP_OUTPUT | |
907 | && output_dependency_cache) | |
908 | RESET_BIT (output_dependency_cache[INSN_LUID (insn)], | |
909 | INSN_LUID (elem)); | |
910 | else | |
911 | abort (); | |
912 | } | |
913 | #endif | |
356edbd7 | 914 | |
178b88b9 VM |
915 | /* If this is a more restrictive type of dependence than the existing |
916 | one, then change the existing dependence to this type. */ | |
917 | if ((int) dep_type < (int) REG_NOTE_KIND (link)) | |
918 | PUT_REG_NOTE_KIND (link, dep_type); | |
919 | ||
35c95c5a | 920 | #ifdef INSN_SCHEDULING |
178b88b9 VM |
921 | /* If we are adding a dependency to INSN's LOG_LINKs, then |
922 | note that in the bitmap caches of dependency information. */ | |
923 | if (true_dependency_cache != NULL) | |
924 | { | |
925 | if ((int)REG_NOTE_KIND (link) == 0) | |
926 | SET_BIT (true_dependency_cache[INSN_LUID (insn)], | |
927 | INSN_LUID (elem)); | |
928 | else if (REG_NOTE_KIND (link) == REG_DEP_ANTI) | |
929 | SET_BIT (anti_dependency_cache[INSN_LUID (insn)], | |
930 | INSN_LUID (elem)); | |
931 | else if (REG_NOTE_KIND (link) == REG_DEP_OUTPUT) | |
932 | SET_BIT (output_dependency_cache[INSN_LUID (insn)], | |
933 | INSN_LUID (elem)); | |
934 | } | |
35c95c5a | 935 | #endif |
178b88b9 | 936 | return; |
8c660648 JL |
937 | } |
938 | /* Might want to check one level of transitivity to save conses. */ | |
939 | ||
ebb7b10b RH |
940 | link = alloc_INSN_LIST (elem, LOG_LINKS (insn)); |
941 | LOG_LINKS (insn) = link; | |
942 | ||
8c660648 JL |
943 | /* Insn dependency, not data dependency. */ |
944 | PUT_REG_NOTE_KIND (link, dep_type); | |
4525e228 JL |
945 | |
946 | #ifdef INSN_SCHEDULING | |
178b88b9 VM |
947 | /* If we are adding a dependency to INSN's LOG_LINKs, then note that |
948 | in the bitmap caches of dependency information. */ | |
949 | if (true_dependency_cache != NULL) | |
950 | { | |
951 | if ((int)dep_type == 0) | |
952 | SET_BIT (true_dependency_cache[INSN_LUID (insn)], INSN_LUID (elem)); | |
953 | else if (dep_type == REG_DEP_ANTI) | |
954 | SET_BIT (anti_dependency_cache[INSN_LUID (insn)], INSN_LUID (elem)); | |
955 | else if (dep_type == REG_DEP_OUTPUT) | |
956 | SET_BIT (output_dependency_cache[INSN_LUID (insn)], INSN_LUID (elem)); | |
957 | } | |
4525e228 | 958 | #endif |
8c660648 JL |
959 | } |
960 | ||
961 | /* Remove ELEM wrapped in an INSN_LIST from the LOG_LINKS | |
962 | of INSN. Abort if not found. */ | |
963 | ||
964 | static void | |
965 | remove_dependence (insn, elem) | |
966 | rtx insn; | |
967 | rtx elem; | |
968 | { | |
ebb7b10b | 969 | rtx prev, link, next; |
8c660648 JL |
970 | int found = 0; |
971 | ||
ebb7b10b | 972 | for (prev = 0, link = LOG_LINKS (insn); link; link = next) |
8c660648 | 973 | { |
ebb7b10b | 974 | next = XEXP (link, 1); |
8c660648 JL |
975 | if (XEXP (link, 0) == elem) |
976 | { | |
977 | if (prev) | |
ebb7b10b | 978 | XEXP (prev, 1) = next; |
8c660648 | 979 | else |
ebb7b10b | 980 | LOG_LINKS (insn) = next; |
356edbd7 | 981 | |
35c95c5a | 982 | #ifdef INSN_SCHEDULING |
178b88b9 | 983 | /* If we are removing a dependency from the LOG_LINKS list, |
356edbd7 | 984 | make sure to remove it from the cache too. */ |
178b88b9 VM |
985 | if (true_dependency_cache != NULL) |
986 | { | |
987 | if (REG_NOTE_KIND (link) == 0) | |
988 | RESET_BIT (true_dependency_cache[INSN_LUID (insn)], | |
989 | INSN_LUID (elem)); | |
990 | else if (REG_NOTE_KIND (link) == REG_DEP_ANTI) | |
991 | RESET_BIT (anti_dependency_cache[INSN_LUID (insn)], | |
992 | INSN_LUID (elem)); | |
993 | else if (REG_NOTE_KIND (link) == REG_DEP_OUTPUT) | |
994 | RESET_BIT (output_dependency_cache[INSN_LUID (insn)], | |
995 | INSN_LUID (elem)); | |
996 | } | |
35c95c5a | 997 | #endif |
356edbd7 | 998 | |
5a4f6418 | 999 | free_INSN_LIST_node (link); |
ebb7b10b | 1000 | |
8c660648 JL |
1001 | found = 1; |
1002 | } | |
6d8ccdbb JL |
1003 | else |
1004 | prev = link; | |
8c660648 JL |
1005 | } |
1006 | ||
1007 | if (!found) | |
1008 | abort (); | |
1009 | return; | |
1010 | } | |
ef384380 RH |
1011 | |
1012 | /* Return the INSN_LIST containing INSN in LIST, or NULL | |
1013 | if LIST does not contain INSN. */ | |
1014 | ||
1015 | static inline rtx | |
1016 | find_insn_list (insn, list) | |
1017 | rtx insn; | |
1018 | rtx list; | |
1019 | { | |
1020 | while (list) | |
1021 | { | |
1022 | if (XEXP (list, 0) == insn) | |
1023 | return list; | |
1024 | list = XEXP (list, 1); | |
1025 | } | |
1026 | return 0; | |
1027 | } | |
1028 | ||
1029 | /* Set SCHED_GROUP_P and care for the rest of the bookkeeping that | |
1030 | goes along with that. */ | |
1031 | ||
1032 | static void | |
1033 | set_sched_group_p (insn) | |
1034 | rtx insn; | |
1035 | { | |
1036 | rtx link, prev; | |
1037 | ||
1038 | SCHED_GROUP_P (insn) = 1; | |
1039 | ||
1040 | /* There may be a note before this insn now, but all notes will | |
1041 | be removed before we actually try to schedule the insns, so | |
1042 | it won't cause a problem later. We must avoid it here though. */ | |
1043 | prev = prev_nonnote_insn (insn); | |
1044 | ||
1045 | /* Make a copy of all dependencies on the immediately previous insn, | |
1046 | and add to this insn. This is so that all the dependencies will | |
1047 | apply to the group. Remove an explicit dependence on this insn | |
1048 | as SCHED_GROUP_P now represents it. */ | |
1049 | ||
1050 | if (find_insn_list (prev, LOG_LINKS (insn))) | |
1051 | remove_dependence (insn, prev); | |
1052 | ||
1053 | for (link = LOG_LINKS (prev); link; link = XEXP (link, 1)) | |
1054 | add_dependence (insn, XEXP (link, 0), REG_NOTE_KIND (link)); | |
1055 | } | |
8c660648 JL |
1056 | \f |
1057 | #ifndef INSN_SCHEDULING | |
1058 | void | |
1059 | schedule_insns (dump_file) | |
7bdb32b9 | 1060 | FILE *dump_file ATTRIBUTE_UNUSED; |
8c660648 JL |
1061 | { |
1062 | } | |
1063 | #else | |
1064 | #ifndef __GNUC__ | |
1065 | #define __inline | |
1066 | #endif | |
1067 | ||
cbb13457 MM |
1068 | #ifndef HAIFA_INLINE |
1069 | #define HAIFA_INLINE __inline | |
1070 | #endif | |
1071 | ||
8c660648 JL |
1072 | /* Computation of memory dependencies. */ |
1073 | ||
e1306f49 BS |
1074 | /* Data structures for the computation of data dependences in a regions. We |
1075 | keep one mem_deps structure for every basic block. Before analyzing the | |
1076 | data dependences for a bb, its variables are initialized as a function of | |
1077 | the variables of its predecessors. When the analysis for a bb completes, | |
1078 | we save the contents to the corresponding bb_mem_deps[bb] variable. */ | |
8c660648 | 1079 | |
e1306f49 | 1080 | static struct deps *bb_deps; |
8c660648 JL |
1081 | |
1082 | /* Pointer to the last instruction scheduled. Used by rank_for_schedule, | |
1083 | so that insns independent of the last scheduled insn will be preferred | |
1084 | over dependent instructions. */ | |
1085 | ||
1086 | static rtx last_scheduled_insn; | |
1087 | ||
63de6c74 | 1088 | /* Functions for construction of the control flow graph. */ |
8c660648 JL |
1089 | |
1090 | /* Return 1 if control flow graph should not be constructed, 0 otherwise. | |
168cbdf9 | 1091 | |
8c660648 | 1092 | We decide not to build the control flow graph if there is possibly more |
168cbdf9 JL |
1093 | than one entry to the function, if computed branches exist, of if we |
1094 | have nonlocal gotos. */ | |
8c660648 | 1095 | |
168cbdf9 | 1096 | static int |
8c660648 JL |
1097 | is_cfg_nonregular () |
1098 | { | |
1099 | int b; | |
1100 | rtx insn; | |
1101 | RTX_CODE code; | |
1102 | ||
168cbdf9 JL |
1103 | /* If we have a label that could be the target of a nonlocal goto, then |
1104 | the cfg is not well structured. */ | |
e881bb1b | 1105 | if (nonlocal_goto_handler_labels) |
168cbdf9 | 1106 | return 1; |
8c660648 | 1107 | |
168cbdf9 | 1108 | /* If we have any forced labels, then the cfg is not well structured. */ |
8c660648 | 1109 | if (forced_labels) |
168cbdf9 | 1110 | return 1; |
8c660648 | 1111 | |
4d1d8045 BS |
1112 | /* If this function has a computed jump, then we consider the cfg |
1113 | not well structured. */ | |
1114 | if (current_function_has_computed_jump) | |
1115 | return 1; | |
1116 | ||
168cbdf9 JL |
1117 | /* If we have exception handlers, then we consider the cfg not well |
1118 | structured. ?!? We should be able to handle this now that flow.c | |
1119 | computes an accurate cfg for EH. */ | |
8c660648 | 1120 | if (exception_handler_labels) |
168cbdf9 | 1121 | return 1; |
8c660648 | 1122 | |
168cbdf9 JL |
1123 | /* If we have non-jumping insns which refer to labels, then we consider |
1124 | the cfg not well structured. */ | |
63de6c74 | 1125 | /* Check for labels referred to other thn by jumps. */ |
8c660648 | 1126 | for (b = 0; b < n_basic_blocks; b++) |
3b413743 | 1127 | for (insn = BLOCK_HEAD (b);; insn = NEXT_INSN (insn)) |
8c660648 JL |
1128 | { |
1129 | code = GET_CODE (insn); | |
1130 | if (GET_RTX_CLASS (code) == 'i') | |
1131 | { | |
1132 | rtx note; | |
1133 | ||
1134 | for (note = REG_NOTES (insn); note; note = XEXP (note, 1)) | |
1135 | if (REG_NOTE_KIND (note) == REG_LABEL) | |
168cbdf9 | 1136 | return 1; |
8c660648 JL |
1137 | } |
1138 | ||
3b413743 | 1139 | if (insn == BLOCK_END (b)) |
8c660648 JL |
1140 | break; |
1141 | } | |
1142 | ||
168cbdf9 | 1143 | /* All the tests passed. Consider the cfg well structured. */ |
8c660648 JL |
1144 | return 0; |
1145 | } | |
1146 | ||
5ece9746 JL |
1147 | /* Build the control flow graph and set nr_edges. |
1148 | ||
1149 | Instead of trying to build a cfg ourselves, we rely on flow to | |
168cbdf9 | 1150 | do it for us. Stamp out useless code (and bug) duplication. |
8c660648 | 1151 | |
168cbdf9 JL |
1152 | Return nonzero if an irregularity in the cfg is found which would |
1153 | prevent cross block scheduling. */ | |
1154 | ||
1155 | static int | |
6b8cf0c5 JL |
1156 | build_control_flow (edge_list) |
1157 | struct edge_list *edge_list; | |
8c660648 | 1158 | { |
6b8cf0c5 | 1159 | int i, unreachable, num_edges; |
5ece9746 | 1160 | |
6b8cf0c5 JL |
1161 | /* This already accounts for entry/exit edges. */ |
1162 | num_edges = NUM_EDGES (edge_list); | |
1163 | ||
1164 | /* Unreachable loops with more than one basic block are detected | |
1165 | during the DFS traversal in find_rgns. | |
1166 | ||
1167 | Unreachable loops with a single block are detected here. This | |
1168 | test is redundant with the one in find_rgns, but it's much | |
1169 | cheaper to go ahead and catch the trivial case here. */ | |
168cbdf9 JL |
1170 | unreachable = 0; |
1171 | for (i = 0; i < n_basic_blocks; i++) | |
1172 | { | |
6b8cf0c5 | 1173 | basic_block b = BASIC_BLOCK (i); |
15ebe47d | 1174 | |
6b8cf0c5 | 1175 | if (b->pred == NULL |
7f103e88 | 1176 | || (b->pred->src == b |
6b8cf0c5 | 1177 | && b->pred->pred_next == NULL)) |
168cbdf9 JL |
1178 | unreachable = 1; |
1179 | } | |
1180 | ||
6b8cf0c5 | 1181 | /* ??? We can kill these soon. */ |
3de90026 RH |
1182 | in_edges = (int *) xcalloc (n_basic_blocks, sizeof (int)); |
1183 | out_edges = (int *) xcalloc (n_basic_blocks, sizeof (int)); | |
6b8cf0c5 | 1184 | edge_table = (haifa_edge *) xcalloc (num_edges, sizeof (haifa_edge)); |
168cbdf9 | 1185 | |
8c660648 | 1186 | nr_edges = 0; |
6b8cf0c5 JL |
1187 | for (i = 0; i < num_edges; i++) |
1188 | { | |
1189 | edge e = INDEX_EDGE (edge_list, i); | |
1190 | ||
1191 | if (e->dest != EXIT_BLOCK_PTR | |
1192 | && e->src != ENTRY_BLOCK_PTR) | |
1193 | new_edge (e->src->index, e->dest->index); | |
1194 | } | |
8c660648 | 1195 | |
63de6c74 | 1196 | /* Increment by 1, since edge 0 is unused. */ |
8c660648 JL |
1197 | nr_edges++; |
1198 | ||
168cbdf9 | 1199 | return unreachable; |
8c660648 JL |
1200 | } |
1201 | ||
5ece9746 | 1202 | /* Record an edge in the control flow graph from SOURCE to TARGET. |
8c660648 | 1203 | |
5ece9746 JL |
1204 | In theory, this is redundant with the s_succs computed above, but |
1205 | we have not converted all of haifa to use information from the | |
1206 | integer lists. */ | |
8c660648 JL |
1207 | |
1208 | static void | |
1209 | new_edge (source, target) | |
1210 | int source, target; | |
1211 | { | |
1212 | int e, next_edge; | |
1213 | int curr_edge, fst_edge; | |
1214 | ||
63de6c74 | 1215 | /* Check for duplicates. */ |
8c660648 JL |
1216 | fst_edge = curr_edge = OUT_EDGES (source); |
1217 | while (curr_edge) | |
1218 | { | |
1219 | if (FROM_BLOCK (curr_edge) == source | |
1220 | && TO_BLOCK (curr_edge) == target) | |
1221 | { | |
1222 | return; | |
1223 | } | |
1224 | ||
1225 | curr_edge = NEXT_OUT (curr_edge); | |
1226 | ||
1227 | if (fst_edge == curr_edge) | |
1228 | break; | |
1229 | } | |
1230 | ||
1231 | e = ++nr_edges; | |
1232 | ||
1233 | FROM_BLOCK (e) = source; | |
1234 | TO_BLOCK (e) = target; | |
1235 | ||
1236 | if (OUT_EDGES (source)) | |
1237 | { | |
1238 | next_edge = NEXT_OUT (OUT_EDGES (source)); | |
1239 | NEXT_OUT (OUT_EDGES (source)) = e; | |
1240 | NEXT_OUT (e) = next_edge; | |
1241 | } | |
1242 | else | |
1243 | { | |
1244 | OUT_EDGES (source) = e; | |
1245 | NEXT_OUT (e) = e; | |
1246 | } | |
1247 | ||
1248 | if (IN_EDGES (target)) | |
1249 | { | |
1250 | next_edge = NEXT_IN (IN_EDGES (target)); | |
1251 | NEXT_IN (IN_EDGES (target)) = e; | |
1252 | NEXT_IN (e) = next_edge; | |
1253 | } | |
1254 | else | |
1255 | { | |
1256 | IN_EDGES (target) = e; | |
1257 | NEXT_IN (e) = e; | |
1258 | } | |
1259 | } | |
1260 | ||
8c660648 JL |
1261 | /* BITSET macros for operations on the control flow graph. */ |
1262 | ||
63de6c74 | 1263 | /* Compute bitwise union of two bitsets. */ |
8c660648 JL |
1264 | #define BITSET_UNION(set1, set2, len) \ |
1265 | do { register bitset tp = set1, sp = set2; \ | |
1266 | register int i; \ | |
1267 | for (i = 0; i < len; i++) \ | |
1268 | *(tp++) |= *(sp++); } while (0) | |
1269 | ||
63de6c74 | 1270 | /* Compute bitwise intersection of two bitsets. */ |
8c660648 JL |
1271 | #define BITSET_INTER(set1, set2, len) \ |
1272 | do { register bitset tp = set1, sp = set2; \ | |
1273 | register int i; \ | |
1274 | for (i = 0; i < len; i++) \ | |
1275 | *(tp++) &= *(sp++); } while (0) | |
1276 | ||
63de6c74 | 1277 | /* Compute bitwise difference of two bitsets. */ |
8c660648 JL |
1278 | #define BITSET_DIFFER(set1, set2, len) \ |
1279 | do { register bitset tp = set1, sp = set2; \ | |
1280 | register int i; \ | |
1281 | for (i = 0; i < len; i++) \ | |
1282 | *(tp++) &= ~*(sp++); } while (0) | |
1283 | ||
63de6c74 | 1284 | /* Inverts every bit of bitset 'set'. */ |
8c660648 JL |
1285 | #define BITSET_INVERT(set, len) \ |
1286 | do { register bitset tmpset = set; \ | |
1287 | register int i; \ | |
1288 | for (i = 0; i < len; i++, tmpset++) \ | |
1289 | *tmpset = ~*tmpset; } while (0) | |
1290 | ||
1291 | /* Turn on the index'th bit in bitset set. */ | |
1292 | #define BITSET_ADD(set, index, len) \ | |
1293 | { \ | |
1294 | if (index >= HOST_BITS_PER_WIDE_INT * len) \ | |
1295 | abort (); \ | |
1296 | else \ | |
1297 | set[index/HOST_BITS_PER_WIDE_INT] |= \ | |
1298 | 1 << (index % HOST_BITS_PER_WIDE_INT); \ | |
1299 | } | |
1300 | ||
1301 | /* Turn off the index'th bit in set. */ | |
1302 | #define BITSET_REMOVE(set, index, len) \ | |
1303 | { \ | |
1304 | if (index >= HOST_BITS_PER_WIDE_INT * len) \ | |
1305 | abort (); \ | |
1306 | else \ | |
1307 | set[index/HOST_BITS_PER_WIDE_INT] &= \ | |
1308 | ~(1 << (index%HOST_BITS_PER_WIDE_INT)); \ | |
1309 | } | |
1310 | ||
63de6c74 | 1311 | /* Check if the index'th bit in bitset set is on. */ |
8c660648 JL |
1312 | |
1313 | static char | |
1314 | bitset_member (set, index, len) | |
1315 | bitset set; | |
1316 | int index, len; | |
1317 | { | |
1318 | if (index >= HOST_BITS_PER_WIDE_INT * len) | |
1319 | abort (); | |
1320 | return (set[index / HOST_BITS_PER_WIDE_INT] & | |
1321 | 1 << (index % HOST_BITS_PER_WIDE_INT)) ? 1 : 0; | |
1322 | } | |
1323 | ||
8c660648 JL |
1324 | /* Translate a bit-set SET to a list BL of the bit-set members. */ |
1325 | ||
1326 | static void | |
86133292 | 1327 | extract_bitlst (set, len, bitlen, bl) |
8c660648 JL |
1328 | bitset set; |
1329 | int len; | |
394c46fe | 1330 | int bitlen; |
8c660648 JL |
1331 | bitlst *bl; |
1332 | { | |
1333 | int i, j, offset; | |
1334 | unsigned HOST_WIDE_INT word; | |
1335 | ||
63de6c74 | 1336 | /* bblst table space is reused in each call to extract_bitlst. */ |
8c660648 JL |
1337 | bitlst_table_last = 0; |
1338 | ||
1339 | bl->first_member = &bitlst_table[bitlst_table_last]; | |
1340 | bl->nr_members = 0; | |
1341 | ||
86133292 | 1342 | /* Iterate over each word in the bitset. */ |
8c660648 JL |
1343 | for (i = 0; i < len; i++) |
1344 | { | |
1345 | word = set[i]; | |
1346 | offset = i * HOST_BITS_PER_WIDE_INT; | |
86133292 JL |
1347 | |
1348 | /* Iterate over each bit in the word, but do not | |
1349 | go beyond the end of the defined bits. */ | |
1350 | for (j = 0; offset < bitlen && word; j++) | |
8c660648 JL |
1351 | { |
1352 | if (word & 1) | |
1353 | { | |
1354 | bitlst_table[bitlst_table_last++] = offset; | |
1355 | (bl->nr_members)++; | |
1356 | } | |
1357 | word >>= 1; | |
1358 | ++offset; | |
1359 | } | |
1360 | } | |
1361 | ||
1362 | } | |
1363 | ||
63de6c74 | 1364 | /* Functions for the construction of regions. */ |
8c660648 JL |
1365 | |
1366 | /* Print the regions, for debugging purposes. Callable from debugger. */ | |
1367 | ||
1368 | void | |
1369 | debug_regions () | |
1370 | { | |
1371 | int rgn, bb; | |
1372 | ||
1373 | fprintf (dump, "\n;; ------------ REGIONS ----------\n\n"); | |
1374 | for (rgn = 0; rgn < nr_regions; rgn++) | |
1375 | { | |
1376 | fprintf (dump, ";;\trgn %d nr_blocks %d:\n", rgn, | |
1377 | rgn_table[rgn].rgn_nr_blocks); | |
1378 | fprintf (dump, ";;\tbb/block: "); | |
1379 | ||
1380 | for (bb = 0; bb < rgn_table[rgn].rgn_nr_blocks; bb++) | |
1381 | { | |
1382 | current_blocks = RGN_BLOCKS (rgn); | |
1383 | ||
1384 | if (bb != BLOCK_TO_BB (BB_TO_BLOCK (bb))) | |
1385 | abort (); | |
1386 | ||
1387 | fprintf (dump, " %d/%d ", bb, BB_TO_BLOCK (bb)); | |
1388 | } | |
1389 | ||
1390 | fprintf (dump, "\n\n"); | |
1391 | } | |
1392 | } | |
1393 | ||
8c660648 JL |
1394 | /* Build a single block region for each basic block in the function. |
1395 | This allows for using the same code for interblock and basic block | |
1396 | scheduling. */ | |
1397 | ||
1398 | static void | |
1399 | find_single_block_region () | |
1400 | { | |
1401 | int i; | |
1402 | ||
1403 | for (i = 0; i < n_basic_blocks; i++) | |
1404 | { | |
1405 | rgn_bb_table[i] = i; | |
1406 | RGN_NR_BLOCKS (i) = 1; | |
1407 | RGN_BLOCKS (i) = i; | |
1408 | CONTAINING_RGN (i) = i; | |
1409 | BLOCK_TO_BB (i) = 0; | |
1410 | } | |
1411 | nr_regions = n_basic_blocks; | |
1412 | } | |
1413 | ||
8c660648 JL |
1414 | /* Update number of blocks and the estimate for number of insns |
1415 | in the region. Return 1 if the region is "too large" for interblock | |
1416 | scheduling (compile time considerations), otherwise return 0. */ | |
1417 | ||
1418 | static int | |
1419 | too_large (block, num_bbs, num_insns) | |
1420 | int block, *num_bbs, *num_insns; | |
1421 | { | |
1422 | (*num_bbs)++; | |
3b413743 RH |
1423 | (*num_insns) += (INSN_LUID (BLOCK_END (block)) - |
1424 | INSN_LUID (BLOCK_HEAD (block))); | |
cc132865 | 1425 | if ((*num_bbs > MAX_RGN_BLOCKS) || (*num_insns > MAX_RGN_INSNS)) |
8c660648 JL |
1426 | return 1; |
1427 | else | |
1428 | return 0; | |
1429 | } | |
1430 | ||
8c660648 JL |
1431 | /* Update_loop_relations(blk, hdr): Check if the loop headed by max_hdr[blk] |
1432 | is still an inner loop. Put in max_hdr[blk] the header of the most inner | |
1433 | loop containing blk. */ | |
1434 | #define UPDATE_LOOP_RELATIONS(blk, hdr) \ | |
1435 | { \ | |
1436 | if (max_hdr[blk] == -1) \ | |
1437 | max_hdr[blk] = hdr; \ | |
1438 | else if (dfs_nr[max_hdr[blk]] > dfs_nr[hdr]) \ | |
a2e68776 | 1439 | RESET_BIT (inner, hdr); \ |
8c660648 JL |
1440 | else if (dfs_nr[max_hdr[blk]] < dfs_nr[hdr]) \ |
1441 | { \ | |
a2e68776 | 1442 | RESET_BIT (inner,max_hdr[blk]); \ |
8c660648 JL |
1443 | max_hdr[blk] = hdr; \ |
1444 | } \ | |
1445 | } | |
1446 | ||
a2e68776 JL |
1447 | /* Find regions for interblock scheduling. |
1448 | ||
1449 | A region for scheduling can be: | |
1450 | ||
1451 | * A loop-free procedure, or | |
1452 | ||
1453 | * A reducible inner loop, or | |
1454 | ||
1455 | * A basic block not contained in any other region. | |
1456 | ||
a2e68776 JL |
1457 | ?!? In theory we could build other regions based on extended basic |
1458 | blocks or reverse extended basic blocks. Is it worth the trouble? | |
1459 | ||
1460 | Loop blocks that form a region are put into the region's block list | |
1461 | in topological order. | |
1462 | ||
1463 | This procedure stores its results into the following global (ick) variables | |
1464 | ||
1465 | * rgn_nr | |
1466 | * rgn_table | |
1467 | * rgn_bb_table | |
1468 | * block_to_bb | |
1469 | * containing region | |
1470 | ||
a2e68776 JL |
1471 | We use dominator relationships to avoid making regions out of non-reducible |
1472 | loops. | |
8c660648 | 1473 | |
a2e68776 JL |
1474 | This procedure needs to be converted to work on pred/succ lists instead |
1475 | of edge tables. That would simplify it somewhat. */ | |
8c660648 JL |
1476 | |
1477 | static void | |
6b8cf0c5 JL |
1478 | find_rgns (edge_list, dom) |
1479 | struct edge_list *edge_list; | |
a2e68776 | 1480 | sbitmap *dom; |
8c660648 | 1481 | { |
98903742 | 1482 | int *max_hdr, *dfs_nr, *stack, *degree; |
a2e68776 | 1483 | char no_loops = 1; |
487a6e06 | 1484 | int node, child, loop_head, i, head, tail; |
8c660648 | 1485 | int count = 0, sp, idx = 0, current_edge = out_edges[0]; |
15ebe47d | 1486 | int num_bbs, num_insns, unreachable; |
8c660648 | 1487 | int too_large_failure; |
8c660648 | 1488 | |
a2e68776 JL |
1489 | /* Note if an edge has been passed. */ |
1490 | sbitmap passed; | |
1491 | ||
1492 | /* Note if a block is a natural loop header. */ | |
1493 | sbitmap header; | |
1494 | ||
1495 | /* Note if a block is an natural inner loop header. */ | |
1496 | sbitmap inner; | |
1497 | ||
7a403706 | 1498 | /* Note if a block is in the block queue. */ |
a2e68776 JL |
1499 | sbitmap in_queue; |
1500 | ||
7a403706 | 1501 | /* Note if a block is in the block queue. */ |
cc132865 JL |
1502 | sbitmap in_stack; |
1503 | ||
6b8cf0c5 JL |
1504 | int num_edges = NUM_EDGES (edge_list); |
1505 | ||
a2e68776 JL |
1506 | /* Perform a DFS traversal of the cfg. Identify loop headers, inner loops |
1507 | and a mapping from block to its loop header (if the block is contained | |
1508 | in a loop, else -1). | |
1509 | ||
1510 | Store results in HEADER, INNER, and MAX_HDR respectively, these will | |
1511 | be used as inputs to the second traversal. | |
1512 | ||
1513 | STACK, SP and DFS_NR are only used during the first traversal. */ | |
1514 | ||
1515 | /* Allocate and initialize variables for the first traversal. */ | |
98903742 MM |
1516 | max_hdr = (int *) xmalloc (n_basic_blocks * sizeof (int)); |
1517 | dfs_nr = (int *) xcalloc (n_basic_blocks, sizeof (int)); | |
1518 | stack = (int *) xmalloc (nr_edges * sizeof (int)); | |
8c660648 | 1519 | |
a2e68776 JL |
1520 | inner = sbitmap_alloc (n_basic_blocks); |
1521 | sbitmap_ones (inner); | |
1522 | ||
1523 | header = sbitmap_alloc (n_basic_blocks); | |
1524 | sbitmap_zero (header); | |
8c660648 | 1525 | |
a2e68776 JL |
1526 | passed = sbitmap_alloc (nr_edges); |
1527 | sbitmap_zero (passed); | |
1528 | ||
1529 | in_queue = sbitmap_alloc (n_basic_blocks); | |
1530 | sbitmap_zero (in_queue); | |
8c660648 | 1531 | |
cc132865 JL |
1532 | in_stack = sbitmap_alloc (n_basic_blocks); |
1533 | sbitmap_zero (in_stack); | |
1534 | ||
8c660648 | 1535 | for (i = 0; i < n_basic_blocks; i++) |
a2e68776 | 1536 | max_hdr[i] = -1; |
8c660648 | 1537 | |
a2e68776 | 1538 | /* DFS traversal to find inner loops in the cfg. */ |
8c660648 | 1539 | |
8c660648 JL |
1540 | sp = -1; |
1541 | while (1) | |
1542 | { | |
a2e68776 | 1543 | if (current_edge == 0 || TEST_BIT (passed, current_edge)) |
8c660648 | 1544 | { |
a2e68776 | 1545 | /* We have reached a leaf node or a node that was already |
cc132865 | 1546 | processed. Pop edges off the stack until we find |
a2e68776 JL |
1547 | an edge that has not yet been processed. */ |
1548 | while (sp >= 0 | |
1549 | && (current_edge == 0 || TEST_BIT (passed, current_edge))) | |
8c660648 | 1550 | { |
a2e68776 | 1551 | /* Pop entry off the stack. */ |
8c660648 JL |
1552 | current_edge = stack[sp--]; |
1553 | node = FROM_BLOCK (current_edge); | |
1554 | child = TO_BLOCK (current_edge); | |
cc132865 JL |
1555 | RESET_BIT (in_stack, child); |
1556 | if (max_hdr[child] >= 0 && TEST_BIT (in_stack, max_hdr[child])) | |
8c660648 JL |
1557 | UPDATE_LOOP_RELATIONS (node, max_hdr[child]); |
1558 | current_edge = NEXT_OUT (current_edge); | |
1559 | } | |
1560 | ||
a2e68776 JL |
1561 | /* See if have finished the DFS tree traversal. */ |
1562 | if (sp < 0 && TEST_BIT (passed, current_edge)) | |
8c660648 | 1563 | break; |
a2e68776 JL |
1564 | |
1565 | /* Nope, continue the traversal with the popped node. */ | |
8c660648 JL |
1566 | continue; |
1567 | } | |
1568 | ||
a2e68776 | 1569 | /* Process a node. */ |
8c660648 | 1570 | node = FROM_BLOCK (current_edge); |
8c660648 | 1571 | child = TO_BLOCK (current_edge); |
cc132865 | 1572 | SET_BIT (in_stack, node); |
a2e68776 | 1573 | dfs_nr[node] = ++count; |
8c660648 | 1574 | |
cc132865 JL |
1575 | /* If the successor is in the stack, then we've found a loop. |
1576 | Mark the loop, if it is not a natural loop, then it will | |
1577 | be rejected during the second traversal. */ | |
1578 | if (TEST_BIT (in_stack, child)) | |
8c660648 JL |
1579 | { |
1580 | no_loops = 0; | |
a2e68776 | 1581 | SET_BIT (header, child); |
8c660648 | 1582 | UPDATE_LOOP_RELATIONS (node, child); |
a2e68776 | 1583 | SET_BIT (passed, current_edge); |
8c660648 JL |
1584 | current_edge = NEXT_OUT (current_edge); |
1585 | continue; | |
1586 | } | |
1587 | ||
a2e68776 JL |
1588 | /* If the child was already visited, then there is no need to visit |
1589 | it again. Just update the loop relationships and restart | |
1590 | with a new edge. */ | |
8c660648 JL |
1591 | if (dfs_nr[child]) |
1592 | { | |
cc132865 | 1593 | if (max_hdr[child] >= 0 && TEST_BIT (in_stack, max_hdr[child])) |
8c660648 | 1594 | UPDATE_LOOP_RELATIONS (node, max_hdr[child]); |
a2e68776 | 1595 | SET_BIT (passed, current_edge); |
8c660648 JL |
1596 | current_edge = NEXT_OUT (current_edge); |
1597 | continue; | |
1598 | } | |
1599 | ||
a2e68776 | 1600 | /* Push an entry on the stack and continue DFS traversal. */ |
8c660648 | 1601 | stack[++sp] = current_edge; |
a2e68776 | 1602 | SET_BIT (passed, current_edge); |
8c660648 | 1603 | current_edge = OUT_EDGES (child); |
50f71e6f JL |
1604 | |
1605 | /* This is temporary until haifa is converted to use rth's new | |
1606 | cfg routines which have true entry/exit blocks and the | |
1607 | appropriate edges from/to those blocks. | |
1608 | ||
1609 | Generally we update dfs_nr for a node when we process its | |
1610 | out edge. However, if the node has no out edge then we will | |
1611 | not set dfs_nr for that node. This can confuse the scheduler | |
1612 | into thinking that we have unreachable blocks, which in turn | |
7a403706 | 1613 | disables cross block scheduling. |
50f71e6f JL |
1614 | |
1615 | So, if we have a node with no out edges, go ahead and mark it | |
1616 | as reachable now. */ | |
1617 | if (current_edge == 0) | |
1618 | dfs_nr[child] = ++count; | |
a2e68776 | 1619 | } |
8c660648 | 1620 | |
15ebe47d JL |
1621 | /* Another check for unreachable blocks. The earlier test in |
1622 | is_cfg_nonregular only finds unreachable blocks that do not | |
1623 | form a loop. | |
a2e68776 | 1624 | |
15ebe47d JL |
1625 | The DFS traversal will mark every block that is reachable from |
1626 | the entry node by placing a nonzero value in dfs_nr. Thus if | |
1627 | dfs_nr is zero for any block, then it must be unreachable. */ | |
1628 | unreachable = 0; | |
1629 | for (i = 0; i < n_basic_blocks; i++) | |
1630 | if (dfs_nr[i] == 0) | |
1631 | { | |
1632 | unreachable = 1; | |
1633 | break; | |
1634 | } | |
a2e68776 JL |
1635 | |
1636 | /* Gross. To avoid wasting memory, the second pass uses the dfs_nr array | |
1637 | to hold degree counts. */ | |
1638 | degree = dfs_nr; | |
8c660648 | 1639 | |
7f103e88 SC |
1640 | for (i = 0; i < n_basic_blocks; i++) |
1641 | degree[i] = 0; | |
6b8cf0c5 JL |
1642 | for (i = 0; i < num_edges; i++) |
1643 | { | |
1644 | edge e = INDEX_EDGE (edge_list, i); | |
1645 | ||
7f103e88 SC |
1646 | if (e->dest != EXIT_BLOCK_PTR) |
1647 | degree[e->dest->index]++; | |
6b8cf0c5 | 1648 | } |
a2e68776 | 1649 | |
15ebe47d JL |
1650 | /* Do not perform region scheduling if there are any unreachable |
1651 | blocks. */ | |
1652 | if (!unreachable) | |
8c660648 | 1653 | { |
98903742 MM |
1654 | int *queue; |
1655 | ||
15ebe47d JL |
1656 | if (no_loops) |
1657 | SET_BIT (header, 0); | |
8c660648 | 1658 | |
15ebe47d JL |
1659 | /* Second travsersal:find reducible inner loops and topologically sort |
1660 | block of each region. */ | |
8c660648 | 1661 | |
98903742 | 1662 | queue = (int *) xmalloc (n_basic_blocks * sizeof (int)); |
8c660648 | 1663 | |
cc132865 JL |
1664 | /* Find blocks which are inner loop headers. We still have non-reducible |
1665 | loops to consider at this point. */ | |
15ebe47d JL |
1666 | for (i = 0; i < n_basic_blocks; i++) |
1667 | { | |
1668 | if (TEST_BIT (header, i) && TEST_BIT (inner, i)) | |
1669 | { | |
6b8cf0c5 | 1670 | edge e; |
cc132865 JL |
1671 | int j; |
1672 | ||
1673 | /* Now check that the loop is reducible. We do this separate | |
1674 | from finding inner loops so that we do not find a reducible | |
63de6c74 | 1675 | loop which contains an inner non-reducible loop. |
cc132865 | 1676 | |
63de6c74 | 1677 | A simple way to find reducible/natural loops is to verify |
cc132865 JL |
1678 | that each block in the loop is dominated by the loop |
1679 | header. | |
1680 | ||
1681 | If there exists a block that is not dominated by the loop | |
1682 | header, then the block is reachable from outside the loop | |
1683 | and thus the loop is not a natural loop. */ | |
7a403706 | 1684 | for (j = 0; j < n_basic_blocks; j++) |
cc132865 JL |
1685 | { |
1686 | /* First identify blocks in the loop, except for the loop | |
1687 | entry block. */ | |
1688 | if (i == max_hdr[j] && i != j) | |
1689 | { | |
1690 | /* Now verify that the block is dominated by the loop | |
1691 | header. */ | |
1692 | if (!TEST_BIT (dom[j], i)) | |
1693 | break; | |
1694 | } | |
1695 | } | |
1696 | ||
63de6c74 MH |
1697 | /* If we exited the loop early, then I is the header of |
1698 | a non-reducible loop and we should quit processing it | |
1699 | now. */ | |
cc132865 JL |
1700 | if (j != n_basic_blocks) |
1701 | continue; | |
8c660648 | 1702 | |
cc132865 JL |
1703 | /* I is a header of an inner loop, or block 0 in a subroutine |
1704 | with no loops at all. */ | |
15ebe47d JL |
1705 | head = tail = -1; |
1706 | too_large_failure = 0; | |
1707 | loop_head = max_hdr[i]; | |
8c660648 | 1708 | |
15ebe47d | 1709 | /* Decrease degree of all I's successors for topological |
a59bfd78 | 1710 | ordering. */ |
6b8cf0c5 JL |
1711 | for (e = BASIC_BLOCK (i)->succ; e; e = e->succ_next) |
1712 | if (e->dest != EXIT_BLOCK_PTR) | |
1713 | --degree[e->dest->index]; | |
a2e68776 | 1714 | |
15ebe47d JL |
1715 | /* Estimate # insns, and count # blocks in the region. */ |
1716 | num_bbs = 1; | |
7a403706 | 1717 | num_insns = (INSN_LUID (BLOCK_END (i)) |
3b413743 | 1718 | - INSN_LUID (BLOCK_HEAD (i))); |
8c660648 | 1719 | |
63de6c74 | 1720 | /* Find all loop latches (blocks with back edges to the loop |
15ebe47d JL |
1721 | header) or all the leaf blocks in the cfg has no loops. |
1722 | ||
1723 | Place those blocks into the queue. */ | |
1724 | if (no_loops) | |
1725 | { | |
1726 | for (j = 0; j < n_basic_blocks; j++) | |
1727 | /* Leaf nodes have only a single successor which must | |
1728 | be EXIT_BLOCK. */ | |
6b8cf0c5 JL |
1729 | if (BASIC_BLOCK (j)->succ |
1730 | && BASIC_BLOCK (j)->succ->dest == EXIT_BLOCK_PTR | |
1731 | && BASIC_BLOCK (j)->succ->succ_next == NULL) | |
8c660648 | 1732 | { |
15ebe47d JL |
1733 | queue[++tail] = j; |
1734 | SET_BIT (in_queue, j); | |
1735 | ||
1736 | if (too_large (j, &num_bbs, &num_insns)) | |
1737 | { | |
1738 | too_large_failure = 1; | |
1739 | break; | |
1740 | } | |
8c660648 | 1741 | } |
15ebe47d JL |
1742 | } |
1743 | else | |
8c660648 | 1744 | { |
6b8cf0c5 | 1745 | edge e; |
a2e68776 | 1746 | |
6b8cf0c5 | 1747 | for (e = BASIC_BLOCK (i)->pred; e; e = e->pred_next) |
8c660648 | 1748 | { |
6b8cf0c5 | 1749 | if (e->src == ENTRY_BLOCK_PTR) |
15ebe47d | 1750 | continue; |
6b8cf0c5 JL |
1751 | |
1752 | node = e->src->index; | |
1753 | ||
15ebe47d | 1754 | if (max_hdr[node] == loop_head && node != i) |
8c660648 | 1755 | { |
15ebe47d JL |
1756 | /* This is a loop latch. */ |
1757 | queue[++tail] = node; | |
1758 | SET_BIT (in_queue, node); | |
1759 | ||
1760 | if (too_large (node, &num_bbs, &num_insns)) | |
1761 | { | |
1762 | too_large_failure = 1; | |
1763 | break; | |
1764 | } | |
8c660648 JL |
1765 | } |
1766 | } | |
8c660648 | 1767 | } |
8c660648 | 1768 | |
15ebe47d | 1769 | /* Now add all the blocks in the loop to the queue. |
a2e68776 JL |
1770 | |
1771 | We know the loop is a natural loop; however the algorithm | |
1772 | above will not always mark certain blocks as being in the | |
1773 | loop. Consider: | |
1774 | node children | |
1775 | a b,c | |
1776 | b c | |
1777 | c a,d | |
1778 | d b | |
1779 | ||
a2e68776 JL |
1780 | The algorithm in the DFS traversal may not mark B & D as part |
1781 | of the loop (ie they will not have max_hdr set to A). | |
1782 | ||
1783 | We know they can not be loop latches (else they would have | |
1784 | had max_hdr set since they'd have a backedge to a dominator | |
1785 | block). So we don't need them on the initial queue. | |
1786 | ||
1787 | We know they are part of the loop because they are dominated | |
1788 | by the loop header and can be reached by a backwards walk of | |
1789 | the edges starting with nodes on the initial queue. | |
1790 | ||
1791 | It is safe and desirable to include those nodes in the | |
1792 | loop/scheduling region. To do so we would need to decrease | |
1793 | the degree of a node if it is the target of a backedge | |
1794 | within the loop itself as the node is placed in the queue. | |
1795 | ||
1796 | We do not do this because I'm not sure that the actual | |
1797 | scheduling code will properly handle this case. ?!? */ | |
7a403706 | 1798 | |
15ebe47d | 1799 | while (head < tail && !too_large_failure) |
8c660648 | 1800 | { |
6b8cf0c5 | 1801 | edge e; |
15ebe47d | 1802 | child = queue[++head]; |
8c660648 | 1803 | |
6b8cf0c5 | 1804 | for (e = BASIC_BLOCK (child)->pred; e; e = e->pred_next) |
8c660648 | 1805 | { |
6b8cf0c5 | 1806 | node = e->src->index; |
8c660648 | 1807 | |
15ebe47d JL |
1808 | /* See discussion above about nodes not marked as in |
1809 | this loop during the initial DFS traversal. */ | |
6b8cf0c5 | 1810 | if (e->src == ENTRY_BLOCK_PTR |
15ebe47d | 1811 | || max_hdr[node] != loop_head) |
8c660648 | 1812 | { |
15ebe47d | 1813 | tail = -1; |
8c660648 JL |
1814 | break; |
1815 | } | |
15ebe47d JL |
1816 | else if (!TEST_BIT (in_queue, node) && node != i) |
1817 | { | |
1818 | queue[++tail] = node; | |
1819 | SET_BIT (in_queue, node); | |
1820 | ||
1821 | if (too_large (node, &num_bbs, &num_insns)) | |
1822 | { | |
1823 | too_large_failure = 1; | |
1824 | break; | |
1825 | } | |
1826 | } | |
8c660648 | 1827 | } |
8c660648 | 1828 | } |
8c660648 | 1829 | |
15ebe47d JL |
1830 | if (tail >= 0 && !too_large_failure) |
1831 | { | |
1832 | /* Place the loop header into list of region blocks. */ | |
1833 | degree[i] = -1; | |
1834 | rgn_bb_table[idx] = i; | |
1835 | RGN_NR_BLOCKS (nr_regions) = num_bbs; | |
1836 | RGN_BLOCKS (nr_regions) = idx++; | |
1837 | CONTAINING_RGN (i) = nr_regions; | |
1838 | BLOCK_TO_BB (i) = count = 0; | |
1839 | ||
63de6c74 MH |
1840 | /* Remove blocks from queue[] when their in degree |
1841 | becomes zero. Repeat until no blocks are left on the | |
1842 | list. This produces a topological list of blocks in | |
1843 | the region. */ | |
15ebe47d | 1844 | while (tail >= 0) |
8c660648 | 1845 | { |
15ebe47d JL |
1846 | if (head < 0) |
1847 | head = tail; | |
1848 | child = queue[head]; | |
1849 | if (degree[child] == 0) | |
1850 | { | |
6b8cf0c5 JL |
1851 | edge e; |
1852 | ||
15ebe47d JL |
1853 | degree[child] = -1; |
1854 | rgn_bb_table[idx++] = child; | |
1855 | BLOCK_TO_BB (child) = ++count; | |
1856 | CONTAINING_RGN (child) = nr_regions; | |
1857 | queue[head] = queue[tail--]; | |
1858 | ||
6b8cf0c5 JL |
1859 | for (e = BASIC_BLOCK (child)->succ; |
1860 | e; | |
1861 | e = e->succ_next) | |
1862 | if (e->dest != EXIT_BLOCK_PTR) | |
1863 | --degree[e->dest->index]; | |
15ebe47d JL |
1864 | } |
1865 | else | |
1866 | --head; | |
8c660648 | 1867 | } |
15ebe47d | 1868 | ++nr_regions; |
8c660648 | 1869 | } |
8c660648 JL |
1870 | } |
1871 | } | |
98903742 | 1872 | free (queue); |
8c660648 JL |
1873 | } |
1874 | ||
a2e68776 JL |
1875 | /* Any block that did not end up in a region is placed into a region |
1876 | by itself. */ | |
8c660648 JL |
1877 | for (i = 0; i < n_basic_blocks; i++) |
1878 | if (degree[i] >= 0) | |
1879 | { | |
1880 | rgn_bb_table[idx] = i; | |
1881 | RGN_NR_BLOCKS (nr_regions) = 1; | |
1882 | RGN_BLOCKS (nr_regions) = idx++; | |
1883 | CONTAINING_RGN (i) = nr_regions++; | |
1884 | BLOCK_TO_BB (i) = 0; | |
1885 | } | |
1886 | ||
98903742 MM |
1887 | free (max_hdr); |
1888 | free (dfs_nr); | |
1889 | free (stack); | |
a2e68776 JL |
1890 | free (passed); |
1891 | free (header); | |
1892 | free (inner); | |
1893 | free (in_queue); | |
cc132865 | 1894 | free (in_stack); |
a2e68776 | 1895 | } |
8c660648 | 1896 | |
63de6c74 | 1897 | /* Functions for regions scheduling information. */ |
8c660648 JL |
1898 | |
1899 | /* Compute dominators, probability, and potential-split-edges of bb. | |
1900 | Assume that these values were already computed for bb's predecessors. */ | |
1901 | ||
1902 | static void | |
1903 | compute_dom_prob_ps (bb) | |
1904 | int bb; | |
1905 | { | |
1906 | int nxt_in_edge, fst_in_edge, pred; | |
1907 | int fst_out_edge, nxt_out_edge, nr_out_edges, nr_rgn_out_edges; | |
1908 | ||
1909 | prob[bb] = 0.0; | |
1910 | if (IS_RGN_ENTRY (bb)) | |
1911 | { | |
1912 | BITSET_ADD (dom[bb], 0, bbset_size); | |
1913 | prob[bb] = 1.0; | |
1914 | return; | |
1915 | } | |
1916 | ||
1917 | fst_in_edge = nxt_in_edge = IN_EDGES (BB_TO_BLOCK (bb)); | |
1918 | ||
63de6c74 | 1919 | /* Intialize dom[bb] to '111..1'. */ |
8c660648 JL |
1920 | BITSET_INVERT (dom[bb], bbset_size); |
1921 | ||
1922 | do | |
1923 | { | |
1924 | pred = FROM_BLOCK (nxt_in_edge); | |
1925 | BITSET_INTER (dom[bb], dom[BLOCK_TO_BB (pred)], bbset_size); | |
1926 | ||
1927 | BITSET_UNION (ancestor_edges[bb], ancestor_edges[BLOCK_TO_BB (pred)], | |
1928 | edgeset_size); | |
1929 | ||
1930 | BITSET_ADD (ancestor_edges[bb], EDGE_TO_BIT (nxt_in_edge), edgeset_size); | |
1931 | ||
1932 | nr_out_edges = 1; | |
1933 | nr_rgn_out_edges = 0; | |
1934 | fst_out_edge = OUT_EDGES (pred); | |
1935 | nxt_out_edge = NEXT_OUT (fst_out_edge); | |
1936 | BITSET_UNION (pot_split[bb], pot_split[BLOCK_TO_BB (pred)], | |
1937 | edgeset_size); | |
1938 | ||
1939 | BITSET_ADD (pot_split[bb], EDGE_TO_BIT (fst_out_edge), edgeset_size); | |
1940 | ||
63de6c74 | 1941 | /* The successor doesn't belong in the region? */ |
8c660648 JL |
1942 | if (CONTAINING_RGN (TO_BLOCK (fst_out_edge)) != |
1943 | CONTAINING_RGN (BB_TO_BLOCK (bb))) | |
1944 | ++nr_rgn_out_edges; | |
1945 | ||
1946 | while (fst_out_edge != nxt_out_edge) | |
1947 | { | |
1948 | ++nr_out_edges; | |
63de6c74 | 1949 | /* The successor doesn't belong in the region? */ |
8c660648 JL |
1950 | if (CONTAINING_RGN (TO_BLOCK (nxt_out_edge)) != |
1951 | CONTAINING_RGN (BB_TO_BLOCK (bb))) | |
1952 | ++nr_rgn_out_edges; | |
1953 | BITSET_ADD (pot_split[bb], EDGE_TO_BIT (nxt_out_edge), edgeset_size); | |
1954 | nxt_out_edge = NEXT_OUT (nxt_out_edge); | |
1955 | ||
1956 | } | |
1957 | ||
63de6c74 MH |
1958 | /* Now nr_rgn_out_edges is the number of region-exit edges from |
1959 | pred, and nr_out_edges will be the number of pred out edges | |
1960 | not leaving the region. */ | |
8c660648 JL |
1961 | nr_out_edges -= nr_rgn_out_edges; |
1962 | if (nr_rgn_out_edges > 0) | |
1963 | prob[bb] += 0.9 * prob[BLOCK_TO_BB (pred)] / nr_out_edges; | |
1964 | else | |
1965 | prob[bb] += prob[BLOCK_TO_BB (pred)] / nr_out_edges; | |
1966 | nxt_in_edge = NEXT_IN (nxt_in_edge); | |
1967 | } | |
1968 | while (fst_in_edge != nxt_in_edge); | |
1969 | ||
1970 | BITSET_ADD (dom[bb], bb, bbset_size); | |
1971 | BITSET_DIFFER (pot_split[bb], ancestor_edges[bb], edgeset_size); | |
1972 | ||
1973 | if (sched_verbose >= 2) | |
7a403706 KH |
1974 | fprintf (dump, ";; bb_prob(%d, %d) = %3d\n", bb, BB_TO_BLOCK (bb), |
1975 | (int) (100.0 * prob[bb])); | |
1976 | } | |
8c660648 | 1977 | |
63de6c74 | 1978 | /* Functions for target info. */ |
8c660648 JL |
1979 | |
1980 | /* Compute in BL the list of split-edges of bb_src relatively to bb_trg. | |
1981 | Note that bb_trg dominates bb_src. */ | |
1982 | ||
1983 | static void | |
1984 | split_edges (bb_src, bb_trg, bl) | |
1985 | int bb_src; | |
1986 | int bb_trg; | |
1987 | edgelst *bl; | |
1988 | { | |
1989 | int es = edgeset_size; | |
86133292 | 1990 | edgeset src = (edgeset) xcalloc (es, sizeof (HOST_WIDE_INT)); |
8c660648 JL |
1991 | |
1992 | while (es--) | |
1993 | src[es] = (pot_split[bb_src])[es]; | |
1994 | BITSET_DIFFER (src, pot_split[bb_trg], edgeset_size); | |
394c46fe | 1995 | extract_bitlst (src, edgeset_size, edgeset_bitsize, bl); |
98903742 | 1996 | free (src); |
8c660648 JL |
1997 | } |
1998 | ||
8c660648 JL |
1999 | /* Find the valid candidate-source-blocks for the target block TRG, compute |
2000 | their probability, and check if they are speculative or not. | |
2001 | For speculative sources, compute their update-blocks and split-blocks. */ | |
2002 | ||
2003 | static void | |
2004 | compute_trg_info (trg) | |
2005 | int trg; | |
2006 | { | |
2007 | register candidate *sp; | |
2008 | edgelst el; | |
2009 | int check_block, update_idx; | |
2010 | int i, j, k, fst_edge, nxt_edge; | |
2011 | ||
63de6c74 | 2012 | /* Define some of the fields for the target bb as well. */ |
8c660648 JL |
2013 | sp = candidate_table + trg; |
2014 | sp->is_valid = 1; | |
2015 | sp->is_speculative = 0; | |
2016 | sp->src_prob = 100; | |
2017 | ||
2018 | for (i = trg + 1; i < current_nr_blocks; i++) | |
2019 | { | |
2020 | sp = candidate_table + i; | |
2021 | ||
2022 | sp->is_valid = IS_DOMINATED (i, trg); | |
2023 | if (sp->is_valid) | |
2024 | { | |
2025 | sp->src_prob = GET_SRC_PROB (i, trg); | |
2026 | sp->is_valid = (sp->src_prob >= MIN_PROBABILITY); | |
2027 | } | |
2028 | ||
2029 | if (sp->is_valid) | |
2030 | { | |
2031 | split_edges (i, trg, &el); | |
2032 | sp->is_speculative = (el.nr_members) ? 1 : 0; | |
2033 | if (sp->is_speculative && !flag_schedule_speculative) | |
2034 | sp->is_valid = 0; | |
2035 | } | |
2036 | ||
2037 | if (sp->is_valid) | |
2038 | { | |
ef375129 JW |
2039 | char *update_blocks; |
2040 | ||
2041 | /* Compute split blocks and store them in bblst_table. | |
2042 | The TO block of every split edge is a split block. */ | |
8c660648 JL |
2043 | sp->split_bbs.first_member = &bblst_table[bblst_last]; |
2044 | sp->split_bbs.nr_members = el.nr_members; | |
2045 | for (j = 0; j < el.nr_members; bblst_last++, j++) | |
2046 | bblst_table[bblst_last] = | |
2047 | TO_BLOCK (rgn_edges[el.first_member[j]]); | |
2048 | sp->update_bbs.first_member = &bblst_table[bblst_last]; | |
ef375129 JW |
2049 | |
2050 | /* Compute update blocks and store them in bblst_table. | |
2051 | For every split edge, look at the FROM block, and check | |
2052 | all out edges. For each out edge that is not a split edge, | |
2053 | add the TO block to the update block list. This list can end | |
2054 | up with a lot of duplicates. We need to weed them out to avoid | |
2055 | overrunning the end of the bblst_table. */ | |
2056 | update_blocks = (char *) alloca (n_basic_blocks); | |
2057 | bzero (update_blocks, n_basic_blocks); | |
2058 | ||
8c660648 JL |
2059 | update_idx = 0; |
2060 | for (j = 0; j < el.nr_members; j++) | |
2061 | { | |
2062 | check_block = FROM_BLOCK (rgn_edges[el.first_member[j]]); | |
2063 | fst_edge = nxt_edge = OUT_EDGES (check_block); | |
2064 | do | |
2065 | { | |
ef375129 | 2066 | if (! update_blocks[TO_BLOCK (nxt_edge)]) |
8c660648 | 2067 | { |
ef375129 JW |
2068 | for (k = 0; k < el.nr_members; k++) |
2069 | if (EDGE_TO_BIT (nxt_edge) == el.first_member[k]) | |
2070 | break; | |
2071 | ||
2072 | if (k >= el.nr_members) | |
2073 | { | |
2074 | bblst_table[bblst_last++] = TO_BLOCK (nxt_edge); | |
2075 | update_blocks[TO_BLOCK (nxt_edge)] = 1; | |
2076 | update_idx++; | |
2077 | } | |
8c660648 JL |
2078 | } |
2079 | ||
2080 | nxt_edge = NEXT_OUT (nxt_edge); | |
2081 | } | |
2082 | while (fst_edge != nxt_edge); | |
2083 | } | |
2084 | sp->update_bbs.nr_members = update_idx; | |
2085 | ||
ef375129 JW |
2086 | /* Make sure we didn't overrun the end of bblst_table. */ |
2087 | if (bblst_last > bblst_size) | |
2088 | abort (); | |
8c660648 JL |
2089 | } |
2090 | else | |
2091 | { | |
2092 | sp->split_bbs.nr_members = sp->update_bbs.nr_members = 0; | |
2093 | ||
2094 | sp->is_speculative = 0; | |
2095 | sp->src_prob = 0; | |
2096 | } | |
2097 | } | |
7a403706 | 2098 | } |
8c660648 JL |
2099 | |
2100 | /* Print candidates info, for debugging purposes. Callable from debugger. */ | |
2101 | ||
2102 | void | |
2103 | debug_candidate (i) | |
2104 | int i; | |
2105 | { | |
2106 | if (!candidate_table[i].is_valid) | |
2107 | return; | |
2108 | ||
2109 | if (candidate_table[i].is_speculative) | |
2110 | { | |
2111 | int j; | |
2112 | fprintf (dump, "src b %d bb %d speculative \n", BB_TO_BLOCK (i), i); | |
2113 | ||
2114 | fprintf (dump, "split path: "); | |
2115 | for (j = 0; j < candidate_table[i].split_bbs.nr_members; j++) | |
2116 | { | |
2117 | int b = candidate_table[i].split_bbs.first_member[j]; | |
2118 | ||
2119 | fprintf (dump, " %d ", b); | |
2120 | } | |
2121 | fprintf (dump, "\n"); | |
2122 | ||
2123 | fprintf (dump, "update path: "); | |
2124 | for (j = 0; j < candidate_table[i].update_bbs.nr_members; j++) | |
2125 | { | |
2126 | int b = candidate_table[i].update_bbs.first_member[j]; | |
2127 | ||
2128 | fprintf (dump, " %d ", b); | |
2129 | } | |
2130 | fprintf (dump, "\n"); | |
2131 | } | |
2132 | else | |
2133 | { | |
2134 | fprintf (dump, " src %d equivalent\n", BB_TO_BLOCK (i)); | |
2135 | } | |
2136 | } | |
2137 | ||
8c660648 JL |
2138 | /* Print candidates info, for debugging purposes. Callable from debugger. */ |
2139 | ||
2140 | void | |
2141 | debug_candidates (trg) | |
2142 | int trg; | |
2143 | { | |
2144 | int i; | |
2145 | ||
2146 | fprintf (dump, "----------- candidate table: target: b=%d bb=%d ---\n", | |
2147 | BB_TO_BLOCK (trg), trg); | |
2148 | for (i = trg + 1; i < current_nr_blocks; i++) | |
2149 | debug_candidate (i); | |
2150 | } | |
2151 | ||
63de6c74 | 2152 | /* Functions for speculative scheduing. */ |
8c660648 JL |
2153 | |
2154 | /* Return 0 if x is a set of a register alive in the beginning of one | |
2155 | of the split-blocks of src, otherwise return 1. */ | |
2156 | ||
2157 | static int | |
2158 | check_live_1 (src, x) | |
2159 | int src; | |
2160 | rtx x; | |
2161 | { | |
5835e573 | 2162 | register int i; |
8c660648 JL |
2163 | register int regno; |
2164 | register rtx reg = SET_DEST (x); | |
2165 | ||
2166 | if (reg == 0) | |
2167 | return 1; | |
2168 | ||
2169 | while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT | |
2170 | || GET_CODE (reg) == SIGN_EXTRACT | |
2171 | || GET_CODE (reg) == STRICT_LOW_PART) | |
2172 | reg = XEXP (reg, 0); | |
2173 | ||
c0222c21 DM |
2174 | if (GET_CODE (reg) == PARALLEL |
2175 | && GET_MODE (reg) == BLKmode) | |
2176 | { | |
2177 | register int i; | |
2178 | for (i = XVECLEN (reg, 0) - 1; i >= 0; i--) | |
2179 | if (check_live_1 (src, XVECEXP (reg, 0, i))) | |
2180 | return 1; | |
2181 | return 0; | |
2182 | } | |
2183 | ||
8c660648 JL |
2184 | if (GET_CODE (reg) != REG) |
2185 | return 1; | |
2186 | ||
2187 | regno = REGNO (reg); | |
2188 | ||
2189 | if (regno < FIRST_PSEUDO_REGISTER && global_regs[regno]) | |
2190 | { | |
63de6c74 | 2191 | /* Global registers are assumed live. */ |
8c660648 JL |
2192 | return 0; |
2193 | } | |
2194 | else | |
2195 | { | |
2196 | if (regno < FIRST_PSEUDO_REGISTER) | |
2197 | { | |
63de6c74 | 2198 | /* Check for hard registers. */ |
8c660648 JL |
2199 | int j = HARD_REGNO_NREGS (regno, GET_MODE (reg)); |
2200 | while (--j >= 0) | |
2201 | { | |
2202 | for (i = 0; i < candidate_table[src].split_bbs.nr_members; i++) | |
2203 | { | |
2204 | int b = candidate_table[src].split_bbs.first_member[i]; | |
2205 | ||
e881bb1b RH |
2206 | if (REGNO_REG_SET_P (BASIC_BLOCK (b)->global_live_at_start, |
2207 | regno + j)) | |
8c660648 JL |
2208 | { |
2209 | return 0; | |
2210 | } | |
2211 | } | |
2212 | } | |
2213 | } | |
2214 | else | |
2215 | { | |
63de6c74 | 2216 | /* Check for psuedo registers. */ |
8c660648 JL |
2217 | for (i = 0; i < candidate_table[src].split_bbs.nr_members; i++) |
2218 | { | |
2219 | int b = candidate_table[src].split_bbs.first_member[i]; | |
2220 | ||
e881bb1b | 2221 | if (REGNO_REG_SET_P (BASIC_BLOCK (b)->global_live_at_start, regno)) |
8c660648 JL |
2222 | { |
2223 | return 0; | |
2224 | } | |
2225 | } | |
2226 | } | |
2227 | } | |
2228 | ||
2229 | return 1; | |
2230 | } | |
2231 | ||
8c660648 JL |
2232 | /* If x is a set of a register R, mark that R is alive in the beginning |
2233 | of every update-block of src. */ | |
2234 | ||
2235 | static void | |
2236 | update_live_1 (src, x) | |
2237 | int src; | |
2238 | rtx x; | |
2239 | { | |
5835e573 | 2240 | register int i; |
8c660648 JL |
2241 | register int regno; |
2242 | register rtx reg = SET_DEST (x); | |
2243 | ||
2244 | if (reg == 0) | |
2245 | return; | |
2246 | ||
2247 | while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT | |
2248 | || GET_CODE (reg) == SIGN_EXTRACT | |
2249 | || GET_CODE (reg) == STRICT_LOW_PART) | |
2250 | reg = XEXP (reg, 0); | |
2251 | ||
c0222c21 DM |
2252 | if (GET_CODE (reg) == PARALLEL |
2253 | && GET_MODE (reg) == BLKmode) | |
2254 | { | |
2255 | register int i; | |
2256 | for (i = XVECLEN (reg, 0) - 1; i >= 0; i--) | |
2257 | update_live_1 (src, XVECEXP (reg, 0, i)); | |
2258 | return; | |
2259 | } | |
2260 | ||
8c660648 JL |
2261 | if (GET_CODE (reg) != REG) |
2262 | return; | |
2263 | ||
2264 | /* Global registers are always live, so the code below does not apply | |
2265 | to them. */ | |
2266 | ||
2267 | regno = REGNO (reg); | |
2268 | ||
2269 | if (regno >= FIRST_PSEUDO_REGISTER || !global_regs[regno]) | |
2270 | { | |
2271 | if (regno < FIRST_PSEUDO_REGISTER) | |
2272 | { | |
2273 | int j = HARD_REGNO_NREGS (regno, GET_MODE (reg)); | |
2274 | while (--j >= 0) | |
2275 | { | |
2276 | for (i = 0; i < candidate_table[src].update_bbs.nr_members; i++) | |
2277 | { | |
2278 | int b = candidate_table[src].update_bbs.first_member[i]; | |
2279 | ||
e881bb1b RH |
2280 | SET_REGNO_REG_SET (BASIC_BLOCK (b)->global_live_at_start, |
2281 | regno + j); | |
8c660648 JL |
2282 | } |
2283 | } | |
2284 | } | |
2285 | else | |
2286 | { | |
2287 | for (i = 0; i < candidate_table[src].update_bbs.nr_members; i++) | |
2288 | { | |
2289 | int b = candidate_table[src].update_bbs.first_member[i]; | |
2290 | ||
e881bb1b | 2291 | SET_REGNO_REG_SET (BASIC_BLOCK (b)->global_live_at_start, regno); |
8c660648 JL |
2292 | } |
2293 | } | |
2294 | } | |
2295 | } | |
2296 | ||
8c660648 JL |
2297 | /* Return 1 if insn can be speculatively moved from block src to trg, |
2298 | otherwise return 0. Called before first insertion of insn to | |
2299 | ready-list or before the scheduling. */ | |
2300 | ||
2301 | static int | |
5835e573 | 2302 | check_live (insn, src) |
8c660648 JL |
2303 | rtx insn; |
2304 | int src; | |
8c660648 | 2305 | { |
63de6c74 | 2306 | /* Find the registers set by instruction. */ |
8c660648 JL |
2307 | if (GET_CODE (PATTERN (insn)) == SET |
2308 | || GET_CODE (PATTERN (insn)) == CLOBBER) | |
2309 | return check_live_1 (src, PATTERN (insn)); | |
2310 | else if (GET_CODE (PATTERN (insn)) == PARALLEL) | |
2311 | { | |
2312 | int j; | |
2313 | for (j = XVECLEN (PATTERN (insn), 0) - 1; j >= 0; j--) | |
2314 | if ((GET_CODE (XVECEXP (PATTERN (insn), 0, j)) == SET | |
2315 | || GET_CODE (XVECEXP (PATTERN (insn), 0, j)) == CLOBBER) | |
2316 | && !check_live_1 (src, XVECEXP (PATTERN (insn), 0, j))) | |
2317 | return 0; | |
2318 | ||
2319 | return 1; | |
2320 | } | |
2321 | ||
2322 | return 1; | |
2323 | } | |
2324 | ||
8c660648 JL |
2325 | /* Update the live registers info after insn was moved speculatively from |
2326 | block src to trg. */ | |
2327 | ||
2328 | static void | |
5835e573 | 2329 | update_live (insn, src) |
8c660648 | 2330 | rtx insn; |
5835e573 | 2331 | int src; |
8c660648 | 2332 | { |
63de6c74 | 2333 | /* Find the registers set by instruction. */ |
8c660648 JL |
2334 | if (GET_CODE (PATTERN (insn)) == SET |
2335 | || GET_CODE (PATTERN (insn)) == CLOBBER) | |
2336 | update_live_1 (src, PATTERN (insn)); | |
2337 | else if (GET_CODE (PATTERN (insn)) == PARALLEL) | |
2338 | { | |
2339 | int j; | |
2340 | for (j = XVECLEN (PATTERN (insn), 0) - 1; j >= 0; j--) | |
2341 | if (GET_CODE (XVECEXP (PATTERN (insn), 0, j)) == SET | |
2342 | || GET_CODE (XVECEXP (PATTERN (insn), 0, j)) == CLOBBER) | |
2343 | update_live_1 (src, XVECEXP (PATTERN (insn), 0, j)); | |
2344 | } | |
2345 | } | |
2346 | ||
2347 | /* Exception Free Loads: | |
2348 | ||
2349 | We define five classes of speculative loads: IFREE, IRISKY, | |
2350 | PFREE, PRISKY, and MFREE. | |
2351 | ||
2352 | IFREE loads are loads that are proved to be exception-free, just | |
2353 | by examining the load insn. Examples for such loads are loads | |
2354 | from TOC and loads of global data. | |
2355 | ||
2356 | IRISKY loads are loads that are proved to be exception-risky, | |
2357 | just by examining the load insn. Examples for such loads are | |
2358 | volatile loads and loads from shared memory. | |
2359 | ||
2360 | PFREE loads are loads for which we can prove, by examining other | |
2361 | insns, that they are exception-free. Currently, this class consists | |
2362 | of loads for which we are able to find a "similar load", either in | |
2363 | the target block, or, if only one split-block exists, in that split | |
2364 | block. Load2 is similar to load1 if both have same single base | |
2365 | register. We identify only part of the similar loads, by finding | |
2366 | an insn upon which both load1 and load2 have a DEF-USE dependence. | |
2367 | ||
2368 | PRISKY loads are loads for which we can prove, by examining other | |
2369 | insns, that they are exception-risky. Currently we have two proofs for | |
2370 | such loads. The first proof detects loads that are probably guarded by a | |
2371 | test on the memory address. This proof is based on the | |
2372 | backward and forward data dependence information for the region. | |
2373 | Let load-insn be the examined load. | |
2374 | Load-insn is PRISKY iff ALL the following hold: | |
2375 | ||
2376 | - insn1 is not in the same block as load-insn | |
2377 | - there is a DEF-USE dependence chain (insn1, ..., load-insn) | |
63de6c74 MH |
2378 | - test-insn is either a compare or a branch, not in the same block |
2379 | as load-insn | |
8c660648 JL |
2380 | - load-insn is reachable from test-insn |
2381 | - there is a DEF-USE dependence chain (insn1, ..., test-insn) | |
2382 | ||
2383 | This proof might fail when the compare and the load are fed | |
2384 | by an insn not in the region. To solve this, we will add to this | |
2385 | group all loads that have no input DEF-USE dependence. | |
2386 | ||
2387 | The second proof detects loads that are directly or indirectly | |
2388 | fed by a speculative load. This proof is affected by the | |
2389 | scheduling process. We will use the flag fed_by_spec_load. | |
2390 | Initially, all insns have this flag reset. After a speculative | |
2391 | motion of an insn, if insn is either a load, or marked as | |
2392 | fed_by_spec_load, we will also mark as fed_by_spec_load every | |
2393 | insn1 for which a DEF-USE dependence (insn, insn1) exists. A | |
2394 | load which is fed_by_spec_load is also PRISKY. | |
2395 | ||
2396 | MFREE (maybe-free) loads are all the remaining loads. They may be | |
2397 | exception-free, but we cannot prove it. | |
2398 | ||
2399 | Now, all loads in IFREE and PFREE classes are considered | |
2400 | exception-free, while all loads in IRISKY and PRISKY classes are | |
2401 | considered exception-risky. As for loads in the MFREE class, | |
2402 | these are considered either exception-free or exception-risky, | |
2403 | depending on whether we are pessimistic or optimistic. We have | |
2404 | to take the pessimistic approach to assure the safety of | |
2405 | speculative scheduling, but we can take the optimistic approach | |
2406 | by invoking the -fsched_spec_load_dangerous option. */ | |
2407 | ||
2408 | enum INSN_TRAP_CLASS | |
2409 | { | |
2410 | TRAP_FREE = 0, IFREE = 1, PFREE_CANDIDATE = 2, | |
2411 | PRISKY_CANDIDATE = 3, IRISKY = 4, TRAP_RISKY = 5 | |
2412 | }; | |
2413 | ||
2414 | #define WORST_CLASS(class1, class2) \ | |
2415 | ((class1 > class2) ? class1 : class2) | |
2416 | ||
8c660648 JL |
2417 | /* Non-zero if block bb_to is equal to, or reachable from block bb_from. */ |
2418 | #define IS_REACHABLE(bb_from, bb_to) \ | |
2419 | (bb_from == bb_to \ | |
2420 | || IS_RGN_ENTRY (bb_from) \ | |
2421 | || (bitset_member (ancestor_edges[bb_to], \ | |
2422 | EDGE_TO_BIT (IN_EDGES (BB_TO_BLOCK (bb_from))), \ | |
2423 | edgeset_size))) | |
8c660648 | 2424 | |
63de6c74 | 2425 | /* Non-zero iff the address is comprised from at most 1 register. */ |
8c660648 JL |
2426 | #define CONST_BASED_ADDRESS_P(x) \ |
2427 | (GET_CODE (x) == REG \ | |
2428 | || ((GET_CODE (x) == PLUS || GET_CODE (x) == MINUS \ | |
2429 | || (GET_CODE (x) == LO_SUM)) \ | |
2430 | && (GET_CODE (XEXP (x, 0)) == CONST_INT \ | |
2431 | || GET_CODE (XEXP (x, 1)) == CONST_INT))) | |
2432 | ||
2433 | /* Turns on the fed_by_spec_load flag for insns fed by load_insn. */ | |
2434 | ||
2435 | static void | |
2436 | set_spec_fed (load_insn) | |
2437 | rtx load_insn; | |
2438 | { | |
2439 | rtx link; | |
2440 | ||
2441 | for (link = INSN_DEPEND (load_insn); link; link = XEXP (link, 1)) | |
2442 | if (GET_MODE (link) == VOIDmode) | |
2443 | FED_BY_SPEC_LOAD (XEXP (link, 0)) = 1; | |
2444 | } /* set_spec_fed */ | |
2445 | ||
63de6c74 MH |
2446 | /* On the path from the insn to load_insn_bb, find a conditional |
2447 | branch depending on insn, that guards the speculative load. */ | |
8c660648 JL |
2448 | |
2449 | static int | |
2450 | find_conditional_protection (insn, load_insn_bb) | |
2451 | rtx insn; | |
2452 | int load_insn_bb; | |
2453 | { | |
2454 | rtx link; | |
2455 | ||
63de6c74 | 2456 | /* Iterate through DEF-USE forward dependences. */ |
8c660648 JL |
2457 | for (link = INSN_DEPEND (insn); link; link = XEXP (link, 1)) |
2458 | { | |
2459 | rtx next = XEXP (link, 0); | |
c88e8206 | 2460 | if ((CONTAINING_RGN (BLOCK_NUM (next)) == |
8c660648 JL |
2461 | CONTAINING_RGN (BB_TO_BLOCK (load_insn_bb))) |
2462 | && IS_REACHABLE (INSN_BB (next), load_insn_bb) | |
2463 | && load_insn_bb != INSN_BB (next) | |
2464 | && GET_MODE (link) == VOIDmode | |
2465 | && (GET_CODE (next) == JUMP_INSN | |
2466 | || find_conditional_protection (next, load_insn_bb))) | |
2467 | return 1; | |
2468 | } | |
2469 | return 0; | |
2470 | } /* find_conditional_protection */ | |
2471 | ||
2472 | /* Returns 1 if the same insn1 that participates in the computation | |
2473 | of load_insn's address is feeding a conditional branch that is | |
2474 | guarding on load_insn. This is true if we find a the two DEF-USE | |
2475 | chains: | |
2476 | insn1 -> ... -> conditional-branch | |
2477 | insn1 -> ... -> load_insn, | |
2478 | and if a flow path exist: | |
2479 | insn1 -> ... -> conditional-branch -> ... -> load_insn, | |
2480 | and if insn1 is on the path | |
2481 | region-entry -> ... -> bb_trg -> ... load_insn. | |
2482 | ||
2483 | Locate insn1 by climbing on LOG_LINKS from load_insn. | |
2484 | Locate the branch by following INSN_DEPEND from insn1. */ | |
2485 | ||
2486 | static int | |
2487 | is_conditionally_protected (load_insn, bb_src, bb_trg) | |
2488 | rtx load_insn; | |
2489 | int bb_src, bb_trg; | |
2490 | { | |
2491 | rtx link; | |
2492 | ||
2493 | for (link = LOG_LINKS (load_insn); link; link = XEXP (link, 1)) | |
2494 | { | |
2495 | rtx insn1 = XEXP (link, 0); | |
2496 | ||
63de6c74 | 2497 | /* Must be a DEF-USE dependence upon non-branch. */ |
8c660648 JL |
2498 | if (GET_MODE (link) != VOIDmode |
2499 | || GET_CODE (insn1) == JUMP_INSN) | |
2500 | continue; | |
2501 | ||
63de6c74 | 2502 | /* Must exist a path: region-entry -> ... -> bb_trg -> ... load_insn. */ |
8c660648 | 2503 | if (INSN_BB (insn1) == bb_src |
c88e8206 | 2504 | || (CONTAINING_RGN (BLOCK_NUM (insn1)) |
8c660648 JL |
2505 | != CONTAINING_RGN (BB_TO_BLOCK (bb_src))) |
2506 | || (!IS_REACHABLE (bb_trg, INSN_BB (insn1)) | |
2507 | && !IS_REACHABLE (INSN_BB (insn1), bb_trg))) | |
2508 | continue; | |
2509 | ||
63de6c74 | 2510 | /* Now search for the conditional-branch. */ |
8c660648 JL |
2511 | if (find_conditional_protection (insn1, bb_src)) |
2512 | return 1; | |
2513 | ||
63de6c74 | 2514 | /* Recursive step: search another insn1, "above" current insn1. */ |
8c660648 JL |
2515 | return is_conditionally_protected (insn1, bb_src, bb_trg); |
2516 | } | |
2517 | ||
63de6c74 | 2518 | /* The chain does not exist. */ |
8c660648 JL |
2519 | return 0; |
2520 | } /* is_conditionally_protected */ | |
2521 | ||
2522 | /* Returns 1 if a clue for "similar load" 'insn2' is found, and hence | |
2523 | load_insn can move speculatively from bb_src to bb_trg. All the | |
2524 | following must hold: | |
2525 | ||
2526 | (1) both loads have 1 base register (PFREE_CANDIDATEs). | |
2527 | (2) load_insn and load1 have a def-use dependence upon | |
2528 | the same insn 'insn1'. | |
2529 | (3) either load2 is in bb_trg, or: | |
2530 | - there's only one split-block, and | |
2531 | - load1 is on the escape path, and | |
2532 | ||
2533 | From all these we can conclude that the two loads access memory | |
2534 | addresses that differ at most by a constant, and hence if moving | |
2535 | load_insn would cause an exception, it would have been caused by | |
2536 | load2 anyhow. */ | |
2537 | ||
2538 | static int | |
2539 | is_pfree (load_insn, bb_src, bb_trg) | |
2540 | rtx load_insn; | |
2541 | int bb_src, bb_trg; | |
2542 | { | |
2543 | rtx back_link; | |
2544 | register candidate *candp = candidate_table + bb_src; | |
2545 | ||
2546 | if (candp->split_bbs.nr_members != 1) | |
63de6c74 | 2547 | /* Must have exactly one escape block. */ |
8c660648 JL |
2548 | return 0; |
2549 | ||
2550 | for (back_link = LOG_LINKS (load_insn); | |
2551 | back_link; back_link = XEXP (back_link, 1)) | |
2552 | { | |
2553 | rtx insn1 = XEXP (back_link, 0); | |
2554 | ||
2555 | if (GET_MODE (back_link) == VOIDmode) | |
2556 | { | |
63de6c74 | 2557 | /* Found a DEF-USE dependence (insn1, load_insn). */ |
8c660648 JL |
2558 | rtx fore_link; |
2559 | ||
2560 | for (fore_link = INSN_DEPEND (insn1); | |
2561 | fore_link; fore_link = XEXP (fore_link, 1)) | |
2562 | { | |
2563 | rtx insn2 = XEXP (fore_link, 0); | |
2564 | if (GET_MODE (fore_link) == VOIDmode) | |
2565 | { | |
63de6c74 | 2566 | /* Found a DEF-USE dependence (insn1, insn2). */ |
ac957f13 | 2567 | if (haifa_classify_insn (insn2) != PFREE_CANDIDATE) |
63de6c74 | 2568 | /* insn2 not guaranteed to be a 1 base reg load. */ |
8c660648 JL |
2569 | continue; |
2570 | ||
2571 | if (INSN_BB (insn2) == bb_trg) | |
63de6c74 | 2572 | /* insn2 is the similar load, in the target block. */ |
8c660648 JL |
2573 | return 1; |
2574 | ||
c88e8206 | 2575 | if (*(candp->split_bbs.first_member) == BLOCK_NUM (insn2)) |
63de6c74 | 2576 | /* insn2 is a similar load, in a split-block. */ |
8c660648 JL |
2577 | return 1; |
2578 | } | |
2579 | } | |
2580 | } | |
2581 | } | |
2582 | ||
63de6c74 | 2583 | /* Couldn't find a similar load. */ |
8c660648 JL |
2584 | return 0; |
2585 | } /* is_pfree */ | |
2586 | ||
2587 | /* Returns a class that insn with GET_DEST(insn)=x may belong to, | |
2588 | as found by analyzing insn's expression. */ | |
2589 | ||
2590 | static int | |
2591 | may_trap_exp (x, is_store) | |
2592 | rtx x; | |
2593 | int is_store; | |
2594 | { | |
2595 | enum rtx_code code; | |
2596 | ||
2597 | if (x == 0) | |
2598 | return TRAP_FREE; | |
2599 | code = GET_CODE (x); | |
2600 | if (is_store) | |
2601 | { | |
2602 | if (code == MEM) | |
2603 | return TRAP_RISKY; | |
2604 | else | |
2605 | return TRAP_FREE; | |
2606 | } | |
2607 | if (code == MEM) | |
2608 | { | |
63de6c74 | 2609 | /* The insn uses memory: a volatile load. */ |
8c660648 JL |
2610 | if (MEM_VOLATILE_P (x)) |
2611 | return IRISKY; | |
63de6c74 | 2612 | /* An exception-free load. */ |
8c660648 JL |
2613 | if (!may_trap_p (x)) |
2614 | return IFREE; | |
63de6c74 | 2615 | /* A load with 1 base register, to be further checked. */ |
8c660648 JL |
2616 | if (CONST_BASED_ADDRESS_P (XEXP (x, 0))) |
2617 | return PFREE_CANDIDATE; | |
63de6c74 | 2618 | /* No info on the load, to be further checked. */ |
8c660648 JL |
2619 | return PRISKY_CANDIDATE; |
2620 | } | |
2621 | else | |
2622 | { | |
6f7d635c | 2623 | const char *fmt; |
8c660648 JL |
2624 | int i, insn_class = TRAP_FREE; |
2625 | ||
63de6c74 | 2626 | /* Neither store nor load, check if it may cause a trap. */ |
8c660648 JL |
2627 | if (may_trap_p (x)) |
2628 | return TRAP_RISKY; | |
63de6c74 | 2629 | /* Recursive step: walk the insn... */ |
8c660648 JL |
2630 | fmt = GET_RTX_FORMAT (code); |
2631 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
2632 | { | |
2633 | if (fmt[i] == 'e') | |
2634 | { | |
2635 | int tmp_class = may_trap_exp (XEXP (x, i), is_store); | |
2636 | insn_class = WORST_CLASS (insn_class, tmp_class); | |
2637 | } | |
2638 | else if (fmt[i] == 'E') | |
2639 | { | |
2640 | int j; | |
2641 | for (j = 0; j < XVECLEN (x, i); j++) | |
2642 | { | |
2643 | int tmp_class = may_trap_exp (XVECEXP (x, i, j), is_store); | |
2644 | insn_class = WORST_CLASS (insn_class, tmp_class); | |
2645 | if (insn_class == TRAP_RISKY || insn_class == IRISKY) | |
2646 | break; | |
2647 | } | |
2648 | } | |
2649 | if (insn_class == TRAP_RISKY || insn_class == IRISKY) | |
2650 | break; | |
2651 | } | |
2652 | return insn_class; | |
2653 | } | |
7a403706 | 2654 | } |
8c660648 JL |
2655 | |
2656 | /* Classifies insn for the purpose of verifying that it can be | |
2657 | moved speculatively, by examining it's patterns, returning: | |
2658 | TRAP_RISKY: store, or risky non-load insn (e.g. division by variable). | |
2659 | TRAP_FREE: non-load insn. | |
2660 | IFREE: load from a globaly safe location. | |
2661 | IRISKY: volatile load. | |
2662 | PFREE_CANDIDATE, PRISKY_CANDIDATE: load that need to be checked for | |
2663 | being either PFREE or PRISKY. */ | |
2664 | ||
2665 | static int | |
ac957f13 | 2666 | haifa_classify_insn (insn) |
8c660648 JL |
2667 | rtx insn; |
2668 | { | |
2669 | rtx pat = PATTERN (insn); | |
2670 | int tmp_class = TRAP_FREE; | |
2671 | int insn_class = TRAP_FREE; | |
2672 | enum rtx_code code; | |
2673 | ||
2674 | if (GET_CODE (pat) == PARALLEL) | |
2675 | { | |
2676 | int i, len = XVECLEN (pat, 0); | |
2677 | ||
2678 | for (i = len - 1; i >= 0; i--) | |
2679 | { | |
2680 | code = GET_CODE (XVECEXP (pat, 0, i)); | |
2681 | switch (code) | |
2682 | { | |
2683 | case CLOBBER: | |
63de6c74 | 2684 | /* Test if it is a 'store'. */ |
8c660648 JL |
2685 | tmp_class = may_trap_exp (XEXP (XVECEXP (pat, 0, i), 0), 1); |
2686 | break; | |
2687 | case SET: | |
63de6c74 | 2688 | /* Test if it is a store. */ |
8c660648 JL |
2689 | tmp_class = may_trap_exp (SET_DEST (XVECEXP (pat, 0, i)), 1); |
2690 | if (tmp_class == TRAP_RISKY) | |
2691 | break; | |
63de6c74 | 2692 | /* Test if it is a load. */ |
8c660648 JL |
2693 | tmp_class = |
2694 | WORST_CLASS (tmp_class, | |
7a403706 | 2695 | may_trap_exp (SET_SRC (XVECEXP (pat, 0, i)), 0)); |
e0cd0770 | 2696 | break; |
0c99ec5c | 2697 | case COND_EXEC: |
e0cd0770 JC |
2698 | case TRAP_IF: |
2699 | tmp_class = TRAP_RISKY; | |
2700 | break; | |
8c660648 JL |
2701 | default:; |
2702 | } | |
2703 | insn_class = WORST_CLASS (insn_class, tmp_class); | |
2704 | if (insn_class == TRAP_RISKY || insn_class == IRISKY) | |
2705 | break; | |
2706 | } | |
2707 | } | |
2708 | else | |
2709 | { | |
2710 | code = GET_CODE (pat); | |
2711 | switch (code) | |
2712 | { | |
2713 | case CLOBBER: | |
63de6c74 | 2714 | /* Test if it is a 'store'. */ |
8c660648 JL |
2715 | tmp_class = may_trap_exp (XEXP (pat, 0), 1); |
2716 | break; | |
2717 | case SET: | |
63de6c74 | 2718 | /* Test if it is a store. */ |
8c660648 JL |
2719 | tmp_class = may_trap_exp (SET_DEST (pat), 1); |
2720 | if (tmp_class == TRAP_RISKY) | |
2721 | break; | |
63de6c74 | 2722 | /* Test if it is a load. */ |
8c660648 JL |
2723 | tmp_class = |
2724 | WORST_CLASS (tmp_class, | |
2725 | may_trap_exp (SET_SRC (pat), 0)); | |
e0cd0770 | 2726 | break; |
0c99ec5c | 2727 | case COND_EXEC: |
e0cd0770 JC |
2728 | case TRAP_IF: |
2729 | tmp_class = TRAP_RISKY; | |
2730 | break; | |
8c660648 JL |
2731 | default:; |
2732 | } | |
2733 | insn_class = tmp_class; | |
2734 | } | |
2735 | ||
2736 | return insn_class; | |
7a403706 | 2737 | } |
8c660648 JL |
2738 | |
2739 | /* Return 1 if load_insn is prisky (i.e. if load_insn is fed by | |
2740 | a load moved speculatively, or if load_insn is protected by | |
2741 | a compare on load_insn's address). */ | |
2742 | ||
2743 | static int | |
2744 | is_prisky (load_insn, bb_src, bb_trg) | |
2745 | rtx load_insn; | |
2746 | int bb_src, bb_trg; | |
2747 | { | |
2748 | if (FED_BY_SPEC_LOAD (load_insn)) | |
2749 | return 1; | |
2750 | ||
2751 | if (LOG_LINKS (load_insn) == NULL) | |
63de6c74 | 2752 | /* Dependence may 'hide' out of the region. */ |
8c660648 JL |
2753 | return 1; |
2754 | ||
2755 | if (is_conditionally_protected (load_insn, bb_src, bb_trg)) | |
2756 | return 1; | |
2757 | ||
2758 | return 0; | |
7a403706 | 2759 | } |
8c660648 JL |
2760 | |
2761 | /* Insn is a candidate to be moved speculatively from bb_src to bb_trg. | |
2762 | Return 1 if insn is exception-free (and the motion is valid) | |
2763 | and 0 otherwise. */ | |
2764 | ||
2765 | static int | |
2766 | is_exception_free (insn, bb_src, bb_trg) | |
2767 | rtx insn; | |
2768 | int bb_src, bb_trg; | |
2769 | { | |
ac957f13 | 2770 | int insn_class = haifa_classify_insn (insn); |
8c660648 | 2771 | |
63de6c74 | 2772 | /* Handle non-load insns. */ |
8c660648 JL |
2773 | switch (insn_class) |
2774 | { | |
2775 | case TRAP_FREE: | |
2776 | return 1; | |
2777 | case TRAP_RISKY: | |
2778 | return 0; | |
2779 | default:; | |
2780 | } | |
2781 | ||
63de6c74 | 2782 | /* Handle loads. */ |
8c660648 JL |
2783 | if (!flag_schedule_speculative_load) |
2784 | return 0; | |
2785 | IS_LOAD_INSN (insn) = 1; | |
2786 | switch (insn_class) | |
2787 | { | |
2788 | case IFREE: | |
2789 | return (1); | |
2790 | case IRISKY: | |
2791 | return 0; | |
2792 | case PFREE_CANDIDATE: | |
2793 | if (is_pfree (insn, bb_src, bb_trg)) | |
2794 | return 1; | |
63de6c74 | 2795 | /* Don't 'break' here: PFREE-candidate is also PRISKY-candidate. */ |
8c660648 JL |
2796 | case PRISKY_CANDIDATE: |
2797 | if (!flag_schedule_speculative_load_dangerous | |
2798 | || is_prisky (insn, bb_src, bb_trg)) | |
2799 | return 0; | |
2800 | break; | |
2801 | default:; | |
2802 | } | |
2803 | ||
2804 | return flag_schedule_speculative_load_dangerous; | |
7a403706 | 2805 | } |
8c660648 JL |
2806 | |
2807 | /* Process an insn's memory dependencies. There are four kinds of | |
2808 | dependencies: | |
2809 | ||
2810 | (0) read dependence: read follows read | |
2811 | (1) true dependence: read follows write | |
2812 | (2) anti dependence: write follows read | |
2813 | (3) output dependence: write follows write | |
2814 | ||
2815 | We are careful to build only dependencies which actually exist, and | |
2816 | use transitivity to avoid building too many links. */ | |
2817 | \f | |
63de6c74 MH |
2818 | /* Return 1 if the pair (insn, x) is found in (LIST, LIST1), or 0 |
2819 | otherwise. */ | |
8c660648 | 2820 | |
cbb13457 | 2821 | HAIFA_INLINE static char |
8c660648 JL |
2822 | find_insn_mem_list (insn, x, list, list1) |
2823 | rtx insn, x; | |
2824 | rtx list, list1; | |
2825 | { | |
2826 | while (list) | |
2827 | { | |
2828 | if (XEXP (list, 0) == insn | |
2829 | && XEXP (list1, 0) == x) | |
2830 | return 1; | |
2831 | list = XEXP (list, 1); | |
2832 | list1 = XEXP (list1, 1); | |
2833 | } | |
2834 | return 0; | |
2835 | } | |
2836 | ||
8c660648 JL |
2837 | /* Compute the function units used by INSN. This caches the value |
2838 | returned by function_units_used. A function unit is encoded as the | |
2839 | unit number if the value is non-negative and the compliment of a | |
2840 | mask if the value is negative. A function unit index is the | |
2841 | non-negative encoding. */ | |
2842 | ||
cbb13457 | 2843 | HAIFA_INLINE static int |
8c660648 JL |
2844 | insn_unit (insn) |
2845 | rtx insn; | |
2846 | { | |
2847 | register int unit = INSN_UNIT (insn); | |
2848 | ||
2849 | if (unit == 0) | |
2850 | { | |
2851 | recog_memoized (insn); | |
2852 | ||
2853 | /* A USE insn, or something else we don't need to understand. | |
2854 | We can't pass these directly to function_units_used because it will | |
2855 | trigger a fatal error for unrecognizable insns. */ | |
2856 | if (INSN_CODE (insn) < 0) | |
2857 | unit = -1; | |
2858 | else | |
2859 | { | |
2860 | unit = function_units_used (insn); | |
2861 | /* Increment non-negative values so we can cache zero. */ | |
2862 | if (unit >= 0) | |
2863 | unit++; | |
2864 | } | |
2865 | /* We only cache 16 bits of the result, so if the value is out of | |
2866 | range, don't cache it. */ | |
2867 | if (FUNCTION_UNITS_SIZE < HOST_BITS_PER_SHORT | |
2868 | || unit >= 0 | |
77f3d48a | 2869 | || (unit & ~((1 << (HOST_BITS_PER_SHORT - 1)) - 1)) == 0) |
8c660648 JL |
2870 | INSN_UNIT (insn) = unit; |
2871 | } | |
2872 | return (unit > 0 ? unit - 1 : unit); | |
2873 | } | |
2874 | ||
2875 | /* Compute the blockage range for executing INSN on UNIT. This caches | |
2876 | the value returned by the blockage_range_function for the unit. | |
2877 | These values are encoded in an int where the upper half gives the | |
2878 | minimum value and the lower half gives the maximum value. */ | |
2879 | ||
cbb13457 | 2880 | HAIFA_INLINE static unsigned int |
8c660648 JL |
2881 | blockage_range (unit, insn) |
2882 | int unit; | |
2883 | rtx insn; | |
2884 | { | |
2885 | unsigned int blockage = INSN_BLOCKAGE (insn); | |
2886 | unsigned int range; | |
2887 | ||
79c9824e | 2888 | if ((int) UNIT_BLOCKED (blockage) != unit + 1) |
8c660648 JL |
2889 | { |
2890 | range = function_units[unit].blockage_range_function (insn); | |
2891 | /* We only cache the blockage range for one unit and then only if | |
2892 | the values fit. */ | |
2893 | if (HOST_BITS_PER_INT >= UNIT_BITS + 2 * BLOCKAGE_BITS) | |
2894 | INSN_BLOCKAGE (insn) = ENCODE_BLOCKAGE (unit + 1, range); | |
2895 | } | |
2896 | else | |
2897 | range = BLOCKAGE_RANGE (blockage); | |
2898 | ||
2899 | return range; | |
2900 | } | |
2901 | ||
2902 | /* A vector indexed by function unit instance giving the last insn to use | |
2903 | the unit. The value of the function unit instance index for unit U | |
2904 | instance I is (U + I * FUNCTION_UNITS_SIZE). */ | |
2905 | static rtx unit_last_insn[FUNCTION_UNITS_SIZE * MAX_MULTIPLICITY]; | |
2906 | ||
2907 | /* A vector indexed by function unit instance giving the minimum time when | |
2908 | the unit will unblock based on the maximum blockage cost. */ | |
2909 | static int unit_tick[FUNCTION_UNITS_SIZE * MAX_MULTIPLICITY]; | |
2910 | ||
2911 | /* A vector indexed by function unit number giving the number of insns | |
2912 | that remain to use the unit. */ | |
2913 | static int unit_n_insns[FUNCTION_UNITS_SIZE]; | |
2914 | ||
2915 | /* Reset the function unit state to the null state. */ | |
2916 | ||
2917 | static void | |
2918 | clear_units () | |
2919 | { | |
2920 | bzero ((char *) unit_last_insn, sizeof (unit_last_insn)); | |
2921 | bzero ((char *) unit_tick, sizeof (unit_tick)); | |
2922 | bzero ((char *) unit_n_insns, sizeof (unit_n_insns)); | |
2923 | } | |
2924 | ||
63de6c74 | 2925 | /* Return the issue-delay of an insn. */ |
8c660648 | 2926 | |
cbb13457 | 2927 | HAIFA_INLINE static int |
8c660648 JL |
2928 | insn_issue_delay (insn) |
2929 | rtx insn; | |
2930 | { | |
8c660648 JL |
2931 | int i, delay = 0; |
2932 | int unit = insn_unit (insn); | |
2933 | ||
63de6c74 | 2934 | /* Efficiency note: in fact, we are working 'hard' to compute a |
8c660648 JL |
2935 | value that was available in md file, and is not available in |
2936 | function_units[] structure. It would be nice to have this | |
2937 | value there, too. */ | |
2938 | if (unit >= 0) | |
2939 | { | |
2940 | if (function_units[unit].blockage_range_function && | |
2941 | function_units[unit].blockage_function) | |
2942 | delay = function_units[unit].blockage_function (insn, insn); | |
2943 | } | |
2944 | else | |
2945 | for (i = 0, unit = ~unit; unit; i++, unit >>= 1) | |
2946 | if ((unit & 1) != 0 && function_units[i].blockage_range_function | |
2947 | && function_units[i].blockage_function) | |
2948 | delay = MAX (delay, function_units[i].blockage_function (insn, insn)); | |
2949 | ||
2950 | return delay; | |
2951 | } | |
2952 | ||
2953 | /* Return the actual hazard cost of executing INSN on the unit UNIT, | |
2954 | instance INSTANCE at time CLOCK if the previous actual hazard cost | |
2955 | was COST. */ | |
2956 | ||
cbb13457 | 2957 | HAIFA_INLINE static int |
8c660648 JL |
2958 | actual_hazard_this_instance (unit, instance, insn, clock, cost) |
2959 | int unit, instance, clock, cost; | |
2960 | rtx insn; | |
2961 | { | |
63de6c74 | 2962 | int tick = unit_tick[instance]; /* Issue time of the last issued insn. */ |
8c660648 JL |
2963 | |
2964 | if (tick - clock > cost) | |
2965 | { | |
2966 | /* The scheduler is operating forward, so unit's last insn is the | |
2967 | executing insn and INSN is the candidate insn. We want a | |
2968 | more exact measure of the blockage if we execute INSN at CLOCK | |
2969 | given when we committed the execution of the unit's last insn. | |
2970 | ||
2971 | The blockage value is given by either the unit's max blockage | |
2972 | constant, blockage range function, or blockage function. Use | |
2973 | the most exact form for the given unit. */ | |
2974 | ||
2975 | if (function_units[unit].blockage_range_function) | |
2976 | { | |
2977 | if (function_units[unit].blockage_function) | |
2978 | tick += (function_units[unit].blockage_function | |
2979 | (unit_last_insn[instance], insn) | |
2980 | - function_units[unit].max_blockage); | |
2981 | else | |
2982 | tick += ((int) MAX_BLOCKAGE_COST (blockage_range (unit, insn)) | |
2983 | - function_units[unit].max_blockage); | |
2984 | } | |
2985 | if (tick - clock > cost) | |
2986 | cost = tick - clock; | |
2987 | } | |
2988 | return cost; | |
2989 | } | |
2990 | ||
2991 | /* Record INSN as having begun execution on the units encoded by UNIT at | |
2992 | time CLOCK. */ | |
2993 | ||
cbb13457 | 2994 | HAIFA_INLINE static void |
8c660648 JL |
2995 | schedule_unit (unit, insn, clock) |
2996 | int unit, clock; | |
2997 | rtx insn; | |
2998 | { | |
2999 | int i; | |
3000 | ||
3001 | if (unit >= 0) | |
3002 | { | |
3003 | int instance = unit; | |
3004 | #if MAX_MULTIPLICITY > 1 | |
3005 | /* Find the first free instance of the function unit and use that | |
3006 | one. We assume that one is free. */ | |
3007 | for (i = function_units[unit].multiplicity - 1; i > 0; i--) | |
3008 | { | |
3009 | if (!actual_hazard_this_instance (unit, instance, insn, clock, 0)) | |
3010 | break; | |
3011 | instance += FUNCTION_UNITS_SIZE; | |
3012 | } | |
3013 | #endif | |
3014 | unit_last_insn[instance] = insn; | |
3015 | unit_tick[instance] = (clock + function_units[unit].max_blockage); | |
3016 | } | |
3017 | else | |
3018 | for (i = 0, unit = ~unit; unit; i++, unit >>= 1) | |
3019 | if ((unit & 1) != 0) | |
3020 | schedule_unit (i, insn, clock); | |
3021 | } | |
3022 | ||
3023 | /* Return the actual hazard cost of executing INSN on the units encoded by | |
3024 | UNIT at time CLOCK if the previous actual hazard cost was COST. */ | |
3025 | ||
cbb13457 | 3026 | HAIFA_INLINE static int |
8c660648 JL |
3027 | actual_hazard (unit, insn, clock, cost) |
3028 | int unit, clock, cost; | |
3029 | rtx insn; | |
3030 | { | |
3031 | int i; | |
3032 | ||
3033 | if (unit >= 0) | |
3034 | { | |
3035 | /* Find the instance of the function unit with the minimum hazard. */ | |
3036 | int instance = unit; | |
3037 | int best_cost = actual_hazard_this_instance (unit, instance, insn, | |
3038 | clock, cost); | |
1eda7a81 | 3039 | #if MAX_MULTIPLICITY > 1 |
8c660648 JL |
3040 | int this_cost; |
3041 | ||
8c660648 JL |
3042 | if (best_cost > cost) |
3043 | { | |
3044 | for (i = function_units[unit].multiplicity - 1; i > 0; i--) | |
3045 | { | |
3046 | instance += FUNCTION_UNITS_SIZE; | |
3047 | this_cost = actual_hazard_this_instance (unit, instance, insn, | |
3048 | clock, cost); | |
3049 | if (this_cost < best_cost) | |
3050 | { | |
3051 | best_cost = this_cost; | |
3052 | if (this_cost <= cost) | |
3053 | break; | |
3054 | } | |
3055 | } | |
3056 | } | |
3057 | #endif | |
3058 | cost = MAX (cost, best_cost); | |
3059 | } | |
3060 | else | |
3061 | for (i = 0, unit = ~unit; unit; i++, unit >>= 1) | |
3062 | if ((unit & 1) != 0) | |
3063 | cost = actual_hazard (i, insn, clock, cost); | |
3064 | ||
3065 | return cost; | |
3066 | } | |
3067 | ||
3068 | /* Return the potential hazard cost of executing an instruction on the | |
3069 | units encoded by UNIT if the previous potential hazard cost was COST. | |
3070 | An insn with a large blockage time is chosen in preference to one | |
3071 | with a smaller time; an insn that uses a unit that is more likely | |
3072 | to be used is chosen in preference to one with a unit that is less | |
3073 | used. We are trying to minimize a subsequent actual hazard. */ | |
3074 | ||
cbb13457 | 3075 | HAIFA_INLINE static int |
8c660648 JL |
3076 | potential_hazard (unit, insn, cost) |
3077 | int unit, cost; | |
3078 | rtx insn; | |
3079 | { | |
3080 | int i, ncost; | |
3081 | unsigned int minb, maxb; | |
3082 | ||
3083 | if (unit >= 0) | |
3084 | { | |
3085 | minb = maxb = function_units[unit].max_blockage; | |
3086 | if (maxb > 1) | |
3087 | { | |
3088 | if (function_units[unit].blockage_range_function) | |
3089 | { | |
3090 | maxb = minb = blockage_range (unit, insn); | |
3091 | maxb = MAX_BLOCKAGE_COST (maxb); | |
3092 | minb = MIN_BLOCKAGE_COST (minb); | |
3093 | } | |
3094 | ||
3095 | if (maxb > 1) | |
3096 | { | |
3097 | /* Make the number of instructions left dominate. Make the | |
3098 | minimum delay dominate the maximum delay. If all these | |
3099 | are the same, use the unit number to add an arbitrary | |
3100 | ordering. Other terms can be added. */ | |
3101 | ncost = minb * 0x40 + maxb; | |
3102 | ncost *= (unit_n_insns[unit] - 1) * 0x1000 + unit; | |
3103 | if (ncost > cost) | |
3104 | cost = ncost; | |
3105 | } | |
3106 | } | |
3107 | } | |
3108 | else | |
3109 | for (i = 0, unit = ~unit; unit; i++, unit >>= 1) | |
3110 | if ((unit & 1) != 0) | |
3111 | cost = potential_hazard (i, insn, cost); | |
3112 | ||
3113 | return cost; | |
3114 | } | |
3115 | ||
3116 | /* Compute cost of executing INSN given the dependence LINK on the insn USED. | |
3117 | This is the number of cycles between instruction issue and | |
3118 | instruction results. */ | |
3119 | ||
cbb13457 | 3120 | HAIFA_INLINE static int |
8c660648 JL |
3121 | insn_cost (insn, link, used) |
3122 | rtx insn, link, used; | |
3123 | { | |
3124 | register int cost = INSN_COST (insn); | |
3125 | ||
3126 | if (cost == 0) | |
3127 | { | |
3128 | recog_memoized (insn); | |
3129 | ||
3130 | /* A USE insn, or something else we don't need to understand. | |
3131 | We can't pass these directly to result_ready_cost because it will | |
3132 | trigger a fatal error for unrecognizable insns. */ | |
3133 | if (INSN_CODE (insn) < 0) | |
3134 | { | |
3135 | INSN_COST (insn) = 1; | |
3136 | return 1; | |
3137 | } | |
3138 | else | |
3139 | { | |
3140 | cost = result_ready_cost (insn); | |
3141 | ||
3142 | if (cost < 1) | |
3143 | cost = 1; | |
3144 | ||
3145 | INSN_COST (insn) = cost; | |
3146 | } | |
3147 | } | |
3148 | ||
63de6c74 | 3149 | /* In this case estimate cost without caring how insn is used. */ |
8c660648 JL |
3150 | if (link == 0 && used == 0) |
3151 | return cost; | |
3152 | ||
3153 | /* A USE insn should never require the value used to be computed. This | |
3154 | allows the computation of a function's result and parameter values to | |
3155 | overlap the return and call. */ | |
3156 | recog_memoized (used); | |
3157 | if (INSN_CODE (used) < 0) | |
3158 | LINK_COST_FREE (link) = 1; | |
3159 | ||
3160 | /* If some dependencies vary the cost, compute the adjustment. Most | |
3161 | commonly, the adjustment is complete: either the cost is ignored | |
3162 | (in the case of an output- or anti-dependence), or the cost is | |
3163 | unchanged. These values are cached in the link as LINK_COST_FREE | |
3164 | and LINK_COST_ZERO. */ | |
3165 | ||
3166 | if (LINK_COST_FREE (link)) | |
197043f5 | 3167 | cost = 0; |
8c660648 JL |
3168 | #ifdef ADJUST_COST |
3169 | else if (!LINK_COST_ZERO (link)) | |
3170 | { | |
3171 | int ncost = cost; | |
3172 | ||
3173 | ADJUST_COST (used, link, insn, ncost); | |
197043f5 RH |
3174 | if (ncost < 1) |
3175 | { | |
3176 | LINK_COST_FREE (link) = 1; | |
3177 | ncost = 0; | |
3178 | } | |
8c660648 JL |
3179 | if (cost == ncost) |
3180 | LINK_COST_ZERO (link) = 1; | |
3181 | cost = ncost; | |
3182 | } | |
3183 | #endif | |
3184 | return cost; | |
3185 | } | |
3186 | ||
3187 | /* Compute the priority number for INSN. */ | |
3188 | ||
3189 | static int | |
3190 | priority (insn) | |
3191 | rtx insn; | |
3192 | { | |
3193 | int this_priority; | |
3194 | rtx link; | |
3195 | ||
2c3c49de | 3196 | if (! INSN_P (insn)) |
8c660648 JL |
3197 | return 0; |
3198 | ||
3199 | if ((this_priority = INSN_PRIORITY (insn)) == 0) | |
3200 | { | |
3201 | if (INSN_DEPEND (insn) == 0) | |
3202 | this_priority = insn_cost (insn, 0, 0); | |
3203 | else | |
3204 | for (link = INSN_DEPEND (insn); link; link = XEXP (link, 1)) | |
3205 | { | |
3206 | rtx next; | |
3207 | int next_priority; | |
3208 | ||
6d8ccdbb JL |
3209 | if (RTX_INTEGRATED_P (link)) |
3210 | continue; | |
3211 | ||
8c660648 JL |
3212 | next = XEXP (link, 0); |
3213 | ||
63de6c74 | 3214 | /* Critical path is meaningful in block boundaries only. */ |
c88e8206 | 3215 | if (BLOCK_NUM (next) != BLOCK_NUM (insn)) |
8c660648 JL |
3216 | continue; |
3217 | ||
3218 | next_priority = insn_cost (insn, link, next) + priority (next); | |
3219 | if (next_priority > this_priority) | |
3220 | this_priority = next_priority; | |
3221 | } | |
3222 | INSN_PRIORITY (insn) = this_priority; | |
3223 | } | |
3224 | return this_priority; | |
3225 | } | |
3226 | \f | |
8c660648 JL |
3227 | /* Remove all INSN_LISTs and EXPR_LISTs from the pending lists and add |
3228 | them to the unused_*_list variables, so that they can be reused. */ | |
3229 | ||
8c660648 JL |
3230 | static void |
3231 | free_pending_lists () | |
3232 | { | |
e1306f49 | 3233 | int bb; |
8c660648 | 3234 | |
e1306f49 BS |
3235 | for (bb = 0; bb < current_nr_blocks; bb++) |
3236 | { | |
3237 | free_INSN_LIST_list (&bb_deps[bb].pending_read_insns); | |
3238 | free_INSN_LIST_list (&bb_deps[bb].pending_write_insns); | |
3239 | free_EXPR_LIST_list (&bb_deps[bb].pending_read_mems); | |
3240 | free_EXPR_LIST_list (&bb_deps[bb].pending_write_mems); | |
8c660648 JL |
3241 | } |
3242 | } | |
3243 | ||
3244 | /* Add an INSN and MEM reference pair to a pending INSN_LIST and MEM_LIST. | |
3245 | The MEM is a memory reference contained within INSN, which we are saving | |
3246 | so that we can do memory aliasing on it. */ | |
3247 | ||
3248 | static void | |
e1306f49 BS |
3249 | add_insn_mem_dependence (deps, insn_list, mem_list, insn, mem) |
3250 | struct deps *deps; | |
8c660648 JL |
3251 | rtx *insn_list, *mem_list, insn, mem; |
3252 | { | |
3253 | register rtx link; | |
3254 | ||
ebb7b10b | 3255 | link = alloc_INSN_LIST (insn, *insn_list); |
8c660648 JL |
3256 | *insn_list = link; |
3257 | ||
ebb7b10b | 3258 | link = alloc_EXPR_LIST (VOIDmode, mem, *mem_list); |
8c660648 JL |
3259 | *mem_list = link; |
3260 | ||
e1306f49 | 3261 | deps->pending_lists_length++; |
8c660648 JL |
3262 | } |
3263 | \f | |
8c660648 JL |
3264 | /* Make a dependency between every memory reference on the pending lists |
3265 | and INSN, thus flushing the pending lists. If ONLY_WRITE, don't flush | |
3266 | the read list. */ | |
3267 | ||
3268 | static void | |
e1306f49 BS |
3269 | flush_pending_lists (deps, insn, only_write) |
3270 | struct deps *deps; | |
8c660648 JL |
3271 | rtx insn; |
3272 | int only_write; | |
3273 | { | |
3274 | rtx u; | |
3275 | rtx link; | |
3276 | ||
e1306f49 | 3277 | while (deps->pending_read_insns && ! only_write) |
8c660648 | 3278 | { |
e1306f49 BS |
3279 | add_dependence (insn, XEXP (deps->pending_read_insns, 0), |
3280 | REG_DEP_ANTI); | |
8c660648 | 3281 | |
e1306f49 BS |
3282 | link = deps->pending_read_insns; |
3283 | deps->pending_read_insns = XEXP (deps->pending_read_insns, 1); | |
5a4f6418 | 3284 | free_INSN_LIST_node (link); |
8c660648 | 3285 | |
e1306f49 BS |
3286 | link = deps->pending_read_mems; |
3287 | deps->pending_read_mems = XEXP (deps->pending_read_mems, 1); | |
5a4f6418 | 3288 | free_EXPR_LIST_node (link); |
8c660648 | 3289 | } |
e1306f49 | 3290 | while (deps->pending_write_insns) |
8c660648 | 3291 | { |
e1306f49 BS |
3292 | add_dependence (insn, XEXP (deps->pending_write_insns, 0), |
3293 | REG_DEP_ANTI); | |
8c660648 | 3294 | |
e1306f49 BS |
3295 | link = deps->pending_write_insns; |
3296 | deps->pending_write_insns = XEXP (deps->pending_write_insns, 1); | |
5a4f6418 | 3297 | free_INSN_LIST_node (link); |
8c660648 | 3298 | |
e1306f49 BS |
3299 | link = deps->pending_write_mems; |
3300 | deps->pending_write_mems = XEXP (deps->pending_write_mems, 1); | |
5a4f6418 | 3301 | free_EXPR_LIST_node (link); |
8c660648 | 3302 | } |
e1306f49 | 3303 | deps->pending_lists_length = 0; |
8c660648 | 3304 | |
63de6c74 | 3305 | /* last_pending_memory_flush is now a list of insns. */ |
e1306f49 | 3306 | for (u = deps->last_pending_memory_flush; u; u = XEXP (u, 1)) |
8c660648 JL |
3307 | add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI); |
3308 | ||
e1306f49 BS |
3309 | free_INSN_LIST_list (&deps->last_pending_memory_flush); |
3310 | deps->last_pending_memory_flush = alloc_INSN_LIST (insn, NULL_RTX); | |
8c660648 JL |
3311 | } |
3312 | ||
355fca3e AB |
3313 | /* Analyze a single SET, CLOBBER, PRE_DEC, POST_DEC, PRE_INC or POST_INC |
3314 | rtx, X, creating all dependencies generated by the write to the | |
3315 | destination of X, and reads of everything mentioned. */ | |
8c660648 JL |
3316 | |
3317 | static void | |
e1306f49 BS |
3318 | sched_analyze_1 (deps, x, insn) |
3319 | struct deps *deps; | |
8c660648 JL |
3320 | rtx x; |
3321 | rtx insn; | |
3322 | { | |
3323 | register int regno; | |
355fca3e | 3324 | register rtx dest = XEXP (x, 0); |
28c95eff | 3325 | enum rtx_code code = GET_CODE (x); |
8c660648 JL |
3326 | |
3327 | if (dest == 0) | |
3328 | return; | |
3329 | ||
c0222c21 DM |
3330 | if (GET_CODE (dest) == PARALLEL |
3331 | && GET_MODE (dest) == BLKmode) | |
3332 | { | |
3333 | register int i; | |
3334 | for (i = XVECLEN (dest, 0) - 1; i >= 0; i--) | |
e1306f49 | 3335 | sched_analyze_1 (deps, XVECEXP (dest, 0, i), insn); |
c0222c21 | 3336 | if (GET_CODE (x) == SET) |
e1306f49 | 3337 | sched_analyze_2 (deps, SET_SRC (x), insn); |
c0222c21 DM |
3338 | return; |
3339 | } | |
3340 | ||
8c660648 | 3341 | while (GET_CODE (dest) == STRICT_LOW_PART || GET_CODE (dest) == SUBREG |
7a403706 | 3342 | || GET_CODE (dest) == ZERO_EXTRACT || GET_CODE (dest) == SIGN_EXTRACT) |
8c660648 JL |
3343 | { |
3344 | if (GET_CODE (dest) == ZERO_EXTRACT || GET_CODE (dest) == SIGN_EXTRACT) | |
3345 | { | |
3346 | /* The second and third arguments are values read by this insn. */ | |
e1306f49 BS |
3347 | sched_analyze_2 (deps, XEXP (dest, 1), insn); |
3348 | sched_analyze_2 (deps, XEXP (dest, 2), insn); | |
8c660648 | 3349 | } |
355fca3e | 3350 | dest = XEXP (dest, 0); |
8c660648 JL |
3351 | } |
3352 | ||
3353 | if (GET_CODE (dest) == REG) | |
3354 | { | |
3355 | register int i; | |
3356 | ||
3357 | regno = REGNO (dest); | |
3358 | ||
3359 | /* A hard reg in a wide mode may really be multiple registers. | |
3360 | If so, mark all of them just like the first. */ | |
3361 | if (regno < FIRST_PSEUDO_REGISTER) | |
3362 | { | |
3363 | i = HARD_REGNO_NREGS (regno, GET_MODE (dest)); | |
3364 | while (--i >= 0) | |
3365 | { | |
e1306f49 | 3366 | int r = regno + i; |
8c660648 JL |
3367 | rtx u; |
3368 | ||
e1306f49 | 3369 | for (u = deps->reg_last_uses[r]; u; u = XEXP (u, 1)) |
8c660648 | 3370 | add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI); |
8c660648 | 3371 | |
e1306f49 | 3372 | for (u = deps->reg_last_sets[r]; u; u = XEXP (u, 1)) |
8c660648 JL |
3373 | add_dependence (insn, XEXP (u, 0), REG_DEP_OUTPUT); |
3374 | ||
63de6c74 MH |
3375 | /* Clobbers need not be ordered with respect to one |
3376 | another, but sets must be ordered with respect to a | |
3377 | pending clobber. */ | |
28c95eff RH |
3378 | if (code == SET) |
3379 | { | |
e1306f49 | 3380 | free_INSN_LIST_list (&deps->reg_last_uses[r]); |
7a403706 | 3381 | for (u = deps->reg_last_clobbers[r]; u; u = XEXP (u, 1)) |
28c95eff | 3382 | add_dependence (insn, XEXP (u, 0), REG_DEP_OUTPUT); |
7a403706 | 3383 | SET_REGNO_REG_SET (reg_pending_sets, r); |
28c95eff RH |
3384 | } |
3385 | else | |
e1306f49 | 3386 | SET_REGNO_REG_SET (reg_pending_clobbers, r); |
8c660648 | 3387 | |
28c95eff | 3388 | /* Function calls clobber all call_used regs. */ |
e1306f49 BS |
3389 | if (global_regs[r] || (code == SET && call_used_regs[r])) |
3390 | for (u = deps->last_function_call; u; u = XEXP (u, 1)) | |
8c660648 JL |
3391 | add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI); |
3392 | } | |
3393 | } | |
3394 | else | |
3395 | { | |
3396 | rtx u; | |
3397 | ||
e1306f49 | 3398 | for (u = deps->reg_last_uses[regno]; u; u = XEXP (u, 1)) |
8c660648 | 3399 | add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI); |
8c660648 | 3400 | |
e1306f49 | 3401 | for (u = deps->reg_last_sets[regno]; u; u = XEXP (u, 1)) |
8c660648 JL |
3402 | add_dependence (insn, XEXP (u, 0), REG_DEP_OUTPUT); |
3403 | ||
28c95eff | 3404 | if (code == SET) |
7399257b | 3405 | { |
e1306f49 BS |
3406 | free_INSN_LIST_list (&deps->reg_last_uses[regno]); |
3407 | for (u = deps->reg_last_clobbers[regno]; u; u = XEXP (u, 1)) | |
7399257b RH |
3408 | add_dependence (insn, XEXP (u, 0), REG_DEP_OUTPUT); |
3409 | SET_REGNO_REG_SET (reg_pending_sets, regno); | |
3410 | } | |
28c95eff RH |
3411 | else |
3412 | SET_REGNO_REG_SET (reg_pending_clobbers, regno); | |
8c660648 JL |
3413 | |
3414 | /* Pseudos that are REG_EQUIV to something may be replaced | |
3415 | by that during reloading. We need only add dependencies for | |
3416 | the address in the REG_EQUIV note. */ | |
3417 | if (!reload_completed | |
3418 | && reg_known_equiv_p[regno] | |
3419 | && GET_CODE (reg_known_value[regno]) == MEM) | |
e1306f49 | 3420 | sched_analyze_2 (deps, XEXP (reg_known_value[regno], 0), insn); |
8c660648 JL |
3421 | |
3422 | /* Don't let it cross a call after scheduling if it doesn't | |
3423 | already cross one. */ | |
3424 | ||
3425 | if (REG_N_CALLS_CROSSED (regno) == 0) | |
e1306f49 | 3426 | for (u = deps->last_function_call; u; u = XEXP (u, 1)) |
8c660648 JL |
3427 | add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI); |
3428 | } | |
3429 | } | |
3430 | else if (GET_CODE (dest) == MEM) | |
3431 | { | |
3432 | /* Writing memory. */ | |
3433 | ||
e1306f49 | 3434 | if (deps->pending_lists_length > 32) |
8c660648 JL |
3435 | { |
3436 | /* Flush all pending reads and writes to prevent the pending lists | |
3437 | from getting any larger. Insn scheduling runs too slowly when | |
3438 | these lists get long. The number 32 was chosen because it | |
3439 | seems like a reasonable number. When compiling GCC with itself, | |
3440 | this flush occurs 8 times for sparc, and 10 times for m88k using | |
3441 | the number 32. */ | |
e1306f49 | 3442 | flush_pending_lists (deps, insn, 0); |
8c660648 JL |
3443 | } |
3444 | else | |
3445 | { | |
3446 | rtx u; | |
3447 | rtx pending, pending_mem; | |
3448 | ||
e1306f49 BS |
3449 | pending = deps->pending_read_insns; |
3450 | pending_mem = deps->pending_read_mems; | |
8c660648 JL |
3451 | while (pending) |
3452 | { | |
87373fba RH |
3453 | if (anti_dependence (XEXP (pending_mem, 0), dest)) |
3454 | add_dependence (insn, XEXP (pending, 0), REG_DEP_ANTI); | |
8c660648 JL |
3455 | |
3456 | pending = XEXP (pending, 1); | |
3457 | pending_mem = XEXP (pending_mem, 1); | |
3458 | } | |
3459 | ||
e1306f49 BS |
3460 | pending = deps->pending_write_insns; |
3461 | pending_mem = deps->pending_write_mems; | |
8c660648 JL |
3462 | while (pending) |
3463 | { | |
87373fba RH |
3464 | if (output_dependence (XEXP (pending_mem, 0), dest)) |
3465 | add_dependence (insn, XEXP (pending, 0), REG_DEP_OUTPUT); | |
8c660648 JL |
3466 | |
3467 | pending = XEXP (pending, 1); | |
3468 | pending_mem = XEXP (pending_mem, 1); | |
3469 | } | |
3470 | ||
e1306f49 | 3471 | for (u = deps->last_pending_memory_flush; u; u = XEXP (u, 1)) |
8c660648 JL |
3472 | add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI); |
3473 | ||
e1306f49 BS |
3474 | add_insn_mem_dependence (deps, &deps->pending_write_insns, |
3475 | &deps->pending_write_mems, insn, dest); | |
8c660648 | 3476 | } |
e1306f49 | 3477 | sched_analyze_2 (deps, XEXP (dest, 0), insn); |
8c660648 JL |
3478 | } |
3479 | ||
3480 | /* Analyze reads. */ | |
3481 | if (GET_CODE (x) == SET) | |
e1306f49 | 3482 | sched_analyze_2 (deps, SET_SRC (x), insn); |
8c660648 JL |
3483 | } |
3484 | ||
3485 | /* Analyze the uses of memory and registers in rtx X in INSN. */ | |
3486 | ||
3487 | static void | |
e1306f49 BS |
3488 | sched_analyze_2 (deps, x, insn) |
3489 | struct deps *deps; | |
8c660648 JL |
3490 | rtx x; |
3491 | rtx insn; | |
3492 | { | |
3493 | register int i; | |
3494 | register int j; | |
3495 | register enum rtx_code code; | |
6f7d635c | 3496 | register const char *fmt; |
8c660648 JL |
3497 | |
3498 | if (x == 0) | |
3499 | return; | |
3500 | ||
3501 | code = GET_CODE (x); | |
3502 | ||
3503 | switch (code) | |
3504 | { | |
3505 | case CONST_INT: | |
3506 | case CONST_DOUBLE: | |
3507 | case SYMBOL_REF: | |
3508 | case CONST: | |
3509 | case LABEL_REF: | |
3510 | /* Ignore constants. Note that we must handle CONST_DOUBLE here | |
3511 | because it may have a cc0_rtx in its CONST_DOUBLE_CHAIN field, but | |
3512 | this does not mean that this insn is using cc0. */ | |
3513 | return; | |
3514 | ||
3515 | #ifdef HAVE_cc0 | |
3516 | case CC0: | |
ef384380 RH |
3517 | /* User of CC0 depends on immediately preceding insn. */ |
3518 | set_sched_group_p (insn); | |
3519 | return; | |
8c660648 JL |
3520 | #endif |
3521 | ||
3522 | case REG: | |
3523 | { | |
3524 | rtx u; | |
3525 | int regno = REGNO (x); | |
3526 | if (regno < FIRST_PSEUDO_REGISTER) | |
3527 | { | |
3528 | int i; | |
3529 | ||
3530 | i = HARD_REGNO_NREGS (regno, GET_MODE (x)); | |
3531 | while (--i >= 0) | |
3532 | { | |
e1306f49 BS |
3533 | int r = regno + i; |
3534 | deps->reg_last_uses[r] | |
3535 | = alloc_INSN_LIST (insn, deps->reg_last_uses[r]); | |
8c660648 | 3536 | |
e1306f49 | 3537 | for (u = deps->reg_last_sets[r]; u; u = XEXP (u, 1)) |
8c660648 JL |
3538 | add_dependence (insn, XEXP (u, 0), 0); |
3539 | ||
28c95eff | 3540 | /* ??? This should never happen. */ |
e1306f49 | 3541 | for (u = deps->reg_last_clobbers[r]; u; u = XEXP (u, 1)) |
28c95eff RH |
3542 | add_dependence (insn, XEXP (u, 0), 0); |
3543 | ||
e1306f49 | 3544 | if (call_used_regs[r] || global_regs[r]) |
8c660648 | 3545 | /* Function calls clobber all call_used regs. */ |
e1306f49 | 3546 | for (u = deps->last_function_call; u; u = XEXP (u, 1)) |
8c660648 JL |
3547 | add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI); |
3548 | } | |
3549 | } | |
3550 | else | |
3551 | { | |
e1306f49 BS |
3552 | deps->reg_last_uses[regno] |
3553 | = alloc_INSN_LIST (insn, deps->reg_last_uses[regno]); | |
8c660648 | 3554 | |
e1306f49 | 3555 | for (u = deps->reg_last_sets[regno]; u; u = XEXP (u, 1)) |
8c660648 JL |
3556 | add_dependence (insn, XEXP (u, 0), 0); |
3557 | ||
28c95eff | 3558 | /* ??? This should never happen. */ |
e1306f49 | 3559 | for (u = deps->reg_last_clobbers[regno]; u; u = XEXP (u, 1)) |
28c95eff RH |
3560 | add_dependence (insn, XEXP (u, 0), 0); |
3561 | ||
8c660648 JL |
3562 | /* Pseudos that are REG_EQUIV to something may be replaced |
3563 | by that during reloading. We need only add dependencies for | |
3564 | the address in the REG_EQUIV note. */ | |
3565 | if (!reload_completed | |
3566 | && reg_known_equiv_p[regno] | |
3567 | && GET_CODE (reg_known_value[regno]) == MEM) | |
e1306f49 | 3568 | sched_analyze_2 (deps, XEXP (reg_known_value[regno], 0), insn); |
8c660648 JL |
3569 | |
3570 | /* If the register does not already cross any calls, then add this | |
3571 | insn to the sched_before_next_call list so that it will still | |
3572 | not cross calls after scheduling. */ | |
3573 | if (REG_N_CALLS_CROSSED (regno) == 0) | |
e1306f49 BS |
3574 | add_dependence (deps->sched_before_next_call, insn, |
3575 | REG_DEP_ANTI); | |
8c660648 JL |
3576 | } |
3577 | return; | |
3578 | } | |
3579 | ||
3580 | case MEM: | |
3581 | { | |
3582 | /* Reading memory. */ | |
3583 | rtx u; | |
3584 | rtx pending, pending_mem; | |
3585 | ||
e1306f49 BS |
3586 | pending = deps->pending_read_insns; |
3587 | pending_mem = deps->pending_read_mems; | |
8c660648 JL |
3588 | while (pending) |
3589 | { | |
87373fba RH |
3590 | if (read_dependence (XEXP (pending_mem, 0), x)) |
3591 | add_dependence (insn, XEXP (pending, 0), REG_DEP_ANTI); | |
8c660648 JL |
3592 | |
3593 | pending = XEXP (pending, 1); | |
3594 | pending_mem = XEXP (pending_mem, 1); | |
3595 | } | |
3596 | ||
e1306f49 BS |
3597 | pending = deps->pending_write_insns; |
3598 | pending_mem = deps->pending_write_mems; | |
8c660648 JL |
3599 | while (pending) |
3600 | { | |
87373fba | 3601 | if (true_dependence (XEXP (pending_mem, 0), VOIDmode, |
7a403706 | 3602 | x, rtx_varies_p)) |
87373fba | 3603 | add_dependence (insn, XEXP (pending, 0), 0); |
8c660648 JL |
3604 | |
3605 | pending = XEXP (pending, 1); | |
3606 | pending_mem = XEXP (pending_mem, 1); | |
3607 | } | |
3608 | ||
e1306f49 | 3609 | for (u = deps->last_pending_memory_flush; u; u = XEXP (u, 1)) |
8c660648 JL |
3610 | add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI); |
3611 | ||
3612 | /* Always add these dependencies to pending_reads, since | |
3613 | this insn may be followed by a write. */ | |
e1306f49 BS |
3614 | add_insn_mem_dependence (deps, &deps->pending_read_insns, |
3615 | &deps->pending_read_mems, insn, x); | |
8c660648 JL |
3616 | |
3617 | /* Take advantage of tail recursion here. */ | |
e1306f49 | 3618 | sched_analyze_2 (deps, XEXP (x, 0), insn); |
8c660648 JL |
3619 | return; |
3620 | } | |
3621 | ||
e0cd0770 JC |
3622 | /* Force pending stores to memory in case a trap handler needs them. */ |
3623 | case TRAP_IF: | |
e1306f49 | 3624 | flush_pending_lists (deps, insn, 1); |
e0cd0770 JC |
3625 | break; |
3626 | ||
8c660648 JL |
3627 | case ASM_OPERANDS: |
3628 | case ASM_INPUT: | |
3629 | case UNSPEC_VOLATILE: | |
8c660648 JL |
3630 | { |
3631 | rtx u; | |
3632 | ||
3633 | /* Traditional and volatile asm instructions must be considered to use | |
3634 | and clobber all hard registers, all pseudo-registers and all of | |
3635 | memory. So must TRAP_IF and UNSPEC_VOLATILE operations. | |
3636 | ||
3637 | Consider for instance a volatile asm that changes the fpu rounding | |
3638 | mode. An insn should not be moved across this even if it only uses | |
3639 | pseudo-regs because it might give an incorrectly rounded result. */ | |
3640 | if (code != ASM_OPERANDS || MEM_VOLATILE_P (x)) | |
3641 | { | |
3642 | int max_reg = max_reg_num (); | |
3643 | for (i = 0; i < max_reg; i++) | |
3644 | { | |
e1306f49 | 3645 | for (u = deps->reg_last_uses[i]; u; u = XEXP (u, 1)) |
8c660648 | 3646 | add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI); |
e1306f49 | 3647 | free_INSN_LIST_list (&deps->reg_last_uses[i]); |
8c660648 | 3648 | |
e1306f49 | 3649 | for (u = deps->reg_last_sets[i]; u; u = XEXP (u, 1)) |
8c660648 | 3650 | add_dependence (insn, XEXP (u, 0), 0); |
28c95eff | 3651 | |
e1306f49 | 3652 | for (u = deps->reg_last_clobbers[i]; u; u = XEXP (u, 1)) |
28c95eff | 3653 | add_dependence (insn, XEXP (u, 0), 0); |
8c660648 JL |
3654 | } |
3655 | reg_pending_sets_all = 1; | |
3656 | ||
e1306f49 | 3657 | flush_pending_lists (deps, insn, 0); |
8c660648 JL |
3658 | } |
3659 | ||
3660 | /* For all ASM_OPERANDS, we must traverse the vector of input operands. | |
3661 | We can not just fall through here since then we would be confused | |
3662 | by the ASM_INPUT rtx inside ASM_OPERANDS, which do not indicate | |
3663 | traditional asms unlike their normal usage. */ | |
3664 | ||
3665 | if (code == ASM_OPERANDS) | |
3666 | { | |
3667 | for (j = 0; j < ASM_OPERANDS_INPUT_LENGTH (x); j++) | |
e1306f49 | 3668 | sched_analyze_2 (deps, ASM_OPERANDS_INPUT (x, j), insn); |
8c660648 JL |
3669 | return; |
3670 | } | |
3671 | break; | |
3672 | } | |
3673 | ||
3674 | case PRE_DEC: | |
3675 | case POST_DEC: | |
3676 | case PRE_INC: | |
3677 | case POST_INC: | |
3678 | /* These both read and modify the result. We must handle them as writes | |
3679 | to get proper dependencies for following instructions. We must handle | |
3680 | them as reads to get proper dependencies from this to previous | |
3681 | instructions. Thus we need to pass them to both sched_analyze_1 | |
3682 | and sched_analyze_2. We must call sched_analyze_2 first in order | |
3683 | to get the proper antecedent for the read. */ | |
e1306f49 BS |
3684 | sched_analyze_2 (deps, XEXP (x, 0), insn); |
3685 | sched_analyze_1 (deps, x, insn); | |
8c660648 | 3686 | return; |
5835e573 | 3687 | |
4b983fdc RH |
3688 | case POST_MODIFY: |
3689 | case PRE_MODIFY: | |
3690 | /* op0 = op0 + op1 */ | |
3691 | sched_analyze_2 (deps, XEXP (x, 0), insn); | |
3692 | sched_analyze_2 (deps, XEXP (x, 1), insn); | |
3693 | sched_analyze_1 (deps, x, insn); | |
3694 | return; | |
3695 | ||
5835e573 KG |
3696 | default: |
3697 | break; | |
8c660648 JL |
3698 | } |
3699 | ||
3700 | /* Other cases: walk the insn. */ | |
3701 | fmt = GET_RTX_FORMAT (code); | |
3702 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
3703 | { | |
3704 | if (fmt[i] == 'e') | |
e1306f49 | 3705 | sched_analyze_2 (deps, XEXP (x, i), insn); |
8c660648 JL |
3706 | else if (fmt[i] == 'E') |
3707 | for (j = 0; j < XVECLEN (x, i); j++) | |
e1306f49 | 3708 | sched_analyze_2 (deps, XVECEXP (x, i, j), insn); |
8c660648 JL |
3709 | } |
3710 | } | |
3711 | ||
3712 | /* Analyze an INSN with pattern X to find all dependencies. */ | |
3713 | ||
3714 | static void | |
e1306f49 BS |
3715 | sched_analyze_insn (deps, x, insn, loop_notes) |
3716 | struct deps *deps; | |
8c660648 JL |
3717 | rtx x, insn; |
3718 | rtx loop_notes; | |
3719 | { | |
3720 | register RTX_CODE code = GET_CODE (x); | |
3721 | rtx link; | |
3722 | int maxreg = max_reg_num (); | |
3723 | int i; | |
3724 | ||
0c99ec5c RH |
3725 | if (code == COND_EXEC) |
3726 | { | |
3727 | sched_analyze_2 (deps, COND_EXEC_TEST (x), insn); | |
3728 | ||
3729 | /* ??? Should be recording conditions so we reduce the number of | |
3730 | false dependancies. */ | |
3731 | x = COND_EXEC_CODE (x); | |
3732 | code = GET_CODE (x); | |
3733 | } | |
8c660648 | 3734 | if (code == SET || code == CLOBBER) |
e1306f49 | 3735 | sched_analyze_1 (deps, x, insn); |
8c660648 JL |
3736 | else if (code == PARALLEL) |
3737 | { | |
3738 | register int i; | |
3739 | for (i = XVECLEN (x, 0) - 1; i >= 0; i--) | |
3740 | { | |
0c99ec5c RH |
3741 | rtx sub = XVECEXP (x, 0, i); |
3742 | code = GET_CODE (sub); | |
3743 | ||
3744 | if (code == COND_EXEC) | |
3745 | { | |
3746 | sched_analyze_2 (deps, COND_EXEC_TEST (sub), insn); | |
3747 | sub = COND_EXEC_CODE (sub); | |
3748 | code = GET_CODE (sub); | |
3749 | } | |
8c660648 | 3750 | if (code == SET || code == CLOBBER) |
0c99ec5c | 3751 | sched_analyze_1 (deps, sub, insn); |
8c660648 | 3752 | else |
0c99ec5c | 3753 | sched_analyze_2 (deps, sub, insn); |
8c660648 JL |
3754 | } |
3755 | } | |
3756 | else | |
e1306f49 | 3757 | sched_analyze_2 (deps, x, insn); |
8c660648 JL |
3758 | |
3759 | /* Mark registers CLOBBERED or used by called function. */ | |
3760 | if (GET_CODE (insn) == CALL_INSN) | |
3761 | for (link = CALL_INSN_FUNCTION_USAGE (insn); link; link = XEXP (link, 1)) | |
3762 | { | |
3763 | if (GET_CODE (XEXP (link, 0)) == CLOBBER) | |
e1306f49 | 3764 | sched_analyze_1 (deps, XEXP (link, 0), insn); |
8c660648 | 3765 | else |
e1306f49 | 3766 | sched_analyze_2 (deps, XEXP (link, 0), insn); |
8c660648 JL |
3767 | } |
3768 | ||
1f1ed00c JL |
3769 | /* If there is a {LOOP,EHREGION}_{BEG,END} note in the middle of a basic |
3770 | block, then we must be sure that no instructions are scheduled across it. | |
8c660648 JL |
3771 | Otherwise, the reg_n_refs info (which depends on loop_depth) would |
3772 | become incorrect. */ | |
3773 | ||
3774 | if (loop_notes) | |
3775 | { | |
3776 | int max_reg = max_reg_num (); | |
1f1ed00c | 3777 | int schedule_barrier_found = 0; |
8c660648 JL |
3778 | rtx link; |
3779 | ||
1f1ed00c JL |
3780 | /* Update loop_notes with any notes from this insn. Also determine |
3781 | if any of the notes on the list correspond to instruction scheduling | |
3782 | barriers (loop, eh & setjmp notes, but not range notes. */ | |
8c660648 JL |
3783 | link = loop_notes; |
3784 | while (XEXP (link, 1)) | |
1f1ed00c | 3785 | { |
54c3cf4b JL |
3786 | if (INTVAL (XEXP (link, 0)) == NOTE_INSN_LOOP_BEG |
3787 | || INTVAL (XEXP (link, 0)) == NOTE_INSN_LOOP_END | |
3788 | || INTVAL (XEXP (link, 0)) == NOTE_INSN_EH_REGION_BEG | |
3789 | || INTVAL (XEXP (link, 0)) == NOTE_INSN_EH_REGION_END | |
3790 | || INTVAL (XEXP (link, 0)) == NOTE_INSN_SETJMP) | |
1f1ed00c JL |
3791 | schedule_barrier_found = 1; |
3792 | ||
3793 | link = XEXP (link, 1); | |
3794 | } | |
8c660648 JL |
3795 | XEXP (link, 1) = REG_NOTES (insn); |
3796 | REG_NOTES (insn) = loop_notes; | |
1f1ed00c JL |
3797 | |
3798 | /* Add dependencies if a scheduling barrier was found. */ | |
3799 | if (schedule_barrier_found) | |
3800 | { | |
3801 | for (i = 0; i < max_reg; i++) | |
3802 | { | |
3803 | rtx u; | |
e1306f49 | 3804 | for (u = deps->reg_last_uses[i]; u; u = XEXP (u, 1)) |
1f1ed00c | 3805 | add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI); |
e1306f49 | 3806 | free_INSN_LIST_list (&deps->reg_last_uses[i]); |
1f1ed00c | 3807 | |
e1306f49 | 3808 | for (u = deps->reg_last_sets[i]; u; u = XEXP (u, 1)) |
1f1ed00c | 3809 | add_dependence (insn, XEXP (u, 0), 0); |
28c95eff | 3810 | |
e1306f49 | 3811 | for (u = deps->reg_last_clobbers[i]; u; u = XEXP (u, 1)) |
28c95eff | 3812 | add_dependence (insn, XEXP (u, 0), 0); |
1f1ed00c JL |
3813 | } |
3814 | reg_pending_sets_all = 1; | |
3815 | ||
e1306f49 | 3816 | flush_pending_lists (deps, insn, 0); |
1f1ed00c JL |
3817 | } |
3818 | ||
8c660648 JL |
3819 | } |
3820 | ||
63de6c74 | 3821 | /* Accumulate clobbers until the next set so that it will be output dependent |
28c95eff | 3822 | on all of them. At the next set we can clear the clobber list, since |
63de6c74 | 3823 | subsequent sets will be output dependent on it. */ |
e1306f49 BS |
3824 | EXECUTE_IF_SET_IN_REG_SET |
3825 | (reg_pending_sets, 0, i, | |
3826 | { | |
3827 | free_INSN_LIST_list (&deps->reg_last_sets[i]); | |
3828 | free_INSN_LIST_list (&deps->reg_last_clobbers[i]); | |
3829 | deps->reg_last_sets[i] = alloc_INSN_LIST (insn, NULL_RTX); | |
3830 | }); | |
3831 | EXECUTE_IF_SET_IN_REG_SET | |
3832 | (reg_pending_clobbers, 0, i, | |
3833 | { | |
3834 | deps->reg_last_clobbers[i] | |
3835 | = alloc_INSN_LIST (insn, deps->reg_last_clobbers[i]); | |
3836 | }); | |
8c660648 | 3837 | CLEAR_REG_SET (reg_pending_sets); |
28c95eff | 3838 | CLEAR_REG_SET (reg_pending_clobbers); |
8c660648 JL |
3839 | |
3840 | if (reg_pending_sets_all) | |
3841 | { | |
3842 | for (i = 0; i < maxreg; i++) | |
ebb7b10b | 3843 | { |
e1306f49 BS |
3844 | free_INSN_LIST_list (&deps->reg_last_sets[i]); |
3845 | free_INSN_LIST_list (&deps->reg_last_clobbers[i]); | |
3846 | deps->reg_last_sets[i] = alloc_INSN_LIST (insn, NULL_RTX); | |
ebb7b10b | 3847 | } |
8c660648 JL |
3848 | |
3849 | reg_pending_sets_all = 0; | |
3850 | } | |
3851 | ||
ef384380 RH |
3852 | /* If a post-call group is still open, see if it should remain so. |
3853 | This insn must be a simple move of a hard reg to a pseudo or | |
7a403706 | 3854 | vice-versa. |
ef384380 RH |
3855 | |
3856 | We must avoid moving these insns for correctness on | |
3857 | SMALL_REGISTER_CLASS machines, and for special registers like | |
7a403706 | 3858 | PIC_OFFSET_TABLE_REGNUM. For simplicity, extend this to all |
ef384380 RH |
3859 | hard regs for all targets. */ |
3860 | ||
3861 | if (deps->in_post_call_group_p) | |
8c660648 | 3862 | { |
ef384380 RH |
3863 | rtx tmp, set = single_set (insn); |
3864 | int src_regno, dest_regno; | |
8c660648 | 3865 | |
ef384380 RH |
3866 | if (set == NULL) |
3867 | goto end_call_group; | |
8c660648 | 3868 | |
ef384380 RH |
3869 | tmp = SET_DEST (set); |
3870 | if (GET_CODE (tmp) == SUBREG) | |
3871 | tmp = SUBREG_REG (tmp); | |
3872 | if (GET_CODE (tmp) == REG) | |
3873 | dest_regno = REGNO (tmp); | |
3874 | else | |
3875 | goto end_call_group; | |
8c660648 | 3876 | |
ef384380 RH |
3877 | tmp = SET_SRC (set); |
3878 | if (GET_CODE (tmp) == SUBREG) | |
3879 | tmp = SUBREG_REG (tmp); | |
3880 | if (GET_CODE (tmp) == REG) | |
3881 | src_regno = REGNO (tmp); | |
3882 | else | |
3883 | goto end_call_group; | |
3884 | ||
3885 | if (src_regno < FIRST_PSEUDO_REGISTER | |
3886 | || dest_regno < FIRST_PSEUDO_REGISTER) | |
3887 | { | |
3888 | set_sched_group_p (insn); | |
3889 | CANT_MOVE (insn) = 1; | |
3890 | } | |
3891 | else | |
3892 | { | |
3893 | end_call_group: | |
3894 | deps->in_post_call_group_p = 0; | |
8c660648 JL |
3895 | } |
3896 | } | |
3897 | } | |
3898 | ||
3899 | /* Analyze every insn between HEAD and TAIL inclusive, creating LOG_LINKS | |
3900 | for every dependency. */ | |
3901 | ||
3902 | static void | |
e1306f49 BS |
3903 | sched_analyze (deps, head, tail) |
3904 | struct deps *deps; | |
8c660648 JL |
3905 | rtx head, tail; |
3906 | { | |
3907 | register rtx insn; | |
3908 | register rtx u; | |
3909 | rtx loop_notes = 0; | |
3910 | ||
3911 | for (insn = head;; insn = NEXT_INSN (insn)) | |
3912 | { | |
3913 | if (GET_CODE (insn) == INSN || GET_CODE (insn) == JUMP_INSN) | |
3914 | { | |
87373fba RH |
3915 | /* Clear out the stale LOG_LINKS from flow. */ |
3916 | free_INSN_LIST_list (&LOG_LINKS (insn)); | |
3917 | ||
ef384380 RH |
3918 | /* Clear out stale SCHED_GROUP_P. */ |
3919 | SCHED_GROUP_P (insn) = 0; | |
3920 | ||
63de6c74 MH |
3921 | /* Make each JUMP_INSN a scheduling barrier for memory |
3922 | references. */ | |
062ae7ed | 3923 | if (GET_CODE (insn) == JUMP_INSN) |
e1306f49 BS |
3924 | deps->last_pending_memory_flush |
3925 | = alloc_INSN_LIST (insn, deps->last_pending_memory_flush); | |
3926 | sched_analyze_insn (deps, PATTERN (insn), insn, loop_notes); | |
8c660648 JL |
3927 | loop_notes = 0; |
3928 | } | |
3929 | else if (GET_CODE (insn) == CALL_INSN) | |
3930 | { | |
3931 | rtx x; | |
3932 | register int i; | |
3933 | ||
ef384380 RH |
3934 | /* Clear out stale SCHED_GROUP_P. */ |
3935 | SCHED_GROUP_P (insn) = 0; | |
3936 | ||
8c660648 JL |
3937 | CANT_MOVE (insn) = 1; |
3938 | ||
87373fba RH |
3939 | /* Clear out the stale LOG_LINKS from flow. */ |
3940 | free_INSN_LIST_list (&LOG_LINKS (insn)); | |
3941 | ||
8c660648 JL |
3942 | /* Any instruction using a hard register which may get clobbered |
3943 | by a call needs to be marked as dependent on this call. | |
3944 | This prevents a use of a hard return reg from being moved | |
3945 | past a void call (i.e. it does not explicitly set the hard | |
3946 | return reg). */ | |
3947 | ||
3948 | /* If this call is followed by a NOTE_INSN_SETJMP, then assume that | |
3949 | all registers, not just hard registers, may be clobbered by this | |
3950 | call. */ | |
3951 | ||
3952 | /* Insn, being a CALL_INSN, magically depends on | |
3953 | `last_function_call' already. */ | |
3954 | ||
3955 | if (NEXT_INSN (insn) && GET_CODE (NEXT_INSN (insn)) == NOTE | |
3956 | && NOTE_LINE_NUMBER (NEXT_INSN (insn)) == NOTE_INSN_SETJMP) | |
3957 | { | |
3958 | int max_reg = max_reg_num (); | |
3959 | for (i = 0; i < max_reg; i++) | |
3960 | { | |
e1306f49 | 3961 | for (u = deps->reg_last_uses[i]; u; u = XEXP (u, 1)) |
8c660648 | 3962 | add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI); |
e1306f49 | 3963 | free_INSN_LIST_list (&deps->reg_last_uses[i]); |
8c660648 | 3964 | |
e1306f49 | 3965 | for (u = deps->reg_last_sets[i]; u; u = XEXP (u, 1)) |
8c660648 | 3966 | add_dependence (insn, XEXP (u, 0), 0); |
28c95eff | 3967 | |
e1306f49 | 3968 | for (u = deps->reg_last_clobbers[i]; u; u = XEXP (u, 1)) |
28c95eff | 3969 | add_dependence (insn, XEXP (u, 0), 0); |
8c660648 JL |
3970 | } |
3971 | reg_pending_sets_all = 1; | |
3972 | ||
c46a37c4 | 3973 | /* Add a pair of REG_SAVE_NOTEs which we will later |
8c660648 JL |
3974 | convert back into a NOTE_INSN_SETJMP note. See |
3975 | reemit_notes for why we use a pair of NOTEs. */ | |
c46a37c4 | 3976 | REG_NOTES (insn) = alloc_EXPR_LIST (REG_SAVE_NOTE, |
ebb7b10b RH |
3977 | GEN_INT (0), |
3978 | REG_NOTES (insn)); | |
c46a37c4 | 3979 | REG_NOTES (insn) = alloc_EXPR_LIST (REG_SAVE_NOTE, |
ebb7b10b RH |
3980 | GEN_INT (NOTE_INSN_SETJMP), |
3981 | REG_NOTES (insn)); | |
8c660648 JL |
3982 | } |
3983 | else | |
3984 | { | |
3985 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
3986 | if (call_used_regs[i] || global_regs[i]) | |
3987 | { | |
e1306f49 | 3988 | for (u = deps->reg_last_uses[i]; u; u = XEXP (u, 1)) |
8c660648 | 3989 | add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI); |
8c660648 | 3990 | |
e1306f49 | 3991 | for (u = deps->reg_last_sets[i]; u; u = XEXP (u, 1)) |
8c660648 JL |
3992 | add_dependence (insn, XEXP (u, 0), REG_DEP_ANTI); |
3993 | ||
c1cb76e9 | 3994 | SET_REGNO_REG_SET (reg_pending_clobbers, i); |
8c660648 JL |
3995 | } |
3996 | } | |
3997 | ||
3998 | /* For each insn which shouldn't cross a call, add a dependence | |
3999 | between that insn and this call insn. */ | |
e1306f49 | 4000 | x = LOG_LINKS (deps->sched_before_next_call); |
8c660648 JL |
4001 | while (x) |
4002 | { | |
4003 | add_dependence (insn, XEXP (x, 0), REG_DEP_ANTI); | |
4004 | x = XEXP (x, 1); | |
4005 | } | |
e1306f49 | 4006 | free_INSN_LIST_list (&LOG_LINKS (deps->sched_before_next_call)); |
8c660648 | 4007 | |
e1306f49 | 4008 | sched_analyze_insn (deps, PATTERN (insn), insn, loop_notes); |
8c660648 JL |
4009 | loop_notes = 0; |
4010 | ||
4011 | /* In the absence of interprocedural alias analysis, we must flush | |
4012 | all pending reads and writes, and start new dependencies starting | |
4013 | from here. But only flush writes for constant calls (which may | |
4014 | be passed a pointer to something we haven't written yet). */ | |
e1306f49 | 4015 | flush_pending_lists (deps, insn, CONST_CALL_P (insn)); |
8c660648 JL |
4016 | |
4017 | /* Depend this function call (actually, the user of this | |
4018 | function call) on all hard register clobberage. */ | |
4019 | ||
63de6c74 | 4020 | /* last_function_call is now a list of insns. */ |
e1306f49 BS |
4021 | free_INSN_LIST_list (&deps->last_function_call); |
4022 | deps->last_function_call = alloc_INSN_LIST (insn, NULL_RTX); | |
ef384380 | 4023 | |
7a403706 | 4024 | /* Before reload, begin a post-call group, so as to keep the |
ef384380 RH |
4025 | lifetimes of hard registers correct. */ |
4026 | if (! reload_completed) | |
4027 | deps->in_post_call_group_p = 1; | |
8c660648 JL |
4028 | } |
4029 | ||
7a403706 | 4030 | /* See comments on reemit_notes as to why we do this. |
63de6c74 | 4031 | ??? Actually, the reemit_notes just say what is done, not why. */ |
6dfdecdb RH |
4032 | |
4033 | else if (GET_CODE (insn) == NOTE | |
b3b42a4d | 4034 | && (NOTE_LINE_NUMBER (insn) == NOTE_INSN_RANGE_BEG |
6dfdecdb RH |
4035 | || NOTE_LINE_NUMBER (insn) == NOTE_INSN_RANGE_END)) |
4036 | { | |
c46a37c4 | 4037 | loop_notes = alloc_EXPR_LIST (REG_SAVE_NOTE, NOTE_RANGE_INFO (insn), |
6dfdecdb | 4038 | loop_notes); |
c46a37c4 | 4039 | loop_notes = alloc_EXPR_LIST (REG_SAVE_NOTE, |
6dfdecdb RH |
4040 | GEN_INT (NOTE_LINE_NUMBER (insn)), |
4041 | loop_notes); | |
4042 | } | |
8c660648 JL |
4043 | else if (GET_CODE (insn) == NOTE |
4044 | && (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG | |
4045 | || NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_END | |
4046 | || NOTE_LINE_NUMBER (insn) == NOTE_INSN_EH_REGION_BEG | |
4047 | || NOTE_LINE_NUMBER (insn) == NOTE_INSN_EH_REGION_END | |
4048 | || (NOTE_LINE_NUMBER (insn) == NOTE_INSN_SETJMP | |
4049 | && GET_CODE (PREV_INSN (insn)) != CALL_INSN))) | |
4050 | { | |
f5db61ef | 4051 | rtx rtx_region; |
7bd41ea6 | 4052 | |
1a4450c7 MM |
4053 | if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_EH_REGION_BEG |
4054 | || NOTE_LINE_NUMBER (insn) == NOTE_INSN_EH_REGION_END) | |
f5db61ef | 4055 | rtx_region = GEN_INT (NOTE_EH_HANDLER (insn)); |
7bd41ea6 | 4056 | else |
f5db61ef | 4057 | rtx_region = GEN_INT (0); |
1a4450c7 | 4058 | |
c46a37c4 | 4059 | loop_notes = alloc_EXPR_LIST (REG_SAVE_NOTE, |
f5db61ef | 4060 | rtx_region, |
7bd41ea6 | 4061 | loop_notes); |
c46a37c4 | 4062 | loop_notes = alloc_EXPR_LIST (REG_SAVE_NOTE, |
ebb7b10b RH |
4063 | GEN_INT (NOTE_LINE_NUMBER (insn)), |
4064 | loop_notes); | |
8c660648 JL |
4065 | CONST_CALL_P (loop_notes) = CONST_CALL_P (insn); |
4066 | } | |
4067 | ||
4068 | if (insn == tail) | |
4069 | return; | |
4070 | } | |
4071 | abort (); | |
4072 | } | |
4073 | \f | |
8c660648 JL |
4074 | /* Macros and functions for keeping the priority queue sorted, and |
4075 | dealing with queueing and dequeueing of instructions. */ | |
4076 | ||
4077 | #define SCHED_SORT(READY, N_READY) \ | |
4078 | do { if ((N_READY) == 2) \ | |
4079 | swap_sort (READY, N_READY); \ | |
4080 | else if ((N_READY) > 2) \ | |
4081 | qsort (READY, N_READY, sizeof (rtx), rank_for_schedule); } \ | |
4082 | while (0) | |
4083 | ||
4084 | /* Returns a positive value if x is preferred; returns a negative value if | |
4085 | y is preferred. Should never return 0, since that will make the sort | |
4086 | unstable. */ | |
4087 | ||
4088 | static int | |
4089 | rank_for_schedule (x, y) | |
e1b6684c KG |
4090 | const PTR x; |
4091 | const PTR y; | |
8c660648 | 4092 | { |
7a403706 KH |
4093 | rtx tmp = *(const rtx *) y; |
4094 | rtx tmp2 = *(const rtx *) x; | |
8c660648 | 4095 | rtx link; |
2db45993 | 4096 | int tmp_class, tmp2_class, depend_count1, depend_count2; |
8c660648 JL |
4097 | int val, priority_val, spec_val, prob_val, weight_val; |
4098 | ||
63de6c74 | 4099 | /* Prefer insn with higher priority. */ |
8c660648 JL |
4100 | priority_val = INSN_PRIORITY (tmp2) - INSN_PRIORITY (tmp); |
4101 | if (priority_val) | |
4102 | return priority_val; | |
4103 | ||
63de6c74 | 4104 | /* Prefer an insn with smaller contribution to registers-pressure. */ |
8c660648 JL |
4105 | if (!reload_completed && |
4106 | (weight_val = INSN_REG_WEIGHT (tmp) - INSN_REG_WEIGHT (tmp2))) | |
4107 | return (weight_val); | |
4108 | ||
63de6c74 | 4109 | /* Some comparison make sense in interblock scheduling only. */ |
8c660648 JL |
4110 | if (INSN_BB (tmp) != INSN_BB (tmp2)) |
4111 | { | |
63de6c74 | 4112 | /* Prefer an inblock motion on an interblock motion. */ |
8c660648 JL |
4113 | if ((INSN_BB (tmp2) == target_bb) && (INSN_BB (tmp) != target_bb)) |
4114 | return 1; | |
4115 | if ((INSN_BB (tmp) == target_bb) && (INSN_BB (tmp2) != target_bb)) | |
4116 | return -1; | |
4117 | ||
63de6c74 | 4118 | /* Prefer a useful motion on a speculative one. */ |
8c660648 JL |
4119 | if ((spec_val = IS_SPECULATIVE_INSN (tmp) - IS_SPECULATIVE_INSN (tmp2))) |
4120 | return (spec_val); | |
4121 | ||
63de6c74 | 4122 | /* Prefer a more probable (speculative) insn. */ |
8c660648 JL |
4123 | prob_val = INSN_PROBABILITY (tmp2) - INSN_PROBABILITY (tmp); |
4124 | if (prob_val) | |
4125 | return (prob_val); | |
4126 | } | |
4127 | ||
63de6c74 | 4128 | /* Compare insns based on their relation to the last-scheduled-insn. */ |
8c660648 JL |
4129 | if (last_scheduled_insn) |
4130 | { | |
4131 | /* Classify the instructions into three classes: | |
4132 | 1) Data dependent on last schedule insn. | |
4133 | 2) Anti/Output dependent on last scheduled insn. | |
4134 | 3) Independent of last scheduled insn, or has latency of one. | |
4135 | Choose the insn from the highest numbered class if different. */ | |
4136 | link = find_insn_list (tmp, INSN_DEPEND (last_scheduled_insn)); | |
4137 | if (link == 0 || insn_cost (last_scheduled_insn, link, tmp) == 1) | |
4138 | tmp_class = 3; | |
4139 | else if (REG_NOTE_KIND (link) == 0) /* Data dependence. */ | |
4140 | tmp_class = 1; | |
4141 | else | |
4142 | tmp_class = 2; | |
4143 | ||
4144 | link = find_insn_list (tmp2, INSN_DEPEND (last_scheduled_insn)); | |
4145 | if (link == 0 || insn_cost (last_scheduled_insn, link, tmp2) == 1) | |
4146 | tmp2_class = 3; | |
4147 | else if (REG_NOTE_KIND (link) == 0) /* Data dependence. */ | |
4148 | tmp2_class = 1; | |
4149 | else | |
4150 | tmp2_class = 2; | |
4151 | ||
4152 | if ((val = tmp2_class - tmp_class)) | |
4153 | return val; | |
4154 | } | |
4155 | ||
7a403706 | 4156 | /* Prefer the insn which has more later insns that depend on it. |
2db45993 JL |
4157 | This gives the scheduler more freedom when scheduling later |
4158 | instructions at the expense of added register pressure. */ | |
4159 | depend_count1 = 0; | |
4160 | for (link = INSN_DEPEND (tmp); link; link = XEXP (link, 1)) | |
4161 | depend_count1++; | |
4162 | ||
4163 | depend_count2 = 0; | |
4164 | for (link = INSN_DEPEND (tmp2); link; link = XEXP (link, 1)) | |
4165 | depend_count2++; | |
4166 | ||
4167 | val = depend_count2 - depend_count1; | |
4168 | if (val) | |
4169 | return val; | |
7a403706 | 4170 | |
8c660648 JL |
4171 | /* If insns are equally good, sort by INSN_LUID (original insn order), |
4172 | so that we make the sort stable. This minimizes instruction movement, | |
4173 | thus minimizing sched's effect on debugging and cross-jumping. */ | |
4174 | return INSN_LUID (tmp) - INSN_LUID (tmp2); | |
4175 | } | |
4176 | ||
4177 | /* Resort the array A in which only element at index N may be out of order. */ | |
4178 | ||
cbb13457 | 4179 | HAIFA_INLINE static void |
8c660648 JL |
4180 | swap_sort (a, n) |
4181 | rtx *a; | |
4182 | int n; | |
4183 | { | |
4184 | rtx insn = a[n - 1]; | |
4185 | int i = n - 2; | |
4186 | ||
4187 | while (i >= 0 && rank_for_schedule (a + i, &insn) >= 0) | |
4188 | { | |
4189 | a[i + 1] = a[i]; | |
4190 | i -= 1; | |
4191 | } | |
4192 | a[i + 1] = insn; | |
4193 | } | |
4194 | ||
4195 | static int max_priority; | |
4196 | ||
4197 | /* Add INSN to the insn queue so that it can be executed at least | |
4198 | N_CYCLES after the currently executing insn. Preserve insns | |
4199 | chain for debugging purposes. */ | |
4200 | ||
cbb13457 | 4201 | HAIFA_INLINE static void |
8c660648 JL |
4202 | queue_insn (insn, n_cycles) |
4203 | rtx insn; | |
4204 | int n_cycles; | |
4205 | { | |
4206 | int next_q = NEXT_Q_AFTER (q_ptr, n_cycles); | |
ebb7b10b | 4207 | rtx link = alloc_INSN_LIST (insn, insn_queue[next_q]); |
8c660648 JL |
4208 | insn_queue[next_q] = link; |
4209 | q_size += 1; | |
4210 | ||
4211 | if (sched_verbose >= 2) | |
4212 | { | |
4213 | fprintf (dump, ";;\t\tReady-->Q: insn %d: ", INSN_UID (insn)); | |
4214 | ||
4215 | if (INSN_BB (insn) != target_bb) | |
c88e8206 | 4216 | fprintf (dump, "(b%d) ", BLOCK_NUM (insn)); |
8c660648 JL |
4217 | |
4218 | fprintf (dump, "queued for %d cycles.\n", n_cycles); | |
4219 | } | |
4220 | ||
4221 | } | |
4222 | ||
8c660648 | 4223 | /* PREV is an insn that is ready to execute. Adjust its priority if that |
c46a37c4 RH |
4224 | will help shorten or lengthen register lifetimes as appropriate. Also |
4225 | provide a hook for the target to tweek itself. */ | |
8c660648 | 4226 | |
cbb13457 | 4227 | HAIFA_INLINE static void |
8c660648 | 4228 | adjust_priority (prev) |
c46a37c4 | 4229 | rtx prev ATTRIBUTE_UNUSED; |
8c660648 | 4230 | { |
c46a37c4 RH |
4231 | /* ??? There used to be code here to try and estimate how an insn |
4232 | affected register lifetimes, but it did it by looking at REG_DEAD | |
7a403706 | 4233 | notes, which we removed in schedule_region. Nor did it try to |
c46a37c4 | 4234 | take into account register pressure or anything useful like that. |
8c660648 | 4235 | |
c46a37c4 | 4236 | Revisit when we have a machine model to work with and not before. */ |
197043f5 | 4237 | |
8c660648 | 4238 | #ifdef ADJUST_PRIORITY |
197043f5 | 4239 | ADJUST_PRIORITY (prev); |
8c660648 | 4240 | #endif |
8c660648 JL |
4241 | } |
4242 | ||
4bdc8810 RH |
4243 | /* Clock at which the previous instruction was issued. */ |
4244 | static int last_clock_var; | |
4245 | ||
8c660648 JL |
4246 | /* INSN is the "currently executing insn". Launch each insn which was |
4247 | waiting on INSN. READY is a vector of insns which are ready to fire. | |
4248 | N_READY is the number of elements in READY. CLOCK is the current | |
4249 | cycle. */ | |
4250 | ||
4251 | static int | |
4252 | schedule_insn (insn, ready, n_ready, clock) | |
4253 | rtx insn; | |
4254 | rtx *ready; | |
4255 | int n_ready; | |
4256 | int clock; | |
4257 | { | |
4258 | rtx link; | |
4259 | int unit; | |
4260 | ||
4261 | unit = insn_unit (insn); | |
4262 | ||
4263 | if (sched_verbose >= 2) | |
4264 | { | |
63de6c74 MH |
4265 | fprintf (dump, ";;\t\t--> scheduling insn <<<%d>>> on unit ", |
4266 | INSN_UID (insn)); | |
8c660648 JL |
4267 | insn_print_units (insn); |
4268 | fprintf (dump, "\n"); | |
4269 | } | |
4270 | ||
4271 | if (sched_verbose && unit == -1) | |
4272 | visualize_no_unit (insn); | |
4273 | ||
4274 | if (MAX_BLOCKAGE > 1 || issue_rate > 1 || sched_verbose) | |
4275 | schedule_unit (unit, insn, clock); | |
4276 | ||
4277 | if (INSN_DEPEND (insn) == 0) | |
4278 | return n_ready; | |
4279 | ||
4280 | /* This is used by the function adjust_priority above. */ | |
4281 | if (n_ready > 0) | |
4282 | max_priority = MAX (INSN_PRIORITY (ready[0]), INSN_PRIORITY (insn)); | |
4283 | else | |
4284 | max_priority = INSN_PRIORITY (insn); | |
4285 | ||
4286 | for (link = INSN_DEPEND (insn); link != 0; link = XEXP (link, 1)) | |
4287 | { | |
4288 | rtx next = XEXP (link, 0); | |
4289 | int cost = insn_cost (insn, link, next); | |
4290 | ||
4291 | INSN_TICK (next) = MAX (INSN_TICK (next), clock + cost); | |
4292 | ||
4293 | if ((INSN_DEP_COUNT (next) -= 1) == 0) | |
4294 | { | |
4295 | int effective_cost = INSN_TICK (next) - clock; | |
4296 | ||
4297 | /* For speculative insns, before inserting to ready/queue, | |
63de6c74 | 4298 | check live, exception-free, and issue-delay. */ |
8c660648 JL |
4299 | if (INSN_BB (next) != target_bb |
4300 | && (!IS_VALID (INSN_BB (next)) | |
4301 | || CANT_MOVE (next) | |
4302 | || (IS_SPECULATIVE_INSN (next) | |
4303 | && (insn_issue_delay (next) > 3 | |
5835e573 | 4304 | || !check_live (next, INSN_BB (next)) |
8c660648 JL |
4305 | || !is_exception_free (next, INSN_BB (next), target_bb))))) |
4306 | continue; | |
4307 | ||
4308 | if (sched_verbose >= 2) | |
4309 | { | |
7a403706 | 4310 | fprintf (dump, ";;\t\tdependences resolved: insn %d ", |
63de6c74 | 4311 | INSN_UID (next)); |
8c660648 JL |
4312 | |
4313 | if (current_nr_blocks > 1 && INSN_BB (next) != target_bb) | |
c88e8206 | 4314 | fprintf (dump, "/b%d ", BLOCK_NUM (next)); |
8c660648 | 4315 | |
197043f5 | 4316 | if (effective_cost < 1) |
8c660648 JL |
4317 | fprintf (dump, "into ready\n"); |
4318 | else | |
4319 | fprintf (dump, "into queue with cost=%d\n", effective_cost); | |
4320 | } | |
4321 | ||
4322 | /* Adjust the priority of NEXT and either put it on the ready | |
4323 | list or queue it. */ | |
4324 | adjust_priority (next); | |
197043f5 | 4325 | if (effective_cost < 1) |
8c660648 JL |
4326 | ready[n_ready++] = next; |
4327 | else | |
4328 | queue_insn (next, effective_cost); | |
4329 | } | |
4330 | } | |
4331 | ||
7a403706 | 4332 | /* Annotate the instruction with issue information -- TImode |
4bdc8810 RH |
4333 | indicates that the instruction is expected not to be able |
4334 | to issue on the same cycle as the previous insn. A machine | |
4335 | may use this information to decide how the instruction should | |
4336 | be aligned. */ | |
4337 | if (reload_completed && issue_rate > 1) | |
4338 | { | |
4339 | PUT_MODE (insn, clock > last_clock_var ? TImode : VOIDmode); | |
4340 | last_clock_var = clock; | |
4341 | } | |
4342 | ||
8c660648 JL |
4343 | return n_ready; |
4344 | } | |
4345 | ||
63de6c74 | 4346 | /* Functions for handling of notes. */ |
8c660648 JL |
4347 | |
4348 | /* Delete notes beginning with INSN and put them in the chain | |
4349 | of notes ended by NOTE_LIST. | |
4350 | Returns the insn following the notes. */ | |
4351 | ||
4352 | static rtx | |
4353 | unlink_other_notes (insn, tail) | |
4354 | rtx insn, tail; | |
4355 | { | |
4356 | rtx prev = PREV_INSN (insn); | |
4357 | ||
4358 | while (insn != tail && GET_CODE (insn) == NOTE) | |
4359 | { | |
4360 | rtx next = NEXT_INSN (insn); | |
4361 | /* Delete the note from its current position. */ | |
4362 | if (prev) | |
4363 | NEXT_INSN (prev) = next; | |
4364 | if (next) | |
4365 | PREV_INSN (next) = prev; | |
4366 | ||
c46a37c4 | 4367 | /* See sched_analyze to see how these are handled. */ |
8c660648 JL |
4368 | if (NOTE_LINE_NUMBER (insn) != NOTE_INSN_SETJMP |
4369 | && NOTE_LINE_NUMBER (insn) != NOTE_INSN_LOOP_BEG | |
4370 | && NOTE_LINE_NUMBER (insn) != NOTE_INSN_LOOP_END | |
b3b42a4d | 4371 | && NOTE_LINE_NUMBER (insn) != NOTE_INSN_RANGE_BEG |
0dfa1860 | 4372 | && NOTE_LINE_NUMBER (insn) != NOTE_INSN_RANGE_END |
8c660648 JL |
4373 | && NOTE_LINE_NUMBER (insn) != NOTE_INSN_EH_REGION_BEG |
4374 | && NOTE_LINE_NUMBER (insn) != NOTE_INSN_EH_REGION_END) | |
4375 | { | |
4376 | /* Insert the note at the end of the notes list. */ | |
4377 | PREV_INSN (insn) = note_list; | |
4378 | if (note_list) | |
4379 | NEXT_INSN (note_list) = insn; | |
4380 | note_list = insn; | |
4381 | } | |
4382 | ||
4383 | insn = next; | |
4384 | } | |
4385 | return insn; | |
4386 | } | |
4387 | ||
4388 | /* Delete line notes beginning with INSN. Record line-number notes so | |
4389 | they can be reused. Returns the insn following the notes. */ | |
4390 | ||
4391 | static rtx | |
4392 | unlink_line_notes (insn, tail) | |
4393 | rtx insn, tail; | |
4394 | { | |
4395 | rtx prev = PREV_INSN (insn); | |
4396 | ||
4397 | while (insn != tail && GET_CODE (insn) == NOTE) | |
4398 | { | |
4399 | rtx next = NEXT_INSN (insn); | |
4400 | ||
4401 | if (write_symbols != NO_DEBUG && NOTE_LINE_NUMBER (insn) > 0) | |
4402 | { | |
4403 | /* Delete the note from its current position. */ | |
4404 | if (prev) | |
4405 | NEXT_INSN (prev) = next; | |
4406 | if (next) | |
4407 | PREV_INSN (next) = prev; | |
4408 | ||
4409 | /* Record line-number notes so they can be reused. */ | |
4410 | LINE_NOTE (insn) = insn; | |
4411 | } | |
4412 | else | |
4413 | prev = insn; | |
4414 | ||
4415 | insn = next; | |
4416 | } | |
4417 | return insn; | |
4418 | } | |
4419 | ||
4420 | /* Return the head and tail pointers of BB. */ | |
4421 | ||
cbb13457 | 4422 | HAIFA_INLINE static void |
49c3bb12 RH |
4423 | get_block_head_tail (b, headp, tailp) |
4424 | int b; | |
8c660648 JL |
4425 | rtx *headp; |
4426 | rtx *tailp; | |
4427 | { | |
4428 | ||
55d89719 TK |
4429 | rtx head; |
4430 | rtx tail; | |
8c660648 JL |
4431 | |
4432 | /* HEAD and TAIL delimit the basic block being scheduled. */ | |
3b413743 RH |
4433 | head = BLOCK_HEAD (b); |
4434 | tail = BLOCK_END (b); | |
8c660648 JL |
4435 | |
4436 | /* Don't include any notes or labels at the beginning of the | |
4437 | basic block, or notes at the ends of basic blocks. */ | |
4438 | while (head != tail) | |
4439 | { | |
4440 | if (GET_CODE (head) == NOTE) | |
4441 | head = NEXT_INSN (head); | |
4442 | else if (GET_CODE (tail) == NOTE) | |
4443 | tail = PREV_INSN (tail); | |
4444 | else if (GET_CODE (head) == CODE_LABEL) | |
4445 | head = NEXT_INSN (head); | |
4446 | else | |
4447 | break; | |
4448 | } | |
4449 | ||
4450 | *headp = head; | |
4451 | *tailp = tail; | |
4452 | } | |
4453 | ||
49c3bb12 RH |
4454 | HAIFA_INLINE static void |
4455 | get_bb_head_tail (bb, headp, tailp) | |
4456 | int bb; | |
4457 | rtx *headp; | |
4458 | rtx *tailp; | |
4459 | { | |
4460 | get_block_head_tail (BB_TO_BLOCK (bb), headp, tailp); | |
4461 | } | |
4462 | ||
8c660648 JL |
4463 | /* Delete line notes from bb. Save them so they can be later restored |
4464 | (in restore_line_notes ()). */ | |
4465 | ||
4466 | static void | |
4467 | rm_line_notes (bb) | |
4468 | int bb; | |
4469 | { | |
4470 | rtx next_tail; | |
4471 | rtx tail; | |
4472 | rtx head; | |
4473 | rtx insn; | |
4474 | ||
49c3bb12 | 4475 | get_bb_head_tail (bb, &head, &tail); |
8c660648 | 4476 | |
2c3c49de | 4477 | if (head == tail && (! INSN_P (head))) |
8c660648 JL |
4478 | return; |
4479 | ||
4480 | next_tail = NEXT_INSN (tail); | |
4481 | for (insn = head; insn != next_tail; insn = NEXT_INSN (insn)) | |
4482 | { | |
4483 | rtx prev; | |
4484 | ||
4485 | /* Farm out notes, and maybe save them in NOTE_LIST. | |
4486 | This is needed to keep the debugger from | |
4487 | getting completely deranged. */ | |
4488 | if (GET_CODE (insn) == NOTE) | |
4489 | { | |
4490 | prev = insn; | |
4491 | insn = unlink_line_notes (insn, next_tail); | |
4492 | ||
4493 | if (prev == tail) | |
4494 | abort (); | |
4495 | if (prev == head) | |
4496 | abort (); | |
4497 | if (insn == next_tail) | |
4498 | abort (); | |
4499 | } | |
4500 | } | |
4501 | } | |
4502 | ||
4503 | /* Save line number notes for each insn in bb. */ | |
4504 | ||
4505 | static void | |
4506 | save_line_notes (bb) | |
4507 | int bb; | |
4508 | { | |
4509 | rtx head, tail; | |
4510 | rtx next_tail; | |
4511 | ||
4512 | /* We must use the true line number for the first insn in the block | |
4513 | that was computed and saved at the start of this pass. We can't | |
4514 | use the current line number, because scheduling of the previous | |
4515 | block may have changed the current line number. */ | |
4516 | ||
4517 | rtx line = line_note_head[BB_TO_BLOCK (bb)]; | |
4518 | rtx insn; | |
4519 | ||
49c3bb12 | 4520 | get_bb_head_tail (bb, &head, &tail); |
8c660648 JL |
4521 | next_tail = NEXT_INSN (tail); |
4522 | ||
3b413743 | 4523 | for (insn = BLOCK_HEAD (BB_TO_BLOCK (bb)); |
8c660648 JL |
4524 | insn != next_tail; |
4525 | insn = NEXT_INSN (insn)) | |
4526 | if (GET_CODE (insn) == NOTE && NOTE_LINE_NUMBER (insn) > 0) | |
4527 | line = insn; | |
4528 | else | |
4529 | LINE_NOTE (insn) = line; | |
4530 | } | |
4531 | ||
8c660648 JL |
4532 | /* After bb was scheduled, insert line notes into the insns list. */ |
4533 | ||
4534 | static void | |
4535 | restore_line_notes (bb) | |
4536 | int bb; | |
4537 | { | |
4538 | rtx line, note, prev, new; | |
4539 | int added_notes = 0; | |
4540 | int b; | |
4541 | rtx head, next_tail, insn; | |
4542 | ||
4543 | b = BB_TO_BLOCK (bb); | |
4544 | ||
3b413743 RH |
4545 | head = BLOCK_HEAD (b); |
4546 | next_tail = NEXT_INSN (BLOCK_END (b)); | |
8c660648 JL |
4547 | |
4548 | /* Determine the current line-number. We want to know the current | |
4549 | line number of the first insn of the block here, in case it is | |
4550 | different from the true line number that was saved earlier. If | |
4551 | different, then we need a line number note before the first insn | |
4552 | of this block. If it happens to be the same, then we don't want to | |
4553 | emit another line number note here. */ | |
4554 | for (line = head; line; line = PREV_INSN (line)) | |
4555 | if (GET_CODE (line) == NOTE && NOTE_LINE_NUMBER (line) > 0) | |
4556 | break; | |
4557 | ||
4558 | /* Walk the insns keeping track of the current line-number and inserting | |
4559 | the line-number notes as needed. */ | |
4560 | for (insn = head; insn != next_tail; insn = NEXT_INSN (insn)) | |
4561 | if (GET_CODE (insn) == NOTE && NOTE_LINE_NUMBER (insn) > 0) | |
4562 | line = insn; | |
4563 | /* This used to emit line number notes before every non-deleted note. | |
4564 | However, this confuses a debugger, because line notes not separated | |
4565 | by real instructions all end up at the same address. I can find no | |
4566 | use for line number notes before other notes, so none are emitted. */ | |
4567 | else if (GET_CODE (insn) != NOTE | |
4568 | && (note = LINE_NOTE (insn)) != 0 | |
4569 | && note != line | |
4570 | && (line == 0 | |
4571 | || NOTE_LINE_NUMBER (note) != NOTE_LINE_NUMBER (line) | |
4572 | || NOTE_SOURCE_FILE (note) != NOTE_SOURCE_FILE (line))) | |
4573 | { | |
4574 | line = note; | |
4575 | prev = PREV_INSN (insn); | |
4576 | if (LINE_NOTE (note)) | |
4577 | { | |
4578 | /* Re-use the original line-number note. */ | |
4579 | LINE_NOTE (note) = 0; | |
4580 | PREV_INSN (note) = prev; | |
4581 | NEXT_INSN (prev) = note; | |
4582 | PREV_INSN (insn) = note; | |
4583 | NEXT_INSN (note) = insn; | |
4584 | } | |
4585 | else | |
4586 | { | |
4587 | added_notes++; | |
4588 | new = emit_note_after (NOTE_LINE_NUMBER (note), prev); | |
4589 | NOTE_SOURCE_FILE (new) = NOTE_SOURCE_FILE (note); | |
4590 | RTX_INTEGRATED_P (new) = RTX_INTEGRATED_P (note); | |
4591 | } | |
4592 | } | |
4593 | if (sched_verbose && added_notes) | |
4594 | fprintf (dump, ";; added %d line-number notes\n", added_notes); | |
4595 | } | |
4596 | ||
4597 | /* After scheduling the function, delete redundant line notes from the | |
4598 | insns list. */ | |
4599 | ||
4600 | static void | |
4601 | rm_redundant_line_notes () | |
4602 | { | |
4603 | rtx line = 0; | |
4604 | rtx insn = get_insns (); | |
4605 | int active_insn = 0; | |
4606 | int notes = 0; | |
4607 | ||
4608 | /* Walk the insns deleting redundant line-number notes. Many of these | |
4609 | are already present. The remainder tend to occur at basic | |
4610 | block boundaries. */ | |
4611 | for (insn = get_last_insn (); insn; insn = PREV_INSN (insn)) | |
4612 | if (GET_CODE (insn) == NOTE && NOTE_LINE_NUMBER (insn) > 0) | |
4613 | { | |
4614 | /* If there are no active insns following, INSN is redundant. */ | |
4615 | if (active_insn == 0) | |
4616 | { | |
4617 | notes++; | |
4618 | NOTE_SOURCE_FILE (insn) = 0; | |
4619 | NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED; | |
4620 | } | |
4621 | /* If the line number is unchanged, LINE is redundant. */ | |
4622 | else if (line | |
4623 | && NOTE_LINE_NUMBER (line) == NOTE_LINE_NUMBER (insn) | |
4624 | && NOTE_SOURCE_FILE (line) == NOTE_SOURCE_FILE (insn)) | |
4625 | { | |
4626 | notes++; | |
4627 | NOTE_SOURCE_FILE (line) = 0; | |
4628 | NOTE_LINE_NUMBER (line) = NOTE_INSN_DELETED; | |
4629 | line = insn; | |
4630 | } | |
4631 | else | |
4632 | line = insn; | |
4633 | active_insn = 0; | |
4634 | } | |
4635 | else if (!((GET_CODE (insn) == NOTE | |
4636 | && NOTE_LINE_NUMBER (insn) == NOTE_INSN_DELETED) | |
4637 | || (GET_CODE (insn) == INSN | |
4638 | && (GET_CODE (PATTERN (insn)) == USE | |
4639 | || GET_CODE (PATTERN (insn)) == CLOBBER)))) | |
4640 | active_insn++; | |
4641 | ||
4642 | if (sched_verbose && notes) | |
4643 | fprintf (dump, ";; deleted %d line-number notes\n", notes); | |
4644 | } | |
4645 | ||
4646 | /* Delete notes between head and tail and put them in the chain | |
4647 | of notes ended by NOTE_LIST. */ | |
4648 | ||
4649 | static void | |
4650 | rm_other_notes (head, tail) | |
4651 | rtx head; | |
4652 | rtx tail; | |
4653 | { | |
4654 | rtx next_tail; | |
4655 | rtx insn; | |
4656 | ||
2c3c49de | 4657 | if (head == tail && (! INSN_P (head))) |
8c660648 JL |
4658 | return; |
4659 | ||
4660 | next_tail = NEXT_INSN (tail); | |
4661 | for (insn = head; insn != next_tail; insn = NEXT_INSN (insn)) | |
4662 | { | |
4663 | rtx prev; | |
4664 | ||
4665 | /* Farm out notes, and maybe save them in NOTE_LIST. | |
4666 | This is needed to keep the debugger from | |
4667 | getting completely deranged. */ | |
4668 | if (GET_CODE (insn) == NOTE) | |
4669 | { | |
4670 | prev = insn; | |
4671 | ||
4672 | insn = unlink_other_notes (insn, next_tail); | |
4673 | ||
4674 | if (prev == tail) | |
4675 | abort (); | |
4676 | if (prev == head) | |
4677 | abort (); | |
4678 | if (insn == next_tail) | |
4679 | abort (); | |
4680 | } | |
4681 | } | |
4682 | } | |
4683 | ||
63de6c74 | 4684 | /* Functions for computation of registers live/usage info. */ |
8c660648 | 4685 | |
c46a37c4 | 4686 | /* Calculate INSN_REG_WEIGHT for all insns of a block. */ |
8c660648 JL |
4687 | |
4688 | static void | |
49c3bb12 | 4689 | find_insn_reg_weight (b) |
7a403706 | 4690 | int b; |
8c660648 JL |
4691 | { |
4692 | rtx insn, next_tail, head, tail; | |
8c660648 | 4693 | |
49c3bb12 | 4694 | get_block_head_tail (b, &head, &tail); |
8c660648 JL |
4695 | next_tail = NEXT_INSN (tail); |
4696 | ||
4697 | for (insn = head; insn != next_tail; insn = NEXT_INSN (insn)) | |
4698 | { | |
8c660648 | 4699 | int reg_weight = 0; |
c46a37c4 | 4700 | rtx x; |
8c660648 JL |
4701 | |
4702 | /* Handle register life information. */ | |
2c3c49de | 4703 | if (! INSN_P (insn)) |
8c660648 JL |
4704 | continue; |
4705 | ||
c46a37c4 RH |
4706 | /* Increment weight for each register born here. */ |
4707 | x = PATTERN (insn); | |
4708 | if ((GET_CODE (x) == SET || GET_CODE (x) == CLOBBER) | |
4709 | && register_operand (SET_DEST (x), VOIDmode)) | |
4710 | reg_weight++; | |
4711 | else if (GET_CODE (x) == PARALLEL) | |
8c660648 | 4712 | { |
c46a37c4 RH |
4713 | int j; |
4714 | for (j = XVECLEN (x, 0) - 1; j >= 0; j--) | |
4715 | { | |
4716 | x = XVECEXP (PATTERN (insn), 0, j); | |
4717 | if ((GET_CODE (x) == SET || GET_CODE (x) == CLOBBER) | |
4718 | && register_operand (SET_DEST (x), VOIDmode)) | |
4719 | reg_weight++; | |
4720 | } | |
8c660648 JL |
4721 | } |
4722 | ||
c46a37c4 RH |
4723 | /* Decrement weight for each register that dies here. */ |
4724 | for (x = REG_NOTES (insn); x; x = XEXP (x, 1)) | |
8c660648 | 4725 | { |
c46a37c4 RH |
4726 | if (REG_NOTE_KIND (x) == REG_DEAD |
4727 | || REG_NOTE_KIND (x) == REG_UNUSED) | |
4728 | reg_weight--; | |
8c660648 JL |
4729 | } |
4730 | ||
c46a37c4 | 4731 | INSN_REG_WEIGHT (insn) = reg_weight; |
8c660648 | 4732 | } |
8c660648 JL |
4733 | } |
4734 | ||
63de6c74 | 4735 | /* Scheduling clock, modified in schedule_block() and queue_to_ready (). */ |
8c660648 JL |
4736 | static int clock_var; |
4737 | ||
4738 | /* Move insns that became ready to fire from queue to ready list. */ | |
4739 | ||
4740 | static int | |
4741 | queue_to_ready (ready, n_ready) | |
4742 | rtx ready[]; | |
4743 | int n_ready; | |
4744 | { | |
4745 | rtx insn; | |
4746 | rtx link; | |
4747 | ||
4748 | q_ptr = NEXT_Q (q_ptr); | |
4749 | ||
4750 | /* Add all pending insns that can be scheduled without stalls to the | |
4751 | ready list. */ | |
4752 | for (link = insn_queue[q_ptr]; link; link = XEXP (link, 1)) | |
4753 | { | |
4754 | ||
4755 | insn = XEXP (link, 0); | |
4756 | q_size -= 1; | |
4757 | ||
4758 | if (sched_verbose >= 2) | |
4759 | fprintf (dump, ";;\t\tQ-->Ready: insn %d: ", INSN_UID (insn)); | |
4760 | ||
4761 | if (sched_verbose >= 2 && INSN_BB (insn) != target_bb) | |
c88e8206 | 4762 | fprintf (dump, "(b%d) ", BLOCK_NUM (insn)); |
8c660648 JL |
4763 | |
4764 | ready[n_ready++] = insn; | |
4765 | if (sched_verbose >= 2) | |
4766 | fprintf (dump, "moving to ready without stalls\n"); | |
4767 | } | |
4768 | insn_queue[q_ptr] = 0; | |
4769 | ||
4770 | /* If there are no ready insns, stall until one is ready and add all | |
4771 | of the pending insns at that point to the ready list. */ | |
4772 | if (n_ready == 0) | |
4773 | { | |
4774 | register int stalls; | |
4775 | ||
4776 | for (stalls = 1; stalls < INSN_QUEUE_SIZE; stalls++) | |
4777 | { | |
4778 | if ((link = insn_queue[NEXT_Q_AFTER (q_ptr, stalls)])) | |
4779 | { | |
4780 | for (; link; link = XEXP (link, 1)) | |
4781 | { | |
4782 | insn = XEXP (link, 0); | |
4783 | q_size -= 1; | |
4784 | ||
4785 | if (sched_verbose >= 2) | |
7a403706 KH |
4786 | fprintf (dump, ";;\t\tQ-->Ready: insn %d: ", |
4787 | INSN_UID (insn)); | |
8c660648 JL |
4788 | |
4789 | if (sched_verbose >= 2 && INSN_BB (insn) != target_bb) | |
c88e8206 | 4790 | fprintf (dump, "(b%d) ", BLOCK_NUM (insn)); |
8c660648 JL |
4791 | |
4792 | ready[n_ready++] = insn; | |
4793 | if (sched_verbose >= 2) | |
4794 | fprintf (dump, "moving to ready with %d stalls\n", stalls); | |
4795 | } | |
4796 | insn_queue[NEXT_Q_AFTER (q_ptr, stalls)] = 0; | |
4797 | ||
4798 | if (n_ready) | |
4799 | break; | |
4800 | } | |
4801 | } | |
4802 | ||
4803 | if (sched_verbose && stalls) | |
4804 | visualize_stall_cycles (BB_TO_BLOCK (target_bb), stalls); | |
4805 | q_ptr = NEXT_Q_AFTER (q_ptr, stalls); | |
4806 | clock_var += stalls; | |
4807 | } | |
4808 | return n_ready; | |
4809 | } | |
4810 | ||
63de6c74 | 4811 | /* Print the ready list for debugging purposes. Callable from debugger. */ |
8c660648 | 4812 | |
9a8b0889 | 4813 | static void |
8c660648 JL |
4814 | debug_ready_list (ready, n_ready) |
4815 | rtx ready[]; | |
4816 | int n_ready; | |
4817 | { | |
4818 | int i; | |
4819 | ||
4820 | for (i = 0; i < n_ready; i++) | |
4821 | { | |
4822 | fprintf (dump, " %d", INSN_UID (ready[i])); | |
4823 | if (current_nr_blocks > 1 && INSN_BB (ready[i]) != target_bb) | |
c88e8206 | 4824 | fprintf (dump, "/b%d", BLOCK_NUM (ready[i])); |
8c660648 JL |
4825 | } |
4826 | fprintf (dump, "\n"); | |
4827 | } | |
4828 | ||
4829 | /* Print names of units on which insn can/should execute, for debugging. */ | |
4830 | ||
4831 | static void | |
4832 | insn_print_units (insn) | |
4833 | rtx insn; | |
4834 | { | |
4835 | int i; | |
4836 | int unit = insn_unit (insn); | |
4837 | ||
4838 | if (unit == -1) | |
4839 | fprintf (dump, "none"); | |
4840 | else if (unit >= 0) | |
4841 | fprintf (dump, "%s", function_units[unit].name); | |
4842 | else | |
4843 | { | |
4844 | fprintf (dump, "["); | |
4845 | for (i = 0, unit = ~unit; unit; i++, unit >>= 1) | |
4846 | if (unit & 1) | |
4847 | { | |
4848 | fprintf (dump, "%s", function_units[i].name); | |
4849 | if (unit != 1) | |
4850 | fprintf (dump, " "); | |
4851 | } | |
4852 | fprintf (dump, "]"); | |
4853 | } | |
4854 | } | |
4855 | ||
4856 | /* MAX_VISUAL_LINES is the maximum number of lines in visualization table | |
4857 | of a basic block. If more lines are needed, table is splitted to two. | |
4858 | n_visual_lines is the number of lines printed so far for a block. | |
4859 | visual_tbl contains the block visualization info. | |
4860 | vis_no_unit holds insns in a cycle that are not mapped to any unit. */ | |
4861 | #define MAX_VISUAL_LINES 100 | |
4862 | #define INSN_LEN 30 | |
4863 | int n_visual_lines; | |
4864 | char *visual_tbl; | |
4865 | int n_vis_no_unit; | |
4866 | rtx vis_no_unit[10]; | |
4867 | ||
63de6c74 | 4868 | /* Finds units that are in use in this fuction. Required only |
8c660648 JL |
4869 | for visualization. */ |
4870 | ||
4871 | static void | |
4872 | init_target_units () | |
4873 | { | |
4874 | rtx insn; | |
4875 | int unit; | |
4876 | ||
4877 | for (insn = get_last_insn (); insn; insn = PREV_INSN (insn)) | |
4878 | { | |
2c3c49de | 4879 | if (! INSN_P (insn)) |
8c660648 JL |
4880 | continue; |
4881 | ||
4882 | unit = insn_unit (insn); | |
4883 | ||
4884 | if (unit < 0) | |
4885 | target_units |= ~unit; | |
4886 | else | |
4887 | target_units |= (1 << unit); | |
4888 | } | |
4889 | } | |
4890 | ||
63de6c74 | 4891 | /* Return the length of the visualization table. */ |
8c660648 JL |
4892 | |
4893 | static int | |
4894 | get_visual_tbl_length () | |
4895 | { | |
4896 | int unit, i; | |
4897 | int n, n1; | |
4898 | char *s; | |
4899 | ||
63de6c74 | 4900 | /* Compute length of one field in line. */ |
8f04d345 | 4901 | s = (char *) alloca (INSN_LEN + 6); |
8c660648 JL |
4902 | sprintf (s, " %33s", "uname"); |
4903 | n1 = strlen (s); | |
4904 | ||
63de6c74 | 4905 | /* Compute length of one line. */ |
8c660648 JL |
4906 | n = strlen (";; "); |
4907 | n += n1; | |
4908 | for (unit = 0; unit < FUNCTION_UNITS_SIZE; unit++) | |
4909 | if (function_units[unit].bitmask & target_units) | |
4910 | for (i = 0; i < function_units[unit].multiplicity; i++) | |
4911 | n += n1; | |
4912 | n += n1; | |
4913 | n += strlen ("\n") + 2; | |
4914 | ||
63de6c74 | 4915 | /* Compute length of visualization string. */ |
8c660648 JL |
4916 | return (MAX_VISUAL_LINES * n); |
4917 | } | |
4918 | ||
63de6c74 | 4919 | /* Init block visualization debugging info. */ |
8c660648 JL |
4920 | |
4921 | static void | |
4922 | init_block_visualization () | |
4923 | { | |
4924 | strcpy (visual_tbl, ""); | |
4925 | n_visual_lines = 0; | |
4926 | n_vis_no_unit = 0; | |
4927 | } | |
4928 | ||
3db18f59 | 4929 | #define BUF_LEN 2048 |
8c660648 | 4930 | |
459b3825 MM |
4931 | static char * |
4932 | safe_concat (buf, cur, str) | |
4933 | char *buf; | |
4934 | char *cur; | |
5f06c983 | 4935 | const char *str; |
459b3825 | 4936 | { |
63de6c74 | 4937 | char *end = buf + BUF_LEN - 2; /* Leave room for null. */ |
459b3825 MM |
4938 | int c; |
4939 | ||
4940 | if (cur > end) | |
4941 | { | |
4942 | *end = '\0'; | |
4943 | return end; | |
4944 | } | |
4945 | ||
4946 | while (cur < end && (c = *str++) != '\0') | |
4947 | *cur++ = c; | |
4948 | ||
4949 | *cur = '\0'; | |
4950 | return cur; | |
4951 | } | |
4952 | ||
63de6c74 MH |
4953 | /* This recognizes rtx, I classified as expressions. These are always |
4954 | represent some action on values or results of other expression, that | |
4955 | may be stored in objects representing values. */ | |
8c660648 JL |
4956 | |
4957 | static void | |
4958 | print_exp (buf, x, verbose) | |
4959 | char *buf; | |
4960 | rtx x; | |
4961 | int verbose; | |
4962 | { | |
459b3825 | 4963 | char tmp[BUF_LEN]; |
5f06c983 | 4964 | const char *st[4]; |
459b3825 | 4965 | char *cur = buf; |
7a403706 | 4966 | const char *fun = (char *) 0; |
5f06c983 | 4967 | const char *sep; |
459b3825 MM |
4968 | rtx op[4]; |
4969 | int i; | |
4970 | ||
4971 | for (i = 0; i < 4; i++) | |
4972 | { | |
7a403706 | 4973 | st[i] = (char *) 0; |
459b3825 MM |
4974 | op[i] = NULL_RTX; |
4975 | } | |
8c660648 JL |
4976 | |
4977 | switch (GET_CODE (x)) | |
4978 | { | |
4979 | case PLUS: | |
459b3825 | 4980 | op[0] = XEXP (x, 0); |
f4b94256 RH |
4981 | if (GET_CODE (XEXP (x, 1)) == CONST_INT |
4982 | && INTVAL (XEXP (x, 1)) < 0) | |
4983 | { | |
4984 | st[1] = "-"; | |
4985 | op[1] = GEN_INT (-INTVAL (XEXP (x, 1))); | |
4986 | } | |
4987 | else | |
4988 | { | |
4989 | st[1] = "+"; | |
4990 | op[1] = XEXP (x, 1); | |
4991 | } | |
8c660648 JL |
4992 | break; |
4993 | case LO_SUM: | |
459b3825 MM |
4994 | op[0] = XEXP (x, 0); |
4995 | st[1] = "+low("; | |
4996 | op[1] = XEXP (x, 1); | |
4997 | st[2] = ")"; | |
8c660648 JL |
4998 | break; |
4999 | case MINUS: | |
459b3825 MM |
5000 | op[0] = XEXP (x, 0); |
5001 | st[1] = "-"; | |
5002 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5003 | break; |
5004 | case COMPARE: | |
459b3825 MM |
5005 | fun = "cmp"; |
5006 | op[0] = XEXP (x, 0); | |
5007 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5008 | break; |
5009 | case NEG: | |
459b3825 MM |
5010 | st[0] = "-"; |
5011 | op[0] = XEXP (x, 0); | |
8c660648 JL |
5012 | break; |
5013 | case MULT: | |
459b3825 MM |
5014 | op[0] = XEXP (x, 0); |
5015 | st[1] = "*"; | |
5016 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5017 | break; |
5018 | case DIV: | |
459b3825 MM |
5019 | op[0] = XEXP (x, 0); |
5020 | st[1] = "/"; | |
5021 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5022 | break; |
5023 | case UDIV: | |
459b3825 MM |
5024 | fun = "udiv"; |
5025 | op[0] = XEXP (x, 0); | |
5026 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5027 | break; |
5028 | case MOD: | |
459b3825 MM |
5029 | op[0] = XEXP (x, 0); |
5030 | st[1] = "%"; | |
5031 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5032 | break; |
5033 | case UMOD: | |
459b3825 MM |
5034 | fun = "umod"; |
5035 | op[0] = XEXP (x, 0); | |
5036 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5037 | break; |
5038 | case SMIN: | |
459b3825 MM |
5039 | fun = "smin"; |
5040 | op[0] = XEXP (x, 0); | |
5041 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5042 | break; |
5043 | case SMAX: | |
459b3825 MM |
5044 | fun = "smax"; |
5045 | op[0] = XEXP (x, 0); | |
5046 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5047 | break; |
5048 | case UMIN: | |
459b3825 MM |
5049 | fun = "umin"; |
5050 | op[0] = XEXP (x, 0); | |
5051 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5052 | break; |
5053 | case UMAX: | |
459b3825 MM |
5054 | fun = "umax"; |
5055 | op[0] = XEXP (x, 0); | |
5056 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5057 | break; |
5058 | case NOT: | |
459b3825 MM |
5059 | st[0] = "!"; |
5060 | op[0] = XEXP (x, 0); | |
8c660648 JL |
5061 | break; |
5062 | case AND: | |
459b3825 MM |
5063 | op[0] = XEXP (x, 0); |
5064 | st[1] = "&"; | |
5065 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5066 | break; |
5067 | case IOR: | |
459b3825 MM |
5068 | op[0] = XEXP (x, 0); |
5069 | st[1] = "|"; | |
5070 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5071 | break; |
5072 | case XOR: | |
459b3825 MM |
5073 | op[0] = XEXP (x, 0); |
5074 | st[1] = "^"; | |
5075 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5076 | break; |
5077 | case ASHIFT: | |
459b3825 MM |
5078 | op[0] = XEXP (x, 0); |
5079 | st[1] = "<<"; | |
5080 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5081 | break; |
5082 | case LSHIFTRT: | |
459b3825 MM |
5083 | op[0] = XEXP (x, 0); |
5084 | st[1] = " 0>>"; | |
5085 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5086 | break; |
5087 | case ASHIFTRT: | |
459b3825 MM |
5088 | op[0] = XEXP (x, 0); |
5089 | st[1] = ">>"; | |
5090 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5091 | break; |
5092 | case ROTATE: | |
459b3825 MM |
5093 | op[0] = XEXP (x, 0); |
5094 | st[1] = "<-<"; | |
5095 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5096 | break; |
5097 | case ROTATERT: | |
459b3825 MM |
5098 | op[0] = XEXP (x, 0); |
5099 | st[1] = ">->"; | |
5100 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5101 | break; |
5102 | case ABS: | |
459b3825 MM |
5103 | fun = "abs"; |
5104 | op[0] = XEXP (x, 0); | |
8c660648 JL |
5105 | break; |
5106 | case SQRT: | |
459b3825 MM |
5107 | fun = "sqrt"; |
5108 | op[0] = XEXP (x, 0); | |
8c660648 JL |
5109 | break; |
5110 | case FFS: | |
459b3825 MM |
5111 | fun = "ffs"; |
5112 | op[0] = XEXP (x, 0); | |
8c660648 JL |
5113 | break; |
5114 | case EQ: | |
459b3825 MM |
5115 | op[0] = XEXP (x, 0); |
5116 | st[1] = "=="; | |
5117 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5118 | break; |
5119 | case NE: | |
459b3825 MM |
5120 | op[0] = XEXP (x, 0); |
5121 | st[1] = "!="; | |
5122 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5123 | break; |
5124 | case GT: | |
459b3825 MM |
5125 | op[0] = XEXP (x, 0); |
5126 | st[1] = ">"; | |
5127 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5128 | break; |
5129 | case GTU: | |
459b3825 MM |
5130 | fun = "gtu"; |
5131 | op[0] = XEXP (x, 0); | |
5132 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5133 | break; |
5134 | case LT: | |
459b3825 MM |
5135 | op[0] = XEXP (x, 0); |
5136 | st[1] = "<"; | |
5137 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5138 | break; |
5139 | case LTU: | |
459b3825 MM |
5140 | fun = "ltu"; |
5141 | op[0] = XEXP (x, 0); | |
5142 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5143 | break; |
5144 | case GE: | |
459b3825 MM |
5145 | op[0] = XEXP (x, 0); |
5146 | st[1] = ">="; | |
5147 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5148 | break; |
5149 | case GEU: | |
459b3825 MM |
5150 | fun = "geu"; |
5151 | op[0] = XEXP (x, 0); | |
5152 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5153 | break; |
5154 | case LE: | |
459b3825 MM |
5155 | op[0] = XEXP (x, 0); |
5156 | st[1] = "<="; | |
5157 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5158 | break; |
5159 | case LEU: | |
459b3825 MM |
5160 | fun = "leu"; |
5161 | op[0] = XEXP (x, 0); | |
5162 | op[1] = XEXP (x, 1); | |
8c660648 JL |
5163 | break; |
5164 | case SIGN_EXTRACT: | |
459b3825 MM |
5165 | fun = (verbose) ? "sign_extract" : "sxt"; |
5166 | op[0] = XEXP (x, 0); | |
5167 | op[1] = XEXP (x, 1); | |
5168 | op[2] = XEXP (x, 2); | |
8c660648 JL |
5169 | break; |
5170 | case ZERO_EXTRACT: | |
459b3825 MM |
5171 | fun = (verbose) ? "zero_extract" : "zxt"; |
5172 | op[0] = XEXP (x, 0); | |
5173 | op[1] = XEXP (x, 1); | |
5174 | op[2] = XEXP (x, 2); | |
8c660648 JL |
5175 | break; |
5176 | case SIGN_EXTEND: | |
459b3825 MM |
5177 | fun = (verbose) ? "sign_extend" : "sxn"; |
5178 | op[0] = XEXP (x, 0); | |
8c660648 JL |
5179 | break; |
5180 | case ZERO_EXTEND: | |
459b3825 MM |
5181 | fun = (verbose) ? "zero_extend" : "zxn"; |
5182 | op[0] = XEXP (x, 0); | |
8c660648 JL |
5183 | break; |
5184 | case FLOAT_EXTEND: | |
459b3825 MM |
5185 | fun = (verbose) ? "float_extend" : "fxn"; |
5186 | op[0] = XEXP (x, 0); | |
8c660648 JL |
5187 | break; |
5188 | case TRUNCATE: | |
459b3825 MM |
5189 | fun = (verbose) ? "trunc" : "trn"; |
5190 | op[0] = XEXP (x, 0); | |
8c660648 JL |
5191 | break; |
5192 | case FLOAT_TRUNCATE: | |
459b3825 MM |
5193 | fun = (verbose) ? "float_trunc" : "ftr"; |
5194 | op[0] = XEXP (x, 0); | |
8c660648 JL |
5195 | break; |
5196 | case FLOAT: | |
459b3825 MM |
5197 | fun = (verbose) ? "float" : "flt"; |
5198 | op[0] = XEXP (x, 0); | |
8c660648 JL |
5199 | break; |
5200 | case UNSIGNED_FLOAT: | |
459b3825 MM |
5201 | fun = (verbose) ? "uns_float" : "ufl"; |
5202 | op[0] = XEXP (x, 0); | |
8c660648 JL |
5203 | break; |
5204 | case FIX: | |
459b3825 MM |
5205 | fun = "fix"; |
5206 | op[0] = XEXP (x, 0); | |
8c660648 JL |
5207 | break; |
5208 | case UNSIGNED_FIX: | |
459b3825 MM |
5209 | fun = (verbose) ? "uns_fix" : "ufx"; |
5210 | op[0] = XEXP (x, 0); | |
8c660648 JL |
5211 | break; |
5212 | case PRE_DEC: | |
459b3825 MM |
5213 | st[0] = "--"; |
5214 | op[0] = XEXP (x, 0); | |
8c660648 JL |
5215 | break; |
5216 | case PRE_INC: | |
459b3825 MM |
5217 | st[0] = "++"; |
5218 | op[0] = XEXP (x, 0); | |
8c660648 JL |
5219 | break; |
5220 | case POST_DEC: | |
459b3825 MM |
5221 | op[0] = XEXP (x, 0); |
5222 | st[1] = "--"; | |
8c660648 JL |
5223 | break; |
5224 | case POST_INC: | |
459b3825 MM |
5225 | op[0] = XEXP (x, 0); |
5226 | st[1] = "++"; | |
8c660648 JL |
5227 | break; |
5228 | case CALL: | |
459b3825 MM |
5229 | st[0] = "call "; |
5230 | op[0] = XEXP (x, 0); | |
8c660648 JL |
5231 | if (verbose) |
5232 | { | |
459b3825 MM |
5233 | st[1] = " argc:"; |
5234 | op[1] = XEXP (x, 1); | |
8c660648 | 5235 | } |
8c660648 JL |
5236 | break; |
5237 | case IF_THEN_ELSE: | |
459b3825 MM |
5238 | st[0] = "{("; |
5239 | op[0] = XEXP (x, 0); | |
5240 | st[1] = ")?"; | |
5241 | op[1] = XEXP (x, 1); | |
5242 | st[2] = ":"; | |
5243 | op[2] = XEXP (x, 2); | |
5244 | st[3] = "}"; | |
8c660648 JL |
5245 | break; |
5246 | case TRAP_IF: | |
459b3825 MM |
5247 | fun = "trap_if"; |
5248 | op[0] = TRAP_CONDITION (x); | |
8c660648 JL |
5249 | break; |
5250 | case UNSPEC: | |
8c660648 JL |
5251 | case UNSPEC_VOLATILE: |
5252 | { | |
459b3825 MM |
5253 | cur = safe_concat (buf, cur, "unspec"); |
5254 | if (GET_CODE (x) == UNSPEC_VOLATILE) | |
5255 | cur = safe_concat (buf, cur, "/v"); | |
5256 | cur = safe_concat (buf, cur, "["); | |
5257 | sep = ""; | |
8c660648 JL |
5258 | for (i = 0; i < XVECLEN (x, 0); i++) |
5259 | { | |
459b3825 MM |
5260 | print_pattern (tmp, XVECEXP (x, 0, i), verbose); |
5261 | cur = safe_concat (buf, cur, sep); | |
5262 | cur = safe_concat (buf, cur, tmp); | |
5263 | sep = ","; | |
8c660648 | 5264 | } |
459b3825 MM |
5265 | cur = safe_concat (buf, cur, "] "); |
5266 | sprintf (tmp, "%d", XINT (x, 1)); | |
5267 | cur = safe_concat (buf, cur, tmp); | |
8c660648 JL |
5268 | } |
5269 | break; | |
5270 | default: | |
63de6c74 | 5271 | /* If (verbose) debug_rtx (x); */ |
53c0919d | 5272 | st[0] = GET_RTX_NAME (GET_CODE (x)); |
459b3825 MM |
5273 | break; |
5274 | } | |
5275 | ||
63de6c74 | 5276 | /* Print this as a function? */ |
459b3825 MM |
5277 | if (fun) |
5278 | { | |
5279 | cur = safe_concat (buf, cur, fun); | |
5280 | cur = safe_concat (buf, cur, "("); | |
5281 | } | |
5282 | ||
5283 | for (i = 0; i < 4; i++) | |
5284 | { | |
5285 | if (st[i]) | |
5286 | cur = safe_concat (buf, cur, st[i]); | |
5287 | ||
5288 | if (op[i]) | |
5289 | { | |
5290 | if (fun && i != 0) | |
5291 | cur = safe_concat (buf, cur, ","); | |
5292 | ||
5293 | print_value (tmp, op[i], verbose); | |
5294 | cur = safe_concat (buf, cur, tmp); | |
5295 | } | |
8c660648 | 5296 | } |
459b3825 MM |
5297 | |
5298 | if (fun) | |
5299 | cur = safe_concat (buf, cur, ")"); | |
5300 | } /* print_exp */ | |
8c660648 | 5301 | |
63de6c74 MH |
5302 | /* Prints rtxes, I customly classified as values. They're constants, |
5303 | registers, labels, symbols and memory accesses. */ | |
8c660648 JL |
5304 | |
5305 | static void | |
5306 | print_value (buf, x, verbose) | |
5307 | char *buf; | |
5308 | rtx x; | |
5309 | int verbose; | |
5310 | { | |
5311 | char t[BUF_LEN]; | |
459b3825 | 5312 | char *cur = buf; |
8c660648 JL |
5313 | |
5314 | switch (GET_CODE (x)) | |
5315 | { | |
5316 | case CONST_INT: | |
f4b94256 | 5317 | sprintf (t, HOST_WIDE_INT_PRINT_HEX, INTVAL (x)); |
459b3825 | 5318 | cur = safe_concat (buf, cur, t); |
8c660648 JL |
5319 | break; |
5320 | case CONST_DOUBLE: | |
7a403706 | 5321 | sprintf (t, "<0x%lx,0x%lx>", (long) XWINT (x, 2), (long) XWINT (x, 3)); |
459b3825 | 5322 | cur = safe_concat (buf, cur, t); |
8c660648 JL |
5323 | break; |
5324 | case CONST_STRING: | |
459b3825 MM |
5325 | cur = safe_concat (buf, cur, "\""); |
5326 | cur = safe_concat (buf, cur, XSTR (x, 0)); | |
5327 | cur = safe_concat (buf, cur, "\""); | |
8c660648 JL |
5328 | break; |
5329 | case SYMBOL_REF: | |
459b3825 MM |
5330 | cur = safe_concat (buf, cur, "`"); |
5331 | cur = safe_concat (buf, cur, XSTR (x, 0)); | |
5332 | cur = safe_concat (buf, cur, "'"); | |
8c660648 JL |
5333 | break; |
5334 | case LABEL_REF: | |
459b3825 MM |
5335 | sprintf (t, "L%d", INSN_UID (XEXP (x, 0))); |
5336 | cur = safe_concat (buf, cur, t); | |
8c660648 JL |
5337 | break; |
5338 | case CONST: | |
459b3825 MM |
5339 | print_value (t, XEXP (x, 0), verbose); |
5340 | cur = safe_concat (buf, cur, "const("); | |
5341 | cur = safe_concat (buf, cur, t); | |
5342 | cur = safe_concat (buf, cur, ")"); | |
8c660648 JL |
5343 | break; |
5344 | case HIGH: | |
459b3825 MM |
5345 | print_value (t, XEXP (x, 0), verbose); |
5346 | cur = safe_concat (buf, cur, "high("); | |
5347 | cur = safe_concat (buf, cur, t); | |
5348 | cur = safe_concat (buf, cur, ")"); | |
8c660648 JL |
5349 | break; |
5350 | case REG: | |
459b3825 MM |
5351 | if (REGNO (x) < FIRST_PSEUDO_REGISTER) |
5352 | { | |
7a403706 | 5353 | int c = reg_names[REGNO (x)][0]; |
459b3825 MM |
5354 | if (c >= '0' && c <= '9') |
5355 | cur = safe_concat (buf, cur, "%"); | |
5356 | ||
7a403706 | 5357 | cur = safe_concat (buf, cur, reg_names[REGNO (x)]); |
459b3825 | 5358 | } |
8c660648 | 5359 | else |
459b3825 MM |
5360 | { |
5361 | sprintf (t, "r%d", REGNO (x)); | |
5362 | cur = safe_concat (buf, cur, t); | |
5363 | } | |
8c660648 JL |
5364 | break; |
5365 | case SUBREG: | |
459b3825 MM |
5366 | print_value (t, SUBREG_REG (x), verbose); |
5367 | cur = safe_concat (buf, cur, t); | |
6b879bcc | 5368 | sprintf (t, "#%d", SUBREG_WORD (x)); |
459b3825 | 5369 | cur = safe_concat (buf, cur, t); |
8c660648 JL |
5370 | break; |
5371 | case SCRATCH: | |
459b3825 | 5372 | cur = safe_concat (buf, cur, "scratch"); |
8c660648 JL |
5373 | break; |
5374 | case CC0: | |
459b3825 | 5375 | cur = safe_concat (buf, cur, "cc0"); |
8c660648 JL |
5376 | break; |
5377 | case PC: | |
459b3825 | 5378 | cur = safe_concat (buf, cur, "pc"); |
8c660648 JL |
5379 | break; |
5380 | case MEM: | |
5381 | print_value (t, XEXP (x, 0), verbose); | |
459b3825 MM |
5382 | cur = safe_concat (buf, cur, "["); |
5383 | cur = safe_concat (buf, cur, t); | |
5384 | cur = safe_concat (buf, cur, "]"); | |
8c660648 JL |
5385 | break; |
5386 | default: | |
459b3825 MM |
5387 | print_exp (t, x, verbose); |
5388 | cur = safe_concat (buf, cur, t); | |
5389 | break; | |
8c660648 JL |
5390 | } |
5391 | } /* print_value */ | |
5392 | ||
63de6c74 | 5393 | /* The next step in insn detalization, its pattern recognition. */ |
8c660648 JL |
5394 | |
5395 | static void | |
5396 | print_pattern (buf, x, verbose) | |
5397 | char *buf; | |
5398 | rtx x; | |
5399 | int verbose; | |
5400 | { | |
5401 | char t1[BUF_LEN], t2[BUF_LEN], t3[BUF_LEN]; | |
5402 | ||
5403 | switch (GET_CODE (x)) | |
5404 | { | |
5405 | case SET: | |
5406 | print_value (t1, SET_DEST (x), verbose); | |
5407 | print_value (t2, SET_SRC (x), verbose); | |
5408 | sprintf (buf, "%s=%s", t1, t2); | |
5409 | break; | |
5410 | case RETURN: | |
5411 | sprintf (buf, "return"); | |
5412 | break; | |
5413 | case CALL: | |
5414 | print_exp (buf, x, verbose); | |
5415 | break; | |
5416 | case CLOBBER: | |
5417 | print_value (t1, XEXP (x, 0), verbose); | |
5418 | sprintf (buf, "clobber %s", t1); | |
5419 | break; | |
5420 | case USE: | |
5421 | print_value (t1, XEXP (x, 0), verbose); | |
5422 | sprintf (buf, "use %s", t1); | |
5423 | break; | |
0c99ec5c RH |
5424 | case COND_EXEC: |
5425 | print_value (t1, COND_EXEC_CODE (x), verbose); | |
5426 | print_value (t2, COND_EXEC_TEST (x), verbose); | |
5427 | sprintf (buf, "cond_exec %s %s", t1, t2); | |
5428 | break; | |
8c660648 JL |
5429 | case PARALLEL: |
5430 | { | |
5431 | int i; | |
5432 | ||
5433 | sprintf (t1, "{"); | |
5434 | for (i = 0; i < XVECLEN (x, 0); i++) | |
5435 | { | |
5436 | print_pattern (t2, XVECEXP (x, 0, i), verbose); | |
5437 | sprintf (t3, "%s%s;", t1, t2); | |
5438 | strcpy (t1, t3); | |
5439 | } | |
5440 | sprintf (buf, "%s}", t1); | |
5441 | } | |
5442 | break; | |
5443 | case SEQUENCE: | |
5444 | { | |
5445 | int i; | |
5446 | ||
5447 | sprintf (t1, "%%{"); | |
5448 | for (i = 0; i < XVECLEN (x, 0); i++) | |
5449 | { | |
5450 | print_insn (t2, XVECEXP (x, 0, i), verbose); | |
5451 | sprintf (t3, "%s%s;", t1, t2); | |
5452 | strcpy (t1, t3); | |
5453 | } | |
5454 | sprintf (buf, "%s%%}", t1); | |
5455 | } | |
5456 | break; | |
5457 | case ASM_INPUT: | |
c4fa3460 | 5458 | sprintf (buf, "asm {%s}", XSTR (x, 0)); |
8c660648 JL |
5459 | break; |
5460 | case ADDR_VEC: | |
5461 | break; | |
5462 | case ADDR_DIFF_VEC: | |
5463 | print_value (buf, XEXP (x, 0), verbose); | |
5464 | break; | |
5465 | case TRAP_IF: | |
5466 | print_value (t1, TRAP_CONDITION (x), verbose); | |
5467 | sprintf (buf, "trap_if %s", t1); | |
5468 | break; | |
5469 | case UNSPEC: | |
5470 | { | |
5471 | int i; | |
5472 | ||
5473 | sprintf (t1, "unspec{"); | |
5474 | for (i = 0; i < XVECLEN (x, 0); i++) | |
5475 | { | |
5476 | print_pattern (t2, XVECEXP (x, 0, i), verbose); | |
5477 | sprintf (t3, "%s%s;", t1, t2); | |
5478 | strcpy (t1, t3); | |
5479 | } | |
5480 | sprintf (buf, "%s}", t1); | |
5481 | } | |
5482 | break; | |
5483 | case UNSPEC_VOLATILE: | |
5484 | { | |
5485 | int i; | |
5486 | ||
5487 | sprintf (t1, "unspec/v{"); | |
5488 | for (i = 0; i < XVECLEN (x, 0); i++) | |
5489 | { | |
5490 | print_pattern (t2, XVECEXP (x, 0, i), verbose); | |
5491 | sprintf (t3, "%s%s;", t1, t2); | |
5492 | strcpy (t1, t3); | |
5493 | } | |
5494 | sprintf (buf, "%s}", t1); | |
5495 | } | |
5496 | break; | |
5497 | default: | |
5498 | print_value (buf, x, verbose); | |
5499 | } | |
5500 | } /* print_pattern */ | |
5501 | ||
5502 | /* This is the main function in rtl visualization mechanism. It | |
5503 | accepts an rtx and tries to recognize it as an insn, then prints it | |
63de6c74 MH |
5504 | properly in human readable form, resembling assembler mnemonics. |
5505 | For every insn it prints its UID and BB the insn belongs too. | |
5506 | (Probably the last "option" should be extended somehow, since it | |
5507 | depends now on sched.c inner variables ...) */ | |
8c660648 JL |
5508 | |
5509 | static void | |
5510 | print_insn (buf, x, verbose) | |
5511 | char *buf; | |
5512 | rtx x; | |
5513 | int verbose; | |
5514 | { | |
5515 | char t[BUF_LEN]; | |
5516 | rtx insn = x; | |
5517 | ||
5518 | switch (GET_CODE (x)) | |
5519 | { | |
5520 | case INSN: | |
5521 | print_pattern (t, PATTERN (x), verbose); | |
5522 | if (verbose) | |
5523 | sprintf (buf, "b%d: i% 4d: %s", INSN_BB (x), | |
5524 | INSN_UID (x), t); | |
5525 | else | |
5526 | sprintf (buf, "%-4d %s", INSN_UID (x), t); | |
5527 | break; | |
5528 | case JUMP_INSN: | |
5529 | print_pattern (t, PATTERN (x), verbose); | |
5530 | if (verbose) | |
5531 | sprintf (buf, "b%d: i% 4d: jump %s", INSN_BB (x), | |
5532 | INSN_UID (x), t); | |
5533 | else | |
5534 | sprintf (buf, "%-4d %s", INSN_UID (x), t); | |
5535 | break; | |
5536 | case CALL_INSN: | |
5537 | x = PATTERN (insn); | |
5538 | if (GET_CODE (x) == PARALLEL) | |
5539 | { | |
5540 | x = XVECEXP (x, 0, 0); | |
5541 | print_pattern (t, x, verbose); | |
5542 | } | |
5543 | else | |
5544 | strcpy (t, "call <...>"); | |
5545 | if (verbose) | |
5546 | sprintf (buf, "b%d: i% 4d: %s", INSN_BB (insn), | |
5547 | INSN_UID (insn), t); | |
5548 | else | |
5549 | sprintf (buf, "%-4d %s", INSN_UID (insn), t); | |
5550 | break; | |
5551 | case CODE_LABEL: | |
5552 | sprintf (buf, "L%d:", INSN_UID (x)); | |
5553 | break; | |
5554 | case BARRIER: | |
5555 | sprintf (buf, "i% 4d: barrier", INSN_UID (x)); | |
5556 | break; | |
5557 | case NOTE: | |
5558 | if (NOTE_LINE_NUMBER (x) > 0) | |
5559 | sprintf (buf, "%4d note \"%s\" %d", INSN_UID (x), | |
5560 | NOTE_SOURCE_FILE (x), NOTE_LINE_NUMBER (x)); | |
5561 | else | |
5562 | sprintf (buf, "%4d %s", INSN_UID (x), | |
5563 | GET_NOTE_INSN_NAME (NOTE_LINE_NUMBER (x))); | |
5564 | break; | |
5565 | default: | |
5566 | if (verbose) | |
5567 | { | |
5568 | sprintf (buf, "Not an INSN at all\n"); | |
5569 | debug_rtx (x); | |
5570 | } | |
5571 | else | |
5572 | sprintf (buf, "i%-4d <What?>", INSN_UID (x)); | |
5573 | } | |
5574 | } /* print_insn */ | |
5575 | ||
63de6c74 | 5576 | /* Print visualization debugging info. */ |
8c660648 JL |
5577 | |
5578 | static void | |
5579 | print_block_visualization (b, s) | |
5580 | int b; | |
5f06c983 | 5581 | const char *s; |
8c660648 JL |
5582 | { |
5583 | int unit, i; | |
8c660648 | 5584 | |
63de6c74 | 5585 | /* Print header. */ |
8c660648 JL |
5586 | fprintf (dump, "\n;; ==================== scheduling visualization for block %d %s \n", b, s); |
5587 | ||
63de6c74 | 5588 | /* Print names of units. */ |
2f308fec | 5589 | fprintf (dump, ";; %-8s", "clock"); |
8c660648 JL |
5590 | for (unit = 0; unit < FUNCTION_UNITS_SIZE; unit++) |
5591 | if (function_units[unit].bitmask & target_units) | |
5592 | for (i = 0; i < function_units[unit].multiplicity; i++) | |
2f308fec RH |
5593 | fprintf (dump, " %-33s", function_units[unit].name); |
5594 | fprintf (dump, " %-8s\n", "no-unit"); | |
5595 | ||
5596 | fprintf (dump, ";; %-8s", "====="); | |
5597 | for (unit = 0; unit < FUNCTION_UNITS_SIZE; unit++) | |
5598 | if (function_units[unit].bitmask & target_units) | |
5599 | for (i = 0; i < function_units[unit].multiplicity; i++) | |
5600 | fprintf (dump, " %-33s", "=============================="); | |
5601 | fprintf (dump, " %-8s\n", "======="); | |
8c660648 | 5602 | |
63de6c74 | 5603 | /* Print insns in each cycle. */ |
8c660648 JL |
5604 | fprintf (dump, "%s\n", visual_tbl); |
5605 | } | |
5606 | ||
63de6c74 | 5607 | /* Print insns in the 'no_unit' column of visualization. */ |
8c660648 JL |
5608 | |
5609 | static void | |
5610 | visualize_no_unit (insn) | |
5611 | rtx insn; | |
5612 | { | |
5613 | vis_no_unit[n_vis_no_unit] = insn; | |
5614 | n_vis_no_unit++; | |
5615 | } | |
5616 | ||
5617 | /* Print insns scheduled in clock, for visualization. */ | |
5618 | ||
5619 | static void | |
5620 | visualize_scheduled_insns (b, clock) | |
5621 | int b, clock; | |
5622 | { | |
5623 | int i, unit; | |
5624 | ||
63de6c74 | 5625 | /* If no more room, split table into two. */ |
8c660648 JL |
5626 | if (n_visual_lines >= MAX_VISUAL_LINES) |
5627 | { | |
5628 | print_block_visualization (b, "(incomplete)"); | |
5629 | init_block_visualization (); | |
5630 | } | |
5631 | ||
5632 | n_visual_lines++; | |
5633 | ||
5634 | sprintf (visual_tbl + strlen (visual_tbl), ";; %-8d", clock); | |
5635 | for (unit = 0; unit < FUNCTION_UNITS_SIZE; unit++) | |
5636 | if (function_units[unit].bitmask & target_units) | |
5637 | for (i = 0; i < function_units[unit].multiplicity; i++) | |
5638 | { | |
5639 | int instance = unit + i * FUNCTION_UNITS_SIZE; | |
5640 | rtx insn = unit_last_insn[instance]; | |
5641 | ||
63de6c74 | 5642 | /* Print insns that still keep the unit busy. */ |
8c660648 JL |
5643 | if (insn && |
5644 | actual_hazard_this_instance (unit, instance, insn, clock, 0)) | |
5645 | { | |
5646 | char str[BUF_LEN]; | |
5647 | print_insn (str, insn, 0); | |
5648 | str[INSN_LEN] = '\0'; | |
5649 | sprintf (visual_tbl + strlen (visual_tbl), " %-33s", str); | |
5650 | } | |
5651 | else | |
5652 | sprintf (visual_tbl + strlen (visual_tbl), " %-33s", "------------------------------"); | |
5653 | } | |
5654 | ||
63de6c74 | 5655 | /* Print insns that are not assigned to any unit. */ |
8c660648 JL |
5656 | for (i = 0; i < n_vis_no_unit; i++) |
5657 | sprintf (visual_tbl + strlen (visual_tbl), " %-8d", | |
5658 | INSN_UID (vis_no_unit[i])); | |
5659 | n_vis_no_unit = 0; | |
5660 | ||
5661 | sprintf (visual_tbl + strlen (visual_tbl), "\n"); | |
5662 | } | |
5663 | ||
63de6c74 | 5664 | /* Print stalled cycles. */ |
8c660648 JL |
5665 | |
5666 | static void | |
5667 | visualize_stall_cycles (b, stalls) | |
5668 | int b, stalls; | |
5669 | { | |
5670 | int i; | |
5671 | ||
63de6c74 | 5672 | /* If no more room, split table into two. */ |
8c660648 JL |
5673 | if (n_visual_lines >= MAX_VISUAL_LINES) |
5674 | { | |
5675 | print_block_visualization (b, "(incomplete)"); | |
5676 | init_block_visualization (); | |
5677 | } | |
5678 | ||
5679 | n_visual_lines++; | |
5680 | ||
5681 | sprintf (visual_tbl + strlen (visual_tbl), ";; "); | |
5682 | for (i = 0; i < stalls; i++) | |
5683 | sprintf (visual_tbl + strlen (visual_tbl), "."); | |
5684 | sprintf (visual_tbl + strlen (visual_tbl), "\n"); | |
5685 | } | |
5686 | ||
63de6c74 | 5687 | /* move_insn1: Remove INSN from insn chain, and link it after LAST insn. */ |
8c660648 JL |
5688 | |
5689 | static rtx | |
5690 | move_insn1 (insn, last) | |
5691 | rtx insn, last; | |
5692 | { | |
5693 | NEXT_INSN (PREV_INSN (insn)) = NEXT_INSN (insn); | |
5694 | PREV_INSN (NEXT_INSN (insn)) = PREV_INSN (insn); | |
5695 | ||
5696 | NEXT_INSN (insn) = NEXT_INSN (last); | |
5697 | PREV_INSN (NEXT_INSN (last)) = insn; | |
5698 | ||
5699 | NEXT_INSN (last) = insn; | |
5700 | PREV_INSN (insn) = last; | |
5701 | ||
5702 | return insn; | |
5703 | } | |
5704 | ||
c46a37c4 | 5705 | /* Search INSN for REG_SAVE_NOTE note pairs for NOTE_INSN_SETJMP, |
8c660648 | 5706 | NOTE_INSN_{LOOP,EHREGION}_{BEG,END}; and convert them back into |
c46a37c4 RH |
5707 | NOTEs. The REG_SAVE_NOTE note following first one is contains the |
5708 | saved value for NOTE_BLOCK_NUMBER which is useful for | |
8c660648 JL |
5709 | NOTE_INSN_EH_REGION_{BEG,END} NOTEs. LAST is the last instruction |
5710 | output by the instruction scheduler. Return the new value of LAST. */ | |
5711 | ||
5712 | static rtx | |
5713 | reemit_notes (insn, last) | |
5714 | rtx insn; | |
5715 | rtx last; | |
5716 | { | |
5717 | rtx note, retval; | |
5718 | ||
5719 | retval = last; | |
5720 | for (note = REG_NOTES (insn); note; note = XEXP (note, 1)) | |
5721 | { | |
c46a37c4 | 5722 | if (REG_NOTE_KIND (note) == REG_SAVE_NOTE) |
8c660648 | 5723 | { |
b3b42a4d RK |
5724 | enum insn_note note_type = INTVAL (XEXP (note, 0)); |
5725 | ||
6dfdecdb | 5726 | if (note_type == NOTE_INSN_SETJMP) |
8c660648 | 5727 | { |
6dfdecdb | 5728 | retval = emit_note_after (NOTE_INSN_SETJMP, insn); |
8c660648 | 5729 | CONST_CALL_P (retval) = CONST_CALL_P (note); |
7bd41ea6 MM |
5730 | remove_note (insn, note); |
5731 | note = XEXP (note, 1); | |
8c660648 | 5732 | } |
b3b42a4d | 5733 | else if (note_type == NOTE_INSN_RANGE_BEG |
6dfdecdb RH |
5734 | || note_type == NOTE_INSN_RANGE_END) |
5735 | { | |
5736 | last = emit_note_before (note_type, last); | |
5737 | remove_note (insn, note); | |
5738 | note = XEXP (note, 1); | |
5739 | NOTE_RANGE_INFO (last) = XEXP (note, 0); | |
5740 | } | |
8c660648 JL |
5741 | else |
5742 | { | |
19699da4 | 5743 | last = emit_note_before (note_type, last); |
7bd41ea6 MM |
5744 | remove_note (insn, note); |
5745 | note = XEXP (note, 1); | |
1a4450c7 MM |
5746 | if (note_type == NOTE_INSN_EH_REGION_BEG |
5747 | || note_type == NOTE_INSN_EH_REGION_END) | |
7bd41ea6 | 5748 | NOTE_EH_HANDLER (last) = INTVAL (XEXP (note, 0)); |
8c660648 JL |
5749 | } |
5750 | remove_note (insn, note); | |
5751 | } | |
5752 | } | |
5753 | return retval; | |
5754 | } | |
5755 | ||
5756 | /* Move INSN, and all insns which should be issued before it, | |
c9e03727 JL |
5757 | due to SCHED_GROUP_P flag. Reemit notes if needed. |
5758 | ||
5759 | Return the last insn emitted by the scheduler, which is the | |
5760 | return value from the first call to reemit_notes. */ | |
8c660648 JL |
5761 | |
5762 | static rtx | |
5763 | move_insn (insn, last) | |
5764 | rtx insn, last; | |
5765 | { | |
c9e03727 | 5766 | rtx retval = NULL; |
8c660648 | 5767 | |
c9e03727 JL |
5768 | /* If INSN has SCHED_GROUP_P set, then issue it and any other |
5769 | insns with SCHED_GROUP_P set first. */ | |
8c660648 JL |
5770 | while (SCHED_GROUP_P (insn)) |
5771 | { | |
5772 | rtx prev = PREV_INSN (insn); | |
c9e03727 JL |
5773 | |
5774 | /* Move a SCHED_GROUP_P insn. */ | |
8c660648 | 5775 | move_insn1 (insn, last); |
c9e03727 JL |
5776 | /* If this is the first call to reemit_notes, then record |
5777 | its return value. */ | |
5778 | if (retval == NULL_RTX) | |
5779 | retval = reemit_notes (insn, insn); | |
5780 | else | |
5781 | reemit_notes (insn, insn); | |
8c660648 JL |
5782 | insn = prev; |
5783 | } | |
5784 | ||
c9e03727 | 5785 | /* Now move the first non SCHED_GROUP_P insn. */ |
8c660648 | 5786 | move_insn1 (insn, last); |
c9e03727 JL |
5787 | |
5788 | /* If this is the first call to reemit_notes, then record | |
5789 | its return value. */ | |
5790 | if (retval == NULL_RTX) | |
5791 | retval = reemit_notes (insn, insn); | |
5792 | else | |
5793 | reemit_notes (insn, insn); | |
5794 | ||
5795 | return retval; | |
8c660648 JL |
5796 | } |
5797 | ||
5798 | /* Return an insn which represents a SCHED_GROUP, which is | |
5799 | the last insn in the group. */ | |
5800 | ||
5801 | static rtx | |
5802 | group_leader (insn) | |
5803 | rtx insn; | |
5804 | { | |
5805 | rtx prev; | |
5806 | ||
5807 | do | |
5808 | { | |
5809 | prev = insn; | |
5810 | insn = next_nonnote_insn (insn); | |
5811 | } | |
5812 | while (insn && SCHED_GROUP_P (insn) && (GET_CODE (insn) != CODE_LABEL)); | |
5813 | ||
5814 | return prev; | |
5815 | } | |
5816 | ||
5817 | /* Use forward list scheduling to rearrange insns of block BB in region RGN, | |
5818 | possibly bringing insns from subsequent blocks in the same region. | |
5819 | Return number of insns scheduled. */ | |
5820 | ||
5821 | static int | |
5835e573 | 5822 | schedule_block (bb, rgn_n_insns) |
8c660648 | 5823 | int bb; |
8c660648 JL |
5824 | int rgn_n_insns; |
5825 | { | |
5826 | /* Local variables. */ | |
5827 | rtx insn, last; | |
5828 | rtx *ready; | |
8c660648 JL |
5829 | int n_ready = 0; |
5830 | int can_issue_more; | |
5831 | ||
63de6c74 | 5832 | /* Flow block of this bb. */ |
8c660648 JL |
5833 | int b = BB_TO_BLOCK (bb); |
5834 | ||
5835 | /* target_n_insns == number of insns in b before scheduling starts. | |
5836 | sched_target_n_insns == how many of b's insns were scheduled. | |
63de6c74 | 5837 | sched_n_insns == how many insns were scheduled in b. */ |
8c660648 JL |
5838 | int target_n_insns = 0; |
5839 | int sched_target_n_insns = 0; | |
5840 | int sched_n_insns = 0; | |
5841 | ||
5842 | #define NEED_NOTHING 0 | |
5843 | #define NEED_HEAD 1 | |
5844 | #define NEED_TAIL 2 | |
5845 | int new_needs; | |
5846 | ||
63de6c74 | 5847 | /* Head/tail info for this block. */ |
8c660648 JL |
5848 | rtx prev_head; |
5849 | rtx next_tail; | |
5850 | rtx head; | |
5851 | rtx tail; | |
5852 | int bb_src; | |
5853 | ||
484df988 JL |
5854 | /* We used to have code to avoid getting parameters moved from hard |
5855 | argument registers into pseudos. | |
8c660648 | 5856 | |
484df988 JL |
5857 | However, it was removed when it proved to be of marginal benefit |
5858 | and caused problems because schedule_block and compute_forward_dependences | |
5859 | had different notions of what the "head" insn was. */ | |
49c3bb12 | 5860 | get_bb_head_tail (bb, &head, &tail); |
8c660648 | 5861 | |
0e2eaba4 GK |
5862 | /* rm_other_notes only removes notes which are _inside_ the |
5863 | block---that is, it won't remove notes before the first real insn | |
5864 | or after the last real insn of the block. So if the first insn | |
5865 | has a REG_SAVE_NOTE which would otherwise be emitted before the | |
5866 | insn, it is redundant with the note before the start of the | |
5867 | block, and so we have to take it out. | |
5868 | ||
5869 | FIXME: Probably the same thing should be done with REG_SAVE_NOTEs | |
5870 | referencing NOTE_INSN_SETJMP at the end of the block. */ | |
2c3c49de | 5871 | if (INSN_P (head)) |
1447b516 JL |
5872 | { |
5873 | rtx note; | |
5874 | ||
5875 | for (note = REG_NOTES (head); note; note = XEXP (note, 1)) | |
c46a37c4 | 5876 | if (REG_NOTE_KIND (note) == REG_SAVE_NOTE) |
0e2eaba4 GK |
5877 | { |
5878 | if (INTVAL (XEXP (note, 0)) != NOTE_INSN_SETJMP) | |
5879 | { | |
5880 | remove_note (head, note); | |
5881 | note = XEXP (note, 1); | |
5882 | remove_note (head, note); | |
5883 | } | |
5884 | else | |
5885 | note = XEXP (note, 1); | |
5886 | } | |
1447b516 JL |
5887 | } |
5888 | ||
8c660648 JL |
5889 | next_tail = NEXT_INSN (tail); |
5890 | prev_head = PREV_INSN (head); | |
5891 | ||
5892 | /* If the only insn left is a NOTE or a CODE_LABEL, then there is no need | |
5893 | to schedule this block. */ | |
2c3c49de | 5894 | if (head == tail && (! INSN_P (head))) |
8c660648 JL |
5895 | return (sched_n_insns); |
5896 | ||
63de6c74 | 5897 | /* Debug info. */ |
8c660648 JL |
5898 | if (sched_verbose) |
5899 | { | |
5900 | fprintf (dump, ";; ======================================================\n"); | |
5901 | fprintf (dump, | |
5902 | ";; -- basic block %d from %d to %d -- %s reload\n", | |
3b413743 | 5903 | b, INSN_UID (BLOCK_HEAD (b)), INSN_UID (BLOCK_END (b)), |
8c660648 JL |
5904 | (reload_completed ? "after" : "before")); |
5905 | fprintf (dump, ";; ======================================================\n"); | |
8c660648 JL |
5906 | fprintf (dump, "\n"); |
5907 | ||
5908 | visual_tbl = (char *) alloca (get_visual_tbl_length ()); | |
5909 | init_block_visualization (); | |
5910 | } | |
5911 | ||
63de6c74 | 5912 | /* Remove remaining note insns from the block, save them in |
8c660648 JL |
5913 | note_list. These notes are restored at the end of |
5914 | schedule_block (). */ | |
5915 | note_list = 0; | |
5916 | rm_other_notes (head, tail); | |
5917 | ||
5918 | target_bb = bb; | |
5919 | ||
63de6c74 | 5920 | /* Prepare current target block info. */ |
8c660648 JL |
5921 | if (current_nr_blocks > 1) |
5922 | { | |
7a403706 | 5923 | candidate_table = (candidate *) xmalloc (current_nr_blocks |
98903742 | 5924 | * sizeof (candidate)); |
8c660648 JL |
5925 | |
5926 | bblst_last = 0; | |
ef375129 JW |
5927 | /* bblst_table holds split blocks and update blocks for each block after |
5928 | the current one in the region. split blocks and update blocks are | |
5929 | the TO blocks of region edges, so there can be at most rgn_nr_edges | |
5930 | of them. */ | |
5931 | bblst_size = (current_nr_blocks - bb) * rgn_nr_edges; | |
98903742 | 5932 | bblst_table = (int *) xmalloc (bblst_size * sizeof (int)); |
8c660648 JL |
5933 | |
5934 | bitlst_table_last = 0; | |
5935 | bitlst_table_size = rgn_nr_edges; | |
98903742 | 5936 | bitlst_table = (int *) xmalloc (rgn_nr_edges * sizeof (int)); |
8c660648 JL |
5937 | |
5938 | compute_trg_info (bb); | |
5939 | } | |
5940 | ||
5941 | clear_units (); | |
5942 | ||
63de6c74 | 5943 | /* Allocate the ready list. */ |
98903742 | 5944 | ready = (rtx *) xmalloc ((rgn_n_insns + 1) * sizeof (rtx)); |
8c660648 JL |
5945 | |
5946 | /* Print debugging information. */ | |
5947 | if (sched_verbose >= 5) | |
5948 | debug_dependencies (); | |
5949 | ||
8c660648 JL |
5950 | /* Initialize ready list with all 'ready' insns in target block. |
5951 | Count number of insns in the target block being scheduled. */ | |
5952 | n_ready = 0; | |
5953 | for (insn = head; insn != next_tail; insn = NEXT_INSN (insn)) | |
5954 | { | |
5955 | rtx next; | |
5956 | ||
2c3c49de | 5957 | if (! INSN_P (insn)) |
8c660648 JL |
5958 | continue; |
5959 | next = NEXT_INSN (insn); | |
5960 | ||
5961 | if (INSN_DEP_COUNT (insn) == 0 | |
2c3c49de | 5962 | && (SCHED_GROUP_P (next) == 0 || ! INSN_P (next))) |
8c660648 JL |
5963 | ready[n_ready++] = insn; |
5964 | if (!(SCHED_GROUP_P (insn))) | |
5965 | target_n_insns++; | |
5966 | } | |
5967 | ||
5968 | /* Add to ready list all 'ready' insns in valid source blocks. | |
5969 | For speculative insns, check-live, exception-free, and | |
5970 | issue-delay. */ | |
5971 | for (bb_src = bb + 1; bb_src < current_nr_blocks; bb_src++) | |
5972 | if (IS_VALID (bb_src)) | |
5973 | { | |
5974 | rtx src_head; | |
5975 | rtx src_next_tail; | |
5976 | rtx tail, head; | |
5977 | ||
49c3bb12 | 5978 | get_bb_head_tail (bb_src, &head, &tail); |
8c660648 JL |
5979 | src_next_tail = NEXT_INSN (tail); |
5980 | src_head = head; | |
5981 | ||
2c3c49de | 5982 | if (head == tail && (! INSN_P (head))) |
8c660648 JL |
5983 | continue; |
5984 | ||
5985 | for (insn = src_head; insn != src_next_tail; insn = NEXT_INSN (insn)) | |
5986 | { | |
2c3c49de | 5987 | if (! INSN_P (insn)) |
8c660648 JL |
5988 | continue; |
5989 | ||
5990 | if (!CANT_MOVE (insn) | |
5991 | && (!IS_SPECULATIVE_INSN (insn) | |
5992 | || (insn_issue_delay (insn) <= 3 | |
5835e573 | 5993 | && check_live (insn, bb_src) |
8c660648 | 5994 | && is_exception_free (insn, bb_src, target_bb)))) |
8c660648 JL |
5995 | { |
5996 | rtx next; | |
5997 | ||
7a403706 | 5998 | /* Note that we havn't squirrled away the notes for |
0d8b2ca1 RH |
5999 | blocks other than the current. So if this is a |
6000 | speculative insn, NEXT might otherwise be a note. */ | |
6001 | next = next_nonnote_insn (insn); | |
8c660648 | 6002 | if (INSN_DEP_COUNT (insn) == 0 |
b182031e RH |
6003 | && (! next |
6004 | || SCHED_GROUP_P (next) == 0 | |
2c3c49de | 6005 | || ! INSN_P (next))) |
8c660648 JL |
6006 | ready[n_ready++] = insn; |
6007 | } | |
6008 | } | |
6009 | } | |
6010 | ||
e4da5f6d MM |
6011 | #ifdef MD_SCHED_INIT |
6012 | MD_SCHED_INIT (dump, sched_verbose); | |
6013 | #endif | |
6014 | ||
63de6c74 | 6015 | /* No insns scheduled in this block yet. */ |
8c660648 JL |
6016 | last_scheduled_insn = 0; |
6017 | ||
8c660648 JL |
6018 | /* Q_SIZE is the total number of insns in the queue. */ |
6019 | q_ptr = 0; | |
6020 | q_size = 0; | |
4bdc8810 | 6021 | last_clock_var = 0; |
8c660648 JL |
6022 | bzero ((char *) insn_queue, sizeof (insn_queue)); |
6023 | ||
197043f5 RH |
6024 | /* Start just before the beginning of time. */ |
6025 | clock_var = -1; | |
6026 | ||
8c660648 JL |
6027 | /* We start inserting insns after PREV_HEAD. */ |
6028 | last = prev_head; | |
6029 | ||
6030 | /* Initialize INSN_QUEUE, LIST and NEW_NEEDS. */ | |
3b413743 | 6031 | new_needs = (NEXT_INSN (prev_head) == BLOCK_HEAD (b) |
8c660648 | 6032 | ? NEED_HEAD : NEED_NOTHING); |
3b413743 | 6033 | if (PREV_INSN (next_tail) == BLOCK_END (b)) |
8c660648 JL |
6034 | new_needs |= NEED_TAIL; |
6035 | ||
63de6c74 | 6036 | /* Loop until all the insns in BB are scheduled. */ |
8c660648 JL |
6037 | while (sched_target_n_insns < target_n_insns) |
6038 | { | |
8c660648 JL |
6039 | clock_var++; |
6040 | ||
6041 | /* Add to the ready list all pending insns that can be issued now. | |
6042 | If there are no ready insns, increment clock until one | |
6043 | is ready and add all pending insns at that point to the ready | |
6044 | list. */ | |
6045 | n_ready = queue_to_ready (ready, n_ready); | |
6046 | ||
6047 | if (n_ready == 0) | |
6048 | abort (); | |
6049 | ||
6050 | if (sched_verbose >= 2) | |
6051 | { | |
6052 | fprintf (dump, ";;\t\tReady list after queue_to_ready: "); | |
6053 | debug_ready_list (ready, n_ready); | |
6054 | } | |
6055 | ||
197043f5 | 6056 | /* Sort the ready list based on priority. */ |
8c660648 | 6057 | SCHED_SORT (ready, n_ready); |
197043f5 | 6058 | |
7a403706 | 6059 | /* Allow the target to reorder the list, typically for |
197043f5 | 6060 | better instruction bundling. */ |
e4da5f6d | 6061 | #ifdef MD_SCHED_REORDER |
197043f5 RH |
6062 | MD_SCHED_REORDER (dump, sched_verbose, ready, n_ready, clock_var, |
6063 | can_issue_more); | |
6064 | #else | |
6065 | can_issue_more = issue_rate; | |
e4da5f6d | 6066 | #endif |
8c660648 JL |
6067 | |
6068 | if (sched_verbose) | |
6069 | { | |
47312d84 | 6070 | fprintf (dump, "\n;;\tReady list (t =%3d): ", clock_var); |
8c660648 JL |
6071 | debug_ready_list (ready, n_ready); |
6072 | } | |
6073 | ||
197043f5 RH |
6074 | /* Issue insns from ready list. */ |
6075 | while (n_ready != 0 && can_issue_more) | |
8c660648 | 6076 | { |
197043f5 RH |
6077 | /* Select and remove the insn from the ready list. */ |
6078 | rtx insn = ready[--n_ready]; | |
8c660648 JL |
6079 | int cost = actual_hazard (insn_unit (insn), insn, clock_var, 0); |
6080 | ||
197043f5 | 6081 | if (cost >= 1) |
8c660648 JL |
6082 | { |
6083 | queue_insn (insn, cost); | |
197043f5 | 6084 | continue; |
8c660648 | 6085 | } |
4f64eaca | 6086 | |
197043f5 RH |
6087 | /* An interblock motion? */ |
6088 | if (INSN_BB (insn) != target_bb) | |
6089 | { | |
6090 | rtx temp; | |
c88e8206 | 6091 | basic_block b1; |
8c660648 | 6092 | |
197043f5 RH |
6093 | if (IS_SPECULATIVE_INSN (insn)) |
6094 | { | |
6095 | if (!check_live (insn, INSN_BB (insn))) | |
6096 | continue; | |
6097 | update_live (insn, INSN_BB (insn)); | |
8c660648 | 6098 | |
197043f5 RH |
6099 | /* For speculative load, mark insns fed by it. */ |
6100 | if (IS_LOAD_INSN (insn) || FED_BY_SPEC_LOAD (insn)) | |
6101 | set_spec_fed (insn); | |
8c660648 | 6102 | |
197043f5 RH |
6103 | nr_spec++; |
6104 | } | |
6105 | nr_inter++; | |
8c660648 | 6106 | |
49c3bb12 | 6107 | /* Find the beginning of the scheduling group. */ |
7a403706 KH |
6108 | /* ??? Ought to update basic block here, but later bits of |
6109 | schedule_block assumes the original insn block is | |
49c3bb12 RH |
6110 | still intact. */ |
6111 | ||
197043f5 | 6112 | temp = insn; |
eae48b73 | 6113 | while (SCHED_GROUP_P (temp)) |
49c3bb12 | 6114 | temp = PREV_INSN (temp); |
4f64eaca | 6115 | |
197043f5 | 6116 | /* Update source block boundaries. */ |
c88e8206 RH |
6117 | b1 = BLOCK_FOR_INSN (temp); |
6118 | if (temp == b1->head && insn == b1->end) | |
197043f5 RH |
6119 | { |
6120 | /* We moved all the insns in the basic block. | |
6121 | Emit a note after the last insn and update the | |
6122 | begin/end boundaries to point to the note. */ | |
c88e8206 RH |
6123 | rtx note = emit_note_after (NOTE_INSN_DELETED, insn); |
6124 | b1->head = note; | |
6125 | b1->end = note; | |
8c660648 | 6126 | } |
c88e8206 | 6127 | else if (insn == b1->end) |
8c660648 | 6128 | { |
197043f5 RH |
6129 | /* We took insns from the end of the basic block, |
6130 | so update the end of block boundary so that it | |
6131 | points to the first insn we did not move. */ | |
c88e8206 | 6132 | b1->end = PREV_INSN (temp); |
8c660648 | 6133 | } |
c88e8206 | 6134 | else if (temp == b1->head) |
197043f5 RH |
6135 | { |
6136 | /* We took insns from the start of the basic block, | |
6137 | so update the start of block boundary so that | |
6138 | it points to the first insn we did not move. */ | |
c88e8206 | 6139 | b1->head = NEXT_INSN (insn); |
197043f5 RH |
6140 | } |
6141 | } | |
6142 | else | |
6143 | { | |
6144 | /* In block motion. */ | |
6145 | sched_target_n_insns++; | |
6146 | } | |
8c660648 | 6147 | |
197043f5 RH |
6148 | last_scheduled_insn = insn; |
6149 | last = move_insn (insn, last); | |
6150 | sched_n_insns++; | |
8c660648 | 6151 | |
e4da5f6d | 6152 | #ifdef MD_SCHED_VARIABLE_ISSUE |
197043f5 RH |
6153 | MD_SCHED_VARIABLE_ISSUE (dump, sched_verbose, insn, |
6154 | can_issue_more); | |
e4da5f6d | 6155 | #else |
197043f5 | 6156 | can_issue_more--; |
e4da5f6d | 6157 | #endif |
8c660648 | 6158 | |
197043f5 | 6159 | n_ready = schedule_insn (insn, ready, n_ready, clock_var); |
8c660648 | 6160 | |
197043f5 RH |
6161 | /* Close this block after scheduling its jump. */ |
6162 | if (GET_CODE (last_scheduled_insn) == JUMP_INSN) | |
6163 | break; | |
8c660648 JL |
6164 | } |
6165 | ||
197043f5 | 6166 | /* Debug info. */ |
8c660648 | 6167 | if (sched_verbose) |
197043f5 | 6168 | visualize_scheduled_insns (b, clock_var); |
8c660648 JL |
6169 | } |
6170 | ||
63de6c74 | 6171 | /* Debug info. */ |
8c660648 JL |
6172 | if (sched_verbose) |
6173 | { | |
6174 | fprintf (dump, ";;\tReady list (final): "); | |
6175 | debug_ready_list (ready, n_ready); | |
6176 | print_block_visualization (b, ""); | |
6177 | } | |
6178 | ||
6179 | /* Sanity check -- queue must be empty now. Meaningless if region has | |
cc132865 | 6180 | multiple bbs. */ |
8c660648 | 6181 | if (current_nr_blocks > 1) |
cc132865 JL |
6182 | if (!flag_schedule_interblock && q_size != 0) |
6183 | abort (); | |
8c660648 | 6184 | |
63de6c74 | 6185 | /* Update head/tail boundaries. */ |
8c660648 JL |
6186 | head = NEXT_INSN (prev_head); |
6187 | tail = last; | |
6188 | ||
8c660648 JL |
6189 | /* Restore-other-notes: NOTE_LIST is the end of a chain of notes |
6190 | previously found among the insns. Insert them at the beginning | |
6191 | of the insns. */ | |
6192 | if (note_list != 0) | |
6193 | { | |
6194 | rtx note_head = note_list; | |
6195 | ||
6196 | while (PREV_INSN (note_head)) | |
6197 | { | |
6198 | note_head = PREV_INSN (note_head); | |
6199 | } | |
6200 | ||
6201 | PREV_INSN (note_head) = PREV_INSN (head); | |
6202 | NEXT_INSN (PREV_INSN (head)) = note_head; | |
6203 | PREV_INSN (head) = note_list; | |
6204 | NEXT_INSN (note_list) = head; | |
6205 | head = note_head; | |
6206 | } | |
6207 | ||
63de6c74 | 6208 | /* Update target block boundaries. */ |
8c660648 | 6209 | if (new_needs & NEED_HEAD) |
3b413743 | 6210 | BLOCK_HEAD (b) = head; |
8c660648 JL |
6211 | |
6212 | if (new_needs & NEED_TAIL) | |
3b413743 | 6213 | BLOCK_END (b) = tail; |
8c660648 | 6214 | |
63de6c74 | 6215 | /* Debugging. */ |
8c660648 JL |
6216 | if (sched_verbose) |
6217 | { | |
6218 | fprintf (dump, ";; total time = %d\n;; new basic block head = %d\n", | |
3b413743 | 6219 | clock_var, INSN_UID (BLOCK_HEAD (b))); |
8c660648 | 6220 | fprintf (dump, ";; new basic block end = %d\n\n", |
3b413743 | 6221 | INSN_UID (BLOCK_END (b))); |
8c660648 JL |
6222 | } |
6223 | ||
98903742 MM |
6224 | /* Clean up. */ |
6225 | if (current_nr_blocks > 1) | |
6226 | { | |
6227 | free (candidate_table); | |
6228 | free (bblst_table); | |
6229 | free (bitlst_table); | |
6230 | } | |
6231 | free (ready); | |
6232 | ||
8c660648 | 6233 | return (sched_n_insns); |
7a403706 | 6234 | } |
8c660648 | 6235 | \f |
63de6c74 | 6236 | /* Print the bit-set of registers, S, callable from debugger. */ |
8c660648 JL |
6237 | |
6238 | extern void | |
6239 | debug_reg_vector (s) | |
6240 | regset s; | |
6241 | { | |
6242 | int regno; | |
6243 | ||
6244 | EXECUTE_IF_SET_IN_REG_SET (s, 0, regno, | |
6245 | { | |
6246 | fprintf (dump, " %d", regno); | |
6247 | }); | |
6248 | ||
6249 | fprintf (dump, "\n"); | |
6250 | } | |
6251 | ||
6252 | /* Use the backward dependences from LOG_LINKS to build | |
6253 | forward dependences in INSN_DEPEND. */ | |
6254 | ||
6255 | static void | |
6256 | compute_block_forward_dependences (bb) | |
6257 | int bb; | |
6258 | { | |
6259 | rtx insn, link; | |
6260 | rtx tail, head; | |
6261 | rtx next_tail; | |
6262 | enum reg_note dep_type; | |
6263 | ||
49c3bb12 | 6264 | get_bb_head_tail (bb, &head, &tail); |
8c660648 JL |
6265 | next_tail = NEXT_INSN (tail); |
6266 | for (insn = head; insn != next_tail; insn = NEXT_INSN (insn)) | |
6267 | { | |
2c3c49de | 6268 | if (! INSN_P (insn)) |
8c660648 JL |
6269 | continue; |
6270 | ||
6271 | insn = group_leader (insn); | |
6272 | ||
6273 | for (link = LOG_LINKS (insn); link; link = XEXP (link, 1)) | |
6274 | { | |
6275 | rtx x = group_leader (XEXP (link, 0)); | |
6276 | rtx new_link; | |
6277 | ||
6278 | if (x != XEXP (link, 0)) | |
6279 | continue; | |
6280 | ||
706c5c2f JL |
6281 | #ifdef ENABLE_CHECKING |
6282 | /* If add_dependence is working properly there should never | |
6283 | be notes, deleted insns or duplicates in the backward | |
6284 | links. Thus we need not check for them here. | |
6285 | ||
6286 | However, if we have enabled checking we might as well go | |
6287 | ahead and verify that add_dependence worked properly. */ | |
6288 | if (GET_CODE (x) == NOTE | |
6289 | || INSN_DELETED_P (x) | |
178b88b9 VM |
6290 | || (forward_dependency_cache != NULL |
6291 | && TEST_BIT (forward_dependency_cache[INSN_LUID (x)], | |
6292 | INSN_LUID (insn))) | |
6293 | || (forward_dependency_cache == NULL | |
6294 | && find_insn_list (insn, INSN_DEPEND (x)))) | |
706c5c2f | 6295 | abort (); |
178b88b9 VM |
6296 | if (forward_dependency_cache != NULL) |
6297 | SET_BIT (forward_dependency_cache[INSN_LUID (x)], | |
6298 | INSN_LUID (insn)); | |
706c5c2f | 6299 | #endif |
8c660648 | 6300 | |
ebb7b10b | 6301 | new_link = alloc_INSN_LIST (insn, INSN_DEPEND (x)); |
8c660648 JL |
6302 | |
6303 | dep_type = REG_NOTE_KIND (link); | |
6304 | PUT_REG_NOTE_KIND (new_link, dep_type); | |
6305 | ||
8c660648 JL |
6306 | INSN_DEPEND (x) = new_link; |
6307 | INSN_DEP_COUNT (insn) += 1; | |
6308 | } | |
6309 | } | |
6310 | } | |
6311 | ||
6312 | /* Initialize variables for region data dependence analysis. | |
63de6c74 | 6313 | n_bbs is the number of region blocks. */ |
8c660648 | 6314 | |
e1306f49 BS |
6315 | static void |
6316 | init_deps (deps) | |
6317 | struct deps *deps; | |
8c660648 | 6318 | { |
e1306f49 BS |
6319 | int maxreg = max_reg_num (); |
6320 | deps->reg_last_uses = (rtx *) xcalloc (maxreg, sizeof (rtx)); | |
6321 | deps->reg_last_sets = (rtx *) xcalloc (maxreg, sizeof (rtx)); | |
6322 | deps->reg_last_clobbers = (rtx *) xcalloc (maxreg, sizeof (rtx)); | |
6323 | ||
6324 | deps->pending_read_insns = 0; | |
6325 | deps->pending_read_mems = 0; | |
6326 | deps->pending_write_insns = 0; | |
6327 | deps->pending_write_mems = 0; | |
6328 | deps->pending_lists_length = 0; | |
6329 | deps->last_pending_memory_flush = 0; | |
6330 | deps->last_function_call = 0; | |
ef384380 | 6331 | deps->in_post_call_group_p = 0; |
e1306f49 BS |
6332 | |
6333 | deps->sched_before_next_call | |
6334 | = gen_rtx_INSN (VOIDmode, 0, NULL_RTX, NULL_RTX, | |
6335 | NULL_RTX, 0, NULL_RTX, NULL_RTX); | |
6336 | LOG_LINKS (deps->sched_before_next_call) = 0; | |
8c660648 JL |
6337 | } |
6338 | ||
63de6c74 MH |
6339 | /* Add dependences so that branches are scheduled to run last in their |
6340 | block. */ | |
8c660648 JL |
6341 | |
6342 | static void | |
6343 | add_branch_dependences (head, tail) | |
6344 | rtx head, tail; | |
6345 | { | |
8c660648 JL |
6346 | rtx insn, last; |
6347 | ||
b182031e RH |
6348 | /* For all branches, calls, uses, clobbers, and cc0 setters, force them |
6349 | to remain in order at the end of the block by adding dependencies and | |
6350 | giving the last a high priority. There may be notes present, and | |
6351 | prev_head may also be a note. | |
8c660648 JL |
6352 | |
6353 | Branches must obviously remain at the end. Calls should remain at the | |
6354 | end since moving them results in worse register allocation. Uses remain | |
6355 | at the end to ensure proper register allocation. cc0 setters remaim | |
6356 | at the end because they can't be moved away from their cc0 user. */ | |
6357 | insn = tail; | |
6358 | last = 0; | |
b182031e RH |
6359 | while (GET_CODE (insn) == CALL_INSN |
6360 | || GET_CODE (insn) == JUMP_INSN | |
8c660648 JL |
6361 | || (GET_CODE (insn) == INSN |
6362 | && (GET_CODE (PATTERN (insn)) == USE | |
b182031e | 6363 | || GET_CODE (PATTERN (insn)) == CLOBBER |
8c660648 JL |
6364 | #ifdef HAVE_cc0 |
6365 | || sets_cc0_p (PATTERN (insn)) | |
6366 | #endif | |
6367 | )) | |
6368 | || GET_CODE (insn) == NOTE) | |
6369 | { | |
6370 | if (GET_CODE (insn) != NOTE) | |
6371 | { | |
6372 | if (last != 0 | |
6373 | && !find_insn_list (insn, LOG_LINKS (last))) | |
6374 | { | |
6375 | add_dependence (last, insn, REG_DEP_ANTI); | |
6376 | INSN_REF_COUNT (insn)++; | |
6377 | } | |
6378 | ||
6379 | CANT_MOVE (insn) = 1; | |
6380 | ||
6381 | last = insn; | |
326ee7a3 JL |
6382 | /* Skip over insns that are part of a group. |
6383 | Make each insn explicitly depend on the previous insn. | |
6384 | This ensures that only the group header will ever enter | |
6385 | the ready queue (and, when scheduled, will automatically | |
6386 | schedule the SCHED_GROUP_P block). */ | |
8c660648 | 6387 | while (SCHED_GROUP_P (insn)) |
326ee7a3 JL |
6388 | { |
6389 | rtx temp = prev_nonnote_insn (insn); | |
6390 | add_dependence (insn, temp, REG_DEP_ANTI); | |
6391 | insn = temp; | |
6392 | } | |
8c660648 JL |
6393 | } |
6394 | ||
6395 | /* Don't overrun the bounds of the basic block. */ | |
6396 | if (insn == head) | |
6397 | break; | |
6398 | ||
6399 | insn = PREV_INSN (insn); | |
6400 | } | |
6401 | ||
63de6c74 | 6402 | /* Make sure these insns are scheduled last in their block. */ |
8c660648 JL |
6403 | insn = last; |
6404 | if (insn != 0) | |
6405 | while (insn != head) | |
6406 | { | |
6407 | insn = prev_nonnote_insn (insn); | |
6408 | ||
6409 | if (INSN_REF_COUNT (insn) != 0) | |
6410 | continue; | |
6411 | ||
87373fba | 6412 | add_dependence (last, insn, REG_DEP_ANTI); |
8c660648 JL |
6413 | INSN_REF_COUNT (insn) = 1; |
6414 | ||
6415 | /* Skip over insns that are part of a group. */ | |
6416 | while (SCHED_GROUP_P (insn)) | |
6417 | insn = prev_nonnote_insn (insn); | |
6418 | } | |
6419 | } | |
6420 | ||
e1306f49 BS |
6421 | /* After computing the dependencies for block BB, propagate the dependencies |
6422 | found in TMP_DEPS to the successors of the block. MAX_REG is the number | |
6423 | of registers. */ | |
6424 | static void | |
6425 | propagate_deps (bb, tmp_deps, max_reg) | |
6426 | int bb; | |
6427 | struct deps *tmp_deps; | |
6428 | int max_reg; | |
6429 | { | |
6430 | int b = BB_TO_BLOCK (bb); | |
6431 | int e, first_edge; | |
6432 | int reg; | |
6433 | rtx link_insn, link_mem; | |
6434 | rtx u; | |
6435 | ||
6436 | /* These lists should point to the right place, for correct | |
6437 | freeing later. */ | |
6438 | bb_deps[bb].pending_read_insns = tmp_deps->pending_read_insns; | |
6439 | bb_deps[bb].pending_read_mems = tmp_deps->pending_read_mems; | |
6440 | bb_deps[bb].pending_write_insns = tmp_deps->pending_write_insns; | |
6441 | bb_deps[bb].pending_write_mems = tmp_deps->pending_write_mems; | |
6442 | ||
6443 | /* bb's structures are inherited by its successors. */ | |
6444 | first_edge = e = OUT_EDGES (b); | |
6445 | if (e <= 0) | |
6446 | return; | |
6447 | ||
6448 | do | |
6449 | { | |
6450 | rtx x; | |
6451 | int b_succ = TO_BLOCK (e); | |
6452 | int bb_succ = BLOCK_TO_BB (b_succ); | |
6453 | struct deps *succ_deps = bb_deps + bb_succ; | |
6454 | ||
6455 | /* Only bbs "below" bb, in the same region, are interesting. */ | |
6456 | if (CONTAINING_RGN (b) != CONTAINING_RGN (b_succ) | |
6457 | || bb_succ <= bb) | |
6458 | { | |
6459 | e = NEXT_OUT (e); | |
6460 | continue; | |
6461 | } | |
6462 | ||
6463 | for (reg = 0; reg < max_reg; reg++) | |
6464 | { | |
6465 | /* reg-last-uses lists are inherited by bb_succ. */ | |
6466 | for (u = tmp_deps->reg_last_uses[reg]; u; u = XEXP (u, 1)) | |
6467 | { | |
6468 | if (find_insn_list (XEXP (u, 0), | |
6469 | succ_deps->reg_last_uses[reg])) | |
6470 | continue; | |
6471 | ||
6472 | succ_deps->reg_last_uses[reg] | |
6473 | = alloc_INSN_LIST (XEXP (u, 0), | |
6474 | succ_deps->reg_last_uses[reg]); | |
6475 | } | |
6476 | ||
6477 | /* reg-last-defs lists are inherited by bb_succ. */ | |
6478 | for (u = tmp_deps->reg_last_sets[reg]; u; u = XEXP (u, 1)) | |
6479 | { | |
6480 | if (find_insn_list (XEXP (u, 0), | |
6481 | succ_deps->reg_last_sets[reg])) | |
6482 | continue; | |
6483 | ||
6484 | succ_deps->reg_last_sets[reg] | |
6485 | = alloc_INSN_LIST (XEXP (u, 0), | |
6486 | succ_deps->reg_last_sets[reg]); | |
6487 | } | |
6488 | ||
6489 | for (u = tmp_deps->reg_last_clobbers[reg]; u; u = XEXP (u, 1)) | |
6490 | { | |
6491 | if (find_insn_list (XEXP (u, 0), | |
6492 | succ_deps->reg_last_clobbers[reg])) | |
6493 | continue; | |
6494 | ||
6495 | succ_deps->reg_last_clobbers[reg] | |
6496 | = alloc_INSN_LIST (XEXP (u, 0), | |
6497 | succ_deps->reg_last_clobbers[reg]); | |
6498 | } | |
6499 | } | |
6500 | ||
6501 | /* Mem read/write lists are inherited by bb_succ. */ | |
6502 | link_insn = tmp_deps->pending_read_insns; | |
6503 | link_mem = tmp_deps->pending_read_mems; | |
6504 | while (link_insn) | |
6505 | { | |
6506 | if (!(find_insn_mem_list (XEXP (link_insn, 0), | |
6507 | XEXP (link_mem, 0), | |
6508 | succ_deps->pending_read_insns, | |
6509 | succ_deps->pending_read_mems))) | |
6510 | add_insn_mem_dependence (succ_deps, &succ_deps->pending_read_insns, | |
6511 | &succ_deps->pending_read_mems, | |
6512 | XEXP (link_insn, 0), XEXP (link_mem, 0)); | |
6513 | link_insn = XEXP (link_insn, 1); | |
6514 | link_mem = XEXP (link_mem, 1); | |
6515 | } | |
6516 | ||
6517 | link_insn = tmp_deps->pending_write_insns; | |
6518 | link_mem = tmp_deps->pending_write_mems; | |
6519 | while (link_insn) | |
6520 | { | |
6521 | if (!(find_insn_mem_list (XEXP (link_insn, 0), | |
6522 | XEXP (link_mem, 0), | |
6523 | succ_deps->pending_write_insns, | |
6524 | succ_deps->pending_write_mems))) | |
6525 | add_insn_mem_dependence (succ_deps, | |
6526 | &succ_deps->pending_write_insns, | |
6527 | &succ_deps->pending_write_mems, | |
6528 | XEXP (link_insn, 0), XEXP (link_mem, 0)); | |
6529 | ||
6530 | link_insn = XEXP (link_insn, 1); | |
6531 | link_mem = XEXP (link_mem, 1); | |
6532 | } | |
6533 | ||
6534 | /* last_function_call is inherited by bb_succ. */ | |
6535 | for (u = tmp_deps->last_function_call; u; u = XEXP (u, 1)) | |
6536 | { | |
6537 | if (find_insn_list (XEXP (u, 0), | |
6538 | succ_deps->last_function_call)) | |
6539 | continue; | |
6540 | ||
6541 | succ_deps->last_function_call | |
6542 | = alloc_INSN_LIST (XEXP (u, 0), | |
6543 | succ_deps->last_function_call); | |
6544 | } | |
6545 | ||
6546 | /* last_pending_memory_flush is inherited by bb_succ. */ | |
6547 | for (u = tmp_deps->last_pending_memory_flush; u; u = XEXP (u, 1)) | |
6548 | { | |
7a403706 | 6549 | if (find_insn_list (XEXP (u, 0), |
e1306f49 BS |
6550 | succ_deps->last_pending_memory_flush)) |
6551 | continue; | |
6552 | ||
6553 | succ_deps->last_pending_memory_flush | |
6554 | = alloc_INSN_LIST (XEXP (u, 0), | |
6555 | succ_deps->last_pending_memory_flush); | |
6556 | } | |
6557 | ||
6558 | /* sched_before_next_call is inherited by bb_succ. */ | |
6559 | x = LOG_LINKS (tmp_deps->sched_before_next_call); | |
6560 | for (; x; x = XEXP (x, 1)) | |
6561 | add_dependence (succ_deps->sched_before_next_call, | |
6562 | XEXP (x, 0), REG_DEP_ANTI); | |
6563 | ||
6564 | e = NEXT_OUT (e); | |
6565 | } | |
6566 | while (e != first_edge); | |
6567 | } | |
6568 | ||
63de6c74 | 6569 | /* Compute backward dependences inside bb. In a multiple blocks region: |
8c660648 JL |
6570 | (1) a bb is analyzed after its predecessors, and (2) the lists in |
6571 | effect at the end of bb (after analyzing for bb) are inherited by | |
6572 | bb's successrs. | |
6573 | ||
6574 | Specifically for reg-reg data dependences, the block insns are | |
6575 | scanned by sched_analyze () top-to-bottom. Two lists are | |
63de6c74 | 6576 | maintained by sched_analyze (): reg_last_sets[] for register DEFs, |
8c660648 JL |
6577 | and reg_last_uses[] for register USEs. |
6578 | ||
6579 | When analysis is completed for bb, we update for its successors: | |
6580 | ; - DEFS[succ] = Union (DEFS [succ], DEFS [bb]) | |
6581 | ; - USES[succ] = Union (USES [succ], DEFS [bb]) | |
6582 | ||
6583 | The mechanism for computing mem-mem data dependence is very | |
6584 | similar, and the result is interblock dependences in the region. */ | |
6585 | ||
6586 | static void | |
6587 | compute_block_backward_dependences (bb) | |
6588 | int bb; | |
6589 | { | |
e1306f49 | 6590 | int i; |
8c660648 JL |
6591 | rtx head, tail; |
6592 | int max_reg = max_reg_num (); | |
e1306f49 | 6593 | struct deps tmp_deps; |
8c660648 | 6594 | |
e1306f49 | 6595 | tmp_deps = bb_deps[bb]; |
8c660648 | 6596 | |
63de6c74 | 6597 | /* Do the analysis for this block. */ |
49c3bb12 | 6598 | get_bb_head_tail (bb, &head, &tail); |
e1306f49 | 6599 | sched_analyze (&tmp_deps, head, tail); |
8c660648 JL |
6600 | add_branch_dependences (head, tail); |
6601 | ||
6602 | if (current_nr_blocks > 1) | |
e1306f49 | 6603 | propagate_deps (bb, &tmp_deps, max_reg); |
ebb7b10b | 6604 | |
63de6c74 | 6605 | /* Free up the INSN_LISTs. |
7eea6443 | 6606 | |
7a403706 | 6607 | Note this loop is executed max_reg * nr_regions times. It's first |
5a4f6418 | 6608 | implementation accounted for over 90% of the calls to free_INSN_LIST_list. |
7a403706 | 6609 | The list was empty for the vast majority of those calls. On the PA, not |
5a4f6418 | 6610 | calling free_INSN_LIST_list in those cases improves -O2 compile times by |
7eea6443 | 6611 | 3-5% on average. */ |
e1306f49 | 6612 | for (i = 0; i < max_reg; ++i) |
ebb7b10b | 6613 | { |
e1306f49 BS |
6614 | if (tmp_deps.reg_last_clobbers[i]) |
6615 | free_INSN_LIST_list (&tmp_deps.reg_last_clobbers[i]); | |
6616 | if (tmp_deps.reg_last_sets[i]) | |
6617 | free_INSN_LIST_list (&tmp_deps.reg_last_sets[i]); | |
6618 | if (tmp_deps.reg_last_uses[i]) | |
6619 | free_INSN_LIST_list (&tmp_deps.reg_last_uses[i]); | |
ebb7b10b RH |
6620 | } |
6621 | ||
6622 | /* Assert that we won't need bb_reg_last_* for this block anymore. */ | |
e1306f49 BS |
6623 | free (bb_deps[bb].reg_last_uses); |
6624 | free (bb_deps[bb].reg_last_sets); | |
6625 | free (bb_deps[bb].reg_last_clobbers); | |
6626 | bb_deps[bb].reg_last_uses = 0; | |
6627 | bb_deps[bb].reg_last_sets = 0; | |
6628 | bb_deps[bb].reg_last_clobbers = 0; | |
8c660648 JL |
6629 | } |
6630 | ||
63de6c74 | 6631 | /* Print dependences for debugging, callable from debugger. */ |
8c660648 JL |
6632 | |
6633 | void | |
6634 | debug_dependencies () | |
6635 | { | |
6636 | int bb; | |
6637 | ||
6638 | fprintf (dump, ";; --------------- forward dependences: ------------ \n"); | |
6639 | for (bb = 0; bb < current_nr_blocks; bb++) | |
6640 | { | |
6641 | if (1) | |
6642 | { | |
6643 | rtx head, tail; | |
6644 | rtx next_tail; | |
6645 | rtx insn; | |
6646 | ||
49c3bb12 | 6647 | get_bb_head_tail (bb, &head, &tail); |
8c660648 JL |
6648 | next_tail = NEXT_INSN (tail); |
6649 | fprintf (dump, "\n;; --- Region Dependences --- b %d bb %d \n", | |
6650 | BB_TO_BLOCK (bb), bb); | |
6651 | ||
6652 | fprintf (dump, ";; %7s%6s%6s%6s%6s%6s%11s%6s\n", | |
6653 | "insn", "code", "bb", "dep", "prio", "cost", "blockage", "units"); | |
6654 | fprintf (dump, ";; %7s%6s%6s%6s%6s%6s%11s%6s\n", | |
6655 | "----", "----", "--", "---", "----", "----", "--------", "-----"); | |
6656 | for (insn = head; insn != next_tail; insn = NEXT_INSN (insn)) | |
6657 | { | |
6658 | rtx link; | |
6659 | int unit, range; | |
6660 | ||
2c3c49de | 6661 | if (! INSN_P (insn)) |
8c660648 JL |
6662 | { |
6663 | int n; | |
6664 | fprintf (dump, ";; %6d ", INSN_UID (insn)); | |
6665 | if (GET_CODE (insn) == NOTE) | |
ebc25a17 MM |
6666 | { |
6667 | n = NOTE_LINE_NUMBER (insn); | |
6668 | if (n < 0) | |
6669 | fprintf (dump, "%s\n", GET_NOTE_INSN_NAME (n)); | |
6670 | else | |
6671 | fprintf (dump, "line %d, file %s\n", n, | |
6672 | NOTE_SOURCE_FILE (insn)); | |
6673 | } | |
6674 | else | |
4f64eaca | 6675 | fprintf (dump, " {%s}\n", GET_RTX_NAME (GET_CODE (insn))); |
8c660648 JL |
6676 | continue; |
6677 | } | |
6678 | ||
6679 | unit = insn_unit (insn); | |
6680 | range = (unit < 0 | |
6681 | || function_units[unit].blockage_range_function == 0) ? 0 : | |
6682 | function_units[unit].blockage_range_function (insn); | |
6683 | fprintf (dump, | |
6684 | ";; %s%5d%6d%6d%6d%6d%6d %3d -%3d ", | |
6685 | (SCHED_GROUP_P (insn) ? "+" : " "), | |
6686 | INSN_UID (insn), | |
6687 | INSN_CODE (insn), | |
6688 | INSN_BB (insn), | |
6689 | INSN_DEP_COUNT (insn), | |
6690 | INSN_PRIORITY (insn), | |
6691 | insn_cost (insn, 0, 0), | |
6692 | (int) MIN_BLOCKAGE_COST (range), | |
6693 | (int) MAX_BLOCKAGE_COST (range)); | |
6694 | insn_print_units (insn); | |
6695 | fprintf (dump, "\t: "); | |
6696 | for (link = INSN_DEPEND (insn); link; link = XEXP (link, 1)) | |
6697 | fprintf (dump, "%d ", INSN_UID (XEXP (link, 0))); | |
6698 | fprintf (dump, "\n"); | |
6699 | } | |
6700 | } | |
6701 | } | |
6702 | fprintf (dump, "\n"); | |
6703 | } | |
6704 | ||
63de6c74 | 6705 | /* Set_priorities: compute priority of each insn in the block. */ |
8c660648 JL |
6706 | |
6707 | static int | |
6708 | set_priorities (bb) | |
6709 | int bb; | |
6710 | { | |
6711 | rtx insn; | |
6712 | int n_insn; | |
6713 | ||
6714 | rtx tail; | |
6715 | rtx prev_head; | |
6716 | rtx head; | |
6717 | ||
49c3bb12 | 6718 | get_bb_head_tail (bb, &head, &tail); |
8c660648 JL |
6719 | prev_head = PREV_INSN (head); |
6720 | ||
2c3c49de | 6721 | if (head == tail && (! INSN_P (head))) |
8c660648 JL |
6722 | return 0; |
6723 | ||
6724 | n_insn = 0; | |
6725 | for (insn = tail; insn != prev_head; insn = PREV_INSN (insn)) | |
6726 | { | |
6727 | ||
6728 | if (GET_CODE (insn) == NOTE) | |
6729 | continue; | |
6730 | ||
6731 | if (!(SCHED_GROUP_P (insn))) | |
6732 | n_insn++; | |
6733 | (void) priority (insn); | |
6734 | } | |
6735 | ||
6736 | return n_insn; | |
6737 | } | |
6738 | ||
8c660648 JL |
6739 | /* Schedule a region. A region is either an inner loop, a loop-free |
6740 | subroutine, or a single basic block. Each bb in the region is | |
6741 | scheduled after its flow predecessors. */ | |
6742 | ||
6743 | static void | |
6744 | schedule_region (rgn) | |
6745 | int rgn; | |
6746 | { | |
6747 | int bb; | |
6748 | int rgn_n_insns = 0; | |
6749 | int sched_rgn_n_insns = 0; | |
ee25a7a5 MM |
6750 | regset_head reg_pending_sets_head; |
6751 | regset_head reg_pending_clobbers_head; | |
8c660648 | 6752 | |
63de6c74 | 6753 | /* Set variables for the current region. */ |
8c660648 JL |
6754 | current_nr_blocks = RGN_NR_BLOCKS (rgn); |
6755 | current_blocks = RGN_BLOCKS (rgn); | |
6756 | ||
ee25a7a5 MM |
6757 | reg_pending_sets = INITIALIZE_REG_SET (reg_pending_sets_head); |
6758 | reg_pending_clobbers = INITIALIZE_REG_SET (reg_pending_clobbers_head); | |
8c660648 JL |
6759 | reg_pending_sets_all = 0; |
6760 | ||
63de6c74 | 6761 | /* Initializations for region data dependence analyisis. */ |
e1306f49 BS |
6762 | bb_deps = (struct deps *) xmalloc (sizeof (struct deps) * current_nr_blocks); |
6763 | for (bb = 0; bb < current_nr_blocks; bb++) | |
6764 | init_deps (bb_deps + bb); | |
8c660648 | 6765 | |
63de6c74 | 6766 | /* Compute LOG_LINKS. */ |
8c660648 JL |
6767 | for (bb = 0; bb < current_nr_blocks; bb++) |
6768 | compute_block_backward_dependences (bb); | |
6769 | ||
63de6c74 | 6770 | /* Compute INSN_DEPEND. */ |
8c660648 JL |
6771 | for (bb = current_nr_blocks - 1; bb >= 0; bb--) |
6772 | compute_block_forward_dependences (bb); | |
6773 | ||
c46a37c4 | 6774 | /* Delete line notes and set priorities. */ |
8c660648 JL |
6775 | for (bb = 0; bb < current_nr_blocks; bb++) |
6776 | { | |
8c660648 JL |
6777 | if (write_symbols != NO_DEBUG) |
6778 | { | |
6779 | save_line_notes (bb); | |
6780 | rm_line_notes (bb); | |
6781 | } | |
6782 | ||
6783 | rgn_n_insns += set_priorities (bb); | |
6784 | } | |
6785 | ||
63de6c74 | 6786 | /* Compute interblock info: probabilities, split-edges, dominators, etc. */ |
8c660648 JL |
6787 | if (current_nr_blocks > 1) |
6788 | { | |
6789 | int i; | |
6790 | ||
98903742 | 6791 | prob = (float *) xmalloc ((current_nr_blocks) * sizeof (float)); |
8c660648 JL |
6792 | |
6793 | bbset_size = current_nr_blocks / HOST_BITS_PER_WIDE_INT + 1; | |
98903742 | 6794 | dom = (bbset *) xmalloc (current_nr_blocks * sizeof (bbset)); |
8c660648 | 6795 | for (i = 0; i < current_nr_blocks; i++) |
98903742 | 6796 | dom[i] = (bbset) xcalloc (bbset_size, sizeof (HOST_WIDE_INT)); |
8c660648 | 6797 | |
63de6c74 | 6798 | /* Edge to bit. */ |
8c660648 | 6799 | rgn_nr_edges = 0; |
98903742 | 6800 | edge_to_bit = (int *) xmalloc (nr_edges * sizeof (int)); |
8c660648 JL |
6801 | for (i = 1; i < nr_edges; i++) |
6802 | if (CONTAINING_RGN (FROM_BLOCK (i)) == rgn) | |
6803 | EDGE_TO_BIT (i) = rgn_nr_edges++; | |
98903742 | 6804 | rgn_edges = (int *) xmalloc (rgn_nr_edges * sizeof (int)); |
8c660648 JL |
6805 | |
6806 | rgn_nr_edges = 0; | |
6807 | for (i = 1; i < nr_edges; i++) | |
6808 | if (CONTAINING_RGN (FROM_BLOCK (i)) == (rgn)) | |
6809 | rgn_edges[rgn_nr_edges++] = i; | |
6810 | ||
63de6c74 | 6811 | /* Split edges. */ |
8c660648 | 6812 | edgeset_size = rgn_nr_edges / HOST_BITS_PER_WIDE_INT + 1; |
86133292 | 6813 | edgeset_bitsize = rgn_nr_edges; |
98903742 | 6814 | pot_split = (edgeset *) xmalloc (current_nr_blocks * sizeof (edgeset)); |
7a403706 | 6815 | ancestor_edges |
98903742 | 6816 | = (edgeset *) xmalloc (current_nr_blocks * sizeof (edgeset)); |
8c660648 JL |
6817 | for (i = 0; i < current_nr_blocks; i++) |
6818 | { | |
6819 | pot_split[i] = | |
98903742 | 6820 | (edgeset) xcalloc (edgeset_size, sizeof (HOST_WIDE_INT)); |
8c660648 | 6821 | ancestor_edges[i] = |
98903742 | 6822 | (edgeset) xcalloc (edgeset_size, sizeof (HOST_WIDE_INT)); |
8c660648 JL |
6823 | } |
6824 | ||
63de6c74 | 6825 | /* Compute probabilities, dominators, split_edges. */ |
8c660648 JL |
6826 | for (bb = 0; bb < current_nr_blocks; bb++) |
6827 | compute_dom_prob_ps (bb); | |
6828 | } | |
6829 | ||
63de6c74 | 6830 | /* Now we can schedule all blocks. */ |
8c660648 | 6831 | for (bb = 0; bb < current_nr_blocks; bb++) |
98903742 | 6832 | sched_rgn_n_insns += schedule_block (bb, rgn_n_insns); |
8c660648 | 6833 | |
63de6c74 | 6834 | /* Sanity check: verify that all region insns were scheduled. */ |
cc132865 JL |
6835 | if (sched_rgn_n_insns != rgn_n_insns) |
6836 | abort (); | |
8c660648 | 6837 | |
63de6c74 | 6838 | /* Restore line notes. */ |
8c660648 JL |
6839 | if (write_symbols != NO_DEBUG) |
6840 | { | |
6841 | for (bb = 0; bb < current_nr_blocks; bb++) | |
6842 | restore_line_notes (bb); | |
6843 | } | |
6844 | ||
63de6c74 | 6845 | /* Done with this region. */ |
8c660648 | 6846 | free_pending_lists (); |
f187056f JL |
6847 | |
6848 | FREE_REG_SET (reg_pending_sets); | |
28c95eff | 6849 | FREE_REG_SET (reg_pending_clobbers); |
98903742 | 6850 | |
e1306f49 BS |
6851 | free (bb_deps); |
6852 | ||
98903742 MM |
6853 | if (current_nr_blocks > 1) |
6854 | { | |
6855 | int i; | |
6856 | ||
98903742 MM |
6857 | free (prob); |
6858 | for (i = 0; i < current_nr_blocks; ++i) | |
6859 | { | |
6860 | free (dom[i]); | |
6861 | free (pot_split[i]); | |
6862 | free (ancestor_edges[i]); | |
6863 | } | |
6864 | free (dom); | |
6865 | free (edge_to_bit); | |
6866 | free (rgn_edges); | |
6867 | free (pot_split); | |
6868 | free (ancestor_edges); | |
6869 | } | |
8c660648 JL |
6870 | } |
6871 | ||
8c660648 JL |
6872 | /* The one entry point in this file. DUMP_FILE is the dump file for |
6873 | this pass. */ | |
6874 | ||
6875 | void | |
6876 | schedule_insns (dump_file) | |
6877 | FILE *dump_file; | |
6878 | { | |
49c3bb12 RH |
6879 | int *deaths_in_region; |
6880 | sbitmap blocks, large_region_blocks; | |
8c660648 JL |
6881 | int max_uid; |
6882 | int b; | |
8c660648 JL |
6883 | rtx insn; |
6884 | int rgn; | |
8c660648 | 6885 | int luid; |
49c3bb12 | 6886 | int any_large_regions; |
8c660648 | 6887 | |
63de6c74 | 6888 | /* Disable speculative loads in their presence if cc0 defined. */ |
8c660648 JL |
6889 | #ifdef HAVE_cc0 |
6890 | flag_schedule_speculative_load = 0; | |
6891 | #endif | |
6892 | ||
6893 | /* Taking care of this degenerate case makes the rest of | |
6894 | this code simpler. */ | |
6895 | if (n_basic_blocks == 0) | |
6896 | return; | |
6897 | ||
63de6c74 | 6898 | /* Set dump and sched_verbose for the desired debugging output. If no |
409f8483 DE |
6899 | dump-file was specified, but -fsched-verbose=N (any N), print to stderr. |
6900 | For -fsched-verbose=N, N>=10, print everything to stderr. */ | |
8c660648 JL |
6901 | sched_verbose = sched_verbose_param; |
6902 | if (sched_verbose_param == 0 && dump_file) | |
6903 | sched_verbose = 1; | |
6904 | dump = ((sched_verbose_param >= 10 || !dump_file) ? stderr : dump_file); | |
6905 | ||
6906 | nr_inter = 0; | |
6907 | nr_spec = 0; | |
6908 | ||
63de6c74 | 6909 | /* Initialize issue_rate. */ |
62d65906 | 6910 | issue_rate = ISSUE_RATE; |
8c660648 | 6911 | |
d3a923ee | 6912 | split_all_insns (1); |
8c660648 | 6913 | |
c88e8206 RH |
6914 | /* We use LUID 0 for the fake insn (UID 0) which holds dependencies for |
6915 | pseudos which do not cross calls. */ | |
6916 | max_uid = get_max_uid () + 1; | |
8c660648 | 6917 | |
f66d83e1 | 6918 | h_i_d = (struct haifa_insn_data *) xcalloc (max_uid, sizeof (*h_i_d)); |
8c660648 | 6919 | |
f66d83e1 | 6920 | h_i_d[0].luid = 0; |
356edbd7 | 6921 | luid = 1; |
8c660648 | 6922 | for (b = 0; b < n_basic_blocks; b++) |
3b413743 | 6923 | for (insn = BLOCK_HEAD (b);; insn = NEXT_INSN (insn)) |
8c660648 | 6924 | { |
f77e39fc MM |
6925 | INSN_LUID (insn) = luid; |
6926 | ||
6927 | /* Increment the next luid, unless this is a note. We don't | |
6928 | really need separate IDs for notes and we don't want to | |
6929 | schedule differently depending on whether or not there are | |
6930 | line-number notes, i.e., depending on whether or not we're | |
6931 | generating debugging information. */ | |
6932 | if (GET_CODE (insn) != NOTE) | |
6933 | ++luid; | |
6934 | ||
3b413743 | 6935 | if (insn == BLOCK_END (b)) |
8c660648 JL |
6936 | break; |
6937 | } | |
7a403706 | 6938 | |
356edbd7 JL |
6939 | /* ?!? We could save some memory by computing a per-region luid mapping |
6940 | which could reduce both the number of vectors in the cache and the size | |
aae0390e JL |
6941 | of each vector. Instead we just avoid the cache entirely unless the |
6942 | average number of instructions in a basic block is very high. See | |
6943 | the comment before the declaration of true_dependency_cache for | |
6944 | what we consider "very high". */ | |
6945 | if (luid / n_basic_blocks > 100 * 5) | |
6946 | { | |
6947 | true_dependency_cache = sbitmap_vector_alloc (luid, luid); | |
6948 | sbitmap_vector_zero (true_dependency_cache, luid); | |
178b88b9 VM |
6949 | anti_dependency_cache = sbitmap_vector_alloc (luid, luid); |
6950 | sbitmap_vector_zero (anti_dependency_cache, luid); | |
6951 | output_dependency_cache = sbitmap_vector_alloc (luid, luid); | |
6952 | sbitmap_vector_zero (output_dependency_cache, luid); | |
6953 | #ifdef ENABLE_CHECKING | |
6954 | forward_dependency_cache = sbitmap_vector_alloc (luid, luid); | |
6955 | sbitmap_vector_zero (forward_dependency_cache, luid); | |
6956 | #endif | |
aae0390e | 6957 | } |
8c660648 | 6958 | |
8c660648 | 6959 | nr_regions = 0; |
98903742 MM |
6960 | rgn_table = (region *) xmalloc ((n_basic_blocks) * sizeof (region)); |
6961 | rgn_bb_table = (int *) xmalloc ((n_basic_blocks) * sizeof (int)); | |
6962 | block_to_bb = (int *) xmalloc ((n_basic_blocks) * sizeof (int)); | |
6963 | containing_rgn = (int *) xmalloc ((n_basic_blocks) * sizeof (int)); | |
8c660648 | 6964 | |
49c3bb12 RH |
6965 | blocks = sbitmap_alloc (n_basic_blocks); |
6966 | large_region_blocks = sbitmap_alloc (n_basic_blocks); | |
6967 | ||
c88e8206 RH |
6968 | compute_bb_for_insn (max_uid); |
6969 | ||
63de6c74 | 6970 | /* Compute regions for scheduling. */ |
8c660648 JL |
6971 | if (reload_completed |
6972 | || n_basic_blocks == 1 | |
6973 | || !flag_schedule_interblock) | |
6974 | { | |
6975 | find_single_block_region (); | |
6976 | } | |
6977 | else | |
6978 | { | |
63de6c74 | 6979 | /* Verify that a 'good' control flow graph can be built. */ |
168cbdf9 | 6980 | if (is_cfg_nonregular ()) |
8c660648 JL |
6981 | { |
6982 | find_single_block_region (); | |
6983 | } | |
6984 | else | |
6985 | { | |
092ae4ba | 6986 | sbitmap *dom; |
6b8cf0c5 | 6987 | struct edge_list *edge_list; |
a2e68776 | 6988 | |
a2e68776 | 6989 | dom = sbitmap_vector_alloc (n_basic_blocks, n_basic_blocks); |
a2e68776 JL |
6990 | |
6991 | /* The scheduler runs after flow; therefore, we can't blindly call | |
6992 | back into find_basic_blocks since doing so could invalidate the | |
e881bb1b | 6993 | info in global_live_at_start. |
a2e68776 JL |
6994 | |
6995 | Consider a block consisting entirely of dead stores; after life | |
6996 | analysis it would be a block of NOTE_INSN_DELETED notes. If | |
6997 | we call find_basic_blocks again, then the block would be removed | |
6998 | entirely and invalidate our the register live information. | |
6999 | ||
7000 | We could (should?) recompute register live information. Doing | |
7001 | so may even be beneficial. */ | |
6b8cf0c5 | 7002 | edge_list = create_edge_list (); |
a2e68776 | 7003 | |
63de6c74 MH |
7004 | /* Compute the dominators and post dominators. We don't |
7005 | currently use post dominators, but we should for | |
7006 | speculative motion analysis. */ | |
092ae4ba | 7007 | compute_flow_dominators (dom, NULL); |
a2e68776 | 7008 | |
168cbdf9 JL |
7009 | /* build_control_flow will return nonzero if it detects unreachable |
7010 | blocks or any other irregularity with the cfg which prevents | |
7011 | cross block scheduling. */ | |
6b8cf0c5 | 7012 | if (build_control_flow (edge_list) != 0) |
168cbdf9 JL |
7013 | find_single_block_region (); |
7014 | else | |
6b8cf0c5 | 7015 | find_rgns (edge_list, dom); |
8c660648 JL |
7016 | |
7017 | if (sched_verbose >= 3) | |
a2e68776 | 7018 | debug_regions (); |
8c660648 | 7019 | |
4e95db71 JL |
7020 | /* We are done with flow's edge list. */ |
7021 | free_edge_list (edge_list); | |
7022 | ||
a2e68776 | 7023 | /* For now. This will move as more and more of haifa is converted |
63de6c74 | 7024 | to using the cfg code in flow.c. */ |
a2e68776 | 7025 | free (dom); |
8c660648 JL |
7026 | } |
7027 | } | |
7028 | ||
231a2226 | 7029 | deaths_in_region = (int *) xmalloc (sizeof (int) * nr_regions); |
49c3bb12 | 7030 | |
8c660648 JL |
7031 | init_alias_analysis (); |
7032 | ||
7033 | if (write_symbols != NO_DEBUG) | |
7034 | { | |
7035 | rtx line; | |
7036 | ||
98903742 | 7037 | line_note_head = (rtx *) xcalloc (n_basic_blocks, sizeof (rtx)); |
8c660648 JL |
7038 | |
7039 | /* Save-line-note-head: | |
7040 | Determine the line-number at the start of each basic block. | |
7041 | This must be computed and saved now, because after a basic block's | |
7042 | predecessor has been scheduled, it is impossible to accurately | |
7043 | determine the correct line number for the first insn of the block. */ | |
7044 | ||
7045 | for (b = 0; b < n_basic_blocks; b++) | |
3b413743 | 7046 | for (line = BLOCK_HEAD (b); line; line = PREV_INSN (line)) |
8c660648 JL |
7047 | if (GET_CODE (line) == NOTE && NOTE_LINE_NUMBER (line) > 0) |
7048 | { | |
7049 | line_note_head[b] = line; | |
7050 | break; | |
7051 | } | |
7052 | } | |
7053 | ||
63de6c74 | 7054 | /* Find units used in this fuction, for visualization. */ |
8c660648 JL |
7055 | if (sched_verbose) |
7056 | init_target_units (); | |
7057 | ||
7058 | /* ??? Add a NOTE after the last insn of the last basic block. It is not | |
7059 | known why this is done. */ | |
7060 | ||
3b413743 | 7061 | insn = BLOCK_END (n_basic_blocks - 1); |
8c660648 JL |
7062 | if (NEXT_INSN (insn) == 0 |
7063 | || (GET_CODE (insn) != NOTE | |
7064 | && GET_CODE (insn) != CODE_LABEL | |
3b413743 RH |
7065 | /* Don't emit a NOTE if it would end up between an unconditional |
7066 | jump and a BARRIER. */ | |
8c660648 JL |
7067 | && !(GET_CODE (insn) == JUMP_INSN |
7068 | && GET_CODE (NEXT_INSN (insn)) == BARRIER))) | |
3b413743 | 7069 | emit_note_after (NOTE_INSN_DELETED, BLOCK_END (n_basic_blocks - 1)); |
8c660648 | 7070 | |
49c3bb12 RH |
7071 | /* Compute INSN_REG_WEIGHT for all blocks. We must do this before |
7072 | removing death notes. */ | |
7073 | for (b = n_basic_blocks - 1; b >= 0; b--) | |
7074 | find_insn_reg_weight (b); | |
7075 | ||
7076 | /* Remove all death notes from the subroutine. */ | |
7077 | for (rgn = 0; rgn < nr_regions; rgn++) | |
7078 | { | |
7079 | sbitmap_zero (blocks); | |
7080 | for (b = RGN_NR_BLOCKS (rgn) - 1; b >= 0; --b) | |
7a403706 | 7081 | SET_BIT (blocks, rgn_bb_table[RGN_BLOCKS (rgn) + b]); |
49c3bb12 RH |
7082 | |
7083 | deaths_in_region[rgn] = count_or_remove_death_notes (blocks, 1); | |
7084 | } | |
7085 | ||
63de6c74 | 7086 | /* Schedule every region in the subroutine. */ |
8c660648 | 7087 | for (rgn = 0; rgn < nr_regions; rgn++) |
98903742 | 7088 | schedule_region (rgn); |
8c660648 | 7089 | |
49c3bb12 RH |
7090 | /* Update life analysis for the subroutine. Do single block regions |
7091 | first so that we can verify that live_at_start didn't change. Then | |
7092 | do all other blocks. */ | |
7093 | /* ??? There is an outside possibility that update_life_info, or more | |
7094 | to the point propagate_block, could get called with non-zero flags | |
7095 | more than once for one basic block. This would be kinda bad if it | |
7096 | were to happen, since REG_INFO would be accumulated twice for the | |
7097 | block, and we'd have twice the REG_DEAD notes. | |
7098 | ||
7099 | I'm fairly certain that this _shouldn't_ happen, since I don't think | |
7100 | that live_at_start should change at region heads. Not sure what the | |
7a403706 | 7101 | best way to test for this kind of thing... */ |
49c3bb12 RH |
7102 | |
7103 | allocate_reg_life_data (); | |
7104 | compute_bb_for_insn (max_uid); | |
7105 | ||
7106 | any_large_regions = 0; | |
7107 | sbitmap_ones (large_region_blocks); | |
7108 | ||
7109 | for (rgn = 0; rgn < nr_regions; rgn++) | |
7110 | if (RGN_NR_BLOCKS (rgn) > 1) | |
7111 | any_large_regions = 1; | |
7112 | else | |
7113 | { | |
7114 | sbitmap_zero (blocks); | |
7115 | SET_BIT (blocks, rgn_bb_table[RGN_BLOCKS (rgn)]); | |
7116 | RESET_BIT (large_region_blocks, rgn_bb_table[RGN_BLOCKS (rgn)]); | |
7117 | ||
47e6ea66 RH |
7118 | /* Don't update reg info after reload, since that affects |
7119 | regs_ever_live, which should not change after reload. */ | |
49c3bb12 | 7120 | update_life_info (blocks, UPDATE_LIFE_LOCAL, |
47e6ea66 RH |
7121 | (reload_completed ? PROP_DEATH_NOTES |
7122 | : PROP_DEATH_NOTES | PROP_REG_INFO)); | |
49c3bb12 | 7123 | |
11ae508b RH |
7124 | #ifndef HAVE_conditional_execution |
7125 | /* ??? REG_DEAD notes only exist for unconditional deaths. We need | |
7126 | a count of the conditional plus unconditional deaths for this to | |
7127 | work out. */ | |
49c3bb12 RH |
7128 | /* In the single block case, the count of registers that died should |
7129 | not have changed during the schedule. */ | |
7130 | if (count_or_remove_death_notes (blocks, 0) != deaths_in_region[rgn]) | |
7a403706 | 7131 | abort (); |
11ae508b | 7132 | #endif |
49c3bb12 RH |
7133 | } |
7134 | ||
7135 | if (any_large_regions) | |
7136 | { | |
7137 | update_life_info (large_region_blocks, UPDATE_LIFE_GLOBAL, | |
7a403706 | 7138 | PROP_DEATH_NOTES | PROP_REG_INFO); |
49c3bb12 RH |
7139 | } |
7140 | ||
8c660648 JL |
7141 | /* Reposition the prologue and epilogue notes in case we moved the |
7142 | prologue/epilogue insns. */ | |
7143 | if (reload_completed) | |
7144 | reposition_prologue_and_epilogue_notes (get_insns ()); | |
7145 | ||
63de6c74 | 7146 | /* Delete redundant line notes. */ |
8c660648 JL |
7147 | if (write_symbols != NO_DEBUG) |
7148 | rm_redundant_line_notes (); | |
7149 | ||
8c660648 JL |
7150 | if (sched_verbose) |
7151 | { | |
7152 | if (reload_completed == 0 && flag_schedule_interblock) | |
7153 | { | |
7a403706 KH |
7154 | fprintf (dump, |
7155 | "\n;; Procedure interblock/speculative motions == %d/%d \n", | |
8c660648 JL |
7156 | nr_inter, nr_spec); |
7157 | } | |
7158 | else | |
7159 | { | |
7160 | if (nr_inter > 0) | |
7161 | abort (); | |
7162 | } | |
7163 | fprintf (dump, "\n\n"); | |
7164 | } | |
f187056f | 7165 | |
e05e2395 MM |
7166 | /* Clean up. */ |
7167 | end_alias_analysis (); | |
7168 | ||
aae0390e JL |
7169 | if (true_dependency_cache) |
7170 | { | |
7171 | free (true_dependency_cache); | |
60588660 | 7172 | true_dependency_cache = NULL; |
178b88b9 VM |
7173 | free (anti_dependency_cache); |
7174 | anti_dependency_cache = NULL; | |
7175 | free (output_dependency_cache); | |
7176 | output_dependency_cache = NULL; | |
7177 | #ifdef ENABLE_CHECKING | |
4071f896 | 7178 | free (forward_dependency_cache); |
178b88b9 VM |
7179 | forward_dependency_cache = NULL; |
7180 | #endif | |
aae0390e | 7181 | } |
98903742 MM |
7182 | free (rgn_table); |
7183 | free (rgn_bb_table); | |
7184 | free (block_to_bb); | |
7185 | free (containing_rgn); | |
f66d83e1 RH |
7186 | |
7187 | free (h_i_d); | |
7c74b010 JW |
7188 | |
7189 | if (write_symbols != NO_DEBUG) | |
f66d83e1 | 7190 | free (line_note_head); |
7c74b010 | 7191 | |
168cbdf9 JL |
7192 | if (edge_table) |
7193 | { | |
7194 | free (edge_table); | |
7195 | edge_table = NULL; | |
7196 | } | |
7197 | ||
7198 | if (in_edges) | |
7199 | { | |
7200 | free (in_edges); | |
7201 | in_edges = NULL; | |
7202 | } | |
7203 | if (out_edges) | |
7204 | { | |
7205 | free (out_edges); | |
7206 | out_edges = NULL; | |
7207 | } | |
49c3bb12 RH |
7208 | |
7209 | sbitmap_free (blocks); | |
7210 | sbitmap_free (large_region_blocks); | |
98903742 MM |
7211 | |
7212 | free (deaths_in_region); | |
8c660648 | 7213 | } |
98903742 | 7214 | |
8c660648 | 7215 | #endif /* INSN_SCHEDULING */ |