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f4e584dc 1/* Global common subexpression elimination/Partial redundancy elimination
7506f491 2 and global constant/copy propagation for GNU compiler.
62e5bf5d 3 Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005,
6216f94e 4 2006, 2007, 2008, 2009 Free Software Foundation, Inc.
7506f491 5
1322177d 6This file is part of GCC.
7506f491 7
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8GCC is free software; you can redistribute it and/or modify it under
9the terms of the GNU General Public License as published by the Free
9dcd6f09 10Software Foundation; either version 3, or (at your option) any later
1322177d 11version.
7506f491 12
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13GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14WARRANTY; without even the implied warranty of MERCHANTABILITY or
15FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16for more details.
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17
18You should have received a copy of the GNU General Public License
9dcd6f09
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19along with GCC; see the file COPYING3. If not see
20<http://www.gnu.org/licenses/>. */
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21
22/* TODO
23 - reordering of memory allocation and freeing to be more space efficient
24 - do rough calc of how many regs are needed in each block, and a rough
25 calc of how many regs are available in each class and use that to
26 throttle back the code in cases where RTX_COST is minimal.
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27 - a store to the same address as a load does not kill the load if the
28 source of the store is also the destination of the load. Handling this
29 allows more load motion, particularly out of loops.
7506f491 30
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31*/
32
33/* References searched while implementing this.
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34
35 Compilers Principles, Techniques and Tools
36 Aho, Sethi, Ullman
37 Addison-Wesley, 1988
38
39 Global Optimization by Suppression of Partial Redundancies
40 E. Morel, C. Renvoise
41 communications of the acm, Vol. 22, Num. 2, Feb. 1979
42
43 A Portable Machine-Independent Global Optimizer - Design and Measurements
44 Frederick Chow
45 Stanford Ph.D. thesis, Dec. 1983
46
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47 A Fast Algorithm for Code Movement Optimization
48 D.M. Dhamdhere
49 SIGPLAN Notices, Vol. 23, Num. 10, Oct. 1988
50
51 A Solution to a Problem with Morel and Renvoise's
52 Global Optimization by Suppression of Partial Redundancies
53 K-H Drechsler, M.P. Stadel
54 ACM TOPLAS, Vol. 10, Num. 4, Oct. 1988
55
56 Practical Adaptation of the Global Optimization
57 Algorithm of Morel and Renvoise
58 D.M. Dhamdhere
59 ACM TOPLAS, Vol. 13, Num. 2. Apr. 1991
60
61 Efficiently Computing Static Single Assignment Form and the Control
62 Dependence Graph
63 R. Cytron, J. Ferrante, B.K. Rosen, M.N. Wegman, and F.K. Zadeck
64 ACM TOPLAS, Vol. 13, Num. 4, Oct. 1991
65
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66 Lazy Code Motion
67 J. Knoop, O. Ruthing, B. Steffen
68 ACM SIGPLAN Notices Vol. 27, Num. 7, Jul. 1992, '92 Conference on PLDI
69
70 What's In a Region? Or Computing Control Dependence Regions in Near-Linear
71 Time for Reducible Flow Control
72 Thomas Ball
73 ACM Letters on Programming Languages and Systems,
74 Vol. 2, Num. 1-4, Mar-Dec 1993
75
76 An Efficient Representation for Sparse Sets
77 Preston Briggs, Linda Torczon
78 ACM Letters on Programming Languages and Systems,
79 Vol. 2, Num. 1-4, Mar-Dec 1993
80
81 A Variation of Knoop, Ruthing, and Steffen's Lazy Code Motion
82 K-H Drechsler, M.P. Stadel
83 ACM SIGPLAN Notices, Vol. 28, Num. 5, May 1993
84
85 Partial Dead Code Elimination
86 J. Knoop, O. Ruthing, B. Steffen
87 ACM SIGPLAN Notices, Vol. 29, Num. 6, Jun. 1994
88
89 Effective Partial Redundancy Elimination
90 P. Briggs, K.D. Cooper
91 ACM SIGPLAN Notices, Vol. 29, Num. 6, Jun. 1994
92
93 The Program Structure Tree: Computing Control Regions in Linear Time
94 R. Johnson, D. Pearson, K. Pingali
95 ACM SIGPLAN Notices, Vol. 29, Num. 6, Jun. 1994
96
97 Optimal Code Motion: Theory and Practice
98 J. Knoop, O. Ruthing, B. Steffen
99 ACM TOPLAS, Vol. 16, Num. 4, Jul. 1994
100
101 The power of assignment motion
102 J. Knoop, O. Ruthing, B. Steffen
103 ACM SIGPLAN Notices Vol. 30, Num. 6, Jun. 1995, '95 Conference on PLDI
104
105 Global code motion / global value numbering
106 C. Click
107 ACM SIGPLAN Notices Vol. 30, Num. 6, Jun. 1995, '95 Conference on PLDI
108
109 Value Driven Redundancy Elimination
110 L.T. Simpson
111 Rice University Ph.D. thesis, Apr. 1996
112
113 Value Numbering
114 L.T. Simpson
115 Massively Scalar Compiler Project, Rice University, Sep. 1996
116
117 High Performance Compilers for Parallel Computing
118 Michael Wolfe
119 Addison-Wesley, 1996
120
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121 Advanced Compiler Design and Implementation
122 Steven Muchnick
123 Morgan Kaufmann, 1997
124
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125 Building an Optimizing Compiler
126 Robert Morgan
127 Digital Press, 1998
128
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129 People wishing to speed up the code here should read:
130 Elimination Algorithms for Data Flow Analysis
131 B.G. Ryder, M.C. Paull
132 ACM Computing Surveys, Vol. 18, Num. 3, Sep. 1986
133
134 How to Analyze Large Programs Efficiently and Informatively
135 D.M. Dhamdhere, B.K. Rosen, F.K. Zadeck
136 ACM SIGPLAN Notices Vol. 27, Num. 7, Jul. 1992, '92 Conference on PLDI
137
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138 People wishing to do something different can find various possibilities
139 in the above papers and elsewhere.
140*/
141
142#include "config.h"
50b2596f 143#include "system.h"
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144#include "coretypes.h"
145#include "tm.h"
01198c2f 146#include "toplev.h"
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147
148#include "rtl.h"
b0656d8b 149#include "tree.h"
6baf1cc8 150#include "tm_p.h"
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151#include "regs.h"
152#include "hard-reg-set.h"
153#include "flags.h"
154#include "real.h"
155#include "insn-config.h"
156#include "recog.h"
157#include "basic-block.h"
50b2596f 158#include "output.h"
49ad7cfa 159#include "function.h"
589005ff 160#include "expr.h"
e7d482b9 161#include "except.h"
fb0c0a12 162#include "ggc.h"
f1fa37ff 163#include "params.h"
ae860ff7 164#include "cselib.h"
d128effb 165#include "intl.h"
7506f491 166#include "obstack.h"
27fb79ad 167#include "timevar.h"
ef330312 168#include "tree-pass.h"
9727e468 169#include "hashtab.h"
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170#include "df.h"
171#include "dbgcnt.h"
ec0a1343 172#include "target.h"
4fa31c2a 173
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174/* Propagate flow information through back edges and thus enable PRE's
175 moving loop invariant calculations out of loops.
176
177 Originally this tended to create worse overall code, but several
178 improvements during the development of PRE seem to have made following
179 back edges generally a win.
180
181 Note much of the loop invariant code motion done here would normally
182 be done by loop.c, which has more heuristics for when to move invariants
183 out of loops. At some point we might need to move some of those
184 heuristics into gcse.c. */
7506f491 185
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186/* We support GCSE via Partial Redundancy Elimination. PRE optimizations
187 are a superset of those done by GCSE.
7506f491 188
f4e584dc 189 We perform the following steps:
7506f491 190
3906a4a1 191 1) Compute table of places where registers are set.
7506f491 192
3906a4a1 193 2) Perform copy/constant propagation.
7506f491 194
3906a4a1 195 3) Perform global cse using lazy code motion if not optimizing
e83f4801 196 for size, or code hoisting if we are.
7506f491 197
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198 4) Perform another pass of copy/constant propagation. Try to bypass
199 conditional jumps if the condition can be computed from a value of
200 an incoming edge.
201
202 5) Perform store motion.
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203
204 Two passes of copy/constant propagation are done because the first one
205 enables more GCSE and the second one helps to clean up the copies that
206 GCSE creates. This is needed more for PRE than for Classic because Classic
207 GCSE will try to use an existing register containing the common
208 subexpression rather than create a new one. This is harder to do for PRE
209 because of the code motion (which Classic GCSE doesn't do).
210
211 Expressions we are interested in GCSE-ing are of the form
212 (set (pseudo-reg) (expression)).
213 Function want_to_gcse_p says what these are.
214
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215 In addition, expressions in REG_EQUAL notes are candidates for GXSE-ing.
216 This allows PRE to hoist expressions that are expressed in multiple insns,
b8698a0f 217 such as comprex address calculations (e.g. for PIC code, or loads with a
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218 high part and as lowe part).
219
7506f491 220 PRE handles moving invariant expressions out of loops (by treating them as
f4e584dc 221 partially redundant).
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222
223 Eventually it would be nice to replace cse.c/gcse.c with SSA (static single
224 assignment) based GVN (global value numbering). L. T. Simpson's paper
225 (Rice University) on value numbering is a useful reference for this.
226
227 **********************
228
229 We used to support multiple passes but there are diminishing returns in
230 doing so. The first pass usually makes 90% of the changes that are doable.
231 A second pass can make a few more changes made possible by the first pass.
232 Experiments show any further passes don't make enough changes to justify
233 the expense.
234
235 A study of spec92 using an unlimited number of passes:
236 [1 pass] = 1208 substitutions, [2] = 577, [3] = 202, [4] = 192, [5] = 83,
237 [6] = 34, [7] = 17, [8] = 9, [9] = 4, [10] = 4, [11] = 2,
238 [12] = 2, [13] = 1, [15] = 1, [16] = 2, [41] = 1
239
240 It was found doing copy propagation between each pass enables further
241 substitutions.
242
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243 This study was done before expressions in REG_EQUAL notes were added as
244 candidate expressions for optimization, and before the GIMPLE optimizers
245 were added. Probably, multiple passes is even less efficient now than
246 at the time when the study was conducted.
247
7506f491 248 PRE is quite expensive in complicated functions because the DFA can take
3906a4a1 249 a while to converge. Hence we only perform one pass.
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250
251 **********************
252
253 The steps for PRE are:
254
255 1) Build the hash table of expressions we wish to GCSE (expr_hash_table).
256
257 2) Perform the data flow analysis for PRE.
258
259 3) Delete the redundant instructions
260
261 4) Insert the required copies [if any] that make the partially
262 redundant instructions fully redundant.
263
264 5) For other reaching expressions, insert an instruction to copy the value
265 to a newly created pseudo that will reach the redundant instruction.
266
267 The deletion is done first so that when we do insertions we
268 know which pseudo reg to use.
269
270 Various papers have argued that PRE DFA is expensive (O(n^2)) and others
271 argue it is not. The number of iterations for the algorithm to converge
272 is typically 2-4 so I don't view it as that expensive (relatively speaking).
273
f4e584dc 274 PRE GCSE depends heavily on the second CSE pass to clean up the copies
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275 we create. To make an expression reach the place where it's redundant,
276 the result of the expression is copied to a new register, and the redundant
277 expression is deleted by replacing it with this new register. Classic GCSE
278 doesn't have this problem as much as it computes the reaching defs of
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279 each register in each block and thus can try to use an existing
280 register. */
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281\f
282/* GCSE global vars. */
283
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284/* Set to non-zero if CSE should run after all GCSE optimizations are done. */
285int flag_rerun_cse_after_global_opts;
f4e584dc 286
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287/* An obstack for our working variables. */
288static struct obstack gcse_obstack;
289
c4c81601 290struct reg_use {rtx reg_rtx; };
abd535b6 291
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292/* Hash table of expressions. */
293
294struct expr
295{
296 /* The expression (SET_SRC for expressions, PATTERN for assignments). */
297 rtx expr;
298 /* Index in the available expression bitmaps. */
299 int bitmap_index;
300 /* Next entry with the same hash. */
301 struct expr *next_same_hash;
302 /* List of anticipatable occurrences in basic blocks in the function.
303 An "anticipatable occurrence" is one that is the first occurrence in the
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304 basic block, the operands are not modified in the basic block prior
305 to the occurrence and the output is not used between the start of
306 the block and the occurrence. */
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307 struct occr *antic_occr;
308 /* List of available occurrence in basic blocks in the function.
309 An "available occurrence" is one that is the last occurrence in the
310 basic block and the operands are not modified by following statements in
311 the basic block [including this insn]. */
312 struct occr *avail_occr;
313 /* Non-null if the computation is PRE redundant.
314 The value is the newly created pseudo-reg to record a copy of the
315 expression in all the places that reach the redundant copy. */
316 rtx reaching_reg;
317};
318
319/* Occurrence of an expression.
320 There is one per basic block. If a pattern appears more than once the
321 last appearance is used [or first for anticipatable expressions]. */
322
323struct occr
324{
325 /* Next occurrence of this expression. */
326 struct occr *next;
327 /* The insn that computes the expression. */
328 rtx insn;
cc2902df 329 /* Nonzero if this [anticipatable] occurrence has been deleted. */
7506f491 330 char deleted_p;
cc2902df 331 /* Nonzero if this [available] occurrence has been copied to
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332 reaching_reg. */
333 /* ??? This is mutually exclusive with deleted_p, so they could share
334 the same byte. */
335 char copied_p;
336};
337
338/* Expression and copy propagation hash tables.
339 Each hash table is an array of buckets.
340 ??? It is known that if it were an array of entries, structure elements
341 `next_same_hash' and `bitmap_index' wouldn't be necessary. However, it is
342 not clear whether in the final analysis a sufficient amount of memory would
343 be saved as the size of the available expression bitmaps would be larger
344 [one could build a mapping table without holes afterwards though].
c4c81601 345 Someday I'll perform the computation and figure it out. */
7506f491 346
7e5487a2 347struct hash_table_d
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348{
349 /* The table itself.
350 This is an array of `expr_hash_table_size' elements. */
351 struct expr **table;
352
353 /* Size of the hash table, in elements. */
354 unsigned int size;
2e653e39 355
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356 /* Number of hash table elements. */
357 unsigned int n_elems;
7506f491 358
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359 /* Whether the table is expression of copy propagation one. */
360 int set_p;
361};
c4c81601 362
02280659 363/* Expression hash table. */
7e5487a2 364static struct hash_table_d expr_hash_table;
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365
366/* Copy propagation hash table. */
7e5487a2 367static struct hash_table_d set_hash_table;
7506f491 368
a13d4ebf 369/* This is a list of expressions which are MEMs and will be used by load
589005ff 370 or store motion.
a13d4ebf 371 Load motion tracks MEMs which aren't killed by
454ff5cb 372 anything except itself. (i.e., loads and stores to a single location).
589005ff 373 We can then allow movement of these MEM refs with a little special
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374 allowance. (all stores copy the same value to the reaching reg used
375 for the loads). This means all values used to store into memory must have
589005ff 376 no side effects so we can re-issue the setter value.
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377 Store Motion uses this structure as an expression table to track stores
378 which look interesting, and might be moveable towards the exit block. */
379
380struct ls_expr
381{
382 struct expr * expr; /* Gcse expression reference for LM. */
383 rtx pattern; /* Pattern of this mem. */
47a3dae1 384 rtx pattern_regs; /* List of registers mentioned by the mem. */
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385 rtx loads; /* INSN list of loads seen. */
386 rtx stores; /* INSN list of stores seen. */
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387 struct ls_expr * next; /* Next in the list. */
388 int invalid; /* Invalid for some reason. */
389 int index; /* If it maps to a bitmap index. */
b58b21d5 390 unsigned int hash_index; /* Index when in a hash table. */
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391 rtx reaching_reg; /* Register to use when re-writing. */
392};
393
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394/* Array of implicit set patterns indexed by basic block index. */
395static rtx *implicit_sets;
396
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397/* Head of the list of load/store memory refs. */
398static struct ls_expr * pre_ldst_mems = NULL;
399
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400/* Hashtable for the load/store memory refs. */
401static htab_t pre_ldst_table = NULL;
402
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403/* Bitmap containing one bit for each register in the program.
404 Used when performing GCSE to track which registers have been set since
405 the start of the basic block. */
73991d6a 406static regset reg_set_bitmap;
7506f491 407
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408/* Array, indexed by basic block number for a list of insns which modify
409 memory within that block. */
410static rtx * modify_mem_list;
0516f6fe 411static bitmap modify_mem_list_set;
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412
413/* This array parallels modify_mem_list, but is kept canonicalized. */
414static rtx * canon_modify_mem_list;
0516f6fe 415
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416/* Bitmap indexed by block numbers to record which blocks contain
417 function calls. */
418static bitmap blocks_with_calls;
419
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420/* Various variables for statistics gathering. */
421
422/* Memory used in a pass.
423 This isn't intended to be absolutely precise. Its intent is only
424 to keep an eye on memory usage. */
425static int bytes_used;
c4c81601 426
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427/* GCSE substitutions made. */
428static int gcse_subst_count;
429/* Number of copy instructions created. */
430static int gcse_create_count;
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431/* Number of local constants propagated. */
432static int local_const_prop_count;
0fa2e4df 433/* Number of local copies propagated. */
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434static int local_copy_prop_count;
435/* Number of global constants propagated. */
436static int global_const_prop_count;
0fa2e4df 437/* Number of global copies propagated. */
27fb79ad 438static int global_copy_prop_count;
7506f491 439\f
e83f4801 440/* For available exprs */
df35c271 441static sbitmap *ae_kill;
7506f491 442\f
1d088dee 443static void compute_can_copy (void);
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444static void *gmalloc (size_t) ATTRIBUTE_MALLOC;
445static void *gcalloc (size_t, size_t) ATTRIBUTE_MALLOC;
703ad42b 446static void *gcse_alloc (unsigned long);
eb232f4e 447static void alloc_gcse_mem (void);
1d088dee 448static void free_gcse_mem (void);
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449static void hash_scan_insn (rtx, struct hash_table_d *);
450static void hash_scan_set (rtx, rtx, struct hash_table_d *);
451static void hash_scan_clobber (rtx, rtx, struct hash_table_d *);
452static void hash_scan_call (rtx, rtx, struct hash_table_d *);
1d088dee 453static int want_to_gcse_p (rtx);
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454static bool gcse_constant_p (const_rtx);
455static int oprs_unchanged_p (const_rtx, const_rtx, int);
456static int oprs_anticipatable_p (const_rtx, const_rtx);
457static int oprs_available_p (const_rtx, const_rtx);
1d088dee 458static void insert_expr_in_table (rtx, enum machine_mode, rtx, int, int,
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459 struct hash_table_d *);
460static void insert_set_in_table (rtx, rtx, struct hash_table_d *);
ed7a4b4b 461static unsigned int hash_expr (const_rtx, enum machine_mode, int *, int);
1d088dee 462static unsigned int hash_set (int, int);
ed7a4b4b 463static int expr_equiv_p (const_rtx, const_rtx);
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464static void record_last_reg_set_info (rtx, int);
465static void record_last_mem_set_info (rtx);
7bc980e1 466static void record_last_set_info (rtx, const_rtx, void *);
7e5487a2 467static void compute_hash_table (struct hash_table_d *);
b5b8b0ac 468static void alloc_hash_table (struct hash_table_d *, int);
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469static void free_hash_table (struct hash_table_d *);
470static void compute_hash_table_work (struct hash_table_d *);
471static void dump_hash_table (FILE *, const char *, struct hash_table_d *);
472static struct expr *lookup_set (unsigned int, struct hash_table_d *);
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473static struct expr *next_set (unsigned int, struct expr *);
474static void reset_opr_set_tables (void);
ed7a4b4b 475static int oprs_not_set_p (const_rtx, const_rtx);
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476static void mark_call (rtx);
477static void mark_set (rtx, rtx);
478static void mark_clobber (rtx, rtx);
479static void mark_oprs_set (rtx);
480static void alloc_cprop_mem (int, int);
481static void free_cprop_mem (void);
ed7a4b4b 482static void compute_transp (const_rtx, int, sbitmap *, int);
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483static void compute_transpout (void);
484static void compute_local_properties (sbitmap *, sbitmap *, sbitmap *,
7e5487a2 485 struct hash_table_d *);
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486static void compute_cprop_data (void);
487static void find_used_regs (rtx *, void *);
488static int try_replace_reg (rtx, rtx, rtx);
489static struct expr *find_avail_set (int, rtx);
490static int cprop_jump (basic_block, rtx, rtx, rtx, rtx);
7bc980e1 491static void mems_conflict_for_gcse_p (rtx, const_rtx, void *);
ed7a4b4b 492static int load_killed_in_block_p (const_basic_block, int, const_rtx, int);
7bc980e1 493static void canon_list_insert (rtx, const_rtx, void *);
5f39ad47 494static int cprop_insn (rtx);
1d088dee 495static void find_implicit_sets (void);
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496static int one_cprop_pass (void);
497static bool constprop_register (rtx, rtx, rtx);
1d088dee 498static struct expr *find_bypass_set (int, int);
ed7a4b4b 499static bool reg_killed_on_edge (const_rtx, const_edge);
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500static int bypass_block (basic_block, rtx, rtx);
501static int bypass_conditional_jumps (void);
502static void alloc_pre_mem (int, int);
503static void free_pre_mem (void);
504static void compute_pre_data (void);
505static int pre_expr_reaches_here_p (basic_block, struct expr *,
506 basic_block);
6fb5fa3c 507static void insert_insn_end_basic_block (struct expr *, basic_block, int);
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508static void pre_insert_copy_insn (struct expr *, rtx);
509static void pre_insert_copies (void);
510static int pre_delete (void);
511static int pre_gcse (void);
5f39ad47 512static int one_pre_gcse_pass (void);
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513static void add_label_notes (rtx, rtx);
514static void alloc_code_hoist_mem (int, int);
515static void free_code_hoist_mem (void);
516static void compute_code_hoist_vbeinout (void);
517static void compute_code_hoist_data (void);
518static int hoist_expr_reaches_here_p (basic_block, int, basic_block, char *);
5f39ad47 519static int hoist_code (void);
1d088dee 520static int one_code_hoisting_pass (void);
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521static rtx process_insert_insn (struct expr *);
522static int pre_edge_insert (struct edge_list *, struct expr **);
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523static int pre_expr_reaches_here_p_work (basic_block, struct expr *,
524 basic_block, char *);
525static struct ls_expr * ldst_entry (rtx);
526static void free_ldst_entry (struct ls_expr *);
527static void free_ldst_mems (void);
528static void print_ldst_list (FILE *);
529static struct ls_expr * find_rtx_in_ldst (rtx);
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530static inline struct ls_expr * first_ls_expr (void);
531static inline struct ls_expr * next_ls_expr (struct ls_expr *);
ed7a4b4b 532static int simple_mem (const_rtx);
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533static void invalidate_any_buried_refs (rtx);
534static void compute_ld_motion_mems (void);
535static void trim_ld_motion_mems (void);
536static void update_ld_motion_stores (struct expr *);
1d088dee
AJ
537static void free_insn_expr_list_list (rtx *);
538static void clear_modify_mem_tables (void);
539static void free_modify_mem_tables (void);
540static rtx gcse_emit_move_after (rtx, rtx, rtx);
541static void local_cprop_find_used_regs (rtx *, void *);
5f39ad47
SB
542static bool do_local_cprop (rtx, rtx);
543static int local_cprop_pass (void);
d128effb 544static bool is_too_expensive (const char *);
1b4572a8
KG
545
546#define GNEW(T) ((T *) gmalloc (sizeof (T)))
547#define GCNEW(T) ((T *) gcalloc (1, sizeof (T)))
548
549#define GNEWVEC(T, N) ((T *) gmalloc (sizeof (T) * (N)))
550#define GCNEWVEC(T, N) ((T *) gcalloc ((N), sizeof (T)))
1b4572a8
KG
551
552#define GNEWVAR(T, S) ((T *) gmalloc ((S)))
553#define GCNEWVAR(T, S) ((T *) gcalloc (1, (S)))
1b4572a8
KG
554
555#define GOBNEW(T) ((T *) gcse_alloc (sizeof (T)))
556#define GOBNEWVAR(T, S) ((T *) gcse_alloc ((S)))
7506f491 557\f
7506f491
DE
558/* Misc. utilities. */
559
773eae39
EB
560/* Nonzero for each mode that supports (set (reg) (reg)).
561 This is trivially true for integer and floating point values.
562 It may or may not be true for condition codes. */
563static char can_copy[(int) NUM_MACHINE_MODES];
564
7506f491
DE
565/* Compute which modes support reg/reg copy operations. */
566
567static void
1d088dee 568compute_can_copy (void)
7506f491
DE
569{
570 int i;
50b2596f 571#ifndef AVOID_CCMODE_COPIES
8e42ace1 572 rtx reg, insn;
50b2596f 573#endif
773eae39 574 memset (can_copy, 0, NUM_MACHINE_MODES);
7506f491
DE
575
576 start_sequence ();
577 for (i = 0; i < NUM_MACHINE_MODES; i++)
c4c81601
RK
578 if (GET_MODE_CLASS (i) == MODE_CC)
579 {
7506f491 580#ifdef AVOID_CCMODE_COPIES
773eae39 581 can_copy[i] = 0;
7506f491 582#else
c4c81601
RK
583 reg = gen_rtx_REG ((enum machine_mode) i, LAST_VIRTUAL_REGISTER + 1);
584 insn = emit_insn (gen_rtx_SET (VOIDmode, reg, reg));
9714cf43 585 if (recog (PATTERN (insn), insn, NULL) >= 0)
773eae39 586 can_copy[i] = 1;
7506f491 587#endif
c4c81601 588 }
141b5810 589 else
773eae39 590 can_copy[i] = 1;
c4c81601 591
7506f491 592 end_sequence ();
7506f491 593}
773eae39
EB
594
595/* Returns whether the mode supports reg/reg copy operations. */
596
597bool
1d088dee 598can_copy_p (enum machine_mode mode)
773eae39
EB
599{
600 static bool can_copy_init_p = false;
601
602 if (! can_copy_init_p)
603 {
604 compute_can_copy ();
605 can_copy_init_p = true;
606 }
607
608 return can_copy[mode] != 0;
609}
4a81774c 610
7506f491
DE
611\f
612/* Cover function to xmalloc to record bytes allocated. */
613
703ad42b 614static void *
4ac11022 615gmalloc (size_t size)
7506f491
DE
616{
617 bytes_used += size;
618 return xmalloc (size);
619}
620
9fe15a12
KG
621/* Cover function to xcalloc to record bytes allocated. */
622
623static void *
624gcalloc (size_t nelem, size_t elsize)
625{
626 bytes_used += nelem * elsize;
627 return xcalloc (nelem, elsize);
628}
629
77bbd421 630/* Cover function to obstack_alloc. */
7506f491 631
703ad42b 632static void *
1d088dee 633gcse_alloc (unsigned long size)
7506f491 634{
77bbd421 635 bytes_used += size;
703ad42b 636 return obstack_alloc (&gcse_obstack, size);
7506f491
DE
637}
638
4a81774c 639/* Allocate memory for the reg/memory set tracking tables.
7506f491
DE
640 This is called at the start of each pass. */
641
642static void
eb232f4e 643alloc_gcse_mem (void)
7506f491 644{
7506f491 645 /* Allocate vars to track sets of regs. */
8bdbfff5 646 reg_set_bitmap = BITMAP_ALLOC (NULL);
7506f491 647
a13d4ebf
AM
648 /* Allocate array to keep a list of insns which modify memory in each
649 basic block. */
1b4572a8
KG
650 modify_mem_list = GCNEWVEC (rtx, last_basic_block);
651 canon_modify_mem_list = GCNEWVEC (rtx, last_basic_block);
8bdbfff5
NS
652 modify_mem_list_set = BITMAP_ALLOC (NULL);
653 blocks_with_calls = BITMAP_ALLOC (NULL);
7506f491
DE
654}
655
656/* Free memory allocated by alloc_gcse_mem. */
657
658static void
1d088dee 659free_gcse_mem (void)
7506f491 660{
73991d6a 661 free_modify_mem_tables ();
8bdbfff5
NS
662 BITMAP_FREE (modify_mem_list_set);
663 BITMAP_FREE (blocks_with_calls);
7506f491 664}
b5ce41ff
JL
665\f
666/* Compute the local properties of each recorded expression.
c4c81601
RK
667
668 Local properties are those that are defined by the block, irrespective of
669 other blocks.
b5ce41ff
JL
670
671 An expression is transparent in a block if its operands are not modified
672 in the block.
673
674 An expression is computed (locally available) in a block if it is computed
675 at least once and expression would contain the same value if the
676 computation was moved to the end of the block.
677
678 An expression is locally anticipatable in a block if it is computed at
679 least once and expression would contain the same value if the computation
680 was moved to the beginning of the block.
681
c4c81601
RK
682 We call this routine for cprop, pre and code hoisting. They all compute
683 basically the same information and thus can easily share this code.
7506f491 684
c4c81601
RK
685 TRANSP, COMP, and ANTLOC are destination sbitmaps for recording local
686 properties. If NULL, then it is not necessary to compute or record that
687 particular property.
b5ce41ff 688
02280659
ZD
689 TABLE controls which hash table to look at. If it is set hash table,
690 additionally, TRANSP is computed as ~TRANSP, since this is really cprop's
c4c81601 691 ABSALTERED. */
589005ff 692
b5ce41ff 693static void
7b1b4aed 694compute_local_properties (sbitmap *transp, sbitmap *comp, sbitmap *antloc,
7e5487a2 695 struct hash_table_d *table)
b5ce41ff 696{
02280659 697 unsigned int i;
589005ff 698
b5ce41ff
JL
699 /* Initialize any bitmaps that were passed in. */
700 if (transp)
695ab36a 701 {
02280659 702 if (table->set_p)
d55bc081 703 sbitmap_vector_zero (transp, last_basic_block);
695ab36a 704 else
d55bc081 705 sbitmap_vector_ones (transp, last_basic_block);
695ab36a 706 }
c4c81601 707
b5ce41ff 708 if (comp)
d55bc081 709 sbitmap_vector_zero (comp, last_basic_block);
b5ce41ff 710 if (antloc)
d55bc081 711 sbitmap_vector_zero (antloc, last_basic_block);
b5ce41ff 712
02280659 713 for (i = 0; i < table->size; i++)
7506f491 714 {
b5ce41ff
JL
715 struct expr *expr;
716
02280659 717 for (expr = table->table[i]; expr != NULL; expr = expr->next_same_hash)
b5ce41ff 718 {
b5ce41ff 719 int indx = expr->bitmap_index;
c4c81601 720 struct occr *occr;
b5ce41ff
JL
721
722 /* The expression is transparent in this block if it is not killed.
723 We start by assuming all are transparent [none are killed], and
724 then reset the bits for those that are. */
b5ce41ff 725 if (transp)
02280659 726 compute_transp (expr->expr, indx, transp, table->set_p);
b5ce41ff
JL
727
728 /* The occurrences recorded in antic_occr are exactly those that
cc2902df 729 we want to set to nonzero in ANTLOC. */
b5ce41ff 730 if (antloc)
c4c81601
RK
731 for (occr = expr->antic_occr; occr != NULL; occr = occr->next)
732 {
733 SET_BIT (antloc[BLOCK_NUM (occr->insn)], indx);
b5ce41ff 734
c4c81601
RK
735 /* While we're scanning the table, this is a good place to
736 initialize this. */
737 occr->deleted_p = 0;
738 }
b5ce41ff
JL
739
740 /* The occurrences recorded in avail_occr are exactly those that
cc2902df 741 we want to set to nonzero in COMP. */
b5ce41ff 742 if (comp)
c4c81601
RK
743 for (occr = expr->avail_occr; occr != NULL; occr = occr->next)
744 {
745 SET_BIT (comp[BLOCK_NUM (occr->insn)], indx);
b5ce41ff 746
c4c81601
RK
747 /* While we're scanning the table, this is a good place to
748 initialize this. */
749 occr->copied_p = 0;
750 }
b5ce41ff
JL
751
752 /* While we're scanning the table, this is a good place to
753 initialize this. */
754 expr->reaching_reg = 0;
755 }
7506f491 756 }
7506f491
DE
757}
758\f
7506f491
DE
759/* Hash table support. */
760
80c29cc4
RZ
761struct reg_avail_info
762{
e0082a72 763 basic_block last_bb;
80c29cc4
RZ
764 int first_set;
765 int last_set;
766};
767
768static struct reg_avail_info *reg_avail_info;
e0082a72 769static basic_block current_bb;
7506f491 770
7506f491 771
fb0c0a12
RK
772/* See whether X, the source of a set, is something we want to consider for
773 GCSE. */
7506f491
DE
774
775static int
1d088dee 776want_to_gcse_p (rtx x)
7506f491 777{
3d8504ac
RS
778#ifdef STACK_REGS
779 /* On register stack architectures, don't GCSE constants from the
780 constant pool, as the benefits are often swamped by the overhead
781 of shuffling the register stack between basic blocks. */
782 if (IS_STACK_MODE (GET_MODE (x)))
783 x = avoid_constant_pool_reference (x);
784#endif
785
c4c81601 786 switch (GET_CODE (x))
7506f491
DE
787 {
788 case REG:
789 case SUBREG:
790 case CONST_INT:
791 case CONST_DOUBLE:
091a3ac7 792 case CONST_FIXED:
69ef87e2 793 case CONST_VECTOR:
7506f491
DE
794 case CALL:
795 return 0;
796
797 default:
df35c271 798 return can_assign_to_reg_without_clobbers_p (x);
7506f491 799 }
1707bafa
RS
800}
801
df35c271 802/* Used internally by can_assign_to_reg_without_clobbers_p. */
1707bafa
RS
803
804static GTY(()) rtx test_insn;
805
df35c271
SB
806/* Return true if we can assign X to a pseudo register such that the
807 resulting insn does not result in clobbering a hard register as a
808 side-effect.
ec0a1343
JB
809
810 Additionally, if the target requires it, check that the resulting insn
811 can be copied. If it cannot, this means that X is special and probably
812 has hidden side-effects we don't want to mess with.
813
df35c271
SB
814 This function is typically used by code motion passes, to verify
815 that it is safe to insert an insn without worrying about clobbering
816 maybe live hard regs. */
1707bafa 817
df35c271
SB
818bool
819can_assign_to_reg_without_clobbers_p (rtx x)
1707bafa
RS
820{
821 int num_clobbers = 0;
822 int icode;
7506f491 823
fb0c0a12
RK
824 /* If this is a valid operand, we are OK. If it's VOIDmode, we aren't. */
825 if (general_operand (x, GET_MODE (x)))
826 return 1;
827 else if (GET_MODE (x) == VOIDmode)
828 return 0;
829
830 /* Otherwise, check if we can make a valid insn from it. First initialize
831 our test insn if we haven't already. */
832 if (test_insn == 0)
833 {
834 test_insn
835 = make_insn_raw (gen_rtx_SET (VOIDmode,
836 gen_rtx_REG (word_mode,
837 FIRST_PSEUDO_REGISTER * 2),
838 const0_rtx));
839 NEXT_INSN (test_insn) = PREV_INSN (test_insn) = 0;
fb0c0a12
RK
840 }
841
842 /* Now make an insn like the one we would make when GCSE'ing and see if
843 valid. */
844 PUT_MODE (SET_DEST (PATTERN (test_insn)), GET_MODE (x));
845 SET_SRC (PATTERN (test_insn)) = x;
b8698a0f 846
ec0a1343
JB
847 icode = recog (PATTERN (test_insn), test_insn, &num_clobbers);
848 if (icode < 0)
849 return false;
b8698a0f 850
ec0a1343
JB
851 if (num_clobbers > 0 && added_clobbers_hard_reg_p (icode))
852 return false;
b8698a0f 853
ec0a1343
JB
854 if (targetm.cannot_copy_insn_p && targetm.cannot_copy_insn_p (test_insn))
855 return false;
b8698a0f 856
ec0a1343 857 return true;
7506f491
DE
858}
859
cc2902df 860/* Return nonzero if the operands of expression X are unchanged from the
7506f491
DE
861 start of INSN's basic block up to but not including INSN (if AVAIL_P == 0),
862 or from INSN to the end of INSN's basic block (if AVAIL_P != 0). */
863
864static int
ed7a4b4b 865oprs_unchanged_p (const_rtx x, const_rtx insn, int avail_p)
7506f491 866{
c4c81601 867 int i, j;
7506f491 868 enum rtx_code code;
6f7d635c 869 const char *fmt;
7506f491 870
7506f491
DE
871 if (x == 0)
872 return 1;
873
874 code = GET_CODE (x);
875 switch (code)
876 {
877 case REG:
80c29cc4
RZ
878 {
879 struct reg_avail_info *info = &reg_avail_info[REGNO (x)];
880
881 if (info->last_bb != current_bb)
882 return 1;
589005ff 883 if (avail_p)
4a81774c 884 return info->last_set < DF_INSN_LUID (insn);
80c29cc4 885 else
4a81774c 886 return info->first_set >= DF_INSN_LUID (insn);
80c29cc4 887 }
7506f491
DE
888
889 case MEM:
4a81774c 890 if (load_killed_in_block_p (current_bb, DF_INSN_LUID (insn),
a13d4ebf
AM
891 x, avail_p))
892 return 0;
7506f491 893 else
c4c81601 894 return oprs_unchanged_p (XEXP (x, 0), insn, avail_p);
7506f491
DE
895
896 case PRE_DEC:
897 case PRE_INC:
898 case POST_DEC:
899 case POST_INC:
4b983fdc
RH
900 case PRE_MODIFY:
901 case POST_MODIFY:
7506f491
DE
902 return 0;
903
904 case PC:
905 case CC0: /*FIXME*/
906 case CONST:
907 case CONST_INT:
908 case CONST_DOUBLE:
091a3ac7 909 case CONST_FIXED:
69ef87e2 910 case CONST_VECTOR:
7506f491
DE
911 case SYMBOL_REF:
912 case LABEL_REF:
913 case ADDR_VEC:
914 case ADDR_DIFF_VEC:
915 return 1;
916
917 default:
918 break;
919 }
920
c4c81601 921 for (i = GET_RTX_LENGTH (code) - 1, fmt = GET_RTX_FORMAT (code); i >= 0; i--)
7506f491
DE
922 {
923 if (fmt[i] == 'e')
924 {
c4c81601
RK
925 /* If we are about to do the last recursive call needed at this
926 level, change it into iteration. This function is called enough
927 to be worth it. */
7506f491 928 if (i == 0)
c4c81601
RK
929 return oprs_unchanged_p (XEXP (x, i), insn, avail_p);
930
931 else if (! oprs_unchanged_p (XEXP (x, i), insn, avail_p))
7506f491
DE
932 return 0;
933 }
934 else if (fmt[i] == 'E')
c4c81601
RK
935 for (j = 0; j < XVECLEN (x, i); j++)
936 if (! oprs_unchanged_p (XVECEXP (x, i, j), insn, avail_p))
937 return 0;
7506f491
DE
938 }
939
940 return 1;
941}
942
a13d4ebf
AM
943/* Used for communication between mems_conflict_for_gcse_p and
944 load_killed_in_block_p. Nonzero if mems_conflict_for_gcse_p finds a
945 conflict between two memory references. */
946static int gcse_mems_conflict_p;
947
948/* Used for communication between mems_conflict_for_gcse_p and
949 load_killed_in_block_p. A memory reference for a load instruction,
950 mems_conflict_for_gcse_p will see if a memory store conflicts with
951 this memory load. */
ed7a4b4b 952static const_rtx gcse_mem_operand;
a13d4ebf
AM
953
954/* DEST is the output of an instruction. If it is a memory reference, and
955 possibly conflicts with the load found in gcse_mem_operand, then set
956 gcse_mems_conflict_p to a nonzero value. */
957
958static void
7bc980e1 959mems_conflict_for_gcse_p (rtx dest, const_rtx setter ATTRIBUTE_UNUSED,
1d088dee 960 void *data ATTRIBUTE_UNUSED)
a13d4ebf
AM
961{
962 while (GET_CODE (dest) == SUBREG
963 || GET_CODE (dest) == ZERO_EXTRACT
a13d4ebf
AM
964 || GET_CODE (dest) == STRICT_LOW_PART)
965 dest = XEXP (dest, 0);
966
967 /* If DEST is not a MEM, then it will not conflict with the load. Note
968 that function calls are assumed to clobber memory, but are handled
969 elsewhere. */
7b1b4aed 970 if (! MEM_P (dest))
a13d4ebf 971 return;
aaa4ca30 972
a13d4ebf 973 /* If we are setting a MEM in our list of specially recognized MEMs,
589005ff
KH
974 don't mark as killed this time. */
975
47a3dae1 976 if (expr_equiv_p (dest, gcse_mem_operand) && pre_ldst_mems != NULL)
a13d4ebf
AM
977 {
978 if (!find_rtx_in_ldst (dest))
979 gcse_mems_conflict_p = 1;
980 return;
981 }
aaa4ca30 982
a13d4ebf
AM
983 if (true_dependence (dest, GET_MODE (dest), gcse_mem_operand,
984 rtx_addr_varies_p))
985 gcse_mems_conflict_p = 1;
986}
987
988/* Return nonzero if the expression in X (a memory reference) is killed
4a81774c 989 in block BB before or after the insn with the LUID in UID_LIMIT.
a13d4ebf
AM
990 AVAIL_P is nonzero for kills after UID_LIMIT, and zero for kills
991 before UID_LIMIT.
992
993 To check the entire block, set UID_LIMIT to max_uid + 1 and
994 AVAIL_P to 0. */
995
996static int
ed7a4b4b 997load_killed_in_block_p (const_basic_block bb, int uid_limit, const_rtx x, int avail_p)
a13d4ebf 998{
0b17ab2f 999 rtx list_entry = modify_mem_list[bb->index];
16c5b95d
MH
1000
1001 /* If this is a readonly then we aren't going to be changing it. */
1002 if (MEM_READONLY_P (x))
1003 return 0;
1004
a13d4ebf
AM
1005 while (list_entry)
1006 {
1007 rtx setter;
1008 /* Ignore entries in the list that do not apply. */
1009 if ((avail_p
4a81774c 1010 && DF_INSN_LUID (XEXP (list_entry, 0)) < uid_limit)
a13d4ebf 1011 || (! avail_p
4a81774c 1012 && DF_INSN_LUID (XEXP (list_entry, 0)) > uid_limit))
a13d4ebf
AM
1013 {
1014 list_entry = XEXP (list_entry, 1);
1015 continue;
1016 }
1017
1018 setter = XEXP (list_entry, 0);
1019
1020 /* If SETTER is a call everything is clobbered. Note that calls
1021 to pure functions are never put on the list, so we need not
1022 worry about them. */
7b1b4aed 1023 if (CALL_P (setter))
a13d4ebf
AM
1024 return 1;
1025
1026 /* SETTER must be an INSN of some kind that sets memory. Call
589005ff 1027 note_stores to examine each hunk of memory that is modified.
a13d4ebf
AM
1028
1029 The note_stores interface is pretty limited, so we have to
1030 communicate via global variables. Yuk. */
1031 gcse_mem_operand = x;
1032 gcse_mems_conflict_p = 0;
1033 note_stores (PATTERN (setter), mems_conflict_for_gcse_p, NULL);
1034 if (gcse_mems_conflict_p)
1035 return 1;
1036 list_entry = XEXP (list_entry, 1);
1037 }
1038 return 0;
1039}
1040
cc2902df 1041/* Return nonzero if the operands of expression X are unchanged from
7506f491
DE
1042 the start of INSN's basic block up to but not including INSN. */
1043
1044static int
ed7a4b4b 1045oprs_anticipatable_p (const_rtx x, const_rtx insn)
7506f491
DE
1046{
1047 return oprs_unchanged_p (x, insn, 0);
1048}
1049
cc2902df 1050/* Return nonzero if the operands of expression X are unchanged from
7506f491
DE
1051 INSN to the end of INSN's basic block. */
1052
1053static int
ed7a4b4b 1054oprs_available_p (const_rtx x, const_rtx insn)
7506f491
DE
1055{
1056 return oprs_unchanged_p (x, insn, 1);
1057}
1058
1059/* Hash expression X.
c4c81601
RK
1060
1061 MODE is only used if X is a CONST_INT. DO_NOT_RECORD_P is a boolean
1062 indicating if a volatile operand is found or if the expression contains
b58b21d5 1063 something we don't want to insert in the table. HASH_TABLE_SIZE is
0516f6fe 1064 the current size of the hash table to be probed. */
7506f491
DE
1065
1066static unsigned int
ed7a4b4b 1067hash_expr (const_rtx x, enum machine_mode mode, int *do_not_record_p,
b58b21d5 1068 int hash_table_size)
7506f491
DE
1069{
1070 unsigned int hash;
1071
1072 *do_not_record_p = 0;
1073
0516f6fe
SB
1074 hash = hash_rtx (x, mode, do_not_record_p,
1075 NULL, /*have_reg_qty=*/false);
7506f491
DE
1076 return hash % hash_table_size;
1077}
172890a2 1078
7506f491
DE
1079/* Hash a set of register REGNO.
1080
c4c81601
RK
1081 Sets are hashed on the register that is set. This simplifies the PRE copy
1082 propagation code.
7506f491
DE
1083
1084 ??? May need to make things more elaborate. Later, as necessary. */
1085
1086static unsigned int
1d088dee 1087hash_set (int regno, int hash_table_size)
7506f491
DE
1088{
1089 unsigned int hash;
1090
1091 hash = regno;
1092 return hash % hash_table_size;
1093}
1094
0516f6fe 1095/* Return nonzero if exp1 is equivalent to exp2. */
7506f491
DE
1096
1097static int
ed7a4b4b 1098expr_equiv_p (const_rtx x, const_rtx y)
7506f491 1099{
0516f6fe 1100 return exp_equiv_p (x, y, 0, true);
7506f491
DE
1101}
1102
02280659 1103/* Insert expression X in INSN in the hash TABLE.
7506f491
DE
1104 If it is already present, record it as the last occurrence in INSN's
1105 basic block.
1106
1107 MODE is the mode of the value X is being stored into.
1108 It is only used if X is a CONST_INT.
1109
cc2902df
KH
1110 ANTIC_P is nonzero if X is an anticipatable expression.
1111 AVAIL_P is nonzero if X is an available expression. */
7506f491
DE
1112
1113static void
1d088dee 1114insert_expr_in_table (rtx x, enum machine_mode mode, rtx insn, int antic_p,
7e5487a2 1115 int avail_p, struct hash_table_d *table)
7506f491
DE
1116{
1117 int found, do_not_record_p;
1118 unsigned int hash;
1119 struct expr *cur_expr, *last_expr = NULL;
1120 struct occr *antic_occr, *avail_occr;
7506f491 1121
02280659 1122 hash = hash_expr (x, mode, &do_not_record_p, table->size);
7506f491
DE
1123
1124 /* Do not insert expression in table if it contains volatile operands,
1125 or if hash_expr determines the expression is something we don't want
1126 to or can't handle. */
1127 if (do_not_record_p)
1128 return;
1129
02280659 1130 cur_expr = table->table[hash];
7506f491
DE
1131 found = 0;
1132
c4c81601 1133 while (cur_expr && 0 == (found = expr_equiv_p (cur_expr->expr, x)))
7506f491
DE
1134 {
1135 /* If the expression isn't found, save a pointer to the end of
1136 the list. */
1137 last_expr = cur_expr;
1138 cur_expr = cur_expr->next_same_hash;
1139 }
1140
1141 if (! found)
1142 {
1b4572a8 1143 cur_expr = GOBNEW (struct expr);
7506f491 1144 bytes_used += sizeof (struct expr);
02280659 1145 if (table->table[hash] == NULL)
c4c81601 1146 /* This is the first pattern that hashed to this index. */
02280659 1147 table->table[hash] = cur_expr;
7506f491 1148 else
c4c81601
RK
1149 /* Add EXPR to end of this hash chain. */
1150 last_expr->next_same_hash = cur_expr;
1151
589005ff 1152 /* Set the fields of the expr element. */
7506f491 1153 cur_expr->expr = x;
02280659 1154 cur_expr->bitmap_index = table->n_elems++;
7506f491
DE
1155 cur_expr->next_same_hash = NULL;
1156 cur_expr->antic_occr = NULL;
1157 cur_expr->avail_occr = NULL;
1158 }
1159
1160 /* Now record the occurrence(s). */
7506f491
DE
1161 if (antic_p)
1162 {
1163 antic_occr = cur_expr->antic_occr;
1164
b6e47ceb
JL
1165 if (antic_occr && BLOCK_NUM (antic_occr->insn) != BLOCK_NUM (insn))
1166 antic_occr = NULL;
7506f491
DE
1167
1168 if (antic_occr)
c4c81601
RK
1169 /* Found another instance of the expression in the same basic block.
1170 Prefer the currently recorded one. We want the first one in the
1171 block and the block is scanned from start to end. */
1172 ; /* nothing to do */
7506f491
DE
1173 else
1174 {
1175 /* First occurrence of this expression in this basic block. */
1b4572a8 1176 antic_occr = GOBNEW (struct occr);
7506f491 1177 bytes_used += sizeof (struct occr);
7506f491 1178 antic_occr->insn = insn;
b6e47ceb 1179 antic_occr->next = cur_expr->antic_occr;
f9957958 1180 antic_occr->deleted_p = 0;
b6e47ceb 1181 cur_expr->antic_occr = antic_occr;
7506f491
DE
1182 }
1183 }
1184
1185 if (avail_p)
1186 {
1187 avail_occr = cur_expr->avail_occr;
1188
b6e47ceb 1189 if (avail_occr && BLOCK_NUM (avail_occr->insn) == BLOCK_NUM (insn))
7506f491 1190 {
b6e47ceb
JL
1191 /* Found another instance of the expression in the same basic block.
1192 Prefer this occurrence to the currently recorded one. We want
1193 the last one in the block and the block is scanned from start
1194 to end. */
1195 avail_occr->insn = insn;
7506f491 1196 }
7506f491
DE
1197 else
1198 {
1199 /* First occurrence of this expression in this basic block. */
1b4572a8 1200 avail_occr = GOBNEW (struct occr);
7506f491 1201 bytes_used += sizeof (struct occr);
7506f491 1202 avail_occr->insn = insn;
b6e47ceb 1203 avail_occr->next = cur_expr->avail_occr;
f9957958 1204 avail_occr->deleted_p = 0;
b6e47ceb 1205 cur_expr->avail_occr = avail_occr;
7506f491
DE
1206 }
1207 }
1208}
1209
1210/* Insert pattern X in INSN in the hash table.
1211 X is a SET of a reg to either another reg or a constant.
1212 If it is already present, record it as the last occurrence in INSN's
1213 basic block. */
1214
1215static void
7e5487a2 1216insert_set_in_table (rtx x, rtx insn, struct hash_table_d *table)
7506f491
DE
1217{
1218 int found;
1219 unsigned int hash;
1220 struct expr *cur_expr, *last_expr = NULL;
b6e47ceb 1221 struct occr *cur_occr;
7506f491 1222
282899df 1223 gcc_assert (GET_CODE (x) == SET && REG_P (SET_DEST (x)));
7506f491 1224
02280659 1225 hash = hash_set (REGNO (SET_DEST (x)), table->size);
7506f491 1226
02280659 1227 cur_expr = table->table[hash];
7506f491
DE
1228 found = 0;
1229
c4c81601 1230 while (cur_expr && 0 == (found = expr_equiv_p (cur_expr->expr, x)))
7506f491
DE
1231 {
1232 /* If the expression isn't found, save a pointer to the end of
1233 the list. */
1234 last_expr = cur_expr;
1235 cur_expr = cur_expr->next_same_hash;
1236 }
1237
1238 if (! found)
1239 {
1b4572a8 1240 cur_expr = GOBNEW (struct expr);
7506f491 1241 bytes_used += sizeof (struct expr);
02280659 1242 if (table->table[hash] == NULL)
c4c81601 1243 /* This is the first pattern that hashed to this index. */
02280659 1244 table->table[hash] = cur_expr;
7506f491 1245 else
c4c81601
RK
1246 /* Add EXPR to end of this hash chain. */
1247 last_expr->next_same_hash = cur_expr;
1248
7506f491
DE
1249 /* Set the fields of the expr element.
1250 We must copy X because it can be modified when copy propagation is
1251 performed on its operands. */
7506f491 1252 cur_expr->expr = copy_rtx (x);
02280659 1253 cur_expr->bitmap_index = table->n_elems++;
7506f491
DE
1254 cur_expr->next_same_hash = NULL;
1255 cur_expr->antic_occr = NULL;
1256 cur_expr->avail_occr = NULL;
1257 }
1258
1259 /* Now record the occurrence. */
7506f491
DE
1260 cur_occr = cur_expr->avail_occr;
1261
b6e47ceb 1262 if (cur_occr && BLOCK_NUM (cur_occr->insn) == BLOCK_NUM (insn))
7506f491 1263 {
b6e47ceb
JL
1264 /* Found another instance of the expression in the same basic block.
1265 Prefer this occurrence to the currently recorded one. We want
1266 the last one in the block and the block is scanned from start
1267 to end. */
1268 cur_occr->insn = insn;
7506f491 1269 }
7506f491
DE
1270 else
1271 {
1272 /* First occurrence of this expression in this basic block. */
1b4572a8 1273 cur_occr = GOBNEW (struct occr);
7506f491 1274 bytes_used += sizeof (struct occr);
5f39ad47
SB
1275 cur_occr->insn = insn;
1276 cur_occr->next = cur_expr->avail_occr;
1277 cur_occr->deleted_p = 0;
1278 cur_expr->avail_occr = cur_occr;
7506f491
DE
1279 }
1280}
1281
6b2d1c9e
RS
1282/* Determine whether the rtx X should be treated as a constant for
1283 the purposes of GCSE's constant propagation. */
1284
1285static bool
ed7a4b4b 1286gcse_constant_p (const_rtx x)
6b2d1c9e
RS
1287{
1288 /* Consider a COMPARE of two integers constant. */
1289 if (GET_CODE (x) == COMPARE
481683e1
SZ
1290 && CONST_INT_P (XEXP (x, 0))
1291 && CONST_INT_P (XEXP (x, 1)))
6b2d1c9e
RS
1292 return true;
1293
db2f435b 1294 /* Consider a COMPARE of the same registers is a constant
7b1b4aed 1295 if they are not floating point registers. */
db2f435b 1296 if (GET_CODE(x) == COMPARE
7b1b4aed 1297 && REG_P (XEXP (x, 0)) && REG_P (XEXP (x, 1))
db2f435b
AP
1298 && REGNO (XEXP (x, 0)) == REGNO (XEXP (x, 1))
1299 && ! FLOAT_MODE_P (GET_MODE (XEXP (x, 0)))
1300 && ! FLOAT_MODE_P (GET_MODE (XEXP (x, 1))))
1301 return true;
1302
82f5c05d
AK
1303 /* Since X might be inserted more than once we have to take care that it
1304 is sharable. */
fa5ed76e 1305 return CONSTANT_P (x) && (GET_CODE (x) != CONST || shared_const_p (x));
6b2d1c9e
RS
1306}
1307
02280659
ZD
1308/* Scan pattern PAT of INSN and add an entry to the hash TABLE (set or
1309 expression one). */
7506f491
DE
1310
1311static void
7e5487a2 1312hash_scan_set (rtx pat, rtx insn, struct hash_table_d *table)
7506f491
DE
1313{
1314 rtx src = SET_SRC (pat);
1315 rtx dest = SET_DEST (pat);
172890a2 1316 rtx note;
7506f491 1317
6e72d1e9 1318 if (GET_CODE (src) == CALL)
02280659 1319 hash_scan_call (src, insn, table);
7506f491 1320
7b1b4aed 1321 else if (REG_P (dest))
7506f491 1322 {
172890a2 1323 unsigned int regno = REGNO (dest);
7506f491
DE
1324 rtx tmp;
1325
29470771
SB
1326 /* See if a REG_EQUAL note shows this equivalent to a simpler expression.
1327
90631280
PB
1328 This allows us to do a single GCSE pass and still eliminate
1329 redundant constants, addresses or other expressions that are
29470771
SB
1330 constructed with multiple instructions.
1331
1332 However, keep the original SRC if INSN is a simple reg-reg move. In
1333 In this case, there will almost always be a REG_EQUAL note on the
1334 insn that sets SRC. By recording the REG_EQUAL value here as SRC
1335 for INSN, we miss copy propagation opportunities and we perform the
1336 same PRE GCSE operation repeatedly on the same REG_EQUAL value if we
1337 do more than one PRE GCSE pass.
1338
fa10beec 1339 Note that this does not impede profitable constant propagations. We
29470771 1340 "look through" reg-reg sets in lookup_avail_set. */
90631280
PB
1341 note = find_reg_equal_equiv_note (insn);
1342 if (note != 0
29470771
SB
1343 && REG_NOTE_KIND (note) == REG_EQUAL
1344 && !REG_P (src)
90631280
PB
1345 && (table->set_p
1346 ? gcse_constant_p (XEXP (note, 0))
1347 : want_to_gcse_p (XEXP (note, 0))))
172890a2
RK
1348 src = XEXP (note, 0), pat = gen_rtx_SET (VOIDmode, dest, src);
1349
7506f491 1350 /* Only record sets of pseudo-regs in the hash table. */
02280659 1351 if (! table->set_p
7506f491
DE
1352 && regno >= FIRST_PSEUDO_REGISTER
1353 /* Don't GCSE something if we can't do a reg/reg copy. */
773eae39 1354 && can_copy_p (GET_MODE (dest))
068473ec 1355 /* GCSE commonly inserts instruction after the insn. We can't
1d65f45c
RH
1356 do that easily for EH edges so disable GCSE on these for now. */
1357 /* ??? We can now easily create new EH landing pads at the
1358 gimple level, for splitting edges; there's no reason we
1359 can't do the same thing at the rtl level. */
1360 && !can_throw_internal (insn)
7506f491 1361 /* Is SET_SRC something we want to gcse? */
172890a2
RK
1362 && want_to_gcse_p (src)
1363 /* Don't CSE a nop. */
43e72072
JJ
1364 && ! set_noop_p (pat)
1365 /* Don't GCSE if it has attached REG_EQUIV note.
1366 At this point this only function parameters should have
1367 REG_EQUIV notes and if the argument slot is used somewhere
a1f300c0 1368 explicitly, it means address of parameter has been taken,
43e72072 1369 so we should not extend the lifetime of the pseudo. */
90631280 1370 && (note == NULL_RTX || ! MEM_P (XEXP (note, 0))))
7506f491
DE
1371 {
1372 /* An expression is not anticipatable if its operands are
52d76e11 1373 modified before this insn or if this is not the only SET in
6fb5fa3c
DB
1374 this insn. The latter condition does not have to mean that
1375 SRC itself is not anticipatable, but we just will not be
1376 able to handle code motion of insns with multiple sets. */
1377 int antic_p = oprs_anticipatable_p (src, insn)
1378 && !multiple_sets (insn);
7506f491 1379 /* An expression is not available if its operands are
eb296bd9
GK
1380 subsequently modified, including this insn. It's also not
1381 available if this is a branch, because we can't insert
1382 a set after the branch. */
1383 int avail_p = (oprs_available_p (src, insn)
1384 && ! JUMP_P (insn));
c4c81601 1385
02280659 1386 insert_expr_in_table (src, GET_MODE (dest), insn, antic_p, avail_p, table);
7506f491 1387 }
c4c81601 1388
7506f491 1389 /* Record sets for constant/copy propagation. */
02280659 1390 else if (table->set_p
7506f491 1391 && regno >= FIRST_PSEUDO_REGISTER
7b1b4aed 1392 && ((REG_P (src)
7506f491 1393 && REGNO (src) >= FIRST_PSEUDO_REGISTER
773eae39 1394 && can_copy_p (GET_MODE (dest))
172890a2 1395 && REGNO (src) != regno)
6b2d1c9e 1396 || gcse_constant_p (src))
7506f491
DE
1397 /* A copy is not available if its src or dest is subsequently
1398 modified. Here we want to search from INSN+1 on, but
1399 oprs_available_p searches from INSN on. */
a813c111 1400 && (insn == BB_END (BLOCK_FOR_INSN (insn))
02a4823b 1401 || (tmp = next_nonnote_insn (insn)) == NULL_RTX
1ef40d6b 1402 || BLOCK_FOR_INSN (tmp) != BLOCK_FOR_INSN (insn)
02a4823b 1403 || oprs_available_p (pat, tmp)))
02280659 1404 insert_set_in_table (pat, insn, table);
7506f491 1405 }
d91edf86 1406 /* In case of store we want to consider the memory value as available in
f5f2e3cd
MH
1407 the REG stored in that memory. This makes it possible to remove
1408 redundant loads from due to stores to the same location. */
7b1b4aed 1409 else if (flag_gcse_las && REG_P (src) && MEM_P (dest))
f5f2e3cd
MH
1410 {
1411 unsigned int regno = REGNO (src);
1412
1413 /* Do not do this for constant/copy propagation. */
1414 if (! table->set_p
1415 /* Only record sets of pseudo-regs in the hash table. */
1416 && regno >= FIRST_PSEUDO_REGISTER
1417 /* Don't GCSE something if we can't do a reg/reg copy. */
1418 && can_copy_p (GET_MODE (src))
1419 /* GCSE commonly inserts instruction after the insn. We can't
1d65f45c
RH
1420 do that easily for EH edges so disable GCSE on these for now. */
1421 && !can_throw_internal (insn)
f5f2e3cd
MH
1422 /* Is SET_DEST something we want to gcse? */
1423 && want_to_gcse_p (dest)
1424 /* Don't CSE a nop. */
1425 && ! set_noop_p (pat)
1426 /* Don't GCSE if it has attached REG_EQUIV note.
1427 At this point this only function parameters should have
1428 REG_EQUIV notes and if the argument slot is used somewhere
1429 explicitly, it means address of parameter has been taken,
1430 so we should not extend the lifetime of the pseudo. */
1431 && ((note = find_reg_note (insn, REG_EQUIV, NULL_RTX)) == 0
7b1b4aed 1432 || ! MEM_P (XEXP (note, 0))))
f5f2e3cd
MH
1433 {
1434 /* Stores are never anticipatable. */
1435 int antic_p = 0;
1436 /* An expression is not available if its operands are
1437 subsequently modified, including this insn. It's also not
1438 available if this is a branch, because we can't insert
1439 a set after the branch. */
1440 int avail_p = oprs_available_p (dest, insn)
1441 && ! JUMP_P (insn);
1442
1443 /* Record the memory expression (DEST) in the hash table. */
1444 insert_expr_in_table (dest, GET_MODE (dest), insn,
1445 antic_p, avail_p, table);
1446 }
1447 }
7506f491
DE
1448}
1449
1450static void
1d088dee 1451hash_scan_clobber (rtx x ATTRIBUTE_UNUSED, rtx insn ATTRIBUTE_UNUSED,
7e5487a2 1452 struct hash_table_d *table ATTRIBUTE_UNUSED)
7506f491
DE
1453{
1454 /* Currently nothing to do. */
1455}
1456
1457static void
1d088dee 1458hash_scan_call (rtx x ATTRIBUTE_UNUSED, rtx insn ATTRIBUTE_UNUSED,
7e5487a2 1459 struct hash_table_d *table ATTRIBUTE_UNUSED)
7506f491
DE
1460{
1461 /* Currently nothing to do. */
1462}
1463
1464/* Process INSN and add hash table entries as appropriate.
1465
1466 Only available expressions that set a single pseudo-reg are recorded.
1467
1468 Single sets in a PARALLEL could be handled, but it's an extra complication
1469 that isn't dealt with right now. The trick is handling the CLOBBERs that
1470 are also in the PARALLEL. Later.
1471
cc2902df 1472 If SET_P is nonzero, this is for the assignment hash table,
4a8cae83 1473 otherwise it is for the expression hash table. */
7506f491
DE
1474
1475static void
7e5487a2 1476hash_scan_insn (rtx insn, struct hash_table_d *table)
7506f491
DE
1477{
1478 rtx pat = PATTERN (insn);
c4c81601 1479 int i;
7506f491
DE
1480
1481 /* Pick out the sets of INSN and for other forms of instructions record
1482 what's been modified. */
1483
172890a2 1484 if (GET_CODE (pat) == SET)
02280659 1485 hash_scan_set (pat, insn, table);
7506f491 1486 else if (GET_CODE (pat) == PARALLEL)
c4c81601
RK
1487 for (i = 0; i < XVECLEN (pat, 0); i++)
1488 {
1489 rtx x = XVECEXP (pat, 0, i);
7506f491 1490
c4c81601 1491 if (GET_CODE (x) == SET)
02280659 1492 hash_scan_set (x, insn, table);
c4c81601 1493 else if (GET_CODE (x) == CLOBBER)
02280659 1494 hash_scan_clobber (x, insn, table);
6e72d1e9 1495 else if (GET_CODE (x) == CALL)
02280659 1496 hash_scan_call (x, insn, table);
c4c81601 1497 }
7506f491 1498
7506f491 1499 else if (GET_CODE (pat) == CLOBBER)
02280659 1500 hash_scan_clobber (pat, insn, table);
6e72d1e9 1501 else if (GET_CODE (pat) == CALL)
02280659 1502 hash_scan_call (pat, insn, table);
7506f491
DE
1503}
1504
1505static void
7e5487a2 1506dump_hash_table (FILE *file, const char *name, struct hash_table_d *table)
7506f491
DE
1507{
1508 int i;
1509 /* Flattened out table, so it's printed in proper order. */
4da896b2
MM
1510 struct expr **flat_table;
1511 unsigned int *hash_val;
c4c81601 1512 struct expr *expr;
4da896b2 1513
1b4572a8
KG
1514 flat_table = XCNEWVEC (struct expr *, table->n_elems);
1515 hash_val = XNEWVEC (unsigned int, table->n_elems);
7506f491 1516
02280659
ZD
1517 for (i = 0; i < (int) table->size; i++)
1518 for (expr = table->table[i]; expr != NULL; expr = expr->next_same_hash)
c4c81601
RK
1519 {
1520 flat_table[expr->bitmap_index] = expr;
1521 hash_val[expr->bitmap_index] = i;
1522 }
7506f491
DE
1523
1524 fprintf (file, "%s hash table (%d buckets, %d entries)\n",
02280659 1525 name, table->size, table->n_elems);
7506f491 1526
02280659 1527 for (i = 0; i < (int) table->n_elems; i++)
21318741
RK
1528 if (flat_table[i] != 0)
1529 {
a0ac9e5a 1530 expr = flat_table[i];
21318741
RK
1531 fprintf (file, "Index %d (hash value %d)\n ",
1532 expr->bitmap_index, hash_val[i]);
a0ac9e5a 1533 print_rtl (file, expr->expr);
21318741
RK
1534 fprintf (file, "\n");
1535 }
7506f491
DE
1536
1537 fprintf (file, "\n");
4da896b2 1538
4da896b2
MM
1539 free (flat_table);
1540 free (hash_val);
7506f491
DE
1541}
1542
1543/* Record register first/last/block set information for REGNO in INSN.
c4c81601 1544
80c29cc4 1545 first_set records the first place in the block where the register
7506f491 1546 is set and is used to compute "anticipatability".
c4c81601 1547
80c29cc4 1548 last_set records the last place in the block where the register
7506f491 1549 is set and is used to compute "availability".
c4c81601 1550
80c29cc4 1551 last_bb records the block for which first_set and last_set are
4a81774c 1552 valid, as a quick test to invalidate them. */
7506f491
DE
1553
1554static void
1d088dee 1555record_last_reg_set_info (rtx insn, int regno)
7506f491 1556{
80c29cc4 1557 struct reg_avail_info *info = &reg_avail_info[regno];
4a81774c 1558 int luid = DF_INSN_LUID (insn);
c4c81601 1559
4a81774c 1560 info->last_set = luid;
80c29cc4
RZ
1561 if (info->last_bb != current_bb)
1562 {
1563 info->last_bb = current_bb;
4a81774c 1564 info->first_set = luid;
80c29cc4 1565 }
7506f491
DE
1566}
1567
a13d4ebf
AM
1568
1569/* Record all of the canonicalized MEMs of record_last_mem_set_info's insn.
1570 Note we store a pair of elements in the list, so they have to be
1571 taken off pairwise. */
1572
589005ff 1573static void
7bc980e1 1574canon_list_insert (rtx dest ATTRIBUTE_UNUSED, const_rtx unused1 ATTRIBUTE_UNUSED,
1d088dee 1575 void * v_insn)
a13d4ebf
AM
1576{
1577 rtx dest_addr, insn;
0fe854a7 1578 int bb;
a13d4ebf
AM
1579
1580 while (GET_CODE (dest) == SUBREG
1581 || GET_CODE (dest) == ZERO_EXTRACT
a13d4ebf
AM
1582 || GET_CODE (dest) == STRICT_LOW_PART)
1583 dest = XEXP (dest, 0);
1584
1585 /* If DEST is not a MEM, then it will not conflict with a load. Note
1586 that function calls are assumed to clobber memory, but are handled
1587 elsewhere. */
1588
7b1b4aed 1589 if (! MEM_P (dest))
a13d4ebf
AM
1590 return;
1591
1592 dest_addr = get_addr (XEXP (dest, 0));
1593 dest_addr = canon_rtx (dest_addr);
589005ff 1594 insn = (rtx) v_insn;
0fe854a7 1595 bb = BLOCK_NUM (insn);
a13d4ebf 1596
589005ff 1597 canon_modify_mem_list[bb] =
0fe854a7 1598 alloc_EXPR_LIST (VOIDmode, dest_addr, canon_modify_mem_list[bb]);
589005ff 1599 canon_modify_mem_list[bb] =
0fe854a7 1600 alloc_EXPR_LIST (VOIDmode, dest, canon_modify_mem_list[bb]);
a13d4ebf
AM
1601}
1602
a13d4ebf
AM
1603/* Record memory modification information for INSN. We do not actually care
1604 about the memory location(s) that are set, or even how they are set (consider
1605 a CALL_INSN). We merely need to record which insns modify memory. */
7506f491
DE
1606
1607static void
1d088dee 1608record_last_mem_set_info (rtx insn)
7506f491 1609{
0fe854a7
RH
1610 int bb = BLOCK_NUM (insn);
1611
ccef9ef5 1612 /* load_killed_in_block_p will handle the case of calls clobbering
dc297297 1613 everything. */
0fe854a7
RH
1614 modify_mem_list[bb] = alloc_INSN_LIST (insn, modify_mem_list[bb]);
1615 bitmap_set_bit (modify_mem_list_set, bb);
a13d4ebf 1616
7b1b4aed 1617 if (CALL_P (insn))
a13d4ebf
AM
1618 {
1619 /* Note that traversals of this loop (other than for free-ing)
1620 will break after encountering a CALL_INSN. So, there's no
dc297297 1621 need to insert a pair of items, as canon_list_insert does. */
589005ff
KH
1622 canon_modify_mem_list[bb] =
1623 alloc_INSN_LIST (insn, canon_modify_mem_list[bb]);
aa47fcfa 1624 bitmap_set_bit (blocks_with_calls, bb);
a13d4ebf
AM
1625 }
1626 else
0fe854a7 1627 note_stores (PATTERN (insn), canon_list_insert, (void*) insn);
7506f491
DE
1628}
1629
7506f491 1630/* Called from compute_hash_table via note_stores to handle one
84832317
MM
1631 SET or CLOBBER in an insn. DATA is really the instruction in which
1632 the SET is taking place. */
7506f491
DE
1633
1634static void
7bc980e1 1635record_last_set_info (rtx dest, const_rtx setter ATTRIBUTE_UNUSED, void *data)
7506f491 1636{
84832317
MM
1637 rtx last_set_insn = (rtx) data;
1638
7506f491
DE
1639 if (GET_CODE (dest) == SUBREG)
1640 dest = SUBREG_REG (dest);
1641
7b1b4aed 1642 if (REG_P (dest))
7506f491 1643 record_last_reg_set_info (last_set_insn, REGNO (dest));
7b1b4aed 1644 else if (MEM_P (dest)
7506f491
DE
1645 /* Ignore pushes, they clobber nothing. */
1646 && ! push_operand (dest, GET_MODE (dest)))
1647 record_last_mem_set_info (last_set_insn);
1648}
1649
1650/* Top level function to create an expression or assignment hash table.
1651
1652 Expression entries are placed in the hash table if
1653 - they are of the form (set (pseudo-reg) src),
1654 - src is something we want to perform GCSE on,
1655 - none of the operands are subsequently modified in the block
1656
1657 Assignment entries are placed in the hash table if
1658 - they are of the form (set (pseudo-reg) src),
1659 - src is something we want to perform const/copy propagation on,
1660 - none of the operands or target are subsequently modified in the block
c4c81601 1661
7506f491
DE
1662 Currently src must be a pseudo-reg or a const_int.
1663
02280659 1664 TABLE is the table computed. */
7506f491
DE
1665
1666static void
7e5487a2 1667compute_hash_table_work (struct hash_table_d *table)
7506f491 1668{
5f39ad47 1669 int i;
7506f491 1670
a13d4ebf 1671 /* re-Cache any INSN_LIST nodes we have allocated. */
73991d6a 1672 clear_modify_mem_tables ();
7506f491 1673 /* Some working arrays used to track first and last set in each block. */
5f39ad47 1674 reg_avail_info = GNEWVEC (struct reg_avail_info, max_reg_num ());
80c29cc4 1675
5f39ad47 1676 for (i = 0; i < max_reg_num (); ++i)
e0082a72 1677 reg_avail_info[i].last_bb = NULL;
7506f491 1678
e0082a72 1679 FOR_EACH_BB (current_bb)
7506f491
DE
1680 {
1681 rtx insn;
770ae6cc 1682 unsigned int regno;
7506f491
DE
1683
1684 /* First pass over the instructions records information used to
4a81774c 1685 determine when registers and memory are first and last set. */
eb232f4e 1686 FOR_BB_INSNS (current_bb, insn)
7506f491 1687 {
2c3c49de 1688 if (! INSN_P (insn))
7506f491
DE
1689 continue;
1690
7b1b4aed 1691 if (CALL_P (insn))
7506f491
DE
1692 {
1693 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
6e14af16 1694 if (TEST_HARD_REG_BIT (regs_invalidated_by_call, regno))
7506f491 1695 record_last_reg_set_info (insn, regno);
c4c81601 1696
24a28584 1697 mark_call (insn);
7506f491
DE
1698 }
1699
84832317 1700 note_stores (PATTERN (insn), record_last_set_info, insn);
7506f491
DE
1701 }
1702
fbef91d8
RS
1703 /* Insert implicit sets in the hash table. */
1704 if (table->set_p
1705 && implicit_sets[current_bb->index] != NULL_RTX)
1706 hash_scan_set (implicit_sets[current_bb->index],
a813c111 1707 BB_HEAD (current_bb), table);
fbef91d8 1708
7506f491 1709 /* The next pass builds the hash table. */
eb232f4e 1710 FOR_BB_INSNS (current_bb, insn)
2c3c49de 1711 if (INSN_P (insn))
4a8cae83 1712 hash_scan_insn (insn, table);
7506f491
DE
1713 }
1714
80c29cc4
RZ
1715 free (reg_avail_info);
1716 reg_avail_info = NULL;
7506f491
DE
1717}
1718
02280659 1719/* Allocate space for the set/expr hash TABLE.
02280659
ZD
1720 It is used to determine the number of buckets to use.
1721 SET_P determines whether set or expression table will
1722 be created. */
7506f491
DE
1723
1724static void
b5b8b0ac 1725alloc_hash_table (struct hash_table_d *table, int set_p)
7506f491
DE
1726{
1727 int n;
1728
b5b8b0ac
AO
1729 n = get_max_insn_count ();
1730
1731 table->size = n / 4;
02280659
ZD
1732 if (table->size < 11)
1733 table->size = 11;
c4c81601 1734
7506f491
DE
1735 /* Attempt to maintain efficient use of hash table.
1736 Making it an odd number is simplest for now.
1737 ??? Later take some measurements. */
02280659
ZD
1738 table->size |= 1;
1739 n = table->size * sizeof (struct expr *);
1b4572a8 1740 table->table = GNEWVAR (struct expr *, n);
02280659 1741 table->set_p = set_p;
7506f491
DE
1742}
1743
02280659 1744/* Free things allocated by alloc_hash_table. */
7506f491
DE
1745
1746static void
7e5487a2 1747free_hash_table (struct hash_table_d *table)
7506f491 1748{
02280659 1749 free (table->table);
7506f491
DE
1750}
1751
02280659
ZD
1752/* Compute the hash TABLE for doing copy/const propagation or
1753 expression hash table. */
7506f491
DE
1754
1755static void
7e5487a2 1756compute_hash_table (struct hash_table_d *table)
7506f491
DE
1757{
1758 /* Initialize count of number of entries in hash table. */
02280659 1759 table->n_elems = 0;
703ad42b 1760 memset (table->table, 0, table->size * sizeof (struct expr *));
7506f491 1761
02280659 1762 compute_hash_table_work (table);
7506f491
DE
1763}
1764\f
1765/* Expression tracking support. */
1766
ceda50e9
RH
1767/* Lookup REGNO in the set TABLE. The result is a pointer to the
1768 table entry, or NULL if not found. */
7506f491
DE
1769
1770static struct expr *
7e5487a2 1771lookup_set (unsigned int regno, struct hash_table_d *table)
7506f491 1772{
02280659 1773 unsigned int hash = hash_set (regno, table->size);
7506f491
DE
1774 struct expr *expr;
1775
02280659 1776 expr = table->table[hash];
7506f491 1777
ceda50e9
RH
1778 while (expr && REGNO (SET_DEST (expr->expr)) != regno)
1779 expr = expr->next_same_hash;
7506f491
DE
1780
1781 return expr;
1782}
1783
1784/* Return the next entry for REGNO in list EXPR. */
1785
1786static struct expr *
1d088dee 1787next_set (unsigned int regno, struct expr *expr)
7506f491
DE
1788{
1789 do
1790 expr = expr->next_same_hash;
1791 while (expr && REGNO (SET_DEST (expr->expr)) != regno);
c4c81601 1792
7506f491
DE
1793 return expr;
1794}
1795
0fe854a7
RH
1796/* Like free_INSN_LIST_list or free_EXPR_LIST_list, except that the node
1797 types may be mixed. */
1798
1799static void
1d088dee 1800free_insn_expr_list_list (rtx *listp)
0fe854a7
RH
1801{
1802 rtx list, next;
1803
1804 for (list = *listp; list ; list = next)
1805 {
1806 next = XEXP (list, 1);
1807 if (GET_CODE (list) == EXPR_LIST)
1808 free_EXPR_LIST_node (list);
1809 else
1810 free_INSN_LIST_node (list);
1811 }
1812
1813 *listp = NULL;
1814}
1815
73991d6a
JH
1816/* Clear canon_modify_mem_list and modify_mem_list tables. */
1817static void
1d088dee 1818clear_modify_mem_tables (void)
73991d6a 1819{
3cd8c58a 1820 unsigned i;
87c476a2 1821 bitmap_iterator bi;
73991d6a 1822
87c476a2
ZD
1823 EXECUTE_IF_SET_IN_BITMAP (modify_mem_list_set, 0, i, bi)
1824 {
1825 free_INSN_LIST_list (modify_mem_list + i);
87c476a2
ZD
1826 free_insn_expr_list_list (canon_modify_mem_list + i);
1827 }
9a6cf911 1828 bitmap_clear (modify_mem_list_set);
aa47fcfa 1829 bitmap_clear (blocks_with_calls);
73991d6a
JH
1830}
1831
9a6cf911 1832/* Release memory used by modify_mem_list_set. */
73991d6a
JH
1833
1834static void
1d088dee 1835free_modify_mem_tables (void)
73991d6a
JH
1836{
1837 clear_modify_mem_tables ();
1838 free (modify_mem_list);
1839 free (canon_modify_mem_list);
1840 modify_mem_list = 0;
1841 canon_modify_mem_list = 0;
1842}
1843
7506f491
DE
1844/* Reset tables used to keep track of what's still available [since the
1845 start of the block]. */
1846
1847static void
1d088dee 1848reset_opr_set_tables (void)
7506f491
DE
1849{
1850 /* Maintain a bitmap of which regs have been set since beginning of
1851 the block. */
73991d6a 1852 CLEAR_REG_SET (reg_set_bitmap);
c4c81601 1853
7506f491
DE
1854 /* Also keep a record of the last instruction to modify memory.
1855 For now this is very trivial, we only record whether any memory
1856 location has been modified. */
73991d6a 1857 clear_modify_mem_tables ();
7506f491
DE
1858}
1859
cc2902df 1860/* Return nonzero if the operands of X are not set before INSN in
7506f491
DE
1861 INSN's basic block. */
1862
1863static int
ed7a4b4b 1864oprs_not_set_p (const_rtx x, const_rtx insn)
7506f491 1865{
c4c81601 1866 int i, j;
7506f491 1867 enum rtx_code code;
6f7d635c 1868 const char *fmt;
7506f491 1869
7506f491
DE
1870 if (x == 0)
1871 return 1;
1872
1873 code = GET_CODE (x);
1874 switch (code)
1875 {
1876 case PC:
1877 case CC0:
1878 case CONST:
1879 case CONST_INT:
1880 case CONST_DOUBLE:
091a3ac7 1881 case CONST_FIXED:
69ef87e2 1882 case CONST_VECTOR:
7506f491
DE
1883 case SYMBOL_REF:
1884 case LABEL_REF:
1885 case ADDR_VEC:
1886 case ADDR_DIFF_VEC:
1887 return 1;
1888
1889 case MEM:
589005ff 1890 if (load_killed_in_block_p (BLOCK_FOR_INSN (insn),
4a81774c 1891 DF_INSN_LUID (insn), x, 0))
a13d4ebf 1892 return 0;
c4c81601
RK
1893 else
1894 return oprs_not_set_p (XEXP (x, 0), insn);
7506f491
DE
1895
1896 case REG:
73991d6a 1897 return ! REGNO_REG_SET_P (reg_set_bitmap, REGNO (x));
7506f491
DE
1898
1899 default:
1900 break;
1901 }
1902
c4c81601 1903 for (i = GET_RTX_LENGTH (code) - 1, fmt = GET_RTX_FORMAT (code); i >= 0; i--)
7506f491
DE
1904 {
1905 if (fmt[i] == 'e')
1906 {
7506f491
DE
1907 /* If we are about to do the last recursive call
1908 needed at this level, change it into iteration.
1909 This function is called enough to be worth it. */
1910 if (i == 0)
c4c81601
RK
1911 return oprs_not_set_p (XEXP (x, i), insn);
1912
1913 if (! oprs_not_set_p (XEXP (x, i), insn))
7506f491
DE
1914 return 0;
1915 }
1916 else if (fmt[i] == 'E')
c4c81601
RK
1917 for (j = 0; j < XVECLEN (x, i); j++)
1918 if (! oprs_not_set_p (XVECEXP (x, i, j), insn))
1919 return 0;
7506f491
DE
1920 }
1921
1922 return 1;
1923}
1924
1925/* Mark things set by a CALL. */
1926
1927static void
1d088dee 1928mark_call (rtx insn)
7506f491 1929{
becfd6e5 1930 if (! RTL_CONST_OR_PURE_CALL_P (insn))
a13d4ebf 1931 record_last_mem_set_info (insn);
7506f491
DE
1932}
1933
1934/* Mark things set by a SET. */
1935
1936static void
1d088dee 1937mark_set (rtx pat, rtx insn)
7506f491
DE
1938{
1939 rtx dest = SET_DEST (pat);
1940
1941 while (GET_CODE (dest) == SUBREG
1942 || GET_CODE (dest) == ZERO_EXTRACT
7506f491
DE
1943 || GET_CODE (dest) == STRICT_LOW_PART)
1944 dest = XEXP (dest, 0);
1945
7b1b4aed 1946 if (REG_P (dest))
73991d6a 1947 SET_REGNO_REG_SET (reg_set_bitmap, REGNO (dest));
7b1b4aed 1948 else if (MEM_P (dest))
a13d4ebf
AM
1949 record_last_mem_set_info (insn);
1950
6e72d1e9 1951 if (GET_CODE (SET_SRC (pat)) == CALL)
b5ce41ff 1952 mark_call (insn);
7506f491
DE
1953}
1954
1955/* Record things set by a CLOBBER. */
1956
1957static void
1d088dee 1958mark_clobber (rtx pat, rtx insn)
7506f491
DE
1959{
1960 rtx clob = XEXP (pat, 0);
1961
1962 while (GET_CODE (clob) == SUBREG || GET_CODE (clob) == STRICT_LOW_PART)
1963 clob = XEXP (clob, 0);
1964
7b1b4aed 1965 if (REG_P (clob))
73991d6a 1966 SET_REGNO_REG_SET (reg_set_bitmap, REGNO (clob));
a13d4ebf
AM
1967 else
1968 record_last_mem_set_info (insn);
7506f491
DE
1969}
1970
1971/* Record things set by INSN.
1972 This data is used by oprs_not_set_p. */
1973
1974static void
1d088dee 1975mark_oprs_set (rtx insn)
7506f491
DE
1976{
1977 rtx pat = PATTERN (insn);
c4c81601 1978 int i;
7506f491
DE
1979
1980 if (GET_CODE (pat) == SET)
1981 mark_set (pat, insn);
1982 else if (GET_CODE (pat) == PARALLEL)
c4c81601
RK
1983 for (i = 0; i < XVECLEN (pat, 0); i++)
1984 {
1985 rtx x = XVECEXP (pat, 0, i);
1986
1987 if (GET_CODE (x) == SET)
1988 mark_set (x, insn);
1989 else if (GET_CODE (x) == CLOBBER)
1990 mark_clobber (x, insn);
6e72d1e9 1991 else if (GET_CODE (x) == CALL)
c4c81601
RK
1992 mark_call (insn);
1993 }
7506f491 1994
7506f491
DE
1995 else if (GET_CODE (pat) == CLOBBER)
1996 mark_clobber (pat, insn);
6e72d1e9 1997 else if (GET_CODE (pat) == CALL)
b5ce41ff 1998 mark_call (insn);
7506f491 1999}
b5ce41ff 2000
7506f491
DE
2001\f
2002/* Compute copy/constant propagation working variables. */
2003
2004/* Local properties of assignments. */
7506f491
DE
2005static sbitmap *cprop_pavloc;
2006static sbitmap *cprop_absaltered;
2007
2008/* Global properties of assignments (computed from the local properties). */
7506f491
DE
2009static sbitmap *cprop_avin;
2010static sbitmap *cprop_avout;
2011
c4c81601
RK
2012/* Allocate vars used for copy/const propagation. N_BLOCKS is the number of
2013 basic blocks. N_SETS is the number of sets. */
7506f491
DE
2014
2015static void
1d088dee 2016alloc_cprop_mem (int n_blocks, int n_sets)
7506f491
DE
2017{
2018 cprop_pavloc = sbitmap_vector_alloc (n_blocks, n_sets);
2019 cprop_absaltered = sbitmap_vector_alloc (n_blocks, n_sets);
2020
2021 cprop_avin = sbitmap_vector_alloc (n_blocks, n_sets);
2022 cprop_avout = sbitmap_vector_alloc (n_blocks, n_sets);
2023}
2024
2025/* Free vars used by copy/const propagation. */
2026
2027static void
1d088dee 2028free_cprop_mem (void)
7506f491 2029{
5a660bff
DB
2030 sbitmap_vector_free (cprop_pavloc);
2031 sbitmap_vector_free (cprop_absaltered);
2032 sbitmap_vector_free (cprop_avin);
2033 sbitmap_vector_free (cprop_avout);
7506f491
DE
2034}
2035
c4c81601
RK
2036/* For each block, compute whether X is transparent. X is either an
2037 expression or an assignment [though we don't care which, for this context
2038 an assignment is treated as an expression]. For each block where an
2039 element of X is modified, set (SET_P == 1) or reset (SET_P == 0) the INDX
2040 bit in BMAP. */
7506f491
DE
2041
2042static void
ed7a4b4b 2043compute_transp (const_rtx x, int indx, sbitmap *bmap, int set_p)
7506f491 2044{
e0082a72 2045 int i, j;
7506f491 2046 enum rtx_code code;
6f7d635c 2047 const char *fmt;
7506f491 2048
c4c81601
RK
2049 /* repeat is used to turn tail-recursion into iteration since GCC
2050 can't do it when there's no return value. */
7506f491
DE
2051 repeat:
2052
2053 if (x == 0)
2054 return;
2055
2056 code = GET_CODE (x);
2057 switch (code)
2058 {
2059 case REG:
c4c81601
RK
2060 if (set_p)
2061 {
4a81774c
SB
2062 df_ref def;
2063 for (def = DF_REG_DEF_CHAIN (REGNO (x));
2064 def;
2065 def = DF_REF_NEXT_REG (def))
2066 SET_BIT (bmap[DF_REF_BB (def)->index], indx);
c4c81601
RK
2067 }
2068 else
2069 {
4a81774c
SB
2070 df_ref def;
2071 for (def = DF_REG_DEF_CHAIN (REGNO (x));
2072 def;
2073 def = DF_REF_NEXT_REG (def))
2074 RESET_BIT (bmap[DF_REF_BB (def)->index], indx);
c4c81601 2075 }
7506f491 2076
c4c81601 2077 return;
7506f491
DE
2078
2079 case MEM:
16c5b95d
MH
2080 if (! MEM_READONLY_P (x))
2081 {
2082 bitmap_iterator bi;
2083 unsigned bb_index;
aa47fcfa 2084
16c5b95d
MH
2085 /* First handle all the blocks with calls. We don't need to
2086 do any list walking for them. */
2087 EXECUTE_IF_SET_IN_BITMAP (blocks_with_calls, 0, bb_index, bi)
2088 {
2089 if (set_p)
2090 SET_BIT (bmap[bb_index], indx);
2091 else
2092 RESET_BIT (bmap[bb_index], indx);
2093 }
aa47fcfa 2094
16c5b95d
MH
2095 /* Now iterate over the blocks which have memory modifications
2096 but which do not have any calls. */
b8698a0f 2097 EXECUTE_IF_AND_COMPL_IN_BITMAP (modify_mem_list_set,
16c5b95d
MH
2098 blocks_with_calls,
2099 0, bb_index, bi)
aa47fcfa 2100 {
16c5b95d 2101 rtx list_entry = canon_modify_mem_list[bb_index];
aa47fcfa 2102
16c5b95d 2103 while (list_entry)
aa47fcfa 2104 {
16c5b95d
MH
2105 rtx dest, dest_addr;
2106
2107 /* LIST_ENTRY must be an INSN of some kind that sets memory.
2108 Examine each hunk of memory that is modified. */
2109
2110 dest = XEXP (list_entry, 0);
2111 list_entry = XEXP (list_entry, 1);
2112 dest_addr = XEXP (list_entry, 0);
2113
2114 if (canon_true_dependence (dest, GET_MODE (dest), dest_addr,
6216f94e 2115 x, NULL_RTX, rtx_addr_varies_p))
16c5b95d
MH
2116 {
2117 if (set_p)
2118 SET_BIT (bmap[bb_index], indx);
2119 else
2120 RESET_BIT (bmap[bb_index], indx);
2121 break;
2122 }
2123 list_entry = XEXP (list_entry, 1);
2124 }
aa47fcfa 2125 }
16c5b95d 2126 }
c4c81601 2127
7506f491
DE
2128 x = XEXP (x, 0);
2129 goto repeat;
2130
2131 case PC:
2132 case CC0: /*FIXME*/
2133 case CONST:
2134 case CONST_INT:
2135 case CONST_DOUBLE:
091a3ac7 2136 case CONST_FIXED:
69ef87e2 2137 case CONST_VECTOR:
7506f491
DE
2138 case SYMBOL_REF:
2139 case LABEL_REF:
2140 case ADDR_VEC:
2141 case ADDR_DIFF_VEC:
2142 return;
2143
2144 default:
2145 break;
2146 }
2147
c4c81601 2148 for (i = GET_RTX_LENGTH (code) - 1, fmt = GET_RTX_FORMAT (code); i >= 0; i--)
7506f491
DE
2149 {
2150 if (fmt[i] == 'e')
2151 {
7506f491
DE
2152 /* If we are about to do the last recursive call
2153 needed at this level, change it into iteration.
2154 This function is called enough to be worth it. */
2155 if (i == 0)
2156 {
c4c81601 2157 x = XEXP (x, i);
7506f491
DE
2158 goto repeat;
2159 }
c4c81601
RK
2160
2161 compute_transp (XEXP (x, i), indx, bmap, set_p);
7506f491
DE
2162 }
2163 else if (fmt[i] == 'E')
c4c81601
RK
2164 for (j = 0; j < XVECLEN (x, i); j++)
2165 compute_transp (XVECEXP (x, i, j), indx, bmap, set_p);
7506f491
DE
2166 }
2167}
2168
7506f491
DE
2169/* Top level routine to do the dataflow analysis needed by copy/const
2170 propagation. */
2171
2172static void
1d088dee 2173compute_cprop_data (void)
7506f491 2174{
02280659 2175 compute_local_properties (cprop_absaltered, cprop_pavloc, NULL, &set_hash_table);
ce724250
JL
2176 compute_available (cprop_pavloc, cprop_absaltered,
2177 cprop_avout, cprop_avin);
7506f491
DE
2178}
2179\f
2180/* Copy/constant propagation. */
2181
7506f491
DE
2182/* Maximum number of register uses in an insn that we handle. */
2183#define MAX_USES 8
2184
2185/* Table of uses found in an insn.
2186 Allocated statically to avoid alloc/free complexity and overhead. */
2187static struct reg_use reg_use_table[MAX_USES];
2188
2189/* Index into `reg_use_table' while building it. */
2190static int reg_use_count;
2191
c4c81601
RK
2192/* Set up a list of register numbers used in INSN. The found uses are stored
2193 in `reg_use_table'. `reg_use_count' is initialized to zero before entry,
2194 and contains the number of uses in the table upon exit.
7506f491 2195
c4c81601
RK
2196 ??? If a register appears multiple times we will record it multiple times.
2197 This doesn't hurt anything but it will slow things down. */
7506f491
DE
2198
2199static void
1d088dee 2200find_used_regs (rtx *xptr, void *data ATTRIBUTE_UNUSED)
7506f491 2201{
c4c81601 2202 int i, j;
7506f491 2203 enum rtx_code code;
6f7d635c 2204 const char *fmt;
9e71c818 2205 rtx x = *xptr;
7506f491 2206
c4c81601
RK
2207 /* repeat is used to turn tail-recursion into iteration since GCC
2208 can't do it when there's no return value. */
7506f491 2209 repeat:
7506f491
DE
2210 if (x == 0)
2211 return;
2212
2213 code = GET_CODE (x);
9e71c818 2214 if (REG_P (x))
7506f491 2215 {
7506f491
DE
2216 if (reg_use_count == MAX_USES)
2217 return;
c4c81601 2218
7506f491
DE
2219 reg_use_table[reg_use_count].reg_rtx = x;
2220 reg_use_count++;
7506f491
DE
2221 }
2222
2223 /* Recursively scan the operands of this expression. */
2224
c4c81601 2225 for (i = GET_RTX_LENGTH (code) - 1, fmt = GET_RTX_FORMAT (code); i >= 0; i--)
7506f491
DE
2226 {
2227 if (fmt[i] == 'e')
2228 {
2229 /* If we are about to do the last recursive call
2230 needed at this level, change it into iteration.
2231 This function is called enough to be worth it. */
2232 if (i == 0)
2233 {
2234 x = XEXP (x, 0);
2235 goto repeat;
2236 }
c4c81601 2237
9e71c818 2238 find_used_regs (&XEXP (x, i), data);
7506f491
DE
2239 }
2240 else if (fmt[i] == 'E')
c4c81601 2241 for (j = 0; j < XVECLEN (x, i); j++)
9e71c818 2242 find_used_regs (&XVECEXP (x, i, j), data);
7506f491
DE
2243 }
2244}
2245
2246/* Try to replace all non-SET_DEST occurrences of FROM in INSN with TO.
cc2902df 2247 Returns nonzero is successful. */
7506f491
DE
2248
2249static int
1d088dee 2250try_replace_reg (rtx from, rtx to, rtx insn)
7506f491 2251{
205eb6e7 2252 rtx note = find_reg_equal_equiv_note (insn);
fb0c0a12 2253 rtx src = 0;
172890a2
RK
2254 int success = 0;
2255 rtx set = single_set (insn);
833fc3ad 2256
3e916873
JH
2257 /* Usually we substitute easy stuff, so we won't copy everything.
2258 We however need to take care to not duplicate non-trivial CONST
2259 expressions. */
2260 to = copy_rtx (to);
2261
2b773ee2
JH
2262 validate_replace_src_group (from, to, insn);
2263 if (num_changes_pending () && apply_change_group ())
2264 success = 1;
9e71c818 2265
9feff114
JDA
2266 /* Try to simplify SET_SRC if we have substituted a constant. */
2267 if (success && set && CONSTANT_P (to))
2268 {
2269 src = simplify_rtx (SET_SRC (set));
2270
2271 if (src)
2272 validate_change (insn, &SET_SRC (set), src, 0);
2273 }
2274
205eb6e7
RS
2275 /* If there is already a REG_EQUAL note, update the expression in it
2276 with our replacement. */
2277 if (note != 0 && REG_NOTE_KIND (note) == REG_EQUAL)
a31830a7 2278 set_unique_reg_note (insn, REG_EQUAL,
3af4ba41 2279 simplify_replace_rtx (XEXP (note, 0), from, to));
f305679f 2280 if (!success && set && reg_mentioned_p (from, SET_SRC (set)))
833fc3ad 2281 {
f305679f
JH
2282 /* If above failed and this is a single set, try to simplify the source of
2283 the set given our substitution. We could perhaps try this for multiple
2284 SETs, but it probably won't buy us anything. */
172890a2
RK
2285 src = simplify_replace_rtx (SET_SRC (set), from, to);
2286
9e71c818
JH
2287 if (!rtx_equal_p (src, SET_SRC (set))
2288 && validate_change (insn, &SET_SRC (set), src, 0))
172890a2 2289 success = 1;
833fc3ad 2290
bbd288a4
FS
2291 /* If we've failed to do replacement, have a single SET, don't already
2292 have a note, and have no special SET, add a REG_EQUAL note to not
2293 lose information. */
2294 if (!success && note == 0 && set != 0
70a640af
AK
2295 && GET_CODE (SET_DEST (set)) != ZERO_EXTRACT
2296 && GET_CODE (SET_DEST (set)) != STRICT_LOW_PART)
f305679f
JH
2297 note = set_unique_reg_note (insn, REG_EQUAL, copy_rtx (src));
2298 }
e251e2a2 2299
172890a2
RK
2300 /* REG_EQUAL may get simplified into register.
2301 We don't allow that. Remove that note. This code ought
fbe5a4a6 2302 not to happen, because previous code ought to synthesize
172890a2 2303 reg-reg move, but be on the safe side. */
205eb6e7 2304 if (note && REG_NOTE_KIND (note) == REG_EQUAL && REG_P (XEXP (note, 0)))
172890a2 2305 remove_note (insn, note);
833fc3ad 2306
833fc3ad
JH
2307 return success;
2308}
c4c81601
RK
2309
2310/* Find a set of REGNOs that are available on entry to INSN's block. Returns
2311 NULL no such set is found. */
7506f491
DE
2312
2313static struct expr *
1d088dee 2314find_avail_set (int regno, rtx insn)
7506f491 2315{
cafba495
BS
2316 /* SET1 contains the last set found that can be returned to the caller for
2317 use in a substitution. */
2318 struct expr *set1 = 0;
589005ff 2319
cafba495 2320 /* Loops are not possible here. To get a loop we would need two sets
454ff5cb 2321 available at the start of the block containing INSN. i.e. we would
cafba495
BS
2322 need two sets like this available at the start of the block:
2323
2324 (set (reg X) (reg Y))
2325 (set (reg Y) (reg X))
2326
2327 This can not happen since the set of (reg Y) would have killed the
2328 set of (reg X) making it unavailable at the start of this block. */
2329 while (1)
8e42ace1 2330 {
cafba495 2331 rtx src;
ceda50e9 2332 struct expr *set = lookup_set (regno, &set_hash_table);
cafba495
BS
2333
2334 /* Find a set that is available at the start of the block
2335 which contains INSN. */
2336 while (set)
2337 {
2338 if (TEST_BIT (cprop_avin[BLOCK_NUM (insn)], set->bitmap_index))
2339 break;
2340 set = next_set (regno, set);
2341 }
7506f491 2342
cafba495
BS
2343 /* If no available set was found we've reached the end of the
2344 (possibly empty) copy chain. */
2345 if (set == 0)
589005ff 2346 break;
cafba495 2347
282899df 2348 gcc_assert (GET_CODE (set->expr) == SET);
cafba495
BS
2349
2350 src = SET_SRC (set->expr);
2351
2352 /* We know the set is available.
2353 Now check that SRC is ANTLOC (i.e. none of the source operands
589005ff 2354 have changed since the start of the block).
cafba495
BS
2355
2356 If the source operand changed, we may still use it for the next
2357 iteration of this loop, but we may not use it for substitutions. */
c4c81601 2358
6b2d1c9e 2359 if (gcse_constant_p (src) || oprs_not_set_p (src, insn))
cafba495
BS
2360 set1 = set;
2361
2362 /* If the source of the set is anything except a register, then
2363 we have reached the end of the copy chain. */
7b1b4aed 2364 if (! REG_P (src))
7506f491 2365 break;
7506f491 2366
454ff5cb 2367 /* Follow the copy chain, i.e. start another iteration of the loop
cafba495
BS
2368 and see if we have an available copy into SRC. */
2369 regno = REGNO (src);
8e42ace1 2370 }
cafba495
BS
2371
2372 /* SET1 holds the last set that was available and anticipatable at
2373 INSN. */
2374 return set1;
7506f491
DE
2375}
2376
abd535b6 2377/* Subroutine of cprop_insn that tries to propagate constants into
0e3f0221 2378 JUMP_INSNS. JUMP must be a conditional jump. If SETCC is non-NULL
fbe5a4a6 2379 it is the instruction that immediately precedes JUMP, and must be a
818b6b7f 2380 single SET of a register. FROM is what we will try to replace,
0e3f0221 2381 SRC is the constant we will try to substitute for it. Returns nonzero
589005ff 2382 if a change was made. */
c4c81601 2383
abd535b6 2384static int
1d088dee 2385cprop_jump (basic_block bb, rtx setcc, rtx jump, rtx from, rtx src)
abd535b6 2386{
60564289 2387 rtx new_rtx, set_src, note_src;
0e3f0221 2388 rtx set = pc_set (jump);
bc6688b4 2389 rtx note = find_reg_equal_equiv_note (jump);
0e3f0221 2390
bc6688b4
RS
2391 if (note)
2392 {
2393 note_src = XEXP (note, 0);
2394 if (GET_CODE (note_src) == EXPR_LIST)
2395 note_src = NULL_RTX;
2396 }
2397 else note_src = NULL_RTX;
2398
2399 /* Prefer REG_EQUAL notes except those containing EXPR_LISTs. */
2400 set_src = note_src ? note_src : SET_SRC (set);
2401
2402 /* First substitute the SETCC condition into the JUMP instruction,
2403 then substitute that given values into this expanded JUMP. */
2404 if (setcc != NULL_RTX
48ddd46c
JH
2405 && !modified_between_p (from, setcc, jump)
2406 && !modified_between_p (src, setcc, jump))
b2f02503 2407 {
bc6688b4 2408 rtx setcc_src;
b2f02503 2409 rtx setcc_set = single_set (setcc);
bc6688b4
RS
2410 rtx setcc_note = find_reg_equal_equiv_note (setcc);
2411 setcc_src = (setcc_note && GET_CODE (XEXP (setcc_note, 0)) != EXPR_LIST)
2412 ? XEXP (setcc_note, 0) : SET_SRC (setcc_set);
2413 set_src = simplify_replace_rtx (set_src, SET_DEST (setcc_set),
2414 setcc_src);
b2f02503 2415 }
0e3f0221 2416 else
bc6688b4 2417 setcc = NULL_RTX;
0e3f0221 2418
60564289 2419 new_rtx = simplify_replace_rtx (set_src, from, src);
abd535b6 2420
bc6688b4 2421 /* If no simplification can be made, then try the next register. */
60564289 2422 if (rtx_equal_p (new_rtx, SET_SRC (set)))
9e48c409 2423 return 0;
589005ff 2424
7d5ab30e 2425 /* If this is now a no-op delete it, otherwise this must be a valid insn. */
60564289 2426 if (new_rtx == pc_rtx)
0e3f0221 2427 delete_insn (jump);
7d5ab30e 2428 else
abd535b6 2429 {
48ddd46c
JH
2430 /* Ensure the value computed inside the jump insn to be equivalent
2431 to one computed by setcc. */
60564289 2432 if (setcc && modified_in_p (new_rtx, setcc))
48ddd46c 2433 return 0;
60564289 2434 if (! validate_unshare_change (jump, &SET_SRC (set), new_rtx, 0))
bc6688b4
RS
2435 {
2436 /* When (some) constants are not valid in a comparison, and there
2437 are two registers to be replaced by constants before the entire
2438 comparison can be folded into a constant, we need to keep
2439 intermediate information in REG_EQUAL notes. For targets with
2440 separate compare insns, such notes are added by try_replace_reg.
2441 When we have a combined compare-and-branch instruction, however,
2442 we need to attach a note to the branch itself to make this
2443 optimization work. */
2444
60564289
KG
2445 if (!rtx_equal_p (new_rtx, note_src))
2446 set_unique_reg_note (jump, REG_EQUAL, copy_rtx (new_rtx));
bc6688b4
RS
2447 return 0;
2448 }
2449
2450 /* Remove REG_EQUAL note after simplification. */
2451 if (note_src)
2452 remove_note (jump, note);
7d5ab30e 2453 }
abd535b6 2454
0e3f0221
RS
2455#ifdef HAVE_cc0
2456 /* Delete the cc0 setter. */
818b6b7f 2457 if (setcc != NULL && CC0_P (SET_DEST (single_set (setcc))))
0e3f0221
RS
2458 delete_insn (setcc);
2459#endif
2460
27fb79ad 2461 global_const_prop_count++;
10d22567 2462 if (dump_file != NULL)
172890a2 2463 {
10d22567 2464 fprintf (dump_file,
27fb79ad 2465 "GLOBAL CONST-PROP: Replacing reg %d in jump_insn %d with constant ",
0e3f0221 2466 REGNO (from), INSN_UID (jump));
10d22567
ZD
2467 print_rtl (dump_file, src);
2468 fprintf (dump_file, "\n");
abd535b6 2469 }
0005550b 2470 purge_dead_edges (bb);
172890a2 2471
d0a55efc
JJ
2472 /* If a conditional jump has been changed into unconditional jump, remove
2473 the jump and make the edge fallthru - this is always called in
2474 cfglayout mode. */
60564289 2475 if (new_rtx != pc_rtx && simplejump_p (jump))
d0a55efc
JJ
2476 {
2477 edge e;
2478 edge_iterator ei;
2479
2480 for (ei = ei_start (bb->succs); (e = ei_safe_edge (ei)); ei_next (&ei))
2481 if (e->dest != EXIT_BLOCK_PTR
2482 && BB_HEAD (e->dest) == JUMP_LABEL (jump))
2483 {
2484 e->flags |= EDGE_FALLTHRU;
2485 break;
2486 }
2487 delete_insn (jump);
2488 }
2489
172890a2 2490 return 1;
abd535b6
BS
2491}
2492
ae860ff7 2493static bool
5f39ad47 2494constprop_register (rtx insn, rtx from, rtx to)
ae860ff7
JH
2495{
2496 rtx sset;
2497
2498 /* Check for reg or cc0 setting instructions followed by
2499 conditional branch instructions first. */
5f39ad47 2500 if ((sset = single_set (insn)) != NULL
244d05fb 2501 && NEXT_INSN (insn)
ae860ff7
JH
2502 && any_condjump_p (NEXT_INSN (insn)) && onlyjump_p (NEXT_INSN (insn)))
2503 {
2504 rtx dest = SET_DEST (sset);
2505 if ((REG_P (dest) || CC0_P (dest))
2506 && cprop_jump (BLOCK_FOR_INSN (insn), insn, NEXT_INSN (insn), from, to))
2507 return 1;
2508 }
2509
2510 /* Handle normal insns next. */
4b4bf941 2511 if (NONJUMP_INSN_P (insn)
ae860ff7
JH
2512 && try_replace_reg (from, to, insn))
2513 return 1;
2514
2515 /* Try to propagate a CONST_INT into a conditional jump.
2516 We're pretty specific about what we will handle in this
2517 code, we can extend this as necessary over time.
2518
2519 Right now the insn in question must look like
2520 (set (pc) (if_then_else ...)) */
5f39ad47 2521 else if (any_condjump_p (insn) && onlyjump_p (insn))
ae860ff7
JH
2522 return cprop_jump (BLOCK_FOR_INSN (insn), NULL, insn, from, to);
2523 return 0;
2524}
2525
7506f491 2526/* Perform constant and copy propagation on INSN.
cc2902df 2527 The result is nonzero if a change was made. */
7506f491
DE
2528
2529static int
5f39ad47 2530cprop_insn (rtx insn)
7506f491
DE
2531{
2532 struct reg_use *reg_used;
2533 int changed = 0;
833fc3ad 2534 rtx note;
7506f491 2535
9e71c818 2536 if (!INSN_P (insn))
7506f491
DE
2537 return 0;
2538
2539 reg_use_count = 0;
9e71c818 2540 note_uses (&PATTERN (insn), find_used_regs, NULL);
589005ff 2541
172890a2 2542 note = find_reg_equal_equiv_note (insn);
833fc3ad 2543
dc297297 2544 /* We may win even when propagating constants into notes. */
833fc3ad 2545 if (note)
9e71c818 2546 find_used_regs (&XEXP (note, 0), NULL);
7506f491 2547
c4c81601
RK
2548 for (reg_used = &reg_use_table[0]; reg_use_count > 0;
2549 reg_used++, reg_use_count--)
7506f491 2550 {
770ae6cc 2551 unsigned int regno = REGNO (reg_used->reg_rtx);
7506f491
DE
2552 rtx pat, src;
2553 struct expr *set;
7506f491 2554
7506f491
DE
2555 /* If the register has already been set in this block, there's
2556 nothing we can do. */
2557 if (! oprs_not_set_p (reg_used->reg_rtx, insn))
2558 continue;
2559
2560 /* Find an assignment that sets reg_used and is available
2561 at the start of the block. */
2562 set = find_avail_set (regno, insn);
2563 if (! set)
2564 continue;
589005ff 2565
7506f491
DE
2566 pat = set->expr;
2567 /* ??? We might be able to handle PARALLELs. Later. */
282899df 2568 gcc_assert (GET_CODE (pat) == SET);
c4c81601 2569
7506f491
DE
2570 src = SET_SRC (pat);
2571
e78d9500 2572 /* Constant propagation. */
6b2d1c9e 2573 if (gcse_constant_p (src))
7506f491 2574 {
5f39ad47 2575 if (constprop_register (insn, reg_used->reg_rtx, src))
7506f491
DE
2576 {
2577 changed = 1;
27fb79ad 2578 global_const_prop_count++;
10d22567 2579 if (dump_file != NULL)
7506f491 2580 {
10d22567
ZD
2581 fprintf (dump_file, "GLOBAL CONST-PROP: Replacing reg %d in ", regno);
2582 fprintf (dump_file, "insn %d with constant ", INSN_UID (insn));
2583 print_rtl (dump_file, src);
2584 fprintf (dump_file, "\n");
7506f491 2585 }
bc6688b4
RS
2586 if (INSN_DELETED_P (insn))
2587 return 1;
7506f491
DE
2588 }
2589 }
7b1b4aed 2590 else if (REG_P (src)
7506f491
DE
2591 && REGNO (src) >= FIRST_PSEUDO_REGISTER
2592 && REGNO (src) != regno)
2593 {
cafba495 2594 if (try_replace_reg (reg_used->reg_rtx, src, insn))
7506f491 2595 {
cafba495 2596 changed = 1;
27fb79ad 2597 global_copy_prop_count++;
10d22567 2598 if (dump_file != NULL)
7506f491 2599 {
10d22567 2600 fprintf (dump_file, "GLOBAL COPY-PROP: Replacing reg %d in insn %d",
c4c81601 2601 regno, INSN_UID (insn));
10d22567 2602 fprintf (dump_file, " with reg %d\n", REGNO (src));
7506f491 2603 }
cafba495
BS
2604
2605 /* The original insn setting reg_used may or may not now be
2606 deletable. We leave the deletion to flow. */
2607 /* FIXME: If it turns out that the insn isn't deletable,
2608 then we may have unnecessarily extended register lifetimes
2609 and made things worse. */
7506f491
DE
2610 }
2611 }
2612 }
2613
b5b8b0ac
AO
2614 if (changed && DEBUG_INSN_P (insn))
2615 return 0;
2616
7506f491
DE
2617 return changed;
2618}
2619
710ee3ed
RH
2620/* Like find_used_regs, but avoid recording uses that appear in
2621 input-output contexts such as zero_extract or pre_dec. This
2622 restricts the cases we consider to those for which local cprop
2623 can legitimately make replacements. */
2624
2625static void
1d088dee 2626local_cprop_find_used_regs (rtx *xptr, void *data)
710ee3ed
RH
2627{
2628 rtx x = *xptr;
2629
2630 if (x == 0)
2631 return;
2632
2633 switch (GET_CODE (x))
2634 {
2635 case ZERO_EXTRACT:
2636 case SIGN_EXTRACT:
2637 case STRICT_LOW_PART:
2638 return;
2639
2640 case PRE_DEC:
2641 case PRE_INC:
2642 case POST_DEC:
2643 case POST_INC:
2644 case PRE_MODIFY:
2645 case POST_MODIFY:
2646 /* Can only legitimately appear this early in the context of
2647 stack pushes for function arguments, but handle all of the
2648 codes nonetheless. */
2649 return;
2650
2651 case SUBREG:
2652 /* Setting a subreg of a register larger than word_mode leaves
2653 the non-written words unchanged. */
2654 if (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) > BITS_PER_WORD)
2655 return;
2656 break;
2657
2658 default:
2659 break;
2660 }
2661
2662 find_used_regs (xptr, data);
2663}
1d088dee 2664
5f39ad47 2665/* Try to perform local const/copy propagation on X in INSN. */
e197b6fc 2666
ae860ff7 2667static bool
5f39ad47 2668do_local_cprop (rtx x, rtx insn)
ae860ff7
JH
2669{
2670 rtx newreg = NULL, newcnst = NULL;
2671
e197b6fc
RH
2672 /* Rule out USE instructions and ASM statements as we don't want to
2673 change the hard registers mentioned. */
7b1b4aed 2674 if (REG_P (x)
ae860ff7 2675 && (REGNO (x) >= FIRST_PSEUDO_REGISTER
e197b6fc
RH
2676 || (GET_CODE (PATTERN (insn)) != USE
2677 && asm_noperands (PATTERN (insn)) < 0)))
ae860ff7
JH
2678 {
2679 cselib_val *val = cselib_lookup (x, GET_MODE (x), 0);
2680 struct elt_loc_list *l;
2681
2682 if (!val)
2683 return false;
2684 for (l = val->locs; l; l = l->next)
2685 {
2686 rtx this_rtx = l->loc;
46690369
JH
2687 rtx note;
2688
6b2d1c9e 2689 if (gcse_constant_p (this_rtx))
ae860ff7 2690 newcnst = this_rtx;
46690369
JH
2691 if (REG_P (this_rtx) && REGNO (this_rtx) >= FIRST_PSEUDO_REGISTER
2692 /* Don't copy propagate if it has attached REG_EQUIV note.
2693 At this point this only function parameters should have
2694 REG_EQUIV notes and if the argument slot is used somewhere
2695 explicitly, it means address of parameter has been taken,
2696 so we should not extend the lifetime of the pseudo. */
2697 && (!(note = find_reg_note (l->setting_insn, REG_EQUIV, NULL_RTX))
7b1b4aed 2698 || ! MEM_P (XEXP (note, 0))))
ae860ff7
JH
2699 newreg = this_rtx;
2700 }
5f39ad47 2701 if (newcnst && constprop_register (insn, x, newcnst))
ae860ff7 2702 {
10d22567 2703 if (dump_file != NULL)
ae860ff7 2704 {
10d22567 2705 fprintf (dump_file, "LOCAL CONST-PROP: Replacing reg %d in ",
ae860ff7 2706 REGNO (x));
10d22567 2707 fprintf (dump_file, "insn %d with constant ",
ae860ff7 2708 INSN_UID (insn));
10d22567
ZD
2709 print_rtl (dump_file, newcnst);
2710 fprintf (dump_file, "\n");
ae860ff7 2711 }
27fb79ad 2712 local_const_prop_count++;
ae860ff7
JH
2713 return true;
2714 }
2715 else if (newreg && newreg != x && try_replace_reg (x, newreg, insn))
2716 {
10d22567 2717 if (dump_file != NULL)
ae860ff7 2718 {
10d22567 2719 fprintf (dump_file,
ae860ff7
JH
2720 "LOCAL COPY-PROP: Replacing reg %d in insn %d",
2721 REGNO (x), INSN_UID (insn));
10d22567 2722 fprintf (dump_file, " with reg %d\n", REGNO (newreg));
ae860ff7 2723 }
27fb79ad 2724 local_copy_prop_count++;
ae860ff7
JH
2725 return true;
2726 }
2727 }
2728 return false;
2729}
2730
5f39ad47 2731/* Do local const/copy propagation (i.e. within each basic block). */
eb232f4e 2732
5f39ad47
SB
2733static int
2734local_cprop_pass (void)
ae860ff7 2735{
eb232f4e 2736 basic_block bb;
ae860ff7
JH
2737 rtx insn;
2738 struct reg_use *reg_used;
1649d92f 2739 bool changed = false;
ae860ff7 2740
463301c3 2741 cselib_init (false);
eb232f4e 2742 FOR_EACH_BB (bb)
ae860ff7 2743 {
eb232f4e 2744 FOR_BB_INSNS (bb, insn)
ae860ff7 2745 {
eb232f4e 2746 if (INSN_P (insn))
ae860ff7 2747 {
4a8cae83 2748 rtx note = find_reg_equal_equiv_note (insn);
eb232f4e
SB
2749 do
2750 {
2751 reg_use_count = 0;
2752 note_uses (&PATTERN (insn), local_cprop_find_used_regs,
2753 NULL);
2754 if (note)
2755 local_cprop_find_used_regs (&XEXP (note, 0), NULL);
2756
2757 for (reg_used = &reg_use_table[0]; reg_use_count > 0;
2758 reg_used++, reg_use_count--)
6fb5fa3c 2759 {
5f39ad47 2760 if (do_local_cprop (reg_used->reg_rtx, insn))
6fb5fa3c
DB
2761 {
2762 changed = true;
2763 break;
2764 }
2765 }
eb232f4e 2766 if (INSN_DELETED_P (insn))
1649d92f 2767 break;
eb232f4e
SB
2768 }
2769 while (reg_use_count);
ae860ff7 2770 }
eb232f4e 2771 cselib_process_insn (insn);
ae860ff7 2772 }
eb232f4e 2773
4a8cae83 2774 /* Forget everything at the end of a basic block. */
eb232f4e 2775 cselib_clear_table ();
ae860ff7 2776 }
eb232f4e 2777
ae860ff7 2778 cselib_finish ();
eb232f4e 2779
7506f491
DE
2780 return changed;
2781}
2782
fbef91d8
RS
2783/* Similar to get_condition, only the resulting condition must be
2784 valid at JUMP, instead of at EARLIEST.
2785
2786 This differs from noce_get_condition in ifcvt.c in that we prefer not to
2787 settle for the condition variable in the jump instruction being integral.
2788 We prefer to be able to record the value of a user variable, rather than
2789 the value of a temporary used in a condition. This could be solved by
aabcd309 2790 recording the value of *every* register scanned by canonicalize_condition,
fbef91d8
RS
2791 but this would require some code reorganization. */
2792
2fa4a849 2793rtx
1d088dee 2794fis_get_condition (rtx jump)
fbef91d8 2795{
45d09c02 2796 return get_condition (jump, NULL, false, true);
fbef91d8
RS
2797}
2798
b0656d8b
JW
2799/* Check the comparison COND to see if we can safely form an implicit set from
2800 it. COND is either an EQ or NE comparison. */
2801
2802static bool
ed7a4b4b 2803implicit_set_cond_p (const_rtx cond)
b0656d8b 2804{
ed7a4b4b
KG
2805 const enum machine_mode mode = GET_MODE (XEXP (cond, 0));
2806 const_rtx cst = XEXP (cond, 1);
b0656d8b
JW
2807
2808 /* We can't perform this optimization if either operand might be or might
2809 contain a signed zero. */
2810 if (HONOR_SIGNED_ZEROS (mode))
2811 {
2812 /* It is sufficient to check if CST is or contains a zero. We must
2813 handle float, complex, and vector. If any subpart is a zero, then
2814 the optimization can't be performed. */
2815 /* ??? The complex and vector checks are not implemented yet. We just
2816 always return zero for them. */
2817 if (GET_CODE (cst) == CONST_DOUBLE)
2818 {
2819 REAL_VALUE_TYPE d;
2820 REAL_VALUE_FROM_CONST_DOUBLE (d, cst);
2821 if (REAL_VALUES_EQUAL (d, dconst0))
2822 return 0;
2823 }
2824 else
2825 return 0;
2826 }
2827
2828 return gcse_constant_p (cst);
2829}
2830
fbef91d8
RS
2831/* Find the implicit sets of a function. An "implicit set" is a constraint
2832 on the value of a variable, implied by a conditional jump. For example,
2833 following "if (x == 2)", the then branch may be optimized as though the
2834 conditional performed an "explicit set", in this example, "x = 2". This
2835 function records the set patterns that are implicit at the start of each
5f39ad47
SB
2836 basic block.
2837
2838 FIXME: This would be more effective if critical edges are pre-split. As
2839 it is now, we can't record implicit sets for blocks that have
2840 critical successor edges. This results in missed optimizations
2841 and in more (unnecessary) work in cfgcleanup.c:thread_jump(). */
fbef91d8
RS
2842
2843static void
1d088dee 2844find_implicit_sets (void)
fbef91d8
RS
2845{
2846 basic_block bb, dest;
2847 unsigned int count;
60564289 2848 rtx cond, new_rtx;
fbef91d8
RS
2849
2850 count = 0;
2851 FOR_EACH_BB (bb)
a98ebe2e 2852 /* Check for more than one successor. */
628f6a4e 2853 if (EDGE_COUNT (bb->succs) > 1)
fbef91d8 2854 {
a813c111 2855 cond = fis_get_condition (BB_END (bb));
fbef91d8
RS
2856
2857 if (cond
2858 && (GET_CODE (cond) == EQ || GET_CODE (cond) == NE)
7b1b4aed 2859 && REG_P (XEXP (cond, 0))
fbef91d8 2860 && REGNO (XEXP (cond, 0)) >= FIRST_PSEUDO_REGISTER
b0656d8b 2861 && implicit_set_cond_p (cond))
fbef91d8
RS
2862 {
2863 dest = GET_CODE (cond) == EQ ? BRANCH_EDGE (bb)->dest
2864 : FALLTHRU_EDGE (bb)->dest;
2865
5f39ad47
SB
2866 if (dest
2867 /* Record nothing for a critical edge. */
2868 && single_pred_p (dest)
fbef91d8
RS
2869 && dest != EXIT_BLOCK_PTR)
2870 {
60564289 2871 new_rtx = gen_rtx_SET (VOIDmode, XEXP (cond, 0),
fbef91d8 2872 XEXP (cond, 1));
60564289 2873 implicit_sets[dest->index] = new_rtx;
10d22567 2874 if (dump_file)
fbef91d8 2875 {
10d22567 2876 fprintf(dump_file, "Implicit set of reg %d in ",
fbef91d8 2877 REGNO (XEXP (cond, 0)));
10d22567 2878 fprintf(dump_file, "basic block %d\n", dest->index);
fbef91d8
RS
2879 }
2880 count++;
2881 }
2882 }
2883 }
2884
10d22567
ZD
2885 if (dump_file)
2886 fprintf (dump_file, "Found %d implicit sets\n", count);
fbef91d8
RS
2887}
2888
0e3f0221
RS
2889/* Bypass conditional jumps. */
2890
7821bfc7
RS
2891/* The value of last_basic_block at the beginning of the jump_bypass
2892 pass. The use of redirect_edge_and_branch_force may introduce new
2893 basic blocks, but the data flow analysis is only valid for basic
2894 block indices less than bypass_last_basic_block. */
2895
2896static int bypass_last_basic_block;
2897
0e3f0221
RS
2898/* Find a set of REGNO to a constant that is available at the end of basic
2899 block BB. Returns NULL if no such set is found. Based heavily upon
2900 find_avail_set. */
2901
2902static struct expr *
1d088dee 2903find_bypass_set (int regno, int bb)
0e3f0221
RS
2904{
2905 struct expr *result = 0;
2906
2907 for (;;)
2908 {
2909 rtx src;
ceda50e9 2910 struct expr *set = lookup_set (regno, &set_hash_table);
0e3f0221
RS
2911
2912 while (set)
2913 {
2914 if (TEST_BIT (cprop_avout[bb], set->bitmap_index))
2915 break;
2916 set = next_set (regno, set);
2917 }
2918
2919 if (set == 0)
2920 break;
2921
282899df 2922 gcc_assert (GET_CODE (set->expr) == SET);
0e3f0221
RS
2923
2924 src = SET_SRC (set->expr);
6b2d1c9e 2925 if (gcse_constant_p (src))
0e3f0221
RS
2926 result = set;
2927
7b1b4aed 2928 if (! REG_P (src))
0e3f0221
RS
2929 break;
2930
2931 regno = REGNO (src);
2932 }
2933 return result;
2934}
2935
2936
e129b3f9
RS
2937/* Subroutine of bypass_block that checks whether a pseudo is killed by
2938 any of the instructions inserted on an edge. Jump bypassing places
2939 condition code setters on CFG edges using insert_insn_on_edge. This
2940 function is required to check that our data flow analysis is still
2941 valid prior to commit_edge_insertions. */
2942
2943static bool
ed7a4b4b 2944reg_killed_on_edge (const_rtx reg, const_edge e)
e129b3f9
RS
2945{
2946 rtx insn;
2947
6de9cd9a 2948 for (insn = e->insns.r; insn; insn = NEXT_INSN (insn))
e129b3f9
RS
2949 if (INSN_P (insn) && reg_set_p (reg, insn))
2950 return true;
2951
2952 return false;
2953}
2954
0e3f0221
RS
2955/* Subroutine of bypass_conditional_jumps that attempts to bypass the given
2956 basic block BB which has more than one predecessor. If not NULL, SETCC
2957 is the first instruction of BB, which is immediately followed by JUMP_INSN
2958 JUMP. Otherwise, SETCC is NULL, and JUMP is the first insn of BB.
e129b3f9
RS
2959 Returns nonzero if a change was made.
2960
e0bb17a8 2961 During the jump bypassing pass, we may place copies of SETCC instructions
e129b3f9
RS
2962 on CFG edges. The following routine must be careful to pay attention to
2963 these inserted insns when performing its transformations. */
0e3f0221
RS
2964
2965static int
1d088dee 2966bypass_block (basic_block bb, rtx setcc, rtx jump)
0e3f0221
RS
2967{
2968 rtx insn, note;
628f6a4e 2969 edge e, edest;
818b6b7f 2970 int i, change;
72b8d451 2971 int may_be_loop_header;
628f6a4e
BE
2972 unsigned removed_p;
2973 edge_iterator ei;
0e3f0221
RS
2974
2975 insn = (setcc != NULL) ? setcc : jump;
2976
2977 /* Determine set of register uses in INSN. */
2978 reg_use_count = 0;
2979 note_uses (&PATTERN (insn), find_used_regs, NULL);
2980 note = find_reg_equal_equiv_note (insn);
2981 if (note)
2982 find_used_regs (&XEXP (note, 0), NULL);
2983
72b8d451 2984 may_be_loop_header = false;
628f6a4e 2985 FOR_EACH_EDGE (e, ei, bb->preds)
72b8d451
ZD
2986 if (e->flags & EDGE_DFS_BACK)
2987 {
2988 may_be_loop_header = true;
2989 break;
2990 }
2991
0e3f0221 2992 change = 0;
628f6a4e 2993 for (ei = ei_start (bb->preds); (e = ei_safe_edge (ei)); )
0e3f0221 2994 {
628f6a4e 2995 removed_p = 0;
b8698a0f 2996
7821bfc7 2997 if (e->flags & EDGE_COMPLEX)
628f6a4e
BE
2998 {
2999 ei_next (&ei);
3000 continue;
3001 }
7821bfc7
RS
3002
3003 /* We can't redirect edges from new basic blocks. */
3004 if (e->src->index >= bypass_last_basic_block)
628f6a4e
BE
3005 {
3006 ei_next (&ei);
3007 continue;
3008 }
7821bfc7 3009
72b8d451 3010 /* The irreducible loops created by redirecting of edges entering the
e0bb17a8
KH
3011 loop from outside would decrease effectiveness of some of the following
3012 optimizations, so prevent this. */
72b8d451
ZD
3013 if (may_be_loop_header
3014 && !(e->flags & EDGE_DFS_BACK))
628f6a4e
BE
3015 {
3016 ei_next (&ei);
3017 continue;
3018 }
72b8d451 3019
0e3f0221
RS
3020 for (i = 0; i < reg_use_count; i++)
3021 {
3022 struct reg_use *reg_used = &reg_use_table[i];
589005ff 3023 unsigned int regno = REGNO (reg_used->reg_rtx);
818b6b7f 3024 basic_block dest, old_dest;
589005ff 3025 struct expr *set;
60564289 3026 rtx src, new_rtx;
0e3f0221 3027
589005ff 3028 set = find_bypass_set (regno, e->src->index);
0e3f0221
RS
3029
3030 if (! set)
3031 continue;
3032
e129b3f9 3033 /* Check the data flow is valid after edge insertions. */
6de9cd9a 3034 if (e->insns.r && reg_killed_on_edge (reg_used->reg_rtx, e))
e129b3f9
RS
3035 continue;
3036
589005ff 3037 src = SET_SRC (pc_set (jump));
0e3f0221
RS
3038
3039 if (setcc != NULL)
3af4ba41
RS
3040 src = simplify_replace_rtx (src,
3041 SET_DEST (PATTERN (setcc)),
3042 SET_SRC (PATTERN (setcc)));
0e3f0221 3043
60564289 3044 new_rtx = simplify_replace_rtx (src, reg_used->reg_rtx,
3af4ba41 3045 SET_SRC (set->expr));
0e3f0221 3046
1d088dee 3047 /* Jump bypassing may have already placed instructions on
e129b3f9
RS
3048 edges of the CFG. We can't bypass an outgoing edge that
3049 has instructions associated with it, as these insns won't
3050 get executed if the incoming edge is redirected. */
3051
60564289 3052 if (new_rtx == pc_rtx)
e129b3f9
RS
3053 {
3054 edest = FALLTHRU_EDGE (bb);
6de9cd9a 3055 dest = edest->insns.r ? NULL : edest->dest;
e129b3f9 3056 }
60564289 3057 else if (GET_CODE (new_rtx) == LABEL_REF)
e129b3f9 3058 {
60564289 3059 dest = BLOCK_FOR_INSN (XEXP (new_rtx, 0));
e129b3f9 3060 /* Don't bypass edges containing instructions. */
c7d1b449
KH
3061 edest = find_edge (bb, dest);
3062 if (edest && edest->insns.r)
3063 dest = NULL;
e129b3f9 3064 }
0e3f0221
RS
3065 else
3066 dest = NULL;
3067
a544524a
JH
3068 /* Avoid unification of the edge with other edges from original
3069 branch. We would end up emitting the instruction on "both"
3070 edges. */
7b1b4aed 3071
c7d1b449
KH
3072 if (dest && setcc && !CC0_P (SET_DEST (PATTERN (setcc)))
3073 && find_edge (e->src, dest))
3074 dest = NULL;
a544524a 3075
818b6b7f 3076 old_dest = e->dest;
7821bfc7
RS
3077 if (dest != NULL
3078 && dest != old_dest
3079 && dest != EXIT_BLOCK_PTR)
3080 {
3081 redirect_edge_and_branch_force (e, dest);
3082
818b6b7f 3083 /* Copy the register setter to the redirected edge.
0e3f0221
RS
3084 Don't copy CC0 setters, as CC0 is dead after jump. */
3085 if (setcc)
3086 {
3087 rtx pat = PATTERN (setcc);
818b6b7f 3088 if (!CC0_P (SET_DEST (pat)))
0e3f0221
RS
3089 insert_insn_on_edge (copy_insn (pat), e);
3090 }
3091
10d22567 3092 if (dump_file != NULL)
0e3f0221 3093 {
10d22567 3094 fprintf (dump_file, "JUMP-BYPASS: Proved reg %d "
27fb79ad 3095 "in jump_insn %d equals constant ",
818b6b7f 3096 regno, INSN_UID (jump));
10d22567
ZD
3097 print_rtl (dump_file, SET_SRC (set->expr));
3098 fprintf (dump_file, "\nBypass edge from %d->%d to %d\n",
818b6b7f 3099 e->src->index, old_dest->index, dest->index);
0e3f0221
RS
3100 }
3101 change = 1;
628f6a4e 3102 removed_p = 1;
0e3f0221
RS
3103 break;
3104 }
3105 }
628f6a4e
BE
3106 if (!removed_p)
3107 ei_next (&ei);
0e3f0221
RS
3108 }
3109 return change;
3110}
3111
3112/* Find basic blocks with more than one predecessor that only contain a
3113 single conditional jump. If the result of the comparison is known at
3114 compile-time from any incoming edge, redirect that edge to the
9a71ece1
RH
3115 appropriate target. Returns nonzero if a change was made.
3116
3117 This function is now mis-named, because we also handle indirect jumps. */
0e3f0221
RS
3118
3119static int
1d088dee 3120bypass_conditional_jumps (void)
0e3f0221
RS
3121{
3122 basic_block bb;
3123 int changed;
3124 rtx setcc;
3125 rtx insn;
3126 rtx dest;
3127
3128 /* Note we start at block 1. */
3129 if (ENTRY_BLOCK_PTR->next_bb == EXIT_BLOCK_PTR)
3130 return 0;
3131
7821bfc7 3132 bypass_last_basic_block = last_basic_block;
72b8d451 3133 mark_dfs_back_edges ();
7821bfc7 3134
0e3f0221
RS
3135 changed = 0;
3136 FOR_BB_BETWEEN (bb, ENTRY_BLOCK_PTR->next_bb->next_bb,
589005ff 3137 EXIT_BLOCK_PTR, next_bb)
0e3f0221
RS
3138 {
3139 /* Check for more than one predecessor. */
c5cbcccf 3140 if (!single_pred_p (bb))
0e3f0221
RS
3141 {
3142 setcc = NULL_RTX;
eb232f4e 3143 FOR_BB_INSNS (bb, insn)
b5b8b0ac
AO
3144 if (DEBUG_INSN_P (insn))
3145 continue;
3146 else if (NONJUMP_INSN_P (insn))
0e3f0221 3147 {
9543a9d2 3148 if (setcc)
0e3f0221 3149 break;
ba4f7968 3150 if (GET_CODE (PATTERN (insn)) != SET)
0e3f0221
RS
3151 break;
3152
ba4f7968 3153 dest = SET_DEST (PATTERN (insn));
818b6b7f 3154 if (REG_P (dest) || CC0_P (dest))
0e3f0221 3155 setcc = insn;
0e3f0221
RS
3156 else
3157 break;
3158 }
7b1b4aed 3159 else if (JUMP_P (insn))
0e3f0221 3160 {
9a71ece1
RH
3161 if ((any_condjump_p (insn) || computed_jump_p (insn))
3162 && onlyjump_p (insn))
0e3f0221
RS
3163 changed |= bypass_block (bb, setcc, insn);
3164 break;
3165 }
3166 else if (INSN_P (insn))
3167 break;
3168 }
3169 }
3170
818b6b7f 3171 /* If we bypassed any register setting insns, we inserted a
fbe5a4a6 3172 copy on the redirected edge. These need to be committed. */
0e3f0221 3173 if (changed)
62e5bf5d 3174 commit_edge_insertions ();
0e3f0221
RS
3175
3176 return changed;
3177}
3178\f
a65f3558 3179/* Compute PRE+LCM working variables. */
7506f491
DE
3180
3181/* Local properties of expressions. */
3182/* Nonzero for expressions that are transparent in the block. */
a65f3558 3183static sbitmap *transp;
7506f491 3184
5c35539b
RH
3185/* Nonzero for expressions that are transparent at the end of the block.
3186 This is only zero for expressions killed by abnormal critical edge
3187 created by a calls. */
a65f3558 3188static sbitmap *transpout;
5c35539b 3189
a65f3558
JL
3190/* Nonzero for expressions that are computed (available) in the block. */
3191static sbitmap *comp;
7506f491 3192
a65f3558
JL
3193/* Nonzero for expressions that are locally anticipatable in the block. */
3194static sbitmap *antloc;
7506f491 3195
a65f3558
JL
3196/* Nonzero for expressions where this block is an optimal computation
3197 point. */
3198static sbitmap *pre_optimal;
5c35539b 3199
a65f3558
JL
3200/* Nonzero for expressions which are redundant in a particular block. */
3201static sbitmap *pre_redundant;
7506f491 3202
a42cd965
AM
3203/* Nonzero for expressions which should be inserted on a specific edge. */
3204static sbitmap *pre_insert_map;
3205
3206/* Nonzero for expressions which should be deleted in a specific block. */
3207static sbitmap *pre_delete_map;
3208
3209/* Contains the edge_list returned by pre_edge_lcm. */
3210static struct edge_list *edge_list;
3211
a65f3558 3212/* Allocate vars used for PRE analysis. */
7506f491
DE
3213
3214static void
1d088dee 3215alloc_pre_mem (int n_blocks, int n_exprs)
7506f491 3216{
a65f3558
JL
3217 transp = sbitmap_vector_alloc (n_blocks, n_exprs);
3218 comp = sbitmap_vector_alloc (n_blocks, n_exprs);
3219 antloc = sbitmap_vector_alloc (n_blocks, n_exprs);
5faf03ae 3220
a42cd965
AM
3221 pre_optimal = NULL;
3222 pre_redundant = NULL;
3223 pre_insert_map = NULL;
3224 pre_delete_map = NULL;
a42cd965 3225 ae_kill = sbitmap_vector_alloc (n_blocks, n_exprs);
c4c81601 3226
a42cd965 3227 /* pre_insert and pre_delete are allocated later. */
7506f491
DE
3228}
3229
a65f3558 3230/* Free vars used for PRE analysis. */
7506f491
DE
3231
3232static void
1d088dee 3233free_pre_mem (void)
7506f491 3234{
5a660bff
DB
3235 sbitmap_vector_free (transp);
3236 sbitmap_vector_free (comp);
bd3675fc
JL
3237
3238 /* ANTLOC and AE_KILL are freed just after pre_lcm finishes. */
7506f491 3239
a42cd965 3240 if (pre_optimal)
5a660bff 3241 sbitmap_vector_free (pre_optimal);
a42cd965 3242 if (pre_redundant)
5a660bff 3243 sbitmap_vector_free (pre_redundant);
a42cd965 3244 if (pre_insert_map)
5a660bff 3245 sbitmap_vector_free (pre_insert_map);
a42cd965 3246 if (pre_delete_map)
5a660bff 3247 sbitmap_vector_free (pre_delete_map);
a42cd965 3248
bd3675fc 3249 transp = comp = NULL;
a42cd965 3250 pre_optimal = pre_redundant = pre_insert_map = pre_delete_map = NULL;
7506f491
DE
3251}
3252
3253/* Top level routine to do the dataflow analysis needed by PRE. */
3254
3255static void
1d088dee 3256compute_pre_data (void)
7506f491 3257{
b614171e 3258 sbitmap trapping_expr;
e0082a72 3259 basic_block bb;
b614171e 3260 unsigned int ui;
c66e8ae9 3261
02280659 3262 compute_local_properties (transp, comp, antloc, &expr_hash_table);
d55bc081 3263 sbitmap_vector_zero (ae_kill, last_basic_block);
c66e8ae9 3264
b614171e 3265 /* Collect expressions which might trap. */
02280659 3266 trapping_expr = sbitmap_alloc (expr_hash_table.n_elems);
b614171e 3267 sbitmap_zero (trapping_expr);
02280659 3268 for (ui = 0; ui < expr_hash_table.size; ui++)
b614171e
MM
3269 {
3270 struct expr *e;
02280659 3271 for (e = expr_hash_table.table[ui]; e != NULL; e = e->next_same_hash)
b614171e
MM
3272 if (may_trap_p (e->expr))
3273 SET_BIT (trapping_expr, e->bitmap_index);
3274 }
3275
c66e8ae9
JL
3276 /* Compute ae_kill for each basic block using:
3277
3278 ~(TRANSP | COMP)
e83f4801 3279 */
c66e8ae9 3280
e0082a72 3281 FOR_EACH_BB (bb)
c66e8ae9 3282 {
b614171e 3283 edge e;
628f6a4e 3284 edge_iterator ei;
b614171e
MM
3285
3286 /* If the current block is the destination of an abnormal edge, we
3287 kill all trapping expressions because we won't be able to properly
3288 place the instruction on the edge. So make them neither
3289 anticipatable nor transparent. This is fairly conservative. */
628f6a4e 3290 FOR_EACH_EDGE (e, ei, bb->preds)
b614171e
MM
3291 if (e->flags & EDGE_ABNORMAL)
3292 {
e0082a72
ZD
3293 sbitmap_difference (antloc[bb->index], antloc[bb->index], trapping_expr);
3294 sbitmap_difference (transp[bb->index], transp[bb->index], trapping_expr);
b614171e
MM
3295 break;
3296 }
3297
e0082a72
ZD
3298 sbitmap_a_or_b (ae_kill[bb->index], transp[bb->index], comp[bb->index]);
3299 sbitmap_not (ae_kill[bb->index], ae_kill[bb->index]);
c66e8ae9
JL
3300 }
3301
10d22567 3302 edge_list = pre_edge_lcm (expr_hash_table.n_elems, transp, comp, antloc,
a42cd965 3303 ae_kill, &pre_insert_map, &pre_delete_map);
5a660bff 3304 sbitmap_vector_free (antloc);
bd3675fc 3305 antloc = NULL;
5a660bff 3306 sbitmap_vector_free (ae_kill);
589005ff 3307 ae_kill = NULL;
76ac938b 3308 sbitmap_free (trapping_expr);
7506f491
DE
3309}
3310\f
3311/* PRE utilities */
3312
cc2902df 3313/* Return nonzero if an occurrence of expression EXPR in OCCR_BB would reach
a65f3558 3314 block BB.
7506f491
DE
3315
3316 VISITED is a pointer to a working buffer for tracking which BB's have
3317 been visited. It is NULL for the top-level call.
3318
3319 We treat reaching expressions that go through blocks containing the same
3320 reaching expression as "not reaching". E.g. if EXPR is generated in blocks
3321 2 and 3, INSN is in block 4, and 2->3->4, we treat the expression in block
3322 2 as not reaching. The intent is to improve the probability of finding
3323 only one reaching expression and to reduce register lifetimes by picking
3324 the closest such expression. */
3325
3326static int
1d088dee 3327pre_expr_reaches_here_p_work (basic_block occr_bb, struct expr *expr, basic_block bb, char *visited)
7506f491 3328{
36349f8b 3329 edge pred;
628f6a4e 3330 edge_iterator ei;
b8698a0f 3331
628f6a4e 3332 FOR_EACH_EDGE (pred, ei, bb->preds)
7506f491 3333 {
e2d2ed72 3334 basic_block pred_bb = pred->src;
7506f491 3335
36349f8b 3336 if (pred->src == ENTRY_BLOCK_PTR
7506f491 3337 /* Has predecessor has already been visited? */
0b17ab2f 3338 || visited[pred_bb->index])
c4c81601
RK
3339 ;/* Nothing to do. */
3340
7506f491 3341 /* Does this predecessor generate this expression? */
0b17ab2f 3342 else if (TEST_BIT (comp[pred_bb->index], expr->bitmap_index))
7506f491
DE
3343 {
3344 /* Is this the occurrence we're looking for?
3345 Note that there's only one generating occurrence per block
3346 so we just need to check the block number. */
a65f3558 3347 if (occr_bb == pred_bb)
7506f491 3348 return 1;
c4c81601 3349
0b17ab2f 3350 visited[pred_bb->index] = 1;
7506f491
DE
3351 }
3352 /* Ignore this predecessor if it kills the expression. */
0b17ab2f
RH
3353 else if (! TEST_BIT (transp[pred_bb->index], expr->bitmap_index))
3354 visited[pred_bb->index] = 1;
c4c81601 3355
7506f491
DE
3356 /* Neither gen nor kill. */
3357 else
ac7c5af5 3358 {
0b17ab2f 3359 visited[pred_bb->index] = 1;
89e606c9 3360 if (pre_expr_reaches_here_p_work (occr_bb, expr, pred_bb, visited))
7506f491 3361 return 1;
ac7c5af5 3362 }
7506f491
DE
3363 }
3364
3365 /* All paths have been checked. */
3366 return 0;
3367}
283a2545
RL
3368
3369/* The wrapper for pre_expr_reaches_here_work that ensures that any
dc297297 3370 memory allocated for that function is returned. */
283a2545
RL
3371
3372static int
1d088dee 3373pre_expr_reaches_here_p (basic_block occr_bb, struct expr *expr, basic_block bb)
283a2545
RL
3374{
3375 int rval;
5ed6ace5 3376 char *visited = XCNEWVEC (char, last_basic_block);
283a2545 3377
8e42ace1 3378 rval = pre_expr_reaches_here_p_work (occr_bb, expr, bb, visited);
283a2545
RL
3379
3380 free (visited);
c4c81601 3381 return rval;
283a2545 3382}
7506f491 3383\f
a42cd965
AM
3384
3385/* Given an expr, generate RTL which we can insert at the end of a BB,
589005ff 3386 or on an edge. Set the block number of any insns generated to
a42cd965
AM
3387 the value of BB. */
3388
3389static rtx
1d088dee 3390process_insert_insn (struct expr *expr)
a42cd965
AM
3391{
3392 rtx reg = expr->reaching_reg;
fb0c0a12
RK
3393 rtx exp = copy_rtx (expr->expr);
3394 rtx pat;
a42cd965
AM
3395
3396 start_sequence ();
fb0c0a12
RK
3397
3398 /* If the expression is something that's an operand, like a constant,
3399 just copy it to a register. */
3400 if (general_operand (exp, GET_MODE (reg)))
3401 emit_move_insn (reg, exp);
3402
3403 /* Otherwise, make a new insn to compute this expression and make sure the
3404 insn will be recognized (this also adds any needed CLOBBERs). Copy the
3405 expression to make sure we don't have any sharing issues. */
282899df
NS
3406 else
3407 {
3408 rtx insn = emit_insn (gen_rtx_SET (VOIDmode, reg, exp));
3409
2f021b67
AP
3410 if (insn_invalid_p (insn))
3411 gcc_unreachable ();
282899df 3412 }
b8698a0f 3413
589005ff 3414
2f937369 3415 pat = get_insns ();
a42cd965
AM
3416 end_sequence ();
3417
3418 return pat;
3419}
589005ff 3420
a65f3558
JL
3421/* Add EXPR to the end of basic block BB.
3422
3423 This is used by both the PRE and code hoisting.
3424
3425 For PRE, we want to verify that the expr is either transparent
3426 or locally anticipatable in the target block. This check makes
3427 no sense for code hoisting. */
7506f491
DE
3428
3429static void
6fb5fa3c 3430insert_insn_end_basic_block (struct expr *expr, basic_block bb, int pre)
7506f491 3431{
a813c111 3432 rtx insn = BB_END (bb);
7506f491
DE
3433 rtx new_insn;
3434 rtx reg = expr->reaching_reg;
3435 int regno = REGNO (reg);
2f937369 3436 rtx pat, pat_end;
7506f491 3437
a42cd965 3438 pat = process_insert_insn (expr);
282899df 3439 gcc_assert (pat && INSN_P (pat));
2f937369
DM
3440
3441 pat_end = pat;
3442 while (NEXT_INSN (pat_end) != NULL_RTX)
3443 pat_end = NEXT_INSN (pat_end);
7506f491
DE
3444
3445 /* If the last insn is a jump, insert EXPR in front [taking care to
4d6922ee 3446 handle cc0, etc. properly]. Similarly we need to care trapping
068473ec 3447 instructions in presence of non-call exceptions. */
7506f491 3448
7b1b4aed 3449 if (JUMP_P (insn)
4b4bf941 3450 || (NONJUMP_INSN_P (insn)
c5cbcccf
ZD
3451 && (!single_succ_p (bb)
3452 || single_succ_edge (bb)->flags & EDGE_ABNORMAL)))
7506f491 3453 {
50b2596f 3454#ifdef HAVE_cc0
7506f491 3455 rtx note;
50b2596f 3456#endif
068473ec
JH
3457 /* It should always be the case that we can put these instructions
3458 anywhere in the basic block with performing PRE optimizations.
3459 Check this. */
282899df
NS
3460 gcc_assert (!NONJUMP_INSN_P (insn) || !pre
3461 || TEST_BIT (antloc[bb->index], expr->bitmap_index)
3462 || TEST_BIT (transp[bb->index], expr->bitmap_index));
7506f491
DE
3463
3464 /* If this is a jump table, then we can't insert stuff here. Since
3465 we know the previous real insn must be the tablejump, we insert
3466 the new instruction just before the tablejump. */
3467 if (GET_CODE (PATTERN (insn)) == ADDR_VEC
3468 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC)
3469 insn = prev_real_insn (insn);
3470
3471#ifdef HAVE_cc0
3472 /* FIXME: 'twould be nice to call prev_cc0_setter here but it aborts
3473 if cc0 isn't set. */
3474 note = find_reg_note (insn, REG_CC_SETTER, NULL_RTX);
3475 if (note)
3476 insn = XEXP (note, 0);
3477 else
3478 {
3479 rtx maybe_cc0_setter = prev_nonnote_insn (insn);
3480 if (maybe_cc0_setter
2c3c49de 3481 && INSN_P (maybe_cc0_setter)
7506f491
DE
3482 && sets_cc0_p (PATTERN (maybe_cc0_setter)))
3483 insn = maybe_cc0_setter;
3484 }
3485#endif
3486 /* FIXME: What if something in cc0/jump uses value set in new insn? */
6fb5fa3c 3487 new_insn = emit_insn_before_noloc (pat, insn, bb);
3947e2f9 3488 }
c4c81601 3489
3947e2f9
RH
3490 /* Likewise if the last insn is a call, as will happen in the presence
3491 of exception handling. */
7b1b4aed 3492 else if (CALL_P (insn)
c5cbcccf
ZD
3493 && (!single_succ_p (bb)
3494 || single_succ_edge (bb)->flags & EDGE_ABNORMAL))
3947e2f9 3495 {
3947e2f9
RH
3496 /* Keeping in mind SMALL_REGISTER_CLASSES and parameters in registers,
3497 we search backward and place the instructions before the first
3498 parameter is loaded. Do this for everyone for consistency and a
fbe5a4a6 3499 presumption that we'll get better code elsewhere as well.
3947e2f9 3500
c4c81601 3501 It should always be the case that we can put these instructions
a65f3558
JL
3502 anywhere in the basic block with performing PRE optimizations.
3503 Check this. */
c4c81601 3504
282899df
NS
3505 gcc_assert (!pre
3506 || TEST_BIT (antloc[bb->index], expr->bitmap_index)
3507 || TEST_BIT (transp[bb->index], expr->bitmap_index));
3947e2f9
RH
3508
3509 /* Since different machines initialize their parameter registers
3510 in different orders, assume nothing. Collect the set of all
3511 parameter registers. */
a813c111 3512 insn = find_first_parameter_load (insn, BB_HEAD (bb));
3947e2f9 3513
b1d26727
JL
3514 /* If we found all the parameter loads, then we want to insert
3515 before the first parameter load.
3516
3517 If we did not find all the parameter loads, then we might have
3518 stopped on the head of the block, which could be a CODE_LABEL.
3519 If we inserted before the CODE_LABEL, then we would be putting
3520 the insn in the wrong basic block. In that case, put the insn
b5229628 3521 after the CODE_LABEL. Also, respect NOTE_INSN_BASIC_BLOCK. */
7b1b4aed 3522 while (LABEL_P (insn)
589ca5cb 3523 || NOTE_INSN_BASIC_BLOCK_P (insn))
b5229628 3524 insn = NEXT_INSN (insn);
c4c81601 3525
6fb5fa3c 3526 new_insn = emit_insn_before_noloc (pat, insn, bb);
7506f491
DE
3527 }
3528 else
6fb5fa3c 3529 new_insn = emit_insn_after_noloc (pat, insn, bb);
7506f491 3530
2f937369 3531 while (1)
a65f3558 3532 {
2f937369 3533 if (INSN_P (pat))
4a81774c 3534 add_label_notes (PATTERN (pat), new_insn);
2f937369
DM
3535 if (pat == pat_end)
3536 break;
3537 pat = NEXT_INSN (pat);
a65f3558 3538 }
3947e2f9 3539
7506f491
DE
3540 gcse_create_count++;
3541
10d22567 3542 if (dump_file)
7506f491 3543 {
10d22567 3544 fprintf (dump_file, "PRE/HOIST: end of bb %d, insn %d, ",
0b17ab2f 3545 bb->index, INSN_UID (new_insn));
10d22567 3546 fprintf (dump_file, "copying expression %d to reg %d\n",
c4c81601 3547 expr->bitmap_index, regno);
7506f491
DE
3548 }
3549}
3550
a42cd965
AM
3551/* Insert partially redundant expressions on edges in the CFG to make
3552 the expressions fully redundant. */
7506f491 3553
a42cd965 3554static int
1d088dee 3555pre_edge_insert (struct edge_list *edge_list, struct expr **index_map)
7506f491 3556{
c4c81601 3557 int e, i, j, num_edges, set_size, did_insert = 0;
a65f3558
JL
3558 sbitmap *inserted;
3559
a42cd965
AM
3560 /* Where PRE_INSERT_MAP is nonzero, we add the expression on that edge
3561 if it reaches any of the deleted expressions. */
7506f491 3562
a42cd965
AM
3563 set_size = pre_insert_map[0]->size;
3564 num_edges = NUM_EDGES (edge_list);
02280659 3565 inserted = sbitmap_vector_alloc (num_edges, expr_hash_table.n_elems);
a42cd965 3566 sbitmap_vector_zero (inserted, num_edges);
7506f491 3567
a42cd965 3568 for (e = 0; e < num_edges; e++)
7506f491
DE
3569 {
3570 int indx;
e2d2ed72 3571 basic_block bb = INDEX_EDGE_PRED_BB (edge_list, e);
a65f3558 3572
a65f3558 3573 for (i = indx = 0; i < set_size; i++, indx += SBITMAP_ELT_BITS)
7506f491 3574 {
a42cd965 3575 SBITMAP_ELT_TYPE insert = pre_insert_map[e]->elms[i];
7506f491 3576
02280659 3577 for (j = indx; insert && j < (int) expr_hash_table.n_elems; j++, insert >>= 1)
c4c81601
RK
3578 if ((insert & 1) != 0 && index_map[j]->reaching_reg != NULL_RTX)
3579 {
3580 struct expr *expr = index_map[j];
3581 struct occr *occr;
a65f3558 3582
ff7cc307 3583 /* Now look at each deleted occurrence of this expression. */
c4c81601
RK
3584 for (occr = expr->antic_occr; occr != NULL; occr = occr->next)
3585 {
3586 if (! occr->deleted_p)
3587 continue;
3588
3f117656 3589 /* Insert this expression on this edge if it would
ff7cc307 3590 reach the deleted occurrence in BB. */
c4c81601
RK
3591 if (!TEST_BIT (inserted[e], j))
3592 {
3593 rtx insn;
3594 edge eg = INDEX_EDGE (edge_list, e);
3595
3596 /* We can't insert anything on an abnormal and
3597 critical edge, so we insert the insn at the end of
3598 the previous block. There are several alternatives
3599 detailed in Morgans book P277 (sec 10.5) for
3600 handling this situation. This one is easiest for
3601 now. */
3602
b16aa8a5 3603 if (eg->flags & EDGE_ABNORMAL)
6fb5fa3c 3604 insert_insn_end_basic_block (index_map[j], bb, 0);
c4c81601
RK
3605 else
3606 {
3607 insn = process_insert_insn (index_map[j]);
3608 insert_insn_on_edge (insn, eg);
3609 }
3610
10d22567 3611 if (dump_file)
c4c81601 3612 {
5f39ad47 3613 fprintf (dump_file, "PRE: edge (%d,%d), ",
0b17ab2f
RH
3614 bb->index,
3615 INDEX_EDGE_SUCC_BB (edge_list, e)->index);
10d22567 3616 fprintf (dump_file, "copy expression %d\n",
c4c81601
RK
3617 expr->bitmap_index);
3618 }
3619
a13d4ebf 3620 update_ld_motion_stores (expr);
c4c81601
RK
3621 SET_BIT (inserted[e], j);
3622 did_insert = 1;
3623 gcse_create_count++;
3624 }
3625 }
3626 }
7506f491
DE
3627 }
3628 }
5faf03ae 3629
5a660bff 3630 sbitmap_vector_free (inserted);
a42cd965 3631 return did_insert;
7506f491
DE
3632}
3633
073089a7 3634/* Copy the result of EXPR->EXPR generated by INSN to EXPR->REACHING_REG.
b885908b
MH
3635 Given "old_reg <- expr" (INSN), instead of adding after it
3636 reaching_reg <- old_reg
3637 it's better to do the following:
3638 reaching_reg <- expr
3639 old_reg <- reaching_reg
3640 because this way copy propagation can discover additional PRE
f5f2e3cd
MH
3641 opportunities. But if this fails, we try the old way.
3642 When "expr" is a store, i.e.
3643 given "MEM <- old_reg", instead of adding after it
3644 reaching_reg <- old_reg
3645 it's better to add it before as follows:
3646 reaching_reg <- old_reg
3647 MEM <- reaching_reg. */
7506f491
DE
3648
3649static void
1d088dee 3650pre_insert_copy_insn (struct expr *expr, rtx insn)
7506f491
DE
3651{
3652 rtx reg = expr->reaching_reg;
3653 int regno = REGNO (reg);
3654 int indx = expr->bitmap_index;
073089a7 3655 rtx pat = PATTERN (insn);
64068ca2 3656 rtx set, first_set, new_insn;
b885908b 3657 rtx old_reg;
073089a7 3658 int i;
7506f491 3659
073089a7 3660 /* This block matches the logic in hash_scan_insn. */
282899df 3661 switch (GET_CODE (pat))
073089a7 3662 {
282899df
NS
3663 case SET:
3664 set = pat;
3665 break;
3666
3667 case PARALLEL:
073089a7
RS
3668 /* Search through the parallel looking for the set whose
3669 source was the expression that we're interested in. */
64068ca2 3670 first_set = NULL_RTX;
073089a7
RS
3671 set = NULL_RTX;
3672 for (i = 0; i < XVECLEN (pat, 0); i++)
3673 {
3674 rtx x = XVECEXP (pat, 0, i);
64068ca2 3675 if (GET_CODE (x) == SET)
073089a7 3676 {
64068ca2
RS
3677 /* If the source was a REG_EQUAL or REG_EQUIV note, we
3678 may not find an equivalent expression, but in this
3679 case the PARALLEL will have a single set. */
3680 if (first_set == NULL_RTX)
3681 first_set = x;
3682 if (expr_equiv_p (SET_SRC (x), expr->expr))
3683 {
3684 set = x;
3685 break;
3686 }
073089a7
RS
3687 }
3688 }
64068ca2
RS
3689
3690 gcc_assert (first_set);
3691 if (set == NULL_RTX)
3692 set = first_set;
282899df
NS
3693 break;
3694
3695 default:
3696 gcc_unreachable ();
073089a7 3697 }
c4c81601 3698
7b1b4aed 3699 if (REG_P (SET_DEST (set)))
073089a7 3700 {
f5f2e3cd
MH
3701 old_reg = SET_DEST (set);
3702 /* Check if we can modify the set destination in the original insn. */
3703 if (validate_change (insn, &SET_DEST (set), reg, 0))
3704 {
3705 new_insn = gen_move_insn (old_reg, reg);
3706 new_insn = emit_insn_after (new_insn, insn);
f5f2e3cd
MH
3707 }
3708 else
3709 {
3710 new_insn = gen_move_insn (reg, old_reg);
3711 new_insn = emit_insn_after (new_insn, insn);
f5f2e3cd 3712 }
073089a7 3713 }
f5f2e3cd 3714 else /* This is possible only in case of a store to memory. */
073089a7 3715 {
f5f2e3cd 3716 old_reg = SET_SRC (set);
073089a7 3717 new_insn = gen_move_insn (reg, old_reg);
f5f2e3cd
MH
3718
3719 /* Check if we can modify the set source in the original insn. */
3720 if (validate_change (insn, &SET_SRC (set), reg, 0))
3721 new_insn = emit_insn_before (new_insn, insn);
3722 else
3723 new_insn = emit_insn_after (new_insn, insn);
073089a7 3724 }
7506f491
DE
3725
3726 gcse_create_count++;
3727
10d22567
ZD
3728 if (dump_file)
3729 fprintf (dump_file,
a42cd965
AM
3730 "PRE: bb %d, insn %d, copy expression %d in insn %d to reg %d\n",
3731 BLOCK_NUM (insn), INSN_UID (new_insn), indx,
3732 INSN_UID (insn), regno);
7506f491
DE
3733}
3734
3735/* Copy available expressions that reach the redundant expression
3736 to `reaching_reg'. */
3737
3738static void
1d088dee 3739pre_insert_copies (void)
7506f491 3740{
f5f2e3cd 3741 unsigned int i, added_copy;
c4c81601
RK
3742 struct expr *expr;
3743 struct occr *occr;
3744 struct occr *avail;
a65f3558 3745
7506f491
DE
3746 /* For each available expression in the table, copy the result to
3747 `reaching_reg' if the expression reaches a deleted one.
3748
3749 ??? The current algorithm is rather brute force.
3750 Need to do some profiling. */
3751
02280659
ZD
3752 for (i = 0; i < expr_hash_table.size; i++)
3753 for (expr = expr_hash_table.table[i]; expr != NULL; expr = expr->next_same_hash)
c4c81601
RK
3754 {
3755 /* If the basic block isn't reachable, PPOUT will be TRUE. However,
3756 we don't want to insert a copy here because the expression may not
3757 really be redundant. So only insert an insn if the expression was
3758 deleted. This test also avoids further processing if the
3759 expression wasn't deleted anywhere. */
3760 if (expr->reaching_reg == NULL)
3761 continue;
7b1b4aed 3762
f5f2e3cd 3763 /* Set when we add a copy for that expression. */
7b1b4aed 3764 added_copy = 0;
c4c81601
RK
3765
3766 for (occr = expr->antic_occr; occr != NULL; occr = occr->next)
3767 {
3768 if (! occr->deleted_p)
3769 continue;
7506f491 3770
c4c81601
RK
3771 for (avail = expr->avail_occr; avail != NULL; avail = avail->next)
3772 {
3773 rtx insn = avail->insn;
7506f491 3774
c4c81601
RK
3775 /* No need to handle this one if handled already. */
3776 if (avail->copied_p)
3777 continue;
7506f491 3778
c4c81601 3779 /* Don't handle this one if it's a redundant one. */
4a81774c 3780 if (INSN_DELETED_P (insn))
c4c81601 3781 continue;
7506f491 3782
c4c81601 3783 /* Or if the expression doesn't reach the deleted one. */
589005ff 3784 if (! pre_expr_reaches_here_p (BLOCK_FOR_INSN (avail->insn),
e2d2ed72
AM
3785 expr,
3786 BLOCK_FOR_INSN (occr->insn)))
c4c81601 3787 continue;
7506f491 3788
f5f2e3cd
MH
3789 added_copy = 1;
3790
c4c81601
RK
3791 /* Copy the result of avail to reaching_reg. */
3792 pre_insert_copy_insn (expr, insn);
3793 avail->copied_p = 1;
3794 }
3795 }
f5f2e3cd 3796
7b1b4aed 3797 if (added_copy)
f5f2e3cd 3798 update_ld_motion_stores (expr);
c4c81601 3799 }
7506f491
DE
3800}
3801
10d1bb36
JH
3802/* Emit move from SRC to DEST noting the equivalence with expression computed
3803 in INSN. */
3804static rtx
1d088dee 3805gcse_emit_move_after (rtx src, rtx dest, rtx insn)
10d1bb36 3806{
60564289 3807 rtx new_rtx;
6bdb8dd6 3808 rtx set = single_set (insn), set2;
10d1bb36
JH
3809 rtx note;
3810 rtx eqv;
3811
3812 /* This should never fail since we're creating a reg->reg copy
3813 we've verified to be valid. */
3814
60564289 3815 new_rtx = emit_insn_after (gen_move_insn (dest, src), insn);
285464d0 3816
10d1bb36 3817 /* Note the equivalence for local CSE pass. */
60564289 3818 set2 = single_set (new_rtx);
6bdb8dd6 3819 if (!set2 || !rtx_equal_p (SET_DEST (set2), dest))
60564289 3820 return new_rtx;
10d1bb36
JH
3821 if ((note = find_reg_equal_equiv_note (insn)))
3822 eqv = XEXP (note, 0);
3823 else
3824 eqv = SET_SRC (set);
3825
60564289 3826 set_unique_reg_note (new_rtx, REG_EQUAL, copy_insn_1 (eqv));
10d1bb36 3827
60564289 3828 return new_rtx;
10d1bb36
JH
3829}
3830
7506f491 3831/* Delete redundant computations.
7506f491
DE
3832 Deletion is done by changing the insn to copy the `reaching_reg' of
3833 the expression into the result of the SET. It is left to later passes
3834 (cprop, cse2, flow, combine, regmove) to propagate the copy or eliminate it.
3835
cc2902df 3836 Returns nonzero if a change is made. */
7506f491
DE
3837
3838static int
1d088dee 3839pre_delete (void)
7506f491 3840{
2e653e39 3841 unsigned int i;
63bc1d05 3842 int changed;
c4c81601
RK
3843 struct expr *expr;
3844 struct occr *occr;
a65f3558 3845
7506f491 3846 changed = 0;
02280659 3847 for (i = 0; i < expr_hash_table.size; i++)
073089a7
RS
3848 for (expr = expr_hash_table.table[i];
3849 expr != NULL;
3850 expr = expr->next_same_hash)
c4c81601
RK
3851 {
3852 int indx = expr->bitmap_index;
7506f491 3853
c4c81601
RK
3854 /* We only need to search antic_occr since we require
3855 ANTLOC != 0. */
7506f491 3856
c4c81601
RK
3857 for (occr = expr->antic_occr; occr != NULL; occr = occr->next)
3858 {
3859 rtx insn = occr->insn;
3860 rtx set;
e2d2ed72 3861 basic_block bb = BLOCK_FOR_INSN (insn);
7506f491 3862
073089a7
RS
3863 /* We only delete insns that have a single_set. */
3864 if (TEST_BIT (pre_delete_map[bb->index], indx)
6fb5fa3c
DB
3865 && (set = single_set (insn)) != 0
3866 && dbg_cnt (pre_insn))
c4c81601 3867 {
c4c81601
RK
3868 /* Create a pseudo-reg to store the result of reaching
3869 expressions into. Get the mode for the new pseudo from
3870 the mode of the original destination pseudo. */
3871 if (expr->reaching_reg == NULL)
46b71b03 3872 expr->reaching_reg = gen_reg_rtx_and_attrs (SET_DEST (set));
c4c81601 3873
9b76aa3b 3874 gcse_emit_move_after (expr->reaching_reg, SET_DEST (set), insn);
10d1bb36
JH
3875 delete_insn (insn);
3876 occr->deleted_p = 1;
10d1bb36
JH
3877 changed = 1;
3878 gcse_subst_count++;
7506f491 3879
10d22567 3880 if (dump_file)
c4c81601 3881 {
10d22567 3882 fprintf (dump_file,
c4c81601
RK
3883 "PRE: redundant insn %d (expression %d) in ",
3884 INSN_UID (insn), indx);
10d22567 3885 fprintf (dump_file, "bb %d, reaching reg is %d\n",
0b17ab2f 3886 bb->index, REGNO (expr->reaching_reg));
c4c81601
RK
3887 }
3888 }
3889 }
3890 }
7506f491
DE
3891
3892 return changed;
3893}
3894
3895/* Perform GCSE optimizations using PRE.
3896 This is called by one_pre_gcse_pass after all the dataflow analysis
3897 has been done.
3898
c4c81601
RK
3899 This is based on the original Morel-Renvoise paper Fred Chow's thesis, and
3900 lazy code motion from Knoop, Ruthing and Steffen as described in Advanced
3901 Compiler Design and Implementation.
7506f491 3902
c4c81601
RK
3903 ??? A new pseudo reg is created to hold the reaching expression. The nice
3904 thing about the classical approach is that it would try to use an existing
3905 reg. If the register can't be adequately optimized [i.e. we introduce
3906 reload problems], one could add a pass here to propagate the new register
3907 through the block.
7506f491 3908
c4c81601
RK
3909 ??? We don't handle single sets in PARALLELs because we're [currently] not
3910 able to copy the rest of the parallel when we insert copies to create full
3911 redundancies from partial redundancies. However, there's no reason why we
3912 can't handle PARALLELs in the cases where there are no partial
7506f491
DE
3913 redundancies. */
3914
3915static int
1d088dee 3916pre_gcse (void)
7506f491 3917{
2e653e39
RK
3918 unsigned int i;
3919 int did_insert, changed;
7506f491 3920 struct expr **index_map;
c4c81601 3921 struct expr *expr;
7506f491
DE
3922
3923 /* Compute a mapping from expression number (`bitmap_index') to
3924 hash table entry. */
3925
5ed6ace5 3926 index_map = XCNEWVEC (struct expr *, expr_hash_table.n_elems);
02280659
ZD
3927 for (i = 0; i < expr_hash_table.size; i++)
3928 for (expr = expr_hash_table.table[i]; expr != NULL; expr = expr->next_same_hash)
c4c81601 3929 index_map[expr->bitmap_index] = expr;
7506f491 3930
7506f491
DE
3931 /* Delete the redundant insns first so that
3932 - we know what register to use for the new insns and for the other
3933 ones with reaching expressions
3934 - we know which insns are redundant when we go to create copies */
c4c81601 3935
7506f491 3936 changed = pre_delete ();
a42cd965 3937 did_insert = pre_edge_insert (edge_list, index_map);
c4c81601 3938
7506f491 3939 /* In other places with reaching expressions, copy the expression to the
a42cd965 3940 specially allocated pseudo-reg that reaches the redundant expr. */
7506f491 3941 pre_insert_copies ();
a42cd965
AM
3942 if (did_insert)
3943 {
3944 commit_edge_insertions ();
3945 changed = 1;
3946 }
7506f491 3947
283a2545 3948 free (index_map);
7506f491
DE
3949 return changed;
3950}
3951
3952/* Top level routine to perform one PRE GCSE pass.
3953
cc2902df 3954 Return nonzero if a change was made. */
7506f491
DE
3955
3956static int
5f39ad47 3957one_pre_gcse_pass (void)
7506f491
DE
3958{
3959 int changed = 0;
3960
3961 gcse_subst_count = 0;
3962 gcse_create_count = 0;
3963
5f39ad47
SB
3964 /* Return if there's nothing to do, or it is too expensive. */
3965 if (n_basic_blocks <= NUM_FIXED_BLOCKS + 1
3966 || is_too_expensive (_("PRE disabled")))
3967 return 0;
3968
3969 /* We need alias. */
3970 init_alias_analysis ();
3971
3972 bytes_used = 0;
3973 gcc_obstack_init (&gcse_obstack);
3974 alloc_gcse_mem ();
3975
b5b8b0ac 3976 alloc_hash_table (&expr_hash_table, 0);
a42cd965 3977 add_noreturn_fake_exit_edges ();
a13d4ebf
AM
3978 if (flag_gcse_lm)
3979 compute_ld_motion_mems ();
3980
02280659 3981 compute_hash_table (&expr_hash_table);
a13d4ebf 3982 trim_ld_motion_mems ();
10d22567
ZD
3983 if (dump_file)
3984 dump_hash_table (dump_file, "Expression", &expr_hash_table);
c4c81601 3985
02280659 3986 if (expr_hash_table.n_elems > 0)
7506f491 3987 {
02280659 3988 alloc_pre_mem (last_basic_block, expr_hash_table.n_elems);
7506f491
DE
3989 compute_pre_data ();
3990 changed |= pre_gcse ();
a42cd965 3991 free_edge_list (edge_list);
7506f491
DE
3992 free_pre_mem ();
3993 }
c4c81601 3994
a13d4ebf 3995 free_ldst_mems ();
6809cbf9 3996 remove_fake_exit_edges ();
02280659 3997 free_hash_table (&expr_hash_table);
7506f491 3998
5f39ad47
SB
3999 free_gcse_mem ();
4000 obstack_free (&gcse_obstack, NULL);
4001
4002 /* We are finished with alias. */
4003 end_alias_analysis ();
4004
10d22567 4005 if (dump_file)
7506f491 4006 {
5f39ad47
SB
4007 fprintf (dump_file, "PRE GCSE of %s, %d basic blocks, %d bytes needed, ",
4008 current_function_name (), n_basic_blocks, bytes_used);
10d22567 4009 fprintf (dump_file, "%d substs, %d insns created\n",
c4c81601 4010 gcse_subst_count, gcse_create_count);
7506f491
DE
4011 }
4012
4013 return changed;
4014}
aeb2f500 4015\f
cf7c4aa6
HPN
4016/* If X contains any LABEL_REF's, add REG_LABEL_OPERAND notes for them
4017 to INSN. If such notes are added to an insn which references a
4018 CODE_LABEL, the LABEL_NUSES count is incremented. We have to add
4019 that note, because the following loop optimization pass requires
4020 them. */
aeb2f500 4021
aeb2f500
JW
4022/* ??? If there was a jump optimization pass after gcse and before loop,
4023 then we would not need to do this here, because jump would add the
cf7c4aa6 4024 necessary REG_LABEL_OPERAND and REG_LABEL_TARGET notes. */
aeb2f500
JW
4025
4026static void
1d088dee 4027add_label_notes (rtx x, rtx insn)
aeb2f500
JW
4028{
4029 enum rtx_code code = GET_CODE (x);
4030 int i, j;
6f7d635c 4031 const char *fmt;
aeb2f500
JW
4032
4033 if (code == LABEL_REF && !LABEL_REF_NONLOCAL_P (x))
4034 {
6b3603c2 4035 /* This code used to ignore labels that referred to dispatch tables to
e0bb17a8 4036 avoid flow generating (slightly) worse code.
6b3603c2 4037
ac7c5af5
JL
4038 We no longer ignore such label references (see LABEL_REF handling in
4039 mark_jump_label for additional information). */
c4c81601 4040
cb2f563b
HPN
4041 /* There's no reason for current users to emit jump-insns with
4042 such a LABEL_REF, so we don't have to handle REG_LABEL_TARGET
4043 notes. */
4044 gcc_assert (!JUMP_P (insn));
65c5f2a6
ILT
4045 add_reg_note (insn, REG_LABEL_OPERAND, XEXP (x, 0));
4046
cb2f563b
HPN
4047 if (LABEL_P (XEXP (x, 0)))
4048 LABEL_NUSES (XEXP (x, 0))++;
4049
aeb2f500
JW
4050 return;
4051 }
4052
c4c81601 4053 for (i = GET_RTX_LENGTH (code) - 1, fmt = GET_RTX_FORMAT (code); i >= 0; i--)
aeb2f500
JW
4054 {
4055 if (fmt[i] == 'e')
4056 add_label_notes (XEXP (x, i), insn);
4057 else if (fmt[i] == 'E')
4058 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4059 add_label_notes (XVECEXP (x, i, j), insn);
4060 }
4061}
a65f3558
JL
4062
4063/* Compute transparent outgoing information for each block.
4064
4065 An expression is transparent to an edge unless it is killed by
4066 the edge itself. This can only happen with abnormal control flow,
4067 when the edge is traversed through a call. This happens with
4068 non-local labels and exceptions.
4069
4070 This would not be necessary if we split the edge. While this is
4071 normally impossible for abnormal critical edges, with some effort
4072 it should be possible with exception handling, since we still have
4073 control over which handler should be invoked. But due to increased
4074 EH table sizes, this may not be worthwhile. */
4075
4076static void
1d088dee 4077compute_transpout (void)
a65f3558 4078{
e0082a72 4079 basic_block bb;
2e653e39 4080 unsigned int i;
c4c81601 4081 struct expr *expr;
a65f3558 4082
d55bc081 4083 sbitmap_vector_ones (transpout, last_basic_block);
a65f3558 4084
e0082a72 4085 FOR_EACH_BB (bb)
a65f3558 4086 {
fa10beec 4087 /* Note that flow inserted a nop at the end of basic blocks that
a65f3558
JL
4088 end in call instructions for reasons other than abnormal
4089 control flow. */
7b1b4aed 4090 if (! CALL_P (BB_END (bb)))
a65f3558
JL
4091 continue;
4092
02280659
ZD
4093 for (i = 0; i < expr_hash_table.size; i++)
4094 for (expr = expr_hash_table.table[i]; expr ; expr = expr->next_same_hash)
7b1b4aed 4095 if (MEM_P (expr->expr))
c4c81601
RK
4096 {
4097 if (GET_CODE (XEXP (expr->expr, 0)) == SYMBOL_REF
4098 && CONSTANT_POOL_ADDRESS_P (XEXP (expr->expr, 0)))
4099 continue;
589005ff 4100
c4c81601
RK
4101 /* ??? Optimally, we would use interprocedural alias
4102 analysis to determine if this mem is actually killed
4103 by this call. */
e0082a72 4104 RESET_BIT (transpout[bb->index], expr->bitmap_index);
c4c81601 4105 }
a65f3558
JL
4106 }
4107}
dfdb644f 4108
bb457bd9
JL
4109/* Code Hoisting variables and subroutines. */
4110
4111/* Very busy expressions. */
4112static sbitmap *hoist_vbein;
4113static sbitmap *hoist_vbeout;
4114
4115/* Hoistable expressions. */
4116static sbitmap *hoist_exprs;
4117
bb457bd9 4118/* ??? We could compute post dominators and run this algorithm in
68e82b83 4119 reverse to perform tail merging, doing so would probably be
bb457bd9
JL
4120 more effective than the tail merging code in jump.c.
4121
4122 It's unclear if tail merging could be run in parallel with
4123 code hoisting. It would be nice. */
4124
4125/* Allocate vars used for code hoisting analysis. */
4126
4127static void
1d088dee 4128alloc_code_hoist_mem (int n_blocks, int n_exprs)
bb457bd9
JL
4129{
4130 antloc = sbitmap_vector_alloc (n_blocks, n_exprs);
4131 transp = sbitmap_vector_alloc (n_blocks, n_exprs);
4132 comp = sbitmap_vector_alloc (n_blocks, n_exprs);
4133
4134 hoist_vbein = sbitmap_vector_alloc (n_blocks, n_exprs);
4135 hoist_vbeout = sbitmap_vector_alloc (n_blocks, n_exprs);
4136 hoist_exprs = sbitmap_vector_alloc (n_blocks, n_exprs);
4137 transpout = sbitmap_vector_alloc (n_blocks, n_exprs);
bb457bd9
JL
4138}
4139
4140/* Free vars used for code hoisting analysis. */
4141
4142static void
1d088dee 4143free_code_hoist_mem (void)
bb457bd9 4144{
5a660bff
DB
4145 sbitmap_vector_free (antloc);
4146 sbitmap_vector_free (transp);
4147 sbitmap_vector_free (comp);
bb457bd9 4148
5a660bff
DB
4149 sbitmap_vector_free (hoist_vbein);
4150 sbitmap_vector_free (hoist_vbeout);
4151 sbitmap_vector_free (hoist_exprs);
4152 sbitmap_vector_free (transpout);
bb457bd9 4153
d47cc544 4154 free_dominance_info (CDI_DOMINATORS);
bb457bd9
JL
4155}
4156
4157/* Compute the very busy expressions at entry/exit from each block.
4158
4159 An expression is very busy if all paths from a given point
4160 compute the expression. */
4161
4162static void
1d088dee 4163compute_code_hoist_vbeinout (void)
bb457bd9 4164{
e0082a72
ZD
4165 int changed, passes;
4166 basic_block bb;
bb457bd9 4167
d55bc081
ZD
4168 sbitmap_vector_zero (hoist_vbeout, last_basic_block);
4169 sbitmap_vector_zero (hoist_vbein, last_basic_block);
bb457bd9
JL
4170
4171 passes = 0;
4172 changed = 1;
c4c81601 4173
bb457bd9
JL
4174 while (changed)
4175 {
4176 changed = 0;
c4c81601 4177
bb457bd9
JL
4178 /* We scan the blocks in the reverse order to speed up
4179 the convergence. */
e0082a72 4180 FOR_EACH_BB_REVERSE (bb)
bb457bd9 4181 {
e0082a72 4182 if (bb->next_bb != EXIT_BLOCK_PTR)
f8423fea
SB
4183 sbitmap_intersection_of_succs (hoist_vbeout[bb->index],
4184 hoist_vbein, bb->index);
4185
4186 changed |= sbitmap_a_or_b_and_c_cg (hoist_vbein[bb->index],
4187 antloc[bb->index],
4188 hoist_vbeout[bb->index],
4189 transp[bb->index]);
bb457bd9 4190 }
c4c81601 4191
bb457bd9
JL
4192 passes++;
4193 }
4194
10d22567
ZD
4195 if (dump_file)
4196 fprintf (dump_file, "hoisting vbeinout computation: %d passes\n", passes);
bb457bd9
JL
4197}
4198
4199/* Top level routine to do the dataflow analysis needed by code hoisting. */
4200
4201static void
1d088dee 4202compute_code_hoist_data (void)
bb457bd9 4203{
02280659 4204 compute_local_properties (transp, comp, antloc, &expr_hash_table);
bb457bd9
JL
4205 compute_transpout ();
4206 compute_code_hoist_vbeinout ();
d47cc544 4207 calculate_dominance_info (CDI_DOMINATORS);
10d22567
ZD
4208 if (dump_file)
4209 fprintf (dump_file, "\n");
bb457bd9
JL
4210}
4211
4212/* Determine if the expression identified by EXPR_INDEX would
4213 reach BB unimpared if it was placed at the end of EXPR_BB.
4214
4215 It's unclear exactly what Muchnick meant by "unimpared". It seems
4216 to me that the expression must either be computed or transparent in
4217 *every* block in the path(s) from EXPR_BB to BB. Any other definition
4218 would allow the expression to be hoisted out of loops, even if
4219 the expression wasn't a loop invariant.
4220
4221 Contrast this to reachability for PRE where an expression is
4222 considered reachable if *any* path reaches instead of *all*
4223 paths. */
4224
4225static int
1d088dee 4226hoist_expr_reaches_here_p (basic_block expr_bb, int expr_index, basic_block bb, char *visited)
bb457bd9
JL
4227{
4228 edge pred;
628f6a4e 4229 edge_iterator ei;
283a2545 4230 int visited_allocated_locally = 0;
589005ff 4231
bb457bd9
JL
4232
4233 if (visited == NULL)
4234 {
8e42ace1 4235 visited_allocated_locally = 1;
5ed6ace5 4236 visited = XCNEWVEC (char, last_basic_block);
bb457bd9
JL
4237 }
4238
628f6a4e 4239 FOR_EACH_EDGE (pred, ei, bb->preds)
bb457bd9 4240 {
e2d2ed72 4241 basic_block pred_bb = pred->src;
bb457bd9
JL
4242
4243 if (pred->src == ENTRY_BLOCK_PTR)
4244 break;
f305679f
JH
4245 else if (pred_bb == expr_bb)
4246 continue;
0b17ab2f 4247 else if (visited[pred_bb->index])
bb457bd9 4248 continue;
c4c81601 4249
bb457bd9 4250 /* Does this predecessor generate this expression? */
0b17ab2f 4251 else if (TEST_BIT (comp[pred_bb->index], expr_index))
bb457bd9 4252 break;
0b17ab2f 4253 else if (! TEST_BIT (transp[pred_bb->index], expr_index))
bb457bd9 4254 break;
c4c81601 4255
bb457bd9
JL
4256 /* Not killed. */
4257 else
4258 {
0b17ab2f 4259 visited[pred_bb->index] = 1;
bb457bd9
JL
4260 if (! hoist_expr_reaches_here_p (expr_bb, expr_index,
4261 pred_bb, visited))
4262 break;
4263 }
4264 }
589005ff 4265 if (visited_allocated_locally)
283a2545 4266 free (visited);
c4c81601 4267
bb457bd9
JL
4268 return (pred == NULL);
4269}
4270\f
4271/* Actually perform code hoisting. */
c4c81601 4272
5f39ad47 4273static int
1d088dee 4274hoist_code (void)
bb457bd9 4275{
e0082a72 4276 basic_block bb, dominated;
66f97d31 4277 VEC (basic_block, heap) *domby;
c635a1ec 4278 unsigned int i,j;
bb457bd9 4279 struct expr **index_map;
c4c81601 4280 struct expr *expr;
5f39ad47 4281 int changed = 0;
bb457bd9 4282
d55bc081 4283 sbitmap_vector_zero (hoist_exprs, last_basic_block);
bb457bd9
JL
4284
4285 /* Compute a mapping from expression number (`bitmap_index') to
4286 hash table entry. */
4287
5ed6ace5 4288 index_map = XCNEWVEC (struct expr *, expr_hash_table.n_elems);
02280659
ZD
4289 for (i = 0; i < expr_hash_table.size; i++)
4290 for (expr = expr_hash_table.table[i]; expr != NULL; expr = expr->next_same_hash)
c4c81601 4291 index_map[expr->bitmap_index] = expr;
bb457bd9
JL
4292
4293 /* Walk over each basic block looking for potentially hoistable
4294 expressions, nothing gets hoisted from the entry block. */
e0082a72 4295 FOR_EACH_BB (bb)
bb457bd9
JL
4296 {
4297 int found = 0;
4298 int insn_inserted_p;
4299
66f97d31 4300 domby = get_dominated_by (CDI_DOMINATORS, bb);
bb457bd9
JL
4301 /* Examine each expression that is very busy at the exit of this
4302 block. These are the potentially hoistable expressions. */
e0082a72 4303 for (i = 0; i < hoist_vbeout[bb->index]->n_bits; i++)
bb457bd9
JL
4304 {
4305 int hoistable = 0;
c4c81601 4306
c635a1ec
DB
4307 if (TEST_BIT (hoist_vbeout[bb->index], i)
4308 && TEST_BIT (transpout[bb->index], i))
bb457bd9
JL
4309 {
4310 /* We've found a potentially hoistable expression, now
4311 we look at every block BB dominates to see if it
4312 computes the expression. */
66f97d31 4313 for (j = 0; VEC_iterate (basic_block, domby, j, dominated); j++)
bb457bd9
JL
4314 {
4315 /* Ignore self dominance. */
c635a1ec 4316 if (bb == dominated)
bb457bd9 4317 continue;
bb457bd9
JL
4318 /* We've found a dominated block, now see if it computes
4319 the busy expression and whether or not moving that
4320 expression to the "beginning" of that block is safe. */
e0082a72 4321 if (!TEST_BIT (antloc[dominated->index], i))
bb457bd9
JL
4322 continue;
4323
4324 /* Note if the expression would reach the dominated block
589005ff 4325 unimpared if it was placed at the end of BB.
bb457bd9
JL
4326
4327 Keep track of how many times this expression is hoistable
4328 from a dominated block into BB. */
e0082a72 4329 if (hoist_expr_reaches_here_p (bb, i, dominated, NULL))
bb457bd9
JL
4330 hoistable++;
4331 }
4332
ff7cc307 4333 /* If we found more than one hoistable occurrence of this
bb457bd9
JL
4334 expression, then note it in the bitmap of expressions to
4335 hoist. It makes no sense to hoist things which are computed
4336 in only one BB, and doing so tends to pessimize register
4337 allocation. One could increase this value to try harder
4338 to avoid any possible code expansion due to register
4339 allocation issues; however experiments have shown that
4340 the vast majority of hoistable expressions are only movable
e0bb17a8 4341 from two successors, so raising this threshold is likely
bb457bd9
JL
4342 to nullify any benefit we get from code hoisting. */
4343 if (hoistable > 1)
4344 {
e0082a72 4345 SET_BIT (hoist_exprs[bb->index], i);
bb457bd9
JL
4346 found = 1;
4347 }
4348 }
4349 }
bb457bd9
JL
4350 /* If we found nothing to hoist, then quit now. */
4351 if (! found)
c635a1ec 4352 {
66f97d31
ZD
4353 VEC_free (basic_block, heap, domby);
4354 continue;
c635a1ec 4355 }
bb457bd9
JL
4356
4357 /* Loop over all the hoistable expressions. */
e0082a72 4358 for (i = 0; i < hoist_exprs[bb->index]->n_bits; i++)
bb457bd9
JL
4359 {
4360 /* We want to insert the expression into BB only once, so
4361 note when we've inserted it. */
4362 insn_inserted_p = 0;
4363
4364 /* These tests should be the same as the tests above. */
cb83c2ec 4365 if (TEST_BIT (hoist_exprs[bb->index], i))
bb457bd9
JL
4366 {
4367 /* We've found a potentially hoistable expression, now
4368 we look at every block BB dominates to see if it
4369 computes the expression. */
66f97d31 4370 for (j = 0; VEC_iterate (basic_block, domby, j, dominated); j++)
bb457bd9
JL
4371 {
4372 /* Ignore self dominance. */
c635a1ec 4373 if (bb == dominated)
bb457bd9
JL
4374 continue;
4375
4376 /* We've found a dominated block, now see if it computes
4377 the busy expression and whether or not moving that
4378 expression to the "beginning" of that block is safe. */
e0082a72 4379 if (!TEST_BIT (antloc[dominated->index], i))
bb457bd9
JL
4380 continue;
4381
4382 /* The expression is computed in the dominated block and
4383 it would be safe to compute it at the start of the
4384 dominated block. Now we have to determine if the
ff7cc307 4385 expression would reach the dominated block if it was
bb457bd9 4386 placed at the end of BB. */
e0082a72 4387 if (hoist_expr_reaches_here_p (bb, i, dominated, NULL))
bb457bd9
JL
4388 {
4389 struct expr *expr = index_map[i];
4390 struct occr *occr = expr->antic_occr;
4391 rtx insn;
4392 rtx set;
4393
ff7cc307 4394 /* Find the right occurrence of this expression. */
e0082a72 4395 while (BLOCK_FOR_INSN (occr->insn) != dominated && occr)
bb457bd9
JL
4396 occr = occr->next;
4397
282899df 4398 gcc_assert (occr);
bb457bd9 4399 insn = occr->insn;
bb457bd9 4400 set = single_set (insn);
282899df 4401 gcc_assert (set);
bb457bd9
JL
4402
4403 /* Create a pseudo-reg to store the result of reaching
4404 expressions into. Get the mode for the new pseudo
4405 from the mode of the original destination pseudo. */
4406 if (expr->reaching_reg == NULL)
4407 expr->reaching_reg
46b71b03 4408 = gen_reg_rtx_and_attrs (SET_DEST (set));
bb457bd9 4409
10d1bb36
JH
4410 gcse_emit_move_after (expr->reaching_reg, SET_DEST (set), insn);
4411 delete_insn (insn);
4412 occr->deleted_p = 1;
5f39ad47
SB
4413 changed = 1;
4414 gcse_subst_count++;
4415
10d1bb36 4416 if (!insn_inserted_p)
bb457bd9 4417 {
6fb5fa3c 4418 insert_insn_end_basic_block (index_map[i], bb, 0);
10d1bb36 4419 insn_inserted_p = 1;
bb457bd9
JL
4420 }
4421 }
4422 }
4423 }
4424 }
66f97d31 4425 VEC_free (basic_block, heap, domby);
bb457bd9 4426 }
c4c81601 4427
8e42ace1 4428 free (index_map);
5f39ad47
SB
4429
4430 return changed;
bb457bd9
JL
4431}
4432
4433/* Top level routine to perform one code hoisting (aka unification) pass
4434
cc2902df 4435 Return nonzero if a change was made. */
bb457bd9
JL
4436
4437static int
1d088dee 4438one_code_hoisting_pass (void)
bb457bd9
JL
4439{
4440 int changed = 0;
4441
5f39ad47
SB
4442 gcse_subst_count = 0;
4443 gcse_create_count = 0;
4444
4445 /* Return if there's nothing to do, or it is too expensive. */
4446 if (n_basic_blocks <= NUM_FIXED_BLOCKS + 1
4447 || is_too_expensive (_("GCSE disabled")))
4448 return 0;
4449
4450 /* We need alias. */
4451 init_alias_analysis ();
4452
4453 bytes_used = 0;
4454 gcc_obstack_init (&gcse_obstack);
4455 alloc_gcse_mem ();
4456
b5b8b0ac 4457 alloc_hash_table (&expr_hash_table, 0);
02280659 4458 compute_hash_table (&expr_hash_table);
10d22567
ZD
4459 if (dump_file)
4460 dump_hash_table (dump_file, "Code Hosting Expressions", &expr_hash_table);
c4c81601 4461
02280659 4462 if (expr_hash_table.n_elems > 0)
bb457bd9 4463 {
02280659 4464 alloc_code_hoist_mem (last_basic_block, expr_hash_table.n_elems);
bb457bd9 4465 compute_code_hoist_data ();
5f39ad47 4466 changed = hoist_code ();
bb457bd9
JL
4467 free_code_hoist_mem ();
4468 }
c4c81601 4469
02280659 4470 free_hash_table (&expr_hash_table);
5f39ad47
SB
4471 free_gcse_mem ();
4472 obstack_free (&gcse_obstack, NULL);
4473
4474 /* We are finished with alias. */
4475 end_alias_analysis ();
4476
4477 if (dump_file)
4478 {
4479 fprintf (dump_file, "HOIST of %s, %d basic blocks, %d bytes needed, ",
4480 current_function_name (), n_basic_blocks, bytes_used);
4481 fprintf (dump_file, "%d substs, %d insns created\n",
4482 gcse_subst_count, gcse_create_count);
4483 }
bb457bd9
JL
4484
4485 return changed;
4486}
a13d4ebf
AM
4487\f
4488/* Here we provide the things required to do store motion towards
4489 the exit. In order for this to be effective, gcse also needed to
4490 be taught how to move a load when it is kill only by a store to itself.
4491
4492 int i;
4493 float a[10];
4494
4495 void foo(float scale)
4496 {
4497 for (i=0; i<10; i++)
4498 a[i] *= scale;
4499 }
4500
4501 'i' is both loaded and stored to in the loop. Normally, gcse cannot move
589005ff
KH
4502 the load out since its live around the loop, and stored at the bottom
4503 of the loop.
a13d4ebf 4504
589005ff 4505 The 'Load Motion' referred to and implemented in this file is
a13d4ebf
AM
4506 an enhancement to gcse which when using edge based lcm, recognizes
4507 this situation and allows gcse to move the load out of the loop.
4508
4509 Once gcse has hoisted the load, store motion can then push this
4510 load towards the exit, and we end up with no loads or stores of 'i'
4511 in the loop. */
4512
9727e468
RG
4513static hashval_t
4514pre_ldst_expr_hash (const void *p)
4515{
4516 int do_not_record_p = 0;
1b4572a8 4517 const struct ls_expr *const x = (const struct ls_expr *) p;
9727e468
RG
4518 return hash_rtx (x->pattern, GET_MODE (x->pattern), &do_not_record_p, NULL, false);
4519}
4520
4521static int
4522pre_ldst_expr_eq (const void *p1, const void *p2)
4523{
1b4572a8
KG
4524 const struct ls_expr *const ptr1 = (const struct ls_expr *) p1,
4525 *const ptr2 = (const struct ls_expr *) p2;
9727e468
RG
4526 return expr_equiv_p (ptr1->pattern, ptr2->pattern);
4527}
4528
ff7cc307 4529/* This will search the ldst list for a matching expression. If it
a13d4ebf
AM
4530 doesn't find one, we create one and initialize it. */
4531
4532static struct ls_expr *
1d088dee 4533ldst_entry (rtx x)
a13d4ebf 4534{
b58b21d5 4535 int do_not_record_p = 0;
a13d4ebf 4536 struct ls_expr * ptr;
b58b21d5 4537 unsigned int hash;
9727e468
RG
4538 void **slot;
4539 struct ls_expr e;
a13d4ebf 4540
0516f6fe
SB
4541 hash = hash_rtx (x, GET_MODE (x), &do_not_record_p,
4542 NULL, /*have_reg_qty=*/false);
a13d4ebf 4543
9727e468
RG
4544 e.pattern = x;
4545 slot = htab_find_slot_with_hash (pre_ldst_table, &e, hash, INSERT);
4546 if (*slot)
4547 return (struct ls_expr *)*slot;
b58b21d5 4548
5ed6ace5 4549 ptr = XNEW (struct ls_expr);
b58b21d5
RS
4550
4551 ptr->next = pre_ldst_mems;
4552 ptr->expr = NULL;
4553 ptr->pattern = x;
4554 ptr->pattern_regs = NULL_RTX;
4555 ptr->loads = NULL_RTX;
4556 ptr->stores = NULL_RTX;
4557 ptr->reaching_reg = NULL_RTX;
4558 ptr->invalid = 0;
4559 ptr->index = 0;
4560 ptr->hash_index = hash;
4561 pre_ldst_mems = ptr;
9727e468 4562 *slot = ptr;
589005ff 4563
a13d4ebf
AM
4564 return ptr;
4565}
4566
4567/* Free up an individual ldst entry. */
4568
589005ff 4569static void
1d088dee 4570free_ldst_entry (struct ls_expr * ptr)
a13d4ebf 4571{
aaa4ca30
AJ
4572 free_INSN_LIST_list (& ptr->loads);
4573 free_INSN_LIST_list (& ptr->stores);
a13d4ebf
AM
4574
4575 free (ptr);
4576}
4577
4578/* Free up all memory associated with the ldst list. */
4579
4580static void
1d088dee 4581free_ldst_mems (void)
a13d4ebf 4582{
35b5442a
RG
4583 if (pre_ldst_table)
4584 htab_delete (pre_ldst_table);
9727e468
RG
4585 pre_ldst_table = NULL;
4586
589005ff 4587 while (pre_ldst_mems)
a13d4ebf
AM
4588 {
4589 struct ls_expr * tmp = pre_ldst_mems;
4590
4591 pre_ldst_mems = pre_ldst_mems->next;
4592
4593 free_ldst_entry (tmp);
4594 }
4595
4596 pre_ldst_mems = NULL;
4597}
4598
4599/* Dump debugging info about the ldst list. */
4600
4601static void
1d088dee 4602print_ldst_list (FILE * file)
a13d4ebf
AM
4603{
4604 struct ls_expr * ptr;
4605
4606 fprintf (file, "LDST list: \n");
4607
62e5bf5d 4608 for (ptr = first_ls_expr (); ptr != NULL; ptr = next_ls_expr (ptr))
a13d4ebf
AM
4609 {
4610 fprintf (file, " Pattern (%3d): ", ptr->index);
4611
4612 print_rtl (file, ptr->pattern);
4613
4614 fprintf (file, "\n Loads : ");
4615
4616 if (ptr->loads)
4617 print_rtl (file, ptr->loads);
4618 else
4619 fprintf (file, "(nil)");
4620
4621 fprintf (file, "\n Stores : ");
4622
4623 if (ptr->stores)
4624 print_rtl (file, ptr->stores);
4625 else
4626 fprintf (file, "(nil)");
4627
4628 fprintf (file, "\n\n");
4629 }
4630
4631 fprintf (file, "\n");
4632}
4633
4634/* Returns 1 if X is in the list of ldst only expressions. */
4635
4636static struct ls_expr *
1d088dee 4637find_rtx_in_ldst (rtx x)
a13d4ebf 4638{
9727e468
RG
4639 struct ls_expr e;
4640 void **slot;
6375779a
RG
4641 if (!pre_ldst_table)
4642 return NULL;
9727e468
RG
4643 e.pattern = x;
4644 slot = htab_find_slot (pre_ldst_table, &e, NO_INSERT);
4645 if (!slot || ((struct ls_expr *)*slot)->invalid)
4646 return NULL;
1b4572a8 4647 return (struct ls_expr *) *slot;
a13d4ebf
AM
4648}
4649
a13d4ebf
AM
4650/* Return first item in the list. */
4651
4652static inline struct ls_expr *
1d088dee 4653first_ls_expr (void)
a13d4ebf
AM
4654{
4655 return pre_ldst_mems;
4656}
4657
0e8a66de 4658/* Return the next item in the list after the specified one. */
a13d4ebf
AM
4659
4660static inline struct ls_expr *
1d088dee 4661next_ls_expr (struct ls_expr * ptr)
a13d4ebf
AM
4662{
4663 return ptr->next;
4664}
4665\f
4666/* Load Motion for loads which only kill themselves. */
4667
4668/* Return true if x is a simple MEM operation, with no registers or
4669 side effects. These are the types of loads we consider for the
4670 ld_motion list, otherwise we let the usual aliasing take care of it. */
4671
589005ff 4672static int
ed7a4b4b 4673simple_mem (const_rtx x)
a13d4ebf 4674{
7b1b4aed 4675 if (! MEM_P (x))
a13d4ebf 4676 return 0;
589005ff 4677
a13d4ebf
AM
4678 if (MEM_VOLATILE_P (x))
4679 return 0;
589005ff 4680
a13d4ebf
AM
4681 if (GET_MODE (x) == BLKmode)
4682 return 0;
aaa4ca30 4683
47a3dae1
ZD
4684 /* If we are handling exceptions, we must be careful with memory references
4685 that may trap. If we are not, the behavior is undefined, so we may just
4686 continue. */
4687 if (flag_non_call_exceptions && may_trap_p (x))
98d3d336
RS
4688 return 0;
4689
47a3dae1
ZD
4690 if (side_effects_p (x))
4691 return 0;
589005ff 4692
47a3dae1
ZD
4693 /* Do not consider function arguments passed on stack. */
4694 if (reg_mentioned_p (stack_pointer_rtx, x))
4695 return 0;
4696
4697 if (flag_float_store && FLOAT_MODE_P (GET_MODE (x)))
4698 return 0;
4699
4700 return 1;
a13d4ebf
AM
4701}
4702
589005ff
KH
4703/* Make sure there isn't a buried reference in this pattern anywhere.
4704 If there is, invalidate the entry for it since we're not capable
4705 of fixing it up just yet.. We have to be sure we know about ALL
a13d4ebf
AM
4706 loads since the aliasing code will allow all entries in the
4707 ld_motion list to not-alias itself. If we miss a load, we will get
589005ff 4708 the wrong value since gcse might common it and we won't know to
a13d4ebf
AM
4709 fix it up. */
4710
4711static void
1d088dee 4712invalidate_any_buried_refs (rtx x)
a13d4ebf
AM
4713{
4714 const char * fmt;
8e42ace1 4715 int i, j;
a13d4ebf
AM
4716 struct ls_expr * ptr;
4717
4718 /* Invalidate it in the list. */
7b1b4aed 4719 if (MEM_P (x) && simple_mem (x))
a13d4ebf
AM
4720 {
4721 ptr = ldst_entry (x);
4722 ptr->invalid = 1;
4723 }
4724
4725 /* Recursively process the insn. */
4726 fmt = GET_RTX_FORMAT (GET_CODE (x));
589005ff 4727
a13d4ebf
AM
4728 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
4729 {
4730 if (fmt[i] == 'e')
4731 invalidate_any_buried_refs (XEXP (x, i));
4732 else if (fmt[i] == 'E')
4733 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4734 invalidate_any_buried_refs (XVECEXP (x, i, j));
4735 }
4736}
4737
4d3eb89a
HPN
4738/* Find all the 'simple' MEMs which are used in LOADs and STORES. Simple
4739 being defined as MEM loads and stores to symbols, with no side effects
4740 and no registers in the expression. For a MEM destination, we also
4741 check that the insn is still valid if we replace the destination with a
4742 REG, as is done in update_ld_motion_stores. If there are any uses/defs
4743 which don't match this criteria, they are invalidated and trimmed out
4744 later. */
a13d4ebf 4745
589005ff 4746static void
1d088dee 4747compute_ld_motion_mems (void)
a13d4ebf
AM
4748{
4749 struct ls_expr * ptr;
e0082a72 4750 basic_block bb;
a13d4ebf 4751 rtx insn;
589005ff 4752
a13d4ebf 4753 pre_ldst_mems = NULL;
9727e468
RG
4754 pre_ldst_table = htab_create (13, pre_ldst_expr_hash,
4755 pre_ldst_expr_eq, NULL);
a13d4ebf 4756
e0082a72 4757 FOR_EACH_BB (bb)
a13d4ebf 4758 {
eb232f4e 4759 FOR_BB_INSNS (bb, insn)
a13d4ebf 4760 {
b5b8b0ac 4761 if (NONDEBUG_INSN_P (insn))
a13d4ebf
AM
4762 {
4763 if (GET_CODE (PATTERN (insn)) == SET)
4764 {
4765 rtx src = SET_SRC (PATTERN (insn));
4766 rtx dest = SET_DEST (PATTERN (insn));
4767
4768 /* Check for a simple LOAD... */
7b1b4aed 4769 if (MEM_P (src) && simple_mem (src))
a13d4ebf
AM
4770 {
4771 ptr = ldst_entry (src);
7b1b4aed 4772 if (REG_P (dest))
a13d4ebf
AM
4773 ptr->loads = alloc_INSN_LIST (insn, ptr->loads);
4774 else
4775 ptr->invalid = 1;
4776 }
4777 else
4778 {
4779 /* Make sure there isn't a buried load somewhere. */
4780 invalidate_any_buried_refs (src);
4781 }
589005ff 4782
a13d4ebf
AM
4783 /* Check for stores. Don't worry about aliased ones, they
4784 will block any movement we might do later. We only care
4785 about this exact pattern since those are the only
4786 circumstance that we will ignore the aliasing info. */
7b1b4aed 4787 if (MEM_P (dest) && simple_mem (dest))
a13d4ebf
AM
4788 {
4789 ptr = ldst_entry (dest);
589005ff 4790
7b1b4aed 4791 if (! MEM_P (src)
4d3eb89a
HPN
4792 && GET_CODE (src) != ASM_OPERANDS
4793 /* Check for REG manually since want_to_gcse_p
4794 returns 0 for all REGs. */
df35c271 4795 && can_assign_to_reg_without_clobbers_p (src))
a13d4ebf
AM
4796 ptr->stores = alloc_INSN_LIST (insn, ptr->stores);
4797 else
4798 ptr->invalid = 1;
4799 }
4800 }
4801 else
4802 invalidate_any_buried_refs (PATTERN (insn));
4803 }
4804 }
4805 }
4806}
4807
589005ff 4808/* Remove any references that have been either invalidated or are not in the
a13d4ebf
AM
4809 expression list for pre gcse. */
4810
4811static void
1d088dee 4812trim_ld_motion_mems (void)
a13d4ebf 4813{
b58b21d5
RS
4814 struct ls_expr * * last = & pre_ldst_mems;
4815 struct ls_expr * ptr = pre_ldst_mems;
a13d4ebf
AM
4816
4817 while (ptr != NULL)
4818 {
b58b21d5 4819 struct expr * expr;
589005ff 4820
a13d4ebf 4821 /* Delete if entry has been made invalid. */
b58b21d5 4822 if (! ptr->invalid)
a13d4ebf 4823 {
a13d4ebf 4824 /* Delete if we cannot find this mem in the expression list. */
b58b21d5 4825 unsigned int hash = ptr->hash_index % expr_hash_table.size;
589005ff 4826
b58b21d5
RS
4827 for (expr = expr_hash_table.table[hash];
4828 expr != NULL;
4829 expr = expr->next_same_hash)
4830 if (expr_equiv_p (expr->expr, ptr->pattern))
4831 break;
a13d4ebf
AM
4832 }
4833 else
b58b21d5
RS
4834 expr = (struct expr *) 0;
4835
4836 if (expr)
a13d4ebf
AM
4837 {
4838 /* Set the expression field if we are keeping it. */
a13d4ebf 4839 ptr->expr = expr;
b58b21d5 4840 last = & ptr->next;
a13d4ebf
AM
4841 ptr = ptr->next;
4842 }
b58b21d5
RS
4843 else
4844 {
4845 *last = ptr->next;
9727e468 4846 htab_remove_elt_with_hash (pre_ldst_table, ptr, ptr->hash_index);
b58b21d5
RS
4847 free_ldst_entry (ptr);
4848 ptr = * last;
4849 }
a13d4ebf
AM
4850 }
4851
4852 /* Show the world what we've found. */
10d22567
ZD
4853 if (dump_file && pre_ldst_mems != NULL)
4854 print_ldst_list (dump_file);
a13d4ebf
AM
4855}
4856
4857/* This routine will take an expression which we are replacing with
4858 a reaching register, and update any stores that are needed if
4859 that expression is in the ld_motion list. Stores are updated by
a98ebe2e 4860 copying their SRC to the reaching register, and then storing
a13d4ebf
AM
4861 the reaching register into the store location. These keeps the
4862 correct value in the reaching register for the loads. */
4863
4864static void
1d088dee 4865update_ld_motion_stores (struct expr * expr)
a13d4ebf
AM
4866{
4867 struct ls_expr * mem_ptr;
4868
4869 if ((mem_ptr = find_rtx_in_ldst (expr->expr)))
4870 {
589005ff
KH
4871 /* We can try to find just the REACHED stores, but is shouldn't
4872 matter to set the reaching reg everywhere... some might be
a13d4ebf
AM
4873 dead and should be eliminated later. */
4874
4d3eb89a
HPN
4875 /* We replace (set mem expr) with (set reg expr) (set mem reg)
4876 where reg is the reaching reg used in the load. We checked in
4877 compute_ld_motion_mems that we can replace (set mem expr) with
4878 (set reg expr) in that insn. */
a13d4ebf 4879 rtx list = mem_ptr->stores;
589005ff 4880
a13d4ebf
AM
4881 for ( ; list != NULL_RTX; list = XEXP (list, 1))
4882 {
4883 rtx insn = XEXP (list, 0);
4884 rtx pat = PATTERN (insn);
4885 rtx src = SET_SRC (pat);
4886 rtx reg = expr->reaching_reg;
038dc49a 4887 rtx copy;
a13d4ebf
AM
4888
4889 /* If we've already copied it, continue. */
4890 if (expr->reaching_reg == src)
4891 continue;
589005ff 4892
10d22567 4893 if (dump_file)
a13d4ebf 4894 {
10d22567
ZD
4895 fprintf (dump_file, "PRE: store updated with reaching reg ");
4896 print_rtl (dump_file, expr->reaching_reg);
4897 fprintf (dump_file, ":\n ");
4898 print_inline_rtx (dump_file, insn, 8);
4899 fprintf (dump_file, "\n");
a13d4ebf 4900 }
589005ff 4901
4a81774c 4902 copy = gen_move_insn (reg, copy_rtx (SET_SRC (pat)));
038dc49a 4903 emit_insn_before (copy, insn);
a13d4ebf 4904 SET_SRC (pat) = reg;
6fb5fa3c 4905 df_insn_rescan (insn);
a13d4ebf
AM
4906
4907 /* un-recognize this pattern since it's probably different now. */
4908 INSN_CODE (insn) = -1;
4909 gcse_create_count++;
4910 }
4911 }
4912}
4913\f
df35c271
SB
4914/* Return true if the graph is too expensive to optimize. PASS is the
4915 optimization about to be performed. */
47a3dae1 4916
df35c271
SB
4917static bool
4918is_too_expensive (const char *pass)
4919{
4920 /* Trying to perform global optimizations on flow graphs which have
4921 a high connectivity will take a long time and is unlikely to be
4922 particularly useful.
aaa4ca30 4923
df35c271
SB
4924 In normal circumstances a cfg should have about twice as many
4925 edges as blocks. But we do not want to punish small functions
4926 which have a couple switch statements. Rather than simply
4927 threshold the number of blocks, uses something with a more
4928 graceful degradation. */
4929 if (n_edges > 20000 + n_basic_blocks * 4)
4930 {
4931 warning (OPT_Wdisabled_optimization,
4932 "%s: %d basic blocks and %d edges/basic block",
4933 pass, n_basic_blocks, n_edges / n_basic_blocks);
a13d4ebf 4934
df35c271
SB
4935 return true;
4936 }
a13d4ebf 4937
df35c271
SB
4938 /* If allocating memory for the cprop bitmap would take up too much
4939 storage it's better just to disable the optimization. */
4940 if ((n_basic_blocks
4941 * SBITMAP_SET_SIZE (max_reg_num ())
4942 * sizeof (SBITMAP_ELT_TYPE)) > MAX_GCSE_MEMORY)
4943 {
4944 warning (OPT_Wdisabled_optimization,
4945 "%s: %d basic blocks and %d registers",
4946 pass, n_basic_blocks, max_reg_num ());
a13d4ebf 4947
df35c271
SB
4948 return true;
4949 }
adfcce61 4950
df35c271 4951 return false;
01c43039
RE
4952}
4953
df35c271
SB
4954\f
4955/* Main function for the CPROP pass. */
01c43039 4956
df35c271
SB
4957static int
4958one_cprop_pass (void)
01c43039 4959{
df35c271 4960 int changed = 0;
01c43039 4961
df35c271
SB
4962 /* Return if there's nothing to do, or it is too expensive. */
4963 if (n_basic_blocks <= NUM_FIXED_BLOCKS + 1
4964 || is_too_expensive (_ ("const/copy propagation disabled")))
4965 return 0;
01c43039 4966
df35c271
SB
4967 global_const_prop_count = local_const_prop_count = 0;
4968 global_copy_prop_count = local_copy_prop_count = 0;
a13d4ebf 4969
df35c271
SB
4970 bytes_used = 0;
4971 gcc_obstack_init (&gcse_obstack);
4972 alloc_gcse_mem ();
1d088dee 4973
df35c271
SB
4974 /* Do a local const/copy propagation pass first. The global pass
4975 only handles global opportunities.
4976 If the local pass changes something, remove any unreachable blocks
4977 because the CPROP global dataflow analysis may get into infinite
4978 loops for CFGs with unreachable blocks.
47a3dae1 4979
df35c271
SB
4980 FIXME: This local pass should not be necessary after CSE (but for
4981 some reason it still is). It is also (proven) not necessary
4982 to run the local pass right after FWPWOP.
b8698a0f 4983
df35c271
SB
4984 FIXME: The global analysis would not get into infinite loops if it
4985 would use the DF solver (via df_simple_dataflow) instead of
4986 the solver implemented in this file. */
4987 if (local_cprop_pass ())
47a3dae1 4988 {
df35c271
SB
4989 delete_unreachable_blocks ();
4990 df_analyze ();
47a3dae1 4991 }
a13d4ebf 4992
df35c271
SB
4993 /* Determine implicit sets. */
4994 implicit_sets = XCNEWVEC (rtx, last_basic_block);
4995 find_implicit_sets ();
a13d4ebf 4996
b5b8b0ac 4997 alloc_hash_table (&set_hash_table, 1);
df35c271 4998 compute_hash_table (&set_hash_table);
a13d4ebf 4999
df35c271
SB
5000 /* Free implicit_sets before peak usage. */
5001 free (implicit_sets);
5002 implicit_sets = NULL;
a13d4ebf 5003
df35c271
SB
5004 if (dump_file)
5005 dump_hash_table (dump_file, "SET", &set_hash_table);
5006 if (set_hash_table.n_elems > 0)
a13d4ebf 5007 {
df35c271
SB
5008 basic_block bb;
5009 rtx insn;
a13d4ebf 5010
df35c271
SB
5011 alloc_cprop_mem (last_basic_block, set_hash_table.n_elems);
5012 compute_cprop_data ();
589005ff 5013
df35c271 5014 FOR_BB_BETWEEN (bb, ENTRY_BLOCK_PTR->next_bb->next_bb, EXIT_BLOCK_PTR, next_bb)
a13d4ebf 5015 {
df35c271
SB
5016 /* Reset tables used to keep track of what's still valid [since
5017 the start of the block]. */
5018 reset_opr_set_tables ();
a13d4ebf 5019
df35c271
SB
5020 FOR_BB_INSNS (bb, insn)
5021 if (INSN_P (insn))
5022 {
5023 changed |= cprop_insn (insn);
589005ff 5024
df35c271
SB
5025 /* Keep track of everything modified by this insn. */
5026 /* ??? Need to be careful w.r.t. mods done to INSN.
5027 Don't call mark_oprs_set if we turned the
5028 insn into a NOTE. */
5029 if (! NOTE_P (insn))
5030 mark_oprs_set (insn);
5031 }
a13d4ebf 5032 }
589005ff 5033
df35c271
SB
5034 changed |= bypass_conditional_jumps ();
5035 free_cprop_mem ();
a13d4ebf
AM
5036 }
5037
df35c271
SB
5038 free_hash_table (&set_hash_table);
5039 free_gcse_mem ();
5040 obstack_free (&gcse_obstack, NULL);
a13d4ebf 5041
df35c271
SB
5042 if (dump_file)
5043 {
5044 fprintf (dump_file, "CPROP of %s, %d basic blocks, %d bytes needed, ",
5045 current_function_name (), n_basic_blocks, bytes_used);
5046 fprintf (dump_file, "%d local const props, %d local copy props, ",
5047 local_const_prop_count, local_copy_prop_count);
5048 fprintf (dump_file, "%d global const props, %d global copy props\n\n",
5049 global_const_prop_count, global_copy_prop_count);
5050 }
1d088dee 5051
df35c271
SB
5052 return changed;
5053}
47a3dae1 5054
df35c271
SB
5055\f
5056/* All the passes implemented in this file. Each pass has its
5057 own gate and execute function, and at the end of the file a
5058 pass definition for passes.c.
47a3dae1 5059
df35c271
SB
5060 We do not construct an accurate cfg in functions which call
5061 setjmp, so none of these passes runs if the function calls
5062 setjmp.
5063 FIXME: Should just handle setjmp via REG_SETJMP notes. */
a13d4ebf 5064
df35c271
SB
5065static bool
5066gate_rtl_cprop (void)
a13d4ebf 5067{
df35c271
SB
5068 return optimize > 0 && flag_gcse
5069 && !cfun->calls_setjmp
5070 && dbg_cnt (cprop);
5071}
a13d4ebf 5072
df35c271
SB
5073static unsigned int
5074execute_rtl_cprop (void)
5075{
5076 delete_unreachable_blocks ();
5077 df_note_add_problem ();
5078 df_set_flags (DF_LR_RUN_DCE);
5079 df_analyze ();
5080 flag_rerun_cse_after_global_opts |= one_cprop_pass ();
5081 return 0;
5082}
a13d4ebf 5083
df35c271
SB
5084static bool
5085gate_rtl_pre (void)
5086{
5087 return optimize > 0 && flag_gcse
5088 && !cfun->calls_setjmp
5089 && optimize_function_for_speed_p (cfun)
5090 && dbg_cnt (pre);
5091}
589005ff 5092
df35c271
SB
5093static unsigned int
5094execute_rtl_pre (void)
5095{
5096 delete_unreachable_blocks ();
5097 df_note_add_problem ();
5098 df_analyze ();
5099 flag_rerun_cse_after_global_opts |= one_pre_gcse_pass ();
5100 return 0;
5101}
aaa4ca30 5102
df35c271
SB
5103static bool
5104gate_rtl_hoist (void)
5105{
5106 return optimize > 0 && flag_gcse
5107 && !cfun->calls_setjmp
5108 /* It does not make sense to run code hoisting unless we are optimizing
5109 for code size -- it rarely makes programs faster, and can make then
5110 bigger if we did PRE (when optimizing for space, we don't run PRE). */
5111 && optimize_function_for_size_p (cfun)
5112 && dbg_cnt (hoist);
5113}
aaa4ca30 5114
df35c271
SB
5115static unsigned int
5116execute_rtl_hoist (void)
5117{
5118 delete_unreachable_blocks ();
5119 df_note_add_problem ();
5120 df_analyze ();
5121 flag_rerun_cse_after_global_opts |= one_code_hoisting_pass ();
5122 return 0;
5123}
ef330312 5124
5f39ad47 5125struct rtl_opt_pass pass_rtl_cprop =
ef330312 5126{
8ddbbcae
JH
5127 {
5128 RTL_PASS,
5f39ad47 5129 "cprop", /* name */
b8698a0f
L
5130 gate_rtl_cprop, /* gate */
5131 execute_rtl_cprop, /* execute */
ef330312
PB
5132 NULL, /* sub */
5133 NULL, /* next */
5134 0, /* static_pass_number */
5f39ad47 5135 TV_CPROP, /* tv_id */
9c9e26f5 5136 PROP_cfglayout, /* properties_required */
ef330312
PB
5137 0, /* properties_provided */
5138 0, /* properties_destroyed */
5139 0, /* todo_flags_start */
5f39ad47 5140 TODO_df_finish | TODO_verify_rtl_sharing |
ef330312 5141 TODO_dump_func |
5f39ad47 5142 TODO_verify_flow | TODO_ggc_collect /* todo_flags_finish */
8ddbbcae 5143 }
ef330312
PB
5144};
5145
5f39ad47 5146struct rtl_opt_pass pass_rtl_pre =
ef330312 5147{
5f39ad47
SB
5148 {
5149 RTL_PASS,
e0a42b0f 5150 "rtl pre", /* name */
b8698a0f
L
5151 gate_rtl_pre, /* gate */
5152 execute_rtl_pre, /* execute */
5f39ad47
SB
5153 NULL, /* sub */
5154 NULL, /* next */
5155 0, /* static_pass_number */
5156 TV_PRE, /* tv_id */
5157 PROP_cfglayout, /* properties_required */
5158 0, /* properties_provided */
5159 0, /* properties_destroyed */
5160 0, /* todo_flags_start */
5161 TODO_df_finish | TODO_verify_rtl_sharing |
5162 TODO_dump_func |
5163 TODO_verify_flow | TODO_ggc_collect /* todo_flags_finish */
5164 }
5165};
ef330312 5166
5f39ad47 5167struct rtl_opt_pass pass_rtl_hoist =
ef330312 5168{
8ddbbcae
JH
5169 {
5170 RTL_PASS,
5f39ad47 5171 "hoist", /* name */
b8698a0f
L
5172 gate_rtl_hoist, /* gate */
5173 execute_rtl_hoist, /* execute */
ef330312
PB
5174 NULL, /* sub */
5175 NULL, /* next */
5176 0, /* static_pass_number */
5f39ad47 5177 TV_HOIST, /* tv_id */
9c9e26f5 5178 PROP_cfglayout, /* properties_required */
ef330312
PB
5179 0, /* properties_provided */
5180 0, /* properties_destroyed */
5181 0, /* todo_flags_start */
a36b8a1e 5182 TODO_df_finish | TODO_verify_rtl_sharing |
ef330312 5183 TODO_dump_func |
8ddbbcae
JH
5184 TODO_verify_flow | TODO_ggc_collect /* todo_flags_finish */
5185 }
ef330312
PB
5186};
5187
e2500fed 5188#include "gt-gcse.h"
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