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f4e584dc 1/* Global common subexpression elimination/Partial redundancy elimination
7506f491 2 and global constant/copy propagation for GNU compiler.
d9221e01 3 Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004
8e42ace1 4 Free Software Foundation, Inc.
7506f491 5
1322177d 6This file is part of GCC.
7506f491 7
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8GCC is free software; you can redistribute it and/or modify it under
9the terms of the GNU General Public License as published by the Free
10Software Foundation; either version 2, or (at your option) any later
11version.
7506f491 12
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13GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14WARRANTY; without even the implied warranty of MERCHANTABILITY or
15FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16for more details.
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17
18You should have received a copy of the GNU General Public License
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19along with GCC; see the file COPYING. If not, write to the Free
20Software Foundation, 59 Temple Place - Suite 330, Boston, MA
2102111-1307, USA. */
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22
23/* TODO
24 - reordering of memory allocation and freeing to be more space efficient
25 - do rough calc of how many regs are needed in each block, and a rough
26 calc of how many regs are available in each class and use that to
27 throttle back the code in cases where RTX_COST is minimal.
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28 - a store to the same address as a load does not kill the load if the
29 source of the store is also the destination of the load. Handling this
30 allows more load motion, particularly out of loops.
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31 - ability to realloc sbitmap vectors would allow one initial computation
32 of reg_set_in_block with only subsequent additions, rather than
33 recomputing it for each pass
34
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35*/
36
37/* References searched while implementing this.
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38
39 Compilers Principles, Techniques and Tools
40 Aho, Sethi, Ullman
41 Addison-Wesley, 1988
42
43 Global Optimization by Suppression of Partial Redundancies
44 E. Morel, C. Renvoise
45 communications of the acm, Vol. 22, Num. 2, Feb. 1979
46
47 A Portable Machine-Independent Global Optimizer - Design and Measurements
48 Frederick Chow
49 Stanford Ph.D. thesis, Dec. 1983
50
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51 A Fast Algorithm for Code Movement Optimization
52 D.M. Dhamdhere
53 SIGPLAN Notices, Vol. 23, Num. 10, Oct. 1988
54
55 A Solution to a Problem with Morel and Renvoise's
56 Global Optimization by Suppression of Partial Redundancies
57 K-H Drechsler, M.P. Stadel
58 ACM TOPLAS, Vol. 10, Num. 4, Oct. 1988
59
60 Practical Adaptation of the Global Optimization
61 Algorithm of Morel and Renvoise
62 D.M. Dhamdhere
63 ACM TOPLAS, Vol. 13, Num. 2. Apr. 1991
64
65 Efficiently Computing Static Single Assignment Form and the Control
66 Dependence Graph
67 R. Cytron, J. Ferrante, B.K. Rosen, M.N. Wegman, and F.K. Zadeck
68 ACM TOPLAS, Vol. 13, Num. 4, Oct. 1991
69
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70 Lazy Code Motion
71 J. Knoop, O. Ruthing, B. Steffen
72 ACM SIGPLAN Notices Vol. 27, Num. 7, Jul. 1992, '92 Conference on PLDI
73
74 What's In a Region? Or Computing Control Dependence Regions in Near-Linear
75 Time for Reducible Flow Control
76 Thomas Ball
77 ACM Letters on Programming Languages and Systems,
78 Vol. 2, Num. 1-4, Mar-Dec 1993
79
80 An Efficient Representation for Sparse Sets
81 Preston Briggs, Linda Torczon
82 ACM Letters on Programming Languages and Systems,
83 Vol. 2, Num. 1-4, Mar-Dec 1993
84
85 A Variation of Knoop, Ruthing, and Steffen's Lazy Code Motion
86 K-H Drechsler, M.P. Stadel
87 ACM SIGPLAN Notices, Vol. 28, Num. 5, May 1993
88
89 Partial Dead Code Elimination
90 J. Knoop, O. Ruthing, B. Steffen
91 ACM SIGPLAN Notices, Vol. 29, Num. 6, Jun. 1994
92
93 Effective Partial Redundancy Elimination
94 P. Briggs, K.D. Cooper
95 ACM SIGPLAN Notices, Vol. 29, Num. 6, Jun. 1994
96
97 The Program Structure Tree: Computing Control Regions in Linear Time
98 R. Johnson, D. Pearson, K. Pingali
99 ACM SIGPLAN Notices, Vol. 29, Num. 6, Jun. 1994
100
101 Optimal Code Motion: Theory and Practice
102 J. Knoop, O. Ruthing, B. Steffen
103 ACM TOPLAS, Vol. 16, Num. 4, Jul. 1994
104
105 The power of assignment motion
106 J. Knoop, O. Ruthing, B. Steffen
107 ACM SIGPLAN Notices Vol. 30, Num. 6, Jun. 1995, '95 Conference on PLDI
108
109 Global code motion / global value numbering
110 C. Click
111 ACM SIGPLAN Notices Vol. 30, Num. 6, Jun. 1995, '95 Conference on PLDI
112
113 Value Driven Redundancy Elimination
114 L.T. Simpson
115 Rice University Ph.D. thesis, Apr. 1996
116
117 Value Numbering
118 L.T. Simpson
119 Massively Scalar Compiler Project, Rice University, Sep. 1996
120
121 High Performance Compilers for Parallel Computing
122 Michael Wolfe
123 Addison-Wesley, 1996
124
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125 Advanced Compiler Design and Implementation
126 Steven Muchnick
127 Morgan Kaufmann, 1997
128
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129 Building an Optimizing Compiler
130 Robert Morgan
131 Digital Press, 1998
132
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133 People wishing to speed up the code here should read:
134 Elimination Algorithms for Data Flow Analysis
135 B.G. Ryder, M.C. Paull
136 ACM Computing Surveys, Vol. 18, Num. 3, Sep. 1986
137
138 How to Analyze Large Programs Efficiently and Informatively
139 D.M. Dhamdhere, B.K. Rosen, F.K. Zadeck
140 ACM SIGPLAN Notices Vol. 27, Num. 7, Jul. 1992, '92 Conference on PLDI
141
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142 People wishing to do something different can find various possibilities
143 in the above papers and elsewhere.
144*/
145
146#include "config.h"
50b2596f 147#include "system.h"
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148#include "coretypes.h"
149#include "tm.h"
01198c2f 150#include "toplev.h"
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151
152#include "rtl.h"
b0656d8b 153#include "tree.h"
6baf1cc8 154#include "tm_p.h"
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155#include "regs.h"
156#include "hard-reg-set.h"
157#include "flags.h"
158#include "real.h"
159#include "insn-config.h"
160#include "recog.h"
161#include "basic-block.h"
50b2596f 162#include "output.h"
49ad7cfa 163#include "function.h"
589005ff 164#include "expr.h"
e7d482b9 165#include "except.h"
fb0c0a12 166#include "ggc.h"
f1fa37ff 167#include "params.h"
ae860ff7 168#include "cselib.h"
d128effb 169#include "intl.h"
7506f491 170#include "obstack.h"
27fb79ad 171#include "timevar.h"
4fa31c2a 172
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173/* Propagate flow information through back edges and thus enable PRE's
174 moving loop invariant calculations out of loops.
175
176 Originally this tended to create worse overall code, but several
177 improvements during the development of PRE seem to have made following
178 back edges generally a win.
179
180 Note much of the loop invariant code motion done here would normally
181 be done by loop.c, which has more heuristics for when to move invariants
182 out of loops. At some point we might need to move some of those
183 heuristics into gcse.c. */
7506f491 184
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185/* We support GCSE via Partial Redundancy Elimination. PRE optimizations
186 are a superset of those done by GCSE.
7506f491 187
f4e584dc 188 We perform the following steps:
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189
190 1) Compute basic block information.
191
192 2) Compute table of places where registers are set.
193
194 3) Perform copy/constant propagation.
195
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196 4) Perform global cse using lazy code motion if not optimizing
197 for size, or code hoisting if we are.
7506f491 198
e78d9500 199 5) Perform another pass of copy/constant propagation.
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200
201 Two passes of copy/constant propagation are done because the first one
202 enables more GCSE and the second one helps to clean up the copies that
203 GCSE creates. This is needed more for PRE than for Classic because Classic
204 GCSE will try to use an existing register containing the common
205 subexpression rather than create a new one. This is harder to do for PRE
206 because of the code motion (which Classic GCSE doesn't do).
207
208 Expressions we are interested in GCSE-ing are of the form
209 (set (pseudo-reg) (expression)).
210 Function want_to_gcse_p says what these are.
211
212 PRE handles moving invariant expressions out of loops (by treating them as
f4e584dc 213 partially redundant).
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214
215 Eventually it would be nice to replace cse.c/gcse.c with SSA (static single
216 assignment) based GVN (global value numbering). L. T. Simpson's paper
217 (Rice University) on value numbering is a useful reference for this.
218
219 **********************
220
221 We used to support multiple passes but there are diminishing returns in
222 doing so. The first pass usually makes 90% of the changes that are doable.
223 A second pass can make a few more changes made possible by the first pass.
224 Experiments show any further passes don't make enough changes to justify
225 the expense.
226
227 A study of spec92 using an unlimited number of passes:
228 [1 pass] = 1208 substitutions, [2] = 577, [3] = 202, [4] = 192, [5] = 83,
229 [6] = 34, [7] = 17, [8] = 9, [9] = 4, [10] = 4, [11] = 2,
230 [12] = 2, [13] = 1, [15] = 1, [16] = 2, [41] = 1
231
232 It was found doing copy propagation between each pass enables further
233 substitutions.
234
235 PRE is quite expensive in complicated functions because the DFA can take
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236 a while to converge. Hence we only perform one pass. The parameter
237 max-gcse-passes can be modified if one wants to experiment.
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238
239 **********************
240
241 The steps for PRE are:
242
243 1) Build the hash table of expressions we wish to GCSE (expr_hash_table).
244
245 2) Perform the data flow analysis for PRE.
246
247 3) Delete the redundant instructions
248
249 4) Insert the required copies [if any] that make the partially
250 redundant instructions fully redundant.
251
252 5) For other reaching expressions, insert an instruction to copy the value
253 to a newly created pseudo that will reach the redundant instruction.
254
255 The deletion is done first so that when we do insertions we
256 know which pseudo reg to use.
257
258 Various papers have argued that PRE DFA is expensive (O(n^2)) and others
259 argue it is not. The number of iterations for the algorithm to converge
260 is typically 2-4 so I don't view it as that expensive (relatively speaking).
261
f4e584dc 262 PRE GCSE depends heavily on the second CSE pass to clean up the copies
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263 we create. To make an expression reach the place where it's redundant,
264 the result of the expression is copied to a new register, and the redundant
265 expression is deleted by replacing it with this new register. Classic GCSE
266 doesn't have this problem as much as it computes the reaching defs of
267 each register in each block and thus can try to use an existing register.
268
269 **********************
270
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271 A fair bit of simplicity is created by creating small functions for simple
272 tasks, even when the function is only called in one place. This may
273 measurably slow things down [or may not] by creating more function call
274 overhead than is necessary. The source is laid out so that it's trivial
275 to make the affected functions inline so that one can measure what speed
276 up, if any, can be achieved, and maybe later when things settle things can
277 be rearranged.
278
279 Help stamp out big monolithic functions! */
280\f
281/* GCSE global vars. */
282
283/* -dG dump file. */
284static FILE *gcse_file;
285
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286/* Note whether or not we should run jump optimization after gcse. We
287 want to do this for two cases.
288
289 * If we changed any jumps via cprop.
290
291 * If we added any labels via edge splitting. */
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292static int run_jump_opt_after_gcse;
293
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294/* Bitmaps are normally not included in debugging dumps.
295 However it's useful to be able to print them from GDB.
296 We could create special functions for this, but it's simpler to
297 just allow passing stderr to the dump_foo fns. Since stderr can
298 be a macro, we store a copy here. */
299static FILE *debug_stderr;
300
301/* An obstack for our working variables. */
302static struct obstack gcse_obstack;
303
c4c81601 304struct reg_use {rtx reg_rtx; };
abd535b6 305
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306/* Hash table of expressions. */
307
308struct expr
309{
310 /* The expression (SET_SRC for expressions, PATTERN for assignments). */
311 rtx expr;
312 /* Index in the available expression bitmaps. */
313 int bitmap_index;
314 /* Next entry with the same hash. */
315 struct expr *next_same_hash;
316 /* List of anticipatable occurrences in basic blocks in the function.
317 An "anticipatable occurrence" is one that is the first occurrence in the
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318 basic block, the operands are not modified in the basic block prior
319 to the occurrence and the output is not used between the start of
320 the block and the occurrence. */
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321 struct occr *antic_occr;
322 /* List of available occurrence in basic blocks in the function.
323 An "available occurrence" is one that is the last occurrence in the
324 basic block and the operands are not modified by following statements in
325 the basic block [including this insn]. */
326 struct occr *avail_occr;
327 /* Non-null if the computation is PRE redundant.
328 The value is the newly created pseudo-reg to record a copy of the
329 expression in all the places that reach the redundant copy. */
330 rtx reaching_reg;
331};
332
333/* Occurrence of an expression.
334 There is one per basic block. If a pattern appears more than once the
335 last appearance is used [or first for anticipatable expressions]. */
336
337struct occr
338{
339 /* Next occurrence of this expression. */
340 struct occr *next;
341 /* The insn that computes the expression. */
342 rtx insn;
cc2902df 343 /* Nonzero if this [anticipatable] occurrence has been deleted. */
7506f491 344 char deleted_p;
cc2902df 345 /* Nonzero if this [available] occurrence has been copied to
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346 reaching_reg. */
347 /* ??? This is mutually exclusive with deleted_p, so they could share
348 the same byte. */
349 char copied_p;
350};
351
352/* Expression and copy propagation hash tables.
353 Each hash table is an array of buckets.
354 ??? It is known that if it were an array of entries, structure elements
355 `next_same_hash' and `bitmap_index' wouldn't be necessary. However, it is
356 not clear whether in the final analysis a sufficient amount of memory would
357 be saved as the size of the available expression bitmaps would be larger
358 [one could build a mapping table without holes afterwards though].
c4c81601 359 Someday I'll perform the computation and figure it out. */
7506f491 360
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361struct hash_table
362{
363 /* The table itself.
364 This is an array of `expr_hash_table_size' elements. */
365 struct expr **table;
366
367 /* Size of the hash table, in elements. */
368 unsigned int size;
2e653e39 369
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370 /* Number of hash table elements. */
371 unsigned int n_elems;
7506f491 372
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373 /* Whether the table is expression of copy propagation one. */
374 int set_p;
375};
c4c81601 376
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377/* Expression hash table. */
378static struct hash_table expr_hash_table;
379
380/* Copy propagation hash table. */
381static struct hash_table set_hash_table;
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382
383/* Mapping of uids to cuids.
384 Only real insns get cuids. */
385static int *uid_cuid;
386
387/* Highest UID in UID_CUID. */
388static int max_uid;
389
390/* Get the cuid of an insn. */
b86db3eb 391#ifdef ENABLE_CHECKING
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392#define INSN_CUID(INSN) \
393 (gcc_assert (INSN_UID (INSN) <= max_uid), uid_cuid[INSN_UID (INSN)])
b86db3eb 394#else
7506f491 395#define INSN_CUID(INSN) (uid_cuid[INSN_UID (INSN)])
b86db3eb 396#endif
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397
398/* Number of cuids. */
399static int max_cuid;
400
401/* Mapping of cuids to insns. */
402static rtx *cuid_insn;
403
404/* Get insn from cuid. */
405#define CUID_INSN(CUID) (cuid_insn[CUID])
406
407/* Maximum register number in function prior to doing gcse + 1.
408 Registers created during this pass have regno >= max_gcse_regno.
409 This is named with "gcse" to not collide with global of same name. */
770ae6cc 410static unsigned int max_gcse_regno;
7506f491 411
7506f491 412/* Table of registers that are modified.
c4c81601 413
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414 For each register, each element is a list of places where the pseudo-reg
415 is set.
416
417 For simplicity, GCSE is done on sets of pseudo-regs only. PRE GCSE only
418 requires knowledge of which blocks kill which regs [and thus could use
f4e584dc 419 a bitmap instead of the lists `reg_set_table' uses].
7506f491 420
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421 `reg_set_table' and could be turned into an array of bitmaps (num-bbs x
422 num-regs) [however perhaps it may be useful to keep the data as is]. One
423 advantage of recording things this way is that `reg_set_table' is fairly
424 sparse with respect to pseudo regs but for hard regs could be fairly dense
425 [relatively speaking]. And recording sets of pseudo-regs in lists speeds
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426 up functions like compute_transp since in the case of pseudo-regs we only
427 need to iterate over the number of times a pseudo-reg is set, not over the
428 number of basic blocks [clearly there is a bit of a slow down in the cases
429 where a pseudo is set more than once in a block, however it is believed
430 that the net effect is to speed things up]. This isn't done for hard-regs
431 because recording call-clobbered hard-regs in `reg_set_table' at each
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432 function call can consume a fair bit of memory, and iterating over
433 hard-regs stored this way in compute_transp will be more expensive. */
7506f491 434
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435typedef struct reg_set
436{
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437 /* The next setting of this register. */
438 struct reg_set *next;
439 /* The insn where it was set. */
440 rtx insn;
441} reg_set;
c4c81601 442
7506f491 443static reg_set **reg_set_table;
c4c81601 444
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445/* Size of `reg_set_table'.
446 The table starts out at max_gcse_regno + slop, and is enlarged as
447 necessary. */
448static int reg_set_table_size;
c4c81601 449
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450/* Amount to grow `reg_set_table' by when it's full. */
451#define REG_SET_TABLE_SLOP 100
452
a13d4ebf 453/* This is a list of expressions which are MEMs and will be used by load
589005ff 454 or store motion.
a13d4ebf 455 Load motion tracks MEMs which aren't killed by
454ff5cb 456 anything except itself. (i.e., loads and stores to a single location).
589005ff 457 We can then allow movement of these MEM refs with a little special
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458 allowance. (all stores copy the same value to the reaching reg used
459 for the loads). This means all values used to store into memory must have
589005ff 460 no side effects so we can re-issue the setter value.
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461 Store Motion uses this structure as an expression table to track stores
462 which look interesting, and might be moveable towards the exit block. */
463
464struct ls_expr
465{
466 struct expr * expr; /* Gcse expression reference for LM. */
467 rtx pattern; /* Pattern of this mem. */
47a3dae1 468 rtx pattern_regs; /* List of registers mentioned by the mem. */
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469 rtx loads; /* INSN list of loads seen. */
470 rtx stores; /* INSN list of stores seen. */
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471 struct ls_expr * next; /* Next in the list. */
472 int invalid; /* Invalid for some reason. */
473 int index; /* If it maps to a bitmap index. */
b58b21d5 474 unsigned int hash_index; /* Index when in a hash table. */
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475 rtx reaching_reg; /* Register to use when re-writing. */
476};
477
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478/* Array of implicit set patterns indexed by basic block index. */
479static rtx *implicit_sets;
480
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481/* Head of the list of load/store memory refs. */
482static struct ls_expr * pre_ldst_mems = NULL;
483
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484/* Bitmap containing one bit for each register in the program.
485 Used when performing GCSE to track which registers have been set since
486 the start of the basic block. */
73991d6a 487static regset reg_set_bitmap;
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488
489/* For each block, a bitmap of registers set in the block.
e83f4801 490 This is used by compute_transp.
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491 It is computed during hash table computation and not by compute_sets
492 as it includes registers added since the last pass (or between cprop and
493 gcse) and it's currently not easy to realloc sbitmap vectors. */
494static sbitmap *reg_set_in_block;
495
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496/* Array, indexed by basic block number for a list of insns which modify
497 memory within that block. */
498static rtx * modify_mem_list;
0516f6fe 499static bitmap modify_mem_list_set;
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500
501/* This array parallels modify_mem_list, but is kept canonicalized. */
502static rtx * canon_modify_mem_list;
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503static bitmap canon_modify_mem_list_set;
504
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505/* Various variables for statistics gathering. */
506
507/* Memory used in a pass.
508 This isn't intended to be absolutely precise. Its intent is only
509 to keep an eye on memory usage. */
510static int bytes_used;
c4c81601 511
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512/* GCSE substitutions made. */
513static int gcse_subst_count;
514/* Number of copy instructions created. */
515static int gcse_create_count;
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516/* Number of local constants propagated. */
517static int local_const_prop_count;
518/* Number of local copys propagated. */
519static int local_copy_prop_count;
520/* Number of global constants propagated. */
521static int global_const_prop_count;
522/* Number of global copys propagated. */
523static int global_copy_prop_count;
7506f491 524\f
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525/* For available exprs */
526static sbitmap *ae_kill, *ae_gen;
b5ce41ff 527
0511851c
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528/* Objects of this type are passed around by the null-pointer check
529 removal routines. */
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530struct null_pointer_info
531{
0511851c 532 /* The basic block being processed. */
e0082a72 533 basic_block current_block;
0511851c 534 /* The first register to be handled in this pass. */
770ae6cc 535 unsigned int min_reg;
0511851c 536 /* One greater than the last register to be handled in this pass. */
770ae6cc 537 unsigned int max_reg;
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538 sbitmap *nonnull_local;
539 sbitmap *nonnull_killed;
540};
7506f491 541\f
1d088dee 542static void compute_can_copy (void);
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543static void *gmalloc (size_t) ATTRIBUTE_MALLOC;
544static void *gcalloc (size_t, size_t) ATTRIBUTE_MALLOC;
545static void *grealloc (void *, size_t);
703ad42b 546static void *gcse_alloc (unsigned long);
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547static void alloc_gcse_mem (rtx);
548static void free_gcse_mem (void);
549static void alloc_reg_set_mem (int);
550static void free_reg_set_mem (void);
1d088dee 551static void record_one_set (int, rtx);
b885908b 552static void replace_one_set (int, rtx, rtx);
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553static void record_set_info (rtx, rtx, void *);
554static void compute_sets (rtx);
555static void hash_scan_insn (rtx, struct hash_table *, int);
556static void hash_scan_set (rtx, rtx, struct hash_table *);
557static void hash_scan_clobber (rtx, rtx, struct hash_table *);
558static void hash_scan_call (rtx, rtx, struct hash_table *);
559static int want_to_gcse_p (rtx);
1707bafa 560static bool can_assign_to_reg_p (rtx);
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561static bool gcse_constant_p (rtx);
562static int oprs_unchanged_p (rtx, rtx, int);
563static int oprs_anticipatable_p (rtx, rtx);
564static int oprs_available_p (rtx, rtx);
565static void insert_expr_in_table (rtx, enum machine_mode, rtx, int, int,
566 struct hash_table *);
567static void insert_set_in_table (rtx, rtx, struct hash_table *);
568static unsigned int hash_expr (rtx, enum machine_mode, int *, int);
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569static unsigned int hash_set (int, int);
570static int expr_equiv_p (rtx, rtx);
571static void record_last_reg_set_info (rtx, int);
572static void record_last_mem_set_info (rtx);
573static void record_last_set_info (rtx, rtx, void *);
574static void compute_hash_table (struct hash_table *);
575static void alloc_hash_table (int, struct hash_table *, int);
576static void free_hash_table (struct hash_table *);
577static void compute_hash_table_work (struct hash_table *);
578static void dump_hash_table (FILE *, const char *, struct hash_table *);
1d088dee
AJ
579static struct expr *lookup_set (unsigned int, struct hash_table *);
580static struct expr *next_set (unsigned int, struct expr *);
581static void reset_opr_set_tables (void);
582static int oprs_not_set_p (rtx, rtx);
583static void mark_call (rtx);
584static void mark_set (rtx, rtx);
585static void mark_clobber (rtx, rtx);
586static void mark_oprs_set (rtx);
587static void alloc_cprop_mem (int, int);
588static void free_cprop_mem (void);
589static void compute_transp (rtx, int, sbitmap *, int);
590static void compute_transpout (void);
591static void compute_local_properties (sbitmap *, sbitmap *, sbitmap *,
592 struct hash_table *);
593static void compute_cprop_data (void);
594static void find_used_regs (rtx *, void *);
595static int try_replace_reg (rtx, rtx, rtx);
596static struct expr *find_avail_set (int, rtx);
597static int cprop_jump (basic_block, rtx, rtx, rtx, rtx);
598static void mems_conflict_for_gcse_p (rtx, rtx, void *);
599static int load_killed_in_block_p (basic_block, int, rtx, int);
600static void canon_list_insert (rtx, rtx, void *);
601static int cprop_insn (rtx, int);
602static int cprop (int);
603static void find_implicit_sets (void);
604static int one_cprop_pass (int, int, int);
605static bool constprop_register (rtx, rtx, rtx, int);
606static struct expr *find_bypass_set (int, int);
607static bool reg_killed_on_edge (rtx, edge);
608static int bypass_block (basic_block, rtx, rtx);
609static int bypass_conditional_jumps (void);
610static void alloc_pre_mem (int, int);
611static void free_pre_mem (void);
612static void compute_pre_data (void);
613static int pre_expr_reaches_here_p (basic_block, struct expr *,
614 basic_block);
615static void insert_insn_end_bb (struct expr *, basic_block, int);
616static void pre_insert_copy_insn (struct expr *, rtx);
617static void pre_insert_copies (void);
618static int pre_delete (void);
619static int pre_gcse (void);
620static int one_pre_gcse_pass (int);
621static void add_label_notes (rtx, rtx);
622static void alloc_code_hoist_mem (int, int);
623static void free_code_hoist_mem (void);
624static void compute_code_hoist_vbeinout (void);
625static void compute_code_hoist_data (void);
626static int hoist_expr_reaches_here_p (basic_block, int, basic_block, char *);
627static void hoist_code (void);
628static int one_code_hoisting_pass (void);
1d088dee
AJ
629static rtx process_insert_insn (struct expr *);
630static int pre_edge_insert (struct edge_list *, struct expr **);
1d088dee
AJ
631static int pre_expr_reaches_here_p_work (basic_block, struct expr *,
632 basic_block, char *);
633static struct ls_expr * ldst_entry (rtx);
634static void free_ldst_entry (struct ls_expr *);
635static void free_ldst_mems (void);
636static void print_ldst_list (FILE *);
637static struct ls_expr * find_rtx_in_ldst (rtx);
638static int enumerate_ldsts (void);
639static inline struct ls_expr * first_ls_expr (void);
640static inline struct ls_expr * next_ls_expr (struct ls_expr *);
641static int simple_mem (rtx);
642static void invalidate_any_buried_refs (rtx);
643static void compute_ld_motion_mems (void);
644static void trim_ld_motion_mems (void);
645static void update_ld_motion_stores (struct expr *);
646static void reg_set_info (rtx, rtx, void *);
01c43039 647static void reg_clear_last_set (rtx, rtx, void *);
1d088dee
AJ
648static bool store_ops_ok (rtx, int *);
649static rtx extract_mentioned_regs (rtx);
650static rtx extract_mentioned_regs_helper (rtx, rtx);
651static void find_moveable_store (rtx, int *, int *);
652static int compute_store_table (void);
3b14e3af
ZD
653static bool load_kills_store (rtx, rtx, int);
654static bool find_loads (rtx, rtx, int);
655static bool store_killed_in_insn (rtx, rtx, rtx, int);
1d088dee
AJ
656static bool store_killed_after (rtx, rtx, rtx, basic_block, int *, rtx *);
657static bool store_killed_before (rtx, rtx, rtx, basic_block, int *);
658static void build_store_vectors (void);
659static void insert_insn_start_bb (rtx, basic_block);
660static int insert_store (struct ls_expr *, edge);
d088acea
ZD
661static void remove_reachable_equiv_notes (basic_block, struct ls_expr *);
662static void replace_store_insn (rtx, rtx, basic_block, struct ls_expr *);
1d088dee
AJ
663static void delete_store (struct ls_expr *, basic_block);
664static void free_store_memory (void);
665static void store_motion (void);
666static void free_insn_expr_list_list (rtx *);
667static void clear_modify_mem_tables (void);
668static void free_modify_mem_tables (void);
669static rtx gcse_emit_move_after (rtx, rtx, rtx);
670static void local_cprop_find_used_regs (rtx *, void *);
671static bool do_local_cprop (rtx, rtx, int, rtx*);
672static bool adjust_libcall_notes (rtx, rtx, rtx, rtx*);
673static void local_cprop_pass (int);
d128effb 674static bool is_too_expensive (const char *);
7506f491 675\f
d128effb 676
7506f491
DE
677/* Entry point for global common subexpression elimination.
678 F is the first instruction in the function. */
679
e78d9500 680int
1d088dee 681gcse_main (rtx f, FILE *file)
7506f491
DE
682{
683 int changed, pass;
684 /* Bytes used at start of pass. */
685 int initial_bytes_used;
686 /* Maximum number of bytes used by a pass. */
687 int max_pass_bytes;
688 /* Point to release obstack data from for each pass. */
689 char *gcse_obstack_bottom;
690
b5ce41ff
JL
691 /* We do not construct an accurate cfg in functions which call
692 setjmp, so just punt to be safe. */
7506f491 693 if (current_function_calls_setjmp)
e78d9500 694 return 0;
589005ff 695
b5ce41ff
JL
696 /* Assume that we do not need to run jump optimizations after gcse. */
697 run_jump_opt_after_gcse = 0;
698
7506f491
DE
699 /* For calling dump_foo fns from gdb. */
700 debug_stderr = stderr;
b5ce41ff 701 gcse_file = file;
7506f491 702
b5ce41ff
JL
703 /* Identify the basic block information for this function, including
704 successors and predecessors. */
7506f491 705 max_gcse_regno = max_reg_num ();
7506f491 706
a42cd965
AM
707 if (file)
708 dump_flow_info (file);
709
d128effb
NS
710 /* Return if there's nothing to do, or it is too expensive. */
711 if (n_basic_blocks <= 1 || is_too_expensive (_("GCSE disabled")))
a18820c6 712 return 0;
7b1b4aed 713
7506f491 714 gcc_obstack_init (&gcse_obstack);
a42cd965 715 bytes_used = 0;
7506f491 716
a13d4ebf
AM
717 /* We need alias. */
718 init_alias_analysis ();
c4c81601
RK
719 /* Record where pseudo-registers are set. This data is kept accurate
720 during each pass. ??? We could also record hard-reg information here
721 [since it's unchanging], however it is currently done during hash table
722 computation.
b5ce41ff 723
c4c81601
RK
724 It may be tempting to compute MEM set information here too, but MEM sets
725 will be subject to code motion one day and thus we need to compute
b5ce41ff 726 information about memory sets when we build the hash tables. */
7506f491
DE
727
728 alloc_reg_set_mem (max_gcse_regno);
729 compute_sets (f);
730
731 pass = 0;
732 initial_bytes_used = bytes_used;
733 max_pass_bytes = 0;
734 gcse_obstack_bottom = gcse_alloc (1);
735 changed = 1;
740f35a0 736 while (changed && pass < MAX_GCSE_PASSES)
7506f491
DE
737 {
738 changed = 0;
739 if (file)
740 fprintf (file, "GCSE pass %d\n\n", pass + 1);
741
742 /* Initialize bytes_used to the space for the pred/succ lists,
743 and the reg_set_table data. */
744 bytes_used = initial_bytes_used;
745
746 /* Each pass may create new registers, so recalculate each time. */
747 max_gcse_regno = max_reg_num ();
748
749 alloc_gcse_mem (f);
750
b5ce41ff
JL
751 /* Don't allow constant propagation to modify jumps
752 during this pass. */
27fb79ad 753 timevar_push (TV_CPROP1);
a0134312 754 changed = one_cprop_pass (pass + 1, 0, 0);
27fb79ad 755 timevar_pop (TV_CPROP1);
7506f491
DE
756
757 if (optimize_size)
e83f4801 758 /* Do nothing. */ ;
7506f491 759 else
589005ff 760 {
27fb79ad 761 timevar_push (TV_PRE);
a42cd965 762 changed |= one_pre_gcse_pass (pass + 1);
a13d4ebf
AM
763 /* We may have just created new basic blocks. Release and
764 recompute various things which are sized on the number of
765 basic blocks. */
766 if (changed)
767 {
73991d6a 768 free_modify_mem_tables ();
9fe15a12
KG
769 modify_mem_list = gcalloc (last_basic_block, sizeof (rtx));
770 canon_modify_mem_list = gcalloc (last_basic_block, sizeof (rtx));
a13d4ebf 771 }
a42cd965
AM
772 free_reg_set_mem ();
773 alloc_reg_set_mem (max_reg_num ());
774 compute_sets (f);
775 run_jump_opt_after_gcse = 1;
27fb79ad 776 timevar_pop (TV_PRE);
a42cd965 777 }
7506f491
DE
778
779 if (max_pass_bytes < bytes_used)
780 max_pass_bytes = bytes_used;
781
bb457bd9
JL
782 /* Free up memory, then reallocate for code hoisting. We can
783 not re-use the existing allocated memory because the tables
784 will not have info for the insns or registers created by
785 partial redundancy elimination. */
7506f491
DE
786 free_gcse_mem ();
787
5d3cc252 788 /* It does not make sense to run code hoisting unless we are optimizing
bb457bd9
JL
789 for code size -- it rarely makes programs faster, and can make
790 them bigger if we did partial redundancy elimination (when optimizing
e83f4801 791 for space, we don't run the partial redundancy algorithms). */
bb457bd9 792 if (optimize_size)
589005ff 793 {
27fb79ad 794 timevar_push (TV_HOIST);
bb457bd9
JL
795 max_gcse_regno = max_reg_num ();
796 alloc_gcse_mem (f);
797 changed |= one_code_hoisting_pass ();
798 free_gcse_mem ();
799
800 if (max_pass_bytes < bytes_used)
801 max_pass_bytes = bytes_used;
27fb79ad 802 timevar_pop (TV_HOIST);
589005ff 803 }
bb457bd9 804
7506f491
DE
805 if (file)
806 {
807 fprintf (file, "\n");
808 fflush (file);
809 }
c4c81601 810
7506f491
DE
811 obstack_free (&gcse_obstack, gcse_obstack_bottom);
812 pass++;
813 }
814
b5ce41ff
JL
815 /* Do one last pass of copy propagation, including cprop into
816 conditional jumps. */
817
818 max_gcse_regno = max_reg_num ();
819 alloc_gcse_mem (f);
820 /* This time, go ahead and allow cprop to alter jumps. */
27fb79ad 821 timevar_push (TV_CPROP2);
a0134312 822 one_cprop_pass (pass + 1, 1, 0);
27fb79ad 823 timevar_pop (TV_CPROP2);
b5ce41ff 824 free_gcse_mem ();
7506f491
DE
825
826 if (file)
827 {
828 fprintf (file, "GCSE of %s: %d basic blocks, ",
faed5cc3 829 current_function_name (), n_basic_blocks);
7506f491
DE
830 fprintf (file, "%d pass%s, %d bytes\n\n",
831 pass, pass > 1 ? "es" : "", max_pass_bytes);
832 }
833
6496a589 834 obstack_free (&gcse_obstack, NULL);
7506f491 835 free_reg_set_mem ();
7b1b4aed 836
a13d4ebf
AM
837 /* We are finished with alias. */
838 end_alias_analysis ();
839 allocate_reg_info (max_reg_num (), FALSE, FALSE);
840
47a3dae1 841 if (!optimize_size && flag_gcse_sm)
27fb79ad
SB
842 {
843 timevar_push (TV_LSM);
844 store_motion ();
845 timevar_pop (TV_LSM);
846 }
47a3dae1 847
a13d4ebf 848 /* Record where pseudo-registers are set. */
e78d9500 849 return run_jump_opt_after_gcse;
7506f491
DE
850}
851\f
852/* Misc. utilities. */
853
773eae39
EB
854/* Nonzero for each mode that supports (set (reg) (reg)).
855 This is trivially true for integer and floating point values.
856 It may or may not be true for condition codes. */
857static char can_copy[(int) NUM_MACHINE_MODES];
858
7506f491
DE
859/* Compute which modes support reg/reg copy operations. */
860
861static void
1d088dee 862compute_can_copy (void)
7506f491
DE
863{
864 int i;
50b2596f 865#ifndef AVOID_CCMODE_COPIES
8e42ace1 866 rtx reg, insn;
50b2596f 867#endif
773eae39 868 memset (can_copy, 0, NUM_MACHINE_MODES);
7506f491
DE
869
870 start_sequence ();
871 for (i = 0; i < NUM_MACHINE_MODES; i++)
c4c81601
RK
872 if (GET_MODE_CLASS (i) == MODE_CC)
873 {
7506f491 874#ifdef AVOID_CCMODE_COPIES
773eae39 875 can_copy[i] = 0;
7506f491 876#else
c4c81601
RK
877 reg = gen_rtx_REG ((enum machine_mode) i, LAST_VIRTUAL_REGISTER + 1);
878 insn = emit_insn (gen_rtx_SET (VOIDmode, reg, reg));
9714cf43 879 if (recog (PATTERN (insn), insn, NULL) >= 0)
773eae39 880 can_copy[i] = 1;
7506f491 881#endif
c4c81601 882 }
141b5810 883 else
773eae39 884 can_copy[i] = 1;
c4c81601 885
7506f491 886 end_sequence ();
7506f491 887}
773eae39
EB
888
889/* Returns whether the mode supports reg/reg copy operations. */
890
891bool
1d088dee 892can_copy_p (enum machine_mode mode)
773eae39
EB
893{
894 static bool can_copy_init_p = false;
895
896 if (! can_copy_init_p)
897 {
898 compute_can_copy ();
899 can_copy_init_p = true;
900 }
901
902 return can_copy[mode] != 0;
903}
7506f491
DE
904\f
905/* Cover function to xmalloc to record bytes allocated. */
906
703ad42b 907static void *
4ac11022 908gmalloc (size_t size)
7506f491
DE
909{
910 bytes_used += size;
911 return xmalloc (size);
912}
913
9fe15a12
KG
914/* Cover function to xcalloc to record bytes allocated. */
915
916static void *
917gcalloc (size_t nelem, size_t elsize)
918{
919 bytes_used += nelem * elsize;
920 return xcalloc (nelem, elsize);
921}
922
7506f491
DE
923/* Cover function to xrealloc.
924 We don't record the additional size since we don't know it.
925 It won't affect memory usage stats much anyway. */
926
703ad42b 927static void *
9fe15a12 928grealloc (void *ptr, size_t size)
7506f491
DE
929{
930 return xrealloc (ptr, size);
931}
932
77bbd421 933/* Cover function to obstack_alloc. */
7506f491 934
703ad42b 935static void *
1d088dee 936gcse_alloc (unsigned long size)
7506f491 937{
77bbd421 938 bytes_used += size;
703ad42b 939 return obstack_alloc (&gcse_obstack, size);
7506f491
DE
940}
941
942/* Allocate memory for the cuid mapping array,
943 and reg/memory set tracking tables.
944
945 This is called at the start of each pass. */
946
947static void
1d088dee 948alloc_gcse_mem (rtx f)
7506f491 949{
9fe15a12 950 int i;
7506f491
DE
951 rtx insn;
952
953 /* Find the largest UID and create a mapping from UIDs to CUIDs.
954 CUIDs are like UIDs except they increase monotonically, have no gaps,
955 and only apply to real insns. */
956
957 max_uid = get_max_uid ();
9fe15a12 958 uid_cuid = gcalloc (max_uid + 1, sizeof (int));
7506f491
DE
959 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
960 {
2c3c49de 961 if (INSN_P (insn))
b86db3eb 962 uid_cuid[INSN_UID (insn)] = i++;
7506f491 963 else
b86db3eb 964 uid_cuid[INSN_UID (insn)] = i;
7506f491
DE
965 }
966
967 /* Create a table mapping cuids to insns. */
968
969 max_cuid = i;
9fe15a12 970 cuid_insn = gcalloc (max_cuid + 1, sizeof (rtx));
7506f491 971 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
2c3c49de 972 if (INSN_P (insn))
c4c81601 973 CUID_INSN (i++) = insn;
7506f491
DE
974
975 /* Allocate vars to track sets of regs. */
73991d6a 976 reg_set_bitmap = BITMAP_XMALLOC ();
7506f491
DE
977
978 /* Allocate vars to track sets of regs, memory per block. */
703ad42b 979 reg_set_in_block = sbitmap_vector_alloc (last_basic_block, max_gcse_regno);
a13d4ebf
AM
980 /* Allocate array to keep a list of insns which modify memory in each
981 basic block. */
9fe15a12
KG
982 modify_mem_list = gcalloc (last_basic_block, sizeof (rtx));
983 canon_modify_mem_list = gcalloc (last_basic_block, sizeof (rtx));
73991d6a
JH
984 modify_mem_list_set = BITMAP_XMALLOC ();
985 canon_modify_mem_list_set = BITMAP_XMALLOC ();
7506f491
DE
986}
987
988/* Free memory allocated by alloc_gcse_mem. */
989
990static void
1d088dee 991free_gcse_mem (void)
7506f491
DE
992{
993 free (uid_cuid);
994 free (cuid_insn);
995
73991d6a 996 BITMAP_XFREE (reg_set_bitmap);
7506f491 997
5a660bff 998 sbitmap_vector_free (reg_set_in_block);
73991d6a
JH
999 free_modify_mem_tables ();
1000 BITMAP_XFREE (modify_mem_list_set);
1001 BITMAP_XFREE (canon_modify_mem_list_set);
7506f491 1002}
b5ce41ff
JL
1003\f
1004/* Compute the local properties of each recorded expression.
c4c81601
RK
1005
1006 Local properties are those that are defined by the block, irrespective of
1007 other blocks.
b5ce41ff
JL
1008
1009 An expression is transparent in a block if its operands are not modified
1010 in the block.
1011
1012 An expression is computed (locally available) in a block if it is computed
1013 at least once and expression would contain the same value if the
1014 computation was moved to the end of the block.
1015
1016 An expression is locally anticipatable in a block if it is computed at
1017 least once and expression would contain the same value if the computation
1018 was moved to the beginning of the block.
1019
c4c81601
RK
1020 We call this routine for cprop, pre and code hoisting. They all compute
1021 basically the same information and thus can easily share this code.
7506f491 1022
c4c81601
RK
1023 TRANSP, COMP, and ANTLOC are destination sbitmaps for recording local
1024 properties. If NULL, then it is not necessary to compute or record that
1025 particular property.
b5ce41ff 1026
02280659
ZD
1027 TABLE controls which hash table to look at. If it is set hash table,
1028 additionally, TRANSP is computed as ~TRANSP, since this is really cprop's
c4c81601 1029 ABSALTERED. */
589005ff 1030
b5ce41ff 1031static void
7b1b4aed
SB
1032compute_local_properties (sbitmap *transp, sbitmap *comp, sbitmap *antloc,
1033 struct hash_table *table)
b5ce41ff 1034{
02280659 1035 unsigned int i;
589005ff 1036
b5ce41ff
JL
1037 /* Initialize any bitmaps that were passed in. */
1038 if (transp)
695ab36a 1039 {
02280659 1040 if (table->set_p)
d55bc081 1041 sbitmap_vector_zero (transp, last_basic_block);
695ab36a 1042 else
d55bc081 1043 sbitmap_vector_ones (transp, last_basic_block);
695ab36a 1044 }
c4c81601 1045
b5ce41ff 1046 if (comp)
d55bc081 1047 sbitmap_vector_zero (comp, last_basic_block);
b5ce41ff 1048 if (antloc)
d55bc081 1049 sbitmap_vector_zero (antloc, last_basic_block);
b5ce41ff 1050
02280659 1051 for (i = 0; i < table->size; i++)
7506f491 1052 {
b5ce41ff
JL
1053 struct expr *expr;
1054
02280659 1055 for (expr = table->table[i]; expr != NULL; expr = expr->next_same_hash)
b5ce41ff 1056 {
b5ce41ff 1057 int indx = expr->bitmap_index;
c4c81601 1058 struct occr *occr;
b5ce41ff
JL
1059
1060 /* The expression is transparent in this block if it is not killed.
1061 We start by assuming all are transparent [none are killed], and
1062 then reset the bits for those that are. */
b5ce41ff 1063 if (transp)
02280659 1064 compute_transp (expr->expr, indx, transp, table->set_p);
b5ce41ff
JL
1065
1066 /* The occurrences recorded in antic_occr are exactly those that
cc2902df 1067 we want to set to nonzero in ANTLOC. */
b5ce41ff 1068 if (antloc)
c4c81601
RK
1069 for (occr = expr->antic_occr; occr != NULL; occr = occr->next)
1070 {
1071 SET_BIT (antloc[BLOCK_NUM (occr->insn)], indx);
b5ce41ff 1072
c4c81601
RK
1073 /* While we're scanning the table, this is a good place to
1074 initialize this. */
1075 occr->deleted_p = 0;
1076 }
b5ce41ff
JL
1077
1078 /* The occurrences recorded in avail_occr are exactly those that
cc2902df 1079 we want to set to nonzero in COMP. */
b5ce41ff 1080 if (comp)
c4c81601
RK
1081 for (occr = expr->avail_occr; occr != NULL; occr = occr->next)
1082 {
1083 SET_BIT (comp[BLOCK_NUM (occr->insn)], indx);
b5ce41ff 1084
c4c81601
RK
1085 /* While we're scanning the table, this is a good place to
1086 initialize this. */
1087 occr->copied_p = 0;
1088 }
b5ce41ff
JL
1089
1090 /* While we're scanning the table, this is a good place to
1091 initialize this. */
1092 expr->reaching_reg = 0;
1093 }
7506f491 1094 }
7506f491
DE
1095}
1096\f
1097/* Register set information.
1098
1099 `reg_set_table' records where each register is set or otherwise
1100 modified. */
1101
1102static struct obstack reg_set_obstack;
1103
1104static void
1d088dee 1105alloc_reg_set_mem (int n_regs)
7506f491 1106{
7506f491 1107 reg_set_table_size = n_regs + REG_SET_TABLE_SLOP;
9fe15a12 1108 reg_set_table = gcalloc (reg_set_table_size, sizeof (struct reg_set *));
7506f491
DE
1109
1110 gcc_obstack_init (&reg_set_obstack);
1111}
1112
1113static void
1d088dee 1114free_reg_set_mem (void)
7506f491
DE
1115{
1116 free (reg_set_table);
6496a589 1117 obstack_free (&reg_set_obstack, NULL);
7506f491
DE
1118}
1119
b885908b
MH
1120/* An OLD_INSN that used to set REGNO was replaced by NEW_INSN.
1121 Update the corresponding `reg_set_table' entry accordingly.
1122 We assume that NEW_INSN is not already recorded in reg_set_table[regno]. */
1123
1124static void
1125replace_one_set (int regno, rtx old_insn, rtx new_insn)
1126{
1127 struct reg_set *reg_info;
1128 if (regno >= reg_set_table_size)
1129 return;
1130 for (reg_info = reg_set_table[regno]; reg_info; reg_info = reg_info->next)
1131 if (reg_info->insn == old_insn)
1132 {
1133 reg_info->insn = new_insn;
1134 break;
1135 }
1136}
1137
7506f491
DE
1138/* Record REGNO in the reg_set table. */
1139
1140static void
1d088dee 1141record_one_set (int regno, rtx insn)
7506f491 1142{
172890a2 1143 /* Allocate a new reg_set element and link it onto the list. */
63bc1d05 1144 struct reg_set *new_reg_info;
7506f491
DE
1145
1146 /* If the table isn't big enough, enlarge it. */
1147 if (regno >= reg_set_table_size)
1148 {
1149 int new_size = regno + REG_SET_TABLE_SLOP;
c4c81601 1150
703ad42b
KG
1151 reg_set_table = grealloc (reg_set_table,
1152 new_size * sizeof (struct reg_set *));
1153 memset (reg_set_table + reg_set_table_size, 0,
8e42ace1 1154 (new_size - reg_set_table_size) * sizeof (struct reg_set *));
7506f491
DE
1155 reg_set_table_size = new_size;
1156 }
1157
703ad42b 1158 new_reg_info = obstack_alloc (&reg_set_obstack, sizeof (struct reg_set));
7506f491
DE
1159 bytes_used += sizeof (struct reg_set);
1160 new_reg_info->insn = insn;
274969ea
MM
1161 new_reg_info->next = reg_set_table[regno];
1162 reg_set_table[regno] = new_reg_info;
7506f491
DE
1163}
1164
c4c81601
RK
1165/* Called from compute_sets via note_stores to handle one SET or CLOBBER in
1166 an insn. The DATA is really the instruction in which the SET is
1167 occurring. */
7506f491
DE
1168
1169static void
1d088dee 1170record_set_info (rtx dest, rtx setter ATTRIBUTE_UNUSED, void *data)
7506f491 1171{
84832317
MM
1172 rtx record_set_insn = (rtx) data;
1173
7b1b4aed 1174 if (REG_P (dest) && REGNO (dest) >= FIRST_PSEUDO_REGISTER)
c4c81601 1175 record_one_set (REGNO (dest), record_set_insn);
7506f491
DE
1176}
1177
1178/* Scan the function and record each set of each pseudo-register.
1179
c4c81601 1180 This is called once, at the start of the gcse pass. See the comments for
fbe5a4a6 1181 `reg_set_table' for further documentation. */
7506f491
DE
1182
1183static void
1d088dee 1184compute_sets (rtx f)
7506f491 1185{
c4c81601 1186 rtx insn;
7506f491 1187
c4c81601 1188 for (insn = f; insn != 0; insn = NEXT_INSN (insn))
2c3c49de 1189 if (INSN_P (insn))
c4c81601 1190 note_stores (PATTERN (insn), record_set_info, insn);
7506f491
DE
1191}
1192\f
1193/* Hash table support. */
1194
80c29cc4
RZ
1195struct reg_avail_info
1196{
e0082a72 1197 basic_block last_bb;
80c29cc4
RZ
1198 int first_set;
1199 int last_set;
1200};
1201
1202static struct reg_avail_info *reg_avail_info;
e0082a72 1203static basic_block current_bb;
7506f491 1204
7506f491 1205
fb0c0a12
RK
1206/* See whether X, the source of a set, is something we want to consider for
1207 GCSE. */
7506f491
DE
1208
1209static int
1d088dee 1210want_to_gcse_p (rtx x)
7506f491 1211{
c4c81601 1212 switch (GET_CODE (x))
7506f491
DE
1213 {
1214 case REG:
1215 case SUBREG:
1216 case CONST_INT:
1217 case CONST_DOUBLE:
69ef87e2 1218 case CONST_VECTOR:
7506f491
DE
1219 case CALL:
1220 return 0;
1221
1222 default:
1707bafa 1223 return can_assign_to_reg_p (x);
7506f491 1224 }
1707bafa
RS
1225}
1226
1227/* Used internally by can_assign_to_reg_p. */
1228
1229static GTY(()) rtx test_insn;
1230
1231/* Return true if we can assign X to a pseudo register. */
1232
1233static bool
1234can_assign_to_reg_p (rtx x)
1235{
1236 int num_clobbers = 0;
1237 int icode;
7506f491 1238
fb0c0a12
RK
1239 /* If this is a valid operand, we are OK. If it's VOIDmode, we aren't. */
1240 if (general_operand (x, GET_MODE (x)))
1241 return 1;
1242 else if (GET_MODE (x) == VOIDmode)
1243 return 0;
1244
1245 /* Otherwise, check if we can make a valid insn from it. First initialize
1246 our test insn if we haven't already. */
1247 if (test_insn == 0)
1248 {
1249 test_insn
1250 = make_insn_raw (gen_rtx_SET (VOIDmode,
1251 gen_rtx_REG (word_mode,
1252 FIRST_PSEUDO_REGISTER * 2),
1253 const0_rtx));
1254 NEXT_INSN (test_insn) = PREV_INSN (test_insn) = 0;
fb0c0a12
RK
1255 }
1256
1257 /* Now make an insn like the one we would make when GCSE'ing and see if
1258 valid. */
1259 PUT_MODE (SET_DEST (PATTERN (test_insn)), GET_MODE (x));
1260 SET_SRC (PATTERN (test_insn)) = x;
1261 return ((icode = recog (PATTERN (test_insn), test_insn, &num_clobbers)) >= 0
1262 && (num_clobbers == 0 || ! added_clobbers_hard_reg_p (icode)));
7506f491
DE
1263}
1264
cc2902df 1265/* Return nonzero if the operands of expression X are unchanged from the
7506f491
DE
1266 start of INSN's basic block up to but not including INSN (if AVAIL_P == 0),
1267 or from INSN to the end of INSN's basic block (if AVAIL_P != 0). */
1268
1269static int
1d088dee 1270oprs_unchanged_p (rtx x, rtx insn, int avail_p)
7506f491 1271{
c4c81601 1272 int i, j;
7506f491 1273 enum rtx_code code;
6f7d635c 1274 const char *fmt;
7506f491 1275
7506f491
DE
1276 if (x == 0)
1277 return 1;
1278
1279 code = GET_CODE (x);
1280 switch (code)
1281 {
1282 case REG:
80c29cc4
RZ
1283 {
1284 struct reg_avail_info *info = &reg_avail_info[REGNO (x)];
1285
1286 if (info->last_bb != current_bb)
1287 return 1;
589005ff 1288 if (avail_p)
80c29cc4
RZ
1289 return info->last_set < INSN_CUID (insn);
1290 else
1291 return info->first_set >= INSN_CUID (insn);
1292 }
7506f491
DE
1293
1294 case MEM:
e0082a72 1295 if (load_killed_in_block_p (current_bb, INSN_CUID (insn),
a13d4ebf
AM
1296 x, avail_p))
1297 return 0;
7506f491 1298 else
c4c81601 1299 return oprs_unchanged_p (XEXP (x, 0), insn, avail_p);
7506f491
DE
1300
1301 case PRE_DEC:
1302 case PRE_INC:
1303 case POST_DEC:
1304 case POST_INC:
4b983fdc
RH
1305 case PRE_MODIFY:
1306 case POST_MODIFY:
7506f491
DE
1307 return 0;
1308
1309 case PC:
1310 case CC0: /*FIXME*/
1311 case CONST:
1312 case CONST_INT:
1313 case CONST_DOUBLE:
69ef87e2 1314 case CONST_VECTOR:
7506f491
DE
1315 case SYMBOL_REF:
1316 case LABEL_REF:
1317 case ADDR_VEC:
1318 case ADDR_DIFF_VEC:
1319 return 1;
1320
1321 default:
1322 break;
1323 }
1324
c4c81601 1325 for (i = GET_RTX_LENGTH (code) - 1, fmt = GET_RTX_FORMAT (code); i >= 0; i--)
7506f491
DE
1326 {
1327 if (fmt[i] == 'e')
1328 {
c4c81601
RK
1329 /* If we are about to do the last recursive call needed at this
1330 level, change it into iteration. This function is called enough
1331 to be worth it. */
7506f491 1332 if (i == 0)
c4c81601
RK
1333 return oprs_unchanged_p (XEXP (x, i), insn, avail_p);
1334
1335 else if (! oprs_unchanged_p (XEXP (x, i), insn, avail_p))
7506f491
DE
1336 return 0;
1337 }
1338 else if (fmt[i] == 'E')
c4c81601
RK
1339 for (j = 0; j < XVECLEN (x, i); j++)
1340 if (! oprs_unchanged_p (XVECEXP (x, i, j), insn, avail_p))
1341 return 0;
7506f491
DE
1342 }
1343
1344 return 1;
1345}
1346
a13d4ebf
AM
1347/* Used for communication between mems_conflict_for_gcse_p and
1348 load_killed_in_block_p. Nonzero if mems_conflict_for_gcse_p finds a
1349 conflict between two memory references. */
1350static int gcse_mems_conflict_p;
1351
1352/* Used for communication between mems_conflict_for_gcse_p and
1353 load_killed_in_block_p. A memory reference for a load instruction,
1354 mems_conflict_for_gcse_p will see if a memory store conflicts with
1355 this memory load. */
1356static rtx gcse_mem_operand;
1357
1358/* DEST is the output of an instruction. If it is a memory reference, and
1359 possibly conflicts with the load found in gcse_mem_operand, then set
1360 gcse_mems_conflict_p to a nonzero value. */
1361
1362static void
1d088dee
AJ
1363mems_conflict_for_gcse_p (rtx dest, rtx setter ATTRIBUTE_UNUSED,
1364 void *data ATTRIBUTE_UNUSED)
a13d4ebf
AM
1365{
1366 while (GET_CODE (dest) == SUBREG
1367 || GET_CODE (dest) == ZERO_EXTRACT
1368 || GET_CODE (dest) == SIGN_EXTRACT
1369 || GET_CODE (dest) == STRICT_LOW_PART)
1370 dest = XEXP (dest, 0);
1371
1372 /* If DEST is not a MEM, then it will not conflict with the load. Note
1373 that function calls are assumed to clobber memory, but are handled
1374 elsewhere. */
7b1b4aed 1375 if (! MEM_P (dest))
a13d4ebf 1376 return;
aaa4ca30 1377
a13d4ebf 1378 /* If we are setting a MEM in our list of specially recognized MEMs,
589005ff
KH
1379 don't mark as killed this time. */
1380
47a3dae1 1381 if (expr_equiv_p (dest, gcse_mem_operand) && pre_ldst_mems != NULL)
a13d4ebf
AM
1382 {
1383 if (!find_rtx_in_ldst (dest))
1384 gcse_mems_conflict_p = 1;
1385 return;
1386 }
aaa4ca30 1387
a13d4ebf
AM
1388 if (true_dependence (dest, GET_MODE (dest), gcse_mem_operand,
1389 rtx_addr_varies_p))
1390 gcse_mems_conflict_p = 1;
1391}
1392
1393/* Return nonzero if the expression in X (a memory reference) is killed
1394 in block BB before or after the insn with the CUID in UID_LIMIT.
1395 AVAIL_P is nonzero for kills after UID_LIMIT, and zero for kills
1396 before UID_LIMIT.
1397
1398 To check the entire block, set UID_LIMIT to max_uid + 1 and
1399 AVAIL_P to 0. */
1400
1401static int
1d088dee 1402load_killed_in_block_p (basic_block bb, int uid_limit, rtx x, int avail_p)
a13d4ebf 1403{
0b17ab2f 1404 rtx list_entry = modify_mem_list[bb->index];
a13d4ebf
AM
1405 while (list_entry)
1406 {
1407 rtx setter;
1408 /* Ignore entries in the list that do not apply. */
1409 if ((avail_p
1410 && INSN_CUID (XEXP (list_entry, 0)) < uid_limit)
1411 || (! avail_p
1412 && INSN_CUID (XEXP (list_entry, 0)) > uid_limit))
1413 {
1414 list_entry = XEXP (list_entry, 1);
1415 continue;
1416 }
1417
1418 setter = XEXP (list_entry, 0);
1419
1420 /* If SETTER is a call everything is clobbered. Note that calls
1421 to pure functions are never put on the list, so we need not
1422 worry about them. */
7b1b4aed 1423 if (CALL_P (setter))
a13d4ebf
AM
1424 return 1;
1425
1426 /* SETTER must be an INSN of some kind that sets memory. Call
589005ff 1427 note_stores to examine each hunk of memory that is modified.
a13d4ebf
AM
1428
1429 The note_stores interface is pretty limited, so we have to
1430 communicate via global variables. Yuk. */
1431 gcse_mem_operand = x;
1432 gcse_mems_conflict_p = 0;
1433 note_stores (PATTERN (setter), mems_conflict_for_gcse_p, NULL);
1434 if (gcse_mems_conflict_p)
1435 return 1;
1436 list_entry = XEXP (list_entry, 1);
1437 }
1438 return 0;
1439}
1440
cc2902df 1441/* Return nonzero if the operands of expression X are unchanged from
7506f491
DE
1442 the start of INSN's basic block up to but not including INSN. */
1443
1444static int
1d088dee 1445oprs_anticipatable_p (rtx x, rtx insn)
7506f491
DE
1446{
1447 return oprs_unchanged_p (x, insn, 0);
1448}
1449
cc2902df 1450/* Return nonzero if the operands of expression X are unchanged from
7506f491
DE
1451 INSN to the end of INSN's basic block. */
1452
1453static int
1d088dee 1454oprs_available_p (rtx x, rtx insn)
7506f491
DE
1455{
1456 return oprs_unchanged_p (x, insn, 1);
1457}
1458
1459/* Hash expression X.
c4c81601
RK
1460
1461 MODE is only used if X is a CONST_INT. DO_NOT_RECORD_P is a boolean
1462 indicating if a volatile operand is found or if the expression contains
b58b21d5 1463 something we don't want to insert in the table. HASH_TABLE_SIZE is
0516f6fe 1464 the current size of the hash table to be probed. */
7506f491
DE
1465
1466static unsigned int
b58b21d5
RS
1467hash_expr (rtx x, enum machine_mode mode, int *do_not_record_p,
1468 int hash_table_size)
7506f491
DE
1469{
1470 unsigned int hash;
1471
1472 *do_not_record_p = 0;
1473
0516f6fe
SB
1474 hash = hash_rtx (x, mode, do_not_record_p,
1475 NULL, /*have_reg_qty=*/false);
7506f491
DE
1476 return hash % hash_table_size;
1477}
172890a2 1478
7506f491
DE
1479/* Hash a set of register REGNO.
1480
c4c81601
RK
1481 Sets are hashed on the register that is set. This simplifies the PRE copy
1482 propagation code.
7506f491
DE
1483
1484 ??? May need to make things more elaborate. Later, as necessary. */
1485
1486static unsigned int
1d088dee 1487hash_set (int regno, int hash_table_size)
7506f491
DE
1488{
1489 unsigned int hash;
1490
1491 hash = regno;
1492 return hash % hash_table_size;
1493}
1494
0516f6fe 1495/* Return nonzero if exp1 is equivalent to exp2. */
7506f491
DE
1496
1497static int
1d088dee 1498expr_equiv_p (rtx x, rtx y)
7506f491 1499{
0516f6fe 1500 return exp_equiv_p (x, y, 0, true);
7506f491
DE
1501}
1502
02280659 1503/* Insert expression X in INSN in the hash TABLE.
7506f491
DE
1504 If it is already present, record it as the last occurrence in INSN's
1505 basic block.
1506
1507 MODE is the mode of the value X is being stored into.
1508 It is only used if X is a CONST_INT.
1509
cc2902df
KH
1510 ANTIC_P is nonzero if X is an anticipatable expression.
1511 AVAIL_P is nonzero if X is an available expression. */
7506f491
DE
1512
1513static void
1d088dee
AJ
1514insert_expr_in_table (rtx x, enum machine_mode mode, rtx insn, int antic_p,
1515 int avail_p, struct hash_table *table)
7506f491
DE
1516{
1517 int found, do_not_record_p;
1518 unsigned int hash;
1519 struct expr *cur_expr, *last_expr = NULL;
1520 struct occr *antic_occr, *avail_occr;
1521 struct occr *last_occr = NULL;
1522
02280659 1523 hash = hash_expr (x, mode, &do_not_record_p, table->size);
7506f491
DE
1524
1525 /* Do not insert expression in table if it contains volatile operands,
1526 or if hash_expr determines the expression is something we don't want
1527 to or can't handle. */
1528 if (do_not_record_p)
1529 return;
1530
02280659 1531 cur_expr = table->table[hash];
7506f491
DE
1532 found = 0;
1533
c4c81601 1534 while (cur_expr && 0 == (found = expr_equiv_p (cur_expr->expr, x)))
7506f491
DE
1535 {
1536 /* If the expression isn't found, save a pointer to the end of
1537 the list. */
1538 last_expr = cur_expr;
1539 cur_expr = cur_expr->next_same_hash;
1540 }
1541
1542 if (! found)
1543 {
703ad42b 1544 cur_expr = gcse_alloc (sizeof (struct expr));
7506f491 1545 bytes_used += sizeof (struct expr);
02280659 1546 if (table->table[hash] == NULL)
c4c81601 1547 /* This is the first pattern that hashed to this index. */
02280659 1548 table->table[hash] = cur_expr;
7506f491 1549 else
c4c81601
RK
1550 /* Add EXPR to end of this hash chain. */
1551 last_expr->next_same_hash = cur_expr;
1552
589005ff 1553 /* Set the fields of the expr element. */
7506f491 1554 cur_expr->expr = x;
02280659 1555 cur_expr->bitmap_index = table->n_elems++;
7506f491
DE
1556 cur_expr->next_same_hash = NULL;
1557 cur_expr->antic_occr = NULL;
1558 cur_expr->avail_occr = NULL;
1559 }
1560
1561 /* Now record the occurrence(s). */
7506f491
DE
1562 if (antic_p)
1563 {
1564 antic_occr = cur_expr->antic_occr;
1565
1566 /* Search for another occurrence in the same basic block. */
1567 while (antic_occr && BLOCK_NUM (antic_occr->insn) != BLOCK_NUM (insn))
1568 {
1569 /* If an occurrence isn't found, save a pointer to the end of
1570 the list. */
1571 last_occr = antic_occr;
1572 antic_occr = antic_occr->next;
1573 }
1574
1575 if (antic_occr)
c4c81601
RK
1576 /* Found another instance of the expression in the same basic block.
1577 Prefer the currently recorded one. We want the first one in the
1578 block and the block is scanned from start to end. */
1579 ; /* nothing to do */
7506f491
DE
1580 else
1581 {
1582 /* First occurrence of this expression in this basic block. */
703ad42b 1583 antic_occr = gcse_alloc (sizeof (struct occr));
7506f491
DE
1584 bytes_used += sizeof (struct occr);
1585 /* First occurrence of this expression in any block? */
1586 if (cur_expr->antic_occr == NULL)
1587 cur_expr->antic_occr = antic_occr;
1588 else
1589 last_occr->next = antic_occr;
c4c81601 1590
7506f491
DE
1591 antic_occr->insn = insn;
1592 antic_occr->next = NULL;
f9957958 1593 antic_occr->deleted_p = 0;
7506f491
DE
1594 }
1595 }
1596
1597 if (avail_p)
1598 {
1599 avail_occr = cur_expr->avail_occr;
1600
1601 /* Search for another occurrence in the same basic block. */
1602 while (avail_occr && BLOCK_NUM (avail_occr->insn) != BLOCK_NUM (insn))
1603 {
1604 /* If an occurrence isn't found, save a pointer to the end of
1605 the list. */
1606 last_occr = avail_occr;
1607 avail_occr = avail_occr->next;
1608 }
1609
1610 if (avail_occr)
c4c81601
RK
1611 /* Found another instance of the expression in the same basic block.
1612 Prefer this occurrence to the currently recorded one. We want
1613 the last one in the block and the block is scanned from start
1614 to end. */
1615 avail_occr->insn = insn;
7506f491
DE
1616 else
1617 {
1618 /* First occurrence of this expression in this basic block. */
703ad42b 1619 avail_occr = gcse_alloc (sizeof (struct occr));
7506f491 1620 bytes_used += sizeof (struct occr);
c4c81601 1621
7506f491
DE
1622 /* First occurrence of this expression in any block? */
1623 if (cur_expr->avail_occr == NULL)
1624 cur_expr->avail_occr = avail_occr;
1625 else
1626 last_occr->next = avail_occr;
c4c81601 1627
7506f491
DE
1628 avail_occr->insn = insn;
1629 avail_occr->next = NULL;
f9957958 1630 avail_occr->deleted_p = 0;
7506f491
DE
1631 }
1632 }
1633}
1634
1635/* Insert pattern X in INSN in the hash table.
1636 X is a SET of a reg to either another reg or a constant.
1637 If it is already present, record it as the last occurrence in INSN's
1638 basic block. */
1639
1640static void
1d088dee 1641insert_set_in_table (rtx x, rtx insn, struct hash_table *table)
7506f491
DE
1642{
1643 int found;
1644 unsigned int hash;
1645 struct expr *cur_expr, *last_expr = NULL;
1646 struct occr *cur_occr, *last_occr = NULL;
1647
282899df 1648 gcc_assert (GET_CODE (x) == SET && REG_P (SET_DEST (x)));
7506f491 1649
02280659 1650 hash = hash_set (REGNO (SET_DEST (x)), table->size);
7506f491 1651
02280659 1652 cur_expr = table->table[hash];
7506f491
DE
1653 found = 0;
1654
c4c81601 1655 while (cur_expr && 0 == (found = expr_equiv_p (cur_expr->expr, x)))
7506f491
DE
1656 {
1657 /* If the expression isn't found, save a pointer to the end of
1658 the list. */
1659 last_expr = cur_expr;
1660 cur_expr = cur_expr->next_same_hash;
1661 }
1662
1663 if (! found)
1664 {
703ad42b 1665 cur_expr = gcse_alloc (sizeof (struct expr));
7506f491 1666 bytes_used += sizeof (struct expr);
02280659 1667 if (table->table[hash] == NULL)
c4c81601 1668 /* This is the first pattern that hashed to this index. */
02280659 1669 table->table[hash] = cur_expr;
7506f491 1670 else
c4c81601
RK
1671 /* Add EXPR to end of this hash chain. */
1672 last_expr->next_same_hash = cur_expr;
1673
7506f491
DE
1674 /* Set the fields of the expr element.
1675 We must copy X because it can be modified when copy propagation is
1676 performed on its operands. */
7506f491 1677 cur_expr->expr = copy_rtx (x);
02280659 1678 cur_expr->bitmap_index = table->n_elems++;
7506f491
DE
1679 cur_expr->next_same_hash = NULL;
1680 cur_expr->antic_occr = NULL;
1681 cur_expr->avail_occr = NULL;
1682 }
1683
1684 /* Now record the occurrence. */
7506f491
DE
1685 cur_occr = cur_expr->avail_occr;
1686
1687 /* Search for another occurrence in the same basic block. */
1688 while (cur_occr && BLOCK_NUM (cur_occr->insn) != BLOCK_NUM (insn))
1689 {
1690 /* If an occurrence isn't found, save a pointer to the end of
1691 the list. */
1692 last_occr = cur_occr;
1693 cur_occr = cur_occr->next;
1694 }
1695
1696 if (cur_occr)
c4c81601
RK
1697 /* Found another instance of the expression in the same basic block.
1698 Prefer this occurrence to the currently recorded one. We want the
1699 last one in the block and the block is scanned from start to end. */
1700 cur_occr->insn = insn;
7506f491
DE
1701 else
1702 {
1703 /* First occurrence of this expression in this basic block. */
703ad42b 1704 cur_occr = gcse_alloc (sizeof (struct occr));
7506f491 1705 bytes_used += sizeof (struct occr);
c4c81601 1706
7506f491
DE
1707 /* First occurrence of this expression in any block? */
1708 if (cur_expr->avail_occr == NULL)
1709 cur_expr->avail_occr = cur_occr;
1710 else
1711 last_occr->next = cur_occr;
c4c81601 1712
7506f491
DE
1713 cur_occr->insn = insn;
1714 cur_occr->next = NULL;
f9957958 1715 cur_occr->deleted_p = 0;
7506f491
DE
1716 }
1717}
1718
6b2d1c9e
RS
1719/* Determine whether the rtx X should be treated as a constant for
1720 the purposes of GCSE's constant propagation. */
1721
1722static bool
1d088dee 1723gcse_constant_p (rtx x)
6b2d1c9e
RS
1724{
1725 /* Consider a COMPARE of two integers constant. */
1726 if (GET_CODE (x) == COMPARE
1727 && GET_CODE (XEXP (x, 0)) == CONST_INT
1728 && GET_CODE (XEXP (x, 1)) == CONST_INT)
1729 return true;
1730
db2f435b 1731 /* Consider a COMPARE of the same registers is a constant
7b1b4aed 1732 if they are not floating point registers. */
db2f435b 1733 if (GET_CODE(x) == COMPARE
7b1b4aed 1734 && REG_P (XEXP (x, 0)) && REG_P (XEXP (x, 1))
db2f435b
AP
1735 && REGNO (XEXP (x, 0)) == REGNO (XEXP (x, 1))
1736 && ! FLOAT_MODE_P (GET_MODE (XEXP (x, 0)))
1737 && ! FLOAT_MODE_P (GET_MODE (XEXP (x, 1))))
1738 return true;
1739
6b2d1c9e
RS
1740 return CONSTANT_P (x);
1741}
1742
02280659
ZD
1743/* Scan pattern PAT of INSN and add an entry to the hash TABLE (set or
1744 expression one). */
7506f491
DE
1745
1746static void
1d088dee 1747hash_scan_set (rtx pat, rtx insn, struct hash_table *table)
7506f491
DE
1748{
1749 rtx src = SET_SRC (pat);
1750 rtx dest = SET_DEST (pat);
172890a2 1751 rtx note;
7506f491 1752
6e72d1e9 1753 if (GET_CODE (src) == CALL)
02280659 1754 hash_scan_call (src, insn, table);
7506f491 1755
7b1b4aed 1756 else if (REG_P (dest))
7506f491 1757 {
172890a2 1758 unsigned int regno = REGNO (dest);
7506f491
DE
1759 rtx tmp;
1760
172890a2
RK
1761 /* If this is a single set and we are doing constant propagation,
1762 see if a REG_NOTE shows this equivalent to a constant. */
02280659 1763 if (table->set_p && (note = find_reg_equal_equiv_note (insn)) != 0
6b2d1c9e 1764 && gcse_constant_p (XEXP (note, 0)))
172890a2
RK
1765 src = XEXP (note, 0), pat = gen_rtx_SET (VOIDmode, dest, src);
1766
7506f491 1767 /* Only record sets of pseudo-regs in the hash table. */
02280659 1768 if (! table->set_p
7506f491
DE
1769 && regno >= FIRST_PSEUDO_REGISTER
1770 /* Don't GCSE something if we can't do a reg/reg copy. */
773eae39 1771 && can_copy_p (GET_MODE (dest))
068473ec
JH
1772 /* GCSE commonly inserts instruction after the insn. We can't
1773 do that easily for EH_REGION notes so disable GCSE on these
1774 for now. */
1775 && !find_reg_note (insn, REG_EH_REGION, NULL_RTX)
7506f491 1776 /* Is SET_SRC something we want to gcse? */
172890a2
RK
1777 && want_to_gcse_p (src)
1778 /* Don't CSE a nop. */
43e72072
JJ
1779 && ! set_noop_p (pat)
1780 /* Don't GCSE if it has attached REG_EQUIV note.
1781 At this point this only function parameters should have
1782 REG_EQUIV notes and if the argument slot is used somewhere
a1f300c0 1783 explicitly, it means address of parameter has been taken,
43e72072
JJ
1784 so we should not extend the lifetime of the pseudo. */
1785 && ((note = find_reg_note (insn, REG_EQUIV, NULL_RTX)) == 0
7b1b4aed 1786 || ! MEM_P (XEXP (note, 0))))
7506f491
DE
1787 {
1788 /* An expression is not anticipatable if its operands are
52d76e11
RK
1789 modified before this insn or if this is not the only SET in
1790 this insn. */
1791 int antic_p = oprs_anticipatable_p (src, insn) && single_set (insn);
7506f491 1792 /* An expression is not available if its operands are
eb296bd9
GK
1793 subsequently modified, including this insn. It's also not
1794 available if this is a branch, because we can't insert
1795 a set after the branch. */
1796 int avail_p = (oprs_available_p (src, insn)
1797 && ! JUMP_P (insn));
c4c81601 1798
02280659 1799 insert_expr_in_table (src, GET_MODE (dest), insn, antic_p, avail_p, table);
7506f491 1800 }
c4c81601 1801
7506f491 1802 /* Record sets for constant/copy propagation. */
02280659 1803 else if (table->set_p
7506f491 1804 && regno >= FIRST_PSEUDO_REGISTER
7b1b4aed 1805 && ((REG_P (src)
7506f491 1806 && REGNO (src) >= FIRST_PSEUDO_REGISTER
773eae39 1807 && can_copy_p (GET_MODE (dest))
172890a2 1808 && REGNO (src) != regno)
6b2d1c9e 1809 || gcse_constant_p (src))
7506f491
DE
1810 /* A copy is not available if its src or dest is subsequently
1811 modified. Here we want to search from INSN+1 on, but
1812 oprs_available_p searches from INSN on. */
a813c111 1813 && (insn == BB_END (BLOCK_FOR_INSN (insn))
7506f491
DE
1814 || ((tmp = next_nonnote_insn (insn)) != NULL_RTX
1815 && oprs_available_p (pat, tmp))))
02280659 1816 insert_set_in_table (pat, insn, table);
7506f491 1817 }
d91edf86 1818 /* In case of store we want to consider the memory value as available in
f5f2e3cd
MH
1819 the REG stored in that memory. This makes it possible to remove
1820 redundant loads from due to stores to the same location. */
7b1b4aed 1821 else if (flag_gcse_las && REG_P (src) && MEM_P (dest))
f5f2e3cd
MH
1822 {
1823 unsigned int regno = REGNO (src);
1824
1825 /* Do not do this for constant/copy propagation. */
1826 if (! table->set_p
1827 /* Only record sets of pseudo-regs in the hash table. */
1828 && regno >= FIRST_PSEUDO_REGISTER
1829 /* Don't GCSE something if we can't do a reg/reg copy. */
1830 && can_copy_p (GET_MODE (src))
1831 /* GCSE commonly inserts instruction after the insn. We can't
1832 do that easily for EH_REGION notes so disable GCSE on these
1833 for now. */
1834 && ! find_reg_note (insn, REG_EH_REGION, NULL_RTX)
1835 /* Is SET_DEST something we want to gcse? */
1836 && want_to_gcse_p (dest)
1837 /* Don't CSE a nop. */
1838 && ! set_noop_p (pat)
1839 /* Don't GCSE if it has attached REG_EQUIV note.
1840 At this point this only function parameters should have
1841 REG_EQUIV notes and if the argument slot is used somewhere
1842 explicitly, it means address of parameter has been taken,
1843 so we should not extend the lifetime of the pseudo. */
1844 && ((note = find_reg_note (insn, REG_EQUIV, NULL_RTX)) == 0
7b1b4aed 1845 || ! MEM_P (XEXP (note, 0))))
f5f2e3cd
MH
1846 {
1847 /* Stores are never anticipatable. */
1848 int antic_p = 0;
1849 /* An expression is not available if its operands are
1850 subsequently modified, including this insn. It's also not
1851 available if this is a branch, because we can't insert
1852 a set after the branch. */
1853 int avail_p = oprs_available_p (dest, insn)
1854 && ! JUMP_P (insn);
1855
1856 /* Record the memory expression (DEST) in the hash table. */
1857 insert_expr_in_table (dest, GET_MODE (dest), insn,
1858 antic_p, avail_p, table);
1859 }
1860 }
7506f491
DE
1861}
1862
1863static void
1d088dee
AJ
1864hash_scan_clobber (rtx x ATTRIBUTE_UNUSED, rtx insn ATTRIBUTE_UNUSED,
1865 struct hash_table *table ATTRIBUTE_UNUSED)
7506f491
DE
1866{
1867 /* Currently nothing to do. */
1868}
1869
1870static void
1d088dee
AJ
1871hash_scan_call (rtx x ATTRIBUTE_UNUSED, rtx insn ATTRIBUTE_UNUSED,
1872 struct hash_table *table ATTRIBUTE_UNUSED)
7506f491
DE
1873{
1874 /* Currently nothing to do. */
1875}
1876
1877/* Process INSN and add hash table entries as appropriate.
1878
1879 Only available expressions that set a single pseudo-reg are recorded.
1880
1881 Single sets in a PARALLEL could be handled, but it's an extra complication
1882 that isn't dealt with right now. The trick is handling the CLOBBERs that
1883 are also in the PARALLEL. Later.
1884
cc2902df 1885 If SET_P is nonzero, this is for the assignment hash table,
ed79bb3d
R
1886 otherwise it is for the expression hash table.
1887 If IN_LIBCALL_BLOCK nonzero, we are in a libcall block, and should
1888 not record any expressions. */
7506f491
DE
1889
1890static void
1d088dee 1891hash_scan_insn (rtx insn, struct hash_table *table, int in_libcall_block)
7506f491
DE
1892{
1893 rtx pat = PATTERN (insn);
c4c81601 1894 int i;
7506f491 1895
172890a2
RK
1896 if (in_libcall_block)
1897 return;
1898
7506f491
DE
1899 /* Pick out the sets of INSN and for other forms of instructions record
1900 what's been modified. */
1901
172890a2 1902 if (GET_CODE (pat) == SET)
02280659 1903 hash_scan_set (pat, insn, table);
7506f491 1904 else if (GET_CODE (pat) == PARALLEL)
c4c81601
RK
1905 for (i = 0; i < XVECLEN (pat, 0); i++)
1906 {
1907 rtx x = XVECEXP (pat, 0, i);
7506f491 1908
c4c81601 1909 if (GET_CODE (x) == SET)
02280659 1910 hash_scan_set (x, insn, table);
c4c81601 1911 else if (GET_CODE (x) == CLOBBER)
02280659 1912 hash_scan_clobber (x, insn, table);
6e72d1e9 1913 else if (GET_CODE (x) == CALL)
02280659 1914 hash_scan_call (x, insn, table);
c4c81601 1915 }
7506f491 1916
7506f491 1917 else if (GET_CODE (pat) == CLOBBER)
02280659 1918 hash_scan_clobber (pat, insn, table);
6e72d1e9 1919 else if (GET_CODE (pat) == CALL)
02280659 1920 hash_scan_call (pat, insn, table);
7506f491
DE
1921}
1922
1923static void
1d088dee 1924dump_hash_table (FILE *file, const char *name, struct hash_table *table)
7506f491
DE
1925{
1926 int i;
1927 /* Flattened out table, so it's printed in proper order. */
4da896b2
MM
1928 struct expr **flat_table;
1929 unsigned int *hash_val;
c4c81601 1930 struct expr *expr;
4da896b2 1931
703ad42b
KG
1932 flat_table = xcalloc (table->n_elems, sizeof (struct expr *));
1933 hash_val = xmalloc (table->n_elems * sizeof (unsigned int));
7506f491 1934
02280659
ZD
1935 for (i = 0; i < (int) table->size; i++)
1936 for (expr = table->table[i]; expr != NULL; expr = expr->next_same_hash)
c4c81601
RK
1937 {
1938 flat_table[expr->bitmap_index] = expr;
1939 hash_val[expr->bitmap_index] = i;
1940 }
7506f491
DE
1941
1942 fprintf (file, "%s hash table (%d buckets, %d entries)\n",
02280659 1943 name, table->size, table->n_elems);
7506f491 1944
02280659 1945 for (i = 0; i < (int) table->n_elems; i++)
21318741
RK
1946 if (flat_table[i] != 0)
1947 {
a0ac9e5a 1948 expr = flat_table[i];
21318741
RK
1949 fprintf (file, "Index %d (hash value %d)\n ",
1950 expr->bitmap_index, hash_val[i]);
a0ac9e5a 1951 print_rtl (file, expr->expr);
21318741
RK
1952 fprintf (file, "\n");
1953 }
7506f491
DE
1954
1955 fprintf (file, "\n");
4da896b2 1956
4da896b2
MM
1957 free (flat_table);
1958 free (hash_val);
7506f491
DE
1959}
1960
1961/* Record register first/last/block set information for REGNO in INSN.
c4c81601 1962
80c29cc4 1963 first_set records the first place in the block where the register
7506f491 1964 is set and is used to compute "anticipatability".
c4c81601 1965
80c29cc4 1966 last_set records the last place in the block where the register
7506f491 1967 is set and is used to compute "availability".
c4c81601 1968
80c29cc4
RZ
1969 last_bb records the block for which first_set and last_set are
1970 valid, as a quick test to invalidate them.
1971
7506f491
DE
1972 reg_set_in_block records whether the register is set in the block
1973 and is used to compute "transparency". */
1974
1975static void
1d088dee 1976record_last_reg_set_info (rtx insn, int regno)
7506f491 1977{
80c29cc4
RZ
1978 struct reg_avail_info *info = &reg_avail_info[regno];
1979 int cuid = INSN_CUID (insn);
c4c81601 1980
80c29cc4
RZ
1981 info->last_set = cuid;
1982 if (info->last_bb != current_bb)
1983 {
1984 info->last_bb = current_bb;
1985 info->first_set = cuid;
e0082a72 1986 SET_BIT (reg_set_in_block[current_bb->index], regno);
80c29cc4 1987 }
7506f491
DE
1988}
1989
a13d4ebf
AM
1990
1991/* Record all of the canonicalized MEMs of record_last_mem_set_info's insn.
1992 Note we store a pair of elements in the list, so they have to be
1993 taken off pairwise. */
1994
589005ff 1995static void
1d088dee
AJ
1996canon_list_insert (rtx dest ATTRIBUTE_UNUSED, rtx unused1 ATTRIBUTE_UNUSED,
1997 void * v_insn)
a13d4ebf
AM
1998{
1999 rtx dest_addr, insn;
0fe854a7 2000 int bb;
a13d4ebf
AM
2001
2002 while (GET_CODE (dest) == SUBREG
2003 || GET_CODE (dest) == ZERO_EXTRACT
2004 || GET_CODE (dest) == SIGN_EXTRACT
2005 || GET_CODE (dest) == STRICT_LOW_PART)
2006 dest = XEXP (dest, 0);
2007
2008 /* If DEST is not a MEM, then it will not conflict with a load. Note
2009 that function calls are assumed to clobber memory, but are handled
2010 elsewhere. */
2011
7b1b4aed 2012 if (! MEM_P (dest))
a13d4ebf
AM
2013 return;
2014
2015 dest_addr = get_addr (XEXP (dest, 0));
2016 dest_addr = canon_rtx (dest_addr);
589005ff 2017 insn = (rtx) v_insn;
0fe854a7 2018 bb = BLOCK_NUM (insn);
a13d4ebf 2019
589005ff 2020 canon_modify_mem_list[bb] =
0fe854a7 2021 alloc_EXPR_LIST (VOIDmode, dest_addr, canon_modify_mem_list[bb]);
589005ff 2022 canon_modify_mem_list[bb] =
0fe854a7
RH
2023 alloc_EXPR_LIST (VOIDmode, dest, canon_modify_mem_list[bb]);
2024 bitmap_set_bit (canon_modify_mem_list_set, bb);
a13d4ebf
AM
2025}
2026
a13d4ebf
AM
2027/* Record memory modification information for INSN. We do not actually care
2028 about the memory location(s) that are set, or even how they are set (consider
2029 a CALL_INSN). We merely need to record which insns modify memory. */
7506f491
DE
2030
2031static void
1d088dee 2032record_last_mem_set_info (rtx insn)
7506f491 2033{
0fe854a7
RH
2034 int bb = BLOCK_NUM (insn);
2035
ccef9ef5 2036 /* load_killed_in_block_p will handle the case of calls clobbering
dc297297 2037 everything. */
0fe854a7
RH
2038 modify_mem_list[bb] = alloc_INSN_LIST (insn, modify_mem_list[bb]);
2039 bitmap_set_bit (modify_mem_list_set, bb);
a13d4ebf 2040
7b1b4aed 2041 if (CALL_P (insn))
a13d4ebf
AM
2042 {
2043 /* Note that traversals of this loop (other than for free-ing)
2044 will break after encountering a CALL_INSN. So, there's no
dc297297 2045 need to insert a pair of items, as canon_list_insert does. */
589005ff
KH
2046 canon_modify_mem_list[bb] =
2047 alloc_INSN_LIST (insn, canon_modify_mem_list[bb]);
0fe854a7 2048 bitmap_set_bit (canon_modify_mem_list_set, bb);
a13d4ebf
AM
2049 }
2050 else
0fe854a7 2051 note_stores (PATTERN (insn), canon_list_insert, (void*) insn);
7506f491
DE
2052}
2053
7506f491 2054/* Called from compute_hash_table via note_stores to handle one
84832317
MM
2055 SET or CLOBBER in an insn. DATA is really the instruction in which
2056 the SET is taking place. */
7506f491
DE
2057
2058static void
1d088dee 2059record_last_set_info (rtx dest, rtx setter ATTRIBUTE_UNUSED, void *data)
7506f491 2060{
84832317
MM
2061 rtx last_set_insn = (rtx) data;
2062
7506f491
DE
2063 if (GET_CODE (dest) == SUBREG)
2064 dest = SUBREG_REG (dest);
2065
7b1b4aed 2066 if (REG_P (dest))
7506f491 2067 record_last_reg_set_info (last_set_insn, REGNO (dest));
7b1b4aed 2068 else if (MEM_P (dest)
7506f491
DE
2069 /* Ignore pushes, they clobber nothing. */
2070 && ! push_operand (dest, GET_MODE (dest)))
2071 record_last_mem_set_info (last_set_insn);
2072}
2073
2074/* Top level function to create an expression or assignment hash table.
2075
2076 Expression entries are placed in the hash table if
2077 - they are of the form (set (pseudo-reg) src),
2078 - src is something we want to perform GCSE on,
2079 - none of the operands are subsequently modified in the block
2080
2081 Assignment entries are placed in the hash table if
2082 - they are of the form (set (pseudo-reg) src),
2083 - src is something we want to perform const/copy propagation on,
2084 - none of the operands or target are subsequently modified in the block
c4c81601 2085
7506f491
DE
2086 Currently src must be a pseudo-reg or a const_int.
2087
02280659 2088 TABLE is the table computed. */
7506f491
DE
2089
2090static void
1d088dee 2091compute_hash_table_work (struct hash_table *table)
7506f491 2092{
80c29cc4 2093 unsigned int i;
7506f491
DE
2094
2095 /* While we compute the hash table we also compute a bit array of which
2096 registers are set in which blocks.
7506f491
DE
2097 ??? This isn't needed during const/copy propagation, but it's cheap to
2098 compute. Later. */
d55bc081 2099 sbitmap_vector_zero (reg_set_in_block, last_basic_block);
7506f491 2100
a13d4ebf 2101 /* re-Cache any INSN_LIST nodes we have allocated. */
73991d6a 2102 clear_modify_mem_tables ();
7506f491 2103 /* Some working arrays used to track first and last set in each block. */
703ad42b 2104 reg_avail_info = gmalloc (max_gcse_regno * sizeof (struct reg_avail_info));
80c29cc4
RZ
2105
2106 for (i = 0; i < max_gcse_regno; ++i)
e0082a72 2107 reg_avail_info[i].last_bb = NULL;
7506f491 2108
e0082a72 2109 FOR_EACH_BB (current_bb)
7506f491
DE
2110 {
2111 rtx insn;
770ae6cc 2112 unsigned int regno;
ed79bb3d 2113 int in_libcall_block;
7506f491
DE
2114
2115 /* First pass over the instructions records information used to
2116 determine when registers and memory are first and last set.
ccef9ef5 2117 ??? hard-reg reg_set_in_block computation
7506f491
DE
2118 could be moved to compute_sets since they currently don't change. */
2119
a813c111
SB
2120 for (insn = BB_HEAD (current_bb);
2121 insn && insn != NEXT_INSN (BB_END (current_bb));
7506f491
DE
2122 insn = NEXT_INSN (insn))
2123 {
2c3c49de 2124 if (! INSN_P (insn))
7506f491
DE
2125 continue;
2126
7b1b4aed 2127 if (CALL_P (insn))
7506f491 2128 {
19652adf 2129 bool clobbers_all = false;
589005ff 2130#ifdef NON_SAVING_SETJMP
19652adf
ZW
2131 if (NON_SAVING_SETJMP
2132 && find_reg_note (insn, REG_SETJMP, NULL_RTX))
2133 clobbers_all = true;
2134#endif
2135
7506f491 2136 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
19652adf
ZW
2137 if (clobbers_all
2138 || TEST_HARD_REG_BIT (regs_invalidated_by_call, regno))
7506f491 2139 record_last_reg_set_info (insn, regno);
c4c81601 2140
24a28584 2141 mark_call (insn);
7506f491
DE
2142 }
2143
84832317 2144 note_stores (PATTERN (insn), record_last_set_info, insn);
7506f491
DE
2145 }
2146
fbef91d8
RS
2147 /* Insert implicit sets in the hash table. */
2148 if (table->set_p
2149 && implicit_sets[current_bb->index] != NULL_RTX)
2150 hash_scan_set (implicit_sets[current_bb->index],
a813c111 2151 BB_HEAD (current_bb), table);
fbef91d8 2152
7506f491
DE
2153 /* The next pass builds the hash table. */
2154
a813c111
SB
2155 for (insn = BB_HEAD (current_bb), in_libcall_block = 0;
2156 insn && insn != NEXT_INSN (BB_END (current_bb));
7506f491 2157 insn = NEXT_INSN (insn))
2c3c49de 2158 if (INSN_P (insn))
c4c81601
RK
2159 {
2160 if (find_reg_note (insn, REG_LIBCALL, NULL_RTX))
589005ff 2161 in_libcall_block = 1;
02280659 2162 else if (table->set_p && find_reg_note (insn, REG_RETVAL, NULL_RTX))
589005ff 2163 in_libcall_block = 0;
02280659
ZD
2164 hash_scan_insn (insn, table, in_libcall_block);
2165 if (!table->set_p && find_reg_note (insn, REG_RETVAL, NULL_RTX))
589005ff 2166 in_libcall_block = 0;
8e42ace1 2167 }
7506f491
DE
2168 }
2169
80c29cc4
RZ
2170 free (reg_avail_info);
2171 reg_avail_info = NULL;
7506f491
DE
2172}
2173
02280659 2174/* Allocate space for the set/expr hash TABLE.
7506f491 2175 N_INSNS is the number of instructions in the function.
02280659
ZD
2176 It is used to determine the number of buckets to use.
2177 SET_P determines whether set or expression table will
2178 be created. */
7506f491
DE
2179
2180static void
1d088dee 2181alloc_hash_table (int n_insns, struct hash_table *table, int set_p)
7506f491
DE
2182{
2183 int n;
2184
02280659
ZD
2185 table->size = n_insns / 4;
2186 if (table->size < 11)
2187 table->size = 11;
c4c81601 2188
7506f491
DE
2189 /* Attempt to maintain efficient use of hash table.
2190 Making it an odd number is simplest for now.
2191 ??? Later take some measurements. */
02280659
ZD
2192 table->size |= 1;
2193 n = table->size * sizeof (struct expr *);
703ad42b 2194 table->table = gmalloc (n);
02280659 2195 table->set_p = set_p;
7506f491
DE
2196}
2197
02280659 2198/* Free things allocated by alloc_hash_table. */
7506f491
DE
2199
2200static void
1d088dee 2201free_hash_table (struct hash_table *table)
7506f491 2202{
02280659 2203 free (table->table);
7506f491
DE
2204}
2205
02280659
ZD
2206/* Compute the hash TABLE for doing copy/const propagation or
2207 expression hash table. */
7506f491
DE
2208
2209static void
1d088dee 2210compute_hash_table (struct hash_table *table)
7506f491
DE
2211{
2212 /* Initialize count of number of entries in hash table. */
02280659 2213 table->n_elems = 0;
703ad42b 2214 memset (table->table, 0, table->size * sizeof (struct expr *));
7506f491 2215
02280659 2216 compute_hash_table_work (table);
7506f491
DE
2217}
2218\f
2219/* Expression tracking support. */
2220
ceda50e9
RH
2221/* Lookup REGNO in the set TABLE. The result is a pointer to the
2222 table entry, or NULL if not found. */
7506f491
DE
2223
2224static struct expr *
1d088dee 2225lookup_set (unsigned int regno, struct hash_table *table)
7506f491 2226{
02280659 2227 unsigned int hash = hash_set (regno, table->size);
7506f491
DE
2228 struct expr *expr;
2229
02280659 2230 expr = table->table[hash];
7506f491 2231
ceda50e9
RH
2232 while (expr && REGNO (SET_DEST (expr->expr)) != regno)
2233 expr = expr->next_same_hash;
7506f491
DE
2234
2235 return expr;
2236}
2237
2238/* Return the next entry for REGNO in list EXPR. */
2239
2240static struct expr *
1d088dee 2241next_set (unsigned int regno, struct expr *expr)
7506f491
DE
2242{
2243 do
2244 expr = expr->next_same_hash;
2245 while (expr && REGNO (SET_DEST (expr->expr)) != regno);
c4c81601 2246
7506f491
DE
2247 return expr;
2248}
2249
0fe854a7
RH
2250/* Like free_INSN_LIST_list or free_EXPR_LIST_list, except that the node
2251 types may be mixed. */
2252
2253static void
1d088dee 2254free_insn_expr_list_list (rtx *listp)
0fe854a7
RH
2255{
2256 rtx list, next;
2257
2258 for (list = *listp; list ; list = next)
2259 {
2260 next = XEXP (list, 1);
2261 if (GET_CODE (list) == EXPR_LIST)
2262 free_EXPR_LIST_node (list);
2263 else
2264 free_INSN_LIST_node (list);
2265 }
2266
2267 *listp = NULL;
2268}
2269
73991d6a
JH
2270/* Clear canon_modify_mem_list and modify_mem_list tables. */
2271static void
1d088dee 2272clear_modify_mem_tables (void)
73991d6a 2273{
3cd8c58a 2274 unsigned i;
87c476a2 2275 bitmap_iterator bi;
73991d6a 2276
87c476a2
ZD
2277 EXECUTE_IF_SET_IN_BITMAP (modify_mem_list_set, 0, i, bi)
2278 {
2279 free_INSN_LIST_list (modify_mem_list + i);
2280 }
0fe854a7 2281 bitmap_clear (modify_mem_list_set);
73991d6a 2282
87c476a2
ZD
2283 EXECUTE_IF_SET_IN_BITMAP (canon_modify_mem_list_set, 0, i, bi)
2284 {
2285 free_insn_expr_list_list (canon_modify_mem_list + i);
2286 }
0fe854a7 2287 bitmap_clear (canon_modify_mem_list_set);
73991d6a
JH
2288}
2289
2290/* Release memory used by modify_mem_list_set and canon_modify_mem_list_set. */
2291
2292static void
1d088dee 2293free_modify_mem_tables (void)
73991d6a
JH
2294{
2295 clear_modify_mem_tables ();
2296 free (modify_mem_list);
2297 free (canon_modify_mem_list);
2298 modify_mem_list = 0;
2299 canon_modify_mem_list = 0;
2300}
2301
7506f491
DE
2302/* Reset tables used to keep track of what's still available [since the
2303 start of the block]. */
2304
2305static void
1d088dee 2306reset_opr_set_tables (void)
7506f491
DE
2307{
2308 /* Maintain a bitmap of which regs have been set since beginning of
2309 the block. */
73991d6a 2310 CLEAR_REG_SET (reg_set_bitmap);
c4c81601 2311
7506f491
DE
2312 /* Also keep a record of the last instruction to modify memory.
2313 For now this is very trivial, we only record whether any memory
2314 location has been modified. */
73991d6a 2315 clear_modify_mem_tables ();
7506f491
DE
2316}
2317
cc2902df 2318/* Return nonzero if the operands of X are not set before INSN in
7506f491
DE
2319 INSN's basic block. */
2320
2321static int
1d088dee 2322oprs_not_set_p (rtx x, rtx insn)
7506f491 2323{
c4c81601 2324 int i, j;
7506f491 2325 enum rtx_code code;
6f7d635c 2326 const char *fmt;
7506f491 2327
7506f491
DE
2328 if (x == 0)
2329 return 1;
2330
2331 code = GET_CODE (x);
2332 switch (code)
2333 {
2334 case PC:
2335 case CC0:
2336 case CONST:
2337 case CONST_INT:
2338 case CONST_DOUBLE:
69ef87e2 2339 case CONST_VECTOR:
7506f491
DE
2340 case SYMBOL_REF:
2341 case LABEL_REF:
2342 case ADDR_VEC:
2343 case ADDR_DIFF_VEC:
2344 return 1;
2345
2346 case MEM:
589005ff 2347 if (load_killed_in_block_p (BLOCK_FOR_INSN (insn),
e2d2ed72 2348 INSN_CUID (insn), x, 0))
a13d4ebf 2349 return 0;
c4c81601
RK
2350 else
2351 return oprs_not_set_p (XEXP (x, 0), insn);
7506f491
DE
2352
2353 case REG:
73991d6a 2354 return ! REGNO_REG_SET_P (reg_set_bitmap, REGNO (x));
7506f491
DE
2355
2356 default:
2357 break;
2358 }
2359
c4c81601 2360 for (i = GET_RTX_LENGTH (code) - 1, fmt = GET_RTX_FORMAT (code); i >= 0; i--)
7506f491
DE
2361 {
2362 if (fmt[i] == 'e')
2363 {
7506f491
DE
2364 /* If we are about to do the last recursive call
2365 needed at this level, change it into iteration.
2366 This function is called enough to be worth it. */
2367 if (i == 0)
c4c81601
RK
2368 return oprs_not_set_p (XEXP (x, i), insn);
2369
2370 if (! oprs_not_set_p (XEXP (x, i), insn))
7506f491
DE
2371 return 0;
2372 }
2373 else if (fmt[i] == 'E')
c4c81601
RK
2374 for (j = 0; j < XVECLEN (x, i); j++)
2375 if (! oprs_not_set_p (XVECEXP (x, i, j), insn))
2376 return 0;
7506f491
DE
2377 }
2378
2379 return 1;
2380}
2381
2382/* Mark things set by a CALL. */
2383
2384static void
1d088dee 2385mark_call (rtx insn)
7506f491 2386{
24a28584 2387 if (! CONST_OR_PURE_CALL_P (insn))
a13d4ebf 2388 record_last_mem_set_info (insn);
7506f491
DE
2389}
2390
2391/* Mark things set by a SET. */
2392
2393static void
1d088dee 2394mark_set (rtx pat, rtx insn)
7506f491
DE
2395{
2396 rtx dest = SET_DEST (pat);
2397
2398 while (GET_CODE (dest) == SUBREG
2399 || GET_CODE (dest) == ZERO_EXTRACT
2400 || GET_CODE (dest) == SIGN_EXTRACT
2401 || GET_CODE (dest) == STRICT_LOW_PART)
2402 dest = XEXP (dest, 0);
2403
7b1b4aed 2404 if (REG_P (dest))
73991d6a 2405 SET_REGNO_REG_SET (reg_set_bitmap, REGNO (dest));
7b1b4aed 2406 else if (MEM_P (dest))
a13d4ebf
AM
2407 record_last_mem_set_info (insn);
2408
6e72d1e9 2409 if (GET_CODE (SET_SRC (pat)) == CALL)
b5ce41ff 2410 mark_call (insn);
7506f491
DE
2411}
2412
2413/* Record things set by a CLOBBER. */
2414
2415static void
1d088dee 2416mark_clobber (rtx pat, rtx insn)
7506f491
DE
2417{
2418 rtx clob = XEXP (pat, 0);
2419
2420 while (GET_CODE (clob) == SUBREG || GET_CODE (clob) == STRICT_LOW_PART)
2421 clob = XEXP (clob, 0);
2422
7b1b4aed 2423 if (REG_P (clob))
73991d6a 2424 SET_REGNO_REG_SET (reg_set_bitmap, REGNO (clob));
a13d4ebf
AM
2425 else
2426 record_last_mem_set_info (insn);
7506f491
DE
2427}
2428
2429/* Record things set by INSN.
2430 This data is used by oprs_not_set_p. */
2431
2432static void
1d088dee 2433mark_oprs_set (rtx insn)
7506f491
DE
2434{
2435 rtx pat = PATTERN (insn);
c4c81601 2436 int i;
7506f491
DE
2437
2438 if (GET_CODE (pat) == SET)
2439 mark_set (pat, insn);
2440 else if (GET_CODE (pat) == PARALLEL)
c4c81601
RK
2441 for (i = 0; i < XVECLEN (pat, 0); i++)
2442 {
2443 rtx x = XVECEXP (pat, 0, i);
2444
2445 if (GET_CODE (x) == SET)
2446 mark_set (x, insn);
2447 else if (GET_CODE (x) == CLOBBER)
2448 mark_clobber (x, insn);
6e72d1e9 2449 else if (GET_CODE (x) == CALL)
c4c81601
RK
2450 mark_call (insn);
2451 }
7506f491 2452
7506f491
DE
2453 else if (GET_CODE (pat) == CLOBBER)
2454 mark_clobber (pat, insn);
6e72d1e9 2455 else if (GET_CODE (pat) == CALL)
b5ce41ff 2456 mark_call (insn);
7506f491 2457}
b5ce41ff 2458
7506f491
DE
2459\f
2460/* Compute copy/constant propagation working variables. */
2461
2462/* Local properties of assignments. */
7506f491
DE
2463static sbitmap *cprop_pavloc;
2464static sbitmap *cprop_absaltered;
2465
2466/* Global properties of assignments (computed from the local properties). */
7506f491
DE
2467static sbitmap *cprop_avin;
2468static sbitmap *cprop_avout;
2469
c4c81601
RK
2470/* Allocate vars used for copy/const propagation. N_BLOCKS is the number of
2471 basic blocks. N_SETS is the number of sets. */
7506f491
DE
2472
2473static void
1d088dee 2474alloc_cprop_mem (int n_blocks, int n_sets)
7506f491
DE
2475{
2476 cprop_pavloc = sbitmap_vector_alloc (n_blocks, n_sets);
2477 cprop_absaltered = sbitmap_vector_alloc (n_blocks, n_sets);
2478
2479 cprop_avin = sbitmap_vector_alloc (n_blocks, n_sets);
2480 cprop_avout = sbitmap_vector_alloc (n_blocks, n_sets);
2481}
2482
2483/* Free vars used by copy/const propagation. */
2484
2485static void
1d088dee 2486free_cprop_mem (void)
7506f491 2487{
5a660bff
DB
2488 sbitmap_vector_free (cprop_pavloc);
2489 sbitmap_vector_free (cprop_absaltered);
2490 sbitmap_vector_free (cprop_avin);
2491 sbitmap_vector_free (cprop_avout);
7506f491
DE
2492}
2493
c4c81601
RK
2494/* For each block, compute whether X is transparent. X is either an
2495 expression or an assignment [though we don't care which, for this context
2496 an assignment is treated as an expression]. For each block where an
2497 element of X is modified, set (SET_P == 1) or reset (SET_P == 0) the INDX
2498 bit in BMAP. */
7506f491
DE
2499
2500static void
1d088dee 2501compute_transp (rtx x, int indx, sbitmap *bmap, int set_p)
7506f491 2502{
e0082a72
ZD
2503 int i, j;
2504 basic_block bb;
7506f491 2505 enum rtx_code code;
c4c81601 2506 reg_set *r;
6f7d635c 2507 const char *fmt;
7506f491 2508
c4c81601
RK
2509 /* repeat is used to turn tail-recursion into iteration since GCC
2510 can't do it when there's no return value. */
7506f491
DE
2511 repeat:
2512
2513 if (x == 0)
2514 return;
2515
2516 code = GET_CODE (x);
2517 switch (code)
2518 {
2519 case REG:
c4c81601
RK
2520 if (set_p)
2521 {
2522 if (REGNO (x) < FIRST_PSEUDO_REGISTER)
2523 {
e0082a72
ZD
2524 FOR_EACH_BB (bb)
2525 if (TEST_BIT (reg_set_in_block[bb->index], REGNO (x)))
2526 SET_BIT (bmap[bb->index], indx);
c4c81601
RK
2527 }
2528 else
2529 {
2530 for (r = reg_set_table[REGNO (x)]; r != NULL; r = r->next)
2531 SET_BIT (bmap[BLOCK_NUM (r->insn)], indx);
2532 }
2533 }
2534 else
2535 {
2536 if (REGNO (x) < FIRST_PSEUDO_REGISTER)
2537 {
e0082a72
ZD
2538 FOR_EACH_BB (bb)
2539 if (TEST_BIT (reg_set_in_block[bb->index], REGNO (x)))
2540 RESET_BIT (bmap[bb->index], indx);
c4c81601
RK
2541 }
2542 else
2543 {
2544 for (r = reg_set_table[REGNO (x)]; r != NULL; r = r->next)
2545 RESET_BIT (bmap[BLOCK_NUM (r->insn)], indx);
2546 }
2547 }
7506f491 2548
c4c81601 2549 return;
7506f491
DE
2550
2551 case MEM:
e0082a72 2552 FOR_EACH_BB (bb)
a13d4ebf 2553 {
e0082a72 2554 rtx list_entry = canon_modify_mem_list[bb->index];
a13d4ebf
AM
2555
2556 while (list_entry)
2557 {
2558 rtx dest, dest_addr;
2559
7b1b4aed 2560 if (CALL_P (XEXP (list_entry, 0)))
a13d4ebf
AM
2561 {
2562 if (set_p)
e0082a72 2563 SET_BIT (bmap[bb->index], indx);
a13d4ebf 2564 else
e0082a72 2565 RESET_BIT (bmap[bb->index], indx);
a13d4ebf
AM
2566 break;
2567 }
2568 /* LIST_ENTRY must be an INSN of some kind that sets memory.
2569 Examine each hunk of memory that is modified. */
2570
2571 dest = XEXP (list_entry, 0);
2572 list_entry = XEXP (list_entry, 1);
2573 dest_addr = XEXP (list_entry, 0);
589005ff 2574
a13d4ebf
AM
2575 if (canon_true_dependence (dest, GET_MODE (dest), dest_addr,
2576 x, rtx_addr_varies_p))
2577 {
2578 if (set_p)
e0082a72 2579 SET_BIT (bmap[bb->index], indx);
a13d4ebf 2580 else
e0082a72 2581 RESET_BIT (bmap[bb->index], indx);
a13d4ebf
AM
2582 break;
2583 }
2584 list_entry = XEXP (list_entry, 1);
2585 }
2586 }
c4c81601 2587
7506f491
DE
2588 x = XEXP (x, 0);
2589 goto repeat;
2590
2591 case PC:
2592 case CC0: /*FIXME*/
2593 case CONST:
2594 case CONST_INT:
2595 case CONST_DOUBLE:
69ef87e2 2596 case CONST_VECTOR:
7506f491
DE
2597 case SYMBOL_REF:
2598 case LABEL_REF:
2599 case ADDR_VEC:
2600 case ADDR_DIFF_VEC:
2601 return;
2602
2603 default:
2604 break;
2605 }
2606
c4c81601 2607 for (i = GET_RTX_LENGTH (code) - 1, fmt = GET_RTX_FORMAT (code); i >= 0; i--)
7506f491
DE
2608 {
2609 if (fmt[i] == 'e')
2610 {
7506f491
DE
2611 /* If we are about to do the last recursive call
2612 needed at this level, change it into iteration.
2613 This function is called enough to be worth it. */
2614 if (i == 0)
2615 {
c4c81601 2616 x = XEXP (x, i);
7506f491
DE
2617 goto repeat;
2618 }
c4c81601
RK
2619
2620 compute_transp (XEXP (x, i), indx, bmap, set_p);
7506f491
DE
2621 }
2622 else if (fmt[i] == 'E')
c4c81601
RK
2623 for (j = 0; j < XVECLEN (x, i); j++)
2624 compute_transp (XVECEXP (x, i, j), indx, bmap, set_p);
7506f491
DE
2625 }
2626}
2627
7506f491
DE
2628/* Top level routine to do the dataflow analysis needed by copy/const
2629 propagation. */
2630
2631static void
1d088dee 2632compute_cprop_data (void)
7506f491 2633{
02280659 2634 compute_local_properties (cprop_absaltered, cprop_pavloc, NULL, &set_hash_table);
ce724250
JL
2635 compute_available (cprop_pavloc, cprop_absaltered,
2636 cprop_avout, cprop_avin);
7506f491
DE
2637}
2638\f
2639/* Copy/constant propagation. */
2640
7506f491
DE
2641/* Maximum number of register uses in an insn that we handle. */
2642#define MAX_USES 8
2643
2644/* Table of uses found in an insn.
2645 Allocated statically to avoid alloc/free complexity and overhead. */
2646static struct reg_use reg_use_table[MAX_USES];
2647
2648/* Index into `reg_use_table' while building it. */
2649static int reg_use_count;
2650
c4c81601
RK
2651/* Set up a list of register numbers used in INSN. The found uses are stored
2652 in `reg_use_table'. `reg_use_count' is initialized to zero before entry,
2653 and contains the number of uses in the table upon exit.
7506f491 2654
c4c81601
RK
2655 ??? If a register appears multiple times we will record it multiple times.
2656 This doesn't hurt anything but it will slow things down. */
7506f491
DE
2657
2658static void
1d088dee 2659find_used_regs (rtx *xptr, void *data ATTRIBUTE_UNUSED)
7506f491 2660{
c4c81601 2661 int i, j;
7506f491 2662 enum rtx_code code;
6f7d635c 2663 const char *fmt;
9e71c818 2664 rtx x = *xptr;
7506f491 2665
c4c81601
RK
2666 /* repeat is used to turn tail-recursion into iteration since GCC
2667 can't do it when there's no return value. */
7506f491 2668 repeat:
7506f491
DE
2669 if (x == 0)
2670 return;
2671
2672 code = GET_CODE (x);
9e71c818 2673 if (REG_P (x))
7506f491 2674 {
7506f491
DE
2675 if (reg_use_count == MAX_USES)
2676 return;
c4c81601 2677
7506f491
DE
2678 reg_use_table[reg_use_count].reg_rtx = x;
2679 reg_use_count++;
7506f491
DE
2680 }
2681
2682 /* Recursively scan the operands of this expression. */
2683
c4c81601 2684 for (i = GET_RTX_LENGTH (code) - 1, fmt = GET_RTX_FORMAT (code); i >= 0; i--)
7506f491
DE
2685 {
2686 if (fmt[i] == 'e')
2687 {
2688 /* If we are about to do the last recursive call
2689 needed at this level, change it into iteration.
2690 This function is called enough to be worth it. */
2691 if (i == 0)
2692 {
2693 x = XEXP (x, 0);
2694 goto repeat;
2695 }
c4c81601 2696
9e71c818 2697 find_used_regs (&XEXP (x, i), data);
7506f491
DE
2698 }
2699 else if (fmt[i] == 'E')
c4c81601 2700 for (j = 0; j < XVECLEN (x, i); j++)
9e71c818 2701 find_used_regs (&XVECEXP (x, i, j), data);
7506f491
DE
2702 }
2703}
2704
2705/* Try to replace all non-SET_DEST occurrences of FROM in INSN with TO.
cc2902df 2706 Returns nonzero is successful. */
7506f491
DE
2707
2708static int
1d088dee 2709try_replace_reg (rtx from, rtx to, rtx insn)
7506f491 2710{
172890a2 2711 rtx note = find_reg_equal_equiv_note (insn);
fb0c0a12 2712 rtx src = 0;
172890a2
RK
2713 int success = 0;
2714 rtx set = single_set (insn);
833fc3ad 2715
2b773ee2
JH
2716 validate_replace_src_group (from, to, insn);
2717 if (num_changes_pending () && apply_change_group ())
2718 success = 1;
9e71c818 2719
9feff114
JDA
2720 /* Try to simplify SET_SRC if we have substituted a constant. */
2721 if (success && set && CONSTANT_P (to))
2722 {
2723 src = simplify_rtx (SET_SRC (set));
2724
2725 if (src)
2726 validate_change (insn, &SET_SRC (set), src, 0);
2727 }
2728
ed8395a0
JZ
2729 /* If there is already a NOTE, update the expression in it with our
2730 replacement. */
2731 if (note != 0)
2732 XEXP (note, 0) = simplify_replace_rtx (XEXP (note, 0), from, to);
2733
f305679f 2734 if (!success && set && reg_mentioned_p (from, SET_SRC (set)))
833fc3ad 2735 {
f305679f
JH
2736 /* If above failed and this is a single set, try to simplify the source of
2737 the set given our substitution. We could perhaps try this for multiple
2738 SETs, but it probably won't buy us anything. */
172890a2
RK
2739 src = simplify_replace_rtx (SET_SRC (set), from, to);
2740
9e71c818
JH
2741 if (!rtx_equal_p (src, SET_SRC (set))
2742 && validate_change (insn, &SET_SRC (set), src, 0))
172890a2 2743 success = 1;
833fc3ad 2744
bbd288a4
FS
2745 /* If we've failed to do replacement, have a single SET, don't already
2746 have a note, and have no special SET, add a REG_EQUAL note to not
2747 lose information. */
2748 if (!success && note == 0 && set != 0
2749 && GET_CODE (XEXP (set, 0)) != ZERO_EXTRACT
2750 && GET_CODE (XEXP (set, 0)) != SIGN_EXTRACT)
f305679f
JH
2751 note = set_unique_reg_note (insn, REG_EQUAL, copy_rtx (src));
2752 }
e251e2a2 2753
172890a2
RK
2754 /* REG_EQUAL may get simplified into register.
2755 We don't allow that. Remove that note. This code ought
fbe5a4a6 2756 not to happen, because previous code ought to synthesize
172890a2
RK
2757 reg-reg move, but be on the safe side. */
2758 if (note && REG_P (XEXP (note, 0)))
2759 remove_note (insn, note);
833fc3ad 2760
833fc3ad
JH
2761 return success;
2762}
c4c81601
RK
2763
2764/* Find a set of REGNOs that are available on entry to INSN's block. Returns
2765 NULL no such set is found. */
7506f491
DE
2766
2767static struct expr *
1d088dee 2768find_avail_set (int regno, rtx insn)
7506f491 2769{
cafba495
BS
2770 /* SET1 contains the last set found that can be returned to the caller for
2771 use in a substitution. */
2772 struct expr *set1 = 0;
589005ff 2773
cafba495 2774 /* Loops are not possible here. To get a loop we would need two sets
454ff5cb 2775 available at the start of the block containing INSN. i.e. we would
cafba495
BS
2776 need two sets like this available at the start of the block:
2777
2778 (set (reg X) (reg Y))
2779 (set (reg Y) (reg X))
2780
2781 This can not happen since the set of (reg Y) would have killed the
2782 set of (reg X) making it unavailable at the start of this block. */
2783 while (1)
8e42ace1 2784 {
cafba495 2785 rtx src;
ceda50e9 2786 struct expr *set = lookup_set (regno, &set_hash_table);
cafba495
BS
2787
2788 /* Find a set that is available at the start of the block
2789 which contains INSN. */
2790 while (set)
2791 {
2792 if (TEST_BIT (cprop_avin[BLOCK_NUM (insn)], set->bitmap_index))
2793 break;
2794 set = next_set (regno, set);
2795 }
7506f491 2796
cafba495
BS
2797 /* If no available set was found we've reached the end of the
2798 (possibly empty) copy chain. */
2799 if (set == 0)
589005ff 2800 break;
cafba495 2801
282899df 2802 gcc_assert (GET_CODE (set->expr) == SET);
cafba495
BS
2803
2804 src = SET_SRC (set->expr);
2805
2806 /* We know the set is available.
2807 Now check that SRC is ANTLOC (i.e. none of the source operands
589005ff 2808 have changed since the start of the block).
cafba495
BS
2809
2810 If the source operand changed, we may still use it for the next
2811 iteration of this loop, but we may not use it for substitutions. */
c4c81601 2812
6b2d1c9e 2813 if (gcse_constant_p (src) || oprs_not_set_p (src, insn))
cafba495
BS
2814 set1 = set;
2815
2816 /* If the source of the set is anything except a register, then
2817 we have reached the end of the copy chain. */
7b1b4aed 2818 if (! REG_P (src))
7506f491 2819 break;
7506f491 2820
454ff5cb 2821 /* Follow the copy chain, i.e. start another iteration of the loop
cafba495
BS
2822 and see if we have an available copy into SRC. */
2823 regno = REGNO (src);
8e42ace1 2824 }
cafba495
BS
2825
2826 /* SET1 holds the last set that was available and anticipatable at
2827 INSN. */
2828 return set1;
7506f491
DE
2829}
2830
abd535b6 2831/* Subroutine of cprop_insn that tries to propagate constants into
0e3f0221 2832 JUMP_INSNS. JUMP must be a conditional jump. If SETCC is non-NULL
fbe5a4a6 2833 it is the instruction that immediately precedes JUMP, and must be a
818b6b7f 2834 single SET of a register. FROM is what we will try to replace,
0e3f0221 2835 SRC is the constant we will try to substitute for it. Returns nonzero
589005ff 2836 if a change was made. */
c4c81601 2837
abd535b6 2838static int
1d088dee 2839cprop_jump (basic_block bb, rtx setcc, rtx jump, rtx from, rtx src)
abd535b6 2840{
bc6688b4 2841 rtx new, set_src, note_src;
0e3f0221 2842 rtx set = pc_set (jump);
bc6688b4 2843 rtx note = find_reg_equal_equiv_note (jump);
0e3f0221 2844
bc6688b4
RS
2845 if (note)
2846 {
2847 note_src = XEXP (note, 0);
2848 if (GET_CODE (note_src) == EXPR_LIST)
2849 note_src = NULL_RTX;
2850 }
2851 else note_src = NULL_RTX;
2852
2853 /* Prefer REG_EQUAL notes except those containing EXPR_LISTs. */
2854 set_src = note_src ? note_src : SET_SRC (set);
2855
2856 /* First substitute the SETCC condition into the JUMP instruction,
2857 then substitute that given values into this expanded JUMP. */
2858 if (setcc != NULL_RTX
48ddd46c
JH
2859 && !modified_between_p (from, setcc, jump)
2860 && !modified_between_p (src, setcc, jump))
b2f02503 2861 {
bc6688b4 2862 rtx setcc_src;
b2f02503 2863 rtx setcc_set = single_set (setcc);
bc6688b4
RS
2864 rtx setcc_note = find_reg_equal_equiv_note (setcc);
2865 setcc_src = (setcc_note && GET_CODE (XEXP (setcc_note, 0)) != EXPR_LIST)
2866 ? XEXP (setcc_note, 0) : SET_SRC (setcc_set);
2867 set_src = simplify_replace_rtx (set_src, SET_DEST (setcc_set),
2868 setcc_src);
b2f02503 2869 }
0e3f0221 2870 else
bc6688b4 2871 setcc = NULL_RTX;
0e3f0221 2872
bc6688b4 2873 new = simplify_replace_rtx (set_src, from, src);
abd535b6 2874
bc6688b4
RS
2875 /* If no simplification can be made, then try the next register. */
2876 if (rtx_equal_p (new, SET_SRC (set)))
9e48c409 2877 return 0;
589005ff 2878
7d5ab30e 2879 /* If this is now a no-op delete it, otherwise this must be a valid insn. */
172890a2 2880 if (new == pc_rtx)
0e3f0221 2881 delete_insn (jump);
7d5ab30e 2882 else
abd535b6 2883 {
48ddd46c
JH
2884 /* Ensure the value computed inside the jump insn to be equivalent
2885 to one computed by setcc. */
bc6688b4 2886 if (setcc && modified_in_p (new, setcc))
48ddd46c 2887 return 0;
0e3f0221 2888 if (! validate_change (jump, &SET_SRC (set), new, 0))
bc6688b4
RS
2889 {
2890 /* When (some) constants are not valid in a comparison, and there
2891 are two registers to be replaced by constants before the entire
2892 comparison can be folded into a constant, we need to keep
2893 intermediate information in REG_EQUAL notes. For targets with
2894 separate compare insns, such notes are added by try_replace_reg.
2895 When we have a combined compare-and-branch instruction, however,
2896 we need to attach a note to the branch itself to make this
2897 optimization work. */
2898
2899 if (!rtx_equal_p (new, note_src))
2900 set_unique_reg_note (jump, REG_EQUAL, copy_rtx (new));
2901 return 0;
2902 }
2903
2904 /* Remove REG_EQUAL note after simplification. */
2905 if (note_src)
2906 remove_note (jump, note);
abd535b6 2907
7d5ab30e
JH
2908 /* If this has turned into an unconditional jump,
2909 then put a barrier after it so that the unreachable
2910 code will be deleted. */
2911 if (GET_CODE (SET_SRC (set)) == LABEL_REF)
0e3f0221 2912 emit_barrier_after (jump);
7d5ab30e 2913 }
abd535b6 2914
0e3f0221
RS
2915#ifdef HAVE_cc0
2916 /* Delete the cc0 setter. */
818b6b7f 2917 if (setcc != NULL && CC0_P (SET_DEST (single_set (setcc))))
0e3f0221
RS
2918 delete_insn (setcc);
2919#endif
2920
172890a2 2921 run_jump_opt_after_gcse = 1;
c4c81601 2922
27fb79ad 2923 global_const_prop_count++;
172890a2
RK
2924 if (gcse_file != NULL)
2925 {
2926 fprintf (gcse_file,
27fb79ad 2927 "GLOBAL CONST-PROP: Replacing reg %d in jump_insn %d with constant ",
0e3f0221 2928 REGNO (from), INSN_UID (jump));
172890a2
RK
2929 print_rtl (gcse_file, src);
2930 fprintf (gcse_file, "\n");
abd535b6 2931 }
0005550b 2932 purge_dead_edges (bb);
172890a2
RK
2933
2934 return 1;
abd535b6
BS
2935}
2936
ae860ff7 2937static bool
1d088dee 2938constprop_register (rtx insn, rtx from, rtx to, int alter_jumps)
ae860ff7
JH
2939{
2940 rtx sset;
2941
2942 /* Check for reg or cc0 setting instructions followed by
2943 conditional branch instructions first. */
2944 if (alter_jumps
2945 && (sset = single_set (insn)) != NULL
244d05fb 2946 && NEXT_INSN (insn)
ae860ff7
JH
2947 && any_condjump_p (NEXT_INSN (insn)) && onlyjump_p (NEXT_INSN (insn)))
2948 {
2949 rtx dest = SET_DEST (sset);
2950 if ((REG_P (dest) || CC0_P (dest))
2951 && cprop_jump (BLOCK_FOR_INSN (insn), insn, NEXT_INSN (insn), from, to))
2952 return 1;
2953 }
2954
2955 /* Handle normal insns next. */
4b4bf941 2956 if (NONJUMP_INSN_P (insn)
ae860ff7
JH
2957 && try_replace_reg (from, to, insn))
2958 return 1;
2959
2960 /* Try to propagate a CONST_INT into a conditional jump.
2961 We're pretty specific about what we will handle in this
2962 code, we can extend this as necessary over time.
2963
2964 Right now the insn in question must look like
2965 (set (pc) (if_then_else ...)) */
2966 else if (alter_jumps && any_condjump_p (insn) && onlyjump_p (insn))
2967 return cprop_jump (BLOCK_FOR_INSN (insn), NULL, insn, from, to);
2968 return 0;
2969}
2970
7506f491 2971/* Perform constant and copy propagation on INSN.
cc2902df 2972 The result is nonzero if a change was made. */
7506f491
DE
2973
2974static int
1d088dee 2975cprop_insn (rtx insn, int alter_jumps)
7506f491
DE
2976{
2977 struct reg_use *reg_used;
2978 int changed = 0;
833fc3ad 2979 rtx note;
7506f491 2980
9e71c818 2981 if (!INSN_P (insn))
7506f491
DE
2982 return 0;
2983
2984 reg_use_count = 0;
9e71c818 2985 note_uses (&PATTERN (insn), find_used_regs, NULL);
589005ff 2986
172890a2 2987 note = find_reg_equal_equiv_note (insn);
833fc3ad 2988
dc297297 2989 /* We may win even when propagating constants into notes. */
833fc3ad 2990 if (note)
9e71c818 2991 find_used_regs (&XEXP (note, 0), NULL);
7506f491 2992
c4c81601
RK
2993 for (reg_used = &reg_use_table[0]; reg_use_count > 0;
2994 reg_used++, reg_use_count--)
7506f491 2995 {
770ae6cc 2996 unsigned int regno = REGNO (reg_used->reg_rtx);
7506f491
DE
2997 rtx pat, src;
2998 struct expr *set;
7506f491
DE
2999
3000 /* Ignore registers created by GCSE.
dc297297 3001 We do this because ... */
7506f491
DE
3002 if (regno >= max_gcse_regno)
3003 continue;
3004
3005 /* If the register has already been set in this block, there's
3006 nothing we can do. */
3007 if (! oprs_not_set_p (reg_used->reg_rtx, insn))
3008 continue;
3009
3010 /* Find an assignment that sets reg_used and is available
3011 at the start of the block. */
3012 set = find_avail_set (regno, insn);
3013 if (! set)
3014 continue;
589005ff 3015
7506f491
DE
3016 pat = set->expr;
3017 /* ??? We might be able to handle PARALLELs. Later. */
282899df 3018 gcc_assert (GET_CODE (pat) == SET);
c4c81601 3019
7506f491
DE
3020 src = SET_SRC (pat);
3021
e78d9500 3022 /* Constant propagation. */
6b2d1c9e 3023 if (gcse_constant_p (src))
7506f491 3024 {
ae860ff7 3025 if (constprop_register (insn, reg_used->reg_rtx, src, alter_jumps))
7506f491
DE
3026 {
3027 changed = 1;
27fb79ad 3028 global_const_prop_count++;
7506f491
DE
3029 if (gcse_file != NULL)
3030 {
ae860ff7
JH
3031 fprintf (gcse_file, "GLOBAL CONST-PROP: Replacing reg %d in ", regno);
3032 fprintf (gcse_file, "insn %d with constant ", INSN_UID (insn));
e78d9500 3033 print_rtl (gcse_file, src);
7506f491
DE
3034 fprintf (gcse_file, "\n");
3035 }
bc6688b4
RS
3036 if (INSN_DELETED_P (insn))
3037 return 1;
7506f491
DE
3038 }
3039 }
7b1b4aed 3040 else if (REG_P (src)
7506f491
DE
3041 && REGNO (src) >= FIRST_PSEUDO_REGISTER
3042 && REGNO (src) != regno)
3043 {
cafba495 3044 if (try_replace_reg (reg_used->reg_rtx, src, insn))
7506f491 3045 {
cafba495 3046 changed = 1;
27fb79ad 3047 global_copy_prop_count++;
cafba495 3048 if (gcse_file != NULL)
7506f491 3049 {
ae860ff7 3050 fprintf (gcse_file, "GLOBAL COPY-PROP: Replacing reg %d in insn %d",
c4c81601
RK
3051 regno, INSN_UID (insn));
3052 fprintf (gcse_file, " with reg %d\n", REGNO (src));
7506f491 3053 }
cafba495
BS
3054
3055 /* The original insn setting reg_used may or may not now be
3056 deletable. We leave the deletion to flow. */
3057 /* FIXME: If it turns out that the insn isn't deletable,
3058 then we may have unnecessarily extended register lifetimes
3059 and made things worse. */
7506f491
DE
3060 }
3061 }
3062 }
3063
3064 return changed;
3065}
3066
710ee3ed
RH
3067/* Like find_used_regs, but avoid recording uses that appear in
3068 input-output contexts such as zero_extract or pre_dec. This
3069 restricts the cases we consider to those for which local cprop
3070 can legitimately make replacements. */
3071
3072static void
1d088dee 3073local_cprop_find_used_regs (rtx *xptr, void *data)
710ee3ed
RH
3074{
3075 rtx x = *xptr;
3076
3077 if (x == 0)
3078 return;
3079
3080 switch (GET_CODE (x))
3081 {
3082 case ZERO_EXTRACT:
3083 case SIGN_EXTRACT:
3084 case STRICT_LOW_PART:
3085 return;
3086
3087 case PRE_DEC:
3088 case PRE_INC:
3089 case POST_DEC:
3090 case POST_INC:
3091 case PRE_MODIFY:
3092 case POST_MODIFY:
3093 /* Can only legitimately appear this early in the context of
3094 stack pushes for function arguments, but handle all of the
3095 codes nonetheless. */
3096 return;
3097
3098 case SUBREG:
3099 /* Setting a subreg of a register larger than word_mode leaves
3100 the non-written words unchanged. */
3101 if (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) > BITS_PER_WORD)
3102 return;
3103 break;
3104
3105 default:
3106 break;
3107 }
3108
3109 find_used_regs (xptr, data);
3110}
1d088dee 3111
8ba46434
R
3112/* LIBCALL_SP is a zero-terminated array of insns at the end of a libcall;
3113 their REG_EQUAL notes need updating. */
e197b6fc 3114
ae860ff7 3115static bool
1d088dee 3116do_local_cprop (rtx x, rtx insn, int alter_jumps, rtx *libcall_sp)
ae860ff7
JH
3117{
3118 rtx newreg = NULL, newcnst = NULL;
3119
e197b6fc
RH
3120 /* Rule out USE instructions and ASM statements as we don't want to
3121 change the hard registers mentioned. */
7b1b4aed 3122 if (REG_P (x)
ae860ff7 3123 && (REGNO (x) >= FIRST_PSEUDO_REGISTER
e197b6fc
RH
3124 || (GET_CODE (PATTERN (insn)) != USE
3125 && asm_noperands (PATTERN (insn)) < 0)))
ae860ff7
JH
3126 {
3127 cselib_val *val = cselib_lookup (x, GET_MODE (x), 0);
3128 struct elt_loc_list *l;
3129
3130 if (!val)
3131 return false;
3132 for (l = val->locs; l; l = l->next)
3133 {
3134 rtx this_rtx = l->loc;
46690369
JH
3135 rtx note;
3136
5976e643
RS
3137 /* Don't CSE non-constant values out of libcall blocks. */
3138 if (l->in_libcall && ! CONSTANT_P (this_rtx))
9635cfad
JH
3139 continue;
3140
6b2d1c9e 3141 if (gcse_constant_p (this_rtx))
ae860ff7 3142 newcnst = this_rtx;
46690369
JH
3143 if (REG_P (this_rtx) && REGNO (this_rtx) >= FIRST_PSEUDO_REGISTER
3144 /* Don't copy propagate if it has attached REG_EQUIV note.
3145 At this point this only function parameters should have
3146 REG_EQUIV notes and if the argument slot is used somewhere
3147 explicitly, it means address of parameter has been taken,
3148 so we should not extend the lifetime of the pseudo. */
3149 && (!(note = find_reg_note (l->setting_insn, REG_EQUIV, NULL_RTX))
7b1b4aed 3150 || ! MEM_P (XEXP (note, 0))))
ae860ff7
JH
3151 newreg = this_rtx;
3152 }
3153 if (newcnst && constprop_register (insn, x, newcnst, alter_jumps))
3154 {
8ba46434 3155 /* If we find a case where we can't fix the retval REG_EQUAL notes
fbe5a4a6 3156 match the new register, we either have to abandon this replacement
8ba46434
R
3157 or fix delete_trivially_dead_insns to preserve the setting insn,
3158 or make it delete the REG_EUAQL note, and fix up all passes that
3159 require the REG_EQUAL note there. */
282899df
NS
3160 bool adjusted;
3161
3162 adjusted = adjust_libcall_notes (x, newcnst, insn, libcall_sp);
3163 gcc_assert (adjusted);
3164
ae860ff7
JH
3165 if (gcse_file != NULL)
3166 {
3167 fprintf (gcse_file, "LOCAL CONST-PROP: Replacing reg %d in ",
3168 REGNO (x));
3169 fprintf (gcse_file, "insn %d with constant ",
3170 INSN_UID (insn));
3171 print_rtl (gcse_file, newcnst);
3172 fprintf (gcse_file, "\n");
3173 }
27fb79ad 3174 local_const_prop_count++;
ae860ff7
JH
3175 return true;
3176 }
3177 else if (newreg && newreg != x && try_replace_reg (x, newreg, insn))
3178 {
8ba46434 3179 adjust_libcall_notes (x, newreg, insn, libcall_sp);
ae860ff7
JH
3180 if (gcse_file != NULL)
3181 {
3182 fprintf (gcse_file,
3183 "LOCAL COPY-PROP: Replacing reg %d in insn %d",
3184 REGNO (x), INSN_UID (insn));
3185 fprintf (gcse_file, " with reg %d\n", REGNO (newreg));
3186 }
27fb79ad 3187 local_copy_prop_count++;
ae860ff7
JH
3188 return true;
3189 }
3190 }
3191 return false;
3192}
3193
8ba46434
R
3194/* LIBCALL_SP is a zero-terminated array of insns at the end of a libcall;
3195 their REG_EQUAL notes need updating to reflect that OLDREG has been
f4e3e618
RH
3196 replaced with NEWVAL in INSN. Return true if all substitutions could
3197 be made. */
8ba46434 3198static bool
1d088dee 3199adjust_libcall_notes (rtx oldreg, rtx newval, rtx insn, rtx *libcall_sp)
8ba46434 3200{
f4e3e618 3201 rtx end;
8ba46434
R
3202
3203 while ((end = *libcall_sp++))
3204 {
f4e3e618 3205 rtx note = find_reg_equal_equiv_note (end);
8ba46434
R
3206
3207 if (! note)
3208 continue;
3209
3210 if (REG_P (newval))
3211 {
3212 if (reg_set_between_p (newval, PREV_INSN (insn), end))
3213 {
3214 do
3215 {
3216 note = find_reg_equal_equiv_note (end);
3217 if (! note)
3218 continue;
3219 if (reg_mentioned_p (newval, XEXP (note, 0)))
3220 return false;
3221 }
3222 while ((end = *libcall_sp++));
3223 return true;
3224 }
3225 }
5976e643 3226 XEXP (note, 0) = simplify_replace_rtx (XEXP (note, 0), oldreg, newval);
8ba46434
R
3227 insn = end;
3228 }
3229 return true;
3230}
3231
3232#define MAX_NESTED_LIBCALLS 9
3233
ae860ff7 3234static void
1d088dee 3235local_cprop_pass (int alter_jumps)
ae860ff7
JH
3236{
3237 rtx insn;
3238 struct reg_use *reg_used;
8ba46434 3239 rtx libcall_stack[MAX_NESTED_LIBCALLS + 1], *libcall_sp;
1649d92f 3240 bool changed = false;
ae860ff7 3241
463301c3 3242 cselib_init (false);
8ba46434
R
3243 libcall_sp = &libcall_stack[MAX_NESTED_LIBCALLS];
3244 *libcall_sp = 0;
ae860ff7
JH
3245 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
3246 {
3247 if (INSN_P (insn))
3248 {
8ba46434 3249 rtx note = find_reg_note (insn, REG_LIBCALL, NULL_RTX);
ae860ff7 3250
8ba46434
R
3251 if (note)
3252 {
282899df 3253 gcc_assert (libcall_sp != libcall_stack);
8ba46434
R
3254 *--libcall_sp = XEXP (note, 0);
3255 }
3256 note = find_reg_note (insn, REG_RETVAL, NULL_RTX);
3257 if (note)
3258 libcall_sp++;
3259 note = find_reg_equal_equiv_note (insn);
ae860ff7
JH
3260 do
3261 {
3262 reg_use_count = 0;
710ee3ed 3263 note_uses (&PATTERN (insn), local_cprop_find_used_regs, NULL);
ae860ff7 3264 if (note)
710ee3ed 3265 local_cprop_find_used_regs (&XEXP (note, 0), NULL);
ae860ff7
JH
3266
3267 for (reg_used = &reg_use_table[0]; reg_use_count > 0;
3268 reg_used++, reg_use_count--)
8ba46434
R
3269 if (do_local_cprop (reg_used->reg_rtx, insn, alter_jumps,
3270 libcall_sp))
1649d92f
JH
3271 {
3272 changed = true;
3273 break;
3274 }
bc6688b4
RS
3275 if (INSN_DELETED_P (insn))
3276 break;
ae860ff7
JH
3277 }
3278 while (reg_use_count);
3279 }
3280 cselib_process_insn (insn);
3281 }
3282 cselib_finish ();
1649d92f
JH
3283 /* Global analysis may get into infinite loops for unreachable blocks. */
3284 if (changed && alter_jumps)
5f0bea72
JH
3285 {
3286 delete_unreachable_blocks ();
3287 free_reg_set_mem ();
3288 alloc_reg_set_mem (max_reg_num ());
3289 compute_sets (get_insns ());
3290 }
ae860ff7
JH
3291}
3292
c4c81601 3293/* Forward propagate copies. This includes copies and constants. Return
cc2902df 3294 nonzero if a change was made. */
7506f491
DE
3295
3296static int
1d088dee 3297cprop (int alter_jumps)
7506f491 3298{
e0082a72
ZD
3299 int changed;
3300 basic_block bb;
7506f491
DE
3301 rtx insn;
3302
3303 /* Note we start at block 1. */
e0082a72
ZD
3304 if (ENTRY_BLOCK_PTR->next_bb == EXIT_BLOCK_PTR)
3305 {
3306 if (gcse_file != NULL)
3307 fprintf (gcse_file, "\n");
3308 return 0;
3309 }
7506f491
DE
3310
3311 changed = 0;
e0082a72 3312 FOR_BB_BETWEEN (bb, ENTRY_BLOCK_PTR->next_bb->next_bb, EXIT_BLOCK_PTR, next_bb)
7506f491
DE
3313 {
3314 /* Reset tables used to keep track of what's still valid [since the
3315 start of the block]. */
3316 reset_opr_set_tables ();
3317
a813c111
SB
3318 for (insn = BB_HEAD (bb);
3319 insn != NULL && insn != NEXT_INSN (BB_END (bb));
7506f491 3320 insn = NEXT_INSN (insn))
172890a2
RK
3321 if (INSN_P (insn))
3322 {
ae860ff7 3323 changed |= cprop_insn (insn, alter_jumps);
7506f491 3324
172890a2
RK
3325 /* Keep track of everything modified by this insn. */
3326 /* ??? Need to be careful w.r.t. mods done to INSN. Don't
3327 call mark_oprs_set if we turned the insn into a NOTE. */
7b1b4aed 3328 if (! NOTE_P (insn))
172890a2 3329 mark_oprs_set (insn);
8e42ace1 3330 }
7506f491
DE
3331 }
3332
3333 if (gcse_file != NULL)
3334 fprintf (gcse_file, "\n");
3335
3336 return changed;
3337}
3338
fbef91d8
RS
3339/* Similar to get_condition, only the resulting condition must be
3340 valid at JUMP, instead of at EARLIEST.
3341
3342 This differs from noce_get_condition in ifcvt.c in that we prefer not to
3343 settle for the condition variable in the jump instruction being integral.
3344 We prefer to be able to record the value of a user variable, rather than
3345 the value of a temporary used in a condition. This could be solved by
3346 recording the value of *every* register scaned by canonicalize_condition,
3347 but this would require some code reorganization. */
3348
2fa4a849 3349rtx
1d088dee 3350fis_get_condition (rtx jump)
fbef91d8 3351{
45d09c02 3352 return get_condition (jump, NULL, false, true);
fbef91d8
RS
3353}
3354
b0656d8b
JW
3355/* Check the comparison COND to see if we can safely form an implicit set from
3356 it. COND is either an EQ or NE comparison. */
3357
3358static bool
3359implicit_set_cond_p (rtx cond)
3360{
3361 enum machine_mode mode = GET_MODE (XEXP (cond, 0));
3362 rtx cst = XEXP (cond, 1);
3363
3364 /* We can't perform this optimization if either operand might be or might
3365 contain a signed zero. */
3366 if (HONOR_SIGNED_ZEROS (mode))
3367 {
3368 /* It is sufficient to check if CST is or contains a zero. We must
3369 handle float, complex, and vector. If any subpart is a zero, then
3370 the optimization can't be performed. */
3371 /* ??? The complex and vector checks are not implemented yet. We just
3372 always return zero for them. */
3373 if (GET_CODE (cst) == CONST_DOUBLE)
3374 {
3375 REAL_VALUE_TYPE d;
3376 REAL_VALUE_FROM_CONST_DOUBLE (d, cst);
3377 if (REAL_VALUES_EQUAL (d, dconst0))
3378 return 0;
3379 }
3380 else
3381 return 0;
3382 }
3383
3384 return gcse_constant_p (cst);
3385}
3386
fbef91d8
RS
3387/* Find the implicit sets of a function. An "implicit set" is a constraint
3388 on the value of a variable, implied by a conditional jump. For example,
3389 following "if (x == 2)", the then branch may be optimized as though the
3390 conditional performed an "explicit set", in this example, "x = 2". This
3391 function records the set patterns that are implicit at the start of each
3392 basic block. */
3393
3394static void
1d088dee 3395find_implicit_sets (void)
fbef91d8
RS
3396{
3397 basic_block bb, dest;
3398 unsigned int count;
3399 rtx cond, new;
3400
3401 count = 0;
3402 FOR_EACH_BB (bb)
a98ebe2e 3403 /* Check for more than one successor. */
628f6a4e 3404 if (EDGE_COUNT (bb->succs) > 1)
fbef91d8 3405 {
a813c111 3406 cond = fis_get_condition (BB_END (bb));
fbef91d8
RS
3407
3408 if (cond
3409 && (GET_CODE (cond) == EQ || GET_CODE (cond) == NE)
7b1b4aed 3410 && REG_P (XEXP (cond, 0))
fbef91d8 3411 && REGNO (XEXP (cond, 0)) >= FIRST_PSEUDO_REGISTER
b0656d8b 3412 && implicit_set_cond_p (cond))
fbef91d8
RS
3413 {
3414 dest = GET_CODE (cond) == EQ ? BRANCH_EDGE (bb)->dest
3415 : FALLTHRU_EDGE (bb)->dest;
3416
628f6a4e 3417 if (dest && EDGE_COUNT (dest->preds) == 1
fbef91d8
RS
3418 && dest != EXIT_BLOCK_PTR)
3419 {
3420 new = gen_rtx_SET (VOIDmode, XEXP (cond, 0),
3421 XEXP (cond, 1));
3422 implicit_sets[dest->index] = new;
3423 if (gcse_file)
3424 {
3425 fprintf(gcse_file, "Implicit set of reg %d in ",
3426 REGNO (XEXP (cond, 0)));
3427 fprintf(gcse_file, "basic block %d\n", dest->index);
3428 }
3429 count++;
3430 }
3431 }
3432 }
3433
3434 if (gcse_file)
3435 fprintf (gcse_file, "Found %d implicit sets\n", count);
3436}
3437
7506f491 3438/* Perform one copy/constant propagation pass.
a0134312
RS
3439 PASS is the pass count. If CPROP_JUMPS is true, perform constant
3440 propagation into conditional jumps. If BYPASS_JUMPS is true,
3441 perform conditional jump bypassing optimizations. */
7506f491
DE
3442
3443static int
1d088dee 3444one_cprop_pass (int pass, int cprop_jumps, int bypass_jumps)
7506f491
DE
3445{
3446 int changed = 0;
3447
27fb79ad
SB
3448 global_const_prop_count = local_const_prop_count = 0;
3449 global_copy_prop_count = local_copy_prop_count = 0;
7506f491 3450
a0134312 3451 local_cprop_pass (cprop_jumps);
ae860ff7 3452
fbef91d8 3453 /* Determine implicit sets. */
703ad42b 3454 implicit_sets = xcalloc (last_basic_block, sizeof (rtx));
fbef91d8
RS
3455 find_implicit_sets ();
3456
02280659
ZD
3457 alloc_hash_table (max_cuid, &set_hash_table, 1);
3458 compute_hash_table (&set_hash_table);
fbef91d8
RS
3459
3460 /* Free implicit_sets before peak usage. */
3461 free (implicit_sets);
3462 implicit_sets = NULL;
3463
7506f491 3464 if (gcse_file)
02280659
ZD
3465 dump_hash_table (gcse_file, "SET", &set_hash_table);
3466 if (set_hash_table.n_elems > 0)
7506f491 3467 {
02280659 3468 alloc_cprop_mem (last_basic_block, set_hash_table.n_elems);
7506f491 3469 compute_cprop_data ();
a0134312
RS
3470 changed = cprop (cprop_jumps);
3471 if (bypass_jumps)
0e3f0221 3472 changed |= bypass_conditional_jumps ();
7506f491
DE
3473 free_cprop_mem ();
3474 }
c4c81601 3475
02280659 3476 free_hash_table (&set_hash_table);
7506f491
DE
3477
3478 if (gcse_file)
3479 {
c4c81601 3480 fprintf (gcse_file, "CPROP of %s, pass %d: %d bytes needed, ",
faed5cc3 3481 current_function_name (), pass, bytes_used);
27fb79ad
SB
3482 fprintf (gcse_file, "%d local const props, %d local copy props\n\n",
3483 local_const_prop_count, local_copy_prop_count);
3484 fprintf (gcse_file, "%d global const props, %d global copy props\n\n",
3485 global_const_prop_count, global_copy_prop_count);
7506f491 3486 }
1649d92f
JH
3487 /* Global analysis may get into infinite loops for unreachable blocks. */
3488 if (changed && cprop_jumps)
3489 delete_unreachable_blocks ();
7506f491
DE
3490
3491 return changed;
3492}
3493\f
0e3f0221
RS
3494/* Bypass conditional jumps. */
3495
7821bfc7
RS
3496/* The value of last_basic_block at the beginning of the jump_bypass
3497 pass. The use of redirect_edge_and_branch_force may introduce new
3498 basic blocks, but the data flow analysis is only valid for basic
3499 block indices less than bypass_last_basic_block. */
3500
3501static int bypass_last_basic_block;
3502
0e3f0221
RS
3503/* Find a set of REGNO to a constant that is available at the end of basic
3504 block BB. Returns NULL if no such set is found. Based heavily upon
3505 find_avail_set. */
3506
3507static struct expr *
1d088dee 3508find_bypass_set (int regno, int bb)
0e3f0221
RS
3509{
3510 struct expr *result = 0;
3511
3512 for (;;)
3513 {
3514 rtx src;
ceda50e9 3515 struct expr *set = lookup_set (regno, &set_hash_table);
0e3f0221
RS
3516
3517 while (set)
3518 {
3519 if (TEST_BIT (cprop_avout[bb], set->bitmap_index))
3520 break;
3521 set = next_set (regno, set);
3522 }
3523
3524 if (set == 0)
3525 break;
3526
282899df 3527 gcc_assert (GET_CODE (set->expr) == SET);
0e3f0221
RS
3528
3529 src = SET_SRC (set->expr);
6b2d1c9e 3530 if (gcse_constant_p (src))
0e3f0221
RS
3531 result = set;
3532
7b1b4aed 3533 if (! REG_P (src))
0e3f0221
RS
3534 break;
3535
3536 regno = REGNO (src);
3537 }
3538 return result;
3539}
3540
3541
e129b3f9
RS
3542/* Subroutine of bypass_block that checks whether a pseudo is killed by
3543 any of the instructions inserted on an edge. Jump bypassing places
3544 condition code setters on CFG edges using insert_insn_on_edge. This
3545 function is required to check that our data flow analysis is still
3546 valid prior to commit_edge_insertions. */
3547
3548static bool
1d088dee 3549reg_killed_on_edge (rtx reg, edge e)
e129b3f9
RS
3550{
3551 rtx insn;
3552
6de9cd9a 3553 for (insn = e->insns.r; insn; insn = NEXT_INSN (insn))
e129b3f9
RS
3554 if (INSN_P (insn) && reg_set_p (reg, insn))
3555 return true;
3556
3557 return false;
3558}
3559
0e3f0221
RS
3560/* Subroutine of bypass_conditional_jumps that attempts to bypass the given
3561 basic block BB which has more than one predecessor. If not NULL, SETCC
3562 is the first instruction of BB, which is immediately followed by JUMP_INSN
3563 JUMP. Otherwise, SETCC is NULL, and JUMP is the first insn of BB.
e129b3f9
RS
3564 Returns nonzero if a change was made.
3565
e0bb17a8 3566 During the jump bypassing pass, we may place copies of SETCC instructions
e129b3f9
RS
3567 on CFG edges. The following routine must be careful to pay attention to
3568 these inserted insns when performing its transformations. */
0e3f0221
RS
3569
3570static int
1d088dee 3571bypass_block (basic_block bb, rtx setcc, rtx jump)
0e3f0221
RS
3572{
3573 rtx insn, note;
628f6a4e 3574 edge e, edest;
818b6b7f 3575 int i, change;
72b8d451 3576 int may_be_loop_header;
628f6a4e
BE
3577 unsigned removed_p;
3578 edge_iterator ei;
0e3f0221
RS
3579
3580 insn = (setcc != NULL) ? setcc : jump;
3581
3582 /* Determine set of register uses in INSN. */
3583 reg_use_count = 0;
3584 note_uses (&PATTERN (insn), find_used_regs, NULL);
3585 note = find_reg_equal_equiv_note (insn);
3586 if (note)
3587 find_used_regs (&XEXP (note, 0), NULL);
3588
72b8d451 3589 may_be_loop_header = false;
628f6a4e 3590 FOR_EACH_EDGE (e, ei, bb->preds)
72b8d451
ZD
3591 if (e->flags & EDGE_DFS_BACK)
3592 {
3593 may_be_loop_header = true;
3594 break;
3595 }
3596
0e3f0221 3597 change = 0;
628f6a4e 3598 for (ei = ei_start (bb->preds); (e = ei_safe_edge (ei)); )
0e3f0221 3599 {
628f6a4e
BE
3600 removed_p = 0;
3601
7821bfc7 3602 if (e->flags & EDGE_COMPLEX)
628f6a4e
BE
3603 {
3604 ei_next (&ei);
3605 continue;
3606 }
7821bfc7
RS
3607
3608 /* We can't redirect edges from new basic blocks. */
3609 if (e->src->index >= bypass_last_basic_block)
628f6a4e
BE
3610 {
3611 ei_next (&ei);
3612 continue;
3613 }
7821bfc7 3614
72b8d451 3615 /* The irreducible loops created by redirecting of edges entering the
e0bb17a8
KH
3616 loop from outside would decrease effectiveness of some of the following
3617 optimizations, so prevent this. */
72b8d451
ZD
3618 if (may_be_loop_header
3619 && !(e->flags & EDGE_DFS_BACK))
628f6a4e
BE
3620 {
3621 ei_next (&ei);
3622 continue;
3623 }
72b8d451 3624
0e3f0221
RS
3625 for (i = 0; i < reg_use_count; i++)
3626 {
3627 struct reg_use *reg_used = &reg_use_table[i];
589005ff 3628 unsigned int regno = REGNO (reg_used->reg_rtx);
818b6b7f 3629 basic_block dest, old_dest;
589005ff
KH
3630 struct expr *set;
3631 rtx src, new;
0e3f0221 3632
589005ff
KH
3633 if (regno >= max_gcse_regno)
3634 continue;
0e3f0221 3635
589005ff 3636 set = find_bypass_set (regno, e->src->index);
0e3f0221
RS
3637
3638 if (! set)
3639 continue;
3640
e129b3f9 3641 /* Check the data flow is valid after edge insertions. */
6de9cd9a 3642 if (e->insns.r && reg_killed_on_edge (reg_used->reg_rtx, e))
e129b3f9
RS
3643 continue;
3644
589005ff 3645 src = SET_SRC (pc_set (jump));
0e3f0221
RS
3646
3647 if (setcc != NULL)
3648 src = simplify_replace_rtx (src,
589005ff
KH
3649 SET_DEST (PATTERN (setcc)),
3650 SET_SRC (PATTERN (setcc)));
0e3f0221
RS
3651
3652 new = simplify_replace_rtx (src, reg_used->reg_rtx,
589005ff 3653 SET_SRC (set->expr));
0e3f0221 3654
1d088dee 3655 /* Jump bypassing may have already placed instructions on
e129b3f9
RS
3656 edges of the CFG. We can't bypass an outgoing edge that
3657 has instructions associated with it, as these insns won't
3658 get executed if the incoming edge is redirected. */
3659
589005ff 3660 if (new == pc_rtx)
e129b3f9
RS
3661 {
3662 edest = FALLTHRU_EDGE (bb);
6de9cd9a 3663 dest = edest->insns.r ? NULL : edest->dest;
e129b3f9 3664 }
0e3f0221 3665 else if (GET_CODE (new) == LABEL_REF)
e129b3f9 3666 {
628f6a4e
BE
3667 edge_iterator ei2;
3668
e129b3f9
RS
3669 dest = BLOCK_FOR_INSN (XEXP (new, 0));
3670 /* Don't bypass edges containing instructions. */
628f6a4e 3671 FOR_EACH_EDGE (edest, ei2, bb->succs)
6de9cd9a 3672 if (edest->dest == dest && edest->insns.r)
e129b3f9
RS
3673 {
3674 dest = NULL;
3675 break;
3676 }
3677 }
0e3f0221
RS
3678 else
3679 dest = NULL;
3680
a544524a
JH
3681 /* Avoid unification of the edge with other edges from original
3682 branch. We would end up emitting the instruction on "both"
3683 edges. */
7b1b4aed 3684
f0cad2d5 3685 if (dest && setcc && !CC0_P (SET_DEST (PATTERN (setcc))))
a544524a
JH
3686 {
3687 edge e2;
628f6a4e
BE
3688 edge_iterator ei2;
3689
3690 FOR_EACH_EDGE (e2, ei2, e->src->succs)
a544524a
JH
3691 if (e2->dest == dest)
3692 {
3693 dest = NULL;
3694 break;
3695 }
3696 }
3697
818b6b7f 3698 old_dest = e->dest;
7821bfc7
RS
3699 if (dest != NULL
3700 && dest != old_dest
3701 && dest != EXIT_BLOCK_PTR)
3702 {
3703 redirect_edge_and_branch_force (e, dest);
3704
818b6b7f 3705 /* Copy the register setter to the redirected edge.
0e3f0221
RS
3706 Don't copy CC0 setters, as CC0 is dead after jump. */
3707 if (setcc)
3708 {
3709 rtx pat = PATTERN (setcc);
818b6b7f 3710 if (!CC0_P (SET_DEST (pat)))
0e3f0221
RS
3711 insert_insn_on_edge (copy_insn (pat), e);
3712 }
3713
3714 if (gcse_file != NULL)
3715 {
27fb79ad
SB
3716 fprintf (gcse_file, "JUMP-BYPASS: Proved reg %d "
3717 "in jump_insn %d equals constant ",
818b6b7f 3718 regno, INSN_UID (jump));
0e3f0221
RS
3719 print_rtl (gcse_file, SET_SRC (set->expr));
3720 fprintf (gcse_file, "\nBypass edge from %d->%d to %d\n",
818b6b7f 3721 e->src->index, old_dest->index, dest->index);
0e3f0221
RS
3722 }
3723 change = 1;
628f6a4e 3724 removed_p = 1;
0e3f0221
RS
3725 break;
3726 }
3727 }
628f6a4e
BE
3728 if (!removed_p)
3729 ei_next (&ei);
0e3f0221
RS
3730 }
3731 return change;
3732}
3733
3734/* Find basic blocks with more than one predecessor that only contain a
3735 single conditional jump. If the result of the comparison is known at
3736 compile-time from any incoming edge, redirect that edge to the
9a71ece1
RH
3737 appropriate target. Returns nonzero if a change was made.
3738
3739 This function is now mis-named, because we also handle indirect jumps. */
0e3f0221
RS
3740
3741static int
1d088dee 3742bypass_conditional_jumps (void)
0e3f0221
RS
3743{
3744 basic_block bb;
3745 int changed;
3746 rtx setcc;
3747 rtx insn;
3748 rtx dest;
3749
3750 /* Note we start at block 1. */
3751 if (ENTRY_BLOCK_PTR->next_bb == EXIT_BLOCK_PTR)
3752 return 0;
3753
7821bfc7 3754 bypass_last_basic_block = last_basic_block;
72b8d451 3755 mark_dfs_back_edges ();
7821bfc7 3756
0e3f0221
RS
3757 changed = 0;
3758 FOR_BB_BETWEEN (bb, ENTRY_BLOCK_PTR->next_bb->next_bb,
589005ff 3759 EXIT_BLOCK_PTR, next_bb)
0e3f0221
RS
3760 {
3761 /* Check for more than one predecessor. */
628f6a4e 3762 if (EDGE_COUNT (bb->preds) > 1)
0e3f0221
RS
3763 {
3764 setcc = NULL_RTX;
a813c111
SB
3765 for (insn = BB_HEAD (bb);
3766 insn != NULL && insn != NEXT_INSN (BB_END (bb));
0e3f0221 3767 insn = NEXT_INSN (insn))
4b4bf941 3768 if (NONJUMP_INSN_P (insn))
0e3f0221 3769 {
9543a9d2 3770 if (setcc)
0e3f0221 3771 break;
ba4f7968 3772 if (GET_CODE (PATTERN (insn)) != SET)
0e3f0221
RS
3773 break;
3774
ba4f7968 3775 dest = SET_DEST (PATTERN (insn));
818b6b7f 3776 if (REG_P (dest) || CC0_P (dest))
0e3f0221 3777 setcc = insn;
0e3f0221
RS
3778 else
3779 break;
3780 }
7b1b4aed 3781 else if (JUMP_P (insn))
0e3f0221 3782 {
9a71ece1
RH
3783 if ((any_condjump_p (insn) || computed_jump_p (insn))
3784 && onlyjump_p (insn))
0e3f0221
RS
3785 changed |= bypass_block (bb, setcc, insn);
3786 break;
3787 }
3788 else if (INSN_P (insn))
3789 break;
3790 }
3791 }
3792
818b6b7f 3793 /* If we bypassed any register setting insns, we inserted a
fbe5a4a6 3794 copy on the redirected edge. These need to be committed. */
0e3f0221
RS
3795 if (changed)
3796 commit_edge_insertions();
3797
3798 return changed;
3799}
3800\f
a65f3558 3801/* Compute PRE+LCM working variables. */
7506f491
DE
3802
3803/* Local properties of expressions. */
3804/* Nonzero for expressions that are transparent in the block. */
a65f3558 3805static sbitmap *transp;
7506f491 3806
5c35539b
RH
3807/* Nonzero for expressions that are transparent at the end of the block.
3808 This is only zero for expressions killed by abnormal critical edge
3809 created by a calls. */
a65f3558 3810static sbitmap *transpout;
5c35539b 3811
a65f3558
JL
3812/* Nonzero for expressions that are computed (available) in the block. */
3813static sbitmap *comp;
7506f491 3814
a65f3558
JL
3815/* Nonzero for expressions that are locally anticipatable in the block. */
3816static sbitmap *antloc;
7506f491 3817
a65f3558
JL
3818/* Nonzero for expressions where this block is an optimal computation
3819 point. */
3820static sbitmap *pre_optimal;
5c35539b 3821
a65f3558
JL
3822/* Nonzero for expressions which are redundant in a particular block. */
3823static sbitmap *pre_redundant;
7506f491 3824
a42cd965
AM
3825/* Nonzero for expressions which should be inserted on a specific edge. */
3826static sbitmap *pre_insert_map;
3827
3828/* Nonzero for expressions which should be deleted in a specific block. */
3829static sbitmap *pre_delete_map;
3830
3831/* Contains the edge_list returned by pre_edge_lcm. */
3832static struct edge_list *edge_list;
3833
a65f3558
JL
3834/* Redundant insns. */
3835static sbitmap pre_redundant_insns;
7506f491 3836
a65f3558 3837/* Allocate vars used for PRE analysis. */
7506f491
DE
3838
3839static void
1d088dee 3840alloc_pre_mem (int n_blocks, int n_exprs)
7506f491 3841{
a65f3558
JL
3842 transp = sbitmap_vector_alloc (n_blocks, n_exprs);
3843 comp = sbitmap_vector_alloc (n_blocks, n_exprs);
3844 antloc = sbitmap_vector_alloc (n_blocks, n_exprs);
5faf03ae 3845
a42cd965
AM
3846 pre_optimal = NULL;
3847 pre_redundant = NULL;
3848 pre_insert_map = NULL;
3849 pre_delete_map = NULL;
a42cd965 3850 ae_kill = sbitmap_vector_alloc (n_blocks, n_exprs);
c4c81601 3851
a42cd965 3852 /* pre_insert and pre_delete are allocated later. */
7506f491
DE
3853}
3854
a65f3558 3855/* Free vars used for PRE analysis. */
7506f491
DE
3856
3857static void
1d088dee 3858free_pre_mem (void)
7506f491 3859{
5a660bff
DB
3860 sbitmap_vector_free (transp);
3861 sbitmap_vector_free (comp);
bd3675fc
JL
3862
3863 /* ANTLOC and AE_KILL are freed just after pre_lcm finishes. */
7506f491 3864
a42cd965 3865 if (pre_optimal)
5a660bff 3866 sbitmap_vector_free (pre_optimal);
a42cd965 3867 if (pre_redundant)
5a660bff 3868 sbitmap_vector_free (pre_redundant);
a42cd965 3869 if (pre_insert_map)
5a660bff 3870 sbitmap_vector_free (pre_insert_map);
a42cd965 3871 if (pre_delete_map)
5a660bff 3872 sbitmap_vector_free (pre_delete_map);
a42cd965 3873
bd3675fc 3874 transp = comp = NULL;
a42cd965 3875 pre_optimal = pre_redundant = pre_insert_map = pre_delete_map = NULL;
7506f491
DE
3876}
3877
3878/* Top level routine to do the dataflow analysis needed by PRE. */
3879
3880static void
1d088dee 3881compute_pre_data (void)
7506f491 3882{
b614171e 3883 sbitmap trapping_expr;
e0082a72 3884 basic_block bb;
b614171e 3885 unsigned int ui;
c66e8ae9 3886
02280659 3887 compute_local_properties (transp, comp, antloc, &expr_hash_table);
d55bc081 3888 sbitmap_vector_zero (ae_kill, last_basic_block);
c66e8ae9 3889
b614171e 3890 /* Collect expressions which might trap. */
02280659 3891 trapping_expr = sbitmap_alloc (expr_hash_table.n_elems);
b614171e 3892 sbitmap_zero (trapping_expr);
02280659 3893 for (ui = 0; ui < expr_hash_table.size; ui++)
b614171e
MM
3894 {
3895 struct expr *e;
02280659 3896 for (e = expr_hash_table.table[ui]; e != NULL; e = e->next_same_hash)
b614171e
MM
3897 if (may_trap_p (e->expr))
3898 SET_BIT (trapping_expr, e->bitmap_index);
3899 }
3900
c66e8ae9
JL
3901 /* Compute ae_kill for each basic block using:
3902
3903 ~(TRANSP | COMP)
e83f4801 3904 */
c66e8ae9 3905
e0082a72 3906 FOR_EACH_BB (bb)
c66e8ae9 3907 {
b614171e 3908 edge e;
628f6a4e 3909 edge_iterator ei;
b614171e
MM
3910
3911 /* If the current block is the destination of an abnormal edge, we
3912 kill all trapping expressions because we won't be able to properly
3913 place the instruction on the edge. So make them neither
3914 anticipatable nor transparent. This is fairly conservative. */
628f6a4e 3915 FOR_EACH_EDGE (e, ei, bb->preds)
b614171e
MM
3916 if (e->flags & EDGE_ABNORMAL)
3917 {
e0082a72
ZD
3918 sbitmap_difference (antloc[bb->index], antloc[bb->index], trapping_expr);
3919 sbitmap_difference (transp[bb->index], transp[bb->index], trapping_expr);
b614171e
MM
3920 break;
3921 }
3922
e0082a72
ZD
3923 sbitmap_a_or_b (ae_kill[bb->index], transp[bb->index], comp[bb->index]);
3924 sbitmap_not (ae_kill[bb->index], ae_kill[bb->index]);
c66e8ae9
JL
3925 }
3926
02280659 3927 edge_list = pre_edge_lcm (gcse_file, expr_hash_table.n_elems, transp, comp, antloc,
a42cd965 3928 ae_kill, &pre_insert_map, &pre_delete_map);
5a660bff 3929 sbitmap_vector_free (antloc);
bd3675fc 3930 antloc = NULL;
5a660bff 3931 sbitmap_vector_free (ae_kill);
589005ff 3932 ae_kill = NULL;
76ac938b 3933 sbitmap_free (trapping_expr);
7506f491
DE
3934}
3935\f
3936/* PRE utilities */
3937
cc2902df 3938/* Return nonzero if an occurrence of expression EXPR in OCCR_BB would reach
a65f3558 3939 block BB.
7506f491
DE
3940
3941 VISITED is a pointer to a working buffer for tracking which BB's have
3942 been visited. It is NULL for the top-level call.
3943
3944 We treat reaching expressions that go through blocks containing the same
3945 reaching expression as "not reaching". E.g. if EXPR is generated in blocks
3946 2 and 3, INSN is in block 4, and 2->3->4, we treat the expression in block
3947 2 as not reaching. The intent is to improve the probability of finding
3948 only one reaching expression and to reduce register lifetimes by picking
3949 the closest such expression. */
3950
3951static int
1d088dee 3952pre_expr_reaches_here_p_work (basic_block occr_bb, struct expr *expr, basic_block bb, char *visited)
7506f491 3953{
36349f8b 3954 edge pred;
628f6a4e
BE
3955 edge_iterator ei;
3956
3957 FOR_EACH_EDGE (pred, ei, bb->preds)
7506f491 3958 {
e2d2ed72 3959 basic_block pred_bb = pred->src;
7506f491 3960
36349f8b 3961 if (pred->src == ENTRY_BLOCK_PTR
7506f491 3962 /* Has predecessor has already been visited? */
0b17ab2f 3963 || visited[pred_bb->index])
c4c81601
RK
3964 ;/* Nothing to do. */
3965
7506f491 3966 /* Does this predecessor generate this expression? */
0b17ab2f 3967 else if (TEST_BIT (comp[pred_bb->index], expr->bitmap_index))
7506f491
DE
3968 {
3969 /* Is this the occurrence we're looking for?
3970 Note that there's only one generating occurrence per block
3971 so we just need to check the block number. */
a65f3558 3972 if (occr_bb == pred_bb)
7506f491 3973 return 1;
c4c81601 3974
0b17ab2f 3975 visited[pred_bb->index] = 1;
7506f491
DE
3976 }
3977 /* Ignore this predecessor if it kills the expression. */
0b17ab2f
RH
3978 else if (! TEST_BIT (transp[pred_bb->index], expr->bitmap_index))
3979 visited[pred_bb->index] = 1;
c4c81601 3980
7506f491
DE
3981 /* Neither gen nor kill. */
3982 else
ac7c5af5 3983 {
0b17ab2f 3984 visited[pred_bb->index] = 1;
89e606c9 3985 if (pre_expr_reaches_here_p_work (occr_bb, expr, pred_bb, visited))
7506f491 3986 return 1;
ac7c5af5 3987 }
7506f491
DE
3988 }
3989
3990 /* All paths have been checked. */
3991 return 0;
3992}
283a2545
RL
3993
3994/* The wrapper for pre_expr_reaches_here_work that ensures that any
dc297297 3995 memory allocated for that function is returned. */
283a2545
RL
3996
3997static int
1d088dee 3998pre_expr_reaches_here_p (basic_block occr_bb, struct expr *expr, basic_block bb)
283a2545
RL
3999{
4000 int rval;
703ad42b 4001 char *visited = xcalloc (last_basic_block, 1);
283a2545 4002
8e42ace1 4003 rval = pre_expr_reaches_here_p_work (occr_bb, expr, bb, visited);
283a2545
RL
4004
4005 free (visited);
c4c81601 4006 return rval;
283a2545 4007}
7506f491 4008\f
a42cd965
AM
4009
4010/* Given an expr, generate RTL which we can insert at the end of a BB,
589005ff 4011 or on an edge. Set the block number of any insns generated to
a42cd965
AM
4012 the value of BB. */
4013
4014static rtx
1d088dee 4015process_insert_insn (struct expr *expr)
a42cd965
AM
4016{
4017 rtx reg = expr->reaching_reg;
fb0c0a12
RK
4018 rtx exp = copy_rtx (expr->expr);
4019 rtx pat;
a42cd965
AM
4020
4021 start_sequence ();
fb0c0a12
RK
4022
4023 /* If the expression is something that's an operand, like a constant,
4024 just copy it to a register. */
4025 if (general_operand (exp, GET_MODE (reg)))
4026 emit_move_insn (reg, exp);
4027
4028 /* Otherwise, make a new insn to compute this expression and make sure the
4029 insn will be recognized (this also adds any needed CLOBBERs). Copy the
4030 expression to make sure we don't have any sharing issues. */
282899df
NS
4031 else
4032 {
4033 rtx insn = emit_insn (gen_rtx_SET (VOIDmode, reg, exp));
4034
2f021b67
AP
4035 if (insn_invalid_p (insn))
4036 gcc_unreachable ();
282899df
NS
4037 }
4038
589005ff 4039
2f937369 4040 pat = get_insns ();
a42cd965
AM
4041 end_sequence ();
4042
4043 return pat;
4044}
589005ff 4045
a65f3558
JL
4046/* Add EXPR to the end of basic block BB.
4047
4048 This is used by both the PRE and code hoisting.
4049
4050 For PRE, we want to verify that the expr is either transparent
4051 or locally anticipatable in the target block. This check makes
4052 no sense for code hoisting. */
7506f491
DE
4053
4054static void
1d088dee 4055insert_insn_end_bb (struct expr *expr, basic_block bb, int pre)
7506f491 4056{
a813c111 4057 rtx insn = BB_END (bb);
7506f491
DE
4058 rtx new_insn;
4059 rtx reg = expr->reaching_reg;
4060 int regno = REGNO (reg);
2f937369 4061 rtx pat, pat_end;
7506f491 4062
a42cd965 4063 pat = process_insert_insn (expr);
282899df 4064 gcc_assert (pat && INSN_P (pat));
2f937369
DM
4065
4066 pat_end = pat;
4067 while (NEXT_INSN (pat_end) != NULL_RTX)
4068 pat_end = NEXT_INSN (pat_end);
7506f491
DE
4069
4070 /* If the last insn is a jump, insert EXPR in front [taking care to
4d6922ee 4071 handle cc0, etc. properly]. Similarly we need to care trapping
068473ec 4072 instructions in presence of non-call exceptions. */
7506f491 4073
7b1b4aed 4074 if (JUMP_P (insn)
4b4bf941 4075 || (NONJUMP_INSN_P (insn)
628f6a4e
BE
4076 && (EDGE_COUNT (bb->succs) > 1
4077 || EDGE_SUCC (bb, 0)->flags & EDGE_ABNORMAL)))
7506f491 4078 {
50b2596f 4079#ifdef HAVE_cc0
7506f491 4080 rtx note;
50b2596f 4081#endif
068473ec
JH
4082 /* It should always be the case that we can put these instructions
4083 anywhere in the basic block with performing PRE optimizations.
4084 Check this. */
282899df
NS
4085 gcc_assert (!NONJUMP_INSN_P (insn) || !pre
4086 || TEST_BIT (antloc[bb->index], expr->bitmap_index)
4087 || TEST_BIT (transp[bb->index], expr->bitmap_index));
7506f491
DE
4088
4089 /* If this is a jump table, then we can't insert stuff here. Since
4090 we know the previous real insn must be the tablejump, we insert
4091 the new instruction just before the tablejump. */
4092 if (GET_CODE (PATTERN (insn)) == ADDR_VEC
4093 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC)
4094 insn = prev_real_insn (insn);
4095
4096#ifdef HAVE_cc0
4097 /* FIXME: 'twould be nice to call prev_cc0_setter here but it aborts
4098 if cc0 isn't set. */
4099 note = find_reg_note (insn, REG_CC_SETTER, NULL_RTX);
4100 if (note)
4101 insn = XEXP (note, 0);
4102 else
4103 {
4104 rtx maybe_cc0_setter = prev_nonnote_insn (insn);
4105 if (maybe_cc0_setter
2c3c49de 4106 && INSN_P (maybe_cc0_setter)
7506f491
DE
4107 && sets_cc0_p (PATTERN (maybe_cc0_setter)))
4108 insn = maybe_cc0_setter;
4109 }
4110#endif
4111 /* FIXME: What if something in cc0/jump uses value set in new insn? */
a7102479 4112 new_insn = emit_insn_before_noloc (pat, insn);
3947e2f9 4113 }
c4c81601 4114
3947e2f9
RH
4115 /* Likewise if the last insn is a call, as will happen in the presence
4116 of exception handling. */
7b1b4aed 4117 else if (CALL_P (insn)
628f6a4e 4118 && (EDGE_COUNT (bb->succs) > 1 || EDGE_SUCC (bb, 0)->flags & EDGE_ABNORMAL))
3947e2f9 4119 {
3947e2f9
RH
4120 /* Keeping in mind SMALL_REGISTER_CLASSES and parameters in registers,
4121 we search backward and place the instructions before the first
4122 parameter is loaded. Do this for everyone for consistency and a
fbe5a4a6 4123 presumption that we'll get better code elsewhere as well.
3947e2f9 4124
c4c81601 4125 It should always be the case that we can put these instructions
a65f3558
JL
4126 anywhere in the basic block with performing PRE optimizations.
4127 Check this. */
c4c81601 4128
282899df
NS
4129 gcc_assert (!pre
4130 || TEST_BIT (antloc[bb->index], expr->bitmap_index)
4131 || TEST_BIT (transp[bb->index], expr->bitmap_index));
3947e2f9
RH
4132
4133 /* Since different machines initialize their parameter registers
4134 in different orders, assume nothing. Collect the set of all
4135 parameter registers. */
a813c111 4136 insn = find_first_parameter_load (insn, BB_HEAD (bb));
3947e2f9 4137
b1d26727
JL
4138 /* If we found all the parameter loads, then we want to insert
4139 before the first parameter load.
4140
4141 If we did not find all the parameter loads, then we might have
4142 stopped on the head of the block, which could be a CODE_LABEL.
4143 If we inserted before the CODE_LABEL, then we would be putting
4144 the insn in the wrong basic block. In that case, put the insn
b5229628 4145 after the CODE_LABEL. Also, respect NOTE_INSN_BASIC_BLOCK. */
7b1b4aed 4146 while (LABEL_P (insn)
589ca5cb 4147 || NOTE_INSN_BASIC_BLOCK_P (insn))
b5229628 4148 insn = NEXT_INSN (insn);
c4c81601 4149
a7102479 4150 new_insn = emit_insn_before_noloc (pat, insn);
7506f491
DE
4151 }
4152 else
a7102479 4153 new_insn = emit_insn_after_noloc (pat, insn);
7506f491 4154
2f937369 4155 while (1)
a65f3558 4156 {
2f937369 4157 if (INSN_P (pat))
a65f3558 4158 {
2f937369
DM
4159 add_label_notes (PATTERN (pat), new_insn);
4160 note_stores (PATTERN (pat), record_set_info, pat);
a65f3558 4161 }
2f937369
DM
4162 if (pat == pat_end)
4163 break;
4164 pat = NEXT_INSN (pat);
a65f3558 4165 }
3947e2f9 4166
7506f491
DE
4167 gcse_create_count++;
4168
4169 if (gcse_file)
4170 {
c4c81601 4171 fprintf (gcse_file, "PRE/HOIST: end of bb %d, insn %d, ",
0b17ab2f 4172 bb->index, INSN_UID (new_insn));
c4c81601
RK
4173 fprintf (gcse_file, "copying expression %d to reg %d\n",
4174 expr->bitmap_index, regno);
7506f491
DE
4175 }
4176}
4177
a42cd965
AM
4178/* Insert partially redundant expressions on edges in the CFG to make
4179 the expressions fully redundant. */
7506f491 4180
a42cd965 4181static int
1d088dee 4182pre_edge_insert (struct edge_list *edge_list, struct expr **index_map)
7506f491 4183{
c4c81601 4184 int e, i, j, num_edges, set_size, did_insert = 0;
a65f3558
JL
4185 sbitmap *inserted;
4186
a42cd965
AM
4187 /* Where PRE_INSERT_MAP is nonzero, we add the expression on that edge
4188 if it reaches any of the deleted expressions. */
7506f491 4189
a42cd965
AM
4190 set_size = pre_insert_map[0]->size;
4191 num_edges = NUM_EDGES (edge_list);
02280659 4192 inserted = sbitmap_vector_alloc (num_edges, expr_hash_table.n_elems);
a42cd965 4193 sbitmap_vector_zero (inserted, num_edges);
7506f491 4194
a42cd965 4195 for (e = 0; e < num_edges; e++)
7506f491
DE
4196 {
4197 int indx;
e2d2ed72 4198 basic_block bb = INDEX_EDGE_PRED_BB (edge_list, e);
a65f3558 4199
a65f3558 4200 for (i = indx = 0; i < set_size; i++, indx += SBITMAP_ELT_BITS)
7506f491 4201 {
a42cd965 4202 SBITMAP_ELT_TYPE insert = pre_insert_map[e]->elms[i];
7506f491 4203
02280659 4204 for (j = indx; insert && j < (int) expr_hash_table.n_elems; j++, insert >>= 1)
c4c81601
RK
4205 if ((insert & 1) != 0 && index_map[j]->reaching_reg != NULL_RTX)
4206 {
4207 struct expr *expr = index_map[j];
4208 struct occr *occr;
a65f3558 4209
ff7cc307 4210 /* Now look at each deleted occurrence of this expression. */
c4c81601
RK
4211 for (occr = expr->antic_occr; occr != NULL; occr = occr->next)
4212 {
4213 if (! occr->deleted_p)
4214 continue;
4215
4216 /* Insert this expression on this edge if if it would
ff7cc307 4217 reach the deleted occurrence in BB. */
c4c81601
RK
4218 if (!TEST_BIT (inserted[e], j))
4219 {
4220 rtx insn;
4221 edge eg = INDEX_EDGE (edge_list, e);
4222
4223 /* We can't insert anything on an abnormal and
4224 critical edge, so we insert the insn at the end of
4225 the previous block. There are several alternatives
4226 detailed in Morgans book P277 (sec 10.5) for
4227 handling this situation. This one is easiest for
4228 now. */
4229
4230 if ((eg->flags & EDGE_ABNORMAL) == EDGE_ABNORMAL)
4231 insert_insn_end_bb (index_map[j], bb, 0);
4232 else
4233 {
4234 insn = process_insert_insn (index_map[j]);
4235 insert_insn_on_edge (insn, eg);
4236 }
4237
4238 if (gcse_file)
4239 {
4240 fprintf (gcse_file, "PRE/HOIST: edge (%d,%d), ",
0b17ab2f
RH
4241 bb->index,
4242 INDEX_EDGE_SUCC_BB (edge_list, e)->index);
c4c81601
RK
4243 fprintf (gcse_file, "copy expression %d\n",
4244 expr->bitmap_index);
4245 }
4246
a13d4ebf 4247 update_ld_motion_stores (expr);
c4c81601
RK
4248 SET_BIT (inserted[e], j);
4249 did_insert = 1;
4250 gcse_create_count++;
4251 }
4252 }
4253 }
7506f491
DE
4254 }
4255 }
5faf03ae 4256
5a660bff 4257 sbitmap_vector_free (inserted);
a42cd965 4258 return did_insert;
7506f491
DE
4259}
4260
073089a7 4261/* Copy the result of EXPR->EXPR generated by INSN to EXPR->REACHING_REG.
b885908b
MH
4262 Given "old_reg <- expr" (INSN), instead of adding after it
4263 reaching_reg <- old_reg
4264 it's better to do the following:
4265 reaching_reg <- expr
4266 old_reg <- reaching_reg
4267 because this way copy propagation can discover additional PRE
f5f2e3cd
MH
4268 opportunities. But if this fails, we try the old way.
4269 When "expr" is a store, i.e.
4270 given "MEM <- old_reg", instead of adding after it
4271 reaching_reg <- old_reg
4272 it's better to add it before as follows:
4273 reaching_reg <- old_reg
4274 MEM <- reaching_reg. */
7506f491
DE
4275
4276static void
1d088dee 4277pre_insert_copy_insn (struct expr *expr, rtx insn)
7506f491
DE
4278{
4279 rtx reg = expr->reaching_reg;
4280 int regno = REGNO (reg);
4281 int indx = expr->bitmap_index;
073089a7
RS
4282 rtx pat = PATTERN (insn);
4283 rtx set, new_insn;
b885908b 4284 rtx old_reg;
073089a7 4285 int i;
7506f491 4286
073089a7 4287 /* This block matches the logic in hash_scan_insn. */
282899df 4288 switch (GET_CODE (pat))
073089a7 4289 {
282899df
NS
4290 case SET:
4291 set = pat;
4292 break;
4293
4294 case PARALLEL:
073089a7
RS
4295 /* Search through the parallel looking for the set whose
4296 source was the expression that we're interested in. */
4297 set = NULL_RTX;
4298 for (i = 0; i < XVECLEN (pat, 0); i++)
4299 {
4300 rtx x = XVECEXP (pat, 0, i);
4301 if (GET_CODE (x) == SET
4302 && expr_equiv_p (SET_SRC (x), expr->expr))
4303 {
4304 set = x;
4305 break;
4306 }
4307 }
282899df
NS
4308 break;
4309
4310 default:
4311 gcc_unreachable ();
073089a7 4312 }
c4c81601 4313
7b1b4aed 4314 if (REG_P (SET_DEST (set)))
073089a7 4315 {
f5f2e3cd
MH
4316 old_reg = SET_DEST (set);
4317 /* Check if we can modify the set destination in the original insn. */
4318 if (validate_change (insn, &SET_DEST (set), reg, 0))
4319 {
4320 new_insn = gen_move_insn (old_reg, reg);
4321 new_insn = emit_insn_after (new_insn, insn);
4322
4323 /* Keep register set table up to date. */
4324 replace_one_set (REGNO (old_reg), insn, new_insn);
4325 record_one_set (regno, insn);
4326 }
4327 else
4328 {
4329 new_insn = gen_move_insn (reg, old_reg);
4330 new_insn = emit_insn_after (new_insn, insn);
073089a7 4331
f5f2e3cd
MH
4332 /* Keep register set table up to date. */
4333 record_one_set (regno, new_insn);
4334 }
073089a7 4335 }
f5f2e3cd 4336 else /* This is possible only in case of a store to memory. */
073089a7 4337 {
f5f2e3cd 4338 old_reg = SET_SRC (set);
073089a7 4339 new_insn = gen_move_insn (reg, old_reg);
f5f2e3cd
MH
4340
4341 /* Check if we can modify the set source in the original insn. */
4342 if (validate_change (insn, &SET_SRC (set), reg, 0))
4343 new_insn = emit_insn_before (new_insn, insn);
4344 else
4345 new_insn = emit_insn_after (new_insn, insn);
c4c81601 4346
073089a7
RS
4347 /* Keep register set table up to date. */
4348 record_one_set (regno, new_insn);
4349 }
7506f491
DE
4350
4351 gcse_create_count++;
4352
4353 if (gcse_file)
a42cd965
AM
4354 fprintf (gcse_file,
4355 "PRE: bb %d, insn %d, copy expression %d in insn %d to reg %d\n",
4356 BLOCK_NUM (insn), INSN_UID (new_insn), indx,
4357 INSN_UID (insn), regno);
7506f491
DE
4358}
4359
4360/* Copy available expressions that reach the redundant expression
4361 to `reaching_reg'. */
4362
4363static void
1d088dee 4364pre_insert_copies (void)
7506f491 4365{
f5f2e3cd 4366 unsigned int i, added_copy;
c4c81601
RK
4367 struct expr *expr;
4368 struct occr *occr;
4369 struct occr *avail;
a65f3558 4370
7506f491
DE
4371 /* For each available expression in the table, copy the result to
4372 `reaching_reg' if the expression reaches a deleted one.
4373
4374 ??? The current algorithm is rather brute force.
4375 Need to do some profiling. */
4376
02280659
ZD
4377 for (i = 0; i < expr_hash_table.size; i++)
4378 for (expr = expr_hash_table.table[i]; expr != NULL; expr = expr->next_same_hash)
c4c81601
RK
4379 {
4380 /* If the basic block isn't reachable, PPOUT will be TRUE. However,
4381 we don't want to insert a copy here because the expression may not
4382 really be redundant. So only insert an insn if the expression was
4383 deleted. This test also avoids further processing if the
4384 expression wasn't deleted anywhere. */
4385 if (expr->reaching_reg == NULL)
4386 continue;
7b1b4aed 4387
f5f2e3cd 4388 /* Set when we add a copy for that expression. */
7b1b4aed 4389 added_copy = 0;
c4c81601
RK
4390
4391 for (occr = expr->antic_occr; occr != NULL; occr = occr->next)
4392 {
4393 if (! occr->deleted_p)
4394 continue;
7506f491 4395
c4c81601
RK
4396 for (avail = expr->avail_occr; avail != NULL; avail = avail->next)
4397 {
4398 rtx insn = avail->insn;
7506f491 4399
c4c81601
RK
4400 /* No need to handle this one if handled already. */
4401 if (avail->copied_p)
4402 continue;
7506f491 4403
c4c81601
RK
4404 /* Don't handle this one if it's a redundant one. */
4405 if (TEST_BIT (pre_redundant_insns, INSN_CUID (insn)))
4406 continue;
7506f491 4407
c4c81601 4408 /* Or if the expression doesn't reach the deleted one. */
589005ff 4409 if (! pre_expr_reaches_here_p (BLOCK_FOR_INSN (avail->insn),
e2d2ed72
AM
4410 expr,
4411 BLOCK_FOR_INSN (occr->insn)))
c4c81601 4412 continue;
7506f491 4413
f5f2e3cd
MH
4414 added_copy = 1;
4415
c4c81601
RK
4416 /* Copy the result of avail to reaching_reg. */
4417 pre_insert_copy_insn (expr, insn);
4418 avail->copied_p = 1;
4419 }
4420 }
f5f2e3cd 4421
7b1b4aed 4422 if (added_copy)
f5f2e3cd 4423 update_ld_motion_stores (expr);
c4c81601 4424 }
7506f491
DE
4425}
4426
10d1bb36
JH
4427/* Emit move from SRC to DEST noting the equivalence with expression computed
4428 in INSN. */
4429static rtx
1d088dee 4430gcse_emit_move_after (rtx src, rtx dest, rtx insn)
10d1bb36
JH
4431{
4432 rtx new;
6bdb8dd6 4433 rtx set = single_set (insn), set2;
10d1bb36
JH
4434 rtx note;
4435 rtx eqv;
4436
4437 /* This should never fail since we're creating a reg->reg copy
4438 we've verified to be valid. */
4439
6bdb8dd6 4440 new = emit_insn_after (gen_move_insn (dest, src), insn);
285464d0 4441
10d1bb36 4442 /* Note the equivalence for local CSE pass. */
6bdb8dd6
JH
4443 set2 = single_set (new);
4444 if (!set2 || !rtx_equal_p (SET_DEST (set2), dest))
4445 return new;
10d1bb36
JH
4446 if ((note = find_reg_equal_equiv_note (insn)))
4447 eqv = XEXP (note, 0);
4448 else
4449 eqv = SET_SRC (set);
4450
a500466b 4451 set_unique_reg_note (new, REG_EQUAL, copy_insn_1 (eqv));
10d1bb36
JH
4452
4453 return new;
4454}
4455
7506f491 4456/* Delete redundant computations.
7506f491
DE
4457 Deletion is done by changing the insn to copy the `reaching_reg' of
4458 the expression into the result of the SET. It is left to later passes
4459 (cprop, cse2, flow, combine, regmove) to propagate the copy or eliminate it.
4460
cc2902df 4461 Returns nonzero if a change is made. */
7506f491
DE
4462
4463static int
1d088dee 4464pre_delete (void)
7506f491 4465{
2e653e39 4466 unsigned int i;
63bc1d05 4467 int changed;
c4c81601
RK
4468 struct expr *expr;
4469 struct occr *occr;
a65f3558 4470
7506f491 4471 changed = 0;
02280659 4472 for (i = 0; i < expr_hash_table.size; i++)
073089a7
RS
4473 for (expr = expr_hash_table.table[i];
4474 expr != NULL;
4475 expr = expr->next_same_hash)
c4c81601
RK
4476 {
4477 int indx = expr->bitmap_index;
7506f491 4478
c4c81601
RK
4479 /* We only need to search antic_occr since we require
4480 ANTLOC != 0. */
7506f491 4481
c4c81601
RK
4482 for (occr = expr->antic_occr; occr != NULL; occr = occr->next)
4483 {
4484 rtx insn = occr->insn;
4485 rtx set;
e2d2ed72 4486 basic_block bb = BLOCK_FOR_INSN (insn);
7506f491 4487
073089a7
RS
4488 /* We only delete insns that have a single_set. */
4489 if (TEST_BIT (pre_delete_map[bb->index], indx)
4490 && (set = single_set (insn)) != 0)
c4c81601 4491 {
c4c81601
RK
4492 /* Create a pseudo-reg to store the result of reaching
4493 expressions into. Get the mode for the new pseudo from
4494 the mode of the original destination pseudo. */
4495 if (expr->reaching_reg == NULL)
4496 expr->reaching_reg
4497 = gen_reg_rtx (GET_MODE (SET_DEST (set)));
4498
9b76aa3b 4499 gcse_emit_move_after (expr->reaching_reg, SET_DEST (set), insn);
10d1bb36
JH
4500 delete_insn (insn);
4501 occr->deleted_p = 1;
4502 SET_BIT (pre_redundant_insns, INSN_CUID (insn));
4503 changed = 1;
4504 gcse_subst_count++;
7506f491 4505
c4c81601
RK
4506 if (gcse_file)
4507 {
4508 fprintf (gcse_file,
4509 "PRE: redundant insn %d (expression %d) in ",
4510 INSN_UID (insn), indx);
4511 fprintf (gcse_file, "bb %d, reaching reg is %d\n",
0b17ab2f 4512 bb->index, REGNO (expr->reaching_reg));
c4c81601
RK
4513 }
4514 }
4515 }
4516 }
7506f491
DE
4517
4518 return changed;
4519}
4520
4521/* Perform GCSE optimizations using PRE.
4522 This is called by one_pre_gcse_pass after all the dataflow analysis
4523 has been done.
4524
c4c81601
RK
4525 This is based on the original Morel-Renvoise paper Fred Chow's thesis, and
4526 lazy code motion from Knoop, Ruthing and Steffen as described in Advanced
4527 Compiler Design and Implementation.
7506f491 4528
c4c81601
RK
4529 ??? A new pseudo reg is created to hold the reaching expression. The nice
4530 thing about the classical approach is that it would try to use an existing
4531 reg. If the register can't be adequately optimized [i.e. we introduce
4532 reload problems], one could add a pass here to propagate the new register
4533 through the block.
7506f491 4534
c4c81601
RK
4535 ??? We don't handle single sets in PARALLELs because we're [currently] not
4536 able to copy the rest of the parallel when we insert copies to create full
4537 redundancies from partial redundancies. However, there's no reason why we
4538 can't handle PARALLELs in the cases where there are no partial
7506f491
DE
4539 redundancies. */
4540
4541static int
1d088dee 4542pre_gcse (void)
7506f491 4543{
2e653e39
RK
4544 unsigned int i;
4545 int did_insert, changed;
7506f491 4546 struct expr **index_map;
c4c81601 4547 struct expr *expr;
7506f491
DE
4548
4549 /* Compute a mapping from expression number (`bitmap_index') to
4550 hash table entry. */
4551
703ad42b 4552 index_map = xcalloc (expr_hash_table.n_elems, sizeof (struct expr *));
02280659
ZD
4553 for (i = 0; i < expr_hash_table.size; i++)
4554 for (expr = expr_hash_table.table[i]; expr != NULL; expr = expr->next_same_hash)
c4c81601 4555 index_map[expr->bitmap_index] = expr;
7506f491
DE
4556
4557 /* Reset bitmap used to track which insns are redundant. */
a65f3558
JL
4558 pre_redundant_insns = sbitmap_alloc (max_cuid);
4559 sbitmap_zero (pre_redundant_insns);
7506f491
DE
4560
4561 /* Delete the redundant insns first so that
4562 - we know what register to use for the new insns and for the other
4563 ones with reaching expressions
4564 - we know which insns are redundant when we go to create copies */
c4c81601 4565
7506f491
DE
4566 changed = pre_delete ();
4567
a42cd965 4568 did_insert = pre_edge_insert (edge_list, index_map);
c4c81601 4569
7506f491 4570 /* In other places with reaching expressions, copy the expression to the
a42cd965 4571 specially allocated pseudo-reg that reaches the redundant expr. */
7506f491 4572 pre_insert_copies ();
a42cd965
AM
4573 if (did_insert)
4574 {
4575 commit_edge_insertions ();
4576 changed = 1;
4577 }
7506f491 4578
283a2545 4579 free (index_map);
76ac938b 4580 sbitmap_free (pre_redundant_insns);
7506f491
DE
4581 return changed;
4582}
4583
4584/* Top level routine to perform one PRE GCSE pass.
4585
cc2902df 4586 Return nonzero if a change was made. */
7506f491
DE
4587
4588static int
1d088dee 4589one_pre_gcse_pass (int pass)
7506f491
DE
4590{
4591 int changed = 0;
4592
4593 gcse_subst_count = 0;
4594 gcse_create_count = 0;
4595
02280659 4596 alloc_hash_table (max_cuid, &expr_hash_table, 0);
a42cd965 4597 add_noreturn_fake_exit_edges ();
a13d4ebf
AM
4598 if (flag_gcse_lm)
4599 compute_ld_motion_mems ();
4600
02280659 4601 compute_hash_table (&expr_hash_table);
a13d4ebf 4602 trim_ld_motion_mems ();
7506f491 4603 if (gcse_file)
02280659 4604 dump_hash_table (gcse_file, "Expression", &expr_hash_table);
c4c81601 4605
02280659 4606 if (expr_hash_table.n_elems > 0)
7506f491 4607 {
02280659 4608 alloc_pre_mem (last_basic_block, expr_hash_table.n_elems);
7506f491
DE
4609 compute_pre_data ();
4610 changed |= pre_gcse ();
a42cd965 4611 free_edge_list (edge_list);
7506f491
DE
4612 free_pre_mem ();
4613 }
c4c81601 4614
a13d4ebf 4615 free_ldst_mems ();
6809cbf9 4616 remove_fake_exit_edges ();
02280659 4617 free_hash_table (&expr_hash_table);
7506f491
DE
4618
4619 if (gcse_file)
4620 {
c4c81601 4621 fprintf (gcse_file, "\nPRE GCSE of %s, pass %d: %d bytes needed, ",
faed5cc3 4622 current_function_name (), pass, bytes_used);
c4c81601
RK
4623 fprintf (gcse_file, "%d substs, %d insns created\n",
4624 gcse_subst_count, gcse_create_count);
7506f491
DE
4625 }
4626
4627 return changed;
4628}
aeb2f500
JW
4629\f
4630/* If X contains any LABEL_REF's, add REG_LABEL notes for them to INSN.
5b1ef594
JDA
4631 If notes are added to an insn which references a CODE_LABEL, the
4632 LABEL_NUSES count is incremented. We have to add REG_LABEL notes,
4633 because the following loop optimization pass requires them. */
aeb2f500
JW
4634
4635/* ??? This is very similar to the loop.c add_label_notes function. We
4636 could probably share code here. */
4637
4638/* ??? If there was a jump optimization pass after gcse and before loop,
4639 then we would not need to do this here, because jump would add the
4640 necessary REG_LABEL notes. */
4641
4642static void
1d088dee 4643add_label_notes (rtx x, rtx insn)
aeb2f500
JW
4644{
4645 enum rtx_code code = GET_CODE (x);
4646 int i, j;
6f7d635c 4647 const char *fmt;
aeb2f500
JW
4648
4649 if (code == LABEL_REF && !LABEL_REF_NONLOCAL_P (x))
4650 {
6b3603c2 4651 /* This code used to ignore labels that referred to dispatch tables to
e0bb17a8 4652 avoid flow generating (slightly) worse code.
6b3603c2 4653
ac7c5af5
JL
4654 We no longer ignore such label references (see LABEL_REF handling in
4655 mark_jump_label for additional information). */
c4c81601 4656
6b8c9327 4657 REG_NOTES (insn) = gen_rtx_INSN_LIST (REG_LABEL, XEXP (x, 0),
6b3603c2 4658 REG_NOTES (insn));
5b1ef594 4659 if (LABEL_P (XEXP (x, 0)))
589005ff 4660 LABEL_NUSES (XEXP (x, 0))++;
aeb2f500
JW
4661 return;
4662 }
4663
c4c81601 4664 for (i = GET_RTX_LENGTH (code) - 1, fmt = GET_RTX_FORMAT (code); i >= 0; i--)
aeb2f500
JW
4665 {
4666 if (fmt[i] == 'e')
4667 add_label_notes (XEXP (x, i), insn);
4668 else if (fmt[i] == 'E')
4669 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4670 add_label_notes (XVECEXP (x, i, j), insn);
4671 }
4672}
a65f3558
JL
4673
4674/* Compute transparent outgoing information for each block.
4675
4676 An expression is transparent to an edge unless it is killed by
4677 the edge itself. This can only happen with abnormal control flow,
4678 when the edge is traversed through a call. This happens with
4679 non-local labels and exceptions.
4680
4681 This would not be necessary if we split the edge. While this is
4682 normally impossible for abnormal critical edges, with some effort
4683 it should be possible with exception handling, since we still have
4684 control over which handler should be invoked. But due to increased
4685 EH table sizes, this may not be worthwhile. */
4686
4687static void
1d088dee 4688compute_transpout (void)
a65f3558 4689{
e0082a72 4690 basic_block bb;
2e653e39 4691 unsigned int i;
c4c81601 4692 struct expr *expr;
a65f3558 4693
d55bc081 4694 sbitmap_vector_ones (transpout, last_basic_block);
a65f3558 4695
e0082a72 4696 FOR_EACH_BB (bb)
a65f3558 4697 {
a65f3558
JL
4698 /* Note that flow inserted a nop a the end of basic blocks that
4699 end in call instructions for reasons other than abnormal
4700 control flow. */
7b1b4aed 4701 if (! CALL_P (BB_END (bb)))
a65f3558
JL
4702 continue;
4703
02280659
ZD
4704 for (i = 0; i < expr_hash_table.size; i++)
4705 for (expr = expr_hash_table.table[i]; expr ; expr = expr->next_same_hash)
7b1b4aed 4706 if (MEM_P (expr->expr))
c4c81601
RK
4707 {
4708 if (GET_CODE (XEXP (expr->expr, 0)) == SYMBOL_REF
4709 && CONSTANT_POOL_ADDRESS_P (XEXP (expr->expr, 0)))
4710 continue;
589005ff 4711
c4c81601
RK
4712 /* ??? Optimally, we would use interprocedural alias
4713 analysis to determine if this mem is actually killed
4714 by this call. */
e0082a72 4715 RESET_BIT (transpout[bb->index], expr->bitmap_index);
c4c81601 4716 }
a65f3558
JL
4717 }
4718}
dfdb644f 4719
bb457bd9
JL
4720/* Code Hoisting variables and subroutines. */
4721
4722/* Very busy expressions. */
4723static sbitmap *hoist_vbein;
4724static sbitmap *hoist_vbeout;
4725
4726/* Hoistable expressions. */
4727static sbitmap *hoist_exprs;
4728
bb457bd9 4729/* ??? We could compute post dominators and run this algorithm in
68e82b83 4730 reverse to perform tail merging, doing so would probably be
bb457bd9
JL
4731 more effective than the tail merging code in jump.c.
4732
4733 It's unclear if tail merging could be run in parallel with
4734 code hoisting. It would be nice. */
4735
4736/* Allocate vars used for code hoisting analysis. */
4737
4738static void
1d088dee 4739alloc_code_hoist_mem (int n_blocks, int n_exprs)
bb457bd9
JL
4740{
4741 antloc = sbitmap_vector_alloc (n_blocks, n_exprs);
4742 transp = sbitmap_vector_alloc (n_blocks, n_exprs);
4743 comp = sbitmap_vector_alloc (n_blocks, n_exprs);
4744
4745 hoist_vbein = sbitmap_vector_alloc (n_blocks, n_exprs);
4746 hoist_vbeout = sbitmap_vector_alloc (n_blocks, n_exprs);
4747 hoist_exprs = sbitmap_vector_alloc (n_blocks, n_exprs);
4748 transpout = sbitmap_vector_alloc (n_blocks, n_exprs);
bb457bd9
JL
4749}
4750
4751/* Free vars used for code hoisting analysis. */
4752
4753static void
1d088dee 4754free_code_hoist_mem (void)
bb457bd9 4755{
5a660bff
DB
4756 sbitmap_vector_free (antloc);
4757 sbitmap_vector_free (transp);
4758 sbitmap_vector_free (comp);
bb457bd9 4759
5a660bff
DB
4760 sbitmap_vector_free (hoist_vbein);
4761 sbitmap_vector_free (hoist_vbeout);
4762 sbitmap_vector_free (hoist_exprs);
4763 sbitmap_vector_free (transpout);
bb457bd9 4764
d47cc544 4765 free_dominance_info (CDI_DOMINATORS);
bb457bd9
JL
4766}
4767
4768/* Compute the very busy expressions at entry/exit from each block.
4769
4770 An expression is very busy if all paths from a given point
4771 compute the expression. */
4772
4773static void
1d088dee 4774compute_code_hoist_vbeinout (void)
bb457bd9 4775{
e0082a72
ZD
4776 int changed, passes;
4777 basic_block bb;
bb457bd9 4778
d55bc081
ZD
4779 sbitmap_vector_zero (hoist_vbeout, last_basic_block);
4780 sbitmap_vector_zero (hoist_vbein, last_basic_block);
bb457bd9
JL
4781
4782 passes = 0;
4783 changed = 1;
c4c81601 4784
bb457bd9
JL
4785 while (changed)
4786 {
4787 changed = 0;
c4c81601 4788
bb457bd9
JL
4789 /* We scan the blocks in the reverse order to speed up
4790 the convergence. */
e0082a72 4791 FOR_EACH_BB_REVERSE (bb)
bb457bd9 4792 {
e0082a72
ZD
4793 changed |= sbitmap_a_or_b_and_c_cg (hoist_vbein[bb->index], antloc[bb->index],
4794 hoist_vbeout[bb->index], transp[bb->index]);
4795 if (bb->next_bb != EXIT_BLOCK_PTR)
4796 sbitmap_intersection_of_succs (hoist_vbeout[bb->index], hoist_vbein, bb->index);
bb457bd9 4797 }
c4c81601 4798
bb457bd9
JL
4799 passes++;
4800 }
4801
4802 if (gcse_file)
4803 fprintf (gcse_file, "hoisting vbeinout computation: %d passes\n", passes);
4804}
4805
4806/* Top level routine to do the dataflow analysis needed by code hoisting. */
4807
4808static void
1d088dee 4809compute_code_hoist_data (void)
bb457bd9 4810{
02280659 4811 compute_local_properties (transp, comp, antloc, &expr_hash_table);
bb457bd9
JL
4812 compute_transpout ();
4813 compute_code_hoist_vbeinout ();
d47cc544 4814 calculate_dominance_info (CDI_DOMINATORS);
bb457bd9
JL
4815 if (gcse_file)
4816 fprintf (gcse_file, "\n");
4817}
4818
4819/* Determine if the expression identified by EXPR_INDEX would
4820 reach BB unimpared if it was placed at the end of EXPR_BB.
4821
4822 It's unclear exactly what Muchnick meant by "unimpared". It seems
4823 to me that the expression must either be computed or transparent in
4824 *every* block in the path(s) from EXPR_BB to BB. Any other definition
4825 would allow the expression to be hoisted out of loops, even if
4826 the expression wasn't a loop invariant.
4827
4828 Contrast this to reachability for PRE where an expression is
4829 considered reachable if *any* path reaches instead of *all*
4830 paths. */
4831
4832static int
1d088dee 4833hoist_expr_reaches_here_p (basic_block expr_bb, int expr_index, basic_block bb, char *visited)
bb457bd9
JL
4834{
4835 edge pred;
628f6a4e 4836 edge_iterator ei;
283a2545 4837 int visited_allocated_locally = 0;
589005ff 4838
bb457bd9
JL
4839
4840 if (visited == NULL)
4841 {
8e42ace1 4842 visited_allocated_locally = 1;
d55bc081 4843 visited = xcalloc (last_basic_block, 1);
bb457bd9
JL
4844 }
4845
628f6a4e 4846 FOR_EACH_EDGE (pred, ei, bb->preds)
bb457bd9 4847 {
e2d2ed72 4848 basic_block pred_bb = pred->src;
bb457bd9
JL
4849
4850 if (pred->src == ENTRY_BLOCK_PTR)
4851 break;
f305679f
JH
4852 else if (pred_bb == expr_bb)
4853 continue;
0b17ab2f 4854 else if (visited[pred_bb->index])
bb457bd9 4855 continue;
c4c81601 4856
bb457bd9 4857 /* Does this predecessor generate this expression? */
0b17ab2f 4858 else if (TEST_BIT (comp[pred_bb->index], expr_index))
bb457bd9 4859 break;
0b17ab2f 4860 else if (! TEST_BIT (transp[pred_bb->index], expr_index))
bb457bd9 4861 break;
c4c81601 4862
bb457bd9
JL
4863 /* Not killed. */
4864 else
4865 {
0b17ab2f 4866 visited[pred_bb->index] = 1;
bb457bd9
JL
4867 if (! hoist_expr_reaches_here_p (expr_bb, expr_index,
4868 pred_bb, visited))
4869 break;
4870 }
4871 }
589005ff 4872 if (visited_allocated_locally)
283a2545 4873 free (visited);
c4c81601 4874
bb457bd9
JL
4875 return (pred == NULL);
4876}
4877\f
4878/* Actually perform code hoisting. */
c4c81601 4879
bb457bd9 4880static void
1d088dee 4881hoist_code (void)
bb457bd9 4882{
e0082a72 4883 basic_block bb, dominated;
c635a1ec
DB
4884 basic_block *domby;
4885 unsigned int domby_len;
4886 unsigned int i,j;
bb457bd9 4887 struct expr **index_map;
c4c81601 4888 struct expr *expr;
bb457bd9 4889
d55bc081 4890 sbitmap_vector_zero (hoist_exprs, last_basic_block);
bb457bd9
JL
4891
4892 /* Compute a mapping from expression number (`bitmap_index') to
4893 hash table entry. */
4894
703ad42b 4895 index_map = xcalloc (expr_hash_table.n_elems, sizeof (struct expr *));
02280659
ZD
4896 for (i = 0; i < expr_hash_table.size; i++)
4897 for (expr = expr_hash_table.table[i]; expr != NULL; expr = expr->next_same_hash)
c4c81601 4898 index_map[expr->bitmap_index] = expr;
bb457bd9
JL
4899
4900 /* Walk over each basic block looking for potentially hoistable
4901 expressions, nothing gets hoisted from the entry block. */
e0082a72 4902 FOR_EACH_BB (bb)
bb457bd9
JL
4903 {
4904 int found = 0;
4905 int insn_inserted_p;
4906
d47cc544 4907 domby_len = get_dominated_by (CDI_DOMINATORS, bb, &domby);
bb457bd9
JL
4908 /* Examine each expression that is very busy at the exit of this
4909 block. These are the potentially hoistable expressions. */
e0082a72 4910 for (i = 0; i < hoist_vbeout[bb->index]->n_bits; i++)
bb457bd9
JL
4911 {
4912 int hoistable = 0;
c4c81601 4913
c635a1ec
DB
4914 if (TEST_BIT (hoist_vbeout[bb->index], i)
4915 && TEST_BIT (transpout[bb->index], i))
bb457bd9
JL
4916 {
4917 /* We've found a potentially hoistable expression, now
4918 we look at every block BB dominates to see if it
4919 computes the expression. */
c635a1ec 4920 for (j = 0; j < domby_len; j++)
bb457bd9 4921 {
c635a1ec 4922 dominated = domby[j];
bb457bd9 4923 /* Ignore self dominance. */
c635a1ec 4924 if (bb == dominated)
bb457bd9 4925 continue;
bb457bd9
JL
4926 /* We've found a dominated block, now see if it computes
4927 the busy expression and whether or not moving that
4928 expression to the "beginning" of that block is safe. */
e0082a72 4929 if (!TEST_BIT (antloc[dominated->index], i))
bb457bd9
JL
4930 continue;
4931
4932 /* Note if the expression would reach the dominated block
589005ff 4933 unimpared if it was placed at the end of BB.
bb457bd9
JL
4934
4935 Keep track of how many times this expression is hoistable
4936 from a dominated block into BB. */
e0082a72 4937 if (hoist_expr_reaches_here_p (bb, i, dominated, NULL))
bb457bd9
JL
4938 hoistable++;
4939 }
4940
ff7cc307 4941 /* If we found more than one hoistable occurrence of this
bb457bd9
JL
4942 expression, then note it in the bitmap of expressions to
4943 hoist. It makes no sense to hoist things which are computed
4944 in only one BB, and doing so tends to pessimize register
4945 allocation. One could increase this value to try harder
4946 to avoid any possible code expansion due to register
4947 allocation issues; however experiments have shown that
4948 the vast majority of hoistable expressions are only movable
e0bb17a8 4949 from two successors, so raising this threshold is likely
bb457bd9
JL
4950 to nullify any benefit we get from code hoisting. */
4951 if (hoistable > 1)
4952 {
e0082a72 4953 SET_BIT (hoist_exprs[bb->index], i);
bb457bd9
JL
4954 found = 1;
4955 }
4956 }
4957 }
bb457bd9
JL
4958 /* If we found nothing to hoist, then quit now. */
4959 if (! found)
c635a1ec 4960 {
1d088dee 4961 free (domby);
bb457bd9 4962 continue;
c635a1ec 4963 }
bb457bd9
JL
4964
4965 /* Loop over all the hoistable expressions. */
e0082a72 4966 for (i = 0; i < hoist_exprs[bb->index]->n_bits; i++)
bb457bd9
JL
4967 {
4968 /* We want to insert the expression into BB only once, so
4969 note when we've inserted it. */
4970 insn_inserted_p = 0;
4971
4972 /* These tests should be the same as the tests above. */
e0082a72 4973 if (TEST_BIT (hoist_vbeout[bb->index], i))
bb457bd9
JL
4974 {
4975 /* We've found a potentially hoistable expression, now
4976 we look at every block BB dominates to see if it
4977 computes the expression. */
c635a1ec 4978 for (j = 0; j < domby_len; j++)
bb457bd9 4979 {
c635a1ec 4980 dominated = domby[j];
bb457bd9 4981 /* Ignore self dominance. */
c635a1ec 4982 if (bb == dominated)
bb457bd9
JL
4983 continue;
4984
4985 /* We've found a dominated block, now see if it computes
4986 the busy expression and whether or not moving that
4987 expression to the "beginning" of that block is safe. */
e0082a72 4988 if (!TEST_BIT (antloc[dominated->index], i))
bb457bd9
JL
4989 continue;
4990
4991 /* The expression is computed in the dominated block and
4992 it would be safe to compute it at the start of the
4993 dominated block. Now we have to determine if the
ff7cc307 4994 expression would reach the dominated block if it was
bb457bd9 4995 placed at the end of BB. */
e0082a72 4996 if (hoist_expr_reaches_here_p (bb, i, dominated, NULL))
bb457bd9
JL
4997 {
4998 struct expr *expr = index_map[i];
4999 struct occr *occr = expr->antic_occr;
5000 rtx insn;
5001 rtx set;
5002
ff7cc307 5003 /* Find the right occurrence of this expression. */
e0082a72 5004 while (BLOCK_FOR_INSN (occr->insn) != dominated && occr)
bb457bd9
JL
5005 occr = occr->next;
5006
282899df 5007 gcc_assert (occr);
bb457bd9 5008 insn = occr->insn;
bb457bd9 5009 set = single_set (insn);
282899df 5010 gcc_assert (set);
bb457bd9
JL
5011
5012 /* Create a pseudo-reg to store the result of reaching
5013 expressions into. Get the mode for the new pseudo
5014 from the mode of the original destination pseudo. */
5015 if (expr->reaching_reg == NULL)
5016 expr->reaching_reg
5017 = gen_reg_rtx (GET_MODE (SET_DEST (set)));
5018
10d1bb36
JH
5019 gcse_emit_move_after (expr->reaching_reg, SET_DEST (set), insn);
5020 delete_insn (insn);
5021 occr->deleted_p = 1;
5022 if (!insn_inserted_p)
bb457bd9 5023 {
10d1bb36
JH
5024 insert_insn_end_bb (index_map[i], bb, 0);
5025 insn_inserted_p = 1;
bb457bd9
JL
5026 }
5027 }
5028 }
5029 }
5030 }
c635a1ec 5031 free (domby);
bb457bd9 5032 }
c4c81601 5033
8e42ace1 5034 free (index_map);
bb457bd9
JL
5035}
5036
5037/* Top level routine to perform one code hoisting (aka unification) pass
5038
cc2902df 5039 Return nonzero if a change was made. */
bb457bd9
JL
5040
5041static int
1d088dee 5042one_code_hoisting_pass (void)
bb457bd9
JL
5043{
5044 int changed = 0;
5045
02280659
ZD
5046 alloc_hash_table (max_cuid, &expr_hash_table, 0);
5047 compute_hash_table (&expr_hash_table);
bb457bd9 5048 if (gcse_file)
02280659 5049 dump_hash_table (gcse_file, "Code Hosting Expressions", &expr_hash_table);
c4c81601 5050
02280659 5051 if (expr_hash_table.n_elems > 0)
bb457bd9 5052 {
02280659 5053 alloc_code_hoist_mem (last_basic_block, expr_hash_table.n_elems);
bb457bd9
JL
5054 compute_code_hoist_data ();
5055 hoist_code ();
5056 free_code_hoist_mem ();
5057 }
c4c81601 5058
02280659 5059 free_hash_table (&expr_hash_table);
bb457bd9
JL
5060
5061 return changed;
5062}
a13d4ebf
AM
5063\f
5064/* Here we provide the things required to do store motion towards
5065 the exit. In order for this to be effective, gcse also needed to
5066 be taught how to move a load when it is kill only by a store to itself.
5067
5068 int i;
5069 float a[10];
5070
5071 void foo(float scale)
5072 {
5073 for (i=0; i<10; i++)
5074 a[i] *= scale;
5075 }
5076
5077 'i' is both loaded and stored to in the loop. Normally, gcse cannot move
589005ff
KH
5078 the load out since its live around the loop, and stored at the bottom
5079 of the loop.
a13d4ebf 5080
589005ff 5081 The 'Load Motion' referred to and implemented in this file is
a13d4ebf
AM
5082 an enhancement to gcse which when using edge based lcm, recognizes
5083 this situation and allows gcse to move the load out of the loop.
5084
5085 Once gcse has hoisted the load, store motion can then push this
5086 load towards the exit, and we end up with no loads or stores of 'i'
5087 in the loop. */
5088
ff7cc307 5089/* This will search the ldst list for a matching expression. If it
a13d4ebf
AM
5090 doesn't find one, we create one and initialize it. */
5091
5092static struct ls_expr *
1d088dee 5093ldst_entry (rtx x)
a13d4ebf 5094{
b58b21d5 5095 int do_not_record_p = 0;
a13d4ebf 5096 struct ls_expr * ptr;
b58b21d5 5097 unsigned int hash;
a13d4ebf 5098
0516f6fe
SB
5099 hash = hash_rtx (x, GET_MODE (x), &do_not_record_p,
5100 NULL, /*have_reg_qty=*/false);
a13d4ebf 5101
b58b21d5
RS
5102 for (ptr = pre_ldst_mems; ptr != NULL; ptr = ptr->next)
5103 if (ptr->hash_index == hash && expr_equiv_p (ptr->pattern, x))
5104 return ptr;
5105
5106 ptr = xmalloc (sizeof (struct ls_expr));
5107
5108 ptr->next = pre_ldst_mems;
5109 ptr->expr = NULL;
5110 ptr->pattern = x;
5111 ptr->pattern_regs = NULL_RTX;
5112 ptr->loads = NULL_RTX;
5113 ptr->stores = NULL_RTX;
5114 ptr->reaching_reg = NULL_RTX;
5115 ptr->invalid = 0;
5116 ptr->index = 0;
5117 ptr->hash_index = hash;
5118 pre_ldst_mems = ptr;
589005ff 5119
a13d4ebf
AM
5120 return ptr;
5121}
5122
5123/* Free up an individual ldst entry. */
5124
589005ff 5125static void
1d088dee 5126free_ldst_entry (struct ls_expr * ptr)
a13d4ebf 5127{
aaa4ca30
AJ
5128 free_INSN_LIST_list (& ptr->loads);
5129 free_INSN_LIST_list (& ptr->stores);
a13d4ebf
AM
5130
5131 free (ptr);
5132}
5133
5134/* Free up all memory associated with the ldst list. */
5135
5136static void
1d088dee 5137free_ldst_mems (void)
a13d4ebf 5138{
589005ff 5139 while (pre_ldst_mems)
a13d4ebf
AM
5140 {
5141 struct ls_expr * tmp = pre_ldst_mems;
5142
5143 pre_ldst_mems = pre_ldst_mems->next;
5144
5145 free_ldst_entry (tmp);
5146 }
5147
5148 pre_ldst_mems = NULL;
5149}
5150
5151/* Dump debugging info about the ldst list. */
5152
5153static void
1d088dee 5154print_ldst_list (FILE * file)
a13d4ebf
AM
5155{
5156 struct ls_expr * ptr;
5157
5158 fprintf (file, "LDST list: \n");
5159
5160 for (ptr = first_ls_expr(); ptr != NULL; ptr = next_ls_expr (ptr))
5161 {
5162 fprintf (file, " Pattern (%3d): ", ptr->index);
5163
5164 print_rtl (file, ptr->pattern);
5165
5166 fprintf (file, "\n Loads : ");
5167
5168 if (ptr->loads)
5169 print_rtl (file, ptr->loads);
5170 else
5171 fprintf (file, "(nil)");
5172
5173 fprintf (file, "\n Stores : ");
5174
5175 if (ptr->stores)
5176 print_rtl (file, ptr->stores);
5177 else
5178 fprintf (file, "(nil)");
5179
5180 fprintf (file, "\n\n");
5181 }
5182
5183 fprintf (file, "\n");
5184}
5185
5186/* Returns 1 if X is in the list of ldst only expressions. */
5187
5188static struct ls_expr *
1d088dee 5189find_rtx_in_ldst (rtx x)
a13d4ebf
AM
5190{
5191 struct ls_expr * ptr;
589005ff 5192
a13d4ebf
AM
5193 for (ptr = pre_ldst_mems; ptr != NULL; ptr = ptr->next)
5194 if (expr_equiv_p (ptr->pattern, x) && ! ptr->invalid)
5195 return ptr;
5196
5197 return NULL;
5198}
5199
5200/* Assign each element of the list of mems a monotonically increasing value. */
5201
5202static int
1d088dee 5203enumerate_ldsts (void)
a13d4ebf
AM
5204{
5205 struct ls_expr * ptr;
5206 int n = 0;
5207
5208 for (ptr = pre_ldst_mems; ptr != NULL; ptr = ptr->next)
5209 ptr->index = n++;
5210
5211 return n;
5212}
5213
5214/* Return first item in the list. */
5215
5216static inline struct ls_expr *
1d088dee 5217first_ls_expr (void)
a13d4ebf
AM
5218{
5219 return pre_ldst_mems;
5220}
5221
0e8a66de 5222/* Return the next item in the list after the specified one. */
a13d4ebf
AM
5223
5224static inline struct ls_expr *
1d088dee 5225next_ls_expr (struct ls_expr * ptr)
a13d4ebf
AM
5226{
5227 return ptr->next;
5228}
5229\f
5230/* Load Motion for loads which only kill themselves. */
5231
5232/* Return true if x is a simple MEM operation, with no registers or
5233 side effects. These are the types of loads we consider for the
5234 ld_motion list, otherwise we let the usual aliasing take care of it. */
5235
589005ff 5236static int
1d088dee 5237simple_mem (rtx x)
a13d4ebf 5238{
7b1b4aed 5239 if (! MEM_P (x))
a13d4ebf 5240 return 0;
589005ff 5241
a13d4ebf
AM
5242 if (MEM_VOLATILE_P (x))
5243 return 0;
589005ff 5244
a13d4ebf
AM
5245 if (GET_MODE (x) == BLKmode)
5246 return 0;
aaa4ca30 5247
47a3dae1
ZD
5248 /* If we are handling exceptions, we must be careful with memory references
5249 that may trap. If we are not, the behavior is undefined, so we may just
5250 continue. */
5251 if (flag_non_call_exceptions && may_trap_p (x))
98d3d336
RS
5252 return 0;
5253
47a3dae1
ZD
5254 if (side_effects_p (x))
5255 return 0;
589005ff 5256
47a3dae1
ZD
5257 /* Do not consider function arguments passed on stack. */
5258 if (reg_mentioned_p (stack_pointer_rtx, x))
5259 return 0;
5260
5261 if (flag_float_store && FLOAT_MODE_P (GET_MODE (x)))
5262 return 0;
5263
5264 return 1;
a13d4ebf
AM
5265}
5266
589005ff
KH
5267/* Make sure there isn't a buried reference in this pattern anywhere.
5268 If there is, invalidate the entry for it since we're not capable
5269 of fixing it up just yet.. We have to be sure we know about ALL
a13d4ebf
AM
5270 loads since the aliasing code will allow all entries in the
5271 ld_motion list to not-alias itself. If we miss a load, we will get
589005ff 5272 the wrong value since gcse might common it and we won't know to
a13d4ebf
AM
5273 fix it up. */
5274
5275static void
1d088dee 5276invalidate_any_buried_refs (rtx x)
a13d4ebf
AM
5277{
5278 const char * fmt;
8e42ace1 5279 int i, j;
a13d4ebf
AM
5280 struct ls_expr * ptr;
5281
5282 /* Invalidate it in the list. */
7b1b4aed 5283 if (MEM_P (x) && simple_mem (x))
a13d4ebf
AM
5284 {
5285 ptr = ldst_entry (x);
5286 ptr->invalid = 1;
5287 }
5288
5289 /* Recursively process the insn. */
5290 fmt = GET_RTX_FORMAT (GET_CODE (x));
589005ff 5291
a13d4ebf
AM
5292 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
5293 {
5294 if (fmt[i] == 'e')
5295 invalidate_any_buried_refs (XEXP (x, i));
5296 else if (fmt[i] == 'E')
5297 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
5298 invalidate_any_buried_refs (XVECEXP (x, i, j));
5299 }
5300}
5301
4d3eb89a
HPN
5302/* Find all the 'simple' MEMs which are used in LOADs and STORES. Simple
5303 being defined as MEM loads and stores to symbols, with no side effects
5304 and no registers in the expression. For a MEM destination, we also
5305 check that the insn is still valid if we replace the destination with a
5306 REG, as is done in update_ld_motion_stores. If there are any uses/defs
5307 which don't match this criteria, they are invalidated and trimmed out
5308 later. */
a13d4ebf 5309
589005ff 5310static void
1d088dee 5311compute_ld_motion_mems (void)
a13d4ebf
AM
5312{
5313 struct ls_expr * ptr;
e0082a72 5314 basic_block bb;
a13d4ebf 5315 rtx insn;
589005ff 5316
a13d4ebf
AM
5317 pre_ldst_mems = NULL;
5318
e0082a72 5319 FOR_EACH_BB (bb)
a13d4ebf 5320 {
a813c111
SB
5321 for (insn = BB_HEAD (bb);
5322 insn && insn != NEXT_INSN (BB_END (bb));
a13d4ebf
AM
5323 insn = NEXT_INSN (insn))
5324 {
735e8085 5325 if (INSN_P (insn))
a13d4ebf
AM
5326 {
5327 if (GET_CODE (PATTERN (insn)) == SET)
5328 {
5329 rtx src = SET_SRC (PATTERN (insn));
5330 rtx dest = SET_DEST (PATTERN (insn));
5331
5332 /* Check for a simple LOAD... */
7b1b4aed 5333 if (MEM_P (src) && simple_mem (src))
a13d4ebf
AM
5334 {
5335 ptr = ldst_entry (src);
7b1b4aed 5336 if (REG_P (dest))
a13d4ebf
AM
5337 ptr->loads = alloc_INSN_LIST (insn, ptr->loads);
5338 else
5339 ptr->invalid = 1;
5340 }
5341 else
5342 {
5343 /* Make sure there isn't a buried load somewhere. */
5344 invalidate_any_buried_refs (src);
5345 }
589005ff 5346
a13d4ebf
AM
5347 /* Check for stores. Don't worry about aliased ones, they
5348 will block any movement we might do later. We only care
5349 about this exact pattern since those are the only
5350 circumstance that we will ignore the aliasing info. */
7b1b4aed 5351 if (MEM_P (dest) && simple_mem (dest))
a13d4ebf
AM
5352 {
5353 ptr = ldst_entry (dest);
589005ff 5354
7b1b4aed 5355 if (! MEM_P (src)
4d3eb89a
HPN
5356 && GET_CODE (src) != ASM_OPERANDS
5357 /* Check for REG manually since want_to_gcse_p
5358 returns 0 for all REGs. */
1707bafa 5359 && can_assign_to_reg_p (src))
a13d4ebf
AM
5360 ptr->stores = alloc_INSN_LIST (insn, ptr->stores);
5361 else
5362 ptr->invalid = 1;
5363 }
5364 }
5365 else
5366 invalidate_any_buried_refs (PATTERN (insn));
5367 }
5368 }
5369 }
5370}
5371
589005ff 5372/* Remove any references that have been either invalidated or are not in the
a13d4ebf
AM
5373 expression list for pre gcse. */
5374
5375static void
1d088dee 5376trim_ld_motion_mems (void)
a13d4ebf 5377{
b58b21d5
RS
5378 struct ls_expr * * last = & pre_ldst_mems;
5379 struct ls_expr * ptr = pre_ldst_mems;
a13d4ebf
AM
5380
5381 while (ptr != NULL)
5382 {
b58b21d5 5383 struct expr * expr;
589005ff 5384
a13d4ebf 5385 /* Delete if entry has been made invalid. */
b58b21d5 5386 if (! ptr->invalid)
a13d4ebf 5387 {
a13d4ebf 5388 /* Delete if we cannot find this mem in the expression list. */
b58b21d5 5389 unsigned int hash = ptr->hash_index % expr_hash_table.size;
589005ff 5390
b58b21d5
RS
5391 for (expr = expr_hash_table.table[hash];
5392 expr != NULL;
5393 expr = expr->next_same_hash)
5394 if (expr_equiv_p (expr->expr, ptr->pattern))
5395 break;
a13d4ebf
AM
5396 }
5397 else
b58b21d5
RS
5398 expr = (struct expr *) 0;
5399
5400 if (expr)
a13d4ebf
AM
5401 {
5402 /* Set the expression field if we are keeping it. */
a13d4ebf 5403 ptr->expr = expr;
b58b21d5 5404 last = & ptr->next;
a13d4ebf
AM
5405 ptr = ptr->next;
5406 }
b58b21d5
RS
5407 else
5408 {
5409 *last = ptr->next;
5410 free_ldst_entry (ptr);
5411 ptr = * last;
5412 }
a13d4ebf
AM
5413 }
5414
5415 /* Show the world what we've found. */
5416 if (gcse_file && pre_ldst_mems != NULL)
5417 print_ldst_list (gcse_file);
5418}
5419
5420/* This routine will take an expression which we are replacing with
5421 a reaching register, and update any stores that are needed if
5422 that expression is in the ld_motion list. Stores are updated by
a98ebe2e 5423 copying their SRC to the reaching register, and then storing
a13d4ebf
AM
5424 the reaching register into the store location. These keeps the
5425 correct value in the reaching register for the loads. */
5426
5427static void
1d088dee 5428update_ld_motion_stores (struct expr * expr)
a13d4ebf
AM
5429{
5430 struct ls_expr * mem_ptr;
5431
5432 if ((mem_ptr = find_rtx_in_ldst (expr->expr)))
5433 {
589005ff
KH
5434 /* We can try to find just the REACHED stores, but is shouldn't
5435 matter to set the reaching reg everywhere... some might be
a13d4ebf
AM
5436 dead and should be eliminated later. */
5437
4d3eb89a
HPN
5438 /* We replace (set mem expr) with (set reg expr) (set mem reg)
5439 where reg is the reaching reg used in the load. We checked in
5440 compute_ld_motion_mems that we can replace (set mem expr) with
5441 (set reg expr) in that insn. */
a13d4ebf 5442 rtx list = mem_ptr->stores;
589005ff 5443
a13d4ebf
AM
5444 for ( ; list != NULL_RTX; list = XEXP (list, 1))
5445 {
5446 rtx insn = XEXP (list, 0);
5447 rtx pat = PATTERN (insn);
5448 rtx src = SET_SRC (pat);
5449 rtx reg = expr->reaching_reg;
c57718d3 5450 rtx copy, new;
a13d4ebf
AM
5451
5452 /* If we've already copied it, continue. */
5453 if (expr->reaching_reg == src)
5454 continue;
589005ff 5455
a13d4ebf
AM
5456 if (gcse_file)
5457 {
5458 fprintf (gcse_file, "PRE: store updated with reaching reg ");
5459 print_rtl (gcse_file, expr->reaching_reg);
5460 fprintf (gcse_file, ":\n ");
5461 print_inline_rtx (gcse_file, insn, 8);
5462 fprintf (gcse_file, "\n");
5463 }
589005ff 5464
47a3dae1 5465 copy = gen_move_insn ( reg, copy_rtx (SET_SRC (pat)));
c57718d3
RK
5466 new = emit_insn_before (copy, insn);
5467 record_one_set (REGNO (reg), new);
a13d4ebf
AM
5468 SET_SRC (pat) = reg;
5469
5470 /* un-recognize this pattern since it's probably different now. */
5471 INSN_CODE (insn) = -1;
5472 gcse_create_count++;
5473 }
5474 }
5475}
5476\f
5477/* Store motion code. */
5478
47a3dae1
ZD
5479#define ANTIC_STORE_LIST(x) ((x)->loads)
5480#define AVAIL_STORE_LIST(x) ((x)->stores)
5481#define LAST_AVAIL_CHECK_FAILURE(x) ((x)->reaching_reg)
5482
589005ff 5483/* This is used to communicate the target bitvector we want to use in the
aaa4ca30 5484 reg_set_info routine when called via the note_stores mechanism. */
47a3dae1
ZD
5485static int * regvec;
5486
5487/* And current insn, for the same routine. */
5488static rtx compute_store_table_current_insn;
aaa4ca30 5489
a13d4ebf
AM
5490/* Used in computing the reverse edge graph bit vectors. */
5491static sbitmap * st_antloc;
5492
5493/* Global holding the number of store expressions we are dealing with. */
5494static int num_stores;
5495
01c43039
RE
5496/* Checks to set if we need to mark a register set. Called from
5497 note_stores. */
a13d4ebf 5498
aaa4ca30 5499static void
1d088dee 5500reg_set_info (rtx dest, rtx setter ATTRIBUTE_UNUSED,
01c43039 5501 void *data)
a13d4ebf 5502{
01c43039
RE
5503 sbitmap bb_reg = data;
5504
aaa4ca30
AJ
5505 if (GET_CODE (dest) == SUBREG)
5506 dest = SUBREG_REG (dest);
adfcce61 5507
7b1b4aed 5508 if (REG_P (dest))
01c43039
RE
5509 {
5510 regvec[REGNO (dest)] = INSN_UID (compute_store_table_current_insn);
5511 if (bb_reg)
5512 SET_BIT (bb_reg, REGNO (dest));
5513 }
5514}
5515
5516/* Clear any mark that says that this insn sets dest. Called from
5517 note_stores. */
5518
5519static void
5520reg_clear_last_set (rtx dest, rtx setter ATTRIBUTE_UNUSED,
5521 void *data)
5522{
5523 int *dead_vec = data;
5524
5525 if (GET_CODE (dest) == SUBREG)
5526 dest = SUBREG_REG (dest);
5527
7b1b4aed 5528 if (REG_P (dest) &&
01c43039
RE
5529 dead_vec[REGNO (dest)] == INSN_UID (compute_store_table_current_insn))
5530 dead_vec[REGNO (dest)] = 0;
a13d4ebf
AM
5531}
5532
47a3dae1
ZD
5533/* Return zero if some of the registers in list X are killed
5534 due to set of registers in bitmap REGS_SET. */
1d088dee 5535
47a3dae1 5536static bool
1d088dee 5537store_ops_ok (rtx x, int *regs_set)
47a3dae1
ZD
5538{
5539 rtx reg;
5540
5541 for (; x; x = XEXP (x, 1))
5542 {
5543 reg = XEXP (x, 0);
5544 if (regs_set[REGNO(reg)])
1d088dee 5545 return false;
47a3dae1 5546 }
a13d4ebf 5547
47a3dae1
ZD
5548 return true;
5549}
5550
5551/* Returns a list of registers mentioned in X. */
5552static rtx
1d088dee 5553extract_mentioned_regs (rtx x)
47a3dae1
ZD
5554{
5555 return extract_mentioned_regs_helper (x, NULL_RTX);
5556}
5557
5558/* Helper for extract_mentioned_regs; ACCUM is used to accumulate used
5559 registers. */
5560static rtx
1d088dee 5561extract_mentioned_regs_helper (rtx x, rtx accum)
a13d4ebf
AM
5562{
5563 int i;
5564 enum rtx_code code;
5565 const char * fmt;
5566
5567 /* Repeat is used to turn tail-recursion into iteration. */
5568 repeat:
5569
5570 if (x == 0)
47a3dae1 5571 return accum;
a13d4ebf
AM
5572
5573 code = GET_CODE (x);
5574 switch (code)
5575 {
5576 case REG:
47a3dae1 5577 return alloc_EXPR_LIST (0, x, accum);
a13d4ebf
AM
5578
5579 case MEM:
5580 x = XEXP (x, 0);
5581 goto repeat;
5582
5583 case PRE_DEC:
5584 case PRE_INC:
5585 case POST_DEC:
5586 case POST_INC:
47a3dae1 5587 /* We do not run this function with arguments having side effects. */
282899df 5588 gcc_unreachable ();
a13d4ebf
AM
5589
5590 case PC:
5591 case CC0: /*FIXME*/
5592 case CONST:
5593 case CONST_INT:
5594 case CONST_DOUBLE:
69ef87e2 5595 case CONST_VECTOR:
a13d4ebf
AM
5596 case SYMBOL_REF:
5597 case LABEL_REF:
5598 case ADDR_VEC:
5599 case ADDR_DIFF_VEC:
47a3dae1 5600 return accum;
a13d4ebf
AM
5601
5602 default:
5603 break;
5604 }
5605
5606 i = GET_RTX_LENGTH (code) - 1;
5607 fmt = GET_RTX_FORMAT (code);
589005ff 5608
a13d4ebf
AM
5609 for (; i >= 0; i--)
5610 {
5611 if (fmt[i] == 'e')
5612 {
5613 rtx tem = XEXP (x, i);
5614
5615 /* If we are about to do the last recursive call
47a3dae1 5616 needed at this level, change it into iteration. */
a13d4ebf
AM
5617 if (i == 0)
5618 {
5619 x = tem;
5620 goto repeat;
5621 }
589005ff 5622
47a3dae1 5623 accum = extract_mentioned_regs_helper (tem, accum);
a13d4ebf
AM
5624 }
5625 else if (fmt[i] == 'E')
5626 {
5627 int j;
589005ff 5628
a13d4ebf 5629 for (j = 0; j < XVECLEN (x, i); j++)
47a3dae1 5630 accum = extract_mentioned_regs_helper (XVECEXP (x, i, j), accum);
a13d4ebf
AM
5631 }
5632 }
5633
47a3dae1 5634 return accum;
a13d4ebf
AM
5635}
5636
47a3dae1
ZD
5637/* Determine whether INSN is MEM store pattern that we will consider moving.
5638 REGS_SET_BEFORE is bitmap of registers set before (and including) the
5639 current insn, REGS_SET_AFTER is bitmap of registers set after (and
5640 including) the insn in this basic block. We must be passing through BB from
5641 head to end, as we are using this fact to speed things up.
1d088dee 5642
47a3dae1
ZD
5643 The results are stored this way:
5644
5645 -- the first anticipatable expression is added into ANTIC_STORE_LIST
5646 -- if the processed expression is not anticipatable, NULL_RTX is added
5647 there instead, so that we can use it as indicator that no further
5648 expression of this type may be anticipatable
5649 -- if the expression is available, it is added as head of AVAIL_STORE_LIST;
5650 consequently, all of them but this head are dead and may be deleted.
5651 -- if the expression is not available, the insn due to that it fails to be
5652 available is stored in reaching_reg.
5653
5654 The things are complicated a bit by fact that there already may be stores
5655 to the same MEM from other blocks; also caller must take care of the
e0bb17a8 5656 necessary cleanup of the temporary markers after end of the basic block.
47a3dae1 5657 */
a13d4ebf
AM
5658
5659static void
1d088dee 5660find_moveable_store (rtx insn, int *regs_set_before, int *regs_set_after)
a13d4ebf
AM
5661{
5662 struct ls_expr * ptr;
47a3dae1
ZD
5663 rtx dest, set, tmp;
5664 int check_anticipatable, check_available;
5665 basic_block bb = BLOCK_FOR_INSN (insn);
a13d4ebf 5666
47a3dae1
ZD
5667 set = single_set (insn);
5668 if (!set)
a13d4ebf
AM
5669 return;
5670
47a3dae1 5671 dest = SET_DEST (set);
589005ff 5672
7b1b4aed 5673 if (! MEM_P (dest) || MEM_VOLATILE_P (dest)
a13d4ebf 5674 || GET_MODE (dest) == BLKmode)
aaa4ca30
AJ
5675 return;
5676
47a3dae1
ZD
5677 if (side_effects_p (dest))
5678 return;
aaa4ca30 5679
47a3dae1
ZD
5680 /* If we are handling exceptions, we must be careful with memory references
5681 that may trap. If we are not, the behavior is undefined, so we may just
5682 continue. */
94f24ddc 5683 if (flag_non_call_exceptions && may_trap_p (dest))
47a3dae1 5684 return;
1d088dee 5685
c2e2375e
UW
5686 /* Even if the destination cannot trap, the source may. In this case we'd
5687 need to handle updating the REG_EH_REGION note. */
5688 if (find_reg_note (insn, REG_EH_REGION, NULL_RTX))
5689 return;
5690
a13d4ebf 5691 ptr = ldst_entry (dest);
47a3dae1
ZD
5692 if (!ptr->pattern_regs)
5693 ptr->pattern_regs = extract_mentioned_regs (dest);
5694
5695 /* Do not check for anticipatability if we either found one anticipatable
5696 store already, or tested for one and found out that it was killed. */
5697 check_anticipatable = 0;
5698 if (!ANTIC_STORE_LIST (ptr))
5699 check_anticipatable = 1;
5700 else
5701 {
5702 tmp = XEXP (ANTIC_STORE_LIST (ptr), 0);
5703 if (tmp != NULL_RTX
5704 && BLOCK_FOR_INSN (tmp) != bb)
5705 check_anticipatable = 1;
5706 }
5707 if (check_anticipatable)
5708 {
5709 if (store_killed_before (dest, ptr->pattern_regs, insn, bb, regs_set_before))
5710 tmp = NULL_RTX;
5711 else
5712 tmp = insn;
5713 ANTIC_STORE_LIST (ptr) = alloc_INSN_LIST (tmp,
5714 ANTIC_STORE_LIST (ptr));
5715 }
a13d4ebf 5716
e0bb17a8 5717 /* It is not necessary to check whether store is available if we did
47a3dae1
ZD
5718 it successfully before; if we failed before, do not bother to check
5719 until we reach the insn that caused us to fail. */
5720 check_available = 0;
5721 if (!AVAIL_STORE_LIST (ptr))
5722 check_available = 1;
5723 else
5724 {
5725 tmp = XEXP (AVAIL_STORE_LIST (ptr), 0);
5726 if (BLOCK_FOR_INSN (tmp) != bb)
5727 check_available = 1;
5728 }
5729 if (check_available)
5730 {
5731 /* Check that we have already reached the insn at that the check
5732 failed last time. */
5733 if (LAST_AVAIL_CHECK_FAILURE (ptr))
5734 {
a813c111 5735 for (tmp = BB_END (bb);
47a3dae1
ZD
5736 tmp != insn && tmp != LAST_AVAIL_CHECK_FAILURE (ptr);
5737 tmp = PREV_INSN (tmp))
5738 continue;
5739 if (tmp == insn)
5740 check_available = 0;
5741 }
5742 else
5743 check_available = store_killed_after (dest, ptr->pattern_regs, insn,
5744 bb, regs_set_after,
5745 &LAST_AVAIL_CHECK_FAILURE (ptr));
5746 }
5747 if (!check_available)
5748 AVAIL_STORE_LIST (ptr) = alloc_INSN_LIST (insn, AVAIL_STORE_LIST (ptr));
5749}
1d088dee 5750
47a3dae1 5751/* Find available and anticipatable stores. */
a13d4ebf
AM
5752
5753static int
1d088dee 5754compute_store_table (void)
a13d4ebf 5755{
e0082a72
ZD
5756 int ret;
5757 basic_block bb;
aaa4ca30 5758 unsigned regno;
47a3dae1
ZD
5759 rtx insn, pat, tmp;
5760 int *last_set_in, *already_set;
5761 struct ls_expr * ptr, **prev_next_ptr_ptr;
aaa4ca30 5762
a13d4ebf
AM
5763 max_gcse_regno = max_reg_num ();
5764
703ad42b 5765 reg_set_in_block = sbitmap_vector_alloc (last_basic_block,
aaa4ca30 5766 max_gcse_regno);
d55bc081 5767 sbitmap_vector_zero (reg_set_in_block, last_basic_block);
a13d4ebf 5768 pre_ldst_mems = 0;
01c43039 5769 last_set_in = xcalloc (max_gcse_regno, sizeof (int));
47a3dae1 5770 already_set = xmalloc (sizeof (int) * max_gcse_regno);
aaa4ca30 5771
a13d4ebf 5772 /* Find all the stores we care about. */
e0082a72 5773 FOR_EACH_BB (bb)
a13d4ebf 5774 {
47a3dae1 5775 /* First compute the registers set in this block. */
47a3dae1
ZD
5776 regvec = last_set_in;
5777
a813c111
SB
5778 for (insn = BB_HEAD (bb);
5779 insn != NEXT_INSN (BB_END (bb));
47a3dae1
ZD
5780 insn = NEXT_INSN (insn))
5781 {
5782 if (! INSN_P (insn))
5783 continue;
5784
7b1b4aed 5785 if (CALL_P (insn))
47a3dae1
ZD
5786 {
5787 bool clobbers_all = false;
5788#ifdef NON_SAVING_SETJMP
5789 if (NON_SAVING_SETJMP
5790 && find_reg_note (insn, REG_SETJMP, NULL_RTX))
5791 clobbers_all = true;
5792#endif
5793
5794 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
5795 if (clobbers_all
5796 || TEST_HARD_REG_BIT (regs_invalidated_by_call, regno))
01c43039
RE
5797 {
5798 last_set_in[regno] = INSN_UID (insn);
5799 SET_BIT (reg_set_in_block[bb->index], regno);
5800 }
47a3dae1
ZD
5801 }
5802
5803 pat = PATTERN (insn);
5804 compute_store_table_current_insn = insn;
01c43039 5805 note_stores (pat, reg_set_info, reg_set_in_block[bb->index]);
47a3dae1
ZD
5806 }
5807
47a3dae1
ZD
5808 /* Now find the stores. */
5809 memset (already_set, 0, sizeof (int) * max_gcse_regno);
5810 regvec = already_set;
a813c111
SB
5811 for (insn = BB_HEAD (bb);
5812 insn != NEXT_INSN (BB_END (bb));
47a3dae1 5813 insn = NEXT_INSN (insn))
a13d4ebf 5814 {
19652adf 5815 if (! INSN_P (insn))
a13d4ebf
AM
5816 continue;
5817
7b1b4aed 5818 if (CALL_P (insn))
aaa4ca30 5819 {
19652adf 5820 bool clobbers_all = false;
589005ff 5821#ifdef NON_SAVING_SETJMP
19652adf
ZW
5822 if (NON_SAVING_SETJMP
5823 && find_reg_note (insn, REG_SETJMP, NULL_RTX))
5824 clobbers_all = true;
5825#endif
5826
aaa4ca30 5827 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
19652adf
ZW
5828 if (clobbers_all
5829 || TEST_HARD_REG_BIT (regs_invalidated_by_call, regno))
47a3dae1 5830 already_set[regno] = 1;
aaa4ca30 5831 }
589005ff 5832
a13d4ebf 5833 pat = PATTERN (insn);
aaa4ca30 5834 note_stores (pat, reg_set_info, NULL);
589005ff 5835
a13d4ebf 5836 /* Now that we've marked regs, look for stores. */
47a3dae1
ZD
5837 find_moveable_store (insn, already_set, last_set_in);
5838
5839 /* Unmark regs that are no longer set. */
01c43039
RE
5840 compute_store_table_current_insn = insn;
5841 note_stores (pat, reg_clear_last_set, last_set_in);
7b1b4aed 5842 if (CALL_P (insn))
01c43039
RE
5843 {
5844 bool clobbers_all = false;
5845#ifdef NON_SAVING_SETJMP
5846 if (NON_SAVING_SETJMP
5847 && find_reg_note (insn, REG_SETJMP, NULL_RTX))
5848 clobbers_all = true;
5849#endif
5850
5851 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
5852 if ((clobbers_all
5853 || TEST_HARD_REG_BIT (regs_invalidated_by_call, regno))
5854 && last_set_in[regno] == INSN_UID (insn))
5855 last_set_in[regno] = 0;
5856 }
47a3dae1
ZD
5857 }
5858
01c43039
RE
5859#ifdef ENABLE_CHECKING
5860 /* last_set_in should now be all-zero. */
5861 for (regno = 0; regno < max_gcse_regno; regno++)
282899df 5862 gcc_assert (!last_set_in[regno]);
01c43039
RE
5863#endif
5864
47a3dae1
ZD
5865 /* Clear temporary marks. */
5866 for (ptr = first_ls_expr (); ptr != NULL; ptr = next_ls_expr (ptr))
5867 {
5868 LAST_AVAIL_CHECK_FAILURE(ptr) = NULL_RTX;
5869 if (ANTIC_STORE_LIST (ptr)
5870 && (tmp = XEXP (ANTIC_STORE_LIST (ptr), 0)) == NULL_RTX)
5871 ANTIC_STORE_LIST (ptr) = XEXP (ANTIC_STORE_LIST (ptr), 1);
5872 }
5873 }
5874
5875 /* Remove the stores that are not available anywhere, as there will
5876 be no opportunity to optimize them. */
5877 for (ptr = pre_ldst_mems, prev_next_ptr_ptr = &pre_ldst_mems;
5878 ptr != NULL;
5879 ptr = *prev_next_ptr_ptr)
5880 {
5881 if (!AVAIL_STORE_LIST (ptr))
5882 {
5883 *prev_next_ptr_ptr = ptr->next;
5884 free_ldst_entry (ptr);
a13d4ebf 5885 }
47a3dae1
ZD
5886 else
5887 prev_next_ptr_ptr = &ptr->next;
a13d4ebf
AM
5888 }
5889
5890 ret = enumerate_ldsts ();
589005ff 5891
a13d4ebf
AM
5892 if (gcse_file)
5893 {
47a3dae1 5894 fprintf (gcse_file, "ST_avail and ST_antic (shown under loads..)\n");
a13d4ebf
AM
5895 print_ldst_list (gcse_file);
5896 }
589005ff 5897
47a3dae1
ZD
5898 free (last_set_in);
5899 free (already_set);
a13d4ebf
AM
5900 return ret;
5901}
5902
3b14e3af
ZD
5903/* Check to see if the load X is aliased with STORE_PATTERN.
5904 AFTER is true if we are checking the case when STORE_PATTERN occurs
5905 after the X. */
a13d4ebf 5906
47a3dae1 5907static bool
3b14e3af 5908load_kills_store (rtx x, rtx store_pattern, int after)
a13d4ebf 5909{
3b14e3af
ZD
5910 if (after)
5911 return anti_dependence (x, store_pattern);
5912 else
5913 return true_dependence (store_pattern, GET_MODE (store_pattern), x,
5914 rtx_addr_varies_p);
a13d4ebf
AM
5915}
5916
589005ff 5917/* Go through the entire insn X, looking for any loads which might alias
3b14e3af
ZD
5918 STORE_PATTERN. Return true if found.
5919 AFTER is true if we are checking the case when STORE_PATTERN occurs
5920 after the insn X. */
a13d4ebf 5921
47a3dae1 5922static bool
3b14e3af 5923find_loads (rtx x, rtx store_pattern, int after)
a13d4ebf
AM
5924{
5925 const char * fmt;
8e42ace1 5926 int i, j;
47a3dae1 5927 int ret = false;
a13d4ebf 5928
24a28584 5929 if (!x)
47a3dae1 5930 return false;
24a28584 5931
589005ff 5932 if (GET_CODE (x) == SET)
a13d4ebf
AM
5933 x = SET_SRC (x);
5934
7b1b4aed 5935 if (MEM_P (x))
a13d4ebf 5936 {
3b14e3af 5937 if (load_kills_store (x, store_pattern, after))
47a3dae1 5938 return true;
a13d4ebf
AM
5939 }
5940
5941 /* Recursively process the insn. */
5942 fmt = GET_RTX_FORMAT (GET_CODE (x));
589005ff 5943
a13d4ebf
AM
5944 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0 && !ret; i--)
5945 {
5946 if (fmt[i] == 'e')
3b14e3af 5947 ret |= find_loads (XEXP (x, i), store_pattern, after);
a13d4ebf
AM
5948 else if (fmt[i] == 'E')
5949 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3b14e3af 5950 ret |= find_loads (XVECEXP (x, i, j), store_pattern, after);
a13d4ebf
AM
5951 }
5952 return ret;
5953}
5954
589005ff 5955/* Check if INSN kills the store pattern X (is aliased with it).
3b14e3af
ZD
5956 AFTER is true if we are checking the case when store X occurs
5957 after the insn. Return true if it it does. */
a13d4ebf 5958
47a3dae1 5959static bool
3b14e3af 5960store_killed_in_insn (rtx x, rtx x_regs, rtx insn, int after)
a13d4ebf 5961{
d088acea 5962 rtx reg, base, note;
94f24ddc 5963
735e8085 5964 if (!INSN_P (insn))
47a3dae1 5965 return false;
589005ff 5966
7b1b4aed 5967 if (CALL_P (insn))
a13d4ebf 5968 {
1218665b
JJ
5969 /* A normal or pure call might read from pattern,
5970 but a const call will not. */
47a3dae1
ZD
5971 if (! CONST_OR_PURE_CALL_P (insn) || pure_call_p (insn))
5972 return true;
5973
94f24ddc
ZD
5974 /* But even a const call reads its parameters. Check whether the
5975 base of some of registers used in mem is stack pointer. */
5976 for (reg = x_regs; reg; reg = XEXP (reg, 1))
5977 {
bc083e18 5978 base = find_base_term (XEXP (reg, 0));
94f24ddc
ZD
5979 if (!base
5980 || (GET_CODE (base) == ADDRESS
5981 && GET_MODE (base) == Pmode
5982 && XEXP (base, 0) == stack_pointer_rtx))
5983 return true;
5984 }
47a3dae1
ZD
5985
5986 return false;
a13d4ebf 5987 }
589005ff 5988
a13d4ebf
AM
5989 if (GET_CODE (PATTERN (insn)) == SET)
5990 {
5991 rtx pat = PATTERN (insn);
3b14e3af
ZD
5992 rtx dest = SET_DEST (pat);
5993
5994 if (GET_CODE (dest) == SIGN_EXTRACT
5995 || GET_CODE (dest) == ZERO_EXTRACT)
5996 dest = XEXP (dest, 0);
5997
a13d4ebf 5998 /* Check for memory stores to aliased objects. */
7b1b4aed 5999 if (MEM_P (dest)
3b14e3af
ZD
6000 && !expr_equiv_p (dest, x))
6001 {
6002 if (after)
6003 {
6004 if (output_dependence (dest, x))
6005 return true;
6006 }
6007 else
6008 {
6009 if (output_dependence (x, dest))
6010 return true;
6011 }
6012 }
d088acea
ZD
6013 if (find_loads (SET_SRC (pat), x, after))
6014 return true;
a13d4ebf 6015 }
d088acea
ZD
6016 else if (find_loads (PATTERN (insn), x, after))
6017 return true;
6018
6019 /* If this insn has a REG_EQUAL or REG_EQUIV note referencing a memory
6020 location aliased with X, then this insn kills X. */
6021 note = find_reg_equal_equiv_note (insn);
6022 if (! note)
6023 return false;
6024 note = XEXP (note, 0);
6025
6026 /* However, if the note represents a must alias rather than a may
6027 alias relationship, then it does not kill X. */
6028 if (expr_equiv_p (note, x))
6029 return false;
6030
6031 /* See if there are any aliased loads in the note. */
6032 return find_loads (note, x, after);
a13d4ebf
AM
6033}
6034
47a3dae1
ZD
6035/* Returns true if the expression X is loaded or clobbered on or after INSN
6036 within basic block BB. REGS_SET_AFTER is bitmap of registers set in
6037 or after the insn. X_REGS is list of registers mentioned in X. If the store
6038 is killed, return the last insn in that it occurs in FAIL_INSN. */
a13d4ebf 6039
47a3dae1 6040static bool
1d088dee
AJ
6041store_killed_after (rtx x, rtx x_regs, rtx insn, basic_block bb,
6042 int *regs_set_after, rtx *fail_insn)
a13d4ebf 6043{
a813c111 6044 rtx last = BB_END (bb), act;
aaa4ca30 6045
47a3dae1 6046 if (!store_ops_ok (x_regs, regs_set_after))
1d088dee 6047 {
47a3dae1
ZD
6048 /* We do not know where it will happen. */
6049 if (fail_insn)
6050 *fail_insn = NULL_RTX;
6051 return true;
6052 }
a13d4ebf 6053
47a3dae1
ZD
6054 /* Scan from the end, so that fail_insn is determined correctly. */
6055 for (act = last; act != PREV_INSN (insn); act = PREV_INSN (act))
3b14e3af 6056 if (store_killed_in_insn (x, x_regs, act, false))
47a3dae1
ZD
6057 {
6058 if (fail_insn)
6059 *fail_insn = act;
6060 return true;
6061 }
589005ff 6062
47a3dae1 6063 return false;
a13d4ebf 6064}
1d088dee 6065
47a3dae1
ZD
6066/* Returns true if the expression X is loaded or clobbered on or before INSN
6067 within basic block BB. X_REGS is list of registers mentioned in X.
6068 REGS_SET_BEFORE is bitmap of registers set before or in this insn. */
6069static bool
1d088dee
AJ
6070store_killed_before (rtx x, rtx x_regs, rtx insn, basic_block bb,
6071 int *regs_set_before)
a13d4ebf 6072{
a813c111 6073 rtx first = BB_HEAD (bb);
a13d4ebf 6074
47a3dae1
ZD
6075 if (!store_ops_ok (x_regs, regs_set_before))
6076 return true;
a13d4ebf 6077
47a3dae1 6078 for ( ; insn != PREV_INSN (first); insn = PREV_INSN (insn))
3b14e3af 6079 if (store_killed_in_insn (x, x_regs, insn, true))
47a3dae1 6080 return true;
589005ff 6081
47a3dae1 6082 return false;
a13d4ebf 6083}
1d088dee 6084
47a3dae1
ZD
6085/* Fill in available, anticipatable, transparent and kill vectors in
6086 STORE_DATA, based on lists of available and anticipatable stores. */
a13d4ebf 6087static void
1d088dee 6088build_store_vectors (void)
a13d4ebf 6089{
47a3dae1
ZD
6090 basic_block bb;
6091 int *regs_set_in_block;
a13d4ebf
AM
6092 rtx insn, st;
6093 struct ls_expr * ptr;
47a3dae1 6094 unsigned regno;
a13d4ebf
AM
6095
6096 /* Build the gen_vector. This is any store in the table which is not killed
6097 by aliasing later in its block. */
703ad42b 6098 ae_gen = sbitmap_vector_alloc (last_basic_block, num_stores);
d55bc081 6099 sbitmap_vector_zero (ae_gen, last_basic_block);
a13d4ebf 6100
703ad42b 6101 st_antloc = sbitmap_vector_alloc (last_basic_block, num_stores);
d55bc081 6102 sbitmap_vector_zero (st_antloc, last_basic_block);
aaa4ca30 6103
a13d4ebf 6104 for (ptr = first_ls_expr (); ptr != NULL; ptr = next_ls_expr (ptr))
589005ff 6105 {
47a3dae1 6106 for (st = AVAIL_STORE_LIST (ptr); st != NULL; st = XEXP (st, 1))
a13d4ebf
AM
6107 {
6108 insn = XEXP (st, 0);
e2d2ed72 6109 bb = BLOCK_FOR_INSN (insn);
589005ff 6110
47a3dae1
ZD
6111 /* If we've already seen an available expression in this block,
6112 we can delete this one (It occurs earlier in the block). We'll
6113 copy the SRC expression to an unused register in case there
6114 are any side effects. */
6115 if (TEST_BIT (ae_gen[bb->index], ptr->index))
a13d4ebf 6116 {
47a3dae1
ZD
6117 rtx r = gen_reg_rtx (GET_MODE (ptr->pattern));
6118 if (gcse_file)
6119 fprintf (gcse_file, "Removing redundant store:\n");
d088acea 6120 replace_store_insn (r, XEXP (st, 0), bb, ptr);
47a3dae1 6121 continue;
a13d4ebf 6122 }
47a3dae1 6123 SET_BIT (ae_gen[bb->index], ptr->index);
a13d4ebf 6124 }
589005ff 6125
47a3dae1
ZD
6126 for (st = ANTIC_STORE_LIST (ptr); st != NULL; st = XEXP (st, 1))
6127 {
6128 insn = XEXP (st, 0);
6129 bb = BLOCK_FOR_INSN (insn);
6130 SET_BIT (st_antloc[bb->index], ptr->index);
6131 }
a13d4ebf 6132 }
589005ff 6133
703ad42b 6134 ae_kill = sbitmap_vector_alloc (last_basic_block, num_stores);
d55bc081 6135 sbitmap_vector_zero (ae_kill, last_basic_block);
a13d4ebf 6136
703ad42b 6137 transp = sbitmap_vector_alloc (last_basic_block, num_stores);
d55bc081 6138 sbitmap_vector_zero (transp, last_basic_block);
47a3dae1 6139 regs_set_in_block = xmalloc (sizeof (int) * max_gcse_regno);
a13d4ebf 6140
47a3dae1
ZD
6141 FOR_EACH_BB (bb)
6142 {
6143 for (regno = 0; regno < max_gcse_regno; regno++)
6144 regs_set_in_block[regno] = TEST_BIT (reg_set_in_block[bb->index], regno);
6145
6146 for (ptr = first_ls_expr (); ptr != NULL; ptr = next_ls_expr (ptr))
6147 {
a813c111 6148 if (store_killed_after (ptr->pattern, ptr->pattern_regs, BB_HEAD (bb),
47a3dae1
ZD
6149 bb, regs_set_in_block, NULL))
6150 {
e0bb17a8 6151 /* It should not be necessary to consider the expression
47a3dae1
ZD
6152 killed if it is both anticipatable and available. */
6153 if (!TEST_BIT (st_antloc[bb->index], ptr->index)
6154 || !TEST_BIT (ae_gen[bb->index], ptr->index))
6155 SET_BIT (ae_kill[bb->index], ptr->index);
1d088dee
AJ
6156 }
6157 else
6158 SET_BIT (transp[bb->index], ptr->index);
6159 }
47a3dae1
ZD
6160 }
6161
6162 free (regs_set_in_block);
aaa4ca30 6163
589005ff 6164 if (gcse_file)
aaa4ca30 6165 {
d55bc081
ZD
6166 dump_sbitmap_vector (gcse_file, "st_antloc", "", st_antloc, last_basic_block);
6167 dump_sbitmap_vector (gcse_file, "st_kill", "", ae_kill, last_basic_block);
6168 dump_sbitmap_vector (gcse_file, "Transpt", "", transp, last_basic_block);
6169 dump_sbitmap_vector (gcse_file, "st_avloc", "", ae_gen, last_basic_block);
a13d4ebf
AM
6170 }
6171}
6172
fbe5a4a6 6173/* Insert an instruction at the beginning of a basic block, and update
a813c111 6174 the BB_HEAD if needed. */
a13d4ebf 6175
589005ff 6176static void
1d088dee 6177insert_insn_start_bb (rtx insn, basic_block bb)
a13d4ebf
AM
6178{
6179 /* Insert at start of successor block. */
a813c111
SB
6180 rtx prev = PREV_INSN (BB_HEAD (bb));
6181 rtx before = BB_HEAD (bb);
a13d4ebf
AM
6182 while (before != 0)
6183 {
7b1b4aed
SB
6184 if (! LABEL_P (before)
6185 && (! NOTE_P (before)
a13d4ebf
AM
6186 || NOTE_LINE_NUMBER (before) != NOTE_INSN_BASIC_BLOCK))
6187 break;
6188 prev = before;
a813c111 6189 if (prev == BB_END (bb))
a13d4ebf
AM
6190 break;
6191 before = NEXT_INSN (before);
6192 }
6193
a7102479 6194 insn = emit_insn_after_noloc (insn, prev);
a13d4ebf 6195
a13d4ebf
AM
6196 if (gcse_file)
6197 {
6198 fprintf (gcse_file, "STORE_MOTION insert store at start of BB %d:\n",
0b17ab2f 6199 bb->index);
a13d4ebf
AM
6200 print_inline_rtx (gcse_file, insn, 6);
6201 fprintf (gcse_file, "\n");
6202 }
6203}
6204
6205/* This routine will insert a store on an edge. EXPR is the ldst entry for
cc2902df 6206 the memory reference, and E is the edge to insert it on. Returns nonzero
a13d4ebf
AM
6207 if an edge insertion was performed. */
6208
6209static int
1d088dee 6210insert_store (struct ls_expr * expr, edge e)
a13d4ebf
AM
6211{
6212 rtx reg, insn;
e2d2ed72 6213 basic_block bb;
a13d4ebf 6214 edge tmp;
628f6a4e 6215 edge_iterator ei;
a13d4ebf
AM
6216
6217 /* We did all the deleted before this insert, so if we didn't delete a
6218 store, then we haven't set the reaching reg yet either. */
6219 if (expr->reaching_reg == NULL_RTX)
6220 return 0;
6221
a0c8285b
JH
6222 if (e->flags & EDGE_FAKE)
6223 return 0;
6224
a13d4ebf 6225 reg = expr->reaching_reg;
47a3dae1 6226 insn = gen_move_insn (copy_rtx (expr->pattern), reg);
589005ff 6227
a13d4ebf
AM
6228 /* If we are inserting this expression on ALL predecessor edges of a BB,
6229 insert it at the start of the BB, and reset the insert bits on the other
ff7cc307 6230 edges so we don't try to insert it on the other edges. */
e2d2ed72 6231 bb = e->dest;
628f6a4e 6232 FOR_EACH_EDGE (tmp, ei, e->dest->preds)
3f2eae23 6233 if (!(tmp->flags & EDGE_FAKE))
a0c8285b
JH
6234 {
6235 int index = EDGE_INDEX (edge_list, tmp->src, tmp->dest);
282899df
NS
6236
6237 gcc_assert (index != EDGE_INDEX_NO_EDGE);
a0c8285b
JH
6238 if (! TEST_BIT (pre_insert_map[index], expr->index))
6239 break;
6240 }
a13d4ebf
AM
6241
6242 /* If tmp is NULL, we found an insertion on every edge, blank the
6243 insertion vector for these edges, and insert at the start of the BB. */
e2d2ed72 6244 if (!tmp && bb != EXIT_BLOCK_PTR)
a13d4ebf 6245 {
628f6a4e 6246 FOR_EACH_EDGE (tmp, ei, e->dest->preds)
a13d4ebf
AM
6247 {
6248 int index = EDGE_INDEX (edge_list, tmp->src, tmp->dest);
6249 RESET_BIT (pre_insert_map[index], expr->index);
6250 }
6251 insert_insn_start_bb (insn, bb);
6252 return 0;
6253 }
589005ff 6254
a13d4ebf
AM
6255 /* We can't insert on this edge, so we'll insert at the head of the
6256 successors block. See Morgan, sec 10.5. */
6257 if ((e->flags & EDGE_ABNORMAL) == EDGE_ABNORMAL)
6258 {
6259 insert_insn_start_bb (insn, bb);
6260 return 0;
6261 }
6262
6263 insert_insn_on_edge (insn, e);
589005ff 6264
a13d4ebf
AM
6265 if (gcse_file)
6266 {
6267 fprintf (gcse_file, "STORE_MOTION insert insn on edge (%d, %d):\n",
0b17ab2f 6268 e->src->index, e->dest->index);
a13d4ebf
AM
6269 print_inline_rtx (gcse_file, insn, 6);
6270 fprintf (gcse_file, "\n");
6271 }
589005ff 6272
a13d4ebf
AM
6273 return 1;
6274}
6275
d088acea
ZD
6276/* Remove any REG_EQUAL or REG_EQUIV notes containing a reference to the
6277 memory location in SMEXPR set in basic block BB.
6278
6279 This could be rather expensive. */
6280
6281static void
6282remove_reachable_equiv_notes (basic_block bb, struct ls_expr *smexpr)
6283{
628f6a4e
BE
6284 edge_iterator *stack, ei;
6285 int sp;
6286 edge act;
d088acea 6287 sbitmap visited = sbitmap_alloc (last_basic_block);
d088acea
ZD
6288 rtx last, insn, note;
6289 rtx mem = smexpr->pattern;
6290
628f6a4e
BE
6291 stack = xmalloc (sizeof (edge_iterator) * n_basic_blocks);
6292 sp = 0;
6293 ei = ei_start (bb->succs);
6294
d088acea 6295 sbitmap_zero (visited);
d088acea 6296
f76ccf60 6297 act = (EDGE_COUNT (ei_container (ei)) > 0 ? EDGE_I (ei_container (ei), 0) : NULL);
d088acea
ZD
6298 while (1)
6299 {
6300 if (!act)
6301 {
628f6a4e 6302 if (!sp)
d088acea
ZD
6303 {
6304 free (stack);
6305 sbitmap_free (visited);
6306 return;
6307 }
628f6a4e 6308 act = ei_edge (stack[--sp]);
d088acea
ZD
6309 }
6310 bb = act->dest;
7b1b4aed 6311
d088acea 6312 if (bb == EXIT_BLOCK_PTR
d1c6a401 6313 || TEST_BIT (visited, bb->index))
d088acea 6314 {
628f6a4e
BE
6315 if (!ei_end_p (ei))
6316 ei_next (&ei);
6317 act = (! ei_end_p (ei)) ? ei_edge (ei) : NULL;
d088acea
ZD
6318 continue;
6319 }
6320 SET_BIT (visited, bb->index);
6321
6322 if (TEST_BIT (st_antloc[bb->index], smexpr->index))
6323 {
6324 for (last = ANTIC_STORE_LIST (smexpr);
6325 BLOCK_FOR_INSN (XEXP (last, 0)) != bb;
6326 last = XEXP (last, 1))
6327 continue;
6328 last = XEXP (last, 0);
6329 }
6330 else
a813c111 6331 last = NEXT_INSN (BB_END (bb));
7b1b4aed 6332
a813c111 6333 for (insn = BB_HEAD (bb); insn != last; insn = NEXT_INSN (insn))
d088acea
ZD
6334 if (INSN_P (insn))
6335 {
6336 note = find_reg_equal_equiv_note (insn);
6337 if (!note || !expr_equiv_p (XEXP (note, 0), mem))
6338 continue;
6339
6340 if (gcse_file)
6341 fprintf (gcse_file, "STORE_MOTION drop REG_EQUAL note at insn %d:\n",
6342 INSN_UID (insn));
6343 remove_note (insn, note);
6344 }
628f6a4e
BE
6345
6346 if (!ei_end_p (ei))
6347 ei_next (&ei);
6348 act = (! ei_end_p (ei)) ? ei_edge (ei) : NULL;
6349
6350 if (EDGE_COUNT (bb->succs) > 0)
d088acea
ZD
6351 {
6352 if (act)
628f6a4e
BE
6353 stack[sp++] = ei;
6354 ei = ei_start (bb->succs);
f76ccf60 6355 act = (EDGE_COUNT (ei_container (ei)) > 0 ? EDGE_I (ei_container (ei), 0) : NULL);
d088acea
ZD
6356 }
6357 }
6358}
6359
a13d4ebf
AM
6360/* This routine will replace a store with a SET to a specified register. */
6361
6362static void
d088acea 6363replace_store_insn (rtx reg, rtx del, basic_block bb, struct ls_expr *smexpr)
a13d4ebf 6364{
d7fe1183 6365 rtx insn, mem, note, set, ptr, pair;
589005ff 6366
d088acea 6367 mem = smexpr->pattern;
9a318d30 6368 insn = gen_move_insn (reg, SET_SRC (single_set (del)));
a13d4ebf 6369 insn = emit_insn_after (insn, del);
589005ff 6370
a13d4ebf
AM
6371 if (gcse_file)
6372 {
589005ff 6373 fprintf (gcse_file,
0b17ab2f 6374 "STORE_MOTION delete insn in BB %d:\n ", bb->index);
a13d4ebf 6375 print_inline_rtx (gcse_file, del, 6);
8e42ace1 6376 fprintf (gcse_file, "\nSTORE MOTION replaced with insn:\n ");
a13d4ebf 6377 print_inline_rtx (gcse_file, insn, 6);
8e42ace1 6378 fprintf (gcse_file, "\n");
a13d4ebf 6379 }
589005ff 6380
d088acea
ZD
6381 for (ptr = ANTIC_STORE_LIST (smexpr); ptr; ptr = XEXP (ptr, 1))
6382 if (XEXP (ptr, 0) == del)
6383 {
6384 XEXP (ptr, 0) = insn;
6385 break;
6386 }
d7fe1183
ZD
6387
6388 /* Move the notes from the deleted insn to its replacement, and patch
6389 up the LIBCALL notes. */
6390 REG_NOTES (insn) = REG_NOTES (del);
6391
6392 note = find_reg_note (insn, REG_RETVAL, NULL_RTX);
6393 if (note)
6394 {
6395 pair = XEXP (note, 0);
6396 note = find_reg_note (pair, REG_LIBCALL, NULL_RTX);
6397 XEXP (note, 0) = insn;
6398 }
6399 note = find_reg_note (insn, REG_LIBCALL, NULL_RTX);
6400 if (note)
6401 {
6402 pair = XEXP (note, 0);
6403 note = find_reg_note (pair, REG_RETVAL, NULL_RTX);
6404 XEXP (note, 0) = insn;
6405 }
6406
49ce134f 6407 delete_insn (del);
d088acea
ZD
6408
6409 /* Now we must handle REG_EQUAL notes whose contents is equal to the mem;
6410 they are no longer accurate provided that they are reached by this
6411 definition, so drop them. */
a813c111 6412 for (; insn != NEXT_INSN (BB_END (bb)); insn = NEXT_INSN (insn))
d088acea
ZD
6413 if (INSN_P (insn))
6414 {
6415 set = single_set (insn);
6416 if (!set)
6417 continue;
6418 if (expr_equiv_p (SET_DEST (set), mem))
6419 return;
6420 note = find_reg_equal_equiv_note (insn);
6421 if (!note || !expr_equiv_p (XEXP (note, 0), mem))
6422 continue;
6423
6424 if (gcse_file)
6425 fprintf (gcse_file, "STORE_MOTION drop REG_EQUAL note at insn %d:\n",
6426 INSN_UID (insn));
6427 remove_note (insn, note);
6428 }
6429 remove_reachable_equiv_notes (bb, smexpr);
a13d4ebf
AM
6430}
6431
6432
6433/* Delete a store, but copy the value that would have been stored into
6434 the reaching_reg for later storing. */
6435
6436static void
1d088dee 6437delete_store (struct ls_expr * expr, basic_block bb)
a13d4ebf
AM
6438{
6439 rtx reg, i, del;
6440
6441 if (expr->reaching_reg == NULL_RTX)
6442 expr->reaching_reg = gen_reg_rtx (GET_MODE (expr->pattern));
a13d4ebf 6443
a13d4ebf 6444 reg = expr->reaching_reg;
589005ff 6445
a13d4ebf
AM
6446 for (i = AVAIL_STORE_LIST (expr); i; i = XEXP (i, 1))
6447 {
6448 del = XEXP (i, 0);
e2d2ed72 6449 if (BLOCK_FOR_INSN (del) == bb)
a13d4ebf 6450 {
589005ff 6451 /* We know there is only one since we deleted redundant
a13d4ebf 6452 ones during the available computation. */
d088acea 6453 replace_store_insn (reg, del, bb, expr);
a13d4ebf
AM
6454 break;
6455 }
6456 }
6457}
6458
6459/* Free memory used by store motion. */
6460
589005ff 6461static void
1d088dee 6462free_store_memory (void)
a13d4ebf
AM
6463{
6464 free_ldst_mems ();
589005ff 6465
a13d4ebf 6466 if (ae_gen)
5a660bff 6467 sbitmap_vector_free (ae_gen);
a13d4ebf 6468 if (ae_kill)
5a660bff 6469 sbitmap_vector_free (ae_kill);
a13d4ebf 6470 if (transp)
5a660bff 6471 sbitmap_vector_free (transp);
a13d4ebf 6472 if (st_antloc)
5a660bff 6473 sbitmap_vector_free (st_antloc);
a13d4ebf 6474 if (pre_insert_map)
5a660bff 6475 sbitmap_vector_free (pre_insert_map);
a13d4ebf 6476 if (pre_delete_map)
5a660bff 6477 sbitmap_vector_free (pre_delete_map);
aaa4ca30
AJ
6478 if (reg_set_in_block)
6479 sbitmap_vector_free (reg_set_in_block);
589005ff 6480
a13d4ebf
AM
6481 ae_gen = ae_kill = transp = st_antloc = NULL;
6482 pre_insert_map = pre_delete_map = reg_set_in_block = NULL;
6483}
6484
6485/* Perform store motion. Much like gcse, except we move expressions the
6486 other way by looking at the flowgraph in reverse. */
6487
6488static void
1d088dee 6489store_motion (void)
a13d4ebf 6490{
e0082a72 6491 basic_block bb;
0b17ab2f 6492 int x;
a13d4ebf 6493 struct ls_expr * ptr;
adfcce61 6494 int update_flow = 0;
aaa4ca30 6495
a13d4ebf
AM
6496 if (gcse_file)
6497 {
6498 fprintf (gcse_file, "before store motion\n");
6499 print_rtl (gcse_file, get_insns ());
6500 }
6501
a13d4ebf 6502 init_alias_analysis ();
aaa4ca30 6503
47a3dae1 6504 /* Find all the available and anticipatable stores. */
a13d4ebf
AM
6505 num_stores = compute_store_table ();
6506 if (num_stores == 0)
6507 {
aaa4ca30 6508 sbitmap_vector_free (reg_set_in_block);
a13d4ebf
AM
6509 end_alias_analysis ();
6510 return;
6511 }
6512
47a3dae1 6513 /* Now compute kill & transp vectors. */
a13d4ebf 6514 build_store_vectors ();
47a3dae1 6515 add_noreturn_fake_exit_edges ();
2a868ea4 6516 connect_infinite_loops_to_exit ();
a13d4ebf 6517
589005ff
KH
6518 edge_list = pre_edge_rev_lcm (gcse_file, num_stores, transp, ae_gen,
6519 st_antloc, ae_kill, &pre_insert_map,
a13d4ebf
AM
6520 &pre_delete_map);
6521
6522 /* Now we want to insert the new stores which are going to be needed. */
6523 for (ptr = first_ls_expr (); ptr != NULL; ptr = next_ls_expr (ptr))
6524 {
e0082a72
ZD
6525 FOR_EACH_BB (bb)
6526 if (TEST_BIT (pre_delete_map[bb->index], ptr->index))
6527 delete_store (ptr, bb);
a13d4ebf 6528
0b17ab2f
RH
6529 for (x = 0; x < NUM_EDGES (edge_list); x++)
6530 if (TEST_BIT (pre_insert_map[x], ptr->index))
6531 update_flow |= insert_store (ptr, INDEX_EDGE (edge_list, x));
a13d4ebf
AM
6532 }
6533
6534 if (update_flow)
6535 commit_edge_insertions ();
aaa4ca30 6536
a13d4ebf
AM
6537 free_store_memory ();
6538 free_edge_list (edge_list);
6809cbf9 6539 remove_fake_exit_edges ();
a13d4ebf
AM
6540 end_alias_analysis ();
6541}
e2500fed 6542
a0134312
RS
6543\f
6544/* Entry point for jump bypassing optimization pass. */
6545
6546int
1d088dee 6547bypass_jumps (FILE *file)
a0134312
RS
6548{
6549 int changed;
6550
6551 /* We do not construct an accurate cfg in functions which call
6552 setjmp, so just punt to be safe. */
6553 if (current_function_calls_setjmp)
6554 return 0;
6555
6556 /* For calling dump_foo fns from gdb. */
6557 debug_stderr = stderr;
6558 gcse_file = file;
6559
6560 /* Identify the basic block information for this function, including
6561 successors and predecessors. */
6562 max_gcse_regno = max_reg_num ();
6563
6564 if (file)
6565 dump_flow_info (file);
6566
6614fd40 6567 /* Return if there's nothing to do, or it is too expensive. */
d128effb 6568 if (n_basic_blocks <= 1 || is_too_expensive (_ ("jump bypassing disabled")))
a0134312
RS
6569 return 0;
6570
a0134312
RS
6571 gcc_obstack_init (&gcse_obstack);
6572 bytes_used = 0;
6573
6574 /* We need alias. */
6575 init_alias_analysis ();
6576
6577 /* Record where pseudo-registers are set. This data is kept accurate
6578 during each pass. ??? We could also record hard-reg information here
6579 [since it's unchanging], however it is currently done during hash table
6580 computation.
6581
6582 It may be tempting to compute MEM set information here too, but MEM sets
6583 will be subject to code motion one day and thus we need to compute
6584 information about memory sets when we build the hash tables. */
6585
6586 alloc_reg_set_mem (max_gcse_regno);
6587 compute_sets (get_insns ());
6588
6589 max_gcse_regno = max_reg_num ();
6590 alloc_gcse_mem (get_insns ());
27fb79ad 6591 changed = one_cprop_pass (MAX_GCSE_PASSES + 2, 1, 1);
a0134312
RS
6592 free_gcse_mem ();
6593
6594 if (file)
6595 {
6596 fprintf (file, "BYPASS of %s: %d basic blocks, ",
faed5cc3 6597 current_function_name (), n_basic_blocks);
a0134312
RS
6598 fprintf (file, "%d bytes\n\n", bytes_used);
6599 }
6600
6601 obstack_free (&gcse_obstack, NULL);
6602 free_reg_set_mem ();
6603
6604 /* We are finished with alias. */
6605 end_alias_analysis ();
6606 allocate_reg_info (max_reg_num (), FALSE, FALSE);
6607
6608 return changed;
6609}
6610
d128effb
NS
6611/* Return true if the graph is too expensive to optimize. PASS is the
6612 optimization about to be performed. */
6613
6614static bool
6615is_too_expensive (const char *pass)
6616{
6617 /* Trying to perform global optimizations on flow graphs which have
6618 a high connectivity will take a long time and is unlikely to be
6619 particularly useful.
7b1b4aed 6620
d128effb
NS
6621 In normal circumstances a cfg should have about twice as many
6622 edges as blocks. But we do not want to punish small functions
6623 which have a couple switch statements. Rather than simply
6624 threshold the number of blocks, uses something with a more
6625 graceful degradation. */
6626 if (n_edges > 20000 + n_basic_blocks * 4)
6627 {
6628 if (warn_disabled_optimization)
6629 warning ("%s: %d basic blocks and %d edges/basic block",
6630 pass, n_basic_blocks, n_edges / n_basic_blocks);
7b1b4aed 6631
d128effb
NS
6632 return true;
6633 }
6634
6635 /* If allocating memory for the cprop bitmap would take up too much
6636 storage it's better just to disable the optimization. */
6637 if ((n_basic_blocks
6638 * SBITMAP_SET_SIZE (max_reg_num ())
6639 * sizeof (SBITMAP_ELT_TYPE)) > MAX_GCSE_MEMORY)
6640 {
6641 if (warn_disabled_optimization)
6642 warning ("%s: %d basic blocks and %d registers",
6643 pass, n_basic_blocks, max_reg_num ());
6644
6645 return true;
6646 }
6647
6648 return false;
6649}
6650
e2500fed 6651#include "gt-gcse.h"
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