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f4e584dc 1/* Global common subexpression elimination/Partial redundancy elimination
7506f491 2 and global constant/copy propagation for GNU compiler.
8e42ace1
KH
3 Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002
4 Free Software Foundation, Inc.
7506f491 5
1322177d 6This file is part of GCC.
7506f491 7
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8GCC is free software; you can redistribute it and/or modify it under
9the terms of the GNU General Public License as published by the Free
10Software Foundation; either version 2, or (at your option) any later
11version.
7506f491 12
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13GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14WARRANTY; without even the implied warranty of MERCHANTABILITY or
15FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16for more details.
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17
18You should have received a copy of the GNU General Public License
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19along with GCC; see the file COPYING. If not, write to the Free
20Software Foundation, 59 Temple Place - Suite 330, Boston, MA
2102111-1307, USA. */
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22
23/* TODO
24 - reordering of memory allocation and freeing to be more space efficient
25 - do rough calc of how many regs are needed in each block, and a rough
26 calc of how many regs are available in each class and use that to
27 throttle back the code in cases where RTX_COST is minimal.
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28 - a store to the same address as a load does not kill the load if the
29 source of the store is also the destination of the load. Handling this
30 allows more load motion, particularly out of loops.
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31 - ability to realloc sbitmap vectors would allow one initial computation
32 of reg_set_in_block with only subsequent additions, rather than
33 recomputing it for each pass
34
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35*/
36
37/* References searched while implementing this.
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38
39 Compilers Principles, Techniques and Tools
40 Aho, Sethi, Ullman
41 Addison-Wesley, 1988
42
43 Global Optimization by Suppression of Partial Redundancies
44 E. Morel, C. Renvoise
45 communications of the acm, Vol. 22, Num. 2, Feb. 1979
46
47 A Portable Machine-Independent Global Optimizer - Design and Measurements
48 Frederick Chow
49 Stanford Ph.D. thesis, Dec. 1983
50
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51 A Fast Algorithm for Code Movement Optimization
52 D.M. Dhamdhere
53 SIGPLAN Notices, Vol. 23, Num. 10, Oct. 1988
54
55 A Solution to a Problem with Morel and Renvoise's
56 Global Optimization by Suppression of Partial Redundancies
57 K-H Drechsler, M.P. Stadel
58 ACM TOPLAS, Vol. 10, Num. 4, Oct. 1988
59
60 Practical Adaptation of the Global Optimization
61 Algorithm of Morel and Renvoise
62 D.M. Dhamdhere
63 ACM TOPLAS, Vol. 13, Num. 2. Apr. 1991
64
65 Efficiently Computing Static Single Assignment Form and the Control
66 Dependence Graph
67 R. Cytron, J. Ferrante, B.K. Rosen, M.N. Wegman, and F.K. Zadeck
68 ACM TOPLAS, Vol. 13, Num. 4, Oct. 1991
69
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70 Lazy Code Motion
71 J. Knoop, O. Ruthing, B. Steffen
72 ACM SIGPLAN Notices Vol. 27, Num. 7, Jul. 1992, '92 Conference on PLDI
73
74 What's In a Region? Or Computing Control Dependence Regions in Near-Linear
75 Time for Reducible Flow Control
76 Thomas Ball
77 ACM Letters on Programming Languages and Systems,
78 Vol. 2, Num. 1-4, Mar-Dec 1993
79
80 An Efficient Representation for Sparse Sets
81 Preston Briggs, Linda Torczon
82 ACM Letters on Programming Languages and Systems,
83 Vol. 2, Num. 1-4, Mar-Dec 1993
84
85 A Variation of Knoop, Ruthing, and Steffen's Lazy Code Motion
86 K-H Drechsler, M.P. Stadel
87 ACM SIGPLAN Notices, Vol. 28, Num. 5, May 1993
88
89 Partial Dead Code Elimination
90 J. Knoop, O. Ruthing, B. Steffen
91 ACM SIGPLAN Notices, Vol. 29, Num. 6, Jun. 1994
92
93 Effective Partial Redundancy Elimination
94 P. Briggs, K.D. Cooper
95 ACM SIGPLAN Notices, Vol. 29, Num. 6, Jun. 1994
96
97 The Program Structure Tree: Computing Control Regions in Linear Time
98 R. Johnson, D. Pearson, K. Pingali
99 ACM SIGPLAN Notices, Vol. 29, Num. 6, Jun. 1994
100
101 Optimal Code Motion: Theory and Practice
102 J. Knoop, O. Ruthing, B. Steffen
103 ACM TOPLAS, Vol. 16, Num. 4, Jul. 1994
104
105 The power of assignment motion
106 J. Knoop, O. Ruthing, B. Steffen
107 ACM SIGPLAN Notices Vol. 30, Num. 6, Jun. 1995, '95 Conference on PLDI
108
109 Global code motion / global value numbering
110 C. Click
111 ACM SIGPLAN Notices Vol. 30, Num. 6, Jun. 1995, '95 Conference on PLDI
112
113 Value Driven Redundancy Elimination
114 L.T. Simpson
115 Rice University Ph.D. thesis, Apr. 1996
116
117 Value Numbering
118 L.T. Simpson
119 Massively Scalar Compiler Project, Rice University, Sep. 1996
120
121 High Performance Compilers for Parallel Computing
122 Michael Wolfe
123 Addison-Wesley, 1996
124
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125 Advanced Compiler Design and Implementation
126 Steven Muchnick
127 Morgan Kaufmann, 1997
128
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129 Building an Optimizing Compiler
130 Robert Morgan
131 Digital Press, 1998
132
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133 People wishing to speed up the code here should read:
134 Elimination Algorithms for Data Flow Analysis
135 B.G. Ryder, M.C. Paull
136 ACM Computing Surveys, Vol. 18, Num. 3, Sep. 1986
137
138 How to Analyze Large Programs Efficiently and Informatively
139 D.M. Dhamdhere, B.K. Rosen, F.K. Zadeck
140 ACM SIGPLAN Notices Vol. 27, Num. 7, Jul. 1992, '92 Conference on PLDI
141
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142 People wishing to do something different can find various possibilities
143 in the above papers and elsewhere.
144*/
145
146#include "config.h"
50b2596f 147#include "system.h"
01198c2f 148#include "toplev.h"
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149
150#include "rtl.h"
6baf1cc8 151#include "tm_p.h"
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152#include "regs.h"
153#include "hard-reg-set.h"
154#include "flags.h"
155#include "real.h"
156#include "insn-config.h"
157#include "recog.h"
158#include "basic-block.h"
50b2596f 159#include "output.h"
49ad7cfa 160#include "function.h"
3cdbd1f8 161#include "expr.h"
e7d482b9 162#include "except.h"
fb0c0a12 163#include "ggc.h"
f1fa37ff 164#include "params.h"
aaa4ca30 165
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166#include "obstack.h"
167#define obstack_chunk_alloc gmalloc
168#define obstack_chunk_free free
169
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170/* Propagate flow information through back edges and thus enable PRE's
171 moving loop invariant calculations out of loops.
172
173 Originally this tended to create worse overall code, but several
174 improvements during the development of PRE seem to have made following
175 back edges generally a win.
176
177 Note much of the loop invariant code motion done here would normally
178 be done by loop.c, which has more heuristics for when to move invariants
179 out of loops. At some point we might need to move some of those
180 heuristics into gcse.c. */
181#define FOLLOW_BACK_EDGES 1
182
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183/* We support GCSE via Partial Redundancy Elimination. PRE optimizations
184 are a superset of those done by GCSE.
7506f491 185
f4e584dc 186 We perform the following steps:
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187
188 1) Compute basic block information.
189
190 2) Compute table of places where registers are set.
191
192 3) Perform copy/constant propagation.
193
194 4) Perform global cse.
195
e78d9500 196 5) Perform another pass of copy/constant propagation.
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197
198 Two passes of copy/constant propagation are done because the first one
199 enables more GCSE and the second one helps to clean up the copies that
200 GCSE creates. This is needed more for PRE than for Classic because Classic
201 GCSE will try to use an existing register containing the common
202 subexpression rather than create a new one. This is harder to do for PRE
203 because of the code motion (which Classic GCSE doesn't do).
204
205 Expressions we are interested in GCSE-ing are of the form
206 (set (pseudo-reg) (expression)).
207 Function want_to_gcse_p says what these are.
208
209 PRE handles moving invariant expressions out of loops (by treating them as
f4e584dc 210 partially redundant).
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211
212 Eventually it would be nice to replace cse.c/gcse.c with SSA (static single
213 assignment) based GVN (global value numbering). L. T. Simpson's paper
214 (Rice University) on value numbering is a useful reference for this.
215
216 **********************
217
218 We used to support multiple passes but there are diminishing returns in
219 doing so. The first pass usually makes 90% of the changes that are doable.
220 A second pass can make a few more changes made possible by the first pass.
221 Experiments show any further passes don't make enough changes to justify
222 the expense.
223
224 A study of spec92 using an unlimited number of passes:
225 [1 pass] = 1208 substitutions, [2] = 577, [3] = 202, [4] = 192, [5] = 83,
226 [6] = 34, [7] = 17, [8] = 9, [9] = 4, [10] = 4, [11] = 2,
227 [12] = 2, [13] = 1, [15] = 1, [16] = 2, [41] = 1
228
229 It was found doing copy propagation between each pass enables further
230 substitutions.
231
232 PRE is quite expensive in complicated functions because the DFA can take
740f35a0 233 awhile to converge. Hence we only perform one pass. The parameter max-gcse-passes can
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234 be modified if one wants to experiment.
235
236 **********************
237
238 The steps for PRE are:
239
240 1) Build the hash table of expressions we wish to GCSE (expr_hash_table).
241
242 2) Perform the data flow analysis for PRE.
243
244 3) Delete the redundant instructions
245
246 4) Insert the required copies [if any] that make the partially
247 redundant instructions fully redundant.
248
249 5) For other reaching expressions, insert an instruction to copy the value
250 to a newly created pseudo that will reach the redundant instruction.
251
252 The deletion is done first so that when we do insertions we
253 know which pseudo reg to use.
254
255 Various papers have argued that PRE DFA is expensive (O(n^2)) and others
256 argue it is not. The number of iterations for the algorithm to converge
257 is typically 2-4 so I don't view it as that expensive (relatively speaking).
258
f4e584dc 259 PRE GCSE depends heavily on the second CSE pass to clean up the copies
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260 we create. To make an expression reach the place where it's redundant,
261 the result of the expression is copied to a new register, and the redundant
262 expression is deleted by replacing it with this new register. Classic GCSE
263 doesn't have this problem as much as it computes the reaching defs of
264 each register in each block and thus can try to use an existing register.
265
266 **********************
267
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268 A fair bit of simplicity is created by creating small functions for simple
269 tasks, even when the function is only called in one place. This may
270 measurably slow things down [or may not] by creating more function call
271 overhead than is necessary. The source is laid out so that it's trivial
272 to make the affected functions inline so that one can measure what speed
273 up, if any, can be achieved, and maybe later when things settle things can
274 be rearranged.
275
276 Help stamp out big monolithic functions! */
277\f
278/* GCSE global vars. */
279
280/* -dG dump file. */
281static FILE *gcse_file;
282
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283/* Note whether or not we should run jump optimization after gcse. We
284 want to do this for two cases.
285
286 * If we changed any jumps via cprop.
287
288 * If we added any labels via edge splitting. */
289
290static int run_jump_opt_after_gcse;
291
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292/* Bitmaps are normally not included in debugging dumps.
293 However it's useful to be able to print them from GDB.
294 We could create special functions for this, but it's simpler to
295 just allow passing stderr to the dump_foo fns. Since stderr can
296 be a macro, we store a copy here. */
297static FILE *debug_stderr;
298
299/* An obstack for our working variables. */
300static struct obstack gcse_obstack;
301
302/* Non-zero for each mode that supports (set (reg) (reg)).
303 This is trivially true for integer and floating point values.
304 It may or may not be true for condition codes. */
305static char can_copy_p[(int) NUM_MACHINE_MODES];
306
307/* Non-zero if can_copy_p has been initialized. */
308static int can_copy_init_p;
309
c4c81601 310struct reg_use {rtx reg_rtx; };
abd535b6 311
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312/* Hash table of expressions. */
313
314struct expr
315{
316 /* The expression (SET_SRC for expressions, PATTERN for assignments). */
317 rtx expr;
318 /* Index in the available expression bitmaps. */
319 int bitmap_index;
320 /* Next entry with the same hash. */
321 struct expr *next_same_hash;
322 /* List of anticipatable occurrences in basic blocks in the function.
323 An "anticipatable occurrence" is one that is the first occurrence in the
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324 basic block, the operands are not modified in the basic block prior
325 to the occurrence and the output is not used between the start of
326 the block and the occurrence. */
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327 struct occr *antic_occr;
328 /* List of available occurrence in basic blocks in the function.
329 An "available occurrence" is one that is the last occurrence in the
330 basic block and the operands are not modified by following statements in
331 the basic block [including this insn]. */
332 struct occr *avail_occr;
333 /* Non-null if the computation is PRE redundant.
334 The value is the newly created pseudo-reg to record a copy of the
335 expression in all the places that reach the redundant copy. */
336 rtx reaching_reg;
337};
338
339/* Occurrence of an expression.
340 There is one per basic block. If a pattern appears more than once the
341 last appearance is used [or first for anticipatable expressions]. */
342
343struct occr
344{
345 /* Next occurrence of this expression. */
346 struct occr *next;
347 /* The insn that computes the expression. */
348 rtx insn;
349 /* Non-zero if this [anticipatable] occurrence has been deleted. */
350 char deleted_p;
351 /* Non-zero if this [available] occurrence has been copied to
352 reaching_reg. */
353 /* ??? This is mutually exclusive with deleted_p, so they could share
354 the same byte. */
355 char copied_p;
356};
357
358/* Expression and copy propagation hash tables.
359 Each hash table is an array of buckets.
360 ??? It is known that if it were an array of entries, structure elements
361 `next_same_hash' and `bitmap_index' wouldn't be necessary. However, it is
362 not clear whether in the final analysis a sufficient amount of memory would
363 be saved as the size of the available expression bitmaps would be larger
364 [one could build a mapping table without holes afterwards though].
c4c81601 365 Someday I'll perform the computation and figure it out. */
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366
367/* Total size of the expression hash table, in elements. */
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368static unsigned int expr_hash_table_size;
369
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370/* The table itself.
371 This is an array of `expr_hash_table_size' elements. */
372static struct expr **expr_hash_table;
373
374/* Total size of the copy propagation hash table, in elements. */
ebb13e7e 375static unsigned int set_hash_table_size;
c4c81601 376
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377/* The table itself.
378 This is an array of `set_hash_table_size' elements. */
379static struct expr **set_hash_table;
380
381/* Mapping of uids to cuids.
382 Only real insns get cuids. */
383static int *uid_cuid;
384
385/* Highest UID in UID_CUID. */
386static int max_uid;
387
388/* Get the cuid of an insn. */
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389#ifdef ENABLE_CHECKING
390#define INSN_CUID(INSN) (INSN_UID (INSN) > max_uid ? (abort (), 0) : uid_cuid[INSN_UID (INSN)])
391#else
7506f491 392#define INSN_CUID(INSN) (uid_cuid[INSN_UID (INSN)])
b86db3eb 393#endif
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394
395/* Number of cuids. */
396static int max_cuid;
397
398/* Mapping of cuids to insns. */
399static rtx *cuid_insn;
400
401/* Get insn from cuid. */
402#define CUID_INSN(CUID) (cuid_insn[CUID])
403
404/* Maximum register number in function prior to doing gcse + 1.
405 Registers created during this pass have regno >= max_gcse_regno.
406 This is named with "gcse" to not collide with global of same name. */
770ae6cc 407static unsigned int max_gcse_regno;
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408
409/* Maximum number of cse-able expressions found. */
410static int n_exprs;
c4c81601 411
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412/* Maximum number of assignments for copy propagation found. */
413static int n_sets;
414
415/* Table of registers that are modified.
c4c81601 416
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417 For each register, each element is a list of places where the pseudo-reg
418 is set.
419
420 For simplicity, GCSE is done on sets of pseudo-regs only. PRE GCSE only
421 requires knowledge of which blocks kill which regs [and thus could use
f4e584dc 422 a bitmap instead of the lists `reg_set_table' uses].
7506f491 423
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424 `reg_set_table' and could be turned into an array of bitmaps (num-bbs x
425 num-regs) [however perhaps it may be useful to keep the data as is]. One
426 advantage of recording things this way is that `reg_set_table' is fairly
427 sparse with respect to pseudo regs but for hard regs could be fairly dense
428 [relatively speaking]. And recording sets of pseudo-regs in lists speeds
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429 up functions like compute_transp since in the case of pseudo-regs we only
430 need to iterate over the number of times a pseudo-reg is set, not over the
431 number of basic blocks [clearly there is a bit of a slow down in the cases
432 where a pseudo is set more than once in a block, however it is believed
433 that the net effect is to speed things up]. This isn't done for hard-regs
434 because recording call-clobbered hard-regs in `reg_set_table' at each
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435 function call can consume a fair bit of memory, and iterating over
436 hard-regs stored this way in compute_transp will be more expensive. */
7506f491 437
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438typedef struct reg_set
439{
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440 /* The next setting of this register. */
441 struct reg_set *next;
442 /* The insn where it was set. */
443 rtx insn;
444} reg_set;
c4c81601 445
7506f491 446static reg_set **reg_set_table;
c4c81601 447
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448/* Size of `reg_set_table'.
449 The table starts out at max_gcse_regno + slop, and is enlarged as
450 necessary. */
451static int reg_set_table_size;
c4c81601 452
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453/* Amount to grow `reg_set_table' by when it's full. */
454#define REG_SET_TABLE_SLOP 100
455
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456/* This is a list of expressions which are MEMs and will be used by load
457 or store motion.
458 Load motion tracks MEMs which aren't killed by
459 anything except itself. (ie, loads and stores to a single location).
460 We can then allow movement of these MEM refs with a little special
461 allowance. (all stores copy the same value to the reaching reg used
462 for the loads). This means all values used to store into memory must have
463 no side effects so we can re-issue the setter value.
464 Store Motion uses this structure as an expression table to track stores
465 which look interesting, and might be moveable towards the exit block. */
466
467struct ls_expr
468{
469 struct expr * expr; /* Gcse expression reference for LM. */
470 rtx pattern; /* Pattern of this mem. */
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471 rtx loads; /* INSN list of loads seen. */
472 rtx stores; /* INSN list of stores seen. */
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473 struct ls_expr * next; /* Next in the list. */
474 int invalid; /* Invalid for some reason. */
475 int index; /* If it maps to a bitmap index. */
476 int hash_index; /* Index when in a hash table. */
477 rtx reaching_reg; /* Register to use when re-writing. */
478};
479
480/* Head of the list of load/store memory refs. */
481static struct ls_expr * pre_ldst_mems = NULL;
482
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483/* Bitmap containing one bit for each register in the program.
484 Used when performing GCSE to track which registers have been set since
485 the start of the basic block. */
73991d6a 486static regset reg_set_bitmap;
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487
488/* For each block, a bitmap of registers set in the block.
489 This is used by expr_killed_p and compute_transp.
490 It is computed during hash table computation and not by compute_sets
491 as it includes registers added since the last pass (or between cprop and
492 gcse) and it's currently not easy to realloc sbitmap vectors. */
493static sbitmap *reg_set_in_block;
494
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495/* Array, indexed by basic block number for a list of insns which modify
496 memory within that block. */
497static rtx * modify_mem_list;
73991d6a 498bitmap modify_mem_list_set;
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499
500/* This array parallels modify_mem_list, but is kept canonicalized. */
501static rtx * canon_modify_mem_list;
73991d6a 502bitmap canon_modify_mem_list_set;
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503/* Various variables for statistics gathering. */
504
505/* Memory used in a pass.
506 This isn't intended to be absolutely precise. Its intent is only
507 to keep an eye on memory usage. */
508static int bytes_used;
c4c81601 509
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510/* GCSE substitutions made. */
511static int gcse_subst_count;
512/* Number of copy instructions created. */
513static int gcse_create_count;
514/* Number of constants propagated. */
515static int const_prop_count;
516/* Number of copys propagated. */
517static int copy_prop_count;
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518\f
519/* These variables are used by classic GCSE.
520 Normally they'd be defined a bit later, but `rd_gen' needs to
521 be declared sooner. */
522
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523/* Each block has a bitmap of each type.
524 The length of each blocks bitmap is:
525
526 max_cuid - for reaching definitions
527 n_exprs - for available expressions
528
529 Thus we view the bitmaps as 2 dimensional arrays. i.e.
530 rd_kill[block_num][cuid_num]
c4c81601 531 ae_kill[block_num][expr_num] */
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532
533/* For reaching defs */
534static sbitmap *rd_kill, *rd_gen, *reaching_defs, *rd_out;
535
536/* for available exprs */
537static sbitmap *ae_kill, *ae_gen, *ae_in, *ae_out;
b5ce41ff 538
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539/* Objects of this type are passed around by the null-pointer check
540 removal routines. */
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541struct null_pointer_info
542{
0511851c 543 /* The basic block being processed. */
0b17ab2f 544 int current_block;
0511851c 545 /* The first register to be handled in this pass. */
770ae6cc 546 unsigned int min_reg;
0511851c 547 /* One greater than the last register to be handled in this pass. */
770ae6cc 548 unsigned int max_reg;
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549 sbitmap *nonnull_local;
550 sbitmap *nonnull_killed;
551};
7506f491 552\f
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553static void compute_can_copy PARAMS ((void));
554static char *gmalloc PARAMS ((unsigned int));
555static char *grealloc PARAMS ((char *, unsigned int));
556static char *gcse_alloc PARAMS ((unsigned long));
557static void alloc_gcse_mem PARAMS ((rtx));
558static void free_gcse_mem PARAMS ((void));
559static void alloc_reg_set_mem PARAMS ((int));
560static void free_reg_set_mem PARAMS ((void));
561static int get_bitmap_width PARAMS ((int, int, int));
562static void record_one_set PARAMS ((int, rtx));
563static void record_set_info PARAMS ((rtx, rtx, void *));
564static void compute_sets PARAMS ((rtx));
565static void hash_scan_insn PARAMS ((rtx, int, int));
566static void hash_scan_set PARAMS ((rtx, rtx, int));
567static void hash_scan_clobber PARAMS ((rtx, rtx));
568static void hash_scan_call PARAMS ((rtx, rtx));
569static int want_to_gcse_p PARAMS ((rtx));
570static int oprs_unchanged_p PARAMS ((rtx, rtx, int));
571static int oprs_anticipatable_p PARAMS ((rtx, rtx));
572static int oprs_available_p PARAMS ((rtx, rtx));
573static void insert_expr_in_table PARAMS ((rtx, enum machine_mode, rtx,
574 int, int));
575static void insert_set_in_table PARAMS ((rtx, rtx));
576static unsigned int hash_expr PARAMS ((rtx, enum machine_mode, int *, int));
577static unsigned int hash_expr_1 PARAMS ((rtx, enum machine_mode, int *));
c0712acb 578static unsigned int hash_string_1 PARAMS ((const char *));
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579static unsigned int hash_set PARAMS ((int, int));
580static int expr_equiv_p PARAMS ((rtx, rtx));
581static void record_last_reg_set_info PARAMS ((rtx, int));
582static void record_last_mem_set_info PARAMS ((rtx));
583static void record_last_set_info PARAMS ((rtx, rtx, void *));
711d877c 584static void compute_hash_table PARAMS ((int));
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585static void alloc_set_hash_table PARAMS ((int));
586static void free_set_hash_table PARAMS ((void));
587static void compute_set_hash_table PARAMS ((void));
2e653e39 588static void alloc_expr_hash_table PARAMS ((unsigned int));
c4c81601
RK
589static void free_expr_hash_table PARAMS ((void));
590static void compute_expr_hash_table PARAMS ((void));
591static void dump_hash_table PARAMS ((FILE *, const char *, struct expr **,
592 int, int));
593static struct expr *lookup_expr PARAMS ((rtx));
770ae6cc
RK
594static struct expr *lookup_set PARAMS ((unsigned int, rtx));
595static struct expr *next_set PARAMS ((unsigned int, struct expr *));
c4c81601
RK
596static void reset_opr_set_tables PARAMS ((void));
597static int oprs_not_set_p PARAMS ((rtx, rtx));
598static void mark_call PARAMS ((rtx));
599static void mark_set PARAMS ((rtx, rtx));
600static void mark_clobber PARAMS ((rtx, rtx));
601static void mark_oprs_set PARAMS ((rtx));
602static void alloc_cprop_mem PARAMS ((int, int));
603static void free_cprop_mem PARAMS ((void));
604static void compute_transp PARAMS ((rtx, int, sbitmap *, int));
605static void compute_transpout PARAMS ((void));
606static void compute_local_properties PARAMS ((sbitmap *, sbitmap *, sbitmap *,
607 int));
711d877c 608static void compute_cprop_data PARAMS ((void));
9e71c818 609static void find_used_regs PARAMS ((rtx *, void *));
c4c81601
RK
610static int try_replace_reg PARAMS ((rtx, rtx, rtx));
611static struct expr *find_avail_set PARAMS ((int, rtx));
0005550b 612static int cprop_jump PARAMS ((basic_block, rtx, rtx, rtx));
e2bef702 613#ifdef HAVE_cc0
0005550b 614static int cprop_cc0_jump PARAMS ((basic_block, rtx, struct reg_use *, rtx));
e2bef702 615#endif
a13d4ebf 616static void mems_conflict_for_gcse_p PARAMS ((rtx, rtx, void *));
e2d2ed72 617static int load_killed_in_block_p PARAMS ((basic_block, int, rtx, int));
a13d4ebf 618static void canon_list_insert PARAMS ((rtx, rtx, void *));
0005550b 619static int cprop_insn PARAMS ((basic_block, rtx, int));
c4c81601
RK
620static int cprop PARAMS ((int));
621static int one_cprop_pass PARAMS ((int, int));
622static void alloc_pre_mem PARAMS ((int, int));
623static void free_pre_mem PARAMS ((void));
624static void compute_pre_data PARAMS ((void));
e2d2ed72
AM
625static int pre_expr_reaches_here_p PARAMS ((basic_block, struct expr *,
626 basic_block));
627static void insert_insn_end_bb PARAMS ((struct expr *, basic_block, int));
c4c81601
RK
628static void pre_insert_copy_insn PARAMS ((struct expr *, rtx));
629static void pre_insert_copies PARAMS ((void));
630static int pre_delete PARAMS ((void));
631static int pre_gcse PARAMS ((void));
632static int one_pre_gcse_pass PARAMS ((int));
633static void add_label_notes PARAMS ((rtx, rtx));
634static void alloc_code_hoist_mem PARAMS ((int, int));
635static void free_code_hoist_mem PARAMS ((void));
711d877c 636static void compute_code_hoist_vbeinout PARAMS ((void));
c4c81601 637static void compute_code_hoist_data PARAMS ((void));
e2d2ed72
AM
638static int hoist_expr_reaches_here_p PARAMS ((basic_block, int, basic_block,
639 char *));
c4c81601
RK
640static void hoist_code PARAMS ((void));
641static int one_code_hoisting_pass PARAMS ((void));
642static void alloc_rd_mem PARAMS ((int, int));
643static void free_rd_mem PARAMS ((void));
e2d2ed72 644static void handle_rd_kill_set PARAMS ((rtx, int, basic_block));
c4c81601 645static void compute_kill_rd PARAMS ((void));
711d877c 646static void compute_rd PARAMS ((void));
c4c81601
RK
647static void alloc_avail_expr_mem PARAMS ((int, int));
648static void free_avail_expr_mem PARAMS ((void));
649static void compute_ae_gen PARAMS ((void));
e2d2ed72 650static int expr_killed_p PARAMS ((rtx, basic_block));
c4c81601 651static void compute_ae_kill PARAMS ((sbitmap *, sbitmap *));
711d877c 652static int expr_reaches_here_p PARAMS ((struct occr *, struct expr *,
e2d2ed72 653 basic_block, int));
c4c81601
RK
654static rtx computing_insn PARAMS ((struct expr *, rtx));
655static int def_reaches_here_p PARAMS ((rtx, rtx));
656static int can_disregard_other_sets PARAMS ((struct reg_set **, rtx, int));
657static int handle_avail_expr PARAMS ((rtx, struct expr *));
658static int classic_gcse PARAMS ((void));
659static int one_classic_gcse_pass PARAMS ((int));
660static void invalidate_nonnull_info PARAMS ((rtx, rtx, void *));
9cd56be1 661static void delete_null_pointer_checks_1 PARAMS ((unsigned int *,
8e184d9c 662 sbitmap *, sbitmap *,
711d877c
KG
663 struct null_pointer_info *));
664static rtx process_insert_insn PARAMS ((struct expr *));
665static int pre_edge_insert PARAMS ((struct edge_list *, struct expr **));
c4c81601 666static int expr_reaches_here_p_work PARAMS ((struct occr *, struct expr *,
e2d2ed72
AM
667 basic_block, int, char *));
668static int pre_expr_reaches_here_p_work PARAMS ((basic_block, struct expr *,
669 basic_block, char *));
a13d4ebf
AM
670static struct ls_expr * ldst_entry PARAMS ((rtx));
671static void free_ldst_entry PARAMS ((struct ls_expr *));
672static void free_ldst_mems PARAMS ((void));
673static void print_ldst_list PARAMS ((FILE *));
674static struct ls_expr * find_rtx_in_ldst PARAMS ((rtx));
675static int enumerate_ldsts PARAMS ((void));
676static inline struct ls_expr * first_ls_expr PARAMS ((void));
677static inline struct ls_expr * next_ls_expr PARAMS ((struct ls_expr *));
678static int simple_mem PARAMS ((rtx));
679static void invalidate_any_buried_refs PARAMS ((rtx));
680static void compute_ld_motion_mems PARAMS ((void));
681static void trim_ld_motion_mems PARAMS ((void));
682static void update_ld_motion_stores PARAMS ((struct expr *));
aaa4ca30
AJ
683static void reg_set_info PARAMS ((rtx, rtx, void *));
684static int store_ops_ok PARAMS ((rtx, basic_block));
a13d4ebf
AM
685static void find_moveable_store PARAMS ((rtx));
686static int compute_store_table PARAMS ((void));
687static int load_kills_store PARAMS ((rtx, rtx));
688static int find_loads PARAMS ((rtx, rtx));
689static int store_killed_in_insn PARAMS ((rtx, rtx));
aaa4ca30 690static int store_killed_after PARAMS ((rtx, rtx, basic_block));
e2d2ed72 691static int store_killed_before PARAMS ((rtx, rtx, basic_block));
a13d4ebf 692static void build_store_vectors PARAMS ((void));
e2d2ed72 693static void insert_insn_start_bb PARAMS ((rtx, basic_block));
a13d4ebf 694static int insert_store PARAMS ((struct ls_expr *, edge));
e2d2ed72
AM
695static void replace_store_insn PARAMS ((rtx, rtx, basic_block));
696static void delete_store PARAMS ((struct ls_expr *,
697 basic_block));
a13d4ebf
AM
698static void free_store_memory PARAMS ((void));
699static void store_motion PARAMS ((void));
0fe854a7 700static void free_insn_expr_list_list PARAMS ((rtx *));
73991d6a
JH
701static void clear_modify_mem_tables PARAMS ((void));
702static void free_modify_mem_tables PARAMS ((void));
7506f491
DE
703\f
704/* Entry point for global common subexpression elimination.
705 F is the first instruction in the function. */
706
e78d9500 707int
7506f491
DE
708gcse_main (f, file)
709 rtx f;
710 FILE *file;
711{
712 int changed, pass;
713 /* Bytes used at start of pass. */
714 int initial_bytes_used;
715 /* Maximum number of bytes used by a pass. */
716 int max_pass_bytes;
717 /* Point to release obstack data from for each pass. */
718 char *gcse_obstack_bottom;
719
a13d4ebf
AM
720 /* Insertion of instructions on edges can create new basic blocks; we
721 need the original basic block count so that we can properly deallocate
722 arrays sized on the number of basic blocks originally in the cfg. */
723 int orig_bb_count;
b5ce41ff
JL
724 /* We do not construct an accurate cfg in functions which call
725 setjmp, so just punt to be safe. */
7506f491 726 if (current_function_calls_setjmp)
e78d9500 727 return 0;
7506f491 728
b5ce41ff
JL
729 /* Assume that we do not need to run jump optimizations after gcse. */
730 run_jump_opt_after_gcse = 0;
731
7506f491
DE
732 /* For calling dump_foo fns from gdb. */
733 debug_stderr = stderr;
b5ce41ff 734 gcse_file = file;
7506f491 735
b5ce41ff
JL
736 /* Identify the basic block information for this function, including
737 successors and predecessors. */
7506f491 738 max_gcse_regno = max_reg_num ();
7506f491 739
a42cd965
AM
740 if (file)
741 dump_flow_info (file);
742
0b17ab2f 743 orig_bb_count = n_basic_blocks;
7506f491 744 /* Return if there's nothing to do. */
0b17ab2f 745 if (n_basic_blocks <= 1)
a18820c6 746 return 0;
7506f491 747
55f7891b
JL
748 /* Trying to perform global optimizations on flow graphs which have
749 a high connectivity will take a long time and is unlikely to be
750 particularly useful.
751
43e72072 752 In normal circumstances a cfg should have about twice as many edges
55f7891b
JL
753 as blocks. But we do not want to punish small functions which have
754 a couple switch statements. So we require a relatively large number
755 of basic blocks and the ratio of edges to blocks to be high. */
0b17ab2f 756 if (n_basic_blocks > 1000 && n_edges / n_basic_blocks >= 20)
18424ae1
BL
757 {
758 if (warn_disabled_optimization)
8e42ace1 759 warning ("GCSE disabled: %d > 1000 basic blocks and %d >= 20 edges/basic block",
0b17ab2f 760 n_basic_blocks, n_edges / n_basic_blocks);
18424ae1
BL
761 return 0;
762 }
55f7891b 763
f1fa37ff
MM
764 /* If allocating memory for the cprop bitmap would take up too much
765 storage it's better just to disable the optimization. */
0b17ab2f 766 if ((n_basic_blocks
f1fa37ff
MM
767 * SBITMAP_SET_SIZE (max_gcse_regno)
768 * sizeof (SBITMAP_ELT_TYPE)) > MAX_GCSE_MEMORY)
769 {
770 if (warn_disabled_optimization)
771 warning ("GCSE disabled: %d basic blocks and %d registers",
0b17ab2f 772 n_basic_blocks, max_gcse_regno);
f1fa37ff
MM
773
774 return 0;
775 }
776
7506f491
DE
777 /* See what modes support reg/reg copy operations. */
778 if (! can_copy_init_p)
779 {
780 compute_can_copy ();
781 can_copy_init_p = 1;
782 }
783
784 gcc_obstack_init (&gcse_obstack);
a42cd965 785 bytes_used = 0;
7506f491 786
a13d4ebf
AM
787 /* We need alias. */
788 init_alias_analysis ();
c4c81601
RK
789 /* Record where pseudo-registers are set. This data is kept accurate
790 during each pass. ??? We could also record hard-reg information here
791 [since it's unchanging], however it is currently done during hash table
792 computation.
b5ce41ff 793
c4c81601
RK
794 It may be tempting to compute MEM set information here too, but MEM sets
795 will be subject to code motion one day and thus we need to compute
b5ce41ff 796 information about memory sets when we build the hash tables. */
7506f491
DE
797
798 alloc_reg_set_mem (max_gcse_regno);
799 compute_sets (f);
800
801 pass = 0;
802 initial_bytes_used = bytes_used;
803 max_pass_bytes = 0;
804 gcse_obstack_bottom = gcse_alloc (1);
805 changed = 1;
740f35a0 806 while (changed && pass < MAX_GCSE_PASSES)
7506f491
DE
807 {
808 changed = 0;
809 if (file)
810 fprintf (file, "GCSE pass %d\n\n", pass + 1);
811
812 /* Initialize bytes_used to the space for the pred/succ lists,
813 and the reg_set_table data. */
814 bytes_used = initial_bytes_used;
815
816 /* Each pass may create new registers, so recalculate each time. */
817 max_gcse_regno = max_reg_num ();
818
819 alloc_gcse_mem (f);
820
b5ce41ff
JL
821 /* Don't allow constant propagation to modify jumps
822 during this pass. */
823 changed = one_cprop_pass (pass + 1, 0);
7506f491
DE
824
825 if (optimize_size)
b5ce41ff 826 changed |= one_classic_gcse_pass (pass + 1);
7506f491 827 else
a42cd965
AM
828 {
829 changed |= one_pre_gcse_pass (pass + 1);
a13d4ebf
AM
830 /* We may have just created new basic blocks. Release and
831 recompute various things which are sized on the number of
832 basic blocks. */
833 if (changed)
834 {
73991d6a 835 free_modify_mem_tables ();
a13d4ebf 836 modify_mem_list
0b17ab2f 837 = (rtx *) gmalloc (n_basic_blocks * sizeof (rtx));
a13d4ebf 838 canon_modify_mem_list
0b17ab2f
RH
839 = (rtx *) gmalloc (n_basic_blocks * sizeof (rtx));
840 memset ((char *) modify_mem_list, 0, n_basic_blocks * sizeof (rtx));
841 memset ((char *) canon_modify_mem_list, 0, n_basic_blocks * sizeof (rtx));
842 orig_bb_count = n_basic_blocks;
a13d4ebf 843 }
a42cd965
AM
844 free_reg_set_mem ();
845 alloc_reg_set_mem (max_reg_num ());
846 compute_sets (f);
847 run_jump_opt_after_gcse = 1;
848 }
7506f491
DE
849
850 if (max_pass_bytes < bytes_used)
851 max_pass_bytes = bytes_used;
852
bb457bd9
JL
853 /* Free up memory, then reallocate for code hoisting. We can
854 not re-use the existing allocated memory because the tables
855 will not have info for the insns or registers created by
856 partial redundancy elimination. */
7506f491
DE
857 free_gcse_mem ();
858
bb457bd9
JL
859 /* It does not make sense to run code hoisting unless we optimizing
860 for code size -- it rarely makes programs faster, and can make
861 them bigger if we did partial redundancy elimination (when optimizing
862 for space, we use a classic gcse algorithm instead of partial
863 redundancy algorithms). */
864 if (optimize_size)
865 {
866 max_gcse_regno = max_reg_num ();
867 alloc_gcse_mem (f);
868 changed |= one_code_hoisting_pass ();
869 free_gcse_mem ();
870
871 if (max_pass_bytes < bytes_used)
872 max_pass_bytes = bytes_used;
873 }
874
7506f491
DE
875 if (file)
876 {
877 fprintf (file, "\n");
878 fflush (file);
879 }
c4c81601 880
7506f491
DE
881 obstack_free (&gcse_obstack, gcse_obstack_bottom);
882 pass++;
883 }
884
b5ce41ff
JL
885 /* Do one last pass of copy propagation, including cprop into
886 conditional jumps. */
887
888 max_gcse_regno = max_reg_num ();
889 alloc_gcse_mem (f);
890 /* This time, go ahead and allow cprop to alter jumps. */
891 one_cprop_pass (pass + 1, 1);
892 free_gcse_mem ();
7506f491
DE
893
894 if (file)
895 {
896 fprintf (file, "GCSE of %s: %d basic blocks, ",
0b17ab2f 897 current_function_name, n_basic_blocks);
7506f491
DE
898 fprintf (file, "%d pass%s, %d bytes\n\n",
899 pass, pass > 1 ? "es" : "", max_pass_bytes);
900 }
901
6496a589 902 obstack_free (&gcse_obstack, NULL);
7506f491 903 free_reg_set_mem ();
a13d4ebf
AM
904 /* We are finished with alias. */
905 end_alias_analysis ();
906 allocate_reg_info (max_reg_num (), FALSE, FALSE);
907
61ad9a34
JJ
908 /* Store motion disabled until it is fixed. */
909 if (0 && !optimize_size && flag_gcse_sm)
a13d4ebf
AM
910 store_motion ();
911 /* Record where pseudo-registers are set. */
e78d9500 912 return run_jump_opt_after_gcse;
7506f491
DE
913}
914\f
915/* Misc. utilities. */
916
917/* Compute which modes support reg/reg copy operations. */
918
919static void
920compute_can_copy ()
921{
922 int i;
50b2596f 923#ifndef AVOID_CCMODE_COPIES
8e42ace1 924 rtx reg, insn;
50b2596f 925#endif
961192e1 926 memset (can_copy_p, 0, NUM_MACHINE_MODES);
7506f491
DE
927
928 start_sequence ();
929 for (i = 0; i < NUM_MACHINE_MODES; i++)
c4c81601
RK
930 if (GET_MODE_CLASS (i) == MODE_CC)
931 {
7506f491 932#ifdef AVOID_CCMODE_COPIES
c4c81601 933 can_copy_p[i] = 0;
7506f491 934#else
c4c81601
RK
935 reg = gen_rtx_REG ((enum machine_mode) i, LAST_VIRTUAL_REGISTER + 1);
936 insn = emit_insn (gen_rtx_SET (VOIDmode, reg, reg));
9714cf43 937 if (recog (PATTERN (insn), insn, NULL) >= 0)
c4c81601 938 can_copy_p[i] = 1;
7506f491 939#endif
c4c81601 940 }
141b5810
AO
941 else
942 can_copy_p[i] = 1;
c4c81601 943
7506f491 944 end_sequence ();
7506f491
DE
945}
946\f
947/* Cover function to xmalloc to record bytes allocated. */
948
949static char *
950gmalloc (size)
951 unsigned int size;
952{
953 bytes_used += size;
954 return xmalloc (size);
955}
956
957/* Cover function to xrealloc.
958 We don't record the additional size since we don't know it.
959 It won't affect memory usage stats much anyway. */
960
961static char *
962grealloc (ptr, size)
963 char *ptr;
964 unsigned int size;
965{
966 return xrealloc (ptr, size);
967}
968
969/* Cover function to obstack_alloc.
970 We don't need to record the bytes allocated here since
971 obstack_chunk_alloc is set to gmalloc. */
972
973static char *
974gcse_alloc (size)
975 unsigned long size;
976{
977 return (char *) obstack_alloc (&gcse_obstack, size);
978}
979
980/* Allocate memory for the cuid mapping array,
981 and reg/memory set tracking tables.
982
983 This is called at the start of each pass. */
984
985static void
986alloc_gcse_mem (f)
987 rtx f;
988{
8e42ace1 989 int i, n;
7506f491
DE
990 rtx insn;
991
992 /* Find the largest UID and create a mapping from UIDs to CUIDs.
993 CUIDs are like UIDs except they increase monotonically, have no gaps,
994 and only apply to real insns. */
995
996 max_uid = get_max_uid ();
997 n = (max_uid + 1) * sizeof (int);
998 uid_cuid = (int *) gmalloc (n);
961192e1 999 memset ((char *) uid_cuid, 0, n);
7506f491
DE
1000 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
1001 {
2c3c49de 1002 if (INSN_P (insn))
b86db3eb 1003 uid_cuid[INSN_UID (insn)] = i++;
7506f491 1004 else
b86db3eb 1005 uid_cuid[INSN_UID (insn)] = i;
7506f491
DE
1006 }
1007
1008 /* Create a table mapping cuids to insns. */
1009
1010 max_cuid = i;
1011 n = (max_cuid + 1) * sizeof (rtx);
1012 cuid_insn = (rtx *) gmalloc (n);
961192e1 1013 memset ((char *) cuid_insn, 0, n);
7506f491 1014 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
2c3c49de 1015 if (INSN_P (insn))
c4c81601 1016 CUID_INSN (i++) = insn;
7506f491
DE
1017
1018 /* Allocate vars to track sets of regs. */
73991d6a 1019 reg_set_bitmap = BITMAP_XMALLOC ();
7506f491
DE
1020
1021 /* Allocate vars to track sets of regs, memory per block. */
0b17ab2f 1022 reg_set_in_block = (sbitmap *) sbitmap_vector_alloc (n_basic_blocks,
7506f491 1023 max_gcse_regno);
a13d4ebf
AM
1024 /* Allocate array to keep a list of insns which modify memory in each
1025 basic block. */
0b17ab2f
RH
1026 modify_mem_list = (rtx *) gmalloc (n_basic_blocks * sizeof (rtx));
1027 canon_modify_mem_list = (rtx *) gmalloc (n_basic_blocks * sizeof (rtx));
1028 memset ((char *) modify_mem_list, 0, n_basic_blocks * sizeof (rtx));
1029 memset ((char *) canon_modify_mem_list, 0, n_basic_blocks * sizeof (rtx));
73991d6a
JH
1030 modify_mem_list_set = BITMAP_XMALLOC ();
1031 canon_modify_mem_list_set = BITMAP_XMALLOC ();
7506f491
DE
1032}
1033
1034/* Free memory allocated by alloc_gcse_mem. */
1035
1036static void
1037free_gcse_mem ()
1038{
1039 free (uid_cuid);
1040 free (cuid_insn);
1041
73991d6a 1042 BITMAP_XFREE (reg_set_bitmap);
7506f491 1043
5a660bff 1044 sbitmap_vector_free (reg_set_in_block);
73991d6a
JH
1045 free_modify_mem_tables ();
1046 BITMAP_XFREE (modify_mem_list_set);
1047 BITMAP_XFREE (canon_modify_mem_list_set);
7506f491
DE
1048}
1049
0511851c
MM
1050/* Many of the global optimization algorithms work by solving dataflow
1051 equations for various expressions. Initially, some local value is
c4c81601
RK
1052 computed for each expression in each block. Then, the values across the
1053 various blocks are combined (by following flow graph edges) to arrive at
1054 global values. Conceptually, each set of equations is independent. We
1055 may therefore solve all the equations in parallel, solve them one at a
1056 time, or pick any intermediate approach.
1057
1058 When you're going to need N two-dimensional bitmaps, each X (say, the
1059 number of blocks) by Y (say, the number of expressions), call this
1060 function. It's not important what X and Y represent; only that Y
1061 correspond to the things that can be done in parallel. This function will
1062 return an appropriate chunking factor C; you should solve C sets of
1063 equations in parallel. By going through this function, we can easily
1064 trade space against time; by solving fewer equations in parallel we use
1065 less space. */
0511851c
MM
1066
1067static int
1068get_bitmap_width (n, x, y)
1069 int n;
1070 int x;
1071 int y;
1072{
1073 /* It's not really worth figuring out *exactly* how much memory will
1074 be used by a particular choice. The important thing is to get
1075 something approximately right. */
1076 size_t max_bitmap_memory = 10 * 1024 * 1024;
1077
1078 /* The number of bytes we'd use for a single column of minimum
1079 width. */
1080 size_t column_size = n * x * sizeof (SBITMAP_ELT_TYPE);
1081
1082 /* Often, it's reasonable just to solve all the equations in
1083 parallel. */
1084 if (column_size * SBITMAP_SET_SIZE (y) <= max_bitmap_memory)
1085 return y;
1086
1087 /* Otherwise, pick the largest width we can, without going over the
1088 limit. */
1089 return SBITMAP_ELT_BITS * ((max_bitmap_memory + column_size - 1)
1090 / column_size);
1091}
b5ce41ff
JL
1092\f
1093/* Compute the local properties of each recorded expression.
c4c81601
RK
1094
1095 Local properties are those that are defined by the block, irrespective of
1096 other blocks.
b5ce41ff
JL
1097
1098 An expression is transparent in a block if its operands are not modified
1099 in the block.
1100
1101 An expression is computed (locally available) in a block if it is computed
1102 at least once and expression would contain the same value if the
1103 computation was moved to the end of the block.
1104
1105 An expression is locally anticipatable in a block if it is computed at
1106 least once and expression would contain the same value if the computation
1107 was moved to the beginning of the block.
1108
c4c81601
RK
1109 We call this routine for cprop, pre and code hoisting. They all compute
1110 basically the same information and thus can easily share this code.
7506f491 1111
c4c81601
RK
1112 TRANSP, COMP, and ANTLOC are destination sbitmaps for recording local
1113 properties. If NULL, then it is not necessary to compute or record that
1114 particular property.
b5ce41ff 1115
c4c81601
RK
1116 SETP controls which hash table to look at. If zero, this routine looks at
1117 the expr hash table; if nonzero this routine looks at the set hash table.
1118 Additionally, TRANSP is computed as ~TRANSP, since this is really cprop's
1119 ABSALTERED. */
b5ce41ff
JL
1120
1121static void
1122compute_local_properties (transp, comp, antloc, setp)
1123 sbitmap *transp;
1124 sbitmap *comp;
1125 sbitmap *antloc;
1126 int setp;
1127{
2e653e39 1128 unsigned int i, hash_table_size;
b5ce41ff
JL
1129 struct expr **hash_table;
1130
1131 /* Initialize any bitmaps that were passed in. */
1132 if (transp)
695ab36a
BS
1133 {
1134 if (setp)
0b17ab2f 1135 sbitmap_vector_zero (transp, n_basic_blocks);
695ab36a 1136 else
0b17ab2f 1137 sbitmap_vector_ones (transp, n_basic_blocks);
695ab36a 1138 }
c4c81601 1139
b5ce41ff 1140 if (comp)
0b17ab2f 1141 sbitmap_vector_zero (comp, n_basic_blocks);
b5ce41ff 1142 if (antloc)
0b17ab2f 1143 sbitmap_vector_zero (antloc, n_basic_blocks);
b5ce41ff
JL
1144
1145 /* We use the same code for cprop, pre and hoisting. For cprop
1146 we care about the set hash table, for pre and hoisting we
1147 care about the expr hash table. */
1148 hash_table_size = setp ? set_hash_table_size : expr_hash_table_size;
1149 hash_table = setp ? set_hash_table : expr_hash_table;
1150
1151 for (i = 0; i < hash_table_size; i++)
7506f491 1152 {
b5ce41ff
JL
1153 struct expr *expr;
1154
1155 for (expr = hash_table[i]; expr != NULL; expr = expr->next_same_hash)
1156 {
b5ce41ff 1157 int indx = expr->bitmap_index;
c4c81601 1158 struct occr *occr;
b5ce41ff
JL
1159
1160 /* The expression is transparent in this block if it is not killed.
1161 We start by assuming all are transparent [none are killed], and
1162 then reset the bits for those that are. */
b5ce41ff
JL
1163 if (transp)
1164 compute_transp (expr->expr, indx, transp, setp);
1165
1166 /* The occurrences recorded in antic_occr are exactly those that
1167 we want to set to non-zero in ANTLOC. */
b5ce41ff 1168 if (antloc)
c4c81601
RK
1169 for (occr = expr->antic_occr; occr != NULL; occr = occr->next)
1170 {
1171 SET_BIT (antloc[BLOCK_NUM (occr->insn)], indx);
b5ce41ff 1172
c4c81601
RK
1173 /* While we're scanning the table, this is a good place to
1174 initialize this. */
1175 occr->deleted_p = 0;
1176 }
b5ce41ff
JL
1177
1178 /* The occurrences recorded in avail_occr are exactly those that
1179 we want to set to non-zero in COMP. */
1180 if (comp)
c4c81601
RK
1181 for (occr = expr->avail_occr; occr != NULL; occr = occr->next)
1182 {
1183 SET_BIT (comp[BLOCK_NUM (occr->insn)], indx);
b5ce41ff 1184
c4c81601
RK
1185 /* While we're scanning the table, this is a good place to
1186 initialize this. */
1187 occr->copied_p = 0;
1188 }
b5ce41ff
JL
1189
1190 /* While we're scanning the table, this is a good place to
1191 initialize this. */
1192 expr->reaching_reg = 0;
1193 }
7506f491 1194 }
7506f491
DE
1195}
1196\f
1197/* Register set information.
1198
1199 `reg_set_table' records where each register is set or otherwise
1200 modified. */
1201
1202static struct obstack reg_set_obstack;
1203
1204static void
1205alloc_reg_set_mem (n_regs)
1206 int n_regs;
1207{
c4c81601 1208 unsigned int n;
7506f491
DE
1209
1210 reg_set_table_size = n_regs + REG_SET_TABLE_SLOP;
1211 n = reg_set_table_size * sizeof (struct reg_set *);
1212 reg_set_table = (struct reg_set **) gmalloc (n);
961192e1 1213 memset ((char *) reg_set_table, 0, n);
7506f491
DE
1214
1215 gcc_obstack_init (&reg_set_obstack);
1216}
1217
1218static void
1219free_reg_set_mem ()
1220{
1221 free (reg_set_table);
6496a589 1222 obstack_free (&reg_set_obstack, NULL);
7506f491
DE
1223}
1224
1225/* Record REGNO in the reg_set table. */
1226
1227static void
1228record_one_set (regno, insn)
1229 int regno;
1230 rtx insn;
1231{
172890a2 1232 /* Allocate a new reg_set element and link it onto the list. */
63bc1d05 1233 struct reg_set *new_reg_info;
7506f491
DE
1234
1235 /* If the table isn't big enough, enlarge it. */
1236 if (regno >= reg_set_table_size)
1237 {
1238 int new_size = regno + REG_SET_TABLE_SLOP;
c4c81601
RK
1239
1240 reg_set_table
1241 = (struct reg_set **) grealloc ((char *) reg_set_table,
1242 new_size * sizeof (struct reg_set *));
961192e1 1243 memset ((char *) (reg_set_table + reg_set_table_size), 0,
8e42ace1 1244 (new_size - reg_set_table_size) * sizeof (struct reg_set *));
7506f491
DE
1245 reg_set_table_size = new_size;
1246 }
1247
1248 new_reg_info = (struct reg_set *) obstack_alloc (&reg_set_obstack,
1249 sizeof (struct reg_set));
1250 bytes_used += sizeof (struct reg_set);
1251 new_reg_info->insn = insn;
274969ea
MM
1252 new_reg_info->next = reg_set_table[regno];
1253 reg_set_table[regno] = new_reg_info;
7506f491
DE
1254}
1255
c4c81601
RK
1256/* Called from compute_sets via note_stores to handle one SET or CLOBBER in
1257 an insn. The DATA is really the instruction in which the SET is
1258 occurring. */
7506f491
DE
1259
1260static void
84832317 1261record_set_info (dest, setter, data)
50b2596f 1262 rtx dest, setter ATTRIBUTE_UNUSED;
84832317 1263 void *data;
7506f491 1264{
84832317
MM
1265 rtx record_set_insn = (rtx) data;
1266
c4c81601
RK
1267 if (GET_CODE (dest) == REG && REGNO (dest) >= FIRST_PSEUDO_REGISTER)
1268 record_one_set (REGNO (dest), record_set_insn);
7506f491
DE
1269}
1270
1271/* Scan the function and record each set of each pseudo-register.
1272
c4c81601
RK
1273 This is called once, at the start of the gcse pass. See the comments for
1274 `reg_set_table' for further documenation. */
7506f491
DE
1275
1276static void
1277compute_sets (f)
1278 rtx f;
1279{
c4c81601 1280 rtx insn;
7506f491 1281
c4c81601 1282 for (insn = f; insn != 0; insn = NEXT_INSN (insn))
2c3c49de 1283 if (INSN_P (insn))
c4c81601 1284 note_stores (PATTERN (insn), record_set_info, insn);
7506f491
DE
1285}
1286\f
1287/* Hash table support. */
1288
80c29cc4
RZ
1289/* For each register, the cuid of the first/last insn in the block
1290 that set it, or -1 if not set. */
c4c81601 1291#define NEVER_SET -1
80c29cc4
RZ
1292
1293struct reg_avail_info
1294{
0b17ab2f 1295 int last_bb;
80c29cc4
RZ
1296 int first_set;
1297 int last_set;
1298};
1299
1300static struct reg_avail_info *reg_avail_info;
0b17ab2f 1301static int current_bb;
7506f491 1302
7506f491 1303
fb0c0a12
RK
1304/* See whether X, the source of a set, is something we want to consider for
1305 GCSE. */
7506f491
DE
1306
1307static int
1308want_to_gcse_p (x)
1309 rtx x;
1310{
fb0c0a12
RK
1311 static rtx test_insn = 0;
1312 int num_clobbers = 0;
1313 int icode;
1314
c4c81601 1315 switch (GET_CODE (x))
7506f491
DE
1316 {
1317 case REG:
1318 case SUBREG:
1319 case CONST_INT:
1320 case CONST_DOUBLE:
69ef87e2 1321 case CONST_VECTOR:
7506f491
DE
1322 case CALL:
1323 return 0;
1324
1325 default:
1326 break;
1327 }
1328
fb0c0a12
RK
1329 /* If this is a valid operand, we are OK. If it's VOIDmode, we aren't. */
1330 if (general_operand (x, GET_MODE (x)))
1331 return 1;
1332 else if (GET_MODE (x) == VOIDmode)
1333 return 0;
1334
1335 /* Otherwise, check if we can make a valid insn from it. First initialize
1336 our test insn if we haven't already. */
1337 if (test_insn == 0)
1338 {
1339 test_insn
1340 = make_insn_raw (gen_rtx_SET (VOIDmode,
1341 gen_rtx_REG (word_mode,
1342 FIRST_PSEUDO_REGISTER * 2),
1343 const0_rtx));
1344 NEXT_INSN (test_insn) = PREV_INSN (test_insn) = 0;
1345 ggc_add_rtx_root (&test_insn, 1);
1346 }
1347
1348 /* Now make an insn like the one we would make when GCSE'ing and see if
1349 valid. */
1350 PUT_MODE (SET_DEST (PATTERN (test_insn)), GET_MODE (x));
1351 SET_SRC (PATTERN (test_insn)) = x;
1352 return ((icode = recog (PATTERN (test_insn), test_insn, &num_clobbers)) >= 0
1353 && (num_clobbers == 0 || ! added_clobbers_hard_reg_p (icode)));
7506f491
DE
1354}
1355
1356/* Return non-zero if the operands of expression X are unchanged from the
1357 start of INSN's basic block up to but not including INSN (if AVAIL_P == 0),
1358 or from INSN to the end of INSN's basic block (if AVAIL_P != 0). */
1359
1360static int
1361oprs_unchanged_p (x, insn, avail_p)
1362 rtx x, insn;
1363 int avail_p;
1364{
c4c81601 1365 int i, j;
7506f491 1366 enum rtx_code code;
6f7d635c 1367 const char *fmt;
7506f491 1368
7506f491
DE
1369 if (x == 0)
1370 return 1;
1371
1372 code = GET_CODE (x);
1373 switch (code)
1374 {
1375 case REG:
80c29cc4
RZ
1376 {
1377 struct reg_avail_info *info = &reg_avail_info[REGNO (x)];
1378
1379 if (info->last_bb != current_bb)
1380 return 1;
1381 if (avail_p)
1382 return info->last_set < INSN_CUID (insn);
1383 else
1384 return info->first_set >= INSN_CUID (insn);
1385 }
7506f491
DE
1386
1387 case MEM:
0b17ab2f 1388 if (load_killed_in_block_p (BASIC_BLOCK (current_bb), INSN_CUID (insn),
a13d4ebf
AM
1389 x, avail_p))
1390 return 0;
7506f491 1391 else
c4c81601 1392 return oprs_unchanged_p (XEXP (x, 0), insn, avail_p);
7506f491
DE
1393
1394 case PRE_DEC:
1395 case PRE_INC:
1396 case POST_DEC:
1397 case POST_INC:
4b983fdc
RH
1398 case PRE_MODIFY:
1399 case POST_MODIFY:
7506f491
DE
1400 return 0;
1401
1402 case PC:
1403 case CC0: /*FIXME*/
1404 case CONST:
1405 case CONST_INT:
1406 case CONST_DOUBLE:
69ef87e2 1407 case CONST_VECTOR:
7506f491
DE
1408 case SYMBOL_REF:
1409 case LABEL_REF:
1410 case ADDR_VEC:
1411 case ADDR_DIFF_VEC:
1412 return 1;
1413
1414 default:
1415 break;
1416 }
1417
c4c81601 1418 for (i = GET_RTX_LENGTH (code) - 1, fmt = GET_RTX_FORMAT (code); i >= 0; i--)
7506f491
DE
1419 {
1420 if (fmt[i] == 'e')
1421 {
c4c81601
RK
1422 /* If we are about to do the last recursive call needed at this
1423 level, change it into iteration. This function is called enough
1424 to be worth it. */
7506f491 1425 if (i == 0)
c4c81601
RK
1426 return oprs_unchanged_p (XEXP (x, i), insn, avail_p);
1427
1428 else if (! oprs_unchanged_p (XEXP (x, i), insn, avail_p))
7506f491
DE
1429 return 0;
1430 }
1431 else if (fmt[i] == 'E')
c4c81601
RK
1432 for (j = 0; j < XVECLEN (x, i); j++)
1433 if (! oprs_unchanged_p (XVECEXP (x, i, j), insn, avail_p))
1434 return 0;
7506f491
DE
1435 }
1436
1437 return 1;
1438}
1439
a13d4ebf
AM
1440/* Used for communication between mems_conflict_for_gcse_p and
1441 load_killed_in_block_p. Nonzero if mems_conflict_for_gcse_p finds a
1442 conflict between two memory references. */
1443static int gcse_mems_conflict_p;
1444
1445/* Used for communication between mems_conflict_for_gcse_p and
1446 load_killed_in_block_p. A memory reference for a load instruction,
1447 mems_conflict_for_gcse_p will see if a memory store conflicts with
1448 this memory load. */
1449static rtx gcse_mem_operand;
1450
1451/* DEST is the output of an instruction. If it is a memory reference, and
1452 possibly conflicts with the load found in gcse_mem_operand, then set
1453 gcse_mems_conflict_p to a nonzero value. */
1454
1455static void
1456mems_conflict_for_gcse_p (dest, setter, data)
1457 rtx dest, setter ATTRIBUTE_UNUSED;
1458 void *data ATTRIBUTE_UNUSED;
1459{
1460 while (GET_CODE (dest) == SUBREG
1461 || GET_CODE (dest) == ZERO_EXTRACT
1462 || GET_CODE (dest) == SIGN_EXTRACT
1463 || GET_CODE (dest) == STRICT_LOW_PART)
1464 dest = XEXP (dest, 0);
1465
1466 /* If DEST is not a MEM, then it will not conflict with the load. Note
1467 that function calls are assumed to clobber memory, but are handled
1468 elsewhere. */
1469 if (GET_CODE (dest) != MEM)
1470 return;
aaa4ca30 1471
a13d4ebf
AM
1472 /* If we are setting a MEM in our list of specially recognized MEMs,
1473 don't mark as killed this time. */
1474
1475 if (dest == gcse_mem_operand && pre_ldst_mems != NULL)
1476 {
1477 if (!find_rtx_in_ldst (dest))
1478 gcse_mems_conflict_p = 1;
1479 return;
1480 }
aaa4ca30 1481
a13d4ebf
AM
1482 if (true_dependence (dest, GET_MODE (dest), gcse_mem_operand,
1483 rtx_addr_varies_p))
1484 gcse_mems_conflict_p = 1;
1485}
1486
1487/* Return nonzero if the expression in X (a memory reference) is killed
1488 in block BB before or after the insn with the CUID in UID_LIMIT.
1489 AVAIL_P is nonzero for kills after UID_LIMIT, and zero for kills
1490 before UID_LIMIT.
1491
1492 To check the entire block, set UID_LIMIT to max_uid + 1 and
1493 AVAIL_P to 0. */
1494
1495static int
1496load_killed_in_block_p (bb, uid_limit, x, avail_p)
e2d2ed72 1497 basic_block bb;
a13d4ebf
AM
1498 int uid_limit;
1499 rtx x;
1500 int avail_p;
1501{
0b17ab2f 1502 rtx list_entry = modify_mem_list[bb->index];
a13d4ebf
AM
1503 while (list_entry)
1504 {
1505 rtx setter;
1506 /* Ignore entries in the list that do not apply. */
1507 if ((avail_p
1508 && INSN_CUID (XEXP (list_entry, 0)) < uid_limit)
1509 || (! avail_p
1510 && INSN_CUID (XEXP (list_entry, 0)) > uid_limit))
1511 {
1512 list_entry = XEXP (list_entry, 1);
1513 continue;
1514 }
1515
1516 setter = XEXP (list_entry, 0);
1517
1518 /* If SETTER is a call everything is clobbered. Note that calls
1519 to pure functions are never put on the list, so we need not
1520 worry about them. */
1521 if (GET_CODE (setter) == CALL_INSN)
1522 return 1;
1523
1524 /* SETTER must be an INSN of some kind that sets memory. Call
1525 note_stores to examine each hunk of memory that is modified.
1526
1527 The note_stores interface is pretty limited, so we have to
1528 communicate via global variables. Yuk. */
1529 gcse_mem_operand = x;
1530 gcse_mems_conflict_p = 0;
1531 note_stores (PATTERN (setter), mems_conflict_for_gcse_p, NULL);
1532 if (gcse_mems_conflict_p)
1533 return 1;
1534 list_entry = XEXP (list_entry, 1);
1535 }
1536 return 0;
1537}
1538
7506f491
DE
1539/* Return non-zero if the operands of expression X are unchanged from
1540 the start of INSN's basic block up to but not including INSN. */
1541
1542static int
1543oprs_anticipatable_p (x, insn)
1544 rtx x, insn;
1545{
1546 return oprs_unchanged_p (x, insn, 0);
1547}
1548
1549/* Return non-zero if the operands of expression X are unchanged from
1550 INSN to the end of INSN's basic block. */
1551
1552static int
1553oprs_available_p (x, insn)
1554 rtx x, insn;
1555{
1556 return oprs_unchanged_p (x, insn, 1);
1557}
1558
1559/* Hash expression X.
c4c81601
RK
1560
1561 MODE is only used if X is a CONST_INT. DO_NOT_RECORD_P is a boolean
1562 indicating if a volatile operand is found or if the expression contains
1563 something we don't want to insert in the table.
7506f491
DE
1564
1565 ??? One might want to merge this with canon_hash. Later. */
1566
1567static unsigned int
1568hash_expr (x, mode, do_not_record_p, hash_table_size)
1569 rtx x;
1570 enum machine_mode mode;
1571 int *do_not_record_p;
1572 int hash_table_size;
1573{
1574 unsigned int hash;
1575
1576 *do_not_record_p = 0;
1577
1578 hash = hash_expr_1 (x, mode, do_not_record_p);
1579 return hash % hash_table_size;
1580}
172890a2 1581
6462bb43 1582/* Hash a string. Just add its bytes up. */
172890a2 1583
6462bb43
AO
1584static inline unsigned
1585hash_string_1 (ps)
1586 const char *ps;
1587{
1588 unsigned hash = 0;
8e42ace1 1589 const unsigned char *p = (const unsigned char *) ps;
6462bb43
AO
1590
1591 if (p)
1592 while (*p)
1593 hash += *p++;
1594
1595 return hash;
1596}
7506f491
DE
1597
1598/* Subroutine of hash_expr to do the actual work. */
1599
1600static unsigned int
1601hash_expr_1 (x, mode, do_not_record_p)
1602 rtx x;
1603 enum machine_mode mode;
1604 int *do_not_record_p;
1605{
1606 int i, j;
1607 unsigned hash = 0;
1608 enum rtx_code code;
6f7d635c 1609 const char *fmt;
7506f491 1610
c4c81601
RK
1611 /* Used to turn recursion into iteration. We can't rely on GCC's
1612 tail-recursion eliminatio since we need to keep accumulating values
1613 in HASH. */
7506f491
DE
1614
1615 if (x == 0)
1616 return hash;
1617
c4c81601 1618 repeat:
7506f491
DE
1619 code = GET_CODE (x);
1620 switch (code)
1621 {
1622 case REG:
c4c81601
RK
1623 hash += ((unsigned int) REG << 7) + REGNO (x);
1624 return hash;
7506f491
DE
1625
1626 case CONST_INT:
c4c81601
RK
1627 hash += (((unsigned int) CONST_INT << 7) + (unsigned int) mode
1628 + (unsigned int) INTVAL (x));
1629 return hash;
7506f491
DE
1630
1631 case CONST_DOUBLE:
1632 /* This is like the general case, except that it only counts
1633 the integers representing the constant. */
c4c81601 1634 hash += (unsigned int) code + (unsigned int) GET_MODE (x);
7506f491
DE
1635 if (GET_MODE (x) != VOIDmode)
1636 for (i = 2; i < GET_RTX_LENGTH (CONST_DOUBLE); i++)
c4c81601 1637 hash += (unsigned int) XWINT (x, i);
7506f491 1638 else
c4c81601
RK
1639 hash += ((unsigned int) CONST_DOUBLE_LOW (x)
1640 + (unsigned int) CONST_DOUBLE_HIGH (x));
7506f491
DE
1641 return hash;
1642
69ef87e2
AH
1643 case CONST_VECTOR:
1644 {
1645 int units;
1646 rtx elt;
1647
1648 units = CONST_VECTOR_NUNITS (x);
1649
1650 for (i = 0; i < units; ++i)
1651 {
1652 elt = CONST_VECTOR_ELT (x, i);
1653 hash += hash_expr_1 (elt, GET_MODE (elt), do_not_record_p);
1654 }
1655
1656 return hash;
1657 }
1658
7506f491
DE
1659 /* Assume there is only one rtx object for any given label. */
1660 case LABEL_REF:
1661 /* We don't hash on the address of the CODE_LABEL to avoid bootstrap
1662 differences and differences between each stage's debugging dumps. */
c4c81601
RK
1663 hash += (((unsigned int) LABEL_REF << 7)
1664 + CODE_LABEL_NUMBER (XEXP (x, 0)));
7506f491
DE
1665 return hash;
1666
1667 case SYMBOL_REF:
1668 {
1669 /* Don't hash on the symbol's address to avoid bootstrap differences.
1670 Different hash values may cause expressions to be recorded in
1671 different orders and thus different registers to be used in the
1672 final assembler. This also avoids differences in the dump files
1673 between various stages. */
1674 unsigned int h = 0;
3cce094d 1675 const unsigned char *p = (const unsigned char *) XSTR (x, 0);
c4c81601 1676
7506f491
DE
1677 while (*p)
1678 h += (h << 7) + *p++; /* ??? revisit */
c4c81601
RK
1679
1680 hash += ((unsigned int) SYMBOL_REF << 7) + h;
7506f491
DE
1681 return hash;
1682 }
1683
1684 case MEM:
1685 if (MEM_VOLATILE_P (x))
1686 {
1687 *do_not_record_p = 1;
1688 return 0;
1689 }
c4c81601
RK
1690
1691 hash += (unsigned int) MEM;
d51f3632
JH
1692 /* We used alias set for hashing, but this is not good, since the alias
1693 set may differ in -fprofile-arcs and -fbranch-probabilities compilation
1694 causing the profiles to fail to match. */
7506f491
DE
1695 x = XEXP (x, 0);
1696 goto repeat;
1697
1698 case PRE_DEC:
1699 case PRE_INC:
1700 case POST_DEC:
1701 case POST_INC:
1702 case PC:
1703 case CC0:
1704 case CALL:
1705 case UNSPEC_VOLATILE:
1706 *do_not_record_p = 1;
1707 return 0;
1708
1709 case ASM_OPERANDS:
1710 if (MEM_VOLATILE_P (x))
1711 {
1712 *do_not_record_p = 1;
1713 return 0;
1714 }
6462bb43
AO
1715 else
1716 {
1717 /* We don't want to take the filename and line into account. */
1718 hash += (unsigned) code + (unsigned) GET_MODE (x)
1719 + hash_string_1 (ASM_OPERANDS_TEMPLATE (x))
1720 + hash_string_1 (ASM_OPERANDS_OUTPUT_CONSTRAINT (x))
1721 + (unsigned) ASM_OPERANDS_OUTPUT_IDX (x);
1722
1723 if (ASM_OPERANDS_INPUT_LENGTH (x))
1724 {
1725 for (i = 1; i < ASM_OPERANDS_INPUT_LENGTH (x); i++)
1726 {
1727 hash += (hash_expr_1 (ASM_OPERANDS_INPUT (x, i),
1728 GET_MODE (ASM_OPERANDS_INPUT (x, i)),
1729 do_not_record_p)
1730 + hash_string_1 (ASM_OPERANDS_INPUT_CONSTRAINT
1731 (x, i)));
1732 }
1733
1734 hash += hash_string_1 (ASM_OPERANDS_INPUT_CONSTRAINT (x, 0));
1735 x = ASM_OPERANDS_INPUT (x, 0);
1736 mode = GET_MODE (x);
1737 goto repeat;
1738 }
1739 return hash;
1740 }
7506f491
DE
1741
1742 default:
1743 break;
1744 }
1745
7506f491 1746 hash += (unsigned) code + (unsigned) GET_MODE (x);
c4c81601 1747 for (i = GET_RTX_LENGTH (code) - 1, fmt = GET_RTX_FORMAT (code); i >= 0; i--)
7506f491
DE
1748 {
1749 if (fmt[i] == 'e')
1750 {
7506f491
DE
1751 /* If we are about to do the last recursive call
1752 needed at this level, change it into iteration.
1753 This function is called enough to be worth it. */
1754 if (i == 0)
1755 {
c4c81601 1756 x = XEXP (x, i);
7506f491
DE
1757 goto repeat;
1758 }
c4c81601
RK
1759
1760 hash += hash_expr_1 (XEXP (x, i), 0, do_not_record_p);
7506f491
DE
1761 if (*do_not_record_p)
1762 return 0;
1763 }
c4c81601 1764
7506f491
DE
1765 else if (fmt[i] == 'E')
1766 for (j = 0; j < XVECLEN (x, i); j++)
1767 {
1768 hash += hash_expr_1 (XVECEXP (x, i, j), 0, do_not_record_p);
1769 if (*do_not_record_p)
1770 return 0;
1771 }
c4c81601 1772
7506f491 1773 else if (fmt[i] == 's')
6462bb43 1774 hash += hash_string_1 (XSTR (x, i));
7506f491 1775 else if (fmt[i] == 'i')
c4c81601 1776 hash += (unsigned int) XINT (x, i);
7506f491
DE
1777 else
1778 abort ();
1779 }
1780
1781 return hash;
1782}
1783
1784/* Hash a set of register REGNO.
1785
c4c81601
RK
1786 Sets are hashed on the register that is set. This simplifies the PRE copy
1787 propagation code.
7506f491
DE
1788
1789 ??? May need to make things more elaborate. Later, as necessary. */
1790
1791static unsigned int
1792hash_set (regno, hash_table_size)
1793 int regno;
1794 int hash_table_size;
1795{
1796 unsigned int hash;
1797
1798 hash = regno;
1799 return hash % hash_table_size;
1800}
1801
1802/* Return non-zero if exp1 is equivalent to exp2.
1803 ??? Borrowed from cse.c. Might want to remerge with cse.c. Later. */
1804
1805static int
1806expr_equiv_p (x, y)
1807 rtx x, y;
1808{
b3694847
SS
1809 int i, j;
1810 enum rtx_code code;
1811 const char *fmt;
7506f491
DE
1812
1813 if (x == y)
1814 return 1;
c4c81601 1815
7506f491
DE
1816 if (x == 0 || y == 0)
1817 return x == y;
1818
1819 code = GET_CODE (x);
1820 if (code != GET_CODE (y))
1821 return 0;
1822
1823 /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent. */
1824 if (GET_MODE (x) != GET_MODE (y))
1825 return 0;
1826
1827 switch (code)
1828 {
1829 case PC:
1830 case CC0:
1831 return x == y;
1832
1833 case CONST_INT:
1834 return INTVAL (x) == INTVAL (y);
1835
1836 case LABEL_REF:
1837 return XEXP (x, 0) == XEXP (y, 0);
1838
1839 case SYMBOL_REF:
1840 return XSTR (x, 0) == XSTR (y, 0);
1841
1842 case REG:
1843 return REGNO (x) == REGNO (y);
1844
297c3335
RH
1845 case MEM:
1846 /* Can't merge two expressions in different alias sets, since we can
1847 decide that the expression is transparent in a block when it isn't,
1848 due to it being set with the different alias set. */
1849 if (MEM_ALIAS_SET (x) != MEM_ALIAS_SET (y))
1850 return 0;
1851 break;
1852
7506f491
DE
1853 /* For commutative operations, check both orders. */
1854 case PLUS:
1855 case MULT:
1856 case AND:
1857 case IOR:
1858 case XOR:
1859 case NE:
1860 case EQ:
1861 return ((expr_equiv_p (XEXP (x, 0), XEXP (y, 0))
1862 && expr_equiv_p (XEXP (x, 1), XEXP (y, 1)))
1863 || (expr_equiv_p (XEXP (x, 0), XEXP (y, 1))
1864 && expr_equiv_p (XEXP (x, 1), XEXP (y, 0))));
1865
6462bb43
AO
1866 case ASM_OPERANDS:
1867 /* We don't use the generic code below because we want to
1868 disregard filename and line numbers. */
1869
1870 /* A volatile asm isn't equivalent to any other. */
1871 if (MEM_VOLATILE_P (x) || MEM_VOLATILE_P (y))
1872 return 0;
1873
1874 if (GET_MODE (x) != GET_MODE (y)
1875 || strcmp (ASM_OPERANDS_TEMPLATE (x), ASM_OPERANDS_TEMPLATE (y))
1876 || strcmp (ASM_OPERANDS_OUTPUT_CONSTRAINT (x),
1877 ASM_OPERANDS_OUTPUT_CONSTRAINT (y))
1878 || ASM_OPERANDS_OUTPUT_IDX (x) != ASM_OPERANDS_OUTPUT_IDX (y)
1879 || ASM_OPERANDS_INPUT_LENGTH (x) != ASM_OPERANDS_INPUT_LENGTH (y))
1880 return 0;
1881
1882 if (ASM_OPERANDS_INPUT_LENGTH (x))
1883 {
1884 for (i = ASM_OPERANDS_INPUT_LENGTH (x) - 1; i >= 0; i--)
1885 if (! expr_equiv_p (ASM_OPERANDS_INPUT (x, i),
1886 ASM_OPERANDS_INPUT (y, i))
1887 || strcmp (ASM_OPERANDS_INPUT_CONSTRAINT (x, i),
1888 ASM_OPERANDS_INPUT_CONSTRAINT (y, i)))
1889 return 0;
1890 }
1891
1892 return 1;
1893
7506f491
DE
1894 default:
1895 break;
1896 }
1897
1898 /* Compare the elements. If any pair of corresponding elements
1899 fail to match, return 0 for the whole thing. */
1900
1901 fmt = GET_RTX_FORMAT (code);
1902 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
1903 {
1904 switch (fmt[i])
1905 {
1906 case 'e':
1907 if (! expr_equiv_p (XEXP (x, i), XEXP (y, i)))
1908 return 0;
1909 break;
1910
1911 case 'E':
1912 if (XVECLEN (x, i) != XVECLEN (y, i))
1913 return 0;
1914 for (j = 0; j < XVECLEN (x, i); j++)
1915 if (! expr_equiv_p (XVECEXP (x, i, j), XVECEXP (y, i, j)))
1916 return 0;
1917 break;
1918
1919 case 's':
1920 if (strcmp (XSTR (x, i), XSTR (y, i)))
1921 return 0;
1922 break;
1923
1924 case 'i':
1925 if (XINT (x, i) != XINT (y, i))
1926 return 0;
1927 break;
1928
1929 case 'w':
1930 if (XWINT (x, i) != XWINT (y, i))
1931 return 0;
1932 break;
1933
1934 case '0':
1935 break;
aaa4ca30 1936
7506f491
DE
1937 default:
1938 abort ();
1939 }
8e42ace1 1940 }
7506f491
DE
1941
1942 return 1;
1943}
1944
1945/* Insert expression X in INSN in the hash table.
1946 If it is already present, record it as the last occurrence in INSN's
1947 basic block.
1948
1949 MODE is the mode of the value X is being stored into.
1950 It is only used if X is a CONST_INT.
1951
1952 ANTIC_P is non-zero if X is an anticipatable expression.
1953 AVAIL_P is non-zero if X is an available expression. */
1954
1955static void
1956insert_expr_in_table (x, mode, insn, antic_p, avail_p)
1957 rtx x;
1958 enum machine_mode mode;
1959 rtx insn;
1960 int antic_p, avail_p;
1961{
1962 int found, do_not_record_p;
1963 unsigned int hash;
1964 struct expr *cur_expr, *last_expr = NULL;
1965 struct occr *antic_occr, *avail_occr;
1966 struct occr *last_occr = NULL;
1967
1968 hash = hash_expr (x, mode, &do_not_record_p, expr_hash_table_size);
1969
1970 /* Do not insert expression in table if it contains volatile operands,
1971 or if hash_expr determines the expression is something we don't want
1972 to or can't handle. */
1973 if (do_not_record_p)
1974 return;
1975
1976 cur_expr = expr_hash_table[hash];
1977 found = 0;
1978
c4c81601 1979 while (cur_expr && 0 == (found = expr_equiv_p (cur_expr->expr, x)))
7506f491
DE
1980 {
1981 /* If the expression isn't found, save a pointer to the end of
1982 the list. */
1983 last_expr = cur_expr;
1984 cur_expr = cur_expr->next_same_hash;
1985 }
1986
1987 if (! found)
1988 {
1989 cur_expr = (struct expr *) gcse_alloc (sizeof (struct expr));
1990 bytes_used += sizeof (struct expr);
1991 if (expr_hash_table[hash] == NULL)
c4c81601
RK
1992 /* This is the first pattern that hashed to this index. */
1993 expr_hash_table[hash] = cur_expr;
7506f491 1994 else
c4c81601
RK
1995 /* Add EXPR to end of this hash chain. */
1996 last_expr->next_same_hash = cur_expr;
1997
7506f491
DE
1998 /* Set the fields of the expr element. */
1999 cur_expr->expr = x;
2000 cur_expr->bitmap_index = n_exprs++;
2001 cur_expr->next_same_hash = NULL;
2002 cur_expr->antic_occr = NULL;
2003 cur_expr->avail_occr = NULL;
2004 }
2005
2006 /* Now record the occurrence(s). */
7506f491
DE
2007 if (antic_p)
2008 {
2009 antic_occr = cur_expr->antic_occr;
2010
2011 /* Search for another occurrence in the same basic block. */
2012 while (antic_occr && BLOCK_NUM (antic_occr->insn) != BLOCK_NUM (insn))
2013 {
2014 /* If an occurrence isn't found, save a pointer to the end of
2015 the list. */
2016 last_occr = antic_occr;
2017 antic_occr = antic_occr->next;
2018 }
2019
2020 if (antic_occr)
c4c81601
RK
2021 /* Found another instance of the expression in the same basic block.
2022 Prefer the currently recorded one. We want the first one in the
2023 block and the block is scanned from start to end. */
2024 ; /* nothing to do */
7506f491
DE
2025 else
2026 {
2027 /* First occurrence of this expression in this basic block. */
2028 antic_occr = (struct occr *) gcse_alloc (sizeof (struct occr));
2029 bytes_used += sizeof (struct occr);
2030 /* First occurrence of this expression in any block? */
2031 if (cur_expr->antic_occr == NULL)
2032 cur_expr->antic_occr = antic_occr;
2033 else
2034 last_occr->next = antic_occr;
c4c81601 2035
7506f491
DE
2036 antic_occr->insn = insn;
2037 antic_occr->next = NULL;
2038 }
2039 }
2040
2041 if (avail_p)
2042 {
2043 avail_occr = cur_expr->avail_occr;
2044
2045 /* Search for another occurrence in the same basic block. */
2046 while (avail_occr && BLOCK_NUM (avail_occr->insn) != BLOCK_NUM (insn))
2047 {
2048 /* If an occurrence isn't found, save a pointer to the end of
2049 the list. */
2050 last_occr = avail_occr;
2051 avail_occr = avail_occr->next;
2052 }
2053
2054 if (avail_occr)
c4c81601
RK
2055 /* Found another instance of the expression in the same basic block.
2056 Prefer this occurrence to the currently recorded one. We want
2057 the last one in the block and the block is scanned from start
2058 to end. */
2059 avail_occr->insn = insn;
7506f491
DE
2060 else
2061 {
2062 /* First occurrence of this expression in this basic block. */
2063 avail_occr = (struct occr *) gcse_alloc (sizeof (struct occr));
2064 bytes_used += sizeof (struct occr);
c4c81601 2065
7506f491
DE
2066 /* First occurrence of this expression in any block? */
2067 if (cur_expr->avail_occr == NULL)
2068 cur_expr->avail_occr = avail_occr;
2069 else
2070 last_occr->next = avail_occr;
c4c81601 2071
7506f491
DE
2072 avail_occr->insn = insn;
2073 avail_occr->next = NULL;
2074 }
2075 }
2076}
2077
2078/* Insert pattern X in INSN in the hash table.
2079 X is a SET of a reg to either another reg or a constant.
2080 If it is already present, record it as the last occurrence in INSN's
2081 basic block. */
2082
2083static void
2084insert_set_in_table (x, insn)
2085 rtx x;
2086 rtx insn;
2087{
2088 int found;
2089 unsigned int hash;
2090 struct expr *cur_expr, *last_expr = NULL;
2091 struct occr *cur_occr, *last_occr = NULL;
2092
2093 if (GET_CODE (x) != SET
2094 || GET_CODE (SET_DEST (x)) != REG)
2095 abort ();
2096
2097 hash = hash_set (REGNO (SET_DEST (x)), set_hash_table_size);
2098
2099 cur_expr = set_hash_table[hash];
2100 found = 0;
2101
c4c81601 2102 while (cur_expr && 0 == (found = expr_equiv_p (cur_expr->expr, x)))
7506f491
DE
2103 {
2104 /* If the expression isn't found, save a pointer to the end of
2105 the list. */
2106 last_expr = cur_expr;
2107 cur_expr = cur_expr->next_same_hash;
2108 }
2109
2110 if (! found)
2111 {
2112 cur_expr = (struct expr *) gcse_alloc (sizeof (struct expr));
2113 bytes_used += sizeof (struct expr);
2114 if (set_hash_table[hash] == NULL)
c4c81601
RK
2115 /* This is the first pattern that hashed to this index. */
2116 set_hash_table[hash] = cur_expr;
7506f491 2117 else
c4c81601
RK
2118 /* Add EXPR to end of this hash chain. */
2119 last_expr->next_same_hash = cur_expr;
2120
7506f491
DE
2121 /* Set the fields of the expr element.
2122 We must copy X because it can be modified when copy propagation is
2123 performed on its operands. */
7506f491
DE
2124 cur_expr->expr = copy_rtx (x);
2125 cur_expr->bitmap_index = n_sets++;
2126 cur_expr->next_same_hash = NULL;
2127 cur_expr->antic_occr = NULL;
2128 cur_expr->avail_occr = NULL;
2129 }
2130
2131 /* Now record the occurrence. */
7506f491
DE
2132 cur_occr = cur_expr->avail_occr;
2133
2134 /* Search for another occurrence in the same basic block. */
2135 while (cur_occr && BLOCK_NUM (cur_occr->insn) != BLOCK_NUM (insn))
2136 {
2137 /* If an occurrence isn't found, save a pointer to the end of
2138 the list. */
2139 last_occr = cur_occr;
2140 cur_occr = cur_occr->next;
2141 }
2142
2143 if (cur_occr)
c4c81601
RK
2144 /* Found another instance of the expression in the same basic block.
2145 Prefer this occurrence to the currently recorded one. We want the
2146 last one in the block and the block is scanned from start to end. */
2147 cur_occr->insn = insn;
7506f491
DE
2148 else
2149 {
2150 /* First occurrence of this expression in this basic block. */
2151 cur_occr = (struct occr *) gcse_alloc (sizeof (struct occr));
2152 bytes_used += sizeof (struct occr);
c4c81601 2153
7506f491
DE
2154 /* First occurrence of this expression in any block? */
2155 if (cur_expr->avail_occr == NULL)
2156 cur_expr->avail_occr = cur_occr;
2157 else
2158 last_occr->next = cur_occr;
c4c81601 2159
7506f491
DE
2160 cur_occr->insn = insn;
2161 cur_occr->next = NULL;
2162 }
2163}
2164
c4c81601
RK
2165/* Scan pattern PAT of INSN and add an entry to the hash table. If SET_P is
2166 non-zero, this is for the assignment hash table, otherwise it is for the
2167 expression hash table. */
7506f491
DE
2168
2169static void
2170hash_scan_set (pat, insn, set_p)
2171 rtx pat, insn;
2172 int set_p;
2173{
2174 rtx src = SET_SRC (pat);
2175 rtx dest = SET_DEST (pat);
172890a2 2176 rtx note;
7506f491
DE
2177
2178 if (GET_CODE (src) == CALL)
2179 hash_scan_call (src, insn);
2180
172890a2 2181 else if (GET_CODE (dest) == REG)
7506f491 2182 {
172890a2 2183 unsigned int regno = REGNO (dest);
7506f491
DE
2184 rtx tmp;
2185
172890a2
RK
2186 /* If this is a single set and we are doing constant propagation,
2187 see if a REG_NOTE shows this equivalent to a constant. */
2188 if (set_p && (note = find_reg_equal_equiv_note (insn)) != 0
2189 && CONSTANT_P (XEXP (note, 0)))
2190 src = XEXP (note, 0), pat = gen_rtx_SET (VOIDmode, dest, src);
2191
7506f491
DE
2192 /* Only record sets of pseudo-regs in the hash table. */
2193 if (! set_p
2194 && regno >= FIRST_PSEUDO_REGISTER
2195 /* Don't GCSE something if we can't do a reg/reg copy. */
2196 && can_copy_p [GET_MODE (dest)]
068473ec
JH
2197 /* GCSE commonly inserts instruction after the insn. We can't
2198 do that easily for EH_REGION notes so disable GCSE on these
2199 for now. */
2200 && !find_reg_note (insn, REG_EH_REGION, NULL_RTX)
7506f491 2201 /* Is SET_SRC something we want to gcse? */
172890a2
RK
2202 && want_to_gcse_p (src)
2203 /* Don't CSE a nop. */
43e72072
JJ
2204 && ! set_noop_p (pat)
2205 /* Don't GCSE if it has attached REG_EQUIV note.
2206 At this point this only function parameters should have
2207 REG_EQUIV notes and if the argument slot is used somewhere
a1f300c0 2208 explicitly, it means address of parameter has been taken,
43e72072
JJ
2209 so we should not extend the lifetime of the pseudo. */
2210 && ((note = find_reg_note (insn, REG_EQUIV, NULL_RTX)) == 0
2211 || GET_CODE (XEXP (note, 0)) != MEM))
7506f491
DE
2212 {
2213 /* An expression is not anticipatable if its operands are
52d76e11
RK
2214 modified before this insn or if this is not the only SET in
2215 this insn. */
2216 int antic_p = oprs_anticipatable_p (src, insn) && single_set (insn);
7506f491 2217 /* An expression is not available if its operands are
eb296bd9
GK
2218 subsequently modified, including this insn. It's also not
2219 available if this is a branch, because we can't insert
2220 a set after the branch. */
2221 int avail_p = (oprs_available_p (src, insn)
2222 && ! JUMP_P (insn));
c4c81601 2223
7506f491
DE
2224 insert_expr_in_table (src, GET_MODE (dest), insn, antic_p, avail_p);
2225 }
c4c81601 2226
7506f491
DE
2227 /* Record sets for constant/copy propagation. */
2228 else if (set_p
2229 && regno >= FIRST_PSEUDO_REGISTER
2230 && ((GET_CODE (src) == REG
2231 && REGNO (src) >= FIRST_PSEUDO_REGISTER
172890a2
RK
2232 && can_copy_p [GET_MODE (dest)]
2233 && REGNO (src) != regno)
b446e5a2 2234 || CONSTANT_P (src))
7506f491
DE
2235 /* A copy is not available if its src or dest is subsequently
2236 modified. Here we want to search from INSN+1 on, but
2237 oprs_available_p searches from INSN on. */
2238 && (insn == BLOCK_END (BLOCK_NUM (insn))
2239 || ((tmp = next_nonnote_insn (insn)) != NULL_RTX
2240 && oprs_available_p (pat, tmp))))
2241 insert_set_in_table (pat, insn);
2242 }
7506f491
DE
2243}
2244
2245static void
2246hash_scan_clobber (x, insn)
50b2596f 2247 rtx x ATTRIBUTE_UNUSED, insn ATTRIBUTE_UNUSED;
7506f491
DE
2248{
2249 /* Currently nothing to do. */
2250}
2251
2252static void
2253hash_scan_call (x, insn)
50b2596f 2254 rtx x ATTRIBUTE_UNUSED, insn ATTRIBUTE_UNUSED;
7506f491
DE
2255{
2256 /* Currently nothing to do. */
2257}
2258
2259/* Process INSN and add hash table entries as appropriate.
2260
2261 Only available expressions that set a single pseudo-reg are recorded.
2262
2263 Single sets in a PARALLEL could be handled, but it's an extra complication
2264 that isn't dealt with right now. The trick is handling the CLOBBERs that
2265 are also in the PARALLEL. Later.
2266
2267 If SET_P is non-zero, this is for the assignment hash table,
ed79bb3d
R
2268 otherwise it is for the expression hash table.
2269 If IN_LIBCALL_BLOCK nonzero, we are in a libcall block, and should
2270 not record any expressions. */
7506f491
DE
2271
2272static void
ed79bb3d 2273hash_scan_insn (insn, set_p, in_libcall_block)
7506f491
DE
2274 rtx insn;
2275 int set_p;
48e87cef 2276 int in_libcall_block;
7506f491
DE
2277{
2278 rtx pat = PATTERN (insn);
c4c81601 2279 int i;
7506f491 2280
172890a2
RK
2281 if (in_libcall_block)
2282 return;
2283
7506f491
DE
2284 /* Pick out the sets of INSN and for other forms of instructions record
2285 what's been modified. */
2286
172890a2
RK
2287 if (GET_CODE (pat) == SET)
2288 hash_scan_set (pat, insn, set_p);
7506f491 2289 else if (GET_CODE (pat) == PARALLEL)
c4c81601
RK
2290 for (i = 0; i < XVECLEN (pat, 0); i++)
2291 {
2292 rtx x = XVECEXP (pat, 0, i);
7506f491 2293
c4c81601 2294 if (GET_CODE (x) == SET)
172890a2 2295 hash_scan_set (x, insn, set_p);
c4c81601
RK
2296 else if (GET_CODE (x) == CLOBBER)
2297 hash_scan_clobber (x, insn);
2298 else if (GET_CODE (x) == CALL)
2299 hash_scan_call (x, insn);
2300 }
7506f491 2301
7506f491
DE
2302 else if (GET_CODE (pat) == CLOBBER)
2303 hash_scan_clobber (pat, insn);
2304 else if (GET_CODE (pat) == CALL)
2305 hash_scan_call (pat, insn);
2306}
2307
2308static void
2309dump_hash_table (file, name, table, table_size, total_size)
2310 FILE *file;
dff01034 2311 const char *name;
7506f491
DE
2312 struct expr **table;
2313 int table_size, total_size;
2314{
2315 int i;
2316 /* Flattened out table, so it's printed in proper order. */
4da896b2
MM
2317 struct expr **flat_table;
2318 unsigned int *hash_val;
c4c81601 2319 struct expr *expr;
4da896b2
MM
2320
2321 flat_table
2322 = (struct expr **) xcalloc (total_size, sizeof (struct expr *));
2323 hash_val = (unsigned int *) xmalloc (total_size * sizeof (unsigned int));
7506f491 2324
7506f491 2325 for (i = 0; i < table_size; i++)
c4c81601
RK
2326 for (expr = table[i]; expr != NULL; expr = expr->next_same_hash)
2327 {
2328 flat_table[expr->bitmap_index] = expr;
2329 hash_val[expr->bitmap_index] = i;
2330 }
7506f491
DE
2331
2332 fprintf (file, "%s hash table (%d buckets, %d entries)\n",
2333 name, table_size, total_size);
2334
2335 for (i = 0; i < total_size; i++)
21318741
RK
2336 if (flat_table[i] != 0)
2337 {
a0ac9e5a 2338 expr = flat_table[i];
21318741
RK
2339 fprintf (file, "Index %d (hash value %d)\n ",
2340 expr->bitmap_index, hash_val[i]);
a0ac9e5a 2341 print_rtl (file, expr->expr);
21318741
RK
2342 fprintf (file, "\n");
2343 }
7506f491
DE
2344
2345 fprintf (file, "\n");
4da896b2 2346
4da896b2
MM
2347 free (flat_table);
2348 free (hash_val);
7506f491
DE
2349}
2350
2351/* Record register first/last/block set information for REGNO in INSN.
c4c81601 2352
80c29cc4 2353 first_set records the first place in the block where the register
7506f491 2354 is set and is used to compute "anticipatability".
c4c81601 2355
80c29cc4 2356 last_set records the last place in the block where the register
7506f491 2357 is set and is used to compute "availability".
c4c81601 2358
80c29cc4
RZ
2359 last_bb records the block for which first_set and last_set are
2360 valid, as a quick test to invalidate them.
2361
7506f491
DE
2362 reg_set_in_block records whether the register is set in the block
2363 and is used to compute "transparency". */
2364
2365static void
2366record_last_reg_set_info (insn, regno)
2367 rtx insn;
2368 int regno;
2369{
80c29cc4
RZ
2370 struct reg_avail_info *info = &reg_avail_info[regno];
2371 int cuid = INSN_CUID (insn);
c4c81601 2372
80c29cc4
RZ
2373 info->last_set = cuid;
2374 if (info->last_bb != current_bb)
2375 {
2376 info->last_bb = current_bb;
2377 info->first_set = cuid;
0b17ab2f 2378 SET_BIT (reg_set_in_block[current_bb], regno);
80c29cc4 2379 }
7506f491
DE
2380}
2381
a13d4ebf
AM
2382
2383/* Record all of the canonicalized MEMs of record_last_mem_set_info's insn.
2384 Note we store a pair of elements in the list, so they have to be
2385 taken off pairwise. */
2386
2387static void
2388canon_list_insert (dest, unused1, v_insn)
2389 rtx dest ATTRIBUTE_UNUSED;
2390 rtx unused1 ATTRIBUTE_UNUSED;
2391 void * v_insn;
2392{
2393 rtx dest_addr, insn;
0fe854a7 2394 int bb;
a13d4ebf
AM
2395
2396 while (GET_CODE (dest) == SUBREG
2397 || GET_CODE (dest) == ZERO_EXTRACT
2398 || GET_CODE (dest) == SIGN_EXTRACT
2399 || GET_CODE (dest) == STRICT_LOW_PART)
2400 dest = XEXP (dest, 0);
2401
2402 /* If DEST is not a MEM, then it will not conflict with a load. Note
2403 that function calls are assumed to clobber memory, but are handled
2404 elsewhere. */
2405
2406 if (GET_CODE (dest) != MEM)
2407 return;
2408
2409 dest_addr = get_addr (XEXP (dest, 0));
2410 dest_addr = canon_rtx (dest_addr);
2411 insn = (rtx) v_insn;
0fe854a7 2412 bb = BLOCK_NUM (insn);
a13d4ebf 2413
0fe854a7
RH
2414 canon_modify_mem_list[bb] =
2415 alloc_EXPR_LIST (VOIDmode, dest_addr, canon_modify_mem_list[bb]);
2416 canon_modify_mem_list[bb] =
2417 alloc_EXPR_LIST (VOIDmode, dest, canon_modify_mem_list[bb]);
2418 bitmap_set_bit (canon_modify_mem_list_set, bb);
a13d4ebf
AM
2419}
2420
a13d4ebf
AM
2421/* Record memory modification information for INSN. We do not actually care
2422 about the memory location(s) that are set, or even how they are set (consider
2423 a CALL_INSN). We merely need to record which insns modify memory. */
7506f491
DE
2424
2425static void
2426record_last_mem_set_info (insn)
2427 rtx insn;
2428{
0fe854a7
RH
2429 int bb = BLOCK_NUM (insn);
2430
ccef9ef5 2431 /* load_killed_in_block_p will handle the case of calls clobbering
dc297297 2432 everything. */
0fe854a7
RH
2433 modify_mem_list[bb] = alloc_INSN_LIST (insn, modify_mem_list[bb]);
2434 bitmap_set_bit (modify_mem_list_set, bb);
a13d4ebf
AM
2435
2436 if (GET_CODE (insn) == CALL_INSN)
2437 {
2438 /* Note that traversals of this loop (other than for free-ing)
2439 will break after encountering a CALL_INSN. So, there's no
dc297297 2440 need to insert a pair of items, as canon_list_insert does. */
0fe854a7
RH
2441 canon_modify_mem_list[bb] =
2442 alloc_INSN_LIST (insn, canon_modify_mem_list[bb]);
2443 bitmap_set_bit (canon_modify_mem_list_set, bb);
a13d4ebf
AM
2444 }
2445 else
0fe854a7 2446 note_stores (PATTERN (insn), canon_list_insert, (void*) insn);
7506f491
DE
2447}
2448
7506f491 2449/* Called from compute_hash_table via note_stores to handle one
84832317
MM
2450 SET or CLOBBER in an insn. DATA is really the instruction in which
2451 the SET is taking place. */
7506f491
DE
2452
2453static void
84832317 2454record_last_set_info (dest, setter, data)
50b2596f 2455 rtx dest, setter ATTRIBUTE_UNUSED;
84832317 2456 void *data;
7506f491 2457{
84832317
MM
2458 rtx last_set_insn = (rtx) data;
2459
7506f491
DE
2460 if (GET_CODE (dest) == SUBREG)
2461 dest = SUBREG_REG (dest);
2462
2463 if (GET_CODE (dest) == REG)
2464 record_last_reg_set_info (last_set_insn, REGNO (dest));
2465 else if (GET_CODE (dest) == MEM
2466 /* Ignore pushes, they clobber nothing. */
2467 && ! push_operand (dest, GET_MODE (dest)))
2468 record_last_mem_set_info (last_set_insn);
2469}
2470
2471/* Top level function to create an expression or assignment hash table.
2472
2473 Expression entries are placed in the hash table if
2474 - they are of the form (set (pseudo-reg) src),
2475 - src is something we want to perform GCSE on,
2476 - none of the operands are subsequently modified in the block
2477
2478 Assignment entries are placed in the hash table if
2479 - they are of the form (set (pseudo-reg) src),
2480 - src is something we want to perform const/copy propagation on,
2481 - none of the operands or target are subsequently modified in the block
c4c81601 2482
7506f491
DE
2483 Currently src must be a pseudo-reg or a const_int.
2484
2485 F is the first insn.
2486 SET_P is non-zero for computing the assignment hash table. */
2487
2488static void
b5ce41ff 2489compute_hash_table (set_p)
7506f491
DE
2490 int set_p;
2491{
80c29cc4 2492 unsigned int i;
7506f491
DE
2493
2494 /* While we compute the hash table we also compute a bit array of which
2495 registers are set in which blocks.
7506f491
DE
2496 ??? This isn't needed during const/copy propagation, but it's cheap to
2497 compute. Later. */
0b17ab2f 2498 sbitmap_vector_zero (reg_set_in_block, n_basic_blocks);
7506f491 2499
a13d4ebf 2500 /* re-Cache any INSN_LIST nodes we have allocated. */
73991d6a 2501 clear_modify_mem_tables ();
7506f491 2502 /* Some working arrays used to track first and last set in each block. */
80c29cc4
RZ
2503 reg_avail_info = (struct reg_avail_info*)
2504 gmalloc (max_gcse_regno * sizeof (struct reg_avail_info));
2505
2506 for (i = 0; i < max_gcse_regno; ++i)
0b17ab2f 2507 reg_avail_info[i].last_bb = NEVER_SET;
7506f491 2508
0b17ab2f 2509 for (current_bb = 0; current_bb < n_basic_blocks; current_bb++)
7506f491
DE
2510 {
2511 rtx insn;
770ae6cc 2512 unsigned int regno;
ed79bb3d 2513 int in_libcall_block;
7506f491
DE
2514
2515 /* First pass over the instructions records information used to
2516 determine when registers and memory are first and last set.
ccef9ef5 2517 ??? hard-reg reg_set_in_block computation
7506f491
DE
2518 could be moved to compute_sets since they currently don't change. */
2519
0b17ab2f
RH
2520 for (insn = BLOCK_HEAD (current_bb);
2521 insn && insn != NEXT_INSN (BLOCK_END (current_bb));
7506f491
DE
2522 insn = NEXT_INSN (insn))
2523 {
2c3c49de 2524 if (! INSN_P (insn))
7506f491
DE
2525 continue;
2526
2527 if (GET_CODE (insn) == CALL_INSN)
2528 {
19652adf
ZW
2529 bool clobbers_all = false;
2530#ifdef NON_SAVING_SETJMP
2531 if (NON_SAVING_SETJMP
2532 && find_reg_note (insn, REG_SETJMP, NULL_RTX))
2533 clobbers_all = true;
2534#endif
2535
7506f491 2536 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
19652adf
ZW
2537 if (clobbers_all
2538 || TEST_HARD_REG_BIT (regs_invalidated_by_call, regno))
7506f491 2539 record_last_reg_set_info (insn, regno);
c4c81601 2540
24a28584 2541 mark_call (insn);
7506f491
DE
2542 }
2543
84832317 2544 note_stores (PATTERN (insn), record_last_set_info, insn);
7506f491
DE
2545 }
2546
2547 /* The next pass builds the hash table. */
2548
0b17ab2f
RH
2549 for (insn = BLOCK_HEAD (current_bb), in_libcall_block = 0;
2550 insn && insn != NEXT_INSN (BLOCK_END (current_bb));
7506f491 2551 insn = NEXT_INSN (insn))
2c3c49de 2552 if (INSN_P (insn))
c4c81601
RK
2553 {
2554 if (find_reg_note (insn, REG_LIBCALL, NULL_RTX))
c63b1ae8
AM
2555 in_libcall_block = 1;
2556 else if (set_p && find_reg_note (insn, REG_RETVAL, NULL_RTX))
2557 in_libcall_block = 0;
2558 hash_scan_insn (insn, set_p, in_libcall_block);
2559 if (!set_p && find_reg_note (insn, REG_RETVAL, NULL_RTX))
2560 in_libcall_block = 0;
8e42ace1 2561 }
7506f491
DE
2562 }
2563
80c29cc4
RZ
2564 free (reg_avail_info);
2565 reg_avail_info = NULL;
7506f491
DE
2566}
2567
2568/* Allocate space for the set hash table.
2569 N_INSNS is the number of instructions in the function.
2570 It is used to determine the number of buckets to use. */
2571
2572static void
2573alloc_set_hash_table (n_insns)
2574 int n_insns;
2575{
2576 int n;
2577
2578 set_hash_table_size = n_insns / 4;
2579 if (set_hash_table_size < 11)
2580 set_hash_table_size = 11;
c4c81601 2581
7506f491
DE
2582 /* Attempt to maintain efficient use of hash table.
2583 Making it an odd number is simplest for now.
2584 ??? Later take some measurements. */
2585 set_hash_table_size |= 1;
2586 n = set_hash_table_size * sizeof (struct expr *);
2587 set_hash_table = (struct expr **) gmalloc (n);
2588}
2589
2590/* Free things allocated by alloc_set_hash_table. */
2591
2592static void
2593free_set_hash_table ()
2594{
2595 free (set_hash_table);
2596}
2597
2598/* Compute the hash table for doing copy/const propagation. */
2599
2600static void
b5ce41ff 2601compute_set_hash_table ()
7506f491
DE
2602{
2603 /* Initialize count of number of entries in hash table. */
2604 n_sets = 0;
961192e1 2605 memset ((char *) set_hash_table, 0,
8e42ace1 2606 set_hash_table_size * sizeof (struct expr *));
7506f491 2607
b5ce41ff 2608 compute_hash_table (1);
7506f491
DE
2609}
2610
2611/* Allocate space for the expression hash table.
2612 N_INSNS is the number of instructions in the function.
2613 It is used to determine the number of buckets to use. */
2614
2615static void
2616alloc_expr_hash_table (n_insns)
2e653e39 2617 unsigned int n_insns;
7506f491
DE
2618{
2619 int n;
2620
2621 expr_hash_table_size = n_insns / 2;
2622 /* Make sure the amount is usable. */
2623 if (expr_hash_table_size < 11)
2624 expr_hash_table_size = 11;
c4c81601 2625
7506f491
DE
2626 /* Attempt to maintain efficient use of hash table.
2627 Making it an odd number is simplest for now.
2628 ??? Later take some measurements. */
2629 expr_hash_table_size |= 1;
2630 n = expr_hash_table_size * sizeof (struct expr *);
2631 expr_hash_table = (struct expr **) gmalloc (n);
2632}
2633
2634/* Free things allocated by alloc_expr_hash_table. */
2635
2636static void
2637free_expr_hash_table ()
2638{
2639 free (expr_hash_table);
2640}
2641
2642/* Compute the hash table for doing GCSE. */
2643
2644static void
b5ce41ff 2645compute_expr_hash_table ()
7506f491
DE
2646{
2647 /* Initialize count of number of entries in hash table. */
2648 n_exprs = 0;
961192e1 2649 memset ((char *) expr_hash_table, 0,
8e42ace1 2650 expr_hash_table_size * sizeof (struct expr *));
7506f491 2651
b5ce41ff 2652 compute_hash_table (0);
7506f491
DE
2653}
2654\f
2655/* Expression tracking support. */
2656
2657/* Lookup pattern PAT in the expression table.
2658 The result is a pointer to the table entry, or NULL if not found. */
2659
2660static struct expr *
2661lookup_expr (pat)
2662 rtx pat;
2663{
2664 int do_not_record_p;
2665 unsigned int hash = hash_expr (pat, GET_MODE (pat), &do_not_record_p,
2666 expr_hash_table_size);
2667 struct expr *expr;
2668
2669 if (do_not_record_p)
2670 return NULL;
2671
2672 expr = expr_hash_table[hash];
2673
2674 while (expr && ! expr_equiv_p (expr->expr, pat))
2675 expr = expr->next_same_hash;
2676
2677 return expr;
2678}
2679
c4c81601
RK
2680/* Lookup REGNO in the set table. If PAT is non-NULL look for the entry that
2681 matches it, otherwise return the first entry for REGNO. The result is a
2682 pointer to the table entry, or NULL if not found. */
7506f491
DE
2683
2684static struct expr *
2685lookup_set (regno, pat)
770ae6cc 2686 unsigned int regno;
7506f491
DE
2687 rtx pat;
2688{
2689 unsigned int hash = hash_set (regno, set_hash_table_size);
2690 struct expr *expr;
2691
2692 expr = set_hash_table[hash];
2693
2694 if (pat)
2695 {
2696 while (expr && ! expr_equiv_p (expr->expr, pat))
2697 expr = expr->next_same_hash;
2698 }
2699 else
2700 {
2701 while (expr && REGNO (SET_DEST (expr->expr)) != regno)
2702 expr = expr->next_same_hash;
2703 }
2704
2705 return expr;
2706}
2707
2708/* Return the next entry for REGNO in list EXPR. */
2709
2710static struct expr *
2711next_set (regno, expr)
770ae6cc 2712 unsigned int regno;
7506f491
DE
2713 struct expr *expr;
2714{
2715 do
2716 expr = expr->next_same_hash;
2717 while (expr && REGNO (SET_DEST (expr->expr)) != regno);
c4c81601 2718
7506f491
DE
2719 return expr;
2720}
2721
0fe854a7
RH
2722/* Like free_INSN_LIST_list or free_EXPR_LIST_list, except that the node
2723 types may be mixed. */
2724
2725static void
2726free_insn_expr_list_list (listp)
2727 rtx *listp;
2728{
2729 rtx list, next;
2730
2731 for (list = *listp; list ; list = next)
2732 {
2733 next = XEXP (list, 1);
2734 if (GET_CODE (list) == EXPR_LIST)
2735 free_EXPR_LIST_node (list);
2736 else
2737 free_INSN_LIST_node (list);
2738 }
2739
2740 *listp = NULL;
2741}
2742
73991d6a
JH
2743/* Clear canon_modify_mem_list and modify_mem_list tables. */
2744static void
2745clear_modify_mem_tables ()
2746{
2747 int i;
2748
2749 EXECUTE_IF_SET_IN_BITMAP
0fe854a7
RH
2750 (modify_mem_list_set, 0, i, free_INSN_LIST_list (modify_mem_list + i));
2751 bitmap_clear (modify_mem_list_set);
73991d6a
JH
2752
2753 EXECUTE_IF_SET_IN_BITMAP
2754 (canon_modify_mem_list_set, 0, i,
0fe854a7
RH
2755 free_insn_expr_list_list (canon_modify_mem_list + i));
2756 bitmap_clear (canon_modify_mem_list_set);
73991d6a
JH
2757}
2758
2759/* Release memory used by modify_mem_list_set and canon_modify_mem_list_set. */
2760
2761static void
2762free_modify_mem_tables ()
2763{
2764 clear_modify_mem_tables ();
2765 free (modify_mem_list);
2766 free (canon_modify_mem_list);
2767 modify_mem_list = 0;
2768 canon_modify_mem_list = 0;
2769}
2770
7506f491
DE
2771/* Reset tables used to keep track of what's still available [since the
2772 start of the block]. */
2773
2774static void
2775reset_opr_set_tables ()
2776{
2777 /* Maintain a bitmap of which regs have been set since beginning of
2778 the block. */
73991d6a 2779 CLEAR_REG_SET (reg_set_bitmap);
c4c81601 2780
7506f491
DE
2781 /* Also keep a record of the last instruction to modify memory.
2782 For now this is very trivial, we only record whether any memory
2783 location has been modified. */
73991d6a 2784 clear_modify_mem_tables ();
7506f491
DE
2785}
2786
2787/* Return non-zero if the operands of X are not set before INSN in
2788 INSN's basic block. */
2789
2790static int
2791oprs_not_set_p (x, insn)
2792 rtx x, insn;
2793{
c4c81601 2794 int i, j;
7506f491 2795 enum rtx_code code;
6f7d635c 2796 const char *fmt;
7506f491 2797
7506f491
DE
2798 if (x == 0)
2799 return 1;
2800
2801 code = GET_CODE (x);
2802 switch (code)
2803 {
2804 case PC:
2805 case CC0:
2806 case CONST:
2807 case CONST_INT:
2808 case CONST_DOUBLE:
69ef87e2 2809 case CONST_VECTOR:
7506f491
DE
2810 case SYMBOL_REF:
2811 case LABEL_REF:
2812 case ADDR_VEC:
2813 case ADDR_DIFF_VEC:
2814 return 1;
2815
2816 case MEM:
e2d2ed72
AM
2817 if (load_killed_in_block_p (BLOCK_FOR_INSN (insn),
2818 INSN_CUID (insn), x, 0))
a13d4ebf 2819 return 0;
c4c81601
RK
2820 else
2821 return oprs_not_set_p (XEXP (x, 0), insn);
7506f491
DE
2822
2823 case REG:
73991d6a 2824 return ! REGNO_REG_SET_P (reg_set_bitmap, REGNO (x));
7506f491
DE
2825
2826 default:
2827 break;
2828 }
2829
c4c81601 2830 for (i = GET_RTX_LENGTH (code) - 1, fmt = GET_RTX_FORMAT (code); i >= 0; i--)
7506f491
DE
2831 {
2832 if (fmt[i] == 'e')
2833 {
7506f491
DE
2834 /* If we are about to do the last recursive call
2835 needed at this level, change it into iteration.
2836 This function is called enough to be worth it. */
2837 if (i == 0)
c4c81601
RK
2838 return oprs_not_set_p (XEXP (x, i), insn);
2839
2840 if (! oprs_not_set_p (XEXP (x, i), insn))
7506f491
DE
2841 return 0;
2842 }
2843 else if (fmt[i] == 'E')
c4c81601
RK
2844 for (j = 0; j < XVECLEN (x, i); j++)
2845 if (! oprs_not_set_p (XVECEXP (x, i, j), insn))
2846 return 0;
7506f491
DE
2847 }
2848
2849 return 1;
2850}
2851
2852/* Mark things set by a CALL. */
2853
2854static void
b5ce41ff
JL
2855mark_call (insn)
2856 rtx insn;
7506f491 2857{
24a28584 2858 if (! CONST_OR_PURE_CALL_P (insn))
a13d4ebf 2859 record_last_mem_set_info (insn);
7506f491
DE
2860}
2861
2862/* Mark things set by a SET. */
2863
2864static void
2865mark_set (pat, insn)
2866 rtx pat, insn;
2867{
2868 rtx dest = SET_DEST (pat);
2869
2870 while (GET_CODE (dest) == SUBREG
2871 || GET_CODE (dest) == ZERO_EXTRACT
2872 || GET_CODE (dest) == SIGN_EXTRACT
2873 || GET_CODE (dest) == STRICT_LOW_PART)
2874 dest = XEXP (dest, 0);
2875
a13d4ebf 2876 if (GET_CODE (dest) == REG)
73991d6a 2877 SET_REGNO_REG_SET (reg_set_bitmap, REGNO (dest));
a13d4ebf
AM
2878 else if (GET_CODE (dest) == MEM)
2879 record_last_mem_set_info (insn);
2880
7506f491 2881 if (GET_CODE (SET_SRC (pat)) == CALL)
b5ce41ff 2882 mark_call (insn);
7506f491
DE
2883}
2884
2885/* Record things set by a CLOBBER. */
2886
2887static void
2888mark_clobber (pat, insn)
2889 rtx pat, insn;
2890{
2891 rtx clob = XEXP (pat, 0);
2892
2893 while (GET_CODE (clob) == SUBREG || GET_CODE (clob) == STRICT_LOW_PART)
2894 clob = XEXP (clob, 0);
2895
a13d4ebf 2896 if (GET_CODE (clob) == REG)
73991d6a 2897 SET_REGNO_REG_SET (reg_set_bitmap, REGNO (clob));
a13d4ebf
AM
2898 else
2899 record_last_mem_set_info (insn);
7506f491
DE
2900}
2901
2902/* Record things set by INSN.
2903 This data is used by oprs_not_set_p. */
2904
2905static void
2906mark_oprs_set (insn)
2907 rtx insn;
2908{
2909 rtx pat = PATTERN (insn);
c4c81601 2910 int i;
7506f491
DE
2911
2912 if (GET_CODE (pat) == SET)
2913 mark_set (pat, insn);
2914 else if (GET_CODE (pat) == PARALLEL)
c4c81601
RK
2915 for (i = 0; i < XVECLEN (pat, 0); i++)
2916 {
2917 rtx x = XVECEXP (pat, 0, i);
2918
2919 if (GET_CODE (x) == SET)
2920 mark_set (x, insn);
2921 else if (GET_CODE (x) == CLOBBER)
2922 mark_clobber (x, insn);
2923 else if (GET_CODE (x) == CALL)
2924 mark_call (insn);
2925 }
7506f491 2926
7506f491
DE
2927 else if (GET_CODE (pat) == CLOBBER)
2928 mark_clobber (pat, insn);
2929 else if (GET_CODE (pat) == CALL)
b5ce41ff 2930 mark_call (insn);
7506f491 2931}
b5ce41ff 2932
7506f491
DE
2933\f
2934/* Classic GCSE reaching definition support. */
2935
2936/* Allocate reaching def variables. */
2937
2938static void
2939alloc_rd_mem (n_blocks, n_insns)
2940 int n_blocks, n_insns;
2941{
2942 rd_kill = (sbitmap *) sbitmap_vector_alloc (n_blocks, n_insns);
0b17ab2f 2943 sbitmap_vector_zero (rd_kill, n_basic_blocks);
7506f491
DE
2944
2945 rd_gen = (sbitmap *) sbitmap_vector_alloc (n_blocks, n_insns);
0b17ab2f 2946 sbitmap_vector_zero (rd_gen, n_basic_blocks);
7506f491
DE
2947
2948 reaching_defs = (sbitmap *) sbitmap_vector_alloc (n_blocks, n_insns);
0b17ab2f 2949 sbitmap_vector_zero (reaching_defs, n_basic_blocks);
7506f491
DE
2950
2951 rd_out = (sbitmap *) sbitmap_vector_alloc (n_blocks, n_insns);
0b17ab2f 2952 sbitmap_vector_zero (rd_out, n_basic_blocks);
7506f491
DE
2953}
2954
2955/* Free reaching def variables. */
2956
2957static void
2958free_rd_mem ()
2959{
5a660bff
DB
2960 sbitmap_vector_free (rd_kill);
2961 sbitmap_vector_free (rd_gen);
2962 sbitmap_vector_free (reaching_defs);
2963 sbitmap_vector_free (rd_out);
7506f491
DE
2964}
2965
c4c81601 2966/* Add INSN to the kills of BB. REGNO, set in BB, is killed by INSN. */
7506f491
DE
2967
2968static void
2969handle_rd_kill_set (insn, regno, bb)
2970 rtx insn;
e2d2ed72
AM
2971 int regno;
2972 basic_block bb;
7506f491 2973{
c4c81601 2974 struct reg_set *this_reg;
7506f491 2975
c4c81601
RK
2976 for (this_reg = reg_set_table[regno]; this_reg; this_reg = this_reg ->next)
2977 if (BLOCK_NUM (this_reg->insn) != BLOCK_NUM (insn))
0b17ab2f 2978 SET_BIT (rd_kill[bb->index], INSN_CUID (this_reg->insn));
7506f491
DE
2979}
2980
7506f491
DE
2981/* Compute the set of kill's for reaching definitions. */
2982
2983static void
2984compute_kill_rd ()
2985{
0b17ab2f 2986 int bb, cuid;
172890a2
RK
2987 unsigned int regno;
2988 int i;
7506f491
DE
2989
2990 /* For each block
2991 For each set bit in `gen' of the block (i.e each insn which
ac7c5af5
JL
2992 generates a definition in the block)
2993 Call the reg set by the insn corresponding to that bit regx
2994 Look at the linked list starting at reg_set_table[regx]
2995 For each setting of regx in the linked list, which is not in
2996 this block
6d2f8887 2997 Set the bit in `kill' corresponding to that insn. */
0b17ab2f 2998 for (bb = 0; bb < n_basic_blocks; bb++)
c4c81601 2999 for (cuid = 0; cuid < max_cuid; cuid++)
0b17ab2f 3000 if (TEST_BIT (rd_gen[bb], cuid))
7506f491 3001 {
c4c81601
RK
3002 rtx insn = CUID_INSN (cuid);
3003 rtx pat = PATTERN (insn);
7506f491 3004
c4c81601
RK
3005 if (GET_CODE (insn) == CALL_INSN)
3006 {
3007 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
4e2db584 3008 if (TEST_HARD_REG_BIT (regs_invalidated_by_call, regno))
0b17ab2f 3009 handle_rd_kill_set (insn, regno, BASIC_BLOCK (bb));
c4c81601 3010 }
7506f491 3011
c4c81601
RK
3012 if (GET_CODE (pat) == PARALLEL)
3013 {
3014 for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
7506f491 3015 {
c4c81601 3016 enum rtx_code code = GET_CODE (XVECEXP (pat, 0, i));
7506f491 3017
c4c81601
RK
3018 if ((code == SET || code == CLOBBER)
3019 && GET_CODE (XEXP (XVECEXP (pat, 0, i), 0)) == REG)
3020 handle_rd_kill_set (insn,
3021 REGNO (XEXP (XVECEXP (pat, 0, i), 0)),
0b17ab2f 3022 BASIC_BLOCK (bb));
ac7c5af5 3023 }
ac7c5af5 3024 }
c4c81601
RK
3025 else if (GET_CODE (pat) == SET && GET_CODE (SET_DEST (pat)) == REG)
3026 /* Each setting of this register outside of this block
3027 must be marked in the set of kills in this block. */
0b17ab2f 3028 handle_rd_kill_set (insn, REGNO (SET_DEST (pat)), BASIC_BLOCK (bb));
7506f491 3029 }
7506f491
DE
3030}
3031
3032/* Compute the reaching definitions as in
3033 Compilers Principles, Techniques, and Tools. Aho, Sethi, Ullman,
3034 Chapter 10. It is the same algorithm as used for computing available
3035 expressions but applied to the gens and kills of reaching definitions. */
3036
3037static void
3038compute_rd ()
3039{
0b17ab2f 3040 int bb, changed, passes;
7506f491 3041
0b17ab2f
RH
3042 for (bb = 0; bb < n_basic_blocks; bb++)
3043 sbitmap_copy (rd_out[bb] /*dst*/, rd_gen[bb] /*src*/);
7506f491
DE
3044
3045 passes = 0;
3046 changed = 1;
3047 while (changed)
3048 {
3049 changed = 0;
0b17ab2f 3050 for (bb = 0; bb < n_basic_blocks; bb++)
ac7c5af5 3051 {
0b17ab2f
RH
3052 sbitmap_union_of_preds (reaching_defs[bb], rd_out, bb);
3053 changed |= sbitmap_union_of_diff_cg (rd_out[bb], rd_gen[bb],
3054 reaching_defs[bb], rd_kill[bb]);
ac7c5af5 3055 }
7506f491
DE
3056 passes++;
3057 }
3058
3059 if (gcse_file)
3060 fprintf (gcse_file, "reaching def computation: %d passes\n", passes);
3061}
3062\f
3063/* Classic GCSE available expression support. */
3064
3065/* Allocate memory for available expression computation. */
3066
3067static void
3068alloc_avail_expr_mem (n_blocks, n_exprs)
3069 int n_blocks, n_exprs;
3070{
3071 ae_kill = (sbitmap *) sbitmap_vector_alloc (n_blocks, n_exprs);
0b17ab2f 3072 sbitmap_vector_zero (ae_kill, n_basic_blocks);
7506f491
DE
3073
3074 ae_gen = (sbitmap *) sbitmap_vector_alloc (n_blocks, n_exprs);
0b17ab2f 3075 sbitmap_vector_zero (ae_gen, n_basic_blocks);
7506f491
DE
3076
3077 ae_in = (sbitmap *) sbitmap_vector_alloc (n_blocks, n_exprs);
0b17ab2f 3078 sbitmap_vector_zero (ae_in, n_basic_blocks);
7506f491
DE
3079
3080 ae_out = (sbitmap *) sbitmap_vector_alloc (n_blocks, n_exprs);
0b17ab2f 3081 sbitmap_vector_zero (ae_out, n_basic_blocks);
7506f491
DE
3082}
3083
3084static void
3085free_avail_expr_mem ()
3086{
5a660bff
DB
3087 sbitmap_vector_free (ae_kill);
3088 sbitmap_vector_free (ae_gen);
3089 sbitmap_vector_free (ae_in);
3090 sbitmap_vector_free (ae_out);
7506f491
DE
3091}
3092
3093/* Compute the set of available expressions generated in each basic block. */
3094
3095static void
3096compute_ae_gen ()
3097{
2e653e39 3098 unsigned int i;
c4c81601
RK
3099 struct expr *expr;
3100 struct occr *occr;
7506f491
DE
3101
3102 /* For each recorded occurrence of each expression, set ae_gen[bb][expr].
3103 This is all we have to do because an expression is not recorded if it
3104 is not available, and the only expressions we want to work with are the
3105 ones that are recorded. */
7506f491 3106 for (i = 0; i < expr_hash_table_size; i++)
c4c81601
RK
3107 for (expr = expr_hash_table[i]; expr != 0; expr = expr->next_same_hash)
3108 for (occr = expr->avail_occr; occr != 0; occr = occr->next)
3109 SET_BIT (ae_gen[BLOCK_NUM (occr->insn)], expr->bitmap_index);
7506f491
DE
3110}
3111
3112/* Return non-zero if expression X is killed in BB. */
3113
3114static int
3115expr_killed_p (x, bb)
3116 rtx x;
e2d2ed72 3117 basic_block bb;
7506f491 3118{
c4c81601 3119 int i, j;
7506f491 3120 enum rtx_code code;
6f7d635c 3121 const char *fmt;
7506f491 3122
7506f491
DE
3123 if (x == 0)
3124 return 1;
3125
3126 code = GET_CODE (x);
3127 switch (code)
3128 {
3129 case REG:
0b17ab2f 3130 return TEST_BIT (reg_set_in_block[bb->index], REGNO (x));
7506f491
DE
3131
3132 case MEM:
a13d4ebf
AM
3133 if (load_killed_in_block_p (bb, get_max_uid () + 1, x, 0))
3134 return 1;
c4c81601
RK
3135 else
3136 return expr_killed_p (XEXP (x, 0), bb);
7506f491
DE
3137
3138 case PC:
3139 case CC0: /*FIXME*/
3140 case CONST:
3141 case CONST_INT:
3142 case CONST_DOUBLE:
69ef87e2 3143 case CONST_VECTOR:
7506f491
DE
3144 case SYMBOL_REF:
3145 case LABEL_REF:
3146 case ADDR_VEC:
3147 case ADDR_DIFF_VEC:
3148 return 0;
3149
3150 default:
3151 break;
3152 }
3153
c4c81601 3154 for (i = GET_RTX_LENGTH (code) - 1, fmt = GET_RTX_FORMAT (code); i >= 0; i--)
7506f491
DE
3155 {
3156 if (fmt[i] == 'e')
3157 {
7506f491
DE
3158 /* If we are about to do the last recursive call
3159 needed at this level, change it into iteration.
3160 This function is called enough to be worth it. */
3161 if (i == 0)
c4c81601
RK
3162 return expr_killed_p (XEXP (x, i), bb);
3163 else if (expr_killed_p (XEXP (x, i), bb))
7506f491
DE
3164 return 1;
3165 }
3166 else if (fmt[i] == 'E')
c4c81601
RK
3167 for (j = 0; j < XVECLEN (x, i); j++)
3168 if (expr_killed_p (XVECEXP (x, i, j), bb))
3169 return 1;
7506f491
DE
3170 }
3171
3172 return 0;
3173}
3174
3175/* Compute the set of available expressions killed in each basic block. */
3176
3177static void
a42cd965
AM
3178compute_ae_kill (ae_gen, ae_kill)
3179 sbitmap *ae_gen, *ae_kill;
7506f491 3180{
0b17ab2f 3181 int bb;
2e653e39 3182 unsigned int i;
c4c81601 3183 struct expr *expr;
7506f491 3184
0b17ab2f 3185 for (bb = 0; bb < n_basic_blocks; bb++)
c4c81601
RK
3186 for (i = 0; i < expr_hash_table_size; i++)
3187 for (expr = expr_hash_table[i]; expr; expr = expr->next_same_hash)
7506f491 3188 {
c4c81601 3189 /* Skip EXPR if generated in this block. */
0b17ab2f 3190 if (TEST_BIT (ae_gen[bb], expr->bitmap_index))
c4c81601 3191 continue;
7506f491 3192
0b17ab2f
RH
3193 if (expr_killed_p (expr->expr, BASIC_BLOCK (bb)))
3194 SET_BIT (ae_kill[bb], expr->bitmap_index);
7506f491 3195 }
7506f491 3196}
7506f491
DE
3197\f
3198/* Actually perform the Classic GCSE optimizations. */
3199
3200/* Return non-zero if occurrence OCCR of expression EXPR reaches block BB.
3201
3202 CHECK_SELF_LOOP is non-zero if we should consider a block reaching itself
3203 as a positive reach. We want to do this when there are two computations
3204 of the expression in the block.
3205
3206 VISITED is a pointer to a working buffer for tracking which BB's have
3207 been visited. It is NULL for the top-level call.
3208
3209 We treat reaching expressions that go through blocks containing the same
3210 reaching expression as "not reaching". E.g. if EXPR is generated in blocks
3211 2 and 3, INSN is in block 4, and 2->3->4, we treat the expression in block
3212 2 as not reaching. The intent is to improve the probability of finding
3213 only one reaching expression and to reduce register lifetimes by picking
3214 the closest such expression. */
3215
3216static int
283a2545 3217expr_reaches_here_p_work (occr, expr, bb, check_self_loop, visited)
7506f491
DE
3218 struct occr *occr;
3219 struct expr *expr;
e2d2ed72 3220 basic_block bb;
7506f491
DE
3221 int check_self_loop;
3222 char *visited;
3223{
36349f8b 3224 edge pred;
7506f491 3225
e2d2ed72 3226 for (pred = bb->pred; pred != NULL; pred = pred->pred_next)
7506f491 3227 {
e2d2ed72 3228 basic_block pred_bb = pred->src;
7506f491 3229
0b17ab2f 3230 if (visited[pred_bb->index])
c4c81601 3231 /* This predecessor has already been visited. Nothing to do. */
7506f491 3232 ;
7506f491 3233 else if (pred_bb == bb)
ac7c5af5 3234 {
7506f491
DE
3235 /* BB loops on itself. */
3236 if (check_self_loop
0b17ab2f
RH
3237 && TEST_BIT (ae_gen[pred_bb->index], expr->bitmap_index)
3238 && BLOCK_NUM (occr->insn) == pred_bb->index)
7506f491 3239 return 1;
c4c81601 3240
0b17ab2f 3241 visited[pred_bb->index] = 1;
ac7c5af5 3242 }
c4c81601 3243
7506f491 3244 /* Ignore this predecessor if it kills the expression. */
0b17ab2f
RH
3245 else if (TEST_BIT (ae_kill[pred_bb->index], expr->bitmap_index))
3246 visited[pred_bb->index] = 1;
c4c81601 3247
7506f491 3248 /* Does this predecessor generate this expression? */
0b17ab2f 3249 else if (TEST_BIT (ae_gen[pred_bb->index], expr->bitmap_index))
7506f491
DE
3250 {
3251 /* Is this the occurrence we're looking for?
3252 Note that there's only one generating occurrence per block
3253 so we just need to check the block number. */
0b17ab2f 3254 if (BLOCK_NUM (occr->insn) == pred_bb->index)
7506f491 3255 return 1;
c4c81601 3256
0b17ab2f 3257 visited[pred_bb->index] = 1;
7506f491 3258 }
c4c81601 3259
7506f491
DE
3260 /* Neither gen nor kill. */
3261 else
ac7c5af5 3262 {
0b17ab2f 3263 visited[pred_bb->index] = 1;
283a2545
RL
3264 if (expr_reaches_here_p_work (occr, expr, pred_bb, check_self_loop,
3265 visited))
c4c81601 3266
7506f491 3267 return 1;
ac7c5af5 3268 }
7506f491
DE
3269 }
3270
3271 /* All paths have been checked. */
3272 return 0;
3273}
3274
283a2545 3275/* This wrapper for expr_reaches_here_p_work() is to ensure that any
dc297297 3276 memory allocated for that function is returned. */
283a2545
RL
3277
3278static int
3279expr_reaches_here_p (occr, expr, bb, check_self_loop)
3280 struct occr *occr;
3281 struct expr *expr;
e2d2ed72 3282 basic_block bb;
283a2545
RL
3283 int check_self_loop;
3284{
3285 int rval;
0b17ab2f 3286 char *visited = (char *) xcalloc (n_basic_blocks, 1);
283a2545 3287
c4c81601 3288 rval = expr_reaches_here_p_work (occr, expr, bb, check_self_loop, visited);
283a2545
RL
3289
3290 free (visited);
c4c81601 3291 return rval;
283a2545
RL
3292}
3293
7506f491
DE
3294/* Return the instruction that computes EXPR that reaches INSN's basic block.
3295 If there is more than one such instruction, return NULL.
3296
3297 Called only by handle_avail_expr. */
3298
3299static rtx
3300computing_insn (expr, insn)
3301 struct expr *expr;
3302 rtx insn;
3303{
e2d2ed72 3304 basic_block bb = BLOCK_FOR_INSN (insn);
7506f491
DE
3305
3306 if (expr->avail_occr->next == NULL)
3307 {
e2d2ed72 3308 if (BLOCK_FOR_INSN (expr->avail_occr->insn) == bb)
c4c81601
RK
3309 /* The available expression is actually itself
3310 (i.e. a loop in the flow graph) so do nothing. */
3311 return NULL;
3312
7506f491
DE
3313 /* (FIXME) Case that we found a pattern that was created by
3314 a substitution that took place. */
3315 return expr->avail_occr->insn;
3316 }
3317 else
3318 {
3319 /* Pattern is computed more than once.
3320 Search backwards from this insn to see how many of these
3321 computations actually reach this insn. */
3322 struct occr *occr;
3323 rtx insn_computes_expr = NULL;
3324 int can_reach = 0;
3325
3326 for (occr = expr->avail_occr; occr != NULL; occr = occr->next)
3327 {
e2d2ed72 3328 if (BLOCK_FOR_INSN (occr->insn) == bb)
7506f491
DE
3329 {
3330 /* The expression is generated in this block.
3331 The only time we care about this is when the expression
3332 is generated later in the block [and thus there's a loop].
3333 We let the normal cse pass handle the other cases. */
c4c81601
RK
3334 if (INSN_CUID (insn) < INSN_CUID (occr->insn)
3335 && expr_reaches_here_p (occr, expr, bb, 1))
7506f491
DE
3336 {
3337 can_reach++;
3338 if (can_reach > 1)
3339 return NULL;
c4c81601 3340
7506f491
DE
3341 insn_computes_expr = occr->insn;
3342 }
3343 }
c4c81601
RK
3344 else if (expr_reaches_here_p (occr, expr, bb, 0))
3345 {
3346 can_reach++;
3347 if (can_reach > 1)
3348 return NULL;
3349
3350 insn_computes_expr = occr->insn;
3351 }
7506f491
DE
3352 }
3353
3354 if (insn_computes_expr == NULL)
3355 abort ();
c4c81601 3356
7506f491
DE
3357 return insn_computes_expr;
3358 }
3359}
3360
3361/* Return non-zero if the definition in DEF_INSN can reach INSN.
3362 Only called by can_disregard_other_sets. */
3363
3364static int
3365def_reaches_here_p (insn, def_insn)
3366 rtx insn, def_insn;
3367{
3368 rtx reg;
3369
3370 if (TEST_BIT (reaching_defs[BLOCK_NUM (insn)], INSN_CUID (def_insn)))
3371 return 1;
3372
3373 if (BLOCK_NUM (insn) == BLOCK_NUM (def_insn))
3374 {
3375 if (INSN_CUID (def_insn) < INSN_CUID (insn))
ac7c5af5 3376 {
7506f491
DE
3377 if (GET_CODE (PATTERN (def_insn)) == PARALLEL)
3378 return 1;
c4c81601 3379 else if (GET_CODE (PATTERN (def_insn)) == CLOBBER)
7506f491
DE
3380 reg = XEXP (PATTERN (def_insn), 0);
3381 else if (GET_CODE (PATTERN (def_insn)) == SET)
3382 reg = SET_DEST (PATTERN (def_insn));
3383 else
3384 abort ();
c4c81601 3385
7506f491
DE
3386 return ! reg_set_between_p (reg, NEXT_INSN (def_insn), insn);
3387 }
3388 else
3389 return 0;
3390 }
3391
3392 return 0;
3393}
3394
c4c81601
RK
3395/* Return non-zero if *ADDR_THIS_REG can only have one value at INSN. The
3396 value returned is the number of definitions that reach INSN. Returning a
3397 value of zero means that [maybe] more than one definition reaches INSN and
3398 the caller can't perform whatever optimization it is trying. i.e. it is
3399 always safe to return zero. */
7506f491
DE
3400
3401static int
3402can_disregard_other_sets (addr_this_reg, insn, for_combine)
3403 struct reg_set **addr_this_reg;
3404 rtx insn;
3405 int for_combine;
3406{
3407 int number_of_reaching_defs = 0;
c4c81601 3408 struct reg_set *this_reg;
7506f491 3409
c4c81601
RK
3410 for (this_reg = *addr_this_reg; this_reg != 0; this_reg = this_reg->next)
3411 if (def_reaches_here_p (insn, this_reg->insn))
3412 {
3413 number_of_reaching_defs++;
3414 /* Ignore parallels for now. */
3415 if (GET_CODE (PATTERN (this_reg->insn)) == PARALLEL)
3416 return 0;
3417
3418 if (!for_combine
3419 && (GET_CODE (PATTERN (this_reg->insn)) == CLOBBER
3420 || ! rtx_equal_p (SET_SRC (PATTERN (this_reg->insn)),
3421 SET_SRC (PATTERN (insn)))))
3422 /* A setting of the reg to a different value reaches INSN. */
3423 return 0;
3424
3425 if (number_of_reaching_defs > 1)
3426 {
3427 /* If in this setting the value the register is being set to is
3428 equal to the previous value the register was set to and this
3429 setting reaches the insn we are trying to do the substitution
3430 on then we are ok. */
3431 if (GET_CODE (PATTERN (this_reg->insn)) == CLOBBER)
7506f491 3432 return 0;
c4c81601
RK
3433 else if (! rtx_equal_p (SET_SRC (PATTERN (this_reg->insn)),
3434 SET_SRC (PATTERN (insn))))
3435 return 0;
3436 }
7506f491 3437
c4c81601
RK
3438 *addr_this_reg = this_reg;
3439 }
7506f491
DE
3440
3441 return number_of_reaching_defs;
3442}
3443
3444/* Expression computed by insn is available and the substitution is legal,
3445 so try to perform the substitution.
3446
3447 The result is non-zero if any changes were made. */
3448
3449static int
3450handle_avail_expr (insn, expr)
3451 rtx insn;
3452 struct expr *expr;
3453{
0631e0bf 3454 rtx pat, insn_computes_expr, expr_set;
7506f491
DE
3455 rtx to;
3456 struct reg_set *this_reg;
3457 int found_setting, use_src;
3458 int changed = 0;
3459
3460 /* We only handle the case where one computation of the expression
3461 reaches this instruction. */
3462 insn_computes_expr = computing_insn (expr, insn);
3463 if (insn_computes_expr == NULL)
3464 return 0;
0631e0bf
JH
3465 expr_set = single_set (insn_computes_expr);
3466 if (!expr_set)
3467 abort ();
7506f491
DE
3468
3469 found_setting = 0;
3470 use_src = 0;
3471
3472 /* At this point we know only one computation of EXPR outside of this
3473 block reaches this insn. Now try to find a register that the
3474 expression is computed into. */
0631e0bf 3475 if (GET_CODE (SET_SRC (expr_set)) == REG)
7506f491
DE
3476 {
3477 /* This is the case when the available expression that reaches
3478 here has already been handled as an available expression. */
770ae6cc 3479 unsigned int regnum_for_replacing
0631e0bf 3480 = REGNO (SET_SRC (expr_set));
c4c81601 3481
7506f491
DE
3482 /* If the register was created by GCSE we can't use `reg_set_table',
3483 however we know it's set only once. */
3484 if (regnum_for_replacing >= max_gcse_regno
3485 /* If the register the expression is computed into is set only once,
3486 or only one set reaches this insn, we can use it. */
3487 || (((this_reg = reg_set_table[regnum_for_replacing]),
3488 this_reg->next == NULL)
3489 || can_disregard_other_sets (&this_reg, insn, 0)))
8e42ace1
KH
3490 {
3491 use_src = 1;
3492 found_setting = 1;
3493 }
7506f491
DE
3494 }
3495
3496 if (!found_setting)
3497 {
770ae6cc 3498 unsigned int regnum_for_replacing
0631e0bf 3499 = REGNO (SET_DEST (expr_set));
c4c81601 3500
7506f491
DE
3501 /* This shouldn't happen. */
3502 if (regnum_for_replacing >= max_gcse_regno)
3503 abort ();
c4c81601 3504
7506f491 3505 this_reg = reg_set_table[regnum_for_replacing];
c4c81601 3506
7506f491
DE
3507 /* If the register the expression is computed into is set only once,
3508 or only one set reaches this insn, use it. */
3509 if (this_reg->next == NULL
3510 || can_disregard_other_sets (&this_reg, insn, 0))
3511 found_setting = 1;
3512 }
3513
3514 if (found_setting)
3515 {
3516 pat = PATTERN (insn);
3517 if (use_src)
0631e0bf 3518 to = SET_SRC (expr_set);
7506f491 3519 else
0631e0bf 3520 to = SET_DEST (expr_set);
7506f491
DE
3521 changed = validate_change (insn, &SET_SRC (pat), to, 0);
3522
3523 /* We should be able to ignore the return code from validate_change but
3524 to play it safe we check. */
3525 if (changed)
3526 {
3527 gcse_subst_count++;
3528 if (gcse_file != NULL)
3529 {
c4c81601
RK
3530 fprintf (gcse_file, "GCSE: Replacing the source in insn %d with",
3531 INSN_UID (insn));
3532 fprintf (gcse_file, " reg %d %s insn %d\n",
3533 REGNO (to), use_src ? "from" : "set in",
7506f491
DE
3534 INSN_UID (insn_computes_expr));
3535 }
7506f491
DE
3536 }
3537 }
c4c81601 3538
7506f491
DE
3539 /* The register that the expr is computed into is set more than once. */
3540 else if (1 /*expensive_op(this_pattrn->op) && do_expensive_gcse)*/)
3541 {
3542 /* Insert an insn after insnx that copies the reg set in insnx
3543 into a new pseudo register call this new register REGN.
3544 From insnb until end of basic block or until REGB is set
3545 replace all uses of REGB with REGN. */
3546 rtx new_insn;
3547
0631e0bf 3548 to = gen_reg_rtx (GET_MODE (SET_DEST (expr_set)));
7506f491
DE
3549
3550 /* Generate the new insn. */
3551 /* ??? If the change fails, we return 0, even though we created
3552 an insn. I think this is ok. */
9e6a5703
JC
3553 new_insn
3554 = emit_insn_after (gen_rtx_SET (VOIDmode, to,
0631e0bf 3555 SET_DEST (expr_set)),
c4c81601
RK
3556 insn_computes_expr);
3557
7506f491
DE
3558 /* Keep register set table up to date. */
3559 record_one_set (REGNO (to), new_insn);
3560
3561 gcse_create_count++;
3562 if (gcse_file != NULL)
ac7c5af5 3563 {
c4c81601 3564 fprintf (gcse_file, "GCSE: Creating insn %d to copy value of reg %d",
7506f491 3565 INSN_UID (NEXT_INSN (insn_computes_expr)),
c4c81601
RK
3566 REGNO (SET_SRC (PATTERN (NEXT_INSN (insn_computes_expr)))));
3567 fprintf (gcse_file, ", computed in insn %d,\n",
7506f491 3568 INSN_UID (insn_computes_expr));
c4c81601
RK
3569 fprintf (gcse_file, " into newly allocated reg %d\n",
3570 REGNO (to));
ac7c5af5 3571 }
7506f491
DE
3572
3573 pat = PATTERN (insn);
3574
3575 /* Do register replacement for INSN. */
3576 changed = validate_change (insn, &SET_SRC (pat),
c4c81601
RK
3577 SET_DEST (PATTERN
3578 (NEXT_INSN (insn_computes_expr))),
7506f491
DE
3579 0);
3580
3581 /* We should be able to ignore the return code from validate_change but
3582 to play it safe we check. */
3583 if (changed)
3584 {
3585 gcse_subst_count++;
3586 if (gcse_file != NULL)
3587 {
c4c81601
RK
3588 fprintf (gcse_file,
3589 "GCSE: Replacing the source in insn %d with reg %d ",
7506f491 3590 INSN_UID (insn),
c4c81601
RK
3591 REGNO (SET_DEST (PATTERN (NEXT_INSN
3592 (insn_computes_expr)))));
3593 fprintf (gcse_file, "set in insn %d\n",
7506f491
DE
3594 INSN_UID (insn_computes_expr));
3595 }
7506f491
DE
3596 }
3597 }
3598
3599 return changed;
3600}
3601
c4c81601
RK
3602/* Perform classic GCSE. This is called by one_classic_gcse_pass after all
3603 the dataflow analysis has been done.
7506f491
DE
3604
3605 The result is non-zero if a change was made. */
3606
3607static int
3608classic_gcse ()
3609{
0b17ab2f 3610 int bb, changed;
7506f491
DE
3611 rtx insn;
3612
3613 /* Note we start at block 1. */
3614
3615 changed = 0;
0b17ab2f 3616 for (bb = 1; bb < n_basic_blocks; bb++)
7506f491
DE
3617 {
3618 /* Reset tables used to keep track of what's still valid [since the
3619 start of the block]. */
3620 reset_opr_set_tables ();
3621
0b17ab2f
RH
3622 for (insn = BLOCK_HEAD (bb);
3623 insn != NULL && insn != NEXT_INSN (BLOCK_END (bb));
7506f491
DE
3624 insn = NEXT_INSN (insn))
3625 {
3626 /* Is insn of form (set (pseudo-reg) ...)? */
7506f491
DE
3627 if (GET_CODE (insn) == INSN
3628 && GET_CODE (PATTERN (insn)) == SET
3629 && GET_CODE (SET_DEST (PATTERN (insn))) == REG
3630 && REGNO (SET_DEST (PATTERN (insn))) >= FIRST_PSEUDO_REGISTER)
3631 {
3632 rtx pat = PATTERN (insn);
3633 rtx src = SET_SRC (pat);
3634 struct expr *expr;
3635
3636 if (want_to_gcse_p (src)
3637 /* Is the expression recorded? */
3638 && ((expr = lookup_expr (src)) != NULL)
3639 /* Is the expression available [at the start of the
3640 block]? */
0b17ab2f 3641 && TEST_BIT (ae_in[bb], expr->bitmap_index)
7506f491
DE
3642 /* Are the operands unchanged since the start of the
3643 block? */
3644 && oprs_not_set_p (src, insn))
3645 changed |= handle_avail_expr (insn, expr);
3646 }
3647
3648 /* Keep track of everything modified by this insn. */
3649 /* ??? Need to be careful w.r.t. mods done to INSN. */
2c3c49de 3650 if (INSN_P (insn))
7506f491 3651 mark_oprs_set (insn);
ac7c5af5 3652 }
7506f491
DE
3653 }
3654
3655 return changed;
3656}
3657
3658/* Top level routine to perform one classic GCSE pass.
3659
3660 Return non-zero if a change was made. */
3661
3662static int
b5ce41ff 3663one_classic_gcse_pass (pass)
7506f491
DE
3664 int pass;
3665{
3666 int changed = 0;
3667
3668 gcse_subst_count = 0;
3669 gcse_create_count = 0;
3670
3671 alloc_expr_hash_table (max_cuid);
0b17ab2f 3672 alloc_rd_mem (n_basic_blocks, max_cuid);
b5ce41ff 3673 compute_expr_hash_table ();
7506f491
DE
3674 if (gcse_file)
3675 dump_hash_table (gcse_file, "Expression", expr_hash_table,
3676 expr_hash_table_size, n_exprs);
c4c81601 3677
7506f491
DE
3678 if (n_exprs > 0)
3679 {
3680 compute_kill_rd ();
3681 compute_rd ();
0b17ab2f 3682 alloc_avail_expr_mem (n_basic_blocks, n_exprs);
7506f491 3683 compute_ae_gen ();
a42cd965 3684 compute_ae_kill (ae_gen, ae_kill);
bd0eaec2 3685 compute_available (ae_gen, ae_kill, ae_out, ae_in);
7506f491
DE
3686 changed = classic_gcse ();
3687 free_avail_expr_mem ();
3688 }
c4c81601 3689
7506f491
DE
3690 free_rd_mem ();
3691 free_expr_hash_table ();
3692
3693 if (gcse_file)
3694 {
3695 fprintf (gcse_file, "\n");
c4c81601
RK
3696 fprintf (gcse_file, "GCSE of %s, pass %d: %d bytes needed, %d substs,",
3697 current_function_name, pass, bytes_used, gcse_subst_count);
3698 fprintf (gcse_file, "%d insns created\n", gcse_create_count);
7506f491
DE
3699 }
3700
3701 return changed;
3702}
3703\f
3704/* Compute copy/constant propagation working variables. */
3705
3706/* Local properties of assignments. */
7506f491
DE
3707static sbitmap *cprop_pavloc;
3708static sbitmap *cprop_absaltered;
3709
3710/* Global properties of assignments (computed from the local properties). */
7506f491
DE
3711static sbitmap *cprop_avin;
3712static sbitmap *cprop_avout;
3713
c4c81601
RK
3714/* Allocate vars used for copy/const propagation. N_BLOCKS is the number of
3715 basic blocks. N_SETS is the number of sets. */
7506f491
DE
3716
3717static void
3718alloc_cprop_mem (n_blocks, n_sets)
3719 int n_blocks, n_sets;
3720{
3721 cprop_pavloc = sbitmap_vector_alloc (n_blocks, n_sets);
3722 cprop_absaltered = sbitmap_vector_alloc (n_blocks, n_sets);
3723
3724 cprop_avin = sbitmap_vector_alloc (n_blocks, n_sets);
3725 cprop_avout = sbitmap_vector_alloc (n_blocks, n_sets);
3726}
3727
3728/* Free vars used by copy/const propagation. */
3729
3730static void
3731free_cprop_mem ()
3732{
5a660bff
DB
3733 sbitmap_vector_free (cprop_pavloc);
3734 sbitmap_vector_free (cprop_absaltered);
3735 sbitmap_vector_free (cprop_avin);
3736 sbitmap_vector_free (cprop_avout);
7506f491
DE
3737}
3738
c4c81601
RK
3739/* For each block, compute whether X is transparent. X is either an
3740 expression or an assignment [though we don't care which, for this context
3741 an assignment is treated as an expression]. For each block where an
3742 element of X is modified, set (SET_P == 1) or reset (SET_P == 0) the INDX
3743 bit in BMAP. */
7506f491
DE
3744
3745static void
3746compute_transp (x, indx, bmap, set_p)
3747 rtx x;
3748 int indx;
3749 sbitmap *bmap;
3750 int set_p;
3751{
0b17ab2f 3752 int bb, i, j;
7506f491 3753 enum rtx_code code;
c4c81601 3754 reg_set *r;
6f7d635c 3755 const char *fmt;
7506f491 3756
c4c81601
RK
3757 /* repeat is used to turn tail-recursion into iteration since GCC
3758 can't do it when there's no return value. */
7506f491
DE
3759 repeat:
3760
3761 if (x == 0)
3762 return;
3763
3764 code = GET_CODE (x);
3765 switch (code)
3766 {
3767 case REG:
c4c81601
RK
3768 if (set_p)
3769 {
3770 if (REGNO (x) < FIRST_PSEUDO_REGISTER)
3771 {
0b17ab2f
RH
3772 for (bb = 0; bb < n_basic_blocks; bb++)
3773 if (TEST_BIT (reg_set_in_block[bb], REGNO (x)))
3774 SET_BIT (bmap[bb], indx);
c4c81601
RK
3775 }
3776 else
3777 {
3778 for (r = reg_set_table[REGNO (x)]; r != NULL; r = r->next)
3779 SET_BIT (bmap[BLOCK_NUM (r->insn)], indx);
3780 }
3781 }
3782 else
3783 {
3784 if (REGNO (x) < FIRST_PSEUDO_REGISTER)
3785 {
0b17ab2f
RH
3786 for (bb = 0; bb < n_basic_blocks; bb++)
3787 if (TEST_BIT (reg_set_in_block[bb], REGNO (x)))
3788 RESET_BIT (bmap[bb], indx);
c4c81601
RK
3789 }
3790 else
3791 {
3792 for (r = reg_set_table[REGNO (x)]; r != NULL; r = r->next)
3793 RESET_BIT (bmap[BLOCK_NUM (r->insn)], indx);
3794 }
3795 }
7506f491 3796
c4c81601 3797 return;
7506f491
DE
3798
3799 case MEM:
0b17ab2f 3800 for (bb = 0; bb < n_basic_blocks; bb++)
a13d4ebf 3801 {
0b17ab2f 3802 rtx list_entry = canon_modify_mem_list[bb];
a13d4ebf
AM
3803
3804 while (list_entry)
3805 {
3806 rtx dest, dest_addr;
3807
3808 if (GET_CODE (XEXP (list_entry, 0)) == CALL_INSN)
3809 {
3810 if (set_p)
0b17ab2f 3811 SET_BIT (bmap[bb], indx);
a13d4ebf 3812 else
0b17ab2f 3813 RESET_BIT (bmap[bb], indx);
a13d4ebf
AM
3814 break;
3815 }
3816 /* LIST_ENTRY must be an INSN of some kind that sets memory.
3817 Examine each hunk of memory that is modified. */
3818
3819 dest = XEXP (list_entry, 0);
3820 list_entry = XEXP (list_entry, 1);
3821 dest_addr = XEXP (list_entry, 0);
3822
3823 if (canon_true_dependence (dest, GET_MODE (dest), dest_addr,
3824 x, rtx_addr_varies_p))
3825 {
3826 if (set_p)
0b17ab2f 3827 SET_BIT (bmap[bb], indx);
a13d4ebf 3828 else
0b17ab2f 3829 RESET_BIT (bmap[bb], indx);
a13d4ebf
AM
3830 break;
3831 }
3832 list_entry = XEXP (list_entry, 1);
3833 }
3834 }
c4c81601 3835
7506f491
DE
3836 x = XEXP (x, 0);
3837 goto repeat;
3838
3839 case PC:
3840 case CC0: /*FIXME*/
3841 case CONST:
3842 case CONST_INT:
3843 case CONST_DOUBLE:
69ef87e2 3844 case CONST_VECTOR:
7506f491
DE
3845 case SYMBOL_REF:
3846 case LABEL_REF:
3847 case ADDR_VEC:
3848 case ADDR_DIFF_VEC:
3849 return;
3850
3851 default:
3852 break;
3853 }
3854
c4c81601 3855 for (i = GET_RTX_LENGTH (code) - 1, fmt = GET_RTX_FORMAT (code); i >= 0; i--)
7506f491
DE
3856 {
3857 if (fmt[i] == 'e')
3858 {
7506f491
DE
3859 /* If we are about to do the last recursive call
3860 needed at this level, change it into iteration.
3861 This function is called enough to be worth it. */
3862 if (i == 0)
3863 {
c4c81601 3864 x = XEXP (x, i);
7506f491
DE
3865 goto repeat;
3866 }
c4c81601
RK
3867
3868 compute_transp (XEXP (x, i), indx, bmap, set_p);
7506f491
DE
3869 }
3870 else if (fmt[i] == 'E')
c4c81601
RK
3871 for (j = 0; j < XVECLEN (x, i); j++)
3872 compute_transp (XVECEXP (x, i, j), indx, bmap, set_p);
7506f491
DE
3873 }
3874}
3875
7506f491
DE
3876/* Top level routine to do the dataflow analysis needed by copy/const
3877 propagation. */
3878
3879static void
3880compute_cprop_data ()
3881{
b5ce41ff 3882 compute_local_properties (cprop_absaltered, cprop_pavloc, NULL, 1);
ce724250
JL
3883 compute_available (cprop_pavloc, cprop_absaltered,
3884 cprop_avout, cprop_avin);
7506f491
DE
3885}
3886\f
3887/* Copy/constant propagation. */
3888
7506f491
DE
3889/* Maximum number of register uses in an insn that we handle. */
3890#define MAX_USES 8
3891
3892/* Table of uses found in an insn.
3893 Allocated statically to avoid alloc/free complexity and overhead. */
3894static struct reg_use reg_use_table[MAX_USES];
3895
3896/* Index into `reg_use_table' while building it. */
3897static int reg_use_count;
3898
c4c81601
RK
3899/* Set up a list of register numbers used in INSN. The found uses are stored
3900 in `reg_use_table'. `reg_use_count' is initialized to zero before entry,
3901 and contains the number of uses in the table upon exit.
7506f491 3902
c4c81601
RK
3903 ??? If a register appears multiple times we will record it multiple times.
3904 This doesn't hurt anything but it will slow things down. */
7506f491
DE
3905
3906static void
9e71c818
JH
3907find_used_regs (xptr, data)
3908 rtx *xptr;
3909 void *data ATTRIBUTE_UNUSED;
7506f491 3910{
c4c81601 3911 int i, j;
7506f491 3912 enum rtx_code code;
6f7d635c 3913 const char *fmt;
9e71c818 3914 rtx x = *xptr;
7506f491 3915
c4c81601
RK
3916 /* repeat is used to turn tail-recursion into iteration since GCC
3917 can't do it when there's no return value. */
7506f491 3918 repeat:
7506f491
DE
3919 if (x == 0)
3920 return;
3921
3922 code = GET_CODE (x);
9e71c818 3923 if (REG_P (x))
7506f491 3924 {
7506f491
DE
3925 if (reg_use_count == MAX_USES)
3926 return;
c4c81601 3927
7506f491
DE
3928 reg_use_table[reg_use_count].reg_rtx = x;
3929 reg_use_count++;
7506f491
DE
3930 }
3931
3932 /* Recursively scan the operands of this expression. */
3933
c4c81601 3934 for (i = GET_RTX_LENGTH (code) - 1, fmt = GET_RTX_FORMAT (code); i >= 0; i--)
7506f491
DE
3935 {
3936 if (fmt[i] == 'e')
3937 {
3938 /* If we are about to do the last recursive call
3939 needed at this level, change it into iteration.
3940 This function is called enough to be worth it. */
3941 if (i == 0)
3942 {
3943 x = XEXP (x, 0);
3944 goto repeat;
3945 }
c4c81601 3946
9e71c818 3947 find_used_regs (&XEXP (x, i), data);
7506f491
DE
3948 }
3949 else if (fmt[i] == 'E')
c4c81601 3950 for (j = 0; j < XVECLEN (x, i); j++)
9e71c818 3951 find_used_regs (&XVECEXP (x, i, j), data);
7506f491
DE
3952 }
3953}
3954
3955/* Try to replace all non-SET_DEST occurrences of FROM in INSN with TO.
3956 Returns non-zero is successful. */
3957
3958static int
3959try_replace_reg (from, to, insn)
3960 rtx from, to, insn;
3961{
172890a2 3962 rtx note = find_reg_equal_equiv_note (insn);
fb0c0a12 3963 rtx src = 0;
172890a2
RK
3964 int success = 0;
3965 rtx set = single_set (insn);
833fc3ad 3966
9e71c818
JH
3967 success = validate_replace_src (from, to, insn);
3968
3969 /* If above failed and this is a single set, try to simplify the source of
3970 the set given our substitution. We could perhaps try this for multiple
3971 SETs, but it probably won't buy us anything. */
3972 if (!success && set != 0)
833fc3ad 3973 {
172890a2
RK
3974 src = simplify_replace_rtx (SET_SRC (set), from, to);
3975
9e71c818
JH
3976 if (!rtx_equal_p (src, SET_SRC (set))
3977 && validate_change (insn, &SET_SRC (set), src, 0))
172890a2 3978 success = 1;
833fc3ad
JH
3979 }
3980
fb0c0a12
RK
3981 /* If we've failed to do replacement, have a single SET, and don't already
3982 have a note, add a REG_EQUAL note to not lose information. */
172890a2 3983 if (!success && note == 0 && set != 0)
7fcd7218 3984 note = set_unique_reg_note (insn, REG_EQUAL, copy_rtx (src));
e251e2a2 3985
172890a2
RK
3986 /* If there is already a NOTE, update the expression in it with our
3987 replacement. */
3988 else if (note != 0)
3989 XEXP (note, 0) = simplify_replace_rtx (XEXP (note, 0), from, to);
833fc3ad 3990
172890a2
RK
3991 /* REG_EQUAL may get simplified into register.
3992 We don't allow that. Remove that note. This code ought
3993 not to hapen, because previous code ought to syntetize
3994 reg-reg move, but be on the safe side. */
3995 if (note && REG_P (XEXP (note, 0)))
3996 remove_note (insn, note);
833fc3ad 3997
833fc3ad
JH
3998 return success;
3999}
c4c81601
RK
4000
4001/* Find a set of REGNOs that are available on entry to INSN's block. Returns
4002 NULL no such set is found. */
7506f491
DE
4003
4004static struct expr *
4005find_avail_set (regno, insn)
4006 int regno;
4007 rtx insn;
4008{
cafba495
BS
4009 /* SET1 contains the last set found that can be returned to the caller for
4010 use in a substitution. */
4011 struct expr *set1 = 0;
4012
4013 /* Loops are not possible here. To get a loop we would need two sets
4014 available at the start of the block containing INSN. ie we would
4015 need two sets like this available at the start of the block:
4016
4017 (set (reg X) (reg Y))
4018 (set (reg Y) (reg X))
4019
4020 This can not happen since the set of (reg Y) would have killed the
4021 set of (reg X) making it unavailable at the start of this block. */
4022 while (1)
8e42ace1 4023 {
cafba495
BS
4024 rtx src;
4025 struct expr *set = lookup_set (regno, NULL_RTX);
4026
4027 /* Find a set that is available at the start of the block
4028 which contains INSN. */
4029 while (set)
4030 {
4031 if (TEST_BIT (cprop_avin[BLOCK_NUM (insn)], set->bitmap_index))
4032 break;
4033 set = next_set (regno, set);
4034 }
7506f491 4035
cafba495
BS
4036 /* If no available set was found we've reached the end of the
4037 (possibly empty) copy chain. */
4038 if (set == 0)
4039 break;
4040
4041 if (GET_CODE (set->expr) != SET)
4042 abort ();
4043
4044 src = SET_SRC (set->expr);
4045
4046 /* We know the set is available.
4047 Now check that SRC is ANTLOC (i.e. none of the source operands
4048 have changed since the start of the block).
4049
4050 If the source operand changed, we may still use it for the next
4051 iteration of this loop, but we may not use it for substitutions. */
c4c81601 4052
cafba495
BS
4053 if (CONSTANT_P (src) || oprs_not_set_p (src, insn))
4054 set1 = set;
4055
4056 /* If the source of the set is anything except a register, then
4057 we have reached the end of the copy chain. */
4058 if (GET_CODE (src) != REG)
7506f491 4059 break;
7506f491 4060
cafba495
BS
4061 /* Follow the copy chain, ie start another iteration of the loop
4062 and see if we have an available copy into SRC. */
4063 regno = REGNO (src);
8e42ace1 4064 }
cafba495
BS
4065
4066 /* SET1 holds the last set that was available and anticipatable at
4067 INSN. */
4068 return set1;
7506f491
DE
4069}
4070
abd535b6 4071/* Subroutine of cprop_insn that tries to propagate constants into
172890a2
RK
4072 JUMP_INSNS. INSN must be a conditional jump. FROM is what we will try to
4073 replace, SRC is the constant we will try to substitute for it. Returns
4074 nonzero if a change was made. We know INSN has just a SET. */
c4c81601 4075
abd535b6 4076static int
0005550b 4077cprop_jump (bb, insn, from, src)
172890a2
RK
4078 rtx insn;
4079 rtx from;
abd535b6 4080 rtx src;
0005550b 4081 basic_block bb;
abd535b6 4082{
172890a2
RK
4083 rtx set = PATTERN (insn);
4084 rtx new = simplify_replace_rtx (SET_SRC (set), from, src);
abd535b6
BS
4085
4086 /* If no simplification can be made, then try the next
4087 register. */
172890a2 4088 if (rtx_equal_p (new, SET_SRC (set)))
abd535b6
BS
4089 return 0;
4090
7d5ab30e 4091 /* If this is now a no-op delete it, otherwise this must be a valid insn. */
172890a2 4092 if (new == pc_rtx)
7d5ab30e
JH
4093 delete_insn (insn);
4094 else
abd535b6 4095 {
7d5ab30e
JH
4096 if (! validate_change (insn, &SET_SRC (set), new, 0))
4097 return 0;
abd535b6 4098
7d5ab30e
JH
4099 /* If this has turned into an unconditional jump,
4100 then put a barrier after it so that the unreachable
4101 code will be deleted. */
4102 if (GET_CODE (SET_SRC (set)) == LABEL_REF)
4103 emit_barrier_after (insn);
4104 }
abd535b6 4105
172890a2 4106 run_jump_opt_after_gcse = 1;
c4c81601 4107
172890a2
RK
4108 const_prop_count++;
4109 if (gcse_file != NULL)
4110 {
4111 fprintf (gcse_file,
4112 "CONST-PROP: Replacing reg %d in insn %d with constant ",
4113 REGNO (from), INSN_UID (insn));
4114 print_rtl (gcse_file, src);
4115 fprintf (gcse_file, "\n");
abd535b6 4116 }
0005550b 4117 purge_dead_edges (bb);
172890a2
RK
4118
4119 return 1;
abd535b6
BS
4120}
4121
4122#ifdef HAVE_cc0
c4c81601
RK
4123
4124/* Subroutine of cprop_insn that tries to propagate constants into JUMP_INSNS
4125 for machines that have CC0. INSN is a single set that stores into CC0;
4126 the insn following it is a conditional jump. REG_USED is the use we will
4127 try to replace, SRC is the constant we will try to substitute for it.
abd535b6 4128 Returns nonzero if a change was made. */
c4c81601 4129
abd535b6 4130static int
0005550b
JH
4131cprop_cc0_jump (bb, insn, reg_used, src)
4132 basic_block bb;
abd535b6
BS
4133 rtx insn;
4134 struct reg_use *reg_used;
4135 rtx src;
4136{
172890a2
RK
4137 /* First substitute in the SET_SRC of INSN, then substitute that for
4138 CC0 in JUMP. */
abd535b6 4139 rtx jump = NEXT_INSN (insn);
172890a2
RK
4140 rtx new_src = simplify_replace_rtx (SET_SRC (PATTERN (insn)),
4141 reg_used->reg_rtx, src);
abd535b6 4142
0005550b 4143 if (! cprop_jump (bb, jump, cc0_rtx, new_src))
abd535b6
BS
4144 return 0;
4145
4146 /* If we succeeded, delete the cc0 setter. */
ca6c03ca 4147 delete_insn (insn);
172890a2 4148
abd535b6 4149 return 1;
8e42ace1 4150}
abd535b6
BS
4151#endif
4152
7506f491
DE
4153/* Perform constant and copy propagation on INSN.
4154 The result is non-zero if a change was made. */
4155
4156static int
0005550b
JH
4157cprop_insn (bb, insn, alter_jumps)
4158 basic_block bb;
7506f491 4159 rtx insn;
b5ce41ff 4160 int alter_jumps;
7506f491
DE
4161{
4162 struct reg_use *reg_used;
4163 int changed = 0;
833fc3ad 4164 rtx note;
7506f491 4165
9e71c818 4166 if (!INSN_P (insn))
7506f491
DE
4167 return 0;
4168
4169 reg_use_count = 0;
9e71c818 4170 note_uses (&PATTERN (insn), find_used_regs, NULL);
833fc3ad 4171
172890a2 4172 note = find_reg_equal_equiv_note (insn);
833fc3ad 4173
dc297297 4174 /* We may win even when propagating constants into notes. */
833fc3ad 4175 if (note)
9e71c818 4176 find_used_regs (&XEXP (note, 0), NULL);
7506f491 4177
c4c81601
RK
4178 for (reg_used = &reg_use_table[0]; reg_use_count > 0;
4179 reg_used++, reg_use_count--)
7506f491 4180 {
770ae6cc 4181 unsigned int regno = REGNO (reg_used->reg_rtx);
7506f491
DE
4182 rtx pat, src;
4183 struct expr *set;
7506f491
DE
4184
4185 /* Ignore registers created by GCSE.
dc297297 4186 We do this because ... */
7506f491
DE
4187 if (regno >= max_gcse_regno)
4188 continue;
4189
4190 /* If the register has already been set in this block, there's
4191 nothing we can do. */
4192 if (! oprs_not_set_p (reg_used->reg_rtx, insn))
4193 continue;
4194
4195 /* Find an assignment that sets reg_used and is available
4196 at the start of the block. */
4197 set = find_avail_set (regno, insn);
4198 if (! set)
4199 continue;
4200
4201 pat = set->expr;
4202 /* ??? We might be able to handle PARALLELs. Later. */
4203 if (GET_CODE (pat) != SET)
4204 abort ();
c4c81601 4205
7506f491
DE
4206 src = SET_SRC (pat);
4207
e78d9500 4208 /* Constant propagation. */
b446e5a2 4209 if (CONSTANT_P (src))
7506f491 4210 {
e78d9500
JL
4211 /* Handle normal insns first. */
4212 if (GET_CODE (insn) == INSN
4213 && try_replace_reg (reg_used->reg_rtx, src, insn))
7506f491
DE
4214 {
4215 changed = 1;
4216 const_prop_count++;
4217 if (gcse_file != NULL)
4218 {
c4c81601
RK
4219 fprintf (gcse_file, "CONST-PROP: Replacing reg %d in ",
4220 regno);
4221 fprintf (gcse_file, "insn %d with constant ",
4222 INSN_UID (insn));
e78d9500 4223 print_rtl (gcse_file, src);
7506f491
DE
4224 fprintf (gcse_file, "\n");
4225 }
4226
4227 /* The original insn setting reg_used may or may not now be
4228 deletable. We leave the deletion to flow. */
4229 }
e78d9500
JL
4230
4231 /* Try to propagate a CONST_INT into a conditional jump.
4232 We're pretty specific about what we will handle in this
4233 code, we can extend this as necessary over time.
4234
4235 Right now the insn in question must look like
abd535b6 4236 (set (pc) (if_then_else ...)) */
b5ce41ff 4237 else if (alter_jumps
6e9a3c38
JL
4238 && GET_CODE (insn) == JUMP_INSN
4239 && condjump_p (insn)
4240 && ! simplejump_p (insn))
0005550b 4241 changed |= cprop_jump (bb, insn, reg_used->reg_rtx, src);
172890a2 4242
abd535b6
BS
4243#ifdef HAVE_cc0
4244 /* Similar code for machines that use a pair of CC0 setter and
4245 conditional jump insn. */
4246 else if (alter_jumps
4247 && GET_CODE (PATTERN (insn)) == SET
4248 && SET_DEST (PATTERN (insn)) == cc0_rtx
4249 && GET_CODE (NEXT_INSN (insn)) == JUMP_INSN
4250 && condjump_p (NEXT_INSN (insn))
172890a2 4251 && ! simplejump_p (NEXT_INSN (insn))
21715220 4252 && cprop_cc0_jump (bb, insn, reg_used, src))
172890a2
RK
4253 {
4254 changed = 1;
4255 break;
d7836e38 4256 }
abd535b6 4257#endif
7506f491
DE
4258 }
4259 else if (GET_CODE (src) == REG
4260 && REGNO (src) >= FIRST_PSEUDO_REGISTER
4261 && REGNO (src) != regno)
4262 {
cafba495 4263 if (try_replace_reg (reg_used->reg_rtx, src, insn))
7506f491 4264 {
cafba495
BS
4265 changed = 1;
4266 copy_prop_count++;
4267 if (gcse_file != NULL)
7506f491 4268 {
c4c81601
RK
4269 fprintf (gcse_file, "COPY-PROP: Replacing reg %d in insn %d",
4270 regno, INSN_UID (insn));
4271 fprintf (gcse_file, " with reg %d\n", REGNO (src));
7506f491 4272 }
cafba495
BS
4273
4274 /* The original insn setting reg_used may or may not now be
4275 deletable. We leave the deletion to flow. */
4276 /* FIXME: If it turns out that the insn isn't deletable,
4277 then we may have unnecessarily extended register lifetimes
4278 and made things worse. */
7506f491
DE
4279 }
4280 }
4281 }
4282
4283 return changed;
4284}
4285
c4c81601
RK
4286/* Forward propagate copies. This includes copies and constants. Return
4287 non-zero if a change was made. */
7506f491
DE
4288
4289static int
b5ce41ff
JL
4290cprop (alter_jumps)
4291 int alter_jumps;
7506f491 4292{
0b17ab2f 4293 int bb, changed;
7506f491
DE
4294 rtx insn;
4295
4296 /* Note we start at block 1. */
4297
4298 changed = 0;
0b17ab2f 4299 for (bb = 1; bb < n_basic_blocks; bb++)
7506f491
DE
4300 {
4301 /* Reset tables used to keep track of what's still valid [since the
4302 start of the block]. */
4303 reset_opr_set_tables ();
4304
0b17ab2f
RH
4305 for (insn = BLOCK_HEAD (bb);
4306 insn != NULL && insn != NEXT_INSN (BLOCK_END (bb));
7506f491 4307 insn = NEXT_INSN (insn))
172890a2
RK
4308 if (INSN_P (insn))
4309 {
0b17ab2f 4310 changed |= cprop_insn (BASIC_BLOCK (bb), insn, alter_jumps);
7506f491 4311
172890a2
RK
4312 /* Keep track of everything modified by this insn. */
4313 /* ??? Need to be careful w.r.t. mods done to INSN. Don't
4314 call mark_oprs_set if we turned the insn into a NOTE. */
4315 if (GET_CODE (insn) != NOTE)
4316 mark_oprs_set (insn);
8e42ace1 4317 }
7506f491
DE
4318 }
4319
4320 if (gcse_file != NULL)
4321 fprintf (gcse_file, "\n");
4322
4323 return changed;
4324}
4325
4326/* Perform one copy/constant propagation pass.
4327 F is the first insn in the function.
4328 PASS is the pass count. */
4329
4330static int
b5ce41ff 4331one_cprop_pass (pass, alter_jumps)
7506f491 4332 int pass;
b5ce41ff 4333 int alter_jumps;
7506f491
DE
4334{
4335 int changed = 0;
4336
4337 const_prop_count = 0;
4338 copy_prop_count = 0;
4339
4340 alloc_set_hash_table (max_cuid);
b5ce41ff 4341 compute_set_hash_table ();
7506f491
DE
4342 if (gcse_file)
4343 dump_hash_table (gcse_file, "SET", set_hash_table, set_hash_table_size,
4344 n_sets);
4345 if (n_sets > 0)
4346 {
0b17ab2f 4347 alloc_cprop_mem (n_basic_blocks, n_sets);
7506f491 4348 compute_cprop_data ();
b5ce41ff 4349 changed = cprop (alter_jumps);
7506f491
DE
4350 free_cprop_mem ();
4351 }
c4c81601 4352
7506f491
DE
4353 free_set_hash_table ();
4354
4355 if (gcse_file)
4356 {
c4c81601
RK
4357 fprintf (gcse_file, "CPROP of %s, pass %d: %d bytes needed, ",
4358 current_function_name, pass, bytes_used);
4359 fprintf (gcse_file, "%d const props, %d copy props\n\n",
4360 const_prop_count, copy_prop_count);
7506f491
DE
4361 }
4362
4363 return changed;
4364}
4365\f
a65f3558 4366/* Compute PRE+LCM working variables. */
7506f491
DE
4367
4368/* Local properties of expressions. */
4369/* Nonzero for expressions that are transparent in the block. */
a65f3558 4370static sbitmap *transp;
7506f491 4371
5c35539b
RH
4372/* Nonzero for expressions that are transparent at the end of the block.
4373 This is only zero for expressions killed by abnormal critical edge
4374 created by a calls. */
a65f3558 4375static sbitmap *transpout;
5c35539b 4376
a65f3558
JL
4377/* Nonzero for expressions that are computed (available) in the block. */
4378static sbitmap *comp;
7506f491 4379
a65f3558
JL
4380/* Nonzero for expressions that are locally anticipatable in the block. */
4381static sbitmap *antloc;
7506f491 4382
a65f3558
JL
4383/* Nonzero for expressions where this block is an optimal computation
4384 point. */
4385static sbitmap *pre_optimal;
5c35539b 4386
a65f3558
JL
4387/* Nonzero for expressions which are redundant in a particular block. */
4388static sbitmap *pre_redundant;
7506f491 4389
a42cd965
AM
4390/* Nonzero for expressions which should be inserted on a specific edge. */
4391static sbitmap *pre_insert_map;
4392
4393/* Nonzero for expressions which should be deleted in a specific block. */
4394static sbitmap *pre_delete_map;
4395
4396/* Contains the edge_list returned by pre_edge_lcm. */
4397static struct edge_list *edge_list;
4398
a65f3558
JL
4399/* Redundant insns. */
4400static sbitmap pre_redundant_insns;
7506f491 4401
a65f3558 4402/* Allocate vars used for PRE analysis. */
7506f491
DE
4403
4404static void
a65f3558
JL
4405alloc_pre_mem (n_blocks, n_exprs)
4406 int n_blocks, n_exprs;
7506f491 4407{
a65f3558
JL
4408 transp = sbitmap_vector_alloc (n_blocks, n_exprs);
4409 comp = sbitmap_vector_alloc (n_blocks, n_exprs);
4410 antloc = sbitmap_vector_alloc (n_blocks, n_exprs);
5faf03ae 4411
a42cd965
AM
4412 pre_optimal = NULL;
4413 pre_redundant = NULL;
4414 pre_insert_map = NULL;
4415 pre_delete_map = NULL;
4416 ae_in = NULL;
4417 ae_out = NULL;
a42cd965 4418 ae_kill = sbitmap_vector_alloc (n_blocks, n_exprs);
c4c81601 4419
a42cd965 4420 /* pre_insert and pre_delete are allocated later. */
7506f491
DE
4421}
4422
a65f3558 4423/* Free vars used for PRE analysis. */
7506f491
DE
4424
4425static void
a65f3558 4426free_pre_mem ()
7506f491 4427{
5a660bff
DB
4428 sbitmap_vector_free (transp);
4429 sbitmap_vector_free (comp);
bd3675fc
JL
4430
4431 /* ANTLOC and AE_KILL are freed just after pre_lcm finishes. */
7506f491 4432
a42cd965 4433 if (pre_optimal)
5a660bff 4434 sbitmap_vector_free (pre_optimal);
a42cd965 4435 if (pre_redundant)
5a660bff 4436 sbitmap_vector_free (pre_redundant);
a42cd965 4437 if (pre_insert_map)
5a660bff 4438 sbitmap_vector_free (pre_insert_map);
a42cd965 4439 if (pre_delete_map)
5a660bff 4440 sbitmap_vector_free (pre_delete_map);
a42cd965 4441 if (ae_in)
5a660bff 4442 sbitmap_vector_free (ae_in);
a42cd965 4443 if (ae_out)
5a660bff 4444 sbitmap_vector_free (ae_out);
a42cd965 4445
bd3675fc 4446 transp = comp = NULL;
a42cd965 4447 pre_optimal = pre_redundant = pre_insert_map = pre_delete_map = NULL;
55d3f917 4448 ae_in = ae_out = NULL;
7506f491
DE
4449}
4450
4451/* Top level routine to do the dataflow analysis needed by PRE. */
4452
4453static void
4454compute_pre_data ()
4455{
b614171e 4456 sbitmap trapping_expr;
0b17ab2f 4457 int i;
b614171e 4458 unsigned int ui;
c66e8ae9 4459
a65f3558 4460 compute_local_properties (transp, comp, antloc, 0);
0b17ab2f 4461 sbitmap_vector_zero (ae_kill, n_basic_blocks);
c66e8ae9 4462
b614171e
MM
4463 /* Collect expressions which might trap. */
4464 trapping_expr = sbitmap_alloc (n_exprs);
4465 sbitmap_zero (trapping_expr);
4466 for (ui = 0; ui < expr_hash_table_size; ui++)
4467 {
4468 struct expr *e;
4469 for (e = expr_hash_table[ui]; e != NULL; e = e->next_same_hash)
4470 if (may_trap_p (e->expr))
4471 SET_BIT (trapping_expr, e->bitmap_index);
4472 }
4473
c66e8ae9
JL
4474 /* Compute ae_kill for each basic block using:
4475
4476 ~(TRANSP | COMP)
4477
a2e90653 4478 This is significantly faster than compute_ae_kill. */
c66e8ae9 4479
0b17ab2f 4480 for (i = 0; i < n_basic_blocks; i++)
c66e8ae9 4481 {
b614171e
MM
4482 edge e;
4483
4484 /* If the current block is the destination of an abnormal edge, we
4485 kill all trapping expressions because we won't be able to properly
4486 place the instruction on the edge. So make them neither
4487 anticipatable nor transparent. This is fairly conservative. */
0b17ab2f 4488 for (e = BASIC_BLOCK (i)->pred; e ; e = e->pred_next)
b614171e
MM
4489 if (e->flags & EDGE_ABNORMAL)
4490 {
0b17ab2f
RH
4491 sbitmap_difference (antloc[i], antloc[i], trapping_expr);
4492 sbitmap_difference (transp[i], transp[i], trapping_expr);
b614171e
MM
4493 break;
4494 }
4495
0b17ab2f
RH
4496 sbitmap_a_or_b (ae_kill[i], transp[i], comp[i]);
4497 sbitmap_not (ae_kill[i], ae_kill[i]);
c66e8ae9
JL
4498 }
4499
a42cd965
AM
4500 edge_list = pre_edge_lcm (gcse_file, n_exprs, transp, comp, antloc,
4501 ae_kill, &pre_insert_map, &pre_delete_map);
5a660bff 4502 sbitmap_vector_free (antloc);
bd3675fc 4503 antloc = NULL;
5a660bff 4504 sbitmap_vector_free (ae_kill);
bd3675fc 4505 ae_kill = NULL;
76ac938b 4506 sbitmap_free (trapping_expr);
7506f491
DE
4507}
4508\f
4509/* PRE utilities */
4510
a65f3558
JL
4511/* Return non-zero if an occurrence of expression EXPR in OCCR_BB would reach
4512 block BB.
7506f491
DE
4513
4514 VISITED is a pointer to a working buffer for tracking which BB's have
4515 been visited. It is NULL for the top-level call.
4516
4517 We treat reaching expressions that go through blocks containing the same
4518 reaching expression as "not reaching". E.g. if EXPR is generated in blocks
4519 2 and 3, INSN is in block 4, and 2->3->4, we treat the expression in block
4520 2 as not reaching. The intent is to improve the probability of finding
4521 only one reaching expression and to reduce register lifetimes by picking
4522 the closest such expression. */
4523
4524static int
89e606c9 4525pre_expr_reaches_here_p_work (occr_bb, expr, bb, visited)
e2d2ed72 4526 basic_block occr_bb;
7506f491 4527 struct expr *expr;
e2d2ed72 4528 basic_block bb;
7506f491
DE
4529 char *visited;
4530{
36349f8b 4531 edge pred;
7506f491 4532
e2d2ed72 4533 for (pred = bb->pred; pred != NULL; pred = pred->pred_next)
7506f491 4534 {
e2d2ed72 4535 basic_block pred_bb = pred->src;
7506f491 4536
36349f8b 4537 if (pred->src == ENTRY_BLOCK_PTR
7506f491 4538 /* Has predecessor has already been visited? */
0b17ab2f 4539 || visited[pred_bb->index])
c4c81601
RK
4540 ;/* Nothing to do. */
4541
7506f491 4542 /* Does this predecessor generate this expression? */
0b17ab2f 4543 else if (TEST_BIT (comp[pred_bb->index], expr->bitmap_index))
7506f491
DE
4544 {
4545 /* Is this the occurrence we're looking for?
4546 Note that there's only one generating occurrence per block
4547 so we just need to check the block number. */
a65f3558 4548 if (occr_bb == pred_bb)
7506f491 4549 return 1;
c4c81601 4550
0b17ab2f 4551 visited[pred_bb->index] = 1;
7506f491
DE
4552 }
4553 /* Ignore this predecessor if it kills the expression. */
0b17ab2f
RH
4554 else if (! TEST_BIT (transp[pred_bb->index], expr->bitmap_index))
4555 visited[pred_bb->index] = 1;
c4c81601 4556
7506f491
DE
4557 /* Neither gen nor kill. */
4558 else
ac7c5af5 4559 {
0b17ab2f 4560 visited[pred_bb->index] = 1;
89e606c9 4561 if (pre_expr_reaches_here_p_work (occr_bb, expr, pred_bb, visited))
7506f491 4562 return 1;
ac7c5af5 4563 }
7506f491
DE
4564 }
4565
4566 /* All paths have been checked. */
4567 return 0;
4568}
283a2545
RL
4569
4570/* The wrapper for pre_expr_reaches_here_work that ensures that any
dc297297 4571 memory allocated for that function is returned. */
283a2545
RL
4572
4573static int
89e606c9 4574pre_expr_reaches_here_p (occr_bb, expr, bb)
e2d2ed72 4575 basic_block occr_bb;
283a2545 4576 struct expr *expr;
e2d2ed72 4577 basic_block bb;
283a2545
RL
4578{
4579 int rval;
0b17ab2f 4580 char *visited = (char *) xcalloc (n_basic_blocks, 1);
283a2545 4581
8e42ace1 4582 rval = pre_expr_reaches_here_p_work (occr_bb, expr, bb, visited);
283a2545
RL
4583
4584 free (visited);
c4c81601 4585 return rval;
283a2545 4586}
7506f491 4587\f
a42cd965
AM
4588
4589/* Given an expr, generate RTL which we can insert at the end of a BB,
4590 or on an edge. Set the block number of any insns generated to
4591 the value of BB. */
4592
4593static rtx
4594process_insert_insn (expr)
4595 struct expr *expr;
4596{
4597 rtx reg = expr->reaching_reg;
fb0c0a12
RK
4598 rtx exp = copy_rtx (expr->expr);
4599 rtx pat;
a42cd965
AM
4600
4601 start_sequence ();
fb0c0a12
RK
4602
4603 /* If the expression is something that's an operand, like a constant,
4604 just copy it to a register. */
4605 if (general_operand (exp, GET_MODE (reg)))
4606 emit_move_insn (reg, exp);
4607
4608 /* Otherwise, make a new insn to compute this expression and make sure the
4609 insn will be recognized (this also adds any needed CLOBBERs). Copy the
4610 expression to make sure we don't have any sharing issues. */
8d444206 4611 else if (insn_invalid_p (emit_insn (gen_rtx_SET (VOIDmode, reg, exp))))
fb0c0a12
RK
4612 abort ();
4613
a42cd965
AM
4614 pat = gen_sequence ();
4615 end_sequence ();
4616
4617 return pat;
4618}
4619
a65f3558
JL
4620/* Add EXPR to the end of basic block BB.
4621
4622 This is used by both the PRE and code hoisting.
4623
4624 For PRE, we want to verify that the expr is either transparent
4625 or locally anticipatable in the target block. This check makes
4626 no sense for code hoisting. */
7506f491
DE
4627
4628static void
a65f3558 4629insert_insn_end_bb (expr, bb, pre)
7506f491 4630 struct expr *expr;
e2d2ed72 4631 basic_block bb;
a65f3558 4632 int pre;
7506f491 4633{
e2d2ed72 4634 rtx insn = bb->end;
7506f491
DE
4635 rtx new_insn;
4636 rtx reg = expr->reaching_reg;
4637 int regno = REGNO (reg);
a42cd965 4638 rtx pat;
c4c81601 4639 int i;
7506f491 4640
a42cd965 4641 pat = process_insert_insn (expr);
7506f491
DE
4642
4643 /* If the last insn is a jump, insert EXPR in front [taking care to
068473ec
JH
4644 handle cc0, etc. properly]. Similary we need to care trapping
4645 instructions in presence of non-call exceptions. */
7506f491 4646
068473ec
JH
4647 if (GET_CODE (insn) == JUMP_INSN
4648 || (GET_CODE (insn) == INSN
4649 && (bb->succ->succ_next || (bb->succ->flags & EDGE_ABNORMAL))))
7506f491 4650 {
50b2596f 4651#ifdef HAVE_cc0
7506f491 4652 rtx note;
50b2596f 4653#endif
068473ec
JH
4654 /* It should always be the case that we can put these instructions
4655 anywhere in the basic block with performing PRE optimizations.
4656 Check this. */
3b25fbfe 4657 if (GET_CODE (insn) == INSN && pre
0b17ab2f
RH
4658 && !TEST_BIT (antloc[bb->index], expr->bitmap_index)
4659 && !TEST_BIT (transp[bb->index], expr->bitmap_index))
068473ec 4660 abort ();
7506f491
DE
4661
4662 /* If this is a jump table, then we can't insert stuff here. Since
4663 we know the previous real insn must be the tablejump, we insert
4664 the new instruction just before the tablejump. */
4665 if (GET_CODE (PATTERN (insn)) == ADDR_VEC
4666 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC)
4667 insn = prev_real_insn (insn);
4668
4669#ifdef HAVE_cc0
4670 /* FIXME: 'twould be nice to call prev_cc0_setter here but it aborts
4671 if cc0 isn't set. */
4672 note = find_reg_note (insn, REG_CC_SETTER, NULL_RTX);
4673 if (note)
4674 insn = XEXP (note, 0);
4675 else
4676 {
4677 rtx maybe_cc0_setter = prev_nonnote_insn (insn);
4678 if (maybe_cc0_setter
2c3c49de 4679 && INSN_P (maybe_cc0_setter)
7506f491
DE
4680 && sets_cc0_p (PATTERN (maybe_cc0_setter)))
4681 insn = maybe_cc0_setter;
4682 }
4683#endif
4684 /* FIXME: What if something in cc0/jump uses value set in new insn? */
3c030e88 4685 new_insn = emit_insn_before (pat, insn);
3947e2f9 4686 }
c4c81601 4687
3947e2f9
RH
4688 /* Likewise if the last insn is a call, as will happen in the presence
4689 of exception handling. */
068473ec
JH
4690 else if (GET_CODE (insn) == CALL_INSN
4691 && (bb->succ->succ_next || (bb->succ->flags & EDGE_ABNORMAL)))
3947e2f9 4692 {
3947e2f9
RH
4693 /* Keeping in mind SMALL_REGISTER_CLASSES and parameters in registers,
4694 we search backward and place the instructions before the first
4695 parameter is loaded. Do this for everyone for consistency and a
c4c81601 4696 presumtion that we'll get better code elsewhere as well.
3947e2f9 4697
c4c81601 4698 It should always be the case that we can put these instructions
a65f3558
JL
4699 anywhere in the basic block with performing PRE optimizations.
4700 Check this. */
c4c81601 4701
a65f3558 4702 if (pre
0b17ab2f
RH
4703 && !TEST_BIT (antloc[bb->index], expr->bitmap_index)
4704 && !TEST_BIT (transp[bb->index], expr->bitmap_index))
3947e2f9
RH
4705 abort ();
4706
4707 /* Since different machines initialize their parameter registers
4708 in different orders, assume nothing. Collect the set of all
4709 parameter registers. */
833366d6 4710 insn = find_first_parameter_load (insn, bb->head);
3947e2f9 4711
b1d26727
JL
4712 /* If we found all the parameter loads, then we want to insert
4713 before the first parameter load.
4714
4715 If we did not find all the parameter loads, then we might have
4716 stopped on the head of the block, which could be a CODE_LABEL.
4717 If we inserted before the CODE_LABEL, then we would be putting
4718 the insn in the wrong basic block. In that case, put the insn
b5229628 4719 after the CODE_LABEL. Also, respect NOTE_INSN_BASIC_BLOCK. */
0a377997 4720 while (GET_CODE (insn) == CODE_LABEL
589ca5cb 4721 || NOTE_INSN_BASIC_BLOCK_P (insn))
b5229628 4722 insn = NEXT_INSN (insn);
c4c81601 4723
3c030e88 4724 new_insn = emit_insn_before (pat, insn);
7506f491
DE
4725 }
4726 else
3c030e88 4727 new_insn = emit_insn_after (pat, insn);
7506f491 4728
a65f3558
JL
4729 /* Keep block number table up to date.
4730 Note, PAT could be a multiple insn sequence, we have to make
4731 sure that each insn in the sequence is handled. */
4732 if (GET_CODE (pat) == SEQUENCE)
4733 {
a65f3558
JL
4734 for (i = 0; i < XVECLEN (pat, 0); i++)
4735 {
4736 rtx insn = XVECEXP (pat, 0, i);
2c3c49de 4737 if (INSN_P (insn))
a65f3558 4738 add_label_notes (PATTERN (insn), new_insn);
c4c81601 4739
84832317 4740 note_stores (PATTERN (insn), record_set_info, insn);
a65f3558
JL
4741 }
4742 }
4743 else
4744 {
157bd2bb 4745 add_label_notes (pat, new_insn);
c4c81601 4746
a65f3558
JL
4747 /* Keep register set table up to date. */
4748 record_one_set (regno, new_insn);
4749 }
3947e2f9 4750
7506f491
DE
4751 gcse_create_count++;
4752
4753 if (gcse_file)
4754 {
c4c81601 4755 fprintf (gcse_file, "PRE/HOIST: end of bb %d, insn %d, ",
0b17ab2f 4756 bb->index, INSN_UID (new_insn));
c4c81601
RK
4757 fprintf (gcse_file, "copying expression %d to reg %d\n",
4758 expr->bitmap_index, regno);
7506f491
DE
4759 }
4760}
4761
a42cd965
AM
4762/* Insert partially redundant expressions on edges in the CFG to make
4763 the expressions fully redundant. */
7506f491 4764
a42cd965
AM
4765static int
4766pre_edge_insert (edge_list, index_map)
4767 struct edge_list *edge_list;
7506f491
DE
4768 struct expr **index_map;
4769{
c4c81601 4770 int e, i, j, num_edges, set_size, did_insert = 0;
a65f3558
JL
4771 sbitmap *inserted;
4772
a42cd965
AM
4773 /* Where PRE_INSERT_MAP is nonzero, we add the expression on that edge
4774 if it reaches any of the deleted expressions. */
7506f491 4775
a42cd965
AM
4776 set_size = pre_insert_map[0]->size;
4777 num_edges = NUM_EDGES (edge_list);
4778 inserted = sbitmap_vector_alloc (num_edges, n_exprs);
4779 sbitmap_vector_zero (inserted, num_edges);
7506f491 4780
a42cd965 4781 for (e = 0; e < num_edges; e++)
7506f491
DE
4782 {
4783 int indx;
e2d2ed72 4784 basic_block bb = INDEX_EDGE_PRED_BB (edge_list, e);
a65f3558 4785
a65f3558 4786 for (i = indx = 0; i < set_size; i++, indx += SBITMAP_ELT_BITS)
7506f491 4787 {
a42cd965 4788 SBITMAP_ELT_TYPE insert = pre_insert_map[e]->elms[i];
7506f491 4789
a65f3558 4790 for (j = indx; insert && j < n_exprs; j++, insert >>= 1)
c4c81601
RK
4791 if ((insert & 1) != 0 && index_map[j]->reaching_reg != NULL_RTX)
4792 {
4793 struct expr *expr = index_map[j];
4794 struct occr *occr;
a65f3558 4795
ff7cc307 4796 /* Now look at each deleted occurrence of this expression. */
c4c81601
RK
4797 for (occr = expr->antic_occr; occr != NULL; occr = occr->next)
4798 {
4799 if (! occr->deleted_p)
4800 continue;
4801
4802 /* Insert this expression on this edge if if it would
ff7cc307 4803 reach the deleted occurrence in BB. */
c4c81601
RK
4804 if (!TEST_BIT (inserted[e], j))
4805 {
4806 rtx insn;
4807 edge eg = INDEX_EDGE (edge_list, e);
4808
4809 /* We can't insert anything on an abnormal and
4810 critical edge, so we insert the insn at the end of
4811 the previous block. There are several alternatives
4812 detailed in Morgans book P277 (sec 10.5) for
4813 handling this situation. This one is easiest for
4814 now. */
4815
4816 if ((eg->flags & EDGE_ABNORMAL) == EDGE_ABNORMAL)
4817 insert_insn_end_bb (index_map[j], bb, 0);
4818 else
4819 {
4820 insn = process_insert_insn (index_map[j]);
4821 insert_insn_on_edge (insn, eg);
4822 }
4823
4824 if (gcse_file)
4825 {
4826 fprintf (gcse_file, "PRE/HOIST: edge (%d,%d), ",
0b17ab2f
RH
4827 bb->index,
4828 INDEX_EDGE_SUCC_BB (edge_list, e)->index);
c4c81601
RK
4829 fprintf (gcse_file, "copy expression %d\n",
4830 expr->bitmap_index);
4831 }
4832
a13d4ebf 4833 update_ld_motion_stores (expr);
c4c81601
RK
4834 SET_BIT (inserted[e], j);
4835 did_insert = 1;
4836 gcse_create_count++;
4837 }
4838 }
4839 }
7506f491
DE
4840 }
4841 }
5faf03ae 4842
5a660bff 4843 sbitmap_vector_free (inserted);
a42cd965 4844 return did_insert;
7506f491
DE
4845}
4846
c4c81601 4847/* Copy the result of INSN to REG. INDX is the expression number. */
7506f491
DE
4848
4849static void
4850pre_insert_copy_insn (expr, insn)
4851 struct expr *expr;
4852 rtx insn;
4853{
4854 rtx reg = expr->reaching_reg;
4855 int regno = REGNO (reg);
4856 int indx = expr->bitmap_index;
4857 rtx set = single_set (insn);
4858 rtx new_insn;
4859
4860 if (!set)
4861 abort ();
c4c81601 4862
cccf0ae8 4863 new_insn = emit_insn_after (gen_move_insn (reg, SET_DEST (set)), insn);
c4c81601 4864
7506f491
DE
4865 /* Keep register set table up to date. */
4866 record_one_set (regno, new_insn);
4867
4868 gcse_create_count++;
4869
4870 if (gcse_file)
a42cd965
AM
4871 fprintf (gcse_file,
4872 "PRE: bb %d, insn %d, copy expression %d in insn %d to reg %d\n",
4873 BLOCK_NUM (insn), INSN_UID (new_insn), indx,
4874 INSN_UID (insn), regno);
222f7ba9 4875 update_ld_motion_stores (expr);
7506f491
DE
4876}
4877
4878/* Copy available expressions that reach the redundant expression
4879 to `reaching_reg'. */
4880
4881static void
4882pre_insert_copies ()
4883{
2e653e39 4884 unsigned int i;
c4c81601
RK
4885 struct expr *expr;
4886 struct occr *occr;
4887 struct occr *avail;
a65f3558 4888
7506f491
DE
4889 /* For each available expression in the table, copy the result to
4890 `reaching_reg' if the expression reaches a deleted one.
4891
4892 ??? The current algorithm is rather brute force.
4893 Need to do some profiling. */
4894
4895 for (i = 0; i < expr_hash_table_size; i++)
c4c81601
RK
4896 for (expr = expr_hash_table[i]; expr != NULL; expr = expr->next_same_hash)
4897 {
4898 /* If the basic block isn't reachable, PPOUT will be TRUE. However,
4899 we don't want to insert a copy here because the expression may not
4900 really be redundant. So only insert an insn if the expression was
4901 deleted. This test also avoids further processing if the
4902 expression wasn't deleted anywhere. */
4903 if (expr->reaching_reg == NULL)
4904 continue;
4905
4906 for (occr = expr->antic_occr; occr != NULL; occr = occr->next)
4907 {
4908 if (! occr->deleted_p)
4909 continue;
7506f491 4910
c4c81601
RK
4911 for (avail = expr->avail_occr; avail != NULL; avail = avail->next)
4912 {
4913 rtx insn = avail->insn;
7506f491 4914
c4c81601
RK
4915 /* No need to handle this one if handled already. */
4916 if (avail->copied_p)
4917 continue;
7506f491 4918
c4c81601
RK
4919 /* Don't handle this one if it's a redundant one. */
4920 if (TEST_BIT (pre_redundant_insns, INSN_CUID (insn)))
4921 continue;
7506f491 4922
c4c81601 4923 /* Or if the expression doesn't reach the deleted one. */
e2d2ed72
AM
4924 if (! pre_expr_reaches_here_p (BLOCK_FOR_INSN (avail->insn),
4925 expr,
4926 BLOCK_FOR_INSN (occr->insn)))
c4c81601 4927 continue;
7506f491 4928
c4c81601
RK
4929 /* Copy the result of avail to reaching_reg. */
4930 pre_insert_copy_insn (expr, insn);
4931 avail->copied_p = 1;
4932 }
4933 }
4934 }
7506f491
DE
4935}
4936
4937/* Delete redundant computations.
7506f491
DE
4938 Deletion is done by changing the insn to copy the `reaching_reg' of
4939 the expression into the result of the SET. It is left to later passes
4940 (cprop, cse2, flow, combine, regmove) to propagate the copy or eliminate it.
4941
4942 Returns non-zero if a change is made. */
4943
4944static int
4945pre_delete ()
4946{
2e653e39 4947 unsigned int i;
63bc1d05 4948 int changed;
c4c81601
RK
4949 struct expr *expr;
4950 struct occr *occr;
a65f3558 4951
7506f491
DE
4952 changed = 0;
4953 for (i = 0; i < expr_hash_table_size; i++)
c4c81601
RK
4954 for (expr = expr_hash_table[i]; expr != NULL; expr = expr->next_same_hash)
4955 {
4956 int indx = expr->bitmap_index;
7506f491 4957
c4c81601
RK
4958 /* We only need to search antic_occr since we require
4959 ANTLOC != 0. */
7506f491 4960
c4c81601
RK
4961 for (occr = expr->antic_occr; occr != NULL; occr = occr->next)
4962 {
4963 rtx insn = occr->insn;
4964 rtx set;
e2d2ed72 4965 basic_block bb = BLOCK_FOR_INSN (insn);
7506f491 4966
0b17ab2f 4967 if (TEST_BIT (pre_delete_map[bb->index], indx))
c4c81601
RK
4968 {
4969 set = single_set (insn);
4970 if (! set)
4971 abort ();
4972
4973 /* Create a pseudo-reg to store the result of reaching
4974 expressions into. Get the mode for the new pseudo from
4975 the mode of the original destination pseudo. */
4976 if (expr->reaching_reg == NULL)
4977 expr->reaching_reg
4978 = gen_reg_rtx (GET_MODE (SET_DEST (set)));
4979
4980 /* In theory this should never fail since we're creating
4981 a reg->reg copy.
4982
4983 However, on the x86 some of the movXX patterns actually
4984 contain clobbers of scratch regs. This may cause the
4985 insn created by validate_change to not match any pattern
6d2f8887 4986 and thus cause validate_change to fail. */
c4c81601
RK
4987 if (validate_change (insn, &SET_SRC (set),
4988 expr->reaching_reg, 0))
4989 {
4990 occr->deleted_p = 1;
4991 SET_BIT (pre_redundant_insns, INSN_CUID (insn));
4992 changed = 1;
4993 gcse_subst_count++;
4994 }
7506f491 4995
c4c81601
RK
4996 if (gcse_file)
4997 {
4998 fprintf (gcse_file,
4999 "PRE: redundant insn %d (expression %d) in ",
5000 INSN_UID (insn), indx);
5001 fprintf (gcse_file, "bb %d, reaching reg is %d\n",
0b17ab2f 5002 bb->index, REGNO (expr->reaching_reg));
c4c81601
RK
5003 }
5004 }
5005 }
5006 }
7506f491
DE
5007
5008 return changed;
5009}
5010
5011/* Perform GCSE optimizations using PRE.
5012 This is called by one_pre_gcse_pass after all the dataflow analysis
5013 has been done.
5014
c4c81601
RK
5015 This is based on the original Morel-Renvoise paper Fred Chow's thesis, and
5016 lazy code motion from Knoop, Ruthing and Steffen as described in Advanced
5017 Compiler Design and Implementation.
7506f491 5018
c4c81601
RK
5019 ??? A new pseudo reg is created to hold the reaching expression. The nice
5020 thing about the classical approach is that it would try to use an existing
5021 reg. If the register can't be adequately optimized [i.e. we introduce
5022 reload problems], one could add a pass here to propagate the new register
5023 through the block.
7506f491 5024
c4c81601
RK
5025 ??? We don't handle single sets in PARALLELs because we're [currently] not
5026 able to copy the rest of the parallel when we insert copies to create full
5027 redundancies from partial redundancies. However, there's no reason why we
5028 can't handle PARALLELs in the cases where there are no partial
7506f491
DE
5029 redundancies. */
5030
5031static int
5032pre_gcse ()
5033{
2e653e39
RK
5034 unsigned int i;
5035 int did_insert, changed;
7506f491 5036 struct expr **index_map;
c4c81601 5037 struct expr *expr;
7506f491
DE
5038
5039 /* Compute a mapping from expression number (`bitmap_index') to
5040 hash table entry. */
5041
dd1bd863 5042 index_map = (struct expr **) xcalloc (n_exprs, sizeof (struct expr *));
7506f491 5043 for (i = 0; i < expr_hash_table_size; i++)
c4c81601
RK
5044 for (expr = expr_hash_table[i]; expr != NULL; expr = expr->next_same_hash)
5045 index_map[expr->bitmap_index] = expr;
7506f491
DE
5046
5047 /* Reset bitmap used to track which insns are redundant. */
a65f3558
JL
5048 pre_redundant_insns = sbitmap_alloc (max_cuid);
5049 sbitmap_zero (pre_redundant_insns);
7506f491
DE
5050
5051 /* Delete the redundant insns first so that
5052 - we know what register to use for the new insns and for the other
5053 ones with reaching expressions
5054 - we know which insns are redundant when we go to create copies */
c4c81601 5055
7506f491
DE
5056 changed = pre_delete ();
5057
a42cd965 5058 did_insert = pre_edge_insert (edge_list, index_map);
c4c81601 5059
7506f491 5060 /* In other places with reaching expressions, copy the expression to the
a42cd965 5061 specially allocated pseudo-reg that reaches the redundant expr. */
7506f491 5062 pre_insert_copies ();
a42cd965
AM
5063 if (did_insert)
5064 {
5065 commit_edge_insertions ();
5066 changed = 1;
5067 }
7506f491 5068
283a2545 5069 free (index_map);
76ac938b 5070 sbitmap_free (pre_redundant_insns);
7506f491
DE
5071 return changed;
5072}
5073
5074/* Top level routine to perform one PRE GCSE pass.
5075
5076 Return non-zero if a change was made. */
5077
5078static int
b5ce41ff 5079one_pre_gcse_pass (pass)
7506f491
DE
5080 int pass;
5081{
5082 int changed = 0;
5083
5084 gcse_subst_count = 0;
5085 gcse_create_count = 0;
5086
5087 alloc_expr_hash_table (max_cuid);
a42cd965 5088 add_noreturn_fake_exit_edges ();
a13d4ebf
AM
5089 if (flag_gcse_lm)
5090 compute_ld_motion_mems ();
5091
b5ce41ff 5092 compute_expr_hash_table ();
a13d4ebf 5093 trim_ld_motion_mems ();
7506f491
DE
5094 if (gcse_file)
5095 dump_hash_table (gcse_file, "Expression", expr_hash_table,
5096 expr_hash_table_size, n_exprs);
c4c81601 5097
7506f491
DE
5098 if (n_exprs > 0)
5099 {
0b17ab2f 5100 alloc_pre_mem (n_basic_blocks, n_exprs);
7506f491
DE
5101 compute_pre_data ();
5102 changed |= pre_gcse ();
a42cd965 5103 free_edge_list (edge_list);
7506f491
DE
5104 free_pre_mem ();
5105 }
c4c81601 5106
a13d4ebf 5107 free_ldst_mems ();
a42cd965 5108 remove_fake_edges ();
7506f491
DE
5109 free_expr_hash_table ();
5110
5111 if (gcse_file)
5112 {
c4c81601
RK
5113 fprintf (gcse_file, "\nPRE GCSE of %s, pass %d: %d bytes needed, ",
5114 current_function_name, pass, bytes_used);
5115 fprintf (gcse_file, "%d substs, %d insns created\n",
5116 gcse_subst_count, gcse_create_count);
7506f491
DE
5117 }
5118
5119 return changed;
5120}
aeb2f500
JW
5121\f
5122/* If X contains any LABEL_REF's, add REG_LABEL notes for them to INSN.
5b1ef594
JDA
5123 If notes are added to an insn which references a CODE_LABEL, the
5124 LABEL_NUSES count is incremented. We have to add REG_LABEL notes,
5125 because the following loop optimization pass requires them. */
aeb2f500
JW
5126
5127/* ??? This is very similar to the loop.c add_label_notes function. We
5128 could probably share code here. */
5129
5130/* ??? If there was a jump optimization pass after gcse and before loop,
5131 then we would not need to do this here, because jump would add the
5132 necessary REG_LABEL notes. */
5133
5134static void
5135add_label_notes (x, insn)
5136 rtx x;
5137 rtx insn;
5138{
5139 enum rtx_code code = GET_CODE (x);
5140 int i, j;
6f7d635c 5141 const char *fmt;
aeb2f500
JW
5142
5143 if (code == LABEL_REF && !LABEL_REF_NONLOCAL_P (x))
5144 {
6b3603c2 5145 /* This code used to ignore labels that referred to dispatch tables to
ac7c5af5 5146 avoid flow generating (slighly) worse code.
6b3603c2 5147
ac7c5af5
JL
5148 We no longer ignore such label references (see LABEL_REF handling in
5149 mark_jump_label for additional information). */
c4c81601 5150
6b8c9327 5151 REG_NOTES (insn) = gen_rtx_INSN_LIST (REG_LABEL, XEXP (x, 0),
6b3603c2 5152 REG_NOTES (insn));
5b1ef594
JDA
5153 if (LABEL_P (XEXP (x, 0)))
5154 LABEL_NUSES (XEXP (x, 0))++;
aeb2f500
JW
5155 return;
5156 }
5157
c4c81601 5158 for (i = GET_RTX_LENGTH (code) - 1, fmt = GET_RTX_FORMAT (code); i >= 0; i--)
aeb2f500
JW
5159 {
5160 if (fmt[i] == 'e')
5161 add_label_notes (XEXP (x, i), insn);
5162 else if (fmt[i] == 'E')
5163 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
5164 add_label_notes (XVECEXP (x, i, j), insn);
5165 }
5166}
a65f3558
JL
5167
5168/* Compute transparent outgoing information for each block.
5169
5170 An expression is transparent to an edge unless it is killed by
5171 the edge itself. This can only happen with abnormal control flow,
5172 when the edge is traversed through a call. This happens with
5173 non-local labels and exceptions.
5174
5175 This would not be necessary if we split the edge. While this is
5176 normally impossible for abnormal critical edges, with some effort
5177 it should be possible with exception handling, since we still have
5178 control over which handler should be invoked. But due to increased
5179 EH table sizes, this may not be worthwhile. */
5180
5181static void
5182compute_transpout ()
5183{
0b17ab2f 5184 int bb;
2e653e39 5185 unsigned int i;
c4c81601 5186 struct expr *expr;
a65f3558 5187
0b17ab2f 5188 sbitmap_vector_ones (transpout, n_basic_blocks);
a65f3558 5189
0b17ab2f 5190 for (bb = 0; bb < n_basic_blocks; ++bb)
a65f3558 5191 {
a65f3558
JL
5192 /* Note that flow inserted a nop a the end of basic blocks that
5193 end in call instructions for reasons other than abnormal
5194 control flow. */
0b17ab2f 5195 if (GET_CODE (BLOCK_END (bb)) != CALL_INSN)
a65f3558
JL
5196 continue;
5197
5198 for (i = 0; i < expr_hash_table_size; i++)
c4c81601
RK
5199 for (expr = expr_hash_table[i]; expr ; expr = expr->next_same_hash)
5200 if (GET_CODE (expr->expr) == MEM)
5201 {
5202 if (GET_CODE (XEXP (expr->expr, 0)) == SYMBOL_REF
5203 && CONSTANT_POOL_ADDRESS_P (XEXP (expr->expr, 0)))
5204 continue;
a65f3558 5205
c4c81601
RK
5206 /* ??? Optimally, we would use interprocedural alias
5207 analysis to determine if this mem is actually killed
5208 by this call. */
0b17ab2f 5209 RESET_BIT (transpout[bb], expr->bitmap_index);
c4c81601 5210 }
a65f3558
JL
5211 }
5212}
dfdb644f
JL
5213
5214/* Removal of useless null pointer checks */
5215
dfdb644f 5216/* Called via note_stores. X is set by SETTER. If X is a register we must
0511851c
MM
5217 invalidate nonnull_local and set nonnull_killed. DATA is really a
5218 `null_pointer_info *'.
dfdb644f
JL
5219
5220 We ignore hard registers. */
c4c81601 5221
dfdb644f 5222static void
84832317 5223invalidate_nonnull_info (x, setter, data)
dfdb644f
JL
5224 rtx x;
5225 rtx setter ATTRIBUTE_UNUSED;
0511851c 5226 void *data;
dfdb644f 5227{
770ae6cc
RK
5228 unsigned int regno;
5229 struct null_pointer_info *npi = (struct null_pointer_info *) data;
c4c81601 5230
dfdb644f
JL
5231 while (GET_CODE (x) == SUBREG)
5232 x = SUBREG_REG (x);
5233
5234 /* Ignore anything that is not a register or is a hard register. */
5235 if (GET_CODE (x) != REG
0511851c
MM
5236 || REGNO (x) < npi->min_reg
5237 || REGNO (x) >= npi->max_reg)
dfdb644f
JL
5238 return;
5239
0511851c 5240 regno = REGNO (x) - npi->min_reg;
dfdb644f 5241
0b17ab2f
RH
5242 RESET_BIT (npi->nonnull_local[npi->current_block], regno);
5243 SET_BIT (npi->nonnull_killed[npi->current_block], regno);
dfdb644f
JL
5244}
5245
0511851c
MM
5246/* Do null-pointer check elimination for the registers indicated in
5247 NPI. NONNULL_AVIN and NONNULL_AVOUT are pre-allocated sbitmaps;
5248 they are not our responsibility to free. */
dfdb644f 5249
0511851c 5250static void
9cd56be1 5251delete_null_pointer_checks_1 (block_reg, nonnull_avin,
8e184d9c 5252 nonnull_avout, npi)
770ae6cc 5253 unsigned int *block_reg;
0511851c
MM
5254 sbitmap *nonnull_avin;
5255 sbitmap *nonnull_avout;
5256 struct null_pointer_info *npi;
dfdb644f 5257{
0b17ab2f
RH
5258 int bb;
5259 int current_block;
0511851c
MM
5260 sbitmap *nonnull_local = npi->nonnull_local;
5261 sbitmap *nonnull_killed = npi->nonnull_killed;
dfdb644f 5262
dfdb644f
JL
5263 /* Compute local properties, nonnull and killed. A register will have
5264 the nonnull property if at the end of the current block its value is
5265 known to be nonnull. The killed property indicates that somewhere in
5266 the block any information we had about the register is killed.
5267
5268 Note that a register can have both properties in a single block. That
5269 indicates that it's killed, then later in the block a new value is
5270 computed. */
0b17ab2f
RH
5271 sbitmap_vector_zero (nonnull_local, n_basic_blocks);
5272 sbitmap_vector_zero (nonnull_killed, n_basic_blocks);
c4c81601 5273
0b17ab2f 5274 for (current_block = 0; current_block < n_basic_blocks; current_block++)
dfdb644f
JL
5275 {
5276 rtx insn, stop_insn;
5277
0511851c
MM
5278 /* Set the current block for invalidate_nonnull_info. */
5279 npi->current_block = current_block;
5280
dfdb644f
JL
5281 /* Scan each insn in the basic block looking for memory references and
5282 register sets. */
0b17ab2f
RH
5283 stop_insn = NEXT_INSN (BLOCK_END (current_block));
5284 for (insn = BLOCK_HEAD (current_block);
dfdb644f
JL
5285 insn != stop_insn;
5286 insn = NEXT_INSN (insn))
5287 {
5288 rtx set;
0511851c 5289 rtx reg;
dfdb644f
JL
5290
5291 /* Ignore anything that is not a normal insn. */
2c3c49de 5292 if (! INSN_P (insn))
dfdb644f
JL
5293 continue;
5294
5295 /* Basically ignore anything that is not a simple SET. We do have
5296 to make sure to invalidate nonnull_local and set nonnull_killed
5297 for such insns though. */
5298 set = single_set (insn);
5299 if (!set)
5300 {
0511851c 5301 note_stores (PATTERN (insn), invalidate_nonnull_info, npi);
dfdb644f
JL
5302 continue;
5303 }
5304
f63d1bf7 5305 /* See if we've got a usable memory load. We handle it first
dfdb644f
JL
5306 in case it uses its address register as a dest (which kills
5307 the nonnull property). */
5308 if (GET_CODE (SET_SRC (set)) == MEM
0511851c
MM
5309 && GET_CODE ((reg = XEXP (SET_SRC (set), 0))) == REG
5310 && REGNO (reg) >= npi->min_reg
5311 && REGNO (reg) < npi->max_reg)
0b17ab2f 5312 SET_BIT (nonnull_local[current_block],
0511851c 5313 REGNO (reg) - npi->min_reg);
dfdb644f
JL
5314
5315 /* Now invalidate stuff clobbered by this insn. */
0511851c 5316 note_stores (PATTERN (insn), invalidate_nonnull_info, npi);
dfdb644f
JL
5317
5318 /* And handle stores, we do these last since any sets in INSN can
5319 not kill the nonnull property if it is derived from a MEM
5320 appearing in a SET_DEST. */
5321 if (GET_CODE (SET_DEST (set)) == MEM
0511851c
MM
5322 && GET_CODE ((reg = XEXP (SET_DEST (set), 0))) == REG
5323 && REGNO (reg) >= npi->min_reg
5324 && REGNO (reg) < npi->max_reg)
0b17ab2f 5325 SET_BIT (nonnull_local[current_block],
0511851c 5326 REGNO (reg) - npi->min_reg);
dfdb644f
JL
5327 }
5328 }
5329
5330 /* Now compute global properties based on the local properties. This
5331 is a classic global availablity algorithm. */
ce724250
JL
5332 compute_available (nonnull_local, nonnull_killed,
5333 nonnull_avout, nonnull_avin);
dfdb644f
JL
5334
5335 /* Now look at each bb and see if it ends with a compare of a value
5336 against zero. */
0b17ab2f 5337 for (bb = 0; bb < n_basic_blocks; bb++)
dfdb644f 5338 {
0b17ab2f 5339 rtx last_insn = BLOCK_END (bb);
0511851c 5340 rtx condition, earliest;
dfdb644f
JL
5341 int compare_and_branch;
5342
0511851c
MM
5343 /* Since MIN_REG is always at least FIRST_PSEUDO_REGISTER, and
5344 since BLOCK_REG[BB] is zero if this block did not end with a
5345 comparison against zero, this condition works. */
0b17ab2f
RH
5346 if (block_reg[bb] < npi->min_reg
5347 || block_reg[bb] >= npi->max_reg)
dfdb644f
JL
5348 continue;
5349
5350 /* LAST_INSN is a conditional jump. Get its condition. */
5351 condition = get_condition (last_insn, &earliest);
5352
40d7a3fe
NB
5353 /* If we can't determine the condition then skip. */
5354 if (! condition)
5355 continue;
5356
dfdb644f 5357 /* Is the register known to have a nonzero value? */
0b17ab2f 5358 if (!TEST_BIT (nonnull_avout[bb], block_reg[bb] - npi->min_reg))
dfdb644f
JL
5359 continue;
5360
5361 /* Try to compute whether the compare/branch at the loop end is one or
5362 two instructions. */
5363 if (earliest == last_insn)
5364 compare_and_branch = 1;
5365 else if (earliest == prev_nonnote_insn (last_insn))
5366 compare_and_branch = 2;
5367 else
5368 continue;
5369
5370 /* We know the register in this comparison is nonnull at exit from
5371 this block. We can optimize this comparison. */
5372 if (GET_CODE (condition) == NE)
5373 {
5374 rtx new_jump;
5375
38c1593d
JH
5376 new_jump = emit_jump_insn_after (gen_jump (JUMP_LABEL (last_insn)),
5377 last_insn);
dfdb644f
JL
5378 JUMP_LABEL (new_jump) = JUMP_LABEL (last_insn);
5379 LABEL_NUSES (JUMP_LABEL (new_jump))++;
5380 emit_barrier_after (new_jump);
5381 }
8e184d9c 5382
9cd56be1 5383 delete_insn (last_insn);
dfdb644f 5384 if (compare_and_branch == 2)
9cd56be1 5385 delete_insn (earliest);
0b17ab2f 5386 purge_dead_edges (BASIC_BLOCK (bb));
0511851c
MM
5387
5388 /* Don't check this block again. (Note that BLOCK_END is
5389 invalid here; we deleted the last instruction in the
5390 block.) */
0b17ab2f 5391 block_reg[bb] = 0;
0511851c
MM
5392 }
5393}
5394
5395/* Find EQ/NE comparisons against zero which can be (indirectly) evaluated
5396 at compile time.
5397
5398 This is conceptually similar to global constant/copy propagation and
5399 classic global CSE (it even uses the same dataflow equations as cprop).
5400
5401 If a register is used as memory address with the form (mem (reg)), then we
5402 know that REG can not be zero at that point in the program. Any instruction
5403 which sets REG "kills" this property.
5404
5405 So, if every path leading to a conditional branch has an available memory
5406 reference of that form, then we know the register can not have the value
5407 zero at the conditional branch.
5408
5409 So we merely need to compute the local properies and propagate that data
5410 around the cfg, then optimize where possible.
5411
5412 We run this pass two times. Once before CSE, then again after CSE. This
5413 has proven to be the most profitable approach. It is rare for new
5414 optimization opportunities of this nature to appear after the first CSE
5415 pass.
5416
5417 This could probably be integrated with global cprop with a little work. */
5418
5419void
5420delete_null_pointer_checks (f)
2e653e39 5421 rtx f ATTRIBUTE_UNUSED;
0511851c 5422{
0511851c 5423 sbitmap *nonnull_avin, *nonnull_avout;
770ae6cc 5424 unsigned int *block_reg;
0b17ab2f 5425 int bb;
0511851c
MM
5426 int reg;
5427 int regs_per_pass;
5428 int max_reg;
5429 struct null_pointer_info npi;
5430
0511851c 5431 /* If we have only a single block, then there's nothing to do. */
0b17ab2f 5432 if (n_basic_blocks <= 1)
a18820c6 5433 return;
0511851c
MM
5434
5435 /* Trying to perform global optimizations on flow graphs which have
5436 a high connectivity will take a long time and is unlikely to be
5437 particularly useful.
5438
43e72072 5439 In normal circumstances a cfg should have about twice as many edges
0511851c
MM
5440 as blocks. But we do not want to punish small functions which have
5441 a couple switch statements. So we require a relatively large number
5442 of basic blocks and the ratio of edges to blocks to be high. */
0b17ab2f 5443 if (n_basic_blocks > 1000 && n_edges / n_basic_blocks >= 20)
a18820c6 5444 return;
0511851c 5445
0511851c
MM
5446 /* We need four bitmaps, each with a bit for each register in each
5447 basic block. */
5448 max_reg = max_reg_num ();
0b17ab2f 5449 regs_per_pass = get_bitmap_width (4, n_basic_blocks, max_reg);
0511851c
MM
5450
5451 /* Allocate bitmaps to hold local and global properties. */
0b17ab2f
RH
5452 npi.nonnull_local = sbitmap_vector_alloc (n_basic_blocks, regs_per_pass);
5453 npi.nonnull_killed = sbitmap_vector_alloc (n_basic_blocks, regs_per_pass);
5454 nonnull_avin = sbitmap_vector_alloc (n_basic_blocks, regs_per_pass);
5455 nonnull_avout = sbitmap_vector_alloc (n_basic_blocks, regs_per_pass);
0511851c
MM
5456
5457 /* Go through the basic blocks, seeing whether or not each block
5458 ends with a conditional branch whose condition is a comparison
5459 against zero. Record the register compared in BLOCK_REG. */
0b17ab2f
RH
5460 block_reg = (unsigned int *) xcalloc (n_basic_blocks, sizeof (int));
5461 for (bb = 0; bb < n_basic_blocks; bb++)
0511851c 5462 {
0b17ab2f 5463 rtx last_insn = BLOCK_END (bb);
0511851c
MM
5464 rtx condition, earliest, reg;
5465
5466 /* We only want conditional branches. */
5467 if (GET_CODE (last_insn) != JUMP_INSN
7f1c097d
JH
5468 || !any_condjump_p (last_insn)
5469 || !onlyjump_p (last_insn))
0511851c
MM
5470 continue;
5471
5472 /* LAST_INSN is a conditional jump. Get its condition. */
5473 condition = get_condition (last_insn, &earliest);
5474
4fe9b91c 5475 /* If we were unable to get the condition, or it is not an equality
0511851c
MM
5476 comparison against zero then there's nothing we can do. */
5477 if (!condition
5478 || (GET_CODE (condition) != NE && GET_CODE (condition) != EQ)
5479 || GET_CODE (XEXP (condition, 1)) != CONST_INT
5480 || (XEXP (condition, 1)
5481 != CONST0_RTX (GET_MODE (XEXP (condition, 0)))))
5482 continue;
5483
5484 /* We must be checking a register against zero. */
5485 reg = XEXP (condition, 0);
5486 if (GET_CODE (reg) != REG)
5487 continue;
5488
0b17ab2f 5489 block_reg[bb] = REGNO (reg);
0511851c
MM
5490 }
5491
5492 /* Go through the algorithm for each block of registers. */
5493 for (reg = FIRST_PSEUDO_REGISTER; reg < max_reg; reg += regs_per_pass)
5494 {
5495 npi.min_reg = reg;
5496 npi.max_reg = MIN (reg + regs_per_pass, max_reg);
9cd56be1 5497 delete_null_pointer_checks_1 (block_reg, nonnull_avin,
0511851c 5498 nonnull_avout, &npi);
dfdb644f
JL
5499 }
5500
0511851c
MM
5501 /* Free the table of registers compared at the end of every block. */
5502 free (block_reg);
5503
dfdb644f 5504 /* Free bitmaps. */
5a660bff
DB
5505 sbitmap_vector_free (npi.nonnull_local);
5506 sbitmap_vector_free (npi.nonnull_killed);
5507 sbitmap_vector_free (nonnull_avin);
5508 sbitmap_vector_free (nonnull_avout);
dfdb644f 5509}
bb457bd9
JL
5510
5511/* Code Hoisting variables and subroutines. */
5512
5513/* Very busy expressions. */
5514static sbitmap *hoist_vbein;
5515static sbitmap *hoist_vbeout;
5516
5517/* Hoistable expressions. */
5518static sbitmap *hoist_exprs;
5519
5520/* Dominator bitmaps. */
5521static sbitmap *dominators;
bb457bd9
JL
5522
5523/* ??? We could compute post dominators and run this algorithm in
5524 reverse to to perform tail merging, doing so would probably be
5525 more effective than the tail merging code in jump.c.
5526
5527 It's unclear if tail merging could be run in parallel with
5528 code hoisting. It would be nice. */
5529
5530/* Allocate vars used for code hoisting analysis. */
5531
5532static void
5533alloc_code_hoist_mem (n_blocks, n_exprs)
5534 int n_blocks, n_exprs;
5535{
5536 antloc = sbitmap_vector_alloc (n_blocks, n_exprs);
5537 transp = sbitmap_vector_alloc (n_blocks, n_exprs);
5538 comp = sbitmap_vector_alloc (n_blocks, n_exprs);
5539
5540 hoist_vbein = sbitmap_vector_alloc (n_blocks, n_exprs);
5541 hoist_vbeout = sbitmap_vector_alloc (n_blocks, n_exprs);
5542 hoist_exprs = sbitmap_vector_alloc (n_blocks, n_exprs);
5543 transpout = sbitmap_vector_alloc (n_blocks, n_exprs);
5544
5545 dominators = sbitmap_vector_alloc (n_blocks, n_blocks);
bb457bd9
JL
5546}
5547
5548/* Free vars used for code hoisting analysis. */
5549
5550static void
5551free_code_hoist_mem ()
5552{
5a660bff
DB
5553 sbitmap_vector_free (antloc);
5554 sbitmap_vector_free (transp);
5555 sbitmap_vector_free (comp);
bb457bd9 5556
5a660bff
DB
5557 sbitmap_vector_free (hoist_vbein);
5558 sbitmap_vector_free (hoist_vbeout);
5559 sbitmap_vector_free (hoist_exprs);
5560 sbitmap_vector_free (transpout);
bb457bd9 5561
5a660bff 5562 sbitmap_vector_free (dominators);
bb457bd9
JL
5563}
5564
5565/* Compute the very busy expressions at entry/exit from each block.
5566
5567 An expression is very busy if all paths from a given point
5568 compute the expression. */
5569
5570static void
5571compute_code_hoist_vbeinout ()
5572{
0b17ab2f 5573 int bb, changed, passes;
bb457bd9 5574
0b17ab2f
RH
5575 sbitmap_vector_zero (hoist_vbeout, n_basic_blocks);
5576 sbitmap_vector_zero (hoist_vbein, n_basic_blocks);
bb457bd9
JL
5577
5578 passes = 0;
5579 changed = 1;
c4c81601 5580
bb457bd9
JL
5581 while (changed)
5582 {
5583 changed = 0;
c4c81601 5584
bb457bd9
JL
5585 /* We scan the blocks in the reverse order to speed up
5586 the convergence. */
0b17ab2f 5587 for (bb = n_basic_blocks - 1; bb >= 0; bb--)
bb457bd9 5588 {
0b17ab2f
RH
5589 changed |= sbitmap_a_or_b_and_c_cg (hoist_vbein[bb], antloc[bb],
5590 hoist_vbeout[bb], transp[bb]);
f6366fc7 5591 if (BASIC_BLOCK (bb)->next_bb != EXIT_BLOCK_PTR)
0b17ab2f 5592 sbitmap_intersection_of_succs (hoist_vbeout[bb], hoist_vbein, bb);
bb457bd9 5593 }
c4c81601 5594
bb457bd9
JL
5595 passes++;
5596 }
5597
5598 if (gcse_file)
5599 fprintf (gcse_file, "hoisting vbeinout computation: %d passes\n", passes);
5600}
5601
5602/* Top level routine to do the dataflow analysis needed by code hoisting. */
5603
5604static void
5605compute_code_hoist_data ()
5606{
5607 compute_local_properties (transp, comp, antloc, 0);
5608 compute_transpout ();
5609 compute_code_hoist_vbeinout ();
f8032688 5610 calculate_dominance_info (NULL, dominators, CDI_DOMINATORS);
bb457bd9
JL
5611 if (gcse_file)
5612 fprintf (gcse_file, "\n");
5613}
5614
5615/* Determine if the expression identified by EXPR_INDEX would
5616 reach BB unimpared if it was placed at the end of EXPR_BB.
5617
5618 It's unclear exactly what Muchnick meant by "unimpared". It seems
5619 to me that the expression must either be computed or transparent in
5620 *every* block in the path(s) from EXPR_BB to BB. Any other definition
5621 would allow the expression to be hoisted out of loops, even if
5622 the expression wasn't a loop invariant.
5623
5624 Contrast this to reachability for PRE where an expression is
5625 considered reachable if *any* path reaches instead of *all*
5626 paths. */
5627
5628static int
5629hoist_expr_reaches_here_p (expr_bb, expr_index, bb, visited)
e2d2ed72 5630 basic_block expr_bb;
bb457bd9 5631 int expr_index;
e2d2ed72 5632 basic_block bb;
bb457bd9
JL
5633 char *visited;
5634{
5635 edge pred;
283a2545
RL
5636 int visited_allocated_locally = 0;
5637
bb457bd9
JL
5638
5639 if (visited == NULL)
5640 {
8e42ace1 5641 visited_allocated_locally = 1;
0b17ab2f 5642 visited = xcalloc (n_basic_blocks, 1);
bb457bd9
JL
5643 }
5644
e2d2ed72 5645 for (pred = bb->pred; pred != NULL; pred = pred->pred_next)
bb457bd9 5646 {
e2d2ed72 5647 basic_block pred_bb = pred->src;
bb457bd9
JL
5648
5649 if (pred->src == ENTRY_BLOCK_PTR)
5650 break;
0b17ab2f 5651 else if (visited[pred_bb->index])
bb457bd9 5652 continue;
c4c81601 5653
bb457bd9 5654 /* Does this predecessor generate this expression? */
0b17ab2f 5655 else if (TEST_BIT (comp[pred_bb->index], expr_index))
bb457bd9 5656 break;
0b17ab2f 5657 else if (! TEST_BIT (transp[pred_bb->index], expr_index))
bb457bd9 5658 break;
c4c81601 5659
bb457bd9
JL
5660 /* Not killed. */
5661 else
5662 {
0b17ab2f 5663 visited[pred_bb->index] = 1;
bb457bd9
JL
5664 if (! hoist_expr_reaches_here_p (expr_bb, expr_index,
5665 pred_bb, visited))
5666 break;
5667 }
5668 }
283a2545
RL
5669 if (visited_allocated_locally)
5670 free (visited);
c4c81601 5671
bb457bd9
JL
5672 return (pred == NULL);
5673}
5674\f
5675/* Actually perform code hoisting. */
c4c81601 5676
bb457bd9
JL
5677static void
5678hoist_code ()
5679{
0b17ab2f 5680 int bb, dominated;
2e653e39 5681 unsigned int i;
bb457bd9 5682 struct expr **index_map;
c4c81601 5683 struct expr *expr;
bb457bd9 5684
0b17ab2f 5685 sbitmap_vector_zero (hoist_exprs, n_basic_blocks);
bb457bd9
JL
5686
5687 /* Compute a mapping from expression number (`bitmap_index') to
5688 hash table entry. */
5689
dd1bd863 5690 index_map = (struct expr **) xcalloc (n_exprs, sizeof (struct expr *));
bb457bd9 5691 for (i = 0; i < expr_hash_table_size; i++)
c4c81601
RK
5692 for (expr = expr_hash_table[i]; expr != NULL; expr = expr->next_same_hash)
5693 index_map[expr->bitmap_index] = expr;
bb457bd9
JL
5694
5695 /* Walk over each basic block looking for potentially hoistable
5696 expressions, nothing gets hoisted from the entry block. */
0b17ab2f 5697 for (bb = 0; bb < n_basic_blocks; bb++)
bb457bd9
JL
5698 {
5699 int found = 0;
5700 int insn_inserted_p;
5701
5702 /* Examine each expression that is very busy at the exit of this
5703 block. These are the potentially hoistable expressions. */
0b17ab2f 5704 for (i = 0; i < hoist_vbeout[bb]->n_bits; i++)
bb457bd9
JL
5705 {
5706 int hoistable = 0;
c4c81601 5707
0b17ab2f 5708 if (TEST_BIT (hoist_vbeout[bb], i) && TEST_BIT (transpout[bb], i))
bb457bd9
JL
5709 {
5710 /* We've found a potentially hoistable expression, now
5711 we look at every block BB dominates to see if it
5712 computes the expression. */
0b17ab2f 5713 for (dominated = 0; dominated < n_basic_blocks; dominated++)
bb457bd9
JL
5714 {
5715 /* Ignore self dominance. */
5716 if (bb == dominated
0b17ab2f 5717 || ! TEST_BIT (dominators[dominated], bb))
bb457bd9
JL
5718 continue;
5719
5720 /* We've found a dominated block, now see if it computes
5721 the busy expression and whether or not moving that
5722 expression to the "beginning" of that block is safe. */
0b17ab2f 5723 if (!TEST_BIT (antloc[dominated], i))
bb457bd9
JL
5724 continue;
5725
5726 /* Note if the expression would reach the dominated block
5727 unimpared if it was placed at the end of BB.
5728
5729 Keep track of how many times this expression is hoistable
5730 from a dominated block into BB. */
0b17ab2f
RH
5731 if (hoist_expr_reaches_here_p (BASIC_BLOCK (bb), i,
5732 BASIC_BLOCK (dominated), NULL))
bb457bd9
JL
5733 hoistable++;
5734 }
5735
ff7cc307 5736 /* If we found more than one hoistable occurrence of this
bb457bd9
JL
5737 expression, then note it in the bitmap of expressions to
5738 hoist. It makes no sense to hoist things which are computed
5739 in only one BB, and doing so tends to pessimize register
5740 allocation. One could increase this value to try harder
5741 to avoid any possible code expansion due to register
5742 allocation issues; however experiments have shown that
5743 the vast majority of hoistable expressions are only movable
5744 from two successors, so raising this threshhold is likely
5745 to nullify any benefit we get from code hoisting. */
5746 if (hoistable > 1)
5747 {
0b17ab2f 5748 SET_BIT (hoist_exprs[bb], i);
bb457bd9
JL
5749 found = 1;
5750 }
5751 }
5752 }
5753
5754 /* If we found nothing to hoist, then quit now. */
5755 if (! found)
5756 continue;
5757
5758 /* Loop over all the hoistable expressions. */
0b17ab2f 5759 for (i = 0; i < hoist_exprs[bb]->n_bits; i++)
bb457bd9
JL
5760 {
5761 /* We want to insert the expression into BB only once, so
5762 note when we've inserted it. */
5763 insn_inserted_p = 0;
5764
5765 /* These tests should be the same as the tests above. */
0b17ab2f 5766 if (TEST_BIT (hoist_vbeout[bb], i))
bb457bd9
JL
5767 {
5768 /* We've found a potentially hoistable expression, now
5769 we look at every block BB dominates to see if it
5770 computes the expression. */
0b17ab2f 5771 for (dominated = 0; dominated < n_basic_blocks; dominated++)
bb457bd9
JL
5772 {
5773 /* Ignore self dominance. */
5774 if (bb == dominated
0b17ab2f 5775 || ! TEST_BIT (dominators[dominated], bb))
bb457bd9
JL
5776 continue;
5777
5778 /* We've found a dominated block, now see if it computes
5779 the busy expression and whether or not moving that
5780 expression to the "beginning" of that block is safe. */
0b17ab2f 5781 if (!TEST_BIT (antloc[dominated], i))
bb457bd9
JL
5782 continue;
5783
5784 /* The expression is computed in the dominated block and
5785 it would be safe to compute it at the start of the
5786 dominated block. Now we have to determine if the
ff7cc307 5787 expression would reach the dominated block if it was
bb457bd9 5788 placed at the end of BB. */
0b17ab2f
RH
5789 if (hoist_expr_reaches_here_p (BASIC_BLOCK (bb), i,
5790 BASIC_BLOCK (dominated), NULL))
bb457bd9
JL
5791 {
5792 struct expr *expr = index_map[i];
5793 struct occr *occr = expr->antic_occr;
5794 rtx insn;
5795 rtx set;
5796
ff7cc307 5797 /* Find the right occurrence of this expression. */
0b17ab2f 5798 while (BLOCK_NUM (occr->insn) != dominated && occr)
bb457bd9
JL
5799 occr = occr->next;
5800
5801 /* Should never happen. */
5802 if (!occr)
5803 abort ();
5804
5805 insn = occr->insn;
5806
5807 set = single_set (insn);
5808 if (! set)
5809 abort ();
5810
5811 /* Create a pseudo-reg to store the result of reaching
5812 expressions into. Get the mode for the new pseudo
5813 from the mode of the original destination pseudo. */
5814 if (expr->reaching_reg == NULL)
5815 expr->reaching_reg
5816 = gen_reg_rtx (GET_MODE (SET_DEST (set)));
5817
5818 /* In theory this should never fail since we're creating
5819 a reg->reg copy.
5820
c4c81601
RK
5821 However, on the x86 some of the movXX patterns
5822 actually contain clobbers of scratch regs. This may
5823 cause the insn created by validate_change to not
5824 match any pattern and thus cause validate_change to
5825 fail. */
bb457bd9
JL
5826 if (validate_change (insn, &SET_SRC (set),
5827 expr->reaching_reg, 0))
5828 {
5829 occr->deleted_p = 1;
5830 if (!insn_inserted_p)
5831 {
0b17ab2f
RH
5832 insert_insn_end_bb (index_map[i],
5833 BASIC_BLOCK (bb), 0);
bb457bd9
JL
5834 insn_inserted_p = 1;
5835 }
5836 }
5837 }
5838 }
5839 }
5840 }
5841 }
c4c81601 5842
8e42ace1 5843 free (index_map);
bb457bd9
JL
5844}
5845
5846/* Top level routine to perform one code hoisting (aka unification) pass
5847
5848 Return non-zero if a change was made. */
5849
5850static int
5851one_code_hoisting_pass ()
5852{
5853 int changed = 0;
5854
5855 alloc_expr_hash_table (max_cuid);
5856 compute_expr_hash_table ();
5857 if (gcse_file)
5858 dump_hash_table (gcse_file, "Code Hosting Expressions", expr_hash_table,
5859 expr_hash_table_size, n_exprs);
c4c81601 5860
bb457bd9
JL
5861 if (n_exprs > 0)
5862 {
0b17ab2f 5863 alloc_code_hoist_mem (n_basic_blocks, n_exprs);
bb457bd9
JL
5864 compute_code_hoist_data ();
5865 hoist_code ();
5866 free_code_hoist_mem ();
5867 }
c4c81601 5868
bb457bd9
JL
5869 free_expr_hash_table ();
5870
5871 return changed;
5872}
a13d4ebf
AM
5873\f
5874/* Here we provide the things required to do store motion towards
5875 the exit. In order for this to be effective, gcse also needed to
5876 be taught how to move a load when it is kill only by a store to itself.
5877
5878 int i;
5879 float a[10];
5880
5881 void foo(float scale)
5882 {
5883 for (i=0; i<10; i++)
5884 a[i] *= scale;
5885 }
5886
5887 'i' is both loaded and stored to in the loop. Normally, gcse cannot move
5888 the load out since its live around the loop, and stored at the bottom
5889 of the loop.
5890
5891 The 'Load Motion' referred to and implemented in this file is
5892 an enhancement to gcse which when using edge based lcm, recognizes
5893 this situation and allows gcse to move the load out of the loop.
5894
5895 Once gcse has hoisted the load, store motion can then push this
5896 load towards the exit, and we end up with no loads or stores of 'i'
5897 in the loop. */
5898
ff7cc307 5899/* This will search the ldst list for a matching expression. If it
a13d4ebf
AM
5900 doesn't find one, we create one and initialize it. */
5901
5902static struct ls_expr *
5903ldst_entry (x)
5904 rtx x;
5905{
5906 struct ls_expr * ptr;
5907
5908 for (ptr = first_ls_expr(); ptr != NULL; ptr = next_ls_expr (ptr))
5909 if (expr_equiv_p (ptr->pattern, x))
5910 break;
5911
5912 if (!ptr)
5913 {
5914 ptr = (struct ls_expr *) xmalloc (sizeof (struct ls_expr));
5915
5916 ptr->next = pre_ldst_mems;
5917 ptr->expr = NULL;
5918 ptr->pattern = x;
5919 ptr->loads = NULL_RTX;
5920 ptr->stores = NULL_RTX;
5921 ptr->reaching_reg = NULL_RTX;
5922 ptr->invalid = 0;
5923 ptr->index = 0;
5924 ptr->hash_index = 0;
5925 pre_ldst_mems = ptr;
5926 }
5927
5928 return ptr;
5929}
5930
5931/* Free up an individual ldst entry. */
5932
5933static void
5934free_ldst_entry (ptr)
5935 struct ls_expr * ptr;
5936{
aaa4ca30
AJ
5937 free_INSN_LIST_list (& ptr->loads);
5938 free_INSN_LIST_list (& ptr->stores);
a13d4ebf
AM
5939
5940 free (ptr);
5941}
5942
5943/* Free up all memory associated with the ldst list. */
5944
5945static void
5946free_ldst_mems ()
5947{
5948 while (pre_ldst_mems)
5949 {
5950 struct ls_expr * tmp = pre_ldst_mems;
5951
5952 pre_ldst_mems = pre_ldst_mems->next;
5953
5954 free_ldst_entry (tmp);
5955 }
5956
5957 pre_ldst_mems = NULL;
5958}
5959
5960/* Dump debugging info about the ldst list. */
5961
5962static void
5963print_ldst_list (file)
5964 FILE * file;
5965{
5966 struct ls_expr * ptr;
5967
5968 fprintf (file, "LDST list: \n");
5969
5970 for (ptr = first_ls_expr(); ptr != NULL; ptr = next_ls_expr (ptr))
5971 {
5972 fprintf (file, " Pattern (%3d): ", ptr->index);
5973
5974 print_rtl (file, ptr->pattern);
5975
5976 fprintf (file, "\n Loads : ");
5977
5978 if (ptr->loads)
5979 print_rtl (file, ptr->loads);
5980 else
5981 fprintf (file, "(nil)");
5982
5983 fprintf (file, "\n Stores : ");
5984
5985 if (ptr->stores)
5986 print_rtl (file, ptr->stores);
5987 else
5988 fprintf (file, "(nil)");
5989
5990 fprintf (file, "\n\n");
5991 }
5992
5993 fprintf (file, "\n");
5994}
5995
5996/* Returns 1 if X is in the list of ldst only expressions. */
5997
5998static struct ls_expr *
5999find_rtx_in_ldst (x)
6000 rtx x;
6001{
6002 struct ls_expr * ptr;
6003
6004 for (ptr = pre_ldst_mems; ptr != NULL; ptr = ptr->next)
6005 if (expr_equiv_p (ptr->pattern, x) && ! ptr->invalid)
6006 return ptr;
6007
6008 return NULL;
6009}
6010
6011/* Assign each element of the list of mems a monotonically increasing value. */
6012
6013static int
6014enumerate_ldsts ()
6015{
6016 struct ls_expr * ptr;
6017 int n = 0;
6018
6019 for (ptr = pre_ldst_mems; ptr != NULL; ptr = ptr->next)
6020 ptr->index = n++;
6021
6022 return n;
6023}
6024
6025/* Return first item in the list. */
6026
6027static inline struct ls_expr *
6028first_ls_expr ()
6029{
6030 return pre_ldst_mems;
6031}
6032
6033/* Return the next item in ther list after the specified one. */
6034
6035static inline struct ls_expr *
6036next_ls_expr (ptr)
6037 struct ls_expr * ptr;
6038{
6039 return ptr->next;
6040}
6041\f
6042/* Load Motion for loads which only kill themselves. */
6043
6044/* Return true if x is a simple MEM operation, with no registers or
6045 side effects. These are the types of loads we consider for the
6046 ld_motion list, otherwise we let the usual aliasing take care of it. */
6047
6048static int
6049simple_mem (x)
6050 rtx x;
6051{
6052 if (GET_CODE (x) != MEM)
6053 return 0;
6054
6055 if (MEM_VOLATILE_P (x))
6056 return 0;
6057
6058 if (GET_MODE (x) == BLKmode)
6059 return 0;
aaa4ca30
AJ
6060
6061 if (!rtx_varies_p (XEXP (x, 0), 0))
a13d4ebf 6062 return 1;
aaa4ca30 6063
a13d4ebf
AM
6064 return 0;
6065}
6066
6067/* Make sure there isn't a buried reference in this pattern anywhere.
6068 If there is, invalidate the entry for it since we're not capable
6069 of fixing it up just yet.. We have to be sure we know about ALL
6070 loads since the aliasing code will allow all entries in the
6071 ld_motion list to not-alias itself. If we miss a load, we will get
6072 the wrong value since gcse might common it and we won't know to
6073 fix it up. */
6074
6075static void
6076invalidate_any_buried_refs (x)
6077 rtx x;
6078{
6079 const char * fmt;
8e42ace1 6080 int i, j;
a13d4ebf
AM
6081 struct ls_expr * ptr;
6082
6083 /* Invalidate it in the list. */
6084 if (GET_CODE (x) == MEM && simple_mem (x))
6085 {
6086 ptr = ldst_entry (x);
6087 ptr->invalid = 1;
6088 }
6089
6090 /* Recursively process the insn. */
6091 fmt = GET_RTX_FORMAT (GET_CODE (x));
6092
6093 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
6094 {
6095 if (fmt[i] == 'e')
6096 invalidate_any_buried_refs (XEXP (x, i));
6097 else if (fmt[i] == 'E')
6098 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
6099 invalidate_any_buried_refs (XVECEXP (x, i, j));
6100 }
6101}
6102
6103/* Find all the 'simple' MEMs which are used in LOADs and STORES. Simple
6104 being defined as MEM loads and stores to symbols, with no
6105 side effects and no registers in the expression. If there are any
f63d1bf7 6106 uses/defs which don't match this criteria, it is invalidated and
a13d4ebf
AM
6107 trimmed out later. */
6108
6109static void
6110compute_ld_motion_mems ()
6111{
6112 struct ls_expr * ptr;
0b17ab2f 6113 int bb;
a13d4ebf
AM
6114 rtx insn;
6115
6116 pre_ldst_mems = NULL;
6117
0b17ab2f 6118 for (bb = 0; bb < n_basic_blocks; bb++)
a13d4ebf 6119 {
0b17ab2f
RH
6120 for (insn = BLOCK_HEAD (bb);
6121 insn && insn != NEXT_INSN (BLOCK_END (bb));
a13d4ebf
AM
6122 insn = NEXT_INSN (insn))
6123 {
6124 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
6125 {
6126 if (GET_CODE (PATTERN (insn)) == SET)
6127 {
6128 rtx src = SET_SRC (PATTERN (insn));
6129 rtx dest = SET_DEST (PATTERN (insn));
6130
6131 /* Check for a simple LOAD... */
6132 if (GET_CODE (src) == MEM && simple_mem (src))
6133 {
6134 ptr = ldst_entry (src);
6135 if (GET_CODE (dest) == REG)
6136 ptr->loads = alloc_INSN_LIST (insn, ptr->loads);
6137 else
6138 ptr->invalid = 1;
6139 }
6140 else
6141 {
6142 /* Make sure there isn't a buried load somewhere. */
6143 invalidate_any_buried_refs (src);
6144 }
aaa4ca30 6145
a13d4ebf
AM
6146 /* Check for stores. Don't worry about aliased ones, they
6147 will block any movement we might do later. We only care
6148 about this exact pattern since those are the only
6149 circumstance that we will ignore the aliasing info. */
6150 if (GET_CODE (dest) == MEM && simple_mem (dest))
6151 {
6152 ptr = ldst_entry (dest);
6153
f54104df
AO
6154 if (GET_CODE (src) != MEM
6155 && GET_CODE (src) != ASM_OPERANDS)
a13d4ebf
AM
6156 ptr->stores = alloc_INSN_LIST (insn, ptr->stores);
6157 else
6158 ptr->invalid = 1;
6159 }
6160 }
6161 else
6162 invalidate_any_buried_refs (PATTERN (insn));
6163 }
6164 }
6165 }
6166}
6167
6168/* Remove any references that have been either invalidated or are not in the
6169 expression list for pre gcse. */
6170
6171static void
6172trim_ld_motion_mems ()
6173{
6174 struct ls_expr * last = NULL;
6175 struct ls_expr * ptr = first_ls_expr ();
6176
6177 while (ptr != NULL)
6178 {
6179 int del = ptr->invalid;
6180 struct expr * expr = NULL;
6181
6182 /* Delete if entry has been made invalid. */
6183 if (!del)
6184 {
6185 unsigned int i;
6186
6187 del = 1;
6188 /* Delete if we cannot find this mem in the expression list. */
6189 for (i = 0; i < expr_hash_table_size && del; i++)
6190 {
6191 for (expr = expr_hash_table[i];
6192 expr != NULL;
6193 expr = expr->next_same_hash)
6194 if (expr_equiv_p (expr->expr, ptr->pattern))
6195 {
6196 del = 0;
6197 break;
6198 }
6199 }
6200 }
6201
6202 if (del)
6203 {
6204 if (last != NULL)
6205 {
6206 last->next = ptr->next;
6207 free_ldst_entry (ptr);
6208 ptr = last->next;
6209 }
6210 else
6211 {
6212 pre_ldst_mems = pre_ldst_mems->next;
6213 free_ldst_entry (ptr);
6214 ptr = pre_ldst_mems;
6215 }
6216 }
6217 else
6218 {
6219 /* Set the expression field if we are keeping it. */
6220 last = ptr;
6221 ptr->expr = expr;
6222 ptr = ptr->next;
6223 }
6224 }
6225
6226 /* Show the world what we've found. */
6227 if (gcse_file && pre_ldst_mems != NULL)
6228 print_ldst_list (gcse_file);
6229}
6230
6231/* This routine will take an expression which we are replacing with
6232 a reaching register, and update any stores that are needed if
6233 that expression is in the ld_motion list. Stores are updated by
6234 copying their SRC to the reaching register, and then storeing
6235 the reaching register into the store location. These keeps the
6236 correct value in the reaching register for the loads. */
6237
6238static void
6239update_ld_motion_stores (expr)
6240 struct expr * expr;
6241{
6242 struct ls_expr * mem_ptr;
6243
6244 if ((mem_ptr = find_rtx_in_ldst (expr->expr)))
6245 {
6246 /* We can try to find just the REACHED stores, but is shouldn't
6247 matter to set the reaching reg everywhere... some might be
6248 dead and should be eliminated later. */
6249
6250 /* We replace SET mem = expr with
6251 SET reg = expr
6252 SET mem = reg , where reg is the
6253 reaching reg used in the load. */
6254 rtx list = mem_ptr->stores;
6255
6256 for ( ; list != NULL_RTX; list = XEXP (list, 1))
6257 {
6258 rtx insn = XEXP (list, 0);
6259 rtx pat = PATTERN (insn);
6260 rtx src = SET_SRC (pat);
6261 rtx reg = expr->reaching_reg;
c57718d3 6262 rtx copy, new;
a13d4ebf
AM
6263
6264 /* If we've already copied it, continue. */
6265 if (expr->reaching_reg == src)
6266 continue;
6267
6268 if (gcse_file)
6269 {
6270 fprintf (gcse_file, "PRE: store updated with reaching reg ");
6271 print_rtl (gcse_file, expr->reaching_reg);
6272 fprintf (gcse_file, ":\n ");
6273 print_inline_rtx (gcse_file, insn, 8);
6274 fprintf (gcse_file, "\n");
6275 }
6276
6277 copy = gen_move_insn ( reg, SET_SRC (pat));
c57718d3
RK
6278 new = emit_insn_before (copy, insn);
6279 record_one_set (REGNO (reg), new);
a13d4ebf
AM
6280 SET_SRC (pat) = reg;
6281
6282 /* un-recognize this pattern since it's probably different now. */
6283 INSN_CODE (insn) = -1;
6284 gcse_create_count++;
6285 }
6286 }
6287}
6288\f
6289/* Store motion code. */
6290
aaa4ca30
AJ
6291/* This is used to communicate the target bitvector we want to use in the
6292 reg_set_info routine when called via the note_stores mechanism. */
6293static sbitmap * regvec;
6294
a13d4ebf
AM
6295/* Used in computing the reverse edge graph bit vectors. */
6296static sbitmap * st_antloc;
6297
6298/* Global holding the number of store expressions we are dealing with. */
6299static int num_stores;
6300
aaa4ca30 6301/* Checks to set if we need to mark a register set. Called from note_stores. */
a13d4ebf 6302
aaa4ca30
AJ
6303static void
6304reg_set_info (dest, setter, data)
6305 rtx dest, setter ATTRIBUTE_UNUSED;
6306 void * data ATTRIBUTE_UNUSED;
a13d4ebf 6307{
aaa4ca30
AJ
6308 if (GET_CODE (dest) == SUBREG)
6309 dest = SUBREG_REG (dest);
adfcce61 6310
aaa4ca30
AJ
6311 if (GET_CODE (dest) == REG)
6312 SET_BIT (*regvec, REGNO (dest));
a13d4ebf
AM
6313}
6314
6315/* Return non-zero if the register operands of expression X are killed
aaa4ca30 6316 anywhere in basic block BB. */
a13d4ebf
AM
6317
6318static int
aaa4ca30 6319store_ops_ok (x, bb)
a13d4ebf 6320 rtx x;
e2d2ed72 6321 basic_block bb;
a13d4ebf
AM
6322{
6323 int i;
6324 enum rtx_code code;
6325 const char * fmt;
6326
6327 /* Repeat is used to turn tail-recursion into iteration. */
6328 repeat:
6329
6330 if (x == 0)
6331 return 1;
6332
6333 code = GET_CODE (x);
6334 switch (code)
6335 {
6336 case REG:
aaa4ca30
AJ
6337 /* If a reg has changed after us in this
6338 block, the operand has been killed. */
0b17ab2f 6339 return TEST_BIT (reg_set_in_block[bb->index], REGNO (x));
a13d4ebf
AM
6340
6341 case MEM:
6342 x = XEXP (x, 0);
6343 goto repeat;
6344
6345 case PRE_DEC:
6346 case PRE_INC:
6347 case POST_DEC:
6348 case POST_INC:
6349 return 0;
6350
6351 case PC:
6352 case CC0: /*FIXME*/
6353 case CONST:
6354 case CONST_INT:
6355 case CONST_DOUBLE:
69ef87e2 6356 case CONST_VECTOR:
a13d4ebf
AM
6357 case SYMBOL_REF:
6358 case LABEL_REF:
6359 case ADDR_VEC:
6360 case ADDR_DIFF_VEC:
6361 return 1;
6362
6363 default:
6364 break;
6365 }
6366
6367 i = GET_RTX_LENGTH (code) - 1;
6368 fmt = GET_RTX_FORMAT (code);
6369
6370 for (; i >= 0; i--)
6371 {
6372 if (fmt[i] == 'e')
6373 {
6374 rtx tem = XEXP (x, i);
6375
6376 /* If we are about to do the last recursive call
6377 needed at this level, change it into iteration.
6378 This function is called enough to be worth it. */
6379 if (i == 0)
6380 {
6381 x = tem;
6382 goto repeat;
6383 }
6384
aaa4ca30 6385 if (! store_ops_ok (tem, bb))
a13d4ebf
AM
6386 return 0;
6387 }
6388 else if (fmt[i] == 'E')
6389 {
6390 int j;
6391
6392 for (j = 0; j < XVECLEN (x, i); j++)
6393 {
aaa4ca30 6394 if (! store_ops_ok (XVECEXP (x, i, j), bb))
a13d4ebf
AM
6395 return 0;
6396 }
6397 }
6398 }
6399
6400 return 1;
6401}
6402
aaa4ca30 6403/* Determine whether insn is MEM store pattern that we will consider moving. */
a13d4ebf
AM
6404
6405static void
6406find_moveable_store (insn)
6407 rtx insn;
6408{
6409 struct ls_expr * ptr;
6410 rtx dest = PATTERN (insn);
6411
f54104df
AO
6412 if (GET_CODE (dest) != SET
6413 || GET_CODE (SET_SRC (dest)) == ASM_OPERANDS)
a13d4ebf
AM
6414 return;
6415
6416 dest = SET_DEST (dest);
6417
6418 if (GET_CODE (dest) != MEM || MEM_VOLATILE_P (dest)
6419 || GET_MODE (dest) == BLKmode)
aaa4ca30
AJ
6420 return;
6421
6422 if (GET_CODE (XEXP (dest, 0)) != SYMBOL_REF)
a13d4ebf 6423 return;
aaa4ca30
AJ
6424
6425 if (rtx_varies_p (XEXP (dest, 0), 0))
a13d4ebf 6426 return;
aaa4ca30 6427
a13d4ebf
AM
6428 ptr = ldst_entry (dest);
6429 ptr->stores = alloc_INSN_LIST (insn, ptr->stores);
6430}
6431
aaa4ca30
AJ
6432/* Perform store motion. Much like gcse, except we move expressions the
6433 other way by looking at the flowgraph in reverse. */
a13d4ebf
AM
6434
6435static int
6436compute_store_table ()
6437{
0b17ab2f 6438 int bb, ret;
aaa4ca30 6439 unsigned regno;
a13d4ebf 6440 rtx insn, pat;
aaa4ca30 6441
a13d4ebf
AM
6442 max_gcse_regno = max_reg_num ();
6443
0b17ab2f 6444 reg_set_in_block = (sbitmap *) sbitmap_vector_alloc (n_basic_blocks,
aaa4ca30 6445 max_gcse_regno);
0b17ab2f 6446 sbitmap_vector_zero (reg_set_in_block, n_basic_blocks);
a13d4ebf 6447 pre_ldst_mems = 0;
aaa4ca30 6448
a13d4ebf 6449 /* Find all the stores we care about. */
0b17ab2f 6450 for (bb = 0; bb < n_basic_blocks; bb++)
a13d4ebf 6451 {
0b17ab2f
RH
6452 regvec = & (reg_set_in_block[bb]);
6453 for (insn = BLOCK_END (bb);
6454 insn && insn != PREV_INSN (BLOCK_HEAD (bb));
a13d4ebf
AM
6455 insn = PREV_INSN (insn))
6456 {
19652adf
ZW
6457 /* Ignore anything that is not a normal insn. */
6458 if (! INSN_P (insn))
a13d4ebf
AM
6459 continue;
6460
aaa4ca30
AJ
6461 if (GET_CODE (insn) == CALL_INSN)
6462 {
19652adf
ZW
6463 bool clobbers_all = false;
6464#ifdef NON_SAVING_SETJMP
6465 if (NON_SAVING_SETJMP
6466 && find_reg_note (insn, REG_SETJMP, NULL_RTX))
6467 clobbers_all = true;
6468#endif
6469
aaa4ca30 6470 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
19652adf
ZW
6471 if (clobbers_all
6472 || TEST_HARD_REG_BIT (regs_invalidated_by_call, regno))
0b17ab2f 6473 SET_BIT (reg_set_in_block[bb], regno);
aaa4ca30
AJ
6474 }
6475
a13d4ebf 6476 pat = PATTERN (insn);
aaa4ca30
AJ
6477 note_stores (pat, reg_set_info, NULL);
6478
a13d4ebf
AM
6479 /* Now that we've marked regs, look for stores. */
6480 if (GET_CODE (pat) == SET)
6481 find_moveable_store (insn);
6482 }
6483 }
6484
6485 ret = enumerate_ldsts ();
6486
6487 if (gcse_file)
6488 {
6489 fprintf (gcse_file, "Store Motion Expressions.\n");
6490 print_ldst_list (gcse_file);
6491 }
6492
6493 return ret;
6494}
6495
aaa4ca30 6496/* Check to see if the load X is aliased with STORE_PATTERN. */
a13d4ebf
AM
6497
6498static int
6499load_kills_store (x, store_pattern)
6500 rtx x, store_pattern;
6501{
6502 if (true_dependence (x, GET_MODE (x), store_pattern, rtx_addr_varies_p))
6503 return 1;
6504 return 0;
6505}
6506
aaa4ca30
AJ
6507/* Go through the entire insn X, looking for any loads which might alias
6508 STORE_PATTERN. Return 1 if found. */
a13d4ebf
AM
6509
6510static int
6511find_loads (x, store_pattern)
6512 rtx x, store_pattern;
6513{
6514 const char * fmt;
8e42ace1 6515 int i, j;
a13d4ebf
AM
6516 int ret = 0;
6517
24a28584
JH
6518 if (!x)
6519 return 0;
6520
a13d4ebf
AM
6521 if (GET_CODE (x) == SET)
6522 x = SET_SRC (x);
6523
6524 if (GET_CODE (x) == MEM)
6525 {
6526 if (load_kills_store (x, store_pattern))
6527 return 1;
6528 }
6529
6530 /* Recursively process the insn. */
6531 fmt = GET_RTX_FORMAT (GET_CODE (x));
6532
6533 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0 && !ret; i--)
6534 {
6535 if (fmt[i] == 'e')
6536 ret |= find_loads (XEXP (x, i), store_pattern);
6537 else if (fmt[i] == 'E')
6538 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
6539 ret |= find_loads (XVECEXP (x, i, j), store_pattern);
6540 }
6541 return ret;
6542}
6543
6544/* Check if INSN kills the store pattern X (is aliased with it).
6545 Return 1 if it it does. */
6546
6547static int
6548store_killed_in_insn (x, insn)
6549 rtx x, insn;
6550{
6551 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
6552 return 0;
6553
6554 if (GET_CODE (insn) == CALL_INSN)
6555 {
1218665b
JJ
6556 /* A normal or pure call might read from pattern,
6557 but a const call will not. */
a6a063b8 6558 return ! CONST_OR_PURE_CALL_P (insn) || pure_call_p (insn);
a13d4ebf
AM
6559 }
6560
6561 if (GET_CODE (PATTERN (insn)) == SET)
6562 {
6563 rtx pat = PATTERN (insn);
6564 /* Check for memory stores to aliased objects. */
6565 if (GET_CODE (SET_DEST (pat)) == MEM && !expr_equiv_p (SET_DEST (pat), x))
aaa4ca30 6566 /* pretend its a load and check for aliasing. */
a13d4ebf
AM
6567 if (find_loads (SET_DEST (pat), x))
6568 return 1;
6569 return find_loads (SET_SRC (pat), x);
6570 }
6571 else
6572 return find_loads (PATTERN (insn), x);
6573}
6574
6575/* Returns 1 if the expression X is loaded or clobbered on or after INSN
6576 within basic block BB. */
6577
6578static int
aaa4ca30 6579store_killed_after (x, insn, bb)
a13d4ebf 6580 rtx x, insn;
e2d2ed72 6581 basic_block bb;
a13d4ebf 6582{
8e42ace1 6583 rtx last = bb->end;
a13d4ebf 6584
8e42ace1
KH
6585 if (insn == last)
6586 return 0;
aaa4ca30
AJ
6587
6588 /* Check if the register operands of the store are OK in this block.
6589 Note that if registers are changed ANYWHERE in the block, we'll
6590 decide we can't move it, regardless of whether it changed above
6591 or below the store. This could be improved by checking the register
6592 operands while lookinng for aliasing in each insn. */
6593 if (!store_ops_ok (XEXP (x, 0), bb))
a13d4ebf
AM
6594 return 1;
6595
8e42ace1
KH
6596 for ( ; insn && insn != NEXT_INSN (last); insn = NEXT_INSN (insn))
6597 if (store_killed_in_insn (x, insn))
6598 return 1;
a13d4ebf
AM
6599
6600 return 0;
6601}
6602
aaa4ca30 6603/* Returns 1 if the expression X is loaded or clobbered on or before INSN
a13d4ebf
AM
6604 within basic block BB. */
6605static int
6606store_killed_before (x, insn, bb)
6607 rtx x, insn;
e2d2ed72 6608 basic_block bb;
a13d4ebf 6609{
8e42ace1 6610 rtx first = bb->head;
a13d4ebf 6611
8e42ace1
KH
6612 if (insn == first)
6613 return store_killed_in_insn (x, insn);
aaa4ca30
AJ
6614
6615 /* Check if the register operands of the store are OK in this block.
6616 Note that if registers are changed ANYWHERE in the block, we'll
6617 decide we can't move it, regardless of whether it changed above
6618 or below the store. This could be improved by checking the register
6619 operands while lookinng for aliasing in each insn. */
6620 if (!store_ops_ok (XEXP (x, 0), bb))
a13d4ebf
AM
6621 return 1;
6622
8e42ace1
KH
6623 for ( ; insn && insn != PREV_INSN (first); insn = PREV_INSN (insn))
6624 if (store_killed_in_insn (x, insn))
6625 return 1;
a13d4ebf 6626
8e42ace1 6627 return 0;
a13d4ebf
AM
6628}
6629
6630#define ANTIC_STORE_LIST(x) ((x)->loads)
6631#define AVAIL_STORE_LIST(x) ((x)->stores)
6632
6633/* Given the table of available store insns at the end of blocks,
6634 determine which ones are not killed by aliasing, and generate
6635 the appropriate vectors for gen and killed. */
6636static void
6637build_store_vectors ()
6638{
0b17ab2f
RH
6639 basic_block bb;
6640 int b;
a13d4ebf
AM
6641 rtx insn, st;
6642 struct ls_expr * ptr;
6643
6644 /* Build the gen_vector. This is any store in the table which is not killed
6645 by aliasing later in its block. */
0b17ab2f
RH
6646 ae_gen = (sbitmap *) sbitmap_vector_alloc (n_basic_blocks, num_stores);
6647 sbitmap_vector_zero (ae_gen, n_basic_blocks);
a13d4ebf 6648
0b17ab2f
RH
6649 st_antloc = (sbitmap *) sbitmap_vector_alloc (n_basic_blocks, num_stores);
6650 sbitmap_vector_zero (st_antloc, n_basic_blocks);
aaa4ca30 6651
a13d4ebf
AM
6652 for (ptr = first_ls_expr (); ptr != NULL; ptr = next_ls_expr (ptr))
6653 {
6654 /* Put all the stores into either the antic list, or the avail list,
6655 or both. */
6656 rtx store_list = ptr->stores;
6657 ptr->stores = NULL_RTX;
6658
6659 for (st = store_list; st != NULL; st = XEXP (st, 1))
6660 {
6661 insn = XEXP (st, 0);
e2d2ed72 6662 bb = BLOCK_FOR_INSN (insn);
aaa4ca30
AJ
6663
6664 if (!store_killed_after (ptr->pattern, insn, bb))
a13d4ebf
AM
6665 {
6666 /* If we've already seen an availale expression in this block,
6667 we can delete the one we saw already (It occurs earlier in
6668 the block), and replace it with this one). We'll copy the
6669 old SRC expression to an unused register in case there
6670 are any side effects. */
0b17ab2f 6671 if (TEST_BIT (ae_gen[bb->index], ptr->index))
a13d4ebf
AM
6672 {
6673 /* Find previous store. */
6674 rtx st;
6675 for (st = AVAIL_STORE_LIST (ptr); st ; st = XEXP (st, 1))
e2d2ed72 6676 if (BLOCK_FOR_INSN (XEXP (st, 0)) == bb)
a13d4ebf
AM
6677 break;
6678 if (st)
6679 {
6680 rtx r = gen_reg_rtx (GET_MODE (ptr->pattern));
6681 if (gcse_file)
8e42ace1 6682 fprintf (gcse_file, "Removing redundant store:\n");
a13d4ebf
AM
6683 replace_store_insn (r, XEXP (st, 0), bb);
6684 XEXP (st, 0) = insn;
6685 continue;
6686 }
6687 }
0b17ab2f 6688 SET_BIT (ae_gen[bb->index], ptr->index);
a13d4ebf
AM
6689 AVAIL_STORE_LIST (ptr) = alloc_INSN_LIST (insn,
6690 AVAIL_STORE_LIST (ptr));
6691 }
6692
6693 if (!store_killed_before (ptr->pattern, insn, bb))
6694 {
6695 SET_BIT (st_antloc[BLOCK_NUM (insn)], ptr->index);
6696 ANTIC_STORE_LIST (ptr) = alloc_INSN_LIST (insn,
6697 ANTIC_STORE_LIST (ptr));
6698 }
6699 }
6700
6701 /* Free the original list of store insns. */
6702 free_INSN_LIST_list (&store_list);
6703 }
6704
0b17ab2f
RH
6705 ae_kill = (sbitmap *) sbitmap_vector_alloc (n_basic_blocks, num_stores);
6706 sbitmap_vector_zero (ae_kill, n_basic_blocks);
a13d4ebf 6707
0b17ab2f
RH
6708 transp = (sbitmap *) sbitmap_vector_alloc (n_basic_blocks, num_stores);
6709 sbitmap_vector_zero (transp, n_basic_blocks);
a13d4ebf
AM
6710
6711 for (ptr = first_ls_expr (); ptr != NULL; ptr = next_ls_expr (ptr))
0b17ab2f 6712 for (b = 0; b < n_basic_blocks; b++)
a13d4ebf 6713 {
0b17ab2f 6714 if (store_killed_after (ptr->pattern, BLOCK_HEAD (b), BASIC_BLOCK (b)))
a13d4ebf 6715 {
dc297297 6716 /* The anticipatable expression is not killed if it's gen'd. */
aaa4ca30
AJ
6717 /*
6718 We leave this check out for now. If we have a code sequence
6719 in a block which looks like:
6720 ST MEMa = x
6721 L y = MEMa
6722 ST MEMa = z
6723 We should flag this as having an ANTIC expression, NOT
6724 transparent, NOT killed, and AVAIL.
6725 Unfortunately, since we haven't re-written all loads to
6726 use the reaching reg, we'll end up doing an incorrect
6727 Load in the middle here if we push the store down. It happens in
6728 gcc.c-torture/execute/960311-1.c with -O3
6729 If we always kill it in this case, we'll sometimes do
6730 uneccessary work, but it shouldn't actually hurt anything.
6731 if (!TEST_BIT (ae_gen[b], ptr->index)). */
0b17ab2f 6732 SET_BIT (ae_kill[b], ptr->index);
aaa4ca30
AJ
6733 }
6734 else
0b17ab2f 6735 SET_BIT (transp[b], ptr->index);
aaa4ca30
AJ
6736 }
6737
6738 /* Any block with no exits calls some non-returning function, so
6739 we better mark the store killed here, or we might not store to
6740 it at all. If we knew it was abort, we wouldn't have to store,
6741 but we don't know that for sure. */
6742 if (gcse_file)
6743 {
6744 fprintf (gcse_file, "ST_avail and ST_antic (shown under loads..)\n");
6745 print_ldst_list (gcse_file);
0b17ab2f
RH
6746 dump_sbitmap_vector (gcse_file, "st_antloc", "", st_antloc, n_basic_blocks);
6747 dump_sbitmap_vector (gcse_file, "st_kill", "", ae_kill, n_basic_blocks);
6748 dump_sbitmap_vector (gcse_file, "Transpt", "", transp, n_basic_blocks);
6749 dump_sbitmap_vector (gcse_file, "st_avloc", "", ae_gen, n_basic_blocks);
a13d4ebf
AM
6750 }
6751}
6752
6753/* Insert an instruction at the begining of a basic block, and update
6754 the BLOCK_HEAD if needed. */
6755
6756static void
6757insert_insn_start_bb (insn, bb)
6758 rtx insn;
e2d2ed72 6759 basic_block bb;
a13d4ebf
AM
6760{
6761 /* Insert at start of successor block. */
e2d2ed72
AM
6762 rtx prev = PREV_INSN (bb->head);
6763 rtx before = bb->head;
a13d4ebf
AM
6764 while (before != 0)
6765 {
6766 if (GET_CODE (before) != CODE_LABEL
6767 && (GET_CODE (before) != NOTE
6768 || NOTE_LINE_NUMBER (before) != NOTE_INSN_BASIC_BLOCK))
6769 break;
6770 prev = before;
e2d2ed72 6771 if (prev == bb->end)
a13d4ebf
AM
6772 break;
6773 before = NEXT_INSN (before);
6774 }
6775
6776 insn = emit_insn_after (insn, prev);
6777
a13d4ebf
AM
6778 if (gcse_file)
6779 {
6780 fprintf (gcse_file, "STORE_MOTION insert store at start of BB %d:\n",
0b17ab2f 6781 bb->index);
a13d4ebf
AM
6782 print_inline_rtx (gcse_file, insn, 6);
6783 fprintf (gcse_file, "\n");
6784 }
6785}
6786
6787/* This routine will insert a store on an edge. EXPR is the ldst entry for
6788 the memory reference, and E is the edge to insert it on. Returns non-zero
6789 if an edge insertion was performed. */
6790
6791static int
6792insert_store (expr, e)
6793 struct ls_expr * expr;
6794 edge e;
6795{
6796 rtx reg, insn;
e2d2ed72 6797 basic_block bb;
a13d4ebf
AM
6798 edge tmp;
6799
6800 /* We did all the deleted before this insert, so if we didn't delete a
6801 store, then we haven't set the reaching reg yet either. */
6802 if (expr->reaching_reg == NULL_RTX)
6803 return 0;
6804
6805 reg = expr->reaching_reg;
6806 insn = gen_move_insn (expr->pattern, reg);
6807
6808 /* If we are inserting this expression on ALL predecessor edges of a BB,
6809 insert it at the start of the BB, and reset the insert bits on the other
ff7cc307 6810 edges so we don't try to insert it on the other edges. */
e2d2ed72 6811 bb = e->dest;
a13d4ebf
AM
6812 for (tmp = e->dest->pred; tmp ; tmp = tmp->pred_next)
6813 {
6814 int index = EDGE_INDEX (edge_list, tmp->src, tmp->dest);
6815 if (index == EDGE_INDEX_NO_EDGE)
6816 abort ();
6817 if (! TEST_BIT (pre_insert_map[index], expr->index))
6818 break;
6819 }
6820
6821 /* If tmp is NULL, we found an insertion on every edge, blank the
6822 insertion vector for these edges, and insert at the start of the BB. */
e2d2ed72 6823 if (!tmp && bb != EXIT_BLOCK_PTR)
a13d4ebf
AM
6824 {
6825 for (tmp = e->dest->pred; tmp ; tmp = tmp->pred_next)
6826 {
6827 int index = EDGE_INDEX (edge_list, tmp->src, tmp->dest);
6828 RESET_BIT (pre_insert_map[index], expr->index);
6829 }
6830 insert_insn_start_bb (insn, bb);
6831 return 0;
6832 }
6833
6834 /* We can't insert on this edge, so we'll insert at the head of the
6835 successors block. See Morgan, sec 10.5. */
6836 if ((e->flags & EDGE_ABNORMAL) == EDGE_ABNORMAL)
6837 {
6838 insert_insn_start_bb (insn, bb);
6839 return 0;
6840 }
6841
6842 insert_insn_on_edge (insn, e);
6843
6844 if (gcse_file)
6845 {
6846 fprintf (gcse_file, "STORE_MOTION insert insn on edge (%d, %d):\n",
0b17ab2f 6847 e->src->index, e->dest->index);
a13d4ebf
AM
6848 print_inline_rtx (gcse_file, insn, 6);
6849 fprintf (gcse_file, "\n");
6850 }
6851
6852 return 1;
6853}
6854
6855/* This routine will replace a store with a SET to a specified register. */
6856
6857static void
6858replace_store_insn (reg, del, bb)
6859 rtx reg, del;
e2d2ed72 6860 basic_block bb;
a13d4ebf
AM
6861{
6862 rtx insn;
6863
6864 insn = gen_move_insn (reg, SET_SRC (PATTERN (del)));
6865 insn = emit_insn_after (insn, del);
a13d4ebf
AM
6866
6867 if (gcse_file)
6868 {
6869 fprintf (gcse_file,
0b17ab2f 6870 "STORE_MOTION delete insn in BB %d:\n ", bb->index);
a13d4ebf 6871 print_inline_rtx (gcse_file, del, 6);
8e42ace1 6872 fprintf (gcse_file, "\nSTORE MOTION replaced with insn:\n ");
a13d4ebf 6873 print_inline_rtx (gcse_file, insn, 6);
8e42ace1 6874 fprintf (gcse_file, "\n");
a13d4ebf
AM
6875 }
6876
49ce134f 6877 delete_insn (del);
a13d4ebf
AM
6878}
6879
6880
6881/* Delete a store, but copy the value that would have been stored into
6882 the reaching_reg for later storing. */
6883
6884static void
6885delete_store (expr, bb)
6886 struct ls_expr * expr;
e2d2ed72 6887 basic_block bb;
a13d4ebf
AM
6888{
6889 rtx reg, i, del;
6890
6891 if (expr->reaching_reg == NULL_RTX)
6892 expr->reaching_reg = gen_reg_rtx (GET_MODE (expr->pattern));
6893
6894
6895 /* If there is more than 1 store, the earlier ones will be dead,
6896 but it doesn't hurt to replace them here. */
6897 reg = expr->reaching_reg;
6898
6899 for (i = AVAIL_STORE_LIST (expr); i; i = XEXP (i, 1))
6900 {
6901 del = XEXP (i, 0);
e2d2ed72 6902 if (BLOCK_FOR_INSN (del) == bb)
a13d4ebf
AM
6903 {
6904 /* We know there is only one since we deleted redundant
6905 ones during the available computation. */
6906 replace_store_insn (reg, del, bb);
6907 break;
6908 }
6909 }
6910}
6911
6912/* Free memory used by store motion. */
6913
6914static void
6915free_store_memory ()
6916{
6917 free_ldst_mems ();
aaa4ca30 6918
a13d4ebf 6919 if (ae_gen)
5a660bff 6920 sbitmap_vector_free (ae_gen);
a13d4ebf 6921 if (ae_kill)
5a660bff 6922 sbitmap_vector_free (ae_kill);
a13d4ebf 6923 if (transp)
5a660bff 6924 sbitmap_vector_free (transp);
a13d4ebf 6925 if (st_antloc)
5a660bff 6926 sbitmap_vector_free (st_antloc);
a13d4ebf 6927 if (pre_insert_map)
5a660bff 6928 sbitmap_vector_free (pre_insert_map);
a13d4ebf 6929 if (pre_delete_map)
5a660bff 6930 sbitmap_vector_free (pre_delete_map);
aaa4ca30
AJ
6931 if (reg_set_in_block)
6932 sbitmap_vector_free (reg_set_in_block);
a13d4ebf
AM
6933
6934 ae_gen = ae_kill = transp = st_antloc = NULL;
6935 pre_insert_map = pre_delete_map = reg_set_in_block = NULL;
6936}
6937
6938/* Perform store motion. Much like gcse, except we move expressions the
6939 other way by looking at the flowgraph in reverse. */
6940
6941static void
6942store_motion ()
6943{
0b17ab2f 6944 int x;
a13d4ebf 6945 struct ls_expr * ptr;
adfcce61 6946 int update_flow = 0;
aaa4ca30 6947
a13d4ebf
AM
6948 if (gcse_file)
6949 {
6950 fprintf (gcse_file, "before store motion\n");
6951 print_rtl (gcse_file, get_insns ());
6952 }
6953
6954
6955 init_alias_analysis ();
aaa4ca30 6956
a13d4ebf
AM
6957 /* Find all the stores that are live to the end of their block. */
6958 num_stores = compute_store_table ();
6959 if (num_stores == 0)
6960 {
aaa4ca30 6961 sbitmap_vector_free (reg_set_in_block);
a13d4ebf
AM
6962 end_alias_analysis ();
6963 return;
6964 }
6965
6966 /* Now compute whats actually available to move. */
6967 add_noreturn_fake_exit_edges ();
6968 build_store_vectors ();
6969
6970 edge_list = pre_edge_rev_lcm (gcse_file, num_stores, transp, ae_gen,
6971 st_antloc, ae_kill, &pre_insert_map,
6972 &pre_delete_map);
6973
6974 /* Now we want to insert the new stores which are going to be needed. */
6975 for (ptr = first_ls_expr (); ptr != NULL; ptr = next_ls_expr (ptr))
6976 {
0b17ab2f
RH
6977 for (x = 0; x < n_basic_blocks; x++)
6978 if (TEST_BIT (pre_delete_map[x], ptr->index))
6979 delete_store (ptr, BASIC_BLOCK (x));
a13d4ebf 6980
0b17ab2f
RH
6981 for (x = 0; x < NUM_EDGES (edge_list); x++)
6982 if (TEST_BIT (pre_insert_map[x], ptr->index))
6983 update_flow |= insert_store (ptr, INDEX_EDGE (edge_list, x));
a13d4ebf
AM
6984 }
6985
6986 if (update_flow)
6987 commit_edge_insertions ();
aaa4ca30 6988
a13d4ebf
AM
6989 free_store_memory ();
6990 free_edge_list (edge_list);
6991 remove_fake_edges ();
6992 end_alias_analysis ();
6993}
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