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e45425ec | 1 | /* Partial redundancy elimination / Hoisting for RTL. |
62e5bf5d | 2 | Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, |
8cba9a05 | 3 | 2006, 2007, 2008, 2009, 2010, 2011, 2012 Free Software Foundation, Inc. |
7506f491 | 4 | |
1322177d | 5 | This file is part of GCC. |
7506f491 | 6 | |
1322177d LB |
7 | GCC is free software; you can redistribute it and/or modify it under |
8 | the terms of the GNU General Public License as published by the Free | |
9dcd6f09 | 9 | Software Foundation; either version 3, or (at your option) any later |
1322177d | 10 | version. |
7506f491 | 11 | |
1322177d LB |
12 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY |
13 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
15 | for more details. | |
7506f491 DE |
16 | |
17 | You should have received a copy of the GNU General Public License | |
9dcd6f09 NC |
18 | along with GCC; see the file COPYING3. If not see |
19 | <http://www.gnu.org/licenses/>. */ | |
7506f491 DE |
20 | |
21 | /* TODO | |
22 | - reordering of memory allocation and freeing to be more space efficient | |
b11f0116 BC |
23 | - calc rough register pressure information and use the info to drive all |
24 | kinds of code motion (including code hoisting) in a unified way. | |
7506f491 DE |
25 | */ |
26 | ||
27 | /* References searched while implementing this. | |
7506f491 DE |
28 | |
29 | Compilers Principles, Techniques and Tools | |
30 | Aho, Sethi, Ullman | |
31 | Addison-Wesley, 1988 | |
32 | ||
33 | Global Optimization by Suppression of Partial Redundancies | |
34 | E. Morel, C. Renvoise | |
35 | communications of the acm, Vol. 22, Num. 2, Feb. 1979 | |
36 | ||
37 | A Portable Machine-Independent Global Optimizer - Design and Measurements | |
38 | Frederick Chow | |
39 | Stanford Ph.D. thesis, Dec. 1983 | |
40 | ||
7506f491 DE |
41 | A Fast Algorithm for Code Movement Optimization |
42 | D.M. Dhamdhere | |
43 | SIGPLAN Notices, Vol. 23, Num. 10, Oct. 1988 | |
44 | ||
45 | A Solution to a Problem with Morel and Renvoise's | |
46 | Global Optimization by Suppression of Partial Redundancies | |
47 | K-H Drechsler, M.P. Stadel | |
48 | ACM TOPLAS, Vol. 10, Num. 4, Oct. 1988 | |
49 | ||
50 | Practical Adaptation of the Global Optimization | |
51 | Algorithm of Morel and Renvoise | |
52 | D.M. Dhamdhere | |
53 | ACM TOPLAS, Vol. 13, Num. 2. Apr. 1991 | |
54 | ||
55 | Efficiently Computing Static Single Assignment Form and the Control | |
56 | Dependence Graph | |
57 | R. Cytron, J. Ferrante, B.K. Rosen, M.N. Wegman, and F.K. Zadeck | |
58 | ACM TOPLAS, Vol. 13, Num. 4, Oct. 1991 | |
59 | ||
7506f491 DE |
60 | Lazy Code Motion |
61 | J. Knoop, O. Ruthing, B. Steffen | |
62 | ACM SIGPLAN Notices Vol. 27, Num. 7, Jul. 1992, '92 Conference on PLDI | |
63 | ||
64 | What's In a Region? Or Computing Control Dependence Regions in Near-Linear | |
65 | Time for Reducible Flow Control | |
66 | Thomas Ball | |
67 | ACM Letters on Programming Languages and Systems, | |
68 | Vol. 2, Num. 1-4, Mar-Dec 1993 | |
69 | ||
70 | An Efficient Representation for Sparse Sets | |
71 | Preston Briggs, Linda Torczon | |
72 | ACM Letters on Programming Languages and Systems, | |
73 | Vol. 2, Num. 1-4, Mar-Dec 1993 | |
74 | ||
75 | A Variation of Knoop, Ruthing, and Steffen's Lazy Code Motion | |
76 | K-H Drechsler, M.P. Stadel | |
77 | ACM SIGPLAN Notices, Vol. 28, Num. 5, May 1993 | |
78 | ||
79 | Partial Dead Code Elimination | |
80 | J. Knoop, O. Ruthing, B. Steffen | |
81 | ACM SIGPLAN Notices, Vol. 29, Num. 6, Jun. 1994 | |
82 | ||
83 | Effective Partial Redundancy Elimination | |
84 | P. Briggs, K.D. Cooper | |
85 | ACM SIGPLAN Notices, Vol. 29, Num. 6, Jun. 1994 | |
86 | ||
87 | The Program Structure Tree: Computing Control Regions in Linear Time | |
88 | R. Johnson, D. Pearson, K. Pingali | |
89 | ACM SIGPLAN Notices, Vol. 29, Num. 6, Jun. 1994 | |
90 | ||
91 | Optimal Code Motion: Theory and Practice | |
92 | J. Knoop, O. Ruthing, B. Steffen | |
93 | ACM TOPLAS, Vol. 16, Num. 4, Jul. 1994 | |
94 | ||
95 | The power of assignment motion | |
96 | J. Knoop, O. Ruthing, B. Steffen | |
97 | ACM SIGPLAN Notices Vol. 30, Num. 6, Jun. 1995, '95 Conference on PLDI | |
98 | ||
99 | Global code motion / global value numbering | |
100 | C. Click | |
101 | ACM SIGPLAN Notices Vol. 30, Num. 6, Jun. 1995, '95 Conference on PLDI | |
102 | ||
103 | Value Driven Redundancy Elimination | |
104 | L.T. Simpson | |
105 | Rice University Ph.D. thesis, Apr. 1996 | |
106 | ||
107 | Value Numbering | |
108 | L.T. Simpson | |
109 | Massively Scalar Compiler Project, Rice University, Sep. 1996 | |
110 | ||
111 | High Performance Compilers for Parallel Computing | |
112 | Michael Wolfe | |
113 | Addison-Wesley, 1996 | |
114 | ||
f4e584dc JL |
115 | Advanced Compiler Design and Implementation |
116 | Steven Muchnick | |
117 | Morgan Kaufmann, 1997 | |
118 | ||
a42cd965 AM |
119 | Building an Optimizing Compiler |
120 | Robert Morgan | |
121 | Digital Press, 1998 | |
122 | ||
f4e584dc JL |
123 | People wishing to speed up the code here should read: |
124 | Elimination Algorithms for Data Flow Analysis | |
125 | B.G. Ryder, M.C. Paull | |
126 | ACM Computing Surveys, Vol. 18, Num. 3, Sep. 1986 | |
127 | ||
128 | How to Analyze Large Programs Efficiently and Informatively | |
129 | D.M. Dhamdhere, B.K. Rosen, F.K. Zadeck | |
130 | ACM SIGPLAN Notices Vol. 27, Num. 7, Jul. 1992, '92 Conference on PLDI | |
131 | ||
7506f491 DE |
132 | People wishing to do something different can find various possibilities |
133 | in the above papers and elsewhere. | |
134 | */ | |
135 | ||
136 | #include "config.h" | |
50b2596f | 137 | #include "system.h" |
4977bab6 ZW |
138 | #include "coretypes.h" |
139 | #include "tm.h" | |
718f9c0f | 140 | #include "diagnostic-core.h" |
01198c2f | 141 | #include "toplev.h" |
7506f491 | 142 | |
b11f0116 | 143 | #include "hard-reg-set.h" |
7506f491 | 144 | #include "rtl.h" |
b0656d8b | 145 | #include "tree.h" |
6baf1cc8 | 146 | #include "tm_p.h" |
7506f491 | 147 | #include "regs.h" |
b11f0116 | 148 | #include "ira.h" |
7506f491 | 149 | #include "flags.h" |
7506f491 DE |
150 | #include "insn-config.h" |
151 | #include "recog.h" | |
152 | #include "basic-block.h" | |
49ad7cfa | 153 | #include "function.h" |
589005ff | 154 | #include "expr.h" |
e7d482b9 | 155 | #include "except.h" |
fb0c0a12 | 156 | #include "ggc.h" |
f1fa37ff | 157 | #include "params.h" |
ae860ff7 | 158 | #include "cselib.h" |
d128effb | 159 | #include "intl.h" |
7506f491 | 160 | #include "obstack.h" |
ef330312 | 161 | #include "tree-pass.h" |
9727e468 | 162 | #include "hashtab.h" |
6fb5fa3c DB |
163 | #include "df.h" |
164 | #include "dbgcnt.h" | |
ec0a1343 | 165 | #include "target.h" |
7c6811fe | 166 | #include "gcse.h" |
4fa31c2a | 167 | |
f4e584dc | 168 | /* We support GCSE via Partial Redundancy Elimination. PRE optimizations |
4cad6dba | 169 | are a superset of those done by classic GCSE. |
7506f491 | 170 | |
e45425ec SB |
171 | Two passes of copy/constant propagation are done around PRE or hoisting |
172 | because the first one enables more GCSE and the second one helps to clean | |
173 | up the copies that PRE and HOIST create. This is needed more for PRE than | |
174 | for HOIST because code hoisting will try to use an existing register | |
175 | containing the common subexpression rather than create a new one. This is | |
176 | harder to do for PRE because of the code motion (which HOIST doesn't do). | |
7506f491 DE |
177 | |
178 | Expressions we are interested in GCSE-ing are of the form | |
179 | (set (pseudo-reg) (expression)). | |
180 | Function want_to_gcse_p says what these are. | |
181 | ||
4cad6dba | 182 | In addition, expressions in REG_EQUAL notes are candidates for GCSE-ing. |
3906a4a1 | 183 | This allows PRE to hoist expressions that are expressed in multiple insns, |
4cad6dba SB |
184 | such as complex address calculations (e.g. for PIC code, or loads with a |
185 | high part and a low part). | |
3906a4a1 | 186 | |
7506f491 | 187 | PRE handles moving invariant expressions out of loops (by treating them as |
f4e584dc | 188 | partially redundant). |
7506f491 | 189 | |
7506f491 DE |
190 | ********************** |
191 | ||
192 | We used to support multiple passes but there are diminishing returns in | |
193 | doing so. The first pass usually makes 90% of the changes that are doable. | |
194 | A second pass can make a few more changes made possible by the first pass. | |
195 | Experiments show any further passes don't make enough changes to justify | |
196 | the expense. | |
197 | ||
198 | A study of spec92 using an unlimited number of passes: | |
199 | [1 pass] = 1208 substitutions, [2] = 577, [3] = 202, [4] = 192, [5] = 83, | |
200 | [6] = 34, [7] = 17, [8] = 9, [9] = 4, [10] = 4, [11] = 2, | |
201 | [12] = 2, [13] = 1, [15] = 1, [16] = 2, [41] = 1 | |
202 | ||
203 | It was found doing copy propagation between each pass enables further | |
204 | substitutions. | |
205 | ||
3906a4a1 SB |
206 | This study was done before expressions in REG_EQUAL notes were added as |
207 | candidate expressions for optimization, and before the GIMPLE optimizers | |
208 | were added. Probably, multiple passes is even less efficient now than | |
209 | at the time when the study was conducted. | |
210 | ||
7506f491 | 211 | PRE is quite expensive in complicated functions because the DFA can take |
3906a4a1 | 212 | a while to converge. Hence we only perform one pass. |
7506f491 DE |
213 | |
214 | ********************** | |
215 | ||
216 | The steps for PRE are: | |
217 | ||
218 | 1) Build the hash table of expressions we wish to GCSE (expr_hash_table). | |
219 | ||
220 | 2) Perform the data flow analysis for PRE. | |
221 | ||
222 | 3) Delete the redundant instructions | |
223 | ||
224 | 4) Insert the required copies [if any] that make the partially | |
225 | redundant instructions fully redundant. | |
226 | ||
227 | 5) For other reaching expressions, insert an instruction to copy the value | |
228 | to a newly created pseudo that will reach the redundant instruction. | |
229 | ||
230 | The deletion is done first so that when we do insertions we | |
231 | know which pseudo reg to use. | |
232 | ||
233 | Various papers have argued that PRE DFA is expensive (O(n^2)) and others | |
234 | argue it is not. The number of iterations for the algorithm to converge | |
235 | is typically 2-4 so I don't view it as that expensive (relatively speaking). | |
236 | ||
4cad6dba | 237 | PRE GCSE depends heavily on the second CPROP pass to clean up the copies |
7506f491 DE |
238 | we create. To make an expression reach the place where it's redundant, |
239 | the result of the expression is copied to a new register, and the redundant | |
240 | expression is deleted by replacing it with this new register. Classic GCSE | |
241 | doesn't have this problem as much as it computes the reaching defs of | |
a3c28ba2 KH |
242 | each register in each block and thus can try to use an existing |
243 | register. */ | |
7506f491 DE |
244 | \f |
245 | /* GCSE global vars. */ | |
246 | ||
7c6811fe RS |
247 | struct target_gcse default_target_gcse; |
248 | #if SWITCHABLE_TARGET | |
249 | struct target_gcse *this_target_gcse = &default_target_gcse; | |
250 | #endif | |
251 | ||
5f39ad47 SB |
252 | /* Set to non-zero if CSE should run after all GCSE optimizations are done. */ |
253 | int flag_rerun_cse_after_global_opts; | |
f4e584dc | 254 | |
7506f491 DE |
255 | /* An obstack for our working variables. */ |
256 | static struct obstack gcse_obstack; | |
257 | ||
c4c81601 | 258 | struct reg_use {rtx reg_rtx; }; |
abd535b6 | 259 | |
7506f491 DE |
260 | /* Hash table of expressions. */ |
261 | ||
262 | struct expr | |
263 | { | |
43c8a043 | 264 | /* The expression. */ |
7506f491 DE |
265 | rtx expr; |
266 | /* Index in the available expression bitmaps. */ | |
267 | int bitmap_index; | |
268 | /* Next entry with the same hash. */ | |
269 | struct expr *next_same_hash; | |
270 | /* List of anticipatable occurrences in basic blocks in the function. | |
271 | An "anticipatable occurrence" is one that is the first occurrence in the | |
f4e584dc JL |
272 | basic block, the operands are not modified in the basic block prior |
273 | to the occurrence and the output is not used between the start of | |
274 | the block and the occurrence. */ | |
7506f491 DE |
275 | struct occr *antic_occr; |
276 | /* List of available occurrence in basic blocks in the function. | |
277 | An "available occurrence" is one that is the last occurrence in the | |
278 | basic block and the operands are not modified by following statements in | |
279 | the basic block [including this insn]. */ | |
280 | struct occr *avail_occr; | |
281 | /* Non-null if the computation is PRE redundant. | |
282 | The value is the newly created pseudo-reg to record a copy of the | |
283 | expression in all the places that reach the redundant copy. */ | |
284 | rtx reaching_reg; | |
20160347 MK |
285 | /* Maximum distance in instructions this expression can travel. |
286 | We avoid moving simple expressions for more than a few instructions | |
287 | to keep register pressure under control. | |
288 | A value of "0" removes restrictions on how far the expression can | |
289 | travel. */ | |
290 | int max_distance; | |
7506f491 DE |
291 | }; |
292 | ||
293 | /* Occurrence of an expression. | |
294 | There is one per basic block. If a pattern appears more than once the | |
295 | last appearance is used [or first for anticipatable expressions]. */ | |
296 | ||
297 | struct occr | |
298 | { | |
299 | /* Next occurrence of this expression. */ | |
300 | struct occr *next; | |
301 | /* The insn that computes the expression. */ | |
302 | rtx insn; | |
cc2902df | 303 | /* Nonzero if this [anticipatable] occurrence has been deleted. */ |
7506f491 | 304 | char deleted_p; |
cc2902df | 305 | /* Nonzero if this [available] occurrence has been copied to |
7506f491 DE |
306 | reaching_reg. */ |
307 | /* ??? This is mutually exclusive with deleted_p, so they could share | |
308 | the same byte. */ | |
309 | char copied_p; | |
310 | }; | |
311 | ||
cad9aa15 MK |
312 | typedef struct occr *occr_t; |
313 | DEF_VEC_P (occr_t); | |
314 | DEF_VEC_ALLOC_P (occr_t, heap); | |
315 | ||
e45425ec | 316 | /* Expression hash tables. |
7506f491 DE |
317 | Each hash table is an array of buckets. |
318 | ??? It is known that if it were an array of entries, structure elements | |
319 | `next_same_hash' and `bitmap_index' wouldn't be necessary. However, it is | |
320 | not clear whether in the final analysis a sufficient amount of memory would | |
321 | be saved as the size of the available expression bitmaps would be larger | |
322 | [one could build a mapping table without holes afterwards though]. | |
c4c81601 | 323 | Someday I'll perform the computation and figure it out. */ |
7506f491 | 324 | |
7e5487a2 | 325 | struct hash_table_d |
02280659 ZD |
326 | { |
327 | /* The table itself. | |
328 | This is an array of `expr_hash_table_size' elements. */ | |
329 | struct expr **table; | |
330 | ||
331 | /* Size of the hash table, in elements. */ | |
332 | unsigned int size; | |
2e653e39 | 333 | |
02280659 ZD |
334 | /* Number of hash table elements. */ |
335 | unsigned int n_elems; | |
02280659 | 336 | }; |
c4c81601 | 337 | |
02280659 | 338 | /* Expression hash table. */ |
7e5487a2 | 339 | static struct hash_table_d expr_hash_table; |
02280659 | 340 | |
a13d4ebf | 341 | /* This is a list of expressions which are MEMs and will be used by load |
589005ff | 342 | or store motion. |
43c8a043 EB |
343 | Load motion tracks MEMs which aren't killed by anything except itself, |
344 | i.e. loads and stores to a single location. | |
589005ff | 345 | We can then allow movement of these MEM refs with a little special |
a13d4ebf AM |
346 | allowance. (all stores copy the same value to the reaching reg used |
347 | for the loads). This means all values used to store into memory must have | |
43c8a043 | 348 | no side effects so we can re-issue the setter value. */ |
a13d4ebf AM |
349 | |
350 | struct ls_expr | |
351 | { | |
352 | struct expr * expr; /* Gcse expression reference for LM. */ | |
353 | rtx pattern; /* Pattern of this mem. */ | |
47a3dae1 | 354 | rtx pattern_regs; /* List of registers mentioned by the mem. */ |
aaa4ca30 AJ |
355 | rtx loads; /* INSN list of loads seen. */ |
356 | rtx stores; /* INSN list of stores seen. */ | |
a13d4ebf AM |
357 | struct ls_expr * next; /* Next in the list. */ |
358 | int invalid; /* Invalid for some reason. */ | |
359 | int index; /* If it maps to a bitmap index. */ | |
b58b21d5 | 360 | unsigned int hash_index; /* Index when in a hash table. */ |
a13d4ebf AM |
361 | rtx reaching_reg; /* Register to use when re-writing. */ |
362 | }; | |
363 | ||
364 | /* Head of the list of load/store memory refs. */ | |
365 | static struct ls_expr * pre_ldst_mems = NULL; | |
366 | ||
9727e468 RG |
367 | /* Hashtable for the load/store memory refs. */ |
368 | static htab_t pre_ldst_table = NULL; | |
369 | ||
7506f491 DE |
370 | /* Bitmap containing one bit for each register in the program. |
371 | Used when performing GCSE to track which registers have been set since | |
372 | the start of the basic block. */ | |
73991d6a | 373 | static regset reg_set_bitmap; |
7506f491 | 374 | |
a13d4ebf AM |
375 | /* Array, indexed by basic block number for a list of insns which modify |
376 | memory within that block. */ | |
6409abe3 | 377 | static VEC (rtx,heap) **modify_mem_list; |
0516f6fe | 378 | static bitmap modify_mem_list_set; |
a13d4ebf | 379 | |
6ce1edcf NF |
380 | typedef struct modify_pair_s |
381 | { | |
382 | rtx dest; /* A MEM. */ | |
383 | rtx dest_addr; /* The canonical address of `dest'. */ | |
384 | } modify_pair; | |
385 | ||
386 | DEF_VEC_O(modify_pair); | |
387 | DEF_VEC_ALLOC_O(modify_pair,heap); | |
388 | ||
389 | /* This array parallels modify_mem_list, except that it stores MEMs | |
390 | being set and their canonicalized memory addresses. */ | |
6409abe3 | 391 | static VEC (modify_pair,heap) **canon_modify_mem_list; |
0516f6fe | 392 | |
aa47fcfa JL |
393 | /* Bitmap indexed by block numbers to record which blocks contain |
394 | function calls. */ | |
395 | static bitmap blocks_with_calls; | |
396 | ||
7506f491 DE |
397 | /* Various variables for statistics gathering. */ |
398 | ||
399 | /* Memory used in a pass. | |
400 | This isn't intended to be absolutely precise. Its intent is only | |
401 | to keep an eye on memory usage. */ | |
402 | static int bytes_used; | |
c4c81601 | 403 | |
7506f491 DE |
404 | /* GCSE substitutions made. */ |
405 | static int gcse_subst_count; | |
406 | /* Number of copy instructions created. */ | |
407 | static int gcse_create_count; | |
7506f491 | 408 | \f |
20160347 MK |
409 | /* Doing code hoisting. */ |
410 | static bool doing_code_hoisting_p = false; | |
411 | \f | |
e83f4801 | 412 | /* For available exprs */ |
df35c271 | 413 | static sbitmap *ae_kill; |
7506f491 | 414 | \f |
b11f0116 BC |
415 | /* Data stored for each basic block. */ |
416 | struct bb_data | |
417 | { | |
418 | /* Maximal register pressure inside basic block for given register class | |
419 | (defined only for the pressure classes). */ | |
420 | int max_reg_pressure[N_REG_CLASSES]; | |
4b8181c5 BC |
421 | /* Recorded register pressure of basic block before trying to hoist |
422 | an expression. Will be used to restore the register pressure | |
423 | if the expression should not be hoisted. */ | |
424 | int old_pressure; | |
425 | /* Recorded register live_in info of basic block during code hoisting | |
426 | process. BACKUP is used to record live_in info before trying to | |
427 | hoist an expression, and will be used to restore LIVE_IN if the | |
428 | expression should not be hoisted. */ | |
429 | bitmap live_in, backup; | |
b11f0116 BC |
430 | }; |
431 | ||
432 | #define BB_DATA(bb) ((struct bb_data *) (bb)->aux) | |
433 | ||
434 | static basic_block curr_bb; | |
435 | ||
436 | /* Current register pressure for each pressure class. */ | |
437 | static int curr_reg_pressure[N_REG_CLASSES]; | |
438 | \f | |
439 | ||
1d088dee | 440 | static void compute_can_copy (void); |
9fe15a12 KG |
441 | static void *gmalloc (size_t) ATTRIBUTE_MALLOC; |
442 | static void *gcalloc (size_t, size_t) ATTRIBUTE_MALLOC; | |
703ad42b | 443 | static void *gcse_alloc (unsigned long); |
eb232f4e | 444 | static void alloc_gcse_mem (void); |
1d088dee | 445 | static void free_gcse_mem (void); |
7e5487a2 ILT |
446 | static void hash_scan_insn (rtx, struct hash_table_d *); |
447 | static void hash_scan_set (rtx, rtx, struct hash_table_d *); | |
448 | static void hash_scan_clobber (rtx, rtx, struct hash_table_d *); | |
449 | static void hash_scan_call (rtx, rtx, struct hash_table_d *); | |
20160347 | 450 | static int want_to_gcse_p (rtx, int *); |
ed7a4b4b KG |
451 | static int oprs_unchanged_p (const_rtx, const_rtx, int); |
452 | static int oprs_anticipatable_p (const_rtx, const_rtx); | |
453 | static int oprs_available_p (const_rtx, const_rtx); | |
20160347 | 454 | static void insert_expr_in_table (rtx, enum machine_mode, rtx, int, int, int, |
7e5487a2 | 455 | struct hash_table_d *); |
ed7a4b4b | 456 | static unsigned int hash_expr (const_rtx, enum machine_mode, int *, int); |
ed7a4b4b | 457 | static int expr_equiv_p (const_rtx, const_rtx); |
1d088dee AJ |
458 | static void record_last_reg_set_info (rtx, int); |
459 | static void record_last_mem_set_info (rtx); | |
7bc980e1 | 460 | static void record_last_set_info (rtx, const_rtx, void *); |
7e5487a2 | 461 | static void compute_hash_table (struct hash_table_d *); |
e45425ec | 462 | static void alloc_hash_table (struct hash_table_d *); |
7e5487a2 ILT |
463 | static void free_hash_table (struct hash_table_d *); |
464 | static void compute_hash_table_work (struct hash_table_d *); | |
465 | static void dump_hash_table (FILE *, const char *, struct hash_table_d *); | |
e45425ec | 466 | static void compute_transp (const_rtx, int, sbitmap *); |
1d088dee | 467 | static void compute_local_properties (sbitmap *, sbitmap *, sbitmap *, |
7e5487a2 | 468 | struct hash_table_d *); |
7bc980e1 | 469 | static void mems_conflict_for_gcse_p (rtx, const_rtx, void *); |
ed7a4b4b | 470 | static int load_killed_in_block_p (const_basic_block, int, const_rtx, int); |
7bc980e1 | 471 | static void canon_list_insert (rtx, const_rtx, void *); |
1d088dee AJ |
472 | static void alloc_pre_mem (int, int); |
473 | static void free_pre_mem (void); | |
43c8a043 | 474 | static struct edge_list *compute_pre_data (void); |
1d088dee AJ |
475 | static int pre_expr_reaches_here_p (basic_block, struct expr *, |
476 | basic_block); | |
eae7938e | 477 | static void insert_insn_end_basic_block (struct expr *, basic_block); |
1d088dee AJ |
478 | static void pre_insert_copy_insn (struct expr *, rtx); |
479 | static void pre_insert_copies (void); | |
480 | static int pre_delete (void); | |
43c8a043 | 481 | static int pre_gcse (struct edge_list *); |
5f39ad47 | 482 | static int one_pre_gcse_pass (void); |
1d088dee AJ |
483 | static void add_label_notes (rtx, rtx); |
484 | static void alloc_code_hoist_mem (int, int); | |
485 | static void free_code_hoist_mem (void); | |
486 | static void compute_code_hoist_vbeinout (void); | |
487 | static void compute_code_hoist_data (void); | |
b11f0116 BC |
488 | static int should_hoist_expr_to_dom (basic_block, struct expr *, basic_block, |
489 | sbitmap, int, int *, enum reg_class, | |
4b8181c5 | 490 | int *, bitmap, rtx); |
5f39ad47 | 491 | static int hoist_code (void); |
4b8181c5 | 492 | static enum reg_class get_regno_pressure_class (int regno, int *nregs); |
b11f0116 | 493 | static enum reg_class get_pressure_class_and_nregs (rtx insn, int *nregs); |
1d088dee | 494 | static int one_code_hoisting_pass (void); |
1d088dee AJ |
495 | static rtx process_insert_insn (struct expr *); |
496 | static int pre_edge_insert (struct edge_list *, struct expr **); | |
1d088dee AJ |
497 | static int pre_expr_reaches_here_p_work (basic_block, struct expr *, |
498 | basic_block, char *); | |
499 | static struct ls_expr * ldst_entry (rtx); | |
500 | static void free_ldst_entry (struct ls_expr *); | |
43c8a043 | 501 | static void free_ld_motion_mems (void); |
1d088dee AJ |
502 | static void print_ldst_list (FILE *); |
503 | static struct ls_expr * find_rtx_in_ldst (rtx); | |
ed7a4b4b | 504 | static int simple_mem (const_rtx); |
1d088dee AJ |
505 | static void invalidate_any_buried_refs (rtx); |
506 | static void compute_ld_motion_mems (void); | |
507 | static void trim_ld_motion_mems (void); | |
508 | static void update_ld_motion_stores (struct expr *); | |
1d088dee AJ |
509 | static void clear_modify_mem_tables (void); |
510 | static void free_modify_mem_tables (void); | |
511 | static rtx gcse_emit_move_after (rtx, rtx, rtx); | |
d128effb | 512 | static bool is_too_expensive (const char *); |
1b4572a8 KG |
513 | |
514 | #define GNEW(T) ((T *) gmalloc (sizeof (T))) | |
515 | #define GCNEW(T) ((T *) gcalloc (1, sizeof (T))) | |
516 | ||
517 | #define GNEWVEC(T, N) ((T *) gmalloc (sizeof (T) * (N))) | |
518 | #define GCNEWVEC(T, N) ((T *) gcalloc ((N), sizeof (T))) | |
1b4572a8 KG |
519 | |
520 | #define GNEWVAR(T, S) ((T *) gmalloc ((S))) | |
521 | #define GCNEWVAR(T, S) ((T *) gcalloc (1, (S))) | |
1b4572a8 KG |
522 | |
523 | #define GOBNEW(T) ((T *) gcse_alloc (sizeof (T))) | |
524 | #define GOBNEWVAR(T, S) ((T *) gcse_alloc ((S))) | |
7506f491 | 525 | \f |
7506f491 DE |
526 | /* Misc. utilities. */ |
527 | ||
7c6811fe RS |
528 | #define can_copy \ |
529 | (this_target_gcse->x_can_copy) | |
530 | #define can_copy_init_p \ | |
531 | (this_target_gcse->x_can_copy_init_p) | |
773eae39 | 532 | |
7506f491 DE |
533 | /* Compute which modes support reg/reg copy operations. */ |
534 | ||
535 | static void | |
1d088dee | 536 | compute_can_copy (void) |
7506f491 DE |
537 | { |
538 | int i; | |
50b2596f | 539 | #ifndef AVOID_CCMODE_COPIES |
8e42ace1 | 540 | rtx reg, insn; |
50b2596f | 541 | #endif |
773eae39 | 542 | memset (can_copy, 0, NUM_MACHINE_MODES); |
7506f491 DE |
543 | |
544 | start_sequence (); | |
545 | for (i = 0; i < NUM_MACHINE_MODES; i++) | |
c4c81601 RK |
546 | if (GET_MODE_CLASS (i) == MODE_CC) |
547 | { | |
7506f491 | 548 | #ifdef AVOID_CCMODE_COPIES |
773eae39 | 549 | can_copy[i] = 0; |
7506f491 | 550 | #else |
c4c81601 RK |
551 | reg = gen_rtx_REG ((enum machine_mode) i, LAST_VIRTUAL_REGISTER + 1); |
552 | insn = emit_insn (gen_rtx_SET (VOIDmode, reg, reg)); | |
9714cf43 | 553 | if (recog (PATTERN (insn), insn, NULL) >= 0) |
773eae39 | 554 | can_copy[i] = 1; |
7506f491 | 555 | #endif |
c4c81601 | 556 | } |
141b5810 | 557 | else |
773eae39 | 558 | can_copy[i] = 1; |
c4c81601 | 559 | |
7506f491 | 560 | end_sequence (); |
7506f491 | 561 | } |
773eae39 EB |
562 | |
563 | /* Returns whether the mode supports reg/reg copy operations. */ | |
564 | ||
565 | bool | |
1d088dee | 566 | can_copy_p (enum machine_mode mode) |
773eae39 | 567 | { |
773eae39 EB |
568 | if (! can_copy_init_p) |
569 | { | |
570 | compute_can_copy (); | |
571 | can_copy_init_p = true; | |
572 | } | |
573 | ||
574 | return can_copy[mode] != 0; | |
575 | } | |
7506f491 DE |
576 | \f |
577 | /* Cover function to xmalloc to record bytes allocated. */ | |
578 | ||
703ad42b | 579 | static void * |
4ac11022 | 580 | gmalloc (size_t size) |
7506f491 DE |
581 | { |
582 | bytes_used += size; | |
583 | return xmalloc (size); | |
584 | } | |
585 | ||
9fe15a12 KG |
586 | /* Cover function to xcalloc to record bytes allocated. */ |
587 | ||
588 | static void * | |
589 | gcalloc (size_t nelem, size_t elsize) | |
590 | { | |
591 | bytes_used += nelem * elsize; | |
592 | return xcalloc (nelem, elsize); | |
593 | } | |
594 | ||
77bbd421 | 595 | /* Cover function to obstack_alloc. */ |
7506f491 | 596 | |
703ad42b | 597 | static void * |
1d088dee | 598 | gcse_alloc (unsigned long size) |
7506f491 | 599 | { |
77bbd421 | 600 | bytes_used += size; |
703ad42b | 601 | return obstack_alloc (&gcse_obstack, size); |
7506f491 DE |
602 | } |
603 | ||
4a81774c | 604 | /* Allocate memory for the reg/memory set tracking tables. |
7506f491 DE |
605 | This is called at the start of each pass. */ |
606 | ||
607 | static void | |
eb232f4e | 608 | alloc_gcse_mem (void) |
7506f491 | 609 | { |
7506f491 | 610 | /* Allocate vars to track sets of regs. */ |
7a8cba34 | 611 | reg_set_bitmap = ALLOC_REG_SET (NULL); |
7506f491 | 612 | |
a13d4ebf AM |
613 | /* Allocate array to keep a list of insns which modify memory in each |
614 | basic block. */ | |
6409abe3 NF |
615 | modify_mem_list = GCNEWVEC (VEC (rtx,heap) *, last_basic_block); |
616 | canon_modify_mem_list = GCNEWVEC (VEC (modify_pair,heap) *, | |
6ce1edcf | 617 | last_basic_block); |
8bdbfff5 NS |
618 | modify_mem_list_set = BITMAP_ALLOC (NULL); |
619 | blocks_with_calls = BITMAP_ALLOC (NULL); | |
7506f491 DE |
620 | } |
621 | ||
622 | /* Free memory allocated by alloc_gcse_mem. */ | |
623 | ||
624 | static void | |
1d088dee | 625 | free_gcse_mem (void) |
7506f491 | 626 | { |
d5b8da97 SB |
627 | FREE_REG_SET (reg_set_bitmap); |
628 | ||
73991d6a | 629 | free_modify_mem_tables (); |
8bdbfff5 NS |
630 | BITMAP_FREE (modify_mem_list_set); |
631 | BITMAP_FREE (blocks_with_calls); | |
7506f491 | 632 | } |
b5ce41ff JL |
633 | \f |
634 | /* Compute the local properties of each recorded expression. | |
c4c81601 RK |
635 | |
636 | Local properties are those that are defined by the block, irrespective of | |
637 | other blocks. | |
b5ce41ff JL |
638 | |
639 | An expression is transparent in a block if its operands are not modified | |
640 | in the block. | |
641 | ||
642 | An expression is computed (locally available) in a block if it is computed | |
643 | at least once and expression would contain the same value if the | |
644 | computation was moved to the end of the block. | |
645 | ||
646 | An expression is locally anticipatable in a block if it is computed at | |
647 | least once and expression would contain the same value if the computation | |
648 | was moved to the beginning of the block. | |
649 | ||
e45425ec | 650 | We call this routine for pre and code hoisting. They all compute |
c4c81601 | 651 | basically the same information and thus can easily share this code. |
7506f491 | 652 | |
c4c81601 RK |
653 | TRANSP, COMP, and ANTLOC are destination sbitmaps for recording local |
654 | properties. If NULL, then it is not necessary to compute or record that | |
655 | particular property. | |
b5ce41ff | 656 | |
e45425ec | 657 | TABLE controls which hash table to look at. */ |
589005ff | 658 | |
b5ce41ff | 659 | static void |
7b1b4aed | 660 | compute_local_properties (sbitmap *transp, sbitmap *comp, sbitmap *antloc, |
7e5487a2 | 661 | struct hash_table_d *table) |
b5ce41ff | 662 | { |
02280659 | 663 | unsigned int i; |
589005ff | 664 | |
b5ce41ff JL |
665 | /* Initialize any bitmaps that were passed in. */ |
666 | if (transp) | |
695ab36a | 667 | { |
f61e445a | 668 | bitmap_vector_ones (transp, last_basic_block); |
695ab36a | 669 | } |
c4c81601 | 670 | |
b5ce41ff | 671 | if (comp) |
f61e445a | 672 | bitmap_vector_clear (comp, last_basic_block); |
b5ce41ff | 673 | if (antloc) |
f61e445a | 674 | bitmap_vector_clear (antloc, last_basic_block); |
b5ce41ff | 675 | |
02280659 | 676 | for (i = 0; i < table->size; i++) |
7506f491 | 677 | { |
b5ce41ff JL |
678 | struct expr *expr; |
679 | ||
02280659 | 680 | for (expr = table->table[i]; expr != NULL; expr = expr->next_same_hash) |
b5ce41ff | 681 | { |
b5ce41ff | 682 | int indx = expr->bitmap_index; |
c4c81601 | 683 | struct occr *occr; |
b5ce41ff JL |
684 | |
685 | /* The expression is transparent in this block if it is not killed. | |
686 | We start by assuming all are transparent [none are killed], and | |
687 | then reset the bits for those that are. */ | |
b5ce41ff | 688 | if (transp) |
e45425ec | 689 | compute_transp (expr->expr, indx, transp); |
b5ce41ff JL |
690 | |
691 | /* The occurrences recorded in antic_occr are exactly those that | |
cc2902df | 692 | we want to set to nonzero in ANTLOC. */ |
b5ce41ff | 693 | if (antloc) |
c4c81601 RK |
694 | for (occr = expr->antic_occr; occr != NULL; occr = occr->next) |
695 | { | |
d7c028c0 | 696 | bitmap_set_bit (antloc[BLOCK_FOR_INSN (occr->insn)->index], indx); |
b5ce41ff | 697 | |
c4c81601 RK |
698 | /* While we're scanning the table, this is a good place to |
699 | initialize this. */ | |
700 | occr->deleted_p = 0; | |
701 | } | |
b5ce41ff JL |
702 | |
703 | /* The occurrences recorded in avail_occr are exactly those that | |
cc2902df | 704 | we want to set to nonzero in COMP. */ |
b5ce41ff | 705 | if (comp) |
c4c81601 RK |
706 | for (occr = expr->avail_occr; occr != NULL; occr = occr->next) |
707 | { | |
d7c028c0 | 708 | bitmap_set_bit (comp[BLOCK_FOR_INSN (occr->insn)->index], indx); |
b5ce41ff | 709 | |
c4c81601 RK |
710 | /* While we're scanning the table, this is a good place to |
711 | initialize this. */ | |
712 | occr->copied_p = 0; | |
713 | } | |
b5ce41ff JL |
714 | |
715 | /* While we're scanning the table, this is a good place to | |
716 | initialize this. */ | |
717 | expr->reaching_reg = 0; | |
718 | } | |
7506f491 | 719 | } |
7506f491 DE |
720 | } |
721 | \f | |
7506f491 DE |
722 | /* Hash table support. */ |
723 | ||
80c29cc4 RZ |
724 | struct reg_avail_info |
725 | { | |
e0082a72 | 726 | basic_block last_bb; |
80c29cc4 RZ |
727 | int first_set; |
728 | int last_set; | |
729 | }; | |
730 | ||
731 | static struct reg_avail_info *reg_avail_info; | |
e0082a72 | 732 | static basic_block current_bb; |
7506f491 | 733 | |
fb0c0a12 RK |
734 | /* See whether X, the source of a set, is something we want to consider for |
735 | GCSE. */ | |
7506f491 DE |
736 | |
737 | static int | |
20160347 | 738 | want_to_gcse_p (rtx x, int *max_distance_ptr) |
7506f491 | 739 | { |
3d8504ac RS |
740 | #ifdef STACK_REGS |
741 | /* On register stack architectures, don't GCSE constants from the | |
742 | constant pool, as the benefits are often swamped by the overhead | |
743 | of shuffling the register stack between basic blocks. */ | |
744 | if (IS_STACK_MODE (GET_MODE (x))) | |
745 | x = avoid_constant_pool_reference (x); | |
746 | #endif | |
747 | ||
20160347 MK |
748 | /* GCSE'ing constants: |
749 | ||
750 | We do not specifically distinguish between constant and non-constant | |
5e8f01f4 | 751 | expressions in PRE and Hoist. We use set_src_cost below to limit |
20160347 MK |
752 | the maximum distance simple expressions can travel. |
753 | ||
754 | Nevertheless, constants are much easier to GCSE, and, hence, | |
755 | it is easy to overdo the optimizations. Usually, excessive PRE and | |
756 | Hoisting of constant leads to increased register pressure. | |
757 | ||
758 | RA can deal with this by rematerialing some of the constants. | |
759 | Therefore, it is important that the back-end generates sets of constants | |
760 | in a way that allows reload rematerialize them under high register | |
761 | pressure, i.e., a pseudo register with REG_EQUAL to constant | |
762 | is set only once. Failing to do so will result in IRA/reload | |
763 | spilling such constants under high register pressure instead of | |
764 | rematerializing them. */ | |
765 | ||
c4c81601 | 766 | switch (GET_CODE (x)) |
7506f491 DE |
767 | { |
768 | case REG: | |
769 | case SUBREG: | |
20160347 MK |
770 | case CALL: |
771 | return 0; | |
772 | ||
d8116890 | 773 | CASE_CONST_ANY: |
20160347 MK |
774 | if (!doing_code_hoisting_p) |
775 | /* Do not PRE constants. */ | |
776 | return 0; | |
777 | ||
778 | /* FALLTHRU */ | |
7506f491 DE |
779 | |
780 | default: | |
20160347 MK |
781 | if (doing_code_hoisting_p) |
782 | /* PRE doesn't implement max_distance restriction. */ | |
783 | { | |
784 | int cost; | |
785 | int max_distance; | |
786 | ||
787 | gcc_assert (!optimize_function_for_speed_p (cfun) | |
788 | && optimize_function_for_size_p (cfun)); | |
5e8f01f4 | 789 | cost = set_src_cost (x, 0); |
20160347 MK |
790 | |
791 | if (cost < COSTS_N_INSNS (GCSE_UNRESTRICTED_COST)) | |
792 | { | |
793 | max_distance = (GCSE_COST_DISTANCE_RATIO * cost) / 10; | |
794 | if (max_distance == 0) | |
795 | return 0; | |
796 | ||
797 | gcc_assert (max_distance > 0); | |
798 | } | |
799 | else | |
800 | max_distance = 0; | |
801 | ||
802 | if (max_distance_ptr) | |
803 | *max_distance_ptr = max_distance; | |
804 | } | |
805 | ||
df35c271 | 806 | return can_assign_to_reg_without_clobbers_p (x); |
7506f491 | 807 | } |
1707bafa RS |
808 | } |
809 | ||
df35c271 | 810 | /* Used internally by can_assign_to_reg_without_clobbers_p. */ |
1707bafa RS |
811 | |
812 | static GTY(()) rtx test_insn; | |
813 | ||
df35c271 SB |
814 | /* Return true if we can assign X to a pseudo register such that the |
815 | resulting insn does not result in clobbering a hard register as a | |
816 | side-effect. | |
ec0a1343 JB |
817 | |
818 | Additionally, if the target requires it, check that the resulting insn | |
819 | can be copied. If it cannot, this means that X is special and probably | |
820 | has hidden side-effects we don't want to mess with. | |
821 | ||
df35c271 SB |
822 | This function is typically used by code motion passes, to verify |
823 | that it is safe to insert an insn without worrying about clobbering | |
824 | maybe live hard regs. */ | |
1707bafa | 825 | |
df35c271 SB |
826 | bool |
827 | can_assign_to_reg_without_clobbers_p (rtx x) | |
1707bafa RS |
828 | { |
829 | int num_clobbers = 0; | |
830 | int icode; | |
7506f491 | 831 | |
fb0c0a12 RK |
832 | /* If this is a valid operand, we are OK. If it's VOIDmode, we aren't. */ |
833 | if (general_operand (x, GET_MODE (x))) | |
834 | return 1; | |
835 | else if (GET_MODE (x) == VOIDmode) | |
836 | return 0; | |
837 | ||
838 | /* Otherwise, check if we can make a valid insn from it. First initialize | |
839 | our test insn if we haven't already. */ | |
840 | if (test_insn == 0) | |
841 | { | |
842 | test_insn | |
843 | = make_insn_raw (gen_rtx_SET (VOIDmode, | |
844 | gen_rtx_REG (word_mode, | |
845 | FIRST_PSEUDO_REGISTER * 2), | |
846 | const0_rtx)); | |
847 | NEXT_INSN (test_insn) = PREV_INSN (test_insn) = 0; | |
fb0c0a12 RK |
848 | } |
849 | ||
850 | /* Now make an insn like the one we would make when GCSE'ing and see if | |
851 | valid. */ | |
852 | PUT_MODE (SET_DEST (PATTERN (test_insn)), GET_MODE (x)); | |
853 | SET_SRC (PATTERN (test_insn)) = x; | |
b8698a0f | 854 | |
ec0a1343 JB |
855 | icode = recog (PATTERN (test_insn), test_insn, &num_clobbers); |
856 | if (icode < 0) | |
857 | return false; | |
b8698a0f | 858 | |
ec0a1343 JB |
859 | if (num_clobbers > 0 && added_clobbers_hard_reg_p (icode)) |
860 | return false; | |
b8698a0f | 861 | |
ec0a1343 JB |
862 | if (targetm.cannot_copy_insn_p && targetm.cannot_copy_insn_p (test_insn)) |
863 | return false; | |
b8698a0f | 864 | |
ec0a1343 | 865 | return true; |
7506f491 DE |
866 | } |
867 | ||
cc2902df | 868 | /* Return nonzero if the operands of expression X are unchanged from the |
7506f491 DE |
869 | start of INSN's basic block up to but not including INSN (if AVAIL_P == 0), |
870 | or from INSN to the end of INSN's basic block (if AVAIL_P != 0). */ | |
871 | ||
872 | static int | |
ed7a4b4b | 873 | oprs_unchanged_p (const_rtx x, const_rtx insn, int avail_p) |
7506f491 | 874 | { |
c4c81601 | 875 | int i, j; |
7506f491 | 876 | enum rtx_code code; |
6f7d635c | 877 | const char *fmt; |
7506f491 | 878 | |
7506f491 DE |
879 | if (x == 0) |
880 | return 1; | |
881 | ||
882 | code = GET_CODE (x); | |
883 | switch (code) | |
884 | { | |
885 | case REG: | |
80c29cc4 RZ |
886 | { |
887 | struct reg_avail_info *info = ®_avail_info[REGNO (x)]; | |
888 | ||
889 | if (info->last_bb != current_bb) | |
890 | return 1; | |
589005ff | 891 | if (avail_p) |
4a81774c | 892 | return info->last_set < DF_INSN_LUID (insn); |
80c29cc4 | 893 | else |
4a81774c | 894 | return info->first_set >= DF_INSN_LUID (insn); |
80c29cc4 | 895 | } |
7506f491 DE |
896 | |
897 | case MEM: | |
4a81774c | 898 | if (load_killed_in_block_p (current_bb, DF_INSN_LUID (insn), |
a13d4ebf AM |
899 | x, avail_p)) |
900 | return 0; | |
7506f491 | 901 | else |
c4c81601 | 902 | return oprs_unchanged_p (XEXP (x, 0), insn, avail_p); |
7506f491 DE |
903 | |
904 | case PRE_DEC: | |
905 | case PRE_INC: | |
906 | case POST_DEC: | |
907 | case POST_INC: | |
4b983fdc RH |
908 | case PRE_MODIFY: |
909 | case POST_MODIFY: | |
7506f491 DE |
910 | return 0; |
911 | ||
912 | case PC: | |
913 | case CC0: /*FIXME*/ | |
914 | case CONST: | |
d8116890 | 915 | CASE_CONST_ANY: |
7506f491 DE |
916 | case SYMBOL_REF: |
917 | case LABEL_REF: | |
918 | case ADDR_VEC: | |
919 | case ADDR_DIFF_VEC: | |
920 | return 1; | |
921 | ||
922 | default: | |
923 | break; | |
924 | } | |
925 | ||
c4c81601 | 926 | for (i = GET_RTX_LENGTH (code) - 1, fmt = GET_RTX_FORMAT (code); i >= 0; i--) |
7506f491 DE |
927 | { |
928 | if (fmt[i] == 'e') | |
929 | { | |
c4c81601 RK |
930 | /* If we are about to do the last recursive call needed at this |
931 | level, change it into iteration. This function is called enough | |
932 | to be worth it. */ | |
7506f491 | 933 | if (i == 0) |
c4c81601 RK |
934 | return oprs_unchanged_p (XEXP (x, i), insn, avail_p); |
935 | ||
936 | else if (! oprs_unchanged_p (XEXP (x, i), insn, avail_p)) | |
7506f491 DE |
937 | return 0; |
938 | } | |
939 | else if (fmt[i] == 'E') | |
c4c81601 RK |
940 | for (j = 0; j < XVECLEN (x, i); j++) |
941 | if (! oprs_unchanged_p (XVECEXP (x, i, j), insn, avail_p)) | |
942 | return 0; | |
7506f491 DE |
943 | } |
944 | ||
945 | return 1; | |
946 | } | |
947 | ||
43c8a043 | 948 | /* Info passed from load_killed_in_block_p to mems_conflict_for_gcse_p. */ |
a13d4ebf | 949 | |
43c8a043 EB |
950 | struct mem_conflict_info |
951 | { | |
952 | /* A memory reference for a load instruction, mems_conflict_for_gcse_p will | |
953 | see if a memory store conflicts with this memory load. */ | |
954 | const_rtx mem; | |
a13d4ebf | 955 | |
43c8a043 EB |
956 | /* True if mems_conflict_for_gcse_p finds a conflict between two memory |
957 | references. */ | |
958 | bool conflict; | |
959 | }; | |
960 | ||
961 | /* DEST is the output of an instruction. If it is a memory reference and | |
962 | possibly conflicts with the load found in DATA, then communicate this | |
963 | information back through DATA. */ | |
a13d4ebf AM |
964 | |
965 | static void | |
7bc980e1 | 966 | mems_conflict_for_gcse_p (rtx dest, const_rtx setter ATTRIBUTE_UNUSED, |
43c8a043 | 967 | void *data) |
a13d4ebf | 968 | { |
43c8a043 EB |
969 | struct mem_conflict_info *mci = (struct mem_conflict_info *) data; |
970 | ||
a13d4ebf AM |
971 | while (GET_CODE (dest) == SUBREG |
972 | || GET_CODE (dest) == ZERO_EXTRACT | |
a13d4ebf AM |
973 | || GET_CODE (dest) == STRICT_LOW_PART) |
974 | dest = XEXP (dest, 0); | |
975 | ||
976 | /* If DEST is not a MEM, then it will not conflict with the load. Note | |
977 | that function calls are assumed to clobber memory, but are handled | |
978 | elsewhere. */ | |
7b1b4aed | 979 | if (! MEM_P (dest)) |
a13d4ebf | 980 | return; |
aaa4ca30 | 981 | |
a13d4ebf | 982 | /* If we are setting a MEM in our list of specially recognized MEMs, |
589005ff | 983 | don't mark as killed this time. */ |
43c8a043 | 984 | if (pre_ldst_mems != NULL && expr_equiv_p (dest, mci->mem)) |
a13d4ebf AM |
985 | { |
986 | if (!find_rtx_in_ldst (dest)) | |
43c8a043 | 987 | mci->conflict = true; |
a13d4ebf AM |
988 | return; |
989 | } | |
aaa4ca30 | 990 | |
53d9622b | 991 | if (true_dependence (dest, GET_MODE (dest), mci->mem)) |
43c8a043 | 992 | mci->conflict = true; |
a13d4ebf AM |
993 | } |
994 | ||
995 | /* Return nonzero if the expression in X (a memory reference) is killed | |
4a81774c | 996 | in block BB before or after the insn with the LUID in UID_LIMIT. |
a13d4ebf AM |
997 | AVAIL_P is nonzero for kills after UID_LIMIT, and zero for kills |
998 | before UID_LIMIT. | |
999 | ||
1000 | To check the entire block, set UID_LIMIT to max_uid + 1 and | |
1001 | AVAIL_P to 0. */ | |
1002 | ||
1003 | static int | |
43c8a043 EB |
1004 | load_killed_in_block_p (const_basic_block bb, int uid_limit, const_rtx x, |
1005 | int avail_p) | |
a13d4ebf | 1006 | { |
6409abe3 NF |
1007 | VEC (rtx,heap) *list = modify_mem_list[bb->index]; |
1008 | rtx setter; | |
1009 | unsigned ix; | |
16c5b95d MH |
1010 | |
1011 | /* If this is a readonly then we aren't going to be changing it. */ | |
1012 | if (MEM_READONLY_P (x)) | |
1013 | return 0; | |
1014 | ||
6409abe3 | 1015 | FOR_EACH_VEC_ELT_REVERSE (rtx, list, ix, setter) |
a13d4ebf | 1016 | { |
43c8a043 EB |
1017 | struct mem_conflict_info mci; |
1018 | ||
a13d4ebf AM |
1019 | /* Ignore entries in the list that do not apply. */ |
1020 | if ((avail_p | |
6409abe3 | 1021 | && DF_INSN_LUID (setter) < uid_limit) |
a13d4ebf | 1022 | || (! avail_p |
6409abe3 NF |
1023 | && DF_INSN_LUID (setter) > uid_limit)) |
1024 | continue; | |
a13d4ebf AM |
1025 | |
1026 | /* If SETTER is a call everything is clobbered. Note that calls | |
1027 | to pure functions are never put on the list, so we need not | |
1028 | worry about them. */ | |
7b1b4aed | 1029 | if (CALL_P (setter)) |
a13d4ebf AM |
1030 | return 1; |
1031 | ||
1032 | /* SETTER must be an INSN of some kind that sets memory. Call | |
43c8a043 EB |
1033 | note_stores to examine each hunk of memory that is modified. */ |
1034 | mci.mem = x; | |
1035 | mci.conflict = false; | |
1036 | note_stores (PATTERN (setter), mems_conflict_for_gcse_p, &mci); | |
1037 | if (mci.conflict) | |
a13d4ebf | 1038 | return 1; |
a13d4ebf AM |
1039 | } |
1040 | return 0; | |
1041 | } | |
1042 | ||
cc2902df | 1043 | /* Return nonzero if the operands of expression X are unchanged from |
7506f491 DE |
1044 | the start of INSN's basic block up to but not including INSN. */ |
1045 | ||
1046 | static int | |
ed7a4b4b | 1047 | oprs_anticipatable_p (const_rtx x, const_rtx insn) |
7506f491 DE |
1048 | { |
1049 | return oprs_unchanged_p (x, insn, 0); | |
1050 | } | |
1051 | ||
cc2902df | 1052 | /* Return nonzero if the operands of expression X are unchanged from |
7506f491 DE |
1053 | INSN to the end of INSN's basic block. */ |
1054 | ||
1055 | static int | |
ed7a4b4b | 1056 | oprs_available_p (const_rtx x, const_rtx insn) |
7506f491 DE |
1057 | { |
1058 | return oprs_unchanged_p (x, insn, 1); | |
1059 | } | |
1060 | ||
1061 | /* Hash expression X. | |
c4c81601 RK |
1062 | |
1063 | MODE is only used if X is a CONST_INT. DO_NOT_RECORD_P is a boolean | |
1064 | indicating if a volatile operand is found or if the expression contains | |
b58b21d5 | 1065 | something we don't want to insert in the table. HASH_TABLE_SIZE is |
0516f6fe | 1066 | the current size of the hash table to be probed. */ |
7506f491 DE |
1067 | |
1068 | static unsigned int | |
ed7a4b4b | 1069 | hash_expr (const_rtx x, enum machine_mode mode, int *do_not_record_p, |
b58b21d5 | 1070 | int hash_table_size) |
7506f491 DE |
1071 | { |
1072 | unsigned int hash; | |
1073 | ||
1074 | *do_not_record_p = 0; | |
1075 | ||
43c8a043 | 1076 | hash = hash_rtx (x, mode, do_not_record_p, NULL, /*have_reg_qty=*/false); |
7506f491 DE |
1077 | return hash % hash_table_size; |
1078 | } | |
172890a2 | 1079 | |
0516f6fe | 1080 | /* Return nonzero if exp1 is equivalent to exp2. */ |
7506f491 DE |
1081 | |
1082 | static int | |
ed7a4b4b | 1083 | expr_equiv_p (const_rtx x, const_rtx y) |
7506f491 | 1084 | { |
0516f6fe | 1085 | return exp_equiv_p (x, y, 0, true); |
7506f491 DE |
1086 | } |
1087 | ||
02280659 | 1088 | /* Insert expression X in INSN in the hash TABLE. |
7506f491 DE |
1089 | If it is already present, record it as the last occurrence in INSN's |
1090 | basic block. | |
1091 | ||
1092 | MODE is the mode of the value X is being stored into. | |
1093 | It is only used if X is a CONST_INT. | |
1094 | ||
cc2902df | 1095 | ANTIC_P is nonzero if X is an anticipatable expression. |
20160347 MK |
1096 | AVAIL_P is nonzero if X is an available expression. |
1097 | ||
1098 | MAX_DISTANCE is the maximum distance in instructions this expression can | |
1099 | be moved. */ | |
7506f491 DE |
1100 | |
1101 | static void | |
1d088dee | 1102 | insert_expr_in_table (rtx x, enum machine_mode mode, rtx insn, int antic_p, |
20160347 | 1103 | int avail_p, int max_distance, struct hash_table_d *table) |
7506f491 DE |
1104 | { |
1105 | int found, do_not_record_p; | |
1106 | unsigned int hash; | |
1107 | struct expr *cur_expr, *last_expr = NULL; | |
1108 | struct occr *antic_occr, *avail_occr; | |
7506f491 | 1109 | |
02280659 | 1110 | hash = hash_expr (x, mode, &do_not_record_p, table->size); |
7506f491 DE |
1111 | |
1112 | /* Do not insert expression in table if it contains volatile operands, | |
1113 | or if hash_expr determines the expression is something we don't want | |
1114 | to or can't handle. */ | |
1115 | if (do_not_record_p) | |
1116 | return; | |
1117 | ||
02280659 | 1118 | cur_expr = table->table[hash]; |
7506f491 DE |
1119 | found = 0; |
1120 | ||
c4c81601 | 1121 | while (cur_expr && 0 == (found = expr_equiv_p (cur_expr->expr, x))) |
7506f491 DE |
1122 | { |
1123 | /* If the expression isn't found, save a pointer to the end of | |
1124 | the list. */ | |
1125 | last_expr = cur_expr; | |
1126 | cur_expr = cur_expr->next_same_hash; | |
1127 | } | |
1128 | ||
1129 | if (! found) | |
1130 | { | |
1b4572a8 | 1131 | cur_expr = GOBNEW (struct expr); |
7506f491 | 1132 | bytes_used += sizeof (struct expr); |
02280659 | 1133 | if (table->table[hash] == NULL) |
c4c81601 | 1134 | /* This is the first pattern that hashed to this index. */ |
02280659 | 1135 | table->table[hash] = cur_expr; |
7506f491 | 1136 | else |
c4c81601 RK |
1137 | /* Add EXPR to end of this hash chain. */ |
1138 | last_expr->next_same_hash = cur_expr; | |
1139 | ||
589005ff | 1140 | /* Set the fields of the expr element. */ |
7506f491 | 1141 | cur_expr->expr = x; |
02280659 | 1142 | cur_expr->bitmap_index = table->n_elems++; |
7506f491 DE |
1143 | cur_expr->next_same_hash = NULL; |
1144 | cur_expr->antic_occr = NULL; | |
1145 | cur_expr->avail_occr = NULL; | |
20160347 MK |
1146 | gcc_assert (max_distance >= 0); |
1147 | cur_expr->max_distance = max_distance; | |
7506f491 | 1148 | } |
20160347 MK |
1149 | else |
1150 | gcc_assert (cur_expr->max_distance == max_distance); | |
7506f491 DE |
1151 | |
1152 | /* Now record the occurrence(s). */ | |
7506f491 DE |
1153 | if (antic_p) |
1154 | { | |
1155 | antic_occr = cur_expr->antic_occr; | |
1156 | ||
b0de17ef SB |
1157 | if (antic_occr |
1158 | && BLOCK_FOR_INSN (antic_occr->insn) != BLOCK_FOR_INSN (insn)) | |
b6e47ceb | 1159 | antic_occr = NULL; |
7506f491 DE |
1160 | |
1161 | if (antic_occr) | |
c4c81601 RK |
1162 | /* Found another instance of the expression in the same basic block. |
1163 | Prefer the currently recorded one. We want the first one in the | |
1164 | block and the block is scanned from start to end. */ | |
1165 | ; /* nothing to do */ | |
7506f491 DE |
1166 | else |
1167 | { | |
1168 | /* First occurrence of this expression in this basic block. */ | |
1b4572a8 | 1169 | antic_occr = GOBNEW (struct occr); |
7506f491 | 1170 | bytes_used += sizeof (struct occr); |
7506f491 | 1171 | antic_occr->insn = insn; |
b6e47ceb | 1172 | antic_occr->next = cur_expr->antic_occr; |
f9957958 | 1173 | antic_occr->deleted_p = 0; |
b6e47ceb | 1174 | cur_expr->antic_occr = antic_occr; |
7506f491 DE |
1175 | } |
1176 | } | |
1177 | ||
1178 | if (avail_p) | |
1179 | { | |
1180 | avail_occr = cur_expr->avail_occr; | |
1181 | ||
b0de17ef SB |
1182 | if (avail_occr |
1183 | && BLOCK_FOR_INSN (avail_occr->insn) == BLOCK_FOR_INSN (insn)) | |
7506f491 | 1184 | { |
b6e47ceb JL |
1185 | /* Found another instance of the expression in the same basic block. |
1186 | Prefer this occurrence to the currently recorded one. We want | |
1187 | the last one in the block and the block is scanned from start | |
1188 | to end. */ | |
1189 | avail_occr->insn = insn; | |
7506f491 | 1190 | } |
7506f491 DE |
1191 | else |
1192 | { | |
1193 | /* First occurrence of this expression in this basic block. */ | |
1b4572a8 | 1194 | avail_occr = GOBNEW (struct occr); |
7506f491 | 1195 | bytes_used += sizeof (struct occr); |
7506f491 | 1196 | avail_occr->insn = insn; |
b6e47ceb | 1197 | avail_occr->next = cur_expr->avail_occr; |
f9957958 | 1198 | avail_occr->deleted_p = 0; |
b6e47ceb | 1199 | cur_expr->avail_occr = avail_occr; |
7506f491 DE |
1200 | } |
1201 | } | |
1202 | } | |
1203 | ||
43c8a043 | 1204 | /* Scan SET present in INSN and add an entry to the hash TABLE. */ |
7506f491 DE |
1205 | |
1206 | static void | |
43c8a043 | 1207 | hash_scan_set (rtx set, rtx insn, struct hash_table_d *table) |
7506f491 | 1208 | { |
43c8a043 EB |
1209 | rtx src = SET_SRC (set); |
1210 | rtx dest = SET_DEST (set); | |
172890a2 | 1211 | rtx note; |
7506f491 | 1212 | |
6e72d1e9 | 1213 | if (GET_CODE (src) == CALL) |
02280659 | 1214 | hash_scan_call (src, insn, table); |
7506f491 | 1215 | |
7b1b4aed | 1216 | else if (REG_P (dest)) |
7506f491 | 1217 | { |
172890a2 | 1218 | unsigned int regno = REGNO (dest); |
20160347 | 1219 | int max_distance = 0; |
7506f491 | 1220 | |
29470771 SB |
1221 | /* See if a REG_EQUAL note shows this equivalent to a simpler expression. |
1222 | ||
90631280 PB |
1223 | This allows us to do a single GCSE pass and still eliminate |
1224 | redundant constants, addresses or other expressions that are | |
29470771 SB |
1225 | constructed with multiple instructions. |
1226 | ||
e45425ec | 1227 | However, keep the original SRC if INSN is a simple reg-reg move. |
29470771 SB |
1228 | In this case, there will almost always be a REG_EQUAL note on the |
1229 | insn that sets SRC. By recording the REG_EQUAL value here as SRC | |
1230 | for INSN, we miss copy propagation opportunities and we perform the | |
1231 | same PRE GCSE operation repeatedly on the same REG_EQUAL value if we | |
1232 | do more than one PRE GCSE pass. | |
1233 | ||
fa10beec | 1234 | Note that this does not impede profitable constant propagations. We |
29470771 | 1235 | "look through" reg-reg sets in lookup_avail_set. */ |
90631280 PB |
1236 | note = find_reg_equal_equiv_note (insn); |
1237 | if (note != 0 | |
29470771 SB |
1238 | && REG_NOTE_KIND (note) == REG_EQUAL |
1239 | && !REG_P (src) | |
e45425ec | 1240 | && want_to_gcse_p (XEXP (note, 0), NULL)) |
43c8a043 | 1241 | src = XEXP (note, 0), set = gen_rtx_SET (VOIDmode, dest, src); |
172890a2 | 1242 | |
7506f491 | 1243 | /* Only record sets of pseudo-regs in the hash table. */ |
e45425ec | 1244 | if (regno >= FIRST_PSEUDO_REGISTER |
7506f491 | 1245 | /* Don't GCSE something if we can't do a reg/reg copy. */ |
773eae39 | 1246 | && can_copy_p (GET_MODE (dest)) |
068473ec | 1247 | /* GCSE commonly inserts instruction after the insn. We can't |
1d65f45c RH |
1248 | do that easily for EH edges so disable GCSE on these for now. */ |
1249 | /* ??? We can now easily create new EH landing pads at the | |
1250 | gimple level, for splitting edges; there's no reason we | |
1251 | can't do the same thing at the rtl level. */ | |
1252 | && !can_throw_internal (insn) | |
7506f491 | 1253 | /* Is SET_SRC something we want to gcse? */ |
20160347 | 1254 | && want_to_gcse_p (src, &max_distance) |
172890a2 | 1255 | /* Don't CSE a nop. */ |
43c8a043 | 1256 | && ! set_noop_p (set) |
43e72072 JJ |
1257 | /* Don't GCSE if it has attached REG_EQUIV note. |
1258 | At this point this only function parameters should have | |
1259 | REG_EQUIV notes and if the argument slot is used somewhere | |
a1f300c0 | 1260 | explicitly, it means address of parameter has been taken, |
43e72072 | 1261 | so we should not extend the lifetime of the pseudo. */ |
90631280 | 1262 | && (note == NULL_RTX || ! MEM_P (XEXP (note, 0)))) |
7506f491 DE |
1263 | { |
1264 | /* An expression is not anticipatable if its operands are | |
52d76e11 | 1265 | modified before this insn or if this is not the only SET in |
6fb5fa3c DB |
1266 | this insn. The latter condition does not have to mean that |
1267 | SRC itself is not anticipatable, but we just will not be | |
1268 | able to handle code motion of insns with multiple sets. */ | |
1269 | int antic_p = oprs_anticipatable_p (src, insn) | |
1270 | && !multiple_sets (insn); | |
7506f491 | 1271 | /* An expression is not available if its operands are |
eb296bd9 GK |
1272 | subsequently modified, including this insn. It's also not |
1273 | available if this is a branch, because we can't insert | |
1274 | a set after the branch. */ | |
1275 | int avail_p = (oprs_available_p (src, insn) | |
1276 | && ! JUMP_P (insn)); | |
c4c81601 | 1277 | |
20160347 MK |
1278 | insert_expr_in_table (src, GET_MODE (dest), insn, antic_p, avail_p, |
1279 | max_distance, table); | |
7506f491 | 1280 | } |
7506f491 | 1281 | } |
d91edf86 | 1282 | /* In case of store we want to consider the memory value as available in |
f5f2e3cd MH |
1283 | the REG stored in that memory. This makes it possible to remove |
1284 | redundant loads from due to stores to the same location. */ | |
7b1b4aed | 1285 | else if (flag_gcse_las && REG_P (src) && MEM_P (dest)) |
f5f2e3cd MH |
1286 | { |
1287 | unsigned int regno = REGNO (src); | |
fb039b24 | 1288 | int max_distance = 0; |
f5f2e3cd | 1289 | |
e45425ec SB |
1290 | /* Only record sets of pseudo-regs in the hash table. */ |
1291 | if (regno >= FIRST_PSEUDO_REGISTER | |
f5f2e3cd MH |
1292 | /* Don't GCSE something if we can't do a reg/reg copy. */ |
1293 | && can_copy_p (GET_MODE (src)) | |
1294 | /* GCSE commonly inserts instruction after the insn. We can't | |
1d65f45c RH |
1295 | do that easily for EH edges so disable GCSE on these for now. */ |
1296 | && !can_throw_internal (insn) | |
f5f2e3cd | 1297 | /* Is SET_DEST something we want to gcse? */ |
fb039b24 | 1298 | && want_to_gcse_p (dest, &max_distance) |
f5f2e3cd | 1299 | /* Don't CSE a nop. */ |
43c8a043 | 1300 | && ! set_noop_p (set) |
f5f2e3cd MH |
1301 | /* Don't GCSE if it has attached REG_EQUIV note. |
1302 | At this point this only function parameters should have | |
1303 | REG_EQUIV notes and if the argument slot is used somewhere | |
1304 | explicitly, it means address of parameter has been taken, | |
1305 | so we should not extend the lifetime of the pseudo. */ | |
1306 | && ((note = find_reg_note (insn, REG_EQUIV, NULL_RTX)) == 0 | |
7b1b4aed | 1307 | || ! MEM_P (XEXP (note, 0)))) |
f5f2e3cd MH |
1308 | { |
1309 | /* Stores are never anticipatable. */ | |
1310 | int antic_p = 0; | |
1311 | /* An expression is not available if its operands are | |
1312 | subsequently modified, including this insn. It's also not | |
1313 | available if this is a branch, because we can't insert | |
1314 | a set after the branch. */ | |
1315 | int avail_p = oprs_available_p (dest, insn) | |
1316 | && ! JUMP_P (insn); | |
1317 | ||
1318 | /* Record the memory expression (DEST) in the hash table. */ | |
4bcaf354 | 1319 | insert_expr_in_table (dest, GET_MODE (dest), insn, |
fb039b24 | 1320 | antic_p, avail_p, max_distance, table); |
f5f2e3cd MH |
1321 | } |
1322 | } | |
7506f491 DE |
1323 | } |
1324 | ||
1325 | static void | |
1d088dee | 1326 | hash_scan_clobber (rtx x ATTRIBUTE_UNUSED, rtx insn ATTRIBUTE_UNUSED, |
7e5487a2 | 1327 | struct hash_table_d *table ATTRIBUTE_UNUSED) |
7506f491 DE |
1328 | { |
1329 | /* Currently nothing to do. */ | |
1330 | } | |
1331 | ||
1332 | static void | |
1d088dee | 1333 | hash_scan_call (rtx x ATTRIBUTE_UNUSED, rtx insn ATTRIBUTE_UNUSED, |
7e5487a2 | 1334 | struct hash_table_d *table ATTRIBUTE_UNUSED) |
7506f491 DE |
1335 | { |
1336 | /* Currently nothing to do. */ | |
1337 | } | |
1338 | ||
43c8a043 | 1339 | /* Process INSN and add hash table entries as appropriate. */ |
7506f491 DE |
1340 | |
1341 | static void | |
7e5487a2 | 1342 | hash_scan_insn (rtx insn, struct hash_table_d *table) |
7506f491 DE |
1343 | { |
1344 | rtx pat = PATTERN (insn); | |
c4c81601 | 1345 | int i; |
7506f491 DE |
1346 | |
1347 | /* Pick out the sets of INSN and for other forms of instructions record | |
1348 | what's been modified. */ | |
1349 | ||
172890a2 | 1350 | if (GET_CODE (pat) == SET) |
02280659 | 1351 | hash_scan_set (pat, insn, table); |
43c8a043 EB |
1352 | |
1353 | else if (GET_CODE (pat) == CLOBBER) | |
1354 | hash_scan_clobber (pat, insn, table); | |
1355 | ||
1356 | else if (GET_CODE (pat) == CALL) | |
1357 | hash_scan_call (pat, insn, table); | |
1358 | ||
7506f491 | 1359 | else if (GET_CODE (pat) == PARALLEL) |
c4c81601 RK |
1360 | for (i = 0; i < XVECLEN (pat, 0); i++) |
1361 | { | |
1362 | rtx x = XVECEXP (pat, 0, i); | |
7506f491 | 1363 | |
c4c81601 | 1364 | if (GET_CODE (x) == SET) |
02280659 | 1365 | hash_scan_set (x, insn, table); |
c4c81601 | 1366 | else if (GET_CODE (x) == CLOBBER) |
02280659 | 1367 | hash_scan_clobber (x, insn, table); |
6e72d1e9 | 1368 | else if (GET_CODE (x) == CALL) |
02280659 | 1369 | hash_scan_call (x, insn, table); |
c4c81601 | 1370 | } |
7506f491 DE |
1371 | } |
1372 | ||
43c8a043 EB |
1373 | /* Dump the hash table TABLE to file FILE under the name NAME. */ |
1374 | ||
7506f491 | 1375 | static void |
7e5487a2 | 1376 | dump_hash_table (FILE *file, const char *name, struct hash_table_d *table) |
7506f491 DE |
1377 | { |
1378 | int i; | |
1379 | /* Flattened out table, so it's printed in proper order. */ | |
4da896b2 MM |
1380 | struct expr **flat_table; |
1381 | unsigned int *hash_val; | |
c4c81601 | 1382 | struct expr *expr; |
4da896b2 | 1383 | |
1b4572a8 KG |
1384 | flat_table = XCNEWVEC (struct expr *, table->n_elems); |
1385 | hash_val = XNEWVEC (unsigned int, table->n_elems); | |
7506f491 | 1386 | |
02280659 ZD |
1387 | for (i = 0; i < (int) table->size; i++) |
1388 | for (expr = table->table[i]; expr != NULL; expr = expr->next_same_hash) | |
c4c81601 RK |
1389 | { |
1390 | flat_table[expr->bitmap_index] = expr; | |
1391 | hash_val[expr->bitmap_index] = i; | |
1392 | } | |
7506f491 DE |
1393 | |
1394 | fprintf (file, "%s hash table (%d buckets, %d entries)\n", | |
02280659 | 1395 | name, table->size, table->n_elems); |
7506f491 | 1396 | |
02280659 | 1397 | for (i = 0; i < (int) table->n_elems; i++) |
21318741 RK |
1398 | if (flat_table[i] != 0) |
1399 | { | |
a0ac9e5a | 1400 | expr = flat_table[i]; |
20160347 MK |
1401 | fprintf (file, "Index %d (hash value %d; max distance %d)\n ", |
1402 | expr->bitmap_index, hash_val[i], expr->max_distance); | |
a0ac9e5a | 1403 | print_rtl (file, expr->expr); |
21318741 RK |
1404 | fprintf (file, "\n"); |
1405 | } | |
7506f491 DE |
1406 | |
1407 | fprintf (file, "\n"); | |
4da896b2 | 1408 | |
4da896b2 MM |
1409 | free (flat_table); |
1410 | free (hash_val); | |
7506f491 DE |
1411 | } |
1412 | ||
1413 | /* Record register first/last/block set information for REGNO in INSN. | |
c4c81601 | 1414 | |
80c29cc4 | 1415 | first_set records the first place in the block where the register |
7506f491 | 1416 | is set and is used to compute "anticipatability". |
c4c81601 | 1417 | |
80c29cc4 | 1418 | last_set records the last place in the block where the register |
7506f491 | 1419 | is set and is used to compute "availability". |
c4c81601 | 1420 | |
80c29cc4 | 1421 | last_bb records the block for which first_set and last_set are |
4a81774c | 1422 | valid, as a quick test to invalidate them. */ |
7506f491 DE |
1423 | |
1424 | static void | |
1d088dee | 1425 | record_last_reg_set_info (rtx insn, int regno) |
7506f491 | 1426 | { |
80c29cc4 | 1427 | struct reg_avail_info *info = ®_avail_info[regno]; |
4a81774c | 1428 | int luid = DF_INSN_LUID (insn); |
c4c81601 | 1429 | |
4a81774c | 1430 | info->last_set = luid; |
80c29cc4 RZ |
1431 | if (info->last_bb != current_bb) |
1432 | { | |
1433 | info->last_bb = current_bb; | |
4a81774c | 1434 | info->first_set = luid; |
80c29cc4 | 1435 | } |
7506f491 DE |
1436 | } |
1437 | ||
a13d4ebf AM |
1438 | /* Record all of the canonicalized MEMs of record_last_mem_set_info's insn. |
1439 | Note we store a pair of elements in the list, so they have to be | |
1440 | taken off pairwise. */ | |
1441 | ||
589005ff | 1442 | static void |
43c8a043 | 1443 | canon_list_insert (rtx dest ATTRIBUTE_UNUSED, const_rtx x ATTRIBUTE_UNUSED, |
1d088dee | 1444 | void * v_insn) |
a13d4ebf AM |
1445 | { |
1446 | rtx dest_addr, insn; | |
0fe854a7 | 1447 | int bb; |
f32682ca | 1448 | modify_pair pair; |
a13d4ebf AM |
1449 | |
1450 | while (GET_CODE (dest) == SUBREG | |
1451 | || GET_CODE (dest) == ZERO_EXTRACT | |
a13d4ebf AM |
1452 | || GET_CODE (dest) == STRICT_LOW_PART) |
1453 | dest = XEXP (dest, 0); | |
1454 | ||
1455 | /* If DEST is not a MEM, then it will not conflict with a load. Note | |
1456 | that function calls are assumed to clobber memory, but are handled | |
1457 | elsewhere. */ | |
1458 | ||
7b1b4aed | 1459 | if (! MEM_P (dest)) |
a13d4ebf AM |
1460 | return; |
1461 | ||
1462 | dest_addr = get_addr (XEXP (dest, 0)); | |
1463 | dest_addr = canon_rtx (dest_addr); | |
589005ff | 1464 | insn = (rtx) v_insn; |
b0de17ef | 1465 | bb = BLOCK_FOR_INSN (insn)->index; |
a13d4ebf | 1466 | |
f32682ca DN |
1467 | pair.dest = dest; |
1468 | pair.dest_addr = dest_addr; | |
1469 | VEC_safe_push (modify_pair, heap, canon_modify_mem_list[bb], pair); | |
a13d4ebf AM |
1470 | } |
1471 | ||
a13d4ebf AM |
1472 | /* Record memory modification information for INSN. We do not actually care |
1473 | about the memory location(s) that are set, or even how they are set (consider | |
1474 | a CALL_INSN). We merely need to record which insns modify memory. */ | |
7506f491 DE |
1475 | |
1476 | static void | |
1d088dee | 1477 | record_last_mem_set_info (rtx insn) |
7506f491 | 1478 | { |
b0de17ef | 1479 | int bb = BLOCK_FOR_INSN (insn)->index; |
0fe854a7 | 1480 | |
ccef9ef5 | 1481 | /* load_killed_in_block_p will handle the case of calls clobbering |
dc297297 | 1482 | everything. */ |
6409abe3 | 1483 | VEC_safe_push (rtx, heap, modify_mem_list[bb], insn); |
0fe854a7 | 1484 | bitmap_set_bit (modify_mem_list_set, bb); |
a13d4ebf | 1485 | |
7b1b4aed | 1486 | if (CALL_P (insn)) |
6ce1edcf | 1487 | bitmap_set_bit (blocks_with_calls, bb); |
a13d4ebf | 1488 | else |
0fe854a7 | 1489 | note_stores (PATTERN (insn), canon_list_insert, (void*) insn); |
7506f491 DE |
1490 | } |
1491 | ||
7506f491 | 1492 | /* Called from compute_hash_table via note_stores to handle one |
84832317 MM |
1493 | SET or CLOBBER in an insn. DATA is really the instruction in which |
1494 | the SET is taking place. */ | |
7506f491 DE |
1495 | |
1496 | static void | |
7bc980e1 | 1497 | record_last_set_info (rtx dest, const_rtx setter ATTRIBUTE_UNUSED, void *data) |
7506f491 | 1498 | { |
84832317 MM |
1499 | rtx last_set_insn = (rtx) data; |
1500 | ||
7506f491 DE |
1501 | if (GET_CODE (dest) == SUBREG) |
1502 | dest = SUBREG_REG (dest); | |
1503 | ||
7b1b4aed | 1504 | if (REG_P (dest)) |
7506f491 | 1505 | record_last_reg_set_info (last_set_insn, REGNO (dest)); |
7b1b4aed | 1506 | else if (MEM_P (dest) |
7506f491 DE |
1507 | /* Ignore pushes, they clobber nothing. */ |
1508 | && ! push_operand (dest, GET_MODE (dest))) | |
1509 | record_last_mem_set_info (last_set_insn); | |
1510 | } | |
1511 | ||
e45425ec | 1512 | /* Top level function to create an expression hash table. |
7506f491 DE |
1513 | |
1514 | Expression entries are placed in the hash table if | |
1515 | - they are of the form (set (pseudo-reg) src), | |
1516 | - src is something we want to perform GCSE on, | |
1517 | - none of the operands are subsequently modified in the block | |
1518 | ||
7506f491 DE |
1519 | Currently src must be a pseudo-reg or a const_int. |
1520 | ||
02280659 | 1521 | TABLE is the table computed. */ |
7506f491 DE |
1522 | |
1523 | static void | |
7e5487a2 | 1524 | compute_hash_table_work (struct hash_table_d *table) |
7506f491 | 1525 | { |
5f39ad47 | 1526 | int i; |
7506f491 | 1527 | |
a13d4ebf | 1528 | /* re-Cache any INSN_LIST nodes we have allocated. */ |
73991d6a | 1529 | clear_modify_mem_tables (); |
7506f491 | 1530 | /* Some working arrays used to track first and last set in each block. */ |
5f39ad47 | 1531 | reg_avail_info = GNEWVEC (struct reg_avail_info, max_reg_num ()); |
80c29cc4 | 1532 | |
5f39ad47 | 1533 | for (i = 0; i < max_reg_num (); ++i) |
e0082a72 | 1534 | reg_avail_info[i].last_bb = NULL; |
7506f491 | 1535 | |
e0082a72 | 1536 | FOR_EACH_BB (current_bb) |
7506f491 DE |
1537 | { |
1538 | rtx insn; | |
770ae6cc | 1539 | unsigned int regno; |
7506f491 DE |
1540 | |
1541 | /* First pass over the instructions records information used to | |
4a81774c | 1542 | determine when registers and memory are first and last set. */ |
eb232f4e | 1543 | FOR_BB_INSNS (current_bb, insn) |
7506f491 | 1544 | { |
a344c9f1 | 1545 | if (!NONDEBUG_INSN_P (insn)) |
7506f491 DE |
1546 | continue; |
1547 | ||
7b1b4aed | 1548 | if (CALL_P (insn)) |
7506f491 | 1549 | { |
c7fb4c7a SB |
1550 | hard_reg_set_iterator hrsi; |
1551 | EXECUTE_IF_SET_IN_HARD_REG_SET (regs_invalidated_by_call, | |
1552 | 0, regno, hrsi) | |
1553 | record_last_reg_set_info (insn, regno); | |
c4c81601 | 1554 | |
e45425ec SB |
1555 | if (! RTL_CONST_OR_PURE_CALL_P (insn)) |
1556 | record_last_mem_set_info (insn); | |
7506f491 DE |
1557 | } |
1558 | ||
84832317 | 1559 | note_stores (PATTERN (insn), record_last_set_info, insn); |
7506f491 DE |
1560 | } |
1561 | ||
1562 | /* The next pass builds the hash table. */ | |
eb232f4e | 1563 | FOR_BB_INSNS (current_bb, insn) |
a344c9f1 | 1564 | if (NONDEBUG_INSN_P (insn)) |
4a8cae83 | 1565 | hash_scan_insn (insn, table); |
7506f491 DE |
1566 | } |
1567 | ||
80c29cc4 RZ |
1568 | free (reg_avail_info); |
1569 | reg_avail_info = NULL; | |
7506f491 DE |
1570 | } |
1571 | ||
02280659 | 1572 | /* Allocate space for the set/expr hash TABLE. |
e45425ec | 1573 | It is used to determine the number of buckets to use. */ |
7506f491 DE |
1574 | |
1575 | static void | |
e45425ec | 1576 | alloc_hash_table (struct hash_table_d *table) |
7506f491 DE |
1577 | { |
1578 | int n; | |
1579 | ||
b5b8b0ac AO |
1580 | n = get_max_insn_count (); |
1581 | ||
1582 | table->size = n / 4; | |
02280659 ZD |
1583 | if (table->size < 11) |
1584 | table->size = 11; | |
c4c81601 | 1585 | |
7506f491 DE |
1586 | /* Attempt to maintain efficient use of hash table. |
1587 | Making it an odd number is simplest for now. | |
1588 | ??? Later take some measurements. */ | |
02280659 ZD |
1589 | table->size |= 1; |
1590 | n = table->size * sizeof (struct expr *); | |
1b4572a8 | 1591 | table->table = GNEWVAR (struct expr *, n); |
7506f491 DE |
1592 | } |
1593 | ||
02280659 | 1594 | /* Free things allocated by alloc_hash_table. */ |
7506f491 DE |
1595 | |
1596 | static void | |
7e5487a2 | 1597 | free_hash_table (struct hash_table_d *table) |
7506f491 | 1598 | { |
02280659 | 1599 | free (table->table); |
7506f491 DE |
1600 | } |
1601 | ||
e45425ec | 1602 | /* Compute the expression hash table TABLE. */ |
7506f491 DE |
1603 | |
1604 | static void | |
7e5487a2 | 1605 | compute_hash_table (struct hash_table_d *table) |
7506f491 DE |
1606 | { |
1607 | /* Initialize count of number of entries in hash table. */ | |
02280659 | 1608 | table->n_elems = 0; |
703ad42b | 1609 | memset (table->table, 0, table->size * sizeof (struct expr *)); |
7506f491 | 1610 | |
02280659 | 1611 | compute_hash_table_work (table); |
7506f491 DE |
1612 | } |
1613 | \f | |
1614 | /* Expression tracking support. */ | |
1615 | ||
e45425ec SB |
1616 | /* Clear canon_modify_mem_list and modify_mem_list tables. */ |
1617 | static void | |
1618 | clear_modify_mem_tables (void) | |
0e3f0221 | 1619 | { |
e45425ec SB |
1620 | unsigned i; |
1621 | bitmap_iterator bi; | |
0e3f0221 | 1622 | |
e45425ec | 1623 | EXECUTE_IF_SET_IN_BITMAP (modify_mem_list_set, 0, i, bi) |
0e3f0221 | 1624 | { |
6409abe3 | 1625 | VEC_free (rtx, heap, modify_mem_list[i]); |
6ce1edcf | 1626 | VEC_free (modify_pair, heap, canon_modify_mem_list[i]); |
0e3f0221 | 1627 | } |
e45425ec SB |
1628 | bitmap_clear (modify_mem_list_set); |
1629 | bitmap_clear (blocks_with_calls); | |
0e3f0221 RS |
1630 | } |
1631 | ||
e45425ec | 1632 | /* Release memory used by modify_mem_list_set. */ |
0e3f0221 | 1633 | |
e45425ec SB |
1634 | static void |
1635 | free_modify_mem_tables (void) | |
e129b3f9 | 1636 | { |
e45425ec SB |
1637 | clear_modify_mem_tables (); |
1638 | free (modify_mem_list); | |
1639 | free (canon_modify_mem_list); | |
1640 | modify_mem_list = 0; | |
1641 | canon_modify_mem_list = 0; | |
e129b3f9 | 1642 | } |
e45425ec SB |
1643 | \f |
1644 | /* For each block, compute whether X is transparent. X is either an | |
1645 | expression or an assignment [though we don't care which, for this context | |
1646 | an assignment is treated as an expression]. For each block where an | |
1647 | element of X is modified, reset the INDX bit in BMAP. */ | |
0e3f0221 | 1648 | |
e45425ec SB |
1649 | static void |
1650 | compute_transp (const_rtx x, int indx, sbitmap *bmap) | |
0e3f0221 | 1651 | { |
e45425ec SB |
1652 | int i, j; |
1653 | enum rtx_code code; | |
1654 | const char *fmt; | |
0e3f0221 | 1655 | |
e45425ec SB |
1656 | /* repeat is used to turn tail-recursion into iteration since GCC |
1657 | can't do it when there's no return value. */ | |
1658 | repeat: | |
0e3f0221 | 1659 | |
e45425ec SB |
1660 | if (x == 0) |
1661 | return; | |
72b8d451 | 1662 | |
e45425ec SB |
1663 | code = GET_CODE (x); |
1664 | switch (code) | |
0e3f0221 | 1665 | { |
e45425ec | 1666 | case REG: |
628f6a4e | 1667 | { |
e45425ec SB |
1668 | df_ref def; |
1669 | for (def = DF_REG_DEF_CHAIN (REGNO (x)); | |
1670 | def; | |
1671 | def = DF_REF_NEXT_REG (def)) | |
d7c028c0 | 1672 | bitmap_clear_bit (bmap[DF_REF_BB (def)->index], indx); |
628f6a4e | 1673 | } |
7821bfc7 | 1674 | |
e45425ec | 1675 | return; |
72b8d451 | 1676 | |
e45425ec SB |
1677 | case MEM: |
1678 | if (! MEM_READONLY_P (x)) | |
0e3f0221 | 1679 | { |
e45425ec SB |
1680 | bitmap_iterator bi; |
1681 | unsigned bb_index; | |
e129b3f9 | 1682 | |
e45425ec SB |
1683 | /* First handle all the blocks with calls. We don't need to |
1684 | do any list walking for them. */ | |
1685 | EXECUTE_IF_SET_IN_BITMAP (blocks_with_calls, 0, bb_index, bi) | |
1686 | { | |
d7c028c0 | 1687 | bitmap_clear_bit (bmap[bb_index], indx); |
e45425ec | 1688 | } |
0e3f0221 | 1689 | |
e45425ec SB |
1690 | /* Now iterate over the blocks which have memory modifications |
1691 | but which do not have any calls. */ | |
1692 | EXECUTE_IF_AND_COMPL_IN_BITMAP (modify_mem_list_set, | |
1693 | blocks_with_calls, | |
1694 | 0, bb_index, bi) | |
1695 | { | |
6409abe3 | 1696 | VEC (modify_pair,heap) *list |
6ce1edcf NF |
1697 | = canon_modify_mem_list[bb_index]; |
1698 | modify_pair *pair; | |
1699 | unsigned ix; | |
0e3f0221 | 1700 | |
6ce1edcf | 1701 | FOR_EACH_VEC_ELT_REVERSE (modify_pair, list, ix, pair) |
e45425ec | 1702 | { |
6ce1edcf NF |
1703 | rtx dest = pair->dest; |
1704 | rtx dest_addr = pair->dest_addr; | |
0e3f0221 | 1705 | |
53d9622b RS |
1706 | if (canon_true_dependence (dest, GET_MODE (dest), |
1707 | dest_addr, x, NULL_RTX)) | |
d7c028c0 | 1708 | bitmap_clear_bit (bmap[bb_index], indx); |
e45425ec SB |
1709 | } |
1710 | } | |
0e3f0221 | 1711 | } |
0e3f0221 | 1712 | |
e45425ec SB |
1713 | x = XEXP (x, 0); |
1714 | goto repeat; | |
0e3f0221 | 1715 | |
e45425ec SB |
1716 | case PC: |
1717 | case CC0: /*FIXME*/ | |
1718 | case CONST: | |
d8116890 | 1719 | CASE_CONST_ANY: |
e45425ec SB |
1720 | case SYMBOL_REF: |
1721 | case LABEL_REF: | |
1722 | case ADDR_VEC: | |
1723 | case ADDR_DIFF_VEC: | |
1724 | return; | |
0e3f0221 | 1725 | |
e45425ec SB |
1726 | default: |
1727 | break; | |
1728 | } | |
7821bfc7 | 1729 | |
e45425ec | 1730 | for (i = GET_RTX_LENGTH (code) - 1, fmt = GET_RTX_FORMAT (code); i >= 0; i--) |
0e3f0221 | 1731 | { |
e45425ec | 1732 | if (fmt[i] == 'e') |
0e3f0221 | 1733 | { |
e45425ec SB |
1734 | /* If we are about to do the last recursive call |
1735 | needed at this level, change it into iteration. | |
1736 | This function is called enough to be worth it. */ | |
1737 | if (i == 0) | |
1738 | { | |
1739 | x = XEXP (x, i); | |
1740 | goto repeat; | |
1741 | } | |
1742 | ||
1743 | compute_transp (XEXP (x, i), indx, bmap); | |
0e3f0221 | 1744 | } |
e45425ec SB |
1745 | else if (fmt[i] == 'E') |
1746 | for (j = 0; j < XVECLEN (x, i); j++) | |
1747 | compute_transp (XVECEXP (x, i, j), indx, bmap); | |
0e3f0221 | 1748 | } |
0e3f0221 RS |
1749 | } |
1750 | \f | |
a65f3558 | 1751 | /* Compute PRE+LCM working variables. */ |
7506f491 DE |
1752 | |
1753 | /* Local properties of expressions. */ | |
43c8a043 | 1754 | |
7506f491 | 1755 | /* Nonzero for expressions that are transparent in the block. */ |
a65f3558 | 1756 | static sbitmap *transp; |
7506f491 | 1757 | |
a65f3558 JL |
1758 | /* Nonzero for expressions that are computed (available) in the block. */ |
1759 | static sbitmap *comp; | |
7506f491 | 1760 | |
a65f3558 JL |
1761 | /* Nonzero for expressions that are locally anticipatable in the block. */ |
1762 | static sbitmap *antloc; | |
7506f491 | 1763 | |
a65f3558 JL |
1764 | /* Nonzero for expressions where this block is an optimal computation |
1765 | point. */ | |
1766 | static sbitmap *pre_optimal; | |
5c35539b | 1767 | |
a65f3558 JL |
1768 | /* Nonzero for expressions which are redundant in a particular block. */ |
1769 | static sbitmap *pre_redundant; | |
7506f491 | 1770 | |
a42cd965 AM |
1771 | /* Nonzero for expressions which should be inserted on a specific edge. */ |
1772 | static sbitmap *pre_insert_map; | |
1773 | ||
1774 | /* Nonzero for expressions which should be deleted in a specific block. */ | |
1775 | static sbitmap *pre_delete_map; | |
1776 | ||
a65f3558 | 1777 | /* Allocate vars used for PRE analysis. */ |
7506f491 DE |
1778 | |
1779 | static void | |
1d088dee | 1780 | alloc_pre_mem (int n_blocks, int n_exprs) |
7506f491 | 1781 | { |
a65f3558 JL |
1782 | transp = sbitmap_vector_alloc (n_blocks, n_exprs); |
1783 | comp = sbitmap_vector_alloc (n_blocks, n_exprs); | |
1784 | antloc = sbitmap_vector_alloc (n_blocks, n_exprs); | |
5faf03ae | 1785 | |
a42cd965 AM |
1786 | pre_optimal = NULL; |
1787 | pre_redundant = NULL; | |
1788 | pre_insert_map = NULL; | |
1789 | pre_delete_map = NULL; | |
a42cd965 | 1790 | ae_kill = sbitmap_vector_alloc (n_blocks, n_exprs); |
c4c81601 | 1791 | |
a42cd965 | 1792 | /* pre_insert and pre_delete are allocated later. */ |
7506f491 DE |
1793 | } |
1794 | ||
a65f3558 | 1795 | /* Free vars used for PRE analysis. */ |
7506f491 DE |
1796 | |
1797 | static void | |
1d088dee | 1798 | free_pre_mem (void) |
7506f491 | 1799 | { |
5a660bff DB |
1800 | sbitmap_vector_free (transp); |
1801 | sbitmap_vector_free (comp); | |
bd3675fc JL |
1802 | |
1803 | /* ANTLOC and AE_KILL are freed just after pre_lcm finishes. */ | |
7506f491 | 1804 | |
a42cd965 | 1805 | if (pre_optimal) |
5a660bff | 1806 | sbitmap_vector_free (pre_optimal); |
a42cd965 | 1807 | if (pre_redundant) |
5a660bff | 1808 | sbitmap_vector_free (pre_redundant); |
a42cd965 | 1809 | if (pre_insert_map) |
5a660bff | 1810 | sbitmap_vector_free (pre_insert_map); |
a42cd965 | 1811 | if (pre_delete_map) |
5a660bff | 1812 | sbitmap_vector_free (pre_delete_map); |
a42cd965 | 1813 | |
bd3675fc | 1814 | transp = comp = NULL; |
a42cd965 | 1815 | pre_optimal = pre_redundant = pre_insert_map = pre_delete_map = NULL; |
7506f491 DE |
1816 | } |
1817 | ||
9b774782 JL |
1818 | /* Remove certain expressions from anticipatable and transparent |
1819 | sets of basic blocks that have incoming abnormal edge. | |
1820 | For PRE remove potentially trapping expressions to avoid placing | |
1821 | them on abnormal edges. For hoisting remove memory references that | |
1822 | can be clobbered by calls. */ | |
7506f491 DE |
1823 | |
1824 | static void | |
9b774782 | 1825 | prune_expressions (bool pre_p) |
7506f491 | 1826 | { |
9b774782 | 1827 | sbitmap prune_exprs; |
43c8a043 | 1828 | struct expr *expr; |
b614171e | 1829 | unsigned int ui; |
9b774782 | 1830 | basic_block bb; |
c66e8ae9 | 1831 | |
9b774782 | 1832 | prune_exprs = sbitmap_alloc (expr_hash_table.n_elems); |
f61e445a | 1833 | bitmap_clear (prune_exprs); |
02280659 | 1834 | for (ui = 0; ui < expr_hash_table.size; ui++) |
b614171e | 1835 | { |
43c8a043 | 1836 | for (expr = expr_hash_table.table[ui]; expr; expr = expr->next_same_hash) |
9b774782 JL |
1837 | { |
1838 | /* Note potentially trapping expressions. */ | |
43c8a043 | 1839 | if (may_trap_p (expr->expr)) |
9b774782 | 1840 | { |
d7c028c0 | 1841 | bitmap_set_bit (prune_exprs, expr->bitmap_index); |
9b774782 JL |
1842 | continue; |
1843 | } | |
b614171e | 1844 | |
43c8a043 | 1845 | if (!pre_p && MEM_P (expr->expr)) |
9b774782 JL |
1846 | /* Note memory references that can be clobbered by a call. |
1847 | We do not split abnormal edges in hoisting, so would | |
1848 | a memory reference get hoisted along an abnormal edge, | |
1849 | it would be placed /before/ the call. Therefore, only | |
1850 | constant memory references can be hoisted along abnormal | |
1851 | edges. */ | |
1852 | { | |
43c8a043 EB |
1853 | if (GET_CODE (XEXP (expr->expr, 0)) == SYMBOL_REF |
1854 | && CONSTANT_POOL_ADDRESS_P (XEXP (expr->expr, 0))) | |
9b774782 | 1855 | continue; |
c66e8ae9 | 1856 | |
43c8a043 EB |
1857 | if (MEM_READONLY_P (expr->expr) |
1858 | && !MEM_VOLATILE_P (expr->expr) | |
1859 | && MEM_NOTRAP_P (expr->expr)) | |
9b774782 JL |
1860 | /* Constant memory reference, e.g., a PIC address. */ |
1861 | continue; | |
1862 | ||
1863 | /* ??? Optimally, we would use interprocedural alias | |
1864 | analysis to determine if this mem is actually killed | |
1865 | by this call. */ | |
1866 | ||
d7c028c0 | 1867 | bitmap_set_bit (prune_exprs, expr->bitmap_index); |
9b774782 JL |
1868 | } |
1869 | } | |
1870 | } | |
c66e8ae9 | 1871 | |
e0082a72 | 1872 | FOR_EACH_BB (bb) |
c66e8ae9 | 1873 | { |
b614171e | 1874 | edge e; |
628f6a4e | 1875 | edge_iterator ei; |
b614171e MM |
1876 | |
1877 | /* If the current block is the destination of an abnormal edge, we | |
9b774782 JL |
1878 | kill all trapping (for PRE) and memory (for hoist) expressions |
1879 | because we won't be able to properly place the instruction on | |
1880 | the edge. So make them neither anticipatable nor transparent. | |
1881 | This is fairly conservative. | |
1882 | ||
1883 | ??? For hoisting it may be necessary to check for set-and-jump | |
1884 | instructions here, not just for abnormal edges. The general problem | |
1885 | is that when an expression cannot not be placed right at the end of | |
1886 | a basic block we should account for any side-effects of a subsequent | |
1887 | jump instructions that could clobber the expression. It would | |
1888 | be best to implement this check along the lines of | |
b11f0116 | 1889 | should_hoist_expr_to_dom where the target block is already known |
9b774782 JL |
1890 | and, hence, there's no need to conservatively prune expressions on |
1891 | "intermediate" set-and-jump instructions. */ | |
628f6a4e | 1892 | FOR_EACH_EDGE (e, ei, bb->preds) |
9b774782 JL |
1893 | if ((e->flags & EDGE_ABNORMAL) |
1894 | && (pre_p || CALL_P (BB_END (e->src)))) | |
b614171e | 1895 | { |
f61e445a | 1896 | bitmap_and_compl (antloc[bb->index], |
9b774782 | 1897 | antloc[bb->index], prune_exprs); |
f61e445a | 1898 | bitmap_and_compl (transp[bb->index], |
9b774782 | 1899 | transp[bb->index], prune_exprs); |
b614171e MM |
1900 | break; |
1901 | } | |
9b774782 JL |
1902 | } |
1903 | ||
1904 | sbitmap_free (prune_exprs); | |
1905 | } | |
1906 | ||
29fa95ed JL |
1907 | /* It may be necessary to insert a large number of insns on edges to |
1908 | make the existing occurrences of expressions fully redundant. This | |
1909 | routine examines the set of insertions and deletions and if the ratio | |
1910 | of insertions to deletions is too high for a particular expression, then | |
1911 | the expression is removed from the insertion/deletion sets. | |
1912 | ||
1913 | N_ELEMS is the number of elements in the hash table. */ | |
1914 | ||
1915 | static void | |
1916 | prune_insertions_deletions (int n_elems) | |
1917 | { | |
1918 | sbitmap_iterator sbi; | |
1919 | sbitmap prune_exprs; | |
1920 | ||
1921 | /* We always use I to iterate over blocks/edges and J to iterate over | |
1922 | expressions. */ | |
1923 | unsigned int i, j; | |
1924 | ||
1925 | /* Counts for the number of times an expression needs to be inserted and | |
1926 | number of times an expression can be removed as a result. */ | |
1927 | int *insertions = GCNEWVEC (int, n_elems); | |
1928 | int *deletions = GCNEWVEC (int, n_elems); | |
1929 | ||
1930 | /* Set of expressions which require too many insertions relative to | |
1931 | the number of deletions achieved. We will prune these out of the | |
1932 | insertion/deletion sets. */ | |
1933 | prune_exprs = sbitmap_alloc (n_elems); | |
f61e445a | 1934 | bitmap_clear (prune_exprs); |
29fa95ed JL |
1935 | |
1936 | /* Iterate over the edges counting the number of times each expression | |
1937 | needs to be inserted. */ | |
1938 | for (i = 0; i < (unsigned) n_edges; i++) | |
1939 | { | |
d4ac4ce2 | 1940 | EXECUTE_IF_SET_IN_BITMAP (pre_insert_map[i], 0, j, sbi) |
29fa95ed JL |
1941 | insertions[j]++; |
1942 | } | |
1943 | ||
1944 | /* Similarly for deletions, but those occur in blocks rather than on | |
1945 | edges. */ | |
1946 | for (i = 0; i < (unsigned) last_basic_block; i++) | |
1947 | { | |
d4ac4ce2 | 1948 | EXECUTE_IF_SET_IN_BITMAP (pre_delete_map[i], 0, j, sbi) |
29fa95ed JL |
1949 | deletions[j]++; |
1950 | } | |
1951 | ||
1952 | /* Now that we have accurate counts, iterate over the elements in the | |
1953 | hash table and see if any need too many insertions relative to the | |
1954 | number of evaluations that can be removed. If so, mark them in | |
1955 | PRUNE_EXPRS. */ | |
1956 | for (j = 0; j < (unsigned) n_elems; j++) | |
1957 | if (deletions[j] | |
1958 | && ((unsigned) insertions[j] / deletions[j]) > MAX_GCSE_INSERTION_RATIO) | |
d7c028c0 | 1959 | bitmap_set_bit (prune_exprs, j); |
29fa95ed JL |
1960 | |
1961 | /* Now prune PRE_INSERT_MAP and PRE_DELETE_MAP based on PRUNE_EXPRS. */ | |
d4ac4ce2 | 1962 | EXECUTE_IF_SET_IN_BITMAP (prune_exprs, 0, j, sbi) |
29fa95ed JL |
1963 | { |
1964 | for (i = 0; i < (unsigned) n_edges; i++) | |
d7c028c0 | 1965 | bitmap_clear_bit (pre_insert_map[i], j); |
29fa95ed JL |
1966 | |
1967 | for (i = 0; i < (unsigned) last_basic_block; i++) | |
d7c028c0 | 1968 | bitmap_clear_bit (pre_delete_map[i], j); |
29fa95ed JL |
1969 | } |
1970 | ||
1971 | sbitmap_free (prune_exprs); | |
1972 | free (insertions); | |
1973 | free (deletions); | |
1974 | } | |
1975 | ||
9b774782 | 1976 | /* Top level routine to do the dataflow analysis needed by PRE. */ |
b614171e | 1977 | |
43c8a043 | 1978 | static struct edge_list * |
9b774782 JL |
1979 | compute_pre_data (void) |
1980 | { | |
43c8a043 | 1981 | struct edge_list *edge_list; |
9b774782 JL |
1982 | basic_block bb; |
1983 | ||
1984 | compute_local_properties (transp, comp, antloc, &expr_hash_table); | |
1985 | prune_expressions (true); | |
f61e445a | 1986 | bitmap_vector_clear (ae_kill, last_basic_block); |
9b774782 JL |
1987 | |
1988 | /* Compute ae_kill for each basic block using: | |
1989 | ||
1990 | ~(TRANSP | COMP) | |
1991 | */ | |
1992 | ||
1993 | FOR_EACH_BB (bb) | |
1994 | { | |
f61e445a LC |
1995 | bitmap_ior (ae_kill[bb->index], transp[bb->index], comp[bb->index]); |
1996 | bitmap_not (ae_kill[bb->index], ae_kill[bb->index]); | |
c66e8ae9 JL |
1997 | } |
1998 | ||
10d22567 | 1999 | edge_list = pre_edge_lcm (expr_hash_table.n_elems, transp, comp, antloc, |
a42cd965 | 2000 | ae_kill, &pre_insert_map, &pre_delete_map); |
5a660bff | 2001 | sbitmap_vector_free (antloc); |
bd3675fc | 2002 | antloc = NULL; |
5a660bff | 2003 | sbitmap_vector_free (ae_kill); |
589005ff | 2004 | ae_kill = NULL; |
29fa95ed JL |
2005 | |
2006 | prune_insertions_deletions (expr_hash_table.n_elems); | |
43c8a043 EB |
2007 | |
2008 | return edge_list; | |
7506f491 DE |
2009 | } |
2010 | \f | |
2011 | /* PRE utilities */ | |
2012 | ||
cc2902df | 2013 | /* Return nonzero if an occurrence of expression EXPR in OCCR_BB would reach |
a65f3558 | 2014 | block BB. |
7506f491 DE |
2015 | |
2016 | VISITED is a pointer to a working buffer for tracking which BB's have | |
2017 | been visited. It is NULL for the top-level call. | |
2018 | ||
2019 | We treat reaching expressions that go through blocks containing the same | |
2020 | reaching expression as "not reaching". E.g. if EXPR is generated in blocks | |
2021 | 2 and 3, INSN is in block 4, and 2->3->4, we treat the expression in block | |
2022 | 2 as not reaching. The intent is to improve the probability of finding | |
2023 | only one reaching expression and to reduce register lifetimes by picking | |
2024 | the closest such expression. */ | |
2025 | ||
2026 | static int | |
43c8a043 EB |
2027 | pre_expr_reaches_here_p_work (basic_block occr_bb, struct expr *expr, |
2028 | basic_block bb, char *visited) | |
7506f491 | 2029 | { |
36349f8b | 2030 | edge pred; |
628f6a4e | 2031 | edge_iterator ei; |
b8698a0f | 2032 | |
628f6a4e | 2033 | FOR_EACH_EDGE (pred, ei, bb->preds) |
7506f491 | 2034 | { |
e2d2ed72 | 2035 | basic_block pred_bb = pred->src; |
7506f491 | 2036 | |
36349f8b | 2037 | if (pred->src == ENTRY_BLOCK_PTR |
7506f491 | 2038 | /* Has predecessor has already been visited? */ |
0b17ab2f | 2039 | || visited[pred_bb->index]) |
c4c81601 RK |
2040 | ;/* Nothing to do. */ |
2041 | ||
7506f491 | 2042 | /* Does this predecessor generate this expression? */ |
d7c028c0 | 2043 | else if (bitmap_bit_p (comp[pred_bb->index], expr->bitmap_index)) |
7506f491 DE |
2044 | { |
2045 | /* Is this the occurrence we're looking for? | |
2046 | Note that there's only one generating occurrence per block | |
2047 | so we just need to check the block number. */ | |
a65f3558 | 2048 | if (occr_bb == pred_bb) |
7506f491 | 2049 | return 1; |
c4c81601 | 2050 | |
0b17ab2f | 2051 | visited[pred_bb->index] = 1; |
7506f491 DE |
2052 | } |
2053 | /* Ignore this predecessor if it kills the expression. */ | |
d7c028c0 | 2054 | else if (! bitmap_bit_p (transp[pred_bb->index], expr->bitmap_index)) |
0b17ab2f | 2055 | visited[pred_bb->index] = 1; |
c4c81601 | 2056 | |
7506f491 DE |
2057 | /* Neither gen nor kill. */ |
2058 | else | |
ac7c5af5 | 2059 | { |
0b17ab2f | 2060 | visited[pred_bb->index] = 1; |
89e606c9 | 2061 | if (pre_expr_reaches_here_p_work (occr_bb, expr, pred_bb, visited)) |
7506f491 | 2062 | return 1; |
ac7c5af5 | 2063 | } |
7506f491 DE |
2064 | } |
2065 | ||
2066 | /* All paths have been checked. */ | |
2067 | return 0; | |
2068 | } | |
283a2545 RL |
2069 | |
2070 | /* The wrapper for pre_expr_reaches_here_work that ensures that any | |
dc297297 | 2071 | memory allocated for that function is returned. */ |
283a2545 RL |
2072 | |
2073 | static int | |
1d088dee | 2074 | pre_expr_reaches_here_p (basic_block occr_bb, struct expr *expr, basic_block bb) |
283a2545 RL |
2075 | { |
2076 | int rval; | |
5ed6ace5 | 2077 | char *visited = XCNEWVEC (char, last_basic_block); |
283a2545 | 2078 | |
8e42ace1 | 2079 | rval = pre_expr_reaches_here_p_work (occr_bb, expr, bb, visited); |
283a2545 RL |
2080 | |
2081 | free (visited); | |
c4c81601 | 2082 | return rval; |
283a2545 | 2083 | } |
7506f491 | 2084 | \f |
43c8a043 | 2085 | /* Generate RTL to copy an EXPR to its `reaching_reg' and return it. */ |
a42cd965 AM |
2086 | |
2087 | static rtx | |
1d088dee | 2088 | process_insert_insn (struct expr *expr) |
a42cd965 AM |
2089 | { |
2090 | rtx reg = expr->reaching_reg; | |
43c8a043 | 2091 | /* Copy the expression to make sure we don't have any sharing issues. */ |
fb0c0a12 RK |
2092 | rtx exp = copy_rtx (expr->expr); |
2093 | rtx pat; | |
a42cd965 AM |
2094 | |
2095 | start_sequence (); | |
fb0c0a12 RK |
2096 | |
2097 | /* If the expression is something that's an operand, like a constant, | |
2098 | just copy it to a register. */ | |
2099 | if (general_operand (exp, GET_MODE (reg))) | |
2100 | emit_move_insn (reg, exp); | |
2101 | ||
2102 | /* Otherwise, make a new insn to compute this expression and make sure the | |
43c8a043 | 2103 | insn will be recognized (this also adds any needed CLOBBERs). */ |
282899df NS |
2104 | else |
2105 | { | |
2106 | rtx insn = emit_insn (gen_rtx_SET (VOIDmode, reg, exp)); | |
2107 | ||
57ac4c34 | 2108 | if (insn_invalid_p (insn, false)) |
2f021b67 | 2109 | gcc_unreachable (); |
282899df | 2110 | } |
b8698a0f | 2111 | |
2f937369 | 2112 | pat = get_insns (); |
a42cd965 AM |
2113 | end_sequence (); |
2114 | ||
2115 | return pat; | |
2116 | } | |
589005ff | 2117 | |
a65f3558 JL |
2118 | /* Add EXPR to the end of basic block BB. |
2119 | ||
eae7938e | 2120 | This is used by both the PRE and code hoisting. */ |
7506f491 DE |
2121 | |
2122 | static void | |
eae7938e | 2123 | insert_insn_end_basic_block (struct expr *expr, basic_block bb) |
7506f491 | 2124 | { |
a813c111 | 2125 | rtx insn = BB_END (bb); |
7506f491 DE |
2126 | rtx new_insn; |
2127 | rtx reg = expr->reaching_reg; | |
2128 | int regno = REGNO (reg); | |
2f937369 | 2129 | rtx pat, pat_end; |
7506f491 | 2130 | |
a42cd965 | 2131 | pat = process_insert_insn (expr); |
282899df | 2132 | gcc_assert (pat && INSN_P (pat)); |
2f937369 DM |
2133 | |
2134 | pat_end = pat; | |
2135 | while (NEXT_INSN (pat_end) != NULL_RTX) | |
2136 | pat_end = NEXT_INSN (pat_end); | |
7506f491 DE |
2137 | |
2138 | /* If the last insn is a jump, insert EXPR in front [taking care to | |
4d6922ee | 2139 | handle cc0, etc. properly]. Similarly we need to care trapping |
068473ec | 2140 | instructions in presence of non-call exceptions. */ |
7506f491 | 2141 | |
7b1b4aed | 2142 | if (JUMP_P (insn) |
4b4bf941 | 2143 | || (NONJUMP_INSN_P (insn) |
c5cbcccf ZD |
2144 | && (!single_succ_p (bb) |
2145 | || single_succ_edge (bb)->flags & EDGE_ABNORMAL))) | |
7506f491 | 2146 | { |
50b2596f | 2147 | #ifdef HAVE_cc0 |
7506f491 | 2148 | rtx note; |
50b2596f | 2149 | #endif |
7506f491 DE |
2150 | |
2151 | /* If this is a jump table, then we can't insert stuff here. Since | |
2152 | we know the previous real insn must be the tablejump, we insert | |
2153 | the new instruction just before the tablejump. */ | |
2154 | if (GET_CODE (PATTERN (insn)) == ADDR_VEC | |
2155 | || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC) | |
03f43d3d | 2156 | insn = prev_active_insn (insn); |
7506f491 DE |
2157 | |
2158 | #ifdef HAVE_cc0 | |
2159 | /* FIXME: 'twould be nice to call prev_cc0_setter here but it aborts | |
2160 | if cc0 isn't set. */ | |
2161 | note = find_reg_note (insn, REG_CC_SETTER, NULL_RTX); | |
2162 | if (note) | |
2163 | insn = XEXP (note, 0); | |
2164 | else | |
2165 | { | |
2166 | rtx maybe_cc0_setter = prev_nonnote_insn (insn); | |
2167 | if (maybe_cc0_setter | |
2c3c49de | 2168 | && INSN_P (maybe_cc0_setter) |
7506f491 DE |
2169 | && sets_cc0_p (PATTERN (maybe_cc0_setter))) |
2170 | insn = maybe_cc0_setter; | |
2171 | } | |
2172 | #endif | |
2173 | /* FIXME: What if something in cc0/jump uses value set in new insn? */ | |
6fb5fa3c | 2174 | new_insn = emit_insn_before_noloc (pat, insn, bb); |
3947e2f9 | 2175 | } |
c4c81601 | 2176 | |
3947e2f9 RH |
2177 | /* Likewise if the last insn is a call, as will happen in the presence |
2178 | of exception handling. */ | |
7b1b4aed | 2179 | else if (CALL_P (insn) |
c5cbcccf ZD |
2180 | && (!single_succ_p (bb) |
2181 | || single_succ_edge (bb)->flags & EDGE_ABNORMAL)) | |
3947e2f9 | 2182 | { |
42db504c SB |
2183 | /* Keeping in mind targets with small register classes and parameters |
2184 | in registers, we search backward and place the instructions before | |
2185 | the first parameter is loaded. Do this for everyone for consistency | |
eae7938e | 2186 | and a presumption that we'll get better code elsewhere as well. */ |
3947e2f9 RH |
2187 | |
2188 | /* Since different machines initialize their parameter registers | |
2189 | in different orders, assume nothing. Collect the set of all | |
2190 | parameter registers. */ | |
a813c111 | 2191 | insn = find_first_parameter_load (insn, BB_HEAD (bb)); |
3947e2f9 | 2192 | |
b1d26727 JL |
2193 | /* If we found all the parameter loads, then we want to insert |
2194 | before the first parameter load. | |
2195 | ||
2196 | If we did not find all the parameter loads, then we might have | |
2197 | stopped on the head of the block, which could be a CODE_LABEL. | |
2198 | If we inserted before the CODE_LABEL, then we would be putting | |
2199 | the insn in the wrong basic block. In that case, put the insn | |
b5229628 | 2200 | after the CODE_LABEL. Also, respect NOTE_INSN_BASIC_BLOCK. */ |
7b1b4aed | 2201 | while (LABEL_P (insn) |
589ca5cb | 2202 | || NOTE_INSN_BASIC_BLOCK_P (insn)) |
b5229628 | 2203 | insn = NEXT_INSN (insn); |
c4c81601 | 2204 | |
6fb5fa3c | 2205 | new_insn = emit_insn_before_noloc (pat, insn, bb); |
7506f491 DE |
2206 | } |
2207 | else | |
6fb5fa3c | 2208 | new_insn = emit_insn_after_noloc (pat, insn, bb); |
7506f491 | 2209 | |
2f937369 | 2210 | while (1) |
a65f3558 | 2211 | { |
2f937369 | 2212 | if (INSN_P (pat)) |
4a81774c | 2213 | add_label_notes (PATTERN (pat), new_insn); |
2f937369 DM |
2214 | if (pat == pat_end) |
2215 | break; | |
2216 | pat = NEXT_INSN (pat); | |
a65f3558 | 2217 | } |
3947e2f9 | 2218 | |
7506f491 DE |
2219 | gcse_create_count++; |
2220 | ||
10d22567 | 2221 | if (dump_file) |
7506f491 | 2222 | { |
10d22567 | 2223 | fprintf (dump_file, "PRE/HOIST: end of bb %d, insn %d, ", |
0b17ab2f | 2224 | bb->index, INSN_UID (new_insn)); |
10d22567 | 2225 | fprintf (dump_file, "copying expression %d to reg %d\n", |
c4c81601 | 2226 | expr->bitmap_index, regno); |
7506f491 DE |
2227 | } |
2228 | } | |
2229 | ||
a42cd965 AM |
2230 | /* Insert partially redundant expressions on edges in the CFG to make |
2231 | the expressions fully redundant. */ | |
7506f491 | 2232 | |
a42cd965 | 2233 | static int |
1d088dee | 2234 | pre_edge_insert (struct edge_list *edge_list, struct expr **index_map) |
7506f491 | 2235 | { |
c4c81601 | 2236 | int e, i, j, num_edges, set_size, did_insert = 0; |
a65f3558 JL |
2237 | sbitmap *inserted; |
2238 | ||
a42cd965 AM |
2239 | /* Where PRE_INSERT_MAP is nonzero, we add the expression on that edge |
2240 | if it reaches any of the deleted expressions. */ | |
7506f491 | 2241 | |
a42cd965 AM |
2242 | set_size = pre_insert_map[0]->size; |
2243 | num_edges = NUM_EDGES (edge_list); | |
02280659 | 2244 | inserted = sbitmap_vector_alloc (num_edges, expr_hash_table.n_elems); |
f61e445a | 2245 | bitmap_vector_clear (inserted, num_edges); |
7506f491 | 2246 | |
a42cd965 | 2247 | for (e = 0; e < num_edges; e++) |
7506f491 DE |
2248 | { |
2249 | int indx; | |
e2d2ed72 | 2250 | basic_block bb = INDEX_EDGE_PRED_BB (edge_list, e); |
a65f3558 | 2251 | |
a65f3558 | 2252 | for (i = indx = 0; i < set_size; i++, indx += SBITMAP_ELT_BITS) |
7506f491 | 2253 | { |
a42cd965 | 2254 | SBITMAP_ELT_TYPE insert = pre_insert_map[e]->elms[i]; |
7506f491 | 2255 | |
43c8a043 EB |
2256 | for (j = indx; |
2257 | insert && j < (int) expr_hash_table.n_elems; | |
2258 | j++, insert >>= 1) | |
c4c81601 RK |
2259 | if ((insert & 1) != 0 && index_map[j]->reaching_reg != NULL_RTX) |
2260 | { | |
2261 | struct expr *expr = index_map[j]; | |
2262 | struct occr *occr; | |
a65f3558 | 2263 | |
ff7cc307 | 2264 | /* Now look at each deleted occurrence of this expression. */ |
c4c81601 RK |
2265 | for (occr = expr->antic_occr; occr != NULL; occr = occr->next) |
2266 | { | |
2267 | if (! occr->deleted_p) | |
2268 | continue; | |
2269 | ||
3f117656 | 2270 | /* Insert this expression on this edge if it would |
ff7cc307 | 2271 | reach the deleted occurrence in BB. */ |
d7c028c0 | 2272 | if (!bitmap_bit_p (inserted[e], j)) |
c4c81601 RK |
2273 | { |
2274 | rtx insn; | |
2275 | edge eg = INDEX_EDGE (edge_list, e); | |
2276 | ||
2277 | /* We can't insert anything on an abnormal and | |
2278 | critical edge, so we insert the insn at the end of | |
2279 | the previous block. There are several alternatives | |
2280 | detailed in Morgans book P277 (sec 10.5) for | |
2281 | handling this situation. This one is easiest for | |
2282 | now. */ | |
2283 | ||
b16aa8a5 | 2284 | if (eg->flags & EDGE_ABNORMAL) |
eae7938e | 2285 | insert_insn_end_basic_block (index_map[j], bb); |
c4c81601 RK |
2286 | else |
2287 | { | |
2288 | insn = process_insert_insn (index_map[j]); | |
2289 | insert_insn_on_edge (insn, eg); | |
2290 | } | |
2291 | ||
10d22567 | 2292 | if (dump_file) |
c4c81601 | 2293 | { |
5f39ad47 | 2294 | fprintf (dump_file, "PRE: edge (%d,%d), ", |
0b17ab2f RH |
2295 | bb->index, |
2296 | INDEX_EDGE_SUCC_BB (edge_list, e)->index); | |
10d22567 | 2297 | fprintf (dump_file, "copy expression %d\n", |
c4c81601 RK |
2298 | expr->bitmap_index); |
2299 | } | |
2300 | ||
a13d4ebf | 2301 | update_ld_motion_stores (expr); |
d7c028c0 | 2302 | bitmap_set_bit (inserted[e], j); |
c4c81601 RK |
2303 | did_insert = 1; |
2304 | gcse_create_count++; | |
2305 | } | |
2306 | } | |
2307 | } | |
7506f491 DE |
2308 | } |
2309 | } | |
5faf03ae | 2310 | |
5a660bff | 2311 | sbitmap_vector_free (inserted); |
a42cd965 | 2312 | return did_insert; |
7506f491 DE |
2313 | } |
2314 | ||
073089a7 | 2315 | /* Copy the result of EXPR->EXPR generated by INSN to EXPR->REACHING_REG. |
b885908b MH |
2316 | Given "old_reg <- expr" (INSN), instead of adding after it |
2317 | reaching_reg <- old_reg | |
2318 | it's better to do the following: | |
2319 | reaching_reg <- expr | |
2320 | old_reg <- reaching_reg | |
2321 | because this way copy propagation can discover additional PRE | |
f5f2e3cd MH |
2322 | opportunities. But if this fails, we try the old way. |
2323 | When "expr" is a store, i.e. | |
2324 | given "MEM <- old_reg", instead of adding after it | |
2325 | reaching_reg <- old_reg | |
2326 | it's better to add it before as follows: | |
2327 | reaching_reg <- old_reg | |
2328 | MEM <- reaching_reg. */ | |
7506f491 DE |
2329 | |
2330 | static void | |
1d088dee | 2331 | pre_insert_copy_insn (struct expr *expr, rtx insn) |
7506f491 DE |
2332 | { |
2333 | rtx reg = expr->reaching_reg; | |
2334 | int regno = REGNO (reg); | |
2335 | int indx = expr->bitmap_index; | |
073089a7 | 2336 | rtx pat = PATTERN (insn); |
64068ca2 | 2337 | rtx set, first_set, new_insn; |
b885908b | 2338 | rtx old_reg; |
073089a7 | 2339 | int i; |
7506f491 | 2340 | |
073089a7 | 2341 | /* This block matches the logic in hash_scan_insn. */ |
282899df | 2342 | switch (GET_CODE (pat)) |
073089a7 | 2343 | { |
282899df NS |
2344 | case SET: |
2345 | set = pat; | |
2346 | break; | |
2347 | ||
2348 | case PARALLEL: | |
073089a7 RS |
2349 | /* Search through the parallel looking for the set whose |
2350 | source was the expression that we're interested in. */ | |
64068ca2 | 2351 | first_set = NULL_RTX; |
073089a7 RS |
2352 | set = NULL_RTX; |
2353 | for (i = 0; i < XVECLEN (pat, 0); i++) | |
2354 | { | |
2355 | rtx x = XVECEXP (pat, 0, i); | |
64068ca2 | 2356 | if (GET_CODE (x) == SET) |
073089a7 | 2357 | { |
64068ca2 RS |
2358 | /* If the source was a REG_EQUAL or REG_EQUIV note, we |
2359 | may not find an equivalent expression, but in this | |
2360 | case the PARALLEL will have a single set. */ | |
2361 | if (first_set == NULL_RTX) | |
2362 | first_set = x; | |
2363 | if (expr_equiv_p (SET_SRC (x), expr->expr)) | |
2364 | { | |
2365 | set = x; | |
2366 | break; | |
2367 | } | |
073089a7 RS |
2368 | } |
2369 | } | |
64068ca2 RS |
2370 | |
2371 | gcc_assert (first_set); | |
2372 | if (set == NULL_RTX) | |
2373 | set = first_set; | |
282899df NS |
2374 | break; |
2375 | ||
2376 | default: | |
2377 | gcc_unreachable (); | |
073089a7 | 2378 | } |
c4c81601 | 2379 | |
7b1b4aed | 2380 | if (REG_P (SET_DEST (set))) |
073089a7 | 2381 | { |
f5f2e3cd MH |
2382 | old_reg = SET_DEST (set); |
2383 | /* Check if we can modify the set destination in the original insn. */ | |
2384 | if (validate_change (insn, &SET_DEST (set), reg, 0)) | |
2385 | { | |
2386 | new_insn = gen_move_insn (old_reg, reg); | |
2387 | new_insn = emit_insn_after (new_insn, insn); | |
f5f2e3cd MH |
2388 | } |
2389 | else | |
2390 | { | |
2391 | new_insn = gen_move_insn (reg, old_reg); | |
2392 | new_insn = emit_insn_after (new_insn, insn); | |
f5f2e3cd | 2393 | } |
073089a7 | 2394 | } |
f5f2e3cd | 2395 | else /* This is possible only in case of a store to memory. */ |
073089a7 | 2396 | { |
f5f2e3cd | 2397 | old_reg = SET_SRC (set); |
073089a7 | 2398 | new_insn = gen_move_insn (reg, old_reg); |
f5f2e3cd MH |
2399 | |
2400 | /* Check if we can modify the set source in the original insn. */ | |
2401 | if (validate_change (insn, &SET_SRC (set), reg, 0)) | |
2402 | new_insn = emit_insn_before (new_insn, insn); | |
2403 | else | |
2404 | new_insn = emit_insn_after (new_insn, insn); | |
073089a7 | 2405 | } |
7506f491 DE |
2406 | |
2407 | gcse_create_count++; | |
2408 | ||
10d22567 ZD |
2409 | if (dump_file) |
2410 | fprintf (dump_file, | |
a42cd965 | 2411 | "PRE: bb %d, insn %d, copy expression %d in insn %d to reg %d\n", |
b0de17ef | 2412 | BLOCK_FOR_INSN (insn)->index, INSN_UID (new_insn), indx, |
a42cd965 | 2413 | INSN_UID (insn), regno); |
7506f491 DE |
2414 | } |
2415 | ||
2416 | /* Copy available expressions that reach the redundant expression | |
2417 | to `reaching_reg'. */ | |
2418 | ||
2419 | static void | |
1d088dee | 2420 | pre_insert_copies (void) |
7506f491 | 2421 | { |
f5f2e3cd | 2422 | unsigned int i, added_copy; |
c4c81601 RK |
2423 | struct expr *expr; |
2424 | struct occr *occr; | |
2425 | struct occr *avail; | |
a65f3558 | 2426 | |
7506f491 DE |
2427 | /* For each available expression in the table, copy the result to |
2428 | `reaching_reg' if the expression reaches a deleted one. | |
2429 | ||
2430 | ??? The current algorithm is rather brute force. | |
2431 | Need to do some profiling. */ | |
2432 | ||
02280659 | 2433 | for (i = 0; i < expr_hash_table.size; i++) |
43c8a043 | 2434 | for (expr = expr_hash_table.table[i]; expr; expr = expr->next_same_hash) |
c4c81601 RK |
2435 | { |
2436 | /* If the basic block isn't reachable, PPOUT will be TRUE. However, | |
2437 | we don't want to insert a copy here because the expression may not | |
2438 | really be redundant. So only insert an insn if the expression was | |
2439 | deleted. This test also avoids further processing if the | |
2440 | expression wasn't deleted anywhere. */ | |
2441 | if (expr->reaching_reg == NULL) | |
2442 | continue; | |
7b1b4aed | 2443 | |
f5f2e3cd | 2444 | /* Set when we add a copy for that expression. */ |
7b1b4aed | 2445 | added_copy = 0; |
c4c81601 RK |
2446 | |
2447 | for (occr = expr->antic_occr; occr != NULL; occr = occr->next) | |
2448 | { | |
2449 | if (! occr->deleted_p) | |
2450 | continue; | |
7506f491 | 2451 | |
c4c81601 RK |
2452 | for (avail = expr->avail_occr; avail != NULL; avail = avail->next) |
2453 | { | |
2454 | rtx insn = avail->insn; | |
7506f491 | 2455 | |
c4c81601 RK |
2456 | /* No need to handle this one if handled already. */ |
2457 | if (avail->copied_p) | |
2458 | continue; | |
7506f491 | 2459 | |
c4c81601 | 2460 | /* Don't handle this one if it's a redundant one. */ |
4a81774c | 2461 | if (INSN_DELETED_P (insn)) |
c4c81601 | 2462 | continue; |
7506f491 | 2463 | |
c4c81601 | 2464 | /* Or if the expression doesn't reach the deleted one. */ |
589005ff | 2465 | if (! pre_expr_reaches_here_p (BLOCK_FOR_INSN (avail->insn), |
e2d2ed72 AM |
2466 | expr, |
2467 | BLOCK_FOR_INSN (occr->insn))) | |
c4c81601 | 2468 | continue; |
7506f491 | 2469 | |
f5f2e3cd MH |
2470 | added_copy = 1; |
2471 | ||
c4c81601 RK |
2472 | /* Copy the result of avail to reaching_reg. */ |
2473 | pre_insert_copy_insn (expr, insn); | |
2474 | avail->copied_p = 1; | |
2475 | } | |
2476 | } | |
f5f2e3cd | 2477 | |
7b1b4aed | 2478 | if (added_copy) |
f5f2e3cd | 2479 | update_ld_motion_stores (expr); |
c4c81601 | 2480 | } |
7506f491 DE |
2481 | } |
2482 | ||
10d1bb36 JH |
2483 | /* Emit move from SRC to DEST noting the equivalence with expression computed |
2484 | in INSN. */ | |
43c8a043 | 2485 | |
10d1bb36 | 2486 | static rtx |
43c8a043 | 2487 | gcse_emit_move_after (rtx dest, rtx src, rtx insn) |
10d1bb36 | 2488 | { |
60564289 | 2489 | rtx new_rtx; |
6bdb8dd6 | 2490 | rtx set = single_set (insn), set2; |
10d1bb36 JH |
2491 | rtx note; |
2492 | rtx eqv; | |
2493 | ||
2494 | /* This should never fail since we're creating a reg->reg copy | |
2495 | we've verified to be valid. */ | |
2496 | ||
60564289 | 2497 | new_rtx = emit_insn_after (gen_move_insn (dest, src), insn); |
285464d0 | 2498 | |
10d1bb36 | 2499 | /* Note the equivalence for local CSE pass. */ |
60564289 | 2500 | set2 = single_set (new_rtx); |
6bdb8dd6 | 2501 | if (!set2 || !rtx_equal_p (SET_DEST (set2), dest)) |
60564289 | 2502 | return new_rtx; |
10d1bb36 JH |
2503 | if ((note = find_reg_equal_equiv_note (insn))) |
2504 | eqv = XEXP (note, 0); | |
2505 | else | |
2506 | eqv = SET_SRC (set); | |
2507 | ||
60564289 | 2508 | set_unique_reg_note (new_rtx, REG_EQUAL, copy_insn_1 (eqv)); |
10d1bb36 | 2509 | |
60564289 | 2510 | return new_rtx; |
10d1bb36 JH |
2511 | } |
2512 | ||
7506f491 | 2513 | /* Delete redundant computations. |
7506f491 DE |
2514 | Deletion is done by changing the insn to copy the `reaching_reg' of |
2515 | the expression into the result of the SET. It is left to later passes | |
2516 | (cprop, cse2, flow, combine, regmove) to propagate the copy or eliminate it. | |
2517 | ||
43c8a043 | 2518 | Return nonzero if a change is made. */ |
7506f491 DE |
2519 | |
2520 | static int | |
1d088dee | 2521 | pre_delete (void) |
7506f491 | 2522 | { |
2e653e39 | 2523 | unsigned int i; |
63bc1d05 | 2524 | int changed; |
c4c81601 RK |
2525 | struct expr *expr; |
2526 | struct occr *occr; | |
a65f3558 | 2527 | |
7506f491 | 2528 | changed = 0; |
02280659 | 2529 | for (i = 0; i < expr_hash_table.size; i++) |
43c8a043 | 2530 | for (expr = expr_hash_table.table[i]; expr; expr = expr->next_same_hash) |
c4c81601 RK |
2531 | { |
2532 | int indx = expr->bitmap_index; | |
7506f491 | 2533 | |
43c8a043 | 2534 | /* We only need to search antic_occr since we require ANTLOC != 0. */ |
c4c81601 RK |
2535 | for (occr = expr->antic_occr; occr != NULL; occr = occr->next) |
2536 | { | |
2537 | rtx insn = occr->insn; | |
2538 | rtx set; | |
e2d2ed72 | 2539 | basic_block bb = BLOCK_FOR_INSN (insn); |
7506f491 | 2540 | |
073089a7 | 2541 | /* We only delete insns that have a single_set. */ |
d7c028c0 | 2542 | if (bitmap_bit_p (pre_delete_map[bb->index], indx) |
6fb5fa3c DB |
2543 | && (set = single_set (insn)) != 0 |
2544 | && dbg_cnt (pre_insn)) | |
c4c81601 | 2545 | { |
c4c81601 RK |
2546 | /* Create a pseudo-reg to store the result of reaching |
2547 | expressions into. Get the mode for the new pseudo from | |
2548 | the mode of the original destination pseudo. */ | |
2549 | if (expr->reaching_reg == NULL) | |
46b71b03 | 2550 | expr->reaching_reg = gen_reg_rtx_and_attrs (SET_DEST (set)); |
c4c81601 | 2551 | |
43c8a043 | 2552 | gcse_emit_move_after (SET_DEST (set), expr->reaching_reg, insn); |
10d1bb36 JH |
2553 | delete_insn (insn); |
2554 | occr->deleted_p = 1; | |
10d1bb36 JH |
2555 | changed = 1; |
2556 | gcse_subst_count++; | |
7506f491 | 2557 | |
10d22567 | 2558 | if (dump_file) |
c4c81601 | 2559 | { |
10d22567 | 2560 | fprintf (dump_file, |
c4c81601 RK |
2561 | "PRE: redundant insn %d (expression %d) in ", |
2562 | INSN_UID (insn), indx); | |
10d22567 | 2563 | fprintf (dump_file, "bb %d, reaching reg is %d\n", |
0b17ab2f | 2564 | bb->index, REGNO (expr->reaching_reg)); |
c4c81601 RK |
2565 | } |
2566 | } | |
2567 | } | |
2568 | } | |
7506f491 DE |
2569 | |
2570 | return changed; | |
2571 | } | |
2572 | ||
2573 | /* Perform GCSE optimizations using PRE. | |
2574 | This is called by one_pre_gcse_pass after all the dataflow analysis | |
2575 | has been done. | |
2576 | ||
c4c81601 RK |
2577 | This is based on the original Morel-Renvoise paper Fred Chow's thesis, and |
2578 | lazy code motion from Knoop, Ruthing and Steffen as described in Advanced | |
2579 | Compiler Design and Implementation. | |
7506f491 | 2580 | |
c4c81601 RK |
2581 | ??? A new pseudo reg is created to hold the reaching expression. The nice |
2582 | thing about the classical approach is that it would try to use an existing | |
2583 | reg. If the register can't be adequately optimized [i.e. we introduce | |
2584 | reload problems], one could add a pass here to propagate the new register | |
2585 | through the block. | |
7506f491 | 2586 | |
c4c81601 RK |
2587 | ??? We don't handle single sets in PARALLELs because we're [currently] not |
2588 | able to copy the rest of the parallel when we insert copies to create full | |
2589 | redundancies from partial redundancies. However, there's no reason why we | |
2590 | can't handle PARALLELs in the cases where there are no partial | |
7506f491 DE |
2591 | redundancies. */ |
2592 | ||
2593 | static int | |
43c8a043 | 2594 | pre_gcse (struct edge_list *edge_list) |
7506f491 | 2595 | { |
2e653e39 RK |
2596 | unsigned int i; |
2597 | int did_insert, changed; | |
7506f491 | 2598 | struct expr **index_map; |
c4c81601 | 2599 | struct expr *expr; |
7506f491 DE |
2600 | |
2601 | /* Compute a mapping from expression number (`bitmap_index') to | |
2602 | hash table entry. */ | |
2603 | ||
5ed6ace5 | 2604 | index_map = XCNEWVEC (struct expr *, expr_hash_table.n_elems); |
02280659 | 2605 | for (i = 0; i < expr_hash_table.size; i++) |
43c8a043 | 2606 | for (expr = expr_hash_table.table[i]; expr; expr = expr->next_same_hash) |
c4c81601 | 2607 | index_map[expr->bitmap_index] = expr; |
7506f491 | 2608 | |
7506f491 DE |
2609 | /* Delete the redundant insns first so that |
2610 | - we know what register to use for the new insns and for the other | |
2611 | ones with reaching expressions | |
2612 | - we know which insns are redundant when we go to create copies */ | |
c4c81601 | 2613 | |
7506f491 | 2614 | changed = pre_delete (); |
a42cd965 | 2615 | did_insert = pre_edge_insert (edge_list, index_map); |
c4c81601 | 2616 | |
7506f491 | 2617 | /* In other places with reaching expressions, copy the expression to the |
a42cd965 | 2618 | specially allocated pseudo-reg that reaches the redundant expr. */ |
7506f491 | 2619 | pre_insert_copies (); |
a42cd965 AM |
2620 | if (did_insert) |
2621 | { | |
2622 | commit_edge_insertions (); | |
2623 | changed = 1; | |
2624 | } | |
7506f491 | 2625 | |
283a2545 | 2626 | free (index_map); |
7506f491 DE |
2627 | return changed; |
2628 | } | |
2629 | ||
2630 | /* Top level routine to perform one PRE GCSE pass. | |
2631 | ||
cc2902df | 2632 | Return nonzero if a change was made. */ |
7506f491 DE |
2633 | |
2634 | static int | |
5f39ad47 | 2635 | one_pre_gcse_pass (void) |
7506f491 DE |
2636 | { |
2637 | int changed = 0; | |
2638 | ||
2639 | gcse_subst_count = 0; | |
2640 | gcse_create_count = 0; | |
2641 | ||
5f39ad47 SB |
2642 | /* Return if there's nothing to do, or it is too expensive. */ |
2643 | if (n_basic_blocks <= NUM_FIXED_BLOCKS + 1 | |
2644 | || is_too_expensive (_("PRE disabled"))) | |
2645 | return 0; | |
2646 | ||
2647 | /* We need alias. */ | |
2648 | init_alias_analysis (); | |
2649 | ||
2650 | bytes_used = 0; | |
2651 | gcc_obstack_init (&gcse_obstack); | |
2652 | alloc_gcse_mem (); | |
2653 | ||
e45425ec | 2654 | alloc_hash_table (&expr_hash_table); |
a42cd965 | 2655 | add_noreturn_fake_exit_edges (); |
a13d4ebf AM |
2656 | if (flag_gcse_lm) |
2657 | compute_ld_motion_mems (); | |
2658 | ||
02280659 | 2659 | compute_hash_table (&expr_hash_table); |
43c8a043 EB |
2660 | if (flag_gcse_lm) |
2661 | trim_ld_motion_mems (); | |
10d22567 ZD |
2662 | if (dump_file) |
2663 | dump_hash_table (dump_file, "Expression", &expr_hash_table); | |
c4c81601 | 2664 | |
02280659 | 2665 | if (expr_hash_table.n_elems > 0) |
7506f491 | 2666 | { |
43c8a043 | 2667 | struct edge_list *edge_list; |
02280659 | 2668 | alloc_pre_mem (last_basic_block, expr_hash_table.n_elems); |
43c8a043 EB |
2669 | edge_list = compute_pre_data (); |
2670 | changed |= pre_gcse (edge_list); | |
a42cd965 | 2671 | free_edge_list (edge_list); |
7506f491 DE |
2672 | free_pre_mem (); |
2673 | } | |
c4c81601 | 2674 | |
43c8a043 EB |
2675 | if (flag_gcse_lm) |
2676 | free_ld_motion_mems (); | |
6809cbf9 | 2677 | remove_fake_exit_edges (); |
02280659 | 2678 | free_hash_table (&expr_hash_table); |
7506f491 | 2679 | |
5f39ad47 SB |
2680 | free_gcse_mem (); |
2681 | obstack_free (&gcse_obstack, NULL); | |
2682 | ||
2683 | /* We are finished with alias. */ | |
2684 | end_alias_analysis (); | |
2685 | ||
10d22567 | 2686 | if (dump_file) |
7506f491 | 2687 | { |
5f39ad47 SB |
2688 | fprintf (dump_file, "PRE GCSE of %s, %d basic blocks, %d bytes needed, ", |
2689 | current_function_name (), n_basic_blocks, bytes_used); | |
10d22567 | 2690 | fprintf (dump_file, "%d substs, %d insns created\n", |
c4c81601 | 2691 | gcse_subst_count, gcse_create_count); |
7506f491 DE |
2692 | } |
2693 | ||
2694 | return changed; | |
2695 | } | |
aeb2f500 | 2696 | \f |
cf7c4aa6 HPN |
2697 | /* If X contains any LABEL_REF's, add REG_LABEL_OPERAND notes for them |
2698 | to INSN. If such notes are added to an insn which references a | |
2699 | CODE_LABEL, the LABEL_NUSES count is incremented. We have to add | |
2700 | that note, because the following loop optimization pass requires | |
2701 | them. */ | |
aeb2f500 | 2702 | |
aeb2f500 JW |
2703 | /* ??? If there was a jump optimization pass after gcse and before loop, |
2704 | then we would not need to do this here, because jump would add the | |
cf7c4aa6 | 2705 | necessary REG_LABEL_OPERAND and REG_LABEL_TARGET notes. */ |
aeb2f500 JW |
2706 | |
2707 | static void | |
1d088dee | 2708 | add_label_notes (rtx x, rtx insn) |
aeb2f500 JW |
2709 | { |
2710 | enum rtx_code code = GET_CODE (x); | |
2711 | int i, j; | |
6f7d635c | 2712 | const char *fmt; |
aeb2f500 JW |
2713 | |
2714 | if (code == LABEL_REF && !LABEL_REF_NONLOCAL_P (x)) | |
2715 | { | |
6b3603c2 | 2716 | /* This code used to ignore labels that referred to dispatch tables to |
e0bb17a8 | 2717 | avoid flow generating (slightly) worse code. |
6b3603c2 | 2718 | |
ac7c5af5 JL |
2719 | We no longer ignore such label references (see LABEL_REF handling in |
2720 | mark_jump_label for additional information). */ | |
c4c81601 | 2721 | |
cb2f563b HPN |
2722 | /* There's no reason for current users to emit jump-insns with |
2723 | such a LABEL_REF, so we don't have to handle REG_LABEL_TARGET | |
2724 | notes. */ | |
2725 | gcc_assert (!JUMP_P (insn)); | |
65c5f2a6 ILT |
2726 | add_reg_note (insn, REG_LABEL_OPERAND, XEXP (x, 0)); |
2727 | ||
cb2f563b HPN |
2728 | if (LABEL_P (XEXP (x, 0))) |
2729 | LABEL_NUSES (XEXP (x, 0))++; | |
2730 | ||
aeb2f500 JW |
2731 | return; |
2732 | } | |
2733 | ||
c4c81601 | 2734 | for (i = GET_RTX_LENGTH (code) - 1, fmt = GET_RTX_FORMAT (code); i >= 0; i--) |
aeb2f500 JW |
2735 | { |
2736 | if (fmt[i] == 'e') | |
2737 | add_label_notes (XEXP (x, i), insn); | |
2738 | else if (fmt[i] == 'E') | |
2739 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
2740 | add_label_notes (XVECEXP (x, i, j), insn); | |
2741 | } | |
2742 | } | |
a65f3558 | 2743 | |
bb457bd9 JL |
2744 | /* Code Hoisting variables and subroutines. */ |
2745 | ||
2746 | /* Very busy expressions. */ | |
2747 | static sbitmap *hoist_vbein; | |
2748 | static sbitmap *hoist_vbeout; | |
2749 | ||
bb457bd9 | 2750 | /* ??? We could compute post dominators and run this algorithm in |
68e82b83 | 2751 | reverse to perform tail merging, doing so would probably be |
bb457bd9 JL |
2752 | more effective than the tail merging code in jump.c. |
2753 | ||
2754 | It's unclear if tail merging could be run in parallel with | |
2755 | code hoisting. It would be nice. */ | |
2756 | ||
2757 | /* Allocate vars used for code hoisting analysis. */ | |
2758 | ||
2759 | static void | |
1d088dee | 2760 | alloc_code_hoist_mem (int n_blocks, int n_exprs) |
bb457bd9 JL |
2761 | { |
2762 | antloc = sbitmap_vector_alloc (n_blocks, n_exprs); | |
2763 | transp = sbitmap_vector_alloc (n_blocks, n_exprs); | |
2764 | comp = sbitmap_vector_alloc (n_blocks, n_exprs); | |
2765 | ||
2766 | hoist_vbein = sbitmap_vector_alloc (n_blocks, n_exprs); | |
2767 | hoist_vbeout = sbitmap_vector_alloc (n_blocks, n_exprs); | |
bb457bd9 JL |
2768 | } |
2769 | ||
2770 | /* Free vars used for code hoisting analysis. */ | |
2771 | ||
2772 | static void | |
1d088dee | 2773 | free_code_hoist_mem (void) |
bb457bd9 | 2774 | { |
5a660bff DB |
2775 | sbitmap_vector_free (antloc); |
2776 | sbitmap_vector_free (transp); | |
2777 | sbitmap_vector_free (comp); | |
bb457bd9 | 2778 | |
5a660bff DB |
2779 | sbitmap_vector_free (hoist_vbein); |
2780 | sbitmap_vector_free (hoist_vbeout); | |
bb457bd9 | 2781 | |
d47cc544 | 2782 | free_dominance_info (CDI_DOMINATORS); |
bb457bd9 JL |
2783 | } |
2784 | ||
2785 | /* Compute the very busy expressions at entry/exit from each block. | |
2786 | ||
2787 | An expression is very busy if all paths from a given point | |
2788 | compute the expression. */ | |
2789 | ||
2790 | static void | |
1d088dee | 2791 | compute_code_hoist_vbeinout (void) |
bb457bd9 | 2792 | { |
e0082a72 ZD |
2793 | int changed, passes; |
2794 | basic_block bb; | |
bb457bd9 | 2795 | |
f61e445a LC |
2796 | bitmap_vector_clear (hoist_vbeout, last_basic_block); |
2797 | bitmap_vector_clear (hoist_vbein, last_basic_block); | |
bb457bd9 JL |
2798 | |
2799 | passes = 0; | |
2800 | changed = 1; | |
c4c81601 | 2801 | |
bb457bd9 JL |
2802 | while (changed) |
2803 | { | |
2804 | changed = 0; | |
c4c81601 | 2805 | |
bb457bd9 JL |
2806 | /* We scan the blocks in the reverse order to speed up |
2807 | the convergence. */ | |
e0082a72 | 2808 | FOR_EACH_BB_REVERSE (bb) |
bb457bd9 | 2809 | { |
e0082a72 | 2810 | if (bb->next_bb != EXIT_BLOCK_PTR) |
ce4c0015 | 2811 | { |
d7c028c0 LC |
2812 | bitmap_intersection_of_succs (hoist_vbeout[bb->index], |
2813 | hoist_vbein, bb); | |
ce4c0015 MK |
2814 | |
2815 | /* Include expressions in VBEout that are calculated | |
2816 | in BB and available at its end. */ | |
f61e445a | 2817 | bitmap_ior (hoist_vbeout[bb->index], |
ce4c0015 MK |
2818 | hoist_vbeout[bb->index], comp[bb->index]); |
2819 | } | |
f8423fea | 2820 | |
f61e445a | 2821 | changed |= bitmap_or_and (hoist_vbein[bb->index], |
f8423fea SB |
2822 | antloc[bb->index], |
2823 | hoist_vbeout[bb->index], | |
2824 | transp[bb->index]); | |
bb457bd9 | 2825 | } |
c4c81601 | 2826 | |
bb457bd9 JL |
2827 | passes++; |
2828 | } | |
2829 | ||
10d22567 | 2830 | if (dump_file) |
cad9aa15 MK |
2831 | { |
2832 | fprintf (dump_file, "hoisting vbeinout computation: %d passes\n", passes); | |
2833 | ||
2834 | FOR_EACH_BB (bb) | |
2835 | { | |
2836 | fprintf (dump_file, "vbein (%d): ", bb->index); | |
f61e445a | 2837 | dump_bitmap_file (dump_file, hoist_vbein[bb->index]); |
cad9aa15 | 2838 | fprintf (dump_file, "vbeout(%d): ", bb->index); |
f61e445a | 2839 | dump_bitmap_file (dump_file, hoist_vbeout[bb->index]); |
cad9aa15 MK |
2840 | } |
2841 | } | |
bb457bd9 JL |
2842 | } |
2843 | ||
2844 | /* Top level routine to do the dataflow analysis needed by code hoisting. */ | |
2845 | ||
2846 | static void | |
1d088dee | 2847 | compute_code_hoist_data (void) |
bb457bd9 | 2848 | { |
02280659 | 2849 | compute_local_properties (transp, comp, antloc, &expr_hash_table); |
9b774782 | 2850 | prune_expressions (false); |
bb457bd9 | 2851 | compute_code_hoist_vbeinout (); |
d47cc544 | 2852 | calculate_dominance_info (CDI_DOMINATORS); |
10d22567 ZD |
2853 | if (dump_file) |
2854 | fprintf (dump_file, "\n"); | |
bb457bd9 JL |
2855 | } |
2856 | ||
4b8181c5 BC |
2857 | /* Update register pressure for BB when hoisting an expression from |
2858 | instruction FROM, if live ranges of inputs are shrunk. Also | |
2859 | maintain live_in information if live range of register referred | |
2860 | in FROM is shrunk. | |
2861 | ||
2862 | Return 0 if register pressure doesn't change, otherwise return | |
2863 | the number by which register pressure is decreased. | |
2864 | ||
2865 | NOTE: Register pressure won't be increased in this function. */ | |
2866 | ||
2867 | static int | |
2868 | update_bb_reg_pressure (basic_block bb, rtx from) | |
2869 | { | |
2870 | rtx dreg, insn; | |
2871 | basic_block succ_bb; | |
2872 | df_ref *op, op_ref; | |
2873 | edge succ; | |
2874 | edge_iterator ei; | |
2875 | int decreased_pressure = 0; | |
2876 | int nregs; | |
2877 | enum reg_class pressure_class; | |
2878 | ||
2879 | for (op = DF_INSN_USES (from); *op; op++) | |
2880 | { | |
2881 | dreg = DF_REF_REAL_REG (*op); | |
2882 | /* The live range of register is shrunk only if it isn't: | |
2883 | 1. referred on any path from the end of this block to EXIT, or | |
2884 | 2. referred by insns other than FROM in this block. */ | |
2885 | FOR_EACH_EDGE (succ, ei, bb->succs) | |
2886 | { | |
2887 | succ_bb = succ->dest; | |
2888 | if (succ_bb == EXIT_BLOCK_PTR) | |
2889 | continue; | |
2890 | ||
2891 | if (bitmap_bit_p (BB_DATA (succ_bb)->live_in, REGNO (dreg))) | |
2892 | break; | |
2893 | } | |
2894 | if (succ != NULL) | |
2895 | continue; | |
2896 | ||
2897 | op_ref = DF_REG_USE_CHAIN (REGNO (dreg)); | |
2898 | for (; op_ref; op_ref = DF_REF_NEXT_REG (op_ref)) | |
2899 | { | |
2900 | if (!DF_REF_INSN_INFO (op_ref)) | |
2901 | continue; | |
2902 | ||
2903 | insn = DF_REF_INSN (op_ref); | |
2904 | if (BLOCK_FOR_INSN (insn) == bb | |
2905 | && NONDEBUG_INSN_P (insn) && insn != from) | |
2906 | break; | |
2907 | } | |
2908 | ||
2909 | pressure_class = get_regno_pressure_class (REGNO (dreg), &nregs); | |
2910 | /* Decrease register pressure and update live_in information for | |
2911 | this block. */ | |
2912 | if (!op_ref && pressure_class != NO_REGS) | |
2913 | { | |
2914 | decreased_pressure += nregs; | |
2915 | BB_DATA (bb)->max_reg_pressure[pressure_class] -= nregs; | |
2916 | bitmap_clear_bit (BB_DATA (bb)->live_in, REGNO (dreg)); | |
2917 | } | |
2918 | } | |
2919 | return decreased_pressure; | |
2920 | } | |
2921 | ||
b11f0116 BC |
2922 | /* Determine if the expression EXPR should be hoisted to EXPR_BB up in |
2923 | flow graph, if it can reach BB unimpared. Stop the search if the | |
2924 | expression would need to be moved more than DISTANCE instructions. | |
2925 | ||
2926 | DISTANCE is the number of instructions through which EXPR can be | |
2927 | hoisted up in flow graph. | |
2928 | ||
2929 | BB_SIZE points to an array which contains the number of instructions | |
2930 | for each basic block. | |
2931 | ||
2932 | PRESSURE_CLASS and NREGS are register class and number of hard registers | |
2933 | for storing EXPR. | |
2934 | ||
2935 | HOISTED_BBS points to a bitmap indicating basic blocks through which | |
2936 | EXPR is hoisted. | |
bb457bd9 | 2937 | |
4b8181c5 BC |
2938 | FROM is the instruction from which EXPR is hoisted. |
2939 | ||
bb457bd9 JL |
2940 | It's unclear exactly what Muchnick meant by "unimpared". It seems |
2941 | to me that the expression must either be computed or transparent in | |
2942 | *every* block in the path(s) from EXPR_BB to BB. Any other definition | |
2943 | would allow the expression to be hoisted out of loops, even if | |
2944 | the expression wasn't a loop invariant. | |
2945 | ||
2946 | Contrast this to reachability for PRE where an expression is | |
2947 | considered reachable if *any* path reaches instead of *all* | |
2948 | paths. */ | |
2949 | ||
2950 | static int | |
b11f0116 BC |
2951 | should_hoist_expr_to_dom (basic_block expr_bb, struct expr *expr, |
2952 | basic_block bb, sbitmap visited, int distance, | |
2953 | int *bb_size, enum reg_class pressure_class, | |
4b8181c5 | 2954 | int *nregs, bitmap hoisted_bbs, rtx from) |
bb457bd9 | 2955 | { |
b11f0116 | 2956 | unsigned int i; |
bb457bd9 | 2957 | edge pred; |
628f6a4e | 2958 | edge_iterator ei; |
b11f0116 | 2959 | sbitmap_iterator sbi; |
283a2545 | 2960 | int visited_allocated_locally = 0; |
4b8181c5 | 2961 | int decreased_pressure = 0; |
589005ff | 2962 | |
4b8181c5 BC |
2963 | if (flag_ira_hoist_pressure) |
2964 | { | |
2965 | /* Record old information of basic block BB when it is visited | |
2966 | at the first time. */ | |
2967 | if (!bitmap_bit_p (hoisted_bbs, bb->index)) | |
2968 | { | |
2969 | struct bb_data *data = BB_DATA (bb); | |
2970 | bitmap_copy (data->backup, data->live_in); | |
2971 | data->old_pressure = data->max_reg_pressure[pressure_class]; | |
2972 | } | |
2973 | decreased_pressure = update_bb_reg_pressure (bb, from); | |
2974 | } | |
20160347 MK |
2975 | /* Terminate the search if distance, for which EXPR is allowed to move, |
2976 | is exhausted. */ | |
2977 | if (distance > 0) | |
2978 | { | |
4b8181c5 BC |
2979 | if (flag_ira_hoist_pressure) |
2980 | { | |
2981 | /* Prefer to hoist EXPR if register pressure is decreased. */ | |
2982 | if (decreased_pressure > *nregs) | |
2983 | distance += bb_size[bb->index]; | |
2984 | /* Let EXPR be hoisted through basic block at no cost if one | |
2985 | of following conditions is satisfied: | |
2986 | ||
2987 | 1. The basic block has low register pressure. | |
2988 | 2. Register pressure won't be increases after hoisting EXPR. | |
2989 | ||
2990 | Constant expressions is handled conservatively, because | |
2991 | hoisting constant expression aggressively results in worse | |
2992 | code. This decision is made by the observation of CSiBE | |
2993 | on ARM target, while it has no obvious effect on other | |
2994 | targets like x86, x86_64, mips and powerpc. */ | |
2995 | else if (CONST_INT_P (expr->expr) | |
2996 | || (BB_DATA (bb)->max_reg_pressure[pressure_class] | |
2997 | >= ira_class_hard_regs_num[pressure_class] | |
2998 | && decreased_pressure < *nregs)) | |
2999 | distance -= bb_size[bb->index]; | |
3000 | } | |
3001 | else | |
b11f0116 | 3002 | distance -= bb_size[bb->index]; |
20160347 MK |
3003 | |
3004 | if (distance <= 0) | |
3005 | return 0; | |
3006 | } | |
3007 | else | |
3008 | gcc_assert (distance == 0); | |
bb457bd9 JL |
3009 | |
3010 | if (visited == NULL) | |
3011 | { | |
8e42ace1 | 3012 | visited_allocated_locally = 1; |
8cba9a05 | 3013 | visited = sbitmap_alloc (last_basic_block); |
f61e445a | 3014 | bitmap_clear (visited); |
bb457bd9 JL |
3015 | } |
3016 | ||
628f6a4e | 3017 | FOR_EACH_EDGE (pred, ei, bb->preds) |
bb457bd9 | 3018 | { |
e2d2ed72 | 3019 | basic_block pred_bb = pred->src; |
bb457bd9 JL |
3020 | |
3021 | if (pred->src == ENTRY_BLOCK_PTR) | |
3022 | break; | |
f305679f JH |
3023 | else if (pred_bb == expr_bb) |
3024 | continue; | |
d7c028c0 | 3025 | else if (bitmap_bit_p (visited, pred_bb->index)) |
bb457bd9 | 3026 | continue; |
d7c028c0 | 3027 | else if (! bitmap_bit_p (transp[pred_bb->index], expr->bitmap_index)) |
bb457bd9 JL |
3028 | break; |
3029 | /* Not killed. */ | |
3030 | else | |
3031 | { | |
d7c028c0 | 3032 | bitmap_set_bit (visited, pred_bb->index); |
b11f0116 BC |
3033 | if (! should_hoist_expr_to_dom (expr_bb, expr, pred_bb, |
3034 | visited, distance, bb_size, | |
4b8181c5 BC |
3035 | pressure_class, nregs, |
3036 | hoisted_bbs, from)) | |
bb457bd9 JL |
3037 | break; |
3038 | } | |
3039 | } | |
589005ff | 3040 | if (visited_allocated_locally) |
b11f0116 BC |
3041 | { |
3042 | /* If EXPR can be hoisted to expr_bb, record basic blocks through | |
4b8181c5 | 3043 | which EXPR is hoisted in hoisted_bbs. */ |
b11f0116 BC |
3044 | if (flag_ira_hoist_pressure && !pred) |
3045 | { | |
4b8181c5 BC |
3046 | /* Record the basic block from which EXPR is hoisted. */ |
3047 | bitmap_set_bit (visited, bb->index); | |
d4ac4ce2 | 3048 | EXECUTE_IF_SET_IN_BITMAP (visited, 0, i, sbi) |
4b8181c5 | 3049 | bitmap_set_bit (hoisted_bbs, i); |
b11f0116 BC |
3050 | } |
3051 | sbitmap_free (visited); | |
3052 | } | |
c4c81601 | 3053 | |
bb457bd9 JL |
3054 | return (pred == NULL); |
3055 | } | |
3056 | \f | |
073a8998 | 3057 | /* Find occurrence in BB. */ |
43c8a043 | 3058 | |
20160347 MK |
3059 | static struct occr * |
3060 | find_occr_in_bb (struct occr *occr, basic_block bb) | |
3061 | { | |
3062 | /* Find the right occurrence of this expression. */ | |
3063 | while (occr && BLOCK_FOR_INSN (occr->insn) != bb) | |
3064 | occr = occr->next; | |
3065 | ||
3066 | return occr; | |
3067 | } | |
3068 | ||
b11f0116 BC |
3069 | /* Actually perform code hoisting. |
3070 | ||
3071 | The code hoisting pass can hoist multiple computations of the same | |
3072 | expression along dominated path to a dominating basic block, like | |
3073 | from b2/b3 to b1 as depicted below: | |
3074 | ||
3075 | b1 ------ | |
3076 | /\ | | |
3077 | / \ | | |
3078 | bx by distance | |
3079 | / \ | | |
3080 | / \ | | |
3081 | b2 b3 ------ | |
3082 | ||
3083 | Unfortunately code hoisting generally extends the live range of an | |
3084 | output pseudo register, which increases register pressure and hurts | |
3085 | register allocation. To address this issue, an attribute MAX_DISTANCE | |
3086 | is computed and attached to each expression. The attribute is computed | |
3087 | from rtx cost of the corresponding expression and it's used to control | |
3088 | how long the expression can be hoisted up in flow graph. As the | |
3089 | expression is hoisted up in flow graph, GCC decreases its DISTANCE | |
4b8181c5 BC |
3090 | and stops the hoist if DISTANCE reaches 0. Code hoisting can decrease |
3091 | register pressure if live ranges of inputs are shrunk. | |
b11f0116 BC |
3092 | |
3093 | Option "-fira-hoist-pressure" implements register pressure directed | |
3094 | hoist based on upper method. The rationale is: | |
3095 | 1. Calculate register pressure for each basic block by reusing IRA | |
3096 | facility. | |
3097 | 2. When expression is hoisted through one basic block, GCC checks | |
4b8181c5 BC |
3098 | the change of live ranges for inputs/output. The basic block's |
3099 | register pressure will be increased because of extended live | |
3100 | range of output. However, register pressure will be decreased | |
3101 | if the live ranges of inputs are shrunk. | |
3102 | 3. After knowing how hoisting affects register pressure, GCC prefers | |
3103 | to hoist the expression if it can decrease register pressure, by | |
3104 | increasing DISTANCE of the corresponding expression. | |
3105 | 4. If hoisting the expression increases register pressure, GCC checks | |
3106 | register pressure of the basic block and decrease DISTANCE only if | |
3107 | the register pressure is high. In other words, expression will be | |
3108 | hoisted through at no cost if the basic block has low register | |
3109 | pressure. | |
3110 | 5. Update register pressure information for basic blocks through | |
3111 | which expression is hoisted. */ | |
c4c81601 | 3112 | |
5f39ad47 | 3113 | static int |
1d088dee | 3114 | hoist_code (void) |
bb457bd9 | 3115 | { |
e0082a72 | 3116 | basic_block bb, dominated; |
cad9aa15 MK |
3117 | VEC (basic_block, heap) *dom_tree_walk; |
3118 | unsigned int dom_tree_walk_index; | |
66f97d31 | 3119 | VEC (basic_block, heap) *domby; |
b11f0116 | 3120 | unsigned int i, j, k; |
bb457bd9 | 3121 | struct expr **index_map; |
c4c81601 | 3122 | struct expr *expr; |
20160347 MK |
3123 | int *to_bb_head; |
3124 | int *bb_size; | |
5f39ad47 | 3125 | int changed = 0; |
b11f0116 BC |
3126 | struct bb_data *data; |
3127 | /* Basic blocks that have occurrences reachable from BB. */ | |
3128 | bitmap from_bbs; | |
3129 | /* Basic blocks through which expr is hoisted. */ | |
3130 | bitmap hoisted_bbs = NULL; | |
3131 | bitmap_iterator bi; | |
bb457bd9 | 3132 | |
bb457bd9 JL |
3133 | /* Compute a mapping from expression number (`bitmap_index') to |
3134 | hash table entry. */ | |
3135 | ||
5ed6ace5 | 3136 | index_map = XCNEWVEC (struct expr *, expr_hash_table.n_elems); |
02280659 | 3137 | for (i = 0; i < expr_hash_table.size; i++) |
43c8a043 | 3138 | for (expr = expr_hash_table.table[i]; expr; expr = expr->next_same_hash) |
c4c81601 | 3139 | index_map[expr->bitmap_index] = expr; |
bb457bd9 | 3140 | |
20160347 MK |
3141 | /* Calculate sizes of basic blocks and note how far |
3142 | each instruction is from the start of its block. We then use this | |
3143 | data to restrict distance an expression can travel. */ | |
3144 | ||
3145 | to_bb_head = XCNEWVEC (int, get_max_uid ()); | |
3146 | bb_size = XCNEWVEC (int, last_basic_block); | |
3147 | ||
3148 | FOR_EACH_BB (bb) | |
3149 | { | |
3150 | rtx insn; | |
20160347 MK |
3151 | int to_head; |
3152 | ||
20160347 | 3153 | to_head = 0; |
05b5ea34 | 3154 | FOR_BB_INSNS (bb, insn) |
20160347 MK |
3155 | { |
3156 | /* Don't count debug instructions to avoid them affecting | |
3157 | decision choices. */ | |
3158 | if (NONDEBUG_INSN_P (insn)) | |
3159 | to_bb_head[INSN_UID (insn)] = to_head++; | |
20160347 MK |
3160 | } |
3161 | ||
3162 | bb_size[bb->index] = to_head; | |
3163 | } | |
3164 | ||
cad9aa15 MK |
3165 | gcc_assert (EDGE_COUNT (ENTRY_BLOCK_PTR->succs) == 1 |
3166 | && (EDGE_SUCC (ENTRY_BLOCK_PTR, 0)->dest | |
3167 | == ENTRY_BLOCK_PTR->next_bb)); | |
3168 | ||
b11f0116 BC |
3169 | from_bbs = BITMAP_ALLOC (NULL); |
3170 | if (flag_ira_hoist_pressure) | |
3171 | hoisted_bbs = BITMAP_ALLOC (NULL); | |
3172 | ||
cad9aa15 MK |
3173 | dom_tree_walk = get_all_dominated_blocks (CDI_DOMINATORS, |
3174 | ENTRY_BLOCK_PTR->next_bb); | |
3175 | ||
bb457bd9 JL |
3176 | /* Walk over each basic block looking for potentially hoistable |
3177 | expressions, nothing gets hoisted from the entry block. */ | |
ac47786e | 3178 | FOR_EACH_VEC_ELT (basic_block, dom_tree_walk, dom_tree_walk_index, bb) |
bb457bd9 | 3179 | { |
cad9aa15 MK |
3180 | domby = get_dominated_to_depth (CDI_DOMINATORS, bb, MAX_HOIST_DEPTH); |
3181 | ||
3182 | if (VEC_length (basic_block, domby) == 0) | |
3183 | continue; | |
bb457bd9 JL |
3184 | |
3185 | /* Examine each expression that is very busy at the exit of this | |
3186 | block. These are the potentially hoistable expressions. */ | |
5829cc0f | 3187 | for (i = 0; i < SBITMAP_SIZE (hoist_vbeout[bb->index]); i++) |
bb457bd9 | 3188 | { |
d7c028c0 | 3189 | if (bitmap_bit_p (hoist_vbeout[bb->index], i)) |
bb457bd9 | 3190 | { |
b11f0116 BC |
3191 | int nregs = 0; |
3192 | enum reg_class pressure_class = NO_REGS; | |
cad9aa15 MK |
3193 | /* Current expression. */ |
3194 | struct expr *expr = index_map[i]; | |
073a8998 | 3195 | /* Number of occurrences of EXPR that can be hoisted to BB. */ |
cad9aa15 | 3196 | int hoistable = 0; |
073a8998 | 3197 | /* Occurrences reachable from BB. */ |
cad9aa15 MK |
3198 | VEC (occr_t, heap) *occrs_to_hoist = NULL; |
3199 | /* We want to insert the expression into BB only once, so | |
3200 | note when we've inserted it. */ | |
3201 | int insn_inserted_p; | |
3202 | occr_t occr; | |
3203 | ||
ce4c0015 | 3204 | /* If an expression is computed in BB and is available at end of |
073a8998 | 3205 | BB, hoist all occurrences dominated by BB to BB. */ |
d7c028c0 | 3206 | if (bitmap_bit_p (comp[bb->index], i)) |
cad9aa15 MK |
3207 | { |
3208 | occr = find_occr_in_bb (expr->antic_occr, bb); | |
3209 | ||
3210 | if (occr) | |
3211 | { | |
073a8998 | 3212 | /* An occurrence might've been already deleted |
cad9aa15 | 3213 | while processing a dominator of BB. */ |
2d36b47f | 3214 | if (!occr->deleted_p) |
cad9aa15 MK |
3215 | { |
3216 | gcc_assert (NONDEBUG_INSN_P (occr->insn)); | |
3217 | hoistable++; | |
3218 | } | |
3219 | } | |
3220 | else | |
3221 | hoistable++; | |
3222 | } | |
ce4c0015 | 3223 | |
bb457bd9 JL |
3224 | /* We've found a potentially hoistable expression, now |
3225 | we look at every block BB dominates to see if it | |
3226 | computes the expression. */ | |
ac47786e | 3227 | FOR_EACH_VEC_ELT (basic_block, domby, j, dominated) |
bb457bd9 | 3228 | { |
20160347 MK |
3229 | int max_distance; |
3230 | ||
bb457bd9 | 3231 | /* Ignore self dominance. */ |
c635a1ec | 3232 | if (bb == dominated) |
bb457bd9 | 3233 | continue; |
bb457bd9 JL |
3234 | /* We've found a dominated block, now see if it computes |
3235 | the busy expression and whether or not moving that | |
3236 | expression to the "beginning" of that block is safe. */ | |
d7c028c0 | 3237 | if (!bitmap_bit_p (antloc[dominated->index], i)) |
bb457bd9 JL |
3238 | continue; |
3239 | ||
cad9aa15 MK |
3240 | occr = find_occr_in_bb (expr->antic_occr, dominated); |
3241 | gcc_assert (occr); | |
20160347 | 3242 | |
073a8998 | 3243 | /* An occurrence might've been already deleted |
cad9aa15 MK |
3244 | while processing a dominator of BB. */ |
3245 | if (occr->deleted_p) | |
2d36b47f | 3246 | continue; |
cad9aa15 MK |
3247 | gcc_assert (NONDEBUG_INSN_P (occr->insn)); |
3248 | ||
3249 | max_distance = expr->max_distance; | |
3250 | if (max_distance > 0) | |
3251 | /* Adjust MAX_DISTANCE to account for the fact that | |
3252 | OCCR won't have to travel all of DOMINATED, but | |
3253 | only part of it. */ | |
3254 | max_distance += (bb_size[dominated->index] | |
3255 | - to_bb_head[INSN_UID (occr->insn)]); | |
20160347 | 3256 | |
b11f0116 BC |
3257 | pressure_class = get_pressure_class_and_nregs (occr->insn, |
3258 | &nregs); | |
3259 | ||
3260 | /* Note if the expression should be hoisted from the dominated | |
3261 | block to BB if it can reach DOMINATED unimpared. | |
bb457bd9 JL |
3262 | |
3263 | Keep track of how many times this expression is hoistable | |
3264 | from a dominated block into BB. */ | |
b11f0116 BC |
3265 | if (should_hoist_expr_to_dom (bb, expr, dominated, NULL, |
3266 | max_distance, bb_size, | |
3267 | pressure_class, &nregs, | |
4b8181c5 | 3268 | hoisted_bbs, occr->insn)) |
cad9aa15 MK |
3269 | { |
3270 | hoistable++; | |
3271 | VEC_safe_push (occr_t, heap, | |
3272 | occrs_to_hoist, occr); | |
3273 | bitmap_set_bit (from_bbs, dominated->index); | |
3274 | } | |
bb457bd9 JL |
3275 | } |
3276 | ||
ff7cc307 | 3277 | /* If we found more than one hoistable occurrence of this |
cad9aa15 | 3278 | expression, then note it in the vector of expressions to |
bb457bd9 JL |
3279 | hoist. It makes no sense to hoist things which are computed |
3280 | in only one BB, and doing so tends to pessimize register | |
3281 | allocation. One could increase this value to try harder | |
3282 | to avoid any possible code expansion due to register | |
3283 | allocation issues; however experiments have shown that | |
3284 | the vast majority of hoistable expressions are only movable | |
e0bb17a8 | 3285 | from two successors, so raising this threshold is likely |
bb457bd9 | 3286 | to nullify any benefit we get from code hoisting. */ |
62a3f636 | 3287 | if (hoistable > 1 && dbg_cnt (hoist_insn)) |
bb457bd9 | 3288 | { |
cad9aa15 | 3289 | /* If (hoistable != VEC_length), then there is |
073a8998 | 3290 | an occurrence of EXPR in BB itself. Don't waste |
cad9aa15 MK |
3291 | time looking for LCA in this case. */ |
3292 | if ((unsigned) hoistable | |
3293 | == VEC_length (occr_t, occrs_to_hoist)) | |
3294 | { | |
3295 | basic_block lca; | |
3296 | ||
3297 | lca = nearest_common_dominator_for_set (CDI_DOMINATORS, | |
3298 | from_bbs); | |
3299 | if (lca != bb) | |
073a8998 | 3300 | /* Punt, it's better to hoist these occurrences to |
cad9aa15 MK |
3301 | LCA. */ |
3302 | VEC_free (occr_t, heap, occrs_to_hoist); | |
3303 | } | |
bb457bd9 | 3304 | } |
cad9aa15 MK |
3305 | else |
3306 | /* Punt, no point hoisting a single occurence. */ | |
3307 | VEC_free (occr_t, heap, occrs_to_hoist); | |
bb457bd9 | 3308 | |
b11f0116 BC |
3309 | if (flag_ira_hoist_pressure |
3310 | && !VEC_empty (occr_t, occrs_to_hoist)) | |
3311 | { | |
4b8181c5 BC |
3312 | /* Increase register pressure of basic blocks to which |
3313 | expr is hoisted because of extended live range of | |
3314 | output. */ | |
b11f0116 BC |
3315 | data = BB_DATA (bb); |
3316 | data->max_reg_pressure[pressure_class] += nregs; | |
4b8181c5 BC |
3317 | EXECUTE_IF_SET_IN_BITMAP (hoisted_bbs, 0, k, bi) |
3318 | { | |
3319 | data = BB_DATA (BASIC_BLOCK (k)); | |
3320 | data->max_reg_pressure[pressure_class] += nregs; | |
3321 | } | |
b11f0116 BC |
3322 | } |
3323 | else if (flag_ira_hoist_pressure) | |
3324 | { | |
4b8181c5 BC |
3325 | /* Restore register pressure and live_in info for basic |
3326 | blocks recorded in hoisted_bbs when expr will not be | |
3327 | hoisted. */ | |
b11f0116 BC |
3328 | EXECUTE_IF_SET_IN_BITMAP (hoisted_bbs, 0, k, bi) |
3329 | { | |
3330 | data = BB_DATA (BASIC_BLOCK (k)); | |
4b8181c5 BC |
3331 | bitmap_copy (data->live_in, data->backup); |
3332 | data->max_reg_pressure[pressure_class] | |
3333 | = data->old_pressure; | |
b11f0116 BC |
3334 | } |
3335 | } | |
3336 | ||
3337 | if (flag_ira_hoist_pressure) | |
3338 | bitmap_clear (hoisted_bbs); | |
3339 | ||
cad9aa15 | 3340 | insn_inserted_p = 0; |
bb457bd9 | 3341 | |
073a8998 | 3342 | /* Walk through occurrences of I'th expressions we want |
cad9aa15 | 3343 | to hoist to BB and make the transformations. */ |
ac47786e | 3344 | FOR_EACH_VEC_ELT (occr_t, occrs_to_hoist, j, occr) |
bb457bd9 | 3345 | { |
cad9aa15 MK |
3346 | rtx insn; |
3347 | rtx set; | |
3348 | ||
3349 | gcc_assert (!occr->deleted_p); | |
3350 | ||
3351 | insn = occr->insn; | |
3352 | set = single_set (insn); | |
3353 | gcc_assert (set); | |
3354 | ||
3355 | /* Create a pseudo-reg to store the result of reaching | |
3356 | expressions into. Get the mode for the new pseudo | |
3357 | from the mode of the original destination pseudo. | |
3358 | ||
3359 | It is important to use new pseudos whenever we | |
3360 | emit a set. This will allow reload to use | |
3361 | rematerialization for such registers. */ | |
3362 | if (!insn_inserted_p) | |
3363 | expr->reaching_reg | |
3364 | = gen_reg_rtx_and_attrs (SET_DEST (set)); | |
3365 | ||
43c8a043 | 3366 | gcse_emit_move_after (SET_DEST (set), expr->reaching_reg, |
cad9aa15 MK |
3367 | insn); |
3368 | delete_insn (insn); | |
3369 | occr->deleted_p = 1; | |
3370 | changed = 1; | |
3371 | gcse_subst_count++; | |
3372 | ||
3373 | if (!insn_inserted_p) | |
bb457bd9 | 3374 | { |
cad9aa15 MK |
3375 | insert_insn_end_basic_block (expr, bb); |
3376 | insn_inserted_p = 1; | |
bb457bd9 JL |
3377 | } |
3378 | } | |
cad9aa15 MK |
3379 | |
3380 | VEC_free (occr_t, heap, occrs_to_hoist); | |
3381 | bitmap_clear (from_bbs); | |
bb457bd9 JL |
3382 | } |
3383 | } | |
66f97d31 | 3384 | VEC_free (basic_block, heap, domby); |
bb457bd9 | 3385 | } |
c4c81601 | 3386 | |
cad9aa15 | 3387 | VEC_free (basic_block, heap, dom_tree_walk); |
b11f0116 BC |
3388 | BITMAP_FREE (from_bbs); |
3389 | if (flag_ira_hoist_pressure) | |
3390 | BITMAP_FREE (hoisted_bbs); | |
3391 | ||
20160347 MK |
3392 | free (bb_size); |
3393 | free (to_bb_head); | |
8e42ace1 | 3394 | free (index_map); |
5f39ad47 SB |
3395 | |
3396 | return changed; | |
bb457bd9 JL |
3397 | } |
3398 | ||
b11f0116 BC |
3399 | /* Return pressure class and number of needed hard registers (through |
3400 | *NREGS) of register REGNO. */ | |
3401 | static enum reg_class | |
3402 | get_regno_pressure_class (int regno, int *nregs) | |
3403 | { | |
3404 | if (regno >= FIRST_PSEUDO_REGISTER) | |
3405 | { | |
3406 | enum reg_class pressure_class; | |
3407 | ||
3408 | pressure_class = reg_allocno_class (regno); | |
3409 | pressure_class = ira_pressure_class_translate[pressure_class]; | |
3410 | *nregs | |
3411 | = ira_reg_class_max_nregs[pressure_class][PSEUDO_REGNO_MODE (regno)]; | |
3412 | return pressure_class; | |
3413 | } | |
3414 | else if (! TEST_HARD_REG_BIT (ira_no_alloc_regs, regno) | |
3415 | && ! TEST_HARD_REG_BIT (eliminable_regset, regno)) | |
3416 | { | |
3417 | *nregs = 1; | |
3418 | return ira_pressure_class_translate[REGNO_REG_CLASS (regno)]; | |
3419 | } | |
3420 | else | |
3421 | { | |
3422 | *nregs = 0; | |
3423 | return NO_REGS; | |
3424 | } | |
3425 | } | |
3426 | ||
3427 | /* Return pressure class and number of hard registers (through *NREGS) | |
3428 | for destination of INSN. */ | |
3429 | static enum reg_class | |
3430 | get_pressure_class_and_nregs (rtx insn, int *nregs) | |
3431 | { | |
3432 | rtx reg; | |
3433 | enum reg_class pressure_class; | |
3434 | rtx set = single_set (insn); | |
3435 | ||
3436 | /* Considered invariant insns have only one set. */ | |
3437 | gcc_assert (set != NULL_RTX); | |
3438 | reg = SET_DEST (set); | |
3439 | if (GET_CODE (reg) == SUBREG) | |
3440 | reg = SUBREG_REG (reg); | |
3441 | if (MEM_P (reg)) | |
3442 | { | |
3443 | *nregs = 0; | |
3444 | pressure_class = NO_REGS; | |
3445 | } | |
3446 | else | |
3447 | { | |
3448 | gcc_assert (REG_P (reg)); | |
3449 | pressure_class = reg_allocno_class (REGNO (reg)); | |
3450 | pressure_class = ira_pressure_class_translate[pressure_class]; | |
3451 | *nregs | |
3452 | = ira_reg_class_max_nregs[pressure_class][GET_MODE (SET_SRC (set))]; | |
3453 | } | |
3454 | return pressure_class; | |
3455 | } | |
3456 | ||
3457 | /* Increase (if INCR_P) or decrease current register pressure for | |
3458 | register REGNO. */ | |
3459 | static void | |
3460 | change_pressure (int regno, bool incr_p) | |
3461 | { | |
3462 | int nregs; | |
3463 | enum reg_class pressure_class; | |
3464 | ||
3465 | pressure_class = get_regno_pressure_class (regno, &nregs); | |
3466 | if (! incr_p) | |
3467 | curr_reg_pressure[pressure_class] -= nregs; | |
3468 | else | |
3469 | { | |
3470 | curr_reg_pressure[pressure_class] += nregs; | |
3471 | if (BB_DATA (curr_bb)->max_reg_pressure[pressure_class] | |
3472 | < curr_reg_pressure[pressure_class]) | |
3473 | BB_DATA (curr_bb)->max_reg_pressure[pressure_class] | |
3474 | = curr_reg_pressure[pressure_class]; | |
3475 | } | |
3476 | } | |
3477 | ||
3478 | /* Calculate register pressure for each basic block by walking insns | |
3479 | from last to first. */ | |
3480 | static void | |
3481 | calculate_bb_reg_pressure (void) | |
3482 | { | |
3483 | int i; | |
3484 | unsigned int j; | |
3485 | rtx insn; | |
3486 | basic_block bb; | |
3487 | bitmap curr_regs_live; | |
3488 | bitmap_iterator bi; | |
3489 | ||
3490 | ||
55a2c322 | 3491 | ira_setup_eliminable_regset (false); |
b11f0116 BC |
3492 | curr_regs_live = BITMAP_ALLOC (®_obstack); |
3493 | FOR_EACH_BB (bb) | |
3494 | { | |
3495 | curr_bb = bb; | |
4b8181c5 BC |
3496 | BB_DATA (bb)->live_in = BITMAP_ALLOC (NULL); |
3497 | BB_DATA (bb)->backup = BITMAP_ALLOC (NULL); | |
3498 | bitmap_copy (BB_DATA (bb)->live_in, df_get_live_in (bb)); | |
3499 | bitmap_copy (curr_regs_live, df_get_live_out (bb)); | |
b11f0116 BC |
3500 | for (i = 0; i < ira_pressure_classes_num; i++) |
3501 | curr_reg_pressure[ira_pressure_classes[i]] = 0; | |
3502 | EXECUTE_IF_SET_IN_BITMAP (curr_regs_live, 0, j, bi) | |
3503 | change_pressure (j, true); | |
3504 | ||
3505 | FOR_BB_INSNS_REVERSE (bb, insn) | |
3506 | { | |
3507 | rtx dreg; | |
3508 | int regno; | |
3509 | df_ref *def_rec, *use_rec; | |
3510 | ||
3511 | if (! NONDEBUG_INSN_P (insn)) | |
3512 | continue; | |
3513 | ||
3514 | for (def_rec = DF_INSN_DEFS (insn); *def_rec; def_rec++) | |
3515 | { | |
3516 | dreg = DF_REF_REAL_REG (*def_rec); | |
3517 | gcc_assert (REG_P (dreg)); | |
3518 | regno = REGNO (dreg); | |
3519 | if (!(DF_REF_FLAGS (*def_rec) | |
3520 | & (DF_REF_PARTIAL | DF_REF_CONDITIONAL))) | |
3521 | { | |
3522 | if (bitmap_clear_bit (curr_regs_live, regno)) | |
3523 | change_pressure (regno, false); | |
3524 | } | |
3525 | } | |
3526 | ||
3527 | for (use_rec = DF_INSN_USES (insn); *use_rec; use_rec++) | |
3528 | { | |
3529 | dreg = DF_REF_REAL_REG (*use_rec); | |
3530 | gcc_assert (REG_P (dreg)); | |
3531 | regno = REGNO (dreg); | |
3532 | if (bitmap_set_bit (curr_regs_live, regno)) | |
3533 | change_pressure (regno, true); | |
3534 | } | |
3535 | } | |
3536 | } | |
3537 | BITMAP_FREE (curr_regs_live); | |
3538 | ||
3539 | if (dump_file == NULL) | |
3540 | return; | |
3541 | ||
3542 | fprintf (dump_file, "\nRegister Pressure: \n"); | |
3543 | FOR_EACH_BB (bb) | |
3544 | { | |
3545 | fprintf (dump_file, " Basic block %d: \n", bb->index); | |
3546 | for (i = 0; (int) i < ira_pressure_classes_num; i++) | |
3547 | { | |
3548 | enum reg_class pressure_class; | |
3549 | ||
3550 | pressure_class = ira_pressure_classes[i]; | |
3551 | if (BB_DATA (bb)->max_reg_pressure[pressure_class] == 0) | |
3552 | continue; | |
3553 | ||
3554 | fprintf (dump_file, " %s=%d\n", reg_class_names[pressure_class], | |
3555 | BB_DATA (bb)->max_reg_pressure[pressure_class]); | |
3556 | } | |
3557 | } | |
3558 | fprintf (dump_file, "\n"); | |
3559 | } | |
3560 | ||
bb457bd9 JL |
3561 | /* Top level routine to perform one code hoisting (aka unification) pass |
3562 | ||
cc2902df | 3563 | Return nonzero if a change was made. */ |
bb457bd9 JL |
3564 | |
3565 | static int | |
1d088dee | 3566 | one_code_hoisting_pass (void) |
bb457bd9 JL |
3567 | { |
3568 | int changed = 0; | |
3569 | ||
5f39ad47 SB |
3570 | gcse_subst_count = 0; |
3571 | gcse_create_count = 0; | |
3572 | ||
3573 | /* Return if there's nothing to do, or it is too expensive. */ | |
3574 | if (n_basic_blocks <= NUM_FIXED_BLOCKS + 1 | |
3575 | || is_too_expensive (_("GCSE disabled"))) | |
3576 | return 0; | |
3577 | ||
20160347 MK |
3578 | doing_code_hoisting_p = true; |
3579 | ||
b11f0116 BC |
3580 | /* Calculate register pressure for each basic block. */ |
3581 | if (flag_ira_hoist_pressure) | |
3582 | { | |
3583 | regstat_init_n_sets_and_refs (); | |
3584 | ira_set_pseudo_classes (false, dump_file); | |
3585 | alloc_aux_for_blocks (sizeof (struct bb_data)); | |
3586 | calculate_bb_reg_pressure (); | |
3587 | regstat_free_n_sets_and_refs (); | |
3588 | } | |
3589 | ||
5f39ad47 SB |
3590 | /* We need alias. */ |
3591 | init_alias_analysis (); | |
3592 | ||
3593 | bytes_used = 0; | |
3594 | gcc_obstack_init (&gcse_obstack); | |
3595 | alloc_gcse_mem (); | |
3596 | ||
e45425ec | 3597 | alloc_hash_table (&expr_hash_table); |
02280659 | 3598 | compute_hash_table (&expr_hash_table); |
10d22567 ZD |
3599 | if (dump_file) |
3600 | dump_hash_table (dump_file, "Code Hosting Expressions", &expr_hash_table); | |
c4c81601 | 3601 | |
02280659 | 3602 | if (expr_hash_table.n_elems > 0) |
bb457bd9 | 3603 | { |
02280659 | 3604 | alloc_code_hoist_mem (last_basic_block, expr_hash_table.n_elems); |
bb457bd9 | 3605 | compute_code_hoist_data (); |
5f39ad47 | 3606 | changed = hoist_code (); |
bb457bd9 JL |
3607 | free_code_hoist_mem (); |
3608 | } | |
c4c81601 | 3609 | |
b11f0116 BC |
3610 | if (flag_ira_hoist_pressure) |
3611 | { | |
3612 | free_aux_for_blocks (); | |
3613 | free_reg_info (); | |
3614 | } | |
02280659 | 3615 | free_hash_table (&expr_hash_table); |
5f39ad47 SB |
3616 | free_gcse_mem (); |
3617 | obstack_free (&gcse_obstack, NULL); | |
3618 | ||
3619 | /* We are finished with alias. */ | |
3620 | end_alias_analysis (); | |
3621 | ||
3622 | if (dump_file) | |
3623 | { | |
3624 | fprintf (dump_file, "HOIST of %s, %d basic blocks, %d bytes needed, ", | |
3625 | current_function_name (), n_basic_blocks, bytes_used); | |
3626 | fprintf (dump_file, "%d substs, %d insns created\n", | |
3627 | gcse_subst_count, gcse_create_count); | |
3628 | } | |
bb457bd9 | 3629 | |
20160347 MK |
3630 | doing_code_hoisting_p = false; |
3631 | ||
bb457bd9 JL |
3632 | return changed; |
3633 | } | |
a13d4ebf | 3634 | \f |
43c8a043 EB |
3635 | /* Here we provide the things required to do store motion towards the exit. |
3636 | In order for this to be effective, gcse also needed to be taught how to | |
3637 | move a load when it is killed only by a store to itself. | |
a13d4ebf AM |
3638 | |
3639 | int i; | |
3640 | float a[10]; | |
3641 | ||
3642 | void foo(float scale) | |
3643 | { | |
3644 | for (i=0; i<10; i++) | |
3645 | a[i] *= scale; | |
3646 | } | |
3647 | ||
3648 | 'i' is both loaded and stored to in the loop. Normally, gcse cannot move | |
589005ff KH |
3649 | the load out since its live around the loop, and stored at the bottom |
3650 | of the loop. | |
a13d4ebf | 3651 | |
589005ff | 3652 | The 'Load Motion' referred to and implemented in this file is |
43c8a043 | 3653 | an enhancement to gcse which when using edge based LCM, recognizes |
a13d4ebf AM |
3654 | this situation and allows gcse to move the load out of the loop. |
3655 | ||
3656 | Once gcse has hoisted the load, store motion can then push this | |
3657 | load towards the exit, and we end up with no loads or stores of 'i' | |
3658 | in the loop. */ | |
3659 | ||
9727e468 RG |
3660 | static hashval_t |
3661 | pre_ldst_expr_hash (const void *p) | |
3662 | { | |
3663 | int do_not_record_p = 0; | |
1b4572a8 | 3664 | const struct ls_expr *const x = (const struct ls_expr *) p; |
43c8a043 EB |
3665 | return |
3666 | hash_rtx (x->pattern, GET_MODE (x->pattern), &do_not_record_p, NULL, false); | |
9727e468 RG |
3667 | } |
3668 | ||
3669 | static int | |
3670 | pre_ldst_expr_eq (const void *p1, const void *p2) | |
3671 | { | |
1b4572a8 KG |
3672 | const struct ls_expr *const ptr1 = (const struct ls_expr *) p1, |
3673 | *const ptr2 = (const struct ls_expr *) p2; | |
9727e468 RG |
3674 | return expr_equiv_p (ptr1->pattern, ptr2->pattern); |
3675 | } | |
3676 | ||
ff7cc307 | 3677 | /* This will search the ldst list for a matching expression. If it |
a13d4ebf AM |
3678 | doesn't find one, we create one and initialize it. */ |
3679 | ||
3680 | static struct ls_expr * | |
1d088dee | 3681 | ldst_entry (rtx x) |
a13d4ebf | 3682 | { |
b58b21d5 | 3683 | int do_not_record_p = 0; |
a13d4ebf | 3684 | struct ls_expr * ptr; |
b58b21d5 | 3685 | unsigned int hash; |
9727e468 RG |
3686 | void **slot; |
3687 | struct ls_expr e; | |
a13d4ebf | 3688 | |
0516f6fe SB |
3689 | hash = hash_rtx (x, GET_MODE (x), &do_not_record_p, |
3690 | NULL, /*have_reg_qty=*/false); | |
a13d4ebf | 3691 | |
9727e468 RG |
3692 | e.pattern = x; |
3693 | slot = htab_find_slot_with_hash (pre_ldst_table, &e, hash, INSERT); | |
3694 | if (*slot) | |
3695 | return (struct ls_expr *)*slot; | |
b58b21d5 | 3696 | |
5ed6ace5 | 3697 | ptr = XNEW (struct ls_expr); |
b58b21d5 RS |
3698 | |
3699 | ptr->next = pre_ldst_mems; | |
3700 | ptr->expr = NULL; | |
3701 | ptr->pattern = x; | |
3702 | ptr->pattern_regs = NULL_RTX; | |
3703 | ptr->loads = NULL_RTX; | |
3704 | ptr->stores = NULL_RTX; | |
3705 | ptr->reaching_reg = NULL_RTX; | |
3706 | ptr->invalid = 0; | |
3707 | ptr->index = 0; | |
3708 | ptr->hash_index = hash; | |
3709 | pre_ldst_mems = ptr; | |
9727e468 | 3710 | *slot = ptr; |
589005ff | 3711 | |
a13d4ebf AM |
3712 | return ptr; |
3713 | } | |
3714 | ||
3715 | /* Free up an individual ldst entry. */ | |
3716 | ||
589005ff | 3717 | static void |
1d088dee | 3718 | free_ldst_entry (struct ls_expr * ptr) |
a13d4ebf | 3719 | { |
aaa4ca30 AJ |
3720 | free_INSN_LIST_list (& ptr->loads); |
3721 | free_INSN_LIST_list (& ptr->stores); | |
a13d4ebf AM |
3722 | |
3723 | free (ptr); | |
3724 | } | |
3725 | ||
3726 | /* Free up all memory associated with the ldst list. */ | |
3727 | ||
3728 | static void | |
43c8a043 | 3729 | free_ld_motion_mems (void) |
a13d4ebf | 3730 | { |
35b5442a RG |
3731 | if (pre_ldst_table) |
3732 | htab_delete (pre_ldst_table); | |
9727e468 RG |
3733 | pre_ldst_table = NULL; |
3734 | ||
589005ff | 3735 | while (pre_ldst_mems) |
a13d4ebf AM |
3736 | { |
3737 | struct ls_expr * tmp = pre_ldst_mems; | |
3738 | ||
3739 | pre_ldst_mems = pre_ldst_mems->next; | |
3740 | ||
3741 | free_ldst_entry (tmp); | |
3742 | } | |
3743 | ||
3744 | pre_ldst_mems = NULL; | |
3745 | } | |
3746 | ||
3747 | /* Dump debugging info about the ldst list. */ | |
3748 | ||
3749 | static void | |
1d088dee | 3750 | print_ldst_list (FILE * file) |
a13d4ebf AM |
3751 | { |
3752 | struct ls_expr * ptr; | |
3753 | ||
3754 | fprintf (file, "LDST list: \n"); | |
3755 | ||
43c8a043 | 3756 | for (ptr = pre_ldst_mems; ptr != NULL; ptr = ptr->next) |
a13d4ebf AM |
3757 | { |
3758 | fprintf (file, " Pattern (%3d): ", ptr->index); | |
3759 | ||
3760 | print_rtl (file, ptr->pattern); | |
3761 | ||
3762 | fprintf (file, "\n Loads : "); | |
3763 | ||
3764 | if (ptr->loads) | |
3765 | print_rtl (file, ptr->loads); | |
3766 | else | |
3767 | fprintf (file, "(nil)"); | |
3768 | ||
3769 | fprintf (file, "\n Stores : "); | |
3770 | ||
3771 | if (ptr->stores) | |
3772 | print_rtl (file, ptr->stores); | |
3773 | else | |
3774 | fprintf (file, "(nil)"); | |
3775 | ||
3776 | fprintf (file, "\n\n"); | |
3777 | } | |
3778 | ||
3779 | fprintf (file, "\n"); | |
3780 | } | |
3781 | ||
3782 | /* Returns 1 if X is in the list of ldst only expressions. */ | |
3783 | ||
3784 | static struct ls_expr * | |
1d088dee | 3785 | find_rtx_in_ldst (rtx x) |
a13d4ebf | 3786 | { |
9727e468 RG |
3787 | struct ls_expr e; |
3788 | void **slot; | |
6375779a RG |
3789 | if (!pre_ldst_table) |
3790 | return NULL; | |
9727e468 RG |
3791 | e.pattern = x; |
3792 | slot = htab_find_slot (pre_ldst_table, &e, NO_INSERT); | |
3793 | if (!slot || ((struct ls_expr *)*slot)->invalid) | |
3794 | return NULL; | |
1b4572a8 | 3795 | return (struct ls_expr *) *slot; |
a13d4ebf | 3796 | } |
a13d4ebf AM |
3797 | \f |
3798 | /* Load Motion for loads which only kill themselves. */ | |
3799 | ||
43c8a043 EB |
3800 | /* Return true if x, a MEM, is a simple access with no side effects. |
3801 | These are the types of loads we consider for the ld_motion list, | |
3802 | otherwise we let the usual aliasing take care of it. */ | |
a13d4ebf | 3803 | |
589005ff | 3804 | static int |
ed7a4b4b | 3805 | simple_mem (const_rtx x) |
a13d4ebf | 3806 | { |
a13d4ebf AM |
3807 | if (MEM_VOLATILE_P (x)) |
3808 | return 0; | |
589005ff | 3809 | |
a13d4ebf AM |
3810 | if (GET_MODE (x) == BLKmode) |
3811 | return 0; | |
aaa4ca30 | 3812 | |
47a3dae1 | 3813 | /* If we are handling exceptions, we must be careful with memory references |
8f4f502f | 3814 | that may trap. If we are not, the behavior is undefined, so we may just |
47a3dae1 | 3815 | continue. */ |
8f4f502f | 3816 | if (cfun->can_throw_non_call_exceptions && may_trap_p (x)) |
98d3d336 RS |
3817 | return 0; |
3818 | ||
47a3dae1 ZD |
3819 | if (side_effects_p (x)) |
3820 | return 0; | |
589005ff | 3821 | |
47a3dae1 ZD |
3822 | /* Do not consider function arguments passed on stack. */ |
3823 | if (reg_mentioned_p (stack_pointer_rtx, x)) | |
3824 | return 0; | |
3825 | ||
3826 | if (flag_float_store && FLOAT_MODE_P (GET_MODE (x))) | |
3827 | return 0; | |
3828 | ||
3829 | return 1; | |
a13d4ebf AM |
3830 | } |
3831 | ||
589005ff KH |
3832 | /* Make sure there isn't a buried reference in this pattern anywhere. |
3833 | If there is, invalidate the entry for it since we're not capable | |
3834 | of fixing it up just yet.. We have to be sure we know about ALL | |
a13d4ebf AM |
3835 | loads since the aliasing code will allow all entries in the |
3836 | ld_motion list to not-alias itself. If we miss a load, we will get | |
589005ff | 3837 | the wrong value since gcse might common it and we won't know to |
a13d4ebf AM |
3838 | fix it up. */ |
3839 | ||
3840 | static void | |
1d088dee | 3841 | invalidate_any_buried_refs (rtx x) |
a13d4ebf AM |
3842 | { |
3843 | const char * fmt; | |
8e42ace1 | 3844 | int i, j; |
a13d4ebf AM |
3845 | struct ls_expr * ptr; |
3846 | ||
3847 | /* Invalidate it in the list. */ | |
7b1b4aed | 3848 | if (MEM_P (x) && simple_mem (x)) |
a13d4ebf AM |
3849 | { |
3850 | ptr = ldst_entry (x); | |
3851 | ptr->invalid = 1; | |
3852 | } | |
3853 | ||
3854 | /* Recursively process the insn. */ | |
3855 | fmt = GET_RTX_FORMAT (GET_CODE (x)); | |
589005ff | 3856 | |
a13d4ebf AM |
3857 | for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--) |
3858 | { | |
3859 | if (fmt[i] == 'e') | |
3860 | invalidate_any_buried_refs (XEXP (x, i)); | |
3861 | else if (fmt[i] == 'E') | |
3862 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
3863 | invalidate_any_buried_refs (XVECEXP (x, i, j)); | |
3864 | } | |
3865 | } | |
3866 | ||
4d3eb89a HPN |
3867 | /* Find all the 'simple' MEMs which are used in LOADs and STORES. Simple |
3868 | being defined as MEM loads and stores to symbols, with no side effects | |
3869 | and no registers in the expression. For a MEM destination, we also | |
3870 | check that the insn is still valid if we replace the destination with a | |
3871 | REG, as is done in update_ld_motion_stores. If there are any uses/defs | |
3872 | which don't match this criteria, they are invalidated and trimmed out | |
3873 | later. */ | |
a13d4ebf | 3874 | |
589005ff | 3875 | static void |
1d088dee | 3876 | compute_ld_motion_mems (void) |
a13d4ebf AM |
3877 | { |
3878 | struct ls_expr * ptr; | |
e0082a72 | 3879 | basic_block bb; |
a13d4ebf | 3880 | rtx insn; |
589005ff | 3881 | |
a13d4ebf | 3882 | pre_ldst_mems = NULL; |
43c8a043 EB |
3883 | pre_ldst_table |
3884 | = htab_create (13, pre_ldst_expr_hash, pre_ldst_expr_eq, NULL); | |
a13d4ebf | 3885 | |
e0082a72 | 3886 | FOR_EACH_BB (bb) |
a13d4ebf | 3887 | { |
eb232f4e | 3888 | FOR_BB_INSNS (bb, insn) |
a13d4ebf | 3889 | { |
b5b8b0ac | 3890 | if (NONDEBUG_INSN_P (insn)) |
a13d4ebf AM |
3891 | { |
3892 | if (GET_CODE (PATTERN (insn)) == SET) | |
3893 | { | |
3894 | rtx src = SET_SRC (PATTERN (insn)); | |
3895 | rtx dest = SET_DEST (PATTERN (insn)); | |
3896 | ||
3897 | /* Check for a simple LOAD... */ | |
7b1b4aed | 3898 | if (MEM_P (src) && simple_mem (src)) |
a13d4ebf AM |
3899 | { |
3900 | ptr = ldst_entry (src); | |
7b1b4aed | 3901 | if (REG_P (dest)) |
a13d4ebf AM |
3902 | ptr->loads = alloc_INSN_LIST (insn, ptr->loads); |
3903 | else | |
3904 | ptr->invalid = 1; | |
3905 | } | |
3906 | else | |
3907 | { | |
3908 | /* Make sure there isn't a buried load somewhere. */ | |
3909 | invalidate_any_buried_refs (src); | |
3910 | } | |
589005ff | 3911 | |
a13d4ebf AM |
3912 | /* Check for stores. Don't worry about aliased ones, they |
3913 | will block any movement we might do later. We only care | |
3914 | about this exact pattern since those are the only | |
3915 | circumstance that we will ignore the aliasing info. */ | |
7b1b4aed | 3916 | if (MEM_P (dest) && simple_mem (dest)) |
a13d4ebf AM |
3917 | { |
3918 | ptr = ldst_entry (dest); | |
589005ff | 3919 | |
7b1b4aed | 3920 | if (! MEM_P (src) |
4d3eb89a HPN |
3921 | && GET_CODE (src) != ASM_OPERANDS |
3922 | /* Check for REG manually since want_to_gcse_p | |
3923 | returns 0 for all REGs. */ | |
df35c271 | 3924 | && can_assign_to_reg_without_clobbers_p (src)) |
a13d4ebf AM |
3925 | ptr->stores = alloc_INSN_LIST (insn, ptr->stores); |
3926 | else | |
3927 | ptr->invalid = 1; | |
3928 | } | |
3929 | } | |
3930 | else | |
3931 | invalidate_any_buried_refs (PATTERN (insn)); | |
3932 | } | |
3933 | } | |
3934 | } | |
3935 | } | |
3936 | ||
589005ff | 3937 | /* Remove any references that have been either invalidated or are not in the |
a13d4ebf AM |
3938 | expression list for pre gcse. */ |
3939 | ||
3940 | static void | |
1d088dee | 3941 | trim_ld_motion_mems (void) |
a13d4ebf | 3942 | { |
b58b21d5 RS |
3943 | struct ls_expr * * last = & pre_ldst_mems; |
3944 | struct ls_expr * ptr = pre_ldst_mems; | |
a13d4ebf AM |
3945 | |
3946 | while (ptr != NULL) | |
3947 | { | |
b58b21d5 | 3948 | struct expr * expr; |
589005ff | 3949 | |
a13d4ebf | 3950 | /* Delete if entry has been made invalid. */ |
b58b21d5 | 3951 | if (! ptr->invalid) |
a13d4ebf | 3952 | { |
a13d4ebf | 3953 | /* Delete if we cannot find this mem in the expression list. */ |
b58b21d5 | 3954 | unsigned int hash = ptr->hash_index % expr_hash_table.size; |
589005ff | 3955 | |
b58b21d5 RS |
3956 | for (expr = expr_hash_table.table[hash]; |
3957 | expr != NULL; | |
3958 | expr = expr->next_same_hash) | |
3959 | if (expr_equiv_p (expr->expr, ptr->pattern)) | |
3960 | break; | |
a13d4ebf AM |
3961 | } |
3962 | else | |
b58b21d5 RS |
3963 | expr = (struct expr *) 0; |
3964 | ||
3965 | if (expr) | |
a13d4ebf AM |
3966 | { |
3967 | /* Set the expression field if we are keeping it. */ | |
a13d4ebf | 3968 | ptr->expr = expr; |
b58b21d5 | 3969 | last = & ptr->next; |
a13d4ebf AM |
3970 | ptr = ptr->next; |
3971 | } | |
b58b21d5 RS |
3972 | else |
3973 | { | |
3974 | *last = ptr->next; | |
9727e468 | 3975 | htab_remove_elt_with_hash (pre_ldst_table, ptr, ptr->hash_index); |
b58b21d5 RS |
3976 | free_ldst_entry (ptr); |
3977 | ptr = * last; | |
3978 | } | |
a13d4ebf AM |
3979 | } |
3980 | ||
3981 | /* Show the world what we've found. */ | |
10d22567 ZD |
3982 | if (dump_file && pre_ldst_mems != NULL) |
3983 | print_ldst_list (dump_file); | |
a13d4ebf AM |
3984 | } |
3985 | ||
3986 | /* This routine will take an expression which we are replacing with | |
3987 | a reaching register, and update any stores that are needed if | |
3988 | that expression is in the ld_motion list. Stores are updated by | |
a98ebe2e | 3989 | copying their SRC to the reaching register, and then storing |
a13d4ebf AM |
3990 | the reaching register into the store location. These keeps the |
3991 | correct value in the reaching register for the loads. */ | |
3992 | ||
3993 | static void | |
1d088dee | 3994 | update_ld_motion_stores (struct expr * expr) |
a13d4ebf AM |
3995 | { |
3996 | struct ls_expr * mem_ptr; | |
3997 | ||
3998 | if ((mem_ptr = find_rtx_in_ldst (expr->expr))) | |
3999 | { | |
589005ff KH |
4000 | /* We can try to find just the REACHED stores, but is shouldn't |
4001 | matter to set the reaching reg everywhere... some might be | |
a13d4ebf AM |
4002 | dead and should be eliminated later. */ |
4003 | ||
4d3eb89a HPN |
4004 | /* We replace (set mem expr) with (set reg expr) (set mem reg) |
4005 | where reg is the reaching reg used in the load. We checked in | |
4006 | compute_ld_motion_mems that we can replace (set mem expr) with | |
4007 | (set reg expr) in that insn. */ | |
a13d4ebf | 4008 | rtx list = mem_ptr->stores; |
589005ff | 4009 | |
a13d4ebf AM |
4010 | for ( ; list != NULL_RTX; list = XEXP (list, 1)) |
4011 | { | |
4012 | rtx insn = XEXP (list, 0); | |
4013 | rtx pat = PATTERN (insn); | |
4014 | rtx src = SET_SRC (pat); | |
4015 | rtx reg = expr->reaching_reg; | |
038dc49a | 4016 | rtx copy; |
a13d4ebf AM |
4017 | |
4018 | /* If we've already copied it, continue. */ | |
4019 | if (expr->reaching_reg == src) | |
4020 | continue; | |
589005ff | 4021 | |
10d22567 | 4022 | if (dump_file) |
a13d4ebf | 4023 | { |
10d22567 | 4024 | fprintf (dump_file, "PRE: store updated with reaching reg "); |
43c8a043 | 4025 | print_rtl (dump_file, reg); |
10d22567 ZD |
4026 | fprintf (dump_file, ":\n "); |
4027 | print_inline_rtx (dump_file, insn, 8); | |
4028 | fprintf (dump_file, "\n"); | |
a13d4ebf | 4029 | } |
589005ff | 4030 | |
4a81774c | 4031 | copy = gen_move_insn (reg, copy_rtx (SET_SRC (pat))); |
038dc49a | 4032 | emit_insn_before (copy, insn); |
a13d4ebf | 4033 | SET_SRC (pat) = reg; |
6fb5fa3c | 4034 | df_insn_rescan (insn); |
a13d4ebf AM |
4035 | |
4036 | /* un-recognize this pattern since it's probably different now. */ | |
4037 | INSN_CODE (insn) = -1; | |
4038 | gcse_create_count++; | |
4039 | } | |
4040 | } | |
4041 | } | |
4042 | \f | |
df35c271 SB |
4043 | /* Return true if the graph is too expensive to optimize. PASS is the |
4044 | optimization about to be performed. */ | |
47a3dae1 | 4045 | |
df35c271 SB |
4046 | static bool |
4047 | is_too_expensive (const char *pass) | |
4048 | { | |
4049 | /* Trying to perform global optimizations on flow graphs which have | |
4050 | a high connectivity will take a long time and is unlikely to be | |
4051 | particularly useful. | |
aaa4ca30 | 4052 | |
df35c271 SB |
4053 | In normal circumstances a cfg should have about twice as many |
4054 | edges as blocks. But we do not want to punish small functions | |
4055 | which have a couple switch statements. Rather than simply | |
4056 | threshold the number of blocks, uses something with a more | |
4057 | graceful degradation. */ | |
4058 | if (n_edges > 20000 + n_basic_blocks * 4) | |
4059 | { | |
4060 | warning (OPT_Wdisabled_optimization, | |
4061 | "%s: %d basic blocks and %d edges/basic block", | |
4062 | pass, n_basic_blocks, n_edges / n_basic_blocks); | |
a13d4ebf | 4063 | |
df35c271 SB |
4064 | return true; |
4065 | } | |
a13d4ebf | 4066 | |
e45425ec | 4067 | /* If allocating memory for the dataflow bitmaps would take up too much |
df35c271 SB |
4068 | storage it's better just to disable the optimization. */ |
4069 | if ((n_basic_blocks | |
4070 | * SBITMAP_SET_SIZE (max_reg_num ()) | |
4071 | * sizeof (SBITMAP_ELT_TYPE)) > MAX_GCSE_MEMORY) | |
4072 | { | |
4073 | warning (OPT_Wdisabled_optimization, | |
4074 | "%s: %d basic blocks and %d registers", | |
4075 | pass, n_basic_blocks, max_reg_num ()); | |
a13d4ebf | 4076 | |
df35c271 SB |
4077 | return true; |
4078 | } | |
adfcce61 | 4079 | |
df35c271 | 4080 | return false; |
01c43039 | 4081 | } |
df35c271 SB |
4082 | \f |
4083 | /* All the passes implemented in this file. Each pass has its | |
4084 | own gate and execute function, and at the end of the file a | |
4085 | pass definition for passes.c. | |
47a3dae1 | 4086 | |
df35c271 SB |
4087 | We do not construct an accurate cfg in functions which call |
4088 | setjmp, so none of these passes runs if the function calls | |
4089 | setjmp. | |
4090 | FIXME: Should just handle setjmp via REG_SETJMP notes. */ | |
a13d4ebf | 4091 | |
df35c271 SB |
4092 | static bool |
4093 | gate_rtl_pre (void) | |
4094 | { | |
4095 | return optimize > 0 && flag_gcse | |
1f9081d1 XDL |
4096 | && !cfun->calls_setjmp |
4097 | && optimize_function_for_speed_p (cfun) | |
4098 | && dbg_cnt (pre); | |
df35c271 | 4099 | } |
589005ff | 4100 | |
df35c271 SB |
4101 | static unsigned int |
4102 | execute_rtl_pre (void) | |
4103 | { | |
f2b01cfb | 4104 | int changed; |
df35c271 | 4105 | delete_unreachable_blocks (); |
df35c271 | 4106 | df_analyze (); |
f2b01cfb RG |
4107 | changed = one_pre_gcse_pass (); |
4108 | flag_rerun_cse_after_global_opts |= changed; | |
4109 | if (changed) | |
4110 | cleanup_cfg (0); | |
df35c271 SB |
4111 | return 0; |
4112 | } | |
aaa4ca30 | 4113 | |
df35c271 SB |
4114 | static bool |
4115 | gate_rtl_hoist (void) | |
4116 | { | |
4117 | return optimize > 0 && flag_gcse | |
1f9081d1 XDL |
4118 | && !cfun->calls_setjmp |
4119 | /* It does not make sense to run code hoisting unless we are optimizing | |
4120 | for code size -- it rarely makes programs faster, and can make then | |
4121 | bigger if we did PRE (when optimizing for space, we don't run PRE). */ | |
4122 | && optimize_function_for_size_p (cfun) | |
4123 | && dbg_cnt (hoist); | |
df35c271 | 4124 | } |
aaa4ca30 | 4125 | |
df35c271 SB |
4126 | static unsigned int |
4127 | execute_rtl_hoist (void) | |
4128 | { | |
f2b01cfb | 4129 | int changed; |
df35c271 | 4130 | delete_unreachable_blocks (); |
df35c271 | 4131 | df_analyze (); |
f2b01cfb RG |
4132 | changed = one_code_hoisting_pass (); |
4133 | flag_rerun_cse_after_global_opts |= changed; | |
4134 | if (changed) | |
4135 | cleanup_cfg (0); | |
df35c271 SB |
4136 | return 0; |
4137 | } | |
ef330312 | 4138 | |
5f39ad47 | 4139 | struct rtl_opt_pass pass_rtl_pre = |
ef330312 | 4140 | { |
5f39ad47 SB |
4141 | { |
4142 | RTL_PASS, | |
e0a42b0f | 4143 | "rtl pre", /* name */ |
2b4e6bf1 | 4144 | OPTGROUP_NONE, /* optinfo_flags */ |
b8698a0f L |
4145 | gate_rtl_pre, /* gate */ |
4146 | execute_rtl_pre, /* execute */ | |
5f39ad47 SB |
4147 | NULL, /* sub */ |
4148 | NULL, /* next */ | |
4149 | 0, /* static_pass_number */ | |
4150 | TV_PRE, /* tv_id */ | |
4151 | PROP_cfglayout, /* properties_required */ | |
4152 | 0, /* properties_provided */ | |
4153 | 0, /* properties_destroyed */ | |
4154 | 0, /* todo_flags_start */ | |
4155 | TODO_df_finish | TODO_verify_rtl_sharing | | |
5f39ad47 SB |
4156 | TODO_verify_flow | TODO_ggc_collect /* todo_flags_finish */ |
4157 | } | |
4158 | }; | |
ef330312 | 4159 | |
5f39ad47 | 4160 | struct rtl_opt_pass pass_rtl_hoist = |
ef330312 | 4161 | { |
8ddbbcae JH |
4162 | { |
4163 | RTL_PASS, | |
5f39ad47 | 4164 | "hoist", /* name */ |
2b4e6bf1 | 4165 | OPTGROUP_NONE, /* optinfo_flags */ |
b8698a0f L |
4166 | gate_rtl_hoist, /* gate */ |
4167 | execute_rtl_hoist, /* execute */ | |
ef330312 PB |
4168 | NULL, /* sub */ |
4169 | NULL, /* next */ | |
4170 | 0, /* static_pass_number */ | |
5f39ad47 | 4171 | TV_HOIST, /* tv_id */ |
9c9e26f5 | 4172 | PROP_cfglayout, /* properties_required */ |
ef330312 PB |
4173 | 0, /* properties_provided */ |
4174 | 0, /* properties_destroyed */ | |
4175 | 0, /* todo_flags_start */ | |
a36b8a1e | 4176 | TODO_df_finish | TODO_verify_rtl_sharing | |
8ddbbcae JH |
4177 | TODO_verify_flow | TODO_ggc_collect /* todo_flags_finish */ |
4178 | } | |
ef330312 PB |
4179 | }; |
4180 | ||
e2500fed | 4181 | #include "gt-gcse.h" |