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d7429b6a 1/* Data flow analysis for GNU compiler.
c9bacfdb 2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
283334f0 3 1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
d7429b6a 4
1322177d 5This file is part of GCC.
d7429b6a 6
1322177d
LB
7GCC is free software; you can redistribute it and/or modify it under
8the terms of the GNU General Public License as published by the Free
9Software Foundation; either version 2, or (at your option) any later
10version.
d7429b6a 11
1322177d
LB
12GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13WARRANTY; without even the implied warranty of MERCHANTABILITY or
14FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15for more details.
d7429b6a
RK
16
17You should have received a copy of the GNU General Public License
1322177d
LB
18along with GCC; see the file COPYING. If not, write to the Free
19Software Foundation, 59 Temple Place - Suite 330, Boston, MA
2002111-1307, USA. */
d7429b6a 21
e881bb1b
RH
22/* This file contains the data flow analysis pass of the compiler. It
23 computes data flow information which tells combine_instructions
24 which insns to consider combining and controls register allocation.
d7429b6a 25
e881bb1b
RH
26 Additional data flow information that is too bulky to record is
27 generated during the analysis, and is used at that time to create
28 autoincrement and autodecrement addressing.
d7429b6a
RK
29
30 The first step is dividing the function into basic blocks.
31 find_basic_blocks does this. Then life_analysis determines
32 where each register is live and where it is dead.
33
34 ** find_basic_blocks **
35
e881bb1b
RH
36 find_basic_blocks divides the current function's rtl into basic
37 blocks and constructs the CFG. The blocks are recorded in the
38 basic_block_info array; the CFG exists in the edge structures
39 referenced by the blocks.
d7429b6a 40
e881bb1b 41 find_basic_blocks also finds any unreachable loops and deletes them.
d7429b6a
RK
42
43 ** life_analysis **
44
45 life_analysis is called immediately after find_basic_blocks.
46 It uses the basic block information to determine where each
47 hard or pseudo register is live.
48
49 ** live-register info **
50
51 The information about where each register is live is in two parts:
e881bb1b 52 the REG_NOTES of insns, and the vector basic_block->global_live_at_start.
d7429b6a 53
e881bb1b
RH
54 basic_block->global_live_at_start has an element for each basic
55 block, and the element is a bit-vector with a bit for each hard or
56 pseudo register. The bit is 1 if the register is live at the
57 beginning of the basic block.
d7429b6a 58
c9bacfdb 59 Two types of elements can be added to an insn's REG_NOTES.
d7429b6a
RK
60 A REG_DEAD note is added to an insn's REG_NOTES for any register
61 that meets both of two conditions: The value in the register is not
62 needed in subsequent insns and the insn does not replace the value in
63 the register (in the case of multi-word hard registers, the value in
64 each register must be replaced by the insn to avoid a REG_DEAD note).
65
66 In the vast majority of cases, an object in a REG_DEAD note will be
67 used somewhere in the insn. The (rare) exception to this is if an
68 insn uses a multi-word hard register and only some of the registers are
69 needed in subsequent insns. In that case, REG_DEAD notes will be
70 provided for those hard registers that are not subsequently needed.
71 Partial REG_DEAD notes of this type do not occur when an insn sets
72 only some of the hard registers used in such a multi-word operand;
73 omitting REG_DEAD notes for objects stored in an insn is optional and
74 the desire to do so does not justify the complexity of the partial
75 REG_DEAD notes.
76
77 REG_UNUSED notes are added for each register that is set by the insn
78 but is unused subsequently (if every register set by the insn is unused
79 and the insn does not reference memory or have some other side-effect,
80 the insn is deleted instead). If only part of a multi-word hard
81 register is used in a subsequent insn, REG_UNUSED notes are made for
82 the parts that will not be used.
83
84 To determine which registers are live after any insn, one can
85 start from the beginning of the basic block and scan insns, noting
86 which registers are set by each insn and which die there.
87
88 ** Other actions of life_analysis **
89
90 life_analysis sets up the LOG_LINKS fields of insns because the
91 information needed to do so is readily available.
92
93 life_analysis deletes insns whose only effect is to store a value
94 that is never used.
95
96 life_analysis notices cases where a reference to a register as
97 a memory address can be combined with a preceding or following
98 incrementation or decrementation of the register. The separate
99 instruction to increment or decrement is deleted and the address
100 is changed to a POST_INC or similar rtx.
101
102 Each time an incrementing or decrementing address is created,
103 a REG_INC element is added to the insn's REG_NOTES list.
104
105 life_analysis fills in certain vectors containing information about
d4b60170
RK
106 register usage: REG_N_REFS, REG_N_DEATHS, REG_N_SETS, REG_LIVE_LENGTH,
107 REG_N_CALLS_CROSSED and REG_BASIC_BLOCK.
fdb8a883
JW
108
109 life_analysis sets current_function_sp_is_unchanging if the function
110 doesn't modify the stack pointer. */
e881bb1b 111
c9bacfdb 112/* TODO:
e881bb1b
RH
113
114 Split out from life_analysis:
115 - local property discovery (bb->local_live, bb->local_set)
116 - global property computation
117 - log links creation
118 - pre/post modify transformation
119*/
d7429b6a 120\f
d7429b6a 121#include "config.h"
670ee920 122#include "system.h"
4977bab6
ZW
123#include "coretypes.h"
124#include "tm.h"
d3a923ee 125#include "tree.h"
d7429b6a 126#include "rtl.h"
6baf1cc8 127#include "tm_p.h"
efc9bd41 128#include "hard-reg-set.h"
d7429b6a
RK
129#include "basic-block.h"
130#include "insn-config.h"
131#include "regs.h"
d7429b6a
RK
132#include "flags.h"
133#include "output.h"
b384405b 134#include "function.h"
3d195391 135#include "except.h"
2e107e9e 136#include "toplev.h"
79c9824e 137#include "recog.h"
11bdd2ae 138#include "expr.h"
4793dca1 139#include "timevar.h"
d7429b6a
RK
140
141#include "obstack.h"
11ae508b 142#include "splay-tree.h"
c5c76735 143
d3a923ee
RH
144#ifndef HAVE_epilogue
145#define HAVE_epilogue 0
146#endif
d3a923ee
RH
147#ifndef HAVE_prologue
148#define HAVE_prologue 0
149#endif
0a1c58a2
JL
150#ifndef HAVE_sibcall_epilogue
151#define HAVE_sibcall_epilogue 0
152#endif
d3a923ee 153
2a3e384f
RH
154#ifndef EPILOGUE_USES
155#define EPILOGUE_USES(REGNO) 0
156#endif
15b5aef3
RH
157#ifndef EH_USES
158#define EH_USES(REGNO) 0
159#endif
2a3e384f 160
7e6d8ba1
AH
161#ifdef HAVE_conditional_execution
162#ifndef REVERSE_CONDEXEC_PREDICATES_P
163#define REVERSE_CONDEXEC_PREDICATES_P(x, y) ((x) == reverse_condition (y))
164#endif
165#endif
166
56744d1a
JL
167/* Nonzero if the second flow pass has completed. */
168int flow2_completed;
169
d7429b6a
RK
170/* Maximum register number used in this function, plus one. */
171
172int max_regno;
173
b1f21e0a 174/* Indexed by n, giving various register information */
d7429b6a 175
6feacd09 176varray_type reg_n_info;
d7429b6a 177
d7429b6a
RK
178/* Size of a regset for the current function,
179 in (1) bytes and (2) elements. */
180
181int regset_bytes;
182int regset_size;
183
d7429b6a 184/* Regset of regs live when calls to `setjmp'-like functions happen. */
e881bb1b 185/* ??? Does this exist only for the setjmp-clobbered warning message? */
d7429b6a
RK
186
187regset regs_live_at_setjmp;
188
189/* List made of EXPR_LIST rtx's which gives pairs of pseudo registers
190 that have to go in the same hard reg.
191 The first two regs in the list are a pair, and the next two
192 are another pair, etc. */
193rtx regs_may_share;
194
d7429b6a
RK
195/* Set of registers that may be eliminable. These are handled specially
196 in updating regs_ever_live. */
197
198static HARD_REG_SET elim_reg_set;
199
11ae508b
RH
200/* Holds information for tracking conditional register life information. */
201struct reg_cond_life_info
202{
685af3af 203 /* A boolean expression of conditions under which a register is dead. */
11ae508b 204 rtx condition;
685af3af
JW
205 /* Conditions under which a register is dead at the basic block end. */
206 rtx orig_condition;
207
208 /* A boolean expression of conditions under which a register has been
209 stored into. */
210 rtx stores;
11ae508b
RH
211
212 /* ??? Could store mask of bytes that are dead, so that we could finally
213 track lifetimes of multi-word registers accessed via subregs. */
214};
215
62828c00
RH
216/* For use in communicating between propagate_block and its subroutines.
217 Holds all information needed to compute life and def-use information. */
218
219struct propagate_block_info
220{
221 /* The basic block we're considering. */
222 basic_block bb;
223
224 /* Bit N is set if register N is conditionally or unconditionally live. */
225 regset reg_live;
226
9785c68d
RH
227 /* Bit N is set if register N is set this insn. */
228 regset new_set;
8e3f9094 229
62828c00
RH
230 /* Element N is the next insn that uses (hard or pseudo) register N
231 within the current basic block; or zero, if there is no such insn. */
232 rtx *reg_next_use;
233
234 /* Contains a list of all the MEMs we are tracking for dead store
235 elimination. */
236 rtx mem_set_list;
237
7dfc0fbe
BS
238 /* If non-null, record the set of registers set unconditionally in the
239 basic block. */
62828c00
RH
240 regset local_set;
241
7dfc0fbe
BS
242 /* If non-null, record the set of registers set conditionally in the
243 basic block. */
244 regset cond_local_set;
245
11ae508b
RH
246#ifdef HAVE_conditional_execution
247 /* Indexed by register number, holds a reg_cond_life_info for each
248 register that is not unconditionally live or dead. */
249 splay_tree reg_cond_dead;
250
251 /* Bit N is set if register N is in an expression in reg_cond_dead. */
252 regset reg_cond_reg;
253#endif
254
0875baa0
RH
255 /* The length of mem_set_list. */
256 int mem_set_list_len;
257
cc2902df 258 /* Nonzero if the value of CC0 is live. */
62828c00
RH
259 int cc0_live;
260
fbe5a4a6 261 /* Flags controlling the set of information propagate_block collects. */
62828c00 262 int flags;
736b64dd
JH
263 /* Index of instruction being processed. */
264 int insn_num;
62828c00
RH
265};
266
3dec4024
JH
267/* Number of dead insns removed. */
268static int ndead;
269
736b64dd
JH
270/* When PROP_REG_INFO set, array contains pbi->insn_num of instruction
271 where given register died. When the register is marked alive, we use the
272 information to compute amount of instructions life range cross.
273 (remember, we are walking backward). This can be computed as current
274 pbi->insn_num - reg_deaths[regno].
275 At the end of processing each basic block, the remaining live registers
276 are inspected and liferanges are increased same way so liverange of global
277 registers are computed correctly.
278
279 The array is maintained clear for dead registers, so it can be safely reused
280 for next basic block without expensive memset of the whole array after
281 reseting pbi->insn_num to 0. */
282
283static int *reg_deaths;
284
0875baa0
RH
285/* Maximum length of pbi->mem_set_list before we start dropping
286 new elements on the floor. */
287#define MAX_MEM_SET_LIST_LEN 100
288
d7429b6a 289/* Forward declarations */
6cf9ac28
AJ
290static int verify_wide_reg_1 (rtx *, void *);
291static void verify_wide_reg (int, basic_block);
292static void verify_local_live_at_start (regset, basic_block);
293static void notice_stack_pointer_modification_1 (rtx, rtx, void *);
827c06b6 294static void notice_stack_pointer_modification (void);
6cf9ac28
AJ
295static void mark_reg (rtx, void *);
296static void mark_regs_live_at_end (regset);
6cf9ac28
AJ
297static void calculate_global_regs_live (sbitmap, sbitmap, int);
298static void propagate_block_delete_insn (rtx);
299static rtx propagate_block_delete_libcall (rtx, rtx);
300static int insn_dead_p (struct propagate_block_info *, rtx, int, rtx);
301static int libcall_dead_p (struct propagate_block_info *, rtx, rtx);
302static void mark_set_regs (struct propagate_block_info *, rtx, rtx);
303static void mark_set_1 (struct propagate_block_info *, enum rtx_code, rtx,
304 rtx, rtx, int);
305static int find_regno_partial (rtx *, void *);
0626ef8a 306
11ae508b 307#ifdef HAVE_conditional_execution
6cf9ac28
AJ
308static int mark_regno_cond_dead (struct propagate_block_info *, int, rtx);
309static void free_reg_cond_life_info (splay_tree_value);
310static int flush_reg_cond_reg_1 (splay_tree_node, void *);
311static void flush_reg_cond_reg (struct propagate_block_info *, int);
312static rtx elim_reg_cond (rtx, unsigned int);
313static rtx ior_reg_cond (rtx, rtx, int);
314static rtx not_reg_cond (rtx);
315static rtx and_reg_cond (rtx, rtx, int);
11ae508b 316#endif
1d300e19 317#ifdef AUTO_INC_DEC
6cf9ac28
AJ
318static void attempt_auto_inc (struct propagate_block_info *, rtx, rtx, rtx,
319 rtx, rtx);
320static void find_auto_inc (struct propagate_block_info *, rtx, rtx);
321static int try_pre_increment_1 (struct propagate_block_info *, rtx);
322static int try_pre_increment (rtx, rtx, HOST_WIDE_INT);
1d300e19 323#endif
6cf9ac28
AJ
324static void mark_used_reg (struct propagate_block_info *, rtx, rtx, rtx);
325static void mark_used_regs (struct propagate_block_info *, rtx, rtx, rtx);
326void debug_flow_info (void);
327static void add_to_mem_set_list (struct propagate_block_info *, rtx);
328static int invalidate_mems_from_autoinc (rtx *, void *);
329static void invalidate_mems_from_set (struct propagate_block_info *, rtx);
330static void clear_log_links (sbitmap);
095c3bbd 331static int count_or_remove_death_notes_bb (basic_block, int);
d7429b6a 332\f
402209ff
JH
333/* Return the INSN immediately following the NOTE_INSN_BASIC_BLOCK
334 note associated with the BLOCK. */
335
336rtx
6cf9ac28 337first_insn_after_basic_block_note (basic_block block)
402209ff
JH
338{
339 rtx insn;
b313a0fe 340
402209ff 341 /* Get the first instruction in the block. */
a813c111 342 insn = BB_HEAD (block);
dc2ede84 343
402209ff
JH
344 if (insn == NULL_RTX)
345 return NULL_RTX;
4b4bf941 346 if (LABEL_P (insn))
402209ff
JH
347 insn = NEXT_INSN (insn);
348 if (!NOTE_INSN_BASIC_BLOCK_P (insn))
349 abort ();
350
351 return NEXT_INSN (insn);
352}
353\f
827c06b6
SB
354/* Perform data flow analysis for the whole control flow graph.
355 FLAGS is a set of PROP_* flags to be used in accumulating flow info. */
402209ff
JH
356
357void
827c06b6 358life_analysis (FILE *file, int flags)
e881bb1b 359{
cff9f8d5 360#ifdef ELIMINABLE_REGS
c1b50e49 361 int i;
8b60264b 362 static const struct {const int from, to; } eliminables[] = ELIMINABLE_REGS;
402209ff 363#endif
dc2ede84 364
402209ff
JH
365 /* Record which registers will be eliminated. We use this in
366 mark_used_regs. */
e881bb1b 367
402209ff 368 CLEAR_HARD_REG_SET (elim_reg_set);
314883b8 369
402209ff
JH
370#ifdef ELIMINABLE_REGS
371 for (i = 0; i < (int) ARRAY_SIZE (eliminables); i++)
372 SET_HARD_REG_BIT (elim_reg_set, eliminables[i].from);
373#else
374 SET_HARD_REG_BIT (elim_reg_set, FRAME_POINTER_REGNUM);
375#endif
52a11cbf 376
cff9f8d5
AH
377
378#ifdef CANNOT_CHANGE_MODE_CLASS
379 if (flags & PROP_REG_INFO)
10a3fdd9 380 bitmap_initialize (&subregs_of_mode, 1);
cff9f8d5
AH
381#endif
382
402209ff
JH
383 if (! optimize)
384 flags &= ~(PROP_LOG_LINKS | PROP_AUTOINC | PROP_ALLOW_CFG_CHANGES);
52a11cbf 385
402209ff
JH
386 /* The post-reload life analysis have (on a global basis) the same
387 registers live as was computed by reload itself. elimination
388 Otherwise offsets and such may be incorrect.
e881bb1b 389
402209ff
JH
390 Reload will make some registers as live even though they do not
391 appear in the rtl.
e881bb1b 392
402209ff
JH
393 We don't want to create new auto-incs after reload, since they
394 are unlikely to be useful and can cause problems with shared
395 stack slots. */
396 if (reload_completed)
397 flags &= ~(PROP_REG_INFO | PROP_AUTOINC);
e881bb1b 398
402209ff 399 /* We want alias analysis information for local dead store elimination. */
5149f070 400 if (optimize && (flags & PROP_SCAN_DEAD_STORES))
402209ff 401 init_alias_analysis ();
dc2ede84 402
402209ff
JH
403 /* Always remove no-op moves. Do this before other processing so
404 that we don't have to keep re-scanning them. */
827c06b6 405 delete_noop_moves ();
1bc48f82 406
402209ff
JH
407 /* Some targets can emit simpler epilogues if they know that sp was
408 not ever modified during the function. After reload, of course,
409 we've already emitted the epilogue so there's no sense searching. */
410 if (! reload_completed)
827c06b6 411 notice_stack_pointer_modification ();
1bc48f82 412
402209ff
JH
413 /* Allocate and zero out data structures that will record the
414 data from lifetime analysis. */
415 allocate_reg_life_data ();
416 allocate_bb_life_data ();
1bc48f82 417
402209ff
JH
418 /* Find the set of registers live on function exit. */
419 mark_regs_live_at_end (EXIT_BLOCK_PTR->global_live_at_start);
1bc48f82 420
402209ff
JH
421 /* "Update" life info from zero. It'd be nice to begin the
422 relaxation with just the exit and noreturn blocks, but that set
423 is not immediately handy. */
c9bacfdb 424
402209ff 425 if (flags & PROP_REG_INFO)
df2ef49b
AM
426 {
427 memset (regs_ever_live, 0, sizeof (regs_ever_live));
428 memset (regs_asm_clobbered, 0, sizeof (regs_asm_clobbered));
429 }
402209ff 430 update_life_info (NULL, UPDATE_LIFE_GLOBAL, flags);
736b64dd
JH
431 if (reg_deaths)
432 {
433 free (reg_deaths);
434 reg_deaths = NULL;
435 }
1bc48f82 436
402209ff 437 /* Clean up. */
5149f070 438 if (optimize && (flags & PROP_SCAN_DEAD_STORES))
402209ff 439 end_alias_analysis ();
1bc48f82 440
402209ff
JH
441 if (file)
442 dump_flow_info (file);
0005550b 443
1f52178b 444 /* Removing dead insns should have made jumptables really dead. */
402209ff
JH
445 delete_dead_jumptables ();
446}
0005550b 447
402209ff 448/* A subroutine of verify_wide_reg, called through for_each_rtx.
08ef5437
RH
449 Search for REGNO. If found, return 2 if it is not wider than
450 word_mode. */
a686dbf8 451
402209ff 452static int
6cf9ac28 453verify_wide_reg_1 (rtx *px, void *pregno)
402209ff
JH
454{
455 rtx x = *px;
456 unsigned int regno = *(int *) pregno;
134d3a2e 457
f8cfc6aa 458 if (REG_P (x) && REGNO (x) == regno)
134d3a2e 459 {
402209ff 460 if (GET_MODE_BITSIZE (GET_MODE (x)) <= BITS_PER_WORD)
08ef5437 461 return 2;
402209ff 462 return 1;
134d3a2e 463 }
402209ff 464 return 0;
a686dbf8
JH
465}
466
402209ff 467/* A subroutine of verify_local_live_at_start. Search through insns
08ef5437 468 of BB looking for register REGNO. */
8329b5ec 469
be1bb652 470static void
6cf9ac28 471verify_wide_reg (int regno, basic_block bb)
e881bb1b 472{
a813c111 473 rtx head = BB_HEAD (bb), end = BB_END (bb);
08ef5437 474
402209ff 475 while (1)
e881bb1b 476 {
08ef5437
RH
477 if (INSN_P (head))
478 {
479 int r = for_each_rtx (&PATTERN (head), verify_wide_reg_1, &regno);
480 if (r == 1)
481 return;
482 if (r == 2)
483 break;
484 }
402209ff
JH
485 if (head == end)
486 break;
487 head = NEXT_INSN (head);
488 }
d7429b6a 489
c263766c 490 if (dump_file)
08ef5437 491 {
c263766c
RH
492 fprintf (dump_file, "Register %d died unexpectedly.\n", regno);
493 dump_bb (bb, dump_file, 0);
08ef5437
RH
494 }
495 abort ();
402209ff 496}
314883b8 497
402209ff
JH
498/* A subroutine of update_life_info. Verify that there are no untoward
499 changes in live_at_start during a local update. */
d06c6389 500
402209ff 501static void
6cf9ac28 502verify_local_live_at_start (regset new_live_at_start, basic_block bb)
402209ff
JH
503{
504 if (reload_completed)
505 {
506 /* After reload, there are no pseudos, nor subregs of multi-word
507 registers. The regsets should exactly match. */
508 if (! REG_SET_EQUAL_P (new_live_at_start, bb->global_live_at_start))
509 {
c263766c 510 if (dump_file)
e881bb1b 511 {
c263766c 512 fprintf (dump_file,
08ef5437 513 "live_at_start mismatch in bb %d, aborting\nNew:\n",
0b17ab2f 514 bb->index);
c263766c
RH
515 debug_bitmap_file (dump_file, new_live_at_start);
516 fputs ("Old:\n", dump_file);
517 dump_bb (bb, dump_file, 0);
e881bb1b 518 }
08ef5437 519 abort ();
e881bb1b 520 }
402209ff
JH
521 }
522 else
523 {
524 int i;
d7429b6a 525
402209ff
JH
526 /* Find the set of changed registers. */
527 XOR_REG_SET (new_live_at_start, bb->global_live_at_start);
421382ac 528
402209ff
JH
529 EXECUTE_IF_SET_IN_REG_SET (new_live_at_start, 0, i,
530 {
dd3f0101 531 /* No registers should die. */
402209ff
JH
532 if (REGNO_REG_SET_P (bb->global_live_at_start, i))
533 {
c263766c 534 if (dump_file)
08ef5437 535 {
c263766c 536 fprintf (dump_file,
08ef5437 537 "Register %d died unexpectedly.\n", i);
c263766c 538 dump_bb (bb, dump_file, 0);
08ef5437
RH
539 }
540 abort ();
402209ff 541 }
c9bacfdb 542
dd3f0101 543 /* Verify that the now-live register is wider than word_mode. */
08ef5437 544 verify_wide_reg (i, bb);
402209ff 545 });
e881bb1b 546 }
402209ff 547}
d7429b6a 548
402209ff
JH
549/* Updates life information starting with the basic blocks set in BLOCKS.
550 If BLOCKS is null, consider it to be the universal set.
af14ce9c 551
e0bb17a8 552 If EXTENT is UPDATE_LIFE_LOCAL, such as after splitting or peepholing,
402209ff
JH
553 we are only expecting local modifications to basic blocks. If we find
554 extra registers live at the beginning of a block, then we either killed
555 useful data, or we have a broken split that wants data not provided.
556 If we find registers removed from live_at_start, that means we have
557 a broken peephole that is killing a register it shouldn't.
af14ce9c 558
402209ff
JH
559 ??? This is not true in one situation -- when a pre-reload splitter
560 generates subregs of a multi-word pseudo, current life analysis will
561 lose the kill. So we _can_ have a pseudo go live. How irritating.
5ece9746 562
24908375
R
563 It is also not true when a peephole decides that it doesn't need one
564 or more of the inputs.
565
402209ff
JH
566 Including PROP_REG_INFO does not properly refresh regs_ever_live
567 unless the caller resets it to zero. */
19d3c25c 568
3dec4024 569int
6cf9ac28 570update_life_info (sbitmap blocks, enum update_life_extent extent, int prop_flags)
19d3c25c 571{
402209ff
JH
572 regset tmp;
573 regset_head tmp_head;
006844a3 574 int i;
566576e7 575 int stabilized_prop_flags = prop_flags;
e0082a72 576 basic_block bb;
006844a3 577
402209ff 578 tmp = INITIALIZE_REG_SET (tmp_head);
3dec4024 579 ndead = 0;
2cade2ad 580
298c28a8
JH
581 if ((prop_flags & PROP_REG_INFO) && !reg_deaths)
582 reg_deaths = xcalloc (sizeof (*reg_deaths), max_regno);
583
b932f770
JH
584 timevar_push ((extent == UPDATE_LIFE_LOCAL || blocks)
585 ? TV_LIFE_UPDATE : TV_LIFE);
586
402209ff
JH
587 /* Changes to the CFG are only allowed when
588 doing a global update for the entire CFG. */
589 if ((prop_flags & PROP_ALLOW_CFG_CHANGES)
590 && (extent == UPDATE_LIFE_LOCAL || blocks))
591 abort ();
006844a3 592
402209ff
JH
593 /* For a global update, we go through the relaxation process again. */
594 if (extent != UPDATE_LIFE_LOCAL)
595 {
596 for ( ; ; )
597 {
598 int changed = 0;
19d3c25c 599
402209ff
JH
600 calculate_global_regs_live (blocks, blocks,
601 prop_flags & (PROP_SCAN_DEAD_CODE
5149f070 602 | PROP_SCAN_DEAD_STORES
402209ff 603 | PROP_ALLOW_CFG_CHANGES));
5ece9746 604
402209ff
JH
605 if ((prop_flags & (PROP_KILL_DEAD_CODE | PROP_ALLOW_CFG_CHANGES))
606 != (PROP_KILL_DEAD_CODE | PROP_ALLOW_CFG_CHANGES))
607 break;
e881bb1b 608
402209ff
JH
609 /* Removing dead code may allow the CFG to be simplified which
610 in turn may allow for further dead code detection / removal. */
e0082a72 611 FOR_EACH_BB_REVERSE (bb)
402209ff 612 {
402209ff
JH
613 COPY_REG_SET (tmp, bb->global_live_at_end);
614 changed |= propagate_block (bb, tmp, NULL, NULL,
615 prop_flags & (PROP_SCAN_DEAD_CODE
5149f070 616 | PROP_SCAN_DEAD_STORES
402209ff
JH
617 | PROP_KILL_DEAD_CODE));
618 }
47095bfc 619
566576e7
HPN
620 /* Don't pass PROP_SCAN_DEAD_CODE or PROP_KILL_DEAD_CODE to
621 subsequent propagate_block calls, since removing or acting as
622 removing dead code can affect global register liveness, which
623 is supposed to be finalized for this call after this loop. */
624 stabilized_prop_flags
5149f070
JH
625 &= ~(PROP_SCAN_DEAD_CODE | PROP_SCAN_DEAD_STORES
626 | PROP_KILL_DEAD_CODE);
566576e7
HPN
627
628 if (! changed)
402209ff 629 break;
566576e7
HPN
630
631 /* We repeat regardless of what cleanup_cfg says. If there were
632 instructions deleted above, that might have been only a
633 partial improvement (see MAX_MEM_SET_LIST_LEN usage).
634 Further improvement may be possible. */
635 cleanup_cfg (CLEANUP_EXPENSIVE);
cdd1f01b 636
6cf9ac28 637 /* Zap the life information from the last round. If we don't
cdd1f01b 638 do this, we can wind up with registers that no longer appear
6de9cd9a 639 in the code being marked live at entry. */
cdd1f01b
RH
640 FOR_EACH_BB (bb)
641 {
642 CLEAR_REG_SET (bb->global_live_at_start);
643 CLEAR_REG_SET (bb->global_live_at_end);
644 }
e881bb1b 645 }
47095bfc 646
402209ff
JH
647 /* If asked, remove notes from the blocks we'll update. */
648 if (extent == UPDATE_LIFE_GLOBAL_RM_NOTES)
649 count_or_remove_death_notes (blocks, 1);
650 }
651
38c1593d
JH
652 /* Clear log links in case we are asked to (re)compute them. */
653 if (prop_flags & PROP_LOG_LINKS)
654 clear_log_links (blocks);
655
402209ff
JH
656 if (blocks)
657 {
658 EXECUTE_IF_SET_IN_SBITMAP (blocks, 0, i,
659 {
e0082a72 660 bb = BASIC_BLOCK (i);
402209ff
JH
661
662 COPY_REG_SET (tmp, bb->global_live_at_end);
566576e7 663 propagate_block (bb, tmp, NULL, NULL, stabilized_prop_flags);
402209ff
JH
664
665 if (extent == UPDATE_LIFE_LOCAL)
666 verify_local_live_at_start (tmp, bb);
667 });
5ece9746 668 }
e881bb1b
RH
669 else
670 {
e0082a72 671 FOR_EACH_BB_REVERSE (bb)
355e4ec4 672 {
402209ff 673 COPY_REG_SET (tmp, bb->global_live_at_end);
566576e7
HPN
674
675 propagate_block (bb, tmp, NULL, NULL, stabilized_prop_flags);
421382ac 676
402209ff
JH
677 if (extent == UPDATE_LIFE_LOCAL)
678 verify_local_live_at_start (tmp, bb);
e881bb1b 679 }
e881bb1b
RH
680 }
681
402209ff 682 FREE_REG_SET (tmp);
eeea333e 683
402209ff
JH
684 if (prop_flags & PROP_REG_INFO)
685 {
686 /* The only pseudos that are live at the beginning of the function
687 are those that were not set anywhere in the function. local-alloc
688 doesn't know how to handle these correctly, so mark them as not
689 local to any one basic block. */
690 EXECUTE_IF_SET_IN_REG_SET (ENTRY_BLOCK_PTR->global_live_at_end,
691 FIRST_PSEUDO_REGISTER, i,
692 { REG_BASIC_BLOCK (i) = REG_BLOCK_GLOBAL; });
e881bb1b 693
402209ff
JH
694 /* We have a problem with any pseudoreg that lives across the setjmp.
695 ANSI says that if a user variable does not change in value between
696 the setjmp and the longjmp, then the longjmp preserves it. This
697 includes longjmp from a place where the pseudo appears dead.
698 (In principle, the value still exists if it is in scope.)
699 If the pseudo goes in a hard reg, some other value may occupy
700 that hard reg where this pseudo is dead, thus clobbering the pseudo.
701 Conclusion: such a pseudo must not go in a hard reg. */
702 EXECUTE_IF_SET_IN_REG_SET (regs_live_at_setjmp,
703 FIRST_PSEUDO_REGISTER, i,
704 {
705 if (regno_reg_rtx[i] != 0)
706 {
707 REG_LIVE_LENGTH (i) = -1;
708 REG_BASIC_BLOCK (i) = REG_BLOCK_UNKNOWN;
709 }
710 });
711 }
736b64dd
JH
712 if (reg_deaths)
713 {
714 free (reg_deaths);
715 reg_deaths = NULL;
716 }
b932f770
JH
717 timevar_pop ((extent == UPDATE_LIFE_LOCAL || blocks)
718 ? TV_LIFE_UPDATE : TV_LIFE);
c263766c
RH
719 if (ndead && dump_file)
720 fprintf (dump_file, "deleted %i dead insns\n", ndead);
3dec4024 721 return ndead;
421382ac 722}
b62c8881 723
38c1593d
JH
724/* Update life information in all blocks where BB_DIRTY is set. */
725
3dec4024 726int
6cf9ac28 727update_life_info_in_dirty_blocks (enum update_life_extent extent, int prop_flags)
38c1593d 728{
d55bc081 729 sbitmap update_life_blocks = sbitmap_alloc (last_basic_block);
38c1593d 730 int n = 0;
e0082a72 731 basic_block bb;
0a2ed1f1 732 int retval = 0;
38c1593d
JH
733
734 sbitmap_zero (update_life_blocks);
e0082a72 735 FOR_EACH_BB (bb)
e0e577a2
RH
736 {
737 if (extent == UPDATE_LIFE_LOCAL)
738 {
739 if (bb->flags & BB_DIRTY)
740 {
741 SET_BIT (update_life_blocks, bb->index);
742 n++;
743 }
744 }
745 else
746 {
747 /* ??? Bootstrap with -march=pentium4 fails to terminate
748 with only a partial life update. */
749 SET_BIT (update_life_blocks, bb->index);
750 if (bb->flags & BB_DIRTY)
751 n++;
752 }
753 }
38c1593d
JH
754
755 if (n)
0a2ed1f1 756 retval = update_life_info (update_life_blocks, extent, prop_flags);
38c1593d
JH
757
758 sbitmap_free (update_life_blocks);
0a2ed1f1 759 return retval;
38c1593d
JH
760}
761
bb8a619e 762/* Free the variables allocated by find_basic_blocks. */
421382ac 763
2307e372 764void
bb8a619e 765free_basic_block_vars (void)
421382ac 766{
bb8a619e 767 if (basic_block_info)
402209ff 768 {
bb8a619e 769 clear_edges ();
6de9cd9a 770 basic_block_info = NULL;
e881bb1b 771 }
bb8a619e
SB
772 n_basic_blocks = 0;
773 last_basic_block = 0;
774
775 ENTRY_BLOCK_PTR->aux = NULL;
776 ENTRY_BLOCK_PTR->global_live_at_end = NULL;
777 EXIT_BLOCK_PTR->aux = NULL;
778 EXIT_BLOCK_PTR->global_live_at_start = NULL;
421382ac
BS
779}
780
402209ff 781/* Delete any insns that copy a register to itself. */
421382ac 782
3dec4024 783int
827c06b6 784delete_noop_moves (void)
421382ac 785{
402209ff
JH
786 rtx insn, next;
787 basic_block bb;
3dec4024 788 int nnoops = 0;
421382ac 789
e0082a72 790 FOR_EACH_BB (bb)
421382ac 791 {
a813c111 792 for (insn = BB_HEAD (bb); insn != NEXT_INSN (BB_END (bb)); insn = next)
421382ac 793 {
402209ff
JH
794 next = NEXT_INSN (insn);
795 if (INSN_P (insn) && noop_move_p (insn))
796 {
eb9d8e4d
JW
797 rtx note;
798
799 /* If we're about to remove the first insn of a libcall
800 then move the libcall note to the next real insn and
801 update the retval note. */
802 if ((note = find_reg_note (insn, REG_LIBCALL, NULL_RTX))
803 && XEXP (note, 0) != insn)
804 {
805 rtx new_libcall_insn = next_real_insn (insn);
806 rtx retval_note = find_reg_note (XEXP (note, 0),
807 REG_RETVAL, NULL_RTX);
808 REG_NOTES (new_libcall_insn)
809 = gen_rtx_INSN_LIST (REG_LIBCALL, XEXP (note, 0),
810 REG_NOTES (new_libcall_insn));
811 XEXP (retval_note, 0) = new_libcall_insn;
812 }
813
3dec4024
JH
814 delete_insn_and_edges (insn);
815 nnoops++;
402209ff 816 }
421382ac
BS
817 }
818 }
c263766c
RH
819 if (nnoops && dump_file)
820 fprintf (dump_file, "deleted %i noop moves", nnoops);
3dec4024 821 return nnoops;
421382ac
BS
822}
823
402209ff 824/* Delete any jump tables never referenced. We can't delete them at the
eaec9b3d 825 time of removing tablejump insn as they are referenced by the preceding
402209ff
JH
826 insns computing the destination, so we delay deleting and garbagecollect
827 them once life information is computed. */
0010687d 828void
6cf9ac28 829delete_dead_jumptables (void)
402209ff
JH
830{
831 rtx insn, next;
832 for (insn = get_insns (); insn; insn = next)
421382ac 833 {
402209ff 834 next = NEXT_INSN (insn);
4b4bf941 835 if (LABEL_P (insn)
967bd823 836 && LABEL_NUSES (insn) == LABEL_PRESERVE_P (insn)
4b4bf941 837 && JUMP_P (next)
402209ff
JH
838 && (GET_CODE (PATTERN (next)) == ADDR_VEC
839 || GET_CODE (PATTERN (next)) == ADDR_DIFF_VEC))
e881bb1b 840 {
c263766c
RH
841 if (dump_file)
842 fprintf (dump_file, "Dead jumptable %i removed\n", INSN_UID (insn));
53c17031
JH
843 delete_insn (NEXT_INSN (insn));
844 delete_insn (insn);
402209ff 845 next = NEXT_INSN (next);
e881bb1b 846 }
dc2ede84 847 }
e881bb1b
RH
848}
849
402209ff
JH
850/* Determine if the stack pointer is constant over the life of the function.
851 Only useful before prologues have been emitted. */
e881bb1b
RH
852
853static void
6cf9ac28
AJ
854notice_stack_pointer_modification_1 (rtx x, rtx pat ATTRIBUTE_UNUSED,
855 void *data ATTRIBUTE_UNUSED)
e881bb1b 856{
402209ff
JH
857 if (x == stack_pointer_rtx
858 /* The stack pointer is only modified indirectly as the result
859 of a push until later in flow. See the comments in rtl.texi
860 regarding Embedded Side-Effects on Addresses. */
3c0cb5de 861 || (MEM_P (x)
ec8e098d 862 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == RTX_AUTOINC
402209ff
JH
863 && XEXP (XEXP (x, 0), 0) == stack_pointer_rtx))
864 current_function_sp_is_unchanging = 0;
e881bb1b 865}
e6cfb550 866
336a6399 867static void
827c06b6 868notice_stack_pointer_modification (void)
e881bb1b 869{
827c06b6 870 basic_block bb;
402209ff 871 rtx insn;
e881bb1b 872
402209ff
JH
873 /* Assume that the stack pointer is unchanging if alloca hasn't
874 been used. */
875 current_function_sp_is_unchanging = !current_function_calls_alloca;
876 if (! current_function_sp_is_unchanging)
877 return;
e881bb1b 878
827c06b6
SB
879 FOR_EACH_BB (bb)
880 FOR_BB_INSNS (bb, insn)
881 {
882 if (INSN_P (insn))
883 {
884 /* Check if insn modifies the stack pointer. */
885 note_stores (PATTERN (insn),
886 notice_stack_pointer_modification_1,
887 NULL);
888 if (! current_function_sp_is_unchanging)
889 return;
890 }
891 }
e881bb1b 892}
0ecf09f9 893
402209ff
JH
894/* Mark a register in SET. Hard registers in large modes get all
895 of their component registers set as well. */
0ecf09f9 896
402209ff 897static void
6cf9ac28 898mark_reg (rtx reg, void *xset)
0ecf09f9 899{
402209ff
JH
900 regset set = (regset) xset;
901 int regno = REGNO (reg);
0ecf09f9 902
402209ff
JH
903 if (GET_MODE (reg) == BLKmode)
904 abort ();
0ecf09f9 905
402209ff
JH
906 SET_REGNO_REG_SET (set, regno);
907 if (regno < FIRST_PSEUDO_REGISTER)
0ecf09f9 908 {
66fd46b6 909 int n = hard_regno_nregs[regno][GET_MODE (reg)];
402209ff
JH
910 while (--n > 0)
911 SET_REGNO_REG_SET (set, regno + n);
0ecf09f9 912 }
0ecf09f9 913}
c586192c 914
402209ff
JH
915/* Mark those regs which are needed at the end of the function as live
916 at the end of the last basic block. */
c586192c 917
402209ff 918static void
6cf9ac28 919mark_regs_live_at_end (regset set)
402209ff
JH
920{
921 unsigned int i;
c586192c 922
402209ff
JH
923 /* If exiting needs the right stack value, consider the stack pointer
924 live at the end of the function. */
fe3ad572 925 if ((HAVE_epilogue && epilogue_completed)
402209ff
JH
926 || ! EXIT_IGNORE_STACK
927 || (! FRAME_POINTER_REQUIRED
928 && ! current_function_calls_alloca
929 && flag_omit_frame_pointer)
930 || current_function_sp_is_unchanging)
c586192c 931 {
402209ff 932 SET_REGNO_REG_SET (set, STACK_POINTER_REGNUM);
c586192c
MH
933 }
934
402209ff
JH
935 /* Mark the frame pointer if needed at the end of the function. If
936 we end up eliminating it, it will be removed from the live list
937 of each basic block by reload. */
c586192c 938
402209ff 939 if (! reload_completed || frame_pointer_needed)
a686dbf8 940 {
402209ff
JH
941 SET_REGNO_REG_SET (set, FRAME_POINTER_REGNUM);
942#if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
943 /* If they are different, also mark the hard frame pointer as live. */
944 if (! LOCAL_REGNO (HARD_FRAME_POINTER_REGNUM))
dd3f0101 945 SET_REGNO_REG_SET (set, HARD_FRAME_POINTER_REGNUM);
402209ff 946#endif
a686dbf8 947 }
c586192c 948
402209ff
JH
949#ifndef PIC_OFFSET_TABLE_REG_CALL_CLOBBERED
950 /* Many architectures have a GP register even without flag_pic.
951 Assume the pic register is not in use, or will be handled by
952 other means, if it is not fixed. */
fc555370 953 if ((unsigned) PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM
402209ff
JH
954 && fixed_regs[PIC_OFFSET_TABLE_REGNUM])
955 SET_REGNO_REG_SET (set, PIC_OFFSET_TABLE_REGNUM);
956#endif
c586192c 957
402209ff
JH
958 /* Mark all global registers, and all registers used by the epilogue
959 as being live at the end of the function since they may be
960 referenced by our caller. */
961 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
962 if (global_regs[i] || EPILOGUE_USES (i))
963 SET_REGNO_REG_SET (set, i);
c586192c 964
fe3ad572 965 if (HAVE_epilogue && epilogue_completed)
ca9fef16 966 {
402209ff
JH
967 /* Mark all call-saved registers that we actually used. */
968 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
969 if (regs_ever_live[i] && ! LOCAL_REGNO (i)
970 && ! TEST_HARD_REG_BIT (regs_invalidated_by_call, i))
971 SET_REGNO_REG_SET (set, i);
ca9fef16 972 }
b9b2c339 973
402209ff
JH
974#ifdef EH_RETURN_DATA_REGNO
975 /* Mark the registers that will contain data for the handler. */
976 if (reload_completed && current_function_calls_eh_return)
977 for (i = 0; ; ++i)
978 {
979 unsigned regno = EH_RETURN_DATA_REGNO(i);
980 if (regno == INVALID_REGNUM)
981 break;
982 SET_REGNO_REG_SET (set, regno);
983 }
e9644cfe 984#endif
402209ff 985#ifdef EH_RETURN_STACKADJ_RTX
fe3ad572 986 if ((! HAVE_epilogue || ! epilogue_completed)
402209ff 987 && current_function_calls_eh_return)
7a442791 988 {
402209ff
JH
989 rtx tmp = EH_RETURN_STACKADJ_RTX;
990 if (tmp && REG_P (tmp))
991 mark_reg (tmp, set);
7a442791 992 }
402209ff
JH
993#endif
994#ifdef EH_RETURN_HANDLER_RTX
fe3ad572 995 if ((! HAVE_epilogue || ! epilogue_completed)
402209ff 996 && current_function_calls_eh_return)
2b2c8b3e 997 {
402209ff
JH
998 rtx tmp = EH_RETURN_HANDLER_RTX;
999 if (tmp && REG_P (tmp))
1000 mark_reg (tmp, set);
2b2c8b3e 1001 }
402209ff 1002#endif
7a442791 1003
402209ff
JH
1004 /* Mark function return value. */
1005 diddle_return_value (mark_reg, set);
7a442791
JH
1006}
1007
402209ff
JH
1008/* Propagate global life info around the graph of basic blocks. Begin
1009 considering blocks with their corresponding bit set in BLOCKS_IN.
1010 If BLOCKS_IN is null, consider it the universal set.
b9b2c339 1011
402209ff 1012 BLOCKS_OUT is set for every block that was changed. */
b9b2c339 1013
402209ff 1014static void
6cf9ac28 1015calculate_global_regs_live (sbitmap blocks_in, sbitmap blocks_out, int flags)
402209ff 1016{
e0082a72 1017 basic_block *queue, *qhead, *qtail, *qend, bb;
f3ea5f6a
RH
1018 regset tmp, new_live_at_end, invalidated_by_call;
1019 regset_head tmp_head, invalidated_by_call_head;
402209ff
JH
1020 regset_head new_live_at_end_head;
1021 int i;
b9b2c339 1022
1540f9eb 1023 /* Some passes used to forget clear aux field of basic block causing
8d9afc4e 1024 sick behavior here. */
1540f9eb 1025#ifdef ENABLE_CHECKING
e0082a72
ZD
1026 FOR_BB_BETWEEN (bb, ENTRY_BLOCK_PTR, NULL, next_bb)
1027 if (bb->aux)
1540f9eb
JH
1028 abort ();
1029#endif
1030
402209ff
JH
1031 tmp = INITIALIZE_REG_SET (tmp_head);
1032 new_live_at_end = INITIALIZE_REG_SET (new_live_at_end_head);
f3ea5f6a 1033 invalidated_by_call = INITIALIZE_REG_SET (invalidated_by_call_head);
b9b2c339 1034
d6a7951f 1035 /* Inconveniently, this is only readily available in hard reg set form. */
402209ff 1036 for (i = 0; i < FIRST_PSEUDO_REGISTER; ++i)
f3ea5f6a
RH
1037 if (TEST_HARD_REG_BIT (regs_invalidated_by_call, i))
1038 SET_REGNO_REG_SET (invalidated_by_call, i);
2b2c8b3e 1039
402209ff
JH
1040 /* Create a worklist. Allocate an extra slot for ENTRY_BLOCK, and one
1041 because the `head == tail' style test for an empty queue doesn't
1042 work with a full queue. */
703ad42b 1043 queue = xmalloc ((n_basic_blocks + 2) * sizeof (*queue));
402209ff 1044 qtail = queue;
0b17ab2f 1045 qhead = qend = queue + n_basic_blocks + 2;
2b2c8b3e 1046
402209ff
JH
1047 /* Queue the blocks set in the initial mask. Do this in reverse block
1048 number order so that we are more likely for the first round to do
1049 useful work. We use AUX non-null to flag that the block is queued. */
1050 if (blocks_in)
c319629b 1051 {
e0082a72
ZD
1052 FOR_EACH_BB (bb)
1053 if (TEST_BIT (blocks_in, bb->index))
1054 {
1055 *--qhead = bb;
1056 bb->aux = bb;
1057 }
2b2c8b3e 1058 }
402209ff 1059 else
e881bb1b 1060 {
bf77398c 1061 FOR_EACH_BB (bb)
402209ff 1062 {
402209ff
JH
1063 *--qhead = bb;
1064 bb->aux = bb;
1065 }
e881bb1b 1066 }
e881bb1b 1067
70e0ccd0
AO
1068 /* We clean aux when we remove the initially-enqueued bbs, but we
1069 don't enqueue ENTRY and EXIT initially, so clean them upfront and
1070 unconditionally. */
1071 ENTRY_BLOCK_PTR->aux = EXIT_BLOCK_PTR->aux = NULL;
1072
402209ff
JH
1073 if (blocks_out)
1074 sbitmap_zero (blocks_out);
e881bb1b 1075
402209ff
JH
1076 /* We work through the queue until there are no more blocks. What
1077 is live at the end of this block is precisely the union of what
1078 is live at the beginning of all its successors. So, we set its
1079 GLOBAL_LIVE_AT_END field based on the GLOBAL_LIVE_AT_START field
1080 for its successors. Then, we compute GLOBAL_LIVE_AT_START for
1081 this block by walking through the instructions in this block in
1082 reverse order and updating as we go. If that changed
1083 GLOBAL_LIVE_AT_START, we add the predecessors of the block to the
1084 queue; they will now need to recalculate GLOBAL_LIVE_AT_END.
e881bb1b 1085
402209ff
JH
1086 We are guaranteed to terminate, because GLOBAL_LIVE_AT_START
1087 never shrinks. If a register appears in GLOBAL_LIVE_AT_START, it
1088 must either be live at the end of the block, or used within the
1089 block. In the latter case, it will certainly never disappear
1090 from GLOBAL_LIVE_AT_START. In the former case, the register
1091 could go away only if it disappeared from GLOBAL_LIVE_AT_START
1092 for one of the successor blocks. By induction, that cannot
1093 occur. */
1094 while (qhead != qtail)
e881bb1b 1095 {
402209ff
JH
1096 int rescan, changed;
1097 basic_block bb;
e881bb1b 1098 edge e;
e881bb1b 1099
402209ff
JH
1100 bb = *qhead++;
1101 if (qhead == qend)
1102 qhead = queue;
1103 bb->aux = NULL;
1104
1105 /* Begin by propagating live_at_start from the successor blocks. */
1106 CLEAR_REG_SET (new_live_at_end);
e881bb1b 1107
15b5aef3
RH
1108 if (bb->succ)
1109 for (e = bb->succ; e; e = e->succ_next)
1110 {
1111 basic_block sb = e->dest;
1112
1113 /* Call-clobbered registers die across exception and
1114 call edges. */
1115 /* ??? Abnormal call edges ignored for the moment, as this gets
1116 confused by sibling call edges, which crashes reg-stack. */
1117 if (e->flags & EDGE_EH)
1118 {
1119 bitmap_operation (tmp, sb->global_live_at_start,
f3ea5f6a 1120 invalidated_by_call, BITMAP_AND_COMPL);
15b5aef3
RH
1121 IOR_REG_SET (new_live_at_end, tmp);
1122 }
1123 else
1124 IOR_REG_SET (new_live_at_end, sb->global_live_at_start);
1125
1126 /* If a target saves one register in another (instead of on
1127 the stack) the save register will need to be live for EH. */
1128 if (e->flags & EDGE_EH)
1129 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1130 if (EH_USES (i))
1131 SET_REGNO_REG_SET (new_live_at_end, i);
1132 }
1133 else
1134 {
1135 /* This might be a noreturn function that throws. And
1136 even if it isn't, getting the unwind info right helps
1137 debugging. */
1138 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1139 if (EH_USES (i))
1140 SET_REGNO_REG_SET (new_live_at_end, i);
402209ff 1141 }
e881bb1b 1142
402209ff
JH
1143 /* The all-important stack pointer must always be live. */
1144 SET_REGNO_REG_SET (new_live_at_end, STACK_POINTER_REGNUM);
1e7d57a3 1145
402209ff
JH
1146 /* Before reload, there are a few registers that must be forced
1147 live everywhere -- which might not already be the case for
1148 blocks within infinite loops. */
1149 if (! reload_completed)
1150 {
1151 /* Any reference to any pseudo before reload is a potential
1152 reference of the frame pointer. */
1153 SET_REGNO_REG_SET (new_live_at_end, FRAME_POINTER_REGNUM);
c9bacfdb 1154
402209ff
JH
1155#if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
1156 /* Pseudos with argument area equivalences may require
1157 reloading via the argument pointer. */
1158 if (fixed_regs[ARG_POINTER_REGNUM])
1159 SET_REGNO_REG_SET (new_live_at_end, ARG_POINTER_REGNUM);
1160#endif
e881bb1b 1161
402209ff
JH
1162 /* Any constant, or pseudo with constant equivalences, may
1163 require reloading from memory using the pic register. */
fc555370 1164 if ((unsigned) PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM
402209ff
JH
1165 && fixed_regs[PIC_OFFSET_TABLE_REGNUM])
1166 SET_REGNO_REG_SET (new_live_at_end, PIC_OFFSET_TABLE_REGNUM);
e881bb1b 1167 }
e881bb1b 1168
402209ff
JH
1169 if (bb == ENTRY_BLOCK_PTR)
1170 {
1171 COPY_REG_SET (bb->global_live_at_end, new_live_at_end);
1172 continue;
1173 }
e881bb1b 1174
402209ff
JH
1175 /* On our first pass through this block, we'll go ahead and continue.
1176 Recognize first pass by local_set NULL. On subsequent passes, we
1177 get to skip out early if live_at_end wouldn't have changed. */
e881bb1b 1178
402209ff
JH
1179 if (bb->local_set == NULL)
1180 {
1181 bb->local_set = OBSTACK_ALLOC_REG_SET (&flow_obstack);
1182 bb->cond_local_set = OBSTACK_ALLOC_REG_SET (&flow_obstack);
1183 rescan = 1;
1184 }
1185 else
1186 {
1187 /* If any bits were removed from live_at_end, we'll have to
1188 rescan the block. This wouldn't be necessary if we had
1189 precalculated local_live, however with PROP_SCAN_DEAD_CODE
1190 local_live is really dependent on live_at_end. */
1191 CLEAR_REG_SET (tmp);
1192 rescan = bitmap_operation (tmp, bb->global_live_at_end,
1193 new_live_at_end, BITMAP_AND_COMPL);
e881bb1b 1194
402209ff
JH
1195 if (! rescan)
1196 {
1197 /* If any of the registers in the new live_at_end set are
1198 conditionally set in this basic block, we must rescan.
1199 This is because conditional lifetimes at the end of the
1200 block do not just take the live_at_end set into account,
1201 but also the liveness at the start of each successor
1202 block. We can miss changes in those sets if we only
1203 compare the new live_at_end against the previous one. */
1204 CLEAR_REG_SET (tmp);
1205 rescan = bitmap_operation (tmp, new_live_at_end,
1206 bb->cond_local_set, BITMAP_AND);
1207 }
e881bb1b 1208
402209ff
JH
1209 if (! rescan)
1210 {
1211 /* Find the set of changed bits. Take this opportunity
1212 to notice that this set is empty and early out. */
1213 CLEAR_REG_SET (tmp);
1214 changed = bitmap_operation (tmp, bb->global_live_at_end,
1215 new_live_at_end, BITMAP_XOR);
1216 if (! changed)
1217 continue;
e881bb1b 1218
402209ff
JH
1219 /* If any of the changed bits overlap with local_set,
1220 we'll have to rescan the block. Detect overlap by
1221 the AND with ~local_set turning off bits. */
1222 rescan = bitmap_operation (tmp, tmp, bb->local_set,
1223 BITMAP_AND_COMPL);
1224 }
1225 }
e881bb1b 1226
402209ff
JH
1227 /* Let our caller know that BB changed enough to require its
1228 death notes updated. */
1229 if (blocks_out)
0b17ab2f 1230 SET_BIT (blocks_out, bb->index);
e881bb1b 1231
402209ff
JH
1232 if (! rescan)
1233 {
1234 /* Add to live_at_start the set of all registers in
1235 new_live_at_end that aren't in the old live_at_end. */
19d3c25c 1236
402209ff
JH
1237 bitmap_operation (tmp, new_live_at_end, bb->global_live_at_end,
1238 BITMAP_AND_COMPL);
1239 COPY_REG_SET (bb->global_live_at_end, new_live_at_end);
c9bacfdb 1240
402209ff
JH
1241 changed = bitmap_operation (bb->global_live_at_start,
1242 bb->global_live_at_start,
1243 tmp, BITMAP_IOR);
1244 if (! changed)
1245 continue;
e881bb1b
RH
1246 }
1247 else
1248 {
402209ff 1249 COPY_REG_SET (bb->global_live_at_end, new_live_at_end);
e881bb1b 1250
402209ff
JH
1251 /* Rescan the block insn by insn to turn (a copy of) live_at_end
1252 into live_at_start. */
1253 propagate_block (bb, new_live_at_end, bb->local_set,
1254 bb->cond_local_set, flags);
e881bb1b 1255
402209ff
JH
1256 /* If live_at start didn't change, no need to go farther. */
1257 if (REG_SET_EQUAL_P (bb->global_live_at_start, new_live_at_end))
1258 continue;
e881bb1b 1259
402209ff
JH
1260 COPY_REG_SET (bb->global_live_at_start, new_live_at_end);
1261 }
a8688bd6 1262
402209ff
JH
1263 /* Queue all predecessors of BB so that we may re-examine
1264 their live_at_end. */
1265 for (e = bb->pred; e; e = e->pred_next)
1266 {
1267 basic_block pb = e->src;
1268 if (pb->aux == NULL)
1269 {
1270 *qtail++ = pb;
1271 if (qtail == qend)
1272 qtail = queue;
1273 pb->aux = pb;
1274 }
1275 }
a8688bd6
AM
1276 }
1277
402209ff
JH
1278 FREE_REG_SET (tmp);
1279 FREE_REG_SET (new_live_at_end);
f3ea5f6a 1280 FREE_REG_SET (invalidated_by_call);
f5540cd4 1281
402209ff
JH
1282 if (blocks_out)
1283 {
1284 EXECUTE_IF_SET_IN_SBITMAP (blocks_out, 0, i,
1285 {
0b17ab2f 1286 basic_block bb = BASIC_BLOCK (i);
402209ff
JH
1287 FREE_REG_SET (bb->local_set);
1288 FREE_REG_SET (bb->cond_local_set);
1289 });
e881bb1b
RH
1290 }
1291 else
1292 {
e0082a72 1293 FOR_EACH_BB (bb)
402209ff 1294 {
402209ff
JH
1295 FREE_REG_SET (bb->local_set);
1296 FREE_REG_SET (bb->cond_local_set);
1297 }
f5540cd4 1298 }
19d3c25c 1299
402209ff 1300 free (queue);
e881bb1b 1301}
0626ef8a
AM
1302
1303\f
09da1532 1304/* This structure is used to pass parameters to and from the
4a913dd6
EC
1305 the function find_regno_partial(). It is used to pass in the
1306 register number we are looking, as well as to return any rtx
0626ef8a
AM
1307 we find. */
1308
1309typedef struct {
1310 unsigned regno_to_find;
1311 rtx retval;
1312} find_regno_partial_param;
1313
1314
1315/* Find the rtx for the reg numbers specified in 'data' if it is
1316 part of an expression which only uses part of the register. Return
1317 it in the structure passed in. */
4a913dd6 1318static int
6cf9ac28 1319find_regno_partial (rtx *ptr, void *data)
0626ef8a
AM
1320{
1321 find_regno_partial_param *param = (find_regno_partial_param *)data;
1322 unsigned reg = param->regno_to_find;
1323 param->retval = NULL_RTX;
1324
1325 if (*ptr == NULL_RTX)
1326 return 0;
1327
4a913dd6 1328 switch (GET_CODE (*ptr))
0626ef8a 1329 {
448cad06
AH
1330 case ZERO_EXTRACT:
1331 case SIGN_EXTRACT:
1332 case STRICT_LOW_PART:
f8cfc6aa 1333 if (REG_P (XEXP (*ptr, 0)) && REGNO (XEXP (*ptr, 0)) == reg)
448cad06
AH
1334 {
1335 param->retval = XEXP (*ptr, 0);
1336 return 1;
1337 }
1338 break;
0626ef8a 1339
448cad06 1340 case SUBREG:
f8cfc6aa 1341 if (REG_P (SUBREG_REG (*ptr))
448cad06
AH
1342 && REGNO (SUBREG_REG (*ptr)) == reg)
1343 {
1344 param->retval = SUBREG_REG (*ptr);
1345 return 1;
1346 }
1347 break;
1348
1349 default:
1350 break;
0626ef8a
AM
1351 }
1352
1353 return 0;
1354}
1355
1356/* Process all immediate successors of the entry block looking for pseudo
4a913dd6
EC
1357 registers which are live on entry. Find all of those whose first
1358 instance is a partial register reference of some kind, and initialize
0626ef8a 1359 them to 0 after the entry block. This will prevent bit sets within
4a913dd6 1360 registers whose value is unknown, and may contain some kind of sticky
0626ef8a
AM
1361 bits we don't want. */
1362
1363int
6cf9ac28 1364initialize_uninitialized_subregs (void)
0626ef8a
AM
1365{
1366 rtx insn;
1367 edge e;
1368 int reg, did_something = 0;
1369 find_regno_partial_param param;
1370
1371 for (e = ENTRY_BLOCK_PTR->succ; e; e = e->succ_next)
1372 {
1373 basic_block bb = e->dest;
1374 regset map = bb->global_live_at_start;
1375 EXECUTE_IF_SET_IN_REG_SET (map,
1376 FIRST_PSEUDO_REGISTER, reg,
1377 {
1378 int uid = REGNO_FIRST_UID (reg);
1379 rtx i;
1380
1381 /* Find an insn which mentions the register we are looking for.
1382 Its preferable to have an instance of the register's rtl since
4a913dd6 1383 there may be various flags set which we need to duplicate.
0626ef8a 1384 If we can't find it, its probably an automatic whose initial
23d1aac4 1385 value doesn't matter, or hopefully something we don't care about. */
0626ef8a
AM
1386 for (i = get_insns (); i && INSN_UID (i) != uid; i = NEXT_INSN (i))
1387 ;
1388 if (i != NULL_RTX)
1389 {
1390 /* Found the insn, now get the REG rtx, if we can. */
1391 param.regno_to_find = reg;
1392 for_each_rtx (&i, find_regno_partial, &param);
1393 if (param.retval != NULL_RTX)
1394 {
a7a7d7ac
KH
1395 start_sequence ();
1396 emit_move_insn (param.retval,
1397 CONST0_RTX (GET_MODE (param.retval)));
1398 insn = get_insns ();
1399 end_sequence ();
0626ef8a
AM
1400 insert_insn_on_edge (insn, e);
1401 did_something = 1;
1402 }
1403 }
1404 });
1405 }
1406
1407 if (did_something)
1408 commit_edge_insertions ();
1409 return did_something;
1410}
1411
402209ff
JH
1412\f
1413/* Subroutines of life analysis. */
e881bb1b 1414
402209ff
JH
1415/* Allocate the permanent data structures that represent the results
1416 of life analysis. Not static since used also for stupid life analysis. */
e881bb1b
RH
1417
1418void
6cf9ac28 1419allocate_bb_life_data (void)
e881bb1b 1420{
e0082a72 1421 basic_block bb;
c9bacfdb 1422
e0082a72 1423 FOR_BB_BETWEEN (bb, ENTRY_BLOCK_PTR, NULL, next_bb)
e881bb1b 1424 {
402209ff
JH
1425 bb->global_live_at_start = OBSTACK_ALLOC_REG_SET (&flow_obstack);
1426 bb->global_live_at_end = OBSTACK_ALLOC_REG_SET (&flow_obstack);
e881bb1b 1427 }
f1330226 1428
402209ff
JH
1429 regs_live_at_setjmp = OBSTACK_ALLOC_REG_SET (&flow_obstack);
1430}
0ab409ed 1431
402209ff 1432void
6cf9ac28 1433allocate_reg_life_data (void)
0ab409ed
MH
1434{
1435 int i;
0ab409ed 1436
402209ff 1437 max_regno = max_reg_num ();
736b64dd
JH
1438 if (reg_deaths)
1439 abort ();
1440 reg_deaths = xcalloc (sizeof (*reg_deaths), max_regno);
0ab409ed 1441
402209ff
JH
1442 /* Recalculate the register space, in case it has grown. Old style
1443 vector oriented regsets would set regset_{size,bytes} here also. */
1444 allocate_reg_info (max_regno, FALSE, FALSE);
0ab409ed 1445
402209ff
JH
1446 /* Reset all the data we'll collect in propagate_block and its
1447 subroutines. */
1448 for (i = 0; i < max_regno; i++)
0ab409ed 1449 {
402209ff
JH
1450 REG_N_SETS (i) = 0;
1451 REG_N_REFS (i) = 0;
1452 REG_N_DEATHS (i) = 0;
1453 REG_N_CALLS_CROSSED (i) = 0;
1454 REG_LIVE_LENGTH (i) = 0;
e505be85 1455 REG_FREQ (i) = 0;
402209ff 1456 REG_BASIC_BLOCK (i) = REG_BLOCK_UNKNOWN;
0ab409ed 1457 }
402209ff 1458}
0ab409ed 1459
402209ff 1460/* Delete dead instructions for propagate_block. */
f1330226 1461
402209ff 1462static void
6cf9ac28 1463propagate_block_delete_insn (rtx insn)
402209ff
JH
1464{
1465 rtx inote = find_reg_note (insn, REG_LABEL, NULL_RTX);
f1330226 1466
402209ff
JH
1467 /* If the insn referred to a label, and that label was attached to
1468 an ADDR_VEC, it's safe to delete the ADDR_VEC. In fact, it's
1469 pretty much mandatory to delete it, because the ADDR_VEC may be
1470 referencing labels that no longer exist.
f1330226 1471
402209ff
JH
1472 INSN may reference a deleted label, particularly when a jump
1473 table has been optimized into a direct jump. There's no
1474 real good way to fix up the reference to the deleted label
19f71cd7 1475 when the label is deleted, so we just allow it here. */
0ab409ed 1476
4b4bf941 1477 if (inote && LABEL_P (inote))
0ab409ed 1478 {
402209ff
JH
1479 rtx label = XEXP (inote, 0);
1480 rtx next;
0ab409ed 1481
402209ff
JH
1482 /* The label may be forced if it has been put in the constant
1483 pool. If that is the only use we must discard the table
1484 jump following it, but not the label itself. */
1485 if (LABEL_NUSES (label) == 1 + LABEL_PRESERVE_P (label)
1486 && (next = next_nonnote_insn (label)) != NULL
4b4bf941 1487 && JUMP_P (next)
402209ff
JH
1488 && (GET_CODE (PATTERN (next)) == ADDR_VEC
1489 || GET_CODE (PATTERN (next)) == ADDR_DIFF_VEC))
0ab409ed 1490 {
402209ff
JH
1491 rtx pat = PATTERN (next);
1492 int diff_vec_p = GET_CODE (pat) == ADDR_DIFF_VEC;
1493 int len = XVECLEN (pat, diff_vec_p);
1494 int i;
f1330226 1495
402209ff
JH
1496 for (i = 0; i < len; i++)
1497 LABEL_NUSES (XEXP (XVECEXP (pat, diff_vec_p, i), 0))--;
0ab409ed 1498
3dec4024
JH
1499 delete_insn_and_edges (next);
1500 ndead++;
0ab409ed
MH
1501 }
1502 }
1503
3dec4024
JH
1504 delete_insn_and_edges (insn);
1505 ndead++;
0ab409ed 1506}
e881bb1b 1507
402209ff
JH
1508/* Delete dead libcalls for propagate_block. Return the insn
1509 before the libcall. */
e881bb1b 1510
402209ff 1511static rtx
6cf9ac28 1512propagate_block_delete_libcall (rtx insn, rtx note)
402209ff
JH
1513{
1514 rtx first = XEXP (note, 0);
1515 rtx before = PREV_INSN (first);
e881bb1b 1516
3dec4024
JH
1517 delete_insn_chain_and_edges (first, insn);
1518 ndead++;
402209ff 1519 return before;
1e29ee12
JL
1520}
1521
402209ff
JH
1522/* Update the life-status of regs for one insn. Return the previous insn. */
1523
1524rtx
6cf9ac28 1525propagate_one_insn (struct propagate_block_info *pbi, rtx insn)
1e29ee12 1526{
402209ff
JH
1527 rtx prev = PREV_INSN (insn);
1528 int flags = pbi->flags;
1529 int insn_is_dead = 0;
1530 int libcall_is_dead = 0;
1531 rtx note;
1e29ee12
JL
1532 int i;
1533
402209ff
JH
1534 if (! INSN_P (insn))
1535 return prev;
164d59e0 1536
402209ff
JH
1537 note = find_reg_note (insn, REG_RETVAL, NULL_RTX);
1538 if (flags & PROP_SCAN_DEAD_CODE)
1539 {
1540 insn_is_dead = insn_dead_p (pbi, PATTERN (insn), 0, REG_NOTES (insn));
1541 libcall_is_dead = (insn_is_dead && note != 0
1542 && libcall_dead_p (pbi, note, insn));
1543 }
e881bb1b 1544
402209ff
JH
1545 /* If an instruction consists of just dead store(s) on final pass,
1546 delete it. */
1547 if ((flags & PROP_KILL_DEAD_CODE) && insn_is_dead)
e881bb1b 1548 {
402209ff
JH
1549 /* If we're trying to delete a prologue or epilogue instruction
1550 that isn't flagged as possibly being dead, something is wrong.
1551 But if we are keeping the stack pointer depressed, we might well
1552 be deleting insns that are used to compute the amount to update
1553 it by, so they are fine. */
1554 if (reload_completed
1555 && !(TREE_CODE (TREE_TYPE (current_function_decl)) == FUNCTION_TYPE
1556 && (TYPE_RETURNS_STACK_DEPRESSED
1557 (TREE_TYPE (current_function_decl))))
1558 && (((HAVE_epilogue || HAVE_prologue)
1559 && prologue_epilogue_contains (insn))
1560 || (HAVE_sibcall_epilogue
1561 && sibcall_epilogue_contains (insn)))
1562 && find_reg_note (insn, REG_MAYBE_DEAD, NULL_RTX) == 0)
31fce3c4 1563 fatal_insn ("Attempt to delete prologue/epilogue insn:", insn);
e881bb1b 1564
402209ff
JH
1565 /* Record sets. Do this even for dead instructions, since they
1566 would have killed the values if they hadn't been deleted. */
1567 mark_set_regs (pbi, PATTERN (insn), insn);
e881bb1b 1568
402209ff
JH
1569 /* CC0 is now known to be dead. Either this insn used it,
1570 in which case it doesn't anymore, or clobbered it,
1571 so the next insn can't use it. */
1572 pbi->cc0_live = 0;
e881bb1b 1573
402209ff 1574 if (libcall_is_dead)
607a6500 1575 prev = propagate_block_delete_libcall ( insn, note);
d35dfca9
JL
1576 else
1577 {
1578
b0ac73f8
JL
1579 /* If INSN contains a RETVAL note and is dead, but the libcall
1580 as a whole is not dead, then we want to remove INSN, but
1581 not the whole libcall sequence.
1582
6cf9ac28 1583 However, we need to also remove the dangling REG_LIBCALL
b0ac73f8
JL
1584 note so that we do not have mis-matched LIBCALL/RETVAL
1585 notes. In theory we could find a new location for the
6cf9ac28 1586 REG_RETVAL note, but it hardly seems worth the effort.
b0ac73f8
JL
1587
1588 NOTE at this point will be the RETVAL note if it exists. */
d35dfca9
JL
1589 if (note)
1590 {
d35dfca9 1591 rtx libcall_note;
6cf9ac28 1592
d35dfca9
JL
1593 libcall_note
1594 = find_reg_note (XEXP (note, 0), REG_LIBCALL, NULL_RTX);
1595 remove_note (XEXP (note, 0), libcall_note);
1596 }
b0ac73f8
JL
1597
1598 /* Similarly if INSN contains a LIBCALL note, remove the
fbe5a4a6 1599 dangling REG_RETVAL note. */
b0ac73f8
JL
1600 note = find_reg_note (insn, REG_LIBCALL, NULL_RTX);
1601 if (note)
1602 {
1603 rtx retval_note;
1604
1605 retval_note
1606 = find_reg_note (XEXP (note, 0), REG_RETVAL, NULL_RTX);
1607 remove_note (XEXP (note, 0), retval_note);
1608 }
1609
1610 /* Now delete INSN. */
d35dfca9
JL
1611 propagate_block_delete_insn (insn);
1612 }
e881bb1b 1613
402209ff
JH
1614 return prev;
1615 }
e881bb1b 1616
402209ff
JH
1617 /* See if this is an increment or decrement that can be merged into
1618 a following memory address. */
1619#ifdef AUTO_INC_DEC
1620 {
b3694847 1621 rtx x = single_set (insn);
e881bb1b 1622
402209ff
JH
1623 /* Does this instruction increment or decrement a register? */
1624 if ((flags & PROP_AUTOINC)
1625 && x != 0
f8cfc6aa 1626 && REG_P (SET_DEST (x))
402209ff
JH
1627 && (GET_CODE (SET_SRC (x)) == PLUS
1628 || GET_CODE (SET_SRC (x)) == MINUS)
1629 && XEXP (SET_SRC (x), 0) == SET_DEST (x)
1630 && GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
1631 /* Ok, look for a following memory ref we can combine with.
1632 If one is found, change the memory ref to a PRE_INC
1633 or PRE_DEC, cancel this insn, and return 1.
1634 Return 0 if nothing has been done. */
1635 && try_pre_increment_1 (pbi, insn))
1636 return prev;
1637 }
1638#endif /* AUTO_INC_DEC */
e881bb1b 1639
402209ff 1640 CLEAR_REG_SET (pbi->new_set);
e881bb1b 1641
402209ff
JH
1642 /* If this is not the final pass, and this insn is copying the value of
1643 a library call and it's dead, don't scan the insns that perform the
1644 library call, so that the call's arguments are not marked live. */
1645 if (libcall_is_dead)
e881bb1b 1646 {
402209ff
JH
1647 /* Record the death of the dest reg. */
1648 mark_set_regs (pbi, PATTERN (insn), insn);
e881bb1b 1649
402209ff
JH
1650 insn = XEXP (note, 0);
1651 return PREV_INSN (insn);
e881bb1b 1652 }
402209ff
JH
1653 else if (GET_CODE (PATTERN (insn)) == SET
1654 && SET_DEST (PATTERN (insn)) == stack_pointer_rtx
1655 && GET_CODE (SET_SRC (PATTERN (insn))) == PLUS
1656 && XEXP (SET_SRC (PATTERN (insn)), 0) == stack_pointer_rtx
1657 && GET_CODE (XEXP (SET_SRC (PATTERN (insn)), 1)) == CONST_INT)
e344dbf3
R
1658 {
1659 /* We have an insn to pop a constant amount off the stack.
1660 (Such insns use PLUS regardless of the direction of the stack,
1661 and any insn to adjust the stack by a constant is always a pop
1662 or part of a push.)
1663 These insns, if not dead stores, have no effect on life, though
1664 they do have an effect on the memory stores we are tracking. */
1665 invalidate_mems_from_set (pbi, stack_pointer_rtx);
1666 /* Still, we need to update local_set, lest ifcvt.c:dead_or_predicable
1667 concludes that the stack pointer is not modified. */
1668 mark_set_regs (pbi, PATTERN (insn), insn);
1669 }
402209ff
JH
1670 else
1671 {
5a133afd 1672 rtx note;
402209ff
JH
1673 /* Any regs live at the time of a call instruction must not go
1674 in a register clobbered by calls. Find all regs now live and
1675 record this for them. */
e881bb1b 1676
4b4bf941 1677 if (CALL_P (insn) && (flags & PROP_REG_INFO))
402209ff
JH
1678 EXECUTE_IF_SET_IN_REG_SET (pbi->reg_live, 0, i,
1679 { REG_N_CALLS_CROSSED (i)++; });
e881bb1b 1680
402209ff
JH
1681 /* Record sets. Do this even for dead instructions, since they
1682 would have killed the values if they hadn't been deleted. */
1683 mark_set_regs (pbi, PATTERN (insn), insn);
e881bb1b 1684
4b4bf941 1685 if (CALL_P (insn))
402209ff 1686 {
d444b5e8
RH
1687 regset live_at_end;
1688 bool sibcall_p;
402209ff 1689 rtx note, cond;
d444b5e8 1690 int i;
e881bb1b 1691
402209ff
JH
1692 cond = NULL_RTX;
1693 if (GET_CODE (PATTERN (insn)) == COND_EXEC)
1694 cond = COND_EXEC_TEST (PATTERN (insn));
e881bb1b 1695
fe4b3c79
JL
1696 /* Non-constant calls clobber memory, constant calls do not
1697 clobber memory, though they may clobber outgoing arguments
1698 on the stack. */
402209ff
JH
1699 if (! CONST_OR_PURE_CALL_P (insn))
1700 {
1701 free_EXPR_LIST_list (&pbi->mem_set_list);
1702 pbi->mem_set_list_len = 0;
1703 }
dd3f0101 1704 else
fe4b3c79 1705 invalidate_mems_from_set (pbi, stack_pointer_rtx);
e881bb1b 1706
402209ff
JH
1707 /* There may be extra registers to be clobbered. */
1708 for (note = CALL_INSN_FUNCTION_USAGE (insn);
1709 note;
1710 note = XEXP (note, 1))
1711 if (GET_CODE (XEXP (note, 0)) == CLOBBER)
1712 mark_set_1 (pbi, CLOBBER, XEXP (XEXP (note, 0), 0),
1713 cond, insn, pbi->flags);
c9bacfdb 1714
d444b5e8 1715 /* Calls change all call-used and global registers; sibcalls do not
99af0d26
RH
1716 clobber anything that must be preserved at end-of-function,
1717 except for return values. */
d444b5e8
RH
1718
1719 sibcall_p = SIBLING_CALL_P (insn);
1720 live_at_end = EXIT_BLOCK_PTR->global_live_at_start;
402209ff 1721 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
d444b5e8 1722 if (TEST_HARD_REG_BIT (regs_invalidated_by_call, i)
99af0d26
RH
1723 && ! (sibcall_p
1724 && REGNO_REG_SET_P (live_at_end, i)
57856e4d
R
1725 && ! refers_to_regno_p (i, i+1,
1726 current_function_return_rtx,
1727 (rtx *) 0)))
402209ff 1728 {
a10016d3 1729 enum rtx_code code = global_regs[i] ? SET : CLOBBER;
402209ff 1730 /* We do not want REG_UNUSED notes for these registers. */
a10016d3 1731 mark_set_1 (pbi, code, regno_reg_rtx[i], cond, insn,
402209ff
JH
1732 pbi->flags & ~(PROP_DEATH_NOTES | PROP_REG_INFO));
1733 }
1734 }
312f6255 1735
402209ff
JH
1736 /* If an insn doesn't use CC0, it becomes dead since we assume
1737 that every insn clobbers it. So show it dead here;
1738 mark_used_regs will set it live if it is referenced. */
1739 pbi->cc0_live = 0;
e881bb1b 1740
402209ff
JH
1741 /* Record uses. */
1742 if (! insn_is_dead)
1743 mark_used_regs (pbi, PATTERN (insn), NULL_RTX, insn);
5a133afd
JH
1744 if ((flags & PROP_EQUAL_NOTES)
1745 && ((note = find_reg_note (insn, REG_EQUAL, NULL_RTX))
1746 || (note = find_reg_note (insn, REG_EQUIV, NULL_RTX))))
1747 mark_used_regs (pbi, XEXP (note, 0), NULL_RTX, insn);
e881bb1b 1748
402209ff
JH
1749 /* Sometimes we may have inserted something before INSN (such as a move)
1750 when we make an auto-inc. So ensure we will scan those insns. */
1751#ifdef AUTO_INC_DEC
1752 prev = PREV_INSN (insn);
1753#endif
e881bb1b 1754
4b4bf941 1755 if (! insn_is_dead && CALL_P (insn))
402209ff 1756 {
b3694847 1757 int i;
402209ff 1758 rtx note, cond;
e881bb1b 1759
402209ff
JH
1760 cond = NULL_RTX;
1761 if (GET_CODE (PATTERN (insn)) == COND_EXEC)
1762 cond = COND_EXEC_TEST (PATTERN (insn));
e881bb1b 1763
ee960939
OH
1764 /* Calls use their arguments, and may clobber memory which
1765 address involves some register. */
402209ff
JH
1766 for (note = CALL_INSN_FUNCTION_USAGE (insn);
1767 note;
1768 note = XEXP (note, 1))
ee960939
OH
1769 /* We find USE or CLOBBER entities in a FUNCTION_USAGE list: both
1770 of which mark_used_regs knows how to handle. */
1771 mark_used_regs (pbi, XEXP (XEXP (note, 0), 0), cond, insn);
e881bb1b 1772
402209ff 1773 /* The stack ptr is used (honorarily) by a CALL insn. */
736b64dd
JH
1774 if ((flags & PROP_REG_INFO)
1775 && !REGNO_REG_SET_P (pbi->reg_live, STACK_POINTER_REGNUM))
1776 reg_deaths[STACK_POINTER_REGNUM] = pbi->insn_num;
402209ff 1777 SET_REGNO_REG_SET (pbi->reg_live, STACK_POINTER_REGNUM);
e881bb1b 1778
402209ff
JH
1779 /* Calls may also reference any of the global registers,
1780 so they are made live. */
1781 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1782 if (global_regs[i])
e50126e8 1783 mark_used_reg (pbi, regno_reg_rtx[i], cond, insn);
402209ff 1784 }
e881bb1b
RH
1785 }
1786
736b64dd 1787 pbi->insn_num++;
402209ff
JH
1788
1789 return prev;
e881bb1b
RH
1790}
1791
402209ff
JH
1792/* Initialize a propagate_block_info struct for public consumption.
1793 Note that the structure itself is opaque to this file, but that
1794 the user can use the regsets provided here. */
e881bb1b 1795
402209ff 1796struct propagate_block_info *
6cf9ac28
AJ
1797init_propagate_block_info (basic_block bb, regset live, regset local_set,
1798 regset cond_local_set, int flags)
e881bb1b 1799{
402209ff 1800 struct propagate_block_info *pbi = xmalloc (sizeof (*pbi));
e881bb1b 1801
402209ff
JH
1802 pbi->bb = bb;
1803 pbi->reg_live = live;
1804 pbi->mem_set_list = NULL_RTX;
1805 pbi->mem_set_list_len = 0;
1806 pbi->local_set = local_set;
1807 pbi->cond_local_set = cond_local_set;
1808 pbi->cc0_live = 0;
1809 pbi->flags = flags;
736b64dd 1810 pbi->insn_num = 0;
c9bacfdb 1811
402209ff 1812 if (flags & (PROP_LOG_LINKS | PROP_AUTOINC))
703ad42b 1813 pbi->reg_next_use = xcalloc (max_reg_num (), sizeof (rtx));
e881bb1b 1814 else
402209ff 1815 pbi->reg_next_use = NULL;
e6cfb550 1816
402209ff 1817 pbi->new_set = BITMAP_XMALLOC ();
7a442791 1818
402209ff
JH
1819#ifdef HAVE_conditional_execution
1820 pbi->reg_cond_dead = splay_tree_new (splay_tree_compare_ints, NULL,
1821 free_reg_cond_life_info);
1822 pbi->reg_cond_reg = BITMAP_XMALLOC ();
7a442791 1823
38b2a605
RE
1824 /* If this block ends in a conditional branch, for each register
1825 live from one side of the branch and not the other, record the
1826 register as conditionally dead. */
4b4bf941 1827 if (JUMP_P (BB_END (bb))
a813c111 1828 && any_condjump_p (BB_END (bb)))
402209ff
JH
1829 {
1830 regset_head diff_head;
1831 regset diff = INITIALIZE_REG_SET (diff_head);
1832 basic_block bb_true, bb_false;
402209ff 1833 int i;
421382ac 1834
402209ff
JH
1835 /* Identify the successor blocks. */
1836 bb_true = bb->succ->dest;
1837 if (bb->succ->succ_next != NULL)
1838 {
1839 bb_false = bb->succ->succ_next->dest;
c9bacfdb 1840
402209ff
JH
1841 if (bb->succ->flags & EDGE_FALLTHRU)
1842 {
1843 basic_block t = bb_false;
1844 bb_false = bb_true;
1845 bb_true = t;
1846 }
1847 else if (! (bb->succ->succ_next->flags & EDGE_FALLTHRU))
1848 abort ();
1849 }
1850 else
1851 {
1852 /* This can happen with a conditional jump to the next insn. */
a813c111 1853 if (JUMP_LABEL (BB_END (bb)) != BB_HEAD (bb_true))
402209ff 1854 abort ();
421382ac 1855
402209ff
JH
1856 /* Simplest way to do nothing. */
1857 bb_false = bb_true;
1858 }
be1bb652 1859
402209ff
JH
1860 /* Compute which register lead different lives in the successors. */
1861 if (bitmap_operation (diff, bb_true->global_live_at_start,
1862 bb_false->global_live_at_start, BITMAP_XOR))
1863 {
38b2a605 1864 /* Extract the condition from the branch. */
a813c111 1865 rtx set_src = SET_SRC (pc_set (BB_END (bb)));
38b2a605 1866 rtx cond_true = XEXP (set_src, 0);
402209ff 1867 rtx reg = XEXP (cond_true, 0);
8965ece1 1868 enum rtx_code inv_cond;
be1bb652 1869
402209ff
JH
1870 if (GET_CODE (reg) == SUBREG)
1871 reg = SUBREG_REG (reg);
dc108b7a 1872
38b2a605 1873 /* We can only track conditional lifetimes if the condition is
8965ece1
PB
1874 in the form of a reversible comparison of a register against
1875 zero. If the condition is more complex than that, then it is
1876 safe not to record any information. */
1877 inv_cond = reversed_comparison_code (cond_true, BB_END (bb));
1878 if (inv_cond != UNKNOWN
1879 && REG_P (reg)
38b2a605
RE
1880 && XEXP (cond_true, 1) == const0_rtx)
1881 {
1882 rtx cond_false
8965ece1 1883 = gen_rtx_fmt_ee (inv_cond,
38b2a605
RE
1884 GET_MODE (cond_true), XEXP (cond_true, 0),
1885 XEXP (cond_true, 1));
1886 if (GET_CODE (XEXP (set_src, 1)) == PC)
1887 {
1888 rtx t = cond_false;
1889 cond_false = cond_true;
1890 cond_true = t;
1891 }
dc108b7a 1892
38b2a605 1893 SET_REGNO_REG_SET (pbi->reg_cond_reg, REGNO (reg));
dc108b7a 1894
38b2a605
RE
1895 /* For each such register, mark it conditionally dead. */
1896 EXECUTE_IF_SET_IN_REG_SET
1897 (diff, 0, i,
1898 {
1899 struct reg_cond_life_info *rcli;
1900 rtx cond;
dc108b7a 1901
38b2a605 1902 rcli = xmalloc (sizeof (*rcli));
dc108b7a 1903
38b2a605
RE
1904 if (REGNO_REG_SET_P (bb_true->global_live_at_start, i))
1905 cond = cond_false;
1906 else
1907 cond = cond_true;
1908 rcli->condition = cond;
1909 rcli->stores = const0_rtx;
1910 rcli->orig_condition = cond;
dc108b7a 1911
38b2a605
RE
1912 splay_tree_insert (pbi->reg_cond_dead, i,
1913 (splay_tree_value) rcli);
1914 });
1915 }
dc108b7a 1916 }
dc108b7a 1917
402209ff 1918 FREE_REG_SET (diff);
dc108b7a 1919 }
402209ff
JH
1920#endif
1921
1922 /* If this block has no successors, any stores to the frame that aren't
1923 used later in the block are dead. So make a pass over the block
1924 recording any such that are made and show them dead at the end. We do
1925 a very conservative and simple job here. */
1926 if (optimize
1927 && ! (TREE_CODE (TREE_TYPE (current_function_decl)) == FUNCTION_TYPE
1928 && (TYPE_RETURNS_STACK_DEPRESSED
1929 (TREE_TYPE (current_function_decl))))
5149f070 1930 && (flags & PROP_SCAN_DEAD_STORES)
402209ff
JH
1931 && (bb->succ == NULL
1932 || (bb->succ->succ_next == NULL
1933 && bb->succ->dest == EXIT_BLOCK_PTR
1934 && ! current_function_calls_eh_return)))
dc108b7a 1935 {
402209ff 1936 rtx insn, set;
a813c111 1937 for (insn = BB_END (bb); insn != BB_HEAD (bb); insn = PREV_INSN (insn))
4b4bf941 1938 if (NONJUMP_INSN_P (insn)
402209ff 1939 && (set = single_set (insn))
3c0cb5de 1940 && MEM_P (SET_DEST (set)))
402209ff
JH
1941 {
1942 rtx mem = SET_DEST (set);
1943 rtx canon_mem = canon_rtx (mem);
1944
402209ff
JH
1945 if (XEXP (canon_mem, 0) == frame_pointer_rtx
1946 || (GET_CODE (XEXP (canon_mem, 0)) == PLUS
1947 && XEXP (XEXP (canon_mem, 0), 0) == frame_pointer_rtx
1948 && GET_CODE (XEXP (XEXP (canon_mem, 0), 1)) == CONST_INT))
1949 add_to_mem_set_list (pbi, canon_mem);
1950 }
dc108b7a 1951 }
dc108b7a 1952
402209ff 1953 return pbi;
dc108b7a
RH
1954}
1955
402209ff 1956/* Release a propagate_block_info struct. */
558389e3 1957
402209ff 1958void
6cf9ac28 1959free_propagate_block_info (struct propagate_block_info *pbi)
558389e3 1960{
402209ff 1961 free_EXPR_LIST_list (&pbi->mem_set_list);
558389e3 1962
402209ff 1963 BITMAP_XFREE (pbi->new_set);
558389e3 1964
402209ff
JH
1965#ifdef HAVE_conditional_execution
1966 splay_tree_delete (pbi->reg_cond_dead);
1967 BITMAP_XFREE (pbi->reg_cond_reg);
1968#endif
558389e3 1969
736b64dd
JH
1970 if (pbi->flags & PROP_REG_INFO)
1971 {
1972 int num = pbi->insn_num;
1973 int i;
1974
1975 EXECUTE_IF_SET_IN_REG_SET (pbi->reg_live, 0, i,
1976 { REG_LIVE_LENGTH (i) += num - reg_deaths[i];
1977 reg_deaths[i] = 0;
1978 });
1979 }
402209ff
JH
1980 if (pbi->reg_next_use)
1981 free (pbi->reg_next_use);
558389e3 1982
402209ff
JH
1983 free (pbi);
1984}
336a6399 1985
402209ff
JH
1986/* Compute the registers live at the beginning of a basic block BB from
1987 those live at the end.
c9bacfdb 1988
402209ff
JH
1989 When called, REG_LIVE contains those live at the end. On return, it
1990 contains those live at the beginning.
ee7b8369 1991
402209ff
JH
1992 LOCAL_SET, if non-null, will be set with all registers killed
1993 unconditionally by this basic block.
1994 Likewise, COND_LOCAL_SET, if non-null, will be set with all registers
1995 killed conditionally by this basic block. If there is any unconditional
1996 set of a register, then the corresponding bit will be set in LOCAL_SET
1997 and cleared in COND_LOCAL_SET.
1998 It is valid for LOCAL_SET and COND_LOCAL_SET to be the same set. In this
1999 case, the resulting set will be equal to the union of the two sets that
2000 would otherwise be computed.
558389e3 2001
cc2902df 2002 Return nonzero if an INSN is deleted (i.e. by dead code removal). */
558389e3 2003
402209ff 2004int
6cf9ac28
AJ
2005propagate_block (basic_block bb, regset live, regset local_set,
2006 regset cond_local_set, int flags)
558389e3 2007{
402209ff
JH
2008 struct propagate_block_info *pbi;
2009 rtx insn, prev;
2010 int changed;
558389e3 2011
402209ff 2012 pbi = init_propagate_block_info (bb, live, local_set, cond_local_set, flags);
be1bb652 2013
402209ff 2014 if (flags & PROP_REG_INFO)
be1bb652 2015 {
b3694847 2016 int i;
558389e3 2017
402209ff
JH
2018 /* Process the regs live at the end of the block.
2019 Mark them as not local to any one basic block. */
2020 EXECUTE_IF_SET_IN_REG_SET (live, 0, i,
2021 { REG_BASIC_BLOCK (i) = REG_BLOCK_GLOBAL; });
2022 }
558389e3 2023
402209ff 2024 /* Scan the block an insn at a time from end to beginning. */
558389e3 2025
402209ff 2026 changed = 0;
a813c111 2027 for (insn = BB_END (bb); ; insn = prev)
402209ff
JH
2028 {
2029 /* If this is a call to `setjmp' et al, warn if any
2030 non-volatile datum is live. */
2031 if ((flags & PROP_REG_INFO)
4b4bf941 2032 && CALL_P (insn)
402209ff
JH
2033 && find_reg_note (insn, REG_SETJMP, NULL))
2034 IOR_REG_SET (regs_live_at_setjmp, pbi->reg_live);
558389e3 2035
402209ff 2036 prev = propagate_one_insn (pbi, insn);
bc35512f
JH
2037 if (!prev)
2038 changed |= insn != get_insns ();
2039 else
2040 changed |= NEXT_INSN (prev) != insn;
336a6399 2041
a813c111 2042 if (insn == BB_HEAD (bb))
402209ff 2043 break;
336a6399
RH
2044 }
2045
402209ff
JH
2046 free_propagate_block_info (pbi);
2047
2048 return changed;
558389e3 2049}
402209ff
JH
2050\f
2051/* Return 1 if X (the body of an insn, or part of it) is just dead stores
2052 (SET expressions whose destinations are registers dead after the insn).
2053 NEEDED is the regset that says which regs are alive after the insn.
2054
cc2902df 2055 Unless CALL_OK is nonzero, an insn is needed if it contains a CALL.
558389e3 2056
402209ff
JH
2057 If X is the entire body of an insn, NOTES contains the reg notes
2058 pertaining to the insn. */
dc2ede84 2059
dc2ede84 2060static int
6cf9ac28
AJ
2061insn_dead_p (struct propagate_block_info *pbi, rtx x, int call_ok,
2062 rtx notes ATTRIBUTE_UNUSED)
dc2ede84 2063{
402209ff 2064 enum rtx_code code = GET_CODE (x);
be1bb652 2065
a646f6cc
AH
2066 /* Don't eliminate insns that may trap. */
2067 if (flag_non_call_exceptions && may_trap_p (x))
2068 return 0;
2069
402209ff 2070#ifdef AUTO_INC_DEC
ff6051b7
GK
2071 /* As flow is invoked after combine, we must take existing AUTO_INC
2072 expressions into account. */
2073 for (; notes; notes = XEXP (notes, 1))
e881bb1b 2074 {
ff6051b7 2075 if (REG_NOTE_KIND (notes) == REG_INC)
336a6399 2076 {
ff6051b7 2077 int regno = REGNO (XEXP (notes, 0));
4a913dd6 2078
ff6051b7
GK
2079 /* Don't delete insns to set global regs. */
2080 if ((regno < FIRST_PSEUDO_REGISTER && global_regs[regno])
2081 || REGNO_REG_SET_P (pbi->reg_live, regno))
2082 return 0;
402209ff 2083 }
336a6399 2084 }
402209ff 2085#endif
4793dca1 2086
402209ff
JH
2087 /* If setting something that's a reg or part of one,
2088 see if that register's altered value will be live. */
558389e3 2089
402209ff 2090 if (code == SET)
7a442791 2091 {
402209ff 2092 rtx r = SET_DEST (x);
b02eea61 2093
402209ff
JH
2094#ifdef HAVE_cc0
2095 if (GET_CODE (r) == CC0)
2096 return ! pbi->cc0_live;
2097#endif
b9f22704 2098
402209ff
JH
2099 /* A SET that is a subroutine call cannot be dead. */
2100 if (GET_CODE (SET_SRC (x)) == CALL)
2101 {
2102 if (! call_ok)
2103 return 0;
2104 }
b02eea61 2105
402209ff
JH
2106 /* Don't eliminate loads from volatile memory or volatile asms. */
2107 else if (volatile_refs_p (SET_SRC (x)))
2108 return 0;
7a442791 2109
3c0cb5de 2110 if (MEM_P (r))
7a442791 2111 {
402209ff 2112 rtx temp, canon_r;
b9f22704 2113
402209ff
JH
2114 if (MEM_VOLATILE_P (r) || GET_MODE (r) == BLKmode)
2115 return 0;
0068fd96 2116
402209ff 2117 canon_r = canon_rtx (r);
0068fd96 2118
402209ff
JH
2119 /* Walk the set of memory locations we are currently tracking
2120 and see if one is an identical match to this memory location.
2121 If so, this memory write is dead (remember, we're walking
2122 backwards from the end of the block to the start). Since
2123 rtx_equal_p does not check the alias set or flags, we also
2124 must have the potential for them to conflict (anti_dependence). */
2125 for (temp = pbi->mem_set_list; temp != 0; temp = XEXP (temp, 1))
389fdba0 2126 if (anti_dependence (r, XEXP (temp, 0)))
402209ff
JH
2127 {
2128 rtx mem = XEXP (temp, 0);
0068fd96 2129
402209ff
JH
2130 if (rtx_equal_p (XEXP (canon_r, 0), XEXP (mem, 0))
2131 && (GET_MODE_SIZE (GET_MODE (canon_r))
2132 <= GET_MODE_SIZE (GET_MODE (mem))))
2133 return 1;
7a442791 2134
402209ff
JH
2135#ifdef AUTO_INC_DEC
2136 /* Check if memory reference matches an auto increment. Only
2137 post increment/decrement or modify are valid. */
2138 if (GET_MODE (mem) == GET_MODE (r)
2139 && (GET_CODE (XEXP (mem, 0)) == POST_DEC
2140 || GET_CODE (XEXP (mem, 0)) == POST_INC
2141 || GET_CODE (XEXP (mem, 0)) == POST_MODIFY)
2142 && GET_MODE (XEXP (mem, 0)) == GET_MODE (r)
2143 && rtx_equal_p (XEXP (XEXP (mem, 0), 0), XEXP (r, 0)))
2144 return 1;
2145#endif
2146 }
b02eea61 2147 }
d69d0316 2148 else
7a442791 2149 {
402209ff
JH
2150 while (GET_CODE (r) == SUBREG
2151 || GET_CODE (r) == STRICT_LOW_PART
2152 || GET_CODE (r) == ZERO_EXTRACT)
2153 r = XEXP (r, 0);
b02eea61 2154
f8cfc6aa 2155 if (REG_P (r))
d69d0316 2156 {
402209ff 2157 int regno = REGNO (r);
b02eea61 2158
402209ff
JH
2159 /* Obvious. */
2160 if (REGNO_REG_SET_P (pbi->reg_live, regno))
2161 return 0;
7a442791 2162
402209ff
JH
2163 /* If this is a hard register, verify that subsequent
2164 words are not needed. */
2165 if (regno < FIRST_PSEUDO_REGISTER)
2166 {
66fd46b6 2167 int n = hard_regno_nregs[regno][GET_MODE (r)];
46fac664 2168
402209ff
JH
2169 while (--n > 0)
2170 if (REGNO_REG_SET_P (pbi->reg_live, regno+n))
2171 return 0;
2172 }
46fac664 2173
402209ff
JH
2174 /* Don't delete insns to set global regs. */
2175 if (regno < FIRST_PSEUDO_REGISTER && global_regs[regno])
2176 return 0;
46fac664 2177
402209ff
JH
2178 /* Make sure insns to set the stack pointer aren't deleted. */
2179 if (regno == STACK_POINTER_REGNUM)
2180 return 0;
b02eea61 2181
402209ff
JH
2182 /* ??? These bits might be redundant with the force live bits
2183 in calculate_global_regs_live. We would delete from
2184 sequential sets; whether this actually affects real code
2185 for anything but the stack pointer I don't know. */
2186 /* Make sure insns to set the frame pointer aren't deleted. */
2187 if (regno == FRAME_POINTER_REGNUM
2188 && (! reload_completed || frame_pointer_needed))
2189 return 0;
2190#if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
2191 if (regno == HARD_FRAME_POINTER_REGNUM
2192 && (! reload_completed || frame_pointer_needed))
2193 return 0;
2194#endif
b02eea61 2195
402209ff
JH
2196#if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
2197 /* Make sure insns to set arg pointer are never deleted
2198 (if the arg pointer isn't fixed, there will be a USE
2199 for it, so we can treat it normally). */
2200 if (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
2201 return 0;
2202#endif
46fac664 2203
402209ff
JH
2204 /* Otherwise, the set is dead. */
2205 return 1;
2206 }
2207 }
2208 }
46fac664 2209
402209ff
JH
2210 /* If performing several activities, insn is dead if each activity
2211 is individually dead. Also, CLOBBERs and USEs can be ignored; a
2212 CLOBBER or USE that's inside a PARALLEL doesn't make the insn
2213 worth keeping. */
2214 else if (code == PARALLEL)
2215 {
2216 int i = XVECLEN (x, 0);
46fac664 2217
402209ff
JH
2218 for (i--; i >= 0; i--)
2219 if (GET_CODE (XVECEXP (x, 0, i)) != CLOBBER
2220 && GET_CODE (XVECEXP (x, 0, i)) != USE
2221 && ! insn_dead_p (pbi, XVECEXP (x, 0, i), call_ok, NULL_RTX))
2222 return 0;
46fac664 2223
402209ff
JH
2224 return 1;
2225 }
46fac664 2226
402209ff 2227 /* A CLOBBER of a pseudo-register that is dead serves no purpose. That
a6abdce3
RH
2228 is not necessarily true for hard registers until after reload. */
2229 else if (code == CLOBBER)
2230 {
f8cfc6aa 2231 if (REG_P (XEXP (x, 0))
a6abdce3
RH
2232 && (REGNO (XEXP (x, 0)) >= FIRST_PSEUDO_REGISTER
2233 || reload_completed)
2234 && ! REGNO_REG_SET_P (pbi->reg_live, REGNO (XEXP (x, 0))))
2235 return 1;
2236 }
2237
2238 /* ??? A base USE is a historical relic. It ought not be needed anymore.
2239 Instances where it is still used are either (1) temporary and the USE
2240 escaped the pass, (2) cruft and the USE need not be emitted anymore,
2241 or (3) hiding bugs elsewhere that are not properly representing data
2242 flow. */
2243
402209ff
JH
2244 return 0;
2245}
46fac664 2246
402209ff
JH
2247/* If INSN is the last insn in a libcall, and assuming INSN is dead,
2248 return 1 if the entire library call is dead.
2249 This is true if INSN copies a register (hard or pseudo)
2250 and if the hard return reg of the call insn is dead.
2251 (The caller should have tested the destination of the SET inside
2252 INSN already for death.)
46fac664 2253
402209ff
JH
2254 If this insn doesn't just copy a register, then we don't
2255 have an ordinary libcall. In that case, cse could not have
2256 managed to substitute the source for the dest later on,
2257 so we can assume the libcall is dead.
46fac664 2258
402209ff
JH
2259 PBI is the block info giving pseudoregs live before this insn.
2260 NOTE is the REG_RETVAL note of the insn. */
46fac664 2261
402209ff 2262static int
6cf9ac28 2263libcall_dead_p (struct propagate_block_info *pbi, rtx note, rtx insn)
402209ff
JH
2264{
2265 rtx x = single_set (insn);
46fac664 2266
402209ff
JH
2267 if (x)
2268 {
b3694847 2269 rtx r = SET_SRC (x);
46fac664 2270
f8cfc6aa 2271 if (REG_P (r))
402209ff
JH
2272 {
2273 rtx call = XEXP (note, 0);
2274 rtx call_pat;
b3694847 2275 int i;
46fac664 2276
402209ff 2277 /* Find the call insn. */
4b4bf941 2278 while (call != insn && !CALL_P (call))
402209ff 2279 call = NEXT_INSN (call);
46fac664 2280
402209ff
JH
2281 /* If there is none, do nothing special,
2282 since ordinary death handling can understand these insns. */
2283 if (call == insn)
2284 return 0;
b02eea61 2285
402209ff
JH
2286 /* See if the hard reg holding the value is dead.
2287 If this is a PARALLEL, find the call within it. */
2288 call_pat = PATTERN (call);
2289 if (GET_CODE (call_pat) == PARALLEL)
46fac664 2290 {
402209ff
JH
2291 for (i = XVECLEN (call_pat, 0) - 1; i >= 0; i--)
2292 if (GET_CODE (XVECEXP (call_pat, 0, i)) == SET
2293 && GET_CODE (SET_SRC (XVECEXP (call_pat, 0, i))) == CALL)
2294 break;
2295
2296 /* This may be a library call that is returning a value
2297 via invisible pointer. Do nothing special, since
2298 ordinary death handling can understand these insns. */
2299 if (i < 0)
2300 return 0;
2301
2302 call_pat = XVECEXP (call_pat, 0, i);
46fac664 2303 }
46fac664 2304
402209ff 2305 return insn_dead_p (pbi, call_pat, 1, REG_NOTES (call));
46fac664 2306 }
46fac664 2307 }
402209ff
JH
2308 return 1;
2309}
46fac664 2310
402209ff
JH
2311/* 1 if register REGNO was alive at a place where `setjmp' was called
2312 and was set more than once or is an argument.
2313 Such regs may be clobbered by `longjmp'. */
b02eea61 2314
402209ff 2315int
6cf9ac28 2316regno_clobbered_at_setjmp (int regno)
402209ff 2317{
0b17ab2f 2318 if (n_basic_blocks == 0)
402209ff
JH
2319 return 0;
2320
2321 return ((REG_N_SETS (regno) > 1
cdd1f01b 2322 || REGNO_REG_SET_P (ENTRY_BLOCK_PTR->global_live_at_end, regno))
402209ff
JH
2323 && REGNO_REG_SET_P (regs_live_at_setjmp, regno));
2324}
2325\f
2326/* Add MEM to PBI->MEM_SET_LIST. MEM should be canonical. Respect the
2327 maximal list size; look for overlaps in mode and select the largest. */
2328static void
6cf9ac28 2329add_to_mem_set_list (struct propagate_block_info *pbi, rtx mem)
46fac664 2330{
402209ff
JH
2331 rtx i;
2332
2333 /* We don't know how large a BLKmode store is, so we must not
2334 take them into consideration. */
2335 if (GET_MODE (mem) == BLKmode)
2336 return;
2337
2338 for (i = pbi->mem_set_list; i ; i = XEXP (i, 1))
46fac664 2339 {
402209ff
JH
2340 rtx e = XEXP (i, 0);
2341 if (rtx_equal_p (XEXP (mem, 0), XEXP (e, 0)))
46fac664 2342 {
402209ff 2343 if (GET_MODE_SIZE (GET_MODE (mem)) > GET_MODE_SIZE (GET_MODE (e)))
b02eea61 2344 {
402209ff
JH
2345#ifdef AUTO_INC_DEC
2346 /* If we must store a copy of the mem, we can just modify
2347 the mode of the stored copy. */
2348 if (pbi->flags & PROP_AUTOINC)
2349 PUT_MODE (e, GET_MODE (mem));
2350 else
2351#endif
2352 XEXP (i, 0) = mem;
b02eea61 2353 }
402209ff 2354 return;
46fac664 2355 }
46fac664 2356 }
b02eea61 2357
402209ff
JH
2358 if (pbi->mem_set_list_len < MAX_MEM_SET_LIST_LEN)
2359 {
2360#ifdef AUTO_INC_DEC
2361 /* Store a copy of mem, otherwise the address may be
2362 scrogged by find_auto_inc. */
2363 if (pbi->flags & PROP_AUTOINC)
2364 mem = shallow_copy_rtx (mem);
2365#endif
2366 pbi->mem_set_list = alloc_EXPR_LIST (0, mem, pbi->mem_set_list);
2367 pbi->mem_set_list_len++;
2368 }
46fac664
JH
2369}
2370
402209ff
JH
2371/* INSN references memory, possibly using autoincrement addressing modes.
2372 Find any entries on the mem_set_list that need to be invalidated due
2373 to an address change. */
b02eea61 2374
fe4b3c79 2375static int
6cf9ac28 2376invalidate_mems_from_autoinc (rtx *px, void *data)
46fac664 2377{
fe4b3c79
JL
2378 rtx x = *px;
2379 struct propagate_block_info *pbi = data;
2380
ec8e098d 2381 if (GET_RTX_CLASS (GET_CODE (x)) == RTX_AUTOINC)
fe4b3c79
JL
2382 {
2383 invalidate_mems_from_set (pbi, XEXP (x, 0));
2384 return -1;
2385 }
2386
2387 return 0;
402209ff 2388}
46fac664 2389
ff7cc307 2390/* EXP is a REG. Remove any dependent entries from pbi->mem_set_list. */
46fac664 2391
402209ff 2392static void
6cf9ac28 2393invalidate_mems_from_set (struct propagate_block_info *pbi, rtx exp)
402209ff
JH
2394{
2395 rtx temp = pbi->mem_set_list;
2396 rtx prev = NULL_RTX;
2397 rtx next;
46fac664 2398
402209ff 2399 while (temp)
46fac664 2400 {
402209ff
JH
2401 next = XEXP (temp, 1);
2402 if (reg_overlap_mentioned_p (exp, XEXP (temp, 0)))
46fac664 2403 {
402209ff
JH
2404 /* Splice this entry out of the list. */
2405 if (prev)
2406 XEXP (prev, 1) = next;
2407 else
2408 pbi->mem_set_list = next;
2409 free_EXPR_LIST_node (temp);
2410 pbi->mem_set_list_len--;
46fac664 2411 }
46fac664 2412 else
402209ff
JH
2413 prev = temp;
2414 temp = next;
46fac664 2415 }
402209ff 2416}
46fac664 2417
402209ff
JH
2418/* Process the registers that are set within X. Their bits are set to
2419 1 in the regset DEAD, because they are dead prior to this insn.
b02eea61 2420
402209ff 2421 If INSN is nonzero, it is the insn being processed.
46fac664 2422
402209ff 2423 FLAGS is the set of operations to perform. */
b02eea61 2424
402209ff 2425static void
6cf9ac28 2426mark_set_regs (struct propagate_block_info *pbi, rtx x, rtx insn)
46fac664 2427{
402209ff
JH
2428 rtx cond = NULL_RTX;
2429 rtx link;
2430 enum rtx_code code;
df2ef49b 2431 int flags = pbi->flags;
46fac664 2432
402209ff
JH
2433 if (insn)
2434 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
2435 {
2436 if (REG_NOTE_KIND (link) == REG_INC)
2437 mark_set_1 (pbi, SET, XEXP (link, 0),
2438 (GET_CODE (x) == COND_EXEC
2439 ? COND_EXEC_TEST (x) : NULL_RTX),
df2ef49b 2440 insn, flags);
402209ff
JH
2441 }
2442 retry:
2443 switch (code = GET_CODE (x))
46fac664 2444 {
402209ff 2445 case SET:
df2ef49b
AM
2446 if (GET_CODE (XEXP (x, 1)) == ASM_OPERANDS)
2447 flags |= PROP_ASM_SCAN;
ba228239 2448 /* Fall through */
402209ff 2449 case CLOBBER:
df2ef49b 2450 mark_set_1 (pbi, code, SET_DEST (x), cond, insn, flags);
402209ff 2451 return;
b02eea61 2452
402209ff
JH
2453 case COND_EXEC:
2454 cond = COND_EXEC_TEST (x);
2455 x = COND_EXEC_CODE (x);
2456 goto retry;
b02eea61 2457
402209ff
JH
2458 case PARALLEL:
2459 {
b3694847
SS
2460 int i;
2461
a06f01ba
JW
2462 /* We must scan forwards. If we have an asm, we need to set
2463 the PROP_ASM_SCAN flag before scanning the clobbers. */
2464 for (i = 0; i < XVECLEN (x, 0); i++)
402209ff
JH
2465 {
2466 rtx sub = XVECEXP (x, 0, i);
2467 switch (code = GET_CODE (sub))
2468 {
2469 case COND_EXEC:
2470 if (cond != NULL_RTX)
2471 abort ();
b02eea61 2472
402209ff
JH
2473 cond = COND_EXEC_TEST (sub);
2474 sub = COND_EXEC_CODE (sub);
df2ef49b
AM
2475 if (GET_CODE (sub) == SET)
2476 goto mark_set;
2477 if (GET_CODE (sub) == CLOBBER)
2478 goto mark_clob;
2479 break;
b02eea61 2480
402209ff 2481 case SET:
df2ef49b
AM
2482 mark_set:
2483 if (GET_CODE (XEXP (sub, 1)) == ASM_OPERANDS)
2484 flags |= PROP_ASM_SCAN;
ba228239 2485 /* Fall through */
402209ff 2486 case CLOBBER:
df2ef49b
AM
2487 mark_clob:
2488 mark_set_1 (pbi, code, SET_DEST (sub), cond, insn, flags);
402209ff 2489 break;
b02eea61 2490
a06f01ba
JW
2491 case ASM_OPERANDS:
2492 flags |= PROP_ASM_SCAN;
2493 break;
2494
402209ff
JH
2495 default:
2496 break;
2497 }
2498 }
2499 break;
2500 }
b02eea61 2501
402209ff
JH
2502 default:
2503 break;
46fac664 2504 }
46fac664
JH
2505}
2506
402209ff
JH
2507/* Process a single set, which appears in INSN. REG (which may not
2508 actually be a REG, it may also be a SUBREG, PARALLEL, etc.) is
2509 being set using the CODE (which may be SET, CLOBBER, or COND_EXEC).
2510 If the set is conditional (because it appear in a COND_EXEC), COND
2511 will be the condition. */
7a442791 2512
402209ff 2513static void
6cf9ac28 2514mark_set_1 (struct propagate_block_info *pbi, enum rtx_code code, rtx reg, rtx cond, rtx insn, int flags)
336a6399 2515{
402209ff
JH
2516 int regno_first = -1, regno_last = -1;
2517 unsigned long not_dead = 0;
336a6399
RH
2518 int i;
2519
402209ff
JH
2520 /* Modifying just one hardware register of a multi-reg value or just a
2521 byte field of a register does not mean the value from before this insn
2522 is now dead. Of course, if it was dead after it's unused now. */
336a6399 2523
402209ff 2524 switch (GET_CODE (reg))
336a6399 2525 {
402209ff
JH
2526 case PARALLEL:
2527 /* Some targets place small structures in registers for return values of
2528 functions. We have to detect this case specially here to get correct
2529 flow information. */
2530 for (i = XVECLEN (reg, 0) - 1; i >= 0; i--)
2531 if (XEXP (XVECEXP (reg, 0, i), 0) != 0)
2532 mark_set_1 (pbi, code, XEXP (XVECEXP (reg, 0, i), 0), cond, insn,
2533 flags);
2534 return;
2535
2536 case ZERO_EXTRACT:
2537 case SIGN_EXTRACT:
2538 case STRICT_LOW_PART:
2539 /* ??? Assumes STRICT_LOW_PART not used on multi-word registers. */
2540 do
2541 reg = XEXP (reg, 0);
2542 while (GET_CODE (reg) == SUBREG
2543 || GET_CODE (reg) == ZERO_EXTRACT
2544 || GET_CODE (reg) == SIGN_EXTRACT
2545 || GET_CODE (reg) == STRICT_LOW_PART);
3c0cb5de 2546 if (MEM_P (reg))
402209ff
JH
2547 break;
2548 not_dead = (unsigned long) REGNO_REG_SET_P (pbi->reg_live, REGNO (reg));
2549 /* Fall through. */
b02eea61 2550
402209ff
JH
2551 case REG:
2552 regno_last = regno_first = REGNO (reg);
2553 if (regno_first < FIRST_PSEUDO_REGISTER)
66fd46b6 2554 regno_last += hard_regno_nregs[regno_first][GET_MODE (reg)] - 1;
402209ff 2555 break;
b02eea61 2556
402209ff 2557 case SUBREG:
f8cfc6aa 2558 if (REG_P (SUBREG_REG (reg)))
7a442791 2559 {
402209ff
JH
2560 enum machine_mode outer_mode = GET_MODE (reg);
2561 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (reg));
7a442791 2562
402209ff
JH
2563 /* Identify the range of registers affected. This is moderately
2564 tricky for hard registers. See alter_subreg. */
b02eea61 2565
402209ff
JH
2566 regno_last = regno_first = REGNO (SUBREG_REG (reg));
2567 if (regno_first < FIRST_PSEUDO_REGISTER)
4793dca1 2568 {
402209ff
JH
2569 regno_first += subreg_regno_offset (regno_first, inner_mode,
2570 SUBREG_BYTE (reg),
2571 outer_mode);
2572 regno_last = (regno_first
66fd46b6 2573 + hard_regno_nregs[regno_first][outer_mode] - 1);
3e28fe44 2574
402209ff
JH
2575 /* Since we've just adjusted the register number ranges, make
2576 sure REG matches. Otherwise some_was_live will be clear
2577 when it shouldn't have been, and we'll create incorrect
2578 REG_UNUSED notes. */
2579 reg = gen_rtx_REG (outer_mode, regno_first);
62828c00 2580 }
402209ff 2581 else
d3a923ee 2582 {
402209ff
JH
2583 /* If the number of words in the subreg is less than the number
2584 of words in the full register, we have a well-defined partial
2585 set. Otherwise the high bits are undefined.
d3a923ee 2586
402209ff
JH
2587 This is only really applicable to pseudos, since we just took
2588 care of multi-word hard registers. */
2589 if (((GET_MODE_SIZE (outer_mode)
2590 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
2591 < ((GET_MODE_SIZE (inner_mode)
2592 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
2593 not_dead = (unsigned long) REGNO_REG_SET_P (pbi->reg_live,
2594 regno_first);
d3a923ee 2595
402209ff 2596 reg = SUBREG_REG (reg);
d3a923ee 2597 }
d3a923ee 2598 }
402209ff
JH
2599 else
2600 reg = SUBREG_REG (reg);
2601 break;
c586192c 2602
402209ff
JH
2603 default:
2604 break;
c586192c 2605 }
c586192c 2606
402209ff
JH
2607 /* If this set is a MEM, then it kills any aliased writes.
2608 If this set is a REG, then it kills any MEMs which use the reg. */
5149f070 2609 if (optimize && (flags & PROP_SCAN_DEAD_STORES))
e881bb1b 2610 {
f8cfc6aa 2611 if (REG_P (reg))
402209ff 2612 invalidate_mems_from_set (pbi, reg);
e881bb1b 2613
402209ff
JH
2614 /* If the memory reference had embedded side effects (autoincrement
2615 address modes. Then we may need to kill some entries on the
2616 memory set list. */
3c0cb5de 2617 if (insn && MEM_P (reg))
fe4b3c79 2618 for_each_rtx (&PATTERN (insn), invalidate_mems_from_autoinc, pbi);
ccbaf064 2619
3c0cb5de 2620 if (MEM_P (reg) && ! side_effects_p (reg)
402209ff 2621 /* ??? With more effort we could track conditional memory life. */
fe4b3c79 2622 && ! cond)
dd3f0101 2623 add_to_mem_set_list (pbi, canon_rtx (reg));
ccbaf064 2624 }
f2a1bc02 2625
f8cfc6aa 2626 if (REG_P (reg)
402209ff
JH
2627 && ! (regno_first == FRAME_POINTER_REGNUM
2628 && (! reload_completed || frame_pointer_needed))
2629#if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
2630 && ! (regno_first == HARD_FRAME_POINTER_REGNUM
2631 && (! reload_completed || frame_pointer_needed))
2632#endif
2633#if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
2634 && ! (regno_first == ARG_POINTER_REGNUM && fixed_regs[regno_first])
2635#endif
2636 )
f2a1bc02 2637 {
402209ff 2638 int some_was_live = 0, some_was_dead = 0;
f2a1bc02 2639
402209ff 2640 for (i = regno_first; i <= regno_last; ++i)
f2a1bc02 2641 {
402209ff
JH
2642 int needed_regno = REGNO_REG_SET_P (pbi->reg_live, i);
2643 if (pbi->local_set)
f2a1bc02 2644 {
402209ff
JH
2645 /* Order of the set operation matters here since both
2646 sets may be the same. */
2647 CLEAR_REGNO_REG_SET (pbi->cond_local_set, i);
2648 if (cond != NULL_RTX
2649 && ! REGNO_REG_SET_P (pbi->local_set, i))
2650 SET_REGNO_REG_SET (pbi->cond_local_set, i);
2651 else
2652 SET_REGNO_REG_SET (pbi->local_set, i);
f2a1bc02 2653 }
402209ff
JH
2654 if (code != CLOBBER)
2655 SET_REGNO_REG_SET (pbi->new_set, i);
d3a923ee 2656
402209ff
JH
2657 some_was_live |= needed_regno;
2658 some_was_dead |= ! needed_regno;
f2a1bc02 2659 }
402209ff
JH
2660
2661#ifdef HAVE_conditional_execution
2662 /* Consider conditional death in deciding that the register needs
2663 a death note. */
2664 if (some_was_live && ! not_dead
2665 /* The stack pointer is never dead. Well, not strictly true,
2666 but it's very difficult to tell from here. Hopefully
2667 combine_stack_adjustments will fix up the most egregious
2668 errors. */
2669 && regno_first != STACK_POINTER_REGNUM)
d3a923ee 2670 {
402209ff
JH
2671 for (i = regno_first; i <= regno_last; ++i)
2672 if (! mark_regno_cond_dead (pbi, i, cond))
2673 not_dead |= ((unsigned long) 1) << (i - regno_first);
d3a923ee 2674 }
402209ff 2675#endif
6ff71a97 2676
402209ff
JH
2677 /* Additional data to record if this is the final pass. */
2678 if (flags & (PROP_LOG_LINKS | PROP_REG_INFO
2679 | PROP_DEATH_NOTES | PROP_AUTOINC))
f2a1bc02 2680 {
b3694847 2681 rtx y;
0b17ab2f 2682 int blocknum = pbi->bb->index;
402209ff
JH
2683
2684 y = NULL_RTX;
2685 if (flags & (PROP_LOG_LINKS | PROP_AUTOINC))
ca9fef16 2686 {
402209ff 2687 y = pbi->reg_next_use[regno_first];
ca9fef16 2688
402209ff
JH
2689 /* The next use is no longer next, since a store intervenes. */
2690 for (i = regno_first; i <= regno_last; ++i)
2691 pbi->reg_next_use[i] = 0;
2692 }
6e64a52a 2693
402209ff 2694 if (flags & PROP_REG_INFO)
46fac664 2695 {
402209ff
JH
2696 for (i = regno_first; i <= regno_last; ++i)
2697 {
2698 /* Count (weighted) references, stores, etc. This counts a
2699 register twice if it is modified, but that is correct. */
2700 REG_N_SETS (i) += 1;
2701 REG_N_REFS (i) += 1;
2702 REG_FREQ (i) += REG_FREQ_FROM_BB (pbi->bb);
2703
2704 /* The insns where a reg is live are normally counted
2705 elsewhere, but we want the count to include the insn
2706 where the reg is set, and the normal counting mechanism
2707 would not count it. */
2708 REG_LIVE_LENGTH (i) += 1;
2709 }
2710
2711 /* If this is a hard reg, record this function uses the reg. */
2712 if (regno_first < FIRST_PSEUDO_REGISTER)
6e64a52a 2713 {
402209ff
JH
2714 for (i = regno_first; i <= regno_last; i++)
2715 regs_ever_live[i] = 1;
df2ef49b
AM
2716 if (flags & PROP_ASM_SCAN)
2717 for (i = regno_first; i <= regno_last; i++)
2718 regs_asm_clobbered[i] = 1;
6e64a52a
JH
2719 }
2720 else
6e64a52a 2721 {
402209ff
JH
2722 /* Keep track of which basic blocks each reg appears in. */
2723 if (REG_BASIC_BLOCK (regno_first) == REG_BLOCK_UNKNOWN)
2724 REG_BASIC_BLOCK (regno_first) = blocknum;
2725 else if (REG_BASIC_BLOCK (regno_first) != blocknum)
2726 REG_BASIC_BLOCK (regno_first) = REG_BLOCK_GLOBAL;
6e64a52a 2727 }
402209ff 2728 }
f2a1bc02 2729
402209ff 2730 if (! some_was_dead)
f2a1bc02 2731 {
402209ff
JH
2732 if (flags & PROP_LOG_LINKS)
2733 {
2734 /* Make a logical link from the next following insn
2735 that uses this register, back to this insn.
2736 The following insns have already been processed.
2737
2738 We don't build a LOG_LINK for hard registers containing
2739 in ASM_OPERANDs. If these registers get replaced,
2740 we might wind up changing the semantics of the insn,
2741 even if reload can make what appear to be valid
a10016d3
ILT
2742 assignments later.
2743
2744 We don't build a LOG_LINK for global registers to
2745 or from a function call. We don't want to let
2746 combine think that it knows what is going on with
2747 global registers. */
402209ff
JH
2748 if (y && (BLOCK_NUM (y) == blocknum)
2749 && (regno_first >= FIRST_PSEUDO_REGISTER
a10016d3 2750 || (asm_noperands (PATTERN (y)) < 0
4b4bf941
JQ
2751 && ! ((CALL_P (insn)
2752 || CALL_P (y))
a10016d3 2753 && global_regs[regno_first]))))
402209ff
JH
2754 LOG_LINKS (y) = alloc_INSN_LIST (insn, LOG_LINKS (y));
2755 }
34487bf8 2756 }
402209ff
JH
2757 else if (not_dead)
2758 ;
2759 else if (! some_was_live)
2760 {
2761 if (flags & PROP_REG_INFO)
2762 REG_N_DEATHS (regno_first) += 1;
34487bf8 2763
402209ff
JH
2764 if (flags & PROP_DEATH_NOTES)
2765 {
2766 /* Note that dead stores have already been deleted
2767 when possible. If we get here, we have found a
2768 dead store that cannot be eliminated (because the
2769 same insn does something useful). Indicate this
2770 by marking the reg being set as dying here. */
2771 REG_NOTES (insn)
2772 = alloc_EXPR_LIST (REG_UNUSED, reg, REG_NOTES (insn));
2773 }
2774 }
2775 else
34487bf8 2776 {
402209ff
JH
2777 if (flags & PROP_DEATH_NOTES)
2778 {
2779 /* This is a case where we have a multi-word hard register
2780 and some, but not all, of the words of the register are
2781 needed in subsequent insns. Write REG_UNUSED notes
2782 for those parts that were not needed. This case should
2783 be rare. */
2784
2785 for (i = regno_first; i <= regno_last; ++i)
2786 if (! REGNO_REG_SET_P (pbi->reg_live, i))
2787 REG_NOTES (insn)
2788 = alloc_EXPR_LIST (REG_UNUSED,
e50126e8 2789 regno_reg_rtx[i],
402209ff
JH
2790 REG_NOTES (insn));
2791 }
34487bf8 2792 }
34487bf8 2793 }
402209ff
JH
2794
2795 /* Mark the register as being dead. */
2796 if (some_was_live
2797 /* The stack pointer is never dead. Well, not strictly true,
2798 but it's very difficult to tell from here. Hopefully
2799 combine_stack_adjustments will fix up the most egregious
2800 errors. */
2801 && regno_first != STACK_POINTER_REGNUM)
34487bf8 2802 {
402209ff
JH
2803 for (i = regno_first; i <= regno_last; ++i)
2804 if (!(not_dead & (((unsigned long) 1) << (i - regno_first))))
736b64dd
JH
2805 {
2806 if ((pbi->flags & PROP_REG_INFO)
2807 && REGNO_REG_SET_P (pbi->reg_live, i))
2808 {
2809 REG_LIVE_LENGTH (i) += pbi->insn_num - reg_deaths[i];
2810 reg_deaths[i] = 0;
2811 }
2812 CLEAR_REGNO_REG_SET (pbi->reg_live, i);
2813 }
34487bf8 2814 }
402209ff 2815 }
f8cfc6aa 2816 else if (REG_P (reg))
402209ff
JH
2817 {
2818 if (flags & (PROP_LOG_LINKS | PROP_AUTOINC))
2819 pbi->reg_next_use[regno_first] = 0;
df2ef49b
AM
2820
2821 if ((flags & PROP_REG_INFO) != 0
2822 && (flags & PROP_ASM_SCAN) != 0
2823 && regno_first < FIRST_PSEUDO_REGISTER)
2824 {
2825 for (i = regno_first; i <= regno_last; i++)
2826 regs_asm_clobbered[i] = 1;
2827 }
402209ff
JH
2828 }
2829
2830 /* If this is the last pass and this is a SCRATCH, show it will be dying
2831 here and count it. */
2832 else if (GET_CODE (reg) == SCRATCH)
2833 {
2834 if (flags & PROP_DEATH_NOTES)
2835 REG_NOTES (insn)
2836 = alloc_EXPR_LIST (REG_UNUSED, reg, REG_NOTES (insn));
2837 }
2838}
2839\f
2840#ifdef HAVE_conditional_execution
2841/* Mark REGNO conditionally dead.
2842 Return true if the register is now unconditionally dead. */
2843
2844static int
6cf9ac28 2845mark_regno_cond_dead (struct propagate_block_info *pbi, int regno, rtx cond)
402209ff
JH
2846{
2847 /* If this is a store to a predicate register, the value of the
2848 predicate is changing, we don't know that the predicate as seen
2849 before is the same as that seen after. Flush all dependent
2850 conditions from reg_cond_dead. This will make all such
2851 conditionally live registers unconditionally live. */
2852 if (REGNO_REG_SET_P (pbi->reg_cond_reg, regno))
2853 flush_reg_cond_reg (pbi, regno);
2854
2855 /* If this is an unconditional store, remove any conditional
2856 life that may have existed. */
2857 if (cond == NULL_RTX)
2858 splay_tree_remove (pbi->reg_cond_dead, regno);
2859 else
2860 {
2861 splay_tree_node node;
2862 struct reg_cond_life_info *rcli;
2863 rtx ncond;
2864
2865 /* Otherwise this is a conditional set. Record that fact.
2866 It may have been conditionally used, or there may be a
2867 subsequent set with a complimentary condition. */
34487bf8 2868
402209ff
JH
2869 node = splay_tree_lookup (pbi->reg_cond_dead, regno);
2870 if (node == NULL)
34487bf8 2871 {
402209ff
JH
2872 /* The register was unconditionally live previously.
2873 Record the current condition as the condition under
2874 which it is dead. */
703ad42b 2875 rcli = xmalloc (sizeof (*rcli));
402209ff
JH
2876 rcli->condition = cond;
2877 rcli->stores = cond;
2878 rcli->orig_condition = const0_rtx;
2879 splay_tree_insert (pbi->reg_cond_dead, regno,
2880 (splay_tree_value) rcli);
2881
2882 SET_REGNO_REG_SET (pbi->reg_cond_reg, REGNO (XEXP (cond, 0)));
2883
d6a7951f 2884 /* Not unconditionally dead. */
402209ff 2885 return 0;
34487bf8
RH
2886 }
2887 else
2888 {
402209ff
JH
2889 /* The register was conditionally live previously.
2890 Add the new condition to the old. */
2891 rcli = (struct reg_cond_life_info *) node->value;
2892 ncond = rcli->condition;
2893 ncond = ior_reg_cond (ncond, cond, 1);
2894 if (rcli->stores == const0_rtx)
2895 rcli->stores = cond;
2896 else if (rcli->stores != const1_rtx)
2897 rcli->stores = ior_reg_cond (rcli->stores, cond, 1);
34487bf8 2898
402209ff
JH
2899 /* If the register is now unconditionally dead, remove the entry
2900 in the splay_tree. A register is unconditionally dead if the
2901 dead condition ncond is true. A register is also unconditionally
2902 dead if the sum of all conditional stores is an unconditional
2903 store (stores is true), and the dead condition is identically the
2904 same as the original dead condition initialized at the end of
2905 the block. This is a pointer compare, not an rtx_equal_p
2906 compare. */
2907 if (ncond == const1_rtx
2908 || (ncond == rcli->orig_condition && rcli->stores == const1_rtx))
2909 splay_tree_remove (pbi->reg_cond_dead, regno);
2910 else
2911 {
2912 rcli->condition = ncond;
34487bf8 2913
402209ff 2914 SET_REGNO_REG_SET (pbi->reg_cond_reg, REGNO (XEXP (cond, 0)));
34487bf8 2915
d6a7951f 2916 /* Not unconditionally dead. */
402209ff 2917 return 0;
34487bf8
RH
2918 }
2919 }
2920 }
2921
402209ff
JH
2922 return 1;
2923}
bce7bfe8 2924
402209ff 2925/* Called from splay_tree_delete for pbi->reg_cond_life. */
b9f22704 2926
402209ff 2927static void
6cf9ac28 2928free_reg_cond_life_info (splay_tree_value value)
402209ff
JH
2929{
2930 struct reg_cond_life_info *rcli = (struct reg_cond_life_info *) value;
2931 free (rcli);
2932}
18ca529b 2933
402209ff 2934/* Helper function for flush_reg_cond_reg. */
34487bf8 2935
402209ff 2936static int
6cf9ac28 2937flush_reg_cond_reg_1 (splay_tree_node node, void *data)
402209ff
JH
2938{
2939 struct reg_cond_life_info *rcli;
2940 int *xdata = (int *) data;
2941 unsigned int regno = xdata[0];
34487bf8 2942
402209ff
JH
2943 /* Don't need to search if last flushed value was farther on in
2944 the in-order traversal. */
2945 if (xdata[1] >= (int) node->key)
2946 return 0;
34487bf8 2947
402209ff
JH
2948 /* Splice out portions of the expression that refer to regno. */
2949 rcli = (struct reg_cond_life_info *) node->value;
2950 rcli->condition = elim_reg_cond (rcli->condition, regno);
2951 if (rcli->stores != const0_rtx && rcli->stores != const1_rtx)
2952 rcli->stores = elim_reg_cond (rcli->stores, regno);
0edd203b 2953
402209ff
JH
2954 /* If the entire condition is now false, signal the node to be removed. */
2955 if (rcli->condition == const0_rtx)
2956 {
2957 xdata[1] = node->key;
2958 return -1;
34487bf8 2959 }
402209ff
JH
2960 else if (rcli->condition == const1_rtx)
2961 abort ();
d3a923ee 2962
402209ff 2963 return 0;
34487bf8 2964}
410538ea 2965
402209ff 2966/* Flush all (sub) expressions referring to REGNO from REG_COND_LIVE. */
410538ea 2967
402209ff 2968static void
6cf9ac28 2969flush_reg_cond_reg (struct propagate_block_info *pbi, int regno)
402209ff
JH
2970{
2971 int pair[2];
410538ea 2972
402209ff
JH
2973 pair[0] = regno;
2974 pair[1] = -1;
2975 while (splay_tree_foreach (pbi->reg_cond_dead,
2976 flush_reg_cond_reg_1, pair) == -1)
2977 splay_tree_remove (pbi->reg_cond_dead, pair[1]);
410538ea 2978
402209ff
JH
2979 CLEAR_REGNO_REG_SET (pbi->reg_cond_reg, regno);
2980}
410538ea 2981
402209ff
JH
2982/* Logical arithmetic on predicate conditions. IOR, NOT and AND.
2983 For ior/and, the ADD flag determines whether we want to add the new
2984 condition X to the old one unconditionally. If it is zero, we will
2985 only return a new expression if X allows us to simplify part of
b318748f 2986 OLD, otherwise we return NULL to the caller.
402209ff
JH
2987 If ADD is nonzero, we will return a new condition in all cases. The
2988 toplevel caller of one of these functions should always pass 1 for
2989 ADD. */
410538ea 2990
402209ff 2991static rtx
6cf9ac28 2992ior_reg_cond (rtx old, rtx x, int add)
402209ff
JH
2993{
2994 rtx op0, op1;
410538ea 2995
ec8e098d 2996 if (COMPARISON_P (old))
410538ea 2997 {
33e6a97a 2998 if (COMPARISON_P (x)
402209ff
JH
2999 && REVERSE_CONDEXEC_PREDICATES_P (GET_CODE (x), GET_CODE (old))
3000 && REGNO (XEXP (x, 0)) == REGNO (XEXP (old, 0)))
3001 return const1_rtx;
3002 if (GET_CODE (x) == GET_CODE (old)
3003 && REGNO (XEXP (x, 0)) == REGNO (XEXP (old, 0)))
3004 return old;
3005 if (! add)
b318748f 3006 return NULL;
402209ff 3007 return gen_rtx_IOR (0, old, x);
410538ea 3008 }
c9bacfdb 3009
402209ff 3010 switch (GET_CODE (old))
410538ea 3011 {
402209ff
JH
3012 case IOR:
3013 op0 = ior_reg_cond (XEXP (old, 0), x, 0);
3014 op1 = ior_reg_cond (XEXP (old, 1), x, 0);
b318748f 3015 if (op0 != NULL || op1 != NULL)
402209ff
JH
3016 {
3017 if (op0 == const0_rtx)
b318748f 3018 return op1 ? op1 : gen_rtx_IOR (0, XEXP (old, 1), x);
402209ff 3019 if (op1 == const0_rtx)
b318748f 3020 return op0 ? op0 : gen_rtx_IOR (0, XEXP (old, 0), x);
402209ff
JH
3021 if (op0 == const1_rtx || op1 == const1_rtx)
3022 return const1_rtx;
b318748f
JJ
3023 if (op0 == NULL)
3024 op0 = gen_rtx_IOR (0, XEXP (old, 0), x);
3025 else if (rtx_equal_p (x, op0))
3026 /* (x | A) | x ~ (x | A). */
3027 return old;
3028 if (op1 == NULL)
3029 op1 = gen_rtx_IOR (0, XEXP (old, 1), x);
3030 else if (rtx_equal_p (x, op1))
3031 /* (A | x) | x ~ (A | x). */
3032 return old;
402209ff
JH
3033 return gen_rtx_IOR (0, op0, op1);
3034 }
3035 if (! add)
b318748f 3036 return NULL;
402209ff 3037 return gen_rtx_IOR (0, old, x);
410538ea 3038
402209ff
JH
3039 case AND:
3040 op0 = ior_reg_cond (XEXP (old, 0), x, 0);
3041 op1 = ior_reg_cond (XEXP (old, 1), x, 0);
b318748f 3042 if (op0 != NULL || op1 != NULL)
410538ea 3043 {
402209ff 3044 if (op0 == const1_rtx)
b318748f 3045 return op1 ? op1 : gen_rtx_IOR (0, XEXP (old, 1), x);
402209ff 3046 if (op1 == const1_rtx)
b318748f 3047 return op0 ? op0 : gen_rtx_IOR (0, XEXP (old, 0), x);
402209ff
JH
3048 if (op0 == const0_rtx || op1 == const0_rtx)
3049 return const0_rtx;
b318748f
JJ
3050 if (op0 == NULL)
3051 op0 = gen_rtx_IOR (0, XEXP (old, 0), x);
3052 else if (rtx_equal_p (x, op0))
3053 /* (x & A) | x ~ x. */
3054 return op0;
3055 if (op1 == NULL)
3056 op1 = gen_rtx_IOR (0, XEXP (old, 1), x);
3057 else if (rtx_equal_p (x, op1))
3058 /* (A & x) | x ~ x. */
3059 return op1;
402209ff 3060 return gen_rtx_AND (0, op0, op1);
410538ea 3061 }
402209ff 3062 if (! add)
b318748f 3063 return NULL;
402209ff 3064 return gen_rtx_IOR (0, old, x);
410538ea 3065
402209ff
JH
3066 case NOT:
3067 op0 = and_reg_cond (XEXP (old, 0), not_reg_cond (x), 0);
b318748f 3068 if (op0 != NULL)
402209ff
JH
3069 return not_reg_cond (op0);
3070 if (! add)
b318748f 3071 return NULL;
402209ff 3072 return gen_rtx_IOR (0, old, x);
c9bacfdb 3073
402209ff
JH
3074 default:
3075 abort ();
410538ea
AM
3076 }
3077}
3078
402209ff 3079static rtx
6cf9ac28 3080not_reg_cond (rtx x)
410538ea 3081{
402209ff 3082 enum rtx_code x_code;
410538ea 3083
402209ff
JH
3084 if (x == const0_rtx)
3085 return const1_rtx;
3086 else if (x == const1_rtx)
3087 return const0_rtx;
3088 x_code = GET_CODE (x);
3089 if (x_code == NOT)
3090 return XEXP (x, 0);
ec8e098d 3091 if (COMPARISON_P (x)
f8cfc6aa 3092 && REG_P (XEXP (x, 0)))
410538ea 3093 {
402209ff
JH
3094 if (XEXP (x, 1) != const0_rtx)
3095 abort ();
410538ea 3096
402209ff
JH
3097 return gen_rtx_fmt_ee (reverse_condition (x_code),
3098 VOIDmode, XEXP (x, 0), const0_rtx);
410538ea 3099 }
402209ff 3100 return gen_rtx_NOT (0, x);
410538ea
AM
3101}
3102
402209ff 3103static rtx
6cf9ac28 3104and_reg_cond (rtx old, rtx x, int add)
410538ea 3105{
402209ff 3106 rtx op0, op1;
410538ea 3107
ec8e098d 3108 if (COMPARISON_P (old))
410538ea 3109 {
33e6a97a 3110 if (COMPARISON_P (x)
402209ff
JH
3111 && GET_CODE (x) == reverse_condition (GET_CODE (old))
3112 && REGNO (XEXP (x, 0)) == REGNO (XEXP (old, 0)))
3113 return const0_rtx;
3114 if (GET_CODE (x) == GET_CODE (old)
3115 && REGNO (XEXP (x, 0)) == REGNO (XEXP (old, 0)))
3116 return old;
3117 if (! add)
b318748f 3118 return NULL;
402209ff
JH
3119 return gen_rtx_AND (0, old, x);
3120 }
410538ea 3121
402209ff
JH
3122 switch (GET_CODE (old))
3123 {
3124 case IOR:
3125 op0 = and_reg_cond (XEXP (old, 0), x, 0);
3126 op1 = and_reg_cond (XEXP (old, 1), x, 0);
b318748f 3127 if (op0 != NULL || op1 != NULL)
410538ea 3128 {
402209ff 3129 if (op0 == const0_rtx)
b318748f 3130 return op1 ? op1 : gen_rtx_AND (0, XEXP (old, 1), x);
402209ff 3131 if (op1 == const0_rtx)
b318748f 3132 return op0 ? op0 : gen_rtx_AND (0, XEXP (old, 0), x);
402209ff
JH
3133 if (op0 == const1_rtx || op1 == const1_rtx)
3134 return const1_rtx;
b318748f
JJ
3135 if (op0 == NULL)
3136 op0 = gen_rtx_AND (0, XEXP (old, 0), x);
3137 else if (rtx_equal_p (x, op0))
3138 /* (x | A) & x ~ x. */
3139 return op0;
3140 if (op1 == NULL)
3141 op1 = gen_rtx_AND (0, XEXP (old, 1), x);
3142 else if (rtx_equal_p (x, op1))
3143 /* (A | x) & x ~ x. */
3144 return op1;
402209ff 3145 return gen_rtx_IOR (0, op0, op1);
410538ea 3146 }
402209ff 3147 if (! add)
b318748f 3148 return NULL;
402209ff
JH
3149 return gen_rtx_AND (0, old, x);
3150
3151 case AND:
3152 op0 = and_reg_cond (XEXP (old, 0), x, 0);
3153 op1 = and_reg_cond (XEXP (old, 1), x, 0);
b318748f 3154 if (op0 != NULL || op1 != NULL)
410538ea 3155 {
402209ff 3156 if (op0 == const1_rtx)
b318748f 3157 return op1 ? op1 : gen_rtx_AND (0, XEXP (old, 1), x);
402209ff 3158 if (op1 == const1_rtx)
b318748f 3159 return op0 ? op0 : gen_rtx_AND (0, XEXP (old, 0), x);
402209ff
JH
3160 if (op0 == const0_rtx || op1 == const0_rtx)
3161 return const0_rtx;
b318748f
JJ
3162 if (op0 == NULL)
3163 op0 = gen_rtx_AND (0, XEXP (old, 0), x);
3164 else if (rtx_equal_p (x, op0))
3165 /* (x & A) & x ~ (x & A). */
3166 return old;
3167 if (op1 == NULL)
3168 op1 = gen_rtx_AND (0, XEXP (old, 1), x);
3169 else if (rtx_equal_p (x, op1))
3170 /* (A & x) & x ~ (A & x). */
3171 return old;
402209ff 3172 return gen_rtx_AND (0, op0, op1);
410538ea 3173 }
402209ff 3174 if (! add)
b318748f 3175 return NULL;
402209ff 3176 return gen_rtx_AND (0, old, x);
410538ea 3177
402209ff
JH
3178 case NOT:
3179 op0 = ior_reg_cond (XEXP (old, 0), not_reg_cond (x), 0);
b318748f 3180 if (op0 != NULL)
402209ff
JH
3181 return not_reg_cond (op0);
3182 if (! add)
b318748f 3183 return NULL;
402209ff 3184 return gen_rtx_AND (0, old, x);
410538ea 3185
402209ff
JH
3186 default:
3187 abort ();
c9bacfdb 3188 }
410538ea
AM
3189}
3190
402209ff
JH
3191/* Given a condition X, remove references to reg REGNO and return the
3192 new condition. The removal will be done so that all conditions
3193 involving REGNO are considered to evaluate to false. This function
3194 is used when the value of REGNO changes. */
c9bacfdb 3195
402209ff 3196static rtx
6cf9ac28 3197elim_reg_cond (rtx x, unsigned int regno)
410538ea 3198{
402209ff
JH
3199 rtx op0, op1;
3200
ec8e098d 3201 if (COMPARISON_P (x))
410538ea 3202 {
402209ff
JH
3203 if (REGNO (XEXP (x, 0)) == regno)
3204 return const0_rtx;
3205 return x;
410538ea 3206 }
c9bacfdb 3207
402209ff
JH
3208 switch (GET_CODE (x))
3209 {
3210 case AND:
3211 op0 = elim_reg_cond (XEXP (x, 0), regno);
3212 op1 = elim_reg_cond (XEXP (x, 1), regno);
3213 if (op0 == const0_rtx || op1 == const0_rtx)
3214 return const0_rtx;
3215 if (op0 == const1_rtx)
3216 return op1;
3217 if (op1 == const1_rtx)
3218 return op0;
3219 if (op0 == XEXP (x, 0) && op1 == XEXP (x, 1))
3220 return x;
3221 return gen_rtx_AND (0, op0, op1);
87fdf7ff 3222
402209ff
JH
3223 case IOR:
3224 op0 = elim_reg_cond (XEXP (x, 0), regno);
3225 op1 = elim_reg_cond (XEXP (x, 1), regno);
3226 if (op0 == const1_rtx || op1 == const1_rtx)
3227 return const1_rtx;
3228 if (op0 == const0_rtx)
3229 return op1;
3230 if (op1 == const0_rtx)
3231 return op0;
3232 if (op0 == XEXP (x, 0) && op1 == XEXP (x, 1))
3233 return x;
3234 return gen_rtx_IOR (0, op0, op1);
87fdf7ff 3235
402209ff
JH
3236 case NOT:
3237 op0 = elim_reg_cond (XEXP (x, 0), regno);
3238 if (op0 == const0_rtx)
3239 return const1_rtx;
3240 if (op0 == const1_rtx)
3241 return const0_rtx;
3242 if (op0 != XEXP (x, 0))
3243 return not_reg_cond (op0);
3244 return x;
87fdf7ff 3245
402209ff
JH
3246 default:
3247 abort ();
3248 }
87fdf7ff 3249}
402209ff
JH
3250#endif /* HAVE_conditional_execution */
3251\f
3252#ifdef AUTO_INC_DEC
87fdf7ff 3253
402209ff
JH
3254/* Try to substitute the auto-inc expression INC as the address inside
3255 MEM which occurs in INSN. Currently, the address of MEM is an expression
3256 involving INCR_REG, and INCR is the next use of INCR_REG; it is an insn
3257 that has a single set whose source is a PLUS of INCR_REG and something
3258 else. */
c9bacfdb 3259
87fdf7ff 3260static void
6cf9ac28
AJ
3261attempt_auto_inc (struct propagate_block_info *pbi, rtx inc, rtx insn,
3262 rtx mem, rtx incr, rtx incr_reg)
87fdf7ff 3263{
402209ff
JH
3264 int regno = REGNO (incr_reg);
3265 rtx set = single_set (incr);
3266 rtx q = SET_DEST (set);
3267 rtx y = SET_SRC (set);
3268 int opnum = XEXP (y, 0) == incr_reg ? 0 : 1;
c9bacfdb 3269
402209ff
JH
3270 /* Make sure this reg appears only once in this insn. */
3271 if (count_occurrences (PATTERN (insn), incr_reg, 1) != 1)
3272 return;
87fdf7ff 3273
402209ff
JH
3274 if (dead_or_set_p (incr, incr_reg)
3275 /* Mustn't autoinc an eliminable register. */
3276 && (regno >= FIRST_PSEUDO_REGISTER
3277 || ! TEST_HARD_REG_BIT (elim_reg_set, regno)))
3278 {
3279 /* This is the simple case. Try to make the auto-inc. If
3280 we can't, we are done. Otherwise, we will do any
3281 needed updates below. */
3282 if (! validate_change (insn, &XEXP (mem, 0), inc, 0))
3283 return;
3284 }
f8cfc6aa 3285 else if (REG_P (q)
402209ff
JH
3286 /* PREV_INSN used here to check the semi-open interval
3287 [insn,incr). */
3288 && ! reg_used_between_p (q, PREV_INSN (insn), incr)
3289 /* We must also check for sets of q as q may be
3290 a call clobbered hard register and there may
3291 be a call between PREV_INSN (insn) and incr. */
3292 && ! reg_set_between_p (q, PREV_INSN (insn), incr))
3293 {
3294 /* We have *p followed sometime later by q = p+size.
3295 Both p and q must be live afterward,
3296 and q is not used between INSN and its assignment.
3297 Change it to q = p, ...*q..., q = q+size.
3298 Then fall into the usual case. */
3299 rtx insns, temp;
d3a923ee 3300
402209ff
JH
3301 start_sequence ();
3302 emit_move_insn (q, incr_reg);
3303 insns = get_insns ();
3304 end_sequence ();
87fdf7ff 3305
402209ff
JH
3306 /* If we can't make the auto-inc, or can't make the
3307 replacement into Y, exit. There's no point in making
3308 the change below if we can't do the auto-inc and doing
3309 so is not correct in the pre-inc case. */
87fdf7ff 3310
402209ff
JH
3311 XEXP (inc, 0) = q;
3312 validate_change (insn, &XEXP (mem, 0), inc, 1);
3313 validate_change (incr, &XEXP (y, opnum), q, 1);
3314 if (! apply_change_group ())
3315 return;
f008a564 3316
402209ff
JH
3317 /* We now know we'll be doing this change, so emit the
3318 new insn(s) and do the updates. */
2f937369 3319 emit_insn_before (insns, insn);
f008a564 3320
a813c111
SB
3321 if (BB_HEAD (pbi->bb) == insn)
3322 BB_HEAD (pbi->bb) = insns;
b53978a3 3323
402209ff
JH
3324 /* INCR will become a NOTE and INSN won't contain a
3325 use of INCR_REG. If a use of INCR_REG was just placed in
3326 the insn before INSN, make that the next use.
3327 Otherwise, invalidate it. */
4b4bf941 3328 if (NONJUMP_INSN_P (PREV_INSN (insn))
402209ff
JH
3329 && GET_CODE (PATTERN (PREV_INSN (insn))) == SET
3330 && SET_SRC (PATTERN (PREV_INSN (insn))) == incr_reg)
3331 pbi->reg_next_use[regno] = PREV_INSN (insn);
3332 else
3333 pbi->reg_next_use[regno] = 0;
c9bacfdb 3334
402209ff
JH
3335 incr_reg = q;
3336 regno = REGNO (q);
b53978a3 3337
298c28a8
JH
3338 if ((pbi->flags & PROP_REG_INFO)
3339 && !REGNO_REG_SET_P (pbi->reg_live, regno))
3340 reg_deaths[regno] = pbi->insn_num;
3341
402209ff
JH
3342 /* REGNO is now used in INCR which is below INSN, but
3343 it previously wasn't live here. If we don't mark
3344 it as live, we'll put a REG_DEAD note for it
3345 on this insn, which is incorrect. */
3346 SET_REGNO_REG_SET (pbi->reg_live, regno);
b53978a3 3347
402209ff
JH
3348 /* If there are any calls between INSN and INCR, show
3349 that REGNO now crosses them. */
3350 for (temp = insn; temp != incr; temp = NEXT_INSN (temp))
4b4bf941 3351 if (CALL_P (temp))
402209ff 3352 REG_N_CALLS_CROSSED (regno)++;
c9bacfdb 3353
402209ff
JH
3354 /* Invalidate alias info for Q since we just changed its value. */
3355 clear_reg_alias_info (q);
b53978a3 3356 }
402209ff
JH
3357 else
3358 return;
b53978a3 3359
402209ff
JH
3360 /* If we haven't returned, it means we were able to make the
3361 auto-inc, so update the status. First, record that this insn
3362 has an implicit side effect. */
f008a564 3363
402209ff 3364 REG_NOTES (insn) = alloc_EXPR_LIST (REG_INC, incr_reg, REG_NOTES (insn));
f008a564 3365
402209ff
JH
3366 /* Modify the old increment-insn to simply copy
3367 the already-incremented value of our register. */
3368 if (! validate_change (incr, &SET_SRC (set), incr_reg, 0))
3369 abort ();
ca9fef16 3370
402209ff
JH
3371 /* If that makes it a no-op (copying the register into itself) delete
3372 it so it won't appear to be a "use" and a "set" of this
3373 register. */
3374 if (REGNO (SET_DEST (set)) == REGNO (incr_reg))
ca9fef16 3375 {
402209ff
JH
3376 /* If the original source was dead, it's dead now. */
3377 rtx note;
ca9fef16 3378
402209ff
JH
3379 while ((note = find_reg_note (incr, REG_DEAD, NULL_RTX)) != NULL_RTX)
3380 {
3381 remove_note (incr, note);
3382 if (XEXP (note, 0) != incr_reg)
298c28a8
JH
3383 {
3384 unsigned int regno = REGNO (XEXP (note, 0));
3385
3386 if ((pbi->flags & PROP_REG_INFO)
3387 && REGNO_REG_SET_P (pbi->reg_live, regno))
3388 {
3389 REG_LIVE_LENGTH (regno) += pbi->insn_num - reg_deaths[regno];
3390 reg_deaths[regno] = 0;
3391 }
3392 CLEAR_REGNO_REG_SET (pbi->reg_live, REGNO (XEXP (note, 0)));
3393 }
402209ff 3394 }
c9bacfdb 3395
6773e15f 3396 SET_INSN_DELETED (incr);
402209ff 3397 }
f008a564 3398
402209ff
JH
3399 if (regno >= FIRST_PSEUDO_REGISTER)
3400 {
3401 /* Count an extra reference to the reg. When a reg is
3402 incremented, spilling it is worse, so we want to make
3403 that less likely. */
3404 REG_FREQ (regno) += REG_FREQ_FROM_BB (pbi->bb);
f008a564 3405
402209ff
JH
3406 /* Count the increment as a setting of the register,
3407 even though it isn't a SET in rtl. */
3408 REG_N_SETS (regno)++;
3409 }
f008a564 3410}
402209ff
JH
3411
3412/* X is a MEM found in INSN. See if we can convert it into an auto-increment
3413 reference. */
c9bacfdb 3414
21c7361e 3415static void
6cf9ac28 3416find_auto_inc (struct propagate_block_info *pbi, rtx x, rtx insn)
4dc9341c 3417{
402209ff
JH
3418 rtx addr = XEXP (x, 0);
3419 HOST_WIDE_INT offset = 0;
3420 rtx set, y, incr, inc_val;
3421 int regno;
3422 int size = GET_MODE_SIZE (GET_MODE (x));
4dc9341c 3423
4b4bf941 3424 if (JUMP_P (insn))
135ebc36
MH
3425 return;
3426
402209ff
JH
3427 /* Here we detect use of an index register which might be good for
3428 postincrement, postdecrement, preincrement, or predecrement. */
3429
3430 if (GET_CODE (addr) == PLUS && GET_CODE (XEXP (addr, 1)) == CONST_INT)
3431 offset = INTVAL (XEXP (addr, 1)), addr = XEXP (addr, 0);
4dc9341c 3432
f8cfc6aa 3433 if (!REG_P (addr))
402209ff 3434 return;
c9bacfdb 3435
402209ff 3436 regno = REGNO (addr);
135ebc36 3437
402209ff
JH
3438 /* Is the next use an increment that might make auto-increment? */
3439 incr = pbi->reg_next_use[regno];
3440 if (incr == 0 || BLOCK_NUM (incr) != BLOCK_NUM (insn))
3441 return;
3442 set = single_set (incr);
3443 if (set == 0 || GET_CODE (set) != SET)
3444 return;
3445 y = SET_SRC (set);
4dc9341c 3446
402209ff 3447 if (GET_CODE (y) != PLUS)
135ebc36
MH
3448 return;
3449
402209ff
JH
3450 if (REG_P (XEXP (y, 0)) && REGNO (XEXP (y, 0)) == REGNO (addr))
3451 inc_val = XEXP (y, 1);
3452 else if (REG_P (XEXP (y, 1)) && REGNO (XEXP (y, 1)) == REGNO (addr))
3453 inc_val = XEXP (y, 0);
3454 else
3455 return;
4dc9341c 3456
402209ff
JH
3457 if (GET_CODE (inc_val) == CONST_INT)
3458 {
3459 if (HAVE_POST_INCREMENT
3460 && (INTVAL (inc_val) == size && offset == 0))
3461 attempt_auto_inc (pbi, gen_rtx_POST_INC (Pmode, addr), insn, x,
3462 incr, addr);
3463 else if (HAVE_POST_DECREMENT
3464 && (INTVAL (inc_val) == -size && offset == 0))
3465 attempt_auto_inc (pbi, gen_rtx_POST_DEC (Pmode, addr), insn, x,
3466 incr, addr);
3467 else if (HAVE_PRE_INCREMENT
3468 && (INTVAL (inc_val) == size && offset == size))
3469 attempt_auto_inc (pbi, gen_rtx_PRE_INC (Pmode, addr), insn, x,
3470 incr, addr);
3471 else if (HAVE_PRE_DECREMENT
3472 && (INTVAL (inc_val) == -size && offset == -size))
3473 attempt_auto_inc (pbi, gen_rtx_PRE_DEC (Pmode, addr), insn, x,
3474 incr, addr);
3475 else if (HAVE_POST_MODIFY_DISP && offset == 0)
3476 attempt_auto_inc (pbi, gen_rtx_POST_MODIFY (Pmode, addr,
3477 gen_rtx_PLUS (Pmode,
3478 addr,
3479 inc_val)),
3480 insn, x, incr, addr);
89c4b810
RE
3481 else if (HAVE_PRE_MODIFY_DISP && offset == INTVAL (inc_val))
3482 attempt_auto_inc (pbi, gen_rtx_PRE_MODIFY (Pmode, addr,
3483 gen_rtx_PLUS (Pmode,
3484 addr,
3485 inc_val)),
3486 insn, x, incr, addr);
402209ff 3487 }
f8cfc6aa 3488 else if (REG_P (inc_val)
402209ff
JH
3489 && ! reg_set_between_p (inc_val, PREV_INSN (insn),
3490 NEXT_INSN (incr)))
135ebc36 3491
402209ff
JH
3492 {
3493 if (HAVE_POST_MODIFY_REG && offset == 0)
3494 attempt_auto_inc (pbi, gen_rtx_POST_MODIFY (Pmode, addr,
3495 gen_rtx_PLUS (Pmode,
3496 addr,
3497 inc_val)),
3498 insn, x, incr, addr);
3499 }
3500}
c9bacfdb 3501
402209ff
JH
3502#endif /* AUTO_INC_DEC */
3503\f
4dc9341c 3504static void
6cf9ac28
AJ
3505mark_used_reg (struct propagate_block_info *pbi, rtx reg,
3506 rtx cond ATTRIBUTE_UNUSED, rtx insn)
4dc9341c 3507{
402209ff
JH
3508 unsigned int regno_first, regno_last, i;
3509 int some_was_live, some_was_dead, some_not_set;
4dc9341c 3510
402209ff
JH
3511 regno_last = regno_first = REGNO (reg);
3512 if (regno_first < FIRST_PSEUDO_REGISTER)
66fd46b6 3513 regno_last += hard_regno_nregs[regno_first][GET_MODE (reg)] - 1;
4dc9341c 3514
402209ff
JH
3515 /* Find out if any of this register is live after this instruction. */
3516 some_was_live = some_was_dead = 0;
3517 for (i = regno_first; i <= regno_last; ++i)
4dc9341c 3518 {
402209ff
JH
3519 int needed_regno = REGNO_REG_SET_P (pbi->reg_live, i);
3520 some_was_live |= needed_regno;
3521 some_was_dead |= ! needed_regno;
4dc9341c
MH
3522 }
3523
402209ff
JH
3524 /* Find out if any of the register was set this insn. */
3525 some_not_set = 0;
3526 for (i = regno_first; i <= regno_last; ++i)
3527 some_not_set |= ! REGNO_REG_SET_P (pbi->new_set, i);
3528
3529 if (pbi->flags & (PROP_LOG_LINKS | PROP_AUTOINC))
c34d5374 3530 {
402209ff
JH
3531 /* Record where each reg is used, so when the reg is set we know
3532 the next insn that uses it. */
3533 pbi->reg_next_use[regno_first] = insn;
c34d5374 3534 }
c9bacfdb 3535
402209ff
JH
3536 if (pbi->flags & PROP_REG_INFO)
3537 {
3538 if (regno_first < FIRST_PSEUDO_REGISTER)
3539 {
3540 /* If this is a register we are going to try to eliminate,
3541 don't mark it live here. If we are successful in
3542 eliminating it, it need not be live unless it is used for
3543 pseudos, in which case it will have been set live when it
3544 was allocated to the pseudos. If the register will not
3545 be eliminated, reload will set it live at that point.
4dc9341c 3546
402209ff
JH
3547 Otherwise, record that this function uses this register. */
3548 /* ??? The PPC backend tries to "eliminate" on the pic
3549 register to itself. This should be fixed. In the mean
3550 time, hack around it. */
c9bacfdb 3551
402209ff
JH
3552 if (! (TEST_HARD_REG_BIT (elim_reg_set, regno_first)
3553 && (regno_first == FRAME_POINTER_REGNUM
3554 || regno_first == ARG_POINTER_REGNUM)))
3555 for (i = regno_first; i <= regno_last; ++i)
3556 regs_ever_live[i] = 1;
3557 }
3558 else
3559 {
3560 /* Keep track of which basic block each reg appears in. */
6057c0e6 3561
0b17ab2f 3562 int blocknum = pbi->bb->index;
402209ff
JH
3563 if (REG_BASIC_BLOCK (regno_first) == REG_BLOCK_UNKNOWN)
3564 REG_BASIC_BLOCK (regno_first) = blocknum;
3565 else if (REG_BASIC_BLOCK (regno_first) != blocknum)
3566 REG_BASIC_BLOCK (regno_first) = REG_BLOCK_GLOBAL;
6057c0e6 3567
402209ff
JH
3568 /* Count (weighted) number of uses of each reg. */
3569 REG_FREQ (regno_first) += REG_FREQ_FROM_BB (pbi->bb);
3570 REG_N_REFS (regno_first)++;
3571 }
736b64dd
JH
3572 for (i = regno_first; i <= regno_last; ++i)
3573 if (! REGNO_REG_SET_P (pbi->reg_live, i))
3574 {
3575#ifdef ENABLE_CHECKING
3576 if (reg_deaths[i])
3577 abort ();
3578#endif
3579 reg_deaths[i] = pbi->insn_num;
3580 }
402209ff 3581 }
6057c0e6 3582
402209ff
JH
3583 /* Record and count the insns in which a reg dies. If it is used in
3584 this insn and was dead below the insn then it dies in this insn.
3585 If it was set in this insn, we do not make a REG_DEAD note;
3586 likewise if we already made such a note. */
3587 if ((pbi->flags & (PROP_DEATH_NOTES | PROP_REG_INFO))
3588 && some_was_dead
3589 && some_not_set)
3590 {
3591 /* Check for the case where the register dying partially
3592 overlaps the register set by this insn. */
3593 if (regno_first != regno_last)
3594 for (i = regno_first; i <= regno_last; ++i)
3595 some_was_live |= REGNO_REG_SET_P (pbi->new_set, i);
4dc9341c 3596
402209ff
JH
3597 /* If none of the words in X is needed, make a REG_DEAD note.
3598 Otherwise, we must make partial REG_DEAD notes. */
3599 if (! some_was_live)
3600 {
3601 if ((pbi->flags & PROP_DEATH_NOTES)
3602 && ! find_regno_note (insn, REG_DEAD, regno_first))
3603 REG_NOTES (insn)
3604 = alloc_EXPR_LIST (REG_DEAD, reg, REG_NOTES (insn));
4dc9341c 3605
402209ff
JH
3606 if (pbi->flags & PROP_REG_INFO)
3607 REG_N_DEATHS (regno_first)++;
3608 }
3609 else
3610 {
3611 /* Don't make a REG_DEAD note for a part of a register
3612 that is set in the insn. */
3613 for (i = regno_first; i <= regno_last; ++i)
3614 if (! REGNO_REG_SET_P (pbi->reg_live, i)
3615 && ! dead_or_set_regno_p (insn, i))
3616 REG_NOTES (insn)
3617 = alloc_EXPR_LIST (REG_DEAD,
e50126e8 3618 regno_reg_rtx[i],
402209ff
JH
3619 REG_NOTES (insn));
3620 }
3621 }
4dc9341c 3622
402209ff
JH
3623 /* Mark the register as being live. */
3624 for (i = regno_first; i <= regno_last; ++i)
4dc9341c 3625 {
9be40833
RH
3626#ifdef HAVE_conditional_execution
3627 int this_was_live = REGNO_REG_SET_P (pbi->reg_live, i);
3628#endif
3629
402209ff 3630 SET_REGNO_REG_SET (pbi->reg_live, i);
4dc9341c 3631
402209ff
JH
3632#ifdef HAVE_conditional_execution
3633 /* If this is a conditional use, record that fact. If it is later
3634 conditionally set, we'll know to kill the register. */
3635 if (cond != NULL_RTX)
4dc9341c 3636 {
402209ff
JH
3637 splay_tree_node node;
3638 struct reg_cond_life_info *rcli;
3639 rtx ncond;
3640
9be40833 3641 if (this_was_live)
402209ff
JH
3642 {
3643 node = splay_tree_lookup (pbi->reg_cond_dead, i);
3644 if (node == NULL)
3645 {
3646 /* The register was unconditionally live previously.
3647 No need to do anything. */
3648 }
3649 else
3650 {
3651 /* The register was conditionally live previously.
3652 Subtract the new life cond from the old death cond. */
3653 rcli = (struct reg_cond_life_info *) node->value;
3654 ncond = rcli->condition;
3655 ncond = and_reg_cond (ncond, not_reg_cond (cond), 1);
4dc9341c 3656
402209ff
JH
3657 /* If the register is now unconditionally live,
3658 remove the entry in the splay_tree. */
3659 if (ncond == const0_rtx)
3660 splay_tree_remove (pbi->reg_cond_dead, i);
3661 else
3662 {
3663 rcli->condition = ncond;
3664 SET_REGNO_REG_SET (pbi->reg_cond_reg,
3665 REGNO (XEXP (cond, 0)));
3666 }
3667 }
3668 }
3669 else
4dc9341c 3670 {
402209ff
JH
3671 /* The register was not previously live at all. Record
3672 the condition under which it is still dead. */
703ad42b 3673 rcli = xmalloc (sizeof (*rcli));
402209ff
JH
3674 rcli->condition = not_reg_cond (cond);
3675 rcli->stores = const0_rtx;
3676 rcli->orig_condition = const0_rtx;
3677 splay_tree_insert (pbi->reg_cond_dead, i,
3678 (splay_tree_value) rcli);
4dc9341c 3679
402209ff 3680 SET_REGNO_REG_SET (pbi->reg_cond_reg, REGNO (XEXP (cond, 0)));
4dc9341c
MH
3681 }
3682 }
9be40833 3683 else if (this_was_live)
4dc9341c 3684 {
402209ff
JH
3685 /* The register may have been conditionally live previously, but
3686 is now unconditionally live. Remove it from the conditionally
3687 dead list, so that a conditional set won't cause us to think
3688 it dead. */
3689 splay_tree_remove (pbi->reg_cond_dead, i);
4dc9341c 3690 }
402209ff 3691#endif
4dc9341c
MH
3692 }
3693}
3694
402209ff
JH
3695/* Scan expression X and store a 1-bit in NEW_LIVE for each reg it uses.
3696 This is done assuming the registers needed from X are those that
3697 have 1-bits in PBI->REG_LIVE.
6057c0e6 3698
402209ff
JH
3699 INSN is the containing instruction. If INSN is dead, this function
3700 is not called. */
135ebc36 3701
402209ff 3702static void
6cf9ac28 3703mark_used_regs (struct propagate_block_info *pbi, rtx x, rtx cond, rtx insn)
135ebc36 3704{
b3694847
SS
3705 RTX_CODE code;
3706 int regno;
402209ff 3707 int flags = pbi->flags;
135ebc36 3708
402209ff 3709 retry:
5a133afd
JH
3710 if (!x)
3711 return;
402209ff
JH
3712 code = GET_CODE (x);
3713 switch (code)
135ebc36 3714 {
402209ff
JH
3715 case LABEL_REF:
3716 case SYMBOL_REF:
3717 case CONST_INT:
3718 case CONST:
3719 case CONST_DOUBLE:
69ef87e2 3720 case CONST_VECTOR:
402209ff
JH
3721 case PC:
3722 case ADDR_VEC:
3723 case ADDR_DIFF_VEC:
3724 return;
4dc9341c 3725
402209ff
JH
3726#ifdef HAVE_cc0
3727 case CC0:
3728 pbi->cc0_live = 1;
3729 return;
3730#endif
4dc9341c 3731
402209ff
JH
3732 case CLOBBER:
3733 /* If we are clobbering a MEM, mark any registers inside the address
3734 as being used. */
3c0cb5de 3735 if (MEM_P (XEXP (x, 0)))
402209ff
JH
3736 mark_used_regs (pbi, XEXP (XEXP (x, 0), 0), cond, insn);
3737 return;
4dc9341c 3738
402209ff
JH
3739 case MEM:
3740 /* Don't bother watching stores to mems if this is not the
3741 final pass. We'll not be deleting dead stores this round. */
5149f070 3742 if (optimize && (flags & PROP_SCAN_DEAD_STORES))
4dc9341c 3743 {
402209ff
JH
3744 /* Invalidate the data for the last MEM stored, but only if MEM is
3745 something that can be stored into. */
3746 if (GET_CODE (XEXP (x, 0)) == SYMBOL_REF
3747 && CONSTANT_POOL_ADDRESS_P (XEXP (x, 0)))
3748 /* Needn't clear the memory set list. */
3749 ;
3750 else
4dc9341c 3751 {
402209ff
JH
3752 rtx temp = pbi->mem_set_list;
3753 rtx prev = NULL_RTX;
3754 rtx next;
3755
3756 while (temp)
3757 {
3758 next = XEXP (temp, 1);
389fdba0 3759 if (anti_dependence (XEXP (temp, 0), x))
402209ff
JH
3760 {
3761 /* Splice temp out of the list. */
3762 if (prev)
3763 XEXP (prev, 1) = next;
3764 else
3765 pbi->mem_set_list = next;
3766 free_EXPR_LIST_node (temp);
3767 pbi->mem_set_list_len--;
3768 }
3769 else
3770 prev = temp;
3771 temp = next;
3772 }
4dc9341c 3773 }
402209ff
JH
3774
3775 /* If the memory reference had embedded side effects (autoincrement
3776 address modes. Then we may need to kill some entries on the
3777 memory set list. */
3778 if (insn)
fe4b3c79 3779 for_each_rtx (&PATTERN (insn), invalidate_mems_from_autoinc, pbi);
4dc9341c 3780 }
4dc9341c 3781
402209ff
JH
3782#ifdef AUTO_INC_DEC
3783 if (flags & PROP_AUTOINC)
dd3f0101 3784 find_auto_inc (pbi, x, insn);
402209ff
JH
3785#endif
3786 break;
d59c5346 3787
402209ff 3788 case SUBREG:
cff9f8d5 3789#ifdef CANNOT_CHANGE_MODE_CLASS
af166e5d 3790 if ((flags & PROP_REG_INFO)
f8cfc6aa 3791 && REG_P (SUBREG_REG (x))
cff9f8d5 3792 && REGNO (SUBREG_REG (x)) >= FIRST_PSEUDO_REGISTER)
10a3fdd9
JH
3793 bitmap_set_bit (&subregs_of_mode, REGNO (SUBREG_REG (x))
3794 * MAX_MACHINE_MODE
3795 + GET_MODE (x));
402209ff 3796#endif
d59c5346 3797
402209ff
JH
3798 /* While we're here, optimize this case. */
3799 x = SUBREG_REG (x);
f8cfc6aa 3800 if (!REG_P (x))
402209ff
JH
3801 goto retry;
3802 /* Fall through. */
d59c5346 3803
402209ff
JH
3804 case REG:
3805 /* See a register other than being set => mark it as needed. */
3806 mark_used_reg (pbi, x, cond, insn);
3807 return;
d59c5346 3808
402209ff
JH
3809 case SET:
3810 {
b3694847 3811 rtx testreg = SET_DEST (x);
402209ff 3812 int mark_dest = 0;
d59c5346 3813
402209ff
JH
3814 /* If storing into MEM, don't show it as being used. But do
3815 show the address as being used. */
3c0cb5de 3816 if (MEM_P (testreg))
402209ff
JH
3817 {
3818#ifdef AUTO_INC_DEC
3819 if (flags & PROP_AUTOINC)
3820 find_auto_inc (pbi, testreg, insn);
3821#endif
3822 mark_used_regs (pbi, XEXP (testreg, 0), cond, insn);
3823 mark_used_regs (pbi, SET_SRC (x), cond, insn);
3824 return;
3825 }
d59c5346 3826
402209ff
JH
3827 /* Storing in STRICT_LOW_PART is like storing in a reg
3828 in that this SET might be dead, so ignore it in TESTREG.
3829 but in some other ways it is like using the reg.
d59c5346 3830
402209ff
JH
3831 Storing in a SUBREG or a bit field is like storing the entire
3832 register in that if the register's value is not used
3833 then this SET is not needed. */
3834 while (GET_CODE (testreg) == STRICT_LOW_PART
3835 || GET_CODE (testreg) == ZERO_EXTRACT
3836 || GET_CODE (testreg) == SIGN_EXTRACT
3837 || GET_CODE (testreg) == SUBREG)
3838 {
cff9f8d5 3839#ifdef CANNOT_CHANGE_MODE_CLASS
af166e5d
ZD
3840 if ((flags & PROP_REG_INFO)
3841 && GET_CODE (testreg) == SUBREG
f8cfc6aa 3842 && REG_P (SUBREG_REG (testreg))
cff9f8d5 3843 && REGNO (SUBREG_REG (testreg)) >= FIRST_PSEUDO_REGISTER)
10a3fdd9
JH
3844 bitmap_set_bit (&subregs_of_mode, REGNO (SUBREG_REG (testreg))
3845 * MAX_MACHINE_MODE
3846 + GET_MODE (testreg));
402209ff 3847#endif
d59c5346 3848
402209ff
JH
3849 /* Modifying a single register in an alternate mode
3850 does not use any of the old value. But these other
3851 ways of storing in a register do use the old value. */
3852 if (GET_CODE (testreg) == SUBREG
ec8e621d
KG
3853 && !((REG_BYTES (SUBREG_REG (testreg))
3854 + UNITS_PER_WORD - 1) / UNITS_PER_WORD
3855 > (REG_BYTES (testreg)
3856 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
402209ff
JH
3857 ;
3858 else
3859 mark_dest = 1;
d59c5346 3860
402209ff
JH
3861 testreg = XEXP (testreg, 0);
3862 }
d59c5346 3863
402209ff
JH
3864 /* If this is a store into a register or group of registers,
3865 recursively scan the value being stored. */
d59c5346 3866
402209ff
JH
3867 if ((GET_CODE (testreg) == PARALLEL
3868 && GET_MODE (testreg) == BLKmode)
f8cfc6aa 3869 || (REG_P (testreg)
402209ff
JH
3870 && (regno = REGNO (testreg),
3871 ! (regno == FRAME_POINTER_REGNUM
3872 && (! reload_completed || frame_pointer_needed)))
3873#if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
3874 && ! (regno == HARD_FRAME_POINTER_REGNUM
3875 && (! reload_completed || frame_pointer_needed))
3876#endif
3877#if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
3878 && ! (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
3879#endif
3880 ))
3881 {
3882 if (mark_dest)
3883 mark_used_regs (pbi, SET_DEST (x), cond, insn);
3884 mark_used_regs (pbi, SET_SRC (x), cond, insn);
3885 return;
3886 }
3887 }
3888 break;
c9bacfdb 3889
402209ff
JH
3890 case ASM_OPERANDS:
3891 case UNSPEC_VOLATILE:
3892 case TRAP_IF:
3893 case ASM_INPUT:
3894 {
3895 /* Traditional and volatile asm instructions must be considered to use
3896 and clobber all hard registers, all pseudo-registers and all of
3897 memory. So must TRAP_IF and UNSPEC_VOLATILE operations.
4dc9341c 3898
402209ff
JH
3899 Consider for instance a volatile asm that changes the fpu rounding
3900 mode. An insn should not be moved across this even if it only uses
3901 pseudo-regs because it might give an incorrectly rounded result.
4dc9341c 3902
402209ff
JH
3903 ?!? Unfortunately, marking all hard registers as live causes massive
3904 problems for the register allocator and marking all pseudos as live
3905 creates mountains of uninitialized variable warnings.
4dc9341c 3906
402209ff
JH
3907 So for now, just clear the memory set list and mark any regs
3908 we can find in ASM_OPERANDS as used. */
3909 if (code != ASM_OPERANDS || MEM_VOLATILE_P (x))
3910 {
3911 free_EXPR_LIST_list (&pbi->mem_set_list);
3912 pbi->mem_set_list_len = 0;
3913 }
c9bacfdb 3914
402209ff
JH
3915 /* For all ASM_OPERANDS, we must traverse the vector of input operands.
3916 We can not just fall through here since then we would be confused
3917 by the ASM_INPUT rtx inside ASM_OPERANDS, which do not indicate
3918 traditional asms unlike their normal usage. */
3919 if (code == ASM_OPERANDS)
3920 {
3921 int j;
628f05b4 3922
402209ff
JH
3923 for (j = 0; j < ASM_OPERANDS_INPUT_LENGTH (x); j++)
3924 mark_used_regs (pbi, ASM_OPERANDS_INPUT (x, j), cond, insn);
3925 }
3926 break;
3927 }
628f05b4 3928
402209ff
JH
3929 case COND_EXEC:
3930 if (cond != NULL_RTX)
3931 abort ();
c9bacfdb 3932
402209ff 3933 mark_used_regs (pbi, COND_EXEC_TEST (x), NULL_RTX, insn);
c9bacfdb 3934
402209ff
JH
3935 cond = COND_EXEC_TEST (x);
3936 x = COND_EXEC_CODE (x);
3937 goto retry;
628f05b4 3938
402209ff
JH
3939 default:
3940 break;
4dc9341c 3941 }
628f05b4 3942
402209ff 3943 /* Recursively scan the operands of this expression. */
4dc9341c 3944
402209ff 3945 {
b3694847
SS
3946 const char * const fmt = GET_RTX_FORMAT (code);
3947 int i;
4dc9341c 3948
402209ff
JH
3949 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3950 {
3951 if (fmt[i] == 'e')
3952 {
3953 /* Tail recursive case: save a function call level. */
3954 if (i == 0)
3955 {
3956 x = XEXP (x, 0);
3957 goto retry;
3958 }
3959 mark_used_regs (pbi, XEXP (x, i), cond, insn);
3960 }
3961 else if (fmt[i] == 'E')
3962 {
b3694847 3963 int j;
402209ff
JH
3964 for (j = 0; j < XVECLEN (x, i); j++)
3965 mark_used_regs (pbi, XVECEXP (x, i, j), cond, insn);
3966 }
3967 }
3968 }
4dc9341c 3969}
402209ff
JH
3970\f
3971#ifdef AUTO_INC_DEC
4dc9341c 3972
402209ff 3973static int
6cf9ac28 3974try_pre_increment_1 (struct propagate_block_info *pbi, rtx insn)
402209ff
JH
3975{
3976 /* Find the next use of this reg. If in same basic block,
3977 make it do pre-increment or pre-decrement if appropriate. */
3978 rtx x = single_set (insn);
3979 HOST_WIDE_INT amount = ((GET_CODE (SET_SRC (x)) == PLUS ? 1 : -1)
3980 * INTVAL (XEXP (SET_SRC (x), 1)));
3981 int regno = REGNO (SET_DEST (x));
3982 rtx y = pbi->reg_next_use[regno];
3983 if (y != 0
3984 && SET_DEST (x) != stack_pointer_rtx
3985 && BLOCK_NUM (y) == BLOCK_NUM (insn)
3986 /* Don't do this if the reg dies, or gets set in y; a standard addressing
3987 mode would be better. */
3988 && ! dead_or_set_p (y, SET_DEST (x))
3989 && try_pre_increment (y, SET_DEST (x), amount))
3990 {
3991 /* We have found a suitable auto-increment and already changed
3992 insn Y to do it. So flush this increment instruction. */
3dec4024 3993 propagate_block_delete_insn (insn);
b53978a3 3994
402209ff
JH
3995 /* Count a reference to this reg for the increment insn we are
3996 deleting. When a reg is incremented, spilling it is worse,
3997 so we want to make that less likely. */
3998 if (regno >= FIRST_PSEUDO_REGISTER)
3999 {
4000 REG_FREQ (regno) += REG_FREQ_FROM_BB (pbi->bb);
4001 REG_N_SETS (regno)++;
4002 }
b53978a3 4003
402209ff
JH
4004 /* Flush any remembered memories depending on the value of
4005 the incremented register. */
4006 invalidate_mems_from_set (pbi, SET_DEST (x));
b53978a3 4007
402209ff
JH
4008 return 1;
4009 }
4010 return 0;
4011}
b53978a3 4012
402209ff
JH
4013/* Try to change INSN so that it does pre-increment or pre-decrement
4014 addressing on register REG in order to add AMOUNT to REG.
4015 AMOUNT is negative for pre-decrement.
4016 Returns 1 if the change could be made.
4017 This checks all about the validity of the result of modifying INSN. */
b53978a3 4018
402209ff 4019static int
6cf9ac28 4020try_pre_increment (rtx insn, rtx reg, HOST_WIDE_INT amount)
b53978a3 4021{
b3694847 4022 rtx use;
b53978a3 4023
402209ff
JH
4024 /* Nonzero if we can try to make a pre-increment or pre-decrement.
4025 For example, addl $4,r1; movl (r1),... can become movl +(r1),... */
4026 int pre_ok = 0;
4027 /* Nonzero if we can try to make a post-increment or post-decrement.
4028 For example, addl $4,r1; movl -4(r1),... can become movl (r1)+,...
4029 It is possible for both PRE_OK and POST_OK to be nonzero if the machine
4030 supports both pre-inc and post-inc, or both pre-dec and post-dec. */
4031 int post_ok = 0;
b53978a3 4032
402209ff
JH
4033 /* Nonzero if the opportunity actually requires post-inc or post-dec. */
4034 int do_post = 0;
b53978a3 4035
402209ff
JH
4036 /* From the sign of increment, see which possibilities are conceivable
4037 on this target machine. */
4038 if (HAVE_PRE_INCREMENT && amount > 0)
4039 pre_ok = 1;
4040 if (HAVE_POST_INCREMENT && amount > 0)
4041 post_ok = 1;
b53978a3 4042
402209ff
JH
4043 if (HAVE_PRE_DECREMENT && amount < 0)
4044 pre_ok = 1;
4045 if (HAVE_POST_DECREMENT && amount < 0)
4046 post_ok = 1;
b53978a3 4047
402209ff
JH
4048 if (! (pre_ok || post_ok))
4049 return 0;
b53978a3 4050
402209ff
JH
4051 /* It is not safe to add a side effect to a jump insn
4052 because if the incremented register is spilled and must be reloaded
4053 there would be no way to store the incremented value back in memory. */
c9bacfdb 4054
4b4bf941 4055 if (JUMP_P (insn))
402209ff 4056 return 0;
b53978a3 4057
402209ff
JH
4058 use = 0;
4059 if (pre_ok)
4060 use = find_use_as_address (PATTERN (insn), reg, 0);
60e8b9f0 4061 if (post_ok && (use == 0 || use == (rtx) (size_t) 1))
b53978a3 4062 {
402209ff
JH
4063 use = find_use_as_address (PATTERN (insn), reg, -amount);
4064 do_post = 1;
b53978a3
JO
4065 }
4066
60e8b9f0 4067 if (use == 0 || use == (rtx) (size_t) 1)
402209ff
JH
4068 return 0;
4069
4070 if (GET_MODE_SIZE (GET_MODE (use)) != (amount > 0 ? amount : - amount))
4071 return 0;
b53978a3 4072
402209ff
JH
4073 /* See if this combination of instruction and addressing mode exists. */
4074 if (! validate_change (insn, &XEXP (use, 0),
4075 gen_rtx_fmt_e (amount > 0
4076 ? (do_post ? POST_INC : PRE_INC)
4077 : (do_post ? POST_DEC : PRE_DEC),
4078 Pmode, reg), 0))
4079 return 0;
b53978a3 4080
402209ff
JH
4081 /* Record that this insn now has an implicit side effect on X. */
4082 REG_NOTES (insn) = alloc_EXPR_LIST (REG_INC, reg, REG_NOTES (insn));
4083 return 1;
b53978a3
JO
4084}
4085
402209ff
JH
4086#endif /* AUTO_INC_DEC */
4087\f
4088/* Find the place in the rtx X where REG is used as a memory address.
4089 Return the MEM rtx that so uses it.
4090 If PLUSCONST is nonzero, search instead for a memory address equivalent to
4091 (plus REG (const_int PLUSCONST)).
5d6a16e2 4092
402209ff
JH
4093 If such an address does not appear, return 0.
4094 If REG appears more than once, or is used other than in such an address,
60e8b9f0 4095 return (rtx) 1. */
5d6a16e2 4096
402209ff 4097rtx
6cf9ac28 4098find_use_as_address (rtx x, rtx reg, HOST_WIDE_INT plusconst)
5d6a16e2 4099{
402209ff
JH
4100 enum rtx_code code = GET_CODE (x);
4101 const char * const fmt = GET_RTX_FORMAT (code);
b3694847
SS
4102 int i;
4103 rtx value = 0;
4104 rtx tem;
4a7da9b5 4105
402209ff
JH
4106 if (code == MEM && XEXP (x, 0) == reg && plusconst == 0)
4107 return x;
5d6a16e2 4108
402209ff
JH
4109 if (code == MEM && GET_CODE (XEXP (x, 0)) == PLUS
4110 && XEXP (XEXP (x, 0), 0) == reg
4111 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4112 && INTVAL (XEXP (XEXP (x, 0), 1)) == plusconst)
4113 return x;
ef120fc0 4114
402209ff 4115 if (code == SIGN_EXTRACT || code == ZERO_EXTRACT)
5d6a16e2 4116 {
402209ff
JH
4117 /* If REG occurs inside a MEM used in a bit-field reference,
4118 that is unacceptable. */
4119 if (find_use_as_address (XEXP (x, 0), reg, 0) != 0)
60e8b9f0 4120 return (rtx) (size_t) 1;
5d6a16e2 4121 }
5d6a16e2 4122
402209ff 4123 if (x == reg)
60e8b9f0 4124 return (rtx) (size_t) 1;
4dc9341c 4125
402209ff 4126 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4dc9341c 4127 {
402209ff
JH
4128 if (fmt[i] == 'e')
4129 {
4130 tem = find_use_as_address (XEXP (x, i), reg, plusconst);
4131 if (value == 0)
4132 value = tem;
4133 else if (tem != 0)
60e8b9f0 4134 return (rtx) (size_t) 1;
402209ff
JH
4135 }
4136 else if (fmt[i] == 'E')
4dc9341c 4137 {
b3694847 4138 int j;
402209ff 4139 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4dc9341c 4140 {
402209ff
JH
4141 tem = find_use_as_address (XVECEXP (x, i, j), reg, plusconst);
4142 if (value == 0)
4143 value = tem;
4144 else if (tem != 0)
60e8b9f0 4145 return (rtx) (size_t) 1;
4dc9341c
MH
4146 }
4147 }
4148 }
4dc9341c 4149
402209ff
JH
4150 return value;
4151}
4152\f
4153/* Write information about registers and basic blocks into FILE.
4154 This is part of making a debugging dump. */
c9bacfdb 4155
402209ff 4156void
6cf9ac28 4157dump_regset (regset r, FILE *outf)
4dc9341c 4158{
402209ff
JH
4159 int i;
4160 if (r == NULL)
3abd3239 4161 {
402209ff 4162 fputs (" (nil)", outf);
3abd3239
MH
4163 return;
4164 }
4dc9341c 4165
402209ff 4166 EXECUTE_IF_SET_IN_REG_SET (r, 0, i,
4dc9341c 4167 {
402209ff
JH
4168 fprintf (outf, " %d", i);
4169 if (i < FIRST_PSEUDO_REGISTER)
4170 fprintf (outf, " [%s]",
4171 reg_names[i]);
4172 });
4dc9341c
MH
4173}
4174
fbe5a4a6 4175/* Print a human-readable representation of R on the standard error
402209ff
JH
4176 stream. This function is designed to be used from within the
4177 debugger. */
c9bacfdb 4178
402209ff 4179void
6cf9ac28 4180debug_regset (regset r)
4dc9341c 4181{
402209ff
JH
4182 dump_regset (r, stderr);
4183 putc ('\n', stderr);
4dc9341c
MH
4184}
4185
402209ff
JH
4186/* Recompute register set/reference counts immediately prior to register
4187 allocation.
5d6a16e2 4188
402209ff
JH
4189 This avoids problems with set/reference counts changing to/from values
4190 which have special meanings to the register allocators.
eab02feb 4191
402209ff
JH
4192 Additionally, the reference counts are the primary component used by the
4193 register allocators to prioritize pseudos for allocation to hard regs.
4194 More accurate reference counts generally lead to better register allocation.
eab02feb 4195
402209ff 4196 F is the first insn to be scanned.
eab02feb 4197
402209ff
JH
4198 LOOP_STEP denotes how much loop_depth should be incremented per
4199 loop nesting level in order to increase the ref count more for
4200 references in a loop.
b9f22704 4201
402209ff
JH
4202 It might be worthwhile to update REG_LIVE_LENGTH, REG_BASIC_BLOCK and
4203 possibly other information which is used by the register allocators. */
eab02feb 4204
402209ff 4205void
6cf9ac28 4206recompute_reg_usage (rtx f ATTRIBUTE_UNUSED, int loop_step ATTRIBUTE_UNUSED)
402209ff
JH
4207{
4208 allocate_reg_life_data ();
58565a33
SKG
4209 /* distribute_notes in combiner fails to convert some of the REG_UNUSED notes
4210 to REG_DEAD notes. This causes CHECK_DEAD_NOTES in sched1 to abort. To
4211 solve this update the DEATH_NOTES here. */
4212 update_life_info (NULL, UPDATE_LIFE_LOCAL, PROP_REG_INFO | PROP_DEATH_NOTES);
eab02feb
MH
4213}
4214
402209ff
JH
4215/* Optionally removes all the REG_DEAD and REG_UNUSED notes from a set of
4216 blocks. If BLOCKS is NULL, assume the universal set. Returns a count
4217 of the number of registers that died. */
d4b60170 4218
c9bacfdb 4219int
6cf9ac28 4220count_or_remove_death_notes (sbitmap blocks, int kill)
4dc9341c 4221{
e0082a72 4222 int count = 0;
095c3bbd 4223 int i;
e0082a72 4224 basic_block bb;
ce4bbac7 4225
095c3bbd
JL
4226 /* This used to be a loop over all the blocks with a membership test
4227 inside the loop. That can be amazingly expensive on a large CFG
4228 when only a small number of bits are set in BLOCKs (for example,
4229 the calls from the scheduler typically have very few bits set).
4230
4231 For extra credit, someone should convert BLOCKS to a bitmap rather
4232 than an sbitmap. */
4233 if (blocks)
4234 {
4235 EXECUTE_IF_SET_IN_SBITMAP (blocks, 0, i,
4236 {
4237 count += count_or_remove_death_notes_bb (BASIC_BLOCK (i), kill);
4238 });
4239 }
4240 else
4dc9341c 4241 {
095c3bbd
JL
4242 FOR_EACH_BB (bb)
4243 {
4244 count += count_or_remove_death_notes_bb (bb, kill);
4245 }
4246 }
5d6a16e2 4247
095c3bbd
JL
4248 return count;
4249}
4250
4251/* Optionally removes all the REG_DEAD and REG_UNUSED notes from basic
4252 block BB. Returns a count of the number of registers that died. */
5d6a16e2 4253
095c3bbd
JL
4254static int
4255count_or_remove_death_notes_bb (basic_block bb, int kill)
4256{
4257 int count = 0;
4258 rtx insn;
4259
a813c111 4260 for (insn = BB_HEAD (bb); ; insn = NEXT_INSN (insn))
095c3bbd
JL
4261 {
4262 if (INSN_P (insn))
4dc9341c 4263 {
095c3bbd
JL
4264 rtx *pprev = &REG_NOTES (insn);
4265 rtx link = *pprev;
402209ff 4266
095c3bbd
JL
4267 while (link)
4268 {
4269 switch (REG_NOTE_KIND (link))
4dc9341c 4270 {
095c3bbd 4271 case REG_DEAD:
f8cfc6aa 4272 if (REG_P (XEXP (link, 0)))
095c3bbd
JL
4273 {
4274 rtx reg = XEXP (link, 0);
4275 int n;
4276
4277 if (REGNO (reg) >= FIRST_PSEUDO_REGISTER)
4278 n = 1;
4279 else
66fd46b6 4280 n = hard_regno_nregs[REGNO (reg)][GET_MODE (reg)];
095c3bbd
JL
4281 count += n;
4282 }
4283
4284 /* Fall through. */
4285
4286 case REG_UNUSED:
4287 if (kill)
402209ff 4288 {
095c3bbd
JL
4289 rtx next = XEXP (link, 1);
4290 free_EXPR_LIST_node (link);
4291 *pprev = link = next;
402209ff
JH
4292 break;
4293 }
095c3bbd
JL
4294 /* Fall through. */
4295
4296 default:
4297 pprev = &XEXP (link, 1);
4298 link = *pprev;
4299 break;
4dc9341c
MH
4300 }
4301 }
5d6a16e2 4302 }
095c3bbd 4303
a813c111 4304 if (insn == BB_END (bb))
095c3bbd 4305 break;
5a660bff 4306 }
4dc9341c 4307
402209ff 4308 return count;
4dc9341c 4309}
095c3bbd 4310
b932f770
JH
4311/* Clear LOG_LINKS fields of insns in a selected blocks or whole chain
4312 if blocks is NULL. */
efc9bd41 4313
b932f770 4314static void
6cf9ac28 4315clear_log_links (sbitmap blocks)
d9d4fb43 4316{
b932f770
JH
4317 rtx insn;
4318 int i;
1868b439 4319
b932f770 4320 if (!blocks)
1868b439 4321 {
b932f770
JH
4322 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
4323 if (INSN_P (insn))
e9cf0934 4324 free_INSN_LIST_list (&LOG_LINKS (insn));
1868b439 4325 }
b932f770
JH
4326 else
4327 EXECUTE_IF_SET_IN_SBITMAP (blocks, 0, i,
4328 {
4329 basic_block bb = BASIC_BLOCK (i);
16e99e29 4330
a813c111 4331 for (insn = BB_HEAD (bb); insn != NEXT_INSN (BB_END (bb));
b932f770
JH
4332 insn = NEXT_INSN (insn))
4333 if (INSN_P (insn))
e9cf0934 4334 free_INSN_LIST_list (&LOG_LINKS (insn));
b932f770 4335 });
d9d4fb43 4336}
efc9bd41
RK
4337
4338/* Given a register bitmap, turn on the bits in a HARD_REG_SET that
4339 correspond to the hard registers, if any, set in that map. This
4340 could be done far more efficiently by having all sorts of special-cases
4341 with moving single words, but probably isn't worth the trouble. */
4342
4343void
6cf9ac28 4344reg_set_to_hard_reg_set (HARD_REG_SET *to, bitmap from)
efc9bd41
RK
4345{
4346 int i;
4347
4348 EXECUTE_IF_SET_IN_BITMAP
4349 (from, 0, i,
4350 {
4351 if (i >= FIRST_PSEUDO_REGISTER)
4352 return;
4353 SET_HARD_REG_BIT (*to, i);
4354 });
4355}
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