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3cf2715d | 1 | /* Convert RTL to assembler code and output it, for GNU compiler. |
3b708058 | 2 | Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, |
3897f229 | 3 | 1998, 1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc. |
3cf2715d | 4 | |
1322177d | 5 | This file is part of GCC. |
3cf2715d | 6 | |
1322177d LB |
7 | GCC is free software; you can redistribute it and/or modify it under |
8 | the terms of the GNU General Public License as published by the Free | |
9 | Software Foundation; either version 2, or (at your option) any later | |
10 | version. | |
3cf2715d | 11 | |
1322177d LB |
12 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY |
13 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
15 | for more details. | |
3cf2715d DE |
16 | |
17 | You should have received a copy of the GNU General Public License | |
1322177d LB |
18 | along with GCC; see the file COPYING. If not, write to the Free |
19 | Software Foundation, 59 Temple Place - Suite 330, Boston, MA | |
20 | 02111-1307, USA. */ | |
3cf2715d | 21 | |
3cf2715d DE |
22 | /* This is the final pass of the compiler. |
23 | It looks at the rtl code for a function and outputs assembler code. | |
24 | ||
25 | Call `final_start_function' to output the assembler code for function entry, | |
26 | `final' to output assembler code for some RTL code, | |
27 | `final_end_function' to output assembler code for function exit. | |
28 | If a function is compiled in several pieces, each piece is | |
29 | output separately with `final'. | |
30 | ||
31 | Some optimizations are also done at this level. | |
32 | Move instructions that were made unnecessary by good register allocation | |
33 | are detected and omitted from the output. (Though most of these | |
34 | are removed by the last jump pass.) | |
35 | ||
36 | Instructions to set the condition codes are omitted when it can be | |
37 | seen that the condition codes already had the desired values. | |
38 | ||
39 | In some cases it is sufficient if the inherited condition codes | |
40 | have related values, but this may require the following insn | |
41 | (the one that tests the condition codes) to be modified. | |
42 | ||
43 | The code for the function prologue and epilogue are generated | |
08c148a8 NB |
44 | directly in assembler by the target functions function_prologue and |
45 | function_epilogue. Those instructions never exist as rtl. */ | |
3cf2715d DE |
46 | |
47 | #include "config.h" | |
670ee920 | 48 | #include "system.h" |
4977bab6 ZW |
49 | #include "coretypes.h" |
50 | #include "tm.h" | |
3cf2715d DE |
51 | |
52 | #include "tree.h" | |
53 | #include "rtl.h" | |
6baf1cc8 | 54 | #include "tm_p.h" |
3cf2715d DE |
55 | #include "regs.h" |
56 | #include "insn-config.h" | |
3cf2715d | 57 | #include "insn-attr.h" |
3cf2715d DE |
58 | #include "recog.h" |
59 | #include "conditions.h" | |
60 | #include "flags.h" | |
61 | #include "real.h" | |
62 | #include "hard-reg-set.h" | |
3cf2715d | 63 | #include "output.h" |
3d195391 | 64 | #include "except.h" |
49ad7cfa | 65 | #include "function.h" |
10f0ad3d | 66 | #include "toplev.h" |
d6f4ec51 | 67 | #include "reload.h" |
ab87f8c8 | 68 | #include "intl.h" |
be1bb652 | 69 | #include "basic-block.h" |
08c148a8 | 70 | #include "target.h" |
a5a42b92 | 71 | #include "debug.h" |
49d801d3 | 72 | #include "expr.h" |
ba4f7968 | 73 | #include "cfglayout.h" |
3cf2715d | 74 | |
440aabf8 NB |
75 | #ifdef XCOFF_DEBUGGING_INFO |
76 | #include "xcoffout.h" /* Needed for external data | |
77 | declarations for e.g. AIX 4.x. */ | |
78 | #endif | |
79 | ||
76ead72b RL |
80 | #if defined (DWARF2_UNWIND_INFO) || defined (DWARF2_DEBUGGING_INFO) |
81 | #include "dwarf2out.h" | |
82 | #endif | |
83 | ||
6a08f7b3 DP |
84 | #ifdef DBX_DEBUGGING_INFO |
85 | #include "dbxout.h" | |
86 | #endif | |
87 | ||
3cf2715d DE |
88 | /* If we aren't using cc0, CC_STATUS_INIT shouldn't exist. So define a |
89 | null default for it to save conditionalization later. */ | |
90 | #ifndef CC_STATUS_INIT | |
91 | #define CC_STATUS_INIT | |
92 | #endif | |
93 | ||
94 | /* How to start an assembler comment. */ | |
95 | #ifndef ASM_COMMENT_START | |
96 | #define ASM_COMMENT_START ";#" | |
97 | #endif | |
98 | ||
99 | /* Is the given character a logical line separator for the assembler? */ | |
100 | #ifndef IS_ASM_LOGICAL_LINE_SEPARATOR | |
101 | #define IS_ASM_LOGICAL_LINE_SEPARATOR(C) ((C) == ';') | |
102 | #endif | |
103 | ||
75197b37 BS |
104 | #ifndef JUMP_TABLES_IN_TEXT_SECTION |
105 | #define JUMP_TABLES_IN_TEXT_SECTION 0 | |
106 | #endif | |
107 | ||
d48bc59a RH |
108 | #if defined(READONLY_DATA_SECTION) || defined(READONLY_DATA_SECTION_ASM_OP) |
109 | #define HAVE_READONLY_DATA_SECTION 1 | |
110 | #else | |
111 | #define HAVE_READONLY_DATA_SECTION 0 | |
112 | #endif | |
113 | ||
589fe865 DJ |
114 | /* Bitflags used by final_scan_insn. */ |
115 | #define SEEN_BB 1 | |
116 | #define SEEN_NOTE 2 | |
117 | #define SEEN_EMITTED 4 | |
118 | ||
3cf2715d | 119 | /* Last insn processed by final_scan_insn. */ |
b1a9f6a0 RH |
120 | static rtx debug_insn; |
121 | rtx current_output_insn; | |
3cf2715d DE |
122 | |
123 | /* Line number of last NOTE. */ | |
124 | static int last_linenum; | |
125 | ||
eac40081 RK |
126 | /* Highest line number in current block. */ |
127 | static int high_block_linenum; | |
128 | ||
129 | /* Likewise for function. */ | |
130 | static int high_function_linenum; | |
131 | ||
3cf2715d | 132 | /* Filename of last NOTE. */ |
3cce094d | 133 | static const char *last_filename; |
3cf2715d | 134 | |
fc470718 R |
135 | extern int length_unit_log; /* This is defined in insn-attrtab.c. */ |
136 | ||
3cf2715d DE |
137 | /* Nonzero while outputting an `asm' with operands. |
138 | This means that inconsistencies are the user's fault, so don't abort. | |
139 | The precise value is the insn being output, to pass to error_for_asm. */ | |
c8b94768 | 140 | rtx this_is_asm_operands; |
3cf2715d DE |
141 | |
142 | /* Number of operands of this insn, for an `asm' with operands. */ | |
22bf4422 | 143 | static unsigned int insn_noperands; |
3cf2715d DE |
144 | |
145 | /* Compare optimization flag. */ | |
146 | ||
147 | static rtx last_ignored_compare = 0; | |
148 | ||
3cf2715d DE |
149 | /* Assign a unique number to each insn that is output. |
150 | This can be used to generate unique local labels. */ | |
151 | ||
152 | static int insn_counter = 0; | |
153 | ||
154 | #ifdef HAVE_cc0 | |
155 | /* This variable contains machine-dependent flags (defined in tm.h) | |
156 | set and examined by output routines | |
157 | that describe how to interpret the condition codes properly. */ | |
158 | ||
159 | CC_STATUS cc_status; | |
160 | ||
161 | /* During output of an insn, this contains a copy of cc_status | |
162 | from before the insn. */ | |
163 | ||
164 | CC_STATUS cc_prev_status; | |
165 | #endif | |
166 | ||
167 | /* Indexed by hardware reg number, is 1 if that register is ever | |
168 | used in the current function. | |
169 | ||
170 | In life_analysis, or in stupid_life_analysis, this is set | |
171 | up to record the hard regs used explicitly. Reload adds | |
172 | in the hard regs used for holding pseudo regs. Final uses | |
173 | it to generate the code in the function prologue and epilogue | |
174 | to save and restore registers as needed. */ | |
175 | ||
176 | char regs_ever_live[FIRST_PSEUDO_REGISTER]; | |
177 | ||
df2ef49b AM |
178 | /* Like regs_ever_live, but 1 if a reg is set or clobbered from an asm. |
179 | Unlike regs_ever_live, elements of this array corresponding to | |
180 | eliminable regs like the frame pointer are set if an asm sets them. */ | |
181 | ||
182 | char regs_asm_clobbered[FIRST_PSEUDO_REGISTER]; | |
183 | ||
3cf2715d | 184 | /* Nonzero means current function must be given a frame pointer. |
b483cfb7 EB |
185 | Initialized in function.c to 0. Set only in reload1.c as per |
186 | the needs of the function. */ | |
3cf2715d DE |
187 | |
188 | int frame_pointer_needed; | |
189 | ||
18c038b9 | 190 | /* Number of unmatched NOTE_INSN_BLOCK_BEG notes we have seen. */ |
3cf2715d DE |
191 | |
192 | static int block_depth; | |
193 | ||
194 | /* Nonzero if have enabled APP processing of our assembler output. */ | |
195 | ||
196 | static int app_on; | |
197 | ||
198 | /* If we are outputting an insn sequence, this contains the sequence rtx. | |
199 | Zero otherwise. */ | |
200 | ||
201 | rtx final_sequence; | |
202 | ||
203 | #ifdef ASSEMBLER_DIALECT | |
204 | ||
205 | /* Number of the assembler dialect to use, starting at 0. */ | |
206 | static int dialect_number; | |
207 | #endif | |
208 | ||
afe48e06 RH |
209 | #ifdef HAVE_conditional_execution |
210 | /* Nonnull if the insn currently being emitted was a COND_EXEC pattern. */ | |
211 | rtx current_insn_predicate; | |
212 | #endif | |
213 | ||
1d300e19 | 214 | #ifdef HAVE_ATTR_length |
6cf9ac28 AJ |
215 | static int asm_insn_count (rtx); |
216 | #endif | |
217 | static void profile_function (FILE *); | |
218 | static void profile_after_prologue (FILE *); | |
219 | static bool notice_source_line (rtx); | |
220 | static rtx walk_alter_subreg (rtx *); | |
221 | static void output_asm_name (void); | |
222 | static void output_alternate_entry_point (FILE *, rtx); | |
223 | static tree get_mem_expr_from_op (rtx, int *); | |
224 | static void output_asm_operand_names (rtx *, int *, int); | |
225 | static void output_operand (rtx, int); | |
e9a25f70 | 226 | #ifdef LEAF_REGISTERS |
6cf9ac28 | 227 | static void leaf_renumber_regs (rtx); |
e9a25f70 JL |
228 | #endif |
229 | #ifdef HAVE_cc0 | |
6cf9ac28 | 230 | static int alter_cond (rtx); |
e9a25f70 | 231 | #endif |
ca3075bd | 232 | #ifndef ADDR_VEC_ALIGN |
6cf9ac28 | 233 | static int final_addr_vec_align (rtx); |
ca3075bd | 234 | #endif |
7bdb32b9 | 235 | #ifdef HAVE_ATTR_length |
6cf9ac28 | 236 | static int align_fuzz (rtx, rtx, int, unsigned); |
7bdb32b9 | 237 | #endif |
3cf2715d DE |
238 | \f |
239 | /* Initialize data in final at the beginning of a compilation. */ | |
240 | ||
241 | void | |
6cf9ac28 | 242 | init_final (const char *filename ATTRIBUTE_UNUSED) |
3cf2715d | 243 | { |
3cf2715d | 244 | app_on = 0; |
3cf2715d DE |
245 | final_sequence = 0; |
246 | ||
247 | #ifdef ASSEMBLER_DIALECT | |
248 | dialect_number = ASSEMBLER_DIALECT; | |
249 | #endif | |
250 | } | |
251 | ||
08c148a8 | 252 | /* Default target function prologue and epilogue assembler output. |
b9f22704 | 253 | |
08c148a8 NB |
254 | If not overridden for epilogue code, then the function body itself |
255 | contains return instructions wherever needed. */ | |
256 | void | |
6cf9ac28 AJ |
257 | default_function_pro_epilogue (FILE *file ATTRIBUTE_UNUSED, |
258 | HOST_WIDE_INT size ATTRIBUTE_UNUSED) | |
08c148a8 NB |
259 | { |
260 | } | |
261 | ||
b4c25db2 NB |
262 | /* Default target hook that outputs nothing to a stream. */ |
263 | void | |
6cf9ac28 | 264 | no_asm_to_stream (FILE *file ATTRIBUTE_UNUSED) |
b4c25db2 NB |
265 | { |
266 | } | |
267 | ||
3cf2715d DE |
268 | /* Enable APP processing of subsequent output. |
269 | Used before the output from an `asm' statement. */ | |
270 | ||
271 | void | |
6cf9ac28 | 272 | app_enable (void) |
3cf2715d DE |
273 | { |
274 | if (! app_on) | |
275 | { | |
51723711 | 276 | fputs (ASM_APP_ON, asm_out_file); |
3cf2715d DE |
277 | app_on = 1; |
278 | } | |
279 | } | |
280 | ||
281 | /* Disable APP processing of subsequent output. | |
282 | Called from varasm.c before most kinds of output. */ | |
283 | ||
284 | void | |
6cf9ac28 | 285 | app_disable (void) |
3cf2715d DE |
286 | { |
287 | if (app_on) | |
288 | { | |
51723711 | 289 | fputs (ASM_APP_OFF, asm_out_file); |
3cf2715d DE |
290 | app_on = 0; |
291 | } | |
292 | } | |
293 | \f | |
f5d927c0 | 294 | /* Return the number of slots filled in the current |
3cf2715d DE |
295 | delayed branch sequence (we don't count the insn needing the |
296 | delay slot). Zero if not in a delayed branch sequence. */ | |
297 | ||
298 | #ifdef DELAY_SLOTS | |
299 | int | |
6cf9ac28 | 300 | dbr_sequence_length (void) |
3cf2715d DE |
301 | { |
302 | if (final_sequence != 0) | |
303 | return XVECLEN (final_sequence, 0) - 1; | |
304 | else | |
305 | return 0; | |
306 | } | |
307 | #endif | |
308 | \f | |
309 | /* The next two pages contain routines used to compute the length of an insn | |
310 | and to shorten branches. */ | |
311 | ||
312 | /* Arrays for insn lengths, and addresses. The latter is referenced by | |
313 | `insn_current_length'. */ | |
314 | ||
addd7df6 | 315 | static int *insn_lengths; |
9d98a694 | 316 | |
9d98a694 | 317 | varray_type insn_addresses_; |
3cf2715d | 318 | |
ea3cbda5 R |
319 | /* Max uid for which the above arrays are valid. */ |
320 | static int insn_lengths_max_uid; | |
321 | ||
3cf2715d DE |
322 | /* Address of insn being processed. Used by `insn_current_length'. */ |
323 | int insn_current_address; | |
324 | ||
fc470718 R |
325 | /* Address of insn being processed in previous iteration. */ |
326 | int insn_last_address; | |
327 | ||
d6a7951f | 328 | /* known invariant alignment of insn being processed. */ |
fc470718 R |
329 | int insn_current_align; |
330 | ||
95707627 R |
331 | /* After shorten_branches, for any insn, uid_align[INSN_UID (insn)] |
332 | gives the next following alignment insn that increases the known | |
333 | alignment, or NULL_RTX if there is no such insn. | |
334 | For any alignment obtained this way, we can again index uid_align with | |
335 | its uid to obtain the next following align that in turn increases the | |
336 | alignment, till we reach NULL_RTX; the sequence obtained this way | |
337 | for each insn we'll call the alignment chain of this insn in the following | |
338 | comments. */ | |
339 | ||
f5d927c0 KH |
340 | struct label_alignment |
341 | { | |
9e423e6d JW |
342 | short alignment; |
343 | short max_skip; | |
344 | }; | |
345 | ||
346 | static rtx *uid_align; | |
347 | static int *uid_shuid; | |
348 | static struct label_alignment *label_align; | |
95707627 | 349 | |
3cf2715d DE |
350 | /* Indicate that branch shortening hasn't yet been done. */ |
351 | ||
352 | void | |
6cf9ac28 | 353 | init_insn_lengths (void) |
3cf2715d | 354 | { |
95707627 R |
355 | if (uid_shuid) |
356 | { | |
357 | free (uid_shuid); | |
358 | uid_shuid = 0; | |
359 | } | |
360 | if (insn_lengths) | |
361 | { | |
362 | free (insn_lengths); | |
363 | insn_lengths = 0; | |
ea3cbda5 | 364 | insn_lengths_max_uid = 0; |
95707627 | 365 | } |
9d98a694 AO |
366 | #ifdef HAVE_ATTR_length |
367 | INSN_ADDRESSES_FREE (); | |
368 | #endif | |
95707627 R |
369 | if (uid_align) |
370 | { | |
371 | free (uid_align); | |
372 | uid_align = 0; | |
373 | } | |
3cf2715d DE |
374 | } |
375 | ||
376 | /* Obtain the current length of an insn. If branch shortening has been done, | |
377 | get its actual length. Otherwise, get its maximum length. */ | |
378 | ||
379 | int | |
6cf9ac28 | 380 | get_attr_length (rtx insn ATTRIBUTE_UNUSED) |
3cf2715d DE |
381 | { |
382 | #ifdef HAVE_ATTR_length | |
383 | rtx body; | |
384 | int i; | |
385 | int length = 0; | |
386 | ||
ea3cbda5 | 387 | if (insn_lengths_max_uid > INSN_UID (insn)) |
3cf2715d DE |
388 | return insn_lengths[INSN_UID (insn)]; |
389 | else | |
390 | switch (GET_CODE (insn)) | |
391 | { | |
392 | case NOTE: | |
393 | case BARRIER: | |
394 | case CODE_LABEL: | |
395 | return 0; | |
396 | ||
397 | case CALL_INSN: | |
398 | length = insn_default_length (insn); | |
399 | break; | |
400 | ||
401 | case JUMP_INSN: | |
402 | body = PATTERN (insn); | |
dd3f0101 | 403 | if (GET_CODE (body) == ADDR_VEC || GET_CODE (body) == ADDR_DIFF_VEC) |
3cf2715d | 404 | { |
fc470718 R |
405 | /* Alignment is machine-dependent and should be handled by |
406 | ADDR_VEC_ALIGN. */ | |
3cf2715d DE |
407 | } |
408 | else | |
409 | length = insn_default_length (insn); | |
410 | break; | |
411 | ||
412 | case INSN: | |
413 | body = PATTERN (insn); | |
414 | if (GET_CODE (body) == USE || GET_CODE (body) == CLOBBER) | |
415 | return 0; | |
416 | ||
417 | else if (GET_CODE (body) == ASM_INPUT || asm_noperands (body) >= 0) | |
418 | length = asm_insn_count (body) * insn_default_length (insn); | |
419 | else if (GET_CODE (body) == SEQUENCE) | |
420 | for (i = 0; i < XVECLEN (body, 0); i++) | |
421 | length += get_attr_length (XVECEXP (body, 0, i)); | |
422 | else | |
423 | length = insn_default_length (insn); | |
e9a25f70 JL |
424 | break; |
425 | ||
426 | default: | |
427 | break; | |
3cf2715d DE |
428 | } |
429 | ||
430 | #ifdef ADJUST_INSN_LENGTH | |
431 | ADJUST_INSN_LENGTH (insn, length); | |
432 | #endif | |
433 | return length; | |
434 | #else /* not HAVE_ATTR_length */ | |
435 | return 0; | |
436 | #endif /* not HAVE_ATTR_length */ | |
437 | } | |
438 | \f | |
fc470718 R |
439 | /* Code to handle alignment inside shorten_branches. */ |
440 | ||
441 | /* Here is an explanation how the algorithm in align_fuzz can give | |
442 | proper results: | |
443 | ||
444 | Call a sequence of instructions beginning with alignment point X | |
445 | and continuing until the next alignment point `block X'. When `X' | |
f5d927c0 | 446 | is used in an expression, it means the alignment value of the |
fc470718 | 447 | alignment point. |
f5d927c0 | 448 | |
fc470718 R |
449 | Call the distance between the start of the first insn of block X, and |
450 | the end of the last insn of block X `IX', for the `inner size of X'. | |
451 | This is clearly the sum of the instruction lengths. | |
f5d927c0 | 452 | |
fc470718 R |
453 | Likewise with the next alignment-delimited block following X, which we |
454 | shall call block Y. | |
f5d927c0 | 455 | |
fc470718 R |
456 | Call the distance between the start of the first insn of block X, and |
457 | the start of the first insn of block Y `OX', for the `outer size of X'. | |
f5d927c0 | 458 | |
fc470718 | 459 | The estimated padding is then OX - IX. |
f5d927c0 | 460 | |
fc470718 | 461 | OX can be safely estimated as |
f5d927c0 | 462 | |
fc470718 R |
463 | if (X >= Y) |
464 | OX = round_up(IX, Y) | |
465 | else | |
466 | OX = round_up(IX, X) + Y - X | |
f5d927c0 | 467 | |
fc470718 R |
468 | Clearly est(IX) >= real(IX), because that only depends on the |
469 | instruction lengths, and those being overestimated is a given. | |
f5d927c0 | 470 | |
fc470718 R |
471 | Clearly round_up(foo, Z) >= round_up(bar, Z) if foo >= bar, so |
472 | we needn't worry about that when thinking about OX. | |
f5d927c0 | 473 | |
fc470718 R |
474 | When X >= Y, the alignment provided by Y adds no uncertainty factor |
475 | for branch ranges starting before X, so we can just round what we have. | |
476 | But when X < Y, we don't know anything about the, so to speak, | |
477 | `middle bits', so we have to assume the worst when aligning up from an | |
478 | address mod X to one mod Y, which is Y - X. */ | |
479 | ||
480 | #ifndef LABEL_ALIGN | |
efa3896a | 481 | #define LABEL_ALIGN(LABEL) align_labels_log |
fc470718 R |
482 | #endif |
483 | ||
9e423e6d | 484 | #ifndef LABEL_ALIGN_MAX_SKIP |
2cca7283 | 485 | #define LABEL_ALIGN_MAX_SKIP align_labels_max_skip |
9e423e6d JW |
486 | #endif |
487 | ||
fc470718 | 488 | #ifndef LOOP_ALIGN |
efa3896a | 489 | #define LOOP_ALIGN(LABEL) align_loops_log |
fc470718 R |
490 | #endif |
491 | ||
9e423e6d | 492 | #ifndef LOOP_ALIGN_MAX_SKIP |
2cca7283 | 493 | #define LOOP_ALIGN_MAX_SKIP align_loops_max_skip |
9e423e6d JW |
494 | #endif |
495 | ||
fc470718 | 496 | #ifndef LABEL_ALIGN_AFTER_BARRIER |
340f7e7c | 497 | #define LABEL_ALIGN_AFTER_BARRIER(LABEL) 0 |
fc470718 R |
498 | #endif |
499 | ||
9e423e6d | 500 | #ifndef LABEL_ALIGN_AFTER_BARRIER_MAX_SKIP |
247a370b JH |
501 | #define LABEL_ALIGN_AFTER_BARRIER_MAX_SKIP 0 |
502 | #endif | |
503 | ||
504 | #ifndef JUMP_ALIGN | |
505 | #define JUMP_ALIGN(LABEL) align_jumps_log | |
506 | #endif | |
507 | ||
508 | #ifndef JUMP_ALIGN_MAX_SKIP | |
2cca7283 | 509 | #define JUMP_ALIGN_MAX_SKIP align_jumps_max_skip |
9e423e6d JW |
510 | #endif |
511 | ||
fc470718 | 512 | #ifndef ADDR_VEC_ALIGN |
ca3075bd | 513 | static int |
6cf9ac28 | 514 | final_addr_vec_align (rtx addr_vec) |
fc470718 | 515 | { |
2a841588 | 516 | int align = GET_MODE_SIZE (GET_MODE (PATTERN (addr_vec))); |
fc470718 R |
517 | |
518 | if (align > BIGGEST_ALIGNMENT / BITS_PER_UNIT) | |
519 | align = BIGGEST_ALIGNMENT / BITS_PER_UNIT; | |
2a841588 | 520 | return exact_log2 (align); |
fc470718 R |
521 | |
522 | } | |
f5d927c0 | 523 | |
fc470718 R |
524 | #define ADDR_VEC_ALIGN(ADDR_VEC) final_addr_vec_align (ADDR_VEC) |
525 | #endif | |
526 | ||
527 | #ifndef INSN_LENGTH_ALIGNMENT | |
528 | #define INSN_LENGTH_ALIGNMENT(INSN) length_unit_log | |
529 | #endif | |
530 | ||
fc470718 R |
531 | #define INSN_SHUID(INSN) (uid_shuid[INSN_UID (INSN)]) |
532 | ||
de7987a6 | 533 | static int min_labelno, max_labelno; |
fc470718 R |
534 | |
535 | #define LABEL_TO_ALIGNMENT(LABEL) \ | |
9e423e6d JW |
536 | (label_align[CODE_LABEL_NUMBER (LABEL) - min_labelno].alignment) |
537 | ||
538 | #define LABEL_TO_MAX_SKIP(LABEL) \ | |
539 | (label_align[CODE_LABEL_NUMBER (LABEL) - min_labelno].max_skip) | |
fc470718 R |
540 | |
541 | /* For the benefit of port specific code do this also as a function. */ | |
f5d927c0 | 542 | |
fc470718 | 543 | int |
6cf9ac28 | 544 | label_to_alignment (rtx label) |
fc470718 R |
545 | { |
546 | return LABEL_TO_ALIGNMENT (label); | |
547 | } | |
548 | ||
549 | #ifdef HAVE_ATTR_length | |
550 | /* The differences in addresses | |
551 | between a branch and its target might grow or shrink depending on | |
552 | the alignment the start insn of the range (the branch for a forward | |
553 | branch or the label for a backward branch) starts out on; if these | |
554 | differences are used naively, they can even oscillate infinitely. | |
555 | We therefore want to compute a 'worst case' address difference that | |
556 | is independent of the alignment the start insn of the range end | |
557 | up on, and that is at least as large as the actual difference. | |
558 | The function align_fuzz calculates the amount we have to add to the | |
559 | naively computed difference, by traversing the part of the alignment | |
560 | chain of the start insn of the range that is in front of the end insn | |
561 | of the range, and considering for each alignment the maximum amount | |
562 | that it might contribute to a size increase. | |
563 | ||
564 | For casesi tables, we also want to know worst case minimum amounts of | |
565 | address difference, in case a machine description wants to introduce | |
566 | some common offset that is added to all offsets in a table. | |
d6a7951f | 567 | For this purpose, align_fuzz with a growth argument of 0 computes the |
fc470718 R |
568 | appropriate adjustment. */ |
569 | ||
fc470718 R |
570 | /* Compute the maximum delta by which the difference of the addresses of |
571 | START and END might grow / shrink due to a different address for start | |
572 | which changes the size of alignment insns between START and END. | |
573 | KNOWN_ALIGN_LOG is the alignment known for START. | |
574 | GROWTH should be ~0 if the objective is to compute potential code size | |
575 | increase, and 0 if the objective is to compute potential shrink. | |
576 | The return value is undefined for any other value of GROWTH. */ | |
f5d927c0 | 577 | |
ca3075bd | 578 | static int |
6cf9ac28 | 579 | align_fuzz (rtx start, rtx end, int known_align_log, unsigned int growth) |
fc470718 R |
580 | { |
581 | int uid = INSN_UID (start); | |
582 | rtx align_label; | |
583 | int known_align = 1 << known_align_log; | |
584 | int end_shuid = INSN_SHUID (end); | |
585 | int fuzz = 0; | |
586 | ||
587 | for (align_label = uid_align[uid]; align_label; align_label = uid_align[uid]) | |
588 | { | |
589 | int align_addr, new_align; | |
590 | ||
591 | uid = INSN_UID (align_label); | |
9d98a694 | 592 | align_addr = INSN_ADDRESSES (uid) - insn_lengths[uid]; |
fc470718 R |
593 | if (uid_shuid[uid] > end_shuid) |
594 | break; | |
595 | known_align_log = LABEL_TO_ALIGNMENT (align_label); | |
596 | new_align = 1 << known_align_log; | |
597 | if (new_align < known_align) | |
598 | continue; | |
599 | fuzz += (-align_addr ^ growth) & (new_align - known_align); | |
600 | known_align = new_align; | |
601 | } | |
602 | return fuzz; | |
603 | } | |
604 | ||
605 | /* Compute a worst-case reference address of a branch so that it | |
606 | can be safely used in the presence of aligned labels. Since the | |
607 | size of the branch itself is unknown, the size of the branch is | |
608 | not included in the range. I.e. for a forward branch, the reference | |
609 | address is the end address of the branch as known from the previous | |
610 | branch shortening pass, minus a value to account for possible size | |
611 | increase due to alignment. For a backward branch, it is the start | |
612 | address of the branch as known from the current pass, plus a value | |
613 | to account for possible size increase due to alignment. | |
614 | NB.: Therefore, the maximum offset allowed for backward branches needs | |
615 | to exclude the branch size. */ | |
f5d927c0 | 616 | |
fc470718 | 617 | int |
6cf9ac28 | 618 | insn_current_reference_address (rtx branch) |
fc470718 | 619 | { |
5527bf14 RH |
620 | rtx dest, seq; |
621 | int seq_uid; | |
622 | ||
623 | if (! INSN_ADDRESSES_SET_P ()) | |
624 | return 0; | |
625 | ||
626 | seq = NEXT_INSN (PREV_INSN (branch)); | |
627 | seq_uid = INSN_UID (seq); | |
fc470718 R |
628 | if (GET_CODE (branch) != JUMP_INSN) |
629 | /* This can happen for example on the PA; the objective is to know the | |
630 | offset to address something in front of the start of the function. | |
631 | Thus, we can treat it like a backward branch. | |
632 | We assume here that FUNCTION_BOUNDARY / BITS_PER_UNIT is larger than | |
633 | any alignment we'd encounter, so we skip the call to align_fuzz. */ | |
634 | return insn_current_address; | |
635 | dest = JUMP_LABEL (branch); | |
5527bf14 | 636 | |
b9f22704 | 637 | /* BRANCH has no proper alignment chain set, so use SEQ. |
afc6898e BS |
638 | BRANCH also has no INSN_SHUID. */ |
639 | if (INSN_SHUID (seq) < INSN_SHUID (dest)) | |
fc470718 | 640 | { |
f5d927c0 | 641 | /* Forward branch. */ |
fc470718 | 642 | return (insn_last_address + insn_lengths[seq_uid] |
26024475 | 643 | - align_fuzz (seq, dest, length_unit_log, ~0)); |
fc470718 R |
644 | } |
645 | else | |
646 | { | |
f5d927c0 | 647 | /* Backward branch. */ |
fc470718 | 648 | return (insn_current_address |
923f7cf9 | 649 | + align_fuzz (dest, seq, length_unit_log, ~0)); |
fc470718 R |
650 | } |
651 | } | |
652 | #endif /* HAVE_ATTR_length */ | |
653 | \f | |
247a370b | 654 | void |
6cf9ac28 | 655 | compute_alignments (void) |
247a370b | 656 | { |
247a370b | 657 | int log, max_skip, max_log; |
e0082a72 | 658 | basic_block bb; |
247a370b JH |
659 | |
660 | if (label_align) | |
661 | { | |
662 | free (label_align); | |
663 | label_align = 0; | |
664 | } | |
665 | ||
666 | max_labelno = max_label_num (); | |
667 | min_labelno = get_first_label_num (); | |
703ad42b KG |
668 | label_align = xcalloc (max_labelno - min_labelno + 1, |
669 | sizeof (struct label_alignment)); | |
247a370b JH |
670 | |
671 | /* If not optimizing or optimizing for size, don't assign any alignments. */ | |
ba712955 | 672 | if (! optimize || optimize_size) |
247a370b JH |
673 | return; |
674 | ||
e0082a72 | 675 | FOR_EACH_BB (bb) |
247a370b | 676 | { |
a813c111 | 677 | rtx label = BB_HEAD (bb); |
247a370b JH |
678 | int fallthru_frequency = 0, branch_frequency = 0, has_fallthru = 0; |
679 | edge e; | |
680 | ||
66b4e478 JH |
681 | if (GET_CODE (label) != CODE_LABEL |
682 | || probably_never_executed_bb_p (bb)) | |
247a370b JH |
683 | continue; |
684 | max_log = LABEL_ALIGN (label); | |
685 | max_skip = LABEL_ALIGN_MAX_SKIP; | |
686 | ||
687 | for (e = bb->pred; e; e = e->pred_next) | |
688 | { | |
689 | if (e->flags & EDGE_FALLTHRU) | |
690 | has_fallthru = 1, fallthru_frequency += EDGE_FREQUENCY (e); | |
691 | else | |
692 | branch_frequency += EDGE_FREQUENCY (e); | |
693 | } | |
694 | ||
f63d1bf7 | 695 | /* There are two purposes to align block with no fallthru incoming edge: |
247a370b | 696 | 1) to avoid fetch stalls when branch destination is near cache boundary |
d6a7951f | 697 | 2) to improve cache efficiency in case the previous block is not executed |
247a370b JH |
698 | (so it does not need to be in the cache). |
699 | ||
700 | We to catch first case, we align frequently executed blocks. | |
701 | To catch the second, we align blocks that are executed more frequently | |
eaec9b3d | 702 | than the predecessor and the predecessor is likely to not be executed |
247a370b JH |
703 | when function is called. */ |
704 | ||
705 | if (!has_fallthru | |
706 | && (branch_frequency > BB_FREQ_MAX / 10 | |
f6366fc7 ZD |
707 | || (bb->frequency > bb->prev_bb->frequency * 10 |
708 | && (bb->prev_bb->frequency | |
247a370b JH |
709 | <= ENTRY_BLOCK_PTR->frequency / 2)))) |
710 | { | |
711 | log = JUMP_ALIGN (label); | |
712 | if (max_log < log) | |
713 | { | |
714 | max_log = log; | |
715 | max_skip = JUMP_ALIGN_MAX_SKIP; | |
716 | } | |
717 | } | |
718 | /* In case block is frequent and reached mostly by non-fallthru edge, | |
09da1532 | 719 | align it. It is most likely a first block of loop. */ |
247a370b | 720 | if (has_fallthru |
66b4e478 | 721 | && maybe_hot_bb_p (bb) |
247a370b | 722 | && branch_frequency + fallthru_frequency > BB_FREQ_MAX / 10 |
1877be45 | 723 | && branch_frequency > fallthru_frequency * 2) |
247a370b JH |
724 | { |
725 | log = LOOP_ALIGN (label); | |
726 | if (max_log < log) | |
727 | { | |
728 | max_log = log; | |
729 | max_skip = LOOP_ALIGN_MAX_SKIP; | |
730 | } | |
731 | } | |
732 | LABEL_TO_ALIGNMENT (label) = max_log; | |
733 | LABEL_TO_MAX_SKIP (label) = max_skip; | |
734 | } | |
735 | } | |
736 | \f | |
3cf2715d DE |
737 | /* Make a pass over all insns and compute their actual lengths by shortening |
738 | any branches of variable length if possible. */ | |
739 | ||
fc470718 R |
740 | /* shorten_branches might be called multiple times: for example, the SH |
741 | port splits out-of-range conditional branches in MACHINE_DEPENDENT_REORG. | |
742 | In order to do this, it needs proper length information, which it obtains | |
743 | by calling shorten_branches. This cannot be collapsed with | |
d6a7951f | 744 | shorten_branches itself into a single pass unless we also want to integrate |
fc470718 R |
745 | reorg.c, since the branch splitting exposes new instructions with delay |
746 | slots. */ | |
747 | ||
3cf2715d | 748 | void |
6cf9ac28 | 749 | shorten_branches (rtx first ATTRIBUTE_UNUSED) |
3cf2715d | 750 | { |
3cf2715d | 751 | rtx insn; |
fc470718 R |
752 | int max_uid; |
753 | int i; | |
fc470718 | 754 | int max_log; |
9e423e6d | 755 | int max_skip; |
fc470718 R |
756 | #ifdef HAVE_ATTR_length |
757 | #define MAX_CODE_ALIGN 16 | |
758 | rtx seq; | |
3cf2715d | 759 | int something_changed = 1; |
3cf2715d DE |
760 | char *varying_length; |
761 | rtx body; | |
762 | int uid; | |
fc470718 | 763 | rtx align_tab[MAX_CODE_ALIGN]; |
3cf2715d | 764 | |
fc470718 | 765 | #endif |
3d14e82f | 766 | |
3446405d JH |
767 | /* Compute maximum UID and allocate label_align / uid_shuid. */ |
768 | max_uid = get_max_uid (); | |
d9b6874b | 769 | |
07a1f795 AP |
770 | /* Free uid_shuid before reallocating it. */ |
771 | free (uid_shuid); | |
772 | ||
703ad42b | 773 | uid_shuid = xmalloc (max_uid * sizeof *uid_shuid); |
25e22dc0 | 774 | |
247a370b JH |
775 | if (max_labelno != max_label_num ()) |
776 | { | |
777 | int old = max_labelno; | |
778 | int n_labels; | |
779 | int n_old_labels; | |
780 | ||
781 | max_labelno = max_label_num (); | |
782 | ||
783 | n_labels = max_labelno - min_labelno + 1; | |
784 | n_old_labels = old - min_labelno + 1; | |
785 | ||
703ad42b KG |
786 | label_align = xrealloc (label_align, |
787 | n_labels * sizeof (struct label_alignment)); | |
247a370b JH |
788 | |
789 | /* Range of labels grows monotonically in the function. Abort here | |
790 | means that the initialization of array got lost. */ | |
791 | if (n_old_labels > n_labels) | |
792 | abort (); | |
793 | ||
794 | memset (label_align + n_old_labels, 0, | |
795 | (n_labels - n_old_labels) * sizeof (struct label_alignment)); | |
796 | } | |
797 | ||
fc470718 R |
798 | /* Initialize label_align and set up uid_shuid to be strictly |
799 | monotonically rising with insn order. */ | |
e2faec75 R |
800 | /* We use max_log here to keep track of the maximum alignment we want to |
801 | impose on the next CODE_LABEL (or the current one if we are processing | |
802 | the CODE_LABEL itself). */ | |
f5d927c0 | 803 | |
9e423e6d JW |
804 | max_log = 0; |
805 | max_skip = 0; | |
806 | ||
807 | for (insn = get_insns (), i = 1; insn; insn = NEXT_INSN (insn)) | |
fc470718 R |
808 | { |
809 | int log; | |
810 | ||
811 | INSN_SHUID (insn) = i++; | |
2c3c49de | 812 | if (INSN_P (insn)) |
e2faec75 R |
813 | { |
814 | /* reorg might make the first insn of a loop being run once only, | |
815 | and delete the label in front of it. Then we want to apply | |
816 | the loop alignment to the new label created by reorg, which | |
817 | is separated by the former loop start insn from the | |
818 | NOTE_INSN_LOOP_BEG. */ | |
819 | } | |
fc470718 R |
820 | else if (GET_CODE (insn) == CODE_LABEL) |
821 | { | |
822 | rtx next; | |
ff81832f | 823 | |
247a370b JH |
824 | /* Merge in alignments computed by compute_alignments. */ |
825 | log = LABEL_TO_ALIGNMENT (insn); | |
826 | if (max_log < log) | |
827 | { | |
828 | max_log = log; | |
829 | max_skip = LABEL_TO_MAX_SKIP (insn); | |
830 | } | |
fc470718 R |
831 | |
832 | log = LABEL_ALIGN (insn); | |
833 | if (max_log < log) | |
9e423e6d JW |
834 | { |
835 | max_log = log; | |
836 | max_skip = LABEL_ALIGN_MAX_SKIP; | |
837 | } | |
fc470718 | 838 | next = NEXT_INSN (insn); |
75197b37 BS |
839 | /* ADDR_VECs only take room if read-only data goes into the text |
840 | section. */ | |
d48bc59a | 841 | if (JUMP_TABLES_IN_TEXT_SECTION || !HAVE_READONLY_DATA_SECTION) |
75197b37 BS |
842 | if (next && GET_CODE (next) == JUMP_INSN) |
843 | { | |
844 | rtx nextbody = PATTERN (next); | |
845 | if (GET_CODE (nextbody) == ADDR_VEC | |
846 | || GET_CODE (nextbody) == ADDR_DIFF_VEC) | |
847 | { | |
848 | log = ADDR_VEC_ALIGN (next); | |
849 | if (max_log < log) | |
850 | { | |
851 | max_log = log; | |
852 | max_skip = LABEL_ALIGN_MAX_SKIP; | |
853 | } | |
854 | } | |
855 | } | |
fc470718 | 856 | LABEL_TO_ALIGNMENT (insn) = max_log; |
9e423e6d | 857 | LABEL_TO_MAX_SKIP (insn) = max_skip; |
fc470718 | 858 | max_log = 0; |
9e423e6d | 859 | max_skip = 0; |
fc470718 R |
860 | } |
861 | else if (GET_CODE (insn) == BARRIER) | |
862 | { | |
863 | rtx label; | |
864 | ||
2c3c49de | 865 | for (label = insn; label && ! INSN_P (label); |
fc470718 R |
866 | label = NEXT_INSN (label)) |
867 | if (GET_CODE (label) == CODE_LABEL) | |
868 | { | |
869 | log = LABEL_ALIGN_AFTER_BARRIER (insn); | |
870 | if (max_log < log) | |
9e423e6d JW |
871 | { |
872 | max_log = log; | |
873 | max_skip = LABEL_ALIGN_AFTER_BARRIER_MAX_SKIP; | |
874 | } | |
fc470718 R |
875 | break; |
876 | } | |
877 | } | |
fc470718 R |
878 | } |
879 | #ifdef HAVE_ATTR_length | |
880 | ||
881 | /* Allocate the rest of the arrays. */ | |
703ad42b | 882 | insn_lengths = xmalloc (max_uid * sizeof (*insn_lengths)); |
ea3cbda5 | 883 | insn_lengths_max_uid = max_uid; |
af035616 R |
884 | /* Syntax errors can lead to labels being outside of the main insn stream. |
885 | Initialize insn_addresses, so that we get reproducible results. */ | |
9d98a694 | 886 | INSN_ADDRESSES_ALLOC (max_uid); |
fc470718 | 887 | |
703ad42b | 888 | varying_length = xcalloc (max_uid, sizeof (char)); |
fc470718 R |
889 | |
890 | /* Initialize uid_align. We scan instructions | |
891 | from end to start, and keep in align_tab[n] the last seen insn | |
892 | that does an alignment of at least n+1, i.e. the successor | |
893 | in the alignment chain for an insn that does / has a known | |
894 | alignment of n. */ | |
703ad42b | 895 | uid_align = xcalloc (max_uid, sizeof *uid_align); |
fc470718 | 896 | |
f5d927c0 | 897 | for (i = MAX_CODE_ALIGN; --i >= 0;) |
fc470718 R |
898 | align_tab[i] = NULL_RTX; |
899 | seq = get_last_insn (); | |
33f7f353 | 900 | for (; seq; seq = PREV_INSN (seq)) |
fc470718 R |
901 | { |
902 | int uid = INSN_UID (seq); | |
903 | int log; | |
fc470718 R |
904 | log = (GET_CODE (seq) == CODE_LABEL ? LABEL_TO_ALIGNMENT (seq) : 0); |
905 | uid_align[uid] = align_tab[0]; | |
fc470718 R |
906 | if (log) |
907 | { | |
908 | /* Found an alignment label. */ | |
909 | uid_align[uid] = align_tab[log]; | |
910 | for (i = log - 1; i >= 0; i--) | |
911 | align_tab[i] = seq; | |
912 | } | |
33f7f353 JR |
913 | } |
914 | #ifdef CASE_VECTOR_SHORTEN_MODE | |
915 | if (optimize) | |
916 | { | |
917 | /* Look for ADDR_DIFF_VECs, and initialize their minimum and maximum | |
918 | label fields. */ | |
919 | ||
920 | int min_shuid = INSN_SHUID (get_insns ()) - 1; | |
921 | int max_shuid = INSN_SHUID (get_last_insn ()) + 1; | |
922 | int rel; | |
923 | ||
924 | for (insn = first; insn != 0; insn = NEXT_INSN (insn)) | |
fc470718 | 925 | { |
33f7f353 JR |
926 | rtx min_lab = NULL_RTX, max_lab = NULL_RTX, pat; |
927 | int len, i, min, max, insn_shuid; | |
928 | int min_align; | |
929 | addr_diff_vec_flags flags; | |
930 | ||
931 | if (GET_CODE (insn) != JUMP_INSN | |
932 | || GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC) | |
933 | continue; | |
934 | pat = PATTERN (insn); | |
935 | len = XVECLEN (pat, 1); | |
936 | if (len <= 0) | |
937 | abort (); | |
938 | min_align = MAX_CODE_ALIGN; | |
939 | for (min = max_shuid, max = min_shuid, i = len - 1; i >= 0; i--) | |
940 | { | |
941 | rtx lab = XEXP (XVECEXP (pat, 1, i), 0); | |
942 | int shuid = INSN_SHUID (lab); | |
943 | if (shuid < min) | |
944 | { | |
945 | min = shuid; | |
946 | min_lab = lab; | |
947 | } | |
948 | if (shuid > max) | |
949 | { | |
950 | max = shuid; | |
951 | max_lab = lab; | |
952 | } | |
953 | if (min_align > LABEL_TO_ALIGNMENT (lab)) | |
954 | min_align = LABEL_TO_ALIGNMENT (lab); | |
955 | } | |
956 | XEXP (pat, 2) = gen_rtx_LABEL_REF (VOIDmode, min_lab); | |
957 | XEXP (pat, 3) = gen_rtx_LABEL_REF (VOIDmode, max_lab); | |
958 | insn_shuid = INSN_SHUID (insn); | |
959 | rel = INSN_SHUID (XEXP (XEXP (pat, 0), 0)); | |
960 | flags.min_align = min_align; | |
961 | flags.base_after_vec = rel > insn_shuid; | |
962 | flags.min_after_vec = min > insn_shuid; | |
963 | flags.max_after_vec = max > insn_shuid; | |
964 | flags.min_after_base = min > rel; | |
965 | flags.max_after_base = max > rel; | |
966 | ADDR_DIFF_VEC_FLAGS (pat) = flags; | |
fc470718 R |
967 | } |
968 | } | |
33f7f353 | 969 | #endif /* CASE_VECTOR_SHORTEN_MODE */ |
3cf2715d | 970 | |
3cf2715d | 971 | /* Compute initial lengths, addresses, and varying flags for each insn. */ |
b816f339 | 972 | for (insn_current_address = 0, insn = first; |
3cf2715d DE |
973 | insn != 0; |
974 | insn_current_address += insn_lengths[uid], insn = NEXT_INSN (insn)) | |
975 | { | |
976 | uid = INSN_UID (insn); | |
fc470718 | 977 | |
3cf2715d | 978 | insn_lengths[uid] = 0; |
fc470718 R |
979 | |
980 | if (GET_CODE (insn) == CODE_LABEL) | |
981 | { | |
982 | int log = LABEL_TO_ALIGNMENT (insn); | |
983 | if (log) | |
984 | { | |
985 | int align = 1 << log; | |
ecb06768 | 986 | int new_address = (insn_current_address + align - 1) & -align; |
fc470718 | 987 | insn_lengths[uid] = new_address - insn_current_address; |
fc470718 R |
988 | } |
989 | } | |
990 | ||
5a09edba | 991 | INSN_ADDRESSES (uid) = insn_current_address + insn_lengths[uid]; |
f5d927c0 | 992 | |
3cf2715d DE |
993 | if (GET_CODE (insn) == NOTE || GET_CODE (insn) == BARRIER |
994 | || GET_CODE (insn) == CODE_LABEL) | |
995 | continue; | |
04da53bd R |
996 | if (INSN_DELETED_P (insn)) |
997 | continue; | |
3cf2715d DE |
998 | |
999 | body = PATTERN (insn); | |
1000 | if (GET_CODE (body) == ADDR_VEC || GET_CODE (body) == ADDR_DIFF_VEC) | |
5a32a90c JR |
1001 | { |
1002 | /* This only takes room if read-only data goes into the text | |
1003 | section. */ | |
d48bc59a | 1004 | if (JUMP_TABLES_IN_TEXT_SECTION || !HAVE_READONLY_DATA_SECTION) |
75197b37 BS |
1005 | insn_lengths[uid] = (XVECLEN (body, |
1006 | GET_CODE (body) == ADDR_DIFF_VEC) | |
1007 | * GET_MODE_SIZE (GET_MODE (body))); | |
5a32a90c | 1008 | /* Alignment is handled by ADDR_VEC_ALIGN. */ |
5a32a90c | 1009 | } |
a30caf5c | 1010 | else if (GET_CODE (body) == ASM_INPUT || asm_noperands (body) >= 0) |
3cf2715d DE |
1011 | insn_lengths[uid] = asm_insn_count (body) * insn_default_length (insn); |
1012 | else if (GET_CODE (body) == SEQUENCE) | |
1013 | { | |
1014 | int i; | |
1015 | int const_delay_slots; | |
1016 | #ifdef DELAY_SLOTS | |
1017 | const_delay_slots = const_num_delay_slots (XVECEXP (body, 0, 0)); | |
1018 | #else | |
1019 | const_delay_slots = 0; | |
1020 | #endif | |
1021 | /* Inside a delay slot sequence, we do not do any branch shortening | |
1022 | if the shortening could change the number of delay slots | |
0f41302f | 1023 | of the branch. */ |
3cf2715d DE |
1024 | for (i = 0; i < XVECLEN (body, 0); i++) |
1025 | { | |
1026 | rtx inner_insn = XVECEXP (body, 0, i); | |
1027 | int inner_uid = INSN_UID (inner_insn); | |
1028 | int inner_length; | |
1029 | ||
a30caf5c DC |
1030 | if (GET_CODE (body) == ASM_INPUT |
1031 | || asm_noperands (PATTERN (XVECEXP (body, 0, i))) >= 0) | |
3cf2715d DE |
1032 | inner_length = (asm_insn_count (PATTERN (inner_insn)) |
1033 | * insn_default_length (inner_insn)); | |
1034 | else | |
1035 | inner_length = insn_default_length (inner_insn); | |
f5d927c0 | 1036 | |
3cf2715d DE |
1037 | insn_lengths[inner_uid] = inner_length; |
1038 | if (const_delay_slots) | |
1039 | { | |
1040 | if ((varying_length[inner_uid] | |
1041 | = insn_variable_length_p (inner_insn)) != 0) | |
1042 | varying_length[uid] = 1; | |
9d98a694 AO |
1043 | INSN_ADDRESSES (inner_uid) = (insn_current_address |
1044 | + insn_lengths[uid]); | |
3cf2715d DE |
1045 | } |
1046 | else | |
1047 | varying_length[inner_uid] = 0; | |
1048 | insn_lengths[uid] += inner_length; | |
1049 | } | |
1050 | } | |
1051 | else if (GET_CODE (body) != USE && GET_CODE (body) != CLOBBER) | |
1052 | { | |
1053 | insn_lengths[uid] = insn_default_length (insn); | |
1054 | varying_length[uid] = insn_variable_length_p (insn); | |
1055 | } | |
1056 | ||
1057 | /* If needed, do any adjustment. */ | |
1058 | #ifdef ADJUST_INSN_LENGTH | |
1059 | ADJUST_INSN_LENGTH (insn, insn_lengths[uid]); | |
04b6000c | 1060 | if (insn_lengths[uid] < 0) |
c725bd79 | 1061 | fatal_insn ("negative insn length", insn); |
3cf2715d DE |
1062 | #endif |
1063 | } | |
1064 | ||
1065 | /* Now loop over all the insns finding varying length insns. For each, | |
1066 | get the current insn length. If it has changed, reflect the change. | |
1067 | When nothing changes for a full pass, we are done. */ | |
1068 | ||
1069 | while (something_changed) | |
1070 | { | |
1071 | something_changed = 0; | |
fc470718 | 1072 | insn_current_align = MAX_CODE_ALIGN - 1; |
b816f339 | 1073 | for (insn_current_address = 0, insn = first; |
3cf2715d DE |
1074 | insn != 0; |
1075 | insn = NEXT_INSN (insn)) | |
1076 | { | |
1077 | int new_length; | |
b729186a | 1078 | #ifdef ADJUST_INSN_LENGTH |
3cf2715d | 1079 | int tmp_length; |
b729186a | 1080 | #endif |
fc470718 | 1081 | int length_align; |
3cf2715d DE |
1082 | |
1083 | uid = INSN_UID (insn); | |
fc470718 R |
1084 | |
1085 | if (GET_CODE (insn) == CODE_LABEL) | |
1086 | { | |
1087 | int log = LABEL_TO_ALIGNMENT (insn); | |
1088 | if (log > insn_current_align) | |
1089 | { | |
1090 | int align = 1 << log; | |
ecb06768 | 1091 | int new_address= (insn_current_address + align - 1) & -align; |
fc470718 R |
1092 | insn_lengths[uid] = new_address - insn_current_address; |
1093 | insn_current_align = log; | |
1094 | insn_current_address = new_address; | |
1095 | } | |
1096 | else | |
1097 | insn_lengths[uid] = 0; | |
9d98a694 | 1098 | INSN_ADDRESSES (uid) = insn_current_address; |
fc470718 R |
1099 | continue; |
1100 | } | |
1101 | ||
1102 | length_align = INSN_LENGTH_ALIGNMENT (insn); | |
1103 | if (length_align < insn_current_align) | |
1104 | insn_current_align = length_align; | |
1105 | ||
9d98a694 AO |
1106 | insn_last_address = INSN_ADDRESSES (uid); |
1107 | INSN_ADDRESSES (uid) = insn_current_address; | |
fc470718 | 1108 | |
5e75ef4a | 1109 | #ifdef CASE_VECTOR_SHORTEN_MODE |
33f7f353 JR |
1110 | if (optimize && GET_CODE (insn) == JUMP_INSN |
1111 | && GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC) | |
1112 | { | |
33f7f353 JR |
1113 | rtx body = PATTERN (insn); |
1114 | int old_length = insn_lengths[uid]; | |
1115 | rtx rel_lab = XEXP (XEXP (body, 0), 0); | |
1116 | rtx min_lab = XEXP (XEXP (body, 2), 0); | |
1117 | rtx max_lab = XEXP (XEXP (body, 3), 0); | |
9d98a694 AO |
1118 | int rel_addr = INSN_ADDRESSES (INSN_UID (rel_lab)); |
1119 | int min_addr = INSN_ADDRESSES (INSN_UID (min_lab)); | |
1120 | int max_addr = INSN_ADDRESSES (INSN_UID (max_lab)); | |
33f7f353 JR |
1121 | rtx prev; |
1122 | int rel_align = 0; | |
950a3816 KG |
1123 | addr_diff_vec_flags flags; |
1124 | ||
1125 | /* Avoid automatic aggregate initialization. */ | |
1126 | flags = ADDR_DIFF_VEC_FLAGS (body); | |
33f7f353 JR |
1127 | |
1128 | /* Try to find a known alignment for rel_lab. */ | |
1129 | for (prev = rel_lab; | |
1130 | prev | |
1131 | && ! insn_lengths[INSN_UID (prev)] | |
1132 | && ! (varying_length[INSN_UID (prev)] & 1); | |
1133 | prev = PREV_INSN (prev)) | |
1134 | if (varying_length[INSN_UID (prev)] & 2) | |
1135 | { | |
1136 | rel_align = LABEL_TO_ALIGNMENT (prev); | |
1137 | break; | |
1138 | } | |
1139 | ||
1140 | /* See the comment on addr_diff_vec_flags in rtl.h for the | |
1141 | meaning of the flags values. base: REL_LAB vec: INSN */ | |
1142 | /* Anything after INSN has still addresses from the last | |
1143 | pass; adjust these so that they reflect our current | |
1144 | estimate for this pass. */ | |
1145 | if (flags.base_after_vec) | |
1146 | rel_addr += insn_current_address - insn_last_address; | |
1147 | if (flags.min_after_vec) | |
1148 | min_addr += insn_current_address - insn_last_address; | |
1149 | if (flags.max_after_vec) | |
1150 | max_addr += insn_current_address - insn_last_address; | |
1151 | /* We want to know the worst case, i.e. lowest possible value | |
1152 | for the offset of MIN_LAB. If MIN_LAB is after REL_LAB, | |
1153 | its offset is positive, and we have to be wary of code shrink; | |
1154 | otherwise, it is negative, and we have to be vary of code | |
1155 | size increase. */ | |
1156 | if (flags.min_after_base) | |
1157 | { | |
1158 | /* If INSN is between REL_LAB and MIN_LAB, the size | |
1159 | changes we are about to make can change the alignment | |
1160 | within the observed offset, therefore we have to break | |
1161 | it up into two parts that are independent. */ | |
1162 | if (! flags.base_after_vec && flags.min_after_vec) | |
1163 | { | |
1164 | min_addr -= align_fuzz (rel_lab, insn, rel_align, 0); | |
1165 | min_addr -= align_fuzz (insn, min_lab, 0, 0); | |
1166 | } | |
1167 | else | |
1168 | min_addr -= align_fuzz (rel_lab, min_lab, rel_align, 0); | |
1169 | } | |
1170 | else | |
1171 | { | |
1172 | if (flags.base_after_vec && ! flags.min_after_vec) | |
1173 | { | |
1174 | min_addr -= align_fuzz (min_lab, insn, 0, ~0); | |
1175 | min_addr -= align_fuzz (insn, rel_lab, 0, ~0); | |
1176 | } | |
1177 | else | |
1178 | min_addr -= align_fuzz (min_lab, rel_lab, 0, ~0); | |
1179 | } | |
1180 | /* Likewise, determine the highest lowest possible value | |
1181 | for the offset of MAX_LAB. */ | |
1182 | if (flags.max_after_base) | |
1183 | { | |
1184 | if (! flags.base_after_vec && flags.max_after_vec) | |
1185 | { | |
1186 | max_addr += align_fuzz (rel_lab, insn, rel_align, ~0); | |
1187 | max_addr += align_fuzz (insn, max_lab, 0, ~0); | |
1188 | } | |
1189 | else | |
1190 | max_addr += align_fuzz (rel_lab, max_lab, rel_align, ~0); | |
1191 | } | |
1192 | else | |
1193 | { | |
1194 | if (flags.base_after_vec && ! flags.max_after_vec) | |
1195 | { | |
1196 | max_addr += align_fuzz (max_lab, insn, 0, 0); | |
1197 | max_addr += align_fuzz (insn, rel_lab, 0, 0); | |
1198 | } | |
1199 | else | |
1200 | max_addr += align_fuzz (max_lab, rel_lab, 0, 0); | |
1201 | } | |
1202 | PUT_MODE (body, CASE_VECTOR_SHORTEN_MODE (min_addr - rel_addr, | |
1203 | max_addr - rel_addr, | |
1204 | body)); | |
d48bc59a | 1205 | if (JUMP_TABLES_IN_TEXT_SECTION || !HAVE_READONLY_DATA_SECTION) |
75197b37 BS |
1206 | { |
1207 | insn_lengths[uid] | |
1208 | = (XVECLEN (body, 1) * GET_MODE_SIZE (GET_MODE (body))); | |
1209 | insn_current_address += insn_lengths[uid]; | |
1210 | if (insn_lengths[uid] != old_length) | |
1211 | something_changed = 1; | |
1212 | } | |
1213 | ||
33f7f353 | 1214 | continue; |
33f7f353 | 1215 | } |
5e75ef4a JL |
1216 | #endif /* CASE_VECTOR_SHORTEN_MODE */ |
1217 | ||
1218 | if (! (varying_length[uid])) | |
3cf2715d | 1219 | { |
674fc07d GS |
1220 | if (GET_CODE (insn) == INSN |
1221 | && GET_CODE (PATTERN (insn)) == SEQUENCE) | |
1222 | { | |
1223 | int i; | |
1224 | ||
1225 | body = PATTERN (insn); | |
1226 | for (i = 0; i < XVECLEN (body, 0); i++) | |
1227 | { | |
1228 | rtx inner_insn = XVECEXP (body, 0, i); | |
1229 | int inner_uid = INSN_UID (inner_insn); | |
1230 | ||
1231 | INSN_ADDRESSES (inner_uid) = insn_current_address; | |
1232 | ||
1233 | insn_current_address += insn_lengths[inner_uid]; | |
1234 | } | |
dd3f0101 | 1235 | } |
674fc07d GS |
1236 | else |
1237 | insn_current_address += insn_lengths[uid]; | |
1238 | ||
3cf2715d DE |
1239 | continue; |
1240 | } | |
674fc07d | 1241 | |
3cf2715d DE |
1242 | if (GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SEQUENCE) |
1243 | { | |
1244 | int i; | |
f5d927c0 | 1245 | |
3cf2715d DE |
1246 | body = PATTERN (insn); |
1247 | new_length = 0; | |
1248 | for (i = 0; i < XVECLEN (body, 0); i++) | |
1249 | { | |
1250 | rtx inner_insn = XVECEXP (body, 0, i); | |
1251 | int inner_uid = INSN_UID (inner_insn); | |
1252 | int inner_length; | |
1253 | ||
9d98a694 | 1254 | INSN_ADDRESSES (inner_uid) = insn_current_address; |
3cf2715d DE |
1255 | |
1256 | /* insn_current_length returns 0 for insns with a | |
1257 | non-varying length. */ | |
1258 | if (! varying_length[inner_uid]) | |
1259 | inner_length = insn_lengths[inner_uid]; | |
1260 | else | |
1261 | inner_length = insn_current_length (inner_insn); | |
1262 | ||
1263 | if (inner_length != insn_lengths[inner_uid]) | |
1264 | { | |
1265 | insn_lengths[inner_uid] = inner_length; | |
1266 | something_changed = 1; | |
1267 | } | |
1268 | insn_current_address += insn_lengths[inner_uid]; | |
1269 | new_length += inner_length; | |
1270 | } | |
1271 | } | |
1272 | else | |
1273 | { | |
1274 | new_length = insn_current_length (insn); | |
1275 | insn_current_address += new_length; | |
1276 | } | |
1277 | ||
3cf2715d DE |
1278 | #ifdef ADJUST_INSN_LENGTH |
1279 | /* If needed, do any adjustment. */ | |
1280 | tmp_length = new_length; | |
1281 | ADJUST_INSN_LENGTH (insn, new_length); | |
1282 | insn_current_address += (new_length - tmp_length); | |
3cf2715d DE |
1283 | #endif |
1284 | ||
1285 | if (new_length != insn_lengths[uid]) | |
1286 | { | |
1287 | insn_lengths[uid] = new_length; | |
1288 | something_changed = 1; | |
1289 | } | |
1290 | } | |
bb4aaf18 TG |
1291 | /* For a non-optimizing compile, do only a single pass. */ |
1292 | if (!optimize) | |
1293 | break; | |
3cf2715d | 1294 | } |
fc470718 R |
1295 | |
1296 | free (varying_length); | |
1297 | ||
3cf2715d DE |
1298 | #endif /* HAVE_ATTR_length */ |
1299 | } | |
1300 | ||
1301 | #ifdef HAVE_ATTR_length | |
1302 | /* Given the body of an INSN known to be generated by an ASM statement, return | |
1303 | the number of machine instructions likely to be generated for this insn. | |
1304 | This is used to compute its length. */ | |
1305 | ||
1306 | static int | |
6cf9ac28 | 1307 | asm_insn_count (rtx body) |
3cf2715d | 1308 | { |
3cce094d | 1309 | const char *template; |
3cf2715d DE |
1310 | int count = 1; |
1311 | ||
5d0930ea DE |
1312 | if (GET_CODE (body) == ASM_INPUT) |
1313 | template = XSTR (body, 0); | |
1314 | else | |
df4ae160 | 1315 | template = decode_asm_operands (body, NULL, NULL, NULL, NULL); |
5d0930ea | 1316 | |
f5d927c0 KH |
1317 | for (; *template; template++) |
1318 | if (IS_ASM_LOGICAL_LINE_SEPARATOR (*template) || *template == '\n') | |
3cf2715d DE |
1319 | count++; |
1320 | ||
1321 | return count; | |
1322 | } | |
1323 | #endif | |
1324 | \f | |
1325 | /* Output assembler code for the start of a function, | |
1326 | and initialize some of the variables in this file | |
1327 | for the new function. The label for the function and associated | |
1328 | assembler pseudo-ops have already been output in `assemble_start_function'. | |
1329 | ||
1330 | FIRST is the first insn of the rtl for the function being compiled. | |
1331 | FILE is the file to write assembler code to. | |
1332 | OPTIMIZE is nonzero if we should eliminate redundant | |
1333 | test and compare insns. */ | |
1334 | ||
1335 | void | |
6cf9ac28 AJ |
1336 | final_start_function (rtx first ATTRIBUTE_UNUSED, FILE *file, |
1337 | int optimize ATTRIBUTE_UNUSED) | |
3cf2715d DE |
1338 | { |
1339 | block_depth = 0; | |
1340 | ||
1341 | this_is_asm_operands = 0; | |
1342 | ||
9ae130f8 JH |
1343 | last_filename = locator_file (prologue_locator); |
1344 | last_linenum = locator_line (prologue_locator); | |
1345 | ||
653e276c | 1346 | high_block_linenum = high_function_linenum = last_linenum; |
eac40081 | 1347 | |
653e276c | 1348 | (*debug_hooks->begin_prologue) (last_linenum, last_filename); |
d291dd49 | 1349 | |
653e276c | 1350 | #if defined (DWARF2_UNWIND_INFO) || defined (IA64_UNWIND_INFO) |
7a0c8d71 | 1351 | if (write_symbols != DWARF2_DEBUG && write_symbols != VMS_AND_DWARF2_DEBUG) |
653e276c | 1352 | dwarf2out_begin_prologue (0, NULL); |
f5d927c0 | 1353 | #endif |
3cf2715d DE |
1354 | |
1355 | #ifdef LEAF_REG_REMAP | |
54ff41b7 | 1356 | if (current_function_uses_only_leaf_regs) |
3cf2715d DE |
1357 | leaf_renumber_regs (first); |
1358 | #endif | |
1359 | ||
1360 | /* The Sun386i and perhaps other machines don't work right | |
1361 | if the profiling code comes after the prologue. */ | |
1362 | #ifdef PROFILE_BEFORE_PROLOGUE | |
70f4f91c | 1363 | if (current_function_profile) |
3cf2715d DE |
1364 | profile_function (file); |
1365 | #endif /* PROFILE_BEFORE_PROLOGUE */ | |
1366 | ||
0021b564 JM |
1367 | #if defined (DWARF2_UNWIND_INFO) && defined (HAVE_prologue) |
1368 | if (dwarf2out_do_frame ()) | |
1369 | dwarf2out_frame_debug (NULL_RTX); | |
1370 | #endif | |
1371 | ||
18c038b9 MM |
1372 | /* If debugging, assign block numbers to all of the blocks in this |
1373 | function. */ | |
1374 | if (write_symbols) | |
1375 | { | |
3ac79482 | 1376 | remove_unnecessary_notes (); |
0435312e | 1377 | reemit_insn_block_notes (); |
a20612aa | 1378 | number_blocks (current_function_decl); |
18c038b9 MM |
1379 | /* We never actually put out begin/end notes for the top-level |
1380 | block in the function. But, conceptually, that block is | |
1381 | always needed. */ | |
1382 | TREE_ASM_WRITTEN (DECL_INITIAL (current_function_decl)) = 1; | |
1383 | } | |
1384 | ||
3cf2715d | 1385 | /* First output the function prologue: code to set up the stack frame. */ |
5fd9b178 | 1386 | targetm.asm_out.function_prologue (file, get_frame_size ()); |
3cf2715d | 1387 | |
3cf2715d DE |
1388 | /* If the machine represents the prologue as RTL, the profiling code must |
1389 | be emitted when NOTE_INSN_PROLOGUE_END is scanned. */ | |
1390 | #ifdef HAVE_prologue | |
1391 | if (! HAVE_prologue) | |
1392 | #endif | |
1393 | profile_after_prologue (file); | |
3cf2715d DE |
1394 | } |
1395 | ||
1396 | static void | |
6cf9ac28 | 1397 | profile_after_prologue (FILE *file ATTRIBUTE_UNUSED) |
3cf2715d | 1398 | { |
3cf2715d | 1399 | #ifndef PROFILE_BEFORE_PROLOGUE |
70f4f91c | 1400 | if (current_function_profile) |
3cf2715d DE |
1401 | profile_function (file); |
1402 | #endif /* not PROFILE_BEFORE_PROLOGUE */ | |
1403 | } | |
1404 | ||
1405 | static void | |
6cf9ac28 | 1406 | profile_function (FILE *file ATTRIBUTE_UNUSED) |
3cf2715d | 1407 | { |
dcacfa04 | 1408 | #ifndef NO_PROFILE_COUNTERS |
9739c90c | 1409 | # define NO_PROFILE_COUNTERS 0 |
dcacfa04 | 1410 | #endif |
b729186a | 1411 | #if defined(ASM_OUTPUT_REG_PUSH) |
3cf2715d | 1412 | int sval = current_function_returns_struct; |
61f71b34 | 1413 | rtx svrtx = targetm.calls.struct_value_rtx (TREE_TYPE (current_function_decl), 1); |
b729186a | 1414 | #if defined(STATIC_CHAIN_INCOMING_REGNUM) || defined(STATIC_CHAIN_REGNUM) |
6de9cd9a | 1415 | int cxt = cfun->static_chain_decl != NULL; |
b729186a JL |
1416 | #endif |
1417 | #endif /* ASM_OUTPUT_REG_PUSH */ | |
3cf2715d | 1418 | |
9739c90c JJ |
1419 | if (! NO_PROFILE_COUNTERS) |
1420 | { | |
1421 | int align = MIN (BIGGEST_ALIGNMENT, LONG_TYPE_SIZE); | |
1422 | data_section (); | |
1423 | ASM_OUTPUT_ALIGN (file, floor_log2 (align / BITS_PER_UNIT)); | |
5fd9b178 | 1424 | targetm.asm_out.internal_label (file, "LP", current_function_funcdef_no); |
9739c90c JJ |
1425 | assemble_integer (const0_rtx, LONG_TYPE_SIZE / BITS_PER_UNIT, align, 1); |
1426 | } | |
3cf2715d | 1427 | |
499df339 | 1428 | function_section (current_function_decl); |
3cf2715d | 1429 | |
61f71b34 | 1430 | #if defined(ASM_OUTPUT_REG_PUSH) |
f8cfc6aa | 1431 | if (sval && svrtx != NULL_RTX && REG_P (svrtx)) |
61f71b34 | 1432 | ASM_OUTPUT_REG_PUSH (file, REGNO (svrtx)); |
3cf2715d DE |
1433 | #endif |
1434 | ||
65ed39df | 1435 | #if defined(STATIC_CHAIN_INCOMING_REGNUM) && defined(ASM_OUTPUT_REG_PUSH) |
3cf2715d DE |
1436 | if (cxt) |
1437 | ASM_OUTPUT_REG_PUSH (file, STATIC_CHAIN_INCOMING_REGNUM); | |
1438 | #else | |
65ed39df | 1439 | #if defined(STATIC_CHAIN_REGNUM) && defined(ASM_OUTPUT_REG_PUSH) |
3cf2715d | 1440 | if (cxt) |
51723711 KG |
1441 | { |
1442 | ASM_OUTPUT_REG_PUSH (file, STATIC_CHAIN_REGNUM); | |
1443 | } | |
3cf2715d DE |
1444 | #endif |
1445 | #endif | |
3cf2715d | 1446 | |
df696a75 | 1447 | FUNCTION_PROFILER (file, current_function_funcdef_no); |
3cf2715d | 1448 | |
65ed39df | 1449 | #if defined(STATIC_CHAIN_INCOMING_REGNUM) && defined(ASM_OUTPUT_REG_PUSH) |
3cf2715d DE |
1450 | if (cxt) |
1451 | ASM_OUTPUT_REG_POP (file, STATIC_CHAIN_INCOMING_REGNUM); | |
1452 | #else | |
65ed39df | 1453 | #if defined(STATIC_CHAIN_REGNUM) && defined(ASM_OUTPUT_REG_PUSH) |
3cf2715d | 1454 | if (cxt) |
51723711 KG |
1455 | { |
1456 | ASM_OUTPUT_REG_POP (file, STATIC_CHAIN_REGNUM); | |
1457 | } | |
3cf2715d DE |
1458 | #endif |
1459 | #endif | |
3cf2715d | 1460 | |
61f71b34 | 1461 | #if defined(ASM_OUTPUT_REG_PUSH) |
f8cfc6aa | 1462 | if (sval && svrtx != NULL_RTX && REG_P (svrtx)) |
61f71b34 | 1463 | ASM_OUTPUT_REG_POP (file, REGNO (svrtx)); |
3cf2715d DE |
1464 | #endif |
1465 | } | |
1466 | ||
1467 | /* Output assembler code for the end of a function. | |
1468 | For clarity, args are same as those of `final_start_function' | |
1469 | even though not all of them are needed. */ | |
1470 | ||
1471 | void | |
6cf9ac28 | 1472 | final_end_function (void) |
3cf2715d | 1473 | { |
be1bb652 | 1474 | app_disable (); |
3cf2715d | 1475 | |
e2a12aca | 1476 | (*debug_hooks->end_function) (high_function_linenum); |
3cf2715d | 1477 | |
3cf2715d DE |
1478 | /* Finally, output the function epilogue: |
1479 | code to restore the stack frame and return to the caller. */ | |
5fd9b178 | 1480 | targetm.asm_out.function_epilogue (asm_out_file, get_frame_size ()); |
3cf2715d | 1481 | |
e2a12aca | 1482 | /* And debug output. */ |
702ada3d | 1483 | (*debug_hooks->end_epilogue) (last_linenum, last_filename); |
3cf2715d | 1484 | |
e2a12aca | 1485 | #if defined (DWARF2_UNWIND_INFO) |
7a0c8d71 DR |
1486 | if (write_symbols != DWARF2_DEBUG && write_symbols != VMS_AND_DWARF2_DEBUG |
1487 | && dwarf2out_do_frame ()) | |
702ada3d | 1488 | dwarf2out_end_epilogue (last_linenum, last_filename); |
9a666dda | 1489 | #endif |
3cf2715d DE |
1490 | } |
1491 | \f | |
3cf2715d DE |
1492 | /* Output assembler code for some insns: all or part of a function. |
1493 | For description of args, see `final_start_function', above. | |
1494 | ||
1495 | PRESCAN is 1 if we are not really outputting, | |
1496 | just scanning as if we were outputting. | |
1497 | Prescanning deletes and rearranges insns just like ordinary output. | |
1498 | PRESCAN is -2 if we are outputting after having prescanned. | |
1499 | In this case, don't try to delete or rearrange insns | |
1500 | because that has already been done. | |
1501 | Prescanning is done only on certain machines. */ | |
1502 | ||
1503 | void | |
6cf9ac28 | 1504 | final (rtx first, FILE *file, int optimize, int prescan) |
3cf2715d | 1505 | { |
b3694847 | 1506 | rtx insn; |
a8c3510c | 1507 | int max_uid = 0; |
589fe865 | 1508 | int seen = 0; |
3cf2715d DE |
1509 | |
1510 | last_ignored_compare = 0; | |
3cf2715d | 1511 | |
589fe865 DJ |
1512 | #ifdef SDB_DEBUGGING_INFO |
1513 | /* When producing SDB debugging info, delete troublesome line number | |
3cf2715d DE |
1514 | notes from inlined functions in other files as well as duplicate |
1515 | line number notes. */ | |
3cf2715d DE |
1516 | if (write_symbols == SDB_DEBUG) |
1517 | { | |
1518 | rtx last = 0; | |
1519 | for (insn = first; insn; insn = NEXT_INSN (insn)) | |
1520 | if (GET_CODE (insn) == NOTE && NOTE_LINE_NUMBER (insn) > 0) | |
1521 | { | |
6de9cd9a | 1522 | if (last != 0 |
6773e15f PB |
1523 | #ifdef USE_MAPPED_LOCATION |
1524 | && NOTE_SOURCE_LOCATION (insn) == NOTE_SOURCE_LOCATION (last) | |
1525 | #else | |
6de9cd9a | 1526 | && NOTE_LINE_NUMBER (insn) == NOTE_LINE_NUMBER (last) |
6773e15f | 1527 | && NOTE_SOURCE_FILE (insn) == NOTE_SOURCE_FILE (last) |
d70dc103 | 1528 | #endif |
6773e15f | 1529 | ) |
3cf2715d | 1530 | { |
2e106602 | 1531 | delete_insn (insn); /* Use delete_note. */ |
3cf2715d DE |
1532 | continue; |
1533 | } | |
1534 | last = insn; | |
3cf2715d DE |
1535 | } |
1536 | } | |
3cf2715d | 1537 | #endif |
3cf2715d DE |
1538 | |
1539 | for (insn = first; insn; insn = NEXT_INSN (insn)) | |
a8c3510c | 1540 | { |
938d968e | 1541 | if (INSN_UID (insn) > max_uid) /* Find largest UID. */ |
f5d927c0 | 1542 | max_uid = INSN_UID (insn); |
9ef4c6ef JC |
1543 | #ifdef HAVE_cc0 |
1544 | /* If CC tracking across branches is enabled, record the insn which | |
1545 | jumps to each branch only reached from one place. */ | |
7ad7f828 | 1546 | if (optimize && GET_CODE (insn) == JUMP_INSN) |
9ef4c6ef JC |
1547 | { |
1548 | rtx lab = JUMP_LABEL (insn); | |
1549 | if (lab && LABEL_NUSES (lab) == 1) | |
1550 | { | |
1551 | LABEL_REFS (lab) = insn; | |
1552 | } | |
1553 | } | |
1554 | #endif | |
a8c3510c AM |
1555 | } |
1556 | ||
3cf2715d DE |
1557 | init_recog (); |
1558 | ||
1559 | CC_STATUS_INIT; | |
1560 | ||
1561 | /* Output the insns. */ | |
1562 | for (insn = NEXT_INSN (first); insn;) | |
2f16edb1 TG |
1563 | { |
1564 | #ifdef HAVE_ATTR_length | |
b9f22704 | 1565 | if ((unsigned) INSN_UID (insn) >= INSN_ADDRESSES_SIZE ()) |
0ac76ad9 | 1566 | { |
0ac76ad9 RH |
1567 | /* This can be triggered by bugs elsewhere in the compiler if |
1568 | new insns are created after init_insn_lengths is called. */ | |
0acb0203 JH |
1569 | if (GET_CODE (insn) == NOTE) |
1570 | insn_current_address = -1; | |
1571 | else | |
1572 | abort (); | |
0ac76ad9 RH |
1573 | } |
1574 | else | |
9d98a694 | 1575 | insn_current_address = INSN_ADDRESSES (INSN_UID (insn)); |
0ac76ad9 RH |
1576 | #endif /* HAVE_ATTR_length */ |
1577 | ||
589fe865 | 1578 | insn = final_scan_insn (insn, file, optimize, prescan, 0, &seen); |
2f16edb1 | 1579 | } |
3cf2715d DE |
1580 | } |
1581 | \f | |
4bbf910e | 1582 | const char * |
6cf9ac28 | 1583 | get_insn_template (int code, rtx insn) |
4bbf910e | 1584 | { |
4bbf910e RH |
1585 | switch (insn_data[code].output_format) |
1586 | { | |
1587 | case INSN_OUTPUT_FORMAT_SINGLE: | |
3897f229 | 1588 | return insn_data[code].output.single; |
4bbf910e | 1589 | case INSN_OUTPUT_FORMAT_MULTI: |
3897f229 | 1590 | return insn_data[code].output.multi[which_alternative]; |
4bbf910e RH |
1591 | case INSN_OUTPUT_FORMAT_FUNCTION: |
1592 | if (insn == NULL) | |
1593 | abort (); | |
3897f229 | 1594 | return (*insn_data[code].output.function) (recog_data.operand, insn); |
4bbf910e RH |
1595 | |
1596 | default: | |
1597 | abort (); | |
1598 | } | |
1599 | } | |
f5d927c0 | 1600 | |
0dc36574 ZW |
1601 | /* Emit the appropriate declaration for an alternate-entry-point |
1602 | symbol represented by INSN, to FILE. INSN is a CODE_LABEL with | |
1603 | LABEL_KIND != LABEL_NORMAL. | |
1604 | ||
1605 | The case fall-through in this function is intentional. */ | |
1606 | static void | |
6cf9ac28 | 1607 | output_alternate_entry_point (FILE *file, rtx insn) |
0dc36574 ZW |
1608 | { |
1609 | const char *name = LABEL_NAME (insn); | |
1610 | ||
1611 | switch (LABEL_KIND (insn)) | |
1612 | { | |
1613 | case LABEL_WEAK_ENTRY: | |
1614 | #ifdef ASM_WEAKEN_LABEL | |
1615 | ASM_WEAKEN_LABEL (file, name); | |
1616 | #endif | |
1617 | case LABEL_GLOBAL_ENTRY: | |
5fd9b178 | 1618 | targetm.asm_out.globalize_label (file, name); |
0dc36574 | 1619 | case LABEL_STATIC_ENTRY: |
905173eb ZW |
1620 | #ifdef ASM_OUTPUT_TYPE_DIRECTIVE |
1621 | ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function"); | |
1622 | #endif | |
0dc36574 ZW |
1623 | ASM_OUTPUT_LABEL (file, name); |
1624 | break; | |
1625 | ||
1626 | case LABEL_NORMAL: | |
1627 | default: | |
1628 | abort (); | |
1629 | } | |
1630 | } | |
1631 | ||
750054a2 CT |
1632 | /* Return boolean indicating if there is a NOTE_INSN_UNLIKELY_EXECUTED_CODE |
1633 | note in the instruction chain (going forward) between the current | |
1634 | instruction, and the next 'executable' instruction. */ | |
1635 | ||
1636 | bool | |
1637 | scan_ahead_for_unlikely_executed_note (rtx insn) | |
1638 | { | |
1639 | rtx temp; | |
1640 | int bb_note_count = 0; | |
1641 | ||
1642 | for (temp = insn; temp; temp = NEXT_INSN (temp)) | |
1643 | { | |
1644 | if (GET_CODE (temp) == NOTE | |
1645 | && NOTE_LINE_NUMBER (temp) == NOTE_INSN_UNLIKELY_EXECUTED_CODE) | |
1646 | return true; | |
1647 | if (GET_CODE (temp) == NOTE | |
1648 | && NOTE_LINE_NUMBER (temp) == NOTE_INSN_BASIC_BLOCK) | |
1649 | { | |
1650 | bb_note_count++; | |
1651 | if (bb_note_count > 1) | |
1652 | return false; | |
1653 | } | |
1654 | if (INSN_P (temp)) | |
1655 | return false; | |
1656 | } | |
1657 | ||
1658 | return false; | |
1659 | } | |
1660 | ||
3cf2715d DE |
1661 | /* The final scan for one insn, INSN. |
1662 | Args are same as in `final', except that INSN | |
1663 | is the insn being scanned. | |
1664 | Value returned is the next insn to be scanned. | |
1665 | ||
1666 | NOPEEPHOLES is the flag to disallow peephole processing (currently | |
589fe865 | 1667 | used for within delayed branch sequence output). |
3cf2715d | 1668 | |
589fe865 DJ |
1669 | SEEN is used to track the end of the prologue, for emitting |
1670 | debug information. We force the emission of a line note after | |
1671 | both NOTE_INSN_PROLOGUE_END and NOTE_INSN_FUNCTION_BEG, or | |
1672 | at the beginning of the second basic block, whichever comes | |
1673 | first. */ | |
1674 | ||
5cfc5f84 | 1675 | rtx |
6cf9ac28 | 1676 | final_scan_insn (rtx insn, FILE *file, int optimize ATTRIBUTE_UNUSED, |
589fe865 DJ |
1677 | int prescan, int nopeepholes ATTRIBUTE_UNUSED, |
1678 | int *seen) | |
3cf2715d | 1679 | { |
90ca38bb MM |
1680 | #ifdef HAVE_cc0 |
1681 | rtx set; | |
1682 | #endif | |
1683 | ||
3cf2715d DE |
1684 | insn_counter++; |
1685 | ||
1686 | /* Ignore deleted insns. These can occur when we split insns (due to a | |
1687 | template of "#") while not optimizing. */ | |
1688 | if (INSN_DELETED_P (insn)) | |
1689 | return NEXT_INSN (insn); | |
1690 | ||
1691 | switch (GET_CODE (insn)) | |
1692 | { | |
1693 | case NOTE: | |
1694 | if (prescan > 0) | |
1695 | break; | |
1696 | ||
be1bb652 RH |
1697 | switch (NOTE_LINE_NUMBER (insn)) |
1698 | { | |
1699 | case NOTE_INSN_DELETED: | |
1700 | case NOTE_INSN_LOOP_BEG: | |
1701 | case NOTE_INSN_LOOP_END: | |
2c79137a | 1702 | case NOTE_INSN_LOOP_END_TOP_COND: |
be1bb652 RH |
1703 | case NOTE_INSN_LOOP_CONT: |
1704 | case NOTE_INSN_LOOP_VTOP: | |
1705 | case NOTE_INSN_FUNCTION_END: | |
be1bb652 | 1706 | case NOTE_INSN_REPEATED_LINE_NUMBER: |
be1bb652 RH |
1707 | case NOTE_INSN_EXPECTED_VALUE: |
1708 | break; | |
3cf2715d | 1709 | |
750054a2 CT |
1710 | case NOTE_INSN_UNLIKELY_EXECUTED_CODE: |
1711 | ||
1712 | /* The presence of this note indicates that this basic block | |
1713 | belongs in the "cold" section of the .o file. If we are | |
1714 | not already writing to the cold section we need to change | |
1715 | to it. */ | |
1716 | ||
1717 | unlikely_text_section (); | |
1718 | break; | |
1719 | ||
be1bb652 | 1720 | case NOTE_INSN_BASIC_BLOCK: |
750054a2 | 1721 | |
2b8a92de | 1722 | /* If we are performing the optimization that partitions |
750054a2 CT |
1723 | basic blocks into hot & cold sections of the .o file, |
1724 | then at the start of each new basic block, before | |
1725 | beginning to write code for the basic block, we need to | |
1726 | check to see whether the basic block belongs in the hot | |
1727 | or cold section of the .o file, and change the section we | |
1728 | are writing to appropriately. */ | |
1729 | ||
1730 | if (flag_reorder_blocks_and_partition | |
1731 | && in_unlikely_text_section() | |
1732 | && !scan_ahead_for_unlikely_executed_note (insn)) | |
1733 | text_section (); | |
1734 | ||
ad0fc698 JW |
1735 | #ifdef IA64_UNWIND_INFO |
1736 | IA64_UNWIND_EMIT (asm_out_file, insn); | |
1737 | #endif | |
be1bb652 RH |
1738 | if (flag_debug_asm) |
1739 | fprintf (asm_out_file, "\t%s basic block %d\n", | |
0b17ab2f | 1740 | ASM_COMMENT_START, NOTE_BASIC_BLOCK (insn)->index); |
589fe865 DJ |
1741 | |
1742 | if ((*seen & (SEEN_EMITTED | SEEN_BB)) == SEEN_BB) | |
1743 | { | |
1744 | *seen |= SEEN_EMITTED; | |
1745 | last_filename = NULL; | |
1746 | } | |
1747 | else | |
1748 | *seen |= SEEN_BB; | |
1749 | ||
be1bb652 | 1750 | break; |
3cf2715d | 1751 | |
be1bb652 | 1752 | case NOTE_INSN_EH_REGION_BEG: |
52a11cbf RH |
1753 | ASM_OUTPUT_DEBUG_LABEL (asm_out_file, "LEHB", |
1754 | NOTE_EH_HANDLER (insn)); | |
3d195391 | 1755 | break; |
3d195391 | 1756 | |
be1bb652 | 1757 | case NOTE_INSN_EH_REGION_END: |
52a11cbf RH |
1758 | ASM_OUTPUT_DEBUG_LABEL (asm_out_file, "LEHE", |
1759 | NOTE_EH_HANDLER (insn)); | |
3d195391 | 1760 | break; |
3d195391 | 1761 | |
be1bb652 | 1762 | case NOTE_INSN_PROLOGUE_END: |
5fd9b178 | 1763 | targetm.asm_out.function_end_prologue (file); |
3cf2715d | 1764 | profile_after_prologue (file); |
589fe865 DJ |
1765 | |
1766 | if ((*seen & (SEEN_EMITTED | SEEN_NOTE)) == SEEN_NOTE) | |
1767 | { | |
1768 | *seen |= SEEN_EMITTED; | |
1769 | last_filename = NULL; | |
1770 | } | |
1771 | else | |
1772 | *seen |= SEEN_NOTE; | |
1773 | ||
3cf2715d | 1774 | break; |
3cf2715d | 1775 | |
be1bb652 | 1776 | case NOTE_INSN_EPILOGUE_BEG: |
5fd9b178 | 1777 | targetm.asm_out.function_begin_epilogue (file); |
be1bb652 | 1778 | break; |
3cf2715d | 1779 | |
be1bb652 | 1780 | case NOTE_INSN_FUNCTION_BEG: |
653e276c | 1781 | app_disable (); |
702ada3d | 1782 | (*debug_hooks->end_prologue) (last_linenum, last_filename); |
589fe865 DJ |
1783 | |
1784 | if ((*seen & (SEEN_EMITTED | SEEN_NOTE)) == SEEN_NOTE) | |
1785 | { | |
1786 | *seen |= SEEN_EMITTED; | |
1787 | last_filename = NULL; | |
1788 | } | |
1789 | else | |
1790 | *seen |= SEEN_NOTE; | |
1791 | ||
3cf2715d | 1792 | break; |
be1bb652 RH |
1793 | |
1794 | case NOTE_INSN_BLOCK_BEG: | |
1795 | if (debug_info_level == DINFO_LEVEL_NORMAL | |
3cf2715d | 1796 | || debug_info_level == DINFO_LEVEL_VERBOSE |
3cf2715d | 1797 | || write_symbols == DWARF_DEBUG |
7a0c8d71 DR |
1798 | || write_symbols == DWARF2_DEBUG |
1799 | || write_symbols == VMS_AND_DWARF2_DEBUG | |
1800 | || write_symbols == VMS_DEBUG) | |
be1bb652 RH |
1801 | { |
1802 | int n = BLOCK_NUMBER (NOTE_BLOCK (insn)); | |
3cf2715d | 1803 | |
be1bb652 RH |
1804 | app_disable (); |
1805 | ++block_depth; | |
1806 | high_block_linenum = last_linenum; | |
eac40081 | 1807 | |
a5a42b92 | 1808 | /* Output debugging info about the symbol-block beginning. */ |
e2a12aca | 1809 | (*debug_hooks->begin_block) (last_linenum, n); |
3cf2715d | 1810 | |
be1bb652 RH |
1811 | /* Mark this block as output. */ |
1812 | TREE_ASM_WRITTEN (NOTE_BLOCK (insn)) = 1; | |
1813 | } | |
1814 | break; | |
18c038b9 | 1815 | |
be1bb652 RH |
1816 | case NOTE_INSN_BLOCK_END: |
1817 | if (debug_info_level == DINFO_LEVEL_NORMAL | |
1818 | || debug_info_level == DINFO_LEVEL_VERBOSE | |
1819 | || write_symbols == DWARF_DEBUG | |
7a0c8d71 DR |
1820 | || write_symbols == DWARF2_DEBUG |
1821 | || write_symbols == VMS_AND_DWARF2_DEBUG | |
1822 | || write_symbols == VMS_DEBUG) | |
be1bb652 RH |
1823 | { |
1824 | int n = BLOCK_NUMBER (NOTE_BLOCK (insn)); | |
3cf2715d | 1825 | |
be1bb652 RH |
1826 | app_disable (); |
1827 | ||
1828 | /* End of a symbol-block. */ | |
1829 | --block_depth; | |
1830 | if (block_depth < 0) | |
1831 | abort (); | |
3cf2715d | 1832 | |
e2a12aca | 1833 | (*debug_hooks->end_block) (high_block_linenum, n); |
be1bb652 RH |
1834 | } |
1835 | break; | |
1836 | ||
1837 | case NOTE_INSN_DELETED_LABEL: | |
1838 | /* Emit the label. We may have deleted the CODE_LABEL because | |
1839 | the label could be proved to be unreachable, though still | |
1840 | referenced (in the form of having its address taken. */ | |
8215347e | 1841 | ASM_OUTPUT_DEBUG_LABEL (file, "L", CODE_LABEL_NUMBER (insn)); |
be1bb652 | 1842 | break; |
3cf2715d | 1843 | |
014a1138 JZ |
1844 | case NOTE_INSN_VAR_LOCATION: |
1845 | (*debug_hooks->var_location) (insn); | |
1846 | break; | |
1847 | ||
21835d9b JJ |
1848 | case 0: |
1849 | break; | |
1850 | ||
be1bb652 RH |
1851 | default: |
1852 | if (NOTE_LINE_NUMBER (insn) <= 0) | |
1853 | abort (); | |
f5d927c0 | 1854 | break; |
3cf2715d DE |
1855 | } |
1856 | break; | |
1857 | ||
1858 | case BARRIER: | |
f73ad30e | 1859 | #if defined (DWARF2_UNWIND_INFO) |
fbfa55b0 | 1860 | if (dwarf2out_do_frame ()) |
be1bb652 | 1861 | dwarf2out_frame_debug (insn); |
3cf2715d DE |
1862 | #endif |
1863 | break; | |
1864 | ||
1865 | case CODE_LABEL: | |
1dd8faa8 R |
1866 | /* The target port might emit labels in the output function for |
1867 | some insn, e.g. sh.c output_branchy_insn. */ | |
de7987a6 R |
1868 | if (CODE_LABEL_NUMBER (insn) <= max_labelno) |
1869 | { | |
1870 | int align = LABEL_TO_ALIGNMENT (insn); | |
50b2596f | 1871 | #ifdef ASM_OUTPUT_MAX_SKIP_ALIGN |
9e423e6d | 1872 | int max_skip = LABEL_TO_MAX_SKIP (insn); |
50b2596f | 1873 | #endif |
fc470718 | 1874 | |
1dd8faa8 | 1875 | if (align && NEXT_INSN (insn)) |
40cdfca6 | 1876 | { |
9e423e6d | 1877 | #ifdef ASM_OUTPUT_MAX_SKIP_ALIGN |
40cdfca6 | 1878 | ASM_OUTPUT_MAX_SKIP_ALIGN (file, align, max_skip); |
8e16ab99 SF |
1879 | #else |
1880 | #ifdef ASM_OUTPUT_ALIGN_WITH_NOP | |
1881 | ASM_OUTPUT_ALIGN_WITH_NOP (file, align); | |
9e423e6d | 1882 | #else |
40cdfca6 | 1883 | ASM_OUTPUT_ALIGN (file, align); |
8e16ab99 | 1884 | #endif |
9e423e6d | 1885 | #endif |
40cdfca6 | 1886 | } |
de7987a6 | 1887 | } |
9ef4c6ef | 1888 | #ifdef HAVE_cc0 |
3cf2715d | 1889 | CC_STATUS_INIT; |
9ef4c6ef JC |
1890 | /* If this label is reached from only one place, set the condition |
1891 | codes from the instruction just before the branch. */ | |
7ad7f828 JC |
1892 | |
1893 | /* Disabled because some insns set cc_status in the C output code | |
1894 | and NOTICE_UPDATE_CC alone can set incorrect status. */ | |
1895 | if (0 /* optimize && LABEL_NUSES (insn) == 1*/) | |
9ef4c6ef JC |
1896 | { |
1897 | rtx jump = LABEL_REFS (insn); | |
1898 | rtx barrier = prev_nonnote_insn (insn); | |
1899 | rtx prev; | |
1900 | /* If the LABEL_REFS field of this label has been set to point | |
1901 | at a branch, the predecessor of the branch is a regular | |
1902 | insn, and that branch is the only way to reach this label, | |
1903 | set the condition codes based on the branch and its | |
1904 | predecessor. */ | |
1905 | if (barrier && GET_CODE (barrier) == BARRIER | |
1906 | && jump && GET_CODE (jump) == JUMP_INSN | |
1907 | && (prev = prev_nonnote_insn (jump)) | |
1908 | && GET_CODE (prev) == INSN) | |
1909 | { | |
1910 | NOTICE_UPDATE_CC (PATTERN (prev), prev); | |
1911 | NOTICE_UPDATE_CC (PATTERN (jump), jump); | |
1912 | } | |
1913 | } | |
1914 | #endif | |
3cf2715d DE |
1915 | if (prescan > 0) |
1916 | break; | |
03ffa171 | 1917 | |
e1772ac0 NB |
1918 | if (LABEL_NAME (insn)) |
1919 | (*debug_hooks->label) (insn); | |
1920 | ||
750054a2 CT |
1921 | /* If we are doing the optimization that partitions hot & cold |
1922 | basic blocks into separate sections of the .o file, we need | |
1923 | to ensure the jump table ends up in the correct section... */ | |
1924 | ||
1925 | if (flag_reorder_blocks_and_partition) | |
1926 | { | |
1927 | rtx tmp_table, tmp_label; | |
1928 | if (GET_CODE (insn) == CODE_LABEL | |
1929 | && tablejump_p (NEXT_INSN (insn), &tmp_label, &tmp_table)) | |
1930 | { | |
1931 | /* Do nothing; Do NOT change the current section. */ | |
1932 | } | |
1933 | else if (scan_ahead_for_unlikely_executed_note (insn)) | |
1934 | unlikely_text_section (); | |
1935 | else | |
1936 | { | |
1937 | if (in_unlikely_text_section ()) | |
1938 | text_section (); | |
1939 | } | |
1940 | } | |
1941 | ||
3cf2715d DE |
1942 | if (app_on) |
1943 | { | |
51723711 | 1944 | fputs (ASM_APP_OFF, file); |
3cf2715d DE |
1945 | app_on = 0; |
1946 | } | |
1947 | if (NEXT_INSN (insn) != 0 | |
1948 | && GET_CODE (NEXT_INSN (insn)) == JUMP_INSN) | |
1949 | { | |
1950 | rtx nextbody = PATTERN (NEXT_INSN (insn)); | |
1951 | ||
1952 | /* If this label is followed by a jump-table, | |
1953 | make sure we put the label in the read-only section. Also | |
1954 | possibly write the label and jump table together. */ | |
1955 | ||
1956 | if (GET_CODE (nextbody) == ADDR_VEC | |
1957 | || GET_CODE (nextbody) == ADDR_DIFF_VEC) | |
1958 | { | |
e0d80184 DM |
1959 | #if defined(ASM_OUTPUT_ADDR_VEC) || defined(ASM_OUTPUT_ADDR_DIFF_VEC) |
1960 | /* In this case, the case vector is being moved by the | |
1961 | target, so don't output the label at all. Leave that | |
1962 | to the back end macros. */ | |
1963 | #else | |
75197b37 BS |
1964 | if (! JUMP_TABLES_IN_TEXT_SECTION) |
1965 | { | |
340f7e7c RH |
1966 | int log_align; |
1967 | ||
75197b37 | 1968 | readonly_data_section (); |
340f7e7c RH |
1969 | |
1970 | #ifdef ADDR_VEC_ALIGN | |
3e4eece3 | 1971 | log_align = ADDR_VEC_ALIGN (NEXT_INSN (insn)); |
340f7e7c RH |
1972 | #else |
1973 | log_align = exact_log2 (BIGGEST_ALIGNMENT / BITS_PER_UNIT); | |
1974 | #endif | |
1975 | ASM_OUTPUT_ALIGN (file, log_align); | |
75197b37 BS |
1976 | } |
1977 | else | |
1978 | function_section (current_function_decl); | |
1979 | ||
3cf2715d DE |
1980 | #ifdef ASM_OUTPUT_CASE_LABEL |
1981 | ASM_OUTPUT_CASE_LABEL (file, "L", CODE_LABEL_NUMBER (insn), | |
1982 | NEXT_INSN (insn)); | |
1983 | #else | |
5fd9b178 | 1984 | targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (insn)); |
e0d80184 | 1985 | #endif |
3cf2715d DE |
1986 | #endif |
1987 | break; | |
1988 | } | |
1989 | } | |
0dc36574 ZW |
1990 | if (LABEL_ALT_ENTRY_P (insn)) |
1991 | output_alternate_entry_point (file, insn); | |
8cd0faaf | 1992 | else |
5fd9b178 | 1993 | targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (insn)); |
3cf2715d DE |
1994 | break; |
1995 | ||
1996 | default: | |
1997 | { | |
b3694847 | 1998 | rtx body = PATTERN (insn); |
3cf2715d | 1999 | int insn_code_number; |
9b3142b3 | 2000 | const char *template; |
3cf2715d DE |
2001 | rtx note; |
2002 | ||
2003 | /* An INSN, JUMP_INSN or CALL_INSN. | |
2004 | First check for special kinds that recog doesn't recognize. */ | |
2005 | ||
6614fd40 | 2006 | if (GET_CODE (body) == USE /* These are just declarations. */ |
3cf2715d DE |
2007 | || GET_CODE (body) == CLOBBER) |
2008 | break; | |
2009 | ||
2010 | #ifdef HAVE_cc0 | |
2011 | /* If there is a REG_CC_SETTER note on this insn, it means that | |
2012 | the setting of the condition code was done in the delay slot | |
2013 | of the insn that branched here. So recover the cc status | |
2014 | from the insn that set it. */ | |
2015 | ||
2016 | note = find_reg_note (insn, REG_CC_SETTER, NULL_RTX); | |
2017 | if (note) | |
2018 | { | |
2019 | NOTICE_UPDATE_CC (PATTERN (XEXP (note, 0)), XEXP (note, 0)); | |
2020 | cc_prev_status = cc_status; | |
2021 | } | |
2022 | #endif | |
2023 | ||
2024 | /* Detect insns that are really jump-tables | |
2025 | and output them as such. */ | |
2026 | ||
2027 | if (GET_CODE (body) == ADDR_VEC || GET_CODE (body) == ADDR_DIFF_VEC) | |
2028 | { | |
7f7f8214 | 2029 | #if !(defined(ASM_OUTPUT_ADDR_VEC) || defined(ASM_OUTPUT_ADDR_DIFF_VEC)) |
b3694847 | 2030 | int vlen, idx; |
7f7f8214 | 2031 | #endif |
3cf2715d DE |
2032 | |
2033 | if (prescan > 0) | |
2034 | break; | |
2035 | ||
2036 | if (app_on) | |
2037 | { | |
51723711 | 2038 | fputs (ASM_APP_OFF, file); |
3cf2715d DE |
2039 | app_on = 0; |
2040 | } | |
2041 | ||
e0d80184 DM |
2042 | #if defined(ASM_OUTPUT_ADDR_VEC) || defined(ASM_OUTPUT_ADDR_DIFF_VEC) |
2043 | if (GET_CODE (body) == ADDR_VEC) | |
2044 | { | |
2045 | #ifdef ASM_OUTPUT_ADDR_VEC | |
2046 | ASM_OUTPUT_ADDR_VEC (PREV_INSN (insn), body); | |
2047 | #else | |
f5d927c0 | 2048 | abort (); |
e0d80184 DM |
2049 | #endif |
2050 | } | |
2051 | else | |
2052 | { | |
2053 | #ifdef ASM_OUTPUT_ADDR_DIFF_VEC | |
2054 | ASM_OUTPUT_ADDR_DIFF_VEC (PREV_INSN (insn), body); | |
2055 | #else | |
f5d927c0 | 2056 | abort (); |
e0d80184 DM |
2057 | #endif |
2058 | } | |
2059 | #else | |
3cf2715d DE |
2060 | vlen = XVECLEN (body, GET_CODE (body) == ADDR_DIFF_VEC); |
2061 | for (idx = 0; idx < vlen; idx++) | |
2062 | { | |
2063 | if (GET_CODE (body) == ADDR_VEC) | |
2064 | { | |
2065 | #ifdef ASM_OUTPUT_ADDR_VEC_ELT | |
2066 | ASM_OUTPUT_ADDR_VEC_ELT | |
2067 | (file, CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 0, idx), 0))); | |
2068 | #else | |
2069 | abort (); | |
2070 | #endif | |
2071 | } | |
2072 | else | |
2073 | { | |
2074 | #ifdef ASM_OUTPUT_ADDR_DIFF_ELT | |
2075 | ASM_OUTPUT_ADDR_DIFF_ELT | |
2076 | (file, | |
33f7f353 | 2077 | body, |
3cf2715d DE |
2078 | CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 1, idx), 0)), |
2079 | CODE_LABEL_NUMBER (XEXP (XEXP (body, 0), 0))); | |
2080 | #else | |
2081 | abort (); | |
2082 | #endif | |
2083 | } | |
2084 | } | |
2085 | #ifdef ASM_OUTPUT_CASE_END | |
2086 | ASM_OUTPUT_CASE_END (file, | |
2087 | CODE_LABEL_NUMBER (PREV_INSN (insn)), | |
2088 | insn); | |
e0d80184 | 2089 | #endif |
3cf2715d DE |
2090 | #endif |
2091 | ||
4d1065ed | 2092 | function_section (current_function_decl); |
3cf2715d DE |
2093 | |
2094 | break; | |
2095 | } | |
0435312e JH |
2096 | /* Output this line note if it is the first or the last line |
2097 | note in a row. */ | |
2098 | if (notice_source_line (insn)) | |
2099 | { | |
2100 | (*debug_hooks->source_line) (last_linenum, last_filename); | |
2101 | } | |
3cf2715d | 2102 | |
3cf2715d DE |
2103 | if (GET_CODE (body) == ASM_INPUT) |
2104 | { | |
36d7136e RH |
2105 | const char *string = XSTR (body, 0); |
2106 | ||
3cf2715d DE |
2107 | /* There's no telling what that did to the condition codes. */ |
2108 | CC_STATUS_INIT; | |
2109 | if (prescan > 0) | |
2110 | break; | |
36d7136e RH |
2111 | |
2112 | if (string[0]) | |
3cf2715d | 2113 | { |
36d7136e RH |
2114 | if (! app_on) |
2115 | { | |
2116 | fputs (ASM_APP_ON, file); | |
2117 | app_on = 1; | |
2118 | } | |
2119 | fprintf (asm_out_file, "\t%s\n", string); | |
3cf2715d | 2120 | } |
3cf2715d DE |
2121 | break; |
2122 | } | |
2123 | ||
2124 | /* Detect `asm' construct with operands. */ | |
2125 | if (asm_noperands (body) >= 0) | |
2126 | { | |
22bf4422 | 2127 | unsigned int noperands = asm_noperands (body); |
703ad42b | 2128 | rtx *ops = alloca (noperands * sizeof (rtx)); |
3cce094d | 2129 | const char *string; |
3cf2715d DE |
2130 | |
2131 | /* There's no telling what that did to the condition codes. */ | |
2132 | CC_STATUS_INIT; | |
2133 | if (prescan > 0) | |
2134 | break; | |
2135 | ||
3cf2715d | 2136 | /* Get out the operand values. */ |
df4ae160 | 2137 | string = decode_asm_operands (body, ops, NULL, NULL, NULL); |
3cf2715d DE |
2138 | /* Inhibit aborts on what would otherwise be compiler bugs. */ |
2139 | insn_noperands = noperands; | |
2140 | this_is_asm_operands = insn; | |
2141 | ||
ad7e39ca AO |
2142 | #ifdef FINAL_PRESCAN_INSN |
2143 | FINAL_PRESCAN_INSN (insn, ops, insn_noperands); | |
2144 | #endif | |
2145 | ||
3cf2715d | 2146 | /* Output the insn using them. */ |
36d7136e RH |
2147 | if (string[0]) |
2148 | { | |
2149 | if (! app_on) | |
2150 | { | |
2151 | fputs (ASM_APP_ON, file); | |
2152 | app_on = 1; | |
2153 | } | |
2154 | output_asm_insn (string, ops); | |
2155 | } | |
2156 | ||
3cf2715d DE |
2157 | this_is_asm_operands = 0; |
2158 | break; | |
2159 | } | |
2160 | ||
2161 | if (prescan <= 0 && app_on) | |
2162 | { | |
51723711 | 2163 | fputs (ASM_APP_OFF, file); |
3cf2715d DE |
2164 | app_on = 0; |
2165 | } | |
2166 | ||
2167 | if (GET_CODE (body) == SEQUENCE) | |
2168 | { | |
2169 | /* A delayed-branch sequence */ | |
b3694847 | 2170 | int i; |
3cf2715d DE |
2171 | rtx next; |
2172 | ||
2173 | if (prescan > 0) | |
2174 | break; | |
2175 | final_sequence = body; | |
2176 | ||
d660cefe RS |
2177 | /* Record the delay slots' frame information before the branch. |
2178 | This is needed for delayed calls: see execute_cfa_program(). */ | |
2179 | #if defined (DWARF2_UNWIND_INFO) | |
2180 | if (dwarf2out_do_frame ()) | |
2181 | for (i = 1; i < XVECLEN (body, 0); i++) | |
2182 | dwarf2out_frame_debug (XVECEXP (body, 0, i)); | |
2183 | #endif | |
2184 | ||
3cf2715d DE |
2185 | /* The first insn in this SEQUENCE might be a JUMP_INSN that will |
2186 | force the restoration of a comparison that was previously | |
2187 | thought unnecessary. If that happens, cancel this sequence | |
2188 | and cause that insn to be restored. */ | |
2189 | ||
589fe865 | 2190 | next = final_scan_insn (XVECEXP (body, 0, 0), file, 0, prescan, 1, seen); |
3cf2715d DE |
2191 | if (next != XVECEXP (body, 0, 1)) |
2192 | { | |
2193 | final_sequence = 0; | |
2194 | return next; | |
2195 | } | |
2196 | ||
2197 | for (i = 1; i < XVECLEN (body, 0); i++) | |
c7eee2df RK |
2198 | { |
2199 | rtx insn = XVECEXP (body, 0, i); | |
2200 | rtx next = NEXT_INSN (insn); | |
2201 | /* We loop in case any instruction in a delay slot gets | |
2202 | split. */ | |
2203 | do | |
589fe865 | 2204 | insn = final_scan_insn (insn, file, 0, prescan, 1, seen); |
c7eee2df RK |
2205 | while (insn != next); |
2206 | } | |
3cf2715d DE |
2207 | #ifdef DBR_OUTPUT_SEQEND |
2208 | DBR_OUTPUT_SEQEND (file); | |
2209 | #endif | |
2210 | final_sequence = 0; | |
2211 | ||
2212 | /* If the insn requiring the delay slot was a CALL_INSN, the | |
2213 | insns in the delay slot are actually executed before the | |
2214 | called function. Hence we don't preserve any CC-setting | |
2215 | actions in these insns and the CC must be marked as being | |
2216 | clobbered by the function. */ | |
2217 | if (GET_CODE (XVECEXP (body, 0, 0)) == CALL_INSN) | |
b729186a JL |
2218 | { |
2219 | CC_STATUS_INIT; | |
2220 | } | |
3cf2715d DE |
2221 | break; |
2222 | } | |
2223 | ||
2224 | /* We have a real machine instruction as rtl. */ | |
2225 | ||
2226 | body = PATTERN (insn); | |
2227 | ||
2228 | #ifdef HAVE_cc0 | |
f5d927c0 | 2229 | set = single_set (insn); |
b88c92cc | 2230 | |
3cf2715d DE |
2231 | /* Check for redundant test and compare instructions |
2232 | (when the condition codes are already set up as desired). | |
2233 | This is done only when optimizing; if not optimizing, | |
2234 | it should be possible for the user to alter a variable | |
2235 | with the debugger in between statements | |
2236 | and the next statement should reexamine the variable | |
2237 | to compute the condition codes. */ | |
2238 | ||
30f5e9f5 | 2239 | if (optimize) |
3cf2715d | 2240 | { |
30f5e9f5 RK |
2241 | if (set |
2242 | && GET_CODE (SET_DEST (set)) == CC0 | |
2243 | && insn != last_ignored_compare) | |
3cf2715d | 2244 | { |
30f5e9f5 | 2245 | if (GET_CODE (SET_SRC (set)) == SUBREG) |
49d801d3 | 2246 | SET_SRC (set) = alter_subreg (&SET_SRC (set)); |
30f5e9f5 RK |
2247 | else if (GET_CODE (SET_SRC (set)) == COMPARE) |
2248 | { | |
2249 | if (GET_CODE (XEXP (SET_SRC (set), 0)) == SUBREG) | |
2250 | XEXP (SET_SRC (set), 0) | |
49d801d3 | 2251 | = alter_subreg (&XEXP (SET_SRC (set), 0)); |
30f5e9f5 RK |
2252 | if (GET_CODE (XEXP (SET_SRC (set), 1)) == SUBREG) |
2253 | XEXP (SET_SRC (set), 1) | |
49d801d3 | 2254 | = alter_subreg (&XEXP (SET_SRC (set), 1)); |
30f5e9f5 RK |
2255 | } |
2256 | if ((cc_status.value1 != 0 | |
2257 | && rtx_equal_p (SET_SRC (set), cc_status.value1)) | |
2258 | || (cc_status.value2 != 0 | |
2259 | && rtx_equal_p (SET_SRC (set), cc_status.value2))) | |
3cf2715d | 2260 | { |
30f5e9f5 | 2261 | /* Don't delete insn if it has an addressing side-effect. */ |
ff81832f | 2262 | if (! FIND_REG_INC_NOTE (insn, NULL_RTX) |
30f5e9f5 RK |
2263 | /* or if anything in it is volatile. */ |
2264 | && ! volatile_refs_p (PATTERN (insn))) | |
2265 | { | |
2266 | /* We don't really delete the insn; just ignore it. */ | |
2267 | last_ignored_compare = insn; | |
2268 | break; | |
2269 | } | |
3cf2715d DE |
2270 | } |
2271 | } | |
2272 | } | |
2273 | #endif | |
2274 | ||
3cf2715d DE |
2275 | #ifndef STACK_REGS |
2276 | /* Don't bother outputting obvious no-ops, even without -O. | |
2277 | This optimization is fast and doesn't interfere with debugging. | |
2278 | Don't do this if the insn is in a delay slot, since this | |
2279 | will cause an improper number of delay insns to be written. */ | |
2280 | if (final_sequence == 0 | |
2281 | && prescan >= 0 | |
2282 | && GET_CODE (insn) == INSN && GET_CODE (body) == SET | |
f8cfc6aa JQ |
2283 | && REG_P (SET_SRC (body)) |
2284 | && REG_P (SET_DEST (body)) | |
3cf2715d DE |
2285 | && REGNO (SET_SRC (body)) == REGNO (SET_DEST (body))) |
2286 | break; | |
2287 | #endif | |
2288 | ||
2289 | #ifdef HAVE_cc0 | |
2290 | /* If this is a conditional branch, maybe modify it | |
2291 | if the cc's are in a nonstandard state | |
2292 | so that it accomplishes the same thing that it would | |
2293 | do straightforwardly if the cc's were set up normally. */ | |
2294 | ||
2295 | if (cc_status.flags != 0 | |
2296 | && GET_CODE (insn) == JUMP_INSN | |
2297 | && GET_CODE (body) == SET | |
2298 | && SET_DEST (body) == pc_rtx | |
2299 | && GET_CODE (SET_SRC (body)) == IF_THEN_ELSE | |
ec8e098d | 2300 | && COMPARISON_P (XEXP (SET_SRC (body), 0)) |
fff752ad | 2301 | && XEXP (XEXP (SET_SRC (body), 0), 0) == cc0_rtx |
3cf2715d DE |
2302 | /* This is done during prescan; it is not done again |
2303 | in final scan when prescan has been done. */ | |
2304 | && prescan >= 0) | |
2305 | { | |
2306 | /* This function may alter the contents of its argument | |
2307 | and clear some of the cc_status.flags bits. | |
2308 | It may also return 1 meaning condition now always true | |
2309 | or -1 meaning condition now always false | |
2310 | or 2 meaning condition nontrivial but altered. */ | |
b3694847 | 2311 | int result = alter_cond (XEXP (SET_SRC (body), 0)); |
3cf2715d DE |
2312 | /* If condition now has fixed value, replace the IF_THEN_ELSE |
2313 | with its then-operand or its else-operand. */ | |
2314 | if (result == 1) | |
2315 | SET_SRC (body) = XEXP (SET_SRC (body), 1); | |
2316 | if (result == -1) | |
2317 | SET_SRC (body) = XEXP (SET_SRC (body), 2); | |
2318 | ||
2319 | /* The jump is now either unconditional or a no-op. | |
2320 | If it has become a no-op, don't try to output it. | |
2321 | (It would not be recognized.) */ | |
2322 | if (SET_SRC (body) == pc_rtx) | |
2323 | { | |
ca6c03ca | 2324 | delete_insn (insn); |
3cf2715d DE |
2325 | break; |
2326 | } | |
2327 | else if (GET_CODE (SET_SRC (body)) == RETURN) | |
2328 | /* Replace (set (pc) (return)) with (return). */ | |
2329 | PATTERN (insn) = body = SET_SRC (body); | |
2330 | ||
2331 | /* Rerecognize the instruction if it has changed. */ | |
2332 | if (result != 0) | |
2333 | INSN_CODE (insn) = -1; | |
2334 | } | |
2335 | ||
2336 | /* Make same adjustments to instructions that examine the | |
462da2af SC |
2337 | condition codes without jumping and instructions that |
2338 | handle conditional moves (if this machine has either one). */ | |
3cf2715d DE |
2339 | |
2340 | if (cc_status.flags != 0 | |
b88c92cc | 2341 | && set != 0) |
3cf2715d | 2342 | { |
462da2af | 2343 | rtx cond_rtx, then_rtx, else_rtx; |
f5d927c0 | 2344 | |
462da2af | 2345 | if (GET_CODE (insn) != JUMP_INSN |
b88c92cc | 2346 | && GET_CODE (SET_SRC (set)) == IF_THEN_ELSE) |
462da2af | 2347 | { |
b88c92cc RK |
2348 | cond_rtx = XEXP (SET_SRC (set), 0); |
2349 | then_rtx = XEXP (SET_SRC (set), 1); | |
2350 | else_rtx = XEXP (SET_SRC (set), 2); | |
462da2af SC |
2351 | } |
2352 | else | |
2353 | { | |
b88c92cc | 2354 | cond_rtx = SET_SRC (set); |
462da2af SC |
2355 | then_rtx = const_true_rtx; |
2356 | else_rtx = const0_rtx; | |
2357 | } | |
f5d927c0 | 2358 | |
462da2af | 2359 | switch (GET_CODE (cond_rtx)) |
3cf2715d DE |
2360 | { |
2361 | case GTU: | |
2362 | case GT: | |
2363 | case LTU: | |
2364 | case LT: | |
2365 | case GEU: | |
2366 | case GE: | |
2367 | case LEU: | |
2368 | case LE: | |
2369 | case EQ: | |
2370 | case NE: | |
2371 | { | |
b3694847 | 2372 | int result; |
462da2af | 2373 | if (XEXP (cond_rtx, 0) != cc0_rtx) |
3cf2715d | 2374 | break; |
462da2af | 2375 | result = alter_cond (cond_rtx); |
3cf2715d | 2376 | if (result == 1) |
b88c92cc | 2377 | validate_change (insn, &SET_SRC (set), then_rtx, 0); |
3cf2715d | 2378 | else if (result == -1) |
b88c92cc | 2379 | validate_change (insn, &SET_SRC (set), else_rtx, 0); |
3cf2715d DE |
2380 | else if (result == 2) |
2381 | INSN_CODE (insn) = -1; | |
b88c92cc | 2382 | if (SET_DEST (set) == SET_SRC (set)) |
ca6c03ca | 2383 | delete_insn (insn); |
3cf2715d | 2384 | } |
e9a25f70 JL |
2385 | break; |
2386 | ||
2387 | default: | |
2388 | break; | |
3cf2715d DE |
2389 | } |
2390 | } | |
462da2af | 2391 | |
3cf2715d DE |
2392 | #endif |
2393 | ||
ede7cd44 | 2394 | #ifdef HAVE_peephole |
3cf2715d DE |
2395 | /* Do machine-specific peephole optimizations if desired. */ |
2396 | ||
2397 | if (optimize && !flag_no_peephole && !nopeepholes) | |
2398 | { | |
2399 | rtx next = peephole (insn); | |
2400 | /* When peepholing, if there were notes within the peephole, | |
2401 | emit them before the peephole. */ | |
2402 | if (next != 0 && next != NEXT_INSN (insn)) | |
2403 | { | |
2404 | rtx prev = PREV_INSN (insn); | |
3cf2715d DE |
2405 | |
2406 | for (note = NEXT_INSN (insn); note != next; | |
2407 | note = NEXT_INSN (note)) | |
589fe865 | 2408 | final_scan_insn (note, file, optimize, prescan, nopeepholes, seen); |
3cf2715d DE |
2409 | |
2410 | /* In case this is prescan, put the notes | |
2411 | in proper position for later rescan. */ | |
2412 | note = NEXT_INSN (insn); | |
2413 | PREV_INSN (note) = prev; | |
2414 | NEXT_INSN (prev) = note; | |
2415 | NEXT_INSN (PREV_INSN (next)) = insn; | |
2416 | PREV_INSN (insn) = PREV_INSN (next); | |
2417 | NEXT_INSN (insn) = next; | |
2418 | PREV_INSN (next) = insn; | |
2419 | } | |
2420 | ||
2421 | /* PEEPHOLE might have changed this. */ | |
2422 | body = PATTERN (insn); | |
2423 | } | |
ede7cd44 | 2424 | #endif |
3cf2715d DE |
2425 | |
2426 | /* Try to recognize the instruction. | |
2427 | If successful, verify that the operands satisfy the | |
2428 | constraints for the instruction. Crash if they don't, | |
2429 | since `reload' should have changed them so that they do. */ | |
2430 | ||
2431 | insn_code_number = recog_memoized (insn); | |
0304f787 | 2432 | cleanup_subreg_operands (insn); |
3cf2715d | 2433 | |
dd3f0101 KH |
2434 | /* Dump the insn in the assembly for debugging. */ |
2435 | if (flag_dump_rtl_in_asm) | |
2436 | { | |
2437 | print_rtx_head = ASM_COMMENT_START; | |
2438 | print_rtl_single (asm_out_file, insn); | |
2439 | print_rtx_head = ""; | |
2440 | } | |
b9f22704 | 2441 | |
6c698a6d | 2442 | if (! constrain_operands_cached (1)) |
3cf2715d | 2443 | fatal_insn_not_found (insn); |
3cf2715d DE |
2444 | |
2445 | /* Some target machines need to prescan each insn before | |
2446 | it is output. */ | |
2447 | ||
2448 | #ifdef FINAL_PRESCAN_INSN | |
1ccbefce | 2449 | FINAL_PRESCAN_INSN (insn, recog_data.operand, recog_data.n_operands); |
3cf2715d DE |
2450 | #endif |
2451 | ||
afe48e06 RH |
2452 | #ifdef HAVE_conditional_execution |
2453 | if (GET_CODE (PATTERN (insn)) == COND_EXEC) | |
2454 | current_insn_predicate = COND_EXEC_TEST (PATTERN (insn)); | |
2455 | else | |
2456 | current_insn_predicate = NULL_RTX; | |
2457 | #endif | |
2458 | ||
3cf2715d DE |
2459 | #ifdef HAVE_cc0 |
2460 | cc_prev_status = cc_status; | |
2461 | ||
2462 | /* Update `cc_status' for this instruction. | |
2463 | The instruction's output routine may change it further. | |
2464 | If the output routine for a jump insn needs to depend | |
2465 | on the cc status, it should look at cc_prev_status. */ | |
2466 | ||
2467 | NOTICE_UPDATE_CC (body, insn); | |
2468 | #endif | |
2469 | ||
b1a9f6a0 | 2470 | current_output_insn = debug_insn = insn; |
3cf2715d | 2471 | |
f73ad30e | 2472 | #if defined (DWARF2_UNWIND_INFO) |
fbfa55b0 | 2473 | if (GET_CODE (insn) == CALL_INSN && dwarf2out_do_frame ()) |
b57d9225 JM |
2474 | dwarf2out_frame_debug (insn); |
2475 | #endif | |
2476 | ||
4bbf910e RH |
2477 | /* Find the proper template for this insn. */ |
2478 | template = get_insn_template (insn_code_number, insn); | |
3cf2715d | 2479 | |
4bbf910e RH |
2480 | /* If the C code returns 0, it means that it is a jump insn |
2481 | which follows a deleted test insn, and that test insn | |
2482 | needs to be reinserted. */ | |
3cf2715d DE |
2483 | if (template == 0) |
2484 | { | |
efd0378b HPN |
2485 | rtx prev; |
2486 | ||
4bbf910e RH |
2487 | if (prev_nonnote_insn (insn) != last_ignored_compare) |
2488 | abort (); | |
efd0378b HPN |
2489 | |
2490 | /* We have already processed the notes between the setter and | |
2491 | the user. Make sure we don't process them again, this is | |
2492 | particularly important if one of the notes is a block | |
2493 | scope note or an EH note. */ | |
2494 | for (prev = insn; | |
2495 | prev != last_ignored_compare; | |
2496 | prev = PREV_INSN (prev)) | |
2497 | { | |
2498 | if (GET_CODE (prev) == NOTE) | |
ca6c03ca | 2499 | delete_insn (prev); /* Use delete_note. */ |
efd0378b HPN |
2500 | } |
2501 | ||
2502 | return prev; | |
3cf2715d DE |
2503 | } |
2504 | ||
2505 | /* If the template is the string "#", it means that this insn must | |
2506 | be split. */ | |
2507 | if (template[0] == '#' && template[1] == '\0') | |
2508 | { | |
2509 | rtx new = try_split (body, insn, 0); | |
2510 | ||
2511 | /* If we didn't split the insn, go away. */ | |
2512 | if (new == insn && PATTERN (new) == body) | |
c725bd79 | 2513 | fatal_insn ("could not split insn", insn); |
f5d927c0 | 2514 | |
3d14e82f JW |
2515 | #ifdef HAVE_ATTR_length |
2516 | /* This instruction should have been split in shorten_branches, | |
2517 | to ensure that we would have valid length info for the | |
2518 | splitees. */ | |
2519 | abort (); | |
2520 | #endif | |
2521 | ||
3cf2715d DE |
2522 | return new; |
2523 | } | |
f5d927c0 | 2524 | |
3cf2715d DE |
2525 | if (prescan > 0) |
2526 | break; | |
2527 | ||
ce152ef8 AM |
2528 | #ifdef IA64_UNWIND_INFO |
2529 | IA64_UNWIND_EMIT (asm_out_file, insn); | |
2530 | #endif | |
3cf2715d DE |
2531 | /* Output assembler code from the template. */ |
2532 | ||
1ccbefce | 2533 | output_asm_insn (template, recog_data.operand); |
3cf2715d | 2534 | |
d660cefe RS |
2535 | /* If necessary, report the effect that the instruction has on |
2536 | the unwind info. We've already done this for delay slots | |
2537 | and call instructions. */ | |
0021b564 | 2538 | #if defined (DWARF2_UNWIND_INFO) |
d660cefe RS |
2539 | if (GET_CODE (insn) == INSN |
2540 | #if !defined (HAVE_prologue) | |
2541 | && !ACCUMULATE_OUTGOING_ARGS | |
2542 | #endif | |
2543 | && final_sequence == 0 | |
fbfa55b0 RH |
2544 | && dwarf2out_do_frame ()) |
2545 | dwarf2out_frame_debug (insn); | |
0021b564 | 2546 | #endif |
469ac993 | 2547 | |
3cf2715d | 2548 | #if 0 |
6001794d KH |
2549 | /* It's not at all clear why we did this and doing so used to |
2550 | interfere with tests that used REG_WAS_0 notes, which are | |
2551 | now gone, so let's try with this out. */ | |
3cf2715d DE |
2552 | |
2553 | /* Mark this insn as having been output. */ | |
2554 | INSN_DELETED_P (insn) = 1; | |
2555 | #endif | |
2556 | ||
4a8d0c9c RH |
2557 | /* Emit information for vtable gc. */ |
2558 | note = find_reg_note (insn, REG_VTABLE_REF, NULL_RTX); | |
4a8d0c9c | 2559 | |
b1a9f6a0 | 2560 | current_output_insn = debug_insn = 0; |
3cf2715d DE |
2561 | } |
2562 | } | |
2563 | return NEXT_INSN (insn); | |
2564 | } | |
2565 | \f | |
2566 | /* Output debugging info to the assembler file FILE | |
2567 | based on the NOTE-insn INSN, assumed to be a line number. */ | |
2568 | ||
0435312e | 2569 | static bool |
6cf9ac28 | 2570 | notice_source_line (rtx insn) |
3cf2715d | 2571 | { |
0435312e JH |
2572 | const char *filename = insn_file (insn); |
2573 | int linenum = insn_line (insn); | |
3cf2715d | 2574 | |
0435312e JH |
2575 | if (filename && (filename != last_filename || last_linenum != linenum)) |
2576 | { | |
2577 | last_filename = filename; | |
2578 | last_linenum = linenum; | |
2579 | high_block_linenum = MAX (last_linenum, high_block_linenum); | |
2580 | high_function_linenum = MAX (last_linenum, high_function_linenum); | |
2581 | return true; | |
2582 | } | |
2583 | return false; | |
3cf2715d DE |
2584 | } |
2585 | \f | |
0304f787 JL |
2586 | /* For each operand in INSN, simplify (subreg (reg)) so that it refers |
2587 | directly to the desired hard register. */ | |
f5d927c0 | 2588 | |
0304f787 | 2589 | void |
6cf9ac28 | 2590 | cleanup_subreg_operands (rtx insn) |
0304f787 | 2591 | { |
f62a15e3 | 2592 | int i; |
6c698a6d | 2593 | extract_insn_cached (insn); |
1ccbefce | 2594 | for (i = 0; i < recog_data.n_operands; i++) |
0304f787 | 2595 | { |
2067c116 | 2596 | /* The following test cannot use recog_data.operand when testing |
9f4524f2 RE |
2597 | for a SUBREG: the underlying object might have been changed |
2598 | already if we are inside a match_operator expression that | |
2599 | matches the else clause. Instead we test the underlying | |
2600 | expression directly. */ | |
2601 | if (GET_CODE (*recog_data.operand_loc[i]) == SUBREG) | |
49d801d3 | 2602 | recog_data.operand[i] = alter_subreg (recog_data.operand_loc[i]); |
1ccbefce | 2603 | else if (GET_CODE (recog_data.operand[i]) == PLUS |
04337620 | 2604 | || GET_CODE (recog_data.operand[i]) == MULT |
3c0cb5de | 2605 | || MEM_P (recog_data.operand[i])) |
49d801d3 | 2606 | recog_data.operand[i] = walk_alter_subreg (recog_data.operand_loc[i]); |
0304f787 JL |
2607 | } |
2608 | ||
1ccbefce | 2609 | for (i = 0; i < recog_data.n_dups; i++) |
0304f787 | 2610 | { |
1ccbefce | 2611 | if (GET_CODE (*recog_data.dup_loc[i]) == SUBREG) |
49d801d3 | 2612 | *recog_data.dup_loc[i] = alter_subreg (recog_data.dup_loc[i]); |
1ccbefce | 2613 | else if (GET_CODE (*recog_data.dup_loc[i]) == PLUS |
04337620 | 2614 | || GET_CODE (*recog_data.dup_loc[i]) == MULT |
3c0cb5de | 2615 | || MEM_P (*recog_data.dup_loc[i])) |
49d801d3 | 2616 | *recog_data.dup_loc[i] = walk_alter_subreg (recog_data.dup_loc[i]); |
0304f787 JL |
2617 | } |
2618 | } | |
2619 | ||
3cf2715d DE |
2620 | /* If X is a SUBREG, replace it with a REG or a MEM, |
2621 | based on the thing it is a subreg of. */ | |
2622 | ||
2623 | rtx | |
6cf9ac28 | 2624 | alter_subreg (rtx *xp) |
3cf2715d | 2625 | { |
49d801d3 | 2626 | rtx x = *xp; |
b3694847 | 2627 | rtx y = SUBREG_REG (x); |
f5963e61 | 2628 | |
49d801d3 JH |
2629 | /* simplify_subreg does not remove subreg from volatile references. |
2630 | We are required to. */ | |
3c0cb5de | 2631 | if (MEM_P (y)) |
49d801d3 JH |
2632 | *xp = adjust_address (y, GET_MODE (x), SUBREG_BYTE (x)); |
2633 | else | |
fea54805 RK |
2634 | { |
2635 | rtx new = simplify_subreg (GET_MODE (x), y, GET_MODE (y), | |
2636 | SUBREG_BYTE (x)); | |
2637 | ||
2638 | if (new != 0) | |
2639 | *xp = new; | |
2640 | /* Simplify_subreg can't handle some REG cases, but we have to. */ | |
f8cfc6aa | 2641 | else if (REG_P (y)) |
fea54805 | 2642 | { |
7687c5b8 | 2643 | unsigned int regno = subreg_hard_regno (x, 1); |
a560d4d4 | 2644 | *xp = gen_rtx_REG_offset (y, GET_MODE (x), regno, SUBREG_BYTE (x)); |
fea54805 RK |
2645 | } |
2646 | else | |
2647 | abort (); | |
2648 | } | |
2649 | ||
49d801d3 | 2650 | return *xp; |
3cf2715d DE |
2651 | } |
2652 | ||
2653 | /* Do alter_subreg on all the SUBREGs contained in X. */ | |
2654 | ||
2655 | static rtx | |
6cf9ac28 | 2656 | walk_alter_subreg (rtx *xp) |
3cf2715d | 2657 | { |
49d801d3 | 2658 | rtx x = *xp; |
3cf2715d DE |
2659 | switch (GET_CODE (x)) |
2660 | { | |
2661 | case PLUS: | |
2662 | case MULT: | |
beed8fc0 | 2663 | case AND: |
49d801d3 JH |
2664 | XEXP (x, 0) = walk_alter_subreg (&XEXP (x, 0)); |
2665 | XEXP (x, 1) = walk_alter_subreg (&XEXP (x, 1)); | |
3cf2715d DE |
2666 | break; |
2667 | ||
2668 | case MEM: | |
beed8fc0 | 2669 | case ZERO_EXTEND: |
49d801d3 | 2670 | XEXP (x, 0) = walk_alter_subreg (&XEXP (x, 0)); |
3cf2715d DE |
2671 | break; |
2672 | ||
2673 | case SUBREG: | |
49d801d3 | 2674 | return alter_subreg (xp); |
f5d927c0 | 2675 | |
e9a25f70 JL |
2676 | default: |
2677 | break; | |
3cf2715d DE |
2678 | } |
2679 | ||
5bc72aeb | 2680 | return *xp; |
3cf2715d DE |
2681 | } |
2682 | \f | |
2683 | #ifdef HAVE_cc0 | |
2684 | ||
2685 | /* Given BODY, the body of a jump instruction, alter the jump condition | |
2686 | as required by the bits that are set in cc_status.flags. | |
2687 | Not all of the bits there can be handled at this level in all cases. | |
2688 | ||
2689 | The value is normally 0. | |
2690 | 1 means that the condition has become always true. | |
2691 | -1 means that the condition has become always false. | |
2692 | 2 means that COND has been altered. */ | |
2693 | ||
2694 | static int | |
6cf9ac28 | 2695 | alter_cond (rtx cond) |
3cf2715d DE |
2696 | { |
2697 | int value = 0; | |
2698 | ||
2699 | if (cc_status.flags & CC_REVERSED) | |
2700 | { | |
2701 | value = 2; | |
2702 | PUT_CODE (cond, swap_condition (GET_CODE (cond))); | |
2703 | } | |
2704 | ||
2705 | if (cc_status.flags & CC_INVERTED) | |
2706 | { | |
2707 | value = 2; | |
2708 | PUT_CODE (cond, reverse_condition (GET_CODE (cond))); | |
2709 | } | |
2710 | ||
2711 | if (cc_status.flags & CC_NOT_POSITIVE) | |
2712 | switch (GET_CODE (cond)) | |
2713 | { | |
2714 | case LE: | |
2715 | case LEU: | |
2716 | case GEU: | |
2717 | /* Jump becomes unconditional. */ | |
2718 | return 1; | |
2719 | ||
2720 | case GT: | |
2721 | case GTU: | |
2722 | case LTU: | |
2723 | /* Jump becomes no-op. */ | |
2724 | return -1; | |
2725 | ||
2726 | case GE: | |
2727 | PUT_CODE (cond, EQ); | |
2728 | value = 2; | |
2729 | break; | |
2730 | ||
2731 | case LT: | |
2732 | PUT_CODE (cond, NE); | |
2733 | value = 2; | |
2734 | break; | |
f5d927c0 | 2735 | |
e9a25f70 JL |
2736 | default: |
2737 | break; | |
3cf2715d DE |
2738 | } |
2739 | ||
2740 | if (cc_status.flags & CC_NOT_NEGATIVE) | |
2741 | switch (GET_CODE (cond)) | |
2742 | { | |
2743 | case GE: | |
2744 | case GEU: | |
2745 | /* Jump becomes unconditional. */ | |
2746 | return 1; | |
2747 | ||
2748 | case LT: | |
2749 | case LTU: | |
2750 | /* Jump becomes no-op. */ | |
2751 | return -1; | |
2752 | ||
2753 | case LE: | |
2754 | case LEU: | |
2755 | PUT_CODE (cond, EQ); | |
2756 | value = 2; | |
2757 | break; | |
2758 | ||
2759 | case GT: | |
2760 | case GTU: | |
2761 | PUT_CODE (cond, NE); | |
2762 | value = 2; | |
2763 | break; | |
f5d927c0 | 2764 | |
e9a25f70 JL |
2765 | default: |
2766 | break; | |
3cf2715d DE |
2767 | } |
2768 | ||
2769 | if (cc_status.flags & CC_NO_OVERFLOW) | |
2770 | switch (GET_CODE (cond)) | |
2771 | { | |
2772 | case GEU: | |
2773 | /* Jump becomes unconditional. */ | |
2774 | return 1; | |
2775 | ||
2776 | case LEU: | |
2777 | PUT_CODE (cond, EQ); | |
2778 | value = 2; | |
2779 | break; | |
2780 | ||
2781 | case GTU: | |
2782 | PUT_CODE (cond, NE); | |
2783 | value = 2; | |
2784 | break; | |
2785 | ||
2786 | case LTU: | |
2787 | /* Jump becomes no-op. */ | |
2788 | return -1; | |
f5d927c0 | 2789 | |
e9a25f70 JL |
2790 | default: |
2791 | break; | |
3cf2715d DE |
2792 | } |
2793 | ||
2794 | if (cc_status.flags & (CC_Z_IN_NOT_N | CC_Z_IN_N)) | |
2795 | switch (GET_CODE (cond)) | |
2796 | { | |
e9a25f70 | 2797 | default: |
3cf2715d DE |
2798 | abort (); |
2799 | ||
2800 | case NE: | |
2801 | PUT_CODE (cond, cc_status.flags & CC_Z_IN_N ? GE : LT); | |
2802 | value = 2; | |
2803 | break; | |
2804 | ||
2805 | case EQ: | |
2806 | PUT_CODE (cond, cc_status.flags & CC_Z_IN_N ? LT : GE); | |
2807 | value = 2; | |
2808 | break; | |
2809 | } | |
2810 | ||
2811 | if (cc_status.flags & CC_NOT_SIGNED) | |
2812 | /* The flags are valid if signed condition operators are converted | |
2813 | to unsigned. */ | |
2814 | switch (GET_CODE (cond)) | |
2815 | { | |
2816 | case LE: | |
2817 | PUT_CODE (cond, LEU); | |
2818 | value = 2; | |
2819 | break; | |
2820 | ||
2821 | case LT: | |
2822 | PUT_CODE (cond, LTU); | |
2823 | value = 2; | |
2824 | break; | |
2825 | ||
2826 | case GT: | |
2827 | PUT_CODE (cond, GTU); | |
2828 | value = 2; | |
2829 | break; | |
2830 | ||
2831 | case GE: | |
2832 | PUT_CODE (cond, GEU); | |
2833 | value = 2; | |
2834 | break; | |
e9a25f70 JL |
2835 | |
2836 | default: | |
2837 | break; | |
3cf2715d DE |
2838 | } |
2839 | ||
2840 | return value; | |
2841 | } | |
2842 | #endif | |
2843 | \f | |
2844 | /* Report inconsistency between the assembler template and the operands. | |
2845 | In an `asm', it's the user's fault; otherwise, the compiler's fault. */ | |
2846 | ||
2847 | void | |
e34d07f2 | 2848 | output_operand_lossage (const char *msgid, ...) |
3cf2715d | 2849 | { |
a52453cc PT |
2850 | char *fmt_string; |
2851 | char *new_message; | |
fd478a0a | 2852 | const char *pfx_str; |
e34d07f2 | 2853 | va_list ap; |
6cf9ac28 | 2854 | |
e34d07f2 | 2855 | va_start (ap, msgid); |
a52453cc PT |
2856 | |
2857 | pfx_str = this_is_asm_operands ? _("invalid `asm': ") : "output_operand: "; | |
2858 | asprintf (&fmt_string, "%s%s", pfx_str, _(msgid)); | |
2859 | vasprintf (&new_message, fmt_string, ap); | |
dd3f0101 | 2860 | |
3cf2715d | 2861 | if (this_is_asm_operands) |
a52453cc | 2862 | error_for_asm (this_is_asm_operands, "%s", new_message); |
3cf2715d | 2863 | else |
a52453cc PT |
2864 | internal_error ("%s", new_message); |
2865 | ||
2866 | free (fmt_string); | |
2867 | free (new_message); | |
e34d07f2 | 2868 | va_end (ap); |
3cf2715d DE |
2869 | } |
2870 | \f | |
2871 | /* Output of assembler code from a template, and its subroutines. */ | |
2872 | ||
0d4903b8 RK |
2873 | /* Annotate the assembly with a comment describing the pattern and |
2874 | alternative used. */ | |
2875 | ||
2876 | static void | |
6cf9ac28 | 2877 | output_asm_name (void) |
0d4903b8 RK |
2878 | { |
2879 | if (debug_insn) | |
2880 | { | |
2881 | int num = INSN_CODE (debug_insn); | |
2882 | fprintf (asm_out_file, "\t%s %d\t%s", | |
2883 | ASM_COMMENT_START, INSN_UID (debug_insn), | |
2884 | insn_data[num].name); | |
2885 | if (insn_data[num].n_alternatives > 1) | |
2886 | fprintf (asm_out_file, "/%d", which_alternative + 1); | |
2887 | #ifdef HAVE_ATTR_length | |
2888 | fprintf (asm_out_file, "\t[length = %d]", | |
2889 | get_attr_length (debug_insn)); | |
2890 | #endif | |
2891 | /* Clear this so only the first assembler insn | |
2892 | of any rtl insn will get the special comment for -dp. */ | |
2893 | debug_insn = 0; | |
2894 | } | |
2895 | } | |
2896 | ||
998d7deb RH |
2897 | /* If OP is a REG or MEM and we can find a MEM_EXPR corresponding to it |
2898 | or its address, return that expr . Set *PADDRESSP to 1 if the expr | |
c5adc06a RK |
2899 | corresponds to the address of the object and 0 if to the object. */ |
2900 | ||
2901 | static tree | |
6cf9ac28 | 2902 | get_mem_expr_from_op (rtx op, int *paddressp) |
c5adc06a | 2903 | { |
998d7deb | 2904 | tree expr; |
c5adc06a RK |
2905 | int inner_addressp; |
2906 | ||
2907 | *paddressp = 0; | |
2908 | ||
f8cfc6aa | 2909 | if (REG_P (op)) |
a560d4d4 | 2910 | return REG_EXPR (op); |
3c0cb5de | 2911 | else if (!MEM_P (op)) |
c5adc06a RK |
2912 | return 0; |
2913 | ||
998d7deb RH |
2914 | if (MEM_EXPR (op) != 0) |
2915 | return MEM_EXPR (op); | |
c5adc06a RK |
2916 | |
2917 | /* Otherwise we have an address, so indicate it and look at the address. */ | |
2918 | *paddressp = 1; | |
2919 | op = XEXP (op, 0); | |
2920 | ||
2921 | /* First check if we have a decl for the address, then look at the right side | |
2922 | if it is a PLUS. Otherwise, strip off arithmetic and keep looking. | |
2923 | But don't allow the address to itself be indirect. */ | |
998d7deb RH |
2924 | if ((expr = get_mem_expr_from_op (op, &inner_addressp)) && ! inner_addressp) |
2925 | return expr; | |
c5adc06a | 2926 | else if (GET_CODE (op) == PLUS |
998d7deb RH |
2927 | && (expr = get_mem_expr_from_op (XEXP (op, 1), &inner_addressp))) |
2928 | return expr; | |
c5adc06a | 2929 | |
ec8e098d PB |
2930 | while (GET_RTX_CLASS (GET_CODE (op)) == RTX_UNARY |
2931 | || GET_RTX_CLASS (GET_CODE (op)) == RTX_BIN_ARITH) | |
c5adc06a RK |
2932 | op = XEXP (op, 0); |
2933 | ||
998d7deb RH |
2934 | expr = get_mem_expr_from_op (op, &inner_addressp); |
2935 | return inner_addressp ? 0 : expr; | |
c5adc06a | 2936 | } |
ff81832f | 2937 | |
4f9b4029 RK |
2938 | /* Output operand names for assembler instructions. OPERANDS is the |
2939 | operand vector, OPORDER is the order to write the operands, and NOPS | |
2940 | is the number of operands to write. */ | |
2941 | ||
2942 | static void | |
6cf9ac28 | 2943 | output_asm_operand_names (rtx *operands, int *oporder, int nops) |
4f9b4029 RK |
2944 | { |
2945 | int wrote = 0; | |
2946 | int i; | |
2947 | ||
2948 | for (i = 0; i < nops; i++) | |
2949 | { | |
2950 | int addressp; | |
a560d4d4 JH |
2951 | rtx op = operands[oporder[i]]; |
2952 | tree expr = get_mem_expr_from_op (op, &addressp); | |
4f9b4029 | 2953 | |
a560d4d4 JH |
2954 | fprintf (asm_out_file, "%c%s", |
2955 | wrote ? ',' : '\t', wrote ? "" : ASM_COMMENT_START); | |
2956 | wrote = 1; | |
998d7deb | 2957 | if (expr) |
4f9b4029 | 2958 | { |
a560d4d4 | 2959 | fprintf (asm_out_file, "%s", |
998d7deb RH |
2960 | addressp ? "*" : ""); |
2961 | print_mem_expr (asm_out_file, expr); | |
4f9b4029 RK |
2962 | wrote = 1; |
2963 | } | |
a560d4d4 JH |
2964 | else if (REG_P (op) && ORIGINAL_REGNO (op) |
2965 | && ORIGINAL_REGNO (op) != REGNO (op)) | |
2966 | fprintf (asm_out_file, " tmp%i", ORIGINAL_REGNO (op)); | |
4f9b4029 RK |
2967 | } |
2968 | } | |
2969 | ||
3cf2715d DE |
2970 | /* Output text from TEMPLATE to the assembler output file, |
2971 | obeying %-directions to substitute operands taken from | |
2972 | the vector OPERANDS. | |
2973 | ||
2974 | %N (for N a digit) means print operand N in usual manner. | |
2975 | %lN means require operand N to be a CODE_LABEL or LABEL_REF | |
2976 | and print the label name with no punctuation. | |
2977 | %cN means require operand N to be a constant | |
2978 | and print the constant expression with no punctuation. | |
2979 | %aN means expect operand N to be a memory address | |
2980 | (not a memory reference!) and print a reference | |
2981 | to that address. | |
2982 | %nN means expect operand N to be a constant | |
2983 | and print a constant expression for minus the value | |
2984 | of the operand, with no other punctuation. */ | |
2985 | ||
2986 | void | |
6cf9ac28 | 2987 | output_asm_insn (const char *template, rtx *operands) |
3cf2715d | 2988 | { |
b3694847 SS |
2989 | const char *p; |
2990 | int c; | |
8554d9a4 JJ |
2991 | #ifdef ASSEMBLER_DIALECT |
2992 | int dialect = 0; | |
2993 | #endif | |
0d4903b8 | 2994 | int oporder[MAX_RECOG_OPERANDS]; |
4f9b4029 | 2995 | char opoutput[MAX_RECOG_OPERANDS]; |
0d4903b8 | 2996 | int ops = 0; |
3cf2715d DE |
2997 | |
2998 | /* An insn may return a null string template | |
2999 | in a case where no assembler code is needed. */ | |
3000 | if (*template == 0) | |
3001 | return; | |
3002 | ||
4f9b4029 | 3003 | memset (opoutput, 0, sizeof opoutput); |
3cf2715d DE |
3004 | p = template; |
3005 | putc ('\t', asm_out_file); | |
3006 | ||
3007 | #ifdef ASM_OUTPUT_OPCODE | |
3008 | ASM_OUTPUT_OPCODE (asm_out_file, p); | |
3009 | #endif | |
3010 | ||
b729186a | 3011 | while ((c = *p++)) |
3cf2715d DE |
3012 | switch (c) |
3013 | { | |
3cf2715d | 3014 | case '\n': |
4f9b4029 RK |
3015 | if (flag_verbose_asm) |
3016 | output_asm_operand_names (operands, oporder, ops); | |
0d4903b8 RK |
3017 | if (flag_print_asm_name) |
3018 | output_asm_name (); | |
3019 | ||
4f9b4029 RK |
3020 | ops = 0; |
3021 | memset (opoutput, 0, sizeof opoutput); | |
3022 | ||
3cf2715d | 3023 | putc (c, asm_out_file); |
cb649530 | 3024 | #ifdef ASM_OUTPUT_OPCODE |
3cf2715d DE |
3025 | while ((c = *p) == '\t') |
3026 | { | |
3027 | putc (c, asm_out_file); | |
3028 | p++; | |
3029 | } | |
3030 | ASM_OUTPUT_OPCODE (asm_out_file, p); | |
3cf2715d | 3031 | #endif |
cb649530 | 3032 | break; |
3cf2715d DE |
3033 | |
3034 | #ifdef ASSEMBLER_DIALECT | |
3035 | case '{': | |
b729186a | 3036 | { |
b3694847 | 3037 | int i; |
f5d927c0 | 3038 | |
8554d9a4 JJ |
3039 | if (dialect) |
3040 | output_operand_lossage ("nested assembly dialect alternatives"); | |
3041 | else | |
3042 | dialect = 1; | |
3043 | ||
b729186a JL |
3044 | /* If we want the first dialect, do nothing. Otherwise, skip |
3045 | DIALECT_NUMBER of strings ending with '|'. */ | |
3046 | for (i = 0; i < dialect_number; i++) | |
3047 | { | |
463a8384 | 3048 | while (*p && *p != '}' && *p++ != '|') |
b729186a | 3049 | ; |
463a8384 BS |
3050 | if (*p == '}') |
3051 | break; | |
b729186a JL |
3052 | if (*p == '|') |
3053 | p++; | |
3054 | } | |
8554d9a4 JJ |
3055 | |
3056 | if (*p == '\0') | |
3057 | output_operand_lossage ("unterminated assembly dialect alternative"); | |
b729186a | 3058 | } |
3cf2715d DE |
3059 | break; |
3060 | ||
3061 | case '|': | |
8554d9a4 JJ |
3062 | if (dialect) |
3063 | { | |
3064 | /* Skip to close brace. */ | |
3065 | do | |
3066 | { | |
3067 | if (*p == '\0') | |
3068 | { | |
3069 | output_operand_lossage ("unterminated assembly dialect alternative"); | |
3070 | break; | |
3071 | } | |
ff81832f | 3072 | } |
8554d9a4 JJ |
3073 | while (*p++ != '}'); |
3074 | dialect = 0; | |
3075 | } | |
3076 | else | |
3077 | putc (c, asm_out_file); | |
3cf2715d DE |
3078 | break; |
3079 | ||
3080 | case '}': | |
8554d9a4 JJ |
3081 | if (! dialect) |
3082 | putc (c, asm_out_file); | |
3083 | dialect = 0; | |
3cf2715d DE |
3084 | break; |
3085 | #endif | |
3086 | ||
3087 | case '%': | |
3088 | /* %% outputs a single %. */ | |
3089 | if (*p == '%') | |
3090 | { | |
3091 | p++; | |
3092 | putc (c, asm_out_file); | |
3093 | } | |
3094 | /* %= outputs a number which is unique to each insn in the entire | |
3095 | compilation. This is useful for making local labels that are | |
3096 | referred to more than once in a given insn. */ | |
3097 | else if (*p == '=') | |
3098 | { | |
3099 | p++; | |
3100 | fprintf (asm_out_file, "%d", insn_counter); | |
3101 | } | |
3102 | /* % followed by a letter and some digits | |
3103 | outputs an operand in a special way depending on the letter. | |
3104 | Letters `acln' are implemented directly. | |
3105 | Other letters are passed to `output_operand' so that | |
3106 | the PRINT_OPERAND macro can define them. */ | |
0df6c2c7 | 3107 | else if (ISALPHA (*p)) |
3cf2715d DE |
3108 | { |
3109 | int letter = *p++; | |
3110 | c = atoi (p); | |
3111 | ||
0df6c2c7 | 3112 | if (! ISDIGIT (*p)) |
a52453cc | 3113 | output_operand_lossage ("operand number missing after %%-letter"); |
0d4903b8 RK |
3114 | else if (this_is_asm_operands |
3115 | && (c < 0 || (unsigned int) c >= insn_noperands)) | |
3cf2715d DE |
3116 | output_operand_lossage ("operand number out of range"); |
3117 | else if (letter == 'l') | |
3118 | output_asm_label (operands[c]); | |
3119 | else if (letter == 'a') | |
3120 | output_address (operands[c]); | |
3121 | else if (letter == 'c') | |
3122 | { | |
3123 | if (CONSTANT_ADDRESS_P (operands[c])) | |
3124 | output_addr_const (asm_out_file, operands[c]); | |
3125 | else | |
3126 | output_operand (operands[c], 'c'); | |
3127 | } | |
3128 | else if (letter == 'n') | |
3129 | { | |
3130 | if (GET_CODE (operands[c]) == CONST_INT) | |
21e3a81b | 3131 | fprintf (asm_out_file, HOST_WIDE_INT_PRINT_DEC, |
3cf2715d DE |
3132 | - INTVAL (operands[c])); |
3133 | else | |
3134 | { | |
3135 | putc ('-', asm_out_file); | |
3136 | output_addr_const (asm_out_file, operands[c]); | |
3137 | } | |
3138 | } | |
3139 | else | |
3140 | output_operand (operands[c], letter); | |
f5d927c0 | 3141 | |
4f9b4029 RK |
3142 | if (!opoutput[c]) |
3143 | oporder[ops++] = c; | |
3144 | opoutput[c] = 1; | |
0d4903b8 | 3145 | |
0df6c2c7 | 3146 | while (ISDIGIT (c = *p)) |
f5d927c0 | 3147 | p++; |
3cf2715d DE |
3148 | } |
3149 | /* % followed by a digit outputs an operand the default way. */ | |
0df6c2c7 | 3150 | else if (ISDIGIT (*p)) |
3cf2715d DE |
3151 | { |
3152 | c = atoi (p); | |
f5d927c0 KH |
3153 | if (this_is_asm_operands |
3154 | && (c < 0 || (unsigned int) c >= insn_noperands)) | |
3cf2715d DE |
3155 | output_operand_lossage ("operand number out of range"); |
3156 | else | |
3157 | output_operand (operands[c], 0); | |
0d4903b8 | 3158 | |
4f9b4029 RK |
3159 | if (!opoutput[c]) |
3160 | oporder[ops++] = c; | |
3161 | opoutput[c] = 1; | |
3162 | ||
0df6c2c7 | 3163 | while (ISDIGIT (c = *p)) |
f5d927c0 | 3164 | p++; |
3cf2715d DE |
3165 | } |
3166 | /* % followed by punctuation: output something for that | |
3167 | punctuation character alone, with no operand. | |
3168 | The PRINT_OPERAND macro decides what is actually done. */ | |
3169 | #ifdef PRINT_OPERAND_PUNCT_VALID_P | |
f5d927c0 | 3170 | else if (PRINT_OPERAND_PUNCT_VALID_P ((unsigned char) *p)) |
3cf2715d DE |
3171 | output_operand (NULL_RTX, *p++); |
3172 | #endif | |
3173 | else | |
3174 | output_operand_lossage ("invalid %%-code"); | |
3175 | break; | |
3176 | ||
3177 | default: | |
3178 | putc (c, asm_out_file); | |
3179 | } | |
3180 | ||
0d4903b8 RK |
3181 | /* Write out the variable names for operands, if we know them. */ |
3182 | if (flag_verbose_asm) | |
4f9b4029 | 3183 | output_asm_operand_names (operands, oporder, ops); |
0d4903b8 RK |
3184 | if (flag_print_asm_name) |
3185 | output_asm_name (); | |
3cf2715d DE |
3186 | |
3187 | putc ('\n', asm_out_file); | |
3188 | } | |
3189 | \f | |
3190 | /* Output a LABEL_REF, or a bare CODE_LABEL, as an assembler symbol. */ | |
3191 | ||
3192 | void | |
6cf9ac28 | 3193 | output_asm_label (rtx x) |
3cf2715d DE |
3194 | { |
3195 | char buf[256]; | |
3196 | ||
3197 | if (GET_CODE (x) == LABEL_REF) | |
be1bb652 RH |
3198 | x = XEXP (x, 0); |
3199 | if (GET_CODE (x) == CODE_LABEL | |
3200 | || (GET_CODE (x) == NOTE | |
3201 | && NOTE_LINE_NUMBER (x) == NOTE_INSN_DELETED_LABEL)) | |
3cf2715d DE |
3202 | ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (x)); |
3203 | else | |
a52453cc | 3204 | output_operand_lossage ("`%%l' operand isn't a label"); |
3cf2715d DE |
3205 | |
3206 | assemble_name (asm_out_file, buf); | |
3207 | } | |
3208 | ||
3209 | /* Print operand X using machine-dependent assembler syntax. | |
3210 | The macro PRINT_OPERAND is defined just to control this function. | |
3211 | CODE is a non-digit that preceded the operand-number in the % spec, | |
3212 | such as 'z' if the spec was `%z3'. CODE is 0 if there was no char | |
3213 | between the % and the digits. | |
3214 | When CODE is a non-letter, X is 0. | |
3215 | ||
3216 | The meanings of the letters are machine-dependent and controlled | |
3217 | by PRINT_OPERAND. */ | |
3218 | ||
3219 | static void | |
6cf9ac28 | 3220 | output_operand (rtx x, int code ATTRIBUTE_UNUSED) |
3cf2715d DE |
3221 | { |
3222 | if (x && GET_CODE (x) == SUBREG) | |
49d801d3 | 3223 | x = alter_subreg (&x); |
3cf2715d DE |
3224 | |
3225 | /* If X is a pseudo-register, abort now rather than writing trash to the | |
3226 | assembler file. */ | |
3227 | ||
f8cfc6aa | 3228 | if (x && REG_P (x) && REGNO (x) >= FIRST_PSEUDO_REGISTER) |
3cf2715d DE |
3229 | abort (); |
3230 | ||
3231 | PRINT_OPERAND (asm_out_file, x, code); | |
3232 | } | |
3233 | ||
3234 | /* Print a memory reference operand for address X | |
3235 | using machine-dependent assembler syntax. | |
3236 | The macro PRINT_OPERAND_ADDRESS exists just to control this function. */ | |
3237 | ||
3238 | void | |
6cf9ac28 | 3239 | output_address (rtx x) |
3cf2715d | 3240 | { |
49d801d3 | 3241 | walk_alter_subreg (&x); |
3cf2715d DE |
3242 | PRINT_OPERAND_ADDRESS (asm_out_file, x); |
3243 | } | |
3244 | \f | |
3245 | /* Print an integer constant expression in assembler syntax. | |
3246 | Addition and subtraction are the only arithmetic | |
3247 | that may appear in these expressions. */ | |
3248 | ||
3249 | void | |
6cf9ac28 | 3250 | output_addr_const (FILE *file, rtx x) |
3cf2715d DE |
3251 | { |
3252 | char buf[256]; | |
3253 | ||
3254 | restart: | |
3255 | switch (GET_CODE (x)) | |
3256 | { | |
3257 | case PC: | |
eac50d7a | 3258 | putc ('.', file); |
3cf2715d DE |
3259 | break; |
3260 | ||
3261 | case SYMBOL_REF: | |
bb9a388d ZW |
3262 | if (SYMBOL_REF_DECL (x)) |
3263 | mark_decl_referenced (SYMBOL_REF_DECL (x)); | |
99c8c61c AO |
3264 | #ifdef ASM_OUTPUT_SYMBOL_REF |
3265 | ASM_OUTPUT_SYMBOL_REF (file, x); | |
3266 | #else | |
3cf2715d | 3267 | assemble_name (file, XSTR (x, 0)); |
99c8c61c | 3268 | #endif |
3cf2715d DE |
3269 | break; |
3270 | ||
3271 | case LABEL_REF: | |
422be3c3 AO |
3272 | x = XEXP (x, 0); |
3273 | /* Fall through. */ | |
3cf2715d DE |
3274 | case CODE_LABEL: |
3275 | ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (x)); | |
2f0b7af6 GK |
3276 | #ifdef ASM_OUTPUT_LABEL_REF |
3277 | ASM_OUTPUT_LABEL_REF (file, buf); | |
3278 | #else | |
3cf2715d | 3279 | assemble_name (file, buf); |
2f0b7af6 | 3280 | #endif |
3cf2715d DE |
3281 | break; |
3282 | ||
3283 | case CONST_INT: | |
21e3a81b | 3284 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x)); |
3cf2715d DE |
3285 | break; |
3286 | ||
3287 | case CONST: | |
3288 | /* This used to output parentheses around the expression, | |
3289 | but that does not work on the 386 (either ATT or BSD assembler). */ | |
3290 | output_addr_const (file, XEXP (x, 0)); | |
3291 | break; | |
3292 | ||
3293 | case CONST_DOUBLE: | |
3294 | if (GET_MODE (x) == VOIDmode) | |
3295 | { | |
3296 | /* We can use %d if the number is one word and positive. */ | |
3297 | if (CONST_DOUBLE_HIGH (x)) | |
21e3a81b | 3298 | fprintf (file, HOST_WIDE_INT_PRINT_DOUBLE_HEX, |
3cf2715d | 3299 | CONST_DOUBLE_HIGH (x), CONST_DOUBLE_LOW (x)); |
f5d927c0 | 3300 | else if (CONST_DOUBLE_LOW (x) < 0) |
21e3a81b | 3301 | fprintf (file, HOST_WIDE_INT_PRINT_HEX, CONST_DOUBLE_LOW (x)); |
3cf2715d | 3302 | else |
21e3a81b | 3303 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x)); |
3cf2715d DE |
3304 | } |
3305 | else | |
3306 | /* We can't handle floating point constants; | |
3307 | PRINT_OPERAND must handle them. */ | |
3308 | output_operand_lossage ("floating constant misused"); | |
3309 | break; | |
3310 | ||
3311 | case PLUS: | |
3312 | /* Some assemblers need integer constants to appear last (eg masm). */ | |
3313 | if (GET_CODE (XEXP (x, 0)) == CONST_INT) | |
3314 | { | |
3315 | output_addr_const (file, XEXP (x, 1)); | |
3316 | if (INTVAL (XEXP (x, 0)) >= 0) | |
3317 | fprintf (file, "+"); | |
3318 | output_addr_const (file, XEXP (x, 0)); | |
3319 | } | |
3320 | else | |
3321 | { | |
3322 | output_addr_const (file, XEXP (x, 0)); | |
08106825 AO |
3323 | if (GET_CODE (XEXP (x, 1)) != CONST_INT |
3324 | || INTVAL (XEXP (x, 1)) >= 0) | |
3cf2715d DE |
3325 | fprintf (file, "+"); |
3326 | output_addr_const (file, XEXP (x, 1)); | |
3327 | } | |
3328 | break; | |
3329 | ||
3330 | case MINUS: | |
3331 | /* Avoid outputting things like x-x or x+5-x, | |
3332 | since some assemblers can't handle that. */ | |
3333 | x = simplify_subtraction (x); | |
3334 | if (GET_CODE (x) != MINUS) | |
3335 | goto restart; | |
3336 | ||
3337 | output_addr_const (file, XEXP (x, 0)); | |
3338 | fprintf (file, "-"); | |
301d03af RS |
3339 | if ((GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) >= 0) |
3340 | || GET_CODE (XEXP (x, 1)) == PC | |
3341 | || GET_CODE (XEXP (x, 1)) == SYMBOL_REF) | |
3342 | output_addr_const (file, XEXP (x, 1)); | |
3343 | else | |
3cf2715d | 3344 | { |
17b53c33 | 3345 | fputs (targetm.asm_out.open_paren, file); |
3cf2715d | 3346 | output_addr_const (file, XEXP (x, 1)); |
17b53c33 | 3347 | fputs (targetm.asm_out.close_paren, file); |
3cf2715d | 3348 | } |
3cf2715d DE |
3349 | break; |
3350 | ||
3351 | case ZERO_EXTEND: | |
3352 | case SIGN_EXTEND: | |
fdf473ae | 3353 | case SUBREG: |
3cf2715d DE |
3354 | output_addr_const (file, XEXP (x, 0)); |
3355 | break; | |
3356 | ||
3357 | default: | |
422be3c3 AO |
3358 | #ifdef OUTPUT_ADDR_CONST_EXTRA |
3359 | OUTPUT_ADDR_CONST_EXTRA (file, x, fail); | |
3360 | break; | |
3361 | ||
3362 | fail: | |
3363 | #endif | |
3cf2715d DE |
3364 | output_operand_lossage ("invalid expression as operand"); |
3365 | } | |
3366 | } | |
3367 | \f | |
3368 | /* A poor man's fprintf, with the added features of %I, %R, %L, and %U. | |
3369 | %R prints the value of REGISTER_PREFIX. | |
3370 | %L prints the value of LOCAL_LABEL_PREFIX. | |
3371 | %U prints the value of USER_LABEL_PREFIX. | |
3372 | %I prints the value of IMMEDIATE_PREFIX. | |
3373 | %O runs ASM_OUTPUT_OPCODE to transform what follows in the string. | |
b1721339 | 3374 | Also supported are %d, %i, %u, %x, %X, %o, %c, %s and %%. |
3cf2715d DE |
3375 | |
3376 | We handle alternate assembler dialects here, just like output_asm_insn. */ | |
3377 | ||
3378 | void | |
e34d07f2 | 3379 | asm_fprintf (FILE *file, const char *p, ...) |
3cf2715d | 3380 | { |
3cf2715d DE |
3381 | char buf[10]; |
3382 | char *q, c; | |
e34d07f2 | 3383 | va_list argptr; |
6cf9ac28 | 3384 | |
e34d07f2 | 3385 | va_start (argptr, p); |
3cf2715d DE |
3386 | |
3387 | buf[0] = '%'; | |
3388 | ||
b729186a | 3389 | while ((c = *p++)) |
3cf2715d DE |
3390 | switch (c) |
3391 | { | |
3392 | #ifdef ASSEMBLER_DIALECT | |
3393 | case '{': | |
b729186a JL |
3394 | { |
3395 | int i; | |
3cf2715d | 3396 | |
b729186a JL |
3397 | /* If we want the first dialect, do nothing. Otherwise, skip |
3398 | DIALECT_NUMBER of strings ending with '|'. */ | |
3399 | for (i = 0; i < dialect_number; i++) | |
3400 | { | |
3401 | while (*p && *p++ != '|') | |
3402 | ; | |
3403 | ||
3404 | if (*p == '|') | |
3405 | p++; | |
f5d927c0 | 3406 | } |
b729186a | 3407 | } |
3cf2715d DE |
3408 | break; |
3409 | ||
3410 | case '|': | |
3411 | /* Skip to close brace. */ | |
3412 | while (*p && *p++ != '}') | |
3413 | ; | |
3414 | break; | |
3415 | ||
3416 | case '}': | |
3417 | break; | |
3418 | #endif | |
3419 | ||
3420 | case '%': | |
3421 | c = *p++; | |
3422 | q = &buf[1]; | |
b1721339 KG |
3423 | while (strchr ("-+ #0", c)) |
3424 | { | |
3425 | *q++ = c; | |
3426 | c = *p++; | |
3427 | } | |
0df6c2c7 | 3428 | while (ISDIGIT (c) || c == '.') |
3cf2715d DE |
3429 | { |
3430 | *q++ = c; | |
3431 | c = *p++; | |
3432 | } | |
3433 | switch (c) | |
3434 | { | |
3435 | case '%': | |
b1721339 | 3436 | putc ('%', file); |
3cf2715d DE |
3437 | break; |
3438 | ||
3439 | case 'd': case 'i': case 'u': | |
b1721339 KG |
3440 | case 'x': case 'X': case 'o': |
3441 | case 'c': | |
3cf2715d DE |
3442 | *q++ = c; |
3443 | *q = 0; | |
3444 | fprintf (file, buf, va_arg (argptr, int)); | |
3445 | break; | |
3446 | ||
3447 | case 'w': | |
b1721339 KG |
3448 | /* This is a prefix to the 'd', 'i', 'u', 'x', 'X', and |
3449 | 'o' cases, but we do not check for those cases. It | |
3450 | means that the value is a HOST_WIDE_INT, which may be | |
3451 | either `long' or `long long'. */ | |
85f015e1 KG |
3452 | memcpy (q, HOST_WIDE_INT_PRINT, strlen (HOST_WIDE_INT_PRINT)); |
3453 | q += strlen (HOST_WIDE_INT_PRINT); | |
3cf2715d DE |
3454 | *q++ = *p++; |
3455 | *q = 0; | |
3456 | fprintf (file, buf, va_arg (argptr, HOST_WIDE_INT)); | |
3457 | break; | |
3458 | ||
3459 | case 'l': | |
3460 | *q++ = c; | |
b1721339 KG |
3461 | #ifdef HAVE_LONG_LONG |
3462 | if (*p == 'l') | |
3463 | { | |
3464 | *q++ = *p++; | |
3465 | *q++ = *p++; | |
3466 | *q = 0; | |
3467 | fprintf (file, buf, va_arg (argptr, long long)); | |
3468 | } | |
3469 | else | |
3470 | #endif | |
3471 | { | |
3472 | *q++ = *p++; | |
3473 | *q = 0; | |
3474 | fprintf (file, buf, va_arg (argptr, long)); | |
3475 | } | |
6cf9ac28 | 3476 | |
3cf2715d DE |
3477 | break; |
3478 | ||
3479 | case 's': | |
3480 | *q++ = c; | |
3481 | *q = 0; | |
3482 | fprintf (file, buf, va_arg (argptr, char *)); | |
3483 | break; | |
3484 | ||
3485 | case 'O': | |
3486 | #ifdef ASM_OUTPUT_OPCODE | |
3487 | ASM_OUTPUT_OPCODE (asm_out_file, p); | |
3488 | #endif | |
3489 | break; | |
3490 | ||
3491 | case 'R': | |
3492 | #ifdef REGISTER_PREFIX | |
3493 | fprintf (file, "%s", REGISTER_PREFIX); | |
3494 | #endif | |
3495 | break; | |
3496 | ||
3497 | case 'I': | |
3498 | #ifdef IMMEDIATE_PREFIX | |
3499 | fprintf (file, "%s", IMMEDIATE_PREFIX); | |
3500 | #endif | |
3501 | break; | |
3502 | ||
3503 | case 'L': | |
3504 | #ifdef LOCAL_LABEL_PREFIX | |
3505 | fprintf (file, "%s", LOCAL_LABEL_PREFIX); | |
3506 | #endif | |
3507 | break; | |
3508 | ||
3509 | case 'U': | |
19283265 | 3510 | fputs (user_label_prefix, file); |
3cf2715d DE |
3511 | break; |
3512 | ||
fe0503ea | 3513 | #ifdef ASM_FPRINTF_EXTENSIONS |
7ef0daad | 3514 | /* Uppercase letters are reserved for general use by asm_fprintf |
fe0503ea NC |
3515 | and so are not available to target specific code. In order to |
3516 | prevent the ASM_FPRINTF_EXTENSIONS macro from using them then, | |
3517 | they are defined here. As they get turned into real extensions | |
3518 | to asm_fprintf they should be removed from this list. */ | |
3519 | case 'A': case 'B': case 'C': case 'D': case 'E': | |
3520 | case 'F': case 'G': case 'H': case 'J': case 'K': | |
3521 | case 'M': case 'N': case 'P': case 'Q': case 'S': | |
3522 | case 'T': case 'V': case 'W': case 'Y': case 'Z': | |
3523 | break; | |
f5d927c0 | 3524 | |
fe0503ea NC |
3525 | ASM_FPRINTF_EXTENSIONS (file, argptr, p) |
3526 | #endif | |
3cf2715d DE |
3527 | default: |
3528 | abort (); | |
3529 | } | |
3530 | break; | |
3531 | ||
3532 | default: | |
b1721339 | 3533 | putc (c, file); |
3cf2715d | 3534 | } |
e34d07f2 | 3535 | va_end (argptr); |
3cf2715d DE |
3536 | } |
3537 | \f | |
3538 | /* Split up a CONST_DOUBLE or integer constant rtx | |
3539 | into two rtx's for single words, | |
3540 | storing in *FIRST the word that comes first in memory in the target | |
3541 | and in *SECOND the other. */ | |
3542 | ||
3543 | void | |
6cf9ac28 | 3544 | split_double (rtx value, rtx *first, rtx *second) |
3cf2715d DE |
3545 | { |
3546 | if (GET_CODE (value) == CONST_INT) | |
3547 | { | |
5a1a6efd | 3548 | if (HOST_BITS_PER_WIDE_INT >= (2 * BITS_PER_WORD)) |
f76b9db2 | 3549 | { |
5a1a6efd | 3550 | /* In this case the CONST_INT holds both target words. |
27eef9ce JC |
3551 | Extract the bits from it into two word-sized pieces. |
3552 | Sign extend each half to HOST_WIDE_INT. */ | |
7f251dee AO |
3553 | unsigned HOST_WIDE_INT low, high; |
3554 | unsigned HOST_WIDE_INT mask, sign_bit, sign_extend; | |
3555 | ||
3556 | /* Set sign_bit to the most significant bit of a word. */ | |
3557 | sign_bit = 1; | |
3558 | sign_bit <<= BITS_PER_WORD - 1; | |
3559 | ||
3560 | /* Set mask so that all bits of the word are set. We could | |
3561 | have used 1 << BITS_PER_WORD instead of basing the | |
3562 | calculation on sign_bit. However, on machines where | |
3563 | HOST_BITS_PER_WIDE_INT == BITS_PER_WORD, it could cause a | |
3564 | compiler warning, even though the code would never be | |
3565 | executed. */ | |
3566 | mask = sign_bit << 1; | |
3567 | mask--; | |
3568 | ||
3569 | /* Set sign_extend as any remaining bits. */ | |
3570 | sign_extend = ~mask; | |
f5d927c0 | 3571 | |
7f251dee AO |
3572 | /* Pick the lower word and sign-extend it. */ |
3573 | low = INTVAL (value); | |
3574 | low &= mask; | |
3575 | if (low & sign_bit) | |
3576 | low |= sign_extend; | |
3577 | ||
3578 | /* Pick the higher word, shifted to the least significant | |
3579 | bits, and sign-extend it. */ | |
3580 | high = INTVAL (value); | |
3581 | high >>= BITS_PER_WORD - 1; | |
3582 | high >>= 1; | |
3583 | high &= mask; | |
3584 | if (high & sign_bit) | |
3585 | high |= sign_extend; | |
3586 | ||
3587 | /* Store the words in the target machine order. */ | |
5a1a6efd RK |
3588 | if (WORDS_BIG_ENDIAN) |
3589 | { | |
7f251dee AO |
3590 | *first = GEN_INT (high); |
3591 | *second = GEN_INT (low); | |
5a1a6efd RK |
3592 | } |
3593 | else | |
3594 | { | |
7f251dee AO |
3595 | *first = GEN_INT (low); |
3596 | *second = GEN_INT (high); | |
5a1a6efd | 3597 | } |
f76b9db2 ILT |
3598 | } |
3599 | else | |
3600 | { | |
5a1a6efd RK |
3601 | /* The rule for using CONST_INT for a wider mode |
3602 | is that we regard the value as signed. | |
3603 | So sign-extend it. */ | |
3604 | rtx high = (INTVAL (value) < 0 ? constm1_rtx : const0_rtx); | |
3605 | if (WORDS_BIG_ENDIAN) | |
3606 | { | |
3607 | *first = high; | |
3608 | *second = value; | |
3609 | } | |
3610 | else | |
3611 | { | |
3612 | *first = value; | |
3613 | *second = high; | |
3614 | } | |
f76b9db2 | 3615 | } |
3cf2715d DE |
3616 | } |
3617 | else if (GET_CODE (value) != CONST_DOUBLE) | |
3618 | { | |
f76b9db2 ILT |
3619 | if (WORDS_BIG_ENDIAN) |
3620 | { | |
3621 | *first = const0_rtx; | |
3622 | *second = value; | |
3623 | } | |
3624 | else | |
3625 | { | |
3626 | *first = value; | |
3627 | *second = const0_rtx; | |
3628 | } | |
3cf2715d DE |
3629 | } |
3630 | else if (GET_MODE (value) == VOIDmode | |
3631 | /* This is the old way we did CONST_DOUBLE integers. */ | |
3632 | || GET_MODE_CLASS (GET_MODE (value)) == MODE_INT) | |
3633 | { | |
3634 | /* In an integer, the words are defined as most and least significant. | |
3635 | So order them by the target's convention. */ | |
f76b9db2 ILT |
3636 | if (WORDS_BIG_ENDIAN) |
3637 | { | |
3638 | *first = GEN_INT (CONST_DOUBLE_HIGH (value)); | |
3639 | *second = GEN_INT (CONST_DOUBLE_LOW (value)); | |
3640 | } | |
3641 | else | |
3642 | { | |
3643 | *first = GEN_INT (CONST_DOUBLE_LOW (value)); | |
3644 | *second = GEN_INT (CONST_DOUBLE_HIGH (value)); | |
3645 | } | |
3cf2715d DE |
3646 | } |
3647 | else | |
3648 | { | |
f5d927c0 KH |
3649 | REAL_VALUE_TYPE r; |
3650 | long l[2]; | |
3cf2715d DE |
3651 | REAL_VALUE_FROM_CONST_DOUBLE (r, value); |
3652 | ||
3653 | /* Note, this converts the REAL_VALUE_TYPE to the target's | |
3654 | format, splits up the floating point double and outputs | |
3655 | exactly 32 bits of it into each of l[0] and l[1] -- | |
0f41302f | 3656 | not necessarily BITS_PER_WORD bits. */ |
3cf2715d DE |
3657 | REAL_VALUE_TO_TARGET_DOUBLE (r, l); |
3658 | ||
b5a3eb84 JW |
3659 | /* If 32 bits is an entire word for the target, but not for the host, |
3660 | then sign-extend on the host so that the number will look the same | |
3661 | way on the host that it would on the target. See for instance | |
3662 | simplify_unary_operation. The #if is needed to avoid compiler | |
3663 | warnings. */ | |
3664 | ||
3665 | #if HOST_BITS_PER_LONG > 32 | |
3666 | if (BITS_PER_WORD < HOST_BITS_PER_LONG && BITS_PER_WORD == 32) | |
3667 | { | |
3668 | if (l[0] & ((long) 1 << 31)) | |
3669 | l[0] |= ((long) (-1) << 32); | |
3670 | if (l[1] & ((long) 1 << 31)) | |
3671 | l[1] |= ((long) (-1) << 32); | |
3672 | } | |
3673 | #endif | |
3674 | ||
3cf2715d DE |
3675 | *first = GEN_INT ((HOST_WIDE_INT) l[0]); |
3676 | *second = GEN_INT ((HOST_WIDE_INT) l[1]); | |
3cf2715d DE |
3677 | } |
3678 | } | |
3679 | \f | |
3680 | /* Return nonzero if this function has no function calls. */ | |
3681 | ||
3682 | int | |
6cf9ac28 | 3683 | leaf_function_p (void) |
3cf2715d DE |
3684 | { |
3685 | rtx insn; | |
b660f82f | 3686 | rtx link; |
3cf2715d | 3687 | |
70f4f91c | 3688 | if (current_function_profile || profile_arc_flag) |
3cf2715d DE |
3689 | return 0; |
3690 | ||
3691 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) | |
3692 | { | |
7d167afd JJ |
3693 | if (GET_CODE (insn) == CALL_INSN |
3694 | && ! SIBLING_CALL_P (insn)) | |
3cf2715d DE |
3695 | return 0; |
3696 | if (GET_CODE (insn) == INSN | |
3697 | && GET_CODE (PATTERN (insn)) == SEQUENCE | |
0a1c58a2 JL |
3698 | && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == CALL_INSN |
3699 | && ! SIBLING_CALL_P (XVECEXP (PATTERN (insn), 0, 0))) | |
3cf2715d DE |
3700 | return 0; |
3701 | } | |
b660f82f JW |
3702 | for (link = current_function_epilogue_delay_list; |
3703 | link; | |
3704 | link = XEXP (link, 1)) | |
3cf2715d | 3705 | { |
b660f82f JW |
3706 | insn = XEXP (link, 0); |
3707 | ||
3708 | if (GET_CODE (insn) == CALL_INSN | |
7d167afd | 3709 | && ! SIBLING_CALL_P (insn)) |
3cf2715d | 3710 | return 0; |
b660f82f JW |
3711 | if (GET_CODE (insn) == INSN |
3712 | && GET_CODE (PATTERN (insn)) == SEQUENCE | |
3713 | && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == CALL_INSN | |
3714 | && ! SIBLING_CALL_P (XVECEXP (PATTERN (insn), 0, 0))) | |
3cf2715d DE |
3715 | return 0; |
3716 | } | |
3717 | ||
3718 | return 1; | |
3719 | } | |
3720 | ||
09da1532 | 3721 | /* Return 1 if branch is a forward branch. |
ef6257cd JH |
3722 | Uses insn_shuid array, so it works only in the final pass. May be used by |
3723 | output templates to customary add branch prediction hints. | |
3724 | */ | |
3725 | int | |
6cf9ac28 | 3726 | final_forward_branch_p (rtx insn) |
ef6257cd JH |
3727 | { |
3728 | int insn_id, label_id; | |
3729 | if (!uid_shuid) | |
3730 | abort (); | |
3731 | insn_id = INSN_SHUID (insn); | |
3732 | label_id = INSN_SHUID (JUMP_LABEL (insn)); | |
3733 | /* We've hit some insns that does not have id information available. */ | |
3734 | if (!insn_id || !label_id) | |
3735 | abort (); | |
3736 | return insn_id < label_id; | |
3737 | } | |
3738 | ||
3cf2715d DE |
3739 | /* On some machines, a function with no call insns |
3740 | can run faster if it doesn't create its own register window. | |
3741 | When output, the leaf function should use only the "output" | |
3742 | registers. Ordinarily, the function would be compiled to use | |
3743 | the "input" registers to find its arguments; it is a candidate | |
3744 | for leaf treatment if it uses only the "input" registers. | |
3745 | Leaf function treatment means renumbering so the function | |
3746 | uses the "output" registers instead. */ | |
3747 | ||
3748 | #ifdef LEAF_REGISTERS | |
3749 | ||
3cf2715d DE |
3750 | /* Return 1 if this function uses only the registers that can be |
3751 | safely renumbered. */ | |
3752 | ||
3753 | int | |
6cf9ac28 | 3754 | only_leaf_regs_used (void) |
3cf2715d DE |
3755 | { |
3756 | int i; | |
4977bab6 | 3757 | const char *const permitted_reg_in_leaf_functions = LEAF_REGISTERS; |
3cf2715d DE |
3758 | |
3759 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
e5e809f4 JL |
3760 | if ((regs_ever_live[i] || global_regs[i]) |
3761 | && ! permitted_reg_in_leaf_functions[i]) | |
3762 | return 0; | |
3763 | ||
3764 | if (current_function_uses_pic_offset_table | |
3765 | && pic_offset_table_rtx != 0 | |
f8cfc6aa | 3766 | && REG_P (pic_offset_table_rtx) |
e5e809f4 JL |
3767 | && ! permitted_reg_in_leaf_functions[REGNO (pic_offset_table_rtx)]) |
3768 | return 0; | |
3769 | ||
3cf2715d DE |
3770 | return 1; |
3771 | } | |
3772 | ||
3773 | /* Scan all instructions and renumber all registers into those | |
3774 | available in leaf functions. */ | |
3775 | ||
3776 | static void | |
6cf9ac28 | 3777 | leaf_renumber_regs (rtx first) |
3cf2715d DE |
3778 | { |
3779 | rtx insn; | |
3780 | ||
3781 | /* Renumber only the actual patterns. | |
3782 | The reg-notes can contain frame pointer refs, | |
3783 | and renumbering them could crash, and should not be needed. */ | |
3784 | for (insn = first; insn; insn = NEXT_INSN (insn)) | |
2c3c49de | 3785 | if (INSN_P (insn)) |
3cf2715d | 3786 | leaf_renumber_regs_insn (PATTERN (insn)); |
f5d927c0 KH |
3787 | for (insn = current_function_epilogue_delay_list; |
3788 | insn; | |
3789 | insn = XEXP (insn, 1)) | |
2c3c49de | 3790 | if (INSN_P (XEXP (insn, 0))) |
3cf2715d DE |
3791 | leaf_renumber_regs_insn (PATTERN (XEXP (insn, 0))); |
3792 | } | |
3793 | ||
3794 | /* Scan IN_RTX and its subexpressions, and renumber all regs into those | |
3795 | available in leaf functions. */ | |
3796 | ||
3797 | void | |
6cf9ac28 | 3798 | leaf_renumber_regs_insn (rtx in_rtx) |
3cf2715d | 3799 | { |
b3694847 SS |
3800 | int i, j; |
3801 | const char *format_ptr; | |
3cf2715d DE |
3802 | |
3803 | if (in_rtx == 0) | |
3804 | return; | |
3805 | ||
3806 | /* Renumber all input-registers into output-registers. | |
3807 | renumbered_regs would be 1 for an output-register; | |
3808 | they */ | |
3809 | ||
f8cfc6aa | 3810 | if (REG_P (in_rtx)) |
3cf2715d DE |
3811 | { |
3812 | int newreg; | |
3813 | ||
3814 | /* Don't renumber the same reg twice. */ | |
3815 | if (in_rtx->used) | |
3816 | return; | |
3817 | ||
3818 | newreg = REGNO (in_rtx); | |
3819 | /* Don't try to renumber pseudo regs. It is possible for a pseudo reg | |
3820 | to reach here as part of a REG_NOTE. */ | |
3821 | if (newreg >= FIRST_PSEUDO_REGISTER) | |
3822 | { | |
3823 | in_rtx->used = 1; | |
3824 | return; | |
3825 | } | |
3826 | newreg = LEAF_REG_REMAP (newreg); | |
3827 | if (newreg < 0) | |
3828 | abort (); | |
3829 | regs_ever_live[REGNO (in_rtx)] = 0; | |
3830 | regs_ever_live[newreg] = 1; | |
3831 | REGNO (in_rtx) = newreg; | |
3832 | in_rtx->used = 1; | |
3833 | } | |
3834 | ||
2c3c49de | 3835 | if (INSN_P (in_rtx)) |
3cf2715d DE |
3836 | { |
3837 | /* Inside a SEQUENCE, we find insns. | |
3838 | Renumber just the patterns of these insns, | |
3839 | just as we do for the top-level insns. */ | |
3840 | leaf_renumber_regs_insn (PATTERN (in_rtx)); | |
3841 | return; | |
3842 | } | |
3843 | ||
3844 | format_ptr = GET_RTX_FORMAT (GET_CODE (in_rtx)); | |
3845 | ||
3846 | for (i = 0; i < GET_RTX_LENGTH (GET_CODE (in_rtx)); i++) | |
3847 | switch (*format_ptr++) | |
3848 | { | |
3849 | case 'e': | |
3850 | leaf_renumber_regs_insn (XEXP (in_rtx, i)); | |
3851 | break; | |
3852 | ||
3853 | case 'E': | |
3854 | if (NULL != XVEC (in_rtx, i)) | |
3855 | { | |
3856 | for (j = 0; j < XVECLEN (in_rtx, i); j++) | |
3857 | leaf_renumber_regs_insn (XVECEXP (in_rtx, i, j)); | |
3858 | } | |
3859 | break; | |
3860 | ||
3861 | case 'S': | |
3862 | case 's': | |
3863 | case '0': | |
3864 | case 'i': | |
3865 | case 'w': | |
3866 | case 'n': | |
3867 | case 'u': | |
3868 | break; | |
3869 | ||
3870 | default: | |
3871 | abort (); | |
3872 | } | |
3873 | } | |
3874 | #endif | |
6a08f7b3 DP |
3875 | |
3876 | ||
3877 | /* When -gused is used, emit debug info for only used symbols. But in | |
3878 | addition to the standard intercepted debug_hooks there are some direct | |
3879 | calls into this file, i.e., dbxout_symbol, dbxout_parms, and dbxout_reg_params. | |
3880 | Those routines may also be called from a higher level intercepted routine. So | |
3881 | to prevent recording data for an inner call to one of these for an intercept, | |
5d3cc252 | 3882 | we maintain an intercept nesting counter (debug_nesting). We only save the |
6a08f7b3 DP |
3883 | intercepted arguments if the nesting is 1. */ |
3884 | int debug_nesting = 0; | |
3885 | ||
3886 | static tree *symbol_queue; | |
3887 | int symbol_queue_index = 0; | |
3888 | static int symbol_queue_size = 0; | |
3889 | ||
3890 | /* Generate the symbols for any queued up type symbols we encountered | |
3891 | while generating the type info for some originally used symbol. | |
3892 | This might generate additional entries in the queue. Only when | |
3893 | the nesting depth goes to 0 is this routine called. */ | |
3894 | ||
3895 | void | |
6cf9ac28 | 3896 | debug_flush_symbol_queue (void) |
6a08f7b3 DP |
3897 | { |
3898 | int i; | |
6cf9ac28 | 3899 | |
6a08f7b3 DP |
3900 | /* Make sure that additionally queued items are not flushed |
3901 | prematurely. */ | |
6cf9ac28 | 3902 | |
6a08f7b3 | 3903 | ++debug_nesting; |
6cf9ac28 | 3904 | |
6a08f7b3 DP |
3905 | for (i = 0; i < symbol_queue_index; ++i) |
3906 | { | |
3907 | /* If we pushed queued symbols then such symbols are must be | |
3908 | output no matter what anyone else says. Specifically, | |
3909 | we need to make sure dbxout_symbol() thinks the symbol was | |
3910 | used and also we need to override TYPE_DECL_SUPPRESS_DEBUG | |
3911 | which may be set for outside reasons. */ | |
3912 | int saved_tree_used = TREE_USED (symbol_queue[i]); | |
3913 | int saved_suppress_debug = TYPE_DECL_SUPPRESS_DEBUG (symbol_queue[i]); | |
3914 | TREE_USED (symbol_queue[i]) = 1; | |
3915 | TYPE_DECL_SUPPRESS_DEBUG (symbol_queue[i]) = 0; | |
3916 | ||
3917 | #ifdef DBX_DEBUGGING_INFO | |
3918 | dbxout_symbol (symbol_queue[i], 0); | |
3919 | #endif | |
3920 | ||
3921 | TREE_USED (symbol_queue[i]) = saved_tree_used; | |
3922 | TYPE_DECL_SUPPRESS_DEBUG (symbol_queue[i]) = saved_suppress_debug; | |
3923 | } | |
3924 | ||
3925 | symbol_queue_index = 0; | |
6cf9ac28 | 3926 | --debug_nesting; |
6a08f7b3 DP |
3927 | } |
3928 | ||
3929 | /* Queue a type symbol needed as part of the definition of a decl | |
3930 | symbol. These symbols are generated when debug_flush_symbol_queue() | |
3931 | is called. */ | |
3932 | ||
6cf9ac28 | 3933 | void |
6a08f7b3 DP |
3934 | debug_queue_symbol (tree decl) |
3935 | { | |
6cf9ac28 | 3936 | if (symbol_queue_index >= symbol_queue_size) |
6a08f7b3 DP |
3937 | { |
3938 | symbol_queue_size += 10; | |
703ad42b KG |
3939 | symbol_queue = xrealloc (symbol_queue, |
3940 | symbol_queue_size * sizeof (tree)); | |
6a08f7b3 DP |
3941 | } |
3942 | ||
3943 | symbol_queue[symbol_queue_index++] = decl; | |
6cf9ac28 | 3944 | } |
6a08f7b3 | 3945 | |
f9da5064 | 3946 | /* Free symbol queue. */ |
6a08f7b3 | 3947 | void |
6cf9ac28 | 3948 | debug_free_queue (void) |
6a08f7b3 DP |
3949 | { |
3950 | if (symbol_queue) | |
3951 | { | |
3952 | free (symbol_queue); | |
3953 | symbol_queue = NULL; | |
3954 | symbol_queue_size = 0; | |
3955 | } | |
3956 | } |