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44037a66 TG |
1 | /* Medium-level subroutines: convert bit-field store and extract |
2 | and shifts, multiplies and divides to rtl instructions. | |
e54d80d0 | 3 | Copyright (C) 1987, 1988, 1989, 1992, 1993 Free Software Foundation, Inc. |
44037a66 TG |
4 | |
5 | This file is part of GNU CC. | |
6 | ||
7 | GNU CC is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2, or (at your option) | |
10 | any later version. | |
11 | ||
12 | GNU CC is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GNU CC; see the file COPYING. If not, write to | |
19 | the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ | |
20 | ||
21 | ||
22 | #include "config.h" | |
23 | #include "rtl.h" | |
24 | #include "tree.h" | |
25 | #include "flags.h" | |
26 | #include "insn-flags.h" | |
27 | #include "insn-codes.h" | |
28 | #include "insn-config.h" | |
29 | #include "expr.h" | |
30 | #include "real.h" | |
31 | #include "recog.h" | |
32 | ||
33 | static rtx extract_split_bit_field (); | |
34 | static rtx extract_fixed_bit_field (); | |
35 | static void store_split_bit_field (); | |
36 | static void store_fixed_bit_field (); | |
37 | static rtx mask_rtx (); | |
38 | static rtx lshift_value (); | |
39 | ||
40 | #define CEIL(x,y) (((x) + (y) - 1) / (y)) | |
41 | ||
44037a66 TG |
42 | /* Non-zero means divides or modulus operations are relatively cheap for |
43 | powers of two, so don't use branches; emit the operation instead. | |
44 | Usually, this will mean that the MD file will emit non-branch | |
45 | sequences. */ | |
46 | ||
47 | static int sdiv_pow2_cheap, smod_pow2_cheap; | |
48 | ||
e49a094d RS |
49 | /* For compilers that support multiple targets with different word sizes, |
50 | MAX_BITS_PER_WORD contains the biggest value of BITS_PER_WORD. An example | |
51 | is the H8/300(H) compiler. */ | |
52 | ||
53 | #ifndef MAX_BITS_PER_WORD | |
54 | #define MAX_BITS_PER_WORD BITS_PER_WORD | |
55 | #endif | |
56 | ||
44037a66 | 57 | /* Cost of various pieces of RTL. */ |
819126a6 | 58 | static int add_cost, negate_cost, zero_cost; |
e49a094d RS |
59 | static int shift_cost[MAX_BITS_PER_WORD]; |
60 | static int shiftadd_cost[MAX_BITS_PER_WORD]; | |
61 | static int shiftsub_cost[MAX_BITS_PER_WORD]; | |
44037a66 | 62 | |
44037a66 TG |
63 | void |
64 | init_expmed () | |
65 | { | |
b385aeda | 66 | char *free_point; |
44037a66 TG |
67 | /* This is "some random pseudo register" for purposes of calling recog |
68 | to see what insns exist. */ | |
69 | rtx reg = gen_rtx (REG, word_mode, FIRST_PSEUDO_REGISTER); | |
b385aeda | 70 | rtx shift_insn, shiftadd_insn, shiftsub_insn; |
b1ec3c92 | 71 | int dummy; |
7963ac37 | 72 | int m; |
44037a66 | 73 | |
b385aeda RK |
74 | start_sequence (); |
75 | ||
76 | /* Since we are on the permanent obstack, we must be sure we save this | |
77 | spot AFTER we call start_sequence, since it will reuse the rtl it | |
78 | makes. */ | |
79 | ||
80 | free_point = (char *) oballoc (0); | |
81 | ||
172a1cb0 | 82 | zero_cost = rtx_cost (const0_rtx, 0); |
aeedc93f | 83 | add_cost = rtx_cost (gen_rtx (PLUS, word_mode, reg, reg), SET); |
7963ac37 | 84 | |
b385aeda RK |
85 | shift_insn = emit_insn (gen_rtx (SET, VOIDmode, reg, |
86 | gen_rtx (ASHIFT, word_mode, reg, | |
87 | const0_rtx))); | |
88 | ||
89 | shiftadd_insn = emit_insn (gen_rtx (SET, VOIDmode, reg, | |
90 | gen_rtx (PLUS, word_mode, | |
91 | gen_rtx (MULT, word_mode, | |
92 | reg, const0_rtx), | |
93 | reg))); | |
94 | ||
95 | shiftsub_insn = emit_insn (gen_rtx (SET, VOIDmode, reg, | |
96 | gen_rtx (MINUS, word_mode, | |
97 | gen_rtx (MULT, word_mode, | |
98 | reg, const0_rtx), | |
99 | reg))); | |
7963ac37 RK |
100 | |
101 | init_recog (); | |
b385aeda RK |
102 | |
103 | shift_cost[0] = 0; | |
104 | shiftadd_cost[0] = shiftsub_cost[0] = add_cost; | |
105 | ||
7963ac37 RK |
106 | for (m = 1; m < BITS_PER_WORD; m++) |
107 | { | |
108 | shift_cost[m] = shiftadd_cost[m] = shiftsub_cost[m] = 32000; | |
b385aeda RK |
109 | |
110 | XEXP (SET_SRC (PATTERN (shift_insn)), 1) = GEN_INT (m); | |
111 | if (recog (PATTERN (shift_insn), shift_insn, &dummy) >= 0) | |
112 | shift_cost[m] = rtx_cost (SET_SRC (PATTERN (shift_insn)), SET); | |
113 | ||
114 | XEXP (XEXP (SET_SRC (PATTERN (shiftadd_insn)), 0), 1) | |
115 | = GEN_INT ((HOST_WIDE_INT) 1 << m); | |
116 | if (recog (PATTERN (shiftadd_insn), shiftadd_insn, &dummy) >= 0) | |
dac57de0 | 117 | shiftadd_cost[m] = rtx_cost (SET_SRC (PATTERN (shiftadd_insn)), SET); |
b385aeda RK |
118 | |
119 | XEXP (XEXP (SET_SRC (PATTERN (shiftsub_insn)), 0), 1) | |
120 | = GEN_INT ((HOST_WIDE_INT) 1 << m); | |
121 | if (recog (PATTERN (shiftsub_insn), shiftsub_insn, &dummy) >= 0) | |
dac57de0 | 122 | shiftsub_cost[m] = rtx_cost (SET_SRC (PATTERN (shiftsub_insn)), SET); |
7963ac37 RK |
123 | } |
124 | ||
aeedc93f | 125 | negate_cost = rtx_cost (gen_rtx (NEG, word_mode, reg), SET); |
44037a66 | 126 | |
44037a66 | 127 | sdiv_pow2_cheap |
b385aeda RK |
128 | = (rtx_cost (gen_rtx (DIV, word_mode, reg, GEN_INT (32)), SET) |
129 | <= 2 * add_cost); | |
44037a66 | 130 | smod_pow2_cheap |
b385aeda RK |
131 | = (rtx_cost (gen_rtx (MOD, word_mode, reg, GEN_INT (32)), SET) |
132 | <= 2 * add_cost); | |
44037a66 | 133 | |
44037a66 | 134 | /* Free the objects we just allocated. */ |
b385aeda | 135 | end_sequence (); |
44037a66 TG |
136 | obfree (free_point); |
137 | } | |
138 | ||
139 | /* Return an rtx representing minus the value of X. | |
140 | MODE is the intended mode of the result, | |
141 | useful if X is a CONST_INT. */ | |
142 | ||
143 | rtx | |
144 | negate_rtx (mode, x) | |
145 | enum machine_mode mode; | |
146 | rtx x; | |
147 | { | |
148 | if (GET_CODE (x) == CONST_INT) | |
149 | { | |
b1ec3c92 CH |
150 | HOST_WIDE_INT val = - INTVAL (x); |
151 | if (GET_MODE_BITSIZE (mode) < HOST_BITS_PER_WIDE_INT) | |
44037a66 TG |
152 | { |
153 | /* Sign extend the value from the bits that are significant. */ | |
b1ec3c92 CH |
154 | if (val & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))) |
155 | val |= (HOST_WIDE_INT) (-1) << GET_MODE_BITSIZE (mode); | |
44037a66 | 156 | else |
b1ec3c92 | 157 | val &= ((HOST_WIDE_INT) 1 << GET_MODE_BITSIZE (mode)) - 1; |
44037a66 | 158 | } |
b1ec3c92 | 159 | return GEN_INT (val); |
44037a66 TG |
160 | } |
161 | else | |
b1ec3c92 | 162 | return expand_unop (GET_MODE (x), neg_optab, x, NULL_RTX, 0); |
44037a66 TG |
163 | } |
164 | \f | |
165 | /* Generate code to store value from rtx VALUE | |
166 | into a bit-field within structure STR_RTX | |
167 | containing BITSIZE bits starting at bit BITNUM. | |
168 | FIELDMODE is the machine-mode of the FIELD_DECL node for this field. | |
169 | ALIGN is the alignment that STR_RTX is known to have, measured in bytes. | |
170 | TOTAL_SIZE is the size of the structure in bytes, or -1 if varying. */ | |
171 | ||
172 | /* ??? Note that there are two different ideas here for how | |
173 | to determine the size to count bits within, for a register. | |
174 | One is BITS_PER_WORD, and the other is the size of operand 3 | |
175 | of the insv pattern. (The latter assumes that an n-bit machine | |
176 | will be able to insert bit fields up to n bits wide.) | |
177 | It isn't certain that either of these is right. | |
178 | extract_bit_field has the same quandary. */ | |
179 | ||
180 | rtx | |
181 | store_bit_field (str_rtx, bitsize, bitnum, fieldmode, value, align, total_size) | |
182 | rtx str_rtx; | |
183 | register int bitsize; | |
184 | int bitnum; | |
185 | enum machine_mode fieldmode; | |
186 | rtx value; | |
187 | int align; | |
188 | int total_size; | |
189 | { | |
190 | int unit = (GET_CODE (str_rtx) == MEM) ? BITS_PER_UNIT : BITS_PER_WORD; | |
191 | register int offset = bitnum / unit; | |
192 | register int bitpos = bitnum % unit; | |
193 | register rtx op0 = str_rtx; | |
194 | ||
195 | if (GET_CODE (str_rtx) == MEM && ! MEM_IN_STRUCT_P (str_rtx)) | |
196 | abort (); | |
197 | ||
198 | /* Discount the part of the structure before the desired byte. | |
199 | We need to know how many bytes are safe to reference after it. */ | |
200 | if (total_size >= 0) | |
201 | total_size -= (bitpos / BIGGEST_ALIGNMENT | |
202 | * (BIGGEST_ALIGNMENT / BITS_PER_UNIT)); | |
203 | ||
204 | while (GET_CODE (op0) == SUBREG) | |
205 | { | |
206 | /* The following line once was done only if WORDS_BIG_ENDIAN, | |
207 | but I think that is a mistake. WORDS_BIG_ENDIAN is | |
208 | meaningful at a much higher level; when structures are copied | |
209 | between memory and regs, the higher-numbered regs | |
210 | always get higher addresses. */ | |
211 | offset += SUBREG_WORD (op0); | |
212 | /* We used to adjust BITPOS here, but now we do the whole adjustment | |
213 | right after the loop. */ | |
214 | op0 = SUBREG_REG (op0); | |
215 | } | |
216 | ||
217 | #if BYTES_BIG_ENDIAN | |
218 | /* If OP0 is a register, BITPOS must count within a word. | |
219 | But as we have it, it counts within whatever size OP0 now has. | |
220 | On a bigendian machine, these are not the same, so convert. */ | |
221 | if (GET_CODE (op0) != MEM && unit > GET_MODE_BITSIZE (GET_MODE (op0))) | |
222 | bitpos += unit - GET_MODE_BITSIZE (GET_MODE (op0)); | |
223 | #endif | |
224 | ||
225 | value = protect_from_queue (value, 0); | |
226 | ||
227 | if (flag_force_mem) | |
228 | value = force_not_mem (value); | |
229 | ||
230 | /* Note that the adjustment of BITPOS above has no effect on whether | |
231 | BITPOS is 0 in a REG bigger than a word. */ | |
56a2f049 RS |
232 | if (GET_MODE_SIZE (fieldmode) >= UNITS_PER_WORD |
233 | && (! STRICT_ALIGNMENT || GET_CODE (op0) != MEM) | |
44037a66 TG |
234 | && bitpos == 0 && bitsize == GET_MODE_BITSIZE (fieldmode)) |
235 | { | |
236 | /* Storing in a full-word or multi-word field in a register | |
237 | can be done with just SUBREG. */ | |
238 | if (GET_MODE (op0) != fieldmode) | |
56a2f049 RS |
239 | if (GET_CODE (op0) == REG) |
240 | op0 = gen_rtx (SUBREG, fieldmode, op0, offset); | |
241 | else | |
242 | op0 = change_address (op0, fieldmode, | |
243 | plus_constant (XEXP (op0, 0), offset)); | |
44037a66 TG |
244 | emit_move_insn (op0, value); |
245 | return value; | |
246 | } | |
247 | ||
248 | /* Storing an lsb-aligned field in a register | |
249 | can be done with a movestrict instruction. */ | |
250 | ||
251 | if (GET_CODE (op0) != MEM | |
252 | #if BYTES_BIG_ENDIAN | |
253 | && bitpos + bitsize == unit | |
254 | #else | |
255 | && bitpos == 0 | |
256 | #endif | |
257 | && bitsize == GET_MODE_BITSIZE (fieldmode) | |
258 | && (GET_MODE (op0) == fieldmode | |
259 | || (movstrict_optab->handlers[(int) fieldmode].insn_code | |
260 | != CODE_FOR_nothing))) | |
261 | { | |
262 | /* Get appropriate low part of the value being stored. */ | |
263 | if (GET_CODE (value) == CONST_INT || GET_CODE (value) == REG) | |
264 | value = gen_lowpart (fieldmode, value); | |
265 | else if (!(GET_CODE (value) == SYMBOL_REF | |
266 | || GET_CODE (value) == LABEL_REF | |
267 | || GET_CODE (value) == CONST)) | |
268 | value = convert_to_mode (fieldmode, value, 0); | |
269 | ||
270 | if (GET_MODE (op0) == fieldmode) | |
271 | emit_move_insn (op0, value); | |
272 | else | |
273 | { | |
274 | int icode = movstrict_optab->handlers[(int) fieldmode].insn_code; | |
275 | if(! (*insn_operand_predicate[icode][1]) (value, fieldmode)) | |
276 | value = copy_to_mode_reg (fieldmode, value); | |
277 | emit_insn (GEN_FCN (icode) | |
278 | (gen_rtx (SUBREG, fieldmode, op0, offset), value)); | |
279 | } | |
280 | return value; | |
281 | } | |
282 | ||
283 | /* Handle fields bigger than a word. */ | |
284 | ||
285 | if (bitsize > BITS_PER_WORD) | |
286 | { | |
287 | /* Here we transfer the words of the field | |
288 | in the order least significant first. | |
289 | This is because the most significant word is the one which may | |
290 | be less than full. */ | |
291 | ||
292 | int nwords = (bitsize + (BITS_PER_WORD - 1)) / BITS_PER_WORD; | |
293 | int i; | |
294 | ||
295 | /* This is the mode we must force value to, so that there will be enough | |
296 | subwords to extract. Note that fieldmode will often (always?) be | |
297 | VOIDmode, because that is what store_field uses to indicate that this | |
298 | is a bit field, but passing VOIDmode to operand_subword_force will | |
299 | result in an abort. */ | |
300 | fieldmode = mode_for_size (nwords * BITS_PER_WORD, MODE_INT, 0); | |
301 | ||
302 | for (i = 0; i < nwords; i++) | |
303 | { | |
304 | /* If I is 0, use the low-order word in both field and target; | |
305 | if I is 1, use the next to lowest word; and so on. */ | |
306 | int wordnum = (WORDS_BIG_ENDIAN ? nwords - i - 1 : i); | |
307 | int bit_offset = (WORDS_BIG_ENDIAN | |
308 | ? MAX (bitsize - (i + 1) * BITS_PER_WORD, 0) | |
309 | : i * BITS_PER_WORD); | |
310 | store_bit_field (op0, MIN (BITS_PER_WORD, | |
311 | bitsize - i * BITS_PER_WORD), | |
312 | bitnum + bit_offset, word_mode, | |
313 | operand_subword_force (value, wordnum, fieldmode), | |
314 | align, total_size); | |
315 | } | |
316 | return value; | |
317 | } | |
318 | ||
319 | /* From here on we can assume that the field to be stored in is | |
320 | a full-word (whatever type that is), since it is shorter than a word. */ | |
321 | ||
322 | /* OFFSET is the number of words or bytes (UNIT says which) | |
323 | from STR_RTX to the first word or byte containing part of the field. */ | |
324 | ||
325 | if (GET_CODE (op0) == REG) | |
326 | { | |
327 | if (offset != 0 | |
328 | || GET_MODE_SIZE (GET_MODE (op0)) > UNITS_PER_WORD) | |
329 | op0 = gen_rtx (SUBREG, TYPE_MODE (type_for_size (BITS_PER_WORD, 0)), | |
330 | op0, offset); | |
331 | offset = 0; | |
332 | } | |
333 | else | |
334 | { | |
335 | op0 = protect_from_queue (op0, 1); | |
336 | } | |
337 | ||
338 | /* Now OFFSET is nonzero only if OP0 is memory | |
339 | and is therefore always measured in bytes. */ | |
340 | ||
341 | #ifdef HAVE_insv | |
342 | if (HAVE_insv | |
343 | && !(bitsize == 1 && GET_CODE (value) == CONST_INT) | |
344 | /* Ensure insv's size is wide enough for this field. */ | |
345 | && (GET_MODE_BITSIZE (insn_operand_mode[(int) CODE_FOR_insv][3]) | |
346 | >= bitsize)) | |
347 | { | |
348 | int xbitpos = bitpos; | |
349 | rtx value1; | |
350 | rtx xop0 = op0; | |
351 | rtx last = get_last_insn (); | |
352 | rtx pat; | |
353 | enum machine_mode maxmode | |
354 | = insn_operand_mode[(int) CODE_FOR_insv][3]; | |
355 | ||
356 | int save_volatile_ok = volatile_ok; | |
357 | volatile_ok = 1; | |
358 | ||
359 | /* If this machine's insv can only insert into a register, or if we | |
360 | are to force MEMs into a register, copy OP0 into a register and | |
361 | save it back later. */ | |
362 | if (GET_CODE (op0) == MEM | |
363 | && (flag_force_mem | |
364 | || ! ((*insn_operand_predicate[(int) CODE_FOR_insv][0]) | |
365 | (op0, VOIDmode)))) | |
366 | { | |
367 | rtx tempreg; | |
368 | enum machine_mode bestmode; | |
369 | ||
370 | /* Get the mode to use for inserting into this field. If OP0 is | |
371 | BLKmode, get the smallest mode consistent with the alignment. If | |
372 | OP0 is a non-BLKmode object that is no wider than MAXMODE, use its | |
373 | mode. Otherwise, use the smallest mode containing the field. */ | |
374 | ||
375 | if (GET_MODE (op0) == BLKmode | |
376 | || GET_MODE_SIZE (GET_MODE (op0)) > GET_MODE_SIZE (maxmode)) | |
377 | bestmode | |
717702e6 RK |
378 | = get_best_mode (bitsize, bitnum, align * BITS_PER_UNIT, maxmode, |
379 | MEM_VOLATILE_P (op0)); | |
44037a66 TG |
380 | else |
381 | bestmode = GET_MODE (op0); | |
382 | ||
383 | if (bestmode == VOIDmode) | |
384 | goto insv_loses; | |
385 | ||
386 | /* Adjust address to point to the containing unit of that mode. */ | |
387 | unit = GET_MODE_BITSIZE (bestmode); | |
388 | /* Compute offset as multiple of this unit, counting in bytes. */ | |
389 | offset = (bitnum / unit) * GET_MODE_SIZE (bestmode); | |
390 | bitpos = bitnum % unit; | |
391 | op0 = change_address (op0, bestmode, | |
392 | plus_constant (XEXP (op0, 0), offset)); | |
393 | ||
394 | /* Fetch that unit, store the bitfield in it, then store the unit. */ | |
395 | tempreg = copy_to_reg (op0); | |
396 | store_bit_field (tempreg, bitsize, bitpos, fieldmode, value, | |
397 | align, total_size); | |
398 | emit_move_insn (op0, tempreg); | |
399 | return value; | |
400 | } | |
401 | volatile_ok = save_volatile_ok; | |
402 | ||
403 | /* Add OFFSET into OP0's address. */ | |
404 | if (GET_CODE (xop0) == MEM) | |
405 | xop0 = change_address (xop0, byte_mode, | |
406 | plus_constant (XEXP (xop0, 0), offset)); | |
407 | ||
408 | /* If xop0 is a register, we need it in MAXMODE | |
409 | to make it acceptable to the format of insv. */ | |
410 | if (GET_CODE (xop0) == SUBREG) | |
411 | PUT_MODE (xop0, maxmode); | |
412 | if (GET_CODE (xop0) == REG && GET_MODE (xop0) != maxmode) | |
413 | xop0 = gen_rtx (SUBREG, maxmode, xop0, 0); | |
414 | ||
415 | /* On big-endian machines, we count bits from the most significant. | |
416 | If the bit field insn does not, we must invert. */ | |
417 | ||
418 | #if BITS_BIG_ENDIAN != BYTES_BIG_ENDIAN | |
419 | xbitpos = unit - bitsize - xbitpos; | |
420 | #endif | |
421 | /* We have been counting XBITPOS within UNIT. | |
422 | Count instead within the size of the register. */ | |
423 | #if BITS_BIG_ENDIAN | |
424 | if (GET_CODE (xop0) != MEM) | |
425 | xbitpos += GET_MODE_BITSIZE (maxmode) - unit; | |
426 | #endif | |
427 | unit = GET_MODE_BITSIZE (maxmode); | |
428 | ||
429 | /* Convert VALUE to maxmode (which insv insn wants) in VALUE1. */ | |
430 | value1 = value; | |
431 | if (GET_MODE (value) != maxmode) | |
432 | { | |
433 | if (GET_MODE_BITSIZE (GET_MODE (value)) >= bitsize) | |
434 | { | |
435 | /* Optimization: Don't bother really extending VALUE | |
f5df292e RS |
436 | if it has all the bits we will actually use. However, |
437 | if we must narrow it, be sure we do it correctly. */ | |
44037a66 | 438 | |
f5df292e RS |
439 | if (GET_MODE_SIZE (GET_MODE (value)) < GET_MODE_SIZE (maxmode)) |
440 | { | |
441 | /* Avoid making subreg of a subreg, or of a mem. */ | |
442 | if (GET_CODE (value1) != REG) | |
44037a66 | 443 | value1 = copy_to_reg (value1); |
f5df292e RS |
444 | value1 = gen_rtx (SUBREG, maxmode, value1, 0); |
445 | } | |
446 | else | |
447 | value1 = gen_lowpart (maxmode, value1); | |
44037a66 TG |
448 | } |
449 | else if (!CONSTANT_P (value)) | |
450 | /* Parse phase is supposed to make VALUE's data type | |
451 | match that of the component reference, which is a type | |
452 | at least as wide as the field; so VALUE should have | |
453 | a mode that corresponds to that type. */ | |
454 | abort (); | |
455 | } | |
456 | ||
457 | /* If this machine's insv insists on a register, | |
458 | get VALUE1 into a register. */ | |
459 | if (! ((*insn_operand_predicate[(int) CODE_FOR_insv][3]) | |
460 | (value1, maxmode))) | |
461 | value1 = force_reg (maxmode, value1); | |
462 | ||
b1ec3c92 | 463 | pat = gen_insv (xop0, GEN_INT (bitsize), GEN_INT (xbitpos), value1); |
44037a66 TG |
464 | if (pat) |
465 | emit_insn (pat); | |
466 | else | |
467 | { | |
468 | delete_insns_since (last); | |
469 | store_fixed_bit_field (op0, offset, bitsize, bitpos, value, align); | |
470 | } | |
471 | } | |
472 | else | |
473 | insv_loses: | |
474 | #endif | |
475 | /* Insv is not available; store using shifts and boolean ops. */ | |
476 | store_fixed_bit_field (op0, offset, bitsize, bitpos, value, align); | |
477 | return value; | |
478 | } | |
479 | \f | |
480 | /* Use shifts and boolean operations to store VALUE | |
481 | into a bit field of width BITSIZE | |
482 | in a memory location specified by OP0 except offset by OFFSET bytes. | |
483 | (OFFSET must be 0 if OP0 is a register.) | |
484 | The field starts at position BITPOS within the byte. | |
485 | (If OP0 is a register, it may be a full word or a narrower mode, | |
486 | but BITPOS still counts within a full word, | |
487 | which is significant on bigendian machines.) | |
488 | STRUCT_ALIGN is the alignment the structure is known to have (in bytes). | |
489 | ||
490 | Note that protect_from_queue has already been done on OP0 and VALUE. */ | |
491 | ||
492 | static void | |
493 | store_fixed_bit_field (op0, offset, bitsize, bitpos, value, struct_align) | |
494 | register rtx op0; | |
495 | register int offset, bitsize, bitpos; | |
496 | register rtx value; | |
497 | int struct_align; | |
498 | { | |
499 | register enum machine_mode mode; | |
500 | int total_bits = BITS_PER_WORD; | |
501 | rtx subtarget, temp; | |
502 | int all_zero = 0; | |
503 | int all_one = 0; | |
504 | ||
44037a66 TG |
505 | /* There is a case not handled here: |
506 | a structure with a known alignment of just a halfword | |
507 | and a field split across two aligned halfwords within the structure. | |
508 | Or likewise a structure with a known alignment of just a byte | |
509 | and a field split across two bytes. | |
510 | Such cases are not supposed to be able to occur. */ | |
511 | ||
512 | if (GET_CODE (op0) == REG || GET_CODE (op0) == SUBREG) | |
513 | { | |
514 | if (offset != 0) | |
515 | abort (); | |
516 | /* Special treatment for a bit field split across two registers. */ | |
517 | if (bitsize + bitpos > BITS_PER_WORD) | |
518 | { | |
06c94bce RS |
519 | store_split_bit_field (op0, bitsize, bitpos, |
520 | value, BITS_PER_WORD); | |
44037a66 TG |
521 | return; |
522 | } | |
523 | } | |
524 | else | |
525 | { | |
526 | /* Get the proper mode to use for this field. We want a mode that | |
527 | includes the entire field. If such a mode would be larger than | |
528 | a word, we won't be doing the extraction the normal way. */ | |
529 | ||
530 | mode = get_best_mode (bitsize, bitpos + offset * BITS_PER_UNIT, | |
531 | struct_align * BITS_PER_UNIT, word_mode, | |
532 | GET_CODE (op0) == MEM && MEM_VOLATILE_P (op0)); | |
533 | ||
534 | if (mode == VOIDmode) | |
535 | { | |
536 | /* The only way this should occur is if the field spans word | |
537 | boundaries. */ | |
06c94bce RS |
538 | store_split_bit_field (op0, |
539 | bitsize, bitpos + offset * BITS_PER_UNIT, | |
44037a66 TG |
540 | value, struct_align); |
541 | return; | |
542 | } | |
543 | ||
544 | total_bits = GET_MODE_BITSIZE (mode); | |
545 | ||
546 | /* Get ref to an aligned byte, halfword, or word containing the field. | |
547 | Adjust BITPOS to be position within a word, | |
548 | and OFFSET to be the offset of that word. | |
549 | Then alter OP0 to refer to that word. */ | |
550 | bitpos += (offset % (total_bits / BITS_PER_UNIT)) * BITS_PER_UNIT; | |
551 | offset -= (offset % (total_bits / BITS_PER_UNIT)); | |
552 | op0 = change_address (op0, mode, | |
553 | plus_constant (XEXP (op0, 0), offset)); | |
554 | } | |
555 | ||
556 | mode = GET_MODE (op0); | |
557 | ||
558 | /* Now MODE is either some integral mode for a MEM as OP0, | |
559 | or is a full-word for a REG as OP0. TOTAL_BITS corresponds. | |
560 | The bit field is contained entirely within OP0. | |
561 | BITPOS is the starting bit number within OP0. | |
562 | (OP0's mode may actually be narrower than MODE.) */ | |
563 | ||
564 | #if BYTES_BIG_ENDIAN | |
565 | /* BITPOS is the distance between our msb | |
566 | and that of the containing datum. | |
567 | Convert it to the distance from the lsb. */ | |
568 | ||
569 | bitpos = total_bits - bitsize - bitpos; | |
570 | #endif | |
571 | /* Now BITPOS is always the distance between our lsb | |
572 | and that of OP0. */ | |
573 | ||
574 | /* Shift VALUE left by BITPOS bits. If VALUE is not constant, | |
575 | we must first convert its mode to MODE. */ | |
576 | ||
577 | if (GET_CODE (value) == CONST_INT) | |
578 | { | |
b1ec3c92 | 579 | register HOST_WIDE_INT v = INTVAL (value); |
44037a66 | 580 | |
b1ec3c92 CH |
581 | if (bitsize < HOST_BITS_PER_WIDE_INT) |
582 | v &= ((HOST_WIDE_INT) 1 << bitsize) - 1; | |
44037a66 TG |
583 | |
584 | if (v == 0) | |
585 | all_zero = 1; | |
b1ec3c92 CH |
586 | else if ((bitsize < HOST_BITS_PER_WIDE_INT |
587 | && v == ((HOST_WIDE_INT) 1 << bitsize) - 1) | |
588 | || (bitsize == HOST_BITS_PER_WIDE_INT && v == -1)) | |
44037a66 TG |
589 | all_one = 1; |
590 | ||
591 | value = lshift_value (mode, value, bitpos, bitsize); | |
592 | } | |
593 | else | |
594 | { | |
595 | int must_and = (GET_MODE_BITSIZE (GET_MODE (value)) != bitsize | |
596 | && bitpos + bitsize != GET_MODE_BITSIZE (mode)); | |
597 | ||
598 | if (GET_MODE (value) != mode) | |
599 | { | |
600 | /* If VALUE is a floating-point mode, access it as an integer | |
601 | of the corresponding size, then convert it. This can occur on | |
602 | a machine with 64 bit registers that uses SFmode for float. */ | |
603 | if (GET_MODE_CLASS (GET_MODE (value)) == MODE_FLOAT) | |
604 | { | |
605 | if (GET_CODE (value) != REG) | |
606 | value = copy_to_reg (value); | |
607 | value | |
608 | = gen_rtx (SUBREG, word_mode, value, 0); | |
609 | } | |
610 | ||
611 | if ((GET_CODE (value) == REG || GET_CODE (value) == SUBREG) | |
612 | && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (value))) | |
613 | value = gen_lowpart (mode, value); | |
614 | else | |
615 | value = convert_to_mode (mode, value, 1); | |
616 | } | |
617 | ||
618 | if (must_and) | |
619 | value = expand_binop (mode, and_optab, value, | |
620 | mask_rtx (mode, 0, bitsize, 0), | |
b1ec3c92 | 621 | NULL_RTX, 1, OPTAB_LIB_WIDEN); |
44037a66 TG |
622 | if (bitpos > 0) |
623 | value = expand_shift (LSHIFT_EXPR, mode, value, | |
b1ec3c92 | 624 | build_int_2 (bitpos, 0), NULL_RTX, 1); |
44037a66 TG |
625 | } |
626 | ||
627 | /* Now clear the chosen bits in OP0, | |
628 | except that if VALUE is -1 we need not bother. */ | |
629 | ||
630 | subtarget = (GET_CODE (op0) == REG || ! flag_force_mem) ? op0 : 0; | |
631 | ||
632 | if (! all_one) | |
633 | { | |
634 | temp = expand_binop (mode, and_optab, op0, | |
635 | mask_rtx (mode, bitpos, bitsize, 1), | |
636 | subtarget, 1, OPTAB_LIB_WIDEN); | |
637 | subtarget = temp; | |
638 | } | |
639 | else | |
640 | temp = op0; | |
641 | ||
642 | /* Now logical-or VALUE into OP0, unless it is zero. */ | |
643 | ||
644 | if (! all_zero) | |
645 | temp = expand_binop (mode, ior_optab, temp, value, | |
646 | subtarget, 1, OPTAB_LIB_WIDEN); | |
647 | if (op0 != temp) | |
648 | emit_move_insn (op0, temp); | |
649 | } | |
650 | \f | |
06c94bce | 651 | /* Store a bit field that is split across multiple accessible memory objects. |
44037a66 | 652 | |
06c94bce | 653 | OP0 is the REG, SUBREG or MEM rtx for the first of the objects. |
44037a66 TG |
654 | BITSIZE is the field width; BITPOS the position of its first bit |
655 | (within the word). | |
06c94bce RS |
656 | VALUE is the value to store. |
657 | ALIGN is the known alignment of OP0, measured in bytes. | |
658 | This is also the size of the memory objects to be used. | |
659 | ||
660 | This does not yet handle fields wider than BITS_PER_WORD. */ | |
44037a66 TG |
661 | |
662 | static void | |
663 | store_split_bit_field (op0, bitsize, bitpos, value, align) | |
664 | rtx op0; | |
665 | int bitsize, bitpos; | |
666 | rtx value; | |
667 | int align; | |
668 | { | |
0eb61c19 DE |
669 | /* Make sure UNIT isn't larger than BITS_PER_WORD, we can only handle that |
670 | much at a time. */ | |
671 | int unit = MIN (align * BITS_PER_UNIT, BITS_PER_WORD); | |
44037a66 | 672 | rtx word; |
06c94bce | 673 | int bitsdone = 0; |
e54d80d0 RK |
674 | |
675 | if (GET_CODE (value) == CONST_DOUBLE | |
06c94bce RS |
676 | && (word = gen_lowpart_common (word_mode, value)) != 0) |
677 | value = word; | |
e54d80d0 | 678 | |
44037a66 | 679 | if (CONSTANT_P (value) && GET_CODE (value) != CONST_INT) |
e54d80d0 | 680 | value = copy_to_mode_reg (word_mode, value); |
44037a66 | 681 | |
06c94bce | 682 | while (bitsdone < bitsize) |
44037a66 | 683 | { |
06c94bce RS |
684 | int thissize; |
685 | rtx part, word; | |
686 | int thispos; | |
687 | int offset; | |
44037a66 | 688 | |
06c94bce RS |
689 | offset = (bitpos + bitsdone) / unit; |
690 | thispos = (bitpos + bitsdone) % unit; | |
44037a66 | 691 | |
0eb61c19 DE |
692 | /* THISSIZE must not overrun a word boundary. Otherwise, |
693 | store_fixed_bit_field will call us again, and we will mutually | |
694 | recurse forever. */ | |
695 | thissize = MIN (bitsize - bitsdone, BITS_PER_WORD); | |
696 | thissize = MIN (thissize, unit - thispos); | |
44037a66 | 697 | |
06c94bce RS |
698 | #if BYTES_BIG_ENDIAN |
699 | /* Fetch successively less significant portions. */ | |
700 | if (GET_CODE (value) == CONST_INT) | |
701 | part = GEN_INT (((unsigned HOST_WIDE_INT) (INTVAL (value)) | |
702 | >> (bitsize - bitsdone - thissize)) | |
703 | & (((HOST_WIDE_INT) 1 << thissize) - 1)); | |
704 | else | |
705 | /* The args are chosen so that the last part | |
706 | includes the lsb. */ | |
707 | part = extract_fixed_bit_field (word_mode, value, 0, thissize, | |
708 | BITS_PER_WORD - bitsize + bitsdone, | |
709 | NULL_RTX, 1, align); | |
710 | #else | |
711 | /* Fetch successively more significant portions. */ | |
712 | if (GET_CODE (value) == CONST_INT) | |
713 | part = GEN_INT (((unsigned HOST_WIDE_INT) (INTVAL (value)) >> bitsdone) | |
714 | & (((HOST_WIDE_INT) 1 << thissize) - 1)); | |
715 | else | |
716 | part = extract_fixed_bit_field (word_mode, value, 0, thissize, | |
717 | bitsdone, NULL_RTX, 1, align); | |
718 | #endif | |
44037a66 | 719 | |
06c94bce RS |
720 | /* If OP0 is a register, then handle OFFSET here. |
721 | In the register case, UNIT must be a whole word. */ | |
722 | if (GET_CODE (op0) == SUBREG || GET_CODE (op0) == REG) | |
723 | { | |
724 | word = operand_subword (op0, offset, 1, GET_MODE (op0)); | |
725 | offset = 0; | |
726 | } | |
727 | else | |
728 | word = op0; | |
44037a66 | 729 | |
06c94bce RS |
730 | if (word == 0) |
731 | abort (); | |
732 | ||
0eb61c19 DE |
733 | /* OFFSET is in UNITs, and UNIT is in bits. |
734 | store_fixed_bit_field wants offset in bytes. */ | |
735 | store_fixed_bit_field (word, offset * unit / BITS_PER_UNIT, | |
736 | thissize, thispos, part, align); | |
06c94bce RS |
737 | bitsdone += thissize; |
738 | } | |
44037a66 TG |
739 | } |
740 | \f | |
741 | /* Generate code to extract a byte-field from STR_RTX | |
742 | containing BITSIZE bits, starting at BITNUM, | |
743 | and put it in TARGET if possible (if TARGET is nonzero). | |
744 | Regardless of TARGET, we return the rtx for where the value is placed. | |
745 | It may be a QUEUED. | |
746 | ||
747 | STR_RTX is the structure containing the byte (a REG or MEM). | |
748 | UNSIGNEDP is nonzero if this is an unsigned bit field. | |
749 | MODE is the natural mode of the field value once extracted. | |
750 | TMODE is the mode the caller would like the value to have; | |
751 | but the value may be returned with type MODE instead. | |
752 | ||
753 | ALIGN is the alignment that STR_RTX is known to have, measured in bytes. | |
754 | TOTAL_SIZE is the size in bytes of the containing structure, | |
755 | or -1 if varying. | |
756 | ||
757 | If a TARGET is specified and we can store in it at no extra cost, | |
758 | we do so, and return TARGET. | |
759 | Otherwise, we return a REG of mode TMODE or MODE, with TMODE preferred | |
760 | if they are equally easy. */ | |
761 | ||
762 | rtx | |
763 | extract_bit_field (str_rtx, bitsize, bitnum, unsignedp, | |
764 | target, mode, tmode, align, total_size) | |
765 | rtx str_rtx; | |
766 | register int bitsize; | |
767 | int bitnum; | |
768 | int unsignedp; | |
769 | rtx target; | |
770 | enum machine_mode mode, tmode; | |
771 | int align; | |
772 | int total_size; | |
773 | { | |
774 | int unit = (GET_CODE (str_rtx) == MEM) ? BITS_PER_UNIT : BITS_PER_WORD; | |
775 | register int offset = bitnum / unit; | |
776 | register int bitpos = bitnum % unit; | |
777 | register rtx op0 = str_rtx; | |
778 | rtx spec_target = target; | |
779 | rtx spec_target_subreg = 0; | |
780 | ||
781 | if (GET_CODE (str_rtx) == MEM && ! MEM_IN_STRUCT_P (str_rtx)) | |
782 | abort (); | |
783 | ||
784 | /* Discount the part of the structure before the desired byte. | |
785 | We need to know how many bytes are safe to reference after it. */ | |
786 | if (total_size >= 0) | |
787 | total_size -= (bitpos / BIGGEST_ALIGNMENT | |
788 | * (BIGGEST_ALIGNMENT / BITS_PER_UNIT)); | |
789 | ||
790 | if (tmode == VOIDmode) | |
791 | tmode = mode; | |
44037a66 TG |
792 | while (GET_CODE (op0) == SUBREG) |
793 | { | |
794 | offset += SUBREG_WORD (op0); | |
795 | op0 = SUBREG_REG (op0); | |
796 | } | |
797 | ||
798 | #if BYTES_BIG_ENDIAN | |
799 | /* If OP0 is a register, BITPOS must count within a word. | |
800 | But as we have it, it counts within whatever size OP0 now has. | |
801 | On a bigendian machine, these are not the same, so convert. */ | |
802 | if (GET_CODE (op0) != MEM && unit > GET_MODE_BITSIZE (GET_MODE (op0))) | |
803 | bitpos += unit - GET_MODE_BITSIZE (GET_MODE (op0)); | |
804 | #endif | |
805 | ||
806 | /* Extracting a full-word or multi-word value | |
807 | from a structure in a register. | |
808 | This can be done with just SUBREG. | |
809 | So too extracting a subword value in | |
810 | the least significant part of the register. */ | |
811 | ||
812 | if (GET_CODE (op0) == REG | |
813 | && ((bitsize >= BITS_PER_WORD && bitsize == GET_MODE_BITSIZE (mode) | |
814 | && bitpos % BITS_PER_WORD == 0) | |
815 | || (mode_for_size (bitsize, GET_MODE_CLASS (tmode), 0) != BLKmode | |
816 | #if BYTES_BIG_ENDIAN | |
817 | && bitpos + bitsize == BITS_PER_WORD | |
818 | #else | |
819 | && bitpos == 0 | |
820 | #endif | |
821 | ))) | |
822 | { | |
823 | enum machine_mode mode1 | |
824 | = mode_for_size (bitsize, GET_MODE_CLASS (tmode), 0); | |
825 | ||
826 | if (mode1 != GET_MODE (op0)) | |
827 | op0 = gen_rtx (SUBREG, mode1, op0, offset); | |
828 | ||
829 | if (mode1 != mode) | |
830 | return convert_to_mode (tmode, op0, unsignedp); | |
831 | return op0; | |
832 | } | |
833 | ||
834 | /* Handle fields bigger than a word. */ | |
835 | ||
836 | if (bitsize > BITS_PER_WORD) | |
837 | { | |
838 | /* Here we transfer the words of the field | |
839 | in the order least significant first. | |
840 | This is because the most significant word is the one which may | |
841 | be less than full. */ | |
842 | ||
843 | int nwords = (bitsize + (BITS_PER_WORD - 1)) / BITS_PER_WORD; | |
844 | int i; | |
845 | ||
846 | if (target == 0 || GET_CODE (target) != REG) | |
847 | target = gen_reg_rtx (mode); | |
848 | ||
849 | for (i = 0; i < nwords; i++) | |
850 | { | |
851 | /* If I is 0, use the low-order word in both field and target; | |
852 | if I is 1, use the next to lowest word; and so on. */ | |
853 | int wordnum = (WORDS_BIG_ENDIAN ? nwords - i - 1 : i); | |
854 | int bit_offset = (WORDS_BIG_ENDIAN | |
855 | ? MAX (0, bitsize - (i + 1) * BITS_PER_WORD) | |
856 | : i * BITS_PER_WORD); | |
857 | rtx target_part = operand_subword (target, wordnum, 1, VOIDmode); | |
858 | rtx result_part | |
859 | = extract_bit_field (op0, MIN (BITS_PER_WORD, | |
860 | bitsize - i * BITS_PER_WORD), | |
861 | bitnum + bit_offset, | |
862 | 1, target_part, mode, word_mode, | |
863 | align, total_size); | |
864 | ||
865 | if (target_part == 0) | |
866 | abort (); | |
867 | ||
868 | if (result_part != target_part) | |
869 | emit_move_insn (target_part, result_part); | |
870 | } | |
871 | ||
872 | return target; | |
873 | } | |
874 | ||
875 | /* From here on we know the desired field is smaller than a word | |
876 | so we can assume it is an integer. So we can safely extract it as one | |
877 | size of integer, if necessary, and then truncate or extend | |
878 | to the size that is wanted. */ | |
879 | ||
880 | /* OFFSET is the number of words or bytes (UNIT says which) | |
881 | from STR_RTX to the first word or byte containing part of the field. */ | |
882 | ||
883 | if (GET_CODE (op0) == REG) | |
884 | { | |
885 | if (offset != 0 | |
886 | || GET_MODE_SIZE (GET_MODE (op0)) > UNITS_PER_WORD) | |
887 | op0 = gen_rtx (SUBREG, TYPE_MODE (type_for_size (BITS_PER_WORD, 0)), | |
888 | op0, offset); | |
889 | offset = 0; | |
890 | } | |
891 | else | |
892 | { | |
893 | op0 = protect_from_queue (str_rtx, 1); | |
894 | } | |
895 | ||
896 | /* Now OFFSET is nonzero only for memory operands. */ | |
897 | ||
898 | if (unsignedp) | |
899 | { | |
900 | #ifdef HAVE_extzv | |
901 | if (HAVE_extzv | |
902 | && (GET_MODE_BITSIZE (insn_operand_mode[(int) CODE_FOR_extzv][0]) | |
903 | >= bitsize)) | |
904 | { | |
905 | int xbitpos = bitpos, xoffset = offset; | |
906 | rtx bitsize_rtx, bitpos_rtx; | |
907 | rtx last = get_last_insn(); | |
908 | rtx xop0 = op0; | |
909 | rtx xtarget = target; | |
910 | rtx xspec_target = spec_target; | |
911 | rtx xspec_target_subreg = spec_target_subreg; | |
912 | rtx pat; | |
913 | enum machine_mode maxmode | |
914 | = insn_operand_mode[(int) CODE_FOR_extzv][0]; | |
915 | ||
916 | if (GET_CODE (xop0) == MEM) | |
917 | { | |
918 | int save_volatile_ok = volatile_ok; | |
919 | volatile_ok = 1; | |
920 | ||
921 | /* Is the memory operand acceptable? */ | |
922 | if (flag_force_mem | |
923 | || ! ((*insn_operand_predicate[(int) CODE_FOR_extzv][1]) | |
924 | (xop0, GET_MODE (xop0)))) | |
925 | { | |
926 | /* No, load into a reg and extract from there. */ | |
927 | enum machine_mode bestmode; | |
928 | ||
929 | /* Get the mode to use for inserting into this field. If | |
930 | OP0 is BLKmode, get the smallest mode consistent with the | |
931 | alignment. If OP0 is a non-BLKmode object that is no | |
932 | wider than MAXMODE, use its mode. Otherwise, use the | |
933 | smallest mode containing the field. */ | |
934 | ||
935 | if (GET_MODE (xop0) == BLKmode | |
936 | || (GET_MODE_SIZE (GET_MODE (op0)) | |
937 | > GET_MODE_SIZE (maxmode))) | |
938 | bestmode = get_best_mode (bitsize, bitnum, | |
939 | align * BITS_PER_UNIT, maxmode, | |
717702e6 | 940 | MEM_VOLATILE_P (xop0)); |
44037a66 TG |
941 | else |
942 | bestmode = GET_MODE (xop0); | |
943 | ||
944 | if (bestmode == VOIDmode) | |
945 | goto extzv_loses; | |
946 | ||
947 | /* Compute offset as multiple of this unit, | |
948 | counting in bytes. */ | |
949 | unit = GET_MODE_BITSIZE (bestmode); | |
950 | xoffset = (bitnum / unit) * GET_MODE_SIZE (bestmode); | |
951 | xbitpos = bitnum % unit; | |
952 | xop0 = change_address (xop0, bestmode, | |
953 | plus_constant (XEXP (xop0, 0), | |
954 | xoffset)); | |
955 | /* Fetch it to a register in that size. */ | |
956 | xop0 = force_reg (bestmode, xop0); | |
957 | ||
958 | /* XBITPOS counts within UNIT, which is what is expected. */ | |
959 | } | |
960 | else | |
961 | /* Get ref to first byte containing part of the field. */ | |
962 | xop0 = change_address (xop0, byte_mode, | |
963 | plus_constant (XEXP (xop0, 0), xoffset)); | |
964 | ||
965 | volatile_ok = save_volatile_ok; | |
966 | } | |
967 | ||
968 | /* If op0 is a register, we need it in MAXMODE (which is usually | |
969 | SImode). to make it acceptable to the format of extzv. */ | |
970 | if (GET_CODE (xop0) == SUBREG && GET_MODE (xop0) != maxmode) | |
971 | abort (); | |
972 | if (GET_CODE (xop0) == REG && GET_MODE (xop0) != maxmode) | |
973 | xop0 = gen_rtx (SUBREG, maxmode, xop0, 0); | |
974 | ||
975 | /* On big-endian machines, we count bits from the most significant. | |
976 | If the bit field insn does not, we must invert. */ | |
977 | #if BITS_BIG_ENDIAN != BYTES_BIG_ENDIAN | |
978 | xbitpos = unit - bitsize - xbitpos; | |
979 | #endif | |
980 | /* Now convert from counting within UNIT to counting in MAXMODE. */ | |
981 | #if BITS_BIG_ENDIAN | |
982 | if (GET_CODE (xop0) != MEM) | |
983 | xbitpos += GET_MODE_BITSIZE (maxmode) - unit; | |
984 | #endif | |
985 | unit = GET_MODE_BITSIZE (maxmode); | |
986 | ||
987 | if (xtarget == 0 | |
988 | || (flag_force_mem && GET_CODE (xtarget) == MEM)) | |
989 | xtarget = xspec_target = gen_reg_rtx (tmode); | |
990 | ||
991 | if (GET_MODE (xtarget) != maxmode) | |
992 | { | |
993 | if (GET_CODE (xtarget) == REG) | |
b7a09135 RS |
994 | { |
995 | int wider = (GET_MODE_SIZE (maxmode) | |
996 | > GET_MODE_SIZE (GET_MODE (xtarget))); | |
997 | xtarget = gen_lowpart (maxmode, xtarget); | |
998 | if (wider) | |
999 | xspec_target_subreg = xtarget; | |
1000 | } | |
44037a66 TG |
1001 | else |
1002 | xtarget = gen_reg_rtx (maxmode); | |
1003 | } | |
1004 | ||
1005 | /* If this machine's extzv insists on a register target, | |
1006 | make sure we have one. */ | |
1007 | if (! ((*insn_operand_predicate[(int) CODE_FOR_extzv][0]) | |
1008 | (xtarget, maxmode))) | |
1009 | xtarget = gen_reg_rtx (maxmode); | |
1010 | ||
b1ec3c92 CH |
1011 | bitsize_rtx = GEN_INT (bitsize); |
1012 | bitpos_rtx = GEN_INT (xbitpos); | |
44037a66 TG |
1013 | |
1014 | pat = gen_extzv (protect_from_queue (xtarget, 1), | |
1015 | xop0, bitsize_rtx, bitpos_rtx); | |
1016 | if (pat) | |
1017 | { | |
1018 | emit_insn (pat); | |
1019 | target = xtarget; | |
1020 | spec_target = xspec_target; | |
1021 | spec_target_subreg = xspec_target_subreg; | |
1022 | } | |
1023 | else | |
1024 | { | |
1025 | delete_insns_since (last); | |
1026 | target = extract_fixed_bit_field (tmode, op0, offset, bitsize, | |
1027 | bitpos, target, 1, align); | |
1028 | } | |
1029 | } | |
1030 | else | |
1031 | extzv_loses: | |
1032 | #endif | |
1033 | target = extract_fixed_bit_field (tmode, op0, offset, bitsize, bitpos, | |
1034 | target, 1, align); | |
1035 | } | |
1036 | else | |
1037 | { | |
1038 | #ifdef HAVE_extv | |
1039 | if (HAVE_extv | |
1040 | && (GET_MODE_BITSIZE (insn_operand_mode[(int) CODE_FOR_extv][0]) | |
1041 | >= bitsize)) | |
1042 | { | |
1043 | int xbitpos = bitpos, xoffset = offset; | |
1044 | rtx bitsize_rtx, bitpos_rtx; | |
1045 | rtx last = get_last_insn(); | |
1046 | rtx xop0 = op0, xtarget = target; | |
1047 | rtx xspec_target = spec_target; | |
1048 | rtx xspec_target_subreg = spec_target_subreg; | |
1049 | rtx pat; | |
1050 | enum machine_mode maxmode | |
1051 | = insn_operand_mode[(int) CODE_FOR_extv][0]; | |
1052 | ||
1053 | if (GET_CODE (xop0) == MEM) | |
1054 | { | |
1055 | /* Is the memory operand acceptable? */ | |
1056 | if (! ((*insn_operand_predicate[(int) CODE_FOR_extv][1]) | |
1057 | (xop0, GET_MODE (xop0)))) | |
1058 | { | |
1059 | /* No, load into a reg and extract from there. */ | |
1060 | enum machine_mode bestmode; | |
1061 | ||
1062 | /* Get the mode to use for inserting into this field. If | |
1063 | OP0 is BLKmode, get the smallest mode consistent with the | |
1064 | alignment. If OP0 is a non-BLKmode object that is no | |
1065 | wider than MAXMODE, use its mode. Otherwise, use the | |
1066 | smallest mode containing the field. */ | |
1067 | ||
1068 | if (GET_MODE (xop0) == BLKmode | |
1069 | || (GET_MODE_SIZE (GET_MODE (op0)) | |
1070 | > GET_MODE_SIZE (maxmode))) | |
1071 | bestmode = get_best_mode (bitsize, bitnum, | |
1072 | align * BITS_PER_UNIT, maxmode, | |
717702e6 | 1073 | MEM_VOLATILE_P (xop0)); |
44037a66 TG |
1074 | else |
1075 | bestmode = GET_MODE (xop0); | |
1076 | ||
1077 | if (bestmode == VOIDmode) | |
1078 | goto extv_loses; | |
1079 | ||
1080 | /* Compute offset as multiple of this unit, | |
1081 | counting in bytes. */ | |
1082 | unit = GET_MODE_BITSIZE (bestmode); | |
1083 | xoffset = (bitnum / unit) * GET_MODE_SIZE (bestmode); | |
1084 | xbitpos = bitnum % unit; | |
1085 | xop0 = change_address (xop0, bestmode, | |
1086 | plus_constant (XEXP (xop0, 0), | |
1087 | xoffset)); | |
1088 | /* Fetch it to a register in that size. */ | |
1089 | xop0 = force_reg (bestmode, xop0); | |
1090 | ||
1091 | /* XBITPOS counts within UNIT, which is what is expected. */ | |
1092 | } | |
1093 | else | |
1094 | /* Get ref to first byte containing part of the field. */ | |
1095 | xop0 = change_address (xop0, byte_mode, | |
1096 | plus_constant (XEXP (xop0, 0), xoffset)); | |
1097 | } | |
1098 | ||
1099 | /* If op0 is a register, we need it in MAXMODE (which is usually | |
1100 | SImode) to make it acceptable to the format of extv. */ | |
1101 | if (GET_CODE (xop0) == SUBREG && GET_MODE (xop0) != maxmode) | |
1102 | abort (); | |
1103 | if (GET_CODE (xop0) == REG && GET_MODE (xop0) != maxmode) | |
1104 | xop0 = gen_rtx (SUBREG, maxmode, xop0, 0); | |
1105 | ||
1106 | /* On big-endian machines, we count bits from the most significant. | |
1107 | If the bit field insn does not, we must invert. */ | |
1108 | #if BITS_BIG_ENDIAN != BYTES_BIG_ENDIAN | |
1109 | xbitpos = unit - bitsize - xbitpos; | |
1110 | #endif | |
1111 | /* XBITPOS counts within a size of UNIT. | |
1112 | Adjust to count within a size of MAXMODE. */ | |
1113 | #if BITS_BIG_ENDIAN | |
1114 | if (GET_CODE (xop0) != MEM) | |
1115 | xbitpos += (GET_MODE_BITSIZE (maxmode) - unit); | |
1116 | #endif | |
1117 | unit = GET_MODE_BITSIZE (maxmode); | |
1118 | ||
1119 | if (xtarget == 0 | |
1120 | || (flag_force_mem && GET_CODE (xtarget) == MEM)) | |
1121 | xtarget = xspec_target = gen_reg_rtx (tmode); | |
1122 | ||
1123 | if (GET_MODE (xtarget) != maxmode) | |
1124 | { | |
1125 | if (GET_CODE (xtarget) == REG) | |
b7a09135 RS |
1126 | { |
1127 | int wider = (GET_MODE_SIZE (maxmode) | |
1128 | > GET_MODE_SIZE (GET_MODE (xtarget))); | |
1129 | xtarget = gen_lowpart (maxmode, xtarget); | |
1130 | if (wider) | |
1131 | xspec_target_subreg = xtarget; | |
1132 | } | |
44037a66 TG |
1133 | else |
1134 | xtarget = gen_reg_rtx (maxmode); | |
1135 | } | |
1136 | ||
1137 | /* If this machine's extv insists on a register target, | |
1138 | make sure we have one. */ | |
1139 | if (! ((*insn_operand_predicate[(int) CODE_FOR_extv][0]) | |
1140 | (xtarget, maxmode))) | |
1141 | xtarget = gen_reg_rtx (maxmode); | |
1142 | ||
b1ec3c92 CH |
1143 | bitsize_rtx = GEN_INT (bitsize); |
1144 | bitpos_rtx = GEN_INT (xbitpos); | |
44037a66 TG |
1145 | |
1146 | pat = gen_extv (protect_from_queue (xtarget, 1), | |
1147 | xop0, bitsize_rtx, bitpos_rtx); | |
1148 | if (pat) | |
1149 | { | |
1150 | emit_insn (pat); | |
1151 | target = xtarget; | |
1152 | spec_target = xspec_target; | |
1153 | spec_target_subreg = xspec_target_subreg; | |
1154 | } | |
1155 | else | |
1156 | { | |
1157 | delete_insns_since (last); | |
1158 | target = extract_fixed_bit_field (tmode, op0, offset, bitsize, | |
1159 | bitpos, target, 0, align); | |
1160 | } | |
1161 | } | |
1162 | else | |
1163 | extv_loses: | |
1164 | #endif | |
1165 | target = extract_fixed_bit_field (tmode, op0, offset, bitsize, bitpos, | |
1166 | target, 0, align); | |
1167 | } | |
1168 | if (target == spec_target) | |
1169 | return target; | |
1170 | if (target == spec_target_subreg) | |
1171 | return spec_target; | |
1172 | if (GET_MODE (target) != tmode && GET_MODE (target) != mode) | |
1173 | { | |
1174 | /* If the target mode is floating-point, first convert to the | |
1175 | integer mode of that size and then access it as a floating-point | |
1176 | value via a SUBREG. */ | |
1177 | if (GET_MODE_CLASS (tmode) == MODE_FLOAT) | |
1178 | { | |
1179 | target = convert_to_mode (mode_for_size (GET_MODE_BITSIZE (tmode), | |
1180 | MODE_INT, 0), | |
1181 | target, unsignedp); | |
1182 | if (GET_CODE (target) != REG) | |
1183 | target = copy_to_reg (target); | |
1184 | return gen_rtx (SUBREG, tmode, target, 0); | |
1185 | } | |
1186 | else | |
1187 | return convert_to_mode (tmode, target, unsignedp); | |
1188 | } | |
1189 | return target; | |
1190 | } | |
1191 | \f | |
1192 | /* Extract a bit field using shifts and boolean operations | |
1193 | Returns an rtx to represent the value. | |
1194 | OP0 addresses a register (word) or memory (byte). | |
1195 | BITPOS says which bit within the word or byte the bit field starts in. | |
1196 | OFFSET says how many bytes farther the bit field starts; | |
1197 | it is 0 if OP0 is a register. | |
1198 | BITSIZE says how many bits long the bit field is. | |
1199 | (If OP0 is a register, it may be narrower than a full word, | |
1200 | but BITPOS still counts within a full word, | |
1201 | which is significant on bigendian machines.) | |
1202 | ||
1203 | UNSIGNEDP is nonzero for an unsigned bit field (don't sign-extend value). | |
1204 | If TARGET is nonzero, attempts to store the value there | |
1205 | and return TARGET, but this is not guaranteed. | |
1206 | If TARGET is not used, create a pseudo-reg of mode TMODE for the value. | |
1207 | ||
1208 | ALIGN is the alignment that STR_RTX is known to have, measured in bytes. */ | |
1209 | ||
1210 | static rtx | |
1211 | extract_fixed_bit_field (tmode, op0, offset, bitsize, bitpos, | |
1212 | target, unsignedp, align) | |
1213 | enum machine_mode tmode; | |
1214 | register rtx op0, target; | |
1215 | register int offset, bitsize, bitpos; | |
1216 | int unsignedp; | |
1217 | int align; | |
1218 | { | |
1219 | int total_bits = BITS_PER_WORD; | |
1220 | enum machine_mode mode; | |
1221 | ||
1222 | if (GET_CODE (op0) == SUBREG || GET_CODE (op0) == REG) | |
1223 | { | |
1224 | /* Special treatment for a bit field split across two registers. */ | |
1225 | if (bitsize + bitpos > BITS_PER_WORD) | |
1226 | return extract_split_bit_field (op0, bitsize, bitpos, | |
1227 | unsignedp, align); | |
1228 | } | |
1229 | else | |
1230 | { | |
1231 | /* Get the proper mode to use for this field. We want a mode that | |
1232 | includes the entire field. If such a mode would be larger than | |
1233 | a word, we won't be doing the extraction the normal way. */ | |
1234 | ||
1235 | mode = get_best_mode (bitsize, bitpos + offset * BITS_PER_UNIT, | |
1236 | align * BITS_PER_UNIT, word_mode, | |
1237 | GET_CODE (op0) == MEM && MEM_VOLATILE_P (op0)); | |
1238 | ||
1239 | if (mode == VOIDmode) | |
1240 | /* The only way this should occur is if the field spans word | |
1241 | boundaries. */ | |
1242 | return extract_split_bit_field (op0, bitsize, | |
1243 | bitpos + offset * BITS_PER_UNIT, | |
1244 | unsignedp, align); | |
1245 | ||
1246 | total_bits = GET_MODE_BITSIZE (mode); | |
1247 | ||
401db791 JW |
1248 | /* Make sure bitpos is valid for the chosen mode. Adjust BITPOS to |
1249 | be be in the range 0 to total_bits-1, and put any excess bytes in | |
1250 | OFFSET. */ | |
1251 | if (bitpos >= total_bits) | |
1252 | { | |
1253 | offset += (bitpos / total_bits) * (total_bits / BITS_PER_UNIT); | |
1254 | bitpos -= ((bitpos / total_bits) * (total_bits / BITS_PER_UNIT) | |
1255 | * BITS_PER_UNIT); | |
1256 | } | |
1257 | ||
44037a66 TG |
1258 | /* Get ref to an aligned byte, halfword, or word containing the field. |
1259 | Adjust BITPOS to be position within a word, | |
1260 | and OFFSET to be the offset of that word. | |
1261 | Then alter OP0 to refer to that word. */ | |
1262 | bitpos += (offset % (total_bits / BITS_PER_UNIT)) * BITS_PER_UNIT; | |
1263 | offset -= (offset % (total_bits / BITS_PER_UNIT)); | |
1264 | op0 = change_address (op0, mode, | |
1265 | plus_constant (XEXP (op0, 0), offset)); | |
1266 | } | |
1267 | ||
1268 | mode = GET_MODE (op0); | |
1269 | ||
1270 | #if BYTES_BIG_ENDIAN | |
1271 | /* BITPOS is the distance between our msb and that of OP0. | |
1272 | Convert it to the distance from the lsb. */ | |
1273 | ||
1274 | bitpos = total_bits - bitsize - bitpos; | |
1275 | #endif | |
1276 | /* Now BITPOS is always the distance between the field's lsb and that of OP0. | |
1277 | We have reduced the big-endian case to the little-endian case. */ | |
1278 | ||
1279 | if (unsignedp) | |
1280 | { | |
1281 | if (bitpos) | |
1282 | { | |
1283 | /* If the field does not already start at the lsb, | |
1284 | shift it so it does. */ | |
1285 | tree amount = build_int_2 (bitpos, 0); | |
1286 | /* Maybe propagate the target for the shift. */ | |
1287 | /* But not if we will return it--could confuse integrate.c. */ | |
1288 | rtx subtarget = (target != 0 && GET_CODE (target) == REG | |
1289 | && !REG_FUNCTION_VALUE_P (target) | |
1290 | ? target : 0); | |
1291 | if (tmode != mode) subtarget = 0; | |
1292 | op0 = expand_shift (RSHIFT_EXPR, mode, op0, amount, subtarget, 1); | |
1293 | } | |
1294 | /* Convert the value to the desired mode. */ | |
1295 | if (mode != tmode) | |
1296 | op0 = convert_to_mode (tmode, op0, 1); | |
1297 | ||
1298 | /* Unless the msb of the field used to be the msb when we shifted, | |
1299 | mask out the upper bits. */ | |
1300 | ||
1301 | if (GET_MODE_BITSIZE (mode) != bitpos + bitsize | |
1302 | #if 0 | |
1303 | #ifdef SLOW_ZERO_EXTEND | |
1304 | /* Always generate an `and' if | |
1305 | we just zero-extended op0 and SLOW_ZERO_EXTEND, since it | |
1306 | will combine fruitfully with the zero-extend. */ | |
1307 | || tmode != mode | |
1308 | #endif | |
1309 | #endif | |
1310 | ) | |
1311 | return expand_binop (GET_MODE (op0), and_optab, op0, | |
1312 | mask_rtx (GET_MODE (op0), 0, bitsize, 0), | |
1313 | target, 1, OPTAB_LIB_WIDEN); | |
1314 | return op0; | |
1315 | } | |
1316 | ||
1317 | /* To extract a signed bit-field, first shift its msb to the msb of the word, | |
1318 | then arithmetic-shift its lsb to the lsb of the word. */ | |
1319 | op0 = force_reg (mode, op0); | |
1320 | if (mode != tmode) | |
1321 | target = 0; | |
1322 | ||
1323 | /* Find the narrowest integer mode that contains the field. */ | |
1324 | ||
1325 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT); mode != VOIDmode; | |
1326 | mode = GET_MODE_WIDER_MODE (mode)) | |
1327 | if (GET_MODE_BITSIZE (mode) >= bitsize + bitpos) | |
1328 | { | |
1329 | op0 = convert_to_mode (mode, op0, 0); | |
1330 | break; | |
1331 | } | |
1332 | ||
1333 | if (GET_MODE_BITSIZE (mode) != (bitsize + bitpos)) | |
1334 | { | |
1335 | tree amount = build_int_2 (GET_MODE_BITSIZE (mode) - (bitsize + bitpos), 0); | |
1336 | /* Maybe propagate the target for the shift. */ | |
1337 | /* But not if we will return the result--could confuse integrate.c. */ | |
1338 | rtx subtarget = (target != 0 && GET_CODE (target) == REG | |
1339 | && ! REG_FUNCTION_VALUE_P (target) | |
1340 | ? target : 0); | |
1341 | op0 = expand_shift (LSHIFT_EXPR, mode, op0, amount, subtarget, 1); | |
1342 | } | |
1343 | ||
1344 | return expand_shift (RSHIFT_EXPR, mode, op0, | |
1345 | build_int_2 (GET_MODE_BITSIZE (mode) - bitsize, 0), | |
1346 | target, 0); | |
1347 | } | |
1348 | \f | |
1349 | /* Return a constant integer (CONST_INT or CONST_DOUBLE) mask value | |
1350 | of mode MODE with BITSIZE ones followed by BITPOS zeros, or the | |
1351 | complement of that if COMPLEMENT. The mask is truncated if | |
1352 | necessary to the width of mode MODE. */ | |
1353 | ||
1354 | static rtx | |
1355 | mask_rtx (mode, bitpos, bitsize, complement) | |
1356 | enum machine_mode mode; | |
1357 | int bitpos, bitsize, complement; | |
1358 | { | |
b1ec3c92 | 1359 | HOST_WIDE_INT masklow, maskhigh; |
44037a66 | 1360 | |
b1ec3c92 CH |
1361 | if (bitpos < HOST_BITS_PER_WIDE_INT) |
1362 | masklow = (HOST_WIDE_INT) -1 << bitpos; | |
44037a66 TG |
1363 | else |
1364 | masklow = 0; | |
1365 | ||
b1ec3c92 CH |
1366 | if (bitpos + bitsize < HOST_BITS_PER_WIDE_INT) |
1367 | masklow &= ((unsigned HOST_WIDE_INT) -1 | |
1368 | >> (HOST_BITS_PER_WIDE_INT - bitpos - bitsize)); | |
44037a66 | 1369 | |
b1ec3c92 | 1370 | if (bitpos <= HOST_BITS_PER_WIDE_INT) |
44037a66 TG |
1371 | maskhigh = -1; |
1372 | else | |
b1ec3c92 | 1373 | maskhigh = (HOST_WIDE_INT) -1 << (bitpos - HOST_BITS_PER_WIDE_INT); |
44037a66 | 1374 | |
b1ec3c92 CH |
1375 | if (bitpos + bitsize > HOST_BITS_PER_WIDE_INT) |
1376 | maskhigh &= ((unsigned HOST_WIDE_INT) -1 | |
1377 | >> (2 * HOST_BITS_PER_WIDE_INT - bitpos - bitsize)); | |
44037a66 TG |
1378 | else |
1379 | maskhigh = 0; | |
1380 | ||
1381 | if (complement) | |
1382 | { | |
1383 | maskhigh = ~maskhigh; | |
1384 | masklow = ~masklow; | |
1385 | } | |
1386 | ||
1387 | return immed_double_const (masklow, maskhigh, mode); | |
1388 | } | |
1389 | ||
1390 | /* Return a constant integer (CONST_INT or CONST_DOUBLE) rtx with the value | |
1391 | VALUE truncated to BITSIZE bits and then shifted left BITPOS bits. */ | |
1392 | ||
1393 | static rtx | |
1394 | lshift_value (mode, value, bitpos, bitsize) | |
1395 | enum machine_mode mode; | |
1396 | rtx value; | |
1397 | int bitpos, bitsize; | |
1398 | { | |
b1ec3c92 CH |
1399 | unsigned HOST_WIDE_INT v = INTVAL (value); |
1400 | HOST_WIDE_INT low, high; | |
44037a66 | 1401 | |
b1ec3c92 CH |
1402 | if (bitsize < HOST_BITS_PER_WIDE_INT) |
1403 | v &= ~((HOST_WIDE_INT) -1 << bitsize); | |
44037a66 | 1404 | |
b1ec3c92 | 1405 | if (bitpos < HOST_BITS_PER_WIDE_INT) |
44037a66 TG |
1406 | { |
1407 | low = v << bitpos; | |
b1ec3c92 | 1408 | high = (bitpos > 0 ? (v >> (HOST_BITS_PER_WIDE_INT - bitpos)) : 0); |
44037a66 TG |
1409 | } |
1410 | else | |
1411 | { | |
1412 | low = 0; | |
b1ec3c92 | 1413 | high = v << (bitpos - HOST_BITS_PER_WIDE_INT); |
44037a66 TG |
1414 | } |
1415 | ||
1416 | return immed_double_const (low, high, mode); | |
1417 | } | |
1418 | \f | |
1419 | /* Extract a bit field that is split across two words | |
1420 | and return an RTX for the result. | |
1421 | ||
1422 | OP0 is the REG, SUBREG or MEM rtx for the first of the two words. | |
1423 | BITSIZE is the field width; BITPOS, position of its first bit, in the word. | |
06c94bce RS |
1424 | UNSIGNEDP is 1 if should zero-extend the contents; else sign-extend. |
1425 | ||
1426 | ALIGN is the known alignment of OP0, measured in bytes. | |
1427 | This is also the size of the memory objects to be used. */ | |
44037a66 TG |
1428 | |
1429 | static rtx | |
1430 | extract_split_bit_field (op0, bitsize, bitpos, unsignedp, align) | |
1431 | rtx op0; | |
1432 | int bitsize, bitpos, unsignedp, align; | |
1433 | { | |
0eb61c19 DE |
1434 | /* Make sure UNIT isn't larger than BITS_PER_WORD, we can only handle that |
1435 | much at a time. */ | |
1436 | int unit = MIN (align * BITS_PER_UNIT, BITS_PER_WORD); | |
06c94bce RS |
1437 | int bitsdone = 0; |
1438 | rtx result; | |
1439 | int first = 1; | |
44037a66 | 1440 | |
06c94bce RS |
1441 | while (bitsdone < bitsize) |
1442 | { | |
1443 | int thissize; | |
1444 | rtx part, word; | |
1445 | int thispos; | |
1446 | int offset; | |
1447 | ||
1448 | offset = (bitpos + bitsdone) / unit; | |
1449 | thispos = (bitpos + bitsdone) % unit; | |
1450 | ||
0eb61c19 DE |
1451 | /* THISSIZE must not overrun a word boundary. Otherwise, |
1452 | extract_fixed_bit_field will call us again, and we will mutually | |
1453 | recurse forever. */ | |
1454 | thissize = MIN (bitsize - bitsdone, BITS_PER_WORD); | |
1455 | thissize = MIN (thissize, unit - thispos); | |
06c94bce RS |
1456 | |
1457 | /* If OP0 is a register, then handle OFFSET here. | |
1458 | In the register case, UNIT must be a whole word. */ | |
1459 | if (GET_CODE (op0) == SUBREG || GET_CODE (op0) == REG) | |
1460 | { | |
1461 | word = operand_subword_force (op0, offset, GET_MODE (op0)); | |
1462 | offset = 0; | |
1463 | } | |
1464 | else | |
1465 | word = op0; | |
1466 | ||
1467 | if (word == 0) | |
1468 | abort (); | |
44037a66 | 1469 | |
06c94bce | 1470 | /* Extract the parts in bit-counting order, |
0eb61c19 DE |
1471 | whose meaning is determined by BYTES_PER_UNIT. |
1472 | OFFSET is in UNITs, and UNIT is in bits. | |
1473 | extract_fixed_bit_field wants offset in bytes. */ | |
1474 | part = extract_fixed_bit_field (word_mode, word, | |
1475 | offset * unit / BITS_PER_UNIT, | |
06c94bce RS |
1476 | thissize, thispos, 0, 1, align); |
1477 | bitsdone += thissize; | |
44037a66 | 1478 | |
06c94bce | 1479 | /* Shift this part into place for the result. */ |
44037a66 | 1480 | #if BYTES_BIG_ENDIAN |
06c94bce RS |
1481 | if (bitsize != bitsdone) |
1482 | part = expand_shift (LSHIFT_EXPR, word_mode, part, | |
1483 | build_int_2 (bitsize - bitsdone, 0), 0, 1); | |
44037a66 | 1484 | #else |
06c94bce RS |
1485 | if (bitsdone != 0) |
1486 | part = expand_shift (LSHIFT_EXPR, word_mode, part, | |
1487 | build_int_2 (bitsdone, 0), 0, 1); | |
44037a66 TG |
1488 | #endif |
1489 | ||
06c94bce RS |
1490 | if (first) |
1491 | result = part; | |
1492 | else | |
1493 | /* Combine the parts with bitwise or. This works | |
1494 | because we extracted each part as an unsigned bit field. */ | |
1495 | result = expand_binop (word_mode, ior_optab, part, result, NULL_RTX, 1, | |
1496 | OPTAB_LIB_WIDEN); | |
1497 | ||
1498 | first = 0; | |
1499 | } | |
44037a66 TG |
1500 | |
1501 | /* Unsigned bit field: we are done. */ | |
1502 | if (unsignedp) | |
1503 | return result; | |
1504 | /* Signed bit field: sign-extend with two arithmetic shifts. */ | |
1505 | result = expand_shift (LSHIFT_EXPR, word_mode, result, | |
b1ec3c92 CH |
1506 | build_int_2 (BITS_PER_WORD - bitsize, 0), |
1507 | NULL_RTX, 0); | |
44037a66 | 1508 | return expand_shift (RSHIFT_EXPR, word_mode, result, |
b1ec3c92 | 1509 | build_int_2 (BITS_PER_WORD - bitsize, 0), NULL_RTX, 0); |
44037a66 TG |
1510 | } |
1511 | \f | |
1512 | /* Add INC into TARGET. */ | |
1513 | ||
1514 | void | |
1515 | expand_inc (target, inc) | |
1516 | rtx target, inc; | |
1517 | { | |
1518 | rtx value = expand_binop (GET_MODE (target), add_optab, | |
1519 | target, inc, | |
1520 | target, 0, OPTAB_LIB_WIDEN); | |
1521 | if (value != target) | |
1522 | emit_move_insn (target, value); | |
1523 | } | |
1524 | ||
1525 | /* Subtract DEC from TARGET. */ | |
1526 | ||
1527 | void | |
1528 | expand_dec (target, dec) | |
1529 | rtx target, dec; | |
1530 | { | |
1531 | rtx value = expand_binop (GET_MODE (target), sub_optab, | |
1532 | target, dec, | |
1533 | target, 0, OPTAB_LIB_WIDEN); | |
1534 | if (value != target) | |
1535 | emit_move_insn (target, value); | |
1536 | } | |
1537 | \f | |
1538 | /* Output a shift instruction for expression code CODE, | |
1539 | with SHIFTED being the rtx for the value to shift, | |
1540 | and AMOUNT the tree for the amount to shift by. | |
1541 | Store the result in the rtx TARGET, if that is convenient. | |
1542 | If UNSIGNEDP is nonzero, do a logical shift; otherwise, arithmetic. | |
1543 | Return the rtx for where the value is. */ | |
1544 | ||
1545 | rtx | |
1546 | expand_shift (code, mode, shifted, amount, target, unsignedp) | |
1547 | enum tree_code code; | |
1548 | register enum machine_mode mode; | |
1549 | rtx shifted; | |
1550 | tree amount; | |
1551 | register rtx target; | |
1552 | int unsignedp; | |
1553 | { | |
1554 | register rtx op1, temp = 0; | |
1555 | register int left = (code == LSHIFT_EXPR || code == LROTATE_EXPR); | |
1556 | register int rotate = (code == LROTATE_EXPR || code == RROTATE_EXPR); | |
1557 | int try; | |
1558 | ||
1559 | /* Previously detected shift-counts computed by NEGATE_EXPR | |
1560 | and shifted in the other direction; but that does not work | |
1561 | on all machines. */ | |
1562 | ||
b1ec3c92 | 1563 | op1 = expand_expr (amount, NULL_RTX, VOIDmode, 0); |
44037a66 TG |
1564 | |
1565 | if (op1 == const0_rtx) | |
1566 | return shifted; | |
1567 | ||
1568 | for (try = 0; temp == 0 && try < 3; try++) | |
1569 | { | |
1570 | enum optab_methods methods; | |
1571 | ||
1572 | if (try == 0) | |
1573 | methods = OPTAB_DIRECT; | |
1574 | else if (try == 1) | |
1575 | methods = OPTAB_WIDEN; | |
1576 | else | |
1577 | methods = OPTAB_LIB_WIDEN; | |
1578 | ||
1579 | if (rotate) | |
1580 | { | |
1581 | /* Widening does not work for rotation. */ | |
1582 | if (methods == OPTAB_WIDEN) | |
1583 | continue; | |
1584 | else if (methods == OPTAB_LIB_WIDEN) | |
cbec710e RK |
1585 | { |
1586 | /* If we are rotating by a constant that is valid and | |
1587 | we have been unable to open-code this by a rotation, | |
1588 | do it as the IOR of two shifts. I.e., to rotate A | |
1589 | by N bits, compute (A << N) | ((unsigned) A >> (C - N)) | |
1590 | where C is the bitsize of A. | |
1591 | ||
1592 | It is theoretically possible that the target machine might | |
1593 | not be able to perform either shift and hence we would | |
1594 | be making two libcalls rather than just the one for the | |
1595 | shift (similarly if IOR could not be done). We will allow | |
1596 | this extremely unlikely lossage to avoid complicating the | |
1597 | code below. */ | |
1598 | ||
1599 | if (GET_CODE (op1) == CONST_INT && INTVAL (op1) > 0 | |
1600 | && INTVAL (op1) < GET_MODE_BITSIZE (mode)) | |
1601 | { | |
1602 | rtx subtarget = target == shifted ? 0 : target; | |
1603 | rtx temp1; | |
1604 | tree other_amount | |
1605 | = build_int_2 (GET_MODE_BITSIZE (mode) - INTVAL (op1), 0); | |
1606 | ||
1607 | shifted = force_reg (mode, shifted); | |
1608 | ||
1609 | temp = expand_shift (left ? LSHIFT_EXPR : RSHIFT_EXPR, | |
1610 | mode, shifted, amount, subtarget, 1); | |
1611 | temp1 = expand_shift (left ? RSHIFT_EXPR : LSHIFT_EXPR, | |
1612 | mode, shifted, other_amount, 0, 1); | |
1613 | return expand_binop (mode, ior_optab, temp, temp1, target, | |
1614 | unsignedp, methods); | |
1615 | } | |
1616 | else | |
1617 | methods = OPTAB_LIB; | |
1618 | } | |
44037a66 TG |
1619 | |
1620 | temp = expand_binop (mode, | |
1621 | left ? rotl_optab : rotr_optab, | |
1622 | shifted, op1, target, unsignedp, methods); | |
cbec710e RK |
1623 | |
1624 | /* If we don't have the rotate, but we are rotating by a constant | |
1625 | that is in range, try a rotate in the opposite direction. */ | |
1626 | ||
1627 | if (temp == 0 && GET_CODE (op1) == CONST_INT | |
1628 | && INTVAL (op1) > 0 && INTVAL (op1) < GET_MODE_BITSIZE (mode)) | |
1629 | temp = expand_binop (mode, | |
1630 | left ? rotr_optab : rotl_optab, | |
1631 | shifted, | |
1632 | GEN_INT (GET_MODE_BITSIZE (mode) | |
1633 | - INTVAL (op1)), | |
1634 | target, unsignedp, methods); | |
44037a66 TG |
1635 | } |
1636 | else if (unsignedp) | |
1637 | { | |
1638 | temp = expand_binop (mode, | |
1639 | left ? lshl_optab : lshr_optab, | |
1640 | shifted, op1, target, unsignedp, methods); | |
1641 | if (temp == 0 && left) | |
1642 | temp = expand_binop (mode, ashl_optab, | |
1643 | shifted, op1, target, unsignedp, methods); | |
1644 | } | |
1645 | ||
1646 | /* Do arithmetic shifts. | |
1647 | Also, if we are going to widen the operand, we can just as well | |
1648 | use an arithmetic right-shift instead of a logical one. */ | |
1649 | if (temp == 0 && ! rotate | |
1650 | && (! unsignedp || (! left && methods == OPTAB_WIDEN))) | |
1651 | { | |
1652 | enum optab_methods methods1 = methods; | |
1653 | ||
1654 | /* If trying to widen a log shift to an arithmetic shift, | |
1655 | don't accept an arithmetic shift of the same size. */ | |
1656 | if (unsignedp) | |
1657 | methods1 = OPTAB_MUST_WIDEN; | |
1658 | ||
1659 | /* Arithmetic shift */ | |
1660 | ||
1661 | temp = expand_binop (mode, | |
1662 | left ? ashl_optab : ashr_optab, | |
1663 | shifted, op1, target, unsignedp, methods1); | |
1664 | } | |
1665 | ||
1666 | #ifdef HAVE_extzv | |
1667 | /* We can do a logical (unsigned) right shift with a bit-field | |
1668 | extract insn. But first check if one of the above methods worked. */ | |
1669 | if (temp != 0) | |
1670 | return temp; | |
1671 | ||
1672 | if (unsignedp && code == RSHIFT_EXPR && ! BITS_BIG_ENDIAN && HAVE_extzv) | |
1673 | { | |
1674 | enum machine_mode output_mode | |
1675 | = insn_operand_mode[(int) CODE_FOR_extzv][0]; | |
1676 | ||
1677 | if ((methods == OPTAB_DIRECT && mode == output_mode) | |
1678 | || (methods == OPTAB_WIDEN | |
1679 | && GET_MODE_SIZE (mode) < GET_MODE_SIZE (output_mode))) | |
1680 | { | |
b3d4e1b2 RS |
1681 | rtx shifted1 = convert_to_mode (output_mode, |
1682 | protect_from_queue (shifted, 0), | |
1683 | 1); | |
44037a66 TG |
1684 | enum machine_mode length_mode |
1685 | = insn_operand_mode[(int) CODE_FOR_extzv][2]; | |
1686 | enum machine_mode pos_mode | |
1687 | = insn_operand_mode[(int) CODE_FOR_extzv][3]; | |
1688 | rtx target1 = 0; | |
1689 | rtx last = get_last_insn (); | |
1690 | rtx width; | |
1691 | rtx xop1 = op1; | |
1692 | rtx pat; | |
1693 | ||
1694 | if (target != 0) | |
1695 | target1 = protect_from_queue (target, 1); | |
1696 | ||
1697 | /* We define extract insns as having OUTPUT_MODE in a register | |
1698 | and the mode of operand 1 in memory. Since we want | |
1699 | OUTPUT_MODE, we will always force the operand into a | |
1700 | register. At some point we might want to support MEM | |
1701 | directly. */ | |
1702 | shifted1 = force_reg (output_mode, shifted1); | |
1703 | ||
1704 | /* If we don't have or cannot use a suggested target, | |
1705 | make a place for the result, in the proper mode. */ | |
1706 | if (methods == OPTAB_WIDEN || target1 == 0 | |
1707 | || ! ((*insn_operand_predicate[(int) CODE_FOR_extzv][0]) | |
1708 | (target1, output_mode))) | |
1709 | target1 = gen_reg_rtx (output_mode); | |
1710 | ||
b3d4e1b2 | 1711 | xop1 = protect_from_queue (xop1, 0); |
44037a66 TG |
1712 | xop1 = convert_to_mode (pos_mode, xop1, |
1713 | TREE_UNSIGNED (TREE_TYPE (amount))); | |
1714 | ||
1715 | /* If this machine's extzv insists on a register for | |
1716 | operand 3 (position), arrange for that. */ | |
1717 | if (! ((*insn_operand_predicate[(int) CODE_FOR_extzv][3]) | |
1718 | (xop1, pos_mode))) | |
1719 | xop1 = force_reg (pos_mode, xop1); | |
1720 | ||
1721 | /* WIDTH gets the width of the bit field to extract: | |
1722 | wordsize minus # bits to shift by. */ | |
1723 | if (GET_CODE (xop1) == CONST_INT) | |
b1ec3c92 | 1724 | width = GEN_INT (GET_MODE_BITSIZE (mode) - INTVAL (op1)); |
44037a66 TG |
1725 | else |
1726 | { | |
1727 | /* Now get the width in the proper mode. */ | |
b3d4e1b2 | 1728 | op1 = protect_from_queue (op1, 0); |
44037a66 TG |
1729 | width = convert_to_mode (length_mode, op1, |
1730 | TREE_UNSIGNED (TREE_TYPE (amount))); | |
1731 | ||
1732 | width = expand_binop (length_mode, sub_optab, | |
b1ec3c92 CH |
1733 | GEN_INT (GET_MODE_BITSIZE (mode)), |
1734 | width, NULL_RTX, 0, OPTAB_LIB_WIDEN); | |
44037a66 TG |
1735 | } |
1736 | ||
1737 | /* If this machine's extzv insists on a register for | |
1738 | operand 2 (length), arrange for that. */ | |
1739 | if (! ((*insn_operand_predicate[(int) CODE_FOR_extzv][2]) | |
1740 | (width, length_mode))) | |
1741 | width = force_reg (length_mode, width); | |
1742 | ||
1743 | /* Now extract with WIDTH, omitting OP1 least sig bits. */ | |
1744 | pat = gen_extzv (target1, shifted1, width, xop1); | |
1745 | if (pat) | |
1746 | { | |
1747 | emit_insn (pat); | |
1748 | temp = convert_to_mode (mode, target1, 1); | |
1749 | } | |
1750 | else | |
1751 | delete_insns_since (last); | |
1752 | } | |
1753 | ||
1754 | /* Can also do logical shift with signed bit-field extract | |
1755 | followed by inserting the bit-field at a different position. | |
1756 | That strategy is not yet implemented. */ | |
1757 | } | |
1758 | #endif /* HAVE_extzv */ | |
1759 | } | |
1760 | ||
1761 | if (temp == 0) | |
1762 | abort (); | |
1763 | return temp; | |
1764 | } | |
1765 | \f | |
b385aeda | 1766 | enum alg_code { alg_zero, alg_m, alg_shift, |
b2fb324c | 1767 | alg_add_t_m2, alg_sub_t_m2, |
7963ac37 RK |
1768 | alg_add_factor, alg_sub_factor, |
1769 | alg_add_t2_m, alg_sub_t2_m, | |
b385aeda | 1770 | alg_add, alg_subtract, alg_factor, alg_shiftop }; |
44037a66 TG |
1771 | |
1772 | /* This structure records a sequence of operations. | |
1773 | `ops' is the number of operations recorded. | |
1774 | `cost' is their total cost. | |
1775 | The operations are stored in `op' and the corresponding | |
b385aeda RK |
1776 | logarithms of the integer coefficients in `log'. |
1777 | ||
44037a66 | 1778 | These are the operations: |
b385aeda RK |
1779 | alg_zero total := 0; |
1780 | alg_m total := multiplicand; | |
b2fb324c | 1781 | alg_shift total := total * coeff |
7963ac37 RK |
1782 | alg_add_t_m2 total := total + multiplicand * coeff; |
1783 | alg_sub_t_m2 total := total - multiplicand * coeff; | |
1784 | alg_add_factor total := total * coeff + total; | |
1785 | alg_sub_factor total := total * coeff - total; | |
1786 | alg_add_t2_m total := total * coeff + multiplicand; | |
1787 | alg_sub_t2_m total := total * coeff - multiplicand; | |
b385aeda RK |
1788 | |
1789 | The first operand must be either alg_zero or alg_m. */ | |
44037a66 | 1790 | |
44037a66 TG |
1791 | struct algorithm |
1792 | { | |
7963ac37 RK |
1793 | short cost; |
1794 | short ops; | |
b385aeda RK |
1795 | /* The size of the OP and LOG fields are not directly related to the |
1796 | word size, but the worst-case algorithms will be if we have few | |
1797 | consecutive ones or zeros, i.e., a multiplicand like 10101010101... | |
1798 | In that case we will generate shift-by-2, add, shift-by-2, add,..., | |
1799 | in total wordsize operations. */ | |
44037a66 | 1800 | enum alg_code op[MAX_BITS_PER_WORD]; |
b385aeda | 1801 | char log[MAX_BITS_PER_WORD]; |
44037a66 TG |
1802 | }; |
1803 | ||
1804 | /* Compute and return the best algorithm for multiplying by T. | |
7963ac37 RK |
1805 | The algorithm must cost less than cost_limit |
1806 | If retval.cost >= COST_LIMIT, no algorithm was found and all | |
1807 | other field of the returned struct are undefined. */ | |
44037a66 | 1808 | |
819126a6 RK |
1809 | static void |
1810 | synth_mult (alg_out, t, cost_limit) | |
1811 | struct algorithm *alg_out; | |
b1ec3c92 | 1812 | unsigned HOST_WIDE_INT t; |
7963ac37 | 1813 | int cost_limit; |
44037a66 | 1814 | { |
b2fb324c | 1815 | int m; |
b1ec3c92 CH |
1816 | struct algorithm *best_alg |
1817 | = (struct algorithm *)alloca (sizeof (struct algorithm)); | |
1818 | struct algorithm *alg_in | |
1819 | = (struct algorithm *)alloca (sizeof (struct algorithm)); | |
44037a66 | 1820 | unsigned int cost; |
b2fb324c | 1821 | unsigned HOST_WIDE_INT q; |
44037a66 | 1822 | |
7963ac37 RK |
1823 | /* Indicate that no algorithm is yet found. If no algorithm |
1824 | is found, this value will be returned and indicate failure. */ | |
819126a6 | 1825 | alg_out->cost = cost_limit; |
44037a66 | 1826 | |
b2fb324c | 1827 | if (cost_limit <= 0) |
819126a6 | 1828 | return; |
44037a66 | 1829 | |
b385aeda RK |
1830 | /* t == 1 can be done in zero cost. */ |
1831 | if (t == 1) | |
b2fb324c | 1832 | { |
819126a6 RK |
1833 | alg_out->ops = 1; |
1834 | alg_out->cost = 0; | |
1835 | alg_out->op[0] = alg_m; | |
1836 | return; | |
b2fb324c RK |
1837 | } |
1838 | ||
b385aeda RK |
1839 | /* t == 0 sometimes has a cost. If it does and it exceeds our limit, |
1840 | fail now. */ | |
819126a6 | 1841 | if (t == 0) |
b385aeda RK |
1842 | { |
1843 | if (zero_cost >= cost_limit) | |
819126a6 | 1844 | return; |
b385aeda RK |
1845 | else |
1846 | { | |
819126a6 RK |
1847 | alg_out->ops = 1; |
1848 | alg_out->cost = zero_cost; | |
1849 | alg_out->op[0] = alg_zero; | |
1850 | return; | |
b385aeda RK |
1851 | } |
1852 | } | |
1853 | ||
1854 | /* If we have a group of zero bits at the low-order part of T, try | |
1855 | multiplying by the remaining bits and then doing a shift. */ | |
1856 | ||
b2fb324c | 1857 | if ((t & 1) == 0) |
44037a66 | 1858 | { |
b2fb324c RK |
1859 | m = floor_log2 (t & -t); /* m = number of low zero bits */ |
1860 | q = t >> m; | |
1861 | cost = shift_cost[m]; | |
819126a6 RK |
1862 | synth_mult (alg_in, q, cost_limit - cost); |
1863 | ||
1864 | cost += alg_in->cost; | |
b2fb324c | 1865 | if (cost < cost_limit) |
44037a66 | 1866 | { |
819126a6 RK |
1867 | struct algorithm *x; |
1868 | x = alg_in, alg_in = best_alg, best_alg = x; | |
1869 | best_alg->log[best_alg->ops] = m; | |
1870 | best_alg->op[best_alg->ops] = alg_shift; | |
1871 | cost_limit = cost; | |
1872 | } | |
1873 | } | |
1874 | ||
1875 | /* If we have an odd number, add or subtract one. */ | |
1876 | if ((t & 1) != 0) | |
1877 | { | |
1878 | unsigned HOST_WIDE_INT w; | |
1879 | ||
1880 | for (w = 1; (w & t) != 0; w <<= 1) | |
1881 | ; | |
1882 | if (w > 2 | |
1883 | /* Reject the case where t is 3. | |
1884 | Thus we prefer addition in that case. */ | |
1885 | && t != 3) | |
1886 | { | |
1887 | /* T ends with ...111. Multiply by (T + 1) and subtract 1. */ | |
1888 | ||
1889 | cost = add_cost; | |
1890 | synth_mult (alg_in, t + 1, cost_limit - cost); | |
b2fb324c RK |
1891 | |
1892 | cost += alg_in->cost; | |
819126a6 | 1893 | if (cost < cost_limit) |
44037a66 | 1894 | { |
b2fb324c RK |
1895 | struct algorithm *x; |
1896 | x = alg_in, alg_in = best_alg, best_alg = x; | |
819126a6 RK |
1897 | best_alg->log[best_alg->ops] = 0; |
1898 | best_alg->op[best_alg->ops] = alg_sub_t_m2; | |
1899 | cost_limit = cost; | |
44037a66 | 1900 | } |
44037a66 | 1901 | } |
819126a6 RK |
1902 | else |
1903 | { | |
1904 | /* T ends with ...01 or ...011. Multiply by (T - 1) and add 1. */ | |
44037a66 | 1905 | |
819126a6 RK |
1906 | cost = add_cost; |
1907 | synth_mult (alg_in, t - 1, cost_limit - cost); | |
1908 | ||
1909 | cost += alg_in->cost; | |
1910 | if (cost < cost_limit) | |
1911 | { | |
1912 | struct algorithm *x; | |
1913 | x = alg_in, alg_in = best_alg, best_alg = x; | |
1914 | best_alg->log[best_alg->ops] = 0; | |
1915 | best_alg->op[best_alg->ops] = alg_add_t_m2; | |
1916 | cost_limit = cost; | |
1917 | } | |
1918 | } | |
1919 | } | |
63610db9 | 1920 | |
44037a66 | 1921 | /* Look for factors of t of the form |
7963ac37 | 1922 | t = q(2**m +- 1), 2 <= m <= floor(log2(t - 1)). |
44037a66 | 1923 | If we find such a factor, we can multiply by t using an algorithm that |
7963ac37 | 1924 | multiplies by q, shift the result by m and add/subtract it to itself. |
44037a66 | 1925 | |
7963ac37 RK |
1926 | We search for large factors first and loop down, even if large factors |
1927 | are less probable than small; if we find a large factor we will find a | |
1928 | good sequence quickly, and therefore be able to prune (by decreasing | |
1929 | COST_LIMIT) the search. */ | |
1930 | ||
1931 | for (m = floor_log2 (t - 1); m >= 2; m--) | |
44037a66 | 1932 | { |
7963ac37 | 1933 | unsigned HOST_WIDE_INT d; |
44037a66 | 1934 | |
7963ac37 RK |
1935 | d = ((unsigned HOST_WIDE_INT) 1 << m) + 1; |
1936 | if (t % d == 0 && t > d) | |
44037a66 | 1937 | { |
b385aeda | 1938 | cost = MIN (shiftadd_cost[m], add_cost + shift_cost[m]); |
819126a6 | 1939 | synth_mult (alg_in, t / d, cost_limit - cost); |
44037a66 | 1940 | |
7963ac37 | 1941 | cost += alg_in->cost; |
819126a6 | 1942 | if (cost < cost_limit) |
44037a66 | 1943 | { |
7963ac37 RK |
1944 | struct algorithm *x; |
1945 | x = alg_in, alg_in = best_alg, best_alg = x; | |
b385aeda | 1946 | best_alg->log[best_alg->ops] = m; |
819126a6 RK |
1947 | best_alg->op[best_alg->ops] = alg_add_factor; |
1948 | cost_limit = cost; | |
44037a66 TG |
1949 | } |
1950 | } | |
1951 | ||
7963ac37 RK |
1952 | d = ((unsigned HOST_WIDE_INT) 1 << m) - 1; |
1953 | if (t % d == 0 && t > d) | |
44037a66 | 1954 | { |
b385aeda | 1955 | cost = MIN (shiftsub_cost[m], add_cost + shift_cost[m]); |
819126a6 | 1956 | synth_mult (alg_in, t / d, cost_limit - cost); |
44037a66 | 1957 | |
7963ac37 | 1958 | cost += alg_in->cost; |
819126a6 | 1959 | if (cost < cost_limit) |
44037a66 | 1960 | { |
7963ac37 RK |
1961 | struct algorithm *x; |
1962 | x = alg_in, alg_in = best_alg, best_alg = x; | |
b385aeda | 1963 | best_alg->log[best_alg->ops] = m; |
819126a6 RK |
1964 | best_alg->op[best_alg->ops] = alg_sub_factor; |
1965 | cost_limit = cost; | |
44037a66 TG |
1966 | } |
1967 | } | |
1968 | } | |
1969 | ||
7963ac37 RK |
1970 | /* Try shift-and-add (load effective address) instructions, |
1971 | i.e. do a*3, a*5, a*9. */ | |
1972 | if ((t & 1) != 0) | |
1973 | { | |
7963ac37 RK |
1974 | q = t - 1; |
1975 | q = q & -q; | |
1976 | m = exact_log2 (q); | |
5eebe2eb | 1977 | if (m >= 0) |
b385aeda | 1978 | { |
5eebe2eb | 1979 | cost = shiftadd_cost[m]; |
819126a6 | 1980 | synth_mult (alg_in, (t - 1) >> m, cost_limit - cost); |
5eebe2eb RK |
1981 | |
1982 | cost += alg_in->cost; | |
819126a6 | 1983 | if (cost < cost_limit) |
5eebe2eb RK |
1984 | { |
1985 | struct algorithm *x; | |
1986 | x = alg_in, alg_in = best_alg, best_alg = x; | |
1987 | best_alg->log[best_alg->ops] = m; | |
819126a6 RK |
1988 | best_alg->op[best_alg->ops] = alg_add_t2_m; |
1989 | cost_limit = cost; | |
5eebe2eb | 1990 | } |
7963ac37 | 1991 | } |
44037a66 | 1992 | |
7963ac37 RK |
1993 | q = t + 1; |
1994 | q = q & -q; | |
1995 | m = exact_log2 (q); | |
5eebe2eb | 1996 | if (m >= 0) |
b385aeda | 1997 | { |
5eebe2eb | 1998 | cost = shiftsub_cost[m]; |
819126a6 | 1999 | synth_mult (alg_in, (t + 1) >> m, cost_limit - cost); |
5eebe2eb RK |
2000 | |
2001 | cost += alg_in->cost; | |
819126a6 | 2002 | if (cost < cost_limit) |
5eebe2eb RK |
2003 | { |
2004 | struct algorithm *x; | |
2005 | x = alg_in, alg_in = best_alg, best_alg = x; | |
2006 | best_alg->log[best_alg->ops] = m; | |
819126a6 RK |
2007 | best_alg->op[best_alg->ops] = alg_sub_t2_m; |
2008 | cost_limit = cost; | |
5eebe2eb | 2009 | } |
7963ac37 RK |
2010 | } |
2011 | } | |
44037a66 | 2012 | |
b2fb324c | 2013 | /* If we are getting a too long sequence for `struct algorithm' |
819126a6 | 2014 | to record, make this search fail. */ |
b2fb324c | 2015 | if (best_alg->ops == MAX_BITS_PER_WORD) |
819126a6 RK |
2016 | return; |
2017 | ||
2018 | /* If cost_limit has not decreased since we stored it in alg_out->cost, | |
2019 | we have not found any algorithm. */ | |
2020 | if (cost_limit == alg_out->cost) | |
2021 | return; | |
2022 | ||
2023 | /* Copy the algorithm from temporary space to the space at alg_out. | |
2024 | We avoid using structure assignment because the majority of | |
2025 | best_alg is normally undefined, and this is a critical function. */ | |
2026 | alg_out->ops = best_alg->ops + 1; | |
2027 | alg_out->cost = cost_limit; | |
2028 | bcopy (best_alg->op, alg_out->op, alg_out->ops * sizeof *alg_out->op); | |
2029 | bcopy (best_alg->log, alg_out->log, alg_out->ops * sizeof *alg_out->log); | |
44037a66 TG |
2030 | } |
2031 | \f | |
2032 | /* Perform a multiplication and return an rtx for the result. | |
2033 | MODE is mode of value; OP0 and OP1 are what to multiply (rtx's); | |
2034 | TARGET is a suggestion for where to store the result (an rtx). | |
2035 | ||
2036 | We check specially for a constant integer as OP1. | |
2037 | If you want this check for OP0 as well, then before calling | |
2038 | you should swap the two operands if OP0 would be constant. */ | |
2039 | ||
2040 | rtx | |
2041 | expand_mult (mode, op0, op1, target, unsignedp) | |
2042 | enum machine_mode mode; | |
2043 | register rtx op0, op1, target; | |
2044 | int unsignedp; | |
2045 | { | |
2046 | rtx const_op1 = op1; | |
2047 | ||
2048 | /* If we are multiplying in DImode, it may still be a win | |
2049 | to try to work with shifts and adds. */ | |
2050 | if (GET_CODE (op1) == CONST_DOUBLE | |
2051 | && GET_MODE_CLASS (GET_MODE (op1)) == MODE_INT | |
2052 | && HOST_BITS_PER_INT <= BITS_PER_WORD) | |
2053 | { | |
2054 | if ((CONST_DOUBLE_HIGH (op1) == 0 && CONST_DOUBLE_LOW (op1) >= 0) | |
2055 | || (CONST_DOUBLE_HIGH (op1) == -1 && CONST_DOUBLE_LOW (op1) < 0)) | |
b1ec3c92 | 2056 | const_op1 = GEN_INT (CONST_DOUBLE_LOW (op1)); |
44037a66 TG |
2057 | } |
2058 | ||
66c1f88e RS |
2059 | /* We used to test optimize here, on the grounds that it's better to |
2060 | produce a smaller program when -O is not used. | |
2061 | But this causes such a terrible slowdown sometimes | |
2062 | that it seems better to use synth_mult always. */ | |
b385aeda | 2063 | |
819126a6 | 2064 | if (GET_CODE (const_op1) == CONST_INT) |
44037a66 TG |
2065 | { |
2066 | struct algorithm alg; | |
2067 | struct algorithm neg_alg; | |
2068 | int negate = 0; | |
7963ac37 | 2069 | HOST_WIDE_INT val = INTVAL (op1); |
b385aeda RK |
2070 | HOST_WIDE_INT val_so_far; |
2071 | rtx insn; | |
819126a6 | 2072 | int mult_cost; |
44037a66 TG |
2073 | |
2074 | /* Try to do the computation two ways: multiply by the negative of OP1 | |
2075 | and then negate, or do the multiplication directly. The latter is | |
2076 | usually faster for positive numbers and the former for negative | |
2077 | numbers, but the opposite can be faster if the original value | |
2078 | has a factor of 2**m +/- 1, while the negated value does not or | |
2079 | vice versa. */ | |
2080 | ||
819126a6 RK |
2081 | mult_cost = rtx_cost (gen_rtx (MULT, mode, op0, op1), SET); |
2082 | mult_cost = MIN (12 * add_cost, mult_cost); | |
2083 | ||
2084 | synth_mult (&alg, val, mult_cost); | |
2085 | synth_mult (&neg_alg, - val, | |
2086 | (alg.cost < mult_cost ? alg.cost : mult_cost) - negate_cost); | |
44037a66 | 2087 | |
7963ac37 | 2088 | if (neg_alg.cost + negate_cost < alg.cost) |
5eebe2eb | 2089 | alg = neg_alg, negate = 1; |
44037a66 | 2090 | |
7963ac37 | 2091 | if (alg.cost < mult_cost) |
44037a66 | 2092 | { |
b2fb324c | 2093 | /* We found something cheaper than a multiply insn. */ |
7963ac37 | 2094 | int opno; |
44037a66 | 2095 | rtx accum, tem; |
44037a66 TG |
2096 | |
2097 | op0 = protect_from_queue (op0, 0); | |
2098 | ||
2099 | /* Avoid referencing memory over and over. | |
2100 | For speed, but also for correctness when mem is volatile. */ | |
2101 | if (GET_CODE (op0) == MEM) | |
2102 | op0 = force_reg (mode, op0); | |
2103 | ||
b385aeda RK |
2104 | /* ACCUM starts out either as OP0 or as a zero, depending on |
2105 | the first operation. */ | |
2106 | ||
2107 | if (alg.op[0] == alg_zero) | |
44037a66 | 2108 | { |
b385aeda RK |
2109 | accum = copy_to_mode_reg (mode, const0_rtx); |
2110 | val_so_far = 0; | |
2111 | } | |
2112 | else if (alg.op[0] == alg_m) | |
2113 | { | |
819126a6 | 2114 | accum = copy_to_mode_reg (mode, op0); |
b385aeda | 2115 | val_so_far = 1; |
44037a66 | 2116 | } |
b385aeda RK |
2117 | else |
2118 | abort (); | |
7963ac37 RK |
2119 | |
2120 | for (opno = 1; opno < alg.ops; opno++) | |
44037a66 | 2121 | { |
b385aeda RK |
2122 | int log = alg.log[opno]; |
2123 | rtx shift_subtarget = preserve_subexpressions_p () ? 0 : accum; | |
2124 | rtx add_target = opno == alg.ops - 1 && target != 0 ? target : 0; | |
2125 | ||
44037a66 TG |
2126 | switch (alg.op[opno]) |
2127 | { | |
b2fb324c RK |
2128 | case alg_shift: |
2129 | accum = expand_shift (LSHIFT_EXPR, mode, accum, | |
2130 | build_int_2 (log, 0), NULL_RTX, 0); | |
b385aeda | 2131 | val_so_far <<= log; |
b2fb324c RK |
2132 | break; |
2133 | ||
7963ac37 | 2134 | case alg_add_t_m2: |
b385aeda RK |
2135 | tem = expand_shift (LSHIFT_EXPR, mode, op0, |
2136 | build_int_2 (log, 0), NULL_RTX, 0); | |
2137 | accum = force_operand (gen_rtx (PLUS, mode, accum, tem), | |
2138 | add_target ? add_target : accum); | |
2139 | val_so_far += (HOST_WIDE_INT) 1 << log; | |
44037a66 TG |
2140 | break; |
2141 | ||
7963ac37 | 2142 | case alg_sub_t_m2: |
b385aeda RK |
2143 | tem = expand_shift (LSHIFT_EXPR, mode, op0, |
2144 | build_int_2 (log, 0), NULL_RTX, 0); | |
2145 | accum = force_operand (gen_rtx (MINUS, mode, accum, tem), | |
2146 | add_target ? add_target : accum); | |
2147 | val_so_far -= (HOST_WIDE_INT) 1 << log; | |
7963ac37 | 2148 | break; |
44037a66 | 2149 | |
7963ac37 RK |
2150 | case alg_add_t2_m: |
2151 | accum = expand_shift (LSHIFT_EXPR, mode, accum, | |
b385aeda | 2152 | build_int_2 (log, 0), accum, 0); |
7963ac37 | 2153 | accum = force_operand (gen_rtx (PLUS, mode, accum, op0), |
b385aeda RK |
2154 | add_target ? add_target : accum); |
2155 | val_so_far = (val_so_far << log) + 1; | |
44037a66 TG |
2156 | break; |
2157 | ||
7963ac37 RK |
2158 | case alg_sub_t2_m: |
2159 | accum = expand_shift (LSHIFT_EXPR, mode, accum, | |
b385aeda | 2160 | build_int_2 (log, 0), accum, 0); |
7963ac37 | 2161 | accum = force_operand (gen_rtx (MINUS, mode, accum, op0), |
b385aeda RK |
2162 | add_target ? add_target : accum); |
2163 | val_so_far = (val_so_far << log) - 1; | |
7963ac37 RK |
2164 | break; |
2165 | ||
2166 | case alg_add_factor: | |
44037a66 | 2167 | tem = expand_shift (LSHIFT_EXPR, mode, accum, |
b1ec3c92 | 2168 | build_int_2 (log, 0), NULL_RTX, 0); |
b385aeda RK |
2169 | accum = force_operand (gen_rtx (PLUS, mode, accum, tem), |
2170 | add_target ? add_target : accum); | |
2171 | val_so_far += val_so_far << log; | |
7963ac37 | 2172 | break; |
44037a66 | 2173 | |
7963ac37 RK |
2174 | case alg_sub_factor: |
2175 | tem = expand_shift (LSHIFT_EXPR, mode, accum, | |
2176 | build_int_2 (log, 0), NULL_RTX, 0); | |
2177 | accum = force_operand (gen_rtx (MINUS, mode, tem, accum), | |
b385aeda RK |
2178 | add_target ? add_target : tem); |
2179 | val_so_far = (val_so_far << log) - val_so_far; | |
7963ac37 | 2180 | break; |
44037a66 | 2181 | |
b385aeda RK |
2182 | default: |
2183 | abort ();; | |
2184 | } | |
44037a66 | 2185 | |
b385aeda RK |
2186 | /* Write a REG_EQUAL note on the last insn so that we can cse |
2187 | multiplication sequences. */ | |
44037a66 | 2188 | |
b385aeda RK |
2189 | insn = get_last_insn (); |
2190 | REG_NOTES (insn) | |
2191 | = gen_rtx (EXPR_LIST, REG_EQUAL, | |
2192 | gen_rtx (MULT, mode, op0, GEN_INT (val_so_far)), | |
2193 | REG_NOTES (insn)); | |
2194 | } | |
44037a66 | 2195 | |
b385aeda | 2196 | if (negate) |
44037a66 | 2197 | { |
b385aeda RK |
2198 | val_so_far = - val_so_far; |
2199 | accum = expand_unop (mode, neg_optab, accum, target, 0); | |
44037a66 TG |
2200 | } |
2201 | ||
b385aeda RK |
2202 | if (val != val_so_far) |
2203 | abort (); | |
2204 | ||
2205 | return accum; | |
44037a66 TG |
2206 | } |
2207 | } | |
2208 | ||
819126a6 RK |
2209 | /* This used to use umul_optab if unsigned, but for non-widening multiply |
2210 | there is no difference between signed and unsigned. */ | |
44037a66 TG |
2211 | op0 = expand_binop (mode, smul_optab, |
2212 | op0, op1, target, unsignedp, OPTAB_LIB_WIDEN); | |
2213 | if (op0 == 0) | |
2214 | abort (); | |
2215 | return op0; | |
2216 | } | |
2217 | \f | |
2218 | /* Emit the code to divide OP0 by OP1, putting the result in TARGET | |
2219 | if that is convenient, and returning where the result is. | |
2220 | You may request either the quotient or the remainder as the result; | |
2221 | specify REM_FLAG nonzero to get the remainder. | |
2222 | ||
2223 | CODE is the expression code for which kind of division this is; | |
2224 | it controls how rounding is done. MODE is the machine mode to use. | |
2225 | UNSIGNEDP nonzero means do unsigned division. */ | |
2226 | ||
2227 | /* ??? For CEIL_MOD_EXPR, can compute incorrect remainder with ANDI | |
2228 | and then correct it by or'ing in missing high bits | |
2229 | if result of ANDI is nonzero. | |
2230 | For ROUND_MOD_EXPR, can use ANDI and then sign-extend the result. | |
2231 | This could optimize to a bfexts instruction. | |
2232 | But C doesn't use these operations, so their optimizations are | |
2233 | left for later. */ | |
2234 | ||
2235 | rtx | |
2236 | expand_divmod (rem_flag, code, mode, op0, op1, target, unsignedp) | |
2237 | int rem_flag; | |
2238 | enum tree_code code; | |
2239 | enum machine_mode mode; | |
2240 | register rtx op0, op1, target; | |
2241 | int unsignedp; | |
2242 | { | |
2243 | register rtx result = 0; | |
2244 | enum machine_mode compute_mode; | |
2245 | int log = -1; | |
2c414fba | 2246 | int size; |
44037a66 TG |
2247 | int can_clobber_op0; |
2248 | int mod_insn_no_good = 0; | |
2249 | rtx adjusted_op0 = op0; | |
2250 | optab optab1, optab2; | |
2251 | ||
3d32ffd1 TW |
2252 | /* We shouldn't be called with op1 == const1_rtx, but some of the |
2253 | code below will malfunction if we are, so check here and handle | |
2254 | the special case if so. */ | |
2255 | if (op1 == const1_rtx) | |
2256 | return rem_flag ? const0_rtx : op0; | |
2257 | ||
44037a66 TG |
2258 | /* Don't use the function value register as a target |
2259 | since we have to read it as well as write it, | |
2260 | and function-inlining gets confused by this. */ | |
2261 | if (target && REG_P (target) && REG_FUNCTION_VALUE_P (target)) | |
2262 | target = 0; | |
2263 | ||
2264 | /* Don't clobber an operand while doing a multi-step calculation. */ | |
2265 | if (target) | |
2266 | if ((rem_flag && (reg_mentioned_p (target, op0) | |
2267 | || (GET_CODE (op0) == MEM && GET_CODE (target) == MEM))) | |
2268 | || reg_mentioned_p (target, op1) | |
2269 | || (GET_CODE (op1) == MEM && GET_CODE (target) == MEM)) | |
2270 | target = 0; | |
2271 | ||
2272 | can_clobber_op0 = (GET_CODE (op0) == REG && op0 == target); | |
2273 | ||
2274 | if (GET_CODE (op1) == CONST_INT) | |
2275 | log = exact_log2 (INTVAL (op1)); | |
2276 | ||
2277 | /* If log is >= 0, we are dividing by 2**log, and will do it by shifting, | |
2278 | which is really floor-division. Otherwise we will really do a divide, | |
2279 | and we assume that is trunc-division. | |
2280 | ||
2281 | We must correct the dividend by adding or subtracting something | |
2282 | based on the divisor, in order to do the kind of rounding specified | |
2283 | by CODE. The correction depends on what kind of rounding is actually | |
2284 | available, and that depends on whether we will shift or divide. | |
2285 | ||
2286 | In many of these cases it is possible to perform the operation by a | |
2287 | clever series of logical operations (shifts and/or exclusive-ors). | |
2288 | Although avoiding the jump has the advantage that it extends the basic | |
2289 | block and allows further optimization, the branch-free code is normally | |
2290 | at least one instruction longer in the (most common) case where the | |
2291 | dividend is non-negative. Performance measurements of the two | |
2292 | alternatives show that the branch-free code is slightly faster on the | |
2293 | IBM ROMP but slower on CISC processors (significantly slower on the | |
2294 | VAX). Accordingly, the jump code has been retained. | |
2295 | ||
2296 | On machines where the jump code is slower, the cost of a DIV or MOD | |
2297 | operation can be set small (less than twice that of an addition); in | |
2298 | that case, we pretend that we don't have a power of two and perform | |
2299 | a normal division or modulus operation. */ | |
2300 | ||
2301 | if ((code == TRUNC_MOD_EXPR || code == TRUNC_DIV_EXPR) | |
2302 | && ! unsignedp | |
2303 | && (rem_flag ? smod_pow2_cheap : sdiv_pow2_cheap)) | |
2304 | log = -1; | |
2305 | ||
2306 | /* Get the mode in which to perform this computation. Normally it will | |
2307 | be MODE, but sometimes we can't do the desired operation in MODE. | |
2308 | If so, pick a wider mode in which we can do the operation. Convert | |
2309 | to that mode at the start to avoid repeated conversions. | |
2310 | ||
2311 | First see what operations we need. These depend on the expression | |
2312 | we are evaluating. (We assume that divxx3 insns exist under the | |
2313 | same conditions that modxx3 insns and that these insns don't normally | |
2314 | fail. If these assumptions are not correct, we may generate less | |
2315 | efficient code in some cases.) | |
2316 | ||
2317 | Then see if we find a mode in which we can open-code that operation | |
2318 | (either a division, modulus, or shift). Finally, check for the smallest | |
2319 | mode for which we can do the operation with a library call. */ | |
2320 | ||
2321 | optab1 = (log >= 0 ? (unsignedp ? lshr_optab : ashr_optab) | |
2322 | : (unsignedp ? udiv_optab : sdiv_optab)); | |
2323 | optab2 = (log >= 0 ? optab1 : (unsignedp ? udivmod_optab : sdivmod_optab)); | |
2324 | ||
2325 | for (compute_mode = mode; compute_mode != VOIDmode; | |
2326 | compute_mode = GET_MODE_WIDER_MODE (compute_mode)) | |
2327 | if (optab1->handlers[(int) compute_mode].insn_code != CODE_FOR_nothing | |
2328 | || optab2->handlers[(int) compute_mode].insn_code != CODE_FOR_nothing) | |
2329 | break; | |
2330 | ||
2331 | if (compute_mode == VOIDmode) | |
2332 | for (compute_mode = mode; compute_mode != VOIDmode; | |
2333 | compute_mode = GET_MODE_WIDER_MODE (compute_mode)) | |
2334 | if (optab1->handlers[(int) compute_mode].libfunc | |
2335 | || optab2->handlers[(int) compute_mode].libfunc) | |
2336 | break; | |
2337 | ||
2338 | /* If we still couldn't find a mode, use MODE; we'll probably abort in | |
2339 | expand_binop. */ | |
2340 | if (compute_mode == VOIDmode) | |
2341 | compute_mode = mode; | |
2342 | ||
2c414fba RK |
2343 | size = GET_MODE_BITSIZE (compute_mode); |
2344 | ||
44037a66 TG |
2345 | /* Now convert to the best mode to use. Show we made a copy of OP0 |
2346 | and hence we can clobber it (we cannot use a SUBREG to widen | |
2347 | something. */ | |
2348 | if (compute_mode != mode) | |
2349 | { | |
2350 | adjusted_op0 = op0 = convert_to_mode (compute_mode, op0, unsignedp); | |
2351 | can_clobber_op0 = 1; | |
2352 | op1 = convert_to_mode (compute_mode, op1, unsignedp); | |
2353 | } | |
2354 | ||
c2a47e48 RK |
2355 | /* If we are computing the remainder and one of the operands is a volatile |
2356 | MEM, copy it into a register. */ | |
2357 | ||
2358 | if (rem_flag && GET_CODE (op0) == MEM && MEM_VOLATILE_P (op0)) | |
2359 | adjusted_op0 = op0 = force_reg (compute_mode, op0), can_clobber_op0 = 1; | |
2360 | if (rem_flag && GET_CODE (op1) == MEM && MEM_VOLATILE_P (op1)) | |
2361 | op1 = force_reg (compute_mode, op1); | |
2362 | ||
d8064a5d RS |
2363 | /* If we are computing the remainder, op0 will be needed later to calculate |
2364 | X - Y * (X / Y), therefore cannot be clobbered. */ | |
2365 | if (rem_flag) | |
2366 | can_clobber_op0 = 0; | |
2367 | ||
44037a66 TG |
2368 | if (target == 0 || GET_MODE (target) != compute_mode) |
2369 | target = gen_reg_rtx (compute_mode); | |
2370 | ||
2371 | switch (code) | |
2372 | { | |
2373 | case TRUNC_MOD_EXPR: | |
2374 | case TRUNC_DIV_EXPR: | |
2375 | if (log >= 0 && ! unsignedp) | |
2376 | { | |
3d32ffd1 TW |
2377 | /* Here we need to add OP1-1 if OP0 is negative, 0 otherwise. |
2378 | This can be computed without jumps by arithmetically shifting | |
2379 | OP0 right LOG-1 places and then shifting right logically | |
2380 | SIZE-LOG bits. The resulting value is unconditionally added | |
2381 | to OP0. */ | |
2382 | if (log == 1 || BRANCH_COST >= 3) | |
2383 | { | |
2384 | rtx temp = gen_reg_rtx (compute_mode); | |
f2dd8372 RS |
2385 | if (! can_clobber_op0) |
2386 | /* Copy op0 to a reg, to play safe, | |
2387 | since this is done in the other path. */ | |
2388 | op0 = force_reg (compute_mode, op0); | |
3d32ffd1 TW |
2389 | temp = copy_to_suggested_reg (adjusted_op0, temp, compute_mode); |
2390 | temp = expand_shift (RSHIFT_EXPR, compute_mode, temp, | |
2391 | build_int_2 (log - 1, 0), NULL_RTX, 0); | |
2392 | temp = expand_shift (RSHIFT_EXPR, compute_mode, temp, | |
2c414fba | 2393 | build_int_2 (size - log, 0), |
3d32ffd1 | 2394 | temp, 1); |
f2dd8372 RS |
2395 | /* We supply 0 as the target to make a new pseudo |
2396 | for the value; that helps loop.c optimize the result. */ | |
2397 | adjusted_op0 = expand_binop (compute_mode, add_optab, | |
2398 | adjusted_op0, temp, | |
2399 | 0, 0, OPTAB_LIB_WIDEN); | |
3d32ffd1 TW |
2400 | } |
2401 | else | |
2402 | { | |
2403 | rtx label = gen_label_rtx (); | |
f2dd8372 RS |
2404 | if (! can_clobber_op0) |
2405 | { | |
2406 | adjusted_op0 = copy_to_suggested_reg (adjusted_op0, target, | |
2407 | compute_mode); | |
2408 | /* Copy op0 to a reg, since emit_cmp_insn will call emit_queue | |
2409 | which will screw up mem refs for autoincrements. */ | |
2410 | op0 = force_reg (compute_mode, op0); | |
2411 | } | |
3d32ffd1 TW |
2412 | emit_cmp_insn (adjusted_op0, const0_rtx, GE, |
2413 | NULL_RTX, compute_mode, 0, 0); | |
2414 | emit_jump_insn (gen_bge (label)); | |
2415 | expand_inc (adjusted_op0, plus_constant (op1, -1)); | |
2416 | emit_label (label); | |
2417 | } | |
44037a66 TG |
2418 | mod_insn_no_good = 1; |
2419 | } | |
2420 | break; | |
2421 | ||
2422 | case FLOOR_DIV_EXPR: | |
2423 | case FLOOR_MOD_EXPR: | |
2424 | if (log < 0 && ! unsignedp) | |
2425 | { | |
2426 | rtx label = gen_label_rtx (); | |
2427 | if (! can_clobber_op0) | |
2428 | { | |
36d747f6 RS |
2429 | adjusted_op0 = copy_to_suggested_reg (adjusted_op0, target, |
2430 | compute_mode); | |
44037a66 TG |
2431 | /* Copy op0 to a reg, since emit_cmp_insn will call emit_queue |
2432 | which will screw up mem refs for autoincrements. */ | |
2433 | op0 = force_reg (compute_mode, op0); | |
2434 | } | |
b1ec3c92 CH |
2435 | emit_cmp_insn (adjusted_op0, const0_rtx, GE, |
2436 | NULL_RTX, compute_mode, 0, 0); | |
44037a66 TG |
2437 | emit_jump_insn (gen_bge (label)); |
2438 | expand_dec (adjusted_op0, op1); | |
2439 | expand_inc (adjusted_op0, const1_rtx); | |
2440 | emit_label (label); | |
2441 | mod_insn_no_good = 1; | |
2442 | } | |
2443 | break; | |
2444 | ||
2445 | case CEIL_DIV_EXPR: | |
2446 | case CEIL_MOD_EXPR: | |
2447 | if (! can_clobber_op0) | |
2448 | { | |
36d747f6 RS |
2449 | adjusted_op0 = copy_to_suggested_reg (adjusted_op0, target, |
2450 | compute_mode); | |
44037a66 TG |
2451 | /* Copy op0 to a reg, since emit_cmp_insn will call emit_queue |
2452 | which will screw up mem refs for autoincrements. */ | |
2453 | op0 = force_reg (compute_mode, op0); | |
2454 | } | |
2455 | if (log < 0) | |
2456 | { | |
2457 | rtx label = 0; | |
2458 | if (! unsignedp) | |
2459 | { | |
2460 | label = gen_label_rtx (); | |
b1ec3c92 CH |
2461 | emit_cmp_insn (adjusted_op0, const0_rtx, LE, |
2462 | NULL_RTX, compute_mode, 0, 0); | |
44037a66 TG |
2463 | emit_jump_insn (gen_ble (label)); |
2464 | } | |
2465 | expand_inc (adjusted_op0, op1); | |
2466 | expand_dec (adjusted_op0, const1_rtx); | |
2467 | if (! unsignedp) | |
2468 | emit_label (label); | |
2469 | } | |
2470 | else | |
2471 | { | |
2472 | adjusted_op0 = expand_binop (compute_mode, add_optab, | |
2473 | adjusted_op0, plus_constant (op1, -1), | |
b1ec3c92 | 2474 | NULL_RTX, 0, OPTAB_LIB_WIDEN); |
44037a66 TG |
2475 | } |
2476 | mod_insn_no_good = 1; | |
2477 | break; | |
2478 | ||
2479 | case ROUND_DIV_EXPR: | |
2480 | case ROUND_MOD_EXPR: | |
2481 | if (! can_clobber_op0) | |
2482 | { | |
36d747f6 RS |
2483 | adjusted_op0 = copy_to_suggested_reg (adjusted_op0, target, |
2484 | compute_mode); | |
44037a66 TG |
2485 | /* Copy op0 to a reg, since emit_cmp_insn will call emit_queue |
2486 | which will screw up mem refs for autoincrements. */ | |
2487 | op0 = force_reg (compute_mode, op0); | |
2488 | } | |
2489 | if (log < 0) | |
2490 | { | |
2491 | op1 = expand_shift (RSHIFT_EXPR, compute_mode, op1, | |
b1ec3c92 | 2492 | integer_one_node, NULL_RTX, 0); |
44037a66 TG |
2493 | if (! unsignedp) |
2494 | { | |
3d32ffd1 TW |
2495 | if (BRANCH_COST >= 2) |
2496 | { | |
2497 | /* Negate OP1 if OP0 < 0. Do this by computing a temporary | |
2498 | that has all bits equal to the sign bit and exclusive | |
2499 | or-ing it with OP1. */ | |
2500 | rtx temp = gen_reg_rtx (compute_mode); | |
2501 | temp = copy_to_suggested_reg (adjusted_op0, temp, compute_mode); | |
2502 | temp = expand_shift (RSHIFT_EXPR, compute_mode, temp, | |
2c414fba | 2503 | build_int_2 (size - 1, 0), |
3d32ffd1 TW |
2504 | NULL_RTX, 0); |
2505 | op1 = expand_binop (compute_mode, xor_optab, op1, temp, op1, | |
2506 | unsignedp, OPTAB_LIB_WIDEN); | |
2507 | } | |
2508 | else | |
2509 | { | |
2510 | rtx label = gen_label_rtx (); | |
2511 | emit_cmp_insn (adjusted_op0, const0_rtx, GE, NULL_RTX, | |
2512 | compute_mode, 0, 0); | |
2513 | emit_jump_insn (gen_bge (label)); | |
2514 | expand_unop (compute_mode, neg_optab, op1, op1, 0); | |
2515 | emit_label (label); | |
2516 | } | |
44037a66 TG |
2517 | } |
2518 | expand_inc (adjusted_op0, op1); | |
2519 | } | |
2520 | else | |
2521 | { | |
b1ec3c92 | 2522 | op1 = GEN_INT (((HOST_WIDE_INT) 1 << log) / 2); |
44037a66 TG |
2523 | expand_inc (adjusted_op0, op1); |
2524 | } | |
2525 | mod_insn_no_good = 1; | |
2526 | break; | |
2527 | } | |
2528 | ||
2529 | if (rem_flag && !mod_insn_no_good) | |
2530 | { | |
2531 | /* Try to produce the remainder directly */ | |
2532 | if (log >= 0) | |
2533 | result = expand_binop (compute_mode, and_optab, adjusted_op0, | |
b1ec3c92 | 2534 | GEN_INT (((HOST_WIDE_INT) 1 << log) - 1), |
44037a66 TG |
2535 | target, 1, OPTAB_LIB_WIDEN); |
2536 | else | |
2537 | { | |
2538 | /* See if we can do remainder without a library call. */ | |
2539 | result = sign_expand_binop (mode, umod_optab, smod_optab, | |
2540 | adjusted_op0, op1, target, | |
2541 | unsignedp, OPTAB_WIDEN); | |
2542 | if (result == 0) | |
2543 | { | |
2544 | /* No luck there. Can we do remainder and divide at once | |
2545 | without a library call? */ | |
2546 | result = gen_reg_rtx (compute_mode); | |
2547 | if (! expand_twoval_binop (unsignedp | |
2548 | ? udivmod_optab : sdivmod_optab, | |
2549 | adjusted_op0, op1, | |
b1ec3c92 | 2550 | NULL_RTX, result, unsignedp)) |
44037a66 TG |
2551 | result = 0; |
2552 | } | |
2553 | } | |
2554 | } | |
2555 | ||
2556 | if (result) | |
2557 | return gen_lowpart (mode, result); | |
2558 | ||
2559 | /* Produce the quotient. */ | |
2560 | if (log >= 0) | |
2561 | result = expand_shift (RSHIFT_EXPR, compute_mode, adjusted_op0, | |
2562 | build_int_2 (log, 0), target, unsignedp); | |
2563 | else if (rem_flag && !mod_insn_no_good) | |
2564 | /* If producing quotient in order to subtract for remainder, | |
2565 | and a remainder subroutine would be ok, | |
2566 | don't use a divide subroutine. */ | |
2567 | result = sign_expand_binop (compute_mode, udiv_optab, sdiv_optab, | |
b1ec3c92 CH |
2568 | adjusted_op0, op1, NULL_RTX, unsignedp, |
2569 | OPTAB_WIDEN); | |
44037a66 TG |
2570 | else |
2571 | { | |
2572 | /* Try a quotient insn, but not a library call. */ | |
2573 | result = sign_expand_binop (compute_mode, udiv_optab, sdiv_optab, | |
b1ec3c92 CH |
2574 | adjusted_op0, op1, |
2575 | rem_flag ? NULL_RTX : target, | |
44037a66 TG |
2576 | unsignedp, OPTAB_WIDEN); |
2577 | if (result == 0) | |
2578 | { | |
2579 | /* No luck there. Try a quotient-and-remainder insn, | |
2580 | keeping the quotient alone. */ | |
2581 | result = gen_reg_rtx (mode); | |
2582 | if (! expand_twoval_binop (unsignedp ? udivmod_optab : sdivmod_optab, | |
2583 | adjusted_op0, op1, | |
b1ec3c92 | 2584 | result, NULL_RTX, unsignedp)) |
44037a66 TG |
2585 | result = 0; |
2586 | } | |
2587 | ||
2588 | /* If still no luck, use a library call. */ | |
2589 | if (result == 0) | |
2590 | result = sign_expand_binop (compute_mode, udiv_optab, sdiv_optab, | |
b1ec3c92 CH |
2591 | adjusted_op0, op1, |
2592 | rem_flag ? NULL_RTX : target, | |
44037a66 TG |
2593 | unsignedp, OPTAB_LIB_WIDEN); |
2594 | } | |
2595 | ||
2596 | /* If we really want the remainder, get it by subtraction. */ | |
2597 | if (rem_flag) | |
2598 | { | |
2599 | if (result == 0) | |
2600 | /* No divide instruction either. Use library for remainder. */ | |
2601 | result = sign_expand_binop (compute_mode, umod_optab, smod_optab, | |
2602 | op0, op1, target, | |
2603 | unsignedp, OPTAB_LIB_WIDEN); | |
2604 | else | |
2605 | { | |
2606 | /* We divided. Now finish doing X - Y * (X / Y). */ | |
2607 | result = expand_mult (compute_mode, result, op1, target, unsignedp); | |
2608 | if (! result) abort (); | |
2609 | result = expand_binop (compute_mode, sub_optab, op0, | |
2610 | result, target, unsignedp, OPTAB_LIB_WIDEN); | |
2611 | } | |
2612 | } | |
2613 | ||
2614 | if (result == 0) | |
2615 | abort (); | |
2616 | ||
2617 | return gen_lowpart (mode, result); | |
2618 | } | |
2619 | \f | |
2620 | /* Return a tree node with data type TYPE, describing the value of X. | |
2621 | Usually this is an RTL_EXPR, if there is no obvious better choice. | |
2622 | X may be an expression, however we only support those expressions | |
2623 | generated by loop.c. */ | |
2624 | ||
2625 | tree | |
2626 | make_tree (type, x) | |
2627 | tree type; | |
2628 | rtx x; | |
2629 | { | |
2630 | tree t; | |
2631 | ||
2632 | switch (GET_CODE (x)) | |
2633 | { | |
2634 | case CONST_INT: | |
2635 | t = build_int_2 (INTVAL (x), | |
2636 | ! TREE_UNSIGNED (type) && INTVAL (x) >= 0 ? 0 : -1); | |
2637 | TREE_TYPE (t) = type; | |
2638 | return t; | |
2639 | ||
2640 | case CONST_DOUBLE: | |
2641 | if (GET_MODE (x) == VOIDmode) | |
2642 | { | |
2643 | t = build_int_2 (CONST_DOUBLE_LOW (x), CONST_DOUBLE_HIGH (x)); | |
2644 | TREE_TYPE (t) = type; | |
2645 | } | |
2646 | else | |
2647 | { | |
2648 | REAL_VALUE_TYPE d; | |
2649 | ||
2650 | REAL_VALUE_FROM_CONST_DOUBLE (d, x); | |
2651 | t = build_real (type, d); | |
2652 | } | |
2653 | ||
2654 | return t; | |
2655 | ||
2656 | case PLUS: | |
2657 | return fold (build (PLUS_EXPR, type, make_tree (type, XEXP (x, 0)), | |
2658 | make_tree (type, XEXP (x, 1)))); | |
2659 | ||
2660 | case MINUS: | |
2661 | return fold (build (MINUS_EXPR, type, make_tree (type, XEXP (x, 0)), | |
2662 | make_tree (type, XEXP (x, 1)))); | |
2663 | ||
2664 | case NEG: | |
2665 | return fold (build1 (NEGATE_EXPR, type, make_tree (type, XEXP (x, 0)))); | |
2666 | ||
2667 | case MULT: | |
2668 | return fold (build (MULT_EXPR, type, make_tree (type, XEXP (x, 0)), | |
2669 | make_tree (type, XEXP (x, 1)))); | |
2670 | ||
2671 | case ASHIFT: | |
2672 | return fold (build (LSHIFT_EXPR, type, make_tree (type, XEXP (x, 0)), | |
2673 | make_tree (type, XEXP (x, 1)))); | |
2674 | ||
2675 | case LSHIFTRT: | |
2676 | return fold (convert (type, | |
2677 | build (RSHIFT_EXPR, unsigned_type (type), | |
2678 | make_tree (unsigned_type (type), | |
2679 | XEXP (x, 0)), | |
2680 | make_tree (type, XEXP (x, 1))))); | |
2681 | ||
2682 | case ASHIFTRT: | |
2683 | return fold (convert (type, | |
2684 | build (RSHIFT_EXPR, signed_type (type), | |
2685 | make_tree (signed_type (type), XEXP (x, 0)), | |
2686 | make_tree (type, XEXP (x, 1))))); | |
2687 | ||
2688 | case DIV: | |
2689 | if (TREE_CODE (type) != REAL_TYPE) | |
2690 | t = signed_type (type); | |
2691 | else | |
2692 | t = type; | |
2693 | ||
2694 | return fold (convert (type, | |
2695 | build (TRUNC_DIV_EXPR, t, | |
2696 | make_tree (t, XEXP (x, 0)), | |
2697 | make_tree (t, XEXP (x, 1))))); | |
2698 | case UDIV: | |
2699 | t = unsigned_type (type); | |
2700 | return fold (convert (type, | |
2701 | build (TRUNC_DIV_EXPR, t, | |
2702 | make_tree (t, XEXP (x, 0)), | |
2703 | make_tree (t, XEXP (x, 1))))); | |
2704 | default: | |
2705 | t = make_node (RTL_EXPR); | |
2706 | TREE_TYPE (t) = type; | |
2707 | RTL_EXPR_RTL (t) = x; | |
2708 | /* There are no insns to be output | |
2709 | when this rtl_expr is used. */ | |
2710 | RTL_EXPR_SEQUENCE (t) = 0; | |
2711 | return t; | |
2712 | } | |
2713 | } | |
2714 | ||
2715 | /* Return an rtx representing the value of X * MULT + ADD. | |
2716 | TARGET is a suggestion for where to store the result (an rtx). | |
2717 | MODE is the machine mode for the computation. | |
2718 | X and MULT must have mode MODE. ADD may have a different mode. | |
2719 | So can X (defaults to same as MODE). | |
2720 | UNSIGNEDP is non-zero to do unsigned multiplication. | |
2721 | This may emit insns. */ | |
2722 | ||
2723 | rtx | |
2724 | expand_mult_add (x, target, mult, add, mode, unsignedp) | |
2725 | rtx x, target, mult, add; | |
2726 | enum machine_mode mode; | |
2727 | int unsignedp; | |
2728 | { | |
2729 | tree type = type_for_mode (mode, unsignedp); | |
2730 | tree add_type = (GET_MODE (add) == VOIDmode | |
36d747f6 | 2731 | ? type : type_for_mode (GET_MODE (add), unsignedp)); |
44037a66 TG |
2732 | tree result = fold (build (PLUS_EXPR, type, |
2733 | fold (build (MULT_EXPR, type, | |
2734 | make_tree (type, x), | |
2735 | make_tree (type, mult))), | |
2736 | make_tree (add_type, add))); | |
2737 | ||
2738 | return expand_expr (result, target, VOIDmode, 0); | |
2739 | } | |
2740 | \f | |
2741 | /* Compute the logical-and of OP0 and OP1, storing it in TARGET | |
2742 | and returning TARGET. | |
2743 | ||
2744 | If TARGET is 0, a pseudo-register or constant is returned. */ | |
2745 | ||
2746 | rtx | |
2747 | expand_and (op0, op1, target) | |
2748 | rtx op0, op1, target; | |
2749 | { | |
2750 | enum machine_mode mode = VOIDmode; | |
2751 | rtx tem; | |
2752 | ||
2753 | if (GET_MODE (op0) != VOIDmode) | |
2754 | mode = GET_MODE (op0); | |
2755 | else if (GET_MODE (op1) != VOIDmode) | |
2756 | mode = GET_MODE (op1); | |
2757 | ||
2758 | if (mode != VOIDmode) | |
2759 | tem = expand_binop (mode, and_optab, op0, op1, target, 0, OPTAB_LIB_WIDEN); | |
2760 | else if (GET_CODE (op0) == CONST_INT && GET_CODE (op1) == CONST_INT) | |
b1ec3c92 | 2761 | tem = GEN_INT (INTVAL (op0) & INTVAL (op1)); |
44037a66 TG |
2762 | else |
2763 | abort (); | |
2764 | ||
2765 | if (target == 0) | |
2766 | target = tem; | |
2767 | else if (tem != target) | |
2768 | emit_move_insn (target, tem); | |
2769 | return target; | |
2770 | } | |
2771 | \f | |
2772 | /* Emit a store-flags instruction for comparison CODE on OP0 and OP1 | |
2773 | and storing in TARGET. Normally return TARGET. | |
2774 | Return 0 if that cannot be done. | |
2775 | ||
2776 | MODE is the mode to use for OP0 and OP1 should they be CONST_INTs. If | |
2777 | it is VOIDmode, they cannot both be CONST_INT. | |
2778 | ||
2779 | UNSIGNEDP is for the case where we have to widen the operands | |
2780 | to perform the operation. It says to use zero-extension. | |
2781 | ||
2782 | NORMALIZEP is 1 if we should convert the result to be either zero | |
2783 | or one one. Normalize is -1 if we should convert the result to be | |
2784 | either zero or -1. If NORMALIZEP is zero, the result will be left | |
2785 | "raw" out of the scc insn. */ | |
2786 | ||
2787 | rtx | |
2788 | emit_store_flag (target, code, op0, op1, mode, unsignedp, normalizep) | |
2789 | rtx target; | |
2790 | enum rtx_code code; | |
2791 | rtx op0, op1; | |
2792 | enum machine_mode mode; | |
2793 | int unsignedp; | |
2794 | int normalizep; | |
2795 | { | |
2796 | rtx subtarget; | |
2797 | enum insn_code icode; | |
2798 | enum machine_mode compare_mode; | |
2799 | enum machine_mode target_mode = GET_MODE (target); | |
2800 | rtx tem; | |
2801 | rtx last = 0; | |
2802 | rtx pattern, comparison; | |
2803 | ||
2804 | if (mode == VOIDmode) | |
2805 | mode = GET_MODE (op0); | |
2806 | ||
c2615a67 RK |
2807 | /* If one operand is constant, make it the second one. Only do this |
2808 | if the other operand is not constant as well. */ | |
2809 | ||
2810 | if ((CONSTANT_P (op0) && ! CONSTANT_P (op1)) | |
2811 | || (GET_CODE (op0) == CONST_INT && GET_CODE (op1) != CONST_INT)) | |
2812 | { | |
2813 | tem = op0; | |
2814 | op0 = op1; | |
2815 | op1 = tem; | |
2816 | code = swap_condition (code); | |
2817 | } | |
2818 | ||
44037a66 TG |
2819 | /* For some comparisons with 1 and -1, we can convert this to |
2820 | comparisons with zero. This will often produce more opportunities for | |
2821 | store-flag insns. */ | |
2822 | ||
2823 | switch (code) | |
2824 | { | |
2825 | case LT: | |
2826 | if (op1 == const1_rtx) | |
2827 | op1 = const0_rtx, code = LE; | |
2828 | break; | |
2829 | case LE: | |
2830 | if (op1 == constm1_rtx) | |
2831 | op1 = const0_rtx, code = LT; | |
2832 | break; | |
2833 | case GE: | |
2834 | if (op1 == const1_rtx) | |
2835 | op1 = const0_rtx, code = GT; | |
2836 | break; | |
2837 | case GT: | |
2838 | if (op1 == constm1_rtx) | |
2839 | op1 = const0_rtx, code = GE; | |
2840 | break; | |
2841 | case GEU: | |
2842 | if (op1 == const1_rtx) | |
2843 | op1 = const0_rtx, code = NE; | |
2844 | break; | |
2845 | case LTU: | |
2846 | if (op1 == const1_rtx) | |
2847 | op1 = const0_rtx, code = EQ; | |
2848 | break; | |
2849 | } | |
2850 | ||
2851 | /* From now on, we won't change CODE, so set ICODE now. */ | |
2852 | icode = setcc_gen_code[(int) code]; | |
2853 | ||
2854 | /* If this is A < 0 or A >= 0, we can do this by taking the ones | |
2855 | complement of A (for GE) and shifting the sign bit to the low bit. */ | |
2856 | if (op1 == const0_rtx && (code == LT || code == GE) | |
2857 | && GET_MODE_CLASS (mode) == MODE_INT | |
2858 | && (normalizep || STORE_FLAG_VALUE == 1 | |
b1ec3c92 CH |
2859 | || (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT |
2860 | && (STORE_FLAG_VALUE | |
2861 | == (HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))))) | |
44037a66 | 2862 | { |
8deb7047 | 2863 | subtarget = target; |
44037a66 TG |
2864 | |
2865 | /* If the result is to be wider than OP0, it is best to convert it | |
2866 | first. If it is to be narrower, it is *incorrect* to convert it | |
2867 | first. */ | |
2868 | if (GET_MODE_SIZE (target_mode) > GET_MODE_SIZE (mode)) | |
2869 | { | |
b3d4e1b2 | 2870 | op0 = protect_from_queue (op0, 0); |
44037a66 TG |
2871 | op0 = convert_to_mode (target_mode, op0, 0); |
2872 | mode = target_mode; | |
2873 | } | |
2874 | ||
2875 | if (target_mode != mode) | |
2876 | subtarget = 0; | |
2877 | ||
2878 | if (code == GE) | |
2879 | op0 = expand_unop (mode, one_cmpl_optab, op0, subtarget, 0); | |
2880 | ||
2881 | if (normalizep || STORE_FLAG_VALUE == 1) | |
2882 | /* If we are supposed to produce a 0/1 value, we want to do | |
2883 | a logical shift from the sign bit to the low-order bit; for | |
2884 | a -1/0 value, we do an arithmetic shift. */ | |
2885 | op0 = expand_shift (RSHIFT_EXPR, mode, op0, | |
2886 | size_int (GET_MODE_BITSIZE (mode) - 1), | |
2887 | subtarget, normalizep != -1); | |
2888 | ||
2889 | if (mode != target_mode) | |
2890 | op0 = convert_to_mode (target_mode, op0, 0); | |
2891 | ||
2892 | return op0; | |
2893 | } | |
2894 | ||
2895 | if (icode != CODE_FOR_nothing) | |
2896 | { | |
2897 | /* We think we may be able to do this with a scc insn. Emit the | |
2898 | comparison and then the scc insn. | |
2899 | ||
2900 | compare_from_rtx may call emit_queue, which would be deleted below | |
2901 | if the scc insn fails. So call it ourselves before setting LAST. */ | |
2902 | ||
2903 | emit_queue (); | |
2904 | last = get_last_insn (); | |
2905 | ||
b1ec3c92 CH |
2906 | comparison |
2907 | = compare_from_rtx (op0, op1, code, unsignedp, mode, NULL_RTX, 0); | |
44037a66 TG |
2908 | if (GET_CODE (comparison) == CONST_INT) |
2909 | return (comparison == const0_rtx ? const0_rtx | |
2910 | : normalizep == 1 ? const1_rtx | |
2911 | : normalizep == -1 ? constm1_rtx | |
2912 | : const_true_rtx); | |
2913 | ||
c2615a67 RK |
2914 | /* If the code of COMPARISON doesn't match CODE, something is |
2915 | wrong; we can no longer be sure that we have the operation. | |
2916 | We could handle this case, but it should not happen. */ | |
2917 | ||
2918 | if (GET_CODE (comparison) != code) | |
2919 | abort (); | |
8deb7047 | 2920 | |
44037a66 TG |
2921 | /* Get a reference to the target in the proper mode for this insn. */ |
2922 | compare_mode = insn_operand_mode[(int) icode][0]; | |
2923 | subtarget = target; | |
2924 | if (preserve_subexpressions_p () | |
2925 | || ! (*insn_operand_predicate[(int) icode][0]) (subtarget, compare_mode)) | |
2926 | subtarget = gen_reg_rtx (compare_mode); | |
2927 | ||
2928 | pattern = GEN_FCN (icode) (subtarget); | |
2929 | if (pattern) | |
2930 | { | |
2931 | emit_insn (pattern); | |
2932 | ||
2933 | /* If we are converting to a wider mode, first convert to | |
2934 | TARGET_MODE, then normalize. This produces better combining | |
2935 | opportunities on machines that have a SIGN_EXTRACT when we are | |
2936 | testing a single bit. This mostly benefits the 68k. | |
2937 | ||
2938 | If STORE_FLAG_VALUE does not have the sign bit set when | |
2939 | interpreted in COMPARE_MODE, we can do this conversion as | |
2940 | unsigned, which is usually more efficient. */ | |
2941 | if (GET_MODE_SIZE (target_mode) > GET_MODE_SIZE (compare_mode)) | |
2942 | { | |
2943 | convert_move (target, subtarget, | |
2944 | (GET_MODE_BITSIZE (compare_mode) | |
b1ec3c92 | 2945 | <= HOST_BITS_PER_WIDE_INT) |
44037a66 | 2946 | && 0 == (STORE_FLAG_VALUE |
b1ec3c92 CH |
2947 | & ((HOST_WIDE_INT) 1 |
2948 | << (GET_MODE_BITSIZE (compare_mode) -1)))); | |
44037a66 TG |
2949 | op0 = target; |
2950 | compare_mode = target_mode; | |
2951 | } | |
2952 | else | |
2953 | op0 = subtarget; | |
2954 | ||
4b980e20 RK |
2955 | /* If we want to keep subexpressions around, don't reuse our |
2956 | last target. */ | |
2957 | ||
2958 | if (preserve_subexpressions_p ()) | |
2959 | subtarget = 0; | |
2960 | ||
44037a66 TG |
2961 | /* Now normalize to the proper value in COMPARE_MODE. Sometimes |
2962 | we don't have to do anything. */ | |
2963 | if (normalizep == 0 || normalizep == STORE_FLAG_VALUE) | |
2964 | ; | |
2965 | else if (normalizep == - STORE_FLAG_VALUE) | |
2966 | op0 = expand_unop (compare_mode, neg_optab, op0, subtarget, 0); | |
2967 | ||
2968 | /* We don't want to use STORE_FLAG_VALUE < 0 below since this | |
2969 | makes it hard to use a value of just the sign bit due to | |
2970 | ANSI integer constant typing rules. */ | |
b1ec3c92 | 2971 | else if (GET_MODE_BITSIZE (compare_mode) <= HOST_BITS_PER_WIDE_INT |
44037a66 | 2972 | && (STORE_FLAG_VALUE |
b1ec3c92 CH |
2973 | & ((HOST_WIDE_INT) 1 |
2974 | << (GET_MODE_BITSIZE (compare_mode) - 1)))) | |
44037a66 TG |
2975 | op0 = expand_shift (RSHIFT_EXPR, compare_mode, op0, |
2976 | size_int (GET_MODE_BITSIZE (compare_mode) - 1), | |
2977 | subtarget, normalizep == 1); | |
2978 | else if (STORE_FLAG_VALUE & 1) | |
2979 | { | |
2980 | op0 = expand_and (op0, const1_rtx, subtarget); | |
2981 | if (normalizep == -1) | |
2982 | op0 = expand_unop (compare_mode, neg_optab, op0, op0, 0); | |
2983 | } | |
2984 | else | |
2985 | abort (); | |
2986 | ||
2987 | /* If we were converting to a smaller mode, do the | |
2988 | conversion now. */ | |
2989 | if (target_mode != compare_mode) | |
2990 | { | |
522ae84c | 2991 | convert_move (target, op0, 0); |
44037a66 TG |
2992 | return target; |
2993 | } | |
2994 | else | |
2995 | return op0; | |
2996 | } | |
2997 | } | |
2998 | ||
2999 | if (last) | |
3000 | delete_insns_since (last); | |
3001 | ||
3002 | subtarget = target_mode == mode ? target : 0; | |
3003 | ||
3004 | /* If we reached here, we can't do this with a scc insn. However, there | |
3005 | are some comparisons that can be done directly. For example, if | |
3006 | this is an equality comparison of integers, we can try to exclusive-or | |
3007 | (or subtract) the two operands and use a recursive call to try the | |
3008 | comparison with zero. Don't do any of these cases if branches are | |
3009 | very cheap. */ | |
3010 | ||
c8c1bde3 | 3011 | if (BRANCH_COST > 0 |
44037a66 TG |
3012 | && GET_MODE_CLASS (mode) == MODE_INT && (code == EQ || code == NE) |
3013 | && op1 != const0_rtx) | |
3014 | { | |
3015 | tem = expand_binop (mode, xor_optab, op0, op1, subtarget, 1, | |
3016 | OPTAB_WIDEN); | |
3017 | ||
3018 | if (tem == 0) | |
3019 | tem = expand_binop (mode, sub_optab, op0, op1, subtarget, 1, | |
3020 | OPTAB_WIDEN); | |
3021 | if (tem != 0) | |
3022 | tem = emit_store_flag (target, code, tem, const0_rtx, | |
3023 | mode, unsignedp, normalizep); | |
3024 | if (tem == 0) | |
3025 | delete_insns_since (last); | |
3026 | return tem; | |
3027 | } | |
3028 | ||
3029 | /* Some other cases we can do are EQ, NE, LE, and GT comparisons with | |
3030 | the constant zero. Reject all other comparisons at this point. Only | |
3031 | do LE and GT if branches are expensive since they are expensive on | |
3032 | 2-operand machines. */ | |
3033 | ||
3034 | if (BRANCH_COST == 0 | |
3035 | || GET_MODE_CLASS (mode) != MODE_INT || op1 != const0_rtx | |
3036 | || (code != EQ && code != NE | |
3037 | && (BRANCH_COST <= 1 || (code != LE && code != GT)))) | |
3038 | return 0; | |
3039 | ||
3040 | /* See what we need to return. We can only return a 1, -1, or the | |
3041 | sign bit. */ | |
3042 | ||
3043 | if (normalizep == 0) | |
3044 | { | |
3045 | if (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1) | |
3046 | normalizep = STORE_FLAG_VALUE; | |
3047 | ||
b1ec3c92 CH |
3048 | else if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT |
3049 | && (STORE_FLAG_VALUE | |
3050 | == (HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))) | |
44037a66 TG |
3051 | ; |
3052 | else | |
3053 | return 0; | |
3054 | } | |
3055 | ||
3056 | /* Try to put the result of the comparison in the sign bit. Assume we can't | |
3057 | do the necessary operation below. */ | |
3058 | ||
3059 | tem = 0; | |
3060 | ||
3061 | /* To see if A <= 0, compute (A | (A - 1)). A <= 0 iff that result has | |
3062 | the sign bit set. */ | |
3063 | ||
3064 | if (code == LE) | |
3065 | { | |
3066 | /* This is destructive, so SUBTARGET can't be OP0. */ | |
3067 | if (rtx_equal_p (subtarget, op0)) | |
3068 | subtarget = 0; | |
3069 | ||
3070 | tem = expand_binop (mode, sub_optab, op0, const1_rtx, subtarget, 0, | |
3071 | OPTAB_WIDEN); | |
3072 | if (tem) | |
3073 | tem = expand_binop (mode, ior_optab, op0, tem, subtarget, 0, | |
3074 | OPTAB_WIDEN); | |
3075 | } | |
3076 | ||
3077 | /* To see if A > 0, compute (((signed) A) << BITS) - A, where BITS is the | |
3078 | number of bits in the mode of OP0, minus one. */ | |
3079 | ||
3080 | if (code == GT) | |
3081 | { | |
3082 | if (rtx_equal_p (subtarget, op0)) | |
3083 | subtarget = 0; | |
3084 | ||
3085 | tem = expand_shift (RSHIFT_EXPR, mode, op0, | |
3086 | size_int (GET_MODE_BITSIZE (mode) - 1), | |
3087 | subtarget, 0); | |
3088 | tem = expand_binop (mode, sub_optab, tem, op0, subtarget, 0, | |
3089 | OPTAB_WIDEN); | |
3090 | } | |
3091 | ||
3092 | if (code == EQ || code == NE) | |
3093 | { | |
3094 | /* For EQ or NE, one way to do the comparison is to apply an operation | |
3095 | that converts the operand into a positive number if it is non-zero | |
3096 | or zero if it was originally zero. Then, for EQ, we subtract 1 and | |
3097 | for NE we negate. This puts the result in the sign bit. Then we | |
3098 | normalize with a shift, if needed. | |
3099 | ||
3100 | Two operations that can do the above actions are ABS and FFS, so try | |
3101 | them. If that doesn't work, and MODE is smaller than a full word, | |
36d747f6 | 3102 | we can use zero-extension to the wider mode (an unsigned conversion) |
44037a66 TG |
3103 | as the operation. */ |
3104 | ||
3105 | if (abs_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing) | |
3106 | tem = expand_unop (mode, abs_optab, op0, subtarget, 1); | |
3107 | else if (ffs_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing) | |
3108 | tem = expand_unop (mode, ffs_optab, op0, subtarget, 1); | |
3109 | else if (GET_MODE_SIZE (mode) < UNITS_PER_WORD) | |
3110 | { | |
3111 | mode = word_mode; | |
b3d4e1b2 | 3112 | op0 = protect_from_queue (op0, 0); |
44037a66 TG |
3113 | tem = convert_to_mode (mode, op0, 1); |
3114 | } | |
3115 | ||
3116 | if (tem != 0) | |
3117 | { | |
3118 | if (code == EQ) | |
3119 | tem = expand_binop (mode, sub_optab, tem, const1_rtx, subtarget, | |
3120 | 0, OPTAB_WIDEN); | |
3121 | else | |
3122 | tem = expand_unop (mode, neg_optab, tem, subtarget, 0); | |
3123 | } | |
3124 | ||
3125 | /* If we couldn't do it that way, for NE we can "or" the two's complement | |
3126 | of the value with itself. For EQ, we take the one's complement of | |
3127 | that "or", which is an extra insn, so we only handle EQ if branches | |
3128 | are expensive. */ | |
3129 | ||
3130 | if (tem == 0 && (code == NE || BRANCH_COST > 1)) | |
3131 | { | |
36d747f6 RS |
3132 | if (rtx_equal_p (subtarget, op0)) |
3133 | subtarget = 0; | |
3134 | ||
44037a66 TG |
3135 | tem = expand_unop (mode, neg_optab, op0, subtarget, 0); |
3136 | tem = expand_binop (mode, ior_optab, tem, op0, subtarget, 0, | |
3137 | OPTAB_WIDEN); | |
3138 | ||
3139 | if (tem && code == EQ) | |
3140 | tem = expand_unop (mode, one_cmpl_optab, tem, subtarget, 0); | |
3141 | } | |
3142 | } | |
3143 | ||
3144 | if (tem && normalizep) | |
3145 | tem = expand_shift (RSHIFT_EXPR, mode, tem, | |
3146 | size_int (GET_MODE_BITSIZE (mode) - 1), | |
3147 | tem, normalizep == 1); | |
3148 | ||
3149 | if (tem && GET_MODE (tem) != target_mode) | |
3150 | { | |
3151 | convert_move (target, tem, 0); | |
3152 | tem = target; | |
3153 | } | |
3154 | ||
3155 | if (tem == 0) | |
3156 | delete_insns_since (last); | |
3157 | ||
3158 | return tem; | |
3159 | } | |
3160 | emit_jump_insn ((*bcc_gen_fctn[(int) code]) (label)); | |
3161 | emit_move_insn (target, const1_rtx); | |
3162 | emit_label (label); | |
3163 | ||
3164 | return target; | |
3165 | } |