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44037a66 TG |
1 | /* Medium-level subroutines: convert bit-field store and extract |
2 | and shifts, multiplies and divides to rtl instructions. | |
c7554b28 | 3 | Copyright (C) 1987, 88, 89, 92-6, 1997 Free Software Foundation, Inc. |
44037a66 TG |
4 | |
5 | This file is part of GNU CC. | |
6 | ||
7 | GNU CC is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2, or (at your option) | |
10 | any later version. | |
11 | ||
12 | GNU CC is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GNU CC; see the file COPYING. If not, write to | |
940d9d63 RK |
19 | the Free Software Foundation, 59 Temple Place - Suite 330, |
20 | Boston, MA 02111-1307, USA. */ | |
44037a66 TG |
21 | |
22 | ||
23 | #include "config.h" | |
670ee920 | 24 | #include "system.h" |
44037a66 TG |
25 | #include "rtl.h" |
26 | #include "tree.h" | |
27 | #include "flags.h" | |
28 | #include "insn-flags.h" | |
29 | #include "insn-codes.h" | |
30 | #include "insn-config.h" | |
31 | #include "expr.h" | |
32 | #include "real.h" | |
33 | #include "recog.h" | |
34 | ||
82c68a78 RK |
35 | static void store_fixed_bit_field PROTO((rtx, int, int, int, rtx, int)); |
36 | static void store_split_bit_field PROTO((rtx, int, int, rtx, int)); | |
37 | static rtx extract_fixed_bit_field PROTO((enum machine_mode, rtx, int, | |
38 | int, int, rtx, int, int)); | |
39 | static rtx mask_rtx PROTO((enum machine_mode, int, | |
40 | int, int)); | |
41 | static rtx lshift_value PROTO((enum machine_mode, rtx, | |
42 | int, int)); | |
43 | static rtx extract_split_bit_field PROTO((rtx, int, int, int, int)); | |
44037a66 TG |
44 | |
45 | #define CEIL(x,y) (((x) + (y) - 1) / (y)) | |
46 | ||
44037a66 TG |
47 | /* Non-zero means divides or modulus operations are relatively cheap for |
48 | powers of two, so don't use branches; emit the operation instead. | |
49 | Usually, this will mean that the MD file will emit non-branch | |
50 | sequences. */ | |
51 | ||
52 | static int sdiv_pow2_cheap, smod_pow2_cheap; | |
53 | ||
c7e33f89 RS |
54 | #ifndef SLOW_UNALIGNED_ACCESS |
55 | #define SLOW_UNALIGNED_ACCESS STRICT_ALIGNMENT | |
56 | #endif | |
57 | ||
e49a094d RS |
58 | /* For compilers that support multiple targets with different word sizes, |
59 | MAX_BITS_PER_WORD contains the biggest value of BITS_PER_WORD. An example | |
60 | is the H8/300(H) compiler. */ | |
61 | ||
62 | #ifndef MAX_BITS_PER_WORD | |
63 | #define MAX_BITS_PER_WORD BITS_PER_WORD | |
64 | #endif | |
65 | ||
71af73bb TG |
66 | /* Cost of various pieces of RTL. Note that some of these are indexed by shift count, |
67 | and some by mode. */ | |
819126a6 | 68 | static int add_cost, negate_cost, zero_cost; |
e49a094d RS |
69 | static int shift_cost[MAX_BITS_PER_WORD]; |
70 | static int shiftadd_cost[MAX_BITS_PER_WORD]; | |
71 | static int shiftsub_cost[MAX_BITS_PER_WORD]; | |
71af73bb TG |
72 | static int mul_cost[NUM_MACHINE_MODES]; |
73 | static int div_cost[NUM_MACHINE_MODES]; | |
74 | static int mul_widen_cost[NUM_MACHINE_MODES]; | |
75 | static int mul_highpart_cost[NUM_MACHINE_MODES]; | |
44037a66 | 76 | |
44037a66 TG |
77 | void |
78 | init_expmed () | |
79 | { | |
b385aeda | 80 | char *free_point; |
44037a66 TG |
81 | /* This is "some random pseudo register" for purposes of calling recog |
82 | to see what insns exist. */ | |
38a448ca | 83 | rtx reg = gen_rtx_REG (word_mode, 10000); |
b385aeda | 84 | rtx shift_insn, shiftadd_insn, shiftsub_insn; |
b1ec3c92 | 85 | int dummy; |
7963ac37 | 86 | int m; |
71af73bb | 87 | enum machine_mode mode, wider_mode; |
44037a66 | 88 | |
b385aeda RK |
89 | start_sequence (); |
90 | ||
91 | /* Since we are on the permanent obstack, we must be sure we save this | |
92 | spot AFTER we call start_sequence, since it will reuse the rtl it | |
93 | makes. */ | |
94 | ||
95 | free_point = (char *) oballoc (0); | |
96 | ||
172a1cb0 | 97 | zero_cost = rtx_cost (const0_rtx, 0); |
38a448ca RH |
98 | add_cost = rtx_cost (gen_rtx_PLUS (word_mode, reg, reg), SET); |
99 | ||
100 | shift_insn = emit_insn (gen_rtx_SET (VOIDmode, reg, | |
101 | gen_rtx_ASHIFT (word_mode, reg, | |
102 | const0_rtx))); | |
103 | ||
104 | shiftadd_insn | |
105 | = emit_insn (gen_rtx_SET (VOIDmode, reg, | |
106 | gen_rtx_PLUS (word_mode, | |
107 | gen_rtx_MULT (word_mode, | |
108 | reg, const0_rtx), | |
109 | reg))); | |
110 | ||
111 | shiftsub_insn | |
112 | = emit_insn (gen_rtx_SET (VOIDmode, reg, | |
113 | gen_rtx_MINUS (word_mode, | |
114 | gen_rtx_MULT (word_mode, | |
115 | reg, const0_rtx), | |
116 | reg))); | |
7963ac37 RK |
117 | |
118 | init_recog (); | |
b385aeda RK |
119 | |
120 | shift_cost[0] = 0; | |
121 | shiftadd_cost[0] = shiftsub_cost[0] = add_cost; | |
122 | ||
7963ac37 RK |
123 | for (m = 1; m < BITS_PER_WORD; m++) |
124 | { | |
125 | shift_cost[m] = shiftadd_cost[m] = shiftsub_cost[m] = 32000; | |
b385aeda RK |
126 | |
127 | XEXP (SET_SRC (PATTERN (shift_insn)), 1) = GEN_INT (m); | |
128 | if (recog (PATTERN (shift_insn), shift_insn, &dummy) >= 0) | |
129 | shift_cost[m] = rtx_cost (SET_SRC (PATTERN (shift_insn)), SET); | |
130 | ||
131 | XEXP (XEXP (SET_SRC (PATTERN (shiftadd_insn)), 0), 1) | |
132 | = GEN_INT ((HOST_WIDE_INT) 1 << m); | |
133 | if (recog (PATTERN (shiftadd_insn), shiftadd_insn, &dummy) >= 0) | |
dac57de0 | 134 | shiftadd_cost[m] = rtx_cost (SET_SRC (PATTERN (shiftadd_insn)), SET); |
b385aeda RK |
135 | |
136 | XEXP (XEXP (SET_SRC (PATTERN (shiftsub_insn)), 0), 1) | |
137 | = GEN_INT ((HOST_WIDE_INT) 1 << m); | |
138 | if (recog (PATTERN (shiftsub_insn), shiftsub_insn, &dummy) >= 0) | |
dac57de0 | 139 | shiftsub_cost[m] = rtx_cost (SET_SRC (PATTERN (shiftsub_insn)), SET); |
7963ac37 RK |
140 | } |
141 | ||
38a448ca | 142 | negate_cost = rtx_cost (gen_rtx_NEG (word_mode, reg), SET); |
44037a66 | 143 | |
44037a66 | 144 | sdiv_pow2_cheap |
38a448ca | 145 | = (rtx_cost (gen_rtx_DIV (word_mode, reg, GEN_INT (32)), SET) |
b385aeda | 146 | <= 2 * add_cost); |
44037a66 | 147 | smod_pow2_cheap |
38a448ca | 148 | = (rtx_cost (gen_rtx_MOD (word_mode, reg, GEN_INT (32)), SET) |
b385aeda | 149 | <= 2 * add_cost); |
44037a66 | 150 | |
71af73bb TG |
151 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT); |
152 | mode != VOIDmode; | |
153 | mode = GET_MODE_WIDER_MODE (mode)) | |
154 | { | |
38a448ca RH |
155 | reg = gen_rtx_REG (mode, 10000); |
156 | div_cost[(int) mode] = rtx_cost (gen_rtx_UDIV (mode, reg, reg), SET); | |
157 | mul_cost[(int) mode] = rtx_cost (gen_rtx_MULT (mode, reg, reg), SET); | |
71af73bb TG |
158 | wider_mode = GET_MODE_WIDER_MODE (mode); |
159 | if (wider_mode != VOIDmode) | |
160 | { | |
161 | mul_widen_cost[(int) wider_mode] | |
38a448ca RH |
162 | = rtx_cost (gen_rtx_MULT (wider_mode, |
163 | gen_rtx_ZERO_EXTEND (wider_mode, reg), | |
164 | gen_rtx_ZERO_EXTEND (wider_mode, reg)), | |
71af73bb TG |
165 | SET); |
166 | mul_highpart_cost[(int) mode] | |
38a448ca RH |
167 | = rtx_cost (gen_rtx_TRUNCATE |
168 | (mode, | |
169 | gen_rtx_LSHIFTRT | |
170 | (wider_mode, | |
171 | gen_rtx_MULT (wider_mode, | |
172 | gen_rtx_ZERO_EXTEND (wider_mode, reg), | |
173 | gen_rtx_ZERO_EXTEND (wider_mode, reg)), | |
174 | GEN_INT (GET_MODE_BITSIZE (mode)))), | |
71af73bb TG |
175 | SET); |
176 | } | |
177 | } | |
178 | ||
44037a66 | 179 | /* Free the objects we just allocated. */ |
b385aeda | 180 | end_sequence (); |
44037a66 TG |
181 | obfree (free_point); |
182 | } | |
183 | ||
184 | /* Return an rtx representing minus the value of X. | |
185 | MODE is the intended mode of the result, | |
186 | useful if X is a CONST_INT. */ | |
187 | ||
188 | rtx | |
189 | negate_rtx (mode, x) | |
190 | enum machine_mode mode; | |
191 | rtx x; | |
192 | { | |
a39a7484 RK |
193 | rtx result = simplify_unary_operation (NEG, mode, x, mode); |
194 | ||
fdb5537f | 195 | if (result == 0) |
a39a7484 RK |
196 | result = expand_unop (mode, neg_optab, x, NULL_RTX, 0); |
197 | ||
198 | return result; | |
44037a66 TG |
199 | } |
200 | \f | |
201 | /* Generate code to store value from rtx VALUE | |
202 | into a bit-field within structure STR_RTX | |
203 | containing BITSIZE bits starting at bit BITNUM. | |
204 | FIELDMODE is the machine-mode of the FIELD_DECL node for this field. | |
205 | ALIGN is the alignment that STR_RTX is known to have, measured in bytes. | |
206 | TOTAL_SIZE is the size of the structure in bytes, or -1 if varying. */ | |
207 | ||
208 | /* ??? Note that there are two different ideas here for how | |
209 | to determine the size to count bits within, for a register. | |
210 | One is BITS_PER_WORD, and the other is the size of operand 3 | |
211 | of the insv pattern. (The latter assumes that an n-bit machine | |
212 | will be able to insert bit fields up to n bits wide.) | |
213 | It isn't certain that either of these is right. | |
214 | extract_bit_field has the same quandary. */ | |
215 | ||
216 | rtx | |
217 | store_bit_field (str_rtx, bitsize, bitnum, fieldmode, value, align, total_size) | |
218 | rtx str_rtx; | |
219 | register int bitsize; | |
220 | int bitnum; | |
221 | enum machine_mode fieldmode; | |
222 | rtx value; | |
223 | int align; | |
224 | int total_size; | |
225 | { | |
226 | int unit = (GET_CODE (str_rtx) == MEM) ? BITS_PER_UNIT : BITS_PER_WORD; | |
227 | register int offset = bitnum / unit; | |
228 | register int bitpos = bitnum % unit; | |
229 | register rtx op0 = str_rtx; | |
230 | ||
231 | if (GET_CODE (str_rtx) == MEM && ! MEM_IN_STRUCT_P (str_rtx)) | |
232 | abort (); | |
233 | ||
234 | /* Discount the part of the structure before the desired byte. | |
235 | We need to know how many bytes are safe to reference after it. */ | |
236 | if (total_size >= 0) | |
237 | total_size -= (bitpos / BIGGEST_ALIGNMENT | |
238 | * (BIGGEST_ALIGNMENT / BITS_PER_UNIT)); | |
239 | ||
240 | while (GET_CODE (op0) == SUBREG) | |
241 | { | |
242 | /* The following line once was done only if WORDS_BIG_ENDIAN, | |
243 | but I think that is a mistake. WORDS_BIG_ENDIAN is | |
244 | meaningful at a much higher level; when structures are copied | |
245 | between memory and regs, the higher-numbered regs | |
246 | always get higher addresses. */ | |
247 | offset += SUBREG_WORD (op0); | |
248 | /* We used to adjust BITPOS here, but now we do the whole adjustment | |
249 | right after the loop. */ | |
250 | op0 = SUBREG_REG (op0); | |
251 | } | |
252 | ||
44037a66 TG |
253 | /* If OP0 is a register, BITPOS must count within a word. |
254 | But as we have it, it counts within whatever size OP0 now has. | |
255 | On a bigendian machine, these are not the same, so convert. */ | |
f76b9db2 ILT |
256 | if (BYTES_BIG_ENDIAN |
257 | && GET_CODE (op0) != MEM | |
258 | && unit > GET_MODE_BITSIZE (GET_MODE (op0))) | |
44037a66 | 259 | bitpos += unit - GET_MODE_BITSIZE (GET_MODE (op0)); |
44037a66 TG |
260 | |
261 | value = protect_from_queue (value, 0); | |
262 | ||
263 | if (flag_force_mem) | |
264 | value = force_not_mem (value); | |
265 | ||
266 | /* Note that the adjustment of BITPOS above has no effect on whether | |
267 | BITPOS is 0 in a REG bigger than a word. */ | |
56a2f049 | 268 | if (GET_MODE_SIZE (fieldmode) >= UNITS_PER_WORD |
c7e33f89 RS |
269 | && (GET_CODE (op0) != MEM |
270 | || ! SLOW_UNALIGNED_ACCESS | |
271 | || (offset * BITS_PER_UNIT % bitsize == 0 | |
272 | && align % GET_MODE_SIZE (fieldmode) == 0)) | |
44037a66 TG |
273 | && bitpos == 0 && bitsize == GET_MODE_BITSIZE (fieldmode)) |
274 | { | |
275 | /* Storing in a full-word or multi-word field in a register | |
276 | can be done with just SUBREG. */ | |
277 | if (GET_MODE (op0) != fieldmode) | |
c7e33f89 RS |
278 | { |
279 | if (GET_CODE (op0) == REG) | |
38a448ca | 280 | op0 = gen_rtx_SUBREG (fieldmode, op0, offset); |
c7e33f89 RS |
281 | else |
282 | op0 = change_address (op0, fieldmode, | |
283 | plus_constant (XEXP (op0, 0), offset)); | |
284 | } | |
44037a66 TG |
285 | emit_move_insn (op0, value); |
286 | return value; | |
287 | } | |
288 | ||
289 | /* Storing an lsb-aligned field in a register | |
290 | can be done with a movestrict instruction. */ | |
291 | ||
292 | if (GET_CODE (op0) != MEM | |
f76b9db2 | 293 | && (BYTES_BIG_ENDIAN ? bitpos + bitsize == unit : bitpos == 0) |
44037a66 TG |
294 | && bitsize == GET_MODE_BITSIZE (fieldmode) |
295 | && (GET_MODE (op0) == fieldmode | |
296 | || (movstrict_optab->handlers[(int) fieldmode].insn_code | |
297 | != CODE_FOR_nothing))) | |
298 | { | |
299 | /* Get appropriate low part of the value being stored. */ | |
300 | if (GET_CODE (value) == CONST_INT || GET_CODE (value) == REG) | |
301 | value = gen_lowpart (fieldmode, value); | |
302 | else if (!(GET_CODE (value) == SYMBOL_REF | |
303 | || GET_CODE (value) == LABEL_REF | |
304 | || GET_CODE (value) == CONST)) | |
305 | value = convert_to_mode (fieldmode, value, 0); | |
306 | ||
307 | if (GET_MODE (op0) == fieldmode) | |
308 | emit_move_insn (op0, value); | |
309 | else | |
310 | { | |
311 | int icode = movstrict_optab->handlers[(int) fieldmode].insn_code; | |
312 | if(! (*insn_operand_predicate[icode][1]) (value, fieldmode)) | |
313 | value = copy_to_mode_reg (fieldmode, value); | |
314 | emit_insn (GEN_FCN (icode) | |
38a448ca | 315 | (gen_rtx_SUBREG (fieldmode, op0, offset), value)); |
44037a66 TG |
316 | } |
317 | return value; | |
318 | } | |
319 | ||
320 | /* Handle fields bigger than a word. */ | |
321 | ||
322 | if (bitsize > BITS_PER_WORD) | |
323 | { | |
324 | /* Here we transfer the words of the field | |
325 | in the order least significant first. | |
326 | This is because the most significant word is the one which may | |
ad83e87b PB |
327 | be less than full. |
328 | However, only do that if the value is not BLKmode. */ | |
329 | ||
330 | int backwards = WORDS_BIG_ENDIAN && fieldmode != BLKmode; | |
44037a66 TG |
331 | |
332 | int nwords = (bitsize + (BITS_PER_WORD - 1)) / BITS_PER_WORD; | |
333 | int i; | |
334 | ||
335 | /* This is the mode we must force value to, so that there will be enough | |
336 | subwords to extract. Note that fieldmode will often (always?) be | |
337 | VOIDmode, because that is what store_field uses to indicate that this | |
338 | is a bit field, but passing VOIDmode to operand_subword_force will | |
339 | result in an abort. */ | |
340 | fieldmode = mode_for_size (nwords * BITS_PER_WORD, MODE_INT, 0); | |
341 | ||
342 | for (i = 0; i < nwords; i++) | |
343 | { | |
ad83e87b PB |
344 | /* If I is 0, use the low-order word in both field and target; |
345 | if I is 1, use the next to lowest word; and so on. */ | |
346 | int wordnum = (backwards ? nwords - i - 1 : i); | |
347 | int bit_offset = (backwards | |
348 | ? MAX (bitsize - (i + 1) * BITS_PER_WORD, 0) | |
349 | : i * BITS_PER_WORD); | |
44037a66 TG |
350 | store_bit_field (op0, MIN (BITS_PER_WORD, |
351 | bitsize - i * BITS_PER_WORD), | |
352 | bitnum + bit_offset, word_mode, | |
b3487765 RS |
353 | operand_subword_force (value, wordnum, |
354 | (GET_MODE (value) == VOIDmode | |
355 | ? fieldmode | |
356 | : GET_MODE (value))), | |
44037a66 TG |
357 | align, total_size); |
358 | } | |
359 | return value; | |
360 | } | |
361 | ||
362 | /* From here on we can assume that the field to be stored in is | |
363 | a full-word (whatever type that is), since it is shorter than a word. */ | |
364 | ||
365 | /* OFFSET is the number of words or bytes (UNIT says which) | |
366 | from STR_RTX to the first word or byte containing part of the field. */ | |
367 | ||
368 | if (GET_CODE (op0) == REG) | |
369 | { | |
370 | if (offset != 0 | |
371 | || GET_MODE_SIZE (GET_MODE (op0)) > UNITS_PER_WORD) | |
38a448ca | 372 | op0 = gen_rtx_SUBREG (TYPE_MODE (type_for_size (BITS_PER_WORD, 0)), |
44037a66 TG |
373 | op0, offset); |
374 | offset = 0; | |
375 | } | |
376 | else | |
377 | { | |
378 | op0 = protect_from_queue (op0, 1); | |
379 | } | |
380 | ||
2305bcad JW |
381 | /* If VALUE is a floating-point mode, access it as an integer of the |
382 | corresponding size. This can occur on a machine with 64 bit registers | |
383 | that uses SFmode for float. This can also occur for unaligned float | |
384 | structure fields. */ | |
385 | if (GET_MODE_CLASS (GET_MODE (value)) == MODE_FLOAT) | |
386 | { | |
387 | if (GET_CODE (value) != REG) | |
388 | value = copy_to_reg (value); | |
38a448ca | 389 | value = gen_rtx_SUBREG (word_mode, value, 0); |
2305bcad JW |
390 | } |
391 | ||
44037a66 TG |
392 | /* Now OFFSET is nonzero only if OP0 is memory |
393 | and is therefore always measured in bytes. */ | |
394 | ||
395 | #ifdef HAVE_insv | |
396 | if (HAVE_insv | |
1d269b0c | 397 | && GET_MODE (value) != BLKmode |
44037a66 TG |
398 | && !(bitsize == 1 && GET_CODE (value) == CONST_INT) |
399 | /* Ensure insv's size is wide enough for this field. */ | |
400 | && (GET_MODE_BITSIZE (insn_operand_mode[(int) CODE_FOR_insv][3]) | |
39e0911f RK |
401 | >= bitsize) |
402 | && ! ((GET_CODE (op0) == REG || GET_CODE (op0) == SUBREG) | |
403 | && (bitsize + bitpos | |
404 | > GET_MODE_BITSIZE (insn_operand_mode[(int) CODE_FOR_insv][3])))) | |
44037a66 TG |
405 | { |
406 | int xbitpos = bitpos; | |
407 | rtx value1; | |
408 | rtx xop0 = op0; | |
409 | rtx last = get_last_insn (); | |
410 | rtx pat; | |
411 | enum machine_mode maxmode | |
412 | = insn_operand_mode[(int) CODE_FOR_insv][3]; | |
413 | ||
414 | int save_volatile_ok = volatile_ok; | |
415 | volatile_ok = 1; | |
416 | ||
4dbebeb2 JW |
417 | /* If this machine's insv can only insert into a register, copy OP0 |
418 | into a register and save it back later. */ | |
419 | /* This used to check flag_force_mem, but that was a serious | |
420 | de-optimization now that flag_force_mem is enabled by -O2. */ | |
44037a66 | 421 | if (GET_CODE (op0) == MEM |
4dbebeb2 JW |
422 | && ! ((*insn_operand_predicate[(int) CODE_FOR_insv][0]) |
423 | (op0, VOIDmode))) | |
44037a66 TG |
424 | { |
425 | rtx tempreg; | |
426 | enum machine_mode bestmode; | |
427 | ||
428 | /* Get the mode to use for inserting into this field. If OP0 is | |
429 | BLKmode, get the smallest mode consistent with the alignment. If | |
430 | OP0 is a non-BLKmode object that is no wider than MAXMODE, use its | |
431 | mode. Otherwise, use the smallest mode containing the field. */ | |
432 | ||
433 | if (GET_MODE (op0) == BLKmode | |
434 | || GET_MODE_SIZE (GET_MODE (op0)) > GET_MODE_SIZE (maxmode)) | |
435 | bestmode | |
717702e6 RK |
436 | = get_best_mode (bitsize, bitnum, align * BITS_PER_UNIT, maxmode, |
437 | MEM_VOLATILE_P (op0)); | |
44037a66 TG |
438 | else |
439 | bestmode = GET_MODE (op0); | |
440 | ||
bd5d175a | 441 | if (bestmode == VOIDmode |
5970d32e | 442 | || (SLOW_UNALIGNED_ACCESS && GET_MODE_SIZE (bestmode) > align)) |
44037a66 TG |
443 | goto insv_loses; |
444 | ||
445 | /* Adjust address to point to the containing unit of that mode. */ | |
446 | unit = GET_MODE_BITSIZE (bestmode); | |
447 | /* Compute offset as multiple of this unit, counting in bytes. */ | |
448 | offset = (bitnum / unit) * GET_MODE_SIZE (bestmode); | |
449 | bitpos = bitnum % unit; | |
450 | op0 = change_address (op0, bestmode, | |
451 | plus_constant (XEXP (op0, 0), offset)); | |
452 | ||
453 | /* Fetch that unit, store the bitfield in it, then store the unit. */ | |
454 | tempreg = copy_to_reg (op0); | |
455 | store_bit_field (tempreg, bitsize, bitpos, fieldmode, value, | |
456 | align, total_size); | |
457 | emit_move_insn (op0, tempreg); | |
458 | return value; | |
459 | } | |
460 | volatile_ok = save_volatile_ok; | |
461 | ||
462 | /* Add OFFSET into OP0's address. */ | |
463 | if (GET_CODE (xop0) == MEM) | |
464 | xop0 = change_address (xop0, byte_mode, | |
465 | plus_constant (XEXP (xop0, 0), offset)); | |
466 | ||
467 | /* If xop0 is a register, we need it in MAXMODE | |
468 | to make it acceptable to the format of insv. */ | |
469 | if (GET_CODE (xop0) == SUBREG) | |
bac7cdfd DE |
470 | /* We can't just change the mode, because this might clobber op0, |
471 | and we will need the original value of op0 if insv fails. */ | |
38a448ca | 472 | xop0 = gen_rtx_SUBREG (maxmode, SUBREG_REG (xop0), SUBREG_WORD (xop0)); |
44037a66 | 473 | if (GET_CODE (xop0) == REG && GET_MODE (xop0) != maxmode) |
38a448ca | 474 | xop0 = gen_rtx_SUBREG (maxmode, xop0, 0); |
44037a66 TG |
475 | |
476 | /* On big-endian machines, we count bits from the most significant. | |
477 | If the bit field insn does not, we must invert. */ | |
478 | ||
f76b9db2 ILT |
479 | if (BITS_BIG_ENDIAN != BYTES_BIG_ENDIAN) |
480 | xbitpos = unit - bitsize - xbitpos; | |
481 | ||
44037a66 TG |
482 | /* We have been counting XBITPOS within UNIT. |
483 | Count instead within the size of the register. */ | |
f76b9db2 | 484 | if (BITS_BIG_ENDIAN && GET_CODE (xop0) != MEM) |
44037a66 | 485 | xbitpos += GET_MODE_BITSIZE (maxmode) - unit; |
f76b9db2 | 486 | |
44037a66 TG |
487 | unit = GET_MODE_BITSIZE (maxmode); |
488 | ||
489 | /* Convert VALUE to maxmode (which insv insn wants) in VALUE1. */ | |
490 | value1 = value; | |
491 | if (GET_MODE (value) != maxmode) | |
492 | { | |
493 | if (GET_MODE_BITSIZE (GET_MODE (value)) >= bitsize) | |
494 | { | |
495 | /* Optimization: Don't bother really extending VALUE | |
f5df292e RS |
496 | if it has all the bits we will actually use. However, |
497 | if we must narrow it, be sure we do it correctly. */ | |
44037a66 | 498 | |
f5df292e RS |
499 | if (GET_MODE_SIZE (GET_MODE (value)) < GET_MODE_SIZE (maxmode)) |
500 | { | |
501 | /* Avoid making subreg of a subreg, or of a mem. */ | |
502 | if (GET_CODE (value1) != REG) | |
44037a66 | 503 | value1 = copy_to_reg (value1); |
38a448ca | 504 | value1 = gen_rtx_SUBREG (maxmode, value1, 0); |
f5df292e RS |
505 | } |
506 | else | |
507 | value1 = gen_lowpart (maxmode, value1); | |
44037a66 TG |
508 | } |
509 | else if (!CONSTANT_P (value)) | |
510 | /* Parse phase is supposed to make VALUE's data type | |
511 | match that of the component reference, which is a type | |
512 | at least as wide as the field; so VALUE should have | |
513 | a mode that corresponds to that type. */ | |
514 | abort (); | |
515 | } | |
516 | ||
517 | /* If this machine's insv insists on a register, | |
518 | get VALUE1 into a register. */ | |
519 | if (! ((*insn_operand_predicate[(int) CODE_FOR_insv][3]) | |
520 | (value1, maxmode))) | |
521 | value1 = force_reg (maxmode, value1); | |
522 | ||
b1ec3c92 | 523 | pat = gen_insv (xop0, GEN_INT (bitsize), GEN_INT (xbitpos), value1); |
44037a66 TG |
524 | if (pat) |
525 | emit_insn (pat); | |
526 | else | |
527 | { | |
528 | delete_insns_since (last); | |
529 | store_fixed_bit_field (op0, offset, bitsize, bitpos, value, align); | |
530 | } | |
531 | } | |
532 | else | |
533 | insv_loses: | |
534 | #endif | |
535 | /* Insv is not available; store using shifts and boolean ops. */ | |
536 | store_fixed_bit_field (op0, offset, bitsize, bitpos, value, align); | |
537 | return value; | |
538 | } | |
539 | \f | |
540 | /* Use shifts and boolean operations to store VALUE | |
541 | into a bit field of width BITSIZE | |
542 | in a memory location specified by OP0 except offset by OFFSET bytes. | |
543 | (OFFSET must be 0 if OP0 is a register.) | |
544 | The field starts at position BITPOS within the byte. | |
545 | (If OP0 is a register, it may be a full word or a narrower mode, | |
546 | but BITPOS still counts within a full word, | |
547 | which is significant on bigendian machines.) | |
548 | STRUCT_ALIGN is the alignment the structure is known to have (in bytes). | |
549 | ||
550 | Note that protect_from_queue has already been done on OP0 and VALUE. */ | |
551 | ||
552 | static void | |
553 | store_fixed_bit_field (op0, offset, bitsize, bitpos, value, struct_align) | |
554 | register rtx op0; | |
555 | register int offset, bitsize, bitpos; | |
556 | register rtx value; | |
557 | int struct_align; | |
558 | { | |
559 | register enum machine_mode mode; | |
560 | int total_bits = BITS_PER_WORD; | |
561 | rtx subtarget, temp; | |
562 | int all_zero = 0; | |
563 | int all_one = 0; | |
564 | ||
c7554b28 RK |
565 | if (! SLOW_UNALIGNED_ACCESS) |
566 | struct_align = BIGGEST_ALIGNMENT / BITS_PER_UNIT; | |
567 | ||
44037a66 TG |
568 | /* There is a case not handled here: |
569 | a structure with a known alignment of just a halfword | |
570 | and a field split across two aligned halfwords within the structure. | |
571 | Or likewise a structure with a known alignment of just a byte | |
572 | and a field split across two bytes. | |
573 | Such cases are not supposed to be able to occur. */ | |
574 | ||
575 | if (GET_CODE (op0) == REG || GET_CODE (op0) == SUBREG) | |
576 | { | |
577 | if (offset != 0) | |
578 | abort (); | |
579 | /* Special treatment for a bit field split across two registers. */ | |
580 | if (bitsize + bitpos > BITS_PER_WORD) | |
581 | { | |
06c94bce RS |
582 | store_split_bit_field (op0, bitsize, bitpos, |
583 | value, BITS_PER_WORD); | |
44037a66 TG |
584 | return; |
585 | } | |
586 | } | |
587 | else | |
588 | { | |
589 | /* Get the proper mode to use for this field. We want a mode that | |
590 | includes the entire field. If such a mode would be larger than | |
591 | a word, we won't be doing the extraction the normal way. */ | |
592 | ||
593 | mode = get_best_mode (bitsize, bitpos + offset * BITS_PER_UNIT, | |
594 | struct_align * BITS_PER_UNIT, word_mode, | |
595 | GET_CODE (op0) == MEM && MEM_VOLATILE_P (op0)); | |
596 | ||
597 | if (mode == VOIDmode) | |
598 | { | |
599 | /* The only way this should occur is if the field spans word | |
600 | boundaries. */ | |
06c94bce RS |
601 | store_split_bit_field (op0, |
602 | bitsize, bitpos + offset * BITS_PER_UNIT, | |
44037a66 TG |
603 | value, struct_align); |
604 | return; | |
605 | } | |
606 | ||
607 | total_bits = GET_MODE_BITSIZE (mode); | |
608 | ||
3bd98790 JW |
609 | /* Make sure bitpos is valid for the chosen mode. Adjust BITPOS to |
610 | be be in the range 0 to total_bits-1, and put any excess bytes in | |
611 | OFFSET. */ | |
612 | if (bitpos >= total_bits) | |
613 | { | |
614 | offset += (bitpos / total_bits) * (total_bits / BITS_PER_UNIT); | |
615 | bitpos -= ((bitpos / total_bits) * (total_bits / BITS_PER_UNIT) | |
616 | * BITS_PER_UNIT); | |
617 | } | |
618 | ||
44037a66 TG |
619 | /* Get ref to an aligned byte, halfword, or word containing the field. |
620 | Adjust BITPOS to be position within a word, | |
621 | and OFFSET to be the offset of that word. | |
622 | Then alter OP0 to refer to that word. */ | |
623 | bitpos += (offset % (total_bits / BITS_PER_UNIT)) * BITS_PER_UNIT; | |
624 | offset -= (offset % (total_bits / BITS_PER_UNIT)); | |
625 | op0 = change_address (op0, mode, | |
626 | plus_constant (XEXP (op0, 0), offset)); | |
627 | } | |
628 | ||
629 | mode = GET_MODE (op0); | |
630 | ||
631 | /* Now MODE is either some integral mode for a MEM as OP0, | |
632 | or is a full-word for a REG as OP0. TOTAL_BITS corresponds. | |
633 | The bit field is contained entirely within OP0. | |
634 | BITPOS is the starting bit number within OP0. | |
635 | (OP0's mode may actually be narrower than MODE.) */ | |
636 | ||
f76b9db2 ILT |
637 | if (BYTES_BIG_ENDIAN) |
638 | /* BITPOS is the distance between our msb | |
639 | and that of the containing datum. | |
640 | Convert it to the distance from the lsb. */ | |
641 | bitpos = total_bits - bitsize - bitpos; | |
44037a66 | 642 | |
44037a66 TG |
643 | /* Now BITPOS is always the distance between our lsb |
644 | and that of OP0. */ | |
645 | ||
646 | /* Shift VALUE left by BITPOS bits. If VALUE is not constant, | |
647 | we must first convert its mode to MODE. */ | |
648 | ||
649 | if (GET_CODE (value) == CONST_INT) | |
650 | { | |
b1ec3c92 | 651 | register HOST_WIDE_INT v = INTVAL (value); |
44037a66 | 652 | |
b1ec3c92 CH |
653 | if (bitsize < HOST_BITS_PER_WIDE_INT) |
654 | v &= ((HOST_WIDE_INT) 1 << bitsize) - 1; | |
44037a66 TG |
655 | |
656 | if (v == 0) | |
657 | all_zero = 1; | |
b1ec3c92 CH |
658 | else if ((bitsize < HOST_BITS_PER_WIDE_INT |
659 | && v == ((HOST_WIDE_INT) 1 << bitsize) - 1) | |
660 | || (bitsize == HOST_BITS_PER_WIDE_INT && v == -1)) | |
44037a66 TG |
661 | all_one = 1; |
662 | ||
663 | value = lshift_value (mode, value, bitpos, bitsize); | |
664 | } | |
665 | else | |
666 | { | |
667 | int must_and = (GET_MODE_BITSIZE (GET_MODE (value)) != bitsize | |
668 | && bitpos + bitsize != GET_MODE_BITSIZE (mode)); | |
669 | ||
670 | if (GET_MODE (value) != mode) | |
671 | { | |
44037a66 TG |
672 | if ((GET_CODE (value) == REG || GET_CODE (value) == SUBREG) |
673 | && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (value))) | |
674 | value = gen_lowpart (mode, value); | |
675 | else | |
676 | value = convert_to_mode (mode, value, 1); | |
677 | } | |
678 | ||
679 | if (must_and) | |
680 | value = expand_binop (mode, and_optab, value, | |
681 | mask_rtx (mode, 0, bitsize, 0), | |
b1ec3c92 | 682 | NULL_RTX, 1, OPTAB_LIB_WIDEN); |
44037a66 TG |
683 | if (bitpos > 0) |
684 | value = expand_shift (LSHIFT_EXPR, mode, value, | |
b1ec3c92 | 685 | build_int_2 (bitpos, 0), NULL_RTX, 1); |
44037a66 TG |
686 | } |
687 | ||
688 | /* Now clear the chosen bits in OP0, | |
689 | except that if VALUE is -1 we need not bother. */ | |
690 | ||
691 | subtarget = (GET_CODE (op0) == REG || ! flag_force_mem) ? op0 : 0; | |
692 | ||
693 | if (! all_one) | |
694 | { | |
695 | temp = expand_binop (mode, and_optab, op0, | |
696 | mask_rtx (mode, bitpos, bitsize, 1), | |
697 | subtarget, 1, OPTAB_LIB_WIDEN); | |
698 | subtarget = temp; | |
699 | } | |
700 | else | |
701 | temp = op0; | |
702 | ||
703 | /* Now logical-or VALUE into OP0, unless it is zero. */ | |
704 | ||
705 | if (! all_zero) | |
706 | temp = expand_binop (mode, ior_optab, temp, value, | |
707 | subtarget, 1, OPTAB_LIB_WIDEN); | |
708 | if (op0 != temp) | |
709 | emit_move_insn (op0, temp); | |
710 | } | |
711 | \f | |
06c94bce | 712 | /* Store a bit field that is split across multiple accessible memory objects. |
44037a66 | 713 | |
06c94bce | 714 | OP0 is the REG, SUBREG or MEM rtx for the first of the objects. |
44037a66 TG |
715 | BITSIZE is the field width; BITPOS the position of its first bit |
716 | (within the word). | |
06c94bce RS |
717 | VALUE is the value to store. |
718 | ALIGN is the known alignment of OP0, measured in bytes. | |
719 | This is also the size of the memory objects to be used. | |
720 | ||
721 | This does not yet handle fields wider than BITS_PER_WORD. */ | |
44037a66 TG |
722 | |
723 | static void | |
724 | store_split_bit_field (op0, bitsize, bitpos, value, align) | |
725 | rtx op0; | |
726 | int bitsize, bitpos; | |
727 | rtx value; | |
728 | int align; | |
729 | { | |
4ee16841 DE |
730 | int unit; |
731 | int bitsdone = 0; | |
732 | ||
0eb61c19 DE |
733 | /* Make sure UNIT isn't larger than BITS_PER_WORD, we can only handle that |
734 | much at a time. */ | |
4ee16841 DE |
735 | if (GET_CODE (op0) == REG || GET_CODE (op0) == SUBREG) |
736 | unit = BITS_PER_WORD; | |
737 | else | |
738 | unit = MIN (align * BITS_PER_UNIT, BITS_PER_WORD); | |
e54d80d0 | 739 | |
3d709ff0 RS |
740 | /* If VALUE is a constant other than a CONST_INT, get it into a register in |
741 | WORD_MODE. If we can do this using gen_lowpart_common, do so. Note | |
742 | that VALUE might be a floating-point constant. */ | |
44037a66 | 743 | if (CONSTANT_P (value) && GET_CODE (value) != CONST_INT) |
3d709ff0 RS |
744 | { |
745 | rtx word = gen_lowpart_common (word_mode, value); | |
746 | ||
bc8a0e39 | 747 | if (word && (value != word)) |
3d709ff0 RS |
748 | value = word; |
749 | else | |
750 | value = gen_lowpart_common (word_mode, | |
d01bc862 DE |
751 | force_reg (GET_MODE (value) != VOIDmode |
752 | ? GET_MODE (value) | |
753 | : word_mode, value)); | |
3d709ff0 | 754 | } |
956d6950 JL |
755 | else if (GET_CODE (value) == ADDRESSOF) |
756 | value = copy_to_reg (value); | |
44037a66 | 757 | |
06c94bce | 758 | while (bitsdone < bitsize) |
44037a66 | 759 | { |
06c94bce RS |
760 | int thissize; |
761 | rtx part, word; | |
762 | int thispos; | |
763 | int offset; | |
44037a66 | 764 | |
06c94bce RS |
765 | offset = (bitpos + bitsdone) / unit; |
766 | thispos = (bitpos + bitsdone) % unit; | |
44037a66 | 767 | |
0eb61c19 DE |
768 | /* THISSIZE must not overrun a word boundary. Otherwise, |
769 | store_fixed_bit_field will call us again, and we will mutually | |
770 | recurse forever. */ | |
771 | thissize = MIN (bitsize - bitsdone, BITS_PER_WORD); | |
772 | thissize = MIN (thissize, unit - thispos); | |
44037a66 | 773 | |
f76b9db2 ILT |
774 | if (BYTES_BIG_ENDIAN) |
775 | { | |
37811a73 RK |
776 | int total_bits; |
777 | ||
778 | /* We must do an endian conversion exactly the same way as it is | |
779 | done in extract_bit_field, so that the two calls to | |
780 | extract_fixed_bit_field will have comparable arguments. */ | |
1d269b0c | 781 | if (GET_CODE (value) != MEM || GET_MODE (value) == BLKmode) |
37811a73 RK |
782 | total_bits = BITS_PER_WORD; |
783 | else | |
784 | total_bits = GET_MODE_BITSIZE (GET_MODE (value)); | |
785 | ||
f76b9db2 ILT |
786 | /* Fetch successively less significant portions. */ |
787 | if (GET_CODE (value) == CONST_INT) | |
788 | part = GEN_INT (((unsigned HOST_WIDE_INT) (INTVAL (value)) | |
789 | >> (bitsize - bitsdone - thissize)) | |
790 | & (((HOST_WIDE_INT) 1 << thissize) - 1)); | |
791 | else | |
792 | /* The args are chosen so that the last part includes the | |
793 | lsb. Give extract_bit_field the value it needs (with | |
3cd45606 RK |
794 | endianness compensation) to fetch the piece we want. |
795 | ||
796 | ??? We have no idea what the alignment of VALUE is, so | |
797 | we have to use a guess. */ | |
798 | part | |
799 | = extract_fixed_bit_field | |
800 | (word_mode, value, 0, thissize, | |
801 | total_bits - bitsize + bitsdone, NULL_RTX, 1, | |
802 | GET_MODE (value) == VOIDmode | |
803 | ? UNITS_PER_WORD | |
804 | : (GET_MODE (value) == BLKmode | |
805 | ? 1 | |
806 | : GET_MODE_ALIGNMENT (GET_MODE (value)) / BITS_PER_UNIT)); | |
f76b9db2 | 807 | } |
06c94bce | 808 | else |
f76b9db2 ILT |
809 | { |
810 | /* Fetch successively more significant portions. */ | |
811 | if (GET_CODE (value) == CONST_INT) | |
812 | part = GEN_INT (((unsigned HOST_WIDE_INT) (INTVAL (value)) | |
813 | >> bitsdone) | |
814 | & (((HOST_WIDE_INT) 1 << thissize) - 1)); | |
815 | else | |
3cd45606 RK |
816 | part |
817 | = extract_fixed_bit_field | |
818 | (word_mode, value, 0, thissize, bitsdone, NULL_RTX, 1, | |
819 | GET_MODE (value) == VOIDmode | |
820 | ? UNITS_PER_WORD | |
821 | : (GET_MODE (value) == BLKmode | |
822 | ? 1 | |
823 | : GET_MODE_ALIGNMENT (GET_MODE (value)) / BITS_PER_UNIT)); | |
f76b9db2 | 824 | } |
44037a66 | 825 | |
06c94bce | 826 | /* If OP0 is a register, then handle OFFSET here. |
5f57dff0 JW |
827 | |
828 | When handling multiword bitfields, extract_bit_field may pass | |
829 | down a word_mode SUBREG of a larger REG for a bitfield that actually | |
830 | crosses a word boundary. Thus, for a SUBREG, we must find | |
831 | the current word starting from the base register. */ | |
832 | if (GET_CODE (op0) == SUBREG) | |
833 | { | |
4ee16841 DE |
834 | word = operand_subword_force (SUBREG_REG (op0), |
835 | SUBREG_WORD (op0) + offset, | |
836 | GET_MODE (SUBREG_REG (op0))); | |
5f57dff0 JW |
837 | offset = 0; |
838 | } | |
839 | else if (GET_CODE (op0) == REG) | |
06c94bce | 840 | { |
4ee16841 | 841 | word = operand_subword_force (op0, offset, GET_MODE (op0)); |
06c94bce RS |
842 | offset = 0; |
843 | } | |
844 | else | |
845 | word = op0; | |
44037a66 | 846 | |
0eb61c19 DE |
847 | /* OFFSET is in UNITs, and UNIT is in bits. |
848 | store_fixed_bit_field wants offset in bytes. */ | |
849 | store_fixed_bit_field (word, offset * unit / BITS_PER_UNIT, | |
850 | thissize, thispos, part, align); | |
06c94bce RS |
851 | bitsdone += thissize; |
852 | } | |
44037a66 TG |
853 | } |
854 | \f | |
855 | /* Generate code to extract a byte-field from STR_RTX | |
856 | containing BITSIZE bits, starting at BITNUM, | |
857 | and put it in TARGET if possible (if TARGET is nonzero). | |
858 | Regardless of TARGET, we return the rtx for where the value is placed. | |
859 | It may be a QUEUED. | |
860 | ||
861 | STR_RTX is the structure containing the byte (a REG or MEM). | |
862 | UNSIGNEDP is nonzero if this is an unsigned bit field. | |
863 | MODE is the natural mode of the field value once extracted. | |
864 | TMODE is the mode the caller would like the value to have; | |
865 | but the value may be returned with type MODE instead. | |
866 | ||
867 | ALIGN is the alignment that STR_RTX is known to have, measured in bytes. | |
868 | TOTAL_SIZE is the size in bytes of the containing structure, | |
869 | or -1 if varying. | |
870 | ||
871 | If a TARGET is specified and we can store in it at no extra cost, | |
872 | we do so, and return TARGET. | |
873 | Otherwise, we return a REG of mode TMODE or MODE, with TMODE preferred | |
874 | if they are equally easy. */ | |
875 | ||
876 | rtx | |
877 | extract_bit_field (str_rtx, bitsize, bitnum, unsignedp, | |
878 | target, mode, tmode, align, total_size) | |
879 | rtx str_rtx; | |
880 | register int bitsize; | |
881 | int bitnum; | |
882 | int unsignedp; | |
883 | rtx target; | |
884 | enum machine_mode mode, tmode; | |
885 | int align; | |
886 | int total_size; | |
887 | { | |
888 | int unit = (GET_CODE (str_rtx) == MEM) ? BITS_PER_UNIT : BITS_PER_WORD; | |
889 | register int offset = bitnum / unit; | |
890 | register int bitpos = bitnum % unit; | |
891 | register rtx op0 = str_rtx; | |
892 | rtx spec_target = target; | |
893 | rtx spec_target_subreg = 0; | |
894 | ||
44037a66 TG |
895 | /* Discount the part of the structure before the desired byte. |
896 | We need to know how many bytes are safe to reference after it. */ | |
897 | if (total_size >= 0) | |
898 | total_size -= (bitpos / BIGGEST_ALIGNMENT | |
899 | * (BIGGEST_ALIGNMENT / BITS_PER_UNIT)); | |
900 | ||
901 | if (tmode == VOIDmode) | |
902 | tmode = mode; | |
44037a66 TG |
903 | while (GET_CODE (op0) == SUBREG) |
904 | { | |
64191612 MM |
905 | int outer_size = GET_MODE_BITSIZE (GET_MODE (op0)); |
906 | int inner_size = GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))); | |
907 | ||
44037a66 | 908 | offset += SUBREG_WORD (op0); |
64191612 MM |
909 | |
910 | if (BYTES_BIG_ENDIAN && (outer_size < inner_size)) | |
911 | { | |
912 | bitpos += inner_size - outer_size; | |
913 | if (bitpos > unit) | |
914 | { | |
915 | offset += (bitpos / unit); | |
916 | bitpos %= unit; | |
917 | } | |
918 | } | |
919 | ||
44037a66 TG |
920 | op0 = SUBREG_REG (op0); |
921 | } | |
77295dec DE |
922 | |
923 | /* ??? We currently assume TARGET is at least as big as BITSIZE. | |
924 | If that's wrong, the solution is to test for it and set TARGET to 0 | |
925 | if needed. */ | |
44037a66 | 926 | |
44037a66 TG |
927 | /* If OP0 is a register, BITPOS must count within a word. |
928 | But as we have it, it counts within whatever size OP0 now has. | |
929 | On a bigendian machine, these are not the same, so convert. */ | |
db3cf6fb MS |
930 | if (BYTES_BIG_ENDIAN |
931 | && GET_CODE (op0) != MEM | |
f76b9db2 | 932 | && unit > GET_MODE_BITSIZE (GET_MODE (op0))) |
44037a66 | 933 | bitpos += unit - GET_MODE_BITSIZE (GET_MODE (op0)); |
44037a66 TG |
934 | |
935 | /* Extracting a full-word or multi-word value | |
c7e33f89 | 936 | from a structure in a register or aligned memory. |
44037a66 TG |
937 | This can be done with just SUBREG. |
938 | So too extracting a subword value in | |
939 | the least significant part of the register. */ | |
940 | ||
f8fe20b2 JW |
941 | if (((GET_CODE (op0) == REG |
942 | && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode), | |
943 | GET_MODE_BITSIZE (GET_MODE (op0)))) | |
c7e33f89 RS |
944 | || (GET_CODE (op0) == MEM |
945 | && (! SLOW_UNALIGNED_ACCESS | |
946 | || (offset * BITS_PER_UNIT % bitsize == 0 | |
947 | && align * BITS_PER_UNIT % bitsize == 0)))) | |
44037a66 TG |
948 | && ((bitsize >= BITS_PER_WORD && bitsize == GET_MODE_BITSIZE (mode) |
949 | && bitpos % BITS_PER_WORD == 0) | |
950 | || (mode_for_size (bitsize, GET_MODE_CLASS (tmode), 0) != BLKmode | |
f76b9db2 ILT |
951 | && (BYTES_BIG_ENDIAN |
952 | ? bitpos + bitsize == BITS_PER_WORD | |
953 | : bitpos == 0)))) | |
44037a66 TG |
954 | { |
955 | enum machine_mode mode1 | |
956 | = mode_for_size (bitsize, GET_MODE_CLASS (tmode), 0); | |
957 | ||
958 | if (mode1 != GET_MODE (op0)) | |
c7e33f89 RS |
959 | { |
960 | if (GET_CODE (op0) == REG) | |
38a448ca | 961 | op0 = gen_rtx_SUBREG (mode1, op0, offset); |
c7e33f89 RS |
962 | else |
963 | op0 = change_address (op0, mode1, | |
964 | plus_constant (XEXP (op0, 0), offset)); | |
965 | } | |
44037a66 TG |
966 | if (mode1 != mode) |
967 | return convert_to_mode (tmode, op0, unsignedp); | |
968 | return op0; | |
969 | } | |
970 | ||
971 | /* Handle fields bigger than a word. */ | |
972 | ||
973 | if (bitsize > BITS_PER_WORD) | |
974 | { | |
975 | /* Here we transfer the words of the field | |
976 | in the order least significant first. | |
977 | This is because the most significant word is the one which may | |
978 | be less than full. */ | |
979 | ||
980 | int nwords = (bitsize + (BITS_PER_WORD - 1)) / BITS_PER_WORD; | |
981 | int i; | |
982 | ||
983 | if (target == 0 || GET_CODE (target) != REG) | |
984 | target = gen_reg_rtx (mode); | |
985 | ||
34ea783b | 986 | /* Indicate for flow that the entire target reg is being set. */ |
38a448ca | 987 | emit_insn (gen_rtx_CLOBBER (VOIDmode, target)); |
34ea783b | 988 | |
44037a66 TG |
989 | for (i = 0; i < nwords; i++) |
990 | { | |
991 | /* If I is 0, use the low-order word in both field and target; | |
992 | if I is 1, use the next to lowest word; and so on. */ | |
77295dec DE |
993 | /* Word number in TARGET to use. */ |
994 | int wordnum = (WORDS_BIG_ENDIAN | |
995 | ? GET_MODE_SIZE (GET_MODE (target)) / UNITS_PER_WORD - i - 1 | |
996 | : i); | |
997 | /* Offset from start of field in OP0. */ | |
44037a66 TG |
998 | int bit_offset = (WORDS_BIG_ENDIAN |
999 | ? MAX (0, bitsize - (i + 1) * BITS_PER_WORD) | |
1000 | : i * BITS_PER_WORD); | |
1001 | rtx target_part = operand_subword (target, wordnum, 1, VOIDmode); | |
1002 | rtx result_part | |
1003 | = extract_bit_field (op0, MIN (BITS_PER_WORD, | |
1004 | bitsize - i * BITS_PER_WORD), | |
1005 | bitnum + bit_offset, | |
1006 | 1, target_part, mode, word_mode, | |
1007 | align, total_size); | |
1008 | ||
1009 | if (target_part == 0) | |
1010 | abort (); | |
1011 | ||
1012 | if (result_part != target_part) | |
1013 | emit_move_insn (target_part, result_part); | |
1014 | } | |
1015 | ||
5f57dff0 | 1016 | if (unsignedp) |
77295dec DE |
1017 | { |
1018 | /* Unless we've filled TARGET, the upper regs in a multi-reg value | |
1019 | need to be zero'd out. */ | |
1020 | if (GET_MODE_SIZE (GET_MODE (target)) > nwords * UNITS_PER_WORD) | |
1021 | { | |
1022 | int i,total_words; | |
1023 | ||
1024 | total_words = GET_MODE_SIZE (GET_MODE (target)) / UNITS_PER_WORD; | |
1025 | for (i = nwords; i < total_words; i++) | |
1026 | { | |
1027 | int wordnum = WORDS_BIG_ENDIAN ? total_words - i - 1 : i; | |
1028 | rtx target_part = operand_subword (target, wordnum, 1, VOIDmode); | |
1029 | emit_move_insn (target_part, const0_rtx); | |
1030 | } | |
1031 | } | |
1032 | return target; | |
1033 | } | |
1034 | ||
5f57dff0 JW |
1035 | /* Signed bit field: sign-extend with two arithmetic shifts. */ |
1036 | target = expand_shift (LSHIFT_EXPR, mode, target, | |
1037 | build_int_2 (GET_MODE_BITSIZE (mode) - bitsize, 0), | |
1038 | NULL_RTX, 0); | |
1039 | return expand_shift (RSHIFT_EXPR, mode, target, | |
1040 | build_int_2 (GET_MODE_BITSIZE (mode) - bitsize, 0), | |
1041 | NULL_RTX, 0); | |
44037a66 TG |
1042 | } |
1043 | ||
1044 | /* From here on we know the desired field is smaller than a word | |
1045 | so we can assume it is an integer. So we can safely extract it as one | |
1046 | size of integer, if necessary, and then truncate or extend | |
1047 | to the size that is wanted. */ | |
1048 | ||
1049 | /* OFFSET is the number of words or bytes (UNIT says which) | |
1050 | from STR_RTX to the first word or byte containing part of the field. */ | |
1051 | ||
1052 | if (GET_CODE (op0) == REG) | |
1053 | { | |
1054 | if (offset != 0 | |
1055 | || GET_MODE_SIZE (GET_MODE (op0)) > UNITS_PER_WORD) | |
38a448ca | 1056 | op0 = gen_rtx_SUBREG (TYPE_MODE (type_for_size (BITS_PER_WORD, 0)), |
44037a66 TG |
1057 | op0, offset); |
1058 | offset = 0; | |
1059 | } | |
1060 | else | |
1061 | { | |
1062 | op0 = protect_from_queue (str_rtx, 1); | |
1063 | } | |
1064 | ||
1065 | /* Now OFFSET is nonzero only for memory operands. */ | |
1066 | ||
1067 | if (unsignedp) | |
1068 | { | |
1069 | #ifdef HAVE_extzv | |
1070 | if (HAVE_extzv | |
1071 | && (GET_MODE_BITSIZE (insn_operand_mode[(int) CODE_FOR_extzv][0]) | |
39e0911f RK |
1072 | >= bitsize) |
1073 | && ! ((GET_CODE (op0) == REG || GET_CODE (op0) == SUBREG) | |
1074 | && (bitsize + bitpos | |
1075 | > GET_MODE_BITSIZE (insn_operand_mode[(int) CODE_FOR_extzv][0])))) | |
44037a66 TG |
1076 | { |
1077 | int xbitpos = bitpos, xoffset = offset; | |
1078 | rtx bitsize_rtx, bitpos_rtx; | |
1079 | rtx last = get_last_insn(); | |
1080 | rtx xop0 = op0; | |
1081 | rtx xtarget = target; | |
1082 | rtx xspec_target = spec_target; | |
1083 | rtx xspec_target_subreg = spec_target_subreg; | |
1084 | rtx pat; | |
1085 | enum machine_mode maxmode | |
1086 | = insn_operand_mode[(int) CODE_FOR_extzv][0]; | |
1087 | ||
1088 | if (GET_CODE (xop0) == MEM) | |
1089 | { | |
1090 | int save_volatile_ok = volatile_ok; | |
1091 | volatile_ok = 1; | |
1092 | ||
1093 | /* Is the memory operand acceptable? */ | |
3bf1b082 JW |
1094 | if (! ((*insn_operand_predicate[(int) CODE_FOR_extzv][1]) |
1095 | (xop0, GET_MODE (xop0)))) | |
44037a66 TG |
1096 | { |
1097 | /* No, load into a reg and extract from there. */ | |
1098 | enum machine_mode bestmode; | |
1099 | ||
1100 | /* Get the mode to use for inserting into this field. If | |
1101 | OP0 is BLKmode, get the smallest mode consistent with the | |
1102 | alignment. If OP0 is a non-BLKmode object that is no | |
1103 | wider than MAXMODE, use its mode. Otherwise, use the | |
1104 | smallest mode containing the field. */ | |
1105 | ||
1106 | if (GET_MODE (xop0) == BLKmode | |
1107 | || (GET_MODE_SIZE (GET_MODE (op0)) | |
1108 | > GET_MODE_SIZE (maxmode))) | |
1109 | bestmode = get_best_mode (bitsize, bitnum, | |
1110 | align * BITS_PER_UNIT, maxmode, | |
717702e6 | 1111 | MEM_VOLATILE_P (xop0)); |
44037a66 TG |
1112 | else |
1113 | bestmode = GET_MODE (xop0); | |
1114 | ||
bd5d175a | 1115 | if (bestmode == VOIDmode |
5970d32e | 1116 | || (SLOW_UNALIGNED_ACCESS && GET_MODE_SIZE (bestmode) > align)) |
44037a66 TG |
1117 | goto extzv_loses; |
1118 | ||
1119 | /* Compute offset as multiple of this unit, | |
1120 | counting in bytes. */ | |
1121 | unit = GET_MODE_BITSIZE (bestmode); | |
1122 | xoffset = (bitnum / unit) * GET_MODE_SIZE (bestmode); | |
1123 | xbitpos = bitnum % unit; | |
1124 | xop0 = change_address (xop0, bestmode, | |
1125 | plus_constant (XEXP (xop0, 0), | |
1126 | xoffset)); | |
1127 | /* Fetch it to a register in that size. */ | |
1128 | xop0 = force_reg (bestmode, xop0); | |
1129 | ||
1130 | /* XBITPOS counts within UNIT, which is what is expected. */ | |
1131 | } | |
1132 | else | |
1133 | /* Get ref to first byte containing part of the field. */ | |
1134 | xop0 = change_address (xop0, byte_mode, | |
1135 | plus_constant (XEXP (xop0, 0), xoffset)); | |
1136 | ||
1137 | volatile_ok = save_volatile_ok; | |
1138 | } | |
1139 | ||
1140 | /* If op0 is a register, we need it in MAXMODE (which is usually | |
1141 | SImode). to make it acceptable to the format of extzv. */ | |
1142 | if (GET_CODE (xop0) == SUBREG && GET_MODE (xop0) != maxmode) | |
1143 | abort (); | |
1144 | if (GET_CODE (xop0) == REG && GET_MODE (xop0) != maxmode) | |
38a448ca | 1145 | xop0 = gen_rtx_SUBREG (maxmode, xop0, 0); |
44037a66 TG |
1146 | |
1147 | /* On big-endian machines, we count bits from the most significant. | |
1148 | If the bit field insn does not, we must invert. */ | |
f76b9db2 ILT |
1149 | if (BITS_BIG_ENDIAN != BYTES_BIG_ENDIAN) |
1150 | xbitpos = unit - bitsize - xbitpos; | |
1151 | ||
44037a66 | 1152 | /* Now convert from counting within UNIT to counting in MAXMODE. */ |
f76b9db2 | 1153 | if (BITS_BIG_ENDIAN && GET_CODE (xop0) != MEM) |
44037a66 | 1154 | xbitpos += GET_MODE_BITSIZE (maxmode) - unit; |
f76b9db2 | 1155 | |
44037a66 TG |
1156 | unit = GET_MODE_BITSIZE (maxmode); |
1157 | ||
1158 | if (xtarget == 0 | |
1159 | || (flag_force_mem && GET_CODE (xtarget) == MEM)) | |
1160 | xtarget = xspec_target = gen_reg_rtx (tmode); | |
1161 | ||
1162 | if (GET_MODE (xtarget) != maxmode) | |
1163 | { | |
1164 | if (GET_CODE (xtarget) == REG) | |
b7a09135 RS |
1165 | { |
1166 | int wider = (GET_MODE_SIZE (maxmode) | |
1167 | > GET_MODE_SIZE (GET_MODE (xtarget))); | |
1168 | xtarget = gen_lowpart (maxmode, xtarget); | |
1169 | if (wider) | |
1170 | xspec_target_subreg = xtarget; | |
1171 | } | |
44037a66 TG |
1172 | else |
1173 | xtarget = gen_reg_rtx (maxmode); | |
1174 | } | |
1175 | ||
1176 | /* If this machine's extzv insists on a register target, | |
1177 | make sure we have one. */ | |
1178 | if (! ((*insn_operand_predicate[(int) CODE_FOR_extzv][0]) | |
1179 | (xtarget, maxmode))) | |
1180 | xtarget = gen_reg_rtx (maxmode); | |
1181 | ||
b1ec3c92 CH |
1182 | bitsize_rtx = GEN_INT (bitsize); |
1183 | bitpos_rtx = GEN_INT (xbitpos); | |
44037a66 TG |
1184 | |
1185 | pat = gen_extzv (protect_from_queue (xtarget, 1), | |
1186 | xop0, bitsize_rtx, bitpos_rtx); | |
1187 | if (pat) | |
1188 | { | |
1189 | emit_insn (pat); | |
1190 | target = xtarget; | |
1191 | spec_target = xspec_target; | |
1192 | spec_target_subreg = xspec_target_subreg; | |
1193 | } | |
1194 | else | |
1195 | { | |
1196 | delete_insns_since (last); | |
1197 | target = extract_fixed_bit_field (tmode, op0, offset, bitsize, | |
1198 | bitpos, target, 1, align); | |
1199 | } | |
1200 | } | |
1201 | else | |
1202 | extzv_loses: | |
1203 | #endif | |
1204 | target = extract_fixed_bit_field (tmode, op0, offset, bitsize, bitpos, | |
1205 | target, 1, align); | |
1206 | } | |
1207 | else | |
1208 | { | |
1209 | #ifdef HAVE_extv | |
1210 | if (HAVE_extv | |
1211 | && (GET_MODE_BITSIZE (insn_operand_mode[(int) CODE_FOR_extv][0]) | |
39e0911f RK |
1212 | >= bitsize) |
1213 | && ! ((GET_CODE (op0) == REG || GET_CODE (op0) == SUBREG) | |
1214 | && (bitsize + bitpos | |
1215 | > GET_MODE_BITSIZE (insn_operand_mode[(int) CODE_FOR_extv][0])))) | |
44037a66 TG |
1216 | { |
1217 | int xbitpos = bitpos, xoffset = offset; | |
1218 | rtx bitsize_rtx, bitpos_rtx; | |
1219 | rtx last = get_last_insn(); | |
1220 | rtx xop0 = op0, xtarget = target; | |
1221 | rtx xspec_target = spec_target; | |
1222 | rtx xspec_target_subreg = spec_target_subreg; | |
1223 | rtx pat; | |
1224 | enum machine_mode maxmode | |
1225 | = insn_operand_mode[(int) CODE_FOR_extv][0]; | |
1226 | ||
1227 | if (GET_CODE (xop0) == MEM) | |
1228 | { | |
1229 | /* Is the memory operand acceptable? */ | |
1230 | if (! ((*insn_operand_predicate[(int) CODE_FOR_extv][1]) | |
1231 | (xop0, GET_MODE (xop0)))) | |
1232 | { | |
1233 | /* No, load into a reg and extract from there. */ | |
1234 | enum machine_mode bestmode; | |
1235 | ||
1236 | /* Get the mode to use for inserting into this field. If | |
1237 | OP0 is BLKmode, get the smallest mode consistent with the | |
1238 | alignment. If OP0 is a non-BLKmode object that is no | |
1239 | wider than MAXMODE, use its mode. Otherwise, use the | |
1240 | smallest mode containing the field. */ | |
1241 | ||
1242 | if (GET_MODE (xop0) == BLKmode | |
1243 | || (GET_MODE_SIZE (GET_MODE (op0)) | |
1244 | > GET_MODE_SIZE (maxmode))) | |
1245 | bestmode = get_best_mode (bitsize, bitnum, | |
1246 | align * BITS_PER_UNIT, maxmode, | |
717702e6 | 1247 | MEM_VOLATILE_P (xop0)); |
44037a66 TG |
1248 | else |
1249 | bestmode = GET_MODE (xop0); | |
1250 | ||
bd5d175a | 1251 | if (bestmode == VOIDmode |
5970d32e | 1252 | || (SLOW_UNALIGNED_ACCESS && GET_MODE_SIZE (bestmode) > align)) |
44037a66 TG |
1253 | goto extv_loses; |
1254 | ||
1255 | /* Compute offset as multiple of this unit, | |
1256 | counting in bytes. */ | |
1257 | unit = GET_MODE_BITSIZE (bestmode); | |
1258 | xoffset = (bitnum / unit) * GET_MODE_SIZE (bestmode); | |
1259 | xbitpos = bitnum % unit; | |
1260 | xop0 = change_address (xop0, bestmode, | |
1261 | plus_constant (XEXP (xop0, 0), | |
1262 | xoffset)); | |
1263 | /* Fetch it to a register in that size. */ | |
1264 | xop0 = force_reg (bestmode, xop0); | |
1265 | ||
1266 | /* XBITPOS counts within UNIT, which is what is expected. */ | |
1267 | } | |
1268 | else | |
1269 | /* Get ref to first byte containing part of the field. */ | |
1270 | xop0 = change_address (xop0, byte_mode, | |
1271 | plus_constant (XEXP (xop0, 0), xoffset)); | |
1272 | } | |
1273 | ||
1274 | /* If op0 is a register, we need it in MAXMODE (which is usually | |
1275 | SImode) to make it acceptable to the format of extv. */ | |
1276 | if (GET_CODE (xop0) == SUBREG && GET_MODE (xop0) != maxmode) | |
1277 | abort (); | |
1278 | if (GET_CODE (xop0) == REG && GET_MODE (xop0) != maxmode) | |
38a448ca | 1279 | xop0 = gen_rtx_SUBREG (maxmode, xop0, 0); |
44037a66 TG |
1280 | |
1281 | /* On big-endian machines, we count bits from the most significant. | |
1282 | If the bit field insn does not, we must invert. */ | |
f76b9db2 ILT |
1283 | if (BITS_BIG_ENDIAN != BYTES_BIG_ENDIAN) |
1284 | xbitpos = unit - bitsize - xbitpos; | |
1285 | ||
44037a66 TG |
1286 | /* XBITPOS counts within a size of UNIT. |
1287 | Adjust to count within a size of MAXMODE. */ | |
f76b9db2 | 1288 | if (BITS_BIG_ENDIAN && GET_CODE (xop0) != MEM) |
44037a66 | 1289 | xbitpos += (GET_MODE_BITSIZE (maxmode) - unit); |
f76b9db2 | 1290 | |
44037a66 TG |
1291 | unit = GET_MODE_BITSIZE (maxmode); |
1292 | ||
1293 | if (xtarget == 0 | |
1294 | || (flag_force_mem && GET_CODE (xtarget) == MEM)) | |
1295 | xtarget = xspec_target = gen_reg_rtx (tmode); | |
1296 | ||
1297 | if (GET_MODE (xtarget) != maxmode) | |
1298 | { | |
1299 | if (GET_CODE (xtarget) == REG) | |
b7a09135 RS |
1300 | { |
1301 | int wider = (GET_MODE_SIZE (maxmode) | |
1302 | > GET_MODE_SIZE (GET_MODE (xtarget))); | |
1303 | xtarget = gen_lowpart (maxmode, xtarget); | |
1304 | if (wider) | |
1305 | xspec_target_subreg = xtarget; | |
1306 | } | |
44037a66 TG |
1307 | else |
1308 | xtarget = gen_reg_rtx (maxmode); | |
1309 | } | |
1310 | ||
1311 | /* If this machine's extv insists on a register target, | |
1312 | make sure we have one. */ | |
1313 | if (! ((*insn_operand_predicate[(int) CODE_FOR_extv][0]) | |
1314 | (xtarget, maxmode))) | |
1315 | xtarget = gen_reg_rtx (maxmode); | |
1316 | ||
b1ec3c92 CH |
1317 | bitsize_rtx = GEN_INT (bitsize); |
1318 | bitpos_rtx = GEN_INT (xbitpos); | |
44037a66 TG |
1319 | |
1320 | pat = gen_extv (protect_from_queue (xtarget, 1), | |
1321 | xop0, bitsize_rtx, bitpos_rtx); | |
1322 | if (pat) | |
1323 | { | |
1324 | emit_insn (pat); | |
1325 | target = xtarget; | |
1326 | spec_target = xspec_target; | |
1327 | spec_target_subreg = xspec_target_subreg; | |
1328 | } | |
1329 | else | |
1330 | { | |
1331 | delete_insns_since (last); | |
1332 | target = extract_fixed_bit_field (tmode, op0, offset, bitsize, | |
1333 | bitpos, target, 0, align); | |
1334 | } | |
1335 | } | |
1336 | else | |
1337 | extv_loses: | |
1338 | #endif | |
1339 | target = extract_fixed_bit_field (tmode, op0, offset, bitsize, bitpos, | |
1340 | target, 0, align); | |
1341 | } | |
1342 | if (target == spec_target) | |
1343 | return target; | |
1344 | if (target == spec_target_subreg) | |
1345 | return spec_target; | |
1346 | if (GET_MODE (target) != tmode && GET_MODE (target) != mode) | |
1347 | { | |
1348 | /* If the target mode is floating-point, first convert to the | |
1349 | integer mode of that size and then access it as a floating-point | |
1350 | value via a SUBREG. */ | |
1351 | if (GET_MODE_CLASS (tmode) == MODE_FLOAT) | |
1352 | { | |
1353 | target = convert_to_mode (mode_for_size (GET_MODE_BITSIZE (tmode), | |
1354 | MODE_INT, 0), | |
1355 | target, unsignedp); | |
1356 | if (GET_CODE (target) != REG) | |
1357 | target = copy_to_reg (target); | |
38a448ca | 1358 | return gen_rtx_SUBREG (tmode, target, 0); |
44037a66 TG |
1359 | } |
1360 | else | |
1361 | return convert_to_mode (tmode, target, unsignedp); | |
1362 | } | |
1363 | return target; | |
1364 | } | |
1365 | \f | |
1366 | /* Extract a bit field using shifts and boolean operations | |
1367 | Returns an rtx to represent the value. | |
1368 | OP0 addresses a register (word) or memory (byte). | |
1369 | BITPOS says which bit within the word or byte the bit field starts in. | |
1370 | OFFSET says how many bytes farther the bit field starts; | |
1371 | it is 0 if OP0 is a register. | |
1372 | BITSIZE says how many bits long the bit field is. | |
1373 | (If OP0 is a register, it may be narrower than a full word, | |
1374 | but BITPOS still counts within a full word, | |
1375 | which is significant on bigendian machines.) | |
1376 | ||
1377 | UNSIGNEDP is nonzero for an unsigned bit field (don't sign-extend value). | |
1378 | If TARGET is nonzero, attempts to store the value there | |
1379 | and return TARGET, but this is not guaranteed. | |
1380 | If TARGET is not used, create a pseudo-reg of mode TMODE for the value. | |
1381 | ||
1382 | ALIGN is the alignment that STR_RTX is known to have, measured in bytes. */ | |
1383 | ||
1384 | static rtx | |
1385 | extract_fixed_bit_field (tmode, op0, offset, bitsize, bitpos, | |
1386 | target, unsignedp, align) | |
1387 | enum machine_mode tmode; | |
1388 | register rtx op0, target; | |
1389 | register int offset, bitsize, bitpos; | |
1390 | int unsignedp; | |
1391 | int align; | |
1392 | { | |
37811a73 | 1393 | int total_bits = BITS_PER_WORD; |
44037a66 TG |
1394 | enum machine_mode mode; |
1395 | ||
1396 | if (GET_CODE (op0) == SUBREG || GET_CODE (op0) == REG) | |
1397 | { | |
1398 | /* Special treatment for a bit field split across two registers. */ | |
1399 | if (bitsize + bitpos > BITS_PER_WORD) | |
1400 | return extract_split_bit_field (op0, bitsize, bitpos, | |
1401 | unsignedp, align); | |
1402 | } | |
1403 | else | |
1404 | { | |
1405 | /* Get the proper mode to use for this field. We want a mode that | |
1406 | includes the entire field. If such a mode would be larger than | |
1407 | a word, we won't be doing the extraction the normal way. */ | |
1408 | ||
1409 | mode = get_best_mode (bitsize, bitpos + offset * BITS_PER_UNIT, | |
1410 | align * BITS_PER_UNIT, word_mode, | |
1411 | GET_CODE (op0) == MEM && MEM_VOLATILE_P (op0)); | |
1412 | ||
1413 | if (mode == VOIDmode) | |
1414 | /* The only way this should occur is if the field spans word | |
1415 | boundaries. */ | |
1416 | return extract_split_bit_field (op0, bitsize, | |
1417 | bitpos + offset * BITS_PER_UNIT, | |
1418 | unsignedp, align); | |
1419 | ||
1420 | total_bits = GET_MODE_BITSIZE (mode); | |
1421 | ||
401db791 JW |
1422 | /* Make sure bitpos is valid for the chosen mode. Adjust BITPOS to |
1423 | be be in the range 0 to total_bits-1, and put any excess bytes in | |
1424 | OFFSET. */ | |
1425 | if (bitpos >= total_bits) | |
1426 | { | |
1427 | offset += (bitpos / total_bits) * (total_bits / BITS_PER_UNIT); | |
1428 | bitpos -= ((bitpos / total_bits) * (total_bits / BITS_PER_UNIT) | |
1429 | * BITS_PER_UNIT); | |
1430 | } | |
1431 | ||
44037a66 TG |
1432 | /* Get ref to an aligned byte, halfword, or word containing the field. |
1433 | Adjust BITPOS to be position within a word, | |
1434 | and OFFSET to be the offset of that word. | |
1435 | Then alter OP0 to refer to that word. */ | |
1436 | bitpos += (offset % (total_bits / BITS_PER_UNIT)) * BITS_PER_UNIT; | |
1437 | offset -= (offset % (total_bits / BITS_PER_UNIT)); | |
1438 | op0 = change_address (op0, mode, | |
1439 | plus_constant (XEXP (op0, 0), offset)); | |
1440 | } | |
1441 | ||
37811a73 RK |
1442 | mode = GET_MODE (op0); |
1443 | ||
f76b9db2 ILT |
1444 | if (BYTES_BIG_ENDIAN) |
1445 | { | |
1446 | /* BITPOS is the distance between our msb and that of OP0. | |
1447 | Convert it to the distance from the lsb. */ | |
1448 | ||
1449 | bitpos = total_bits - bitsize - bitpos; | |
1450 | } | |
44037a66 | 1451 | |
44037a66 TG |
1452 | /* Now BITPOS is always the distance between the field's lsb and that of OP0. |
1453 | We have reduced the big-endian case to the little-endian case. */ | |
1454 | ||
1455 | if (unsignedp) | |
1456 | { | |
1457 | if (bitpos) | |
1458 | { | |
1459 | /* If the field does not already start at the lsb, | |
1460 | shift it so it does. */ | |
1461 | tree amount = build_int_2 (bitpos, 0); | |
1462 | /* Maybe propagate the target for the shift. */ | |
1463 | /* But not if we will return it--could confuse integrate.c. */ | |
1464 | rtx subtarget = (target != 0 && GET_CODE (target) == REG | |
1465 | && !REG_FUNCTION_VALUE_P (target) | |
1466 | ? target : 0); | |
1467 | if (tmode != mode) subtarget = 0; | |
1468 | op0 = expand_shift (RSHIFT_EXPR, mode, op0, amount, subtarget, 1); | |
1469 | } | |
1470 | /* Convert the value to the desired mode. */ | |
1471 | if (mode != tmode) | |
1472 | op0 = convert_to_mode (tmode, op0, 1); | |
1473 | ||
1474 | /* Unless the msb of the field used to be the msb when we shifted, | |
1475 | mask out the upper bits. */ | |
1476 | ||
1477 | if (GET_MODE_BITSIZE (mode) != bitpos + bitsize | |
1478 | #if 0 | |
1479 | #ifdef SLOW_ZERO_EXTEND | |
1480 | /* Always generate an `and' if | |
1481 | we just zero-extended op0 and SLOW_ZERO_EXTEND, since it | |
0f41302f | 1482 | will combine fruitfully with the zero-extend. */ |
44037a66 TG |
1483 | || tmode != mode |
1484 | #endif | |
1485 | #endif | |
1486 | ) | |
1487 | return expand_binop (GET_MODE (op0), and_optab, op0, | |
1488 | mask_rtx (GET_MODE (op0), 0, bitsize, 0), | |
1489 | target, 1, OPTAB_LIB_WIDEN); | |
1490 | return op0; | |
1491 | } | |
1492 | ||
1493 | /* To extract a signed bit-field, first shift its msb to the msb of the word, | |
1494 | then arithmetic-shift its lsb to the lsb of the word. */ | |
1495 | op0 = force_reg (mode, op0); | |
1496 | if (mode != tmode) | |
1497 | target = 0; | |
1498 | ||
1499 | /* Find the narrowest integer mode that contains the field. */ | |
1500 | ||
1501 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT); mode != VOIDmode; | |
1502 | mode = GET_MODE_WIDER_MODE (mode)) | |
1503 | if (GET_MODE_BITSIZE (mode) >= bitsize + bitpos) | |
1504 | { | |
1505 | op0 = convert_to_mode (mode, op0, 0); | |
1506 | break; | |
1507 | } | |
1508 | ||
1509 | if (GET_MODE_BITSIZE (mode) != (bitsize + bitpos)) | |
1510 | { | |
1511 | tree amount = build_int_2 (GET_MODE_BITSIZE (mode) - (bitsize + bitpos), 0); | |
1512 | /* Maybe propagate the target for the shift. */ | |
1513 | /* But not if we will return the result--could confuse integrate.c. */ | |
1514 | rtx subtarget = (target != 0 && GET_CODE (target) == REG | |
1515 | && ! REG_FUNCTION_VALUE_P (target) | |
1516 | ? target : 0); | |
1517 | op0 = expand_shift (LSHIFT_EXPR, mode, op0, amount, subtarget, 1); | |
1518 | } | |
1519 | ||
1520 | return expand_shift (RSHIFT_EXPR, mode, op0, | |
1521 | build_int_2 (GET_MODE_BITSIZE (mode) - bitsize, 0), | |
1522 | target, 0); | |
1523 | } | |
1524 | \f | |
1525 | /* Return a constant integer (CONST_INT or CONST_DOUBLE) mask value | |
1526 | of mode MODE with BITSIZE ones followed by BITPOS zeros, or the | |
1527 | complement of that if COMPLEMENT. The mask is truncated if | |
77295dec DE |
1528 | necessary to the width of mode MODE. The mask is zero-extended if |
1529 | BITSIZE+BITPOS is too small for MODE. */ | |
44037a66 TG |
1530 | |
1531 | static rtx | |
1532 | mask_rtx (mode, bitpos, bitsize, complement) | |
1533 | enum machine_mode mode; | |
1534 | int bitpos, bitsize, complement; | |
1535 | { | |
b1ec3c92 | 1536 | HOST_WIDE_INT masklow, maskhigh; |
44037a66 | 1537 | |
b1ec3c92 CH |
1538 | if (bitpos < HOST_BITS_PER_WIDE_INT) |
1539 | masklow = (HOST_WIDE_INT) -1 << bitpos; | |
44037a66 TG |
1540 | else |
1541 | masklow = 0; | |
1542 | ||
b1ec3c92 CH |
1543 | if (bitpos + bitsize < HOST_BITS_PER_WIDE_INT) |
1544 | masklow &= ((unsigned HOST_WIDE_INT) -1 | |
1545 | >> (HOST_BITS_PER_WIDE_INT - bitpos - bitsize)); | |
44037a66 | 1546 | |
b1ec3c92 | 1547 | if (bitpos <= HOST_BITS_PER_WIDE_INT) |
44037a66 TG |
1548 | maskhigh = -1; |
1549 | else | |
b1ec3c92 | 1550 | maskhigh = (HOST_WIDE_INT) -1 << (bitpos - HOST_BITS_PER_WIDE_INT); |
44037a66 | 1551 | |
b1ec3c92 CH |
1552 | if (bitpos + bitsize > HOST_BITS_PER_WIDE_INT) |
1553 | maskhigh &= ((unsigned HOST_WIDE_INT) -1 | |
1554 | >> (2 * HOST_BITS_PER_WIDE_INT - bitpos - bitsize)); | |
44037a66 TG |
1555 | else |
1556 | maskhigh = 0; | |
1557 | ||
1558 | if (complement) | |
1559 | { | |
1560 | maskhigh = ~maskhigh; | |
1561 | masklow = ~masklow; | |
1562 | } | |
1563 | ||
1564 | return immed_double_const (masklow, maskhigh, mode); | |
1565 | } | |
1566 | ||
1567 | /* Return a constant integer (CONST_INT or CONST_DOUBLE) rtx with the value | |
1568 | VALUE truncated to BITSIZE bits and then shifted left BITPOS bits. */ | |
1569 | ||
1570 | static rtx | |
1571 | lshift_value (mode, value, bitpos, bitsize) | |
1572 | enum machine_mode mode; | |
1573 | rtx value; | |
1574 | int bitpos, bitsize; | |
1575 | { | |
b1ec3c92 CH |
1576 | unsigned HOST_WIDE_INT v = INTVAL (value); |
1577 | HOST_WIDE_INT low, high; | |
44037a66 | 1578 | |
b1ec3c92 CH |
1579 | if (bitsize < HOST_BITS_PER_WIDE_INT) |
1580 | v &= ~((HOST_WIDE_INT) -1 << bitsize); | |
44037a66 | 1581 | |
b1ec3c92 | 1582 | if (bitpos < HOST_BITS_PER_WIDE_INT) |
44037a66 TG |
1583 | { |
1584 | low = v << bitpos; | |
b1ec3c92 | 1585 | high = (bitpos > 0 ? (v >> (HOST_BITS_PER_WIDE_INT - bitpos)) : 0); |
44037a66 TG |
1586 | } |
1587 | else | |
1588 | { | |
1589 | low = 0; | |
b1ec3c92 | 1590 | high = v << (bitpos - HOST_BITS_PER_WIDE_INT); |
44037a66 TG |
1591 | } |
1592 | ||
1593 | return immed_double_const (low, high, mode); | |
1594 | } | |
1595 | \f | |
1596 | /* Extract a bit field that is split across two words | |
1597 | and return an RTX for the result. | |
1598 | ||
1599 | OP0 is the REG, SUBREG or MEM rtx for the first of the two words. | |
1600 | BITSIZE is the field width; BITPOS, position of its first bit, in the word. | |
06c94bce RS |
1601 | UNSIGNEDP is 1 if should zero-extend the contents; else sign-extend. |
1602 | ||
1603 | ALIGN is the known alignment of OP0, measured in bytes. | |
1604 | This is also the size of the memory objects to be used. */ | |
44037a66 TG |
1605 | |
1606 | static rtx | |
1607 | extract_split_bit_field (op0, bitsize, bitpos, unsignedp, align) | |
1608 | rtx op0; | |
1609 | int bitsize, bitpos, unsignedp, align; | |
1610 | { | |
4ee16841 | 1611 | int unit; |
06c94bce RS |
1612 | int bitsdone = 0; |
1613 | rtx result; | |
1614 | int first = 1; | |
44037a66 | 1615 | |
4ee16841 DE |
1616 | /* Make sure UNIT isn't larger than BITS_PER_WORD, we can only handle that |
1617 | much at a time. */ | |
1618 | if (GET_CODE (op0) == REG || GET_CODE (op0) == SUBREG) | |
1619 | unit = BITS_PER_WORD; | |
1620 | else | |
1621 | unit = MIN (align * BITS_PER_UNIT, BITS_PER_WORD); | |
1622 | ||
06c94bce RS |
1623 | while (bitsdone < bitsize) |
1624 | { | |
1625 | int thissize; | |
1626 | rtx part, word; | |
1627 | int thispos; | |
1628 | int offset; | |
1629 | ||
1630 | offset = (bitpos + bitsdone) / unit; | |
1631 | thispos = (bitpos + bitsdone) % unit; | |
1632 | ||
0eb61c19 DE |
1633 | /* THISSIZE must not overrun a word boundary. Otherwise, |
1634 | extract_fixed_bit_field will call us again, and we will mutually | |
1635 | recurse forever. */ | |
1636 | thissize = MIN (bitsize - bitsdone, BITS_PER_WORD); | |
1637 | thissize = MIN (thissize, unit - thispos); | |
06c94bce RS |
1638 | |
1639 | /* If OP0 is a register, then handle OFFSET here. | |
5f57dff0 JW |
1640 | |
1641 | When handling multiword bitfields, extract_bit_field may pass | |
1642 | down a word_mode SUBREG of a larger REG for a bitfield that actually | |
1643 | crosses a word boundary. Thus, for a SUBREG, we must find | |
1644 | the current word starting from the base register. */ | |
1645 | if (GET_CODE (op0) == SUBREG) | |
1646 | { | |
1647 | word = operand_subword_force (SUBREG_REG (op0), | |
1648 | SUBREG_WORD (op0) + offset, | |
1649 | GET_MODE (SUBREG_REG (op0))); | |
1650 | offset = 0; | |
1651 | } | |
1652 | else if (GET_CODE (op0) == REG) | |
06c94bce RS |
1653 | { |
1654 | word = operand_subword_force (op0, offset, GET_MODE (op0)); | |
1655 | offset = 0; | |
1656 | } | |
1657 | else | |
1658 | word = op0; | |
1659 | ||
06c94bce | 1660 | /* Extract the parts in bit-counting order, |
0eb61c19 DE |
1661 | whose meaning is determined by BYTES_PER_UNIT. |
1662 | OFFSET is in UNITs, and UNIT is in bits. | |
1663 | extract_fixed_bit_field wants offset in bytes. */ | |
1664 | part = extract_fixed_bit_field (word_mode, word, | |
1665 | offset * unit / BITS_PER_UNIT, | |
06c94bce RS |
1666 | thissize, thispos, 0, 1, align); |
1667 | bitsdone += thissize; | |
44037a66 | 1668 | |
06c94bce | 1669 | /* Shift this part into place for the result. */ |
f76b9db2 ILT |
1670 | if (BYTES_BIG_ENDIAN) |
1671 | { | |
1672 | if (bitsize != bitsdone) | |
1673 | part = expand_shift (LSHIFT_EXPR, word_mode, part, | |
1674 | build_int_2 (bitsize - bitsdone, 0), 0, 1); | |
1675 | } | |
1676 | else | |
1677 | { | |
1678 | if (bitsdone != thissize) | |
1679 | part = expand_shift (LSHIFT_EXPR, word_mode, part, | |
1680 | build_int_2 (bitsdone - thissize, 0), 0, 1); | |
1681 | } | |
44037a66 | 1682 | |
06c94bce RS |
1683 | if (first) |
1684 | result = part; | |
1685 | else | |
1686 | /* Combine the parts with bitwise or. This works | |
1687 | because we extracted each part as an unsigned bit field. */ | |
1688 | result = expand_binop (word_mode, ior_optab, part, result, NULL_RTX, 1, | |
1689 | OPTAB_LIB_WIDEN); | |
1690 | ||
1691 | first = 0; | |
1692 | } | |
44037a66 TG |
1693 | |
1694 | /* Unsigned bit field: we are done. */ | |
1695 | if (unsignedp) | |
1696 | return result; | |
1697 | /* Signed bit field: sign-extend with two arithmetic shifts. */ | |
1698 | result = expand_shift (LSHIFT_EXPR, word_mode, result, | |
b1ec3c92 CH |
1699 | build_int_2 (BITS_PER_WORD - bitsize, 0), |
1700 | NULL_RTX, 0); | |
44037a66 | 1701 | return expand_shift (RSHIFT_EXPR, word_mode, result, |
b1ec3c92 | 1702 | build_int_2 (BITS_PER_WORD - bitsize, 0), NULL_RTX, 0); |
44037a66 TG |
1703 | } |
1704 | \f | |
1705 | /* Add INC into TARGET. */ | |
1706 | ||
1707 | void | |
1708 | expand_inc (target, inc) | |
1709 | rtx target, inc; | |
1710 | { | |
1711 | rtx value = expand_binop (GET_MODE (target), add_optab, | |
1712 | target, inc, | |
1713 | target, 0, OPTAB_LIB_WIDEN); | |
1714 | if (value != target) | |
1715 | emit_move_insn (target, value); | |
1716 | } | |
1717 | ||
1718 | /* Subtract DEC from TARGET. */ | |
1719 | ||
1720 | void | |
1721 | expand_dec (target, dec) | |
1722 | rtx target, dec; | |
1723 | { | |
1724 | rtx value = expand_binop (GET_MODE (target), sub_optab, | |
1725 | target, dec, | |
1726 | target, 0, OPTAB_LIB_WIDEN); | |
1727 | if (value != target) | |
1728 | emit_move_insn (target, value); | |
1729 | } | |
1730 | \f | |
1731 | /* Output a shift instruction for expression code CODE, | |
1732 | with SHIFTED being the rtx for the value to shift, | |
1733 | and AMOUNT the tree for the amount to shift by. | |
1734 | Store the result in the rtx TARGET, if that is convenient. | |
1735 | If UNSIGNEDP is nonzero, do a logical shift; otherwise, arithmetic. | |
1736 | Return the rtx for where the value is. */ | |
1737 | ||
1738 | rtx | |
1739 | expand_shift (code, mode, shifted, amount, target, unsignedp) | |
1740 | enum tree_code code; | |
1741 | register enum machine_mode mode; | |
1742 | rtx shifted; | |
1743 | tree amount; | |
1744 | register rtx target; | |
1745 | int unsignedp; | |
1746 | { | |
1747 | register rtx op1, temp = 0; | |
1748 | register int left = (code == LSHIFT_EXPR || code == LROTATE_EXPR); | |
1749 | register int rotate = (code == LROTATE_EXPR || code == RROTATE_EXPR); | |
1750 | int try; | |
1751 | ||
1752 | /* Previously detected shift-counts computed by NEGATE_EXPR | |
1753 | and shifted in the other direction; but that does not work | |
1754 | on all machines. */ | |
1755 | ||
b1ec3c92 | 1756 | op1 = expand_expr (amount, NULL_RTX, VOIDmode, 0); |
44037a66 | 1757 | |
1433f0f9 | 1758 | #ifdef SHIFT_COUNT_TRUNCATED |
166cdf4a RH |
1759 | if (SHIFT_COUNT_TRUNCATED) |
1760 | { | |
1761 | if (GET_CODE (op1) == CONST_INT | |
1762 | && (unsigned HOST_WIDE_INT) INTVAL (op1) >= GET_MODE_BITSIZE (mode)) | |
1763 | op1 = GEN_INT ((unsigned HOST_WIDE_INT) INTVAL (op1) | |
1764 | % GET_MODE_BITSIZE (mode)); | |
1765 | else if (GET_CODE (op1) == SUBREG | |
1766 | && SUBREG_WORD (op1) == 0) | |
1767 | op1 = SUBREG_REG (op1); | |
1768 | } | |
2ab0a5c4 TG |
1769 | #endif |
1770 | ||
44037a66 TG |
1771 | if (op1 == const0_rtx) |
1772 | return shifted; | |
1773 | ||
1774 | for (try = 0; temp == 0 && try < 3; try++) | |
1775 | { | |
1776 | enum optab_methods methods; | |
1777 | ||
1778 | if (try == 0) | |
1779 | methods = OPTAB_DIRECT; | |
1780 | else if (try == 1) | |
1781 | methods = OPTAB_WIDEN; | |
1782 | else | |
1783 | methods = OPTAB_LIB_WIDEN; | |
1784 | ||
1785 | if (rotate) | |
1786 | { | |
1787 | /* Widening does not work for rotation. */ | |
1788 | if (methods == OPTAB_WIDEN) | |
1789 | continue; | |
1790 | else if (methods == OPTAB_LIB_WIDEN) | |
cbec710e | 1791 | { |
39e71615 | 1792 | /* If we have been unable to open-code this by a rotation, |
cbec710e RK |
1793 | do it as the IOR of two shifts. I.e., to rotate A |
1794 | by N bits, compute (A << N) | ((unsigned) A >> (C - N)) | |
1795 | where C is the bitsize of A. | |
1796 | ||
1797 | It is theoretically possible that the target machine might | |
1798 | not be able to perform either shift and hence we would | |
1799 | be making two libcalls rather than just the one for the | |
1800 | shift (similarly if IOR could not be done). We will allow | |
1801 | this extremely unlikely lossage to avoid complicating the | |
1802 | code below. */ | |
1803 | ||
39e71615 RK |
1804 | rtx subtarget = target == shifted ? 0 : target; |
1805 | rtx temp1; | |
1806 | tree type = TREE_TYPE (amount); | |
1807 | tree new_amount = make_tree (type, op1); | |
1808 | tree other_amount | |
1809 | = fold (build (MINUS_EXPR, type, | |
1810 | convert (type, | |
1811 | build_int_2 (GET_MODE_BITSIZE (mode), | |
1812 | 0)), | |
1813 | amount)); | |
1814 | ||
1815 | shifted = force_reg (mode, shifted); | |
1816 | ||
1817 | temp = expand_shift (left ? LSHIFT_EXPR : RSHIFT_EXPR, | |
1818 | mode, shifted, new_amount, subtarget, 1); | |
1819 | temp1 = expand_shift (left ? RSHIFT_EXPR : LSHIFT_EXPR, | |
1820 | mode, shifted, other_amount, 0, 1); | |
1821 | return expand_binop (mode, ior_optab, temp, temp1, target, | |
1822 | unsignedp, methods); | |
cbec710e | 1823 | } |
44037a66 TG |
1824 | |
1825 | temp = expand_binop (mode, | |
1826 | left ? rotl_optab : rotr_optab, | |
1827 | shifted, op1, target, unsignedp, methods); | |
cbec710e RK |
1828 | |
1829 | /* If we don't have the rotate, but we are rotating by a constant | |
1830 | that is in range, try a rotate in the opposite direction. */ | |
1831 | ||
1832 | if (temp == 0 && GET_CODE (op1) == CONST_INT | |
1833 | && INTVAL (op1) > 0 && INTVAL (op1) < GET_MODE_BITSIZE (mode)) | |
1834 | temp = expand_binop (mode, | |
1835 | left ? rotr_optab : rotl_optab, | |
1836 | shifted, | |
1837 | GEN_INT (GET_MODE_BITSIZE (mode) | |
1838 | - INTVAL (op1)), | |
1839 | target, unsignedp, methods); | |
44037a66 TG |
1840 | } |
1841 | else if (unsignedp) | |
a34958c9 RK |
1842 | temp = expand_binop (mode, |
1843 | left ? ashl_optab : lshr_optab, | |
1844 | shifted, op1, target, unsignedp, methods); | |
44037a66 TG |
1845 | |
1846 | /* Do arithmetic shifts. | |
1847 | Also, if we are going to widen the operand, we can just as well | |
1848 | use an arithmetic right-shift instead of a logical one. */ | |
1849 | if (temp == 0 && ! rotate | |
1850 | && (! unsignedp || (! left && methods == OPTAB_WIDEN))) | |
1851 | { | |
1852 | enum optab_methods methods1 = methods; | |
1853 | ||
1854 | /* If trying to widen a log shift to an arithmetic shift, | |
1855 | don't accept an arithmetic shift of the same size. */ | |
1856 | if (unsignedp) | |
1857 | methods1 = OPTAB_MUST_WIDEN; | |
1858 | ||
1859 | /* Arithmetic shift */ | |
1860 | ||
1861 | temp = expand_binop (mode, | |
1862 | left ? ashl_optab : ashr_optab, | |
1863 | shifted, op1, target, unsignedp, methods1); | |
1864 | } | |
1865 | ||
711a5e64 RK |
1866 | /* We used to try extzv here for logical right shifts, but that was |
1867 | only useful for one machine, the VAX, and caused poor code | |
1868 | generation there for lshrdi3, so the code was deleted and a | |
1869 | define_expand for lshrsi3 was added to vax.md. */ | |
44037a66 TG |
1870 | } |
1871 | ||
1872 | if (temp == 0) | |
1873 | abort (); | |
1874 | return temp; | |
1875 | } | |
1876 | \f | |
b385aeda | 1877 | enum alg_code { alg_zero, alg_m, alg_shift, |
b2fb324c | 1878 | alg_add_t_m2, alg_sub_t_m2, |
7963ac37 RK |
1879 | alg_add_factor, alg_sub_factor, |
1880 | alg_add_t2_m, alg_sub_t2_m, | |
b385aeda | 1881 | alg_add, alg_subtract, alg_factor, alg_shiftop }; |
44037a66 TG |
1882 | |
1883 | /* This structure records a sequence of operations. | |
1884 | `ops' is the number of operations recorded. | |
1885 | `cost' is their total cost. | |
1886 | The operations are stored in `op' and the corresponding | |
b385aeda RK |
1887 | logarithms of the integer coefficients in `log'. |
1888 | ||
44037a66 | 1889 | These are the operations: |
b385aeda RK |
1890 | alg_zero total := 0; |
1891 | alg_m total := multiplicand; | |
b2fb324c | 1892 | alg_shift total := total * coeff |
7963ac37 RK |
1893 | alg_add_t_m2 total := total + multiplicand * coeff; |
1894 | alg_sub_t_m2 total := total - multiplicand * coeff; | |
1895 | alg_add_factor total := total * coeff + total; | |
1896 | alg_sub_factor total := total * coeff - total; | |
1897 | alg_add_t2_m total := total * coeff + multiplicand; | |
1898 | alg_sub_t2_m total := total * coeff - multiplicand; | |
b385aeda RK |
1899 | |
1900 | The first operand must be either alg_zero or alg_m. */ | |
44037a66 | 1901 | |
44037a66 TG |
1902 | struct algorithm |
1903 | { | |
7963ac37 RK |
1904 | short cost; |
1905 | short ops; | |
b385aeda RK |
1906 | /* The size of the OP and LOG fields are not directly related to the |
1907 | word size, but the worst-case algorithms will be if we have few | |
1908 | consecutive ones or zeros, i.e., a multiplicand like 10101010101... | |
1909 | In that case we will generate shift-by-2, add, shift-by-2, add,..., | |
1910 | in total wordsize operations. */ | |
44037a66 | 1911 | enum alg_code op[MAX_BITS_PER_WORD]; |
b385aeda | 1912 | char log[MAX_BITS_PER_WORD]; |
44037a66 TG |
1913 | }; |
1914 | ||
1915 | /* Compute and return the best algorithm for multiplying by T. | |
7963ac37 RK |
1916 | The algorithm must cost less than cost_limit |
1917 | If retval.cost >= COST_LIMIT, no algorithm was found and all | |
1918 | other field of the returned struct are undefined. */ | |
44037a66 | 1919 | |
819126a6 RK |
1920 | static void |
1921 | synth_mult (alg_out, t, cost_limit) | |
1922 | struct algorithm *alg_out; | |
b1ec3c92 | 1923 | unsigned HOST_WIDE_INT t; |
7963ac37 | 1924 | int cost_limit; |
44037a66 | 1925 | { |
b2fb324c | 1926 | int m; |
52786026 | 1927 | struct algorithm *alg_in, *best_alg; |
44037a66 | 1928 | unsigned int cost; |
b2fb324c | 1929 | unsigned HOST_WIDE_INT q; |
44037a66 | 1930 | |
7963ac37 RK |
1931 | /* Indicate that no algorithm is yet found. If no algorithm |
1932 | is found, this value will be returned and indicate failure. */ | |
819126a6 | 1933 | alg_out->cost = cost_limit; |
44037a66 | 1934 | |
b2fb324c | 1935 | if (cost_limit <= 0) |
819126a6 | 1936 | return; |
44037a66 | 1937 | |
b385aeda RK |
1938 | /* t == 1 can be done in zero cost. */ |
1939 | if (t == 1) | |
b2fb324c | 1940 | { |
819126a6 RK |
1941 | alg_out->ops = 1; |
1942 | alg_out->cost = 0; | |
1943 | alg_out->op[0] = alg_m; | |
1944 | return; | |
b2fb324c RK |
1945 | } |
1946 | ||
b385aeda RK |
1947 | /* t == 0 sometimes has a cost. If it does and it exceeds our limit, |
1948 | fail now. */ | |
819126a6 | 1949 | if (t == 0) |
b385aeda RK |
1950 | { |
1951 | if (zero_cost >= cost_limit) | |
819126a6 | 1952 | return; |
b385aeda RK |
1953 | else |
1954 | { | |
819126a6 RK |
1955 | alg_out->ops = 1; |
1956 | alg_out->cost = zero_cost; | |
1957 | alg_out->op[0] = alg_zero; | |
1958 | return; | |
b385aeda RK |
1959 | } |
1960 | } | |
1961 | ||
52786026 RK |
1962 | /* We'll be needing a couple extra algorithm structures now. */ |
1963 | ||
1964 | alg_in = (struct algorithm *)alloca (sizeof (struct algorithm)); | |
1965 | best_alg = (struct algorithm *)alloca (sizeof (struct algorithm)); | |
1966 | ||
b385aeda RK |
1967 | /* If we have a group of zero bits at the low-order part of T, try |
1968 | multiplying by the remaining bits and then doing a shift. */ | |
1969 | ||
b2fb324c | 1970 | if ((t & 1) == 0) |
44037a66 | 1971 | { |
b2fb324c RK |
1972 | m = floor_log2 (t & -t); /* m = number of low zero bits */ |
1973 | q = t >> m; | |
1974 | cost = shift_cost[m]; | |
819126a6 RK |
1975 | synth_mult (alg_in, q, cost_limit - cost); |
1976 | ||
1977 | cost += alg_in->cost; | |
b2fb324c | 1978 | if (cost < cost_limit) |
44037a66 | 1979 | { |
819126a6 RK |
1980 | struct algorithm *x; |
1981 | x = alg_in, alg_in = best_alg, best_alg = x; | |
1982 | best_alg->log[best_alg->ops] = m; | |
1983 | best_alg->op[best_alg->ops] = alg_shift; | |
1984 | cost_limit = cost; | |
1985 | } | |
1986 | } | |
1987 | ||
1988 | /* If we have an odd number, add or subtract one. */ | |
1989 | if ((t & 1) != 0) | |
1990 | { | |
1991 | unsigned HOST_WIDE_INT w; | |
1992 | ||
1993 | for (w = 1; (w & t) != 0; w <<= 1) | |
1994 | ; | |
1995 | if (w > 2 | |
1996 | /* Reject the case where t is 3. | |
1997 | Thus we prefer addition in that case. */ | |
1998 | && t != 3) | |
1999 | { | |
2000 | /* T ends with ...111. Multiply by (T + 1) and subtract 1. */ | |
2001 | ||
2002 | cost = add_cost; | |
2003 | synth_mult (alg_in, t + 1, cost_limit - cost); | |
b2fb324c RK |
2004 | |
2005 | cost += alg_in->cost; | |
819126a6 | 2006 | if (cost < cost_limit) |
44037a66 | 2007 | { |
b2fb324c RK |
2008 | struct algorithm *x; |
2009 | x = alg_in, alg_in = best_alg, best_alg = x; | |
819126a6 RK |
2010 | best_alg->log[best_alg->ops] = 0; |
2011 | best_alg->op[best_alg->ops] = alg_sub_t_m2; | |
2012 | cost_limit = cost; | |
44037a66 | 2013 | } |
44037a66 | 2014 | } |
819126a6 RK |
2015 | else |
2016 | { | |
2017 | /* T ends with ...01 or ...011. Multiply by (T - 1) and add 1. */ | |
44037a66 | 2018 | |
819126a6 RK |
2019 | cost = add_cost; |
2020 | synth_mult (alg_in, t - 1, cost_limit - cost); | |
2021 | ||
2022 | cost += alg_in->cost; | |
2023 | if (cost < cost_limit) | |
2024 | { | |
2025 | struct algorithm *x; | |
2026 | x = alg_in, alg_in = best_alg, best_alg = x; | |
2027 | best_alg->log[best_alg->ops] = 0; | |
2028 | best_alg->op[best_alg->ops] = alg_add_t_m2; | |
2029 | cost_limit = cost; | |
2030 | } | |
2031 | } | |
2032 | } | |
63610db9 | 2033 | |
44037a66 | 2034 | /* Look for factors of t of the form |
7963ac37 | 2035 | t = q(2**m +- 1), 2 <= m <= floor(log2(t - 1)). |
44037a66 | 2036 | If we find such a factor, we can multiply by t using an algorithm that |
7963ac37 | 2037 | multiplies by q, shift the result by m and add/subtract it to itself. |
44037a66 | 2038 | |
7963ac37 RK |
2039 | We search for large factors first and loop down, even if large factors |
2040 | are less probable than small; if we find a large factor we will find a | |
2041 | good sequence quickly, and therefore be able to prune (by decreasing | |
2042 | COST_LIMIT) the search. */ | |
2043 | ||
2044 | for (m = floor_log2 (t - 1); m >= 2; m--) | |
44037a66 | 2045 | { |
7963ac37 | 2046 | unsigned HOST_WIDE_INT d; |
44037a66 | 2047 | |
7963ac37 RK |
2048 | d = ((unsigned HOST_WIDE_INT) 1 << m) + 1; |
2049 | if (t % d == 0 && t > d) | |
44037a66 | 2050 | { |
b385aeda | 2051 | cost = MIN (shiftadd_cost[m], add_cost + shift_cost[m]); |
819126a6 | 2052 | synth_mult (alg_in, t / d, cost_limit - cost); |
44037a66 | 2053 | |
7963ac37 | 2054 | cost += alg_in->cost; |
819126a6 | 2055 | if (cost < cost_limit) |
44037a66 | 2056 | { |
7963ac37 RK |
2057 | struct algorithm *x; |
2058 | x = alg_in, alg_in = best_alg, best_alg = x; | |
b385aeda | 2059 | best_alg->log[best_alg->ops] = m; |
819126a6 RK |
2060 | best_alg->op[best_alg->ops] = alg_add_factor; |
2061 | cost_limit = cost; | |
44037a66 | 2062 | } |
c0b262c1 TG |
2063 | /* Other factors will have been taken care of in the recursion. */ |
2064 | break; | |
44037a66 TG |
2065 | } |
2066 | ||
7963ac37 RK |
2067 | d = ((unsigned HOST_WIDE_INT) 1 << m) - 1; |
2068 | if (t % d == 0 && t > d) | |
44037a66 | 2069 | { |
b385aeda | 2070 | cost = MIN (shiftsub_cost[m], add_cost + shift_cost[m]); |
819126a6 | 2071 | synth_mult (alg_in, t / d, cost_limit - cost); |
44037a66 | 2072 | |
7963ac37 | 2073 | cost += alg_in->cost; |
819126a6 | 2074 | if (cost < cost_limit) |
44037a66 | 2075 | { |
7963ac37 RK |
2076 | struct algorithm *x; |
2077 | x = alg_in, alg_in = best_alg, best_alg = x; | |
b385aeda | 2078 | best_alg->log[best_alg->ops] = m; |
819126a6 RK |
2079 | best_alg->op[best_alg->ops] = alg_sub_factor; |
2080 | cost_limit = cost; | |
44037a66 | 2081 | } |
c0b262c1 | 2082 | break; |
44037a66 TG |
2083 | } |
2084 | } | |
2085 | ||
7963ac37 RK |
2086 | /* Try shift-and-add (load effective address) instructions, |
2087 | i.e. do a*3, a*5, a*9. */ | |
2088 | if ((t & 1) != 0) | |
2089 | { | |
7963ac37 RK |
2090 | q = t - 1; |
2091 | q = q & -q; | |
2092 | m = exact_log2 (q); | |
5eebe2eb | 2093 | if (m >= 0) |
b385aeda | 2094 | { |
5eebe2eb | 2095 | cost = shiftadd_cost[m]; |
819126a6 | 2096 | synth_mult (alg_in, (t - 1) >> m, cost_limit - cost); |
5eebe2eb RK |
2097 | |
2098 | cost += alg_in->cost; | |
819126a6 | 2099 | if (cost < cost_limit) |
5eebe2eb RK |
2100 | { |
2101 | struct algorithm *x; | |
2102 | x = alg_in, alg_in = best_alg, best_alg = x; | |
2103 | best_alg->log[best_alg->ops] = m; | |
819126a6 RK |
2104 | best_alg->op[best_alg->ops] = alg_add_t2_m; |
2105 | cost_limit = cost; | |
5eebe2eb | 2106 | } |
7963ac37 | 2107 | } |
44037a66 | 2108 | |
7963ac37 RK |
2109 | q = t + 1; |
2110 | q = q & -q; | |
2111 | m = exact_log2 (q); | |
5eebe2eb | 2112 | if (m >= 0) |
b385aeda | 2113 | { |
5eebe2eb | 2114 | cost = shiftsub_cost[m]; |
819126a6 | 2115 | synth_mult (alg_in, (t + 1) >> m, cost_limit - cost); |
5eebe2eb RK |
2116 | |
2117 | cost += alg_in->cost; | |
819126a6 | 2118 | if (cost < cost_limit) |
5eebe2eb RK |
2119 | { |
2120 | struct algorithm *x; | |
2121 | x = alg_in, alg_in = best_alg, best_alg = x; | |
2122 | best_alg->log[best_alg->ops] = m; | |
819126a6 RK |
2123 | best_alg->op[best_alg->ops] = alg_sub_t2_m; |
2124 | cost_limit = cost; | |
5eebe2eb | 2125 | } |
7963ac37 RK |
2126 | } |
2127 | } | |
44037a66 | 2128 | |
819126a6 RK |
2129 | /* If cost_limit has not decreased since we stored it in alg_out->cost, |
2130 | we have not found any algorithm. */ | |
2131 | if (cost_limit == alg_out->cost) | |
2132 | return; | |
2133 | ||
52786026 RK |
2134 | /* If we are getting a too long sequence for `struct algorithm' |
2135 | to record, make this search fail. */ | |
2136 | if (best_alg->ops == MAX_BITS_PER_WORD) | |
2137 | return; | |
2138 | ||
819126a6 RK |
2139 | /* Copy the algorithm from temporary space to the space at alg_out. |
2140 | We avoid using structure assignment because the majority of | |
2141 | best_alg is normally undefined, and this is a critical function. */ | |
2142 | alg_out->ops = best_alg->ops + 1; | |
2143 | alg_out->cost = cost_limit; | |
4c9a05bc RK |
2144 | bcopy ((char *) best_alg->op, (char *) alg_out->op, |
2145 | alg_out->ops * sizeof *alg_out->op); | |
2146 | bcopy ((char *) best_alg->log, (char *) alg_out->log, | |
2147 | alg_out->ops * sizeof *alg_out->log); | |
44037a66 TG |
2148 | } |
2149 | \f | |
2150 | /* Perform a multiplication and return an rtx for the result. | |
2151 | MODE is mode of value; OP0 and OP1 are what to multiply (rtx's); | |
2152 | TARGET is a suggestion for where to store the result (an rtx). | |
2153 | ||
2154 | We check specially for a constant integer as OP1. | |
2155 | If you want this check for OP0 as well, then before calling | |
2156 | you should swap the two operands if OP0 would be constant. */ | |
2157 | ||
2158 | rtx | |
2159 | expand_mult (mode, op0, op1, target, unsignedp) | |
2160 | enum machine_mode mode; | |
2161 | register rtx op0, op1, target; | |
2162 | int unsignedp; | |
2163 | { | |
2164 | rtx const_op1 = op1; | |
2165 | ||
ceb1d268 JW |
2166 | /* synth_mult does an `unsigned int' multiply. As long as the mode is |
2167 | less than or equal in size to `unsigned int' this doesn't matter. | |
2168 | If the mode is larger than `unsigned int', then synth_mult works only | |
2169 | if the constant value exactly fits in an `unsigned int' without any | |
2170 | truncation. This means that multiplying by negative values does | |
2171 | not work; results are off by 2^32 on a 32 bit machine. */ | |
2172 | ||
44037a66 TG |
2173 | /* If we are multiplying in DImode, it may still be a win |
2174 | to try to work with shifts and adds. */ | |
2175 | if (GET_CODE (op1) == CONST_DOUBLE | |
2176 | && GET_MODE_CLASS (GET_MODE (op1)) == MODE_INT | |
ceb1d268 JW |
2177 | && HOST_BITS_PER_INT >= BITS_PER_WORD |
2178 | && CONST_DOUBLE_HIGH (op1) == 0) | |
2179 | const_op1 = GEN_INT (CONST_DOUBLE_LOW (op1)); | |
2180 | else if (HOST_BITS_PER_INT < GET_MODE_BITSIZE (mode) | |
2181 | && GET_CODE (op1) == CONST_INT | |
2182 | && INTVAL (op1) < 0) | |
2183 | const_op1 = 0; | |
44037a66 | 2184 | |
66c1f88e RS |
2185 | /* We used to test optimize here, on the grounds that it's better to |
2186 | produce a smaller program when -O is not used. | |
2187 | But this causes such a terrible slowdown sometimes | |
2188 | that it seems better to use synth_mult always. */ | |
b385aeda | 2189 | |
ceb1d268 | 2190 | if (const_op1 && GET_CODE (const_op1) == CONST_INT) |
44037a66 TG |
2191 | { |
2192 | struct algorithm alg; | |
55c2d311 | 2193 | struct algorithm alg2; |
7963ac37 | 2194 | HOST_WIDE_INT val = INTVAL (op1); |
b385aeda RK |
2195 | HOST_WIDE_INT val_so_far; |
2196 | rtx insn; | |
819126a6 | 2197 | int mult_cost; |
55c2d311 | 2198 | enum {basic_variant, negate_variant, add_variant} variant = basic_variant; |
44037a66 | 2199 | |
55c2d311 TG |
2200 | /* Try to do the computation three ways: multiply by the negative of OP1 |
2201 | and then negate, do the multiplication directly, or do multiplication | |
2202 | by OP1 - 1. */ | |
44037a66 | 2203 | |
38a448ca | 2204 | mult_cost = rtx_cost (gen_rtx_MULT (mode, op0, op1), SET); |
c0b262c1 | 2205 | mult_cost = MIN (12 * add_cost, mult_cost); |
819126a6 RK |
2206 | |
2207 | synth_mult (&alg, val, mult_cost); | |
ceb1d268 JW |
2208 | |
2209 | /* This works only if the inverted value actually fits in an | |
2210 | `unsigned int' */ | |
2211 | if (HOST_BITS_PER_INT >= GET_MODE_BITSIZE (mode)) | |
2212 | { | |
2213 | synth_mult (&alg2, - val, | |
2214 | (alg.cost < mult_cost ? alg.cost : mult_cost) - negate_cost); | |
2215 | if (alg2.cost + negate_cost < alg.cost) | |
2216 | alg = alg2, variant = negate_variant; | |
2217 | } | |
44037a66 | 2218 | |
55c2d311 | 2219 | /* This proves very useful for division-by-constant. */ |
98310eaa RK |
2220 | synth_mult (&alg2, val - 1, |
2221 | (alg.cost < mult_cost ? alg.cost : mult_cost) - add_cost); | |
55c2d311 TG |
2222 | if (alg2.cost + add_cost < alg.cost) |
2223 | alg = alg2, variant = add_variant; | |
44037a66 | 2224 | |
7963ac37 | 2225 | if (alg.cost < mult_cost) |
44037a66 | 2226 | { |
b2fb324c | 2227 | /* We found something cheaper than a multiply insn. */ |
7963ac37 | 2228 | int opno; |
44037a66 | 2229 | rtx accum, tem; |
44037a66 TG |
2230 | |
2231 | op0 = protect_from_queue (op0, 0); | |
2232 | ||
2233 | /* Avoid referencing memory over and over. | |
2234 | For speed, but also for correctness when mem is volatile. */ | |
2235 | if (GET_CODE (op0) == MEM) | |
2236 | op0 = force_reg (mode, op0); | |
2237 | ||
b385aeda RK |
2238 | /* ACCUM starts out either as OP0 or as a zero, depending on |
2239 | the first operation. */ | |
2240 | ||
2241 | if (alg.op[0] == alg_zero) | |
44037a66 | 2242 | { |
b385aeda RK |
2243 | accum = copy_to_mode_reg (mode, const0_rtx); |
2244 | val_so_far = 0; | |
2245 | } | |
2246 | else if (alg.op[0] == alg_m) | |
2247 | { | |
819126a6 | 2248 | accum = copy_to_mode_reg (mode, op0); |
b385aeda | 2249 | val_so_far = 1; |
44037a66 | 2250 | } |
b385aeda RK |
2251 | else |
2252 | abort (); | |
7963ac37 RK |
2253 | |
2254 | for (opno = 1; opno < alg.ops; opno++) | |
44037a66 | 2255 | { |
b385aeda | 2256 | int log = alg.log[opno]; |
c0a08574 RK |
2257 | int preserve = preserve_subexpressions_p (); |
2258 | rtx shift_subtarget = preserve ? 0 : accum; | |
98310eaa RK |
2259 | rtx add_target |
2260 | = (opno == alg.ops - 1 && target != 0 && variant != add_variant | |
2261 | ? target : 0); | |
c0a08574 RK |
2262 | rtx accum_target = preserve ? 0 : accum; |
2263 | ||
44037a66 TG |
2264 | switch (alg.op[opno]) |
2265 | { | |
b2fb324c RK |
2266 | case alg_shift: |
2267 | accum = expand_shift (LSHIFT_EXPR, mode, accum, | |
2268 | build_int_2 (log, 0), NULL_RTX, 0); | |
b385aeda | 2269 | val_so_far <<= log; |
b2fb324c RK |
2270 | break; |
2271 | ||
7963ac37 | 2272 | case alg_add_t_m2: |
b385aeda RK |
2273 | tem = expand_shift (LSHIFT_EXPR, mode, op0, |
2274 | build_int_2 (log, 0), NULL_RTX, 0); | |
38a448ca | 2275 | accum = force_operand (gen_rtx_PLUS (mode, accum, tem), |
c0a08574 | 2276 | add_target ? add_target : accum_target); |
b385aeda | 2277 | val_so_far += (HOST_WIDE_INT) 1 << log; |
44037a66 TG |
2278 | break; |
2279 | ||
7963ac37 | 2280 | case alg_sub_t_m2: |
b385aeda RK |
2281 | tem = expand_shift (LSHIFT_EXPR, mode, op0, |
2282 | build_int_2 (log, 0), NULL_RTX, 0); | |
38a448ca | 2283 | accum = force_operand (gen_rtx_MINUS (mode, accum, tem), |
c0a08574 | 2284 | add_target ? add_target : accum_target); |
b385aeda | 2285 | val_so_far -= (HOST_WIDE_INT) 1 << log; |
7963ac37 | 2286 | break; |
44037a66 | 2287 | |
7963ac37 RK |
2288 | case alg_add_t2_m: |
2289 | accum = expand_shift (LSHIFT_EXPR, mode, accum, | |
c0a08574 RK |
2290 | build_int_2 (log, 0), shift_subtarget, |
2291 | 0); | |
38a448ca | 2292 | accum = force_operand (gen_rtx_PLUS (mode, accum, op0), |
c0a08574 | 2293 | add_target ? add_target : accum_target); |
b385aeda | 2294 | val_so_far = (val_so_far << log) + 1; |
44037a66 TG |
2295 | break; |
2296 | ||
7963ac37 RK |
2297 | case alg_sub_t2_m: |
2298 | accum = expand_shift (LSHIFT_EXPR, mode, accum, | |
c0a08574 RK |
2299 | build_int_2 (log, 0), shift_subtarget, |
2300 | 0); | |
38a448ca | 2301 | accum = force_operand (gen_rtx_MINUS (mode, accum, op0), |
c0a08574 | 2302 | add_target ? add_target : accum_target); |
b385aeda | 2303 | val_so_far = (val_so_far << log) - 1; |
7963ac37 RK |
2304 | break; |
2305 | ||
2306 | case alg_add_factor: | |
44037a66 | 2307 | tem = expand_shift (LSHIFT_EXPR, mode, accum, |
b1ec3c92 | 2308 | build_int_2 (log, 0), NULL_RTX, 0); |
38a448ca | 2309 | accum = force_operand (gen_rtx_PLUS (mode, accum, tem), |
c0a08574 | 2310 | add_target ? add_target : accum_target); |
b385aeda | 2311 | val_so_far += val_so_far << log; |
7963ac37 | 2312 | break; |
44037a66 | 2313 | |
7963ac37 RK |
2314 | case alg_sub_factor: |
2315 | tem = expand_shift (LSHIFT_EXPR, mode, accum, | |
2316 | build_int_2 (log, 0), NULL_RTX, 0); | |
38a448ca | 2317 | accum = force_operand (gen_rtx_MINUS (mode, tem, accum), |
c0a08574 RK |
2318 | (add_target ? add_target |
2319 | : preserve ? 0 : tem)); | |
b385aeda | 2320 | val_so_far = (val_so_far << log) - val_so_far; |
7963ac37 | 2321 | break; |
44037a66 | 2322 | |
b385aeda RK |
2323 | default: |
2324 | abort ();; | |
2325 | } | |
44037a66 | 2326 | |
b385aeda RK |
2327 | /* Write a REG_EQUAL note on the last insn so that we can cse |
2328 | multiplication sequences. */ | |
44037a66 | 2329 | |
b385aeda RK |
2330 | insn = get_last_insn (); |
2331 | REG_NOTES (insn) | |
38a448ca RH |
2332 | = gen_rtx_EXPR_LIST (REG_EQUAL, |
2333 | gen_rtx_MULT (mode, op0, GEN_INT (val_so_far)), | |
2334 | REG_NOTES (insn)); | |
b385aeda | 2335 | } |
44037a66 | 2336 | |
55c2d311 | 2337 | if (variant == negate_variant) |
44037a66 | 2338 | { |
b385aeda RK |
2339 | val_so_far = - val_so_far; |
2340 | accum = expand_unop (mode, neg_optab, accum, target, 0); | |
44037a66 | 2341 | } |
55c2d311 TG |
2342 | else if (variant == add_variant) |
2343 | { | |
2344 | val_so_far = val_so_far + 1; | |
38a448ca | 2345 | accum = force_operand (gen_rtx_PLUS (mode, accum, op0), target); |
55c2d311 | 2346 | } |
44037a66 | 2347 | |
b385aeda RK |
2348 | if (val != val_so_far) |
2349 | abort (); | |
2350 | ||
2351 | return accum; | |
44037a66 TG |
2352 | } |
2353 | } | |
2354 | ||
819126a6 RK |
2355 | /* This used to use umul_optab if unsigned, but for non-widening multiply |
2356 | there is no difference between signed and unsigned. */ | |
44037a66 TG |
2357 | op0 = expand_binop (mode, smul_optab, |
2358 | op0, op1, target, unsignedp, OPTAB_LIB_WIDEN); | |
2359 | if (op0 == 0) | |
2360 | abort (); | |
2361 | return op0; | |
2362 | } | |
2363 | \f | |
55c2d311 TG |
2364 | /* Return the smallest n such that 2**n >= X. */ |
2365 | ||
2366 | int | |
2367 | ceil_log2 (x) | |
2368 | unsigned HOST_WIDE_INT x; | |
2369 | { | |
2370 | return floor_log2 (x - 1) + 1; | |
2371 | } | |
2372 | ||
2373 | /* Choose a minimal N + 1 bit approximation to 1/D that can be used to | |
2374 | replace division by D, and put the least significant N bits of the result | |
2375 | in *MULTIPLIER_PTR and return the most significant bit. | |
2376 | ||
2377 | The width of operations is N (should be <= HOST_BITS_PER_WIDE_INT), the | |
2378 | needed precision is in PRECISION (should be <= N). | |
2379 | ||
2380 | PRECISION should be as small as possible so this function can choose | |
2381 | multiplier more freely. | |
2382 | ||
2383 | The rounded-up logarithm of D is placed in *lgup_ptr. A shift count that | |
2384 | is to be used for a final right shift is placed in *POST_SHIFT_PTR. | |
2385 | ||
2386 | Using this function, x/D will be equal to (x * m) >> (*POST_SHIFT_PTR), | |
2387 | where m is the full HOST_BITS_PER_WIDE_INT + 1 bit multiplier. */ | |
2388 | ||
2389 | static | |
2390 | unsigned HOST_WIDE_INT | |
2391 | choose_multiplier (d, n, precision, multiplier_ptr, post_shift_ptr, lgup_ptr) | |
2392 | unsigned HOST_WIDE_INT d; | |
2393 | int n; | |
2394 | int precision; | |
2395 | unsigned HOST_WIDE_INT *multiplier_ptr; | |
2396 | int *post_shift_ptr; | |
2397 | int *lgup_ptr; | |
2398 | { | |
2399 | unsigned HOST_WIDE_INT mhigh_hi, mhigh_lo; | |
2400 | unsigned HOST_WIDE_INT mlow_hi, mlow_lo; | |
2401 | int lgup, post_shift; | |
2402 | int pow, pow2; | |
2403 | unsigned HOST_WIDE_INT nh, nl, dummy1, dummy2; | |
2404 | ||
2405 | /* lgup = ceil(log2(divisor)); */ | |
2406 | lgup = ceil_log2 (d); | |
2407 | ||
2408 | if (lgup > n) | |
2409 | abort (); | |
2410 | ||
2411 | pow = n + lgup; | |
2412 | pow2 = n + lgup - precision; | |
2413 | ||
2414 | if (pow == 2 * HOST_BITS_PER_WIDE_INT) | |
2415 | { | |
2416 | /* We could handle this with some effort, but this case is much better | |
2417 | handled directly with a scc insn, so rely on caller using that. */ | |
2418 | abort (); | |
2419 | } | |
2420 | ||
2421 | /* mlow = 2^(N + lgup)/d */ | |
2422 | if (pow >= HOST_BITS_PER_WIDE_INT) | |
2423 | { | |
2424 | nh = (unsigned HOST_WIDE_INT) 1 << (pow - HOST_BITS_PER_WIDE_INT); | |
2425 | nl = 0; | |
2426 | } | |
2427 | else | |
2428 | { | |
2429 | nh = 0; | |
2430 | nl = (unsigned HOST_WIDE_INT) 1 << pow; | |
2431 | } | |
2432 | div_and_round_double (TRUNC_DIV_EXPR, 1, nl, nh, d, (HOST_WIDE_INT) 0, | |
2433 | &mlow_lo, &mlow_hi, &dummy1, &dummy2); | |
2434 | ||
2435 | /* mhigh = (2^(N + lgup) + 2^N + lgup - precision)/d */ | |
2436 | if (pow2 >= HOST_BITS_PER_WIDE_INT) | |
2437 | nh |= (unsigned HOST_WIDE_INT) 1 << (pow2 - HOST_BITS_PER_WIDE_INT); | |
2438 | else | |
2439 | nl |= (unsigned HOST_WIDE_INT) 1 << pow2; | |
2440 | div_and_round_double (TRUNC_DIV_EXPR, 1, nl, nh, d, (HOST_WIDE_INT) 0, | |
2441 | &mhigh_lo, &mhigh_hi, &dummy1, &dummy2); | |
2442 | ||
2443 | if (mhigh_hi && nh - d >= d) | |
2444 | abort (); | |
2445 | if (mhigh_hi > 1 || mlow_hi > 1) | |
2446 | abort (); | |
2447 | /* assert that mlow < mhigh. */ | |
2448 | if (! (mlow_hi < mhigh_hi || (mlow_hi == mhigh_hi && mlow_lo < mhigh_lo))) | |
2449 | abort(); | |
2450 | ||
2451 | /* If precision == N, then mlow, mhigh exceed 2^N | |
2452 | (but they do not exceed 2^(N+1)). */ | |
2453 | ||
2454 | /* Reduce to lowest terms */ | |
2455 | for (post_shift = lgup; post_shift > 0; post_shift--) | |
2456 | { | |
2457 | unsigned HOST_WIDE_INT ml_lo = (mlow_hi << (HOST_BITS_PER_WIDE_INT - 1)) | (mlow_lo >> 1); | |
2458 | unsigned HOST_WIDE_INT mh_lo = (mhigh_hi << (HOST_BITS_PER_WIDE_INT - 1)) | (mhigh_lo >> 1); | |
2459 | if (ml_lo >= mh_lo) | |
2460 | break; | |
2461 | ||
2462 | mlow_hi = 0; | |
2463 | mlow_lo = ml_lo; | |
2464 | mhigh_hi = 0; | |
2465 | mhigh_lo = mh_lo; | |
2466 | } | |
2467 | ||
2468 | *post_shift_ptr = post_shift; | |
2469 | *lgup_ptr = lgup; | |
2470 | if (n < HOST_BITS_PER_WIDE_INT) | |
2471 | { | |
2472 | unsigned HOST_WIDE_INT mask = ((unsigned HOST_WIDE_INT) 1 << n) - 1; | |
2473 | *multiplier_ptr = mhigh_lo & mask; | |
2474 | return mhigh_lo >= mask; | |
2475 | } | |
2476 | else | |
2477 | { | |
2478 | *multiplier_ptr = mhigh_lo; | |
2479 | return mhigh_hi; | |
2480 | } | |
2481 | } | |
2482 | ||
2483 | /* Compute the inverse of X mod 2**n, i.e., find Y such that X * Y is | |
2484 | congruent to 1 (mod 2**N). */ | |
2485 | ||
2486 | static unsigned HOST_WIDE_INT | |
2487 | invert_mod2n (x, n) | |
2488 | unsigned HOST_WIDE_INT x; | |
2489 | int n; | |
2490 | { | |
0f41302f | 2491 | /* Solve x*y == 1 (mod 2^n), where x is odd. Return y. */ |
55c2d311 TG |
2492 | |
2493 | /* The algorithm notes that the choice y = x satisfies | |
2494 | x*y == 1 mod 2^3, since x is assumed odd. | |
2495 | Each iteration doubles the number of bits of significance in y. */ | |
2496 | ||
2497 | unsigned HOST_WIDE_INT mask; | |
2498 | unsigned HOST_WIDE_INT y = x; | |
2499 | int nbit = 3; | |
2500 | ||
2501 | mask = (n == HOST_BITS_PER_WIDE_INT | |
2502 | ? ~(unsigned HOST_WIDE_INT) 0 | |
2503 | : ((unsigned HOST_WIDE_INT) 1 << n) - 1); | |
2504 | ||
2505 | while (nbit < n) | |
2506 | { | |
2507 | y = y * (2 - x*y) & mask; /* Modulo 2^N */ | |
2508 | nbit *= 2; | |
2509 | } | |
2510 | return y; | |
2511 | } | |
2512 | ||
2513 | /* Emit code to adjust ADJ_OPERAND after multiplication of wrong signedness | |
2514 | flavor of OP0 and OP1. ADJ_OPERAND is already the high half of the | |
2515 | product OP0 x OP1. If UNSIGNEDP is nonzero, adjust the signed product | |
2516 | to become unsigned, if UNSIGNEDP is zero, adjust the unsigned product to | |
2517 | become signed. | |
2518 | ||
2519 | The result is put in TARGET if that is convenient. | |
2520 | ||
2521 | MODE is the mode of operation. */ | |
2522 | ||
2523 | rtx | |
2524 | expand_mult_highpart_adjust (mode, adj_operand, op0, op1, target, unsignedp) | |
2525 | enum machine_mode mode; | |
2526 | register rtx adj_operand, op0, op1, target; | |
2527 | int unsignedp; | |
2528 | { | |
2529 | rtx tem; | |
2530 | enum rtx_code adj_code = unsignedp ? PLUS : MINUS; | |
2531 | ||
2532 | tem = expand_shift (RSHIFT_EXPR, mode, op0, | |
2533 | build_int_2 (GET_MODE_BITSIZE (mode) - 1, 0), | |
2534 | NULL_RTX, 0); | |
2535 | tem = expand_and (tem, op1, NULL_RTX); | |
38a448ca RH |
2536 | adj_operand |
2537 | = force_operand (gen_rtx_fmt_ee (adj_code, mode, adj_operand, tem), | |
2538 | adj_operand); | |
55c2d311 TG |
2539 | |
2540 | tem = expand_shift (RSHIFT_EXPR, mode, op1, | |
2541 | build_int_2 (GET_MODE_BITSIZE (mode) - 1, 0), | |
2542 | NULL_RTX, 0); | |
2543 | tem = expand_and (tem, op0, NULL_RTX); | |
38a448ca RH |
2544 | target = force_operand (gen_rtx_fmt_ee (adj_code, mode, adj_operand, tem), |
2545 | target); | |
55c2d311 TG |
2546 | |
2547 | return target; | |
2548 | } | |
2549 | ||
2550 | /* Emit code to multiply OP0 and CNST1, putting the high half of the result | |
2551 | in TARGET if that is convenient, and return where the result is. If the | |
2552 | operation can not be performed, 0 is returned. | |
2553 | ||
2554 | MODE is the mode of operation and result. | |
2555 | ||
71af73bb TG |
2556 | UNSIGNEDP nonzero means unsigned multiply. |
2557 | ||
2558 | MAX_COST is the total allowed cost for the expanded RTL. */ | |
55c2d311 TG |
2559 | |
2560 | rtx | |
71af73bb | 2561 | expand_mult_highpart (mode, op0, cnst1, target, unsignedp, max_cost) |
55c2d311 TG |
2562 | enum machine_mode mode; |
2563 | register rtx op0, target; | |
2564 | unsigned HOST_WIDE_INT cnst1; | |
2565 | int unsignedp; | |
71af73bb | 2566 | int max_cost; |
55c2d311 TG |
2567 | { |
2568 | enum machine_mode wider_mode = GET_MODE_WIDER_MODE (mode); | |
2569 | optab mul_highpart_optab; | |
2570 | optab moptab; | |
2571 | rtx tem; | |
2572 | int size = GET_MODE_BITSIZE (mode); | |
5b0ce758 | 2573 | rtx op1, wide_op1; |
55c2d311 | 2574 | |
5b0ce758 RK |
2575 | /* We can't support modes wider than HOST_BITS_PER_INT. */ |
2576 | if (size > HOST_BITS_PER_WIDE_INT) | |
2577 | abort (); | |
2578 | ||
2579 | op1 = GEN_INT (cnst1); | |
2580 | ||
2581 | if (GET_MODE_BITSIZE (wider_mode) <= HOST_BITS_PER_INT) | |
2582 | wide_op1 = op1; | |
2583 | else | |
2584 | wide_op1 | |
2585 | = immed_double_const (cnst1, | |
55c2d311 TG |
2586 | (unsignedp |
2587 | ? (HOST_WIDE_INT) 0 | |
2588 | : -(cnst1 >> (HOST_BITS_PER_WIDE_INT - 1))), | |
2589 | wider_mode); | |
2590 | ||
2591 | /* expand_mult handles constant multiplication of word_mode | |
2592 | or narrower. It does a poor job for large modes. */ | |
71af73bb TG |
2593 | if (size < BITS_PER_WORD |
2594 | && mul_cost[(int) wider_mode] + shift_cost[size-1] < max_cost) | |
55c2d311 TG |
2595 | { |
2596 | /* We have to do this, since expand_binop doesn't do conversion for | |
2597 | multiply. Maybe change expand_binop to handle widening multiply? */ | |
2598 | op0 = convert_to_mode (wider_mode, op0, unsignedp); | |
2599 | ||
5b0ce758 | 2600 | tem = expand_mult (wider_mode, op0, wide_op1, NULL_RTX, unsignedp); |
55c2d311 TG |
2601 | tem = expand_shift (RSHIFT_EXPR, wider_mode, tem, |
2602 | build_int_2 (size, 0), NULL_RTX, 1); | |
2f97afcb | 2603 | return convert_modes (mode, wider_mode, tem, unsignedp); |
55c2d311 TG |
2604 | } |
2605 | ||
2606 | if (target == 0) | |
2607 | target = gen_reg_rtx (mode); | |
2608 | ||
2609 | /* Firstly, try using a multiplication insn that only generates the needed | |
2610 | high part of the product, and in the sign flavor of unsignedp. */ | |
71af73bb TG |
2611 | if (mul_highpart_cost[(int) mode] < max_cost) |
2612 | { | |
2613 | mul_highpart_optab = unsignedp ? umul_highpart_optab : smul_highpart_optab; | |
2614 | target = expand_binop (mode, mul_highpart_optab, | |
24dcc9c5 | 2615 | op0, wide_op1, target, unsignedp, OPTAB_DIRECT); |
71af73bb TG |
2616 | if (target) |
2617 | return target; | |
2618 | } | |
55c2d311 TG |
2619 | |
2620 | /* Secondly, same as above, but use sign flavor opposite of unsignedp. | |
2621 | Need to adjust the result after the multiplication. */ | |
71af73bb TG |
2622 | if (mul_highpart_cost[(int) mode] + 2 * shift_cost[size-1] + 4 * add_cost < max_cost) |
2623 | { | |
2624 | mul_highpart_optab = unsignedp ? smul_highpart_optab : umul_highpart_optab; | |
2625 | target = expand_binop (mode, mul_highpart_optab, | |
24dcc9c5 | 2626 | op0, wide_op1, target, unsignedp, OPTAB_DIRECT); |
71af73bb TG |
2627 | if (target) |
2628 | /* We used the wrong signedness. Adjust the result. */ | |
2629 | return expand_mult_highpart_adjust (mode, target, op0, | |
2630 | op1, target, unsignedp); | |
2631 | } | |
55c2d311 | 2632 | |
71af73bb | 2633 | /* Try widening multiplication. */ |
55c2d311 | 2634 | moptab = unsignedp ? umul_widen_optab : smul_widen_optab; |
71af73bb TG |
2635 | if (moptab->handlers[(int) wider_mode].insn_code != CODE_FOR_nothing |
2636 | && mul_widen_cost[(int) wider_mode] < max_cost) | |
a295d331 TG |
2637 | { |
2638 | op1 = force_reg (mode, op1); | |
2639 | goto try; | |
2640 | } | |
71af73bb TG |
2641 | |
2642 | /* Try widening the mode and perform a non-widening multiplication. */ | |
2643 | moptab = smul_optab; | |
2644 | if (smul_optab->handlers[(int) wider_mode].insn_code != CODE_FOR_nothing | |
2645 | && mul_cost[(int) wider_mode] + shift_cost[size-1] < max_cost) | |
a295d331 TG |
2646 | { |
2647 | op1 = wide_op1; | |
2648 | goto try; | |
2649 | } | |
71af73bb TG |
2650 | |
2651 | /* Try widening multiplication of opposite signedness, and adjust. */ | |
2652 | moptab = unsignedp ? smul_widen_optab : umul_widen_optab; | |
2653 | if (moptab->handlers[(int) wider_mode].insn_code != CODE_FOR_nothing | |
2654 | && (mul_widen_cost[(int) wider_mode] | |
2655 | + 2 * shift_cost[size-1] + 4 * add_cost < max_cost)) | |
55c2d311 | 2656 | { |
a295d331 TG |
2657 | rtx regop1 = force_reg (mode, op1); |
2658 | tem = expand_binop (wider_mode, moptab, op0, regop1, | |
71af73bb TG |
2659 | NULL_RTX, ! unsignedp, OPTAB_WIDEN); |
2660 | if (tem != 0) | |
55c2d311 | 2661 | { |
71af73bb TG |
2662 | /* Extract the high half of the just generated product. */ |
2663 | tem = expand_shift (RSHIFT_EXPR, wider_mode, tem, | |
2664 | build_int_2 (size, 0), NULL_RTX, 1); | |
2665 | tem = convert_modes (mode, wider_mode, tem, unsignedp); | |
2666 | /* We used the wrong signedness. Adjust the result. */ | |
2667 | return expand_mult_highpart_adjust (mode, tem, op0, op1, | |
2668 | target, unsignedp); | |
55c2d311 | 2669 | } |
55c2d311 TG |
2670 | } |
2671 | ||
71af73bb TG |
2672 | return 0; |
2673 | ||
2674 | try: | |
55c2d311 | 2675 | /* Pass NULL_RTX as target since TARGET has wrong mode. */ |
a295d331 | 2676 | tem = expand_binop (wider_mode, moptab, op0, op1, |
55c2d311 TG |
2677 | NULL_RTX, unsignedp, OPTAB_WIDEN); |
2678 | if (tem == 0) | |
2679 | return 0; | |
2680 | ||
2681 | /* Extract the high half of the just generated product. */ | |
a295d331 TG |
2682 | if (mode == word_mode) |
2683 | { | |
2684 | return gen_highpart (mode, tem); | |
2685 | } | |
2686 | else | |
2687 | { | |
2688 | tem = expand_shift (RSHIFT_EXPR, wider_mode, tem, | |
2689 | build_int_2 (size, 0), NULL_RTX, 1); | |
2690 | return convert_modes (mode, wider_mode, tem, unsignedp); | |
2691 | } | |
55c2d311 TG |
2692 | } |
2693 | \f | |
44037a66 TG |
2694 | /* Emit the code to divide OP0 by OP1, putting the result in TARGET |
2695 | if that is convenient, and returning where the result is. | |
2696 | You may request either the quotient or the remainder as the result; | |
2697 | specify REM_FLAG nonzero to get the remainder. | |
2698 | ||
2699 | CODE is the expression code for which kind of division this is; | |
2700 | it controls how rounding is done. MODE is the machine mode to use. | |
2701 | UNSIGNEDP nonzero means do unsigned division. */ | |
2702 | ||
2703 | /* ??? For CEIL_MOD_EXPR, can compute incorrect remainder with ANDI | |
2704 | and then correct it by or'ing in missing high bits | |
2705 | if result of ANDI is nonzero. | |
2706 | For ROUND_MOD_EXPR, can use ANDI and then sign-extend the result. | |
2707 | This could optimize to a bfexts instruction. | |
2708 | But C doesn't use these operations, so their optimizations are | |
2709 | left for later. */ | |
2710 | ||
55c2d311 TG |
2711 | #define EXACT_POWER_OF_2_OR_ZERO_P(x) (((x) & ((x) - 1)) == 0) |
2712 | ||
44037a66 TG |
2713 | rtx |
2714 | expand_divmod (rem_flag, code, mode, op0, op1, target, unsignedp) | |
2715 | int rem_flag; | |
2716 | enum tree_code code; | |
2717 | enum machine_mode mode; | |
2718 | register rtx op0, op1, target; | |
2719 | int unsignedp; | |
2720 | { | |
44037a66 | 2721 | enum machine_mode compute_mode; |
55c2d311 TG |
2722 | register rtx tquotient; |
2723 | rtx quotient = 0, remainder = 0; | |
2724 | rtx last; | |
2c414fba | 2725 | int size; |
4e430df8 | 2726 | rtx insn, set; |
44037a66 | 2727 | optab optab1, optab2; |
55c2d311 | 2728 | int op1_is_constant, op1_is_pow2; |
71af73bb | 2729 | int max_cost, extra_cost; |
55c2d311 TG |
2730 | |
2731 | op1_is_constant = GET_CODE (op1) == CONST_INT; | |
9176af2f TG |
2732 | op1_is_pow2 = (op1_is_constant |
2733 | && ((EXACT_POWER_OF_2_OR_ZERO_P (INTVAL (op1)) | |
db7cafb0 | 2734 | || (! unsignedp && EXACT_POWER_OF_2_OR_ZERO_P (-INTVAL (op1)))))); |
55c2d311 TG |
2735 | |
2736 | /* | |
2737 | This is the structure of expand_divmod: | |
2738 | ||
2739 | First comes code to fix up the operands so we can perform the operations | |
2740 | correctly and efficiently. | |
2741 | ||
2742 | Second comes a switch statement with code specific for each rounding mode. | |
2743 | For some special operands this code emits all RTL for the desired | |
69f61901 | 2744 | operation, for other cases, it generates only a quotient and stores it in |
55c2d311 TG |
2745 | QUOTIENT. The case for trunc division/remainder might leave quotient = 0, |
2746 | to indicate that it has not done anything. | |
2747 | ||
69f61901 RK |
2748 | Last comes code that finishes the operation. If QUOTIENT is set and |
2749 | REM_FLAG is set, the remainder is computed as OP0 - QUOTIENT * OP1. If | |
2750 | QUOTIENT is not set, it is computed using trunc rounding. | |
44037a66 | 2751 | |
55c2d311 TG |
2752 | We try to generate special code for division and remainder when OP1 is a |
2753 | constant. If |OP1| = 2**n we can use shifts and some other fast | |
2754 | operations. For other values of OP1, we compute a carefully selected | |
2755 | fixed-point approximation m = 1/OP1, and generate code that multiplies OP0 | |
2756 | by m. | |
2757 | ||
2758 | In all cases but EXACT_DIV_EXPR, this multiplication requires the upper | |
2759 | half of the product. Different strategies for generating the product are | |
2760 | implemented in expand_mult_highpart. | |
2761 | ||
2762 | If what we actually want is the remainder, we generate that by another | |
2763 | by-constant multiplication and a subtraction. */ | |
2764 | ||
2765 | /* We shouldn't be called with OP1 == const1_rtx, but some of the | |
3d32ffd1 TW |
2766 | code below will malfunction if we are, so check here and handle |
2767 | the special case if so. */ | |
2768 | if (op1 == const1_rtx) | |
2769 | return rem_flag ? const0_rtx : op0; | |
2770 | ||
bc1c7e93 RK |
2771 | if (target |
2772 | /* Don't use the function value register as a target | |
2773 | since we have to read it as well as write it, | |
2774 | and function-inlining gets confused by this. */ | |
2775 | && ((REG_P (target) && REG_FUNCTION_VALUE_P (target)) | |
2776 | /* Don't clobber an operand while doing a multi-step calculation. */ | |
515dfc7a | 2777 | || ((rem_flag || op1_is_constant) |
bc1c7e93 RK |
2778 | && (reg_mentioned_p (target, op0) |
2779 | || (GET_CODE (op0) == MEM && GET_CODE (target) == MEM))) | |
2780 | || reg_mentioned_p (target, op1) | |
2781 | || (GET_CODE (op1) == MEM && GET_CODE (target) == MEM))) | |
44037a66 TG |
2782 | target = 0; |
2783 | ||
44037a66 TG |
2784 | /* Get the mode in which to perform this computation. Normally it will |
2785 | be MODE, but sometimes we can't do the desired operation in MODE. | |
2786 | If so, pick a wider mode in which we can do the operation. Convert | |
2787 | to that mode at the start to avoid repeated conversions. | |
2788 | ||
2789 | First see what operations we need. These depend on the expression | |
2790 | we are evaluating. (We assume that divxx3 insns exist under the | |
2791 | same conditions that modxx3 insns and that these insns don't normally | |
2792 | fail. If these assumptions are not correct, we may generate less | |
2793 | efficient code in some cases.) | |
2794 | ||
2795 | Then see if we find a mode in which we can open-code that operation | |
2796 | (either a division, modulus, or shift). Finally, check for the smallest | |
2797 | mode for which we can do the operation with a library call. */ | |
2798 | ||
55c2d311 TG |
2799 | /* We might want to refine this now that we have division-by-constant |
2800 | optimization. Since expand_mult_highpart tries so many variants, it is | |
2801 | not straightforward to generalize this. Maybe we should make an array | |
2802 | of possible modes in init_expmed? Save this for GCC 2.7. */ | |
2803 | ||
2804 | optab1 = (op1_is_pow2 ? (unsignedp ? lshr_optab : ashr_optab) | |
44037a66 | 2805 | : (unsignedp ? udiv_optab : sdiv_optab)); |
55c2d311 | 2806 | optab2 = (op1_is_pow2 ? optab1 : (unsignedp ? udivmod_optab : sdivmod_optab)); |
44037a66 TG |
2807 | |
2808 | for (compute_mode = mode; compute_mode != VOIDmode; | |
2809 | compute_mode = GET_MODE_WIDER_MODE (compute_mode)) | |
2810 | if (optab1->handlers[(int) compute_mode].insn_code != CODE_FOR_nothing | |
2811 | || optab2->handlers[(int) compute_mode].insn_code != CODE_FOR_nothing) | |
2812 | break; | |
2813 | ||
2814 | if (compute_mode == VOIDmode) | |
2815 | for (compute_mode = mode; compute_mode != VOIDmode; | |
2816 | compute_mode = GET_MODE_WIDER_MODE (compute_mode)) | |
2817 | if (optab1->handlers[(int) compute_mode].libfunc | |
2818 | || optab2->handlers[(int) compute_mode].libfunc) | |
2819 | break; | |
2820 | ||
bc1c7e93 RK |
2821 | /* If we still couldn't find a mode, use MODE, but we'll probably abort |
2822 | in expand_binop. */ | |
44037a66 TG |
2823 | if (compute_mode == VOIDmode) |
2824 | compute_mode = mode; | |
2825 | ||
55c2d311 TG |
2826 | if (target && GET_MODE (target) == compute_mode) |
2827 | tquotient = target; | |
2828 | else | |
2829 | tquotient = gen_reg_rtx (compute_mode); | |
2c414fba | 2830 | |
55c2d311 TG |
2831 | size = GET_MODE_BITSIZE (compute_mode); |
2832 | #if 0 | |
2833 | /* It should be possible to restrict the precision to GET_MODE_BITSIZE | |
71af73bb TG |
2834 | (mode), and thereby get better code when OP1 is a constant. Do that |
2835 | later. It will require going over all usages of SIZE below. */ | |
55c2d311 TG |
2836 | size = GET_MODE_BITSIZE (mode); |
2837 | #endif | |
bc1c7e93 | 2838 | |
71af73bb TG |
2839 | max_cost = div_cost[(int) compute_mode] |
2840 | - (rem_flag ? mul_cost[(int) compute_mode] + add_cost : 0); | |
2841 | ||
55c2d311 | 2842 | /* Now convert to the best mode to use. */ |
44037a66 TG |
2843 | if (compute_mode != mode) |
2844 | { | |
55c2d311 | 2845 | op0 = convert_modes (compute_mode, mode, op0, unsignedp); |
81722fa9 | 2846 | op1 = convert_modes (compute_mode, mode, op1, unsignedp); |
e13a25d5 | 2847 | |
e9a25f70 JL |
2848 | /* convert_modes may have placed op1 into a register, so we |
2849 | must recompute the following. */ | |
e13a25d5 DM |
2850 | op1_is_constant = GET_CODE (op1) == CONST_INT; |
2851 | op1_is_pow2 = (op1_is_constant | |
2852 | && ((EXACT_POWER_OF_2_OR_ZERO_P (INTVAL (op1)) | |
2853 | || (! unsignedp | |
e9a25f70 | 2854 | && EXACT_POWER_OF_2_OR_ZERO_P (-INTVAL (op1)))))) ; |
44037a66 TG |
2855 | } |
2856 | ||
55c2d311 | 2857 | /* If one of the operands is a volatile MEM, copy it into a register. */ |
c2a47e48 | 2858 | |
55c2d311 TG |
2859 | if (GET_CODE (op0) == MEM && MEM_VOLATILE_P (op0)) |
2860 | op0 = force_reg (compute_mode, op0); | |
2861 | if (GET_CODE (op1) == MEM && MEM_VOLATILE_P (op1)) | |
c2a47e48 RK |
2862 | op1 = force_reg (compute_mode, op1); |
2863 | ||
ab0b6581 TG |
2864 | /* If we need the remainder or if OP1 is constant, we need to |
2865 | put OP0 in a register in case it has any queued subexpressions. */ | |
2866 | if (rem_flag || op1_is_constant) | |
2867 | op0 = force_reg (compute_mode, op0); | |
bc1c7e93 | 2868 | |
55c2d311 | 2869 | last = get_last_insn (); |
44037a66 | 2870 | |
9faa82d8 | 2871 | /* Promote floor rounding to trunc rounding for unsigned operations. */ |
55c2d311 | 2872 | if (unsignedp) |
44037a66 | 2873 | { |
55c2d311 TG |
2874 | if (code == FLOOR_DIV_EXPR) |
2875 | code = TRUNC_DIV_EXPR; | |
2876 | if (code == FLOOR_MOD_EXPR) | |
2877 | code = TRUNC_MOD_EXPR; | |
db7cafb0 JL |
2878 | if (code == EXACT_DIV_EXPR && op1_is_pow2) |
2879 | code = TRUNC_DIV_EXPR; | |
55c2d311 | 2880 | } |
bc1c7e93 | 2881 | |
55c2d311 TG |
2882 | if (op1 != const0_rtx) |
2883 | switch (code) | |
2884 | { | |
2885 | case TRUNC_MOD_EXPR: | |
2886 | case TRUNC_DIV_EXPR: | |
34f016ed | 2887 | if (op1_is_constant) |
55c2d311 | 2888 | { |
d8f1376c | 2889 | if (unsignedp) |
55c2d311 TG |
2890 | { |
2891 | unsigned HOST_WIDE_INT mh, ml; | |
2892 | int pre_shift, post_shift; | |
2893 | int dummy; | |
2894 | unsigned HOST_WIDE_INT d = INTVAL (op1); | |
2895 | ||
2896 | if (EXACT_POWER_OF_2_OR_ZERO_P (d)) | |
2897 | { | |
2898 | pre_shift = floor_log2 (d); | |
2899 | if (rem_flag) | |
2900 | { | |
db3cf6fb MS |
2901 | remainder |
2902 | = expand_binop (compute_mode, and_optab, op0, | |
2903 | GEN_INT (((HOST_WIDE_INT) 1 << pre_shift) - 1), | |
2904 | remainder, 1, | |
2905 | OPTAB_LIB_WIDEN); | |
55c2d311 | 2906 | if (remainder) |
c8dbc8ca | 2907 | return gen_lowpart (mode, remainder); |
55c2d311 TG |
2908 | } |
2909 | quotient = expand_shift (RSHIFT_EXPR, compute_mode, op0, | |
2910 | build_int_2 (pre_shift, 0), | |
2911 | tquotient, 1); | |
2912 | } | |
34f016ed | 2913 | else if (size <= HOST_BITS_PER_WIDE_INT) |
55c2d311 | 2914 | { |
dc1d6150 | 2915 | if (d >= ((unsigned HOST_WIDE_INT) 1 << (size - 1))) |
55c2d311 | 2916 | { |
dc1d6150 TG |
2917 | /* Most significant bit of divisor is set; emit an scc |
2918 | insn. */ | |
2919 | quotient = emit_store_flag (tquotient, GEU, op0, op1, | |
2920 | compute_mode, 1, 1); | |
2921 | if (quotient == 0) | |
55c2d311 | 2922 | goto fail1; |
55c2d311 TG |
2923 | } |
2924 | else | |
2925 | { | |
dc1d6150 TG |
2926 | /* Find a suitable multiplier and right shift count |
2927 | instead of multiplying with D. */ | |
2928 | ||
2929 | mh = choose_multiplier (d, size, size, | |
2930 | &ml, &post_shift, &dummy); | |
2931 | ||
2932 | /* If the suggested multiplier is more than SIZE bits, | |
2933 | we can do better for even divisors, using an | |
2934 | initial right shift. */ | |
2935 | if (mh != 0 && (d & 1) == 0) | |
2936 | { | |
2937 | pre_shift = floor_log2 (d & -d); | |
2938 | mh = choose_multiplier (d >> pre_shift, size, | |
2939 | size - pre_shift, | |
2940 | &ml, &post_shift, &dummy); | |
2941 | if (mh) | |
2942 | abort (); | |
2943 | } | |
2944 | else | |
2945 | pre_shift = 0; | |
2946 | ||
2947 | if (mh != 0) | |
2948 | { | |
2949 | rtx t1, t2, t3, t4; | |
2950 | ||
2951 | extra_cost = (shift_cost[post_shift - 1] | |
2952 | + shift_cost[1] + 2 * add_cost); | |
2953 | t1 = expand_mult_highpart (compute_mode, op0, ml, | |
2954 | NULL_RTX, 1, | |
2955 | max_cost - extra_cost); | |
2956 | if (t1 == 0) | |
2957 | goto fail1; | |
38a448ca RH |
2958 | t2 = force_operand (gen_rtx_MINUS (compute_mode, |
2959 | op0, t1), | |
dc1d6150 TG |
2960 | NULL_RTX); |
2961 | t3 = expand_shift (RSHIFT_EXPR, compute_mode, t2, | |
2962 | build_int_2 (1, 0), NULL_RTX,1); | |
38a448ca RH |
2963 | t4 = force_operand (gen_rtx_PLUS (compute_mode, |
2964 | t1, t3), | |
dc1d6150 | 2965 | NULL_RTX); |
db3cf6fb MS |
2966 | quotient |
2967 | = expand_shift (RSHIFT_EXPR, compute_mode, t4, | |
2968 | build_int_2 (post_shift - 1, 0), | |
2969 | tquotient, 1); | |
dc1d6150 TG |
2970 | } |
2971 | else | |
2972 | { | |
2973 | rtx t1, t2; | |
2974 | ||
2975 | t1 = expand_shift (RSHIFT_EXPR, compute_mode, op0, | |
2976 | build_int_2 (pre_shift, 0), | |
2977 | NULL_RTX, 1); | |
2978 | extra_cost = (shift_cost[pre_shift] | |
2979 | + shift_cost[post_shift]); | |
2980 | t2 = expand_mult_highpart (compute_mode, t1, ml, | |
2981 | NULL_RTX, 1, | |
2982 | max_cost - extra_cost); | |
2983 | if (t2 == 0) | |
2984 | goto fail1; | |
db3cf6fb MS |
2985 | quotient |
2986 | = expand_shift (RSHIFT_EXPR, compute_mode, t2, | |
2987 | build_int_2 (post_shift, 0), | |
2988 | tquotient, 1); | |
dc1d6150 | 2989 | } |
55c2d311 TG |
2990 | } |
2991 | } | |
34f016ed TG |
2992 | else /* Too wide mode to use tricky code */ |
2993 | break; | |
55c2d311 TG |
2994 | |
2995 | insn = get_last_insn (); | |
4e430df8 RK |
2996 | if (insn != last |
2997 | && (set = single_set (insn)) != 0 | |
2998 | && SET_DEST (set) == quotient) | |
2999 | REG_NOTES (insn) | |
38a448ca RH |
3000 | = gen_rtx_EXPR_LIST (REG_EQUAL, |
3001 | gen_rtx_UDIV (compute_mode, op0, op1), | |
3002 | REG_NOTES (insn)); | |
55c2d311 TG |
3003 | } |
3004 | else /* TRUNC_DIV, signed */ | |
3005 | { | |
3006 | unsigned HOST_WIDE_INT ml; | |
3007 | int lgup, post_shift; | |
3008 | HOST_WIDE_INT d = INTVAL (op1); | |
3009 | unsigned HOST_WIDE_INT abs_d = d >= 0 ? d : -d; | |
3010 | ||
3011 | /* n rem d = n rem -d */ | |
3012 | if (rem_flag && d < 0) | |
3013 | { | |
3014 | d = abs_d; | |
3015 | op1 = GEN_INT (abs_d); | |
3016 | } | |
3017 | ||
3018 | if (d == 1) | |
3019 | quotient = op0; | |
3020 | else if (d == -1) | |
3021 | quotient = expand_unop (compute_mode, neg_optab, op0, | |
3022 | tquotient, 0); | |
f737b132 RK |
3023 | else if (abs_d == (unsigned HOST_WIDE_INT) 1 << (size - 1)) |
3024 | { | |
3025 | /* This case is not handled correctly below. */ | |
3026 | quotient = emit_store_flag (tquotient, EQ, op0, op1, | |
3027 | compute_mode, 1, 1); | |
3028 | if (quotient == 0) | |
3029 | goto fail1; | |
3030 | } | |
55c2d311 TG |
3031 | else if (EXACT_POWER_OF_2_OR_ZERO_P (d) |
3032 | && (rem_flag ? smod_pow2_cheap : sdiv_pow2_cheap)) | |
3033 | ; | |
3034 | else if (EXACT_POWER_OF_2_OR_ZERO_P (abs_d)) | |
3035 | { | |
3036 | lgup = floor_log2 (abs_d); | |
3037 | if (abs_d != 2 && BRANCH_COST < 3) | |
3038 | { | |
3039 | rtx label = gen_label_rtx (); | |
3040 | rtx t1; | |
3041 | ||
3042 | t1 = copy_to_mode_reg (compute_mode, op0); | |
3043 | emit_cmp_insn (t1, const0_rtx, GE, | |
3044 | NULL_RTX, compute_mode, 0, 0); | |
3045 | emit_jump_insn (gen_bge (label)); | |
3046 | expand_inc (t1, GEN_INT (abs_d - 1)); | |
3047 | emit_label (label); | |
3048 | quotient = expand_shift (RSHIFT_EXPR, compute_mode, t1, | |
3049 | build_int_2 (lgup, 0), | |
3050 | tquotient, 0); | |
3051 | } | |
3052 | else | |
3053 | { | |
3054 | rtx t1, t2, t3; | |
3055 | t1 = expand_shift (RSHIFT_EXPR, compute_mode, op0, | |
3056 | build_int_2 (size - 1, 0), | |
3057 | NULL_RTX, 0); | |
3058 | t2 = expand_shift (RSHIFT_EXPR, compute_mode, t1, | |
3059 | build_int_2 (size - lgup, 0), | |
3060 | NULL_RTX, 1); | |
38a448ca RH |
3061 | t3 = force_operand (gen_rtx_PLUS (compute_mode, |
3062 | op0, t2), | |
55c2d311 TG |
3063 | NULL_RTX); |
3064 | quotient = expand_shift (RSHIFT_EXPR, compute_mode, t3, | |
3065 | build_int_2 (lgup, 0), | |
3066 | tquotient, 0); | |
3067 | } | |
3068 | ||
e8031612 RK |
3069 | /* We have computed OP0 / abs(OP1). If OP1 is negative, negate |
3070 | the quotient. */ | |
55c2d311 TG |
3071 | if (d < 0) |
3072 | { | |
3073 | insn = get_last_insn (); | |
4e430df8 RK |
3074 | if (insn != last |
3075 | && (set = single_set (insn)) != 0 | |
3076 | && SET_DEST (set) == quotient) | |
3077 | REG_NOTES (insn) | |
38a448ca RH |
3078 | = gen_rtx_EXPR_LIST (REG_EQUAL, |
3079 | gen_rtx_DIV (compute_mode, | |
3080 | op0, | |
3081 | GEN_INT (abs_d)), | |
4e430df8 | 3082 | REG_NOTES (insn)); |
55c2d311 TG |
3083 | |
3084 | quotient = expand_unop (compute_mode, neg_optab, | |
3085 | quotient, quotient, 0); | |
3086 | } | |
3087 | } | |
34f016ed | 3088 | else if (size <= HOST_BITS_PER_WIDE_INT) |
55c2d311 TG |
3089 | { |
3090 | choose_multiplier (abs_d, size, size - 1, | |
3091 | &ml, &post_shift, &lgup); | |
3092 | if (ml < (unsigned HOST_WIDE_INT) 1 << (size - 1)) | |
3093 | { | |
3094 | rtx t1, t2, t3; | |
3095 | ||
71af73bb TG |
3096 | extra_cost = (shift_cost[post_shift] |
3097 | + shift_cost[size - 1] + add_cost); | |
55c2d311 | 3098 | t1 = expand_mult_highpart (compute_mode, op0, ml, |
71af73bb TG |
3099 | NULL_RTX, 0, |
3100 | max_cost - extra_cost); | |
55c2d311 TG |
3101 | if (t1 == 0) |
3102 | goto fail1; | |
3103 | t2 = expand_shift (RSHIFT_EXPR, compute_mode, t1, | |
3104 | build_int_2 (post_shift, 0), NULL_RTX, 0); | |
3105 | t3 = expand_shift (RSHIFT_EXPR, compute_mode, op0, | |
3106 | build_int_2 (size - 1, 0), NULL_RTX, 0); | |
3107 | if (d < 0) | |
38a448ca | 3108 | quotient = force_operand (gen_rtx_MINUS (compute_mode, t3, t2), |
55c2d311 TG |
3109 | tquotient); |
3110 | else | |
38a448ca | 3111 | quotient = force_operand (gen_rtx_MINUS (compute_mode, t2, t3), |
55c2d311 TG |
3112 | tquotient); |
3113 | } | |
3114 | else | |
3115 | { | |
3116 | rtx t1, t2, t3, t4; | |
3117 | ||
3118 | ml |= (~(unsigned HOST_WIDE_INT) 0) << (size - 1); | |
71af73bb TG |
3119 | extra_cost = (shift_cost[post_shift] |
3120 | + shift_cost[size - 1] + 2 * add_cost); | |
55c2d311 | 3121 | t1 = expand_mult_highpart (compute_mode, op0, ml, |
71af73bb TG |
3122 | NULL_RTX, 0, |
3123 | max_cost - extra_cost); | |
55c2d311 TG |
3124 | if (t1 == 0) |
3125 | goto fail1; | |
38a448ca | 3126 | t2 = force_operand (gen_rtx_PLUS (compute_mode, t1, op0), |
55c2d311 TG |
3127 | NULL_RTX); |
3128 | t3 = expand_shift (RSHIFT_EXPR, compute_mode, t2, | |
3129 | build_int_2 (post_shift, 0), NULL_RTX, 0); | |
3130 | t4 = expand_shift (RSHIFT_EXPR, compute_mode, op0, | |
3131 | build_int_2 (size - 1, 0), NULL_RTX, 0); | |
3132 | if (d < 0) | |
38a448ca | 3133 | quotient = force_operand (gen_rtx_MINUS (compute_mode, t4, t3), |
55c2d311 TG |
3134 | tquotient); |
3135 | else | |
38a448ca | 3136 | quotient = force_operand (gen_rtx_MINUS (compute_mode, t3, t4), |
55c2d311 TG |
3137 | tquotient); |
3138 | } | |
3139 | } | |
34f016ed TG |
3140 | else /* Too wide mode to use tricky code */ |
3141 | break; | |
55c2d311 | 3142 | |
4e430df8 RK |
3143 | insn = get_last_insn (); |
3144 | if (insn != last | |
3145 | && (set = single_set (insn)) != 0 | |
3146 | && SET_DEST (set) == quotient) | |
3147 | REG_NOTES (insn) | |
38a448ca RH |
3148 | = gen_rtx_EXPR_LIST (REG_EQUAL, |
3149 | gen_rtx_DIV (compute_mode, op0, op1), | |
3150 | REG_NOTES (insn)); | |
55c2d311 TG |
3151 | } |
3152 | break; | |
3153 | } | |
3154 | fail1: | |
3155 | delete_insns_since (last); | |
3156 | break; | |
44037a66 | 3157 | |
55c2d311 TG |
3158 | case FLOOR_DIV_EXPR: |
3159 | case FLOOR_MOD_EXPR: | |
3160 | /* We will come here only for signed operations. */ | |
3161 | if (op1_is_constant && HOST_BITS_PER_WIDE_INT >= size) | |
3162 | { | |
3163 | unsigned HOST_WIDE_INT mh, ml; | |
3164 | int pre_shift, lgup, post_shift; | |
3165 | HOST_WIDE_INT d = INTVAL (op1); | |
3166 | ||
3167 | if (d > 0) | |
3168 | { | |
3169 | /* We could just as easily deal with negative constants here, | |
3170 | but it does not seem worth the trouble for GCC 2.6. */ | |
3171 | if (EXACT_POWER_OF_2_OR_ZERO_P (d)) | |
3172 | { | |
3173 | pre_shift = floor_log2 (d); | |
3174 | if (rem_flag) | |
3175 | { | |
3176 | remainder = expand_binop (compute_mode, and_optab, op0, | |
3177 | GEN_INT (((HOST_WIDE_INT) 1 << pre_shift) - 1), | |
3178 | remainder, 0, OPTAB_LIB_WIDEN); | |
3179 | if (remainder) | |
c8dbc8ca | 3180 | return gen_lowpart (mode, remainder); |
55c2d311 TG |
3181 | } |
3182 | quotient = expand_shift (RSHIFT_EXPR, compute_mode, op0, | |
3183 | build_int_2 (pre_shift, 0), | |
3184 | tquotient, 0); | |
3185 | } | |
3186 | else | |
3187 | { | |
3188 | rtx t1, t2, t3, t4; | |
3189 | ||
3190 | mh = choose_multiplier (d, size, size - 1, | |
3191 | &ml, &post_shift, &lgup); | |
3192 | if (mh) | |
3193 | abort (); | |
3194 | ||
3195 | t1 = expand_shift (RSHIFT_EXPR, compute_mode, op0, | |
3196 | build_int_2 (size - 1, 0), NULL_RTX, 0); | |
3197 | t2 = expand_binop (compute_mode, xor_optab, op0, t1, | |
3198 | NULL_RTX, 0, OPTAB_WIDEN); | |
71af73bb TG |
3199 | extra_cost = (shift_cost[post_shift] |
3200 | + shift_cost[size - 1] + 2 * add_cost); | |
55c2d311 | 3201 | t3 = expand_mult_highpart (compute_mode, t2, ml, |
71af73bb TG |
3202 | NULL_RTX, 1, |
3203 | max_cost - extra_cost); | |
55c2d311 TG |
3204 | if (t3 != 0) |
3205 | { | |
3206 | t4 = expand_shift (RSHIFT_EXPR, compute_mode, t3, | |
3207 | build_int_2 (post_shift, 0), | |
3208 | NULL_RTX, 1); | |
3209 | quotient = expand_binop (compute_mode, xor_optab, | |
3210 | t4, t1, tquotient, 0, | |
3211 | OPTAB_WIDEN); | |
3212 | } | |
3213 | } | |
3214 | } | |
3215 | else | |
3216 | { | |
3217 | rtx nsign, t1, t2, t3, t4; | |
38a448ca RH |
3218 | t1 = force_operand (gen_rtx_PLUS (compute_mode, |
3219 | op0, constm1_rtx), NULL_RTX); | |
55c2d311 TG |
3220 | t2 = expand_binop (compute_mode, ior_optab, op0, t1, NULL_RTX, |
3221 | 0, OPTAB_WIDEN); | |
3222 | nsign = expand_shift (RSHIFT_EXPR, compute_mode, t2, | |
3223 | build_int_2 (size - 1, 0), NULL_RTX, 0); | |
38a448ca | 3224 | t3 = force_operand (gen_rtx_MINUS (compute_mode, t1, nsign), |
55c2d311 TG |
3225 | NULL_RTX); |
3226 | t4 = expand_divmod (0, TRUNC_DIV_EXPR, compute_mode, t3, op1, | |
3227 | NULL_RTX, 0); | |
3228 | if (t4) | |
3229 | { | |
3230 | rtx t5; | |
3231 | t5 = expand_unop (compute_mode, one_cmpl_optab, nsign, | |
3232 | NULL_RTX, 0); | |
38a448ca RH |
3233 | quotient = force_operand (gen_rtx_PLUS (compute_mode, |
3234 | t4, t5), | |
55c2d311 TG |
3235 | tquotient); |
3236 | } | |
3237 | } | |
3238 | } | |
3239 | ||
3240 | if (quotient != 0) | |
3241 | break; | |
3242 | delete_insns_since (last); | |
3243 | ||
3244 | /* Try using an instruction that produces both the quotient and | |
3245 | remainder, using truncation. We can easily compensate the quotient | |
3246 | or remainder to get floor rounding, once we have the remainder. | |
3247 | Notice that we compute also the final remainder value here, | |
3248 | and return the result right away. */ | |
a45cf58c | 3249 | if (target == 0 || GET_MODE (target) != compute_mode) |
55c2d311 | 3250 | target = gen_reg_rtx (compute_mode); |
668443c9 | 3251 | |
55c2d311 TG |
3252 | if (rem_flag) |
3253 | { | |
668443c9 RK |
3254 | remainder |
3255 | = GET_CODE (target) == REG ? target : gen_reg_rtx (compute_mode); | |
55c2d311 TG |
3256 | quotient = gen_reg_rtx (compute_mode); |
3257 | } | |
3258 | else | |
3259 | { | |
668443c9 RK |
3260 | quotient |
3261 | = GET_CODE (target) == REG ? target : gen_reg_rtx (compute_mode); | |
55c2d311 TG |
3262 | remainder = gen_reg_rtx (compute_mode); |
3263 | } | |
3264 | ||
3265 | if (expand_twoval_binop (sdivmod_optab, op0, op1, | |
3266 | quotient, remainder, 0)) | |
3267 | { | |
3268 | /* This could be computed with a branch-less sequence. | |
3269 | Save that for later. */ | |
3270 | rtx tem; | |
3271 | rtx label = gen_label_rtx (); | |
3272 | emit_cmp_insn (remainder, const0_rtx, EQ, NULL_RTX, | |
3273 | compute_mode, 0, 0); | |
3274 | emit_jump_insn (gen_beq (label)); | |
3275 | tem = expand_binop (compute_mode, xor_optab, op0, op1, | |
3276 | NULL_RTX, 0, OPTAB_WIDEN); | |
3277 | emit_cmp_insn (tem, const0_rtx, GE, NULL_RTX, compute_mode, 0, 0); | |
3278 | emit_jump_insn (gen_bge (label)); | |
3279 | expand_dec (quotient, const1_rtx); | |
3280 | expand_inc (remainder, op1); | |
3281 | emit_label (label); | |
c8dbc8ca | 3282 | return gen_lowpart (mode, rem_flag ? remainder : quotient); |
55c2d311 TG |
3283 | } |
3284 | ||
3285 | /* No luck with division elimination or divmod. Have to do it | |
3286 | by conditionally adjusting op0 *and* the result. */ | |
44037a66 | 3287 | { |
55c2d311 TG |
3288 | rtx label1, label2, label3, label4, label5; |
3289 | rtx adjusted_op0; | |
3290 | rtx tem; | |
3291 | ||
3292 | quotient = gen_reg_rtx (compute_mode); | |
3293 | adjusted_op0 = copy_to_mode_reg (compute_mode, op0); | |
3294 | label1 = gen_label_rtx (); | |
3295 | label2 = gen_label_rtx (); | |
3296 | label3 = gen_label_rtx (); | |
3297 | label4 = gen_label_rtx (); | |
3298 | label5 = gen_label_rtx (); | |
3299 | emit_cmp_insn (op1, const0_rtx, LT, NULL_RTX, compute_mode, 0, 0); | |
3300 | emit_jump_insn (gen_blt (label2)); | |
3301 | emit_cmp_insn (adjusted_op0, const0_rtx, LT, NULL_RTX, | |
3302 | compute_mode, 0, 0); | |
3303 | emit_jump_insn (gen_blt (label1)); | |
3304 | tem = expand_binop (compute_mode, sdiv_optab, adjusted_op0, op1, | |
3305 | quotient, 0, OPTAB_LIB_WIDEN); | |
3306 | if (tem != quotient) | |
3307 | emit_move_insn (quotient, tem); | |
3308 | emit_jump_insn (gen_jump (label5)); | |
3309 | emit_barrier (); | |
3310 | emit_label (label1); | |
44037a66 | 3311 | expand_inc (adjusted_op0, const1_rtx); |
55c2d311 TG |
3312 | emit_jump_insn (gen_jump (label4)); |
3313 | emit_barrier (); | |
3314 | emit_label (label2); | |
3315 | emit_cmp_insn (adjusted_op0, const0_rtx, GT, NULL_RTX, | |
3316 | compute_mode, 0, 0); | |
3317 | emit_jump_insn (gen_bgt (label3)); | |
3318 | tem = expand_binop (compute_mode, sdiv_optab, adjusted_op0, op1, | |
3319 | quotient, 0, OPTAB_LIB_WIDEN); | |
3320 | if (tem != quotient) | |
3321 | emit_move_insn (quotient, tem); | |
3322 | emit_jump_insn (gen_jump (label5)); | |
3323 | emit_barrier (); | |
3324 | emit_label (label3); | |
3325 | expand_dec (adjusted_op0, const1_rtx); | |
3326 | emit_label (label4); | |
3327 | tem = expand_binop (compute_mode, sdiv_optab, adjusted_op0, op1, | |
3328 | quotient, 0, OPTAB_LIB_WIDEN); | |
3329 | if (tem != quotient) | |
3330 | emit_move_insn (quotient, tem); | |
3331 | expand_dec (quotient, const1_rtx); | |
3332 | emit_label (label5); | |
44037a66 | 3333 | } |
55c2d311 | 3334 | break; |
44037a66 | 3335 | |
55c2d311 TG |
3336 | case CEIL_DIV_EXPR: |
3337 | case CEIL_MOD_EXPR: | |
3338 | if (unsignedp) | |
3339 | { | |
9176af2f TG |
3340 | if (op1_is_constant && EXACT_POWER_OF_2_OR_ZERO_P (INTVAL (op1))) |
3341 | { | |
3342 | rtx t1, t2, t3; | |
3343 | unsigned HOST_WIDE_INT d = INTVAL (op1); | |
3344 | t1 = expand_shift (RSHIFT_EXPR, compute_mode, op0, | |
3345 | build_int_2 (floor_log2 (d), 0), | |
412381d9 | 3346 | tquotient, 1); |
9176af2f TG |
3347 | t2 = expand_binop (compute_mode, and_optab, op0, |
3348 | GEN_INT (d - 1), | |
3349 | NULL_RTX, 1, OPTAB_LIB_WIDEN); | |
3350 | t3 = gen_reg_rtx (compute_mode); | |
3351 | t3 = emit_store_flag (t3, NE, t2, const0_rtx, | |
3352 | compute_mode, 1, 1); | |
412381d9 TG |
3353 | if (t3 == 0) |
3354 | { | |
3355 | rtx lab; | |
3356 | lab = gen_label_rtx (); | |
3357 | emit_cmp_insn (t2, const0_rtx, EQ, NULL_RTX, | |
3358 | compute_mode, 0, 0); | |
3359 | emit_jump_insn (gen_beq (lab)); | |
3360 | expand_inc (t1, const1_rtx); | |
3361 | emit_label (lab); | |
3362 | quotient = t1; | |
3363 | } | |
3364 | else | |
38a448ca RH |
3365 | quotient = force_operand (gen_rtx_PLUS (compute_mode, |
3366 | t1, t3), | |
412381d9 | 3367 | tquotient); |
9176af2f TG |
3368 | break; |
3369 | } | |
55c2d311 TG |
3370 | |
3371 | /* Try using an instruction that produces both the quotient and | |
3372 | remainder, using truncation. We can easily compensate the | |
3373 | quotient or remainder to get ceiling rounding, once we have the | |
3374 | remainder. Notice that we compute also the final remainder | |
3375 | value here, and return the result right away. */ | |
a45cf58c | 3376 | if (target == 0 || GET_MODE (target) != compute_mode) |
55c2d311 | 3377 | target = gen_reg_rtx (compute_mode); |
668443c9 | 3378 | |
55c2d311 TG |
3379 | if (rem_flag) |
3380 | { | |
668443c9 RK |
3381 | remainder = (GET_CODE (target) == REG |
3382 | ? target : gen_reg_rtx (compute_mode)); | |
55c2d311 TG |
3383 | quotient = gen_reg_rtx (compute_mode); |
3384 | } | |
3385 | else | |
3386 | { | |
668443c9 RK |
3387 | quotient = (GET_CODE (target) == REG |
3388 | ? target : gen_reg_rtx (compute_mode)); | |
55c2d311 TG |
3389 | remainder = gen_reg_rtx (compute_mode); |
3390 | } | |
3391 | ||
3392 | if (expand_twoval_binop (udivmod_optab, op0, op1, quotient, | |
3393 | remainder, 1)) | |
3394 | { | |
3395 | /* This could be computed with a branch-less sequence. | |
3396 | Save that for later. */ | |
3397 | rtx label = gen_label_rtx (); | |
3398 | emit_cmp_insn (remainder, const0_rtx, EQ, NULL_RTX, | |
3399 | compute_mode, 0, 0); | |
3400 | emit_jump_insn (gen_beq (label)); | |
3401 | expand_inc (quotient, const1_rtx); | |
3402 | expand_dec (remainder, op1); | |
3403 | emit_label (label); | |
c8dbc8ca | 3404 | return gen_lowpart (mode, rem_flag ? remainder : quotient); |
55c2d311 TG |
3405 | } |
3406 | ||
3407 | /* No luck with division elimination or divmod. Have to do it | |
3408 | by conditionally adjusting op0 *and* the result. */ | |
44037a66 | 3409 | { |
55c2d311 TG |
3410 | rtx label1, label2; |
3411 | rtx adjusted_op0, tem; | |
3412 | ||
3413 | quotient = gen_reg_rtx (compute_mode); | |
3414 | adjusted_op0 = copy_to_mode_reg (compute_mode, op0); | |
3415 | label1 = gen_label_rtx (); | |
3416 | label2 = gen_label_rtx (); | |
3417 | emit_cmp_insn (adjusted_op0, const0_rtx, NE, NULL_RTX, | |
3418 | compute_mode, 0, 0); | |
3419 | emit_jump_insn (gen_bne (label1)); | |
3420 | emit_move_insn (quotient, const0_rtx); | |
3421 | emit_jump_insn (gen_jump (label2)); | |
3422 | emit_barrier (); | |
3423 | emit_label (label1); | |
3424 | expand_dec (adjusted_op0, const1_rtx); | |
3425 | tem = expand_binop (compute_mode, udiv_optab, adjusted_op0, op1, | |
3426 | quotient, 1, OPTAB_LIB_WIDEN); | |
3427 | if (tem != quotient) | |
3428 | emit_move_insn (quotient, tem); | |
3429 | expand_inc (quotient, const1_rtx); | |
3430 | emit_label (label2); | |
44037a66 | 3431 | } |
55c2d311 TG |
3432 | } |
3433 | else /* signed */ | |
3434 | { | |
73f27728 RK |
3435 | if (op1_is_constant && EXACT_POWER_OF_2_OR_ZERO_P (INTVAL (op1)) |
3436 | && INTVAL (op1) >= 0) | |
3437 | { | |
3438 | /* This is extremely similar to the code for the unsigned case | |
3439 | above. For 2.7 we should merge these variants, but for | |
3440 | 2.6.1 I don't want to touch the code for unsigned since that | |
3441 | get used in C. The signed case will only be used by other | |
3442 | languages (Ada). */ | |
3443 | ||
3444 | rtx t1, t2, t3; | |
3445 | unsigned HOST_WIDE_INT d = INTVAL (op1); | |
3446 | t1 = expand_shift (RSHIFT_EXPR, compute_mode, op0, | |
3447 | build_int_2 (floor_log2 (d), 0), | |
3448 | tquotient, 0); | |
3449 | t2 = expand_binop (compute_mode, and_optab, op0, | |
3450 | GEN_INT (d - 1), | |
3451 | NULL_RTX, 1, OPTAB_LIB_WIDEN); | |
3452 | t3 = gen_reg_rtx (compute_mode); | |
3453 | t3 = emit_store_flag (t3, NE, t2, const0_rtx, | |
3454 | compute_mode, 1, 1); | |
3455 | if (t3 == 0) | |
3456 | { | |
3457 | rtx lab; | |
3458 | lab = gen_label_rtx (); | |
3459 | emit_cmp_insn (t2, const0_rtx, EQ, NULL_RTX, | |
3460 | compute_mode, 0, 0); | |
3461 | emit_jump_insn (gen_beq (lab)); | |
3462 | expand_inc (t1, const1_rtx); | |
3463 | emit_label (lab); | |
3464 | quotient = t1; | |
3465 | } | |
3466 | else | |
38a448ca RH |
3467 | quotient = force_operand (gen_rtx_PLUS (compute_mode, |
3468 | t1, t3), | |
73f27728 RK |
3469 | tquotient); |
3470 | break; | |
3471 | } | |
3472 | ||
55c2d311 TG |
3473 | /* Try using an instruction that produces both the quotient and |
3474 | remainder, using truncation. We can easily compensate the | |
3475 | quotient or remainder to get ceiling rounding, once we have the | |
3476 | remainder. Notice that we compute also the final remainder | |
3477 | value here, and return the result right away. */ | |
a45cf58c | 3478 | if (target == 0 || GET_MODE (target) != compute_mode) |
55c2d311 TG |
3479 | target = gen_reg_rtx (compute_mode); |
3480 | if (rem_flag) | |
3481 | { | |
668443c9 RK |
3482 | remainder= (GET_CODE (target) == REG |
3483 | ? target : gen_reg_rtx (compute_mode)); | |
55c2d311 TG |
3484 | quotient = gen_reg_rtx (compute_mode); |
3485 | } | |
3486 | else | |
3487 | { | |
668443c9 RK |
3488 | quotient = (GET_CODE (target) == REG |
3489 | ? target : gen_reg_rtx (compute_mode)); | |
55c2d311 TG |
3490 | remainder = gen_reg_rtx (compute_mode); |
3491 | } | |
3492 | ||
3493 | if (expand_twoval_binop (sdivmod_optab, op0, op1, quotient, | |
3494 | remainder, 0)) | |
3495 | { | |
3496 | /* This could be computed with a branch-less sequence. | |
3497 | Save that for later. */ | |
3498 | rtx tem; | |
3499 | rtx label = gen_label_rtx (); | |
3500 | emit_cmp_insn (remainder, const0_rtx, EQ, NULL_RTX, | |
3501 | compute_mode, 0, 0); | |
3502 | emit_jump_insn (gen_beq (label)); | |
3503 | tem = expand_binop (compute_mode, xor_optab, op0, op1, | |
3504 | NULL_RTX, 0, OPTAB_WIDEN); | |
3505 | emit_cmp_insn (tem, const0_rtx, LT, NULL_RTX, | |
3506 | compute_mode, 0, 0); | |
3507 | emit_jump_insn (gen_blt (label)); | |
3508 | expand_inc (quotient, const1_rtx); | |
3509 | expand_dec (remainder, op1); | |
3510 | emit_label (label); | |
c8dbc8ca | 3511 | return gen_lowpart (mode, rem_flag ? remainder : quotient); |
55c2d311 TG |
3512 | } |
3513 | ||
3514 | /* No luck with division elimination or divmod. Have to do it | |
3515 | by conditionally adjusting op0 *and* the result. */ | |
44037a66 | 3516 | { |
55c2d311 TG |
3517 | rtx label1, label2, label3, label4, label5; |
3518 | rtx adjusted_op0; | |
3519 | rtx tem; | |
3520 | ||
3521 | quotient = gen_reg_rtx (compute_mode); | |
3522 | adjusted_op0 = copy_to_mode_reg (compute_mode, op0); | |
3523 | label1 = gen_label_rtx (); | |
3524 | label2 = gen_label_rtx (); | |
3525 | label3 = gen_label_rtx (); | |
3526 | label4 = gen_label_rtx (); | |
3527 | label5 = gen_label_rtx (); | |
3528 | emit_cmp_insn (op1, const0_rtx, LT, NULL_RTX, | |
3529 | compute_mode, 0, 0); | |
3530 | emit_jump_insn (gen_blt (label2)); | |
3531 | emit_cmp_insn (adjusted_op0, const0_rtx, GT, NULL_RTX, | |
3532 | compute_mode, 0, 0); | |
3533 | emit_jump_insn (gen_bgt (label1)); | |
3534 | tem = expand_binop (compute_mode, sdiv_optab, adjusted_op0, op1, | |
3535 | quotient, 0, OPTAB_LIB_WIDEN); | |
3536 | if (tem != quotient) | |
3537 | emit_move_insn (quotient, tem); | |
3538 | emit_jump_insn (gen_jump (label5)); | |
3539 | emit_barrier (); | |
3540 | emit_label (label1); | |
3541 | expand_dec (adjusted_op0, const1_rtx); | |
3542 | emit_jump_insn (gen_jump (label4)); | |
3543 | emit_barrier (); | |
3544 | emit_label (label2); | |
3545 | emit_cmp_insn (adjusted_op0, const0_rtx, LT, NULL_RTX, | |
3546 | compute_mode, 0, 0); | |
3547 | emit_jump_insn (gen_blt (label3)); | |
3548 | tem = expand_binop (compute_mode, sdiv_optab, adjusted_op0, op1, | |
3549 | quotient, 0, OPTAB_LIB_WIDEN); | |
3550 | if (tem != quotient) | |
3551 | emit_move_insn (quotient, tem); | |
3552 | emit_jump_insn (gen_jump (label5)); | |
3553 | emit_barrier (); | |
3554 | emit_label (label3); | |
3555 | expand_inc (adjusted_op0, const1_rtx); | |
3556 | emit_label (label4); | |
3557 | tem = expand_binop (compute_mode, sdiv_optab, adjusted_op0, op1, | |
3558 | quotient, 0, OPTAB_LIB_WIDEN); | |
3559 | if (tem != quotient) | |
3560 | emit_move_insn (quotient, tem); | |
3561 | expand_inc (quotient, const1_rtx); | |
3562 | emit_label (label5); | |
44037a66 | 3563 | } |
55c2d311 TG |
3564 | } |
3565 | break; | |
bc1c7e93 | 3566 | |
55c2d311 TG |
3567 | case EXACT_DIV_EXPR: |
3568 | if (op1_is_constant && HOST_BITS_PER_WIDE_INT >= size) | |
3569 | { | |
3570 | HOST_WIDE_INT d = INTVAL (op1); | |
3571 | unsigned HOST_WIDE_INT ml; | |
3572 | int post_shift; | |
3573 | rtx t1; | |
3574 | ||
3575 | post_shift = floor_log2 (d & -d); | |
3576 | ml = invert_mod2n (d >> post_shift, size); | |
3577 | t1 = expand_mult (compute_mode, op0, GEN_INT (ml), NULL_RTX, | |
3578 | unsignedp); | |
3579 | quotient = expand_shift (RSHIFT_EXPR, compute_mode, t1, | |
3580 | build_int_2 (post_shift, 0), | |
3581 | NULL_RTX, unsignedp); | |
3582 | ||
3583 | insn = get_last_insn (); | |
3584 | REG_NOTES (insn) | |
38a448ca RH |
3585 | = gen_rtx_EXPR_LIST (REG_EQUAL, |
3586 | gen_rtx_fmt_ee (unsignedp ? UDIV : DIV, | |
3587 | compute_mode, | |
3588 | op0, op1), | |
3589 | REG_NOTES (insn)); | |
55c2d311 TG |
3590 | } |
3591 | break; | |
3592 | ||
3593 | case ROUND_DIV_EXPR: | |
3594 | case ROUND_MOD_EXPR: | |
69f61901 RK |
3595 | if (unsignedp) |
3596 | { | |
3597 | rtx tem; | |
3598 | rtx label; | |
3599 | label = gen_label_rtx (); | |
3600 | quotient = gen_reg_rtx (compute_mode); | |
3601 | remainder = gen_reg_rtx (compute_mode); | |
3602 | if (expand_twoval_binop (udivmod_optab, op0, op1, quotient, remainder, 1) == 0) | |
3603 | { | |
3604 | rtx tem; | |
3605 | quotient = expand_binop (compute_mode, udiv_optab, op0, op1, | |
3606 | quotient, 1, OPTAB_LIB_WIDEN); | |
3607 | tem = expand_mult (compute_mode, quotient, op1, NULL_RTX, 1); | |
3608 | remainder = expand_binop (compute_mode, sub_optab, op0, tem, | |
3609 | remainder, 1, OPTAB_LIB_WIDEN); | |
3610 | } | |
3611 | tem = plus_constant (op1, -1); | |
3612 | tem = expand_shift (RSHIFT_EXPR, compute_mode, tem, | |
3613 | build_int_2 (1, 0), NULL_RTX, 1); | |
3614 | emit_cmp_insn (remainder, tem, LEU, NULL_RTX, compute_mode, 0, 0); | |
3615 | emit_jump_insn (gen_bleu (label)); | |
3616 | expand_inc (quotient, const1_rtx); | |
3617 | expand_dec (remainder, op1); | |
3618 | emit_label (label); | |
3619 | } | |
3620 | else | |
3621 | { | |
3622 | rtx abs_rem, abs_op1, tem, mask; | |
3623 | rtx label; | |
3624 | label = gen_label_rtx (); | |
3625 | quotient = gen_reg_rtx (compute_mode); | |
3626 | remainder = gen_reg_rtx (compute_mode); | |
3627 | if (expand_twoval_binop (sdivmod_optab, op0, op1, quotient, remainder, 0) == 0) | |
3628 | { | |
3629 | rtx tem; | |
3630 | quotient = expand_binop (compute_mode, sdiv_optab, op0, op1, | |
3631 | quotient, 0, OPTAB_LIB_WIDEN); | |
3632 | tem = expand_mult (compute_mode, quotient, op1, NULL_RTX, 0); | |
3633 | remainder = expand_binop (compute_mode, sub_optab, op0, tem, | |
3634 | remainder, 0, OPTAB_LIB_WIDEN); | |
3635 | } | |
3636 | abs_rem = expand_abs (compute_mode, remainder, NULL_RTX, 0, 0); | |
3637 | abs_op1 = expand_abs (compute_mode, op1, NULL_RTX, 0, 0); | |
3638 | tem = expand_shift (LSHIFT_EXPR, compute_mode, abs_rem, | |
3639 | build_int_2 (1, 0), NULL_RTX, 1); | |
3640 | emit_cmp_insn (tem, abs_op1, LTU, NULL_RTX, compute_mode, 0, 0); | |
3641 | emit_jump_insn (gen_bltu (label)); | |
3642 | tem = expand_binop (compute_mode, xor_optab, op0, op1, | |
3643 | NULL_RTX, 0, OPTAB_WIDEN); | |
3644 | mask = expand_shift (RSHIFT_EXPR, compute_mode, tem, | |
3645 | build_int_2 (size - 1, 0), NULL_RTX, 0); | |
3646 | tem = expand_binop (compute_mode, xor_optab, mask, const1_rtx, | |
3647 | NULL_RTX, 0, OPTAB_WIDEN); | |
3648 | tem = expand_binop (compute_mode, sub_optab, tem, mask, | |
3649 | NULL_RTX, 0, OPTAB_WIDEN); | |
3650 | expand_inc (quotient, tem); | |
3651 | tem = expand_binop (compute_mode, xor_optab, mask, op1, | |
3652 | NULL_RTX, 0, OPTAB_WIDEN); | |
3653 | tem = expand_binop (compute_mode, sub_optab, tem, mask, | |
3654 | NULL_RTX, 0, OPTAB_WIDEN); | |
3655 | expand_dec (remainder, tem); | |
3656 | emit_label (label); | |
3657 | } | |
3658 | return gen_lowpart (mode, rem_flag ? remainder : quotient); | |
e9a25f70 JL |
3659 | |
3660 | default: | |
3661 | abort (); | |
55c2d311 | 3662 | } |
44037a66 | 3663 | |
55c2d311 | 3664 | if (quotient == 0) |
44037a66 | 3665 | { |
a45cf58c RK |
3666 | if (target && GET_MODE (target) != compute_mode) |
3667 | target = 0; | |
3668 | ||
55c2d311 | 3669 | if (rem_flag) |
44037a66 | 3670 | { |
55c2d311 TG |
3671 | /* Try to produce the remainder directly without a library call. */ |
3672 | remainder = sign_expand_binop (compute_mode, umod_optab, smod_optab, | |
3673 | op0, op1, target, | |
3674 | unsignedp, OPTAB_WIDEN); | |
3675 | if (remainder == 0) | |
44037a66 TG |
3676 | { |
3677 | /* No luck there. Can we do remainder and divide at once | |
3678 | without a library call? */ | |
55c2d311 TG |
3679 | remainder = gen_reg_rtx (compute_mode); |
3680 | if (! expand_twoval_binop ((unsignedp | |
3681 | ? udivmod_optab | |
3682 | : sdivmod_optab), | |
3683 | op0, op1, | |
3684 | NULL_RTX, remainder, unsignedp)) | |
3685 | remainder = 0; | |
44037a66 | 3686 | } |
55c2d311 TG |
3687 | |
3688 | if (remainder) | |
3689 | return gen_lowpart (mode, remainder); | |
44037a66 | 3690 | } |
44037a66 | 3691 | |
dc38b292 RK |
3692 | /* Produce the quotient. Try a quotient insn, but not a library call. |
3693 | If we have a divmod in this mode, use it in preference to widening | |
3694 | the div (for this test we assume it will not fail). Note that optab2 | |
3695 | is set to the one of the two optabs that the call below will use. */ | |
3696 | quotient | |
3697 | = sign_expand_binop (compute_mode, udiv_optab, sdiv_optab, | |
3698 | op0, op1, rem_flag ? NULL_RTX : target, | |
3699 | unsignedp, | |
3700 | ((optab2->handlers[(int) compute_mode].insn_code | |
3701 | != CODE_FOR_nothing) | |
3702 | ? OPTAB_DIRECT : OPTAB_WIDEN)); | |
3703 | ||
55c2d311 | 3704 | if (quotient == 0) |
44037a66 TG |
3705 | { |
3706 | /* No luck there. Try a quotient-and-remainder insn, | |
3707 | keeping the quotient alone. */ | |
55c2d311 | 3708 | quotient = gen_reg_rtx (compute_mode); |
44037a66 | 3709 | if (! expand_twoval_binop (unsignedp ? udivmod_optab : sdivmod_optab, |
55c2d311 TG |
3710 | op0, op1, |
3711 | quotient, NULL_RTX, unsignedp)) | |
3712 | { | |
3713 | quotient = 0; | |
3714 | if (! rem_flag) | |
3715 | /* Still no luck. If we are not computing the remainder, | |
3716 | use a library call for the quotient. */ | |
3717 | quotient = sign_expand_binop (compute_mode, | |
3718 | udiv_optab, sdiv_optab, | |
3719 | op0, op1, target, | |
3720 | unsignedp, OPTAB_LIB_WIDEN); | |
3721 | } | |
44037a66 | 3722 | } |
44037a66 TG |
3723 | } |
3724 | ||
44037a66 TG |
3725 | if (rem_flag) |
3726 | { | |
a45cf58c RK |
3727 | if (target && GET_MODE (target) != compute_mode) |
3728 | target = 0; | |
3729 | ||
55c2d311 | 3730 | if (quotient == 0) |
44037a66 | 3731 | /* No divide instruction either. Use library for remainder. */ |
55c2d311 TG |
3732 | remainder = sign_expand_binop (compute_mode, umod_optab, smod_optab, |
3733 | op0, op1, target, | |
3734 | unsignedp, OPTAB_LIB_WIDEN); | |
44037a66 TG |
3735 | else |
3736 | { | |
3737 | /* We divided. Now finish doing X - Y * (X / Y). */ | |
55c2d311 TG |
3738 | remainder = expand_mult (compute_mode, quotient, op1, |
3739 | NULL_RTX, unsignedp); | |
3740 | remainder = expand_binop (compute_mode, sub_optab, op0, | |
3741 | remainder, target, unsignedp, | |
3742 | OPTAB_LIB_WIDEN); | |
44037a66 TG |
3743 | } |
3744 | } | |
3745 | ||
55c2d311 | 3746 | return gen_lowpart (mode, rem_flag ? remainder : quotient); |
44037a66 TG |
3747 | } |
3748 | \f | |
3749 | /* Return a tree node with data type TYPE, describing the value of X. | |
3750 | Usually this is an RTL_EXPR, if there is no obvious better choice. | |
3751 | X may be an expression, however we only support those expressions | |
3752 | generated by loop.c. */ | |
3753 | ||
3754 | tree | |
3755 | make_tree (type, x) | |
3756 | tree type; | |
3757 | rtx x; | |
3758 | { | |
3759 | tree t; | |
3760 | ||
3761 | switch (GET_CODE (x)) | |
3762 | { | |
3763 | case CONST_INT: | |
3764 | t = build_int_2 (INTVAL (x), | |
4b46230e | 3765 | TREE_UNSIGNED (type) || INTVAL (x) >= 0 ? 0 : -1); |
44037a66 TG |
3766 | TREE_TYPE (t) = type; |
3767 | return t; | |
3768 | ||
3769 | case CONST_DOUBLE: | |
3770 | if (GET_MODE (x) == VOIDmode) | |
3771 | { | |
3772 | t = build_int_2 (CONST_DOUBLE_LOW (x), CONST_DOUBLE_HIGH (x)); | |
3773 | TREE_TYPE (t) = type; | |
3774 | } | |
3775 | else | |
3776 | { | |
3777 | REAL_VALUE_TYPE d; | |
3778 | ||
3779 | REAL_VALUE_FROM_CONST_DOUBLE (d, x); | |
3780 | t = build_real (type, d); | |
3781 | } | |
3782 | ||
3783 | return t; | |
3784 | ||
3785 | case PLUS: | |
3786 | return fold (build (PLUS_EXPR, type, make_tree (type, XEXP (x, 0)), | |
3787 | make_tree (type, XEXP (x, 1)))); | |
3788 | ||
3789 | case MINUS: | |
3790 | return fold (build (MINUS_EXPR, type, make_tree (type, XEXP (x, 0)), | |
3791 | make_tree (type, XEXP (x, 1)))); | |
3792 | ||
3793 | case NEG: | |
3794 | return fold (build1 (NEGATE_EXPR, type, make_tree (type, XEXP (x, 0)))); | |
3795 | ||
3796 | case MULT: | |
3797 | return fold (build (MULT_EXPR, type, make_tree (type, XEXP (x, 0)), | |
3798 | make_tree (type, XEXP (x, 1)))); | |
3799 | ||
3800 | case ASHIFT: | |
3801 | return fold (build (LSHIFT_EXPR, type, make_tree (type, XEXP (x, 0)), | |
3802 | make_tree (type, XEXP (x, 1)))); | |
3803 | ||
3804 | case LSHIFTRT: | |
3805 | return fold (convert (type, | |
3806 | build (RSHIFT_EXPR, unsigned_type (type), | |
3807 | make_tree (unsigned_type (type), | |
3808 | XEXP (x, 0)), | |
3809 | make_tree (type, XEXP (x, 1))))); | |
3810 | ||
3811 | case ASHIFTRT: | |
3812 | return fold (convert (type, | |
3813 | build (RSHIFT_EXPR, signed_type (type), | |
3814 | make_tree (signed_type (type), XEXP (x, 0)), | |
3815 | make_tree (type, XEXP (x, 1))))); | |
3816 | ||
3817 | case DIV: | |
3818 | if (TREE_CODE (type) != REAL_TYPE) | |
3819 | t = signed_type (type); | |
3820 | else | |
3821 | t = type; | |
3822 | ||
3823 | return fold (convert (type, | |
3824 | build (TRUNC_DIV_EXPR, t, | |
3825 | make_tree (t, XEXP (x, 0)), | |
3826 | make_tree (t, XEXP (x, 1))))); | |
3827 | case UDIV: | |
3828 | t = unsigned_type (type); | |
3829 | return fold (convert (type, | |
3830 | build (TRUNC_DIV_EXPR, t, | |
3831 | make_tree (t, XEXP (x, 0)), | |
3832 | make_tree (t, XEXP (x, 1))))); | |
3833 | default: | |
3834 | t = make_node (RTL_EXPR); | |
3835 | TREE_TYPE (t) = type; | |
3836 | RTL_EXPR_RTL (t) = x; | |
3837 | /* There are no insns to be output | |
3838 | when this rtl_expr is used. */ | |
3839 | RTL_EXPR_SEQUENCE (t) = 0; | |
3840 | return t; | |
3841 | } | |
3842 | } | |
3843 | ||
3844 | /* Return an rtx representing the value of X * MULT + ADD. | |
3845 | TARGET is a suggestion for where to store the result (an rtx). | |
3846 | MODE is the machine mode for the computation. | |
3847 | X and MULT must have mode MODE. ADD may have a different mode. | |
3848 | So can X (defaults to same as MODE). | |
3849 | UNSIGNEDP is non-zero to do unsigned multiplication. | |
3850 | This may emit insns. */ | |
3851 | ||
3852 | rtx | |
3853 | expand_mult_add (x, target, mult, add, mode, unsignedp) | |
3854 | rtx x, target, mult, add; | |
3855 | enum machine_mode mode; | |
3856 | int unsignedp; | |
3857 | { | |
3858 | tree type = type_for_mode (mode, unsignedp); | |
3859 | tree add_type = (GET_MODE (add) == VOIDmode | |
36d747f6 | 3860 | ? type : type_for_mode (GET_MODE (add), unsignedp)); |
44037a66 TG |
3861 | tree result = fold (build (PLUS_EXPR, type, |
3862 | fold (build (MULT_EXPR, type, | |
3863 | make_tree (type, x), | |
3864 | make_tree (type, mult))), | |
3865 | make_tree (add_type, add))); | |
3866 | ||
3867 | return expand_expr (result, target, VOIDmode, 0); | |
3868 | } | |
3869 | \f | |
3870 | /* Compute the logical-and of OP0 and OP1, storing it in TARGET | |
3871 | and returning TARGET. | |
3872 | ||
3873 | If TARGET is 0, a pseudo-register or constant is returned. */ | |
3874 | ||
3875 | rtx | |
3876 | expand_and (op0, op1, target) | |
3877 | rtx op0, op1, target; | |
3878 | { | |
3879 | enum machine_mode mode = VOIDmode; | |
3880 | rtx tem; | |
3881 | ||
3882 | if (GET_MODE (op0) != VOIDmode) | |
3883 | mode = GET_MODE (op0); | |
3884 | else if (GET_MODE (op1) != VOIDmode) | |
3885 | mode = GET_MODE (op1); | |
3886 | ||
3887 | if (mode != VOIDmode) | |
3888 | tem = expand_binop (mode, and_optab, op0, op1, target, 0, OPTAB_LIB_WIDEN); | |
3889 | else if (GET_CODE (op0) == CONST_INT && GET_CODE (op1) == CONST_INT) | |
b1ec3c92 | 3890 | tem = GEN_INT (INTVAL (op0) & INTVAL (op1)); |
44037a66 TG |
3891 | else |
3892 | abort (); | |
3893 | ||
3894 | if (target == 0) | |
3895 | target = tem; | |
3896 | else if (tem != target) | |
3897 | emit_move_insn (target, tem); | |
3898 | return target; | |
3899 | } | |
3900 | \f | |
3901 | /* Emit a store-flags instruction for comparison CODE on OP0 and OP1 | |
3902 | and storing in TARGET. Normally return TARGET. | |
3903 | Return 0 if that cannot be done. | |
3904 | ||
3905 | MODE is the mode to use for OP0 and OP1 should they be CONST_INTs. If | |
3906 | it is VOIDmode, they cannot both be CONST_INT. | |
3907 | ||
3908 | UNSIGNEDP is for the case where we have to widen the operands | |
3909 | to perform the operation. It says to use zero-extension. | |
3910 | ||
3911 | NORMALIZEP is 1 if we should convert the result to be either zero | |
373e7d69 | 3912 | or one. Normalize is -1 if we should convert the result to be |
44037a66 TG |
3913 | either zero or -1. If NORMALIZEP is zero, the result will be left |
3914 | "raw" out of the scc insn. */ | |
3915 | ||
3916 | rtx | |
3917 | emit_store_flag (target, code, op0, op1, mode, unsignedp, normalizep) | |
3918 | rtx target; | |
3919 | enum rtx_code code; | |
3920 | rtx op0, op1; | |
3921 | enum machine_mode mode; | |
3922 | int unsignedp; | |
3923 | int normalizep; | |
3924 | { | |
3925 | rtx subtarget; | |
3926 | enum insn_code icode; | |
3927 | enum machine_mode compare_mode; | |
3928 | enum machine_mode target_mode = GET_MODE (target); | |
3929 | rtx tem; | |
db2f8a07 | 3930 | rtx last = get_last_insn (); |
44037a66 TG |
3931 | rtx pattern, comparison; |
3932 | ||
c2615a67 RK |
3933 | /* If one operand is constant, make it the second one. Only do this |
3934 | if the other operand is not constant as well. */ | |
3935 | ||
3936 | if ((CONSTANT_P (op0) && ! CONSTANT_P (op1)) | |
3937 | || (GET_CODE (op0) == CONST_INT && GET_CODE (op1) != CONST_INT)) | |
3938 | { | |
3939 | tem = op0; | |
3940 | op0 = op1; | |
3941 | op1 = tem; | |
3942 | code = swap_condition (code); | |
3943 | } | |
3944 | ||
6405e07b DE |
3945 | if (mode == VOIDmode) |
3946 | mode = GET_MODE (op0); | |
3947 | ||
44037a66 TG |
3948 | /* For some comparisons with 1 and -1, we can convert this to |
3949 | comparisons with zero. This will often produce more opportunities for | |
0f41302f | 3950 | store-flag insns. */ |
44037a66 TG |
3951 | |
3952 | switch (code) | |
3953 | { | |
3954 | case LT: | |
3955 | if (op1 == const1_rtx) | |
3956 | op1 = const0_rtx, code = LE; | |
3957 | break; | |
3958 | case LE: | |
3959 | if (op1 == constm1_rtx) | |
3960 | op1 = const0_rtx, code = LT; | |
3961 | break; | |
3962 | case GE: | |
3963 | if (op1 == const1_rtx) | |
3964 | op1 = const0_rtx, code = GT; | |
3965 | break; | |
3966 | case GT: | |
3967 | if (op1 == constm1_rtx) | |
3968 | op1 = const0_rtx, code = GE; | |
3969 | break; | |
3970 | case GEU: | |
3971 | if (op1 == const1_rtx) | |
3972 | op1 = const0_rtx, code = NE; | |
3973 | break; | |
3974 | case LTU: | |
3975 | if (op1 == const1_rtx) | |
3976 | op1 = const0_rtx, code = EQ; | |
3977 | break; | |
e9a25f70 JL |
3978 | default: |
3979 | break; | |
44037a66 TG |
3980 | } |
3981 | ||
3982 | /* From now on, we won't change CODE, so set ICODE now. */ | |
3983 | icode = setcc_gen_code[(int) code]; | |
3984 | ||
3985 | /* If this is A < 0 or A >= 0, we can do this by taking the ones | |
3986 | complement of A (for GE) and shifting the sign bit to the low bit. */ | |
3987 | if (op1 == const0_rtx && (code == LT || code == GE) | |
3988 | && GET_MODE_CLASS (mode) == MODE_INT | |
3989 | && (normalizep || STORE_FLAG_VALUE == 1 | |
b1ec3c92 | 3990 | || (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT |
12dd565f | 3991 | && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode)) |
b1ec3c92 | 3992 | == (HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))))) |
44037a66 | 3993 | { |
8deb7047 | 3994 | subtarget = target; |
44037a66 TG |
3995 | |
3996 | /* If the result is to be wider than OP0, it is best to convert it | |
3997 | first. If it is to be narrower, it is *incorrect* to convert it | |
3998 | first. */ | |
3999 | if (GET_MODE_SIZE (target_mode) > GET_MODE_SIZE (mode)) | |
4000 | { | |
b3d4e1b2 | 4001 | op0 = protect_from_queue (op0, 0); |
81722fa9 | 4002 | op0 = convert_modes (target_mode, mode, op0, 0); |
44037a66 TG |
4003 | mode = target_mode; |
4004 | } | |
4005 | ||
4006 | if (target_mode != mode) | |
4007 | subtarget = 0; | |
4008 | ||
4009 | if (code == GE) | |
1d6eaf3d RK |
4010 | op0 = expand_unop (mode, one_cmpl_optab, op0, |
4011 | ((STORE_FLAG_VALUE == 1 || normalizep) | |
4012 | ? 0 : subtarget), 0); | |
44037a66 | 4013 | |
1d6eaf3d | 4014 | if (STORE_FLAG_VALUE == 1 || normalizep) |
44037a66 TG |
4015 | /* If we are supposed to produce a 0/1 value, we want to do |
4016 | a logical shift from the sign bit to the low-order bit; for | |
4017 | a -1/0 value, we do an arithmetic shift. */ | |
4018 | op0 = expand_shift (RSHIFT_EXPR, mode, op0, | |
4019 | size_int (GET_MODE_BITSIZE (mode) - 1), | |
4020 | subtarget, normalizep != -1); | |
4021 | ||
4022 | if (mode != target_mode) | |
c2ec26b8 | 4023 | op0 = convert_modes (target_mode, mode, op0, 0); |
44037a66 TG |
4024 | |
4025 | return op0; | |
4026 | } | |
4027 | ||
4028 | if (icode != CODE_FOR_nothing) | |
4029 | { | |
4030 | /* We think we may be able to do this with a scc insn. Emit the | |
4031 | comparison and then the scc insn. | |
4032 | ||
4033 | compare_from_rtx may call emit_queue, which would be deleted below | |
4034 | if the scc insn fails. So call it ourselves before setting LAST. */ | |
4035 | ||
4036 | emit_queue (); | |
4037 | last = get_last_insn (); | |
4038 | ||
b1ec3c92 CH |
4039 | comparison |
4040 | = compare_from_rtx (op0, op1, code, unsignedp, mode, NULL_RTX, 0); | |
44037a66 TG |
4041 | if (GET_CODE (comparison) == CONST_INT) |
4042 | return (comparison == const0_rtx ? const0_rtx | |
4043 | : normalizep == 1 ? const1_rtx | |
4044 | : normalizep == -1 ? constm1_rtx | |
4045 | : const_true_rtx); | |
4046 | ||
c2615a67 RK |
4047 | /* If the code of COMPARISON doesn't match CODE, something is |
4048 | wrong; we can no longer be sure that we have the operation. | |
4049 | We could handle this case, but it should not happen. */ | |
4050 | ||
4051 | if (GET_CODE (comparison) != code) | |
4052 | abort (); | |
8deb7047 | 4053 | |
44037a66 TG |
4054 | /* Get a reference to the target in the proper mode for this insn. */ |
4055 | compare_mode = insn_operand_mode[(int) icode][0]; | |
4056 | subtarget = target; | |
4057 | if (preserve_subexpressions_p () | |
4058 | || ! (*insn_operand_predicate[(int) icode][0]) (subtarget, compare_mode)) | |
4059 | subtarget = gen_reg_rtx (compare_mode); | |
4060 | ||
4061 | pattern = GEN_FCN (icode) (subtarget); | |
4062 | if (pattern) | |
4063 | { | |
4064 | emit_insn (pattern); | |
4065 | ||
4066 | /* If we are converting to a wider mode, first convert to | |
4067 | TARGET_MODE, then normalize. This produces better combining | |
4068 | opportunities on machines that have a SIGN_EXTRACT when we are | |
4069 | testing a single bit. This mostly benefits the 68k. | |
4070 | ||
4071 | If STORE_FLAG_VALUE does not have the sign bit set when | |
4072 | interpreted in COMPARE_MODE, we can do this conversion as | |
4073 | unsigned, which is usually more efficient. */ | |
4074 | if (GET_MODE_SIZE (target_mode) > GET_MODE_SIZE (compare_mode)) | |
4075 | { | |
4076 | convert_move (target, subtarget, | |
4077 | (GET_MODE_BITSIZE (compare_mode) | |
b1ec3c92 | 4078 | <= HOST_BITS_PER_WIDE_INT) |
44037a66 | 4079 | && 0 == (STORE_FLAG_VALUE |
b1ec3c92 CH |
4080 | & ((HOST_WIDE_INT) 1 |
4081 | << (GET_MODE_BITSIZE (compare_mode) -1)))); | |
44037a66 TG |
4082 | op0 = target; |
4083 | compare_mode = target_mode; | |
4084 | } | |
4085 | else | |
4086 | op0 = subtarget; | |
4087 | ||
4b980e20 RK |
4088 | /* If we want to keep subexpressions around, don't reuse our |
4089 | last target. */ | |
4090 | ||
4091 | if (preserve_subexpressions_p ()) | |
4092 | subtarget = 0; | |
4093 | ||
44037a66 TG |
4094 | /* Now normalize to the proper value in COMPARE_MODE. Sometimes |
4095 | we don't have to do anything. */ | |
4096 | if (normalizep == 0 || normalizep == STORE_FLAG_VALUE) | |
4097 | ; | |
4098 | else if (normalizep == - STORE_FLAG_VALUE) | |
4099 | op0 = expand_unop (compare_mode, neg_optab, op0, subtarget, 0); | |
4100 | ||
4101 | /* We don't want to use STORE_FLAG_VALUE < 0 below since this | |
4102 | makes it hard to use a value of just the sign bit due to | |
4103 | ANSI integer constant typing rules. */ | |
b1ec3c92 | 4104 | else if (GET_MODE_BITSIZE (compare_mode) <= HOST_BITS_PER_WIDE_INT |
44037a66 | 4105 | && (STORE_FLAG_VALUE |
b1ec3c92 CH |
4106 | & ((HOST_WIDE_INT) 1 |
4107 | << (GET_MODE_BITSIZE (compare_mode) - 1)))) | |
44037a66 TG |
4108 | op0 = expand_shift (RSHIFT_EXPR, compare_mode, op0, |
4109 | size_int (GET_MODE_BITSIZE (compare_mode) - 1), | |
4110 | subtarget, normalizep == 1); | |
4111 | else if (STORE_FLAG_VALUE & 1) | |
4112 | { | |
4113 | op0 = expand_and (op0, const1_rtx, subtarget); | |
4114 | if (normalizep == -1) | |
4115 | op0 = expand_unop (compare_mode, neg_optab, op0, op0, 0); | |
4116 | } | |
4117 | else | |
4118 | abort (); | |
4119 | ||
4120 | /* If we were converting to a smaller mode, do the | |
4121 | conversion now. */ | |
4122 | if (target_mode != compare_mode) | |
4123 | { | |
522ae84c | 4124 | convert_move (target, op0, 0); |
44037a66 TG |
4125 | return target; |
4126 | } | |
4127 | else | |
4128 | return op0; | |
4129 | } | |
4130 | } | |
4131 | ||
db2f8a07 | 4132 | delete_insns_since (last); |
44037a66 | 4133 | |
91e66235 MM |
4134 | /* If expensive optimizations, use different pseudo registers for each |
4135 | insn, instead of reusing the same pseudo. This leads to better CSE, | |
4136 | but slows down the compiler, since there are more pseudos */ | |
4137 | subtarget = (!flag_expensive_optimizations | |
4138 | && (target_mode == mode)) ? target : NULL_RTX; | |
44037a66 TG |
4139 | |
4140 | /* If we reached here, we can't do this with a scc insn. However, there | |
4141 | are some comparisons that can be done directly. For example, if | |
4142 | this is an equality comparison of integers, we can try to exclusive-or | |
4143 | (or subtract) the two operands and use a recursive call to try the | |
4144 | comparison with zero. Don't do any of these cases if branches are | |
4145 | very cheap. */ | |
4146 | ||
c8c1bde3 | 4147 | if (BRANCH_COST > 0 |
44037a66 TG |
4148 | && GET_MODE_CLASS (mode) == MODE_INT && (code == EQ || code == NE) |
4149 | && op1 != const0_rtx) | |
4150 | { | |
4151 | tem = expand_binop (mode, xor_optab, op0, op1, subtarget, 1, | |
4152 | OPTAB_WIDEN); | |
4153 | ||
4154 | if (tem == 0) | |
4155 | tem = expand_binop (mode, sub_optab, op0, op1, subtarget, 1, | |
4156 | OPTAB_WIDEN); | |
4157 | if (tem != 0) | |
4158 | tem = emit_store_flag (target, code, tem, const0_rtx, | |
4159 | mode, unsignedp, normalizep); | |
4160 | if (tem == 0) | |
4161 | delete_insns_since (last); | |
4162 | return tem; | |
4163 | } | |
4164 | ||
4165 | /* Some other cases we can do are EQ, NE, LE, and GT comparisons with | |
4166 | the constant zero. Reject all other comparisons at this point. Only | |
4167 | do LE and GT if branches are expensive since they are expensive on | |
4168 | 2-operand machines. */ | |
4169 | ||
4170 | if (BRANCH_COST == 0 | |
4171 | || GET_MODE_CLASS (mode) != MODE_INT || op1 != const0_rtx | |
4172 | || (code != EQ && code != NE | |
4173 | && (BRANCH_COST <= 1 || (code != LE && code != GT)))) | |
4174 | return 0; | |
4175 | ||
4176 | /* See what we need to return. We can only return a 1, -1, or the | |
4177 | sign bit. */ | |
4178 | ||
4179 | if (normalizep == 0) | |
4180 | { | |
4181 | if (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1) | |
4182 | normalizep = STORE_FLAG_VALUE; | |
4183 | ||
b1ec3c92 | 4184 | else if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT |
12dd565f | 4185 | && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode)) |
b1ec3c92 | 4186 | == (HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))) |
44037a66 TG |
4187 | ; |
4188 | else | |
4189 | return 0; | |
4190 | } | |
4191 | ||
4192 | /* Try to put the result of the comparison in the sign bit. Assume we can't | |
4193 | do the necessary operation below. */ | |
4194 | ||
4195 | tem = 0; | |
4196 | ||
4197 | /* To see if A <= 0, compute (A | (A - 1)). A <= 0 iff that result has | |
4198 | the sign bit set. */ | |
4199 | ||
4200 | if (code == LE) | |
4201 | { | |
4202 | /* This is destructive, so SUBTARGET can't be OP0. */ | |
4203 | if (rtx_equal_p (subtarget, op0)) | |
4204 | subtarget = 0; | |
4205 | ||
4206 | tem = expand_binop (mode, sub_optab, op0, const1_rtx, subtarget, 0, | |
4207 | OPTAB_WIDEN); | |
4208 | if (tem) | |
4209 | tem = expand_binop (mode, ior_optab, op0, tem, subtarget, 0, | |
4210 | OPTAB_WIDEN); | |
4211 | } | |
4212 | ||
4213 | /* To see if A > 0, compute (((signed) A) << BITS) - A, where BITS is the | |
4214 | number of bits in the mode of OP0, minus one. */ | |
4215 | ||
4216 | if (code == GT) | |
4217 | { | |
4218 | if (rtx_equal_p (subtarget, op0)) | |
4219 | subtarget = 0; | |
4220 | ||
4221 | tem = expand_shift (RSHIFT_EXPR, mode, op0, | |
4222 | size_int (GET_MODE_BITSIZE (mode) - 1), | |
4223 | subtarget, 0); | |
4224 | tem = expand_binop (mode, sub_optab, tem, op0, subtarget, 0, | |
4225 | OPTAB_WIDEN); | |
4226 | } | |
4227 | ||
4228 | if (code == EQ || code == NE) | |
4229 | { | |
4230 | /* For EQ or NE, one way to do the comparison is to apply an operation | |
4231 | that converts the operand into a positive number if it is non-zero | |
4232 | or zero if it was originally zero. Then, for EQ, we subtract 1 and | |
4233 | for NE we negate. This puts the result in the sign bit. Then we | |
4234 | normalize with a shift, if needed. | |
4235 | ||
4236 | Two operations that can do the above actions are ABS and FFS, so try | |
4237 | them. If that doesn't work, and MODE is smaller than a full word, | |
36d747f6 | 4238 | we can use zero-extension to the wider mode (an unsigned conversion) |
44037a66 TG |
4239 | as the operation. */ |
4240 | ||
4241 | if (abs_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing) | |
4242 | tem = expand_unop (mode, abs_optab, op0, subtarget, 1); | |
4243 | else if (ffs_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing) | |
4244 | tem = expand_unop (mode, ffs_optab, op0, subtarget, 1); | |
4245 | else if (GET_MODE_SIZE (mode) < UNITS_PER_WORD) | |
4246 | { | |
b3d4e1b2 | 4247 | op0 = protect_from_queue (op0, 0); |
c2ec26b8 | 4248 | tem = convert_modes (word_mode, mode, op0, 1); |
81722fa9 | 4249 | mode = word_mode; |
44037a66 TG |
4250 | } |
4251 | ||
4252 | if (tem != 0) | |
4253 | { | |
4254 | if (code == EQ) | |
4255 | tem = expand_binop (mode, sub_optab, tem, const1_rtx, subtarget, | |
4256 | 0, OPTAB_WIDEN); | |
4257 | else | |
4258 | tem = expand_unop (mode, neg_optab, tem, subtarget, 0); | |
4259 | } | |
4260 | ||
4261 | /* If we couldn't do it that way, for NE we can "or" the two's complement | |
4262 | of the value with itself. For EQ, we take the one's complement of | |
4263 | that "or", which is an extra insn, so we only handle EQ if branches | |
4264 | are expensive. */ | |
4265 | ||
4266 | if (tem == 0 && (code == NE || BRANCH_COST > 1)) | |
4267 | { | |
36d747f6 RS |
4268 | if (rtx_equal_p (subtarget, op0)) |
4269 | subtarget = 0; | |
4270 | ||
44037a66 TG |
4271 | tem = expand_unop (mode, neg_optab, op0, subtarget, 0); |
4272 | tem = expand_binop (mode, ior_optab, tem, op0, subtarget, 0, | |
4273 | OPTAB_WIDEN); | |
4274 | ||
4275 | if (tem && code == EQ) | |
4276 | tem = expand_unop (mode, one_cmpl_optab, tem, subtarget, 0); | |
4277 | } | |
4278 | } | |
4279 | ||
4280 | if (tem && normalizep) | |
4281 | tem = expand_shift (RSHIFT_EXPR, mode, tem, | |
4282 | size_int (GET_MODE_BITSIZE (mode) - 1), | |
91e66235 | 4283 | subtarget, normalizep == 1); |
44037a66 | 4284 | |
91e66235 | 4285 | if (tem) |
44037a66 | 4286 | { |
91e66235 MM |
4287 | if (GET_MODE (tem) != target_mode) |
4288 | { | |
4289 | convert_move (target, tem, 0); | |
4290 | tem = target; | |
4291 | } | |
4292 | else if (!subtarget) | |
4293 | { | |
4294 | emit_move_insn (target, tem); | |
4295 | tem = target; | |
4296 | } | |
44037a66 | 4297 | } |
91e66235 | 4298 | else |
44037a66 TG |
4299 | delete_insns_since (last); |
4300 | ||
4301 | return tem; | |
4302 | } | |
04a8ee2f TG |
4303 | |
4304 | /* Like emit_store_flag, but always succeeds. */ | |
4305 | ||
4306 | rtx | |
4307 | emit_store_flag_force (target, code, op0, op1, mode, unsignedp, normalizep) | |
4308 | rtx target; | |
4309 | enum rtx_code code; | |
4310 | rtx op0, op1; | |
4311 | enum machine_mode mode; | |
4312 | int unsignedp; | |
4313 | int normalizep; | |
4314 | { | |
4315 | rtx tem, label; | |
4316 | ||
4317 | /* First see if emit_store_flag can do the job. */ | |
4318 | tem = emit_store_flag (target, code, op0, op1, mode, unsignedp, normalizep); | |
4319 | if (tem != 0) | |
4320 | return tem; | |
4321 | ||
4322 | if (normalizep == 0) | |
4323 | normalizep = 1; | |
4324 | ||
4325 | /* If this failed, we have to do this with set/compare/jump/set code. */ | |
4326 | ||
4327 | if (GET_CODE (target) != REG | |
4328 | || reg_mentioned_p (target, op0) || reg_mentioned_p (target, op1)) | |
4329 | target = gen_reg_rtx (GET_MODE (target)); | |
4330 | ||
e4565aff | 4331 | emit_move_insn (target, const1_rtx); |
04a8ee2f TG |
4332 | tem = compare_from_rtx (op0, op1, code, unsignedp, mode, NULL_RTX, 0); |
4333 | if (GET_CODE (tem) == CONST_INT) | |
4334 | return tem; | |
4335 | ||
4336 | label = gen_label_rtx (); | |
4337 | if (bcc_gen_fctn[(int) code] == 0) | |
4338 | abort (); | |
4339 | ||
44037a66 | 4340 | emit_jump_insn ((*bcc_gen_fctn[(int) code]) (label)); |
e4565aff | 4341 | emit_move_insn (target, const0_rtx); |
44037a66 TG |
4342 | emit_label (label); |
4343 | ||
4344 | return target; | |
4345 | } |