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Commit | Line | Data |
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44037a66 TG |
1 | /* Medium-level subroutines: convert bit-field store and extract |
2 | and shifts, multiplies and divides to rtl instructions. | |
ef58a523 JL |
3 | Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998, |
4 | 1999, 2000 Free Software Foundation, Inc. | |
44037a66 TG |
5 | |
6 | This file is part of GNU CC. | |
7 | ||
8 | GNU CC is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 2, or (at your option) | |
11 | any later version. | |
12 | ||
13 | GNU CC is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with GNU CC; see the file COPYING. If not, write to | |
940d9d63 RK |
20 | the Free Software Foundation, 59 Temple Place - Suite 330, |
21 | Boston, MA 02111-1307, USA. */ | |
44037a66 TG |
22 | |
23 | ||
24 | #include "config.h" | |
670ee920 | 25 | #include "system.h" |
01198c2f | 26 | #include "toplev.h" |
44037a66 TG |
27 | #include "rtl.h" |
28 | #include "tree.h" | |
6baf1cc8 | 29 | #include "tm_p.h" |
44037a66 TG |
30 | #include "flags.h" |
31 | #include "insn-flags.h" | |
32 | #include "insn-codes.h" | |
33 | #include "insn-config.h" | |
34 | #include "expr.h" | |
35 | #include "real.h" | |
36 | #include "recog.h" | |
37 | ||
770ae6cc RK |
38 | static void store_fixed_bit_field PARAMS ((rtx, unsigned HOST_WIDE_INT, |
39 | unsigned HOST_WIDE_INT, | |
40 | unsigned HOST_WIDE_INT, rtx, | |
729a2125 | 41 | unsigned int)); |
770ae6cc RK |
42 | static void store_split_bit_field PARAMS ((rtx, unsigned HOST_WIDE_INT, |
43 | unsigned HOST_WIDE_INT, rtx, | |
729a2125 | 44 | unsigned int)); |
770ae6cc RK |
45 | static rtx extract_fixed_bit_field PARAMS ((enum machine_mode, rtx, |
46 | unsigned HOST_WIDE_INT, | |
47 | unsigned HOST_WIDE_INT, | |
48 | unsigned HOST_WIDE_INT, | |
49 | rtx, int, unsigned int)); | |
711d877c KG |
50 | static rtx mask_rtx PARAMS ((enum machine_mode, int, |
51 | int, int)); | |
52 | static rtx lshift_value PARAMS ((enum machine_mode, rtx, | |
53 | int, int)); | |
770ae6cc RK |
54 | static rtx extract_split_bit_field PARAMS ((rtx, unsigned HOST_WIDE_INT, |
55 | unsigned HOST_WIDE_INT, int, | |
729a2125 | 56 | unsigned int)); |
711d877c KG |
57 | static void do_cmp_and_jump PARAMS ((rtx, rtx, enum rtx_code, |
58 | enum machine_mode, rtx)); | |
44037a66 | 59 | |
44037a66 TG |
60 | /* Non-zero means divides or modulus operations are relatively cheap for |
61 | powers of two, so don't use branches; emit the operation instead. | |
62 | Usually, this will mean that the MD file will emit non-branch | |
63 | sequences. */ | |
64 | ||
65 | static int sdiv_pow2_cheap, smod_pow2_cheap; | |
66 | ||
c7e33f89 | 67 | #ifndef SLOW_UNALIGNED_ACCESS |
e1565e65 | 68 | #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) STRICT_ALIGNMENT |
c7e33f89 RS |
69 | #endif |
70 | ||
e49a094d RS |
71 | /* For compilers that support multiple targets with different word sizes, |
72 | MAX_BITS_PER_WORD contains the biggest value of BITS_PER_WORD. An example | |
73 | is the H8/300(H) compiler. */ | |
74 | ||
75 | #ifndef MAX_BITS_PER_WORD | |
76 | #define MAX_BITS_PER_WORD BITS_PER_WORD | |
77 | #endif | |
78 | ||
c5c76735 JL |
79 | /* Cost of various pieces of RTL. Note that some of these are indexed by |
80 | shift count and some by mode. */ | |
819126a6 | 81 | static int add_cost, negate_cost, zero_cost; |
e49a094d RS |
82 | static int shift_cost[MAX_BITS_PER_WORD]; |
83 | static int shiftadd_cost[MAX_BITS_PER_WORD]; | |
84 | static int shiftsub_cost[MAX_BITS_PER_WORD]; | |
71af73bb TG |
85 | static int mul_cost[NUM_MACHINE_MODES]; |
86 | static int div_cost[NUM_MACHINE_MODES]; | |
87 | static int mul_widen_cost[NUM_MACHINE_MODES]; | |
88 | static int mul_highpart_cost[NUM_MACHINE_MODES]; | |
44037a66 | 89 | |
44037a66 TG |
90 | void |
91 | init_expmed () | |
92 | { | |
44037a66 TG |
93 | /* This is "some random pseudo register" for purposes of calling recog |
94 | to see what insns exist. */ | |
38a448ca | 95 | rtx reg = gen_rtx_REG (word_mode, 10000); |
b385aeda | 96 | rtx shift_insn, shiftadd_insn, shiftsub_insn; |
b1ec3c92 | 97 | int dummy; |
7963ac37 | 98 | int m; |
71af73bb | 99 | enum machine_mode mode, wider_mode; |
44037a66 | 100 | |
b385aeda RK |
101 | start_sequence (); |
102 | ||
c5c76735 | 103 | reg = gen_rtx_REG (word_mode, 10000); |
9ec36da5 | 104 | |
172a1cb0 | 105 | zero_cost = rtx_cost (const0_rtx, 0); |
38a448ca RH |
106 | add_cost = rtx_cost (gen_rtx_PLUS (word_mode, reg, reg), SET); |
107 | ||
108 | shift_insn = emit_insn (gen_rtx_SET (VOIDmode, reg, | |
109 | gen_rtx_ASHIFT (word_mode, reg, | |
110 | const0_rtx))); | |
111 | ||
112 | shiftadd_insn | |
113 | = emit_insn (gen_rtx_SET (VOIDmode, reg, | |
114 | gen_rtx_PLUS (word_mode, | |
115 | gen_rtx_MULT (word_mode, | |
116 | reg, const0_rtx), | |
117 | reg))); | |
118 | ||
119 | shiftsub_insn | |
120 | = emit_insn (gen_rtx_SET (VOIDmode, reg, | |
121 | gen_rtx_MINUS (word_mode, | |
122 | gen_rtx_MULT (word_mode, | |
123 | reg, const0_rtx), | |
124 | reg))); | |
7963ac37 RK |
125 | |
126 | init_recog (); | |
b385aeda RK |
127 | |
128 | shift_cost[0] = 0; | |
129 | shiftadd_cost[0] = shiftsub_cost[0] = add_cost; | |
130 | ||
55a6ba9f | 131 | for (m = 1; m < MAX_BITS_PER_WORD; m++) |
7963ac37 RK |
132 | { |
133 | shift_cost[m] = shiftadd_cost[m] = shiftsub_cost[m] = 32000; | |
b385aeda RK |
134 | |
135 | XEXP (SET_SRC (PATTERN (shift_insn)), 1) = GEN_INT (m); | |
136 | if (recog (PATTERN (shift_insn), shift_insn, &dummy) >= 0) | |
137 | shift_cost[m] = rtx_cost (SET_SRC (PATTERN (shift_insn)), SET); | |
138 | ||
139 | XEXP (XEXP (SET_SRC (PATTERN (shiftadd_insn)), 0), 1) | |
140 | = GEN_INT ((HOST_WIDE_INT) 1 << m); | |
141 | if (recog (PATTERN (shiftadd_insn), shiftadd_insn, &dummy) >= 0) | |
dac57de0 | 142 | shiftadd_cost[m] = rtx_cost (SET_SRC (PATTERN (shiftadd_insn)), SET); |
b385aeda RK |
143 | |
144 | XEXP (XEXP (SET_SRC (PATTERN (shiftsub_insn)), 0), 1) | |
145 | = GEN_INT ((HOST_WIDE_INT) 1 << m); | |
146 | if (recog (PATTERN (shiftsub_insn), shiftsub_insn, &dummy) >= 0) | |
dac57de0 | 147 | shiftsub_cost[m] = rtx_cost (SET_SRC (PATTERN (shiftsub_insn)), SET); |
7963ac37 RK |
148 | } |
149 | ||
38a448ca | 150 | negate_cost = rtx_cost (gen_rtx_NEG (word_mode, reg), SET); |
44037a66 | 151 | |
44037a66 | 152 | sdiv_pow2_cheap |
38a448ca | 153 | = (rtx_cost (gen_rtx_DIV (word_mode, reg, GEN_INT (32)), SET) |
b385aeda | 154 | <= 2 * add_cost); |
44037a66 | 155 | smod_pow2_cheap |
38a448ca | 156 | = (rtx_cost (gen_rtx_MOD (word_mode, reg, GEN_INT (32)), SET) |
b385aeda | 157 | <= 2 * add_cost); |
44037a66 | 158 | |
71af73bb TG |
159 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT); |
160 | mode != VOIDmode; | |
161 | mode = GET_MODE_WIDER_MODE (mode)) | |
162 | { | |
38a448ca RH |
163 | reg = gen_rtx_REG (mode, 10000); |
164 | div_cost[(int) mode] = rtx_cost (gen_rtx_UDIV (mode, reg, reg), SET); | |
165 | mul_cost[(int) mode] = rtx_cost (gen_rtx_MULT (mode, reg, reg), SET); | |
71af73bb TG |
166 | wider_mode = GET_MODE_WIDER_MODE (mode); |
167 | if (wider_mode != VOIDmode) | |
168 | { | |
169 | mul_widen_cost[(int) wider_mode] | |
38a448ca RH |
170 | = rtx_cost (gen_rtx_MULT (wider_mode, |
171 | gen_rtx_ZERO_EXTEND (wider_mode, reg), | |
172 | gen_rtx_ZERO_EXTEND (wider_mode, reg)), | |
71af73bb TG |
173 | SET); |
174 | mul_highpart_cost[(int) mode] | |
38a448ca RH |
175 | = rtx_cost (gen_rtx_TRUNCATE |
176 | (mode, | |
c5c76735 JL |
177 | gen_rtx_LSHIFTRT (wider_mode, |
178 | gen_rtx_MULT (wider_mode, | |
179 | gen_rtx_ZERO_EXTEND | |
180 | (wider_mode, reg), | |
181 | gen_rtx_ZERO_EXTEND | |
182 | (wider_mode, reg)), | |
183 | GEN_INT (GET_MODE_BITSIZE (mode)))), | |
71af73bb TG |
184 | SET); |
185 | } | |
186 | } | |
187 | ||
b385aeda | 188 | end_sequence (); |
44037a66 TG |
189 | } |
190 | ||
191 | /* Return an rtx representing minus the value of X. | |
192 | MODE is the intended mode of the result, | |
193 | useful if X is a CONST_INT. */ | |
194 | ||
195 | rtx | |
196 | negate_rtx (mode, x) | |
197 | enum machine_mode mode; | |
198 | rtx x; | |
199 | { | |
a39a7484 RK |
200 | rtx result = simplify_unary_operation (NEG, mode, x, mode); |
201 | ||
fdb5537f | 202 | if (result == 0) |
a39a7484 RK |
203 | result = expand_unop (mode, neg_optab, x, NULL_RTX, 0); |
204 | ||
205 | return result; | |
44037a66 TG |
206 | } |
207 | \f | |
208 | /* Generate code to store value from rtx VALUE | |
209 | into a bit-field within structure STR_RTX | |
210 | containing BITSIZE bits starting at bit BITNUM. | |
211 | FIELDMODE is the machine-mode of the FIELD_DECL node for this field. | |
0e805f81 | 212 | ALIGN is the alignment that STR_RTX is known to have. |
44037a66 TG |
213 | TOTAL_SIZE is the size of the structure in bytes, or -1 if varying. */ |
214 | ||
215 | /* ??? Note that there are two different ideas here for how | |
216 | to determine the size to count bits within, for a register. | |
217 | One is BITS_PER_WORD, and the other is the size of operand 3 | |
0d8e55d8 JL |
218 | of the insv pattern. |
219 | ||
220 | If operand 3 of the insv pattern is VOIDmode, then we will use BITS_PER_WORD | |
221 | else, we use the mode of operand 3. */ | |
44037a66 TG |
222 | |
223 | rtx | |
224 | store_bit_field (str_rtx, bitsize, bitnum, fieldmode, value, align, total_size) | |
225 | rtx str_rtx; | |
770ae6cc RK |
226 | unsigned HOST_WIDE_INT bitsize; |
227 | unsigned HOST_WIDE_INT bitnum; | |
44037a66 TG |
228 | enum machine_mode fieldmode; |
229 | rtx value; | |
729a2125 | 230 | unsigned int align; |
770ae6cc | 231 | HOST_WIDE_INT total_size; |
44037a66 | 232 | { |
770ae6cc RK |
233 | unsigned int unit |
234 | = (GET_CODE (str_rtx) == MEM) ? BITS_PER_UNIT : BITS_PER_WORD; | |
235 | unsigned HOST_WIDE_INT offset = bitnum / unit; | |
236 | unsigned HOST_WIDE_INT bitpos = bitnum % unit; | |
44037a66 | 237 | register rtx op0 = str_rtx; |
0d8e55d8 | 238 | #ifdef HAVE_insv |
770ae6cc | 239 | unsigned HOST_WIDE_INT insv_bitsize; |
a995e389 | 240 | enum machine_mode op_mode; |
0d8e55d8 | 241 | |
a995e389 RH |
242 | op_mode = insn_data[(int) CODE_FOR_insv].operand[3].mode; |
243 | if (op_mode == VOIDmode) | |
244 | op_mode = word_mode; | |
245 | insv_bitsize = GET_MODE_BITSIZE (op_mode); | |
0d8e55d8 | 246 | #endif |
44037a66 | 247 | |
2f5c7f45 GK |
248 | /* It is wrong to have align==0, since every object is aligned at |
249 | least at a bit boundary. This usually means a bug elsewhere. */ | |
250 | if (align == 0) | |
251 | abort (); | |
252 | ||
44037a66 TG |
253 | /* Discount the part of the structure before the desired byte. |
254 | We need to know how many bytes are safe to reference after it. */ | |
255 | if (total_size >= 0) | |
256 | total_size -= (bitpos / BIGGEST_ALIGNMENT | |
257 | * (BIGGEST_ALIGNMENT / BITS_PER_UNIT)); | |
258 | ||
259 | while (GET_CODE (op0) == SUBREG) | |
260 | { | |
261 | /* The following line once was done only if WORDS_BIG_ENDIAN, | |
262 | but I think that is a mistake. WORDS_BIG_ENDIAN is | |
263 | meaningful at a much higher level; when structures are copied | |
264 | between memory and regs, the higher-numbered regs | |
265 | always get higher addresses. */ | |
266 | offset += SUBREG_WORD (op0); | |
267 | /* We used to adjust BITPOS here, but now we do the whole adjustment | |
268 | right after the loop. */ | |
269 | op0 = SUBREG_REG (op0); | |
270 | } | |
271 | ||
d006aa54 RH |
272 | /* Make sure we are playing with integral modes. Pun with subregs |
273 | if we aren't. */ | |
274 | { | |
275 | enum machine_mode imode = int_mode_for_mode (GET_MODE (op0)); | |
276 | if (imode != GET_MODE (op0)) | |
277 | { | |
278 | if (GET_CODE (op0) == MEM) | |
279 | op0 = change_address (op0, imode, NULL_RTX); | |
280 | else if (imode != BLKmode) | |
281 | op0 = gen_lowpart (imode, op0); | |
282 | else | |
283 | abort (); | |
284 | } | |
285 | } | |
286 | ||
44037a66 TG |
287 | /* If OP0 is a register, BITPOS must count within a word. |
288 | But as we have it, it counts within whatever size OP0 now has. | |
289 | On a bigendian machine, these are not the same, so convert. */ | |
f76b9db2 ILT |
290 | if (BYTES_BIG_ENDIAN |
291 | && GET_CODE (op0) != MEM | |
292 | && unit > GET_MODE_BITSIZE (GET_MODE (op0))) | |
44037a66 | 293 | bitpos += unit - GET_MODE_BITSIZE (GET_MODE (op0)); |
44037a66 TG |
294 | |
295 | value = protect_from_queue (value, 0); | |
296 | ||
297 | if (flag_force_mem) | |
298 | value = force_not_mem (value); | |
299 | ||
308ecea0 RH |
300 | /* If the target is a register, overwriting the entire object, or storing |
301 | a full-word or multi-word field can be done with just a SUBREG. | |
302 | ||
303 | If the target is memory, storing any naturally aligned field can be | |
304 | done with a simple store. For targets that support fast unaligned | |
305 | memory, any naturally sized, unit aligned field can be done directly. */ | |
306 | ||
307 | if (bitsize == GET_MODE_BITSIZE (fieldmode) | |
ea9ea008 RH |
308 | && (GET_CODE (op0) != MEM |
309 | ? (GET_MODE_SIZE (fieldmode) >= UNITS_PER_WORD | |
310 | || GET_MODE_SIZE (GET_MODE (op0)) == GET_MODE_SIZE (fieldmode)) | |
311 | : (! SLOW_UNALIGNED_ACCESS (fieldmode, align) | |
312 | || (offset * BITS_PER_UNIT % bitsize == 0 | |
313 | && align % GET_MODE_BITSIZE (fieldmode) == 0))) | |
308ecea0 | 314 | && (BYTES_BIG_ENDIAN ? bitpos + bitsize == unit : bitpos == 0)) |
44037a66 | 315 | { |
44037a66 | 316 | if (GET_MODE (op0) != fieldmode) |
c7e33f89 | 317 | { |
d006aa54 RH |
318 | if (GET_CODE (op0) == SUBREG) |
319 | { | |
320 | if (GET_MODE (SUBREG_REG (op0)) == fieldmode | |
321 | || GET_MODE_CLASS (fieldmode) == MODE_INT | |
322 | || GET_MODE_CLASS (fieldmode) == MODE_PARTIAL_INT) | |
323 | op0 = SUBREG_REG (op0); | |
324 | else | |
325 | /* Else we've got some float mode source being extracted into | |
326 | a different float mode destination -- this combination of | |
327 | subregs results in Severe Tire Damage. */ | |
328 | abort (); | |
329 | } | |
c7e33f89 | 330 | if (GET_CODE (op0) == REG) |
38a448ca | 331 | op0 = gen_rtx_SUBREG (fieldmode, op0, offset); |
c7e33f89 RS |
332 | else |
333 | op0 = change_address (op0, fieldmode, | |
334 | plus_constant (XEXP (op0, 0), offset)); | |
335 | } | |
44037a66 TG |
336 | emit_move_insn (op0, value); |
337 | return value; | |
338 | } | |
339 | ||
340 | /* Storing an lsb-aligned field in a register | |
341 | can be done with a movestrict instruction. */ | |
342 | ||
343 | if (GET_CODE (op0) != MEM | |
f76b9db2 | 344 | && (BYTES_BIG_ENDIAN ? bitpos + bitsize == unit : bitpos == 0) |
44037a66 | 345 | && bitsize == GET_MODE_BITSIZE (fieldmode) |
5e4900c7 JW |
346 | && (movstrict_optab->handlers[(int) fieldmode].insn_code |
347 | != CODE_FOR_nothing)) | |
44037a66 | 348 | { |
5e4900c7 JW |
349 | int icode = movstrict_optab->handlers[(int) fieldmode].insn_code; |
350 | ||
44037a66 TG |
351 | /* Get appropriate low part of the value being stored. */ |
352 | if (GET_CODE (value) == CONST_INT || GET_CODE (value) == REG) | |
353 | value = gen_lowpart (fieldmode, value); | |
354 | else if (!(GET_CODE (value) == SYMBOL_REF | |
355 | || GET_CODE (value) == LABEL_REF | |
356 | || GET_CODE (value) == CONST)) | |
357 | value = convert_to_mode (fieldmode, value, 0); | |
358 | ||
5e4900c7 JW |
359 | if (! (*insn_data[icode].operand[1].predicate) (value, fieldmode)) |
360 | value = copy_to_mode_reg (fieldmode, value); | |
361 | ||
362 | if (GET_CODE (op0) == SUBREG) | |
44037a66 | 363 | { |
5e4900c7 JW |
364 | if (GET_MODE (SUBREG_REG (op0)) == fieldmode |
365 | || GET_MODE_CLASS (fieldmode) == MODE_INT | |
366 | || GET_MODE_CLASS (fieldmode) == MODE_PARTIAL_INT) | |
367 | op0 = SUBREG_REG (op0); | |
368 | else | |
369 | /* Else we've got some float mode source being extracted into | |
370 | a different float mode destination -- this combination of | |
371 | subregs results in Severe Tire Damage. */ | |
372 | abort (); | |
373 | } | |
470032d7 | 374 | |
5e4900c7 JW |
375 | emit_insn (GEN_FCN (icode) |
376 | (gen_rtx_SUBREG (fieldmode, op0, offset), value)); | |
470032d7 | 377 | |
44037a66 TG |
378 | return value; |
379 | } | |
380 | ||
381 | /* Handle fields bigger than a word. */ | |
382 | ||
383 | if (bitsize > BITS_PER_WORD) | |
384 | { | |
385 | /* Here we transfer the words of the field | |
386 | in the order least significant first. | |
387 | This is because the most significant word is the one which may | |
ad83e87b PB |
388 | be less than full. |
389 | However, only do that if the value is not BLKmode. */ | |
390 | ||
770ae6cc RK |
391 | unsigned int backwards = WORDS_BIG_ENDIAN && fieldmode != BLKmode; |
392 | unsigned int nwords = (bitsize + (BITS_PER_WORD - 1)) / BITS_PER_WORD; | |
393 | unsigned int i; | |
44037a66 TG |
394 | |
395 | /* This is the mode we must force value to, so that there will be enough | |
396 | subwords to extract. Note that fieldmode will often (always?) be | |
397 | VOIDmode, because that is what store_field uses to indicate that this | |
398 | is a bit field, but passing VOIDmode to operand_subword_force will | |
399 | result in an abort. */ | |
400 | fieldmode = mode_for_size (nwords * BITS_PER_WORD, MODE_INT, 0); | |
401 | ||
402 | for (i = 0; i < nwords; i++) | |
403 | { | |
ad83e87b PB |
404 | /* If I is 0, use the low-order word in both field and target; |
405 | if I is 1, use the next to lowest word; and so on. */ | |
770ae6cc RK |
406 | unsigned int wordnum = (backwards ? nwords - i - 1 : i); |
407 | unsigned int bit_offset = (backwards | |
408 | ? MAX ((int) bitsize - ((int) i + 1) | |
409 | * BITS_PER_WORD, | |
410 | 0) | |
411 | : (int) i * BITS_PER_WORD); | |
412 | ||
44037a66 TG |
413 | store_bit_field (op0, MIN (BITS_PER_WORD, |
414 | bitsize - i * BITS_PER_WORD), | |
415 | bitnum + bit_offset, word_mode, | |
b3487765 RS |
416 | operand_subword_force (value, wordnum, |
417 | (GET_MODE (value) == VOIDmode | |
418 | ? fieldmode | |
419 | : GET_MODE (value))), | |
44037a66 TG |
420 | align, total_size); |
421 | } | |
422 | return value; | |
423 | } | |
424 | ||
425 | /* From here on we can assume that the field to be stored in is | |
426 | a full-word (whatever type that is), since it is shorter than a word. */ | |
427 | ||
428 | /* OFFSET is the number of words or bytes (UNIT says which) | |
429 | from STR_RTX to the first word or byte containing part of the field. */ | |
430 | ||
470032d7 | 431 | if (GET_CODE (op0) != MEM) |
44037a66 TG |
432 | { |
433 | if (offset != 0 | |
434 | || GET_MODE_SIZE (GET_MODE (op0)) > UNITS_PER_WORD) | |
470032d7 RH |
435 | { |
436 | if (GET_CODE (op0) != REG) | |
7be7a07d JW |
437 | { |
438 | /* Since this is a destination (lvalue), we can't copy it to a | |
439 | pseudo. We can trivially remove a SUBREG that does not | |
440 | change the size of the operand. Such a SUBREG may have been | |
441 | added above. Otherwise, abort. */ | |
442 | if (GET_CODE (op0) == SUBREG | |
443 | && (GET_MODE_SIZE (GET_MODE (op0)) | |
444 | == GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))) | |
445 | op0 = SUBREG_REG (op0); | |
446 | else | |
447 | abort (); | |
448 | } | |
470032d7 RH |
449 | op0 = gen_rtx_SUBREG (mode_for_size (BITS_PER_WORD, MODE_INT, 0), |
450 | op0, offset); | |
451 | } | |
44037a66 TG |
452 | offset = 0; |
453 | } | |
454 | else | |
455 | { | |
456 | op0 = protect_from_queue (op0, 1); | |
457 | } | |
458 | ||
2305bcad JW |
459 | /* If VALUE is a floating-point mode, access it as an integer of the |
460 | corresponding size. This can occur on a machine with 64 bit registers | |
461 | that uses SFmode for float. This can also occur for unaligned float | |
462 | structure fields. */ | |
463 | if (GET_MODE_CLASS (GET_MODE (value)) == MODE_FLOAT) | |
464 | { | |
465 | if (GET_CODE (value) != REG) | |
466 | value = copy_to_reg (value); | |
38a448ca | 467 | value = gen_rtx_SUBREG (word_mode, value, 0); |
2305bcad JW |
468 | } |
469 | ||
44037a66 TG |
470 | /* Now OFFSET is nonzero only if OP0 is memory |
471 | and is therefore always measured in bytes. */ | |
472 | ||
473 | #ifdef HAVE_insv | |
474 | if (HAVE_insv | |
1d269b0c | 475 | && GET_MODE (value) != BLKmode |
44037a66 TG |
476 | && !(bitsize == 1 && GET_CODE (value) == CONST_INT) |
477 | /* Ensure insv's size is wide enough for this field. */ | |
0d8e55d8 | 478 | && (insv_bitsize >= bitsize) |
39e0911f | 479 | && ! ((GET_CODE (op0) == REG || GET_CODE (op0) == SUBREG) |
0d8e55d8 | 480 | && (bitsize + bitpos > insv_bitsize))) |
44037a66 TG |
481 | { |
482 | int xbitpos = bitpos; | |
483 | rtx value1; | |
484 | rtx xop0 = op0; | |
485 | rtx last = get_last_insn (); | |
486 | rtx pat; | |
0d8e55d8 | 487 | enum machine_mode maxmode; |
44037a66 | 488 | int save_volatile_ok = volatile_ok; |
0d8e55d8 | 489 | |
a995e389 | 490 | maxmode = insn_data[(int) CODE_FOR_insv].operand[3].mode; |
0d8e55d8 JL |
491 | if (maxmode == VOIDmode) |
492 | maxmode = word_mode; | |
493 | ||
44037a66 TG |
494 | volatile_ok = 1; |
495 | ||
4dbebeb2 JW |
496 | /* If this machine's insv can only insert into a register, copy OP0 |
497 | into a register and save it back later. */ | |
498 | /* This used to check flag_force_mem, but that was a serious | |
499 | de-optimization now that flag_force_mem is enabled by -O2. */ | |
44037a66 | 500 | if (GET_CODE (op0) == MEM |
a995e389 | 501 | && ! ((*insn_data[(int) CODE_FOR_insv].operand[0].predicate) |
4dbebeb2 | 502 | (op0, VOIDmode))) |
44037a66 TG |
503 | { |
504 | rtx tempreg; | |
505 | enum machine_mode bestmode; | |
506 | ||
507 | /* Get the mode to use for inserting into this field. If OP0 is | |
508 | BLKmode, get the smallest mode consistent with the alignment. If | |
509 | OP0 is a non-BLKmode object that is no wider than MAXMODE, use its | |
510 | mode. Otherwise, use the smallest mode containing the field. */ | |
511 | ||
512 | if (GET_MODE (op0) == BLKmode | |
513 | || GET_MODE_SIZE (GET_MODE (op0)) > GET_MODE_SIZE (maxmode)) | |
514 | bestmode | |
0e805f81 | 515 | = get_best_mode (bitsize, bitnum, align, maxmode, |
717702e6 | 516 | MEM_VOLATILE_P (op0)); |
44037a66 TG |
517 | else |
518 | bestmode = GET_MODE (op0); | |
519 | ||
bd5d175a | 520 | if (bestmode == VOIDmode |
e1565e65 | 521 | || (SLOW_UNALIGNED_ACCESS (bestmode, align) |
0e805f81 | 522 | && GET_MODE_BITSIZE (bestmode) > align)) |
44037a66 TG |
523 | goto insv_loses; |
524 | ||
525 | /* Adjust address to point to the containing unit of that mode. */ | |
526 | unit = GET_MODE_BITSIZE (bestmode); | |
527 | /* Compute offset as multiple of this unit, counting in bytes. */ | |
528 | offset = (bitnum / unit) * GET_MODE_SIZE (bestmode); | |
529 | bitpos = bitnum % unit; | |
530 | op0 = change_address (op0, bestmode, | |
531 | plus_constant (XEXP (op0, 0), offset)); | |
532 | ||
0e805f81 RK |
533 | /* Fetch that unit, store the bitfield in it, then store |
534 | the unit. */ | |
44037a66 TG |
535 | tempreg = copy_to_reg (op0); |
536 | store_bit_field (tempreg, bitsize, bitpos, fieldmode, value, | |
537 | align, total_size); | |
538 | emit_move_insn (op0, tempreg); | |
539 | return value; | |
540 | } | |
541 | volatile_ok = save_volatile_ok; | |
542 | ||
543 | /* Add OFFSET into OP0's address. */ | |
544 | if (GET_CODE (xop0) == MEM) | |
545 | xop0 = change_address (xop0, byte_mode, | |
546 | plus_constant (XEXP (xop0, 0), offset)); | |
547 | ||
548 | /* If xop0 is a register, we need it in MAXMODE | |
549 | to make it acceptable to the format of insv. */ | |
550 | if (GET_CODE (xop0) == SUBREG) | |
bac7cdfd DE |
551 | /* We can't just change the mode, because this might clobber op0, |
552 | and we will need the original value of op0 if insv fails. */ | |
38a448ca | 553 | xop0 = gen_rtx_SUBREG (maxmode, SUBREG_REG (xop0), SUBREG_WORD (xop0)); |
44037a66 | 554 | if (GET_CODE (xop0) == REG && GET_MODE (xop0) != maxmode) |
38a448ca | 555 | xop0 = gen_rtx_SUBREG (maxmode, xop0, 0); |
44037a66 TG |
556 | |
557 | /* On big-endian machines, we count bits from the most significant. | |
558 | If the bit field insn does not, we must invert. */ | |
559 | ||
f76b9db2 ILT |
560 | if (BITS_BIG_ENDIAN != BYTES_BIG_ENDIAN) |
561 | xbitpos = unit - bitsize - xbitpos; | |
562 | ||
44037a66 TG |
563 | /* We have been counting XBITPOS within UNIT. |
564 | Count instead within the size of the register. */ | |
f76b9db2 | 565 | if (BITS_BIG_ENDIAN && GET_CODE (xop0) != MEM) |
44037a66 | 566 | xbitpos += GET_MODE_BITSIZE (maxmode) - unit; |
f76b9db2 | 567 | |
44037a66 TG |
568 | unit = GET_MODE_BITSIZE (maxmode); |
569 | ||
570 | /* Convert VALUE to maxmode (which insv insn wants) in VALUE1. */ | |
571 | value1 = value; | |
572 | if (GET_MODE (value) != maxmode) | |
573 | { | |
574 | if (GET_MODE_BITSIZE (GET_MODE (value)) >= bitsize) | |
575 | { | |
576 | /* Optimization: Don't bother really extending VALUE | |
f5df292e RS |
577 | if it has all the bits we will actually use. However, |
578 | if we must narrow it, be sure we do it correctly. */ | |
44037a66 | 579 | |
f5df292e RS |
580 | if (GET_MODE_SIZE (GET_MODE (value)) < GET_MODE_SIZE (maxmode)) |
581 | { | |
582 | /* Avoid making subreg of a subreg, or of a mem. */ | |
583 | if (GET_CODE (value1) != REG) | |
470032d7 | 584 | value1 = copy_to_reg (value1); |
38a448ca | 585 | value1 = gen_rtx_SUBREG (maxmode, value1, 0); |
f5df292e RS |
586 | } |
587 | else | |
588 | value1 = gen_lowpart (maxmode, value1); | |
44037a66 TG |
589 | } |
590 | else if (!CONSTANT_P (value)) | |
591 | /* Parse phase is supposed to make VALUE's data type | |
592 | match that of the component reference, which is a type | |
593 | at least as wide as the field; so VALUE should have | |
594 | a mode that corresponds to that type. */ | |
595 | abort (); | |
596 | } | |
597 | ||
598 | /* If this machine's insv insists on a register, | |
599 | get VALUE1 into a register. */ | |
a995e389 | 600 | if (! ((*insn_data[(int) CODE_FOR_insv].operand[3].predicate) |
44037a66 TG |
601 | (value1, maxmode))) |
602 | value1 = force_reg (maxmode, value1); | |
603 | ||
b1ec3c92 | 604 | pat = gen_insv (xop0, GEN_INT (bitsize), GEN_INT (xbitpos), value1); |
44037a66 TG |
605 | if (pat) |
606 | emit_insn (pat); | |
607 | else | |
608 | { | |
609 | delete_insns_since (last); | |
610 | store_fixed_bit_field (op0, offset, bitsize, bitpos, value, align); | |
611 | } | |
612 | } | |
613 | else | |
614 | insv_loses: | |
615 | #endif | |
616 | /* Insv is not available; store using shifts and boolean ops. */ | |
617 | store_fixed_bit_field (op0, offset, bitsize, bitpos, value, align); | |
618 | return value; | |
619 | } | |
620 | \f | |
621 | /* Use shifts and boolean operations to store VALUE | |
622 | into a bit field of width BITSIZE | |
623 | in a memory location specified by OP0 except offset by OFFSET bytes. | |
624 | (OFFSET must be 0 if OP0 is a register.) | |
625 | The field starts at position BITPOS within the byte. | |
626 | (If OP0 is a register, it may be a full word or a narrower mode, | |
627 | but BITPOS still counts within a full word, | |
628 | which is significant on bigendian machines.) | |
0e805f81 | 629 | STRUCT_ALIGN is the alignment the structure is known to have. |
44037a66 TG |
630 | |
631 | Note that protect_from_queue has already been done on OP0 and VALUE. */ | |
632 | ||
633 | static void | |
634 | store_fixed_bit_field (op0, offset, bitsize, bitpos, value, struct_align) | |
635 | register rtx op0; | |
770ae6cc | 636 | unsigned HOST_WIDE_INT offset, bitsize, bitpos; |
44037a66 | 637 | register rtx value; |
729a2125 | 638 | unsigned int struct_align; |
44037a66 TG |
639 | { |
640 | register enum machine_mode mode; | |
770ae6cc | 641 | unsigned int total_bits = BITS_PER_WORD; |
44037a66 TG |
642 | rtx subtarget, temp; |
643 | int all_zero = 0; | |
644 | int all_one = 0; | |
645 | ||
e1565e65 | 646 | if (! SLOW_UNALIGNED_ACCESS (word_mode, struct_align)) |
2b968770 | 647 | struct_align = BIGGEST_ALIGNMENT; |
c7554b28 | 648 | |
44037a66 TG |
649 | /* There is a case not handled here: |
650 | a structure with a known alignment of just a halfword | |
651 | and a field split across two aligned halfwords within the structure. | |
652 | Or likewise a structure with a known alignment of just a byte | |
653 | and a field split across two bytes. | |
654 | Such cases are not supposed to be able to occur. */ | |
655 | ||
656 | if (GET_CODE (op0) == REG || GET_CODE (op0) == SUBREG) | |
657 | { | |
658 | if (offset != 0) | |
659 | abort (); | |
660 | /* Special treatment for a bit field split across two registers. */ | |
661 | if (bitsize + bitpos > BITS_PER_WORD) | |
662 | { | |
06c94bce RS |
663 | store_split_bit_field (op0, bitsize, bitpos, |
664 | value, BITS_PER_WORD); | |
44037a66 TG |
665 | return; |
666 | } | |
667 | } | |
668 | else | |
669 | { | |
670 | /* Get the proper mode to use for this field. We want a mode that | |
671 | includes the entire field. If such a mode would be larger than | |
672 | a word, we won't be doing the extraction the normal way. */ | |
673 | ||
674 | mode = get_best_mode (bitsize, bitpos + offset * BITS_PER_UNIT, | |
2b968770 | 675 | struct_align, word_mode, |
44037a66 TG |
676 | GET_CODE (op0) == MEM && MEM_VOLATILE_P (op0)); |
677 | ||
678 | if (mode == VOIDmode) | |
679 | { | |
680 | /* The only way this should occur is if the field spans word | |
681 | boundaries. */ | |
06c94bce RS |
682 | store_split_bit_field (op0, |
683 | bitsize, bitpos + offset * BITS_PER_UNIT, | |
44037a66 TG |
684 | value, struct_align); |
685 | return; | |
686 | } | |
687 | ||
688 | total_bits = GET_MODE_BITSIZE (mode); | |
689 | ||
3bd98790 | 690 | /* Make sure bitpos is valid for the chosen mode. Adjust BITPOS to |
38e01259 | 691 | be in the range 0 to total_bits-1, and put any excess bytes in |
3bd98790 JW |
692 | OFFSET. */ |
693 | if (bitpos >= total_bits) | |
694 | { | |
695 | offset += (bitpos / total_bits) * (total_bits / BITS_PER_UNIT); | |
696 | bitpos -= ((bitpos / total_bits) * (total_bits / BITS_PER_UNIT) | |
697 | * BITS_PER_UNIT); | |
698 | } | |
699 | ||
44037a66 TG |
700 | /* Get ref to an aligned byte, halfword, or word containing the field. |
701 | Adjust BITPOS to be position within a word, | |
702 | and OFFSET to be the offset of that word. | |
703 | Then alter OP0 to refer to that word. */ | |
704 | bitpos += (offset % (total_bits / BITS_PER_UNIT)) * BITS_PER_UNIT; | |
705 | offset -= (offset % (total_bits / BITS_PER_UNIT)); | |
706 | op0 = change_address (op0, mode, | |
707 | plus_constant (XEXP (op0, 0), offset)); | |
708 | } | |
709 | ||
710 | mode = GET_MODE (op0); | |
711 | ||
712 | /* Now MODE is either some integral mode for a MEM as OP0, | |
713 | or is a full-word for a REG as OP0. TOTAL_BITS corresponds. | |
714 | The bit field is contained entirely within OP0. | |
715 | BITPOS is the starting bit number within OP0. | |
716 | (OP0's mode may actually be narrower than MODE.) */ | |
717 | ||
f76b9db2 ILT |
718 | if (BYTES_BIG_ENDIAN) |
719 | /* BITPOS is the distance between our msb | |
720 | and that of the containing datum. | |
721 | Convert it to the distance from the lsb. */ | |
722 | bitpos = total_bits - bitsize - bitpos; | |
44037a66 | 723 | |
44037a66 TG |
724 | /* Now BITPOS is always the distance between our lsb |
725 | and that of OP0. */ | |
726 | ||
727 | /* Shift VALUE left by BITPOS bits. If VALUE is not constant, | |
728 | we must first convert its mode to MODE. */ | |
729 | ||
730 | if (GET_CODE (value) == CONST_INT) | |
731 | { | |
b1ec3c92 | 732 | register HOST_WIDE_INT v = INTVAL (value); |
44037a66 | 733 | |
b1ec3c92 CH |
734 | if (bitsize < HOST_BITS_PER_WIDE_INT) |
735 | v &= ((HOST_WIDE_INT) 1 << bitsize) - 1; | |
44037a66 TG |
736 | |
737 | if (v == 0) | |
738 | all_zero = 1; | |
b1ec3c92 CH |
739 | else if ((bitsize < HOST_BITS_PER_WIDE_INT |
740 | && v == ((HOST_WIDE_INT) 1 << bitsize) - 1) | |
741 | || (bitsize == HOST_BITS_PER_WIDE_INT && v == -1)) | |
44037a66 TG |
742 | all_one = 1; |
743 | ||
744 | value = lshift_value (mode, value, bitpos, bitsize); | |
745 | } | |
746 | else | |
747 | { | |
748 | int must_and = (GET_MODE_BITSIZE (GET_MODE (value)) != bitsize | |
749 | && bitpos + bitsize != GET_MODE_BITSIZE (mode)); | |
750 | ||
751 | if (GET_MODE (value) != mode) | |
752 | { | |
44037a66 TG |
753 | if ((GET_CODE (value) == REG || GET_CODE (value) == SUBREG) |
754 | && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (value))) | |
755 | value = gen_lowpart (mode, value); | |
756 | else | |
757 | value = convert_to_mode (mode, value, 1); | |
758 | } | |
759 | ||
760 | if (must_and) | |
761 | value = expand_binop (mode, and_optab, value, | |
762 | mask_rtx (mode, 0, bitsize, 0), | |
b1ec3c92 | 763 | NULL_RTX, 1, OPTAB_LIB_WIDEN); |
44037a66 TG |
764 | if (bitpos > 0) |
765 | value = expand_shift (LSHIFT_EXPR, mode, value, | |
b1ec3c92 | 766 | build_int_2 (bitpos, 0), NULL_RTX, 1); |
44037a66 TG |
767 | } |
768 | ||
769 | /* Now clear the chosen bits in OP0, | |
770 | except that if VALUE is -1 we need not bother. */ | |
771 | ||
772 | subtarget = (GET_CODE (op0) == REG || ! flag_force_mem) ? op0 : 0; | |
773 | ||
774 | if (! all_one) | |
775 | { | |
776 | temp = expand_binop (mode, and_optab, op0, | |
777 | mask_rtx (mode, bitpos, bitsize, 1), | |
778 | subtarget, 1, OPTAB_LIB_WIDEN); | |
779 | subtarget = temp; | |
780 | } | |
781 | else | |
782 | temp = op0; | |
783 | ||
784 | /* Now logical-or VALUE into OP0, unless it is zero. */ | |
785 | ||
786 | if (! all_zero) | |
787 | temp = expand_binop (mode, ior_optab, temp, value, | |
788 | subtarget, 1, OPTAB_LIB_WIDEN); | |
789 | if (op0 != temp) | |
790 | emit_move_insn (op0, temp); | |
791 | } | |
792 | \f | |
06c94bce | 793 | /* Store a bit field that is split across multiple accessible memory objects. |
44037a66 | 794 | |
06c94bce | 795 | OP0 is the REG, SUBREG or MEM rtx for the first of the objects. |
44037a66 TG |
796 | BITSIZE is the field width; BITPOS the position of its first bit |
797 | (within the word). | |
06c94bce | 798 | VALUE is the value to store. |
0e805f81 | 799 | ALIGN is the known alignment of OP0. |
06c94bce RS |
800 | This is also the size of the memory objects to be used. |
801 | ||
802 | This does not yet handle fields wider than BITS_PER_WORD. */ | |
44037a66 TG |
803 | |
804 | static void | |
805 | store_split_bit_field (op0, bitsize, bitpos, value, align) | |
806 | rtx op0; | |
770ae6cc | 807 | unsigned HOST_WIDE_INT bitsize, bitpos; |
44037a66 | 808 | rtx value; |
729a2125 | 809 | unsigned int align; |
44037a66 | 810 | { |
770ae6cc RK |
811 | unsigned int unit; |
812 | unsigned int bitsdone = 0; | |
4ee16841 | 813 | |
0eb61c19 DE |
814 | /* Make sure UNIT isn't larger than BITS_PER_WORD, we can only handle that |
815 | much at a time. */ | |
4ee16841 DE |
816 | if (GET_CODE (op0) == REG || GET_CODE (op0) == SUBREG) |
817 | unit = BITS_PER_WORD; | |
818 | else | |
0e805f81 | 819 | unit = MIN (align, BITS_PER_WORD); |
e54d80d0 | 820 | |
3d709ff0 RS |
821 | /* If VALUE is a constant other than a CONST_INT, get it into a register in |
822 | WORD_MODE. If we can do this using gen_lowpart_common, do so. Note | |
823 | that VALUE might be a floating-point constant. */ | |
44037a66 | 824 | if (CONSTANT_P (value) && GET_CODE (value) != CONST_INT) |
3d709ff0 RS |
825 | { |
826 | rtx word = gen_lowpart_common (word_mode, value); | |
827 | ||
bc8a0e39 | 828 | if (word && (value != word)) |
3d709ff0 RS |
829 | value = word; |
830 | else | |
831 | value = gen_lowpart_common (word_mode, | |
d01bc862 DE |
832 | force_reg (GET_MODE (value) != VOIDmode |
833 | ? GET_MODE (value) | |
834 | : word_mode, value)); | |
3d709ff0 | 835 | } |
956d6950 JL |
836 | else if (GET_CODE (value) == ADDRESSOF) |
837 | value = copy_to_reg (value); | |
44037a66 | 838 | |
06c94bce | 839 | while (bitsdone < bitsize) |
44037a66 | 840 | { |
770ae6cc | 841 | unsigned HOST_WIDE_INT thissize; |
06c94bce | 842 | rtx part, word; |
770ae6cc RK |
843 | unsigned HOST_WIDE_INT thispos; |
844 | unsigned HOST_WIDE_INT offset; | |
44037a66 | 845 | |
06c94bce RS |
846 | offset = (bitpos + bitsdone) / unit; |
847 | thispos = (bitpos + bitsdone) % unit; | |
44037a66 | 848 | |
0eb61c19 DE |
849 | /* THISSIZE must not overrun a word boundary. Otherwise, |
850 | store_fixed_bit_field will call us again, and we will mutually | |
851 | recurse forever. */ | |
852 | thissize = MIN (bitsize - bitsdone, BITS_PER_WORD); | |
853 | thissize = MIN (thissize, unit - thispos); | |
44037a66 | 854 | |
f76b9db2 ILT |
855 | if (BYTES_BIG_ENDIAN) |
856 | { | |
37811a73 RK |
857 | int total_bits; |
858 | ||
859 | /* We must do an endian conversion exactly the same way as it is | |
860 | done in extract_bit_field, so that the two calls to | |
861 | extract_fixed_bit_field will have comparable arguments. */ | |
1d269b0c | 862 | if (GET_CODE (value) != MEM || GET_MODE (value) == BLKmode) |
37811a73 RK |
863 | total_bits = BITS_PER_WORD; |
864 | else | |
865 | total_bits = GET_MODE_BITSIZE (GET_MODE (value)); | |
866 | ||
f76b9db2 ILT |
867 | /* Fetch successively less significant portions. */ |
868 | if (GET_CODE (value) == CONST_INT) | |
869 | part = GEN_INT (((unsigned HOST_WIDE_INT) (INTVAL (value)) | |
870 | >> (bitsize - bitsdone - thissize)) | |
871 | & (((HOST_WIDE_INT) 1 << thissize) - 1)); | |
872 | else | |
873 | /* The args are chosen so that the last part includes the | |
874 | lsb. Give extract_bit_field the value it needs (with | |
3cd45606 RK |
875 | endianness compensation) to fetch the piece we want. |
876 | ||
877 | ??? We have no idea what the alignment of VALUE is, so | |
878 | we have to use a guess. */ | |
879 | part | |
880 | = extract_fixed_bit_field | |
881 | (word_mode, value, 0, thissize, | |
882 | total_bits - bitsize + bitsdone, NULL_RTX, 1, | |
883 | GET_MODE (value) == VOIDmode | |
884 | ? UNITS_PER_WORD | |
885 | : (GET_MODE (value) == BLKmode | |
0e805f81 | 886 | ? 1 : GET_MODE_ALIGNMENT (GET_MODE (value)))); |
f76b9db2 | 887 | } |
06c94bce | 888 | else |
f76b9db2 ILT |
889 | { |
890 | /* Fetch successively more significant portions. */ | |
891 | if (GET_CODE (value) == CONST_INT) | |
892 | part = GEN_INT (((unsigned HOST_WIDE_INT) (INTVAL (value)) | |
893 | >> bitsdone) | |
894 | & (((HOST_WIDE_INT) 1 << thissize) - 1)); | |
895 | else | |
3cd45606 RK |
896 | part |
897 | = extract_fixed_bit_field | |
898 | (word_mode, value, 0, thissize, bitsdone, NULL_RTX, 1, | |
899 | GET_MODE (value) == VOIDmode | |
900 | ? UNITS_PER_WORD | |
901 | : (GET_MODE (value) == BLKmode | |
0e805f81 | 902 | ? 1 : GET_MODE_ALIGNMENT (GET_MODE (value)))); |
f76b9db2 | 903 | } |
44037a66 | 904 | |
06c94bce | 905 | /* If OP0 is a register, then handle OFFSET here. |
5f57dff0 JW |
906 | |
907 | When handling multiword bitfields, extract_bit_field may pass | |
908 | down a word_mode SUBREG of a larger REG for a bitfield that actually | |
909 | crosses a word boundary. Thus, for a SUBREG, we must find | |
910 | the current word starting from the base register. */ | |
911 | if (GET_CODE (op0) == SUBREG) | |
912 | { | |
4ee16841 DE |
913 | word = operand_subword_force (SUBREG_REG (op0), |
914 | SUBREG_WORD (op0) + offset, | |
915 | GET_MODE (SUBREG_REG (op0))); | |
5f57dff0 JW |
916 | offset = 0; |
917 | } | |
918 | else if (GET_CODE (op0) == REG) | |
06c94bce | 919 | { |
4ee16841 | 920 | word = operand_subword_force (op0, offset, GET_MODE (op0)); |
06c94bce RS |
921 | offset = 0; |
922 | } | |
923 | else | |
924 | word = op0; | |
44037a66 | 925 | |
0eb61c19 DE |
926 | /* OFFSET is in UNITs, and UNIT is in bits. |
927 | store_fixed_bit_field wants offset in bytes. */ | |
928 | store_fixed_bit_field (word, offset * unit / BITS_PER_UNIT, | |
929 | thissize, thispos, part, align); | |
06c94bce RS |
930 | bitsdone += thissize; |
931 | } | |
44037a66 TG |
932 | } |
933 | \f | |
934 | /* Generate code to extract a byte-field from STR_RTX | |
935 | containing BITSIZE bits, starting at BITNUM, | |
936 | and put it in TARGET if possible (if TARGET is nonzero). | |
937 | Regardless of TARGET, we return the rtx for where the value is placed. | |
938 | It may be a QUEUED. | |
939 | ||
940 | STR_RTX is the structure containing the byte (a REG or MEM). | |
941 | UNSIGNEDP is nonzero if this is an unsigned bit field. | |
942 | MODE is the natural mode of the field value once extracted. | |
943 | TMODE is the mode the caller would like the value to have; | |
944 | but the value may be returned with type MODE instead. | |
945 | ||
19caa751 | 946 | ALIGN is the alignment that STR_RTX is known to have. |
44037a66 TG |
947 | TOTAL_SIZE is the size in bytes of the containing structure, |
948 | or -1 if varying. | |
949 | ||
950 | If a TARGET is specified and we can store in it at no extra cost, | |
951 | we do so, and return TARGET. | |
952 | Otherwise, we return a REG of mode TMODE or MODE, with TMODE preferred | |
953 | if they are equally easy. */ | |
954 | ||
955 | rtx | |
956 | extract_bit_field (str_rtx, bitsize, bitnum, unsignedp, | |
957 | target, mode, tmode, align, total_size) | |
958 | rtx str_rtx; | |
770ae6cc RK |
959 | unsigned HOST_WIDE_INT bitsize; |
960 | unsigned HOST_WIDE_INT bitnum; | |
44037a66 TG |
961 | int unsignedp; |
962 | rtx target; | |
963 | enum machine_mode mode, tmode; | |
729a2125 | 964 | unsigned int align; |
770ae6cc | 965 | HOST_WIDE_INT total_size; |
44037a66 | 966 | { |
770ae6cc RK |
967 | unsigned int unit |
968 | = (GET_CODE (str_rtx) == MEM) ? BITS_PER_UNIT : BITS_PER_WORD; | |
969 | unsigned HOST_WIDE_INT offset = bitnum / unit; | |
970 | unsigned HOST_WIDE_INT bitpos = bitnum % unit; | |
44037a66 TG |
971 | register rtx op0 = str_rtx; |
972 | rtx spec_target = target; | |
973 | rtx spec_target_subreg = 0; | |
3306eb80 | 974 | enum machine_mode int_mode; |
0d8e55d8 | 975 | #ifdef HAVE_extv |
770ae6cc | 976 | unsigned HOST_WIDE_INT extv_bitsize; |
a995e389 | 977 | enum machine_mode extv_mode; |
0d8e55d8 JL |
978 | #endif |
979 | #ifdef HAVE_extzv | |
770ae6cc | 980 | unsigned HOST_WIDE_INT extzv_bitsize; |
a995e389 | 981 | enum machine_mode extzv_mode; |
0d8e55d8 JL |
982 | #endif |
983 | ||
984 | #ifdef HAVE_extv | |
a995e389 RH |
985 | extv_mode = insn_data[(int) CODE_FOR_extv].operand[0].mode; |
986 | if (extv_mode == VOIDmode) | |
987 | extv_mode = word_mode; | |
988 | extv_bitsize = GET_MODE_BITSIZE (extv_mode); | |
0d8e55d8 JL |
989 | #endif |
990 | ||
991 | #ifdef HAVE_extzv | |
a995e389 RH |
992 | extzv_mode = insn_data[(int) CODE_FOR_extzv].operand[0].mode; |
993 | if (extzv_mode == VOIDmode) | |
994 | extzv_mode = word_mode; | |
995 | extzv_bitsize = GET_MODE_BITSIZE (extzv_mode); | |
0d8e55d8 | 996 | #endif |
44037a66 | 997 | |
44037a66 TG |
998 | /* Discount the part of the structure before the desired byte. |
999 | We need to know how many bytes are safe to reference after it. */ | |
1000 | if (total_size >= 0) | |
1001 | total_size -= (bitpos / BIGGEST_ALIGNMENT | |
1002 | * (BIGGEST_ALIGNMENT / BITS_PER_UNIT)); | |
1003 | ||
1004 | if (tmode == VOIDmode) | |
1005 | tmode = mode; | |
44037a66 TG |
1006 | while (GET_CODE (op0) == SUBREG) |
1007 | { | |
64191612 MM |
1008 | int outer_size = GET_MODE_BITSIZE (GET_MODE (op0)); |
1009 | int inner_size = GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))); | |
1010 | ||
44037a66 | 1011 | offset += SUBREG_WORD (op0); |
64191612 | 1012 | |
e5e809f4 JL |
1013 | inner_size = MIN (inner_size, BITS_PER_WORD); |
1014 | ||
64191612 MM |
1015 | if (BYTES_BIG_ENDIAN && (outer_size < inner_size)) |
1016 | { | |
1017 | bitpos += inner_size - outer_size; | |
1018 | if (bitpos > unit) | |
1019 | { | |
1020 | offset += (bitpos / unit); | |
1021 | bitpos %= unit; | |
1022 | } | |
1023 | } | |
1024 | ||
44037a66 TG |
1025 | op0 = SUBREG_REG (op0); |
1026 | } | |
77295dec | 1027 | |
d006aa54 RH |
1028 | /* Make sure we are playing with integral modes. Pun with subregs |
1029 | if we aren't. */ | |
1030 | { | |
1031 | enum machine_mode imode = int_mode_for_mode (GET_MODE (op0)); | |
1032 | if (imode != GET_MODE (op0)) | |
1033 | { | |
1034 | if (GET_CODE (op0) == MEM) | |
1035 | op0 = change_address (op0, imode, NULL_RTX); | |
1036 | else if (imode != BLKmode) | |
1037 | op0 = gen_lowpart (imode, op0); | |
1038 | else | |
1039 | abort (); | |
1040 | } | |
1041 | } | |
1042 | ||
77295dec DE |
1043 | /* ??? We currently assume TARGET is at least as big as BITSIZE. |
1044 | If that's wrong, the solution is to test for it and set TARGET to 0 | |
1045 | if needed. */ | |
44037a66 | 1046 | |
44037a66 TG |
1047 | /* If OP0 is a register, BITPOS must count within a word. |
1048 | But as we have it, it counts within whatever size OP0 now has. | |
1049 | On a bigendian machine, these are not the same, so convert. */ | |
db3cf6fb MS |
1050 | if (BYTES_BIG_ENDIAN |
1051 | && GET_CODE (op0) != MEM | |
f76b9db2 | 1052 | && unit > GET_MODE_BITSIZE (GET_MODE (op0))) |
44037a66 | 1053 | bitpos += unit - GET_MODE_BITSIZE (GET_MODE (op0)); |
44037a66 TG |
1054 | |
1055 | /* Extracting a full-word or multi-word value | |
c7e33f89 | 1056 | from a structure in a register or aligned memory. |
44037a66 TG |
1057 | This can be done with just SUBREG. |
1058 | So too extracting a subword value in | |
1059 | the least significant part of the register. */ | |
1060 | ||
d006aa54 | 1061 | if (((GET_CODE (op0) != MEM |
f8fe20b2 JW |
1062 | && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode), |
1063 | GET_MODE_BITSIZE (GET_MODE (op0)))) | |
c7e33f89 | 1064 | || (GET_CODE (op0) == MEM |
e1565e65 | 1065 | && (! SLOW_UNALIGNED_ACCESS (mode, align) |
c7e33f89 | 1066 | || (offset * BITS_PER_UNIT % bitsize == 0 |
19caa751 | 1067 | && align % bitsize == 0)))) |
44037a66 TG |
1068 | && ((bitsize >= BITS_PER_WORD && bitsize == GET_MODE_BITSIZE (mode) |
1069 | && bitpos % BITS_PER_WORD == 0) | |
1070 | || (mode_for_size (bitsize, GET_MODE_CLASS (tmode), 0) != BLKmode | |
f916eeb6 NC |
1071 | /* ??? The big endian test here is wrong. This is correct |
1072 | if the value is in a register, and if mode_for_size is not | |
1073 | the same mode as op0. This causes us to get unnecessarily | |
1074 | inefficient code from the Thumb port when -mbig-endian. */ | |
f76b9db2 ILT |
1075 | && (BYTES_BIG_ENDIAN |
1076 | ? bitpos + bitsize == BITS_PER_WORD | |
1077 | : bitpos == 0)))) | |
44037a66 TG |
1078 | { |
1079 | enum machine_mode mode1 | |
0b4565c9 BS |
1080 | = (VECTOR_MODE_P (tmode) ? mode |
1081 | : mode_for_size (bitsize, GET_MODE_CLASS (tmode), 0)); | |
44037a66 TG |
1082 | |
1083 | if (mode1 != GET_MODE (op0)) | |
c7e33f89 | 1084 | { |
d006aa54 RH |
1085 | if (GET_CODE (op0) == SUBREG) |
1086 | { | |
1087 | if (GET_MODE (SUBREG_REG (op0)) == mode1 | |
1088 | || GET_MODE_CLASS (mode1) == MODE_INT | |
1089 | || GET_MODE_CLASS (mode1) == MODE_PARTIAL_INT) | |
1090 | op0 = SUBREG_REG (op0); | |
1091 | else | |
1092 | /* Else we've got some float mode source being extracted into | |
1093 | a different float mode destination -- this combination of | |
1094 | subregs results in Severe Tire Damage. */ | |
1095 | abort (); | |
1096 | } | |
c7e33f89 | 1097 | if (GET_CODE (op0) == REG) |
38a448ca | 1098 | op0 = gen_rtx_SUBREG (mode1, op0, offset); |
c7e33f89 RS |
1099 | else |
1100 | op0 = change_address (op0, mode1, | |
1101 | plus_constant (XEXP (op0, 0), offset)); | |
1102 | } | |
44037a66 TG |
1103 | if (mode1 != mode) |
1104 | return convert_to_mode (tmode, op0, unsignedp); | |
1105 | return op0; | |
1106 | } | |
1107 | ||
1108 | /* Handle fields bigger than a word. */ | |
1109 | ||
1110 | if (bitsize > BITS_PER_WORD) | |
1111 | { | |
1112 | /* Here we transfer the words of the field | |
1113 | in the order least significant first. | |
1114 | This is because the most significant word is the one which may | |
1115 | be less than full. */ | |
1116 | ||
770ae6cc RK |
1117 | unsigned int nwords = (bitsize + (BITS_PER_WORD - 1)) / BITS_PER_WORD; |
1118 | unsigned int i; | |
44037a66 TG |
1119 | |
1120 | if (target == 0 || GET_CODE (target) != REG) | |
1121 | target = gen_reg_rtx (mode); | |
1122 | ||
34ea783b | 1123 | /* Indicate for flow that the entire target reg is being set. */ |
38a448ca | 1124 | emit_insn (gen_rtx_CLOBBER (VOIDmode, target)); |
34ea783b | 1125 | |
44037a66 TG |
1126 | for (i = 0; i < nwords; i++) |
1127 | { | |
1128 | /* If I is 0, use the low-order word in both field and target; | |
1129 | if I is 1, use the next to lowest word; and so on. */ | |
77295dec | 1130 | /* Word number in TARGET to use. */ |
770ae6cc RK |
1131 | unsigned int wordnum |
1132 | = (WORDS_BIG_ENDIAN | |
1133 | ? GET_MODE_SIZE (GET_MODE (target)) / UNITS_PER_WORD - i - 1 | |
1134 | : i); | |
77295dec | 1135 | /* Offset from start of field in OP0. */ |
770ae6cc RK |
1136 | unsigned int bit_offset = (WORDS_BIG_ENDIAN |
1137 | ? MAX (0, ((int) bitsize - ((int) i + 1) | |
75131237 | 1138 | * (int) BITS_PER_WORD)) |
770ae6cc | 1139 | : (int) i * BITS_PER_WORD); |
44037a66 TG |
1140 | rtx target_part = operand_subword (target, wordnum, 1, VOIDmode); |
1141 | rtx result_part | |
1142 | = extract_bit_field (op0, MIN (BITS_PER_WORD, | |
1143 | bitsize - i * BITS_PER_WORD), | |
19caa751 RK |
1144 | bitnum + bit_offset, 1, target_part, mode, |
1145 | word_mode, align, total_size); | |
44037a66 TG |
1146 | |
1147 | if (target_part == 0) | |
1148 | abort (); | |
1149 | ||
1150 | if (result_part != target_part) | |
1151 | emit_move_insn (target_part, result_part); | |
1152 | } | |
1153 | ||
5f57dff0 | 1154 | if (unsignedp) |
77295dec DE |
1155 | { |
1156 | /* Unless we've filled TARGET, the upper regs in a multi-reg value | |
1157 | need to be zero'd out. */ | |
1158 | if (GET_MODE_SIZE (GET_MODE (target)) > nwords * UNITS_PER_WORD) | |
1159 | { | |
770ae6cc | 1160 | unsigned int i, total_words; |
77295dec DE |
1161 | |
1162 | total_words = GET_MODE_SIZE (GET_MODE (target)) / UNITS_PER_WORD; | |
1163 | for (i = nwords; i < total_words; i++) | |
1164 | { | |
1165 | int wordnum = WORDS_BIG_ENDIAN ? total_words - i - 1 : i; | |
1166 | rtx target_part = operand_subword (target, wordnum, 1, VOIDmode); | |
1167 | emit_move_insn (target_part, const0_rtx); | |
1168 | } | |
1169 | } | |
1170 | return target; | |
1171 | } | |
1172 | ||
5f57dff0 JW |
1173 | /* Signed bit field: sign-extend with two arithmetic shifts. */ |
1174 | target = expand_shift (LSHIFT_EXPR, mode, target, | |
1175 | build_int_2 (GET_MODE_BITSIZE (mode) - bitsize, 0), | |
1176 | NULL_RTX, 0); | |
1177 | return expand_shift (RSHIFT_EXPR, mode, target, | |
1178 | build_int_2 (GET_MODE_BITSIZE (mode) - bitsize, 0), | |
1179 | NULL_RTX, 0); | |
44037a66 TG |
1180 | } |
1181 | ||
3306eb80 GK |
1182 | /* From here on we know the desired field is smaller than a word. */ |
1183 | ||
1184 | /* Check if there is a correspondingly-sized integer field, so we can | |
1185 | safely extract it as one size of integer, if necessary; then | |
1186 | truncate or extend to the size that is wanted; then use SUBREGs or | |
1187 | convert_to_mode to get one of the modes we really wanted. */ | |
1188 | ||
1189 | int_mode = int_mode_for_mode (tmode); | |
1190 | if (int_mode == BLKmode) | |
1191 | int_mode = int_mode_for_mode (mode); | |
1192 | if (int_mode == BLKmode) | |
1193 | abort(); /* Should probably push op0 out to memory and then | |
1194 | do a load. */ | |
44037a66 TG |
1195 | |
1196 | /* OFFSET is the number of words or bytes (UNIT says which) | |
1197 | from STR_RTX to the first word or byte containing part of the field. */ | |
1198 | ||
d006aa54 | 1199 | if (GET_CODE (op0) != MEM) |
44037a66 TG |
1200 | { |
1201 | if (offset != 0 | |
1202 | || GET_MODE_SIZE (GET_MODE (op0)) > UNITS_PER_WORD) | |
470032d7 RH |
1203 | { |
1204 | if (GET_CODE (op0) != REG) | |
1205 | op0 = copy_to_reg (op0); | |
1206 | op0 = gen_rtx_SUBREG (mode_for_size (BITS_PER_WORD, MODE_INT, 0), | |
1207 | op0, offset); | |
1208 | } | |
44037a66 TG |
1209 | offset = 0; |
1210 | } | |
1211 | else | |
1212 | { | |
1213 | op0 = protect_from_queue (str_rtx, 1); | |
1214 | } | |
1215 | ||
1216 | /* Now OFFSET is nonzero only for memory operands. */ | |
1217 | ||
1218 | if (unsignedp) | |
1219 | { | |
1220 | #ifdef HAVE_extzv | |
1221 | if (HAVE_extzv | |
0d8e55d8 | 1222 | && (extzv_bitsize >= bitsize) |
39e0911f | 1223 | && ! ((GET_CODE (op0) == REG || GET_CODE (op0) == SUBREG) |
0d8e55d8 | 1224 | && (bitsize + bitpos > extzv_bitsize))) |
44037a66 | 1225 | { |
770ae6cc | 1226 | unsigned HOST_WIDE_INT xbitpos = bitpos, xoffset = offset; |
44037a66 | 1227 | rtx bitsize_rtx, bitpos_rtx; |
e5e809f4 | 1228 | rtx last = get_last_insn (); |
44037a66 TG |
1229 | rtx xop0 = op0; |
1230 | rtx xtarget = target; | |
1231 | rtx xspec_target = spec_target; | |
1232 | rtx xspec_target_subreg = spec_target_subreg; | |
1233 | rtx pat; | |
0d8e55d8 JL |
1234 | enum machine_mode maxmode; |
1235 | ||
a995e389 | 1236 | maxmode = insn_data[(int) CODE_FOR_extzv].operand[0].mode; |
0d8e55d8 JL |
1237 | if (maxmode == VOIDmode) |
1238 | maxmode = word_mode; | |
44037a66 TG |
1239 | |
1240 | if (GET_CODE (xop0) == MEM) | |
1241 | { | |
1242 | int save_volatile_ok = volatile_ok; | |
1243 | volatile_ok = 1; | |
1244 | ||
1245 | /* Is the memory operand acceptable? */ | |
a995e389 | 1246 | if (! ((*insn_data[(int) CODE_FOR_extzv].operand[1].predicate) |
3bf1b082 | 1247 | (xop0, GET_MODE (xop0)))) |
44037a66 TG |
1248 | { |
1249 | /* No, load into a reg and extract from there. */ | |
1250 | enum machine_mode bestmode; | |
1251 | ||
1252 | /* Get the mode to use for inserting into this field. If | |
1253 | OP0 is BLKmode, get the smallest mode consistent with the | |
1254 | alignment. If OP0 is a non-BLKmode object that is no | |
1255 | wider than MAXMODE, use its mode. Otherwise, use the | |
1256 | smallest mode containing the field. */ | |
1257 | ||
1258 | if (GET_MODE (xop0) == BLKmode | |
1259 | || (GET_MODE_SIZE (GET_MODE (op0)) | |
1260 | > GET_MODE_SIZE (maxmode))) | |
19caa751 | 1261 | bestmode = get_best_mode (bitsize, bitnum, align, maxmode, |
717702e6 | 1262 | MEM_VOLATILE_P (xop0)); |
44037a66 TG |
1263 | else |
1264 | bestmode = GET_MODE (xop0); | |
1265 | ||
bd5d175a | 1266 | if (bestmode == VOIDmode |
e1565e65 | 1267 | || (SLOW_UNALIGNED_ACCESS (bestmode, align) |
19caa751 | 1268 | && GET_MODE_BITSIZE (bestmode) > align)) |
44037a66 TG |
1269 | goto extzv_loses; |
1270 | ||
1271 | /* Compute offset as multiple of this unit, | |
1272 | counting in bytes. */ | |
1273 | unit = GET_MODE_BITSIZE (bestmode); | |
1274 | xoffset = (bitnum / unit) * GET_MODE_SIZE (bestmode); | |
1275 | xbitpos = bitnum % unit; | |
1276 | xop0 = change_address (xop0, bestmode, | |
1277 | plus_constant (XEXP (xop0, 0), | |
1278 | xoffset)); | |
1279 | /* Fetch it to a register in that size. */ | |
1280 | xop0 = force_reg (bestmode, xop0); | |
1281 | ||
1282 | /* XBITPOS counts within UNIT, which is what is expected. */ | |
1283 | } | |
1284 | else | |
1285 | /* Get ref to first byte containing part of the field. */ | |
1286 | xop0 = change_address (xop0, byte_mode, | |
1287 | plus_constant (XEXP (xop0, 0), xoffset)); | |
1288 | ||
1289 | volatile_ok = save_volatile_ok; | |
1290 | } | |
1291 | ||
1292 | /* If op0 is a register, we need it in MAXMODE (which is usually | |
1293 | SImode). to make it acceptable to the format of extzv. */ | |
1294 | if (GET_CODE (xop0) == SUBREG && GET_MODE (xop0) != maxmode) | |
e5e809f4 | 1295 | goto extzv_loses; |
44037a66 | 1296 | if (GET_CODE (xop0) == REG && GET_MODE (xop0) != maxmode) |
38a448ca | 1297 | xop0 = gen_rtx_SUBREG (maxmode, xop0, 0); |
44037a66 TG |
1298 | |
1299 | /* On big-endian machines, we count bits from the most significant. | |
1300 | If the bit field insn does not, we must invert. */ | |
f76b9db2 ILT |
1301 | if (BITS_BIG_ENDIAN != BYTES_BIG_ENDIAN) |
1302 | xbitpos = unit - bitsize - xbitpos; | |
1303 | ||
44037a66 | 1304 | /* Now convert from counting within UNIT to counting in MAXMODE. */ |
f76b9db2 | 1305 | if (BITS_BIG_ENDIAN && GET_CODE (xop0) != MEM) |
44037a66 | 1306 | xbitpos += GET_MODE_BITSIZE (maxmode) - unit; |
f76b9db2 | 1307 | |
44037a66 TG |
1308 | unit = GET_MODE_BITSIZE (maxmode); |
1309 | ||
1310 | if (xtarget == 0 | |
1311 | || (flag_force_mem && GET_CODE (xtarget) == MEM)) | |
1312 | xtarget = xspec_target = gen_reg_rtx (tmode); | |
1313 | ||
1314 | if (GET_MODE (xtarget) != maxmode) | |
1315 | { | |
1316 | if (GET_CODE (xtarget) == REG) | |
b7a09135 RS |
1317 | { |
1318 | int wider = (GET_MODE_SIZE (maxmode) | |
1319 | > GET_MODE_SIZE (GET_MODE (xtarget))); | |
1320 | xtarget = gen_lowpart (maxmode, xtarget); | |
1321 | if (wider) | |
1322 | xspec_target_subreg = xtarget; | |
1323 | } | |
44037a66 TG |
1324 | else |
1325 | xtarget = gen_reg_rtx (maxmode); | |
1326 | } | |
1327 | ||
1328 | /* If this machine's extzv insists on a register target, | |
1329 | make sure we have one. */ | |
a995e389 | 1330 | if (! ((*insn_data[(int) CODE_FOR_extzv].operand[0].predicate) |
44037a66 TG |
1331 | (xtarget, maxmode))) |
1332 | xtarget = gen_reg_rtx (maxmode); | |
1333 | ||
b1ec3c92 CH |
1334 | bitsize_rtx = GEN_INT (bitsize); |
1335 | bitpos_rtx = GEN_INT (xbitpos); | |
44037a66 TG |
1336 | |
1337 | pat = gen_extzv (protect_from_queue (xtarget, 1), | |
1338 | xop0, bitsize_rtx, bitpos_rtx); | |
1339 | if (pat) | |
1340 | { | |
1341 | emit_insn (pat); | |
1342 | target = xtarget; | |
1343 | spec_target = xspec_target; | |
1344 | spec_target_subreg = xspec_target_subreg; | |
1345 | } | |
1346 | else | |
1347 | { | |
1348 | delete_insns_since (last); | |
3306eb80 | 1349 | target = extract_fixed_bit_field (int_mode, op0, offset, bitsize, |
44037a66 TG |
1350 | bitpos, target, 1, align); |
1351 | } | |
1352 | } | |
1353 | else | |
1354 | extzv_loses: | |
1355 | #endif | |
3306eb80 GK |
1356 | target = extract_fixed_bit_field (int_mode, op0, offset, bitsize, |
1357 | bitpos, target, 1, align); | |
44037a66 TG |
1358 | } |
1359 | else | |
1360 | { | |
1361 | #ifdef HAVE_extv | |
1362 | if (HAVE_extv | |
0d8e55d8 | 1363 | && (extv_bitsize >= bitsize) |
39e0911f | 1364 | && ! ((GET_CODE (op0) == REG || GET_CODE (op0) == SUBREG) |
0d8e55d8 | 1365 | && (bitsize + bitpos > extv_bitsize))) |
44037a66 TG |
1366 | { |
1367 | int xbitpos = bitpos, xoffset = offset; | |
1368 | rtx bitsize_rtx, bitpos_rtx; | |
e5e809f4 | 1369 | rtx last = get_last_insn (); |
44037a66 TG |
1370 | rtx xop0 = op0, xtarget = target; |
1371 | rtx xspec_target = spec_target; | |
1372 | rtx xspec_target_subreg = spec_target_subreg; | |
1373 | rtx pat; | |
0d8e55d8 JL |
1374 | enum machine_mode maxmode; |
1375 | ||
a995e389 | 1376 | maxmode = insn_data[(int) CODE_FOR_extv].operand[0].mode; |
0d8e55d8 JL |
1377 | if (maxmode == VOIDmode) |
1378 | maxmode = word_mode; | |
44037a66 TG |
1379 | |
1380 | if (GET_CODE (xop0) == MEM) | |
1381 | { | |
1382 | /* Is the memory operand acceptable? */ | |
a995e389 | 1383 | if (! ((*insn_data[(int) CODE_FOR_extv].operand[1].predicate) |
44037a66 TG |
1384 | (xop0, GET_MODE (xop0)))) |
1385 | { | |
1386 | /* No, load into a reg and extract from there. */ | |
1387 | enum machine_mode bestmode; | |
1388 | ||
1389 | /* Get the mode to use for inserting into this field. If | |
1390 | OP0 is BLKmode, get the smallest mode consistent with the | |
1391 | alignment. If OP0 is a non-BLKmode object that is no | |
1392 | wider than MAXMODE, use its mode. Otherwise, use the | |
1393 | smallest mode containing the field. */ | |
1394 | ||
1395 | if (GET_MODE (xop0) == BLKmode | |
1396 | || (GET_MODE_SIZE (GET_MODE (op0)) | |
1397 | > GET_MODE_SIZE (maxmode))) | |
19caa751 | 1398 | bestmode = get_best_mode (bitsize, bitnum, align, maxmode, |
717702e6 | 1399 | MEM_VOLATILE_P (xop0)); |
44037a66 TG |
1400 | else |
1401 | bestmode = GET_MODE (xop0); | |
1402 | ||
bd5d175a | 1403 | if (bestmode == VOIDmode |
e1565e65 | 1404 | || (SLOW_UNALIGNED_ACCESS (bestmode, align) |
19caa751 | 1405 | && GET_MODE_BITSIZE (bestmode) > align)) |
44037a66 TG |
1406 | goto extv_loses; |
1407 | ||
1408 | /* Compute offset as multiple of this unit, | |
1409 | counting in bytes. */ | |
1410 | unit = GET_MODE_BITSIZE (bestmode); | |
1411 | xoffset = (bitnum / unit) * GET_MODE_SIZE (bestmode); | |
1412 | xbitpos = bitnum % unit; | |
1413 | xop0 = change_address (xop0, bestmode, | |
1414 | plus_constant (XEXP (xop0, 0), | |
1415 | xoffset)); | |
1416 | /* Fetch it to a register in that size. */ | |
1417 | xop0 = force_reg (bestmode, xop0); | |
1418 | ||
1419 | /* XBITPOS counts within UNIT, which is what is expected. */ | |
1420 | } | |
1421 | else | |
1422 | /* Get ref to first byte containing part of the field. */ | |
1423 | xop0 = change_address (xop0, byte_mode, | |
1424 | plus_constant (XEXP (xop0, 0), xoffset)); | |
1425 | } | |
1426 | ||
1427 | /* If op0 is a register, we need it in MAXMODE (which is usually | |
1428 | SImode) to make it acceptable to the format of extv. */ | |
1429 | if (GET_CODE (xop0) == SUBREG && GET_MODE (xop0) != maxmode) | |
e5e809f4 | 1430 | goto extv_loses; |
44037a66 | 1431 | if (GET_CODE (xop0) == REG && GET_MODE (xop0) != maxmode) |
38a448ca | 1432 | xop0 = gen_rtx_SUBREG (maxmode, xop0, 0); |
44037a66 TG |
1433 | |
1434 | /* On big-endian machines, we count bits from the most significant. | |
1435 | If the bit field insn does not, we must invert. */ | |
f76b9db2 ILT |
1436 | if (BITS_BIG_ENDIAN != BYTES_BIG_ENDIAN) |
1437 | xbitpos = unit - bitsize - xbitpos; | |
1438 | ||
44037a66 TG |
1439 | /* XBITPOS counts within a size of UNIT. |
1440 | Adjust to count within a size of MAXMODE. */ | |
f76b9db2 | 1441 | if (BITS_BIG_ENDIAN && GET_CODE (xop0) != MEM) |
44037a66 | 1442 | xbitpos += (GET_MODE_BITSIZE (maxmode) - unit); |
f76b9db2 | 1443 | |
44037a66 TG |
1444 | unit = GET_MODE_BITSIZE (maxmode); |
1445 | ||
1446 | if (xtarget == 0 | |
1447 | || (flag_force_mem && GET_CODE (xtarget) == MEM)) | |
1448 | xtarget = xspec_target = gen_reg_rtx (tmode); | |
1449 | ||
1450 | if (GET_MODE (xtarget) != maxmode) | |
1451 | { | |
1452 | if (GET_CODE (xtarget) == REG) | |
b7a09135 RS |
1453 | { |
1454 | int wider = (GET_MODE_SIZE (maxmode) | |
1455 | > GET_MODE_SIZE (GET_MODE (xtarget))); | |
1456 | xtarget = gen_lowpart (maxmode, xtarget); | |
1457 | if (wider) | |
1458 | xspec_target_subreg = xtarget; | |
1459 | } | |
44037a66 TG |
1460 | else |
1461 | xtarget = gen_reg_rtx (maxmode); | |
1462 | } | |
1463 | ||
1464 | /* If this machine's extv insists on a register target, | |
1465 | make sure we have one. */ | |
a995e389 | 1466 | if (! ((*insn_data[(int) CODE_FOR_extv].operand[0].predicate) |
44037a66 TG |
1467 | (xtarget, maxmode))) |
1468 | xtarget = gen_reg_rtx (maxmode); | |
1469 | ||
b1ec3c92 CH |
1470 | bitsize_rtx = GEN_INT (bitsize); |
1471 | bitpos_rtx = GEN_INT (xbitpos); | |
44037a66 TG |
1472 | |
1473 | pat = gen_extv (protect_from_queue (xtarget, 1), | |
1474 | xop0, bitsize_rtx, bitpos_rtx); | |
1475 | if (pat) | |
1476 | { | |
1477 | emit_insn (pat); | |
1478 | target = xtarget; | |
1479 | spec_target = xspec_target; | |
1480 | spec_target_subreg = xspec_target_subreg; | |
1481 | } | |
1482 | else | |
1483 | { | |
1484 | delete_insns_since (last); | |
3306eb80 | 1485 | target = extract_fixed_bit_field (int_mode, op0, offset, bitsize, |
44037a66 TG |
1486 | bitpos, target, 0, align); |
1487 | } | |
1488 | } | |
1489 | else | |
1490 | extv_loses: | |
1491 | #endif | |
3306eb80 GK |
1492 | target = extract_fixed_bit_field (int_mode, op0, offset, bitsize, |
1493 | bitpos, target, 0, align); | |
44037a66 TG |
1494 | } |
1495 | if (target == spec_target) | |
1496 | return target; | |
1497 | if (target == spec_target_subreg) | |
1498 | return spec_target; | |
1499 | if (GET_MODE (target) != tmode && GET_MODE (target) != mode) | |
1500 | { | |
1501 | /* If the target mode is floating-point, first convert to the | |
1502 | integer mode of that size and then access it as a floating-point | |
1503 | value via a SUBREG. */ | |
1504 | if (GET_MODE_CLASS (tmode) == MODE_FLOAT) | |
1505 | { | |
1506 | target = convert_to_mode (mode_for_size (GET_MODE_BITSIZE (tmode), | |
1507 | MODE_INT, 0), | |
1508 | target, unsignedp); | |
1509 | if (GET_CODE (target) != REG) | |
1510 | target = copy_to_reg (target); | |
38a448ca | 1511 | return gen_rtx_SUBREG (tmode, target, 0); |
44037a66 TG |
1512 | } |
1513 | else | |
1514 | return convert_to_mode (tmode, target, unsignedp); | |
1515 | } | |
1516 | return target; | |
1517 | } | |
1518 | \f | |
1519 | /* Extract a bit field using shifts and boolean operations | |
1520 | Returns an rtx to represent the value. | |
1521 | OP0 addresses a register (word) or memory (byte). | |
1522 | BITPOS says which bit within the word or byte the bit field starts in. | |
1523 | OFFSET says how many bytes farther the bit field starts; | |
1524 | it is 0 if OP0 is a register. | |
1525 | BITSIZE says how many bits long the bit field is. | |
1526 | (If OP0 is a register, it may be narrower than a full word, | |
1527 | but BITPOS still counts within a full word, | |
1528 | which is significant on bigendian machines.) | |
1529 | ||
1530 | UNSIGNEDP is nonzero for an unsigned bit field (don't sign-extend value). | |
1531 | If TARGET is nonzero, attempts to store the value there | |
1532 | and return TARGET, but this is not guaranteed. | |
1533 | If TARGET is not used, create a pseudo-reg of mode TMODE for the value. | |
1534 | ||
19caa751 | 1535 | ALIGN is the alignment that STR_RTX is known to have. */ |
44037a66 TG |
1536 | |
1537 | static rtx | |
1538 | extract_fixed_bit_field (tmode, op0, offset, bitsize, bitpos, | |
1539 | target, unsignedp, align) | |
1540 | enum machine_mode tmode; | |
1541 | register rtx op0, target; | |
770ae6cc | 1542 | unsigned HOST_WIDE_INT offset, bitsize, bitpos; |
44037a66 | 1543 | int unsignedp; |
729a2125 | 1544 | unsigned int align; |
44037a66 | 1545 | { |
770ae6cc | 1546 | unsigned int total_bits = BITS_PER_WORD; |
44037a66 TG |
1547 | enum machine_mode mode; |
1548 | ||
1549 | if (GET_CODE (op0) == SUBREG || GET_CODE (op0) == REG) | |
1550 | { | |
1551 | /* Special treatment for a bit field split across two registers. */ | |
1552 | if (bitsize + bitpos > BITS_PER_WORD) | |
1553 | return extract_split_bit_field (op0, bitsize, bitpos, | |
1554 | unsignedp, align); | |
1555 | } | |
1556 | else | |
1557 | { | |
1558 | /* Get the proper mode to use for this field. We want a mode that | |
1559 | includes the entire field. If such a mode would be larger than | |
1560 | a word, we won't be doing the extraction the normal way. */ | |
1561 | ||
19caa751 RK |
1562 | mode = get_best_mode (bitsize, bitpos + offset * BITS_PER_UNIT, align, |
1563 | word_mode, | |
44037a66 TG |
1564 | GET_CODE (op0) == MEM && MEM_VOLATILE_P (op0)); |
1565 | ||
1566 | if (mode == VOIDmode) | |
1567 | /* The only way this should occur is if the field spans word | |
1568 | boundaries. */ | |
1569 | return extract_split_bit_field (op0, bitsize, | |
1570 | bitpos + offset * BITS_PER_UNIT, | |
1571 | unsignedp, align); | |
1572 | ||
1573 | total_bits = GET_MODE_BITSIZE (mode); | |
1574 | ||
401db791 | 1575 | /* Make sure bitpos is valid for the chosen mode. Adjust BITPOS to |
38e01259 | 1576 | be in the range 0 to total_bits-1, and put any excess bytes in |
401db791 JW |
1577 | OFFSET. */ |
1578 | if (bitpos >= total_bits) | |
1579 | { | |
1580 | offset += (bitpos / total_bits) * (total_bits / BITS_PER_UNIT); | |
1581 | bitpos -= ((bitpos / total_bits) * (total_bits / BITS_PER_UNIT) | |
1582 | * BITS_PER_UNIT); | |
1583 | } | |
1584 | ||
44037a66 TG |
1585 | /* Get ref to an aligned byte, halfword, or word containing the field. |
1586 | Adjust BITPOS to be position within a word, | |
1587 | and OFFSET to be the offset of that word. | |
1588 | Then alter OP0 to refer to that word. */ | |
1589 | bitpos += (offset % (total_bits / BITS_PER_UNIT)) * BITS_PER_UNIT; | |
1590 | offset -= (offset % (total_bits / BITS_PER_UNIT)); | |
1591 | op0 = change_address (op0, mode, | |
1592 | plus_constant (XEXP (op0, 0), offset)); | |
1593 | } | |
1594 | ||
37811a73 RK |
1595 | mode = GET_MODE (op0); |
1596 | ||
f76b9db2 ILT |
1597 | if (BYTES_BIG_ENDIAN) |
1598 | { | |
1599 | /* BITPOS is the distance between our msb and that of OP0. | |
1600 | Convert it to the distance from the lsb. */ | |
1601 | ||
1602 | bitpos = total_bits - bitsize - bitpos; | |
1603 | } | |
44037a66 | 1604 | |
44037a66 TG |
1605 | /* Now BITPOS is always the distance between the field's lsb and that of OP0. |
1606 | We have reduced the big-endian case to the little-endian case. */ | |
1607 | ||
1608 | if (unsignedp) | |
1609 | { | |
1610 | if (bitpos) | |
1611 | { | |
1612 | /* If the field does not already start at the lsb, | |
1613 | shift it so it does. */ | |
1614 | tree amount = build_int_2 (bitpos, 0); | |
1615 | /* Maybe propagate the target for the shift. */ | |
1616 | /* But not if we will return it--could confuse integrate.c. */ | |
1617 | rtx subtarget = (target != 0 && GET_CODE (target) == REG | |
1618 | && !REG_FUNCTION_VALUE_P (target) | |
1619 | ? target : 0); | |
1620 | if (tmode != mode) subtarget = 0; | |
1621 | op0 = expand_shift (RSHIFT_EXPR, mode, op0, amount, subtarget, 1); | |
1622 | } | |
1623 | /* Convert the value to the desired mode. */ | |
1624 | if (mode != tmode) | |
1625 | op0 = convert_to_mode (tmode, op0, 1); | |
1626 | ||
1627 | /* Unless the msb of the field used to be the msb when we shifted, | |
1628 | mask out the upper bits. */ | |
1629 | ||
1630 | if (GET_MODE_BITSIZE (mode) != bitpos + bitsize | |
1631 | #if 0 | |
1632 | #ifdef SLOW_ZERO_EXTEND | |
1633 | /* Always generate an `and' if | |
1634 | we just zero-extended op0 and SLOW_ZERO_EXTEND, since it | |
0f41302f | 1635 | will combine fruitfully with the zero-extend. */ |
44037a66 TG |
1636 | || tmode != mode |
1637 | #endif | |
1638 | #endif | |
1639 | ) | |
1640 | return expand_binop (GET_MODE (op0), and_optab, op0, | |
1641 | mask_rtx (GET_MODE (op0), 0, bitsize, 0), | |
1642 | target, 1, OPTAB_LIB_WIDEN); | |
1643 | return op0; | |
1644 | } | |
1645 | ||
1646 | /* To extract a signed bit-field, first shift its msb to the msb of the word, | |
1647 | then arithmetic-shift its lsb to the lsb of the word. */ | |
1648 | op0 = force_reg (mode, op0); | |
1649 | if (mode != tmode) | |
1650 | target = 0; | |
1651 | ||
1652 | /* Find the narrowest integer mode that contains the field. */ | |
1653 | ||
1654 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT); mode != VOIDmode; | |
1655 | mode = GET_MODE_WIDER_MODE (mode)) | |
1656 | if (GET_MODE_BITSIZE (mode) >= bitsize + bitpos) | |
1657 | { | |
1658 | op0 = convert_to_mode (mode, op0, 0); | |
1659 | break; | |
1660 | } | |
1661 | ||
1662 | if (GET_MODE_BITSIZE (mode) != (bitsize + bitpos)) | |
1663 | { | |
1664 | tree amount = build_int_2 (GET_MODE_BITSIZE (mode) - (bitsize + bitpos), 0); | |
1665 | /* Maybe propagate the target for the shift. */ | |
1666 | /* But not if we will return the result--could confuse integrate.c. */ | |
1667 | rtx subtarget = (target != 0 && GET_CODE (target) == REG | |
1668 | && ! REG_FUNCTION_VALUE_P (target) | |
1669 | ? target : 0); | |
1670 | op0 = expand_shift (LSHIFT_EXPR, mode, op0, amount, subtarget, 1); | |
1671 | } | |
1672 | ||
1673 | return expand_shift (RSHIFT_EXPR, mode, op0, | |
1674 | build_int_2 (GET_MODE_BITSIZE (mode) - bitsize, 0), | |
1675 | target, 0); | |
1676 | } | |
1677 | \f | |
1678 | /* Return a constant integer (CONST_INT or CONST_DOUBLE) mask value | |
1679 | of mode MODE with BITSIZE ones followed by BITPOS zeros, or the | |
1680 | complement of that if COMPLEMENT. The mask is truncated if | |
77295dec DE |
1681 | necessary to the width of mode MODE. The mask is zero-extended if |
1682 | BITSIZE+BITPOS is too small for MODE. */ | |
44037a66 TG |
1683 | |
1684 | static rtx | |
1685 | mask_rtx (mode, bitpos, bitsize, complement) | |
1686 | enum machine_mode mode; | |
1687 | int bitpos, bitsize, complement; | |
1688 | { | |
b1ec3c92 | 1689 | HOST_WIDE_INT masklow, maskhigh; |
44037a66 | 1690 | |
b1ec3c92 CH |
1691 | if (bitpos < HOST_BITS_PER_WIDE_INT) |
1692 | masklow = (HOST_WIDE_INT) -1 << bitpos; | |
44037a66 TG |
1693 | else |
1694 | masklow = 0; | |
1695 | ||
b1ec3c92 CH |
1696 | if (bitpos + bitsize < HOST_BITS_PER_WIDE_INT) |
1697 | masklow &= ((unsigned HOST_WIDE_INT) -1 | |
1698 | >> (HOST_BITS_PER_WIDE_INT - bitpos - bitsize)); | |
44037a66 | 1699 | |
b1ec3c92 | 1700 | if (bitpos <= HOST_BITS_PER_WIDE_INT) |
44037a66 TG |
1701 | maskhigh = -1; |
1702 | else | |
b1ec3c92 | 1703 | maskhigh = (HOST_WIDE_INT) -1 << (bitpos - HOST_BITS_PER_WIDE_INT); |
44037a66 | 1704 | |
b1ec3c92 CH |
1705 | if (bitpos + bitsize > HOST_BITS_PER_WIDE_INT) |
1706 | maskhigh &= ((unsigned HOST_WIDE_INT) -1 | |
1707 | >> (2 * HOST_BITS_PER_WIDE_INT - bitpos - bitsize)); | |
44037a66 TG |
1708 | else |
1709 | maskhigh = 0; | |
1710 | ||
1711 | if (complement) | |
1712 | { | |
1713 | maskhigh = ~maskhigh; | |
1714 | masklow = ~masklow; | |
1715 | } | |
1716 | ||
1717 | return immed_double_const (masklow, maskhigh, mode); | |
1718 | } | |
1719 | ||
1720 | /* Return a constant integer (CONST_INT or CONST_DOUBLE) rtx with the value | |
1721 | VALUE truncated to BITSIZE bits and then shifted left BITPOS bits. */ | |
1722 | ||
1723 | static rtx | |
1724 | lshift_value (mode, value, bitpos, bitsize) | |
1725 | enum machine_mode mode; | |
1726 | rtx value; | |
1727 | int bitpos, bitsize; | |
1728 | { | |
b1ec3c92 CH |
1729 | unsigned HOST_WIDE_INT v = INTVAL (value); |
1730 | HOST_WIDE_INT low, high; | |
44037a66 | 1731 | |
b1ec3c92 CH |
1732 | if (bitsize < HOST_BITS_PER_WIDE_INT) |
1733 | v &= ~((HOST_WIDE_INT) -1 << bitsize); | |
44037a66 | 1734 | |
b1ec3c92 | 1735 | if (bitpos < HOST_BITS_PER_WIDE_INT) |
44037a66 TG |
1736 | { |
1737 | low = v << bitpos; | |
b1ec3c92 | 1738 | high = (bitpos > 0 ? (v >> (HOST_BITS_PER_WIDE_INT - bitpos)) : 0); |
44037a66 TG |
1739 | } |
1740 | else | |
1741 | { | |
1742 | low = 0; | |
b1ec3c92 | 1743 | high = v << (bitpos - HOST_BITS_PER_WIDE_INT); |
44037a66 TG |
1744 | } |
1745 | ||
1746 | return immed_double_const (low, high, mode); | |
1747 | } | |
1748 | \f | |
1749 | /* Extract a bit field that is split across two words | |
1750 | and return an RTX for the result. | |
1751 | ||
1752 | OP0 is the REG, SUBREG or MEM rtx for the first of the two words. | |
1753 | BITSIZE is the field width; BITPOS, position of its first bit, in the word. | |
06c94bce RS |
1754 | UNSIGNEDP is 1 if should zero-extend the contents; else sign-extend. |
1755 | ||
19caa751 RK |
1756 | ALIGN is the known alignment of OP0. This is also the size of the |
1757 | memory objects to be used. */ | |
44037a66 TG |
1758 | |
1759 | static rtx | |
1760 | extract_split_bit_field (op0, bitsize, bitpos, unsignedp, align) | |
1761 | rtx op0; | |
770ae6cc RK |
1762 | unsigned HOST_WIDE_INT bitsize, bitpos; |
1763 | int unsignedp; | |
729a2125 | 1764 | unsigned int align; |
44037a66 | 1765 | { |
770ae6cc RK |
1766 | unsigned int unit; |
1767 | unsigned int bitsdone = 0; | |
c16ddde3 | 1768 | rtx result = NULL_RTX; |
06c94bce | 1769 | int first = 1; |
44037a66 | 1770 | |
4ee16841 DE |
1771 | /* Make sure UNIT isn't larger than BITS_PER_WORD, we can only handle that |
1772 | much at a time. */ | |
1773 | if (GET_CODE (op0) == REG || GET_CODE (op0) == SUBREG) | |
1774 | unit = BITS_PER_WORD; | |
1775 | else | |
19caa751 | 1776 | unit = MIN (align, BITS_PER_WORD); |
4ee16841 | 1777 | |
06c94bce RS |
1778 | while (bitsdone < bitsize) |
1779 | { | |
770ae6cc | 1780 | unsigned HOST_WIDE_INT thissize; |
06c94bce | 1781 | rtx part, word; |
770ae6cc RK |
1782 | unsigned HOST_WIDE_INT thispos; |
1783 | unsigned HOST_WIDE_INT offset; | |
06c94bce RS |
1784 | |
1785 | offset = (bitpos + bitsdone) / unit; | |
1786 | thispos = (bitpos + bitsdone) % unit; | |
1787 | ||
0eb61c19 DE |
1788 | /* THISSIZE must not overrun a word boundary. Otherwise, |
1789 | extract_fixed_bit_field will call us again, and we will mutually | |
1790 | recurse forever. */ | |
1791 | thissize = MIN (bitsize - bitsdone, BITS_PER_WORD); | |
1792 | thissize = MIN (thissize, unit - thispos); | |
06c94bce RS |
1793 | |
1794 | /* If OP0 is a register, then handle OFFSET here. | |
5f57dff0 JW |
1795 | |
1796 | When handling multiword bitfields, extract_bit_field may pass | |
1797 | down a word_mode SUBREG of a larger REG for a bitfield that actually | |
1798 | crosses a word boundary. Thus, for a SUBREG, we must find | |
1799 | the current word starting from the base register. */ | |
1800 | if (GET_CODE (op0) == SUBREG) | |
1801 | { | |
1802 | word = operand_subword_force (SUBREG_REG (op0), | |
1803 | SUBREG_WORD (op0) + offset, | |
1804 | GET_MODE (SUBREG_REG (op0))); | |
1805 | offset = 0; | |
1806 | } | |
1807 | else if (GET_CODE (op0) == REG) | |
06c94bce RS |
1808 | { |
1809 | word = operand_subword_force (op0, offset, GET_MODE (op0)); | |
1810 | offset = 0; | |
1811 | } | |
1812 | else | |
1813 | word = op0; | |
1814 | ||
06c94bce | 1815 | /* Extract the parts in bit-counting order, |
0eb61c19 DE |
1816 | whose meaning is determined by BYTES_PER_UNIT. |
1817 | OFFSET is in UNITs, and UNIT is in bits. | |
1818 | extract_fixed_bit_field wants offset in bytes. */ | |
1819 | part = extract_fixed_bit_field (word_mode, word, | |
1820 | offset * unit / BITS_PER_UNIT, | |
06c94bce RS |
1821 | thissize, thispos, 0, 1, align); |
1822 | bitsdone += thissize; | |
44037a66 | 1823 | |
06c94bce | 1824 | /* Shift this part into place for the result. */ |
f76b9db2 ILT |
1825 | if (BYTES_BIG_ENDIAN) |
1826 | { | |
1827 | if (bitsize != bitsdone) | |
1828 | part = expand_shift (LSHIFT_EXPR, word_mode, part, | |
1829 | build_int_2 (bitsize - bitsdone, 0), 0, 1); | |
1830 | } | |
1831 | else | |
1832 | { | |
1833 | if (bitsdone != thissize) | |
1834 | part = expand_shift (LSHIFT_EXPR, word_mode, part, | |
1835 | build_int_2 (bitsdone - thissize, 0), 0, 1); | |
1836 | } | |
44037a66 | 1837 | |
06c94bce RS |
1838 | if (first) |
1839 | result = part; | |
1840 | else | |
1841 | /* Combine the parts with bitwise or. This works | |
1842 | because we extracted each part as an unsigned bit field. */ | |
1843 | result = expand_binop (word_mode, ior_optab, part, result, NULL_RTX, 1, | |
1844 | OPTAB_LIB_WIDEN); | |
1845 | ||
1846 | first = 0; | |
1847 | } | |
44037a66 TG |
1848 | |
1849 | /* Unsigned bit field: we are done. */ | |
1850 | if (unsignedp) | |
1851 | return result; | |
1852 | /* Signed bit field: sign-extend with two arithmetic shifts. */ | |
1853 | result = expand_shift (LSHIFT_EXPR, word_mode, result, | |
b1ec3c92 CH |
1854 | build_int_2 (BITS_PER_WORD - bitsize, 0), |
1855 | NULL_RTX, 0); | |
44037a66 | 1856 | return expand_shift (RSHIFT_EXPR, word_mode, result, |
b1ec3c92 | 1857 | build_int_2 (BITS_PER_WORD - bitsize, 0), NULL_RTX, 0); |
44037a66 TG |
1858 | } |
1859 | \f | |
1860 | /* Add INC into TARGET. */ | |
1861 | ||
1862 | void | |
1863 | expand_inc (target, inc) | |
1864 | rtx target, inc; | |
1865 | { | |
1866 | rtx value = expand_binop (GET_MODE (target), add_optab, | |
1867 | target, inc, | |
1868 | target, 0, OPTAB_LIB_WIDEN); | |
1869 | if (value != target) | |
1870 | emit_move_insn (target, value); | |
1871 | } | |
1872 | ||
1873 | /* Subtract DEC from TARGET. */ | |
1874 | ||
1875 | void | |
1876 | expand_dec (target, dec) | |
1877 | rtx target, dec; | |
1878 | { | |
1879 | rtx value = expand_binop (GET_MODE (target), sub_optab, | |
1880 | target, dec, | |
1881 | target, 0, OPTAB_LIB_WIDEN); | |
1882 | if (value != target) | |
1883 | emit_move_insn (target, value); | |
1884 | } | |
1885 | \f | |
1886 | /* Output a shift instruction for expression code CODE, | |
1887 | with SHIFTED being the rtx for the value to shift, | |
1888 | and AMOUNT the tree for the amount to shift by. | |
1889 | Store the result in the rtx TARGET, if that is convenient. | |
1890 | If UNSIGNEDP is nonzero, do a logical shift; otherwise, arithmetic. | |
1891 | Return the rtx for where the value is. */ | |
1892 | ||
1893 | rtx | |
1894 | expand_shift (code, mode, shifted, amount, target, unsignedp) | |
1895 | enum tree_code code; | |
1896 | register enum machine_mode mode; | |
1897 | rtx shifted; | |
1898 | tree amount; | |
1899 | register rtx target; | |
1900 | int unsignedp; | |
1901 | { | |
1902 | register rtx op1, temp = 0; | |
1903 | register int left = (code == LSHIFT_EXPR || code == LROTATE_EXPR); | |
1904 | register int rotate = (code == LROTATE_EXPR || code == RROTATE_EXPR); | |
1905 | int try; | |
1906 | ||
1907 | /* Previously detected shift-counts computed by NEGATE_EXPR | |
1908 | and shifted in the other direction; but that does not work | |
1909 | on all machines. */ | |
1910 | ||
b1ec3c92 | 1911 | op1 = expand_expr (amount, NULL_RTX, VOIDmode, 0); |
44037a66 | 1912 | |
1433f0f9 | 1913 | #ifdef SHIFT_COUNT_TRUNCATED |
166cdf4a RH |
1914 | if (SHIFT_COUNT_TRUNCATED) |
1915 | { | |
1916 | if (GET_CODE (op1) == CONST_INT | |
c84e2712 KG |
1917 | && ((unsigned HOST_WIDE_INT) INTVAL (op1) >= |
1918 | (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode))) | |
166cdf4a RH |
1919 | op1 = GEN_INT ((unsigned HOST_WIDE_INT) INTVAL (op1) |
1920 | % GET_MODE_BITSIZE (mode)); | |
1921 | else if (GET_CODE (op1) == SUBREG | |
1922 | && SUBREG_WORD (op1) == 0) | |
1923 | op1 = SUBREG_REG (op1); | |
1924 | } | |
2ab0a5c4 TG |
1925 | #endif |
1926 | ||
44037a66 TG |
1927 | if (op1 == const0_rtx) |
1928 | return shifted; | |
1929 | ||
1930 | for (try = 0; temp == 0 && try < 3; try++) | |
1931 | { | |
1932 | enum optab_methods methods; | |
1933 | ||
1934 | if (try == 0) | |
1935 | methods = OPTAB_DIRECT; | |
1936 | else if (try == 1) | |
1937 | methods = OPTAB_WIDEN; | |
1938 | else | |
1939 | methods = OPTAB_LIB_WIDEN; | |
1940 | ||
1941 | if (rotate) | |
1942 | { | |
1943 | /* Widening does not work for rotation. */ | |
1944 | if (methods == OPTAB_WIDEN) | |
1945 | continue; | |
1946 | else if (methods == OPTAB_LIB_WIDEN) | |
cbec710e | 1947 | { |
39e71615 | 1948 | /* If we have been unable to open-code this by a rotation, |
cbec710e RK |
1949 | do it as the IOR of two shifts. I.e., to rotate A |
1950 | by N bits, compute (A << N) | ((unsigned) A >> (C - N)) | |
1951 | where C is the bitsize of A. | |
1952 | ||
1953 | It is theoretically possible that the target machine might | |
1954 | not be able to perform either shift and hence we would | |
1955 | be making two libcalls rather than just the one for the | |
1956 | shift (similarly if IOR could not be done). We will allow | |
1957 | this extremely unlikely lossage to avoid complicating the | |
1958 | code below. */ | |
1959 | ||
39e71615 RK |
1960 | rtx subtarget = target == shifted ? 0 : target; |
1961 | rtx temp1; | |
1962 | tree type = TREE_TYPE (amount); | |
1963 | tree new_amount = make_tree (type, op1); | |
1964 | tree other_amount | |
1965 | = fold (build (MINUS_EXPR, type, | |
1966 | convert (type, | |
1967 | build_int_2 (GET_MODE_BITSIZE (mode), | |
1968 | 0)), | |
1969 | amount)); | |
1970 | ||
1971 | shifted = force_reg (mode, shifted); | |
1972 | ||
1973 | temp = expand_shift (left ? LSHIFT_EXPR : RSHIFT_EXPR, | |
1974 | mode, shifted, new_amount, subtarget, 1); | |
1975 | temp1 = expand_shift (left ? RSHIFT_EXPR : LSHIFT_EXPR, | |
1976 | mode, shifted, other_amount, 0, 1); | |
1977 | return expand_binop (mode, ior_optab, temp, temp1, target, | |
1978 | unsignedp, methods); | |
cbec710e | 1979 | } |
44037a66 TG |
1980 | |
1981 | temp = expand_binop (mode, | |
1982 | left ? rotl_optab : rotr_optab, | |
1983 | shifted, op1, target, unsignedp, methods); | |
cbec710e RK |
1984 | |
1985 | /* If we don't have the rotate, but we are rotating by a constant | |
1986 | that is in range, try a rotate in the opposite direction. */ | |
1987 | ||
1988 | if (temp == 0 && GET_CODE (op1) == CONST_INT | |
1989 | && INTVAL (op1) > 0 && INTVAL (op1) < GET_MODE_BITSIZE (mode)) | |
1990 | temp = expand_binop (mode, | |
1991 | left ? rotr_optab : rotl_optab, | |
1992 | shifted, | |
1993 | GEN_INT (GET_MODE_BITSIZE (mode) | |
1994 | - INTVAL (op1)), | |
1995 | target, unsignedp, methods); | |
44037a66 TG |
1996 | } |
1997 | else if (unsignedp) | |
a34958c9 RK |
1998 | temp = expand_binop (mode, |
1999 | left ? ashl_optab : lshr_optab, | |
2000 | shifted, op1, target, unsignedp, methods); | |
44037a66 TG |
2001 | |
2002 | /* Do arithmetic shifts. | |
2003 | Also, if we are going to widen the operand, we can just as well | |
2004 | use an arithmetic right-shift instead of a logical one. */ | |
2005 | if (temp == 0 && ! rotate | |
2006 | && (! unsignedp || (! left && methods == OPTAB_WIDEN))) | |
2007 | { | |
2008 | enum optab_methods methods1 = methods; | |
2009 | ||
2010 | /* If trying to widen a log shift to an arithmetic shift, | |
2011 | don't accept an arithmetic shift of the same size. */ | |
2012 | if (unsignedp) | |
2013 | methods1 = OPTAB_MUST_WIDEN; | |
2014 | ||
2015 | /* Arithmetic shift */ | |
2016 | ||
2017 | temp = expand_binop (mode, | |
2018 | left ? ashl_optab : ashr_optab, | |
2019 | shifted, op1, target, unsignedp, methods1); | |
2020 | } | |
2021 | ||
711a5e64 RK |
2022 | /* We used to try extzv here for logical right shifts, but that was |
2023 | only useful for one machine, the VAX, and caused poor code | |
2024 | generation there for lshrdi3, so the code was deleted and a | |
2025 | define_expand for lshrsi3 was added to vax.md. */ | |
44037a66 TG |
2026 | } |
2027 | ||
2028 | if (temp == 0) | |
2029 | abort (); | |
2030 | return temp; | |
2031 | } | |
2032 | \f | |
b385aeda | 2033 | enum alg_code { alg_zero, alg_m, alg_shift, |
b2fb324c | 2034 | alg_add_t_m2, alg_sub_t_m2, |
7963ac37 RK |
2035 | alg_add_factor, alg_sub_factor, |
2036 | alg_add_t2_m, alg_sub_t2_m, | |
b385aeda | 2037 | alg_add, alg_subtract, alg_factor, alg_shiftop }; |
44037a66 TG |
2038 | |
2039 | /* This structure records a sequence of operations. | |
2040 | `ops' is the number of operations recorded. | |
2041 | `cost' is their total cost. | |
2042 | The operations are stored in `op' and the corresponding | |
b385aeda RK |
2043 | logarithms of the integer coefficients in `log'. |
2044 | ||
44037a66 | 2045 | These are the operations: |
b385aeda RK |
2046 | alg_zero total := 0; |
2047 | alg_m total := multiplicand; | |
b2fb324c | 2048 | alg_shift total := total * coeff |
7963ac37 RK |
2049 | alg_add_t_m2 total := total + multiplicand * coeff; |
2050 | alg_sub_t_m2 total := total - multiplicand * coeff; | |
2051 | alg_add_factor total := total * coeff + total; | |
2052 | alg_sub_factor total := total * coeff - total; | |
2053 | alg_add_t2_m total := total * coeff + multiplicand; | |
2054 | alg_sub_t2_m total := total * coeff - multiplicand; | |
b385aeda RK |
2055 | |
2056 | The first operand must be either alg_zero or alg_m. */ | |
44037a66 | 2057 | |
44037a66 TG |
2058 | struct algorithm |
2059 | { | |
7963ac37 RK |
2060 | short cost; |
2061 | short ops; | |
b385aeda RK |
2062 | /* The size of the OP and LOG fields are not directly related to the |
2063 | word size, but the worst-case algorithms will be if we have few | |
2064 | consecutive ones or zeros, i.e., a multiplicand like 10101010101... | |
2065 | In that case we will generate shift-by-2, add, shift-by-2, add,..., | |
2066 | in total wordsize operations. */ | |
44037a66 | 2067 | enum alg_code op[MAX_BITS_PER_WORD]; |
b385aeda | 2068 | char log[MAX_BITS_PER_WORD]; |
44037a66 TG |
2069 | }; |
2070 | ||
711d877c KG |
2071 | static void synth_mult PARAMS ((struct algorithm *, |
2072 | unsigned HOST_WIDE_INT, | |
2073 | int)); | |
2074 | static unsigned HOST_WIDE_INT choose_multiplier PARAMS ((unsigned HOST_WIDE_INT, | |
2075 | int, int, | |
2076 | unsigned HOST_WIDE_INT *, | |
2077 | int *, int *)); | |
2078 | static unsigned HOST_WIDE_INT invert_mod2n PARAMS ((unsigned HOST_WIDE_INT, | |
2079 | int)); | |
44037a66 | 2080 | /* Compute and return the best algorithm for multiplying by T. |
7963ac37 RK |
2081 | The algorithm must cost less than cost_limit |
2082 | If retval.cost >= COST_LIMIT, no algorithm was found and all | |
2083 | other field of the returned struct are undefined. */ | |
44037a66 | 2084 | |
819126a6 RK |
2085 | static void |
2086 | synth_mult (alg_out, t, cost_limit) | |
2087 | struct algorithm *alg_out; | |
b1ec3c92 | 2088 | unsigned HOST_WIDE_INT t; |
7963ac37 | 2089 | int cost_limit; |
44037a66 | 2090 | { |
b2fb324c | 2091 | int m; |
52786026 | 2092 | struct algorithm *alg_in, *best_alg; |
c84e2712 | 2093 | int cost; |
b2fb324c | 2094 | unsigned HOST_WIDE_INT q; |
44037a66 | 2095 | |
7963ac37 RK |
2096 | /* Indicate that no algorithm is yet found. If no algorithm |
2097 | is found, this value will be returned and indicate failure. */ | |
819126a6 | 2098 | alg_out->cost = cost_limit; |
44037a66 | 2099 | |
b2fb324c | 2100 | if (cost_limit <= 0) |
819126a6 | 2101 | return; |
44037a66 | 2102 | |
b385aeda RK |
2103 | /* t == 1 can be done in zero cost. */ |
2104 | if (t == 1) | |
b2fb324c | 2105 | { |
819126a6 RK |
2106 | alg_out->ops = 1; |
2107 | alg_out->cost = 0; | |
2108 | alg_out->op[0] = alg_m; | |
2109 | return; | |
b2fb324c RK |
2110 | } |
2111 | ||
b385aeda RK |
2112 | /* t == 0 sometimes has a cost. If it does and it exceeds our limit, |
2113 | fail now. */ | |
819126a6 | 2114 | if (t == 0) |
b385aeda RK |
2115 | { |
2116 | if (zero_cost >= cost_limit) | |
819126a6 | 2117 | return; |
b385aeda RK |
2118 | else |
2119 | { | |
819126a6 RK |
2120 | alg_out->ops = 1; |
2121 | alg_out->cost = zero_cost; | |
2122 | alg_out->op[0] = alg_zero; | |
2123 | return; | |
b385aeda RK |
2124 | } |
2125 | } | |
2126 | ||
52786026 RK |
2127 | /* We'll be needing a couple extra algorithm structures now. */ |
2128 | ||
2129 | alg_in = (struct algorithm *)alloca (sizeof (struct algorithm)); | |
2130 | best_alg = (struct algorithm *)alloca (sizeof (struct algorithm)); | |
2131 | ||
b385aeda RK |
2132 | /* If we have a group of zero bits at the low-order part of T, try |
2133 | multiplying by the remaining bits and then doing a shift. */ | |
2134 | ||
b2fb324c | 2135 | if ((t & 1) == 0) |
44037a66 | 2136 | { |
b2fb324c RK |
2137 | m = floor_log2 (t & -t); /* m = number of low zero bits */ |
2138 | q = t >> m; | |
2139 | cost = shift_cost[m]; | |
819126a6 RK |
2140 | synth_mult (alg_in, q, cost_limit - cost); |
2141 | ||
2142 | cost += alg_in->cost; | |
b2fb324c | 2143 | if (cost < cost_limit) |
44037a66 | 2144 | { |
819126a6 RK |
2145 | struct algorithm *x; |
2146 | x = alg_in, alg_in = best_alg, best_alg = x; | |
2147 | best_alg->log[best_alg->ops] = m; | |
2148 | best_alg->op[best_alg->ops] = alg_shift; | |
2149 | cost_limit = cost; | |
2150 | } | |
2151 | } | |
2152 | ||
2153 | /* If we have an odd number, add or subtract one. */ | |
2154 | if ((t & 1) != 0) | |
2155 | { | |
2156 | unsigned HOST_WIDE_INT w; | |
2157 | ||
2158 | for (w = 1; (w & t) != 0; w <<= 1) | |
2159 | ; | |
31031edd JL |
2160 | /* If T was -1, then W will be zero after the loop. This is another |
2161 | case where T ends with ...111. Handling this with (T + 1) and | |
2162 | subtract 1 produces slightly better code and results in algorithm | |
2163 | selection much faster than treating it like the ...0111 case | |
2164 | below. */ | |
2165 | if (w == 0 | |
2166 | || (w > 2 | |
2167 | /* Reject the case where t is 3. | |
2168 | Thus we prefer addition in that case. */ | |
2169 | && t != 3)) | |
819126a6 RK |
2170 | { |
2171 | /* T ends with ...111. Multiply by (T + 1) and subtract 1. */ | |
2172 | ||
2173 | cost = add_cost; | |
2174 | synth_mult (alg_in, t + 1, cost_limit - cost); | |
b2fb324c RK |
2175 | |
2176 | cost += alg_in->cost; | |
819126a6 | 2177 | if (cost < cost_limit) |
44037a66 | 2178 | { |
b2fb324c RK |
2179 | struct algorithm *x; |
2180 | x = alg_in, alg_in = best_alg, best_alg = x; | |
819126a6 RK |
2181 | best_alg->log[best_alg->ops] = 0; |
2182 | best_alg->op[best_alg->ops] = alg_sub_t_m2; | |
2183 | cost_limit = cost; | |
44037a66 | 2184 | } |
44037a66 | 2185 | } |
819126a6 RK |
2186 | else |
2187 | { | |
2188 | /* T ends with ...01 or ...011. Multiply by (T - 1) and add 1. */ | |
44037a66 | 2189 | |
819126a6 RK |
2190 | cost = add_cost; |
2191 | synth_mult (alg_in, t - 1, cost_limit - cost); | |
2192 | ||
2193 | cost += alg_in->cost; | |
2194 | if (cost < cost_limit) | |
2195 | { | |
2196 | struct algorithm *x; | |
2197 | x = alg_in, alg_in = best_alg, best_alg = x; | |
2198 | best_alg->log[best_alg->ops] = 0; | |
2199 | best_alg->op[best_alg->ops] = alg_add_t_m2; | |
2200 | cost_limit = cost; | |
2201 | } | |
2202 | } | |
2203 | } | |
63610db9 | 2204 | |
44037a66 | 2205 | /* Look for factors of t of the form |
7963ac37 | 2206 | t = q(2**m +- 1), 2 <= m <= floor(log2(t - 1)). |
44037a66 | 2207 | If we find such a factor, we can multiply by t using an algorithm that |
7963ac37 | 2208 | multiplies by q, shift the result by m and add/subtract it to itself. |
44037a66 | 2209 | |
7963ac37 RK |
2210 | We search for large factors first and loop down, even if large factors |
2211 | are less probable than small; if we find a large factor we will find a | |
2212 | good sequence quickly, and therefore be able to prune (by decreasing | |
2213 | COST_LIMIT) the search. */ | |
2214 | ||
2215 | for (m = floor_log2 (t - 1); m >= 2; m--) | |
44037a66 | 2216 | { |
7963ac37 | 2217 | unsigned HOST_WIDE_INT d; |
44037a66 | 2218 | |
7963ac37 RK |
2219 | d = ((unsigned HOST_WIDE_INT) 1 << m) + 1; |
2220 | if (t % d == 0 && t > d) | |
44037a66 | 2221 | { |
b385aeda | 2222 | cost = MIN (shiftadd_cost[m], add_cost + shift_cost[m]); |
819126a6 | 2223 | synth_mult (alg_in, t / d, cost_limit - cost); |
44037a66 | 2224 | |
7963ac37 | 2225 | cost += alg_in->cost; |
819126a6 | 2226 | if (cost < cost_limit) |
44037a66 | 2227 | { |
7963ac37 RK |
2228 | struct algorithm *x; |
2229 | x = alg_in, alg_in = best_alg, best_alg = x; | |
b385aeda | 2230 | best_alg->log[best_alg->ops] = m; |
819126a6 RK |
2231 | best_alg->op[best_alg->ops] = alg_add_factor; |
2232 | cost_limit = cost; | |
44037a66 | 2233 | } |
c0b262c1 TG |
2234 | /* Other factors will have been taken care of in the recursion. */ |
2235 | break; | |
44037a66 TG |
2236 | } |
2237 | ||
7963ac37 RK |
2238 | d = ((unsigned HOST_WIDE_INT) 1 << m) - 1; |
2239 | if (t % d == 0 && t > d) | |
44037a66 | 2240 | { |
b385aeda | 2241 | cost = MIN (shiftsub_cost[m], add_cost + shift_cost[m]); |
819126a6 | 2242 | synth_mult (alg_in, t / d, cost_limit - cost); |
44037a66 | 2243 | |
7963ac37 | 2244 | cost += alg_in->cost; |
819126a6 | 2245 | if (cost < cost_limit) |
44037a66 | 2246 | { |
7963ac37 RK |
2247 | struct algorithm *x; |
2248 | x = alg_in, alg_in = best_alg, best_alg = x; | |
b385aeda | 2249 | best_alg->log[best_alg->ops] = m; |
819126a6 RK |
2250 | best_alg->op[best_alg->ops] = alg_sub_factor; |
2251 | cost_limit = cost; | |
44037a66 | 2252 | } |
c0b262c1 | 2253 | break; |
44037a66 TG |
2254 | } |
2255 | } | |
2256 | ||
7963ac37 RK |
2257 | /* Try shift-and-add (load effective address) instructions, |
2258 | i.e. do a*3, a*5, a*9. */ | |
2259 | if ((t & 1) != 0) | |
2260 | { | |
7963ac37 RK |
2261 | q = t - 1; |
2262 | q = q & -q; | |
2263 | m = exact_log2 (q); | |
5eebe2eb | 2264 | if (m >= 0) |
b385aeda | 2265 | { |
5eebe2eb | 2266 | cost = shiftadd_cost[m]; |
819126a6 | 2267 | synth_mult (alg_in, (t - 1) >> m, cost_limit - cost); |
5eebe2eb RK |
2268 | |
2269 | cost += alg_in->cost; | |
819126a6 | 2270 | if (cost < cost_limit) |
5eebe2eb RK |
2271 | { |
2272 | struct algorithm *x; | |
2273 | x = alg_in, alg_in = best_alg, best_alg = x; | |
2274 | best_alg->log[best_alg->ops] = m; | |
819126a6 RK |
2275 | best_alg->op[best_alg->ops] = alg_add_t2_m; |
2276 | cost_limit = cost; | |
5eebe2eb | 2277 | } |
7963ac37 | 2278 | } |
44037a66 | 2279 | |
7963ac37 RK |
2280 | q = t + 1; |
2281 | q = q & -q; | |
2282 | m = exact_log2 (q); | |
5eebe2eb | 2283 | if (m >= 0) |
b385aeda | 2284 | { |
5eebe2eb | 2285 | cost = shiftsub_cost[m]; |
819126a6 | 2286 | synth_mult (alg_in, (t + 1) >> m, cost_limit - cost); |
5eebe2eb RK |
2287 | |
2288 | cost += alg_in->cost; | |
819126a6 | 2289 | if (cost < cost_limit) |
5eebe2eb RK |
2290 | { |
2291 | struct algorithm *x; | |
2292 | x = alg_in, alg_in = best_alg, best_alg = x; | |
2293 | best_alg->log[best_alg->ops] = m; | |
819126a6 RK |
2294 | best_alg->op[best_alg->ops] = alg_sub_t2_m; |
2295 | cost_limit = cost; | |
5eebe2eb | 2296 | } |
7963ac37 RK |
2297 | } |
2298 | } | |
44037a66 | 2299 | |
819126a6 RK |
2300 | /* If cost_limit has not decreased since we stored it in alg_out->cost, |
2301 | we have not found any algorithm. */ | |
2302 | if (cost_limit == alg_out->cost) | |
2303 | return; | |
2304 | ||
52786026 RK |
2305 | /* If we are getting a too long sequence for `struct algorithm' |
2306 | to record, make this search fail. */ | |
2307 | if (best_alg->ops == MAX_BITS_PER_WORD) | |
2308 | return; | |
2309 | ||
819126a6 RK |
2310 | /* Copy the algorithm from temporary space to the space at alg_out. |
2311 | We avoid using structure assignment because the majority of | |
2312 | best_alg is normally undefined, and this is a critical function. */ | |
2313 | alg_out->ops = best_alg->ops + 1; | |
2314 | alg_out->cost = cost_limit; | |
4c9a05bc RK |
2315 | bcopy ((char *) best_alg->op, (char *) alg_out->op, |
2316 | alg_out->ops * sizeof *alg_out->op); | |
2317 | bcopy ((char *) best_alg->log, (char *) alg_out->log, | |
2318 | alg_out->ops * sizeof *alg_out->log); | |
44037a66 TG |
2319 | } |
2320 | \f | |
2321 | /* Perform a multiplication and return an rtx for the result. | |
2322 | MODE is mode of value; OP0 and OP1 are what to multiply (rtx's); | |
2323 | TARGET is a suggestion for where to store the result (an rtx). | |
2324 | ||
2325 | We check specially for a constant integer as OP1. | |
2326 | If you want this check for OP0 as well, then before calling | |
2327 | you should swap the two operands if OP0 would be constant. */ | |
2328 | ||
2329 | rtx | |
2330 | expand_mult (mode, op0, op1, target, unsignedp) | |
2331 | enum machine_mode mode; | |
2332 | register rtx op0, op1, target; | |
2333 | int unsignedp; | |
2334 | { | |
2335 | rtx const_op1 = op1; | |
2336 | ||
ceb1d268 JW |
2337 | /* synth_mult does an `unsigned int' multiply. As long as the mode is |
2338 | less than or equal in size to `unsigned int' this doesn't matter. | |
2339 | If the mode is larger than `unsigned int', then synth_mult works only | |
2340 | if the constant value exactly fits in an `unsigned int' without any | |
2341 | truncation. This means that multiplying by negative values does | |
2342 | not work; results are off by 2^32 on a 32 bit machine. */ | |
2343 | ||
44037a66 TG |
2344 | /* If we are multiplying in DImode, it may still be a win |
2345 | to try to work with shifts and adds. */ | |
2346 | if (GET_CODE (op1) == CONST_DOUBLE | |
2347 | && GET_MODE_CLASS (GET_MODE (op1)) == MODE_INT | |
ceb1d268 JW |
2348 | && HOST_BITS_PER_INT >= BITS_PER_WORD |
2349 | && CONST_DOUBLE_HIGH (op1) == 0) | |
2350 | const_op1 = GEN_INT (CONST_DOUBLE_LOW (op1)); | |
2351 | else if (HOST_BITS_PER_INT < GET_MODE_BITSIZE (mode) | |
2352 | && GET_CODE (op1) == CONST_INT | |
2353 | && INTVAL (op1) < 0) | |
2354 | const_op1 = 0; | |
44037a66 | 2355 | |
66c1f88e RS |
2356 | /* We used to test optimize here, on the grounds that it's better to |
2357 | produce a smaller program when -O is not used. | |
2358 | But this causes such a terrible slowdown sometimes | |
2359 | that it seems better to use synth_mult always. */ | |
b385aeda | 2360 | |
ceb1d268 | 2361 | if (const_op1 && GET_CODE (const_op1) == CONST_INT) |
44037a66 TG |
2362 | { |
2363 | struct algorithm alg; | |
55c2d311 | 2364 | struct algorithm alg2; |
7963ac37 | 2365 | HOST_WIDE_INT val = INTVAL (op1); |
b385aeda RK |
2366 | HOST_WIDE_INT val_so_far; |
2367 | rtx insn; | |
819126a6 | 2368 | int mult_cost; |
55c2d311 | 2369 | enum {basic_variant, negate_variant, add_variant} variant = basic_variant; |
44037a66 | 2370 | |
55c2d311 TG |
2371 | /* Try to do the computation three ways: multiply by the negative of OP1 |
2372 | and then negate, do the multiplication directly, or do multiplication | |
2373 | by OP1 - 1. */ | |
44037a66 | 2374 | |
38a448ca | 2375 | mult_cost = rtx_cost (gen_rtx_MULT (mode, op0, op1), SET); |
c0b262c1 | 2376 | mult_cost = MIN (12 * add_cost, mult_cost); |
819126a6 RK |
2377 | |
2378 | synth_mult (&alg, val, mult_cost); | |
ceb1d268 JW |
2379 | |
2380 | /* This works only if the inverted value actually fits in an | |
2381 | `unsigned int' */ | |
2382 | if (HOST_BITS_PER_INT >= GET_MODE_BITSIZE (mode)) | |
2383 | { | |
2384 | synth_mult (&alg2, - val, | |
2385 | (alg.cost < mult_cost ? alg.cost : mult_cost) - negate_cost); | |
2386 | if (alg2.cost + negate_cost < alg.cost) | |
2387 | alg = alg2, variant = negate_variant; | |
2388 | } | |
44037a66 | 2389 | |
55c2d311 | 2390 | /* This proves very useful for division-by-constant. */ |
98310eaa RK |
2391 | synth_mult (&alg2, val - 1, |
2392 | (alg.cost < mult_cost ? alg.cost : mult_cost) - add_cost); | |
55c2d311 TG |
2393 | if (alg2.cost + add_cost < alg.cost) |
2394 | alg = alg2, variant = add_variant; | |
44037a66 | 2395 | |
7963ac37 | 2396 | if (alg.cost < mult_cost) |
44037a66 | 2397 | { |
b2fb324c | 2398 | /* We found something cheaper than a multiply insn. */ |
7963ac37 | 2399 | int opno; |
44037a66 | 2400 | rtx accum, tem; |
44037a66 TG |
2401 | |
2402 | op0 = protect_from_queue (op0, 0); | |
2403 | ||
2404 | /* Avoid referencing memory over and over. | |
2405 | For speed, but also for correctness when mem is volatile. */ | |
2406 | if (GET_CODE (op0) == MEM) | |
2407 | op0 = force_reg (mode, op0); | |
2408 | ||
b385aeda RK |
2409 | /* ACCUM starts out either as OP0 or as a zero, depending on |
2410 | the first operation. */ | |
2411 | ||
2412 | if (alg.op[0] == alg_zero) | |
44037a66 | 2413 | { |
b385aeda RK |
2414 | accum = copy_to_mode_reg (mode, const0_rtx); |
2415 | val_so_far = 0; | |
2416 | } | |
2417 | else if (alg.op[0] == alg_m) | |
2418 | { | |
819126a6 | 2419 | accum = copy_to_mode_reg (mode, op0); |
b385aeda | 2420 | val_so_far = 1; |
44037a66 | 2421 | } |
b385aeda RK |
2422 | else |
2423 | abort (); | |
7963ac37 RK |
2424 | |
2425 | for (opno = 1; opno < alg.ops; opno++) | |
44037a66 | 2426 | { |
b385aeda | 2427 | int log = alg.log[opno]; |
c0a08574 RK |
2428 | int preserve = preserve_subexpressions_p (); |
2429 | rtx shift_subtarget = preserve ? 0 : accum; | |
98310eaa RK |
2430 | rtx add_target |
2431 | = (opno == alg.ops - 1 && target != 0 && variant != add_variant | |
9ec36da5 JL |
2432 | && ! preserve) |
2433 | ? target : 0; | |
c0a08574 RK |
2434 | rtx accum_target = preserve ? 0 : accum; |
2435 | ||
44037a66 TG |
2436 | switch (alg.op[opno]) |
2437 | { | |
b2fb324c RK |
2438 | case alg_shift: |
2439 | accum = expand_shift (LSHIFT_EXPR, mode, accum, | |
2440 | build_int_2 (log, 0), NULL_RTX, 0); | |
b385aeda | 2441 | val_so_far <<= log; |
b2fb324c RK |
2442 | break; |
2443 | ||
7963ac37 | 2444 | case alg_add_t_m2: |
b385aeda RK |
2445 | tem = expand_shift (LSHIFT_EXPR, mode, op0, |
2446 | build_int_2 (log, 0), NULL_RTX, 0); | |
38a448ca | 2447 | accum = force_operand (gen_rtx_PLUS (mode, accum, tem), |
c5c76735 JL |
2448 | add_target |
2449 | ? add_target : accum_target); | |
b385aeda | 2450 | val_so_far += (HOST_WIDE_INT) 1 << log; |
44037a66 TG |
2451 | break; |
2452 | ||
7963ac37 | 2453 | case alg_sub_t_m2: |
b385aeda RK |
2454 | tem = expand_shift (LSHIFT_EXPR, mode, op0, |
2455 | build_int_2 (log, 0), NULL_RTX, 0); | |
38a448ca | 2456 | accum = force_operand (gen_rtx_MINUS (mode, accum, tem), |
c5c76735 JL |
2457 | add_target |
2458 | ? add_target : accum_target); | |
b385aeda | 2459 | val_so_far -= (HOST_WIDE_INT) 1 << log; |
7963ac37 | 2460 | break; |
44037a66 | 2461 | |
7963ac37 RK |
2462 | case alg_add_t2_m: |
2463 | accum = expand_shift (LSHIFT_EXPR, mode, accum, | |
c0a08574 RK |
2464 | build_int_2 (log, 0), shift_subtarget, |
2465 | 0); | |
38a448ca | 2466 | accum = force_operand (gen_rtx_PLUS (mode, accum, op0), |
c5c76735 JL |
2467 | add_target |
2468 | ? add_target : accum_target); | |
b385aeda | 2469 | val_so_far = (val_so_far << log) + 1; |
44037a66 TG |
2470 | break; |
2471 | ||
7963ac37 RK |
2472 | case alg_sub_t2_m: |
2473 | accum = expand_shift (LSHIFT_EXPR, mode, accum, | |
c0a08574 RK |
2474 | build_int_2 (log, 0), shift_subtarget, |
2475 | 0); | |
38a448ca | 2476 | accum = force_operand (gen_rtx_MINUS (mode, accum, op0), |
c5c76735 JL |
2477 | add_target |
2478 | ? add_target : accum_target); | |
b385aeda | 2479 | val_so_far = (val_so_far << log) - 1; |
7963ac37 RK |
2480 | break; |
2481 | ||
2482 | case alg_add_factor: | |
44037a66 | 2483 | tem = expand_shift (LSHIFT_EXPR, mode, accum, |
b1ec3c92 | 2484 | build_int_2 (log, 0), NULL_RTX, 0); |
38a448ca | 2485 | accum = force_operand (gen_rtx_PLUS (mode, accum, tem), |
c5c76735 JL |
2486 | add_target |
2487 | ? add_target : accum_target); | |
b385aeda | 2488 | val_so_far += val_so_far << log; |
7963ac37 | 2489 | break; |
44037a66 | 2490 | |
7963ac37 RK |
2491 | case alg_sub_factor: |
2492 | tem = expand_shift (LSHIFT_EXPR, mode, accum, | |
2493 | build_int_2 (log, 0), NULL_RTX, 0); | |
38a448ca | 2494 | accum = force_operand (gen_rtx_MINUS (mode, tem, accum), |
c0a08574 RK |
2495 | (add_target ? add_target |
2496 | : preserve ? 0 : tem)); | |
b385aeda | 2497 | val_so_far = (val_so_far << log) - val_so_far; |
7963ac37 | 2498 | break; |
44037a66 | 2499 | |
b385aeda | 2500 | default: |
6d649d26 | 2501 | abort (); |
b385aeda | 2502 | } |
44037a66 | 2503 | |
b385aeda RK |
2504 | /* Write a REG_EQUAL note on the last insn so that we can cse |
2505 | multiplication sequences. */ | |
44037a66 | 2506 | |
b385aeda | 2507 | insn = get_last_insn (); |
7e5bda2c AM |
2508 | set_unique_reg_note (insn, |
2509 | REG_EQUAL, | |
2510 | gen_rtx_MULT (mode, op0, | |
2511 | GEN_INT (val_so_far))); | |
b385aeda | 2512 | } |
44037a66 | 2513 | |
55c2d311 | 2514 | if (variant == negate_variant) |
44037a66 | 2515 | { |
b385aeda RK |
2516 | val_so_far = - val_so_far; |
2517 | accum = expand_unop (mode, neg_optab, accum, target, 0); | |
44037a66 | 2518 | } |
55c2d311 TG |
2519 | else if (variant == add_variant) |
2520 | { | |
2521 | val_so_far = val_so_far + 1; | |
38a448ca | 2522 | accum = force_operand (gen_rtx_PLUS (mode, accum, op0), target); |
55c2d311 | 2523 | } |
44037a66 | 2524 | |
b385aeda RK |
2525 | if (val != val_so_far) |
2526 | abort (); | |
2527 | ||
2528 | return accum; | |
44037a66 TG |
2529 | } |
2530 | } | |
2531 | ||
819126a6 RK |
2532 | /* This used to use umul_optab if unsigned, but for non-widening multiply |
2533 | there is no difference between signed and unsigned. */ | |
44037a66 TG |
2534 | op0 = expand_binop (mode, smul_optab, |
2535 | op0, op1, target, unsignedp, OPTAB_LIB_WIDEN); | |
2536 | if (op0 == 0) | |
2537 | abort (); | |
2538 | return op0; | |
2539 | } | |
2540 | \f | |
55c2d311 TG |
2541 | /* Return the smallest n such that 2**n >= X. */ |
2542 | ||
2543 | int | |
2544 | ceil_log2 (x) | |
2545 | unsigned HOST_WIDE_INT x; | |
2546 | { | |
2547 | return floor_log2 (x - 1) + 1; | |
2548 | } | |
2549 | ||
2550 | /* Choose a minimal N + 1 bit approximation to 1/D that can be used to | |
2551 | replace division by D, and put the least significant N bits of the result | |
2552 | in *MULTIPLIER_PTR and return the most significant bit. | |
2553 | ||
2554 | The width of operations is N (should be <= HOST_BITS_PER_WIDE_INT), the | |
2555 | needed precision is in PRECISION (should be <= N). | |
2556 | ||
2557 | PRECISION should be as small as possible so this function can choose | |
2558 | multiplier more freely. | |
2559 | ||
2560 | The rounded-up logarithm of D is placed in *lgup_ptr. A shift count that | |
2561 | is to be used for a final right shift is placed in *POST_SHIFT_PTR. | |
2562 | ||
2563 | Using this function, x/D will be equal to (x * m) >> (*POST_SHIFT_PTR), | |
2564 | where m is the full HOST_BITS_PER_WIDE_INT + 1 bit multiplier. */ | |
2565 | ||
2566 | static | |
2567 | unsigned HOST_WIDE_INT | |
2568 | choose_multiplier (d, n, precision, multiplier_ptr, post_shift_ptr, lgup_ptr) | |
2569 | unsigned HOST_WIDE_INT d; | |
2570 | int n; | |
2571 | int precision; | |
2572 | unsigned HOST_WIDE_INT *multiplier_ptr; | |
2573 | int *post_shift_ptr; | |
2574 | int *lgup_ptr; | |
2575 | { | |
f9e158c3 JM |
2576 | HOST_WIDE_INT mhigh_hi, mlow_hi; |
2577 | unsigned HOST_WIDE_INT mhigh_lo, mlow_lo; | |
55c2d311 TG |
2578 | int lgup, post_shift; |
2579 | int pow, pow2; | |
f9e158c3 JM |
2580 | unsigned HOST_WIDE_INT nl, dummy1; |
2581 | HOST_WIDE_INT nh, dummy2; | |
55c2d311 TG |
2582 | |
2583 | /* lgup = ceil(log2(divisor)); */ | |
2584 | lgup = ceil_log2 (d); | |
2585 | ||
2586 | if (lgup > n) | |
2587 | abort (); | |
2588 | ||
2589 | pow = n + lgup; | |
2590 | pow2 = n + lgup - precision; | |
2591 | ||
2592 | if (pow == 2 * HOST_BITS_PER_WIDE_INT) | |
2593 | { | |
2594 | /* We could handle this with some effort, but this case is much better | |
2595 | handled directly with a scc insn, so rely on caller using that. */ | |
2596 | abort (); | |
2597 | } | |
2598 | ||
2599 | /* mlow = 2^(N + lgup)/d */ | |
2600 | if (pow >= HOST_BITS_PER_WIDE_INT) | |
2601 | { | |
f9e158c3 | 2602 | nh = (HOST_WIDE_INT) 1 << (pow - HOST_BITS_PER_WIDE_INT); |
55c2d311 TG |
2603 | nl = 0; |
2604 | } | |
2605 | else | |
2606 | { | |
2607 | nh = 0; | |
2608 | nl = (unsigned HOST_WIDE_INT) 1 << pow; | |
2609 | } | |
2610 | div_and_round_double (TRUNC_DIV_EXPR, 1, nl, nh, d, (HOST_WIDE_INT) 0, | |
2611 | &mlow_lo, &mlow_hi, &dummy1, &dummy2); | |
2612 | ||
2613 | /* mhigh = (2^(N + lgup) + 2^N + lgup - precision)/d */ | |
2614 | if (pow2 >= HOST_BITS_PER_WIDE_INT) | |
f9e158c3 | 2615 | nh |= (HOST_WIDE_INT) 1 << (pow2 - HOST_BITS_PER_WIDE_INT); |
55c2d311 TG |
2616 | else |
2617 | nl |= (unsigned HOST_WIDE_INT) 1 << pow2; | |
2618 | div_and_round_double (TRUNC_DIV_EXPR, 1, nl, nh, d, (HOST_WIDE_INT) 0, | |
2619 | &mhigh_lo, &mhigh_hi, &dummy1, &dummy2); | |
2620 | ||
2621 | if (mhigh_hi && nh - d >= d) | |
2622 | abort (); | |
2623 | if (mhigh_hi > 1 || mlow_hi > 1) | |
2624 | abort (); | |
2625 | /* assert that mlow < mhigh. */ | |
2626 | if (! (mlow_hi < mhigh_hi || (mlow_hi == mhigh_hi && mlow_lo < mhigh_lo))) | |
2627 | abort(); | |
2628 | ||
2629 | /* If precision == N, then mlow, mhigh exceed 2^N | |
2630 | (but they do not exceed 2^(N+1)). */ | |
2631 | ||
2632 | /* Reduce to lowest terms */ | |
2633 | for (post_shift = lgup; post_shift > 0; post_shift--) | |
2634 | { | |
2635 | unsigned HOST_WIDE_INT ml_lo = (mlow_hi << (HOST_BITS_PER_WIDE_INT - 1)) | (mlow_lo >> 1); | |
2636 | unsigned HOST_WIDE_INT mh_lo = (mhigh_hi << (HOST_BITS_PER_WIDE_INT - 1)) | (mhigh_lo >> 1); | |
2637 | if (ml_lo >= mh_lo) | |
2638 | break; | |
2639 | ||
2640 | mlow_hi = 0; | |
2641 | mlow_lo = ml_lo; | |
2642 | mhigh_hi = 0; | |
2643 | mhigh_lo = mh_lo; | |
2644 | } | |
2645 | ||
2646 | *post_shift_ptr = post_shift; | |
2647 | *lgup_ptr = lgup; | |
2648 | if (n < HOST_BITS_PER_WIDE_INT) | |
2649 | { | |
2650 | unsigned HOST_WIDE_INT mask = ((unsigned HOST_WIDE_INT) 1 << n) - 1; | |
2651 | *multiplier_ptr = mhigh_lo & mask; | |
2652 | return mhigh_lo >= mask; | |
2653 | } | |
2654 | else | |
2655 | { | |
2656 | *multiplier_ptr = mhigh_lo; | |
2657 | return mhigh_hi; | |
2658 | } | |
2659 | } | |
2660 | ||
2661 | /* Compute the inverse of X mod 2**n, i.e., find Y such that X * Y is | |
2662 | congruent to 1 (mod 2**N). */ | |
2663 | ||
2664 | static unsigned HOST_WIDE_INT | |
2665 | invert_mod2n (x, n) | |
2666 | unsigned HOST_WIDE_INT x; | |
2667 | int n; | |
2668 | { | |
0f41302f | 2669 | /* Solve x*y == 1 (mod 2^n), where x is odd. Return y. */ |
55c2d311 TG |
2670 | |
2671 | /* The algorithm notes that the choice y = x satisfies | |
2672 | x*y == 1 mod 2^3, since x is assumed odd. | |
2673 | Each iteration doubles the number of bits of significance in y. */ | |
2674 | ||
2675 | unsigned HOST_WIDE_INT mask; | |
2676 | unsigned HOST_WIDE_INT y = x; | |
2677 | int nbit = 3; | |
2678 | ||
2679 | mask = (n == HOST_BITS_PER_WIDE_INT | |
2680 | ? ~(unsigned HOST_WIDE_INT) 0 | |
2681 | : ((unsigned HOST_WIDE_INT) 1 << n) - 1); | |
2682 | ||
2683 | while (nbit < n) | |
2684 | { | |
2685 | y = y * (2 - x*y) & mask; /* Modulo 2^N */ | |
2686 | nbit *= 2; | |
2687 | } | |
2688 | return y; | |
2689 | } | |
2690 | ||
2691 | /* Emit code to adjust ADJ_OPERAND after multiplication of wrong signedness | |
2692 | flavor of OP0 and OP1. ADJ_OPERAND is already the high half of the | |
2693 | product OP0 x OP1. If UNSIGNEDP is nonzero, adjust the signed product | |
2694 | to become unsigned, if UNSIGNEDP is zero, adjust the unsigned product to | |
2695 | become signed. | |
2696 | ||
2697 | The result is put in TARGET if that is convenient. | |
2698 | ||
2699 | MODE is the mode of operation. */ | |
2700 | ||
2701 | rtx | |
2702 | expand_mult_highpart_adjust (mode, adj_operand, op0, op1, target, unsignedp) | |
2703 | enum machine_mode mode; | |
2704 | register rtx adj_operand, op0, op1, target; | |
2705 | int unsignedp; | |
2706 | { | |
2707 | rtx tem; | |
2708 | enum rtx_code adj_code = unsignedp ? PLUS : MINUS; | |
2709 | ||
2710 | tem = expand_shift (RSHIFT_EXPR, mode, op0, | |
2711 | build_int_2 (GET_MODE_BITSIZE (mode) - 1, 0), | |
2712 | NULL_RTX, 0); | |
2713 | tem = expand_and (tem, op1, NULL_RTX); | |
38a448ca RH |
2714 | adj_operand |
2715 | = force_operand (gen_rtx_fmt_ee (adj_code, mode, adj_operand, tem), | |
2716 | adj_operand); | |
55c2d311 TG |
2717 | |
2718 | tem = expand_shift (RSHIFT_EXPR, mode, op1, | |
2719 | build_int_2 (GET_MODE_BITSIZE (mode) - 1, 0), | |
2720 | NULL_RTX, 0); | |
2721 | tem = expand_and (tem, op0, NULL_RTX); | |
38a448ca RH |
2722 | target = force_operand (gen_rtx_fmt_ee (adj_code, mode, adj_operand, tem), |
2723 | target); | |
55c2d311 TG |
2724 | |
2725 | return target; | |
2726 | } | |
2727 | ||
2728 | /* Emit code to multiply OP0 and CNST1, putting the high half of the result | |
2729 | in TARGET if that is convenient, and return where the result is. If the | |
2730 | operation can not be performed, 0 is returned. | |
2731 | ||
2732 | MODE is the mode of operation and result. | |
2733 | ||
71af73bb TG |
2734 | UNSIGNEDP nonzero means unsigned multiply. |
2735 | ||
2736 | MAX_COST is the total allowed cost for the expanded RTL. */ | |
55c2d311 TG |
2737 | |
2738 | rtx | |
71af73bb | 2739 | expand_mult_highpart (mode, op0, cnst1, target, unsignedp, max_cost) |
55c2d311 TG |
2740 | enum machine_mode mode; |
2741 | register rtx op0, target; | |
2742 | unsigned HOST_WIDE_INT cnst1; | |
2743 | int unsignedp; | |
71af73bb | 2744 | int max_cost; |
55c2d311 TG |
2745 | { |
2746 | enum machine_mode wider_mode = GET_MODE_WIDER_MODE (mode); | |
2747 | optab mul_highpart_optab; | |
2748 | optab moptab; | |
2749 | rtx tem; | |
2750 | int size = GET_MODE_BITSIZE (mode); | |
5b0ce758 | 2751 | rtx op1, wide_op1; |
55c2d311 | 2752 | |
0865c631 | 2753 | /* We can't support modes wider than HOST_BITS_PER_INT. */ |
5b0ce758 RK |
2754 | if (size > HOST_BITS_PER_WIDE_INT) |
2755 | abort (); | |
2756 | ||
0865c631 | 2757 | op1 = GEN_INT (cnst1); |
5b0ce758 | 2758 | |
0865c631 | 2759 | if (GET_MODE_BITSIZE (wider_mode) <= HOST_BITS_PER_INT) |
5b0ce758 RK |
2760 | wide_op1 = op1; |
2761 | else | |
2762 | wide_op1 | |
2763 | = immed_double_const (cnst1, | |
55c2d311 TG |
2764 | (unsignedp |
2765 | ? (HOST_WIDE_INT) 0 | |
2766 | : -(cnst1 >> (HOST_BITS_PER_WIDE_INT - 1))), | |
2767 | wider_mode); | |
2768 | ||
2769 | /* expand_mult handles constant multiplication of word_mode | |
2770 | or narrower. It does a poor job for large modes. */ | |
71af73bb TG |
2771 | if (size < BITS_PER_WORD |
2772 | && mul_cost[(int) wider_mode] + shift_cost[size-1] < max_cost) | |
55c2d311 TG |
2773 | { |
2774 | /* We have to do this, since expand_binop doesn't do conversion for | |
2775 | multiply. Maybe change expand_binop to handle widening multiply? */ | |
2776 | op0 = convert_to_mode (wider_mode, op0, unsignedp); | |
2777 | ||
5b0ce758 | 2778 | tem = expand_mult (wider_mode, op0, wide_op1, NULL_RTX, unsignedp); |
55c2d311 TG |
2779 | tem = expand_shift (RSHIFT_EXPR, wider_mode, tem, |
2780 | build_int_2 (size, 0), NULL_RTX, 1); | |
2f97afcb | 2781 | return convert_modes (mode, wider_mode, tem, unsignedp); |
55c2d311 TG |
2782 | } |
2783 | ||
2784 | if (target == 0) | |
2785 | target = gen_reg_rtx (mode); | |
2786 | ||
2787 | /* Firstly, try using a multiplication insn that only generates the needed | |
2788 | high part of the product, and in the sign flavor of unsignedp. */ | |
71af73bb TG |
2789 | if (mul_highpart_cost[(int) mode] < max_cost) |
2790 | { | |
2791 | mul_highpart_optab = unsignedp ? umul_highpart_optab : smul_highpart_optab; | |
2792 | target = expand_binop (mode, mul_highpart_optab, | |
3b5286d7 | 2793 | op0, op1, target, unsignedp, OPTAB_DIRECT); |
71af73bb TG |
2794 | if (target) |
2795 | return target; | |
2796 | } | |
55c2d311 TG |
2797 | |
2798 | /* Secondly, same as above, but use sign flavor opposite of unsignedp. | |
2799 | Need to adjust the result after the multiplication. */ | |
71af73bb TG |
2800 | if (mul_highpart_cost[(int) mode] + 2 * shift_cost[size-1] + 4 * add_cost < max_cost) |
2801 | { | |
2802 | mul_highpart_optab = unsignedp ? smul_highpart_optab : umul_highpart_optab; | |
2803 | target = expand_binop (mode, mul_highpart_optab, | |
3b5286d7 | 2804 | op0, op1, target, unsignedp, OPTAB_DIRECT); |
71af73bb TG |
2805 | if (target) |
2806 | /* We used the wrong signedness. Adjust the result. */ | |
2807 | return expand_mult_highpart_adjust (mode, target, op0, | |
2808 | op1, target, unsignedp); | |
2809 | } | |
55c2d311 | 2810 | |
71af73bb | 2811 | /* Try widening multiplication. */ |
55c2d311 | 2812 | moptab = unsignedp ? umul_widen_optab : smul_widen_optab; |
71af73bb TG |
2813 | if (moptab->handlers[(int) wider_mode].insn_code != CODE_FOR_nothing |
2814 | && mul_widen_cost[(int) wider_mode] < max_cost) | |
a295d331 TG |
2815 | { |
2816 | op1 = force_reg (mode, op1); | |
2817 | goto try; | |
2818 | } | |
71af73bb TG |
2819 | |
2820 | /* Try widening the mode and perform a non-widening multiplication. */ | |
2821 | moptab = smul_optab; | |
2822 | if (smul_optab->handlers[(int) wider_mode].insn_code != CODE_FOR_nothing | |
2823 | && mul_cost[(int) wider_mode] + shift_cost[size-1] < max_cost) | |
a295d331 TG |
2824 | { |
2825 | op1 = wide_op1; | |
2826 | goto try; | |
2827 | } | |
71af73bb TG |
2828 | |
2829 | /* Try widening multiplication of opposite signedness, and adjust. */ | |
2830 | moptab = unsignedp ? smul_widen_optab : umul_widen_optab; | |
2831 | if (moptab->handlers[(int) wider_mode].insn_code != CODE_FOR_nothing | |
2832 | && (mul_widen_cost[(int) wider_mode] | |
2833 | + 2 * shift_cost[size-1] + 4 * add_cost < max_cost)) | |
55c2d311 | 2834 | { |
a295d331 TG |
2835 | rtx regop1 = force_reg (mode, op1); |
2836 | tem = expand_binop (wider_mode, moptab, op0, regop1, | |
71af73bb TG |
2837 | NULL_RTX, ! unsignedp, OPTAB_WIDEN); |
2838 | if (tem != 0) | |
55c2d311 | 2839 | { |
71af73bb TG |
2840 | /* Extract the high half of the just generated product. */ |
2841 | tem = expand_shift (RSHIFT_EXPR, wider_mode, tem, | |
2842 | build_int_2 (size, 0), NULL_RTX, 1); | |
2843 | tem = convert_modes (mode, wider_mode, tem, unsignedp); | |
2844 | /* We used the wrong signedness. Adjust the result. */ | |
2845 | return expand_mult_highpart_adjust (mode, tem, op0, op1, | |
2846 | target, unsignedp); | |
55c2d311 | 2847 | } |
55c2d311 TG |
2848 | } |
2849 | ||
71af73bb TG |
2850 | return 0; |
2851 | ||
2852 | try: | |
55c2d311 | 2853 | /* Pass NULL_RTX as target since TARGET has wrong mode. */ |
a295d331 | 2854 | tem = expand_binop (wider_mode, moptab, op0, op1, |
55c2d311 TG |
2855 | NULL_RTX, unsignedp, OPTAB_WIDEN); |
2856 | if (tem == 0) | |
2857 | return 0; | |
2858 | ||
2859 | /* Extract the high half of the just generated product. */ | |
a295d331 TG |
2860 | if (mode == word_mode) |
2861 | { | |
2862 | return gen_highpart (mode, tem); | |
2863 | } | |
2864 | else | |
2865 | { | |
2866 | tem = expand_shift (RSHIFT_EXPR, wider_mode, tem, | |
2867 | build_int_2 (size, 0), NULL_RTX, 1); | |
2868 | return convert_modes (mode, wider_mode, tem, unsignedp); | |
2869 | } | |
55c2d311 TG |
2870 | } |
2871 | \f | |
44037a66 TG |
2872 | /* Emit the code to divide OP0 by OP1, putting the result in TARGET |
2873 | if that is convenient, and returning where the result is. | |
2874 | You may request either the quotient or the remainder as the result; | |
2875 | specify REM_FLAG nonzero to get the remainder. | |
2876 | ||
2877 | CODE is the expression code for which kind of division this is; | |
2878 | it controls how rounding is done. MODE is the machine mode to use. | |
2879 | UNSIGNEDP nonzero means do unsigned division. */ | |
2880 | ||
2881 | /* ??? For CEIL_MOD_EXPR, can compute incorrect remainder with ANDI | |
2882 | and then correct it by or'ing in missing high bits | |
2883 | if result of ANDI is nonzero. | |
2884 | For ROUND_MOD_EXPR, can use ANDI and then sign-extend the result. | |
2885 | This could optimize to a bfexts instruction. | |
2886 | But C doesn't use these operations, so their optimizations are | |
2887 | left for later. */ | |
5353610b R |
2888 | /* ??? For modulo, we don't actually need the highpart of the first product, |
2889 | the low part will do nicely. And for small divisors, the second multiply | |
2890 | can also be a low-part only multiply or even be completely left out. | |
2891 | E.g. to calculate the remainder of a division by 3 with a 32 bit | |
2892 | multiply, multiply with 0x55555556 and extract the upper two bits; | |
2893 | the result is exact for inputs up to 0x1fffffff. | |
2894 | The input range can be reduced by using cross-sum rules. | |
2895 | For odd divisors >= 3, the following table gives right shift counts | |
2896 | so that if an number is shifted by an integer multiple of the given | |
2897 | amount, the remainder stays the same: | |
2898 | 2, 4, 3, 6, 10, 12, 4, 8, 18, 6, 11, 20, 18, 0, 5, 10, 12, 0, 12, 20, | |
2899 | 14, 12, 23, 21, 8, 0, 20, 18, 0, 0, 6, 12, 0, 22, 0, 18, 20, 30, 0, 0, | |
2900 | 0, 8, 0, 11, 12, 10, 36, 0, 30, 0, 0, 12, 0, 0, 0, 0, 44, 12, 24, 0, | |
2901 | 20, 0, 7, 14, 0, 18, 36, 0, 0, 46, 60, 0, 42, 0, 15, 24, 20, 0, 0, 33, | |
2902 | 0, 20, 0, 0, 18, 0, 60, 0, 0, 0, 0, 0, 40, 18, 0, 0, 12 | |
2903 | ||
2904 | Cross-sum rules for even numbers can be derived by leaving as many bits | |
2905 | to the right alone as the divisor has zeros to the right. | |
2906 | E.g. if x is an unsigned 32 bit number: | |
2907 | (x mod 12) == (((x & 1023) + ((x >> 8) & ~3)) * 0x15555558 >> 2 * 3) >> 28 | |
2908 | */ | |
44037a66 | 2909 | |
55c2d311 TG |
2910 | #define EXACT_POWER_OF_2_OR_ZERO_P(x) (((x) & ((x) - 1)) == 0) |
2911 | ||
44037a66 TG |
2912 | rtx |
2913 | expand_divmod (rem_flag, code, mode, op0, op1, target, unsignedp) | |
2914 | int rem_flag; | |
2915 | enum tree_code code; | |
2916 | enum machine_mode mode; | |
2917 | register rtx op0, op1, target; | |
2918 | int unsignedp; | |
2919 | { | |
44037a66 | 2920 | enum machine_mode compute_mode; |
55c2d311 TG |
2921 | register rtx tquotient; |
2922 | rtx quotient = 0, remainder = 0; | |
2923 | rtx last; | |
2c414fba | 2924 | int size; |
4e430df8 | 2925 | rtx insn, set; |
44037a66 | 2926 | optab optab1, optab2; |
55c2d311 | 2927 | int op1_is_constant, op1_is_pow2; |
71af73bb | 2928 | int max_cost, extra_cost; |
9ec36da5 | 2929 | static HOST_WIDE_INT last_div_const = 0; |
55c2d311 TG |
2930 | |
2931 | op1_is_constant = GET_CODE (op1) == CONST_INT; | |
9176af2f TG |
2932 | op1_is_pow2 = (op1_is_constant |
2933 | && ((EXACT_POWER_OF_2_OR_ZERO_P (INTVAL (op1)) | |
db7cafb0 | 2934 | || (! unsignedp && EXACT_POWER_OF_2_OR_ZERO_P (-INTVAL (op1)))))); |
55c2d311 TG |
2935 | |
2936 | /* | |
2937 | This is the structure of expand_divmod: | |
2938 | ||
2939 | First comes code to fix up the operands so we can perform the operations | |
2940 | correctly and efficiently. | |
2941 | ||
2942 | Second comes a switch statement with code specific for each rounding mode. | |
2943 | For some special operands this code emits all RTL for the desired | |
69f61901 | 2944 | operation, for other cases, it generates only a quotient and stores it in |
55c2d311 TG |
2945 | QUOTIENT. The case for trunc division/remainder might leave quotient = 0, |
2946 | to indicate that it has not done anything. | |
2947 | ||
69f61901 RK |
2948 | Last comes code that finishes the operation. If QUOTIENT is set and |
2949 | REM_FLAG is set, the remainder is computed as OP0 - QUOTIENT * OP1. If | |
2950 | QUOTIENT is not set, it is computed using trunc rounding. | |
44037a66 | 2951 | |
55c2d311 TG |
2952 | We try to generate special code for division and remainder when OP1 is a |
2953 | constant. If |OP1| = 2**n we can use shifts and some other fast | |
2954 | operations. For other values of OP1, we compute a carefully selected | |
2955 | fixed-point approximation m = 1/OP1, and generate code that multiplies OP0 | |
2956 | by m. | |
2957 | ||
2958 | In all cases but EXACT_DIV_EXPR, this multiplication requires the upper | |
2959 | half of the product. Different strategies for generating the product are | |
2960 | implemented in expand_mult_highpart. | |
2961 | ||
2962 | If what we actually want is the remainder, we generate that by another | |
2963 | by-constant multiplication and a subtraction. */ | |
2964 | ||
2965 | /* We shouldn't be called with OP1 == const1_rtx, but some of the | |
3d32ffd1 TW |
2966 | code below will malfunction if we are, so check here and handle |
2967 | the special case if so. */ | |
2968 | if (op1 == const1_rtx) | |
2969 | return rem_flag ? const0_rtx : op0; | |
2970 | ||
bc1c7e93 RK |
2971 | if (target |
2972 | /* Don't use the function value register as a target | |
2973 | since we have to read it as well as write it, | |
2974 | and function-inlining gets confused by this. */ | |
2975 | && ((REG_P (target) && REG_FUNCTION_VALUE_P (target)) | |
2976 | /* Don't clobber an operand while doing a multi-step calculation. */ | |
515dfc7a | 2977 | || ((rem_flag || op1_is_constant) |
bc1c7e93 RK |
2978 | && (reg_mentioned_p (target, op0) |
2979 | || (GET_CODE (op0) == MEM && GET_CODE (target) == MEM))) | |
2980 | || reg_mentioned_p (target, op1) | |
2981 | || (GET_CODE (op1) == MEM && GET_CODE (target) == MEM))) | |
44037a66 TG |
2982 | target = 0; |
2983 | ||
44037a66 TG |
2984 | /* Get the mode in which to perform this computation. Normally it will |
2985 | be MODE, but sometimes we can't do the desired operation in MODE. | |
2986 | If so, pick a wider mode in which we can do the operation. Convert | |
2987 | to that mode at the start to avoid repeated conversions. | |
2988 | ||
2989 | First see what operations we need. These depend on the expression | |
2990 | we are evaluating. (We assume that divxx3 insns exist under the | |
2991 | same conditions that modxx3 insns and that these insns don't normally | |
2992 | fail. If these assumptions are not correct, we may generate less | |
2993 | efficient code in some cases.) | |
2994 | ||
2995 | Then see if we find a mode in which we can open-code that operation | |
2996 | (either a division, modulus, or shift). Finally, check for the smallest | |
2997 | mode for which we can do the operation with a library call. */ | |
2998 | ||
55c2d311 TG |
2999 | /* We might want to refine this now that we have division-by-constant |
3000 | optimization. Since expand_mult_highpart tries so many variants, it is | |
3001 | not straightforward to generalize this. Maybe we should make an array | |
3002 | of possible modes in init_expmed? Save this for GCC 2.7. */ | |
3003 | ||
3004 | optab1 = (op1_is_pow2 ? (unsignedp ? lshr_optab : ashr_optab) | |
44037a66 | 3005 | : (unsignedp ? udiv_optab : sdiv_optab)); |
55c2d311 | 3006 | optab2 = (op1_is_pow2 ? optab1 : (unsignedp ? udivmod_optab : sdivmod_optab)); |
44037a66 TG |
3007 | |
3008 | for (compute_mode = mode; compute_mode != VOIDmode; | |
3009 | compute_mode = GET_MODE_WIDER_MODE (compute_mode)) | |
3010 | if (optab1->handlers[(int) compute_mode].insn_code != CODE_FOR_nothing | |
3011 | || optab2->handlers[(int) compute_mode].insn_code != CODE_FOR_nothing) | |
3012 | break; | |
3013 | ||
3014 | if (compute_mode == VOIDmode) | |
3015 | for (compute_mode = mode; compute_mode != VOIDmode; | |
3016 | compute_mode = GET_MODE_WIDER_MODE (compute_mode)) | |
3017 | if (optab1->handlers[(int) compute_mode].libfunc | |
3018 | || optab2->handlers[(int) compute_mode].libfunc) | |
3019 | break; | |
3020 | ||
bc1c7e93 RK |
3021 | /* If we still couldn't find a mode, use MODE, but we'll probably abort |
3022 | in expand_binop. */ | |
44037a66 TG |
3023 | if (compute_mode == VOIDmode) |
3024 | compute_mode = mode; | |
3025 | ||
55c2d311 TG |
3026 | if (target && GET_MODE (target) == compute_mode) |
3027 | tquotient = target; | |
3028 | else | |
3029 | tquotient = gen_reg_rtx (compute_mode); | |
2c414fba | 3030 | |
55c2d311 TG |
3031 | size = GET_MODE_BITSIZE (compute_mode); |
3032 | #if 0 | |
3033 | /* It should be possible to restrict the precision to GET_MODE_BITSIZE | |
71af73bb TG |
3034 | (mode), and thereby get better code when OP1 is a constant. Do that |
3035 | later. It will require going over all usages of SIZE below. */ | |
55c2d311 TG |
3036 | size = GET_MODE_BITSIZE (mode); |
3037 | #endif | |
bc1c7e93 | 3038 | |
9ec36da5 JL |
3039 | /* Only deduct something for a REM if the last divide done was |
3040 | for a different constant. Then set the constant of the last | |
3041 | divide. */ | |
71af73bb | 3042 | max_cost = div_cost[(int) compute_mode] |
9ec36da5 JL |
3043 | - (rem_flag && ! (last_div_const != 0 && op1_is_constant |
3044 | && INTVAL (op1) == last_div_const) | |
3045 | ? mul_cost[(int) compute_mode] + add_cost : 0); | |
3046 | ||
3047 | last_div_const = ! rem_flag && op1_is_constant ? INTVAL (op1) : 0; | |
71af73bb | 3048 | |
55c2d311 | 3049 | /* Now convert to the best mode to use. */ |
44037a66 TG |
3050 | if (compute_mode != mode) |
3051 | { | |
55c2d311 | 3052 | op0 = convert_modes (compute_mode, mode, op0, unsignedp); |
81722fa9 | 3053 | op1 = convert_modes (compute_mode, mode, op1, unsignedp); |
e13a25d5 | 3054 | |
e9a25f70 JL |
3055 | /* convert_modes may have placed op1 into a register, so we |
3056 | must recompute the following. */ | |
e13a25d5 DM |
3057 | op1_is_constant = GET_CODE (op1) == CONST_INT; |
3058 | op1_is_pow2 = (op1_is_constant | |
3059 | && ((EXACT_POWER_OF_2_OR_ZERO_P (INTVAL (op1)) | |
3060 | || (! unsignedp | |
e9a25f70 | 3061 | && EXACT_POWER_OF_2_OR_ZERO_P (-INTVAL (op1)))))) ; |
44037a66 TG |
3062 | } |
3063 | ||
55c2d311 | 3064 | /* If one of the operands is a volatile MEM, copy it into a register. */ |
c2a47e48 | 3065 | |
55c2d311 TG |
3066 | if (GET_CODE (op0) == MEM && MEM_VOLATILE_P (op0)) |
3067 | op0 = force_reg (compute_mode, op0); | |
3068 | if (GET_CODE (op1) == MEM && MEM_VOLATILE_P (op1)) | |
c2a47e48 RK |
3069 | op1 = force_reg (compute_mode, op1); |
3070 | ||
ab0b6581 TG |
3071 | /* If we need the remainder or if OP1 is constant, we need to |
3072 | put OP0 in a register in case it has any queued subexpressions. */ | |
3073 | if (rem_flag || op1_is_constant) | |
3074 | op0 = force_reg (compute_mode, op0); | |
bc1c7e93 | 3075 | |
55c2d311 | 3076 | last = get_last_insn (); |
44037a66 | 3077 | |
9faa82d8 | 3078 | /* Promote floor rounding to trunc rounding for unsigned operations. */ |
55c2d311 | 3079 | if (unsignedp) |
44037a66 | 3080 | { |
55c2d311 TG |
3081 | if (code == FLOOR_DIV_EXPR) |
3082 | code = TRUNC_DIV_EXPR; | |
3083 | if (code == FLOOR_MOD_EXPR) | |
3084 | code = TRUNC_MOD_EXPR; | |
db7cafb0 JL |
3085 | if (code == EXACT_DIV_EXPR && op1_is_pow2) |
3086 | code = TRUNC_DIV_EXPR; | |
55c2d311 | 3087 | } |
bc1c7e93 | 3088 | |
55c2d311 TG |
3089 | if (op1 != const0_rtx) |
3090 | switch (code) | |
3091 | { | |
3092 | case TRUNC_MOD_EXPR: | |
3093 | case TRUNC_DIV_EXPR: | |
34f016ed | 3094 | if (op1_is_constant) |
55c2d311 | 3095 | { |
d8f1376c | 3096 | if (unsignedp) |
55c2d311 TG |
3097 | { |
3098 | unsigned HOST_WIDE_INT mh, ml; | |
3099 | int pre_shift, post_shift; | |
3100 | int dummy; | |
3101 | unsigned HOST_WIDE_INT d = INTVAL (op1); | |
3102 | ||
3103 | if (EXACT_POWER_OF_2_OR_ZERO_P (d)) | |
3104 | { | |
3105 | pre_shift = floor_log2 (d); | |
3106 | if (rem_flag) | |
3107 | { | |
db3cf6fb MS |
3108 | remainder |
3109 | = expand_binop (compute_mode, and_optab, op0, | |
3110 | GEN_INT (((HOST_WIDE_INT) 1 << pre_shift) - 1), | |
3111 | remainder, 1, | |
3112 | OPTAB_LIB_WIDEN); | |
55c2d311 | 3113 | if (remainder) |
c8dbc8ca | 3114 | return gen_lowpart (mode, remainder); |
55c2d311 TG |
3115 | } |
3116 | quotient = expand_shift (RSHIFT_EXPR, compute_mode, op0, | |
3117 | build_int_2 (pre_shift, 0), | |
3118 | tquotient, 1); | |
3119 | } | |
34f016ed | 3120 | else if (size <= HOST_BITS_PER_WIDE_INT) |
55c2d311 | 3121 | { |
dc1d6150 | 3122 | if (d >= ((unsigned HOST_WIDE_INT) 1 << (size - 1))) |
55c2d311 | 3123 | { |
dc1d6150 TG |
3124 | /* Most significant bit of divisor is set; emit an scc |
3125 | insn. */ | |
3126 | quotient = emit_store_flag (tquotient, GEU, op0, op1, | |
3127 | compute_mode, 1, 1); | |
3128 | if (quotient == 0) | |
55c2d311 | 3129 | goto fail1; |
55c2d311 TG |
3130 | } |
3131 | else | |
3132 | { | |
dc1d6150 TG |
3133 | /* Find a suitable multiplier and right shift count |
3134 | instead of multiplying with D. */ | |
3135 | ||
3136 | mh = choose_multiplier (d, size, size, | |
3137 | &ml, &post_shift, &dummy); | |
3138 | ||
3139 | /* If the suggested multiplier is more than SIZE bits, | |
3140 | we can do better for even divisors, using an | |
3141 | initial right shift. */ | |
3142 | if (mh != 0 && (d & 1) == 0) | |
3143 | { | |
3144 | pre_shift = floor_log2 (d & -d); | |
3145 | mh = choose_multiplier (d >> pre_shift, size, | |
3146 | size - pre_shift, | |
3147 | &ml, &post_shift, &dummy); | |
3148 | if (mh) | |
3149 | abort (); | |
3150 | } | |
3151 | else | |
3152 | pre_shift = 0; | |
3153 | ||
3154 | if (mh != 0) | |
3155 | { | |
3156 | rtx t1, t2, t3, t4; | |
3157 | ||
3158 | extra_cost = (shift_cost[post_shift - 1] | |
3159 | + shift_cost[1] + 2 * add_cost); | |
3160 | t1 = expand_mult_highpart (compute_mode, op0, ml, | |
3161 | NULL_RTX, 1, | |
3162 | max_cost - extra_cost); | |
3163 | if (t1 == 0) | |
3164 | goto fail1; | |
38a448ca RH |
3165 | t2 = force_operand (gen_rtx_MINUS (compute_mode, |
3166 | op0, t1), | |
dc1d6150 TG |
3167 | NULL_RTX); |
3168 | t3 = expand_shift (RSHIFT_EXPR, compute_mode, t2, | |
3169 | build_int_2 (1, 0), NULL_RTX,1); | |
38a448ca RH |
3170 | t4 = force_operand (gen_rtx_PLUS (compute_mode, |
3171 | t1, t3), | |
dc1d6150 | 3172 | NULL_RTX); |
db3cf6fb MS |
3173 | quotient |
3174 | = expand_shift (RSHIFT_EXPR, compute_mode, t4, | |
3175 | build_int_2 (post_shift - 1, 0), | |
3176 | tquotient, 1); | |
dc1d6150 TG |
3177 | } |
3178 | else | |
3179 | { | |
3180 | rtx t1, t2; | |
3181 | ||
3182 | t1 = expand_shift (RSHIFT_EXPR, compute_mode, op0, | |
3183 | build_int_2 (pre_shift, 0), | |
3184 | NULL_RTX, 1); | |
3185 | extra_cost = (shift_cost[pre_shift] | |
3186 | + shift_cost[post_shift]); | |
3187 | t2 = expand_mult_highpart (compute_mode, t1, ml, | |
3188 | NULL_RTX, 1, | |
3189 | max_cost - extra_cost); | |
3190 | if (t2 == 0) | |
3191 | goto fail1; | |
db3cf6fb MS |
3192 | quotient |
3193 | = expand_shift (RSHIFT_EXPR, compute_mode, t2, | |
3194 | build_int_2 (post_shift, 0), | |
3195 | tquotient, 1); | |
dc1d6150 | 3196 | } |
55c2d311 TG |
3197 | } |
3198 | } | |
34f016ed TG |
3199 | else /* Too wide mode to use tricky code */ |
3200 | break; | |
55c2d311 TG |
3201 | |
3202 | insn = get_last_insn (); | |
4e430df8 RK |
3203 | if (insn != last |
3204 | && (set = single_set (insn)) != 0 | |
3205 | && SET_DEST (set) == quotient) | |
7e5bda2c AM |
3206 | set_unique_reg_note (insn, |
3207 | REG_EQUAL, | |
3208 | gen_rtx_UDIV (compute_mode, op0, op1)); | |
55c2d311 TG |
3209 | } |
3210 | else /* TRUNC_DIV, signed */ | |
3211 | { | |
3212 | unsigned HOST_WIDE_INT ml; | |
3213 | int lgup, post_shift; | |
3214 | HOST_WIDE_INT d = INTVAL (op1); | |
3215 | unsigned HOST_WIDE_INT abs_d = d >= 0 ? d : -d; | |
3216 | ||
3217 | /* n rem d = n rem -d */ | |
3218 | if (rem_flag && d < 0) | |
3219 | { | |
3220 | d = abs_d; | |
3221 | op1 = GEN_INT (abs_d); | |
3222 | } | |
3223 | ||
3224 | if (d == 1) | |
3225 | quotient = op0; | |
3226 | else if (d == -1) | |
3227 | quotient = expand_unop (compute_mode, neg_optab, op0, | |
3228 | tquotient, 0); | |
f737b132 RK |
3229 | else if (abs_d == (unsigned HOST_WIDE_INT) 1 << (size - 1)) |
3230 | { | |
3231 | /* This case is not handled correctly below. */ | |
3232 | quotient = emit_store_flag (tquotient, EQ, op0, op1, | |
3233 | compute_mode, 1, 1); | |
3234 | if (quotient == 0) | |
3235 | goto fail1; | |
3236 | } | |
55c2d311 TG |
3237 | else if (EXACT_POWER_OF_2_OR_ZERO_P (d) |
3238 | && (rem_flag ? smod_pow2_cheap : sdiv_pow2_cheap)) | |
3239 | ; | |
3240 | else if (EXACT_POWER_OF_2_OR_ZERO_P (abs_d)) | |
3241 | { | |
3242 | lgup = floor_log2 (abs_d); | |
3243 | if (abs_d != 2 && BRANCH_COST < 3) | |
3244 | { | |
3245 | rtx label = gen_label_rtx (); | |
3246 | rtx t1; | |
3247 | ||
3248 | t1 = copy_to_mode_reg (compute_mode, op0); | |
f5963e61 JL |
3249 | do_cmp_and_jump (t1, const0_rtx, GE, |
3250 | compute_mode, label); | |
55c2d311 TG |
3251 | expand_inc (t1, GEN_INT (abs_d - 1)); |
3252 | emit_label (label); | |
3253 | quotient = expand_shift (RSHIFT_EXPR, compute_mode, t1, | |
3254 | build_int_2 (lgup, 0), | |
3255 | tquotient, 0); | |
3256 | } | |
3257 | else | |
3258 | { | |
3259 | rtx t1, t2, t3; | |
3260 | t1 = expand_shift (RSHIFT_EXPR, compute_mode, op0, | |
3261 | build_int_2 (size - 1, 0), | |
3262 | NULL_RTX, 0); | |
3263 | t2 = expand_shift (RSHIFT_EXPR, compute_mode, t1, | |
3264 | build_int_2 (size - lgup, 0), | |
3265 | NULL_RTX, 1); | |
38a448ca RH |
3266 | t3 = force_operand (gen_rtx_PLUS (compute_mode, |
3267 | op0, t2), | |
55c2d311 TG |
3268 | NULL_RTX); |
3269 | quotient = expand_shift (RSHIFT_EXPR, compute_mode, t3, | |
3270 | build_int_2 (lgup, 0), | |
3271 | tquotient, 0); | |
3272 | } | |
3273 | ||
e8031612 RK |
3274 | /* We have computed OP0 / abs(OP1). If OP1 is negative, negate |
3275 | the quotient. */ | |
55c2d311 TG |
3276 | if (d < 0) |
3277 | { | |
3278 | insn = get_last_insn (); | |
4e430df8 RK |
3279 | if (insn != last |
3280 | && (set = single_set (insn)) != 0 | |
c8e7fe58 DE |
3281 | && SET_DEST (set) == quotient |
3282 | && abs_d < ((unsigned HOST_WIDE_INT) 1 | |
3283 | << (HOST_BITS_PER_WIDE_INT - 1))) | |
7e5bda2c AM |
3284 | set_unique_reg_note (insn, |
3285 | REG_EQUAL, | |
3286 | gen_rtx_DIV (compute_mode, | |
3287 | op0, | |
3288 | GEN_INT (abs_d))); | |
55c2d311 TG |
3289 | |
3290 | quotient = expand_unop (compute_mode, neg_optab, | |
3291 | quotient, quotient, 0); | |
3292 | } | |
3293 | } | |
34f016ed | 3294 | else if (size <= HOST_BITS_PER_WIDE_INT) |
55c2d311 TG |
3295 | { |
3296 | choose_multiplier (abs_d, size, size - 1, | |
3297 | &ml, &post_shift, &lgup); | |
3298 | if (ml < (unsigned HOST_WIDE_INT) 1 << (size - 1)) | |
3299 | { | |
3300 | rtx t1, t2, t3; | |
3301 | ||
71af73bb TG |
3302 | extra_cost = (shift_cost[post_shift] |
3303 | + shift_cost[size - 1] + add_cost); | |
55c2d311 | 3304 | t1 = expand_mult_highpart (compute_mode, op0, ml, |
71af73bb TG |
3305 | NULL_RTX, 0, |
3306 | max_cost - extra_cost); | |
55c2d311 TG |
3307 | if (t1 == 0) |
3308 | goto fail1; | |
3309 | t2 = expand_shift (RSHIFT_EXPR, compute_mode, t1, | |
3310 | build_int_2 (post_shift, 0), NULL_RTX, 0); | |
3311 | t3 = expand_shift (RSHIFT_EXPR, compute_mode, op0, | |
3312 | build_int_2 (size - 1, 0), NULL_RTX, 0); | |
3313 | if (d < 0) | |
c5c76735 JL |
3314 | quotient |
3315 | = force_operand (gen_rtx_MINUS (compute_mode, | |
3316 | t3, t2), | |
3317 | tquotient); | |
55c2d311 | 3318 | else |
c5c76735 JL |
3319 | quotient |
3320 | = force_operand (gen_rtx_MINUS (compute_mode, | |
3321 | t2, t3), | |
3322 | tquotient); | |
55c2d311 TG |
3323 | } |
3324 | else | |
3325 | { | |
3326 | rtx t1, t2, t3, t4; | |
3327 | ||
3328 | ml |= (~(unsigned HOST_WIDE_INT) 0) << (size - 1); | |
71af73bb TG |
3329 | extra_cost = (shift_cost[post_shift] |
3330 | + shift_cost[size - 1] + 2 * add_cost); | |
55c2d311 | 3331 | t1 = expand_mult_highpart (compute_mode, op0, ml, |
71af73bb TG |
3332 | NULL_RTX, 0, |
3333 | max_cost - extra_cost); | |
55c2d311 TG |
3334 | if (t1 == 0) |
3335 | goto fail1; | |
c5c76735 JL |
3336 | t2 = force_operand (gen_rtx_PLUS (compute_mode, |
3337 | t1, op0), | |
55c2d311 TG |
3338 | NULL_RTX); |
3339 | t3 = expand_shift (RSHIFT_EXPR, compute_mode, t2, | |
c5c76735 JL |
3340 | build_int_2 (post_shift, 0), |
3341 | NULL_RTX, 0); | |
55c2d311 | 3342 | t4 = expand_shift (RSHIFT_EXPR, compute_mode, op0, |
c5c76735 JL |
3343 | build_int_2 (size - 1, 0), |
3344 | NULL_RTX, 0); | |
55c2d311 | 3345 | if (d < 0) |
c5c76735 JL |
3346 | quotient |
3347 | = force_operand (gen_rtx_MINUS (compute_mode, | |
3348 | t4, t3), | |
3349 | tquotient); | |
55c2d311 | 3350 | else |
c5c76735 JL |
3351 | quotient |
3352 | = force_operand (gen_rtx_MINUS (compute_mode, | |
3353 | t3, t4), | |
3354 | tquotient); | |
55c2d311 TG |
3355 | } |
3356 | } | |
34f016ed TG |
3357 | else /* Too wide mode to use tricky code */ |
3358 | break; | |
55c2d311 | 3359 | |
4e430df8 RK |
3360 | insn = get_last_insn (); |
3361 | if (insn != last | |
3362 | && (set = single_set (insn)) != 0 | |
3363 | && SET_DEST (set) == quotient) | |
7e5bda2c AM |
3364 | set_unique_reg_note (insn, |
3365 | REG_EQUAL, | |
3366 | gen_rtx_DIV (compute_mode, op0, op1)); | |
55c2d311 TG |
3367 | } |
3368 | break; | |
3369 | } | |
3370 | fail1: | |
3371 | delete_insns_since (last); | |
3372 | break; | |
44037a66 | 3373 | |
55c2d311 TG |
3374 | case FLOOR_DIV_EXPR: |
3375 | case FLOOR_MOD_EXPR: | |
3376 | /* We will come here only for signed operations. */ | |
3377 | if (op1_is_constant && HOST_BITS_PER_WIDE_INT >= size) | |
3378 | { | |
3379 | unsigned HOST_WIDE_INT mh, ml; | |
3380 | int pre_shift, lgup, post_shift; | |
3381 | HOST_WIDE_INT d = INTVAL (op1); | |
3382 | ||
3383 | if (d > 0) | |
3384 | { | |
3385 | /* We could just as easily deal with negative constants here, | |
3386 | but it does not seem worth the trouble for GCC 2.6. */ | |
3387 | if (EXACT_POWER_OF_2_OR_ZERO_P (d)) | |
3388 | { | |
3389 | pre_shift = floor_log2 (d); | |
3390 | if (rem_flag) | |
3391 | { | |
3392 | remainder = expand_binop (compute_mode, and_optab, op0, | |
3393 | GEN_INT (((HOST_WIDE_INT) 1 << pre_shift) - 1), | |
3394 | remainder, 0, OPTAB_LIB_WIDEN); | |
3395 | if (remainder) | |
c8dbc8ca | 3396 | return gen_lowpart (mode, remainder); |
55c2d311 TG |
3397 | } |
3398 | quotient = expand_shift (RSHIFT_EXPR, compute_mode, op0, | |
3399 | build_int_2 (pre_shift, 0), | |
3400 | tquotient, 0); | |
3401 | } | |
3402 | else | |
3403 | { | |
3404 | rtx t1, t2, t3, t4; | |
3405 | ||
3406 | mh = choose_multiplier (d, size, size - 1, | |
3407 | &ml, &post_shift, &lgup); | |
3408 | if (mh) | |
3409 | abort (); | |
3410 | ||
3411 | t1 = expand_shift (RSHIFT_EXPR, compute_mode, op0, | |
3412 | build_int_2 (size - 1, 0), NULL_RTX, 0); | |
3413 | t2 = expand_binop (compute_mode, xor_optab, op0, t1, | |
3414 | NULL_RTX, 0, OPTAB_WIDEN); | |
71af73bb TG |
3415 | extra_cost = (shift_cost[post_shift] |
3416 | + shift_cost[size - 1] + 2 * add_cost); | |
55c2d311 | 3417 | t3 = expand_mult_highpart (compute_mode, t2, ml, |
71af73bb TG |
3418 | NULL_RTX, 1, |
3419 | max_cost - extra_cost); | |
55c2d311 TG |
3420 | if (t3 != 0) |
3421 | { | |
3422 | t4 = expand_shift (RSHIFT_EXPR, compute_mode, t3, | |
3423 | build_int_2 (post_shift, 0), | |
3424 | NULL_RTX, 1); | |
3425 | quotient = expand_binop (compute_mode, xor_optab, | |
3426 | t4, t1, tquotient, 0, | |
3427 | OPTAB_WIDEN); | |
3428 | } | |
3429 | } | |
3430 | } | |
3431 | else | |
3432 | { | |
3433 | rtx nsign, t1, t2, t3, t4; | |
38a448ca RH |
3434 | t1 = force_operand (gen_rtx_PLUS (compute_mode, |
3435 | op0, constm1_rtx), NULL_RTX); | |
55c2d311 TG |
3436 | t2 = expand_binop (compute_mode, ior_optab, op0, t1, NULL_RTX, |
3437 | 0, OPTAB_WIDEN); | |
3438 | nsign = expand_shift (RSHIFT_EXPR, compute_mode, t2, | |
3439 | build_int_2 (size - 1, 0), NULL_RTX, 0); | |
38a448ca | 3440 | t3 = force_operand (gen_rtx_MINUS (compute_mode, t1, nsign), |
55c2d311 TG |
3441 | NULL_RTX); |
3442 | t4 = expand_divmod (0, TRUNC_DIV_EXPR, compute_mode, t3, op1, | |
3443 | NULL_RTX, 0); | |
3444 | if (t4) | |
3445 | { | |
3446 | rtx t5; | |
3447 | t5 = expand_unop (compute_mode, one_cmpl_optab, nsign, | |
3448 | NULL_RTX, 0); | |
38a448ca RH |
3449 | quotient = force_operand (gen_rtx_PLUS (compute_mode, |
3450 | t4, t5), | |
55c2d311 TG |
3451 | tquotient); |
3452 | } | |
3453 | } | |
3454 | } | |
3455 | ||
3456 | if (quotient != 0) | |
3457 | break; | |
3458 | delete_insns_since (last); | |
3459 | ||
3460 | /* Try using an instruction that produces both the quotient and | |
3461 | remainder, using truncation. We can easily compensate the quotient | |
3462 | or remainder to get floor rounding, once we have the remainder. | |
3463 | Notice that we compute also the final remainder value here, | |
3464 | and return the result right away. */ | |
a45cf58c | 3465 | if (target == 0 || GET_MODE (target) != compute_mode) |
55c2d311 | 3466 | target = gen_reg_rtx (compute_mode); |
668443c9 | 3467 | |
55c2d311 TG |
3468 | if (rem_flag) |
3469 | { | |
668443c9 RK |
3470 | remainder |
3471 | = GET_CODE (target) == REG ? target : gen_reg_rtx (compute_mode); | |
55c2d311 TG |
3472 | quotient = gen_reg_rtx (compute_mode); |
3473 | } | |
3474 | else | |
3475 | { | |
668443c9 RK |
3476 | quotient |
3477 | = GET_CODE (target) == REG ? target : gen_reg_rtx (compute_mode); | |
55c2d311 TG |
3478 | remainder = gen_reg_rtx (compute_mode); |
3479 | } | |
3480 | ||
3481 | if (expand_twoval_binop (sdivmod_optab, op0, op1, | |
3482 | quotient, remainder, 0)) | |
3483 | { | |
3484 | /* This could be computed with a branch-less sequence. | |
3485 | Save that for later. */ | |
3486 | rtx tem; | |
3487 | rtx label = gen_label_rtx (); | |
f5963e61 | 3488 | do_cmp_and_jump (remainder, const0_rtx, EQ, compute_mode, label); |
55c2d311 TG |
3489 | tem = expand_binop (compute_mode, xor_optab, op0, op1, |
3490 | NULL_RTX, 0, OPTAB_WIDEN); | |
f5963e61 | 3491 | do_cmp_and_jump (tem, const0_rtx, GE, compute_mode, label); |
55c2d311 TG |
3492 | expand_dec (quotient, const1_rtx); |
3493 | expand_inc (remainder, op1); | |
3494 | emit_label (label); | |
c8dbc8ca | 3495 | return gen_lowpart (mode, rem_flag ? remainder : quotient); |
55c2d311 TG |
3496 | } |
3497 | ||
3498 | /* No luck with division elimination or divmod. Have to do it | |
3499 | by conditionally adjusting op0 *and* the result. */ | |
44037a66 | 3500 | { |
55c2d311 TG |
3501 | rtx label1, label2, label3, label4, label5; |
3502 | rtx adjusted_op0; | |
3503 | rtx tem; | |
3504 | ||
3505 | quotient = gen_reg_rtx (compute_mode); | |
3506 | adjusted_op0 = copy_to_mode_reg (compute_mode, op0); | |
3507 | label1 = gen_label_rtx (); | |
3508 | label2 = gen_label_rtx (); | |
3509 | label3 = gen_label_rtx (); | |
3510 | label4 = gen_label_rtx (); | |
3511 | label5 = gen_label_rtx (); | |
f5963e61 JL |
3512 | do_cmp_and_jump (op1, const0_rtx, LT, compute_mode, label2); |
3513 | do_cmp_and_jump (adjusted_op0, const0_rtx, LT, compute_mode, label1); | |
55c2d311 TG |
3514 | tem = expand_binop (compute_mode, sdiv_optab, adjusted_op0, op1, |
3515 | quotient, 0, OPTAB_LIB_WIDEN); | |
3516 | if (tem != quotient) | |
3517 | emit_move_insn (quotient, tem); | |
3518 | emit_jump_insn (gen_jump (label5)); | |
3519 | emit_barrier (); | |
3520 | emit_label (label1); | |
44037a66 | 3521 | expand_inc (adjusted_op0, const1_rtx); |
55c2d311 TG |
3522 | emit_jump_insn (gen_jump (label4)); |
3523 | emit_barrier (); | |
3524 | emit_label (label2); | |
f5963e61 | 3525 | do_cmp_and_jump (adjusted_op0, const0_rtx, GT, compute_mode, label3); |
55c2d311 TG |
3526 | tem = expand_binop (compute_mode, sdiv_optab, adjusted_op0, op1, |
3527 | quotient, 0, OPTAB_LIB_WIDEN); | |
3528 | if (tem != quotient) | |
3529 | emit_move_insn (quotient, tem); | |
3530 | emit_jump_insn (gen_jump (label5)); | |
3531 | emit_barrier (); | |
3532 | emit_label (label3); | |
3533 | expand_dec (adjusted_op0, const1_rtx); | |
3534 | emit_label (label4); | |
3535 | tem = expand_binop (compute_mode, sdiv_optab, adjusted_op0, op1, | |
3536 | quotient, 0, OPTAB_LIB_WIDEN); | |
3537 | if (tem != quotient) | |
3538 | emit_move_insn (quotient, tem); | |
3539 | expand_dec (quotient, const1_rtx); | |
3540 | emit_label (label5); | |
44037a66 | 3541 | } |
55c2d311 | 3542 | break; |
44037a66 | 3543 | |
55c2d311 TG |
3544 | case CEIL_DIV_EXPR: |
3545 | case CEIL_MOD_EXPR: | |
3546 | if (unsignedp) | |
3547 | { | |
9176af2f TG |
3548 | if (op1_is_constant && EXACT_POWER_OF_2_OR_ZERO_P (INTVAL (op1))) |
3549 | { | |
3550 | rtx t1, t2, t3; | |
3551 | unsigned HOST_WIDE_INT d = INTVAL (op1); | |
3552 | t1 = expand_shift (RSHIFT_EXPR, compute_mode, op0, | |
3553 | build_int_2 (floor_log2 (d), 0), | |
412381d9 | 3554 | tquotient, 1); |
9176af2f TG |
3555 | t2 = expand_binop (compute_mode, and_optab, op0, |
3556 | GEN_INT (d - 1), | |
3557 | NULL_RTX, 1, OPTAB_LIB_WIDEN); | |
3558 | t3 = gen_reg_rtx (compute_mode); | |
3559 | t3 = emit_store_flag (t3, NE, t2, const0_rtx, | |
3560 | compute_mode, 1, 1); | |
412381d9 TG |
3561 | if (t3 == 0) |
3562 | { | |
3563 | rtx lab; | |
3564 | lab = gen_label_rtx (); | |
f5963e61 | 3565 | do_cmp_and_jump (t2, const0_rtx, EQ, compute_mode, lab); |
412381d9 TG |
3566 | expand_inc (t1, const1_rtx); |
3567 | emit_label (lab); | |
3568 | quotient = t1; | |
3569 | } | |
3570 | else | |
38a448ca RH |
3571 | quotient = force_operand (gen_rtx_PLUS (compute_mode, |
3572 | t1, t3), | |
412381d9 | 3573 | tquotient); |
9176af2f TG |
3574 | break; |
3575 | } | |
55c2d311 TG |
3576 | |
3577 | /* Try using an instruction that produces both the quotient and | |
3578 | remainder, using truncation. We can easily compensate the | |
3579 | quotient or remainder to get ceiling rounding, once we have the | |
3580 | remainder. Notice that we compute also the final remainder | |
3581 | value here, and return the result right away. */ | |
a45cf58c | 3582 | if (target == 0 || GET_MODE (target) != compute_mode) |
55c2d311 | 3583 | target = gen_reg_rtx (compute_mode); |
668443c9 | 3584 | |
55c2d311 TG |
3585 | if (rem_flag) |
3586 | { | |
668443c9 RK |
3587 | remainder = (GET_CODE (target) == REG |
3588 | ? target : gen_reg_rtx (compute_mode)); | |
55c2d311 TG |
3589 | quotient = gen_reg_rtx (compute_mode); |
3590 | } | |
3591 | else | |
3592 | { | |
668443c9 RK |
3593 | quotient = (GET_CODE (target) == REG |
3594 | ? target : gen_reg_rtx (compute_mode)); | |
55c2d311 TG |
3595 | remainder = gen_reg_rtx (compute_mode); |
3596 | } | |
3597 | ||
3598 | if (expand_twoval_binop (udivmod_optab, op0, op1, quotient, | |
3599 | remainder, 1)) | |
3600 | { | |
3601 | /* This could be computed with a branch-less sequence. | |
3602 | Save that for later. */ | |
3603 | rtx label = gen_label_rtx (); | |
f5963e61 JL |
3604 | do_cmp_and_jump (remainder, const0_rtx, EQ, |
3605 | compute_mode, label); | |
55c2d311 TG |
3606 | expand_inc (quotient, const1_rtx); |
3607 | expand_dec (remainder, op1); | |
3608 | emit_label (label); | |
c8dbc8ca | 3609 | return gen_lowpart (mode, rem_flag ? remainder : quotient); |
55c2d311 TG |
3610 | } |
3611 | ||
3612 | /* No luck with division elimination or divmod. Have to do it | |
3613 | by conditionally adjusting op0 *and* the result. */ | |
44037a66 | 3614 | { |
55c2d311 TG |
3615 | rtx label1, label2; |
3616 | rtx adjusted_op0, tem; | |
3617 | ||
3618 | quotient = gen_reg_rtx (compute_mode); | |
3619 | adjusted_op0 = copy_to_mode_reg (compute_mode, op0); | |
3620 | label1 = gen_label_rtx (); | |
3621 | label2 = gen_label_rtx (); | |
f5963e61 JL |
3622 | do_cmp_and_jump (adjusted_op0, const0_rtx, NE, |
3623 | compute_mode, label1); | |
55c2d311 TG |
3624 | emit_move_insn (quotient, const0_rtx); |
3625 | emit_jump_insn (gen_jump (label2)); | |
3626 | emit_barrier (); | |
3627 | emit_label (label1); | |
3628 | expand_dec (adjusted_op0, const1_rtx); | |
3629 | tem = expand_binop (compute_mode, udiv_optab, adjusted_op0, op1, | |
3630 | quotient, 1, OPTAB_LIB_WIDEN); | |
3631 | if (tem != quotient) | |
3632 | emit_move_insn (quotient, tem); | |
3633 | expand_inc (quotient, const1_rtx); | |
3634 | emit_label (label2); | |
44037a66 | 3635 | } |
55c2d311 TG |
3636 | } |
3637 | else /* signed */ | |
3638 | { | |
73f27728 RK |
3639 | if (op1_is_constant && EXACT_POWER_OF_2_OR_ZERO_P (INTVAL (op1)) |
3640 | && INTVAL (op1) >= 0) | |
3641 | { | |
3642 | /* This is extremely similar to the code for the unsigned case | |
3643 | above. For 2.7 we should merge these variants, but for | |
3644 | 2.6.1 I don't want to touch the code for unsigned since that | |
3645 | get used in C. The signed case will only be used by other | |
3646 | languages (Ada). */ | |
3647 | ||
3648 | rtx t1, t2, t3; | |
3649 | unsigned HOST_WIDE_INT d = INTVAL (op1); | |
3650 | t1 = expand_shift (RSHIFT_EXPR, compute_mode, op0, | |
3651 | build_int_2 (floor_log2 (d), 0), | |
3652 | tquotient, 0); | |
3653 | t2 = expand_binop (compute_mode, and_optab, op0, | |
3654 | GEN_INT (d - 1), | |
3655 | NULL_RTX, 1, OPTAB_LIB_WIDEN); | |
3656 | t3 = gen_reg_rtx (compute_mode); | |
3657 | t3 = emit_store_flag (t3, NE, t2, const0_rtx, | |
3658 | compute_mode, 1, 1); | |
3659 | if (t3 == 0) | |
3660 | { | |
3661 | rtx lab; | |
3662 | lab = gen_label_rtx (); | |
f5963e61 | 3663 | do_cmp_and_jump (t2, const0_rtx, EQ, compute_mode, lab); |
73f27728 RK |
3664 | expand_inc (t1, const1_rtx); |
3665 | emit_label (lab); | |
3666 | quotient = t1; | |
3667 | } | |
3668 | else | |
38a448ca RH |
3669 | quotient = force_operand (gen_rtx_PLUS (compute_mode, |
3670 | t1, t3), | |
73f27728 RK |
3671 | tquotient); |
3672 | break; | |
3673 | } | |
3674 | ||
55c2d311 TG |
3675 | /* Try using an instruction that produces both the quotient and |
3676 | remainder, using truncation. We can easily compensate the | |
3677 | quotient or remainder to get ceiling rounding, once we have the | |
3678 | remainder. Notice that we compute also the final remainder | |
3679 | value here, and return the result right away. */ | |
a45cf58c | 3680 | if (target == 0 || GET_MODE (target) != compute_mode) |
55c2d311 TG |
3681 | target = gen_reg_rtx (compute_mode); |
3682 | if (rem_flag) | |
3683 | { | |
668443c9 RK |
3684 | remainder= (GET_CODE (target) == REG |
3685 | ? target : gen_reg_rtx (compute_mode)); | |
55c2d311 TG |
3686 | quotient = gen_reg_rtx (compute_mode); |
3687 | } | |
3688 | else | |
3689 | { | |
668443c9 RK |
3690 | quotient = (GET_CODE (target) == REG |
3691 | ? target : gen_reg_rtx (compute_mode)); | |
55c2d311 TG |
3692 | remainder = gen_reg_rtx (compute_mode); |
3693 | } | |
3694 | ||
3695 | if (expand_twoval_binop (sdivmod_optab, op0, op1, quotient, | |
3696 | remainder, 0)) | |
3697 | { | |
3698 | /* This could be computed with a branch-less sequence. | |
3699 | Save that for later. */ | |
3700 | rtx tem; | |
3701 | rtx label = gen_label_rtx (); | |
f5963e61 JL |
3702 | do_cmp_and_jump (remainder, const0_rtx, EQ, |
3703 | compute_mode, label); | |
55c2d311 TG |
3704 | tem = expand_binop (compute_mode, xor_optab, op0, op1, |
3705 | NULL_RTX, 0, OPTAB_WIDEN); | |
f5963e61 | 3706 | do_cmp_and_jump (tem, const0_rtx, LT, compute_mode, label); |
55c2d311 TG |
3707 | expand_inc (quotient, const1_rtx); |
3708 | expand_dec (remainder, op1); | |
3709 | emit_label (label); | |
c8dbc8ca | 3710 | return gen_lowpart (mode, rem_flag ? remainder : quotient); |
55c2d311 TG |
3711 | } |
3712 | ||
3713 | /* No luck with division elimination or divmod. Have to do it | |
3714 | by conditionally adjusting op0 *and* the result. */ | |
44037a66 | 3715 | { |
55c2d311 TG |
3716 | rtx label1, label2, label3, label4, label5; |
3717 | rtx adjusted_op0; | |
3718 | rtx tem; | |
3719 | ||
3720 | quotient = gen_reg_rtx (compute_mode); | |
3721 | adjusted_op0 = copy_to_mode_reg (compute_mode, op0); | |
3722 | label1 = gen_label_rtx (); | |
3723 | label2 = gen_label_rtx (); | |
3724 | label3 = gen_label_rtx (); | |
3725 | label4 = gen_label_rtx (); | |
3726 | label5 = gen_label_rtx (); | |
f5963e61 JL |
3727 | do_cmp_and_jump (op1, const0_rtx, LT, compute_mode, label2); |
3728 | do_cmp_and_jump (adjusted_op0, const0_rtx, GT, | |
3729 | compute_mode, label1); | |
55c2d311 TG |
3730 | tem = expand_binop (compute_mode, sdiv_optab, adjusted_op0, op1, |
3731 | quotient, 0, OPTAB_LIB_WIDEN); | |
3732 | if (tem != quotient) | |
3733 | emit_move_insn (quotient, tem); | |
3734 | emit_jump_insn (gen_jump (label5)); | |
3735 | emit_barrier (); | |
3736 | emit_label (label1); | |
3737 | expand_dec (adjusted_op0, const1_rtx); | |
3738 | emit_jump_insn (gen_jump (label4)); | |
3739 | emit_barrier (); | |
3740 | emit_label (label2); | |
f5963e61 JL |
3741 | do_cmp_and_jump (adjusted_op0, const0_rtx, LT, |
3742 | compute_mode, label3); | |
55c2d311 TG |
3743 | tem = expand_binop (compute_mode, sdiv_optab, adjusted_op0, op1, |
3744 | quotient, 0, OPTAB_LIB_WIDEN); | |
3745 | if (tem != quotient) | |
3746 | emit_move_insn (quotient, tem); | |
3747 | emit_jump_insn (gen_jump (label5)); | |
3748 | emit_barrier (); | |
3749 | emit_label (label3); | |
3750 | expand_inc (adjusted_op0, const1_rtx); | |
3751 | emit_label (label4); | |
3752 | tem = expand_binop (compute_mode, sdiv_optab, adjusted_op0, op1, | |
3753 | quotient, 0, OPTAB_LIB_WIDEN); | |
3754 | if (tem != quotient) | |
3755 | emit_move_insn (quotient, tem); | |
3756 | expand_inc (quotient, const1_rtx); | |
3757 | emit_label (label5); | |
44037a66 | 3758 | } |
55c2d311 TG |
3759 | } |
3760 | break; | |
bc1c7e93 | 3761 | |
55c2d311 TG |
3762 | case EXACT_DIV_EXPR: |
3763 | if (op1_is_constant && HOST_BITS_PER_WIDE_INT >= size) | |
3764 | { | |
3765 | HOST_WIDE_INT d = INTVAL (op1); | |
3766 | unsigned HOST_WIDE_INT ml; | |
3767 | int post_shift; | |
3768 | rtx t1; | |
3769 | ||
3770 | post_shift = floor_log2 (d & -d); | |
3771 | ml = invert_mod2n (d >> post_shift, size); | |
3772 | t1 = expand_mult (compute_mode, op0, GEN_INT (ml), NULL_RTX, | |
3773 | unsignedp); | |
3774 | quotient = expand_shift (RSHIFT_EXPR, compute_mode, t1, | |
3775 | build_int_2 (post_shift, 0), | |
3776 | NULL_RTX, unsignedp); | |
3777 | ||
3778 | insn = get_last_insn (); | |
7e5bda2c AM |
3779 | set_unique_reg_note (insn, |
3780 | REG_EQUAL, | |
3781 | gen_rtx_fmt_ee (unsignedp ? UDIV : DIV, | |
3782 | compute_mode, | |
3783 | op0, op1)); | |
55c2d311 TG |
3784 | } |
3785 | break; | |
3786 | ||
3787 | case ROUND_DIV_EXPR: | |
3788 | case ROUND_MOD_EXPR: | |
69f61901 RK |
3789 | if (unsignedp) |
3790 | { | |
3791 | rtx tem; | |
3792 | rtx label; | |
3793 | label = gen_label_rtx (); | |
3794 | quotient = gen_reg_rtx (compute_mode); | |
3795 | remainder = gen_reg_rtx (compute_mode); | |
3796 | if (expand_twoval_binop (udivmod_optab, op0, op1, quotient, remainder, 1) == 0) | |
3797 | { | |
3798 | rtx tem; | |
3799 | quotient = expand_binop (compute_mode, udiv_optab, op0, op1, | |
3800 | quotient, 1, OPTAB_LIB_WIDEN); | |
3801 | tem = expand_mult (compute_mode, quotient, op1, NULL_RTX, 1); | |
3802 | remainder = expand_binop (compute_mode, sub_optab, op0, tem, | |
3803 | remainder, 1, OPTAB_LIB_WIDEN); | |
3804 | } | |
3805 | tem = plus_constant (op1, -1); | |
3806 | tem = expand_shift (RSHIFT_EXPR, compute_mode, tem, | |
3807 | build_int_2 (1, 0), NULL_RTX, 1); | |
f5963e61 | 3808 | do_cmp_and_jump (remainder, tem, LEU, compute_mode, label); |
69f61901 RK |
3809 | expand_inc (quotient, const1_rtx); |
3810 | expand_dec (remainder, op1); | |
3811 | emit_label (label); | |
3812 | } | |
3813 | else | |
3814 | { | |
3815 | rtx abs_rem, abs_op1, tem, mask; | |
3816 | rtx label; | |
3817 | label = gen_label_rtx (); | |
3818 | quotient = gen_reg_rtx (compute_mode); | |
3819 | remainder = gen_reg_rtx (compute_mode); | |
3820 | if (expand_twoval_binop (sdivmod_optab, op0, op1, quotient, remainder, 0) == 0) | |
3821 | { | |
3822 | rtx tem; | |
3823 | quotient = expand_binop (compute_mode, sdiv_optab, op0, op1, | |
3824 | quotient, 0, OPTAB_LIB_WIDEN); | |
3825 | tem = expand_mult (compute_mode, quotient, op1, NULL_RTX, 0); | |
3826 | remainder = expand_binop (compute_mode, sub_optab, op0, tem, | |
3827 | remainder, 0, OPTAB_LIB_WIDEN); | |
3828 | } | |
91813b28 KG |
3829 | abs_rem = expand_abs (compute_mode, remainder, NULL_RTX, 0); |
3830 | abs_op1 = expand_abs (compute_mode, op1, NULL_RTX, 0); | |
69f61901 RK |
3831 | tem = expand_shift (LSHIFT_EXPR, compute_mode, abs_rem, |
3832 | build_int_2 (1, 0), NULL_RTX, 1); | |
f5963e61 | 3833 | do_cmp_and_jump (tem, abs_op1, LTU, compute_mode, label); |
69f61901 RK |
3834 | tem = expand_binop (compute_mode, xor_optab, op0, op1, |
3835 | NULL_RTX, 0, OPTAB_WIDEN); | |
3836 | mask = expand_shift (RSHIFT_EXPR, compute_mode, tem, | |
3837 | build_int_2 (size - 1, 0), NULL_RTX, 0); | |
3838 | tem = expand_binop (compute_mode, xor_optab, mask, const1_rtx, | |
3839 | NULL_RTX, 0, OPTAB_WIDEN); | |
3840 | tem = expand_binop (compute_mode, sub_optab, tem, mask, | |
3841 | NULL_RTX, 0, OPTAB_WIDEN); | |
3842 | expand_inc (quotient, tem); | |
3843 | tem = expand_binop (compute_mode, xor_optab, mask, op1, | |
3844 | NULL_RTX, 0, OPTAB_WIDEN); | |
3845 | tem = expand_binop (compute_mode, sub_optab, tem, mask, | |
3846 | NULL_RTX, 0, OPTAB_WIDEN); | |
3847 | expand_dec (remainder, tem); | |
3848 | emit_label (label); | |
3849 | } | |
3850 | return gen_lowpart (mode, rem_flag ? remainder : quotient); | |
e9a25f70 JL |
3851 | |
3852 | default: | |
3853 | abort (); | |
55c2d311 | 3854 | } |
44037a66 | 3855 | |
55c2d311 | 3856 | if (quotient == 0) |
44037a66 | 3857 | { |
a45cf58c RK |
3858 | if (target && GET_MODE (target) != compute_mode) |
3859 | target = 0; | |
3860 | ||
55c2d311 | 3861 | if (rem_flag) |
44037a66 | 3862 | { |
32fdf36b TG |
3863 | /* Try to produce the remainder without producing the quotient. |
3864 | If we seem to have a divmod patten that does not require widening, | |
3865 | don't try windening here. We should really have an WIDEN argument | |
3866 | to expand_twoval_binop, since what we'd really like to do here is | |
3867 | 1) try a mod insn in compute_mode | |
3868 | 2) try a divmod insn in compute_mode | |
3869 | 3) try a div insn in compute_mode and multiply-subtract to get | |
3870 | remainder | |
3871 | 4) try the same things with widening allowed. */ | |
3872 | remainder | |
3873 | = sign_expand_binop (compute_mode, umod_optab, smod_optab, | |
3874 | op0, op1, target, | |
3875 | unsignedp, | |
3876 | ((optab2->handlers[(int) compute_mode].insn_code | |
3877 | != CODE_FOR_nothing) | |
3878 | ? OPTAB_DIRECT : OPTAB_WIDEN)); | |
55c2d311 | 3879 | if (remainder == 0) |
44037a66 TG |
3880 | { |
3881 | /* No luck there. Can we do remainder and divide at once | |
3882 | without a library call? */ | |
55c2d311 TG |
3883 | remainder = gen_reg_rtx (compute_mode); |
3884 | if (! expand_twoval_binop ((unsignedp | |
3885 | ? udivmod_optab | |
3886 | : sdivmod_optab), | |
3887 | op0, op1, | |
3888 | NULL_RTX, remainder, unsignedp)) | |
3889 | remainder = 0; | |
44037a66 | 3890 | } |
55c2d311 TG |
3891 | |
3892 | if (remainder) | |
3893 | return gen_lowpart (mode, remainder); | |
44037a66 | 3894 | } |
44037a66 | 3895 | |
dc38b292 RK |
3896 | /* Produce the quotient. Try a quotient insn, but not a library call. |
3897 | If we have a divmod in this mode, use it in preference to widening | |
3898 | the div (for this test we assume it will not fail). Note that optab2 | |
3899 | is set to the one of the two optabs that the call below will use. */ | |
3900 | quotient | |
3901 | = sign_expand_binop (compute_mode, udiv_optab, sdiv_optab, | |
3902 | op0, op1, rem_flag ? NULL_RTX : target, | |
3903 | unsignedp, | |
3904 | ((optab2->handlers[(int) compute_mode].insn_code | |
3905 | != CODE_FOR_nothing) | |
3906 | ? OPTAB_DIRECT : OPTAB_WIDEN)); | |
3907 | ||
55c2d311 | 3908 | if (quotient == 0) |
44037a66 TG |
3909 | { |
3910 | /* No luck there. Try a quotient-and-remainder insn, | |
3911 | keeping the quotient alone. */ | |
55c2d311 | 3912 | quotient = gen_reg_rtx (compute_mode); |
44037a66 | 3913 | if (! expand_twoval_binop (unsignedp ? udivmod_optab : sdivmod_optab, |
55c2d311 TG |
3914 | op0, op1, |
3915 | quotient, NULL_RTX, unsignedp)) | |
3916 | { | |
3917 | quotient = 0; | |
3918 | if (! rem_flag) | |
3919 | /* Still no luck. If we are not computing the remainder, | |
3920 | use a library call for the quotient. */ | |
3921 | quotient = sign_expand_binop (compute_mode, | |
3922 | udiv_optab, sdiv_optab, | |
3923 | op0, op1, target, | |
3924 | unsignedp, OPTAB_LIB_WIDEN); | |
3925 | } | |
44037a66 | 3926 | } |
44037a66 TG |
3927 | } |
3928 | ||
44037a66 TG |
3929 | if (rem_flag) |
3930 | { | |
a45cf58c RK |
3931 | if (target && GET_MODE (target) != compute_mode) |
3932 | target = 0; | |
3933 | ||
55c2d311 | 3934 | if (quotient == 0) |
44037a66 | 3935 | /* No divide instruction either. Use library for remainder. */ |
55c2d311 TG |
3936 | remainder = sign_expand_binop (compute_mode, umod_optab, smod_optab, |
3937 | op0, op1, target, | |
3938 | unsignedp, OPTAB_LIB_WIDEN); | |
44037a66 TG |
3939 | else |
3940 | { | |
3941 | /* We divided. Now finish doing X - Y * (X / Y). */ | |
55c2d311 TG |
3942 | remainder = expand_mult (compute_mode, quotient, op1, |
3943 | NULL_RTX, unsignedp); | |
3944 | remainder = expand_binop (compute_mode, sub_optab, op0, | |
3945 | remainder, target, unsignedp, | |
3946 | OPTAB_LIB_WIDEN); | |
44037a66 TG |
3947 | } |
3948 | } | |
3949 | ||
55c2d311 | 3950 | return gen_lowpart (mode, rem_flag ? remainder : quotient); |
44037a66 TG |
3951 | } |
3952 | \f | |
3953 | /* Return a tree node with data type TYPE, describing the value of X. | |
3954 | Usually this is an RTL_EXPR, if there is no obvious better choice. | |
3955 | X may be an expression, however we only support those expressions | |
3956 | generated by loop.c. */ | |
3957 | ||
3958 | tree | |
3959 | make_tree (type, x) | |
3960 | tree type; | |
3961 | rtx x; | |
3962 | { | |
3963 | tree t; | |
3964 | ||
3965 | switch (GET_CODE (x)) | |
3966 | { | |
3967 | case CONST_INT: | |
3968 | t = build_int_2 (INTVAL (x), | |
172f4957 DM |
3969 | (TREE_UNSIGNED (type) |
3970 | && (GET_MODE_BITSIZE (TYPE_MODE (type)) < HOST_BITS_PER_WIDE_INT)) | |
3971 | || INTVAL (x) >= 0 ? 0 : -1); | |
44037a66 TG |
3972 | TREE_TYPE (t) = type; |
3973 | return t; | |
3974 | ||
3975 | case CONST_DOUBLE: | |
3976 | if (GET_MODE (x) == VOIDmode) | |
3977 | { | |
3978 | t = build_int_2 (CONST_DOUBLE_LOW (x), CONST_DOUBLE_HIGH (x)); | |
3979 | TREE_TYPE (t) = type; | |
3980 | } | |
3981 | else | |
3982 | { | |
3983 | REAL_VALUE_TYPE d; | |
3984 | ||
3985 | REAL_VALUE_FROM_CONST_DOUBLE (d, x); | |
3986 | t = build_real (type, d); | |
3987 | } | |
3988 | ||
3989 | return t; | |
3990 | ||
3991 | case PLUS: | |
3992 | return fold (build (PLUS_EXPR, type, make_tree (type, XEXP (x, 0)), | |
3993 | make_tree (type, XEXP (x, 1)))); | |
3994 | ||
3995 | case MINUS: | |
3996 | return fold (build (MINUS_EXPR, type, make_tree (type, XEXP (x, 0)), | |
3997 | make_tree (type, XEXP (x, 1)))); | |
3998 | ||
3999 | case NEG: | |
4000 | return fold (build1 (NEGATE_EXPR, type, make_tree (type, XEXP (x, 0)))); | |
4001 | ||
4002 | case MULT: | |
4003 | return fold (build (MULT_EXPR, type, make_tree (type, XEXP (x, 0)), | |
4004 | make_tree (type, XEXP (x, 1)))); | |
4005 | ||
4006 | case ASHIFT: | |
4007 | return fold (build (LSHIFT_EXPR, type, make_tree (type, XEXP (x, 0)), | |
4008 | make_tree (type, XEXP (x, 1)))); | |
4009 | ||
4010 | case LSHIFTRT: | |
4011 | return fold (convert (type, | |
4012 | build (RSHIFT_EXPR, unsigned_type (type), | |
4013 | make_tree (unsigned_type (type), | |
4014 | XEXP (x, 0)), | |
4015 | make_tree (type, XEXP (x, 1))))); | |
4016 | ||
4017 | case ASHIFTRT: | |
4018 | return fold (convert (type, | |
4019 | build (RSHIFT_EXPR, signed_type (type), | |
4020 | make_tree (signed_type (type), XEXP (x, 0)), | |
4021 | make_tree (type, XEXP (x, 1))))); | |
4022 | ||
4023 | case DIV: | |
4024 | if (TREE_CODE (type) != REAL_TYPE) | |
4025 | t = signed_type (type); | |
4026 | else | |
4027 | t = type; | |
4028 | ||
4029 | return fold (convert (type, | |
4030 | build (TRUNC_DIV_EXPR, t, | |
4031 | make_tree (t, XEXP (x, 0)), | |
4032 | make_tree (t, XEXP (x, 1))))); | |
4033 | case UDIV: | |
4034 | t = unsigned_type (type); | |
4035 | return fold (convert (type, | |
4036 | build (TRUNC_DIV_EXPR, t, | |
4037 | make_tree (t, XEXP (x, 0)), | |
4038 | make_tree (t, XEXP (x, 1))))); | |
4039 | default: | |
4040 | t = make_node (RTL_EXPR); | |
4041 | TREE_TYPE (t) = type; | |
4042 | RTL_EXPR_RTL (t) = x; | |
4043 | /* There are no insns to be output | |
4044 | when this rtl_expr is used. */ | |
4045 | RTL_EXPR_SEQUENCE (t) = 0; | |
4046 | return t; | |
4047 | } | |
4048 | } | |
4049 | ||
4050 | /* Return an rtx representing the value of X * MULT + ADD. | |
4051 | TARGET is a suggestion for where to store the result (an rtx). | |
4052 | MODE is the machine mode for the computation. | |
4053 | X and MULT must have mode MODE. ADD may have a different mode. | |
4054 | So can X (defaults to same as MODE). | |
4055 | UNSIGNEDP is non-zero to do unsigned multiplication. | |
4056 | This may emit insns. */ | |
4057 | ||
4058 | rtx | |
4059 | expand_mult_add (x, target, mult, add, mode, unsignedp) | |
4060 | rtx x, target, mult, add; | |
4061 | enum machine_mode mode; | |
4062 | int unsignedp; | |
4063 | { | |
4064 | tree type = type_for_mode (mode, unsignedp); | |
4065 | tree add_type = (GET_MODE (add) == VOIDmode | |
36d747f6 | 4066 | ? type : type_for_mode (GET_MODE (add), unsignedp)); |
44037a66 TG |
4067 | tree result = fold (build (PLUS_EXPR, type, |
4068 | fold (build (MULT_EXPR, type, | |
4069 | make_tree (type, x), | |
4070 | make_tree (type, mult))), | |
4071 | make_tree (add_type, add))); | |
4072 | ||
4073 | return expand_expr (result, target, VOIDmode, 0); | |
4074 | } | |
4075 | \f | |
4076 | /* Compute the logical-and of OP0 and OP1, storing it in TARGET | |
4077 | and returning TARGET. | |
4078 | ||
4079 | If TARGET is 0, a pseudo-register or constant is returned. */ | |
4080 | ||
4081 | rtx | |
4082 | expand_and (op0, op1, target) | |
4083 | rtx op0, op1, target; | |
4084 | { | |
4085 | enum machine_mode mode = VOIDmode; | |
4086 | rtx tem; | |
4087 | ||
4088 | if (GET_MODE (op0) != VOIDmode) | |
4089 | mode = GET_MODE (op0); | |
4090 | else if (GET_MODE (op1) != VOIDmode) | |
4091 | mode = GET_MODE (op1); | |
4092 | ||
4093 | if (mode != VOIDmode) | |
4094 | tem = expand_binop (mode, and_optab, op0, op1, target, 0, OPTAB_LIB_WIDEN); | |
4095 | else if (GET_CODE (op0) == CONST_INT && GET_CODE (op1) == CONST_INT) | |
b1ec3c92 | 4096 | tem = GEN_INT (INTVAL (op0) & INTVAL (op1)); |
44037a66 TG |
4097 | else |
4098 | abort (); | |
4099 | ||
4100 | if (target == 0) | |
4101 | target = tem; | |
4102 | else if (tem != target) | |
4103 | emit_move_insn (target, tem); | |
4104 | return target; | |
4105 | } | |
4106 | \f | |
4107 | /* Emit a store-flags instruction for comparison CODE on OP0 and OP1 | |
4108 | and storing in TARGET. Normally return TARGET. | |
4109 | Return 0 if that cannot be done. | |
4110 | ||
4111 | MODE is the mode to use for OP0 and OP1 should they be CONST_INTs. If | |
4112 | it is VOIDmode, they cannot both be CONST_INT. | |
4113 | ||
4114 | UNSIGNEDP is for the case where we have to widen the operands | |
4115 | to perform the operation. It says to use zero-extension. | |
4116 | ||
4117 | NORMALIZEP is 1 if we should convert the result to be either zero | |
373e7d69 | 4118 | or one. Normalize is -1 if we should convert the result to be |
44037a66 TG |
4119 | either zero or -1. If NORMALIZEP is zero, the result will be left |
4120 | "raw" out of the scc insn. */ | |
4121 | ||
4122 | rtx | |
4123 | emit_store_flag (target, code, op0, op1, mode, unsignedp, normalizep) | |
4124 | rtx target; | |
4125 | enum rtx_code code; | |
4126 | rtx op0, op1; | |
4127 | enum machine_mode mode; | |
4128 | int unsignedp; | |
4129 | int normalizep; | |
4130 | { | |
4131 | rtx subtarget; | |
4132 | enum insn_code icode; | |
4133 | enum machine_mode compare_mode; | |
4134 | enum machine_mode target_mode = GET_MODE (target); | |
4135 | rtx tem; | |
db2f8a07 | 4136 | rtx last = get_last_insn (); |
44037a66 TG |
4137 | rtx pattern, comparison; |
4138 | ||
b30f05db BS |
4139 | if (unsignedp) |
4140 | code = unsigned_condition (code); | |
4141 | ||
c2615a67 RK |
4142 | /* If one operand is constant, make it the second one. Only do this |
4143 | if the other operand is not constant as well. */ | |
4144 | ||
4145 | if ((CONSTANT_P (op0) && ! CONSTANT_P (op1)) | |
4146 | || (GET_CODE (op0) == CONST_INT && GET_CODE (op1) != CONST_INT)) | |
4147 | { | |
4148 | tem = op0; | |
4149 | op0 = op1; | |
4150 | op1 = tem; | |
4151 | code = swap_condition (code); | |
4152 | } | |
4153 | ||
6405e07b DE |
4154 | if (mode == VOIDmode) |
4155 | mode = GET_MODE (op0); | |
4156 | ||
44037a66 TG |
4157 | /* For some comparisons with 1 and -1, we can convert this to |
4158 | comparisons with zero. This will often produce more opportunities for | |
0f41302f | 4159 | store-flag insns. */ |
44037a66 TG |
4160 | |
4161 | switch (code) | |
4162 | { | |
4163 | case LT: | |
4164 | if (op1 == const1_rtx) | |
4165 | op1 = const0_rtx, code = LE; | |
4166 | break; | |
4167 | case LE: | |
4168 | if (op1 == constm1_rtx) | |
4169 | op1 = const0_rtx, code = LT; | |
4170 | break; | |
4171 | case GE: | |
4172 | if (op1 == const1_rtx) | |
4173 | op1 = const0_rtx, code = GT; | |
4174 | break; | |
4175 | case GT: | |
4176 | if (op1 == constm1_rtx) | |
4177 | op1 = const0_rtx, code = GE; | |
4178 | break; | |
4179 | case GEU: | |
4180 | if (op1 == const1_rtx) | |
4181 | op1 = const0_rtx, code = NE; | |
4182 | break; | |
4183 | case LTU: | |
4184 | if (op1 == const1_rtx) | |
4185 | op1 = const0_rtx, code = EQ; | |
4186 | break; | |
e9a25f70 JL |
4187 | default: |
4188 | break; | |
44037a66 TG |
4189 | } |
4190 | ||
6912b84b RK |
4191 | /* If we are comparing a double-word integer with zero, we can convert |
4192 | the comparison into one involving a single word. */ | |
4193 | if (GET_MODE_BITSIZE (mode) == BITS_PER_WORD * 2 | |
4194 | && GET_MODE_CLASS (mode) == MODE_INT | |
4195 | && op1 == const0_rtx) | |
4196 | { | |
4197 | if (code == EQ || code == NE) | |
4198 | { | |
4199 | /* Do a logical OR of the two words and compare the result. */ | |
4200 | rtx op0h = gen_highpart (word_mode, op0); | |
4201 | rtx op0l = gen_lowpart (word_mode, op0); | |
4202 | rtx op0both = expand_binop (word_mode, ior_optab, op0h, op0l, | |
4203 | NULL_RTX, unsignedp, OPTAB_DIRECT); | |
4204 | if (op0both != 0) | |
4205 | return emit_store_flag (target, code, op0both, op1, word_mode, | |
4206 | unsignedp, normalizep); | |
4207 | } | |
4208 | else if (code == LT || code == GE) | |
4209 | /* If testing the sign bit, can just test on high word. */ | |
4210 | return emit_store_flag (target, code, gen_highpart (word_mode, op0), | |
4211 | op1, word_mode, unsignedp, normalizep); | |
4212 | } | |
4213 | ||
44037a66 TG |
4214 | /* From now on, we won't change CODE, so set ICODE now. */ |
4215 | icode = setcc_gen_code[(int) code]; | |
4216 | ||
4217 | /* If this is A < 0 or A >= 0, we can do this by taking the ones | |
4218 | complement of A (for GE) and shifting the sign bit to the low bit. */ | |
4219 | if (op1 == const0_rtx && (code == LT || code == GE) | |
4220 | && GET_MODE_CLASS (mode) == MODE_INT | |
4221 | && (normalizep || STORE_FLAG_VALUE == 1 | |
b1ec3c92 | 4222 | || (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT |
12dd565f | 4223 | && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode)) |
b1ec3c92 | 4224 | == (HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))))) |
44037a66 | 4225 | { |
8deb7047 | 4226 | subtarget = target; |
44037a66 TG |
4227 | |
4228 | /* If the result is to be wider than OP0, it is best to convert it | |
4229 | first. If it is to be narrower, it is *incorrect* to convert it | |
4230 | first. */ | |
4231 | if (GET_MODE_SIZE (target_mode) > GET_MODE_SIZE (mode)) | |
4232 | { | |
b3d4e1b2 | 4233 | op0 = protect_from_queue (op0, 0); |
81722fa9 | 4234 | op0 = convert_modes (target_mode, mode, op0, 0); |
44037a66 TG |
4235 | mode = target_mode; |
4236 | } | |
4237 | ||
4238 | if (target_mode != mode) | |
4239 | subtarget = 0; | |
4240 | ||
4241 | if (code == GE) | |
1d6eaf3d RK |
4242 | op0 = expand_unop (mode, one_cmpl_optab, op0, |
4243 | ((STORE_FLAG_VALUE == 1 || normalizep) | |
4244 | ? 0 : subtarget), 0); | |
44037a66 | 4245 | |
1d6eaf3d | 4246 | if (STORE_FLAG_VALUE == 1 || normalizep) |
44037a66 TG |
4247 | /* If we are supposed to produce a 0/1 value, we want to do |
4248 | a logical shift from the sign bit to the low-order bit; for | |
4249 | a -1/0 value, we do an arithmetic shift. */ | |
4250 | op0 = expand_shift (RSHIFT_EXPR, mode, op0, | |
4251 | size_int (GET_MODE_BITSIZE (mode) - 1), | |
4252 | subtarget, normalizep != -1); | |
4253 | ||
4254 | if (mode != target_mode) | |
c2ec26b8 | 4255 | op0 = convert_modes (target_mode, mode, op0, 0); |
44037a66 TG |
4256 | |
4257 | return op0; | |
4258 | } | |
4259 | ||
4260 | if (icode != CODE_FOR_nothing) | |
4261 | { | |
a995e389 RH |
4262 | insn_operand_predicate_fn pred; |
4263 | ||
44037a66 TG |
4264 | /* We think we may be able to do this with a scc insn. Emit the |
4265 | comparison and then the scc insn. | |
4266 | ||
4267 | compare_from_rtx may call emit_queue, which would be deleted below | |
3bdf5848 BS |
4268 | if the scc insn fails. So call it ourselves before setting LAST. |
4269 | Likewise for do_pending_stack_adjust. */ | |
44037a66 TG |
4270 | |
4271 | emit_queue (); | |
3bdf5848 | 4272 | do_pending_stack_adjust (); |
44037a66 TG |
4273 | last = get_last_insn (); |
4274 | ||
b1ec3c92 CH |
4275 | comparison |
4276 | = compare_from_rtx (op0, op1, code, unsignedp, mode, NULL_RTX, 0); | |
44037a66 TG |
4277 | if (GET_CODE (comparison) == CONST_INT) |
4278 | return (comparison == const0_rtx ? const0_rtx | |
4279 | : normalizep == 1 ? const1_rtx | |
4280 | : normalizep == -1 ? constm1_rtx | |
4281 | : const_true_rtx); | |
4282 | ||
c2615a67 RK |
4283 | /* If the code of COMPARISON doesn't match CODE, something is |
4284 | wrong; we can no longer be sure that we have the operation. | |
4285 | We could handle this case, but it should not happen. */ | |
4286 | ||
4287 | if (GET_CODE (comparison) != code) | |
4288 | abort (); | |
8deb7047 | 4289 | |
44037a66 | 4290 | /* Get a reference to the target in the proper mode for this insn. */ |
a995e389 | 4291 | compare_mode = insn_data[(int) icode].operand[0].mode; |
44037a66 | 4292 | subtarget = target; |
a995e389 | 4293 | pred = insn_data[(int) icode].operand[0].predicate; |
44037a66 | 4294 | if (preserve_subexpressions_p () |
a995e389 | 4295 | || ! (*pred) (subtarget, compare_mode)) |
44037a66 TG |
4296 | subtarget = gen_reg_rtx (compare_mode); |
4297 | ||
4298 | pattern = GEN_FCN (icode) (subtarget); | |
4299 | if (pattern) | |
4300 | { | |
4301 | emit_insn (pattern); | |
4302 | ||
4303 | /* If we are converting to a wider mode, first convert to | |
4304 | TARGET_MODE, then normalize. This produces better combining | |
4305 | opportunities on machines that have a SIGN_EXTRACT when we are | |
4306 | testing a single bit. This mostly benefits the 68k. | |
4307 | ||
4308 | If STORE_FLAG_VALUE does not have the sign bit set when | |
4309 | interpreted in COMPARE_MODE, we can do this conversion as | |
4310 | unsigned, which is usually more efficient. */ | |
4311 | if (GET_MODE_SIZE (target_mode) > GET_MODE_SIZE (compare_mode)) | |
4312 | { | |
4313 | convert_move (target, subtarget, | |
4314 | (GET_MODE_BITSIZE (compare_mode) | |
b1ec3c92 | 4315 | <= HOST_BITS_PER_WIDE_INT) |
44037a66 | 4316 | && 0 == (STORE_FLAG_VALUE |
b1ec3c92 CH |
4317 | & ((HOST_WIDE_INT) 1 |
4318 | << (GET_MODE_BITSIZE (compare_mode) -1)))); | |
44037a66 TG |
4319 | op0 = target; |
4320 | compare_mode = target_mode; | |
4321 | } | |
4322 | else | |
4323 | op0 = subtarget; | |
4324 | ||
4b980e20 RK |
4325 | /* If we want to keep subexpressions around, don't reuse our |
4326 | last target. */ | |
4327 | ||
4328 | if (preserve_subexpressions_p ()) | |
4329 | subtarget = 0; | |
4330 | ||
44037a66 TG |
4331 | /* Now normalize to the proper value in COMPARE_MODE. Sometimes |
4332 | we don't have to do anything. */ | |
4333 | if (normalizep == 0 || normalizep == STORE_FLAG_VALUE) | |
4334 | ; | |
c5c76735 JL |
4335 | /* STORE_FLAG_VALUE might be the most negative number, so write |
4336 | the comparison this way to avoid a compiler-time warning. */ | |
4337 | else if (- normalizep == STORE_FLAG_VALUE) | |
44037a66 TG |
4338 | op0 = expand_unop (compare_mode, neg_optab, op0, subtarget, 0); |
4339 | ||
4340 | /* We don't want to use STORE_FLAG_VALUE < 0 below since this | |
4341 | makes it hard to use a value of just the sign bit due to | |
4342 | ANSI integer constant typing rules. */ | |
b1ec3c92 | 4343 | else if (GET_MODE_BITSIZE (compare_mode) <= HOST_BITS_PER_WIDE_INT |
44037a66 | 4344 | && (STORE_FLAG_VALUE |
b1ec3c92 CH |
4345 | & ((HOST_WIDE_INT) 1 |
4346 | << (GET_MODE_BITSIZE (compare_mode) - 1)))) | |
44037a66 TG |
4347 | op0 = expand_shift (RSHIFT_EXPR, compare_mode, op0, |
4348 | size_int (GET_MODE_BITSIZE (compare_mode) - 1), | |
4349 | subtarget, normalizep == 1); | |
4350 | else if (STORE_FLAG_VALUE & 1) | |
4351 | { | |
4352 | op0 = expand_and (op0, const1_rtx, subtarget); | |
4353 | if (normalizep == -1) | |
4354 | op0 = expand_unop (compare_mode, neg_optab, op0, op0, 0); | |
4355 | } | |
4356 | else | |
4357 | abort (); | |
4358 | ||
4359 | /* If we were converting to a smaller mode, do the | |
4360 | conversion now. */ | |
4361 | if (target_mode != compare_mode) | |
4362 | { | |
522ae84c | 4363 | convert_move (target, op0, 0); |
44037a66 TG |
4364 | return target; |
4365 | } | |
4366 | else | |
4367 | return op0; | |
4368 | } | |
4369 | } | |
4370 | ||
db2f8a07 | 4371 | delete_insns_since (last); |
44037a66 | 4372 | |
91e66235 MM |
4373 | /* If expensive optimizations, use different pseudo registers for each |
4374 | insn, instead of reusing the same pseudo. This leads to better CSE, | |
4375 | but slows down the compiler, since there are more pseudos */ | |
4376 | subtarget = (!flag_expensive_optimizations | |
4377 | && (target_mode == mode)) ? target : NULL_RTX; | |
44037a66 TG |
4378 | |
4379 | /* If we reached here, we can't do this with a scc insn. However, there | |
4380 | are some comparisons that can be done directly. For example, if | |
4381 | this is an equality comparison of integers, we can try to exclusive-or | |
4382 | (or subtract) the two operands and use a recursive call to try the | |
4383 | comparison with zero. Don't do any of these cases if branches are | |
4384 | very cheap. */ | |
4385 | ||
c8c1bde3 | 4386 | if (BRANCH_COST > 0 |
44037a66 TG |
4387 | && GET_MODE_CLASS (mode) == MODE_INT && (code == EQ || code == NE) |
4388 | && op1 != const0_rtx) | |
4389 | { | |
4390 | tem = expand_binop (mode, xor_optab, op0, op1, subtarget, 1, | |
4391 | OPTAB_WIDEN); | |
4392 | ||
4393 | if (tem == 0) | |
4394 | tem = expand_binop (mode, sub_optab, op0, op1, subtarget, 1, | |
4395 | OPTAB_WIDEN); | |
4396 | if (tem != 0) | |
4397 | tem = emit_store_flag (target, code, tem, const0_rtx, | |
4398 | mode, unsignedp, normalizep); | |
4399 | if (tem == 0) | |
4400 | delete_insns_since (last); | |
4401 | return tem; | |
4402 | } | |
4403 | ||
4404 | /* Some other cases we can do are EQ, NE, LE, and GT comparisons with | |
4405 | the constant zero. Reject all other comparisons at this point. Only | |
4406 | do LE and GT if branches are expensive since they are expensive on | |
4407 | 2-operand machines. */ | |
4408 | ||
4409 | if (BRANCH_COST == 0 | |
4410 | || GET_MODE_CLASS (mode) != MODE_INT || op1 != const0_rtx | |
4411 | || (code != EQ && code != NE | |
4412 | && (BRANCH_COST <= 1 || (code != LE && code != GT)))) | |
4413 | return 0; | |
4414 | ||
4415 | /* See what we need to return. We can only return a 1, -1, or the | |
4416 | sign bit. */ | |
4417 | ||
4418 | if (normalizep == 0) | |
4419 | { | |
4420 | if (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1) | |
4421 | normalizep = STORE_FLAG_VALUE; | |
4422 | ||
b1ec3c92 | 4423 | else if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT |
12dd565f | 4424 | && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode)) |
c84e2712 | 4425 | == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))) |
44037a66 TG |
4426 | ; |
4427 | else | |
4428 | return 0; | |
4429 | } | |
4430 | ||
4431 | /* Try to put the result of the comparison in the sign bit. Assume we can't | |
4432 | do the necessary operation below. */ | |
4433 | ||
4434 | tem = 0; | |
4435 | ||
4436 | /* To see if A <= 0, compute (A | (A - 1)). A <= 0 iff that result has | |
4437 | the sign bit set. */ | |
4438 | ||
4439 | if (code == LE) | |
4440 | { | |
4441 | /* This is destructive, so SUBTARGET can't be OP0. */ | |
4442 | if (rtx_equal_p (subtarget, op0)) | |
4443 | subtarget = 0; | |
4444 | ||
4445 | tem = expand_binop (mode, sub_optab, op0, const1_rtx, subtarget, 0, | |
4446 | OPTAB_WIDEN); | |
4447 | if (tem) | |
4448 | tem = expand_binop (mode, ior_optab, op0, tem, subtarget, 0, | |
4449 | OPTAB_WIDEN); | |
4450 | } | |
4451 | ||
4452 | /* To see if A > 0, compute (((signed) A) << BITS) - A, where BITS is the | |
4453 | number of bits in the mode of OP0, minus one. */ | |
4454 | ||
4455 | if (code == GT) | |
4456 | { | |
4457 | if (rtx_equal_p (subtarget, op0)) | |
4458 | subtarget = 0; | |
4459 | ||
4460 | tem = expand_shift (RSHIFT_EXPR, mode, op0, | |
4461 | size_int (GET_MODE_BITSIZE (mode) - 1), | |
4462 | subtarget, 0); | |
4463 | tem = expand_binop (mode, sub_optab, tem, op0, subtarget, 0, | |
4464 | OPTAB_WIDEN); | |
4465 | } | |
4466 | ||
4467 | if (code == EQ || code == NE) | |
4468 | { | |
4469 | /* For EQ or NE, one way to do the comparison is to apply an operation | |
4470 | that converts the operand into a positive number if it is non-zero | |
4471 | or zero if it was originally zero. Then, for EQ, we subtract 1 and | |
4472 | for NE we negate. This puts the result in the sign bit. Then we | |
4473 | normalize with a shift, if needed. | |
4474 | ||
4475 | Two operations that can do the above actions are ABS and FFS, so try | |
4476 | them. If that doesn't work, and MODE is smaller than a full word, | |
36d747f6 | 4477 | we can use zero-extension to the wider mode (an unsigned conversion) |
44037a66 TG |
4478 | as the operation. */ |
4479 | ||
4480 | if (abs_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing) | |
4481 | tem = expand_unop (mode, abs_optab, op0, subtarget, 1); | |
4482 | else if (ffs_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing) | |
4483 | tem = expand_unop (mode, ffs_optab, op0, subtarget, 1); | |
4484 | else if (GET_MODE_SIZE (mode) < UNITS_PER_WORD) | |
4485 | { | |
b3d4e1b2 | 4486 | op0 = protect_from_queue (op0, 0); |
c2ec26b8 | 4487 | tem = convert_modes (word_mode, mode, op0, 1); |
81722fa9 | 4488 | mode = word_mode; |
44037a66 TG |
4489 | } |
4490 | ||
4491 | if (tem != 0) | |
4492 | { | |
4493 | if (code == EQ) | |
4494 | tem = expand_binop (mode, sub_optab, tem, const1_rtx, subtarget, | |
4495 | 0, OPTAB_WIDEN); | |
4496 | else | |
4497 | tem = expand_unop (mode, neg_optab, tem, subtarget, 0); | |
4498 | } | |
4499 | ||
4500 | /* If we couldn't do it that way, for NE we can "or" the two's complement | |
4501 | of the value with itself. For EQ, we take the one's complement of | |
4502 | that "or", which is an extra insn, so we only handle EQ if branches | |
4503 | are expensive. */ | |
4504 | ||
4505 | if (tem == 0 && (code == NE || BRANCH_COST > 1)) | |
4506 | { | |
36d747f6 RS |
4507 | if (rtx_equal_p (subtarget, op0)) |
4508 | subtarget = 0; | |
4509 | ||
44037a66 TG |
4510 | tem = expand_unop (mode, neg_optab, op0, subtarget, 0); |
4511 | tem = expand_binop (mode, ior_optab, tem, op0, subtarget, 0, | |
4512 | OPTAB_WIDEN); | |
4513 | ||
4514 | if (tem && code == EQ) | |
4515 | tem = expand_unop (mode, one_cmpl_optab, tem, subtarget, 0); | |
4516 | } | |
4517 | } | |
4518 | ||
4519 | if (tem && normalizep) | |
4520 | tem = expand_shift (RSHIFT_EXPR, mode, tem, | |
4521 | size_int (GET_MODE_BITSIZE (mode) - 1), | |
91e66235 | 4522 | subtarget, normalizep == 1); |
44037a66 | 4523 | |
91e66235 | 4524 | if (tem) |
44037a66 | 4525 | { |
91e66235 MM |
4526 | if (GET_MODE (tem) != target_mode) |
4527 | { | |
4528 | convert_move (target, tem, 0); | |
4529 | tem = target; | |
4530 | } | |
4531 | else if (!subtarget) | |
4532 | { | |
4533 | emit_move_insn (target, tem); | |
4534 | tem = target; | |
4535 | } | |
44037a66 | 4536 | } |
91e66235 | 4537 | else |
44037a66 TG |
4538 | delete_insns_since (last); |
4539 | ||
4540 | return tem; | |
4541 | } | |
04a8ee2f TG |
4542 | |
4543 | /* Like emit_store_flag, but always succeeds. */ | |
4544 | ||
4545 | rtx | |
4546 | emit_store_flag_force (target, code, op0, op1, mode, unsignedp, normalizep) | |
4547 | rtx target; | |
4548 | enum rtx_code code; | |
4549 | rtx op0, op1; | |
4550 | enum machine_mode mode; | |
4551 | int unsignedp; | |
4552 | int normalizep; | |
4553 | { | |
4554 | rtx tem, label; | |
4555 | ||
4556 | /* First see if emit_store_flag can do the job. */ | |
4557 | tem = emit_store_flag (target, code, op0, op1, mode, unsignedp, normalizep); | |
4558 | if (tem != 0) | |
4559 | return tem; | |
4560 | ||
4561 | if (normalizep == 0) | |
4562 | normalizep = 1; | |
4563 | ||
4564 | /* If this failed, we have to do this with set/compare/jump/set code. */ | |
4565 | ||
4566 | if (GET_CODE (target) != REG | |
4567 | || reg_mentioned_p (target, op0) || reg_mentioned_p (target, op1)) | |
4568 | target = gen_reg_rtx (GET_MODE (target)); | |
4569 | ||
e4565aff | 4570 | emit_move_insn (target, const1_rtx); |
04a8ee2f | 4571 | label = gen_label_rtx (); |
b30f05db BS |
4572 | do_compare_rtx_and_jump (op0, op1, code, unsignedp, mode, NULL_RTX, 0, |
4573 | NULL_RTX, label); | |
04a8ee2f | 4574 | |
e4565aff | 4575 | emit_move_insn (target, const0_rtx); |
44037a66 TG |
4576 | emit_label (label); |
4577 | ||
4578 | return target; | |
4579 | } | |
f5963e61 JL |
4580 | \f |
4581 | /* Perform possibly multi-word comparison and conditional jump to LABEL | |
4582 | if ARG1 OP ARG2 true where ARG1 and ARG2 are of mode MODE | |
4583 | ||
4584 | The algorithm is based on the code in expr.c:do_jump. | |
4585 | ||
4586 | Note that this does not perform a general comparison. Only variants | |
4587 | generated within expmed.c are correctly handled, others abort (but could | |
4588 | be handled if needed). */ | |
4589 | ||
4590 | static void | |
4591 | do_cmp_and_jump (arg1, arg2, op, mode, label) | |
4592 | rtx arg1, arg2, label; | |
b30f05db BS |
4593 | enum rtx_code op; |
4594 | enum machine_mode mode; | |
f5963e61 JL |
4595 | { |
4596 | /* If this mode is an integer too wide to compare properly, | |
4597 | compare word by word. Rely on cse to optimize constant cases. */ | |
4598 | ||
1eb8759b RH |
4599 | if (GET_MODE_CLASS (mode) == MODE_INT |
4600 | && ! can_compare_p (op, mode, ccp_jump)) | |
f5963e61 JL |
4601 | { |
4602 | rtx label2 = gen_label_rtx (); | |
4603 | ||
4604 | switch (op) | |
4605 | { | |
4606 | case LTU: | |
4607 | do_jump_by_parts_greater_rtx (mode, 1, arg2, arg1, label2, label); | |
4608 | break; | |
4609 | ||
4610 | case LEU: | |
4611 | do_jump_by_parts_greater_rtx (mode, 1, arg1, arg2, label, label2); | |
4612 | break; | |
4613 | ||
4614 | case LT: | |
4615 | do_jump_by_parts_greater_rtx (mode, 0, arg2, arg1, label2, label); | |
4616 | break; | |
4617 | ||
4618 | case GT: | |
4619 | do_jump_by_parts_greater_rtx (mode, 0, arg1, arg2, label2, label); | |
4620 | break; | |
4621 | ||
4622 | case GE: | |
4623 | do_jump_by_parts_greater_rtx (mode, 0, arg2, arg1, label, label2); | |
4624 | break; | |
4625 | ||
4626 | /* do_jump_by_parts_equality_rtx compares with zero. Luckily | |
4627 | that's the only equality operations we do */ | |
4628 | case EQ: | |
4629 | if (arg2 != const0_rtx || mode != GET_MODE(arg1)) | |
4630 | abort(); | |
4631 | do_jump_by_parts_equality_rtx (arg1, label2, label); | |
4632 | break; | |
4633 | ||
4634 | case NE: | |
4635 | if (arg2 != const0_rtx || mode != GET_MODE(arg1)) | |
4636 | abort(); | |
4637 | do_jump_by_parts_equality_rtx (arg1, label, label2); | |
4638 | break; | |
4639 | ||
4640 | default: | |
4641 | abort(); | |
4642 | } | |
4643 | ||
4644 | emit_label (label2); | |
4645 | } | |
4646 | else | |
4647 | { | |
c5d5d461 | 4648 | emit_cmp_and_jump_insns (arg1, arg2, op, NULL_RTX, mode, 0, 0, label); |
f5963e61 JL |
4649 | } |
4650 | } |