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44037a66 TG |
1 | /* Medium-level subroutines: convert bit-field store and extract |
2 | and shifts, multiplies and divides to rtl instructions. | |
ef58a523 | 3 | Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998, |
c4f2c499 | 4 | 1999, 2000, 2001, 2002 Free Software Foundation, Inc. |
44037a66 | 5 | |
1322177d | 6 | This file is part of GCC. |
44037a66 | 7 | |
1322177d LB |
8 | GCC is free software; you can redistribute it and/or modify it under |
9 | the terms of the GNU General Public License as published by the Free | |
10 | Software Foundation; either version 2, or (at your option) any later | |
11 | version. | |
44037a66 | 12 | |
1322177d LB |
13 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY |
14 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
15 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
16 | for more details. | |
44037a66 TG |
17 | |
18 | You should have received a copy of the GNU General Public License | |
1322177d LB |
19 | along with GCC; see the file COPYING. If not, write to the Free |
20 | Software Foundation, 59 Temple Place - Suite 330, Boston, MA | |
21 | 02111-1307, USA. */ | |
44037a66 TG |
22 | |
23 | ||
24 | #include "config.h" | |
670ee920 | 25 | #include "system.h" |
01198c2f | 26 | #include "toplev.h" |
44037a66 TG |
27 | #include "rtl.h" |
28 | #include "tree.h" | |
6baf1cc8 | 29 | #include "tm_p.h" |
44037a66 | 30 | #include "flags.h" |
44037a66 TG |
31 | #include "insn-config.h" |
32 | #include "expr.h" | |
e78d8e51 | 33 | #include "optabs.h" |
44037a66 TG |
34 | #include "real.h" |
35 | #include "recog.h" | |
36 | ||
770ae6cc RK |
37 | static void store_fixed_bit_field PARAMS ((rtx, unsigned HOST_WIDE_INT, |
38 | unsigned HOST_WIDE_INT, | |
04050c69 | 39 | unsigned HOST_WIDE_INT, rtx)); |
770ae6cc | 40 | static void store_split_bit_field PARAMS ((rtx, unsigned HOST_WIDE_INT, |
04050c69 | 41 | unsigned HOST_WIDE_INT, rtx)); |
770ae6cc RK |
42 | static rtx extract_fixed_bit_field PARAMS ((enum machine_mode, rtx, |
43 | unsigned HOST_WIDE_INT, | |
44 | unsigned HOST_WIDE_INT, | |
45 | unsigned HOST_WIDE_INT, | |
04050c69 | 46 | rtx, int)); |
711d877c KG |
47 | static rtx mask_rtx PARAMS ((enum machine_mode, int, |
48 | int, int)); | |
49 | static rtx lshift_value PARAMS ((enum machine_mode, rtx, | |
50 | int, int)); | |
770ae6cc | 51 | static rtx extract_split_bit_field PARAMS ((rtx, unsigned HOST_WIDE_INT, |
04050c69 | 52 | unsigned HOST_WIDE_INT, int)); |
711d877c KG |
53 | static void do_cmp_and_jump PARAMS ((rtx, rtx, enum rtx_code, |
54 | enum machine_mode, rtx)); | |
44037a66 | 55 | |
44037a66 TG |
56 | /* Non-zero means divides or modulus operations are relatively cheap for |
57 | powers of two, so don't use branches; emit the operation instead. | |
58 | Usually, this will mean that the MD file will emit non-branch | |
59 | sequences. */ | |
60 | ||
61 | static int sdiv_pow2_cheap, smod_pow2_cheap; | |
62 | ||
c7e33f89 | 63 | #ifndef SLOW_UNALIGNED_ACCESS |
e1565e65 | 64 | #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) STRICT_ALIGNMENT |
c7e33f89 RS |
65 | #endif |
66 | ||
e49a094d RS |
67 | /* For compilers that support multiple targets with different word sizes, |
68 | MAX_BITS_PER_WORD contains the biggest value of BITS_PER_WORD. An example | |
69 | is the H8/300(H) compiler. */ | |
70 | ||
71 | #ifndef MAX_BITS_PER_WORD | |
72 | #define MAX_BITS_PER_WORD BITS_PER_WORD | |
73 | #endif | |
74 | ||
d523b40e RH |
75 | /* Reduce conditional compilation elsewhere. */ |
76 | #ifndef HAVE_insv | |
a242b083 | 77 | #define HAVE_insv 0 |
d523b40e RH |
78 | #define CODE_FOR_insv CODE_FOR_nothing |
79 | #define gen_insv(a,b,c,d) NULL_RTX | |
80 | #endif | |
81 | #ifndef HAVE_extv | |
a242b083 | 82 | #define HAVE_extv 0 |
d523b40e RH |
83 | #define CODE_FOR_extv CODE_FOR_nothing |
84 | #define gen_extv(a,b,c,d) NULL_RTX | |
85 | #endif | |
86 | #ifndef HAVE_extzv | |
a242b083 | 87 | #define HAVE_extzv 0 |
d523b40e RH |
88 | #define CODE_FOR_extzv CODE_FOR_nothing |
89 | #define gen_extzv(a,b,c,d) NULL_RTX | |
90 | #endif | |
91 | ||
c5c76735 JL |
92 | /* Cost of various pieces of RTL. Note that some of these are indexed by |
93 | shift count and some by mode. */ | |
819126a6 | 94 | static int add_cost, negate_cost, zero_cost; |
e49a094d RS |
95 | static int shift_cost[MAX_BITS_PER_WORD]; |
96 | static int shiftadd_cost[MAX_BITS_PER_WORD]; | |
97 | static int shiftsub_cost[MAX_BITS_PER_WORD]; | |
71af73bb TG |
98 | static int mul_cost[NUM_MACHINE_MODES]; |
99 | static int div_cost[NUM_MACHINE_MODES]; | |
100 | static int mul_widen_cost[NUM_MACHINE_MODES]; | |
101 | static int mul_highpart_cost[NUM_MACHINE_MODES]; | |
44037a66 | 102 | |
44037a66 TG |
103 | void |
104 | init_expmed () | |
105 | { | |
44037a66 TG |
106 | /* This is "some random pseudo register" for purposes of calling recog |
107 | to see what insns exist. */ | |
38a448ca | 108 | rtx reg = gen_rtx_REG (word_mode, 10000); |
b385aeda | 109 | rtx shift_insn, shiftadd_insn, shiftsub_insn; |
b1ec3c92 | 110 | int dummy; |
7963ac37 | 111 | int m; |
71af73bb | 112 | enum machine_mode mode, wider_mode; |
44037a66 | 113 | |
b385aeda RK |
114 | start_sequence (); |
115 | ||
c5c76735 | 116 | reg = gen_rtx_REG (word_mode, 10000); |
9ec36da5 | 117 | |
172a1cb0 | 118 | zero_cost = rtx_cost (const0_rtx, 0); |
38a448ca RH |
119 | add_cost = rtx_cost (gen_rtx_PLUS (word_mode, reg, reg), SET); |
120 | ||
121 | shift_insn = emit_insn (gen_rtx_SET (VOIDmode, reg, | |
122 | gen_rtx_ASHIFT (word_mode, reg, | |
123 | const0_rtx))); | |
124 | ||
125 | shiftadd_insn | |
126 | = emit_insn (gen_rtx_SET (VOIDmode, reg, | |
127 | gen_rtx_PLUS (word_mode, | |
128 | gen_rtx_MULT (word_mode, | |
129 | reg, const0_rtx), | |
130 | reg))); | |
131 | ||
132 | shiftsub_insn | |
133 | = emit_insn (gen_rtx_SET (VOIDmode, reg, | |
134 | gen_rtx_MINUS (word_mode, | |
135 | gen_rtx_MULT (word_mode, | |
136 | reg, const0_rtx), | |
137 | reg))); | |
7963ac37 RK |
138 | |
139 | init_recog (); | |
b385aeda RK |
140 | |
141 | shift_cost[0] = 0; | |
142 | shiftadd_cost[0] = shiftsub_cost[0] = add_cost; | |
143 | ||
55a6ba9f | 144 | for (m = 1; m < MAX_BITS_PER_WORD; m++) |
7963ac37 RK |
145 | { |
146 | shift_cost[m] = shiftadd_cost[m] = shiftsub_cost[m] = 32000; | |
b385aeda RK |
147 | |
148 | XEXP (SET_SRC (PATTERN (shift_insn)), 1) = GEN_INT (m); | |
149 | if (recog (PATTERN (shift_insn), shift_insn, &dummy) >= 0) | |
150 | shift_cost[m] = rtx_cost (SET_SRC (PATTERN (shift_insn)), SET); | |
151 | ||
152 | XEXP (XEXP (SET_SRC (PATTERN (shiftadd_insn)), 0), 1) | |
153 | = GEN_INT ((HOST_WIDE_INT) 1 << m); | |
154 | if (recog (PATTERN (shiftadd_insn), shiftadd_insn, &dummy) >= 0) | |
dac57de0 | 155 | shiftadd_cost[m] = rtx_cost (SET_SRC (PATTERN (shiftadd_insn)), SET); |
b385aeda RK |
156 | |
157 | XEXP (XEXP (SET_SRC (PATTERN (shiftsub_insn)), 0), 1) | |
158 | = GEN_INT ((HOST_WIDE_INT) 1 << m); | |
159 | if (recog (PATTERN (shiftsub_insn), shiftsub_insn, &dummy) >= 0) | |
dac57de0 | 160 | shiftsub_cost[m] = rtx_cost (SET_SRC (PATTERN (shiftsub_insn)), SET); |
7963ac37 RK |
161 | } |
162 | ||
38a448ca | 163 | negate_cost = rtx_cost (gen_rtx_NEG (word_mode, reg), SET); |
44037a66 | 164 | |
44037a66 | 165 | sdiv_pow2_cheap |
38a448ca | 166 | = (rtx_cost (gen_rtx_DIV (word_mode, reg, GEN_INT (32)), SET) |
b385aeda | 167 | <= 2 * add_cost); |
44037a66 | 168 | smod_pow2_cheap |
38a448ca | 169 | = (rtx_cost (gen_rtx_MOD (word_mode, reg, GEN_INT (32)), SET) |
b385aeda | 170 | <= 2 * add_cost); |
44037a66 | 171 | |
71af73bb TG |
172 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT); |
173 | mode != VOIDmode; | |
174 | mode = GET_MODE_WIDER_MODE (mode)) | |
175 | { | |
38a448ca RH |
176 | reg = gen_rtx_REG (mode, 10000); |
177 | div_cost[(int) mode] = rtx_cost (gen_rtx_UDIV (mode, reg, reg), SET); | |
178 | mul_cost[(int) mode] = rtx_cost (gen_rtx_MULT (mode, reg, reg), SET); | |
71af73bb TG |
179 | wider_mode = GET_MODE_WIDER_MODE (mode); |
180 | if (wider_mode != VOIDmode) | |
181 | { | |
182 | mul_widen_cost[(int) wider_mode] | |
38a448ca RH |
183 | = rtx_cost (gen_rtx_MULT (wider_mode, |
184 | gen_rtx_ZERO_EXTEND (wider_mode, reg), | |
185 | gen_rtx_ZERO_EXTEND (wider_mode, reg)), | |
71af73bb TG |
186 | SET); |
187 | mul_highpart_cost[(int) mode] | |
38a448ca RH |
188 | = rtx_cost (gen_rtx_TRUNCATE |
189 | (mode, | |
c5c76735 JL |
190 | gen_rtx_LSHIFTRT (wider_mode, |
191 | gen_rtx_MULT (wider_mode, | |
192 | gen_rtx_ZERO_EXTEND | |
193 | (wider_mode, reg), | |
194 | gen_rtx_ZERO_EXTEND | |
195 | (wider_mode, reg)), | |
196 | GEN_INT (GET_MODE_BITSIZE (mode)))), | |
71af73bb TG |
197 | SET); |
198 | } | |
199 | } | |
200 | ||
b385aeda | 201 | end_sequence (); |
44037a66 TG |
202 | } |
203 | ||
204 | /* Return an rtx representing minus the value of X. | |
205 | MODE is the intended mode of the result, | |
206 | useful if X is a CONST_INT. */ | |
207 | ||
208 | rtx | |
209 | negate_rtx (mode, x) | |
210 | enum machine_mode mode; | |
211 | rtx x; | |
212 | { | |
a39a7484 RK |
213 | rtx result = simplify_unary_operation (NEG, mode, x, mode); |
214 | ||
fdb5537f | 215 | if (result == 0) |
a39a7484 RK |
216 | result = expand_unop (mode, neg_optab, x, NULL_RTX, 0); |
217 | ||
218 | return result; | |
44037a66 | 219 | } |
da920570 ZW |
220 | |
221 | /* Report on the availability of insv/extv/extzv and the desired mode | |
222 | of each of their operands. Returns MAX_MACHINE_MODE if HAVE_foo | |
223 | is false; else the mode of the specified operand. If OPNO is -1, | |
224 | all the caller cares about is whether the insn is available. */ | |
225 | enum machine_mode | |
226 | mode_for_extraction (pattern, opno) | |
227 | enum extraction_pattern pattern; | |
228 | int opno; | |
229 | { | |
230 | const struct insn_data *data; | |
231 | ||
232 | switch (pattern) | |
233 | { | |
234 | case EP_insv: | |
da920570 ZW |
235 | if (HAVE_insv) |
236 | { | |
237 | data = &insn_data[CODE_FOR_insv]; | |
238 | break; | |
239 | } | |
da920570 ZW |
240 | return MAX_MACHINE_MODE; |
241 | ||
242 | case EP_extv: | |
da920570 ZW |
243 | if (HAVE_extv) |
244 | { | |
245 | data = &insn_data[CODE_FOR_extv]; | |
246 | break; | |
247 | } | |
da920570 ZW |
248 | return MAX_MACHINE_MODE; |
249 | ||
250 | case EP_extzv: | |
da920570 ZW |
251 | if (HAVE_extzv) |
252 | { | |
253 | data = &insn_data[CODE_FOR_extzv]; | |
254 | break; | |
255 | } | |
da920570 | 256 | return MAX_MACHINE_MODE; |
a242b083 ZW |
257 | |
258 | default: | |
259 | abort (); | |
da920570 ZW |
260 | } |
261 | ||
262 | if (opno == -1) | |
263 | return VOIDmode; | |
264 | ||
265 | /* Everyone who uses this function used to follow it with | |
266 | if (result == VOIDmode) result = word_mode; */ | |
267 | if (data->operand[opno].mode == VOIDmode) | |
268 | return word_mode; | |
269 | return data->operand[opno].mode; | |
270 | } | |
271 | ||
44037a66 TG |
272 | \f |
273 | /* Generate code to store value from rtx VALUE | |
274 | into a bit-field within structure STR_RTX | |
275 | containing BITSIZE bits starting at bit BITNUM. | |
276 | FIELDMODE is the machine-mode of the FIELD_DECL node for this field. | |
0e805f81 | 277 | ALIGN is the alignment that STR_RTX is known to have. |
44037a66 TG |
278 | TOTAL_SIZE is the size of the structure in bytes, or -1 if varying. */ |
279 | ||
280 | /* ??? Note that there are two different ideas here for how | |
281 | to determine the size to count bits within, for a register. | |
282 | One is BITS_PER_WORD, and the other is the size of operand 3 | |
0d8e55d8 JL |
283 | of the insv pattern. |
284 | ||
285 | If operand 3 of the insv pattern is VOIDmode, then we will use BITS_PER_WORD | |
286 | else, we use the mode of operand 3. */ | |
44037a66 TG |
287 | |
288 | rtx | |
04050c69 | 289 | store_bit_field (str_rtx, bitsize, bitnum, fieldmode, value, total_size) |
44037a66 | 290 | rtx str_rtx; |
770ae6cc RK |
291 | unsigned HOST_WIDE_INT bitsize; |
292 | unsigned HOST_WIDE_INT bitnum; | |
44037a66 TG |
293 | enum machine_mode fieldmode; |
294 | rtx value; | |
770ae6cc | 295 | HOST_WIDE_INT total_size; |
44037a66 | 296 | { |
770ae6cc RK |
297 | unsigned int unit |
298 | = (GET_CODE (str_rtx) == MEM) ? BITS_PER_UNIT : BITS_PER_WORD; | |
299 | unsigned HOST_WIDE_INT offset = bitnum / unit; | |
300 | unsigned HOST_WIDE_INT bitpos = bitnum % unit; | |
b3694847 | 301 | rtx op0 = str_rtx; |
da920570 | 302 | |
a242b083 | 303 | enum machine_mode op_mode = mode_for_extraction (EP_insv, 3); |
44037a66 | 304 | |
44037a66 TG |
305 | /* Discount the part of the structure before the desired byte. |
306 | We need to know how many bytes are safe to reference after it. */ | |
307 | if (total_size >= 0) | |
308 | total_size -= (bitpos / BIGGEST_ALIGNMENT | |
309 | * (BIGGEST_ALIGNMENT / BITS_PER_UNIT)); | |
310 | ||
311 | while (GET_CODE (op0) == SUBREG) | |
312 | { | |
313 | /* The following line once was done only if WORDS_BIG_ENDIAN, | |
314 | but I think that is a mistake. WORDS_BIG_ENDIAN is | |
315 | meaningful at a much higher level; when structures are copied | |
316 | between memory and regs, the higher-numbered regs | |
317 | always get higher addresses. */ | |
ddef6bc7 | 318 | offset += (SUBREG_BYTE (op0) / UNITS_PER_WORD); |
44037a66 TG |
319 | /* We used to adjust BITPOS here, but now we do the whole adjustment |
320 | right after the loop. */ | |
321 | op0 = SUBREG_REG (op0); | |
322 | } | |
323 | ||
44037a66 TG |
324 | value = protect_from_queue (value, 0); |
325 | ||
326 | if (flag_force_mem) | |
327 | value = force_not_mem (value); | |
328 | ||
308ecea0 RH |
329 | /* If the target is a register, overwriting the entire object, or storing |
330 | a full-word or multi-word field can be done with just a SUBREG. | |
331 | ||
332 | If the target is memory, storing any naturally aligned field can be | |
333 | done with a simple store. For targets that support fast unaligned | |
334 | memory, any naturally sized, unit aligned field can be done directly. */ | |
335 | ||
57bfa49a | 336 | if (bitpos == 0 |
f21bdd05 | 337 | && bitsize == GET_MODE_BITSIZE (fieldmode) |
ea9ea008 RH |
338 | && (GET_CODE (op0) != MEM |
339 | ? (GET_MODE_SIZE (fieldmode) >= UNITS_PER_WORD | |
340 | || GET_MODE_SIZE (GET_MODE (op0)) == GET_MODE_SIZE (fieldmode)) | |
04050c69 | 341 | : (! SLOW_UNALIGNED_ACCESS (fieldmode, MEM_ALIGN (op0)) |
ea9ea008 | 342 | || (offset * BITS_PER_UNIT % bitsize == 0 |
04050c69 | 343 | && MEM_ALIGN (op0) % GET_MODE_BITSIZE (fieldmode) == 0)))) |
44037a66 | 344 | { |
44037a66 | 345 | if (GET_MODE (op0) != fieldmode) |
c7e33f89 | 346 | { |
d006aa54 RH |
347 | if (GET_CODE (op0) == SUBREG) |
348 | { | |
349 | if (GET_MODE (SUBREG_REG (op0)) == fieldmode | |
350 | || GET_MODE_CLASS (fieldmode) == MODE_INT | |
351 | || GET_MODE_CLASS (fieldmode) == MODE_PARTIAL_INT) | |
352 | op0 = SUBREG_REG (op0); | |
353 | else | |
354 | /* Else we've got some float mode source being extracted into | |
355 | a different float mode destination -- this combination of | |
356 | subregs results in Severe Tire Damage. */ | |
357 | abort (); | |
358 | } | |
c7e33f89 | 359 | if (GET_CODE (op0) == REG) |
ddef6bc7 JJ |
360 | op0 = gen_rtx_SUBREG (fieldmode, op0, |
361 | (bitnum % BITS_PER_WORD) / BITS_PER_UNIT | |
362 | + (offset * UNITS_PER_WORD)); | |
c7e33f89 | 363 | else |
f4ef873c | 364 | op0 = adjust_address (op0, fieldmode, offset); |
c7e33f89 | 365 | } |
44037a66 TG |
366 | emit_move_insn (op0, value); |
367 | return value; | |
368 | } | |
369 | ||
a8ca7756 JW |
370 | /* Make sure we are playing with integral modes. Pun with subregs |
371 | if we aren't. This must come after the entire register case above, | |
372 | since that case is valid for any mode. The following cases are only | |
373 | valid for integral modes. */ | |
374 | { | |
375 | enum machine_mode imode = int_mode_for_mode (GET_MODE (op0)); | |
376 | if (imode != GET_MODE (op0)) | |
377 | { | |
378 | if (GET_CODE (op0) == MEM) | |
f4ef873c | 379 | op0 = adjust_address (op0, imode, 0); |
a8ca7756 JW |
380 | else if (imode != BLKmode) |
381 | op0 = gen_lowpart (imode, op0); | |
382 | else | |
383 | abort (); | |
384 | } | |
385 | } | |
386 | ||
57bfa49a RZ |
387 | /* If OP0 is a register, BITPOS must count within a word. |
388 | But as we have it, it counts within whatever size OP0 now has. | |
389 | On a bigendian machine, these are not the same, so convert. */ | |
390 | if (BYTES_BIG_ENDIAN | |
391 | && GET_CODE (op0) != MEM | |
392 | && unit > GET_MODE_BITSIZE (GET_MODE (op0))) | |
393 | bitpos += unit - GET_MODE_BITSIZE (GET_MODE (op0)); | |
394 | ||
44037a66 TG |
395 | /* Storing an lsb-aligned field in a register |
396 | can be done with a movestrict instruction. */ | |
397 | ||
398 | if (GET_CODE (op0) != MEM | |
f76b9db2 | 399 | && (BYTES_BIG_ENDIAN ? bitpos + bitsize == unit : bitpos == 0) |
44037a66 | 400 | && bitsize == GET_MODE_BITSIZE (fieldmode) |
5e4900c7 JW |
401 | && (movstrict_optab->handlers[(int) fieldmode].insn_code |
402 | != CODE_FOR_nothing)) | |
44037a66 | 403 | { |
5e4900c7 JW |
404 | int icode = movstrict_optab->handlers[(int) fieldmode].insn_code; |
405 | ||
44037a66 TG |
406 | /* Get appropriate low part of the value being stored. */ |
407 | if (GET_CODE (value) == CONST_INT || GET_CODE (value) == REG) | |
408 | value = gen_lowpart (fieldmode, value); | |
409 | else if (!(GET_CODE (value) == SYMBOL_REF | |
410 | || GET_CODE (value) == LABEL_REF | |
411 | || GET_CODE (value) == CONST)) | |
412 | value = convert_to_mode (fieldmode, value, 0); | |
413 | ||
5e4900c7 JW |
414 | if (! (*insn_data[icode].operand[1].predicate) (value, fieldmode)) |
415 | value = copy_to_mode_reg (fieldmode, value); | |
416 | ||
417 | if (GET_CODE (op0) == SUBREG) | |
44037a66 | 418 | { |
5e4900c7 JW |
419 | if (GET_MODE (SUBREG_REG (op0)) == fieldmode |
420 | || GET_MODE_CLASS (fieldmode) == MODE_INT | |
421 | || GET_MODE_CLASS (fieldmode) == MODE_PARTIAL_INT) | |
422 | op0 = SUBREG_REG (op0); | |
423 | else | |
424 | /* Else we've got some float mode source being extracted into | |
425 | a different float mode destination -- this combination of | |
426 | subregs results in Severe Tire Damage. */ | |
427 | abort (); | |
428 | } | |
470032d7 | 429 | |
5e4900c7 | 430 | emit_insn (GEN_FCN (icode) |
ddef6bc7 JJ |
431 | (gen_rtx_SUBREG (fieldmode, op0, |
432 | (bitnum % BITS_PER_WORD) / BITS_PER_UNIT | |
433 | + (offset * UNITS_PER_WORD)), | |
434 | value)); | |
470032d7 | 435 | |
44037a66 TG |
436 | return value; |
437 | } | |
438 | ||
439 | /* Handle fields bigger than a word. */ | |
440 | ||
441 | if (bitsize > BITS_PER_WORD) | |
442 | { | |
443 | /* Here we transfer the words of the field | |
444 | in the order least significant first. | |
445 | This is because the most significant word is the one which may | |
ad83e87b PB |
446 | be less than full. |
447 | However, only do that if the value is not BLKmode. */ | |
448 | ||
770ae6cc RK |
449 | unsigned int backwards = WORDS_BIG_ENDIAN && fieldmode != BLKmode; |
450 | unsigned int nwords = (bitsize + (BITS_PER_WORD - 1)) / BITS_PER_WORD; | |
451 | unsigned int i; | |
44037a66 TG |
452 | |
453 | /* This is the mode we must force value to, so that there will be enough | |
454 | subwords to extract. Note that fieldmode will often (always?) be | |
455 | VOIDmode, because that is what store_field uses to indicate that this | |
456 | is a bit field, but passing VOIDmode to operand_subword_force will | |
457 | result in an abort. */ | |
df7978d9 | 458 | fieldmode = smallest_mode_for_size (nwords * BITS_PER_WORD, MODE_INT); |
44037a66 TG |
459 | |
460 | for (i = 0; i < nwords; i++) | |
461 | { | |
ad83e87b PB |
462 | /* If I is 0, use the low-order word in both field and target; |
463 | if I is 1, use the next to lowest word; and so on. */ | |
770ae6cc RK |
464 | unsigned int wordnum = (backwards ? nwords - i - 1 : i); |
465 | unsigned int bit_offset = (backwards | |
04050c69 RK |
466 | ? MAX ((int) bitsize - ((int) i + 1) |
467 | * BITS_PER_WORD, | |
468 | 0) | |
469 | : (int) i * BITS_PER_WORD); | |
770ae6cc | 470 | |
44037a66 TG |
471 | store_bit_field (op0, MIN (BITS_PER_WORD, |
472 | bitsize - i * BITS_PER_WORD), | |
473 | bitnum + bit_offset, word_mode, | |
b3487765 RS |
474 | operand_subword_force (value, wordnum, |
475 | (GET_MODE (value) == VOIDmode | |
476 | ? fieldmode | |
477 | : GET_MODE (value))), | |
04050c69 | 478 | total_size); |
44037a66 TG |
479 | } |
480 | return value; | |
481 | } | |
482 | ||
483 | /* From here on we can assume that the field to be stored in is | |
484 | a full-word (whatever type that is), since it is shorter than a word. */ | |
485 | ||
486 | /* OFFSET is the number of words or bytes (UNIT says which) | |
487 | from STR_RTX to the first word or byte containing part of the field. */ | |
488 | ||
470032d7 | 489 | if (GET_CODE (op0) != MEM) |
44037a66 TG |
490 | { |
491 | if (offset != 0 | |
492 | || GET_MODE_SIZE (GET_MODE (op0)) > UNITS_PER_WORD) | |
470032d7 RH |
493 | { |
494 | if (GET_CODE (op0) != REG) | |
7be7a07d JW |
495 | { |
496 | /* Since this is a destination (lvalue), we can't copy it to a | |
497 | pseudo. We can trivially remove a SUBREG that does not | |
498 | change the size of the operand. Such a SUBREG may have been | |
499 | added above. Otherwise, abort. */ | |
500 | if (GET_CODE (op0) == SUBREG | |
501 | && (GET_MODE_SIZE (GET_MODE (op0)) | |
502 | == GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))) | |
503 | op0 = SUBREG_REG (op0); | |
504 | else | |
505 | abort (); | |
506 | } | |
470032d7 | 507 | op0 = gen_rtx_SUBREG (mode_for_size (BITS_PER_WORD, MODE_INT, 0), |
ddef6bc7 | 508 | op0, (offset * UNITS_PER_WORD)); |
470032d7 | 509 | } |
44037a66 TG |
510 | offset = 0; |
511 | } | |
512 | else | |
04050c69 | 513 | op0 = protect_from_queue (op0, 1); |
44037a66 | 514 | |
2305bcad JW |
515 | /* If VALUE is a floating-point mode, access it as an integer of the |
516 | corresponding size. This can occur on a machine with 64 bit registers | |
517 | that uses SFmode for float. This can also occur for unaligned float | |
518 | structure fields. */ | |
519 | if (GET_MODE_CLASS (GET_MODE (value)) == MODE_FLOAT) | |
520 | { | |
521 | if (GET_CODE (value) != REG) | |
522 | value = copy_to_reg (value); | |
38a448ca | 523 | value = gen_rtx_SUBREG (word_mode, value, 0); |
2305bcad JW |
524 | } |
525 | ||
44037a66 TG |
526 | /* Now OFFSET is nonzero only if OP0 is memory |
527 | and is therefore always measured in bytes. */ | |
528 | ||
a242b083 | 529 | if (HAVE_insv |
1d269b0c | 530 | && GET_MODE (value) != BLKmode |
44037a66 TG |
531 | && !(bitsize == 1 && GET_CODE (value) == CONST_INT) |
532 | /* Ensure insv's size is wide enough for this field. */ | |
a242b083 | 533 | && (GET_MODE_BITSIZE (op_mode) >= bitsize) |
39e0911f | 534 | && ! ((GET_CODE (op0) == REG || GET_CODE (op0) == SUBREG) |
a242b083 | 535 | && (bitsize + bitpos > GET_MODE_BITSIZE (op_mode)))) |
44037a66 TG |
536 | { |
537 | int xbitpos = bitpos; | |
538 | rtx value1; | |
539 | rtx xop0 = op0; | |
540 | rtx last = get_last_insn (); | |
541 | rtx pat; | |
d523b40e | 542 | enum machine_mode maxmode = mode_for_extraction (EP_insv, 3); |
44037a66 | 543 | int save_volatile_ok = volatile_ok; |
0d8e55d8 | 544 | |
44037a66 TG |
545 | volatile_ok = 1; |
546 | ||
4dbebeb2 JW |
547 | /* If this machine's insv can only insert into a register, copy OP0 |
548 | into a register and save it back later. */ | |
549 | /* This used to check flag_force_mem, but that was a serious | |
550 | de-optimization now that flag_force_mem is enabled by -O2. */ | |
44037a66 | 551 | if (GET_CODE (op0) == MEM |
a995e389 | 552 | && ! ((*insn_data[(int) CODE_FOR_insv].operand[0].predicate) |
4dbebeb2 | 553 | (op0, VOIDmode))) |
44037a66 TG |
554 | { |
555 | rtx tempreg; | |
556 | enum machine_mode bestmode; | |
557 | ||
558 | /* Get the mode to use for inserting into this field. If OP0 is | |
559 | BLKmode, get the smallest mode consistent with the alignment. If | |
560 | OP0 is a non-BLKmode object that is no wider than MAXMODE, use its | |
561 | mode. Otherwise, use the smallest mode containing the field. */ | |
562 | ||
563 | if (GET_MODE (op0) == BLKmode | |
564 | || GET_MODE_SIZE (GET_MODE (op0)) > GET_MODE_SIZE (maxmode)) | |
565 | bestmode | |
04050c69 | 566 | = get_best_mode (bitsize, bitnum, MEM_ALIGN (op0), maxmode, |
717702e6 | 567 | MEM_VOLATILE_P (op0)); |
44037a66 TG |
568 | else |
569 | bestmode = GET_MODE (op0); | |
570 | ||
bd5d175a | 571 | if (bestmode == VOIDmode |
04050c69 RK |
572 | || (SLOW_UNALIGNED_ACCESS (bestmode, MEM_ALIGN (op0)) |
573 | && GET_MODE_BITSIZE (bestmode) > MEM_ALIGN (op0))) | |
44037a66 TG |
574 | goto insv_loses; |
575 | ||
04050c69 RK |
576 | /* Adjust address to point to the containing unit of that mode. |
577 | Compute offset as multiple of this unit, counting in bytes. */ | |
44037a66 | 578 | unit = GET_MODE_BITSIZE (bestmode); |
44037a66 TG |
579 | offset = (bitnum / unit) * GET_MODE_SIZE (bestmode); |
580 | bitpos = bitnum % unit; | |
f4ef873c | 581 | op0 = adjust_address (op0, bestmode, offset); |
44037a66 | 582 | |
0e805f81 RK |
583 | /* Fetch that unit, store the bitfield in it, then store |
584 | the unit. */ | |
44037a66 TG |
585 | tempreg = copy_to_reg (op0); |
586 | store_bit_field (tempreg, bitsize, bitpos, fieldmode, value, | |
04050c69 | 587 | total_size); |
44037a66 TG |
588 | emit_move_insn (op0, tempreg); |
589 | return value; | |
590 | } | |
591 | volatile_ok = save_volatile_ok; | |
592 | ||
593 | /* Add OFFSET into OP0's address. */ | |
594 | if (GET_CODE (xop0) == MEM) | |
f4ef873c | 595 | xop0 = adjust_address (xop0, byte_mode, offset); |
44037a66 TG |
596 | |
597 | /* If xop0 is a register, we need it in MAXMODE | |
598 | to make it acceptable to the format of insv. */ | |
599 | if (GET_CODE (xop0) == SUBREG) | |
bac7cdfd DE |
600 | /* We can't just change the mode, because this might clobber op0, |
601 | and we will need the original value of op0 if insv fails. */ | |
ddef6bc7 | 602 | xop0 = gen_rtx_SUBREG (maxmode, SUBREG_REG (xop0), SUBREG_BYTE (xop0)); |
44037a66 | 603 | if (GET_CODE (xop0) == REG && GET_MODE (xop0) != maxmode) |
38a448ca | 604 | xop0 = gen_rtx_SUBREG (maxmode, xop0, 0); |
44037a66 TG |
605 | |
606 | /* On big-endian machines, we count bits from the most significant. | |
607 | If the bit field insn does not, we must invert. */ | |
608 | ||
f76b9db2 ILT |
609 | if (BITS_BIG_ENDIAN != BYTES_BIG_ENDIAN) |
610 | xbitpos = unit - bitsize - xbitpos; | |
611 | ||
44037a66 TG |
612 | /* We have been counting XBITPOS within UNIT. |
613 | Count instead within the size of the register. */ | |
f76b9db2 | 614 | if (BITS_BIG_ENDIAN && GET_CODE (xop0) != MEM) |
44037a66 | 615 | xbitpos += GET_MODE_BITSIZE (maxmode) - unit; |
f76b9db2 | 616 | |
44037a66 TG |
617 | unit = GET_MODE_BITSIZE (maxmode); |
618 | ||
619 | /* Convert VALUE to maxmode (which insv insn wants) in VALUE1. */ | |
620 | value1 = value; | |
621 | if (GET_MODE (value) != maxmode) | |
622 | { | |
623 | if (GET_MODE_BITSIZE (GET_MODE (value)) >= bitsize) | |
624 | { | |
625 | /* Optimization: Don't bother really extending VALUE | |
f5df292e RS |
626 | if it has all the bits we will actually use. However, |
627 | if we must narrow it, be sure we do it correctly. */ | |
44037a66 | 628 | |
f5df292e | 629 | if (GET_MODE_SIZE (GET_MODE (value)) < GET_MODE_SIZE (maxmode)) |
04050c69 RK |
630 | value1 = simplify_gen_subreg (maxmode, value1, |
631 | GET_MODE (value1), 0); | |
f5df292e RS |
632 | else |
633 | value1 = gen_lowpart (maxmode, value1); | |
44037a66 | 634 | } |
69107307 AO |
635 | else if (GET_CODE (value) == CONST_INT) |
636 | value1 = GEN_INT (trunc_int_for_mode (INTVAL (value), maxmode)); | |
44037a66 TG |
637 | else if (!CONSTANT_P (value)) |
638 | /* Parse phase is supposed to make VALUE's data type | |
639 | match that of the component reference, which is a type | |
640 | at least as wide as the field; so VALUE should have | |
641 | a mode that corresponds to that type. */ | |
642 | abort (); | |
643 | } | |
644 | ||
645 | /* If this machine's insv insists on a register, | |
646 | get VALUE1 into a register. */ | |
a995e389 | 647 | if (! ((*insn_data[(int) CODE_FOR_insv].operand[3].predicate) |
44037a66 TG |
648 | (value1, maxmode))) |
649 | value1 = force_reg (maxmode, value1); | |
650 | ||
b1ec3c92 | 651 | pat = gen_insv (xop0, GEN_INT (bitsize), GEN_INT (xbitpos), value1); |
44037a66 TG |
652 | if (pat) |
653 | emit_insn (pat); | |
654 | else | |
655 | { | |
656 | delete_insns_since (last); | |
04050c69 | 657 | store_fixed_bit_field (op0, offset, bitsize, bitpos, value); |
44037a66 TG |
658 | } |
659 | } | |
660 | else | |
661 | insv_loses: | |
44037a66 | 662 | /* Insv is not available; store using shifts and boolean ops. */ |
04050c69 | 663 | store_fixed_bit_field (op0, offset, bitsize, bitpos, value); |
44037a66 TG |
664 | return value; |
665 | } | |
666 | \f | |
667 | /* Use shifts and boolean operations to store VALUE | |
668 | into a bit field of width BITSIZE | |
669 | in a memory location specified by OP0 except offset by OFFSET bytes. | |
670 | (OFFSET must be 0 if OP0 is a register.) | |
671 | The field starts at position BITPOS within the byte. | |
672 | (If OP0 is a register, it may be a full word or a narrower mode, | |
673 | but BITPOS still counts within a full word, | |
674 | which is significant on bigendian machines.) | |
44037a66 TG |
675 | |
676 | Note that protect_from_queue has already been done on OP0 and VALUE. */ | |
677 | ||
678 | static void | |
04050c69 | 679 | store_fixed_bit_field (op0, offset, bitsize, bitpos, value) |
b3694847 | 680 | rtx op0; |
770ae6cc | 681 | unsigned HOST_WIDE_INT offset, bitsize, bitpos; |
b3694847 | 682 | rtx value; |
44037a66 | 683 | { |
b3694847 | 684 | enum machine_mode mode; |
770ae6cc | 685 | unsigned int total_bits = BITS_PER_WORD; |
44037a66 TG |
686 | rtx subtarget, temp; |
687 | int all_zero = 0; | |
688 | int all_one = 0; | |
689 | ||
44037a66 TG |
690 | /* There is a case not handled here: |
691 | a structure with a known alignment of just a halfword | |
692 | and a field split across two aligned halfwords within the structure. | |
693 | Or likewise a structure with a known alignment of just a byte | |
694 | and a field split across two bytes. | |
695 | Such cases are not supposed to be able to occur. */ | |
696 | ||
697 | if (GET_CODE (op0) == REG || GET_CODE (op0) == SUBREG) | |
698 | { | |
699 | if (offset != 0) | |
700 | abort (); | |
701 | /* Special treatment for a bit field split across two registers. */ | |
702 | if (bitsize + bitpos > BITS_PER_WORD) | |
703 | { | |
04050c69 | 704 | store_split_bit_field (op0, bitsize, bitpos, value); |
44037a66 TG |
705 | return; |
706 | } | |
707 | } | |
708 | else | |
709 | { | |
710 | /* Get the proper mode to use for this field. We want a mode that | |
711 | includes the entire field. If such a mode would be larger than | |
053a35af AH |
712 | a word, we won't be doing the extraction the normal way. |
713 | We don't want a mode bigger than the destination. */ | |
44037a66 | 714 | |
053a35af AH |
715 | mode = GET_MODE (op0); |
716 | if (GET_MODE_BITSIZE (mode) == 0 | |
717 | || GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (word_mode)) | |
718 | mode = word_mode; | |
44037a66 | 719 | mode = get_best_mode (bitsize, bitpos + offset * BITS_PER_UNIT, |
04050c69 | 720 | MEM_ALIGN (op0), mode, MEM_VOLATILE_P (op0)); |
44037a66 TG |
721 | |
722 | if (mode == VOIDmode) | |
723 | { | |
724 | /* The only way this should occur is if the field spans word | |
725 | boundaries. */ | |
04050c69 RK |
726 | store_split_bit_field (op0, bitsize, bitpos + offset * BITS_PER_UNIT, |
727 | value); | |
44037a66 TG |
728 | return; |
729 | } | |
730 | ||
731 | total_bits = GET_MODE_BITSIZE (mode); | |
732 | ||
3bd98790 | 733 | /* Make sure bitpos is valid for the chosen mode. Adjust BITPOS to |
38e01259 | 734 | be in the range 0 to total_bits-1, and put any excess bytes in |
3bd98790 JW |
735 | OFFSET. */ |
736 | if (bitpos >= total_bits) | |
737 | { | |
738 | offset += (bitpos / total_bits) * (total_bits / BITS_PER_UNIT); | |
739 | bitpos -= ((bitpos / total_bits) * (total_bits / BITS_PER_UNIT) | |
740 | * BITS_PER_UNIT); | |
741 | } | |
742 | ||
44037a66 TG |
743 | /* Get ref to an aligned byte, halfword, or word containing the field. |
744 | Adjust BITPOS to be position within a word, | |
745 | and OFFSET to be the offset of that word. | |
746 | Then alter OP0 to refer to that word. */ | |
747 | bitpos += (offset % (total_bits / BITS_PER_UNIT)) * BITS_PER_UNIT; | |
748 | offset -= (offset % (total_bits / BITS_PER_UNIT)); | |
f4ef873c | 749 | op0 = adjust_address (op0, mode, offset); |
44037a66 TG |
750 | } |
751 | ||
752 | mode = GET_MODE (op0); | |
753 | ||
754 | /* Now MODE is either some integral mode for a MEM as OP0, | |
755 | or is a full-word for a REG as OP0. TOTAL_BITS corresponds. | |
756 | The bit field is contained entirely within OP0. | |
757 | BITPOS is the starting bit number within OP0. | |
758 | (OP0's mode may actually be narrower than MODE.) */ | |
759 | ||
f76b9db2 ILT |
760 | if (BYTES_BIG_ENDIAN) |
761 | /* BITPOS is the distance between our msb | |
762 | and that of the containing datum. | |
763 | Convert it to the distance from the lsb. */ | |
764 | bitpos = total_bits - bitsize - bitpos; | |
44037a66 | 765 | |
44037a66 TG |
766 | /* Now BITPOS is always the distance between our lsb |
767 | and that of OP0. */ | |
768 | ||
769 | /* Shift VALUE left by BITPOS bits. If VALUE is not constant, | |
770 | we must first convert its mode to MODE. */ | |
771 | ||
772 | if (GET_CODE (value) == CONST_INT) | |
773 | { | |
b3694847 | 774 | HOST_WIDE_INT v = INTVAL (value); |
44037a66 | 775 | |
b1ec3c92 CH |
776 | if (bitsize < HOST_BITS_PER_WIDE_INT) |
777 | v &= ((HOST_WIDE_INT) 1 << bitsize) - 1; | |
44037a66 TG |
778 | |
779 | if (v == 0) | |
780 | all_zero = 1; | |
b1ec3c92 CH |
781 | else if ((bitsize < HOST_BITS_PER_WIDE_INT |
782 | && v == ((HOST_WIDE_INT) 1 << bitsize) - 1) | |
783 | || (bitsize == HOST_BITS_PER_WIDE_INT && v == -1)) | |
44037a66 TG |
784 | all_one = 1; |
785 | ||
786 | value = lshift_value (mode, value, bitpos, bitsize); | |
787 | } | |
788 | else | |
789 | { | |
790 | int must_and = (GET_MODE_BITSIZE (GET_MODE (value)) != bitsize | |
791 | && bitpos + bitsize != GET_MODE_BITSIZE (mode)); | |
792 | ||
793 | if (GET_MODE (value) != mode) | |
794 | { | |
44037a66 TG |
795 | if ((GET_CODE (value) == REG || GET_CODE (value) == SUBREG) |
796 | && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (value))) | |
797 | value = gen_lowpart (mode, value); | |
798 | else | |
799 | value = convert_to_mode (mode, value, 1); | |
800 | } | |
801 | ||
802 | if (must_and) | |
803 | value = expand_binop (mode, and_optab, value, | |
804 | mask_rtx (mode, 0, bitsize, 0), | |
b1ec3c92 | 805 | NULL_RTX, 1, OPTAB_LIB_WIDEN); |
44037a66 TG |
806 | if (bitpos > 0) |
807 | value = expand_shift (LSHIFT_EXPR, mode, value, | |
b1ec3c92 | 808 | build_int_2 (bitpos, 0), NULL_RTX, 1); |
44037a66 TG |
809 | } |
810 | ||
811 | /* Now clear the chosen bits in OP0, | |
812 | except that if VALUE is -1 we need not bother. */ | |
813 | ||
814 | subtarget = (GET_CODE (op0) == REG || ! flag_force_mem) ? op0 : 0; | |
815 | ||
816 | if (! all_one) | |
817 | { | |
818 | temp = expand_binop (mode, and_optab, op0, | |
819 | mask_rtx (mode, bitpos, bitsize, 1), | |
820 | subtarget, 1, OPTAB_LIB_WIDEN); | |
821 | subtarget = temp; | |
822 | } | |
823 | else | |
824 | temp = op0; | |
825 | ||
826 | /* Now logical-or VALUE into OP0, unless it is zero. */ | |
827 | ||
828 | if (! all_zero) | |
829 | temp = expand_binop (mode, ior_optab, temp, value, | |
830 | subtarget, 1, OPTAB_LIB_WIDEN); | |
831 | if (op0 != temp) | |
832 | emit_move_insn (op0, temp); | |
833 | } | |
834 | \f | |
06c94bce | 835 | /* Store a bit field that is split across multiple accessible memory objects. |
44037a66 | 836 | |
06c94bce | 837 | OP0 is the REG, SUBREG or MEM rtx for the first of the objects. |
44037a66 TG |
838 | BITSIZE is the field width; BITPOS the position of its first bit |
839 | (within the word). | |
06c94bce | 840 | VALUE is the value to store. |
06c94bce RS |
841 | |
842 | This does not yet handle fields wider than BITS_PER_WORD. */ | |
44037a66 TG |
843 | |
844 | static void | |
04050c69 | 845 | store_split_bit_field (op0, bitsize, bitpos, value) |
44037a66 | 846 | rtx op0; |
770ae6cc | 847 | unsigned HOST_WIDE_INT bitsize, bitpos; |
44037a66 | 848 | rtx value; |
44037a66 | 849 | { |
770ae6cc RK |
850 | unsigned int unit; |
851 | unsigned int bitsdone = 0; | |
4ee16841 | 852 | |
0eb61c19 DE |
853 | /* Make sure UNIT isn't larger than BITS_PER_WORD, we can only handle that |
854 | much at a time. */ | |
4ee16841 DE |
855 | if (GET_CODE (op0) == REG || GET_CODE (op0) == SUBREG) |
856 | unit = BITS_PER_WORD; | |
857 | else | |
04050c69 | 858 | unit = MIN (MEM_ALIGN (op0), BITS_PER_WORD); |
e54d80d0 | 859 | |
3d709ff0 RS |
860 | /* If VALUE is a constant other than a CONST_INT, get it into a register in |
861 | WORD_MODE. If we can do this using gen_lowpart_common, do so. Note | |
862 | that VALUE might be a floating-point constant. */ | |
44037a66 | 863 | if (CONSTANT_P (value) && GET_CODE (value) != CONST_INT) |
3d709ff0 RS |
864 | { |
865 | rtx word = gen_lowpart_common (word_mode, value); | |
866 | ||
bc8a0e39 | 867 | if (word && (value != word)) |
3d709ff0 RS |
868 | value = word; |
869 | else | |
870 | value = gen_lowpart_common (word_mode, | |
d01bc862 DE |
871 | force_reg (GET_MODE (value) != VOIDmode |
872 | ? GET_MODE (value) | |
873 | : word_mode, value)); | |
3d709ff0 | 874 | } |
956d6950 JL |
875 | else if (GET_CODE (value) == ADDRESSOF) |
876 | value = copy_to_reg (value); | |
44037a66 | 877 | |
06c94bce | 878 | while (bitsdone < bitsize) |
44037a66 | 879 | { |
770ae6cc | 880 | unsigned HOST_WIDE_INT thissize; |
06c94bce | 881 | rtx part, word; |
770ae6cc RK |
882 | unsigned HOST_WIDE_INT thispos; |
883 | unsigned HOST_WIDE_INT offset; | |
44037a66 | 884 | |
06c94bce RS |
885 | offset = (bitpos + bitsdone) / unit; |
886 | thispos = (bitpos + bitsdone) % unit; | |
44037a66 | 887 | |
0eb61c19 DE |
888 | /* THISSIZE must not overrun a word boundary. Otherwise, |
889 | store_fixed_bit_field will call us again, and we will mutually | |
890 | recurse forever. */ | |
891 | thissize = MIN (bitsize - bitsdone, BITS_PER_WORD); | |
892 | thissize = MIN (thissize, unit - thispos); | |
44037a66 | 893 | |
f76b9db2 ILT |
894 | if (BYTES_BIG_ENDIAN) |
895 | { | |
37811a73 RK |
896 | int total_bits; |
897 | ||
898 | /* We must do an endian conversion exactly the same way as it is | |
899 | done in extract_bit_field, so that the two calls to | |
900 | extract_fixed_bit_field will have comparable arguments. */ | |
1d269b0c | 901 | if (GET_CODE (value) != MEM || GET_MODE (value) == BLKmode) |
37811a73 RK |
902 | total_bits = BITS_PER_WORD; |
903 | else | |
904 | total_bits = GET_MODE_BITSIZE (GET_MODE (value)); | |
905 | ||
f76b9db2 ILT |
906 | /* Fetch successively less significant portions. */ |
907 | if (GET_CODE (value) == CONST_INT) | |
908 | part = GEN_INT (((unsigned HOST_WIDE_INT) (INTVAL (value)) | |
909 | >> (bitsize - bitsdone - thissize)) | |
910 | & (((HOST_WIDE_INT) 1 << thissize) - 1)); | |
911 | else | |
912 | /* The args are chosen so that the last part includes the | |
913 | lsb. Give extract_bit_field the value it needs (with | |
04050c69 RK |
914 | endianness compensation) to fetch the piece we want. */ |
915 | part = extract_fixed_bit_field (word_mode, value, 0, thissize, | |
916 | total_bits - bitsize + bitsdone, | |
917 | NULL_RTX, 1); | |
f76b9db2 | 918 | } |
06c94bce | 919 | else |
f76b9db2 ILT |
920 | { |
921 | /* Fetch successively more significant portions. */ | |
922 | if (GET_CODE (value) == CONST_INT) | |
923 | part = GEN_INT (((unsigned HOST_WIDE_INT) (INTVAL (value)) | |
924 | >> bitsdone) | |
925 | & (((HOST_WIDE_INT) 1 << thissize) - 1)); | |
926 | else | |
04050c69 RK |
927 | part = extract_fixed_bit_field (word_mode, value, 0, thissize, |
928 | bitsdone, NULL_RTX, 1); | |
f76b9db2 | 929 | } |
44037a66 | 930 | |
06c94bce | 931 | /* If OP0 is a register, then handle OFFSET here. |
5f57dff0 JW |
932 | |
933 | When handling multiword bitfields, extract_bit_field may pass | |
934 | down a word_mode SUBREG of a larger REG for a bitfield that actually | |
935 | crosses a word boundary. Thus, for a SUBREG, we must find | |
936 | the current word starting from the base register. */ | |
937 | if (GET_CODE (op0) == SUBREG) | |
938 | { | |
ddef6bc7 JJ |
939 | int word_offset = (SUBREG_BYTE (op0) / UNITS_PER_WORD) + offset; |
940 | word = operand_subword_force (SUBREG_REG (op0), word_offset, | |
4ee16841 | 941 | GET_MODE (SUBREG_REG (op0))); |
5f57dff0 JW |
942 | offset = 0; |
943 | } | |
944 | else if (GET_CODE (op0) == REG) | |
06c94bce | 945 | { |
4ee16841 | 946 | word = operand_subword_force (op0, offset, GET_MODE (op0)); |
06c94bce RS |
947 | offset = 0; |
948 | } | |
949 | else | |
950 | word = op0; | |
44037a66 | 951 | |
0eb61c19 DE |
952 | /* OFFSET is in UNITs, and UNIT is in bits. |
953 | store_fixed_bit_field wants offset in bytes. */ | |
04050c69 RK |
954 | store_fixed_bit_field (word, offset * unit / BITS_PER_UNIT, thissize, |
955 | thispos, part); | |
06c94bce RS |
956 | bitsdone += thissize; |
957 | } | |
44037a66 TG |
958 | } |
959 | \f | |
960 | /* Generate code to extract a byte-field from STR_RTX | |
961 | containing BITSIZE bits, starting at BITNUM, | |
962 | and put it in TARGET if possible (if TARGET is nonzero). | |
963 | Regardless of TARGET, we return the rtx for where the value is placed. | |
964 | It may be a QUEUED. | |
965 | ||
966 | STR_RTX is the structure containing the byte (a REG or MEM). | |
967 | UNSIGNEDP is nonzero if this is an unsigned bit field. | |
968 | MODE is the natural mode of the field value once extracted. | |
969 | TMODE is the mode the caller would like the value to have; | |
970 | but the value may be returned with type MODE instead. | |
971 | ||
44037a66 TG |
972 | TOTAL_SIZE is the size in bytes of the containing structure, |
973 | or -1 if varying. | |
974 | ||
975 | If a TARGET is specified and we can store in it at no extra cost, | |
976 | we do so, and return TARGET. | |
977 | Otherwise, we return a REG of mode TMODE or MODE, with TMODE preferred | |
978 | if they are equally easy. */ | |
979 | ||
980 | rtx | |
981 | extract_bit_field (str_rtx, bitsize, bitnum, unsignedp, | |
04050c69 | 982 | target, mode, tmode, total_size) |
44037a66 | 983 | rtx str_rtx; |
770ae6cc RK |
984 | unsigned HOST_WIDE_INT bitsize; |
985 | unsigned HOST_WIDE_INT bitnum; | |
44037a66 TG |
986 | int unsignedp; |
987 | rtx target; | |
988 | enum machine_mode mode, tmode; | |
770ae6cc | 989 | HOST_WIDE_INT total_size; |
44037a66 | 990 | { |
770ae6cc RK |
991 | unsigned int unit |
992 | = (GET_CODE (str_rtx) == MEM) ? BITS_PER_UNIT : BITS_PER_WORD; | |
993 | unsigned HOST_WIDE_INT offset = bitnum / unit; | |
994 | unsigned HOST_WIDE_INT bitpos = bitnum % unit; | |
b3694847 | 995 | rtx op0 = str_rtx; |
44037a66 TG |
996 | rtx spec_target = target; |
997 | rtx spec_target_subreg = 0; | |
3306eb80 | 998 | enum machine_mode int_mode; |
a242b083 ZW |
999 | enum machine_mode extv_mode = mode_for_extraction (EP_extv, 0); |
1000 | enum machine_mode extzv_mode = mode_for_extraction (EP_extzv, 0); | |
e98f90d3 GK |
1001 | enum machine_mode mode1; |
1002 | int byte_offset; | |
44037a66 | 1003 | |
44037a66 TG |
1004 | /* Discount the part of the structure before the desired byte. |
1005 | We need to know how many bytes are safe to reference after it. */ | |
1006 | if (total_size >= 0) | |
1007 | total_size -= (bitpos / BIGGEST_ALIGNMENT | |
1008 | * (BIGGEST_ALIGNMENT / BITS_PER_UNIT)); | |
1009 | ||
1010 | if (tmode == VOIDmode) | |
1011 | tmode = mode; | |
44037a66 TG |
1012 | while (GET_CODE (op0) == SUBREG) |
1013 | { | |
64191612 MM |
1014 | int outer_size = GET_MODE_BITSIZE (GET_MODE (op0)); |
1015 | int inner_size = GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))); | |
1016 | ||
ddef6bc7 | 1017 | offset += SUBREG_BYTE (op0) / UNITS_PER_WORD; |
64191612 | 1018 | |
e5e809f4 JL |
1019 | inner_size = MIN (inner_size, BITS_PER_WORD); |
1020 | ||
64191612 MM |
1021 | if (BYTES_BIG_ENDIAN && (outer_size < inner_size)) |
1022 | { | |
1023 | bitpos += inner_size - outer_size; | |
1024 | if (bitpos > unit) | |
1025 | { | |
1026 | offset += (bitpos / unit); | |
1027 | bitpos %= unit; | |
1028 | } | |
1029 | } | |
1030 | ||
44037a66 TG |
1031 | op0 = SUBREG_REG (op0); |
1032 | } | |
77295dec | 1033 | |
aac280fb DD |
1034 | if (GET_CODE (op0) == REG |
1035 | && mode == GET_MODE (op0) | |
1036 | && bitnum == 0 | |
1037 | && bitsize == GET_MODE_BITSIZE (GET_MODE (op0))) | |
1038 | { | |
1039 | /* We're trying to extract a full register from itself. */ | |
1040 | return op0; | |
1041 | } | |
1042 | ||
d006aa54 RH |
1043 | /* Make sure we are playing with integral modes. Pun with subregs |
1044 | if we aren't. */ | |
1045 | { | |
1046 | enum machine_mode imode = int_mode_for_mode (GET_MODE (op0)); | |
1047 | if (imode != GET_MODE (op0)) | |
1048 | { | |
1049 | if (GET_CODE (op0) == MEM) | |
f4ef873c | 1050 | op0 = adjust_address (op0, imode, 0); |
d006aa54 RH |
1051 | else if (imode != BLKmode) |
1052 | op0 = gen_lowpart (imode, op0); | |
1053 | else | |
1054 | abort (); | |
1055 | } | |
1056 | } | |
1057 | ||
77295dec DE |
1058 | /* ??? We currently assume TARGET is at least as big as BITSIZE. |
1059 | If that's wrong, the solution is to test for it and set TARGET to 0 | |
1060 | if needed. */ | |
44037a66 | 1061 | |
44037a66 TG |
1062 | /* If OP0 is a register, BITPOS must count within a word. |
1063 | But as we have it, it counts within whatever size OP0 now has. | |
1064 | On a bigendian machine, these are not the same, so convert. */ | |
db3cf6fb MS |
1065 | if (BYTES_BIG_ENDIAN |
1066 | && GET_CODE (op0) != MEM | |
f76b9db2 | 1067 | && unit > GET_MODE_BITSIZE (GET_MODE (op0))) |
44037a66 | 1068 | bitpos += unit - GET_MODE_BITSIZE (GET_MODE (op0)); |
44037a66 TG |
1069 | |
1070 | /* Extracting a full-word or multi-word value | |
c7e33f89 | 1071 | from a structure in a register or aligned memory. |
44037a66 TG |
1072 | This can be done with just SUBREG. |
1073 | So too extracting a subword value in | |
1074 | the least significant part of the register. */ | |
1075 | ||
e98f90d3 GK |
1076 | byte_offset = (bitnum % BITS_PER_WORD) / BITS_PER_UNIT |
1077 | + (offset * UNITS_PER_WORD); | |
1078 | ||
1079 | mode1 = (VECTOR_MODE_P (tmode) | |
1080 | ? mode | |
1081 | : mode_for_size (bitsize, GET_MODE_CLASS (tmode), 0)); | |
1082 | ||
d006aa54 | 1083 | if (((GET_CODE (op0) != MEM |
f8fe20b2 | 1084 | && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode), |
e98f90d3 GK |
1085 | GET_MODE_BITSIZE (GET_MODE (op0))) |
1086 | && GET_MODE_SIZE (mode1) != 0 | |
1087 | && byte_offset % GET_MODE_SIZE (mode1) == 0) | |
c7e33f89 | 1088 | || (GET_CODE (op0) == MEM |
04050c69 | 1089 | && (! SLOW_UNALIGNED_ACCESS (mode, MEM_ALIGN (op0)) |
c7e33f89 | 1090 | || (offset * BITS_PER_UNIT % bitsize == 0 |
04050c69 | 1091 | && MEM_ALIGN (op0) % bitsize == 0)))) |
44037a66 TG |
1092 | && ((bitsize >= BITS_PER_WORD && bitsize == GET_MODE_BITSIZE (mode) |
1093 | && bitpos % BITS_PER_WORD == 0) | |
1094 | || (mode_for_size (bitsize, GET_MODE_CLASS (tmode), 0) != BLKmode | |
f916eeb6 NC |
1095 | /* ??? The big endian test here is wrong. This is correct |
1096 | if the value is in a register, and if mode_for_size is not | |
1097 | the same mode as op0. This causes us to get unnecessarily | |
1098 | inefficient code from the Thumb port when -mbig-endian. */ | |
f76b9db2 ILT |
1099 | && (BYTES_BIG_ENDIAN |
1100 | ? bitpos + bitsize == BITS_PER_WORD | |
1101 | : bitpos == 0)))) | |
44037a66 | 1102 | { |
44037a66 | 1103 | if (mode1 != GET_MODE (op0)) |
c7e33f89 | 1104 | { |
d006aa54 RH |
1105 | if (GET_CODE (op0) == SUBREG) |
1106 | { | |
1107 | if (GET_MODE (SUBREG_REG (op0)) == mode1 | |
1108 | || GET_MODE_CLASS (mode1) == MODE_INT | |
1109 | || GET_MODE_CLASS (mode1) == MODE_PARTIAL_INT) | |
1110 | op0 = SUBREG_REG (op0); | |
1111 | else | |
1112 | /* Else we've got some float mode source being extracted into | |
1113 | a different float mode destination -- this combination of | |
1114 | subregs results in Severe Tire Damage. */ | |
1115 | abort (); | |
1116 | } | |
c7e33f89 | 1117 | if (GET_CODE (op0) == REG) |
e98f90d3 | 1118 | op0 = gen_rtx_SUBREG (mode1, op0, byte_offset); |
c7e33f89 | 1119 | else |
f4ef873c | 1120 | op0 = adjust_address (op0, mode1, offset); |
c7e33f89 | 1121 | } |
44037a66 TG |
1122 | if (mode1 != mode) |
1123 | return convert_to_mode (tmode, op0, unsignedp); | |
1124 | return op0; | |
1125 | } | |
1126 | ||
1127 | /* Handle fields bigger than a word. */ | |
1128 | ||
1129 | if (bitsize > BITS_PER_WORD) | |
1130 | { | |
1131 | /* Here we transfer the words of the field | |
1132 | in the order least significant first. | |
1133 | This is because the most significant word is the one which may | |
1134 | be less than full. */ | |
1135 | ||
770ae6cc RK |
1136 | unsigned int nwords = (bitsize + (BITS_PER_WORD - 1)) / BITS_PER_WORD; |
1137 | unsigned int i; | |
44037a66 TG |
1138 | |
1139 | if (target == 0 || GET_CODE (target) != REG) | |
1140 | target = gen_reg_rtx (mode); | |
1141 | ||
34ea783b | 1142 | /* Indicate for flow that the entire target reg is being set. */ |
38a448ca | 1143 | emit_insn (gen_rtx_CLOBBER (VOIDmode, target)); |
34ea783b | 1144 | |
44037a66 TG |
1145 | for (i = 0; i < nwords; i++) |
1146 | { | |
1147 | /* If I is 0, use the low-order word in both field and target; | |
1148 | if I is 1, use the next to lowest word; and so on. */ | |
77295dec | 1149 | /* Word number in TARGET to use. */ |
770ae6cc RK |
1150 | unsigned int wordnum |
1151 | = (WORDS_BIG_ENDIAN | |
1152 | ? GET_MODE_SIZE (GET_MODE (target)) / UNITS_PER_WORD - i - 1 | |
1153 | : i); | |
77295dec | 1154 | /* Offset from start of field in OP0. */ |
770ae6cc RK |
1155 | unsigned int bit_offset = (WORDS_BIG_ENDIAN |
1156 | ? MAX (0, ((int) bitsize - ((int) i + 1) | |
75131237 | 1157 | * (int) BITS_PER_WORD)) |
770ae6cc | 1158 | : (int) i * BITS_PER_WORD); |
44037a66 TG |
1159 | rtx target_part = operand_subword (target, wordnum, 1, VOIDmode); |
1160 | rtx result_part | |
1161 | = extract_bit_field (op0, MIN (BITS_PER_WORD, | |
1162 | bitsize - i * BITS_PER_WORD), | |
19caa751 | 1163 | bitnum + bit_offset, 1, target_part, mode, |
04050c69 | 1164 | word_mode, total_size); |
44037a66 TG |
1165 | |
1166 | if (target_part == 0) | |
1167 | abort (); | |
1168 | ||
1169 | if (result_part != target_part) | |
1170 | emit_move_insn (target_part, result_part); | |
1171 | } | |
1172 | ||
5f57dff0 | 1173 | if (unsignedp) |
77295dec DE |
1174 | { |
1175 | /* Unless we've filled TARGET, the upper regs in a multi-reg value | |
1176 | need to be zero'd out. */ | |
1177 | if (GET_MODE_SIZE (GET_MODE (target)) > nwords * UNITS_PER_WORD) | |
1178 | { | |
770ae6cc | 1179 | unsigned int i, total_words; |
77295dec DE |
1180 | |
1181 | total_words = GET_MODE_SIZE (GET_MODE (target)) / UNITS_PER_WORD; | |
1182 | for (i = nwords; i < total_words; i++) | |
04050c69 RK |
1183 | emit_move_insn |
1184 | (operand_subword (target, | |
1185 | WORDS_BIG_ENDIAN ? total_words - i - 1 : i, | |
1186 | 1, VOIDmode), | |
1187 | const0_rtx); | |
77295dec DE |
1188 | } |
1189 | return target; | |
1190 | } | |
1191 | ||
5f57dff0 JW |
1192 | /* Signed bit field: sign-extend with two arithmetic shifts. */ |
1193 | target = expand_shift (LSHIFT_EXPR, mode, target, | |
1194 | build_int_2 (GET_MODE_BITSIZE (mode) - bitsize, 0), | |
1195 | NULL_RTX, 0); | |
1196 | return expand_shift (RSHIFT_EXPR, mode, target, | |
1197 | build_int_2 (GET_MODE_BITSIZE (mode) - bitsize, 0), | |
1198 | NULL_RTX, 0); | |
44037a66 TG |
1199 | } |
1200 | ||
3306eb80 GK |
1201 | /* From here on we know the desired field is smaller than a word. */ |
1202 | ||
1203 | /* Check if there is a correspondingly-sized integer field, so we can | |
1204 | safely extract it as one size of integer, if necessary; then | |
1205 | truncate or extend to the size that is wanted; then use SUBREGs or | |
1206 | convert_to_mode to get one of the modes we really wanted. */ | |
1207 | ||
1208 | int_mode = int_mode_for_mode (tmode); | |
1209 | if (int_mode == BLKmode) | |
1210 | int_mode = int_mode_for_mode (mode); | |
1211 | if (int_mode == BLKmode) | |
c4f2c499 KH |
1212 | abort (); /* Should probably push op0 out to memory and then |
1213 | do a load. */ | |
44037a66 TG |
1214 | |
1215 | /* OFFSET is the number of words or bytes (UNIT says which) | |
1216 | from STR_RTX to the first word or byte containing part of the field. */ | |
1217 | ||
d006aa54 | 1218 | if (GET_CODE (op0) != MEM) |
44037a66 TG |
1219 | { |
1220 | if (offset != 0 | |
1221 | || GET_MODE_SIZE (GET_MODE (op0)) > UNITS_PER_WORD) | |
470032d7 RH |
1222 | { |
1223 | if (GET_CODE (op0) != REG) | |
1224 | op0 = copy_to_reg (op0); | |
1225 | op0 = gen_rtx_SUBREG (mode_for_size (BITS_PER_WORD, MODE_INT, 0), | |
ddef6bc7 | 1226 | op0, (offset * UNITS_PER_WORD)); |
470032d7 | 1227 | } |
44037a66 TG |
1228 | offset = 0; |
1229 | } | |
1230 | else | |
04050c69 | 1231 | op0 = protect_from_queue (str_rtx, 1); |
44037a66 TG |
1232 | |
1233 | /* Now OFFSET is nonzero only for memory operands. */ | |
1234 | ||
1235 | if (unsignedp) | |
1236 | { | |
a242b083 ZW |
1237 | if (HAVE_extzv |
1238 | && (GET_MODE_BITSIZE (extzv_mode) >= bitsize) | |
39e0911f | 1239 | && ! ((GET_CODE (op0) == REG || GET_CODE (op0) == SUBREG) |
a242b083 | 1240 | && (bitsize + bitpos > GET_MODE_BITSIZE (extzv_mode)))) |
44037a66 | 1241 | { |
770ae6cc | 1242 | unsigned HOST_WIDE_INT xbitpos = bitpos, xoffset = offset; |
44037a66 | 1243 | rtx bitsize_rtx, bitpos_rtx; |
e5e809f4 | 1244 | rtx last = get_last_insn (); |
44037a66 TG |
1245 | rtx xop0 = op0; |
1246 | rtx xtarget = target; | |
1247 | rtx xspec_target = spec_target; | |
1248 | rtx xspec_target_subreg = spec_target_subreg; | |
1249 | rtx pat; | |
d523b40e | 1250 | enum machine_mode maxmode = mode_for_extraction (EP_extzv, 0); |
44037a66 TG |
1251 | |
1252 | if (GET_CODE (xop0) == MEM) | |
1253 | { | |
1254 | int save_volatile_ok = volatile_ok; | |
1255 | volatile_ok = 1; | |
1256 | ||
1257 | /* Is the memory operand acceptable? */ | |
a995e389 | 1258 | if (! ((*insn_data[(int) CODE_FOR_extzv].operand[1].predicate) |
3bf1b082 | 1259 | (xop0, GET_MODE (xop0)))) |
44037a66 TG |
1260 | { |
1261 | /* No, load into a reg and extract from there. */ | |
1262 | enum machine_mode bestmode; | |
1263 | ||
1264 | /* Get the mode to use for inserting into this field. If | |
1265 | OP0 is BLKmode, get the smallest mode consistent with the | |
1266 | alignment. If OP0 is a non-BLKmode object that is no | |
1267 | wider than MAXMODE, use its mode. Otherwise, use the | |
1268 | smallest mode containing the field. */ | |
1269 | ||
1270 | if (GET_MODE (xop0) == BLKmode | |
1271 | || (GET_MODE_SIZE (GET_MODE (op0)) | |
1272 | > GET_MODE_SIZE (maxmode))) | |
04050c69 RK |
1273 | bestmode = get_best_mode (bitsize, bitnum, |
1274 | MEM_ALIGN (xop0), maxmode, | |
717702e6 | 1275 | MEM_VOLATILE_P (xop0)); |
44037a66 TG |
1276 | else |
1277 | bestmode = GET_MODE (xop0); | |
1278 | ||
bd5d175a | 1279 | if (bestmode == VOIDmode |
04050c69 RK |
1280 | || (SLOW_UNALIGNED_ACCESS (bestmode, MEM_ALIGN (xop0)) |
1281 | && GET_MODE_BITSIZE (bestmode) > MEM_ALIGN (xop0))) | |
44037a66 TG |
1282 | goto extzv_loses; |
1283 | ||
1284 | /* Compute offset as multiple of this unit, | |
1285 | counting in bytes. */ | |
1286 | unit = GET_MODE_BITSIZE (bestmode); | |
1287 | xoffset = (bitnum / unit) * GET_MODE_SIZE (bestmode); | |
1288 | xbitpos = bitnum % unit; | |
f4ef873c RK |
1289 | xop0 = adjust_address (xop0, bestmode, xoffset); |
1290 | ||
44037a66 TG |
1291 | /* Fetch it to a register in that size. */ |
1292 | xop0 = force_reg (bestmode, xop0); | |
1293 | ||
1294 | /* XBITPOS counts within UNIT, which is what is expected. */ | |
1295 | } | |
1296 | else | |
1297 | /* Get ref to first byte containing part of the field. */ | |
f4ef873c | 1298 | xop0 = adjust_address (xop0, byte_mode, xoffset); |
44037a66 TG |
1299 | |
1300 | volatile_ok = save_volatile_ok; | |
1301 | } | |
1302 | ||
1303 | /* If op0 is a register, we need it in MAXMODE (which is usually | |
1304 | SImode). to make it acceptable to the format of extzv. */ | |
1305 | if (GET_CODE (xop0) == SUBREG && GET_MODE (xop0) != maxmode) | |
e5e809f4 | 1306 | goto extzv_loses; |
44037a66 | 1307 | if (GET_CODE (xop0) == REG && GET_MODE (xop0) != maxmode) |
38a448ca | 1308 | xop0 = gen_rtx_SUBREG (maxmode, xop0, 0); |
44037a66 TG |
1309 | |
1310 | /* On big-endian machines, we count bits from the most significant. | |
1311 | If the bit field insn does not, we must invert. */ | |
f76b9db2 ILT |
1312 | if (BITS_BIG_ENDIAN != BYTES_BIG_ENDIAN) |
1313 | xbitpos = unit - bitsize - xbitpos; | |
1314 | ||
44037a66 | 1315 | /* Now convert from counting within UNIT to counting in MAXMODE. */ |
f76b9db2 | 1316 | if (BITS_BIG_ENDIAN && GET_CODE (xop0) != MEM) |
44037a66 | 1317 | xbitpos += GET_MODE_BITSIZE (maxmode) - unit; |
f76b9db2 | 1318 | |
44037a66 TG |
1319 | unit = GET_MODE_BITSIZE (maxmode); |
1320 | ||
1321 | if (xtarget == 0 | |
1322 | || (flag_force_mem && GET_CODE (xtarget) == MEM)) | |
1323 | xtarget = xspec_target = gen_reg_rtx (tmode); | |
1324 | ||
1325 | if (GET_MODE (xtarget) != maxmode) | |
1326 | { | |
1327 | if (GET_CODE (xtarget) == REG) | |
b7a09135 RS |
1328 | { |
1329 | int wider = (GET_MODE_SIZE (maxmode) | |
1330 | > GET_MODE_SIZE (GET_MODE (xtarget))); | |
1331 | xtarget = gen_lowpart (maxmode, xtarget); | |
1332 | if (wider) | |
1333 | xspec_target_subreg = xtarget; | |
1334 | } | |
44037a66 TG |
1335 | else |
1336 | xtarget = gen_reg_rtx (maxmode); | |
1337 | } | |
1338 | ||
1339 | /* If this machine's extzv insists on a register target, | |
1340 | make sure we have one. */ | |
a995e389 | 1341 | if (! ((*insn_data[(int) CODE_FOR_extzv].operand[0].predicate) |
44037a66 TG |
1342 | (xtarget, maxmode))) |
1343 | xtarget = gen_reg_rtx (maxmode); | |
1344 | ||
b1ec3c92 CH |
1345 | bitsize_rtx = GEN_INT (bitsize); |
1346 | bitpos_rtx = GEN_INT (xbitpos); | |
44037a66 TG |
1347 | |
1348 | pat = gen_extzv (protect_from_queue (xtarget, 1), | |
1349 | xop0, bitsize_rtx, bitpos_rtx); | |
1350 | if (pat) | |
1351 | { | |
1352 | emit_insn (pat); | |
1353 | target = xtarget; | |
1354 | spec_target = xspec_target; | |
1355 | spec_target_subreg = xspec_target_subreg; | |
1356 | } | |
1357 | else | |
1358 | { | |
1359 | delete_insns_since (last); | |
3306eb80 | 1360 | target = extract_fixed_bit_field (int_mode, op0, offset, bitsize, |
04050c69 | 1361 | bitpos, target, 1); |
44037a66 TG |
1362 | } |
1363 | } | |
1364 | else | |
04050c69 RK |
1365 | extzv_loses: |
1366 | target = extract_fixed_bit_field (int_mode, op0, offset, bitsize, | |
1367 | bitpos, target, 1); | |
44037a66 TG |
1368 | } |
1369 | else | |
1370 | { | |
a242b083 ZW |
1371 | if (HAVE_extv |
1372 | && (GET_MODE_BITSIZE (extv_mode) >= bitsize) | |
39e0911f | 1373 | && ! ((GET_CODE (op0) == REG || GET_CODE (op0) == SUBREG) |
a242b083 | 1374 | && (bitsize + bitpos > GET_MODE_BITSIZE (extv_mode)))) |
44037a66 TG |
1375 | { |
1376 | int xbitpos = bitpos, xoffset = offset; | |
1377 | rtx bitsize_rtx, bitpos_rtx; | |
e5e809f4 | 1378 | rtx last = get_last_insn (); |
44037a66 TG |
1379 | rtx xop0 = op0, xtarget = target; |
1380 | rtx xspec_target = spec_target; | |
1381 | rtx xspec_target_subreg = spec_target_subreg; | |
1382 | rtx pat; | |
d523b40e | 1383 | enum machine_mode maxmode = mode_for_extraction (EP_extv, 0); |
44037a66 TG |
1384 | |
1385 | if (GET_CODE (xop0) == MEM) | |
1386 | { | |
1387 | /* Is the memory operand acceptable? */ | |
a995e389 | 1388 | if (! ((*insn_data[(int) CODE_FOR_extv].operand[1].predicate) |
44037a66 TG |
1389 | (xop0, GET_MODE (xop0)))) |
1390 | { | |
1391 | /* No, load into a reg and extract from there. */ | |
1392 | enum machine_mode bestmode; | |
1393 | ||
1394 | /* Get the mode to use for inserting into this field. If | |
1395 | OP0 is BLKmode, get the smallest mode consistent with the | |
1396 | alignment. If OP0 is a non-BLKmode object that is no | |
1397 | wider than MAXMODE, use its mode. Otherwise, use the | |
1398 | smallest mode containing the field. */ | |
1399 | ||
1400 | if (GET_MODE (xop0) == BLKmode | |
1401 | || (GET_MODE_SIZE (GET_MODE (op0)) | |
1402 | > GET_MODE_SIZE (maxmode))) | |
04050c69 RK |
1403 | bestmode = get_best_mode (bitsize, bitnum, |
1404 | MEM_ALIGN (xop0), maxmode, | |
717702e6 | 1405 | MEM_VOLATILE_P (xop0)); |
44037a66 TG |
1406 | else |
1407 | bestmode = GET_MODE (xop0); | |
1408 | ||
bd5d175a | 1409 | if (bestmode == VOIDmode |
04050c69 RK |
1410 | || (SLOW_UNALIGNED_ACCESS (bestmode, MEM_ALIGN (xop0)) |
1411 | && GET_MODE_BITSIZE (bestmode) > MEM_ALIGN (xop0))) | |
44037a66 TG |
1412 | goto extv_loses; |
1413 | ||
1414 | /* Compute offset as multiple of this unit, | |
1415 | counting in bytes. */ | |
1416 | unit = GET_MODE_BITSIZE (bestmode); | |
1417 | xoffset = (bitnum / unit) * GET_MODE_SIZE (bestmode); | |
1418 | xbitpos = bitnum % unit; | |
f4ef873c RK |
1419 | xop0 = adjust_address (xop0, bestmode, xoffset); |
1420 | ||
44037a66 TG |
1421 | /* Fetch it to a register in that size. */ |
1422 | xop0 = force_reg (bestmode, xop0); | |
1423 | ||
1424 | /* XBITPOS counts within UNIT, which is what is expected. */ | |
1425 | } | |
1426 | else | |
1427 | /* Get ref to first byte containing part of the field. */ | |
f4ef873c | 1428 | xop0 = adjust_address (xop0, byte_mode, xoffset); |
44037a66 TG |
1429 | } |
1430 | ||
1431 | /* If op0 is a register, we need it in MAXMODE (which is usually | |
1432 | SImode) to make it acceptable to the format of extv. */ | |
1433 | if (GET_CODE (xop0) == SUBREG && GET_MODE (xop0) != maxmode) | |
e5e809f4 | 1434 | goto extv_loses; |
44037a66 | 1435 | if (GET_CODE (xop0) == REG && GET_MODE (xop0) != maxmode) |
38a448ca | 1436 | xop0 = gen_rtx_SUBREG (maxmode, xop0, 0); |
44037a66 TG |
1437 | |
1438 | /* On big-endian machines, we count bits from the most significant. | |
1439 | If the bit field insn does not, we must invert. */ | |
f76b9db2 ILT |
1440 | if (BITS_BIG_ENDIAN != BYTES_BIG_ENDIAN) |
1441 | xbitpos = unit - bitsize - xbitpos; | |
1442 | ||
44037a66 TG |
1443 | /* XBITPOS counts within a size of UNIT. |
1444 | Adjust to count within a size of MAXMODE. */ | |
f76b9db2 | 1445 | if (BITS_BIG_ENDIAN && GET_CODE (xop0) != MEM) |
44037a66 | 1446 | xbitpos += (GET_MODE_BITSIZE (maxmode) - unit); |
f76b9db2 | 1447 | |
44037a66 TG |
1448 | unit = GET_MODE_BITSIZE (maxmode); |
1449 | ||
1450 | if (xtarget == 0 | |
1451 | || (flag_force_mem && GET_CODE (xtarget) == MEM)) | |
1452 | xtarget = xspec_target = gen_reg_rtx (tmode); | |
1453 | ||
1454 | if (GET_MODE (xtarget) != maxmode) | |
1455 | { | |
1456 | if (GET_CODE (xtarget) == REG) | |
b7a09135 RS |
1457 | { |
1458 | int wider = (GET_MODE_SIZE (maxmode) | |
1459 | > GET_MODE_SIZE (GET_MODE (xtarget))); | |
1460 | xtarget = gen_lowpart (maxmode, xtarget); | |
1461 | if (wider) | |
1462 | xspec_target_subreg = xtarget; | |
1463 | } | |
44037a66 TG |
1464 | else |
1465 | xtarget = gen_reg_rtx (maxmode); | |
1466 | } | |
1467 | ||
1468 | /* If this machine's extv insists on a register target, | |
1469 | make sure we have one. */ | |
a995e389 | 1470 | if (! ((*insn_data[(int) CODE_FOR_extv].operand[0].predicate) |
44037a66 TG |
1471 | (xtarget, maxmode))) |
1472 | xtarget = gen_reg_rtx (maxmode); | |
1473 | ||
b1ec3c92 CH |
1474 | bitsize_rtx = GEN_INT (bitsize); |
1475 | bitpos_rtx = GEN_INT (xbitpos); | |
44037a66 TG |
1476 | |
1477 | pat = gen_extv (protect_from_queue (xtarget, 1), | |
1478 | xop0, bitsize_rtx, bitpos_rtx); | |
1479 | if (pat) | |
1480 | { | |
1481 | emit_insn (pat); | |
1482 | target = xtarget; | |
1483 | spec_target = xspec_target; | |
1484 | spec_target_subreg = xspec_target_subreg; | |
1485 | } | |
1486 | else | |
1487 | { | |
1488 | delete_insns_since (last); | |
3306eb80 | 1489 | target = extract_fixed_bit_field (int_mode, op0, offset, bitsize, |
04050c69 | 1490 | bitpos, target, 0); |
44037a66 TG |
1491 | } |
1492 | } | |
1493 | else | |
04050c69 RK |
1494 | extv_loses: |
1495 | target = extract_fixed_bit_field (int_mode, op0, offset, bitsize, | |
1496 | bitpos, target, 0); | |
44037a66 TG |
1497 | } |
1498 | if (target == spec_target) | |
1499 | return target; | |
1500 | if (target == spec_target_subreg) | |
1501 | return spec_target; | |
1502 | if (GET_MODE (target) != tmode && GET_MODE (target) != mode) | |
1503 | { | |
1504 | /* If the target mode is floating-point, first convert to the | |
1505 | integer mode of that size and then access it as a floating-point | |
1506 | value via a SUBREG. */ | |
1507 | if (GET_MODE_CLASS (tmode) == MODE_FLOAT) | |
1508 | { | |
1509 | target = convert_to_mode (mode_for_size (GET_MODE_BITSIZE (tmode), | |
1510 | MODE_INT, 0), | |
1511 | target, unsignedp); | |
1512 | if (GET_CODE (target) != REG) | |
1513 | target = copy_to_reg (target); | |
38a448ca | 1514 | return gen_rtx_SUBREG (tmode, target, 0); |
44037a66 TG |
1515 | } |
1516 | else | |
1517 | return convert_to_mode (tmode, target, unsignedp); | |
1518 | } | |
1519 | return target; | |
1520 | } | |
1521 | \f | |
1522 | /* Extract a bit field using shifts and boolean operations | |
1523 | Returns an rtx to represent the value. | |
1524 | OP0 addresses a register (word) or memory (byte). | |
1525 | BITPOS says which bit within the word or byte the bit field starts in. | |
1526 | OFFSET says how many bytes farther the bit field starts; | |
1527 | it is 0 if OP0 is a register. | |
1528 | BITSIZE says how many bits long the bit field is. | |
1529 | (If OP0 is a register, it may be narrower than a full word, | |
1530 | but BITPOS still counts within a full word, | |
1531 | which is significant on bigendian machines.) | |
1532 | ||
1533 | UNSIGNEDP is nonzero for an unsigned bit field (don't sign-extend value). | |
1534 | If TARGET is nonzero, attempts to store the value there | |
1535 | and return TARGET, but this is not guaranteed. | |
04050c69 | 1536 | If TARGET is not used, create a pseudo-reg of mode TMODE for the value. */ |
44037a66 TG |
1537 | |
1538 | static rtx | |
1539 | extract_fixed_bit_field (tmode, op0, offset, bitsize, bitpos, | |
04050c69 | 1540 | target, unsignedp) |
44037a66 | 1541 | enum machine_mode tmode; |
b3694847 | 1542 | rtx op0, target; |
770ae6cc | 1543 | unsigned HOST_WIDE_INT offset, bitsize, bitpos; |
44037a66 | 1544 | int unsignedp; |
44037a66 | 1545 | { |
770ae6cc | 1546 | unsigned int total_bits = BITS_PER_WORD; |
44037a66 TG |
1547 | enum machine_mode mode; |
1548 | ||
1549 | if (GET_CODE (op0) == SUBREG || GET_CODE (op0) == REG) | |
1550 | { | |
1551 | /* Special treatment for a bit field split across two registers. */ | |
1552 | if (bitsize + bitpos > BITS_PER_WORD) | |
04050c69 | 1553 | return extract_split_bit_field (op0, bitsize, bitpos, unsignedp); |
44037a66 TG |
1554 | } |
1555 | else | |
1556 | { | |
1557 | /* Get the proper mode to use for this field. We want a mode that | |
1558 | includes the entire field. If such a mode would be larger than | |
1559 | a word, we won't be doing the extraction the normal way. */ | |
1560 | ||
04050c69 RK |
1561 | mode = get_best_mode (bitsize, bitpos + offset * BITS_PER_UNIT, |
1562 | MEM_ALIGN (op0), word_mode, MEM_VOLATILE_P (op0)); | |
44037a66 TG |
1563 | |
1564 | if (mode == VOIDmode) | |
1565 | /* The only way this should occur is if the field spans word | |
1566 | boundaries. */ | |
1567 | return extract_split_bit_field (op0, bitsize, | |
1568 | bitpos + offset * BITS_PER_UNIT, | |
04050c69 | 1569 | unsignedp); |
44037a66 TG |
1570 | |
1571 | total_bits = GET_MODE_BITSIZE (mode); | |
1572 | ||
401db791 | 1573 | /* Make sure bitpos is valid for the chosen mode. Adjust BITPOS to |
38e01259 | 1574 | be in the range 0 to total_bits-1, and put any excess bytes in |
401db791 JW |
1575 | OFFSET. */ |
1576 | if (bitpos >= total_bits) | |
1577 | { | |
1578 | offset += (bitpos / total_bits) * (total_bits / BITS_PER_UNIT); | |
1579 | bitpos -= ((bitpos / total_bits) * (total_bits / BITS_PER_UNIT) | |
1580 | * BITS_PER_UNIT); | |
1581 | } | |
1582 | ||
44037a66 TG |
1583 | /* Get ref to an aligned byte, halfword, or word containing the field. |
1584 | Adjust BITPOS to be position within a word, | |
1585 | and OFFSET to be the offset of that word. | |
1586 | Then alter OP0 to refer to that word. */ | |
1587 | bitpos += (offset % (total_bits / BITS_PER_UNIT)) * BITS_PER_UNIT; | |
1588 | offset -= (offset % (total_bits / BITS_PER_UNIT)); | |
f4ef873c | 1589 | op0 = adjust_address (op0, mode, offset); |
44037a66 TG |
1590 | } |
1591 | ||
37811a73 RK |
1592 | mode = GET_MODE (op0); |
1593 | ||
f76b9db2 | 1594 | if (BYTES_BIG_ENDIAN) |
04050c69 RK |
1595 | /* BITPOS is the distance between our msb and that of OP0. |
1596 | Convert it to the distance from the lsb. */ | |
1597 | bitpos = total_bits - bitsize - bitpos; | |
44037a66 | 1598 | |
44037a66 TG |
1599 | /* Now BITPOS is always the distance between the field's lsb and that of OP0. |
1600 | We have reduced the big-endian case to the little-endian case. */ | |
1601 | ||
1602 | if (unsignedp) | |
1603 | { | |
1604 | if (bitpos) | |
1605 | { | |
1606 | /* If the field does not already start at the lsb, | |
1607 | shift it so it does. */ | |
1608 | tree amount = build_int_2 (bitpos, 0); | |
1609 | /* Maybe propagate the target for the shift. */ | |
1610 | /* But not if we will return it--could confuse integrate.c. */ | |
1611 | rtx subtarget = (target != 0 && GET_CODE (target) == REG | |
1612 | && !REG_FUNCTION_VALUE_P (target) | |
1613 | ? target : 0); | |
1614 | if (tmode != mode) subtarget = 0; | |
1615 | op0 = expand_shift (RSHIFT_EXPR, mode, op0, amount, subtarget, 1); | |
1616 | } | |
1617 | /* Convert the value to the desired mode. */ | |
1618 | if (mode != tmode) | |
1619 | op0 = convert_to_mode (tmode, op0, 1); | |
1620 | ||
1621 | /* Unless the msb of the field used to be the msb when we shifted, | |
1622 | mask out the upper bits. */ | |
1623 | ||
c99d986a | 1624 | if (GET_MODE_BITSIZE (mode) != bitpos + bitsize) |
44037a66 TG |
1625 | return expand_binop (GET_MODE (op0), and_optab, op0, |
1626 | mask_rtx (GET_MODE (op0), 0, bitsize, 0), | |
1627 | target, 1, OPTAB_LIB_WIDEN); | |
1628 | return op0; | |
1629 | } | |
1630 | ||
1631 | /* To extract a signed bit-field, first shift its msb to the msb of the word, | |
1632 | then arithmetic-shift its lsb to the lsb of the word. */ | |
1633 | op0 = force_reg (mode, op0); | |
1634 | if (mode != tmode) | |
1635 | target = 0; | |
1636 | ||
1637 | /* Find the narrowest integer mode that contains the field. */ | |
1638 | ||
1639 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT); mode != VOIDmode; | |
1640 | mode = GET_MODE_WIDER_MODE (mode)) | |
1641 | if (GET_MODE_BITSIZE (mode) >= bitsize + bitpos) | |
1642 | { | |
1643 | op0 = convert_to_mode (mode, op0, 0); | |
1644 | break; | |
1645 | } | |
1646 | ||
1647 | if (GET_MODE_BITSIZE (mode) != (bitsize + bitpos)) | |
1648 | { | |
04050c69 RK |
1649 | tree amount |
1650 | = build_int_2 (GET_MODE_BITSIZE (mode) - (bitsize + bitpos), 0); | |
44037a66 TG |
1651 | /* Maybe propagate the target for the shift. */ |
1652 | /* But not if we will return the result--could confuse integrate.c. */ | |
1653 | rtx subtarget = (target != 0 && GET_CODE (target) == REG | |
1654 | && ! REG_FUNCTION_VALUE_P (target) | |
1655 | ? target : 0); | |
1656 | op0 = expand_shift (LSHIFT_EXPR, mode, op0, amount, subtarget, 1); | |
1657 | } | |
1658 | ||
1659 | return expand_shift (RSHIFT_EXPR, mode, op0, | |
1660 | build_int_2 (GET_MODE_BITSIZE (mode) - bitsize, 0), | |
1661 | target, 0); | |
1662 | } | |
1663 | \f | |
1664 | /* Return a constant integer (CONST_INT or CONST_DOUBLE) mask value | |
1665 | of mode MODE with BITSIZE ones followed by BITPOS zeros, or the | |
1666 | complement of that if COMPLEMENT. The mask is truncated if | |
77295dec DE |
1667 | necessary to the width of mode MODE. The mask is zero-extended if |
1668 | BITSIZE+BITPOS is too small for MODE. */ | |
44037a66 TG |
1669 | |
1670 | static rtx | |
1671 | mask_rtx (mode, bitpos, bitsize, complement) | |
1672 | enum machine_mode mode; | |
1673 | int bitpos, bitsize, complement; | |
1674 | { | |
b1ec3c92 | 1675 | HOST_WIDE_INT masklow, maskhigh; |
44037a66 | 1676 | |
b1ec3c92 CH |
1677 | if (bitpos < HOST_BITS_PER_WIDE_INT) |
1678 | masklow = (HOST_WIDE_INT) -1 << bitpos; | |
44037a66 TG |
1679 | else |
1680 | masklow = 0; | |
1681 | ||
b1ec3c92 CH |
1682 | if (bitpos + bitsize < HOST_BITS_PER_WIDE_INT) |
1683 | masklow &= ((unsigned HOST_WIDE_INT) -1 | |
1684 | >> (HOST_BITS_PER_WIDE_INT - bitpos - bitsize)); | |
44037a66 | 1685 | |
b1ec3c92 | 1686 | if (bitpos <= HOST_BITS_PER_WIDE_INT) |
44037a66 TG |
1687 | maskhigh = -1; |
1688 | else | |
b1ec3c92 | 1689 | maskhigh = (HOST_WIDE_INT) -1 << (bitpos - HOST_BITS_PER_WIDE_INT); |
44037a66 | 1690 | |
b1ec3c92 CH |
1691 | if (bitpos + bitsize > HOST_BITS_PER_WIDE_INT) |
1692 | maskhigh &= ((unsigned HOST_WIDE_INT) -1 | |
1693 | >> (2 * HOST_BITS_PER_WIDE_INT - bitpos - bitsize)); | |
44037a66 TG |
1694 | else |
1695 | maskhigh = 0; | |
1696 | ||
1697 | if (complement) | |
1698 | { | |
1699 | maskhigh = ~maskhigh; | |
1700 | masklow = ~masklow; | |
1701 | } | |
1702 | ||
1703 | return immed_double_const (masklow, maskhigh, mode); | |
1704 | } | |
1705 | ||
1706 | /* Return a constant integer (CONST_INT or CONST_DOUBLE) rtx with the value | |
1707 | VALUE truncated to BITSIZE bits and then shifted left BITPOS bits. */ | |
1708 | ||
1709 | static rtx | |
1710 | lshift_value (mode, value, bitpos, bitsize) | |
1711 | enum machine_mode mode; | |
1712 | rtx value; | |
1713 | int bitpos, bitsize; | |
1714 | { | |
b1ec3c92 CH |
1715 | unsigned HOST_WIDE_INT v = INTVAL (value); |
1716 | HOST_WIDE_INT low, high; | |
44037a66 | 1717 | |
b1ec3c92 CH |
1718 | if (bitsize < HOST_BITS_PER_WIDE_INT) |
1719 | v &= ~((HOST_WIDE_INT) -1 << bitsize); | |
44037a66 | 1720 | |
b1ec3c92 | 1721 | if (bitpos < HOST_BITS_PER_WIDE_INT) |
44037a66 TG |
1722 | { |
1723 | low = v << bitpos; | |
b1ec3c92 | 1724 | high = (bitpos > 0 ? (v >> (HOST_BITS_PER_WIDE_INT - bitpos)) : 0); |
44037a66 TG |
1725 | } |
1726 | else | |
1727 | { | |
1728 | low = 0; | |
b1ec3c92 | 1729 | high = v << (bitpos - HOST_BITS_PER_WIDE_INT); |
44037a66 TG |
1730 | } |
1731 | ||
1732 | return immed_double_const (low, high, mode); | |
1733 | } | |
1734 | \f | |
1735 | /* Extract a bit field that is split across two words | |
1736 | and return an RTX for the result. | |
1737 | ||
1738 | OP0 is the REG, SUBREG or MEM rtx for the first of the two words. | |
1739 | BITSIZE is the field width; BITPOS, position of its first bit, in the word. | |
04050c69 | 1740 | UNSIGNEDP is 1 if should zero-extend the contents; else sign-extend. */ |
44037a66 TG |
1741 | |
1742 | static rtx | |
04050c69 | 1743 | extract_split_bit_field (op0, bitsize, bitpos, unsignedp) |
44037a66 | 1744 | rtx op0; |
770ae6cc RK |
1745 | unsigned HOST_WIDE_INT bitsize, bitpos; |
1746 | int unsignedp; | |
44037a66 | 1747 | { |
770ae6cc RK |
1748 | unsigned int unit; |
1749 | unsigned int bitsdone = 0; | |
c16ddde3 | 1750 | rtx result = NULL_RTX; |
06c94bce | 1751 | int first = 1; |
44037a66 | 1752 | |
4ee16841 DE |
1753 | /* Make sure UNIT isn't larger than BITS_PER_WORD, we can only handle that |
1754 | much at a time. */ | |
1755 | if (GET_CODE (op0) == REG || GET_CODE (op0) == SUBREG) | |
1756 | unit = BITS_PER_WORD; | |
1757 | else | |
04050c69 | 1758 | unit = MIN (MEM_ALIGN (op0), BITS_PER_WORD); |
4ee16841 | 1759 | |
06c94bce RS |
1760 | while (bitsdone < bitsize) |
1761 | { | |
770ae6cc | 1762 | unsigned HOST_WIDE_INT thissize; |
06c94bce | 1763 | rtx part, word; |
770ae6cc RK |
1764 | unsigned HOST_WIDE_INT thispos; |
1765 | unsigned HOST_WIDE_INT offset; | |
06c94bce RS |
1766 | |
1767 | offset = (bitpos + bitsdone) / unit; | |
1768 | thispos = (bitpos + bitsdone) % unit; | |
1769 | ||
0eb61c19 DE |
1770 | /* THISSIZE must not overrun a word boundary. Otherwise, |
1771 | extract_fixed_bit_field will call us again, and we will mutually | |
1772 | recurse forever. */ | |
1773 | thissize = MIN (bitsize - bitsdone, BITS_PER_WORD); | |
1774 | thissize = MIN (thissize, unit - thispos); | |
06c94bce RS |
1775 | |
1776 | /* If OP0 is a register, then handle OFFSET here. | |
5f57dff0 JW |
1777 | |
1778 | When handling multiword bitfields, extract_bit_field may pass | |
1779 | down a word_mode SUBREG of a larger REG for a bitfield that actually | |
1780 | crosses a word boundary. Thus, for a SUBREG, we must find | |
1781 | the current word starting from the base register. */ | |
1782 | if (GET_CODE (op0) == SUBREG) | |
1783 | { | |
ddef6bc7 JJ |
1784 | int word_offset = (SUBREG_BYTE (op0) / UNITS_PER_WORD) + offset; |
1785 | word = operand_subword_force (SUBREG_REG (op0), word_offset, | |
5f57dff0 JW |
1786 | GET_MODE (SUBREG_REG (op0))); |
1787 | offset = 0; | |
1788 | } | |
1789 | else if (GET_CODE (op0) == REG) | |
06c94bce RS |
1790 | { |
1791 | word = operand_subword_force (op0, offset, GET_MODE (op0)); | |
1792 | offset = 0; | |
1793 | } | |
1794 | else | |
1795 | word = op0; | |
1796 | ||
06c94bce | 1797 | /* Extract the parts in bit-counting order, |
0eb61c19 DE |
1798 | whose meaning is determined by BYTES_PER_UNIT. |
1799 | OFFSET is in UNITs, and UNIT is in bits. | |
1800 | extract_fixed_bit_field wants offset in bytes. */ | |
1801 | part = extract_fixed_bit_field (word_mode, word, | |
1802 | offset * unit / BITS_PER_UNIT, | |
04050c69 | 1803 | thissize, thispos, 0, 1); |
06c94bce | 1804 | bitsdone += thissize; |
44037a66 | 1805 | |
06c94bce | 1806 | /* Shift this part into place for the result. */ |
f76b9db2 ILT |
1807 | if (BYTES_BIG_ENDIAN) |
1808 | { | |
1809 | if (bitsize != bitsdone) | |
1810 | part = expand_shift (LSHIFT_EXPR, word_mode, part, | |
1811 | build_int_2 (bitsize - bitsdone, 0), 0, 1); | |
1812 | } | |
1813 | else | |
1814 | { | |
1815 | if (bitsdone != thissize) | |
1816 | part = expand_shift (LSHIFT_EXPR, word_mode, part, | |
1817 | build_int_2 (bitsdone - thissize, 0), 0, 1); | |
1818 | } | |
44037a66 | 1819 | |
06c94bce RS |
1820 | if (first) |
1821 | result = part; | |
1822 | else | |
1823 | /* Combine the parts with bitwise or. This works | |
1824 | because we extracted each part as an unsigned bit field. */ | |
1825 | result = expand_binop (word_mode, ior_optab, part, result, NULL_RTX, 1, | |
1826 | OPTAB_LIB_WIDEN); | |
1827 | ||
1828 | first = 0; | |
1829 | } | |
44037a66 TG |
1830 | |
1831 | /* Unsigned bit field: we are done. */ | |
1832 | if (unsignedp) | |
1833 | return result; | |
1834 | /* Signed bit field: sign-extend with two arithmetic shifts. */ | |
1835 | result = expand_shift (LSHIFT_EXPR, word_mode, result, | |
b1ec3c92 CH |
1836 | build_int_2 (BITS_PER_WORD - bitsize, 0), |
1837 | NULL_RTX, 0); | |
44037a66 | 1838 | return expand_shift (RSHIFT_EXPR, word_mode, result, |
b1ec3c92 | 1839 | build_int_2 (BITS_PER_WORD - bitsize, 0), NULL_RTX, 0); |
44037a66 TG |
1840 | } |
1841 | \f | |
1842 | /* Add INC into TARGET. */ | |
1843 | ||
1844 | void | |
1845 | expand_inc (target, inc) | |
1846 | rtx target, inc; | |
1847 | { | |
1848 | rtx value = expand_binop (GET_MODE (target), add_optab, | |
1849 | target, inc, | |
1850 | target, 0, OPTAB_LIB_WIDEN); | |
1851 | if (value != target) | |
1852 | emit_move_insn (target, value); | |
1853 | } | |
1854 | ||
1855 | /* Subtract DEC from TARGET. */ | |
1856 | ||
1857 | void | |
1858 | expand_dec (target, dec) | |
1859 | rtx target, dec; | |
1860 | { | |
1861 | rtx value = expand_binop (GET_MODE (target), sub_optab, | |
1862 | target, dec, | |
1863 | target, 0, OPTAB_LIB_WIDEN); | |
1864 | if (value != target) | |
1865 | emit_move_insn (target, value); | |
1866 | } | |
1867 | \f | |
1868 | /* Output a shift instruction for expression code CODE, | |
1869 | with SHIFTED being the rtx for the value to shift, | |
1870 | and AMOUNT the tree for the amount to shift by. | |
1871 | Store the result in the rtx TARGET, if that is convenient. | |
1872 | If UNSIGNEDP is nonzero, do a logical shift; otherwise, arithmetic. | |
1873 | Return the rtx for where the value is. */ | |
1874 | ||
1875 | rtx | |
1876 | expand_shift (code, mode, shifted, amount, target, unsignedp) | |
1877 | enum tree_code code; | |
b3694847 | 1878 | enum machine_mode mode; |
44037a66 TG |
1879 | rtx shifted; |
1880 | tree amount; | |
b3694847 | 1881 | rtx target; |
44037a66 TG |
1882 | int unsignedp; |
1883 | { | |
b3694847 SS |
1884 | rtx op1, temp = 0; |
1885 | int left = (code == LSHIFT_EXPR || code == LROTATE_EXPR); | |
1886 | int rotate = (code == LROTATE_EXPR || code == RROTATE_EXPR); | |
44037a66 TG |
1887 | int try; |
1888 | ||
1889 | /* Previously detected shift-counts computed by NEGATE_EXPR | |
1890 | and shifted in the other direction; but that does not work | |
1891 | on all machines. */ | |
1892 | ||
b1ec3c92 | 1893 | op1 = expand_expr (amount, NULL_RTX, VOIDmode, 0); |
44037a66 | 1894 | |
1433f0f9 | 1895 | #ifdef SHIFT_COUNT_TRUNCATED |
166cdf4a RH |
1896 | if (SHIFT_COUNT_TRUNCATED) |
1897 | { | |
1898 | if (GET_CODE (op1) == CONST_INT | |
c84e2712 KG |
1899 | && ((unsigned HOST_WIDE_INT) INTVAL (op1) >= |
1900 | (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode))) | |
166cdf4a RH |
1901 | op1 = GEN_INT ((unsigned HOST_WIDE_INT) INTVAL (op1) |
1902 | % GET_MODE_BITSIZE (mode)); | |
1903 | else if (GET_CODE (op1) == SUBREG | |
ddef6bc7 | 1904 | && SUBREG_BYTE (op1) == 0) |
166cdf4a RH |
1905 | op1 = SUBREG_REG (op1); |
1906 | } | |
2ab0a5c4 TG |
1907 | #endif |
1908 | ||
44037a66 TG |
1909 | if (op1 == const0_rtx) |
1910 | return shifted; | |
1911 | ||
1912 | for (try = 0; temp == 0 && try < 3; try++) | |
1913 | { | |
1914 | enum optab_methods methods; | |
1915 | ||
1916 | if (try == 0) | |
1917 | methods = OPTAB_DIRECT; | |
1918 | else if (try == 1) | |
1919 | methods = OPTAB_WIDEN; | |
1920 | else | |
1921 | methods = OPTAB_LIB_WIDEN; | |
1922 | ||
1923 | if (rotate) | |
1924 | { | |
1925 | /* Widening does not work for rotation. */ | |
1926 | if (methods == OPTAB_WIDEN) | |
1927 | continue; | |
1928 | else if (methods == OPTAB_LIB_WIDEN) | |
cbec710e | 1929 | { |
39e71615 | 1930 | /* If we have been unable to open-code this by a rotation, |
cbec710e RK |
1931 | do it as the IOR of two shifts. I.e., to rotate A |
1932 | by N bits, compute (A << N) | ((unsigned) A >> (C - N)) | |
1933 | where C is the bitsize of A. | |
1934 | ||
1935 | It is theoretically possible that the target machine might | |
1936 | not be able to perform either shift and hence we would | |
1937 | be making two libcalls rather than just the one for the | |
1938 | shift (similarly if IOR could not be done). We will allow | |
1939 | this extremely unlikely lossage to avoid complicating the | |
1940 | code below. */ | |
1941 | ||
39e71615 RK |
1942 | rtx subtarget = target == shifted ? 0 : target; |
1943 | rtx temp1; | |
1944 | tree type = TREE_TYPE (amount); | |
1945 | tree new_amount = make_tree (type, op1); | |
1946 | tree other_amount | |
1947 | = fold (build (MINUS_EXPR, type, | |
1948 | convert (type, | |
1949 | build_int_2 (GET_MODE_BITSIZE (mode), | |
1950 | 0)), | |
1951 | amount)); | |
1952 | ||
1953 | shifted = force_reg (mode, shifted); | |
1954 | ||
1955 | temp = expand_shift (left ? LSHIFT_EXPR : RSHIFT_EXPR, | |
1956 | mode, shifted, new_amount, subtarget, 1); | |
1957 | temp1 = expand_shift (left ? RSHIFT_EXPR : LSHIFT_EXPR, | |
1958 | mode, shifted, other_amount, 0, 1); | |
1959 | return expand_binop (mode, ior_optab, temp, temp1, target, | |
1960 | unsignedp, methods); | |
cbec710e | 1961 | } |
44037a66 TG |
1962 | |
1963 | temp = expand_binop (mode, | |
1964 | left ? rotl_optab : rotr_optab, | |
1965 | shifted, op1, target, unsignedp, methods); | |
cbec710e RK |
1966 | |
1967 | /* If we don't have the rotate, but we are rotating by a constant | |
1968 | that is in range, try a rotate in the opposite direction. */ | |
1969 | ||
1970 | if (temp == 0 && GET_CODE (op1) == CONST_INT | |
da920570 ZW |
1971 | && INTVAL (op1) > 0 |
1972 | && (unsigned int) INTVAL (op1) < GET_MODE_BITSIZE (mode)) | |
cbec710e RK |
1973 | temp = expand_binop (mode, |
1974 | left ? rotr_optab : rotl_optab, | |
1975 | shifted, | |
1976 | GEN_INT (GET_MODE_BITSIZE (mode) | |
1977 | - INTVAL (op1)), | |
1978 | target, unsignedp, methods); | |
44037a66 TG |
1979 | } |
1980 | else if (unsignedp) | |
a34958c9 RK |
1981 | temp = expand_binop (mode, |
1982 | left ? ashl_optab : lshr_optab, | |
1983 | shifted, op1, target, unsignedp, methods); | |
44037a66 TG |
1984 | |
1985 | /* Do arithmetic shifts. | |
1986 | Also, if we are going to widen the operand, we can just as well | |
1987 | use an arithmetic right-shift instead of a logical one. */ | |
1988 | if (temp == 0 && ! rotate | |
1989 | && (! unsignedp || (! left && methods == OPTAB_WIDEN))) | |
1990 | { | |
1991 | enum optab_methods methods1 = methods; | |
1992 | ||
1993 | /* If trying to widen a log shift to an arithmetic shift, | |
1994 | don't accept an arithmetic shift of the same size. */ | |
1995 | if (unsignedp) | |
1996 | methods1 = OPTAB_MUST_WIDEN; | |
1997 | ||
1998 | /* Arithmetic shift */ | |
1999 | ||
2000 | temp = expand_binop (mode, | |
2001 | left ? ashl_optab : ashr_optab, | |
2002 | shifted, op1, target, unsignedp, methods1); | |
2003 | } | |
2004 | ||
711a5e64 RK |
2005 | /* We used to try extzv here for logical right shifts, but that was |
2006 | only useful for one machine, the VAX, and caused poor code | |
2007 | generation there for lshrdi3, so the code was deleted and a | |
2008 | define_expand for lshrsi3 was added to vax.md. */ | |
44037a66 TG |
2009 | } |
2010 | ||
2011 | if (temp == 0) | |
2012 | abort (); | |
2013 | return temp; | |
2014 | } | |
2015 | \f | |
b385aeda | 2016 | enum alg_code { alg_zero, alg_m, alg_shift, |
b2fb324c | 2017 | alg_add_t_m2, alg_sub_t_m2, |
7963ac37 RK |
2018 | alg_add_factor, alg_sub_factor, |
2019 | alg_add_t2_m, alg_sub_t2_m, | |
b385aeda | 2020 | alg_add, alg_subtract, alg_factor, alg_shiftop }; |
44037a66 TG |
2021 | |
2022 | /* This structure records a sequence of operations. | |
2023 | `ops' is the number of operations recorded. | |
2024 | `cost' is their total cost. | |
2025 | The operations are stored in `op' and the corresponding | |
b385aeda RK |
2026 | logarithms of the integer coefficients in `log'. |
2027 | ||
44037a66 | 2028 | These are the operations: |
b385aeda RK |
2029 | alg_zero total := 0; |
2030 | alg_m total := multiplicand; | |
b2fb324c | 2031 | alg_shift total := total * coeff |
7963ac37 RK |
2032 | alg_add_t_m2 total := total + multiplicand * coeff; |
2033 | alg_sub_t_m2 total := total - multiplicand * coeff; | |
2034 | alg_add_factor total := total * coeff + total; | |
2035 | alg_sub_factor total := total * coeff - total; | |
2036 | alg_add_t2_m total := total * coeff + multiplicand; | |
2037 | alg_sub_t2_m total := total * coeff - multiplicand; | |
b385aeda RK |
2038 | |
2039 | The first operand must be either alg_zero or alg_m. */ | |
44037a66 | 2040 | |
44037a66 TG |
2041 | struct algorithm |
2042 | { | |
7963ac37 RK |
2043 | short cost; |
2044 | short ops; | |
b385aeda RK |
2045 | /* The size of the OP and LOG fields are not directly related to the |
2046 | word size, but the worst-case algorithms will be if we have few | |
2047 | consecutive ones or zeros, i.e., a multiplicand like 10101010101... | |
2048 | In that case we will generate shift-by-2, add, shift-by-2, add,..., | |
2049 | in total wordsize operations. */ | |
44037a66 | 2050 | enum alg_code op[MAX_BITS_PER_WORD]; |
b385aeda | 2051 | char log[MAX_BITS_PER_WORD]; |
44037a66 TG |
2052 | }; |
2053 | ||
711d877c KG |
2054 | static void synth_mult PARAMS ((struct algorithm *, |
2055 | unsigned HOST_WIDE_INT, | |
2056 | int)); | |
2057 | static unsigned HOST_WIDE_INT choose_multiplier PARAMS ((unsigned HOST_WIDE_INT, | |
2058 | int, int, | |
2059 | unsigned HOST_WIDE_INT *, | |
2060 | int *, int *)); | |
2061 | static unsigned HOST_WIDE_INT invert_mod2n PARAMS ((unsigned HOST_WIDE_INT, | |
2062 | int)); | |
44037a66 | 2063 | /* Compute and return the best algorithm for multiplying by T. |
7963ac37 RK |
2064 | The algorithm must cost less than cost_limit |
2065 | If retval.cost >= COST_LIMIT, no algorithm was found and all | |
2066 | other field of the returned struct are undefined. */ | |
44037a66 | 2067 | |
819126a6 RK |
2068 | static void |
2069 | synth_mult (alg_out, t, cost_limit) | |
2070 | struct algorithm *alg_out; | |
b1ec3c92 | 2071 | unsigned HOST_WIDE_INT t; |
7963ac37 | 2072 | int cost_limit; |
44037a66 | 2073 | { |
b2fb324c | 2074 | int m; |
52786026 | 2075 | struct algorithm *alg_in, *best_alg; |
c84e2712 | 2076 | int cost; |
b2fb324c | 2077 | unsigned HOST_WIDE_INT q; |
44037a66 | 2078 | |
7963ac37 RK |
2079 | /* Indicate that no algorithm is yet found. If no algorithm |
2080 | is found, this value will be returned and indicate failure. */ | |
819126a6 | 2081 | alg_out->cost = cost_limit; |
44037a66 | 2082 | |
b2fb324c | 2083 | if (cost_limit <= 0) |
819126a6 | 2084 | return; |
44037a66 | 2085 | |
b385aeda RK |
2086 | /* t == 1 can be done in zero cost. */ |
2087 | if (t == 1) | |
b2fb324c | 2088 | { |
819126a6 RK |
2089 | alg_out->ops = 1; |
2090 | alg_out->cost = 0; | |
2091 | alg_out->op[0] = alg_m; | |
2092 | return; | |
b2fb324c RK |
2093 | } |
2094 | ||
b385aeda RK |
2095 | /* t == 0 sometimes has a cost. If it does and it exceeds our limit, |
2096 | fail now. */ | |
819126a6 | 2097 | if (t == 0) |
b385aeda RK |
2098 | { |
2099 | if (zero_cost >= cost_limit) | |
819126a6 | 2100 | return; |
b385aeda RK |
2101 | else |
2102 | { | |
819126a6 RK |
2103 | alg_out->ops = 1; |
2104 | alg_out->cost = zero_cost; | |
2105 | alg_out->op[0] = alg_zero; | |
2106 | return; | |
b385aeda RK |
2107 | } |
2108 | } | |
2109 | ||
52786026 RK |
2110 | /* We'll be needing a couple extra algorithm structures now. */ |
2111 | ||
2112 | alg_in = (struct algorithm *)alloca (sizeof (struct algorithm)); | |
2113 | best_alg = (struct algorithm *)alloca (sizeof (struct algorithm)); | |
2114 | ||
b385aeda RK |
2115 | /* If we have a group of zero bits at the low-order part of T, try |
2116 | multiplying by the remaining bits and then doing a shift. */ | |
2117 | ||
b2fb324c | 2118 | if ((t & 1) == 0) |
44037a66 | 2119 | { |
b2fb324c | 2120 | m = floor_log2 (t & -t); /* m = number of low zero bits */ |
02a65aef | 2121 | if (m < BITS_PER_WORD) |
44037a66 | 2122 | { |
02a65aef R |
2123 | q = t >> m; |
2124 | cost = shift_cost[m]; | |
2125 | synth_mult (alg_in, q, cost_limit - cost); | |
2126 | ||
2127 | cost += alg_in->cost; | |
2128 | if (cost < cost_limit) | |
2129 | { | |
2130 | struct algorithm *x; | |
2131 | x = alg_in, alg_in = best_alg, best_alg = x; | |
2132 | best_alg->log[best_alg->ops] = m; | |
2133 | best_alg->op[best_alg->ops] = alg_shift; | |
2134 | cost_limit = cost; | |
2135 | } | |
819126a6 RK |
2136 | } |
2137 | } | |
2138 | ||
2139 | /* If we have an odd number, add or subtract one. */ | |
2140 | if ((t & 1) != 0) | |
2141 | { | |
2142 | unsigned HOST_WIDE_INT w; | |
2143 | ||
2144 | for (w = 1; (w & t) != 0; w <<= 1) | |
2145 | ; | |
31031edd JL |
2146 | /* If T was -1, then W will be zero after the loop. This is another |
2147 | case where T ends with ...111. Handling this with (T + 1) and | |
2148 | subtract 1 produces slightly better code and results in algorithm | |
2149 | selection much faster than treating it like the ...0111 case | |
2150 | below. */ | |
2151 | if (w == 0 | |
2152 | || (w > 2 | |
2153 | /* Reject the case where t is 3. | |
2154 | Thus we prefer addition in that case. */ | |
2155 | && t != 3)) | |
819126a6 RK |
2156 | { |
2157 | /* T ends with ...111. Multiply by (T + 1) and subtract 1. */ | |
2158 | ||
2159 | cost = add_cost; | |
2160 | synth_mult (alg_in, t + 1, cost_limit - cost); | |
b2fb324c RK |
2161 | |
2162 | cost += alg_in->cost; | |
819126a6 | 2163 | if (cost < cost_limit) |
44037a66 | 2164 | { |
b2fb324c RK |
2165 | struct algorithm *x; |
2166 | x = alg_in, alg_in = best_alg, best_alg = x; | |
819126a6 RK |
2167 | best_alg->log[best_alg->ops] = 0; |
2168 | best_alg->op[best_alg->ops] = alg_sub_t_m2; | |
2169 | cost_limit = cost; | |
44037a66 | 2170 | } |
44037a66 | 2171 | } |
819126a6 RK |
2172 | else |
2173 | { | |
2174 | /* T ends with ...01 or ...011. Multiply by (T - 1) and add 1. */ | |
44037a66 | 2175 | |
819126a6 RK |
2176 | cost = add_cost; |
2177 | synth_mult (alg_in, t - 1, cost_limit - cost); | |
2178 | ||
2179 | cost += alg_in->cost; | |
2180 | if (cost < cost_limit) | |
2181 | { | |
2182 | struct algorithm *x; | |
2183 | x = alg_in, alg_in = best_alg, best_alg = x; | |
2184 | best_alg->log[best_alg->ops] = 0; | |
2185 | best_alg->op[best_alg->ops] = alg_add_t_m2; | |
2186 | cost_limit = cost; | |
2187 | } | |
2188 | } | |
2189 | } | |
63610db9 | 2190 | |
44037a66 | 2191 | /* Look for factors of t of the form |
7963ac37 | 2192 | t = q(2**m +- 1), 2 <= m <= floor(log2(t - 1)). |
44037a66 | 2193 | If we find such a factor, we can multiply by t using an algorithm that |
7963ac37 | 2194 | multiplies by q, shift the result by m and add/subtract it to itself. |
44037a66 | 2195 | |
7963ac37 RK |
2196 | We search for large factors first and loop down, even if large factors |
2197 | are less probable than small; if we find a large factor we will find a | |
2198 | good sequence quickly, and therefore be able to prune (by decreasing | |
2199 | COST_LIMIT) the search. */ | |
2200 | ||
2201 | for (m = floor_log2 (t - 1); m >= 2; m--) | |
44037a66 | 2202 | { |
7963ac37 | 2203 | unsigned HOST_WIDE_INT d; |
44037a66 | 2204 | |
7963ac37 | 2205 | d = ((unsigned HOST_WIDE_INT) 1 << m) + 1; |
02a65aef | 2206 | if (t % d == 0 && t > d && m < BITS_PER_WORD) |
44037a66 | 2207 | { |
b385aeda | 2208 | cost = MIN (shiftadd_cost[m], add_cost + shift_cost[m]); |
819126a6 | 2209 | synth_mult (alg_in, t / d, cost_limit - cost); |
44037a66 | 2210 | |
7963ac37 | 2211 | cost += alg_in->cost; |
819126a6 | 2212 | if (cost < cost_limit) |
44037a66 | 2213 | { |
7963ac37 RK |
2214 | struct algorithm *x; |
2215 | x = alg_in, alg_in = best_alg, best_alg = x; | |
b385aeda | 2216 | best_alg->log[best_alg->ops] = m; |
819126a6 RK |
2217 | best_alg->op[best_alg->ops] = alg_add_factor; |
2218 | cost_limit = cost; | |
44037a66 | 2219 | } |
c0b262c1 TG |
2220 | /* Other factors will have been taken care of in the recursion. */ |
2221 | break; | |
44037a66 TG |
2222 | } |
2223 | ||
7963ac37 | 2224 | d = ((unsigned HOST_WIDE_INT) 1 << m) - 1; |
02a65aef | 2225 | if (t % d == 0 && t > d && m < BITS_PER_WORD) |
44037a66 | 2226 | { |
b385aeda | 2227 | cost = MIN (shiftsub_cost[m], add_cost + shift_cost[m]); |
819126a6 | 2228 | synth_mult (alg_in, t / d, cost_limit - cost); |
44037a66 | 2229 | |
7963ac37 | 2230 | cost += alg_in->cost; |
819126a6 | 2231 | if (cost < cost_limit) |
44037a66 | 2232 | { |
7963ac37 RK |
2233 | struct algorithm *x; |
2234 | x = alg_in, alg_in = best_alg, best_alg = x; | |
b385aeda | 2235 | best_alg->log[best_alg->ops] = m; |
819126a6 RK |
2236 | best_alg->op[best_alg->ops] = alg_sub_factor; |
2237 | cost_limit = cost; | |
44037a66 | 2238 | } |
c0b262c1 | 2239 | break; |
44037a66 TG |
2240 | } |
2241 | } | |
2242 | ||
7963ac37 RK |
2243 | /* Try shift-and-add (load effective address) instructions, |
2244 | i.e. do a*3, a*5, a*9. */ | |
2245 | if ((t & 1) != 0) | |
2246 | { | |
7963ac37 RK |
2247 | q = t - 1; |
2248 | q = q & -q; | |
2249 | m = exact_log2 (q); | |
02a65aef | 2250 | if (m >= 0 && m < BITS_PER_WORD) |
b385aeda | 2251 | { |
5eebe2eb | 2252 | cost = shiftadd_cost[m]; |
819126a6 | 2253 | synth_mult (alg_in, (t - 1) >> m, cost_limit - cost); |
5eebe2eb RK |
2254 | |
2255 | cost += alg_in->cost; | |
819126a6 | 2256 | if (cost < cost_limit) |
5eebe2eb RK |
2257 | { |
2258 | struct algorithm *x; | |
2259 | x = alg_in, alg_in = best_alg, best_alg = x; | |
2260 | best_alg->log[best_alg->ops] = m; | |
819126a6 RK |
2261 | best_alg->op[best_alg->ops] = alg_add_t2_m; |
2262 | cost_limit = cost; | |
5eebe2eb | 2263 | } |
7963ac37 | 2264 | } |
44037a66 | 2265 | |
7963ac37 RK |
2266 | q = t + 1; |
2267 | q = q & -q; | |
2268 | m = exact_log2 (q); | |
02a65aef | 2269 | if (m >= 0 && m < BITS_PER_WORD) |
b385aeda | 2270 | { |
5eebe2eb | 2271 | cost = shiftsub_cost[m]; |
819126a6 | 2272 | synth_mult (alg_in, (t + 1) >> m, cost_limit - cost); |
5eebe2eb RK |
2273 | |
2274 | cost += alg_in->cost; | |
819126a6 | 2275 | if (cost < cost_limit) |
5eebe2eb RK |
2276 | { |
2277 | struct algorithm *x; | |
2278 | x = alg_in, alg_in = best_alg, best_alg = x; | |
2279 | best_alg->log[best_alg->ops] = m; | |
819126a6 RK |
2280 | best_alg->op[best_alg->ops] = alg_sub_t2_m; |
2281 | cost_limit = cost; | |
5eebe2eb | 2282 | } |
7963ac37 RK |
2283 | } |
2284 | } | |
44037a66 | 2285 | |
819126a6 RK |
2286 | /* If cost_limit has not decreased since we stored it in alg_out->cost, |
2287 | we have not found any algorithm. */ | |
2288 | if (cost_limit == alg_out->cost) | |
2289 | return; | |
2290 | ||
52786026 RK |
2291 | /* If we are getting a too long sequence for `struct algorithm' |
2292 | to record, make this search fail. */ | |
2293 | if (best_alg->ops == MAX_BITS_PER_WORD) | |
2294 | return; | |
2295 | ||
819126a6 RK |
2296 | /* Copy the algorithm from temporary space to the space at alg_out. |
2297 | We avoid using structure assignment because the majority of | |
2298 | best_alg is normally undefined, and this is a critical function. */ | |
2299 | alg_out->ops = best_alg->ops + 1; | |
2300 | alg_out->cost = cost_limit; | |
4e135bdd KG |
2301 | memcpy (alg_out->op, best_alg->op, |
2302 | alg_out->ops * sizeof *alg_out->op); | |
2303 | memcpy (alg_out->log, best_alg->log, | |
2304 | alg_out->ops * sizeof *alg_out->log); | |
44037a66 TG |
2305 | } |
2306 | \f | |
2307 | /* Perform a multiplication and return an rtx for the result. | |
2308 | MODE is mode of value; OP0 and OP1 are what to multiply (rtx's); | |
2309 | TARGET is a suggestion for where to store the result (an rtx). | |
2310 | ||
2311 | We check specially for a constant integer as OP1. | |
2312 | If you want this check for OP0 as well, then before calling | |
2313 | you should swap the two operands if OP0 would be constant. */ | |
2314 | ||
2315 | rtx | |
2316 | expand_mult (mode, op0, op1, target, unsignedp) | |
2317 | enum machine_mode mode; | |
b3694847 | 2318 | rtx op0, op1, target; |
44037a66 TG |
2319 | int unsignedp; |
2320 | { | |
2321 | rtx const_op1 = op1; | |
2322 | ||
ceb1d268 JW |
2323 | /* synth_mult does an `unsigned int' multiply. As long as the mode is |
2324 | less than or equal in size to `unsigned int' this doesn't matter. | |
2325 | If the mode is larger than `unsigned int', then synth_mult works only | |
2326 | if the constant value exactly fits in an `unsigned int' without any | |
2327 | truncation. This means that multiplying by negative values does | |
2328 | not work; results are off by 2^32 on a 32 bit machine. */ | |
2329 | ||
44037a66 TG |
2330 | /* If we are multiplying in DImode, it may still be a win |
2331 | to try to work with shifts and adds. */ | |
2332 | if (GET_CODE (op1) == CONST_DOUBLE | |
2333 | && GET_MODE_CLASS (GET_MODE (op1)) == MODE_INT | |
ceb1d268 JW |
2334 | && HOST_BITS_PER_INT >= BITS_PER_WORD |
2335 | && CONST_DOUBLE_HIGH (op1) == 0) | |
2336 | const_op1 = GEN_INT (CONST_DOUBLE_LOW (op1)); | |
2337 | else if (HOST_BITS_PER_INT < GET_MODE_BITSIZE (mode) | |
2338 | && GET_CODE (op1) == CONST_INT | |
2339 | && INTVAL (op1) < 0) | |
2340 | const_op1 = 0; | |
44037a66 | 2341 | |
66c1f88e RS |
2342 | /* We used to test optimize here, on the grounds that it's better to |
2343 | produce a smaller program when -O is not used. | |
2344 | But this causes such a terrible slowdown sometimes | |
2345 | that it seems better to use synth_mult always. */ | |
b385aeda | 2346 | |
91ce572a CC |
2347 | if (const_op1 && GET_CODE (const_op1) == CONST_INT |
2348 | && (unsignedp || ! flag_trapv)) | |
44037a66 TG |
2349 | { |
2350 | struct algorithm alg; | |
55c2d311 | 2351 | struct algorithm alg2; |
7963ac37 | 2352 | HOST_WIDE_INT val = INTVAL (op1); |
b385aeda RK |
2353 | HOST_WIDE_INT val_so_far; |
2354 | rtx insn; | |
819126a6 | 2355 | int mult_cost; |
55c2d311 | 2356 | enum {basic_variant, negate_variant, add_variant} variant = basic_variant; |
44037a66 | 2357 | |
b972dd02 JH |
2358 | /* op0 must be register to make mult_cost match the precomputed |
2359 | shiftadd_cost array. */ | |
2360 | op0 = force_reg (mode, op0); | |
2361 | ||
55c2d311 TG |
2362 | /* Try to do the computation three ways: multiply by the negative of OP1 |
2363 | and then negate, do the multiplication directly, or do multiplication | |
2364 | by OP1 - 1. */ | |
44037a66 | 2365 | |
38a448ca | 2366 | mult_cost = rtx_cost (gen_rtx_MULT (mode, op0, op1), SET); |
c0b262c1 | 2367 | mult_cost = MIN (12 * add_cost, mult_cost); |
819126a6 RK |
2368 | |
2369 | synth_mult (&alg, val, mult_cost); | |
ceb1d268 JW |
2370 | |
2371 | /* This works only if the inverted value actually fits in an | |
2372 | `unsigned int' */ | |
2373 | if (HOST_BITS_PER_INT >= GET_MODE_BITSIZE (mode)) | |
2374 | { | |
2375 | synth_mult (&alg2, - val, | |
2376 | (alg.cost < mult_cost ? alg.cost : mult_cost) - negate_cost); | |
2377 | if (alg2.cost + negate_cost < alg.cost) | |
2378 | alg = alg2, variant = negate_variant; | |
2379 | } | |
44037a66 | 2380 | |
55c2d311 | 2381 | /* This proves very useful for division-by-constant. */ |
98310eaa RK |
2382 | synth_mult (&alg2, val - 1, |
2383 | (alg.cost < mult_cost ? alg.cost : mult_cost) - add_cost); | |
55c2d311 TG |
2384 | if (alg2.cost + add_cost < alg.cost) |
2385 | alg = alg2, variant = add_variant; | |
44037a66 | 2386 | |
7963ac37 | 2387 | if (alg.cost < mult_cost) |
44037a66 | 2388 | { |
b2fb324c | 2389 | /* We found something cheaper than a multiply insn. */ |
7963ac37 | 2390 | int opno; |
44037a66 | 2391 | rtx accum, tem; |
23cb454a | 2392 | enum machine_mode nmode; |
44037a66 TG |
2393 | |
2394 | op0 = protect_from_queue (op0, 0); | |
2395 | ||
2396 | /* Avoid referencing memory over and over. | |
2397 | For speed, but also for correctness when mem is volatile. */ | |
2398 | if (GET_CODE (op0) == MEM) | |
2399 | op0 = force_reg (mode, op0); | |
2400 | ||
b385aeda RK |
2401 | /* ACCUM starts out either as OP0 or as a zero, depending on |
2402 | the first operation. */ | |
2403 | ||
2404 | if (alg.op[0] == alg_zero) | |
44037a66 | 2405 | { |
b385aeda RK |
2406 | accum = copy_to_mode_reg (mode, const0_rtx); |
2407 | val_so_far = 0; | |
2408 | } | |
2409 | else if (alg.op[0] == alg_m) | |
2410 | { | |
819126a6 | 2411 | accum = copy_to_mode_reg (mode, op0); |
b385aeda | 2412 | val_so_far = 1; |
44037a66 | 2413 | } |
b385aeda RK |
2414 | else |
2415 | abort (); | |
7963ac37 RK |
2416 | |
2417 | for (opno = 1; opno < alg.ops; opno++) | |
44037a66 | 2418 | { |
b385aeda | 2419 | int log = alg.log[opno]; |
c0a08574 RK |
2420 | int preserve = preserve_subexpressions_p (); |
2421 | rtx shift_subtarget = preserve ? 0 : accum; | |
98310eaa RK |
2422 | rtx add_target |
2423 | = (opno == alg.ops - 1 && target != 0 && variant != add_variant | |
9ec36da5 JL |
2424 | && ! preserve) |
2425 | ? target : 0; | |
c0a08574 RK |
2426 | rtx accum_target = preserve ? 0 : accum; |
2427 | ||
44037a66 TG |
2428 | switch (alg.op[opno]) |
2429 | { | |
b2fb324c RK |
2430 | case alg_shift: |
2431 | accum = expand_shift (LSHIFT_EXPR, mode, accum, | |
2432 | build_int_2 (log, 0), NULL_RTX, 0); | |
b385aeda | 2433 | val_so_far <<= log; |
b2fb324c RK |
2434 | break; |
2435 | ||
7963ac37 | 2436 | case alg_add_t_m2: |
b385aeda RK |
2437 | tem = expand_shift (LSHIFT_EXPR, mode, op0, |
2438 | build_int_2 (log, 0), NULL_RTX, 0); | |
38a448ca | 2439 | accum = force_operand (gen_rtx_PLUS (mode, accum, tem), |
c5c76735 JL |
2440 | add_target |
2441 | ? add_target : accum_target); | |
b385aeda | 2442 | val_so_far += (HOST_WIDE_INT) 1 << log; |
44037a66 TG |
2443 | break; |
2444 | ||
7963ac37 | 2445 | case alg_sub_t_m2: |
b385aeda RK |
2446 | tem = expand_shift (LSHIFT_EXPR, mode, op0, |
2447 | build_int_2 (log, 0), NULL_RTX, 0); | |
38a448ca | 2448 | accum = force_operand (gen_rtx_MINUS (mode, accum, tem), |
c5c76735 JL |
2449 | add_target |
2450 | ? add_target : accum_target); | |
b385aeda | 2451 | val_so_far -= (HOST_WIDE_INT) 1 << log; |
7963ac37 | 2452 | break; |
44037a66 | 2453 | |
7963ac37 RK |
2454 | case alg_add_t2_m: |
2455 | accum = expand_shift (LSHIFT_EXPR, mode, accum, | |
c0a08574 RK |
2456 | build_int_2 (log, 0), shift_subtarget, |
2457 | 0); | |
38a448ca | 2458 | accum = force_operand (gen_rtx_PLUS (mode, accum, op0), |
c5c76735 JL |
2459 | add_target |
2460 | ? add_target : accum_target); | |
b385aeda | 2461 | val_so_far = (val_so_far << log) + 1; |
44037a66 TG |
2462 | break; |
2463 | ||
7963ac37 RK |
2464 | case alg_sub_t2_m: |
2465 | accum = expand_shift (LSHIFT_EXPR, mode, accum, | |
c0a08574 RK |
2466 | build_int_2 (log, 0), shift_subtarget, |
2467 | 0); | |
38a448ca | 2468 | accum = force_operand (gen_rtx_MINUS (mode, accum, op0), |
c5c76735 JL |
2469 | add_target |
2470 | ? add_target : accum_target); | |
b385aeda | 2471 | val_so_far = (val_so_far << log) - 1; |
7963ac37 RK |
2472 | break; |
2473 | ||
2474 | case alg_add_factor: | |
44037a66 | 2475 | tem = expand_shift (LSHIFT_EXPR, mode, accum, |
b1ec3c92 | 2476 | build_int_2 (log, 0), NULL_RTX, 0); |
38a448ca | 2477 | accum = force_operand (gen_rtx_PLUS (mode, accum, tem), |
c5c76735 JL |
2478 | add_target |
2479 | ? add_target : accum_target); | |
b385aeda | 2480 | val_so_far += val_so_far << log; |
7963ac37 | 2481 | break; |
44037a66 | 2482 | |
7963ac37 RK |
2483 | case alg_sub_factor: |
2484 | tem = expand_shift (LSHIFT_EXPR, mode, accum, | |
2485 | build_int_2 (log, 0), NULL_RTX, 0); | |
38a448ca | 2486 | accum = force_operand (gen_rtx_MINUS (mode, tem, accum), |
c0a08574 RK |
2487 | (add_target ? add_target |
2488 | : preserve ? 0 : tem)); | |
b385aeda | 2489 | val_so_far = (val_so_far << log) - val_so_far; |
7963ac37 | 2490 | break; |
44037a66 | 2491 | |
b385aeda | 2492 | default: |
6d649d26 | 2493 | abort (); |
b385aeda | 2494 | } |
44037a66 | 2495 | |
b385aeda | 2496 | /* Write a REG_EQUAL note on the last insn so that we can cse |
23cb454a RK |
2497 | multiplication sequences. Note that if ACCUM is a SUBREG, |
2498 | we've set the inner register and must properly indicate | |
2499 | that. */ | |
2500 | ||
2501 | tem = op0, nmode = mode; | |
2502 | if (GET_CODE (accum) == SUBREG) | |
2503 | { | |
2504 | nmode = GET_MODE (SUBREG_REG (accum)); | |
2505 | tem = gen_lowpart (nmode, op0); | |
2506 | } | |
44037a66 | 2507 | |
b385aeda | 2508 | insn = get_last_insn (); |
7e5bda2c AM |
2509 | set_unique_reg_note (insn, |
2510 | REG_EQUAL, | |
23cb454a | 2511 | gen_rtx_MULT (nmode, tem, |
7e5bda2c | 2512 | GEN_INT (val_so_far))); |
b385aeda | 2513 | } |
44037a66 | 2514 | |
55c2d311 | 2515 | if (variant == negate_variant) |
44037a66 | 2516 | { |
b385aeda RK |
2517 | val_so_far = - val_so_far; |
2518 | accum = expand_unop (mode, neg_optab, accum, target, 0); | |
44037a66 | 2519 | } |
55c2d311 TG |
2520 | else if (variant == add_variant) |
2521 | { | |
2522 | val_so_far = val_so_far + 1; | |
38a448ca | 2523 | accum = force_operand (gen_rtx_PLUS (mode, accum, op0), target); |
55c2d311 | 2524 | } |
44037a66 | 2525 | |
b385aeda RK |
2526 | if (val != val_so_far) |
2527 | abort (); | |
2528 | ||
2529 | return accum; | |
44037a66 TG |
2530 | } |
2531 | } | |
2532 | ||
819126a6 RK |
2533 | /* This used to use umul_optab if unsigned, but for non-widening multiply |
2534 | there is no difference between signed and unsigned. */ | |
91ce572a CC |
2535 | op0 = expand_binop (mode, |
2536 | ! unsignedp | |
2537 | && flag_trapv && (GET_MODE_CLASS(mode) == MODE_INT) | |
2538 | ? smulv_optab : smul_optab, | |
44037a66 TG |
2539 | op0, op1, target, unsignedp, OPTAB_LIB_WIDEN); |
2540 | if (op0 == 0) | |
2541 | abort (); | |
2542 | return op0; | |
2543 | } | |
2544 | \f | |
55c2d311 TG |
2545 | /* Return the smallest n such that 2**n >= X. */ |
2546 | ||
2547 | int | |
2548 | ceil_log2 (x) | |
2549 | unsigned HOST_WIDE_INT x; | |
2550 | { | |
2551 | return floor_log2 (x - 1) + 1; | |
2552 | } | |
2553 | ||
2554 | /* Choose a minimal N + 1 bit approximation to 1/D that can be used to | |
2555 | replace division by D, and put the least significant N bits of the result | |
2556 | in *MULTIPLIER_PTR and return the most significant bit. | |
2557 | ||
2558 | The width of operations is N (should be <= HOST_BITS_PER_WIDE_INT), the | |
2559 | needed precision is in PRECISION (should be <= N). | |
2560 | ||
2561 | PRECISION should be as small as possible so this function can choose | |
2562 | multiplier more freely. | |
2563 | ||
2564 | The rounded-up logarithm of D is placed in *lgup_ptr. A shift count that | |
2565 | is to be used for a final right shift is placed in *POST_SHIFT_PTR. | |
2566 | ||
2567 | Using this function, x/D will be equal to (x * m) >> (*POST_SHIFT_PTR), | |
2568 | where m is the full HOST_BITS_PER_WIDE_INT + 1 bit multiplier. */ | |
2569 | ||
2570 | static | |
2571 | unsigned HOST_WIDE_INT | |
2572 | choose_multiplier (d, n, precision, multiplier_ptr, post_shift_ptr, lgup_ptr) | |
2573 | unsigned HOST_WIDE_INT d; | |
2574 | int n; | |
2575 | int precision; | |
2576 | unsigned HOST_WIDE_INT *multiplier_ptr; | |
2577 | int *post_shift_ptr; | |
2578 | int *lgup_ptr; | |
2579 | { | |
f9e158c3 JM |
2580 | HOST_WIDE_INT mhigh_hi, mlow_hi; |
2581 | unsigned HOST_WIDE_INT mhigh_lo, mlow_lo; | |
55c2d311 TG |
2582 | int lgup, post_shift; |
2583 | int pow, pow2; | |
f9e158c3 JM |
2584 | unsigned HOST_WIDE_INT nl, dummy1; |
2585 | HOST_WIDE_INT nh, dummy2; | |
55c2d311 TG |
2586 | |
2587 | /* lgup = ceil(log2(divisor)); */ | |
2588 | lgup = ceil_log2 (d); | |
2589 | ||
2590 | if (lgup > n) | |
2591 | abort (); | |
2592 | ||
2593 | pow = n + lgup; | |
2594 | pow2 = n + lgup - precision; | |
2595 | ||
2596 | if (pow == 2 * HOST_BITS_PER_WIDE_INT) | |
2597 | { | |
2598 | /* We could handle this with some effort, but this case is much better | |
2599 | handled directly with a scc insn, so rely on caller using that. */ | |
2600 | abort (); | |
2601 | } | |
2602 | ||
2603 | /* mlow = 2^(N + lgup)/d */ | |
2604 | if (pow >= HOST_BITS_PER_WIDE_INT) | |
2605 | { | |
f9e158c3 | 2606 | nh = (HOST_WIDE_INT) 1 << (pow - HOST_BITS_PER_WIDE_INT); |
55c2d311 TG |
2607 | nl = 0; |
2608 | } | |
2609 | else | |
2610 | { | |
2611 | nh = 0; | |
2612 | nl = (unsigned HOST_WIDE_INT) 1 << pow; | |
2613 | } | |
2614 | div_and_round_double (TRUNC_DIV_EXPR, 1, nl, nh, d, (HOST_WIDE_INT) 0, | |
2615 | &mlow_lo, &mlow_hi, &dummy1, &dummy2); | |
2616 | ||
2617 | /* mhigh = (2^(N + lgup) + 2^N + lgup - precision)/d */ | |
2618 | if (pow2 >= HOST_BITS_PER_WIDE_INT) | |
f9e158c3 | 2619 | nh |= (HOST_WIDE_INT) 1 << (pow2 - HOST_BITS_PER_WIDE_INT); |
55c2d311 TG |
2620 | else |
2621 | nl |= (unsigned HOST_WIDE_INT) 1 << pow2; | |
2622 | div_and_round_double (TRUNC_DIV_EXPR, 1, nl, nh, d, (HOST_WIDE_INT) 0, | |
2623 | &mhigh_lo, &mhigh_hi, &dummy1, &dummy2); | |
2624 | ||
2625 | if (mhigh_hi && nh - d >= d) | |
2626 | abort (); | |
2627 | if (mhigh_hi > 1 || mlow_hi > 1) | |
2628 | abort (); | |
2629 | /* assert that mlow < mhigh. */ | |
2630 | if (! (mlow_hi < mhigh_hi || (mlow_hi == mhigh_hi && mlow_lo < mhigh_lo))) | |
c4f2c499 | 2631 | abort (); |
55c2d311 TG |
2632 | |
2633 | /* If precision == N, then mlow, mhigh exceed 2^N | |
2634 | (but they do not exceed 2^(N+1)). */ | |
2635 | ||
2636 | /* Reduce to lowest terms */ | |
2637 | for (post_shift = lgup; post_shift > 0; post_shift--) | |
2638 | { | |
2639 | unsigned HOST_WIDE_INT ml_lo = (mlow_hi << (HOST_BITS_PER_WIDE_INT - 1)) | (mlow_lo >> 1); | |
2640 | unsigned HOST_WIDE_INT mh_lo = (mhigh_hi << (HOST_BITS_PER_WIDE_INT - 1)) | (mhigh_lo >> 1); | |
2641 | if (ml_lo >= mh_lo) | |
2642 | break; | |
2643 | ||
2644 | mlow_hi = 0; | |
2645 | mlow_lo = ml_lo; | |
2646 | mhigh_hi = 0; | |
2647 | mhigh_lo = mh_lo; | |
2648 | } | |
2649 | ||
2650 | *post_shift_ptr = post_shift; | |
2651 | *lgup_ptr = lgup; | |
2652 | if (n < HOST_BITS_PER_WIDE_INT) | |
2653 | { | |
2654 | unsigned HOST_WIDE_INT mask = ((unsigned HOST_WIDE_INT) 1 << n) - 1; | |
2655 | *multiplier_ptr = mhigh_lo & mask; | |
2656 | return mhigh_lo >= mask; | |
2657 | } | |
2658 | else | |
2659 | { | |
2660 | *multiplier_ptr = mhigh_lo; | |
2661 | return mhigh_hi; | |
2662 | } | |
2663 | } | |
2664 | ||
2665 | /* Compute the inverse of X mod 2**n, i.e., find Y such that X * Y is | |
2666 | congruent to 1 (mod 2**N). */ | |
2667 | ||
2668 | static unsigned HOST_WIDE_INT | |
2669 | invert_mod2n (x, n) | |
2670 | unsigned HOST_WIDE_INT x; | |
2671 | int n; | |
2672 | { | |
0f41302f | 2673 | /* Solve x*y == 1 (mod 2^n), where x is odd. Return y. */ |
55c2d311 TG |
2674 | |
2675 | /* The algorithm notes that the choice y = x satisfies | |
2676 | x*y == 1 mod 2^3, since x is assumed odd. | |
2677 | Each iteration doubles the number of bits of significance in y. */ | |
2678 | ||
2679 | unsigned HOST_WIDE_INT mask; | |
2680 | unsigned HOST_WIDE_INT y = x; | |
2681 | int nbit = 3; | |
2682 | ||
2683 | mask = (n == HOST_BITS_PER_WIDE_INT | |
2684 | ? ~(unsigned HOST_WIDE_INT) 0 | |
2685 | : ((unsigned HOST_WIDE_INT) 1 << n) - 1); | |
2686 | ||
2687 | while (nbit < n) | |
2688 | { | |
2689 | y = y * (2 - x*y) & mask; /* Modulo 2^N */ | |
2690 | nbit *= 2; | |
2691 | } | |
2692 | return y; | |
2693 | } | |
2694 | ||
2695 | /* Emit code to adjust ADJ_OPERAND after multiplication of wrong signedness | |
2696 | flavor of OP0 and OP1. ADJ_OPERAND is already the high half of the | |
2697 | product OP0 x OP1. If UNSIGNEDP is nonzero, adjust the signed product | |
2698 | to become unsigned, if UNSIGNEDP is zero, adjust the unsigned product to | |
2699 | become signed. | |
2700 | ||
2701 | The result is put in TARGET if that is convenient. | |
2702 | ||
2703 | MODE is the mode of operation. */ | |
2704 | ||
2705 | rtx | |
2706 | expand_mult_highpart_adjust (mode, adj_operand, op0, op1, target, unsignedp) | |
2707 | enum machine_mode mode; | |
b3694847 | 2708 | rtx adj_operand, op0, op1, target; |
55c2d311 TG |
2709 | int unsignedp; |
2710 | { | |
2711 | rtx tem; | |
2712 | enum rtx_code adj_code = unsignedp ? PLUS : MINUS; | |
2713 | ||
2714 | tem = expand_shift (RSHIFT_EXPR, mode, op0, | |
2715 | build_int_2 (GET_MODE_BITSIZE (mode) - 1, 0), | |
2716 | NULL_RTX, 0); | |
2717 | tem = expand_and (tem, op1, NULL_RTX); | |
38a448ca RH |
2718 | adj_operand |
2719 | = force_operand (gen_rtx_fmt_ee (adj_code, mode, adj_operand, tem), | |
2720 | adj_operand); | |
55c2d311 TG |
2721 | |
2722 | tem = expand_shift (RSHIFT_EXPR, mode, op1, | |
2723 | build_int_2 (GET_MODE_BITSIZE (mode) - 1, 0), | |
2724 | NULL_RTX, 0); | |
2725 | tem = expand_and (tem, op0, NULL_RTX); | |
38a448ca RH |
2726 | target = force_operand (gen_rtx_fmt_ee (adj_code, mode, adj_operand, tem), |
2727 | target); | |
55c2d311 TG |
2728 | |
2729 | return target; | |
2730 | } | |
2731 | ||
2732 | /* Emit code to multiply OP0 and CNST1, putting the high half of the result | |
2733 | in TARGET if that is convenient, and return where the result is. If the | |
2734 | operation can not be performed, 0 is returned. | |
2735 | ||
2736 | MODE is the mode of operation and result. | |
2737 | ||
71af73bb TG |
2738 | UNSIGNEDP nonzero means unsigned multiply. |
2739 | ||
2740 | MAX_COST is the total allowed cost for the expanded RTL. */ | |
55c2d311 TG |
2741 | |
2742 | rtx | |
71af73bb | 2743 | expand_mult_highpart (mode, op0, cnst1, target, unsignedp, max_cost) |
55c2d311 | 2744 | enum machine_mode mode; |
b3694847 | 2745 | rtx op0, target; |
55c2d311 TG |
2746 | unsigned HOST_WIDE_INT cnst1; |
2747 | int unsignedp; | |
71af73bb | 2748 | int max_cost; |
55c2d311 TG |
2749 | { |
2750 | enum machine_mode wider_mode = GET_MODE_WIDER_MODE (mode); | |
2751 | optab mul_highpart_optab; | |
2752 | optab moptab; | |
2753 | rtx tem; | |
2754 | int size = GET_MODE_BITSIZE (mode); | |
5b0ce758 | 2755 | rtx op1, wide_op1; |
55c2d311 | 2756 | |
0865c631 | 2757 | /* We can't support modes wider than HOST_BITS_PER_INT. */ |
5b0ce758 RK |
2758 | if (size > HOST_BITS_PER_WIDE_INT) |
2759 | abort (); | |
2760 | ||
69107307 | 2761 | op1 = GEN_INT (trunc_int_for_mode (cnst1, mode)); |
5b0ce758 | 2762 | |
d3c52658 JJ |
2763 | wide_op1 |
2764 | = immed_double_const (cnst1, | |
2765 | (unsignedp | |
2766 | ? (HOST_WIDE_INT) 0 | |
2767 | : -(cnst1 >> (HOST_BITS_PER_WIDE_INT - 1))), | |
2768 | wider_mode); | |
55c2d311 TG |
2769 | |
2770 | /* expand_mult handles constant multiplication of word_mode | |
2771 | or narrower. It does a poor job for large modes. */ | |
71af73bb TG |
2772 | if (size < BITS_PER_WORD |
2773 | && mul_cost[(int) wider_mode] + shift_cost[size-1] < max_cost) | |
55c2d311 TG |
2774 | { |
2775 | /* We have to do this, since expand_binop doesn't do conversion for | |
2776 | multiply. Maybe change expand_binop to handle widening multiply? */ | |
2777 | op0 = convert_to_mode (wider_mode, op0, unsignedp); | |
2778 | ||
91ce572a CC |
2779 | /* We know that this can't have signed overflow, so pretend this is |
2780 | an unsigned multiply. */ | |
2781 | tem = expand_mult (wider_mode, op0, wide_op1, NULL_RTX, 0); | |
55c2d311 TG |
2782 | tem = expand_shift (RSHIFT_EXPR, wider_mode, tem, |
2783 | build_int_2 (size, 0), NULL_RTX, 1); | |
2f97afcb | 2784 | return convert_modes (mode, wider_mode, tem, unsignedp); |
55c2d311 TG |
2785 | } |
2786 | ||
2787 | if (target == 0) | |
2788 | target = gen_reg_rtx (mode); | |
2789 | ||
2790 | /* Firstly, try using a multiplication insn that only generates the needed | |
2791 | high part of the product, and in the sign flavor of unsignedp. */ | |
71af73bb TG |
2792 | if (mul_highpart_cost[(int) mode] < max_cost) |
2793 | { | |
2794 | mul_highpart_optab = unsignedp ? umul_highpart_optab : smul_highpart_optab; | |
2795 | target = expand_binop (mode, mul_highpart_optab, | |
3b5286d7 | 2796 | op0, op1, target, unsignedp, OPTAB_DIRECT); |
71af73bb TG |
2797 | if (target) |
2798 | return target; | |
2799 | } | |
55c2d311 TG |
2800 | |
2801 | /* Secondly, same as above, but use sign flavor opposite of unsignedp. | |
2802 | Need to adjust the result after the multiplication. */ | |
02a65aef R |
2803 | if (size - 1 < BITS_PER_WORD |
2804 | && (mul_highpart_cost[(int) mode] + 2 * shift_cost[size-1] + 4 * add_cost | |
2805 | < max_cost)) | |
71af73bb TG |
2806 | { |
2807 | mul_highpart_optab = unsignedp ? smul_highpart_optab : umul_highpart_optab; | |
2808 | target = expand_binop (mode, mul_highpart_optab, | |
3b5286d7 | 2809 | op0, op1, target, unsignedp, OPTAB_DIRECT); |
71af73bb TG |
2810 | if (target) |
2811 | /* We used the wrong signedness. Adjust the result. */ | |
2812 | return expand_mult_highpart_adjust (mode, target, op0, | |
2813 | op1, target, unsignedp); | |
2814 | } | |
55c2d311 | 2815 | |
71af73bb | 2816 | /* Try widening multiplication. */ |
55c2d311 | 2817 | moptab = unsignedp ? umul_widen_optab : smul_widen_optab; |
71af73bb TG |
2818 | if (moptab->handlers[(int) wider_mode].insn_code != CODE_FOR_nothing |
2819 | && mul_widen_cost[(int) wider_mode] < max_cost) | |
a295d331 TG |
2820 | { |
2821 | op1 = force_reg (mode, op1); | |
2822 | goto try; | |
2823 | } | |
71af73bb TG |
2824 | |
2825 | /* Try widening the mode and perform a non-widening multiplication. */ | |
2826 | moptab = smul_optab; | |
2827 | if (smul_optab->handlers[(int) wider_mode].insn_code != CODE_FOR_nothing | |
02a65aef | 2828 | && size - 1 < BITS_PER_WORD |
71af73bb | 2829 | && mul_cost[(int) wider_mode] + shift_cost[size-1] < max_cost) |
a295d331 TG |
2830 | { |
2831 | op1 = wide_op1; | |
2832 | goto try; | |
2833 | } | |
71af73bb TG |
2834 | |
2835 | /* Try widening multiplication of opposite signedness, and adjust. */ | |
2836 | moptab = unsignedp ? smul_widen_optab : umul_widen_optab; | |
2837 | if (moptab->handlers[(int) wider_mode].insn_code != CODE_FOR_nothing | |
02a65aef | 2838 | && size - 1 < BITS_PER_WORD |
71af73bb TG |
2839 | && (mul_widen_cost[(int) wider_mode] |
2840 | + 2 * shift_cost[size-1] + 4 * add_cost < max_cost)) | |
55c2d311 | 2841 | { |
a295d331 TG |
2842 | rtx regop1 = force_reg (mode, op1); |
2843 | tem = expand_binop (wider_mode, moptab, op0, regop1, | |
71af73bb TG |
2844 | NULL_RTX, ! unsignedp, OPTAB_WIDEN); |
2845 | if (tem != 0) | |
55c2d311 | 2846 | { |
71af73bb TG |
2847 | /* Extract the high half of the just generated product. */ |
2848 | tem = expand_shift (RSHIFT_EXPR, wider_mode, tem, | |
2849 | build_int_2 (size, 0), NULL_RTX, 1); | |
2850 | tem = convert_modes (mode, wider_mode, tem, unsignedp); | |
2851 | /* We used the wrong signedness. Adjust the result. */ | |
2852 | return expand_mult_highpart_adjust (mode, tem, op0, op1, | |
2853 | target, unsignedp); | |
55c2d311 | 2854 | } |
55c2d311 TG |
2855 | } |
2856 | ||
71af73bb TG |
2857 | return 0; |
2858 | ||
2859 | try: | |
55c2d311 | 2860 | /* Pass NULL_RTX as target since TARGET has wrong mode. */ |
a295d331 | 2861 | tem = expand_binop (wider_mode, moptab, op0, op1, |
55c2d311 TG |
2862 | NULL_RTX, unsignedp, OPTAB_WIDEN); |
2863 | if (tem == 0) | |
2864 | return 0; | |
2865 | ||
2866 | /* Extract the high half of the just generated product. */ | |
a295d331 TG |
2867 | if (mode == word_mode) |
2868 | { | |
2869 | return gen_highpart (mode, tem); | |
2870 | } | |
2871 | else | |
2872 | { | |
2873 | tem = expand_shift (RSHIFT_EXPR, wider_mode, tem, | |
2874 | build_int_2 (size, 0), NULL_RTX, 1); | |
2875 | return convert_modes (mode, wider_mode, tem, unsignedp); | |
2876 | } | |
55c2d311 TG |
2877 | } |
2878 | \f | |
44037a66 TG |
2879 | /* Emit the code to divide OP0 by OP1, putting the result in TARGET |
2880 | if that is convenient, and returning where the result is. | |
2881 | You may request either the quotient or the remainder as the result; | |
2882 | specify REM_FLAG nonzero to get the remainder. | |
2883 | ||
2884 | CODE is the expression code for which kind of division this is; | |
2885 | it controls how rounding is done. MODE is the machine mode to use. | |
2886 | UNSIGNEDP nonzero means do unsigned division. */ | |
2887 | ||
2888 | /* ??? For CEIL_MOD_EXPR, can compute incorrect remainder with ANDI | |
2889 | and then correct it by or'ing in missing high bits | |
2890 | if result of ANDI is nonzero. | |
2891 | For ROUND_MOD_EXPR, can use ANDI and then sign-extend the result. | |
2892 | This could optimize to a bfexts instruction. | |
2893 | But C doesn't use these operations, so their optimizations are | |
2894 | left for later. */ | |
5353610b R |
2895 | /* ??? For modulo, we don't actually need the highpart of the first product, |
2896 | the low part will do nicely. And for small divisors, the second multiply | |
2897 | can also be a low-part only multiply or even be completely left out. | |
2898 | E.g. to calculate the remainder of a division by 3 with a 32 bit | |
2899 | multiply, multiply with 0x55555556 and extract the upper two bits; | |
2900 | the result is exact for inputs up to 0x1fffffff. | |
2901 | The input range can be reduced by using cross-sum rules. | |
2902 | For odd divisors >= 3, the following table gives right shift counts | |
2903 | so that if an number is shifted by an integer multiple of the given | |
2904 | amount, the remainder stays the same: | |
2905 | 2, 4, 3, 6, 10, 12, 4, 8, 18, 6, 11, 20, 18, 0, 5, 10, 12, 0, 12, 20, | |
2906 | 14, 12, 23, 21, 8, 0, 20, 18, 0, 0, 6, 12, 0, 22, 0, 18, 20, 30, 0, 0, | |
2907 | 0, 8, 0, 11, 12, 10, 36, 0, 30, 0, 0, 12, 0, 0, 0, 0, 44, 12, 24, 0, | |
2908 | 20, 0, 7, 14, 0, 18, 36, 0, 0, 46, 60, 0, 42, 0, 15, 24, 20, 0, 0, 33, | |
2909 | 0, 20, 0, 0, 18, 0, 60, 0, 0, 0, 0, 0, 40, 18, 0, 0, 12 | |
2910 | ||
2911 | Cross-sum rules for even numbers can be derived by leaving as many bits | |
2912 | to the right alone as the divisor has zeros to the right. | |
2913 | E.g. if x is an unsigned 32 bit number: | |
2914 | (x mod 12) == (((x & 1023) + ((x >> 8) & ~3)) * 0x15555558 >> 2 * 3) >> 28 | |
2915 | */ | |
44037a66 | 2916 | |
55c2d311 TG |
2917 | #define EXACT_POWER_OF_2_OR_ZERO_P(x) (((x) & ((x) - 1)) == 0) |
2918 | ||
44037a66 TG |
2919 | rtx |
2920 | expand_divmod (rem_flag, code, mode, op0, op1, target, unsignedp) | |
2921 | int rem_flag; | |
2922 | enum tree_code code; | |
2923 | enum machine_mode mode; | |
b3694847 | 2924 | rtx op0, op1, target; |
44037a66 TG |
2925 | int unsignedp; |
2926 | { | |
44037a66 | 2927 | enum machine_mode compute_mode; |
b3694847 | 2928 | rtx tquotient; |
55c2d311 TG |
2929 | rtx quotient = 0, remainder = 0; |
2930 | rtx last; | |
2c414fba | 2931 | int size; |
4e430df8 | 2932 | rtx insn, set; |
44037a66 | 2933 | optab optab1, optab2; |
55c2d311 | 2934 | int op1_is_constant, op1_is_pow2; |
71af73bb | 2935 | int max_cost, extra_cost; |
9ec36da5 | 2936 | static HOST_WIDE_INT last_div_const = 0; |
55c2d311 TG |
2937 | |
2938 | op1_is_constant = GET_CODE (op1) == CONST_INT; | |
9176af2f TG |
2939 | op1_is_pow2 = (op1_is_constant |
2940 | && ((EXACT_POWER_OF_2_OR_ZERO_P (INTVAL (op1)) | |
db7cafb0 | 2941 | || (! unsignedp && EXACT_POWER_OF_2_OR_ZERO_P (-INTVAL (op1)))))); |
55c2d311 TG |
2942 | |
2943 | /* | |
2944 | This is the structure of expand_divmod: | |
2945 | ||
2946 | First comes code to fix up the operands so we can perform the operations | |
2947 | correctly and efficiently. | |
2948 | ||
2949 | Second comes a switch statement with code specific for each rounding mode. | |
2950 | For some special operands this code emits all RTL for the desired | |
69f61901 | 2951 | operation, for other cases, it generates only a quotient and stores it in |
55c2d311 TG |
2952 | QUOTIENT. The case for trunc division/remainder might leave quotient = 0, |
2953 | to indicate that it has not done anything. | |
2954 | ||
69f61901 RK |
2955 | Last comes code that finishes the operation. If QUOTIENT is set and |
2956 | REM_FLAG is set, the remainder is computed as OP0 - QUOTIENT * OP1. If | |
2957 | QUOTIENT is not set, it is computed using trunc rounding. | |
44037a66 | 2958 | |
55c2d311 TG |
2959 | We try to generate special code for division and remainder when OP1 is a |
2960 | constant. If |OP1| = 2**n we can use shifts and some other fast | |
2961 | operations. For other values of OP1, we compute a carefully selected | |
2962 | fixed-point approximation m = 1/OP1, and generate code that multiplies OP0 | |
2963 | by m. | |
2964 | ||
2965 | In all cases but EXACT_DIV_EXPR, this multiplication requires the upper | |
2966 | half of the product. Different strategies for generating the product are | |
2967 | implemented in expand_mult_highpart. | |
2968 | ||
2969 | If what we actually want is the remainder, we generate that by another | |
2970 | by-constant multiplication and a subtraction. */ | |
2971 | ||
2972 | /* We shouldn't be called with OP1 == const1_rtx, but some of the | |
3d32ffd1 TW |
2973 | code below will malfunction if we are, so check here and handle |
2974 | the special case if so. */ | |
2975 | if (op1 == const1_rtx) | |
2976 | return rem_flag ? const0_rtx : op0; | |
2977 | ||
91ce572a CC |
2978 | /* When dividing by -1, we could get an overflow. |
2979 | negv_optab can handle overflows. */ | |
2980 | if (! unsignedp && op1 == constm1_rtx) | |
2981 | { | |
2982 | if (rem_flag) | |
2983 | return const0_rtx; | |
2984 | return expand_unop (mode, flag_trapv && GET_MODE_CLASS(mode) == MODE_INT | |
2985 | ? negv_optab : neg_optab, op0, target, 0); | |
2986 | } | |
2987 | ||
bc1c7e93 RK |
2988 | if (target |
2989 | /* Don't use the function value register as a target | |
2990 | since we have to read it as well as write it, | |
2991 | and function-inlining gets confused by this. */ | |
2992 | && ((REG_P (target) && REG_FUNCTION_VALUE_P (target)) | |
2993 | /* Don't clobber an operand while doing a multi-step calculation. */ | |
515dfc7a | 2994 | || ((rem_flag || op1_is_constant) |
bc1c7e93 RK |
2995 | && (reg_mentioned_p (target, op0) |
2996 | || (GET_CODE (op0) == MEM && GET_CODE (target) == MEM))) | |
2997 | || reg_mentioned_p (target, op1) | |
2998 | || (GET_CODE (op1) == MEM && GET_CODE (target) == MEM))) | |
44037a66 TG |
2999 | target = 0; |
3000 | ||
44037a66 TG |
3001 | /* Get the mode in which to perform this computation. Normally it will |
3002 | be MODE, but sometimes we can't do the desired operation in MODE. | |
3003 | If so, pick a wider mode in which we can do the operation. Convert | |
3004 | to that mode at the start to avoid repeated conversions. | |
3005 | ||
3006 | First see what operations we need. These depend on the expression | |
3007 | we are evaluating. (We assume that divxx3 insns exist under the | |
3008 | same conditions that modxx3 insns and that these insns don't normally | |
3009 | fail. If these assumptions are not correct, we may generate less | |
3010 | efficient code in some cases.) | |
3011 | ||
3012 | Then see if we find a mode in which we can open-code that operation | |
3013 | (either a division, modulus, or shift). Finally, check for the smallest | |
3014 | mode for which we can do the operation with a library call. */ | |
3015 | ||
55c2d311 TG |
3016 | /* We might want to refine this now that we have division-by-constant |
3017 | optimization. Since expand_mult_highpart tries so many variants, it is | |
3018 | not straightforward to generalize this. Maybe we should make an array | |
3019 | of possible modes in init_expmed? Save this for GCC 2.7. */ | |
3020 | ||
3021 | optab1 = (op1_is_pow2 ? (unsignedp ? lshr_optab : ashr_optab) | |
44037a66 | 3022 | : (unsignedp ? udiv_optab : sdiv_optab)); |
55c2d311 | 3023 | optab2 = (op1_is_pow2 ? optab1 : (unsignedp ? udivmod_optab : sdivmod_optab)); |
44037a66 TG |
3024 | |
3025 | for (compute_mode = mode; compute_mode != VOIDmode; | |
3026 | compute_mode = GET_MODE_WIDER_MODE (compute_mode)) | |
3027 | if (optab1->handlers[(int) compute_mode].insn_code != CODE_FOR_nothing | |
3028 | || optab2->handlers[(int) compute_mode].insn_code != CODE_FOR_nothing) | |
3029 | break; | |
3030 | ||
3031 | if (compute_mode == VOIDmode) | |
3032 | for (compute_mode = mode; compute_mode != VOIDmode; | |
3033 | compute_mode = GET_MODE_WIDER_MODE (compute_mode)) | |
3034 | if (optab1->handlers[(int) compute_mode].libfunc | |
3035 | || optab2->handlers[(int) compute_mode].libfunc) | |
3036 | break; | |
3037 | ||
bc1c7e93 RK |
3038 | /* If we still couldn't find a mode, use MODE, but we'll probably abort |
3039 | in expand_binop. */ | |
44037a66 TG |
3040 | if (compute_mode == VOIDmode) |
3041 | compute_mode = mode; | |
3042 | ||
55c2d311 TG |
3043 | if (target && GET_MODE (target) == compute_mode) |
3044 | tquotient = target; | |
3045 | else | |
3046 | tquotient = gen_reg_rtx (compute_mode); | |
2c414fba | 3047 | |
55c2d311 TG |
3048 | size = GET_MODE_BITSIZE (compute_mode); |
3049 | #if 0 | |
3050 | /* It should be possible to restrict the precision to GET_MODE_BITSIZE | |
71af73bb TG |
3051 | (mode), and thereby get better code when OP1 is a constant. Do that |
3052 | later. It will require going over all usages of SIZE below. */ | |
55c2d311 TG |
3053 | size = GET_MODE_BITSIZE (mode); |
3054 | #endif | |
bc1c7e93 | 3055 | |
9ec36da5 JL |
3056 | /* Only deduct something for a REM if the last divide done was |
3057 | for a different constant. Then set the constant of the last | |
3058 | divide. */ | |
71af73bb | 3059 | max_cost = div_cost[(int) compute_mode] |
9ec36da5 JL |
3060 | - (rem_flag && ! (last_div_const != 0 && op1_is_constant |
3061 | && INTVAL (op1) == last_div_const) | |
3062 | ? mul_cost[(int) compute_mode] + add_cost : 0); | |
3063 | ||
3064 | last_div_const = ! rem_flag && op1_is_constant ? INTVAL (op1) : 0; | |
71af73bb | 3065 | |
55c2d311 | 3066 | /* Now convert to the best mode to use. */ |
44037a66 TG |
3067 | if (compute_mode != mode) |
3068 | { | |
55c2d311 | 3069 | op0 = convert_modes (compute_mode, mode, op0, unsignedp); |
81722fa9 | 3070 | op1 = convert_modes (compute_mode, mode, op1, unsignedp); |
e13a25d5 | 3071 | |
e9a25f70 JL |
3072 | /* convert_modes may have placed op1 into a register, so we |
3073 | must recompute the following. */ | |
e13a25d5 DM |
3074 | op1_is_constant = GET_CODE (op1) == CONST_INT; |
3075 | op1_is_pow2 = (op1_is_constant | |
3076 | && ((EXACT_POWER_OF_2_OR_ZERO_P (INTVAL (op1)) | |
3077 | || (! unsignedp | |
e9a25f70 | 3078 | && EXACT_POWER_OF_2_OR_ZERO_P (-INTVAL (op1)))))) ; |
44037a66 TG |
3079 | } |
3080 | ||
55c2d311 | 3081 | /* If one of the operands is a volatile MEM, copy it into a register. */ |
c2a47e48 | 3082 | |
55c2d311 TG |
3083 | if (GET_CODE (op0) == MEM && MEM_VOLATILE_P (op0)) |
3084 | op0 = force_reg (compute_mode, op0); | |
3085 | if (GET_CODE (op1) == MEM && MEM_VOLATILE_P (op1)) | |
c2a47e48 RK |
3086 | op1 = force_reg (compute_mode, op1); |
3087 | ||
ab0b6581 TG |
3088 | /* If we need the remainder or if OP1 is constant, we need to |
3089 | put OP0 in a register in case it has any queued subexpressions. */ | |
3090 | if (rem_flag || op1_is_constant) | |
3091 | op0 = force_reg (compute_mode, op0); | |
bc1c7e93 | 3092 | |
55c2d311 | 3093 | last = get_last_insn (); |
44037a66 | 3094 | |
9faa82d8 | 3095 | /* Promote floor rounding to trunc rounding for unsigned operations. */ |
55c2d311 | 3096 | if (unsignedp) |
44037a66 | 3097 | { |
55c2d311 TG |
3098 | if (code == FLOOR_DIV_EXPR) |
3099 | code = TRUNC_DIV_EXPR; | |
3100 | if (code == FLOOR_MOD_EXPR) | |
3101 | code = TRUNC_MOD_EXPR; | |
db7cafb0 JL |
3102 | if (code == EXACT_DIV_EXPR && op1_is_pow2) |
3103 | code = TRUNC_DIV_EXPR; | |
55c2d311 | 3104 | } |
bc1c7e93 | 3105 | |
55c2d311 TG |
3106 | if (op1 != const0_rtx) |
3107 | switch (code) | |
3108 | { | |
3109 | case TRUNC_MOD_EXPR: | |
3110 | case TRUNC_DIV_EXPR: | |
34f016ed | 3111 | if (op1_is_constant) |
55c2d311 | 3112 | { |
d8f1376c | 3113 | if (unsignedp) |
55c2d311 TG |
3114 | { |
3115 | unsigned HOST_WIDE_INT mh, ml; | |
3116 | int pre_shift, post_shift; | |
3117 | int dummy; | |
3118 | unsigned HOST_WIDE_INT d = INTVAL (op1); | |
3119 | ||
3120 | if (EXACT_POWER_OF_2_OR_ZERO_P (d)) | |
3121 | { | |
3122 | pre_shift = floor_log2 (d); | |
3123 | if (rem_flag) | |
3124 | { | |
db3cf6fb MS |
3125 | remainder |
3126 | = expand_binop (compute_mode, and_optab, op0, | |
3127 | GEN_INT (((HOST_WIDE_INT) 1 << pre_shift) - 1), | |
3128 | remainder, 1, | |
3129 | OPTAB_LIB_WIDEN); | |
55c2d311 | 3130 | if (remainder) |
c8dbc8ca | 3131 | return gen_lowpart (mode, remainder); |
55c2d311 TG |
3132 | } |
3133 | quotient = expand_shift (RSHIFT_EXPR, compute_mode, op0, | |
3134 | build_int_2 (pre_shift, 0), | |
3135 | tquotient, 1); | |
3136 | } | |
34f016ed | 3137 | else if (size <= HOST_BITS_PER_WIDE_INT) |
55c2d311 | 3138 | { |
dc1d6150 | 3139 | if (d >= ((unsigned HOST_WIDE_INT) 1 << (size - 1))) |
55c2d311 | 3140 | { |
dc1d6150 TG |
3141 | /* Most significant bit of divisor is set; emit an scc |
3142 | insn. */ | |
3143 | quotient = emit_store_flag (tquotient, GEU, op0, op1, | |
3144 | compute_mode, 1, 1); | |
3145 | if (quotient == 0) | |
55c2d311 | 3146 | goto fail1; |
55c2d311 TG |
3147 | } |
3148 | else | |
3149 | { | |
dc1d6150 TG |
3150 | /* Find a suitable multiplier and right shift count |
3151 | instead of multiplying with D. */ | |
3152 | ||
3153 | mh = choose_multiplier (d, size, size, | |
3154 | &ml, &post_shift, &dummy); | |
3155 | ||
3156 | /* If the suggested multiplier is more than SIZE bits, | |
3157 | we can do better for even divisors, using an | |
3158 | initial right shift. */ | |
3159 | if (mh != 0 && (d & 1) == 0) | |
3160 | { | |
3161 | pre_shift = floor_log2 (d & -d); | |
3162 | mh = choose_multiplier (d >> pre_shift, size, | |
3163 | size - pre_shift, | |
3164 | &ml, &post_shift, &dummy); | |
3165 | if (mh) | |
3166 | abort (); | |
3167 | } | |
3168 | else | |
3169 | pre_shift = 0; | |
3170 | ||
3171 | if (mh != 0) | |
3172 | { | |
3173 | rtx t1, t2, t3, t4; | |
3174 | ||
02a65aef R |
3175 | if (post_shift - 1 >= BITS_PER_WORD) |
3176 | goto fail1; | |
3177 | ||
dc1d6150 TG |
3178 | extra_cost = (shift_cost[post_shift - 1] |
3179 | + shift_cost[1] + 2 * add_cost); | |
3180 | t1 = expand_mult_highpart (compute_mode, op0, ml, | |
3181 | NULL_RTX, 1, | |
3182 | max_cost - extra_cost); | |
3183 | if (t1 == 0) | |
3184 | goto fail1; | |
38a448ca RH |
3185 | t2 = force_operand (gen_rtx_MINUS (compute_mode, |
3186 | op0, t1), | |
dc1d6150 TG |
3187 | NULL_RTX); |
3188 | t3 = expand_shift (RSHIFT_EXPR, compute_mode, t2, | |
3189 | build_int_2 (1, 0), NULL_RTX,1); | |
38a448ca RH |
3190 | t4 = force_operand (gen_rtx_PLUS (compute_mode, |
3191 | t1, t3), | |
dc1d6150 | 3192 | NULL_RTX); |
db3cf6fb MS |
3193 | quotient |
3194 | = expand_shift (RSHIFT_EXPR, compute_mode, t4, | |
3195 | build_int_2 (post_shift - 1, 0), | |
3196 | tquotient, 1); | |
dc1d6150 TG |
3197 | } |
3198 | else | |
3199 | { | |
3200 | rtx t1, t2; | |
3201 | ||
02a65aef R |
3202 | if (pre_shift >= BITS_PER_WORD |
3203 | || post_shift >= BITS_PER_WORD) | |
3204 | goto fail1; | |
3205 | ||
dc1d6150 TG |
3206 | t1 = expand_shift (RSHIFT_EXPR, compute_mode, op0, |
3207 | build_int_2 (pre_shift, 0), | |
3208 | NULL_RTX, 1); | |
3209 | extra_cost = (shift_cost[pre_shift] | |
3210 | + shift_cost[post_shift]); | |
3211 | t2 = expand_mult_highpart (compute_mode, t1, ml, | |
3212 | NULL_RTX, 1, | |
3213 | max_cost - extra_cost); | |
3214 | if (t2 == 0) | |
3215 | goto fail1; | |
db3cf6fb MS |
3216 | quotient |
3217 | = expand_shift (RSHIFT_EXPR, compute_mode, t2, | |
3218 | build_int_2 (post_shift, 0), | |
3219 | tquotient, 1); | |
dc1d6150 | 3220 | } |
55c2d311 TG |
3221 | } |
3222 | } | |
34f016ed TG |
3223 | else /* Too wide mode to use tricky code */ |
3224 | break; | |
55c2d311 TG |
3225 | |
3226 | insn = get_last_insn (); | |
4e430df8 RK |
3227 | if (insn != last |
3228 | && (set = single_set (insn)) != 0 | |
3229 | && SET_DEST (set) == quotient) | |
7e5bda2c AM |
3230 | set_unique_reg_note (insn, |
3231 | REG_EQUAL, | |
3232 | gen_rtx_UDIV (compute_mode, op0, op1)); | |
55c2d311 TG |
3233 | } |
3234 | else /* TRUNC_DIV, signed */ | |
3235 | { | |
3236 | unsigned HOST_WIDE_INT ml; | |
3237 | int lgup, post_shift; | |
3238 | HOST_WIDE_INT d = INTVAL (op1); | |
3239 | unsigned HOST_WIDE_INT abs_d = d >= 0 ? d : -d; | |
3240 | ||
3241 | /* n rem d = n rem -d */ | |
3242 | if (rem_flag && d < 0) | |
3243 | { | |
3244 | d = abs_d; | |
69107307 | 3245 | op1 = GEN_INT (trunc_int_for_mode (abs_d, compute_mode)); |
55c2d311 TG |
3246 | } |
3247 | ||
3248 | if (d == 1) | |
3249 | quotient = op0; | |
3250 | else if (d == -1) | |
3251 | quotient = expand_unop (compute_mode, neg_optab, op0, | |
3252 | tquotient, 0); | |
f737b132 RK |
3253 | else if (abs_d == (unsigned HOST_WIDE_INT) 1 << (size - 1)) |
3254 | { | |
3255 | /* This case is not handled correctly below. */ | |
3256 | quotient = emit_store_flag (tquotient, EQ, op0, op1, | |
3257 | compute_mode, 1, 1); | |
3258 | if (quotient == 0) | |
3259 | goto fail1; | |
3260 | } | |
55c2d311 | 3261 | else if (EXACT_POWER_OF_2_OR_ZERO_P (d) |
a8c7e72d RH |
3262 | && (rem_flag ? smod_pow2_cheap : sdiv_pow2_cheap) |
3263 | /* ??? The cheap metric is computed only for | |
3264 | word_mode. If this operation is wider, this may | |
3265 | not be so. Assume true if the optab has an | |
3266 | expander for this mode. */ | |
3267 | && (((rem_flag ? smod_optab : sdiv_optab) | |
3268 | ->handlers[(int) compute_mode].insn_code | |
3269 | != CODE_FOR_nothing) | |
3270 | || (sdivmod_optab->handlers[(int) compute_mode] | |
3271 | .insn_code != CODE_FOR_nothing))) | |
55c2d311 TG |
3272 | ; |
3273 | else if (EXACT_POWER_OF_2_OR_ZERO_P (abs_d)) | |
3274 | { | |
3275 | lgup = floor_log2 (abs_d); | |
1cf7847f | 3276 | if (BRANCH_COST < 1 || (abs_d != 2 && BRANCH_COST < 3)) |
55c2d311 TG |
3277 | { |
3278 | rtx label = gen_label_rtx (); | |
3279 | rtx t1; | |
3280 | ||
3281 | t1 = copy_to_mode_reg (compute_mode, op0); | |
f5963e61 JL |
3282 | do_cmp_and_jump (t1, const0_rtx, GE, |
3283 | compute_mode, label); | |
69107307 AO |
3284 | expand_inc (t1, GEN_INT (trunc_int_for_mode |
3285 | (abs_d - 1, compute_mode))); | |
55c2d311 TG |
3286 | emit_label (label); |
3287 | quotient = expand_shift (RSHIFT_EXPR, compute_mode, t1, | |
3288 | build_int_2 (lgup, 0), | |
3289 | tquotient, 0); | |
3290 | } | |
3291 | else | |
3292 | { | |
3293 | rtx t1, t2, t3; | |
3294 | t1 = expand_shift (RSHIFT_EXPR, compute_mode, op0, | |
3295 | build_int_2 (size - 1, 0), | |
3296 | NULL_RTX, 0); | |
3297 | t2 = expand_shift (RSHIFT_EXPR, compute_mode, t1, | |
3298 | build_int_2 (size - lgup, 0), | |
3299 | NULL_RTX, 1); | |
38a448ca RH |
3300 | t3 = force_operand (gen_rtx_PLUS (compute_mode, |
3301 | op0, t2), | |
55c2d311 TG |
3302 | NULL_RTX); |
3303 | quotient = expand_shift (RSHIFT_EXPR, compute_mode, t3, | |
3304 | build_int_2 (lgup, 0), | |
3305 | tquotient, 0); | |
3306 | } | |
3307 | ||
e8031612 RK |
3308 | /* We have computed OP0 / abs(OP1). If OP1 is negative, negate |
3309 | the quotient. */ | |
55c2d311 TG |
3310 | if (d < 0) |
3311 | { | |
3312 | insn = get_last_insn (); | |
4e430df8 RK |
3313 | if (insn != last |
3314 | && (set = single_set (insn)) != 0 | |
c8e7fe58 DE |
3315 | && SET_DEST (set) == quotient |
3316 | && abs_d < ((unsigned HOST_WIDE_INT) 1 | |
3317 | << (HOST_BITS_PER_WIDE_INT - 1))) | |
7e5bda2c AM |
3318 | set_unique_reg_note (insn, |
3319 | REG_EQUAL, | |
3320 | gen_rtx_DIV (compute_mode, | |
3321 | op0, | |
69107307 AO |
3322 | GEN_INT |
3323 | (trunc_int_for_mode | |
3324 | (abs_d, | |
3325 | compute_mode)))); | |
55c2d311 TG |
3326 | |
3327 | quotient = expand_unop (compute_mode, neg_optab, | |
3328 | quotient, quotient, 0); | |
3329 | } | |
3330 | } | |
34f016ed | 3331 | else if (size <= HOST_BITS_PER_WIDE_INT) |
55c2d311 TG |
3332 | { |
3333 | choose_multiplier (abs_d, size, size - 1, | |
3334 | &ml, &post_shift, &lgup); | |
3335 | if (ml < (unsigned HOST_WIDE_INT) 1 << (size - 1)) | |
3336 | { | |
3337 | rtx t1, t2, t3; | |
3338 | ||
02a65aef R |
3339 | if (post_shift >= BITS_PER_WORD |
3340 | || size - 1 >= BITS_PER_WORD) | |
3341 | goto fail1; | |
3342 | ||
71af73bb TG |
3343 | extra_cost = (shift_cost[post_shift] |
3344 | + shift_cost[size - 1] + add_cost); | |
55c2d311 | 3345 | t1 = expand_mult_highpart (compute_mode, op0, ml, |
71af73bb TG |
3346 | NULL_RTX, 0, |
3347 | max_cost - extra_cost); | |
55c2d311 TG |
3348 | if (t1 == 0) |
3349 | goto fail1; | |
3350 | t2 = expand_shift (RSHIFT_EXPR, compute_mode, t1, | |
3351 | build_int_2 (post_shift, 0), NULL_RTX, 0); | |
3352 | t3 = expand_shift (RSHIFT_EXPR, compute_mode, op0, | |
3353 | build_int_2 (size - 1, 0), NULL_RTX, 0); | |
3354 | if (d < 0) | |
c5c76735 JL |
3355 | quotient |
3356 | = force_operand (gen_rtx_MINUS (compute_mode, | |
3357 | t3, t2), | |
3358 | tquotient); | |
55c2d311 | 3359 | else |
c5c76735 JL |
3360 | quotient |
3361 | = force_operand (gen_rtx_MINUS (compute_mode, | |
3362 | t2, t3), | |
3363 | tquotient); | |
55c2d311 TG |
3364 | } |
3365 | else | |
3366 | { | |
3367 | rtx t1, t2, t3, t4; | |
3368 | ||
02a65aef R |
3369 | if (post_shift >= BITS_PER_WORD |
3370 | || size - 1 >= BITS_PER_WORD) | |
3371 | goto fail1; | |
3372 | ||
55c2d311 | 3373 | ml |= (~(unsigned HOST_WIDE_INT) 0) << (size - 1); |
71af73bb TG |
3374 | extra_cost = (shift_cost[post_shift] |
3375 | + shift_cost[size - 1] + 2 * add_cost); | |
55c2d311 | 3376 | t1 = expand_mult_highpart (compute_mode, op0, ml, |
71af73bb TG |
3377 | NULL_RTX, 0, |
3378 | max_cost - extra_cost); | |
55c2d311 TG |
3379 | if (t1 == 0) |
3380 | goto fail1; | |
c5c76735 JL |
3381 | t2 = force_operand (gen_rtx_PLUS (compute_mode, |
3382 | t1, op0), | |
55c2d311 TG |
3383 | NULL_RTX); |
3384 | t3 = expand_shift (RSHIFT_EXPR, compute_mode, t2, | |
c5c76735 JL |
3385 | build_int_2 (post_shift, 0), |
3386 | NULL_RTX, 0); | |
55c2d311 | 3387 | t4 = expand_shift (RSHIFT_EXPR, compute_mode, op0, |
c5c76735 JL |
3388 | build_int_2 (size - 1, 0), |
3389 | NULL_RTX, 0); | |
55c2d311 | 3390 | if (d < 0) |
c5c76735 JL |
3391 | quotient |
3392 | = force_operand (gen_rtx_MINUS (compute_mode, | |
3393 | t4, t3), | |
3394 | tquotient); | |
55c2d311 | 3395 | else |
c5c76735 JL |
3396 | quotient |
3397 | = force_operand (gen_rtx_MINUS (compute_mode, | |
3398 | t3, t4), | |
3399 | tquotient); | |
55c2d311 TG |
3400 | } |
3401 | } | |
34f016ed TG |
3402 | else /* Too wide mode to use tricky code */ |
3403 | break; | |
55c2d311 | 3404 | |
4e430df8 RK |
3405 | insn = get_last_insn (); |
3406 | if (insn != last | |
3407 | && (set = single_set (insn)) != 0 | |
3408 | && SET_DEST (set) == quotient) | |
7e5bda2c AM |
3409 | set_unique_reg_note (insn, |
3410 | REG_EQUAL, | |
3411 | gen_rtx_DIV (compute_mode, op0, op1)); | |
55c2d311 TG |
3412 | } |
3413 | break; | |
3414 | } | |
3415 | fail1: | |
3416 | delete_insns_since (last); | |
3417 | break; | |
44037a66 | 3418 | |
55c2d311 TG |
3419 | case FLOOR_DIV_EXPR: |
3420 | case FLOOR_MOD_EXPR: | |
3421 | /* We will come here only for signed operations. */ | |
3422 | if (op1_is_constant && HOST_BITS_PER_WIDE_INT >= size) | |
3423 | { | |
3424 | unsigned HOST_WIDE_INT mh, ml; | |
3425 | int pre_shift, lgup, post_shift; | |
3426 | HOST_WIDE_INT d = INTVAL (op1); | |
3427 | ||
3428 | if (d > 0) | |
3429 | { | |
3430 | /* We could just as easily deal with negative constants here, | |
3431 | but it does not seem worth the trouble for GCC 2.6. */ | |
3432 | if (EXACT_POWER_OF_2_OR_ZERO_P (d)) | |
3433 | { | |
3434 | pre_shift = floor_log2 (d); | |
3435 | if (rem_flag) | |
3436 | { | |
3437 | remainder = expand_binop (compute_mode, and_optab, op0, | |
3438 | GEN_INT (((HOST_WIDE_INT) 1 << pre_shift) - 1), | |
3439 | remainder, 0, OPTAB_LIB_WIDEN); | |
3440 | if (remainder) | |
c8dbc8ca | 3441 | return gen_lowpart (mode, remainder); |
55c2d311 TG |
3442 | } |
3443 | quotient = expand_shift (RSHIFT_EXPR, compute_mode, op0, | |
3444 | build_int_2 (pre_shift, 0), | |
3445 | tquotient, 0); | |
3446 | } | |
3447 | else | |
3448 | { | |
3449 | rtx t1, t2, t3, t4; | |
3450 | ||
3451 | mh = choose_multiplier (d, size, size - 1, | |
3452 | &ml, &post_shift, &lgup); | |
3453 | if (mh) | |
3454 | abort (); | |
3455 | ||
02a65aef R |
3456 | if (post_shift < BITS_PER_WORD |
3457 | && size - 1 < BITS_PER_WORD) | |
55c2d311 | 3458 | { |
02a65aef R |
3459 | t1 = expand_shift (RSHIFT_EXPR, compute_mode, op0, |
3460 | build_int_2 (size - 1, 0), | |
3461 | NULL_RTX, 0); | |
3462 | t2 = expand_binop (compute_mode, xor_optab, op0, t1, | |
3463 | NULL_RTX, 0, OPTAB_WIDEN); | |
3464 | extra_cost = (shift_cost[post_shift] | |
3465 | + shift_cost[size - 1] + 2 * add_cost); | |
3466 | t3 = expand_mult_highpart (compute_mode, t2, ml, | |
3467 | NULL_RTX, 1, | |
3468 | max_cost - extra_cost); | |
3469 | if (t3 != 0) | |
3470 | { | |
3471 | t4 = expand_shift (RSHIFT_EXPR, compute_mode, t3, | |
3472 | build_int_2 (post_shift, 0), | |
3473 | NULL_RTX, 1); | |
3474 | quotient = expand_binop (compute_mode, xor_optab, | |
3475 | t4, t1, tquotient, 0, | |
3476 | OPTAB_WIDEN); | |
3477 | } | |
55c2d311 TG |
3478 | } |
3479 | } | |
3480 | } | |
3481 | else | |
3482 | { | |
3483 | rtx nsign, t1, t2, t3, t4; | |
38a448ca RH |
3484 | t1 = force_operand (gen_rtx_PLUS (compute_mode, |
3485 | op0, constm1_rtx), NULL_RTX); | |
55c2d311 TG |
3486 | t2 = expand_binop (compute_mode, ior_optab, op0, t1, NULL_RTX, |
3487 | 0, OPTAB_WIDEN); | |
3488 | nsign = expand_shift (RSHIFT_EXPR, compute_mode, t2, | |
3489 | build_int_2 (size - 1, 0), NULL_RTX, 0); | |
38a448ca | 3490 | t3 = force_operand (gen_rtx_MINUS (compute_mode, t1, nsign), |
55c2d311 TG |
3491 | NULL_RTX); |
3492 | t4 = expand_divmod (0, TRUNC_DIV_EXPR, compute_mode, t3, op1, | |
3493 | NULL_RTX, 0); | |
3494 | if (t4) | |
3495 | { | |
3496 | rtx t5; | |
3497 | t5 = expand_unop (compute_mode, one_cmpl_optab, nsign, | |
3498 | NULL_RTX, 0); | |
38a448ca RH |
3499 | quotient = force_operand (gen_rtx_PLUS (compute_mode, |
3500 | t4, t5), | |
55c2d311 TG |
3501 | tquotient); |
3502 | } | |
3503 | } | |
3504 | } | |
3505 | ||
3506 | if (quotient != 0) | |
3507 | break; | |
3508 | delete_insns_since (last); | |
3509 | ||
3510 | /* Try using an instruction that produces both the quotient and | |
3511 | remainder, using truncation. We can easily compensate the quotient | |
3512 | or remainder to get floor rounding, once we have the remainder. | |
3513 | Notice that we compute also the final remainder value here, | |
3514 | and return the result right away. */ | |
a45cf58c | 3515 | if (target == 0 || GET_MODE (target) != compute_mode) |
55c2d311 | 3516 | target = gen_reg_rtx (compute_mode); |
668443c9 | 3517 | |
55c2d311 TG |
3518 | if (rem_flag) |
3519 | { | |
668443c9 RK |
3520 | remainder |
3521 | = GET_CODE (target) == REG ? target : gen_reg_rtx (compute_mode); | |
55c2d311 TG |
3522 | quotient = gen_reg_rtx (compute_mode); |
3523 | } | |
3524 | else | |
3525 | { | |
668443c9 RK |
3526 | quotient |
3527 | = GET_CODE (target) == REG ? target : gen_reg_rtx (compute_mode); | |
55c2d311 TG |
3528 | remainder = gen_reg_rtx (compute_mode); |
3529 | } | |
3530 | ||
3531 | if (expand_twoval_binop (sdivmod_optab, op0, op1, | |
3532 | quotient, remainder, 0)) | |
3533 | { | |
3534 | /* This could be computed with a branch-less sequence. | |
3535 | Save that for later. */ | |
3536 | rtx tem; | |
3537 | rtx label = gen_label_rtx (); | |
f5963e61 | 3538 | do_cmp_and_jump (remainder, const0_rtx, EQ, compute_mode, label); |
55c2d311 TG |
3539 | tem = expand_binop (compute_mode, xor_optab, op0, op1, |
3540 | NULL_RTX, 0, OPTAB_WIDEN); | |
f5963e61 | 3541 | do_cmp_and_jump (tem, const0_rtx, GE, compute_mode, label); |
55c2d311 TG |
3542 | expand_dec (quotient, const1_rtx); |
3543 | expand_inc (remainder, op1); | |
3544 | emit_label (label); | |
c8dbc8ca | 3545 | return gen_lowpart (mode, rem_flag ? remainder : quotient); |
55c2d311 TG |
3546 | } |
3547 | ||
3548 | /* No luck with division elimination or divmod. Have to do it | |
3549 | by conditionally adjusting op0 *and* the result. */ | |
44037a66 | 3550 | { |
55c2d311 TG |
3551 | rtx label1, label2, label3, label4, label5; |
3552 | rtx adjusted_op0; | |
3553 | rtx tem; | |
3554 | ||
3555 | quotient = gen_reg_rtx (compute_mode); | |
3556 | adjusted_op0 = copy_to_mode_reg (compute_mode, op0); | |
3557 | label1 = gen_label_rtx (); | |
3558 | label2 = gen_label_rtx (); | |
3559 | label3 = gen_label_rtx (); | |
3560 | label4 = gen_label_rtx (); | |
3561 | label5 = gen_label_rtx (); | |
f5963e61 JL |
3562 | do_cmp_and_jump (op1, const0_rtx, LT, compute_mode, label2); |
3563 | do_cmp_and_jump (adjusted_op0, const0_rtx, LT, compute_mode, label1); | |
55c2d311 TG |
3564 | tem = expand_binop (compute_mode, sdiv_optab, adjusted_op0, op1, |
3565 | quotient, 0, OPTAB_LIB_WIDEN); | |
3566 | if (tem != quotient) | |
3567 | emit_move_insn (quotient, tem); | |
3568 | emit_jump_insn (gen_jump (label5)); | |
3569 | emit_barrier (); | |
3570 | emit_label (label1); | |
44037a66 | 3571 | expand_inc (adjusted_op0, const1_rtx); |
55c2d311 TG |
3572 | emit_jump_insn (gen_jump (label4)); |
3573 | emit_barrier (); | |
3574 | emit_label (label2); | |
f5963e61 | 3575 | do_cmp_and_jump (adjusted_op0, const0_rtx, GT, compute_mode, label3); |
55c2d311 TG |
3576 | tem = expand_binop (compute_mode, sdiv_optab, adjusted_op0, op1, |
3577 | quotient, 0, OPTAB_LIB_WIDEN); | |
3578 | if (tem != quotient) | |
3579 | emit_move_insn (quotient, tem); | |
3580 | emit_jump_insn (gen_jump (label5)); | |
3581 | emit_barrier (); | |
3582 | emit_label (label3); | |
3583 | expand_dec (adjusted_op0, const1_rtx); | |
3584 | emit_label (label4); | |
3585 | tem = expand_binop (compute_mode, sdiv_optab, adjusted_op0, op1, | |
3586 | quotient, 0, OPTAB_LIB_WIDEN); | |
3587 | if (tem != quotient) | |
3588 | emit_move_insn (quotient, tem); | |
3589 | expand_dec (quotient, const1_rtx); | |
3590 | emit_label (label5); | |
44037a66 | 3591 | } |
55c2d311 | 3592 | break; |
44037a66 | 3593 | |
55c2d311 TG |
3594 | case CEIL_DIV_EXPR: |
3595 | case CEIL_MOD_EXPR: | |
3596 | if (unsignedp) | |
3597 | { | |
9176af2f TG |
3598 | if (op1_is_constant && EXACT_POWER_OF_2_OR_ZERO_P (INTVAL (op1))) |
3599 | { | |
3600 | rtx t1, t2, t3; | |
3601 | unsigned HOST_WIDE_INT d = INTVAL (op1); | |
3602 | t1 = expand_shift (RSHIFT_EXPR, compute_mode, op0, | |
3603 | build_int_2 (floor_log2 (d), 0), | |
412381d9 | 3604 | tquotient, 1); |
9176af2f TG |
3605 | t2 = expand_binop (compute_mode, and_optab, op0, |
3606 | GEN_INT (d - 1), | |
3607 | NULL_RTX, 1, OPTAB_LIB_WIDEN); | |
3608 | t3 = gen_reg_rtx (compute_mode); | |
3609 | t3 = emit_store_flag (t3, NE, t2, const0_rtx, | |
3610 | compute_mode, 1, 1); | |
412381d9 TG |
3611 | if (t3 == 0) |
3612 | { | |
3613 | rtx lab; | |
3614 | lab = gen_label_rtx (); | |
f5963e61 | 3615 | do_cmp_and_jump (t2, const0_rtx, EQ, compute_mode, lab); |
412381d9 TG |
3616 | expand_inc (t1, const1_rtx); |
3617 | emit_label (lab); | |
3618 | quotient = t1; | |
3619 | } | |
3620 | else | |
38a448ca RH |
3621 | quotient = force_operand (gen_rtx_PLUS (compute_mode, |
3622 | t1, t3), | |
412381d9 | 3623 | tquotient); |
9176af2f TG |
3624 | break; |
3625 | } | |
55c2d311 TG |
3626 | |
3627 | /* Try using an instruction that produces both the quotient and | |
3628 | remainder, using truncation. We can easily compensate the | |
3629 | quotient or remainder to get ceiling rounding, once we have the | |
3630 | remainder. Notice that we compute also the final remainder | |
3631 | value here, and return the result right away. */ | |
a45cf58c | 3632 | if (target == 0 || GET_MODE (target) != compute_mode) |
55c2d311 | 3633 | target = gen_reg_rtx (compute_mode); |
668443c9 | 3634 | |
55c2d311 TG |
3635 | if (rem_flag) |
3636 | { | |
668443c9 RK |
3637 | remainder = (GET_CODE (target) == REG |
3638 | ? target : gen_reg_rtx (compute_mode)); | |
55c2d311 TG |
3639 | quotient = gen_reg_rtx (compute_mode); |
3640 | } | |
3641 | else | |
3642 | { | |
668443c9 RK |
3643 | quotient = (GET_CODE (target) == REG |
3644 | ? target : gen_reg_rtx (compute_mode)); | |
55c2d311 TG |
3645 | remainder = gen_reg_rtx (compute_mode); |
3646 | } | |
3647 | ||
3648 | if (expand_twoval_binop (udivmod_optab, op0, op1, quotient, | |
3649 | remainder, 1)) | |
3650 | { | |
3651 | /* This could be computed with a branch-less sequence. | |
3652 | Save that for later. */ | |
3653 | rtx label = gen_label_rtx (); | |
f5963e61 JL |
3654 | do_cmp_and_jump (remainder, const0_rtx, EQ, |
3655 | compute_mode, label); | |
55c2d311 TG |
3656 | expand_inc (quotient, const1_rtx); |
3657 | expand_dec (remainder, op1); | |
3658 | emit_label (label); | |
c8dbc8ca | 3659 | return gen_lowpart (mode, rem_flag ? remainder : quotient); |
55c2d311 TG |
3660 | } |
3661 | ||
3662 | /* No luck with division elimination or divmod. Have to do it | |
3663 | by conditionally adjusting op0 *and* the result. */ | |
44037a66 | 3664 | { |
55c2d311 TG |
3665 | rtx label1, label2; |
3666 | rtx adjusted_op0, tem; | |
3667 | ||
3668 | quotient = gen_reg_rtx (compute_mode); | |
3669 | adjusted_op0 = copy_to_mode_reg (compute_mode, op0); | |
3670 | label1 = gen_label_rtx (); | |
3671 | label2 = gen_label_rtx (); | |
f5963e61 JL |
3672 | do_cmp_and_jump (adjusted_op0, const0_rtx, NE, |
3673 | compute_mode, label1); | |
55c2d311 TG |
3674 | emit_move_insn (quotient, const0_rtx); |
3675 | emit_jump_insn (gen_jump (label2)); | |
3676 | emit_barrier (); | |
3677 | emit_label (label1); | |
3678 | expand_dec (adjusted_op0, const1_rtx); | |
3679 | tem = expand_binop (compute_mode, udiv_optab, adjusted_op0, op1, | |
3680 | quotient, 1, OPTAB_LIB_WIDEN); | |
3681 | if (tem != quotient) | |
3682 | emit_move_insn (quotient, tem); | |
3683 | expand_inc (quotient, const1_rtx); | |
3684 | emit_label (label2); | |
44037a66 | 3685 | } |
55c2d311 TG |
3686 | } |
3687 | else /* signed */ | |
3688 | { | |
73f27728 RK |
3689 | if (op1_is_constant && EXACT_POWER_OF_2_OR_ZERO_P (INTVAL (op1)) |
3690 | && INTVAL (op1) >= 0) | |
3691 | { | |
3692 | /* This is extremely similar to the code for the unsigned case | |
3693 | above. For 2.7 we should merge these variants, but for | |
3694 | 2.6.1 I don't want to touch the code for unsigned since that | |
3695 | get used in C. The signed case will only be used by other | |
3696 | languages (Ada). */ | |
3697 | ||
3698 | rtx t1, t2, t3; | |
3699 | unsigned HOST_WIDE_INT d = INTVAL (op1); | |
3700 | t1 = expand_shift (RSHIFT_EXPR, compute_mode, op0, | |
3701 | build_int_2 (floor_log2 (d), 0), | |
3702 | tquotient, 0); | |
3703 | t2 = expand_binop (compute_mode, and_optab, op0, | |
3704 | GEN_INT (d - 1), | |
3705 | NULL_RTX, 1, OPTAB_LIB_WIDEN); | |
3706 | t3 = gen_reg_rtx (compute_mode); | |
3707 | t3 = emit_store_flag (t3, NE, t2, const0_rtx, | |
3708 | compute_mode, 1, 1); | |
3709 | if (t3 == 0) | |
3710 | { | |
3711 | rtx lab; | |
3712 | lab = gen_label_rtx (); | |
f5963e61 | 3713 | do_cmp_and_jump (t2, const0_rtx, EQ, compute_mode, lab); |
73f27728 RK |
3714 | expand_inc (t1, const1_rtx); |
3715 | emit_label (lab); | |
3716 | quotient = t1; | |
3717 | } | |
3718 | else | |
38a448ca RH |
3719 | quotient = force_operand (gen_rtx_PLUS (compute_mode, |
3720 | t1, t3), | |
73f27728 RK |
3721 | tquotient); |
3722 | break; | |
3723 | } | |
3724 | ||
55c2d311 TG |
3725 | /* Try using an instruction that produces both the quotient and |
3726 | remainder, using truncation. We can easily compensate the | |
3727 | quotient or remainder to get ceiling rounding, once we have the | |
3728 | remainder. Notice that we compute also the final remainder | |
3729 | value here, and return the result right away. */ | |
a45cf58c | 3730 | if (target == 0 || GET_MODE (target) != compute_mode) |
55c2d311 TG |
3731 | target = gen_reg_rtx (compute_mode); |
3732 | if (rem_flag) | |
3733 | { | |
668443c9 RK |
3734 | remainder= (GET_CODE (target) == REG |
3735 | ? target : gen_reg_rtx (compute_mode)); | |
55c2d311 TG |
3736 | quotient = gen_reg_rtx (compute_mode); |
3737 | } | |
3738 | else | |
3739 | { | |
668443c9 RK |
3740 | quotient = (GET_CODE (target) == REG |
3741 | ? target : gen_reg_rtx (compute_mode)); | |
55c2d311 TG |
3742 | remainder = gen_reg_rtx (compute_mode); |
3743 | } | |
3744 | ||
3745 | if (expand_twoval_binop (sdivmod_optab, op0, op1, quotient, | |
3746 | remainder, 0)) | |
3747 | { | |
3748 | /* This could be computed with a branch-less sequence. | |
3749 | Save that for later. */ | |
3750 | rtx tem; | |
3751 | rtx label = gen_label_rtx (); | |
f5963e61 JL |
3752 | do_cmp_and_jump (remainder, const0_rtx, EQ, |
3753 | compute_mode, label); | |
55c2d311 TG |
3754 | tem = expand_binop (compute_mode, xor_optab, op0, op1, |
3755 | NULL_RTX, 0, OPTAB_WIDEN); | |
f5963e61 | 3756 | do_cmp_and_jump (tem, const0_rtx, LT, compute_mode, label); |
55c2d311 TG |
3757 | expand_inc (quotient, const1_rtx); |
3758 | expand_dec (remainder, op1); | |
3759 | emit_label (label); | |
c8dbc8ca | 3760 | return gen_lowpart (mode, rem_flag ? remainder : quotient); |
55c2d311 TG |
3761 | } |
3762 | ||
3763 | /* No luck with division elimination or divmod. Have to do it | |
3764 | by conditionally adjusting op0 *and* the result. */ | |
44037a66 | 3765 | { |
55c2d311 TG |
3766 | rtx label1, label2, label3, label4, label5; |
3767 | rtx adjusted_op0; | |
3768 | rtx tem; | |
3769 | ||
3770 | quotient = gen_reg_rtx (compute_mode); | |
3771 | adjusted_op0 = copy_to_mode_reg (compute_mode, op0); | |
3772 | label1 = gen_label_rtx (); | |
3773 | label2 = gen_label_rtx (); | |
3774 | label3 = gen_label_rtx (); | |
3775 | label4 = gen_label_rtx (); | |
3776 | label5 = gen_label_rtx (); | |
f5963e61 JL |
3777 | do_cmp_and_jump (op1, const0_rtx, LT, compute_mode, label2); |
3778 | do_cmp_and_jump (adjusted_op0, const0_rtx, GT, | |
3779 | compute_mode, label1); | |
55c2d311 TG |
3780 | tem = expand_binop (compute_mode, sdiv_optab, adjusted_op0, op1, |
3781 | quotient, 0, OPTAB_LIB_WIDEN); | |
3782 | if (tem != quotient) | |
3783 | emit_move_insn (quotient, tem); | |
3784 | emit_jump_insn (gen_jump (label5)); | |
3785 | emit_barrier (); | |
3786 | emit_label (label1); | |
3787 | expand_dec (adjusted_op0, const1_rtx); | |
3788 | emit_jump_insn (gen_jump (label4)); | |
3789 | emit_barrier (); | |
3790 | emit_label (label2); | |
f5963e61 JL |
3791 | do_cmp_and_jump (adjusted_op0, const0_rtx, LT, |
3792 | compute_mode, label3); | |
55c2d311 TG |
3793 | tem = expand_binop (compute_mode, sdiv_optab, adjusted_op0, op1, |
3794 | quotient, 0, OPTAB_LIB_WIDEN); | |
3795 | if (tem != quotient) | |
3796 | emit_move_insn (quotient, tem); | |
3797 | emit_jump_insn (gen_jump (label5)); | |
3798 | emit_barrier (); | |
3799 | emit_label (label3); | |
3800 | expand_inc (adjusted_op0, const1_rtx); | |
3801 | emit_label (label4); | |
3802 | tem = expand_binop (compute_mode, sdiv_optab, adjusted_op0, op1, | |
3803 | quotient, 0, OPTAB_LIB_WIDEN); | |
3804 | if (tem != quotient) | |
3805 | emit_move_insn (quotient, tem); | |
3806 | expand_inc (quotient, const1_rtx); | |
3807 | emit_label (label5); | |
44037a66 | 3808 | } |
55c2d311 TG |
3809 | } |
3810 | break; | |
bc1c7e93 | 3811 | |
55c2d311 TG |
3812 | case EXACT_DIV_EXPR: |
3813 | if (op1_is_constant && HOST_BITS_PER_WIDE_INT >= size) | |
3814 | { | |
3815 | HOST_WIDE_INT d = INTVAL (op1); | |
3816 | unsigned HOST_WIDE_INT ml; | |
91ce572a | 3817 | int pre_shift; |
55c2d311 TG |
3818 | rtx t1; |
3819 | ||
91ce572a CC |
3820 | pre_shift = floor_log2 (d & -d); |
3821 | ml = invert_mod2n (d >> pre_shift, size); | |
3822 | t1 = expand_shift (RSHIFT_EXPR, compute_mode, op0, | |
3823 | build_int_2 (pre_shift, 0), NULL_RTX, unsignedp); | |
69107307 AO |
3824 | quotient = expand_mult (compute_mode, t1, |
3825 | GEN_INT (trunc_int_for_mode | |
3826 | (ml, compute_mode)), | |
3827 | NULL_RTX, 0); | |
55c2d311 TG |
3828 | |
3829 | insn = get_last_insn (); | |
7e5bda2c AM |
3830 | set_unique_reg_note (insn, |
3831 | REG_EQUAL, | |
3832 | gen_rtx_fmt_ee (unsignedp ? UDIV : DIV, | |
3833 | compute_mode, | |
3834 | op0, op1)); | |
55c2d311 TG |
3835 | } |
3836 | break; | |
3837 | ||
3838 | case ROUND_DIV_EXPR: | |
3839 | case ROUND_MOD_EXPR: | |
69f61901 RK |
3840 | if (unsignedp) |
3841 | { | |
3842 | rtx tem; | |
3843 | rtx label; | |
3844 | label = gen_label_rtx (); | |
3845 | quotient = gen_reg_rtx (compute_mode); | |
3846 | remainder = gen_reg_rtx (compute_mode); | |
3847 | if (expand_twoval_binop (udivmod_optab, op0, op1, quotient, remainder, 1) == 0) | |
3848 | { | |
3849 | rtx tem; | |
3850 | quotient = expand_binop (compute_mode, udiv_optab, op0, op1, | |
3851 | quotient, 1, OPTAB_LIB_WIDEN); | |
3852 | tem = expand_mult (compute_mode, quotient, op1, NULL_RTX, 1); | |
3853 | remainder = expand_binop (compute_mode, sub_optab, op0, tem, | |
3854 | remainder, 1, OPTAB_LIB_WIDEN); | |
3855 | } | |
3856 | tem = plus_constant (op1, -1); | |
3857 | tem = expand_shift (RSHIFT_EXPR, compute_mode, tem, | |
3858 | build_int_2 (1, 0), NULL_RTX, 1); | |
f5963e61 | 3859 | do_cmp_and_jump (remainder, tem, LEU, compute_mode, label); |
69f61901 RK |
3860 | expand_inc (quotient, const1_rtx); |
3861 | expand_dec (remainder, op1); | |
3862 | emit_label (label); | |
3863 | } | |
3864 | else | |
3865 | { | |
3866 | rtx abs_rem, abs_op1, tem, mask; | |
3867 | rtx label; | |
3868 | label = gen_label_rtx (); | |
3869 | quotient = gen_reg_rtx (compute_mode); | |
3870 | remainder = gen_reg_rtx (compute_mode); | |
3871 | if (expand_twoval_binop (sdivmod_optab, op0, op1, quotient, remainder, 0) == 0) | |
3872 | { | |
3873 | rtx tem; | |
3874 | quotient = expand_binop (compute_mode, sdiv_optab, op0, op1, | |
3875 | quotient, 0, OPTAB_LIB_WIDEN); | |
3876 | tem = expand_mult (compute_mode, quotient, op1, NULL_RTX, 0); | |
3877 | remainder = expand_binop (compute_mode, sub_optab, op0, tem, | |
3878 | remainder, 0, OPTAB_LIB_WIDEN); | |
3879 | } | |
91ce572a CC |
3880 | abs_rem = expand_abs (compute_mode, remainder, NULL_RTX, 1, 0); |
3881 | abs_op1 = expand_abs (compute_mode, op1, NULL_RTX, 1, 0); | |
69f61901 RK |
3882 | tem = expand_shift (LSHIFT_EXPR, compute_mode, abs_rem, |
3883 | build_int_2 (1, 0), NULL_RTX, 1); | |
f5963e61 | 3884 | do_cmp_and_jump (tem, abs_op1, LTU, compute_mode, label); |
69f61901 RK |
3885 | tem = expand_binop (compute_mode, xor_optab, op0, op1, |
3886 | NULL_RTX, 0, OPTAB_WIDEN); | |
3887 | mask = expand_shift (RSHIFT_EXPR, compute_mode, tem, | |
3888 | build_int_2 (size - 1, 0), NULL_RTX, 0); | |
3889 | tem = expand_binop (compute_mode, xor_optab, mask, const1_rtx, | |
3890 | NULL_RTX, 0, OPTAB_WIDEN); | |
3891 | tem = expand_binop (compute_mode, sub_optab, tem, mask, | |
3892 | NULL_RTX, 0, OPTAB_WIDEN); | |
3893 | expand_inc (quotient, tem); | |
3894 | tem = expand_binop (compute_mode, xor_optab, mask, op1, | |
3895 | NULL_RTX, 0, OPTAB_WIDEN); | |
3896 | tem = expand_binop (compute_mode, sub_optab, tem, mask, | |
3897 | NULL_RTX, 0, OPTAB_WIDEN); | |
3898 | expand_dec (remainder, tem); | |
3899 | emit_label (label); | |
3900 | } | |
3901 | return gen_lowpart (mode, rem_flag ? remainder : quotient); | |
e9a25f70 JL |
3902 | |
3903 | default: | |
3904 | abort (); | |
55c2d311 | 3905 | } |
44037a66 | 3906 | |
55c2d311 | 3907 | if (quotient == 0) |
44037a66 | 3908 | { |
a45cf58c RK |
3909 | if (target && GET_MODE (target) != compute_mode) |
3910 | target = 0; | |
3911 | ||
55c2d311 | 3912 | if (rem_flag) |
44037a66 | 3913 | { |
32fdf36b | 3914 | /* Try to produce the remainder without producing the quotient. |
d6a7951f JM |
3915 | If we seem to have a divmod pattern that does not require widening, |
3916 | don't try widening here. We should really have an WIDEN argument | |
32fdf36b TG |
3917 | to expand_twoval_binop, since what we'd really like to do here is |
3918 | 1) try a mod insn in compute_mode | |
3919 | 2) try a divmod insn in compute_mode | |
3920 | 3) try a div insn in compute_mode and multiply-subtract to get | |
3921 | remainder | |
3922 | 4) try the same things with widening allowed. */ | |
3923 | remainder | |
3924 | = sign_expand_binop (compute_mode, umod_optab, smod_optab, | |
3925 | op0, op1, target, | |
3926 | unsignedp, | |
3927 | ((optab2->handlers[(int) compute_mode].insn_code | |
3928 | != CODE_FOR_nothing) | |
3929 | ? OPTAB_DIRECT : OPTAB_WIDEN)); | |
55c2d311 | 3930 | if (remainder == 0) |
44037a66 TG |
3931 | { |
3932 | /* No luck there. Can we do remainder and divide at once | |
3933 | without a library call? */ | |
55c2d311 TG |
3934 | remainder = gen_reg_rtx (compute_mode); |
3935 | if (! expand_twoval_binop ((unsignedp | |
3936 | ? udivmod_optab | |
3937 | : sdivmod_optab), | |
3938 | op0, op1, | |
3939 | NULL_RTX, remainder, unsignedp)) | |
3940 | remainder = 0; | |
44037a66 | 3941 | } |
55c2d311 TG |
3942 | |
3943 | if (remainder) | |
3944 | return gen_lowpart (mode, remainder); | |
44037a66 | 3945 | } |
44037a66 | 3946 | |
dc38b292 RK |
3947 | /* Produce the quotient. Try a quotient insn, but not a library call. |
3948 | If we have a divmod in this mode, use it in preference to widening | |
3949 | the div (for this test we assume it will not fail). Note that optab2 | |
3950 | is set to the one of the two optabs that the call below will use. */ | |
3951 | quotient | |
3952 | = sign_expand_binop (compute_mode, udiv_optab, sdiv_optab, | |
3953 | op0, op1, rem_flag ? NULL_RTX : target, | |
3954 | unsignedp, | |
3955 | ((optab2->handlers[(int) compute_mode].insn_code | |
3956 | != CODE_FOR_nothing) | |
3957 | ? OPTAB_DIRECT : OPTAB_WIDEN)); | |
3958 | ||
55c2d311 | 3959 | if (quotient == 0) |
44037a66 TG |
3960 | { |
3961 | /* No luck there. Try a quotient-and-remainder insn, | |
3962 | keeping the quotient alone. */ | |
55c2d311 | 3963 | quotient = gen_reg_rtx (compute_mode); |
44037a66 | 3964 | if (! expand_twoval_binop (unsignedp ? udivmod_optab : sdivmod_optab, |
55c2d311 TG |
3965 | op0, op1, |
3966 | quotient, NULL_RTX, unsignedp)) | |
3967 | { | |
3968 | quotient = 0; | |
3969 | if (! rem_flag) | |
3970 | /* Still no luck. If we are not computing the remainder, | |
3971 | use a library call for the quotient. */ | |
3972 | quotient = sign_expand_binop (compute_mode, | |
3973 | udiv_optab, sdiv_optab, | |
3974 | op0, op1, target, | |
3975 | unsignedp, OPTAB_LIB_WIDEN); | |
3976 | } | |
44037a66 | 3977 | } |
44037a66 TG |
3978 | } |
3979 | ||
44037a66 TG |
3980 | if (rem_flag) |
3981 | { | |
a45cf58c RK |
3982 | if (target && GET_MODE (target) != compute_mode) |
3983 | target = 0; | |
3984 | ||
55c2d311 | 3985 | if (quotient == 0) |
44037a66 | 3986 | /* No divide instruction either. Use library for remainder. */ |
55c2d311 TG |
3987 | remainder = sign_expand_binop (compute_mode, umod_optab, smod_optab, |
3988 | op0, op1, target, | |
3989 | unsignedp, OPTAB_LIB_WIDEN); | |
44037a66 TG |
3990 | else |
3991 | { | |
3992 | /* We divided. Now finish doing X - Y * (X / Y). */ | |
55c2d311 TG |
3993 | remainder = expand_mult (compute_mode, quotient, op1, |
3994 | NULL_RTX, unsignedp); | |
3995 | remainder = expand_binop (compute_mode, sub_optab, op0, | |
3996 | remainder, target, unsignedp, | |
3997 | OPTAB_LIB_WIDEN); | |
44037a66 TG |
3998 | } |
3999 | } | |
4000 | ||
55c2d311 | 4001 | return gen_lowpart (mode, rem_flag ? remainder : quotient); |
44037a66 TG |
4002 | } |
4003 | \f | |
4004 | /* Return a tree node with data type TYPE, describing the value of X. | |
4005 | Usually this is an RTL_EXPR, if there is no obvious better choice. | |
4006 | X may be an expression, however we only support those expressions | |
6d2f8887 | 4007 | generated by loop.c. */ |
44037a66 TG |
4008 | |
4009 | tree | |
4010 | make_tree (type, x) | |
4011 | tree type; | |
4012 | rtx x; | |
4013 | { | |
4014 | tree t; | |
4015 | ||
4016 | switch (GET_CODE (x)) | |
4017 | { | |
4018 | case CONST_INT: | |
4019 | t = build_int_2 (INTVAL (x), | |
172f4957 DM |
4020 | (TREE_UNSIGNED (type) |
4021 | && (GET_MODE_BITSIZE (TYPE_MODE (type)) < HOST_BITS_PER_WIDE_INT)) | |
4022 | || INTVAL (x) >= 0 ? 0 : -1); | |
44037a66 TG |
4023 | TREE_TYPE (t) = type; |
4024 | return t; | |
4025 | ||
4026 | case CONST_DOUBLE: | |
4027 | if (GET_MODE (x) == VOIDmode) | |
4028 | { | |
4029 | t = build_int_2 (CONST_DOUBLE_LOW (x), CONST_DOUBLE_HIGH (x)); | |
4030 | TREE_TYPE (t) = type; | |
4031 | } | |
4032 | else | |
4033 | { | |
4034 | REAL_VALUE_TYPE d; | |
4035 | ||
4036 | REAL_VALUE_FROM_CONST_DOUBLE (d, x); | |
4037 | t = build_real (type, d); | |
4038 | } | |
4039 | ||
4040 | return t; | |
4041 | ||
4042 | case PLUS: | |
4043 | return fold (build (PLUS_EXPR, type, make_tree (type, XEXP (x, 0)), | |
4044 | make_tree (type, XEXP (x, 1)))); | |
4045 | ||
4046 | case MINUS: | |
4047 | return fold (build (MINUS_EXPR, type, make_tree (type, XEXP (x, 0)), | |
4048 | make_tree (type, XEXP (x, 1)))); | |
4049 | ||
4050 | case NEG: | |
4051 | return fold (build1 (NEGATE_EXPR, type, make_tree (type, XEXP (x, 0)))); | |
4052 | ||
4053 | case MULT: | |
4054 | return fold (build (MULT_EXPR, type, make_tree (type, XEXP (x, 0)), | |
4055 | make_tree (type, XEXP (x, 1)))); | |
4056 | ||
4057 | case ASHIFT: | |
4058 | return fold (build (LSHIFT_EXPR, type, make_tree (type, XEXP (x, 0)), | |
4059 | make_tree (type, XEXP (x, 1)))); | |
4060 | ||
4061 | case LSHIFTRT: | |
4062 | return fold (convert (type, | |
4063 | build (RSHIFT_EXPR, unsigned_type (type), | |
4064 | make_tree (unsigned_type (type), | |
4065 | XEXP (x, 0)), | |
4066 | make_tree (type, XEXP (x, 1))))); | |
4067 | ||
4068 | case ASHIFTRT: | |
4069 | return fold (convert (type, | |
4070 | build (RSHIFT_EXPR, signed_type (type), | |
4071 | make_tree (signed_type (type), XEXP (x, 0)), | |
4072 | make_tree (type, XEXP (x, 1))))); | |
4073 | ||
4074 | case DIV: | |
4075 | if (TREE_CODE (type) != REAL_TYPE) | |
4076 | t = signed_type (type); | |
4077 | else | |
4078 | t = type; | |
4079 | ||
4080 | return fold (convert (type, | |
4081 | build (TRUNC_DIV_EXPR, t, | |
4082 | make_tree (t, XEXP (x, 0)), | |
4083 | make_tree (t, XEXP (x, 1))))); | |
4084 | case UDIV: | |
4085 | t = unsigned_type (type); | |
4086 | return fold (convert (type, | |
4087 | build (TRUNC_DIV_EXPR, t, | |
4088 | make_tree (t, XEXP (x, 0)), | |
4089 | make_tree (t, XEXP (x, 1))))); | |
4090 | default: | |
4091 | t = make_node (RTL_EXPR); | |
4092 | TREE_TYPE (t) = type; | |
d1608933 RK |
4093 | |
4094 | #ifdef POINTERS_EXTEND_UNSIGNED | |
4095 | /* If TYPE is a POINTER_TYPE, X might be Pmode with TYPE_MODE being | |
4096 | ptr_mode. So convert. */ | |
4097 | if (POINTER_TYPE_P (type) && GET_MODE (x) != TYPE_MODE (type)) | |
4098 | x = convert_memory_address (TYPE_MODE (type), x); | |
4099 | #endif | |
4100 | ||
44037a66 TG |
4101 | RTL_EXPR_RTL (t) = x; |
4102 | /* There are no insns to be output | |
4103 | when this rtl_expr is used. */ | |
4104 | RTL_EXPR_SEQUENCE (t) = 0; | |
4105 | return t; | |
4106 | } | |
4107 | } | |
4108 | ||
4109 | /* Return an rtx representing the value of X * MULT + ADD. | |
4110 | TARGET is a suggestion for where to store the result (an rtx). | |
4111 | MODE is the machine mode for the computation. | |
4112 | X and MULT must have mode MODE. ADD may have a different mode. | |
4113 | So can X (defaults to same as MODE). | |
4114 | UNSIGNEDP is non-zero to do unsigned multiplication. | |
4115 | This may emit insns. */ | |
4116 | ||
4117 | rtx | |
4118 | expand_mult_add (x, target, mult, add, mode, unsignedp) | |
4119 | rtx x, target, mult, add; | |
4120 | enum machine_mode mode; | |
4121 | int unsignedp; | |
4122 | { | |
4123 | tree type = type_for_mode (mode, unsignedp); | |
4124 | tree add_type = (GET_MODE (add) == VOIDmode | |
36d747f6 | 4125 | ? type : type_for_mode (GET_MODE (add), unsignedp)); |
44037a66 TG |
4126 | tree result = fold (build (PLUS_EXPR, type, |
4127 | fold (build (MULT_EXPR, type, | |
4128 | make_tree (type, x), | |
4129 | make_tree (type, mult))), | |
4130 | make_tree (add_type, add))); | |
4131 | ||
4132 | return expand_expr (result, target, VOIDmode, 0); | |
4133 | } | |
4134 | \f | |
4135 | /* Compute the logical-and of OP0 and OP1, storing it in TARGET | |
4136 | and returning TARGET. | |
4137 | ||
4138 | If TARGET is 0, a pseudo-register or constant is returned. */ | |
4139 | ||
4140 | rtx | |
4141 | expand_and (op0, op1, target) | |
4142 | rtx op0, op1, target; | |
4143 | { | |
4144 | enum machine_mode mode = VOIDmode; | |
4145 | rtx tem; | |
4146 | ||
4147 | if (GET_MODE (op0) != VOIDmode) | |
4148 | mode = GET_MODE (op0); | |
4149 | else if (GET_MODE (op1) != VOIDmode) | |
4150 | mode = GET_MODE (op1); | |
4151 | ||
4152 | if (mode != VOIDmode) | |
4153 | tem = expand_binop (mode, and_optab, op0, op1, target, 0, OPTAB_LIB_WIDEN); | |
4154 | else if (GET_CODE (op0) == CONST_INT && GET_CODE (op1) == CONST_INT) | |
b1ec3c92 | 4155 | tem = GEN_INT (INTVAL (op0) & INTVAL (op1)); |
44037a66 TG |
4156 | else |
4157 | abort (); | |
4158 | ||
4159 | if (target == 0) | |
4160 | target = tem; | |
4161 | else if (tem != target) | |
4162 | emit_move_insn (target, tem); | |
4163 | return target; | |
4164 | } | |
4165 | \f | |
4166 | /* Emit a store-flags instruction for comparison CODE on OP0 and OP1 | |
4167 | and storing in TARGET. Normally return TARGET. | |
4168 | Return 0 if that cannot be done. | |
4169 | ||
4170 | MODE is the mode to use for OP0 and OP1 should they be CONST_INTs. If | |
4171 | it is VOIDmode, they cannot both be CONST_INT. | |
4172 | ||
4173 | UNSIGNEDP is for the case where we have to widen the operands | |
4174 | to perform the operation. It says to use zero-extension. | |
4175 | ||
4176 | NORMALIZEP is 1 if we should convert the result to be either zero | |
373e7d69 | 4177 | or one. Normalize is -1 if we should convert the result to be |
44037a66 TG |
4178 | either zero or -1. If NORMALIZEP is zero, the result will be left |
4179 | "raw" out of the scc insn. */ | |
4180 | ||
4181 | rtx | |
4182 | emit_store_flag (target, code, op0, op1, mode, unsignedp, normalizep) | |
4183 | rtx target; | |
4184 | enum rtx_code code; | |
4185 | rtx op0, op1; | |
4186 | enum machine_mode mode; | |
4187 | int unsignedp; | |
4188 | int normalizep; | |
4189 | { | |
4190 | rtx subtarget; | |
4191 | enum insn_code icode; | |
4192 | enum machine_mode compare_mode; | |
4193 | enum machine_mode target_mode = GET_MODE (target); | |
4194 | rtx tem; | |
db2f8a07 | 4195 | rtx last = get_last_insn (); |
44037a66 TG |
4196 | rtx pattern, comparison; |
4197 | ||
20d32cc2 ZW |
4198 | /* ??? Ok to do this and then fail? */ |
4199 | op0 = protect_from_queue (op0, 0); | |
4200 | op1 = protect_from_queue (op1, 0); | |
4201 | ||
b30f05db BS |
4202 | if (unsignedp) |
4203 | code = unsigned_condition (code); | |
4204 | ||
c2615a67 RK |
4205 | /* If one operand is constant, make it the second one. Only do this |
4206 | if the other operand is not constant as well. */ | |
4207 | ||
8c9864f3 | 4208 | if (swap_commutative_operands_p (op0, op1)) |
c2615a67 RK |
4209 | { |
4210 | tem = op0; | |
4211 | op0 = op1; | |
4212 | op1 = tem; | |
4213 | code = swap_condition (code); | |
4214 | } | |
4215 | ||
6405e07b DE |
4216 | if (mode == VOIDmode) |
4217 | mode = GET_MODE (op0); | |
4218 | ||
44037a66 TG |
4219 | /* For some comparisons with 1 and -1, we can convert this to |
4220 | comparisons with zero. This will often produce more opportunities for | |
0f41302f | 4221 | store-flag insns. */ |
44037a66 TG |
4222 | |
4223 | switch (code) | |
4224 | { | |
4225 | case LT: | |
4226 | if (op1 == const1_rtx) | |
4227 | op1 = const0_rtx, code = LE; | |
4228 | break; | |
4229 | case LE: | |
4230 | if (op1 == constm1_rtx) | |
4231 | op1 = const0_rtx, code = LT; | |
4232 | break; | |
4233 | case GE: | |
4234 | if (op1 == const1_rtx) | |
4235 | op1 = const0_rtx, code = GT; | |
4236 | break; | |
4237 | case GT: | |
4238 | if (op1 == constm1_rtx) | |
4239 | op1 = const0_rtx, code = GE; | |
4240 | break; | |
4241 | case GEU: | |
4242 | if (op1 == const1_rtx) | |
4243 | op1 = const0_rtx, code = NE; | |
4244 | break; | |
4245 | case LTU: | |
4246 | if (op1 == const1_rtx) | |
4247 | op1 = const0_rtx, code = EQ; | |
4248 | break; | |
e9a25f70 JL |
4249 | default: |
4250 | break; | |
44037a66 TG |
4251 | } |
4252 | ||
6912b84b RK |
4253 | /* If we are comparing a double-word integer with zero, we can convert |
4254 | the comparison into one involving a single word. */ | |
4255 | if (GET_MODE_BITSIZE (mode) == BITS_PER_WORD * 2 | |
4256 | && GET_MODE_CLASS (mode) == MODE_INT | |
4257 | && op1 == const0_rtx) | |
4258 | { | |
4259 | if (code == EQ || code == NE) | |
4260 | { | |
4261 | /* Do a logical OR of the two words and compare the result. */ | |
4262 | rtx op0h = gen_highpart (word_mode, op0); | |
4263 | rtx op0l = gen_lowpart (word_mode, op0); | |
4264 | rtx op0both = expand_binop (word_mode, ior_optab, op0h, op0l, | |
4265 | NULL_RTX, unsignedp, OPTAB_DIRECT); | |
4266 | if (op0both != 0) | |
4267 | return emit_store_flag (target, code, op0both, op1, word_mode, | |
4268 | unsignedp, normalizep); | |
4269 | } | |
4270 | else if (code == LT || code == GE) | |
4271 | /* If testing the sign bit, can just test on high word. */ | |
4272 | return emit_store_flag (target, code, gen_highpart (word_mode, op0), | |
4273 | op1, word_mode, unsignedp, normalizep); | |
4274 | } | |
4275 | ||
44037a66 TG |
4276 | /* From now on, we won't change CODE, so set ICODE now. */ |
4277 | icode = setcc_gen_code[(int) code]; | |
4278 | ||
4279 | /* If this is A < 0 or A >= 0, we can do this by taking the ones | |
4280 | complement of A (for GE) and shifting the sign bit to the low bit. */ | |
4281 | if (op1 == const0_rtx && (code == LT || code == GE) | |
4282 | && GET_MODE_CLASS (mode) == MODE_INT | |
4283 | && (normalizep || STORE_FLAG_VALUE == 1 | |
b1ec3c92 | 4284 | || (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT |
12dd565f | 4285 | && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode)) |
b1ec3c92 | 4286 | == (HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))))) |
44037a66 | 4287 | { |
8deb7047 | 4288 | subtarget = target; |
44037a66 TG |
4289 | |
4290 | /* If the result is to be wider than OP0, it is best to convert it | |
4291 | first. If it is to be narrower, it is *incorrect* to convert it | |
4292 | first. */ | |
4293 | if (GET_MODE_SIZE (target_mode) > GET_MODE_SIZE (mode)) | |
4294 | { | |
b3d4e1b2 | 4295 | op0 = protect_from_queue (op0, 0); |
81722fa9 | 4296 | op0 = convert_modes (target_mode, mode, op0, 0); |
44037a66 TG |
4297 | mode = target_mode; |
4298 | } | |
4299 | ||
4300 | if (target_mode != mode) | |
4301 | subtarget = 0; | |
4302 | ||
4303 | if (code == GE) | |
1d6eaf3d RK |
4304 | op0 = expand_unop (mode, one_cmpl_optab, op0, |
4305 | ((STORE_FLAG_VALUE == 1 || normalizep) | |
4306 | ? 0 : subtarget), 0); | |
44037a66 | 4307 | |
1d6eaf3d | 4308 | if (STORE_FLAG_VALUE == 1 || normalizep) |
44037a66 TG |
4309 | /* If we are supposed to produce a 0/1 value, we want to do |
4310 | a logical shift from the sign bit to the low-order bit; for | |
4311 | a -1/0 value, we do an arithmetic shift. */ | |
4312 | op0 = expand_shift (RSHIFT_EXPR, mode, op0, | |
4313 | size_int (GET_MODE_BITSIZE (mode) - 1), | |
4314 | subtarget, normalizep != -1); | |
4315 | ||
4316 | if (mode != target_mode) | |
c2ec26b8 | 4317 | op0 = convert_modes (target_mode, mode, op0, 0); |
44037a66 TG |
4318 | |
4319 | return op0; | |
4320 | } | |
4321 | ||
4322 | if (icode != CODE_FOR_nothing) | |
4323 | { | |
a995e389 RH |
4324 | insn_operand_predicate_fn pred; |
4325 | ||
44037a66 TG |
4326 | /* We think we may be able to do this with a scc insn. Emit the |
4327 | comparison and then the scc insn. | |
4328 | ||
4329 | compare_from_rtx may call emit_queue, which would be deleted below | |
3bdf5848 BS |
4330 | if the scc insn fails. So call it ourselves before setting LAST. |
4331 | Likewise for do_pending_stack_adjust. */ | |
44037a66 TG |
4332 | |
4333 | emit_queue (); | |
3bdf5848 | 4334 | do_pending_stack_adjust (); |
44037a66 TG |
4335 | last = get_last_insn (); |
4336 | ||
b1ec3c92 | 4337 | comparison |
d43e0b7d | 4338 | = compare_from_rtx (op0, op1, code, unsignedp, mode, NULL_RTX); |
44037a66 TG |
4339 | if (GET_CODE (comparison) == CONST_INT) |
4340 | return (comparison == const0_rtx ? const0_rtx | |
4341 | : normalizep == 1 ? const1_rtx | |
4342 | : normalizep == -1 ? constm1_rtx | |
4343 | : const_true_rtx); | |
4344 | ||
8f08e8c0 JL |
4345 | /* The code of COMPARISON may not match CODE if compare_from_rtx |
4346 | decided to swap its operands and reverse the original code. | |
c2615a67 | 4347 | |
8f08e8c0 JL |
4348 | We know that compare_from_rtx returns either a CONST_INT or |
4349 | a new comparison code, so it is safe to just extract the | |
4350 | code from COMPARISON. */ | |
4351 | code = GET_CODE (comparison); | |
8deb7047 | 4352 | |
44037a66 | 4353 | /* Get a reference to the target in the proper mode for this insn. */ |
a995e389 | 4354 | compare_mode = insn_data[(int) icode].operand[0].mode; |
44037a66 | 4355 | subtarget = target; |
a995e389 | 4356 | pred = insn_data[(int) icode].operand[0].predicate; |
44037a66 | 4357 | if (preserve_subexpressions_p () |
a995e389 | 4358 | || ! (*pred) (subtarget, compare_mode)) |
44037a66 TG |
4359 | subtarget = gen_reg_rtx (compare_mode); |
4360 | ||
4361 | pattern = GEN_FCN (icode) (subtarget); | |
4362 | if (pattern) | |
4363 | { | |
4364 | emit_insn (pattern); | |
4365 | ||
4366 | /* If we are converting to a wider mode, first convert to | |
4367 | TARGET_MODE, then normalize. This produces better combining | |
4368 | opportunities on machines that have a SIGN_EXTRACT when we are | |
4369 | testing a single bit. This mostly benefits the 68k. | |
4370 | ||
4371 | If STORE_FLAG_VALUE does not have the sign bit set when | |
4372 | interpreted in COMPARE_MODE, we can do this conversion as | |
4373 | unsigned, which is usually more efficient. */ | |
4374 | if (GET_MODE_SIZE (target_mode) > GET_MODE_SIZE (compare_mode)) | |
4375 | { | |
4376 | convert_move (target, subtarget, | |
4377 | (GET_MODE_BITSIZE (compare_mode) | |
b1ec3c92 | 4378 | <= HOST_BITS_PER_WIDE_INT) |
44037a66 | 4379 | && 0 == (STORE_FLAG_VALUE |
b1ec3c92 CH |
4380 | & ((HOST_WIDE_INT) 1 |
4381 | << (GET_MODE_BITSIZE (compare_mode) -1)))); | |
44037a66 TG |
4382 | op0 = target; |
4383 | compare_mode = target_mode; | |
4384 | } | |
4385 | else | |
4386 | op0 = subtarget; | |
4387 | ||
4b980e20 RK |
4388 | /* If we want to keep subexpressions around, don't reuse our |
4389 | last target. */ | |
4390 | ||
4391 | if (preserve_subexpressions_p ()) | |
4392 | subtarget = 0; | |
4393 | ||
44037a66 TG |
4394 | /* Now normalize to the proper value in COMPARE_MODE. Sometimes |
4395 | we don't have to do anything. */ | |
4396 | if (normalizep == 0 || normalizep == STORE_FLAG_VALUE) | |
4397 | ; | |
c5c76735 JL |
4398 | /* STORE_FLAG_VALUE might be the most negative number, so write |
4399 | the comparison this way to avoid a compiler-time warning. */ | |
4400 | else if (- normalizep == STORE_FLAG_VALUE) | |
44037a66 TG |
4401 | op0 = expand_unop (compare_mode, neg_optab, op0, subtarget, 0); |
4402 | ||
4403 | /* We don't want to use STORE_FLAG_VALUE < 0 below since this | |
4404 | makes it hard to use a value of just the sign bit due to | |
4405 | ANSI integer constant typing rules. */ | |
b1ec3c92 | 4406 | else if (GET_MODE_BITSIZE (compare_mode) <= HOST_BITS_PER_WIDE_INT |
44037a66 | 4407 | && (STORE_FLAG_VALUE |
b1ec3c92 CH |
4408 | & ((HOST_WIDE_INT) 1 |
4409 | << (GET_MODE_BITSIZE (compare_mode) - 1)))) | |
44037a66 TG |
4410 | op0 = expand_shift (RSHIFT_EXPR, compare_mode, op0, |
4411 | size_int (GET_MODE_BITSIZE (compare_mode) - 1), | |
4412 | subtarget, normalizep == 1); | |
4413 | else if (STORE_FLAG_VALUE & 1) | |
4414 | { | |
4415 | op0 = expand_and (op0, const1_rtx, subtarget); | |
4416 | if (normalizep == -1) | |
4417 | op0 = expand_unop (compare_mode, neg_optab, op0, op0, 0); | |
4418 | } | |
4419 | else | |
4420 | abort (); | |
4421 | ||
4422 | /* If we were converting to a smaller mode, do the | |
4423 | conversion now. */ | |
4424 | if (target_mode != compare_mode) | |
4425 | { | |
522ae84c | 4426 | convert_move (target, op0, 0); |
44037a66 TG |
4427 | return target; |
4428 | } | |
4429 | else | |
4430 | return op0; | |
4431 | } | |
4432 | } | |
4433 | ||
db2f8a07 | 4434 | delete_insns_since (last); |
44037a66 | 4435 | |
91e66235 MM |
4436 | /* If expensive optimizations, use different pseudo registers for each |
4437 | insn, instead of reusing the same pseudo. This leads to better CSE, | |
4438 | but slows down the compiler, since there are more pseudos */ | |
4439 | subtarget = (!flag_expensive_optimizations | |
4440 | && (target_mode == mode)) ? target : NULL_RTX; | |
44037a66 TG |
4441 | |
4442 | /* If we reached here, we can't do this with a scc insn. However, there | |
4443 | are some comparisons that can be done directly. For example, if | |
4444 | this is an equality comparison of integers, we can try to exclusive-or | |
4445 | (or subtract) the two operands and use a recursive call to try the | |
4446 | comparison with zero. Don't do any of these cases if branches are | |
4447 | very cheap. */ | |
4448 | ||
c8c1bde3 | 4449 | if (BRANCH_COST > 0 |
44037a66 TG |
4450 | && GET_MODE_CLASS (mode) == MODE_INT && (code == EQ || code == NE) |
4451 | && op1 != const0_rtx) | |
4452 | { | |
4453 | tem = expand_binop (mode, xor_optab, op0, op1, subtarget, 1, | |
4454 | OPTAB_WIDEN); | |
4455 | ||
4456 | if (tem == 0) | |
4457 | tem = expand_binop (mode, sub_optab, op0, op1, subtarget, 1, | |
4458 | OPTAB_WIDEN); | |
4459 | if (tem != 0) | |
4460 | tem = emit_store_flag (target, code, tem, const0_rtx, | |
4461 | mode, unsignedp, normalizep); | |
4462 | if (tem == 0) | |
4463 | delete_insns_since (last); | |
4464 | return tem; | |
4465 | } | |
4466 | ||
4467 | /* Some other cases we can do are EQ, NE, LE, and GT comparisons with | |
4468 | the constant zero. Reject all other comparisons at this point. Only | |
4469 | do LE and GT if branches are expensive since they are expensive on | |
4470 | 2-operand machines. */ | |
4471 | ||
4472 | if (BRANCH_COST == 0 | |
4473 | || GET_MODE_CLASS (mode) != MODE_INT || op1 != const0_rtx | |
4474 | || (code != EQ && code != NE | |
4475 | && (BRANCH_COST <= 1 || (code != LE && code != GT)))) | |
4476 | return 0; | |
4477 | ||
4478 | /* See what we need to return. We can only return a 1, -1, or the | |
4479 | sign bit. */ | |
4480 | ||
4481 | if (normalizep == 0) | |
4482 | { | |
4483 | if (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1) | |
4484 | normalizep = STORE_FLAG_VALUE; | |
4485 | ||
b1ec3c92 | 4486 | else if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT |
12dd565f | 4487 | && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode)) |
c84e2712 | 4488 | == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))) |
44037a66 TG |
4489 | ; |
4490 | else | |
4491 | return 0; | |
4492 | } | |
4493 | ||
4494 | /* Try to put the result of the comparison in the sign bit. Assume we can't | |
4495 | do the necessary operation below. */ | |
4496 | ||
4497 | tem = 0; | |
4498 | ||
4499 | /* To see if A <= 0, compute (A | (A - 1)). A <= 0 iff that result has | |
4500 | the sign bit set. */ | |
4501 | ||
4502 | if (code == LE) | |
4503 | { | |
4504 | /* This is destructive, so SUBTARGET can't be OP0. */ | |
4505 | if (rtx_equal_p (subtarget, op0)) | |
4506 | subtarget = 0; | |
4507 | ||
4508 | tem = expand_binop (mode, sub_optab, op0, const1_rtx, subtarget, 0, | |
4509 | OPTAB_WIDEN); | |
4510 | if (tem) | |
4511 | tem = expand_binop (mode, ior_optab, op0, tem, subtarget, 0, | |
4512 | OPTAB_WIDEN); | |
4513 | } | |
4514 | ||
4515 | /* To see if A > 0, compute (((signed) A) << BITS) - A, where BITS is the | |
4516 | number of bits in the mode of OP0, minus one. */ | |
4517 | ||
4518 | if (code == GT) | |
4519 | { | |
4520 | if (rtx_equal_p (subtarget, op0)) | |
4521 | subtarget = 0; | |
4522 | ||
4523 | tem = expand_shift (RSHIFT_EXPR, mode, op0, | |
4524 | size_int (GET_MODE_BITSIZE (mode) - 1), | |
4525 | subtarget, 0); | |
4526 | tem = expand_binop (mode, sub_optab, tem, op0, subtarget, 0, | |
4527 | OPTAB_WIDEN); | |
4528 | } | |
4529 | ||
4530 | if (code == EQ || code == NE) | |
4531 | { | |
4532 | /* For EQ or NE, one way to do the comparison is to apply an operation | |
4533 | that converts the operand into a positive number if it is non-zero | |
4534 | or zero if it was originally zero. Then, for EQ, we subtract 1 and | |
4535 | for NE we negate. This puts the result in the sign bit. Then we | |
4536 | normalize with a shift, if needed. | |
4537 | ||
4538 | Two operations that can do the above actions are ABS and FFS, so try | |
4539 | them. If that doesn't work, and MODE is smaller than a full word, | |
36d747f6 | 4540 | we can use zero-extension to the wider mode (an unsigned conversion) |
44037a66 TG |
4541 | as the operation. */ |
4542 | ||
e6b4d09d CC |
4543 | /* Note that ABS doesn't yield a positive number for INT_MIN, but |
4544 | that is compensated by the subsequent overflow when subtracting | |
30f7a378 | 4545 | one / negating. */ |
91ce572a | 4546 | |
44037a66 TG |
4547 | if (abs_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing) |
4548 | tem = expand_unop (mode, abs_optab, op0, subtarget, 1); | |
4549 | else if (ffs_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing) | |
4550 | tem = expand_unop (mode, ffs_optab, op0, subtarget, 1); | |
4551 | else if (GET_MODE_SIZE (mode) < UNITS_PER_WORD) | |
4552 | { | |
b3d4e1b2 | 4553 | op0 = protect_from_queue (op0, 0); |
c2ec26b8 | 4554 | tem = convert_modes (word_mode, mode, op0, 1); |
81722fa9 | 4555 | mode = word_mode; |
44037a66 TG |
4556 | } |
4557 | ||
4558 | if (tem != 0) | |
4559 | { | |
4560 | if (code == EQ) | |
4561 | tem = expand_binop (mode, sub_optab, tem, const1_rtx, subtarget, | |
4562 | 0, OPTAB_WIDEN); | |
4563 | else | |
4564 | tem = expand_unop (mode, neg_optab, tem, subtarget, 0); | |
4565 | } | |
4566 | ||
4567 | /* If we couldn't do it that way, for NE we can "or" the two's complement | |
4568 | of the value with itself. For EQ, we take the one's complement of | |
4569 | that "or", which is an extra insn, so we only handle EQ if branches | |
4570 | are expensive. */ | |
4571 | ||
4572 | if (tem == 0 && (code == NE || BRANCH_COST > 1)) | |
4573 | { | |
36d747f6 RS |
4574 | if (rtx_equal_p (subtarget, op0)) |
4575 | subtarget = 0; | |
4576 | ||
44037a66 TG |
4577 | tem = expand_unop (mode, neg_optab, op0, subtarget, 0); |
4578 | tem = expand_binop (mode, ior_optab, tem, op0, subtarget, 0, | |
4579 | OPTAB_WIDEN); | |
4580 | ||
4581 | if (tem && code == EQ) | |
4582 | tem = expand_unop (mode, one_cmpl_optab, tem, subtarget, 0); | |
4583 | } | |
4584 | } | |
4585 | ||
4586 | if (tem && normalizep) | |
4587 | tem = expand_shift (RSHIFT_EXPR, mode, tem, | |
4588 | size_int (GET_MODE_BITSIZE (mode) - 1), | |
91e66235 | 4589 | subtarget, normalizep == 1); |
44037a66 | 4590 | |
91e66235 | 4591 | if (tem) |
44037a66 | 4592 | { |
91e66235 MM |
4593 | if (GET_MODE (tem) != target_mode) |
4594 | { | |
4595 | convert_move (target, tem, 0); | |
4596 | tem = target; | |
4597 | } | |
4598 | else if (!subtarget) | |
4599 | { | |
4600 | emit_move_insn (target, tem); | |
4601 | tem = target; | |
4602 | } | |
44037a66 | 4603 | } |
91e66235 | 4604 | else |
44037a66 TG |
4605 | delete_insns_since (last); |
4606 | ||
4607 | return tem; | |
4608 | } | |
04a8ee2f TG |
4609 | |
4610 | /* Like emit_store_flag, but always succeeds. */ | |
4611 | ||
4612 | rtx | |
4613 | emit_store_flag_force (target, code, op0, op1, mode, unsignedp, normalizep) | |
4614 | rtx target; | |
4615 | enum rtx_code code; | |
4616 | rtx op0, op1; | |
4617 | enum machine_mode mode; | |
4618 | int unsignedp; | |
4619 | int normalizep; | |
4620 | { | |
4621 | rtx tem, label; | |
4622 | ||
4623 | /* First see if emit_store_flag can do the job. */ | |
4624 | tem = emit_store_flag (target, code, op0, op1, mode, unsignedp, normalizep); | |
4625 | if (tem != 0) | |
4626 | return tem; | |
4627 | ||
4628 | if (normalizep == 0) | |
4629 | normalizep = 1; | |
4630 | ||
4631 | /* If this failed, we have to do this with set/compare/jump/set code. */ | |
4632 | ||
4633 | if (GET_CODE (target) != REG | |
4634 | || reg_mentioned_p (target, op0) || reg_mentioned_p (target, op1)) | |
4635 | target = gen_reg_rtx (GET_MODE (target)); | |
4636 | ||
e4565aff | 4637 | emit_move_insn (target, const1_rtx); |
04a8ee2f | 4638 | label = gen_label_rtx (); |
d43e0b7d | 4639 | do_compare_rtx_and_jump (op0, op1, code, unsignedp, mode, NULL_RTX, |
b30f05db | 4640 | NULL_RTX, label); |
04a8ee2f | 4641 | |
e4565aff | 4642 | emit_move_insn (target, const0_rtx); |
44037a66 TG |
4643 | emit_label (label); |
4644 | ||
4645 | return target; | |
4646 | } | |
f5963e61 JL |
4647 | \f |
4648 | /* Perform possibly multi-word comparison and conditional jump to LABEL | |
4649 | if ARG1 OP ARG2 true where ARG1 and ARG2 are of mode MODE | |
4650 | ||
4651 | The algorithm is based on the code in expr.c:do_jump. | |
4652 | ||
4653 | Note that this does not perform a general comparison. Only variants | |
4654 | generated within expmed.c are correctly handled, others abort (but could | |
4655 | be handled if needed). */ | |
4656 | ||
4657 | static void | |
4658 | do_cmp_and_jump (arg1, arg2, op, mode, label) | |
4659 | rtx arg1, arg2, label; | |
b30f05db BS |
4660 | enum rtx_code op; |
4661 | enum machine_mode mode; | |
f5963e61 JL |
4662 | { |
4663 | /* If this mode is an integer too wide to compare properly, | |
4664 | compare word by word. Rely on cse to optimize constant cases. */ | |
4665 | ||
1eb8759b RH |
4666 | if (GET_MODE_CLASS (mode) == MODE_INT |
4667 | && ! can_compare_p (op, mode, ccp_jump)) | |
f5963e61 JL |
4668 | { |
4669 | rtx label2 = gen_label_rtx (); | |
4670 | ||
4671 | switch (op) | |
4672 | { | |
4673 | case LTU: | |
4674 | do_jump_by_parts_greater_rtx (mode, 1, arg2, arg1, label2, label); | |
4675 | break; | |
4676 | ||
4677 | case LEU: | |
4678 | do_jump_by_parts_greater_rtx (mode, 1, arg1, arg2, label, label2); | |
4679 | break; | |
4680 | ||
4681 | case LT: | |
4682 | do_jump_by_parts_greater_rtx (mode, 0, arg2, arg1, label2, label); | |
4683 | break; | |
4684 | ||
4685 | case GT: | |
4686 | do_jump_by_parts_greater_rtx (mode, 0, arg1, arg2, label2, label); | |
4687 | break; | |
4688 | ||
4689 | case GE: | |
4690 | do_jump_by_parts_greater_rtx (mode, 0, arg2, arg1, label, label2); | |
4691 | break; | |
4692 | ||
4693 | /* do_jump_by_parts_equality_rtx compares with zero. Luckily | |
4694 | that's the only equality operations we do */ | |
4695 | case EQ: | |
4696 | if (arg2 != const0_rtx || mode != GET_MODE(arg1)) | |
c4f2c499 | 4697 | abort (); |
f5963e61 JL |
4698 | do_jump_by_parts_equality_rtx (arg1, label2, label); |
4699 | break; | |
4700 | ||
4701 | case NE: | |
4702 | if (arg2 != const0_rtx || mode != GET_MODE(arg1)) | |
c4f2c499 | 4703 | abort (); |
f5963e61 JL |
4704 | do_jump_by_parts_equality_rtx (arg1, label, label2); |
4705 | break; | |
4706 | ||
4707 | default: | |
c4f2c499 | 4708 | abort (); |
f5963e61 JL |
4709 | } |
4710 | ||
4711 | emit_label (label2); | |
4712 | } | |
4713 | else | |
d43e0b7d | 4714 | emit_cmp_and_jump_insns (arg1, arg2, op, NULL_RTX, mode, 0, label); |
f5963e61 | 4715 | } |