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44037a66 TG |
1 | /* Medium-level subroutines: convert bit-field store and extract |
2 | and shifts, multiplies and divides to rtl instructions. | |
e54d80d0 | 3 | Copyright (C) 1987, 1988, 1989, 1992, 1993 Free Software Foundation, Inc. |
44037a66 TG |
4 | |
5 | This file is part of GNU CC. | |
6 | ||
7 | GNU CC is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2, or (at your option) | |
10 | any later version. | |
11 | ||
12 | GNU CC is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GNU CC; see the file COPYING. If not, write to | |
19 | the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ | |
20 | ||
21 | ||
22 | #include "config.h" | |
23 | #include "rtl.h" | |
24 | #include "tree.h" | |
25 | #include "flags.h" | |
26 | #include "insn-flags.h" | |
27 | #include "insn-codes.h" | |
28 | #include "insn-config.h" | |
29 | #include "expr.h" | |
30 | #include "real.h" | |
31 | #include "recog.h" | |
32 | ||
33 | static rtx extract_split_bit_field (); | |
34 | static rtx extract_fixed_bit_field (); | |
35 | static void store_split_bit_field (); | |
36 | static void store_fixed_bit_field (); | |
37 | static rtx mask_rtx (); | |
38 | static rtx lshift_value (); | |
39 | ||
40 | #define CEIL(x,y) (((x) + (y) - 1) / (y)) | |
41 | ||
42 | /* Non-zero means multiply instructions are cheaper than shifts. */ | |
43 | int mult_is_very_cheap; | |
44 | ||
45 | /* Non-zero means divides or modulus operations are relatively cheap for | |
46 | powers of two, so don't use branches; emit the operation instead. | |
47 | Usually, this will mean that the MD file will emit non-branch | |
48 | sequences. */ | |
49 | ||
50 | static int sdiv_pow2_cheap, smod_pow2_cheap; | |
51 | ||
e49a094d RS |
52 | /* For compilers that support multiple targets with different word sizes, |
53 | MAX_BITS_PER_WORD contains the biggest value of BITS_PER_WORD. An example | |
54 | is the H8/300(H) compiler. */ | |
55 | ||
56 | #ifndef MAX_BITS_PER_WORD | |
57 | #define MAX_BITS_PER_WORD BITS_PER_WORD | |
58 | #endif | |
59 | ||
44037a66 | 60 | /* Cost of various pieces of RTL. */ |
b385aeda | 61 | static int add_cost, mult_cost, negate_cost, zero_cost; |
e49a094d RS |
62 | static int shift_cost[MAX_BITS_PER_WORD]; |
63 | static int shiftadd_cost[MAX_BITS_PER_WORD]; | |
64 | static int shiftsub_cost[MAX_BITS_PER_WORD]; | |
44037a66 | 65 | |
44037a66 TG |
66 | void |
67 | init_expmed () | |
68 | { | |
b385aeda | 69 | char *free_point; |
44037a66 TG |
70 | /* This is "some random pseudo register" for purposes of calling recog |
71 | to see what insns exist. */ | |
72 | rtx reg = gen_rtx (REG, word_mode, FIRST_PSEUDO_REGISTER); | |
b385aeda | 73 | rtx shift_insn, shiftadd_insn, shiftsub_insn; |
b1ec3c92 | 74 | int dummy; |
7963ac37 | 75 | int m; |
44037a66 | 76 | |
b385aeda RK |
77 | start_sequence (); |
78 | ||
79 | /* Since we are on the permanent obstack, we must be sure we save this | |
80 | spot AFTER we call start_sequence, since it will reuse the rtl it | |
81 | makes. */ | |
82 | ||
83 | free_point = (char *) oballoc (0); | |
84 | ||
172a1cb0 | 85 | zero_cost = rtx_cost (const0_rtx, 0); |
aeedc93f | 86 | add_cost = rtx_cost (gen_rtx (PLUS, word_mode, reg, reg), SET); |
7963ac37 | 87 | |
b385aeda RK |
88 | shift_insn = emit_insn (gen_rtx (SET, VOIDmode, reg, |
89 | gen_rtx (ASHIFT, word_mode, reg, | |
90 | const0_rtx))); | |
91 | ||
92 | shiftadd_insn = emit_insn (gen_rtx (SET, VOIDmode, reg, | |
93 | gen_rtx (PLUS, word_mode, | |
94 | gen_rtx (MULT, word_mode, | |
95 | reg, const0_rtx), | |
96 | reg))); | |
97 | ||
98 | shiftsub_insn = emit_insn (gen_rtx (SET, VOIDmode, reg, | |
99 | gen_rtx (MINUS, word_mode, | |
100 | gen_rtx (MULT, word_mode, | |
101 | reg, const0_rtx), | |
102 | reg))); | |
7963ac37 RK |
103 | |
104 | init_recog (); | |
b385aeda RK |
105 | |
106 | shift_cost[0] = 0; | |
107 | shiftadd_cost[0] = shiftsub_cost[0] = add_cost; | |
108 | ||
7963ac37 RK |
109 | for (m = 1; m < BITS_PER_WORD; m++) |
110 | { | |
111 | shift_cost[m] = shiftadd_cost[m] = shiftsub_cost[m] = 32000; | |
b385aeda RK |
112 | |
113 | XEXP (SET_SRC (PATTERN (shift_insn)), 1) = GEN_INT (m); | |
114 | if (recog (PATTERN (shift_insn), shift_insn, &dummy) >= 0) | |
115 | shift_cost[m] = rtx_cost (SET_SRC (PATTERN (shift_insn)), SET); | |
116 | ||
117 | XEXP (XEXP (SET_SRC (PATTERN (shiftadd_insn)), 0), 1) | |
118 | = GEN_INT ((HOST_WIDE_INT) 1 << m); | |
119 | if (recog (PATTERN (shiftadd_insn), shiftadd_insn, &dummy) >= 0) | |
dac57de0 | 120 | shiftadd_cost[m] = rtx_cost (SET_SRC (PATTERN (shiftadd_insn)), SET); |
b385aeda RK |
121 | |
122 | XEXP (XEXP (SET_SRC (PATTERN (shiftsub_insn)), 0), 1) | |
123 | = GEN_INT ((HOST_WIDE_INT) 1 << m); | |
124 | if (recog (PATTERN (shiftsub_insn), shiftsub_insn, &dummy) >= 0) | |
dac57de0 | 125 | shiftsub_cost[m] = rtx_cost (SET_SRC (PATTERN (shiftsub_insn)), SET); |
7963ac37 RK |
126 | } |
127 | ||
aeedc93f | 128 | mult_cost = rtx_cost (gen_rtx (MULT, word_mode, reg, reg), SET); |
63610db9 TG |
129 | /* For gcc 2.4 keep MULT_COST small to avoid really slow searches |
130 | in synth_mult. */ | |
131 | mult_cost = MIN (12 * add_cost, mult_cost); | |
aeedc93f | 132 | negate_cost = rtx_cost (gen_rtx (NEG, word_mode, reg), SET); |
44037a66 | 133 | |
36d747f6 | 134 | /* 999999 is chosen to avoid any plausible faster special case. */ |
44037a66 | 135 | mult_is_very_cheap |
b1ec3c92 | 136 | = (rtx_cost (gen_rtx (MULT, word_mode, reg, GEN_INT (999999)), SET) |
7963ac37 | 137 | < rtx_cost (gen_rtx (ASHIFT, word_mode, reg, GEN_INT (7)), SET)); |
44037a66 TG |
138 | |
139 | sdiv_pow2_cheap | |
b385aeda RK |
140 | = (rtx_cost (gen_rtx (DIV, word_mode, reg, GEN_INT (32)), SET) |
141 | <= 2 * add_cost); | |
44037a66 | 142 | smod_pow2_cheap |
b385aeda RK |
143 | = (rtx_cost (gen_rtx (MOD, word_mode, reg, GEN_INT (32)), SET) |
144 | <= 2 * add_cost); | |
44037a66 | 145 | |
44037a66 | 146 | /* Free the objects we just allocated. */ |
b385aeda | 147 | end_sequence (); |
44037a66 TG |
148 | obfree (free_point); |
149 | } | |
150 | ||
151 | /* Return an rtx representing minus the value of X. | |
152 | MODE is the intended mode of the result, | |
153 | useful if X is a CONST_INT. */ | |
154 | ||
155 | rtx | |
156 | negate_rtx (mode, x) | |
157 | enum machine_mode mode; | |
158 | rtx x; | |
159 | { | |
160 | if (GET_CODE (x) == CONST_INT) | |
161 | { | |
b1ec3c92 CH |
162 | HOST_WIDE_INT val = - INTVAL (x); |
163 | if (GET_MODE_BITSIZE (mode) < HOST_BITS_PER_WIDE_INT) | |
44037a66 TG |
164 | { |
165 | /* Sign extend the value from the bits that are significant. */ | |
b1ec3c92 CH |
166 | if (val & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))) |
167 | val |= (HOST_WIDE_INT) (-1) << GET_MODE_BITSIZE (mode); | |
44037a66 | 168 | else |
b1ec3c92 | 169 | val &= ((HOST_WIDE_INT) 1 << GET_MODE_BITSIZE (mode)) - 1; |
44037a66 | 170 | } |
b1ec3c92 | 171 | return GEN_INT (val); |
44037a66 TG |
172 | } |
173 | else | |
b1ec3c92 | 174 | return expand_unop (GET_MODE (x), neg_optab, x, NULL_RTX, 0); |
44037a66 TG |
175 | } |
176 | \f | |
177 | /* Generate code to store value from rtx VALUE | |
178 | into a bit-field within structure STR_RTX | |
179 | containing BITSIZE bits starting at bit BITNUM. | |
180 | FIELDMODE is the machine-mode of the FIELD_DECL node for this field. | |
181 | ALIGN is the alignment that STR_RTX is known to have, measured in bytes. | |
182 | TOTAL_SIZE is the size of the structure in bytes, or -1 if varying. */ | |
183 | ||
184 | /* ??? Note that there are two different ideas here for how | |
185 | to determine the size to count bits within, for a register. | |
186 | One is BITS_PER_WORD, and the other is the size of operand 3 | |
187 | of the insv pattern. (The latter assumes that an n-bit machine | |
188 | will be able to insert bit fields up to n bits wide.) | |
189 | It isn't certain that either of these is right. | |
190 | extract_bit_field has the same quandary. */ | |
191 | ||
192 | rtx | |
193 | store_bit_field (str_rtx, bitsize, bitnum, fieldmode, value, align, total_size) | |
194 | rtx str_rtx; | |
195 | register int bitsize; | |
196 | int bitnum; | |
197 | enum machine_mode fieldmode; | |
198 | rtx value; | |
199 | int align; | |
200 | int total_size; | |
201 | { | |
202 | int unit = (GET_CODE (str_rtx) == MEM) ? BITS_PER_UNIT : BITS_PER_WORD; | |
203 | register int offset = bitnum / unit; | |
204 | register int bitpos = bitnum % unit; | |
205 | register rtx op0 = str_rtx; | |
206 | ||
207 | if (GET_CODE (str_rtx) == MEM && ! MEM_IN_STRUCT_P (str_rtx)) | |
208 | abort (); | |
209 | ||
210 | /* Discount the part of the structure before the desired byte. | |
211 | We need to know how many bytes are safe to reference after it. */ | |
212 | if (total_size >= 0) | |
213 | total_size -= (bitpos / BIGGEST_ALIGNMENT | |
214 | * (BIGGEST_ALIGNMENT / BITS_PER_UNIT)); | |
215 | ||
216 | while (GET_CODE (op0) == SUBREG) | |
217 | { | |
218 | /* The following line once was done only if WORDS_BIG_ENDIAN, | |
219 | but I think that is a mistake. WORDS_BIG_ENDIAN is | |
220 | meaningful at a much higher level; when structures are copied | |
221 | between memory and regs, the higher-numbered regs | |
222 | always get higher addresses. */ | |
223 | offset += SUBREG_WORD (op0); | |
224 | /* We used to adjust BITPOS here, but now we do the whole adjustment | |
225 | right after the loop. */ | |
226 | op0 = SUBREG_REG (op0); | |
227 | } | |
228 | ||
229 | #if BYTES_BIG_ENDIAN | |
230 | /* If OP0 is a register, BITPOS must count within a word. | |
231 | But as we have it, it counts within whatever size OP0 now has. | |
232 | On a bigendian machine, these are not the same, so convert. */ | |
233 | if (GET_CODE (op0) != MEM && unit > GET_MODE_BITSIZE (GET_MODE (op0))) | |
234 | bitpos += unit - GET_MODE_BITSIZE (GET_MODE (op0)); | |
235 | #endif | |
236 | ||
237 | value = protect_from_queue (value, 0); | |
238 | ||
239 | if (flag_force_mem) | |
240 | value = force_not_mem (value); | |
241 | ||
242 | /* Note that the adjustment of BITPOS above has no effect on whether | |
243 | BITPOS is 0 in a REG bigger than a word. */ | |
56a2f049 RS |
244 | if (GET_MODE_SIZE (fieldmode) >= UNITS_PER_WORD |
245 | && (! STRICT_ALIGNMENT || GET_CODE (op0) != MEM) | |
44037a66 TG |
246 | && bitpos == 0 && bitsize == GET_MODE_BITSIZE (fieldmode)) |
247 | { | |
248 | /* Storing in a full-word or multi-word field in a register | |
249 | can be done with just SUBREG. */ | |
250 | if (GET_MODE (op0) != fieldmode) | |
56a2f049 RS |
251 | if (GET_CODE (op0) == REG) |
252 | op0 = gen_rtx (SUBREG, fieldmode, op0, offset); | |
253 | else | |
254 | op0 = change_address (op0, fieldmode, | |
255 | plus_constant (XEXP (op0, 0), offset)); | |
44037a66 TG |
256 | emit_move_insn (op0, value); |
257 | return value; | |
258 | } | |
259 | ||
260 | /* Storing an lsb-aligned field in a register | |
261 | can be done with a movestrict instruction. */ | |
262 | ||
263 | if (GET_CODE (op0) != MEM | |
264 | #if BYTES_BIG_ENDIAN | |
265 | && bitpos + bitsize == unit | |
266 | #else | |
267 | && bitpos == 0 | |
268 | #endif | |
269 | && bitsize == GET_MODE_BITSIZE (fieldmode) | |
270 | && (GET_MODE (op0) == fieldmode | |
271 | || (movstrict_optab->handlers[(int) fieldmode].insn_code | |
272 | != CODE_FOR_nothing))) | |
273 | { | |
274 | /* Get appropriate low part of the value being stored. */ | |
275 | if (GET_CODE (value) == CONST_INT || GET_CODE (value) == REG) | |
276 | value = gen_lowpart (fieldmode, value); | |
277 | else if (!(GET_CODE (value) == SYMBOL_REF | |
278 | || GET_CODE (value) == LABEL_REF | |
279 | || GET_CODE (value) == CONST)) | |
280 | value = convert_to_mode (fieldmode, value, 0); | |
281 | ||
282 | if (GET_MODE (op0) == fieldmode) | |
283 | emit_move_insn (op0, value); | |
284 | else | |
285 | { | |
286 | int icode = movstrict_optab->handlers[(int) fieldmode].insn_code; | |
287 | if(! (*insn_operand_predicate[icode][1]) (value, fieldmode)) | |
288 | value = copy_to_mode_reg (fieldmode, value); | |
289 | emit_insn (GEN_FCN (icode) | |
290 | (gen_rtx (SUBREG, fieldmode, op0, offset), value)); | |
291 | } | |
292 | return value; | |
293 | } | |
294 | ||
295 | /* Handle fields bigger than a word. */ | |
296 | ||
297 | if (bitsize > BITS_PER_WORD) | |
298 | { | |
299 | /* Here we transfer the words of the field | |
300 | in the order least significant first. | |
301 | This is because the most significant word is the one which may | |
302 | be less than full. */ | |
303 | ||
304 | int nwords = (bitsize + (BITS_PER_WORD - 1)) / BITS_PER_WORD; | |
305 | int i; | |
306 | ||
307 | /* This is the mode we must force value to, so that there will be enough | |
308 | subwords to extract. Note that fieldmode will often (always?) be | |
309 | VOIDmode, because that is what store_field uses to indicate that this | |
310 | is a bit field, but passing VOIDmode to operand_subword_force will | |
311 | result in an abort. */ | |
312 | fieldmode = mode_for_size (nwords * BITS_PER_WORD, MODE_INT, 0); | |
313 | ||
314 | for (i = 0; i < nwords; i++) | |
315 | { | |
316 | /* If I is 0, use the low-order word in both field and target; | |
317 | if I is 1, use the next to lowest word; and so on. */ | |
318 | int wordnum = (WORDS_BIG_ENDIAN ? nwords - i - 1 : i); | |
319 | int bit_offset = (WORDS_BIG_ENDIAN | |
320 | ? MAX (bitsize - (i + 1) * BITS_PER_WORD, 0) | |
321 | : i * BITS_PER_WORD); | |
322 | store_bit_field (op0, MIN (BITS_PER_WORD, | |
323 | bitsize - i * BITS_PER_WORD), | |
324 | bitnum + bit_offset, word_mode, | |
325 | operand_subword_force (value, wordnum, fieldmode), | |
326 | align, total_size); | |
327 | } | |
328 | return value; | |
329 | } | |
330 | ||
331 | /* From here on we can assume that the field to be stored in is | |
332 | a full-word (whatever type that is), since it is shorter than a word. */ | |
333 | ||
334 | /* OFFSET is the number of words or bytes (UNIT says which) | |
335 | from STR_RTX to the first word or byte containing part of the field. */ | |
336 | ||
337 | if (GET_CODE (op0) == REG) | |
338 | { | |
339 | if (offset != 0 | |
340 | || GET_MODE_SIZE (GET_MODE (op0)) > UNITS_PER_WORD) | |
341 | op0 = gen_rtx (SUBREG, TYPE_MODE (type_for_size (BITS_PER_WORD, 0)), | |
342 | op0, offset); | |
343 | offset = 0; | |
344 | } | |
345 | else | |
346 | { | |
347 | op0 = protect_from_queue (op0, 1); | |
348 | } | |
349 | ||
350 | /* Now OFFSET is nonzero only if OP0 is memory | |
351 | and is therefore always measured in bytes. */ | |
352 | ||
353 | #ifdef HAVE_insv | |
354 | if (HAVE_insv | |
355 | && !(bitsize == 1 && GET_CODE (value) == CONST_INT) | |
356 | /* Ensure insv's size is wide enough for this field. */ | |
357 | && (GET_MODE_BITSIZE (insn_operand_mode[(int) CODE_FOR_insv][3]) | |
358 | >= bitsize)) | |
359 | { | |
360 | int xbitpos = bitpos; | |
361 | rtx value1; | |
362 | rtx xop0 = op0; | |
363 | rtx last = get_last_insn (); | |
364 | rtx pat; | |
365 | enum machine_mode maxmode | |
366 | = insn_operand_mode[(int) CODE_FOR_insv][3]; | |
367 | ||
368 | int save_volatile_ok = volatile_ok; | |
369 | volatile_ok = 1; | |
370 | ||
371 | /* If this machine's insv can only insert into a register, or if we | |
372 | are to force MEMs into a register, copy OP0 into a register and | |
373 | save it back later. */ | |
374 | if (GET_CODE (op0) == MEM | |
375 | && (flag_force_mem | |
376 | || ! ((*insn_operand_predicate[(int) CODE_FOR_insv][0]) | |
377 | (op0, VOIDmode)))) | |
378 | { | |
379 | rtx tempreg; | |
380 | enum machine_mode bestmode; | |
381 | ||
382 | /* Get the mode to use for inserting into this field. If OP0 is | |
383 | BLKmode, get the smallest mode consistent with the alignment. If | |
384 | OP0 is a non-BLKmode object that is no wider than MAXMODE, use its | |
385 | mode. Otherwise, use the smallest mode containing the field. */ | |
386 | ||
387 | if (GET_MODE (op0) == BLKmode | |
388 | || GET_MODE_SIZE (GET_MODE (op0)) > GET_MODE_SIZE (maxmode)) | |
389 | bestmode | |
717702e6 RK |
390 | = get_best_mode (bitsize, bitnum, align * BITS_PER_UNIT, maxmode, |
391 | MEM_VOLATILE_P (op0)); | |
44037a66 TG |
392 | else |
393 | bestmode = GET_MODE (op0); | |
394 | ||
395 | if (bestmode == VOIDmode) | |
396 | goto insv_loses; | |
397 | ||
398 | /* Adjust address to point to the containing unit of that mode. */ | |
399 | unit = GET_MODE_BITSIZE (bestmode); | |
400 | /* Compute offset as multiple of this unit, counting in bytes. */ | |
401 | offset = (bitnum / unit) * GET_MODE_SIZE (bestmode); | |
402 | bitpos = bitnum % unit; | |
403 | op0 = change_address (op0, bestmode, | |
404 | plus_constant (XEXP (op0, 0), offset)); | |
405 | ||
406 | /* Fetch that unit, store the bitfield in it, then store the unit. */ | |
407 | tempreg = copy_to_reg (op0); | |
408 | store_bit_field (tempreg, bitsize, bitpos, fieldmode, value, | |
409 | align, total_size); | |
410 | emit_move_insn (op0, tempreg); | |
411 | return value; | |
412 | } | |
413 | volatile_ok = save_volatile_ok; | |
414 | ||
415 | /* Add OFFSET into OP0's address. */ | |
416 | if (GET_CODE (xop0) == MEM) | |
417 | xop0 = change_address (xop0, byte_mode, | |
418 | plus_constant (XEXP (xop0, 0), offset)); | |
419 | ||
420 | /* If xop0 is a register, we need it in MAXMODE | |
421 | to make it acceptable to the format of insv. */ | |
422 | if (GET_CODE (xop0) == SUBREG) | |
423 | PUT_MODE (xop0, maxmode); | |
424 | if (GET_CODE (xop0) == REG && GET_MODE (xop0) != maxmode) | |
425 | xop0 = gen_rtx (SUBREG, maxmode, xop0, 0); | |
426 | ||
427 | /* On big-endian machines, we count bits from the most significant. | |
428 | If the bit field insn does not, we must invert. */ | |
429 | ||
430 | #if BITS_BIG_ENDIAN != BYTES_BIG_ENDIAN | |
431 | xbitpos = unit - bitsize - xbitpos; | |
432 | #endif | |
433 | /* We have been counting XBITPOS within UNIT. | |
434 | Count instead within the size of the register. */ | |
435 | #if BITS_BIG_ENDIAN | |
436 | if (GET_CODE (xop0) != MEM) | |
437 | xbitpos += GET_MODE_BITSIZE (maxmode) - unit; | |
438 | #endif | |
439 | unit = GET_MODE_BITSIZE (maxmode); | |
440 | ||
441 | /* Convert VALUE to maxmode (which insv insn wants) in VALUE1. */ | |
442 | value1 = value; | |
443 | if (GET_MODE (value) != maxmode) | |
444 | { | |
445 | if (GET_MODE_BITSIZE (GET_MODE (value)) >= bitsize) | |
446 | { | |
447 | /* Optimization: Don't bother really extending VALUE | |
f5df292e RS |
448 | if it has all the bits we will actually use. However, |
449 | if we must narrow it, be sure we do it correctly. */ | |
44037a66 | 450 | |
f5df292e RS |
451 | if (GET_MODE_SIZE (GET_MODE (value)) < GET_MODE_SIZE (maxmode)) |
452 | { | |
453 | /* Avoid making subreg of a subreg, or of a mem. */ | |
454 | if (GET_CODE (value1) != REG) | |
44037a66 | 455 | value1 = copy_to_reg (value1); |
f5df292e RS |
456 | value1 = gen_rtx (SUBREG, maxmode, value1, 0); |
457 | } | |
458 | else | |
459 | value1 = gen_lowpart (maxmode, value1); | |
44037a66 TG |
460 | } |
461 | else if (!CONSTANT_P (value)) | |
462 | /* Parse phase is supposed to make VALUE's data type | |
463 | match that of the component reference, which is a type | |
464 | at least as wide as the field; so VALUE should have | |
465 | a mode that corresponds to that type. */ | |
466 | abort (); | |
467 | } | |
468 | ||
469 | /* If this machine's insv insists on a register, | |
470 | get VALUE1 into a register. */ | |
471 | if (! ((*insn_operand_predicate[(int) CODE_FOR_insv][3]) | |
472 | (value1, maxmode))) | |
473 | value1 = force_reg (maxmode, value1); | |
474 | ||
b1ec3c92 | 475 | pat = gen_insv (xop0, GEN_INT (bitsize), GEN_INT (xbitpos), value1); |
44037a66 TG |
476 | if (pat) |
477 | emit_insn (pat); | |
478 | else | |
479 | { | |
480 | delete_insns_since (last); | |
481 | store_fixed_bit_field (op0, offset, bitsize, bitpos, value, align); | |
482 | } | |
483 | } | |
484 | else | |
485 | insv_loses: | |
486 | #endif | |
487 | /* Insv is not available; store using shifts and boolean ops. */ | |
488 | store_fixed_bit_field (op0, offset, bitsize, bitpos, value, align); | |
489 | return value; | |
490 | } | |
491 | \f | |
492 | /* Use shifts and boolean operations to store VALUE | |
493 | into a bit field of width BITSIZE | |
494 | in a memory location specified by OP0 except offset by OFFSET bytes. | |
495 | (OFFSET must be 0 if OP0 is a register.) | |
496 | The field starts at position BITPOS within the byte. | |
497 | (If OP0 is a register, it may be a full word or a narrower mode, | |
498 | but BITPOS still counts within a full word, | |
499 | which is significant on bigendian machines.) | |
500 | STRUCT_ALIGN is the alignment the structure is known to have (in bytes). | |
501 | ||
502 | Note that protect_from_queue has already been done on OP0 and VALUE. */ | |
503 | ||
504 | static void | |
505 | store_fixed_bit_field (op0, offset, bitsize, bitpos, value, struct_align) | |
506 | register rtx op0; | |
507 | register int offset, bitsize, bitpos; | |
508 | register rtx value; | |
509 | int struct_align; | |
510 | { | |
511 | register enum machine_mode mode; | |
512 | int total_bits = BITS_PER_WORD; | |
513 | rtx subtarget, temp; | |
514 | int all_zero = 0; | |
515 | int all_one = 0; | |
516 | ||
44037a66 TG |
517 | /* There is a case not handled here: |
518 | a structure with a known alignment of just a halfword | |
519 | and a field split across two aligned halfwords within the structure. | |
520 | Or likewise a structure with a known alignment of just a byte | |
521 | and a field split across two bytes. | |
522 | Such cases are not supposed to be able to occur. */ | |
523 | ||
524 | if (GET_CODE (op0) == REG || GET_CODE (op0) == SUBREG) | |
525 | { | |
526 | if (offset != 0) | |
527 | abort (); | |
528 | /* Special treatment for a bit field split across two registers. */ | |
529 | if (bitsize + bitpos > BITS_PER_WORD) | |
530 | { | |
06c94bce RS |
531 | store_split_bit_field (op0, bitsize, bitpos, |
532 | value, BITS_PER_WORD); | |
44037a66 TG |
533 | return; |
534 | } | |
535 | } | |
536 | else | |
537 | { | |
538 | /* Get the proper mode to use for this field. We want a mode that | |
539 | includes the entire field. If such a mode would be larger than | |
540 | a word, we won't be doing the extraction the normal way. */ | |
541 | ||
542 | mode = get_best_mode (bitsize, bitpos + offset * BITS_PER_UNIT, | |
543 | struct_align * BITS_PER_UNIT, word_mode, | |
544 | GET_CODE (op0) == MEM && MEM_VOLATILE_P (op0)); | |
545 | ||
546 | if (mode == VOIDmode) | |
547 | { | |
548 | /* The only way this should occur is if the field spans word | |
549 | boundaries. */ | |
06c94bce RS |
550 | store_split_bit_field (op0, |
551 | bitsize, bitpos + offset * BITS_PER_UNIT, | |
44037a66 TG |
552 | value, struct_align); |
553 | return; | |
554 | } | |
555 | ||
556 | total_bits = GET_MODE_BITSIZE (mode); | |
557 | ||
558 | /* Get ref to an aligned byte, halfword, or word containing the field. | |
559 | Adjust BITPOS to be position within a word, | |
560 | and OFFSET to be the offset of that word. | |
561 | Then alter OP0 to refer to that word. */ | |
562 | bitpos += (offset % (total_bits / BITS_PER_UNIT)) * BITS_PER_UNIT; | |
563 | offset -= (offset % (total_bits / BITS_PER_UNIT)); | |
564 | op0 = change_address (op0, mode, | |
565 | plus_constant (XEXP (op0, 0), offset)); | |
566 | } | |
567 | ||
568 | mode = GET_MODE (op0); | |
569 | ||
570 | /* Now MODE is either some integral mode for a MEM as OP0, | |
571 | or is a full-word for a REG as OP0. TOTAL_BITS corresponds. | |
572 | The bit field is contained entirely within OP0. | |
573 | BITPOS is the starting bit number within OP0. | |
574 | (OP0's mode may actually be narrower than MODE.) */ | |
575 | ||
576 | #if BYTES_BIG_ENDIAN | |
577 | /* BITPOS is the distance between our msb | |
578 | and that of the containing datum. | |
579 | Convert it to the distance from the lsb. */ | |
580 | ||
581 | bitpos = total_bits - bitsize - bitpos; | |
582 | #endif | |
583 | /* Now BITPOS is always the distance between our lsb | |
584 | and that of OP0. */ | |
585 | ||
586 | /* Shift VALUE left by BITPOS bits. If VALUE is not constant, | |
587 | we must first convert its mode to MODE. */ | |
588 | ||
589 | if (GET_CODE (value) == CONST_INT) | |
590 | { | |
b1ec3c92 | 591 | register HOST_WIDE_INT v = INTVAL (value); |
44037a66 | 592 | |
b1ec3c92 CH |
593 | if (bitsize < HOST_BITS_PER_WIDE_INT) |
594 | v &= ((HOST_WIDE_INT) 1 << bitsize) - 1; | |
44037a66 TG |
595 | |
596 | if (v == 0) | |
597 | all_zero = 1; | |
b1ec3c92 CH |
598 | else if ((bitsize < HOST_BITS_PER_WIDE_INT |
599 | && v == ((HOST_WIDE_INT) 1 << bitsize) - 1) | |
600 | || (bitsize == HOST_BITS_PER_WIDE_INT && v == -1)) | |
44037a66 TG |
601 | all_one = 1; |
602 | ||
603 | value = lshift_value (mode, value, bitpos, bitsize); | |
604 | } | |
605 | else | |
606 | { | |
607 | int must_and = (GET_MODE_BITSIZE (GET_MODE (value)) != bitsize | |
608 | && bitpos + bitsize != GET_MODE_BITSIZE (mode)); | |
609 | ||
610 | if (GET_MODE (value) != mode) | |
611 | { | |
612 | /* If VALUE is a floating-point mode, access it as an integer | |
613 | of the corresponding size, then convert it. This can occur on | |
614 | a machine with 64 bit registers that uses SFmode for float. */ | |
615 | if (GET_MODE_CLASS (GET_MODE (value)) == MODE_FLOAT) | |
616 | { | |
617 | if (GET_CODE (value) != REG) | |
618 | value = copy_to_reg (value); | |
619 | value | |
620 | = gen_rtx (SUBREG, word_mode, value, 0); | |
621 | } | |
622 | ||
623 | if ((GET_CODE (value) == REG || GET_CODE (value) == SUBREG) | |
624 | && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (value))) | |
625 | value = gen_lowpart (mode, value); | |
626 | else | |
627 | value = convert_to_mode (mode, value, 1); | |
628 | } | |
629 | ||
630 | if (must_and) | |
631 | value = expand_binop (mode, and_optab, value, | |
632 | mask_rtx (mode, 0, bitsize, 0), | |
b1ec3c92 | 633 | NULL_RTX, 1, OPTAB_LIB_WIDEN); |
44037a66 TG |
634 | if (bitpos > 0) |
635 | value = expand_shift (LSHIFT_EXPR, mode, value, | |
b1ec3c92 | 636 | build_int_2 (bitpos, 0), NULL_RTX, 1); |
44037a66 TG |
637 | } |
638 | ||
639 | /* Now clear the chosen bits in OP0, | |
640 | except that if VALUE is -1 we need not bother. */ | |
641 | ||
642 | subtarget = (GET_CODE (op0) == REG || ! flag_force_mem) ? op0 : 0; | |
643 | ||
644 | if (! all_one) | |
645 | { | |
646 | temp = expand_binop (mode, and_optab, op0, | |
647 | mask_rtx (mode, bitpos, bitsize, 1), | |
648 | subtarget, 1, OPTAB_LIB_WIDEN); | |
649 | subtarget = temp; | |
650 | } | |
651 | else | |
652 | temp = op0; | |
653 | ||
654 | /* Now logical-or VALUE into OP0, unless it is zero. */ | |
655 | ||
656 | if (! all_zero) | |
657 | temp = expand_binop (mode, ior_optab, temp, value, | |
658 | subtarget, 1, OPTAB_LIB_WIDEN); | |
659 | if (op0 != temp) | |
660 | emit_move_insn (op0, temp); | |
661 | } | |
662 | \f | |
06c94bce | 663 | /* Store a bit field that is split across multiple accessible memory objects. |
44037a66 | 664 | |
06c94bce | 665 | OP0 is the REG, SUBREG or MEM rtx for the first of the objects. |
44037a66 TG |
666 | BITSIZE is the field width; BITPOS the position of its first bit |
667 | (within the word). | |
06c94bce RS |
668 | VALUE is the value to store. |
669 | ALIGN is the known alignment of OP0, measured in bytes. | |
670 | This is also the size of the memory objects to be used. | |
671 | ||
672 | This does not yet handle fields wider than BITS_PER_WORD. */ | |
44037a66 TG |
673 | |
674 | static void | |
675 | store_split_bit_field (op0, bitsize, bitpos, value, align) | |
676 | rtx op0; | |
677 | int bitsize, bitpos; | |
678 | rtx value; | |
679 | int align; | |
680 | { | |
06c94bce | 681 | int unit = align * BITS_PER_UNIT; |
44037a66 | 682 | rtx word; |
06c94bce | 683 | int bitsdone = 0; |
e54d80d0 RK |
684 | |
685 | if (GET_CODE (value) == CONST_DOUBLE | |
06c94bce RS |
686 | && (word = gen_lowpart_common (word_mode, value)) != 0) |
687 | value = word; | |
e54d80d0 | 688 | |
44037a66 | 689 | if (CONSTANT_P (value) && GET_CODE (value) != CONST_INT) |
e54d80d0 | 690 | value = copy_to_mode_reg (word_mode, value); |
44037a66 | 691 | |
06c94bce | 692 | while (bitsdone < bitsize) |
44037a66 | 693 | { |
06c94bce RS |
694 | int thissize; |
695 | rtx part, word; | |
696 | int thispos; | |
697 | int offset; | |
44037a66 | 698 | |
06c94bce RS |
699 | offset = (bitpos + bitsdone) / unit; |
700 | thispos = (bitpos + bitsdone) % unit; | |
44037a66 | 701 | |
06c94bce | 702 | thissize = unit - offset * BITS_PER_UNIT % unit; |
44037a66 | 703 | |
06c94bce RS |
704 | #if BYTES_BIG_ENDIAN |
705 | /* Fetch successively less significant portions. */ | |
706 | if (GET_CODE (value) == CONST_INT) | |
707 | part = GEN_INT (((unsigned HOST_WIDE_INT) (INTVAL (value)) | |
708 | >> (bitsize - bitsdone - thissize)) | |
709 | & (((HOST_WIDE_INT) 1 << thissize) - 1)); | |
710 | else | |
711 | /* The args are chosen so that the last part | |
712 | includes the lsb. */ | |
713 | part = extract_fixed_bit_field (word_mode, value, 0, thissize, | |
714 | BITS_PER_WORD - bitsize + bitsdone, | |
715 | NULL_RTX, 1, align); | |
716 | #else | |
717 | /* Fetch successively more significant portions. */ | |
718 | if (GET_CODE (value) == CONST_INT) | |
719 | part = GEN_INT (((unsigned HOST_WIDE_INT) (INTVAL (value)) >> bitsdone) | |
720 | & (((HOST_WIDE_INT) 1 << thissize) - 1)); | |
721 | else | |
722 | part = extract_fixed_bit_field (word_mode, value, 0, thissize, | |
723 | bitsdone, NULL_RTX, 1, align); | |
724 | #endif | |
44037a66 | 725 | |
06c94bce RS |
726 | /* If OP0 is a register, then handle OFFSET here. |
727 | In the register case, UNIT must be a whole word. */ | |
728 | if (GET_CODE (op0) == SUBREG || GET_CODE (op0) == REG) | |
729 | { | |
730 | word = operand_subword (op0, offset, 1, GET_MODE (op0)); | |
731 | offset = 0; | |
732 | } | |
733 | else | |
734 | word = op0; | |
44037a66 | 735 | |
06c94bce RS |
736 | if (word == 0) |
737 | abort (); | |
738 | ||
739 | store_fixed_bit_field (word, offset, thissize, thispos, part, align); | |
740 | bitsdone += thissize; | |
741 | } | |
44037a66 TG |
742 | } |
743 | \f | |
744 | /* Generate code to extract a byte-field from STR_RTX | |
745 | containing BITSIZE bits, starting at BITNUM, | |
746 | and put it in TARGET if possible (if TARGET is nonzero). | |
747 | Regardless of TARGET, we return the rtx for where the value is placed. | |
748 | It may be a QUEUED. | |
749 | ||
750 | STR_RTX is the structure containing the byte (a REG or MEM). | |
751 | UNSIGNEDP is nonzero if this is an unsigned bit field. | |
752 | MODE is the natural mode of the field value once extracted. | |
753 | TMODE is the mode the caller would like the value to have; | |
754 | but the value may be returned with type MODE instead. | |
755 | ||
756 | ALIGN is the alignment that STR_RTX is known to have, measured in bytes. | |
757 | TOTAL_SIZE is the size in bytes of the containing structure, | |
758 | or -1 if varying. | |
759 | ||
760 | If a TARGET is specified and we can store in it at no extra cost, | |
761 | we do so, and return TARGET. | |
762 | Otherwise, we return a REG of mode TMODE or MODE, with TMODE preferred | |
763 | if they are equally easy. */ | |
764 | ||
765 | rtx | |
766 | extract_bit_field (str_rtx, bitsize, bitnum, unsignedp, | |
767 | target, mode, tmode, align, total_size) | |
768 | rtx str_rtx; | |
769 | register int bitsize; | |
770 | int bitnum; | |
771 | int unsignedp; | |
772 | rtx target; | |
773 | enum machine_mode mode, tmode; | |
774 | int align; | |
775 | int total_size; | |
776 | { | |
777 | int unit = (GET_CODE (str_rtx) == MEM) ? BITS_PER_UNIT : BITS_PER_WORD; | |
778 | register int offset = bitnum / unit; | |
779 | register int bitpos = bitnum % unit; | |
780 | register rtx op0 = str_rtx; | |
781 | rtx spec_target = target; | |
782 | rtx spec_target_subreg = 0; | |
783 | ||
784 | if (GET_CODE (str_rtx) == MEM && ! MEM_IN_STRUCT_P (str_rtx)) | |
785 | abort (); | |
786 | ||
787 | /* Discount the part of the structure before the desired byte. | |
788 | We need to know how many bytes are safe to reference after it. */ | |
789 | if (total_size >= 0) | |
790 | total_size -= (bitpos / BIGGEST_ALIGNMENT | |
791 | * (BIGGEST_ALIGNMENT / BITS_PER_UNIT)); | |
792 | ||
793 | if (tmode == VOIDmode) | |
794 | tmode = mode; | |
44037a66 TG |
795 | while (GET_CODE (op0) == SUBREG) |
796 | { | |
797 | offset += SUBREG_WORD (op0); | |
798 | op0 = SUBREG_REG (op0); | |
799 | } | |
800 | ||
801 | #if BYTES_BIG_ENDIAN | |
802 | /* If OP0 is a register, BITPOS must count within a word. | |
803 | But as we have it, it counts within whatever size OP0 now has. | |
804 | On a bigendian machine, these are not the same, so convert. */ | |
805 | if (GET_CODE (op0) != MEM && unit > GET_MODE_BITSIZE (GET_MODE (op0))) | |
806 | bitpos += unit - GET_MODE_BITSIZE (GET_MODE (op0)); | |
807 | #endif | |
808 | ||
809 | /* Extracting a full-word or multi-word value | |
810 | from a structure in a register. | |
811 | This can be done with just SUBREG. | |
812 | So too extracting a subword value in | |
813 | the least significant part of the register. */ | |
814 | ||
815 | if (GET_CODE (op0) == REG | |
816 | && ((bitsize >= BITS_PER_WORD && bitsize == GET_MODE_BITSIZE (mode) | |
817 | && bitpos % BITS_PER_WORD == 0) | |
818 | || (mode_for_size (bitsize, GET_MODE_CLASS (tmode), 0) != BLKmode | |
819 | #if BYTES_BIG_ENDIAN | |
820 | && bitpos + bitsize == BITS_PER_WORD | |
821 | #else | |
822 | && bitpos == 0 | |
823 | #endif | |
824 | ))) | |
825 | { | |
826 | enum machine_mode mode1 | |
827 | = mode_for_size (bitsize, GET_MODE_CLASS (tmode), 0); | |
828 | ||
829 | if (mode1 != GET_MODE (op0)) | |
830 | op0 = gen_rtx (SUBREG, mode1, op0, offset); | |
831 | ||
832 | if (mode1 != mode) | |
833 | return convert_to_mode (tmode, op0, unsignedp); | |
834 | return op0; | |
835 | } | |
836 | ||
837 | /* Handle fields bigger than a word. */ | |
838 | ||
839 | if (bitsize > BITS_PER_WORD) | |
840 | { | |
841 | /* Here we transfer the words of the field | |
842 | in the order least significant first. | |
843 | This is because the most significant word is the one which may | |
844 | be less than full. */ | |
845 | ||
846 | int nwords = (bitsize + (BITS_PER_WORD - 1)) / BITS_PER_WORD; | |
847 | int i; | |
848 | ||
849 | if (target == 0 || GET_CODE (target) != REG) | |
850 | target = gen_reg_rtx (mode); | |
851 | ||
852 | for (i = 0; i < nwords; i++) | |
853 | { | |
854 | /* If I is 0, use the low-order word in both field and target; | |
855 | if I is 1, use the next to lowest word; and so on. */ | |
856 | int wordnum = (WORDS_BIG_ENDIAN ? nwords - i - 1 : i); | |
857 | int bit_offset = (WORDS_BIG_ENDIAN | |
858 | ? MAX (0, bitsize - (i + 1) * BITS_PER_WORD) | |
859 | : i * BITS_PER_WORD); | |
860 | rtx target_part = operand_subword (target, wordnum, 1, VOIDmode); | |
861 | rtx result_part | |
862 | = extract_bit_field (op0, MIN (BITS_PER_WORD, | |
863 | bitsize - i * BITS_PER_WORD), | |
864 | bitnum + bit_offset, | |
865 | 1, target_part, mode, word_mode, | |
866 | align, total_size); | |
867 | ||
868 | if (target_part == 0) | |
869 | abort (); | |
870 | ||
871 | if (result_part != target_part) | |
872 | emit_move_insn (target_part, result_part); | |
873 | } | |
874 | ||
875 | return target; | |
876 | } | |
877 | ||
878 | /* From here on we know the desired field is smaller than a word | |
879 | so we can assume it is an integer. So we can safely extract it as one | |
880 | size of integer, if necessary, and then truncate or extend | |
881 | to the size that is wanted. */ | |
882 | ||
883 | /* OFFSET is the number of words or bytes (UNIT says which) | |
884 | from STR_RTX to the first word or byte containing part of the field. */ | |
885 | ||
886 | if (GET_CODE (op0) == REG) | |
887 | { | |
888 | if (offset != 0 | |
889 | || GET_MODE_SIZE (GET_MODE (op0)) > UNITS_PER_WORD) | |
890 | op0 = gen_rtx (SUBREG, TYPE_MODE (type_for_size (BITS_PER_WORD, 0)), | |
891 | op0, offset); | |
892 | offset = 0; | |
893 | } | |
894 | else | |
895 | { | |
896 | op0 = protect_from_queue (str_rtx, 1); | |
897 | } | |
898 | ||
899 | /* Now OFFSET is nonzero only for memory operands. */ | |
900 | ||
901 | if (unsignedp) | |
902 | { | |
903 | #ifdef HAVE_extzv | |
904 | if (HAVE_extzv | |
905 | && (GET_MODE_BITSIZE (insn_operand_mode[(int) CODE_FOR_extzv][0]) | |
906 | >= bitsize)) | |
907 | { | |
908 | int xbitpos = bitpos, xoffset = offset; | |
909 | rtx bitsize_rtx, bitpos_rtx; | |
910 | rtx last = get_last_insn(); | |
911 | rtx xop0 = op0; | |
912 | rtx xtarget = target; | |
913 | rtx xspec_target = spec_target; | |
914 | rtx xspec_target_subreg = spec_target_subreg; | |
915 | rtx pat; | |
916 | enum machine_mode maxmode | |
917 | = insn_operand_mode[(int) CODE_FOR_extzv][0]; | |
918 | ||
919 | if (GET_CODE (xop0) == MEM) | |
920 | { | |
921 | int save_volatile_ok = volatile_ok; | |
922 | volatile_ok = 1; | |
923 | ||
924 | /* Is the memory operand acceptable? */ | |
925 | if (flag_force_mem | |
926 | || ! ((*insn_operand_predicate[(int) CODE_FOR_extzv][1]) | |
927 | (xop0, GET_MODE (xop0)))) | |
928 | { | |
929 | /* No, load into a reg and extract from there. */ | |
930 | enum machine_mode bestmode; | |
931 | ||
932 | /* Get the mode to use for inserting into this field. If | |
933 | OP0 is BLKmode, get the smallest mode consistent with the | |
934 | alignment. If OP0 is a non-BLKmode object that is no | |
935 | wider than MAXMODE, use its mode. Otherwise, use the | |
936 | smallest mode containing the field. */ | |
937 | ||
938 | if (GET_MODE (xop0) == BLKmode | |
939 | || (GET_MODE_SIZE (GET_MODE (op0)) | |
940 | > GET_MODE_SIZE (maxmode))) | |
941 | bestmode = get_best_mode (bitsize, bitnum, | |
942 | align * BITS_PER_UNIT, maxmode, | |
717702e6 | 943 | MEM_VOLATILE_P (xop0)); |
44037a66 TG |
944 | else |
945 | bestmode = GET_MODE (xop0); | |
946 | ||
947 | if (bestmode == VOIDmode) | |
948 | goto extzv_loses; | |
949 | ||
950 | /* Compute offset as multiple of this unit, | |
951 | counting in bytes. */ | |
952 | unit = GET_MODE_BITSIZE (bestmode); | |
953 | xoffset = (bitnum / unit) * GET_MODE_SIZE (bestmode); | |
954 | xbitpos = bitnum % unit; | |
955 | xop0 = change_address (xop0, bestmode, | |
956 | plus_constant (XEXP (xop0, 0), | |
957 | xoffset)); | |
958 | /* Fetch it to a register in that size. */ | |
959 | xop0 = force_reg (bestmode, xop0); | |
960 | ||
961 | /* XBITPOS counts within UNIT, which is what is expected. */ | |
962 | } | |
963 | else | |
964 | /* Get ref to first byte containing part of the field. */ | |
965 | xop0 = change_address (xop0, byte_mode, | |
966 | plus_constant (XEXP (xop0, 0), xoffset)); | |
967 | ||
968 | volatile_ok = save_volatile_ok; | |
969 | } | |
970 | ||
971 | /* If op0 is a register, we need it in MAXMODE (which is usually | |
972 | SImode). to make it acceptable to the format of extzv. */ | |
973 | if (GET_CODE (xop0) == SUBREG && GET_MODE (xop0) != maxmode) | |
974 | abort (); | |
975 | if (GET_CODE (xop0) == REG && GET_MODE (xop0) != maxmode) | |
976 | xop0 = gen_rtx (SUBREG, maxmode, xop0, 0); | |
977 | ||
978 | /* On big-endian machines, we count bits from the most significant. | |
979 | If the bit field insn does not, we must invert. */ | |
980 | #if BITS_BIG_ENDIAN != BYTES_BIG_ENDIAN | |
981 | xbitpos = unit - bitsize - xbitpos; | |
982 | #endif | |
983 | /* Now convert from counting within UNIT to counting in MAXMODE. */ | |
984 | #if BITS_BIG_ENDIAN | |
985 | if (GET_CODE (xop0) != MEM) | |
986 | xbitpos += GET_MODE_BITSIZE (maxmode) - unit; | |
987 | #endif | |
988 | unit = GET_MODE_BITSIZE (maxmode); | |
989 | ||
990 | if (xtarget == 0 | |
991 | || (flag_force_mem && GET_CODE (xtarget) == MEM)) | |
992 | xtarget = xspec_target = gen_reg_rtx (tmode); | |
993 | ||
994 | if (GET_MODE (xtarget) != maxmode) | |
995 | { | |
996 | if (GET_CODE (xtarget) == REG) | |
b7a09135 RS |
997 | { |
998 | int wider = (GET_MODE_SIZE (maxmode) | |
999 | > GET_MODE_SIZE (GET_MODE (xtarget))); | |
1000 | xtarget = gen_lowpart (maxmode, xtarget); | |
1001 | if (wider) | |
1002 | xspec_target_subreg = xtarget; | |
1003 | } | |
44037a66 TG |
1004 | else |
1005 | xtarget = gen_reg_rtx (maxmode); | |
1006 | } | |
1007 | ||
1008 | /* If this machine's extzv insists on a register target, | |
1009 | make sure we have one. */ | |
1010 | if (! ((*insn_operand_predicate[(int) CODE_FOR_extzv][0]) | |
1011 | (xtarget, maxmode))) | |
1012 | xtarget = gen_reg_rtx (maxmode); | |
1013 | ||
b1ec3c92 CH |
1014 | bitsize_rtx = GEN_INT (bitsize); |
1015 | bitpos_rtx = GEN_INT (xbitpos); | |
44037a66 TG |
1016 | |
1017 | pat = gen_extzv (protect_from_queue (xtarget, 1), | |
1018 | xop0, bitsize_rtx, bitpos_rtx); | |
1019 | if (pat) | |
1020 | { | |
1021 | emit_insn (pat); | |
1022 | target = xtarget; | |
1023 | spec_target = xspec_target; | |
1024 | spec_target_subreg = xspec_target_subreg; | |
1025 | } | |
1026 | else | |
1027 | { | |
1028 | delete_insns_since (last); | |
1029 | target = extract_fixed_bit_field (tmode, op0, offset, bitsize, | |
1030 | bitpos, target, 1, align); | |
1031 | } | |
1032 | } | |
1033 | else | |
1034 | extzv_loses: | |
1035 | #endif | |
1036 | target = extract_fixed_bit_field (tmode, op0, offset, bitsize, bitpos, | |
1037 | target, 1, align); | |
1038 | } | |
1039 | else | |
1040 | { | |
1041 | #ifdef HAVE_extv | |
1042 | if (HAVE_extv | |
1043 | && (GET_MODE_BITSIZE (insn_operand_mode[(int) CODE_FOR_extv][0]) | |
1044 | >= bitsize)) | |
1045 | { | |
1046 | int xbitpos = bitpos, xoffset = offset; | |
1047 | rtx bitsize_rtx, bitpos_rtx; | |
1048 | rtx last = get_last_insn(); | |
1049 | rtx xop0 = op0, xtarget = target; | |
1050 | rtx xspec_target = spec_target; | |
1051 | rtx xspec_target_subreg = spec_target_subreg; | |
1052 | rtx pat; | |
1053 | enum machine_mode maxmode | |
1054 | = insn_operand_mode[(int) CODE_FOR_extv][0]; | |
1055 | ||
1056 | if (GET_CODE (xop0) == MEM) | |
1057 | { | |
1058 | /* Is the memory operand acceptable? */ | |
1059 | if (! ((*insn_operand_predicate[(int) CODE_FOR_extv][1]) | |
1060 | (xop0, GET_MODE (xop0)))) | |
1061 | { | |
1062 | /* No, load into a reg and extract from there. */ | |
1063 | enum machine_mode bestmode; | |
1064 | ||
1065 | /* Get the mode to use for inserting into this field. If | |
1066 | OP0 is BLKmode, get the smallest mode consistent with the | |
1067 | alignment. If OP0 is a non-BLKmode object that is no | |
1068 | wider than MAXMODE, use its mode. Otherwise, use the | |
1069 | smallest mode containing the field. */ | |
1070 | ||
1071 | if (GET_MODE (xop0) == BLKmode | |
1072 | || (GET_MODE_SIZE (GET_MODE (op0)) | |
1073 | > GET_MODE_SIZE (maxmode))) | |
1074 | bestmode = get_best_mode (bitsize, bitnum, | |
1075 | align * BITS_PER_UNIT, maxmode, | |
717702e6 | 1076 | MEM_VOLATILE_P (xop0)); |
44037a66 TG |
1077 | else |
1078 | bestmode = GET_MODE (xop0); | |
1079 | ||
1080 | if (bestmode == VOIDmode) | |
1081 | goto extv_loses; | |
1082 | ||
1083 | /* Compute offset as multiple of this unit, | |
1084 | counting in bytes. */ | |
1085 | unit = GET_MODE_BITSIZE (bestmode); | |
1086 | xoffset = (bitnum / unit) * GET_MODE_SIZE (bestmode); | |
1087 | xbitpos = bitnum % unit; | |
1088 | xop0 = change_address (xop0, bestmode, | |
1089 | plus_constant (XEXP (xop0, 0), | |
1090 | xoffset)); | |
1091 | /* Fetch it to a register in that size. */ | |
1092 | xop0 = force_reg (bestmode, xop0); | |
1093 | ||
1094 | /* XBITPOS counts within UNIT, which is what is expected. */ | |
1095 | } | |
1096 | else | |
1097 | /* Get ref to first byte containing part of the field. */ | |
1098 | xop0 = change_address (xop0, byte_mode, | |
1099 | plus_constant (XEXP (xop0, 0), xoffset)); | |
1100 | } | |
1101 | ||
1102 | /* If op0 is a register, we need it in MAXMODE (which is usually | |
1103 | SImode) to make it acceptable to the format of extv. */ | |
1104 | if (GET_CODE (xop0) == SUBREG && GET_MODE (xop0) != maxmode) | |
1105 | abort (); | |
1106 | if (GET_CODE (xop0) == REG && GET_MODE (xop0) != maxmode) | |
1107 | xop0 = gen_rtx (SUBREG, maxmode, xop0, 0); | |
1108 | ||
1109 | /* On big-endian machines, we count bits from the most significant. | |
1110 | If the bit field insn does not, we must invert. */ | |
1111 | #if BITS_BIG_ENDIAN != BYTES_BIG_ENDIAN | |
1112 | xbitpos = unit - bitsize - xbitpos; | |
1113 | #endif | |
1114 | /* XBITPOS counts within a size of UNIT. | |
1115 | Adjust to count within a size of MAXMODE. */ | |
1116 | #if BITS_BIG_ENDIAN | |
1117 | if (GET_CODE (xop0) != MEM) | |
1118 | xbitpos += (GET_MODE_BITSIZE (maxmode) - unit); | |
1119 | #endif | |
1120 | unit = GET_MODE_BITSIZE (maxmode); | |
1121 | ||
1122 | if (xtarget == 0 | |
1123 | || (flag_force_mem && GET_CODE (xtarget) == MEM)) | |
1124 | xtarget = xspec_target = gen_reg_rtx (tmode); | |
1125 | ||
1126 | if (GET_MODE (xtarget) != maxmode) | |
1127 | { | |
1128 | if (GET_CODE (xtarget) == REG) | |
b7a09135 RS |
1129 | { |
1130 | int wider = (GET_MODE_SIZE (maxmode) | |
1131 | > GET_MODE_SIZE (GET_MODE (xtarget))); | |
1132 | xtarget = gen_lowpart (maxmode, xtarget); | |
1133 | if (wider) | |
1134 | xspec_target_subreg = xtarget; | |
1135 | } | |
44037a66 TG |
1136 | else |
1137 | xtarget = gen_reg_rtx (maxmode); | |
1138 | } | |
1139 | ||
1140 | /* If this machine's extv insists on a register target, | |
1141 | make sure we have one. */ | |
1142 | if (! ((*insn_operand_predicate[(int) CODE_FOR_extv][0]) | |
1143 | (xtarget, maxmode))) | |
1144 | xtarget = gen_reg_rtx (maxmode); | |
1145 | ||
b1ec3c92 CH |
1146 | bitsize_rtx = GEN_INT (bitsize); |
1147 | bitpos_rtx = GEN_INT (xbitpos); | |
44037a66 TG |
1148 | |
1149 | pat = gen_extv (protect_from_queue (xtarget, 1), | |
1150 | xop0, bitsize_rtx, bitpos_rtx); | |
1151 | if (pat) | |
1152 | { | |
1153 | emit_insn (pat); | |
1154 | target = xtarget; | |
1155 | spec_target = xspec_target; | |
1156 | spec_target_subreg = xspec_target_subreg; | |
1157 | } | |
1158 | else | |
1159 | { | |
1160 | delete_insns_since (last); | |
1161 | target = extract_fixed_bit_field (tmode, op0, offset, bitsize, | |
1162 | bitpos, target, 0, align); | |
1163 | } | |
1164 | } | |
1165 | else | |
1166 | extv_loses: | |
1167 | #endif | |
1168 | target = extract_fixed_bit_field (tmode, op0, offset, bitsize, bitpos, | |
1169 | target, 0, align); | |
1170 | } | |
1171 | if (target == spec_target) | |
1172 | return target; | |
1173 | if (target == spec_target_subreg) | |
1174 | return spec_target; | |
1175 | if (GET_MODE (target) != tmode && GET_MODE (target) != mode) | |
1176 | { | |
1177 | /* If the target mode is floating-point, first convert to the | |
1178 | integer mode of that size and then access it as a floating-point | |
1179 | value via a SUBREG. */ | |
1180 | if (GET_MODE_CLASS (tmode) == MODE_FLOAT) | |
1181 | { | |
1182 | target = convert_to_mode (mode_for_size (GET_MODE_BITSIZE (tmode), | |
1183 | MODE_INT, 0), | |
1184 | target, unsignedp); | |
1185 | if (GET_CODE (target) != REG) | |
1186 | target = copy_to_reg (target); | |
1187 | return gen_rtx (SUBREG, tmode, target, 0); | |
1188 | } | |
1189 | else | |
1190 | return convert_to_mode (tmode, target, unsignedp); | |
1191 | } | |
1192 | return target; | |
1193 | } | |
1194 | \f | |
1195 | /* Extract a bit field using shifts and boolean operations | |
1196 | Returns an rtx to represent the value. | |
1197 | OP0 addresses a register (word) or memory (byte). | |
1198 | BITPOS says which bit within the word or byte the bit field starts in. | |
1199 | OFFSET says how many bytes farther the bit field starts; | |
1200 | it is 0 if OP0 is a register. | |
1201 | BITSIZE says how many bits long the bit field is. | |
1202 | (If OP0 is a register, it may be narrower than a full word, | |
1203 | but BITPOS still counts within a full word, | |
1204 | which is significant on bigendian machines.) | |
1205 | ||
1206 | UNSIGNEDP is nonzero for an unsigned bit field (don't sign-extend value). | |
1207 | If TARGET is nonzero, attempts to store the value there | |
1208 | and return TARGET, but this is not guaranteed. | |
1209 | If TARGET is not used, create a pseudo-reg of mode TMODE for the value. | |
1210 | ||
1211 | ALIGN is the alignment that STR_RTX is known to have, measured in bytes. */ | |
1212 | ||
1213 | static rtx | |
1214 | extract_fixed_bit_field (tmode, op0, offset, bitsize, bitpos, | |
1215 | target, unsignedp, align) | |
1216 | enum machine_mode tmode; | |
1217 | register rtx op0, target; | |
1218 | register int offset, bitsize, bitpos; | |
1219 | int unsignedp; | |
1220 | int align; | |
1221 | { | |
1222 | int total_bits = BITS_PER_WORD; | |
1223 | enum machine_mode mode; | |
1224 | ||
1225 | if (GET_CODE (op0) == SUBREG || GET_CODE (op0) == REG) | |
1226 | { | |
1227 | /* Special treatment for a bit field split across two registers. */ | |
1228 | if (bitsize + bitpos > BITS_PER_WORD) | |
1229 | return extract_split_bit_field (op0, bitsize, bitpos, | |
1230 | unsignedp, align); | |
1231 | } | |
1232 | else | |
1233 | { | |
1234 | /* Get the proper mode to use for this field. We want a mode that | |
1235 | includes the entire field. If such a mode would be larger than | |
1236 | a word, we won't be doing the extraction the normal way. */ | |
1237 | ||
1238 | mode = get_best_mode (bitsize, bitpos + offset * BITS_PER_UNIT, | |
1239 | align * BITS_PER_UNIT, word_mode, | |
1240 | GET_CODE (op0) == MEM && MEM_VOLATILE_P (op0)); | |
1241 | ||
1242 | if (mode == VOIDmode) | |
1243 | /* The only way this should occur is if the field spans word | |
1244 | boundaries. */ | |
1245 | return extract_split_bit_field (op0, bitsize, | |
1246 | bitpos + offset * BITS_PER_UNIT, | |
1247 | unsignedp, align); | |
1248 | ||
1249 | total_bits = GET_MODE_BITSIZE (mode); | |
1250 | ||
401db791 JW |
1251 | /* Make sure bitpos is valid for the chosen mode. Adjust BITPOS to |
1252 | be be in the range 0 to total_bits-1, and put any excess bytes in | |
1253 | OFFSET. */ | |
1254 | if (bitpos >= total_bits) | |
1255 | { | |
1256 | offset += (bitpos / total_bits) * (total_bits / BITS_PER_UNIT); | |
1257 | bitpos -= ((bitpos / total_bits) * (total_bits / BITS_PER_UNIT) | |
1258 | * BITS_PER_UNIT); | |
1259 | } | |
1260 | ||
44037a66 TG |
1261 | /* Get ref to an aligned byte, halfword, or word containing the field. |
1262 | Adjust BITPOS to be position within a word, | |
1263 | and OFFSET to be the offset of that word. | |
1264 | Then alter OP0 to refer to that word. */ | |
1265 | bitpos += (offset % (total_bits / BITS_PER_UNIT)) * BITS_PER_UNIT; | |
1266 | offset -= (offset % (total_bits / BITS_PER_UNIT)); | |
1267 | op0 = change_address (op0, mode, | |
1268 | plus_constant (XEXP (op0, 0), offset)); | |
1269 | } | |
1270 | ||
1271 | mode = GET_MODE (op0); | |
1272 | ||
1273 | #if BYTES_BIG_ENDIAN | |
1274 | /* BITPOS is the distance between our msb and that of OP0. | |
1275 | Convert it to the distance from the lsb. */ | |
1276 | ||
1277 | bitpos = total_bits - bitsize - bitpos; | |
1278 | #endif | |
1279 | /* Now BITPOS is always the distance between the field's lsb and that of OP0. | |
1280 | We have reduced the big-endian case to the little-endian case. */ | |
1281 | ||
1282 | if (unsignedp) | |
1283 | { | |
1284 | if (bitpos) | |
1285 | { | |
1286 | /* If the field does not already start at the lsb, | |
1287 | shift it so it does. */ | |
1288 | tree amount = build_int_2 (bitpos, 0); | |
1289 | /* Maybe propagate the target for the shift. */ | |
1290 | /* But not if we will return it--could confuse integrate.c. */ | |
1291 | rtx subtarget = (target != 0 && GET_CODE (target) == REG | |
1292 | && !REG_FUNCTION_VALUE_P (target) | |
1293 | ? target : 0); | |
1294 | if (tmode != mode) subtarget = 0; | |
1295 | op0 = expand_shift (RSHIFT_EXPR, mode, op0, amount, subtarget, 1); | |
1296 | } | |
1297 | /* Convert the value to the desired mode. */ | |
1298 | if (mode != tmode) | |
1299 | op0 = convert_to_mode (tmode, op0, 1); | |
1300 | ||
1301 | /* Unless the msb of the field used to be the msb when we shifted, | |
1302 | mask out the upper bits. */ | |
1303 | ||
1304 | if (GET_MODE_BITSIZE (mode) != bitpos + bitsize | |
1305 | #if 0 | |
1306 | #ifdef SLOW_ZERO_EXTEND | |
1307 | /* Always generate an `and' if | |
1308 | we just zero-extended op0 and SLOW_ZERO_EXTEND, since it | |
1309 | will combine fruitfully with the zero-extend. */ | |
1310 | || tmode != mode | |
1311 | #endif | |
1312 | #endif | |
1313 | ) | |
1314 | return expand_binop (GET_MODE (op0), and_optab, op0, | |
1315 | mask_rtx (GET_MODE (op0), 0, bitsize, 0), | |
1316 | target, 1, OPTAB_LIB_WIDEN); | |
1317 | return op0; | |
1318 | } | |
1319 | ||
1320 | /* To extract a signed bit-field, first shift its msb to the msb of the word, | |
1321 | then arithmetic-shift its lsb to the lsb of the word. */ | |
1322 | op0 = force_reg (mode, op0); | |
1323 | if (mode != tmode) | |
1324 | target = 0; | |
1325 | ||
1326 | /* Find the narrowest integer mode that contains the field. */ | |
1327 | ||
1328 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT); mode != VOIDmode; | |
1329 | mode = GET_MODE_WIDER_MODE (mode)) | |
1330 | if (GET_MODE_BITSIZE (mode) >= bitsize + bitpos) | |
1331 | { | |
1332 | op0 = convert_to_mode (mode, op0, 0); | |
1333 | break; | |
1334 | } | |
1335 | ||
1336 | if (GET_MODE_BITSIZE (mode) != (bitsize + bitpos)) | |
1337 | { | |
1338 | tree amount = build_int_2 (GET_MODE_BITSIZE (mode) - (bitsize + bitpos), 0); | |
1339 | /* Maybe propagate the target for the shift. */ | |
1340 | /* But not if we will return the result--could confuse integrate.c. */ | |
1341 | rtx subtarget = (target != 0 && GET_CODE (target) == REG | |
1342 | && ! REG_FUNCTION_VALUE_P (target) | |
1343 | ? target : 0); | |
1344 | op0 = expand_shift (LSHIFT_EXPR, mode, op0, amount, subtarget, 1); | |
1345 | } | |
1346 | ||
1347 | return expand_shift (RSHIFT_EXPR, mode, op0, | |
1348 | build_int_2 (GET_MODE_BITSIZE (mode) - bitsize, 0), | |
1349 | target, 0); | |
1350 | } | |
1351 | \f | |
1352 | /* Return a constant integer (CONST_INT or CONST_DOUBLE) mask value | |
1353 | of mode MODE with BITSIZE ones followed by BITPOS zeros, or the | |
1354 | complement of that if COMPLEMENT. The mask is truncated if | |
1355 | necessary to the width of mode MODE. */ | |
1356 | ||
1357 | static rtx | |
1358 | mask_rtx (mode, bitpos, bitsize, complement) | |
1359 | enum machine_mode mode; | |
1360 | int bitpos, bitsize, complement; | |
1361 | { | |
b1ec3c92 | 1362 | HOST_WIDE_INT masklow, maskhigh; |
44037a66 | 1363 | |
b1ec3c92 CH |
1364 | if (bitpos < HOST_BITS_PER_WIDE_INT) |
1365 | masklow = (HOST_WIDE_INT) -1 << bitpos; | |
44037a66 TG |
1366 | else |
1367 | masklow = 0; | |
1368 | ||
b1ec3c92 CH |
1369 | if (bitpos + bitsize < HOST_BITS_PER_WIDE_INT) |
1370 | masklow &= ((unsigned HOST_WIDE_INT) -1 | |
1371 | >> (HOST_BITS_PER_WIDE_INT - bitpos - bitsize)); | |
44037a66 | 1372 | |
b1ec3c92 | 1373 | if (bitpos <= HOST_BITS_PER_WIDE_INT) |
44037a66 TG |
1374 | maskhigh = -1; |
1375 | else | |
b1ec3c92 | 1376 | maskhigh = (HOST_WIDE_INT) -1 << (bitpos - HOST_BITS_PER_WIDE_INT); |
44037a66 | 1377 | |
b1ec3c92 CH |
1378 | if (bitpos + bitsize > HOST_BITS_PER_WIDE_INT) |
1379 | maskhigh &= ((unsigned HOST_WIDE_INT) -1 | |
1380 | >> (2 * HOST_BITS_PER_WIDE_INT - bitpos - bitsize)); | |
44037a66 TG |
1381 | else |
1382 | maskhigh = 0; | |
1383 | ||
1384 | if (complement) | |
1385 | { | |
1386 | maskhigh = ~maskhigh; | |
1387 | masklow = ~masklow; | |
1388 | } | |
1389 | ||
1390 | return immed_double_const (masklow, maskhigh, mode); | |
1391 | } | |
1392 | ||
1393 | /* Return a constant integer (CONST_INT or CONST_DOUBLE) rtx with the value | |
1394 | VALUE truncated to BITSIZE bits and then shifted left BITPOS bits. */ | |
1395 | ||
1396 | static rtx | |
1397 | lshift_value (mode, value, bitpos, bitsize) | |
1398 | enum machine_mode mode; | |
1399 | rtx value; | |
1400 | int bitpos, bitsize; | |
1401 | { | |
b1ec3c92 CH |
1402 | unsigned HOST_WIDE_INT v = INTVAL (value); |
1403 | HOST_WIDE_INT low, high; | |
44037a66 | 1404 | |
b1ec3c92 CH |
1405 | if (bitsize < HOST_BITS_PER_WIDE_INT) |
1406 | v &= ~((HOST_WIDE_INT) -1 << bitsize); | |
44037a66 | 1407 | |
b1ec3c92 | 1408 | if (bitpos < HOST_BITS_PER_WIDE_INT) |
44037a66 TG |
1409 | { |
1410 | low = v << bitpos; | |
b1ec3c92 | 1411 | high = (bitpos > 0 ? (v >> (HOST_BITS_PER_WIDE_INT - bitpos)) : 0); |
44037a66 TG |
1412 | } |
1413 | else | |
1414 | { | |
1415 | low = 0; | |
b1ec3c92 | 1416 | high = v << (bitpos - HOST_BITS_PER_WIDE_INT); |
44037a66 TG |
1417 | } |
1418 | ||
1419 | return immed_double_const (low, high, mode); | |
1420 | } | |
1421 | \f | |
1422 | /* Extract a bit field that is split across two words | |
1423 | and return an RTX for the result. | |
1424 | ||
1425 | OP0 is the REG, SUBREG or MEM rtx for the first of the two words. | |
1426 | BITSIZE is the field width; BITPOS, position of its first bit, in the word. | |
06c94bce RS |
1427 | UNSIGNEDP is 1 if should zero-extend the contents; else sign-extend. |
1428 | ||
1429 | ALIGN is the known alignment of OP0, measured in bytes. | |
1430 | This is also the size of the memory objects to be used. */ | |
44037a66 TG |
1431 | |
1432 | static rtx | |
1433 | extract_split_bit_field (op0, bitsize, bitpos, unsignedp, align) | |
1434 | rtx op0; | |
1435 | int bitsize, bitpos, unsignedp, align; | |
1436 | { | |
06c94bce RS |
1437 | int unit = align * BITS_PER_UNIT; |
1438 | int bitsdone = 0; | |
1439 | rtx result; | |
1440 | int first = 1; | |
44037a66 | 1441 | |
06c94bce RS |
1442 | while (bitsdone < bitsize) |
1443 | { | |
1444 | int thissize; | |
1445 | rtx part, word; | |
1446 | int thispos; | |
1447 | int offset; | |
1448 | ||
1449 | offset = (bitpos + bitsdone) / unit; | |
1450 | thispos = (bitpos + bitsdone) % unit; | |
1451 | ||
1452 | thissize = unit - offset * BITS_PER_UNIT % unit; | |
1453 | ||
1454 | /* If OP0 is a register, then handle OFFSET here. | |
1455 | In the register case, UNIT must be a whole word. */ | |
1456 | if (GET_CODE (op0) == SUBREG || GET_CODE (op0) == REG) | |
1457 | { | |
1458 | word = operand_subword_force (op0, offset, GET_MODE (op0)); | |
1459 | offset = 0; | |
1460 | } | |
1461 | else | |
1462 | word = op0; | |
1463 | ||
1464 | if (word == 0) | |
1465 | abort (); | |
44037a66 | 1466 | |
06c94bce RS |
1467 | /* Extract the parts in bit-counting order, |
1468 | whose meaning is determined by BYTES_PER_UNIT. */ | |
1469 | part = extract_fixed_bit_field (word_mode, word, offset, | |
1470 | thissize, thispos, 0, 1, align); | |
1471 | bitsdone += thissize; | |
44037a66 | 1472 | |
06c94bce | 1473 | /* Shift this part into place for the result. */ |
44037a66 | 1474 | #if BYTES_BIG_ENDIAN |
06c94bce RS |
1475 | if (bitsize != bitsdone) |
1476 | part = expand_shift (LSHIFT_EXPR, word_mode, part, | |
1477 | build_int_2 (bitsize - bitsdone, 0), 0, 1); | |
44037a66 | 1478 | #else |
06c94bce RS |
1479 | if (bitsdone != 0) |
1480 | part = expand_shift (LSHIFT_EXPR, word_mode, part, | |
1481 | build_int_2 (bitsdone, 0), 0, 1); | |
44037a66 TG |
1482 | #endif |
1483 | ||
06c94bce RS |
1484 | if (first) |
1485 | result = part; | |
1486 | else | |
1487 | /* Combine the parts with bitwise or. This works | |
1488 | because we extracted each part as an unsigned bit field. */ | |
1489 | result = expand_binop (word_mode, ior_optab, part, result, NULL_RTX, 1, | |
1490 | OPTAB_LIB_WIDEN); | |
1491 | ||
1492 | first = 0; | |
1493 | } | |
44037a66 TG |
1494 | |
1495 | /* Unsigned bit field: we are done. */ | |
1496 | if (unsignedp) | |
1497 | return result; | |
1498 | /* Signed bit field: sign-extend with two arithmetic shifts. */ | |
1499 | result = expand_shift (LSHIFT_EXPR, word_mode, result, | |
b1ec3c92 CH |
1500 | build_int_2 (BITS_PER_WORD - bitsize, 0), |
1501 | NULL_RTX, 0); | |
44037a66 | 1502 | return expand_shift (RSHIFT_EXPR, word_mode, result, |
b1ec3c92 | 1503 | build_int_2 (BITS_PER_WORD - bitsize, 0), NULL_RTX, 0); |
44037a66 TG |
1504 | } |
1505 | \f | |
1506 | /* Add INC into TARGET. */ | |
1507 | ||
1508 | void | |
1509 | expand_inc (target, inc) | |
1510 | rtx target, inc; | |
1511 | { | |
1512 | rtx value = expand_binop (GET_MODE (target), add_optab, | |
1513 | target, inc, | |
1514 | target, 0, OPTAB_LIB_WIDEN); | |
1515 | if (value != target) | |
1516 | emit_move_insn (target, value); | |
1517 | } | |
1518 | ||
1519 | /* Subtract DEC from TARGET. */ | |
1520 | ||
1521 | void | |
1522 | expand_dec (target, dec) | |
1523 | rtx target, dec; | |
1524 | { | |
1525 | rtx value = expand_binop (GET_MODE (target), sub_optab, | |
1526 | target, dec, | |
1527 | target, 0, OPTAB_LIB_WIDEN); | |
1528 | if (value != target) | |
1529 | emit_move_insn (target, value); | |
1530 | } | |
1531 | \f | |
1532 | /* Output a shift instruction for expression code CODE, | |
1533 | with SHIFTED being the rtx for the value to shift, | |
1534 | and AMOUNT the tree for the amount to shift by. | |
1535 | Store the result in the rtx TARGET, if that is convenient. | |
1536 | If UNSIGNEDP is nonzero, do a logical shift; otherwise, arithmetic. | |
1537 | Return the rtx for where the value is. */ | |
1538 | ||
1539 | rtx | |
1540 | expand_shift (code, mode, shifted, amount, target, unsignedp) | |
1541 | enum tree_code code; | |
1542 | register enum machine_mode mode; | |
1543 | rtx shifted; | |
1544 | tree amount; | |
1545 | register rtx target; | |
1546 | int unsignedp; | |
1547 | { | |
1548 | register rtx op1, temp = 0; | |
1549 | register int left = (code == LSHIFT_EXPR || code == LROTATE_EXPR); | |
1550 | register int rotate = (code == LROTATE_EXPR || code == RROTATE_EXPR); | |
1551 | int try; | |
1552 | ||
1553 | /* Previously detected shift-counts computed by NEGATE_EXPR | |
1554 | and shifted in the other direction; but that does not work | |
1555 | on all machines. */ | |
1556 | ||
b1ec3c92 | 1557 | op1 = expand_expr (amount, NULL_RTX, VOIDmode, 0); |
44037a66 TG |
1558 | |
1559 | if (op1 == const0_rtx) | |
1560 | return shifted; | |
1561 | ||
1562 | for (try = 0; temp == 0 && try < 3; try++) | |
1563 | { | |
1564 | enum optab_methods methods; | |
1565 | ||
1566 | if (try == 0) | |
1567 | methods = OPTAB_DIRECT; | |
1568 | else if (try == 1) | |
1569 | methods = OPTAB_WIDEN; | |
1570 | else | |
1571 | methods = OPTAB_LIB_WIDEN; | |
1572 | ||
1573 | if (rotate) | |
1574 | { | |
1575 | /* Widening does not work for rotation. */ | |
1576 | if (methods == OPTAB_WIDEN) | |
1577 | continue; | |
1578 | else if (methods == OPTAB_LIB_WIDEN) | |
cbec710e RK |
1579 | { |
1580 | /* If we are rotating by a constant that is valid and | |
1581 | we have been unable to open-code this by a rotation, | |
1582 | do it as the IOR of two shifts. I.e., to rotate A | |
1583 | by N bits, compute (A << N) | ((unsigned) A >> (C - N)) | |
1584 | where C is the bitsize of A. | |
1585 | ||
1586 | It is theoretically possible that the target machine might | |
1587 | not be able to perform either shift and hence we would | |
1588 | be making two libcalls rather than just the one for the | |
1589 | shift (similarly if IOR could not be done). We will allow | |
1590 | this extremely unlikely lossage to avoid complicating the | |
1591 | code below. */ | |
1592 | ||
1593 | if (GET_CODE (op1) == CONST_INT && INTVAL (op1) > 0 | |
1594 | && INTVAL (op1) < GET_MODE_BITSIZE (mode)) | |
1595 | { | |
1596 | rtx subtarget = target == shifted ? 0 : target; | |
1597 | rtx temp1; | |
1598 | tree other_amount | |
1599 | = build_int_2 (GET_MODE_BITSIZE (mode) - INTVAL (op1), 0); | |
1600 | ||
1601 | shifted = force_reg (mode, shifted); | |
1602 | ||
1603 | temp = expand_shift (left ? LSHIFT_EXPR : RSHIFT_EXPR, | |
1604 | mode, shifted, amount, subtarget, 1); | |
1605 | temp1 = expand_shift (left ? RSHIFT_EXPR : LSHIFT_EXPR, | |
1606 | mode, shifted, other_amount, 0, 1); | |
1607 | return expand_binop (mode, ior_optab, temp, temp1, target, | |
1608 | unsignedp, methods); | |
1609 | } | |
1610 | else | |
1611 | methods = OPTAB_LIB; | |
1612 | } | |
44037a66 TG |
1613 | |
1614 | temp = expand_binop (mode, | |
1615 | left ? rotl_optab : rotr_optab, | |
1616 | shifted, op1, target, unsignedp, methods); | |
cbec710e RK |
1617 | |
1618 | /* If we don't have the rotate, but we are rotating by a constant | |
1619 | that is in range, try a rotate in the opposite direction. */ | |
1620 | ||
1621 | if (temp == 0 && GET_CODE (op1) == CONST_INT | |
1622 | && INTVAL (op1) > 0 && INTVAL (op1) < GET_MODE_BITSIZE (mode)) | |
1623 | temp = expand_binop (mode, | |
1624 | left ? rotr_optab : rotl_optab, | |
1625 | shifted, | |
1626 | GEN_INT (GET_MODE_BITSIZE (mode) | |
1627 | - INTVAL (op1)), | |
1628 | target, unsignedp, methods); | |
44037a66 TG |
1629 | } |
1630 | else if (unsignedp) | |
1631 | { | |
1632 | temp = expand_binop (mode, | |
1633 | left ? lshl_optab : lshr_optab, | |
1634 | shifted, op1, target, unsignedp, methods); | |
1635 | if (temp == 0 && left) | |
1636 | temp = expand_binop (mode, ashl_optab, | |
1637 | shifted, op1, target, unsignedp, methods); | |
1638 | } | |
1639 | ||
1640 | /* Do arithmetic shifts. | |
1641 | Also, if we are going to widen the operand, we can just as well | |
1642 | use an arithmetic right-shift instead of a logical one. */ | |
1643 | if (temp == 0 && ! rotate | |
1644 | && (! unsignedp || (! left && methods == OPTAB_WIDEN))) | |
1645 | { | |
1646 | enum optab_methods methods1 = methods; | |
1647 | ||
1648 | /* If trying to widen a log shift to an arithmetic shift, | |
1649 | don't accept an arithmetic shift of the same size. */ | |
1650 | if (unsignedp) | |
1651 | methods1 = OPTAB_MUST_WIDEN; | |
1652 | ||
1653 | /* Arithmetic shift */ | |
1654 | ||
1655 | temp = expand_binop (mode, | |
1656 | left ? ashl_optab : ashr_optab, | |
1657 | shifted, op1, target, unsignedp, methods1); | |
1658 | } | |
1659 | ||
1660 | #ifdef HAVE_extzv | |
1661 | /* We can do a logical (unsigned) right shift with a bit-field | |
1662 | extract insn. But first check if one of the above methods worked. */ | |
1663 | if (temp != 0) | |
1664 | return temp; | |
1665 | ||
1666 | if (unsignedp && code == RSHIFT_EXPR && ! BITS_BIG_ENDIAN && HAVE_extzv) | |
1667 | { | |
1668 | enum machine_mode output_mode | |
1669 | = insn_operand_mode[(int) CODE_FOR_extzv][0]; | |
1670 | ||
1671 | if ((methods == OPTAB_DIRECT && mode == output_mode) | |
1672 | || (methods == OPTAB_WIDEN | |
1673 | && GET_MODE_SIZE (mode) < GET_MODE_SIZE (output_mode))) | |
1674 | { | |
b3d4e1b2 RS |
1675 | rtx shifted1 = convert_to_mode (output_mode, |
1676 | protect_from_queue (shifted, 0), | |
1677 | 1); | |
44037a66 TG |
1678 | enum machine_mode length_mode |
1679 | = insn_operand_mode[(int) CODE_FOR_extzv][2]; | |
1680 | enum machine_mode pos_mode | |
1681 | = insn_operand_mode[(int) CODE_FOR_extzv][3]; | |
1682 | rtx target1 = 0; | |
1683 | rtx last = get_last_insn (); | |
1684 | rtx width; | |
1685 | rtx xop1 = op1; | |
1686 | rtx pat; | |
1687 | ||
1688 | if (target != 0) | |
1689 | target1 = protect_from_queue (target, 1); | |
1690 | ||
1691 | /* We define extract insns as having OUTPUT_MODE in a register | |
1692 | and the mode of operand 1 in memory. Since we want | |
1693 | OUTPUT_MODE, we will always force the operand into a | |
1694 | register. At some point we might want to support MEM | |
1695 | directly. */ | |
1696 | shifted1 = force_reg (output_mode, shifted1); | |
1697 | ||
1698 | /* If we don't have or cannot use a suggested target, | |
1699 | make a place for the result, in the proper mode. */ | |
1700 | if (methods == OPTAB_WIDEN || target1 == 0 | |
1701 | || ! ((*insn_operand_predicate[(int) CODE_FOR_extzv][0]) | |
1702 | (target1, output_mode))) | |
1703 | target1 = gen_reg_rtx (output_mode); | |
1704 | ||
b3d4e1b2 | 1705 | xop1 = protect_from_queue (xop1, 0); |
44037a66 TG |
1706 | xop1 = convert_to_mode (pos_mode, xop1, |
1707 | TREE_UNSIGNED (TREE_TYPE (amount))); | |
1708 | ||
1709 | /* If this machine's extzv insists on a register for | |
1710 | operand 3 (position), arrange for that. */ | |
1711 | if (! ((*insn_operand_predicate[(int) CODE_FOR_extzv][3]) | |
1712 | (xop1, pos_mode))) | |
1713 | xop1 = force_reg (pos_mode, xop1); | |
1714 | ||
1715 | /* WIDTH gets the width of the bit field to extract: | |
1716 | wordsize minus # bits to shift by. */ | |
1717 | if (GET_CODE (xop1) == CONST_INT) | |
b1ec3c92 | 1718 | width = GEN_INT (GET_MODE_BITSIZE (mode) - INTVAL (op1)); |
44037a66 TG |
1719 | else |
1720 | { | |
1721 | /* Now get the width in the proper mode. */ | |
b3d4e1b2 | 1722 | op1 = protect_from_queue (op1, 0); |
44037a66 TG |
1723 | width = convert_to_mode (length_mode, op1, |
1724 | TREE_UNSIGNED (TREE_TYPE (amount))); | |
1725 | ||
1726 | width = expand_binop (length_mode, sub_optab, | |
b1ec3c92 CH |
1727 | GEN_INT (GET_MODE_BITSIZE (mode)), |
1728 | width, NULL_RTX, 0, OPTAB_LIB_WIDEN); | |
44037a66 TG |
1729 | } |
1730 | ||
1731 | /* If this machine's extzv insists on a register for | |
1732 | operand 2 (length), arrange for that. */ | |
1733 | if (! ((*insn_operand_predicate[(int) CODE_FOR_extzv][2]) | |
1734 | (width, length_mode))) | |
1735 | width = force_reg (length_mode, width); | |
1736 | ||
1737 | /* Now extract with WIDTH, omitting OP1 least sig bits. */ | |
1738 | pat = gen_extzv (target1, shifted1, width, xop1); | |
1739 | if (pat) | |
1740 | { | |
1741 | emit_insn (pat); | |
1742 | temp = convert_to_mode (mode, target1, 1); | |
1743 | } | |
1744 | else | |
1745 | delete_insns_since (last); | |
1746 | } | |
1747 | ||
1748 | /* Can also do logical shift with signed bit-field extract | |
1749 | followed by inserting the bit-field at a different position. | |
1750 | That strategy is not yet implemented. */ | |
1751 | } | |
1752 | #endif /* HAVE_extzv */ | |
1753 | } | |
1754 | ||
1755 | if (temp == 0) | |
1756 | abort (); | |
1757 | return temp; | |
1758 | } | |
1759 | \f | |
b385aeda | 1760 | enum alg_code { alg_zero, alg_m, alg_shift, |
b2fb324c | 1761 | alg_add_t_m2, alg_sub_t_m2, |
7963ac37 RK |
1762 | alg_add_factor, alg_sub_factor, |
1763 | alg_add_t2_m, alg_sub_t2_m, | |
b385aeda | 1764 | alg_add, alg_subtract, alg_factor, alg_shiftop }; |
44037a66 TG |
1765 | |
1766 | /* This structure records a sequence of operations. | |
1767 | `ops' is the number of operations recorded. | |
1768 | `cost' is their total cost. | |
1769 | The operations are stored in `op' and the corresponding | |
b385aeda RK |
1770 | logarithms of the integer coefficients in `log'. |
1771 | ||
44037a66 | 1772 | These are the operations: |
b385aeda RK |
1773 | alg_zero total := 0; |
1774 | alg_m total := multiplicand; | |
b2fb324c | 1775 | alg_shift total := total * coeff |
7963ac37 RK |
1776 | alg_add_t_m2 total := total + multiplicand * coeff; |
1777 | alg_sub_t_m2 total := total - multiplicand * coeff; | |
1778 | alg_add_factor total := total * coeff + total; | |
1779 | alg_sub_factor total := total * coeff - total; | |
1780 | alg_add_t2_m total := total * coeff + multiplicand; | |
1781 | alg_sub_t2_m total := total * coeff - multiplicand; | |
b385aeda RK |
1782 | |
1783 | The first operand must be either alg_zero or alg_m. */ | |
44037a66 | 1784 | |
44037a66 TG |
1785 | struct algorithm |
1786 | { | |
7963ac37 RK |
1787 | short cost; |
1788 | short ops; | |
b385aeda RK |
1789 | /* The size of the OP and LOG fields are not directly related to the |
1790 | word size, but the worst-case algorithms will be if we have few | |
1791 | consecutive ones or zeros, i.e., a multiplicand like 10101010101... | |
1792 | In that case we will generate shift-by-2, add, shift-by-2, add,..., | |
1793 | in total wordsize operations. */ | |
44037a66 | 1794 | enum alg_code op[MAX_BITS_PER_WORD]; |
b385aeda | 1795 | char log[MAX_BITS_PER_WORD]; |
44037a66 TG |
1796 | }; |
1797 | ||
1798 | /* Compute and return the best algorithm for multiplying by T. | |
7963ac37 RK |
1799 | The algorithm must cost less than cost_limit |
1800 | If retval.cost >= COST_LIMIT, no algorithm was found and all | |
1801 | other field of the returned struct are undefined. */ | |
44037a66 TG |
1802 | |
1803 | static struct algorithm | |
7963ac37 | 1804 | synth_mult (t, cost_limit) |
b1ec3c92 | 1805 | unsigned HOST_WIDE_INT t; |
7963ac37 | 1806 | int cost_limit; |
44037a66 | 1807 | { |
b2fb324c | 1808 | int m; |
b1ec3c92 CH |
1809 | struct algorithm *best_alg |
1810 | = (struct algorithm *)alloca (sizeof (struct algorithm)); | |
1811 | struct algorithm *alg_in | |
1812 | = (struct algorithm *)alloca (sizeof (struct algorithm)); | |
44037a66 | 1813 | unsigned int cost; |
b2fb324c | 1814 | unsigned HOST_WIDE_INT q; |
44037a66 | 1815 | |
7963ac37 RK |
1816 | /* Indicate that no algorithm is yet found. If no algorithm |
1817 | is found, this value will be returned and indicate failure. */ | |
1818 | best_alg->cost = cost_limit; | |
44037a66 | 1819 | |
b2fb324c | 1820 | if (cost_limit <= 0) |
7963ac37 | 1821 | return *best_alg; |
44037a66 | 1822 | |
b385aeda RK |
1823 | /* t == 1 can be done in zero cost. */ |
1824 | if (t == 1) | |
b2fb324c | 1825 | { |
b385aeda | 1826 | best_alg->ops = 1; |
b2fb324c | 1827 | best_alg->cost = 0; |
b385aeda | 1828 | best_alg->op[0] = alg_m; |
b2fb324c RK |
1829 | return *best_alg; |
1830 | } | |
1831 | ||
b385aeda RK |
1832 | /* t == 0 sometimes has a cost. If it does and it exceeds our limit, |
1833 | fail now. */ | |
1834 | ||
1835 | else if (t == 0) | |
1836 | { | |
1837 | if (zero_cost >= cost_limit) | |
1838 | return *best_alg; | |
1839 | else | |
1840 | { | |
1841 | best_alg->ops = 1; | |
1842 | best_alg->cost = zero_cost; | |
1843 | best_alg->op[0] = alg_zero; | |
1844 | return *best_alg; | |
1845 | } | |
1846 | } | |
1847 | ||
1848 | /* If we have a group of zero bits at the low-order part of T, try | |
1849 | multiplying by the remaining bits and then doing a shift. */ | |
1850 | ||
b2fb324c | 1851 | if ((t & 1) == 0) |
44037a66 | 1852 | { |
b2fb324c RK |
1853 | m = floor_log2 (t & -t); /* m = number of low zero bits */ |
1854 | q = t >> m; | |
1855 | cost = shift_cost[m]; | |
1856 | if (cost < cost_limit) | |
44037a66 | 1857 | { |
b2fb324c RK |
1858 | *alg_in = synth_mult (q, cost_limit - cost); |
1859 | ||
1860 | cost += alg_in->cost; | |
1861 | if (cost < best_alg->cost) | |
44037a66 | 1862 | { |
b2fb324c RK |
1863 | struct algorithm *x; |
1864 | x = alg_in, alg_in = best_alg, best_alg = x; | |
b385aeda | 1865 | best_alg->log[best_alg->ops] = m; |
b2fb324c RK |
1866 | best_alg->op[best_alg->ops++] = alg_shift; |
1867 | best_alg->cost = cost_limit = cost; | |
44037a66 | 1868 | } |
44037a66 | 1869 | } |
44037a66 TG |
1870 | } |
1871 | ||
63610db9 TG |
1872 | /* If we have an odd number, add or subtract one. */ |
1873 | if ((t & 1) != 0) | |
1874 | { | |
1875 | unsigned HOST_WIDE_INT w; | |
1876 | ||
1877 | for (w = 1; (w & t) != 0; w <<= 1) | |
1878 | ; | |
1879 | if (w > 2 | |
1880 | /* Reject the case where t is 3. | |
1881 | Thus we prefer addition in that case. */ | |
1882 | && t != 3) | |
1883 | { | |
1884 | /* T ends with ...111. Multiply by (T + 1) and subtract 1. */ | |
1885 | ||
1886 | cost = add_cost; | |
1887 | *alg_in = synth_mult (t + 1, cost_limit - cost); | |
1888 | ||
1889 | cost += alg_in->cost; | |
1890 | if (cost < best_alg->cost) | |
1891 | { | |
1892 | struct algorithm *x; | |
1893 | x = alg_in, alg_in = best_alg, best_alg = x; | |
1894 | best_alg->log[best_alg->ops] = 0; | |
1895 | best_alg->op[best_alg->ops++] = alg_sub_t_m2; | |
1896 | best_alg->cost = cost_limit = cost; | |
1897 | } | |
1898 | } | |
1899 | else | |
1900 | { | |
1901 | /* T ends with ...01 or ...011. Multiply by (T - 1) and add 1. */ | |
1902 | ||
1903 | cost = add_cost; | |
1904 | *alg_in = synth_mult (t - 1, cost_limit - cost); | |
1905 | ||
1906 | cost += alg_in->cost; | |
1907 | if (cost < best_alg->cost) | |
1908 | { | |
1909 | struct algorithm *x; | |
1910 | x = alg_in, alg_in = best_alg, best_alg = x; | |
1911 | best_alg->log[best_alg->ops] = 0; | |
1912 | best_alg->op[best_alg->ops++] = alg_add_t_m2; | |
1913 | best_alg->cost = cost_limit = cost; | |
1914 | } | |
1915 | } | |
1916 | } | |
1917 | ||
44037a66 | 1918 | /* Look for factors of t of the form |
7963ac37 | 1919 | t = q(2**m +- 1), 2 <= m <= floor(log2(t - 1)). |
44037a66 | 1920 | If we find such a factor, we can multiply by t using an algorithm that |
7963ac37 | 1921 | multiplies by q, shift the result by m and add/subtract it to itself. |
44037a66 | 1922 | |
7963ac37 RK |
1923 | We search for large factors first and loop down, even if large factors |
1924 | are less probable than small; if we find a large factor we will find a | |
1925 | good sequence quickly, and therefore be able to prune (by decreasing | |
1926 | COST_LIMIT) the search. */ | |
1927 | ||
1928 | for (m = floor_log2 (t - 1); m >= 2; m--) | |
44037a66 | 1929 | { |
7963ac37 | 1930 | unsigned HOST_WIDE_INT d; |
44037a66 | 1931 | |
7963ac37 RK |
1932 | d = ((unsigned HOST_WIDE_INT) 1 << m) + 1; |
1933 | if (t % d == 0 && t > d) | |
44037a66 | 1934 | { |
b385aeda | 1935 | cost = MIN (shiftadd_cost[m], add_cost + shift_cost[m]); |
b2fb324c | 1936 | *alg_in = synth_mult (t / d, cost_limit - cost); |
44037a66 | 1937 | |
7963ac37 RK |
1938 | cost += alg_in->cost; |
1939 | if (cost < best_alg->cost) | |
44037a66 | 1940 | { |
7963ac37 RK |
1941 | struct algorithm *x; |
1942 | x = alg_in, alg_in = best_alg, best_alg = x; | |
b385aeda | 1943 | best_alg->log[best_alg->ops] = m; |
7963ac37 RK |
1944 | best_alg->op[best_alg->ops++] = alg_add_factor; |
1945 | best_alg->cost = cost_limit = cost; | |
44037a66 TG |
1946 | } |
1947 | } | |
1948 | ||
7963ac37 RK |
1949 | d = ((unsigned HOST_WIDE_INT) 1 << m) - 1; |
1950 | if (t % d == 0 && t > d) | |
44037a66 | 1951 | { |
b385aeda | 1952 | cost = MIN (shiftsub_cost[m], add_cost + shift_cost[m]); |
b2fb324c | 1953 | *alg_in = synth_mult (t / d, cost_limit - cost); |
44037a66 | 1954 | |
7963ac37 RK |
1955 | cost += alg_in->cost; |
1956 | if (cost < best_alg->cost) | |
44037a66 | 1957 | { |
7963ac37 RK |
1958 | struct algorithm *x; |
1959 | x = alg_in, alg_in = best_alg, best_alg = x; | |
b385aeda | 1960 | best_alg->log[best_alg->ops] = m; |
7963ac37 RK |
1961 | best_alg->op[best_alg->ops++] = alg_sub_factor; |
1962 | best_alg->cost = cost_limit = cost; | |
44037a66 TG |
1963 | } |
1964 | } | |
1965 | } | |
1966 | ||
7963ac37 RK |
1967 | /* Try shift-and-add (load effective address) instructions, |
1968 | i.e. do a*3, a*5, a*9. */ | |
1969 | if ((t & 1) != 0) | |
1970 | { | |
7963ac37 RK |
1971 | q = t - 1; |
1972 | q = q & -q; | |
1973 | m = exact_log2 (q); | |
5eebe2eb | 1974 | if (m >= 0) |
b385aeda | 1975 | { |
5eebe2eb RK |
1976 | cost = shiftadd_cost[m]; |
1977 | *alg_in = synth_mult ((t - 1) >> m, cost_limit - cost); | |
1978 | ||
1979 | cost += alg_in->cost; | |
1980 | if (cost < best_alg->cost) | |
1981 | { | |
1982 | struct algorithm *x; | |
1983 | x = alg_in, alg_in = best_alg, best_alg = x; | |
1984 | best_alg->log[best_alg->ops] = m; | |
1985 | best_alg->op[best_alg->ops++] = alg_add_t2_m; | |
1986 | best_alg->cost = cost_limit = cost; | |
1987 | } | |
7963ac37 | 1988 | } |
44037a66 | 1989 | |
7963ac37 RK |
1990 | q = t + 1; |
1991 | q = q & -q; | |
1992 | m = exact_log2 (q); | |
5eebe2eb | 1993 | if (m >= 0) |
b385aeda | 1994 | { |
5eebe2eb RK |
1995 | cost = shiftsub_cost[m]; |
1996 | *alg_in = synth_mult ((t + 1) >> m, cost_limit - cost); | |
1997 | ||
1998 | cost += alg_in->cost; | |
1999 | if (cost < best_alg->cost) | |
2000 | { | |
2001 | struct algorithm *x; | |
2002 | x = alg_in, alg_in = best_alg, best_alg = x; | |
2003 | best_alg->log[best_alg->ops] = m; | |
2004 | best_alg->op[best_alg->ops++] = alg_sub_t2_m; | |
2005 | best_alg->cost = cost_limit = cost; | |
2006 | } | |
7963ac37 RK |
2007 | } |
2008 | } | |
44037a66 | 2009 | |
b2fb324c RK |
2010 | /* If we are getting a too long sequence for `struct algorithm' |
2011 | to record, store a fake cost to make this search fail. */ | |
2012 | if (best_alg->ops == MAX_BITS_PER_WORD) | |
2013 | best_alg->cost = cost_limit; | |
2014 | ||
44037a66 TG |
2015 | return *best_alg; |
2016 | } | |
2017 | \f | |
2018 | /* Perform a multiplication and return an rtx for the result. | |
2019 | MODE is mode of value; OP0 and OP1 are what to multiply (rtx's); | |
2020 | TARGET is a suggestion for where to store the result (an rtx). | |
2021 | ||
2022 | We check specially for a constant integer as OP1. | |
2023 | If you want this check for OP0 as well, then before calling | |
2024 | you should swap the two operands if OP0 would be constant. */ | |
2025 | ||
2026 | rtx | |
2027 | expand_mult (mode, op0, op1, target, unsignedp) | |
2028 | enum machine_mode mode; | |
2029 | register rtx op0, op1, target; | |
2030 | int unsignedp; | |
2031 | { | |
2032 | rtx const_op1 = op1; | |
2033 | ||
2034 | /* If we are multiplying in DImode, it may still be a win | |
2035 | to try to work with shifts and adds. */ | |
2036 | if (GET_CODE (op1) == CONST_DOUBLE | |
2037 | && GET_MODE_CLASS (GET_MODE (op1)) == MODE_INT | |
2038 | && HOST_BITS_PER_INT <= BITS_PER_WORD) | |
2039 | { | |
2040 | if ((CONST_DOUBLE_HIGH (op1) == 0 && CONST_DOUBLE_LOW (op1) >= 0) | |
2041 | || (CONST_DOUBLE_HIGH (op1) == -1 && CONST_DOUBLE_LOW (op1) < 0)) | |
b1ec3c92 | 2042 | const_op1 = GEN_INT (CONST_DOUBLE_LOW (op1)); |
44037a66 TG |
2043 | } |
2044 | ||
66c1f88e RS |
2045 | /* We used to test optimize here, on the grounds that it's better to |
2046 | produce a smaller program when -O is not used. | |
2047 | But this causes such a terrible slowdown sometimes | |
2048 | that it seems better to use synth_mult always. */ | |
b385aeda | 2049 | |
66c1f88e | 2050 | if (GET_CODE (const_op1) == CONST_INT && ! mult_is_very_cheap) |
44037a66 TG |
2051 | { |
2052 | struct algorithm alg; | |
2053 | struct algorithm neg_alg; | |
2054 | int negate = 0; | |
7963ac37 | 2055 | HOST_WIDE_INT val = INTVAL (op1); |
b385aeda RK |
2056 | HOST_WIDE_INT val_so_far; |
2057 | rtx insn; | |
44037a66 TG |
2058 | |
2059 | /* Try to do the computation two ways: multiply by the negative of OP1 | |
2060 | and then negate, or do the multiplication directly. The latter is | |
2061 | usually faster for positive numbers and the former for negative | |
2062 | numbers, but the opposite can be faster if the original value | |
2063 | has a factor of 2**m +/- 1, while the negated value does not or | |
2064 | vice versa. */ | |
2065 | ||
7963ac37 RK |
2066 | alg = synth_mult (val, mult_cost); |
2067 | neg_alg = synth_mult (- val, | |
b2fb324c | 2068 | (alg.cost < mult_cost ? alg.cost : mult_cost) |
2c414fba | 2069 | - negate_cost); |
44037a66 | 2070 | |
7963ac37 | 2071 | if (neg_alg.cost + negate_cost < alg.cost) |
5eebe2eb | 2072 | alg = neg_alg, negate = 1; |
44037a66 | 2073 | |
7963ac37 | 2074 | if (alg.cost < mult_cost) |
44037a66 | 2075 | { |
b2fb324c | 2076 | /* We found something cheaper than a multiply insn. */ |
7963ac37 | 2077 | int opno; |
44037a66 | 2078 | rtx accum, tem; |
44037a66 TG |
2079 | |
2080 | op0 = protect_from_queue (op0, 0); | |
2081 | ||
2082 | /* Avoid referencing memory over and over. | |
2083 | For speed, but also for correctness when mem is volatile. */ | |
2084 | if (GET_CODE (op0) == MEM) | |
2085 | op0 = force_reg (mode, op0); | |
2086 | ||
b385aeda RK |
2087 | /* ACCUM starts out either as OP0 or as a zero, depending on |
2088 | the first operation. */ | |
2089 | ||
2090 | if (alg.op[0] == alg_zero) | |
44037a66 | 2091 | { |
b385aeda RK |
2092 | accum = copy_to_mode_reg (mode, const0_rtx); |
2093 | val_so_far = 0; | |
2094 | } | |
2095 | else if (alg.op[0] == alg_m) | |
2096 | { | |
2097 | accum = copy_to_mode_reg (mode, op0); | |
2098 | val_so_far = 1; | |
44037a66 | 2099 | } |
b385aeda RK |
2100 | else |
2101 | abort (); | |
7963ac37 RK |
2102 | |
2103 | for (opno = 1; opno < alg.ops; opno++) | |
44037a66 | 2104 | { |
b385aeda RK |
2105 | int log = alg.log[opno]; |
2106 | rtx shift_subtarget = preserve_subexpressions_p () ? 0 : accum; | |
2107 | rtx add_target = opno == alg.ops - 1 && target != 0 ? target : 0; | |
2108 | ||
44037a66 TG |
2109 | switch (alg.op[opno]) |
2110 | { | |
b2fb324c RK |
2111 | case alg_shift: |
2112 | accum = expand_shift (LSHIFT_EXPR, mode, accum, | |
2113 | build_int_2 (log, 0), NULL_RTX, 0); | |
b385aeda | 2114 | val_so_far <<= log; |
b2fb324c RK |
2115 | break; |
2116 | ||
7963ac37 | 2117 | case alg_add_t_m2: |
b385aeda RK |
2118 | tem = expand_shift (LSHIFT_EXPR, mode, op0, |
2119 | build_int_2 (log, 0), NULL_RTX, 0); | |
2120 | accum = force_operand (gen_rtx (PLUS, mode, accum, tem), | |
2121 | add_target ? add_target : accum); | |
2122 | val_so_far += (HOST_WIDE_INT) 1 << log; | |
44037a66 TG |
2123 | break; |
2124 | ||
7963ac37 | 2125 | case alg_sub_t_m2: |
b385aeda RK |
2126 | tem = expand_shift (LSHIFT_EXPR, mode, op0, |
2127 | build_int_2 (log, 0), NULL_RTX, 0); | |
2128 | accum = force_operand (gen_rtx (MINUS, mode, accum, tem), | |
2129 | add_target ? add_target : accum); | |
2130 | val_so_far -= (HOST_WIDE_INT) 1 << log; | |
7963ac37 | 2131 | break; |
44037a66 | 2132 | |
7963ac37 RK |
2133 | case alg_add_t2_m: |
2134 | accum = expand_shift (LSHIFT_EXPR, mode, accum, | |
b385aeda | 2135 | build_int_2 (log, 0), accum, 0); |
7963ac37 | 2136 | accum = force_operand (gen_rtx (PLUS, mode, accum, op0), |
b385aeda RK |
2137 | add_target ? add_target : accum); |
2138 | val_so_far = (val_so_far << log) + 1; | |
44037a66 TG |
2139 | break; |
2140 | ||
7963ac37 RK |
2141 | case alg_sub_t2_m: |
2142 | accum = expand_shift (LSHIFT_EXPR, mode, accum, | |
b385aeda | 2143 | build_int_2 (log, 0), accum, 0); |
7963ac37 | 2144 | accum = force_operand (gen_rtx (MINUS, mode, accum, op0), |
b385aeda RK |
2145 | add_target ? add_target : accum); |
2146 | val_so_far = (val_so_far << log) - 1; | |
7963ac37 RK |
2147 | break; |
2148 | ||
2149 | case alg_add_factor: | |
44037a66 | 2150 | tem = expand_shift (LSHIFT_EXPR, mode, accum, |
b1ec3c92 | 2151 | build_int_2 (log, 0), NULL_RTX, 0); |
b385aeda RK |
2152 | accum = force_operand (gen_rtx (PLUS, mode, accum, tem), |
2153 | add_target ? add_target : accum); | |
2154 | val_so_far += val_so_far << log; | |
7963ac37 | 2155 | break; |
44037a66 | 2156 | |
7963ac37 RK |
2157 | case alg_sub_factor: |
2158 | tem = expand_shift (LSHIFT_EXPR, mode, accum, | |
2159 | build_int_2 (log, 0), NULL_RTX, 0); | |
2160 | accum = force_operand (gen_rtx (MINUS, mode, tem, accum), | |
b385aeda RK |
2161 | add_target ? add_target : tem); |
2162 | val_so_far = (val_so_far << log) - val_so_far; | |
7963ac37 | 2163 | break; |
44037a66 | 2164 | |
b385aeda RK |
2165 | default: |
2166 | abort ();; | |
2167 | } | |
44037a66 | 2168 | |
b385aeda RK |
2169 | /* Write a REG_EQUAL note on the last insn so that we can cse |
2170 | multiplication sequences. */ | |
44037a66 | 2171 | |
b385aeda RK |
2172 | insn = get_last_insn (); |
2173 | REG_NOTES (insn) | |
2174 | = gen_rtx (EXPR_LIST, REG_EQUAL, | |
2175 | gen_rtx (MULT, mode, op0, GEN_INT (val_so_far)), | |
2176 | REG_NOTES (insn)); | |
2177 | } | |
44037a66 | 2178 | |
b385aeda | 2179 | if (negate) |
44037a66 | 2180 | { |
b385aeda RK |
2181 | val_so_far = - val_so_far; |
2182 | accum = expand_unop (mode, neg_optab, accum, target, 0); | |
44037a66 TG |
2183 | } |
2184 | ||
b385aeda RK |
2185 | if (val != val_so_far) |
2186 | abort (); | |
2187 | ||
2188 | return accum; | |
44037a66 TG |
2189 | } |
2190 | } | |
2191 | ||
2192 | /* This used to use umul_optab if unsigned, | |
7963ac37 | 2193 | but for non-widening multiply there is no difference |
44037a66 TG |
2194 | between signed and unsigned. */ |
2195 | op0 = expand_binop (mode, smul_optab, | |
2196 | op0, op1, target, unsignedp, OPTAB_LIB_WIDEN); | |
2197 | if (op0 == 0) | |
2198 | abort (); | |
2199 | return op0; | |
2200 | } | |
2201 | \f | |
2202 | /* Emit the code to divide OP0 by OP1, putting the result in TARGET | |
2203 | if that is convenient, and returning where the result is. | |
2204 | You may request either the quotient or the remainder as the result; | |
2205 | specify REM_FLAG nonzero to get the remainder. | |
2206 | ||
2207 | CODE is the expression code for which kind of division this is; | |
2208 | it controls how rounding is done. MODE is the machine mode to use. | |
2209 | UNSIGNEDP nonzero means do unsigned division. */ | |
2210 | ||
2211 | /* ??? For CEIL_MOD_EXPR, can compute incorrect remainder with ANDI | |
2212 | and then correct it by or'ing in missing high bits | |
2213 | if result of ANDI is nonzero. | |
2214 | For ROUND_MOD_EXPR, can use ANDI and then sign-extend the result. | |
2215 | This could optimize to a bfexts instruction. | |
2216 | But C doesn't use these operations, so their optimizations are | |
2217 | left for later. */ | |
2218 | ||
2219 | rtx | |
2220 | expand_divmod (rem_flag, code, mode, op0, op1, target, unsignedp) | |
2221 | int rem_flag; | |
2222 | enum tree_code code; | |
2223 | enum machine_mode mode; | |
2224 | register rtx op0, op1, target; | |
2225 | int unsignedp; | |
2226 | { | |
2227 | register rtx result = 0; | |
2228 | enum machine_mode compute_mode; | |
2229 | int log = -1; | |
2c414fba | 2230 | int size; |
44037a66 TG |
2231 | int can_clobber_op0; |
2232 | int mod_insn_no_good = 0; | |
2233 | rtx adjusted_op0 = op0; | |
2234 | optab optab1, optab2; | |
2235 | ||
3d32ffd1 TW |
2236 | /* We shouldn't be called with op1 == const1_rtx, but some of the |
2237 | code below will malfunction if we are, so check here and handle | |
2238 | the special case if so. */ | |
2239 | if (op1 == const1_rtx) | |
2240 | return rem_flag ? const0_rtx : op0; | |
2241 | ||
44037a66 TG |
2242 | /* Don't use the function value register as a target |
2243 | since we have to read it as well as write it, | |
2244 | and function-inlining gets confused by this. */ | |
2245 | if (target && REG_P (target) && REG_FUNCTION_VALUE_P (target)) | |
2246 | target = 0; | |
2247 | ||
2248 | /* Don't clobber an operand while doing a multi-step calculation. */ | |
2249 | if (target) | |
2250 | if ((rem_flag && (reg_mentioned_p (target, op0) | |
2251 | || (GET_CODE (op0) == MEM && GET_CODE (target) == MEM))) | |
2252 | || reg_mentioned_p (target, op1) | |
2253 | || (GET_CODE (op1) == MEM && GET_CODE (target) == MEM)) | |
2254 | target = 0; | |
2255 | ||
2256 | can_clobber_op0 = (GET_CODE (op0) == REG && op0 == target); | |
2257 | ||
2258 | if (GET_CODE (op1) == CONST_INT) | |
2259 | log = exact_log2 (INTVAL (op1)); | |
2260 | ||
2261 | /* If log is >= 0, we are dividing by 2**log, and will do it by shifting, | |
2262 | which is really floor-division. Otherwise we will really do a divide, | |
2263 | and we assume that is trunc-division. | |
2264 | ||
2265 | We must correct the dividend by adding or subtracting something | |
2266 | based on the divisor, in order to do the kind of rounding specified | |
2267 | by CODE. The correction depends on what kind of rounding is actually | |
2268 | available, and that depends on whether we will shift or divide. | |
2269 | ||
2270 | In many of these cases it is possible to perform the operation by a | |
2271 | clever series of logical operations (shifts and/or exclusive-ors). | |
2272 | Although avoiding the jump has the advantage that it extends the basic | |
2273 | block and allows further optimization, the branch-free code is normally | |
2274 | at least one instruction longer in the (most common) case where the | |
2275 | dividend is non-negative. Performance measurements of the two | |
2276 | alternatives show that the branch-free code is slightly faster on the | |
2277 | IBM ROMP but slower on CISC processors (significantly slower on the | |
2278 | VAX). Accordingly, the jump code has been retained. | |
2279 | ||
2280 | On machines where the jump code is slower, the cost of a DIV or MOD | |
2281 | operation can be set small (less than twice that of an addition); in | |
2282 | that case, we pretend that we don't have a power of two and perform | |
2283 | a normal division or modulus operation. */ | |
2284 | ||
2285 | if ((code == TRUNC_MOD_EXPR || code == TRUNC_DIV_EXPR) | |
2286 | && ! unsignedp | |
2287 | && (rem_flag ? smod_pow2_cheap : sdiv_pow2_cheap)) | |
2288 | log = -1; | |
2289 | ||
2290 | /* Get the mode in which to perform this computation. Normally it will | |
2291 | be MODE, but sometimes we can't do the desired operation in MODE. | |
2292 | If so, pick a wider mode in which we can do the operation. Convert | |
2293 | to that mode at the start to avoid repeated conversions. | |
2294 | ||
2295 | First see what operations we need. These depend on the expression | |
2296 | we are evaluating. (We assume that divxx3 insns exist under the | |
2297 | same conditions that modxx3 insns and that these insns don't normally | |
2298 | fail. If these assumptions are not correct, we may generate less | |
2299 | efficient code in some cases.) | |
2300 | ||
2301 | Then see if we find a mode in which we can open-code that operation | |
2302 | (either a division, modulus, or shift). Finally, check for the smallest | |
2303 | mode for which we can do the operation with a library call. */ | |
2304 | ||
2305 | optab1 = (log >= 0 ? (unsignedp ? lshr_optab : ashr_optab) | |
2306 | : (unsignedp ? udiv_optab : sdiv_optab)); | |
2307 | optab2 = (log >= 0 ? optab1 : (unsignedp ? udivmod_optab : sdivmod_optab)); | |
2308 | ||
2309 | for (compute_mode = mode; compute_mode != VOIDmode; | |
2310 | compute_mode = GET_MODE_WIDER_MODE (compute_mode)) | |
2311 | if (optab1->handlers[(int) compute_mode].insn_code != CODE_FOR_nothing | |
2312 | || optab2->handlers[(int) compute_mode].insn_code != CODE_FOR_nothing) | |
2313 | break; | |
2314 | ||
2315 | if (compute_mode == VOIDmode) | |
2316 | for (compute_mode = mode; compute_mode != VOIDmode; | |
2317 | compute_mode = GET_MODE_WIDER_MODE (compute_mode)) | |
2318 | if (optab1->handlers[(int) compute_mode].libfunc | |
2319 | || optab2->handlers[(int) compute_mode].libfunc) | |
2320 | break; | |
2321 | ||
2322 | /* If we still couldn't find a mode, use MODE; we'll probably abort in | |
2323 | expand_binop. */ | |
2324 | if (compute_mode == VOIDmode) | |
2325 | compute_mode = mode; | |
2326 | ||
2c414fba RK |
2327 | size = GET_MODE_BITSIZE (compute_mode); |
2328 | ||
44037a66 TG |
2329 | /* Now convert to the best mode to use. Show we made a copy of OP0 |
2330 | and hence we can clobber it (we cannot use a SUBREG to widen | |
2331 | something. */ | |
2332 | if (compute_mode != mode) | |
2333 | { | |
2334 | adjusted_op0 = op0 = convert_to_mode (compute_mode, op0, unsignedp); | |
2335 | can_clobber_op0 = 1; | |
2336 | op1 = convert_to_mode (compute_mode, op1, unsignedp); | |
2337 | } | |
2338 | ||
c2a47e48 RK |
2339 | /* If we are computing the remainder and one of the operands is a volatile |
2340 | MEM, copy it into a register. */ | |
2341 | ||
2342 | if (rem_flag && GET_CODE (op0) == MEM && MEM_VOLATILE_P (op0)) | |
2343 | adjusted_op0 = op0 = force_reg (compute_mode, op0), can_clobber_op0 = 1; | |
2344 | if (rem_flag && GET_CODE (op1) == MEM && MEM_VOLATILE_P (op1)) | |
2345 | op1 = force_reg (compute_mode, op1); | |
2346 | ||
d8064a5d RS |
2347 | /* If we are computing the remainder, op0 will be needed later to calculate |
2348 | X - Y * (X / Y), therefore cannot be clobbered. */ | |
2349 | if (rem_flag) | |
2350 | can_clobber_op0 = 0; | |
2351 | ||
44037a66 TG |
2352 | if (target == 0 || GET_MODE (target) != compute_mode) |
2353 | target = gen_reg_rtx (compute_mode); | |
2354 | ||
2355 | switch (code) | |
2356 | { | |
2357 | case TRUNC_MOD_EXPR: | |
2358 | case TRUNC_DIV_EXPR: | |
2359 | if (log >= 0 && ! unsignedp) | |
2360 | { | |
3d32ffd1 TW |
2361 | /* Here we need to add OP1-1 if OP0 is negative, 0 otherwise. |
2362 | This can be computed without jumps by arithmetically shifting | |
2363 | OP0 right LOG-1 places and then shifting right logically | |
2364 | SIZE-LOG bits. The resulting value is unconditionally added | |
2365 | to OP0. */ | |
2366 | if (log == 1 || BRANCH_COST >= 3) | |
2367 | { | |
2368 | rtx temp = gen_reg_rtx (compute_mode); | |
f2dd8372 RS |
2369 | if (! can_clobber_op0) |
2370 | /* Copy op0 to a reg, to play safe, | |
2371 | since this is done in the other path. */ | |
2372 | op0 = force_reg (compute_mode, op0); | |
3d32ffd1 TW |
2373 | temp = copy_to_suggested_reg (adjusted_op0, temp, compute_mode); |
2374 | temp = expand_shift (RSHIFT_EXPR, compute_mode, temp, | |
2375 | build_int_2 (log - 1, 0), NULL_RTX, 0); | |
2376 | temp = expand_shift (RSHIFT_EXPR, compute_mode, temp, | |
2c414fba | 2377 | build_int_2 (size - log, 0), |
3d32ffd1 | 2378 | temp, 1); |
f2dd8372 RS |
2379 | /* We supply 0 as the target to make a new pseudo |
2380 | for the value; that helps loop.c optimize the result. */ | |
2381 | adjusted_op0 = expand_binop (compute_mode, add_optab, | |
2382 | adjusted_op0, temp, | |
2383 | 0, 0, OPTAB_LIB_WIDEN); | |
3d32ffd1 TW |
2384 | } |
2385 | else | |
2386 | { | |
2387 | rtx label = gen_label_rtx (); | |
f2dd8372 RS |
2388 | if (! can_clobber_op0) |
2389 | { | |
2390 | adjusted_op0 = copy_to_suggested_reg (adjusted_op0, target, | |
2391 | compute_mode); | |
2392 | /* Copy op0 to a reg, since emit_cmp_insn will call emit_queue | |
2393 | which will screw up mem refs for autoincrements. */ | |
2394 | op0 = force_reg (compute_mode, op0); | |
2395 | } | |
3d32ffd1 TW |
2396 | emit_cmp_insn (adjusted_op0, const0_rtx, GE, |
2397 | NULL_RTX, compute_mode, 0, 0); | |
2398 | emit_jump_insn (gen_bge (label)); | |
2399 | expand_inc (adjusted_op0, plus_constant (op1, -1)); | |
2400 | emit_label (label); | |
2401 | } | |
44037a66 TG |
2402 | mod_insn_no_good = 1; |
2403 | } | |
2404 | break; | |
2405 | ||
2406 | case FLOOR_DIV_EXPR: | |
2407 | case FLOOR_MOD_EXPR: | |
2408 | if (log < 0 && ! unsignedp) | |
2409 | { | |
2410 | rtx label = gen_label_rtx (); | |
2411 | if (! can_clobber_op0) | |
2412 | { | |
36d747f6 RS |
2413 | adjusted_op0 = copy_to_suggested_reg (adjusted_op0, target, |
2414 | compute_mode); | |
44037a66 TG |
2415 | /* Copy op0 to a reg, since emit_cmp_insn will call emit_queue |
2416 | which will screw up mem refs for autoincrements. */ | |
2417 | op0 = force_reg (compute_mode, op0); | |
2418 | } | |
b1ec3c92 CH |
2419 | emit_cmp_insn (adjusted_op0, const0_rtx, GE, |
2420 | NULL_RTX, compute_mode, 0, 0); | |
44037a66 TG |
2421 | emit_jump_insn (gen_bge (label)); |
2422 | expand_dec (adjusted_op0, op1); | |
2423 | expand_inc (adjusted_op0, const1_rtx); | |
2424 | emit_label (label); | |
2425 | mod_insn_no_good = 1; | |
2426 | } | |
2427 | break; | |
2428 | ||
2429 | case CEIL_DIV_EXPR: | |
2430 | case CEIL_MOD_EXPR: | |
2431 | if (! can_clobber_op0) | |
2432 | { | |
36d747f6 RS |
2433 | adjusted_op0 = copy_to_suggested_reg (adjusted_op0, target, |
2434 | compute_mode); | |
44037a66 TG |
2435 | /* Copy op0 to a reg, since emit_cmp_insn will call emit_queue |
2436 | which will screw up mem refs for autoincrements. */ | |
2437 | op0 = force_reg (compute_mode, op0); | |
2438 | } | |
2439 | if (log < 0) | |
2440 | { | |
2441 | rtx label = 0; | |
2442 | if (! unsignedp) | |
2443 | { | |
2444 | label = gen_label_rtx (); | |
b1ec3c92 CH |
2445 | emit_cmp_insn (adjusted_op0, const0_rtx, LE, |
2446 | NULL_RTX, compute_mode, 0, 0); | |
44037a66 TG |
2447 | emit_jump_insn (gen_ble (label)); |
2448 | } | |
2449 | expand_inc (adjusted_op0, op1); | |
2450 | expand_dec (adjusted_op0, const1_rtx); | |
2451 | if (! unsignedp) | |
2452 | emit_label (label); | |
2453 | } | |
2454 | else | |
2455 | { | |
2456 | adjusted_op0 = expand_binop (compute_mode, add_optab, | |
2457 | adjusted_op0, plus_constant (op1, -1), | |
b1ec3c92 | 2458 | NULL_RTX, 0, OPTAB_LIB_WIDEN); |
44037a66 TG |
2459 | } |
2460 | mod_insn_no_good = 1; | |
2461 | break; | |
2462 | ||
2463 | case ROUND_DIV_EXPR: | |
2464 | case ROUND_MOD_EXPR: | |
2465 | if (! can_clobber_op0) | |
2466 | { | |
36d747f6 RS |
2467 | adjusted_op0 = copy_to_suggested_reg (adjusted_op0, target, |
2468 | compute_mode); | |
44037a66 TG |
2469 | /* Copy op0 to a reg, since emit_cmp_insn will call emit_queue |
2470 | which will screw up mem refs for autoincrements. */ | |
2471 | op0 = force_reg (compute_mode, op0); | |
2472 | } | |
2473 | if (log < 0) | |
2474 | { | |
2475 | op1 = expand_shift (RSHIFT_EXPR, compute_mode, op1, | |
b1ec3c92 | 2476 | integer_one_node, NULL_RTX, 0); |
44037a66 TG |
2477 | if (! unsignedp) |
2478 | { | |
3d32ffd1 TW |
2479 | if (BRANCH_COST >= 2) |
2480 | { | |
2481 | /* Negate OP1 if OP0 < 0. Do this by computing a temporary | |
2482 | that has all bits equal to the sign bit and exclusive | |
2483 | or-ing it with OP1. */ | |
2484 | rtx temp = gen_reg_rtx (compute_mode); | |
2485 | temp = copy_to_suggested_reg (adjusted_op0, temp, compute_mode); | |
2486 | temp = expand_shift (RSHIFT_EXPR, compute_mode, temp, | |
2c414fba | 2487 | build_int_2 (size - 1, 0), |
3d32ffd1 TW |
2488 | NULL_RTX, 0); |
2489 | op1 = expand_binop (compute_mode, xor_optab, op1, temp, op1, | |
2490 | unsignedp, OPTAB_LIB_WIDEN); | |
2491 | } | |
2492 | else | |
2493 | { | |
2494 | rtx label = gen_label_rtx (); | |
2495 | emit_cmp_insn (adjusted_op0, const0_rtx, GE, NULL_RTX, | |
2496 | compute_mode, 0, 0); | |
2497 | emit_jump_insn (gen_bge (label)); | |
2498 | expand_unop (compute_mode, neg_optab, op1, op1, 0); | |
2499 | emit_label (label); | |
2500 | } | |
44037a66 TG |
2501 | } |
2502 | expand_inc (adjusted_op0, op1); | |
2503 | } | |
2504 | else | |
2505 | { | |
b1ec3c92 | 2506 | op1 = GEN_INT (((HOST_WIDE_INT) 1 << log) / 2); |
44037a66 TG |
2507 | expand_inc (adjusted_op0, op1); |
2508 | } | |
2509 | mod_insn_no_good = 1; | |
2510 | break; | |
2511 | } | |
2512 | ||
2513 | if (rem_flag && !mod_insn_no_good) | |
2514 | { | |
2515 | /* Try to produce the remainder directly */ | |
2516 | if (log >= 0) | |
2517 | result = expand_binop (compute_mode, and_optab, adjusted_op0, | |
b1ec3c92 | 2518 | GEN_INT (((HOST_WIDE_INT) 1 << log) - 1), |
44037a66 TG |
2519 | target, 1, OPTAB_LIB_WIDEN); |
2520 | else | |
2521 | { | |
2522 | /* See if we can do remainder without a library call. */ | |
2523 | result = sign_expand_binop (mode, umod_optab, smod_optab, | |
2524 | adjusted_op0, op1, target, | |
2525 | unsignedp, OPTAB_WIDEN); | |
2526 | if (result == 0) | |
2527 | { | |
2528 | /* No luck there. Can we do remainder and divide at once | |
2529 | without a library call? */ | |
2530 | result = gen_reg_rtx (compute_mode); | |
2531 | if (! expand_twoval_binop (unsignedp | |
2532 | ? udivmod_optab : sdivmod_optab, | |
2533 | adjusted_op0, op1, | |
b1ec3c92 | 2534 | NULL_RTX, result, unsignedp)) |
44037a66 TG |
2535 | result = 0; |
2536 | } | |
2537 | } | |
2538 | } | |
2539 | ||
2540 | if (result) | |
2541 | return gen_lowpart (mode, result); | |
2542 | ||
2543 | /* Produce the quotient. */ | |
2544 | if (log >= 0) | |
2545 | result = expand_shift (RSHIFT_EXPR, compute_mode, adjusted_op0, | |
2546 | build_int_2 (log, 0), target, unsignedp); | |
2547 | else if (rem_flag && !mod_insn_no_good) | |
2548 | /* If producing quotient in order to subtract for remainder, | |
2549 | and a remainder subroutine would be ok, | |
2550 | don't use a divide subroutine. */ | |
2551 | result = sign_expand_binop (compute_mode, udiv_optab, sdiv_optab, | |
b1ec3c92 CH |
2552 | adjusted_op0, op1, NULL_RTX, unsignedp, |
2553 | OPTAB_WIDEN); | |
44037a66 TG |
2554 | else |
2555 | { | |
2556 | /* Try a quotient insn, but not a library call. */ | |
2557 | result = sign_expand_binop (compute_mode, udiv_optab, sdiv_optab, | |
b1ec3c92 CH |
2558 | adjusted_op0, op1, |
2559 | rem_flag ? NULL_RTX : target, | |
44037a66 TG |
2560 | unsignedp, OPTAB_WIDEN); |
2561 | if (result == 0) | |
2562 | { | |
2563 | /* No luck there. Try a quotient-and-remainder insn, | |
2564 | keeping the quotient alone. */ | |
2565 | result = gen_reg_rtx (mode); | |
2566 | if (! expand_twoval_binop (unsignedp ? udivmod_optab : sdivmod_optab, | |
2567 | adjusted_op0, op1, | |
b1ec3c92 | 2568 | result, NULL_RTX, unsignedp)) |
44037a66 TG |
2569 | result = 0; |
2570 | } | |
2571 | ||
2572 | /* If still no luck, use a library call. */ | |
2573 | if (result == 0) | |
2574 | result = sign_expand_binop (compute_mode, udiv_optab, sdiv_optab, | |
b1ec3c92 CH |
2575 | adjusted_op0, op1, |
2576 | rem_flag ? NULL_RTX : target, | |
44037a66 TG |
2577 | unsignedp, OPTAB_LIB_WIDEN); |
2578 | } | |
2579 | ||
2580 | /* If we really want the remainder, get it by subtraction. */ | |
2581 | if (rem_flag) | |
2582 | { | |
2583 | if (result == 0) | |
2584 | /* No divide instruction either. Use library for remainder. */ | |
2585 | result = sign_expand_binop (compute_mode, umod_optab, smod_optab, | |
2586 | op0, op1, target, | |
2587 | unsignedp, OPTAB_LIB_WIDEN); | |
2588 | else | |
2589 | { | |
2590 | /* We divided. Now finish doing X - Y * (X / Y). */ | |
2591 | result = expand_mult (compute_mode, result, op1, target, unsignedp); | |
2592 | if (! result) abort (); | |
2593 | result = expand_binop (compute_mode, sub_optab, op0, | |
2594 | result, target, unsignedp, OPTAB_LIB_WIDEN); | |
2595 | } | |
2596 | } | |
2597 | ||
2598 | if (result == 0) | |
2599 | abort (); | |
2600 | ||
2601 | return gen_lowpart (mode, result); | |
2602 | } | |
2603 | \f | |
2604 | /* Return a tree node with data type TYPE, describing the value of X. | |
2605 | Usually this is an RTL_EXPR, if there is no obvious better choice. | |
2606 | X may be an expression, however we only support those expressions | |
2607 | generated by loop.c. */ | |
2608 | ||
2609 | tree | |
2610 | make_tree (type, x) | |
2611 | tree type; | |
2612 | rtx x; | |
2613 | { | |
2614 | tree t; | |
2615 | ||
2616 | switch (GET_CODE (x)) | |
2617 | { | |
2618 | case CONST_INT: | |
2619 | t = build_int_2 (INTVAL (x), | |
2620 | ! TREE_UNSIGNED (type) && INTVAL (x) >= 0 ? 0 : -1); | |
2621 | TREE_TYPE (t) = type; | |
2622 | return t; | |
2623 | ||
2624 | case CONST_DOUBLE: | |
2625 | if (GET_MODE (x) == VOIDmode) | |
2626 | { | |
2627 | t = build_int_2 (CONST_DOUBLE_LOW (x), CONST_DOUBLE_HIGH (x)); | |
2628 | TREE_TYPE (t) = type; | |
2629 | } | |
2630 | else | |
2631 | { | |
2632 | REAL_VALUE_TYPE d; | |
2633 | ||
2634 | REAL_VALUE_FROM_CONST_DOUBLE (d, x); | |
2635 | t = build_real (type, d); | |
2636 | } | |
2637 | ||
2638 | return t; | |
2639 | ||
2640 | case PLUS: | |
2641 | return fold (build (PLUS_EXPR, type, make_tree (type, XEXP (x, 0)), | |
2642 | make_tree (type, XEXP (x, 1)))); | |
2643 | ||
2644 | case MINUS: | |
2645 | return fold (build (MINUS_EXPR, type, make_tree (type, XEXP (x, 0)), | |
2646 | make_tree (type, XEXP (x, 1)))); | |
2647 | ||
2648 | case NEG: | |
2649 | return fold (build1 (NEGATE_EXPR, type, make_tree (type, XEXP (x, 0)))); | |
2650 | ||
2651 | case MULT: | |
2652 | return fold (build (MULT_EXPR, type, make_tree (type, XEXP (x, 0)), | |
2653 | make_tree (type, XEXP (x, 1)))); | |
2654 | ||
2655 | case ASHIFT: | |
2656 | return fold (build (LSHIFT_EXPR, type, make_tree (type, XEXP (x, 0)), | |
2657 | make_tree (type, XEXP (x, 1)))); | |
2658 | ||
2659 | case LSHIFTRT: | |
2660 | return fold (convert (type, | |
2661 | build (RSHIFT_EXPR, unsigned_type (type), | |
2662 | make_tree (unsigned_type (type), | |
2663 | XEXP (x, 0)), | |
2664 | make_tree (type, XEXP (x, 1))))); | |
2665 | ||
2666 | case ASHIFTRT: | |
2667 | return fold (convert (type, | |
2668 | build (RSHIFT_EXPR, signed_type (type), | |
2669 | make_tree (signed_type (type), XEXP (x, 0)), | |
2670 | make_tree (type, XEXP (x, 1))))); | |
2671 | ||
2672 | case DIV: | |
2673 | if (TREE_CODE (type) != REAL_TYPE) | |
2674 | t = signed_type (type); | |
2675 | else | |
2676 | t = type; | |
2677 | ||
2678 | return fold (convert (type, | |
2679 | build (TRUNC_DIV_EXPR, t, | |
2680 | make_tree (t, XEXP (x, 0)), | |
2681 | make_tree (t, XEXP (x, 1))))); | |
2682 | case UDIV: | |
2683 | t = unsigned_type (type); | |
2684 | return fold (convert (type, | |
2685 | build (TRUNC_DIV_EXPR, t, | |
2686 | make_tree (t, XEXP (x, 0)), | |
2687 | make_tree (t, XEXP (x, 1))))); | |
2688 | default: | |
2689 | t = make_node (RTL_EXPR); | |
2690 | TREE_TYPE (t) = type; | |
2691 | RTL_EXPR_RTL (t) = x; | |
2692 | /* There are no insns to be output | |
2693 | when this rtl_expr is used. */ | |
2694 | RTL_EXPR_SEQUENCE (t) = 0; | |
2695 | return t; | |
2696 | } | |
2697 | } | |
2698 | ||
2699 | /* Return an rtx representing the value of X * MULT + ADD. | |
2700 | TARGET is a suggestion for where to store the result (an rtx). | |
2701 | MODE is the machine mode for the computation. | |
2702 | X and MULT must have mode MODE. ADD may have a different mode. | |
2703 | So can X (defaults to same as MODE). | |
2704 | UNSIGNEDP is non-zero to do unsigned multiplication. | |
2705 | This may emit insns. */ | |
2706 | ||
2707 | rtx | |
2708 | expand_mult_add (x, target, mult, add, mode, unsignedp) | |
2709 | rtx x, target, mult, add; | |
2710 | enum machine_mode mode; | |
2711 | int unsignedp; | |
2712 | { | |
2713 | tree type = type_for_mode (mode, unsignedp); | |
2714 | tree add_type = (GET_MODE (add) == VOIDmode | |
36d747f6 | 2715 | ? type : type_for_mode (GET_MODE (add), unsignedp)); |
44037a66 TG |
2716 | tree result = fold (build (PLUS_EXPR, type, |
2717 | fold (build (MULT_EXPR, type, | |
2718 | make_tree (type, x), | |
2719 | make_tree (type, mult))), | |
2720 | make_tree (add_type, add))); | |
2721 | ||
2722 | return expand_expr (result, target, VOIDmode, 0); | |
2723 | } | |
2724 | \f | |
2725 | /* Compute the logical-and of OP0 and OP1, storing it in TARGET | |
2726 | and returning TARGET. | |
2727 | ||
2728 | If TARGET is 0, a pseudo-register or constant is returned. */ | |
2729 | ||
2730 | rtx | |
2731 | expand_and (op0, op1, target) | |
2732 | rtx op0, op1, target; | |
2733 | { | |
2734 | enum machine_mode mode = VOIDmode; | |
2735 | rtx tem; | |
2736 | ||
2737 | if (GET_MODE (op0) != VOIDmode) | |
2738 | mode = GET_MODE (op0); | |
2739 | else if (GET_MODE (op1) != VOIDmode) | |
2740 | mode = GET_MODE (op1); | |
2741 | ||
2742 | if (mode != VOIDmode) | |
2743 | tem = expand_binop (mode, and_optab, op0, op1, target, 0, OPTAB_LIB_WIDEN); | |
2744 | else if (GET_CODE (op0) == CONST_INT && GET_CODE (op1) == CONST_INT) | |
b1ec3c92 | 2745 | tem = GEN_INT (INTVAL (op0) & INTVAL (op1)); |
44037a66 TG |
2746 | else |
2747 | abort (); | |
2748 | ||
2749 | if (target == 0) | |
2750 | target = tem; | |
2751 | else if (tem != target) | |
2752 | emit_move_insn (target, tem); | |
2753 | return target; | |
2754 | } | |
2755 | \f | |
2756 | /* Emit a store-flags instruction for comparison CODE on OP0 and OP1 | |
2757 | and storing in TARGET. Normally return TARGET. | |
2758 | Return 0 if that cannot be done. | |
2759 | ||
2760 | MODE is the mode to use for OP0 and OP1 should they be CONST_INTs. If | |
2761 | it is VOIDmode, they cannot both be CONST_INT. | |
2762 | ||
2763 | UNSIGNEDP is for the case where we have to widen the operands | |
2764 | to perform the operation. It says to use zero-extension. | |
2765 | ||
2766 | NORMALIZEP is 1 if we should convert the result to be either zero | |
2767 | or one one. Normalize is -1 if we should convert the result to be | |
2768 | either zero or -1. If NORMALIZEP is zero, the result will be left | |
2769 | "raw" out of the scc insn. */ | |
2770 | ||
2771 | rtx | |
2772 | emit_store_flag (target, code, op0, op1, mode, unsignedp, normalizep) | |
2773 | rtx target; | |
2774 | enum rtx_code code; | |
2775 | rtx op0, op1; | |
2776 | enum machine_mode mode; | |
2777 | int unsignedp; | |
2778 | int normalizep; | |
2779 | { | |
2780 | rtx subtarget; | |
2781 | enum insn_code icode; | |
2782 | enum machine_mode compare_mode; | |
2783 | enum machine_mode target_mode = GET_MODE (target); | |
2784 | rtx tem; | |
2785 | rtx last = 0; | |
2786 | rtx pattern, comparison; | |
2787 | ||
2788 | if (mode == VOIDmode) | |
2789 | mode = GET_MODE (op0); | |
2790 | ||
c2615a67 RK |
2791 | /* If one operand is constant, make it the second one. Only do this |
2792 | if the other operand is not constant as well. */ | |
2793 | ||
2794 | if ((CONSTANT_P (op0) && ! CONSTANT_P (op1)) | |
2795 | || (GET_CODE (op0) == CONST_INT && GET_CODE (op1) != CONST_INT)) | |
2796 | { | |
2797 | tem = op0; | |
2798 | op0 = op1; | |
2799 | op1 = tem; | |
2800 | code = swap_condition (code); | |
2801 | } | |
2802 | ||
44037a66 TG |
2803 | /* For some comparisons with 1 and -1, we can convert this to |
2804 | comparisons with zero. This will often produce more opportunities for | |
2805 | store-flag insns. */ | |
2806 | ||
2807 | switch (code) | |
2808 | { | |
2809 | case LT: | |
2810 | if (op1 == const1_rtx) | |
2811 | op1 = const0_rtx, code = LE; | |
2812 | break; | |
2813 | case LE: | |
2814 | if (op1 == constm1_rtx) | |
2815 | op1 = const0_rtx, code = LT; | |
2816 | break; | |
2817 | case GE: | |
2818 | if (op1 == const1_rtx) | |
2819 | op1 = const0_rtx, code = GT; | |
2820 | break; | |
2821 | case GT: | |
2822 | if (op1 == constm1_rtx) | |
2823 | op1 = const0_rtx, code = GE; | |
2824 | break; | |
2825 | case GEU: | |
2826 | if (op1 == const1_rtx) | |
2827 | op1 = const0_rtx, code = NE; | |
2828 | break; | |
2829 | case LTU: | |
2830 | if (op1 == const1_rtx) | |
2831 | op1 = const0_rtx, code = EQ; | |
2832 | break; | |
2833 | } | |
2834 | ||
2835 | /* From now on, we won't change CODE, so set ICODE now. */ | |
2836 | icode = setcc_gen_code[(int) code]; | |
2837 | ||
2838 | /* If this is A < 0 or A >= 0, we can do this by taking the ones | |
2839 | complement of A (for GE) and shifting the sign bit to the low bit. */ | |
2840 | if (op1 == const0_rtx && (code == LT || code == GE) | |
2841 | && GET_MODE_CLASS (mode) == MODE_INT | |
2842 | && (normalizep || STORE_FLAG_VALUE == 1 | |
b1ec3c92 CH |
2843 | || (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT |
2844 | && (STORE_FLAG_VALUE | |
2845 | == (HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))))) | |
44037a66 | 2846 | { |
8deb7047 | 2847 | subtarget = target; |
44037a66 TG |
2848 | |
2849 | /* If the result is to be wider than OP0, it is best to convert it | |
2850 | first. If it is to be narrower, it is *incorrect* to convert it | |
2851 | first. */ | |
2852 | if (GET_MODE_SIZE (target_mode) > GET_MODE_SIZE (mode)) | |
2853 | { | |
b3d4e1b2 | 2854 | op0 = protect_from_queue (op0, 0); |
44037a66 TG |
2855 | op0 = convert_to_mode (target_mode, op0, 0); |
2856 | mode = target_mode; | |
2857 | } | |
2858 | ||
2859 | if (target_mode != mode) | |
2860 | subtarget = 0; | |
2861 | ||
2862 | if (code == GE) | |
2863 | op0 = expand_unop (mode, one_cmpl_optab, op0, subtarget, 0); | |
2864 | ||
2865 | if (normalizep || STORE_FLAG_VALUE == 1) | |
2866 | /* If we are supposed to produce a 0/1 value, we want to do | |
2867 | a logical shift from the sign bit to the low-order bit; for | |
2868 | a -1/0 value, we do an arithmetic shift. */ | |
2869 | op0 = expand_shift (RSHIFT_EXPR, mode, op0, | |
2870 | size_int (GET_MODE_BITSIZE (mode) - 1), | |
2871 | subtarget, normalizep != -1); | |
2872 | ||
2873 | if (mode != target_mode) | |
2874 | op0 = convert_to_mode (target_mode, op0, 0); | |
2875 | ||
2876 | return op0; | |
2877 | } | |
2878 | ||
2879 | if (icode != CODE_FOR_nothing) | |
2880 | { | |
2881 | /* We think we may be able to do this with a scc insn. Emit the | |
2882 | comparison and then the scc insn. | |
2883 | ||
2884 | compare_from_rtx may call emit_queue, which would be deleted below | |
2885 | if the scc insn fails. So call it ourselves before setting LAST. */ | |
2886 | ||
2887 | emit_queue (); | |
2888 | last = get_last_insn (); | |
2889 | ||
b1ec3c92 CH |
2890 | comparison |
2891 | = compare_from_rtx (op0, op1, code, unsignedp, mode, NULL_RTX, 0); | |
44037a66 TG |
2892 | if (GET_CODE (comparison) == CONST_INT) |
2893 | return (comparison == const0_rtx ? const0_rtx | |
2894 | : normalizep == 1 ? const1_rtx | |
2895 | : normalizep == -1 ? constm1_rtx | |
2896 | : const_true_rtx); | |
2897 | ||
c2615a67 RK |
2898 | /* If the code of COMPARISON doesn't match CODE, something is |
2899 | wrong; we can no longer be sure that we have the operation. | |
2900 | We could handle this case, but it should not happen. */ | |
2901 | ||
2902 | if (GET_CODE (comparison) != code) | |
2903 | abort (); | |
8deb7047 | 2904 | |
44037a66 TG |
2905 | /* Get a reference to the target in the proper mode for this insn. */ |
2906 | compare_mode = insn_operand_mode[(int) icode][0]; | |
2907 | subtarget = target; | |
2908 | if (preserve_subexpressions_p () | |
2909 | || ! (*insn_operand_predicate[(int) icode][0]) (subtarget, compare_mode)) | |
2910 | subtarget = gen_reg_rtx (compare_mode); | |
2911 | ||
2912 | pattern = GEN_FCN (icode) (subtarget); | |
2913 | if (pattern) | |
2914 | { | |
2915 | emit_insn (pattern); | |
2916 | ||
2917 | /* If we are converting to a wider mode, first convert to | |
2918 | TARGET_MODE, then normalize. This produces better combining | |
2919 | opportunities on machines that have a SIGN_EXTRACT when we are | |
2920 | testing a single bit. This mostly benefits the 68k. | |
2921 | ||
2922 | If STORE_FLAG_VALUE does not have the sign bit set when | |
2923 | interpreted in COMPARE_MODE, we can do this conversion as | |
2924 | unsigned, which is usually more efficient. */ | |
2925 | if (GET_MODE_SIZE (target_mode) > GET_MODE_SIZE (compare_mode)) | |
2926 | { | |
2927 | convert_move (target, subtarget, | |
2928 | (GET_MODE_BITSIZE (compare_mode) | |
b1ec3c92 | 2929 | <= HOST_BITS_PER_WIDE_INT) |
44037a66 | 2930 | && 0 == (STORE_FLAG_VALUE |
b1ec3c92 CH |
2931 | & ((HOST_WIDE_INT) 1 |
2932 | << (GET_MODE_BITSIZE (compare_mode) -1)))); | |
44037a66 TG |
2933 | op0 = target; |
2934 | compare_mode = target_mode; | |
2935 | } | |
2936 | else | |
2937 | op0 = subtarget; | |
2938 | ||
4b980e20 RK |
2939 | /* If we want to keep subexpressions around, don't reuse our |
2940 | last target. */ | |
2941 | ||
2942 | if (preserve_subexpressions_p ()) | |
2943 | subtarget = 0; | |
2944 | ||
44037a66 TG |
2945 | /* Now normalize to the proper value in COMPARE_MODE. Sometimes |
2946 | we don't have to do anything. */ | |
2947 | if (normalizep == 0 || normalizep == STORE_FLAG_VALUE) | |
2948 | ; | |
2949 | else if (normalizep == - STORE_FLAG_VALUE) | |
2950 | op0 = expand_unop (compare_mode, neg_optab, op0, subtarget, 0); | |
2951 | ||
2952 | /* We don't want to use STORE_FLAG_VALUE < 0 below since this | |
2953 | makes it hard to use a value of just the sign bit due to | |
2954 | ANSI integer constant typing rules. */ | |
b1ec3c92 | 2955 | else if (GET_MODE_BITSIZE (compare_mode) <= HOST_BITS_PER_WIDE_INT |
44037a66 | 2956 | && (STORE_FLAG_VALUE |
b1ec3c92 CH |
2957 | & ((HOST_WIDE_INT) 1 |
2958 | << (GET_MODE_BITSIZE (compare_mode) - 1)))) | |
44037a66 TG |
2959 | op0 = expand_shift (RSHIFT_EXPR, compare_mode, op0, |
2960 | size_int (GET_MODE_BITSIZE (compare_mode) - 1), | |
2961 | subtarget, normalizep == 1); | |
2962 | else if (STORE_FLAG_VALUE & 1) | |
2963 | { | |
2964 | op0 = expand_and (op0, const1_rtx, subtarget); | |
2965 | if (normalizep == -1) | |
2966 | op0 = expand_unop (compare_mode, neg_optab, op0, op0, 0); | |
2967 | } | |
2968 | else | |
2969 | abort (); | |
2970 | ||
2971 | /* If we were converting to a smaller mode, do the | |
2972 | conversion now. */ | |
2973 | if (target_mode != compare_mode) | |
2974 | { | |
522ae84c | 2975 | convert_move (target, op0, 0); |
44037a66 TG |
2976 | return target; |
2977 | } | |
2978 | else | |
2979 | return op0; | |
2980 | } | |
2981 | } | |
2982 | ||
2983 | if (last) | |
2984 | delete_insns_since (last); | |
2985 | ||
2986 | subtarget = target_mode == mode ? target : 0; | |
2987 | ||
2988 | /* If we reached here, we can't do this with a scc insn. However, there | |
2989 | are some comparisons that can be done directly. For example, if | |
2990 | this is an equality comparison of integers, we can try to exclusive-or | |
2991 | (or subtract) the two operands and use a recursive call to try the | |
2992 | comparison with zero. Don't do any of these cases if branches are | |
2993 | very cheap. */ | |
2994 | ||
c8c1bde3 | 2995 | if (BRANCH_COST > 0 |
44037a66 TG |
2996 | && GET_MODE_CLASS (mode) == MODE_INT && (code == EQ || code == NE) |
2997 | && op1 != const0_rtx) | |
2998 | { | |
2999 | tem = expand_binop (mode, xor_optab, op0, op1, subtarget, 1, | |
3000 | OPTAB_WIDEN); | |
3001 | ||
3002 | if (tem == 0) | |
3003 | tem = expand_binop (mode, sub_optab, op0, op1, subtarget, 1, | |
3004 | OPTAB_WIDEN); | |
3005 | if (tem != 0) | |
3006 | tem = emit_store_flag (target, code, tem, const0_rtx, | |
3007 | mode, unsignedp, normalizep); | |
3008 | if (tem == 0) | |
3009 | delete_insns_since (last); | |
3010 | return tem; | |
3011 | } | |
3012 | ||
3013 | /* Some other cases we can do are EQ, NE, LE, and GT comparisons with | |
3014 | the constant zero. Reject all other comparisons at this point. Only | |
3015 | do LE and GT if branches are expensive since they are expensive on | |
3016 | 2-operand machines. */ | |
3017 | ||
3018 | if (BRANCH_COST == 0 | |
3019 | || GET_MODE_CLASS (mode) != MODE_INT || op1 != const0_rtx | |
3020 | || (code != EQ && code != NE | |
3021 | && (BRANCH_COST <= 1 || (code != LE && code != GT)))) | |
3022 | return 0; | |
3023 | ||
3024 | /* See what we need to return. We can only return a 1, -1, or the | |
3025 | sign bit. */ | |
3026 | ||
3027 | if (normalizep == 0) | |
3028 | { | |
3029 | if (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1) | |
3030 | normalizep = STORE_FLAG_VALUE; | |
3031 | ||
b1ec3c92 CH |
3032 | else if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT |
3033 | && (STORE_FLAG_VALUE | |
3034 | == (HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))) | |
44037a66 TG |
3035 | ; |
3036 | else | |
3037 | return 0; | |
3038 | } | |
3039 | ||
3040 | /* Try to put the result of the comparison in the sign bit. Assume we can't | |
3041 | do the necessary operation below. */ | |
3042 | ||
3043 | tem = 0; | |
3044 | ||
3045 | /* To see if A <= 0, compute (A | (A - 1)). A <= 0 iff that result has | |
3046 | the sign bit set. */ | |
3047 | ||
3048 | if (code == LE) | |
3049 | { | |
3050 | /* This is destructive, so SUBTARGET can't be OP0. */ | |
3051 | if (rtx_equal_p (subtarget, op0)) | |
3052 | subtarget = 0; | |
3053 | ||
3054 | tem = expand_binop (mode, sub_optab, op0, const1_rtx, subtarget, 0, | |
3055 | OPTAB_WIDEN); | |
3056 | if (tem) | |
3057 | tem = expand_binop (mode, ior_optab, op0, tem, subtarget, 0, | |
3058 | OPTAB_WIDEN); | |
3059 | } | |
3060 | ||
3061 | /* To see if A > 0, compute (((signed) A) << BITS) - A, where BITS is the | |
3062 | number of bits in the mode of OP0, minus one. */ | |
3063 | ||
3064 | if (code == GT) | |
3065 | { | |
3066 | if (rtx_equal_p (subtarget, op0)) | |
3067 | subtarget = 0; | |
3068 | ||
3069 | tem = expand_shift (RSHIFT_EXPR, mode, op0, | |
3070 | size_int (GET_MODE_BITSIZE (mode) - 1), | |
3071 | subtarget, 0); | |
3072 | tem = expand_binop (mode, sub_optab, tem, op0, subtarget, 0, | |
3073 | OPTAB_WIDEN); | |
3074 | } | |
3075 | ||
3076 | if (code == EQ || code == NE) | |
3077 | { | |
3078 | /* For EQ or NE, one way to do the comparison is to apply an operation | |
3079 | that converts the operand into a positive number if it is non-zero | |
3080 | or zero if it was originally zero. Then, for EQ, we subtract 1 and | |
3081 | for NE we negate. This puts the result in the sign bit. Then we | |
3082 | normalize with a shift, if needed. | |
3083 | ||
3084 | Two operations that can do the above actions are ABS and FFS, so try | |
3085 | them. If that doesn't work, and MODE is smaller than a full word, | |
36d747f6 | 3086 | we can use zero-extension to the wider mode (an unsigned conversion) |
44037a66 TG |
3087 | as the operation. */ |
3088 | ||
3089 | if (abs_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing) | |
3090 | tem = expand_unop (mode, abs_optab, op0, subtarget, 1); | |
3091 | else if (ffs_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing) | |
3092 | tem = expand_unop (mode, ffs_optab, op0, subtarget, 1); | |
3093 | else if (GET_MODE_SIZE (mode) < UNITS_PER_WORD) | |
3094 | { | |
3095 | mode = word_mode; | |
b3d4e1b2 | 3096 | op0 = protect_from_queue (op0, 0); |
44037a66 TG |
3097 | tem = convert_to_mode (mode, op0, 1); |
3098 | } | |
3099 | ||
3100 | if (tem != 0) | |
3101 | { | |
3102 | if (code == EQ) | |
3103 | tem = expand_binop (mode, sub_optab, tem, const1_rtx, subtarget, | |
3104 | 0, OPTAB_WIDEN); | |
3105 | else | |
3106 | tem = expand_unop (mode, neg_optab, tem, subtarget, 0); | |
3107 | } | |
3108 | ||
3109 | /* If we couldn't do it that way, for NE we can "or" the two's complement | |
3110 | of the value with itself. For EQ, we take the one's complement of | |
3111 | that "or", which is an extra insn, so we only handle EQ if branches | |
3112 | are expensive. */ | |
3113 | ||
3114 | if (tem == 0 && (code == NE || BRANCH_COST > 1)) | |
3115 | { | |
36d747f6 RS |
3116 | if (rtx_equal_p (subtarget, op0)) |
3117 | subtarget = 0; | |
3118 | ||
44037a66 TG |
3119 | tem = expand_unop (mode, neg_optab, op0, subtarget, 0); |
3120 | tem = expand_binop (mode, ior_optab, tem, op0, subtarget, 0, | |
3121 | OPTAB_WIDEN); | |
3122 | ||
3123 | if (tem && code == EQ) | |
3124 | tem = expand_unop (mode, one_cmpl_optab, tem, subtarget, 0); | |
3125 | } | |
3126 | } | |
3127 | ||
3128 | if (tem && normalizep) | |
3129 | tem = expand_shift (RSHIFT_EXPR, mode, tem, | |
3130 | size_int (GET_MODE_BITSIZE (mode) - 1), | |
3131 | tem, normalizep == 1); | |
3132 | ||
3133 | if (tem && GET_MODE (tem) != target_mode) | |
3134 | { | |
3135 | convert_move (target, tem, 0); | |
3136 | tem = target; | |
3137 | } | |
3138 | ||
3139 | if (tem == 0) | |
3140 | delete_insns_since (last); | |
3141 | ||
3142 | return tem; | |
3143 | } | |
3144 | emit_jump_insn ((*bcc_gen_fctn[(int) code]) (label)); | |
3145 | emit_move_insn (target, const1_rtx); | |
3146 | emit_label (label); | |
3147 | ||
3148 | return target; | |
3149 | } |