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23b2ce53 | 1 | /* Emit RTL for the GNU C-Compiler expander. |
ef58a523 JL |
2 | Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998, |
3 | 1999, 2000 Free Software Foundation, Inc. | |
23b2ce53 RS |
4 | |
5 | This file is part of GNU CC. | |
6 | ||
7 | GNU CC is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2, or (at your option) | |
10 | any later version. | |
11 | ||
12 | GNU CC is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GNU CC; see the file COPYING. If not, write to | |
940d9d63 RK |
19 | the Free Software Foundation, 59 Temple Place - Suite 330, |
20 | Boston, MA 02111-1307, USA. */ | |
23b2ce53 RS |
21 | |
22 | ||
23 | /* Middle-to-low level generation of rtx code and insns. | |
24 | ||
25 | This file contains the functions `gen_rtx', `gen_reg_rtx' | |
26 | and `gen_label_rtx' that are the usual ways of creating rtl | |
27 | expressions for most purposes. | |
28 | ||
29 | It also has the functions for creating insns and linking | |
30 | them in the doubly-linked chain. | |
31 | ||
32 | The patterns of the insns are created by machine-dependent | |
33 | routines in insn-emit.c, which is generated automatically from | |
34 | the machine description. These routines use `gen_rtx' to make | |
35 | the individual rtx's of the pattern; what is machine dependent | |
36 | is the kind of rtx's they make and what arguments they use. */ | |
37 | ||
38 | #include "config.h" | |
670ee920 | 39 | #include "system.h" |
01198c2f | 40 | #include "toplev.h" |
23b2ce53 | 41 | #include "rtl.h" |
a25c7971 | 42 | #include "tree.h" |
6baf1cc8 | 43 | #include "tm_p.h" |
23b2ce53 RS |
44 | #include "flags.h" |
45 | #include "function.h" | |
46 | #include "expr.h" | |
47 | #include "regs.h" | |
aff48bca | 48 | #include "hard-reg-set.h" |
c13e8210 | 49 | #include "hashtab.h" |
23b2ce53 | 50 | #include "insn-config.h" |
e9a25f70 | 51 | #include "recog.h" |
23b2ce53 | 52 | #include "real.h" |
ca695ac9 | 53 | #include "obstack.h" |
0dfa1860 | 54 | #include "bitmap.h" |
a05924f9 | 55 | #include "basic-block.h" |
87ff9c8e | 56 | #include "ggc.h" |
ca695ac9 | 57 | |
1d445e9e ILT |
58 | /* Commonly used modes. */ |
59 | ||
0f41302f MS |
60 | enum machine_mode byte_mode; /* Mode whose width is BITS_PER_UNIT. */ |
61 | enum machine_mode word_mode; /* Mode whose width is BITS_PER_WORD. */ | |
9ec36da5 | 62 | enum machine_mode double_mode; /* Mode whose width is DOUBLE_TYPE_SIZE. */ |
0f41302f | 63 | enum machine_mode ptr_mode; /* Mode whose width is POINTER_SIZE. */ |
1d445e9e | 64 | |
23b2ce53 RS |
65 | |
66 | /* This is *not* reset after each function. It gives each CODE_LABEL | |
67 | in the entire compilation a unique label number. */ | |
68 | ||
69 | static int label_num = 1; | |
70 | ||
23b2ce53 RS |
71 | /* Highest label number in current function. |
72 | Zero means use the value of label_num instead. | |
73 | This is nonzero only when belatedly compiling an inline function. */ | |
74 | ||
75 | static int last_label_num; | |
76 | ||
77 | /* Value label_num had when set_new_first_and_last_label_number was called. | |
78 | If label_num has not changed since then, last_label_num is valid. */ | |
79 | ||
80 | static int base_label_num; | |
81 | ||
82 | /* Nonzero means do not generate NOTEs for source line numbers. */ | |
83 | ||
84 | static int no_line_numbers; | |
85 | ||
86 | /* Commonly used rtx's, so that we only need space for one copy. | |
87 | These are initialized once for the entire compilation. | |
88 | All of these except perhaps the floating-point CONST_DOUBLEs | |
89 | are unique; no other rtx-object will be equal to any of these. */ | |
90 | ||
5da077de | 91 | rtx global_rtl[GR_MAX]; |
23b2ce53 RS |
92 | |
93 | /* We record floating-point CONST_DOUBLEs in each floating-point mode for | |
94 | the values of 0, 1, and 2. For the integer entries and VOIDmode, we | |
95 | record a copy of const[012]_rtx. */ | |
96 | ||
97 | rtx const_tiny_rtx[3][(int) MAX_MACHINE_MODE]; | |
98 | ||
68d75312 JC |
99 | rtx const_true_rtx; |
100 | ||
23b2ce53 RS |
101 | REAL_VALUE_TYPE dconst0; |
102 | REAL_VALUE_TYPE dconst1; | |
103 | REAL_VALUE_TYPE dconst2; | |
104 | REAL_VALUE_TYPE dconstm1; | |
105 | ||
106 | /* All references to the following fixed hard registers go through | |
107 | these unique rtl objects. On machines where the frame-pointer and | |
108 | arg-pointer are the same register, they use the same unique object. | |
109 | ||
110 | After register allocation, other rtl objects which used to be pseudo-regs | |
111 | may be clobbered to refer to the frame-pointer register. | |
112 | But references that were originally to the frame-pointer can be | |
113 | distinguished from the others because they contain frame_pointer_rtx. | |
114 | ||
ac6f08b0 DE |
115 | When to use frame_pointer_rtx and hard_frame_pointer_rtx is a little |
116 | tricky: until register elimination has taken place hard_frame_pointer_rtx | |
117 | should be used if it is being set, and frame_pointer_rtx otherwise. After | |
118 | register elimination hard_frame_pointer_rtx should always be used. | |
119 | On machines where the two registers are same (most) then these are the | |
120 | same. | |
121 | ||
23b2ce53 RS |
122 | In an inline procedure, the stack and frame pointer rtxs may not be |
123 | used for anything else. */ | |
23b2ce53 RS |
124 | rtx struct_value_rtx; /* (REG:Pmode STRUCT_VALUE_REGNUM) */ |
125 | rtx struct_value_incoming_rtx; /* (REG:Pmode STRUCT_VALUE_INCOMING_REGNUM) */ | |
126 | rtx static_chain_rtx; /* (REG:Pmode STATIC_CHAIN_REGNUM) */ | |
127 | rtx static_chain_incoming_rtx; /* (REG:Pmode STATIC_CHAIN_INCOMING_REGNUM) */ | |
128 | rtx pic_offset_table_rtx; /* (REG:Pmode PIC_OFFSET_TABLE_REGNUM) */ | |
129 | ||
a4417a86 JW |
130 | /* This is used to implement __builtin_return_address for some machines. |
131 | See for instance the MIPS port. */ | |
132 | rtx return_address_pointer_rtx; /* (REG:Pmode RETURN_ADDRESS_POINTER_REGNUM) */ | |
133 | ||
23b2ce53 RS |
134 | /* We make one copy of (const_int C) where C is in |
135 | [- MAX_SAVED_CONST_INT, MAX_SAVED_CONST_INT] | |
136 | to save space during the compilation and simplify comparisons of | |
137 | integers. */ | |
138 | ||
5da077de | 139 | rtx const_int_rtx[MAX_SAVED_CONST_INT * 2 + 1]; |
23b2ce53 | 140 | |
c13e8210 MM |
141 | /* A hash table storing CONST_INTs whose absolute value is greater |
142 | than MAX_SAVED_CONST_INT. */ | |
143 | ||
144 | static htab_t const_int_htab; | |
145 | ||
23b2ce53 RS |
146 | /* start_sequence and gen_sequence can make a lot of rtx expressions which are |
147 | shortly thrown away. We use two mechanisms to prevent this waste: | |
148 | ||
a3770a81 RH |
149 | For sizes up to 5 elements, we keep a SEQUENCE and its associated |
150 | rtvec for use by gen_sequence. One entry for each size is | |
151 | sufficient because most cases are calls to gen_sequence followed by | |
152 | immediately emitting the SEQUENCE. Reuse is safe since emitting a | |
153 | sequence is destructive on the insn in it anyway and hence can't be | |
154 | redone. | |
23b2ce53 RS |
155 | |
156 | We do not bother to save this cached data over nested function calls. | |
157 | Instead, we just reinitialize them. */ | |
158 | ||
159 | #define SEQUENCE_RESULT_SIZE 5 | |
160 | ||
23b2ce53 RS |
161 | static rtx sequence_result[SEQUENCE_RESULT_SIZE]; |
162 | ||
0f41302f | 163 | /* During RTL generation, we also keep a list of free INSN rtl codes. */ |
43127294 RK |
164 | static rtx free_insn; |
165 | ||
01d939e8 BS |
166 | #define first_insn (cfun->emit->x_first_insn) |
167 | #define last_insn (cfun->emit->x_last_insn) | |
168 | #define cur_insn_uid (cfun->emit->x_cur_insn_uid) | |
169 | #define last_linenum (cfun->emit->x_last_linenum) | |
170 | #define last_filename (cfun->emit->x_last_filename) | |
171 | #define first_label_num (cfun->emit->x_first_label_num) | |
23b2ce53 | 172 | |
da43a810 BS |
173 | /* This is where the pointer to the obstack being used for RTL is stored. */ |
174 | extern struct obstack *rtl_obstack; | |
175 | ||
711d877c KG |
176 | static rtx make_jump_insn_raw PARAMS ((rtx)); |
177 | static rtx make_call_insn_raw PARAMS ((rtx)); | |
178 | static rtx find_line_note PARAMS ((rtx)); | |
179 | static void mark_sequence_stack PARAMS ((struct sequence_stack *)); | |
d1b81779 | 180 | static void unshare_all_rtl_1 PARAMS ((rtx)); |
c13e8210 MM |
181 | static hashval_t const_int_htab_hash PARAMS ((const void *)); |
182 | static int const_int_htab_eq PARAMS ((const void *, | |
183 | const void *)); | |
184 | static int rtx_htab_mark_1 PARAMS ((void **, void *)); | |
185 | static void rtx_htab_mark PARAMS ((void *)); | |
186 | ||
ca695ac9 | 187 | \f |
c13e8210 MM |
188 | /* Returns a hash code for X (which is a really a CONST_INT). */ |
189 | ||
190 | static hashval_t | |
191 | const_int_htab_hash (x) | |
192 | const void *x; | |
193 | { | |
e77d72cb | 194 | return (hashval_t) INTVAL ((const struct rtx_def *) x); |
c13e8210 MM |
195 | } |
196 | ||
197 | /* Returns non-zero if the value represented by X (which is really a | |
198 | CONST_INT) is the same as that given by Y (which is really a | |
199 | HOST_WIDE_INT *). */ | |
200 | ||
201 | static int | |
202 | const_int_htab_eq (x, y) | |
203 | const void *x; | |
204 | const void *y; | |
205 | { | |
e77d72cb | 206 | return (INTVAL ((const struct rtx_def *) x) == *((const HOST_WIDE_INT *) y)); |
c13e8210 MM |
207 | } |
208 | ||
209 | /* Mark the hash-table element X (which is really a pointer to an | |
210 | rtx). */ | |
211 | ||
212 | static int | |
213 | rtx_htab_mark_1 (x, data) | |
214 | void **x; | |
215 | void *data ATTRIBUTE_UNUSED; | |
216 | { | |
217 | ggc_mark_rtx (*x); | |
218 | return 1; | |
219 | } | |
220 | ||
221 | /* Mark all the elements of HTAB (which is really an htab_t full of | |
222 | rtxs). */ | |
223 | ||
224 | static void | |
225 | rtx_htab_mark (htab) | |
226 | void *htab; | |
227 | { | |
228 | htab_traverse (*((htab_t *) htab), rtx_htab_mark_1, NULL); | |
229 | } | |
230 | ||
c5c76735 JL |
231 | /* There are some RTL codes that require special attention; the generation |
232 | functions do the raw handling. If you add to this list, modify | |
233 | special_rtx in gengenrtl.c as well. */ | |
234 | ||
3b80f6ca RH |
235 | rtx |
236 | gen_rtx_CONST_INT (mode, arg) | |
c13e8210 | 237 | enum machine_mode mode ATTRIBUTE_UNUSED; |
3b80f6ca RH |
238 | HOST_WIDE_INT arg; |
239 | { | |
c13e8210 MM |
240 | void **slot; |
241 | ||
3b80f6ca | 242 | if (arg >= - MAX_SAVED_CONST_INT && arg <= MAX_SAVED_CONST_INT) |
5da077de | 243 | return const_int_rtx[arg + MAX_SAVED_CONST_INT]; |
3b80f6ca RH |
244 | |
245 | #if STORE_FLAG_VALUE != 1 && STORE_FLAG_VALUE != -1 | |
246 | if (const_true_rtx && arg == STORE_FLAG_VALUE) | |
247 | return const_true_rtx; | |
248 | #endif | |
249 | ||
c13e8210 | 250 | /* Look up the CONST_INT in the hash table. */ |
e38992e8 RK |
251 | slot = htab_find_slot_with_hash (const_int_htab, &arg, |
252 | (hashval_t) arg, INSERT); | |
29105cea | 253 | if (*slot == 0) |
8dd2076d MM |
254 | { |
255 | if (!ggc_p) | |
256 | { | |
257 | push_obstacks_nochange (); | |
258 | end_temporary_allocation (); | |
29105cea RK |
259 | *slot = gen_rtx_raw_CONST_INT (VOIDmode, arg); |
260 | pop_obstacks (); | |
8dd2076d | 261 | } |
29105cea RK |
262 | else |
263 | *slot = gen_rtx_raw_CONST_INT (VOIDmode, arg); | |
8dd2076d | 264 | } |
c13e8210 MM |
265 | |
266 | return (rtx) *slot; | |
3b80f6ca RH |
267 | } |
268 | ||
29105cea | 269 | /* CONST_DOUBLEs needs special handling because their length is known |
0133b7d9 | 270 | only at run-time. */ |
29105cea | 271 | |
0133b7d9 RH |
272 | rtx |
273 | gen_rtx_CONST_DOUBLE (mode, arg0, arg1, arg2) | |
274 | enum machine_mode mode; | |
275 | rtx arg0; | |
276 | HOST_WIDE_INT arg1, arg2; | |
277 | { | |
278 | rtx r = rtx_alloc (CONST_DOUBLE); | |
2454beaf RH |
279 | int i; |
280 | ||
0133b7d9 RH |
281 | PUT_MODE (r, mode); |
282 | XEXP (r, 0) = arg0; | |
ef178af3 | 283 | X0EXP (r, 1) = NULL_RTX; |
2454beaf RH |
284 | XWINT (r, 2) = arg1; |
285 | XWINT (r, 3) = arg2; | |
286 | ||
287 | for (i = GET_RTX_LENGTH (CONST_DOUBLE) - 1; i > 3; --i) | |
288 | XWINT (r, i) = 0; | |
289 | ||
0133b7d9 RH |
290 | return r; |
291 | } | |
292 | ||
3b80f6ca RH |
293 | rtx |
294 | gen_rtx_REG (mode, regno) | |
295 | enum machine_mode mode; | |
296 | int regno; | |
297 | { | |
298 | /* In case the MD file explicitly references the frame pointer, have | |
299 | all such references point to the same frame pointer. This is | |
300 | used during frame pointer elimination to distinguish the explicit | |
301 | references to these registers from pseudos that happened to be | |
302 | assigned to them. | |
303 | ||
304 | If we have eliminated the frame pointer or arg pointer, we will | |
305 | be using it as a normal register, for example as a spill | |
306 | register. In such cases, we might be accessing it in a mode that | |
307 | is not Pmode and therefore cannot use the pre-allocated rtx. | |
308 | ||
309 | Also don't do this when we are making new REGs in reload, since | |
310 | we don't want to get confused with the real pointers. */ | |
311 | ||
312 | if (mode == Pmode && !reload_in_progress) | |
313 | { | |
bcb33994 | 314 | if (regno == FRAME_POINTER_REGNUM) |
3b80f6ca RH |
315 | return frame_pointer_rtx; |
316 | #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM | |
bcb33994 | 317 | if (regno == HARD_FRAME_POINTER_REGNUM) |
3b80f6ca RH |
318 | return hard_frame_pointer_rtx; |
319 | #endif | |
320 | #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM && HARD_FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM | |
bcb33994 | 321 | if (regno == ARG_POINTER_REGNUM) |
3b80f6ca RH |
322 | return arg_pointer_rtx; |
323 | #endif | |
324 | #ifdef RETURN_ADDRESS_POINTER_REGNUM | |
bcb33994 | 325 | if (regno == RETURN_ADDRESS_POINTER_REGNUM) |
3b80f6ca RH |
326 | return return_address_pointer_rtx; |
327 | #endif | |
bcb33994 | 328 | if (regno == STACK_POINTER_REGNUM) |
3b80f6ca RH |
329 | return stack_pointer_rtx; |
330 | } | |
331 | ||
332 | return gen_rtx_raw_REG (mode, regno); | |
333 | } | |
334 | ||
41472af8 MM |
335 | rtx |
336 | gen_rtx_MEM (mode, addr) | |
337 | enum machine_mode mode; | |
338 | rtx addr; | |
339 | { | |
340 | rtx rt = gen_rtx_raw_MEM (mode, addr); | |
341 | ||
342 | /* This field is not cleared by the mere allocation of the rtx, so | |
343 | we clear it here. */ | |
344 | MEM_ALIAS_SET (rt) = 0; | |
345 | ||
346 | return rt; | |
347 | } | |
c5c76735 | 348 | \f |
23b2ce53 RS |
349 | /* rtx gen_rtx (code, mode, [element1, ..., elementn]) |
350 | ** | |
351 | ** This routine generates an RTX of the size specified by | |
352 | ** <code>, which is an RTX code. The RTX structure is initialized | |
353 | ** from the arguments <element1> through <elementn>, which are | |
354 | ** interpreted according to the specific RTX type's format. The | |
355 | ** special machine mode associated with the rtx (if any) is specified | |
356 | ** in <mode>. | |
357 | ** | |
1632afca | 358 | ** gen_rtx can be invoked in a way which resembles the lisp-like |
23b2ce53 RS |
359 | ** rtx it will generate. For example, the following rtx structure: |
360 | ** | |
361 | ** (plus:QI (mem:QI (reg:SI 1)) | |
362 | ** (mem:QI (plusw:SI (reg:SI 2) (reg:SI 3)))) | |
363 | ** | |
364 | ** ...would be generated by the following C code: | |
365 | ** | |
366 | ** gen_rtx (PLUS, QImode, | |
367 | ** gen_rtx (MEM, QImode, | |
368 | ** gen_rtx (REG, SImode, 1)), | |
369 | ** gen_rtx (MEM, QImode, | |
370 | ** gen_rtx (PLUS, SImode, | |
371 | ** gen_rtx (REG, SImode, 2), | |
372 | ** gen_rtx (REG, SImode, 3)))), | |
373 | */ | |
374 | ||
375 | /*VARARGS2*/ | |
376 | rtx | |
711d877c | 377 | gen_rtx VPARAMS ((enum rtx_code code, enum machine_mode mode, ...)) |
23b2ce53 | 378 | { |
5148a72b | 379 | #ifndef ANSI_PROTOTYPES |
23b2ce53 RS |
380 | enum rtx_code code; |
381 | enum machine_mode mode; | |
4f90e4a0 RK |
382 | #endif |
383 | va_list p; | |
23b2ce53 | 384 | register int i; /* Array indices... */ |
6f7d635c | 385 | register const char *fmt; /* Current rtx's format... */ |
23b2ce53 RS |
386 | register rtx rt_val; /* RTX to return to caller... */ |
387 | ||
4f90e4a0 RK |
388 | VA_START (p, mode); |
389 | ||
5148a72b | 390 | #ifndef ANSI_PROTOTYPES |
23b2ce53 RS |
391 | code = va_arg (p, enum rtx_code); |
392 | mode = va_arg (p, enum machine_mode); | |
4f90e4a0 | 393 | #endif |
23b2ce53 | 394 | |
0133b7d9 | 395 | switch (code) |
23b2ce53 | 396 | { |
0133b7d9 RH |
397 | case CONST_INT: |
398 | rt_val = gen_rtx_CONST_INT (mode, va_arg (p, HOST_WIDE_INT)); | |
399 | break; | |
400 | ||
401 | case CONST_DOUBLE: | |
402 | { | |
403 | rtx arg0 = va_arg (p, rtx); | |
404 | HOST_WIDE_INT arg1 = va_arg (p, HOST_WIDE_INT); | |
405 | HOST_WIDE_INT arg2 = va_arg (p, HOST_WIDE_INT); | |
406 | rt_val = gen_rtx_CONST_DOUBLE (mode, arg0, arg1, arg2); | |
407 | } | |
408 | break; | |
409 | ||
410 | case REG: | |
411 | rt_val = gen_rtx_REG (mode, va_arg (p, int)); | |
412 | break; | |
413 | ||
414 | case MEM: | |
415 | rt_val = gen_rtx_MEM (mode, va_arg (p, rtx)); | |
416 | break; | |
417 | ||
418 | default: | |
23b2ce53 RS |
419 | rt_val = rtx_alloc (code); /* Allocate the storage space. */ |
420 | rt_val->mode = mode; /* Store the machine mode... */ | |
421 | ||
422 | fmt = GET_RTX_FORMAT (code); /* Find the right format... */ | |
423 | for (i = 0; i < GET_RTX_LENGTH (code); i++) | |
424 | { | |
425 | switch (*fmt++) | |
426 | { | |
427 | case '0': /* Unused field. */ | |
428 | break; | |
429 | ||
430 | case 'i': /* An integer? */ | |
431 | XINT (rt_val, i) = va_arg (p, int); | |
432 | break; | |
433 | ||
906c4e36 RK |
434 | case 'w': /* A wide integer? */ |
435 | XWINT (rt_val, i) = va_arg (p, HOST_WIDE_INT); | |
436 | break; | |
437 | ||
23b2ce53 RS |
438 | case 's': /* A string? */ |
439 | XSTR (rt_val, i) = va_arg (p, char *); | |
440 | break; | |
441 | ||
442 | case 'e': /* An expression? */ | |
443 | case 'u': /* An insn? Same except when printing. */ | |
444 | XEXP (rt_val, i) = va_arg (p, rtx); | |
445 | break; | |
446 | ||
447 | case 'E': /* An RTX vector? */ | |
448 | XVEC (rt_val, i) = va_arg (p, rtvec); | |
449 | break; | |
450 | ||
0dfa1860 MM |
451 | case 'b': /* A bitmap? */ |
452 | XBITMAP (rt_val, i) = va_arg (p, bitmap); | |
453 | break; | |
454 | ||
455 | case 't': /* A tree? */ | |
456 | XTREE (rt_val, i) = va_arg (p, tree); | |
457 | break; | |
458 | ||
23b2ce53 | 459 | default: |
1632afca | 460 | abort (); |
23b2ce53 RS |
461 | } |
462 | } | |
0133b7d9 | 463 | break; |
23b2ce53 | 464 | } |
0133b7d9 | 465 | |
23b2ce53 | 466 | va_end (p); |
0133b7d9 | 467 | return rt_val; |
23b2ce53 RS |
468 | } |
469 | ||
470 | /* gen_rtvec (n, [rt1, ..., rtn]) | |
471 | ** | |
472 | ** This routine creates an rtvec and stores within it the | |
473 | ** pointers to rtx's which are its arguments. | |
474 | */ | |
475 | ||
476 | /*VARARGS1*/ | |
477 | rtvec | |
711d877c | 478 | gen_rtvec VPARAMS ((int n, ...)) |
23b2ce53 | 479 | { |
5148a72b | 480 | #ifndef ANSI_PROTOTYPES |
4f90e4a0 RK |
481 | int n; |
482 | #endif | |
483 | int i; | |
23b2ce53 RS |
484 | va_list p; |
485 | rtx *vector; | |
486 | ||
4f90e4a0 RK |
487 | VA_START (p, n); |
488 | ||
5148a72b | 489 | #ifndef ANSI_PROTOTYPES |
23b2ce53 | 490 | n = va_arg (p, int); |
4f90e4a0 | 491 | #endif |
23b2ce53 RS |
492 | |
493 | if (n == 0) | |
494 | return NULL_RTVEC; /* Don't allocate an empty rtvec... */ | |
495 | ||
496 | vector = (rtx *) alloca (n * sizeof (rtx)); | |
4f90e4a0 | 497 | |
23b2ce53 RS |
498 | for (i = 0; i < n; i++) |
499 | vector[i] = va_arg (p, rtx); | |
500 | va_end (p); | |
501 | ||
502 | return gen_rtvec_v (n, vector); | |
503 | } | |
504 | ||
505 | rtvec | |
506 | gen_rtvec_v (n, argp) | |
507 | int n; | |
508 | rtx *argp; | |
509 | { | |
510 | register int i; | |
511 | register rtvec rt_val; | |
512 | ||
513 | if (n == 0) | |
514 | return NULL_RTVEC; /* Don't allocate an empty rtvec... */ | |
515 | ||
516 | rt_val = rtvec_alloc (n); /* Allocate an rtvec... */ | |
517 | ||
518 | for (i = 0; i < n; i++) | |
8f985ec4 | 519 | rt_val->elem[i] = *argp++; |
23b2ce53 RS |
520 | |
521 | return rt_val; | |
522 | } | |
ba444f92 | 523 | |
23b2ce53 RS |
524 | \f |
525 | /* Generate a REG rtx for a new pseudo register of mode MODE. | |
526 | This pseudo is assigned the next sequential register number. */ | |
527 | ||
528 | rtx | |
529 | gen_reg_rtx (mode) | |
530 | enum machine_mode mode; | |
531 | { | |
01d939e8 | 532 | struct function *f = cfun; |
23b2ce53 RS |
533 | register rtx val; |
534 | ||
f1db3576 JL |
535 | /* Don't let anything called after initial flow analysis create new |
536 | registers. */ | |
537 | if (no_new_pseudos) | |
23b2ce53 RS |
538 | abort (); |
539 | ||
fc84e8a8 RS |
540 | if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT |
541 | || GET_MODE_CLASS (mode) == MODE_COMPLEX_INT) | |
542 | { | |
543 | /* For complex modes, don't make a single pseudo. | |
544 | Instead, make a CONCAT of two pseudos. | |
545 | This allows noncontiguous allocation of the real and imaginary parts, | |
546 | which makes much better code. Besides, allocating DCmode | |
547 | pseudos overstrains reload on some machines like the 386. */ | |
548 | rtx realpart, imagpart; | |
549 | int size = GET_MODE_UNIT_SIZE (mode); | |
550 | enum machine_mode partmode | |
551 | = mode_for_size (size * BITS_PER_UNIT, | |
552 | (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT | |
553 | ? MODE_FLOAT : MODE_INT), | |
554 | 0); | |
555 | ||
556 | realpart = gen_reg_rtx (partmode); | |
557 | imagpart = gen_reg_rtx (partmode); | |
3b80f6ca | 558 | return gen_rtx_CONCAT (mode, realpart, imagpart); |
fc84e8a8 RS |
559 | } |
560 | ||
23b2ce53 RS |
561 | /* Make sure regno_pointer_flag and regno_reg_rtx are large |
562 | enough to have an element for this pseudo reg number. */ | |
563 | ||
49ad7cfa | 564 | if (reg_rtx_no == f->emit->regno_pointer_flag_length) |
23b2ce53 | 565 | { |
49ad7cfa | 566 | int old_size = f->emit->regno_pointer_flag_length; |
23b2ce53 | 567 | rtx *new1; |
e2ecd91c BS |
568 | char *new; |
569 | new = xrealloc (f->emit->regno_pointer_flag, old_size * 2); | |
49ad7cfa BS |
570 | memset (new + old_size, 0, old_size); |
571 | f->emit->regno_pointer_flag = new; | |
572 | ||
e2ecd91c | 573 | new = xrealloc (f->emit->regno_pointer_align, old_size * 2); |
49ad7cfa BS |
574 | memset (new + old_size, 0, old_size); |
575 | f->emit->regno_pointer_align = new; | |
576 | ||
e2ecd91c BS |
577 | new1 = (rtx *) xrealloc (f->emit->x_regno_reg_rtx, |
578 | old_size * 2 * sizeof (rtx)); | |
49ad7cfa | 579 | memset (new1 + old_size, 0, old_size * sizeof (rtx)); |
23b2ce53 RS |
580 | regno_reg_rtx = new1; |
581 | ||
49ad7cfa | 582 | f->emit->regno_pointer_flag_length = old_size * 2; |
23b2ce53 RS |
583 | } |
584 | ||
3b80f6ca | 585 | val = gen_rtx_raw_REG (mode, reg_rtx_no); |
23b2ce53 RS |
586 | regno_reg_rtx[reg_rtx_no++] = val; |
587 | return val; | |
588 | } | |
589 | ||
754fdcca RK |
590 | /* Identify REG (which may be a CONCAT) as a user register. */ |
591 | ||
592 | void | |
593 | mark_user_reg (reg) | |
594 | rtx reg; | |
595 | { | |
596 | if (GET_CODE (reg) == CONCAT) | |
597 | { | |
598 | REG_USERVAR_P (XEXP (reg, 0)) = 1; | |
599 | REG_USERVAR_P (XEXP (reg, 1)) = 1; | |
600 | } | |
601 | else if (GET_CODE (reg) == REG) | |
602 | REG_USERVAR_P (reg) = 1; | |
603 | else | |
604 | abort (); | |
605 | } | |
606 | ||
86fe05e0 RK |
607 | /* Identify REG as a probable pointer register and show its alignment |
608 | as ALIGN, if nonzero. */ | |
23b2ce53 RS |
609 | |
610 | void | |
86fe05e0 | 611 | mark_reg_pointer (reg, align) |
23b2ce53 | 612 | rtx reg; |
86fe05e0 | 613 | int align; |
23b2ce53 | 614 | { |
00995e78 RE |
615 | if (! REGNO_POINTER_FLAG (REGNO (reg))) |
616 | { | |
617 | REGNO_POINTER_FLAG (REGNO (reg)) = 1; | |
86fe05e0 | 618 | |
00995e78 RE |
619 | if (align) |
620 | REGNO_POINTER_ALIGN (REGNO (reg)) = align; | |
621 | } | |
622 | else if (align && align < REGNO_POINTER_ALIGN (REGNO (reg))) | |
623 | /* We can no-longer be sure just how aligned this pointer is */ | |
86fe05e0 | 624 | REGNO_POINTER_ALIGN (REGNO (reg)) = align; |
23b2ce53 RS |
625 | } |
626 | ||
627 | /* Return 1 plus largest pseudo reg number used in the current function. */ | |
628 | ||
629 | int | |
630 | max_reg_num () | |
631 | { | |
632 | return reg_rtx_no; | |
633 | } | |
634 | ||
635 | /* Return 1 + the largest label number used so far in the current function. */ | |
636 | ||
637 | int | |
638 | max_label_num () | |
639 | { | |
640 | if (last_label_num && label_num == base_label_num) | |
641 | return last_label_num; | |
642 | return label_num; | |
643 | } | |
644 | ||
645 | /* Return first label number used in this function (if any were used). */ | |
646 | ||
647 | int | |
648 | get_first_label_num () | |
649 | { | |
650 | return first_label_num; | |
651 | } | |
652 | \f | |
653 | /* Return a value representing some low-order bits of X, where the number | |
654 | of low-order bits is given by MODE. Note that no conversion is done | |
655 | between floating-point and fixed-point values, rather, the bit | |
656 | representation is returned. | |
657 | ||
658 | This function handles the cases in common between gen_lowpart, below, | |
659 | and two variants in cse.c and combine.c. These are the cases that can | |
660 | be safely handled at all points in the compilation. | |
661 | ||
662 | If this is not a case we can handle, return 0. */ | |
663 | ||
664 | rtx | |
665 | gen_lowpart_common (mode, x) | |
666 | enum machine_mode mode; | |
667 | register rtx x; | |
668 | { | |
669 | int word = 0; | |
670 | ||
671 | if (GET_MODE (x) == mode) | |
672 | return x; | |
673 | ||
674 | /* MODE must occupy no more words than the mode of X. */ | |
675 | if (GET_MODE (x) != VOIDmode | |
676 | && ((GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD | |
677 | > ((GET_MODE_SIZE (GET_MODE (x)) + (UNITS_PER_WORD - 1)) | |
678 | / UNITS_PER_WORD))) | |
679 | return 0; | |
680 | ||
681 | if (WORDS_BIG_ENDIAN && GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD) | |
682 | word = ((GET_MODE_SIZE (GET_MODE (x)) | |
683 | - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD)) | |
684 | / UNITS_PER_WORD); | |
685 | ||
686 | if ((GET_CODE (x) == ZERO_EXTEND || GET_CODE (x) == SIGN_EXTEND) | |
83e9c679 RK |
687 | && (GET_MODE_CLASS (mode) == MODE_INT |
688 | || GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)) | |
23b2ce53 RS |
689 | { |
690 | /* If we are getting the low-order part of something that has been | |
691 | sign- or zero-extended, we can either just use the object being | |
692 | extended or make a narrower extension. If we want an even smaller | |
693 | piece than the size of the object being extended, call ourselves | |
694 | recursively. | |
695 | ||
696 | This case is used mostly by combine and cse. */ | |
697 | ||
698 | if (GET_MODE (XEXP (x, 0)) == mode) | |
699 | return XEXP (x, 0); | |
700 | else if (GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (XEXP (x, 0)))) | |
701 | return gen_lowpart_common (mode, XEXP (x, 0)); | |
702 | else if (GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (x))) | |
3b80f6ca | 703 | return gen_rtx_fmt_e (GET_CODE (x), mode, XEXP (x, 0)); |
23b2ce53 RS |
704 | } |
705 | else if (GET_CODE (x) == SUBREG | |
706 | && (GET_MODE_SIZE (mode) <= UNITS_PER_WORD | |
707 | || GET_MODE_SIZE (mode) == GET_MODE_UNIT_SIZE (GET_MODE (x)))) | |
708 | return (GET_MODE (SUBREG_REG (x)) == mode && SUBREG_WORD (x) == 0 | |
709 | ? SUBREG_REG (x) | |
3b80f6ca | 710 | : gen_rtx_SUBREG (mode, SUBREG_REG (x), SUBREG_WORD (x) + word)); |
23b2ce53 RS |
711 | else if (GET_CODE (x) == REG) |
712 | { | |
4901a643 RH |
713 | /* Let the backend decide how many registers to skip. This is needed |
714 | in particular for Sparc64 where fp regs are smaller than a word. */ | |
715 | /* ??? Note that subregs are now ambiguous, in that those against | |
716 | pseudos are sized by the Word Size, while those against hard | |
717 | regs are sized by the underlying register size. Better would be | |
718 | to always interpret the subreg offset parameter as bytes or bits. */ | |
719 | ||
720 | if (WORDS_BIG_ENDIAN && REGNO (x) < FIRST_PSEUDO_REGISTER) | |
721 | word = (HARD_REGNO_NREGS (REGNO (x), GET_MODE (x)) | |
722 | - HARD_REGNO_NREGS (REGNO (x), mode)); | |
723 | ||
23b2ce53 | 724 | /* If the register is not valid for MODE, return 0. If we don't |
674d5d8b RK |
725 | do this, there is no way to fix up the resulting REG later. |
726 | But we do do this if the current REG is not valid for its | |
727 | mode. This latter is a kludge, but is required due to the | |
728 | way that parameters are passed on some machines, most | |
729 | notably Sparc. */ | |
23b2ce53 | 730 | if (REGNO (x) < FIRST_PSEUDO_REGISTER |
674d5d8b RK |
731 | && ! HARD_REGNO_MODE_OK (REGNO (x) + word, mode) |
732 | && HARD_REGNO_MODE_OK (REGNO (x), GET_MODE (x))) | |
23b2ce53 RS |
733 | return 0; |
734 | else if (REGNO (x) < FIRST_PSEUDO_REGISTER | |
735 | /* integrate.c can't handle parts of a return value register. */ | |
736 | && (! REG_FUNCTION_VALUE_P (x) | |
cb00f51a | 737 | || ! rtx_equal_function_value_matters) |
aff48bca JL |
738 | #ifdef CLASS_CANNOT_CHANGE_SIZE |
739 | && ! (GET_MODE_SIZE (mode) != GET_MODE_SIZE (GET_MODE (x)) | |
740 | && GET_MODE_CLASS (GET_MODE (x)) != MODE_COMPLEX_INT | |
741 | && GET_MODE_CLASS (GET_MODE (x)) != MODE_COMPLEX_FLOAT | |
742 | && (TEST_HARD_REG_BIT | |
743 | (reg_class_contents[(int) CLASS_CANNOT_CHANGE_SIZE], | |
744 | REGNO (x)))) | |
745 | #endif | |
cb00f51a RK |
746 | /* We want to keep the stack, frame, and arg pointers |
747 | special. */ | |
65e8fe02 | 748 | && x != frame_pointer_rtx |
cb00f51a | 749 | #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM |
65e8fe02 | 750 | && x != arg_pointer_rtx |
cb00f51a | 751 | #endif |
65e8fe02 | 752 | && x != stack_pointer_rtx) |
3b80f6ca | 753 | return gen_rtx_REG (mode, REGNO (x) + word); |
23b2ce53 | 754 | else |
3b80f6ca | 755 | return gen_rtx_SUBREG (mode, x, word); |
23b2ce53 | 756 | } |
23b2ce53 RS |
757 | /* If X is a CONST_INT or a CONST_DOUBLE, extract the appropriate bits |
758 | from the low-order part of the constant. */ | |
83e9c679 RK |
759 | else if ((GET_MODE_CLASS (mode) == MODE_INT |
760 | || GET_MODE_CLASS (mode) == MODE_PARTIAL_INT) | |
761 | && GET_MODE (x) == VOIDmode | |
23b2ce53 | 762 | && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE)) |
1a5b457d RK |
763 | { |
764 | /* If MODE is twice the host word size, X is already the desired | |
765 | representation. Otherwise, if MODE is wider than a word, we can't | |
766 | do this. If MODE is exactly a word, return just one CONST_INT. | |
767 | If MODE is smaller than a word, clear the bits that don't belong | |
768 | in our mode, unless they and our sign bit are all one. So we get | |
769 | either a reasonable negative value or a reasonable unsigned value | |
770 | for this mode. */ | |
771 | ||
a8dd0e73 | 772 | if (GET_MODE_BITSIZE (mode) >= 2 * HOST_BITS_PER_WIDE_INT) |
1a5b457d | 773 | return x; |
906c4e36 | 774 | else if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT) |
1a5b457d | 775 | return 0; |
906c4e36 | 776 | else if (GET_MODE_BITSIZE (mode) == HOST_BITS_PER_WIDE_INT) |
1a5b457d | 777 | return (GET_CODE (x) == CONST_INT ? x |
906c4e36 | 778 | : GEN_INT (CONST_DOUBLE_LOW (x))); |
1a5b457d RK |
779 | else |
780 | { | |
27eef9ce | 781 | /* MODE must be narrower than HOST_BITS_PER_WIDE_INT. */ |
1a5b457d | 782 | int width = GET_MODE_BITSIZE (mode); |
906c4e36 RK |
783 | HOST_WIDE_INT val = (GET_CODE (x) == CONST_INT ? INTVAL (x) |
784 | : CONST_DOUBLE_LOW (x)); | |
1a5b457d | 785 | |
27eef9ce JC |
786 | /* Sign extend to HOST_WIDE_INT. */ |
787 | val = val << (HOST_BITS_PER_WIDE_INT - width) >> (HOST_BITS_PER_WIDE_INT - width); | |
1a5b457d RK |
788 | |
789 | return (GET_CODE (x) == CONST_INT && INTVAL (x) == val ? x | |
906c4e36 | 790 | : GEN_INT (val)); |
1a5b457d RK |
791 | } |
792 | } | |
23b2ce53 | 793 | |
8aada4ad RK |
794 | /* If X is an integral constant but we want it in floating-point, it |
795 | must be the case that we have a union of an integer and a floating-point | |
796 | value. If the machine-parameters allow it, simulate that union here | |
d6020413 RK |
797 | and return the result. The two-word and single-word cases are |
798 | different. */ | |
8aada4ad | 799 | |
b3bf132d | 800 | else if (((HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT |
906c4e36 | 801 | && HOST_BITS_PER_WIDE_INT == BITS_PER_WORD) |
b3bf132d | 802 | || flag_pretend_float) |
8aada4ad | 803 | && GET_MODE_CLASS (mode) == MODE_FLOAT |
d6020413 RK |
804 | && GET_MODE_SIZE (mode) == UNITS_PER_WORD |
805 | && GET_CODE (x) == CONST_INT | |
906c4e36 | 806 | && sizeof (float) * HOST_BITS_PER_CHAR == HOST_BITS_PER_WIDE_INT) |
b6a524cb RS |
807 | #ifdef REAL_ARITHMETIC |
808 | { | |
809 | REAL_VALUE_TYPE r; | |
810 | HOST_WIDE_INT i; | |
811 | ||
812 | i = INTVAL (x); | |
813 | r = REAL_VALUE_FROM_TARGET_SINGLE (i); | |
53596fba | 814 | return CONST_DOUBLE_FROM_REAL_VALUE (r, mode); |
b6a524cb RS |
815 | } |
816 | #else | |
d6020413 | 817 | { |
906c4e36 | 818 | union {HOST_WIDE_INT i; float d; } u; |
d6020413 RK |
819 | |
820 | u.i = INTVAL (x); | |
53596fba | 821 | return CONST_DOUBLE_FROM_REAL_VALUE (u.d, mode); |
d6020413 | 822 | } |
b6a524cb | 823 | #endif |
d6020413 | 824 | else if (((HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT |
906c4e36 | 825 | && HOST_BITS_PER_WIDE_INT == BITS_PER_WORD) |
d6020413 RK |
826 | || flag_pretend_float) |
827 | && GET_MODE_CLASS (mode) == MODE_FLOAT | |
828 | && GET_MODE_SIZE (mode) == 2 * UNITS_PER_WORD | |
8aada4ad RK |
829 | && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE) |
830 | && GET_MODE (x) == VOIDmode | |
906c4e36 RK |
831 | && (sizeof (double) * HOST_BITS_PER_CHAR |
832 | == 2 * HOST_BITS_PER_WIDE_INT)) | |
b6a524cb RS |
833 | #ifdef REAL_ARITHMETIC |
834 | { | |
835 | REAL_VALUE_TYPE r; | |
836 | HOST_WIDE_INT i[2]; | |
837 | HOST_WIDE_INT low, high; | |
838 | ||
839 | if (GET_CODE (x) == CONST_INT) | |
840 | low = INTVAL (x), high = low >> (HOST_BITS_PER_WIDE_INT -1); | |
841 | else | |
842 | low = CONST_DOUBLE_LOW (x), high = CONST_DOUBLE_HIGH (x); | |
843 | ||
8698cce3 | 844 | /* REAL_VALUE_TARGET_DOUBLE takes the addressing order of the |
0f41302f | 845 | target machine. */ |
8698cce3 RK |
846 | if (WORDS_BIG_ENDIAN) |
847 | i[0] = high, i[1] = low; | |
848 | else | |
849 | i[0] = low, i[1] = high; | |
b6a524cb RS |
850 | |
851 | r = REAL_VALUE_FROM_TARGET_DOUBLE (i); | |
53596fba | 852 | return CONST_DOUBLE_FROM_REAL_VALUE (r, mode); |
b6a524cb RS |
853 | } |
854 | #else | |
8aada4ad | 855 | { |
906c4e36 RK |
856 | union {HOST_WIDE_INT i[2]; double d; } u; |
857 | HOST_WIDE_INT low, high; | |
8aada4ad RK |
858 | |
859 | if (GET_CODE (x) == CONST_INT) | |
906c4e36 | 860 | low = INTVAL (x), high = low >> (HOST_BITS_PER_WIDE_INT -1); |
8aada4ad RK |
861 | else |
862 | low = CONST_DOUBLE_LOW (x), high = CONST_DOUBLE_HIGH (x); | |
863 | ||
864 | #ifdef HOST_WORDS_BIG_ENDIAN | |
865 | u.i[0] = high, u.i[1] = low; | |
866 | #else | |
867 | u.i[0] = low, u.i[1] = high; | |
868 | #endif | |
869 | ||
53596fba | 870 | return CONST_DOUBLE_FROM_REAL_VALUE (u.d, mode); |
8aada4ad | 871 | } |
b6a524cb | 872 | #endif |
a6a503ed JW |
873 | |
874 | /* We need an extra case for machines where HOST_BITS_PER_WIDE_INT is the | |
4926b75a JL |
875 | same as sizeof (double) or when sizeof (float) is larger than the |
876 | size of a word on the target machine. */ | |
a6a503ed | 877 | #ifdef REAL_ARITHMETIC |
4926b75a | 878 | else if (mode == SFmode && GET_CODE (x) == CONST_INT) |
a6a503ed JW |
879 | { |
880 | REAL_VALUE_TYPE r; | |
881 | HOST_WIDE_INT i; | |
882 | ||
883 | i = INTVAL (x); | |
884 | r = REAL_VALUE_FROM_TARGET_SINGLE (i); | |
885 | return CONST_DOUBLE_FROM_REAL_VALUE (r, mode); | |
886 | } | |
8fc4af0f JJ |
887 | else if (((HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT |
888 | && HOST_BITS_PER_WIDE_INT == BITS_PER_WORD) | |
889 | || flag_pretend_float) | |
890 | && GET_MODE_CLASS (mode) == MODE_FLOAT | |
891 | && GET_MODE_SIZE (mode) == UNITS_PER_WORD | |
892 | && GET_CODE (x) == CONST_INT | |
893 | && (sizeof (double) * HOST_BITS_PER_CHAR | |
894 | == HOST_BITS_PER_WIDE_INT)) | |
895 | { | |
896 | REAL_VALUE_TYPE r; | |
897 | HOST_WIDE_INT i; | |
898 | ||
899 | i = INTVAL (x); | |
900 | r = REAL_VALUE_FROM_TARGET_DOUBLE (&i); | |
901 | return CONST_DOUBLE_FROM_REAL_VALUE (r, mode); | |
902 | } | |
a6a503ed JW |
903 | #endif |
904 | ||
b3bf132d RK |
905 | /* Similarly, if this is converting a floating-point value into a |
906 | single-word integer. Only do this is the host and target parameters are | |
907 | compatible. */ | |
908 | ||
909 | else if (((HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT | |
906c4e36 | 910 | && HOST_BITS_PER_WIDE_INT == BITS_PER_WORD) |
b3bf132d | 911 | || flag_pretend_float) |
83e9c679 RK |
912 | && (GET_MODE_CLASS (mode) == MODE_INT |
913 | || GET_MODE_CLASS (mode) == MODE_PARTIAL_INT) | |
b3bf132d RK |
914 | && GET_CODE (x) == CONST_DOUBLE |
915 | && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT | |
916 | && GET_MODE_BITSIZE (mode) == BITS_PER_WORD) | |
a80586cc | 917 | return operand_subword (x, word, 0, GET_MODE (x)); |
b3bf132d | 918 | |
8aada4ad RK |
919 | /* Similarly, if this is converting a floating-point value into a |
920 | two-word integer, we can do this one word at a time and make an | |
921 | integer. Only do this is the host and target parameters are | |
922 | compatible. */ | |
923 | ||
b3bf132d | 924 | else if (((HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT |
906c4e36 | 925 | && HOST_BITS_PER_WIDE_INT == BITS_PER_WORD) |
b3bf132d | 926 | || flag_pretend_float) |
83e9c679 | 927 | && (GET_MODE_CLASS (mode) == MODE_INT |
f5a2fb25 | 928 | || GET_MODE_CLASS (mode) == MODE_PARTIAL_INT) |
8aada4ad RK |
929 | && GET_CODE (x) == CONST_DOUBLE |
930 | && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT | |
931 | && GET_MODE_BITSIZE (mode) == 2 * BITS_PER_WORD) | |
932 | { | |
a80586cc RK |
933 | rtx lowpart |
934 | = operand_subword (x, word + WORDS_BIG_ENDIAN, 0, GET_MODE (x)); | |
935 | rtx highpart | |
936 | = operand_subword (x, word + ! WORDS_BIG_ENDIAN, 0, GET_MODE (x)); | |
8aada4ad RK |
937 | |
938 | if (lowpart && GET_CODE (lowpart) == CONST_INT | |
939 | && highpart && GET_CODE (highpart) == CONST_INT) | |
940 | return immed_double_const (INTVAL (lowpart), INTVAL (highpart), mode); | |
941 | } | |
942 | ||
23b2ce53 RS |
943 | /* Otherwise, we can't do this. */ |
944 | return 0; | |
945 | } | |
946 | \f | |
280194b0 RS |
947 | /* Return the real part (which has mode MODE) of a complex value X. |
948 | This always comes at the low address in memory. */ | |
949 | ||
950 | rtx | |
951 | gen_realpart (mode, x) | |
952 | enum machine_mode mode; | |
953 | register rtx x; | |
954 | { | |
dc139c90 RK |
955 | if (GET_CODE (x) == CONCAT && GET_MODE (XEXP (x, 0)) == mode) |
956 | return XEXP (x, 0); | |
40c0c3cf JL |
957 | else if (WORDS_BIG_ENDIAN |
958 | && GET_MODE_BITSIZE (mode) < BITS_PER_WORD | |
959 | && REG_P (x) | |
960 | && REGNO (x) < FIRST_PSEUDO_REGISTER) | |
961 | fatal ("Unable to access real part of complex value in a hard register on this target"); | |
dc139c90 | 962 | else if (WORDS_BIG_ENDIAN) |
280194b0 RS |
963 | return gen_highpart (mode, x); |
964 | else | |
965 | return gen_lowpart (mode, x); | |
966 | } | |
967 | ||
968 | /* Return the imaginary part (which has mode MODE) of a complex value X. | |
969 | This always comes at the high address in memory. */ | |
970 | ||
971 | rtx | |
972 | gen_imagpart (mode, x) | |
973 | enum machine_mode mode; | |
974 | register rtx x; | |
975 | { | |
dc139c90 RK |
976 | if (GET_CODE (x) == CONCAT && GET_MODE (XEXP (x, 0)) == mode) |
977 | return XEXP (x, 1); | |
978 | else if (WORDS_BIG_ENDIAN) | |
280194b0 | 979 | return gen_lowpart (mode, x); |
40c0c3cf JL |
980 | else if (!WORDS_BIG_ENDIAN |
981 | && GET_MODE_BITSIZE (mode) < BITS_PER_WORD | |
982 | && REG_P (x) | |
983 | && REGNO (x) < FIRST_PSEUDO_REGISTER) | |
984 | fatal ("Unable to access imaginary part of complex value in a hard register on this target"); | |
280194b0 RS |
985 | else |
986 | return gen_highpart (mode, x); | |
987 | } | |
81284a6a JW |
988 | |
989 | /* Return 1 iff X, assumed to be a SUBREG, | |
990 | refers to the real part of the complex value in its containing reg. | |
991 | Complex values are always stored with the real part in the first word, | |
992 | regardless of WORDS_BIG_ENDIAN. */ | |
993 | ||
994 | int | |
995 | subreg_realpart_p (x) | |
996 | rtx x; | |
997 | { | |
998 | if (GET_CODE (x) != SUBREG) | |
999 | abort (); | |
1000 | ||
770ae6cc RK |
1001 | return ((unsigned int) SUBREG_WORD (x) * UNITS_PER_WORD |
1002 | < GET_MODE_UNIT_SIZE (GET_MODE (SUBREG_REG (x)))); | |
81284a6a | 1003 | } |
280194b0 | 1004 | \f |
23b2ce53 RS |
1005 | /* Assuming that X is an rtx (e.g., MEM, REG or SUBREG) for a value, |
1006 | return an rtx (MEM, SUBREG, or CONST_INT) that refers to the | |
1007 | least-significant part of X. | |
1008 | MODE specifies how big a part of X to return; | |
1009 | it usually should not be larger than a word. | |
1010 | If X is a MEM whose address is a QUEUED, the value may be so also. */ | |
1011 | ||
1012 | rtx | |
1013 | gen_lowpart (mode, x) | |
1014 | enum machine_mode mode; | |
1015 | register rtx x; | |
1016 | { | |
1017 | rtx result = gen_lowpart_common (mode, x); | |
1018 | ||
1019 | if (result) | |
1020 | return result; | |
ea8262b0 RK |
1021 | else if (GET_CODE (x) == REG) |
1022 | { | |
1023 | /* Must be a hard reg that's not valid in MODE. */ | |
1024 | result = gen_lowpart_common (mode, copy_to_reg (x)); | |
1025 | if (result == 0) | |
1026 | abort (); | |
72c3833b | 1027 | return result; |
ea8262b0 | 1028 | } |
23b2ce53 RS |
1029 | else if (GET_CODE (x) == MEM) |
1030 | { | |
1031 | /* The only additional case we can do is MEM. */ | |
1032 | register int offset = 0; | |
1033 | if (WORDS_BIG_ENDIAN) | |
1034 | offset = (MAX (GET_MODE_SIZE (GET_MODE (x)), UNITS_PER_WORD) | |
1035 | - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD)); | |
1036 | ||
1037 | if (BYTES_BIG_ENDIAN) | |
1038 | /* Adjust the address so that the address-after-the-data | |
1039 | is unchanged. */ | |
1040 | offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode)) | |
1041 | - MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (x)))); | |
1042 | ||
1043 | return change_address (x, mode, plus_constant (XEXP (x, 0), offset)); | |
1044 | } | |
e9a25f70 JL |
1045 | else if (GET_CODE (x) == ADDRESSOF) |
1046 | return gen_lowpart (mode, force_reg (GET_MODE (x), x)); | |
23b2ce53 RS |
1047 | else |
1048 | abort (); | |
1049 | } | |
1050 | ||
ccba022b RS |
1051 | /* Like `gen_lowpart', but refer to the most significant part. |
1052 | This is used to access the imaginary part of a complex number. */ | |
1053 | ||
1054 | rtx | |
1055 | gen_highpart (mode, x) | |
1056 | enum machine_mode mode; | |
1057 | register rtx x; | |
1058 | { | |
1059 | /* This case loses if X is a subreg. To catch bugs early, | |
1060 | complain if an invalid MODE is used even in other cases. */ | |
1061 | if (GET_MODE_SIZE (mode) > UNITS_PER_WORD | |
1062 | && GET_MODE_SIZE (mode) != GET_MODE_UNIT_SIZE (GET_MODE (x))) | |
1063 | abort (); | |
1064 | if (GET_CODE (x) == CONST_DOUBLE | |
1632afca | 1065 | #if !(TARGET_FLOAT_FORMAT != HOST_FLOAT_FORMAT || defined (REAL_IS_NOT_DOUBLE)) |
ccba022b RS |
1066 | && GET_MODE_CLASS (GET_MODE (x)) != MODE_FLOAT |
1067 | #endif | |
1068 | ) | |
3b80f6ca | 1069 | return GEN_INT (CONST_DOUBLE_HIGH (x) & GET_MODE_MASK (mode)); |
ccba022b | 1070 | else if (GET_CODE (x) == CONST_INT) |
27eef9ce JC |
1071 | { |
1072 | if (HOST_BITS_PER_WIDE_INT <= BITS_PER_WORD) | |
1073 | return const0_rtx; | |
1074 | return GEN_INT (INTVAL (x) >> (HOST_BITS_PER_WIDE_INT - BITS_PER_WORD)); | |
1075 | } | |
ccba022b RS |
1076 | else if (GET_CODE (x) == MEM) |
1077 | { | |
1078 | register int offset = 0; | |
8698cce3 RK |
1079 | if (! WORDS_BIG_ENDIAN) |
1080 | offset = (MAX (GET_MODE_SIZE (GET_MODE (x)), UNITS_PER_WORD) | |
1081 | - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD)); | |
1082 | ||
1083 | if (! BYTES_BIG_ENDIAN | |
1084 | && GET_MODE_SIZE (mode) < UNITS_PER_WORD) | |
ccba022b RS |
1085 | offset -= (GET_MODE_SIZE (mode) |
1086 | - MIN (UNITS_PER_WORD, | |
1087 | GET_MODE_SIZE (GET_MODE (x)))); | |
8698cce3 | 1088 | |
ccba022b RS |
1089 | return change_address (x, mode, plus_constant (XEXP (x, 0), offset)); |
1090 | } | |
1091 | else if (GET_CODE (x) == SUBREG) | |
1092 | { | |
1093 | /* The only time this should occur is when we are looking at a | |
1094 | multi-word item with a SUBREG whose mode is the same as that of the | |
1095 | item. It isn't clear what we would do if it wasn't. */ | |
1096 | if (SUBREG_WORD (x) != 0) | |
1097 | abort (); | |
1098 | return gen_highpart (mode, SUBREG_REG (x)); | |
1099 | } | |
1100 | else if (GET_CODE (x) == REG) | |
1101 | { | |
6cca74ab | 1102 | int word; |
ccba022b | 1103 | |
4901a643 RH |
1104 | /* Let the backend decide how many registers to skip. This is needed |
1105 | in particular for sparc64 where fp regs are smaller than a word. */ | |
1106 | /* ??? Note that subregs are now ambiguous, in that those against | |
6cca74ab | 1107 | pseudos are sized by the word size, while those against hard |
4901a643 RH |
1108 | regs are sized by the underlying register size. Better would be |
1109 | to always interpret the subreg offset parameter as bytes or bits. */ | |
1110 | ||
6cca74ab GM |
1111 | if (WORDS_BIG_ENDIAN) |
1112 | word = 0; | |
1113 | else if (REGNO (x) < FIRST_PSEUDO_REGISTER) | |
4901a643 RH |
1114 | word = (HARD_REGNO_NREGS (REGNO (x), GET_MODE (x)) |
1115 | - HARD_REGNO_NREGS (REGNO (x), mode)); | |
6cca74ab GM |
1116 | else |
1117 | word = ((GET_MODE_SIZE (GET_MODE (x)) | |
1118 | - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD)) | |
1119 | / UNITS_PER_WORD); | |
3e4a14ef | 1120 | |
cb00f51a | 1121 | if (REGNO (x) < FIRST_PSEUDO_REGISTER |
0f41302f | 1122 | /* integrate.c can't handle parts of a return value register. */ |
4badc528 RS |
1123 | && (! REG_FUNCTION_VALUE_P (x) |
1124 | || ! rtx_equal_function_value_matters) | |
cb00f51a | 1125 | /* We want to keep the stack, frame, and arg pointers special. */ |
65e8fe02 | 1126 | && x != frame_pointer_rtx |
cb00f51a | 1127 | #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM |
65e8fe02 | 1128 | && x != arg_pointer_rtx |
cb00f51a | 1129 | #endif |
65e8fe02 | 1130 | && x != stack_pointer_rtx) |
3b80f6ca | 1131 | return gen_rtx_REG (mode, REGNO (x) + word); |
ccba022b | 1132 | else |
3b80f6ca | 1133 | return gen_rtx_SUBREG (mode, x, word); |
ccba022b RS |
1134 | } |
1135 | else | |
1136 | abort (); | |
1137 | } | |
1138 | ||
23b2ce53 RS |
1139 | /* Return 1 iff X, assumed to be a SUBREG, |
1140 | refers to the least significant part of its containing reg. | |
1141 | If X is not a SUBREG, always return 1 (it is its own low part!). */ | |
1142 | ||
1143 | int | |
1144 | subreg_lowpart_p (x) | |
1145 | rtx x; | |
1146 | { | |
1147 | if (GET_CODE (x) != SUBREG) | |
1148 | return 1; | |
a3a03040 RK |
1149 | else if (GET_MODE (SUBREG_REG (x)) == VOIDmode) |
1150 | return 0; | |
23b2ce53 RS |
1151 | |
1152 | if (WORDS_BIG_ENDIAN | |
1153 | && GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))) > UNITS_PER_WORD) | |
1154 | return (SUBREG_WORD (x) | |
1155 | == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))) | |
1156 | - MAX (GET_MODE_SIZE (GET_MODE (x)), UNITS_PER_WORD)) | |
1157 | / UNITS_PER_WORD)); | |
1158 | ||
1159 | return SUBREG_WORD (x) == 0; | |
1160 | } | |
1161 | \f | |
1162 | /* Return subword I of operand OP. | |
1163 | The word number, I, is interpreted as the word number starting at the | |
1164 | low-order address. Word 0 is the low-order word if not WORDS_BIG_ENDIAN, | |
1165 | otherwise it is the high-order word. | |
1166 | ||
1167 | If we cannot extract the required word, we return zero. Otherwise, an | |
1168 | rtx corresponding to the requested word will be returned. | |
1169 | ||
1170 | VALIDATE_ADDRESS is nonzero if the address should be validated. Before | |
1171 | reload has completed, a valid address will always be returned. After | |
1172 | reload, if a valid address cannot be returned, we return zero. | |
1173 | ||
1174 | If VALIDATE_ADDRESS is zero, we simply form the required address; validating | |
1175 | it is the responsibility of the caller. | |
1176 | ||
1177 | MODE is the mode of OP in case it is a CONST_INT. */ | |
1178 | ||
1179 | rtx | |
1180 | operand_subword (op, i, validate_address, mode) | |
1181 | rtx op; | |
770ae6cc | 1182 | unsigned int i; |
23b2ce53 RS |
1183 | int validate_address; |
1184 | enum machine_mode mode; | |
1185 | { | |
906c4e36 RK |
1186 | HOST_WIDE_INT val; |
1187 | int size_ratio = HOST_BITS_PER_WIDE_INT / BITS_PER_WORD; | |
23b2ce53 RS |
1188 | |
1189 | if (mode == VOIDmode) | |
1190 | mode = GET_MODE (op); | |
1191 | ||
1192 | if (mode == VOIDmode) | |
1193 | abort (); | |
1194 | ||
0003feb2 | 1195 | /* If OP is narrower than a word, fail. */ |
23b2ce53 | 1196 | if (mode != BLKmode |
0003feb2 | 1197 | && (GET_MODE_SIZE (mode) < UNITS_PER_WORD)) |
23b2ce53 | 1198 | return 0; |
0003feb2 VM |
1199 | |
1200 | /* If we want a word outside OP, return zero. */ | |
1201 | if (mode != BLKmode | |
1202 | && (i + 1) * UNITS_PER_WORD > GET_MODE_SIZE (mode)) | |
1203 | return const0_rtx; | |
23b2ce53 RS |
1204 | |
1205 | /* If OP is already an integer word, return it. */ | |
1206 | if (GET_MODE_CLASS (mode) == MODE_INT | |
1207 | && GET_MODE_SIZE (mode) == UNITS_PER_WORD) | |
1208 | return op; | |
1209 | ||
1210 | /* If OP is a REG or SUBREG, we can handle it very simply. */ | |
1211 | if (GET_CODE (op) == REG) | |
1212 | { | |
227d6ce0 JL |
1213 | /* ??? There is a potential problem with this code. It does not |
1214 | properly handle extractions of a subword from a hard register | |
1215 | that is larger than word_mode. Presumably the check for | |
1216 | HARD_REGNO_MODE_OK catches these most of these cases. */ | |
1217 | ||
1218 | /* If OP is a hard register, but OP + I is not a hard register, | |
1219 | then extracting a subword is impossible. | |
1220 | ||
1221 | For example, consider if OP is the last hard register and it is | |
1222 | larger than word_mode. If we wanted word N (for N > 0) because a | |
1223 | part of that hard register was known to contain a useful value, | |
1224 | then OP + I would refer to a pseudo, not the hard register we | |
1225 | actually wanted. */ | |
1226 | if (REGNO (op) < FIRST_PSEUDO_REGISTER | |
1227 | && REGNO (op) + i >= FIRST_PSEUDO_REGISTER) | |
1228 | return 0; | |
1229 | ||
1230 | /* If the register is not valid for MODE, return 0. Note we | |
1231 | have to check both OP and OP + I since they may refer to | |
1232 | different parts of the register file. | |
1233 | ||
1234 | Consider if OP refers to the last 96bit FP register and we want | |
1235 | subword 3 because that subword is known to contain a value we | |
1236 | needed. */ | |
23b2ce53 | 1237 | if (REGNO (op) < FIRST_PSEUDO_REGISTER |
227d6ce0 JL |
1238 | && (! HARD_REGNO_MODE_OK (REGNO (op), word_mode) |
1239 | || ! HARD_REGNO_MODE_OK (REGNO (op) + i, word_mode))) | |
23b2ce53 RS |
1240 | return 0; |
1241 | else if (REGNO (op) >= FIRST_PSEUDO_REGISTER | |
1242 | || (REG_FUNCTION_VALUE_P (op) | |
cb00f51a RK |
1243 | && rtx_equal_function_value_matters) |
1244 | /* We want to keep the stack, frame, and arg pointers | |
1245 | special. */ | |
65e8fe02 | 1246 | || op == frame_pointer_rtx |
cb00f51a | 1247 | #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM |
65e8fe02 | 1248 | || op == arg_pointer_rtx |
cb00f51a | 1249 | #endif |
65e8fe02 | 1250 | || op == stack_pointer_rtx) |
3b80f6ca | 1251 | return gen_rtx_SUBREG (word_mode, op, i); |
23b2ce53 | 1252 | else |
3b80f6ca | 1253 | return gen_rtx_REG (word_mode, REGNO (op) + i); |
23b2ce53 RS |
1254 | } |
1255 | else if (GET_CODE (op) == SUBREG) | |
3b80f6ca | 1256 | return gen_rtx_SUBREG (word_mode, SUBREG_REG (op), i + SUBREG_WORD (op)); |
fc84e8a8 RS |
1257 | else if (GET_CODE (op) == CONCAT) |
1258 | { | |
770ae6cc RK |
1259 | unsigned int partwords |
1260 | = GET_MODE_UNIT_SIZE (GET_MODE (op)) / UNITS_PER_WORD; | |
1261 | ||
fc84e8a8 RS |
1262 | if (i < partwords) |
1263 | return operand_subword (XEXP (op, 0), i, validate_address, mode); | |
1264 | return operand_subword (XEXP (op, 1), i - partwords, | |
1265 | validate_address, mode); | |
1266 | } | |
23b2ce53 RS |
1267 | |
1268 | /* Form a new MEM at the requested address. */ | |
1269 | if (GET_CODE (op) == MEM) | |
1270 | { | |
1271 | rtx addr = plus_constant (XEXP (op, 0), i * UNITS_PER_WORD); | |
1272 | rtx new; | |
1273 | ||
1274 | if (validate_address) | |
1275 | { | |
1276 | if (reload_completed) | |
1277 | { | |
1278 | if (! strict_memory_address_p (word_mode, addr)) | |
1279 | return 0; | |
1280 | } | |
1281 | else | |
1282 | addr = memory_address (word_mode, addr); | |
1283 | } | |
1284 | ||
3b80f6ca | 1285 | new = gen_rtx_MEM (word_mode, addr); |
c6df88cb | 1286 | MEM_COPY_ATTRIBUTES (new, op); |
23b2ce53 RS |
1287 | return new; |
1288 | } | |
1289 | ||
1290 | /* The only remaining cases are when OP is a constant. If the host and | |
1291 | target floating formats are the same, handling two-word floating | |
7677ffa4 | 1292 | constants are easy. Note that REAL_VALUE_TO_TARGET_{SINGLE,DOUBLE} |
9847c2f6 RK |
1293 | are defined as returning one or two 32 bit values, respectively, |
1294 | and not values of BITS_PER_WORD bits. */ | |
1632afca | 1295 | #ifdef REAL_ARITHMETIC |
5495cc55 RH |
1296 | /* The output is some bits, the width of the target machine's word. |
1297 | A wider-word host can surely hold them in a CONST_INT. A narrower-word | |
1298 | host can't. */ | |
9847c2f6 | 1299 | if (HOST_BITS_PER_WIDE_INT >= BITS_PER_WORD |
1632afca | 1300 | && GET_MODE_CLASS (mode) == MODE_FLOAT |
7677ffa4 | 1301 | && GET_MODE_BITSIZE (mode) == 64 |
1632afca RS |
1302 | && GET_CODE (op) == CONST_DOUBLE) |
1303 | { | |
9847c2f6 | 1304 | long k[2]; |
1632afca RS |
1305 | REAL_VALUE_TYPE rv; |
1306 | ||
1307 | REAL_VALUE_FROM_CONST_DOUBLE (rv, op); | |
1308 | REAL_VALUE_TO_TARGET_DOUBLE (rv, k); | |
7677ffa4 | 1309 | |
9847c2f6 | 1310 | /* We handle 32-bit and >= 64-bit words here. Note that the order in |
7677ffa4 | 1311 | which the words are written depends on the word endianness. |
7677ffa4 | 1312 | ??? This is a potential portability problem and should |
7cae975e RH |
1313 | be fixed at some point. |
1314 | ||
1315 | We must excercise caution with the sign bit. By definition there | |
1316 | are 32 significant bits in K; there may be more in a HOST_WIDE_INT. | |
1317 | Consider a host with a 32-bit long and a 64-bit HOST_WIDE_INT. | |
1318 | So we explicitly mask and sign-extend as necessary. */ | |
9847c2f6 | 1319 | if (BITS_PER_WORD == 32) |
7cae975e RH |
1320 | { |
1321 | val = k[i]; | |
1322 | val = ((val & 0xffffffff) ^ 0x80000000) - 0x80000000; | |
1323 | return GEN_INT (val); | |
1324 | } | |
1325 | #if HOST_BITS_PER_WIDE_INT >= 64 | |
9847c2f6 | 1326 | else if (BITS_PER_WORD >= 64 && i == 0) |
7cae975e RH |
1327 | { |
1328 | val = k[! WORDS_BIG_ENDIAN]; | |
1329 | val = (((val & 0xffffffff) ^ 0x80000000) - 0x80000000) << 32; | |
1330 | val |= (HOST_WIDE_INT) k[WORDS_BIG_ENDIAN] & 0xffffffff; | |
1331 | return GEN_INT (val); | |
1332 | } | |
9847c2f6 | 1333 | #endif |
47b34d40 JW |
1334 | else if (BITS_PER_WORD == 16) |
1335 | { | |
7cae975e RH |
1336 | val = k[i >> 1]; |
1337 | if ((i & 1) == !WORDS_BIG_ENDIAN) | |
1338 | val >>= 16; | |
1339 | val &= 0xffff; | |
1340 | return GEN_INT (val); | |
47b34d40 | 1341 | } |
7677ffa4 RK |
1342 | else |
1343 | abort (); | |
1632afca | 1344 | } |
a5559dbc RE |
1345 | else if (HOST_BITS_PER_WIDE_INT >= BITS_PER_WORD |
1346 | && GET_MODE_CLASS (mode) == MODE_FLOAT | |
1347 | && GET_MODE_BITSIZE (mode) > 64 | |
1348 | && GET_CODE (op) == CONST_DOUBLE) | |
5495cc55 RH |
1349 | { |
1350 | long k[4]; | |
1351 | REAL_VALUE_TYPE rv; | |
a5559dbc | 1352 | |
5495cc55 RH |
1353 | REAL_VALUE_FROM_CONST_DOUBLE (rv, op); |
1354 | REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, k); | |
a5559dbc | 1355 | |
5495cc55 RH |
1356 | if (BITS_PER_WORD == 32) |
1357 | { | |
1358 | val = k[i]; | |
1359 | val = ((val & 0xffffffff) ^ 0x80000000) - 0x80000000; | |
1360 | return GEN_INT (val); | |
1361 | } | |
1362 | #if HOST_BITS_PER_WIDE_INT >= 64 | |
1363 | else if (BITS_PER_WORD >= 64 && i <= 1) | |
1364 | { | |
1365 | val = k[i*2 + ! WORDS_BIG_ENDIAN]; | |
1366 | val = (((val & 0xffffffff) ^ 0x80000000) - 0x80000000) << 32; | |
1367 | val |= (HOST_WIDE_INT) k[i*2 + WORDS_BIG_ENDIAN] & 0xffffffff; | |
1368 | return GEN_INT (val); | |
1369 | } | |
1370 | #endif | |
1371 | else | |
1372 | abort (); | |
1373 | } | |
1632afca | 1374 | #else /* no REAL_ARITHMETIC */ |
23b2ce53 | 1375 | if (((HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT |
906c4e36 | 1376 | && HOST_BITS_PER_WIDE_INT == BITS_PER_WORD) |
23b2ce53 RS |
1377 | || flag_pretend_float) |
1378 | && GET_MODE_CLASS (mode) == MODE_FLOAT | |
1379 | && GET_MODE_SIZE (mode) == 2 * UNITS_PER_WORD | |
1380 | && GET_CODE (op) == CONST_DOUBLE) | |
7529ac93 CH |
1381 | { |
1382 | /* The constant is stored in the host's word-ordering, | |
1383 | but we want to access it in the target's word-ordering. Some | |
1384 | compilers don't like a conditional inside macro args, so we have two | |
1385 | copies of the return. */ | |
2fe02d7e | 1386 | #ifdef HOST_WORDS_BIG_ENDIAN |
7529ac93 CH |
1387 | return GEN_INT (i == WORDS_BIG_ENDIAN |
1388 | ? CONST_DOUBLE_HIGH (op) : CONST_DOUBLE_LOW (op)); | |
2fe02d7e | 1389 | #else |
7529ac93 CH |
1390 | return GEN_INT (i != WORDS_BIG_ENDIAN |
1391 | ? CONST_DOUBLE_HIGH (op) : CONST_DOUBLE_LOW (op)); | |
2fe02d7e | 1392 | #endif |
7529ac93 | 1393 | } |
1632afca | 1394 | #endif /* no REAL_ARITHMETIC */ |
23b2ce53 RS |
1395 | |
1396 | /* Single word float is a little harder, since single- and double-word | |
1397 | values often do not have the same high-order bits. We have already | |
1398 | verified that we want the only defined word of the single-word value. */ | |
1632afca | 1399 | #ifdef REAL_ARITHMETIC |
9847c2f6 | 1400 | if (GET_MODE_CLASS (mode) == MODE_FLOAT |
7677ffa4 | 1401 | && GET_MODE_BITSIZE (mode) == 32 |
1632afca RS |
1402 | && GET_CODE (op) == CONST_DOUBLE) |
1403 | { | |
9847c2f6 | 1404 | long l; |
1632afca RS |
1405 | REAL_VALUE_TYPE rv; |
1406 | ||
1407 | REAL_VALUE_FROM_CONST_DOUBLE (rv, op); | |
1408 | REAL_VALUE_TO_TARGET_SINGLE (rv, l); | |
aa2ae679 | 1409 | |
7cae975e RH |
1410 | /* Sign extend from known 32-bit value to HOST_WIDE_INT. */ |
1411 | val = l; | |
1412 | val = ((val & 0xffffffff) ^ 0x80000000) - 0x80000000; | |
b5a3eb84 | 1413 | |
aa2ae679 JL |
1414 | if (BITS_PER_WORD == 16) |
1415 | { | |
7cae975e RH |
1416 | if ((i & 1) == !WORDS_BIG_ENDIAN) |
1417 | val >>= 16; | |
1418 | val &= 0xffff; | |
aa2ae679 | 1419 | } |
7cae975e RH |
1420 | |
1421 | return GEN_INT (val); | |
1632afca RS |
1422 | } |
1423 | #else | |
23b2ce53 | 1424 | if (((HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT |
906c4e36 | 1425 | && HOST_BITS_PER_WIDE_INT == BITS_PER_WORD) |
23b2ce53 | 1426 | || flag_pretend_float) |
e01a2cec | 1427 | && sizeof (float) * 8 == HOST_BITS_PER_WIDE_INT |
23b2ce53 RS |
1428 | && GET_MODE_CLASS (mode) == MODE_FLOAT |
1429 | && GET_MODE_SIZE (mode) == UNITS_PER_WORD | |
1430 | && GET_CODE (op) == CONST_DOUBLE) | |
1431 | { | |
1432 | double d; | |
906c4e36 | 1433 | union {float f; HOST_WIDE_INT i; } u; |
23b2ce53 RS |
1434 | |
1435 | REAL_VALUE_FROM_CONST_DOUBLE (d, op); | |
1436 | ||
1437 | u.f = d; | |
906c4e36 | 1438 | return GEN_INT (u.i); |
23b2ce53 | 1439 | } |
e01a2cec RK |
1440 | if (((HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT |
1441 | && HOST_BITS_PER_WIDE_INT == BITS_PER_WORD) | |
1442 | || flag_pretend_float) | |
1443 | && sizeof (double) * 8 == HOST_BITS_PER_WIDE_INT | |
1444 | && GET_MODE_CLASS (mode) == MODE_FLOAT | |
1445 | && GET_MODE_SIZE (mode) == UNITS_PER_WORD | |
1446 | && GET_CODE (op) == CONST_DOUBLE) | |
1447 | { | |
1448 | double d; | |
1449 | union {double d; HOST_WIDE_INT i; } u; | |
1450 | ||
1451 | REAL_VALUE_FROM_CONST_DOUBLE (d, op); | |
1452 | ||
1453 | u.d = d; | |
1454 | return GEN_INT (u.i); | |
1455 | } | |
1632afca | 1456 | #endif /* no REAL_ARITHMETIC */ |
23b2ce53 RS |
1457 | |
1458 | /* The only remaining cases that we can handle are integers. | |
1459 | Convert to proper endianness now since these cases need it. | |
1460 | At this point, i == 0 means the low-order word. | |
1461 | ||
2d4f57f8 RK |
1462 | We do not want to handle the case when BITS_PER_WORD <= HOST_BITS_PER_INT |
1463 | in general. However, if OP is (const_int 0), we can just return | |
1464 | it for any word. */ | |
1465 | ||
1466 | if (op == const0_rtx) | |
1467 | return op; | |
23b2ce53 RS |
1468 | |
1469 | if (GET_MODE_CLASS (mode) != MODE_INT | |
2d4f57f8 | 1470 | || (GET_CODE (op) != CONST_INT && GET_CODE (op) != CONST_DOUBLE) |
0cf214a0 | 1471 | || BITS_PER_WORD > HOST_BITS_PER_WIDE_INT) |
23b2ce53 RS |
1472 | return 0; |
1473 | ||
1474 | if (WORDS_BIG_ENDIAN) | |
1475 | i = GET_MODE_SIZE (mode) / UNITS_PER_WORD - 1 - i; | |
1476 | ||
1477 | /* Find out which word on the host machine this value is in and get | |
1478 | it from the constant. */ | |
1479 | val = (i / size_ratio == 0 | |
1480 | ? (GET_CODE (op) == CONST_INT ? INTVAL (op) : CONST_DOUBLE_LOW (op)) | |
1481 | : (GET_CODE (op) == CONST_INT | |
1482 | ? (INTVAL (op) < 0 ? ~0 : 0) : CONST_DOUBLE_HIGH (op))); | |
1483 | ||
3f518020 | 1484 | /* Get the value we want into the low bits of val. */ |
906c4e36 | 1485 | if (BITS_PER_WORD < HOST_BITS_PER_WIDE_INT) |
3f518020 JL |
1486 | val = ((val >> ((i % size_ratio) * BITS_PER_WORD))); |
1487 | ||
7e4ce834 | 1488 | val = trunc_int_for_mode (val, word_mode); |
23b2ce53 | 1489 | |
906c4e36 | 1490 | return GEN_INT (val); |
23b2ce53 RS |
1491 | } |
1492 | ||
1493 | /* Similar to `operand_subword', but never return 0. If we can't extract | |
1494 | the required subword, put OP into a register and try again. If that fails, | |
1495 | abort. We always validate the address in this case. It is not valid | |
1496 | to call this function after reload; it is mostly meant for RTL | |
1497 | generation. | |
1498 | ||
1499 | MODE is the mode of OP, in case it is CONST_INT. */ | |
1500 | ||
1501 | rtx | |
1502 | operand_subword_force (op, i, mode) | |
1503 | rtx op; | |
770ae6cc | 1504 | unsigned int i; |
23b2ce53 RS |
1505 | enum machine_mode mode; |
1506 | { | |
1507 | rtx result = operand_subword (op, i, 1, mode); | |
1508 | ||
1509 | if (result) | |
1510 | return result; | |
1511 | ||
1512 | if (mode != BLKmode && mode != VOIDmode) | |
77e6b0eb JC |
1513 | { |
1514 | /* If this is a register which can not be accessed by words, copy it | |
1515 | to a pseudo register. */ | |
1516 | if (GET_CODE (op) == REG) | |
1517 | op = copy_to_reg (op); | |
1518 | else | |
1519 | op = force_reg (mode, op); | |
1520 | } | |
23b2ce53 RS |
1521 | |
1522 | result = operand_subword (op, i, 1, mode); | |
1523 | if (result == 0) | |
1524 | abort (); | |
1525 | ||
1526 | return result; | |
1527 | } | |
1528 | \f | |
1529 | /* Given a compare instruction, swap the operands. | |
1530 | A test instruction is changed into a compare of 0 against the operand. */ | |
1531 | ||
1532 | void | |
1533 | reverse_comparison (insn) | |
1534 | rtx insn; | |
1535 | { | |
1536 | rtx body = PATTERN (insn); | |
1537 | rtx comp; | |
1538 | ||
1539 | if (GET_CODE (body) == SET) | |
1540 | comp = SET_SRC (body); | |
1541 | else | |
1542 | comp = SET_SRC (XVECEXP (body, 0, 0)); | |
1543 | ||
1544 | if (GET_CODE (comp) == COMPARE) | |
1545 | { | |
1546 | rtx op0 = XEXP (comp, 0); | |
1547 | rtx op1 = XEXP (comp, 1); | |
1548 | XEXP (comp, 0) = op1; | |
1549 | XEXP (comp, 1) = op0; | |
1550 | } | |
1551 | else | |
1552 | { | |
c5c76735 JL |
1553 | rtx new = gen_rtx_COMPARE (VOIDmode, |
1554 | CONST0_RTX (GET_MODE (comp)), comp); | |
23b2ce53 RS |
1555 | if (GET_CODE (body) == SET) |
1556 | SET_SRC (body) = new; | |
1557 | else | |
1558 | SET_SRC (XVECEXP (body, 0, 0)) = new; | |
1559 | } | |
1560 | } | |
1561 | \f | |
1562 | /* Return a memory reference like MEMREF, but with its mode changed | |
1563 | to MODE and its address changed to ADDR. | |
1564 | (VOIDmode means don't change the mode. | |
1565 | NULL for ADDR means don't change the address.) */ | |
1566 | ||
1567 | rtx | |
1568 | change_address (memref, mode, addr) | |
1569 | rtx memref; | |
1570 | enum machine_mode mode; | |
1571 | rtx addr; | |
1572 | { | |
1573 | rtx new; | |
1574 | ||
1575 | if (GET_CODE (memref) != MEM) | |
1576 | abort (); | |
1577 | if (mode == VOIDmode) | |
1578 | mode = GET_MODE (memref); | |
1579 | if (addr == 0) | |
1580 | addr = XEXP (memref, 0); | |
1581 | ||
1582 | /* If reload is in progress or has completed, ADDR must be valid. | |
1583 | Otherwise, we can call memory_address to make it valid. */ | |
1584 | if (reload_completed || reload_in_progress) | |
1585 | { | |
1586 | if (! memory_address_p (mode, addr)) | |
1587 | abort (); | |
1588 | } | |
1589 | else | |
1590 | addr = memory_address (mode, addr); | |
1591 | ||
9b04c6a8 RK |
1592 | if (rtx_equal_p (addr, XEXP (memref, 0)) && mode == GET_MODE (memref)) |
1593 | return memref; | |
1594 | ||
3b80f6ca | 1595 | new = gen_rtx_MEM (mode, addr); |
c6df88cb | 1596 | MEM_COPY_ATTRIBUTES (new, memref); |
23b2ce53 RS |
1597 | return new; |
1598 | } | |
1599 | \f | |
1600 | /* Return a newly created CODE_LABEL rtx with a unique label number. */ | |
1601 | ||
1602 | rtx | |
1603 | gen_label_rtx () | |
1604 | { | |
ca695ac9 JB |
1605 | register rtx label; |
1606 | ||
b93a436e | 1607 | label = gen_rtx_CODE_LABEL (VOIDmode, 0, NULL_RTX, |
8cd0faaf | 1608 | NULL_RTX, label_num++, NULL_PTR, NULL_PTR); |
ca695ac9 | 1609 | |
23b2ce53 | 1610 | LABEL_NUSES (label) = 0; |
8cd0faaf | 1611 | LABEL_ALTERNATE_NAME (label) = NULL; |
23b2ce53 RS |
1612 | return label; |
1613 | } | |
1614 | \f | |
1615 | /* For procedure integration. */ | |
1616 | ||
23b2ce53 | 1617 | /* Install new pointers to the first and last insns in the chain. |
86fe05e0 | 1618 | Also, set cur_insn_uid to one higher than the last in use. |
23b2ce53 RS |
1619 | Used for an inline-procedure after copying the insn chain. */ |
1620 | ||
1621 | void | |
1622 | set_new_first_and_last_insn (first, last) | |
1623 | rtx first, last; | |
1624 | { | |
86fe05e0 RK |
1625 | rtx insn; |
1626 | ||
23b2ce53 RS |
1627 | first_insn = first; |
1628 | last_insn = last; | |
86fe05e0 RK |
1629 | cur_insn_uid = 0; |
1630 | ||
1631 | for (insn = first; insn; insn = NEXT_INSN (insn)) | |
1632 | cur_insn_uid = MAX (cur_insn_uid, INSN_UID (insn)); | |
1633 | ||
1634 | cur_insn_uid++; | |
23b2ce53 RS |
1635 | } |
1636 | ||
1637 | /* Set the range of label numbers found in the current function. | |
1638 | This is used when belatedly compiling an inline function. */ | |
1639 | ||
1640 | void | |
1641 | set_new_first_and_last_label_num (first, last) | |
1642 | int first, last; | |
1643 | { | |
1644 | base_label_num = label_num; | |
1645 | first_label_num = first; | |
1646 | last_label_num = last; | |
1647 | } | |
49ad7cfa BS |
1648 | |
1649 | /* Set the last label number found in the current function. | |
1650 | This is used when belatedly compiling an inline function. */ | |
23b2ce53 RS |
1651 | |
1652 | void | |
49ad7cfa BS |
1653 | set_new_last_label_num (last) |
1654 | int last; | |
23b2ce53 | 1655 | { |
49ad7cfa BS |
1656 | base_label_num = label_num; |
1657 | last_label_num = last; | |
23b2ce53 | 1658 | } |
49ad7cfa | 1659 | \f |
23b2ce53 RS |
1660 | /* Restore all variables describing the current status from the structure *P. |
1661 | This is used after a nested function. */ | |
1662 | ||
1663 | void | |
1664 | restore_emit_status (p) | |
272df862 | 1665 | struct function *p ATTRIBUTE_UNUSED; |
23b2ce53 | 1666 | { |
457a2d9c | 1667 | last_label_num = 0; |
49ad7cfa | 1668 | clear_emit_caches (); |
23b2ce53 | 1669 | } |
e2ecd91c | 1670 | |
21cd906e | 1671 | /* Clear out all parts of the state in F that can safely be discarded |
e2ecd91c | 1672 | after the function has been compiled, to let garbage collection |
0a8a198c | 1673 | reclaim the memory. */ |
21cd906e | 1674 | |
e2ecd91c | 1675 | void |
0a8a198c | 1676 | free_emit_status (f) |
e2ecd91c BS |
1677 | struct function *f; |
1678 | { | |
1679 | free (f->emit->x_regno_reg_rtx); | |
1680 | free (f->emit->regno_pointer_flag); | |
1681 | free (f->emit->regno_pointer_align); | |
fa51b01b RH |
1682 | free (f->emit); |
1683 | f->emit = NULL; | |
e2ecd91c | 1684 | } |
23b2ce53 | 1685 | \f |
d1b81779 GK |
1686 | /* Go through all the RTL insn bodies and copy any invalid shared |
1687 | structure. This routine should only be called once. */ | |
23b2ce53 RS |
1688 | |
1689 | void | |
d1b81779 GK |
1690 | unshare_all_rtl (fndecl, insn) |
1691 | tree fndecl; | |
1692 | rtx insn; | |
23b2ce53 | 1693 | { |
d1b81779 | 1694 | tree decl; |
23b2ce53 | 1695 | |
d1b81779 GK |
1696 | /* Make sure that virtual parameters are not shared. */ |
1697 | for (decl = DECL_ARGUMENTS (fndecl); decl; decl = TREE_CHAIN (decl)) | |
c13e8210 | 1698 | copy_rtx_if_shared (DECL_RTL (decl)); |
d1b81779 GK |
1699 | |
1700 | /* Unshare just about everything else. */ | |
1701 | unshare_all_rtl_1 (insn); | |
1702 | ||
23b2ce53 RS |
1703 | /* Make sure the addresses of stack slots found outside the insn chain |
1704 | (such as, in DECL_RTL of a variable) are not shared | |
1705 | with the insn chain. | |
1706 | ||
1707 | This special care is necessary when the stack slot MEM does not | |
1708 | actually appear in the insn chain. If it does appear, its address | |
1709 | is unshared from all else at that point. */ | |
23b2ce53 RS |
1710 | copy_rtx_if_shared (stack_slot_list); |
1711 | } | |
1712 | ||
d1b81779 GK |
1713 | /* Go through all the RTL insn bodies and copy any invalid shared |
1714 | structure, again. This is a fairly expensive thing to do so it | |
1715 | should be done sparingly. */ | |
1716 | ||
1717 | void | |
1718 | unshare_all_rtl_again (insn) | |
1719 | rtx insn; | |
1720 | { | |
1721 | rtx p; | |
624c87aa RE |
1722 | tree decl; |
1723 | ||
d1b81779 GK |
1724 | for (p = insn; p; p = NEXT_INSN (p)) |
1725 | if (GET_RTX_CLASS (GET_CODE (p)) == 'i') | |
1726 | { | |
1727 | reset_used_flags (PATTERN (p)); | |
1728 | reset_used_flags (REG_NOTES (p)); | |
1729 | reset_used_flags (LOG_LINKS (p)); | |
1730 | } | |
624c87aa RE |
1731 | |
1732 | /* Make sure that virtual parameters are not shared. */ | |
1733 | for (decl = DECL_ARGUMENTS (cfun->decl); decl; decl = TREE_CHAIN (decl)) | |
1734 | reset_used_flags (DECL_RTL (decl)); | |
1735 | ||
1736 | reset_used_flags (stack_slot_list); | |
1737 | ||
1738 | unshare_all_rtl (cfun->decl, insn); | |
d1b81779 GK |
1739 | } |
1740 | ||
1741 | /* Go through all the RTL insn bodies and copy any invalid shared structure. | |
1742 | Assumes the mark bits are cleared at entry. */ | |
1743 | ||
1744 | static void | |
1745 | unshare_all_rtl_1 (insn) | |
1746 | rtx insn; | |
1747 | { | |
1748 | for (; insn; insn = NEXT_INSN (insn)) | |
1749 | if (GET_RTX_CLASS (GET_CODE (insn)) == 'i') | |
1750 | { | |
1751 | PATTERN (insn) = copy_rtx_if_shared (PATTERN (insn)); | |
1752 | REG_NOTES (insn) = copy_rtx_if_shared (REG_NOTES (insn)); | |
1753 | LOG_LINKS (insn) = copy_rtx_if_shared (LOG_LINKS (insn)); | |
1754 | } | |
1755 | } | |
1756 | ||
23b2ce53 RS |
1757 | /* Mark ORIG as in use, and return a copy of it if it was already in use. |
1758 | Recursively does the same for subexpressions. */ | |
1759 | ||
1760 | rtx | |
1761 | copy_rtx_if_shared (orig) | |
1762 | rtx orig; | |
1763 | { | |
1764 | register rtx x = orig; | |
1765 | register int i; | |
1766 | register enum rtx_code code; | |
6f7d635c | 1767 | register const char *format_ptr; |
23b2ce53 RS |
1768 | int copied = 0; |
1769 | ||
1770 | if (x == 0) | |
1771 | return 0; | |
1772 | ||
1773 | code = GET_CODE (x); | |
1774 | ||
1775 | /* These types may be freely shared. */ | |
1776 | ||
1777 | switch (code) | |
1778 | { | |
1779 | case REG: | |
1780 | case QUEUED: | |
1781 | case CONST_INT: | |
1782 | case CONST_DOUBLE: | |
1783 | case SYMBOL_REF: | |
1784 | case CODE_LABEL: | |
1785 | case PC: | |
1786 | case CC0: | |
1787 | case SCRATCH: | |
0f41302f | 1788 | /* SCRATCH must be shared because they represent distinct values. */ |
23b2ce53 RS |
1789 | return x; |
1790 | ||
b851ea09 RK |
1791 | case CONST: |
1792 | /* CONST can be shared if it contains a SYMBOL_REF. If it contains | |
1793 | a LABEL_REF, it isn't sharable. */ | |
1794 | if (GET_CODE (XEXP (x, 0)) == PLUS | |
1795 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF | |
1796 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT) | |
1797 | return x; | |
1798 | break; | |
1799 | ||
23b2ce53 RS |
1800 | case INSN: |
1801 | case JUMP_INSN: | |
1802 | case CALL_INSN: | |
1803 | case NOTE: | |
23b2ce53 RS |
1804 | case BARRIER: |
1805 | /* The chain of insns is not being copied. */ | |
1806 | return x; | |
1807 | ||
1808 | case MEM: | |
83512665 JL |
1809 | /* A MEM is allowed to be shared if its address is constant. |
1810 | ||
1811 | We used to allow sharing of MEMs which referenced | |
1812 | virtual_stack_vars_rtx or virtual_incoming_args_rtx, but | |
1813 | that can lose. instantiate_virtual_regs will not unshare | |
1814 | the MEMs, and combine may change the structure of the address | |
1815 | because it looks safe and profitable in one context, but | |
1816 | in some other context it creates unrecognizable RTL. */ | |
1817 | if (CONSTANT_ADDRESS_P (XEXP (x, 0))) | |
23b2ce53 RS |
1818 | return x; |
1819 | ||
e9a25f70 JL |
1820 | break; |
1821 | ||
1822 | default: | |
1823 | break; | |
23b2ce53 RS |
1824 | } |
1825 | ||
1826 | /* This rtx may not be shared. If it has already been seen, | |
1827 | replace it with a copy of itself. */ | |
1828 | ||
1829 | if (x->used) | |
1830 | { | |
1831 | register rtx copy; | |
1832 | ||
1833 | copy = rtx_alloc (code); | |
4c9a05bc RK |
1834 | bcopy ((char *) x, (char *) copy, |
1835 | (sizeof (*copy) - sizeof (copy->fld) | |
1836 | + sizeof (copy->fld[0]) * GET_RTX_LENGTH (code))); | |
23b2ce53 RS |
1837 | x = copy; |
1838 | copied = 1; | |
1839 | } | |
1840 | x->used = 1; | |
1841 | ||
1842 | /* Now scan the subexpressions recursively. | |
1843 | We can store any replaced subexpressions directly into X | |
1844 | since we know X is not shared! Any vectors in X | |
1845 | must be copied if X was copied. */ | |
1846 | ||
1847 | format_ptr = GET_RTX_FORMAT (code); | |
1848 | ||
1849 | for (i = 0; i < GET_RTX_LENGTH (code); i++) | |
1850 | { | |
1851 | switch (*format_ptr++) | |
1852 | { | |
1853 | case 'e': | |
1854 | XEXP (x, i) = copy_rtx_if_shared (XEXP (x, i)); | |
1855 | break; | |
1856 | ||
1857 | case 'E': | |
1858 | if (XVEC (x, i) != NULL) | |
1859 | { | |
1860 | register int j; | |
f0722107 | 1861 | int len = XVECLEN (x, i); |
23b2ce53 | 1862 | |
f0722107 | 1863 | if (copied && len > 0) |
8f985ec4 | 1864 | XVEC (x, i) = gen_rtvec_v (len, XVEC (x, i)->elem); |
f0722107 RS |
1865 | for (j = 0; j < len; j++) |
1866 | XVECEXP (x, i, j) = copy_rtx_if_shared (XVECEXP (x, i, j)); | |
23b2ce53 RS |
1867 | } |
1868 | break; | |
1869 | } | |
1870 | } | |
1871 | return x; | |
1872 | } | |
1873 | ||
1874 | /* Clear all the USED bits in X to allow copy_rtx_if_shared to be used | |
1875 | to look for shared sub-parts. */ | |
1876 | ||
1877 | void | |
1878 | reset_used_flags (x) | |
1879 | rtx x; | |
1880 | { | |
1881 | register int i, j; | |
1882 | register enum rtx_code code; | |
6f7d635c | 1883 | register const char *format_ptr; |
23b2ce53 RS |
1884 | |
1885 | if (x == 0) | |
1886 | return; | |
1887 | ||
1888 | code = GET_CODE (x); | |
1889 | ||
9faa82d8 | 1890 | /* These types may be freely shared so we needn't do any resetting |
23b2ce53 RS |
1891 | for them. */ |
1892 | ||
1893 | switch (code) | |
1894 | { | |
1895 | case REG: | |
1896 | case QUEUED: | |
1897 | case CONST_INT: | |
1898 | case CONST_DOUBLE: | |
1899 | case SYMBOL_REF: | |
1900 | case CODE_LABEL: | |
1901 | case PC: | |
1902 | case CC0: | |
1903 | return; | |
1904 | ||
1905 | case INSN: | |
1906 | case JUMP_INSN: | |
1907 | case CALL_INSN: | |
1908 | case NOTE: | |
1909 | case LABEL_REF: | |
1910 | case BARRIER: | |
1911 | /* The chain of insns is not being copied. */ | |
1912 | return; | |
e9a25f70 JL |
1913 | |
1914 | default: | |
1915 | break; | |
23b2ce53 RS |
1916 | } |
1917 | ||
1918 | x->used = 0; | |
1919 | ||
1920 | format_ptr = GET_RTX_FORMAT (code); | |
1921 | for (i = 0; i < GET_RTX_LENGTH (code); i++) | |
1922 | { | |
1923 | switch (*format_ptr++) | |
1924 | { | |
1925 | case 'e': | |
1926 | reset_used_flags (XEXP (x, i)); | |
1927 | break; | |
1928 | ||
1929 | case 'E': | |
1930 | for (j = 0; j < XVECLEN (x, i); j++) | |
1931 | reset_used_flags (XVECEXP (x, i, j)); | |
1932 | break; | |
1933 | } | |
1934 | } | |
1935 | } | |
1936 | \f | |
1937 | /* Copy X if necessary so that it won't be altered by changes in OTHER. | |
1938 | Return X or the rtx for the pseudo reg the value of X was copied into. | |
1939 | OTHER must be valid as a SET_DEST. */ | |
1940 | ||
1941 | rtx | |
1942 | make_safe_from (x, other) | |
1943 | rtx x, other; | |
1944 | { | |
1945 | while (1) | |
1946 | switch (GET_CODE (other)) | |
1947 | { | |
1948 | case SUBREG: | |
1949 | other = SUBREG_REG (other); | |
1950 | break; | |
1951 | case STRICT_LOW_PART: | |
1952 | case SIGN_EXTEND: | |
1953 | case ZERO_EXTEND: | |
1954 | other = XEXP (other, 0); | |
1955 | break; | |
1956 | default: | |
1957 | goto done; | |
1958 | } | |
1959 | done: | |
1960 | if ((GET_CODE (other) == MEM | |
1961 | && ! CONSTANT_P (x) | |
1962 | && GET_CODE (x) != REG | |
1963 | && GET_CODE (x) != SUBREG) | |
1964 | || (GET_CODE (other) == REG | |
1965 | && (REGNO (other) < FIRST_PSEUDO_REGISTER | |
1966 | || reg_mentioned_p (other, x)))) | |
1967 | { | |
1968 | rtx temp = gen_reg_rtx (GET_MODE (x)); | |
1969 | emit_move_insn (temp, x); | |
1970 | return temp; | |
1971 | } | |
1972 | return x; | |
1973 | } | |
1974 | \f | |
1975 | /* Emission of insns (adding them to the doubly-linked list). */ | |
1976 | ||
1977 | /* Return the first insn of the current sequence or current function. */ | |
1978 | ||
1979 | rtx | |
1980 | get_insns () | |
1981 | { | |
1982 | return first_insn; | |
1983 | } | |
1984 | ||
1985 | /* Return the last insn emitted in current sequence or current function. */ | |
1986 | ||
1987 | rtx | |
1988 | get_last_insn () | |
1989 | { | |
1990 | return last_insn; | |
1991 | } | |
1992 | ||
1993 | /* Specify a new insn as the last in the chain. */ | |
1994 | ||
1995 | void | |
1996 | set_last_insn (insn) | |
1997 | rtx insn; | |
1998 | { | |
1999 | if (NEXT_INSN (insn) != 0) | |
2000 | abort (); | |
2001 | last_insn = insn; | |
2002 | } | |
2003 | ||
2004 | /* Return the last insn emitted, even if it is in a sequence now pushed. */ | |
2005 | ||
2006 | rtx | |
2007 | get_last_insn_anywhere () | |
2008 | { | |
2009 | struct sequence_stack *stack; | |
2010 | if (last_insn) | |
2011 | return last_insn; | |
49ad7cfa | 2012 | for (stack = seq_stack; stack; stack = stack->next) |
23b2ce53 RS |
2013 | if (stack->last != 0) |
2014 | return stack->last; | |
2015 | return 0; | |
2016 | } | |
2017 | ||
2018 | /* Return a number larger than any instruction's uid in this function. */ | |
2019 | ||
2020 | int | |
2021 | get_max_uid () | |
2022 | { | |
2023 | return cur_insn_uid; | |
2024 | } | |
aeeeda03 | 2025 | |
673b5311 MM |
2026 | /* Renumber instructions so that no instruction UIDs are wasted. */ |
2027 | ||
aeeeda03 | 2028 | void |
673b5311 MM |
2029 | renumber_insns (stream) |
2030 | FILE *stream; | |
aeeeda03 MM |
2031 | { |
2032 | rtx insn; | |
aeeeda03 | 2033 | |
673b5311 MM |
2034 | /* If we're not supposed to renumber instructions, don't. */ |
2035 | if (!flag_renumber_insns) | |
2036 | return; | |
2037 | ||
aeeeda03 MM |
2038 | /* If there aren't that many instructions, then it's not really |
2039 | worth renumbering them. */ | |
673b5311 | 2040 | if (flag_renumber_insns == 1 && get_max_uid () < 25000) |
aeeeda03 MM |
2041 | return; |
2042 | ||
2043 | cur_insn_uid = 1; | |
2044 | ||
2045 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) | |
673b5311 MM |
2046 | { |
2047 | if (stream) | |
2048 | fprintf (stream, "Renumbering insn %d to %d\n", | |
2049 | INSN_UID (insn), cur_insn_uid); | |
2050 | INSN_UID (insn) = cur_insn_uid++; | |
2051 | } | |
aeeeda03 | 2052 | } |
23b2ce53 RS |
2053 | \f |
2054 | /* Return the next insn. If it is a SEQUENCE, return the first insn | |
2055 | of the sequence. */ | |
2056 | ||
2057 | rtx | |
2058 | next_insn (insn) | |
2059 | rtx insn; | |
2060 | { | |
2061 | if (insn) | |
2062 | { | |
2063 | insn = NEXT_INSN (insn); | |
2064 | if (insn && GET_CODE (insn) == INSN | |
2065 | && GET_CODE (PATTERN (insn)) == SEQUENCE) | |
2066 | insn = XVECEXP (PATTERN (insn), 0, 0); | |
2067 | } | |
2068 | ||
2069 | return insn; | |
2070 | } | |
2071 | ||
2072 | /* Return the previous insn. If it is a SEQUENCE, return the last insn | |
2073 | of the sequence. */ | |
2074 | ||
2075 | rtx | |
2076 | previous_insn (insn) | |
2077 | rtx insn; | |
2078 | { | |
2079 | if (insn) | |
2080 | { | |
2081 | insn = PREV_INSN (insn); | |
2082 | if (insn && GET_CODE (insn) == INSN | |
2083 | && GET_CODE (PATTERN (insn)) == SEQUENCE) | |
2084 | insn = XVECEXP (PATTERN (insn), 0, XVECLEN (PATTERN (insn), 0) - 1); | |
2085 | } | |
2086 | ||
2087 | return insn; | |
2088 | } | |
2089 | ||
2090 | /* Return the next insn after INSN that is not a NOTE. This routine does not | |
2091 | look inside SEQUENCEs. */ | |
2092 | ||
2093 | rtx | |
2094 | next_nonnote_insn (insn) | |
2095 | rtx insn; | |
2096 | { | |
2097 | while (insn) | |
2098 | { | |
2099 | insn = NEXT_INSN (insn); | |
2100 | if (insn == 0 || GET_CODE (insn) != NOTE) | |
2101 | break; | |
2102 | } | |
2103 | ||
2104 | return insn; | |
2105 | } | |
2106 | ||
2107 | /* Return the previous insn before INSN that is not a NOTE. This routine does | |
2108 | not look inside SEQUENCEs. */ | |
2109 | ||
2110 | rtx | |
2111 | prev_nonnote_insn (insn) | |
2112 | rtx insn; | |
2113 | { | |
2114 | while (insn) | |
2115 | { | |
2116 | insn = PREV_INSN (insn); | |
2117 | if (insn == 0 || GET_CODE (insn) != NOTE) | |
2118 | break; | |
2119 | } | |
2120 | ||
2121 | return insn; | |
2122 | } | |
2123 | ||
2124 | /* Return the next INSN, CALL_INSN or JUMP_INSN after INSN; | |
2125 | or 0, if there is none. This routine does not look inside | |
0f41302f | 2126 | SEQUENCEs. */ |
23b2ce53 RS |
2127 | |
2128 | rtx | |
2129 | next_real_insn (insn) | |
2130 | rtx insn; | |
2131 | { | |
2132 | while (insn) | |
2133 | { | |
2134 | insn = NEXT_INSN (insn); | |
2135 | if (insn == 0 || GET_CODE (insn) == INSN | |
2136 | || GET_CODE (insn) == CALL_INSN || GET_CODE (insn) == JUMP_INSN) | |
2137 | break; | |
2138 | } | |
2139 | ||
2140 | return insn; | |
2141 | } | |
2142 | ||
2143 | /* Return the last INSN, CALL_INSN or JUMP_INSN before INSN; | |
2144 | or 0, if there is none. This routine does not look inside | |
2145 | SEQUENCEs. */ | |
2146 | ||
2147 | rtx | |
2148 | prev_real_insn (insn) | |
2149 | rtx insn; | |
2150 | { | |
2151 | while (insn) | |
2152 | { | |
2153 | insn = PREV_INSN (insn); | |
2154 | if (insn == 0 || GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN | |
2155 | || GET_CODE (insn) == JUMP_INSN) | |
2156 | break; | |
2157 | } | |
2158 | ||
2159 | return insn; | |
2160 | } | |
2161 | ||
2162 | /* Find the next insn after INSN that really does something. This routine | |
2163 | does not look inside SEQUENCEs. Until reload has completed, this is the | |
2164 | same as next_real_insn. */ | |
2165 | ||
69732dcb RH |
2166 | int |
2167 | active_insn_p (insn) | |
2168 | rtx insn; | |
2169 | { | |
2170 | return (GET_CODE (insn) == CALL_INSN || GET_CODE (insn) == JUMP_INSN | |
2171 | || (GET_CODE (insn) == INSN | |
2172 | && (! reload_completed | |
2173 | || (GET_CODE (PATTERN (insn)) != USE | |
2174 | && GET_CODE (PATTERN (insn)) != CLOBBER)))); | |
2175 | } | |
2176 | ||
23b2ce53 RS |
2177 | rtx |
2178 | next_active_insn (insn) | |
2179 | rtx insn; | |
2180 | { | |
2181 | while (insn) | |
2182 | { | |
2183 | insn = NEXT_INSN (insn); | |
69732dcb | 2184 | if (insn == 0 || active_insn_p (insn)) |
23b2ce53 RS |
2185 | break; |
2186 | } | |
2187 | ||
2188 | return insn; | |
2189 | } | |
2190 | ||
2191 | /* Find the last insn before INSN that really does something. This routine | |
2192 | does not look inside SEQUENCEs. Until reload has completed, this is the | |
2193 | same as prev_real_insn. */ | |
2194 | ||
2195 | rtx | |
2196 | prev_active_insn (insn) | |
2197 | rtx insn; | |
2198 | { | |
2199 | while (insn) | |
2200 | { | |
2201 | insn = PREV_INSN (insn); | |
69732dcb | 2202 | if (insn == 0 || active_insn_p (insn)) |
23b2ce53 RS |
2203 | break; |
2204 | } | |
2205 | ||
2206 | return insn; | |
2207 | } | |
2208 | ||
2209 | /* Return the next CODE_LABEL after the insn INSN, or 0 if there is none. */ | |
2210 | ||
2211 | rtx | |
2212 | next_label (insn) | |
2213 | rtx insn; | |
2214 | { | |
2215 | while (insn) | |
2216 | { | |
2217 | insn = NEXT_INSN (insn); | |
2218 | if (insn == 0 || GET_CODE (insn) == CODE_LABEL) | |
2219 | break; | |
2220 | } | |
2221 | ||
2222 | return insn; | |
2223 | } | |
2224 | ||
2225 | /* Return the last CODE_LABEL before the insn INSN, or 0 if there is none. */ | |
2226 | ||
2227 | rtx | |
2228 | prev_label (insn) | |
2229 | rtx insn; | |
2230 | { | |
2231 | while (insn) | |
2232 | { | |
2233 | insn = PREV_INSN (insn); | |
2234 | if (insn == 0 || GET_CODE (insn) == CODE_LABEL) | |
2235 | break; | |
2236 | } | |
2237 | ||
2238 | return insn; | |
2239 | } | |
2240 | \f | |
2241 | #ifdef HAVE_cc0 | |
c572e5ba JVA |
2242 | /* INSN uses CC0 and is being moved into a delay slot. Set up REG_CC_SETTER |
2243 | and REG_CC_USER notes so we can find it. */ | |
2244 | ||
2245 | void | |
2246 | link_cc0_insns (insn) | |
2247 | rtx insn; | |
2248 | { | |
2249 | rtx user = next_nonnote_insn (insn); | |
2250 | ||
2251 | if (GET_CODE (user) == INSN && GET_CODE (PATTERN (user)) == SEQUENCE) | |
2252 | user = XVECEXP (PATTERN (user), 0, 0); | |
2253 | ||
c5c76735 JL |
2254 | REG_NOTES (user) = gen_rtx_INSN_LIST (REG_CC_SETTER, insn, |
2255 | REG_NOTES (user)); | |
3b80f6ca | 2256 | REG_NOTES (insn) = gen_rtx_INSN_LIST (REG_CC_USER, user, REG_NOTES (insn)); |
c572e5ba JVA |
2257 | } |
2258 | ||
23b2ce53 RS |
2259 | /* Return the next insn that uses CC0 after INSN, which is assumed to |
2260 | set it. This is the inverse of prev_cc0_setter (i.e., prev_cc0_setter | |
2261 | applied to the result of this function should yield INSN). | |
2262 | ||
2263 | Normally, this is simply the next insn. However, if a REG_CC_USER note | |
2264 | is present, it contains the insn that uses CC0. | |
2265 | ||
2266 | Return 0 if we can't find the insn. */ | |
2267 | ||
2268 | rtx | |
2269 | next_cc0_user (insn) | |
2270 | rtx insn; | |
2271 | { | |
906c4e36 | 2272 | rtx note = find_reg_note (insn, REG_CC_USER, NULL_RTX); |
23b2ce53 RS |
2273 | |
2274 | if (note) | |
2275 | return XEXP (note, 0); | |
2276 | ||
2277 | insn = next_nonnote_insn (insn); | |
2278 | if (insn && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SEQUENCE) | |
2279 | insn = XVECEXP (PATTERN (insn), 0, 0); | |
2280 | ||
2281 | if (insn && GET_RTX_CLASS (GET_CODE (insn)) == 'i' | |
2282 | && reg_mentioned_p (cc0_rtx, PATTERN (insn))) | |
2283 | return insn; | |
2284 | ||
2285 | return 0; | |
2286 | } | |
2287 | ||
2288 | /* Find the insn that set CC0 for INSN. Unless INSN has a REG_CC_SETTER | |
2289 | note, it is the previous insn. */ | |
2290 | ||
2291 | rtx | |
2292 | prev_cc0_setter (insn) | |
2293 | rtx insn; | |
2294 | { | |
906c4e36 | 2295 | rtx note = find_reg_note (insn, REG_CC_SETTER, NULL_RTX); |
23b2ce53 RS |
2296 | |
2297 | if (note) | |
2298 | return XEXP (note, 0); | |
2299 | ||
2300 | insn = prev_nonnote_insn (insn); | |
2301 | if (! sets_cc0_p (PATTERN (insn))) | |
2302 | abort (); | |
2303 | ||
2304 | return insn; | |
2305 | } | |
2306 | #endif | |
2307 | \f | |
2308 | /* Try splitting insns that can be split for better scheduling. | |
2309 | PAT is the pattern which might split. | |
2310 | TRIAL is the insn providing PAT. | |
11147ebe | 2311 | LAST is non-zero if we should return the last insn of the sequence produced. |
23b2ce53 RS |
2312 | |
2313 | If this routine succeeds in splitting, it returns the first or last | |
11147ebe | 2314 | replacement insn depending on the value of LAST. Otherwise, it |
23b2ce53 RS |
2315 | returns TRIAL. If the insn to be returned can be split, it will be. */ |
2316 | ||
2317 | rtx | |
11147ebe | 2318 | try_split (pat, trial, last) |
23b2ce53 | 2319 | rtx pat, trial; |
11147ebe | 2320 | int last; |
23b2ce53 RS |
2321 | { |
2322 | rtx before = PREV_INSN (trial); | |
2323 | rtx after = NEXT_INSN (trial); | |
2324 | rtx seq = split_insns (pat, trial); | |
2325 | int has_barrier = 0; | |
2326 | rtx tem; | |
2327 | ||
2328 | /* If we are splitting a JUMP_INSN, it might be followed by a BARRIER. | |
2329 | We may need to handle this specially. */ | |
2330 | if (after && GET_CODE (after) == BARRIER) | |
2331 | { | |
2332 | has_barrier = 1; | |
2333 | after = NEXT_INSN (after); | |
2334 | } | |
2335 | ||
2336 | if (seq) | |
2337 | { | |
2338 | /* SEQ can either be a SEQUENCE or the pattern of a single insn. | |
2339 | The latter case will normally arise only when being done so that | |
2340 | it, in turn, will be split (SFmode on the 29k is an example). */ | |
2341 | if (GET_CODE (seq) == SEQUENCE) | |
2342 | { | |
4b5e8abe CP |
2343 | int i; |
2344 | ||
2345 | /* Avoid infinite loop if any insn of the result matches | |
2346 | the original pattern. */ | |
2347 | for (i = 0; i < XVECLEN (seq, 0); i++) | |
2348 | if (GET_CODE (XVECEXP (seq, 0, i)) == INSN | |
2349 | && rtx_equal_p (PATTERN (XVECEXP (seq, 0, i)), pat)) | |
2350 | return trial; | |
2351 | ||
23b2ce53 RS |
2352 | /* If we are splitting a JUMP_INSN, look for the JUMP_INSN in |
2353 | SEQ and copy our JUMP_LABEL to it. If JUMP_LABEL is non-zero, | |
2354 | increment the usage count so we don't delete the label. */ | |
23b2ce53 RS |
2355 | |
2356 | if (GET_CODE (trial) == JUMP_INSN) | |
2357 | for (i = XVECLEN (seq, 0) - 1; i >= 0; i--) | |
2358 | if (GET_CODE (XVECEXP (seq, 0, i)) == JUMP_INSN) | |
2359 | { | |
2360 | JUMP_LABEL (XVECEXP (seq, 0, i)) = JUMP_LABEL (trial); | |
2361 | ||
2362 | if (JUMP_LABEL (trial)) | |
2363 | LABEL_NUSES (JUMP_LABEL (trial))++; | |
2364 | } | |
2365 | ||
2366 | tem = emit_insn_after (seq, before); | |
2367 | ||
2368 | delete_insn (trial); | |
2369 | if (has_barrier) | |
2370 | emit_barrier_after (tem); | |
11147ebe RK |
2371 | |
2372 | /* Recursively call try_split for each new insn created; by the | |
2373 | time control returns here that insn will be fully split, so | |
2374 | set LAST and continue from the insn after the one returned. | |
f4a3cd05 | 2375 | We can't use next_active_insn here since AFTER may be a note. |
23886015 | 2376 | Ignore deleted insns, which can be occur if not optimizing. */ |
11147ebe RK |
2377 | for (tem = NEXT_INSN (before); tem != after; |
2378 | tem = NEXT_INSN (tem)) | |
23886015 RH |
2379 | if (! INSN_DELETED_P (tem) |
2380 | && GET_RTX_CLASS (GET_CODE (tem)) == 'i') | |
f4a3cd05 | 2381 | tem = try_split (PATTERN (tem), tem, 1); |
23b2ce53 RS |
2382 | } |
2383 | /* Avoid infinite loop if the result matches the original pattern. */ | |
2384 | else if (rtx_equal_p (seq, pat)) | |
2385 | return trial; | |
2386 | else | |
2387 | { | |
2388 | PATTERN (trial) = seq; | |
2389 | INSN_CODE (trial) = -1; | |
11147ebe | 2390 | try_split (seq, trial, last); |
23b2ce53 RS |
2391 | } |
2392 | ||
11147ebe RK |
2393 | /* Return either the first or the last insn, depending on which was |
2394 | requested. */ | |
ba52f355 CP |
2395 | return last |
2396 | ? (after ? prev_active_insn (after) : last_insn) | |
2397 | : next_active_insn (before); | |
23b2ce53 RS |
2398 | } |
2399 | ||
2400 | return trial; | |
2401 | } | |
2402 | \f | |
2403 | /* Make and return an INSN rtx, initializing all its slots. | |
4b1f5e8c | 2404 | Store PATTERN in the pattern slots. */ |
23b2ce53 RS |
2405 | |
2406 | rtx | |
4b1f5e8c | 2407 | make_insn_raw (pattern) |
23b2ce53 | 2408 | rtx pattern; |
23b2ce53 RS |
2409 | { |
2410 | register rtx insn; | |
2411 | ||
43127294 | 2412 | /* If in RTL generation phase, see if FREE_INSN can be used. */ |
a3770a81 | 2413 | if (!ggc_p && free_insn != 0 && rtx_equal_function_value_matters) |
43127294 RK |
2414 | { |
2415 | insn = free_insn; | |
2416 | free_insn = NEXT_INSN (free_insn); | |
2417 | PUT_CODE (insn, INSN); | |
2418 | } | |
2419 | else | |
2420 | insn = rtx_alloc (INSN); | |
23b2ce53 | 2421 | |
43127294 | 2422 | INSN_UID (insn) = cur_insn_uid++; |
23b2ce53 RS |
2423 | PATTERN (insn) = pattern; |
2424 | INSN_CODE (insn) = -1; | |
1632afca RS |
2425 | LOG_LINKS (insn) = NULL; |
2426 | REG_NOTES (insn) = NULL; | |
23b2ce53 | 2427 | |
47984720 NC |
2428 | #ifdef ENABLE_RTL_CHECKING |
2429 | if (insn | |
2430 | && GET_RTX_CLASS (GET_CODE (insn)) == 'i' | |
2431 | && (returnjump_p (insn) | |
2432 | || (GET_CODE (insn) == SET | |
2433 | && SET_DEST (insn) == pc_rtx))) | |
2434 | { | |
2435 | warning ("ICE: emit_insn used where emit_jump_insn needed:\n"); | |
2436 | debug_rtx (insn); | |
2437 | } | |
2438 | #endif | |
2439 | ||
23b2ce53 RS |
2440 | return insn; |
2441 | } | |
2442 | ||
2443 | /* Like `make_insn' but make a JUMP_INSN instead of an insn. */ | |
2444 | ||
2445 | static rtx | |
4b1f5e8c | 2446 | make_jump_insn_raw (pattern) |
23b2ce53 | 2447 | rtx pattern; |
23b2ce53 RS |
2448 | { |
2449 | register rtx insn; | |
2450 | ||
4b1f5e8c | 2451 | insn = rtx_alloc (JUMP_INSN); |
1632afca | 2452 | INSN_UID (insn) = cur_insn_uid++; |
23b2ce53 RS |
2453 | |
2454 | PATTERN (insn) = pattern; | |
2455 | INSN_CODE (insn) = -1; | |
1632afca RS |
2456 | LOG_LINKS (insn) = NULL; |
2457 | REG_NOTES (insn) = NULL; | |
2458 | JUMP_LABEL (insn) = NULL; | |
23b2ce53 RS |
2459 | |
2460 | return insn; | |
2461 | } | |
aff507f4 RK |
2462 | |
2463 | /* Like `make_insn' but make a CALL_INSN instead of an insn. */ | |
2464 | ||
2465 | static rtx | |
2466 | make_call_insn_raw (pattern) | |
2467 | rtx pattern; | |
2468 | { | |
2469 | register rtx insn; | |
2470 | ||
2471 | insn = rtx_alloc (CALL_INSN); | |
2472 | INSN_UID (insn) = cur_insn_uid++; | |
2473 | ||
2474 | PATTERN (insn) = pattern; | |
2475 | INSN_CODE (insn) = -1; | |
2476 | LOG_LINKS (insn) = NULL; | |
2477 | REG_NOTES (insn) = NULL; | |
2478 | CALL_INSN_FUNCTION_USAGE (insn) = NULL; | |
2479 | ||
2480 | return insn; | |
2481 | } | |
23b2ce53 RS |
2482 | \f |
2483 | /* Add INSN to the end of the doubly-linked list. | |
2484 | INSN may be an INSN, JUMP_INSN, CALL_INSN, CODE_LABEL, BARRIER or NOTE. */ | |
2485 | ||
2486 | void | |
2487 | add_insn (insn) | |
2488 | register rtx insn; | |
2489 | { | |
2490 | PREV_INSN (insn) = last_insn; | |
2491 | NEXT_INSN (insn) = 0; | |
2492 | ||
2493 | if (NULL != last_insn) | |
2494 | NEXT_INSN (last_insn) = insn; | |
2495 | ||
2496 | if (NULL == first_insn) | |
2497 | first_insn = insn; | |
2498 | ||
2499 | last_insn = insn; | |
2500 | } | |
2501 | ||
a0ae8e8d RK |
2502 | /* Add INSN into the doubly-linked list after insn AFTER. This and |
2503 | the next should be the only functions called to insert an insn once | |
ba213285 | 2504 | delay slots have been filled since only they know how to update a |
a0ae8e8d | 2505 | SEQUENCE. */ |
23b2ce53 RS |
2506 | |
2507 | void | |
2508 | add_insn_after (insn, after) | |
2509 | rtx insn, after; | |
2510 | { | |
2511 | rtx next = NEXT_INSN (after); | |
2512 | ||
6782074d | 2513 | if (optimize && INSN_DELETED_P (after)) |
ba213285 RK |
2514 | abort (); |
2515 | ||
23b2ce53 RS |
2516 | NEXT_INSN (insn) = next; |
2517 | PREV_INSN (insn) = after; | |
2518 | ||
2519 | if (next) | |
2520 | { | |
2521 | PREV_INSN (next) = insn; | |
2522 | if (GET_CODE (next) == INSN && GET_CODE (PATTERN (next)) == SEQUENCE) | |
2523 | PREV_INSN (XVECEXP (PATTERN (next), 0, 0)) = insn; | |
2524 | } | |
2525 | else if (last_insn == after) | |
2526 | last_insn = insn; | |
2527 | else | |
2528 | { | |
49ad7cfa | 2529 | struct sequence_stack *stack = seq_stack; |
23b2ce53 RS |
2530 | /* Scan all pending sequences too. */ |
2531 | for (; stack; stack = stack->next) | |
2532 | if (after == stack->last) | |
fef0509b RK |
2533 | { |
2534 | stack->last = insn; | |
2535 | break; | |
2536 | } | |
a0ae8e8d RK |
2537 | |
2538 | if (stack == 0) | |
2539 | abort (); | |
23b2ce53 RS |
2540 | } |
2541 | ||
2542 | NEXT_INSN (after) = insn; | |
2543 | if (GET_CODE (after) == INSN && GET_CODE (PATTERN (after)) == SEQUENCE) | |
2544 | { | |
2545 | rtx sequence = PATTERN (after); | |
2546 | NEXT_INSN (XVECEXP (sequence, 0, XVECLEN (sequence, 0) - 1)) = insn; | |
2547 | } | |
2548 | } | |
2549 | ||
a0ae8e8d RK |
2550 | /* Add INSN into the doubly-linked list before insn BEFORE. This and |
2551 | the previous should be the only functions called to insert an insn once | |
ba213285 | 2552 | delay slots have been filled since only they know how to update a |
a0ae8e8d RK |
2553 | SEQUENCE. */ |
2554 | ||
2555 | void | |
2556 | add_insn_before (insn, before) | |
2557 | rtx insn, before; | |
2558 | { | |
2559 | rtx prev = PREV_INSN (before); | |
2560 | ||
6782074d | 2561 | if (optimize && INSN_DELETED_P (before)) |
ba213285 RK |
2562 | abort (); |
2563 | ||
a0ae8e8d RK |
2564 | PREV_INSN (insn) = prev; |
2565 | NEXT_INSN (insn) = before; | |
2566 | ||
2567 | if (prev) | |
2568 | { | |
2569 | NEXT_INSN (prev) = insn; | |
2570 | if (GET_CODE (prev) == INSN && GET_CODE (PATTERN (prev)) == SEQUENCE) | |
2571 | { | |
2572 | rtx sequence = PATTERN (prev); | |
2573 | NEXT_INSN (XVECEXP (sequence, 0, XVECLEN (sequence, 0) - 1)) = insn; | |
2574 | } | |
2575 | } | |
2576 | else if (first_insn == before) | |
2577 | first_insn = insn; | |
2578 | else | |
2579 | { | |
49ad7cfa | 2580 | struct sequence_stack *stack = seq_stack; |
a0ae8e8d RK |
2581 | /* Scan all pending sequences too. */ |
2582 | for (; stack; stack = stack->next) | |
2583 | if (before == stack->first) | |
fef0509b RK |
2584 | { |
2585 | stack->first = insn; | |
2586 | break; | |
2587 | } | |
a0ae8e8d RK |
2588 | |
2589 | if (stack == 0) | |
2590 | abort (); | |
2591 | } | |
2592 | ||
2593 | PREV_INSN (before) = insn; | |
2594 | if (GET_CODE (before) == INSN && GET_CODE (PATTERN (before)) == SEQUENCE) | |
2595 | PREV_INSN (XVECEXP (PATTERN (before), 0, 0)) = insn; | |
2596 | } | |
2597 | ||
89e99eea DB |
2598 | /* Remove an insn from its doubly-linked list. This function knows how |
2599 | to handle sequences. */ | |
2600 | void | |
2601 | remove_insn (insn) | |
2602 | rtx insn; | |
2603 | { | |
2604 | rtx next = NEXT_INSN (insn); | |
2605 | rtx prev = PREV_INSN (insn); | |
2606 | if (prev) | |
2607 | { | |
2608 | NEXT_INSN (prev) = next; | |
2609 | if (GET_CODE (prev) == INSN && GET_CODE (PATTERN (prev)) == SEQUENCE) | |
2610 | { | |
2611 | rtx sequence = PATTERN (prev); | |
2612 | NEXT_INSN (XVECEXP (sequence, 0, XVECLEN (sequence, 0) - 1)) = next; | |
2613 | } | |
2614 | } | |
2615 | else if (first_insn == insn) | |
2616 | first_insn = next; | |
2617 | else | |
2618 | { | |
49ad7cfa | 2619 | struct sequence_stack *stack = seq_stack; |
89e99eea DB |
2620 | /* Scan all pending sequences too. */ |
2621 | for (; stack; stack = stack->next) | |
2622 | if (insn == stack->first) | |
2623 | { | |
2624 | stack->first = next; | |
2625 | break; | |
2626 | } | |
2627 | ||
2628 | if (stack == 0) | |
2629 | abort (); | |
2630 | } | |
2631 | ||
2632 | if (next) | |
2633 | { | |
2634 | PREV_INSN (next) = prev; | |
2635 | if (GET_CODE (next) == INSN && GET_CODE (PATTERN (next)) == SEQUENCE) | |
2636 | PREV_INSN (XVECEXP (PATTERN (next), 0, 0)) = prev; | |
2637 | } | |
2638 | else if (last_insn == insn) | |
2639 | last_insn = prev; | |
2640 | else | |
2641 | { | |
49ad7cfa | 2642 | struct sequence_stack *stack = seq_stack; |
89e99eea DB |
2643 | /* Scan all pending sequences too. */ |
2644 | for (; stack; stack = stack->next) | |
2645 | if (insn == stack->last) | |
2646 | { | |
2647 | stack->last = prev; | |
2648 | break; | |
2649 | } | |
2650 | ||
2651 | if (stack == 0) | |
2652 | abort (); | |
2653 | } | |
2654 | } | |
2655 | ||
23b2ce53 RS |
2656 | /* Delete all insns made since FROM. |
2657 | FROM becomes the new last instruction. */ | |
2658 | ||
2659 | void | |
2660 | delete_insns_since (from) | |
2661 | rtx from; | |
2662 | { | |
2663 | if (from == 0) | |
2664 | first_insn = 0; | |
2665 | else | |
2666 | NEXT_INSN (from) = 0; | |
2667 | last_insn = from; | |
2668 | } | |
2669 | ||
5dab5552 MS |
2670 | /* This function is deprecated, please use sequences instead. |
2671 | ||
2672 | Move a consecutive bunch of insns to a different place in the chain. | |
23b2ce53 RS |
2673 | The insns to be moved are those between FROM and TO. |
2674 | They are moved to a new position after the insn AFTER. | |
2675 | AFTER must not be FROM or TO or any insn in between. | |
2676 | ||
2677 | This function does not know about SEQUENCEs and hence should not be | |
2678 | called after delay-slot filling has been done. */ | |
2679 | ||
2680 | void | |
2681 | reorder_insns (from, to, after) | |
2682 | rtx from, to, after; | |
2683 | { | |
2684 | /* Splice this bunch out of where it is now. */ | |
2685 | if (PREV_INSN (from)) | |
2686 | NEXT_INSN (PREV_INSN (from)) = NEXT_INSN (to); | |
2687 | if (NEXT_INSN (to)) | |
2688 | PREV_INSN (NEXT_INSN (to)) = PREV_INSN (from); | |
2689 | if (last_insn == to) | |
2690 | last_insn = PREV_INSN (from); | |
2691 | if (first_insn == from) | |
2692 | first_insn = NEXT_INSN (to); | |
2693 | ||
2694 | /* Make the new neighbors point to it and it to them. */ | |
2695 | if (NEXT_INSN (after)) | |
2696 | PREV_INSN (NEXT_INSN (after)) = to; | |
2697 | ||
2698 | NEXT_INSN (to) = NEXT_INSN (after); | |
2699 | PREV_INSN (from) = after; | |
2700 | NEXT_INSN (after) = from; | |
2701 | if (after == last_insn) | |
2702 | last_insn = to; | |
2703 | } | |
2704 | ||
2705 | /* Return the line note insn preceding INSN. */ | |
2706 | ||
2707 | static rtx | |
2708 | find_line_note (insn) | |
2709 | rtx insn; | |
2710 | { | |
2711 | if (no_line_numbers) | |
2712 | return 0; | |
2713 | ||
2714 | for (; insn; insn = PREV_INSN (insn)) | |
2715 | if (GET_CODE (insn) == NOTE | |
2716 | && NOTE_LINE_NUMBER (insn) >= 0) | |
2717 | break; | |
2718 | ||
2719 | return insn; | |
2720 | } | |
2721 | ||
2722 | /* Like reorder_insns, but inserts line notes to preserve the line numbers | |
2723 | of the moved insns when debugging. This may insert a note between AFTER | |
2724 | and FROM, and another one after TO. */ | |
2725 | ||
2726 | void | |
2727 | reorder_insns_with_line_notes (from, to, after) | |
2728 | rtx from, to, after; | |
2729 | { | |
2730 | rtx from_line = find_line_note (from); | |
2731 | rtx after_line = find_line_note (after); | |
2732 | ||
2733 | reorder_insns (from, to, after); | |
2734 | ||
2735 | if (from_line == after_line) | |
2736 | return; | |
2737 | ||
2738 | if (from_line) | |
2739 | emit_line_note_after (NOTE_SOURCE_FILE (from_line), | |
2740 | NOTE_LINE_NUMBER (from_line), | |
2741 | after); | |
2742 | if (after_line) | |
2743 | emit_line_note_after (NOTE_SOURCE_FILE (after_line), | |
2744 | NOTE_LINE_NUMBER (after_line), | |
2745 | to); | |
2746 | } | |
aeeeda03 | 2747 | |
64b59a80 | 2748 | /* Remove unnecessary notes from the instruction stream. */ |
aeeeda03 MM |
2749 | |
2750 | void | |
64b59a80 | 2751 | remove_unnecessary_notes () |
aeeeda03 MM |
2752 | { |
2753 | rtx insn; | |
2754 | rtx next; | |
aeeeda03 | 2755 | |
116eebd6 MM |
2756 | /* We must not remove the first instruction in the function because |
2757 | the compiler depends on the first instruction being a note. */ | |
aeeeda03 MM |
2758 | for (insn = NEXT_INSN (get_insns ()); insn; insn = next) |
2759 | { | |
2760 | /* Remember what's next. */ | |
2761 | next = NEXT_INSN (insn); | |
2762 | ||
2763 | /* We're only interested in notes. */ | |
2764 | if (GET_CODE (insn) != NOTE) | |
2765 | continue; | |
2766 | ||
116eebd6 MM |
2767 | /* By now, all notes indicating lexical blocks should have |
2768 | NOTE_BLOCK filled in. */ | |
2769 | if ((NOTE_LINE_NUMBER (insn) == NOTE_INSN_BLOCK_BEG | |
2770 | || NOTE_LINE_NUMBER (insn) == NOTE_INSN_BLOCK_END) | |
2771 | && NOTE_BLOCK (insn) == NULL_TREE) | |
2772 | abort (); | |
2773 | ||
2774 | /* Remove NOTE_INSN_DELETED notes. */ | |
aeeeda03 MM |
2775 | if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_DELETED) |
2776 | remove_insn (insn); | |
18c038b9 MM |
2777 | else if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_BLOCK_END) |
2778 | { | |
2779 | /* Scan back to see if there are any non-note instructions | |
2780 | between INSN and the beginning of this block. If not, | |
2781 | then there is no PC range in the generated code that will | |
2782 | actually be in this block, so there's no point in | |
2783 | remembering the existence of the block. */ | |
2784 | rtx prev; | |
2785 | ||
2786 | for (prev = PREV_INSN (insn); prev; prev = PREV_INSN (prev)) | |
2787 | { | |
2788 | /* This block contains a real instruction. Note that we | |
2789 | don't include labels; if the only thing in the block | |
2790 | is a label, then there are still no PC values that | |
2791 | lie within the block. */ | |
2792 | if (GET_RTX_CLASS (GET_CODE (prev)) == 'i') | |
2793 | break; | |
2794 | ||
2795 | /* We're only interested in NOTEs. */ | |
2796 | if (GET_CODE (prev) != NOTE) | |
2797 | continue; | |
2798 | ||
2799 | if (NOTE_LINE_NUMBER (prev) == NOTE_INSN_BLOCK_BEG) | |
2800 | { | |
2801 | /* If the BLOCKs referred to by these notes don't | |
2802 | match, then something is wrong with our BLOCK | |
2803 | nesting structure. */ | |
2804 | if (NOTE_BLOCK (prev) != NOTE_BLOCK (insn)) | |
2805 | abort (); | |
fcd7f76b | 2806 | |
64b59a80 | 2807 | if (debug_ignore_block (NOTE_BLOCK (insn))) |
deb5e280 | 2808 | { |
deb5e280 JM |
2809 | remove_insn (prev); |
2810 | remove_insn (insn); | |
2811 | } | |
18c038b9 MM |
2812 | break; |
2813 | } | |
2814 | else if (NOTE_LINE_NUMBER (prev) == NOTE_INSN_BLOCK_END) | |
2815 | /* There's a nested block. We need to leave the | |
2816 | current block in place since otherwise the debugger | |
2817 | wouldn't be able to show symbols from our block in | |
2818 | the nested block. */ | |
2819 | break; | |
2820 | } | |
2821 | } | |
aeeeda03 MM |
2822 | } |
2823 | } | |
2824 | ||
23b2ce53 RS |
2825 | \f |
2826 | /* Emit an insn of given code and pattern | |
2827 | at a specified place within the doubly-linked list. */ | |
2828 | ||
2829 | /* Make an instruction with body PATTERN | |
2830 | and output it before the instruction BEFORE. */ | |
2831 | ||
2832 | rtx | |
2833 | emit_insn_before (pattern, before) | |
2834 | register rtx pattern, before; | |
2835 | { | |
2836 | register rtx insn = before; | |
2837 | ||
2838 | if (GET_CODE (pattern) == SEQUENCE) | |
2839 | { | |
2840 | register int i; | |
2841 | ||
2842 | for (i = 0; i < XVECLEN (pattern, 0); i++) | |
2843 | { | |
2844 | insn = XVECEXP (pattern, 0, i); | |
a0ae8e8d | 2845 | add_insn_before (insn, before); |
23b2ce53 | 2846 | } |
a3770a81 | 2847 | if (!ggc_p && XVECLEN (pattern, 0) < SEQUENCE_RESULT_SIZE) |
23b2ce53 RS |
2848 | sequence_result[XVECLEN (pattern, 0)] = pattern; |
2849 | } | |
2850 | else | |
2851 | { | |
4b1f5e8c | 2852 | insn = make_insn_raw (pattern); |
a0ae8e8d | 2853 | add_insn_before (insn, before); |
23b2ce53 RS |
2854 | } |
2855 | ||
2856 | return insn; | |
2857 | } | |
2858 | ||
a05924f9 JH |
2859 | /* Similar to emit_insn_before, but update basic block boundaries as well. */ |
2860 | ||
2861 | rtx | |
2862 | emit_block_insn_before (pattern, before, block) | |
2863 | rtx pattern, before; | |
2864 | basic_block block; | |
2865 | { | |
2866 | rtx prev = PREV_INSN (before); | |
2867 | rtx r = emit_insn_before (pattern, before); | |
2868 | if (block && block->head == before) | |
2869 | block->head = NEXT_INSN (prev); | |
2870 | return r; | |
2871 | } | |
2872 | ||
23b2ce53 RS |
2873 | /* Make an instruction with body PATTERN and code JUMP_INSN |
2874 | and output it before the instruction BEFORE. */ | |
2875 | ||
2876 | rtx | |
2877 | emit_jump_insn_before (pattern, before) | |
2878 | register rtx pattern, before; | |
2879 | { | |
2880 | register rtx insn; | |
2881 | ||
2882 | if (GET_CODE (pattern) == SEQUENCE) | |
2883 | insn = emit_insn_before (pattern, before); | |
2884 | else | |
2885 | { | |
85cf32bc | 2886 | insn = make_jump_insn_raw (pattern); |
a0ae8e8d | 2887 | add_insn_before (insn, before); |
23b2ce53 RS |
2888 | } |
2889 | ||
2890 | return insn; | |
2891 | } | |
2892 | ||
2893 | /* Make an instruction with body PATTERN and code CALL_INSN | |
2894 | and output it before the instruction BEFORE. */ | |
2895 | ||
2896 | rtx | |
2897 | emit_call_insn_before (pattern, before) | |
2898 | register rtx pattern, before; | |
2899 | { | |
aff507f4 RK |
2900 | register rtx insn; |
2901 | ||
2902 | if (GET_CODE (pattern) == SEQUENCE) | |
2903 | insn = emit_insn_before (pattern, before); | |
2904 | else | |
2905 | { | |
2906 | insn = make_call_insn_raw (pattern); | |
a0ae8e8d | 2907 | add_insn_before (insn, before); |
aff507f4 RK |
2908 | PUT_CODE (insn, CALL_INSN); |
2909 | } | |
2910 | ||
23b2ce53 RS |
2911 | return insn; |
2912 | } | |
2913 | ||
2914 | /* Make an insn of code BARRIER | |
e881bb1b | 2915 | and output it before the insn BEFORE. */ |
23b2ce53 RS |
2916 | |
2917 | rtx | |
2918 | emit_barrier_before (before) | |
2919 | register rtx before; | |
2920 | { | |
2921 | register rtx insn = rtx_alloc (BARRIER); | |
2922 | ||
2923 | INSN_UID (insn) = cur_insn_uid++; | |
2924 | ||
a0ae8e8d | 2925 | add_insn_before (insn, before); |
23b2ce53 RS |
2926 | return insn; |
2927 | } | |
2928 | ||
e881bb1b RH |
2929 | /* Emit the label LABEL before the insn BEFORE. */ |
2930 | ||
2931 | rtx | |
2932 | emit_label_before (label, before) | |
2933 | rtx label, before; | |
2934 | { | |
2935 | /* This can be called twice for the same label as a result of the | |
2936 | confusion that follows a syntax error! So make it harmless. */ | |
2937 | if (INSN_UID (label) == 0) | |
2938 | { | |
2939 | INSN_UID (label) = cur_insn_uid++; | |
2940 | add_insn_before (label, before); | |
2941 | } | |
2942 | ||
2943 | return label; | |
2944 | } | |
2945 | ||
23b2ce53 RS |
2946 | /* Emit a note of subtype SUBTYPE before the insn BEFORE. */ |
2947 | ||
2948 | rtx | |
2949 | emit_note_before (subtype, before) | |
2950 | int subtype; | |
2951 | rtx before; | |
2952 | { | |
2953 | register rtx note = rtx_alloc (NOTE); | |
2954 | INSN_UID (note) = cur_insn_uid++; | |
2955 | NOTE_SOURCE_FILE (note) = 0; | |
2956 | NOTE_LINE_NUMBER (note) = subtype; | |
2957 | ||
a0ae8e8d | 2958 | add_insn_before (note, before); |
23b2ce53 RS |
2959 | return note; |
2960 | } | |
2961 | \f | |
2962 | /* Make an insn of code INSN with body PATTERN | |
2963 | and output it after the insn AFTER. */ | |
2964 | ||
2965 | rtx | |
2966 | emit_insn_after (pattern, after) | |
2967 | register rtx pattern, after; | |
2968 | { | |
2969 | register rtx insn = after; | |
2970 | ||
2971 | if (GET_CODE (pattern) == SEQUENCE) | |
2972 | { | |
2973 | register int i; | |
2974 | ||
2975 | for (i = 0; i < XVECLEN (pattern, 0); i++) | |
2976 | { | |
2977 | insn = XVECEXP (pattern, 0, i); | |
2978 | add_insn_after (insn, after); | |
2979 | after = insn; | |
2980 | } | |
a3770a81 | 2981 | if (!ggc_p && XVECLEN (pattern, 0) < SEQUENCE_RESULT_SIZE) |
23b2ce53 RS |
2982 | sequence_result[XVECLEN (pattern, 0)] = pattern; |
2983 | } | |
2984 | else | |
2985 | { | |
4b1f5e8c | 2986 | insn = make_insn_raw (pattern); |
23b2ce53 RS |
2987 | add_insn_after (insn, after); |
2988 | } | |
2989 | ||
2990 | return insn; | |
2991 | } | |
2992 | ||
255680cf RK |
2993 | /* Similar to emit_insn_after, except that line notes are to be inserted so |
2994 | as to act as if this insn were at FROM. */ | |
2995 | ||
2996 | void | |
2997 | emit_insn_after_with_line_notes (pattern, after, from) | |
2998 | rtx pattern, after, from; | |
2999 | { | |
3000 | rtx from_line = find_line_note (from); | |
3001 | rtx after_line = find_line_note (after); | |
3002 | rtx insn = emit_insn_after (pattern, after); | |
3003 | ||
3004 | if (from_line) | |
3005 | emit_line_note_after (NOTE_SOURCE_FILE (from_line), | |
3006 | NOTE_LINE_NUMBER (from_line), | |
3007 | after); | |
3008 | ||
3009 | if (after_line) | |
3010 | emit_line_note_after (NOTE_SOURCE_FILE (after_line), | |
3011 | NOTE_LINE_NUMBER (after_line), | |
3012 | insn); | |
3013 | } | |
3014 | ||
a05924f9 JH |
3015 | /* Similar to emit_insn_after, but update basic block boundaries as well. */ |
3016 | ||
3017 | rtx | |
3018 | emit_block_insn_after (pattern, after, block) | |
3019 | rtx pattern, after; | |
3020 | basic_block block; | |
3021 | { | |
3022 | rtx r = emit_insn_after (pattern, after); | |
3023 | if (block && block->end == after) | |
3024 | block->end = r; | |
3025 | return r; | |
3026 | } | |
3027 | ||
23b2ce53 RS |
3028 | /* Make an insn of code JUMP_INSN with body PATTERN |
3029 | and output it after the insn AFTER. */ | |
3030 | ||
3031 | rtx | |
3032 | emit_jump_insn_after (pattern, after) | |
3033 | register rtx pattern, after; | |
3034 | { | |
3035 | register rtx insn; | |
3036 | ||
3037 | if (GET_CODE (pattern) == SEQUENCE) | |
3038 | insn = emit_insn_after (pattern, after); | |
3039 | else | |
3040 | { | |
85cf32bc | 3041 | insn = make_jump_insn_raw (pattern); |
23b2ce53 RS |
3042 | add_insn_after (insn, after); |
3043 | } | |
3044 | ||
3045 | return insn; | |
3046 | } | |
3047 | ||
3048 | /* Make an insn of code BARRIER | |
3049 | and output it after the insn AFTER. */ | |
3050 | ||
3051 | rtx | |
3052 | emit_barrier_after (after) | |
3053 | register rtx after; | |
3054 | { | |
3055 | register rtx insn = rtx_alloc (BARRIER); | |
3056 | ||
3057 | INSN_UID (insn) = cur_insn_uid++; | |
3058 | ||
3059 | add_insn_after (insn, after); | |
3060 | return insn; | |
3061 | } | |
3062 | ||
3063 | /* Emit the label LABEL after the insn AFTER. */ | |
3064 | ||
3065 | rtx | |
3066 | emit_label_after (label, after) | |
3067 | rtx label, after; | |
3068 | { | |
3069 | /* This can be called twice for the same label | |
3070 | as a result of the confusion that follows a syntax error! | |
3071 | So make it harmless. */ | |
3072 | if (INSN_UID (label) == 0) | |
3073 | { | |
3074 | INSN_UID (label) = cur_insn_uid++; | |
3075 | add_insn_after (label, after); | |
3076 | } | |
3077 | ||
3078 | return label; | |
3079 | } | |
3080 | ||
3081 | /* Emit a note of subtype SUBTYPE after the insn AFTER. */ | |
3082 | ||
3083 | rtx | |
3084 | emit_note_after (subtype, after) | |
3085 | int subtype; | |
3086 | rtx after; | |
3087 | { | |
3088 | register rtx note = rtx_alloc (NOTE); | |
3089 | INSN_UID (note) = cur_insn_uid++; | |
3090 | NOTE_SOURCE_FILE (note) = 0; | |
3091 | NOTE_LINE_NUMBER (note) = subtype; | |
3092 | add_insn_after (note, after); | |
3093 | return note; | |
3094 | } | |
3095 | ||
3096 | /* Emit a line note for FILE and LINE after the insn AFTER. */ | |
3097 | ||
3098 | rtx | |
3099 | emit_line_note_after (file, line, after) | |
3cce094d | 3100 | const char *file; |
23b2ce53 RS |
3101 | int line; |
3102 | rtx after; | |
3103 | { | |
3104 | register rtx note; | |
3105 | ||
3106 | if (no_line_numbers && line > 0) | |
3107 | { | |
3108 | cur_insn_uid++; | |
3109 | return 0; | |
3110 | } | |
3111 | ||
3112 | note = rtx_alloc (NOTE); | |
3113 | INSN_UID (note) = cur_insn_uid++; | |
3114 | NOTE_SOURCE_FILE (note) = file; | |
3115 | NOTE_LINE_NUMBER (note) = line; | |
3116 | add_insn_after (note, after); | |
3117 | return note; | |
3118 | } | |
3119 | \f | |
3120 | /* Make an insn of code INSN with pattern PATTERN | |
3121 | and add it to the end of the doubly-linked list. | |
3122 | If PATTERN is a SEQUENCE, take the elements of it | |
3123 | and emit an insn for each element. | |
3124 | ||
3125 | Returns the last insn emitted. */ | |
3126 | ||
3127 | rtx | |
3128 | emit_insn (pattern) | |
3129 | rtx pattern; | |
3130 | { | |
3131 | rtx insn = last_insn; | |
3132 | ||
3133 | if (GET_CODE (pattern) == SEQUENCE) | |
3134 | { | |
3135 | register int i; | |
3136 | ||
3137 | for (i = 0; i < XVECLEN (pattern, 0); i++) | |
3138 | { | |
3139 | insn = XVECEXP (pattern, 0, i); | |
3140 | add_insn (insn); | |
3141 | } | |
a3770a81 | 3142 | if (!ggc_p && XVECLEN (pattern, 0) < SEQUENCE_RESULT_SIZE) |
23b2ce53 RS |
3143 | sequence_result[XVECLEN (pattern, 0)] = pattern; |
3144 | } | |
3145 | else | |
3146 | { | |
4b1f5e8c | 3147 | insn = make_insn_raw (pattern); |
23b2ce53 RS |
3148 | add_insn (insn); |
3149 | } | |
3150 | ||
3151 | return insn; | |
3152 | } | |
3153 | ||
3154 | /* Emit the insns in a chain starting with INSN. | |
3155 | Return the last insn emitted. */ | |
3156 | ||
3157 | rtx | |
3158 | emit_insns (insn) | |
3159 | rtx insn; | |
3160 | { | |
3161 | rtx last = 0; | |
3162 | ||
3163 | while (insn) | |
3164 | { | |
3165 | rtx next = NEXT_INSN (insn); | |
3166 | add_insn (insn); | |
3167 | last = insn; | |
3168 | insn = next; | |
3169 | } | |
3170 | ||
3171 | return last; | |
3172 | } | |
3173 | ||
3174 | /* Emit the insns in a chain starting with INSN and place them in front of | |
3175 | the insn BEFORE. Return the last insn emitted. */ | |
3176 | ||
3177 | rtx | |
3178 | emit_insns_before (insn, before) | |
3179 | rtx insn; | |
3180 | rtx before; | |
3181 | { | |
3182 | rtx last = 0; | |
3183 | ||
3184 | while (insn) | |
3185 | { | |
3186 | rtx next = NEXT_INSN (insn); | |
a0ae8e8d | 3187 | add_insn_before (insn, before); |
23b2ce53 RS |
3188 | last = insn; |
3189 | insn = next; | |
3190 | } | |
3191 | ||
3192 | return last; | |
3193 | } | |
3194 | ||
e0a5c5eb RS |
3195 | /* Emit the insns in a chain starting with FIRST and place them in back of |
3196 | the insn AFTER. Return the last insn emitted. */ | |
3197 | ||
3198 | rtx | |
3199 | emit_insns_after (first, after) | |
3200 | register rtx first; | |
3201 | register rtx after; | |
3202 | { | |
3203 | register rtx last; | |
3204 | register rtx after_after; | |
3205 | ||
3206 | if (!after) | |
3207 | abort (); | |
3208 | ||
3209 | if (!first) | |
3210 | return first; | |
3211 | ||
3212 | for (last = first; NEXT_INSN (last); last = NEXT_INSN (last)) | |
3213 | continue; | |
3214 | ||
3215 | after_after = NEXT_INSN (after); | |
3216 | ||
3217 | NEXT_INSN (after) = first; | |
3218 | PREV_INSN (first) = after; | |
3219 | NEXT_INSN (last) = after_after; | |
3220 | if (after_after) | |
3221 | PREV_INSN (after_after) = last; | |
3222 | ||
c4d990db RS |
3223 | if (after == last_insn) |
3224 | last_insn = last; | |
e0a5c5eb RS |
3225 | return last; |
3226 | } | |
3227 | ||
23b2ce53 RS |
3228 | /* Make an insn of code JUMP_INSN with pattern PATTERN |
3229 | and add it to the end of the doubly-linked list. */ | |
3230 | ||
3231 | rtx | |
3232 | emit_jump_insn (pattern) | |
3233 | rtx pattern; | |
3234 | { | |
3235 | if (GET_CODE (pattern) == SEQUENCE) | |
3236 | return emit_insn (pattern); | |
3237 | else | |
3238 | { | |
85cf32bc | 3239 | register rtx insn = make_jump_insn_raw (pattern); |
23b2ce53 RS |
3240 | add_insn (insn); |
3241 | return insn; | |
3242 | } | |
3243 | } | |
3244 | ||
3245 | /* Make an insn of code CALL_INSN with pattern PATTERN | |
3246 | and add it to the end of the doubly-linked list. */ | |
3247 | ||
3248 | rtx | |
3249 | emit_call_insn (pattern) | |
3250 | rtx pattern; | |
3251 | { | |
3252 | if (GET_CODE (pattern) == SEQUENCE) | |
3253 | return emit_insn (pattern); | |
3254 | else | |
3255 | { | |
aff507f4 | 3256 | register rtx insn = make_call_insn_raw (pattern); |
23b2ce53 RS |
3257 | add_insn (insn); |
3258 | PUT_CODE (insn, CALL_INSN); | |
3259 | return insn; | |
3260 | } | |
3261 | } | |
3262 | ||
3263 | /* Add the label LABEL to the end of the doubly-linked list. */ | |
3264 | ||
3265 | rtx | |
3266 | emit_label (label) | |
3267 | rtx label; | |
3268 | { | |
3269 | /* This can be called twice for the same label | |
3270 | as a result of the confusion that follows a syntax error! | |
3271 | So make it harmless. */ | |
3272 | if (INSN_UID (label) == 0) | |
3273 | { | |
3274 | INSN_UID (label) = cur_insn_uid++; | |
3275 | add_insn (label); | |
3276 | } | |
3277 | return label; | |
3278 | } | |
3279 | ||
3280 | /* Make an insn of code BARRIER | |
3281 | and add it to the end of the doubly-linked list. */ | |
3282 | ||
3283 | rtx | |
3284 | emit_barrier () | |
3285 | { | |
3286 | register rtx barrier = rtx_alloc (BARRIER); | |
3287 | INSN_UID (barrier) = cur_insn_uid++; | |
3288 | add_insn (barrier); | |
3289 | return barrier; | |
3290 | } | |
3291 | ||
3292 | /* Make an insn of code NOTE | |
3293 | with data-fields specified by FILE and LINE | |
3294 | and add it to the end of the doubly-linked list, | |
3295 | but only if line-numbers are desired for debugging info. */ | |
3296 | ||
3297 | rtx | |
3298 | emit_line_note (file, line) | |
3cce094d | 3299 | const char *file; |
23b2ce53 RS |
3300 | int line; |
3301 | { | |
3f1d071b | 3302 | set_file_and_line_for_stmt (file, line); |
23b2ce53 RS |
3303 | |
3304 | #if 0 | |
3305 | if (no_line_numbers) | |
3306 | return 0; | |
3307 | #endif | |
3308 | ||
3309 | return emit_note (file, line); | |
3310 | } | |
3311 | ||
3312 | /* Make an insn of code NOTE | |
3313 | with data-fields specified by FILE and LINE | |
3314 | and add it to the end of the doubly-linked list. | |
3315 | If it is a line-number NOTE, omit it if it matches the previous one. */ | |
3316 | ||
3317 | rtx | |
3318 | emit_note (file, line) | |
3cce094d | 3319 | const char *file; |
23b2ce53 RS |
3320 | int line; |
3321 | { | |
3322 | register rtx note; | |
3323 | ||
3324 | if (line > 0) | |
3325 | { | |
3326 | if (file && last_filename && !strcmp (file, last_filename) | |
3327 | && line == last_linenum) | |
3328 | return 0; | |
3329 | last_filename = file; | |
3330 | last_linenum = line; | |
3331 | } | |
3332 | ||
3333 | if (no_line_numbers && line > 0) | |
3334 | { | |
3335 | cur_insn_uid++; | |
3336 | return 0; | |
3337 | } | |
3338 | ||
3339 | note = rtx_alloc (NOTE); | |
3340 | INSN_UID (note) = cur_insn_uid++; | |
3341 | NOTE_SOURCE_FILE (note) = file; | |
3342 | NOTE_LINE_NUMBER (note) = line; | |
3343 | add_insn (note); | |
3344 | return note; | |
3345 | } | |
3346 | ||
fe77a034 | 3347 | /* Emit a NOTE, and don't omit it even if LINE is the previous note. */ |
23b2ce53 RS |
3348 | |
3349 | rtx | |
3350 | emit_line_note_force (file, line) | |
3cce094d | 3351 | const char *file; |
23b2ce53 RS |
3352 | int line; |
3353 | { | |
3354 | last_linenum = -1; | |
3355 | return emit_line_note (file, line); | |
3356 | } | |
3357 | ||
3358 | /* Cause next statement to emit a line note even if the line number | |
3359 | has not changed. This is used at the beginning of a function. */ | |
3360 | ||
3361 | void | |
3362 | force_next_line_note () | |
3363 | { | |
3364 | last_linenum = -1; | |
3365 | } | |
87b47c85 AM |
3366 | |
3367 | /* Place a note of KIND on insn INSN with DATUM as the datum. If a | |
3368 | note of this type already exists, remove it first. */ | |
3369 | ||
3370 | void | |
3371 | set_unique_reg_note (insn, kind, datum) | |
3372 | rtx insn; | |
3373 | enum reg_note kind; | |
3374 | rtx datum; | |
3375 | { | |
3376 | rtx note = find_reg_note (insn, kind, NULL_RTX); | |
3377 | ||
3378 | /* First remove the note if there already is one. */ | |
3379 | if (note) | |
3380 | remove_note (insn, note); | |
3381 | ||
3382 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (kind, datum, REG_NOTES (insn)); | |
3383 | } | |
23b2ce53 RS |
3384 | \f |
3385 | /* Return an indication of which type of insn should have X as a body. | |
3386 | The value is CODE_LABEL, INSN, CALL_INSN or JUMP_INSN. */ | |
3387 | ||
3388 | enum rtx_code | |
3389 | classify_insn (x) | |
3390 | rtx x; | |
3391 | { | |
3392 | if (GET_CODE (x) == CODE_LABEL) | |
3393 | return CODE_LABEL; | |
3394 | if (GET_CODE (x) == CALL) | |
3395 | return CALL_INSN; | |
3396 | if (GET_CODE (x) == RETURN) | |
3397 | return JUMP_INSN; | |
3398 | if (GET_CODE (x) == SET) | |
3399 | { | |
3400 | if (SET_DEST (x) == pc_rtx) | |
3401 | return JUMP_INSN; | |
3402 | else if (GET_CODE (SET_SRC (x)) == CALL) | |
3403 | return CALL_INSN; | |
3404 | else | |
3405 | return INSN; | |
3406 | } | |
3407 | if (GET_CODE (x) == PARALLEL) | |
3408 | { | |
3409 | register int j; | |
3410 | for (j = XVECLEN (x, 0) - 1; j >= 0; j--) | |
3411 | if (GET_CODE (XVECEXP (x, 0, j)) == CALL) | |
3412 | return CALL_INSN; | |
3413 | else if (GET_CODE (XVECEXP (x, 0, j)) == SET | |
3414 | && SET_DEST (XVECEXP (x, 0, j)) == pc_rtx) | |
3415 | return JUMP_INSN; | |
3416 | else if (GET_CODE (XVECEXP (x, 0, j)) == SET | |
3417 | && GET_CODE (SET_SRC (XVECEXP (x, 0, j))) == CALL) | |
3418 | return CALL_INSN; | |
3419 | } | |
3420 | return INSN; | |
3421 | } | |
3422 | ||
3423 | /* Emit the rtl pattern X as an appropriate kind of insn. | |
3424 | If X is a label, it is simply added into the insn chain. */ | |
3425 | ||
3426 | rtx | |
3427 | emit (x) | |
3428 | rtx x; | |
3429 | { | |
3430 | enum rtx_code code = classify_insn (x); | |
3431 | ||
3432 | if (code == CODE_LABEL) | |
3433 | return emit_label (x); | |
3434 | else if (code == INSN) | |
3435 | return emit_insn (x); | |
3436 | else if (code == JUMP_INSN) | |
3437 | { | |
3438 | register rtx insn = emit_jump_insn (x); | |
3439 | if (simplejump_p (insn) || GET_CODE (x) == RETURN) | |
3440 | return emit_barrier (); | |
3441 | return insn; | |
3442 | } | |
3443 | else if (code == CALL_INSN) | |
3444 | return emit_call_insn (x); | |
3445 | else | |
3446 | abort (); | |
3447 | } | |
3448 | \f | |
5c7a310f MM |
3449 | /* Begin emitting insns to a sequence which can be packaged in an |
3450 | RTL_EXPR. If this sequence will contain something that might cause | |
3451 | the compiler to pop arguments to function calls (because those | |
3452 | pops have previously been deferred; see INHIBIT_DEFER_POP for more | |
3453 | details), use do_pending_stack_adjust before calling this function. | |
3454 | That will ensure that the deferred pops are not accidentally | |
3455 | emitted in the middel of this sequence. */ | |
23b2ce53 RS |
3456 | |
3457 | void | |
3458 | start_sequence () | |
3459 | { | |
3460 | struct sequence_stack *tem; | |
3461 | ||
a3770a81 | 3462 | tem = (struct sequence_stack *) xmalloc (sizeof (struct sequence_stack)); |
23b2ce53 | 3463 | |
49ad7cfa | 3464 | tem->next = seq_stack; |
23b2ce53 RS |
3465 | tem->first = first_insn; |
3466 | tem->last = last_insn; | |
591ccf92 | 3467 | tem->sequence_rtl_expr = seq_rtl_expr; |
23b2ce53 | 3468 | |
49ad7cfa | 3469 | seq_stack = tem; |
23b2ce53 RS |
3470 | |
3471 | first_insn = 0; | |
3472 | last_insn = 0; | |
3473 | } | |
3474 | ||
591ccf92 MM |
3475 | /* Similarly, but indicate that this sequence will be placed in T, an |
3476 | RTL_EXPR. See the documentation for start_sequence for more | |
3477 | information about how to use this function. */ | |
3478 | ||
3479 | void | |
3480 | start_sequence_for_rtl_expr (t) | |
3481 | tree t; | |
3482 | { | |
3483 | start_sequence (); | |
3484 | ||
3485 | seq_rtl_expr = t; | |
3486 | } | |
3487 | ||
5c7a310f MM |
3488 | /* Set up the insn chain starting with FIRST as the current sequence, |
3489 | saving the previously current one. See the documentation for | |
3490 | start_sequence for more information about how to use this function. */ | |
23b2ce53 RS |
3491 | |
3492 | void | |
3493 | push_to_sequence (first) | |
3494 | rtx first; | |
3495 | { | |
3496 | rtx last; | |
3497 | ||
3498 | start_sequence (); | |
3499 | ||
3500 | for (last = first; last && NEXT_INSN (last); last = NEXT_INSN (last)); | |
3501 | ||
3502 | first_insn = first; | |
3503 | last_insn = last; | |
3504 | } | |
3505 | ||
c14f7160 ML |
3506 | /* Set up the insn chain from a chain stort in FIRST to LAST. */ |
3507 | ||
3508 | void | |
3509 | push_to_full_sequence (first, last) | |
3510 | rtx first, last; | |
3511 | { | |
3512 | start_sequence (); | |
3513 | first_insn = first; | |
3514 | last_insn = last; | |
3515 | /* We really should have the end of the insn chain here. */ | |
3516 | if (last && NEXT_INSN (last)) | |
3517 | abort (); | |
3518 | } | |
3519 | ||
f15ae3a1 TW |
3520 | /* Set up the outer-level insn chain |
3521 | as the current sequence, saving the previously current one. */ | |
3522 | ||
3523 | void | |
3524 | push_topmost_sequence () | |
3525 | { | |
aefdd5ab | 3526 | struct sequence_stack *stack, *top = NULL; |
f15ae3a1 TW |
3527 | |
3528 | start_sequence (); | |
3529 | ||
49ad7cfa | 3530 | for (stack = seq_stack; stack; stack = stack->next) |
f15ae3a1 TW |
3531 | top = stack; |
3532 | ||
3533 | first_insn = top->first; | |
3534 | last_insn = top->last; | |
591ccf92 | 3535 | seq_rtl_expr = top->sequence_rtl_expr; |
f15ae3a1 TW |
3536 | } |
3537 | ||
3538 | /* After emitting to the outer-level insn chain, update the outer-level | |
3539 | insn chain, and restore the previous saved state. */ | |
3540 | ||
3541 | void | |
3542 | pop_topmost_sequence () | |
3543 | { | |
aefdd5ab | 3544 | struct sequence_stack *stack, *top = NULL; |
f15ae3a1 | 3545 | |
49ad7cfa | 3546 | for (stack = seq_stack; stack; stack = stack->next) |
f15ae3a1 TW |
3547 | top = stack; |
3548 | ||
3549 | top->first = first_insn; | |
3550 | top->last = last_insn; | |
591ccf92 | 3551 | /* ??? Why don't we save seq_rtl_expr here? */ |
f15ae3a1 TW |
3552 | |
3553 | end_sequence (); | |
3554 | } | |
3555 | ||
23b2ce53 RS |
3556 | /* After emitting to a sequence, restore previous saved state. |
3557 | ||
5c7a310f MM |
3558 | To get the contents of the sequence just made, you must call |
3559 | `gen_sequence' *before* calling here. | |
3560 | ||
3561 | If the compiler might have deferred popping arguments while | |
3562 | generating this sequence, and this sequence will not be immediately | |
3563 | inserted into the instruction stream, use do_pending_stack_adjust | |
3564 | before calling gen_sequence. That will ensure that the deferred | |
3565 | pops are inserted into this sequence, and not into some random | |
3566 | location in the instruction stream. See INHIBIT_DEFER_POP for more | |
3567 | information about deferred popping of arguments. */ | |
23b2ce53 RS |
3568 | |
3569 | void | |
3570 | end_sequence () | |
3571 | { | |
49ad7cfa | 3572 | struct sequence_stack *tem = seq_stack; |
23b2ce53 RS |
3573 | |
3574 | first_insn = tem->first; | |
3575 | last_insn = tem->last; | |
591ccf92 | 3576 | seq_rtl_expr = tem->sequence_rtl_expr; |
49ad7cfa | 3577 | seq_stack = tem->next; |
23b2ce53 | 3578 | |
a3770a81 | 3579 | free (tem); |
23b2ce53 RS |
3580 | } |
3581 | ||
c14f7160 ML |
3582 | /* This works like end_sequence, but records the old sequence in FIRST |
3583 | and LAST. */ | |
3584 | ||
3585 | void | |
3586 | end_full_sequence (first, last) | |
3587 | rtx *first, *last; | |
3588 | { | |
3589 | *first = first_insn; | |
3590 | *last = last_insn; | |
3591 | end_sequence(); | |
3592 | } | |
3593 | ||
23b2ce53 RS |
3594 | /* Return 1 if currently emitting into a sequence. */ |
3595 | ||
3596 | int | |
3597 | in_sequence_p () | |
3598 | { | |
49ad7cfa | 3599 | return seq_stack != 0; |
23b2ce53 RS |
3600 | } |
3601 | ||
3602 | /* Generate a SEQUENCE rtx containing the insns already emitted | |
3603 | to the current sequence. | |
3604 | ||
3605 | This is how the gen_... function from a DEFINE_EXPAND | |
3606 | constructs the SEQUENCE that it returns. */ | |
3607 | ||
3608 | rtx | |
3609 | gen_sequence () | |
3610 | { | |
3611 | rtx result; | |
3612 | rtx tem; | |
23b2ce53 RS |
3613 | int i; |
3614 | int len; | |
3615 | ||
3616 | /* Count the insns in the chain. */ | |
3617 | len = 0; | |
3618 | for (tem = first_insn; tem; tem = NEXT_INSN (tem)) | |
3619 | len++; | |
3620 | ||
ee265800 | 3621 | /* If only one insn, return it rather than a SEQUENCE. |
23b2ce53 | 3622 | (Now that we cache SEQUENCE expressions, it isn't worth special-casing |
ee265800 AH |
3623 | the case of an empty list.) |
3624 | We only return the pattern of an insn if its code is INSN and it | |
3625 | has no notes. This ensures that no information gets lost. */ | |
23b2ce53 | 3626 | if (len == 1 |
ca55abae | 3627 | && ! RTX_FRAME_RELATED_P (first_insn) |
ee265800 AH |
3628 | && GET_CODE (first_insn) == INSN |
3629 | /* Don't throw away any reg notes. */ | |
3630 | && REG_NOTES (first_insn) == 0) | |
43127294 | 3631 | { |
a3770a81 RH |
3632 | if (!ggc_p) |
3633 | { | |
3634 | NEXT_INSN (first_insn) = free_insn; | |
3635 | free_insn = first_insn; | |
3636 | } | |
43127294 RK |
3637 | return PATTERN (first_insn); |
3638 | } | |
23b2ce53 RS |
3639 | |
3640 | /* Put them in a vector. See if we already have a SEQUENCE of the | |
3641 | appropriate length around. */ | |
a3770a81 RH |
3642 | if (!ggc_p && len < SEQUENCE_RESULT_SIZE |
3643 | && (result = sequence_result[len]) != 0) | |
23b2ce53 RS |
3644 | sequence_result[len] = 0; |
3645 | else | |
3646 | { | |
9faa82d8 RK |
3647 | /* Ensure that this rtl goes in saveable_obstack, since we may |
3648 | cache it. */ | |
d508ebba JW |
3649 | push_obstacks_nochange (); |
3650 | rtl_in_saveable_obstack (); | |
3b80f6ca | 3651 | result = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (len)); |
d508ebba | 3652 | pop_obstacks (); |
23b2ce53 RS |
3653 | } |
3654 | ||
3655 | for (i = 0, tem = first_insn; tem; tem = NEXT_INSN (tem), i++) | |
3656 | XVECEXP (result, 0, i) = tem; | |
3657 | ||
3658 | return result; | |
3659 | } | |
3660 | \f | |
59ec66dc MM |
3661 | /* Put the various virtual registers into REGNO_REG_RTX. */ |
3662 | ||
3663 | void | |
49ad7cfa BS |
3664 | init_virtual_regs (es) |
3665 | struct emit_status *es; | |
59ec66dc | 3666 | { |
49ad7cfa BS |
3667 | rtx *ptr = es->x_regno_reg_rtx; |
3668 | ptr[VIRTUAL_INCOMING_ARGS_REGNUM] = virtual_incoming_args_rtx; | |
3669 | ptr[VIRTUAL_STACK_VARS_REGNUM] = virtual_stack_vars_rtx; | |
3670 | ptr[VIRTUAL_STACK_DYNAMIC_REGNUM] = virtual_stack_dynamic_rtx; | |
3671 | ptr[VIRTUAL_OUTGOING_ARGS_REGNUM] = virtual_outgoing_args_rtx; | |
3672 | ptr[VIRTUAL_CFA_REGNUM] = virtual_cfa_rtx; | |
3673 | } | |
3674 | ||
3675 | void | |
3676 | clear_emit_caches () | |
3677 | { | |
3678 | int i; | |
3679 | ||
3680 | /* Clear the start_sequence/gen_sequence cache. */ | |
49ad7cfa BS |
3681 | for (i = 0; i < SEQUENCE_RESULT_SIZE; i++) |
3682 | sequence_result[i] = 0; | |
3683 | free_insn = 0; | |
59ec66dc | 3684 | } |
da43a810 BS |
3685 | \f |
3686 | /* Used by copy_insn_1 to avoid copying SCRATCHes more than once. */ | |
3687 | static rtx copy_insn_scratch_in[MAX_RECOG_OPERANDS]; | |
3688 | static rtx copy_insn_scratch_out[MAX_RECOG_OPERANDS]; | |
3689 | static int copy_insn_n_scratches; | |
3690 | ||
3691 | /* When an insn is being copied by copy_insn_1, this is nonzero if we have | |
3692 | copied an ASM_OPERANDS. | |
3693 | In that case, it is the original input-operand vector. */ | |
3694 | static rtvec orig_asm_operands_vector; | |
3695 | ||
3696 | /* When an insn is being copied by copy_insn_1, this is nonzero if we have | |
3697 | copied an ASM_OPERANDS. | |
3698 | In that case, it is the copied input-operand vector. */ | |
3699 | static rtvec copy_asm_operands_vector; | |
3700 | ||
3701 | /* Likewise for the constraints vector. */ | |
3702 | static rtvec orig_asm_constraints_vector; | |
3703 | static rtvec copy_asm_constraints_vector; | |
3704 | ||
3705 | /* Recursively create a new copy of an rtx for copy_insn. | |
3706 | This function differs from copy_rtx in that it handles SCRATCHes and | |
3707 | ASM_OPERANDs properly. | |
3708 | Normally, this function is not used directly; use copy_insn as front end. | |
3709 | However, you could first copy an insn pattern with copy_insn and then use | |
3710 | this function afterwards to properly copy any REG_NOTEs containing | |
3711 | SCRATCHes. */ | |
3712 | ||
3713 | rtx | |
3714 | copy_insn_1 (orig) | |
3715 | register rtx orig; | |
3716 | { | |
3717 | register rtx copy; | |
3718 | register int i, j; | |
3719 | register RTX_CODE code; | |
4724334a | 3720 | register const char *format_ptr; |
da43a810 BS |
3721 | |
3722 | code = GET_CODE (orig); | |
3723 | ||
3724 | switch (code) | |
3725 | { | |
3726 | case REG: | |
3727 | case QUEUED: | |
3728 | case CONST_INT: | |
3729 | case CONST_DOUBLE: | |
3730 | case SYMBOL_REF: | |
3731 | case CODE_LABEL: | |
3732 | case PC: | |
3733 | case CC0: | |
3734 | case ADDRESSOF: | |
3735 | return orig; | |
3736 | ||
3737 | case SCRATCH: | |
3738 | for (i = 0; i < copy_insn_n_scratches; i++) | |
3739 | if (copy_insn_scratch_in[i] == orig) | |
3740 | return copy_insn_scratch_out[i]; | |
3741 | break; | |
3742 | ||
3743 | case CONST: | |
3744 | /* CONST can be shared if it contains a SYMBOL_REF. If it contains | |
3745 | a LABEL_REF, it isn't sharable. */ | |
3746 | if (GET_CODE (XEXP (orig, 0)) == PLUS | |
3747 | && GET_CODE (XEXP (XEXP (orig, 0), 0)) == SYMBOL_REF | |
3748 | && GET_CODE (XEXP (XEXP (orig, 0), 1)) == CONST_INT) | |
3749 | return orig; | |
3750 | break; | |
3751 | ||
3752 | /* A MEM with a constant address is not sharable. The problem is that | |
3753 | the constant address may need to be reloaded. If the mem is shared, | |
3754 | then reloading one copy of this mem will cause all copies to appear | |
3755 | to have been reloaded. */ | |
3756 | ||
3757 | default: | |
3758 | break; | |
3759 | } | |
3760 | ||
3761 | copy = rtx_alloc (code); | |
3762 | ||
3763 | /* Copy the various flags, and other information. We assume that | |
3764 | all fields need copying, and then clear the fields that should | |
3765 | not be copied. That is the sensible default behavior, and forces | |
3766 | us to explicitly document why we are *not* copying a flag. */ | |
3767 | memcpy (copy, orig, sizeof (struct rtx_def) - sizeof (rtunion)); | |
3768 | ||
3769 | /* We do not copy the USED flag, which is used as a mark bit during | |
3770 | walks over the RTL. */ | |
3771 | copy->used = 0; | |
3772 | ||
3773 | /* We do not copy JUMP, CALL, or FRAME_RELATED for INSNs. */ | |
3774 | if (GET_RTX_CLASS (code) == 'i') | |
3775 | { | |
3776 | copy->jump = 0; | |
3777 | copy->call = 0; | |
3778 | copy->frame_related = 0; | |
3779 | } | |
3780 | ||
3781 | format_ptr = GET_RTX_FORMAT (GET_CODE (copy)); | |
3782 | ||
3783 | for (i = 0; i < GET_RTX_LENGTH (GET_CODE (copy)); i++) | |
3784 | { | |
e63db8f6 | 3785 | copy->fld[i] = orig->fld[i]; |
da43a810 BS |
3786 | switch (*format_ptr++) |
3787 | { | |
3788 | case 'e': | |
da43a810 BS |
3789 | if (XEXP (orig, i) != NULL) |
3790 | XEXP (copy, i) = copy_insn_1 (XEXP (orig, i)); | |
3791 | break; | |
3792 | ||
da43a810 BS |
3793 | case 'E': |
3794 | case 'V': | |
da43a810 BS |
3795 | if (XVEC (orig, i) == orig_asm_constraints_vector) |
3796 | XVEC (copy, i) = copy_asm_constraints_vector; | |
3797 | else if (XVEC (orig, i) == orig_asm_operands_vector) | |
3798 | XVEC (copy, i) = copy_asm_operands_vector; | |
3799 | else if (XVEC (orig, i) != NULL) | |
3800 | { | |
3801 | XVEC (copy, i) = rtvec_alloc (XVECLEN (orig, i)); | |
3802 | for (j = 0; j < XVECLEN (copy, i); j++) | |
3803 | XVECEXP (copy, i, j) = copy_insn_1 (XVECEXP (orig, i, j)); | |
3804 | } | |
3805 | break; | |
3806 | ||
3807 | case 'b': | |
3808 | { | |
3809 | bitmap new_bits = BITMAP_OBSTACK_ALLOC (rtl_obstack); | |
3810 | bitmap_copy (new_bits, XBITMAP (orig, i)); | |
3811 | XBITMAP (copy, i) = new_bits; | |
3812 | break; | |
3813 | } | |
3814 | ||
3815 | case 't': | |
da43a810 | 3816 | case 'w': |
da43a810 | 3817 | case 'i': |
da43a810 BS |
3818 | case 's': |
3819 | case 'S': | |
e63db8f6 BS |
3820 | case 'u': |
3821 | case '0': | |
3822 | /* These are left unchanged. */ | |
da43a810 BS |
3823 | break; |
3824 | ||
3825 | default: | |
3826 | abort (); | |
3827 | } | |
3828 | } | |
3829 | ||
3830 | if (code == SCRATCH) | |
3831 | { | |
3832 | i = copy_insn_n_scratches++; | |
3833 | if (i >= MAX_RECOG_OPERANDS) | |
3834 | abort (); | |
3835 | copy_insn_scratch_in[i] = orig; | |
3836 | copy_insn_scratch_out[i] = copy; | |
3837 | } | |
3838 | else if (code == ASM_OPERANDS) | |
3839 | { | |
3840 | orig_asm_operands_vector = XVEC (orig, 3); | |
3841 | copy_asm_operands_vector = XVEC (copy, 3); | |
3842 | orig_asm_constraints_vector = XVEC (orig, 4); | |
3843 | copy_asm_constraints_vector = XVEC (copy, 4); | |
3844 | } | |
3845 | ||
3846 | return copy; | |
3847 | } | |
3848 | ||
3849 | /* Create a new copy of an rtx. | |
3850 | This function differs from copy_rtx in that it handles SCRATCHes and | |
3851 | ASM_OPERANDs properly. | |
3852 | INSN doesn't really have to be a full INSN; it could be just the | |
3853 | pattern. */ | |
3854 | rtx | |
3855 | copy_insn (insn) | |
3856 | rtx insn; | |
3857 | { | |
3858 | copy_insn_n_scratches = 0; | |
3859 | orig_asm_operands_vector = 0; | |
3860 | orig_asm_constraints_vector = 0; | |
3861 | copy_asm_operands_vector = 0; | |
3862 | copy_asm_constraints_vector = 0; | |
3863 | return copy_insn_1 (insn); | |
3864 | } | |
59ec66dc | 3865 | |
23b2ce53 RS |
3866 | /* Initialize data structures and variables in this file |
3867 | before generating rtl for each function. */ | |
3868 | ||
3869 | void | |
3870 | init_emit () | |
3871 | { | |
01d939e8 | 3872 | struct function *f = cfun; |
23b2ce53 | 3873 | |
49ad7cfa | 3874 | f->emit = (struct emit_status *) xmalloc (sizeof (struct emit_status)); |
23b2ce53 RS |
3875 | first_insn = NULL; |
3876 | last_insn = NULL; | |
591ccf92 | 3877 | seq_rtl_expr = NULL; |
23b2ce53 RS |
3878 | cur_insn_uid = 1; |
3879 | reg_rtx_no = LAST_VIRTUAL_REGISTER + 1; | |
3880 | last_linenum = 0; | |
3881 | last_filename = 0; | |
3882 | first_label_num = label_num; | |
3883 | last_label_num = 0; | |
49ad7cfa | 3884 | seq_stack = NULL; |
23b2ce53 | 3885 | |
49ad7cfa | 3886 | clear_emit_caches (); |
23b2ce53 RS |
3887 | |
3888 | /* Init the tables that describe all the pseudo regs. */ | |
3889 | ||
49ad7cfa | 3890 | f->emit->regno_pointer_flag_length = LAST_VIRTUAL_REGISTER + 101; |
23b2ce53 | 3891 | |
49ad7cfa | 3892 | f->emit->regno_pointer_flag |
a3770a81 | 3893 | = (char *) xcalloc (f->emit->regno_pointer_flag_length, sizeof (char)); |
23b2ce53 | 3894 | |
49ad7cfa | 3895 | f->emit->regno_pointer_align |
a3770a81 RH |
3896 | = (char *) xcalloc (f->emit->regno_pointer_flag_length, |
3897 | sizeof (char)); | |
86fe05e0 | 3898 | |
23b2ce53 | 3899 | regno_reg_rtx |
a3770a81 RH |
3900 | = (rtx *) xcalloc (f->emit->regno_pointer_flag_length * sizeof (rtx), |
3901 | sizeof (rtx)); | |
23b2ce53 RS |
3902 | |
3903 | /* Put copies of all the virtual register rtx into regno_reg_rtx. */ | |
49ad7cfa | 3904 | init_virtual_regs (f->emit); |
740ab4a2 RK |
3905 | |
3906 | /* Indicate that the virtual registers and stack locations are | |
3907 | all pointers. */ | |
3908 | REGNO_POINTER_FLAG (STACK_POINTER_REGNUM) = 1; | |
3909 | REGNO_POINTER_FLAG (FRAME_POINTER_REGNUM) = 1; | |
15c9248c | 3910 | REGNO_POINTER_FLAG (HARD_FRAME_POINTER_REGNUM) = 1; |
740ab4a2 RK |
3911 | REGNO_POINTER_FLAG (ARG_POINTER_REGNUM) = 1; |
3912 | ||
3913 | REGNO_POINTER_FLAG (VIRTUAL_INCOMING_ARGS_REGNUM) = 1; | |
3914 | REGNO_POINTER_FLAG (VIRTUAL_STACK_VARS_REGNUM) = 1; | |
3915 | REGNO_POINTER_FLAG (VIRTUAL_STACK_DYNAMIC_REGNUM) = 1; | |
3916 | REGNO_POINTER_FLAG (VIRTUAL_OUTGOING_ARGS_REGNUM) = 1; | |
71038426 | 3917 | REGNO_POINTER_FLAG (VIRTUAL_CFA_REGNUM) = 1; |
5e82e7bd | 3918 | |
86fe05e0 | 3919 | #ifdef STACK_BOUNDARY |
bdb429a5 RK |
3920 | REGNO_POINTER_ALIGN (STACK_POINTER_REGNUM) = STACK_BOUNDARY; |
3921 | REGNO_POINTER_ALIGN (FRAME_POINTER_REGNUM) = STACK_BOUNDARY; | |
3922 | REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = STACK_BOUNDARY; | |
3923 | REGNO_POINTER_ALIGN (ARG_POINTER_REGNUM) = STACK_BOUNDARY; | |
3924 | ||
3925 | REGNO_POINTER_ALIGN (VIRTUAL_INCOMING_ARGS_REGNUM) = STACK_BOUNDARY; | |
3926 | REGNO_POINTER_ALIGN (VIRTUAL_STACK_VARS_REGNUM) = STACK_BOUNDARY; | |
3927 | REGNO_POINTER_ALIGN (VIRTUAL_STACK_DYNAMIC_REGNUM) = STACK_BOUNDARY; | |
3928 | REGNO_POINTER_ALIGN (VIRTUAL_OUTGOING_ARGS_REGNUM) = STACK_BOUNDARY; | |
3929 | REGNO_POINTER_ALIGN (VIRTUAL_CFA_REGNUM) = BITS_PER_WORD; | |
86fe05e0 RK |
3930 | #endif |
3931 | ||
5e82e7bd JVA |
3932 | #ifdef INIT_EXPANDERS |
3933 | INIT_EXPANDERS; | |
3934 | #endif | |
23b2ce53 RS |
3935 | } |
3936 | ||
87ff9c8e RH |
3937 | /* Mark SS for GC. */ |
3938 | ||
3939 | static void | |
3940 | mark_sequence_stack (ss) | |
3941 | struct sequence_stack *ss; | |
3942 | { | |
3943 | while (ss) | |
3944 | { | |
3945 | ggc_mark_rtx (ss->first); | |
591ccf92 | 3946 | ggc_mark_tree (ss->sequence_rtl_expr); |
87ff9c8e RH |
3947 | ss = ss->next; |
3948 | } | |
3949 | } | |
3950 | ||
3951 | /* Mark ES for GC. */ | |
3952 | ||
3953 | void | |
fa51b01b | 3954 | mark_emit_status (es) |
87ff9c8e RH |
3955 | struct emit_status *es; |
3956 | { | |
3957 | rtx *r; | |
3958 | int i; | |
3959 | ||
3960 | if (es == 0) | |
3961 | return; | |
3962 | ||
3963 | for (i = es->regno_pointer_flag_length, r = es->x_regno_reg_rtx; | |
3964 | i > 0; --i, ++r) | |
3965 | ggc_mark_rtx (*r); | |
3966 | ||
3967 | mark_sequence_stack (es->sequence_stack); | |
591ccf92 | 3968 | ggc_mark_tree (es->sequence_rtl_expr); |
87ff9c8e RH |
3969 | ggc_mark_rtx (es->x_first_insn); |
3970 | } | |
3971 | ||
23b2ce53 RS |
3972 | /* Create some permanent unique rtl objects shared between all functions. |
3973 | LINE_NUMBERS is nonzero if line numbers are to be generated. */ | |
3974 | ||
3975 | void | |
3976 | init_emit_once (line_numbers) | |
3977 | int line_numbers; | |
3978 | { | |
3979 | int i; | |
3980 | enum machine_mode mode; | |
9ec36da5 | 3981 | enum machine_mode double_mode; |
23b2ce53 RS |
3982 | |
3983 | no_line_numbers = ! line_numbers; | |
3984 | ||
43fa6302 AS |
3985 | /* Compute the word and byte modes. */ |
3986 | ||
3987 | byte_mode = VOIDmode; | |
3988 | word_mode = VOIDmode; | |
3989 | double_mode = VOIDmode; | |
3990 | ||
3991 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT); mode != VOIDmode; | |
3992 | mode = GET_MODE_WIDER_MODE (mode)) | |
3993 | { | |
3994 | if (GET_MODE_BITSIZE (mode) == BITS_PER_UNIT | |
3995 | && byte_mode == VOIDmode) | |
3996 | byte_mode = mode; | |
3997 | ||
3998 | if (GET_MODE_BITSIZE (mode) == BITS_PER_WORD | |
3999 | && word_mode == VOIDmode) | |
4000 | word_mode = mode; | |
4001 | } | |
4002 | ||
4003 | #ifndef DOUBLE_TYPE_SIZE | |
4004 | #define DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2) | |
4005 | #endif | |
4006 | ||
4007 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_FLOAT); mode != VOIDmode; | |
4008 | mode = GET_MODE_WIDER_MODE (mode)) | |
4009 | { | |
4010 | if (GET_MODE_BITSIZE (mode) == DOUBLE_TYPE_SIZE | |
4011 | && double_mode == VOIDmode) | |
4012 | double_mode = mode; | |
4013 | } | |
4014 | ||
4015 | ptr_mode = mode_for_size (POINTER_SIZE, GET_MODE_CLASS (Pmode), 0); | |
4016 | ||
5da077de AS |
4017 | /* Assign register numbers to the globally defined register rtx. |
4018 | This must be done at runtime because the register number field | |
4019 | is in a union and some compilers can't initialize unions. */ | |
4020 | ||
4021 | pc_rtx = gen_rtx (PC, VOIDmode); | |
4022 | cc0_rtx = gen_rtx (CC0, VOIDmode); | |
4023 | stack_pointer_rtx = gen_rtx_raw_REG (Pmode, STACK_POINTER_REGNUM); | |
4024 | frame_pointer_rtx = gen_rtx_raw_REG (Pmode, FRAME_POINTER_REGNUM); | |
4025 | if (hard_frame_pointer_rtx == 0) | |
4026 | hard_frame_pointer_rtx = gen_rtx_raw_REG (Pmode, | |
4027 | HARD_FRAME_POINTER_REGNUM); | |
4028 | if (arg_pointer_rtx == 0) | |
4029 | arg_pointer_rtx = gen_rtx_raw_REG (Pmode, ARG_POINTER_REGNUM); | |
4030 | virtual_incoming_args_rtx = | |
4031 | gen_rtx_raw_REG (Pmode, VIRTUAL_INCOMING_ARGS_REGNUM); | |
4032 | virtual_stack_vars_rtx = | |
4033 | gen_rtx_raw_REG (Pmode, VIRTUAL_STACK_VARS_REGNUM); | |
4034 | virtual_stack_dynamic_rtx = | |
4035 | gen_rtx_raw_REG (Pmode, VIRTUAL_STACK_DYNAMIC_REGNUM); | |
4036 | virtual_outgoing_args_rtx = | |
4037 | gen_rtx_raw_REG (Pmode, VIRTUAL_OUTGOING_ARGS_REGNUM); | |
4038 | virtual_cfa_rtx = gen_rtx_raw_REG (Pmode, VIRTUAL_CFA_REGNUM); | |
4039 | ||
4040 | /* These rtx must be roots if GC is enabled. */ | |
4041 | if (ggc_p) | |
4042 | ggc_add_rtx_root (global_rtl, GR_MAX); | |
4043 | ||
5da077de AS |
4044 | #ifdef INIT_EXPANDERS |
4045 | /* This is to initialize save_machine_status and restore_machine_status before | |
4046 | the first call to push_function_context_to. This is needed by the Chill | |
4047 | front end which calls push_function_context_to before the first cal to | |
4048 | init_function_start. */ | |
4049 | INIT_EXPANDERS; | |
4050 | #endif | |
4051 | ||
23b2ce53 RS |
4052 | /* Create the unique rtx's for certain rtx codes and operand values. */ |
4053 | ||
c5c76735 JL |
4054 | /* Don't use gen_rtx here since gen_rtx in this case |
4055 | tries to use these variables. */ | |
23b2ce53 | 4056 | for (i = - MAX_SAVED_CONST_INT; i <= MAX_SAVED_CONST_INT; i++) |
5da077de AS |
4057 | const_int_rtx[i + MAX_SAVED_CONST_INT] = |
4058 | gen_rtx_raw_CONST_INT (VOIDmode, i); | |
4059 | if (ggc_p) | |
4060 | ggc_add_rtx_root (const_int_rtx, 2 * MAX_SAVED_CONST_INT + 1); | |
23b2ce53 | 4061 | |
68d75312 JC |
4062 | if (STORE_FLAG_VALUE >= - MAX_SAVED_CONST_INT |
4063 | && STORE_FLAG_VALUE <= MAX_SAVED_CONST_INT) | |
5da077de | 4064 | const_true_rtx = const_int_rtx[STORE_FLAG_VALUE + MAX_SAVED_CONST_INT]; |
68d75312 | 4065 | else |
3b80f6ca | 4066 | const_true_rtx = gen_rtx_CONST_INT (VOIDmode, STORE_FLAG_VALUE); |
23b2ce53 | 4067 | |
9ec36da5 JL |
4068 | dconst0 = REAL_VALUE_ATOF ("0", double_mode); |
4069 | dconst1 = REAL_VALUE_ATOF ("1", double_mode); | |
4070 | dconst2 = REAL_VALUE_ATOF ("2", double_mode); | |
4071 | dconstm1 = REAL_VALUE_ATOF ("-1", double_mode); | |
23b2ce53 RS |
4072 | |
4073 | for (i = 0; i <= 2; i++) | |
4074 | { | |
4075 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_FLOAT); mode != VOIDmode; | |
4076 | mode = GET_MODE_WIDER_MODE (mode)) | |
4077 | { | |
4078 | rtx tem = rtx_alloc (CONST_DOUBLE); | |
4079 | union real_extract u; | |
4080 | ||
4c9a05bc | 4081 | bzero ((char *) &u, sizeof u); /* Zero any holes in a structure. */ |
23b2ce53 RS |
4082 | u.d = i == 0 ? dconst0 : i == 1 ? dconst1 : dconst2; |
4083 | ||
4c9a05bc | 4084 | bcopy ((char *) &u, (char *) &CONST_DOUBLE_LOW (tem), sizeof u); |
23b2ce53 RS |
4085 | CONST_DOUBLE_MEM (tem) = cc0_rtx; |
4086 | PUT_MODE (tem, mode); | |
4087 | ||
4088 | const_tiny_rtx[i][(int) mode] = tem; | |
4089 | } | |
4090 | ||
906c4e36 | 4091 | const_tiny_rtx[i][(int) VOIDmode] = GEN_INT (i); |
23b2ce53 RS |
4092 | |
4093 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT); mode != VOIDmode; | |
4094 | mode = GET_MODE_WIDER_MODE (mode)) | |
906c4e36 | 4095 | const_tiny_rtx[i][(int) mode] = GEN_INT (i); |
33d3e559 RS |
4096 | |
4097 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_PARTIAL_INT); | |
4098 | mode != VOIDmode; | |
4099 | mode = GET_MODE_WIDER_MODE (mode)) | |
4100 | const_tiny_rtx[i][(int) mode] = GEN_INT (i); | |
23b2ce53 RS |
4101 | } |
4102 | ||
aea87e88 RH |
4103 | for (mode = CCmode; mode < MAX_MACHINE_MODE; ++mode) |
4104 | if (GET_MODE_CLASS (mode) == MODE_CC) | |
4105 | const_tiny_rtx[0][(int) mode] = const0_rtx; | |
23b2ce53 | 4106 | |
d7db6646 | 4107 | ggc_add_rtx_root (&const_tiny_rtx[0][0], sizeof(const_tiny_rtx)/sizeof(rtx)); |
21cd906e | 4108 | ggc_add_rtx_root (&const_true_rtx, 1); |
a7e1e2ac AO |
4109 | |
4110 | #ifdef RETURN_ADDRESS_POINTER_REGNUM | |
4111 | return_address_pointer_rtx | |
4112 | = gen_rtx_raw_REG (Pmode, RETURN_ADDRESS_POINTER_REGNUM); | |
4113 | #endif | |
4114 | ||
4115 | #ifdef STRUCT_VALUE | |
4116 | struct_value_rtx = STRUCT_VALUE; | |
4117 | #else | |
4118 | struct_value_rtx = gen_rtx_REG (Pmode, STRUCT_VALUE_REGNUM); | |
4119 | #endif | |
4120 | ||
4121 | #ifdef STRUCT_VALUE_INCOMING | |
4122 | struct_value_incoming_rtx = STRUCT_VALUE_INCOMING; | |
4123 | #else | |
4124 | #ifdef STRUCT_VALUE_INCOMING_REGNUM | |
4125 | struct_value_incoming_rtx | |
4126 | = gen_rtx_REG (Pmode, STRUCT_VALUE_INCOMING_REGNUM); | |
4127 | #else | |
4128 | struct_value_incoming_rtx = struct_value_rtx; | |
4129 | #endif | |
4130 | #endif | |
4131 | ||
4132 | #ifdef STATIC_CHAIN_REGNUM | |
4133 | static_chain_rtx = gen_rtx_REG (Pmode, STATIC_CHAIN_REGNUM); | |
4134 | ||
4135 | #ifdef STATIC_CHAIN_INCOMING_REGNUM | |
4136 | if (STATIC_CHAIN_INCOMING_REGNUM != STATIC_CHAIN_REGNUM) | |
4137 | static_chain_incoming_rtx | |
4138 | = gen_rtx_REG (Pmode, STATIC_CHAIN_INCOMING_REGNUM); | |
4139 | else | |
4140 | #endif | |
4141 | static_chain_incoming_rtx = static_chain_rtx; | |
4142 | #endif | |
4143 | ||
4144 | #ifdef STATIC_CHAIN | |
4145 | static_chain_rtx = STATIC_CHAIN; | |
4146 | ||
4147 | #ifdef STATIC_CHAIN_INCOMING | |
4148 | static_chain_incoming_rtx = STATIC_CHAIN_INCOMING; | |
4149 | #else | |
4150 | static_chain_incoming_rtx = static_chain_rtx; | |
4151 | #endif | |
4152 | #endif | |
4153 | ||
4154 | #ifdef PIC_OFFSET_TABLE_REGNUM | |
4155 | pic_offset_table_rtx = gen_rtx_REG (Pmode, PIC_OFFSET_TABLE_REGNUM); | |
4156 | #endif | |
4157 | ||
d7db6646 RH |
4158 | ggc_add_rtx_root (&pic_offset_table_rtx, 1); |
4159 | ggc_add_rtx_root (&struct_value_rtx, 1); | |
4160 | ggc_add_rtx_root (&struct_value_incoming_rtx, 1); | |
4161 | ggc_add_rtx_root (&static_chain_rtx, 1); | |
4162 | ggc_add_rtx_root (&static_chain_incoming_rtx, 1); | |
4163 | ggc_add_rtx_root (&return_address_pointer_rtx, 1); | |
c13e8210 MM |
4164 | |
4165 | /* Initialize the CONST_INT hash table. */ | |
29105cea RK |
4166 | const_int_htab = htab_create (37, const_int_htab_hash, |
4167 | const_int_htab_eq, NULL); | |
c13e8210 MM |
4168 | ggc_add_root (&const_int_htab, 1, sizeof (const_int_htab), |
4169 | rtx_htab_mark); | |
23b2ce53 | 4170 | } |
a11759a3 JR |
4171 | \f |
4172 | /* Query and clear/ restore no_line_numbers. This is used by the | |
4173 | switch / case handling in stmt.c to give proper line numbers in | |
4174 | warnings about unreachable code. */ | |
4175 | ||
4176 | int | |
4177 | force_line_numbers () | |
4178 | { | |
4179 | int old = no_line_numbers; | |
4180 | ||
4181 | no_line_numbers = 0; | |
4182 | if (old) | |
4183 | force_next_line_note (); | |
4184 | return old; | |
4185 | } | |
4186 | ||
4187 | void | |
4188 | restore_line_number_status (old_value) | |
4189 | int old_value; | |
4190 | { | |
4191 | no_line_numbers = old_value; | |
4192 | } |