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23b2ce53 | 1 | /* Emit RTL for the GNU C-Compiler expander. |
72c3833b | 2 | Copyright (C) 1987, 88, 92, 93, 94, 95, 1996 Free Software Foundation, Inc. |
23b2ce53 RS |
3 | |
4 | This file is part of GNU CC. | |
5 | ||
6 | GNU CC is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
8 | the Free Software Foundation; either version 2, or (at your option) | |
9 | any later version. | |
10 | ||
11 | GNU CC is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with GNU CC; see the file COPYING. If not, write to | |
940d9d63 RK |
18 | the Free Software Foundation, 59 Temple Place - Suite 330, |
19 | Boston, MA 02111-1307, USA. */ | |
23b2ce53 RS |
20 | |
21 | ||
22 | /* Middle-to-low level generation of rtx code and insns. | |
23 | ||
24 | This file contains the functions `gen_rtx', `gen_reg_rtx' | |
25 | and `gen_label_rtx' that are the usual ways of creating rtl | |
26 | expressions for most purposes. | |
27 | ||
28 | It also has the functions for creating insns and linking | |
29 | them in the doubly-linked chain. | |
30 | ||
31 | The patterns of the insns are created by machine-dependent | |
32 | routines in insn-emit.c, which is generated automatically from | |
33 | the machine description. These routines use `gen_rtx' to make | |
34 | the individual rtx's of the pattern; what is machine dependent | |
35 | is the kind of rtx's they make and what arguments they use. */ | |
36 | ||
37 | #include "config.h" | |
4f90e4a0 | 38 | #ifdef __STDC__ |
04fe4385 | 39 | #include <stdarg.h> |
4f90e4a0 | 40 | #else |
04fe4385 | 41 | #include <varargs.h> |
4f90e4a0 | 42 | #endif |
23b2ce53 | 43 | #include "rtl.h" |
a25c7971 | 44 | #include "tree.h" |
23b2ce53 RS |
45 | #include "flags.h" |
46 | #include "function.h" | |
47 | #include "expr.h" | |
48 | #include "regs.h" | |
49 | #include "insn-config.h" | |
50 | #include "real.h" | |
ca695ac9 JB |
51 | #include "obstack.h" |
52 | ||
53 | #include "bytecode.h" | |
54 | #include "machmode.h" | |
55 | #include "bc-opcode.h" | |
56 | #include "bc-typecd.h" | |
57 | #include "bc-optab.h" | |
58 | #include "bc-emit.h" | |
59 | ||
f8d97cf4 | 60 | #include <stdio.h> |
23b2ce53 | 61 | |
ca695ac9 JB |
62 | |
63 | /* Opcode names */ | |
64 | #ifdef BCDEBUG_PRINT_CODE | |
65 | char *opcode_name[] = | |
66 | { | |
67 | #include "bc-opname.h" | |
68 | ||
69 | "***END***" | |
70 | }; | |
71 | #endif | |
72 | ||
73 | ||
1d445e9e ILT |
74 | /* Commonly used modes. */ |
75 | ||
0f41302f MS |
76 | enum machine_mode byte_mode; /* Mode whose width is BITS_PER_UNIT. */ |
77 | enum machine_mode word_mode; /* Mode whose width is BITS_PER_WORD. */ | |
78 | enum machine_mode ptr_mode; /* Mode whose width is POINTER_SIZE. */ | |
1d445e9e | 79 | |
23b2ce53 RS |
80 | /* This is reset to LAST_VIRTUAL_REGISTER + 1 at the start of each function. |
81 | After rtl generation, it is 1 plus the largest register number used. */ | |
82 | ||
83 | int reg_rtx_no = LAST_VIRTUAL_REGISTER + 1; | |
84 | ||
85 | /* This is *not* reset after each function. It gives each CODE_LABEL | |
86 | in the entire compilation a unique label number. */ | |
87 | ||
88 | static int label_num = 1; | |
89 | ||
90 | /* Lowest label number in current function. */ | |
91 | ||
92 | static int first_label_num; | |
93 | ||
94 | /* Highest label number in current function. | |
95 | Zero means use the value of label_num instead. | |
96 | This is nonzero only when belatedly compiling an inline function. */ | |
97 | ||
98 | static int last_label_num; | |
99 | ||
100 | /* Value label_num had when set_new_first_and_last_label_number was called. | |
101 | If label_num has not changed since then, last_label_num is valid. */ | |
102 | ||
103 | static int base_label_num; | |
104 | ||
105 | /* Nonzero means do not generate NOTEs for source line numbers. */ | |
106 | ||
107 | static int no_line_numbers; | |
108 | ||
109 | /* Commonly used rtx's, so that we only need space for one copy. | |
110 | These are initialized once for the entire compilation. | |
111 | All of these except perhaps the floating-point CONST_DOUBLEs | |
112 | are unique; no other rtx-object will be equal to any of these. */ | |
113 | ||
114 | rtx pc_rtx; /* (PC) */ | |
115 | rtx cc0_rtx; /* (CC0) */ | |
116 | rtx cc1_rtx; /* (CC1) (not actually used nowadays) */ | |
117 | rtx const0_rtx; /* (CONST_INT 0) */ | |
118 | rtx const1_rtx; /* (CONST_INT 1) */ | |
119 | rtx const2_rtx; /* (CONST_INT 2) */ | |
120 | rtx constm1_rtx; /* (CONST_INT -1) */ | |
121 | rtx const_true_rtx; /* (CONST_INT STORE_FLAG_VALUE) */ | |
122 | ||
123 | /* We record floating-point CONST_DOUBLEs in each floating-point mode for | |
124 | the values of 0, 1, and 2. For the integer entries and VOIDmode, we | |
125 | record a copy of const[012]_rtx. */ | |
126 | ||
127 | rtx const_tiny_rtx[3][(int) MAX_MACHINE_MODE]; | |
128 | ||
129 | REAL_VALUE_TYPE dconst0; | |
130 | REAL_VALUE_TYPE dconst1; | |
131 | REAL_VALUE_TYPE dconst2; | |
132 | REAL_VALUE_TYPE dconstm1; | |
133 | ||
134 | /* All references to the following fixed hard registers go through | |
135 | these unique rtl objects. On machines where the frame-pointer and | |
136 | arg-pointer are the same register, they use the same unique object. | |
137 | ||
138 | After register allocation, other rtl objects which used to be pseudo-regs | |
139 | may be clobbered to refer to the frame-pointer register. | |
140 | But references that were originally to the frame-pointer can be | |
141 | distinguished from the others because they contain frame_pointer_rtx. | |
142 | ||
ac6f08b0 DE |
143 | When to use frame_pointer_rtx and hard_frame_pointer_rtx is a little |
144 | tricky: until register elimination has taken place hard_frame_pointer_rtx | |
145 | should be used if it is being set, and frame_pointer_rtx otherwise. After | |
146 | register elimination hard_frame_pointer_rtx should always be used. | |
147 | On machines where the two registers are same (most) then these are the | |
148 | same. | |
149 | ||
23b2ce53 RS |
150 | In an inline procedure, the stack and frame pointer rtxs may not be |
151 | used for anything else. */ | |
152 | rtx stack_pointer_rtx; /* (REG:Pmode STACK_POINTER_REGNUM) */ | |
153 | rtx frame_pointer_rtx; /* (REG:Pmode FRAME_POINTER_REGNUM) */ | |
ac6f08b0 | 154 | rtx hard_frame_pointer_rtx; /* (REG:Pmode HARD_FRAME_POINTER_REGNUM) */ |
23b2ce53 RS |
155 | rtx arg_pointer_rtx; /* (REG:Pmode ARG_POINTER_REGNUM) */ |
156 | rtx struct_value_rtx; /* (REG:Pmode STRUCT_VALUE_REGNUM) */ | |
157 | rtx struct_value_incoming_rtx; /* (REG:Pmode STRUCT_VALUE_INCOMING_REGNUM) */ | |
158 | rtx static_chain_rtx; /* (REG:Pmode STATIC_CHAIN_REGNUM) */ | |
159 | rtx static_chain_incoming_rtx; /* (REG:Pmode STATIC_CHAIN_INCOMING_REGNUM) */ | |
160 | rtx pic_offset_table_rtx; /* (REG:Pmode PIC_OFFSET_TABLE_REGNUM) */ | |
161 | ||
a4417a86 JW |
162 | /* This is used to implement __builtin_return_address for some machines. |
163 | See for instance the MIPS port. */ | |
164 | rtx return_address_pointer_rtx; /* (REG:Pmode RETURN_ADDRESS_POINTER_REGNUM) */ | |
165 | ||
23b2ce53 RS |
166 | rtx virtual_incoming_args_rtx; /* (REG:Pmode VIRTUAL_INCOMING_ARGS_REGNUM) */ |
167 | rtx virtual_stack_vars_rtx; /* (REG:Pmode VIRTUAL_STACK_VARS_REGNUM) */ | |
168 | rtx virtual_stack_dynamic_rtx; /* (REG:Pmode VIRTUAL_STACK_DYNAMIC_REGNUM) */ | |
169 | rtx virtual_outgoing_args_rtx; /* (REG:Pmode VIRTUAL_OUTGOING_ARGS_REGNUM) */ | |
170 | ||
171 | /* We make one copy of (const_int C) where C is in | |
172 | [- MAX_SAVED_CONST_INT, MAX_SAVED_CONST_INT] | |
173 | to save space during the compilation and simplify comparisons of | |
174 | integers. */ | |
175 | ||
176 | #define MAX_SAVED_CONST_INT 64 | |
177 | ||
178 | static rtx const_int_rtx[MAX_SAVED_CONST_INT * 2 + 1]; | |
179 | ||
180 | /* The ends of the doubly-linked chain of rtl for the current function. | |
181 | Both are reset to null at the start of rtl generation for the function. | |
182 | ||
a25c7971 RK |
183 | start_sequence saves both of these on `sequence_stack' along with |
184 | `sequence_rtl_expr' and then starts a new, nested sequence of insns. */ | |
23b2ce53 RS |
185 | |
186 | static rtx first_insn = NULL; | |
187 | static rtx last_insn = NULL; | |
188 | ||
a25c7971 RK |
189 | /* RTL_EXPR within which the current sequence will be placed. Use to |
190 | prevent reuse of any temporaries within the sequence until after the | |
191 | RTL_EXPR is emitted. */ | |
192 | ||
193 | tree sequence_rtl_expr = NULL; | |
194 | ||
23b2ce53 RS |
195 | /* INSN_UID for next insn emitted. |
196 | Reset to 1 for each function compiled. */ | |
197 | ||
198 | static int cur_insn_uid = 1; | |
199 | ||
200 | /* Line number and source file of the last line-number NOTE emitted. | |
201 | This is used to avoid generating duplicates. */ | |
202 | ||
203 | static int last_linenum = 0; | |
204 | static char *last_filename = 0; | |
205 | ||
206 | /* A vector indexed by pseudo reg number. The allocated length | |
207 | of this vector is regno_pointer_flag_length. Since this | |
208 | vector is needed during the expansion phase when the total | |
209 | number of registers in the function is not yet known, | |
210 | it is copied and made bigger when necessary. */ | |
211 | ||
212 | char *regno_pointer_flag; | |
213 | int regno_pointer_flag_length; | |
214 | ||
86fe05e0 RK |
215 | /* Indexed by pseudo register number, if nonzero gives the known alignment |
216 | for that pseudo (if regno_pointer_flag is set). | |
217 | Allocated in parallel with regno_pointer_flag. */ | |
218 | char *regno_pointer_align; | |
219 | ||
23b2ce53 RS |
220 | /* Indexed by pseudo register number, gives the rtx for that pseudo. |
221 | Allocated in parallel with regno_pointer_flag. */ | |
222 | ||
223 | rtx *regno_reg_rtx; | |
224 | ||
225 | /* Stack of pending (incomplete) sequences saved by `start_sequence'. | |
226 | Each element describes one pending sequence. | |
227 | The main insn-chain is saved in the last element of the chain, | |
228 | unless the chain is empty. */ | |
229 | ||
230 | struct sequence_stack *sequence_stack; | |
231 | ||
232 | /* start_sequence and gen_sequence can make a lot of rtx expressions which are | |
233 | shortly thrown away. We use two mechanisms to prevent this waste: | |
234 | ||
235 | First, we keep a list of the expressions used to represent the sequence | |
236 | stack in sequence_element_free_list. | |
237 | ||
238 | Second, for sizes up to 5 elements, we keep a SEQUENCE and its associated | |
239 | rtvec for use by gen_sequence. One entry for each size is sufficient | |
240 | because most cases are calls to gen_sequence followed by immediately | |
241 | emitting the SEQUENCE. Reuse is safe since emitting a sequence is | |
242 | destructive on the insn in it anyway and hence can't be redone. | |
243 | ||
244 | We do not bother to save this cached data over nested function calls. | |
245 | Instead, we just reinitialize them. */ | |
246 | ||
247 | #define SEQUENCE_RESULT_SIZE 5 | |
248 | ||
249 | static struct sequence_stack *sequence_element_free_list; | |
250 | static rtx sequence_result[SEQUENCE_RESULT_SIZE]; | |
251 | ||
0f41302f | 252 | /* During RTL generation, we also keep a list of free INSN rtl codes. */ |
43127294 RK |
253 | static rtx free_insn; |
254 | ||
23b2ce53 RS |
255 | extern int rtx_equal_function_value_matters; |
256 | ||
257 | /* Filename and line number of last line-number note, | |
258 | whether we actually emitted it or not. */ | |
259 | extern char *emit_filename; | |
260 | extern int emit_lineno; | |
261 | ||
262 | rtx change_address (); | |
263 | void init_emit (); | |
264 | \f | |
ca695ac9 JB |
265 | extern struct obstack *rtl_obstack; |
266 | ||
267 | extern int stack_depth; | |
268 | extern int max_stack_depth; | |
269 | \f | |
23b2ce53 RS |
270 | /* rtx gen_rtx (code, mode, [element1, ..., elementn]) |
271 | ** | |
272 | ** This routine generates an RTX of the size specified by | |
273 | ** <code>, which is an RTX code. The RTX structure is initialized | |
274 | ** from the arguments <element1> through <elementn>, which are | |
275 | ** interpreted according to the specific RTX type's format. The | |
276 | ** special machine mode associated with the rtx (if any) is specified | |
277 | ** in <mode>. | |
278 | ** | |
1632afca | 279 | ** gen_rtx can be invoked in a way which resembles the lisp-like |
23b2ce53 RS |
280 | ** rtx it will generate. For example, the following rtx structure: |
281 | ** | |
282 | ** (plus:QI (mem:QI (reg:SI 1)) | |
283 | ** (mem:QI (plusw:SI (reg:SI 2) (reg:SI 3)))) | |
284 | ** | |
285 | ** ...would be generated by the following C code: | |
286 | ** | |
287 | ** gen_rtx (PLUS, QImode, | |
288 | ** gen_rtx (MEM, QImode, | |
289 | ** gen_rtx (REG, SImode, 1)), | |
290 | ** gen_rtx (MEM, QImode, | |
291 | ** gen_rtx (PLUS, SImode, | |
292 | ** gen_rtx (REG, SImode, 2), | |
293 | ** gen_rtx (REG, SImode, 3)))), | |
294 | */ | |
295 | ||
296 | /*VARARGS2*/ | |
297 | rtx | |
4f90e4a0 | 298 | gen_rtx VPROTO((enum rtx_code code, enum machine_mode mode, ...)) |
23b2ce53 | 299 | { |
4f90e4a0 | 300 | #ifndef __STDC__ |
23b2ce53 RS |
301 | enum rtx_code code; |
302 | enum machine_mode mode; | |
4f90e4a0 RK |
303 | #endif |
304 | va_list p; | |
23b2ce53 RS |
305 | register int i; /* Array indices... */ |
306 | register char *fmt; /* Current rtx's format... */ | |
307 | register rtx rt_val; /* RTX to return to caller... */ | |
308 | ||
4f90e4a0 RK |
309 | VA_START (p, mode); |
310 | ||
311 | #ifndef __STDC__ | |
23b2ce53 RS |
312 | code = va_arg (p, enum rtx_code); |
313 | mode = va_arg (p, enum machine_mode); | |
4f90e4a0 | 314 | #endif |
23b2ce53 RS |
315 | |
316 | if (code == CONST_INT) | |
317 | { | |
906c4e36 | 318 | HOST_WIDE_INT arg = va_arg (p, HOST_WIDE_INT); |
23b2ce53 RS |
319 | |
320 | if (arg >= - MAX_SAVED_CONST_INT && arg <= MAX_SAVED_CONST_INT) | |
321 | return const_int_rtx[arg + MAX_SAVED_CONST_INT]; | |
322 | ||
323 | if (const_true_rtx && arg == STORE_FLAG_VALUE) | |
324 | return const_true_rtx; | |
325 | ||
326 | rt_val = rtx_alloc (code); | |
327 | INTVAL (rt_val) = arg; | |
328 | } | |
329 | else if (code == REG) | |
330 | { | |
331 | int regno = va_arg (p, int); | |
332 | ||
333 | /* In case the MD file explicitly references the frame pointer, have | |
334 | all such references point to the same frame pointer. This is used | |
335 | during frame pointer elimination to distinguish the explicit | |
336 | references to these registers from pseudos that happened to be | |
337 | assigned to them. | |
338 | ||
339 | If we have eliminated the frame pointer or arg pointer, we will | |
340 | be using it as a normal register, for example as a spill register. | |
341 | In such cases, we might be accessing it in a mode that is not | |
600a5d88 | 342 | Pmode and therefore cannot use the pre-allocated rtx. |
23b2ce53 | 343 | |
600a5d88 RK |
344 | Also don't do this when we are making new REGs in reload, |
345 | since we don't want to get confused with the real pointers. */ | |
346 | ||
347 | if (frame_pointer_rtx && regno == FRAME_POINTER_REGNUM && mode == Pmode | |
348 | && ! reload_in_progress) | |
23b2ce53 | 349 | return frame_pointer_rtx; |
ac6f08b0 DE |
350 | #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM |
351 | if (hard_frame_pointer_rtx && regno == HARD_FRAME_POINTER_REGNUM | |
352 | && mode == Pmode && ! reload_in_progress) | |
353 | return hard_frame_pointer_rtx; | |
354 | #endif | |
355 | #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM && HARD_FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM | |
600a5d88 RK |
356 | if (arg_pointer_rtx && regno == ARG_POINTER_REGNUM && mode == Pmode |
357 | && ! reload_in_progress) | |
23b2ce53 | 358 | return arg_pointer_rtx; |
a4417a86 JW |
359 | #endif |
360 | #ifdef RETURN_ADDRESS_POINTER_REGNUM | |
361 | if (return_address_pointer_rtx && regno == RETURN_ADDRESS_POINTER_REGNUM | |
362 | && mode == Pmode && ! reload_in_progress) | |
363 | return return_address_pointer_rtx; | |
23b2ce53 | 364 | #endif |
600a5d88 RK |
365 | if (stack_pointer_rtx && regno == STACK_POINTER_REGNUM && mode == Pmode |
366 | && ! reload_in_progress) | |
23b2ce53 RS |
367 | return stack_pointer_rtx; |
368 | else | |
369 | { | |
370 | rt_val = rtx_alloc (code); | |
371 | rt_val->mode = mode; | |
372 | REGNO (rt_val) = regno; | |
373 | return rt_val; | |
374 | } | |
375 | } | |
376 | else | |
377 | { | |
378 | rt_val = rtx_alloc (code); /* Allocate the storage space. */ | |
379 | rt_val->mode = mode; /* Store the machine mode... */ | |
380 | ||
381 | fmt = GET_RTX_FORMAT (code); /* Find the right format... */ | |
382 | for (i = 0; i < GET_RTX_LENGTH (code); i++) | |
383 | { | |
384 | switch (*fmt++) | |
385 | { | |
386 | case '0': /* Unused field. */ | |
387 | break; | |
388 | ||
389 | case 'i': /* An integer? */ | |
390 | XINT (rt_val, i) = va_arg (p, int); | |
391 | break; | |
392 | ||
906c4e36 RK |
393 | case 'w': /* A wide integer? */ |
394 | XWINT (rt_val, i) = va_arg (p, HOST_WIDE_INT); | |
395 | break; | |
396 | ||
23b2ce53 RS |
397 | case 's': /* A string? */ |
398 | XSTR (rt_val, i) = va_arg (p, char *); | |
399 | break; | |
400 | ||
401 | case 'e': /* An expression? */ | |
402 | case 'u': /* An insn? Same except when printing. */ | |
403 | XEXP (rt_val, i) = va_arg (p, rtx); | |
404 | break; | |
405 | ||
406 | case 'E': /* An RTX vector? */ | |
407 | XVEC (rt_val, i) = va_arg (p, rtvec); | |
408 | break; | |
409 | ||
410 | default: | |
1632afca | 411 | abort (); |
23b2ce53 RS |
412 | } |
413 | } | |
414 | } | |
415 | va_end (p); | |
416 | return rt_val; /* Return the new RTX... */ | |
417 | } | |
418 | ||
419 | /* gen_rtvec (n, [rt1, ..., rtn]) | |
420 | ** | |
421 | ** This routine creates an rtvec and stores within it the | |
422 | ** pointers to rtx's which are its arguments. | |
423 | */ | |
424 | ||
425 | /*VARARGS1*/ | |
426 | rtvec | |
4f90e4a0 | 427 | gen_rtvec VPROTO((int n, ...)) |
23b2ce53 | 428 | { |
4f90e4a0 RK |
429 | #ifndef __STDC__ |
430 | int n; | |
431 | #endif | |
432 | int i; | |
23b2ce53 RS |
433 | va_list p; |
434 | rtx *vector; | |
435 | ||
4f90e4a0 RK |
436 | VA_START (p, n); |
437 | ||
438 | #ifndef __STDC__ | |
23b2ce53 | 439 | n = va_arg (p, int); |
4f90e4a0 | 440 | #endif |
23b2ce53 RS |
441 | |
442 | if (n == 0) | |
443 | return NULL_RTVEC; /* Don't allocate an empty rtvec... */ | |
444 | ||
445 | vector = (rtx *) alloca (n * sizeof (rtx)); | |
4f90e4a0 | 446 | |
23b2ce53 RS |
447 | for (i = 0; i < n; i++) |
448 | vector[i] = va_arg (p, rtx); | |
449 | va_end (p); | |
450 | ||
451 | return gen_rtvec_v (n, vector); | |
452 | } | |
453 | ||
454 | rtvec | |
455 | gen_rtvec_v (n, argp) | |
456 | int n; | |
457 | rtx *argp; | |
458 | { | |
459 | register int i; | |
460 | register rtvec rt_val; | |
461 | ||
462 | if (n == 0) | |
463 | return NULL_RTVEC; /* Don't allocate an empty rtvec... */ | |
464 | ||
465 | rt_val = rtvec_alloc (n); /* Allocate an rtvec... */ | |
466 | ||
467 | for (i = 0; i < n; i++) | |
468 | rt_val->elem[i].rtx = *argp++; | |
469 | ||
470 | return rt_val; | |
471 | } | |
472 | \f | |
473 | /* Generate a REG rtx for a new pseudo register of mode MODE. | |
474 | This pseudo is assigned the next sequential register number. */ | |
475 | ||
476 | rtx | |
477 | gen_reg_rtx (mode) | |
478 | enum machine_mode mode; | |
479 | { | |
480 | register rtx val; | |
481 | ||
482 | /* Don't let anything called by or after reload create new registers | |
483 | (actually, registers can't be created after flow, but this is a good | |
484 | approximation). */ | |
485 | ||
486 | if (reload_in_progress || reload_completed) | |
487 | abort (); | |
488 | ||
fc84e8a8 RS |
489 | if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT |
490 | || GET_MODE_CLASS (mode) == MODE_COMPLEX_INT) | |
491 | { | |
492 | /* For complex modes, don't make a single pseudo. | |
493 | Instead, make a CONCAT of two pseudos. | |
494 | This allows noncontiguous allocation of the real and imaginary parts, | |
495 | which makes much better code. Besides, allocating DCmode | |
496 | pseudos overstrains reload on some machines like the 386. */ | |
497 | rtx realpart, imagpart; | |
498 | int size = GET_MODE_UNIT_SIZE (mode); | |
499 | enum machine_mode partmode | |
500 | = mode_for_size (size * BITS_PER_UNIT, | |
501 | (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT | |
502 | ? MODE_FLOAT : MODE_INT), | |
503 | 0); | |
504 | ||
505 | realpart = gen_reg_rtx (partmode); | |
506 | imagpart = gen_reg_rtx (partmode); | |
507 | return gen_rtx (CONCAT, mode, realpart, imagpart); | |
508 | } | |
509 | ||
23b2ce53 RS |
510 | /* Make sure regno_pointer_flag and regno_reg_rtx are large |
511 | enough to have an element for this pseudo reg number. */ | |
512 | ||
513 | if (reg_rtx_no == regno_pointer_flag_length) | |
514 | { | |
515 | rtx *new1; | |
516 | char *new = | |
86fe05e0 | 517 | (char *) savealloc (regno_pointer_flag_length * 2); |
23b2ce53 | 518 | bcopy (regno_pointer_flag, new, regno_pointer_flag_length); |
c0b178d0 | 519 | bzero (&new[regno_pointer_flag_length], regno_pointer_flag_length); |
23b2ce53 RS |
520 | regno_pointer_flag = new; |
521 | ||
86fe05e0 RK |
522 | new = (char *) savealloc (regno_pointer_flag_length * 2); |
523 | bcopy (regno_pointer_align, new, regno_pointer_flag_length); | |
524 | bzero (&new[regno_pointer_flag_length], regno_pointer_flag_length); | |
525 | regno_pointer_align = new; | |
526 | ||
527 | new1 = (rtx *) savealloc (regno_pointer_flag_length * 2 * sizeof (rtx)); | |
4c9a05bc RK |
528 | bcopy ((char *) regno_reg_rtx, (char *) new1, |
529 | regno_pointer_flag_length * sizeof (rtx)); | |
530 | bzero ((char *) &new1[regno_pointer_flag_length], | |
c0b178d0 | 531 | regno_pointer_flag_length * sizeof (rtx)); |
23b2ce53 RS |
532 | regno_reg_rtx = new1; |
533 | ||
534 | regno_pointer_flag_length *= 2; | |
535 | } | |
536 | ||
537 | val = gen_rtx (REG, mode, reg_rtx_no); | |
538 | regno_reg_rtx[reg_rtx_no++] = val; | |
539 | return val; | |
540 | } | |
541 | ||
86fe05e0 RK |
542 | /* Identify REG as a probable pointer register and show its alignment |
543 | as ALIGN, if nonzero. */ | |
23b2ce53 RS |
544 | |
545 | void | |
86fe05e0 | 546 | mark_reg_pointer (reg, align) |
23b2ce53 | 547 | rtx reg; |
86fe05e0 | 548 | int align; |
23b2ce53 RS |
549 | { |
550 | REGNO_POINTER_FLAG (REGNO (reg)) = 1; | |
86fe05e0 RK |
551 | |
552 | if (align) | |
553 | REGNO_POINTER_ALIGN (REGNO (reg)) = align; | |
23b2ce53 RS |
554 | } |
555 | ||
556 | /* Return 1 plus largest pseudo reg number used in the current function. */ | |
557 | ||
558 | int | |
559 | max_reg_num () | |
560 | { | |
561 | return reg_rtx_no; | |
562 | } | |
563 | ||
564 | /* Return 1 + the largest label number used so far in the current function. */ | |
565 | ||
566 | int | |
567 | max_label_num () | |
568 | { | |
569 | if (last_label_num && label_num == base_label_num) | |
570 | return last_label_num; | |
571 | return label_num; | |
572 | } | |
573 | ||
574 | /* Return first label number used in this function (if any were used). */ | |
575 | ||
576 | int | |
577 | get_first_label_num () | |
578 | { | |
579 | return first_label_num; | |
580 | } | |
581 | \f | |
582 | /* Return a value representing some low-order bits of X, where the number | |
583 | of low-order bits is given by MODE. Note that no conversion is done | |
584 | between floating-point and fixed-point values, rather, the bit | |
585 | representation is returned. | |
586 | ||
587 | This function handles the cases in common between gen_lowpart, below, | |
588 | and two variants in cse.c and combine.c. These are the cases that can | |
589 | be safely handled at all points in the compilation. | |
590 | ||
591 | If this is not a case we can handle, return 0. */ | |
592 | ||
593 | rtx | |
594 | gen_lowpart_common (mode, x) | |
595 | enum machine_mode mode; | |
596 | register rtx x; | |
597 | { | |
598 | int word = 0; | |
599 | ||
600 | if (GET_MODE (x) == mode) | |
601 | return x; | |
602 | ||
603 | /* MODE must occupy no more words than the mode of X. */ | |
604 | if (GET_MODE (x) != VOIDmode | |
605 | && ((GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD | |
606 | > ((GET_MODE_SIZE (GET_MODE (x)) + (UNITS_PER_WORD - 1)) | |
607 | / UNITS_PER_WORD))) | |
608 | return 0; | |
609 | ||
610 | if (WORDS_BIG_ENDIAN && GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD) | |
611 | word = ((GET_MODE_SIZE (GET_MODE (x)) | |
612 | - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD)) | |
613 | / UNITS_PER_WORD); | |
614 | ||
615 | if ((GET_CODE (x) == ZERO_EXTEND || GET_CODE (x) == SIGN_EXTEND) | |
83e9c679 RK |
616 | && (GET_MODE_CLASS (mode) == MODE_INT |
617 | || GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)) | |
23b2ce53 RS |
618 | { |
619 | /* If we are getting the low-order part of something that has been | |
620 | sign- or zero-extended, we can either just use the object being | |
621 | extended or make a narrower extension. If we want an even smaller | |
622 | piece than the size of the object being extended, call ourselves | |
623 | recursively. | |
624 | ||
625 | This case is used mostly by combine and cse. */ | |
626 | ||
627 | if (GET_MODE (XEXP (x, 0)) == mode) | |
628 | return XEXP (x, 0); | |
629 | else if (GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (XEXP (x, 0)))) | |
630 | return gen_lowpart_common (mode, XEXP (x, 0)); | |
631 | else if (GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (x))) | |
632 | return gen_rtx (GET_CODE (x), mode, XEXP (x, 0)); | |
633 | } | |
634 | else if (GET_CODE (x) == SUBREG | |
635 | && (GET_MODE_SIZE (mode) <= UNITS_PER_WORD | |
636 | || GET_MODE_SIZE (mode) == GET_MODE_UNIT_SIZE (GET_MODE (x)))) | |
637 | return (GET_MODE (SUBREG_REG (x)) == mode && SUBREG_WORD (x) == 0 | |
638 | ? SUBREG_REG (x) | |
639 | : gen_rtx (SUBREG, mode, SUBREG_REG (x), SUBREG_WORD (x))); | |
640 | else if (GET_CODE (x) == REG) | |
641 | { | |
642 | /* If the register is not valid for MODE, return 0. If we don't | |
674d5d8b RK |
643 | do this, there is no way to fix up the resulting REG later. |
644 | But we do do this if the current REG is not valid for its | |
645 | mode. This latter is a kludge, but is required due to the | |
646 | way that parameters are passed on some machines, most | |
647 | notably Sparc. */ | |
23b2ce53 | 648 | if (REGNO (x) < FIRST_PSEUDO_REGISTER |
674d5d8b RK |
649 | && ! HARD_REGNO_MODE_OK (REGNO (x) + word, mode) |
650 | && HARD_REGNO_MODE_OK (REGNO (x), GET_MODE (x))) | |
23b2ce53 RS |
651 | return 0; |
652 | else if (REGNO (x) < FIRST_PSEUDO_REGISTER | |
653 | /* integrate.c can't handle parts of a return value register. */ | |
654 | && (! REG_FUNCTION_VALUE_P (x) | |
cb00f51a RK |
655 | || ! rtx_equal_function_value_matters) |
656 | /* We want to keep the stack, frame, and arg pointers | |
657 | special. */ | |
65e8fe02 | 658 | && x != frame_pointer_rtx |
cb00f51a | 659 | #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM |
65e8fe02 | 660 | && x != arg_pointer_rtx |
cb00f51a | 661 | #endif |
65e8fe02 | 662 | && x != stack_pointer_rtx) |
23b2ce53 RS |
663 | return gen_rtx (REG, mode, REGNO (x) + word); |
664 | else | |
665 | return gen_rtx (SUBREG, mode, x, word); | |
666 | } | |
23b2ce53 RS |
667 | /* If X is a CONST_INT or a CONST_DOUBLE, extract the appropriate bits |
668 | from the low-order part of the constant. */ | |
83e9c679 RK |
669 | else if ((GET_MODE_CLASS (mode) == MODE_INT |
670 | || GET_MODE_CLASS (mode) == MODE_PARTIAL_INT) | |
671 | && GET_MODE (x) == VOIDmode | |
23b2ce53 | 672 | && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE)) |
1a5b457d RK |
673 | { |
674 | /* If MODE is twice the host word size, X is already the desired | |
675 | representation. Otherwise, if MODE is wider than a word, we can't | |
676 | do this. If MODE is exactly a word, return just one CONST_INT. | |
677 | If MODE is smaller than a word, clear the bits that don't belong | |
678 | in our mode, unless they and our sign bit are all one. So we get | |
679 | either a reasonable negative value or a reasonable unsigned value | |
680 | for this mode. */ | |
681 | ||
a8dd0e73 | 682 | if (GET_MODE_BITSIZE (mode) >= 2 * HOST_BITS_PER_WIDE_INT) |
1a5b457d | 683 | return x; |
906c4e36 | 684 | else if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT) |
1a5b457d | 685 | return 0; |
906c4e36 | 686 | else if (GET_MODE_BITSIZE (mode) == HOST_BITS_PER_WIDE_INT) |
1a5b457d | 687 | return (GET_CODE (x) == CONST_INT ? x |
906c4e36 | 688 | : GEN_INT (CONST_DOUBLE_LOW (x))); |
1a5b457d RK |
689 | else |
690 | { | |
691 | /* MODE must be narrower than HOST_BITS_PER_INT. */ | |
692 | int width = GET_MODE_BITSIZE (mode); | |
906c4e36 RK |
693 | HOST_WIDE_INT val = (GET_CODE (x) == CONST_INT ? INTVAL (x) |
694 | : CONST_DOUBLE_LOW (x)); | |
1a5b457d | 695 | |
906c4e36 RK |
696 | if (((val & ((HOST_WIDE_INT) (-1) << (width - 1))) |
697 | != ((HOST_WIDE_INT) (-1) << (width - 1)))) | |
698 | val &= ((HOST_WIDE_INT) 1 << width) - 1; | |
1a5b457d RK |
699 | |
700 | return (GET_CODE (x) == CONST_INT && INTVAL (x) == val ? x | |
906c4e36 | 701 | : GEN_INT (val)); |
1a5b457d RK |
702 | } |
703 | } | |
23b2ce53 | 704 | |
8aada4ad RK |
705 | /* If X is an integral constant but we want it in floating-point, it |
706 | must be the case that we have a union of an integer and a floating-point | |
707 | value. If the machine-parameters allow it, simulate that union here | |
d6020413 RK |
708 | and return the result. The two-word and single-word cases are |
709 | different. */ | |
8aada4ad | 710 | |
b3bf132d | 711 | else if (((HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT |
906c4e36 | 712 | && HOST_BITS_PER_WIDE_INT == BITS_PER_WORD) |
b3bf132d | 713 | || flag_pretend_float) |
8aada4ad | 714 | && GET_MODE_CLASS (mode) == MODE_FLOAT |
d6020413 RK |
715 | && GET_MODE_SIZE (mode) == UNITS_PER_WORD |
716 | && GET_CODE (x) == CONST_INT | |
906c4e36 | 717 | && sizeof (float) * HOST_BITS_PER_CHAR == HOST_BITS_PER_WIDE_INT) |
b6a524cb RS |
718 | #ifdef REAL_ARITHMETIC |
719 | { | |
720 | REAL_VALUE_TYPE r; | |
721 | HOST_WIDE_INT i; | |
722 | ||
723 | i = INTVAL (x); | |
724 | r = REAL_VALUE_FROM_TARGET_SINGLE (i); | |
53596fba | 725 | return CONST_DOUBLE_FROM_REAL_VALUE (r, mode); |
b6a524cb RS |
726 | } |
727 | #else | |
d6020413 | 728 | { |
906c4e36 | 729 | union {HOST_WIDE_INT i; float d; } u; |
d6020413 RK |
730 | |
731 | u.i = INTVAL (x); | |
53596fba | 732 | return CONST_DOUBLE_FROM_REAL_VALUE (u.d, mode); |
d6020413 | 733 | } |
b6a524cb | 734 | #endif |
d6020413 | 735 | else if (((HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT |
906c4e36 | 736 | && HOST_BITS_PER_WIDE_INT == BITS_PER_WORD) |
d6020413 RK |
737 | || flag_pretend_float) |
738 | && GET_MODE_CLASS (mode) == MODE_FLOAT | |
739 | && GET_MODE_SIZE (mode) == 2 * UNITS_PER_WORD | |
8aada4ad RK |
740 | && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE) |
741 | && GET_MODE (x) == VOIDmode | |
906c4e36 RK |
742 | && (sizeof (double) * HOST_BITS_PER_CHAR |
743 | == 2 * HOST_BITS_PER_WIDE_INT)) | |
b6a524cb RS |
744 | #ifdef REAL_ARITHMETIC |
745 | { | |
746 | REAL_VALUE_TYPE r; | |
747 | HOST_WIDE_INT i[2]; | |
748 | HOST_WIDE_INT low, high; | |
749 | ||
750 | if (GET_CODE (x) == CONST_INT) | |
751 | low = INTVAL (x), high = low >> (HOST_BITS_PER_WIDE_INT -1); | |
752 | else | |
753 | low = CONST_DOUBLE_LOW (x), high = CONST_DOUBLE_HIGH (x); | |
754 | ||
8698cce3 | 755 | /* REAL_VALUE_TARGET_DOUBLE takes the addressing order of the |
0f41302f | 756 | target machine. */ |
8698cce3 RK |
757 | if (WORDS_BIG_ENDIAN) |
758 | i[0] = high, i[1] = low; | |
759 | else | |
760 | i[0] = low, i[1] = high; | |
b6a524cb RS |
761 | |
762 | r = REAL_VALUE_FROM_TARGET_DOUBLE (i); | |
53596fba | 763 | return CONST_DOUBLE_FROM_REAL_VALUE (r, mode); |
b6a524cb RS |
764 | } |
765 | #else | |
8aada4ad | 766 | { |
906c4e36 RK |
767 | union {HOST_WIDE_INT i[2]; double d; } u; |
768 | HOST_WIDE_INT low, high; | |
8aada4ad RK |
769 | |
770 | if (GET_CODE (x) == CONST_INT) | |
906c4e36 | 771 | low = INTVAL (x), high = low >> (HOST_BITS_PER_WIDE_INT -1); |
8aada4ad RK |
772 | else |
773 | low = CONST_DOUBLE_LOW (x), high = CONST_DOUBLE_HIGH (x); | |
774 | ||
775 | #ifdef HOST_WORDS_BIG_ENDIAN | |
776 | u.i[0] = high, u.i[1] = low; | |
777 | #else | |
778 | u.i[0] = low, u.i[1] = high; | |
779 | #endif | |
780 | ||
53596fba | 781 | return CONST_DOUBLE_FROM_REAL_VALUE (u.d, mode); |
8aada4ad | 782 | } |
b6a524cb | 783 | #endif |
b3bf132d RK |
784 | /* Similarly, if this is converting a floating-point value into a |
785 | single-word integer. Only do this is the host and target parameters are | |
786 | compatible. */ | |
787 | ||
788 | else if (((HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT | |
906c4e36 | 789 | && HOST_BITS_PER_WIDE_INT == BITS_PER_WORD) |
b3bf132d | 790 | || flag_pretend_float) |
83e9c679 RK |
791 | && (GET_MODE_CLASS (mode) == MODE_INT |
792 | || GET_MODE_CLASS (mode) == MODE_PARTIAL_INT) | |
b3bf132d RK |
793 | && GET_CODE (x) == CONST_DOUBLE |
794 | && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT | |
795 | && GET_MODE_BITSIZE (mode) == BITS_PER_WORD) | |
796 | return operand_subword (x, 0, 0, GET_MODE (x)); | |
797 | ||
8aada4ad RK |
798 | /* Similarly, if this is converting a floating-point value into a |
799 | two-word integer, we can do this one word at a time and make an | |
800 | integer. Only do this is the host and target parameters are | |
801 | compatible. */ | |
802 | ||
b3bf132d | 803 | else if (((HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT |
906c4e36 | 804 | && HOST_BITS_PER_WIDE_INT == BITS_PER_WORD) |
b3bf132d | 805 | || flag_pretend_float) |
83e9c679 | 806 | && (GET_MODE_CLASS (mode) == MODE_INT |
f5a2fb25 | 807 | || GET_MODE_CLASS (mode) == MODE_PARTIAL_INT) |
8aada4ad RK |
808 | && GET_CODE (x) == CONST_DOUBLE |
809 | && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT | |
810 | && GET_MODE_BITSIZE (mode) == 2 * BITS_PER_WORD) | |
811 | { | |
812 | rtx lowpart = operand_subword (x, WORDS_BIG_ENDIAN, 0, GET_MODE (x)); | |
813 | rtx highpart = operand_subword (x, ! WORDS_BIG_ENDIAN, 0, GET_MODE (x)); | |
814 | ||
815 | if (lowpart && GET_CODE (lowpart) == CONST_INT | |
816 | && highpart && GET_CODE (highpart) == CONST_INT) | |
817 | return immed_double_const (INTVAL (lowpart), INTVAL (highpart), mode); | |
818 | } | |
819 | ||
23b2ce53 RS |
820 | /* Otherwise, we can't do this. */ |
821 | return 0; | |
822 | } | |
823 | \f | |
280194b0 RS |
824 | /* Return the real part (which has mode MODE) of a complex value X. |
825 | This always comes at the low address in memory. */ | |
826 | ||
827 | rtx | |
828 | gen_realpart (mode, x) | |
829 | enum machine_mode mode; | |
830 | register rtx x; | |
831 | { | |
dc139c90 RK |
832 | if (GET_CODE (x) == CONCAT && GET_MODE (XEXP (x, 0)) == mode) |
833 | return XEXP (x, 0); | |
834 | else if (WORDS_BIG_ENDIAN) | |
280194b0 RS |
835 | return gen_highpart (mode, x); |
836 | else | |
837 | return gen_lowpart (mode, x); | |
838 | } | |
839 | ||
840 | /* Return the imaginary part (which has mode MODE) of a complex value X. | |
841 | This always comes at the high address in memory. */ | |
842 | ||
843 | rtx | |
844 | gen_imagpart (mode, x) | |
845 | enum machine_mode mode; | |
846 | register rtx x; | |
847 | { | |
dc139c90 RK |
848 | if (GET_CODE (x) == CONCAT && GET_MODE (XEXP (x, 0)) == mode) |
849 | return XEXP (x, 1); | |
850 | else if (WORDS_BIG_ENDIAN) | |
280194b0 RS |
851 | return gen_lowpart (mode, x); |
852 | else | |
853 | return gen_highpart (mode, x); | |
854 | } | |
81284a6a JW |
855 | |
856 | /* Return 1 iff X, assumed to be a SUBREG, | |
857 | refers to the real part of the complex value in its containing reg. | |
858 | Complex values are always stored with the real part in the first word, | |
859 | regardless of WORDS_BIG_ENDIAN. */ | |
860 | ||
861 | int | |
862 | subreg_realpart_p (x) | |
863 | rtx x; | |
864 | { | |
865 | if (GET_CODE (x) != SUBREG) | |
866 | abort (); | |
867 | ||
868 | return SUBREG_WORD (x) == 0; | |
869 | } | |
280194b0 | 870 | \f |
23b2ce53 RS |
871 | /* Assuming that X is an rtx (e.g., MEM, REG or SUBREG) for a value, |
872 | return an rtx (MEM, SUBREG, or CONST_INT) that refers to the | |
873 | least-significant part of X. | |
874 | MODE specifies how big a part of X to return; | |
875 | it usually should not be larger than a word. | |
876 | If X is a MEM whose address is a QUEUED, the value may be so also. */ | |
877 | ||
878 | rtx | |
879 | gen_lowpart (mode, x) | |
880 | enum machine_mode mode; | |
881 | register rtx x; | |
882 | { | |
883 | rtx result = gen_lowpart_common (mode, x); | |
884 | ||
885 | if (result) | |
886 | return result; | |
ea8262b0 RK |
887 | else if (GET_CODE (x) == REG) |
888 | { | |
889 | /* Must be a hard reg that's not valid in MODE. */ | |
890 | result = gen_lowpart_common (mode, copy_to_reg (x)); | |
891 | if (result == 0) | |
892 | abort (); | |
72c3833b | 893 | return result; |
ea8262b0 | 894 | } |
23b2ce53 RS |
895 | else if (GET_CODE (x) == MEM) |
896 | { | |
897 | /* The only additional case we can do is MEM. */ | |
898 | register int offset = 0; | |
899 | if (WORDS_BIG_ENDIAN) | |
900 | offset = (MAX (GET_MODE_SIZE (GET_MODE (x)), UNITS_PER_WORD) | |
901 | - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD)); | |
902 | ||
903 | if (BYTES_BIG_ENDIAN) | |
904 | /* Adjust the address so that the address-after-the-data | |
905 | is unchanged. */ | |
906 | offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode)) | |
907 | - MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (x)))); | |
908 | ||
909 | return change_address (x, mode, plus_constant (XEXP (x, 0), offset)); | |
910 | } | |
911 | else | |
912 | abort (); | |
913 | } | |
914 | ||
ccba022b RS |
915 | /* Like `gen_lowpart', but refer to the most significant part. |
916 | This is used to access the imaginary part of a complex number. */ | |
917 | ||
918 | rtx | |
919 | gen_highpart (mode, x) | |
920 | enum machine_mode mode; | |
921 | register rtx x; | |
922 | { | |
923 | /* This case loses if X is a subreg. To catch bugs early, | |
924 | complain if an invalid MODE is used even in other cases. */ | |
925 | if (GET_MODE_SIZE (mode) > UNITS_PER_WORD | |
926 | && GET_MODE_SIZE (mode) != GET_MODE_UNIT_SIZE (GET_MODE (x))) | |
927 | abort (); | |
928 | if (GET_CODE (x) == CONST_DOUBLE | |
1632afca | 929 | #if !(TARGET_FLOAT_FORMAT != HOST_FLOAT_FORMAT || defined (REAL_IS_NOT_DOUBLE)) |
ccba022b RS |
930 | && GET_MODE_CLASS (GET_MODE (x)) != MODE_FLOAT |
931 | #endif | |
932 | ) | |
933 | return gen_rtx (CONST_INT, VOIDmode, | |
934 | CONST_DOUBLE_HIGH (x) & GET_MODE_MASK (mode)); | |
935 | else if (GET_CODE (x) == CONST_INT) | |
936 | return const0_rtx; | |
937 | else if (GET_CODE (x) == MEM) | |
938 | { | |
939 | register int offset = 0; | |
8698cce3 RK |
940 | if (! WORDS_BIG_ENDIAN) |
941 | offset = (MAX (GET_MODE_SIZE (GET_MODE (x)), UNITS_PER_WORD) | |
942 | - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD)); | |
943 | ||
944 | if (! BYTES_BIG_ENDIAN | |
945 | && GET_MODE_SIZE (mode) < UNITS_PER_WORD) | |
ccba022b RS |
946 | offset -= (GET_MODE_SIZE (mode) |
947 | - MIN (UNITS_PER_WORD, | |
948 | GET_MODE_SIZE (GET_MODE (x)))); | |
8698cce3 | 949 | |
ccba022b RS |
950 | return change_address (x, mode, plus_constant (XEXP (x, 0), offset)); |
951 | } | |
952 | else if (GET_CODE (x) == SUBREG) | |
953 | { | |
954 | /* The only time this should occur is when we are looking at a | |
955 | multi-word item with a SUBREG whose mode is the same as that of the | |
956 | item. It isn't clear what we would do if it wasn't. */ | |
957 | if (SUBREG_WORD (x) != 0) | |
958 | abort (); | |
959 | return gen_highpart (mode, SUBREG_REG (x)); | |
960 | } | |
961 | else if (GET_CODE (x) == REG) | |
962 | { | |
963 | int word = 0; | |
964 | ||
8698cce3 RK |
965 | if (! WORDS_BIG_ENDIAN |
966 | && GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD) | |
ccba022b RS |
967 | word = ((GET_MODE_SIZE (GET_MODE (x)) |
968 | - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD)) | |
969 | / UNITS_PER_WORD); | |
8698cce3 | 970 | |
3e4a14ef RK |
971 | /* |
972 | * ??? This fails miserably for complex values being passed in registers | |
973 | * where the sizeof the real and imaginary part are not equal to the | |
974 | * sizeof SImode. FIXME | |
975 | */ | |
976 | ||
cb00f51a | 977 | if (REGNO (x) < FIRST_PSEUDO_REGISTER |
0f41302f | 978 | /* integrate.c can't handle parts of a return value register. */ |
4badc528 RS |
979 | && (! REG_FUNCTION_VALUE_P (x) |
980 | || ! rtx_equal_function_value_matters) | |
cb00f51a | 981 | /* We want to keep the stack, frame, and arg pointers special. */ |
65e8fe02 | 982 | && x != frame_pointer_rtx |
cb00f51a | 983 | #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM |
65e8fe02 | 984 | && x != arg_pointer_rtx |
cb00f51a | 985 | #endif |
65e8fe02 | 986 | && x != stack_pointer_rtx) |
ccba022b RS |
987 | return gen_rtx (REG, mode, REGNO (x) + word); |
988 | else | |
989 | return gen_rtx (SUBREG, mode, x, word); | |
990 | } | |
991 | else | |
992 | abort (); | |
993 | } | |
994 | ||
23b2ce53 RS |
995 | /* Return 1 iff X, assumed to be a SUBREG, |
996 | refers to the least significant part of its containing reg. | |
997 | If X is not a SUBREG, always return 1 (it is its own low part!). */ | |
998 | ||
999 | int | |
1000 | subreg_lowpart_p (x) | |
1001 | rtx x; | |
1002 | { | |
1003 | if (GET_CODE (x) != SUBREG) | |
1004 | return 1; | |
1005 | ||
1006 | if (WORDS_BIG_ENDIAN | |
1007 | && GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))) > UNITS_PER_WORD) | |
1008 | return (SUBREG_WORD (x) | |
1009 | == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))) | |
1010 | - MAX (GET_MODE_SIZE (GET_MODE (x)), UNITS_PER_WORD)) | |
1011 | / UNITS_PER_WORD)); | |
1012 | ||
1013 | return SUBREG_WORD (x) == 0; | |
1014 | } | |
1015 | \f | |
1016 | /* Return subword I of operand OP. | |
1017 | The word number, I, is interpreted as the word number starting at the | |
1018 | low-order address. Word 0 is the low-order word if not WORDS_BIG_ENDIAN, | |
1019 | otherwise it is the high-order word. | |
1020 | ||
1021 | If we cannot extract the required word, we return zero. Otherwise, an | |
1022 | rtx corresponding to the requested word will be returned. | |
1023 | ||
1024 | VALIDATE_ADDRESS is nonzero if the address should be validated. Before | |
1025 | reload has completed, a valid address will always be returned. After | |
1026 | reload, if a valid address cannot be returned, we return zero. | |
1027 | ||
1028 | If VALIDATE_ADDRESS is zero, we simply form the required address; validating | |
1029 | it is the responsibility of the caller. | |
1030 | ||
1031 | MODE is the mode of OP in case it is a CONST_INT. */ | |
1032 | ||
1033 | rtx | |
1034 | operand_subword (op, i, validate_address, mode) | |
1035 | rtx op; | |
1036 | int i; | |
1037 | int validate_address; | |
1038 | enum machine_mode mode; | |
1039 | { | |
906c4e36 RK |
1040 | HOST_WIDE_INT val; |
1041 | int size_ratio = HOST_BITS_PER_WIDE_INT / BITS_PER_WORD; | |
23b2ce53 RS |
1042 | |
1043 | if (mode == VOIDmode) | |
1044 | mode = GET_MODE (op); | |
1045 | ||
1046 | if (mode == VOIDmode) | |
1047 | abort (); | |
1048 | ||
1049 | /* If OP is narrower than a word or if we want a word outside OP, fail. */ | |
1050 | if (mode != BLKmode | |
1051 | && (GET_MODE_SIZE (mode) < UNITS_PER_WORD | |
1052 | || (i + 1) * UNITS_PER_WORD > GET_MODE_SIZE (mode))) | |
1053 | return 0; | |
1054 | ||
1055 | /* If OP is already an integer word, return it. */ | |
1056 | if (GET_MODE_CLASS (mode) == MODE_INT | |
1057 | && GET_MODE_SIZE (mode) == UNITS_PER_WORD) | |
1058 | return op; | |
1059 | ||
1060 | /* If OP is a REG or SUBREG, we can handle it very simply. */ | |
1061 | if (GET_CODE (op) == REG) | |
1062 | { | |
1063 | /* If the register is not valid for MODE, return 0. If we don't | |
1064 | do this, there is no way to fix up the resulting REG later. */ | |
1065 | if (REGNO (op) < FIRST_PSEUDO_REGISTER | |
1066 | && ! HARD_REGNO_MODE_OK (REGNO (op) + i, word_mode)) | |
1067 | return 0; | |
1068 | else if (REGNO (op) >= FIRST_PSEUDO_REGISTER | |
1069 | || (REG_FUNCTION_VALUE_P (op) | |
cb00f51a RK |
1070 | && rtx_equal_function_value_matters) |
1071 | /* We want to keep the stack, frame, and arg pointers | |
1072 | special. */ | |
65e8fe02 | 1073 | || op == frame_pointer_rtx |
cb00f51a | 1074 | #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM |
65e8fe02 | 1075 | || op == arg_pointer_rtx |
cb00f51a | 1076 | #endif |
65e8fe02 | 1077 | || op == stack_pointer_rtx) |
23b2ce53 RS |
1078 | return gen_rtx (SUBREG, word_mode, op, i); |
1079 | else | |
1080 | return gen_rtx (REG, word_mode, REGNO (op) + i); | |
1081 | } | |
1082 | else if (GET_CODE (op) == SUBREG) | |
1083 | return gen_rtx (SUBREG, word_mode, SUBREG_REG (op), i + SUBREG_WORD (op)); | |
fc84e8a8 RS |
1084 | else if (GET_CODE (op) == CONCAT) |
1085 | { | |
1086 | int partwords = GET_MODE_UNIT_SIZE (GET_MODE (op)) / UNITS_PER_WORD; | |
1087 | if (i < partwords) | |
1088 | return operand_subword (XEXP (op, 0), i, validate_address, mode); | |
1089 | return operand_subword (XEXP (op, 1), i - partwords, | |
1090 | validate_address, mode); | |
1091 | } | |
23b2ce53 RS |
1092 | |
1093 | /* Form a new MEM at the requested address. */ | |
1094 | if (GET_CODE (op) == MEM) | |
1095 | { | |
1096 | rtx addr = plus_constant (XEXP (op, 0), i * UNITS_PER_WORD); | |
1097 | rtx new; | |
1098 | ||
1099 | if (validate_address) | |
1100 | { | |
1101 | if (reload_completed) | |
1102 | { | |
1103 | if (! strict_memory_address_p (word_mode, addr)) | |
1104 | return 0; | |
1105 | } | |
1106 | else | |
1107 | addr = memory_address (word_mode, addr); | |
1108 | } | |
1109 | ||
1110 | new = gen_rtx (MEM, word_mode, addr); | |
1111 | ||
1112 | MEM_VOLATILE_P (new) = MEM_VOLATILE_P (op); | |
1113 | MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (op); | |
1114 | RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (op); | |
1115 | ||
1116 | return new; | |
1117 | } | |
1118 | ||
1119 | /* The only remaining cases are when OP is a constant. If the host and | |
1120 | target floating formats are the same, handling two-word floating | |
7677ffa4 | 1121 | constants are easy. Note that REAL_VALUE_TO_TARGET_{SINGLE,DOUBLE} |
9847c2f6 RK |
1122 | are defined as returning one or two 32 bit values, respectively, |
1123 | and not values of BITS_PER_WORD bits. */ | |
1632afca | 1124 | #ifdef REAL_ARITHMETIC |
9847c2f6 RK |
1125 | /* The output is some bits, the width of the target machine's word. |
1126 | A wider-word host can surely hold them in a CONST_INT. A narrower-word | |
1127 | host can't. */ | |
1128 | if (HOST_BITS_PER_WIDE_INT >= BITS_PER_WORD | |
1632afca | 1129 | && GET_MODE_CLASS (mode) == MODE_FLOAT |
7677ffa4 | 1130 | && GET_MODE_BITSIZE (mode) == 64 |
1632afca RS |
1131 | && GET_CODE (op) == CONST_DOUBLE) |
1132 | { | |
9847c2f6 | 1133 | long k[2]; |
1632afca RS |
1134 | REAL_VALUE_TYPE rv; |
1135 | ||
1136 | REAL_VALUE_FROM_CONST_DOUBLE (rv, op); | |
1137 | REAL_VALUE_TO_TARGET_DOUBLE (rv, k); | |
7677ffa4 | 1138 | |
9847c2f6 | 1139 | /* We handle 32-bit and >= 64-bit words here. Note that the order in |
7677ffa4 RK |
1140 | which the words are written depends on the word endianness. |
1141 | ||
1142 | ??? This is a potential portability problem and should | |
1143 | be fixed at some point. */ | |
9847c2f6 RK |
1144 | if (BITS_PER_WORD == 32) |
1145 | return GEN_INT ((HOST_WIDE_INT) k[i]); | |
1146 | #if HOST_BITS_PER_WIDE_INT > 32 | |
1147 | else if (BITS_PER_WORD >= 64 && i == 0) | |
1148 | return GEN_INT ((((HOST_WIDE_INT) k[! WORDS_BIG_ENDIAN]) << 32) | |
1149 | | (HOST_WIDE_INT) k[WORDS_BIG_ENDIAN]); | |
1150 | #endif | |
47b34d40 JW |
1151 | else if (BITS_PER_WORD == 16) |
1152 | { | |
1153 | long value; | |
1154 | value = k[i >> 1]; | |
1155 | if ((i & 0x1) == 0) | |
1156 | value >>= 16; | |
1157 | value &= 0xffff; | |
1158 | return GEN_INT ((HOST_WIDE_INT) value); | |
1159 | } | |
7677ffa4 RK |
1160 | else |
1161 | abort (); | |
1632afca | 1162 | } |
a5559dbc RE |
1163 | else if (HOST_BITS_PER_WIDE_INT >= BITS_PER_WORD |
1164 | && GET_MODE_CLASS (mode) == MODE_FLOAT | |
1165 | && GET_MODE_BITSIZE (mode) > 64 | |
1166 | && GET_CODE (op) == CONST_DOUBLE) | |
1167 | { | |
1168 | long k[4]; | |
1169 | REAL_VALUE_TYPE rv; | |
1170 | ||
1171 | REAL_VALUE_FROM_CONST_DOUBLE (rv, op); | |
1172 | REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, k); | |
1173 | ||
1174 | if (BITS_PER_WORD == 32) | |
1175 | return GEN_INT ((HOST_WIDE_INT) k[i]); | |
1176 | } | |
1632afca | 1177 | #else /* no REAL_ARITHMETIC */ |
23b2ce53 | 1178 | if (((HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT |
906c4e36 | 1179 | && HOST_BITS_PER_WIDE_INT == BITS_PER_WORD) |
23b2ce53 RS |
1180 | || flag_pretend_float) |
1181 | && GET_MODE_CLASS (mode) == MODE_FLOAT | |
1182 | && GET_MODE_SIZE (mode) == 2 * UNITS_PER_WORD | |
1183 | && GET_CODE (op) == CONST_DOUBLE) | |
7529ac93 CH |
1184 | { |
1185 | /* The constant is stored in the host's word-ordering, | |
1186 | but we want to access it in the target's word-ordering. Some | |
1187 | compilers don't like a conditional inside macro args, so we have two | |
1188 | copies of the return. */ | |
2fe02d7e | 1189 | #ifdef HOST_WORDS_BIG_ENDIAN |
7529ac93 CH |
1190 | return GEN_INT (i == WORDS_BIG_ENDIAN |
1191 | ? CONST_DOUBLE_HIGH (op) : CONST_DOUBLE_LOW (op)); | |
2fe02d7e | 1192 | #else |
7529ac93 CH |
1193 | return GEN_INT (i != WORDS_BIG_ENDIAN |
1194 | ? CONST_DOUBLE_HIGH (op) : CONST_DOUBLE_LOW (op)); | |
2fe02d7e | 1195 | #endif |
7529ac93 | 1196 | } |
1632afca | 1197 | #endif /* no REAL_ARITHMETIC */ |
23b2ce53 RS |
1198 | |
1199 | /* Single word float is a little harder, since single- and double-word | |
1200 | values often do not have the same high-order bits. We have already | |
1201 | verified that we want the only defined word of the single-word value. */ | |
1632afca | 1202 | #ifdef REAL_ARITHMETIC |
9847c2f6 | 1203 | if (GET_MODE_CLASS (mode) == MODE_FLOAT |
7677ffa4 | 1204 | && GET_MODE_BITSIZE (mode) == 32 |
1632afca RS |
1205 | && GET_CODE (op) == CONST_DOUBLE) |
1206 | { | |
9847c2f6 | 1207 | long l; |
1632afca RS |
1208 | REAL_VALUE_TYPE rv; |
1209 | ||
1210 | REAL_VALUE_FROM_CONST_DOUBLE (rv, op); | |
1211 | REAL_VALUE_TO_TARGET_SINGLE (rv, l); | |
9847c2f6 | 1212 | return GEN_INT ((HOST_WIDE_INT) l); |
1632afca RS |
1213 | } |
1214 | #else | |
23b2ce53 | 1215 | if (((HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT |
906c4e36 | 1216 | && HOST_BITS_PER_WIDE_INT == BITS_PER_WORD) |
23b2ce53 RS |
1217 | || flag_pretend_float) |
1218 | && GET_MODE_CLASS (mode) == MODE_FLOAT | |
1219 | && GET_MODE_SIZE (mode) == UNITS_PER_WORD | |
1220 | && GET_CODE (op) == CONST_DOUBLE) | |
1221 | { | |
1222 | double d; | |
906c4e36 | 1223 | union {float f; HOST_WIDE_INT i; } u; |
23b2ce53 RS |
1224 | |
1225 | REAL_VALUE_FROM_CONST_DOUBLE (d, op); | |
1226 | ||
1227 | u.f = d; | |
906c4e36 | 1228 | return GEN_INT (u.i); |
23b2ce53 | 1229 | } |
1632afca | 1230 | #endif /* no REAL_ARITHMETIC */ |
23b2ce53 RS |
1231 | |
1232 | /* The only remaining cases that we can handle are integers. | |
1233 | Convert to proper endianness now since these cases need it. | |
1234 | At this point, i == 0 means the low-order word. | |
1235 | ||
2d4f57f8 RK |
1236 | We do not want to handle the case when BITS_PER_WORD <= HOST_BITS_PER_INT |
1237 | in general. However, if OP is (const_int 0), we can just return | |
1238 | it for any word. */ | |
1239 | ||
1240 | if (op == const0_rtx) | |
1241 | return op; | |
23b2ce53 RS |
1242 | |
1243 | if (GET_MODE_CLASS (mode) != MODE_INT | |
2d4f57f8 | 1244 | || (GET_CODE (op) != CONST_INT && GET_CODE (op) != CONST_DOUBLE) |
0cf214a0 | 1245 | || BITS_PER_WORD > HOST_BITS_PER_WIDE_INT) |
23b2ce53 RS |
1246 | return 0; |
1247 | ||
1248 | if (WORDS_BIG_ENDIAN) | |
1249 | i = GET_MODE_SIZE (mode) / UNITS_PER_WORD - 1 - i; | |
1250 | ||
1251 | /* Find out which word on the host machine this value is in and get | |
1252 | it from the constant. */ | |
1253 | val = (i / size_ratio == 0 | |
1254 | ? (GET_CODE (op) == CONST_INT ? INTVAL (op) : CONST_DOUBLE_LOW (op)) | |
1255 | : (GET_CODE (op) == CONST_INT | |
1256 | ? (INTVAL (op) < 0 ? ~0 : 0) : CONST_DOUBLE_HIGH (op))); | |
1257 | ||
1258 | /* If BITS_PER_WORD is smaller than an int, get the appropriate bits. */ | |
906c4e36 | 1259 | if (BITS_PER_WORD < HOST_BITS_PER_WIDE_INT) |
23b2ce53 | 1260 | val = ((val >> ((i % size_ratio) * BITS_PER_WORD)) |
906c4e36 RK |
1261 | & (((HOST_WIDE_INT) 1 |
1262 | << (BITS_PER_WORD % HOST_BITS_PER_WIDE_INT)) - 1)); | |
23b2ce53 | 1263 | |
906c4e36 | 1264 | return GEN_INT (val); |
23b2ce53 RS |
1265 | } |
1266 | ||
1267 | /* Similar to `operand_subword', but never return 0. If we can't extract | |
1268 | the required subword, put OP into a register and try again. If that fails, | |
1269 | abort. We always validate the address in this case. It is not valid | |
1270 | to call this function after reload; it is mostly meant for RTL | |
1271 | generation. | |
1272 | ||
1273 | MODE is the mode of OP, in case it is CONST_INT. */ | |
1274 | ||
1275 | rtx | |
1276 | operand_subword_force (op, i, mode) | |
1277 | rtx op; | |
1278 | int i; | |
1279 | enum machine_mode mode; | |
1280 | { | |
1281 | rtx result = operand_subword (op, i, 1, mode); | |
1282 | ||
1283 | if (result) | |
1284 | return result; | |
1285 | ||
1286 | if (mode != BLKmode && mode != VOIDmode) | |
1287 | op = force_reg (mode, op); | |
1288 | ||
1289 | result = operand_subword (op, i, 1, mode); | |
1290 | if (result == 0) | |
1291 | abort (); | |
1292 | ||
1293 | return result; | |
1294 | } | |
1295 | \f | |
1296 | /* Given a compare instruction, swap the operands. | |
1297 | A test instruction is changed into a compare of 0 against the operand. */ | |
1298 | ||
1299 | void | |
1300 | reverse_comparison (insn) | |
1301 | rtx insn; | |
1302 | { | |
1303 | rtx body = PATTERN (insn); | |
1304 | rtx comp; | |
1305 | ||
1306 | if (GET_CODE (body) == SET) | |
1307 | comp = SET_SRC (body); | |
1308 | else | |
1309 | comp = SET_SRC (XVECEXP (body, 0, 0)); | |
1310 | ||
1311 | if (GET_CODE (comp) == COMPARE) | |
1312 | { | |
1313 | rtx op0 = XEXP (comp, 0); | |
1314 | rtx op1 = XEXP (comp, 1); | |
1315 | XEXP (comp, 0) = op1; | |
1316 | XEXP (comp, 1) = op0; | |
1317 | } | |
1318 | else | |
1319 | { | |
1320 | rtx new = gen_rtx (COMPARE, VOIDmode, | |
1321 | CONST0_RTX (GET_MODE (comp)), comp); | |
1322 | if (GET_CODE (body) == SET) | |
1323 | SET_SRC (body) = new; | |
1324 | else | |
1325 | SET_SRC (XVECEXP (body, 0, 0)) = new; | |
1326 | } | |
1327 | } | |
1328 | \f | |
1329 | /* Return a memory reference like MEMREF, but with its mode changed | |
1330 | to MODE and its address changed to ADDR. | |
1331 | (VOIDmode means don't change the mode. | |
1332 | NULL for ADDR means don't change the address.) */ | |
1333 | ||
1334 | rtx | |
1335 | change_address (memref, mode, addr) | |
1336 | rtx memref; | |
1337 | enum machine_mode mode; | |
1338 | rtx addr; | |
1339 | { | |
1340 | rtx new; | |
1341 | ||
1342 | if (GET_CODE (memref) != MEM) | |
1343 | abort (); | |
1344 | if (mode == VOIDmode) | |
1345 | mode = GET_MODE (memref); | |
1346 | if (addr == 0) | |
1347 | addr = XEXP (memref, 0); | |
1348 | ||
1349 | /* If reload is in progress or has completed, ADDR must be valid. | |
1350 | Otherwise, we can call memory_address to make it valid. */ | |
1351 | if (reload_completed || reload_in_progress) | |
1352 | { | |
1353 | if (! memory_address_p (mode, addr)) | |
1354 | abort (); | |
1355 | } | |
1356 | else | |
1357 | addr = memory_address (mode, addr); | |
1358 | ||
1359 | new = gen_rtx (MEM, mode, addr); | |
1360 | MEM_VOLATILE_P (new) = MEM_VOLATILE_P (memref); | |
1361 | RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (memref); | |
1362 | MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (memref); | |
1363 | return new; | |
1364 | } | |
1365 | \f | |
1366 | /* Return a newly created CODE_LABEL rtx with a unique label number. */ | |
1367 | ||
1368 | rtx | |
1369 | gen_label_rtx () | |
1370 | { | |
ca695ac9 JB |
1371 | register rtx label; |
1372 | ||
8b6813aa RS |
1373 | label = (output_bytecode |
1374 | ? gen_rtx (CODE_LABEL, VOIDmode, NULL, bc_get_bytecode_label ()) | |
1375 | : gen_rtx (CODE_LABEL, VOIDmode, 0, 0, 0, label_num++, NULL_PTR)); | |
ca695ac9 | 1376 | |
23b2ce53 RS |
1377 | LABEL_NUSES (label) = 0; |
1378 | return label; | |
1379 | } | |
1380 | \f | |
1381 | /* For procedure integration. */ | |
1382 | ||
1383 | /* Return a newly created INLINE_HEADER rtx. Should allocate this | |
1384 | from a permanent obstack when the opportunity arises. */ | |
1385 | ||
1386 | rtx | |
1387 | gen_inline_header_rtx (first_insn, first_parm_insn, first_labelno, | |
1388 | last_labelno, max_parm_regnum, max_regnum, args_size, | |
a6108925 | 1389 | pops_args, stack_slots, forced_labels, function_flags, |
23b2ce53 | 1390 | outgoing_args_size, original_arg_vector, |
86fe05e0 RK |
1391 | original_decl_initial, regno_rtx, regno_flag, |
1392 | regno_align) | |
23b2ce53 RS |
1393 | rtx first_insn, first_parm_insn; |
1394 | int first_labelno, last_labelno, max_parm_regnum, max_regnum, args_size; | |
1395 | int pops_args; | |
1396 | rtx stack_slots; | |
a6108925 | 1397 | rtx forced_labels; |
23b2ce53 RS |
1398 | int function_flags; |
1399 | int outgoing_args_size; | |
1400 | rtvec original_arg_vector; | |
1401 | rtx original_decl_initial; | |
86fe05e0 RK |
1402 | rtvec regno_rtx; |
1403 | char *regno_flag; | |
1404 | char *regno_align; | |
23b2ce53 RS |
1405 | { |
1406 | rtx header = gen_rtx (INLINE_HEADER, VOIDmode, | |
906c4e36 | 1407 | cur_insn_uid++, NULL_RTX, |
23b2ce53 RS |
1408 | first_insn, first_parm_insn, |
1409 | first_labelno, last_labelno, | |
1410 | max_parm_regnum, max_regnum, args_size, pops_args, | |
a6108925 | 1411 | stack_slots, forced_labels, function_flags, |
86fe05e0 RK |
1412 | outgoing_args_size, original_arg_vector, |
1413 | original_decl_initial, | |
1414 | regno_rtx, regno_flag, regno_align); | |
23b2ce53 RS |
1415 | return header; |
1416 | } | |
1417 | ||
1418 | /* Install new pointers to the first and last insns in the chain. | |
86fe05e0 | 1419 | Also, set cur_insn_uid to one higher than the last in use. |
23b2ce53 RS |
1420 | Used for an inline-procedure after copying the insn chain. */ |
1421 | ||
1422 | void | |
1423 | set_new_first_and_last_insn (first, last) | |
1424 | rtx first, last; | |
1425 | { | |
86fe05e0 RK |
1426 | rtx insn; |
1427 | ||
23b2ce53 RS |
1428 | first_insn = first; |
1429 | last_insn = last; | |
86fe05e0 RK |
1430 | cur_insn_uid = 0; |
1431 | ||
1432 | for (insn = first; insn; insn = NEXT_INSN (insn)) | |
1433 | cur_insn_uid = MAX (cur_insn_uid, INSN_UID (insn)); | |
1434 | ||
1435 | cur_insn_uid++; | |
23b2ce53 RS |
1436 | } |
1437 | ||
1438 | /* Set the range of label numbers found in the current function. | |
1439 | This is used when belatedly compiling an inline function. */ | |
1440 | ||
1441 | void | |
1442 | set_new_first_and_last_label_num (first, last) | |
1443 | int first, last; | |
1444 | { | |
1445 | base_label_num = label_num; | |
1446 | first_label_num = first; | |
1447 | last_label_num = last; | |
1448 | } | |
1449 | \f | |
1450 | /* Save all variables describing the current status into the structure *P. | |
1451 | This is used before starting a nested function. */ | |
1452 | ||
1453 | void | |
1454 | save_emit_status (p) | |
1455 | struct function *p; | |
1456 | { | |
1457 | p->reg_rtx_no = reg_rtx_no; | |
1458 | p->first_label_num = first_label_num; | |
1459 | p->first_insn = first_insn; | |
1460 | p->last_insn = last_insn; | |
a25c7971 | 1461 | p->sequence_rtl_expr = sequence_rtl_expr; |
23b2ce53 RS |
1462 | p->sequence_stack = sequence_stack; |
1463 | p->cur_insn_uid = cur_insn_uid; | |
1464 | p->last_linenum = last_linenum; | |
1465 | p->last_filename = last_filename; | |
1466 | p->regno_pointer_flag = regno_pointer_flag; | |
86fe05e0 | 1467 | p->regno_pointer_align = regno_pointer_align; |
23b2ce53 RS |
1468 | p->regno_pointer_flag_length = regno_pointer_flag_length; |
1469 | p->regno_reg_rtx = regno_reg_rtx; | |
1470 | } | |
1471 | ||
1472 | /* Restore all variables describing the current status from the structure *P. | |
1473 | This is used after a nested function. */ | |
1474 | ||
1475 | void | |
1476 | restore_emit_status (p) | |
1477 | struct function *p; | |
1478 | { | |
1479 | int i; | |
1480 | ||
1481 | reg_rtx_no = p->reg_rtx_no; | |
1482 | first_label_num = p->first_label_num; | |
457a2d9c | 1483 | last_label_num = 0; |
23b2ce53 RS |
1484 | first_insn = p->first_insn; |
1485 | last_insn = p->last_insn; | |
a25c7971 | 1486 | sequence_rtl_expr = p->sequence_rtl_expr; |
23b2ce53 RS |
1487 | sequence_stack = p->sequence_stack; |
1488 | cur_insn_uid = p->cur_insn_uid; | |
1489 | last_linenum = p->last_linenum; | |
1490 | last_filename = p->last_filename; | |
1491 | regno_pointer_flag = p->regno_pointer_flag; | |
86fe05e0 | 1492 | regno_pointer_align = p->regno_pointer_align; |
23b2ce53 RS |
1493 | regno_pointer_flag_length = p->regno_pointer_flag_length; |
1494 | regno_reg_rtx = p->regno_reg_rtx; | |
1495 | ||
0f41302f MS |
1496 | /* Clear our cache of rtx expressions for start_sequence and |
1497 | gen_sequence. */ | |
23b2ce53 RS |
1498 | sequence_element_free_list = 0; |
1499 | for (i = 0; i < SEQUENCE_RESULT_SIZE; i++) | |
1500 | sequence_result[i] = 0; | |
43127294 RK |
1501 | |
1502 | free_insn = 0; | |
23b2ce53 RS |
1503 | } |
1504 | \f | |
1505 | /* Go through all the RTL insn bodies and copy any invalid shared structure. | |
1506 | It does not work to do this twice, because the mark bits set here | |
1507 | are not cleared afterwards. */ | |
1508 | ||
1509 | void | |
1510 | unshare_all_rtl (insn) | |
1511 | register rtx insn; | |
1512 | { | |
1513 | for (; insn; insn = NEXT_INSN (insn)) | |
1514 | if (GET_CODE (insn) == INSN || GET_CODE (insn) == JUMP_INSN | |
1515 | || GET_CODE (insn) == CALL_INSN) | |
1516 | { | |
1517 | PATTERN (insn) = copy_rtx_if_shared (PATTERN (insn)); | |
1518 | REG_NOTES (insn) = copy_rtx_if_shared (REG_NOTES (insn)); | |
1519 | LOG_LINKS (insn) = copy_rtx_if_shared (LOG_LINKS (insn)); | |
1520 | } | |
1521 | ||
1522 | /* Make sure the addresses of stack slots found outside the insn chain | |
1523 | (such as, in DECL_RTL of a variable) are not shared | |
1524 | with the insn chain. | |
1525 | ||
1526 | This special care is necessary when the stack slot MEM does not | |
1527 | actually appear in the insn chain. If it does appear, its address | |
1528 | is unshared from all else at that point. */ | |
1529 | ||
1530 | copy_rtx_if_shared (stack_slot_list); | |
1531 | } | |
1532 | ||
1533 | /* Mark ORIG as in use, and return a copy of it if it was already in use. | |
1534 | Recursively does the same for subexpressions. */ | |
1535 | ||
1536 | rtx | |
1537 | copy_rtx_if_shared (orig) | |
1538 | rtx orig; | |
1539 | { | |
1540 | register rtx x = orig; | |
1541 | register int i; | |
1542 | register enum rtx_code code; | |
1543 | register char *format_ptr; | |
1544 | int copied = 0; | |
1545 | ||
1546 | if (x == 0) | |
1547 | return 0; | |
1548 | ||
1549 | code = GET_CODE (x); | |
1550 | ||
1551 | /* These types may be freely shared. */ | |
1552 | ||
1553 | switch (code) | |
1554 | { | |
1555 | case REG: | |
1556 | case QUEUED: | |
1557 | case CONST_INT: | |
1558 | case CONST_DOUBLE: | |
1559 | case SYMBOL_REF: | |
1560 | case CODE_LABEL: | |
1561 | case PC: | |
1562 | case CC0: | |
1563 | case SCRATCH: | |
0f41302f | 1564 | /* SCRATCH must be shared because they represent distinct values. */ |
23b2ce53 RS |
1565 | return x; |
1566 | ||
b851ea09 RK |
1567 | case CONST: |
1568 | /* CONST can be shared if it contains a SYMBOL_REF. If it contains | |
1569 | a LABEL_REF, it isn't sharable. */ | |
1570 | if (GET_CODE (XEXP (x, 0)) == PLUS | |
1571 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF | |
1572 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT) | |
1573 | return x; | |
1574 | break; | |
1575 | ||
23b2ce53 RS |
1576 | case INSN: |
1577 | case JUMP_INSN: | |
1578 | case CALL_INSN: | |
1579 | case NOTE: | |
23b2ce53 RS |
1580 | case BARRIER: |
1581 | /* The chain of insns is not being copied. */ | |
1582 | return x; | |
1583 | ||
1584 | case MEM: | |
1585 | /* A MEM is allowed to be shared if its address is constant | |
1586 | or is a constant plus one of the special registers. */ | |
1587 | if (CONSTANT_ADDRESS_P (XEXP (x, 0)) | |
1588 | || XEXP (x, 0) == virtual_stack_vars_rtx | |
1589 | || XEXP (x, 0) == virtual_incoming_args_rtx) | |
1590 | return x; | |
1591 | ||
1592 | if (GET_CODE (XEXP (x, 0)) == PLUS | |
1593 | && (XEXP (XEXP (x, 0), 0) == virtual_stack_vars_rtx | |
1594 | || XEXP (XEXP (x, 0), 0) == virtual_incoming_args_rtx) | |
1595 | && CONSTANT_ADDRESS_P (XEXP (XEXP (x, 0), 1))) | |
1596 | { | |
1597 | /* This MEM can appear in more than one place, | |
1598 | but its address better not be shared with anything else. */ | |
1599 | if (! x->used) | |
1600 | XEXP (x, 0) = copy_rtx_if_shared (XEXP (x, 0)); | |
1601 | x->used = 1; | |
1602 | return x; | |
1603 | } | |
1604 | } | |
1605 | ||
1606 | /* This rtx may not be shared. If it has already been seen, | |
1607 | replace it with a copy of itself. */ | |
1608 | ||
1609 | if (x->used) | |
1610 | { | |
1611 | register rtx copy; | |
1612 | ||
1613 | copy = rtx_alloc (code); | |
4c9a05bc RK |
1614 | bcopy ((char *) x, (char *) copy, |
1615 | (sizeof (*copy) - sizeof (copy->fld) | |
1616 | + sizeof (copy->fld[0]) * GET_RTX_LENGTH (code))); | |
23b2ce53 RS |
1617 | x = copy; |
1618 | copied = 1; | |
1619 | } | |
1620 | x->used = 1; | |
1621 | ||
1622 | /* Now scan the subexpressions recursively. | |
1623 | We can store any replaced subexpressions directly into X | |
1624 | since we know X is not shared! Any vectors in X | |
1625 | must be copied if X was copied. */ | |
1626 | ||
1627 | format_ptr = GET_RTX_FORMAT (code); | |
1628 | ||
1629 | for (i = 0; i < GET_RTX_LENGTH (code); i++) | |
1630 | { | |
1631 | switch (*format_ptr++) | |
1632 | { | |
1633 | case 'e': | |
1634 | XEXP (x, i) = copy_rtx_if_shared (XEXP (x, i)); | |
1635 | break; | |
1636 | ||
1637 | case 'E': | |
1638 | if (XVEC (x, i) != NULL) | |
1639 | { | |
1640 | register int j; | |
f0722107 | 1641 | int len = XVECLEN (x, i); |
23b2ce53 | 1642 | |
f0722107 RS |
1643 | if (copied && len > 0) |
1644 | XVEC (x, i) = gen_rtvec_v (len, &XVECEXP (x, i, 0)); | |
1645 | for (j = 0; j < len; j++) | |
1646 | XVECEXP (x, i, j) = copy_rtx_if_shared (XVECEXP (x, i, j)); | |
23b2ce53 RS |
1647 | } |
1648 | break; | |
1649 | } | |
1650 | } | |
1651 | return x; | |
1652 | } | |
1653 | ||
1654 | /* Clear all the USED bits in X to allow copy_rtx_if_shared to be used | |
1655 | to look for shared sub-parts. */ | |
1656 | ||
1657 | void | |
1658 | reset_used_flags (x) | |
1659 | rtx x; | |
1660 | { | |
1661 | register int i, j; | |
1662 | register enum rtx_code code; | |
1663 | register char *format_ptr; | |
23b2ce53 RS |
1664 | |
1665 | if (x == 0) | |
1666 | return; | |
1667 | ||
1668 | code = GET_CODE (x); | |
1669 | ||
9faa82d8 | 1670 | /* These types may be freely shared so we needn't do any resetting |
23b2ce53 RS |
1671 | for them. */ |
1672 | ||
1673 | switch (code) | |
1674 | { | |
1675 | case REG: | |
1676 | case QUEUED: | |
1677 | case CONST_INT: | |
1678 | case CONST_DOUBLE: | |
1679 | case SYMBOL_REF: | |
1680 | case CODE_LABEL: | |
1681 | case PC: | |
1682 | case CC0: | |
1683 | return; | |
1684 | ||
1685 | case INSN: | |
1686 | case JUMP_INSN: | |
1687 | case CALL_INSN: | |
1688 | case NOTE: | |
1689 | case LABEL_REF: | |
1690 | case BARRIER: | |
1691 | /* The chain of insns is not being copied. */ | |
1692 | return; | |
1693 | } | |
1694 | ||
1695 | x->used = 0; | |
1696 | ||
1697 | format_ptr = GET_RTX_FORMAT (code); | |
1698 | for (i = 0; i < GET_RTX_LENGTH (code); i++) | |
1699 | { | |
1700 | switch (*format_ptr++) | |
1701 | { | |
1702 | case 'e': | |
1703 | reset_used_flags (XEXP (x, i)); | |
1704 | break; | |
1705 | ||
1706 | case 'E': | |
1707 | for (j = 0; j < XVECLEN (x, i); j++) | |
1708 | reset_used_flags (XVECEXP (x, i, j)); | |
1709 | break; | |
1710 | } | |
1711 | } | |
1712 | } | |
1713 | \f | |
1714 | /* Copy X if necessary so that it won't be altered by changes in OTHER. | |
1715 | Return X or the rtx for the pseudo reg the value of X was copied into. | |
1716 | OTHER must be valid as a SET_DEST. */ | |
1717 | ||
1718 | rtx | |
1719 | make_safe_from (x, other) | |
1720 | rtx x, other; | |
1721 | { | |
1722 | while (1) | |
1723 | switch (GET_CODE (other)) | |
1724 | { | |
1725 | case SUBREG: | |
1726 | other = SUBREG_REG (other); | |
1727 | break; | |
1728 | case STRICT_LOW_PART: | |
1729 | case SIGN_EXTEND: | |
1730 | case ZERO_EXTEND: | |
1731 | other = XEXP (other, 0); | |
1732 | break; | |
1733 | default: | |
1734 | goto done; | |
1735 | } | |
1736 | done: | |
1737 | if ((GET_CODE (other) == MEM | |
1738 | && ! CONSTANT_P (x) | |
1739 | && GET_CODE (x) != REG | |
1740 | && GET_CODE (x) != SUBREG) | |
1741 | || (GET_CODE (other) == REG | |
1742 | && (REGNO (other) < FIRST_PSEUDO_REGISTER | |
1743 | || reg_mentioned_p (other, x)))) | |
1744 | { | |
1745 | rtx temp = gen_reg_rtx (GET_MODE (x)); | |
1746 | emit_move_insn (temp, x); | |
1747 | return temp; | |
1748 | } | |
1749 | return x; | |
1750 | } | |
1751 | \f | |
1752 | /* Emission of insns (adding them to the doubly-linked list). */ | |
1753 | ||
1754 | /* Return the first insn of the current sequence or current function. */ | |
1755 | ||
1756 | rtx | |
1757 | get_insns () | |
1758 | { | |
1759 | return first_insn; | |
1760 | } | |
1761 | ||
1762 | /* Return the last insn emitted in current sequence or current function. */ | |
1763 | ||
1764 | rtx | |
1765 | get_last_insn () | |
1766 | { | |
1767 | return last_insn; | |
1768 | } | |
1769 | ||
1770 | /* Specify a new insn as the last in the chain. */ | |
1771 | ||
1772 | void | |
1773 | set_last_insn (insn) | |
1774 | rtx insn; | |
1775 | { | |
1776 | if (NEXT_INSN (insn) != 0) | |
1777 | abort (); | |
1778 | last_insn = insn; | |
1779 | } | |
1780 | ||
1781 | /* Return the last insn emitted, even if it is in a sequence now pushed. */ | |
1782 | ||
1783 | rtx | |
1784 | get_last_insn_anywhere () | |
1785 | { | |
1786 | struct sequence_stack *stack; | |
1787 | if (last_insn) | |
1788 | return last_insn; | |
1789 | for (stack = sequence_stack; stack; stack = stack->next) | |
1790 | if (stack->last != 0) | |
1791 | return stack->last; | |
1792 | return 0; | |
1793 | } | |
1794 | ||
1795 | /* Return a number larger than any instruction's uid in this function. */ | |
1796 | ||
1797 | int | |
1798 | get_max_uid () | |
1799 | { | |
1800 | return cur_insn_uid; | |
1801 | } | |
1802 | \f | |
1803 | /* Return the next insn. If it is a SEQUENCE, return the first insn | |
1804 | of the sequence. */ | |
1805 | ||
1806 | rtx | |
1807 | next_insn (insn) | |
1808 | rtx insn; | |
1809 | { | |
1810 | if (insn) | |
1811 | { | |
1812 | insn = NEXT_INSN (insn); | |
1813 | if (insn && GET_CODE (insn) == INSN | |
1814 | && GET_CODE (PATTERN (insn)) == SEQUENCE) | |
1815 | insn = XVECEXP (PATTERN (insn), 0, 0); | |
1816 | } | |
1817 | ||
1818 | return insn; | |
1819 | } | |
1820 | ||
1821 | /* Return the previous insn. If it is a SEQUENCE, return the last insn | |
1822 | of the sequence. */ | |
1823 | ||
1824 | rtx | |
1825 | previous_insn (insn) | |
1826 | rtx insn; | |
1827 | { | |
1828 | if (insn) | |
1829 | { | |
1830 | insn = PREV_INSN (insn); | |
1831 | if (insn && GET_CODE (insn) == INSN | |
1832 | && GET_CODE (PATTERN (insn)) == SEQUENCE) | |
1833 | insn = XVECEXP (PATTERN (insn), 0, XVECLEN (PATTERN (insn), 0) - 1); | |
1834 | } | |
1835 | ||
1836 | return insn; | |
1837 | } | |
1838 | ||
1839 | /* Return the next insn after INSN that is not a NOTE. This routine does not | |
1840 | look inside SEQUENCEs. */ | |
1841 | ||
1842 | rtx | |
1843 | next_nonnote_insn (insn) | |
1844 | rtx insn; | |
1845 | { | |
1846 | while (insn) | |
1847 | { | |
1848 | insn = NEXT_INSN (insn); | |
1849 | if (insn == 0 || GET_CODE (insn) != NOTE) | |
1850 | break; | |
1851 | } | |
1852 | ||
1853 | return insn; | |
1854 | } | |
1855 | ||
1856 | /* Return the previous insn before INSN that is not a NOTE. This routine does | |
1857 | not look inside SEQUENCEs. */ | |
1858 | ||
1859 | rtx | |
1860 | prev_nonnote_insn (insn) | |
1861 | rtx insn; | |
1862 | { | |
1863 | while (insn) | |
1864 | { | |
1865 | insn = PREV_INSN (insn); | |
1866 | if (insn == 0 || GET_CODE (insn) != NOTE) | |
1867 | break; | |
1868 | } | |
1869 | ||
1870 | return insn; | |
1871 | } | |
1872 | ||
1873 | /* Return the next INSN, CALL_INSN or JUMP_INSN after INSN; | |
1874 | or 0, if there is none. This routine does not look inside | |
0f41302f | 1875 | SEQUENCEs. */ |
23b2ce53 RS |
1876 | |
1877 | rtx | |
1878 | next_real_insn (insn) | |
1879 | rtx insn; | |
1880 | { | |
1881 | while (insn) | |
1882 | { | |
1883 | insn = NEXT_INSN (insn); | |
1884 | if (insn == 0 || GET_CODE (insn) == INSN | |
1885 | || GET_CODE (insn) == CALL_INSN || GET_CODE (insn) == JUMP_INSN) | |
1886 | break; | |
1887 | } | |
1888 | ||
1889 | return insn; | |
1890 | } | |
1891 | ||
1892 | /* Return the last INSN, CALL_INSN or JUMP_INSN before INSN; | |
1893 | or 0, if there is none. This routine does not look inside | |
1894 | SEQUENCEs. */ | |
1895 | ||
1896 | rtx | |
1897 | prev_real_insn (insn) | |
1898 | rtx insn; | |
1899 | { | |
1900 | while (insn) | |
1901 | { | |
1902 | insn = PREV_INSN (insn); | |
1903 | if (insn == 0 || GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN | |
1904 | || GET_CODE (insn) == JUMP_INSN) | |
1905 | break; | |
1906 | } | |
1907 | ||
1908 | return insn; | |
1909 | } | |
1910 | ||
1911 | /* Find the next insn after INSN that really does something. This routine | |
1912 | does not look inside SEQUENCEs. Until reload has completed, this is the | |
1913 | same as next_real_insn. */ | |
1914 | ||
1915 | rtx | |
1916 | next_active_insn (insn) | |
1917 | rtx insn; | |
1918 | { | |
1919 | while (insn) | |
1920 | { | |
1921 | insn = NEXT_INSN (insn); | |
1922 | if (insn == 0 | |
1923 | || GET_CODE (insn) == CALL_INSN || GET_CODE (insn) == JUMP_INSN | |
1924 | || (GET_CODE (insn) == INSN | |
1925 | && (! reload_completed | |
1926 | || (GET_CODE (PATTERN (insn)) != USE | |
1927 | && GET_CODE (PATTERN (insn)) != CLOBBER)))) | |
1928 | break; | |
1929 | } | |
1930 | ||
1931 | return insn; | |
1932 | } | |
1933 | ||
1934 | /* Find the last insn before INSN that really does something. This routine | |
1935 | does not look inside SEQUENCEs. Until reload has completed, this is the | |
1936 | same as prev_real_insn. */ | |
1937 | ||
1938 | rtx | |
1939 | prev_active_insn (insn) | |
1940 | rtx insn; | |
1941 | { | |
1942 | while (insn) | |
1943 | { | |
1944 | insn = PREV_INSN (insn); | |
1945 | if (insn == 0 | |
1946 | || GET_CODE (insn) == CALL_INSN || GET_CODE (insn) == JUMP_INSN | |
1947 | || (GET_CODE (insn) == INSN | |
1948 | && (! reload_completed | |
1949 | || (GET_CODE (PATTERN (insn)) != USE | |
1950 | && GET_CODE (PATTERN (insn)) != CLOBBER)))) | |
1951 | break; | |
1952 | } | |
1953 | ||
1954 | return insn; | |
1955 | } | |
1956 | ||
1957 | /* Return the next CODE_LABEL after the insn INSN, or 0 if there is none. */ | |
1958 | ||
1959 | rtx | |
1960 | next_label (insn) | |
1961 | rtx insn; | |
1962 | { | |
1963 | while (insn) | |
1964 | { | |
1965 | insn = NEXT_INSN (insn); | |
1966 | if (insn == 0 || GET_CODE (insn) == CODE_LABEL) | |
1967 | break; | |
1968 | } | |
1969 | ||
1970 | return insn; | |
1971 | } | |
1972 | ||
1973 | /* Return the last CODE_LABEL before the insn INSN, or 0 if there is none. */ | |
1974 | ||
1975 | rtx | |
1976 | prev_label (insn) | |
1977 | rtx insn; | |
1978 | { | |
1979 | while (insn) | |
1980 | { | |
1981 | insn = PREV_INSN (insn); | |
1982 | if (insn == 0 || GET_CODE (insn) == CODE_LABEL) | |
1983 | break; | |
1984 | } | |
1985 | ||
1986 | return insn; | |
1987 | } | |
1988 | \f | |
1989 | #ifdef HAVE_cc0 | |
c572e5ba JVA |
1990 | /* INSN uses CC0 and is being moved into a delay slot. Set up REG_CC_SETTER |
1991 | and REG_CC_USER notes so we can find it. */ | |
1992 | ||
1993 | void | |
1994 | link_cc0_insns (insn) | |
1995 | rtx insn; | |
1996 | { | |
1997 | rtx user = next_nonnote_insn (insn); | |
1998 | ||
1999 | if (GET_CODE (user) == INSN && GET_CODE (PATTERN (user)) == SEQUENCE) | |
2000 | user = XVECEXP (PATTERN (user), 0, 0); | |
2001 | ||
2002 | REG_NOTES (user) = gen_rtx (INSN_LIST, REG_CC_SETTER, insn, | |
2003 | REG_NOTES (user)); | |
2004 | REG_NOTES (insn) = gen_rtx (INSN_LIST, REG_CC_USER, user, REG_NOTES (insn)); | |
2005 | } | |
2006 | ||
23b2ce53 RS |
2007 | /* Return the next insn that uses CC0 after INSN, which is assumed to |
2008 | set it. This is the inverse of prev_cc0_setter (i.e., prev_cc0_setter | |
2009 | applied to the result of this function should yield INSN). | |
2010 | ||
2011 | Normally, this is simply the next insn. However, if a REG_CC_USER note | |
2012 | is present, it contains the insn that uses CC0. | |
2013 | ||
2014 | Return 0 if we can't find the insn. */ | |
2015 | ||
2016 | rtx | |
2017 | next_cc0_user (insn) | |
2018 | rtx insn; | |
2019 | { | |
906c4e36 | 2020 | rtx note = find_reg_note (insn, REG_CC_USER, NULL_RTX); |
23b2ce53 RS |
2021 | |
2022 | if (note) | |
2023 | return XEXP (note, 0); | |
2024 | ||
2025 | insn = next_nonnote_insn (insn); | |
2026 | if (insn && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SEQUENCE) | |
2027 | insn = XVECEXP (PATTERN (insn), 0, 0); | |
2028 | ||
2029 | if (insn && GET_RTX_CLASS (GET_CODE (insn)) == 'i' | |
2030 | && reg_mentioned_p (cc0_rtx, PATTERN (insn))) | |
2031 | return insn; | |
2032 | ||
2033 | return 0; | |
2034 | } | |
2035 | ||
2036 | /* Find the insn that set CC0 for INSN. Unless INSN has a REG_CC_SETTER | |
2037 | note, it is the previous insn. */ | |
2038 | ||
2039 | rtx | |
2040 | prev_cc0_setter (insn) | |
2041 | rtx insn; | |
2042 | { | |
906c4e36 | 2043 | rtx note = find_reg_note (insn, REG_CC_SETTER, NULL_RTX); |
23b2ce53 RS |
2044 | rtx link; |
2045 | ||
2046 | if (note) | |
2047 | return XEXP (note, 0); | |
2048 | ||
2049 | insn = prev_nonnote_insn (insn); | |
2050 | if (! sets_cc0_p (PATTERN (insn))) | |
2051 | abort (); | |
2052 | ||
2053 | return insn; | |
2054 | } | |
2055 | #endif | |
2056 | \f | |
2057 | /* Try splitting insns that can be split for better scheduling. | |
2058 | PAT is the pattern which might split. | |
2059 | TRIAL is the insn providing PAT. | |
11147ebe | 2060 | LAST is non-zero if we should return the last insn of the sequence produced. |
23b2ce53 RS |
2061 | |
2062 | If this routine succeeds in splitting, it returns the first or last | |
11147ebe | 2063 | replacement insn depending on the value of LAST. Otherwise, it |
23b2ce53 RS |
2064 | returns TRIAL. If the insn to be returned can be split, it will be. */ |
2065 | ||
2066 | rtx | |
11147ebe | 2067 | try_split (pat, trial, last) |
23b2ce53 | 2068 | rtx pat, trial; |
11147ebe | 2069 | int last; |
23b2ce53 RS |
2070 | { |
2071 | rtx before = PREV_INSN (trial); | |
2072 | rtx after = NEXT_INSN (trial); | |
2073 | rtx seq = split_insns (pat, trial); | |
2074 | int has_barrier = 0; | |
2075 | rtx tem; | |
2076 | ||
2077 | /* If we are splitting a JUMP_INSN, it might be followed by a BARRIER. | |
2078 | We may need to handle this specially. */ | |
2079 | if (after && GET_CODE (after) == BARRIER) | |
2080 | { | |
2081 | has_barrier = 1; | |
2082 | after = NEXT_INSN (after); | |
2083 | } | |
2084 | ||
2085 | if (seq) | |
2086 | { | |
2087 | /* SEQ can either be a SEQUENCE or the pattern of a single insn. | |
2088 | The latter case will normally arise only when being done so that | |
2089 | it, in turn, will be split (SFmode on the 29k is an example). */ | |
2090 | if (GET_CODE (seq) == SEQUENCE) | |
2091 | { | |
2092 | /* If we are splitting a JUMP_INSN, look for the JUMP_INSN in | |
2093 | SEQ and copy our JUMP_LABEL to it. If JUMP_LABEL is non-zero, | |
2094 | increment the usage count so we don't delete the label. */ | |
2095 | int i; | |
2096 | ||
2097 | if (GET_CODE (trial) == JUMP_INSN) | |
2098 | for (i = XVECLEN (seq, 0) - 1; i >= 0; i--) | |
2099 | if (GET_CODE (XVECEXP (seq, 0, i)) == JUMP_INSN) | |
2100 | { | |
2101 | JUMP_LABEL (XVECEXP (seq, 0, i)) = JUMP_LABEL (trial); | |
2102 | ||
2103 | if (JUMP_LABEL (trial)) | |
2104 | LABEL_NUSES (JUMP_LABEL (trial))++; | |
2105 | } | |
2106 | ||
2107 | tem = emit_insn_after (seq, before); | |
2108 | ||
2109 | delete_insn (trial); | |
2110 | if (has_barrier) | |
2111 | emit_barrier_after (tem); | |
11147ebe RK |
2112 | |
2113 | /* Recursively call try_split for each new insn created; by the | |
2114 | time control returns here that insn will be fully split, so | |
2115 | set LAST and continue from the insn after the one returned. | |
f4a3cd05 RK |
2116 | We can't use next_active_insn here since AFTER may be a note. |
2117 | Ignore deleted insns, which can be occur if not optimizing. */ | |
11147ebe RK |
2118 | for (tem = NEXT_INSN (before); tem != after; |
2119 | tem = NEXT_INSN (tem)) | |
f4a3cd05 RK |
2120 | if (! INSN_DELETED_P (tem)) |
2121 | tem = try_split (PATTERN (tem), tem, 1); | |
23b2ce53 RS |
2122 | } |
2123 | /* Avoid infinite loop if the result matches the original pattern. */ | |
2124 | else if (rtx_equal_p (seq, pat)) | |
2125 | return trial; | |
2126 | else | |
2127 | { | |
2128 | PATTERN (trial) = seq; | |
2129 | INSN_CODE (trial) = -1; | |
11147ebe | 2130 | try_split (seq, trial, last); |
23b2ce53 RS |
2131 | } |
2132 | ||
11147ebe RK |
2133 | /* Return either the first or the last insn, depending on which was |
2134 | requested. */ | |
2135 | return last ? prev_active_insn (after) : next_active_insn (before); | |
23b2ce53 RS |
2136 | } |
2137 | ||
2138 | return trial; | |
2139 | } | |
2140 | \f | |
2141 | /* Make and return an INSN rtx, initializing all its slots. | |
4b1f5e8c | 2142 | Store PATTERN in the pattern slots. */ |
23b2ce53 RS |
2143 | |
2144 | rtx | |
4b1f5e8c | 2145 | make_insn_raw (pattern) |
23b2ce53 | 2146 | rtx pattern; |
23b2ce53 RS |
2147 | { |
2148 | register rtx insn; | |
2149 | ||
43127294 RK |
2150 | /* If in RTL generation phase, see if FREE_INSN can be used. */ |
2151 | if (free_insn != 0 && rtx_equal_function_value_matters) | |
2152 | { | |
2153 | insn = free_insn; | |
2154 | free_insn = NEXT_INSN (free_insn); | |
2155 | PUT_CODE (insn, INSN); | |
2156 | } | |
2157 | else | |
2158 | insn = rtx_alloc (INSN); | |
23b2ce53 | 2159 | |
43127294 | 2160 | INSN_UID (insn) = cur_insn_uid++; |
23b2ce53 RS |
2161 | PATTERN (insn) = pattern; |
2162 | INSN_CODE (insn) = -1; | |
1632afca RS |
2163 | LOG_LINKS (insn) = NULL; |
2164 | REG_NOTES (insn) = NULL; | |
23b2ce53 RS |
2165 | |
2166 | return insn; | |
2167 | } | |
2168 | ||
2169 | /* Like `make_insn' but make a JUMP_INSN instead of an insn. */ | |
2170 | ||
2171 | static rtx | |
4b1f5e8c | 2172 | make_jump_insn_raw (pattern) |
23b2ce53 | 2173 | rtx pattern; |
23b2ce53 RS |
2174 | { |
2175 | register rtx insn; | |
2176 | ||
4b1f5e8c | 2177 | insn = rtx_alloc (JUMP_INSN); |
1632afca | 2178 | INSN_UID (insn) = cur_insn_uid++; |
23b2ce53 RS |
2179 | |
2180 | PATTERN (insn) = pattern; | |
2181 | INSN_CODE (insn) = -1; | |
1632afca RS |
2182 | LOG_LINKS (insn) = NULL; |
2183 | REG_NOTES (insn) = NULL; | |
2184 | JUMP_LABEL (insn) = NULL; | |
23b2ce53 RS |
2185 | |
2186 | return insn; | |
2187 | } | |
aff507f4 RK |
2188 | |
2189 | /* Like `make_insn' but make a CALL_INSN instead of an insn. */ | |
2190 | ||
2191 | static rtx | |
2192 | make_call_insn_raw (pattern) | |
2193 | rtx pattern; | |
2194 | { | |
2195 | register rtx insn; | |
2196 | ||
2197 | insn = rtx_alloc (CALL_INSN); | |
2198 | INSN_UID (insn) = cur_insn_uid++; | |
2199 | ||
2200 | PATTERN (insn) = pattern; | |
2201 | INSN_CODE (insn) = -1; | |
2202 | LOG_LINKS (insn) = NULL; | |
2203 | REG_NOTES (insn) = NULL; | |
2204 | CALL_INSN_FUNCTION_USAGE (insn) = NULL; | |
2205 | ||
2206 | return insn; | |
2207 | } | |
23b2ce53 RS |
2208 | \f |
2209 | /* Add INSN to the end of the doubly-linked list. | |
2210 | INSN may be an INSN, JUMP_INSN, CALL_INSN, CODE_LABEL, BARRIER or NOTE. */ | |
2211 | ||
2212 | void | |
2213 | add_insn (insn) | |
2214 | register rtx insn; | |
2215 | { | |
2216 | PREV_INSN (insn) = last_insn; | |
2217 | NEXT_INSN (insn) = 0; | |
2218 | ||
2219 | if (NULL != last_insn) | |
2220 | NEXT_INSN (last_insn) = insn; | |
2221 | ||
2222 | if (NULL == first_insn) | |
2223 | first_insn = insn; | |
2224 | ||
2225 | last_insn = insn; | |
2226 | } | |
2227 | ||
a0ae8e8d RK |
2228 | /* Add INSN into the doubly-linked list after insn AFTER. This and |
2229 | the next should be the only functions called to insert an insn once | |
ba213285 | 2230 | delay slots have been filled since only they know how to update a |
a0ae8e8d | 2231 | SEQUENCE. */ |
23b2ce53 RS |
2232 | |
2233 | void | |
2234 | add_insn_after (insn, after) | |
2235 | rtx insn, after; | |
2236 | { | |
2237 | rtx next = NEXT_INSN (after); | |
2238 | ||
6782074d | 2239 | if (optimize && INSN_DELETED_P (after)) |
ba213285 RK |
2240 | abort (); |
2241 | ||
23b2ce53 RS |
2242 | NEXT_INSN (insn) = next; |
2243 | PREV_INSN (insn) = after; | |
2244 | ||
2245 | if (next) | |
2246 | { | |
2247 | PREV_INSN (next) = insn; | |
2248 | if (GET_CODE (next) == INSN && GET_CODE (PATTERN (next)) == SEQUENCE) | |
2249 | PREV_INSN (XVECEXP (PATTERN (next), 0, 0)) = insn; | |
2250 | } | |
2251 | else if (last_insn == after) | |
2252 | last_insn = insn; | |
2253 | else | |
2254 | { | |
2255 | struct sequence_stack *stack = sequence_stack; | |
2256 | /* Scan all pending sequences too. */ | |
2257 | for (; stack; stack = stack->next) | |
2258 | if (after == stack->last) | |
fef0509b RK |
2259 | { |
2260 | stack->last = insn; | |
2261 | break; | |
2262 | } | |
a0ae8e8d RK |
2263 | |
2264 | if (stack == 0) | |
2265 | abort (); | |
23b2ce53 RS |
2266 | } |
2267 | ||
2268 | NEXT_INSN (after) = insn; | |
2269 | if (GET_CODE (after) == INSN && GET_CODE (PATTERN (after)) == SEQUENCE) | |
2270 | { | |
2271 | rtx sequence = PATTERN (after); | |
2272 | NEXT_INSN (XVECEXP (sequence, 0, XVECLEN (sequence, 0) - 1)) = insn; | |
2273 | } | |
2274 | } | |
2275 | ||
a0ae8e8d RK |
2276 | /* Add INSN into the doubly-linked list before insn BEFORE. This and |
2277 | the previous should be the only functions called to insert an insn once | |
ba213285 | 2278 | delay slots have been filled since only they know how to update a |
a0ae8e8d RK |
2279 | SEQUENCE. */ |
2280 | ||
2281 | void | |
2282 | add_insn_before (insn, before) | |
2283 | rtx insn, before; | |
2284 | { | |
2285 | rtx prev = PREV_INSN (before); | |
2286 | ||
6782074d | 2287 | if (optimize && INSN_DELETED_P (before)) |
ba213285 RK |
2288 | abort (); |
2289 | ||
a0ae8e8d RK |
2290 | PREV_INSN (insn) = prev; |
2291 | NEXT_INSN (insn) = before; | |
2292 | ||
2293 | if (prev) | |
2294 | { | |
2295 | NEXT_INSN (prev) = insn; | |
2296 | if (GET_CODE (prev) == INSN && GET_CODE (PATTERN (prev)) == SEQUENCE) | |
2297 | { | |
2298 | rtx sequence = PATTERN (prev); | |
2299 | NEXT_INSN (XVECEXP (sequence, 0, XVECLEN (sequence, 0) - 1)) = insn; | |
2300 | } | |
2301 | } | |
2302 | else if (first_insn == before) | |
2303 | first_insn = insn; | |
2304 | else | |
2305 | { | |
2306 | struct sequence_stack *stack = sequence_stack; | |
2307 | /* Scan all pending sequences too. */ | |
2308 | for (; stack; stack = stack->next) | |
2309 | if (before == stack->first) | |
fef0509b RK |
2310 | { |
2311 | stack->first = insn; | |
2312 | break; | |
2313 | } | |
a0ae8e8d RK |
2314 | |
2315 | if (stack == 0) | |
2316 | abort (); | |
2317 | } | |
2318 | ||
2319 | PREV_INSN (before) = insn; | |
2320 | if (GET_CODE (before) == INSN && GET_CODE (PATTERN (before)) == SEQUENCE) | |
2321 | PREV_INSN (XVECEXP (PATTERN (before), 0, 0)) = insn; | |
2322 | } | |
2323 | ||
23b2ce53 RS |
2324 | /* Delete all insns made since FROM. |
2325 | FROM becomes the new last instruction. */ | |
2326 | ||
2327 | void | |
2328 | delete_insns_since (from) | |
2329 | rtx from; | |
2330 | { | |
2331 | if (from == 0) | |
2332 | first_insn = 0; | |
2333 | else | |
2334 | NEXT_INSN (from) = 0; | |
2335 | last_insn = from; | |
2336 | } | |
2337 | ||
5dab5552 MS |
2338 | /* This function is deprecated, please use sequences instead. |
2339 | ||
2340 | Move a consecutive bunch of insns to a different place in the chain. | |
23b2ce53 RS |
2341 | The insns to be moved are those between FROM and TO. |
2342 | They are moved to a new position after the insn AFTER. | |
2343 | AFTER must not be FROM or TO or any insn in between. | |
2344 | ||
2345 | This function does not know about SEQUENCEs and hence should not be | |
2346 | called after delay-slot filling has been done. */ | |
2347 | ||
2348 | void | |
2349 | reorder_insns (from, to, after) | |
2350 | rtx from, to, after; | |
2351 | { | |
2352 | /* Splice this bunch out of where it is now. */ | |
2353 | if (PREV_INSN (from)) | |
2354 | NEXT_INSN (PREV_INSN (from)) = NEXT_INSN (to); | |
2355 | if (NEXT_INSN (to)) | |
2356 | PREV_INSN (NEXT_INSN (to)) = PREV_INSN (from); | |
2357 | if (last_insn == to) | |
2358 | last_insn = PREV_INSN (from); | |
2359 | if (first_insn == from) | |
2360 | first_insn = NEXT_INSN (to); | |
2361 | ||
2362 | /* Make the new neighbors point to it and it to them. */ | |
2363 | if (NEXT_INSN (after)) | |
2364 | PREV_INSN (NEXT_INSN (after)) = to; | |
2365 | ||
2366 | NEXT_INSN (to) = NEXT_INSN (after); | |
2367 | PREV_INSN (from) = after; | |
2368 | NEXT_INSN (after) = from; | |
2369 | if (after == last_insn) | |
2370 | last_insn = to; | |
2371 | } | |
2372 | ||
2373 | /* Return the line note insn preceding INSN. */ | |
2374 | ||
2375 | static rtx | |
2376 | find_line_note (insn) | |
2377 | rtx insn; | |
2378 | { | |
2379 | if (no_line_numbers) | |
2380 | return 0; | |
2381 | ||
2382 | for (; insn; insn = PREV_INSN (insn)) | |
2383 | if (GET_CODE (insn) == NOTE | |
2384 | && NOTE_LINE_NUMBER (insn) >= 0) | |
2385 | break; | |
2386 | ||
2387 | return insn; | |
2388 | } | |
2389 | ||
2390 | /* Like reorder_insns, but inserts line notes to preserve the line numbers | |
2391 | of the moved insns when debugging. This may insert a note between AFTER | |
2392 | and FROM, and another one after TO. */ | |
2393 | ||
2394 | void | |
2395 | reorder_insns_with_line_notes (from, to, after) | |
2396 | rtx from, to, after; | |
2397 | { | |
2398 | rtx from_line = find_line_note (from); | |
2399 | rtx after_line = find_line_note (after); | |
2400 | ||
2401 | reorder_insns (from, to, after); | |
2402 | ||
2403 | if (from_line == after_line) | |
2404 | return; | |
2405 | ||
2406 | if (from_line) | |
2407 | emit_line_note_after (NOTE_SOURCE_FILE (from_line), | |
2408 | NOTE_LINE_NUMBER (from_line), | |
2409 | after); | |
2410 | if (after_line) | |
2411 | emit_line_note_after (NOTE_SOURCE_FILE (after_line), | |
2412 | NOTE_LINE_NUMBER (after_line), | |
2413 | to); | |
2414 | } | |
2415 | \f | |
2416 | /* Emit an insn of given code and pattern | |
2417 | at a specified place within the doubly-linked list. */ | |
2418 | ||
2419 | /* Make an instruction with body PATTERN | |
2420 | and output it before the instruction BEFORE. */ | |
2421 | ||
2422 | rtx | |
2423 | emit_insn_before (pattern, before) | |
2424 | register rtx pattern, before; | |
2425 | { | |
2426 | register rtx insn = before; | |
2427 | ||
2428 | if (GET_CODE (pattern) == SEQUENCE) | |
2429 | { | |
2430 | register int i; | |
2431 | ||
2432 | for (i = 0; i < XVECLEN (pattern, 0); i++) | |
2433 | { | |
2434 | insn = XVECEXP (pattern, 0, i); | |
a0ae8e8d | 2435 | add_insn_before (insn, before); |
23b2ce53 RS |
2436 | } |
2437 | if (XVECLEN (pattern, 0) < SEQUENCE_RESULT_SIZE) | |
2438 | sequence_result[XVECLEN (pattern, 0)] = pattern; | |
2439 | } | |
2440 | else | |
2441 | { | |
4b1f5e8c | 2442 | insn = make_insn_raw (pattern); |
a0ae8e8d | 2443 | add_insn_before (insn, before); |
23b2ce53 RS |
2444 | } |
2445 | ||
2446 | return insn; | |
2447 | } | |
2448 | ||
2449 | /* Make an instruction with body PATTERN and code JUMP_INSN | |
2450 | and output it before the instruction BEFORE. */ | |
2451 | ||
2452 | rtx | |
2453 | emit_jump_insn_before (pattern, before) | |
2454 | register rtx pattern, before; | |
2455 | { | |
2456 | register rtx insn; | |
2457 | ||
2458 | if (GET_CODE (pattern) == SEQUENCE) | |
2459 | insn = emit_insn_before (pattern, before); | |
2460 | else | |
2461 | { | |
85cf32bc | 2462 | insn = make_jump_insn_raw (pattern); |
a0ae8e8d | 2463 | add_insn_before (insn, before); |
23b2ce53 RS |
2464 | } |
2465 | ||
2466 | return insn; | |
2467 | } | |
2468 | ||
2469 | /* Make an instruction with body PATTERN and code CALL_INSN | |
2470 | and output it before the instruction BEFORE. */ | |
2471 | ||
2472 | rtx | |
2473 | emit_call_insn_before (pattern, before) | |
2474 | register rtx pattern, before; | |
2475 | { | |
aff507f4 RK |
2476 | register rtx insn; |
2477 | ||
2478 | if (GET_CODE (pattern) == SEQUENCE) | |
2479 | insn = emit_insn_before (pattern, before); | |
2480 | else | |
2481 | { | |
2482 | insn = make_call_insn_raw (pattern); | |
a0ae8e8d | 2483 | add_insn_before (insn, before); |
aff507f4 RK |
2484 | PUT_CODE (insn, CALL_INSN); |
2485 | } | |
2486 | ||
23b2ce53 RS |
2487 | return insn; |
2488 | } | |
2489 | ||
2490 | /* Make an insn of code BARRIER | |
2491 | and output it before the insn AFTER. */ | |
2492 | ||
2493 | rtx | |
2494 | emit_barrier_before (before) | |
2495 | register rtx before; | |
2496 | { | |
2497 | register rtx insn = rtx_alloc (BARRIER); | |
2498 | ||
2499 | INSN_UID (insn) = cur_insn_uid++; | |
2500 | ||
a0ae8e8d | 2501 | add_insn_before (insn, before); |
23b2ce53 RS |
2502 | return insn; |
2503 | } | |
2504 | ||
2505 | /* Emit a note of subtype SUBTYPE before the insn BEFORE. */ | |
2506 | ||
2507 | rtx | |
2508 | emit_note_before (subtype, before) | |
2509 | int subtype; | |
2510 | rtx before; | |
2511 | { | |
2512 | register rtx note = rtx_alloc (NOTE); | |
2513 | INSN_UID (note) = cur_insn_uid++; | |
2514 | NOTE_SOURCE_FILE (note) = 0; | |
2515 | NOTE_LINE_NUMBER (note) = subtype; | |
2516 | ||
a0ae8e8d | 2517 | add_insn_before (note, before); |
23b2ce53 RS |
2518 | return note; |
2519 | } | |
2520 | \f | |
2521 | /* Make an insn of code INSN with body PATTERN | |
2522 | and output it after the insn AFTER. */ | |
2523 | ||
2524 | rtx | |
2525 | emit_insn_after (pattern, after) | |
2526 | register rtx pattern, after; | |
2527 | { | |
2528 | register rtx insn = after; | |
2529 | ||
2530 | if (GET_CODE (pattern) == SEQUENCE) | |
2531 | { | |
2532 | register int i; | |
2533 | ||
2534 | for (i = 0; i < XVECLEN (pattern, 0); i++) | |
2535 | { | |
2536 | insn = XVECEXP (pattern, 0, i); | |
2537 | add_insn_after (insn, after); | |
2538 | after = insn; | |
2539 | } | |
2540 | if (XVECLEN (pattern, 0) < SEQUENCE_RESULT_SIZE) | |
2541 | sequence_result[XVECLEN (pattern, 0)] = pattern; | |
2542 | } | |
2543 | else | |
2544 | { | |
4b1f5e8c | 2545 | insn = make_insn_raw (pattern); |
23b2ce53 RS |
2546 | add_insn_after (insn, after); |
2547 | } | |
2548 | ||
2549 | return insn; | |
2550 | } | |
2551 | ||
255680cf RK |
2552 | /* Similar to emit_insn_after, except that line notes are to be inserted so |
2553 | as to act as if this insn were at FROM. */ | |
2554 | ||
2555 | void | |
2556 | emit_insn_after_with_line_notes (pattern, after, from) | |
2557 | rtx pattern, after, from; | |
2558 | { | |
2559 | rtx from_line = find_line_note (from); | |
2560 | rtx after_line = find_line_note (after); | |
2561 | rtx insn = emit_insn_after (pattern, after); | |
2562 | ||
2563 | if (from_line) | |
2564 | emit_line_note_after (NOTE_SOURCE_FILE (from_line), | |
2565 | NOTE_LINE_NUMBER (from_line), | |
2566 | after); | |
2567 | ||
2568 | if (after_line) | |
2569 | emit_line_note_after (NOTE_SOURCE_FILE (after_line), | |
2570 | NOTE_LINE_NUMBER (after_line), | |
2571 | insn); | |
2572 | } | |
2573 | ||
23b2ce53 RS |
2574 | /* Make an insn of code JUMP_INSN with body PATTERN |
2575 | and output it after the insn AFTER. */ | |
2576 | ||
2577 | rtx | |
2578 | emit_jump_insn_after (pattern, after) | |
2579 | register rtx pattern, after; | |
2580 | { | |
2581 | register rtx insn; | |
2582 | ||
2583 | if (GET_CODE (pattern) == SEQUENCE) | |
2584 | insn = emit_insn_after (pattern, after); | |
2585 | else | |
2586 | { | |
85cf32bc | 2587 | insn = make_jump_insn_raw (pattern); |
23b2ce53 RS |
2588 | add_insn_after (insn, after); |
2589 | } | |
2590 | ||
2591 | return insn; | |
2592 | } | |
2593 | ||
2594 | /* Make an insn of code BARRIER | |
2595 | and output it after the insn AFTER. */ | |
2596 | ||
2597 | rtx | |
2598 | emit_barrier_after (after) | |
2599 | register rtx after; | |
2600 | { | |
2601 | register rtx insn = rtx_alloc (BARRIER); | |
2602 | ||
2603 | INSN_UID (insn) = cur_insn_uid++; | |
2604 | ||
2605 | add_insn_after (insn, after); | |
2606 | return insn; | |
2607 | } | |
2608 | ||
2609 | /* Emit the label LABEL after the insn AFTER. */ | |
2610 | ||
2611 | rtx | |
2612 | emit_label_after (label, after) | |
2613 | rtx label, after; | |
2614 | { | |
2615 | /* This can be called twice for the same label | |
2616 | as a result of the confusion that follows a syntax error! | |
2617 | So make it harmless. */ | |
2618 | if (INSN_UID (label) == 0) | |
2619 | { | |
2620 | INSN_UID (label) = cur_insn_uid++; | |
2621 | add_insn_after (label, after); | |
2622 | } | |
2623 | ||
2624 | return label; | |
2625 | } | |
2626 | ||
2627 | /* Emit a note of subtype SUBTYPE after the insn AFTER. */ | |
2628 | ||
2629 | rtx | |
2630 | emit_note_after (subtype, after) | |
2631 | int subtype; | |
2632 | rtx after; | |
2633 | { | |
2634 | register rtx note = rtx_alloc (NOTE); | |
2635 | INSN_UID (note) = cur_insn_uid++; | |
2636 | NOTE_SOURCE_FILE (note) = 0; | |
2637 | NOTE_LINE_NUMBER (note) = subtype; | |
2638 | add_insn_after (note, after); | |
2639 | return note; | |
2640 | } | |
2641 | ||
2642 | /* Emit a line note for FILE and LINE after the insn AFTER. */ | |
2643 | ||
2644 | rtx | |
2645 | emit_line_note_after (file, line, after) | |
2646 | char *file; | |
2647 | int line; | |
2648 | rtx after; | |
2649 | { | |
2650 | register rtx note; | |
2651 | ||
2652 | if (no_line_numbers && line > 0) | |
2653 | { | |
2654 | cur_insn_uid++; | |
2655 | return 0; | |
2656 | } | |
2657 | ||
2658 | note = rtx_alloc (NOTE); | |
2659 | INSN_UID (note) = cur_insn_uid++; | |
2660 | NOTE_SOURCE_FILE (note) = file; | |
2661 | NOTE_LINE_NUMBER (note) = line; | |
2662 | add_insn_after (note, after); | |
2663 | return note; | |
2664 | } | |
2665 | \f | |
2666 | /* Make an insn of code INSN with pattern PATTERN | |
2667 | and add it to the end of the doubly-linked list. | |
2668 | If PATTERN is a SEQUENCE, take the elements of it | |
2669 | and emit an insn for each element. | |
2670 | ||
2671 | Returns the last insn emitted. */ | |
2672 | ||
2673 | rtx | |
2674 | emit_insn (pattern) | |
2675 | rtx pattern; | |
2676 | { | |
2677 | rtx insn = last_insn; | |
2678 | ||
2679 | if (GET_CODE (pattern) == SEQUENCE) | |
2680 | { | |
2681 | register int i; | |
2682 | ||
2683 | for (i = 0; i < XVECLEN (pattern, 0); i++) | |
2684 | { | |
2685 | insn = XVECEXP (pattern, 0, i); | |
2686 | add_insn (insn); | |
2687 | } | |
2688 | if (XVECLEN (pattern, 0) < SEQUENCE_RESULT_SIZE) | |
2689 | sequence_result[XVECLEN (pattern, 0)] = pattern; | |
2690 | } | |
2691 | else | |
2692 | { | |
4b1f5e8c | 2693 | insn = make_insn_raw (pattern); |
23b2ce53 RS |
2694 | add_insn (insn); |
2695 | } | |
2696 | ||
2697 | return insn; | |
2698 | } | |
2699 | ||
2700 | /* Emit the insns in a chain starting with INSN. | |
2701 | Return the last insn emitted. */ | |
2702 | ||
2703 | rtx | |
2704 | emit_insns (insn) | |
2705 | rtx insn; | |
2706 | { | |
2707 | rtx last = 0; | |
2708 | ||
2709 | while (insn) | |
2710 | { | |
2711 | rtx next = NEXT_INSN (insn); | |
2712 | add_insn (insn); | |
2713 | last = insn; | |
2714 | insn = next; | |
2715 | } | |
2716 | ||
2717 | return last; | |
2718 | } | |
2719 | ||
2720 | /* Emit the insns in a chain starting with INSN and place them in front of | |
2721 | the insn BEFORE. Return the last insn emitted. */ | |
2722 | ||
2723 | rtx | |
2724 | emit_insns_before (insn, before) | |
2725 | rtx insn; | |
2726 | rtx before; | |
2727 | { | |
2728 | rtx last = 0; | |
2729 | ||
2730 | while (insn) | |
2731 | { | |
2732 | rtx next = NEXT_INSN (insn); | |
a0ae8e8d | 2733 | add_insn_before (insn, before); |
23b2ce53 RS |
2734 | last = insn; |
2735 | insn = next; | |
2736 | } | |
2737 | ||
2738 | return last; | |
2739 | } | |
2740 | ||
e0a5c5eb RS |
2741 | /* Emit the insns in a chain starting with FIRST and place them in back of |
2742 | the insn AFTER. Return the last insn emitted. */ | |
2743 | ||
2744 | rtx | |
2745 | emit_insns_after (first, after) | |
2746 | register rtx first; | |
2747 | register rtx after; | |
2748 | { | |
2749 | register rtx last; | |
2750 | register rtx after_after; | |
2751 | ||
2752 | if (!after) | |
2753 | abort (); | |
2754 | ||
2755 | if (!first) | |
2756 | return first; | |
2757 | ||
2758 | for (last = first; NEXT_INSN (last); last = NEXT_INSN (last)) | |
2759 | continue; | |
2760 | ||
2761 | after_after = NEXT_INSN (after); | |
2762 | ||
2763 | NEXT_INSN (after) = first; | |
2764 | PREV_INSN (first) = after; | |
2765 | NEXT_INSN (last) = after_after; | |
2766 | if (after_after) | |
2767 | PREV_INSN (after_after) = last; | |
2768 | ||
c4d990db RS |
2769 | if (after == last_insn) |
2770 | last_insn = last; | |
e0a5c5eb RS |
2771 | return last; |
2772 | } | |
2773 | ||
23b2ce53 RS |
2774 | /* Make an insn of code JUMP_INSN with pattern PATTERN |
2775 | and add it to the end of the doubly-linked list. */ | |
2776 | ||
2777 | rtx | |
2778 | emit_jump_insn (pattern) | |
2779 | rtx pattern; | |
2780 | { | |
2781 | if (GET_CODE (pattern) == SEQUENCE) | |
2782 | return emit_insn (pattern); | |
2783 | else | |
2784 | { | |
85cf32bc | 2785 | register rtx insn = make_jump_insn_raw (pattern); |
23b2ce53 RS |
2786 | add_insn (insn); |
2787 | return insn; | |
2788 | } | |
2789 | } | |
2790 | ||
2791 | /* Make an insn of code CALL_INSN with pattern PATTERN | |
2792 | and add it to the end of the doubly-linked list. */ | |
2793 | ||
2794 | rtx | |
2795 | emit_call_insn (pattern) | |
2796 | rtx pattern; | |
2797 | { | |
2798 | if (GET_CODE (pattern) == SEQUENCE) | |
2799 | return emit_insn (pattern); | |
2800 | else | |
2801 | { | |
aff507f4 | 2802 | register rtx insn = make_call_insn_raw (pattern); |
23b2ce53 RS |
2803 | add_insn (insn); |
2804 | PUT_CODE (insn, CALL_INSN); | |
2805 | return insn; | |
2806 | } | |
2807 | } | |
2808 | ||
2809 | /* Add the label LABEL to the end of the doubly-linked list. */ | |
2810 | ||
2811 | rtx | |
2812 | emit_label (label) | |
2813 | rtx label; | |
2814 | { | |
2815 | /* This can be called twice for the same label | |
2816 | as a result of the confusion that follows a syntax error! | |
2817 | So make it harmless. */ | |
2818 | if (INSN_UID (label) == 0) | |
2819 | { | |
2820 | INSN_UID (label) = cur_insn_uid++; | |
2821 | add_insn (label); | |
2822 | } | |
2823 | return label; | |
2824 | } | |
2825 | ||
2826 | /* Make an insn of code BARRIER | |
2827 | and add it to the end of the doubly-linked list. */ | |
2828 | ||
2829 | rtx | |
2830 | emit_barrier () | |
2831 | { | |
2832 | register rtx barrier = rtx_alloc (BARRIER); | |
2833 | INSN_UID (barrier) = cur_insn_uid++; | |
2834 | add_insn (barrier); | |
2835 | return barrier; | |
2836 | } | |
2837 | ||
2838 | /* Make an insn of code NOTE | |
2839 | with data-fields specified by FILE and LINE | |
2840 | and add it to the end of the doubly-linked list, | |
2841 | but only if line-numbers are desired for debugging info. */ | |
2842 | ||
2843 | rtx | |
2844 | emit_line_note (file, line) | |
2845 | char *file; | |
2846 | int line; | |
2847 | { | |
ca695ac9 JB |
2848 | if (output_bytecode) |
2849 | { | |
2850 | /* FIXME: for now we do nothing, but eventually we will have to deal with | |
2851 | debugging information. */ | |
2852 | return 0; | |
2853 | } | |
2854 | ||
23b2ce53 RS |
2855 | emit_filename = file; |
2856 | emit_lineno = line; | |
2857 | ||
2858 | #if 0 | |
2859 | if (no_line_numbers) | |
2860 | return 0; | |
2861 | #endif | |
2862 | ||
2863 | return emit_note (file, line); | |
2864 | } | |
2865 | ||
2866 | /* Make an insn of code NOTE | |
2867 | with data-fields specified by FILE and LINE | |
2868 | and add it to the end of the doubly-linked list. | |
2869 | If it is a line-number NOTE, omit it if it matches the previous one. */ | |
2870 | ||
2871 | rtx | |
2872 | emit_note (file, line) | |
2873 | char *file; | |
2874 | int line; | |
2875 | { | |
2876 | register rtx note; | |
2877 | ||
2878 | if (line > 0) | |
2879 | { | |
2880 | if (file && last_filename && !strcmp (file, last_filename) | |
2881 | && line == last_linenum) | |
2882 | return 0; | |
2883 | last_filename = file; | |
2884 | last_linenum = line; | |
2885 | } | |
2886 | ||
2887 | if (no_line_numbers && line > 0) | |
2888 | { | |
2889 | cur_insn_uid++; | |
2890 | return 0; | |
2891 | } | |
2892 | ||
2893 | note = rtx_alloc (NOTE); | |
2894 | INSN_UID (note) = cur_insn_uid++; | |
2895 | NOTE_SOURCE_FILE (note) = file; | |
2896 | NOTE_LINE_NUMBER (note) = line; | |
2897 | add_insn (note); | |
2898 | return note; | |
2899 | } | |
2900 | ||
2901 | /* Emit a NOTE, and don't omit it even if LINE it the previous note. */ | |
2902 | ||
2903 | rtx | |
2904 | emit_line_note_force (file, line) | |
2905 | char *file; | |
2906 | int line; | |
2907 | { | |
2908 | last_linenum = -1; | |
2909 | return emit_line_note (file, line); | |
2910 | } | |
2911 | ||
2912 | /* Cause next statement to emit a line note even if the line number | |
2913 | has not changed. This is used at the beginning of a function. */ | |
2914 | ||
2915 | void | |
2916 | force_next_line_note () | |
2917 | { | |
2918 | last_linenum = -1; | |
2919 | } | |
2920 | \f | |
2921 | /* Return an indication of which type of insn should have X as a body. | |
2922 | The value is CODE_LABEL, INSN, CALL_INSN or JUMP_INSN. */ | |
2923 | ||
2924 | enum rtx_code | |
2925 | classify_insn (x) | |
2926 | rtx x; | |
2927 | { | |
2928 | if (GET_CODE (x) == CODE_LABEL) | |
2929 | return CODE_LABEL; | |
2930 | if (GET_CODE (x) == CALL) | |
2931 | return CALL_INSN; | |
2932 | if (GET_CODE (x) == RETURN) | |
2933 | return JUMP_INSN; | |
2934 | if (GET_CODE (x) == SET) | |
2935 | { | |
2936 | if (SET_DEST (x) == pc_rtx) | |
2937 | return JUMP_INSN; | |
2938 | else if (GET_CODE (SET_SRC (x)) == CALL) | |
2939 | return CALL_INSN; | |
2940 | else | |
2941 | return INSN; | |
2942 | } | |
2943 | if (GET_CODE (x) == PARALLEL) | |
2944 | { | |
2945 | register int j; | |
2946 | for (j = XVECLEN (x, 0) - 1; j >= 0; j--) | |
2947 | if (GET_CODE (XVECEXP (x, 0, j)) == CALL) | |
2948 | return CALL_INSN; | |
2949 | else if (GET_CODE (XVECEXP (x, 0, j)) == SET | |
2950 | && SET_DEST (XVECEXP (x, 0, j)) == pc_rtx) | |
2951 | return JUMP_INSN; | |
2952 | else if (GET_CODE (XVECEXP (x, 0, j)) == SET | |
2953 | && GET_CODE (SET_SRC (XVECEXP (x, 0, j))) == CALL) | |
2954 | return CALL_INSN; | |
2955 | } | |
2956 | return INSN; | |
2957 | } | |
2958 | ||
2959 | /* Emit the rtl pattern X as an appropriate kind of insn. | |
2960 | If X is a label, it is simply added into the insn chain. */ | |
2961 | ||
2962 | rtx | |
2963 | emit (x) | |
2964 | rtx x; | |
2965 | { | |
2966 | enum rtx_code code = classify_insn (x); | |
2967 | ||
2968 | if (code == CODE_LABEL) | |
2969 | return emit_label (x); | |
2970 | else if (code == INSN) | |
2971 | return emit_insn (x); | |
2972 | else if (code == JUMP_INSN) | |
2973 | { | |
2974 | register rtx insn = emit_jump_insn (x); | |
2975 | if (simplejump_p (insn) || GET_CODE (x) == RETURN) | |
2976 | return emit_barrier (); | |
2977 | return insn; | |
2978 | } | |
2979 | else if (code == CALL_INSN) | |
2980 | return emit_call_insn (x); | |
2981 | else | |
2982 | abort (); | |
2983 | } | |
2984 | \f | |
2985 | /* Begin emitting insns to a sequence which can be packaged in an RTL_EXPR. */ | |
2986 | ||
2987 | void | |
2988 | start_sequence () | |
2989 | { | |
2990 | struct sequence_stack *tem; | |
2991 | ||
2992 | if (sequence_element_free_list) | |
2993 | { | |
2994 | /* Reuse a previously-saved struct sequence_stack. */ | |
2995 | tem = sequence_element_free_list; | |
2996 | sequence_element_free_list = tem->next; | |
2997 | } | |
2998 | else | |
2999 | tem = (struct sequence_stack *) permalloc (sizeof (struct sequence_stack)); | |
3000 | ||
3001 | tem->next = sequence_stack; | |
3002 | tem->first = first_insn; | |
3003 | tem->last = last_insn; | |
3ae24368 | 3004 | tem->sequence_rtl_expr = sequence_rtl_expr; |
23b2ce53 RS |
3005 | |
3006 | sequence_stack = tem; | |
3007 | ||
3008 | first_insn = 0; | |
3009 | last_insn = 0; | |
3010 | } | |
3011 | ||
a25c7971 RK |
3012 | /* Similarly, but indicate that this sequence will be placed in |
3013 | T, an RTL_EXPR. */ | |
3014 | ||
3015 | void | |
3016 | start_sequence_for_rtl_expr (t) | |
3017 | tree t; | |
3018 | { | |
3019 | start_sequence (); | |
3020 | ||
3021 | sequence_rtl_expr = t; | |
3022 | } | |
3023 | ||
23b2ce53 RS |
3024 | /* Set up the insn chain starting with FIRST |
3025 | as the current sequence, saving the previously current one. */ | |
3026 | ||
3027 | void | |
3028 | push_to_sequence (first) | |
3029 | rtx first; | |
3030 | { | |
3031 | rtx last; | |
3032 | ||
3033 | start_sequence (); | |
3034 | ||
3035 | for (last = first; last && NEXT_INSN (last); last = NEXT_INSN (last)); | |
3036 | ||
3037 | first_insn = first; | |
3038 | last_insn = last; | |
3039 | } | |
3040 | ||
f15ae3a1 TW |
3041 | /* Set up the outer-level insn chain |
3042 | as the current sequence, saving the previously current one. */ | |
3043 | ||
3044 | void | |
3045 | push_topmost_sequence () | |
3046 | { | |
3047 | struct sequence_stack *stack, *top; | |
3048 | ||
3049 | start_sequence (); | |
3050 | ||
3051 | for (stack = sequence_stack; stack; stack = stack->next) | |
3052 | top = stack; | |
3053 | ||
3054 | first_insn = top->first; | |
3055 | last_insn = top->last; | |
629a4238 | 3056 | sequence_rtl_expr = top->sequence_rtl_expr; |
f15ae3a1 TW |
3057 | } |
3058 | ||
3059 | /* After emitting to the outer-level insn chain, update the outer-level | |
3060 | insn chain, and restore the previous saved state. */ | |
3061 | ||
3062 | void | |
3063 | pop_topmost_sequence () | |
3064 | { | |
3065 | struct sequence_stack *stack, *top; | |
3066 | ||
3067 | for (stack = sequence_stack; stack; stack = stack->next) | |
3068 | top = stack; | |
3069 | ||
3070 | top->first = first_insn; | |
3071 | top->last = last_insn; | |
3ae24368 | 3072 | /* ??? Why don't we save sequence_rtl_expr here? */ |
f15ae3a1 TW |
3073 | |
3074 | end_sequence (); | |
3075 | } | |
3076 | ||
23b2ce53 RS |
3077 | /* After emitting to a sequence, restore previous saved state. |
3078 | ||
3079 | To get the contents of the sequence just made, | |
3080 | you must call `gen_sequence' *before* calling here. */ | |
3081 | ||
3082 | void | |
3083 | end_sequence () | |
3084 | { | |
3085 | struct sequence_stack *tem = sequence_stack; | |
3086 | ||
3087 | first_insn = tem->first; | |
3088 | last_insn = tem->last; | |
629a4238 | 3089 | sequence_rtl_expr = tem->sequence_rtl_expr; |
23b2ce53 RS |
3090 | sequence_stack = tem->next; |
3091 | ||
3092 | tem->next = sequence_element_free_list; | |
3093 | sequence_element_free_list = tem; | |
3094 | } | |
3095 | ||
3096 | /* Return 1 if currently emitting into a sequence. */ | |
3097 | ||
3098 | int | |
3099 | in_sequence_p () | |
3100 | { | |
3101 | return sequence_stack != 0; | |
3102 | } | |
3103 | ||
3104 | /* Generate a SEQUENCE rtx containing the insns already emitted | |
3105 | to the current sequence. | |
3106 | ||
3107 | This is how the gen_... function from a DEFINE_EXPAND | |
3108 | constructs the SEQUENCE that it returns. */ | |
3109 | ||
3110 | rtx | |
3111 | gen_sequence () | |
3112 | { | |
3113 | rtx result; | |
3114 | rtx tem; | |
23b2ce53 RS |
3115 | int i; |
3116 | int len; | |
3117 | ||
3118 | /* Count the insns in the chain. */ | |
3119 | len = 0; | |
3120 | for (tem = first_insn; tem; tem = NEXT_INSN (tem)) | |
3121 | len++; | |
3122 | ||
3123 | /* If only one insn, return its pattern rather than a SEQUENCE. | |
3124 | (Now that we cache SEQUENCE expressions, it isn't worth special-casing | |
3125 | the case of an empty list.) */ | |
3126 | if (len == 1 | |
3127 | && (GET_CODE (first_insn) == INSN | |
3128 | || GET_CODE (first_insn) == JUMP_INSN | |
15d23f2b DE |
3129 | /* Don't discard the call usage field. */ |
3130 | || (GET_CODE (first_insn) == CALL_INSN | |
3131 | && CALL_INSN_FUNCTION_USAGE (first_insn) == NULL_RTX))) | |
43127294 RK |
3132 | { |
3133 | NEXT_INSN (first_insn) = free_insn; | |
3134 | free_insn = first_insn; | |
3135 | return PATTERN (first_insn); | |
3136 | } | |
23b2ce53 RS |
3137 | |
3138 | /* Put them in a vector. See if we already have a SEQUENCE of the | |
3139 | appropriate length around. */ | |
3140 | if (len < SEQUENCE_RESULT_SIZE && (result = sequence_result[len]) != 0) | |
3141 | sequence_result[len] = 0; | |
3142 | else | |
3143 | { | |
9faa82d8 RK |
3144 | /* Ensure that this rtl goes in saveable_obstack, since we may |
3145 | cache it. */ | |
d508ebba JW |
3146 | push_obstacks_nochange (); |
3147 | rtl_in_saveable_obstack (); | |
23b2ce53 | 3148 | result = gen_rtx (SEQUENCE, VOIDmode, rtvec_alloc (len)); |
d508ebba | 3149 | pop_obstacks (); |
23b2ce53 RS |
3150 | } |
3151 | ||
3152 | for (i = 0, tem = first_insn; tem; tem = NEXT_INSN (tem), i++) | |
3153 | XVECEXP (result, 0, i) = tem; | |
3154 | ||
3155 | return result; | |
3156 | } | |
3157 | \f | |
23b2ce53 RS |
3158 | /* Initialize data structures and variables in this file |
3159 | before generating rtl for each function. */ | |
3160 | ||
3161 | void | |
3162 | init_emit () | |
3163 | { | |
3164 | int i; | |
3165 | ||
3166 | first_insn = NULL; | |
3167 | last_insn = NULL; | |
a25c7971 | 3168 | sequence_rtl_expr = NULL; |
23b2ce53 RS |
3169 | cur_insn_uid = 1; |
3170 | reg_rtx_no = LAST_VIRTUAL_REGISTER + 1; | |
3171 | last_linenum = 0; | |
3172 | last_filename = 0; | |
3173 | first_label_num = label_num; | |
3174 | last_label_num = 0; | |
24d11a9a | 3175 | sequence_stack = NULL; |
23b2ce53 RS |
3176 | |
3177 | /* Clear the start_sequence/gen_sequence cache. */ | |
3178 | sequence_element_free_list = 0; | |
3179 | for (i = 0; i < SEQUENCE_RESULT_SIZE; i++) | |
3180 | sequence_result[i] = 0; | |
43127294 | 3181 | free_insn = 0; |
23b2ce53 RS |
3182 | |
3183 | /* Init the tables that describe all the pseudo regs. */ | |
3184 | ||
3185 | regno_pointer_flag_length = LAST_VIRTUAL_REGISTER + 101; | |
3186 | ||
3187 | regno_pointer_flag | |
86fe05e0 | 3188 | = (char *) savealloc (regno_pointer_flag_length); |
23b2ce53 RS |
3189 | bzero (regno_pointer_flag, regno_pointer_flag_length); |
3190 | ||
86fe05e0 RK |
3191 | regno_pointer_align |
3192 | = (char *) savealloc (regno_pointer_flag_length); | |
3193 | bzero (regno_pointer_align, regno_pointer_flag_length); | |
3194 | ||
23b2ce53 | 3195 | regno_reg_rtx |
86fe05e0 | 3196 | = (rtx *) savealloc (regno_pointer_flag_length * sizeof (rtx)); |
4c9a05bc | 3197 | bzero ((char *) regno_reg_rtx, regno_pointer_flag_length * sizeof (rtx)); |
23b2ce53 RS |
3198 | |
3199 | /* Put copies of all the virtual register rtx into regno_reg_rtx. */ | |
3200 | regno_reg_rtx[VIRTUAL_INCOMING_ARGS_REGNUM] = virtual_incoming_args_rtx; | |
3201 | regno_reg_rtx[VIRTUAL_STACK_VARS_REGNUM] = virtual_stack_vars_rtx; | |
3202 | regno_reg_rtx[VIRTUAL_STACK_DYNAMIC_REGNUM] = virtual_stack_dynamic_rtx; | |
3203 | regno_reg_rtx[VIRTUAL_OUTGOING_ARGS_REGNUM] = virtual_outgoing_args_rtx; | |
740ab4a2 RK |
3204 | |
3205 | /* Indicate that the virtual registers and stack locations are | |
3206 | all pointers. */ | |
3207 | REGNO_POINTER_FLAG (STACK_POINTER_REGNUM) = 1; | |
3208 | REGNO_POINTER_FLAG (FRAME_POINTER_REGNUM) = 1; | |
15c9248c | 3209 | REGNO_POINTER_FLAG (HARD_FRAME_POINTER_REGNUM) = 1; |
740ab4a2 RK |
3210 | REGNO_POINTER_FLAG (ARG_POINTER_REGNUM) = 1; |
3211 | ||
3212 | REGNO_POINTER_FLAG (VIRTUAL_INCOMING_ARGS_REGNUM) = 1; | |
3213 | REGNO_POINTER_FLAG (VIRTUAL_STACK_VARS_REGNUM) = 1; | |
3214 | REGNO_POINTER_FLAG (VIRTUAL_STACK_DYNAMIC_REGNUM) = 1; | |
3215 | REGNO_POINTER_FLAG (VIRTUAL_OUTGOING_ARGS_REGNUM) = 1; | |
5e82e7bd | 3216 | |
86fe05e0 RK |
3217 | #ifdef STACK_BOUNDARY |
3218 | REGNO_POINTER_ALIGN (STACK_POINTER_REGNUM) = STACK_BOUNDARY / BITS_PER_UNIT; | |
3219 | REGNO_POINTER_ALIGN (FRAME_POINTER_REGNUM) = STACK_BOUNDARY / BITS_PER_UNIT; | |
3220 | REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) | |
3221 | = STACK_BOUNDARY / BITS_PER_UNIT; | |
3222 | REGNO_POINTER_ALIGN (ARG_POINTER_REGNUM) = STACK_BOUNDARY / BITS_PER_UNIT; | |
3223 | ||
3224 | REGNO_POINTER_ALIGN (VIRTUAL_INCOMING_ARGS_REGNUM) | |
3225 | = STACK_BOUNDARY / BITS_PER_UNIT; | |
3226 | REGNO_POINTER_ALIGN (VIRTUAL_STACK_VARS_REGNUM) | |
3227 | = STACK_BOUNDARY / BITS_PER_UNIT; | |
3228 | REGNO_POINTER_ALIGN (VIRTUAL_STACK_DYNAMIC_REGNUM) | |
3229 | = STACK_BOUNDARY / BITS_PER_UNIT; | |
3230 | REGNO_POINTER_ALIGN (VIRTUAL_OUTGOING_ARGS_REGNUM) | |
3231 | = STACK_BOUNDARY / BITS_PER_UNIT; | |
3232 | #endif | |
3233 | ||
5e82e7bd JVA |
3234 | #ifdef INIT_EXPANDERS |
3235 | INIT_EXPANDERS; | |
3236 | #endif | |
23b2ce53 RS |
3237 | } |
3238 | ||
3239 | /* Create some permanent unique rtl objects shared between all functions. | |
3240 | LINE_NUMBERS is nonzero if line numbers are to be generated. */ | |
3241 | ||
3242 | void | |
3243 | init_emit_once (line_numbers) | |
3244 | int line_numbers; | |
3245 | { | |
3246 | int i; | |
3247 | enum machine_mode mode; | |
3248 | ||
3249 | no_line_numbers = ! line_numbers; | |
3250 | ||
3251 | sequence_stack = NULL; | |
3252 | ||
1d445e9e ILT |
3253 | /* Compute the word and byte modes. */ |
3254 | ||
3255 | byte_mode = VOIDmode; | |
3256 | word_mode = VOIDmode; | |
3257 | ||
3258 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT); mode != VOIDmode; | |
3259 | mode = GET_MODE_WIDER_MODE (mode)) | |
3260 | { | |
3261 | if (GET_MODE_BITSIZE (mode) == BITS_PER_UNIT | |
3262 | && byte_mode == VOIDmode) | |
3263 | byte_mode = mode; | |
3264 | ||
3265 | if (GET_MODE_BITSIZE (mode) == BITS_PER_WORD | |
3266 | && word_mode == VOIDmode) | |
3267 | word_mode = mode; | |
3268 | } | |
3269 | ||
15c9248c RK |
3270 | ptr_mode = mode_for_size (POINTER_SIZE, GET_MODE_CLASS (Pmode), 0); |
3271 | ||
23b2ce53 RS |
3272 | /* Create the unique rtx's for certain rtx codes and operand values. */ |
3273 | ||
3274 | pc_rtx = gen_rtx (PC, VOIDmode); | |
3275 | cc0_rtx = gen_rtx (CC0, VOIDmode); | |
3276 | ||
3277 | /* Don't use gen_rtx here since gen_rtx in this case | |
3278 | tries to use these variables. */ | |
3279 | for (i = - MAX_SAVED_CONST_INT; i <= MAX_SAVED_CONST_INT; i++) | |
3280 | { | |
3281 | const_int_rtx[i + MAX_SAVED_CONST_INT] = rtx_alloc (CONST_INT); | |
3282 | PUT_MODE (const_int_rtx[i + MAX_SAVED_CONST_INT], VOIDmode); | |
3283 | INTVAL (const_int_rtx[i + MAX_SAVED_CONST_INT]) = i; | |
3284 | } | |
3285 | ||
3286 | /* These four calls obtain some of the rtx expressions made above. */ | |
906c4e36 RK |
3287 | const0_rtx = GEN_INT (0); |
3288 | const1_rtx = GEN_INT (1); | |
3289 | const2_rtx = GEN_INT (2); | |
3290 | constm1_rtx = GEN_INT (-1); | |
23b2ce53 RS |
3291 | |
3292 | /* This will usually be one of the above constants, but may be a new rtx. */ | |
906c4e36 | 3293 | const_true_rtx = GEN_INT (STORE_FLAG_VALUE); |
23b2ce53 | 3294 | |
1632afca RS |
3295 | dconst0 = REAL_VALUE_ATOF ("0", DFmode); |
3296 | dconst1 = REAL_VALUE_ATOF ("1", DFmode); | |
3297 | dconst2 = REAL_VALUE_ATOF ("2", DFmode); | |
3298 | dconstm1 = REAL_VALUE_ATOF ("-1", DFmode); | |
23b2ce53 RS |
3299 | |
3300 | for (i = 0; i <= 2; i++) | |
3301 | { | |
3302 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_FLOAT); mode != VOIDmode; | |
3303 | mode = GET_MODE_WIDER_MODE (mode)) | |
3304 | { | |
3305 | rtx tem = rtx_alloc (CONST_DOUBLE); | |
3306 | union real_extract u; | |
3307 | ||
4c9a05bc | 3308 | bzero ((char *) &u, sizeof u); /* Zero any holes in a structure. */ |
23b2ce53 RS |
3309 | u.d = i == 0 ? dconst0 : i == 1 ? dconst1 : dconst2; |
3310 | ||
4c9a05bc | 3311 | bcopy ((char *) &u, (char *) &CONST_DOUBLE_LOW (tem), sizeof u); |
23b2ce53 RS |
3312 | CONST_DOUBLE_MEM (tem) = cc0_rtx; |
3313 | PUT_MODE (tem, mode); | |
3314 | ||
3315 | const_tiny_rtx[i][(int) mode] = tem; | |
3316 | } | |
3317 | ||
906c4e36 | 3318 | const_tiny_rtx[i][(int) VOIDmode] = GEN_INT (i); |
23b2ce53 RS |
3319 | |
3320 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT); mode != VOIDmode; | |
3321 | mode = GET_MODE_WIDER_MODE (mode)) | |
906c4e36 | 3322 | const_tiny_rtx[i][(int) mode] = GEN_INT (i); |
33d3e559 RS |
3323 | |
3324 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_PARTIAL_INT); | |
3325 | mode != VOIDmode; | |
3326 | mode = GET_MODE_WIDER_MODE (mode)) | |
3327 | const_tiny_rtx[i][(int) mode] = GEN_INT (i); | |
23b2ce53 RS |
3328 | } |
3329 | ||
dfa09e23 TW |
3330 | for (mode = GET_CLASS_NARROWEST_MODE (MODE_CC); mode != VOIDmode; |
3331 | mode = GET_MODE_WIDER_MODE (mode)) | |
3332 | const_tiny_rtx[0][(int) mode] = const0_rtx; | |
3333 | ||
23b2ce53 RS |
3334 | stack_pointer_rtx = gen_rtx (REG, Pmode, STACK_POINTER_REGNUM); |
3335 | frame_pointer_rtx = gen_rtx (REG, Pmode, FRAME_POINTER_REGNUM); | |
3336 | ||
ac6f08b0 DE |
3337 | if (HARD_FRAME_POINTER_REGNUM == FRAME_POINTER_REGNUM) |
3338 | hard_frame_pointer_rtx = frame_pointer_rtx; | |
3339 | else | |
3340 | hard_frame_pointer_rtx = gen_rtx (REG, Pmode, HARD_FRAME_POINTER_REGNUM); | |
3341 | ||
23b2ce53 RS |
3342 | if (FRAME_POINTER_REGNUM == ARG_POINTER_REGNUM) |
3343 | arg_pointer_rtx = frame_pointer_rtx; | |
ac6f08b0 DE |
3344 | else if (HARD_FRAME_POINTER_REGNUM == ARG_POINTER_REGNUM) |
3345 | arg_pointer_rtx = hard_frame_pointer_rtx; | |
23b2ce53 RS |
3346 | else if (STACK_POINTER_REGNUM == ARG_POINTER_REGNUM) |
3347 | arg_pointer_rtx = stack_pointer_rtx; | |
3348 | else | |
3349 | arg_pointer_rtx = gen_rtx (REG, Pmode, ARG_POINTER_REGNUM); | |
3350 | ||
a4417a86 JW |
3351 | #ifdef RETURN_ADDRESS_POINTER_REGNUM |
3352 | return_address_pointer_rtx = gen_rtx (REG, Pmode, | |
3353 | RETURN_ADDRESS_POINTER_REGNUM); | |
3354 | #endif | |
3355 | ||
23b2ce53 RS |
3356 | /* Create the virtual registers. Do so here since the following objects |
3357 | might reference them. */ | |
3358 | ||
3359 | virtual_incoming_args_rtx = gen_rtx (REG, Pmode, | |
3360 | VIRTUAL_INCOMING_ARGS_REGNUM); | |
3361 | virtual_stack_vars_rtx = gen_rtx (REG, Pmode, | |
3362 | VIRTUAL_STACK_VARS_REGNUM); | |
3363 | virtual_stack_dynamic_rtx = gen_rtx (REG, Pmode, | |
3364 | VIRTUAL_STACK_DYNAMIC_REGNUM); | |
3365 | virtual_outgoing_args_rtx = gen_rtx (REG, Pmode, | |
3366 | VIRTUAL_OUTGOING_ARGS_REGNUM); | |
3367 | ||
3368 | #ifdef STRUCT_VALUE | |
3369 | struct_value_rtx = STRUCT_VALUE; | |
3370 | #else | |
3371 | struct_value_rtx = gen_rtx (REG, Pmode, STRUCT_VALUE_REGNUM); | |
3372 | #endif | |
3373 | ||
3374 | #ifdef STRUCT_VALUE_INCOMING | |
3375 | struct_value_incoming_rtx = STRUCT_VALUE_INCOMING; | |
3376 | #else | |
3377 | #ifdef STRUCT_VALUE_INCOMING_REGNUM | |
3378 | struct_value_incoming_rtx | |
3379 | = gen_rtx (REG, Pmode, STRUCT_VALUE_INCOMING_REGNUM); | |
3380 | #else | |
3381 | struct_value_incoming_rtx = struct_value_rtx; | |
3382 | #endif | |
3383 | #endif | |
3384 | ||
3385 | #ifdef STATIC_CHAIN_REGNUM | |
3386 | static_chain_rtx = gen_rtx (REG, Pmode, STATIC_CHAIN_REGNUM); | |
3387 | ||
3388 | #ifdef STATIC_CHAIN_INCOMING_REGNUM | |
3389 | if (STATIC_CHAIN_INCOMING_REGNUM != STATIC_CHAIN_REGNUM) | |
3390 | static_chain_incoming_rtx = gen_rtx (REG, Pmode, STATIC_CHAIN_INCOMING_REGNUM); | |
3391 | else | |
3392 | #endif | |
3393 | static_chain_incoming_rtx = static_chain_rtx; | |
3394 | #endif | |
3395 | ||
3396 | #ifdef STATIC_CHAIN | |
3397 | static_chain_rtx = STATIC_CHAIN; | |
3398 | ||
3399 | #ifdef STATIC_CHAIN_INCOMING | |
3400 | static_chain_incoming_rtx = STATIC_CHAIN_INCOMING; | |
3401 | #else | |
3402 | static_chain_incoming_rtx = static_chain_rtx; | |
3403 | #endif | |
3404 | #endif | |
3405 | ||
3406 | #ifdef PIC_OFFSET_TABLE_REGNUM | |
3407 | pic_offset_table_rtx = gen_rtx (REG, Pmode, PIC_OFFSET_TABLE_REGNUM); | |
3408 | #endif | |
3409 | } |