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69a0611f | 1 | @c Copyright (C) 1988, 1989, 1992, 1993, 1994, 1996, 1998, 1999, 2000, 2001, 2002 |
5c84b18e | 2 | @c Free Software Foundation, Inc. |
03dda8e3 RK |
3 | @c This is part of the GCC manual. |
4 | @c For copying conditions, see the file gcc.texi. | |
5 | ||
6 | @ifset INTERNALS | |
7 | @node Machine Desc | |
8 | @chapter Machine Descriptions | |
9 | @cindex machine descriptions | |
10 | ||
11 | A machine description has two parts: a file of instruction patterns | |
12 | (@file{.md} file) and a C header file of macro definitions. | |
13 | ||
14 | The @file{.md} file for a target machine contains a pattern for each | |
15 | instruction that the target machine supports (or at least each instruction | |
16 | that is worth telling the compiler about). It may also contain comments. | |
17 | A semicolon causes the rest of the line to be a comment, unless the semicolon | |
18 | is inside a quoted string. | |
19 | ||
20 | See the next chapter for information on the C header file. | |
21 | ||
22 | @menu | |
55e4756f | 23 | * Overview:: How the machine description is used. |
03dda8e3 RK |
24 | * Patterns:: How to write instruction patterns. |
25 | * Example:: An explained example of a @code{define_insn} pattern. | |
26 | * RTL Template:: The RTL template defines what insns match a pattern. | |
27 | * Output Template:: The output template says how to make assembler code | |
28 | from such an insn. | |
29 | * Output Statement:: For more generality, write C code to output | |
30 | the assembler code. | |
31 | * Constraints:: When not all operands are general operands. | |
32 | * Standard Names:: Names mark patterns to use for code generation. | |
33 | * Pattern Ordering:: When the order of patterns makes a difference. | |
34 | * Dependent Patterns:: Having one pattern may make you need another. | |
35 | * Jump Patterns:: Special considerations for patterns for jump insns. | |
6e4fcc95 | 36 | * Looping Patterns:: How to define patterns for special looping insns. |
03dda8e3 | 37 | * Insn Canonicalizations::Canonicalization of Instructions |
03dda8e3 | 38 | * Expander Definitions::Generating a sequence of several RTL insns |
f3a3d0d3 RH |
39 | for a standard operation. |
40 | * Insn Splitting:: Splitting Instructions into Multiple Instructions. | |
04d8aa70 | 41 | * Including Patterns:: Including Patterns in Machine Descriptions. |
f3a3d0d3 | 42 | * Peephole Definitions::Defining machine-specific peephole optimizations. |
03dda8e3 | 43 | * Insn Attributes:: Specifying the value of attributes for generated insns. |
3262c1f5 RH |
44 | * Conditional Execution::Generating @code{define_insn} patterns for |
45 | predication. | |
c25c12b8 R |
46 | * Constant Definitions::Defining symbolic constants that can be used in the |
47 | md file. | |
03dda8e3 RK |
48 | @end menu |
49 | ||
55e4756f DD |
50 | @node Overview |
51 | @section Overview of How the Machine Description is Used | |
52 | ||
53 | There are three main conversions that happen in the compiler: | |
54 | ||
55 | @enumerate | |
56 | ||
57 | @item | |
58 | The front end reads the source code and builds a parse tree. | |
59 | ||
60 | @item | |
61 | The parse tree is used to generate an RTL insn list based on named | |
62 | instruction patterns. | |
63 | ||
64 | @item | |
65 | The insn list is matched against the RTL templates to produce assembler | |
66 | code. | |
67 | ||
68 | @end enumerate | |
69 | ||
70 | For the generate pass, only the names of the insns matter, from either a | |
71 | named @code{define_insn} or a @code{define_expand}. The compiler will | |
72 | choose the pattern with the right name and apply the operands according | |
73 | to the documentation later in this chapter, without regard for the RTL | |
74 | template or operand constraints. Note that the names the compiler looks | |
d7d9c429 | 75 | for are hard-coded in the compiler---it will ignore unnamed patterns and |
55e4756f DD |
76 | patterns with names it doesn't know about, but if you don't provide a |
77 | named pattern it needs, it will abort. | |
78 | ||
79 | If a @code{define_insn} is used, the template given is inserted into the | |
80 | insn list. If a @code{define_expand} is used, one of three things | |
81 | happens, based on the condition logic. The condition logic may manually | |
82 | create new insns for the insn list, say via @code{emit_insn()}, and | |
aee96fe9 | 83 | invoke @code{DONE}. For certain named patterns, it may invoke @code{FAIL} to tell the |
55e4756f DD |
84 | compiler to use an alternate way of performing that task. If it invokes |
85 | neither @code{DONE} nor @code{FAIL}, the template given in the pattern | |
86 | is inserted, as if the @code{define_expand} were a @code{define_insn}. | |
87 | ||
88 | Once the insn list is generated, various optimization passes convert, | |
89 | replace, and rearrange the insns in the insn list. This is where the | |
90 | @code{define_split} and @code{define_peephole} patterns get used, for | |
91 | example. | |
92 | ||
93 | Finally, the insn list's RTL is matched up with the RTL templates in the | |
94 | @code{define_insn} patterns, and those patterns are used to emit the | |
95 | final assembly code. For this purpose, each named @code{define_insn} | |
96 | acts like it's unnamed, since the names are ignored. | |
97 | ||
03dda8e3 RK |
98 | @node Patterns |
99 | @section Everything about Instruction Patterns | |
100 | @cindex patterns | |
101 | @cindex instruction patterns | |
102 | ||
103 | @findex define_insn | |
104 | Each instruction pattern contains an incomplete RTL expression, with pieces | |
105 | to be filled in later, operand constraints that restrict how the pieces can | |
106 | be filled in, and an output pattern or C code to generate the assembler | |
107 | output, all wrapped up in a @code{define_insn} expression. | |
108 | ||
109 | A @code{define_insn} is an RTL expression containing four or five operands: | |
110 | ||
111 | @enumerate | |
112 | @item | |
113 | An optional name. The presence of a name indicate that this instruction | |
114 | pattern can perform a certain standard job for the RTL-generation | |
115 | pass of the compiler. This pass knows certain names and will use | |
116 | the instruction patterns with those names, if the names are defined | |
117 | in the machine description. | |
118 | ||
119 | The absence of a name is indicated by writing an empty string | |
120 | where the name should go. Nameless instruction patterns are never | |
121 | used for generating RTL code, but they may permit several simpler insns | |
122 | to be combined later on. | |
123 | ||
124 | Names that are not thus known and used in RTL-generation have no | |
125 | effect; they are equivalent to no name at all. | |
126 | ||
661cb0b7 RK |
127 | For the purpose of debugging the compiler, you may also specify a |
128 | name beginning with the @samp{*} character. Such a name is used only | |
129 | for identifying the instruction in RTL dumps; it is entirely equivalent | |
130 | to having a nameless pattern for all other purposes. | |
131 | ||
03dda8e3 RK |
132 | @item |
133 | The @dfn{RTL template} (@pxref{RTL Template}) is a vector of incomplete | |
134 | RTL expressions which show what the instruction should look like. It is | |
135 | incomplete because it may contain @code{match_operand}, | |
136 | @code{match_operator}, and @code{match_dup} expressions that stand for | |
137 | operands of the instruction. | |
138 | ||
139 | If the vector has only one element, that element is the template for the | |
140 | instruction pattern. If the vector has multiple elements, then the | |
141 | instruction pattern is a @code{parallel} expression containing the | |
142 | elements described. | |
143 | ||
144 | @item | |
145 | @cindex pattern conditions | |
146 | @cindex conditions, in patterns | |
147 | A condition. This is a string which contains a C expression that is | |
148 | the final test to decide whether an insn body matches this pattern. | |
149 | ||
150 | @cindex named patterns and conditions | |
151 | For a named pattern, the condition (if present) may not depend on | |
152 | the data in the insn being matched, but only the target-machine-type | |
153 | flags. The compiler needs to test these conditions during | |
154 | initialization in order to learn exactly which named instructions are | |
155 | available in a particular run. | |
156 | ||
157 | @findex operands | |
158 | For nameless patterns, the condition is applied only when matching an | |
159 | individual insn, and only after the insn has matched the pattern's | |
160 | recognition template. The insn's operands may be found in the vector | |
fde6d81f HPN |
161 | @code{operands}. For an insn where the condition has once matched, it |
162 | can't be used to control register allocation, for example by excluding | |
163 | certain hard registers or hard register combinations. | |
03dda8e3 RK |
164 | |
165 | @item | |
166 | The @dfn{output template}: a string that says how to output matching | |
167 | insns as assembler code. @samp{%} in this string specifies where | |
168 | to substitute the value of an operand. @xref{Output Template}. | |
169 | ||
170 | When simple substitution isn't general enough, you can specify a piece | |
171 | of C code to compute the output. @xref{Output Statement}. | |
172 | ||
173 | @item | |
174 | Optionally, a vector containing the values of attributes for insns matching | |
175 | this pattern. @xref{Insn Attributes}. | |
176 | @end enumerate | |
177 | ||
178 | @node Example | |
179 | @section Example of @code{define_insn} | |
180 | @cindex @code{define_insn} example | |
181 | ||
182 | Here is an actual example of an instruction pattern, for the 68000/68020. | |
183 | ||
184 | @example | |
185 | (define_insn "tstsi" | |
186 | [(set (cc0) | |
187 | (match_operand:SI 0 "general_operand" "rm"))] | |
188 | "" | |
189 | "* | |
f282ffb3 | 190 | @{ |
0f40f9f7 | 191 | if (TARGET_68020 || ! ADDRESS_REG_P (operands[0])) |
03dda8e3 | 192 | return \"tstl %0\"; |
f282ffb3 | 193 | return \"cmpl #0,%0\"; |
0f40f9f7 ZW |
194 | @}") |
195 | @end example | |
196 | ||
197 | @noindent | |
198 | This can also be written using braced strings: | |
199 | ||
200 | @example | |
201 | (define_insn "tstsi" | |
202 | [(set (cc0) | |
203 | (match_operand:SI 0 "general_operand" "rm"))] | |
204 | "" | |
f282ffb3 | 205 | @{ |
0f40f9f7 ZW |
206 | if (TARGET_68020 || ! ADDRESS_REG_P (operands[0])) |
207 | return "tstl %0"; | |
f282ffb3 | 208 | return "cmpl #0,%0"; |
0f40f9f7 | 209 | @}) |
03dda8e3 RK |
210 | @end example |
211 | ||
212 | This is an instruction that sets the condition codes based on the value of | |
213 | a general operand. It has no condition, so any insn whose RTL description | |
214 | has the form shown may be handled according to this pattern. The name | |
215 | @samp{tstsi} means ``test a @code{SImode} value'' and tells the RTL generation | |
216 | pass that, when it is necessary to test such a value, an insn to do so | |
217 | can be constructed using this pattern. | |
218 | ||
219 | The output control string is a piece of C code which chooses which | |
220 | output template to return based on the kind of operand and the specific | |
221 | type of CPU for which code is being generated. | |
222 | ||
223 | @samp{"rm"} is an operand constraint. Its meaning is explained below. | |
224 | ||
225 | @node RTL Template | |
226 | @section RTL Template | |
227 | @cindex RTL insn template | |
228 | @cindex generating insns | |
229 | @cindex insns, generating | |
230 | @cindex recognizing insns | |
231 | @cindex insns, recognizing | |
232 | ||
233 | The RTL template is used to define which insns match the particular pattern | |
234 | and how to find their operands. For named patterns, the RTL template also | |
235 | says how to construct an insn from specified operands. | |
236 | ||
237 | Construction involves substituting specified operands into a copy of the | |
238 | template. Matching involves determining the values that serve as the | |
239 | operands in the insn being matched. Both of these activities are | |
240 | controlled by special expression types that direct matching and | |
241 | substitution of the operands. | |
242 | ||
243 | @table @code | |
244 | @findex match_operand | |
245 | @item (match_operand:@var{m} @var{n} @var{predicate} @var{constraint}) | |
246 | This expression is a placeholder for operand number @var{n} of | |
247 | the insn. When constructing an insn, operand number @var{n} | |
248 | will be substituted at this point. When matching an insn, whatever | |
249 | appears at this position in the insn will be taken as operand | |
250 | number @var{n}; but it must satisfy @var{predicate} or this instruction | |
251 | pattern will not match at all. | |
252 | ||
253 | Operand numbers must be chosen consecutively counting from zero in | |
254 | each instruction pattern. There may be only one @code{match_operand} | |
255 | expression in the pattern for each operand number. Usually operands | |
256 | are numbered in the order of appearance in @code{match_operand} | |
72938a4c MM |
257 | expressions. In the case of a @code{define_expand}, any operand numbers |
258 | used only in @code{match_dup} expressions have higher values than all | |
259 | other operand numbers. | |
03dda8e3 RK |
260 | |
261 | @var{predicate} is a string that is the name of a C function that accepts two | |
262 | arguments, an expression and a machine mode. During matching, the | |
263 | function will be called with the putative operand as the expression and | |
264 | @var{m} as the mode argument (if @var{m} is not specified, | |
265 | @code{VOIDmode} will be used, which normally causes @var{predicate} to accept | |
266 | any mode). If it returns zero, this instruction pattern fails to match. | |
267 | @var{predicate} may be an empty string; then it means no test is to be done | |
268 | on the operand, so anything which occurs in this position is valid. | |
269 | ||
270 | Most of the time, @var{predicate} will reject modes other than @var{m}---but | |
271 | not always. For example, the predicate @code{address_operand} uses | |
272 | @var{m} as the mode of memory ref that the address should be valid for. | |
273 | Many predicates accept @code{const_int} nodes even though their mode is | |
274 | @code{VOIDmode}. | |
275 | ||
276 | @var{constraint} controls reloading and the choice of the best register | |
277 | class to use for a value, as explained later (@pxref{Constraints}). | |
278 | ||
279 | People are often unclear on the difference between the constraint and the | |
280 | predicate. The predicate helps decide whether a given insn matches the | |
281 | pattern. The constraint plays no role in this decision; instead, it | |
282 | controls various decisions in the case of an insn which does match. | |
283 | ||
284 | @findex general_operand | |
285 | On CISC machines, the most common @var{predicate} is | |
286 | @code{"general_operand"}. This function checks that the putative | |
287 | operand is either a constant, a register or a memory reference, and that | |
288 | it is valid for mode @var{m}. | |
289 | ||
290 | @findex register_operand | |
291 | For an operand that must be a register, @var{predicate} should be | |
292 | @code{"register_operand"}. Using @code{"general_operand"} would be | |
293 | valid, since the reload pass would copy any non-register operands | |
f0523f02 | 294 | through registers, but this would make GCC do extra work, it would |
03dda8e3 RK |
295 | prevent invariant operands (such as constant) from being removed from |
296 | loops, and it would prevent the register allocator from doing the best | |
297 | possible job. On RISC machines, it is usually most efficient to allow | |
298 | @var{predicate} to accept only objects that the constraints allow. | |
299 | ||
300 | @findex immediate_operand | |
301 | For an operand that must be a constant, you must be sure to either use | |
302 | @code{"immediate_operand"} for @var{predicate}, or make the instruction | |
303 | pattern's extra condition require a constant, or both. You cannot | |
304 | expect the constraints to do this work! If the constraints allow only | |
305 | constants, but the predicate allows something else, the compiler will | |
306 | crash when that case arises. | |
307 | ||
308 | @findex match_scratch | |
309 | @item (match_scratch:@var{m} @var{n} @var{constraint}) | |
310 | This expression is also a placeholder for operand number @var{n} | |
311 | and indicates that operand must be a @code{scratch} or @code{reg} | |
312 | expression. | |
313 | ||
314 | When matching patterns, this is equivalent to | |
315 | ||
316 | @smallexample | |
317 | (match_operand:@var{m} @var{n} "scratch_operand" @var{pred}) | |
318 | @end smallexample | |
319 | ||
320 | but, when generating RTL, it produces a (@code{scratch}:@var{m}) | |
321 | expression. | |
322 | ||
323 | If the last few expressions in a @code{parallel} are @code{clobber} | |
324 | expressions whose operands are either a hard register or | |
325 | @code{match_scratch}, the combiner can add or delete them when | |
326 | necessary. @xref{Side Effects}. | |
327 | ||
328 | @findex match_dup | |
329 | @item (match_dup @var{n}) | |
330 | This expression is also a placeholder for operand number @var{n}. | |
331 | It is used when the operand needs to appear more than once in the | |
332 | insn. | |
333 | ||
334 | In construction, @code{match_dup} acts just like @code{match_operand}: | |
335 | the operand is substituted into the insn being constructed. But in | |
336 | matching, @code{match_dup} behaves differently. It assumes that operand | |
337 | number @var{n} has already been determined by a @code{match_operand} | |
338 | appearing earlier in the recognition template, and it matches only an | |
339 | identical-looking expression. | |
340 | ||
55e4756f DD |
341 | Note that @code{match_dup} should not be used to tell the compiler that |
342 | a particular register is being used for two operands (example: | |
343 | @code{add} that adds one register to another; the second register is | |
344 | both an input operand and the output operand). Use a matching | |
345 | constraint (@pxref{Simple Constraints}) for those. @code{match_dup} is for the cases where one | |
346 | operand is used in two places in the template, such as an instruction | |
347 | that computes both a quotient and a remainder, where the opcode takes | |
348 | two input operands but the RTL template has to refer to each of those | |
349 | twice; once for the quotient pattern and once for the remainder pattern. | |
350 | ||
03dda8e3 RK |
351 | @findex match_operator |
352 | @item (match_operator:@var{m} @var{n} @var{predicate} [@var{operands}@dots{}]) | |
353 | This pattern is a kind of placeholder for a variable RTL expression | |
354 | code. | |
355 | ||
356 | When constructing an insn, it stands for an RTL expression whose | |
357 | expression code is taken from that of operand @var{n}, and whose | |
358 | operands are constructed from the patterns @var{operands}. | |
359 | ||
360 | When matching an expression, it matches an expression if the function | |
361 | @var{predicate} returns nonzero on that expression @emph{and} the | |
362 | patterns @var{operands} match the operands of the expression. | |
363 | ||
364 | Suppose that the function @code{commutative_operator} is defined as | |
365 | follows, to match any expression whose operator is one of the | |
366 | commutative arithmetic operators of RTL and whose mode is @var{mode}: | |
367 | ||
368 | @smallexample | |
369 | int | |
370 | commutative_operator (x, mode) | |
371 | rtx x; | |
372 | enum machine_mode mode; | |
373 | @{ | |
374 | enum rtx_code code = GET_CODE (x); | |
375 | if (GET_MODE (x) != mode) | |
376 | return 0; | |
377 | return (GET_RTX_CLASS (code) == 'c' | |
378 | || code == EQ || code == NE); | |
379 | @} | |
380 | @end smallexample | |
381 | ||
382 | Then the following pattern will match any RTL expression consisting | |
383 | of a commutative operator applied to two general operands: | |
384 | ||
385 | @smallexample | |
386 | (match_operator:SI 3 "commutative_operator" | |
387 | [(match_operand:SI 1 "general_operand" "g") | |
388 | (match_operand:SI 2 "general_operand" "g")]) | |
389 | @end smallexample | |
390 | ||
391 | Here the vector @code{[@var{operands}@dots{}]} contains two patterns | |
392 | because the expressions to be matched all contain two operands. | |
393 | ||
394 | When this pattern does match, the two operands of the commutative | |
395 | operator are recorded as operands 1 and 2 of the insn. (This is done | |
396 | by the two instances of @code{match_operand}.) Operand 3 of the insn | |
397 | will be the entire commutative expression: use @code{GET_CODE | |
398 | (operands[3])} to see which commutative operator was used. | |
399 | ||
400 | The machine mode @var{m} of @code{match_operator} works like that of | |
401 | @code{match_operand}: it is passed as the second argument to the | |
402 | predicate function, and that function is solely responsible for | |
403 | deciding whether the expression to be matched ``has'' that mode. | |
404 | ||
405 | When constructing an insn, argument 3 of the gen-function will specify | |
e979f9e8 | 406 | the operation (i.e.@: the expression code) for the expression to be |
03dda8e3 RK |
407 | made. It should be an RTL expression, whose expression code is copied |
408 | into a new expression whose operands are arguments 1 and 2 of the | |
409 | gen-function. The subexpressions of argument 3 are not used; | |
410 | only its expression code matters. | |
411 | ||
412 | When @code{match_operator} is used in a pattern for matching an insn, | |
413 | it usually best if the operand number of the @code{match_operator} | |
414 | is higher than that of the actual operands of the insn. This improves | |
415 | register allocation because the register allocator often looks at | |
416 | operands 1 and 2 of insns to see if it can do register tying. | |
417 | ||
418 | There is no way to specify constraints in @code{match_operator}. The | |
419 | operand of the insn which corresponds to the @code{match_operator} | |
420 | never has any constraints because it is never reloaded as a whole. | |
421 | However, if parts of its @var{operands} are matched by | |
422 | @code{match_operand} patterns, those parts may have constraints of | |
423 | their own. | |
424 | ||
425 | @findex match_op_dup | |
426 | @item (match_op_dup:@var{m} @var{n}[@var{operands}@dots{}]) | |
427 | Like @code{match_dup}, except that it applies to operators instead of | |
428 | operands. When constructing an insn, operand number @var{n} will be | |
429 | substituted at this point. But in matching, @code{match_op_dup} behaves | |
430 | differently. It assumes that operand number @var{n} has already been | |
431 | determined by a @code{match_operator} appearing earlier in the | |
432 | recognition template, and it matches only an identical-looking | |
433 | expression. | |
434 | ||
435 | @findex match_parallel | |
436 | @item (match_parallel @var{n} @var{predicate} [@var{subpat}@dots{}]) | |
437 | This pattern is a placeholder for an insn that consists of a | |
438 | @code{parallel} expression with a variable number of elements. This | |
439 | expression should only appear at the top level of an insn pattern. | |
440 | ||
441 | When constructing an insn, operand number @var{n} will be substituted at | |
442 | this point. When matching an insn, it matches if the body of the insn | |
443 | is a @code{parallel} expression with at least as many elements as the | |
444 | vector of @var{subpat} expressions in the @code{match_parallel}, if each | |
445 | @var{subpat} matches the corresponding element of the @code{parallel}, | |
446 | @emph{and} the function @var{predicate} returns nonzero on the | |
447 | @code{parallel} that is the body of the insn. It is the responsibility | |
448 | of the predicate to validate elements of the @code{parallel} beyond | |
bd819a4a | 449 | those listed in the @code{match_parallel}. |
03dda8e3 RK |
450 | |
451 | A typical use of @code{match_parallel} is to match load and store | |
452 | multiple expressions, which can contain a variable number of elements | |
453 | in a @code{parallel}. For example, | |
03dda8e3 RK |
454 | |
455 | @smallexample | |
456 | (define_insn "" | |
457 | [(match_parallel 0 "load_multiple_operation" | |
458 | [(set (match_operand:SI 1 "gpc_reg_operand" "=r") | |
459 | (match_operand:SI 2 "memory_operand" "m")) | |
460 | (use (reg:SI 179)) | |
461 | (clobber (reg:SI 179))])] | |
462 | "" | |
463 | "loadm 0,0,%1,%2") | |
464 | @end smallexample | |
465 | ||
466 | This example comes from @file{a29k.md}. The function | |
9c34dbbf | 467 | @code{load_multiple_operation} is defined in @file{a29k.c} and checks |
03dda8e3 RK |
468 | that subsequent elements in the @code{parallel} are the same as the |
469 | @code{set} in the pattern, except that they are referencing subsequent | |
470 | registers and memory locations. | |
471 | ||
472 | An insn that matches this pattern might look like: | |
473 | ||
474 | @smallexample | |
475 | (parallel | |
476 | [(set (reg:SI 20) (mem:SI (reg:SI 100))) | |
477 | (use (reg:SI 179)) | |
478 | (clobber (reg:SI 179)) | |
479 | (set (reg:SI 21) | |
480 | (mem:SI (plus:SI (reg:SI 100) | |
481 | (const_int 4)))) | |
482 | (set (reg:SI 22) | |
483 | (mem:SI (plus:SI (reg:SI 100) | |
484 | (const_int 8))))]) | |
485 | @end smallexample | |
486 | ||
487 | @findex match_par_dup | |
488 | @item (match_par_dup @var{n} [@var{subpat}@dots{}]) | |
489 | Like @code{match_op_dup}, but for @code{match_parallel} instead of | |
490 | @code{match_operator}. | |
491 | ||
693e265f MM |
492 | @findex match_insn |
493 | @item (match_insn @var{predicate}) | |
494 | Match a complete insn. Unlike the other @code{match_*} recognizers, | |
495 | @code{match_insn} does not take an operand number. | |
496 | ||
497 | The machine mode @var{m} of @code{match_insn} works like that of | |
498 | @code{match_operand}: it is passed as the second argument to the | |
499 | predicate function, and that function is solely responsible for | |
500 | deciding whether the expression to be matched ``has'' that mode. | |
501 | ||
502 | @findex match_insn2 | |
503 | @item (match_insn2 @var{n} @var{predicate}) | |
504 | Match a complete insn. | |
505 | ||
506 | The machine mode @var{m} of @code{match_insn2} works like that of | |
507 | @code{match_operand}: it is passed as the second argument to the | |
508 | predicate function, and that function is solely responsible for | |
509 | deciding whether the expression to be matched ``has'' that mode. | |
510 | ||
03dda8e3 RK |
511 | @end table |
512 | ||
513 | @node Output Template | |
514 | @section Output Templates and Operand Substitution | |
515 | @cindex output templates | |
516 | @cindex operand substitution | |
517 | ||
518 | @cindex @samp{%} in template | |
519 | @cindex percent sign | |
520 | The @dfn{output template} is a string which specifies how to output the | |
521 | assembler code for an instruction pattern. Most of the template is a | |
522 | fixed string which is output literally. The character @samp{%} is used | |
523 | to specify where to substitute an operand; it can also be used to | |
524 | identify places where different variants of the assembler require | |
525 | different syntax. | |
526 | ||
527 | In the simplest case, a @samp{%} followed by a digit @var{n} says to output | |
528 | operand @var{n} at that point in the string. | |
529 | ||
530 | @samp{%} followed by a letter and a digit says to output an operand in an | |
531 | alternate fashion. Four letters have standard, built-in meanings described | |
532 | below. The machine description macro @code{PRINT_OPERAND} can define | |
533 | additional letters with nonstandard meanings. | |
534 | ||
535 | @samp{%c@var{digit}} can be used to substitute an operand that is a | |
536 | constant value without the syntax that normally indicates an immediate | |
537 | operand. | |
538 | ||
539 | @samp{%n@var{digit}} is like @samp{%c@var{digit}} except that the value of | |
540 | the constant is negated before printing. | |
541 | ||
542 | @samp{%a@var{digit}} can be used to substitute an operand as if it were a | |
543 | memory reference, with the actual operand treated as the address. This may | |
544 | be useful when outputting a ``load address'' instruction, because often the | |
545 | assembler syntax for such an instruction requires you to write the operand | |
546 | as if it were a memory reference. | |
547 | ||
548 | @samp{%l@var{digit}} is used to substitute a @code{label_ref} into a jump | |
549 | instruction. | |
550 | ||
551 | @samp{%=} outputs a number which is unique to each instruction in the | |
552 | entire compilation. This is useful for making local labels to be | |
553 | referred to more than once in a single template that generates multiple | |
554 | assembler instructions. | |
555 | ||
556 | @samp{%} followed by a punctuation character specifies a substitution that | |
557 | does not use an operand. Only one case is standard: @samp{%%} outputs a | |
558 | @samp{%} into the assembler code. Other nonstandard cases can be | |
559 | defined in the @code{PRINT_OPERAND} macro. You must also define | |
560 | which punctuation characters are valid with the | |
561 | @code{PRINT_OPERAND_PUNCT_VALID_P} macro. | |
562 | ||
563 | @cindex \ | |
564 | @cindex backslash | |
565 | The template may generate multiple assembler instructions. Write the text | |
566 | for the instructions, with @samp{\;} between them. | |
567 | ||
568 | @cindex matching operands | |
569 | When the RTL contains two operands which are required by constraint to match | |
570 | each other, the output template must refer only to the lower-numbered operand. | |
571 | Matching operands are not always identical, and the rest of the compiler | |
572 | arranges to put the proper RTL expression for printing into the lower-numbered | |
573 | operand. | |
574 | ||
575 | One use of nonstandard letters or punctuation following @samp{%} is to | |
576 | distinguish between different assembler languages for the same machine; for | |
577 | example, Motorola syntax versus MIT syntax for the 68000. Motorola syntax | |
578 | requires periods in most opcode names, while MIT syntax does not. For | |
579 | example, the opcode @samp{movel} in MIT syntax is @samp{move.l} in Motorola | |
580 | syntax. The same file of patterns is used for both kinds of output syntax, | |
581 | but the character sequence @samp{%.} is used in each place where Motorola | |
582 | syntax wants a period. The @code{PRINT_OPERAND} macro for Motorola syntax | |
583 | defines the sequence to output a period; the macro for MIT syntax defines | |
584 | it to do nothing. | |
585 | ||
586 | @cindex @code{#} in template | |
587 | As a special case, a template consisting of the single character @code{#} | |
588 | instructs the compiler to first split the insn, and then output the | |
589 | resulting instructions separately. This helps eliminate redundancy in the | |
590 | output templates. If you have a @code{define_insn} that needs to emit | |
591 | multiple assembler instructions, and there is an matching @code{define_split} | |
592 | already defined, then you can simply use @code{#} as the output template | |
593 | instead of writing an output template that emits the multiple assembler | |
594 | instructions. | |
595 | ||
596 | If the macro @code{ASSEMBLER_DIALECT} is defined, you can use construct | |
597 | of the form @samp{@{option0|option1|option2@}} in the templates. These | |
598 | describe multiple variants of assembler language syntax. | |
599 | @xref{Instruction Output}. | |
600 | ||
601 | @node Output Statement | |
602 | @section C Statements for Assembler Output | |
603 | @cindex output statements | |
604 | @cindex C statements for assembler output | |
605 | @cindex generating assembler output | |
606 | ||
607 | Often a single fixed template string cannot produce correct and efficient | |
608 | assembler code for all the cases that are recognized by a single | |
609 | instruction pattern. For example, the opcodes may depend on the kinds of | |
610 | operands; or some unfortunate combinations of operands may require extra | |
611 | machine instructions. | |
612 | ||
613 | If the output control string starts with a @samp{@@}, then it is actually | |
614 | a series of templates, each on a separate line. (Blank lines and | |
615 | leading spaces and tabs are ignored.) The templates correspond to the | |
616 | pattern's constraint alternatives (@pxref{Multi-Alternative}). For example, | |
617 | if a target machine has a two-address add instruction @samp{addr} to add | |
618 | into a register and another @samp{addm} to add a register to memory, you | |
619 | might write this pattern: | |
620 | ||
621 | @smallexample | |
622 | (define_insn "addsi3" | |
623 | [(set (match_operand:SI 0 "general_operand" "=r,m") | |
624 | (plus:SI (match_operand:SI 1 "general_operand" "0,0") | |
625 | (match_operand:SI 2 "general_operand" "g,r")))] | |
626 | "" | |
627 | "@@ | |
628 | addr %2,%0 | |
629 | addm %2,%0") | |
630 | @end smallexample | |
631 | ||
632 | @cindex @code{*} in template | |
633 | @cindex asterisk in template | |
634 | If the output control string starts with a @samp{*}, then it is not an | |
635 | output template but rather a piece of C program that should compute a | |
636 | template. It should execute a @code{return} statement to return the | |
637 | template-string you want. Most such templates use C string literals, which | |
638 | require doublequote characters to delimit them. To include these | |
639 | doublequote characters in the string, prefix each one with @samp{\}. | |
640 | ||
0f40f9f7 ZW |
641 | If the output control string is written as a brace block instead of a |
642 | double-quoted string, it is automatically assumed to be C code. In that | |
643 | case, it is not necessary to put in a leading asterisk, or to escape the | |
644 | doublequotes surrounding C string literals. | |
645 | ||
03dda8e3 RK |
646 | The operands may be found in the array @code{operands}, whose C data type |
647 | is @code{rtx []}. | |
648 | ||
649 | It is very common to select different ways of generating assembler code | |
650 | based on whether an immediate operand is within a certain range. Be | |
651 | careful when doing this, because the result of @code{INTVAL} is an | |
652 | integer on the host machine. If the host machine has more bits in an | |
653 | @code{int} than the target machine has in the mode in which the constant | |
654 | will be used, then some of the bits you get from @code{INTVAL} will be | |
655 | superfluous. For proper results, you must carefully disregard the | |
656 | values of those bits. | |
657 | ||
658 | @findex output_asm_insn | |
659 | It is possible to output an assembler instruction and then go on to output | |
660 | or compute more of them, using the subroutine @code{output_asm_insn}. This | |
661 | receives two arguments: a template-string and a vector of operands. The | |
662 | vector may be @code{operands}, or it may be another array of @code{rtx} | |
663 | that you declare locally and initialize yourself. | |
664 | ||
665 | @findex which_alternative | |
666 | When an insn pattern has multiple alternatives in its constraints, often | |
667 | the appearance of the assembler code is determined mostly by which alternative | |
668 | was matched. When this is so, the C code can test the variable | |
669 | @code{which_alternative}, which is the ordinal number of the alternative | |
670 | that was actually satisfied (0 for the first, 1 for the second alternative, | |
671 | etc.). | |
672 | ||
673 | For example, suppose there are two opcodes for storing zero, @samp{clrreg} | |
674 | for registers and @samp{clrmem} for memory locations. Here is how | |
675 | a pattern could use @code{which_alternative} to choose between them: | |
676 | ||
677 | @smallexample | |
678 | (define_insn "" | |
679 | [(set (match_operand:SI 0 "general_operand" "=r,m") | |
680 | (const_int 0))] | |
681 | "" | |
0f40f9f7 | 682 | @{ |
03dda8e3 | 683 | return (which_alternative == 0 |
0f40f9f7 ZW |
684 | ? "clrreg %0" : "clrmem %0"); |
685 | @}) | |
03dda8e3 RK |
686 | @end smallexample |
687 | ||
688 | The example above, where the assembler code to generate was | |
689 | @emph{solely} determined by the alternative, could also have been specified | |
690 | as follows, having the output control string start with a @samp{@@}: | |
691 | ||
692 | @smallexample | |
693 | @group | |
694 | (define_insn "" | |
695 | [(set (match_operand:SI 0 "general_operand" "=r,m") | |
696 | (const_int 0))] | |
697 | "" | |
698 | "@@ | |
699 | clrreg %0 | |
700 | clrmem %0") | |
701 | @end group | |
702 | @end smallexample | |
703 | @end ifset | |
704 | ||
705 | @c Most of this node appears by itself (in a different place) even | |
b11cc610 JM |
706 | @c when the INTERNALS flag is clear. Passages that require the internals |
707 | @c manual's context are conditionalized to appear only in the internals manual. | |
03dda8e3 RK |
708 | @ifset INTERNALS |
709 | @node Constraints | |
710 | @section Operand Constraints | |
711 | @cindex operand constraints | |
712 | @cindex constraints | |
713 | ||
714 | Each @code{match_operand} in an instruction pattern can specify a | |
715 | constraint for the type of operands allowed. | |
716 | @end ifset | |
717 | @ifclear INTERNALS | |
718 | @node Constraints | |
719 | @section Constraints for @code{asm} Operands | |
720 | @cindex operand constraints, @code{asm} | |
721 | @cindex constraints, @code{asm} | |
722 | @cindex @code{asm} constraints | |
723 | ||
724 | Here are specific details on what constraint letters you can use with | |
725 | @code{asm} operands. | |
726 | @end ifclear | |
727 | Constraints can say whether | |
728 | an operand may be in a register, and which kinds of register; whether the | |
729 | operand can be a memory reference, and which kinds of address; whether the | |
730 | operand may be an immediate constant, and which possible values it may | |
731 | have. Constraints can also require two operands to match. | |
732 | ||
733 | @ifset INTERNALS | |
734 | @menu | |
735 | * Simple Constraints:: Basic use of constraints. | |
736 | * Multi-Alternative:: When an insn has two alternative constraint-patterns. | |
737 | * Class Preferences:: Constraints guide which hard register to put things in. | |
738 | * Modifiers:: More precise control over effects of constraints. | |
739 | * Machine Constraints:: Existing constraints for some particular machines. | |
03dda8e3 RK |
740 | @end menu |
741 | @end ifset | |
742 | ||
743 | @ifclear INTERNALS | |
744 | @menu | |
745 | * Simple Constraints:: Basic use of constraints. | |
746 | * Multi-Alternative:: When an insn has two alternative constraint-patterns. | |
747 | * Modifiers:: More precise control over effects of constraints. | |
748 | * Machine Constraints:: Special constraints for some particular machines. | |
749 | @end menu | |
750 | @end ifclear | |
751 | ||
752 | @node Simple Constraints | |
753 | @subsection Simple Constraints | |
754 | @cindex simple constraints | |
755 | ||
756 | The simplest kind of constraint is a string full of letters, each of | |
757 | which describes one kind of operand that is permitted. Here are | |
758 | the letters that are allowed: | |
759 | ||
760 | @table @asis | |
88a56c2e HPN |
761 | @item whitespace |
762 | Whitespace characters are ignored and can be inserted at any position | |
763 | except the first. This enables each alternative for different operands to | |
764 | be visually aligned in the machine description even if they have different | |
765 | number of constraints and modifiers. | |
766 | ||
03dda8e3 RK |
767 | @cindex @samp{m} in constraint |
768 | @cindex memory references in constraints | |
769 | @item @samp{m} | |
770 | A memory operand is allowed, with any kind of address that the machine | |
771 | supports in general. | |
772 | ||
773 | @cindex offsettable address | |
774 | @cindex @samp{o} in constraint | |
775 | @item @samp{o} | |
776 | A memory operand is allowed, but only if the address is | |
777 | @dfn{offsettable}. This means that adding a small integer (actually, | |
778 | the width in bytes of the operand, as determined by its machine mode) | |
779 | may be added to the address and the result is also a valid memory | |
780 | address. | |
781 | ||
782 | @cindex autoincrement/decrement addressing | |
783 | For example, an address which is constant is offsettable; so is an | |
784 | address that is the sum of a register and a constant (as long as a | |
785 | slightly larger constant is also within the range of address-offsets | |
786 | supported by the machine); but an autoincrement or autodecrement | |
787 | address is not offsettable. More complicated indirect/indexed | |
788 | addresses may or may not be offsettable depending on the other | |
789 | addressing modes that the machine supports. | |
790 | ||
791 | Note that in an output operand which can be matched by another | |
792 | operand, the constraint letter @samp{o} is valid only when accompanied | |
793 | by both @samp{<} (if the target machine has predecrement addressing) | |
794 | and @samp{>} (if the target machine has preincrement addressing). | |
795 | ||
796 | @cindex @samp{V} in constraint | |
797 | @item @samp{V} | |
798 | A memory operand that is not offsettable. In other words, anything that | |
799 | would fit the @samp{m} constraint but not the @samp{o} constraint. | |
800 | ||
801 | @cindex @samp{<} in constraint | |
802 | @item @samp{<} | |
803 | A memory operand with autodecrement addressing (either predecrement or | |
804 | postdecrement) is allowed. | |
805 | ||
806 | @cindex @samp{>} in constraint | |
807 | @item @samp{>} | |
808 | A memory operand with autoincrement addressing (either preincrement or | |
809 | postincrement) is allowed. | |
810 | ||
811 | @cindex @samp{r} in constraint | |
812 | @cindex registers in constraints | |
813 | @item @samp{r} | |
814 | A register operand is allowed provided that it is in a general | |
815 | register. | |
816 | ||
03dda8e3 RK |
817 | @cindex constants in constraints |
818 | @cindex @samp{i} in constraint | |
819 | @item @samp{i} | |
820 | An immediate integer operand (one with constant value) is allowed. | |
821 | This includes symbolic constants whose values will be known only at | |
822 | assembly time. | |
823 | ||
824 | @cindex @samp{n} in constraint | |
825 | @item @samp{n} | |
826 | An immediate integer operand with a known numeric value is allowed. | |
827 | Many systems cannot support assembly-time constants for operands less | |
828 | than a word wide. Constraints for these operands should use @samp{n} | |
829 | rather than @samp{i}. | |
830 | ||
831 | @cindex @samp{I} in constraint | |
832 | @item @samp{I}, @samp{J}, @samp{K}, @dots{} @samp{P} | |
833 | Other letters in the range @samp{I} through @samp{P} may be defined in | |
834 | a machine-dependent fashion to permit immediate integer operands with | |
835 | explicit integer values in specified ranges. For example, on the | |
836 | 68000, @samp{I} is defined to stand for the range of values 1 to 8. | |
837 | This is the range permitted as a shift count in the shift | |
838 | instructions. | |
839 | ||
840 | @cindex @samp{E} in constraint | |
841 | @item @samp{E} | |
842 | An immediate floating operand (expression code @code{const_double}) is | |
843 | allowed, but only if the target floating point format is the same as | |
844 | that of the host machine (on which the compiler is running). | |
845 | ||
846 | @cindex @samp{F} in constraint | |
847 | @item @samp{F} | |
bf7cd754 R |
848 | An immediate floating operand (expression code @code{const_double} or |
849 | @code{const_vector}) is allowed. | |
03dda8e3 RK |
850 | |
851 | @cindex @samp{G} in constraint | |
852 | @cindex @samp{H} in constraint | |
853 | @item @samp{G}, @samp{H} | |
854 | @samp{G} and @samp{H} may be defined in a machine-dependent fashion to | |
855 | permit immediate floating operands in particular ranges of values. | |
856 | ||
857 | @cindex @samp{s} in constraint | |
858 | @item @samp{s} | |
859 | An immediate integer operand whose value is not an explicit integer is | |
860 | allowed. | |
861 | ||
862 | This might appear strange; if an insn allows a constant operand with a | |
863 | value not known at compile time, it certainly must allow any known | |
864 | value. So why use @samp{s} instead of @samp{i}? Sometimes it allows | |
865 | better code to be generated. | |
866 | ||
867 | For example, on the 68000 in a fullword instruction it is possible to | |
630d3d5a | 868 | use an immediate operand; but if the immediate value is between @minus{}128 |
03dda8e3 RK |
869 | and 127, better code results from loading the value into a register and |
870 | using the register. This is because the load into the register can be | |
871 | done with a @samp{moveq} instruction. We arrange for this to happen | |
872 | by defining the letter @samp{K} to mean ``any integer outside the | |
630d3d5a | 873 | range @minus{}128 to 127'', and then specifying @samp{Ks} in the operand |
03dda8e3 RK |
874 | constraints. |
875 | ||
876 | @cindex @samp{g} in constraint | |
877 | @item @samp{g} | |
878 | Any register, memory or immediate integer operand is allowed, except for | |
879 | registers that are not general registers. | |
880 | ||
881 | @cindex @samp{X} in constraint | |
882 | @item @samp{X} | |
883 | @ifset INTERNALS | |
884 | Any operand whatsoever is allowed, even if it does not satisfy | |
885 | @code{general_operand}. This is normally used in the constraint of | |
886 | a @code{match_scratch} when certain alternatives will not actually | |
887 | require a scratch register. | |
888 | @end ifset | |
889 | @ifclear INTERNALS | |
890 | Any operand whatsoever is allowed. | |
891 | @end ifclear | |
892 | ||
893 | @cindex @samp{0} in constraint | |
894 | @cindex digits in constraint | |
895 | @item @samp{0}, @samp{1}, @samp{2}, @dots{} @samp{9} | |
896 | An operand that matches the specified operand number is allowed. If a | |
897 | digit is used together with letters within the same alternative, the | |
898 | digit should come last. | |
899 | ||
84b72302 RH |
900 | This number is allowed to be more than a single digit. If multiple |
901 | digits are encountered consecutavely, they are interpreted as a single | |
902 | decimal integer. There is scant chance for ambiguity, since to-date | |
903 | it has never been desirable that @samp{10} be interpreted as matching | |
904 | either operand 1 @emph{or} operand 0. Should this be desired, one | |
905 | can use multiple alternatives instead. | |
906 | ||
03dda8e3 RK |
907 | @cindex matching constraint |
908 | @cindex constraint, matching | |
909 | This is called a @dfn{matching constraint} and what it really means is | |
910 | that the assembler has only a single operand that fills two roles | |
911 | @ifset INTERNALS | |
912 | considered separate in the RTL insn. For example, an add insn has two | |
913 | input operands and one output operand in the RTL, but on most CISC | |
914 | @end ifset | |
915 | @ifclear INTERNALS | |
916 | which @code{asm} distinguishes. For example, an add instruction uses | |
917 | two input operands and an output operand, but on most CISC | |
918 | @end ifclear | |
919 | machines an add instruction really has only two operands, one of them an | |
920 | input-output operand: | |
921 | ||
922 | @smallexample | |
923 | addl #35,r12 | |
924 | @end smallexample | |
925 | ||
926 | Matching constraints are used in these circumstances. | |
927 | More precisely, the two operands that match must include one input-only | |
928 | operand and one output-only operand. Moreover, the digit must be a | |
929 | smaller number than the number of the operand that uses it in the | |
930 | constraint. | |
931 | ||
932 | @ifset INTERNALS | |
933 | For operands to match in a particular case usually means that they | |
934 | are identical-looking RTL expressions. But in a few special cases | |
935 | specific kinds of dissimilarity are allowed. For example, @code{*x} | |
936 | as an input operand will match @code{*x++} as an output operand. | |
937 | For proper results in such cases, the output template should always | |
938 | use the output-operand's number when printing the operand. | |
939 | @end ifset | |
940 | ||
941 | @cindex load address instruction | |
942 | @cindex push address instruction | |
943 | @cindex address constraints | |
944 | @cindex @samp{p} in constraint | |
945 | @item @samp{p} | |
946 | An operand that is a valid memory address is allowed. This is | |
947 | for ``load address'' and ``push address'' instructions. | |
948 | ||
949 | @findex address_operand | |
950 | @samp{p} in the constraint must be accompanied by @code{address_operand} | |
951 | as the predicate in the @code{match_operand}. This predicate interprets | |
952 | the mode specified in the @code{match_operand} as the mode of the memory | |
953 | reference for which the address would be valid. | |
954 | ||
c2cba7a9 | 955 | @cindex other register constraints |
03dda8e3 | 956 | @cindex extensible constraints |
630d3d5a | 957 | @item @var{other-letters} |
c2cba7a9 RH |
958 | Other letters can be defined in machine-dependent fashion to stand for |
959 | particular classes of registers or other arbitrary operand types. | |
960 | @samp{d}, @samp{a} and @samp{f} are defined on the 68000/68020 to stand | |
961 | for data, address and floating point registers. | |
03dda8e3 | 962 | |
c2cba7a9 RH |
963 | @ifset INTERNALS |
964 | The machine description macro @code{REG_CLASS_FROM_LETTER} has first | |
965 | cut at the otherwise unused letters. If it evaluates to @code{NO_REGS}, | |
966 | then @code{EXTRA_CONSTRAINT} is evaluated. | |
03dda8e3 | 967 | |
c2cba7a9 RH |
968 | A typical use for @code{EXTRA_CONSTRANT} would be to distinguish certain |
969 | types of memory references that affect other insn operands. | |
03dda8e3 RK |
970 | @end ifset |
971 | @end table | |
972 | ||
973 | @ifset INTERNALS | |
974 | In order to have valid assembler code, each operand must satisfy | |
975 | its constraint. But a failure to do so does not prevent the pattern | |
976 | from applying to an insn. Instead, it directs the compiler to modify | |
977 | the code so that the constraint will be satisfied. Usually this is | |
978 | done by copying an operand into a register. | |
979 | ||
980 | Contrast, therefore, the two instruction patterns that follow: | |
981 | ||
982 | @smallexample | |
983 | (define_insn "" | |
984 | [(set (match_operand:SI 0 "general_operand" "=r") | |
985 | (plus:SI (match_dup 0) | |
986 | (match_operand:SI 1 "general_operand" "r")))] | |
987 | "" | |
988 | "@dots{}") | |
989 | @end smallexample | |
990 | ||
991 | @noindent | |
992 | which has two operands, one of which must appear in two places, and | |
993 | ||
994 | @smallexample | |
995 | (define_insn "" | |
996 | [(set (match_operand:SI 0 "general_operand" "=r") | |
997 | (plus:SI (match_operand:SI 1 "general_operand" "0") | |
998 | (match_operand:SI 2 "general_operand" "r")))] | |
999 | "" | |
1000 | "@dots{}") | |
1001 | @end smallexample | |
1002 | ||
1003 | @noindent | |
1004 | which has three operands, two of which are required by a constraint to be | |
1005 | identical. If we are considering an insn of the form | |
1006 | ||
1007 | @smallexample | |
1008 | (insn @var{n} @var{prev} @var{next} | |
1009 | (set (reg:SI 3) | |
1010 | (plus:SI (reg:SI 6) (reg:SI 109))) | |
1011 | @dots{}) | |
1012 | @end smallexample | |
1013 | ||
1014 | @noindent | |
1015 | the first pattern would not apply at all, because this insn does not | |
1016 | contain two identical subexpressions in the right place. The pattern would | |
1017 | say, ``That does not look like an add instruction; try other patterns.'' | |
1018 | The second pattern would say, ``Yes, that's an add instruction, but there | |
1019 | is something wrong with it.'' It would direct the reload pass of the | |
1020 | compiler to generate additional insns to make the constraint true. The | |
1021 | results might look like this: | |
1022 | ||
1023 | @smallexample | |
1024 | (insn @var{n2} @var{prev} @var{n} | |
1025 | (set (reg:SI 3) (reg:SI 6)) | |
1026 | @dots{}) | |
1027 | ||
1028 | (insn @var{n} @var{n2} @var{next} | |
1029 | (set (reg:SI 3) | |
1030 | (plus:SI (reg:SI 3) (reg:SI 109))) | |
1031 | @dots{}) | |
1032 | @end smallexample | |
1033 | ||
1034 | It is up to you to make sure that each operand, in each pattern, has | |
1035 | constraints that can handle any RTL expression that could be present for | |
1036 | that operand. (When multiple alternatives are in use, each pattern must, | |
1037 | for each possible combination of operand expressions, have at least one | |
1038 | alternative which can handle that combination of operands.) The | |
1039 | constraints don't need to @emph{allow} any possible operand---when this is | |
1040 | the case, they do not constrain---but they must at least point the way to | |
1041 | reloading any possible operand so that it will fit. | |
1042 | ||
1043 | @itemize @bullet | |
1044 | @item | |
1045 | If the constraint accepts whatever operands the predicate permits, | |
1046 | there is no problem: reloading is never necessary for this operand. | |
1047 | ||
1048 | For example, an operand whose constraints permit everything except | |
1049 | registers is safe provided its predicate rejects registers. | |
1050 | ||
1051 | An operand whose predicate accepts only constant values is safe | |
1052 | provided its constraints include the letter @samp{i}. If any possible | |
1053 | constant value is accepted, then nothing less than @samp{i} will do; | |
1054 | if the predicate is more selective, then the constraints may also be | |
1055 | more selective. | |
1056 | ||
1057 | @item | |
1058 | Any operand expression can be reloaded by copying it into a register. | |
1059 | So if an operand's constraints allow some kind of register, it is | |
1060 | certain to be safe. It need not permit all classes of registers; the | |
1061 | compiler knows how to copy a register into another register of the | |
1062 | proper class in order to make an instruction valid. | |
1063 | ||
1064 | @cindex nonoffsettable memory reference | |
1065 | @cindex memory reference, nonoffsettable | |
1066 | @item | |
1067 | A nonoffsettable memory reference can be reloaded by copying the | |
1068 | address into a register. So if the constraint uses the letter | |
1069 | @samp{o}, all memory references are taken care of. | |
1070 | ||
1071 | @item | |
1072 | A constant operand can be reloaded by allocating space in memory to | |
1073 | hold it as preinitialized data. Then the memory reference can be used | |
1074 | in place of the constant. So if the constraint uses the letters | |
1075 | @samp{o} or @samp{m}, constant operands are not a problem. | |
1076 | ||
1077 | @item | |
1078 | If the constraint permits a constant and a pseudo register used in an insn | |
1079 | was not allocated to a hard register and is equivalent to a constant, | |
1080 | the register will be replaced with the constant. If the predicate does | |
1081 | not permit a constant and the insn is re-recognized for some reason, the | |
1082 | compiler will crash. Thus the predicate must always recognize any | |
1083 | objects allowed by the constraint. | |
1084 | @end itemize | |
1085 | ||
1086 | If the operand's predicate can recognize registers, but the constraint does | |
1087 | not permit them, it can make the compiler crash. When this operand happens | |
1088 | to be a register, the reload pass will be stymied, because it does not know | |
1089 | how to copy a register temporarily into memory. | |
1090 | ||
1091 | If the predicate accepts a unary operator, the constraint applies to the | |
1092 | operand. For example, the MIPS processor at ISA level 3 supports an | |
1093 | instruction which adds two registers in @code{SImode} to produce a | |
1094 | @code{DImode} result, but only if the registers are correctly sign | |
1095 | extended. This predicate for the input operands accepts a | |
1096 | @code{sign_extend} of an @code{SImode} register. Write the constraint | |
1097 | to indicate the type of register that is required for the operand of the | |
1098 | @code{sign_extend}. | |
1099 | @end ifset | |
1100 | ||
1101 | @node Multi-Alternative | |
1102 | @subsection Multiple Alternative Constraints | |
1103 | @cindex multiple alternative constraints | |
1104 | ||
1105 | Sometimes a single instruction has multiple alternative sets of possible | |
1106 | operands. For example, on the 68000, a logical-or instruction can combine | |
1107 | register or an immediate value into memory, or it can combine any kind of | |
1108 | operand into a register; but it cannot combine one memory location into | |
1109 | another. | |
1110 | ||
1111 | These constraints are represented as multiple alternatives. An alternative | |
1112 | can be described by a series of letters for each operand. The overall | |
1113 | constraint for an operand is made from the letters for this operand | |
1114 | from the first alternative, a comma, the letters for this operand from | |
1115 | the second alternative, a comma, and so on until the last alternative. | |
1116 | @ifset INTERNALS | |
1117 | Here is how it is done for fullword logical-or on the 68000: | |
1118 | ||
1119 | @smallexample | |
1120 | (define_insn "iorsi3" | |
1121 | [(set (match_operand:SI 0 "general_operand" "=m,d") | |
1122 | (ior:SI (match_operand:SI 1 "general_operand" "%0,0") | |
1123 | (match_operand:SI 2 "general_operand" "dKs,dmKs")))] | |
1124 | @dots{}) | |
1125 | @end smallexample | |
1126 | ||
1127 | The first alternative has @samp{m} (memory) for operand 0, @samp{0} for | |
1128 | operand 1 (meaning it must match operand 0), and @samp{dKs} for operand | |
1129 | 2. The second alternative has @samp{d} (data register) for operand 0, | |
1130 | @samp{0} for operand 1, and @samp{dmKs} for operand 2. The @samp{=} and | |
1131 | @samp{%} in the constraints apply to all the alternatives; their | |
1132 | meaning is explained in the next section (@pxref{Class Preferences}). | |
1133 | @end ifset | |
1134 | ||
1135 | @c FIXME Is this ? and ! stuff of use in asm()? If not, hide unless INTERNAL | |
1136 | If all the operands fit any one alternative, the instruction is valid. | |
1137 | Otherwise, for each alternative, the compiler counts how many instructions | |
1138 | must be added to copy the operands so that that alternative applies. | |
1139 | The alternative requiring the least copying is chosen. If two alternatives | |
1140 | need the same amount of copying, the one that comes first is chosen. | |
1141 | These choices can be altered with the @samp{?} and @samp{!} characters: | |
1142 | ||
1143 | @table @code | |
1144 | @cindex @samp{?} in constraint | |
1145 | @cindex question mark | |
1146 | @item ? | |
1147 | Disparage slightly the alternative that the @samp{?} appears in, | |
1148 | as a choice when no alternative applies exactly. The compiler regards | |
1149 | this alternative as one unit more costly for each @samp{?} that appears | |
1150 | in it. | |
1151 | ||
1152 | @cindex @samp{!} in constraint | |
1153 | @cindex exclamation point | |
1154 | @item ! | |
1155 | Disparage severely the alternative that the @samp{!} appears in. | |
1156 | This alternative can still be used if it fits without reloading, | |
1157 | but if reloading is needed, some other alternative will be used. | |
1158 | @end table | |
1159 | ||
1160 | @ifset INTERNALS | |
1161 | When an insn pattern has multiple alternatives in its constraints, often | |
1162 | the appearance of the assembler code is determined mostly by which | |
1163 | alternative was matched. When this is so, the C code for writing the | |
1164 | assembler code can use the variable @code{which_alternative}, which is | |
1165 | the ordinal number of the alternative that was actually satisfied (0 for | |
1166 | the first, 1 for the second alternative, etc.). @xref{Output Statement}. | |
1167 | @end ifset | |
1168 | ||
1169 | @ifset INTERNALS | |
1170 | @node Class Preferences | |
1171 | @subsection Register Class Preferences | |
1172 | @cindex class preference constraints | |
1173 | @cindex register class preference constraints | |
1174 | ||
1175 | @cindex voting between constraint alternatives | |
1176 | The operand constraints have another function: they enable the compiler | |
1177 | to decide which kind of hardware register a pseudo register is best | |
1178 | allocated to. The compiler examines the constraints that apply to the | |
1179 | insns that use the pseudo register, looking for the machine-dependent | |
1180 | letters such as @samp{d} and @samp{a} that specify classes of registers. | |
1181 | The pseudo register is put in whichever class gets the most ``votes''. | |
1182 | The constraint letters @samp{g} and @samp{r} also vote: they vote in | |
1183 | favor of a general register. The machine description says which registers | |
1184 | are considered general. | |
1185 | ||
1186 | Of course, on some machines all registers are equivalent, and no register | |
1187 | classes are defined. Then none of this complexity is relevant. | |
1188 | @end ifset | |
1189 | ||
1190 | @node Modifiers | |
1191 | @subsection Constraint Modifier Characters | |
1192 | @cindex modifiers in constraints | |
1193 | @cindex constraint modifier characters | |
1194 | ||
1195 | @c prevent bad page break with this line | |
1196 | Here are constraint modifier characters. | |
1197 | ||
1198 | @table @samp | |
1199 | @cindex @samp{=} in constraint | |
1200 | @item = | |
1201 | Means that this operand is write-only for this instruction: the previous | |
1202 | value is discarded and replaced by output data. | |
1203 | ||
1204 | @cindex @samp{+} in constraint | |
1205 | @item + | |
1206 | Means that this operand is both read and written by the instruction. | |
1207 | ||
1208 | When the compiler fixes up the operands to satisfy the constraints, | |
1209 | it needs to know which operands are inputs to the instruction and | |
1210 | which are outputs from it. @samp{=} identifies an output; @samp{+} | |
1211 | identifies an operand that is both input and output; all other operands | |
1212 | are assumed to be input only. | |
1213 | ||
c5c76735 JL |
1214 | If you specify @samp{=} or @samp{+} in a constraint, you put it in the |
1215 | first character of the constraint string. | |
1216 | ||
03dda8e3 RK |
1217 | @cindex @samp{&} in constraint |
1218 | @cindex earlyclobber operand | |
1219 | @item & | |
1220 | Means (in a particular alternative) that this operand is an | |
1221 | @dfn{earlyclobber} operand, which is modified before the instruction is | |
1222 | finished using the input operands. Therefore, this operand may not lie | |
1223 | in a register that is used as an input operand or as part of any memory | |
1224 | address. | |
1225 | ||
1226 | @samp{&} applies only to the alternative in which it is written. In | |
1227 | constraints with multiple alternatives, sometimes one alternative | |
1228 | requires @samp{&} while others do not. See, for example, the | |
1229 | @samp{movdf} insn of the 68000. | |
1230 | ||
ebb48a4d | 1231 | An input operand can be tied to an earlyclobber operand if its only |
03dda8e3 RK |
1232 | use as an input occurs before the early result is written. Adding |
1233 | alternatives of this form often allows GCC to produce better code | |
ebb48a4d | 1234 | when only some of the inputs can be affected by the earlyclobber. |
161d7b59 | 1235 | See, for example, the @samp{mulsi3} insn of the ARM@. |
03dda8e3 RK |
1236 | |
1237 | @samp{&} does not obviate the need to write @samp{=}. | |
1238 | ||
1239 | @cindex @samp{%} in constraint | |
1240 | @item % | |
1241 | Declares the instruction to be commutative for this operand and the | |
1242 | following operand. This means that the compiler may interchange the | |
1243 | two operands if that is the cheapest way to make all operands fit the | |
1244 | constraints. | |
1245 | @ifset INTERNALS | |
1246 | This is often used in patterns for addition instructions | |
1247 | that really have only two operands: the result must go in one of the | |
1248 | arguments. Here for example, is how the 68000 halfword-add | |
1249 | instruction is defined: | |
1250 | ||
1251 | @smallexample | |
1252 | (define_insn "addhi3" | |
1253 | [(set (match_operand:HI 0 "general_operand" "=m,r") | |
1254 | (plus:HI (match_operand:HI 1 "general_operand" "%0,0") | |
1255 | (match_operand:HI 2 "general_operand" "di,g")))] | |
1256 | @dots{}) | |
1257 | @end smallexample | |
1258 | @end ifset | |
1259 | ||
1260 | @cindex @samp{#} in constraint | |
1261 | @item # | |
1262 | Says that all following characters, up to the next comma, are to be | |
1263 | ignored as a constraint. They are significant only for choosing | |
1264 | register preferences. | |
1265 | ||
03dda8e3 RK |
1266 | @cindex @samp{*} in constraint |
1267 | @item * | |
1268 | Says that the following character should be ignored when choosing | |
1269 | register preferences. @samp{*} has no effect on the meaning of the | |
1270 | constraint as a constraint, and no effect on reloading. | |
1271 | ||
9f339dde | 1272 | @ifset INTERNALS |
03dda8e3 RK |
1273 | Here is an example: the 68000 has an instruction to sign-extend a |
1274 | halfword in a data register, and can also sign-extend a value by | |
1275 | copying it into an address register. While either kind of register is | |
1276 | acceptable, the constraints on an address-register destination are | |
1277 | less strict, so it is best if register allocation makes an address | |
1278 | register its goal. Therefore, @samp{*} is used so that the @samp{d} | |
1279 | constraint letter (for data register) is ignored when computing | |
1280 | register preferences. | |
1281 | ||
1282 | @smallexample | |
1283 | (define_insn "extendhisi2" | |
1284 | [(set (match_operand:SI 0 "general_operand" "=*d,a") | |
1285 | (sign_extend:SI | |
1286 | (match_operand:HI 1 "general_operand" "0,g")))] | |
1287 | @dots{}) | |
1288 | @end smallexample | |
1289 | @end ifset | |
1290 | @end table | |
1291 | ||
1292 | @node Machine Constraints | |
1293 | @subsection Constraints for Particular Machines | |
1294 | @cindex machine specific constraints | |
1295 | @cindex constraints, machine specific | |
1296 | ||
1297 | Whenever possible, you should use the general-purpose constraint letters | |
1298 | in @code{asm} arguments, since they will convey meaning more readily to | |
1299 | people reading your code. Failing that, use the constraint letters | |
1300 | that usually have very similar meanings across architectures. The most | |
1301 | commonly used constraints are @samp{m} and @samp{r} (for memory and | |
1302 | general-purpose registers respectively; @pxref{Simple Constraints}), and | |
1303 | @samp{I}, usually the letter indicating the most common | |
1304 | immediate-constant format. | |
1305 | ||
9c34dbbf ZW |
1306 | For each machine architecture, the |
1307 | @file{config/@var{machine}/@var{machine}.h} file defines additional | |
1308 | constraints. These constraints are used by the compiler itself for | |
1309 | instruction generation, as well as for @code{asm} statements; therefore, | |
1310 | some of the constraints are not particularly interesting for @code{asm}. | |
1311 | The constraints are defined through these macros: | |
03dda8e3 RK |
1312 | |
1313 | @table @code | |
1314 | @item REG_CLASS_FROM_LETTER | |
1315 | Register class constraints (usually lower case). | |
1316 | ||
1317 | @item CONST_OK_FOR_LETTER_P | |
1318 | Immediate constant constraints, for non-floating point constants of | |
1319 | word size or smaller precision (usually upper case). | |
1320 | ||
1321 | @item CONST_DOUBLE_OK_FOR_LETTER_P | |
1322 | Immediate constant constraints, for all floating point constants and for | |
1323 | constants of greater than word size precision (usually upper case). | |
1324 | ||
1325 | @item EXTRA_CONSTRAINT | |
1326 | Special cases of registers or memory. This macro is not required, and | |
1327 | is only defined for some machines. | |
1328 | @end table | |
1329 | ||
1330 | Inspecting these macro definitions in the compiler source for your | |
1331 | machine is the best way to be certain you have the right constraints. | |
1332 | However, here is a summary of the machine-dependent constraints | |
1333 | available on some particular machines. | |
1334 | ||
1335 | @table @emph | |
1336 | @item ARM family---@file{arm.h} | |
1337 | @table @code | |
1338 | @item f | |
1339 | Floating-point register | |
1340 | ||
1341 | @item F | |
1342 | One of the floating-point constants 0.0, 0.5, 1.0, 2.0, 3.0, 4.0, 5.0 | |
1343 | or 10.0 | |
1344 | ||
1345 | @item G | |
1346 | Floating-point constant that would satisfy the constraint @samp{F} if it | |
1347 | were negated | |
1348 | ||
1349 | @item I | |
1350 | Integer that is valid as an immediate operand in a data processing | |
1351 | instruction. That is, an integer in the range 0 to 255 rotated by a | |
1352 | multiple of 2 | |
1353 | ||
1354 | @item J | |
630d3d5a | 1355 | Integer in the range @minus{}4095 to 4095 |
03dda8e3 RK |
1356 | |
1357 | @item K | |
1358 | Integer that satisfies constraint @samp{I} when inverted (ones complement) | |
1359 | ||
1360 | @item L | |
1361 | Integer that satisfies constraint @samp{I} when negated (twos complement) | |
1362 | ||
1363 | @item M | |
1364 | Integer in the range 0 to 32 | |
1365 | ||
1366 | @item Q | |
1367 | A memory reference where the exact address is in a single register | |
1368 | (`@samp{m}' is preferable for @code{asm} statements) | |
1369 | ||
1370 | @item R | |
1371 | An item in the constant pool | |
1372 | ||
1373 | @item S | |
1374 | A symbol in the text segment of the current file | |
1375 | @end table | |
1376 | ||
1377 | @item AMD 29000 family---@file{a29k.h} | |
1378 | @table @code | |
1379 | @item l | |
1380 | Local register 0 | |
1381 | ||
1382 | @item b | |
1383 | Byte Pointer (@samp{BP}) register | |
1384 | ||
1385 | @item q | |
1386 | @samp{Q} register | |
1387 | ||
1388 | @item h | |
1389 | Special purpose register | |
1390 | ||
1391 | @item A | |
1392 | First accumulator register | |
1393 | ||
1394 | @item a | |
1395 | Other accumulator register | |
1396 | ||
1397 | @item f | |
1398 | Floating point register | |
1399 | ||
1400 | @item I | |
1401 | Constant greater than 0, less than 0x100 | |
1402 | ||
1403 | @item J | |
1404 | Constant greater than 0, less than 0x10000 | |
1405 | ||
1406 | @item K | |
1407 | Constant whose high 24 bits are on (1) | |
1408 | ||
1409 | @item L | |
1e5f973d | 1410 | 16-bit constant whose high 8 bits are on (1) |
03dda8e3 RK |
1411 | |
1412 | @item M | |
1e5f973d | 1413 | 32-bit constant whose high 16 bits are on (1) |
03dda8e3 RK |
1414 | |
1415 | @item N | |
1e5f973d | 1416 | 32-bit negative constant that fits in 8 bits |
03dda8e3 RK |
1417 | |
1418 | @item O | |
1e5f973d | 1419 | The constant 0x80000000 or, on the 29050, any 32-bit constant |
03dda8e3 RK |
1420 | whose low 16 bits are 0. |
1421 | ||
1422 | @item P | |
1e5f973d | 1423 | 16-bit negative constant that fits in 8 bits |
03dda8e3 RK |
1424 | |
1425 | @item G | |
1426 | @itemx H | |
1427 | A floating point constant (in @code{asm} statements, use the machine | |
1428 | independent @samp{E} or @samp{F} instead) | |
1429 | @end table | |
1430 | ||
052a4b28 DC |
1431 | @item AVR family---@file{avr.h} |
1432 | @table @code | |
1433 | @item l | |
1434 | Registers from r0 to r15 | |
1435 | ||
1436 | @item a | |
1437 | Registers from r16 to r23 | |
1438 | ||
1439 | @item d | |
1440 | Registers from r16 to r31 | |
1441 | ||
1442 | @item w | |
3a69a7d5 | 1443 | Registers from r24 to r31. These registers can be used in @samp{adiw} command |
052a4b28 DC |
1444 | |
1445 | @item e | |
d7d9c429 | 1446 | Pointer register (r26--r31) |
052a4b28 DC |
1447 | |
1448 | @item b | |
d7d9c429 | 1449 | Base pointer register (r28--r31) |
052a4b28 | 1450 | |
3a69a7d5 MM |
1451 | @item q |
1452 | Stack pointer register (SPH:SPL) | |
1453 | ||
052a4b28 DC |
1454 | @item t |
1455 | Temporary register r0 | |
1456 | ||
1457 | @item x | |
1458 | Register pair X (r27:r26) | |
1459 | ||
1460 | @item y | |
1461 | Register pair Y (r29:r28) | |
1462 | ||
1463 | @item z | |
1464 | Register pair Z (r31:r30) | |
1465 | ||
1466 | @item I | |
630d3d5a | 1467 | Constant greater than @minus{}1, less than 64 |
052a4b28 DC |
1468 | |
1469 | @item J | |
630d3d5a | 1470 | Constant greater than @minus{}64, less than 1 |
052a4b28 DC |
1471 | |
1472 | @item K | |
1473 | Constant integer 2 | |
1474 | ||
1475 | @item L | |
1476 | Constant integer 0 | |
1477 | ||
1478 | @item M | |
1479 | Constant that fits in 8 bits | |
1480 | ||
1481 | @item N | |
630d3d5a | 1482 | Constant integer @minus{}1 |
052a4b28 DC |
1483 | |
1484 | @item O | |
3a69a7d5 | 1485 | Constant integer 8, 16, or 24 |
052a4b28 DC |
1486 | |
1487 | @item P | |
1488 | Constant integer 1 | |
1489 | ||
1490 | @item G | |
1491 | A floating point constant 0.0 | |
1492 | @end table | |
1493 | ||
03dda8e3 RK |
1494 | @item IBM RS6000---@file{rs6000.h} |
1495 | @table @code | |
1496 | @item b | |
1497 | Address base register | |
1498 | ||
1499 | @item f | |
1500 | Floating point register | |
1501 | ||
1502 | @item h | |
1503 | @samp{MQ}, @samp{CTR}, or @samp{LINK} register | |
1504 | ||
1505 | @item q | |
1506 | @samp{MQ} register | |
1507 | ||
1508 | @item c | |
1509 | @samp{CTR} register | |
1510 | ||
1511 | @item l | |
1512 | @samp{LINK} register | |
1513 | ||
1514 | @item x | |
1515 | @samp{CR} register (condition register) number 0 | |
1516 | ||
1517 | @item y | |
1518 | @samp{CR} register (condition register) | |
1519 | ||
8f685459 DE |
1520 | @item z |
1521 | @samp{FPMEM} stack memory for FPR-GPR transfers | |
1522 | ||
03dda8e3 | 1523 | @item I |
1e5f973d | 1524 | Signed 16-bit constant |
03dda8e3 RK |
1525 | |
1526 | @item J | |
ebb48a4d | 1527 | Unsigned 16-bit constant shifted left 16 bits (use @samp{L} instead for |
5f59ecb7 | 1528 | @code{SImode} constants) |
03dda8e3 RK |
1529 | |
1530 | @item K | |
1e5f973d | 1531 | Unsigned 16-bit constant |
03dda8e3 RK |
1532 | |
1533 | @item L | |
1e5f973d | 1534 | Signed 16-bit constant shifted left 16 bits |
03dda8e3 RK |
1535 | |
1536 | @item M | |
1537 | Constant larger than 31 | |
1538 | ||
1539 | @item N | |
1540 | Exact power of 2 | |
1541 | ||
1542 | @item O | |
1543 | Zero | |
1544 | ||
1545 | @item P | |
1e5f973d | 1546 | Constant whose negation is a signed 16-bit constant |
03dda8e3 RK |
1547 | |
1548 | @item G | |
1549 | Floating point constant that can be loaded into a register with one | |
1550 | instruction per word | |
1551 | ||
1552 | @item Q | |
1553 | Memory operand that is an offset from a register (@samp{m} is preferable | |
1554 | for @code{asm} statements) | |
1555 | ||
1556 | @item R | |
1557 | AIX TOC entry | |
1558 | ||
1559 | @item S | |
8f685459 | 1560 | Constant suitable as a 64-bit mask operand |
03dda8e3 | 1561 | |
5f59ecb7 DE |
1562 | @item T |
1563 | Constant suitable as a 32-bit mask operand | |
1564 | ||
03dda8e3 RK |
1565 | @item U |
1566 | System V Release 4 small data area reference | |
1567 | @end table | |
1568 | ||
1569 | @item Intel 386---@file{i386.h} | |
1570 | @table @code | |
1571 | @item q | |
0c56474e | 1572 | @samp{a}, @code{b}, @code{c}, or @code{d} register for the i386. |
1e5f973d | 1573 | For x86-64 it is equivalent to @samp{r} class. (for 8-bit instructions that |
0c56474e JH |
1574 | do not use upper halves) |
1575 | ||
1576 | @item Q | |
1e5f973d | 1577 | @samp{a}, @code{b}, @code{c}, or @code{d} register. (for 8-bit instructions, |
0c56474e JH |
1578 | that do use upper halves) |
1579 | ||
1580 | @item R | |
d7d9c429 | 1581 | Legacy register---equivalent to @code{r} class in i386 mode. |
1e5f973d | 1582 | (for non-8-bit registers used together with 8-bit upper halves in a single |
0c56474e | 1583 | instruction) |
03dda8e3 RK |
1584 | |
1585 | @item A | |
994682b9 AJ |
1586 | Specifies the @samp{a} or @samp{d} registers. This is primarily useful |
1587 | for 64-bit integer values (when in 32-bit mode) intended to be returned | |
1588 | with the @samp{d} register holding the most significant bits and the | |
1589 | @samp{a} register holding the least significant bits. | |
03dda8e3 RK |
1590 | |
1591 | @item f | |
1592 | Floating point register | |
1593 | ||
1594 | @item t | |
1595 | First (top of stack) floating point register | |
1596 | ||
1597 | @item u | |
1598 | Second floating point register | |
1599 | ||
1600 | @item a | |
1601 | @samp{a} register | |
1602 | ||
1603 | @item b | |
1604 | @samp{b} register | |
1605 | ||
1606 | @item c | |
1607 | @samp{c} register | |
1608 | ||
1609 | @item d | |
1610 | @samp{d} register | |
1611 | ||
1612 | @item D | |
1613 | @samp{di} register | |
1614 | ||
1615 | @item S | |
1616 | @samp{si} register | |
1617 | ||
994682b9 AJ |
1618 | @item x |
1619 | @samp{xmm} SSE register | |
1620 | ||
1621 | @item y | |
1622 | MMX register | |
1623 | ||
03dda8e3 | 1624 | @item I |
1e5f973d | 1625 | Constant in range 0 to 31 (for 32-bit shifts) |
03dda8e3 RK |
1626 | |
1627 | @item J | |
1e5f973d | 1628 | Constant in range 0 to 63 (for 64-bit shifts) |
03dda8e3 RK |
1629 | |
1630 | @item K | |
1631 | @samp{0xff} | |
1632 | ||
1633 | @item L | |
1634 | @samp{0xffff} | |
1635 | ||
1636 | @item M | |
1637 | 0, 1, 2, or 3 (shifts for @code{lea} instruction) | |
1638 | ||
1639 | @item N | |
1640 | Constant in range 0 to 255 (for @code{out} instruction) | |
1641 | ||
0c56474e | 1642 | @item Z |
aee96fe9 | 1643 | Constant in range 0 to @code{0xffffffff} or symbolic reference known to fit specified range. |
1e5f973d | 1644 | (for using immediates in zero extending 32-bit to 64-bit x86-64 instructions) |
0c56474e JH |
1645 | |
1646 | @item e | |
630d3d5a | 1647 | Constant in range @minus{}2147483648 to 2147483647 or symbolic reference known to fit specified range. |
1e5f973d | 1648 | (for using immediates in 64-bit x86-64 instructions) |
0c56474e | 1649 | |
03dda8e3 RK |
1650 | @item G |
1651 | Standard 80387 floating point constant | |
1652 | @end table | |
1653 | ||
1654 | @item Intel 960---@file{i960.h} | |
1655 | @table @code | |
1656 | @item f | |
1657 | Floating point register (@code{fp0} to @code{fp3}) | |
1658 | ||
1659 | @item l | |
1660 | Local register (@code{r0} to @code{r15}) | |
1661 | ||
1662 | @item b | |
1663 | Global register (@code{g0} to @code{g15}) | |
1664 | ||
1665 | @item d | |
1666 | Any local or global register | |
1667 | ||
1668 | @item I | |
1669 | Integers from 0 to 31 | |
1670 | ||
1671 | @item J | |
1672 | 0 | |
1673 | ||
1674 | @item K | |
630d3d5a | 1675 | Integers from @minus{}31 to 0 |
03dda8e3 RK |
1676 | |
1677 | @item G | |
1678 | Floating point 0 | |
1679 | ||
1680 | @item H | |
1681 | Floating point 1 | |
1682 | @end table | |
7a430e3b SC |
1683 | |
1684 | @item Intel IA-64---@file{ia64.h} | |
1685 | @table @code | |
1686 | @item a | |
1687 | General register @code{r0} to @code{r3} for @code{addl} instruction | |
1688 | ||
1689 | @item b | |
1690 | Branch register | |
1691 | ||
1692 | @item c | |
1693 | Predicate register (@samp{c} as in ``conditional'') | |
1694 | ||
1695 | @item d | |
1696 | Application register residing in M-unit | |
1697 | ||
1698 | @item e | |
1699 | Application register residing in I-unit | |
1700 | ||
1701 | @item f | |
1702 | Floating-point register | |
1703 | ||
1704 | @item m | |
1705 | Memory operand. | |
1706 | Remember that @samp{m} allows postincrement and postdecrement which | |
1707 | require printing with @samp{%Pn} on IA-64. | |
1708 | Use @samp{S} to disallow postincrement and postdecrement. | |
1709 | ||
1710 | @item G | |
1711 | Floating-point constant 0.0 or 1.0 | |
1712 | ||
1713 | @item I | |
1714 | 14-bit signed integer constant | |
1715 | ||
1716 | @item J | |
1717 | 22-bit signed integer constant | |
1718 | ||
1719 | @item K | |
1720 | 8-bit signed integer constant for logical instructions | |
1721 | ||
1722 | @item L | |
1723 | 8-bit adjusted signed integer constant for compare pseudo-ops | |
1724 | ||
1725 | @item M | |
1726 | 6-bit unsigned integer constant for shift counts | |
1727 | ||
1728 | @item N | |
1729 | 9-bit signed integer constant for load and store postincrements | |
1730 | ||
1731 | @item O | |
1732 | The constant zero | |
1733 | ||
1734 | @item P | |
1735 | 0 or -1 for @code{dep} instruction | |
1736 | ||
1737 | @item Q | |
1738 | Non-volatile memory for floating-point loads and stores | |
1739 | ||
1740 | @item R | |
1741 | Integer constant in the range 1 to 4 for @code{shladd} instruction | |
1742 | ||
1743 | @item S | |
1744 | Memory operand except postincrement and postdecrement | |
1745 | @end table | |
03dda8e3 RK |
1746 | |
1747 | @item MIPS---@file{mips.h} | |
1748 | @table @code | |
1749 | @item d | |
1750 | General-purpose integer register | |
1751 | ||
1752 | @item f | |
1753 | Floating-point register (if available) | |
1754 | ||
1755 | @item h | |
1756 | @samp{Hi} register | |
1757 | ||
1758 | @item l | |
1759 | @samp{Lo} register | |
1760 | ||
1761 | @item x | |
1762 | @samp{Hi} or @samp{Lo} register | |
1763 | ||
1764 | @item y | |
1765 | General-purpose integer register | |
1766 | ||
1767 | @item z | |
1768 | Floating-point status register | |
1769 | ||
1770 | @item I | |
1e5f973d | 1771 | Signed 16-bit constant (for arithmetic instructions) |
03dda8e3 RK |
1772 | |
1773 | @item J | |
1774 | Zero | |
1775 | ||
1776 | @item K | |
1777 | Zero-extended 16-bit constant (for logic instructions) | |
1778 | ||
1779 | @item L | |
1780 | Constant with low 16 bits zero (can be loaded with @code{lui}) | |
1781 | ||
1782 | @item M | |
1e5f973d | 1783 | 32-bit constant which requires two instructions to load (a constant |
03dda8e3 RK |
1784 | which is not @samp{I}, @samp{K}, or @samp{L}) |
1785 | ||
1786 | @item N | |
1e5f973d | 1787 | Negative 16-bit constant |
03dda8e3 RK |
1788 | |
1789 | @item O | |
1790 | Exact power of two | |
1791 | ||
1792 | @item P | |
1e5f973d | 1793 | Positive 16-bit constant |
03dda8e3 RK |
1794 | |
1795 | @item G | |
1796 | Floating point zero | |
1797 | ||
1798 | @item Q | |
1799 | Memory reference that can be loaded with more than one instruction | |
1800 | (@samp{m} is preferable for @code{asm} statements) | |
1801 | ||
1802 | @item R | |
1803 | Memory reference that can be loaded with one instruction | |
1804 | (@samp{m} is preferable for @code{asm} statements) | |
1805 | ||
1806 | @item S | |
1807 | Memory reference in external OSF/rose PIC format | |
1808 | (@samp{m} is preferable for @code{asm} statements) | |
1809 | @end table | |
1810 | ||
e3223ea2 DC |
1811 | @item IP2K---@file{ip2k.h} |
1812 | @table @code | |
1813 | @item a | |
1814 | @samp{DP} or @samp{IP} registers (general address) | |
1815 | ||
1816 | @item f | |
1817 | @samp{IP} register | |
1818 | ||
1819 | @item j | |
1820 | @samp{IPL} register | |
1821 | ||
1822 | @item k | |
1823 | @samp{IPH} register | |
1824 | ||
1825 | @item b | |
1826 | @samp{DP} register | |
1827 | ||
1828 | @item y | |
1829 | @samp{DPH} register | |
1830 | ||
1831 | @item z | |
1832 | @samp{DPL} register | |
1833 | ||
1834 | @item q | |
1835 | @samp{SP} register | |
1836 | ||
1837 | @item c | |
1838 | @samp{DP} or @samp{SP} registers (offsettable address) | |
1839 | ||
1840 | @item d | |
1841 | Non-pointer registers (not @samp{SP}, @samp{DP}, @samp{IP}) | |
1842 | ||
1843 | @item u | |
1844 | Non-SP registers (everything except @samp{SP}) | |
1845 | ||
1846 | @item R | |
1847 | Indirect thru @samp{IP} - Avoid this except for @code{QImode}, since we | |
1848 | can't access extra bytes | |
1849 | ||
1850 | @item S | |
1851 | Indirect thru @samp{SP} or @samp{DP} with short displacement (0..127) | |
1852 | ||
1853 | @item T | |
1854 | Data-section immediate value | |
1855 | ||
1856 | @item I | |
1857 | Integers from @minus{}255 to @minus{}1 | |
1858 | ||
1859 | @item J | |
1860 | Integers from 0 to 7---valid bit number in a register | |
1861 | ||
1862 | @item K | |
1863 | Integers from 0 to 127---valid displacement for addressing mode | |
1864 | ||
1865 | @item L | |
1866 | Integers from 1 to 127 | |
1867 | ||
1868 | @item M | |
1869 | Integer @minus{}1 | |
1870 | ||
1871 | @item N | |
1872 | Integer 1 | |
1873 | ||
1874 | @item O | |
1875 | Zero | |
1876 | ||
1877 | @item P | |
1878 | Integers from 0 to 255 | |
1879 | @end table | |
1880 | ||
03dda8e3 RK |
1881 | @item Motorola 680x0---@file{m68k.h} |
1882 | @table @code | |
1883 | @item a | |
1884 | Address register | |
1885 | ||
1886 | @item d | |
1887 | Data register | |
1888 | ||
1889 | @item f | |
1890 | 68881 floating-point register, if available | |
1891 | ||
1892 | @item x | |
1893 | Sun FPA (floating-point) register, if available | |
1894 | ||
1895 | @item y | |
1896 | First 16 Sun FPA registers, if available | |
1897 | ||
1898 | @item I | |
1899 | Integer in the range 1 to 8 | |
1900 | ||
1901 | @item J | |
1e5f973d | 1902 | 16-bit signed number |
03dda8e3 RK |
1903 | |
1904 | @item K | |
1905 | Signed number whose magnitude is greater than 0x80 | |
1906 | ||
1907 | @item L | |
630d3d5a | 1908 | Integer in the range @minus{}8 to @minus{}1 |
03dda8e3 RK |
1909 | |
1910 | @item M | |
1911 | Signed number whose magnitude is greater than 0x100 | |
1912 | ||
1913 | @item G | |
1914 | Floating point constant that is not a 68881 constant | |
1915 | ||
1916 | @item H | |
1917 | Floating point constant that can be used by Sun FPA | |
1918 | @end table | |
1919 | ||
2856c3e3 SC |
1920 | @item Motorola 68HC11 & 68HC12 families---@file{m68hc11.h} |
1921 | @table @code | |
1922 | @item a | |
1923 | Register 'a' | |
1924 | ||
1925 | @item b | |
1926 | Register 'b' | |
1927 | ||
1928 | @item d | |
1929 | Register 'd' | |
1930 | ||
1931 | @item q | |
1932 | An 8-bit register | |
1933 | ||
1934 | @item t | |
1935 | Temporary soft register _.tmp | |
1936 | ||
1937 | @item u | |
1938 | A soft register _.d1 to _.d31 | |
1939 | ||
1940 | @item w | |
1941 | Stack pointer register | |
1942 | ||
1943 | @item x | |
1944 | Register 'x' | |
1945 | ||
1946 | @item y | |
1947 | Register 'y' | |
1948 | ||
1949 | @item z | |
1950 | Pseudo register 'z' (replaced by 'x' or 'y' at the end) | |
1951 | ||
1952 | @item A | |
1953 | An address register: x, y or z | |
1954 | ||
1955 | @item B | |
1956 | An address register: x or y | |
1957 | ||
1958 | @item D | |
1959 | Register pair (x:d) to form a 32-bit value | |
1960 | ||
1961 | @item L | |
630d3d5a | 1962 | Constants in the range @minus{}65536 to 65535 |
2856c3e3 SC |
1963 | |
1964 | @item M | |
1965 | Constants whose 16-bit low part is zero | |
1966 | ||
1967 | @item N | |
630d3d5a | 1968 | Constant integer 1 or @minus{}1 |
2856c3e3 SC |
1969 | |
1970 | @item O | |
1971 | Constant integer 16 | |
1972 | ||
1973 | @item P | |
630d3d5a | 1974 | Constants in the range @minus{}8 to 2 |
2856c3e3 SC |
1975 | |
1976 | @end table | |
1977 | ||
03dda8e3 RK |
1978 | @need 1000 |
1979 | @item SPARC---@file{sparc.h} | |
1980 | @table @code | |
1981 | @item f | |
1e5f973d | 1982 | Floating-point register that can hold 32- or 64-bit values. |
03dda8e3 RK |
1983 | |
1984 | @item e | |
1e5f973d | 1985 | Floating-point register that can hold 64- or 128-bit values. |
03dda8e3 RK |
1986 | |
1987 | @item I | |
1e5f973d | 1988 | Signed 13-bit constant |
03dda8e3 RK |
1989 | |
1990 | @item J | |
1991 | Zero | |
1992 | ||
1993 | @item K | |
1e5f973d | 1994 | 32-bit constant with the low 12 bits clear (a constant that can be |
03dda8e3 RK |
1995 | loaded with the @code{sethi} instruction) |
1996 | ||
7d6040e8 AO |
1997 | @item L |
1998 | A constant in the range supported by @code{movcc} instructions | |
1999 | ||
2000 | @item M | |
2001 | A constant in the range supported by @code{movrcc} instructions | |
2002 | ||
2003 | @item N | |
2004 | Same as @samp{K}, except that it verifies that bits that are not in the | |
57694e40 | 2005 | lower 32-bit range are all zero. Must be used instead of @samp{K} for |
7d6040e8 AO |
2006 | modes wider than @code{SImode} |
2007 | ||
03dda8e3 RK |
2008 | @item G |
2009 | Floating-point zero | |
2010 | ||
2011 | @item H | |
1e5f973d | 2012 | Signed 13-bit constant, sign-extended to 32 or 64 bits |
03dda8e3 RK |
2013 | |
2014 | @item Q | |
62190128 DM |
2015 | Floating-point constant whose integral representation can |
2016 | be moved into an integer register using a single sethi | |
2017 | instruction | |
2018 | ||
2019 | @item R | |
2020 | Floating-point constant whose integral representation can | |
2021 | be moved into an integer register using a single mov | |
2022 | instruction | |
03dda8e3 RK |
2023 | |
2024 | @item S | |
62190128 DM |
2025 | Floating-point constant whose integral representation can |
2026 | be moved into an integer register using a high/lo_sum | |
2027 | instruction sequence | |
03dda8e3 RK |
2028 | |
2029 | @item T | |
2030 | Memory address aligned to an 8-byte boundary | |
2031 | ||
2032 | @item U | |
2033 | Even register | |
6ca30df6 | 2034 | |
7a31a340 DM |
2035 | @item W |
2036 | Memory address for @samp{e} constraint registers. | |
2037 | ||
6ca30df6 MH |
2038 | @end table |
2039 | ||
2040 | @item TMS320C3x/C4x---@file{c4x.h} | |
2041 | @table @code | |
2042 | @item a | |
2043 | Auxiliary (address) register (ar0-ar7) | |
2044 | ||
2045 | @item b | |
2046 | Stack pointer register (sp) | |
2047 | ||
2048 | @item c | |
1e5f973d | 2049 | Standard (32-bit) precision integer register |
6ca30df6 MH |
2050 | |
2051 | @item f | |
1e5f973d | 2052 | Extended (40-bit) precision register (r0-r11) |
6ca30df6 MH |
2053 | |
2054 | @item k | |
2055 | Block count register (bk) | |
2056 | ||
2057 | @item q | |
1e5f973d | 2058 | Extended (40-bit) precision low register (r0-r7) |
6ca30df6 MH |
2059 | |
2060 | @item t | |
1e5f973d | 2061 | Extended (40-bit) precision register (r0-r1) |
6ca30df6 MH |
2062 | |
2063 | @item u | |
1e5f973d | 2064 | Extended (40-bit) precision register (r2-r3) |
6ca30df6 MH |
2065 | |
2066 | @item v | |
2067 | Repeat count register (rc) | |
2068 | ||
2069 | @item x | |
2070 | Index register (ir0-ir1) | |
2071 | ||
2072 | @item y | |
2073 | Status (condition code) register (st) | |
2074 | ||
2075 | @item z | |
2076 | Data page register (dp) | |
2077 | ||
2078 | @item G | |
2079 | Floating-point zero | |
2080 | ||
2081 | @item H | |
1e5f973d | 2082 | Immediate 16-bit floating-point constant |
6ca30df6 MH |
2083 | |
2084 | @item I | |
1e5f973d | 2085 | Signed 16-bit constant |
6ca30df6 MH |
2086 | |
2087 | @item J | |
1e5f973d | 2088 | Signed 8-bit constant |
6ca30df6 MH |
2089 | |
2090 | @item K | |
1e5f973d | 2091 | Signed 5-bit constant |
6ca30df6 MH |
2092 | |
2093 | @item L | |
1e5f973d | 2094 | Unsigned 16-bit constant |
6ca30df6 MH |
2095 | |
2096 | @item M | |
1e5f973d | 2097 | Unsigned 8-bit constant |
6ca30df6 MH |
2098 | |
2099 | @item N | |
1e5f973d | 2100 | Ones complement of unsigned 16-bit constant |
6ca30df6 MH |
2101 | |
2102 | @item O | |
1e5f973d | 2103 | High 16-bit constant (32-bit constant with 16 LSBs zero) |
6ca30df6 MH |
2104 | |
2105 | @item Q | |
ebb48a4d | 2106 | Indirect memory reference with signed 8-bit or index register displacement |
6ca30df6 MH |
2107 | |
2108 | @item R | |
1e5f973d | 2109 | Indirect memory reference with unsigned 5-bit displacement |
6ca30df6 MH |
2110 | |
2111 | @item S | |
ebb48a4d | 2112 | Indirect memory reference with 1 bit or index register displacement |
6ca30df6 MH |
2113 | |
2114 | @item T | |
2115 | Direct memory reference | |
2116 | ||
2117 | @item U | |
2118 | Symbolic address | |
2119 | ||
03dda8e3 | 2120 | @end table |
91abf72d HP |
2121 | |
2122 | @item S/390 and zSeries---@file{s390.h} | |
2123 | @table @code | |
2124 | @item a | |
2125 | Address register (general purpose register except r0) | |
2126 | ||
2127 | @item d | |
2128 | Data register (arbitrary general purpose register) | |
2129 | ||
2130 | @item f | |
2131 | Floating-point register | |
2132 | ||
2133 | @item I | |
2134 | Unsigned 8-bit constant (0--255) | |
2135 | ||
2136 | @item J | |
2137 | Unsigned 12-bit constant (0--4095) | |
2138 | ||
2139 | @item K | |
2140 | Signed 16-bit constant (@minus{}32768--32767) | |
2141 | ||
2142 | @item L | |
2143 | Unsigned 16-bit constant (0--65535) | |
2144 | ||
2145 | @item Q | |
2146 | Memory reference without index register | |
2147 | ||
2148 | @item S | |
2149 | Symbolic constant suitable for use with the @code{larl} instruction | |
2150 | ||
2151 | @end table | |
2152 | ||
9f339dde GK |
2153 | @item Xstormy16---@file{stormy16.h} |
2154 | @table @code | |
2155 | @item a | |
2156 | Register r0. | |
2157 | ||
2158 | @item b | |
2159 | Register r1. | |
2160 | ||
2161 | @item c | |
2162 | Register r2. | |
2163 | ||
2164 | @item d | |
2165 | Register r8. | |
2166 | ||
2167 | @item e | |
2168 | Registers r0 through r7. | |
2169 | ||
2170 | @item t | |
2171 | Registers r0 and r1. | |
2172 | ||
2173 | @item y | |
2174 | The carry register. | |
2175 | ||
2176 | @item z | |
2177 | Registers r8 and r9. | |
2178 | ||
2179 | @item I | |
2180 | A constant between 0 and 3 inclusive. | |
2181 | ||
2182 | @item J | |
2183 | A constant that has exactly one bit set. | |
2184 | ||
2185 | @item K | |
2186 | A constant that has exactly one bit clear. | |
2187 | ||
2188 | @item L | |
2189 | A constant between 0 and 255 inclusive. | |
2190 | ||
2191 | @item M | |
69a0611f | 2192 | A constant between @minus{}255 and 0 inclusive. |
9f339dde GK |
2193 | |
2194 | @item N | |
69a0611f | 2195 | A constant between @minus{}3 and 0 inclusive. |
9f339dde GK |
2196 | |
2197 | @item O | |
2198 | A constant between 1 and 4 inclusive. | |
2199 | ||
2200 | @item P | |
69a0611f | 2201 | A constant between @minus{}4 and @minus{}1 inclusive. |
9f339dde GK |
2202 | |
2203 | @item Q | |
2204 | A memory reference that is a stack push. | |
2205 | ||
2206 | @item R | |
2207 | A memory reference that is a stack pop. | |
2208 | ||
2209 | @item S | |
2210 | A memory reference that refers to an constant address of known value. | |
2211 | ||
2212 | @item T | |
2213 | The register indicated by Rx (not implemented yet). | |
2214 | ||
2215 | @item U | |
2216 | A constant that is not between 2 and 15 inclusive. | |
2217 | ||
2218 | @end table | |
2219 | ||
03984308 BW |
2220 | @item Xtensa---@file{xtensa.h} |
2221 | @table @code | |
2222 | @item a | |
2223 | General-purpose 32-bit register | |
2224 | ||
2225 | @item b | |
2226 | One-bit boolean register | |
2227 | ||
2228 | @item A | |
2229 | MAC16 40-bit accumulator register | |
2230 | ||
2231 | @item I | |
2232 | Signed 12-bit integer constant, for use in MOVI instructions | |
2233 | ||
2234 | @item J | |
2235 | Signed 8-bit integer constant, for use in ADDI instructions | |
2236 | ||
2237 | @item K | |
2238 | Integer constant valid for BccI instructions | |
2239 | ||
2240 | @item L | |
2241 | Unsigned constant valid for BccUI instructions | |
2242 | ||
2243 | @end table | |
2244 | ||
03dda8e3 RK |
2245 | @end table |
2246 | ||
03dda8e3 RK |
2247 | @ifset INTERNALS |
2248 | @node Standard Names | |
2249 | @section Standard Pattern Names For Generation | |
2250 | @cindex standard pattern names | |
2251 | @cindex pattern names | |
2252 | @cindex names, pattern | |
2253 | ||
2254 | Here is a table of the instruction names that are meaningful in the RTL | |
2255 | generation pass of the compiler. Giving one of these names to an | |
2256 | instruction pattern tells the RTL generation pass that it can use the | |
556e0f21 | 2257 | pattern to accomplish a certain task. |
03dda8e3 RK |
2258 | |
2259 | @table @asis | |
2260 | @cindex @code{mov@var{m}} instruction pattern | |
2261 | @item @samp{mov@var{m}} | |
2262 | Here @var{m} stands for a two-letter machine mode name, in lower case. | |
2263 | This instruction pattern moves data with that machine mode from operand | |
2264 | 1 to operand 0. For example, @samp{movsi} moves full-word data. | |
2265 | ||
2266 | If operand 0 is a @code{subreg} with mode @var{m} of a register whose | |
2267 | own mode is wider than @var{m}, the effect of this instruction is | |
2268 | to store the specified value in the part of the register that corresponds | |
8feb4e28 JL |
2269 | to mode @var{m}. Bits outside of @var{m}, but which are within the |
2270 | same target word as the @code{subreg} are undefined. Bits which are | |
2271 | outside the target word are left unchanged. | |
03dda8e3 RK |
2272 | |
2273 | This class of patterns is special in several ways. First of all, each | |
65945ec1 HPN |
2274 | of these names up to and including full word size @emph{must} be defined, |
2275 | because there is no other way to copy a datum from one place to another. | |
2276 | If there are patterns accepting operands in larger modes, | |
2277 | @samp{mov@var{m}} must be defined for integer modes of those sizes. | |
03dda8e3 RK |
2278 | |
2279 | Second, these patterns are not used solely in the RTL generation pass. | |
2280 | Even the reload pass can generate move insns to copy values from stack | |
2281 | slots into temporary registers. When it does so, one of the operands is | |
2282 | a hard register and the other is an operand that can need to be reloaded | |
2283 | into a register. | |
2284 | ||
2285 | @findex force_reg | |
2286 | Therefore, when given such a pair of operands, the pattern must generate | |
2287 | RTL which needs no reloading and needs no temporary registers---no | |
2288 | registers other than the operands. For example, if you support the | |
2289 | pattern with a @code{define_expand}, then in such a case the | |
2290 | @code{define_expand} mustn't call @code{force_reg} or any other such | |
2291 | function which might generate new pseudo registers. | |
2292 | ||
2293 | This requirement exists even for subword modes on a RISC machine where | |
2294 | fetching those modes from memory normally requires several insns and | |
39ed8974 | 2295 | some temporary registers. |
03dda8e3 RK |
2296 | |
2297 | @findex change_address | |
2298 | During reload a memory reference with an invalid address may be passed | |
2299 | as an operand. Such an address will be replaced with a valid address | |
2300 | later in the reload pass. In this case, nothing may be done with the | |
2301 | address except to use it as it stands. If it is copied, it will not be | |
2302 | replaced with a valid address. No attempt should be made to make such | |
2303 | an address into a valid address and no routine (such as | |
2304 | @code{change_address}) that will do so may be called. Note that | |
2305 | @code{general_operand} will fail when applied to such an address. | |
2306 | ||
2307 | @findex reload_in_progress | |
2308 | The global variable @code{reload_in_progress} (which must be explicitly | |
2309 | declared if required) can be used to determine whether such special | |
2310 | handling is required. | |
2311 | ||
2312 | The variety of operands that have reloads depends on the rest of the | |
2313 | machine description, but typically on a RISC machine these can only be | |
2314 | pseudo registers that did not get hard registers, while on other | |
2315 | machines explicit memory references will get optional reloads. | |
2316 | ||
2317 | If a scratch register is required to move an object to or from memory, | |
f1db3576 JL |
2318 | it can be allocated using @code{gen_reg_rtx} prior to life analysis. |
2319 | ||
9c34dbbf ZW |
2320 | If there are cases which need scratch registers during or after reload, |
2321 | you must define @code{SECONDARY_INPUT_RELOAD_CLASS} and/or | |
03dda8e3 RK |
2322 | @code{SECONDARY_OUTPUT_RELOAD_CLASS} to detect them, and provide |
2323 | patterns @samp{reload_in@var{m}} or @samp{reload_out@var{m}} to handle | |
2324 | them. @xref{Register Classes}. | |
2325 | ||
f1db3576 JL |
2326 | @findex no_new_pseudos |
2327 | The global variable @code{no_new_pseudos} can be used to determine if it | |
2328 | is unsafe to create new pseudo registers. If this variable is nonzero, then | |
2329 | it is unsafe to call @code{gen_reg_rtx} to allocate a new pseudo. | |
2330 | ||
956d6950 | 2331 | The constraints on a @samp{mov@var{m}} must permit moving any hard |
03dda8e3 RK |
2332 | register to any other hard register provided that |
2333 | @code{HARD_REGNO_MODE_OK} permits mode @var{m} in both registers and | |
2334 | @code{REGISTER_MOVE_COST} applied to their classes returns a value of 2. | |
2335 | ||
956d6950 | 2336 | It is obligatory to support floating point @samp{mov@var{m}} |
03dda8e3 RK |
2337 | instructions into and out of any registers that can hold fixed point |
2338 | values, because unions and structures (which have modes @code{SImode} or | |
2339 | @code{DImode}) can be in those registers and they may have floating | |
2340 | point members. | |
2341 | ||
956d6950 | 2342 | There may also be a need to support fixed point @samp{mov@var{m}} |
03dda8e3 RK |
2343 | instructions in and out of floating point registers. Unfortunately, I |
2344 | have forgotten why this was so, and I don't know whether it is still | |
2345 | true. If @code{HARD_REGNO_MODE_OK} rejects fixed point values in | |
2346 | floating point registers, then the constraints of the fixed point | |
956d6950 | 2347 | @samp{mov@var{m}} instructions must be designed to avoid ever trying to |
03dda8e3 RK |
2348 | reload into a floating point register. |
2349 | ||
2350 | @cindex @code{reload_in} instruction pattern | |
2351 | @cindex @code{reload_out} instruction pattern | |
2352 | @item @samp{reload_in@var{m}} | |
2353 | @itemx @samp{reload_out@var{m}} | |
2354 | Like @samp{mov@var{m}}, but used when a scratch register is required to | |
2355 | move between operand 0 and operand 1. Operand 2 describes the scratch | |
2356 | register. See the discussion of the @code{SECONDARY_RELOAD_CLASS} | |
2357 | macro in @pxref{Register Classes}. | |
2358 | ||
d989f648 | 2359 | There are special restrictions on the form of the @code{match_operand}s |
f282ffb3 | 2360 | used in these patterns. First, only the predicate for the reload |
560dbedd RH |
2361 | operand is examined, i.e., @code{reload_in} examines operand 1, but not |
2362 | the predicates for operand 0 or 2. Second, there may be only one | |
d989f648 RH |
2363 | alternative in the constraints. Third, only a single register class |
2364 | letter may be used for the constraint; subsequent constraint letters | |
2365 | are ignored. As a special exception, an empty constraint string | |
2366 | matches the @code{ALL_REGS} register class. This may relieve ports | |
2367 | of the burden of defining an @code{ALL_REGS} constraint letter just | |
2368 | for these patterns. | |
2369 | ||
03dda8e3 RK |
2370 | @cindex @code{movstrict@var{m}} instruction pattern |
2371 | @item @samp{movstrict@var{m}} | |
2372 | Like @samp{mov@var{m}} except that if operand 0 is a @code{subreg} | |
2373 | with mode @var{m} of a register whose natural mode is wider, | |
2374 | the @samp{movstrict@var{m}} instruction is guaranteed not to alter | |
2375 | any of the register except the part which belongs to mode @var{m}. | |
2376 | ||
2377 | @cindex @code{load_multiple} instruction pattern | |
2378 | @item @samp{load_multiple} | |
2379 | Load several consecutive memory locations into consecutive registers. | |
2380 | Operand 0 is the first of the consecutive registers, operand 1 | |
2381 | is the first memory location, and operand 2 is a constant: the | |
2382 | number of consecutive registers. | |
2383 | ||
2384 | Define this only if the target machine really has such an instruction; | |
2385 | do not define this if the most efficient way of loading consecutive | |
2386 | registers from memory is to do them one at a time. | |
2387 | ||
2388 | On some machines, there are restrictions as to which consecutive | |
2389 | registers can be stored into memory, such as particular starting or | |
2390 | ending register numbers or only a range of valid counts. For those | |
2391 | machines, use a @code{define_expand} (@pxref{Expander Definitions}) | |
2392 | and make the pattern fail if the restrictions are not met. | |
2393 | ||
2394 | Write the generated insn as a @code{parallel} with elements being a | |
2395 | @code{set} of one register from the appropriate memory location (you may | |
2396 | also need @code{use} or @code{clobber} elements). Use a | |
2397 | @code{match_parallel} (@pxref{RTL Template}) to recognize the insn. See | |
2398 | @file{a29k.md} and @file{rs6000.md} for examples of the use of this insn | |
2399 | pattern. | |
2400 | ||
2401 | @cindex @samp{store_multiple} instruction pattern | |
2402 | @item @samp{store_multiple} | |
2403 | Similar to @samp{load_multiple}, but store several consecutive registers | |
2404 | into consecutive memory locations. Operand 0 is the first of the | |
2405 | consecutive memory locations, operand 1 is the first register, and | |
2406 | operand 2 is a constant: the number of consecutive registers. | |
2407 | ||
38f4324c JH |
2408 | @cindex @code{push@var{m}} instruction pattern |
2409 | @item @samp{push@var{m}} | |
2410 | Output an push instruction. Operand 0 is value to push. Used only when | |
2411 | @code{PUSH_ROUNDING} is defined. For historical reason, this pattern may be | |
2412 | missing and in such case an @code{mov} expander is used instead, with a | |
6e9aac46 | 2413 | @code{MEM} expression forming the push operation. The @code{mov} expander |
38f4324c JH |
2414 | method is deprecated. |
2415 | ||
03dda8e3 RK |
2416 | @cindex @code{add@var{m}3} instruction pattern |
2417 | @item @samp{add@var{m}3} | |
2418 | Add operand 2 and operand 1, storing the result in operand 0. All operands | |
2419 | must have mode @var{m}. This can be used even on two-address machines, by | |
2420 | means of constraints requiring operands 1 and 0 to be the same location. | |
2421 | ||
2422 | @cindex @code{sub@var{m}3} instruction pattern | |
2423 | @cindex @code{mul@var{m}3} instruction pattern | |
2424 | @cindex @code{div@var{m}3} instruction pattern | |
2425 | @cindex @code{udiv@var{m}3} instruction pattern | |
2426 | @cindex @code{mod@var{m}3} instruction pattern | |
2427 | @cindex @code{umod@var{m}3} instruction pattern | |
2428 | @cindex @code{smin@var{m}3} instruction pattern | |
2429 | @cindex @code{smax@var{m}3} instruction pattern | |
2430 | @cindex @code{umin@var{m}3} instruction pattern | |
2431 | @cindex @code{umax@var{m}3} instruction pattern | |
2432 | @cindex @code{and@var{m}3} instruction pattern | |
2433 | @cindex @code{ior@var{m}3} instruction pattern | |
2434 | @cindex @code{xor@var{m}3} instruction pattern | |
2435 | @item @samp{sub@var{m}3}, @samp{mul@var{m}3} | |
2436 | @itemx @samp{div@var{m}3}, @samp{udiv@var{m}3}, @samp{mod@var{m}3}, @samp{umod@var{m}3} | |
2437 | @itemx @samp{smin@var{m}3}, @samp{smax@var{m}3}, @samp{umin@var{m}3}, @samp{umax@var{m}3} | |
2438 | @itemx @samp{and@var{m}3}, @samp{ior@var{m}3}, @samp{xor@var{m}3} | |
2439 | Similar, for other arithmetic operations. | |
b71b019a JH |
2440 | @cindex @code{min@var{m}3} instruction pattern |
2441 | @cindex @code{max@var{m}3} instruction pattern | |
2442 | @itemx @samp{min@var{m}3}, @samp{max@var{m}3} | |
2443 | Floating point min and max operations. If both operands are zeros, | |
2444 | or if either operand is NaN, then it is unspecified which of the two | |
2445 | operands is returned as the result. | |
2446 | ||
03dda8e3 RK |
2447 | |
2448 | @cindex @code{mulhisi3} instruction pattern | |
2449 | @item @samp{mulhisi3} | |
2450 | Multiply operands 1 and 2, which have mode @code{HImode}, and store | |
2451 | a @code{SImode} product in operand 0. | |
2452 | ||
2453 | @cindex @code{mulqihi3} instruction pattern | |
2454 | @cindex @code{mulsidi3} instruction pattern | |
2455 | @item @samp{mulqihi3}, @samp{mulsidi3} | |
2456 | Similar widening-multiplication instructions of other widths. | |
2457 | ||
2458 | @cindex @code{umulqihi3} instruction pattern | |
2459 | @cindex @code{umulhisi3} instruction pattern | |
2460 | @cindex @code{umulsidi3} instruction pattern | |
2461 | @item @samp{umulqihi3}, @samp{umulhisi3}, @samp{umulsidi3} | |
2462 | Similar widening-multiplication instructions that do unsigned | |
2463 | multiplication. | |
2464 | ||
2465 | @cindex @code{smul@var{m}3_highpart} instruction pattern | |
759c58af | 2466 | @item @samp{smul@var{m}3_highpart} |
03dda8e3 RK |
2467 | Perform a signed multiplication of operands 1 and 2, which have mode |
2468 | @var{m}, and store the most significant half of the product in operand 0. | |
2469 | The least significant half of the product is discarded. | |
2470 | ||
2471 | @cindex @code{umul@var{m}3_highpart} instruction pattern | |
2472 | @item @samp{umul@var{m}3_highpart} | |
2473 | Similar, but the multiplication is unsigned. | |
2474 | ||
2475 | @cindex @code{divmod@var{m}4} instruction pattern | |
2476 | @item @samp{divmod@var{m}4} | |
2477 | Signed division that produces both a quotient and a remainder. | |
2478 | Operand 1 is divided by operand 2 to produce a quotient stored | |
2479 | in operand 0 and a remainder stored in operand 3. | |
2480 | ||
2481 | For machines with an instruction that produces both a quotient and a | |
2482 | remainder, provide a pattern for @samp{divmod@var{m}4} but do not | |
2483 | provide patterns for @samp{div@var{m}3} and @samp{mod@var{m}3}. This | |
2484 | allows optimization in the relatively common case when both the quotient | |
2485 | and remainder are computed. | |
2486 | ||
2487 | If an instruction that just produces a quotient or just a remainder | |
2488 | exists and is more efficient than the instruction that produces both, | |
2489 | write the output routine of @samp{divmod@var{m}4} to call | |
2490 | @code{find_reg_note} and look for a @code{REG_UNUSED} note on the | |
2491 | quotient or remainder and generate the appropriate instruction. | |
2492 | ||
2493 | @cindex @code{udivmod@var{m}4} instruction pattern | |
2494 | @item @samp{udivmod@var{m}4} | |
2495 | Similar, but does unsigned division. | |
2496 | ||
2497 | @cindex @code{ashl@var{m}3} instruction pattern | |
2498 | @item @samp{ashl@var{m}3} | |
2499 | Arithmetic-shift operand 1 left by a number of bits specified by operand | |
2500 | 2, and store the result in operand 0. Here @var{m} is the mode of | |
2501 | operand 0 and operand 1; operand 2's mode is specified by the | |
2502 | instruction pattern, and the compiler will convert the operand to that | |
2503 | mode before generating the instruction. | |
2504 | ||
2505 | @cindex @code{ashr@var{m}3} instruction pattern | |
2506 | @cindex @code{lshr@var{m}3} instruction pattern | |
2507 | @cindex @code{rotl@var{m}3} instruction pattern | |
2508 | @cindex @code{rotr@var{m}3} instruction pattern | |
2509 | @item @samp{ashr@var{m}3}, @samp{lshr@var{m}3}, @samp{rotl@var{m}3}, @samp{rotr@var{m}3} | |
2510 | Other shift and rotate instructions, analogous to the | |
2511 | @code{ashl@var{m}3} instructions. | |
2512 | ||
2513 | @cindex @code{neg@var{m}2} instruction pattern | |
2514 | @item @samp{neg@var{m}2} | |
2515 | Negate operand 1 and store the result in operand 0. | |
2516 | ||
2517 | @cindex @code{abs@var{m}2} instruction pattern | |
2518 | @item @samp{abs@var{m}2} | |
2519 | Store the absolute value of operand 1 into operand 0. | |
2520 | ||
2521 | @cindex @code{sqrt@var{m}2} instruction pattern | |
2522 | @item @samp{sqrt@var{m}2} | |
2523 | Store the square root of operand 1 into operand 0. | |
2524 | ||
2525 | The @code{sqrt} built-in function of C always uses the mode which | |
2526 | corresponds to the C data type @code{double}. | |
2527 | ||
2528 | @cindex @code{ffs@var{m}2} instruction pattern | |
2529 | @item @samp{ffs@var{m}2} | |
2530 | Store into operand 0 one plus the index of the least significant 1-bit | |
2531 | of operand 1. If operand 1 is zero, store zero. @var{m} is the mode | |
2532 | of operand 0; operand 1's mode is specified by the instruction | |
2533 | pattern, and the compiler will convert the operand to that mode before | |
2534 | generating the instruction. | |
2535 | ||
2536 | The @code{ffs} built-in function of C always uses the mode which | |
2537 | corresponds to the C data type @code{int}. | |
2538 | ||
2539 | @cindex @code{one_cmpl@var{m}2} instruction pattern | |
2540 | @item @samp{one_cmpl@var{m}2} | |
2541 | Store the bitwise-complement of operand 1 into operand 0. | |
2542 | ||
2543 | @cindex @code{cmp@var{m}} instruction pattern | |
2544 | @item @samp{cmp@var{m}} | |
2545 | Compare operand 0 and operand 1, and set the condition codes. | |
2546 | The RTL pattern should look like this: | |
2547 | ||
2548 | @smallexample | |
2549 | (set (cc0) (compare (match_operand:@var{m} 0 @dots{}) | |
2550 | (match_operand:@var{m} 1 @dots{}))) | |
2551 | @end smallexample | |
2552 | ||
2553 | @cindex @code{tst@var{m}} instruction pattern | |
2554 | @item @samp{tst@var{m}} | |
2555 | Compare operand 0 against zero, and set the condition codes. | |
2556 | The RTL pattern should look like this: | |
2557 | ||
2558 | @smallexample | |
2559 | (set (cc0) (match_operand:@var{m} 0 @dots{})) | |
2560 | @end smallexample | |
2561 | ||
2562 | @samp{tst@var{m}} patterns should not be defined for machines that do | |
2563 | not use @code{(cc0)}. Doing so would confuse the optimizer since it | |
2564 | would no longer be clear which @code{set} operations were comparisons. | |
2565 | The @samp{cmp@var{m}} patterns should be used instead. | |
2566 | ||
2567 | @cindex @code{movstr@var{m}} instruction pattern | |
2568 | @item @samp{movstr@var{m}} | |
2569 | Block move instruction. The addresses of the destination and source | |
2570 | strings are the first two operands, and both are in mode @code{Pmode}. | |
e5e809f4 | 2571 | |
03dda8e3 | 2572 | The number of bytes to move is the third operand, in mode @var{m}. |
e5e809f4 JL |
2573 | Usually, you specify @code{word_mode} for @var{m}. However, if you can |
2574 | generate better code knowing the range of valid lengths is smaller than | |
2575 | those representable in a full word, you should provide a pattern with a | |
2576 | mode corresponding to the range of values you can handle efficiently | |
2577 | (e.g., @code{QImode} for values in the range 0--127; note we avoid numbers | |
2578 | that appear negative) and also a pattern with @code{word_mode}. | |
03dda8e3 RK |
2579 | |
2580 | The fourth operand is the known shared alignment of the source and | |
2581 | destination, in the form of a @code{const_int} rtx. Thus, if the | |
2582 | compiler knows that both source and destination are word-aligned, | |
2583 | it may provide the value 4 for this operand. | |
2584 | ||
8c01d9b6 | 2585 | Descriptions of multiple @code{movstr@var{m}} patterns can only be |
4693911f | 2586 | beneficial if the patterns for smaller modes have fewer restrictions |
8c01d9b6 JL |
2587 | on their first, second and fourth operands. Note that the mode @var{m} |
2588 | in @code{movstr@var{m}} does not impose any restriction on the mode of | |
2589 | individually moved data units in the block. | |
2590 | ||
03dda8e3 RK |
2591 | These patterns need not give special consideration to the possibility |
2592 | that the source and destination strings might overlap. | |
2593 | ||
2594 | @cindex @code{clrstr@var{m}} instruction pattern | |
2595 | @item @samp{clrstr@var{m}} | |
2596 | Block clear instruction. The addresses of the destination string is the | |
2597 | first operand, in mode @code{Pmode}. The number of bytes to clear is | |
e5e809f4 JL |
2598 | the second operand, in mode @var{m}. See @samp{movstr@var{m}} for |
2599 | a discussion of the choice of mode. | |
03dda8e3 RK |
2600 | |
2601 | The third operand is the known alignment of the destination, in the form | |
2602 | of a @code{const_int} rtx. Thus, if the compiler knows that the | |
2603 | destination is word-aligned, it may provide the value 4 for this | |
2604 | operand. | |
2605 | ||
8c01d9b6 JL |
2606 | The use for multiple @code{clrstr@var{m}} is as for @code{movstr@var{m}}. |
2607 | ||
03dda8e3 RK |
2608 | @cindex @code{cmpstr@var{m}} instruction pattern |
2609 | @item @samp{cmpstr@var{m}} | |
2610 | Block compare instruction, with five operands. Operand 0 is the output; | |
2611 | it has mode @var{m}. The remaining four operands are like the operands | |
2612 | of @samp{movstr@var{m}}. The two memory blocks specified are compared | |
2613 | byte by byte in lexicographic order. The effect of the instruction is | |
2614 | to store a value in operand 0 whose sign indicates the result of the | |
2615 | comparison. | |
2616 | ||
2617 | @cindex @code{strlen@var{m}} instruction pattern | |
2618 | @item @samp{strlen@var{m}} | |
2619 | Compute the length of a string, with three operands. | |
2620 | Operand 0 is the result (of mode @var{m}), operand 1 is | |
2621 | a @code{mem} referring to the first character of the string, | |
2622 | operand 2 is the character to search for (normally zero), | |
2623 | and operand 3 is a constant describing the known alignment | |
2624 | of the beginning of the string. | |
2625 | ||
2626 | @cindex @code{float@var{mn}2} instruction pattern | |
2627 | @item @samp{float@var{m}@var{n}2} | |
2628 | Convert signed integer operand 1 (valid for fixed point mode @var{m}) to | |
2629 | floating point mode @var{n} and store in operand 0 (which has mode | |
2630 | @var{n}). | |
2631 | ||
2632 | @cindex @code{floatuns@var{mn}2} instruction pattern | |
2633 | @item @samp{floatuns@var{m}@var{n}2} | |
2634 | Convert unsigned integer operand 1 (valid for fixed point mode @var{m}) | |
2635 | to floating point mode @var{n} and store in operand 0 (which has mode | |
2636 | @var{n}). | |
2637 | ||
2638 | @cindex @code{fix@var{mn}2} instruction pattern | |
2639 | @item @samp{fix@var{m}@var{n}2} | |
2640 | Convert operand 1 (valid for floating point mode @var{m}) to fixed | |
2641 | point mode @var{n} as a signed number and store in operand 0 (which | |
2642 | has mode @var{n}). This instruction's result is defined only when | |
2643 | the value of operand 1 is an integer. | |
2644 | ||
2645 | @cindex @code{fixuns@var{mn}2} instruction pattern | |
2646 | @item @samp{fixuns@var{m}@var{n}2} | |
2647 | Convert operand 1 (valid for floating point mode @var{m}) to fixed | |
2648 | point mode @var{n} as an unsigned number and store in operand 0 (which | |
2649 | has mode @var{n}). This instruction's result is defined only when the | |
2650 | value of operand 1 is an integer. | |
2651 | ||
2652 | @cindex @code{ftrunc@var{m}2} instruction pattern | |
2653 | @item @samp{ftrunc@var{m}2} | |
2654 | Convert operand 1 (valid for floating point mode @var{m}) to an | |
2655 | integer value, still represented in floating point mode @var{m}, and | |
2656 | store it in operand 0 (valid for floating point mode @var{m}). | |
2657 | ||
2658 | @cindex @code{fix_trunc@var{mn}2} instruction pattern | |
2659 | @item @samp{fix_trunc@var{m}@var{n}2} | |
2660 | Like @samp{fix@var{m}@var{n}2} but works for any floating point value | |
2661 | of mode @var{m} by converting the value to an integer. | |
2662 | ||
2663 | @cindex @code{fixuns_trunc@var{mn}2} instruction pattern | |
2664 | @item @samp{fixuns_trunc@var{m}@var{n}2} | |
2665 | Like @samp{fixuns@var{m}@var{n}2} but works for any floating point | |
2666 | value of mode @var{m} by converting the value to an integer. | |
2667 | ||
2668 | @cindex @code{trunc@var{mn}2} instruction pattern | |
2669 | @item @samp{trunc@var{m}@var{n}2} | |
2670 | Truncate operand 1 (valid for mode @var{m}) to mode @var{n} and | |
2671 | store in operand 0 (which has mode @var{n}). Both modes must be fixed | |
2672 | point or both floating point. | |
2673 | ||
2674 | @cindex @code{extend@var{mn}2} instruction pattern | |
2675 | @item @samp{extend@var{m}@var{n}2} | |
2676 | Sign-extend operand 1 (valid for mode @var{m}) to mode @var{n} and | |
2677 | store in operand 0 (which has mode @var{n}). Both modes must be fixed | |
2678 | point or both floating point. | |
2679 | ||
2680 | @cindex @code{zero_extend@var{mn}2} instruction pattern | |
2681 | @item @samp{zero_extend@var{m}@var{n}2} | |
2682 | Zero-extend operand 1 (valid for mode @var{m}) to mode @var{n} and | |
2683 | store in operand 0 (which has mode @var{n}). Both modes must be fixed | |
2684 | point. | |
2685 | ||
2686 | @cindex @code{extv} instruction pattern | |
2687 | @item @samp{extv} | |
c771326b | 2688 | Extract a bit-field from operand 1 (a register or memory operand), where |
03dda8e3 RK |
2689 | operand 2 specifies the width in bits and operand 3 the starting bit, |
2690 | and store it in operand 0. Operand 0 must have mode @code{word_mode}. | |
2691 | Operand 1 may have mode @code{byte_mode} or @code{word_mode}; often | |
2692 | @code{word_mode} is allowed only for registers. Operands 2 and 3 must | |
2693 | be valid for @code{word_mode}. | |
2694 | ||
2695 | The RTL generation pass generates this instruction only with constants | |
2696 | for operands 2 and 3. | |
2697 | ||
2698 | The bit-field value is sign-extended to a full word integer | |
2699 | before it is stored in operand 0. | |
2700 | ||
2701 | @cindex @code{extzv} instruction pattern | |
2702 | @item @samp{extzv} | |
2703 | Like @samp{extv} except that the bit-field value is zero-extended. | |
2704 | ||
2705 | @cindex @code{insv} instruction pattern | |
2706 | @item @samp{insv} | |
c771326b JM |
2707 | Store operand 3 (which must be valid for @code{word_mode}) into a |
2708 | bit-field in operand 0, where operand 1 specifies the width in bits and | |
03dda8e3 RK |
2709 | operand 2 the starting bit. Operand 0 may have mode @code{byte_mode} or |
2710 | @code{word_mode}; often @code{word_mode} is allowed only for registers. | |
2711 | Operands 1 and 2 must be valid for @code{word_mode}. | |
2712 | ||
2713 | The RTL generation pass generates this instruction only with constants | |
2714 | for operands 1 and 2. | |
2715 | ||
2716 | @cindex @code{mov@var{mode}cc} instruction pattern | |
2717 | @item @samp{mov@var{mode}cc} | |
2718 | Conditionally move operand 2 or operand 3 into operand 0 according to the | |
2719 | comparison in operand 1. If the comparison is true, operand 2 is moved | |
2720 | into operand 0, otherwise operand 3 is moved. | |
2721 | ||
2722 | The mode of the operands being compared need not be the same as the operands | |
2723 | being moved. Some machines, sparc64 for example, have instructions that | |
2724 | conditionally move an integer value based on the floating point condition | |
2725 | codes and vice versa. | |
2726 | ||
2727 | If the machine does not have conditional move instructions, do not | |
2728 | define these patterns. | |
2729 | ||
2730 | @cindex @code{s@var{cond}} instruction pattern | |
2731 | @item @samp{s@var{cond}} | |
2732 | Store zero or nonzero in the operand according to the condition codes. | |
2733 | Value stored is nonzero iff the condition @var{cond} is true. | |
2734 | @var{cond} is the name of a comparison operation expression code, such | |
2735 | as @code{eq}, @code{lt} or @code{leu}. | |
2736 | ||
2737 | You specify the mode that the operand must have when you write the | |
2738 | @code{match_operand} expression. The compiler automatically sees | |
2739 | which mode you have used and supplies an operand of that mode. | |
2740 | ||
2741 | The value stored for a true condition must have 1 as its low bit, or | |
2742 | else must be negative. Otherwise the instruction is not suitable and | |
2743 | you should omit it from the machine description. You describe to the | |
2744 | compiler exactly which value is stored by defining the macro | |
2745 | @code{STORE_FLAG_VALUE} (@pxref{Misc}). If a description cannot be | |
2746 | found that can be used for all the @samp{s@var{cond}} patterns, you | |
2747 | should omit those operations from the machine description. | |
2748 | ||
2749 | These operations may fail, but should do so only in relatively | |
2750 | uncommon cases; if they would fail for common cases involving | |
2751 | integer comparisons, it is best to omit these patterns. | |
2752 | ||
2753 | If these operations are omitted, the compiler will usually generate code | |
2754 | that copies the constant one to the target and branches around an | |
2755 | assignment of zero to the target. If this code is more efficient than | |
2756 | the potential instructions used for the @samp{s@var{cond}} pattern | |
2757 | followed by those required to convert the result into a 1 or a zero in | |
2758 | @code{SImode}, you should omit the @samp{s@var{cond}} operations from | |
2759 | the machine description. | |
2760 | ||
2761 | @cindex @code{b@var{cond}} instruction pattern | |
2762 | @item @samp{b@var{cond}} | |
2763 | Conditional branch instruction. Operand 0 is a @code{label_ref} that | |
2764 | refers to the label to jump to. Jump if the condition codes meet | |
2765 | condition @var{cond}. | |
2766 | ||
2767 | Some machines do not follow the model assumed here where a comparison | |
2768 | instruction is followed by a conditional branch instruction. In that | |
2769 | case, the @samp{cmp@var{m}} (and @samp{tst@var{m}}) patterns should | |
2770 | simply store the operands away and generate all the required insns in a | |
2771 | @code{define_expand} (@pxref{Expander Definitions}) for the conditional | |
2772 | branch operations. All calls to expand @samp{b@var{cond}} patterns are | |
2773 | immediately preceded by calls to expand either a @samp{cmp@var{m}} | |
2774 | pattern or a @samp{tst@var{m}} pattern. | |
2775 | ||
2776 | Machines that use a pseudo register for the condition code value, or | |
2777 | where the mode used for the comparison depends on the condition being | |
0b433de6 | 2778 | tested, should also use the above mechanism. @xref{Jump Patterns}. |
03dda8e3 RK |
2779 | |
2780 | The above discussion also applies to the @samp{mov@var{mode}cc} and | |
2781 | @samp{s@var{cond}} patterns. | |
2782 | ||
d26eedb6 HPN |
2783 | @cindex @code{jump} instruction pattern |
2784 | @item @samp{jump} | |
2785 | A jump inside a function; an unconditional branch. Operand 0 is the | |
2786 | @code{label_ref} of the label to jump to. This pattern name is mandatory | |
2787 | on all machines. | |
2788 | ||
03dda8e3 RK |
2789 | @cindex @code{call} instruction pattern |
2790 | @item @samp{call} | |
2791 | Subroutine call instruction returning no value. Operand 0 is the | |
2792 | function to call; operand 1 is the number of bytes of arguments pushed | |
f5963e61 JL |
2793 | as a @code{const_int}; operand 2 is the number of registers used as |
2794 | operands. | |
03dda8e3 RK |
2795 | |
2796 | On most machines, operand 2 is not actually stored into the RTL | |
2797 | pattern. It is supplied for the sake of some RISC machines which need | |
2798 | to put this information into the assembler code; they can put it in | |
2799 | the RTL instead of operand 1. | |
2800 | ||
2801 | Operand 0 should be a @code{mem} RTX whose address is the address of the | |
2802 | function. Note, however, that this address can be a @code{symbol_ref} | |
2803 | expression even if it would not be a legitimate memory address on the | |
2804 | target machine. If it is also not a valid argument for a call | |
2805 | instruction, the pattern for this operation should be a | |
2806 | @code{define_expand} (@pxref{Expander Definitions}) that places the | |
2807 | address into a register and uses that register in the call instruction. | |
2808 | ||
2809 | @cindex @code{call_value} instruction pattern | |
2810 | @item @samp{call_value} | |
2811 | Subroutine call instruction returning a value. Operand 0 is the hard | |
2812 | register in which the value is returned. There are three more | |
2813 | operands, the same as the three operands of the @samp{call} | |
2814 | instruction (but with numbers increased by one). | |
2815 | ||
2816 | Subroutines that return @code{BLKmode} objects use the @samp{call} | |
2817 | insn. | |
2818 | ||
2819 | @cindex @code{call_pop} instruction pattern | |
2820 | @cindex @code{call_value_pop} instruction pattern | |
2821 | @item @samp{call_pop}, @samp{call_value_pop} | |
2822 | Similar to @samp{call} and @samp{call_value}, except used if defined and | |
df2a54e9 | 2823 | if @code{RETURN_POPS_ARGS} is nonzero. They should emit a @code{parallel} |
03dda8e3 RK |
2824 | that contains both the function call and a @code{set} to indicate the |
2825 | adjustment made to the frame pointer. | |
2826 | ||
df2a54e9 | 2827 | For machines where @code{RETURN_POPS_ARGS} can be nonzero, the use of these |
03dda8e3 RK |
2828 | patterns increases the number of functions for which the frame pointer |
2829 | can be eliminated, if desired. | |
2830 | ||
2831 | @cindex @code{untyped_call} instruction pattern | |
2832 | @item @samp{untyped_call} | |
2833 | Subroutine call instruction returning a value of any type. Operand 0 is | |
2834 | the function to call; operand 1 is a memory location where the result of | |
2835 | calling the function is to be stored; operand 2 is a @code{parallel} | |
2836 | expression where each element is a @code{set} expression that indicates | |
2837 | the saving of a function return value into the result block. | |
2838 | ||
2839 | This instruction pattern should be defined to support | |
2840 | @code{__builtin_apply} on machines where special instructions are needed | |
2841 | to call a subroutine with arbitrary arguments or to save the value | |
2842 | returned. This instruction pattern is required on machines that have | |
e979f9e8 JM |
2843 | multiple registers that can hold a return value |
2844 | (i.e.@: @code{FUNCTION_VALUE_REGNO_P} is true for more than one register). | |
03dda8e3 RK |
2845 | |
2846 | @cindex @code{return} instruction pattern | |
2847 | @item @samp{return} | |
2848 | Subroutine return instruction. This instruction pattern name should be | |
2849 | defined only if a single instruction can do all the work of returning | |
2850 | from a function. | |
2851 | ||
2852 | Like the @samp{mov@var{m}} patterns, this pattern is also used after the | |
2853 | RTL generation phase. In this case it is to support machines where | |
2854 | multiple instructions are usually needed to return from a function, but | |
2855 | some class of functions only requires one instruction to implement a | |
2856 | return. Normally, the applicable functions are those which do not need | |
2857 | to save any registers or allocate stack space. | |
2858 | ||
2859 | @findex reload_completed | |
2860 | @findex leaf_function_p | |
2861 | For such machines, the condition specified in this pattern should only | |
df2a54e9 | 2862 | be true when @code{reload_completed} is nonzero and the function's |
03dda8e3 RK |
2863 | epilogue would only be a single instruction. For machines with register |
2864 | windows, the routine @code{leaf_function_p} may be used to determine if | |
2865 | a register window push is required. | |
2866 | ||
2867 | Machines that have conditional return instructions should define patterns | |
2868 | such as | |
2869 | ||
2870 | @smallexample | |
2871 | (define_insn "" | |
2872 | [(set (pc) | |
2873 | (if_then_else (match_operator | |
2874 | 0 "comparison_operator" | |
2875 | [(cc0) (const_int 0)]) | |
2876 | (return) | |
2877 | (pc)))] | |
2878 | "@var{condition}" | |
2879 | "@dots{}") | |
2880 | @end smallexample | |
2881 | ||
2882 | where @var{condition} would normally be the same condition specified on the | |
2883 | named @samp{return} pattern. | |
2884 | ||
2885 | @cindex @code{untyped_return} instruction pattern | |
2886 | @item @samp{untyped_return} | |
2887 | Untyped subroutine return instruction. This instruction pattern should | |
2888 | be defined to support @code{__builtin_return} on machines where special | |
2889 | instructions are needed to return a value of any type. | |
2890 | ||
2891 | Operand 0 is a memory location where the result of calling a function | |
2892 | with @code{__builtin_apply} is stored; operand 1 is a @code{parallel} | |
2893 | expression where each element is a @code{set} expression that indicates | |
2894 | the restoring of a function return value from the result block. | |
2895 | ||
2896 | @cindex @code{nop} instruction pattern | |
2897 | @item @samp{nop} | |
2898 | No-op instruction. This instruction pattern name should always be defined | |
2899 | to output a no-op in assembler code. @code{(const_int 0)} will do as an | |
2900 | RTL pattern. | |
2901 | ||
2902 | @cindex @code{indirect_jump} instruction pattern | |
2903 | @item @samp{indirect_jump} | |
2904 | An instruction to jump to an address which is operand zero. | |
2905 | This pattern name is mandatory on all machines. | |
2906 | ||
2907 | @cindex @code{casesi} instruction pattern | |
2908 | @item @samp{casesi} | |
2909 | Instruction to jump through a dispatch table, including bounds checking. | |
2910 | This instruction takes five operands: | |
2911 | ||
2912 | @enumerate | |
2913 | @item | |
2914 | The index to dispatch on, which has mode @code{SImode}. | |
2915 | ||
2916 | @item | |
2917 | The lower bound for indices in the table, an integer constant. | |
2918 | ||
2919 | @item | |
2920 | The total range of indices in the table---the largest index | |
2921 | minus the smallest one (both inclusive). | |
2922 | ||
2923 | @item | |
2924 | A label that precedes the table itself. | |
2925 | ||
2926 | @item | |
2927 | A label to jump to if the index has a value outside the bounds. | |
2928 | (If the machine-description macro @code{CASE_DROPS_THROUGH} is defined, | |
2929 | then an out-of-bounds index drops through to the code following | |
2930 | the jump table instead of jumping to this label. In that case, | |
2931 | this label is not actually used by the @samp{casesi} instruction, | |
2932 | but it is always provided as an operand.) | |
2933 | @end enumerate | |
2934 | ||
2935 | The table is a @code{addr_vec} or @code{addr_diff_vec} inside of a | |
2936 | @code{jump_insn}. The number of elements in the table is one plus the | |
2937 | difference between the upper bound and the lower bound. | |
2938 | ||
2939 | @cindex @code{tablejump} instruction pattern | |
2940 | @item @samp{tablejump} | |
2941 | Instruction to jump to a variable address. This is a low-level | |
2942 | capability which can be used to implement a dispatch table when there | |
2943 | is no @samp{casesi} pattern. | |
2944 | ||
2945 | This pattern requires two operands: the address or offset, and a label | |
2946 | which should immediately precede the jump table. If the macro | |
f1f5f142 JL |
2947 | @code{CASE_VECTOR_PC_RELATIVE} evaluates to a nonzero value then the first |
2948 | operand is an offset which counts from the address of the table; otherwise, | |
2949 | it is an absolute address to jump to. In either case, the first operand has | |
03dda8e3 RK |
2950 | mode @code{Pmode}. |
2951 | ||
2952 | The @samp{tablejump} insn is always the last insn before the jump | |
2953 | table it uses. Its assembler code normally has no need to use the | |
2954 | second operand, but you should incorporate it in the RTL pattern so | |
2955 | that the jump optimizer will not delete the table as unreachable code. | |
2956 | ||
6e4fcc95 MH |
2957 | |
2958 | @cindex @code{decrement_and_branch_until_zero} instruction pattern | |
2959 | @item @samp{decrement_and_branch_until_zero} | |
2960 | Conditional branch instruction that decrements a register and | |
df2a54e9 | 2961 | jumps if the register is nonzero. Operand 0 is the register to |
6e4fcc95 | 2962 | decrement and test; operand 1 is the label to jump to if the |
df2a54e9 | 2963 | register is nonzero. @xref{Looping Patterns}. |
6e4fcc95 MH |
2964 | |
2965 | This optional instruction pattern is only used by the combiner, | |
2966 | typically for loops reversed by the loop optimizer when strength | |
2967 | reduction is enabled. | |
2968 | ||
2969 | @cindex @code{doloop_end} instruction pattern | |
2970 | @item @samp{doloop_end} | |
2971 | Conditional branch instruction that decrements a register and jumps if | |
df2a54e9 | 2972 | the register is nonzero. This instruction takes five operands: Operand |
6e4fcc95 MH |
2973 | 0 is the register to decrement and test; operand 1 is the number of loop |
2974 | iterations as a @code{const_int} or @code{const0_rtx} if this cannot be | |
2975 | determined until run-time; operand 2 is the actual or estimated maximum | |
2976 | number of iterations as a @code{const_int}; operand 3 is the number of | |
2977 | enclosed loops as a @code{const_int} (an innermost loop has a value of | |
df2a54e9 | 2978 | 1); operand 4 is the label to jump to if the register is nonzero. |
5c25e11d | 2979 | @xref{Looping Patterns}. |
6e4fcc95 MH |
2980 | |
2981 | This optional instruction pattern should be defined for machines with | |
2982 | low-overhead looping instructions as the loop optimizer will try to | |
2983 | modify suitable loops to utilize it. If nested low-overhead looping is | |
2984 | not supported, use a @code{define_expand} (@pxref{Expander Definitions}) | |
2985 | and make the pattern fail if operand 3 is not @code{const1_rtx}. | |
2986 | Similarly, if the actual or estimated maximum number of iterations is | |
2987 | too large for this instruction, make it fail. | |
2988 | ||
2989 | @cindex @code{doloop_begin} instruction pattern | |
2990 | @item @samp{doloop_begin} | |
2991 | Companion instruction to @code{doloop_end} required for machines that | |
c21cd8b1 JM |
2992 | need to perform some initialization, such as loading special registers |
2993 | used by a low-overhead looping instruction. If initialization insns do | |
6e4fcc95 MH |
2994 | not always need to be emitted, use a @code{define_expand} |
2995 | (@pxref{Expander Definitions}) and make it fail. | |
2996 | ||
2997 | ||
03dda8e3 RK |
2998 | @cindex @code{canonicalize_funcptr_for_compare} instruction pattern |
2999 | @item @samp{canonicalize_funcptr_for_compare} | |
3000 | Canonicalize the function pointer in operand 1 and store the result | |
3001 | into operand 0. | |
3002 | ||
3003 | Operand 0 is always a @code{reg} and has mode @code{Pmode}; operand 1 | |
3004 | may be a @code{reg}, @code{mem}, @code{symbol_ref}, @code{const_int}, etc | |
3005 | and also has mode @code{Pmode}. | |
3006 | ||
3007 | Canonicalization of a function pointer usually involves computing | |
3008 | the address of the function which would be called if the function | |
3009 | pointer were used in an indirect call. | |
3010 | ||
3011 | Only define this pattern if function pointers on the target machine | |
3012 | can have different values but still call the same function when | |
3013 | used in an indirect call. | |
3014 | ||
3015 | @cindex @code{save_stack_block} instruction pattern | |
3016 | @cindex @code{save_stack_function} instruction pattern | |
3017 | @cindex @code{save_stack_nonlocal} instruction pattern | |
3018 | @cindex @code{restore_stack_block} instruction pattern | |
3019 | @cindex @code{restore_stack_function} instruction pattern | |
3020 | @cindex @code{restore_stack_nonlocal} instruction pattern | |
3021 | @item @samp{save_stack_block} | |
3022 | @itemx @samp{save_stack_function} | |
3023 | @itemx @samp{save_stack_nonlocal} | |
3024 | @itemx @samp{restore_stack_block} | |
3025 | @itemx @samp{restore_stack_function} | |
3026 | @itemx @samp{restore_stack_nonlocal} | |
3027 | Most machines save and restore the stack pointer by copying it to or | |
3028 | from an object of mode @code{Pmode}. Do not define these patterns on | |
3029 | such machines. | |
3030 | ||
3031 | Some machines require special handling for stack pointer saves and | |
3032 | restores. On those machines, define the patterns corresponding to the | |
3033 | non-standard cases by using a @code{define_expand} (@pxref{Expander | |
3034 | Definitions}) that produces the required insns. The three types of | |
3035 | saves and restores are: | |
3036 | ||
3037 | @enumerate | |
3038 | @item | |
3039 | @samp{save_stack_block} saves the stack pointer at the start of a block | |
3040 | that allocates a variable-sized object, and @samp{restore_stack_block} | |
3041 | restores the stack pointer when the block is exited. | |
3042 | ||
3043 | @item | |
3044 | @samp{save_stack_function} and @samp{restore_stack_function} do a | |
3045 | similar job for the outermost block of a function and are used when the | |
3046 | function allocates variable-sized objects or calls @code{alloca}. Only | |
3047 | the epilogue uses the restored stack pointer, allowing a simpler save or | |
3048 | restore sequence on some machines. | |
3049 | ||
3050 | @item | |
3051 | @samp{save_stack_nonlocal} is used in functions that contain labels | |
3052 | branched to by nested functions. It saves the stack pointer in such a | |
3053 | way that the inner function can use @samp{restore_stack_nonlocal} to | |
3054 | restore the stack pointer. The compiler generates code to restore the | |
3055 | frame and argument pointer registers, but some machines require saving | |
3056 | and restoring additional data such as register window information or | |
3057 | stack backchains. Place insns in these patterns to save and restore any | |
3058 | such required data. | |
3059 | @end enumerate | |
3060 | ||
3061 | When saving the stack pointer, operand 0 is the save area and operand 1 | |
73c8090f DE |
3062 | is the stack pointer. The mode used to allocate the save area defaults |
3063 | to @code{Pmode} but you can override that choice by defining the | |
7e390c9d | 3064 | @code{STACK_SAVEAREA_MODE} macro (@pxref{Storage Layout}). You must |
73c8090f DE |
3065 | specify an integral mode, or @code{VOIDmode} if no save area is needed |
3066 | for a particular type of save (either because no save is needed or | |
3067 | because a machine-specific save area can be used). Operand 0 is the | |
3068 | stack pointer and operand 1 is the save area for restore operations. If | |
3069 | @samp{save_stack_block} is defined, operand 0 must not be | |
3070 | @code{VOIDmode} since these saves can be arbitrarily nested. | |
03dda8e3 RK |
3071 | |
3072 | A save area is a @code{mem} that is at a constant offset from | |
3073 | @code{virtual_stack_vars_rtx} when the stack pointer is saved for use by | |
3074 | nonlocal gotos and a @code{reg} in the other two cases. | |
3075 | ||
3076 | @cindex @code{allocate_stack} instruction pattern | |
3077 | @item @samp{allocate_stack} | |
72938a4c | 3078 | Subtract (or add if @code{STACK_GROWS_DOWNWARD} is undefined) operand 1 from |
03dda8e3 RK |
3079 | the stack pointer to create space for dynamically allocated data. |
3080 | ||
72938a4c MM |
3081 | Store the resultant pointer to this space into operand 0. If you |
3082 | are allocating space from the main stack, do this by emitting a | |
3083 | move insn to copy @code{virtual_stack_dynamic_rtx} to operand 0. | |
3084 | If you are allocating the space elsewhere, generate code to copy the | |
3085 | location of the space to operand 0. In the latter case, you must | |
956d6950 | 3086 | ensure this space gets freed when the corresponding space on the main |
72938a4c MM |
3087 | stack is free. |
3088 | ||
03dda8e3 RK |
3089 | Do not define this pattern if all that must be done is the subtraction. |
3090 | Some machines require other operations such as stack probes or | |
3091 | maintaining the back chain. Define this pattern to emit those | |
3092 | operations in addition to updating the stack pointer. | |
3093 | ||
3094 | @cindex @code{probe} instruction pattern | |
3095 | @item @samp{probe} | |
3096 | Some machines require instructions to be executed after space is | |
3097 | allocated from the stack, for example to generate a reference at | |
3098 | the bottom of the stack. | |
3099 | ||
3100 | If you need to emit instructions before the stack has been adjusted, | |
3101 | put them into the @samp{allocate_stack} pattern. Otherwise, define | |
3102 | this pattern to emit the required instructions. | |
3103 | ||
3104 | No operands are provided. | |
3105 | ||
861bb6c1 JL |
3106 | @cindex @code{check_stack} instruction pattern |
3107 | @item @samp{check_stack} | |
3108 | If stack checking cannot be done on your system by probing the stack with | |
3109 | a load or store instruction (@pxref{Stack Checking}), define this pattern | |
3110 | to perform the needed check and signaling an error if the stack | |
3111 | has overflowed. The single operand is the location in the stack furthest | |
3112 | from the current stack pointer that you need to validate. Normally, | |
3113 | on machines where this pattern is needed, you would obtain the stack | |
3114 | limit from a global or thread-specific variable or register. | |
3115 | ||
03dda8e3 RK |
3116 | @cindex @code{nonlocal_goto} instruction pattern |
3117 | @item @samp{nonlocal_goto} | |
3118 | Emit code to generate a non-local goto, e.g., a jump from one function | |
3119 | to a label in an outer function. This pattern has four arguments, | |
3120 | each representing a value to be used in the jump. The first | |
45bb86fd | 3121 | argument is to be loaded into the frame pointer, the second is |
03dda8e3 RK |
3122 | the address to branch to (code to dispatch to the actual label), |
3123 | the third is the address of a location where the stack is saved, | |
3124 | and the last is the address of the label, to be placed in the | |
3125 | location for the incoming static chain. | |
3126 | ||
f0523f02 | 3127 | On most machines you need not define this pattern, since GCC will |
03dda8e3 RK |
3128 | already generate the correct code, which is to load the frame pointer |
3129 | and static chain, restore the stack (using the | |
3130 | @samp{restore_stack_nonlocal} pattern, if defined), and jump indirectly | |
3131 | to the dispatcher. You need only define this pattern if this code will | |
3132 | not work on your machine. | |
3133 | ||
3134 | @cindex @code{nonlocal_goto_receiver} instruction pattern | |
3135 | @item @samp{nonlocal_goto_receiver} | |
3136 | This pattern, if defined, contains code needed at the target of a | |
161d7b59 | 3137 | nonlocal goto after the code already generated by GCC@. You will not |
03dda8e3 RK |
3138 | normally need to define this pattern. A typical reason why you might |
3139 | need this pattern is if some value, such as a pointer to a global table, | |
c30ddbc9 | 3140 | must be restored when the frame pointer is restored. Note that a nonlocal |
89bcce1b | 3141 | goto only occurs within a unit-of-translation, so a global table pointer |
c30ddbc9 RH |
3142 | that is shared by all functions of a given module need not be restored. |
3143 | There are no arguments. | |
861bb6c1 JL |
3144 | |
3145 | @cindex @code{exception_receiver} instruction pattern | |
3146 | @item @samp{exception_receiver} | |
3147 | This pattern, if defined, contains code needed at the site of an | |
3148 | exception handler that isn't needed at the site of a nonlocal goto. You | |
3149 | will not normally need to define this pattern. A typical reason why you | |
3150 | might need this pattern is if some value, such as a pointer to a global | |
3151 | table, must be restored after control flow is branched to the handler of | |
3152 | an exception. There are no arguments. | |
c85f7c16 | 3153 | |
c30ddbc9 RH |
3154 | @cindex @code{builtin_setjmp_setup} instruction pattern |
3155 | @item @samp{builtin_setjmp_setup} | |
3156 | This pattern, if defined, contains additional code needed to initialize | |
3157 | the @code{jmp_buf}. You will not normally need to define this pattern. | |
3158 | A typical reason why you might need this pattern is if some value, such | |
3159 | as a pointer to a global table, must be restored. Though it is | |
3160 | preferred that the pointer value be recalculated if possible (given the | |
3161 | address of a label for instance). The single argument is a pointer to | |
3162 | the @code{jmp_buf}. Note that the buffer is five words long and that | |
3163 | the first three are normally used by the generic mechanism. | |
3164 | ||
c85f7c16 JL |
3165 | @cindex @code{builtin_setjmp_receiver} instruction pattern |
3166 | @item @samp{builtin_setjmp_receiver} | |
3167 | This pattern, if defined, contains code needed at the site of an | |
c771326b | 3168 | built-in setjmp that isn't needed at the site of a nonlocal goto. You |
c85f7c16 JL |
3169 | will not normally need to define this pattern. A typical reason why you |
3170 | might need this pattern is if some value, such as a pointer to a global | |
c30ddbc9 RH |
3171 | table, must be restored. It takes one argument, which is the label |
3172 | to which builtin_longjmp transfered control; this pattern may be emitted | |
3173 | at a small offset from that label. | |
3174 | ||
3175 | @cindex @code{builtin_longjmp} instruction pattern | |
3176 | @item @samp{builtin_longjmp} | |
3177 | This pattern, if defined, performs the entire action of the longjmp. | |
3178 | You will not normally need to define this pattern unless you also define | |
3179 | @code{builtin_setjmp_setup}. The single argument is a pointer to the | |
3180 | @code{jmp_buf}. | |
f69864aa | 3181 | |
52a11cbf RH |
3182 | @cindex @code{eh_return} instruction pattern |
3183 | @item @samp{eh_return} | |
f69864aa | 3184 | This pattern, if defined, affects the way @code{__builtin_eh_return}, |
52a11cbf RH |
3185 | and thence the call frame exception handling library routines, are |
3186 | built. It is intended to handle non-trivial actions needed along | |
3187 | the abnormal return path. | |
3188 | ||
3189 | The pattern takes two arguments. The first is an offset to be applied | |
3190 | to the stack pointer. It will have been copied to some appropriate | |
3191 | location (typically @code{EH_RETURN_STACKADJ_RTX}) which will survive | |
ebb48a4d | 3192 | until after reload to when the normal epilogue is generated. |
52a11cbf | 3193 | The second argument is the address of the exception handler to which |
f69864aa | 3194 | the function should return. This will normally need to copied by the |
52a11cbf | 3195 | pattern to some special register or memory location. |
f69864aa | 3196 | |
52a11cbf | 3197 | This pattern only needs to be defined if call frame exception handling |
9c34dbbf ZW |
3198 | is to be used, and simple moves involving @code{EH_RETURN_STACKADJ_RTX} |
3199 | and @code{EH_RETURN_HANDLER_RTX} are not sufficient. | |
0b433de6 JL |
3200 | |
3201 | @cindex @code{prologue} instruction pattern | |
17b53c33 | 3202 | @anchor{prologue instruction pattern} |
0b433de6 JL |
3203 | @item @samp{prologue} |
3204 | This pattern, if defined, emits RTL for entry to a function. The function | |
b192711e | 3205 | entry is responsible for setting up the stack frame, initializing the frame |
0b433de6 JL |
3206 | pointer register, saving callee saved registers, etc. |
3207 | ||
3208 | Using a prologue pattern is generally preferred over defining | |
17b53c33 | 3209 | @code{TARGET_ASM_FUNCTION_PROLOGUE} to emit assembly code for the prologue. |
0b433de6 JL |
3210 | |
3211 | The @code{prologue} pattern is particularly useful for targets which perform | |
3212 | instruction scheduling. | |
3213 | ||
3214 | @cindex @code{epilogue} instruction pattern | |
17b53c33 | 3215 | @anchor{epilogue instruction pattern} |
0b433de6 | 3216 | @item @samp{epilogue} |
396ad517 | 3217 | This pattern emits RTL for exit from a function. The function |
b192711e | 3218 | exit is responsible for deallocating the stack frame, restoring callee saved |
0b433de6 JL |
3219 | registers and emitting the return instruction. |
3220 | ||
3221 | Using an epilogue pattern is generally preferred over defining | |
17b53c33 | 3222 | @code{TARGET_ASM_FUNCTION_EPILOGUE} to emit assembly code for the epilogue. |
0b433de6 JL |
3223 | |
3224 | The @code{epilogue} pattern is particularly useful for targets which perform | |
3225 | instruction scheduling or which have delay slots for their return instruction. | |
3226 | ||
3227 | @cindex @code{sibcall_epilogue} instruction pattern | |
3228 | @item @samp{sibcall_epilogue} | |
3229 | This pattern, if defined, emits RTL for exit from a function without the final | |
3230 | branch back to the calling function. This pattern will be emitted before any | |
3231 | sibling call (aka tail call) sites. | |
3232 | ||
3233 | The @code{sibcall_epilogue} pattern must not clobber any arguments used for | |
3234 | parameter passing or any stack slots for arguments passed to the current | |
ebb48a4d | 3235 | function. |
a157febd GK |
3236 | |
3237 | @cindex @code{trap} instruction pattern | |
3238 | @item @samp{trap} | |
3239 | This pattern, if defined, signals an error, typically by causing some | |
3240 | kind of signal to be raised. Among other places, it is used by the Java | |
c771326b | 3241 | front end to signal `invalid array index' exceptions. |
a157febd GK |
3242 | |
3243 | @cindex @code{conditional_trap} instruction pattern | |
3244 | @item @samp{conditional_trap} | |
3245 | Conditional trap instruction. Operand 0 is a piece of RTL which | |
3246 | performs a comparison. Operand 1 is the trap code, an integer. | |
3247 | ||
3248 | A typical @code{conditional_trap} pattern looks like | |
3249 | ||
3250 | @smallexample | |
3251 | (define_insn "conditional_trap" | |
ebb48a4d | 3252 | [(trap_if (match_operator 0 "trap_operator" |
a157febd GK |
3253 | [(cc0) (const_int 0)]) |
3254 | (match_operand 1 "const_int_operand" "i"))] | |
3255 | "" | |
3256 | "@dots{}") | |
3257 | @end smallexample | |
3258 | ||
e83d297b JJ |
3259 | @cindex @code{prefetch} instruction pattern |
3260 | @item @samp{prefetch} | |
3261 | ||
3262 | This pattern, if defined, emits code for a non-faulting data prefetch | |
3263 | instruction. Operand 0 is the address of the memory to prefetch. Operand 1 | |
3264 | is a constant 1 if the prefetch is preparing for a write to the memory | |
3265 | address, or a constant 0 otherwise. Operand 2 is the expected degree of | |
3266 | temporal locality of the data and is a value between 0 and 3, inclusive; 0 | |
3267 | means that the data has no temporal locality, so it need not be left in the | |
3268 | cache after the access; 3 means that the data has a high degree of temporal | |
3269 | locality and should be left in all levels of cache possible; 1 and 2 mean, | |
3270 | respectively, a low or moderate degree of temporal locality. | |
3271 | ||
3272 | Targets that do not support write prefetches or locality hints can ignore | |
3273 | the values of operands 1 and 2. | |
3274 | ||
03dda8e3 RK |
3275 | @end table |
3276 | ||
3277 | @node Pattern Ordering | |
3278 | @section When the Order of Patterns Matters | |
3279 | @cindex Pattern Ordering | |
3280 | @cindex Ordering of Patterns | |
3281 | ||
3282 | Sometimes an insn can match more than one instruction pattern. Then the | |
3283 | pattern that appears first in the machine description is the one used. | |
3284 | Therefore, more specific patterns (patterns that will match fewer things) | |
3285 | and faster instructions (those that will produce better code when they | |
3286 | do match) should usually go first in the description. | |
3287 | ||
3288 | In some cases the effect of ordering the patterns can be used to hide | |
3289 | a pattern when it is not valid. For example, the 68000 has an | |
3290 | instruction for converting a fullword to floating point and another | |
3291 | for converting a byte to floating point. An instruction converting | |
3292 | an integer to floating point could match either one. We put the | |
3293 | pattern to convert the fullword first to make sure that one will | |
3294 | be used rather than the other. (Otherwise a large integer might | |
3295 | be generated as a single-byte immediate quantity, which would not work.) | |
3296 | Instead of using this pattern ordering it would be possible to make the | |
3297 | pattern for convert-a-byte smart enough to deal properly with any | |
3298 | constant value. | |
3299 | ||
3300 | @node Dependent Patterns | |
3301 | @section Interdependence of Patterns | |
3302 | @cindex Dependent Patterns | |
3303 | @cindex Interdependence of Patterns | |
3304 | ||
3305 | Every machine description must have a named pattern for each of the | |
3306 | conditional branch names @samp{b@var{cond}}. The recognition template | |
3307 | must always have the form | |
3308 | ||
3309 | @example | |
3310 | (set (pc) | |
3311 | (if_then_else (@var{cond} (cc0) (const_int 0)) | |
3312 | (label_ref (match_operand 0 "" "")) | |
3313 | (pc))) | |
3314 | @end example | |
3315 | ||
3316 | @noindent | |
3317 | In addition, every machine description must have an anonymous pattern | |
3318 | for each of the possible reverse-conditional branches. Their templates | |
3319 | look like | |
3320 | ||
3321 | @example | |
3322 | (set (pc) | |
3323 | (if_then_else (@var{cond} (cc0) (const_int 0)) | |
3324 | (pc) | |
3325 | (label_ref (match_operand 0 "" "")))) | |
3326 | @end example | |
3327 | ||
3328 | @noindent | |
3329 | They are necessary because jump optimization can turn direct-conditional | |
3330 | branches into reverse-conditional branches. | |
3331 | ||
3332 | It is often convenient to use the @code{match_operator} construct to | |
3333 | reduce the number of patterns that must be specified for branches. For | |
3334 | example, | |
3335 | ||
3336 | @example | |
3337 | (define_insn "" | |
3338 | [(set (pc) | |
3339 | (if_then_else (match_operator 0 "comparison_operator" | |
3340 | [(cc0) (const_int 0)]) | |
3341 | (pc) | |
3342 | (label_ref (match_operand 1 "" ""))))] | |
3343 | "@var{condition}" | |
3344 | "@dots{}") | |
3345 | @end example | |
3346 | ||
3347 | In some cases machines support instructions identical except for the | |
3348 | machine mode of one or more operands. For example, there may be | |
3349 | ``sign-extend halfword'' and ``sign-extend byte'' instructions whose | |
3350 | patterns are | |
3351 | ||
3352 | @example | |
3353 | (set (match_operand:SI 0 @dots{}) | |
3354 | (extend:SI (match_operand:HI 1 @dots{}))) | |
3355 | ||
3356 | (set (match_operand:SI 0 @dots{}) | |
3357 | (extend:SI (match_operand:QI 1 @dots{}))) | |
3358 | @end example | |
3359 | ||
3360 | @noindent | |
3361 | Constant integers do not specify a machine mode, so an instruction to | |
3362 | extend a constant value could match either pattern. The pattern it | |
3363 | actually will match is the one that appears first in the file. For correct | |
3364 | results, this must be the one for the widest possible mode (@code{HImode}, | |
3365 | here). If the pattern matches the @code{QImode} instruction, the results | |
3366 | will be incorrect if the constant value does not actually fit that mode. | |
3367 | ||
3368 | Such instructions to extend constants are rarely generated because they are | |
3369 | optimized away, but they do occasionally happen in nonoptimized | |
3370 | compilations. | |
3371 | ||
3372 | If a constraint in a pattern allows a constant, the reload pass may | |
3373 | replace a register with a constant permitted by the constraint in some | |
3374 | cases. Similarly for memory references. Because of this substitution, | |
3375 | you should not provide separate patterns for increment and decrement | |
3376 | instructions. Instead, they should be generated from the same pattern | |
3377 | that supports register-register add insns by examining the operands and | |
3378 | generating the appropriate machine instruction. | |
3379 | ||
3380 | @node Jump Patterns | |
3381 | @section Defining Jump Instruction Patterns | |
3382 | @cindex jump instruction patterns | |
3383 | @cindex defining jump instruction patterns | |
3384 | ||
f0523f02 | 3385 | For most machines, GCC assumes that the machine has a condition code. |
03dda8e3 RK |
3386 | A comparison insn sets the condition code, recording the results of both |
3387 | signed and unsigned comparison of the given operands. A separate branch | |
3388 | insn tests the condition code and branches or not according its value. | |
3389 | The branch insns come in distinct signed and unsigned flavors. Many | |
8aeea6e6 | 3390 | common machines, such as the VAX, the 68000 and the 32000, work this |
03dda8e3 RK |
3391 | way. |
3392 | ||
3393 | Some machines have distinct signed and unsigned compare instructions, and | |
3394 | only one set of conditional branch instructions. The easiest way to handle | |
3395 | these machines is to treat them just like the others until the final stage | |
3396 | where assembly code is written. At this time, when outputting code for the | |
3397 | compare instruction, peek ahead at the following branch using | |
3398 | @code{next_cc0_user (insn)}. (The variable @code{insn} refers to the insn | |
3399 | being output, in the output-writing code in an instruction pattern.) If | |
3400 | the RTL says that is an unsigned branch, output an unsigned compare; | |
3401 | otherwise output a signed compare. When the branch itself is output, you | |
3402 | can treat signed and unsigned branches identically. | |
3403 | ||
f0523f02 | 3404 | The reason you can do this is that GCC always generates a pair of |
03dda8e3 RK |
3405 | consecutive RTL insns, possibly separated by @code{note} insns, one to |
3406 | set the condition code and one to test it, and keeps the pair inviolate | |
3407 | until the end. | |
3408 | ||
3409 | To go with this technique, you must define the machine-description macro | |
3410 | @code{NOTICE_UPDATE_CC} to do @code{CC_STATUS_INIT}; in other words, no | |
3411 | compare instruction is superfluous. | |
3412 | ||
3413 | Some machines have compare-and-branch instructions and no condition code. | |
3414 | A similar technique works for them. When it is time to ``output'' a | |
3415 | compare instruction, record its operands in two static variables. When | |
3416 | outputting the branch-on-condition-code instruction that follows, actually | |
3417 | output a compare-and-branch instruction that uses the remembered operands. | |
3418 | ||
3419 | It also works to define patterns for compare-and-branch instructions. | |
3420 | In optimizing compilation, the pair of compare and branch instructions | |
3421 | will be combined according to these patterns. But this does not happen | |
3422 | if optimization is not requested. So you must use one of the solutions | |
3423 | above in addition to any special patterns you define. | |
3424 | ||
3425 | In many RISC machines, most instructions do not affect the condition | |
3426 | code and there may not even be a separate condition code register. On | |
3427 | these machines, the restriction that the definition and use of the | |
3428 | condition code be adjacent insns is not necessary and can prevent | |
3429 | important optimizations. For example, on the IBM RS/6000, there is a | |
3430 | delay for taken branches unless the condition code register is set three | |
3431 | instructions earlier than the conditional branch. The instruction | |
3432 | scheduler cannot perform this optimization if it is not permitted to | |
3433 | separate the definition and use of the condition code register. | |
3434 | ||
3435 | On these machines, do not use @code{(cc0)}, but instead use a register | |
3436 | to represent the condition code. If there is a specific condition code | |
3437 | register in the machine, use a hard register. If the condition code or | |
3438 | comparison result can be placed in any general register, or if there are | |
3439 | multiple condition registers, use a pseudo register. | |
3440 | ||
3441 | @findex prev_cc0_setter | |
3442 | @findex next_cc0_user | |
3443 | On some machines, the type of branch instruction generated may depend on | |
3444 | the way the condition code was produced; for example, on the 68k and | |
3445 | Sparc, setting the condition code directly from an add or subtract | |
3446 | instruction does not clear the overflow bit the way that a test | |
3447 | instruction does, so a different branch instruction must be used for | |
3448 | some conditional branches. For machines that use @code{(cc0)}, the set | |
3449 | and use of the condition code must be adjacent (separated only by | |
3450 | @code{note} insns) allowing flags in @code{cc_status} to be used. | |
3451 | (@xref{Condition Code}.) Also, the comparison and branch insns can be | |
3452 | located from each other by using the functions @code{prev_cc0_setter} | |
3453 | and @code{next_cc0_user}. | |
3454 | ||
3455 | However, this is not true on machines that do not use @code{(cc0)}. On | |
3456 | those machines, no assumptions can be made about the adjacency of the | |
3457 | compare and branch insns and the above methods cannot be used. Instead, | |
3458 | we use the machine mode of the condition code register to record | |
3459 | different formats of the condition code register. | |
3460 | ||
3461 | Registers used to store the condition code value should have a mode that | |
3462 | is in class @code{MODE_CC}. Normally, it will be @code{CCmode}. If | |
3463 | additional modes are required (as for the add example mentioned above in | |
3464 | the Sparc), define the macro @code{EXTRA_CC_MODES} to list the | |
3465 | additional modes required (@pxref{Condition Code}). Also define | |
03dda8e3 RK |
3466 | @code{SELECT_CC_MODE} to choose a mode given an operand of a compare. |
3467 | ||
3468 | If it is known during RTL generation that a different mode will be | |
3469 | required (for example, if the machine has separate compare instructions | |
3470 | for signed and unsigned quantities, like most IBM processors), they can | |
3471 | be specified at that time. | |
3472 | ||
3473 | If the cases that require different modes would be made by instruction | |
3474 | combination, the macro @code{SELECT_CC_MODE} determines which machine | |
3475 | mode should be used for the comparison result. The patterns should be | |
3476 | written using that mode. To support the case of the add on the Sparc | |
3477 | discussed above, we have the pattern | |
3478 | ||
3479 | @smallexample | |
3480 | (define_insn "" | |
3481 | [(set (reg:CC_NOOV 0) | |
3482 | (compare:CC_NOOV | |
3483 | (plus:SI (match_operand:SI 0 "register_operand" "%r") | |
3484 | (match_operand:SI 1 "arith_operand" "rI")) | |
3485 | (const_int 0)))] | |
3486 | "" | |
3487 | "@dots{}") | |
3488 | @end smallexample | |
3489 | ||
3490 | The @code{SELECT_CC_MODE} macro on the Sparc returns @code{CC_NOOVmode} | |
3491 | for comparisons whose argument is a @code{plus}. | |
3492 | ||
6e4fcc95 MH |
3493 | @node Looping Patterns |
3494 | @section Defining Looping Instruction Patterns | |
3495 | @cindex looping instruction patterns | |
3496 | @cindex defining looping instruction patterns | |
3497 | ||
3498 | Some machines have special jump instructions that can be utilised to | |
3499 | make loops more efficient. A common example is the 68000 @samp{dbra} | |
3500 | instruction which performs a decrement of a register and a branch if the | |
3501 | result was greater than zero. Other machines, in particular digital | |
3502 | signal processors (DSPs), have special block repeat instructions to | |
3503 | provide low-overhead loop support. For example, the TI TMS320C3x/C4x | |
3504 | DSPs have a block repeat instruction that loads special registers to | |
3505 | mark the top and end of a loop and to count the number of loop | |
3506 | iterations. This avoids the need for fetching and executing a | |
c771326b | 3507 | @samp{dbra}-like instruction and avoids pipeline stalls associated with |
6e4fcc95 MH |
3508 | the jump. |
3509 | ||
9c34dbbf ZW |
3510 | GCC has three special named patterns to support low overhead looping. |
3511 | They are @samp{decrement_and_branch_until_zero}, @samp{doloop_begin}, | |
3512 | and @samp{doloop_end}. The first pattern, | |
6e4fcc95 MH |
3513 | @samp{decrement_and_branch_until_zero}, is not emitted during RTL |
3514 | generation but may be emitted during the instruction combination phase. | |
3515 | This requires the assistance of the loop optimizer, using information | |
3516 | collected during strength reduction, to reverse a loop to count down to | |
3517 | zero. Some targets also require the loop optimizer to add a | |
3518 | @code{REG_NONNEG} note to indicate that the iteration count is always | |
3519 | positive. This is needed if the target performs a signed loop | |
3520 | termination test. For example, the 68000 uses a pattern similar to the | |
3521 | following for its @code{dbra} instruction: | |
3522 | ||
3523 | @smallexample | |
3524 | @group | |
3525 | (define_insn "decrement_and_branch_until_zero" | |
3526 | [(set (pc) | |
3527 | (if_then_else | |
3528 | (ge (plus:SI (match_operand:SI 0 "general_operand" "+d*am") | |
3529 | (const_int -1)) | |
3530 | (const_int 0)) | |
3531 | (label_ref (match_operand 1 "" "")) | |
3532 | (pc))) | |
3533 | (set (match_dup 0) | |
3534 | (plus:SI (match_dup 0) | |
3535 | (const_int -1)))] | |
3536 | "find_reg_note (insn, REG_NONNEG, 0)" | |
630d3d5a | 3537 | "@dots{}") |
6e4fcc95 MH |
3538 | @end group |
3539 | @end smallexample | |
3540 | ||
3541 | Note that since the insn is both a jump insn and has an output, it must | |
3542 | deal with its own reloads, hence the `m' constraints. Also note that | |
3543 | since this insn is generated by the instruction combination phase | |
3544 | combining two sequential insns together into an implicit parallel insn, | |
3545 | the iteration counter needs to be biased by the same amount as the | |
630d3d5a | 3546 | decrement operation, in this case @minus{}1. Note that the following similar |
6e4fcc95 MH |
3547 | pattern will not be matched by the combiner. |
3548 | ||
3549 | @smallexample | |
3550 | @group | |
3551 | (define_insn "decrement_and_branch_until_zero" | |
3552 | [(set (pc) | |
3553 | (if_then_else | |
3554 | (ge (match_operand:SI 0 "general_operand" "+d*am") | |
3555 | (const_int 1)) | |
3556 | (label_ref (match_operand 1 "" "")) | |
3557 | (pc))) | |
3558 | (set (match_dup 0) | |
3559 | (plus:SI (match_dup 0) | |
3560 | (const_int -1)))] | |
3561 | "find_reg_note (insn, REG_NONNEG, 0)" | |
630d3d5a | 3562 | "@dots{}") |
6e4fcc95 MH |
3563 | @end group |
3564 | @end smallexample | |
3565 | ||
3566 | The other two special looping patterns, @samp{doloop_begin} and | |
c21cd8b1 | 3567 | @samp{doloop_end}, are emitted by the loop optimizer for certain |
6e4fcc95 | 3568 | well-behaved loops with a finite number of loop iterations using |
ebb48a4d | 3569 | information collected during strength reduction. |
6e4fcc95 MH |
3570 | |
3571 | The @samp{doloop_end} pattern describes the actual looping instruction | |
3572 | (or the implicit looping operation) and the @samp{doloop_begin} pattern | |
c21cd8b1 | 3573 | is an optional companion pattern that can be used for initialization |
6e4fcc95 MH |
3574 | needed for some low-overhead looping instructions. |
3575 | ||
3576 | Note that some machines require the actual looping instruction to be | |
3577 | emitted at the top of the loop (e.g., the TMS320C3x/C4x DSPs). Emitting | |
3578 | the true RTL for a looping instruction at the top of the loop can cause | |
3579 | problems with flow analysis. So instead, a dummy @code{doloop} insn is | |
3580 | emitted at the end of the loop. The machine dependent reorg pass checks | |
3581 | for the presence of this @code{doloop} insn and then searches back to | |
3582 | the top of the loop, where it inserts the true looping insn (provided | |
3583 | there are no instructions in the loop which would cause problems). Any | |
3584 | additional labels can be emitted at this point. In addition, if the | |
3585 | desired special iteration counter register was not allocated, this | |
3586 | machine dependent reorg pass could emit a traditional compare and jump | |
3587 | instruction pair. | |
3588 | ||
3589 | The essential difference between the | |
3590 | @samp{decrement_and_branch_until_zero} and the @samp{doloop_end} | |
3591 | patterns is that the loop optimizer allocates an additional pseudo | |
3592 | register for the latter as an iteration counter. This pseudo register | |
3593 | cannot be used within the loop (i.e., general induction variables cannot | |
3594 | be derived from it), however, in many cases the loop induction variable | |
3595 | may become redundant and removed by the flow pass. | |
3596 | ||
3597 | ||
03dda8e3 RK |
3598 | @node Insn Canonicalizations |
3599 | @section Canonicalization of Instructions | |
3600 | @cindex canonicalization of instructions | |
3601 | @cindex insn canonicalization | |
3602 | ||
3603 | There are often cases where multiple RTL expressions could represent an | |
3604 | operation performed by a single machine instruction. This situation is | |
3605 | most commonly encountered with logical, branch, and multiply-accumulate | |
3606 | instructions. In such cases, the compiler attempts to convert these | |
3607 | multiple RTL expressions into a single canonical form to reduce the | |
3608 | number of insn patterns required. | |
3609 | ||
3610 | In addition to algebraic simplifications, following canonicalizations | |
3611 | are performed: | |
3612 | ||
3613 | @itemize @bullet | |
3614 | @item | |
3615 | For commutative and comparison operators, a constant is always made the | |
3616 | second operand. If a machine only supports a constant as the second | |
3617 | operand, only patterns that match a constant in the second operand need | |
3618 | be supplied. | |
3619 | ||
3620 | @cindex @code{neg}, canonicalization of | |
3621 | @cindex @code{not}, canonicalization of | |
3622 | @cindex @code{mult}, canonicalization of | |
3623 | @cindex @code{plus}, canonicalization of | |
3624 | @cindex @code{minus}, canonicalization of | |
3625 | For these operators, if only one operand is a @code{neg}, @code{not}, | |
3626 | @code{mult}, @code{plus}, or @code{minus} expression, it will be the | |
3627 | first operand. | |
3628 | ||
3629 | @cindex @code{compare}, canonicalization of | |
3630 | @item | |
3631 | For the @code{compare} operator, a constant is always the second operand | |
3632 | on machines where @code{cc0} is used (@pxref{Jump Patterns}). On other | |
3633 | machines, there are rare cases where the compiler might want to construct | |
3634 | a @code{compare} with a constant as the first operand. However, these | |
3635 | cases are not common enough for it to be worthwhile to provide a pattern | |
3636 | matching a constant as the first operand unless the machine actually has | |
3637 | such an instruction. | |
3638 | ||
3639 | An operand of @code{neg}, @code{not}, @code{mult}, @code{plus}, or | |
3640 | @code{minus} is made the first operand under the same conditions as | |
3641 | above. | |
3642 | ||
3643 | @item | |
3644 | @code{(minus @var{x} (const_int @var{n}))} is converted to | |
3645 | @code{(plus @var{x} (const_int @var{-n}))}. | |
3646 | ||
3647 | @item | |
3648 | Within address computations (i.e., inside @code{mem}), a left shift is | |
3649 | converted into the appropriate multiplication by a power of two. | |
3650 | ||
3651 | @cindex @code{ior}, canonicalization of | |
3652 | @cindex @code{and}, canonicalization of | |
3653 | @cindex De Morgan's law | |
72938a4c | 3654 | @item |
03dda8e3 RK |
3655 | De`Morgan's Law is used to move bitwise negation inside a bitwise |
3656 | logical-and or logical-or operation. If this results in only one | |
3657 | operand being a @code{not} expression, it will be the first one. | |
3658 | ||
3659 | A machine that has an instruction that performs a bitwise logical-and of one | |
3660 | operand with the bitwise negation of the other should specify the pattern | |
3661 | for that instruction as | |
3662 | ||
3663 | @example | |
3664 | (define_insn "" | |
3665 | [(set (match_operand:@var{m} 0 @dots{}) | |
3666 | (and:@var{m} (not:@var{m} (match_operand:@var{m} 1 @dots{})) | |
3667 | (match_operand:@var{m} 2 @dots{})))] | |
3668 | "@dots{}" | |
3669 | "@dots{}") | |
3670 | @end example | |
3671 | ||
3672 | @noindent | |
3673 | Similarly, a pattern for a ``NAND'' instruction should be written | |
3674 | ||
3675 | @example | |
3676 | (define_insn "" | |
3677 | [(set (match_operand:@var{m} 0 @dots{}) | |
3678 | (ior:@var{m} (not:@var{m} (match_operand:@var{m} 1 @dots{})) | |
3679 | (not:@var{m} (match_operand:@var{m} 2 @dots{}))))] | |
3680 | "@dots{}" | |
3681 | "@dots{}") | |
3682 | @end example | |
3683 | ||
3684 | In both cases, it is not necessary to include patterns for the many | |
3685 | logically equivalent RTL expressions. | |
3686 | ||
3687 | @cindex @code{xor}, canonicalization of | |
3688 | @item | |
3689 | The only possible RTL expressions involving both bitwise exclusive-or | |
3690 | and bitwise negation are @code{(xor:@var{m} @var{x} @var{y})} | |
bd819a4a | 3691 | and @code{(not:@var{m} (xor:@var{m} @var{x} @var{y}))}. |
03dda8e3 RK |
3692 | |
3693 | @item | |
3694 | The sum of three items, one of which is a constant, will only appear in | |
3695 | the form | |
3696 | ||
3697 | @example | |
3698 | (plus:@var{m} (plus:@var{m} @var{x} @var{y}) @var{constant}) | |
3699 | @end example | |
3700 | ||
3701 | @item | |
3702 | On machines that do not use @code{cc0}, | |
3703 | @code{(compare @var{x} (const_int 0))} will be converted to | |
bd819a4a | 3704 | @var{x}. |
03dda8e3 RK |
3705 | |
3706 | @cindex @code{zero_extract}, canonicalization of | |
3707 | @cindex @code{sign_extract}, canonicalization of | |
3708 | @item | |
3709 | Equality comparisons of a group of bits (usually a single bit) with zero | |
3710 | will be written using @code{zero_extract} rather than the equivalent | |
3711 | @code{and} or @code{sign_extract} operations. | |
3712 | ||
3713 | @end itemize | |
3714 | ||
03dda8e3 RK |
3715 | @node Expander Definitions |
3716 | @section Defining RTL Sequences for Code Generation | |
3717 | @cindex expander definitions | |
3718 | @cindex code generation RTL sequences | |
3719 | @cindex defining RTL sequences for code generation | |
3720 | ||
3721 | On some target machines, some standard pattern names for RTL generation | |
3722 | cannot be handled with single insn, but a sequence of RTL insns can | |
3723 | represent them. For these target machines, you can write a | |
161d7b59 | 3724 | @code{define_expand} to specify how to generate the sequence of RTL@. |
03dda8e3 RK |
3725 | |
3726 | @findex define_expand | |
3727 | A @code{define_expand} is an RTL expression that looks almost like a | |
3728 | @code{define_insn}; but, unlike the latter, a @code{define_expand} is used | |
3729 | only for RTL generation and it can produce more than one RTL insn. | |
3730 | ||
3731 | A @code{define_expand} RTX has four operands: | |
3732 | ||
3733 | @itemize @bullet | |
3734 | @item | |
3735 | The name. Each @code{define_expand} must have a name, since the only | |
3736 | use for it is to refer to it by name. | |
3737 | ||
03dda8e3 | 3738 | @item |
f3a3d0d3 RH |
3739 | The RTL template. This is a vector of RTL expressions representing |
3740 | a sequence of separate instructions. Unlike @code{define_insn}, there | |
3741 | is no implicit surrounding @code{PARALLEL}. | |
03dda8e3 RK |
3742 | |
3743 | @item | |
3744 | The condition, a string containing a C expression. This expression is | |
3745 | used to express how the availability of this pattern depends on | |
f0523f02 JM |
3746 | subclasses of target machine, selected by command-line options when GCC |
3747 | is run. This is just like the condition of a @code{define_insn} that | |
03dda8e3 RK |
3748 | has a standard name. Therefore, the condition (if present) may not |
3749 | depend on the data in the insn being matched, but only the | |
3750 | target-machine-type flags. The compiler needs to test these conditions | |
3751 | during initialization in order to learn exactly which named instructions | |
3752 | are available in a particular run. | |
3753 | ||
3754 | @item | |
3755 | The preparation statements, a string containing zero or more C | |
3756 | statements which are to be executed before RTL code is generated from | |
3757 | the RTL template. | |
3758 | ||
3759 | Usually these statements prepare temporary registers for use as | |
3760 | internal operands in the RTL template, but they can also generate RTL | |
3761 | insns directly by calling routines such as @code{emit_insn}, etc. | |
3762 | Any such insns precede the ones that come from the RTL template. | |
3763 | @end itemize | |
3764 | ||
3765 | Every RTL insn emitted by a @code{define_expand} must match some | |
3766 | @code{define_insn} in the machine description. Otherwise, the compiler | |
3767 | will crash when trying to generate code for the insn or trying to optimize | |
3768 | it. | |
3769 | ||
3770 | The RTL template, in addition to controlling generation of RTL insns, | |
3771 | also describes the operands that need to be specified when this pattern | |
3772 | is used. In particular, it gives a predicate for each operand. | |
3773 | ||
3774 | A true operand, which needs to be specified in order to generate RTL from | |
3775 | the pattern, should be described with a @code{match_operand} in its first | |
3776 | occurrence in the RTL template. This enters information on the operand's | |
f0523f02 | 3777 | predicate into the tables that record such things. GCC uses the |
03dda8e3 RK |
3778 | information to preload the operand into a register if that is required for |
3779 | valid RTL code. If the operand is referred to more than once, subsequent | |
3780 | references should use @code{match_dup}. | |
3781 | ||
3782 | The RTL template may also refer to internal ``operands'' which are | |
3783 | temporary registers or labels used only within the sequence made by the | |
3784 | @code{define_expand}. Internal operands are substituted into the RTL | |
3785 | template with @code{match_dup}, never with @code{match_operand}. The | |
3786 | values of the internal operands are not passed in as arguments by the | |
3787 | compiler when it requests use of this pattern. Instead, they are computed | |
3788 | within the pattern, in the preparation statements. These statements | |
3789 | compute the values and store them into the appropriate elements of | |
3790 | @code{operands} so that @code{match_dup} can find them. | |
3791 | ||
3792 | There are two special macros defined for use in the preparation statements: | |
3793 | @code{DONE} and @code{FAIL}. Use them with a following semicolon, | |
3794 | as a statement. | |
3795 | ||
3796 | @table @code | |
3797 | ||
3798 | @findex DONE | |
3799 | @item DONE | |
3800 | Use the @code{DONE} macro to end RTL generation for the pattern. The | |
3801 | only RTL insns resulting from the pattern on this occasion will be | |
3802 | those already emitted by explicit calls to @code{emit_insn} within the | |
3803 | preparation statements; the RTL template will not be generated. | |
3804 | ||
3805 | @findex FAIL | |
3806 | @item FAIL | |
3807 | Make the pattern fail on this occasion. When a pattern fails, it means | |
3808 | that the pattern was not truly available. The calling routines in the | |
3809 | compiler will try other strategies for code generation using other patterns. | |
3810 | ||
3811 | Failure is currently supported only for binary (addition, multiplication, | |
c771326b | 3812 | shifting, etc.) and bit-field (@code{extv}, @code{extzv}, and @code{insv}) |
03dda8e3 RK |
3813 | operations. |
3814 | @end table | |
3815 | ||
55e4756f DD |
3816 | If the preparation falls through (invokes neither @code{DONE} nor |
3817 | @code{FAIL}), then the @code{define_expand} acts like a | |
3818 | @code{define_insn} in that the RTL template is used to generate the | |
3819 | insn. | |
3820 | ||
3821 | The RTL template is not used for matching, only for generating the | |
3822 | initial insn list. If the preparation statement always invokes | |
3823 | @code{DONE} or @code{FAIL}, the RTL template may be reduced to a simple | |
3824 | list of operands, such as this example: | |
3825 | ||
3826 | @smallexample | |
3827 | @group | |
3828 | (define_expand "addsi3" | |
3829 | [(match_operand:SI 0 "register_operand" "") | |
3830 | (match_operand:SI 1 "register_operand" "") | |
3831 | (match_operand:SI 2 "register_operand" "")] | |
3832 | @end group | |
3833 | @group | |
3834 | "" | |
3835 | " | |
58097133 | 3836 | @{ |
55e4756f DD |
3837 | handle_add (operands[0], operands[1], operands[2]); |
3838 | DONE; | |
58097133 | 3839 | @}") |
55e4756f DD |
3840 | @end group |
3841 | @end smallexample | |
3842 | ||
03dda8e3 RK |
3843 | Here is an example, the definition of left-shift for the SPUR chip: |
3844 | ||
3845 | @smallexample | |
3846 | @group | |
3847 | (define_expand "ashlsi3" | |
3848 | [(set (match_operand:SI 0 "register_operand" "") | |
3849 | (ashift:SI | |
3850 | @end group | |
3851 | @group | |
3852 | (match_operand:SI 1 "register_operand" "") | |
3853 | (match_operand:SI 2 "nonmemory_operand" "")))] | |
3854 | "" | |
3855 | " | |
3856 | @end group | |
3857 | @end smallexample | |
3858 | ||
3859 | @smallexample | |
3860 | @group | |
3861 | @{ | |
3862 | if (GET_CODE (operands[2]) != CONST_INT | |
3863 | || (unsigned) INTVAL (operands[2]) > 3) | |
3864 | FAIL; | |
3865 | @}") | |
3866 | @end group | |
3867 | @end smallexample | |
3868 | ||
3869 | @noindent | |
3870 | This example uses @code{define_expand} so that it can generate an RTL insn | |
3871 | for shifting when the shift-count is in the supported range of 0 to 3 but | |
3872 | fail in other cases where machine insns aren't available. When it fails, | |
3873 | the compiler tries another strategy using different patterns (such as, a | |
3874 | library call). | |
3875 | ||
3876 | If the compiler were able to handle nontrivial condition-strings in | |
3877 | patterns with names, then it would be possible to use a | |
3878 | @code{define_insn} in that case. Here is another case (zero-extension | |
3879 | on the 68000) which makes more use of the power of @code{define_expand}: | |
3880 | ||
3881 | @smallexample | |
3882 | (define_expand "zero_extendhisi2" | |
3883 | [(set (match_operand:SI 0 "general_operand" "") | |
3884 | (const_int 0)) | |
3885 | (set (strict_low_part | |
3886 | (subreg:HI | |
3887 | (match_dup 0) | |
3888 | 0)) | |
3889 | (match_operand:HI 1 "general_operand" ""))] | |
3890 | "" | |
3891 | "operands[1] = make_safe_from (operands[1], operands[0]);") | |
3892 | @end smallexample | |
3893 | ||
3894 | @noindent | |
3895 | @findex make_safe_from | |
3896 | Here two RTL insns are generated, one to clear the entire output operand | |
3897 | and the other to copy the input operand into its low half. This sequence | |
3898 | is incorrect if the input operand refers to [the old value of] the output | |
3899 | operand, so the preparation statement makes sure this isn't so. The | |
3900 | function @code{make_safe_from} copies the @code{operands[1]} into a | |
3901 | temporary register if it refers to @code{operands[0]}. It does this | |
3902 | by emitting another RTL insn. | |
3903 | ||
3904 | Finally, a third example shows the use of an internal operand. | |
3905 | Zero-extension on the SPUR chip is done by @code{and}-ing the result | |
3906 | against a halfword mask. But this mask cannot be represented by a | |
3907 | @code{const_int} because the constant value is too large to be legitimate | |
3908 | on this machine. So it must be copied into a register with | |
3909 | @code{force_reg} and then the register used in the @code{and}. | |
3910 | ||
3911 | @smallexample | |
3912 | (define_expand "zero_extendhisi2" | |
3913 | [(set (match_operand:SI 0 "register_operand" "") | |
3914 | (and:SI (subreg:SI | |
3915 | (match_operand:HI 1 "register_operand" "") | |
3916 | 0) | |
3917 | (match_dup 2)))] | |
3918 | "" | |
3919 | "operands[2] | |
3a598fbe | 3920 | = force_reg (SImode, GEN_INT (65535)); ") |
03dda8e3 RK |
3921 | @end smallexample |
3922 | ||
3923 | @strong{Note:} If the @code{define_expand} is used to serve a | |
c771326b | 3924 | standard binary or unary arithmetic operation or a bit-field operation, |
03dda8e3 RK |
3925 | then the last insn it generates must not be a @code{code_label}, |
3926 | @code{barrier} or @code{note}. It must be an @code{insn}, | |
3927 | @code{jump_insn} or @code{call_insn}. If you don't need a real insn | |
3928 | at the end, emit an insn to copy the result of the operation into | |
3929 | itself. Such an insn will generate no code, but it can avoid problems | |
bd819a4a | 3930 | in the compiler. |
03dda8e3 RK |
3931 | |
3932 | @node Insn Splitting | |
3933 | @section Defining How to Split Instructions | |
3934 | @cindex insn splitting | |
3935 | @cindex instruction splitting | |
3936 | @cindex splitting instructions | |
3937 | ||
fae15c93 VM |
3938 | There are two cases where you should specify how to split a pattern |
3939 | into multiple insns. On machines that have instructions requiring | |
3940 | delay slots (@pxref{Delay Slots}) or that have instructions whose | |
3941 | output is not available for multiple cycles (@pxref{Processor pipeline | |
3942 | description}), the compiler phases that optimize these cases need to | |
3943 | be able to move insns into one-instruction delay slots. However, some | |
3944 | insns may generate more than one machine instruction. These insns | |
3945 | cannot be placed into a delay slot. | |
03dda8e3 RK |
3946 | |
3947 | Often you can rewrite the single insn as a list of individual insns, | |
3948 | each corresponding to one machine instruction. The disadvantage of | |
3949 | doing so is that it will cause the compilation to be slower and require | |
3950 | more space. If the resulting insns are too complex, it may also | |
3951 | suppress some optimizations. The compiler splits the insn if there is a | |
3952 | reason to believe that it might improve instruction or delay slot | |
3953 | scheduling. | |
3954 | ||
3955 | The insn combiner phase also splits putative insns. If three insns are | |
3956 | merged into one insn with a complex expression that cannot be matched by | |
3957 | some @code{define_insn} pattern, the combiner phase attempts to split | |
3958 | the complex pattern into two insns that are recognized. Usually it can | |
3959 | break the complex pattern into two patterns by splitting out some | |
3960 | subexpression. However, in some other cases, such as performing an | |
3961 | addition of a large constant in two insns on a RISC machine, the way to | |
3962 | split the addition into two insns is machine-dependent. | |
3963 | ||
f3a3d0d3 | 3964 | @findex define_split |
03dda8e3 RK |
3965 | The @code{define_split} definition tells the compiler how to split a |
3966 | complex insn into several simpler insns. It looks like this: | |
3967 | ||
3968 | @smallexample | |
3969 | (define_split | |
3970 | [@var{insn-pattern}] | |
3971 | "@var{condition}" | |
3972 | [@var{new-insn-pattern-1} | |
3973 | @var{new-insn-pattern-2} | |
3974 | @dots{}] | |
630d3d5a | 3975 | "@var{preparation-statements}") |
03dda8e3 RK |
3976 | @end smallexample |
3977 | ||
3978 | @var{insn-pattern} is a pattern that needs to be split and | |
3979 | @var{condition} is the final condition to be tested, as in a | |
3980 | @code{define_insn}. When an insn matching @var{insn-pattern} and | |
3981 | satisfying @var{condition} is found, it is replaced in the insn list | |
3982 | with the insns given by @var{new-insn-pattern-1}, | |
3983 | @var{new-insn-pattern-2}, etc. | |
3984 | ||
630d3d5a | 3985 | The @var{preparation-statements} are similar to those statements that |
03dda8e3 RK |
3986 | are specified for @code{define_expand} (@pxref{Expander Definitions}) |
3987 | and are executed before the new RTL is generated to prepare for the | |
3988 | generated code or emit some insns whose pattern is not fixed. Unlike | |
3989 | those in @code{define_expand}, however, these statements must not | |
3990 | generate any new pseudo-registers. Once reload has completed, they also | |
3991 | must not allocate any space in the stack frame. | |
3992 | ||
3993 | Patterns are matched against @var{insn-pattern} in two different | |
3994 | circumstances. If an insn needs to be split for delay slot scheduling | |
3995 | or insn scheduling, the insn is already known to be valid, which means | |
3996 | that it must have been matched by some @code{define_insn} and, if | |
df2a54e9 | 3997 | @code{reload_completed} is nonzero, is known to satisfy the constraints |
03dda8e3 RK |
3998 | of that @code{define_insn}. In that case, the new insn patterns must |
3999 | also be insns that are matched by some @code{define_insn} and, if | |
df2a54e9 | 4000 | @code{reload_completed} is nonzero, must also satisfy the constraints |
03dda8e3 RK |
4001 | of those definitions. |
4002 | ||
4003 | As an example of this usage of @code{define_split}, consider the following | |
4004 | example from @file{a29k.md}, which splits a @code{sign_extend} from | |
4005 | @code{HImode} to @code{SImode} into a pair of shift insns: | |
4006 | ||
4007 | @smallexample | |
4008 | (define_split | |
4009 | [(set (match_operand:SI 0 "gen_reg_operand" "") | |
4010 | (sign_extend:SI (match_operand:HI 1 "gen_reg_operand" "")))] | |
4011 | "" | |
4012 | [(set (match_dup 0) | |
4013 | (ashift:SI (match_dup 1) | |
4014 | (const_int 16))) | |
4015 | (set (match_dup 0) | |
4016 | (ashiftrt:SI (match_dup 0) | |
4017 | (const_int 16)))] | |
4018 | " | |
4019 | @{ operands[1] = gen_lowpart (SImode, operands[1]); @}") | |
4020 | @end smallexample | |
4021 | ||
4022 | When the combiner phase tries to split an insn pattern, it is always the | |
4023 | case that the pattern is @emph{not} matched by any @code{define_insn}. | |
4024 | The combiner pass first tries to split a single @code{set} expression | |
4025 | and then the same @code{set} expression inside a @code{parallel}, but | |
4026 | followed by a @code{clobber} of a pseudo-reg to use as a scratch | |
4027 | register. In these cases, the combiner expects exactly two new insn | |
4028 | patterns to be generated. It will verify that these patterns match some | |
4029 | @code{define_insn} definitions, so you need not do this test in the | |
4030 | @code{define_split} (of course, there is no point in writing a | |
4031 | @code{define_split} that will never produce insns that match). | |
4032 | ||
4033 | Here is an example of this use of @code{define_split}, taken from | |
4034 | @file{rs6000.md}: | |
4035 | ||
4036 | @smallexample | |
4037 | (define_split | |
4038 | [(set (match_operand:SI 0 "gen_reg_operand" "") | |
4039 | (plus:SI (match_operand:SI 1 "gen_reg_operand" "") | |
4040 | (match_operand:SI 2 "non_add_cint_operand" "")))] | |
4041 | "" | |
4042 | [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3))) | |
4043 | (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))] | |
4044 | " | |
4045 | @{ | |
4046 | int low = INTVAL (operands[2]) & 0xffff; | |
4047 | int high = (unsigned) INTVAL (operands[2]) >> 16; | |
4048 | ||
4049 | if (low & 0x8000) | |
4050 | high++, low |= 0xffff0000; | |
4051 | ||
3a598fbe JL |
4052 | operands[3] = GEN_INT (high << 16); |
4053 | operands[4] = GEN_INT (low); | |
03dda8e3 RK |
4054 | @}") |
4055 | @end smallexample | |
4056 | ||
4057 | Here the predicate @code{non_add_cint_operand} matches any | |
4058 | @code{const_int} that is @emph{not} a valid operand of a single add | |
4059 | insn. The add with the smaller displacement is written so that it | |
4060 | can be substituted into the address of a subsequent operation. | |
4061 | ||
4062 | An example that uses a scratch register, from the same file, generates | |
4063 | an equality comparison of a register and a large constant: | |
4064 | ||
4065 | @smallexample | |
4066 | (define_split | |
4067 | [(set (match_operand:CC 0 "cc_reg_operand" "") | |
4068 | (compare:CC (match_operand:SI 1 "gen_reg_operand" "") | |
4069 | (match_operand:SI 2 "non_short_cint_operand" ""))) | |
4070 | (clobber (match_operand:SI 3 "gen_reg_operand" ""))] | |
4071 | "find_single_use (operands[0], insn, 0) | |
4072 | && (GET_CODE (*find_single_use (operands[0], insn, 0)) == EQ | |
4073 | || GET_CODE (*find_single_use (operands[0], insn, 0)) == NE)" | |
4074 | [(set (match_dup 3) (xor:SI (match_dup 1) (match_dup 4))) | |
4075 | (set (match_dup 0) (compare:CC (match_dup 3) (match_dup 5)))] | |
4076 | " | |
4077 | @{ | |
4078 | /* Get the constant we are comparing against, C, and see what it | |
4079 | looks like sign-extended to 16 bits. Then see what constant | |
4080 | could be XOR'ed with C to get the sign-extended value. */ | |
4081 | ||
4082 | int c = INTVAL (operands[2]); | |
4083 | int sextc = (c << 16) >> 16; | |
4084 | int xorv = c ^ sextc; | |
4085 | ||
3a598fbe JL |
4086 | operands[4] = GEN_INT (xorv); |
4087 | operands[5] = GEN_INT (sextc); | |
03dda8e3 RK |
4088 | @}") |
4089 | @end smallexample | |
4090 | ||
4091 | To avoid confusion, don't write a single @code{define_split} that | |
4092 | accepts some insns that match some @code{define_insn} as well as some | |
4093 | insns that don't. Instead, write two separate @code{define_split} | |
4094 | definitions, one for the insns that are valid and one for the insns that | |
4095 | are not valid. | |
4096 | ||
6b24c259 JH |
4097 | The splitter is allowed to split jump instructions into sequence of |
4098 | jumps or create new jumps in while splitting non-jump instructions. As | |
4099 | the central flowgraph and branch prediction information needs to be updated, | |
f282ffb3 | 4100 | several restriction apply. |
6b24c259 JH |
4101 | |
4102 | Splitting of jump instruction into sequence that over by another jump | |
c21cd8b1 | 4103 | instruction is always valid, as compiler expect identical behavior of new |
6b24c259 JH |
4104 | jump. When new sequence contains multiple jump instructions or new labels, |
4105 | more assistance is needed. Splitter is required to create only unconditional | |
4106 | jumps, or simple conditional jump instructions. Additionally it must attach a | |
4107 | @code{REG_BR_PROB} note to each conditional jump. An global variable | |
4108 | @code{split_branch_probability} hold the probability of original branch in case | |
4109 | it was an simple conditional jump, @minus{}1 otherwise. To simplify | |
4110 | recomputing of edge frequencies, new sequence is required to have only | |
4111 | forward jumps to the newly created labels. | |
4112 | ||
fae81b38 | 4113 | @findex define_insn_and_split |
c88c0d42 CP |
4114 | For the common case where the pattern of a define_split exactly matches the |
4115 | pattern of a define_insn, use @code{define_insn_and_split}. It looks like | |
4116 | this: | |
4117 | ||
4118 | @smallexample | |
4119 | (define_insn_and_split | |
4120 | [@var{insn-pattern}] | |
4121 | "@var{condition}" | |
4122 | "@var{output-template}" | |
4123 | "@var{split-condition}" | |
4124 | [@var{new-insn-pattern-1} | |
4125 | @var{new-insn-pattern-2} | |
4126 | @dots{}] | |
630d3d5a | 4127 | "@var{preparation-statements}" |
c88c0d42 CP |
4128 | [@var{insn-attributes}]) |
4129 | ||
4130 | @end smallexample | |
4131 | ||
4132 | @var{insn-pattern}, @var{condition}, @var{output-template}, and | |
4133 | @var{insn-attributes} are used as in @code{define_insn}. The | |
4134 | @var{new-insn-pattern} vector and the @var{preparation-statements} are used as | |
4135 | in a @code{define_split}. The @var{split-condition} is also used as in | |
4136 | @code{define_split}, with the additional behavior that if the condition starts | |
4137 | with @samp{&&}, the condition used for the split will be the constructed as a | |
d7d9c429 | 4138 | logical ``and'' of the split condition with the insn condition. For example, |
c88c0d42 CP |
4139 | from i386.md: |
4140 | ||
4141 | @smallexample | |
4142 | (define_insn_and_split "zero_extendhisi2_and" | |
4143 | [(set (match_operand:SI 0 "register_operand" "=r") | |
4144 | (zero_extend:SI (match_operand:HI 1 "register_operand" "0"))) | |
4145 | (clobber (reg:CC 17))] | |
4146 | "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size" | |
4147 | "#" | |
4148 | "&& reload_completed" | |
f282ffb3 | 4149 | [(parallel [(set (match_dup 0) |
9c34dbbf | 4150 | (and:SI (match_dup 0) (const_int 65535))) |
c88c0d42 CP |
4151 | (clobber (reg:CC 17))])] |
4152 | "" | |
4153 | [(set_attr "type" "alu1")]) | |
4154 | ||
4155 | @end smallexample | |
4156 | ||
ebb48a4d | 4157 | In this case, the actual split condition will be |
aee96fe9 | 4158 | @samp{TARGET_ZERO_EXTEND_WITH_AND && !optimize_size && reload_completed}. |
c88c0d42 CP |
4159 | |
4160 | The @code{define_insn_and_split} construction provides exactly the same | |
4161 | functionality as two separate @code{define_insn} and @code{define_split} | |
4162 | patterns. It exists for compactness, and as a maintenance tool to prevent | |
4163 | having to ensure the two patterns' templates match. | |
4164 | ||
04d8aa70 AM |
4165 | @node Including Patterns |
4166 | @section Including Patterns in Machine Descriptions. | |
4167 | @cindex insn includes | |
4168 | ||
4169 | @findex include | |
4170 | The @code{include} pattern tells the compiler tools where to | |
4171 | look for patterns that are in files other than in the file | |
4172 | @file{.md}. This is used only at build time and there is no preprocessing allowed. | |
4173 | ||
4174 | It looks like: | |
4175 | ||
4176 | @smallexample | |
4177 | ||
4178 | (include | |
4179 | @var{pathname}) | |
4180 | @end smallexample | |
4181 | ||
4182 | For example: | |
4183 | ||
4184 | @smallexample | |
4185 | ||
f282ffb3 | 4186 | (include "filestuff") |
04d8aa70 AM |
4187 | |
4188 | @end smallexample | |
4189 | ||
4190 | Where @var{pathname} is a string that specifies the the location of the file, | |
4191 | specifies the include file to be in @file{gcc/config/target/filestuff}. The | |
4192 | directory @file{gcc/config/target} is regarded as the default directory. | |
4193 | ||
4194 | ||
f282ffb3 JM |
4195 | Machine descriptions may be split up into smaller more manageable subsections |
4196 | and placed into subdirectories. | |
04d8aa70 AM |
4197 | |
4198 | By specifying: | |
4199 | ||
4200 | @smallexample | |
4201 | ||
f282ffb3 | 4202 | (include "BOGUS/filestuff") |
04d8aa70 AM |
4203 | |
4204 | @end smallexample | |
4205 | ||
4206 | the include file is specified to be in @file{gcc/config/@var{target}/BOGUS/filestuff}. | |
4207 | ||
4208 | Specifying an absolute path for the include file such as; | |
4209 | @smallexample | |
4210 | ||
f282ffb3 | 4211 | (include "/u2/BOGUS/filestuff") |
04d8aa70 AM |
4212 | |
4213 | @end smallexample | |
f282ffb3 | 4214 | is permitted but is not encouraged. |
04d8aa70 AM |
4215 | |
4216 | @subsection RTL Generation Tool Options for Directory Search | |
4217 | @cindex directory options .md | |
4218 | @cindex options, directory search | |
4219 | @cindex search options | |
4220 | ||
4221 | The @option{-I@var{dir}} option specifies directories to search for machine descriptions. | |
4222 | For example: | |
4223 | ||
4224 | @smallexample | |
4225 | ||
4226 | genrecog -I/p1/abc/proc1 -I/p2/abcd/pro2 target.md | |
4227 | ||
4228 | @end smallexample | |
4229 | ||
4230 | ||
4231 | Add the directory @var{dir} to the head of the list of directories to be | |
4232 | searched for header files. This can be used to override a system machine definition | |
4233 | file, substituting your own version, since these directories are | |
4234 | searched before the default machine description file directories. If you use more than | |
4235 | one @option{-I} option, the directories are scanned in left-to-right | |
4236 | order; the standard default directory come after. | |
4237 | ||
4238 | ||
f3a3d0d3 RH |
4239 | @node Peephole Definitions |
4240 | @section Machine-Specific Peephole Optimizers | |
4241 | @cindex peephole optimizer definitions | |
4242 | @cindex defining peephole optimizers | |
4243 | ||
4244 | In addition to instruction patterns the @file{md} file may contain | |
4245 | definitions of machine-specific peephole optimizations. | |
4246 | ||
4247 | The combiner does not notice certain peephole optimizations when the data | |
4248 | flow in the program does not suggest that it should try them. For example, | |
4249 | sometimes two consecutive insns related in purpose can be combined even | |
4250 | though the second one does not appear to use a register computed in the | |
4251 | first one. A machine-specific peephole optimizer can detect such | |
4252 | opportunities. | |
4253 | ||
4254 | There are two forms of peephole definitions that may be used. The | |
4255 | original @code{define_peephole} is run at assembly output time to | |
4256 | match insns and substitute assembly text. Use of @code{define_peephole} | |
4257 | is deprecated. | |
4258 | ||
4259 | A newer @code{define_peephole2} matches insns and substitutes new | |
4260 | insns. The @code{peephole2} pass is run after register allocation | |
ebb48a4d | 4261 | but before scheduling, which may result in much better code for |
f3a3d0d3 RH |
4262 | targets that do scheduling. |
4263 | ||
4264 | @menu | |
4265 | * define_peephole:: RTL to Text Peephole Optimizers | |
4266 | * define_peephole2:: RTL to RTL Peephole Optimizers | |
4267 | @end menu | |
4268 | ||
4269 | @node define_peephole | |
4270 | @subsection RTL to Text Peephole Optimizers | |
4271 | @findex define_peephole | |
4272 | ||
4273 | @need 1000 | |
4274 | A definition looks like this: | |
4275 | ||
4276 | @smallexample | |
4277 | (define_peephole | |
4278 | [@var{insn-pattern-1} | |
4279 | @var{insn-pattern-2} | |
4280 | @dots{}] | |
4281 | "@var{condition}" | |
4282 | "@var{template}" | |
630d3d5a | 4283 | "@var{optional-insn-attributes}") |
f3a3d0d3 RH |
4284 | @end smallexample |
4285 | ||
4286 | @noindent | |
4287 | The last string operand may be omitted if you are not using any | |
4288 | machine-specific information in this machine description. If present, | |
4289 | it must obey the same rules as in a @code{define_insn}. | |
4290 | ||
4291 | In this skeleton, @var{insn-pattern-1} and so on are patterns to match | |
4292 | consecutive insns. The optimization applies to a sequence of insns when | |
4293 | @var{insn-pattern-1} matches the first one, @var{insn-pattern-2} matches | |
bd819a4a | 4294 | the next, and so on. |
f3a3d0d3 RH |
4295 | |
4296 | Each of the insns matched by a peephole must also match a | |
4297 | @code{define_insn}. Peepholes are checked only at the last stage just | |
4298 | before code generation, and only optionally. Therefore, any insn which | |
4299 | would match a peephole but no @code{define_insn} will cause a crash in code | |
4300 | generation in an unoptimized compilation, or at various optimization | |
4301 | stages. | |
4302 | ||
4303 | The operands of the insns are matched with @code{match_operands}, | |
4304 | @code{match_operator}, and @code{match_dup}, as usual. What is not | |
4305 | usual is that the operand numbers apply to all the insn patterns in the | |
4306 | definition. So, you can check for identical operands in two insns by | |
4307 | using @code{match_operand} in one insn and @code{match_dup} in the | |
4308 | other. | |
4309 | ||
4310 | The operand constraints used in @code{match_operand} patterns do not have | |
4311 | any direct effect on the applicability of the peephole, but they will | |
4312 | be validated afterward, so make sure your constraints are general enough | |
4313 | to apply whenever the peephole matches. If the peephole matches | |
4314 | but the constraints are not satisfied, the compiler will crash. | |
4315 | ||
4316 | It is safe to omit constraints in all the operands of the peephole; or | |
4317 | you can write constraints which serve as a double-check on the criteria | |
4318 | previously tested. | |
4319 | ||
4320 | Once a sequence of insns matches the patterns, the @var{condition} is | |
4321 | checked. This is a C expression which makes the final decision whether to | |
4322 | perform the optimization (we do so if the expression is nonzero). If | |
4323 | @var{condition} is omitted (in other words, the string is empty) then the | |
4324 | optimization is applied to every sequence of insns that matches the | |
4325 | patterns. | |
4326 | ||
4327 | The defined peephole optimizations are applied after register allocation | |
4328 | is complete. Therefore, the peephole definition can check which | |
4329 | operands have ended up in which kinds of registers, just by looking at | |
4330 | the operands. | |
4331 | ||
4332 | @findex prev_active_insn | |
4333 | The way to refer to the operands in @var{condition} is to write | |
4334 | @code{operands[@var{i}]} for operand number @var{i} (as matched by | |
4335 | @code{(match_operand @var{i} @dots{})}). Use the variable @code{insn} | |
4336 | to refer to the last of the insns being matched; use | |
4337 | @code{prev_active_insn} to find the preceding insns. | |
4338 | ||
4339 | @findex dead_or_set_p | |
4340 | When optimizing computations with intermediate results, you can use | |
4341 | @var{condition} to match only when the intermediate results are not used | |
4342 | elsewhere. Use the C expression @code{dead_or_set_p (@var{insn}, | |
4343 | @var{op})}, where @var{insn} is the insn in which you expect the value | |
4344 | to be used for the last time (from the value of @code{insn}, together | |
4345 | with use of @code{prev_nonnote_insn}), and @var{op} is the intermediate | |
bd819a4a | 4346 | value (from @code{operands[@var{i}]}). |
f3a3d0d3 RH |
4347 | |
4348 | Applying the optimization means replacing the sequence of insns with one | |
4349 | new insn. The @var{template} controls ultimate output of assembler code | |
4350 | for this combined insn. It works exactly like the template of a | |
4351 | @code{define_insn}. Operand numbers in this template are the same ones | |
4352 | used in matching the original sequence of insns. | |
4353 | ||
4354 | The result of a defined peephole optimizer does not need to match any of | |
4355 | the insn patterns in the machine description; it does not even have an | |
4356 | opportunity to match them. The peephole optimizer definition itself serves | |
4357 | as the insn pattern to control how the insn is output. | |
4358 | ||
4359 | Defined peephole optimizers are run as assembler code is being output, | |
4360 | so the insns they produce are never combined or rearranged in any way. | |
4361 | ||
4362 | Here is an example, taken from the 68000 machine description: | |
4363 | ||
4364 | @smallexample | |
4365 | (define_peephole | |
4366 | [(set (reg:SI 15) (plus:SI (reg:SI 15) (const_int 4))) | |
4367 | (set (match_operand:DF 0 "register_operand" "=f") | |
4368 | (match_operand:DF 1 "register_operand" "ad"))] | |
4369 | "FP_REG_P (operands[0]) && ! FP_REG_P (operands[1])" | |
f3a3d0d3 RH |
4370 | @{ |
4371 | rtx xoperands[2]; | |
4372 | xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1); | |
4373 | #ifdef MOTOROLA | |
0f40f9f7 ZW |
4374 | output_asm_insn ("move.l %1,(sp)", xoperands); |
4375 | output_asm_insn ("move.l %1,-(sp)", operands); | |
4376 | return "fmove.d (sp)+,%0"; | |
f3a3d0d3 | 4377 | #else |
0f40f9f7 ZW |
4378 | output_asm_insn ("movel %1,sp@@", xoperands); |
4379 | output_asm_insn ("movel %1,sp@@-", operands); | |
4380 | return "fmoved sp@@+,%0"; | |
f3a3d0d3 | 4381 | #endif |
0f40f9f7 | 4382 | @}) |
f3a3d0d3 RH |
4383 | @end smallexample |
4384 | ||
4385 | @need 1000 | |
4386 | The effect of this optimization is to change | |
4387 | ||
4388 | @smallexample | |
4389 | @group | |
4390 | jbsr _foobar | |
4391 | addql #4,sp | |
4392 | movel d1,sp@@- | |
4393 | movel d0,sp@@- | |
4394 | fmoved sp@@+,fp0 | |
4395 | @end group | |
4396 | @end smallexample | |
4397 | ||
4398 | @noindent | |
4399 | into | |
4400 | ||
4401 | @smallexample | |
4402 | @group | |
4403 | jbsr _foobar | |
4404 | movel d1,sp@@ | |
4405 | movel d0,sp@@- | |
4406 | fmoved sp@@+,fp0 | |
4407 | @end group | |
4408 | @end smallexample | |
4409 | ||
4410 | @ignore | |
4411 | @findex CC_REVERSED | |
4412 | If a peephole matches a sequence including one or more jump insns, you must | |
4413 | take account of the flags such as @code{CC_REVERSED} which specify that the | |
4414 | condition codes are represented in an unusual manner. The compiler | |
4415 | automatically alters any ordinary conditional jumps which occur in such | |
4416 | situations, but the compiler cannot alter jumps which have been replaced by | |
4417 | peephole optimizations. So it is up to you to alter the assembler code | |
4418 | that the peephole produces. Supply C code to write the assembler output, | |
4419 | and in this C code check the condition code status flags and change the | |
4420 | assembler code as appropriate. | |
4421 | @end ignore | |
4422 | ||
4423 | @var{insn-pattern-1} and so on look @emph{almost} like the second | |
4424 | operand of @code{define_insn}. There is one important difference: the | |
4425 | second operand of @code{define_insn} consists of one or more RTX's | |
4426 | enclosed in square brackets. Usually, there is only one: then the same | |
4427 | action can be written as an element of a @code{define_peephole}. But | |
4428 | when there are multiple actions in a @code{define_insn}, they are | |
4429 | implicitly enclosed in a @code{parallel}. Then you must explicitly | |
4430 | write the @code{parallel}, and the square brackets within it, in the | |
4431 | @code{define_peephole}. Thus, if an insn pattern looks like this, | |
4432 | ||
4433 | @smallexample | |
4434 | (define_insn "divmodsi4" | |
4435 | [(set (match_operand:SI 0 "general_operand" "=d") | |
4436 | (div:SI (match_operand:SI 1 "general_operand" "0") | |
4437 | (match_operand:SI 2 "general_operand" "dmsK"))) | |
4438 | (set (match_operand:SI 3 "general_operand" "=d") | |
4439 | (mod:SI (match_dup 1) (match_dup 2)))] | |
4440 | "TARGET_68020" | |
4441 | "divsl%.l %2,%3:%0") | |
4442 | @end smallexample | |
4443 | ||
4444 | @noindent | |
4445 | then the way to mention this insn in a peephole is as follows: | |
4446 | ||
4447 | @smallexample | |
4448 | (define_peephole | |
4449 | [@dots{} | |
4450 | (parallel | |
4451 | [(set (match_operand:SI 0 "general_operand" "=d") | |
4452 | (div:SI (match_operand:SI 1 "general_operand" "0") | |
4453 | (match_operand:SI 2 "general_operand" "dmsK"))) | |
4454 | (set (match_operand:SI 3 "general_operand" "=d") | |
4455 | (mod:SI (match_dup 1) (match_dup 2)))]) | |
4456 | @dots{}] | |
4457 | @dots{}) | |
4458 | @end smallexample | |
4459 | ||
4460 | @node define_peephole2 | |
4461 | @subsection RTL to RTL Peephole Optimizers | |
4462 | @findex define_peephole2 | |
4463 | ||
4464 | The @code{define_peephole2} definition tells the compiler how to | |
ebb48a4d | 4465 | substitute one sequence of instructions for another sequence, |
f3a3d0d3 RH |
4466 | what additional scratch registers may be needed and what their |
4467 | lifetimes must be. | |
4468 | ||
4469 | @smallexample | |
4470 | (define_peephole2 | |
4471 | [@var{insn-pattern-1} | |
4472 | @var{insn-pattern-2} | |
4473 | @dots{}] | |
4474 | "@var{condition}" | |
4475 | [@var{new-insn-pattern-1} | |
4476 | @var{new-insn-pattern-2} | |
4477 | @dots{}] | |
630d3d5a | 4478 | "@var{preparation-statements}") |
f3a3d0d3 RH |
4479 | @end smallexample |
4480 | ||
4481 | The definition is almost identical to @code{define_split} | |
4482 | (@pxref{Insn Splitting}) except that the pattern to match is not a | |
4483 | single instruction, but a sequence of instructions. | |
4484 | ||
4485 | It is possible to request additional scratch registers for use in the | |
4486 | output template. If appropriate registers are not free, the pattern | |
4487 | will simply not match. | |
4488 | ||
4489 | @findex match_scratch | |
4490 | @findex match_dup | |
4491 | Scratch registers are requested with a @code{match_scratch} pattern at | |
4492 | the top level of the input pattern. The allocated register (initially) will | |
4493 | be dead at the point requested within the original sequence. If the scratch | |
4494 | is used at more than a single point, a @code{match_dup} pattern at the | |
4495 | top level of the input pattern marks the last position in the input sequence | |
4496 | at which the register must be available. | |
4497 | ||
4498 | Here is an example from the IA-32 machine description: | |
4499 | ||
4500 | @smallexample | |
4501 | (define_peephole2 | |
4502 | [(match_scratch:SI 2 "r") | |
4503 | (parallel [(set (match_operand:SI 0 "register_operand" "") | |
4504 | (match_operator:SI 3 "arith_or_logical_operator" | |
4505 | [(match_dup 0) | |
4506 | (match_operand:SI 1 "memory_operand" "")])) | |
4507 | (clobber (reg:CC 17))])] | |
4508 | "! optimize_size && ! TARGET_READ_MODIFY" | |
4509 | [(set (match_dup 2) (match_dup 1)) | |
4510 | (parallel [(set (match_dup 0) | |
4511 | (match_op_dup 3 [(match_dup 0) (match_dup 2)])) | |
4512 | (clobber (reg:CC 17))])] | |
4513 | "") | |
4514 | @end smallexample | |
4515 | ||
4516 | @noindent | |
4517 | This pattern tries to split a load from its use in the hopes that we'll be | |
4518 | able to schedule around the memory load latency. It allocates a single | |
4519 | @code{SImode} register of class @code{GENERAL_REGS} (@code{"r"}) that needs | |
4520 | to be live only at the point just before the arithmetic. | |
4521 | ||
b192711e | 4522 | A real example requiring extended scratch lifetimes is harder to come by, |
f3a3d0d3 RH |
4523 | so here's a silly made-up example: |
4524 | ||
4525 | @smallexample | |
4526 | (define_peephole2 | |
4527 | [(match_scratch:SI 4 "r") | |
4528 | (set (match_operand:SI 0 "" "") (match_operand:SI 1 "" "")) | |
4529 | (set (match_operand:SI 2 "" "") (match_dup 1)) | |
4530 | (match_dup 4) | |
4531 | (set (match_operand:SI 3 "" "") (match_dup 1))] | |
630d3d5a | 4532 | "/* @r{determine 1 does not overlap 0 and 2} */" |
f3a3d0d3 RH |
4533 | [(set (match_dup 4) (match_dup 1)) |
4534 | (set (match_dup 0) (match_dup 4)) | |
4535 | (set (match_dup 2) (match_dup 4))] | |
4536 | (set (match_dup 3) (match_dup 4))] | |
4537 | "") | |
4538 | @end smallexample | |
4539 | ||
4540 | @noindent | |
a628d195 RH |
4541 | If we had not added the @code{(match_dup 4)} in the middle of the input |
4542 | sequence, it might have been the case that the register we chose at the | |
4543 | beginning of the sequence is killed by the first or second @code{set}. | |
f3a3d0d3 | 4544 | |
03dda8e3 RK |
4545 | @node Insn Attributes |
4546 | @section Instruction Attributes | |
4547 | @cindex insn attributes | |
4548 | @cindex instruction attributes | |
4549 | ||
4550 | In addition to describing the instruction supported by the target machine, | |
4551 | the @file{md} file also defines a group of @dfn{attributes} and a set of | |
4552 | values for each. Every generated insn is assigned a value for each attribute. | |
4553 | One possible attribute would be the effect that the insn has on the machine's | |
4554 | condition code. This attribute can then be used by @code{NOTICE_UPDATE_CC} | |
4555 | to track the condition codes. | |
4556 | ||
4557 | @menu | |
4558 | * Defining Attributes:: Specifying attributes and their values. | |
4559 | * Expressions:: Valid expressions for attribute values. | |
4560 | * Tagging Insns:: Assigning attribute values to insns. | |
4561 | * Attr Example:: An example of assigning attributes. | |
4562 | * Insn Lengths:: Computing the length of insns. | |
4563 | * Constant Attributes:: Defining attributes that are constant. | |
4564 | * Delay Slots:: Defining delay slots required for a machine. | |
fae15c93 | 4565 | * Processor pipeline description:: Specifying information for insn scheduling. |
03dda8e3 RK |
4566 | @end menu |
4567 | ||
4568 | @node Defining Attributes | |
4569 | @subsection Defining Attributes and their Values | |
4570 | @cindex defining attributes and their values | |
4571 | @cindex attributes, defining | |
4572 | ||
4573 | @findex define_attr | |
4574 | The @code{define_attr} expression is used to define each attribute required | |
4575 | by the target machine. It looks like: | |
4576 | ||
4577 | @smallexample | |
4578 | (define_attr @var{name} @var{list-of-values} @var{default}) | |
4579 | @end smallexample | |
4580 | ||
4581 | @var{name} is a string specifying the name of the attribute being defined. | |
4582 | ||
4583 | @var{list-of-values} is either a string that specifies a comma-separated | |
4584 | list of values that can be assigned to the attribute, or a null string to | |
4585 | indicate that the attribute takes numeric values. | |
4586 | ||
4587 | @var{default} is an attribute expression that gives the value of this | |
4588 | attribute for insns that match patterns whose definition does not include | |
4589 | an explicit value for this attribute. @xref{Attr Example}, for more | |
4590 | information on the handling of defaults. @xref{Constant Attributes}, | |
4591 | for information on attributes that do not depend on any particular insn. | |
4592 | ||
4593 | @findex insn-attr.h | |
4594 | For each defined attribute, a number of definitions are written to the | |
4595 | @file{insn-attr.h} file. For cases where an explicit set of values is | |
4596 | specified for an attribute, the following are defined: | |
4597 | ||
4598 | @itemize @bullet | |
4599 | @item | |
4600 | A @samp{#define} is written for the symbol @samp{HAVE_ATTR_@var{name}}. | |
4601 | ||
4602 | @item | |
4603 | An enumeral class is defined for @samp{attr_@var{name}} with | |
4604 | elements of the form @samp{@var{upper-name}_@var{upper-value}} where | |
4605 | the attribute name and value are first converted to upper case. | |
4606 | ||
4607 | @item | |
4608 | A function @samp{get_attr_@var{name}} is defined that is passed an insn and | |
4609 | returns the attribute value for that insn. | |
4610 | @end itemize | |
4611 | ||
4612 | For example, if the following is present in the @file{md} file: | |
4613 | ||
4614 | @smallexample | |
4615 | (define_attr "type" "branch,fp,load,store,arith" @dots{}) | |
4616 | @end smallexample | |
4617 | ||
4618 | @noindent | |
4619 | the following lines will be written to the file @file{insn-attr.h}. | |
4620 | ||
4621 | @smallexample | |
4622 | #define HAVE_ATTR_type | |
4623 | enum attr_type @{TYPE_BRANCH, TYPE_FP, TYPE_LOAD, | |
4624 | TYPE_STORE, TYPE_ARITH@}; | |
4625 | extern enum attr_type get_attr_type (); | |
4626 | @end smallexample | |
4627 | ||
4628 | If the attribute takes numeric values, no @code{enum} type will be | |
4629 | defined and the function to obtain the attribute's value will return | |
4630 | @code{int}. | |
4631 | ||
4632 | @node Expressions | |
4633 | @subsection Attribute Expressions | |
4634 | @cindex attribute expressions | |
4635 | ||
4636 | RTL expressions used to define attributes use the codes described above | |
4637 | plus a few specific to attribute definitions, to be discussed below. | |
4638 | Attribute value expressions must have one of the following forms: | |
4639 | ||
4640 | @table @code | |
4641 | @cindex @code{const_int} and attributes | |
4642 | @item (const_int @var{i}) | |
4643 | The integer @var{i} specifies the value of a numeric attribute. @var{i} | |
4644 | must be non-negative. | |
4645 | ||
4646 | The value of a numeric attribute can be specified either with a | |
00bc45c1 RH |
4647 | @code{const_int}, or as an integer represented as a string in |
4648 | @code{const_string}, @code{eq_attr} (see below), @code{attr}, | |
4649 | @code{symbol_ref}, simple arithmetic expressions, and @code{set_attr} | |
4650 | overrides on specific instructions (@pxref{Tagging Insns}). | |
03dda8e3 RK |
4651 | |
4652 | @cindex @code{const_string} and attributes | |
4653 | @item (const_string @var{value}) | |
4654 | The string @var{value} specifies a constant attribute value. | |
4655 | If @var{value} is specified as @samp{"*"}, it means that the default value of | |
4656 | the attribute is to be used for the insn containing this expression. | |
4657 | @samp{"*"} obviously cannot be used in the @var{default} expression | |
bd819a4a | 4658 | of a @code{define_attr}. |
03dda8e3 RK |
4659 | |
4660 | If the attribute whose value is being specified is numeric, @var{value} | |
4661 | must be a string containing a non-negative integer (normally | |
4662 | @code{const_int} would be used in this case). Otherwise, it must | |
4663 | contain one of the valid values for the attribute. | |
4664 | ||
4665 | @cindex @code{if_then_else} and attributes | |
4666 | @item (if_then_else @var{test} @var{true-value} @var{false-value}) | |
4667 | @var{test} specifies an attribute test, whose format is defined below. | |
4668 | The value of this expression is @var{true-value} if @var{test} is true, | |
4669 | otherwise it is @var{false-value}. | |
4670 | ||
4671 | @cindex @code{cond} and attributes | |
4672 | @item (cond [@var{test1} @var{value1} @dots{}] @var{default}) | |
4673 | The first operand of this expression is a vector containing an even | |
4674 | number of expressions and consisting of pairs of @var{test} and @var{value} | |
4675 | expressions. The value of the @code{cond} expression is that of the | |
4676 | @var{value} corresponding to the first true @var{test} expression. If | |
4677 | none of the @var{test} expressions are true, the value of the @code{cond} | |
4678 | expression is that of the @var{default} expression. | |
4679 | @end table | |
4680 | ||
4681 | @var{test} expressions can have one of the following forms: | |
4682 | ||
4683 | @table @code | |
4684 | @cindex @code{const_int} and attribute tests | |
4685 | @item (const_int @var{i}) | |
df2a54e9 | 4686 | This test is true if @var{i} is nonzero and false otherwise. |
03dda8e3 RK |
4687 | |
4688 | @cindex @code{not} and attributes | |
4689 | @cindex @code{ior} and attributes | |
4690 | @cindex @code{and} and attributes | |
4691 | @item (not @var{test}) | |
4692 | @itemx (ior @var{test1} @var{test2}) | |
4693 | @itemx (and @var{test1} @var{test2}) | |
4694 | These tests are true if the indicated logical function is true. | |
4695 | ||
4696 | @cindex @code{match_operand} and attributes | |
4697 | @item (match_operand:@var{m} @var{n} @var{pred} @var{constraints}) | |
4698 | This test is true if operand @var{n} of the insn whose attribute value | |
4699 | is being determined has mode @var{m} (this part of the test is ignored | |
4700 | if @var{m} is @code{VOIDmode}) and the function specified by the string | |
df2a54e9 | 4701 | @var{pred} returns a nonzero value when passed operand @var{n} and mode |
03dda8e3 RK |
4702 | @var{m} (this part of the test is ignored if @var{pred} is the null |
4703 | string). | |
4704 | ||
4705 | The @var{constraints} operand is ignored and should be the null string. | |
4706 | ||
4707 | @cindex @code{le} and attributes | |
4708 | @cindex @code{leu} and attributes | |
4709 | @cindex @code{lt} and attributes | |
4710 | @cindex @code{gt} and attributes | |
4711 | @cindex @code{gtu} and attributes | |
4712 | @cindex @code{ge} and attributes | |
4713 | @cindex @code{geu} and attributes | |
4714 | @cindex @code{ne} and attributes | |
4715 | @cindex @code{eq} and attributes | |
4716 | @cindex @code{plus} and attributes | |
4717 | @cindex @code{minus} and attributes | |
4718 | @cindex @code{mult} and attributes | |
4719 | @cindex @code{div} and attributes | |
4720 | @cindex @code{mod} and attributes | |
4721 | @cindex @code{abs} and attributes | |
4722 | @cindex @code{neg} and attributes | |
4723 | @cindex @code{ashift} and attributes | |
4724 | @cindex @code{lshiftrt} and attributes | |
4725 | @cindex @code{ashiftrt} and attributes | |
4726 | @item (le @var{arith1} @var{arith2}) | |
4727 | @itemx (leu @var{arith1} @var{arith2}) | |
4728 | @itemx (lt @var{arith1} @var{arith2}) | |
4729 | @itemx (ltu @var{arith1} @var{arith2}) | |
4730 | @itemx (gt @var{arith1} @var{arith2}) | |
4731 | @itemx (gtu @var{arith1} @var{arith2}) | |
4732 | @itemx (ge @var{arith1} @var{arith2}) | |
4733 | @itemx (geu @var{arith1} @var{arith2}) | |
4734 | @itemx (ne @var{arith1} @var{arith2}) | |
4735 | @itemx (eq @var{arith1} @var{arith2}) | |
4736 | These tests are true if the indicated comparison of the two arithmetic | |
4737 | expressions is true. Arithmetic expressions are formed with | |
4738 | @code{plus}, @code{minus}, @code{mult}, @code{div}, @code{mod}, | |
4739 | @code{abs}, @code{neg}, @code{and}, @code{ior}, @code{xor}, @code{not}, | |
bd819a4a | 4740 | @code{ashift}, @code{lshiftrt}, and @code{ashiftrt} expressions. |
03dda8e3 RK |
4741 | |
4742 | @findex get_attr | |
4743 | @code{const_int} and @code{symbol_ref} are always valid terms (@pxref{Insn | |
4744 | Lengths},for additional forms). @code{symbol_ref} is a string | |
4745 | denoting a C expression that yields an @code{int} when evaluated by the | |
4746 | @samp{get_attr_@dots{}} routine. It should normally be a global | |
bd819a4a | 4747 | variable. |
03dda8e3 RK |
4748 | |
4749 | @findex eq_attr | |
4750 | @item (eq_attr @var{name} @var{value}) | |
4751 | @var{name} is a string specifying the name of an attribute. | |
4752 | ||
4753 | @var{value} is a string that is either a valid value for attribute | |
4754 | @var{name}, a comma-separated list of values, or @samp{!} followed by a | |
4755 | value or list. If @var{value} does not begin with a @samp{!}, this | |
4756 | test is true if the value of the @var{name} attribute of the current | |
4757 | insn is in the list specified by @var{value}. If @var{value} begins | |
4758 | with a @samp{!}, this test is true if the attribute's value is | |
4759 | @emph{not} in the specified list. | |
4760 | ||
4761 | For example, | |
4762 | ||
4763 | @smallexample | |
4764 | (eq_attr "type" "load,store") | |
4765 | @end smallexample | |
4766 | ||
4767 | @noindent | |
4768 | is equivalent to | |
4769 | ||
4770 | @smallexample | |
4771 | (ior (eq_attr "type" "load") (eq_attr "type" "store")) | |
4772 | @end smallexample | |
4773 | ||
4774 | If @var{name} specifies an attribute of @samp{alternative}, it refers to the | |
4775 | value of the compiler variable @code{which_alternative} | |
4776 | (@pxref{Output Statement}) and the values must be small integers. For | |
bd819a4a | 4777 | example, |
03dda8e3 RK |
4778 | |
4779 | @smallexample | |
4780 | (eq_attr "alternative" "2,3") | |
4781 | @end smallexample | |
4782 | ||
4783 | @noindent | |
4784 | is equivalent to | |
4785 | ||
4786 | @smallexample | |
4787 | (ior (eq (symbol_ref "which_alternative") (const_int 2)) | |
4788 | (eq (symbol_ref "which_alternative") (const_int 3))) | |
4789 | @end smallexample | |
4790 | ||
4791 | Note that, for most attributes, an @code{eq_attr} test is simplified in cases | |
4792 | where the value of the attribute being tested is known for all insns matching | |
bd819a4a | 4793 | a particular pattern. This is by far the most common case. |
03dda8e3 RK |
4794 | |
4795 | @findex attr_flag | |
4796 | @item (attr_flag @var{name}) | |
4797 | The value of an @code{attr_flag} expression is true if the flag | |
4798 | specified by @var{name} is true for the @code{insn} currently being | |
4799 | scheduled. | |
4800 | ||
4801 | @var{name} is a string specifying one of a fixed set of flags to test. | |
4802 | Test the flags @code{forward} and @code{backward} to determine the | |
4803 | direction of a conditional branch. Test the flags @code{very_likely}, | |
4804 | @code{likely}, @code{very_unlikely}, and @code{unlikely} to determine | |
4805 | if a conditional branch is expected to be taken. | |
4806 | ||
4807 | If the @code{very_likely} flag is true, then the @code{likely} flag is also | |
4808 | true. Likewise for the @code{very_unlikely} and @code{unlikely} flags. | |
4809 | ||
4810 | This example describes a conditional branch delay slot which | |
4811 | can be nullified for forward branches that are taken (annul-true) or | |
4812 | for backward branches which are not taken (annul-false). | |
4813 | ||
4814 | @smallexample | |
4815 | (define_delay (eq_attr "type" "cbranch") | |
4816 | [(eq_attr "in_branch_delay" "true") | |
4817 | (and (eq_attr "in_branch_delay" "true") | |
4818 | (attr_flag "forward")) | |
4819 | (and (eq_attr "in_branch_delay" "true") | |
4820 | (attr_flag "backward"))]) | |
4821 | @end smallexample | |
4822 | ||
4823 | The @code{forward} and @code{backward} flags are false if the current | |
4824 | @code{insn} being scheduled is not a conditional branch. | |
4825 | ||
4826 | The @code{very_likely} and @code{likely} flags are true if the | |
4827 | @code{insn} being scheduled is not a conditional branch. | |
4828 | The @code{very_unlikely} and @code{unlikely} flags are false if the | |
4829 | @code{insn} being scheduled is not a conditional branch. | |
4830 | ||
4831 | @code{attr_flag} is only used during delay slot scheduling and has no | |
4832 | meaning to other passes of the compiler. | |
00bc45c1 RH |
4833 | |
4834 | @findex attr | |
4835 | @item (attr @var{name}) | |
4836 | The value of another attribute is returned. This is most useful | |
4837 | for numeric attributes, as @code{eq_attr} and @code{attr_flag} | |
4838 | produce more efficient code for non-numeric attributes. | |
03dda8e3 RK |
4839 | @end table |
4840 | ||
4841 | @node Tagging Insns | |
4842 | @subsection Assigning Attribute Values to Insns | |
4843 | @cindex tagging insns | |
4844 | @cindex assigning attribute values to insns | |
4845 | ||
4846 | The value assigned to an attribute of an insn is primarily determined by | |
4847 | which pattern is matched by that insn (or which @code{define_peephole} | |
4848 | generated it). Every @code{define_insn} and @code{define_peephole} can | |
4849 | have an optional last argument to specify the values of attributes for | |
4850 | matching insns. The value of any attribute not specified in a particular | |
4851 | insn is set to the default value for that attribute, as specified in its | |
4852 | @code{define_attr}. Extensive use of default values for attributes | |
4853 | permits the specification of the values for only one or two attributes | |
4854 | in the definition of most insn patterns, as seen in the example in the | |
bd819a4a | 4855 | next section. |
03dda8e3 RK |
4856 | |
4857 | The optional last argument of @code{define_insn} and | |
4858 | @code{define_peephole} is a vector of expressions, each of which defines | |
4859 | the value for a single attribute. The most general way of assigning an | |
4860 | attribute's value is to use a @code{set} expression whose first operand is an | |
4861 | @code{attr} expression giving the name of the attribute being set. The | |
4862 | second operand of the @code{set} is an attribute expression | |
bd819a4a | 4863 | (@pxref{Expressions}) giving the value of the attribute. |
03dda8e3 RK |
4864 | |
4865 | When the attribute value depends on the @samp{alternative} attribute | |
4866 | (i.e., which is the applicable alternative in the constraint of the | |
4867 | insn), the @code{set_attr_alternative} expression can be used. It | |
4868 | allows the specification of a vector of attribute expressions, one for | |
4869 | each alternative. | |
4870 | ||
4871 | @findex set_attr | |
4872 | When the generality of arbitrary attribute expressions is not required, | |
4873 | the simpler @code{set_attr} expression can be used, which allows | |
4874 | specifying a string giving either a single attribute value or a list | |
4875 | of attribute values, one for each alternative. | |
4876 | ||
4877 | The form of each of the above specifications is shown below. In each case, | |
4878 | @var{name} is a string specifying the attribute to be set. | |
4879 | ||
4880 | @table @code | |
4881 | @item (set_attr @var{name} @var{value-string}) | |
4882 | @var{value-string} is either a string giving the desired attribute value, | |
4883 | or a string containing a comma-separated list giving the values for | |
4884 | succeeding alternatives. The number of elements must match the number | |
4885 | of alternatives in the constraint of the insn pattern. | |
4886 | ||
4887 | Note that it may be useful to specify @samp{*} for some alternative, in | |
4888 | which case the attribute will assume its default value for insns matching | |
4889 | that alternative. | |
4890 | ||
4891 | @findex set_attr_alternative | |
4892 | @item (set_attr_alternative @var{name} [@var{value1} @var{value2} @dots{}]) | |
4893 | Depending on the alternative of the insn, the value will be one of the | |
4894 | specified values. This is a shorthand for using a @code{cond} with | |
4895 | tests on the @samp{alternative} attribute. | |
4896 | ||
4897 | @findex attr | |
4898 | @item (set (attr @var{name}) @var{value}) | |
4899 | The first operand of this @code{set} must be the special RTL expression | |
4900 | @code{attr}, whose sole operand is a string giving the name of the | |
4901 | attribute being set. @var{value} is the value of the attribute. | |
4902 | @end table | |
4903 | ||
4904 | The following shows three different ways of representing the same | |
4905 | attribute value specification: | |
4906 | ||
4907 | @smallexample | |
4908 | (set_attr "type" "load,store,arith") | |
4909 | ||
4910 | (set_attr_alternative "type" | |
4911 | [(const_string "load") (const_string "store") | |
4912 | (const_string "arith")]) | |
4913 | ||
4914 | (set (attr "type") | |
4915 | (cond [(eq_attr "alternative" "1") (const_string "load") | |
4916 | (eq_attr "alternative" "2") (const_string "store")] | |
4917 | (const_string "arith"))) | |
4918 | @end smallexample | |
4919 | ||
4920 | @need 1000 | |
4921 | @findex define_asm_attributes | |
4922 | The @code{define_asm_attributes} expression provides a mechanism to | |
4923 | specify the attributes assigned to insns produced from an @code{asm} | |
4924 | statement. It has the form: | |
4925 | ||
4926 | @smallexample | |
4927 | (define_asm_attributes [@var{attr-sets}]) | |
4928 | @end smallexample | |
4929 | ||
4930 | @noindent | |
4931 | where @var{attr-sets} is specified the same as for both the | |
4932 | @code{define_insn} and the @code{define_peephole} expressions. | |
4933 | ||
4934 | These values will typically be the ``worst case'' attribute values. For | |
4935 | example, they might indicate that the condition code will be clobbered. | |
4936 | ||
4937 | A specification for a @code{length} attribute is handled specially. The | |
4938 | way to compute the length of an @code{asm} insn is to multiply the | |
4939 | length specified in the expression @code{define_asm_attributes} by the | |
4940 | number of machine instructions specified in the @code{asm} statement, | |
4941 | determined by counting the number of semicolons and newlines in the | |
4942 | string. Therefore, the value of the @code{length} attribute specified | |
4943 | in a @code{define_asm_attributes} should be the maximum possible length | |
4944 | of a single machine instruction. | |
4945 | ||
4946 | @node Attr Example | |
4947 | @subsection Example of Attribute Specifications | |
4948 | @cindex attribute specifications example | |
4949 | @cindex attribute specifications | |
4950 | ||
4951 | The judicious use of defaulting is important in the efficient use of | |
4952 | insn attributes. Typically, insns are divided into @dfn{types} and an | |
4953 | attribute, customarily called @code{type}, is used to represent this | |
4954 | value. This attribute is normally used only to define the default value | |
4955 | for other attributes. An example will clarify this usage. | |
4956 | ||
4957 | Assume we have a RISC machine with a condition code and in which only | |
4958 | full-word operations are performed in registers. Let us assume that we | |
4959 | can divide all insns into loads, stores, (integer) arithmetic | |
4960 | operations, floating point operations, and branches. | |
4961 | ||
4962 | Here we will concern ourselves with determining the effect of an insn on | |
4963 | the condition code and will limit ourselves to the following possible | |
4964 | effects: The condition code can be set unpredictably (clobbered), not | |
4965 | be changed, be set to agree with the results of the operation, or only | |
4966 | changed if the item previously set into the condition code has been | |
4967 | modified. | |
4968 | ||
4969 | Here is part of a sample @file{md} file for such a machine: | |
4970 | ||
4971 | @smallexample | |
4972 | (define_attr "type" "load,store,arith,fp,branch" (const_string "arith")) | |
4973 | ||
4974 | (define_attr "cc" "clobber,unchanged,set,change0" | |
4975 | (cond [(eq_attr "type" "load") | |
4976 | (const_string "change0") | |
4977 | (eq_attr "type" "store,branch") | |
4978 | (const_string "unchanged") | |
4979 | (eq_attr "type" "arith") | |
4980 | (if_then_else (match_operand:SI 0 "" "") | |
4981 | (const_string "set") | |
4982 | (const_string "clobber"))] | |
4983 | (const_string "clobber"))) | |
4984 | ||
4985 | (define_insn "" | |
4986 | [(set (match_operand:SI 0 "general_operand" "=r,r,m") | |
4987 | (match_operand:SI 1 "general_operand" "r,m,r"))] | |
4988 | "" | |
4989 | "@@ | |
4990 | move %0,%1 | |
4991 | load %0,%1 | |
4992 | store %0,%1" | |
4993 | [(set_attr "type" "arith,load,store")]) | |
4994 | @end smallexample | |
4995 | ||
4996 | Note that we assume in the above example that arithmetic operations | |
4997 | performed on quantities smaller than a machine word clobber the condition | |
4998 | code since they will set the condition code to a value corresponding to the | |
4999 | full-word result. | |
5000 | ||
5001 | @node Insn Lengths | |
5002 | @subsection Computing the Length of an Insn | |
5003 | @cindex insn lengths, computing | |
5004 | @cindex computing the length of an insn | |
5005 | ||
5006 | For many machines, multiple types of branch instructions are provided, each | |
5007 | for different length branch displacements. In most cases, the assembler | |
5008 | will choose the correct instruction to use. However, when the assembler | |
5009 | cannot do so, GCC can when a special attribute, the @samp{length} | |
5010 | attribute, is defined. This attribute must be defined to have numeric | |
5011 | values by specifying a null string in its @code{define_attr}. | |
5012 | ||
5013 | In the case of the @samp{length} attribute, two additional forms of | |
5014 | arithmetic terms are allowed in test expressions: | |
5015 | ||
5016 | @table @code | |
5017 | @cindex @code{match_dup} and attributes | |
5018 | @item (match_dup @var{n}) | |
5019 | This refers to the address of operand @var{n} of the current insn, which | |
5020 | must be a @code{label_ref}. | |
5021 | ||
5022 | @cindex @code{pc} and attributes | |
5023 | @item (pc) | |
5024 | This refers to the address of the @emph{current} insn. It might have | |
5025 | been more consistent with other usage to make this the address of the | |
5026 | @emph{next} insn but this would be confusing because the length of the | |
5027 | current insn is to be computed. | |
5028 | @end table | |
5029 | ||
5030 | @cindex @code{addr_vec}, length of | |
5031 | @cindex @code{addr_diff_vec}, length of | |
5032 | For normal insns, the length will be determined by value of the | |
5033 | @samp{length} attribute. In the case of @code{addr_vec} and | |
5034 | @code{addr_diff_vec} insn patterns, the length is computed as | |
5035 | the number of vectors multiplied by the size of each vector. | |
5036 | ||
5037 | Lengths are measured in addressable storage units (bytes). | |
5038 | ||
5039 | The following macros can be used to refine the length computation: | |
5040 | ||
5041 | @table @code | |
5042 | @findex FIRST_INSN_ADDRESS | |
5043 | @item FIRST_INSN_ADDRESS | |
5044 | When the @code{length} insn attribute is used, this macro specifies the | |
5045 | value to be assigned to the address of the first insn in a function. If | |
5046 | not specified, 0 is used. | |
5047 | ||
5048 | @findex ADJUST_INSN_LENGTH | |
5049 | @item ADJUST_INSN_LENGTH (@var{insn}, @var{length}) | |
5050 | If defined, modifies the length assigned to instruction @var{insn} as a | |
5051 | function of the context in which it is used. @var{length} is an lvalue | |
5052 | that contains the initially computed length of the insn and should be | |
a8aa4e0b | 5053 | updated with the correct length of the insn. |
03dda8e3 RK |
5054 | |
5055 | This macro will normally not be required. A case in which it is | |
161d7b59 | 5056 | required is the ROMP@. On this machine, the size of an @code{addr_vec} |
03dda8e3 RK |
5057 | insn must be increased by two to compensate for the fact that alignment |
5058 | may be required. | |
5059 | @end table | |
5060 | ||
5061 | @findex get_attr_length | |
5062 | The routine that returns @code{get_attr_length} (the value of the | |
5063 | @code{length} attribute) can be used by the output routine to | |
5064 | determine the form of the branch instruction to be written, as the | |
5065 | example below illustrates. | |
5066 | ||
5067 | As an example of the specification of variable-length branches, consider | |
5068 | the IBM 360. If we adopt the convention that a register will be set to | |
5069 | the starting address of a function, we can jump to labels within 4k of | |
5070 | the start using a four-byte instruction. Otherwise, we need a six-byte | |
5071 | sequence to load the address from memory and then branch to it. | |
5072 | ||
5073 | On such a machine, a pattern for a branch instruction might be specified | |
5074 | as follows: | |
5075 | ||
5076 | @smallexample | |
5077 | (define_insn "jump" | |
5078 | [(set (pc) | |
5079 | (label_ref (match_operand 0 "" "")))] | |
5080 | "" | |
03dda8e3 RK |
5081 | @{ |
5082 | return (get_attr_length (insn) == 4 | |
0f40f9f7 ZW |
5083 | ? "b %l0" : "l r15,=a(%l0); br r15"); |
5084 | @} | |
9c34dbbf ZW |
5085 | [(set (attr "length") |
5086 | (if_then_else (lt (match_dup 0) (const_int 4096)) | |
5087 | (const_int 4) | |
5088 | (const_int 6)))]) | |
03dda8e3 RK |
5089 | @end smallexample |
5090 | ||
5091 | @node Constant Attributes | |
5092 | @subsection Constant Attributes | |
5093 | @cindex constant attributes | |
5094 | ||
5095 | A special form of @code{define_attr}, where the expression for the | |
5096 | default value is a @code{const} expression, indicates an attribute that | |
5097 | is constant for a given run of the compiler. Constant attributes may be | |
5098 | used to specify which variety of processor is used. For example, | |
5099 | ||
5100 | @smallexample | |
5101 | (define_attr "cpu" "m88100,m88110,m88000" | |
5102 | (const | |
5103 | (cond [(symbol_ref "TARGET_88100") (const_string "m88100") | |
5104 | (symbol_ref "TARGET_88110") (const_string "m88110")] | |
5105 | (const_string "m88000")))) | |
5106 | ||
5107 | (define_attr "memory" "fast,slow" | |
5108 | (const | |
5109 | (if_then_else (symbol_ref "TARGET_FAST_MEM") | |
5110 | (const_string "fast") | |
5111 | (const_string "slow")))) | |
5112 | @end smallexample | |
5113 | ||
5114 | The routine generated for constant attributes has no parameters as it | |
5115 | does not depend on any particular insn. RTL expressions used to define | |
5116 | the value of a constant attribute may use the @code{symbol_ref} form, | |
5117 | but may not use either the @code{match_operand} form or @code{eq_attr} | |
5118 | forms involving insn attributes. | |
5119 | ||
5120 | @node Delay Slots | |
5121 | @subsection Delay Slot Scheduling | |
5122 | @cindex delay slots, defining | |
5123 | ||
5124 | The insn attribute mechanism can be used to specify the requirements for | |
5125 | delay slots, if any, on a target machine. An instruction is said to | |
5126 | require a @dfn{delay slot} if some instructions that are physically | |
5127 | after the instruction are executed as if they were located before it. | |
5128 | Classic examples are branch and call instructions, which often execute | |
5129 | the following instruction before the branch or call is performed. | |
5130 | ||
5131 | On some machines, conditional branch instructions can optionally | |
5132 | @dfn{annul} instructions in the delay slot. This means that the | |
5133 | instruction will not be executed for certain branch outcomes. Both | |
5134 | instructions that annul if the branch is true and instructions that | |
5135 | annul if the branch is false are supported. | |
5136 | ||
5137 | Delay slot scheduling differs from instruction scheduling in that | |
5138 | determining whether an instruction needs a delay slot is dependent only | |
5139 | on the type of instruction being generated, not on data flow between the | |
5140 | instructions. See the next section for a discussion of data-dependent | |
5141 | instruction scheduling. | |
5142 | ||
5143 | @findex define_delay | |
5144 | The requirement of an insn needing one or more delay slots is indicated | |
5145 | via the @code{define_delay} expression. It has the following form: | |
5146 | ||
5147 | @smallexample | |
5148 | (define_delay @var{test} | |
5149 | [@var{delay-1} @var{annul-true-1} @var{annul-false-1} | |
5150 | @var{delay-2} @var{annul-true-2} @var{annul-false-2} | |
5151 | @dots{}]) | |
5152 | @end smallexample | |
5153 | ||
5154 | @var{test} is an attribute test that indicates whether this | |
5155 | @code{define_delay} applies to a particular insn. If so, the number of | |
5156 | required delay slots is determined by the length of the vector specified | |
5157 | as the second argument. An insn placed in delay slot @var{n} must | |
5158 | satisfy attribute test @var{delay-n}. @var{annul-true-n} is an | |
5159 | attribute test that specifies which insns may be annulled if the branch | |
5160 | is true. Similarly, @var{annul-false-n} specifies which insns in the | |
5161 | delay slot may be annulled if the branch is false. If annulling is not | |
bd819a4a | 5162 | supported for that delay slot, @code{(nil)} should be coded. |
03dda8e3 RK |
5163 | |
5164 | For example, in the common case where branch and call insns require | |
5165 | a single delay slot, which may contain any insn other than a branch or | |
5166 | call, the following would be placed in the @file{md} file: | |
5167 | ||
5168 | @smallexample | |
5169 | (define_delay (eq_attr "type" "branch,call") | |
5170 | [(eq_attr "type" "!branch,call") (nil) (nil)]) | |
5171 | @end smallexample | |
5172 | ||
5173 | Multiple @code{define_delay} expressions may be specified. In this | |
5174 | case, each such expression specifies different delay slot requirements | |
5175 | and there must be no insn for which tests in two @code{define_delay} | |
5176 | expressions are both true. | |
5177 | ||
5178 | For example, if we have a machine that requires one delay slot for branches | |
5179 | but two for calls, no delay slot can contain a branch or call insn, | |
5180 | and any valid insn in the delay slot for the branch can be annulled if the | |
5181 | branch is true, we might represent this as follows: | |
5182 | ||
5183 | @smallexample | |
5184 | (define_delay (eq_attr "type" "branch") | |
5185 | [(eq_attr "type" "!branch,call") | |
5186 | (eq_attr "type" "!branch,call") | |
5187 | (nil)]) | |
5188 | ||
5189 | (define_delay (eq_attr "type" "call") | |
5190 | [(eq_attr "type" "!branch,call") (nil) (nil) | |
5191 | (eq_attr "type" "!branch,call") (nil) (nil)]) | |
5192 | @end smallexample | |
5193 | @c the above is *still* too long. --mew 4feb93 | |
5194 | ||
fae15c93 VM |
5195 | @node Processor pipeline description |
5196 | @subsection Specifying processor pipeline description | |
5197 | @cindex processor pipeline description | |
5198 | @cindex processor functional units | |
5199 | @cindex instruction latency time | |
5200 | @cindex interlock delays | |
5201 | @cindex data dependence delays | |
5202 | @cindex reservation delays | |
5203 | @cindex pipeline hazard recognizer | |
5204 | @cindex automaton based pipeline description | |
5205 | @cindex regular expressions | |
5206 | @cindex deterministic finite state automaton | |
5207 | @cindex automaton based scheduler | |
5208 | @cindex RISC | |
5209 | @cindex VLIW | |
5210 | ||
5211 | To achieve better productivity most modern processors | |
5212 | (super-pipelined, superscalar @acronym{RISC}, and @acronym{VLIW} | |
5213 | processors) have many @dfn{functional units} on which several | |
5214 | instructions can be executed simultaneously. An instruction starts | |
5215 | execution if its issue conditions are satisfied. If not, the | |
5216 | instruction is interlocked until its conditions are satisfied. Such | |
5217 | @dfn{interlock (pipeline) delay} causes interruption of the fetching | |
5218 | of successor instructions (or demands nop instructions, e.g. for some | |
5219 | MIPS processors). | |
5220 | ||
5221 | There are two major kinds of interlock delays in modern processors. | |
5222 | The first one is a data dependence delay determining @dfn{instruction | |
5223 | latency time}. The instruction execution is not started until all | |
5224 | source data have been evaluated by prior instructions (there are more | |
5225 | complex cases when the instruction execution starts even when the data | |
5226 | are not availaible but will be ready in given time after the | |
5227 | instruction execution start). Taking the data dependence delays into | |
5228 | account is simple. The data dependence (true, output, and | |
5229 | anti-dependence) delay between two instructions is given by a | |
5230 | constant. In most cases this approach is adequate. The second kind | |
5231 | of interlock delays is a reservation delay. The reservation delay | |
5232 | means that two instructions under execution will be in need of shared | |
5233 | processors resources, i.e. buses, internal registers, and/or | |
5234 | functional units, which are reserved for some time. Taking this kind | |
5235 | of delay into account is complex especially for modern @acronym{RISC} | |
5236 | processors. | |
5237 | ||
5238 | The task of exploiting more processor parallelism is solved by an | |
5239 | instruction scheduler. For better solution of this problem, the | |
5240 | instruction scheduler has to have an adequate description of the | |
5241 | processor parallelism (or @dfn{pipeline description}). Currently GCC | |
5242 | has two ways to describe processor parallelism. The first one is old | |
5243 | and originated from instruction scheduler written by Michael Tiemann | |
5244 | and described in the first subsequent section. The second one was | |
5245 | created later. It is based on description of functional unit | |
5246 | reservations by processor instructions with the aid of @dfn{regular | |
5247 | expressions}. This is so called @dfn{automaton based description}. | |
5248 | ||
5249 | Gcc instruction scheduler uses a @dfn{pipeline hazard recognizer} to | |
5250 | figure out the possibility of the instruction issue by the processor | |
5251 | on given simulated processor cycle. The pipeline hazard recognizer is | |
5252 | a code generated from the processor pipeline description. The | |
5253 | pipeline hazard recognizer generated from the automaton based | |
5254 | description is more sophisticated and based on deterministic finite | |
5255 | state automaton (@acronym{DFA}) and therefore faster than one | |
5256 | generated from the old description. Also its speed is not depended on | |
5257 | processor complexity. The instruction issue is possible if there is | |
5258 | a transition from one automaton state to another one. | |
5259 | ||
5260 | You can use any model to describe processor pipeline characteristics | |
5261 | or even a mix of them. You could use the old description for some | |
5262 | processor submodels and the @acronym{DFA}-based one for the rest | |
5263 | processor submodels. | |
5264 | ||
5265 | In general, the usage of the automaton based description is more | |
5266 | preferable. Its model is more rich. It permits to describe more | |
5267 | accurately pipeline characteristics of processors which results in | |
5268 | improving code quality (although sometimes only on several percent | |
5269 | fractions). It will be also used as an infrastructure to implement | |
5270 | sophisticated and practical insn scheduling which will try many | |
5271 | instruction sequences to choose the best one. | |
5272 | ||
5273 | ||
5274 | @menu | |
5275 | * Old pipeline description:: Specifying information for insn scheduling. | |
5276 | * Automaton pipeline description:: Describing insn pipeline characteristics. | |
5277 | * Comparison of the two descriptions:: Drawbacks of the old pipeline description | |
5278 | @end menu | |
5279 | ||
5280 | @node Old pipeline description | |
5281 | @subsubsection Specifying Function Units | |
5282 | @cindex old pipeline description | |
03dda8e3 RK |
5283 | @cindex function units, for scheduling |
5284 | ||
fae15c93 VM |
5285 | On most @acronym{RISC} machines, there are instructions whose results |
5286 | are not available for a specific number of cycles. Common cases are | |
5287 | instructions that load data from memory. On many machines, a pipeline | |
5288 | stall will result if the data is referenced too soon after the load | |
5289 | instruction. | |
03dda8e3 RK |
5290 | |
5291 | In addition, many newer microprocessors have multiple function units, usually | |
5292 | one for integer and one for floating point, and often will incur pipeline | |
5293 | stalls when a result that is needed is not yet ready. | |
5294 | ||
5295 | The descriptions in this section allow the specification of how much | |
5296 | time must elapse between the execution of an instruction and the time | |
5297 | when its result is used. It also allows specification of when the | |
5298 | execution of an instruction will delay execution of similar instructions | |
5299 | due to function unit conflicts. | |
5300 | ||
5301 | For the purposes of the specifications in this section, a machine is | |
5302 | divided into @dfn{function units}, each of which execute a specific | |
fae15c93 VM |
5303 | class of instructions in first-in-first-out order. Function units |
5304 | that accept one instruction each cycle and allow a result to be used | |
5305 | in the succeeding instruction (usually via forwarding) need not be | |
5306 | specified. Classic @acronym{RISC} microprocessors will normally have | |
5307 | a single function unit, which we can call @samp{memory}. The newer | |
5308 | ``superscalar'' processors will often have function units for floating | |
5309 | point operations, usually at least a floating point adder and | |
5310 | multiplier. | |
03dda8e3 RK |
5311 | |
5312 | @findex define_function_unit | |
5313 | Each usage of a function units by a class of insns is specified with a | |
5314 | @code{define_function_unit} expression, which looks like this: | |
5315 | ||
5316 | @smallexample | |
5317 | (define_function_unit @var{name} @var{multiplicity} @var{simultaneity} | |
5318 | @var{test} @var{ready-delay} @var{issue-delay} | |
5319 | [@var{conflict-list}]) | |
5320 | @end smallexample | |
5321 | ||
5322 | @var{name} is a string giving the name of the function unit. | |
5323 | ||
5324 | @var{multiplicity} is an integer specifying the number of identical | |
5325 | units in the processor. If more than one unit is specified, they will | |
5326 | be scheduled independently. Only truly independent units should be | |
5327 | counted; a pipelined unit should be specified as a single unit. (The | |
5328 | only common example of a machine that has multiple function units for a | |
5329 | single instruction class that are truly independent and not pipelined | |
5330 | are the two multiply and two increment units of the CDC 6600.) | |
5331 | ||
5332 | @var{simultaneity} specifies the maximum number of insns that can be | |
5333 | executing in each instance of the function unit simultaneously or zero | |
5334 | if the unit is pipelined and has no limit. | |
5335 | ||
5336 | All @code{define_function_unit} definitions referring to function unit | |
5337 | @var{name} must have the same name and values for @var{multiplicity} and | |
5338 | @var{simultaneity}. | |
5339 | ||
5340 | @var{test} is an attribute test that selects the insns we are describing | |
5341 | in this definition. Note that an insn may use more than one function | |
5342 | unit and a function unit may be specified in more than one | |
5343 | @code{define_function_unit}. | |
5344 | ||
5345 | @var{ready-delay} is an integer that specifies the number of cycles | |
5346 | after which the result of the instruction can be used without | |
5347 | introducing any stalls. | |
5348 | ||
5349 | @var{issue-delay} is an integer that specifies the number of cycles | |
5350 | after the instruction matching the @var{test} expression begins using | |
5351 | this unit until a subsequent instruction can begin. A cost of @var{N} | |
5352 | indicates an @var{N-1} cycle delay. A subsequent instruction may also | |
5353 | be delayed if an earlier instruction has a longer @var{ready-delay} | |
5354 | value. This blocking effect is computed using the @var{simultaneity}, | |
5355 | @var{ready-delay}, @var{issue-delay}, and @var{conflict-list} terms. | |
5356 | For a normal non-pipelined function unit, @var{simultaneity} is one, the | |
5357 | unit is taken to block for the @var{ready-delay} cycles of the executing | |
5358 | insn, and smaller values of @var{issue-delay} are ignored. | |
5359 | ||
5360 | @var{conflict-list} is an optional list giving detailed conflict costs | |
5361 | for this unit. If specified, it is a list of condition test expressions | |
5362 | to be applied to insns chosen to execute in @var{name} following the | |
5363 | particular insn matching @var{test} that is already executing in | |
5364 | @var{name}. For each insn in the list, @var{issue-delay} specifies the | |
5365 | conflict cost; for insns not in the list, the cost is zero. If not | |
5366 | specified, @var{conflict-list} defaults to all instructions that use the | |
5367 | function unit. | |
5368 | ||
5369 | Typical uses of this vector are where a floating point function unit can | |
5370 | pipeline either single- or double-precision operations, but not both, or | |
5371 | where a memory unit can pipeline loads, but not stores, etc. | |
5372 | ||
fae15c93 VM |
5373 | As an example, consider a classic @acronym{RISC} machine where the |
5374 | result of a load instruction is not available for two cycles (a single | |
5375 | ``delay'' instruction is required) and where only one load instruction | |
5376 | can be executed simultaneously. This would be specified as: | |
03dda8e3 RK |
5377 | |
5378 | @smallexample | |
5379 | (define_function_unit "memory" 1 1 (eq_attr "type" "load") 2 0) | |
5380 | @end smallexample | |
5381 | ||
5382 | For the case of a floating point function unit that can pipeline either | |
5383 | single or double precision, but not both, the following could be specified: | |
5384 | ||
5385 | @smallexample | |
5386 | (define_function_unit | |
5387 | "fp" 1 0 (eq_attr "type" "sp_fp") 4 4 [(eq_attr "type" "dp_fp")]) | |
5388 | (define_function_unit | |
5389 | "fp" 1 0 (eq_attr "type" "dp_fp") 4 4 [(eq_attr "type" "sp_fp")]) | |
5390 | @end smallexample | |
5391 | ||
5392 | @strong{Note:} The scheduler attempts to avoid function unit conflicts | |
5393 | and uses all the specifications in the @code{define_function_unit} | |
5394 | expression. It has recently come to our attention that these | |
5395 | specifications may not allow modeling of some of the newer | |
5396 | ``superscalar'' processors that have insns using multiple pipelined | |
5397 | units. These insns will cause a potential conflict for the second unit | |
5398 | used during their execution and there is no way of representing that | |
5399 | conflict. We welcome any examples of how function unit conflicts work | |
5400 | in such processors and suggestions for their representation. | |
3262c1f5 | 5401 | |
fae15c93 VM |
5402 | @node Automaton pipeline description |
5403 | @subsubsection Describing instruction pipeline characteristics | |
5404 | @cindex automaton based pipeline description | |
5405 | ||
5406 | This section describes constructions of the automaton based processor | |
5407 | pipeline description. The order of all mentioned below constructions | |
5408 | in the machine description file is not important. | |
5409 | ||
5410 | @findex define_automaton | |
5411 | @cindex pipeline hazard recognizer | |
5412 | The following optional construction describes names of automata | |
5413 | generated and used for the pipeline hazards recognition. Sometimes | |
5414 | the generated finite state automaton used by the pipeline hazard | |
5415 | recognizer is large. If we use more one automaton and bind functional | |
5416 | units to the automata, the summary size of the automata usually is | |
5417 | less than the size of the single automaton. If there is no one such | |
5418 | construction, only one finite state automaton is generated. | |
5419 | ||
5420 | @smallexample | |
5421 | (define_automaton @var{automata-names}) | |
5422 | @end smallexample | |
5423 | ||
5424 | @var{automata-names} is a string giving names of the automata. The | |
5425 | names are separated by commas. All the automata should have unique names. | |
5426 | The automaton name is used in construction @code{define_cpu_unit} and | |
5427 | @code{define_query_cpu_unit}. | |
5428 | ||
5429 | @findex define_cpu_unit | |
5430 | @cindex processor functional units | |
5431 | Each processor functional unit used in description of instruction | |
5432 | reservations should be described by the following construction. | |
5433 | ||
5434 | @smallexample | |
5435 | (define_cpu_unit @var{unit-names} [@var{automaton-name}]) | |
5436 | @end smallexample | |
5437 | ||
5438 | @var{unit-names} is a string giving the names of the functional units | |
5439 | separated by commas. Don't use name @samp{nothing}, it is reserved | |
5440 | for other goals. | |
5441 | ||
5442 | @var{automaton-name} is a string giving the name of automaton with | |
5443 | which the unit is bound. The automaton should be described in | |
5444 | construction @code{define_automaton}. You should give | |
5445 | @dfn{automaton-name}, if there is a defined automaton. | |
5446 | ||
5447 | @findex define_query_cpu_unit | |
5448 | @cindex querying function unit reservations | |
5449 | The following construction describes CPU functional units analogously | |
5450 | to @code{define_cpu_unit}. If we use automata without their | |
5451 | minimization, the reservation of such units can be queried for an | |
5452 | automaton state. The instruction scheduler never queries reservation | |
5453 | of functional units for given automaton state. So as a rule, you | |
5454 | don't need this construction. This construction could be used for | |
5455 | future code generation goals (e.g. to generate @acronym{VLIW} insn | |
5456 | templates). | |
5457 | ||
5458 | @smallexample | |
5459 | (define_query_cpu_unit @var{unit-names} [@var{automaton-name}]) | |
5460 | @end smallexample | |
5461 | ||
5462 | @var{unit-names} is a string giving names of the functional units | |
5463 | separated by commas. | |
5464 | ||
5465 | @var{automaton-name} is a string giving name of the automaton with | |
5466 | which the unit is bound. | |
5467 | ||
5468 | @findex define_insn_reservation | |
5469 | @cindex instruction latency time | |
5470 | @cindex regular expressions | |
5471 | @cindex data bypass | |
5472 | The following construction is major one to describe pipeline | |
5473 | characteristics of an instruction. | |
5474 | ||
5475 | @smallexample | |
5476 | (define_insn_reservation @var{insn-name} @var{default_latency} | |
5477 | @var{condition} @var{regexp}) | |
5478 | @end smallexample | |
5479 | ||
5480 | @var{default_latency} is a number giving latency time of the | |
5481 | instruction. There is an important difference between the old | |
5482 | description and the automaton based pipeline description. The latency | |
5483 | time is used for all dependencies when we use the old description. In | |
5484 | the automaton based pipeline description, given latency time is used | |
5485 | only for true dependencies. The cost of anti-dependencies is always | |
5486 | zero and the cost of output dependencies is the difference between | |
5487 | latency times of the producing and consuming insns (if the difference | |
5488 | is negative, the cost is considered to be zero). You always can | |
5489 | change the default costs for any description by using target hook | |
5490 | @code{TARGET_SCHED_ADJUST_COST} (@pxref{Scheduling}). | |
5491 | ||
5492 | @var{insn-names} is a string giving internal name of the insn. The | |
5493 | internal names are used in constructions @code{define_bypass} and in | |
5494 | the automaton description file generated for debugging. The internal | |
5495 | name has nothing common with the names in @code{define_insn}. It is a | |
5496 | good practice to use insn classes described in the processor manual. | |
5497 | ||
5498 | @var{condition} defines what RTL insns are described by this | |
5499 | construction. You should remember that you will be in trouble if | |
5500 | @var{condition} for two or more different | |
5501 | @code{define_insn_reservation} constructions is TRUE for an insn. In | |
5502 | this case what reservation will be used for the insn is not defined. | |
5503 | Such cases are not checked during generation of the pipeline hazards | |
5504 | recognizer because in general recognizing that two conditions may have | |
5505 | the same value is quite difficult (especially if the conditions | |
5506 | contain @code{symbol_ref}). It is also not checked during the | |
5507 | pipeline hazard recognizer work because it would slow down the | |
5508 | recognizer considerably. | |
5509 | ||
5510 | @var{regexp} is a string describing reservation of the cpu functional | |
5511 | units by the instruction. The reservations are described by a regular | |
5512 | expression according to the following syntax: | |
5513 | ||
5514 | @smallexample | |
5515 | regexp = regexp "," oneof | |
5516 | | oneof | |
5517 | ||
5518 | oneof = oneof "|" allof | |
5519 | | allof | |
5520 | ||
5521 | allof = allof "+" repeat | |
5522 | | repeat | |
5523 | ||
5524 | repeat = element "*" number | |
5525 | | element | |
5526 | ||
5527 | element = cpu_function_unit_name | |
5528 | | reservation_name | |
5529 | | result_name | |
5530 | | "nothing" | |
5531 | | "(" regexp ")" | |
5532 | @end smallexample | |
5533 | ||
5534 | @itemize @bullet | |
5535 | @item | |
5536 | @samp{,} is used for describing the start of the next cycle in | |
5537 | the reservation. | |
5538 | ||
5539 | @item | |
5540 | @samp{|} is used for describing a reservation described by the first | |
5541 | regular expression @strong{or} a reservation described by the second | |
5542 | regular expression @strong{or} etc. | |
5543 | ||
5544 | @item | |
5545 | @samp{+} is used for describing a reservation described by the first | |
5546 | regular expression @strong{and} a reservation described by the | |
5547 | second regular expression @strong{and} etc. | |
5548 | ||
5549 | @item | |
5550 | @samp{*} is used for convenience and simply means a sequence in which | |
5551 | the regular expression are repeated @var{number} times with cycle | |
5552 | advancing (see @samp{,}). | |
5553 | ||
5554 | @item | |
5555 | @samp{cpu_function_unit_name} denotes reservation of the named | |
5556 | functional unit. | |
5557 | ||
5558 | @item | |
5559 | @samp{reservation_name} --- see description of construction | |
5560 | @samp{define_reservation}. | |
5561 | ||
5562 | @item | |
5563 | @samp{nothing} denotes no unit reservations. | |
5564 | @end itemize | |
5565 | ||
5566 | @findex define_reservation | |
5567 | Sometimes unit reservations for different insns contain common parts. | |
5568 | In such case, you can simplify the pipeline description by describing | |
5569 | the common part by the following construction | |
5570 | ||
5571 | @smallexample | |
5572 | (define_reservation @var{reservation-name} @var{regexp}) | |
5573 | @end smallexample | |
5574 | ||
5575 | @var{reservation-name} is a string giving name of @var{regexp}. | |
5576 | Functional unit names and reservation names are in the same name | |
5577 | space. So the reservation names should be different from the | |
5578 | functional unit names and can not be reserved name @samp{nothing}. | |
5579 | ||
5580 | @findex define_bypass | |
5581 | @cindex instruction latency time | |
5582 | @cindex data bypass | |
5583 | The following construction is used to describe exceptions in the | |
5584 | latency time for given instruction pair. This is so called bypasses. | |
5585 | ||
5586 | @smallexample | |
5587 | (define_bypass @var{number} @var{out_insn_names} @var{in_insn_names} | |
5588 | [@var{guard}]) | |
5589 | @end smallexample | |
5590 | ||
5591 | @var{number} defines when the result generated by the instructions | |
5592 | given in string @var{out_insn_names} will be ready for the | |
5593 | instructions given in string @var{in_insn_names}. The instructions in | |
5594 | the string are separated by commas. | |
5595 | ||
5596 | @var{guard} is an optional string giving name of a C function which | |
5597 | defines an additional guard for the bypass. The function will get the | |
5598 | two insns as parameters. If the function returns zero the bypass will | |
5599 | be ignored for this case. The additional guard is necessary to | |
5600 | recognize complicated bypasses, e.g. when consumer is only an address | |
5601 | of insn @samp{store} (not a stored value). | |
5602 | ||
5603 | @findex exclusion_set | |
5604 | @findex presence_set | |
5605 | @findex absence_set | |
5606 | @cindex VLIW | |
5607 | @cindex RISC | |
5608 | Usually the following three constructions are used to describe | |
5609 | @acronym{VLIW} processors (more correctly to describe a placement of | |
5610 | small insns into @acronym{VLIW} insn slots). Although they can be | |
5611 | used for @acronym{RISC} processors too. | |
5612 | ||
5613 | @smallexample | |
5614 | (exclusion_set @var{unit-names} @var{unit-names}) | |
5615 | (presence_set @var{unit-names} @var{unit-names}) | |
5616 | (absence_set @var{unit-names} @var{unit-names}) | |
5617 | @end smallexample | |
5618 | ||
5619 | @var{unit-names} is a string giving names of functional units | |
5620 | separated by commas. | |
5621 | ||
5622 | The first construction (@samp{exclusion_set}) means that each | |
5623 | functional unit in the first string can not be reserved simultaneously | |
5624 | with a unit whose name is in the second string and vice versa. For | |
5625 | example, the construction is useful for describing processors | |
5626 | (e.g. some SPARC processors) with a fully pipelined floating point | |
5627 | functional unit which can execute simultaneously only single floating | |
5628 | point insns or only double floating point insns. | |
5629 | ||
5630 | The second construction (@samp{presence_set}) means that each | |
5631 | functional unit in the first string can not be reserved unless at | |
5632 | least one of units whose names are in the second string is reserved. | |
5633 | This is an asymmetric relation. For example, it is useful for | |
5634 | description that @acronym{VLIW} @samp{slot1} is reserved after | |
5635 | @samp{slot0} reservation. | |
5636 | ||
5637 | The third construction (@samp{absence_set}) means that each functional | |
5638 | unit in the first string can be reserved only if each unit whose name | |
5639 | is in the second string is not reserved. This is an asymmetric | |
5640 | relation (actually @samp{exclusion_set} is analogous to this one but | |
5641 | it is symmetric). For example, it is useful for description that | |
5642 | @acronym{VLIW} @samp{slot0} can not be reserved after @samp{slot1} or | |
5643 | @samp{slot2} reservation. | |
5644 | ||
5645 | All functional units mentioned in a set should belong the same | |
5646 | automaton. | |
5647 | ||
5648 | @findex automata_option | |
5649 | @cindex deterministic finite state automaton | |
5650 | @cindex nondeterministic finite state automaton | |
5651 | @cindex finite state automaton minimization | |
5652 | You can control the generator of the pipeline hazard recognizer with | |
5653 | the following construction. | |
5654 | ||
5655 | @smallexample | |
5656 | (automata_option @var{options}) | |
5657 | @end smallexample | |
5658 | ||
5659 | @var{options} is a string giving options which affect the generated | |
5660 | code. Currently there are the following options: | |
5661 | ||
5662 | @itemize @bullet | |
5663 | @item | |
5664 | @dfn{no-minimization} makes no minimization of the automaton. This is | |
5665 | only worth to do when we are going to query CPU functional unit | |
5666 | reservations in an automaton state. | |
5667 | ||
5668 | @item | |
e3c8eb86 VM |
5669 | @dfn{time} means printing additional time statistics about |
5670 | generation of automata. | |
5671 | ||
5672 | @item | |
5673 | @dfn{v} means a generation of the file describing the result automata. | |
5674 | The file has suffix @samp{.dfa} and can be used for the description | |
5675 | verification and debugging. | |
5676 | ||
5677 | @item | |
5678 | @dfn{w} means a generation of warning instead of error for | |
5679 | non-critical errors. | |
fae15c93 VM |
5680 | |
5681 | @item | |
5682 | @dfn{ndfa} makes nondeterministic finite state automata. This affects | |
5683 | the treatment of operator @samp{|} in the regular expressions. The | |
5684 | usual treatment of the operator is to try the first alternative and, | |
5685 | if the reservation is not possible, the second alternative. The | |
5686 | nondeterministic treatment means trying all alternatives, some of them | |
5687 | may be rejected by reservations in the subsequent insns. You can not | |
5688 | query functional unit reservations in nondeterministic automaton | |
5689 | states. | |
5690 | @end itemize | |
5691 | ||
5692 | As an example, consider a superscalar @acronym{RISC} machine which can | |
5693 | issue three insns (two integer insns and one floating point insn) on | |
5694 | the cycle but can finish only two insns. To describe this, we define | |
5695 | the following functional units. | |
5696 | ||
5697 | @smallexample | |
5698 | (define_cpu_unit "i0_pipeline, i1_pipeline, f_pipeline") | |
5699 | (define_cpu_unit "port_0, port1") | |
5700 | @end smallexample | |
5701 | ||
5702 | All simple integer insns can be executed in any integer pipeline and | |
5703 | their result is ready in two cycles. The simple integer insns are | |
5704 | issued into the first pipeline unless it is reserved, otherwise they | |
5705 | are issued into the second pipeline. Integer division and | |
5706 | multiplication insns can be executed only in the second integer | |
5707 | pipeline and their results are ready correspondingly in 8 and 4 | |
5708 | cycles. The integer division is not pipelined, i.e. the subsequent | |
5709 | integer division insn can not be issued until the current division | |
5710 | insn finished. Floating point insns are fully pipelined and their | |
5711 | results are ready in 3 cycles. There is also additional one cycle | |
5712 | delay in the usage by integer insns of result produced by floating | |
5713 | point insns. To describe all of this we could specify | |
5714 | ||
5715 | @smallexample | |
5716 | (define_cpu_unit "div") | |
5717 | ||
5718 | (define_insn_reservation "simple" 2 (eq_attr "cpu" "int") | |
5719 | "(i0_pipeline | i1_pipeline), (port_0 | port1)") | |
5720 | ||
5721 | (define_insn_reservation "mult" 4 (eq_attr "cpu" "mult") | |
5722 | "i1_pipeline, nothing*2, (port_0 | port1)") | |
5723 | ||
5724 | (define_insn_reservation "div" 8 (eq_attr "cpu" "div") | |
5725 | "i1_pipeline, div*7, div + (port_0 | port1)") | |
5726 | ||
5727 | (define_insn_reservation "float" 3 (eq_attr "cpu" "float") | |
5728 | "f_pipeline, nothing, (port_0 | port1)) | |
5729 | ||
5730 | (define_bypass 4 "float" "simple,mut,div") | |
5731 | @end smallexample | |
5732 | ||
5733 | To simplify the description we could describe the following reservation | |
5734 | ||
5735 | @smallexample | |
5736 | (define_reservation "finish" "port0|port1") | |
5737 | @end smallexample | |
5738 | ||
5739 | and use it in all @code{define_insn_reservation} as in the following | |
5740 | construction | |
5741 | ||
5742 | @smallexample | |
5743 | (define_insn_reservation "simple" 2 (eq_attr "cpu" "int") | |
5744 | "(i0_pipeline | i1_pipeline), finish") | |
5745 | @end smallexample | |
5746 | ||
5747 | ||
5748 | @node Comparison of the two descriptions | |
5749 | @subsubsection Drawbacks of the old pipeline description | |
5750 | @cindex old pipeline description | |
5751 | @cindex automaton based pipeline description | |
5752 | @cindex processor functional units | |
5753 | @cindex interlock delays | |
5754 | @cindex instruction latency time | |
5755 | @cindex pipeline hazard recognizer | |
5756 | @cindex data bypass | |
5757 | ||
5758 | The old instruction level parallelism description and the pipeline | |
5759 | hazards recognizer based on it have the following drawbacks in | |
5760 | comparison with the @acronym{DFA}-based ones: | |
5761 | ||
5762 | @itemize @bullet | |
5763 | @item | |
5764 | Each functional unit is believed to be reserved at the instruction | |
5765 | execution start. This is a very inaccurate model for modern | |
5766 | processors. | |
5767 | ||
5768 | @item | |
5769 | An inadequate description of instruction latency times. The latency | |
5770 | time is bound with a functional unit reserved by an instruction not | |
5771 | with the instruction itself. In other words, the description is | |
5772 | oriented to describe at most one unit reservation by each instruction. | |
5773 | It also does not permit to describe special bypasses between | |
5774 | instruction pairs. | |
5775 | ||
5776 | @item | |
5777 | The implementation of the pipeline hazard recognizer interface has | |
5778 | constraints on number of functional units. This is a number of bits | |
5779 | in integer on the host machine. | |
5780 | ||
5781 | @item | |
5782 | The interface to the pipeline hazard recognizer is more complex than | |
5783 | one to the automaton based pipeline recognizer. | |
5784 | ||
5785 | @item | |
5786 | An unnatural description when you write an unit and a condition which | |
5787 | selects instructions using the unit. Writing all unit reservations | |
5788 | for an instruction (an instruction class) is more natural. | |
5789 | ||
5790 | @item | |
5791 | The recognition of the interlock delays has slow implementation. GCC | |
5792 | scheduler supports structures which describe the unit reservations. | |
5793 | The more processor has functional units, the slower pipeline hazard | |
5794 | recognizer. Such implementation would become slower when we enable to | |
5795 | reserve functional units not only at the instruction execution start. | |
5796 | The automaton based pipeline hazard recognizer speed is not depended | |
5797 | on processor complexity. | |
5798 | @end itemize | |
5799 | ||
3262c1f5 RH |
5800 | @node Conditional Execution |
5801 | @section Conditional Execution | |
5802 | @cindex conditional execution | |
5803 | @cindex predication | |
5804 | ||
5805 | A number of architectures provide for some form of conditional | |
5806 | execution, or predication. The hallmark of this feature is the | |
5807 | ability to nullify most of the instructions in the instruction set. | |
5808 | When the instruction set is large and not entirely symmetric, it | |
5809 | can be quite tedious to describe these forms directly in the | |
5810 | @file{.md} file. An alternative is the @code{define_cond_exec} template. | |
5811 | ||
5812 | @findex define_cond_exec | |
5813 | @smallexample | |
5814 | (define_cond_exec | |
5815 | [@var{predicate-pattern}] | |
5816 | "@var{condition}" | |
630d3d5a | 5817 | "@var{output-template}") |
3262c1f5 RH |
5818 | @end smallexample |
5819 | ||
5820 | @var{predicate-pattern} is the condition that must be true for the | |
5821 | insn to be executed at runtime and should match a relational operator. | |
5822 | One can use @code{match_operator} to match several relational operators | |
5823 | at once. Any @code{match_operand} operands must have no more than one | |
5824 | alternative. | |
5825 | ||
5826 | @var{condition} is a C expression that must be true for the generated | |
5827 | pattern to match. | |
5828 | ||
5829 | @findex current_insn_predicate | |
630d3d5a | 5830 | @var{output-template} is a string similar to the @code{define_insn} |
3262c1f5 RH |
5831 | output template (@pxref{Output Template}), except that the @samp{*} |
5832 | and @samp{@@} special cases do not apply. This is only useful if the | |
5833 | assembly text for the predicate is a simple prefix to the main insn. | |
5834 | In order to handle the general case, there is a global variable | |
5835 | @code{current_insn_predicate} that will contain the entire predicate | |
5836 | if the current insn is predicated, and will otherwise be @code{NULL}. | |
5837 | ||
ebb48a4d JM |
5838 | When @code{define_cond_exec} is used, an implicit reference to |
5839 | the @code{predicable} instruction attribute is made. | |
e979f9e8 | 5840 | @xref{Insn Attributes}. This attribute must be boolean (i.e.@: have |
3262c1f5 RH |
5841 | exactly two elements in its @var{list-of-values}). Further, it must |
5842 | not be used with complex expressions. That is, the default and all | |
ebb48a4d | 5843 | uses in the insns must be a simple constant, not dependent on the |
3262c1f5 RH |
5844 | alternative or anything else. |
5845 | ||
ebb48a4d | 5846 | For each @code{define_insn} for which the @code{predicable} |
3262c1f5 RH |
5847 | attribute is true, a new @code{define_insn} pattern will be |
5848 | generated that matches a predicated version of the instruction. | |
5849 | For example, | |
5850 | ||
5851 | @smallexample | |
5852 | (define_insn "addsi" | |
5853 | [(set (match_operand:SI 0 "register_operand" "r") | |
5854 | (plus:SI (match_operand:SI 1 "register_operand" "r") | |
5855 | (match_operand:SI 2 "register_operand" "r")))] | |
5856 | "@var{test1}" | |
5857 | "add %2,%1,%0") | |
5858 | ||
5859 | (define_cond_exec | |
5860 | [(ne (match_operand:CC 0 "register_operand" "c") | |
5861 | (const_int 0))] | |
5862 | "@var{test2}" | |
5863 | "(%0)") | |
5864 | @end smallexample | |
5865 | ||
5866 | @noindent | |
5867 | generates a new pattern | |
5868 | ||
5869 | @smallexample | |
5870 | (define_insn "" | |
5871 | [(cond_exec | |
5872 | (ne (match_operand:CC 3 "register_operand" "c") (const_int 0)) | |
5873 | (set (match_operand:SI 0 "register_operand" "r") | |
5874 | (plus:SI (match_operand:SI 1 "register_operand" "r") | |
5875 | (match_operand:SI 2 "register_operand" "r"))))] | |
5876 | "(@var{test2}) && (@var{test1})" | |
5877 | "(%3) add %2,%1,%0") | |
5878 | @end smallexample | |
c25c12b8 R |
5879 | |
5880 | @node Constant Definitions | |
5881 | @section Constant Definitions | |
5882 | @cindex constant definitions | |
5883 | @findex define_constants | |
5884 | ||
5885 | Using literal constants inside instruction patterns reduces legibility and | |
5886 | can be a maintenance problem. | |
5887 | ||
5888 | To overcome this problem, you may use the @code{define_constants} | |
5889 | expression. It contains a vector of name-value pairs. From that | |
5890 | point on, wherever any of the names appears in the MD file, it is as | |
5891 | if the corresponding value had been written instead. You may use | |
5892 | @code{define_constants} multiple times; each appearance adds more | |
5893 | constants to the table. It is an error to redefine a constant with | |
5894 | a different value. | |
5895 | ||
5896 | To come back to the a29k load multiple example, instead of | |
5897 | ||
5898 | @smallexample | |
5899 | (define_insn "" | |
5900 | [(match_parallel 0 "load_multiple_operation" | |
5901 | [(set (match_operand:SI 1 "gpc_reg_operand" "=r") | |
5902 | (match_operand:SI 2 "memory_operand" "m")) | |
5903 | (use (reg:SI 179)) | |
5904 | (clobber (reg:SI 179))])] | |
5905 | "" | |
5906 | "loadm 0,0,%1,%2") | |
5907 | @end smallexample | |
5908 | ||
5909 | You could write: | |
5910 | ||
5911 | @smallexample | |
5912 | (define_constants [ | |
5913 | (R_BP 177) | |
5914 | (R_FC 178) | |
5915 | (R_CR 179) | |
5916 | (R_Q 180) | |
5917 | ]) | |
5918 | ||
5919 | (define_insn "" | |
5920 | [(match_parallel 0 "load_multiple_operation" | |
5921 | [(set (match_operand:SI 1 "gpc_reg_operand" "=r") | |
5922 | (match_operand:SI 2 "memory_operand" "m")) | |
5923 | (use (reg:SI R_CR)) | |
5924 | (clobber (reg:SI R_CR))])] | |
5925 | "" | |
5926 | "loadm 0,0,%1,%2") | |
5927 | @end smallexample | |
5928 | ||
5929 | The constants that are defined with a define_constant are also output | |
5930 | in the insn-codes.h header file as #defines. | |
b11cc610 | 5931 | @end ifset |