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83ffe9cd | 1 | @c Copyright (C) 1988-2023 Free Software Foundation, Inc. |
d77de738 ML |
2 | @c This is part of the GCC manual. |
3 | @c For copying conditions, see the file gcc.texi. | |
4 | ||
5 | @ifset INTERNALS | |
6 | @node Machine Desc | |
7 | @chapter Machine Descriptions | |
8 | @cindex machine descriptions | |
9 | ||
10 | A machine description has two parts: a file of instruction patterns | |
11 | (@file{.md} file) and a C header file of macro definitions. | |
12 | ||
13 | The @file{.md} file for a target machine contains a pattern for each | |
14 | instruction that the target machine supports (or at least each instruction | |
15 | that is worth telling the compiler about). It may also contain comments. | |
16 | A semicolon causes the rest of the line to be a comment, unless the semicolon | |
17 | is inside a quoted string. | |
18 | ||
19 | See the next chapter for information on the C header file. | |
20 | ||
21 | @menu | |
22 | * Overview:: How the machine description is used. | |
23 | * Patterns:: How to write instruction patterns. | |
24 | * Example:: An explained example of a @code{define_insn} pattern. | |
25 | * RTL Template:: The RTL template defines what insns match a pattern. | |
26 | * Output Template:: The output template says how to make assembler code | |
27 | from such an insn. | |
28 | * Output Statement:: For more generality, write C code to output | |
29 | the assembler code. | |
957ae904 | 30 | * Compact Syntax:: Compact syntax for writing machine descriptors. |
d77de738 ML |
31 | * Predicates:: Controlling what kinds of operands can be used |
32 | for an insn. | |
33 | * Constraints:: Fine-tuning operand selection. | |
34 | * Standard Names:: Names mark patterns to use for code generation. | |
35 | * Pattern Ordering:: When the order of patterns makes a difference. | |
36 | * Dependent Patterns:: Having one pattern may make you need another. | |
37 | * Jump Patterns:: Special considerations for patterns for jump insns. | |
38 | * Looping Patterns:: How to define patterns for special looping insns. | |
39 | * Insn Canonicalizations::Canonicalization of Instructions | |
40 | * Expander Definitions::Generating a sequence of several RTL insns | |
41 | for a standard operation. | |
42 | * Insn Splitting:: Splitting Instructions into Multiple Instructions. | |
43 | * Including Patterns:: Including Patterns in Machine Descriptions. | |
44 | * Peephole Definitions::Defining machine-specific peephole optimizations. | |
45 | * Insn Attributes:: Specifying the value of attributes for generated insns. | |
46 | * Conditional Execution::Generating @code{define_insn} patterns for | |
47 | predication. | |
48 | * Define Subst:: Generating @code{define_insn} and @code{define_expand} | |
49 | patterns from other patterns. | |
50 | * Constant Definitions::Defining symbolic constants that can be used in the | |
51 | md file. | |
52 | * Iterators:: Using iterators to generate patterns from a template. | |
53 | @end menu | |
54 | ||
55 | @node Overview | |
56 | @section Overview of How the Machine Description is Used | |
57 | ||
58 | There are three main conversions that happen in the compiler: | |
59 | ||
60 | @enumerate | |
61 | ||
62 | @item | |
63 | The front end reads the source code and builds a parse tree. | |
64 | ||
65 | @item | |
66 | The parse tree is used to generate an RTL insn list based on named | |
67 | instruction patterns. | |
68 | ||
69 | @item | |
70 | The insn list is matched against the RTL templates to produce assembler | |
71 | code. | |
72 | ||
73 | @end enumerate | |
74 | ||
75 | For the generate pass, only the names of the insns matter, from either a | |
76 | named @code{define_insn} or a @code{define_expand}. The compiler will | |
77 | choose the pattern with the right name and apply the operands according | |
78 | to the documentation later in this chapter, without regard for the RTL | |
79 | template or operand constraints. Note that the names the compiler looks | |
80 | for are hard-coded in the compiler---it will ignore unnamed patterns and | |
81 | patterns with names it doesn't know about, but if you don't provide a | |
82 | named pattern it needs, it will abort. | |
83 | ||
84 | If a @code{define_insn} is used, the template given is inserted into the | |
85 | insn list. If a @code{define_expand} is used, one of three things | |
86 | happens, based on the condition logic. The condition logic may manually | |
87 | create new insns for the insn list, say via @code{emit_insn()}, and | |
88 | invoke @code{DONE}. For certain named patterns, it may invoke @code{FAIL} to tell the | |
89 | compiler to use an alternate way of performing that task. If it invokes | |
90 | neither @code{DONE} nor @code{FAIL}, the template given in the pattern | |
91 | is inserted, as if the @code{define_expand} were a @code{define_insn}. | |
92 | ||
93 | Once the insn list is generated, various optimization passes convert, | |
94 | replace, and rearrange the insns in the insn list. This is where the | |
95 | @code{define_split} and @code{define_peephole} patterns get used, for | |
96 | example. | |
97 | ||
98 | Finally, the insn list's RTL is matched up with the RTL templates in the | |
99 | @code{define_insn} patterns, and those patterns are used to emit the | |
100 | final assembly code. For this purpose, each named @code{define_insn} | |
101 | acts like it's unnamed, since the names are ignored. | |
102 | ||
103 | @node Patterns | |
104 | @section Everything about Instruction Patterns | |
105 | @cindex patterns | |
106 | @cindex instruction patterns | |
107 | ||
108 | @findex define_insn | |
109 | A @code{define_insn} expression is used to define instruction patterns | |
110 | to which insns may be matched. A @code{define_insn} expression contains | |
111 | an incomplete RTL expression, with pieces to be filled in later, operand | |
112 | constraints that restrict how the pieces can be filled in, and an output | |
113 | template or C code to generate the assembler output. | |
114 | ||
115 | A @code{define_insn} is an RTL expression containing four or five operands: | |
116 | ||
117 | @enumerate | |
118 | @item | |
119 | An optional name @var{n}. When a name is present, the compiler | |
120 | automically generates a C++ function @samp{gen_@var{n}} that takes | |
121 | the operands of the instruction as arguments and returns the instruction's | |
122 | rtx pattern. The compiler also assigns the instruction a unique code | |
123 | @samp{CODE_FOR_@var{n}}, with all such codes belonging to an enum | |
124 | called @code{insn_code}. | |
125 | ||
126 | These names serve one of two purposes. The first is to indicate that the | |
127 | instruction performs a certain standard job for the RTL-generation | |
128 | pass of the compiler, such as a move, an addition, or a conditional | |
129 | jump. The second is to help the target generate certain target-specific | |
130 | operations, such as when implementing target-specific intrinsic functions. | |
131 | ||
132 | It is better to prefix target-specific names with the name of the | |
133 | target, to avoid any clash with current or future standard names. | |
134 | ||
135 | The absence of a name is indicated by writing an empty string | |
136 | where the name should go. Nameless instruction patterns are never | |
137 | used for generating RTL code, but they may permit several simpler insns | |
138 | to be combined later on. | |
139 | ||
140 | For the purpose of debugging the compiler, you may also specify a | |
141 | name beginning with the @samp{*} character. Such a name is used only | |
142 | for identifying the instruction in RTL dumps; it is equivalent to having | |
143 | a nameless pattern for all other purposes. Names beginning with the | |
144 | @samp{*} character are not required to be unique. | |
145 | ||
146 | The name may also have the form @samp{@@@var{n}}. This has the same | |
147 | effect as a name @samp{@var{n}}, but in addition tells the compiler to | |
148 | generate further helper functions; see @ref{Parameterized Names} for details. | |
149 | ||
150 | @item | |
151 | The @dfn{RTL template}: This is a vector of incomplete RTL expressions | |
152 | which describe the semantics of the instruction (@pxref{RTL Template}). | |
153 | It is incomplete because it may contain @code{match_operand}, | |
154 | @code{match_operator}, and @code{match_dup} expressions that stand for | |
155 | operands of the instruction. | |
156 | ||
157 | If the vector has multiple elements, the RTL template is treated as a | |
158 | @code{parallel} expression. | |
159 | ||
d77de738 ML |
160 | @cindex pattern conditions |
161 | @cindex conditions, in patterns | |
f33d7a88 | 162 | @item |
d77de738 ML |
163 | The condition: This is a string which contains a C expression. When the |
164 | compiler attempts to match RTL against a pattern, the condition is | |
165 | evaluated. If the condition evaluates to @code{true}, the match is | |
166 | permitted. The condition may be an empty string, which is treated | |
167 | as always @code{true}. | |
168 | ||
169 | @cindex named patterns and conditions | |
170 | For a named pattern, the condition may not depend on the data in the | |
171 | insn being matched, but only the target-machine-type flags. The compiler | |
172 | needs to test these conditions during initialization in order to learn | |
173 | exactly which named instructions are available in a particular run. | |
174 | ||
175 | @findex operands | |
176 | For nameless patterns, the condition is applied only when matching an | |
177 | individual insn, and only after the insn has matched the pattern's | |
178 | recognition template. The insn's operands may be found in the vector | |
179 | @code{operands}. | |
180 | ||
181 | An instruction condition cannot become more restrictive as compilation | |
182 | progresses. If the condition accepts a particular RTL instruction at | |
183 | one stage of compilation, it must continue to accept that instruction | |
184 | until the final pass. For example, @samp{!reload_completed} and | |
185 | @samp{can_create_pseudo_p ()} are both invalid instruction conditions, | |
186 | because they are true during the earlier RTL passes and false during | |
187 | the later ones. For the same reason, if a condition accepts an | |
188 | instruction before register allocation, it cannot later try to control | |
189 | register allocation by excluding certain register or value combinations. | |
190 | ||
191 | Although a condition cannot become more restrictive as compilation | |
192 | progresses, the condition for a nameless pattern @emph{can} become | |
193 | more permissive. For example, a nameless instruction can require | |
194 | @samp{reload_completed} to be true, in which case it only matches | |
195 | after register allocation. | |
196 | ||
197 | @item | |
198 | The @dfn{output template} or @dfn{output statement}: This is either | |
199 | a string, or a fragment of C code which returns a string. | |
200 | ||
201 | When simple substitution isn't general enough, you can specify a piece | |
202 | of C code to compute the output. @xref{Output Statement}. | |
203 | ||
204 | @item | |
205 | The @dfn{insn attributes}: This is an optional vector containing the values of | |
206 | attributes for insns matching this pattern (@pxref{Insn Attributes}). | |
207 | @end enumerate | |
208 | ||
209 | @node Example | |
210 | @section Example of @code{define_insn} | |
211 | @cindex @code{define_insn} example | |
212 | ||
213 | Here is an example of an instruction pattern, taken from the machine | |
214 | description for the 68000/68020. | |
215 | ||
216 | @smallexample | |
217 | (define_insn "tstsi" | |
218 | [(set (cc0) | |
219 | (match_operand:SI 0 "general_operand" "rm"))] | |
220 | "" | |
221 | "* | |
222 | @{ | |
223 | if (TARGET_68020 || ! ADDRESS_REG_P (operands[0])) | |
224 | return \"tstl %0\"; | |
225 | return \"cmpl #0,%0\"; | |
226 | @}") | |
227 | @end smallexample | |
228 | ||
229 | @noindent | |
230 | This can also be written using braced strings: | |
231 | ||
232 | @smallexample | |
233 | (define_insn "tstsi" | |
234 | [(set (cc0) | |
235 | (match_operand:SI 0 "general_operand" "rm"))] | |
236 | "" | |
237 | @{ | |
238 | if (TARGET_68020 || ! ADDRESS_REG_P (operands[0])) | |
239 | return "tstl %0"; | |
240 | return "cmpl #0,%0"; | |
241 | @}) | |
242 | @end smallexample | |
243 | ||
244 | This describes an instruction which sets the condition codes based on the | |
245 | value of a general operand. It has no condition, so any insn with an RTL | |
246 | description of the form shown may be matched to this pattern. The name | |
247 | @samp{tstsi} means ``test a @code{SImode} value'' and tells the RTL | |
248 | generation pass that, when it is necessary to test such a value, an insn | |
249 | to do so can be constructed using this pattern. | |
250 | ||
251 | The output control string is a piece of C code which chooses which | |
252 | output template to return based on the kind of operand and the specific | |
253 | type of CPU for which code is being generated. | |
254 | ||
255 | @samp{"rm"} is an operand constraint. Its meaning is explained below. | |
256 | ||
257 | @node RTL Template | |
258 | @section RTL Template | |
259 | @cindex RTL insn template | |
260 | @cindex generating insns | |
261 | @cindex insns, generating | |
262 | @cindex recognizing insns | |
263 | @cindex insns, recognizing | |
264 | ||
265 | The RTL template is used to define which insns match the particular pattern | |
266 | and how to find their operands. For named patterns, the RTL template also | |
267 | says how to construct an insn from specified operands. | |
268 | ||
269 | Construction involves substituting specified operands into a copy of the | |
270 | template. Matching involves determining the values that serve as the | |
271 | operands in the insn being matched. Both of these activities are | |
272 | controlled by special expression types that direct matching and | |
273 | substitution of the operands. | |
274 | ||
275 | @table @code | |
276 | @findex match_operand | |
277 | @item (match_operand:@var{m} @var{n} @var{predicate} @var{constraint}) | |
278 | This expression is a placeholder for operand number @var{n} of | |
279 | the insn. When constructing an insn, operand number @var{n} | |
280 | will be substituted at this point. When matching an insn, whatever | |
281 | appears at this position in the insn will be taken as operand | |
282 | number @var{n}; but it must satisfy @var{predicate} or this instruction | |
283 | pattern will not match at all. | |
284 | ||
285 | Operand numbers must be chosen consecutively counting from zero in | |
286 | each instruction pattern. There may be only one @code{match_operand} | |
287 | expression in the pattern for each operand number. Usually operands | |
288 | are numbered in the order of appearance in @code{match_operand} | |
289 | expressions. In the case of a @code{define_expand}, any operand numbers | |
290 | used only in @code{match_dup} expressions have higher values than all | |
291 | other operand numbers. | |
292 | ||
293 | @var{predicate} is a string that is the name of a function that | |
294 | accepts two arguments, an expression and a machine mode. | |
295 | @xref{Predicates}. During matching, the function will be called with | |
296 | the putative operand as the expression and @var{m} as the mode | |
297 | argument (if @var{m} is not specified, @code{VOIDmode} will be used, | |
298 | which normally causes @var{predicate} to accept any mode). If it | |
299 | returns zero, this instruction pattern fails to match. | |
300 | @var{predicate} may be an empty string; then it means no test is to be | |
301 | done on the operand, so anything which occurs in this position is | |
302 | valid. | |
303 | ||
304 | Most of the time, @var{predicate} will reject modes other than @var{m}---but | |
305 | not always. For example, the predicate @code{address_operand} uses | |
306 | @var{m} as the mode of memory ref that the address should be valid for. | |
307 | Many predicates accept @code{const_int} nodes even though their mode is | |
308 | @code{VOIDmode}. | |
309 | ||
310 | @var{constraint} controls reloading and the choice of the best register | |
311 | class to use for a value, as explained later (@pxref{Constraints}). | |
312 | If the constraint would be an empty string, it can be omitted. | |
313 | ||
314 | People are often unclear on the difference between the constraint and the | |
315 | predicate. The predicate helps decide whether a given insn matches the | |
316 | pattern. The constraint plays no role in this decision; instead, it | |
317 | controls various decisions in the case of an insn which does match. | |
318 | ||
319 | @findex match_scratch | |
320 | @item (match_scratch:@var{m} @var{n} @var{constraint}) | |
321 | This expression is also a placeholder for operand number @var{n} | |
322 | and indicates that operand must be a @code{scratch} or @code{reg} | |
323 | expression. | |
324 | ||
325 | When matching patterns, this is equivalent to | |
326 | ||
327 | @smallexample | |
328 | (match_operand:@var{m} @var{n} "scratch_operand" @var{constraint}) | |
329 | @end smallexample | |
330 | ||
331 | but, when generating RTL, it produces a (@code{scratch}:@var{m}) | |
332 | expression. | |
333 | ||
334 | If the last few expressions in a @code{parallel} are @code{clobber} | |
335 | expressions whose operands are either a hard register or | |
336 | @code{match_scratch}, the combiner can add or delete them when | |
337 | necessary. @xref{Side Effects}. | |
338 | ||
339 | @findex match_dup | |
340 | @item (match_dup @var{n}) | |
341 | This expression is also a placeholder for operand number @var{n}. | |
342 | It is used when the operand needs to appear more than once in the | |
343 | insn. | |
344 | ||
345 | In construction, @code{match_dup} acts just like @code{match_operand}: | |
346 | the operand is substituted into the insn being constructed. But in | |
347 | matching, @code{match_dup} behaves differently. It assumes that operand | |
348 | number @var{n} has already been determined by a @code{match_operand} | |
349 | appearing earlier in the recognition template, and it matches only an | |
350 | identical-looking expression. | |
351 | ||
352 | Note that @code{match_dup} should not be used to tell the compiler that | |
353 | a particular register is being used for two operands (example: | |
354 | @code{add} that adds one register to another; the second register is | |
355 | both an input operand and the output operand). Use a matching | |
356 | constraint (@pxref{Simple Constraints}) for those. @code{match_dup} is for the cases where one | |
357 | operand is used in two places in the template, such as an instruction | |
358 | that computes both a quotient and a remainder, where the opcode takes | |
359 | two input operands but the RTL template has to refer to each of those | |
360 | twice; once for the quotient pattern and once for the remainder pattern. | |
361 | ||
362 | @findex match_operator | |
363 | @item (match_operator:@var{m} @var{n} @var{predicate} [@var{operands}@dots{}]) | |
364 | This pattern is a kind of placeholder for a variable RTL expression | |
365 | code. | |
366 | ||
367 | When constructing an insn, it stands for an RTL expression whose | |
368 | expression code is taken from that of operand @var{n}, and whose | |
369 | operands are constructed from the patterns @var{operands}. | |
370 | ||
371 | When matching an expression, it matches an expression if the function | |
372 | @var{predicate} returns nonzero on that expression @emph{and} the | |
373 | patterns @var{operands} match the operands of the expression. | |
374 | ||
375 | Suppose that the function @code{commutative_operator} is defined as | |
376 | follows, to match any expression whose operator is one of the | |
377 | commutative arithmetic operators of RTL and whose mode is @var{mode}: | |
378 | ||
379 | @smallexample | |
380 | int | |
27afe64c | 381 | commutative_operator (x, mode) |
d77de738 ML |
382 | rtx x; |
383 | machine_mode mode; | |
384 | @{ | |
385 | enum rtx_code code = GET_CODE (x); | |
386 | if (GET_MODE (x) != mode) | |
387 | return 0; | |
388 | return (GET_RTX_CLASS (code) == RTX_COMM_ARITH | |
389 | || code == EQ || code == NE); | |
390 | @} | |
391 | @end smallexample | |
392 | ||
393 | Then the following pattern will match any RTL expression consisting | |
394 | of a commutative operator applied to two general operands: | |
395 | ||
396 | @smallexample | |
397 | (match_operator:SI 3 "commutative_operator" | |
398 | [(match_operand:SI 1 "general_operand" "g") | |
399 | (match_operand:SI 2 "general_operand" "g")]) | |
400 | @end smallexample | |
401 | ||
402 | Here the vector @code{[@var{operands}@dots{}]} contains two patterns | |
403 | because the expressions to be matched all contain two operands. | |
404 | ||
405 | When this pattern does match, the two operands of the commutative | |
406 | operator are recorded as operands 1 and 2 of the insn. (This is done | |
407 | by the two instances of @code{match_operand}.) Operand 3 of the insn | |
408 | will be the entire commutative expression: use @code{GET_CODE | |
409 | (operands[3])} to see which commutative operator was used. | |
410 | ||
411 | The machine mode @var{m} of @code{match_operator} works like that of | |
412 | @code{match_operand}: it is passed as the second argument to the | |
413 | predicate function, and that function is solely responsible for | |
414 | deciding whether the expression to be matched ``has'' that mode. | |
415 | ||
416 | When constructing an insn, argument 3 of the gen-function will specify | |
417 | the operation (i.e.@: the expression code) for the expression to be | |
418 | made. It should be an RTL expression, whose expression code is copied | |
419 | into a new expression whose operands are arguments 1 and 2 of the | |
420 | gen-function. The subexpressions of argument 3 are not used; | |
421 | only its expression code matters. | |
422 | ||
423 | When @code{match_operator} is used in a pattern for matching an insn, | |
424 | it usually best if the operand number of the @code{match_operator} | |
425 | is higher than that of the actual operands of the insn. This improves | |
426 | register allocation because the register allocator often looks at | |
427 | operands 1 and 2 of insns to see if it can do register tying. | |
428 | ||
429 | There is no way to specify constraints in @code{match_operator}. The | |
430 | operand of the insn which corresponds to the @code{match_operator} | |
431 | never has any constraints because it is never reloaded as a whole. | |
432 | However, if parts of its @var{operands} are matched by | |
433 | @code{match_operand} patterns, those parts may have constraints of | |
434 | their own. | |
435 | ||
436 | @findex match_op_dup | |
437 | @item (match_op_dup:@var{m} @var{n}[@var{operands}@dots{}]) | |
438 | Like @code{match_dup}, except that it applies to operators instead of | |
439 | operands. When constructing an insn, operand number @var{n} will be | |
440 | substituted at this point. But in matching, @code{match_op_dup} behaves | |
441 | differently. It assumes that operand number @var{n} has already been | |
442 | determined by a @code{match_operator} appearing earlier in the | |
443 | recognition template, and it matches only an identical-looking | |
444 | expression. | |
445 | ||
446 | @findex match_parallel | |
447 | @item (match_parallel @var{n} @var{predicate} [@var{subpat}@dots{}]) | |
448 | This pattern is a placeholder for an insn that consists of a | |
449 | @code{parallel} expression with a variable number of elements. This | |
450 | expression should only appear at the top level of an insn pattern. | |
451 | ||
452 | When constructing an insn, operand number @var{n} will be substituted at | |
453 | this point. When matching an insn, it matches if the body of the insn | |
454 | is a @code{parallel} expression with at least as many elements as the | |
455 | vector of @var{subpat} expressions in the @code{match_parallel}, if each | |
456 | @var{subpat} matches the corresponding element of the @code{parallel}, | |
457 | @emph{and} the function @var{predicate} returns nonzero on the | |
458 | @code{parallel} that is the body of the insn. It is the responsibility | |
459 | of the predicate to validate elements of the @code{parallel} beyond | |
460 | those listed in the @code{match_parallel}. | |
461 | ||
462 | A typical use of @code{match_parallel} is to match load and store | |
463 | multiple expressions, which can contain a variable number of elements | |
464 | in a @code{parallel}. For example, | |
465 | ||
466 | @smallexample | |
467 | (define_insn "" | |
468 | [(match_parallel 0 "load_multiple_operation" | |
469 | [(set (match_operand:SI 1 "gpc_reg_operand" "=r") | |
470 | (match_operand:SI 2 "memory_operand" "m")) | |
471 | (use (reg:SI 179)) | |
472 | (clobber (reg:SI 179))])] | |
473 | "" | |
474 | "loadm 0,0,%1,%2") | |
475 | @end smallexample | |
476 | ||
477 | This example comes from @file{a29k.md}. The function | |
478 | @code{load_multiple_operation} is defined in @file{a29k.c} and checks | |
479 | that subsequent elements in the @code{parallel} are the same as the | |
480 | @code{set} in the pattern, except that they are referencing subsequent | |
481 | registers and memory locations. | |
482 | ||
483 | An insn that matches this pattern might look like: | |
484 | ||
485 | @smallexample | |
486 | (parallel | |
487 | [(set (reg:SI 20) (mem:SI (reg:SI 100))) | |
488 | (use (reg:SI 179)) | |
489 | (clobber (reg:SI 179)) | |
490 | (set (reg:SI 21) | |
491 | (mem:SI (plus:SI (reg:SI 100) | |
492 | (const_int 4)))) | |
493 | (set (reg:SI 22) | |
494 | (mem:SI (plus:SI (reg:SI 100) | |
495 | (const_int 8))))]) | |
496 | @end smallexample | |
497 | ||
498 | @findex match_par_dup | |
499 | @item (match_par_dup @var{n} [@var{subpat}@dots{}]) | |
500 | Like @code{match_op_dup}, but for @code{match_parallel} instead of | |
501 | @code{match_operator}. | |
502 | ||
503 | @end table | |
504 | ||
505 | @node Output Template | |
506 | @section Output Templates and Operand Substitution | |
507 | @cindex output templates | |
508 | @cindex operand substitution | |
509 | ||
510 | @cindex @samp{%} in template | |
511 | @cindex percent sign | |
512 | The @dfn{output template} is a string which specifies how to output the | |
513 | assembler code for an instruction pattern. Most of the template is a | |
514 | fixed string which is output literally. The character @samp{%} is used | |
515 | to specify where to substitute an operand; it can also be used to | |
516 | identify places where different variants of the assembler require | |
517 | different syntax. | |
518 | ||
519 | In the simplest case, a @samp{%} followed by a digit @var{n} says to output | |
520 | operand @var{n} at that point in the string. | |
521 | ||
522 | @samp{%} followed by a letter and a digit says to output an operand in an | |
523 | alternate fashion. Four letters have standard, built-in meanings described | |
524 | below. The machine description macro @code{PRINT_OPERAND} can define | |
525 | additional letters with nonstandard meanings. | |
526 | ||
527 | @samp{%c@var{digit}} can be used to substitute an operand that is a | |
528 | constant value without the syntax that normally indicates an immediate | |
529 | operand. | |
530 | ||
531 | @samp{%n@var{digit}} is like @samp{%c@var{digit}} except that the value of | |
532 | the constant is negated before printing. | |
533 | ||
534 | @samp{%a@var{digit}} can be used to substitute an operand as if it were a | |
535 | memory reference, with the actual operand treated as the address. This may | |
536 | be useful when outputting a ``load address'' instruction, because often the | |
537 | assembler syntax for such an instruction requires you to write the operand | |
538 | as if it were a memory reference. | |
539 | ||
540 | @samp{%l@var{digit}} is used to substitute a @code{label_ref} into a jump | |
541 | instruction. | |
542 | ||
543 | @samp{%=} outputs a number which is unique to each instruction in the | |
544 | entire compilation. This is useful for making local labels to be | |
545 | referred to more than once in a single template that generates multiple | |
546 | assembler instructions. | |
547 | ||
548 | @samp{%} followed by a punctuation character specifies a substitution that | |
549 | does not use an operand. Only one case is standard: @samp{%%} outputs a | |
550 | @samp{%} into the assembler code. Other nonstandard cases can be | |
551 | defined in the @code{PRINT_OPERAND} macro. You must also define | |
552 | which punctuation characters are valid with the | |
553 | @code{PRINT_OPERAND_PUNCT_VALID_P} macro. | |
554 | ||
555 | @cindex \ | |
556 | @cindex backslash | |
557 | The template may generate multiple assembler instructions. Write the text | |
558 | for the instructions, with @samp{\;} between them. | |
559 | ||
560 | @cindex matching operands | |
561 | When the RTL contains two operands which are required by constraint to match | |
562 | each other, the output template must refer only to the lower-numbered operand. | |
563 | Matching operands are not always identical, and the rest of the compiler | |
564 | arranges to put the proper RTL expression for printing into the lower-numbered | |
565 | operand. | |
566 | ||
567 | One use of nonstandard letters or punctuation following @samp{%} is to | |
568 | distinguish between different assembler languages for the same machine; for | |
569 | example, Motorola syntax versus MIT syntax for the 68000. Motorola syntax | |
570 | requires periods in most opcode names, while MIT syntax does not. For | |
571 | example, the opcode @samp{movel} in MIT syntax is @samp{move.l} in Motorola | |
572 | syntax. The same file of patterns is used for both kinds of output syntax, | |
573 | but the character sequence @samp{%.} is used in each place where Motorola | |
574 | syntax wants a period. The @code{PRINT_OPERAND} macro for Motorola syntax | |
575 | defines the sequence to output a period; the macro for MIT syntax defines | |
576 | it to do nothing. | |
577 | ||
578 | @cindex @code{#} in template | |
579 | As a special case, a template consisting of the single character @code{#} | |
580 | instructs the compiler to first split the insn, and then output the | |
581 | resulting instructions separately. This helps eliminate redundancy in the | |
582 | output templates. If you have a @code{define_insn} that needs to emit | |
583 | multiple assembler instructions, and there is a matching @code{define_split} | |
584 | already defined, then you can simply use @code{#} as the output template | |
585 | instead of writing an output template that emits the multiple assembler | |
586 | instructions. | |
587 | ||
588 | Note that @code{#} only has an effect while generating assembly code; | |
589 | it does not affect whether a split occurs earlier. An associated | |
590 | @code{define_split} must exist and it must be suitable for use after | |
591 | register allocation. | |
592 | ||
593 | If the macro @code{ASSEMBLER_DIALECT} is defined, you can use construct | |
594 | of the form @samp{@{option0|option1|option2@}} in the templates. These | |
595 | describe multiple variants of assembler language syntax. | |
596 | @xref{Instruction Output}. | |
597 | ||
598 | @node Output Statement | |
599 | @section C Statements for Assembler Output | |
600 | @cindex output statements | |
601 | @cindex C statements for assembler output | |
602 | @cindex generating assembler output | |
603 | ||
604 | Often a single fixed template string cannot produce correct and efficient | |
605 | assembler code for all the cases that are recognized by a single | |
606 | instruction pattern. For example, the opcodes may depend on the kinds of | |
607 | operands; or some unfortunate combinations of operands may require extra | |
608 | machine instructions. | |
609 | ||
610 | If the output control string starts with a @samp{@@}, then it is actually | |
611 | a series of templates, each on a separate line. (Blank lines and | |
612 | leading spaces and tabs are ignored.) The templates correspond to the | |
613 | pattern's constraint alternatives (@pxref{Multi-Alternative}). For example, | |
614 | if a target machine has a two-address add instruction @samp{addr} to add | |
615 | into a register and another @samp{addm} to add a register to memory, you | |
616 | might write this pattern: | |
617 | ||
618 | @smallexample | |
619 | (define_insn "addsi3" | |
620 | [(set (match_operand:SI 0 "general_operand" "=r,m") | |
621 | (plus:SI (match_operand:SI 1 "general_operand" "0,0") | |
622 | (match_operand:SI 2 "general_operand" "g,r")))] | |
623 | "" | |
624 | "@@ | |
625 | addr %2,%0 | |
626 | addm %2,%0") | |
627 | @end smallexample | |
628 | ||
629 | @cindex @code{*} in template | |
630 | @cindex asterisk in template | |
631 | If the output control string starts with a @samp{*}, then it is not an | |
632 | output template but rather a piece of C program that should compute a | |
633 | template. It should execute a @code{return} statement to return the | |
634 | template-string you want. Most such templates use C string literals, which | |
635 | require doublequote characters to delimit them. To include these | |
636 | doublequote characters in the string, prefix each one with @samp{\}. | |
637 | ||
638 | If the output control string is written as a brace block instead of a | |
639 | double-quoted string, it is automatically assumed to be C code. In that | |
640 | case, it is not necessary to put in a leading asterisk, or to escape the | |
641 | doublequotes surrounding C string literals. | |
642 | ||
643 | The operands may be found in the array @code{operands}, whose C data type | |
644 | is @code{rtx []}. | |
645 | ||
646 | It is very common to select different ways of generating assembler code | |
647 | based on whether an immediate operand is within a certain range. Be | |
648 | careful when doing this, because the result of @code{INTVAL} is an | |
649 | integer on the host machine. If the host machine has more bits in an | |
650 | @code{int} than the target machine has in the mode in which the constant | |
651 | will be used, then some of the bits you get from @code{INTVAL} will be | |
652 | superfluous. For proper results, you must carefully disregard the | |
653 | values of those bits. | |
654 | ||
655 | @findex output_asm_insn | |
656 | It is possible to output an assembler instruction and then go on to output | |
657 | or compute more of them, using the subroutine @code{output_asm_insn}. This | |
658 | receives two arguments: a template-string and a vector of operands. The | |
659 | vector may be @code{operands}, or it may be another array of @code{rtx} | |
660 | that you declare locally and initialize yourself. | |
661 | ||
662 | @findex which_alternative | |
663 | When an insn pattern has multiple alternatives in its constraints, often | |
664 | the appearance of the assembler code is determined mostly by which alternative | |
665 | was matched. When this is so, the C code can test the variable | |
666 | @code{which_alternative}, which is the ordinal number of the alternative | |
667 | that was actually satisfied (0 for the first, 1 for the second alternative, | |
668 | etc.). | |
669 | ||
670 | For example, suppose there are two opcodes for storing zero, @samp{clrreg} | |
671 | for registers and @samp{clrmem} for memory locations. Here is how | |
672 | a pattern could use @code{which_alternative} to choose between them: | |
673 | ||
674 | @smallexample | |
675 | (define_insn "" | |
676 | [(set (match_operand:SI 0 "general_operand" "=r,m") | |
677 | (const_int 0))] | |
678 | "" | |
679 | @{ | |
680 | return (which_alternative == 0 | |
681 | ? "clrreg %0" : "clrmem %0"); | |
682 | @}) | |
683 | @end smallexample | |
684 | ||
685 | The example above, where the assembler code to generate was | |
686 | @emph{solely} determined by the alternative, could also have been specified | |
687 | as follows, having the output control string start with a @samp{@@}: | |
688 | ||
689 | @smallexample | |
690 | @group | |
691 | (define_insn "" | |
692 | [(set (match_operand:SI 0 "general_operand" "=r,m") | |
693 | (const_int 0))] | |
694 | "" | |
695 | "@@ | |
696 | clrreg %0 | |
697 | clrmem %0") | |
698 | @end group | |
699 | @end smallexample | |
700 | ||
701 | If you just need a little bit of C code in one (or a few) alternatives, | |
702 | you can use @samp{*} inside of a @samp{@@} multi-alternative template: | |
703 | ||
704 | @smallexample | |
705 | @group | |
706 | (define_insn "" | |
707 | [(set (match_operand:SI 0 "general_operand" "=r,<,m") | |
708 | (const_int 0))] | |
709 | "" | |
710 | "@@ | |
711 | clrreg %0 | |
712 | * return stack_mem_p (operands[0]) ? \"push 0\" : \"clrmem %0\"; | |
713 | clrmem %0") | |
714 | @end group | |
715 | @end smallexample | |
716 | ||
957ae904 TC |
717 | @node Compact Syntax |
718 | @section Compact Syntax | |
719 | @cindex compact syntax | |
720 | ||
721 | When a @code{define_insn} or @code{define_insn_and_split} has multiple | |
722 | alternatives it may be beneficial to use the compact syntax when specifying | |
723 | alternatives. | |
724 | ||
725 | This syntax puts the constraints and attributes on the same horizontal line as | |
726 | the instruction assembly template. | |
727 | ||
728 | As an example | |
729 | ||
730 | @smallexample | |
731 | @group | |
732 | (define_insn_and_split "" | |
733 | [(set (match_operand:SI 0 "nonimmediate_operand" "=r,k,r,r,r,r") | |
734 | (match_operand:SI 1 "aarch64_mov_operand" " r,r,k,M,n,Usv"))] | |
735 | "" | |
736 | "@@ | |
737 | mov\\t%w0, %w1 | |
738 | mov\\t%w0, %w1 | |
739 | mov\\t%w0, %w1 | |
740 | mov\\t%w0, %1 | |
741 | # | |
742 | * return aarch64_output_sve_cnt_immediate ('cnt', '%x0', operands[1]);" | |
743 | "&& true" | |
744 | [(const_int 0)] | |
745 | @{ | |
746 | aarch64_expand_mov_immediate (operands[0], operands[1]); | |
747 | DONE; | |
748 | @} | |
749 | [(set_attr "type" "mov_reg,mov_reg,mov_reg,mov_imm,mov_imm,mov_imm") | |
750 | (set_attr "arch" "*,*,*,*,*,sve") | |
751 | (set_attr "length" "4,4,4,4,*, 4") | |
752 | ] | |
753 | ) | |
754 | @end group | |
755 | @end smallexample | |
756 | ||
757 | can be better expressed as: | |
758 | ||
759 | @smallexample | |
760 | @group | |
761 | (define_insn_and_split "" | |
762 | [(set (match_operand:SI 0 "nonimmediate_operand") | |
763 | (match_operand:SI 1 "aarch64_mov_operand"))] | |
764 | "" | |
765 | @{@@ [cons: =0, 1; attrs: type, arch, length] | |
766 | [r , r ; mov_reg , * , 4] mov\t%w0, %w1 | |
767 | [k , r ; mov_reg , * , 4] ^ | |
768 | [r , k ; mov_reg , * , 4] ^ | |
769 | [r , M ; mov_imm , * , 4] mov\t%w0, %1 | |
770 | [r , n ; mov_imm , * , *] # | |
771 | [r , Usv; mov_imm , sve , 4] << aarch64_output_sve_cnt_immediate ("cnt", "%x0", operands[1]); | |
772 | @} | |
773 | "&& true" | |
774 | [(const_int 0)] | |
775 | @{ | |
776 | aarch64_expand_mov_immediate (operands[0], operands[1]); | |
777 | DONE; | |
778 | @} | |
779 | ) | |
780 | @end group | |
781 | @end smallexample | |
782 | ||
783 | The syntax rules are as follows: | |
784 | @itemize @bullet | |
785 | @item | |
786 | Templates must start with @samp{@{@@} to use the new syntax. | |
787 | ||
788 | @item | |
789 | @samp{@{@@} is followed by a layout in square brackets which is @samp{cons:} | |
790 | followed by a comma-separated list of @code{match_operand}/@code{match_scratch} | |
791 | operand numbers, then a semicolon, followed by the same for attributes | |
792 | (@samp{attrs:}). Operand modifiers like @code{=} and @code{+} can be placed | |
793 | before an operand number. | |
794 | Both sections are optional (so you can use only @samp{cons}, or only | |
795 | @samp{attrs}, or both), and @samp{cons} must come before @samp{attrs} if | |
796 | present. | |
797 | ||
798 | @item | |
799 | Each alternative begins with any amount of whitespace. | |
800 | ||
801 | @item | |
802 | Following the whitespace is a comma-separated list of "constraints" and/or | |
803 | "attributes" within brackets @code{[]}, with sections separated by a semicolon. | |
804 | ||
805 | @item | |
806 | Should you want to copy the previous asm line, the symbol @code{^} can be used. | |
807 | This allows less copy pasting between alternative and reduces the number of | |
808 | lines to update on changes. | |
809 | ||
810 | @item | |
811 | When using C functions for output, the idiom @samp{* return @var{function};} | |
812 | can be replaced with the shorthand @samp{<< @var{function};}. | |
813 | ||
814 | @item | |
815 | Following the closing @samp{]} is any amount of whitespace, and then the actual | |
816 | asm output. | |
817 | ||
818 | @item | |
819 | Spaces are allowed in the list (they will simply be removed). | |
820 | ||
821 | @item | |
822 | All constraint alternatives should be specified. For example, a list of | |
823 | of three blank alternatives should be written @samp{[,,]} rather than | |
824 | @samp{[]}. | |
825 | ||
826 | @item | |
827 | All attribute alternatives should be non-empty, with @samp{*} | |
828 | representing the default attribute value. For example, a list of three | |
829 | default attribute values should be written @samp{[*,*,*]} rather than | |
830 | @samp{[]}. | |
831 | ||
832 | @item | |
833 | Within an @samp{@{@@} block both multiline and singleline C comments are | |
834 | allowed, but when used outside of a C block they must be the only non-whitespace | |
835 | blocks on the line. | |
836 | ||
837 | @item | |
838 | Within an @samp{@{@@} block, any iterators that do not get expanded will result | |
839 | in an error. If for some reason it is required to have @code{<} or @code{>} in | |
b8b19729 | 840 | the output then these must be escaped using @samp{\}. |
957ae904 TC |
841 | |
842 | @item | |
843 | It is possible to use the @samp{attrs} list to specify some attributes and to | |
844 | use the normal @code{set_attr} syntax to specify other attributes. There must | |
845 | not be any overlap between the two lists. | |
846 | ||
847 | In other words, the following is valid: | |
848 | @smallexample | |
849 | @group | |
850 | (define_insn_and_split "" | |
851 | [(set (match_operand:SI 0 "nonimmediate_operand") | |
852 | (match_operand:SI 1 "aarch64_mov_operand"))] | |
853 | "" | |
854 | @{@@ [cons: 0, 1; attrs: type, arch, length]@} | |
855 | @dots{} | |
856 | [(set_attr "foo" "mov_imm")] | |
857 | ) | |
858 | @end group | |
859 | @end smallexample | |
860 | ||
861 | but this is not valid: | |
862 | @smallexample | |
863 | @group | |
864 | (define_insn_and_split "" | |
865 | [(set (match_operand:SI 0 "nonimmediate_operand") | |
866 | (match_operand:SI 1 "aarch64_mov_operand"))] | |
867 | "" | |
868 | @{@@ [cons: 0, 1; attrs: type, arch, length]@} | |
869 | @dots{} | |
870 | [(set_attr "arch" "bar") | |
871 | (set_attr "foo" "mov_imm")] | |
872 | ) | |
873 | @end group | |
874 | @end smallexample | |
875 | ||
876 | because it specifies @code{arch} twice. | |
877 | @end itemize | |
878 | ||
d77de738 ML |
879 | @node Predicates |
880 | @section Predicates | |
881 | @cindex predicates | |
882 | @cindex operand predicates | |
883 | @cindex operator predicates | |
884 | ||
885 | A predicate determines whether a @code{match_operand} or | |
886 | @code{match_operator} expression matches, and therefore whether the | |
887 | surrounding instruction pattern will be used for that combination of | |
888 | operands. GCC has a number of machine-independent predicates, and you | |
889 | can define machine-specific predicates as needed. By convention, | |
890 | predicates used with @code{match_operand} have names that end in | |
891 | @samp{_operand}, and those used with @code{match_operator} have names | |
892 | that end in @samp{_operator}. | |
893 | ||
894 | All predicates are boolean functions (in the mathematical sense) of | |
895 | two arguments: the RTL expression that is being considered at that | |
896 | position in the instruction pattern, and the machine mode that the | |
897 | @code{match_operand} or @code{match_operator} specifies. In this | |
898 | section, the first argument is called @var{op} and the second argument | |
899 | @var{mode}. Predicates can be called from C as ordinary two-argument | |
900 | functions; this can be useful in output templates or other | |
901 | machine-specific code. | |
902 | ||
903 | Operand predicates can allow operands that are not actually acceptable | |
904 | to the hardware, as long as the constraints give reload the ability to | |
905 | fix them up (@pxref{Constraints}). However, GCC will usually generate | |
906 | better code if the predicates specify the requirements of the machine | |
907 | instructions as closely as possible. Reload cannot fix up operands | |
908 | that must be constants (``immediate operands''); you must use a | |
909 | predicate that allows only constants, or else enforce the requirement | |
910 | in the extra condition. | |
911 | ||
912 | @cindex predicates and machine modes | |
913 | @cindex normal predicates | |
914 | @cindex special predicates | |
915 | Most predicates handle their @var{mode} argument in a uniform manner. | |
916 | If @var{mode} is @code{VOIDmode} (unspecified), then @var{op} can have | |
917 | any mode. If @var{mode} is anything else, then @var{op} must have the | |
918 | same mode, unless @var{op} is a @code{CONST_INT} or integer | |
919 | @code{CONST_DOUBLE}. These RTL expressions always have | |
920 | @code{VOIDmode}, so it would be counterproductive to check that their | |
921 | mode matches. Instead, predicates that accept @code{CONST_INT} and/or | |
922 | integer @code{CONST_DOUBLE} check that the value stored in the | |
923 | constant will fit in the requested mode. | |
924 | ||
925 | Predicates with this behavior are called @dfn{normal}. | |
926 | @command{genrecog} can optimize the instruction recognizer based on | |
927 | knowledge of how normal predicates treat modes. It can also diagnose | |
928 | certain kinds of common errors in the use of normal predicates; for | |
929 | instance, it is almost always an error to use a normal predicate | |
930 | without specifying a mode. | |
931 | ||
932 | Predicates that do something different with their @var{mode} argument | |
933 | are called @dfn{special}. The generic predicates | |
934 | @code{address_operand} and @code{pmode_register_operand} are special | |
935 | predicates. @command{genrecog} does not do any optimizations or | |
936 | diagnosis when special predicates are used. | |
937 | ||
938 | @menu | |
939 | * Machine-Independent Predicates:: Predicates available to all back ends. | |
940 | * Defining Predicates:: How to write machine-specific predicate | |
941 | functions. | |
942 | @end menu | |
943 | ||
944 | @node Machine-Independent Predicates | |
945 | @subsection Machine-Independent Predicates | |
946 | @cindex machine-independent predicates | |
947 | @cindex generic predicates | |
948 | ||
949 | These are the generic predicates available to all back ends. They are | |
950 | defined in @file{recog.cc}. The first category of predicates allow | |
951 | only constant, or @dfn{immediate}, operands. | |
952 | ||
953 | @defun immediate_operand | |
954 | This predicate allows any sort of constant that fits in @var{mode}. | |
955 | It is an appropriate choice for instructions that take operands that | |
956 | must be constant. | |
957 | @end defun | |
958 | ||
959 | @defun const_int_operand | |
960 | This predicate allows any @code{CONST_INT} expression that fits in | |
961 | @var{mode}. It is an appropriate choice for an immediate operand that | |
962 | does not allow a symbol or label. | |
963 | @end defun | |
964 | ||
965 | @defun const_double_operand | |
966 | This predicate accepts any @code{CONST_DOUBLE} expression that has | |
967 | exactly @var{mode}. If @var{mode} is @code{VOIDmode}, it will also | |
968 | accept @code{CONST_INT}. It is intended for immediate floating point | |
969 | constants. | |
970 | @end defun | |
971 | ||
972 | @noindent | |
973 | The second category of predicates allow only some kind of machine | |
974 | register. | |
975 | ||
976 | @defun register_operand | |
977 | This predicate allows any @code{REG} or @code{SUBREG} expression that | |
978 | is valid for @var{mode}. It is often suitable for arithmetic | |
979 | instruction operands on a RISC machine. | |
980 | @end defun | |
981 | ||
982 | @defun pmode_register_operand | |
983 | This is a slight variant on @code{register_operand} which works around | |
984 | a limitation in the machine-description reader. | |
985 | ||
986 | @smallexample | |
987 | (match_operand @var{n} "pmode_register_operand" @var{constraint}) | |
988 | @end smallexample | |
989 | ||
990 | @noindent | |
991 | means exactly what | |
992 | ||
993 | @smallexample | |
994 | (match_operand:P @var{n} "register_operand" @var{constraint}) | |
995 | @end smallexample | |
996 | ||
997 | @noindent | |
998 | would mean, if the machine-description reader accepted @samp{:P} | |
999 | mode suffixes. Unfortunately, it cannot, because @code{Pmode} is an | |
1000 | alias for some other mode, and might vary with machine-specific | |
1001 | options. @xref{Misc}. | |
1002 | @end defun | |
1003 | ||
1004 | @defun scratch_operand | |
1005 | This predicate allows hard registers and @code{SCRATCH} expressions, | |
1006 | but not pseudo-registers. It is used internally by @code{match_scratch}; | |
1007 | it should not be used directly. | |
1008 | @end defun | |
1009 | ||
1010 | @noindent | |
1011 | The third category of predicates allow only some kind of memory reference. | |
1012 | ||
1013 | @defun memory_operand | |
1014 | This predicate allows any valid reference to a quantity of mode | |
1015 | @var{mode} in memory, as determined by the weak form of | |
1016 | @code{GO_IF_LEGITIMATE_ADDRESS} (@pxref{Addressing Modes}). | |
1017 | @end defun | |
1018 | ||
1019 | @defun address_operand | |
1020 | This predicate is a little unusual; it allows any operand that is a | |
1021 | valid expression for the @emph{address} of a quantity of mode | |
1022 | @var{mode}, again determined by the weak form of | |
1023 | @code{GO_IF_LEGITIMATE_ADDRESS}. To first order, if | |
1024 | @samp{@w{(mem:@var{mode} (@var{exp}))}} is acceptable to | |
1025 | @code{memory_operand}, then @var{exp} is acceptable to | |
1026 | @code{address_operand}. Note that @var{exp} does not necessarily have | |
1027 | the mode @var{mode}. | |
1028 | @end defun | |
1029 | ||
1030 | @defun indirect_operand | |
1031 | This is a stricter form of @code{memory_operand} which allows only | |
1032 | memory references with a @code{general_operand} as the address | |
1033 | expression. New uses of this predicate are discouraged, because | |
1034 | @code{general_operand} is very permissive, so it's hard to tell what | |
1035 | an @code{indirect_operand} does or does not allow. If a target has | |
1036 | different requirements for memory operands for different instructions, | |
1037 | it is better to define target-specific predicates which enforce the | |
1038 | hardware's requirements explicitly. | |
1039 | @end defun | |
1040 | ||
1041 | @defun push_operand | |
1042 | This predicate allows a memory reference suitable for pushing a value | |
1043 | onto the stack. This will be a @code{MEM} which refers to | |
1044 | @code{stack_pointer_rtx}, with a side effect in its address expression | |
1045 | (@pxref{Incdec}); which one is determined by the | |
1046 | @code{STACK_PUSH_CODE} macro (@pxref{Frame Layout}). | |
1047 | @end defun | |
1048 | ||
1049 | @defun pop_operand | |
1050 | This predicate allows a memory reference suitable for popping a value | |
1051 | off the stack. Again, this will be a @code{MEM} referring to | |
1052 | @code{stack_pointer_rtx}, with a side effect in its address | |
1053 | expression. However, this time @code{STACK_POP_CODE} is expected. | |
1054 | @end defun | |
1055 | ||
1056 | @noindent | |
1057 | The fourth category of predicates allow some combination of the above | |
1058 | operands. | |
1059 | ||
1060 | @defun nonmemory_operand | |
1061 | This predicate allows any immediate or register operand valid for @var{mode}. | |
1062 | @end defun | |
1063 | ||
1064 | @defun nonimmediate_operand | |
1065 | This predicate allows any register or memory operand valid for @var{mode}. | |
1066 | @end defun | |
1067 | ||
1068 | @defun general_operand | |
1069 | This predicate allows any immediate, register, or memory operand | |
1070 | valid for @var{mode}. | |
1071 | @end defun | |
1072 | ||
1073 | @noindent | |
1074 | Finally, there are two generic operator predicates. | |
1075 | ||
1076 | @defun comparison_operator | |
1077 | This predicate matches any expression which performs an arithmetic | |
1078 | comparison in @var{mode}; that is, @code{COMPARISON_P} is true for the | |
1079 | expression code. | |
1080 | @end defun | |
1081 | ||
1082 | @defun ordered_comparison_operator | |
1083 | This predicate matches any expression which performs an arithmetic | |
1084 | comparison in @var{mode} and whose expression code is valid for integer | |
1085 | modes; that is, the expression code will be one of @code{eq}, @code{ne}, | |
1086 | @code{lt}, @code{ltu}, @code{le}, @code{leu}, @code{gt}, @code{gtu}, | |
1087 | @code{ge}, @code{geu}. | |
1088 | @end defun | |
1089 | ||
1090 | @node Defining Predicates | |
1091 | @subsection Defining Machine-Specific Predicates | |
1092 | @cindex defining predicates | |
1093 | @findex define_predicate | |
1094 | @findex define_special_predicate | |
1095 | ||
1096 | Many machines have requirements for their operands that cannot be | |
1097 | expressed precisely using the generic predicates. You can define | |
1098 | additional predicates using @code{define_predicate} and | |
1099 | @code{define_special_predicate} expressions. These expressions have | |
1100 | three operands: | |
1101 | ||
1102 | @itemize @bullet | |
1103 | @item | |
1104 | The name of the predicate, as it will be referred to in | |
1105 | @code{match_operand} or @code{match_operator} expressions. | |
1106 | ||
1107 | @item | |
1108 | An RTL expression which evaluates to true if the predicate allows the | |
1109 | operand @var{op}, false if it does not. This expression can only use | |
1110 | the following RTL codes: | |
1111 | ||
1112 | @table @code | |
1113 | @item MATCH_OPERAND | |
1114 | When written inside a predicate expression, a @code{MATCH_OPERAND} | |
1115 | expression evaluates to true if the predicate it names would allow | |
1116 | @var{op}. The operand number and constraint are ignored. Due to | |
1117 | limitations in @command{genrecog}, you can only refer to generic | |
1118 | predicates and predicates that have already been defined. | |
1119 | ||
1120 | @item MATCH_CODE | |
1121 | This expression evaluates to true if @var{op} or a specified | |
1122 | subexpression of @var{op} has one of a given list of RTX codes. | |
1123 | ||
1124 | The first operand of this expression is a string constant containing a | |
1125 | comma-separated list of RTX code names (in lower case). These are the | |
1126 | codes for which the @code{MATCH_CODE} will be true. | |
1127 | ||
1128 | The second operand is a string constant which indicates what | |
1129 | subexpression of @var{op} to examine. If it is absent or the empty | |
1130 | string, @var{op} itself is examined. Otherwise, the string constant | |
1131 | must be a sequence of digits and/or lowercase letters. Each character | |
1132 | indicates a subexpression to extract from the current expression; for | |
1133 | the first character this is @var{op}, for the second and subsequent | |
1134 | characters it is the result of the previous character. A digit | |
1135 | @var{n} extracts @samp{@w{XEXP (@var{e}, @var{n})}}; a letter @var{l} | |
1136 | extracts @samp{@w{XVECEXP (@var{e}, 0, @var{n})}} where @var{n} is the | |
1137 | alphabetic ordinal of @var{l} (0 for `a', 1 for 'b', and so on). The | |
1138 | @code{MATCH_CODE} then examines the RTX code of the subexpression | |
1139 | extracted by the complete string. It is not possible to extract | |
1140 | components of an @code{rtvec} that is not at position 0 within its RTX | |
1141 | object. | |
1142 | ||
1143 | @item MATCH_TEST | |
1144 | This expression has one operand, a string constant containing a C | |
1145 | expression. The predicate's arguments, @var{op} and @var{mode}, are | |
1146 | available with those names in the C expression. The @code{MATCH_TEST} | |
1147 | evaluates to true if the C expression evaluates to a nonzero value. | |
1148 | @code{MATCH_TEST} expressions must not have side effects. | |
1149 | ||
1150 | @item AND | |
1151 | @itemx IOR | |
1152 | @itemx NOT | |
1153 | @itemx IF_THEN_ELSE | |
1154 | The basic @samp{MATCH_} expressions can be combined using these | |
1155 | logical operators, which have the semantics of the C operators | |
1156 | @samp{&&}, @samp{||}, @samp{!}, and @samp{@w{? :}} respectively. As | |
1157 | in Common Lisp, you may give an @code{AND} or @code{IOR} expression an | |
1158 | arbitrary number of arguments; this has exactly the same effect as | |
1159 | writing a chain of two-argument @code{AND} or @code{IOR} expressions. | |
1160 | @end table | |
1161 | ||
1162 | @item | |
1163 | An optional block of C code, which should execute | |
1164 | @samp{@w{return true}} if the predicate is found to match and | |
1165 | @samp{@w{return false}} if it does not. It must not have any side | |
1166 | effects. The predicate arguments, @var{op} and @var{mode}, are | |
1167 | available with those names. | |
1168 | ||
1169 | If a code block is present in a predicate definition, then the RTL | |
1170 | expression must evaluate to true @emph{and} the code block must | |
1171 | execute @samp{@w{return true}} for the predicate to allow the operand. | |
1172 | The RTL expression is evaluated first; do not re-check anything in the | |
1173 | code block that was checked in the RTL expression. | |
1174 | @end itemize | |
1175 | ||
1176 | The program @command{genrecog} scans @code{define_predicate} and | |
1177 | @code{define_special_predicate} expressions to determine which RTX | |
1178 | codes are possibly allowed. You should always make this explicit in | |
1179 | the RTL predicate expression, using @code{MATCH_OPERAND} and | |
1180 | @code{MATCH_CODE}. | |
1181 | ||
1182 | Here is an example of a simple predicate definition, from the IA64 | |
1183 | machine description: | |
1184 | ||
1185 | @smallexample | |
1186 | @group | |
1187 | ;; @r{True if @var{op} is a @code{SYMBOL_REF} which refers to the sdata section.} | |
1188 | (define_predicate "small_addr_symbolic_operand" | |
1189 | (and (match_code "symbol_ref") | |
1190 | (match_test "SYMBOL_REF_SMALL_ADDR_P (op)"))) | |
1191 | @end group | |
1192 | @end smallexample | |
1193 | ||
1194 | @noindent | |
1195 | And here is another, showing the use of the C block. | |
1196 | ||
1197 | @smallexample | |
1198 | @group | |
1199 | ;; @r{True if @var{op} is a register operand that is (or could be) a GR reg.} | |
1200 | (define_predicate "gr_register_operand" | |
1201 | (match_operand 0 "register_operand") | |
1202 | @{ | |
1203 | unsigned int regno; | |
1204 | if (GET_CODE (op) == SUBREG) | |
1205 | op = SUBREG_REG (op); | |
1206 | ||
1207 | regno = REGNO (op); | |
1208 | return (regno >= FIRST_PSEUDO_REGISTER || GENERAL_REGNO_P (regno)); | |
1209 | @}) | |
1210 | @end group | |
1211 | @end smallexample | |
1212 | ||
1213 | Predicates written with @code{define_predicate} automatically include | |
1214 | a test that @var{mode} is @code{VOIDmode}, or @var{op} has the same | |
1215 | mode as @var{mode}, or @var{op} is a @code{CONST_INT} or | |
1216 | @code{CONST_DOUBLE}. They do @emph{not} check specifically for | |
1217 | integer @code{CONST_DOUBLE}, nor do they test that the value of either | |
1218 | kind of constant fits in the requested mode. This is because | |
1219 | target-specific predicates that take constants usually have to do more | |
1220 | stringent value checks anyway. If you need the exact same treatment | |
1221 | of @code{CONST_INT} or @code{CONST_DOUBLE} that the generic predicates | |
1222 | provide, use a @code{MATCH_OPERAND} subexpression to call | |
1223 | @code{const_int_operand}, @code{const_double_operand}, or | |
1224 | @code{immediate_operand}. | |
1225 | ||
1226 | Predicates written with @code{define_special_predicate} do not get any | |
1227 | automatic mode checks, and are treated as having special mode handling | |
1228 | by @command{genrecog}. | |
1229 | ||
1230 | The program @command{genpreds} is responsible for generating code to | |
1231 | test predicates. It also writes a header file containing function | |
1232 | declarations for all machine-specific predicates. It is not necessary | |
1233 | to declare these predicates in @file{@var{cpu}-protos.h}. | |
1234 | @end ifset | |
1235 | ||
1236 | @c Most of this node appears by itself (in a different place) even | |
1237 | @c when the INTERNALS flag is clear. Passages that require the internals | |
1238 | @c manual's context are conditionalized to appear only in the internals manual. | |
1239 | @ifset INTERNALS | |
1240 | @node Constraints | |
1241 | @section Operand Constraints | |
1242 | @cindex operand constraints | |
1243 | @cindex constraints | |
1244 | ||
1245 | Each @code{match_operand} in an instruction pattern can specify | |
1246 | constraints for the operands allowed. The constraints allow you to | |
1247 | fine-tune matching within the set of operands allowed by the | |
1248 | predicate. | |
1249 | ||
1250 | @end ifset | |
1251 | @ifclear INTERNALS | |
1252 | @node Constraints | |
1253 | @section Constraints for @code{asm} Operands | |
1254 | @cindex operand constraints, @code{asm} | |
1255 | @cindex constraints, @code{asm} | |
1256 | @cindex @code{asm} constraints | |
1257 | ||
1258 | Here are specific details on what constraint letters you can use with | |
1259 | @code{asm} operands. | |
1260 | @end ifclear | |
1261 | Constraints can say whether | |
1262 | an operand may be in a register, and which kinds of register; whether the | |
1263 | operand can be a memory reference, and which kinds of address; whether the | |
1264 | operand may be an immediate constant, and which possible values it may | |
1265 | have. Constraints can also require two operands to match. | |
1266 | Side-effects aren't allowed in operands of inline @code{asm}, unless | |
1267 | @samp{<} or @samp{>} constraints are used, because there is no guarantee | |
1268 | that the side effects will happen exactly once in an instruction that can update | |
1269 | the addressing register. | |
1270 | ||
1271 | @ifset INTERNALS | |
1272 | @menu | |
1273 | * Simple Constraints:: Basic use of constraints. | |
1274 | * Multi-Alternative:: When an insn has two alternative constraint-patterns. | |
1275 | * Class Preferences:: Constraints guide which hard register to put things in. | |
1276 | * Modifiers:: More precise control over effects of constraints. | |
1277 | * Machine Constraints:: Existing constraints for some particular machines. | |
1278 | * Disable Insn Alternatives:: Disable insn alternatives using attributes. | |
1279 | * Define Constraints:: How to define machine-specific constraints. | |
1280 | * C Constraint Interface:: How to test constraints from C code. | |
1281 | @end menu | |
1282 | @end ifset | |
1283 | ||
1284 | @ifclear INTERNALS | |
1285 | @menu | |
1286 | * Simple Constraints:: Basic use of constraints. | |
1287 | * Multi-Alternative:: When an insn has two alternative constraint-patterns. | |
1288 | * Modifiers:: More precise control over effects of constraints. | |
1289 | * Machine Constraints:: Special constraints for some particular machines. | |
1290 | @end menu | |
1291 | @end ifclear | |
1292 | ||
1293 | @node Simple Constraints | |
1294 | @subsection Simple Constraints | |
1295 | @cindex simple constraints | |
1296 | ||
1297 | The simplest kind of constraint is a string full of letters, each of | |
1298 | which describes one kind of operand that is permitted. Here are | |
1299 | the letters that are allowed: | |
1300 | ||
1301 | @table @asis | |
1302 | @item whitespace | |
1303 | Whitespace characters are ignored and can be inserted at any position | |
1304 | except the first. This enables each alternative for different operands to | |
1305 | be visually aligned in the machine description even if they have different | |
1306 | number of constraints and modifiers. | |
1307 | ||
1308 | @cindex @samp{m} in constraint | |
1309 | @cindex memory references in constraints | |
1310 | @item @samp{m} | |
1311 | A memory operand is allowed, with any kind of address that the machine | |
1312 | supports in general. | |
1313 | Note that the letter used for the general memory constraint can be | |
1314 | re-defined by a back end using the @code{TARGET_MEM_CONSTRAINT} macro. | |
1315 | ||
1316 | @cindex offsettable address | |
1317 | @cindex @samp{o} in constraint | |
1318 | @item @samp{o} | |
1319 | A memory operand is allowed, but only if the address is | |
1320 | @dfn{offsettable}. This means that adding a small integer (actually, | |
1321 | the width in bytes of the operand, as determined by its machine mode) | |
1322 | may be added to the address and the result is also a valid memory | |
1323 | address. | |
1324 | ||
1325 | @cindex autoincrement/decrement addressing | |
1326 | For example, an address which is constant is offsettable; so is an | |
1327 | address that is the sum of a register and a constant (as long as a | |
1328 | slightly larger constant is also within the range of address-offsets | |
1329 | supported by the machine); but an autoincrement or autodecrement | |
1330 | address is not offsettable. More complicated indirect/indexed | |
1331 | addresses may or may not be offsettable depending on the other | |
1332 | addressing modes that the machine supports. | |
1333 | ||
1334 | Note that in an output operand which can be matched by another | |
1335 | operand, the constraint letter @samp{o} is valid only when accompanied | |
1336 | by both @samp{<} (if the target machine has predecrement addressing) | |
1337 | and @samp{>} (if the target machine has preincrement addressing). | |
1338 | ||
1339 | @cindex @samp{V} in constraint | |
1340 | @item @samp{V} | |
1341 | A memory operand that is not offsettable. In other words, anything that | |
1342 | would fit the @samp{m} constraint but not the @samp{o} constraint. | |
1343 | ||
1344 | @cindex @samp{<} in constraint | |
1345 | @item @samp{<} | |
1346 | A memory operand with autodecrement addressing (either predecrement or | |
1347 | postdecrement) is allowed. In inline @code{asm} this constraint is only | |
1348 | allowed if the operand is used exactly once in an instruction that can | |
1349 | handle the side effects. Not using an operand with @samp{<} in constraint | |
1350 | string in the inline @code{asm} pattern at all or using it in multiple | |
1351 | instructions isn't valid, because the side effects wouldn't be performed | |
1352 | or would be performed more than once. Furthermore, on some targets | |
1353 | the operand with @samp{<} in constraint string must be accompanied by | |
1354 | special instruction suffixes like @code{%U0} instruction suffix on PowerPC | |
1355 | or @code{%P0} on IA-64. | |
1356 | ||
1357 | @cindex @samp{>} in constraint | |
1358 | @item @samp{>} | |
1359 | A memory operand with autoincrement addressing (either preincrement or | |
1360 | postincrement) is allowed. In inline @code{asm} the same restrictions | |
1361 | as for @samp{<} apply. | |
1362 | ||
1363 | @cindex @samp{r} in constraint | |
1364 | @cindex registers in constraints | |
1365 | @item @samp{r} | |
1366 | A register operand is allowed provided that it is in a general | |
1367 | register. | |
1368 | ||
1369 | @cindex constants in constraints | |
1370 | @cindex @samp{i} in constraint | |
1371 | @item @samp{i} | |
1372 | An immediate integer operand (one with constant value) is allowed. | |
1373 | This includes symbolic constants whose values will be known only at | |
1374 | assembly time or later. | |
1375 | ||
1376 | @cindex @samp{n} in constraint | |
1377 | @item @samp{n} | |
1378 | An immediate integer operand with a known numeric value is allowed. | |
1379 | Many systems cannot support assembly-time constants for operands less | |
1380 | than a word wide. Constraints for these operands should use @samp{n} | |
1381 | rather than @samp{i}. | |
1382 | ||
1383 | @cindex @samp{I} in constraint | |
1384 | @item @samp{I}, @samp{J}, @samp{K}, @dots{} @samp{P} | |
1385 | Other letters in the range @samp{I} through @samp{P} may be defined in | |
1386 | a machine-dependent fashion to permit immediate integer operands with | |
1387 | explicit integer values in specified ranges. For example, on the | |
1388 | 68000, @samp{I} is defined to stand for the range of values 1 to 8. | |
1389 | This is the range permitted as a shift count in the shift | |
1390 | instructions. | |
1391 | ||
1392 | @cindex @samp{E} in constraint | |
1393 | @item @samp{E} | |
1394 | An immediate floating operand (expression code @code{const_double}) is | |
1395 | allowed, but only if the target floating point format is the same as | |
1396 | that of the host machine (on which the compiler is running). | |
1397 | ||
1398 | @cindex @samp{F} in constraint | |
1399 | @item @samp{F} | |
1400 | An immediate floating operand (expression code @code{const_double} or | |
1401 | @code{const_vector}) is allowed. | |
1402 | ||
1403 | @cindex @samp{G} in constraint | |
1404 | @cindex @samp{H} in constraint | |
1405 | @item @samp{G}, @samp{H} | |
1406 | @samp{G} and @samp{H} may be defined in a machine-dependent fashion to | |
1407 | permit immediate floating operands in particular ranges of values. | |
1408 | ||
1409 | @cindex @samp{s} in constraint | |
1410 | @item @samp{s} | |
1411 | An immediate integer operand whose value is not an explicit integer is | |
1412 | allowed. | |
1413 | ||
1414 | This might appear strange; if an insn allows a constant operand with a | |
1415 | value not known at compile time, it certainly must allow any known | |
1416 | value. So why use @samp{s} instead of @samp{i}? Sometimes it allows | |
1417 | better code to be generated. | |
1418 | ||
1419 | For example, on the 68000 in a fullword instruction it is possible to | |
1420 | use an immediate operand; but if the immediate value is between @minus{}128 | |
1421 | and 127, better code results from loading the value into a register and | |
1422 | using the register. This is because the load into the register can be | |
1423 | done with a @samp{moveq} instruction. We arrange for this to happen | |
1424 | by defining the letter @samp{K} to mean ``any integer outside the | |
1425 | range @minus{}128 to 127'', and then specifying @samp{Ks} in the operand | |
1426 | constraints. | |
1427 | ||
1428 | @cindex @samp{g} in constraint | |
1429 | @item @samp{g} | |
1430 | Any register, memory or immediate integer operand is allowed, except for | |
1431 | registers that are not general registers. | |
1432 | ||
1433 | @cindex @samp{X} in constraint | |
1434 | @item @samp{X} | |
1435 | @ifset INTERNALS | |
1436 | Any operand whatsoever is allowed, even if it does not satisfy | |
1437 | @code{general_operand}. This is normally used in the constraint of | |
1438 | a @code{match_scratch} when certain alternatives will not actually | |
1439 | require a scratch register. | |
1440 | @end ifset | |
1441 | @ifclear INTERNALS | |
1442 | Any operand whatsoever is allowed. | |
1443 | @end ifclear | |
1444 | ||
1445 | @cindex @samp{0} in constraint | |
1446 | @cindex digits in constraint | |
1447 | @item @samp{0}, @samp{1}, @samp{2}, @dots{} @samp{9} | |
1448 | An operand that matches the specified operand number is allowed. If a | |
1449 | digit is used together with letters within the same alternative, the | |
1450 | digit should come last. | |
1451 | ||
1452 | This number is allowed to be more than a single digit. If multiple | |
1453 | digits are encountered consecutively, they are interpreted as a single | |
1454 | decimal integer. There is scant chance for ambiguity, since to-date | |
1455 | it has never been desirable that @samp{10} be interpreted as matching | |
1456 | either operand 1 @emph{or} operand 0. Should this be desired, one | |
1457 | can use multiple alternatives instead. | |
1458 | ||
1459 | @cindex matching constraint | |
1460 | @cindex constraint, matching | |
1461 | This is called a @dfn{matching constraint} and what it really means is | |
1462 | that the assembler has only a single operand that fills two roles | |
1463 | @ifset INTERNALS | |
1464 | considered separate in the RTL insn. For example, an add insn has two | |
1465 | input operands and one output operand in the RTL, but on most CISC | |
1466 | @end ifset | |
1467 | @ifclear INTERNALS | |
1468 | which @code{asm} distinguishes. For example, an add instruction uses | |
1469 | two input operands and an output operand, but on most CISC | |
1470 | @end ifclear | |
1471 | machines an add instruction really has only two operands, one of them an | |
1472 | input-output operand: | |
1473 | ||
1474 | @smallexample | |
1475 | addl #35,r12 | |
1476 | @end smallexample | |
1477 | ||
1478 | Matching constraints are used in these circumstances. | |
1479 | More precisely, the two operands that match must include one input-only | |
1480 | operand and one output-only operand. Moreover, the digit must be a | |
1481 | smaller number than the number of the operand that uses it in the | |
1482 | constraint. | |
1483 | ||
1484 | @ifset INTERNALS | |
1485 | For operands to match in a particular case usually means that they | |
1486 | are identical-looking RTL expressions. But in a few special cases | |
1487 | specific kinds of dissimilarity are allowed. For example, @code{*x} | |
1488 | as an input operand will match @code{*x++} as an output operand. | |
1489 | For proper results in such cases, the output template should always | |
1490 | use the output-operand's number when printing the operand. | |
1491 | @end ifset | |
1492 | ||
1493 | @cindex load address instruction | |
1494 | @cindex push address instruction | |
1495 | @cindex address constraints | |
1496 | @cindex @samp{p} in constraint | |
1497 | @item @samp{p} | |
1498 | An operand that is a valid memory address is allowed. This is | |
1499 | for ``load address'' and ``push address'' instructions. | |
1500 | ||
1501 | @findex address_operand | |
1502 | @samp{p} in the constraint must be accompanied by @code{address_operand} | |
1503 | as the predicate in the @code{match_operand}. This predicate interprets | |
1504 | the mode specified in the @code{match_operand} as the mode of the memory | |
1505 | reference for which the address would be valid. | |
1506 | ||
1507 | @cindex other register constraints | |
1508 | @cindex extensible constraints | |
1509 | @item @var{other-letters} | |
1510 | Other letters can be defined in machine-dependent fashion to stand for | |
1511 | particular classes of registers or other arbitrary operand types. | |
1512 | @samp{d}, @samp{a} and @samp{f} are defined on the 68000/68020 to stand | |
1513 | for data, address and floating point registers. | |
1514 | @end table | |
1515 | ||
1516 | @ifset INTERNALS | |
1517 | In order to have valid assembler code, each operand must satisfy | |
1518 | its constraint. But a failure to do so does not prevent the pattern | |
1519 | from applying to an insn. Instead, it directs the compiler to modify | |
1520 | the code so that the constraint will be satisfied. Usually this is | |
1521 | done by copying an operand into a register. | |
1522 | ||
1523 | Contrast, therefore, the two instruction patterns that follow: | |
1524 | ||
1525 | @smallexample | |
1526 | (define_insn "" | |
1527 | [(set (match_operand:SI 0 "general_operand" "=r") | |
1528 | (plus:SI (match_dup 0) | |
1529 | (match_operand:SI 1 "general_operand" "r")))] | |
1530 | "" | |
1531 | "@dots{}") | |
1532 | @end smallexample | |
1533 | ||
1534 | @noindent | |
1535 | which has two operands, one of which must appear in two places, and | |
1536 | ||
1537 | @smallexample | |
1538 | (define_insn "" | |
1539 | [(set (match_operand:SI 0 "general_operand" "=r") | |
1540 | (plus:SI (match_operand:SI 1 "general_operand" "0") | |
1541 | (match_operand:SI 2 "general_operand" "r")))] | |
1542 | "" | |
1543 | "@dots{}") | |
1544 | @end smallexample | |
1545 | ||
1546 | @noindent | |
1547 | which has three operands, two of which are required by a constraint to be | |
1548 | identical. If we are considering an insn of the form | |
1549 | ||
1550 | @smallexample | |
1551 | (insn @var{n} @var{prev} @var{next} | |
1552 | (set (reg:SI 3) | |
1553 | (plus:SI (reg:SI 6) (reg:SI 109))) | |
1554 | @dots{}) | |
1555 | @end smallexample | |
1556 | ||
1557 | @noindent | |
1558 | the first pattern would not apply at all, because this insn does not | |
1559 | contain two identical subexpressions in the right place. The pattern would | |
1560 | say, ``That does not look like an add instruction; try other patterns''. | |
1561 | The second pattern would say, ``Yes, that's an add instruction, but there | |
1562 | is something wrong with it''. It would direct the reload pass of the | |
1563 | compiler to generate additional insns to make the constraint true. The | |
1564 | results might look like this: | |
1565 | ||
1566 | @smallexample | |
1567 | (insn @var{n2} @var{prev} @var{n} | |
1568 | (set (reg:SI 3) (reg:SI 6)) | |
1569 | @dots{}) | |
1570 | ||
1571 | (insn @var{n} @var{n2} @var{next} | |
1572 | (set (reg:SI 3) | |
1573 | (plus:SI (reg:SI 3) (reg:SI 109))) | |
1574 | @dots{}) | |
1575 | @end smallexample | |
1576 | ||
1577 | It is up to you to make sure that each operand, in each pattern, has | |
1578 | constraints that can handle any RTL expression that could be present for | |
1579 | that operand. (When multiple alternatives are in use, each pattern must, | |
1580 | for each possible combination of operand expressions, have at least one | |
1581 | alternative which can handle that combination of operands.) The | |
1582 | constraints don't need to @emph{allow} any possible operand---when this is | |
1583 | the case, they do not constrain---but they must at least point the way to | |
1584 | reloading any possible operand so that it will fit. | |
1585 | ||
1586 | @itemize @bullet | |
1587 | @item | |
1588 | If the constraint accepts whatever operands the predicate permits, | |
1589 | there is no problem: reloading is never necessary for this operand. | |
1590 | ||
1591 | For example, an operand whose constraints permit everything except | |
1592 | registers is safe provided its predicate rejects registers. | |
1593 | ||
1594 | An operand whose predicate accepts only constant values is safe | |
1595 | provided its constraints include the letter @samp{i}. If any possible | |
1596 | constant value is accepted, then nothing less than @samp{i} will do; | |
1597 | if the predicate is more selective, then the constraints may also be | |
1598 | more selective. | |
1599 | ||
1600 | @item | |
1601 | Any operand expression can be reloaded by copying it into a register. | |
1602 | So if an operand's constraints allow some kind of register, it is | |
1603 | certain to be safe. It need not permit all classes of registers; the | |
1604 | compiler knows how to copy a register into another register of the | |
1605 | proper class in order to make an instruction valid. | |
1606 | ||
1607 | @cindex nonoffsettable memory reference | |
1608 | @cindex memory reference, nonoffsettable | |
1609 | @item | |
1610 | A nonoffsettable memory reference can be reloaded by copying the | |
1611 | address into a register. So if the constraint uses the letter | |
1612 | @samp{o}, all memory references are taken care of. | |
1613 | ||
1614 | @item | |
1615 | A constant operand can be reloaded by allocating space in memory to | |
1616 | hold it as preinitialized data. Then the memory reference can be used | |
1617 | in place of the constant. So if the constraint uses the letters | |
1618 | @samp{o} or @samp{m}, constant operands are not a problem. | |
1619 | ||
1620 | @item | |
1621 | If the constraint permits a constant and a pseudo register used in an insn | |
1622 | was not allocated to a hard register and is equivalent to a constant, | |
1623 | the register will be replaced with the constant. If the predicate does | |
1624 | not permit a constant and the insn is re-recognized for some reason, the | |
1625 | compiler will crash. Thus the predicate must always recognize any | |
1626 | objects allowed by the constraint. | |
1627 | @end itemize | |
1628 | ||
1629 | If the operand's predicate can recognize registers, but the constraint does | |
1630 | not permit them, it can make the compiler crash. When this operand happens | |
1631 | to be a register, the reload pass will be stymied, because it does not know | |
1632 | how to copy a register temporarily into memory. | |
1633 | ||
1634 | If the predicate accepts a unary operator, the constraint applies to the | |
1635 | operand. For example, the MIPS processor at ISA level 3 supports an | |
1636 | instruction which adds two registers in @code{SImode} to produce a | |
1637 | @code{DImode} result, but only if the registers are correctly sign | |
1638 | extended. This predicate for the input operands accepts a | |
1639 | @code{sign_extend} of an @code{SImode} register. Write the constraint | |
1640 | to indicate the type of register that is required for the operand of the | |
1641 | @code{sign_extend}. | |
1642 | @end ifset | |
1643 | ||
1644 | @node Multi-Alternative | |
1645 | @subsection Multiple Alternative Constraints | |
1646 | @cindex multiple alternative constraints | |
1647 | ||
1648 | Sometimes a single instruction has multiple alternative sets of possible | |
1649 | operands. For example, on the 68000, a logical-or instruction can combine | |
1650 | register or an immediate value into memory, or it can combine any kind of | |
1651 | operand into a register; but it cannot combine one memory location into | |
1652 | another. | |
1653 | ||
1654 | These constraints are represented as multiple alternatives. An alternative | |
1655 | can be described by a series of letters for each operand. The overall | |
1656 | constraint for an operand is made from the letters for this operand | |
1657 | from the first alternative, a comma, the letters for this operand from | |
1658 | the second alternative, a comma, and so on until the last alternative. | |
1659 | All operands for a single instruction must have the same number of | |
1660 | alternatives. | |
1661 | @ifset INTERNALS | |
1662 | Here is how it is done for fullword logical-or on the 68000: | |
1663 | ||
1664 | @smallexample | |
1665 | (define_insn "iorsi3" | |
1666 | [(set (match_operand:SI 0 "general_operand" "=m,d") | |
1667 | (ior:SI (match_operand:SI 1 "general_operand" "%0,0") | |
1668 | (match_operand:SI 2 "general_operand" "dKs,dmKs")))] | |
1669 | @dots{}) | |
1670 | @end smallexample | |
1671 | ||
1672 | The first alternative has @samp{m} (memory) for operand 0, @samp{0} for | |
1673 | operand 1 (meaning it must match operand 0), and @samp{dKs} for operand | |
1674 | 2. The second alternative has @samp{d} (data register) for operand 0, | |
1675 | @samp{0} for operand 1, and @samp{dmKs} for operand 2. The @samp{=} and | |
1676 | @samp{%} in the constraints apply to all the alternatives; their | |
e48864e5 | 1677 | meaning is explained in a later section (@pxref{Modifiers}). |
d77de738 ML |
1678 | |
1679 | If all the operands fit any one alternative, the instruction is valid. | |
1680 | Otherwise, for each alternative, the compiler counts how many instructions | |
1681 | must be added to copy the operands so that that alternative applies. | |
1682 | The alternative requiring the least copying is chosen. If two alternatives | |
1683 | need the same amount of copying, the one that comes first is chosen. | |
1684 | These choices can be altered with the @samp{?} and @samp{!} characters: | |
1685 | ||
1686 | @table @code | |
1687 | @cindex @samp{?} in constraint | |
1688 | @cindex question mark | |
1689 | @item ? | |
1690 | Disparage slightly the alternative that the @samp{?} appears in, | |
1691 | as a choice when no alternative applies exactly. The compiler regards | |
1692 | this alternative as one unit more costly for each @samp{?} that appears | |
1693 | in it. | |
1694 | ||
1695 | @cindex @samp{!} in constraint | |
1696 | @cindex exclamation point | |
1697 | @item ! | |
1698 | Disparage severely the alternative that the @samp{!} appears in. | |
1699 | This alternative can still be used if it fits without reloading, | |
1700 | but if reloading is needed, some other alternative will be used. | |
1701 | ||
1702 | @cindex @samp{^} in constraint | |
1703 | @cindex caret | |
1704 | @item ^ | |
1705 | This constraint is analogous to @samp{?} but it disparages slightly | |
1706 | the alternative only if the operand with the @samp{^} needs a reload. | |
1707 | ||
1708 | @cindex @samp{$} in constraint | |
1709 | @cindex dollar sign | |
1710 | @item $ | |
1711 | This constraint is analogous to @samp{!} but it disparages severely | |
1712 | the alternative only if the operand with the @samp{$} needs a reload. | |
1713 | @end table | |
1714 | ||
1715 | When an insn pattern has multiple alternatives in its constraints, often | |
1716 | the appearance of the assembler code is determined mostly by which | |
1717 | alternative was matched. When this is so, the C code for writing the | |
1718 | assembler code can use the variable @code{which_alternative}, which is | |
1719 | the ordinal number of the alternative that was actually satisfied (0 for | |
1720 | the first, 1 for the second alternative, etc.). @xref{Output Statement}. | |
1721 | @end ifset | |
1722 | @ifclear INTERNALS | |
1723 | ||
1724 | So the first alternative for the 68000's logical-or could be written as | |
1725 | @code{"+m" (output) : "ir" (input)}. The second could be @code{"+r" | |
1726 | (output): "irm" (input)}. However, the fact that two memory locations | |
1727 | cannot be used in a single instruction prevents simply using @code{"+rm" | |
1728 | (output) : "irm" (input)}. Using multi-alternatives, this might be | |
1729 | written as @code{"+m,r" (output) : "ir,irm" (input)}. This describes | |
1730 | all the available alternatives to the compiler, allowing it to choose | |
1731 | the most efficient one for the current conditions. | |
1732 | ||
1733 | There is no way within the template to determine which alternative was | |
1734 | chosen. However you may be able to wrap your @code{asm} statements with | |
1735 | builtins such as @code{__builtin_constant_p} to achieve the desired results. | |
1736 | @end ifclear | |
1737 | ||
1738 | @ifset INTERNALS | |
1739 | @node Class Preferences | |
1740 | @subsection Register Class Preferences | |
1741 | @cindex class preference constraints | |
1742 | @cindex register class preference constraints | |
1743 | ||
1744 | @cindex voting between constraint alternatives | |
1745 | The operand constraints have another function: they enable the compiler | |
1746 | to decide which kind of hardware register a pseudo register is best | |
1747 | allocated to. The compiler examines the constraints that apply to the | |
1748 | insns that use the pseudo register, looking for the machine-dependent | |
1749 | letters such as @samp{d} and @samp{a} that specify classes of registers. | |
1750 | The pseudo register is put in whichever class gets the most ``votes''. | |
1751 | The constraint letters @samp{g} and @samp{r} also vote: they vote in | |
1752 | favor of a general register. The machine description says which registers | |
1753 | are considered general. | |
1754 | ||
1755 | Of course, on some machines all registers are equivalent, and no register | |
1756 | classes are defined. Then none of this complexity is relevant. | |
1757 | @end ifset | |
1758 | ||
1759 | @node Modifiers | |
1760 | @subsection Constraint Modifier Characters | |
1761 | @cindex modifiers in constraints | |
1762 | @cindex constraint modifier characters | |
1763 | ||
1764 | @c prevent bad page break with this line | |
1765 | Here are constraint modifier characters. | |
1766 | ||
1767 | @table @samp | |
1768 | @cindex @samp{=} in constraint | |
1769 | @item = | |
1770 | Means that this operand is written to by this instruction: | |
1771 | the previous value is discarded and replaced by new data. | |
1772 | ||
1773 | @cindex @samp{+} in constraint | |
1774 | @item + | |
1775 | Means that this operand is both read and written by the instruction. | |
1776 | ||
1777 | When the compiler fixes up the operands to satisfy the constraints, | |
1778 | it needs to know which operands are read by the instruction and | |
1779 | which are written by it. @samp{=} identifies an operand which is only | |
1780 | written; @samp{+} identifies an operand that is both read and written; all | |
1781 | other operands are assumed to only be read. | |
1782 | ||
1783 | If you specify @samp{=} or @samp{+} in a constraint, you put it in the | |
1784 | first character of the constraint string. | |
1785 | ||
1786 | @cindex @samp{&} in constraint | |
1787 | @cindex earlyclobber operand | |
1788 | @item & | |
1789 | Means (in a particular alternative) that this operand is an | |
1790 | @dfn{earlyclobber} operand, which is written before the instruction is | |
1791 | finished using the input operands. Therefore, this operand may not lie | |
1792 | in a register that is read by the instruction or as part of any memory | |
1793 | address. | |
1794 | ||
1795 | @samp{&} applies only to the alternative in which it is written. In | |
1796 | constraints with multiple alternatives, sometimes one alternative | |
1797 | requires @samp{&} while others do not. See, for example, the | |
1798 | @samp{movdf} insn of the 68000. | |
1799 | ||
1800 | An operand which is read by the instruction can be tied to an earlyclobber | |
1801 | operand if its only use as an input occurs before the early result is | |
1802 | written. Adding alternatives of this form often allows GCC to produce | |
1803 | better code when only some of the read operands can be affected by the | |
1804 | earlyclobber. See, for example, the @samp{mulsi3} insn of the ARM@. | |
1805 | ||
1806 | Furthermore, if the @dfn{earlyclobber} operand is also a read/write | |
1807 | operand, then that operand is written only after it's used. | |
1808 | ||
1809 | @samp{&} does not obviate the need to write @samp{=} or @samp{+}. As | |
1810 | @dfn{earlyclobber} operands are always written, a read-only | |
1811 | @dfn{earlyclobber} operand is ill-formed and will be rejected by the | |
1812 | compiler. | |
1813 | ||
1814 | @cindex @samp{%} in constraint | |
1815 | @item % | |
1816 | Declares the instruction to be commutative for this operand and the | |
1817 | following operand. This means that the compiler may interchange the | |
1818 | two operands if that is the cheapest way to make all operands fit the | |
1819 | constraints. @samp{%} applies to all alternatives and must appear as | |
1820 | the first character in the constraint. Only read-only operands can use | |
1821 | @samp{%}. | |
1822 | ||
1823 | @ifset INTERNALS | |
1824 | This is often used in patterns for addition instructions | |
1825 | that really have only two operands: the result must go in one of the | |
1826 | arguments. Here for example, is how the 68000 halfword-add | |
1827 | instruction is defined: | |
1828 | ||
1829 | @smallexample | |
1830 | (define_insn "addhi3" | |
1831 | [(set (match_operand:HI 0 "general_operand" "=m,r") | |
1832 | (plus:HI (match_operand:HI 1 "general_operand" "%0,0") | |
1833 | (match_operand:HI 2 "general_operand" "di,g")))] | |
1834 | @dots{}) | |
1835 | @end smallexample | |
1836 | @end ifset | |
1837 | GCC can only handle one commutative pair in an asm; if you use more, | |
1838 | the compiler may fail. Note that you need not use the modifier if | |
1839 | the two alternatives are strictly identical; this would only waste | |
1840 | time in the reload pass. | |
1841 | @ifset INTERNALS | |
1842 | The modifier is not operational after | |
1843 | register allocation, so the result of @code{define_peephole2} | |
1844 | and @code{define_split}s performed after reload cannot rely on | |
1845 | @samp{%} to make the intended insn match. | |
1846 | ||
1847 | @cindex @samp{#} in constraint | |
1848 | @item # | |
1849 | Says that all following characters, up to the next comma, are to be | |
1850 | ignored as a constraint. They are significant only for choosing | |
1851 | register preferences. | |
1852 | ||
1853 | @cindex @samp{*} in constraint | |
1854 | @item * | |
1855 | Says that the following character should be ignored when choosing | |
1856 | register preferences. @samp{*} has no effect on the meaning of the | |
1857 | constraint as a constraint, and no effect on reloading. For LRA | |
1858 | @samp{*} additionally disparages slightly the alternative if the | |
1859 | following character matches the operand. | |
1860 | ||
1861 | Here is an example: the 68000 has an instruction to sign-extend a | |
1862 | halfword in a data register, and can also sign-extend a value by | |
1863 | copying it into an address register. While either kind of register is | |
1864 | acceptable, the constraints on an address-register destination are | |
1865 | less strict, so it is best if register allocation makes an address | |
1866 | register its goal. Therefore, @samp{*} is used so that the @samp{d} | |
1867 | constraint letter (for data register) is ignored when computing | |
1868 | register preferences. | |
1869 | ||
1870 | @smallexample | |
1871 | (define_insn "extendhisi2" | |
1872 | [(set (match_operand:SI 0 "general_operand" "=*d,a") | |
1873 | (sign_extend:SI | |
1874 | (match_operand:HI 1 "general_operand" "0,g")))] | |
1875 | @dots{}) | |
1876 | @end smallexample | |
1877 | @end ifset | |
1878 | @end table | |
1879 | ||
1880 | @node Machine Constraints | |
1881 | @subsection Constraints for Particular Machines | |
1882 | @cindex machine specific constraints | |
1883 | @cindex constraints, machine specific | |
1884 | ||
1885 | Whenever possible, you should use the general-purpose constraint letters | |
1886 | in @code{asm} arguments, since they will convey meaning more readily to | |
1887 | people reading your code. Failing that, use the constraint letters | |
1888 | that usually have very similar meanings across architectures. The most | |
1889 | commonly used constraints are @samp{m} and @samp{r} (for memory and | |
1890 | general-purpose registers respectively; @pxref{Simple Constraints}), and | |
1891 | @samp{I}, usually the letter indicating the most common | |
1892 | immediate-constant format. | |
1893 | ||
1894 | Each architecture defines additional constraints. These constraints | |
1895 | are used by the compiler itself for instruction generation, as well as | |
1896 | for @code{asm} statements; therefore, some of the constraints are not | |
1897 | particularly useful for @code{asm}. Here is a summary of some of the | |
1898 | machine-dependent constraints available on some particular machines; | |
1899 | it includes both constraints that are useful for @code{asm} and | |
1900 | constraints that aren't. The compiler source file mentioned in the | |
1901 | table heading for each architecture is the definitive reference for | |
1902 | the meanings of that architecture's constraints. | |
1903 | ||
1904 | @c Please keep this table alphabetized by target! | |
1905 | @table @emph | |
1906 | @item AArch64 family---@file{config/aarch64/constraints.md} | |
1907 | @table @code | |
1908 | @item k | |
1909 | The stack pointer register (@code{SP}) | |
1910 | ||
1911 | @item w | |
1912 | Floating point register, Advanced SIMD vector register or SVE vector register | |
1913 | ||
1914 | @item x | |
1915 | Like @code{w}, but restricted to registers 0 to 15 inclusive. | |
1916 | ||
1917 | @item y | |
1918 | Like @code{w}, but restricted to registers 0 to 7 inclusive. | |
1919 | ||
1920 | @item Upl | |
1921 | One of the low eight SVE predicate registers (@code{P0} to @code{P7}) | |
1922 | ||
1923 | @item Upa | |
1924 | Any of the SVE predicate registers (@code{P0} to @code{P15}) | |
1925 | ||
1926 | @item I | |
1927 | Integer constant that is valid as an immediate operand in an @code{ADD} | |
1928 | instruction | |
1929 | ||
1930 | @item J | |
1931 | Integer constant that is valid as an immediate operand in a @code{SUB} | |
1932 | instruction (once negated) | |
1933 | ||
1934 | @item K | |
1935 | Integer constant that can be used with a 32-bit logical instruction | |
1936 | ||
1937 | @item L | |
1938 | Integer constant that can be used with a 64-bit logical instruction | |
1939 | ||
1940 | @item M | |
1941 | Integer constant that is valid as an immediate operand in a 32-bit @code{MOV} | |
1942 | pseudo instruction. The @code{MOV} may be assembled to one of several different | |
1943 | machine instructions depending on the value | |
1944 | ||
1945 | @item N | |
1946 | Integer constant that is valid as an immediate operand in a 64-bit @code{MOV} | |
1947 | pseudo instruction | |
1948 | ||
1949 | @item S | |
1950 | An absolute symbolic address or a label reference | |
1951 | ||
1952 | @item Y | |
1953 | Floating point constant zero | |
1954 | ||
1955 | @item Z | |
1956 | Integer constant zero | |
1957 | ||
1958 | @item Ush | |
1959 | The high part (bits 12 and upwards) of the pc-relative address of a symbol | |
1960 | within 4GB of the instruction | |
1961 | ||
1962 | @item Q | |
1963 | A memory address which uses a single base register with no offset | |
1964 | ||
1965 | @item Ump | |
1966 | A memory address suitable for a load/store pair instruction in SI, DI, SF and | |
1967 | DF modes | |
1968 | ||
1969 | @end table | |
1970 | ||
1971 | ||
1972 | @item AMD GCN ---@file{config/gcn/constraints.md} | |
1973 | @table @code | |
1974 | @item I | |
1975 | Immediate integer in the range @minus{}16 to 64 | |
1976 | ||
1977 | @item J | |
1978 | Immediate 16-bit signed integer | |
1979 | ||
1980 | @item Kf | |
1981 | Immediate constant @minus{}1 | |
1982 | ||
1983 | @item L | |
1984 | Immediate 15-bit unsigned integer | |
1985 | ||
1986 | @item A | |
1987 | Immediate constant that can be inlined in an instruction encoding: integer | |
1988 | @minus{}16..64, or float 0.0, +/@minus{}0.5, +/@minus{}1.0, +/@minus{}2.0, | |
1989 | +/@minus{}4.0, 1.0/(2.0*PI) | |
1990 | ||
1991 | @item B | |
1992 | Immediate 32-bit signed integer that can be attached to an instruction encoding | |
1993 | ||
1994 | @item C | |
1995 | Immediate 32-bit integer in range @minus{}16..4294967295 (i.e. 32-bit unsigned | |
1996 | integer or @samp{A} constraint) | |
1997 | ||
1998 | @item DA | |
1999 | Immediate 64-bit constant that can be split into two @samp{A} constants | |
2000 | ||
2001 | @item DB | |
2002 | Immediate 64-bit constant that can be split into two @samp{B} constants | |
2003 | ||
2004 | @item U | |
2005 | Any @code{unspec} | |
2006 | ||
2007 | @item Y | |
2008 | Any @code{symbol_ref} or @code{label_ref} | |
2009 | ||
2010 | @item v | |
2011 | VGPR register | |
2012 | ||
2013 | @item Sg | |
2014 | SGPR register | |
2015 | ||
2016 | @item SD | |
2017 | SGPR registers valid for instruction destinations, including VCC, M0 and EXEC | |
2018 | ||
2019 | @item SS | |
2020 | SGPR registers valid for instruction sources, including VCC, M0, EXEC and SCC | |
2021 | ||
2022 | @item Sm | |
2023 | SGPR registers valid as a source for scalar memory instructions (excludes M0 | |
2024 | and EXEC) | |
2025 | ||
2026 | @item Sv | |
2027 | SGPR registers valid as a source or destination for vector instructions | |
2028 | (excludes EXEC) | |
2029 | ||
2030 | @item ca | |
2031 | All condition registers: SCC, VCCZ, EXECZ | |
2032 | ||
2033 | @item cs | |
2034 | Scalar condition register: SCC | |
2035 | ||
2036 | @item cV | |
2037 | Vector condition register: VCC, VCC_LO, VCC_HI | |
2038 | ||
2039 | @item e | |
2040 | EXEC register (EXEC_LO and EXEC_HI) | |
2041 | ||
2042 | @item RB | |
2043 | Memory operand with address space suitable for @code{buffer_*} instructions | |
2044 | ||
2045 | @item RF | |
2046 | Memory operand with address space suitable for @code{flat_*} instructions | |
2047 | ||
2048 | @item RS | |
2049 | Memory operand with address space suitable for @code{s_*} instructions | |
2050 | ||
2051 | @item RL | |
2052 | Memory operand with address space suitable for @code{ds_*} LDS instructions | |
2053 | ||
2054 | @item RG | |
2055 | Memory operand with address space suitable for @code{ds_*} GDS instructions | |
2056 | ||
2057 | @item RD | |
2058 | Memory operand with address space suitable for any @code{ds_*} instructions | |
2059 | ||
2060 | @item RM | |
2061 | Memory operand with address space suitable for @code{global_*} instructions | |
2062 | ||
2063 | @end table | |
2064 | ||
2065 | ||
2066 | @item ARC ---@file{config/arc/constraints.md} | |
2067 | @table @code | |
2068 | @item q | |
2069 | Registers usable in ARCompact 16-bit instructions: @code{r0}-@code{r3}, | |
2070 | @code{r12}-@code{r15}. This constraint can only match when the @option{-mq} | |
2071 | option is in effect. | |
2072 | ||
2073 | @item e | |
2074 | Registers usable as base-regs of memory addresses in ARCompact 16-bit memory | |
2075 | instructions: @code{r0}-@code{r3}, @code{r12}-@code{r15}, @code{sp}. | |
2076 | This constraint can only match when the @option{-mq} | |
2077 | option is in effect. | |
2078 | @item D | |
2079 | ARC FPX (dpfp) 64-bit registers. @code{D0}, @code{D1}. | |
2080 | ||
2081 | @item I | |
2082 | A signed 12-bit integer constant. | |
2083 | ||
2084 | @item Cal | |
2085 | constant for arithmetic/logical operations. This might be any constant | |
2086 | that can be put into a long immediate by the assmbler or linker without | |
2087 | involving a PIC relocation. | |
2088 | ||
2089 | @item K | |
2090 | A 3-bit unsigned integer constant. | |
2091 | ||
2092 | @item L | |
2093 | A 6-bit unsigned integer constant. | |
2094 | ||
2095 | @item CnL | |
2096 | One's complement of a 6-bit unsigned integer constant. | |
2097 | ||
2098 | @item CmL | |
2099 | Two's complement of a 6-bit unsigned integer constant. | |
2100 | ||
2101 | @item M | |
2102 | A 5-bit unsigned integer constant. | |
2103 | ||
2104 | @item O | |
2105 | A 7-bit unsigned integer constant. | |
2106 | ||
2107 | @item P | |
2108 | A 8-bit unsigned integer constant. | |
2109 | ||
2110 | @item H | |
2111 | Any const_double value. | |
2112 | @end table | |
2113 | ||
2114 | @item ARM family---@file{config/arm/constraints.md} | |
2115 | @table @code | |
2116 | ||
2117 | @item h | |
2118 | In Thumb state, the core registers @code{r8}-@code{r15}. | |
2119 | ||
2120 | @item k | |
2121 | The stack pointer register. | |
2122 | ||
2123 | @item l | |
2124 | In Thumb State the core registers @code{r0}-@code{r7}. In ARM state this | |
2125 | is an alias for the @code{r} constraint. | |
2126 | ||
2127 | @item t | |
2128 | VFP floating-point registers @code{s0}-@code{s31}. Used for 32 bit values. | |
2129 | ||
2130 | @item w | |
2131 | VFP floating-point registers @code{d0}-@code{d31} and the appropriate | |
2132 | subset @code{d0}-@code{d15} based on command line options. | |
2133 | Used for 64 bit values only. Not valid for Thumb1. | |
2134 | ||
2135 | @item y | |
2136 | The iWMMX co-processor registers. | |
2137 | ||
2138 | @item z | |
2139 | The iWMMX GR registers. | |
2140 | ||
2141 | @item G | |
2142 | The floating-point constant 0.0 | |
2143 | ||
2144 | @item I | |
2145 | Integer that is valid as an immediate operand in a data processing | |
2146 | instruction. That is, an integer in the range 0 to 255 rotated by a | |
2147 | multiple of 2 | |
2148 | ||
2149 | @item J | |
2150 | Integer in the range @minus{}4095 to 4095 | |
2151 | ||
2152 | @item K | |
2153 | Integer that satisfies constraint @samp{I} when inverted (ones complement) | |
2154 | ||
2155 | @item L | |
2156 | Integer that satisfies constraint @samp{I} when negated (twos complement) | |
2157 | ||
2158 | @item M | |
2159 | Integer in the range 0 to 32 | |
2160 | ||
2161 | @item Q | |
2162 | A memory reference where the exact address is in a single register | |
2163 | (`@samp{m}' is preferable for @code{asm} statements) | |
2164 | ||
2165 | @item R | |
2166 | An item in the constant pool | |
2167 | ||
2168 | @item S | |
2169 | A symbol in the text segment of the current file | |
2170 | ||
2171 | @item Uv | |
2172 | A memory reference suitable for VFP load/store insns (reg+constant offset) | |
2173 | ||
2174 | @item Uy | |
2175 | A memory reference suitable for iWMMXt load/store instructions. | |
2176 | ||
2177 | @item Uq | |
2178 | A memory reference suitable for the ARMv4 ldrsb instruction. | |
2179 | @end table | |
2180 | ||
2181 | @item AVR family---@file{config/avr/constraints.md} | |
2182 | @table @code | |
2183 | @item l | |
2184 | Registers from r0 to r15 | |
2185 | ||
2186 | @item a | |
2187 | Registers from r16 to r23 | |
2188 | ||
2189 | @item d | |
2190 | Registers from r16 to r31 | |
2191 | ||
2192 | @item w | |
2193 | Registers from r24 to r31. These registers can be used in @samp{adiw} command | |
2194 | ||
2195 | @item e | |
2196 | Pointer register (r26--r31) | |
2197 | ||
2198 | @item b | |
2199 | Base pointer register (r28--r31) | |
2200 | ||
2201 | @item q | |
2202 | Stack pointer register (SPH:SPL) | |
2203 | ||
2204 | @item t | |
2205 | Temporary register r0 | |
2206 | ||
2207 | @item x | |
2208 | Register pair X (r27:r26) | |
2209 | ||
2210 | @item y | |
2211 | Register pair Y (r29:r28) | |
2212 | ||
2213 | @item z | |
2214 | Register pair Z (r31:r30) | |
2215 | ||
2216 | @item I | |
2217 | Constant greater than @minus{}1, less than 64 | |
2218 | ||
2219 | @item J | |
2220 | Constant greater than @minus{}64, less than 1 | |
2221 | ||
2222 | @item K | |
2223 | Constant integer 2 | |
2224 | ||
2225 | @item L | |
2226 | Constant integer 0 | |
2227 | ||
2228 | @item M | |
2229 | Constant that fits in 8 bits | |
2230 | ||
2231 | @item N | |
2232 | Constant integer @minus{}1 | |
2233 | ||
2234 | @item O | |
2235 | Constant integer 8, 16, or 24 | |
2236 | ||
2237 | @item P | |
2238 | Constant integer 1 | |
2239 | ||
2240 | @item G | |
2241 | A floating point constant 0.0 | |
2242 | ||
2243 | @item Q | |
2244 | A memory address based on Y or Z pointer with displacement. | |
2245 | @end table | |
2246 | ||
2247 | @item Blackfin family---@file{config/bfin/constraints.md} | |
2248 | @table @code | |
2249 | @item a | |
2250 | P register | |
2251 | ||
2252 | @item d | |
2253 | D register | |
2254 | ||
2255 | @item z | |
2256 | A call clobbered P register. | |
2257 | ||
2258 | @item q@var{n} | |
2259 | A single register. If @var{n} is in the range 0 to 7, the corresponding D | |
2260 | register. If it is @code{A}, then the register P0. | |
2261 | ||
2262 | @item D | |
2263 | Even-numbered D register | |
2264 | ||
2265 | @item W | |
2266 | Odd-numbered D register | |
2267 | ||
2268 | @item e | |
2269 | Accumulator register. | |
2270 | ||
2271 | @item A | |
2272 | Even-numbered accumulator register. | |
2273 | ||
2274 | @item B | |
2275 | Odd-numbered accumulator register. | |
2276 | ||
2277 | @item b | |
2278 | I register | |
2279 | ||
2280 | @item v | |
2281 | B register | |
2282 | ||
2283 | @item f | |
2284 | M register | |
2285 | ||
2286 | @item c | |
2287 | Registers used for circular buffering, i.e.@: I, B, or L registers. | |
2288 | ||
2289 | @item C | |
2290 | The CC register. | |
2291 | ||
2292 | @item t | |
2293 | LT0 or LT1. | |
2294 | ||
2295 | @item k | |
2296 | LC0 or LC1. | |
2297 | ||
2298 | @item u | |
2299 | LB0 or LB1. | |
2300 | ||
2301 | @item x | |
2302 | Any D, P, B, M, I or L register. | |
2303 | ||
2304 | @item y | |
2305 | Additional registers typically used only in prologues and epilogues: RETS, | |
2306 | RETN, RETI, RETX, RETE, ASTAT, SEQSTAT and USP. | |
2307 | ||
2308 | @item w | |
2309 | Any register except accumulators or CC. | |
2310 | ||
2311 | @item Ksh | |
2312 | Signed 16 bit integer (in the range @minus{}32768 to 32767) | |
2313 | ||
2314 | @item Kuh | |
2315 | Unsigned 16 bit integer (in the range 0 to 65535) | |
2316 | ||
2317 | @item Ks7 | |
2318 | Signed 7 bit integer (in the range @minus{}64 to 63) | |
2319 | ||
2320 | @item Ku7 | |
2321 | Unsigned 7 bit integer (in the range 0 to 127) | |
2322 | ||
2323 | @item Ku5 | |
2324 | Unsigned 5 bit integer (in the range 0 to 31) | |
2325 | ||
2326 | @item Ks4 | |
2327 | Signed 4 bit integer (in the range @minus{}8 to 7) | |
2328 | ||
2329 | @item Ks3 | |
2330 | Signed 3 bit integer (in the range @minus{}3 to 4) | |
2331 | ||
2332 | @item Ku3 | |
2333 | Unsigned 3 bit integer (in the range 0 to 7) | |
2334 | ||
2335 | @item P@var{n} | |
2336 | Constant @var{n}, where @var{n} is a single-digit constant in the range 0 to 4. | |
2337 | ||
2338 | @item PA | |
2339 | An integer equal to one of the MACFLAG_XXX constants that is suitable for | |
2340 | use with either accumulator. | |
2341 | ||
2342 | @item PB | |
2343 | An integer equal to one of the MACFLAG_XXX constants that is suitable for | |
2344 | use only with accumulator A1. | |
2345 | ||
2346 | @item M1 | |
2347 | Constant 255. | |
2348 | ||
2349 | @item M2 | |
2350 | Constant 65535. | |
2351 | ||
2352 | @item J | |
2353 | An integer constant with exactly a single bit set. | |
2354 | ||
2355 | @item L | |
2356 | An integer constant with all bits set except exactly one. | |
2357 | ||
2358 | @item H | |
f33d7a88 | 2359 | @itemx Q |
d77de738 ML |
2360 | Any SYMBOL_REF. |
2361 | @end table | |
2362 | ||
2363 | @item C-SKY---@file{config/csky/constraints.md} | |
2364 | @table @code | |
2365 | ||
2366 | @item a | |
2367 | The mini registers r0 - r7. | |
2368 | ||
2369 | @item b | |
2370 | The low registers r0 - r15. | |
2371 | ||
2372 | @item c | |
2373 | C register. | |
2374 | ||
2375 | @item y | |
2376 | HI and LO registers. | |
2377 | ||
2378 | @item l | |
2379 | LO register. | |
2380 | ||
2381 | @item h | |
2382 | HI register. | |
2383 | ||
2384 | @item v | |
2385 | Vector registers. | |
2386 | ||
2387 | @item z | |
2388 | Stack pointer register (SP). | |
2389 | ||
2390 | @item Q | |
2391 | A memory address which uses a base register with a short offset | |
2392 | or with a index register with its scale. | |
2393 | ||
2394 | @item W | |
2395 | A memory address which uses a base register with a index register | |
2396 | with its scale. | |
2397 | @end table | |
2398 | ||
2399 | @ifset INTERNALS | |
2400 | The C-SKY back end supports a large set of additional constraints | |
2401 | that are only useful for instruction selection or splitting rather | |
2402 | than inline asm, such as constraints representing constant integer | |
2403 | ranges accepted by particular instruction encodings. | |
2404 | Refer to the source code for details. | |
2405 | @end ifset | |
2406 | ||
2407 | @item Epiphany---@file{config/epiphany/constraints.md} | |
2408 | @table @code | |
2409 | @item U16 | |
2410 | An unsigned 16-bit constant. | |
2411 | ||
2412 | @item K | |
2413 | An unsigned 5-bit constant. | |
2414 | ||
2415 | @item L | |
2416 | A signed 11-bit constant. | |
2417 | ||
2418 | @item Cm1 | |
2419 | A signed 11-bit constant added to @minus{}1. | |
2420 | Can only match when the @option{-m1reg-@var{reg}} option is active. | |
2421 | ||
2422 | @item Cl1 | |
2423 | Left-shift of @minus{}1, i.e., a bit mask with a block of leading ones, the rest | |
2424 | being a block of trailing zeroes. | |
2425 | Can only match when the @option{-m1reg-@var{reg}} option is active. | |
2426 | ||
2427 | @item Cr1 | |
2428 | Right-shift of @minus{}1, i.e., a bit mask with a trailing block of ones, the | |
2429 | rest being zeroes. Or to put it another way, one less than a power of two. | |
2430 | Can only match when the @option{-m1reg-@var{reg}} option is active. | |
2431 | ||
2432 | @item Cal | |
2433 | Constant for arithmetic/logical operations. | |
2434 | This is like @code{i}, except that for position independent code, | |
2435 | no symbols / expressions needing relocations are allowed. | |
2436 | ||
2437 | @item Csy | |
2438 | Symbolic constant for call/jump instruction. | |
2439 | ||
2440 | @item Rcs | |
2441 | The register class usable in short insns. This is a register class | |
2442 | constraint, and can thus drive register allocation. | |
2443 | This constraint won't match unless @option{-mprefer-short-insn-regs} is | |
2444 | in effect. | |
2445 | ||
2446 | @item Rsc | |
2447 | The register class of registers that can be used to hold a | |
2448 | sibcall call address. I.e., a caller-saved register. | |
2449 | ||
2450 | @item Rct | |
2451 | Core control register class. | |
2452 | ||
2453 | @item Rgs | |
2454 | The register group usable in short insns. | |
2455 | This constraint does not use a register class, so that it only | |
2456 | passively matches suitable registers, and doesn't drive register allocation. | |
2457 | ||
2458 | @ifset INTERNALS | |
2459 | @item Car | |
2460 | Constant suitable for the addsi3_r pattern. This is a valid offset | |
2461 | For byte, halfword, or word addressing. | |
2462 | @end ifset | |
2463 | ||
2464 | @item Rra | |
2465 | Matches the return address if it can be replaced with the link register. | |
2466 | ||
2467 | @item Rcc | |
2468 | Matches the integer condition code register. | |
2469 | ||
2470 | @item Sra | |
2471 | Matches the return address if it is in a stack slot. | |
2472 | ||
2473 | @item Cfm | |
2474 | Matches control register values to switch fp mode, which are encapsulated in | |
2475 | @code{UNSPEC_FP_MODE}. | |
2476 | @end table | |
2477 | ||
2478 | @item FRV---@file{config/frv/frv.h} | |
2479 | @table @code | |
2480 | @item a | |
2481 | Register in the class @code{ACC_REGS} (@code{acc0} to @code{acc7}). | |
2482 | ||
2483 | @item b | |
2484 | Register in the class @code{EVEN_ACC_REGS} (@code{acc0} to @code{acc7}). | |
2485 | ||
2486 | @item c | |
2487 | Register in the class @code{CC_REGS} (@code{fcc0} to @code{fcc3} and | |
2488 | @code{icc0} to @code{icc3}). | |
2489 | ||
2490 | @item d | |
2491 | Register in the class @code{GPR_REGS} (@code{gr0} to @code{gr63}). | |
2492 | ||
2493 | @item e | |
2494 | Register in the class @code{EVEN_REGS} (@code{gr0} to @code{gr63}). | |
2495 | Odd registers are excluded not in the class but through the use of a machine | |
2496 | mode larger than 4 bytes. | |
2497 | ||
2498 | @item f | |
2499 | Register in the class @code{FPR_REGS} (@code{fr0} to @code{fr63}). | |
2500 | ||
2501 | @item h | |
2502 | Register in the class @code{FEVEN_REGS} (@code{fr0} to @code{fr63}). | |
2503 | Odd registers are excluded not in the class but through the use of a machine | |
2504 | mode larger than 4 bytes. | |
2505 | ||
2506 | @item l | |
2507 | Register in the class @code{LR_REG} (the @code{lr} register). | |
2508 | ||
2509 | @item q | |
2510 | Register in the class @code{QUAD_REGS} (@code{gr2} to @code{gr63}). | |
2511 | Register numbers not divisible by 4 are excluded not in the class but through | |
2512 | the use of a machine mode larger than 8 bytes. | |
2513 | ||
2514 | @item t | |
2515 | Register in the class @code{ICC_REGS} (@code{icc0} to @code{icc3}). | |
2516 | ||
2517 | @item u | |
2518 | Register in the class @code{FCC_REGS} (@code{fcc0} to @code{fcc3}). | |
2519 | ||
2520 | @item v | |
2521 | Register in the class @code{ICR_REGS} (@code{cc4} to @code{cc7}). | |
2522 | ||
2523 | @item w | |
2524 | Register in the class @code{FCR_REGS} (@code{cc0} to @code{cc3}). | |
2525 | ||
2526 | @item x | |
2527 | Register in the class @code{QUAD_FPR_REGS} (@code{fr0} to @code{fr63}). | |
2528 | Register numbers not divisible by 4 are excluded not in the class but through | |
2529 | the use of a machine mode larger than 8 bytes. | |
2530 | ||
2531 | @item z | |
2532 | Register in the class @code{SPR_REGS} (@code{lcr} and @code{lr}). | |
2533 | ||
2534 | @item A | |
2535 | Register in the class @code{QUAD_ACC_REGS} (@code{acc0} to @code{acc7}). | |
2536 | ||
2537 | @item B | |
2538 | Register in the class @code{ACCG_REGS} (@code{accg0} to @code{accg7}). | |
2539 | ||
2540 | @item C | |
2541 | Register in the class @code{CR_REGS} (@code{cc0} to @code{cc7}). | |
2542 | ||
2543 | @item G | |
2544 | Floating point constant zero | |
2545 | ||
2546 | @item I | |
2547 | 6-bit signed integer constant | |
2548 | ||
2549 | @item J | |
2550 | 10-bit signed integer constant | |
2551 | ||
2552 | @item L | |
2553 | 16-bit signed integer constant | |
2554 | ||
2555 | @item M | |
2556 | 16-bit unsigned integer constant | |
2557 | ||
2558 | @item N | |
2559 | 12-bit signed integer constant that is negative---i.e.@: in the | |
2560 | range of @minus{}2048 to @minus{}1 | |
2561 | ||
2562 | @item O | |
2563 | Constant zero | |
2564 | ||
2565 | @item P | |
2566 | 12-bit signed integer constant that is greater than zero---i.e.@: in the | |
2567 | range of 1 to 2047. | |
2568 | ||
2569 | @end table | |
2570 | ||
2571 | @item FT32---@file{config/ft32/constraints.md} | |
2572 | @table @code | |
2573 | @item A | |
2574 | An absolute address | |
2575 | ||
2576 | @item B | |
2577 | An offset address | |
2578 | ||
2579 | @item W | |
2580 | A register indirect memory operand | |
2581 | ||
2582 | @item e | |
2583 | An offset address. | |
2584 | ||
2585 | @item f | |
2586 | An offset address. | |
2587 | ||
2588 | @item O | |
2589 | The constant zero or one | |
2590 | ||
2591 | @item I | |
2592 | A 16-bit signed constant (@minus{}32768 @dots{} 32767) | |
2593 | ||
2594 | @item w | |
2595 | A bitfield mask suitable for bext or bins | |
2596 | ||
2597 | @item x | |
2598 | An inverted bitfield mask suitable for bext or bins | |
2599 | ||
2600 | @item L | |
2601 | A 16-bit unsigned constant, multiple of 4 (0 @dots{} 65532) | |
2602 | ||
2603 | @item S | |
2604 | A 20-bit signed constant (@minus{}524288 @dots{} 524287) | |
2605 | ||
2606 | @item b | |
2607 | A constant for a bitfield width (1 @dots{} 16) | |
2608 | ||
2609 | @item KA | |
2610 | A 10-bit signed constant (@minus{}512 @dots{} 511) | |
2611 | ||
2612 | @end table | |
2613 | ||
2614 | @item Hewlett-Packard PA-RISC---@file{config/pa/pa.h} | |
2615 | @table @code | |
2616 | @item a | |
2617 | General register 1 | |
2618 | ||
2619 | @item f | |
2620 | Floating point register | |
2621 | ||
2622 | @item q | |
2623 | Shift amount register | |
2624 | ||
2625 | @item x | |
2626 | Floating point register (deprecated) | |
2627 | ||
2628 | @item y | |
2629 | Upper floating point register (32-bit), floating point register (64-bit) | |
2630 | ||
2631 | @item Z | |
2632 | Any register | |
2633 | ||
2634 | @item I | |
2635 | Signed 11-bit integer constant | |
2636 | ||
2637 | @item J | |
2638 | Signed 14-bit integer constant | |
2639 | ||
2640 | @item K | |
2641 | Integer constant that can be deposited with a @code{zdepi} instruction | |
2642 | ||
2643 | @item L | |
2644 | Signed 5-bit integer constant | |
2645 | ||
2646 | @item M | |
2647 | Integer constant 0 | |
2648 | ||
2649 | @item N | |
2650 | Integer constant that can be loaded with a @code{ldil} instruction | |
2651 | ||
2652 | @item O | |
2653 | Integer constant whose value plus one is a power of 2 | |
2654 | ||
2655 | @item P | |
2656 | Integer constant that can be used for @code{and} operations in @code{depi} | |
2657 | and @code{extru} instructions | |
2658 | ||
2659 | @item S | |
2660 | Integer constant 31 | |
2661 | ||
2662 | @item U | |
2663 | Integer constant 63 | |
2664 | ||
2665 | @item G | |
2666 | Floating-point constant 0.0 | |
2667 | ||
2668 | @item A | |
2669 | A @code{lo_sum} data-linkage-table memory operand | |
2670 | ||
2671 | @item Q | |
2672 | A memory operand that can be used as the destination operand of an | |
2673 | integer store instruction | |
2674 | ||
2675 | @item R | |
2676 | A scaled or unscaled indexed memory operand | |
2677 | ||
2678 | @item T | |
2679 | A memory operand for floating-point loads and stores | |
2680 | ||
2681 | @item W | |
2682 | A register indirect memory operand | |
2683 | @end table | |
2684 | ||
2685 | @item Intel IA-64---@file{config/ia64/ia64.h} | |
2686 | @table @code | |
2687 | @item a | |
2688 | General register @code{r0} to @code{r3} for @code{addl} instruction | |
2689 | ||
2690 | @item b | |
2691 | Branch register | |
2692 | ||
2693 | @item c | |
2694 | Predicate register (@samp{c} as in ``conditional'') | |
2695 | ||
2696 | @item d | |
2697 | Application register residing in M-unit | |
2698 | ||
2699 | @item e | |
2700 | Application register residing in I-unit | |
2701 | ||
2702 | @item f | |
2703 | Floating-point register | |
2704 | ||
2705 | @item m | |
2706 | Memory operand. If used together with @samp{<} or @samp{>}, | |
2707 | the operand can have postincrement and postdecrement which | |
2708 | require printing with @samp{%Pn} on IA-64. | |
2709 | ||
2710 | @item G | |
2711 | Floating-point constant 0.0 or 1.0 | |
2712 | ||
2713 | @item I | |
2714 | 14-bit signed integer constant | |
2715 | ||
2716 | @item J | |
2717 | 22-bit signed integer constant | |
2718 | ||
2719 | @item K | |
2720 | 8-bit signed integer constant for logical instructions | |
2721 | ||
2722 | @item L | |
2723 | 8-bit adjusted signed integer constant for compare pseudo-ops | |
2724 | ||
2725 | @item M | |
2726 | 6-bit unsigned integer constant for shift counts | |
2727 | ||
2728 | @item N | |
2729 | 9-bit signed integer constant for load and store postincrements | |
2730 | ||
2731 | @item O | |
2732 | The constant zero | |
2733 | ||
2734 | @item P | |
2735 | 0 or @minus{}1 for @code{dep} instruction | |
2736 | ||
2737 | @item Q | |
2738 | Non-volatile memory for floating-point loads and stores | |
2739 | ||
2740 | @item R | |
2741 | Integer constant in the range 1 to 4 for @code{shladd} instruction | |
2742 | ||
2743 | @item S | |
2744 | Memory operand except postincrement and postdecrement. This is | |
2745 | now roughly the same as @samp{m} when not used together with @samp{<} | |
2746 | or @samp{>}. | |
2747 | @end table | |
2748 | ||
2749 | @item M32C---@file{config/m32c/m32c.cc} | |
2750 | @table @code | |
2751 | @item Rsp | |
2752 | @itemx Rfb | |
2753 | @itemx Rsb | |
2754 | @samp{$sp}, @samp{$fb}, @samp{$sb}. | |
2755 | ||
2756 | @item Rcr | |
2757 | Any control register, when they're 16 bits wide (nothing if control | |
2758 | registers are 24 bits wide) | |
2759 | ||
2760 | @item Rcl | |
2761 | Any control register, when they're 24 bits wide. | |
2762 | ||
2763 | @item R0w | |
2764 | @itemx R1w | |
2765 | @itemx R2w | |
2766 | @itemx R3w | |
2767 | $r0, $r1, $r2, $r3. | |
2768 | ||
2769 | @item R02 | |
2770 | $r0 or $r2, or $r2r0 for 32 bit values. | |
2771 | ||
2772 | @item R13 | |
2773 | $r1 or $r3, or $r3r1 for 32 bit values. | |
2774 | ||
2775 | @item Rdi | |
2776 | A register that can hold a 64 bit value. | |
2777 | ||
2778 | @item Rhl | |
2779 | $r0 or $r1 (registers with addressable high/low bytes) | |
2780 | ||
2781 | @item R23 | |
2782 | $r2 or $r3 | |
2783 | ||
2784 | @item Raa | |
2785 | Address registers | |
2786 | ||
2787 | @item Raw | |
2788 | Address registers when they're 16 bits wide. | |
2789 | ||
2790 | @item Ral | |
2791 | Address registers when they're 24 bits wide. | |
2792 | ||
2793 | @item Rqi | |
2794 | Registers that can hold QI values. | |
2795 | ||
2796 | @item Rad | |
2797 | Registers that can be used with displacements ($a0, $a1, $sb). | |
2798 | ||
2799 | @item Rsi | |
2800 | Registers that can hold 32 bit values. | |
2801 | ||
2802 | @item Rhi | |
2803 | Registers that can hold 16 bit values. | |
2804 | ||
2805 | @item Rhc | |
2806 | Registers chat can hold 16 bit values, including all control | |
2807 | registers. | |
2808 | ||
2809 | @item Rra | |
2810 | $r0 through R1, plus $a0 and $a1. | |
2811 | ||
2812 | @item Rfl | |
2813 | The flags register. | |
2814 | ||
2815 | @item Rmm | |
2816 | The memory-based pseudo-registers $mem0 through $mem15. | |
2817 | ||
2818 | @item Rpi | |
2819 | Registers that can hold pointers (16 bit registers for r8c, m16c; 24 | |
2820 | bit registers for m32cm, m32c). | |
2821 | ||
2822 | @item Rpa | |
2823 | Matches multiple registers in a PARALLEL to form a larger register. | |
2824 | Used to match function return values. | |
2825 | ||
2826 | @item Is3 | |
2827 | @minus{}8 @dots{} 7 | |
2828 | ||
2829 | @item IS1 | |
2830 | @minus{}128 @dots{} 127 | |
2831 | ||
2832 | @item IS2 | |
2833 | @minus{}32768 @dots{} 32767 | |
2834 | ||
2835 | @item IU2 | |
2836 | 0 @dots{} 65535 | |
2837 | ||
2838 | @item In4 | |
2839 | @minus{}8 @dots{} @minus{}1 or 1 @dots{} 8 | |
2840 | ||
2841 | @item In5 | |
2842 | @minus{}16 @dots{} @minus{}1 or 1 @dots{} 16 | |
2843 | ||
2844 | @item In6 | |
2845 | @minus{}32 @dots{} @minus{}1 or 1 @dots{} 32 | |
2846 | ||
2847 | @item IM2 | |
2848 | @minus{}65536 @dots{} @minus{}1 | |
2849 | ||
2850 | @item Ilb | |
2851 | An 8 bit value with exactly one bit set. | |
2852 | ||
2853 | @item Ilw | |
2854 | A 16 bit value with exactly one bit set. | |
2855 | ||
2856 | @item Sd | |
2857 | The common src/dest memory addressing modes. | |
2858 | ||
2859 | @item Sa | |
2860 | Memory addressed using $a0 or $a1. | |
2861 | ||
2862 | @item Si | |
2863 | Memory addressed with immediate addresses. | |
2864 | ||
2865 | @item Ss | |
2866 | Memory addressed using the stack pointer ($sp). | |
2867 | ||
2868 | @item Sf | |
2869 | Memory addressed using the frame base register ($fb). | |
2870 | ||
2871 | @item Ss | |
2872 | Memory addressed using the small base register ($sb). | |
2873 | ||
2874 | @item S1 | |
2875 | $r1h | |
2876 | @end table | |
2877 | ||
2878 | @item LoongArch---@file{config/loongarch/constraints.md} | |
2879 | @table @code | |
2880 | @item f | |
2881 | A floating-point register (if available). | |
2882 | @item k | |
2883 | A memory operand whose address is formed by a base register and | |
2884 | (optionally scaled) index register. | |
2885 | @item l | |
2886 | A signed 16-bit constant. | |
2887 | @item m | |
2888 | A memory operand whose address is formed by a base register and offset | |
2889 | that is suitable for use in instructions with the same addressing mode | |
2890 | as @code{st.w} and @code{ld.w}. | |
2891 | @item I | |
2892 | A signed 12-bit constant (for arithmetic instructions). | |
2893 | @item K | |
2894 | An unsigned 12-bit constant (for logic instructions). | |
c9b4c79e LC |
2895 | @item M |
2896 | A constant that cannot be loaded using @code{lui}, @code{addiu} | |
2897 | or @code{ori}. | |
2898 | @item N | |
2899 | A constant in the range -65535 to -1 (inclusive). | |
2900 | @item O | |
2901 | A signed 15-bit constant. | |
2902 | @item P | |
2903 | A constant in the range 1 to 65535 (inclusive). | |
2904 | @item R | |
2905 | An address that can be used in a non-macro load or store. | |
d77de738 ML |
2906 | @item ZB |
2907 | An address that is held in a general-purpose register. | |
2908 | The offset is zero. | |
2909 | @item ZC | |
2910 | A memory operand whose address is formed by a base register and offset | |
2911 | that is suitable for use in instructions with the same addressing mode | |
2912 | as @code{ll.w} and @code{sc.w}. | |
2913 | @end table | |
2914 | ||
2915 | @item MicroBlaze---@file{config/microblaze/constraints.md} | |
2916 | @table @code | |
2917 | @item d | |
2918 | A general register (@code{r0} to @code{r31}). | |
2919 | ||
2920 | @item z | |
2921 | A status register (@code{rmsr}, @code{$fcc1} to @code{$fcc7}). | |
2922 | ||
2923 | @end table | |
2924 | ||
2925 | @item MIPS---@file{config/mips/constraints.md} | |
2926 | @table @code | |
2927 | @item d | |
2928 | A general-purpose register. This is equivalent to @code{r} unless | |
2929 | generating MIPS16 code, in which case the MIPS16 register set is used. | |
2930 | ||
2931 | @item f | |
2932 | A floating-point register (if available). | |
2933 | ||
2934 | @item h | |
2935 | Formerly the @code{hi} register. This constraint is no longer supported. | |
2936 | ||
2937 | @item l | |
2938 | The @code{lo} register. Use this register to store values that are | |
2939 | no bigger than a word. | |
2940 | ||
2941 | @item x | |
2942 | The concatenated @code{hi} and @code{lo} registers. Use this register | |
2943 | to store doubleword values. | |
2944 | ||
2945 | @item c | |
2946 | A register suitable for use in an indirect jump. This will always be | |
2947 | @code{$25} for @option{-mabicalls}. | |
2948 | ||
2949 | @item v | |
2950 | Register @code{$3}. Do not use this constraint in new code; | |
2951 | it is retained only for compatibility with glibc. | |
2952 | ||
2953 | @item y | |
2954 | Equivalent to @code{r}; retained for backwards compatibility. | |
2955 | ||
2956 | @item z | |
2957 | A floating-point condition code register. | |
2958 | ||
2959 | @item I | |
2960 | A signed 16-bit constant (for arithmetic instructions). | |
2961 | ||
2962 | @item J | |
2963 | Integer zero. | |
2964 | ||
2965 | @item K | |
2966 | An unsigned 16-bit constant (for logic instructions). | |
2967 | ||
2968 | @item L | |
2969 | A signed 32-bit constant in which the lower 16 bits are zero. | |
2970 | Such constants can be loaded using @code{lui}. | |
2971 | ||
2972 | @item M | |
2973 | A constant that cannot be loaded using @code{lui}, @code{addiu} | |
2974 | or @code{ori}. | |
2975 | ||
2976 | @item N | |
2977 | A constant in the range @minus{}65535 to @minus{}1 (inclusive). | |
2978 | ||
2979 | @item O | |
2980 | A signed 15-bit constant. | |
2981 | ||
2982 | @item P | |
2983 | A constant in the range 1 to 65535 (inclusive). | |
2984 | ||
2985 | @item G | |
2986 | Floating-point zero. | |
2987 | ||
2988 | @item R | |
2989 | An address that can be used in a non-macro load or store. | |
2990 | ||
2991 | @item ZC | |
2992 | A memory operand whose address is formed by a base register and offset | |
2993 | that is suitable for use in instructions with the same addressing mode | |
2994 | as @code{ll} and @code{sc}. | |
2995 | ||
2996 | @item ZD | |
2997 | An address suitable for a @code{prefetch} instruction, or for any other | |
2998 | instruction with the same addressing mode as @code{prefetch}. | |
2999 | @end table | |
3000 | ||
3001 | @item Motorola 680x0---@file{config/m68k/constraints.md} | |
3002 | @table @code | |
3003 | @item a | |
3004 | Address register | |
3005 | ||
3006 | @item d | |
3007 | Data register | |
3008 | ||
3009 | @item f | |
3010 | 68881 floating-point register, if available | |
3011 | ||
3012 | @item I | |
3013 | Integer in the range 1 to 8 | |
3014 | ||
3015 | @item J | |
3016 | 16-bit signed number | |
3017 | ||
3018 | @item K | |
3019 | Signed number whose magnitude is greater than 0x80 | |
3020 | ||
3021 | @item L | |
3022 | Integer in the range @minus{}8 to @minus{}1 | |
3023 | ||
3024 | @item M | |
3025 | Signed number whose magnitude is greater than 0x100 | |
3026 | ||
3027 | @item N | |
3028 | Range 24 to 31, rotatert:SI 8 to 1 expressed as rotate | |
3029 | ||
3030 | @item O | |
3031 | 16 (for rotate using swap) | |
3032 | ||
3033 | @item P | |
3034 | Range 8 to 15, rotatert:HI 8 to 1 expressed as rotate | |
3035 | ||
3036 | @item R | |
3037 | Numbers that mov3q can handle | |
3038 | ||
3039 | @item G | |
3040 | Floating point constant that is not a 68881 constant | |
3041 | ||
3042 | @item S | |
3043 | Operands that satisfy 'm' when -mpcrel is in effect | |
3044 | ||
3045 | @item T | |
3046 | Operands that satisfy 's' when -mpcrel is not in effect | |
3047 | ||
3048 | @item Q | |
3049 | Address register indirect addressing mode | |
3050 | ||
3051 | @item U | |
3052 | Register offset addressing | |
3053 | ||
3054 | @item W | |
3055 | const_call_operand | |
3056 | ||
3057 | @item Cs | |
3058 | symbol_ref or const | |
3059 | ||
3060 | @item Ci | |
3061 | const_int | |
3062 | ||
3063 | @item C0 | |
3064 | const_int 0 | |
3065 | ||
3066 | @item Cj | |
3067 | Range of signed numbers that don't fit in 16 bits | |
3068 | ||
3069 | @item Cmvq | |
3070 | Integers valid for mvq | |
3071 | ||
3072 | @item Capsw | |
3073 | Integers valid for a moveq followed by a swap | |
3074 | ||
3075 | @item Cmvz | |
3076 | Integers valid for mvz | |
3077 | ||
3078 | @item Cmvs | |
3079 | Integers valid for mvs | |
3080 | ||
3081 | @item Ap | |
3082 | push_operand | |
3083 | ||
3084 | @item Ac | |
3085 | Non-register operands allowed in clr | |
3086 | ||
3087 | @end table | |
3088 | ||
3089 | @item Moxie---@file{config/moxie/constraints.md} | |
3090 | @table @code | |
3091 | @item A | |
3092 | An absolute address | |
3093 | ||
3094 | @item B | |
3095 | An offset address | |
3096 | ||
3097 | @item W | |
3098 | A register indirect memory operand | |
3099 | ||
3100 | @item I | |
3101 | A constant in the range of 0 to 255. | |
3102 | ||
3103 | @item N | |
3104 | A constant in the range of 0 to @minus{}255. | |
3105 | ||
3106 | @end table | |
3107 | ||
3108 | @item MSP430--@file{config/msp430/constraints.md} | |
3109 | @table @code | |
3110 | ||
3111 | @item R12 | |
3112 | Register R12. | |
3113 | ||
3114 | @item R13 | |
3115 | Register R13. | |
3116 | ||
3117 | @item K | |
3118 | Integer constant 1. | |
3119 | ||
3120 | @item L | |
3121 | Integer constant -1^20..1^19. | |
3122 | ||
3123 | @item M | |
3124 | Integer constant 1-4. | |
3125 | ||
3126 | @item Ya | |
3127 | Memory references which do not require an extended MOVX instruction. | |
3128 | ||
3129 | @item Yl | |
3130 | Memory reference, labels only. | |
3131 | ||
3132 | @item Ys | |
3133 | Memory reference, stack only. | |
3134 | ||
3135 | @end table | |
3136 | ||
3137 | @item NDS32---@file{config/nds32/constraints.md} | |
3138 | @table @code | |
3139 | @item w | |
3140 | LOW register class $r0 to $r7 constraint for V3/V3M ISA. | |
3141 | @item l | |
3142 | LOW register class $r0 to $r7. | |
3143 | @item d | |
3144 | MIDDLE register class $r0 to $r11, $r16 to $r19. | |
3145 | @item h | |
3146 | HIGH register class $r12 to $r14, $r20 to $r31. | |
3147 | @item t | |
3148 | Temporary assist register $ta (i.e.@: $r15). | |
3149 | @item k | |
3150 | Stack register $sp. | |
3151 | @item Iu03 | |
3152 | Unsigned immediate 3-bit value. | |
3153 | @item In03 | |
3154 | Negative immediate 3-bit value in the range of @minus{}7--0. | |
3155 | @item Iu04 | |
3156 | Unsigned immediate 4-bit value. | |
3157 | @item Is05 | |
3158 | Signed immediate 5-bit value. | |
3159 | @item Iu05 | |
3160 | Unsigned immediate 5-bit value. | |
3161 | @item In05 | |
3162 | Negative immediate 5-bit value in the range of @minus{}31--0. | |
3163 | @item Ip05 | |
3164 | Unsigned immediate 5-bit value for movpi45 instruction with range 16--47. | |
3165 | @item Iu06 | |
3166 | Unsigned immediate 6-bit value constraint for addri36.sp instruction. | |
3167 | @item Iu08 | |
3168 | Unsigned immediate 8-bit value. | |
3169 | @item Iu09 | |
3170 | Unsigned immediate 9-bit value. | |
3171 | @item Is10 | |
3172 | Signed immediate 10-bit value. | |
3173 | @item Is11 | |
3174 | Signed immediate 11-bit value. | |
3175 | @item Is15 | |
3176 | Signed immediate 15-bit value. | |
3177 | @item Iu15 | |
3178 | Unsigned immediate 15-bit value. | |
3179 | @item Ic15 | |
3180 | A constant which is not in the range of imm15u but ok for bclr instruction. | |
3181 | @item Ie15 | |
3182 | A constant which is not in the range of imm15u but ok for bset instruction. | |
3183 | @item It15 | |
3184 | A constant which is not in the range of imm15u but ok for btgl instruction. | |
3185 | @item Ii15 | |
3186 | A constant whose compliment value is in the range of imm15u | |
3187 | and ok for bitci instruction. | |
3188 | @item Is16 | |
3189 | Signed immediate 16-bit value. | |
3190 | @item Is17 | |
3191 | Signed immediate 17-bit value. | |
3192 | @item Is19 | |
3193 | Signed immediate 19-bit value. | |
3194 | @item Is20 | |
3195 | Signed immediate 20-bit value. | |
3196 | @item Ihig | |
3197 | The immediate value that can be simply set high 20-bit. | |
3198 | @item Izeb | |
3199 | The immediate value 0xff. | |
3200 | @item Izeh | |
3201 | The immediate value 0xffff. | |
3202 | @item Ixls | |
3203 | The immediate value 0x01. | |
3204 | @item Ix11 | |
3205 | The immediate value 0x7ff. | |
3206 | @item Ibms | |
3207 | The immediate value with power of 2. | |
3208 | @item Ifex | |
3209 | The immediate value with power of 2 minus 1. | |
3210 | @item U33 | |
3211 | Memory constraint for 333 format. | |
3212 | @item U45 | |
3213 | Memory constraint for 45 format. | |
3214 | @item U37 | |
3215 | Memory constraint for 37 format. | |
3216 | @end table | |
3217 | ||
3218 | @item Nios II family---@file{config/nios2/constraints.md} | |
3219 | @table @code | |
3220 | ||
3221 | @item I | |
3222 | Integer that is valid as an immediate operand in an | |
3223 | instruction taking a signed 16-bit number. Range | |
3224 | @minus{}32768 to 32767. | |
3225 | ||
3226 | @item J | |
3227 | Integer that is valid as an immediate operand in an | |
3228 | instruction taking an unsigned 16-bit number. Range | |
3229 | 0 to 65535. | |
3230 | ||
3231 | @item K | |
3232 | Integer that is valid as an immediate operand in an | |
3233 | instruction taking only the upper 16-bits of a | |
3234 | 32-bit number. Range 32-bit numbers with the lower | |
3235 | 16-bits being 0. | |
3236 | ||
3237 | @item L | |
3238 | Integer that is valid as an immediate operand for a | |
3239 | shift instruction. Range 0 to 31. | |
3240 | ||
3241 | @item M | |
3242 | Integer that is valid as an immediate operand for | |
3243 | only the value 0. Can be used in conjunction with | |
3244 | the format modifier @code{z} to use @code{r0} | |
3245 | instead of @code{0} in the assembly output. | |
3246 | ||
3247 | @item N | |
3248 | Integer that is valid as an immediate operand for | |
3249 | a custom instruction opcode. Range 0 to 255. | |
3250 | ||
3251 | @item P | |
3252 | An immediate operand for R2 andchi/andci instructions. | |
3253 | ||
3254 | @item S | |
3255 | Matches immediates which are addresses in the small | |
3256 | data section and therefore can be added to @code{gp} | |
3257 | as a 16-bit immediate to re-create their 32-bit value. | |
3258 | ||
3259 | @item U | |
3260 | Matches constants suitable as an operand for the rdprs and | |
3261 | cache instructions. | |
3262 | ||
3263 | @item v | |
3264 | A memory operand suitable for Nios II R2 load/store | |
3265 | exclusive instructions. | |
3266 | ||
3267 | @item w | |
3268 | A memory operand suitable for load/store IO and cache | |
3269 | instructions. | |
3270 | ||
3271 | @ifset INTERNALS | |
3272 | @item T | |
3273 | A @code{const} wrapped @code{UNSPEC} expression, | |
3274 | representing a supported PIC or TLS relocation. | |
3275 | @end ifset | |
3276 | ||
3277 | @end table | |
3278 | ||
3279 | @item OpenRISC---@file{config/or1k/constraints.md} | |
3280 | @table @code | |
3281 | @item I | |
3282 | Integer that is valid as an immediate operand in an | |
3283 | instruction taking a signed 16-bit number. Range | |
3284 | @minus{}32768 to 32767. | |
3285 | ||
3286 | @item K | |
3287 | Integer that is valid as an immediate operand in an | |
3288 | instruction taking an unsigned 16-bit number. Range | |
3289 | 0 to 65535. | |
3290 | ||
3291 | @item M | |
3292 | Signed 16-bit constant shifted left 16 bits. (Used with @code{l.movhi}) | |
3293 | ||
3294 | @item O | |
3295 | Zero | |
3296 | ||
3297 | @ifset INTERNALS | |
3298 | @item c | |
3299 | Register usable for sibcalls. | |
3300 | @end ifset | |
3301 | ||
3302 | @end table | |
3303 | ||
3304 | @item PDP-11---@file{config/pdp11/constraints.md} | |
3305 | @table @code | |
3306 | @item a | |
3307 | Floating point registers AC0 through AC3. These can be loaded from/to | |
3308 | memory with a single instruction. | |
3309 | ||
3310 | @item d | |
3311 | Odd numbered general registers (R1, R3, R5). These are used for | |
3312 | 16-bit multiply operations. | |
3313 | ||
3314 | @item D | |
3315 | A memory reference that is encoded within the opcode, but not | |
3316 | auto-increment or auto-decrement. | |
3317 | ||
3318 | @item f | |
3319 | Any of the floating point registers (AC0 through AC5). | |
3320 | ||
3321 | @item G | |
3322 | Floating point constant 0. | |
3323 | ||
3324 | @item h | |
3325 | Floating point registers AC4 and AC5. These cannot be loaded from/to | |
3326 | memory with a single instruction. | |
3327 | ||
3328 | @item I | |
3329 | An integer constant that fits in 16 bits. | |
3330 | ||
3331 | @item J | |
3332 | An integer constant whose low order 16 bits are zero. | |
3333 | ||
3334 | @item K | |
3335 | An integer constant that does not meet the constraints for codes | |
3336 | @samp{I} or @samp{J}. | |
3337 | ||
3338 | @item L | |
3339 | The integer constant 1. | |
3340 | ||
3341 | @item M | |
3342 | The integer constant @minus{}1. | |
3343 | ||
3344 | @item N | |
3345 | The integer constant 0. | |
3346 | ||
3347 | @item O | |
3348 | Integer constants 0 through 3; shifts by these | |
3349 | amounts are handled as multiple single-bit shifts rather than a single | |
3350 | variable-length shift. | |
3351 | ||
3352 | @item Q | |
3353 | A memory reference which requires an additional word (address or | |
3354 | offset) after the opcode. | |
3355 | ||
3356 | @item R | |
3357 | A memory reference that is encoded within the opcode. | |
3358 | ||
3359 | @end table | |
3360 | ||
3361 | @item PowerPC and IBM RS6000---@file{config/rs6000/constraints.md} | |
3362 | @table @code | |
3363 | @item r | |
3364 | A general purpose register (GPR), @code{r0}@dots{}@code{r31}. | |
3365 | ||
3366 | @item b | |
3367 | A base register. Like @code{r}, but @code{r0} is not allowed, so | |
3368 | @code{r1}@dots{}@code{r31}. | |
3369 | ||
3370 | @item f | |
3371 | A floating point register (FPR), @code{f0}@dots{}@code{f31}. | |
3372 | ||
3373 | @item d | |
3374 | A floating point register. This is the same as @code{f} nowadays; | |
3375 | historically @code{f} was for single-precision and @code{d} was for | |
3376 | double-precision floating point. | |
3377 | ||
3378 | @item v | |
3379 | An Altivec vector register (VR), @code{v0}@dots{}@code{v31}. | |
3380 | ||
3381 | @item wa | |
3382 | A VSX register (VSR), @code{vs0}@dots{}@code{vs63}. This is either an | |
3383 | FPR (@code{vs0}@dots{}@code{vs31} are @code{f0}@dots{}@code{f31}) or a VR | |
3384 | (@code{vs32}@dots{}@code{vs63} are @code{v0}@dots{}@code{v31}). | |
3385 | ||
3386 | When using @code{wa}, you should use the @code{%x} output modifier, so that | |
3387 | the correct register number is printed. For example: | |
3388 | ||
3389 | @smallexample | |
3390 | asm ("xvadddp %x0,%x1,%x2" | |
3391 | : "=wa" (v1) | |
3392 | : "wa" (v2), "wa" (v3)); | |
3393 | @end smallexample | |
3394 | ||
3395 | You should not use @code{%x} for @code{v} operands: | |
3396 | ||
3397 | @smallexample | |
3398 | asm ("xsaddqp %0,%1,%2" | |
3399 | : "=v" (v1) | |
3400 | : "v" (v2), "v" (v3)); | |
3401 | @end smallexample | |
3402 | ||
3403 | @ifset INTERNALS | |
3404 | @item h | |
3405 | A special register (@code{vrsave}, @code{ctr}, or @code{lr}). | |
3406 | @end ifset | |
3407 | ||
3408 | @item c | |
3409 | The count register, @code{ctr}. | |
3410 | ||
3411 | @item l | |
3412 | The link register, @code{lr}. | |
3413 | ||
3414 | @item x | |
3415 | Condition register field 0, @code{cr0}. | |
3416 | ||
3417 | @item y | |
3418 | Any condition register field, @code{cr0}@dots{}@code{cr7}. | |
3419 | ||
3420 | @ifset INTERNALS | |
3421 | @item z | |
3422 | The carry bit, @code{XER[CA]}. | |
3423 | ||
3424 | @item we | |
3425 | Like @code{wa}, if @option{-mpower9-vector} and @option{-m64} are used; | |
3426 | otherwise, @code{NO_REGS}. | |
3427 | ||
3428 | @item wn | |
3429 | No register (@code{NO_REGS}). | |
3430 | ||
3431 | @item wr | |
3432 | Like @code{r}, if @option{-mpowerpc64} is used; otherwise, @code{NO_REGS}. | |
3433 | ||
3434 | @item wx | |
3435 | Like @code{d}, if @option{-mpowerpc-gfxopt} is used; otherwise, @code{NO_REGS}. | |
3436 | ||
3437 | @item wA | |
3438 | Like @code{b}, if @option{-mpowerpc64} is used; otherwise, @code{NO_REGS}. | |
3439 | ||
3440 | @item wB | |
3441 | Signed 5-bit constant integer that can be loaded into an Altivec register. | |
3442 | ||
3443 | @item wE | |
3444 | Vector constant that can be loaded with the XXSPLTIB instruction. | |
3445 | ||
3446 | @item wF | |
3447 | Memory operand suitable for power8 GPR load fusion. | |
3448 | ||
3449 | @item wL | |
3450 | Int constant that is the element number mfvsrld accesses in a vector. | |
3451 | ||
3452 | @item wM | |
3453 | Match vector constant with all 1's if the XXLORC instruction is available. | |
3454 | ||
3455 | @item wO | |
3456 | Memory operand suitable for the ISA 3.0 vector d-form instructions. | |
3457 | ||
3458 | @item wQ | |
3459 | Memory operand suitable for the load/store quad instructions. | |
3460 | ||
3461 | @item wS | |
3462 | Vector constant that can be loaded with XXSPLTIB & sign extension. | |
3463 | ||
3464 | @item wY | |
3465 | A memory operand for a DS-form instruction. | |
3466 | ||
3467 | @item wZ | |
3468 | An indexed or indirect memory operand, ignoring the bottom 4 bits. | |
3469 | @end ifset | |
3470 | ||
3471 | @item I | |
3472 | A signed 16-bit constant. | |
3473 | ||
3474 | @item J | |
3475 | An unsigned 16-bit constant shifted left 16 bits (use @code{L} instead | |
3476 | for @code{SImode} constants). | |
3477 | ||
3478 | @item K | |
3479 | An unsigned 16-bit constant. | |
3480 | ||
3481 | @item L | |
3482 | A signed 16-bit constant shifted left 16 bits. | |
3483 | ||
3484 | @ifset INTERNALS | |
3485 | @item M | |
3486 | An integer constant greater than 31. | |
3487 | ||
3488 | @item N | |
3489 | An exact power of 2. | |
3490 | ||
3491 | @item O | |
3492 | The integer constant zero. | |
3493 | ||
3494 | @item P | |
3495 | A constant whose negation is a signed 16-bit constant. | |
3496 | @end ifset | |
3497 | ||
3498 | @item eI | |
3499 | A signed 34-bit integer constant if prefixed instructions are supported. | |
3500 | ||
3501 | @item eP | |
3502 | A scalar floating point constant or a vector constant that can be | |
3503 | loaded to a VSX register with one prefixed instruction. | |
3504 | ||
3505 | @item eQ | |
3506 | An IEEE 128-bit constant that can be loaded into a VSX register with | |
3507 | the @code{lxvkq} instruction. | |
3508 | ||
3509 | @ifset INTERNALS | |
3510 | @item G | |
3511 | A floating point constant that can be loaded into a register with one | |
3512 | instruction per word. | |
3513 | ||
3514 | @item H | |
3515 | A floating point constant that can be loaded into a register using | |
3516 | three instructions. | |
3517 | @end ifset | |
3518 | ||
3519 | @item m | |
3520 | A memory operand. | |
3521 | Normally, @code{m} does not allow addresses that update the base register. | |
3522 | If the @code{<} or @code{>} constraint is also used, they are allowed and | |
3523 | therefore on PowerPC targets in that case it is only safe | |
3524 | to use @code{m<>} in an @code{asm} statement if that @code{asm} statement | |
3525 | accesses the operand exactly once. The @code{asm} statement must also | |
3526 | use @code{%U@var{<opno>}} as a placeholder for the ``update'' flag in the | |
3527 | corresponding load or store instruction. For example: | |
3528 | ||
3529 | @smallexample | |
3530 | asm ("st%U0 %1,%0" : "=m<>" (mem) : "r" (val)); | |
3531 | @end smallexample | |
3532 | ||
3533 | is correct but: | |
3534 | ||
3535 | @smallexample | |
3536 | asm ("st %1,%0" : "=m<>" (mem) : "r" (val)); | |
3537 | @end smallexample | |
3538 | ||
3539 | is not. | |
3540 | ||
3541 | @ifset INTERNALS | |
3542 | @item es | |
3543 | A ``stable'' memory operand; that is, one which does not include any | |
3544 | automodification of the base register. This used to be useful when | |
3545 | @code{m} allowed automodification of the base register, but as those | |
3546 | are now only allowed when @code{<} or @code{>} is used, @code{es} is | |
3547 | basically the same as @code{m} without @code{<} and @code{>}. | |
3548 | @end ifset | |
3549 | ||
3550 | @item Q | |
3551 | A memory operand addressed by just a base register. | |
3552 | ||
3553 | @ifset INTERNALS | |
3554 | @item Y | |
3555 | A memory operand for a DQ-form instruction. | |
3556 | @end ifset | |
3557 | ||
3558 | @item Z | |
3559 | A memory operand accessed with indexed or indirect addressing. | |
3560 | ||
3561 | @ifset INTERNALS | |
3562 | @item R | |
3563 | An AIX TOC entry. | |
3564 | @end ifset | |
3565 | ||
3566 | @item a | |
3567 | An indexed or indirect address. | |
3568 | ||
3569 | @ifset INTERNALS | |
3570 | @item U | |
3571 | A V.4 small data reference. | |
3572 | ||
3573 | @item W | |
3574 | A vector constant that does not require memory. | |
3575 | ||
3576 | @item j | |
3577 | The zero vector constant. | |
3578 | @end ifset | |
3579 | ||
3580 | @end table | |
3581 | ||
3582 | @item PRU---@file{config/pru/constraints.md} | |
3583 | @table @code | |
3584 | @item I | |
3585 | An unsigned 8-bit integer constant. | |
3586 | ||
3587 | @item J | |
3588 | An unsigned 16-bit integer constant. | |
3589 | ||
3590 | @item L | |
3591 | An unsigned 5-bit integer constant (for shift counts). | |
3592 | ||
3593 | @item T | |
3594 | A text segment (program memory) constant label. | |
3595 | ||
3596 | @item Z | |
3597 | Integer constant zero. | |
3598 | ||
3599 | @end table | |
3600 | ||
3601 | @item RL78---@file{config/rl78/constraints.md} | |
3602 | @table @code | |
3603 | ||
3604 | @item Int3 | |
3605 | An integer constant in the range 1 @dots{} 7. | |
3606 | @item Int8 | |
3607 | An integer constant in the range 0 @dots{} 255. | |
3608 | @item J | |
3609 | An integer constant in the range @minus{}255 @dots{} 0 | |
3610 | @item K | |
3611 | The integer constant 1. | |
3612 | @item L | |
3613 | The integer constant -1. | |
3614 | @item M | |
3615 | The integer constant 0. | |
3616 | @item N | |
3617 | The integer constant 2. | |
3618 | @item O | |
3619 | The integer constant -2. | |
3620 | @item P | |
3621 | An integer constant in the range 1 @dots{} 15. | |
3622 | @item Qbi | |
3623 | The built-in compare types--eq, ne, gtu, ltu, geu, and leu. | |
3624 | @item Qsc | |
3625 | The synthetic compare types--gt, lt, ge, and le. | |
3626 | @item Wab | |
3627 | A memory reference with an absolute address. | |
3628 | @item Wbc | |
3629 | A memory reference using @code{BC} as a base register, with an optional offset. | |
3630 | @item Wca | |
3631 | A memory reference using @code{AX}, @code{BC}, @code{DE}, or @code{HL} for the address, for calls. | |
3632 | @item Wcv | |
3633 | A memory reference using any 16-bit register pair for the address, for calls. | |
3634 | @item Wd2 | |
3635 | A memory reference using @code{DE} as a base register, with an optional offset. | |
3636 | @item Wde | |
3637 | A memory reference using @code{DE} as a base register, without any offset. | |
3638 | @item Wfr | |
3639 | Any memory reference to an address in the far address space. | |
3640 | @item Wh1 | |
3641 | A memory reference using @code{HL} as a base register, with an optional one-byte offset. | |
3642 | @item Whb | |
3643 | A memory reference using @code{HL} as a base register, with @code{B} or @code{C} as the index register. | |
3644 | @item Whl | |
3645 | A memory reference using @code{HL} as a base register, without any offset. | |
3646 | @item Ws1 | |
3647 | A memory reference using @code{SP} as a base register, with an optional one-byte offset. | |
3648 | @item Y | |
3649 | Any memory reference to an address in the near address space. | |
3650 | @item A | |
3651 | The @code{AX} register. | |
3652 | @item B | |
3653 | The @code{BC} register. | |
3654 | @item D | |
3655 | The @code{DE} register. | |
3656 | @item R | |
3657 | @code{A} through @code{L} registers. | |
3658 | @item S | |
3659 | The @code{SP} register. | |
3660 | @item T | |
3661 | The @code{HL} register. | |
3662 | @item Z08W | |
3663 | The 16-bit @code{R8} register. | |
3664 | @item Z10W | |
3665 | The 16-bit @code{R10} register. | |
3666 | @item Zint | |
3667 | The registers reserved for interrupts (@code{R24} to @code{R31}). | |
3668 | @item a | |
3669 | The @code{A} register. | |
3670 | @item b | |
3671 | The @code{B} register. | |
3672 | @item c | |
3673 | The @code{C} register. | |
3674 | @item d | |
3675 | The @code{D} register. | |
3676 | @item e | |
3677 | The @code{E} register. | |
3678 | @item h | |
3679 | The @code{H} register. | |
3680 | @item l | |
3681 | The @code{L} register. | |
3682 | @item v | |
3683 | The virtual registers. | |
3684 | @item w | |
3685 | The @code{PSW} register. | |
3686 | @item x | |
3687 | The @code{X} register. | |
3688 | ||
3689 | @end table | |
3690 | ||
3691 | @item RISC-V---@file{config/riscv/constraints.md} | |
3692 | @table @code | |
3693 | ||
3694 | @item f | |
3695 | A floating-point register (if available). | |
3696 | ||
3697 | @item I | |
3698 | An I-type 12-bit signed immediate. | |
3699 | ||
3700 | @item J | |
3701 | Integer zero. | |
3702 | ||
3703 | @item K | |
3704 | A 5-bit unsigned immediate for CSR access instructions. | |
3705 | ||
3706 | @item A | |
3707 | An address that is held in a general-purpose register. | |
3708 | ||
3709 | @item S | |
3710 | A constraint that matches an absolute symbolic address. | |
3711 | ||
e8511cbb KC |
3712 | @item vr |
3713 | A vector register (if available).. | |
3714 | ||
3715 | @item vd | |
3716 | A vector register, excluding v0 (if available). | |
3717 | ||
3718 | @item vm | |
3719 | A vector register, only v0 (if available). | |
3720 | ||
d77de738 ML |
3721 | @end table |
3722 | ||
3723 | @item RX---@file{config/rx/constraints.md} | |
3724 | @table @code | |
3725 | @item Q | |
3726 | An address which does not involve register indirect addressing or | |
3727 | pre/post increment/decrement addressing. | |
3728 | ||
3729 | @item Symbol | |
3730 | A symbol reference. | |
3731 | ||
3732 | @item Int08 | |
3733 | A constant in the range @minus{}256 to 255, inclusive. | |
3734 | ||
3735 | @item Sint08 | |
3736 | A constant in the range @minus{}128 to 127, inclusive. | |
3737 | ||
3738 | @item Sint16 | |
3739 | A constant in the range @minus{}32768 to 32767, inclusive. | |
3740 | ||
3741 | @item Sint24 | |
3742 | A constant in the range @minus{}8388608 to 8388607, inclusive. | |
3743 | ||
3744 | @item Uint04 | |
3745 | A constant in the range 0 to 15, inclusive. | |
3746 | ||
3747 | @end table | |
3748 | ||
3749 | @item S/390 and zSeries---@file{config/s390/s390.h} | |
3750 | @table @code | |
3751 | @item a | |
3752 | Address register (general purpose register except r0) | |
3753 | ||
3754 | @item c | |
3755 | Condition code register | |
3756 | ||
3757 | @item d | |
3758 | Data register (arbitrary general purpose register) | |
3759 | ||
3760 | @item f | |
3761 | Floating-point register | |
3762 | ||
3763 | @item I | |
3764 | Unsigned 8-bit constant (0--255) | |
3765 | ||
3766 | @item J | |
3767 | Unsigned 12-bit constant (0--4095) | |
3768 | ||
3769 | @item K | |
3770 | Signed 16-bit constant (@minus{}32768--32767) | |
3771 | ||
3772 | @item L | |
3773 | Value appropriate as displacement. | |
3774 | @table @code | |
3775 | @item (0..4095) | |
3776 | for short displacement | |
3777 | @item (@minus{}524288..524287) | |
3778 | for long displacement | |
3779 | @end table | |
3780 | ||
3781 | @item M | |
3782 | Constant integer with a value of 0x7fffffff. | |
3783 | ||
3784 | @item N | |
3785 | Multiple letter constraint followed by 4 parameter letters. | |
3786 | @table @code | |
3787 | @item 0..9: | |
3788 | number of the part counting from most to least significant | |
3789 | @item H,Q: | |
3790 | mode of the part | |
3791 | @item D,S,H: | |
3792 | mode of the containing operand | |
3793 | @item 0,F: | |
3794 | value of the other parts (F---all bits set) | |
3795 | @end table | |
3796 | The constraint matches if the specified part of a constant | |
3797 | has a value different from its other parts. | |
3798 | ||
3799 | @item Q | |
3800 | Memory reference without index register and with short displacement. | |
3801 | ||
3802 | @item R | |
3803 | Memory reference with index register and short displacement. | |
3804 | ||
3805 | @item S | |
3806 | Memory reference without index register but with long displacement. | |
3807 | ||
3808 | @item T | |
3809 | Memory reference with index register and long displacement. | |
3810 | ||
3811 | @item U | |
3812 | Pointer with short displacement. | |
3813 | ||
3814 | @item W | |
3815 | Pointer with long displacement. | |
3816 | ||
3817 | @item Y | |
3818 | Shift count operand. | |
3819 | ||
3820 | @end table | |
3821 | ||
3822 | @need 1000 | |
3823 | @item SPARC---@file{config/sparc/sparc.h} | |
3824 | @table @code | |
3825 | @item f | |
3826 | Floating-point register on the SPARC-V8 architecture and | |
3827 | lower floating-point register on the SPARC-V9 architecture. | |
3828 | ||
3829 | @item e | |
3830 | Floating-point register. It is equivalent to @samp{f} on the | |
3831 | SPARC-V8 architecture and contains both lower and upper | |
3832 | floating-point registers on the SPARC-V9 architecture. | |
3833 | ||
3834 | @item c | |
3835 | Floating-point condition code register. | |
3836 | ||
3837 | @item d | |
3838 | Lower floating-point register. It is only valid on the SPARC-V9 | |
3839 | architecture when the Visual Instruction Set is available. | |
3840 | ||
3841 | @item b | |
3842 | Floating-point register. It is only valid on the SPARC-V9 architecture | |
3843 | when the Visual Instruction Set is available. | |
3844 | ||
3845 | @item h | |
3846 | 64-bit global or out register for the SPARC-V8+ architecture. | |
3847 | ||
3848 | @item C | |
3849 | The constant all-ones, for floating-point. | |
3850 | ||
3851 | @item A | |
3852 | Signed 5-bit constant | |
3853 | ||
3854 | @item D | |
3855 | A vector constant | |
3856 | ||
3857 | @item I | |
3858 | Signed 13-bit constant | |
3859 | ||
3860 | @item J | |
3861 | Zero | |
3862 | ||
3863 | @item K | |
3864 | 32-bit constant with the low 12 bits clear (a constant that can be | |
3865 | loaded with the @code{sethi} instruction) | |
3866 | ||
3867 | @item L | |
3868 | A constant in the range supported by @code{movcc} instructions (11-bit | |
3869 | signed immediate) | |
3870 | ||
3871 | @item M | |
3872 | A constant in the range supported by @code{movrcc} instructions (10-bit | |
3873 | signed immediate) | |
3874 | ||
3875 | @item N | |
3876 | Same as @samp{K}, except that it verifies that bits that are not in the | |
3877 | lower 32-bit range are all zero. Must be used instead of @samp{K} for | |
3878 | modes wider than @code{SImode} | |
3879 | ||
3880 | @item O | |
3881 | The constant 4096 | |
3882 | ||
3883 | @item G | |
3884 | Floating-point zero | |
3885 | ||
3886 | @item H | |
3887 | Signed 13-bit constant, sign-extended to 32 or 64 bits | |
3888 | ||
3889 | @item P | |
3890 | The constant -1 | |
3891 | ||
3892 | @item Q | |
3893 | Floating-point constant whose integral representation can | |
3894 | be moved into an integer register using a single sethi | |
3895 | instruction | |
3896 | ||
3897 | @item R | |
3898 | Floating-point constant whose integral representation can | |
3899 | be moved into an integer register using a single mov | |
3900 | instruction | |
3901 | ||
3902 | @item S | |
3903 | Floating-point constant whose integral representation can | |
3904 | be moved into an integer register using a high/lo_sum | |
3905 | instruction sequence | |
3906 | ||
3907 | @item T | |
3908 | Memory address aligned to an 8-byte boundary | |
3909 | ||
3910 | @item U | |
3911 | Even register | |
3912 | ||
3913 | @item W | |
3914 | Memory address for @samp{e} constraint registers | |
3915 | ||
3916 | @item w | |
3917 | Memory address with only a base register | |
3918 | ||
3919 | @item Y | |
3920 | Vector zero | |
3921 | ||
3922 | @end table | |
3923 | ||
3924 | @item TI C6X family---@file{config/c6x/constraints.md} | |
3925 | @table @code | |
3926 | @item a | |
3927 | Register file A (A0--A31). | |
3928 | ||
3929 | @item b | |
3930 | Register file B (B0--B31). | |
3931 | ||
3932 | @item A | |
3933 | Predicate registers in register file A (A0--A2 on C64X and | |
3934 | higher, A1 and A2 otherwise). | |
3935 | ||
3936 | @item B | |
3937 | Predicate registers in register file B (B0--B2). | |
3938 | ||
3939 | @item C | |
3940 | A call-used register in register file B (B0--B9, B16--B31). | |
3941 | ||
3942 | @item Da | |
3943 | Register file A, excluding predicate registers (A3--A31, | |
3944 | plus A0 if not C64X or higher). | |
3945 | ||
3946 | @item Db | |
3947 | Register file B, excluding predicate registers (B3--B31). | |
3948 | ||
3949 | @item Iu4 | |
3950 | Integer constant in the range 0 @dots{} 15. | |
3951 | ||
3952 | @item Iu5 | |
3953 | Integer constant in the range 0 @dots{} 31. | |
3954 | ||
3955 | @item In5 | |
3956 | Integer constant in the range @minus{}31 @dots{} 0. | |
3957 | ||
3958 | @item Is5 | |
3959 | Integer constant in the range @minus{}16 @dots{} 15. | |
3960 | ||
3961 | @item I5x | |
3962 | Integer constant that can be the operand of an ADDA or a SUBA insn. | |
3963 | ||
3964 | @item IuB | |
3965 | Integer constant in the range 0 @dots{} 65535. | |
3966 | ||
3967 | @item IsB | |
3968 | Integer constant in the range @minus{}32768 @dots{} 32767. | |
3969 | ||
3970 | @item IsC | |
3971 | Integer constant in the range @math{-2^{20}} @dots{} @math{2^{20} - 1}. | |
3972 | ||
3973 | @item Jc | |
3974 | Integer constant that is a valid mask for the clr instruction. | |
3975 | ||
3976 | @item Js | |
3977 | Integer constant that is a valid mask for the set instruction. | |
3978 | ||
3979 | @item Q | |
3980 | Memory location with A base register. | |
3981 | ||
3982 | @item R | |
3983 | Memory location with B base register. | |
3984 | ||
3985 | @ifset INTERNALS | |
3986 | @item S0 | |
3987 | On C64x+ targets, a GP-relative small data reference. | |
3988 | ||
3989 | @item S1 | |
3990 | Any kind of @code{SYMBOL_REF}, for use in a call address. | |
3991 | ||
3992 | @item Si | |
3993 | Any kind of immediate operand, unless it matches the S0 constraint. | |
3994 | ||
3995 | @item T | |
3996 | Memory location with B base register, but not using a long offset. | |
3997 | ||
3998 | @item W | |
3999 | A memory operand with an address that cannot be used in an unaligned access. | |
4000 | ||
4001 | @end ifset | |
4002 | @item Z | |
4003 | Register B14 (aka DP). | |
4004 | ||
4005 | @end table | |
4006 | ||
4007 | @item Visium---@file{config/visium/constraints.md} | |
4008 | @table @code | |
4009 | @item b | |
4010 | EAM register @code{mdb} | |
4011 | ||
4012 | @item c | |
4013 | EAM register @code{mdc} | |
4014 | ||
4015 | @item f | |
4016 | Floating point register | |
4017 | ||
4018 | @ifset INTERNALS | |
4019 | @item k | |
4020 | Register for sibcall optimization | |
4021 | @end ifset | |
4022 | ||
4023 | @item l | |
4024 | General register, but not @code{r29}, @code{r30} and @code{r31} | |
4025 | ||
4026 | @item t | |
4027 | Register @code{r1} | |
4028 | ||
4029 | @item u | |
4030 | Register @code{r2} | |
4031 | ||
4032 | @item v | |
4033 | Register @code{r3} | |
4034 | ||
4035 | @item G | |
4036 | Floating-point constant 0.0 | |
4037 | ||
4038 | @item J | |
4039 | Integer constant in the range 0 .. 65535 (16-bit immediate) | |
4040 | ||
4041 | @item K | |
4042 | Integer constant in the range 1 .. 31 (5-bit immediate) | |
4043 | ||
4044 | @item L | |
4045 | Integer constant in the range @minus{}65535 .. @minus{}1 (16-bit negative immediate) | |
4046 | ||
4047 | @item M | |
4048 | Integer constant @minus{}1 | |
4049 | ||
4050 | @item O | |
4051 | Integer constant 0 | |
4052 | ||
4053 | @item P | |
4054 | Integer constant 32 | |
4055 | @end table | |
4056 | ||
4057 | @item x86 family---@file{config/i386/constraints.md} | |
4058 | @table @code | |
4059 | @item R | |
4060 | Legacy register---the eight integer registers available on all | |
4061 | i386 processors (@code{a}, @code{b}, @code{c}, @code{d}, | |
4062 | @code{si}, @code{di}, @code{bp}, @code{sp}). | |
4063 | ||
4064 | @item q | |
4065 | Any register accessible as @code{@var{r}l}. In 32-bit mode, @code{a}, | |
4066 | @code{b}, @code{c}, and @code{d}; in 64-bit mode, any integer register. | |
4067 | ||
4068 | @item Q | |
4069 | Any register accessible as @code{@var{r}h}: @code{a}, @code{b}, | |
4070 | @code{c}, and @code{d}. | |
4071 | ||
4072 | @ifset INTERNALS | |
4073 | @item l | |
4074 | Any register that can be used as the index in a base+index memory | |
4075 | access: that is, any general register except the stack pointer. | |
4076 | @end ifset | |
4077 | ||
4078 | @item a | |
4079 | The @code{a} register. | |
4080 | ||
4081 | @item b | |
4082 | The @code{b} register. | |
4083 | ||
4084 | @item c | |
4085 | The @code{c} register. | |
4086 | ||
4087 | @item d | |
4088 | The @code{d} register. | |
4089 | ||
4090 | @item S | |
4091 | The @code{si} register. | |
4092 | ||
4093 | @item D | |
4094 | The @code{di} register. | |
4095 | ||
4096 | @item A | |
4097 | The @code{a} and @code{d} registers. This class is used for instructions | |
4098 | that return double word results in the @code{ax:dx} register pair. Single | |
4099 | word values will be allocated either in @code{ax} or @code{dx}. | |
4100 | For example on i386 the following implements @code{rdtsc}: | |
4101 | ||
4102 | @smallexample | |
4103 | unsigned long long rdtsc (void) | |
4104 | @{ | |
4105 | unsigned long long tick; | |
4106 | __asm__ __volatile__("rdtsc":"=A"(tick)); | |
4107 | return tick; | |
4108 | @} | |
4109 | @end smallexample | |
4110 | ||
4111 | This is not correct on x86-64 as it would allocate tick in either @code{ax} | |
4112 | or @code{dx}. You have to use the following variant instead: | |
4113 | ||
4114 | @smallexample | |
4115 | unsigned long long rdtsc (void) | |
4116 | @{ | |
4117 | unsigned int tickl, tickh; | |
4118 | __asm__ __volatile__("rdtsc":"=a"(tickl),"=d"(tickh)); | |
4119 | return ((unsigned long long)tickh << 32)|tickl; | |
4120 | @} | |
4121 | @end smallexample | |
4122 | ||
4123 | @item U | |
4124 | The call-clobbered integer registers. | |
4125 | ||
4126 | @item f | |
4127 | Any 80387 floating-point (stack) register. | |
4128 | ||
4129 | @item t | |
4130 | Top of 80387 floating-point stack (@code{%st(0)}). | |
4131 | ||
4132 | @item u | |
4133 | Second from top of 80387 floating-point stack (@code{%st(1)}). | |
4134 | ||
4135 | @ifset INTERNALS | |
4136 | @item Yk | |
4137 | Any mask register that can be used as a predicate, i.e.@: @code{k1-k7}. | |
4138 | ||
4139 | @item k | |
4140 | Any mask register. | |
4141 | @end ifset | |
4142 | ||
4143 | @item y | |
4144 | Any MMX register. | |
4145 | ||
4146 | @item x | |
4147 | Any SSE register. | |
4148 | ||
4149 | @item v | |
4150 | Any EVEX encodable SSE register (@code{%xmm0-%xmm31}). | |
4151 | ||
4152 | @ifset INTERNALS | |
4153 | @item w | |
4154 | Any bound register. | |
4155 | @end ifset | |
4156 | ||
4157 | @item Yz | |
4158 | First SSE register (@code{%xmm0}). | |
4159 | ||
4160 | @ifset INTERNALS | |
4161 | @item Yi | |
4162 | Any SSE register, when SSE2 and inter-unit moves are enabled. | |
4163 | ||
4164 | @item Yj | |
4165 | Any SSE register, when SSE2 and inter-unit moves from vector registers are enabled. | |
4166 | ||
4167 | @item Ym | |
4168 | Any MMX register, when inter-unit moves are enabled. | |
4169 | ||
4170 | @item Yn | |
4171 | Any MMX register, when inter-unit moves from vector registers are enabled. | |
4172 | ||
4173 | @item Yp | |
4174 | Any integer register when @code{TARGET_PARTIAL_REG_STALL} is disabled. | |
4175 | ||
4176 | @item Ya | |
4177 | Any integer register when zero extensions with @code{AND} are disabled. | |
4178 | ||
4179 | @item Yb | |
4180 | Any register that can be used as the GOT base when calling@* | |
4181 | @code{___tls_get_addr}: that is, any general register except @code{a} | |
4182 | and @code{sp} registers, for @option{-fno-plt} if linker supports it. | |
4183 | Otherwise, @code{b} register. | |
4184 | ||
4185 | @item Yf | |
4186 | Any x87 register when 80387 floating-point arithmetic is enabled. | |
4187 | ||
4188 | @item Yr | |
4189 | Lower SSE register when avoiding REX prefix and all SSE registers otherwise. | |
4190 | ||
4191 | @item Yv | |
4192 | For AVX512VL, any EVEX-encodable SSE register (@code{%xmm0-%xmm31}), | |
4193 | otherwise any SSE register. | |
4194 | ||
4195 | @item Yh | |
4196 | Any EVEX-encodable SSE register, that has number factor of four. | |
4197 | ||
4198 | @item Bf | |
4199 | Flags register operand. | |
4200 | ||
4201 | @item Bg | |
4202 | GOT memory operand. | |
4203 | ||
4204 | @item Bm | |
4205 | Vector memory operand. | |
4206 | ||
4207 | @item Bc | |
4208 | Constant memory operand. | |
4209 | ||
4210 | @item Bn | |
4211 | Memory operand without REX prefix. | |
4212 | ||
4213 | @item Bs | |
4214 | Sibcall memory operand. | |
4215 | ||
4216 | @item Bw | |
4217 | Call memory operand. | |
4218 | ||
4219 | @item Bz | |
4220 | Constant call address operand. | |
4221 | ||
4222 | @item BC | |
4223 | SSE constant -1 operand. | |
4224 | @end ifset | |
4225 | ||
4226 | @item I | |
4227 | Integer constant in the range 0 @dots{} 31, for 32-bit shifts. | |
4228 | ||
4229 | @item J | |
4230 | Integer constant in the range 0 @dots{} 63, for 64-bit shifts. | |
4231 | ||
4232 | @item K | |
4233 | Signed 8-bit integer constant. | |
4234 | ||
4235 | @item L | |
4236 | @code{0xFF} or @code{0xFFFF}, for andsi as a zero-extending move. | |
4237 | ||
4238 | @item M | |
4239 | 0, 1, 2, or 3 (shifts for the @code{lea} instruction). | |
4240 | ||
4241 | @item N | |
4242 | Unsigned 8-bit integer constant (for @code{in} and @code{out} | |
4243 | instructions). | |
4244 | ||
4245 | @ifset INTERNALS | |
4246 | @item O | |
4247 | Integer constant in the range 0 @dots{} 127, for 128-bit shifts. | |
4248 | @end ifset | |
4249 | ||
4250 | @item G | |
4251 | Standard 80387 floating point constant. | |
4252 | ||
4253 | @item C | |
4254 | SSE constant zero operand. | |
4255 | ||
4256 | @item e | |
4257 | 32-bit signed integer constant, or a symbolic reference known | |
4258 | to fit that range (for immediate operands in sign-extending x86-64 | |
4259 | instructions). | |
4260 | ||
4261 | @item We | |
4262 | 32-bit signed integer constant, or a symbolic reference known | |
4263 | to fit that range (for sign-extending conversion operations that | |
4264 | require non-@code{VOIDmode} immediate operands). | |
4265 | ||
4266 | @item Wz | |
4267 | 32-bit unsigned integer constant, or a symbolic reference known | |
4268 | to fit that range (for zero-extending conversion operations that | |
4269 | require non-@code{VOIDmode} immediate operands). | |
4270 | ||
4271 | @item Wd | |
4272 | 128-bit integer constant where both the high and low 64-bit word | |
4273 | satisfy the @code{e} constraint. | |
4274 | ||
4275 | @item Z | |
4276 | 32-bit unsigned integer constant, or a symbolic reference known | |
4277 | to fit that range (for immediate operands in zero-extending x86-64 | |
4278 | instructions). | |
4279 | ||
4280 | @item Tv | |
4281 | VSIB address operand. | |
4282 | ||
4283 | @item Ts | |
4284 | Address operand without segment register. | |
4285 | ||
4286 | @end table | |
4287 | ||
4288 | @item Xstormy16---@file{config/stormy16/stormy16.h} | |
4289 | @table @code | |
4290 | @item a | |
4291 | Register r0. | |
4292 | ||
4293 | @item b | |
4294 | Register r1. | |
4295 | ||
4296 | @item c | |
4297 | Register r2. | |
4298 | ||
4299 | @item d | |
4300 | Register r8. | |
4301 | ||
4302 | @item e | |
4303 | Registers r0 through r7. | |
4304 | ||
4305 | @item t | |
4306 | Registers r0 and r1. | |
4307 | ||
4308 | @item y | |
4309 | The carry register. | |
4310 | ||
4311 | @item z | |
4312 | Registers r8 and r9. | |
4313 | ||
4314 | @item I | |
4315 | A constant between 0 and 3 inclusive. | |
4316 | ||
4317 | @item J | |
4318 | A constant that has exactly one bit set. | |
4319 | ||
4320 | @item K | |
4321 | A constant that has exactly one bit clear. | |
4322 | ||
4323 | @item L | |
4324 | A constant between 0 and 255 inclusive. | |
4325 | ||
4326 | @item M | |
4327 | A constant between @minus{}255 and 0 inclusive. | |
4328 | ||
4329 | @item N | |
4330 | A constant between @minus{}3 and 0 inclusive. | |
4331 | ||
4332 | @item O | |
4333 | A constant between 1 and 4 inclusive. | |
4334 | ||
4335 | @item P | |
4336 | A constant between @minus{}4 and @minus{}1 inclusive. | |
4337 | ||
4338 | @item Q | |
4339 | A memory reference that is a stack push. | |
4340 | ||
4341 | @item R | |
4342 | A memory reference that is a stack pop. | |
4343 | ||
4344 | @item S | |
4345 | A memory reference that refers to a constant address of known value. | |
4346 | ||
4347 | @item T | |
4348 | The register indicated by Rx (not implemented yet). | |
4349 | ||
4350 | @item U | |
4351 | A constant that is not between 2 and 15 inclusive. | |
4352 | ||
4353 | @item Z | |
4354 | The constant 0. | |
4355 | ||
4356 | @end table | |
4357 | ||
4358 | @item Xtensa---@file{config/xtensa/constraints.md} | |
4359 | @table @code | |
4360 | @item a | |
4361 | General-purpose 32-bit register | |
4362 | ||
4363 | @item b | |
4364 | One-bit boolean register | |
4365 | ||
4366 | @item A | |
4367 | MAC16 40-bit accumulator register | |
4368 | ||
4369 | @item I | |
4370 | Signed 12-bit integer constant, for use in MOVI instructions | |
4371 | ||
4372 | @item J | |
4373 | Signed 8-bit integer constant, for use in ADDI instructions | |
4374 | ||
4375 | @item K | |
4376 | Integer constant valid for BccI instructions | |
4377 | ||
4378 | @item L | |
4379 | Unsigned constant valid for BccUI instructions | |
4380 | ||
4381 | @end table | |
4382 | ||
4383 | @end table | |
4384 | ||
4385 | @ifset INTERNALS | |
4386 | @node Disable Insn Alternatives | |
4387 | @subsection Disable insn alternatives using the @code{enabled} attribute | |
4388 | @cindex enabled | |
4389 | ||
4390 | There are three insn attributes that may be used to selectively disable | |
4391 | instruction alternatives: | |
4392 | ||
4393 | @table @code | |
4394 | @item enabled | |
4395 | Says whether an alternative is available on the current subtarget. | |
4396 | ||
4397 | @item preferred_for_size | |
4398 | Says whether an enabled alternative should be used in code that is | |
4399 | optimized for size. | |
4400 | ||
4401 | @item preferred_for_speed | |
4402 | Says whether an enabled alternative should be used in code that is | |
4403 | optimized for speed. | |
4404 | @end table | |
4405 | ||
4406 | All these attributes should use @code{(const_int 1)} to allow an alternative | |
4407 | or @code{(const_int 0)} to disallow it. The attributes must be a static | |
4408 | property of the subtarget; they cannot for example depend on the | |
4409 | current operands, on the current optimization level, on the location | |
4410 | of the insn within the body of a loop, on whether register allocation | |
4411 | has finished, or on the current compiler pass. | |
4412 | ||
4413 | The @code{enabled} attribute is a correctness property. It tells GCC to act | |
4414 | as though the disabled alternatives were never defined in the first place. | |
4415 | This is useful when adding new instructions to an existing pattern in | |
4416 | cases where the new instructions are only available for certain cpu | |
4417 | architecture levels (typically mapped to the @code{-march=} command-line | |
4418 | option). | |
4419 | ||
4420 | In contrast, the @code{preferred_for_size} and @code{preferred_for_speed} | |
4421 | attributes are strong optimization hints rather than correctness properties. | |
4422 | @code{preferred_for_size} tells GCC which alternatives to consider when | |
4423 | adding or modifying an instruction that GCC wants to optimize for size. | |
4424 | @code{preferred_for_speed} does the same thing for speed. Note that things | |
4425 | like code motion can lead to cases where code optimized for size uses | |
4426 | alternatives that are not preferred for size, and similarly for speed. | |
4427 | ||
4428 | Although @code{define_insn}s can in principle specify the @code{enabled} | |
4429 | attribute directly, it is often clearer to have subsiduary attributes | |
4430 | for each architectural feature of interest. The @code{define_insn}s | |
4431 | can then use these subsiduary attributes to say which alternatives | |
4432 | require which features. The example below does this for @code{cpu_facility}. | |
4433 | ||
4434 | E.g. the following two patterns could easily be merged using the @code{enabled} | |
4435 | attribute: | |
4436 | ||
4437 | @smallexample | |
4438 | ||
4439 | (define_insn "*movdi_old" | |
4440 | [(set (match_operand:DI 0 "register_operand" "=d") | |
4441 | (match_operand:DI 1 "register_operand" " d"))] | |
4442 | "!TARGET_NEW" | |
4443 | "lgr %0,%1") | |
4444 | ||
4445 | (define_insn "*movdi_new" | |
4446 | [(set (match_operand:DI 0 "register_operand" "=d,f,d") | |
4447 | (match_operand:DI 1 "register_operand" " d,d,f"))] | |
4448 | "TARGET_NEW" | |
4449 | "@@ | |
4450 | lgr %0,%1 | |
4451 | ldgr %0,%1 | |
4452 | lgdr %0,%1") | |
4453 | ||
4454 | @end smallexample | |
4455 | ||
4456 | to: | |
4457 | ||
4458 | @smallexample | |
4459 | ||
4460 | (define_insn "*movdi_combined" | |
4461 | [(set (match_operand:DI 0 "register_operand" "=d,f,d") | |
4462 | (match_operand:DI 1 "register_operand" " d,d,f"))] | |
4463 | "" | |
4464 | "@@ | |
4465 | lgr %0,%1 | |
4466 | ldgr %0,%1 | |
4467 | lgdr %0,%1" | |
4468 | [(set_attr "cpu_facility" "*,new,new")]) | |
4469 | ||
4470 | @end smallexample | |
4471 | ||
4472 | with the @code{enabled} attribute defined like this: | |
4473 | ||
4474 | @smallexample | |
4475 | ||
4476 | (define_attr "cpu_facility" "standard,new" (const_string "standard")) | |
4477 | ||
4478 | (define_attr "enabled" "" | |
4479 | (cond [(eq_attr "cpu_facility" "standard") (const_int 1) | |
4480 | (and (eq_attr "cpu_facility" "new") | |
4481 | (ne (symbol_ref "TARGET_NEW") (const_int 0))) | |
4482 | (const_int 1)] | |
4483 | (const_int 0))) | |
4484 | ||
4485 | @end smallexample | |
4486 | ||
4487 | @end ifset | |
4488 | ||
4489 | @ifset INTERNALS | |
4490 | @node Define Constraints | |
4491 | @subsection Defining Machine-Specific Constraints | |
4492 | @cindex defining constraints | |
4493 | @cindex constraints, defining | |
4494 | ||
4495 | Machine-specific constraints fall into two categories: register and | |
4496 | non-register constraints. Within the latter category, constraints | |
4497 | which allow subsets of all possible memory or address operands should | |
4498 | be specially marked, to give @code{reload} more information. | |
4499 | ||
4500 | Machine-specific constraints can be given names of arbitrary length, | |
4501 | but they must be entirely composed of letters, digits, underscores | |
4502 | (@samp{_}), and angle brackets (@samp{< >}). Like C identifiers, they | |
4503 | must begin with a letter or underscore. | |
4504 | ||
4505 | In order to avoid ambiguity in operand constraint strings, no | |
4506 | constraint can have a name that begins with any other constraint's | |
4507 | name. For example, if @code{x} is defined as a constraint name, | |
4508 | @code{xy} may not be, and vice versa. As a consequence of this rule, | |
4509 | no constraint may begin with one of the generic constraint letters: | |
4510 | @samp{E F V X g i m n o p r s}. | |
4511 | ||
4512 | Register constraints correspond directly to register classes. | |
4513 | @xref{Register Classes}. There is thus not much flexibility in their | |
4514 | definitions. | |
4515 | ||
4516 | @deffn {MD Expression} define_register_constraint name regclass docstring | |
4517 | All three arguments are string constants. | |
4518 | @var{name} is the name of the constraint, as it will appear in | |
4519 | @code{match_operand} expressions. If @var{name} is a multi-letter | |
4520 | constraint its length shall be the same for all constraints starting | |
4521 | with the same letter. @var{regclass} can be either the | |
4522 | name of the corresponding register class (@pxref{Register Classes}), | |
4523 | or a C expression which evaluates to the appropriate register class. | |
4524 | If it is an expression, it must have no side effects, and it cannot | |
4525 | look at the operand. The usual use of expressions is to map some | |
4526 | register constraints to @code{NO_REGS} when the register class | |
4527 | is not available on a given subarchitecture. | |
4528 | ||
4529 | @var{docstring} is a sentence documenting the meaning of the | |
4530 | constraint. Docstrings are explained further below. | |
4531 | @end deffn | |
4532 | ||
4533 | Non-register constraints are more like predicates: the constraint | |
4534 | definition gives a boolean expression which indicates whether the | |
4535 | constraint matches. | |
4536 | ||
4537 | @deffn {MD Expression} define_constraint name docstring exp | |
4538 | The @var{name} and @var{docstring} arguments are the same as for | |
4539 | @code{define_register_constraint}, but note that the docstring comes | |
4540 | immediately after the name for these expressions. @var{exp} is an RTL | |
4541 | expression, obeying the same rules as the RTL expressions in predicate | |
4542 | definitions. @xref{Defining Predicates}, for details. If it | |
4543 | evaluates true, the constraint matches; if it evaluates false, it | |
4544 | doesn't. Constraint expressions should indicate which RTL codes they | |
4545 | might match, just like predicate expressions. | |
4546 | ||
4547 | @code{match_test} C expressions have access to the | |
4548 | following variables: | |
4549 | ||
4550 | @table @var | |
4551 | @item op | |
4552 | The RTL object defining the operand. | |
4553 | @item mode | |
4554 | The machine mode of @var{op}. | |
4555 | @item ival | |
4556 | @samp{INTVAL (@var{op})}, if @var{op} is a @code{const_int}. | |
4557 | @item hval | |
4558 | @samp{CONST_DOUBLE_HIGH (@var{op})}, if @var{op} is an integer | |
4559 | @code{const_double}. | |
4560 | @item lval | |
4561 | @samp{CONST_DOUBLE_LOW (@var{op})}, if @var{op} is an integer | |
4562 | @code{const_double}. | |
4563 | @item rval | |
4564 | @samp{CONST_DOUBLE_REAL_VALUE (@var{op})}, if @var{op} is a floating-point | |
4565 | @code{const_double}. | |
4566 | @end table | |
4567 | ||
4568 | The @var{*val} variables should only be used once another piece of the | |
4569 | expression has verified that @var{op} is the appropriate kind of RTL | |
4570 | object. | |
4571 | @end deffn | |
4572 | ||
4573 | Most non-register constraints should be defined with | |
4574 | @code{define_constraint}. The remaining two definition expressions | |
4575 | are only appropriate for constraints that should be handled specially | |
4576 | by @code{reload} if they fail to match. | |
4577 | ||
4578 | @deffn {MD Expression} define_memory_constraint name docstring exp | |
4579 | Use this expression for constraints that match a subset of all memory | |
4580 | operands: that is, @code{reload} can make them match by converting the | |
4581 | operand to the form @samp{@w{(mem (reg @var{X}))}}, where @var{X} is a | |
4582 | base register (from the register class specified by | |
4583 | @code{BASE_REG_CLASS}, @pxref{Register Classes}). | |
4584 | ||
4585 | For example, on the S/390, some instructions do not accept arbitrary | |
4586 | memory references, but only those that do not make use of an index | |
4587 | register. The constraint letter @samp{Q} is defined to represent a | |
4588 | memory address of this type. If @samp{Q} is defined with | |
4589 | @code{define_memory_constraint}, a @samp{Q} constraint can handle any | |
4590 | memory operand, because @code{reload} knows it can simply copy the | |
4591 | memory address into a base register if required. This is analogous to | |
4592 | the way an @samp{o} constraint can handle any memory operand. | |
4593 | ||
4594 | The syntax and semantics are otherwise identical to | |
4595 | @code{define_constraint}. | |
4596 | @end deffn | |
4597 | ||
4598 | @deffn {MD Expression} define_special_memory_constraint name docstring exp | |
4599 | Use this expression for constraints that match a subset of all memory | |
4600 | operands: that is, @code{reload} cannot make them match by reloading | |
4601 | the address as it is described for @code{define_memory_constraint} or | |
4602 | such address reload is undesirable with the performance point of view. | |
4603 | ||
4604 | For example, @code{define_special_memory_constraint} can be useful if | |
4605 | specifically aligned memory is necessary or desirable for some insn | |
4606 | operand. | |
4607 | ||
4608 | The syntax and semantics are otherwise identical to | |
4609 | @code{define_memory_constraint}. | |
4610 | @end deffn | |
4611 | ||
4612 | @deffn {MD Expression} define_relaxed_memory_constraint name docstring exp | |
4613 | The test expression in a @code{define_memory_constraint} can assume | |
4614 | that @code{TARGET_LEGITIMATE_ADDRESS_P} holds for the address inside | |
4615 | a @code{mem} rtx and so it does not need to test this condition itself. | |
4616 | In other words, a @code{define_memory_constraint} test of the form: | |
4617 | ||
4618 | @smallexample | |
4619 | (match_test "mem") | |
4620 | @end smallexample | |
4621 | ||
4622 | is enough to test whether an rtx is a @code{mem} @emph{and} whether | |
4623 | its address satisfies @code{TARGET_MEM_CONSTRAINT} (which is usually | |
4624 | @samp{'m'}). Thus the conditions imposed by a @code{define_memory_constraint} | |
4625 | always apply on top of the conditions imposed by @code{TARGET_MEM_CONSTRAINT}. | |
4626 | ||
4627 | However, it is sometimes useful to define memory constraints that allow | |
4628 | addresses beyond those accepted by @code{TARGET_LEGITIMATE_ADDRESS_P}. | |
4629 | @code{define_relaxed_memory_constraint} exists for this case. | |
4630 | The test expression in a @code{define_relaxed_memory_constraint} is | |
4631 | applied with no preconditions, so that the expression can determine | |
4632 | ``from scratch'' exactly which addresses are valid and which are not. | |
4633 | ||
4634 | The syntax and semantics are otherwise identical to | |
4635 | @code{define_memory_constraint}. | |
4636 | @end deffn | |
4637 | ||
4638 | @deffn {MD Expression} define_address_constraint name docstring exp | |
4639 | Use this expression for constraints that match a subset of all address | |
4640 | operands: that is, @code{reload} can make the constraint match by | |
4641 | converting the operand to the form @samp{@w{(reg @var{X})}}, again | |
4642 | with @var{X} a base register. | |
4643 | ||
4644 | Constraints defined with @code{define_address_constraint} can only be | |
4645 | used with the @code{address_operand} predicate, or machine-specific | |
4646 | predicates that work the same way. They are treated analogously to | |
4647 | the generic @samp{p} constraint. | |
4648 | ||
4649 | The syntax and semantics are otherwise identical to | |
4650 | @code{define_constraint}. | |
4651 | @end deffn | |
4652 | ||
4653 | For historical reasons, names beginning with the letters @samp{G H} | |
4654 | are reserved for constraints that match only @code{const_double}s, and | |
4655 | names beginning with the letters @samp{I J K L M N O P} are reserved | |
4656 | for constraints that match only @code{const_int}s. This may change in | |
4657 | the future. For the time being, constraints with these names must be | |
4658 | written in a stylized form, so that @code{genpreds} can tell you did | |
4659 | it correctly: | |
4660 | ||
4661 | @smallexample | |
4662 | @group | |
4663 | (define_constraint "[@var{GHIJKLMNOP}]@dots{}" | |
4664 | "@var{doc}@dots{}" | |
4665 | (and (match_code "const_int") ; @r{@code{const_double} for G/H} | |
4666 | @var{condition}@dots{})) ; @r{usually a @code{match_test}} | |
4667 | @end group | |
4668 | @end smallexample | |
4669 | @c the semicolons line up in the formatted manual | |
4670 | ||
4671 | It is fine to use names beginning with other letters for constraints | |
4672 | that match @code{const_double}s or @code{const_int}s. | |
4673 | ||
4674 | Each docstring in a constraint definition should be one or more complete | |
4675 | sentences, marked up in Texinfo format. @emph{They are currently unused.} | |
4676 | In the future they will be copied into the GCC manual, in @ref{Machine | |
4677 | Constraints}, replacing the hand-maintained tables currently found in | |
4678 | that section. Also, in the future the compiler may use this to give | |
4679 | more helpful diagnostics when poor choice of @code{asm} constraints | |
4680 | causes a reload failure. | |
4681 | ||
4682 | If you put the pseudo-Texinfo directive @samp{@@internal} at the | |
4683 | beginning of a docstring, then (in the future) it will appear only in | |
4684 | the internals manual's version of the machine-specific constraint tables. | |
4685 | Use this for constraints that should not appear in @code{asm} statements. | |
4686 | ||
4687 | @node C Constraint Interface | |
4688 | @subsection Testing constraints from C | |
4689 | @cindex testing constraints | |
4690 | @cindex constraints, testing | |
4691 | ||
4692 | It is occasionally useful to test a constraint from C code rather than | |
4693 | implicitly via the constraint string in a @code{match_operand}. The | |
4694 | generated file @file{tm_p.h} declares a few interfaces for working | |
4695 | with constraints. At present these are defined for all constraints | |
4696 | except @code{g} (which is equivalent to @code{general_operand}). | |
4697 | ||
4698 | Some valid constraint names are not valid C identifiers, so there is a | |
4699 | mangling scheme for referring to them from C@. Constraint names that | |
4700 | do not contain angle brackets or underscores are left unchanged. | |
4701 | Underscores are doubled, each @samp{<} is replaced with @samp{_l}, and | |
4702 | each @samp{>} with @samp{_g}. Here are some examples: | |
4703 | ||
4704 | @c the @c's prevent double blank lines in the printed manual. | |
4705 | @example | |
4706 | @multitable {Original} {Mangled} | |
4707 | @item @strong{Original} @tab @strong{Mangled} @c | |
4708 | @item @code{x} @tab @code{x} @c | |
4709 | @item @code{P42x} @tab @code{P42x} @c | |
4710 | @item @code{P4_x} @tab @code{P4__x} @c | |
4711 | @item @code{P4>x} @tab @code{P4_gx} @c | |
4712 | @item @code{P4>>} @tab @code{P4_g_g} @c | |
4713 | @item @code{P4_g>} @tab @code{P4__g_g} @c | |
4714 | @end multitable | |
4715 | @end example | |
4716 | ||
4717 | Throughout this section, the variable @var{c} is either a constraint | |
4718 | in the abstract sense, or a constant from @code{enum constraint_num}; | |
4719 | the variable @var{m} is a mangled constraint name (usually as part of | |
4720 | a larger identifier). | |
4721 | ||
4722 | @deftp Enum constraint_num | |
4723 | For each constraint except @code{g}, there is a corresponding | |
4724 | enumeration constant: @samp{CONSTRAINT_} plus the mangled name of the | |
4725 | constraint. Functions that take an @code{enum constraint_num} as an | |
4726 | argument expect one of these constants. | |
4727 | @end deftp | |
4728 | ||
4729 | @deftypefun {inline bool} satisfies_constraint_@var{m} (rtx @var{exp}) | |
4730 | For each non-register constraint @var{m} except @code{g}, there is | |
4731 | one of these functions; it returns @code{true} if @var{exp} satisfies the | |
4732 | constraint. These functions are only visible if @file{rtl.h} was included | |
4733 | before @file{tm_p.h}. | |
4734 | @end deftypefun | |
4735 | ||
4736 | @deftypefun bool constraint_satisfied_p (rtx @var{exp}, enum constraint_num @var{c}) | |
4737 | Like the @code{satisfies_constraint_@var{m}} functions, but the | |
4738 | constraint to test is given as an argument, @var{c}. If @var{c} | |
4739 | specifies a register constraint, this function will always return | |
4740 | @code{false}. | |
4741 | @end deftypefun | |
4742 | ||
4743 | @deftypefun {enum reg_class} reg_class_for_constraint (enum constraint_num @var{c}) | |
4744 | Returns the register class associated with @var{c}. If @var{c} is not | |
4745 | a register constraint, or those registers are not available for the | |
4746 | currently selected subtarget, returns @code{NO_REGS}. | |
4747 | @end deftypefun | |
4748 | ||
4749 | Here is an example use of @code{satisfies_constraint_@var{m}}. In | |
4750 | peephole optimizations (@pxref{Peephole Definitions}), operand | |
4751 | constraint strings are ignored, so if there are relevant constraints, | |
4752 | they must be tested in the C condition. In the example, the | |
4753 | optimization is applied if operand 2 does @emph{not} satisfy the | |
4754 | @samp{K} constraint. (This is a simplified version of a peephole | |
4755 | definition from the i386 machine description.) | |
4756 | ||
4757 | @smallexample | |
4758 | (define_peephole2 | |
4759 | [(match_scratch:SI 3 "r") | |
4760 | (set (match_operand:SI 0 "register_operand" "") | |
4761 | (mult:SI (match_operand:SI 1 "memory_operand" "") | |
4762 | (match_operand:SI 2 "immediate_operand" "")))] | |
4763 | ||
4764 | "!satisfies_constraint_K (operands[2])" | |
4765 | ||
4766 | [(set (match_dup 3) (match_dup 1)) | |
4767 | (set (match_dup 0) (mult:SI (match_dup 3) (match_dup 2)))] | |
4768 | ||
4769 | "") | |
4770 | @end smallexample | |
4771 | ||
4772 | @node Standard Names | |
4773 | @section Standard Pattern Names For Generation | |
4774 | @cindex standard pattern names | |
4775 | @cindex pattern names | |
4776 | @cindex names, pattern | |
4777 | ||
4778 | Here is a table of the instruction names that are meaningful in the RTL | |
4779 | generation pass of the compiler. Giving one of these names to an | |
4780 | instruction pattern tells the RTL generation pass that it can use the | |
4781 | pattern to accomplish a certain task. | |
4782 | ||
4783 | @table @asis | |
4784 | @cindex @code{mov@var{m}} instruction pattern | |
4785 | @item @samp{mov@var{m}} | |
4786 | Here @var{m} stands for a two-letter machine mode name, in lowercase. | |
4787 | This instruction pattern moves data with that machine mode from operand | |
4788 | 1 to operand 0. For example, @samp{movsi} moves full-word data. | |
4789 | ||
4790 | If operand 0 is a @code{subreg} with mode @var{m} of a register whose | |
4791 | own mode is wider than @var{m}, the effect of this instruction is | |
4792 | to store the specified value in the part of the register that corresponds | |
4793 | to mode @var{m}. Bits outside of @var{m}, but which are within the | |
4794 | same target word as the @code{subreg} are undefined. Bits which are | |
4795 | outside the target word are left unchanged. | |
4796 | ||
4797 | This class of patterns is special in several ways. First of all, each | |
4798 | of these names up to and including full word size @emph{must} be defined, | |
4799 | because there is no other way to copy a datum from one place to another. | |
4800 | If there are patterns accepting operands in larger modes, | |
4801 | @samp{mov@var{m}} must be defined for integer modes of those sizes. | |
4802 | ||
4803 | Second, these patterns are not used solely in the RTL generation pass. | |
4804 | Even the reload pass can generate move insns to copy values from stack | |
4805 | slots into temporary registers. When it does so, one of the operands is | |
4806 | a hard register and the other is an operand that can need to be reloaded | |
4807 | into a register. | |
4808 | ||
4809 | @findex force_reg | |
4810 | Therefore, when given such a pair of operands, the pattern must generate | |
4811 | RTL which needs no reloading and needs no temporary registers---no | |
4812 | registers other than the operands. For example, if you support the | |
4813 | pattern with a @code{define_expand}, then in such a case the | |
4814 | @code{define_expand} mustn't call @code{force_reg} or any other such | |
4815 | function which might generate new pseudo registers. | |
4816 | ||
4817 | This requirement exists even for subword modes on a RISC machine where | |
4818 | fetching those modes from memory normally requires several insns and | |
4819 | some temporary registers. | |
4820 | ||
4821 | @findex change_address | |
4822 | During reload a memory reference with an invalid address may be passed | |
4823 | as an operand. Such an address will be replaced with a valid address | |
4824 | later in the reload pass. In this case, nothing may be done with the | |
4825 | address except to use it as it stands. If it is copied, it will not be | |
4826 | replaced with a valid address. No attempt should be made to make such | |
4827 | an address into a valid address and no routine (such as | |
4828 | @code{change_address}) that will do so may be called. Note that | |
4829 | @code{general_operand} will fail when applied to such an address. | |
4830 | ||
4831 | @findex reload_in_progress | |
4832 | The global variable @code{reload_in_progress} (which must be explicitly | |
4833 | declared if required) can be used to determine whether such special | |
4834 | handling is required. | |
4835 | ||
4836 | The variety of operands that have reloads depends on the rest of the | |
4837 | machine description, but typically on a RISC machine these can only be | |
4838 | pseudo registers that did not get hard registers, while on other | |
4839 | machines explicit memory references will get optional reloads. | |
4840 | ||
4841 | If a scratch register is required to move an object to or from memory, | |
4842 | it can be allocated using @code{gen_reg_rtx} prior to life analysis. | |
4843 | ||
4844 | If there are cases which need scratch registers during or after reload, | |
4845 | you must provide an appropriate secondary_reload target hook. | |
4846 | ||
4847 | @findex can_create_pseudo_p | |
4848 | The macro @code{can_create_pseudo_p} can be used to determine if it | |
4849 | is unsafe to create new pseudo registers. If this variable is nonzero, then | |
4850 | it is unsafe to call @code{gen_reg_rtx} to allocate a new pseudo. | |
4851 | ||
4852 | The constraints on a @samp{mov@var{m}} must permit moving any hard | |
4853 | register to any other hard register provided that | |
4854 | @code{TARGET_HARD_REGNO_MODE_OK} permits mode @var{m} in both registers and | |
4855 | @code{TARGET_REGISTER_MOVE_COST} applied to their classes returns a value | |
4856 | of 2. | |
4857 | ||
4858 | It is obligatory to support floating point @samp{mov@var{m}} | |
4859 | instructions into and out of any registers that can hold fixed point | |
4860 | values, because unions and structures (which have modes @code{SImode} or | |
4861 | @code{DImode}) can be in those registers and they may have floating | |
4862 | point members. | |
4863 | ||
4864 | There may also be a need to support fixed point @samp{mov@var{m}} | |
4865 | instructions in and out of floating point registers. Unfortunately, I | |
4866 | have forgotten why this was so, and I don't know whether it is still | |
4867 | true. If @code{TARGET_HARD_REGNO_MODE_OK} rejects fixed point values in | |
4868 | floating point registers, then the constraints of the fixed point | |
4869 | @samp{mov@var{m}} instructions must be designed to avoid ever trying to | |
4870 | reload into a floating point register. | |
4871 | ||
4872 | @cindex @code{reload_in} instruction pattern | |
4873 | @cindex @code{reload_out} instruction pattern | |
4874 | @item @samp{reload_in@var{m}} | |
4875 | @itemx @samp{reload_out@var{m}} | |
4876 | These named patterns have been obsoleted by the target hook | |
4877 | @code{secondary_reload}. | |
4878 | ||
4879 | Like @samp{mov@var{m}}, but used when a scratch register is required to | |
4880 | move between operand 0 and operand 1. Operand 2 describes the scratch | |
4881 | register. See the discussion of the @code{SECONDARY_RELOAD_CLASS} | |
4882 | macro in @pxref{Register Classes}. | |
4883 | ||
4884 | There are special restrictions on the form of the @code{match_operand}s | |
4885 | used in these patterns. First, only the predicate for the reload | |
4886 | operand is examined, i.e., @code{reload_in} examines operand 1, but not | |
4887 | the predicates for operand 0 or 2. Second, there may be only one | |
4888 | alternative in the constraints. Third, only a single register class | |
4889 | letter may be used for the constraint; subsequent constraint letters | |
4890 | are ignored. As a special exception, an empty constraint string | |
4891 | matches the @code{ALL_REGS} register class. This may relieve ports | |
4892 | of the burden of defining an @code{ALL_REGS} constraint letter just | |
4893 | for these patterns. | |
4894 | ||
4895 | @cindex @code{movstrict@var{m}} instruction pattern | |
4896 | @item @samp{movstrict@var{m}} | |
4897 | Like @samp{mov@var{m}} except that if operand 0 is a @code{subreg} | |
4898 | with mode @var{m} of a register whose natural mode is wider, | |
4899 | the @samp{movstrict@var{m}} instruction is guaranteed not to alter | |
4900 | any of the register except the part which belongs to mode @var{m}. | |
4901 | ||
4902 | @cindex @code{movmisalign@var{m}} instruction pattern | |
4903 | @item @samp{movmisalign@var{m}} | |
4904 | This variant of a move pattern is designed to load or store a value | |
4905 | from a memory address that is not naturally aligned for its mode. | |
4906 | For a store, the memory will be in operand 0; for a load, the memory | |
4907 | will be in operand 1. The other operand is guaranteed not to be a | |
4908 | memory, so that it's easy to tell whether this is a load or store. | |
4909 | ||
4910 | This pattern is used by the autovectorizer, and when expanding a | |
4911 | @code{MISALIGNED_INDIRECT_REF} expression. | |
4912 | ||
4913 | @cindex @code{load_multiple} instruction pattern | |
4914 | @item @samp{load_multiple} | |
4915 | Load several consecutive memory locations into consecutive registers. | |
4916 | Operand 0 is the first of the consecutive registers, operand 1 | |
4917 | is the first memory location, and operand 2 is a constant: the | |
4918 | number of consecutive registers. | |
4919 | ||
4920 | Define this only if the target machine really has such an instruction; | |
4921 | do not define this if the most efficient way of loading consecutive | |
4922 | registers from memory is to do them one at a time. | |
4923 | ||
4924 | On some machines, there are restrictions as to which consecutive | |
4925 | registers can be stored into memory, such as particular starting or | |
4926 | ending register numbers or only a range of valid counts. For those | |
4927 | machines, use a @code{define_expand} (@pxref{Expander Definitions}) | |
4928 | and make the pattern fail if the restrictions are not met. | |
4929 | ||
4930 | Write the generated insn as a @code{parallel} with elements being a | |
4931 | @code{set} of one register from the appropriate memory location (you may | |
4932 | also need @code{use} or @code{clobber} elements). Use a | |
4933 | @code{match_parallel} (@pxref{RTL Template}) to recognize the insn. See | |
4934 | @file{rs6000.md} for examples of the use of this insn pattern. | |
4935 | ||
4936 | @cindex @samp{store_multiple} instruction pattern | |
4937 | @item @samp{store_multiple} | |
4938 | Similar to @samp{load_multiple}, but store several consecutive registers | |
4939 | into consecutive memory locations. Operand 0 is the first of the | |
4940 | consecutive memory locations, operand 1 is the first register, and | |
4941 | operand 2 is a constant: the number of consecutive registers. | |
4942 | ||
4943 | @cindex @code{vec_load_lanes@var{m}@var{n}} instruction pattern | |
4944 | @item @samp{vec_load_lanes@var{m}@var{n}} | |
4945 | Perform an interleaved load of several vectors from memory operand 1 | |
4946 | into register operand 0. Both operands have mode @var{m}. The register | |
4947 | operand is viewed as holding consecutive vectors of mode @var{n}, | |
4948 | while the memory operand is a flat array that contains the same number | |
4949 | of elements. The operation is equivalent to: | |
4950 | ||
4951 | @smallexample | |
4952 | int c = GET_MODE_SIZE (@var{m}) / GET_MODE_SIZE (@var{n}); | |
4953 | for (j = 0; j < GET_MODE_NUNITS (@var{n}); j++) | |
4954 | for (i = 0; i < c; i++) | |
4955 | operand0[i][j] = operand1[j * c + i]; | |
4956 | @end smallexample | |
4957 | ||
4958 | For example, @samp{vec_load_lanestiv4hi} loads 8 16-bit values | |
4959 | from memory into a register of mode @samp{TI}@. The register | |
4960 | contains two consecutive vectors of mode @samp{V4HI}@. | |
4961 | ||
4962 | This pattern can only be used if: | |
4963 | @smallexample | |
4964 | TARGET_ARRAY_MODE_SUPPORTED_P (@var{n}, @var{c}) | |
4965 | @end smallexample | |
4966 | is true. GCC assumes that, if a target supports this kind of | |
4967 | instruction for some mode @var{n}, it also supports unaligned | |
4968 | loads for vectors of mode @var{n}. | |
4969 | ||
4970 | This pattern is not allowed to @code{FAIL}. | |
4971 | ||
4972 | @cindex @code{vec_mask_load_lanes@var{m}@var{n}} instruction pattern | |
4973 | @item @samp{vec_mask_load_lanes@var{m}@var{n}} | |
4974 | Like @samp{vec_load_lanes@var{m}@var{n}}, but takes an additional | |
4975 | mask operand (operand 2) that specifies which elements of the destination | |
4976 | vectors should be loaded. Other elements of the destination | |
4977 | vectors are set to zero. The operation is equivalent to: | |
4978 | ||
4979 | @smallexample | |
4980 | int c = GET_MODE_SIZE (@var{m}) / GET_MODE_SIZE (@var{n}); | |
4981 | for (j = 0; j < GET_MODE_NUNITS (@var{n}); j++) | |
4982 | if (operand2[j]) | |
4983 | for (i = 0; i < c; i++) | |
4984 | operand0[i][j] = operand1[j * c + i]; | |
4985 | else | |
4986 | for (i = 0; i < c; i++) | |
4987 | operand0[i][j] = 0; | |
4988 | @end smallexample | |
4989 | ||
4990 | This pattern is not allowed to @code{FAIL}. | |
4991 | ||
59d789b3 JZ |
4992 | @cindex @code{vec_mask_len_load_lanes@var{m}@var{n}} instruction pattern |
4993 | @item @samp{vec_mask_len_load_lanes@var{m}@var{n}} | |
4994 | Like @samp{vec_load_lanes@var{m}@var{n}}, but takes an additional | |
4995 | mask operand (operand 2), length operand (operand 3) as well as bias operand (operand 4) | |
4996 | that specifies which elements of the destination vectors should be loaded. | |
4997 | Other elements of the destination vectors are undefined. The operation is equivalent to: | |
4998 | ||
4999 | @smallexample | |
5000 | int c = GET_MODE_SIZE (@var{m}) / GET_MODE_SIZE (@var{n}); | |
5001 | for (j = 0; j < operand3 + operand4; j++) | |
5002 | if (operand2[j]) | |
5003 | for (i = 0; i < c; i++) | |
5004 | operand0[i][j] = operand1[j * c + i]; | |
5005 | @end smallexample | |
5006 | ||
5007 | This pattern is not allowed to @code{FAIL}. | |
5008 | ||
d77de738 ML |
5009 | @cindex @code{vec_store_lanes@var{m}@var{n}} instruction pattern |
5010 | @item @samp{vec_store_lanes@var{m}@var{n}} | |
5011 | Equivalent to @samp{vec_load_lanes@var{m}@var{n}}, with the memory | |
5012 | and register operands reversed. That is, the instruction is | |
5013 | equivalent to: | |
5014 | ||
5015 | @smallexample | |
5016 | int c = GET_MODE_SIZE (@var{m}) / GET_MODE_SIZE (@var{n}); | |
5017 | for (j = 0; j < GET_MODE_NUNITS (@var{n}); j++) | |
5018 | for (i = 0; i < c; i++) | |
5019 | operand0[j * c + i] = operand1[i][j]; | |
5020 | @end smallexample | |
5021 | ||
5022 | for a memory operand 0 and register operand 1. | |
5023 | ||
5024 | This pattern is not allowed to @code{FAIL}. | |
5025 | ||
5026 | @cindex @code{vec_mask_store_lanes@var{m}@var{n}} instruction pattern | |
5027 | @item @samp{vec_mask_store_lanes@var{m}@var{n}} | |
5028 | Like @samp{vec_store_lanes@var{m}@var{n}}, but takes an additional | |
5029 | mask operand (operand 2) that specifies which elements of the source | |
5030 | vectors should be stored. The operation is equivalent to: | |
5031 | ||
5032 | @smallexample | |
5033 | int c = GET_MODE_SIZE (@var{m}) / GET_MODE_SIZE (@var{n}); | |
5034 | for (j = 0; j < GET_MODE_NUNITS (@var{n}); j++) | |
5035 | if (operand2[j]) | |
5036 | for (i = 0; i < c; i++) | |
5037 | operand0[j * c + i] = operand1[i][j]; | |
5038 | @end smallexample | |
5039 | ||
5040 | This pattern is not allowed to @code{FAIL}. | |
5041 | ||
59d789b3 JZ |
5042 | @cindex @code{vec_mask_len_store_lanes@var{m}@var{n}} instruction pattern |
5043 | @item @samp{vec_mask_len_store_lanes@var{m}@var{n}} | |
5044 | Like @samp{vec_store_lanes@var{m}@var{n}}, but takes an additional | |
5045 | mask operand (operand 2), length operand (operand 3) as well as bias operand (operand 4) | |
5046 | that specifies which elements of the source vectors should be stored. | |
5047 | The operation is equivalent to: | |
5048 | ||
5049 | @smallexample | |
5050 | int c = GET_MODE_SIZE (@var{m}) / GET_MODE_SIZE (@var{n}); | |
5051 | for (j = 0; j < operand3 + operand4; j++) | |
5052 | if (operand2[j]) | |
5053 | for (i = 0; i < c; i++) | |
5054 | operand0[j * c + i] = operand1[i][j]; | |
5055 | @end smallexample | |
5056 | ||
5057 | This pattern is not allowed to @code{FAIL}. | |
5058 | ||
d77de738 ML |
5059 | @cindex @code{gather_load@var{m}@var{n}} instruction pattern |
5060 | @item @samp{gather_load@var{m}@var{n}} | |
5061 | Load several separate memory locations into a vector of mode @var{m}. | |
5062 | Operand 1 is a scalar base address and operand 2 is a vector of mode @var{n} | |
5063 | containing offsets from that base. Operand 0 is a destination vector with | |
5064 | the same number of elements as @var{n}. For each element index @var{i}: | |
5065 | ||
5066 | @itemize @bullet | |
5067 | @item | |
5068 | extend the offset element @var{i} to address width, using zero | |
5069 | extension if operand 3 is 1 and sign extension if operand 3 is zero; | |
5070 | @item | |
5071 | multiply the extended offset by operand 4; | |
5072 | @item | |
5073 | add the result to the base; and | |
5074 | @item | |
5075 | load the value at that address into element @var{i} of operand 0. | |
5076 | @end itemize | |
5077 | ||
5078 | The value of operand 3 does not matter if the offsets are already | |
5079 | address width. | |
5080 | ||
5081 | @cindex @code{mask_gather_load@var{m}@var{n}} instruction pattern | |
5082 | @item @samp{mask_gather_load@var{m}@var{n}} | |
5083 | Like @samp{gather_load@var{m}@var{n}}, but takes an extra mask operand as | |
5084 | operand 5. Bit @var{i} of the mask is set if element @var{i} | |
5085 | of the result should be loaded from memory and clear if element @var{i} | |
5086 | of the result should be set to zero. | |
5087 | ||
bd68b33f JZ |
5088 | @cindex @code{mask_len_gather_load@var{m}@var{n}} instruction pattern |
5089 | @item @samp{mask_len_gather_load@var{m}@var{n}} | |
363bb3dc JZ |
5090 | Like @samp{gather_load@var{m}@var{n}}, but takes an extra mask operand (operand 5), |
5091 | a len operand (operand 6) as well as a bias operand (operand 7). Similar to mask_len_load, | |
5092 | the instruction loads at most (operand 6 + operand 7) elements from memory. | |
db3efdaf JZZ |
5093 | Bit @var{i} of the mask is set if element @var{i} of the result should |
5094 | be loaded from memory and clear if element @var{i} of the result should be undefined. | |
363bb3dc | 5095 | Mask elements @var{i} with @var{i} > (operand 6 + operand 7) are ignored. |
db3efdaf | 5096 | |
d77de738 ML |
5097 | @cindex @code{scatter_store@var{m}@var{n}} instruction pattern |
5098 | @item @samp{scatter_store@var{m}@var{n}} | |
5099 | Store a vector of mode @var{m} into several distinct memory locations. | |
5100 | Operand 0 is a scalar base address and operand 1 is a vector of mode | |
5101 | @var{n} containing offsets from that base. Operand 4 is the vector of | |
5102 | values that should be stored, which has the same number of elements as | |
5103 | @var{n}. For each element index @var{i}: | |
5104 | ||
5105 | @itemize @bullet | |
5106 | @item | |
5107 | extend the offset element @var{i} to address width, using zero | |
5108 | extension if operand 2 is 1 and sign extension if operand 2 is zero; | |
5109 | @item | |
5110 | multiply the extended offset by operand 3; | |
5111 | @item | |
5112 | add the result to the base; and | |
5113 | @item | |
5114 | store element @var{i} of operand 4 to that address. | |
5115 | @end itemize | |
5116 | ||
5117 | The value of operand 2 does not matter if the offsets are already | |
5118 | address width. | |
5119 | ||
5120 | @cindex @code{mask_scatter_store@var{m}@var{n}} instruction pattern | |
5121 | @item @samp{mask_scatter_store@var{m}@var{n}} | |
5122 | Like @samp{scatter_store@var{m}@var{n}}, but takes an extra mask operand as | |
5123 | operand 5. Bit @var{i} of the mask is set if element @var{i} | |
5124 | of the result should be stored to memory. | |
5125 | ||
bd68b33f JZ |
5126 | @cindex @code{mask_len_scatter_store@var{m}@var{n}} instruction pattern |
5127 | @item @samp{mask_len_scatter_store@var{m}@var{n}} | |
363bb3dc JZ |
5128 | Like @samp{scatter_store@var{m}@var{n}}, but takes an extra mask operand (operand 5), |
5129 | a len operand (operand 6) as well as a bias operand (operand 7). The instruction stores | |
5130 | at most (operand 6 + operand 7) elements of (operand 4) to memory. | |
db3efdaf | 5131 | Bit @var{i} of the mask is set if element @var{i} of (operand 4) should be stored. |
363bb3dc | 5132 | Mask elements @var{i} with @var{i} > (operand 6 + operand 7) are ignored. |
db3efdaf | 5133 | |
d77de738 ML |
5134 | @cindex @code{vec_set@var{m}} instruction pattern |
5135 | @item @samp{vec_set@var{m}} | |
5136 | Set given field in the vector value. Operand 0 is the vector to modify, | |
5137 | operand 1 is new value of field and operand 2 specify the field index. | |
5138 | ||
c30efd8c RD |
5139 | This pattern is not allowed to @code{FAIL}. |
5140 | ||
d77de738 ML |
5141 | @cindex @code{vec_extract@var{m}@var{n}} instruction pattern |
5142 | @item @samp{vec_extract@var{m}@var{n}} | |
5143 | Extract given field from the vector value. Operand 1 is the vector, operand 2 | |
5144 | specify field index and operand 0 place to store value into. The | |
5145 | @var{n} mode is the mode of the field or vector of fields that should be | |
5146 | extracted, should be either element mode of the vector mode @var{m}, or | |
5147 | a vector mode with the same element mode and smaller number of elements. | |
c30efd8c RD |
5148 | If @var{n} is a vector mode the index is counted in multiples of |
5149 | mode @var{n}. | |
5150 | ||
5151 | This pattern is not allowed to @code{FAIL}. | |
d77de738 ML |
5152 | |
5153 | @cindex @code{vec_init@var{m}@var{n}} instruction pattern | |
5154 | @item @samp{vec_init@var{m}@var{n}} | |
5155 | Initialize the vector to given values. Operand 0 is the vector to initialize | |
5156 | and operand 1 is parallel containing values for individual fields. The | |
5157 | @var{n} mode is the mode of the elements, should be either element mode of | |
5158 | the vector mode @var{m}, or a vector mode with the same element mode and | |
5159 | smaller number of elements. | |
5160 | ||
5161 | @cindex @code{vec_duplicate@var{m}} instruction pattern | |
5162 | @item @samp{vec_duplicate@var{m}} | |
5163 | Initialize vector output operand 0 so that each element has the value given | |
5164 | by scalar input operand 1. The vector has mode @var{m} and the scalar has | |
5165 | the mode appropriate for one element of @var{m}. | |
5166 | ||
5167 | This pattern only handles duplicates of non-constant inputs. Constant | |
5168 | vectors go through the @code{mov@var{m}} pattern instead. | |
5169 | ||
5170 | This pattern is not allowed to @code{FAIL}. | |
5171 | ||
5172 | @cindex @code{vec_series@var{m}} instruction pattern | |
5173 | @item @samp{vec_series@var{m}} | |
5174 | Initialize vector output operand 0 so that element @var{i} is equal to | |
5175 | operand 1 plus @var{i} times operand 2. In other words, create a linear | |
5176 | series whose base value is operand 1 and whose step is operand 2. | |
5177 | ||
5178 | The vector output has mode @var{m} and the scalar inputs have the mode | |
5179 | appropriate for one element of @var{m}. This pattern is not used for | |
5180 | floating-point vectors, in order to avoid having to specify the | |
5181 | rounding behavior for @var{i} > 1. | |
5182 | ||
5183 | This pattern is not allowed to @code{FAIL}. | |
5184 | ||
5185 | @cindex @code{while_ult@var{m}@var{n}} instruction pattern | |
5186 | @item @code{while_ult@var{m}@var{n}} | |
5187 | Set operand 0 to a mask that is true while incrementing operand 1 | |
5188 | gives a value that is less than operand 2, for a vector length up to operand 3. | |
5189 | Operand 0 has mode @var{n} and operands 1 and 2 are scalar integers of mode | |
5190 | @var{m}. Operand 3 should be omitted when @var{n} is a vector mode, and | |
5191 | a @code{CONST_INT} otherwise. The operation for vector modes is equivalent to: | |
5192 | ||
5193 | @smallexample | |
5194 | operand0[0] = operand1 < operand2; | |
5195 | for (i = 1; i < GET_MODE_NUNITS (@var{n}); i++) | |
5196 | operand0[i] = operand0[i - 1] && (operand1 + i < operand2); | |
5197 | @end smallexample | |
5198 | ||
5199 | And for non-vector modes the operation is equivalent to: | |
5200 | ||
5201 | @smallexample | |
5202 | operand0[0] = operand1 < operand2; | |
5203 | for (i = 1; i < operand3; i++) | |
5204 | operand0[i] = operand0[i - 1] && (operand1 + i < operand2); | |
5205 | @end smallexample | |
5206 | ||
47203d89 JZZ |
5207 | @cindex @code{select_vl@var{m}} instruction pattern |
5208 | @item @code{select_vl@var{m}} | |
5209 | Set operand 0 to the number of scalar iterations that should be handled | |
5210 | by one iteration of a vector loop. Operand 1 is the total number of | |
5211 | scalar iterations that the loop needs to process and operand 2 is a | |
5212 | maximum bound on the result (also known as the maximum ``vectorization | |
5213 | factor''). | |
5214 | ||
5215 | The maximum value of operand 0 is given by: | |
5216 | @smallexample | |
5217 | operand0 = MIN (operand1, operand2) | |
5218 | @end smallexample | |
5219 | However, targets might choose a lower value than this, based on | |
5220 | target-specific criteria. Each iteration of the vector loop might | |
5221 | therefore process a different number of scalar iterations, which in turn | |
5222 | means that induction variables will have a variable step. Because of | |
5223 | this, it is generally not useful to define this instruction if it will | |
5224 | always calculate the maximum value. | |
5225 | ||
5226 | This optab is only useful on targets that implement @samp{len_load_@var{m}} | |
5227 | and/or @samp{len_store_@var{m}}. | |
5228 | ||
d77de738 ML |
5229 | @cindex @code{check_raw_ptrs@var{m}} instruction pattern |
5230 | @item @samp{check_raw_ptrs@var{m}} | |
5231 | Check whether, given two pointers @var{a} and @var{b} and a length @var{len}, | |
5232 | a write of @var{len} bytes at @var{a} followed by a read of @var{len} bytes | |
5233 | at @var{b} can be split into interleaved byte accesses | |
5234 | @samp{@var{a}[0], @var{b}[0], @var{a}[1], @var{b}[1], @dots{}} | |
5235 | without affecting the dependencies between the bytes. Set operand 0 | |
5236 | to true if the split is possible and false otherwise. | |
5237 | ||
5238 | Operands 1, 2 and 3 provide the values of @var{a}, @var{b} and @var{len} | |
5239 | respectively. Operand 4 is a constant integer that provides the known | |
5240 | common alignment of @var{a} and @var{b}. All inputs have mode @var{m}. | |
5241 | ||
5242 | This split is possible if: | |
5243 | ||
5244 | @smallexample | |
5245 | @var{a} == @var{b} || @var{a} + @var{len} <= @var{b} || @var{b} + @var{len} <= @var{a} | |
5246 | @end smallexample | |
5247 | ||
5248 | You should only define this pattern if the target has a way of accelerating | |
5249 | the test without having to do the individual comparisons. | |
5250 | ||
5251 | @cindex @code{check_war_ptrs@var{m}} instruction pattern | |
5252 | @item @samp{check_war_ptrs@var{m}} | |
5253 | Like @samp{check_raw_ptrs@var{m}}, but with the read and write swapped round. | |
5254 | The split is possible in this case if: | |
5255 | ||
5256 | @smallexample | |
5257 | @var{b} <= @var{a} || @var{a} + @var{len} <= @var{b} | |
5258 | @end smallexample | |
5259 | ||
5260 | @cindex @code{vec_cmp@var{m}@var{n}} instruction pattern | |
5261 | @item @samp{vec_cmp@var{m}@var{n}} | |
5262 | Output a vector comparison. Operand 0 of mode @var{n} is the destination for | |
5263 | predicate in operand 1 which is a signed vector comparison with operands of | |
5264 | mode @var{m} in operands 2 and 3. Predicate is computed by element-wise | |
5265 | evaluation of the vector comparison with a truth value of all-ones and a false | |
5266 | value of all-zeros. | |
5267 | ||
5268 | @cindex @code{vec_cmpu@var{m}@var{n}} instruction pattern | |
5269 | @item @samp{vec_cmpu@var{m}@var{n}} | |
5270 | Similar to @code{vec_cmp@var{m}@var{n}} but perform unsigned vector comparison. | |
5271 | ||
5272 | @cindex @code{vec_cmpeq@var{m}@var{n}} instruction pattern | |
5273 | @item @samp{vec_cmpeq@var{m}@var{n}} | |
5274 | Similar to @code{vec_cmp@var{m}@var{n}} but perform equality or non-equality | |
5275 | vector comparison only. If @code{vec_cmp@var{m}@var{n}} | |
5276 | or @code{vec_cmpu@var{m}@var{n}} instruction pattern is supported, | |
5277 | it will be preferred over @code{vec_cmpeq@var{m}@var{n}}, so there is | |
5278 | no need to define this instruction pattern if the others are supported. | |
5279 | ||
5280 | @cindex @code{vcond@var{m}@var{n}} instruction pattern | |
5281 | @item @samp{vcond@var{m}@var{n}} | |
5282 | Output a conditional vector move. Operand 0 is the destination to | |
5283 | receive a combination of operand 1 and operand 2, which are of mode @var{m}, | |
5284 | dependent on the outcome of the predicate in operand 3 which is a signed | |
5285 | vector comparison with operands of mode @var{n} in operands 4 and 5. The | |
5286 | modes @var{m} and @var{n} should have the same size. Operand 0 | |
5287 | will be set to the value @var{op1} & @var{msk} | @var{op2} & ~@var{msk} | |
5288 | where @var{msk} is computed by element-wise evaluation of the vector | |
5289 | comparison with a truth value of all-ones and a false value of all-zeros. | |
5290 | ||
5291 | @cindex @code{vcondu@var{m}@var{n}} instruction pattern | |
5292 | @item @samp{vcondu@var{m}@var{n}} | |
5293 | Similar to @code{vcond@var{m}@var{n}} but performs unsigned vector | |
5294 | comparison. | |
5295 | ||
5296 | @cindex @code{vcondeq@var{m}@var{n}} instruction pattern | |
5297 | @item @samp{vcondeq@var{m}@var{n}} | |
5298 | Similar to @code{vcond@var{m}@var{n}} but performs equality or | |
5299 | non-equality vector comparison only. If @code{vcond@var{m}@var{n}} | |
5300 | or @code{vcondu@var{m}@var{n}} instruction pattern is supported, | |
5301 | it will be preferred over @code{vcondeq@var{m}@var{n}}, so there is | |
5302 | no need to define this instruction pattern if the others are supported. | |
5303 | ||
5304 | @cindex @code{vcond_mask_@var{m}@var{n}} instruction pattern | |
5305 | @item @samp{vcond_mask_@var{m}@var{n}} | |
5306 | Similar to @code{vcond@var{m}@var{n}} but operand 3 holds a pre-computed | |
5307 | result of vector comparison. | |
5308 | ||
5309 | @cindex @code{maskload@var{m}@var{n}} instruction pattern | |
5310 | @item @samp{maskload@var{m}@var{n}} | |
5311 | Perform a masked load of vector from memory operand 1 of mode @var{m} | |
5312 | into register operand 0. Mask is provided in register operand 2 of | |
5313 | mode @var{n}. | |
5314 | ||
5315 | This pattern is not allowed to @code{FAIL}. | |
5316 | ||
5317 | @cindex @code{maskstore@var{m}@var{n}} instruction pattern | |
5318 | @item @samp{maskstore@var{m}@var{n}} | |
5319 | Perform a masked store of vector from register operand 1 of mode @var{m} | |
5320 | into memory operand 0. Mask is provided in register operand 2 of | |
5321 | mode @var{n}. | |
5322 | ||
5323 | This pattern is not allowed to @code{FAIL}. | |
5324 | ||
5325 | @cindex @code{len_load_@var{m}} instruction pattern | |
5326 | @item @samp{len_load_@var{m}} | |
ccfdda34 | 5327 | Load (operand 2 + operand 3) elements from memory operand 1 |
d77de738 ML |
5328 | into vector register operand 0, setting the other elements of |
5329 | operand 0 to undefined values. Operands 0 and 1 have mode @var{m}, | |
5330 | which must be a vector mode. Operand 2 has whichever integer mode the | |
5331 | target prefers. Operand 3 conceptually has mode @code{QI}. | |
5332 | ||
5333 | Operand 2 can be a variable or a constant amount. Operand 3 specifies a | |
5334 | constant bias: it is either a constant 0 or a constant -1. The predicate on | |
5335 | operand 3 must only accept the bias values that the target actually supports. | |
5336 | GCC handles a bias of 0 more efficiently than a bias of -1. | |
5337 | ||
ccfdda34 | 5338 | If (operand 2 + operand 3) exceeds the number of elements in mode |
d77de738 ML |
5339 | @var{m}, the behavior is undefined. |
5340 | ||
5341 | If the target prefers the length to be measured in bytes rather than | |
5342 | elements, it should only implement this pattern for vectors of @code{QI} | |
5343 | elements. | |
5344 | ||
5345 | This pattern is not allowed to @code{FAIL}. | |
5346 | ||
5347 | @cindex @code{len_store_@var{m}} instruction pattern | |
5348 | @item @samp{len_store_@var{m}} | |
ccfdda34 | 5349 | Store (operand 2 + operand 3) vector elements from vector register operand 1 |
d77de738 ML |
5350 | into memory operand 0, leaving the other elements of |
5351 | operand 0 unchanged. Operands 0 and 1 have mode @var{m}, which must be | |
5352 | a vector mode. Operand 2 has whichever integer mode the target prefers. | |
5353 | Operand 3 conceptually has mode @code{QI}. | |
5354 | ||
5355 | Operand 2 can be a variable or a constant amount. Operand 3 specifies a | |
5356 | constant bias: it is either a constant 0 or a constant -1. The predicate on | |
5357 | operand 3 must only accept the bias values that the target actually supports. | |
5358 | GCC handles a bias of 0 more efficiently than a bias of -1. | |
5359 | ||
ccfdda34 JZZ |
5360 | If (operand 2 + operand 3) exceeds the number of elements in mode |
5361 | @var{m}, the behavior is undefined. | |
5362 | ||
5363 | If the target prefers the length to be measured in bytes | |
5364 | rather than elements, it should only implement this pattern for vectors | |
5365 | of @code{QI} elements. | |
5366 | ||
5367 | This pattern is not allowed to @code{FAIL}. | |
5368 | ||
bd68b33f JZ |
5369 | @cindex @code{mask_len_load@var{m}@var{n}} instruction pattern |
5370 | @item @samp{mask_len_load@var{m}@var{n}} | |
ccfdda34 | 5371 | Perform a masked load from the memory location pointed to by operand 1 |
363bb3dc | 5372 | into register operand 0. (operand 3 + operand 4) elements are loaded from |
ccfdda34 JZZ |
5373 | memory and other elements in operand 0 are set to undefined values. |
5374 | This is a combination of len_load and maskload. | |
363bb3dc | 5375 | Operands 0 and 1 have mode @var{m}, which must be a vector mode. Operand 3 |
ccfdda34 | 5376 | has whichever integer mode the target prefers. A mask is specified in |
363bb3dc | 5377 | operand 2 which must be of type @var{n}. The mask has lower precedence than |
ccfdda34 | 5378 | the length and is itself subject to length masking, |
363bb3dc JZ |
5379 | i.e. only mask indices < (operand 3 + operand 4) are used. |
5380 | Operand 4 conceptually has mode @code{QI}. | |
ccfdda34 JZZ |
5381 | |
5382 | Operand 2 can be a variable or a constant amount. Operand 4 specifies a | |
5383 | constant bias: it is either a constant 0 or a constant -1. The predicate on | |
5384 | operand 4 must only accept the bias values that the target actually supports. | |
5385 | GCC handles a bias of 0 more efficiently than a bias of -1. | |
5386 | ||
5387 | If (operand 2 + operand 4) exceeds the number of elements in mode | |
5388 | @var{m}, the behavior is undefined. | |
5389 | ||
5390 | If the target prefers the length to be measured in bytes | |
5391 | rather than elements, it should only implement this pattern for vectors | |
5392 | of @code{QI} elements. | |
5393 | ||
5394 | This pattern is not allowed to @code{FAIL}. | |
5395 | ||
bd68b33f JZ |
5396 | @cindex @code{mask_len_store@var{m}@var{n}} instruction pattern |
5397 | @item @samp{mask_len_store@var{m}@var{n}} | |
ccfdda34 | 5398 | Perform a masked store from vector register operand 1 into memory operand 0. |
363bb3dc | 5399 | (operand 3 + operand 4) elements are stored to memory |
ccfdda34 JZZ |
5400 | and leave the other elements of operand 0 unchanged. |
5401 | This is a combination of len_store and maskstore. | |
363bb3dc JZ |
5402 | Operands 0 and 1 have mode @var{m}, which must be a vector mode. Operand 3 has whichever |
5403 | integer mode the target prefers. A mask is specified in operand 2 which must be | |
ccfdda34 | 5404 | of type @var{n}. The mask has lower precedence than the length and is itself subject to |
363bb3dc JZ |
5405 | length masking, i.e. only mask indices < (operand 3 + operand 4) are used. |
5406 | Operand 4 conceptually has mode @code{QI}. | |
ccfdda34 JZZ |
5407 | |
5408 | Operand 2 can be a variable or a constant amount. Operand 3 specifies a | |
5409 | constant bias: it is either a constant 0 or a constant -1. The predicate on | |
5410 | operand 4 must only accept the bias values that the target actually supports. | |
5411 | GCC handles a bias of 0 more efficiently than a bias of -1. | |
5412 | ||
5413 | If (operand 2 + operand 4) exceeds the number of elements in mode | |
d77de738 ML |
5414 | @var{m}, the behavior is undefined. |
5415 | ||
5416 | If the target prefers the length to be measured in bytes | |
5417 | rather than elements, it should only implement this pattern for vectors | |
5418 | of @code{QI} elements. | |
5419 | ||
5420 | This pattern is not allowed to @code{FAIL}. | |
5421 | ||
5422 | @cindex @code{vec_perm@var{m}} instruction pattern | |
5423 | @item @samp{vec_perm@var{m}} | |
5424 | Output a (variable) vector permutation. Operand 0 is the destination | |
5425 | to receive elements from operand 1 and operand 2, which are of mode | |
5426 | @var{m}. Operand 3 is the @dfn{selector}. It is an integral mode | |
5427 | vector of the same width and number of elements as mode @var{m}. | |
5428 | ||
5429 | The input elements are numbered from 0 in operand 1 through | |
5430 | @math{2*@var{N}-1} in operand 2. The elements of the selector must | |
5431 | be computed modulo @math{2*@var{N}}. Note that if | |
5432 | @code{rtx_equal_p(operand1, operand2)}, this can be implemented | |
5433 | with just operand 1 and selector elements modulo @var{N}. | |
5434 | ||
5435 | In order to make things easy for a number of targets, if there is no | |
5436 | @samp{vec_perm} pattern for mode @var{m}, but there is for mode @var{q} | |
5437 | where @var{q} is a vector of @code{QImode} of the same width as @var{m}, | |
5438 | the middle-end will lower the mode @var{m} @code{VEC_PERM_EXPR} to | |
5439 | mode @var{q}. | |
5440 | ||
5441 | See also @code{TARGET_VECTORIZER_VEC_PERM_CONST}, which performs | |
5442 | the analogous operation for constant selectors. | |
5443 | ||
5444 | @cindex @code{push@var{m}1} instruction pattern | |
5445 | @item @samp{push@var{m}1} | |
5446 | Output a push instruction. Operand 0 is value to push. Used only when | |
5447 | @code{PUSH_ROUNDING} is defined. For historical reason, this pattern may be | |
5448 | missing and in such case an @code{mov} expander is used instead, with a | |
5449 | @code{MEM} expression forming the push operation. The @code{mov} expander | |
5450 | method is deprecated. | |
5451 | ||
5452 | @cindex @code{add@var{m}3} instruction pattern | |
5453 | @item @samp{add@var{m}3} | |
5454 | Add operand 2 and operand 1, storing the result in operand 0. All operands | |
5455 | must have mode @var{m}. This can be used even on two-address machines, by | |
5456 | means of constraints requiring operands 1 and 0 to be the same location. | |
5457 | ||
5458 | @cindex @code{ssadd@var{m}3} instruction pattern | |
5459 | @cindex @code{usadd@var{m}3} instruction pattern | |
5460 | @cindex @code{sub@var{m}3} instruction pattern | |
5461 | @cindex @code{sssub@var{m}3} instruction pattern | |
5462 | @cindex @code{ussub@var{m}3} instruction pattern | |
5463 | @cindex @code{mul@var{m}3} instruction pattern | |
5464 | @cindex @code{ssmul@var{m}3} instruction pattern | |
5465 | @cindex @code{usmul@var{m}3} instruction pattern | |
5466 | @cindex @code{div@var{m}3} instruction pattern | |
5467 | @cindex @code{ssdiv@var{m}3} instruction pattern | |
5468 | @cindex @code{udiv@var{m}3} instruction pattern | |
5469 | @cindex @code{usdiv@var{m}3} instruction pattern | |
5470 | @cindex @code{mod@var{m}3} instruction pattern | |
5471 | @cindex @code{umod@var{m}3} instruction pattern | |
5472 | @cindex @code{umin@var{m}3} instruction pattern | |
5473 | @cindex @code{umax@var{m}3} instruction pattern | |
5474 | @cindex @code{and@var{m}3} instruction pattern | |
5475 | @cindex @code{ior@var{m}3} instruction pattern | |
5476 | @cindex @code{xor@var{m}3} instruction pattern | |
5477 | @item @samp{ssadd@var{m}3}, @samp{usadd@var{m}3} | |
5478 | @itemx @samp{sub@var{m}3}, @samp{sssub@var{m}3}, @samp{ussub@var{m}3} | |
5479 | @itemx @samp{mul@var{m}3}, @samp{ssmul@var{m}3}, @samp{usmul@var{m}3} | |
5480 | @itemx @samp{div@var{m}3}, @samp{ssdiv@var{m}3} | |
5481 | @itemx @samp{udiv@var{m}3}, @samp{usdiv@var{m}3} | |
5482 | @itemx @samp{mod@var{m}3}, @samp{umod@var{m}3} | |
5483 | @itemx @samp{umin@var{m}3}, @samp{umax@var{m}3} | |
5484 | @itemx @samp{and@var{m}3}, @samp{ior@var{m}3}, @samp{xor@var{m}3} | |
5485 | Similar, for other arithmetic operations. | |
5486 | ||
5487 | @cindex @code{addv@var{m}4} instruction pattern | |
5488 | @item @samp{addv@var{m}4} | |
5489 | Like @code{add@var{m}3} but takes a @code{code_label} as operand 3 and | |
5490 | emits code to jump to it if signed overflow occurs during the addition. | |
5491 | This pattern is used to implement the built-in functions performing | |
5492 | signed integer addition with overflow checking. | |
5493 | ||
5494 | @cindex @code{subv@var{m}4} instruction pattern | |
5495 | @cindex @code{mulv@var{m}4} instruction pattern | |
5496 | @item @samp{subv@var{m}4}, @samp{mulv@var{m}4} | |
5497 | Similar, for other signed arithmetic operations. | |
5498 | ||
5499 | @cindex @code{uaddv@var{m}4} instruction pattern | |
5500 | @item @samp{uaddv@var{m}4} | |
5501 | Like @code{addv@var{m}4} but for unsigned addition. That is to | |
5502 | say, the operation is the same as signed addition but the jump | |
5503 | is taken only on unsigned overflow. | |
5504 | ||
5505 | @cindex @code{usubv@var{m}4} instruction pattern | |
5506 | @cindex @code{umulv@var{m}4} instruction pattern | |
5507 | @item @samp{usubv@var{m}4}, @samp{umulv@var{m}4} | |
5508 | Similar, for other unsigned arithmetic operations. | |
5509 | ||
43a3252c JJ |
5510 | @cindex @code{uaddc@var{m}5} instruction pattern |
5511 | @item @samp{uaddc@var{m}5} | |
5512 | Adds unsigned operands 2, 3 and 4 (where the last operand is guaranteed to | |
5513 | have only values 0 or 1) together, sets operand 0 to the result of the | |
5514 | addition of the 3 operands and sets operand 1 to 1 iff there was | |
5515 | overflow on the unsigned additions, and to 0 otherwise. So, it is | |
5516 | an addition with carry in (operand 4) and carry out (operand 1). | |
5517 | All operands have the same mode. | |
5518 | ||
5519 | @cindex @code{usubc@var{m}5} instruction pattern | |
5520 | @item @samp{usubc@var{m}5} | |
5521 | Similarly to @samp{uaddc@var{m}5}, except subtracts unsigned operands 3 | |
5522 | and 4 from operand 2 instead of adding them. So, it is | |
5523 | a subtraction with carry/borrow in (operand 4) and carry/borrow out | |
5524 | (operand 1). All operands have the same mode. | |
5525 | ||
d77de738 ML |
5526 | @cindex @code{addptr@var{m}3} instruction pattern |
5527 | @item @samp{addptr@var{m}3} | |
5528 | Like @code{add@var{m}3} but is guaranteed to only be used for address | |
5529 | calculations. The expanded code is not allowed to clobber the | |
5530 | condition code. It only needs to be defined if @code{add@var{m}3} | |
5531 | sets the condition code. If adds used for address calculations and | |
5532 | normal adds are not compatible it is required to expand a distinct | |
5533 | pattern (e.g.@: using an unspec). The pattern is used by LRA to emit | |
5534 | address calculations. @code{add@var{m}3} is used if | |
5535 | @code{addptr@var{m}3} is not defined. | |
5536 | ||
5537 | @cindex @code{fma@var{m}4} instruction pattern | |
5538 | @item @samp{fma@var{m}4} | |
5539 | Multiply operand 2 and operand 1, then add operand 3, storing the | |
5540 | result in operand 0 without doing an intermediate rounding step. All | |
5541 | operands must have mode @var{m}. This pattern is used to implement | |
5542 | the @code{fma}, @code{fmaf}, and @code{fmal} builtin functions from | |
5543 | the ISO C99 standard. | |
5544 | ||
5545 | @cindex @code{fms@var{m}4} instruction pattern | |
5546 | @item @samp{fms@var{m}4} | |
5547 | Like @code{fma@var{m}4}, except operand 3 subtracted from the | |
5548 | product instead of added to the product. This is represented | |
5549 | in the rtl as | |
5550 | ||
5551 | @smallexample | |
5552 | (fma:@var{m} @var{op1} @var{op2} (neg:@var{m} @var{op3})) | |
5553 | @end smallexample | |
5554 | ||
5555 | @cindex @code{fnma@var{m}4} instruction pattern | |
5556 | @item @samp{fnma@var{m}4} | |
5557 | Like @code{fma@var{m}4} except that the intermediate product | |
5558 | is negated before being added to operand 3. This is represented | |
5559 | in the rtl as | |
5560 | ||
5561 | @smallexample | |
5562 | (fma:@var{m} (neg:@var{m} @var{op1}) @var{op2} @var{op3}) | |
5563 | @end smallexample | |
5564 | ||
5565 | @cindex @code{fnms@var{m}4} instruction pattern | |
5566 | @item @samp{fnms@var{m}4} | |
5567 | Like @code{fms@var{m}4} except that the intermediate product | |
5568 | is negated before subtracting operand 3. This is represented | |
5569 | in the rtl as | |
5570 | ||
5571 | @smallexample | |
5572 | (fma:@var{m} (neg:@var{m} @var{op1}) @var{op2} (neg:@var{m} @var{op3})) | |
5573 | @end smallexample | |
5574 | ||
5575 | @cindex @code{min@var{m}3} instruction pattern | |
5576 | @cindex @code{max@var{m}3} instruction pattern | |
5577 | @item @samp{smin@var{m}3}, @samp{smax@var{m}3} | |
5578 | Signed minimum and maximum operations. When used with floating point, | |
5579 | if both operands are zeros, or if either operand is @code{NaN}, then | |
5580 | it is unspecified which of the two operands is returned as the result. | |
5581 | ||
5582 | @cindex @code{fmin@var{m}3} instruction pattern | |
5583 | @cindex @code{fmax@var{m}3} instruction pattern | |
5584 | @item @samp{fmin@var{m}3}, @samp{fmax@var{m}3} | |
5585 | IEEE-conformant minimum and maximum operations. If one operand is a quiet | |
5586 | @code{NaN}, then the other operand is returned. If both operands are quiet | |
5587 | @code{NaN}, then a quiet @code{NaN} is returned. In the case when gcc supports | |
5588 | signaling @code{NaN} (-fsignaling-nans) an invalid floating point exception is | |
5589 | raised and a quiet @code{NaN} is returned. | |
5590 | ||
5591 | All operands have mode @var{m}, which is a scalar or vector | |
5592 | floating-point mode. These patterns are not allowed to @code{FAIL}. | |
5593 | ||
5594 | @cindex @code{reduc_smin_scal_@var{m}} instruction pattern | |
5595 | @cindex @code{reduc_smax_scal_@var{m}} instruction pattern | |
5596 | @item @samp{reduc_smin_scal_@var{m}}, @samp{reduc_smax_scal_@var{m}} | |
5597 | Find the signed minimum/maximum of the elements of a vector. The vector is | |
5598 | operand 1, and operand 0 is the scalar result, with mode equal to the mode of | |
5599 | the elements of the input vector. | |
5600 | ||
5601 | @cindex @code{reduc_umin_scal_@var{m}} instruction pattern | |
5602 | @cindex @code{reduc_umax_scal_@var{m}} instruction pattern | |
5603 | @item @samp{reduc_umin_scal_@var{m}}, @samp{reduc_umax_scal_@var{m}} | |
5604 | Find the unsigned minimum/maximum of the elements of a vector. The vector is | |
5605 | operand 1, and operand 0 is the scalar result, with mode equal to the mode of | |
5606 | the elements of the input vector. | |
5607 | ||
5608 | @cindex @code{reduc_fmin_scal_@var{m}} instruction pattern | |
5609 | @cindex @code{reduc_fmax_scal_@var{m}} instruction pattern | |
5610 | @item @samp{reduc_fmin_scal_@var{m}}, @samp{reduc_fmax_scal_@var{m}} | |
5611 | Find the floating-point minimum/maximum of the elements of a vector, | |
5612 | using the same rules as @code{fmin@var{m}3} and @code{fmax@var{m}3}. | |
5613 | Operand 1 is a vector of mode @var{m} and operand 0 is the scalar | |
5614 | result, which has mode @code{GET_MODE_INNER (@var{m})}. | |
5615 | ||
5616 | @cindex @code{reduc_plus_scal_@var{m}} instruction pattern | |
5617 | @item @samp{reduc_plus_scal_@var{m}} | |
5618 | Compute the sum of the elements of a vector. The vector is operand 1, and | |
5619 | operand 0 is the scalar result, with mode equal to the mode of the elements of | |
5620 | the input vector. | |
5621 | ||
5622 | @cindex @code{reduc_and_scal_@var{m}} instruction pattern | |
d77de738 | 5623 | @cindex @code{reduc_ior_scal_@var{m}} instruction pattern |
d77de738 | 5624 | @cindex @code{reduc_xor_scal_@var{m}} instruction pattern |
f33d7a88 AA |
5625 | @item @samp{reduc_and_scal_@var{m}} |
5626 | @itemx @samp{reduc_ior_scal_@var{m}} | |
d77de738 ML |
5627 | @itemx @samp{reduc_xor_scal_@var{m}} |
5628 | Compute the bitwise @code{AND}/@code{IOR}/@code{XOR} reduction of the elements | |
5629 | of a vector of mode @var{m}. Operand 1 is the vector input and operand 0 | |
5630 | is the scalar result. The mode of the scalar result is the same as one | |
5631 | element of @var{m}. | |
5632 | ||
5633 | @cindex @code{extract_last_@var{m}} instruction pattern | |
5634 | @item @code{extract_last_@var{m}} | |
5635 | Find the last set bit in mask operand 1 and extract the associated element | |
5636 | of vector operand 2. Store the result in scalar operand 0. Operand 2 | |
5637 | has vector mode @var{m} while operand 0 has the mode appropriate for one | |
5638 | element of @var{m}. Operand 1 has the usual mask mode for vectors of mode | |
5639 | @var{m}; see @code{TARGET_VECTORIZE_GET_MASK_MODE}. | |
5640 | ||
5641 | @cindex @code{fold_extract_last_@var{m}} instruction pattern | |
5642 | @item @code{fold_extract_last_@var{m}} | |
5643 | If any bits of mask operand 2 are set, find the last set bit, extract | |
5644 | the associated element from vector operand 3, and store the result | |
5645 | in operand 0. Store operand 1 in operand 0 otherwise. Operand 3 | |
5646 | has mode @var{m} and operands 0 and 1 have the mode appropriate for | |
5647 | one element of @var{m}. Operand 2 has the usual mask mode for vectors | |
5648 | of mode @var{m}; see @code{TARGET_VECTORIZE_GET_MASK_MODE}. | |
5649 | ||
f4658e02 JZ |
5650 | @cindex @code{len_fold_extract_last_@var{m}} instruction pattern |
5651 | @item @code{len_fold_extract_last_@var{m}} | |
5652 | Like @samp{fold_extract_last_@var{m}}, but takes an extra length operand as | |
5653 | operand 4 and an extra bias operand as operand 5. The last associated element | |
5654 | is extracted should have the index i < len (operand 4) + bias (operand 5). | |
5655 | ||
d77de738 ML |
5656 | @cindex @code{fold_left_plus_@var{m}} instruction pattern |
5657 | @item @code{fold_left_plus_@var{m}} | |
5658 | Take scalar operand 1 and successively add each element from vector | |
5659 | operand 2. Store the result in scalar operand 0. The vector has | |
5660 | mode @var{m} and the scalars have the mode appropriate for one | |
5661 | element of @var{m}. The operation is strictly in-order: there is | |
5662 | no reassociation. | |
5663 | ||
5664 | @cindex @code{mask_fold_left_plus_@var{m}} instruction pattern | |
5665 | @item @code{mask_fold_left_plus_@var{m}} | |
5666 | Like @samp{fold_left_plus_@var{m}}, but takes an additional mask operand | |
5667 | (operand 3) that specifies which elements of the source vector should be added. | |
5668 | ||
ba49332b JZZ |
5669 | @cindex @code{mask_len_fold_left_plus_@var{m}} instruction pattern |
5670 | @item @code{mask_len_fold_left_plus_@var{m}} | |
5671 | Like @samp{fold_left_plus_@var{m}}, but takes an additional mask operand | |
5672 | (operand 3), len operand (operand 4) and bias operand (operand 5) that | |
5673 | performs following operations strictly in-order (no reassociation): | |
5674 | ||
5675 | @smallexample | |
5676 | operand0 = operand1; | |
5677 | for (i = 0; i < LEN + BIAS; i++) | |
5678 | if (operand3[i]) | |
5679 | operand0 += operand2[i]; | |
5680 | @end smallexample | |
5681 | ||
d77de738 ML |
5682 | @cindex @code{sdot_prod@var{m}} instruction pattern |
5683 | @item @samp{sdot_prod@var{m}} | |
5684 | ||
5685 | Compute the sum of the products of two signed elements. | |
5686 | Operand 1 and operand 2 are of the same mode. Their | |
5687 | product, which is of a wider mode, is computed and added to operand 3. | |
5688 | Operand 3 is of a mode equal or wider than the mode of the product. The | |
5689 | result is placed in operand 0, which is of the same mode as operand 3. | |
5690 | ||
5691 | Semantically the expressions perform the multiplication in the following signs | |
5692 | ||
5693 | @smallexample | |
5694 | sdot<signed op0, signed op1, signed op2, signed op3> == | |
5695 | op0 = sign-ext (op1) * sign-ext (op2) + op3 | |
5696 | @dots{} | |
5697 | @end smallexample | |
5698 | ||
5699 | @cindex @code{udot_prod@var{m}} instruction pattern | |
5700 | @item @samp{udot_prod@var{m}} | |
5701 | ||
5702 | Compute the sum of the products of two unsigned elements. | |
5703 | Operand 1 and operand 2 are of the same mode. Their | |
5704 | product, which is of a wider mode, is computed and added to operand 3. | |
5705 | Operand 3 is of a mode equal or wider than the mode of the product. The | |
5706 | result is placed in operand 0, which is of the same mode as operand 3. | |
5707 | ||
5708 | Semantically the expressions perform the multiplication in the following signs | |
5709 | ||
5710 | @smallexample | |
5711 | udot<unsigned op0, unsigned op1, unsigned op2, unsigned op3> == | |
5712 | op0 = zero-ext (op1) * zero-ext (op2) + op3 | |
5713 | @dots{} | |
5714 | @end smallexample | |
5715 | ||
5716 | @cindex @code{usdot_prod@var{m}} instruction pattern | |
5717 | @item @samp{usdot_prod@var{m}} | |
5718 | Compute the sum of the products of elements of different signs. | |
5719 | Operand 1 must be unsigned and operand 2 signed. Their | |
5720 | product, which is of a wider mode, is computed and added to operand 3. | |
5721 | Operand 3 is of a mode equal or wider than the mode of the product. The | |
5722 | result is placed in operand 0, which is of the same mode as operand 3. | |
5723 | ||
5724 | Semantically the expressions perform the multiplication in the following signs | |
5725 | ||
5726 | @smallexample | |
5727 | usdot<signed op0, unsigned op1, signed op2, signed op3> == | |
5728 | op0 = ((signed-conv) zero-ext (op1)) * sign-ext (op2) + op3 | |
5729 | @dots{} | |
5730 | @end smallexample | |
5731 | ||
5732 | @cindex @code{ssad@var{m}} instruction pattern | |
d77de738 | 5733 | @cindex @code{usad@var{m}} instruction pattern |
f33d7a88 | 5734 | @item @samp{ssad@var{m}} |
d77de738 ML |
5735 | @item @samp{usad@var{m}} |
5736 | Compute the sum of absolute differences of two signed/unsigned elements. | |
5737 | Operand 1 and operand 2 are of the same mode. Their absolute difference, which | |
5738 | is of a wider mode, is computed and added to operand 3. Operand 3 is of a mode | |
5739 | equal or wider than the mode of the absolute difference. The result is placed | |
5740 | in operand 0, which is of the same mode as operand 3. | |
5741 | ||
5742 | @cindex @code{widen_ssum@var{m3}} instruction pattern | |
d77de738 | 5743 | @cindex @code{widen_usum@var{m3}} instruction pattern |
f33d7a88 | 5744 | @item @samp{widen_ssum@var{m3}} |
d77de738 ML |
5745 | @itemx @samp{widen_usum@var{m3}} |
5746 | Operands 0 and 2 are of the same mode, which is wider than the mode of | |
5747 | operand 1. Add operand 1 to operand 2 and place the widened result in | |
5748 | operand 0. (This is used express accumulation of elements into an accumulator | |
5749 | of a wider mode.) | |
5750 | ||
5751 | @cindex @code{smulhs@var{m3}} instruction pattern | |
d77de738 | 5752 | @cindex @code{umulhs@var{m3}} instruction pattern |
f33d7a88 | 5753 | @item @samp{smulhs@var{m3}} |
d77de738 ML |
5754 | @itemx @samp{umulhs@var{m3}} |
5755 | Signed/unsigned multiply high with scale. This is equivalent to the C code: | |
5756 | @smallexample | |
5757 | narrow op0, op1, op2; | |
5758 | @dots{} | |
5759 | op0 = (narrow) (((wide) op1 * (wide) op2) >> (N / 2 - 1)); | |
5760 | @end smallexample | |
5761 | where the sign of @samp{narrow} determines whether this is a signed | |
5762 | or unsigned operation, and @var{N} is the size of @samp{wide} in bits. | |
5763 | ||
5764 | @cindex @code{smulhrs@var{m3}} instruction pattern | |
d77de738 | 5765 | @cindex @code{umulhrs@var{m3}} instruction pattern |
f33d7a88 | 5766 | @item @samp{smulhrs@var{m3}} |
d77de738 ML |
5767 | @itemx @samp{umulhrs@var{m3}} |
5768 | Signed/unsigned multiply high with round and scale. This is | |
5769 | equivalent to the C code: | |
5770 | @smallexample | |
5771 | narrow op0, op1, op2; | |
5772 | @dots{} | |
5773 | op0 = (narrow) (((((wide) op1 * (wide) op2) >> (N / 2 - 2)) + 1) >> 1); | |
5774 | @end smallexample | |
5775 | where the sign of @samp{narrow} determines whether this is a signed | |
5776 | or unsigned operation, and @var{N} is the size of @samp{wide} in bits. | |
5777 | ||
5778 | @cindex @code{sdiv_pow2@var{m3}} instruction pattern | |
d77de738 | 5779 | @cindex @code{sdiv_pow2@var{m3}} instruction pattern |
f33d7a88 | 5780 | @item @samp{sdiv_pow2@var{m3}} |
d77de738 ML |
5781 | @itemx @samp{sdiv_pow2@var{m3}} |
5782 | Signed division by power-of-2 immediate. Equivalent to: | |
5783 | @smallexample | |
5784 | signed op0, op1; | |
5785 | @dots{} | |
5786 | op0 = op1 / (1 << imm); | |
5787 | @end smallexample | |
5788 | ||
5789 | @cindex @code{vec_shl_insert_@var{m}} instruction pattern | |
5790 | @item @samp{vec_shl_insert_@var{m}} | |
5791 | Shift the elements in vector input operand 1 left one element (i.e.@: | |
5792 | away from element 0) and fill the vacated element 0 with the scalar | |
5793 | in operand 2. Store the result in vector output operand 0. Operands | |
5794 | 0 and 1 have mode @var{m} and operand 2 has the mode appropriate for | |
5795 | one element of @var{m}. | |
5796 | ||
5797 | @cindex @code{vec_shl_@var{m}} instruction pattern | |
5798 | @item @samp{vec_shl_@var{m}} | |
5799 | Whole vector left shift in bits, i.e.@: away from element 0. | |
5800 | Operand 1 is a vector to be shifted. | |
5801 | Operand 2 is an integer shift amount in bits. | |
5802 | Operand 0 is where the resulting shifted vector is stored. | |
5803 | The output and input vectors should have the same modes. | |
5804 | ||
5805 | @cindex @code{vec_shr_@var{m}} instruction pattern | |
5806 | @item @samp{vec_shr_@var{m}} | |
5807 | Whole vector right shift in bits, i.e.@: towards element 0. | |
5808 | Operand 1 is a vector to be shifted. | |
5809 | Operand 2 is an integer shift amount in bits. | |
5810 | Operand 0 is where the resulting shifted vector is stored. | |
5811 | The output and input vectors should have the same modes. | |
5812 | ||
5813 | @cindex @code{vec_pack_trunc_@var{m}} instruction pattern | |
5814 | @item @samp{vec_pack_trunc_@var{m}} | |
5815 | Narrow (demote) and merge the elements of two vectors. Operands 1 and 2 | |
5816 | are vectors of the same mode having N integral or floating point elements | |
5817 | of size S@. Operand 0 is the resulting vector in which 2*N elements of | |
5818 | size S/2 are concatenated after narrowing them down using truncation. | |
5819 | ||
5820 | @cindex @code{vec_pack_sbool_trunc_@var{m}} instruction pattern | |
5821 | @item @samp{vec_pack_sbool_trunc_@var{m}} | |
5822 | Narrow and merge the elements of two vectors. Operands 1 and 2 are vectors | |
5823 | of the same type having N boolean elements. Operand 0 is the resulting | |
5824 | vector in which 2*N elements are concatenated. The last operand (operand 3) | |
5825 | is the number of elements in the output vector 2*N as a @code{CONST_INT}. | |
5826 | This instruction pattern is used when all the vector input and output | |
5827 | operands have the same scalar mode @var{m} and thus using | |
5828 | @code{vec_pack_trunc_@var{m}} would be ambiguous. | |
5829 | ||
5830 | @cindex @code{vec_pack_ssat_@var{m}} instruction pattern | |
5831 | @cindex @code{vec_pack_usat_@var{m}} instruction pattern | |
5832 | @item @samp{vec_pack_ssat_@var{m}}, @samp{vec_pack_usat_@var{m}} | |
5833 | Narrow (demote) and merge the elements of two vectors. Operands 1 and 2 | |
5834 | are vectors of the same mode having N integral elements of size S. | |
5835 | Operand 0 is the resulting vector in which the elements of the two input | |
5836 | vectors are concatenated after narrowing them down using signed/unsigned | |
5837 | saturating arithmetic. | |
5838 | ||
5839 | @cindex @code{vec_pack_sfix_trunc_@var{m}} instruction pattern | |
5840 | @cindex @code{vec_pack_ufix_trunc_@var{m}} instruction pattern | |
5841 | @item @samp{vec_pack_sfix_trunc_@var{m}}, @samp{vec_pack_ufix_trunc_@var{m}} | |
5842 | Narrow, convert to signed/unsigned integral type and merge the elements | |
5843 | of two vectors. Operands 1 and 2 are vectors of the same mode having N | |
5844 | floating point elements of size S@. Operand 0 is the resulting vector | |
5845 | in which 2*N elements of size S/2 are concatenated. | |
5846 | ||
5847 | @cindex @code{vec_packs_float_@var{m}} instruction pattern | |
5848 | @cindex @code{vec_packu_float_@var{m}} instruction pattern | |
5849 | @item @samp{vec_packs_float_@var{m}}, @samp{vec_packu_float_@var{m}} | |
5850 | Narrow, convert to floating point type and merge the elements | |
5851 | of two vectors. Operands 1 and 2 are vectors of the same mode having N | |
5852 | signed/unsigned integral elements of size S@. Operand 0 is the resulting vector | |
5853 | in which 2*N elements of size S/2 are concatenated. | |
5854 | ||
5855 | @cindex @code{vec_unpacks_hi_@var{m}} instruction pattern | |
5856 | @cindex @code{vec_unpacks_lo_@var{m}} instruction pattern | |
5857 | @item @samp{vec_unpacks_hi_@var{m}}, @samp{vec_unpacks_lo_@var{m}} | |
5858 | Extract and widen (promote) the high/low part of a vector of signed | |
5859 | integral or floating point elements. The input vector (operand 1) has N | |
5860 | elements of size S@. Widen (promote) the high/low elements of the vector | |
5861 | using signed or floating point extension and place the resulting N/2 | |
5862 | values of size 2*S in the output vector (operand 0). | |
5863 | ||
5864 | @cindex @code{vec_unpacku_hi_@var{m}} instruction pattern | |
5865 | @cindex @code{vec_unpacku_lo_@var{m}} instruction pattern | |
5866 | @item @samp{vec_unpacku_hi_@var{m}}, @samp{vec_unpacku_lo_@var{m}} | |
5867 | Extract and widen (promote) the high/low part of a vector of unsigned | |
5868 | integral elements. The input vector (operand 1) has N elements of size S. | |
5869 | Widen (promote) the high/low elements of the vector using zero extension and | |
5870 | place the resulting N/2 values of size 2*S in the output vector (operand 0). | |
5871 | ||
5872 | @cindex @code{vec_unpacks_sbool_hi_@var{m}} instruction pattern | |
5873 | @cindex @code{vec_unpacks_sbool_lo_@var{m}} instruction pattern | |
5874 | @item @samp{vec_unpacks_sbool_hi_@var{m}}, @samp{vec_unpacks_sbool_lo_@var{m}} | |
5875 | Extract the high/low part of a vector of boolean elements that have scalar | |
5876 | mode @var{m}. The input vector (operand 1) has N elements, the output | |
5877 | vector (operand 0) has N/2 elements. The last operand (operand 2) is the | |
5878 | number of elements of the input vector N as a @code{CONST_INT}. These | |
5879 | patterns are used if both the input and output vectors have the same scalar | |
5880 | mode @var{m} and thus using @code{vec_unpacks_hi_@var{m}} or | |
5881 | @code{vec_unpacks_lo_@var{m}} would be ambiguous. | |
5882 | ||
5883 | @cindex @code{vec_unpacks_float_hi_@var{m}} instruction pattern | |
5884 | @cindex @code{vec_unpacks_float_lo_@var{m}} instruction pattern | |
5885 | @cindex @code{vec_unpacku_float_hi_@var{m}} instruction pattern | |
5886 | @cindex @code{vec_unpacku_float_lo_@var{m}} instruction pattern | |
5887 | @item @samp{vec_unpacks_float_hi_@var{m}}, @samp{vec_unpacks_float_lo_@var{m}} | |
5888 | @itemx @samp{vec_unpacku_float_hi_@var{m}}, @samp{vec_unpacku_float_lo_@var{m}} | |
5889 | Extract, convert to floating point type and widen the high/low part of a | |
5890 | vector of signed/unsigned integral elements. The input vector (operand 1) | |
5891 | has N elements of size S@. Convert the high/low elements of the vector using | |
5892 | floating point conversion and place the resulting N/2 values of size 2*S in | |
5893 | the output vector (operand 0). | |
5894 | ||
5895 | @cindex @code{vec_unpack_sfix_trunc_hi_@var{m}} instruction pattern | |
5896 | @cindex @code{vec_unpack_sfix_trunc_lo_@var{m}} instruction pattern | |
5897 | @cindex @code{vec_unpack_ufix_trunc_hi_@var{m}} instruction pattern | |
5898 | @cindex @code{vec_unpack_ufix_trunc_lo_@var{m}} instruction pattern | |
5899 | @item @samp{vec_unpack_sfix_trunc_hi_@var{m}}, | |
5900 | @itemx @samp{vec_unpack_sfix_trunc_lo_@var{m}} | |
5901 | @itemx @samp{vec_unpack_ufix_trunc_hi_@var{m}} | |
5902 | @itemx @samp{vec_unpack_ufix_trunc_lo_@var{m}} | |
5903 | Extract, convert to signed/unsigned integer type and widen the high/low part of a | |
5904 | vector of floating point elements. The input vector (operand 1) | |
5905 | has N elements of size S@. Convert the high/low elements of the vector | |
5906 | to integers and place the resulting N/2 values of size 2*S in | |
5907 | the output vector (operand 0). | |
5908 | ||
5909 | @cindex @code{vec_widen_umult_hi_@var{m}} instruction pattern | |
5910 | @cindex @code{vec_widen_umult_lo_@var{m}} instruction pattern | |
5911 | @cindex @code{vec_widen_smult_hi_@var{m}} instruction pattern | |
5912 | @cindex @code{vec_widen_smult_lo_@var{m}} instruction pattern | |
5913 | @cindex @code{vec_widen_umult_even_@var{m}} instruction pattern | |
5914 | @cindex @code{vec_widen_umult_odd_@var{m}} instruction pattern | |
5915 | @cindex @code{vec_widen_smult_even_@var{m}} instruction pattern | |
5916 | @cindex @code{vec_widen_smult_odd_@var{m}} instruction pattern | |
5917 | @item @samp{vec_widen_umult_hi_@var{m}}, @samp{vec_widen_umult_lo_@var{m}} | |
5918 | @itemx @samp{vec_widen_smult_hi_@var{m}}, @samp{vec_widen_smult_lo_@var{m}} | |
5919 | @itemx @samp{vec_widen_umult_even_@var{m}}, @samp{vec_widen_umult_odd_@var{m}} | |
5920 | @itemx @samp{vec_widen_smult_even_@var{m}}, @samp{vec_widen_smult_odd_@var{m}} | |
5921 | Signed/Unsigned widening multiplication. The two inputs (operands 1 and 2) | |
5922 | are vectors with N signed/unsigned elements of size S@. Multiply the high/low | |
5923 | or even/odd elements of the two vectors, and put the N/2 products of size 2*S | |
5924 | in the output vector (operand 0). A target shouldn't implement even/odd pattern | |
5925 | pair if it is less efficient than lo/hi one. | |
5926 | ||
5927 | @cindex @code{vec_widen_ushiftl_hi_@var{m}} instruction pattern | |
5928 | @cindex @code{vec_widen_ushiftl_lo_@var{m}} instruction pattern | |
5929 | @cindex @code{vec_widen_sshiftl_hi_@var{m}} instruction pattern | |
5930 | @cindex @code{vec_widen_sshiftl_lo_@var{m}} instruction pattern | |
5931 | @item @samp{vec_widen_ushiftl_hi_@var{m}}, @samp{vec_widen_ushiftl_lo_@var{m}} | |
5932 | @itemx @samp{vec_widen_sshiftl_hi_@var{m}}, @samp{vec_widen_sshiftl_lo_@var{m}} | |
5933 | Signed/Unsigned widening shift left. The first input (operand 1) is a vector | |
5934 | with N signed/unsigned elements of size S@. Operand 2 is a constant. Shift | |
5935 | the high/low elements of operand 1, and put the N/2 results of size 2*S in the | |
5936 | output vector (operand 0). | |
5937 | ||
5938 | @cindex @code{vec_widen_saddl_hi_@var{m}} instruction pattern | |
5939 | @cindex @code{vec_widen_saddl_lo_@var{m}} instruction pattern | |
5940 | @cindex @code{vec_widen_uaddl_hi_@var{m}} instruction pattern | |
5941 | @cindex @code{vec_widen_uaddl_lo_@var{m}} instruction pattern | |
5942 | @item @samp{vec_widen_uaddl_hi_@var{m}}, @samp{vec_widen_uaddl_lo_@var{m}} | |
5943 | @itemx @samp{vec_widen_saddl_hi_@var{m}}, @samp{vec_widen_saddl_lo_@var{m}} | |
5944 | Signed/Unsigned widening add long. Operands 1 and 2 are vectors with N | |
5945 | signed/unsigned elements of size S@. Add the high/low elements of 1 and 2 | |
5946 | together, widen the resulting elements and put the N/2 results of size 2*S in | |
5947 | the output vector (operand 0). | |
5948 | ||
5949 | @cindex @code{vec_widen_ssubl_hi_@var{m}} instruction pattern | |
5950 | @cindex @code{vec_widen_ssubl_lo_@var{m}} instruction pattern | |
5951 | @cindex @code{vec_widen_usubl_hi_@var{m}} instruction pattern | |
5952 | @cindex @code{vec_widen_usubl_lo_@var{m}} instruction pattern | |
5953 | @item @samp{vec_widen_usubl_hi_@var{m}}, @samp{vec_widen_usubl_lo_@var{m}} | |
5954 | @itemx @samp{vec_widen_ssubl_hi_@var{m}}, @samp{vec_widen_ssubl_lo_@var{m}} | |
5955 | Signed/Unsigned widening subtract long. Operands 1 and 2 are vectors with N | |
5956 | signed/unsigned elements of size S@. Subtract the high/low elements of 2 from | |
5957 | 1 and widen the resulting elements. Put the N/2 results of size 2*S in the | |
5958 | output vector (operand 0). | |
5959 | ||
aec90c8b OA |
5960 | @cindex @code{vec_widen_sabd_hi_@var{m}} instruction pattern |
5961 | @cindex @code{vec_widen_sabd_lo_@var{m}} instruction pattern | |
5962 | @cindex @code{vec_widen_sabd_odd_@var{m}} instruction pattern | |
5963 | @cindex @code{vec_widen_sabd_even_@var{m}} instruction pattern | |
5964 | @cindex @code{vec_widen_uabd_hi_@var{m}} instruction pattern | |
5965 | @cindex @code{vec_widen_uabd_lo_@var{m}} instruction pattern | |
5966 | @cindex @code{vec_widen_uabd_odd_@var{m}} instruction pattern | |
5967 | @cindex @code{vec_widen_uabd_even_@var{m}} instruction pattern | |
5968 | @item @samp{vec_widen_uabd_hi_@var{m}}, @samp{vec_widen_uabd_lo_@var{m}} | |
5969 | @itemx @samp{vec_widen_uabd_odd_@var{m}}, @samp{vec_widen_uabd_even_@var{m}} | |
5970 | @itemx @samp{vec_widen_sabd_hi_@var{m}}, @samp{vec_widen_sabd_lo_@var{m}} | |
5971 | @itemx @samp{vec_widen_sabd_odd_@var{m}}, @samp{vec_widen_sabd_even_@var{m}} | |
5972 | Signed/Unsigned widening absolute difference. Operands 1 and 2 are | |
5973 | vectors with N signed/unsigned elements of size S@. Find the absolute | |
5974 | difference between operands 1 and 2 and widen the resulting elements. | |
5975 | Put the N/2 results of size 2*S in the output vector (operand 0). | |
5976 | ||
d77de738 ML |
5977 | @cindex @code{vec_addsub@var{m}3} instruction pattern |
5978 | @item @samp{vec_addsub@var{m}3} | |
5979 | Alternating subtract, add with even lanes doing subtract and odd | |
5980 | lanes doing addition. Operands 1 and 2 and the outout operand are vectors | |
5981 | with mode @var{m}. | |
5982 | ||
5983 | @cindex @code{vec_fmaddsub@var{m}4} instruction pattern | |
5984 | @item @samp{vec_fmaddsub@var{m}4} | |
5985 | Alternating multiply subtract, add with even lanes doing subtract and odd | |
5986 | lanes doing addition of the third operand to the multiplication result | |
5987 | of the first two operands. Operands 1, 2 and 3 and the outout operand are vectors | |
5988 | with mode @var{m}. | |
5989 | ||
5990 | @cindex @code{vec_fmsubadd@var{m}4} instruction pattern | |
5991 | @item @samp{vec_fmsubadd@var{m}4} | |
5992 | Alternating multiply add, subtract with even lanes doing addition and odd | |
5993 | lanes doing subtraction of the third operand to the multiplication result | |
5994 | of the first two operands. Operands 1, 2 and 3 and the outout operand are vectors | |
5995 | with mode @var{m}. | |
5996 | ||
5997 | These instructions are not allowed to @code{FAIL}. | |
5998 | ||
5999 | @cindex @code{mulhisi3} instruction pattern | |
6000 | @item @samp{mulhisi3} | |
6001 | Multiply operands 1 and 2, which have mode @code{HImode}, and store | |
6002 | a @code{SImode} product in operand 0. | |
6003 | ||
6004 | @cindex @code{mulqihi3} instruction pattern | |
6005 | @cindex @code{mulsidi3} instruction pattern | |
6006 | @item @samp{mulqihi3}, @samp{mulsidi3} | |
6007 | Similar widening-multiplication instructions of other widths. | |
6008 | ||
6009 | @cindex @code{umulqihi3} instruction pattern | |
6010 | @cindex @code{umulhisi3} instruction pattern | |
6011 | @cindex @code{umulsidi3} instruction pattern | |
6012 | @item @samp{umulqihi3}, @samp{umulhisi3}, @samp{umulsidi3} | |
6013 | Similar widening-multiplication instructions that do unsigned | |
6014 | multiplication. | |
6015 | ||
6016 | @cindex @code{usmulqihi3} instruction pattern | |
6017 | @cindex @code{usmulhisi3} instruction pattern | |
6018 | @cindex @code{usmulsidi3} instruction pattern | |
6019 | @item @samp{usmulqihi3}, @samp{usmulhisi3}, @samp{usmulsidi3} | |
6020 | Similar widening-multiplication instructions that interpret the first | |
6021 | operand as unsigned and the second operand as signed, then do a signed | |
6022 | multiplication. | |
6023 | ||
6024 | @cindex @code{smul@var{m}3_highpart} instruction pattern | |
6025 | @item @samp{smul@var{m}3_highpart} | |
6026 | Perform a signed multiplication of operands 1 and 2, which have mode | |
6027 | @var{m}, and store the most significant half of the product in operand 0. | |
6028 | The least significant half of the product is discarded. This may be | |
6029 | represented in RTL using a @code{smul_highpart} RTX expression. | |
6030 | ||
6031 | @cindex @code{umul@var{m}3_highpart} instruction pattern | |
6032 | @item @samp{umul@var{m}3_highpart} | |
6033 | Similar, but the multiplication is unsigned. This may be represented | |
6034 | in RTL using an @code{umul_highpart} RTX expression. | |
6035 | ||
6036 | @cindex @code{madd@var{m}@var{n}4} instruction pattern | |
6037 | @item @samp{madd@var{m}@var{n}4} | |
6038 | Multiply operands 1 and 2, sign-extend them to mode @var{n}, add | |
6039 | operand 3, and store the result in operand 0. Operands 1 and 2 | |
6040 | have mode @var{m} and operands 0 and 3 have mode @var{n}. | |
6041 | Both modes must be integer or fixed-point modes and @var{n} must be twice | |
6042 | the size of @var{m}. | |
6043 | ||
6044 | In other words, @code{madd@var{m}@var{n}4} is like | |
6045 | @code{mul@var{m}@var{n}3} except that it also adds operand 3. | |
6046 | ||
6047 | These instructions are not allowed to @code{FAIL}. | |
6048 | ||
6049 | @cindex @code{umadd@var{m}@var{n}4} instruction pattern | |
6050 | @item @samp{umadd@var{m}@var{n}4} | |
6051 | Like @code{madd@var{m}@var{n}4}, but zero-extend the multiplication | |
6052 | operands instead of sign-extending them. | |
6053 | ||
6054 | @cindex @code{ssmadd@var{m}@var{n}4} instruction pattern | |
6055 | @item @samp{ssmadd@var{m}@var{n}4} | |
6056 | Like @code{madd@var{m}@var{n}4}, but all involved operations must be | |
6057 | signed-saturating. | |
6058 | ||
6059 | @cindex @code{usmadd@var{m}@var{n}4} instruction pattern | |
6060 | @item @samp{usmadd@var{m}@var{n}4} | |
6061 | Like @code{umadd@var{m}@var{n}4}, but all involved operations must be | |
6062 | unsigned-saturating. | |
6063 | ||
6064 | @cindex @code{msub@var{m}@var{n}4} instruction pattern | |
6065 | @item @samp{msub@var{m}@var{n}4} | |
6066 | Multiply operands 1 and 2, sign-extend them to mode @var{n}, subtract the | |
6067 | result from operand 3, and store the result in operand 0. Operands 1 and 2 | |
6068 | have mode @var{m} and operands 0 and 3 have mode @var{n}. | |
6069 | Both modes must be integer or fixed-point modes and @var{n} must be twice | |
6070 | the size of @var{m}. | |
6071 | ||
6072 | In other words, @code{msub@var{m}@var{n}4} is like | |
6073 | @code{mul@var{m}@var{n}3} except that it also subtracts the result | |
6074 | from operand 3. | |
6075 | ||
6076 | These instructions are not allowed to @code{FAIL}. | |
6077 | ||
6078 | @cindex @code{umsub@var{m}@var{n}4} instruction pattern | |
6079 | @item @samp{umsub@var{m}@var{n}4} | |
6080 | Like @code{msub@var{m}@var{n}4}, but zero-extend the multiplication | |
6081 | operands instead of sign-extending them. | |
6082 | ||
6083 | @cindex @code{ssmsub@var{m}@var{n}4} instruction pattern | |
6084 | @item @samp{ssmsub@var{m}@var{n}4} | |
6085 | Like @code{msub@var{m}@var{n}4}, but all involved operations must be | |
6086 | signed-saturating. | |
6087 | ||
6088 | @cindex @code{usmsub@var{m}@var{n}4} instruction pattern | |
6089 | @item @samp{usmsub@var{m}@var{n}4} | |
6090 | Like @code{umsub@var{m}@var{n}4}, but all involved operations must be | |
6091 | unsigned-saturating. | |
6092 | ||
6093 | @cindex @code{divmod@var{m}4} instruction pattern | |
6094 | @item @samp{divmod@var{m}4} | |
6095 | Signed division that produces both a quotient and a remainder. | |
6096 | Operand 1 is divided by operand 2 to produce a quotient stored | |
6097 | in operand 0 and a remainder stored in operand 3. | |
6098 | ||
6099 | For machines with an instruction that produces both a quotient and a | |
6100 | remainder, provide a pattern for @samp{divmod@var{m}4} but do not | |
6101 | provide patterns for @samp{div@var{m}3} and @samp{mod@var{m}3}. This | |
6102 | allows optimization in the relatively common case when both the quotient | |
6103 | and remainder are computed. | |
6104 | ||
6105 | If an instruction that just produces a quotient or just a remainder | |
6106 | exists and is more efficient than the instruction that produces both, | |
6107 | write the output routine of @samp{divmod@var{m}4} to call | |
6108 | @code{find_reg_note} and look for a @code{REG_UNUSED} note on the | |
6109 | quotient or remainder and generate the appropriate instruction. | |
6110 | ||
6111 | @cindex @code{udivmod@var{m}4} instruction pattern | |
6112 | @item @samp{udivmod@var{m}4} | |
6113 | Similar, but does unsigned division. | |
6114 | ||
6115 | @anchor{shift patterns} | |
6116 | @cindex @code{ashl@var{m}3} instruction pattern | |
6117 | @cindex @code{ssashl@var{m}3} instruction pattern | |
6118 | @cindex @code{usashl@var{m}3} instruction pattern | |
6119 | @item @samp{ashl@var{m}3}, @samp{ssashl@var{m}3}, @samp{usashl@var{m}3} | |
6120 | Arithmetic-shift operand 1 left by a number of bits specified by operand | |
6121 | 2, and store the result in operand 0. Here @var{m} is the mode of | |
6122 | operand 0 and operand 1; operand 2's mode is specified by the | |
6123 | instruction pattern, and the compiler will convert the operand to that | |
6124 | mode before generating the instruction. The shift or rotate expander | |
6125 | or instruction pattern should explicitly specify the mode of the operand 2, | |
6126 | it should never be @code{VOIDmode}. The meaning of out-of-range shift | |
6127 | counts can optionally be specified by @code{TARGET_SHIFT_TRUNCATION_MASK}. | |
6128 | @xref{TARGET_SHIFT_TRUNCATION_MASK}. Operand 2 is always a scalar type. | |
6129 | ||
6130 | @cindex @code{ashr@var{m}3} instruction pattern | |
6131 | @cindex @code{lshr@var{m}3} instruction pattern | |
6132 | @cindex @code{rotl@var{m}3} instruction pattern | |
6133 | @cindex @code{rotr@var{m}3} instruction pattern | |
6134 | @item @samp{ashr@var{m}3}, @samp{lshr@var{m}3}, @samp{rotl@var{m}3}, @samp{rotr@var{m}3} | |
6135 | Other shift and rotate instructions, analogous to the | |
6136 | @code{ashl@var{m}3} instructions. Operand 2 is always a scalar type. | |
6137 | ||
6138 | @cindex @code{vashl@var{m}3} instruction pattern | |
6139 | @cindex @code{vashr@var{m}3} instruction pattern | |
6140 | @cindex @code{vlshr@var{m}3} instruction pattern | |
6141 | @cindex @code{vrotl@var{m}3} instruction pattern | |
6142 | @cindex @code{vrotr@var{m}3} instruction pattern | |
6143 | @item @samp{vashl@var{m}3}, @samp{vashr@var{m}3}, @samp{vlshr@var{m}3}, @samp{vrotl@var{m}3}, @samp{vrotr@var{m}3} | |
6144 | Vector shift and rotate instructions that take vectors as operand 2 | |
6145 | instead of a scalar type. | |
6146 | ||
710b8dec OA |
6147 | @cindex @code{uabd@var{m}} instruction pattern |
6148 | @cindex @code{sabd@var{m}} instruction pattern | |
6149 | @item @samp{uabd@var{m}}, @samp{sabd@var{m}} | |
6150 | Signed and unsigned absolute difference instructions. These | |
6151 | instructions find the difference between operands 1 and 2 | |
6152 | then return the absolute value. A C code equivalent would be: | |
6153 | @smallexample | |
6154 | op0 = op1 > op2 ? op1 - op2 : op2 - op1; | |
6155 | @end smallexample | |
6156 | ||
d77de738 ML |
6157 | @cindex @code{avg@var{m}3_floor} instruction pattern |
6158 | @cindex @code{uavg@var{m}3_floor} instruction pattern | |
6159 | @item @samp{avg@var{m}3_floor} | |
6160 | @itemx @samp{uavg@var{m}3_floor} | |
6161 | Signed and unsigned average instructions. These instructions add | |
6162 | operands 1 and 2 without truncation, divide the result by 2, | |
6163 | round towards -Inf, and store the result in operand 0. This is | |
6164 | equivalent to the C code: | |
6165 | @smallexample | |
6166 | narrow op0, op1, op2; | |
6167 | @dots{} | |
6168 | op0 = (narrow) (((wide) op1 + (wide) op2) >> 1); | |
6169 | @end smallexample | |
6170 | where the sign of @samp{narrow} determines whether this is a signed | |
6171 | or unsigned operation. | |
6172 | ||
6173 | @cindex @code{avg@var{m}3_ceil} instruction pattern | |
6174 | @cindex @code{uavg@var{m}3_ceil} instruction pattern | |
6175 | @item @samp{avg@var{m}3_ceil} | |
6176 | @itemx @samp{uavg@var{m}3_ceil} | |
6177 | Like @samp{avg@var{m}3_floor} and @samp{uavg@var{m}3_floor}, but round | |
6178 | towards +Inf. This is equivalent to the C code: | |
6179 | @smallexample | |
6180 | narrow op0, op1, op2; | |
6181 | @dots{} | |
6182 | op0 = (narrow) (((wide) op1 + (wide) op2 + 1) >> 1); | |
6183 | @end smallexample | |
6184 | ||
6185 | @cindex @code{bswap@var{m}2} instruction pattern | |
6186 | @item @samp{bswap@var{m}2} | |
6187 | Reverse the order of bytes of operand 1 and store the result in operand 0. | |
6188 | ||
6189 | @cindex @code{neg@var{m}2} instruction pattern | |
6190 | @cindex @code{ssneg@var{m}2} instruction pattern | |
6191 | @cindex @code{usneg@var{m}2} instruction pattern | |
6192 | @item @samp{neg@var{m}2}, @samp{ssneg@var{m}2}, @samp{usneg@var{m}2} | |
6193 | Negate operand 1 and store the result in operand 0. | |
6194 | ||
6195 | @cindex @code{negv@var{m}3} instruction pattern | |
6196 | @item @samp{negv@var{m}3} | |
6197 | Like @code{neg@var{m}2} but takes a @code{code_label} as operand 2 and | |
6198 | emits code to jump to it if signed overflow occurs during the negation. | |
6199 | ||
6200 | @cindex @code{abs@var{m}2} instruction pattern | |
6201 | @item @samp{abs@var{m}2} | |
6202 | Store the absolute value of operand 1 into operand 0. | |
6203 | ||
6204 | @cindex @code{sqrt@var{m}2} instruction pattern | |
6205 | @item @samp{sqrt@var{m}2} | |
6206 | Store the square root of operand 1 into operand 0. Both operands have | |
6207 | mode @var{m}, which is a scalar or vector floating-point mode. | |
6208 | ||
6209 | This pattern is not allowed to @code{FAIL}. | |
6210 | ||
6211 | @cindex @code{rsqrt@var{m}2} instruction pattern | |
6212 | @item @samp{rsqrt@var{m}2} | |
6213 | Store the reciprocal of the square root of operand 1 into operand 0. | |
6214 | Both operands have mode @var{m}, which is a scalar or vector | |
6215 | floating-point mode. | |
6216 | ||
6217 | On most architectures this pattern is only approximate, so either | |
6218 | its C condition or the @code{TARGET_OPTAB_SUPPORTED_P} hook should | |
6219 | check for the appropriate math flags. (Using the C condition is | |
6220 | more direct, but using @code{TARGET_OPTAB_SUPPORTED_P} can be useful | |
6221 | if a target-specific built-in also uses the @samp{rsqrt@var{m}2} | |
6222 | pattern.) | |
6223 | ||
6224 | This pattern is not allowed to @code{FAIL}. | |
6225 | ||
6226 | @cindex @code{fmod@var{m}3} instruction pattern | |
6227 | @item @samp{fmod@var{m}3} | |
6228 | Store the remainder of dividing operand 1 by operand 2 into | |
6229 | operand 0, rounded towards zero to an integer. All operands have | |
6230 | mode @var{m}, which is a scalar or vector floating-point mode. | |
6231 | ||
6232 | This pattern is not allowed to @code{FAIL}. | |
6233 | ||
6234 | @cindex @code{remainder@var{m}3} instruction pattern | |
6235 | @item @samp{remainder@var{m}3} | |
6236 | Store the remainder of dividing operand 1 by operand 2 into | |
6237 | operand 0, rounded to the nearest integer. All operands have | |
6238 | mode @var{m}, which is a scalar or vector floating-point mode. | |
6239 | ||
6240 | This pattern is not allowed to @code{FAIL}. | |
6241 | ||
6242 | @cindex @code{scalb@var{m}3} instruction pattern | |
6243 | @item @samp{scalb@var{m}3} | |
6244 | Raise @code{FLT_RADIX} to the power of operand 2, multiply it by | |
6245 | operand 1, and store the result in operand 0. All operands have | |
6246 | mode @var{m}, which is a scalar or vector floating-point mode. | |
6247 | ||
6248 | This pattern is not allowed to @code{FAIL}. | |
6249 | ||
6250 | @cindex @code{ldexp@var{m}3} instruction pattern | |
6251 | @item @samp{ldexp@var{m}3} | |
6252 | Raise 2 to the power of operand 2, multiply it by operand 1, and store | |
6253 | the result in operand 0. Operands 0 and 1 have mode @var{m}, which is | |
6254 | a scalar or vector floating-point mode. Operand 2's mode has | |
6255 | the same number of elements as @var{m} and each element is wide | |
6256 | enough to store an @code{int}. The integers are signed. | |
6257 | ||
6258 | This pattern is not allowed to @code{FAIL}. | |
6259 | ||
6260 | @cindex @code{cos@var{m}2} instruction pattern | |
6261 | @item @samp{cos@var{m}2} | |
6262 | Store the cosine of operand 1 into operand 0. Both operands have | |
6263 | mode @var{m}, which is a scalar or vector floating-point mode. | |
6264 | ||
6265 | This pattern is not allowed to @code{FAIL}. | |
6266 | ||
6267 | @cindex @code{sin@var{m}2} instruction pattern | |
6268 | @item @samp{sin@var{m}2} | |
6269 | Store the sine of operand 1 into operand 0. Both operands have | |
6270 | mode @var{m}, which is a scalar or vector floating-point mode. | |
6271 | ||
6272 | This pattern is not allowed to @code{FAIL}. | |
6273 | ||
6274 | @cindex @code{sincos@var{m}3} instruction pattern | |
6275 | @item @samp{sincos@var{m}3} | |
6276 | Store the cosine of operand 2 into operand 0 and the sine of | |
6277 | operand 2 into operand 1. All operands have mode @var{m}, | |
6278 | which is a scalar or vector floating-point mode. | |
6279 | ||
6280 | Targets that can calculate the sine and cosine simultaneously can | |
6281 | implement this pattern as opposed to implementing individual | |
6282 | @code{sin@var{m}2} and @code{cos@var{m}2} patterns. The @code{sin} | |
6283 | and @code{cos} built-in functions will then be expanded to the | |
6284 | @code{sincos@var{m}3} pattern, with one of the output values | |
6285 | left unused. | |
6286 | ||
6287 | @cindex @code{tan@var{m}2} instruction pattern | |
6288 | @item @samp{tan@var{m}2} | |
6289 | Store the tangent of operand 1 into operand 0. Both operands have | |
6290 | mode @var{m}, which is a scalar or vector floating-point mode. | |
6291 | ||
6292 | This pattern is not allowed to @code{FAIL}. | |
6293 | ||
6294 | @cindex @code{asin@var{m}2} instruction pattern | |
6295 | @item @samp{asin@var{m}2} | |
6296 | Store the arc sine of operand 1 into operand 0. Both operands have | |
6297 | mode @var{m}, which is a scalar or vector floating-point mode. | |
6298 | ||
6299 | This pattern is not allowed to @code{FAIL}. | |
6300 | ||
6301 | @cindex @code{acos@var{m}2} instruction pattern | |
6302 | @item @samp{acos@var{m}2} | |
6303 | Store the arc cosine of operand 1 into operand 0. Both operands have | |
6304 | mode @var{m}, which is a scalar or vector floating-point mode. | |
6305 | ||
6306 | This pattern is not allowed to @code{FAIL}. | |
6307 | ||
6308 | @cindex @code{atan@var{m}2} instruction pattern | |
6309 | @item @samp{atan@var{m}2} | |
6310 | Store the arc tangent of operand 1 into operand 0. Both operands have | |
6311 | mode @var{m}, which is a scalar or vector floating-point mode. | |
6312 | ||
6313 | This pattern is not allowed to @code{FAIL}. | |
6314 | ||
6315 | @cindex @code{fegetround@var{m}} instruction pattern | |
6316 | @item @samp{fegetround@var{m}} | |
6317 | Store the current machine floating-point rounding mode into operand 0. | |
6318 | Operand 0 has mode @var{m}, which is scalar. This pattern is used to | |
6319 | implement the @code{fegetround} function from the ISO C99 standard. | |
6320 | ||
6321 | @cindex @code{feclearexcept@var{m}} instruction pattern | |
6322 | @cindex @code{feraiseexcept@var{m}} instruction pattern | |
6323 | @item @samp{feclearexcept@var{m}} | |
6324 | @item @samp{feraiseexcept@var{m}} | |
6325 | Clears or raises the supported machine floating-point exceptions | |
6326 | represented by the bits in operand 1. Error status is stored as | |
6327 | nonzero value in operand 0. Both operands have mode @var{m}, which is | |
6328 | a scalar. These patterns are used to implement the | |
6329 | @code{feclearexcept} and @code{feraiseexcept} functions from the ISO | |
6330 | C99 standard. | |
6331 | ||
6332 | @cindex @code{exp@var{m}2} instruction pattern | |
6333 | @item @samp{exp@var{m}2} | |
6334 | Raise e (the base of natural logarithms) to the power of operand 1 | |
6335 | and store the result in operand 0. Both operands have mode @var{m}, | |
6336 | which is a scalar or vector floating-point mode. | |
6337 | ||
6338 | This pattern is not allowed to @code{FAIL}. | |
6339 | ||
6340 | @cindex @code{expm1@var{m}2} instruction pattern | |
6341 | @item @samp{expm1@var{m}2} | |
6342 | Raise e (the base of natural logarithms) to the power of operand 1, | |
6343 | subtract 1, and store the result in operand 0. Both operands have | |
6344 | mode @var{m}, which is a scalar or vector floating-point mode. | |
6345 | ||
6346 | For inputs close to zero, the pattern is expected to be more | |
6347 | accurate than a separate @code{exp@var{m}2} and @code{sub@var{m}3} | |
6348 | would be. | |
6349 | ||
6350 | This pattern is not allowed to @code{FAIL}. | |
6351 | ||
6352 | @cindex @code{exp10@var{m}2} instruction pattern | |
6353 | @item @samp{exp10@var{m}2} | |
6354 | Raise 10 to the power of operand 1 and store the result in operand 0. | |
6355 | Both operands have mode @var{m}, which is a scalar or vector | |
6356 | floating-point mode. | |
6357 | ||
6358 | This pattern is not allowed to @code{FAIL}. | |
6359 | ||
6360 | @cindex @code{exp2@var{m}2} instruction pattern | |
6361 | @item @samp{exp2@var{m}2} | |
6362 | Raise 2 to the power of operand 1 and store the result in operand 0. | |
6363 | Both operands have mode @var{m}, which is a scalar or vector | |
6364 | floating-point mode. | |
6365 | ||
6366 | This pattern is not allowed to @code{FAIL}. | |
6367 | ||
6368 | @cindex @code{log@var{m}2} instruction pattern | |
6369 | @item @samp{log@var{m}2} | |
6370 | Store the natural logarithm of operand 1 into operand 0. Both operands | |
6371 | have mode @var{m}, which is a scalar or vector floating-point mode. | |
6372 | ||
6373 | This pattern is not allowed to @code{FAIL}. | |
6374 | ||
6375 | @cindex @code{log1p@var{m}2} instruction pattern | |
6376 | @item @samp{log1p@var{m}2} | |
6377 | Add 1 to operand 1, compute the natural logarithm, and store | |
6378 | the result in operand 0. Both operands have mode @var{m}, which is | |
6379 | a scalar or vector floating-point mode. | |
6380 | ||
6381 | For inputs close to zero, the pattern is expected to be more | |
6382 | accurate than a separate @code{add@var{m}3} and @code{log@var{m}2} | |
6383 | would be. | |
6384 | ||
6385 | This pattern is not allowed to @code{FAIL}. | |
6386 | ||
6387 | @cindex @code{log10@var{m}2} instruction pattern | |
6388 | @item @samp{log10@var{m}2} | |
6389 | Store the base-10 logarithm of operand 1 into operand 0. Both operands | |
6390 | have mode @var{m}, which is a scalar or vector floating-point mode. | |
6391 | ||
6392 | This pattern is not allowed to @code{FAIL}. | |
6393 | ||
6394 | @cindex @code{log2@var{m}2} instruction pattern | |
6395 | @item @samp{log2@var{m}2} | |
6396 | Store the base-2 logarithm of operand 1 into operand 0. Both operands | |
6397 | have mode @var{m}, which is a scalar or vector floating-point mode. | |
6398 | ||
6399 | This pattern is not allowed to @code{FAIL}. | |
6400 | ||
6401 | @cindex @code{logb@var{m}2} instruction pattern | |
6402 | @item @samp{logb@var{m}2} | |
6403 | Store the base-@code{FLT_RADIX} logarithm of operand 1 into operand 0. | |
6404 | Both operands have mode @var{m}, which is a scalar or vector | |
6405 | floating-point mode. | |
6406 | ||
6407 | This pattern is not allowed to @code{FAIL}. | |
6408 | ||
b551ea37 | 6409 | @cindex @code{signbit@var{m}2} instruction pattern |
6410 | @item @samp{signbit@var{m}2} | |
6411 | Store the sign bit of floating-point operand 1 in operand 0. | |
6412 | @var{m} is either a scalar or vector mode. When it is a scalar, | |
6413 | operand 1 has mode @var{m} but operand 0 must have mode @code{SImode}. | |
6414 | When @var{m} is a vector, operand 1 has the mode @var{m}. | |
6415 | operand 0's mode should be an vector integer mode which has | |
6416 | the same number of elements and the same size as mode @var{m}. | |
6417 | ||
6418 | This pattern is not allowed to @code{FAIL}. | |
6419 | ||
d77de738 ML |
6420 | @cindex @code{significand@var{m}2} instruction pattern |
6421 | @item @samp{significand@var{m}2} | |
6422 | Store the significand of floating-point operand 1 in operand 0. | |
6423 | Both operands have mode @var{m}, which is a scalar or vector | |
6424 | floating-point mode. | |
6425 | ||
6426 | This pattern is not allowed to @code{FAIL}. | |
6427 | ||
6428 | @cindex @code{pow@var{m}3} instruction pattern | |
6429 | @item @samp{pow@var{m}3} | |
6430 | Store the value of operand 1 raised to the exponent operand 2 | |
6431 | into operand 0. All operands have mode @var{m}, which is a scalar | |
6432 | or vector floating-point mode. | |
6433 | ||
6434 | This pattern is not allowed to @code{FAIL}. | |
6435 | ||
6436 | @cindex @code{atan2@var{m}3} instruction pattern | |
6437 | @item @samp{atan2@var{m}3} | |
6438 | Store the arc tangent (inverse tangent) of operand 1 divided by | |
6439 | operand 2 into operand 0, using the signs of both arguments to | |
6440 | determine the quadrant of the result. All operands have mode | |
6441 | @var{m}, which is a scalar or vector floating-point mode. | |
6442 | ||
6443 | This pattern is not allowed to @code{FAIL}. | |
6444 | ||
6445 | @cindex @code{floor@var{m}2} instruction pattern | |
6446 | @item @samp{floor@var{m}2} | |
6447 | Store the largest integral value not greater than operand 1 in operand 0. | |
6448 | Both operands have mode @var{m}, which is a scalar or vector | |
6449 | floating-point mode. If @option{-ffp-int-builtin-inexact} is in | |
6450 | effect, the ``inexact'' exception may be raised for noninteger | |
6451 | operands; otherwise, it may not. | |
6452 | ||
6453 | This pattern is not allowed to @code{FAIL}. | |
6454 | ||
6455 | @cindex @code{btrunc@var{m}2} instruction pattern | |
6456 | @item @samp{btrunc@var{m}2} | |
6457 | Round operand 1 to an integer, towards zero, and store the result in | |
6458 | operand 0. Both operands have mode @var{m}, which is a scalar or | |
6459 | vector floating-point mode. If @option{-ffp-int-builtin-inexact} is | |
6460 | in effect, the ``inexact'' exception may be raised for noninteger | |
6461 | operands; otherwise, it may not. | |
6462 | ||
6463 | This pattern is not allowed to @code{FAIL}. | |
6464 | ||
6465 | @cindex @code{round@var{m}2} instruction pattern | |
6466 | @item @samp{round@var{m}2} | |
6467 | Round operand 1 to the nearest integer, rounding away from zero in the | |
6468 | event of a tie, and store the result in operand 0. Both operands have | |
6469 | mode @var{m}, which is a scalar or vector floating-point mode. If | |
6470 | @option{-ffp-int-builtin-inexact} is in effect, the ``inexact'' | |
6471 | exception may be raised for noninteger operands; otherwise, it may | |
6472 | not. | |
6473 | ||
6474 | This pattern is not allowed to @code{FAIL}. | |
6475 | ||
6476 | @cindex @code{ceil@var{m}2} instruction pattern | |
6477 | @item @samp{ceil@var{m}2} | |
6478 | Store the smallest integral value not less than operand 1 in operand 0. | |
6479 | Both operands have mode @var{m}, which is a scalar or vector | |
6480 | floating-point mode. If @option{-ffp-int-builtin-inexact} is in | |
6481 | effect, the ``inexact'' exception may be raised for noninteger | |
6482 | operands; otherwise, it may not. | |
6483 | ||
6484 | This pattern is not allowed to @code{FAIL}. | |
6485 | ||
6486 | @cindex @code{nearbyint@var{m}2} instruction pattern | |
6487 | @item @samp{nearbyint@var{m}2} | |
6488 | Round operand 1 to an integer, using the current rounding mode, and | |
6489 | store the result in operand 0. Do not raise an inexact condition when | |
6490 | the result is different from the argument. Both operands have mode | |
6491 | @var{m}, which is a scalar or vector floating-point mode. | |
6492 | ||
6493 | This pattern is not allowed to @code{FAIL}. | |
6494 | ||
6495 | @cindex @code{rint@var{m}2} instruction pattern | |
6496 | @item @samp{rint@var{m}2} | |
6497 | Round operand 1 to an integer, using the current rounding mode, and | |
6498 | store the result in operand 0. Raise an inexact condition when | |
6499 | the result is different from the argument. Both operands have mode | |
6500 | @var{m}, which is a scalar or vector floating-point mode. | |
6501 | ||
6502 | This pattern is not allowed to @code{FAIL}. | |
6503 | ||
6504 | @cindex @code{lrint@var{m}@var{n}2} | |
6505 | @item @samp{lrint@var{m}@var{n}2} | |
6506 | Convert operand 1 (valid for floating point mode @var{m}) to fixed | |
6507 | point mode @var{n} as a signed number according to the current | |
6508 | rounding mode and store in operand 0 (which has mode @var{n}). | |
6509 | ||
6510 | @cindex @code{lround@var{m}@var{n}2} | |
6511 | @item @samp{lround@var{m}@var{n}2} | |
6512 | Convert operand 1 (valid for floating point mode @var{m}) to fixed | |
6513 | point mode @var{n} as a signed number rounding to nearest and away | |
6514 | from zero and store in operand 0 (which has mode @var{n}). | |
6515 | ||
6516 | @cindex @code{lfloor@var{m}@var{n}2} | |
6517 | @item @samp{lfloor@var{m}@var{n}2} | |
6518 | Convert operand 1 (valid for floating point mode @var{m}) to fixed | |
6519 | point mode @var{n} as a signed number rounding down and store in | |
6520 | operand 0 (which has mode @var{n}). | |
6521 | ||
6522 | @cindex @code{lceil@var{m}@var{n}2} | |
6523 | @item @samp{lceil@var{m}@var{n}2} | |
6524 | Convert operand 1 (valid for floating point mode @var{m}) to fixed | |
6525 | point mode @var{n} as a signed number rounding up and store in | |
6526 | operand 0 (which has mode @var{n}). | |
6527 | ||
6528 | @cindex @code{copysign@var{m}3} instruction pattern | |
6529 | @item @samp{copysign@var{m}3} | |
6530 | Store a value with the magnitude of operand 1 and the sign of operand | |
6531 | 2 into operand 0. All operands have mode @var{m}, which is a scalar or | |
6532 | vector floating-point mode. | |
6533 | ||
6534 | This pattern is not allowed to @code{FAIL}. | |
6535 | ||
6536 | @cindex @code{xorsign@var{m}3} instruction pattern | |
6537 | @item @samp{xorsign@var{m}3} | |
6538 | Equivalent to @samp{op0 = op1 * copysign (1.0, op2)}: store a value with | |
6539 | the magnitude of operand 1 and the sign of operand 2 into operand 0. | |
6540 | All operands have mode @var{m}, which is a scalar or vector | |
6541 | floating-point mode. | |
6542 | ||
6543 | This pattern is not allowed to @code{FAIL}. | |
6544 | ||
6545 | @cindex @code{issignaling@var{m}2} instruction pattern | |
6546 | @item @samp{issignaling@var{m}2} | |
6547 | Set operand 0 to 1 if operand 1 is a signaling NaN and to 0 otherwise. | |
6548 | ||
6549 | @cindex @code{cadd90@var{m}3} instruction pattern | |
6550 | @item @samp{cadd90@var{m}3} | |
6551 | Perform vector add and subtract on even/odd number pairs. The operation being | |
6552 | matched is semantically described as | |
6553 | ||
6554 | @smallexample | |
6555 | for (int i = 0; i < N; i += 2) | |
6556 | @{ | |
6557 | c[i] = a[i] - b[i+1]; | |
6558 | c[i+1] = a[i+1] + b[i]; | |
6559 | @} | |
6560 | @end smallexample | |
6561 | ||
6562 | This operation is semantically equivalent to performing a vector addition of | |
6563 | complex numbers in operand 1 with operand 2 rotated by 90 degrees around | |
6564 | the argand plane and storing the result in operand 0. | |
6565 | ||
6566 | In GCC lane ordering the real part of the number must be in the even lanes with | |
6567 | the imaginary part in the odd lanes. | |
6568 | ||
6569 | The operation is only supported for vector modes @var{m}. | |
6570 | ||
6571 | This pattern is not allowed to @code{FAIL}. | |
6572 | ||
6573 | @cindex @code{cadd270@var{m}3} instruction pattern | |
6574 | @item @samp{cadd270@var{m}3} | |
6575 | Perform vector add and subtract on even/odd number pairs. The operation being | |
6576 | matched is semantically described as | |
6577 | ||
6578 | @smallexample | |
6579 | for (int i = 0; i < N; i += 2) | |
6580 | @{ | |
6581 | c[i] = a[i] + b[i+1]; | |
6582 | c[i+1] = a[i+1] - b[i]; | |
6583 | @} | |
6584 | @end smallexample | |
6585 | ||
6586 | This operation is semantically equivalent to performing a vector addition of | |
6587 | complex numbers in operand 1 with operand 2 rotated by 270 degrees around | |
6588 | the argand plane and storing the result in operand 0. | |
6589 | ||
6590 | In GCC lane ordering the real part of the number must be in the even lanes with | |
6591 | the imaginary part in the odd lanes. | |
6592 | ||
6593 | The operation is only supported for vector modes @var{m}. | |
6594 | ||
6595 | This pattern is not allowed to @code{FAIL}. | |
6596 | ||
6597 | @cindex @code{cmla@var{m}4} instruction pattern | |
6598 | @item @samp{cmla@var{m}4} | |
6599 | Perform a vector multiply and accumulate that is semantically the same as | |
6600 | a multiply and accumulate of complex numbers. | |
6601 | ||
6602 | @smallexample | |
6603 | complex TYPE op0[N]; | |
6604 | complex TYPE op1[N]; | |
6605 | complex TYPE op2[N]; | |
6606 | complex TYPE op3[N]; | |
6607 | for (int i = 0; i < N; i += 1) | |
6608 | @{ | |
6609 | op0[i] = op1[i] * op2[i] + op3[i]; | |
6610 | @} | |
6611 | @end smallexample | |
6612 | ||
6613 | In GCC lane ordering the real part of the number must be in the even lanes with | |
6614 | the imaginary part in the odd lanes. | |
6615 | ||
6616 | The operation is only supported for vector modes @var{m}. | |
6617 | ||
6618 | This pattern is not allowed to @code{FAIL}. | |
6619 | ||
6620 | @cindex @code{cmla_conj@var{m}4} instruction pattern | |
6621 | @item @samp{cmla_conj@var{m}4} | |
6622 | Perform a vector multiply by conjugate and accumulate that is semantically | |
6623 | the same as a multiply and accumulate of complex numbers where the second | |
6624 | multiply arguments is conjugated. | |
6625 | ||
6626 | @smallexample | |
6627 | complex TYPE op0[N]; | |
6628 | complex TYPE op1[N]; | |
6629 | complex TYPE op2[N]; | |
6630 | complex TYPE op3[N]; | |
6631 | for (int i = 0; i < N; i += 1) | |
6632 | @{ | |
6633 | op0[i] = op1[i] * conj (op2[i]) + op3[i]; | |
6634 | @} | |
6635 | @end smallexample | |
6636 | ||
6637 | In GCC lane ordering the real part of the number must be in the even lanes with | |
6638 | the imaginary part in the odd lanes. | |
6639 | ||
6640 | The operation is only supported for vector modes @var{m}. | |
6641 | ||
6642 | This pattern is not allowed to @code{FAIL}. | |
6643 | ||
6644 | @cindex @code{cmls@var{m}4} instruction pattern | |
6645 | @item @samp{cmls@var{m}4} | |
6646 | Perform a vector multiply and subtract that is semantically the same as | |
6647 | a multiply and subtract of complex numbers. | |
6648 | ||
6649 | @smallexample | |
6650 | complex TYPE op0[N]; | |
6651 | complex TYPE op1[N]; | |
6652 | complex TYPE op2[N]; | |
6653 | complex TYPE op3[N]; | |
6654 | for (int i = 0; i < N; i += 1) | |
6655 | @{ | |
6656 | op0[i] = op1[i] * op2[i] - op3[i]; | |
6657 | @} | |
6658 | @end smallexample | |
6659 | ||
6660 | In GCC lane ordering the real part of the number must be in the even lanes with | |
6661 | the imaginary part in the odd lanes. | |
6662 | ||
6663 | The operation is only supported for vector modes @var{m}. | |
6664 | ||
6665 | This pattern is not allowed to @code{FAIL}. | |
6666 | ||
6667 | @cindex @code{cmls_conj@var{m}4} instruction pattern | |
6668 | @item @samp{cmls_conj@var{m}4} | |
6669 | Perform a vector multiply by conjugate and subtract that is semantically | |
6670 | the same as a multiply and subtract of complex numbers where the second | |
6671 | multiply arguments is conjugated. | |
6672 | ||
6673 | @smallexample | |
6674 | complex TYPE op0[N]; | |
6675 | complex TYPE op1[N]; | |
6676 | complex TYPE op2[N]; | |
6677 | complex TYPE op3[N]; | |
6678 | for (int i = 0; i < N; i += 1) | |
6679 | @{ | |
6680 | op0[i] = op1[i] * conj (op2[i]) - op3[i]; | |
6681 | @} | |
6682 | @end smallexample | |
6683 | ||
6684 | In GCC lane ordering the real part of the number must be in the even lanes with | |
6685 | the imaginary part in the odd lanes. | |
6686 | ||
6687 | The operation is only supported for vector modes @var{m}. | |
6688 | ||
6689 | This pattern is not allowed to @code{FAIL}. | |
6690 | ||
6691 | @cindex @code{cmul@var{m}4} instruction pattern | |
6692 | @item @samp{cmul@var{m}4} | |
6693 | Perform a vector multiply that is semantically the same as multiply of | |
6694 | complex numbers. | |
6695 | ||
6696 | @smallexample | |
6697 | complex TYPE op0[N]; | |
6698 | complex TYPE op1[N]; | |
6699 | complex TYPE op2[N]; | |
6700 | for (int i = 0; i < N; i += 1) | |
6701 | @{ | |
6702 | op0[i] = op1[i] * op2[i]; | |
6703 | @} | |
6704 | @end smallexample | |
6705 | ||
6706 | In GCC lane ordering the real part of the number must be in the even lanes with | |
6707 | the imaginary part in the odd lanes. | |
6708 | ||
6709 | The operation is only supported for vector modes @var{m}. | |
6710 | ||
6711 | This pattern is not allowed to @code{FAIL}. | |
6712 | ||
6713 | @cindex @code{cmul_conj@var{m}4} instruction pattern | |
6714 | @item @samp{cmul_conj@var{m}4} | |
6715 | Perform a vector multiply by conjugate that is semantically the same as a | |
6716 | multiply of complex numbers where the second multiply arguments is conjugated. | |
6717 | ||
6718 | @smallexample | |
6719 | complex TYPE op0[N]; | |
6720 | complex TYPE op1[N]; | |
6721 | complex TYPE op2[N]; | |
6722 | for (int i = 0; i < N; i += 1) | |
6723 | @{ | |
6724 | op0[i] = op1[i] * conj (op2[i]); | |
6725 | @} | |
6726 | @end smallexample | |
6727 | ||
6728 | In GCC lane ordering the real part of the number must be in the even lanes with | |
6729 | the imaginary part in the odd lanes. | |
6730 | ||
6731 | The operation is only supported for vector modes @var{m}. | |
6732 | ||
6733 | This pattern is not allowed to @code{FAIL}. | |
6734 | ||
6735 | @cindex @code{ffs@var{m}2} instruction pattern | |
6736 | @item @samp{ffs@var{m}2} | |
6737 | Store into operand 0 one plus the index of the least significant 1-bit | |
6738 | of operand 1. If operand 1 is zero, store zero. | |
6739 | ||
6740 | @var{m} is either a scalar or vector integer mode. When it is a scalar, | |
6741 | operand 1 has mode @var{m} but operand 0 can have whatever scalar | |
6742 | integer mode is suitable for the target. The compiler will insert | |
6743 | conversion instructions as necessary (typically to convert the result | |
6744 | to the same width as @code{int}). When @var{m} is a vector, both | |
6745 | operands must have mode @var{m}. | |
6746 | ||
6747 | This pattern is not allowed to @code{FAIL}. | |
6748 | ||
6749 | @cindex @code{clrsb@var{m}2} instruction pattern | |
6750 | @item @samp{clrsb@var{m}2} | |
6751 | Count leading redundant sign bits. | |
6752 | Store into operand 0 the number of redundant sign bits in operand 1, starting | |
6753 | at the most significant bit position. | |
6754 | A redundant sign bit is defined as any sign bit after the first. As such, | |
6755 | this count will be one less than the count of leading sign bits. | |
6756 | ||
6757 | @var{m} is either a scalar or vector integer mode. When it is a scalar, | |
6758 | operand 1 has mode @var{m} but operand 0 can have whatever scalar | |
6759 | integer mode is suitable for the target. The compiler will insert | |
6760 | conversion instructions as necessary (typically to convert the result | |
6761 | to the same width as @code{int}). When @var{m} is a vector, both | |
6762 | operands must have mode @var{m}. | |
6763 | ||
6764 | This pattern is not allowed to @code{FAIL}. | |
6765 | ||
6766 | @cindex @code{clz@var{m}2} instruction pattern | |
6767 | @item @samp{clz@var{m}2} | |
6768 | Store into operand 0 the number of leading 0-bits in operand 1, starting | |
6769 | at the most significant bit position. If operand 1 is 0, the | |
6770 | @code{CLZ_DEFINED_VALUE_AT_ZERO} (@pxref{Misc}) macro defines if | |
6771 | the result is undefined or has a useful value. | |
6772 | ||
6773 | @var{m} is either a scalar or vector integer mode. When it is a scalar, | |
6774 | operand 1 has mode @var{m} but operand 0 can have whatever scalar | |
6775 | integer mode is suitable for the target. The compiler will insert | |
6776 | conversion instructions as necessary (typically to convert the result | |
6777 | to the same width as @code{int}). When @var{m} is a vector, both | |
6778 | operands must have mode @var{m}. | |
6779 | ||
6780 | This pattern is not allowed to @code{FAIL}. | |
6781 | ||
6782 | @cindex @code{ctz@var{m}2} instruction pattern | |
6783 | @item @samp{ctz@var{m}2} | |
6784 | Store into operand 0 the number of trailing 0-bits in operand 1, starting | |
6785 | at the least significant bit position. If operand 1 is 0, the | |
6786 | @code{CTZ_DEFINED_VALUE_AT_ZERO} (@pxref{Misc}) macro defines if | |
6787 | the result is undefined or has a useful value. | |
6788 | ||
6789 | @var{m} is either a scalar or vector integer mode. When it is a scalar, | |
6790 | operand 1 has mode @var{m} but operand 0 can have whatever scalar | |
6791 | integer mode is suitable for the target. The compiler will insert | |
6792 | conversion instructions as necessary (typically to convert the result | |
6793 | to the same width as @code{int}). When @var{m} is a vector, both | |
6794 | operands must have mode @var{m}. | |
6795 | ||
6796 | This pattern is not allowed to @code{FAIL}. | |
6797 | ||
6798 | @cindex @code{popcount@var{m}2} instruction pattern | |
6799 | @item @samp{popcount@var{m}2} | |
6800 | Store into operand 0 the number of 1-bits in operand 1. | |
6801 | ||
6802 | @var{m} is either a scalar or vector integer mode. When it is a scalar, | |
6803 | operand 1 has mode @var{m} but operand 0 can have whatever scalar | |
6804 | integer mode is suitable for the target. The compiler will insert | |
6805 | conversion instructions as necessary (typically to convert the result | |
6806 | to the same width as @code{int}). When @var{m} is a vector, both | |
6807 | operands must have mode @var{m}. | |
6808 | ||
6809 | This pattern is not allowed to @code{FAIL}. | |
6810 | ||
6811 | @cindex @code{parity@var{m}2} instruction pattern | |
6812 | @item @samp{parity@var{m}2} | |
6813 | Store into operand 0 the parity of operand 1, i.e.@: the number of 1-bits | |
6814 | in operand 1 modulo 2. | |
6815 | ||
6816 | @var{m} is either a scalar or vector integer mode. When it is a scalar, | |
6817 | operand 1 has mode @var{m} but operand 0 can have whatever scalar | |
6818 | integer mode is suitable for the target. The compiler will insert | |
6819 | conversion instructions as necessary (typically to convert the result | |
6820 | to the same width as @code{int}). When @var{m} is a vector, both | |
6821 | operands must have mode @var{m}. | |
6822 | ||
6823 | This pattern is not allowed to @code{FAIL}. | |
6824 | ||
6825 | @cindex @code{one_cmpl@var{m}2} instruction pattern | |
6826 | @item @samp{one_cmpl@var{m}2} | |
6827 | Store the bitwise-complement of operand 1 into operand 0. | |
6828 | ||
6829 | @cindex @code{cpymem@var{m}} instruction pattern | |
6830 | @item @samp{cpymem@var{m}} | |
6831 | Block copy instruction. The destination and source blocks of memory | |
6832 | are the first two operands, and both are @code{mem:BLK}s with an | |
6833 | address in mode @code{Pmode}. | |
6834 | ||
6835 | The number of bytes to copy is the third operand, in mode @var{m}. | |
6836 | Usually, you specify @code{Pmode} for @var{m}. However, if you can | |
6837 | generate better code knowing the range of valid lengths is smaller than | |
6838 | those representable in a full Pmode pointer, you should provide | |
6839 | a pattern with a | |
6840 | mode corresponding to the range of values you can handle efficiently | |
6841 | (e.g., @code{QImode} for values in the range 0--127; note we avoid numbers | |
6842 | that appear negative) and also a pattern with @code{Pmode}. | |
6843 | ||
6844 | The fourth operand is the known shared alignment of the source and | |
6845 | destination, in the form of a @code{const_int} rtx. Thus, if the | |
6846 | compiler knows that both source and destination are word-aligned, | |
6847 | it may provide the value 4 for this operand. | |
6848 | ||
6849 | Optional operands 5 and 6 specify expected alignment and size of block | |
6850 | respectively. The expected alignment differs from alignment in operand 4 | |
6851 | in a way that the blocks are not required to be aligned according to it in | |
6852 | all cases. This expected alignment is also in bytes, just like operand 4. | |
6853 | Expected size, when unknown, is set to @code{(const_int -1)}. | |
6854 | ||
6855 | Descriptions of multiple @code{cpymem@var{m}} patterns can only be | |
6856 | beneficial if the patterns for smaller modes have fewer restrictions | |
6857 | on their first, second and fourth operands. Note that the mode @var{m} | |
6858 | in @code{cpymem@var{m}} does not impose any restriction on the mode of | |
6859 | individually copied data units in the block. | |
6860 | ||
6861 | The @code{cpymem@var{m}} patterns need not give special consideration | |
6862 | to the possibility that the source and destination strings might | |
6863 | overlap. These patterns are used to do inline expansion of | |
6864 | @code{__builtin_memcpy}. | |
6865 | ||
6866 | @cindex @code{movmem@var{m}} instruction pattern | |
6867 | @item @samp{movmem@var{m}} | |
6868 | Block move instruction. The destination and source blocks of memory | |
6869 | are the first two operands, and both are @code{mem:BLK}s with an | |
6870 | address in mode @code{Pmode}. | |
6871 | ||
6872 | The number of bytes to copy is the third operand, in mode @var{m}. | |
6873 | Usually, you specify @code{Pmode} for @var{m}. However, if you can | |
6874 | generate better code knowing the range of valid lengths is smaller than | |
6875 | those representable in a full Pmode pointer, you should provide | |
6876 | a pattern with a | |
6877 | mode corresponding to the range of values you can handle efficiently | |
6878 | (e.g., @code{QImode} for values in the range 0--127; note we avoid numbers | |
6879 | that appear negative) and also a pattern with @code{Pmode}. | |
6880 | ||
6881 | The fourth operand is the known shared alignment of the source and | |
6882 | destination, in the form of a @code{const_int} rtx. Thus, if the | |
6883 | compiler knows that both source and destination are word-aligned, | |
6884 | it may provide the value 4 for this operand. | |
6885 | ||
6886 | Optional operands 5 and 6 specify expected alignment and size of block | |
6887 | respectively. The expected alignment differs from alignment in operand 4 | |
6888 | in a way that the blocks are not required to be aligned according to it in | |
6889 | all cases. This expected alignment is also in bytes, just like operand 4. | |
6890 | Expected size, when unknown, is set to @code{(const_int -1)}. | |
6891 | ||
6892 | Descriptions of multiple @code{movmem@var{m}} patterns can only be | |
6893 | beneficial if the patterns for smaller modes have fewer restrictions | |
6894 | on their first, second and fourth operands. Note that the mode @var{m} | |
6895 | in @code{movmem@var{m}} does not impose any restriction on the mode of | |
6896 | individually copied data units in the block. | |
6897 | ||
6898 | The @code{movmem@var{m}} patterns must correctly handle the case where | |
6899 | the source and destination strings overlap. These patterns are used to | |
6900 | do inline expansion of @code{__builtin_memmove}. | |
6901 | ||
6902 | @cindex @code{movstr} instruction pattern | |
6903 | @item @samp{movstr} | |
6904 | String copy instruction, with @code{stpcpy} semantics. Operand 0 is | |
6905 | an output operand in mode @code{Pmode}. The addresses of the | |
6906 | destination and source strings are operands 1 and 2, and both are | |
6907 | @code{mem:BLK}s with addresses in mode @code{Pmode}. The execution of | |
6908 | the expansion of this pattern should store in operand 0 the address in | |
6909 | which the @code{NUL} terminator was stored in the destination string. | |
6910 | ||
6911 | This pattern has also several optional operands that are same as in | |
6912 | @code{setmem}. | |
6913 | ||
6914 | @cindex @code{setmem@var{m}} instruction pattern | |
6915 | @item @samp{setmem@var{m}} | |
6916 | Block set instruction. The destination string is the first operand, | |
6917 | given as a @code{mem:BLK} whose address is in mode @code{Pmode}. The | |
6918 | number of bytes to set is the second operand, in mode @var{m}. The value to | |
6919 | initialize the memory with is the third operand. Targets that only support the | |
6920 | clearing of memory should reject any value that is not the constant 0. See | |
6921 | @samp{cpymem@var{m}} for a discussion of the choice of mode. | |
6922 | ||
6923 | The fourth operand is the known alignment of the destination, in the form | |
6924 | of a @code{const_int} rtx. Thus, if the compiler knows that the | |
6925 | destination is word-aligned, it may provide the value 4 for this | |
6926 | operand. | |
6927 | ||
6928 | Optional operands 5 and 6 specify expected alignment and size of block | |
6929 | respectively. The expected alignment differs from alignment in operand 4 | |
6930 | in a way that the blocks are not required to be aligned according to it in | |
6931 | all cases. This expected alignment is also in bytes, just like operand 4. | |
6932 | Expected size, when unknown, is set to @code{(const_int -1)}. | |
6933 | Operand 7 is the minimal size of the block and operand 8 is the | |
6934 | maximal size of the block (NULL if it cannot be represented as CONST_INT). | |
6935 | Operand 9 is the probable maximal size (i.e.@: we cannot rely on it for | |
6936 | correctness, but it can be used for choosing proper code sequence for a | |
6937 | given size). | |
6938 | ||
6939 | The use for multiple @code{setmem@var{m}} is as for @code{cpymem@var{m}}. | |
6940 | ||
6941 | @cindex @code{cmpstrn@var{m}} instruction pattern | |
6942 | @item @samp{cmpstrn@var{m}} | |
6943 | String compare instruction, with five operands. Operand 0 is the output; | |
6944 | it has mode @var{m}. The remaining four operands are like the operands | |
6945 | of @samp{cpymem@var{m}}. The two memory blocks specified are compared | |
6946 | byte by byte in lexicographic order starting at the beginning of each | |
6947 | string. The instruction is not allowed to prefetch more than one byte | |
6948 | at a time since either string may end in the first byte and reading past | |
6949 | that may access an invalid page or segment and cause a fault. The | |
6950 | comparison terminates early if the fetched bytes are different or if | |
6951 | they are equal to zero. The effect of the instruction is to store a | |
6952 | value in operand 0 whose sign indicates the result of the comparison. | |
6953 | ||
6954 | @cindex @code{cmpstr@var{m}} instruction pattern | |
6955 | @item @samp{cmpstr@var{m}} | |
6956 | String compare instruction, without known maximum length. Operand 0 is the | |
6957 | output; it has mode @var{m}. The second and third operand are the blocks of | |
6958 | memory to be compared; both are @code{mem:BLK} with an address in mode | |
6959 | @code{Pmode}. | |
6960 | ||
6961 | The fourth operand is the known shared alignment of the source and | |
6962 | destination, in the form of a @code{const_int} rtx. Thus, if the | |
6963 | compiler knows that both source and destination are word-aligned, | |
6964 | it may provide the value 4 for this operand. | |
6965 | ||
6966 | The two memory blocks specified are compared byte by byte in lexicographic | |
6967 | order starting at the beginning of each string. The instruction is not allowed | |
6968 | to prefetch more than one byte at a time since either string may end in the | |
6969 | first byte and reading past that may access an invalid page or segment and | |
6970 | cause a fault. The comparison will terminate when the fetched bytes | |
6971 | are different or if they are equal to zero. The effect of the | |
6972 | instruction is to store a value in operand 0 whose sign indicates the | |
6973 | result of the comparison. | |
6974 | ||
6975 | @cindex @code{cmpmem@var{m}} instruction pattern | |
6976 | @item @samp{cmpmem@var{m}} | |
6977 | Block compare instruction, with five operands like the operands | |
6978 | of @samp{cmpstr@var{m}}. The two memory blocks specified are compared | |
6979 | byte by byte in lexicographic order starting at the beginning of each | |
6980 | block. Unlike @samp{cmpstr@var{m}} the instruction can prefetch | |
6981 | any bytes in the two memory blocks. Also unlike @samp{cmpstr@var{m}} | |
6982 | the comparison will not stop if both bytes are zero. The effect of | |
6983 | the instruction is to store a value in operand 0 whose sign indicates | |
6984 | the result of the comparison. | |
6985 | ||
6986 | @cindex @code{strlen@var{m}} instruction pattern | |
6987 | @item @samp{strlen@var{m}} | |
6988 | Compute the length of a string, with three operands. | |
6989 | Operand 0 is the result (of mode @var{m}), operand 1 is | |
6990 | a @code{mem} referring to the first character of the string, | |
6991 | operand 2 is the character to search for (normally zero), | |
6992 | and operand 3 is a constant describing the known alignment | |
6993 | of the beginning of the string. | |
6994 | ||
6995 | @cindex @code{rawmemchr@var{m}} instruction pattern | |
6996 | @item @samp{rawmemchr@var{m}} | |
6997 | Scan memory referred to by operand 1 for the first occurrence of operand 2. | |
6998 | Operand 1 is a @code{mem} and operand 2 a @code{const_int} of mode @var{m}. | |
6999 | Operand 0 is the result, i.e., a pointer to the first occurrence of operand 2 | |
7000 | in the memory block given by operand 1. | |
7001 | ||
7002 | @cindex @code{float@var{m}@var{n}2} instruction pattern | |
7003 | @item @samp{float@var{m}@var{n}2} | |
7004 | Convert signed integer operand 1 (valid for fixed point mode @var{m}) to | |
7005 | floating point mode @var{n} and store in operand 0 (which has mode | |
7006 | @var{n}). | |
7007 | ||
7008 | @cindex @code{floatuns@var{m}@var{n}2} instruction pattern | |
7009 | @item @samp{floatuns@var{m}@var{n}2} | |
7010 | Convert unsigned integer operand 1 (valid for fixed point mode @var{m}) | |
7011 | to floating point mode @var{n} and store in operand 0 (which has mode | |
7012 | @var{n}). | |
7013 | ||
7014 | @cindex @code{fix@var{m}@var{n}2} instruction pattern | |
7015 | @item @samp{fix@var{m}@var{n}2} | |
7016 | Convert operand 1 (valid for floating point mode @var{m}) to fixed | |
7017 | point mode @var{n} as a signed number and store in operand 0 (which | |
7018 | has mode @var{n}). This instruction's result is defined only when | |
7019 | the value of operand 1 is an integer. | |
7020 | ||
7021 | If the machine description defines this pattern, it also needs to | |
7022 | define the @code{ftrunc} pattern. | |
7023 | ||
7024 | @cindex @code{fixuns@var{m}@var{n}2} instruction pattern | |
7025 | @item @samp{fixuns@var{m}@var{n}2} | |
7026 | Convert operand 1 (valid for floating point mode @var{m}) to fixed | |
7027 | point mode @var{n} as an unsigned number and store in operand 0 (which | |
7028 | has mode @var{n}). This instruction's result is defined only when the | |
7029 | value of operand 1 is an integer. | |
7030 | ||
7031 | @cindex @code{ftrunc@var{m}2} instruction pattern | |
7032 | @item @samp{ftrunc@var{m}2} | |
7033 | Convert operand 1 (valid for floating point mode @var{m}) to an | |
7034 | integer value, still represented in floating point mode @var{m}, and | |
7035 | store it in operand 0 (valid for floating point mode @var{m}). | |
7036 | ||
7037 | @cindex @code{fix_trunc@var{m}@var{n}2} instruction pattern | |
7038 | @item @samp{fix_trunc@var{m}@var{n}2} | |
7039 | Like @samp{fix@var{m}@var{n}2} but works for any floating point value | |
7040 | of mode @var{m} by converting the value to an integer. | |
7041 | ||
7042 | @cindex @code{fixuns_trunc@var{m}@var{n}2} instruction pattern | |
7043 | @item @samp{fixuns_trunc@var{m}@var{n}2} | |
7044 | Like @samp{fixuns@var{m}@var{n}2} but works for any floating point | |
7045 | value of mode @var{m} by converting the value to an integer. | |
7046 | ||
7047 | @cindex @code{trunc@var{m}@var{n}2} instruction pattern | |
7048 | @item @samp{trunc@var{m}@var{n}2} | |
7049 | Truncate operand 1 (valid for mode @var{m}) to mode @var{n} and | |
7050 | store in operand 0 (which has mode @var{n}). Both modes must be fixed | |
7051 | point or both floating point. | |
7052 | ||
7053 | @cindex @code{extend@var{m}@var{n}2} instruction pattern | |
7054 | @item @samp{extend@var{m}@var{n}2} | |
7055 | Sign-extend operand 1 (valid for mode @var{m}) to mode @var{n} and | |
7056 | store in operand 0 (which has mode @var{n}). Both modes must be fixed | |
7057 | point or both floating point. | |
7058 | ||
7059 | @cindex @code{zero_extend@var{m}@var{n}2} instruction pattern | |
7060 | @item @samp{zero_extend@var{m}@var{n}2} | |
7061 | Zero-extend operand 1 (valid for mode @var{m}) to mode @var{n} and | |
7062 | store in operand 0 (which has mode @var{n}). Both modes must be fixed | |
7063 | point. | |
7064 | ||
7065 | @cindex @code{fract@var{m}@var{n}2} instruction pattern | |
7066 | @item @samp{fract@var{m}@var{n}2} | |
7067 | Convert operand 1 of mode @var{m} to mode @var{n} and store in | |
7068 | operand 0 (which has mode @var{n}). Mode @var{m} and mode @var{n} | |
7069 | could be fixed-point to fixed-point, signed integer to fixed-point, | |
7070 | fixed-point to signed integer, floating-point to fixed-point, | |
7071 | or fixed-point to floating-point. | |
7072 | When overflows or underflows happen, the results are undefined. | |
7073 | ||
7074 | @cindex @code{satfract@var{m}@var{n}2} instruction pattern | |
7075 | @item @samp{satfract@var{m}@var{n}2} | |
7076 | Convert operand 1 of mode @var{m} to mode @var{n} and store in | |
7077 | operand 0 (which has mode @var{n}). Mode @var{m} and mode @var{n} | |
7078 | could be fixed-point to fixed-point, signed integer to fixed-point, | |
7079 | or floating-point to fixed-point. | |
7080 | When overflows or underflows happen, the instruction saturates the | |
7081 | results to the maximum or the minimum. | |
7082 | ||
7083 | @cindex @code{fractuns@var{m}@var{n}2} instruction pattern | |
7084 | @item @samp{fractuns@var{m}@var{n}2} | |
7085 | Convert operand 1 of mode @var{m} to mode @var{n} and store in | |
7086 | operand 0 (which has mode @var{n}). Mode @var{m} and mode @var{n} | |
7087 | could be unsigned integer to fixed-point, or | |
7088 | fixed-point to unsigned integer. | |
7089 | When overflows or underflows happen, the results are undefined. | |
7090 | ||
7091 | @cindex @code{satfractuns@var{m}@var{n}2} instruction pattern | |
7092 | @item @samp{satfractuns@var{m}@var{n}2} | |
7093 | Convert unsigned integer operand 1 of mode @var{m} to fixed-point mode | |
7094 | @var{n} and store in operand 0 (which has mode @var{n}). | |
7095 | When overflows or underflows happen, the instruction saturates the | |
7096 | results to the maximum or the minimum. | |
7097 | ||
7098 | @cindex @code{extv@var{m}} instruction pattern | |
7099 | @item @samp{extv@var{m}} | |
7100 | Extract a bit-field from register operand 1, sign-extend it, and store | |
7101 | it in operand 0. Operand 2 specifies the width of the field in bits | |
7102 | and operand 3 the starting bit, which counts from the most significant | |
7103 | bit if @samp{BITS_BIG_ENDIAN} is true and from the least significant bit | |
7104 | otherwise. | |
7105 | ||
7106 | Operands 0 and 1 both have mode @var{m}. Operands 2 and 3 have a | |
7107 | target-specific mode. | |
7108 | ||
7109 | @cindex @code{extvmisalign@var{m}} instruction pattern | |
7110 | @item @samp{extvmisalign@var{m}} | |
7111 | Extract a bit-field from memory operand 1, sign extend it, and store | |
7112 | it in operand 0. Operand 2 specifies the width in bits and operand 3 | |
7113 | the starting bit. The starting bit is always somewhere in the first byte of | |
7114 | operand 1; it counts from the most significant bit if @samp{BITS_BIG_ENDIAN} | |
7115 | is true and from the least significant bit otherwise. | |
7116 | ||
7117 | Operand 0 has mode @var{m} while operand 1 has @code{BLK} mode. | |
7118 | Operands 2 and 3 have a target-specific mode. | |
7119 | ||
7120 | The instruction must not read beyond the last byte of the bit-field. | |
7121 | ||
7122 | @cindex @code{extzv@var{m}} instruction pattern | |
7123 | @item @samp{extzv@var{m}} | |
7124 | Like @samp{extv@var{m}} except that the bit-field value is zero-extended. | |
7125 | ||
7126 | @cindex @code{extzvmisalign@var{m}} instruction pattern | |
7127 | @item @samp{extzvmisalign@var{m}} | |
7128 | Like @samp{extvmisalign@var{m}} except that the bit-field value is | |
7129 | zero-extended. | |
7130 | ||
7131 | @cindex @code{insv@var{m}} instruction pattern | |
7132 | @item @samp{insv@var{m}} | |
7133 | Insert operand 3 into a bit-field of register operand 0. Operand 1 | |
7134 | specifies the width of the field in bits and operand 2 the starting bit, | |
7135 | which counts from the most significant bit if @samp{BITS_BIG_ENDIAN} | |
7136 | is true and from the least significant bit otherwise. | |
7137 | ||
7138 | Operands 0 and 3 both have mode @var{m}. Operands 1 and 2 have a | |
7139 | target-specific mode. | |
7140 | ||
7141 | @cindex @code{insvmisalign@var{m}} instruction pattern | |
7142 | @item @samp{insvmisalign@var{m}} | |
7143 | Insert operand 3 into a bit-field of memory operand 0. Operand 1 | |
7144 | specifies the width of the field in bits and operand 2 the starting bit. | |
7145 | The starting bit is always somewhere in the first byte of operand 0; | |
7146 | it counts from the most significant bit if @samp{BITS_BIG_ENDIAN} | |
7147 | is true and from the least significant bit otherwise. | |
7148 | ||
7149 | Operand 3 has mode @var{m} while operand 0 has @code{BLK} mode. | |
7150 | Operands 1 and 2 have a target-specific mode. | |
7151 | ||
7152 | The instruction must not read or write beyond the last byte of the bit-field. | |
7153 | ||
7154 | @cindex @code{extv} instruction pattern | |
7155 | @item @samp{extv} | |
7156 | Extract a bit-field from operand 1 (a register or memory operand), where | |
7157 | operand 2 specifies the width in bits and operand 3 the starting bit, | |
7158 | and store it in operand 0. Operand 0 must have mode @code{word_mode}. | |
7159 | Operand 1 may have mode @code{byte_mode} or @code{word_mode}; often | |
7160 | @code{word_mode} is allowed only for registers. Operands 2 and 3 must | |
7161 | be valid for @code{word_mode}. | |
7162 | ||
7163 | The RTL generation pass generates this instruction only with constants | |
7164 | for operands 2 and 3 and the constant is never zero for operand 2. | |
7165 | ||
7166 | The bit-field value is sign-extended to a full word integer | |
7167 | before it is stored in operand 0. | |
7168 | ||
7169 | This pattern is deprecated; please use @samp{extv@var{m}} and | |
7170 | @code{extvmisalign@var{m}} instead. | |
7171 | ||
7172 | @cindex @code{extzv} instruction pattern | |
7173 | @item @samp{extzv} | |
7174 | Like @samp{extv} except that the bit-field value is zero-extended. | |
7175 | ||
7176 | This pattern is deprecated; please use @samp{extzv@var{m}} and | |
7177 | @code{extzvmisalign@var{m}} instead. | |
7178 | ||
7179 | @cindex @code{insv} instruction pattern | |
7180 | @item @samp{insv} | |
7181 | Store operand 3 (which must be valid for @code{word_mode}) into a | |
7182 | bit-field in operand 0, where operand 1 specifies the width in bits and | |
7183 | operand 2 the starting bit. Operand 0 may have mode @code{byte_mode} or | |
7184 | @code{word_mode}; often @code{word_mode} is allowed only for registers. | |
7185 | Operands 1 and 2 must be valid for @code{word_mode}. | |
7186 | ||
7187 | The RTL generation pass generates this instruction only with constants | |
7188 | for operands 1 and 2 and the constant is never zero for operand 1. | |
7189 | ||
7190 | This pattern is deprecated; please use @samp{insv@var{m}} and | |
7191 | @code{insvmisalign@var{m}} instead. | |
7192 | ||
7193 | @cindex @code{mov@var{mode}cc} instruction pattern | |
7194 | @item @samp{mov@var{mode}cc} | |
7195 | Conditionally move operand 2 or operand 3 into operand 0 according to the | |
7196 | comparison in operand 1. If the comparison is true, operand 2 is moved | |
7197 | into operand 0, otherwise operand 3 is moved. | |
7198 | ||
7199 | The mode of the operands being compared need not be the same as the operands | |
7200 | being moved. Some machines, sparc64 for example, have instructions that | |
7201 | conditionally move an integer value based on the floating point condition | |
7202 | codes and vice versa. | |
7203 | ||
7204 | If the machine does not have conditional move instructions, do not | |
7205 | define these patterns. | |
7206 | ||
7207 | @cindex @code{add@var{mode}cc} instruction pattern | |
7208 | @item @samp{add@var{mode}cc} | |
7209 | Similar to @samp{mov@var{mode}cc} but for conditional addition. Conditionally | |
7210 | move operand 2 or (operands 2 + operand 3) into operand 0 according to the | |
7211 | comparison in operand 1. If the comparison is false, operand 2 is moved into | |
7212 | operand 0, otherwise (operand 2 + operand 3) is moved. | |
7213 | ||
3064471b AP |
7214 | @cindex @code{cond_neg@var{mode}} instruction pattern |
7215 | @cindex @code{cond_one_cmpl@var{mode}} instruction pattern | |
7216 | @item @samp{cond_neg@var{mode}} | |
7217 | @itemx @samp{cond_one_cmpl@var{mode}} | |
7218 | When operand 1 is true, perform an operation on operands 2 and | |
7219 | store the result in operand 0, otherwise store operand 3 in operand 0. | |
7220 | The operation works elementwise if the operands are vectors. | |
7221 | ||
7222 | The scalar case is equivalent to: | |
7223 | ||
7224 | @smallexample | |
7225 | op0 = op1 ? @var{op} op2 : op3; | |
7226 | @end smallexample | |
7227 | ||
7228 | while the vector case is equivalent to: | |
7229 | ||
7230 | @smallexample | |
7231 | for (i = 0; i < GET_MODE_NUNITS (@var{m}); i++) | |
7232 | op0[i] = op1[i] ? @var{op} op2[i] : op3[i]; | |
7233 | @end smallexample | |
7234 | ||
7235 | where, for example, @var{op} is @code{~} for @samp{cond_one_cmpl@var{mode}}. | |
7236 | ||
7237 | When defined for floating-point modes, the contents of @samp{op2[i]} | |
7238 | are not interpreted if @samp{op1[i]} is false, just like they would not | |
7239 | be in a normal C @samp{?:} condition. | |
7240 | ||
7241 | Operands 0, 2, and 3 all have mode @var{m}. Operand 1 is a scalar | |
7242 | integer if @var{m} is scalar, otherwise it has the mode returned by | |
7243 | @code{TARGET_VECTORIZE_GET_MASK_MODE}. | |
7244 | ||
7245 | @samp{cond_@var{op}@var{mode}} generally corresponds to a conditional | |
7246 | form of @samp{@var{op}@var{mode}2}. | |
7247 | ||
d77de738 ML |
7248 | @cindex @code{cond_add@var{mode}} instruction pattern |
7249 | @cindex @code{cond_sub@var{mode}} instruction pattern | |
7250 | @cindex @code{cond_mul@var{mode}} instruction pattern | |
7251 | @cindex @code{cond_div@var{mode}} instruction pattern | |
7252 | @cindex @code{cond_udiv@var{mode}} instruction pattern | |
7253 | @cindex @code{cond_mod@var{mode}} instruction pattern | |
7254 | @cindex @code{cond_umod@var{mode}} instruction pattern | |
7255 | @cindex @code{cond_and@var{mode}} instruction pattern | |
7256 | @cindex @code{cond_ior@var{mode}} instruction pattern | |
7257 | @cindex @code{cond_xor@var{mode}} instruction pattern | |
7258 | @cindex @code{cond_smin@var{mode}} instruction pattern | |
7259 | @cindex @code{cond_smax@var{mode}} instruction pattern | |
7260 | @cindex @code{cond_umin@var{mode}} instruction pattern | |
7261 | @cindex @code{cond_umax@var{mode}} instruction pattern | |
7262 | @cindex @code{cond_fmin@var{mode}} instruction pattern | |
7263 | @cindex @code{cond_fmax@var{mode}} instruction pattern | |
7264 | @cindex @code{cond_ashl@var{mode}} instruction pattern | |
7265 | @cindex @code{cond_ashr@var{mode}} instruction pattern | |
7266 | @cindex @code{cond_lshr@var{mode}} instruction pattern | |
7267 | @item @samp{cond_add@var{mode}} | |
7268 | @itemx @samp{cond_sub@var{mode}} | |
7269 | @itemx @samp{cond_mul@var{mode}} | |
7270 | @itemx @samp{cond_div@var{mode}} | |
7271 | @itemx @samp{cond_udiv@var{mode}} | |
7272 | @itemx @samp{cond_mod@var{mode}} | |
7273 | @itemx @samp{cond_umod@var{mode}} | |
7274 | @itemx @samp{cond_and@var{mode}} | |
7275 | @itemx @samp{cond_ior@var{mode}} | |
7276 | @itemx @samp{cond_xor@var{mode}} | |
7277 | @itemx @samp{cond_smin@var{mode}} | |
7278 | @itemx @samp{cond_smax@var{mode}} | |
7279 | @itemx @samp{cond_umin@var{mode}} | |
7280 | @itemx @samp{cond_umax@var{mode}} | |
7281 | @itemx @samp{cond_fmin@var{mode}} | |
7282 | @itemx @samp{cond_fmax@var{mode}} | |
7283 | @itemx @samp{cond_ashl@var{mode}} | |
7284 | @itemx @samp{cond_ashr@var{mode}} | |
7285 | @itemx @samp{cond_lshr@var{mode}} | |
7286 | When operand 1 is true, perform an operation on operands 2 and 3 and | |
7287 | store the result in operand 0, otherwise store operand 4 in operand 0. | |
7288 | The operation works elementwise if the operands are vectors. | |
7289 | ||
7290 | The scalar case is equivalent to: | |
7291 | ||
7292 | @smallexample | |
7293 | op0 = op1 ? op2 @var{op} op3 : op4; | |
7294 | @end smallexample | |
7295 | ||
7296 | while the vector case is equivalent to: | |
7297 | ||
7298 | @smallexample | |
7299 | for (i = 0; i < GET_MODE_NUNITS (@var{m}); i++) | |
7300 | op0[i] = op1[i] ? op2[i] @var{op} op3[i] : op4[i]; | |
7301 | @end smallexample | |
7302 | ||
7303 | where, for example, @var{op} is @code{+} for @samp{cond_add@var{mode}}. | |
7304 | ||
7305 | When defined for floating-point modes, the contents of @samp{op3[i]} | |
7306 | are not interpreted if @samp{op1[i]} is false, just like they would not | |
7307 | be in a normal C @samp{?:} condition. | |
7308 | ||
7309 | Operands 0, 2, 3 and 4 all have mode @var{m}. Operand 1 is a scalar | |
7310 | integer if @var{m} is scalar, otherwise it has the mode returned by | |
7311 | @code{TARGET_VECTORIZE_GET_MASK_MODE}. | |
7312 | ||
7313 | @samp{cond_@var{op}@var{mode}} generally corresponds to a conditional | |
7314 | form of @samp{@var{op}@var{mode}3}. As an exception, the vector forms | |
7315 | of shifts correspond to patterns like @code{vashl@var{mode}3} rather | |
7316 | than patterns like @code{ashl@var{mode}3}. | |
7317 | ||
7318 | @cindex @code{cond_fma@var{mode}} instruction pattern | |
7319 | @cindex @code{cond_fms@var{mode}} instruction pattern | |
7320 | @cindex @code{cond_fnma@var{mode}} instruction pattern | |
7321 | @cindex @code{cond_fnms@var{mode}} instruction pattern | |
7322 | @item @samp{cond_fma@var{mode}} | |
7323 | @itemx @samp{cond_fms@var{mode}} | |
7324 | @itemx @samp{cond_fnma@var{mode}} | |
7325 | @itemx @samp{cond_fnms@var{mode}} | |
7326 | Like @samp{cond_add@var{m}}, except that the conditional operation | |
7327 | takes 3 operands rather than two. For example, the vector form of | |
7328 | @samp{cond_fma@var{mode}} is equivalent to: | |
7329 | ||
7330 | @smallexample | |
7331 | for (i = 0; i < GET_MODE_NUNITS (@var{m}); i++) | |
7332 | op0[i] = op1[i] ? fma (op2[i], op3[i], op4[i]) : op5[i]; | |
7333 | @end smallexample | |
7334 | ||
3064471b AP |
7335 | @cindex @code{cond_len_neg@var{mode}} instruction pattern |
7336 | @cindex @code{cond_len_one_cmpl@var{mode}} instruction pattern | |
7337 | @item @samp{cond_len_neg@var{mode}} | |
7338 | @itemx @samp{cond_len_one_cmpl@var{mode}} | |
7339 | When operand 1 is true and element index < operand 4 + operand 5, perform an operation on operands 1 and | |
7340 | store the result in operand 0, otherwise store operand 2 in operand 0. | |
7341 | The operation only works for the operands are vectors. | |
7342 | ||
7343 | @smallexample | |
7344 | for (i = 0; i < ops[4] + ops[5]; i++) | |
7345 | op0[i] = op1[i] ? @var{op} op2[i] : op3[i]; | |
7346 | @end smallexample | |
7347 | ||
7348 | where, for example, @var{op} is @code{~} for @samp{cond_len_one_cmpl@var{mode}}. | |
7349 | ||
7350 | When defined for floating-point modes, the contents of @samp{op2[i]} | |
7351 | are not interpreted if @samp{op1[i]} is false, just like they would not | |
7352 | be in a normal C @samp{?:} condition. | |
7353 | ||
7354 | Operands 0, 2, and 3 all have mode @var{m}. Operand 1 is a scalar | |
7355 | integer if @var{m} is scalar, otherwise it has the mode returned by | |
7356 | @code{TARGET_VECTORIZE_GET_MASK_MODE}. Operand 4 has whichever | |
7357 | integer mode the target prefers. | |
7358 | ||
7359 | @samp{cond_len_@var{op}@var{mode}} generally corresponds to a conditional | |
7360 | form of @samp{@var{op}@var{mode}2}. | |
7361 | ||
7362 | ||
6c96d1e4 JZZ |
7363 | @cindex @code{cond_len_add@var{mode}} instruction pattern |
7364 | @cindex @code{cond_len_sub@var{mode}} instruction pattern | |
7365 | @cindex @code{cond_len_mul@var{mode}} instruction pattern | |
7366 | @cindex @code{cond_len_div@var{mode}} instruction pattern | |
7367 | @cindex @code{cond_len_udiv@var{mode}} instruction pattern | |
7368 | @cindex @code{cond_len_mod@var{mode}} instruction pattern | |
7369 | @cindex @code{cond_len_umod@var{mode}} instruction pattern | |
7370 | @cindex @code{cond_len_and@var{mode}} instruction pattern | |
7371 | @cindex @code{cond_len_ior@var{mode}} instruction pattern | |
7372 | @cindex @code{cond_len_xor@var{mode}} instruction pattern | |
7373 | @cindex @code{cond_len_smin@var{mode}} instruction pattern | |
7374 | @cindex @code{cond_len_smax@var{mode}} instruction pattern | |
7375 | @cindex @code{cond_len_umin@var{mode}} instruction pattern | |
7376 | @cindex @code{cond_len_umax@var{mode}} instruction pattern | |
7377 | @cindex @code{cond_len_fmin@var{mode}} instruction pattern | |
7378 | @cindex @code{cond_len_fmax@var{mode}} instruction pattern | |
7379 | @cindex @code{cond_len_ashl@var{mode}} instruction pattern | |
7380 | @cindex @code{cond_len_ashr@var{mode}} instruction pattern | |
7381 | @cindex @code{cond_len_lshr@var{mode}} instruction pattern | |
7382 | @item @samp{cond_len_add@var{mode}} | |
7383 | @itemx @samp{cond_len_sub@var{mode}} | |
7384 | @itemx @samp{cond_len_mul@var{mode}} | |
7385 | @itemx @samp{cond_len_div@var{mode}} | |
7386 | @itemx @samp{cond_len_udiv@var{mode}} | |
7387 | @itemx @samp{cond_len_mod@var{mode}} | |
7388 | @itemx @samp{cond_len_umod@var{mode}} | |
7389 | @itemx @samp{cond_len_and@var{mode}} | |
7390 | @itemx @samp{cond_len_ior@var{mode}} | |
7391 | @itemx @samp{cond_len_xor@var{mode}} | |
7392 | @itemx @samp{cond_len_smin@var{mode}} | |
7393 | @itemx @samp{cond_len_smax@var{mode}} | |
7394 | @itemx @samp{cond_len_umin@var{mode}} | |
7395 | @itemx @samp{cond_len_umax@var{mode}} | |
7396 | @itemx @samp{cond_len_fmin@var{mode}} | |
7397 | @itemx @samp{cond_len_fmax@var{mode}} | |
7398 | @itemx @samp{cond_len_ashl@var{mode}} | |
7399 | @itemx @samp{cond_len_ashr@var{mode}} | |
7400 | @itemx @samp{cond_len_lshr@var{mode}} | |
7401 | When operand 1 is true and element index < operand 5 + operand 6, perform an operation on operands 2 and 3 and | |
7402 | store the result in operand 0, otherwise store operand 4 in operand 0. | |
7403 | The operation only works for the operands are vectors. | |
7404 | ||
7405 | @smallexample | |
7406 | for (i = 0; i < ops[5] + ops[6]; i++) | |
7407 | op0[i] = op1[i] ? op2[i] @var{op} op3[i] : op4[i]; | |
7408 | @end smallexample | |
7409 | ||
7410 | where, for example, @var{op} is @code{+} for @samp{cond_len_add@var{mode}}. | |
7411 | ||
7412 | When defined for floating-point modes, the contents of @samp{op3[i]} | |
7413 | are not interpreted if @samp{op1[i]} is false, just like they would not | |
7414 | be in a normal C @samp{?:} condition. | |
7415 | ||
7416 | Operands 0, 2, 3 and 4 all have mode @var{m}. Operand 1 is a scalar | |
7417 | integer if @var{m} is scalar, otherwise it has the mode returned by | |
7418 | @code{TARGET_VECTORIZE_GET_MASK_MODE}. Operand 5 has whichever | |
7419 | integer mode the target prefers. | |
7420 | ||
7421 | @samp{cond_@var{op}@var{mode}} generally corresponds to a conditional | |
7422 | form of @samp{@var{op}@var{mode}3}. As an exception, the vector forms | |
7423 | of shifts correspond to patterns like @code{vashl@var{mode}3} rather | |
7424 | than patterns like @code{ashl@var{mode}3}. | |
7425 | ||
7426 | @cindex @code{cond_len_fma@var{mode}} instruction pattern | |
7427 | @cindex @code{cond_len_fms@var{mode}} instruction pattern | |
7428 | @cindex @code{cond_len_fnma@var{mode}} instruction pattern | |
7429 | @cindex @code{cond_len_fnms@var{mode}} instruction pattern | |
7430 | @item @samp{cond_len_fma@var{mode}} | |
7431 | @itemx @samp{cond_len_fms@var{mode}} | |
7432 | @itemx @samp{cond_len_fnma@var{mode}} | |
7433 | @itemx @samp{cond_len_fnms@var{mode}} | |
7434 | Like @samp{cond_len_add@var{m}}, except that the conditional operation | |
7435 | takes 3 operands rather than two. For example, the vector form of | |
7436 | @samp{cond_len_fma@var{mode}} is equivalent to: | |
7437 | ||
7438 | @smallexample | |
7439 | for (i = 0; i < ops[6] + ops[7]; i++) | |
7440 | op0[i] = op1[i] ? fma (op2[i], op3[i], op4[i]) : op5[i]; | |
7441 | @end smallexample | |
7442 | ||
d77de738 ML |
7443 | @cindex @code{neg@var{mode}cc} instruction pattern |
7444 | @item @samp{neg@var{mode}cc} | |
7445 | Similar to @samp{mov@var{mode}cc} but for conditional negation. Conditionally | |
7446 | move the negation of operand 2 or the unchanged operand 3 into operand 0 | |
7447 | according to the comparison in operand 1. If the comparison is true, the negation | |
7448 | of operand 2 is moved into operand 0, otherwise operand 3 is moved. | |
7449 | ||
7450 | @cindex @code{not@var{mode}cc} instruction pattern | |
7451 | @item @samp{not@var{mode}cc} | |
7452 | Similar to @samp{neg@var{mode}cc} but for conditional complement. | |
7453 | Conditionally move the bitwise complement of operand 2 or the unchanged | |
7454 | operand 3 into operand 0 according to the comparison in operand 1. | |
7455 | If the comparison is true, the complement of operand 2 is moved into | |
7456 | operand 0, otherwise operand 3 is moved. | |
7457 | ||
7458 | @cindex @code{cstore@var{mode}4} instruction pattern | |
7459 | @item @samp{cstore@var{mode}4} | |
7460 | Store zero or nonzero in operand 0 according to whether a comparison | |
7461 | is true. Operand 1 is a comparison operator. Operand 2 and operand 3 | |
7462 | are the first and second operand of the comparison, respectively. | |
7463 | You specify the mode that operand 0 must have when you write the | |
7464 | @code{match_operand} expression. The compiler automatically sees which | |
7465 | mode you have used and supplies an operand of that mode. | |
7466 | ||
7467 | The value stored for a true condition must have 1 as its low bit, or | |
7468 | else must be negative. Otherwise the instruction is not suitable and | |
7469 | you should omit it from the machine description. You describe to the | |
7470 | compiler exactly which value is stored by defining the macro | |
7471 | @code{STORE_FLAG_VALUE} (@pxref{Misc}). If a description cannot be | |
7472 | found that can be used for all the possible comparison operators, you | |
7473 | should pick one and use a @code{define_expand} to map all results | |
7474 | onto the one you chose. | |
7475 | ||
7476 | These operations may @code{FAIL}, but should do so only in relatively | |
7477 | uncommon cases; if they would @code{FAIL} for common cases involving | |
7478 | integer comparisons, it is best to restrict the predicates to not | |
7479 | allow these operands. Likewise if a given comparison operator will | |
7480 | always fail, independent of the operands (for floating-point modes, the | |
7481 | @code{ordered_comparison_operator} predicate is often useful in this case). | |
7482 | ||
7483 | If this pattern is omitted, the compiler will generate a conditional | |
7484 | branch---for example, it may copy a constant one to the target and branching | |
7485 | around an assignment of zero to the target---or a libcall. If the predicate | |
7486 | for operand 1 only rejects some operators, it will also try reordering the | |
7487 | operands and/or inverting the result value (e.g.@: by an exclusive OR). | |
7488 | These possibilities could be cheaper or equivalent to the instructions | |
7489 | used for the @samp{cstore@var{mode}4} pattern followed by those required | |
7490 | to convert a positive result from @code{STORE_FLAG_VALUE} to 1; in this | |
7491 | case, you can and should make operand 1's predicate reject some operators | |
7492 | in the @samp{cstore@var{mode}4} pattern, or remove the pattern altogether | |
7493 | from the machine description. | |
7494 | ||
dc582d2e TC |
7495 | @cindex @code{tbranch_@var{op}@var{mode}3} instruction pattern |
7496 | @item @samp{tbranch_@var{op}@var{mode}3} | |
7497 | Conditional branch instruction combined with a bit test-and-compare | |
7498 | instruction. Operand 0 is the operand of the comparison. Operand 1 is the bit | |
7499 | position of Operand 1 to test. Operand 3 is the @code{code_label} to jump to. | |
7500 | @var{op} is one of @var{eq} or @var{ne}. | |
7501 | ||
d77de738 ML |
7502 | @cindex @code{cbranch@var{mode}4} instruction pattern |
7503 | @item @samp{cbranch@var{mode}4} | |
7504 | Conditional branch instruction combined with a compare instruction. | |
7505 | Operand 0 is a comparison operator. Operand 1 and operand 2 are the | |
7506 | first and second operands of the comparison, respectively. Operand 3 | |
7507 | is the @code{code_label} to jump to. | |
7508 | ||
7509 | @cindex @code{jump} instruction pattern | |
7510 | @item @samp{jump} | |
7511 | A jump inside a function; an unconditional branch. Operand 0 is the | |
7512 | @code{code_label} to jump to. This pattern name is mandatory on all | |
7513 | machines. | |
7514 | ||
7515 | @cindex @code{call} instruction pattern | |
7516 | @item @samp{call} | |
7517 | Subroutine call instruction returning no value. Operand 0 is the | |
7518 | function to call; operand 1 is the number of bytes of arguments pushed | |
7519 | as a @code{const_int}. Operand 2 is the result of calling the target | |
7520 | hook @code{TARGET_FUNCTION_ARG} with the second argument @code{arg} | |
7521 | yielding true for @code{arg.end_marker_p ()}, in a call after all | |
7522 | parameters have been passed to that hook. By default this is the first | |
7523 | register beyond those used for arguments in the call, or @code{NULL} if | |
7524 | all the argument-registers are used in the call. | |
7525 | ||
7526 | On most machines, operand 2 is not actually stored into the RTL | |
7527 | pattern. It is supplied for the sake of some RISC machines which need | |
7528 | to put this information into the assembler code; they can put it in | |
7529 | the RTL instead of operand 1. | |
7530 | ||
7531 | Operand 0 should be a @code{mem} RTX whose address is the address of the | |
7532 | function. Note, however, that this address can be a @code{symbol_ref} | |
7533 | expression even if it would not be a legitimate memory address on the | |
7534 | target machine. If it is also not a valid argument for a call | |
7535 | instruction, the pattern for this operation should be a | |
7536 | @code{define_expand} (@pxref{Expander Definitions}) that places the | |
7537 | address into a register and uses that register in the call instruction. | |
7538 | ||
7539 | @cindex @code{call_value} instruction pattern | |
7540 | @item @samp{call_value} | |
7541 | Subroutine call instruction returning a value. Operand 0 is the hard | |
7542 | register in which the value is returned. There are three more | |
7543 | operands, the same as the three operands of the @samp{call} | |
7544 | instruction (but with numbers increased by one). | |
7545 | ||
7546 | Subroutines that return @code{BLKmode} objects use the @samp{call} | |
7547 | insn. | |
7548 | ||
7549 | @cindex @code{call_pop} instruction pattern | |
7550 | @cindex @code{call_value_pop} instruction pattern | |
7551 | @item @samp{call_pop}, @samp{call_value_pop} | |
7552 | Similar to @samp{call} and @samp{call_value}, except used if defined and | |
7553 | if @code{RETURN_POPS_ARGS} is nonzero. They should emit a @code{parallel} | |
7554 | that contains both the function call and a @code{set} to indicate the | |
7555 | adjustment made to the frame pointer. | |
7556 | ||
7557 | For machines where @code{RETURN_POPS_ARGS} can be nonzero, the use of these | |
7558 | patterns increases the number of functions for which the frame pointer | |
7559 | can be eliminated, if desired. | |
7560 | ||
7561 | @cindex @code{untyped_call} instruction pattern | |
7562 | @item @samp{untyped_call} | |
7563 | Subroutine call instruction returning a value of any type. Operand 0 is | |
7564 | the function to call; operand 1 is a memory location where the result of | |
7565 | calling the function is to be stored; operand 2 is a @code{parallel} | |
7566 | expression where each element is a @code{set} expression that indicates | |
7567 | the saving of a function return value into the result block. | |
7568 | ||
7569 | This instruction pattern should be defined to support | |
7570 | @code{__builtin_apply} on machines where special instructions are needed | |
7571 | to call a subroutine with arbitrary arguments or to save the value | |
7572 | returned. This instruction pattern is required on machines that have | |
7573 | multiple registers that can hold a return value | |
7574 | (i.e.@: @code{FUNCTION_VALUE_REGNO_P} is true for more than one register). | |
7575 | ||
7576 | @cindex @code{return} instruction pattern | |
7577 | @item @samp{return} | |
7578 | Subroutine return instruction. This instruction pattern name should be | |
7579 | defined only if a single instruction can do all the work of returning | |
7580 | from a function. | |
7581 | ||
7582 | Like the @samp{mov@var{m}} patterns, this pattern is also used after the | |
7583 | RTL generation phase. In this case it is to support machines where | |
7584 | multiple instructions are usually needed to return from a function, but | |
7585 | some class of functions only requires one instruction to implement a | |
7586 | return. Normally, the applicable functions are those which do not need | |
7587 | to save any registers or allocate stack space. | |
7588 | ||
7589 | It is valid for this pattern to expand to an instruction using | |
7590 | @code{simple_return} if no epilogue is required. | |
7591 | ||
7592 | @cindex @code{simple_return} instruction pattern | |
7593 | @item @samp{simple_return} | |
7594 | Subroutine return instruction. This instruction pattern name should be | |
7595 | defined only if a single instruction can do all the work of returning | |
7596 | from a function on a path where no epilogue is required. This pattern | |
7597 | is very similar to the @code{return} instruction pattern, but it is emitted | |
7598 | only by the shrink-wrapping optimization on paths where the function | |
7599 | prologue has not been executed, and a function return should occur without | |
7600 | any of the effects of the epilogue. Additional uses may be introduced on | |
7601 | paths where both the prologue and the epilogue have executed. | |
7602 | ||
7603 | @findex reload_completed | |
7604 | @findex leaf_function_p | |
7605 | For such machines, the condition specified in this pattern should only | |
7606 | be true when @code{reload_completed} is nonzero and the function's | |
7607 | epilogue would only be a single instruction. For machines with register | |
7608 | windows, the routine @code{leaf_function_p} may be used to determine if | |
7609 | a register window push is required. | |
7610 | ||
7611 | Machines that have conditional return instructions should define patterns | |
7612 | such as | |
7613 | ||
7614 | @smallexample | |
7615 | (define_insn "" | |
7616 | [(set (pc) | |
7617 | (if_then_else (match_operator | |
7618 | 0 "comparison_operator" | |
7619 | [(reg:CC CC_REG) (const_int 0)]) | |
7620 | (return) | |
7621 | (pc)))] | |
7622 | "@var{condition}" | |
7623 | "@dots{}") | |
7624 | @end smallexample | |
7625 | ||
7626 | where @var{condition} would normally be the same condition specified on the | |
7627 | named @samp{return} pattern. | |
7628 | ||
7629 | @cindex @code{untyped_return} instruction pattern | |
7630 | @item @samp{untyped_return} | |
7631 | Untyped subroutine return instruction. This instruction pattern should | |
7632 | be defined to support @code{__builtin_return} on machines where special | |
7633 | instructions are needed to return a value of any type. | |
7634 | ||
7635 | Operand 0 is a memory location where the result of calling a function | |
7636 | with @code{__builtin_apply} is stored; operand 1 is a @code{parallel} | |
7637 | expression where each element is a @code{set} expression that indicates | |
7638 | the restoring of a function return value from the result block. | |
7639 | ||
7640 | @cindex @code{nop} instruction pattern | |
7641 | @item @samp{nop} | |
7642 | No-op instruction. This instruction pattern name should always be defined | |
7643 | to output a no-op in assembler code. @code{(const_int 0)} will do as an | |
7644 | RTL pattern. | |
7645 | ||
7646 | @cindex @code{indirect_jump} instruction pattern | |
7647 | @item @samp{indirect_jump} | |
7648 | An instruction to jump to an address which is operand zero. | |
7649 | This pattern name is mandatory on all machines. | |
7650 | ||
7651 | @cindex @code{casesi} instruction pattern | |
7652 | @item @samp{casesi} | |
7653 | Instruction to jump through a dispatch table, including bounds checking. | |
7654 | This instruction takes five operands: | |
7655 | ||
7656 | @enumerate | |
7657 | @item | |
7658 | The index to dispatch on, which has mode @code{SImode}. | |
7659 | ||
7660 | @item | |
7661 | The lower bound for indices in the table, an integer constant. | |
7662 | ||
7663 | @item | |
7664 | The total range of indices in the table---the largest index | |
7665 | minus the smallest one (both inclusive). | |
7666 | ||
7667 | @item | |
7668 | A label that precedes the table itself. | |
7669 | ||
7670 | @item | |
7671 | A label to jump to if the index has a value outside the bounds. | |
7672 | @end enumerate | |
7673 | ||
7674 | The table is an @code{addr_vec} or @code{addr_diff_vec} inside of a | |
7675 | @code{jump_table_data}. The number of elements in the table is one plus the | |
7676 | difference between the upper bound and the lower bound. | |
7677 | ||
7678 | @cindex @code{tablejump} instruction pattern | |
7679 | @item @samp{tablejump} | |
7680 | Instruction to jump to a variable address. This is a low-level | |
7681 | capability which can be used to implement a dispatch table when there | |
7682 | is no @samp{casesi} pattern. | |
7683 | ||
7684 | This pattern requires two operands: the address or offset, and a label | |
7685 | which should immediately precede the jump table. If the macro | |
7686 | @code{CASE_VECTOR_PC_RELATIVE} evaluates to a nonzero value then the first | |
7687 | operand is an offset which counts from the address of the table; otherwise, | |
7688 | it is an absolute address to jump to. In either case, the first operand has | |
7689 | mode @code{Pmode}. | |
7690 | ||
7691 | The @samp{tablejump} insn is always the last insn before the jump | |
7692 | table it uses. Its assembler code normally has no need to use the | |
7693 | second operand, but you should incorporate it in the RTL pattern so | |
7694 | that the jump optimizer will not delete the table as unreachable code. | |
7695 | ||
7696 | ||
7697 | @cindex @code{doloop_end} instruction pattern | |
7698 | @item @samp{doloop_end} | |
7699 | Conditional branch instruction that decrements a register and | |
7700 | jumps if the register is nonzero. Operand 0 is the register to | |
7701 | decrement and test; operand 1 is the label to jump to if the | |
7702 | register is nonzero. | |
7703 | @xref{Looping Patterns}. | |
7704 | ||
7705 | This optional instruction pattern should be defined for machines with | |
7706 | low-overhead looping instructions as the loop optimizer will try to | |
7707 | modify suitable loops to utilize it. The target hook | |
7708 | @code{TARGET_CAN_USE_DOLOOP_P} controls the conditions under which | |
7709 | low-overhead loops can be used. | |
7710 | ||
7711 | @cindex @code{doloop_begin} instruction pattern | |
7712 | @item @samp{doloop_begin} | |
7713 | Companion instruction to @code{doloop_end} required for machines that | |
7714 | need to perform some initialization, such as loading a special counter | |
7715 | register. Operand 1 is the associated @code{doloop_end} pattern and | |
7716 | operand 0 is the register that it decrements. | |
7717 | ||
7718 | If initialization insns do not always need to be emitted, use a | |
7719 | @code{define_expand} (@pxref{Expander Definitions}) and make it fail. | |
7720 | ||
7721 | @cindex @code{canonicalize_funcptr_for_compare} instruction pattern | |
7722 | @item @samp{canonicalize_funcptr_for_compare} | |
7723 | Canonicalize the function pointer in operand 1 and store the result | |
7724 | into operand 0. | |
7725 | ||
7726 | Operand 0 is always a @code{reg} and has mode @code{Pmode}; operand 1 | |
7727 | may be a @code{reg}, @code{mem}, @code{symbol_ref}, @code{const_int}, etc | |
7728 | and also has mode @code{Pmode}. | |
7729 | ||
7730 | Canonicalization of a function pointer usually involves computing | |
7731 | the address of the function which would be called if the function | |
7732 | pointer were used in an indirect call. | |
7733 | ||
7734 | Only define this pattern if function pointers on the target machine | |
7735 | can have different values but still call the same function when | |
7736 | used in an indirect call. | |
7737 | ||
7738 | @cindex @code{save_stack_block} instruction pattern | |
7739 | @cindex @code{save_stack_function} instruction pattern | |
7740 | @cindex @code{save_stack_nonlocal} instruction pattern | |
7741 | @cindex @code{restore_stack_block} instruction pattern | |
7742 | @cindex @code{restore_stack_function} instruction pattern | |
7743 | @cindex @code{restore_stack_nonlocal} instruction pattern | |
7744 | @item @samp{save_stack_block} | |
7745 | @itemx @samp{save_stack_function} | |
7746 | @itemx @samp{save_stack_nonlocal} | |
7747 | @itemx @samp{restore_stack_block} | |
7748 | @itemx @samp{restore_stack_function} | |
7749 | @itemx @samp{restore_stack_nonlocal} | |
7750 | Most machines save and restore the stack pointer by copying it to or | |
7751 | from an object of mode @code{Pmode}. Do not define these patterns on | |
7752 | such machines. | |
7753 | ||
7754 | Some machines require special handling for stack pointer saves and | |
7755 | restores. On those machines, define the patterns corresponding to the | |
7756 | non-standard cases by using a @code{define_expand} (@pxref{Expander | |
7757 | Definitions}) that produces the required insns. The three types of | |
7758 | saves and restores are: | |
7759 | ||
7760 | @enumerate | |
7761 | @item | |
7762 | @samp{save_stack_block} saves the stack pointer at the start of a block | |
7763 | that allocates a variable-sized object, and @samp{restore_stack_block} | |
7764 | restores the stack pointer when the block is exited. | |
7765 | ||
7766 | @item | |
7767 | @samp{save_stack_function} and @samp{restore_stack_function} do a | |
7768 | similar job for the outermost block of a function and are used when the | |
7769 | function allocates variable-sized objects or calls @code{alloca}. Only | |
7770 | the epilogue uses the restored stack pointer, allowing a simpler save or | |
7771 | restore sequence on some machines. | |
7772 | ||
7773 | @item | |
7774 | @samp{save_stack_nonlocal} is used in functions that contain labels | |
7775 | branched to by nested functions. It saves the stack pointer in such a | |
7776 | way that the inner function can use @samp{restore_stack_nonlocal} to | |
7777 | restore the stack pointer. The compiler generates code to restore the | |
7778 | frame and argument pointer registers, but some machines require saving | |
7779 | and restoring additional data such as register window information or | |
7780 | stack backchains. Place insns in these patterns to save and restore any | |
7781 | such required data. | |
7782 | @end enumerate | |
7783 | ||
7784 | When saving the stack pointer, operand 0 is the save area and operand 1 | |
7785 | is the stack pointer. The mode used to allocate the save area defaults | |
7786 | to @code{Pmode} but you can override that choice by defining the | |
7787 | @code{STACK_SAVEAREA_MODE} macro (@pxref{Storage Layout}). You must | |
7788 | specify an integral mode, or @code{VOIDmode} if no save area is needed | |
7789 | for a particular type of save (either because no save is needed or | |
7790 | because a machine-specific save area can be used). Operand 0 is the | |
7791 | stack pointer and operand 1 is the save area for restore operations. If | |
7792 | @samp{save_stack_block} is defined, operand 0 must not be | |
7793 | @code{VOIDmode} since these saves can be arbitrarily nested. | |
7794 | ||
7795 | A save area is a @code{mem} that is at a constant offset from | |
7796 | @code{virtual_stack_vars_rtx} when the stack pointer is saved for use by | |
7797 | nonlocal gotos and a @code{reg} in the other two cases. | |
7798 | ||
7799 | @cindex @code{allocate_stack} instruction pattern | |
7800 | @item @samp{allocate_stack} | |
7801 | Subtract (or add if @code{STACK_GROWS_DOWNWARD} is undefined) operand 1 from | |
7802 | the stack pointer to create space for dynamically allocated data. | |
7803 | ||
7804 | Store the resultant pointer to this space into operand 0. If you | |
7805 | are allocating space from the main stack, do this by emitting a | |
7806 | move insn to copy @code{virtual_stack_dynamic_rtx} to operand 0. | |
7807 | If you are allocating the space elsewhere, generate code to copy the | |
7808 | location of the space to operand 0. In the latter case, you must | |
7809 | ensure this space gets freed when the corresponding space on the main | |
7810 | stack is free. | |
7811 | ||
7812 | Do not define this pattern if all that must be done is the subtraction. | |
7813 | Some machines require other operations such as stack probes or | |
7814 | maintaining the back chain. Define this pattern to emit those | |
7815 | operations in addition to updating the stack pointer. | |
7816 | ||
7817 | @cindex @code{check_stack} instruction pattern | |
7818 | @item @samp{check_stack} | |
7819 | If stack checking (@pxref{Stack Checking}) cannot be done on your system by | |
7820 | probing the stack, define this pattern to perform the needed check and signal | |
7821 | an error if the stack has overflowed. The single operand is the address in | |
7822 | the stack farthest from the current stack pointer that you need to validate. | |
7823 | Normally, on platforms where this pattern is needed, you would obtain the | |
7824 | stack limit from a global or thread-specific variable or register. | |
7825 | ||
7826 | @cindex @code{probe_stack_address} instruction pattern | |
7827 | @item @samp{probe_stack_address} | |
7828 | If stack checking (@pxref{Stack Checking}) can be done on your system by | |
7829 | probing the stack but without the need to actually access it, define this | |
7830 | pattern and signal an error if the stack has overflowed. The single operand | |
7831 | is the memory address in the stack that needs to be probed. | |
7832 | ||
7833 | @cindex @code{probe_stack} instruction pattern | |
7834 | @item @samp{probe_stack} | |
7835 | If stack checking (@pxref{Stack Checking}) can be done on your system by | |
7836 | probing the stack but doing it with a ``store zero'' instruction is not valid | |
7837 | or optimal, define this pattern to do the probing differently and signal an | |
7838 | error if the stack has overflowed. The single operand is the memory reference | |
7839 | in the stack that needs to be probed. | |
7840 | ||
7841 | @cindex @code{nonlocal_goto} instruction pattern | |
7842 | @item @samp{nonlocal_goto} | |
7843 | Emit code to generate a non-local goto, e.g., a jump from one function | |
7844 | to a label in an outer function. This pattern has four arguments, | |
7845 | each representing a value to be used in the jump. The first | |
7846 | argument is to be loaded into the frame pointer, the second is | |
7847 | the address to branch to (code to dispatch to the actual label), | |
7848 | the third is the address of a location where the stack is saved, | |
7849 | and the last is the address of the label, to be placed in the | |
7850 | location for the incoming static chain. | |
7851 | ||
7852 | On most machines you need not define this pattern, since GCC will | |
7853 | already generate the correct code, which is to load the frame pointer | |
7854 | and static chain, restore the stack (using the | |
7855 | @samp{restore_stack_nonlocal} pattern, if defined), and jump indirectly | |
7856 | to the dispatcher. You need only define this pattern if this code will | |
7857 | not work on your machine. | |
7858 | ||
7859 | @cindex @code{nonlocal_goto_receiver} instruction pattern | |
7860 | @item @samp{nonlocal_goto_receiver} | |
7861 | This pattern, if defined, contains code needed at the target of a | |
7862 | nonlocal goto after the code already generated by GCC@. You will not | |
7863 | normally need to define this pattern. A typical reason why you might | |
7864 | need this pattern is if some value, such as a pointer to a global table, | |
7865 | must be restored when the frame pointer is restored. Note that a nonlocal | |
7866 | goto only occurs within a unit-of-translation, so a global table pointer | |
7867 | that is shared by all functions of a given module need not be restored. | |
7868 | There are no arguments. | |
7869 | ||
7870 | @cindex @code{exception_receiver} instruction pattern | |
7871 | @item @samp{exception_receiver} | |
7872 | This pattern, if defined, contains code needed at the site of an | |
7873 | exception handler that isn't needed at the site of a nonlocal goto. You | |
7874 | will not normally need to define this pattern. A typical reason why you | |
7875 | might need this pattern is if some value, such as a pointer to a global | |
7876 | table, must be restored after control flow is branched to the handler of | |
7877 | an exception. There are no arguments. | |
7878 | ||
7879 | @cindex @code{builtin_setjmp_setup} instruction pattern | |
7880 | @item @samp{builtin_setjmp_setup} | |
7881 | This pattern, if defined, contains additional code needed to initialize | |
7882 | the @code{jmp_buf}. You will not normally need to define this pattern. | |
7883 | A typical reason why you might need this pattern is if some value, such | |
7884 | as a pointer to a global table, must be restored. Though it is | |
7885 | preferred that the pointer value be recalculated if possible (given the | |
7886 | address of a label for instance). The single argument is a pointer to | |
7887 | the @code{jmp_buf}. Note that the buffer is five words long and that | |
7888 | the first three are normally used by the generic mechanism. | |
7889 | ||
7890 | @cindex @code{builtin_setjmp_receiver} instruction pattern | |
7891 | @item @samp{builtin_setjmp_receiver} | |
7892 | This pattern, if defined, contains code needed at the site of a | |
7893 | built-in setjmp that isn't needed at the site of a nonlocal goto. You | |
7894 | will not normally need to define this pattern. A typical reason why you | |
7895 | might need this pattern is if some value, such as a pointer to a global | |
7896 | table, must be restored. It takes one argument, which is the label | |
7897 | to which builtin_longjmp transferred control; this pattern may be emitted | |
7898 | at a small offset from that label. | |
7899 | ||
7900 | @cindex @code{builtin_longjmp} instruction pattern | |
7901 | @item @samp{builtin_longjmp} | |
7902 | This pattern, if defined, performs the entire action of the longjmp. | |
7903 | You will not normally need to define this pattern unless you also define | |
7904 | @code{builtin_setjmp_setup}. The single argument is a pointer to the | |
7905 | @code{jmp_buf}. | |
7906 | ||
7907 | @cindex @code{eh_return} instruction pattern | |
7908 | @item @samp{eh_return} | |
7909 | This pattern, if defined, affects the way @code{__builtin_eh_return}, | |
7910 | and thence the call frame exception handling library routines, are | |
7911 | built. It is intended to handle non-trivial actions needed along | |
7912 | the abnormal return path. | |
7913 | ||
7914 | The address of the exception handler to which the function should return | |
7915 | is passed as operand to this pattern. It will normally need to copied by | |
7916 | the pattern to some special register or memory location. | |
7917 | If the pattern needs to determine the location of the target call | |
7918 | frame in order to do so, it may use @code{EH_RETURN_STACKADJ_RTX}, | |
7919 | if defined; it will have already been assigned. | |
7920 | ||
7921 | If this pattern is not defined, the default action will be to simply | |
7922 | copy the return address to @code{EH_RETURN_HANDLER_RTX}. Either | |
7923 | that macro or this pattern needs to be defined if call frame exception | |
7924 | handling is to be used. | |
7925 | ||
7926 | @cindex @code{prologue} instruction pattern | |
7927 | @anchor{prologue instruction pattern} | |
7928 | @item @samp{prologue} | |
7929 | This pattern, if defined, emits RTL for entry to a function. The function | |
7930 | entry is responsible for setting up the stack frame, initializing the frame | |
7931 | pointer register, saving callee saved registers, etc. | |
7932 | ||
7933 | Using a prologue pattern is generally preferred over defining | |
7934 | @code{TARGET_ASM_FUNCTION_PROLOGUE} to emit assembly code for the prologue. | |
7935 | ||
7936 | The @code{prologue} pattern is particularly useful for targets which perform | |
7937 | instruction scheduling. | |
7938 | ||
7939 | @cindex @code{window_save} instruction pattern | |
7940 | @anchor{window_save instruction pattern} | |
7941 | @item @samp{window_save} | |
7942 | This pattern, if defined, emits RTL for a register window save. It should | |
7943 | be defined if the target machine has register windows but the window events | |
7944 | are decoupled from calls to subroutines. The canonical example is the SPARC | |
7945 | architecture. | |
7946 | ||
7947 | @cindex @code{epilogue} instruction pattern | |
7948 | @anchor{epilogue instruction pattern} | |
7949 | @item @samp{epilogue} | |
7950 | This pattern emits RTL for exit from a function. The function | |
7951 | exit is responsible for deallocating the stack frame, restoring callee saved | |
7952 | registers and emitting the return instruction. | |
7953 | ||
7954 | Using an epilogue pattern is generally preferred over defining | |
7955 | @code{TARGET_ASM_FUNCTION_EPILOGUE} to emit assembly code for the epilogue. | |
7956 | ||
7957 | The @code{epilogue} pattern is particularly useful for targets which perform | |
7958 | instruction scheduling or which have delay slots for their return instruction. | |
7959 | ||
7960 | @cindex @code{sibcall_epilogue} instruction pattern | |
7961 | @item @samp{sibcall_epilogue} | |
7962 | This pattern, if defined, emits RTL for exit from a function without the final | |
7963 | branch back to the calling function. This pattern will be emitted before any | |
7964 | sibling call (aka tail call) sites. | |
7965 | ||
7966 | The @code{sibcall_epilogue} pattern must not clobber any arguments used for | |
7967 | parameter passing or any stack slots for arguments passed to the current | |
7968 | function. | |
7969 | ||
7970 | @cindex @code{trap} instruction pattern | |
7971 | @item @samp{trap} | |
7972 | This pattern, if defined, signals an error, typically by causing some | |
7973 | kind of signal to be raised. | |
7974 | ||
7975 | @cindex @code{ctrap@var{MM}4} instruction pattern | |
7976 | @item @samp{ctrap@var{MM}4} | |
7977 | Conditional trap instruction. Operand 0 is a piece of RTL which | |
7978 | performs a comparison, and operands 1 and 2 are the arms of the | |
7979 | comparison. Operand 3 is the trap code, an integer. | |
7980 | ||
7981 | A typical @code{ctrap} pattern looks like | |
7982 | ||
7983 | @smallexample | |
7984 | (define_insn "ctrapsi4" | |
7985 | [(trap_if (match_operator 0 "trap_operator" | |
7986 | [(match_operand 1 "register_operand") | |
7987 | (match_operand 2 "immediate_operand")]) | |
7988 | (match_operand 3 "const_int_operand" "i"))] | |
7989 | "" | |
7990 | "@dots{}") | |
7991 | @end smallexample | |
7992 | ||
7993 | @cindex @code{prefetch} instruction pattern | |
7994 | @item @samp{prefetch} | |
7995 | This pattern, if defined, emits code for a non-faulting data prefetch | |
7996 | instruction. Operand 0 is the address of the memory to prefetch. Operand 1 | |
7997 | is a constant 1 if the prefetch is preparing for a write to the memory | |
7998 | address, or a constant 0 otherwise. Operand 2 is the expected degree of | |
7999 | temporal locality of the data and is a value between 0 and 3, inclusive; 0 | |
8000 | means that the data has no temporal locality, so it need not be left in the | |
8001 | cache after the access; 3 means that the data has a high degree of temporal | |
8002 | locality and should be left in all levels of cache possible; 1 and 2 mean, | |
8003 | respectively, a low or moderate degree of temporal locality. | |
8004 | ||
8005 | Targets that do not support write prefetches or locality hints can ignore | |
8006 | the values of operands 1 and 2. | |
8007 | ||
8008 | @cindex @code{blockage} instruction pattern | |
8009 | @item @samp{blockage} | |
8010 | This pattern defines a pseudo insn that prevents the instruction | |
8011 | scheduler and other passes from moving instructions and using register | |
8012 | equivalences across the boundary defined by the blockage insn. | |
8013 | This needs to be an UNSPEC_VOLATILE pattern or a volatile ASM. | |
8014 | ||
8015 | @cindex @code{memory_blockage} instruction pattern | |
8016 | @item @samp{memory_blockage} | |
8017 | This pattern, if defined, represents a compiler memory barrier, and will be | |
8018 | placed at points across which RTL passes may not propagate memory accesses. | |
8019 | This instruction needs to read and write volatile BLKmode memory. It does | |
8020 | not need to generate any machine instruction. If this pattern is not defined, | |
8021 | the compiler falls back to emitting an instruction corresponding | |
8022 | to @code{asm volatile ("" ::: "memory")}. | |
8023 | ||
8024 | @cindex @code{memory_barrier} instruction pattern | |
8025 | @item @samp{memory_barrier} | |
8026 | If the target memory model is not fully synchronous, then this pattern | |
8027 | should be defined to an instruction that orders both loads and stores | |
8028 | before the instruction with respect to loads and stores after the instruction. | |
8029 | This pattern has no operands. | |
8030 | ||
8031 | @cindex @code{speculation_barrier} instruction pattern | |
8032 | @item @samp{speculation_barrier} | |
8033 | If the target can support speculative execution, then this pattern should | |
8034 | be defined to an instruction that will block subsequent execution until | |
8035 | any prior speculation conditions has been resolved. The pattern must also | |
8036 | ensure that the compiler cannot move memory operations past the barrier, | |
8037 | so it needs to be an UNSPEC_VOLATILE pattern. The pattern has no | |
8038 | operands. | |
8039 | ||
8040 | If this pattern is not defined then the default expansion of | |
8041 | @code{__builtin_speculation_safe_value} will emit a warning. You can | |
8042 | suppress this warning by defining this pattern with a final condition | |
8043 | of @code{0} (zero), which tells the compiler that a speculation | |
8044 | barrier is not needed for this target. | |
8045 | ||
8046 | @cindex @code{sync_compare_and_swap@var{mode}} instruction pattern | |
8047 | @item @samp{sync_compare_and_swap@var{mode}} | |
8048 | This pattern, if defined, emits code for an atomic compare-and-swap | |
8049 | operation. Operand 1 is the memory on which the atomic operation is | |
8050 | performed. Operand 2 is the ``old'' value to be compared against the | |
8051 | current contents of the memory location. Operand 3 is the ``new'' value | |
8052 | to store in the memory if the compare succeeds. Operand 0 is the result | |
8053 | of the operation; it should contain the contents of the memory | |
8054 | before the operation. If the compare succeeds, this should obviously be | |
8055 | a copy of operand 2. | |
8056 | ||
8057 | This pattern must show that both operand 0 and operand 1 are modified. | |
8058 | ||
8059 | This pattern must issue any memory barrier instructions such that all | |
8060 | memory operations before the atomic operation occur before the atomic | |
8061 | operation and all memory operations after the atomic operation occur | |
8062 | after the atomic operation. | |
8063 | ||
8064 | For targets where the success or failure of the compare-and-swap | |
8065 | operation is available via the status flags, it is possible to | |
8066 | avoid a separate compare operation and issue the subsequent | |
8067 | branch or store-flag operation immediately after the compare-and-swap. | |
8068 | To this end, GCC will look for a @code{MODE_CC} set in the | |
8069 | output of @code{sync_compare_and_swap@var{mode}}; if the machine | |
8070 | description includes such a set, the target should also define special | |
8071 | @code{cbranchcc4} and/or @code{cstorecc4} instructions. GCC will then | |
8072 | be able to take the destination of the @code{MODE_CC} set and pass it | |
8073 | to the @code{cbranchcc4} or @code{cstorecc4} pattern as the first | |
8074 | operand of the comparison (the second will be @code{(const_int 0)}). | |
8075 | ||
8076 | For targets where the operating system may provide support for this | |
8077 | operation via library calls, the @code{sync_compare_and_swap_optab} | |
8078 | may be initialized to a function with the same interface as the | |
8079 | @code{__sync_val_compare_and_swap_@var{n}} built-in. If the entire | |
8080 | set of @var{__sync} builtins are supported via library calls, the | |
8081 | target can initialize all of the optabs at once with | |
8082 | @code{init_sync_libfuncs}. | |
8083 | For the purposes of C++11 @code{std::atomic::is_lock_free}, it is | |
8084 | assumed that these library calls do @emph{not} use any kind of | |
8085 | interruptable locking. | |
8086 | ||
8087 | @cindex @code{sync_add@var{mode}} instruction pattern | |
8088 | @cindex @code{sync_sub@var{mode}} instruction pattern | |
8089 | @cindex @code{sync_ior@var{mode}} instruction pattern | |
8090 | @cindex @code{sync_and@var{mode}} instruction pattern | |
8091 | @cindex @code{sync_xor@var{mode}} instruction pattern | |
8092 | @cindex @code{sync_nand@var{mode}} instruction pattern | |
8093 | @item @samp{sync_add@var{mode}}, @samp{sync_sub@var{mode}} | |
8094 | @itemx @samp{sync_ior@var{mode}}, @samp{sync_and@var{mode}} | |
8095 | @itemx @samp{sync_xor@var{mode}}, @samp{sync_nand@var{mode}} | |
8096 | These patterns emit code for an atomic operation on memory. | |
8097 | Operand 0 is the memory on which the atomic operation is performed. | |
8098 | Operand 1 is the second operand to the binary operator. | |
8099 | ||
8100 | This pattern must issue any memory barrier instructions such that all | |
8101 | memory operations before the atomic operation occur before the atomic | |
8102 | operation and all memory operations after the atomic operation occur | |
8103 | after the atomic operation. | |
8104 | ||
8105 | If these patterns are not defined, the operation will be constructed | |
8106 | from a compare-and-swap operation, if defined. | |
8107 | ||
8108 | @cindex @code{sync_old_add@var{mode}} instruction pattern | |
8109 | @cindex @code{sync_old_sub@var{mode}} instruction pattern | |
8110 | @cindex @code{sync_old_ior@var{mode}} instruction pattern | |
8111 | @cindex @code{sync_old_and@var{mode}} instruction pattern | |
8112 | @cindex @code{sync_old_xor@var{mode}} instruction pattern | |
8113 | @cindex @code{sync_old_nand@var{mode}} instruction pattern | |
8114 | @item @samp{sync_old_add@var{mode}}, @samp{sync_old_sub@var{mode}} | |
8115 | @itemx @samp{sync_old_ior@var{mode}}, @samp{sync_old_and@var{mode}} | |
8116 | @itemx @samp{sync_old_xor@var{mode}}, @samp{sync_old_nand@var{mode}} | |
8117 | These patterns emit code for an atomic operation on memory, | |
8118 | and return the value that the memory contained before the operation. | |
8119 | Operand 0 is the result value, operand 1 is the memory on which the | |
8120 | atomic operation is performed, and operand 2 is the second operand | |
8121 | to the binary operator. | |
8122 | ||
8123 | This pattern must issue any memory barrier instructions such that all | |
8124 | memory operations before the atomic operation occur before the atomic | |
8125 | operation and all memory operations after the atomic operation occur | |
8126 | after the atomic operation. | |
8127 | ||
8128 | If these patterns are not defined, the operation will be constructed | |
8129 | from a compare-and-swap operation, if defined. | |
8130 | ||
8131 | @cindex @code{sync_new_add@var{mode}} instruction pattern | |
8132 | @cindex @code{sync_new_sub@var{mode}} instruction pattern | |
8133 | @cindex @code{sync_new_ior@var{mode}} instruction pattern | |
8134 | @cindex @code{sync_new_and@var{mode}} instruction pattern | |
8135 | @cindex @code{sync_new_xor@var{mode}} instruction pattern | |
8136 | @cindex @code{sync_new_nand@var{mode}} instruction pattern | |
8137 | @item @samp{sync_new_add@var{mode}}, @samp{sync_new_sub@var{mode}} | |
8138 | @itemx @samp{sync_new_ior@var{mode}}, @samp{sync_new_and@var{mode}} | |
8139 | @itemx @samp{sync_new_xor@var{mode}}, @samp{sync_new_nand@var{mode}} | |
8140 | These patterns are like their @code{sync_old_@var{op}} counterparts, | |
8141 | except that they return the value that exists in the memory location | |
8142 | after the operation, rather than before the operation. | |
8143 | ||
8144 | @cindex @code{sync_lock_test_and_set@var{mode}} instruction pattern | |
8145 | @item @samp{sync_lock_test_and_set@var{mode}} | |
8146 | This pattern takes two forms, based on the capabilities of the target. | |
8147 | In either case, operand 0 is the result of the operand, operand 1 is | |
8148 | the memory on which the atomic operation is performed, and operand 2 | |
8149 | is the value to set in the lock. | |
8150 | ||
8151 | In the ideal case, this operation is an atomic exchange operation, in | |
8152 | which the previous value in memory operand is copied into the result | |
8153 | operand, and the value operand is stored in the memory operand. | |
8154 | ||
8155 | For less capable targets, any value operand that is not the constant 1 | |
8156 | should be rejected with @code{FAIL}. In this case the target may use | |
8157 | an atomic test-and-set bit operation. The result operand should contain | |
8158 | 1 if the bit was previously set and 0 if the bit was previously clear. | |
8159 | The true contents of the memory operand are implementation defined. | |
8160 | ||
8161 | This pattern must issue any memory barrier instructions such that the | |
8162 | pattern as a whole acts as an acquire barrier, that is all memory | |
8163 | operations after the pattern do not occur until the lock is acquired. | |
8164 | ||
8165 | If this pattern is not defined, the operation will be constructed from | |
8166 | a compare-and-swap operation, if defined. | |
8167 | ||
8168 | @cindex @code{sync_lock_release@var{mode}} instruction pattern | |
8169 | @item @samp{sync_lock_release@var{mode}} | |
8170 | This pattern, if defined, releases a lock set by | |
8171 | @code{sync_lock_test_and_set@var{mode}}. Operand 0 is the memory | |
8172 | that contains the lock; operand 1 is the value to store in the lock. | |
8173 | ||
8174 | If the target doesn't implement full semantics for | |
8175 | @code{sync_lock_test_and_set@var{mode}}, any value operand which is not | |
8176 | the constant 0 should be rejected with @code{FAIL}, and the true contents | |
8177 | of the memory operand are implementation defined. | |
8178 | ||
8179 | This pattern must issue any memory barrier instructions such that the | |
8180 | pattern as a whole acts as a release barrier, that is the lock is | |
8181 | released only after all previous memory operations have completed. | |
8182 | ||
8183 | If this pattern is not defined, then a @code{memory_barrier} pattern | |
8184 | will be emitted, followed by a store of the value to the memory operand. | |
8185 | ||
8186 | @cindex @code{atomic_compare_and_swap@var{mode}} instruction pattern | |
8187 | @item @samp{atomic_compare_and_swap@var{mode}} | |
8188 | This pattern, if defined, emits code for an atomic compare-and-swap | |
8189 | operation with memory model semantics. Operand 2 is the memory on which | |
8190 | the atomic operation is performed. Operand 0 is an output operand which | |
8191 | is set to true or false based on whether the operation succeeded. Operand | |
8192 | 1 is an output operand which is set to the contents of the memory before | |
8193 | the operation was attempted. Operand 3 is the value that is expected to | |
8194 | be in memory. Operand 4 is the value to put in memory if the expected | |
8195 | value is found there. Operand 5 is set to 1 if this compare and swap is to | |
8196 | be treated as a weak operation. Operand 6 is the memory model to be used | |
8197 | if the operation is a success. Operand 7 is the memory model to be used | |
8198 | if the operation fails. | |
8199 | ||
8200 | If memory referred to in operand 2 contains the value in operand 3, then | |
8201 | operand 4 is stored in memory pointed to by operand 2 and fencing based on | |
8202 | the memory model in operand 6 is issued. | |
8203 | ||
8204 | If memory referred to in operand 2 does not contain the value in operand 3, | |
8205 | then fencing based on the memory model in operand 7 is issued. | |
8206 | ||
8207 | If a target does not support weak compare-and-swap operations, or the port | |
8208 | elects not to implement weak operations, the argument in operand 5 can be | |
8209 | ignored. Note a strong implementation must be provided. | |
8210 | ||
8211 | If this pattern is not provided, the @code{__atomic_compare_exchange} | |
8212 | built-in functions will utilize the legacy @code{sync_compare_and_swap} | |
8213 | pattern with an @code{__ATOMIC_SEQ_CST} memory model. | |
8214 | ||
8215 | @cindex @code{atomic_load@var{mode}} instruction pattern | |
8216 | @item @samp{atomic_load@var{mode}} | |
8217 | This pattern implements an atomic load operation with memory model | |
8218 | semantics. Operand 1 is the memory address being loaded from. Operand 0 | |
8219 | is the result of the load. Operand 2 is the memory model to be used for | |
8220 | the load operation. | |
8221 | ||
8222 | If not present, the @code{__atomic_load} built-in function will either | |
8223 | resort to a normal load with memory barriers, or a compare-and-swap | |
8224 | operation if a normal load would not be atomic. | |
8225 | ||
8226 | @cindex @code{atomic_store@var{mode}} instruction pattern | |
8227 | @item @samp{atomic_store@var{mode}} | |
8228 | This pattern implements an atomic store operation with memory model | |
8229 | semantics. Operand 0 is the memory address being stored to. Operand 1 | |
8230 | is the value to be written. Operand 2 is the memory model to be used for | |
8231 | the operation. | |
8232 | ||
8233 | If not present, the @code{__atomic_store} built-in function will attempt to | |
8234 | perform a normal store and surround it with any required memory fences. If | |
8235 | the store would not be atomic, then an @code{__atomic_exchange} is | |
8236 | attempted with the result being ignored. | |
8237 | ||
8238 | @cindex @code{atomic_exchange@var{mode}} instruction pattern | |
8239 | @item @samp{atomic_exchange@var{mode}} | |
8240 | This pattern implements an atomic exchange operation with memory model | |
8241 | semantics. Operand 1 is the memory location the operation is performed on. | |
8242 | Operand 0 is an output operand which is set to the original value contained | |
8243 | in the memory pointed to by operand 1. Operand 2 is the value to be | |
8244 | stored. Operand 3 is the memory model to be used. | |
8245 | ||
8246 | If this pattern is not present, the built-in function | |
8247 | @code{__atomic_exchange} will attempt to preform the operation with a | |
8248 | compare and swap loop. | |
8249 | ||
8250 | @cindex @code{atomic_add@var{mode}} instruction pattern | |
8251 | @cindex @code{atomic_sub@var{mode}} instruction pattern | |
8252 | @cindex @code{atomic_or@var{mode}} instruction pattern | |
8253 | @cindex @code{atomic_and@var{mode}} instruction pattern | |
8254 | @cindex @code{atomic_xor@var{mode}} instruction pattern | |
8255 | @cindex @code{atomic_nand@var{mode}} instruction pattern | |
8256 | @item @samp{atomic_add@var{mode}}, @samp{atomic_sub@var{mode}} | |
8257 | @itemx @samp{atomic_or@var{mode}}, @samp{atomic_and@var{mode}} | |
8258 | @itemx @samp{atomic_xor@var{mode}}, @samp{atomic_nand@var{mode}} | |
8259 | These patterns emit code for an atomic operation on memory with memory | |
8260 | model semantics. Operand 0 is the memory on which the atomic operation is | |
8261 | performed. Operand 1 is the second operand to the binary operator. | |
8262 | Operand 2 is the memory model to be used by the operation. | |
8263 | ||
8264 | If these patterns are not defined, attempts will be made to use legacy | |
8265 | @code{sync} patterns, or equivalent patterns which return a result. If | |
8266 | none of these are available a compare-and-swap loop will be used. | |
8267 | ||
8268 | @cindex @code{atomic_fetch_add@var{mode}} instruction pattern | |
8269 | @cindex @code{atomic_fetch_sub@var{mode}} instruction pattern | |
8270 | @cindex @code{atomic_fetch_or@var{mode}} instruction pattern | |
8271 | @cindex @code{atomic_fetch_and@var{mode}} instruction pattern | |
8272 | @cindex @code{atomic_fetch_xor@var{mode}} instruction pattern | |
8273 | @cindex @code{atomic_fetch_nand@var{mode}} instruction pattern | |
8274 | @item @samp{atomic_fetch_add@var{mode}}, @samp{atomic_fetch_sub@var{mode}} | |
8275 | @itemx @samp{atomic_fetch_or@var{mode}}, @samp{atomic_fetch_and@var{mode}} | |
8276 | @itemx @samp{atomic_fetch_xor@var{mode}}, @samp{atomic_fetch_nand@var{mode}} | |
8277 | These patterns emit code for an atomic operation on memory with memory | |
8278 | model semantics, and return the original value. Operand 0 is an output | |
8279 | operand which contains the value of the memory location before the | |
8280 | operation was performed. Operand 1 is the memory on which the atomic | |
8281 | operation is performed. Operand 2 is the second operand to the binary | |
8282 | operator. Operand 3 is the memory model to be used by the operation. | |
8283 | ||
8284 | If these patterns are not defined, attempts will be made to use legacy | |
8285 | @code{sync} patterns. If none of these are available a compare-and-swap | |
8286 | loop will be used. | |
8287 | ||
8288 | @cindex @code{atomic_add_fetch@var{mode}} instruction pattern | |
8289 | @cindex @code{atomic_sub_fetch@var{mode}} instruction pattern | |
8290 | @cindex @code{atomic_or_fetch@var{mode}} instruction pattern | |
8291 | @cindex @code{atomic_and_fetch@var{mode}} instruction pattern | |
8292 | @cindex @code{atomic_xor_fetch@var{mode}} instruction pattern | |
8293 | @cindex @code{atomic_nand_fetch@var{mode}} instruction pattern | |
8294 | @item @samp{atomic_add_fetch@var{mode}}, @samp{atomic_sub_fetch@var{mode}} | |
8295 | @itemx @samp{atomic_or_fetch@var{mode}}, @samp{atomic_and_fetch@var{mode}} | |
8296 | @itemx @samp{atomic_xor_fetch@var{mode}}, @samp{atomic_nand_fetch@var{mode}} | |
8297 | These patterns emit code for an atomic operation on memory with memory | |
8298 | model semantics and return the result after the operation is performed. | |
8299 | Operand 0 is an output operand which contains the value after the | |
8300 | operation. Operand 1 is the memory on which the atomic operation is | |
8301 | performed. Operand 2 is the second operand to the binary operator. | |
8302 | Operand 3 is the memory model to be used by the operation. | |
8303 | ||
8304 | If these patterns are not defined, attempts will be made to use legacy | |
8305 | @code{sync} patterns, or equivalent patterns which return the result before | |
8306 | the operation followed by the arithmetic operation required to produce the | |
8307 | result. If none of these are available a compare-and-swap loop will be | |
8308 | used. | |
8309 | ||
8310 | @cindex @code{atomic_test_and_set} instruction pattern | |
8311 | @item @samp{atomic_test_and_set} | |
8312 | This pattern emits code for @code{__builtin_atomic_test_and_set}. | |
8313 | Operand 0 is an output operand which is set to true if the previous | |
8314 | previous contents of the byte was "set", and false otherwise. Operand 1 | |
8315 | is the @code{QImode} memory to be modified. Operand 2 is the memory | |
8316 | model to be used. | |
8317 | ||
8318 | The specific value that defines "set" is implementation defined, and | |
8319 | is normally based on what is performed by the native atomic test and set | |
8320 | instruction. | |
8321 | ||
8322 | @cindex @code{atomic_bit_test_and_set@var{mode}} instruction pattern | |
8323 | @cindex @code{atomic_bit_test_and_complement@var{mode}} instruction pattern | |
8324 | @cindex @code{atomic_bit_test_and_reset@var{mode}} instruction pattern | |
8325 | @item @samp{atomic_bit_test_and_set@var{mode}} | |
8326 | @itemx @samp{atomic_bit_test_and_complement@var{mode}} | |
8327 | @itemx @samp{atomic_bit_test_and_reset@var{mode}} | |
8328 | These patterns emit code for an atomic bitwise operation on memory with memory | |
8329 | model semantics, and return the original value of the specified bit. | |
8330 | Operand 0 is an output operand which contains the value of the specified bit | |
8331 | from the memory location before the operation was performed. Operand 1 is the | |
8332 | memory on which the atomic operation is performed. Operand 2 is the bit within | |
8333 | the operand, starting with least significant bit. Operand 3 is the memory model | |
8334 | to be used by the operation. Operand 4 is a flag - it is @code{const1_rtx} | |
8335 | if operand 0 should contain the original value of the specified bit in the | |
8336 | least significant bit of the operand, and @code{const0_rtx} if the bit should | |
8337 | be in its original position in the operand. | |
8338 | @code{atomic_bit_test_and_set@var{mode}} atomically sets the specified bit after | |
8339 | remembering its original value, @code{atomic_bit_test_and_complement@var{mode}} | |
8340 | inverts the specified bit and @code{atomic_bit_test_and_reset@var{mode}} clears | |
8341 | the specified bit. | |
8342 | ||
8343 | If these patterns are not defined, attempts will be made to use | |
8344 | @code{atomic_fetch_or@var{mode}}, @code{atomic_fetch_xor@var{mode}} or | |
8345 | @code{atomic_fetch_and@var{mode}} instruction patterns, or their @code{sync} | |
8346 | counterparts. If none of these are available a compare-and-swap | |
8347 | loop will be used. | |
8348 | ||
8349 | @cindex @code{atomic_add_fetch_cmp_0@var{mode}} instruction pattern | |
8350 | @cindex @code{atomic_sub_fetch_cmp_0@var{mode}} instruction pattern | |
8351 | @cindex @code{atomic_and_fetch_cmp_0@var{mode}} instruction pattern | |
8352 | @cindex @code{atomic_or_fetch_cmp_0@var{mode}} instruction pattern | |
8353 | @cindex @code{atomic_xor_fetch_cmp_0@var{mode}} instruction pattern | |
8354 | @item @samp{atomic_add_fetch_cmp_0@var{mode}} | |
8355 | @itemx @samp{atomic_sub_fetch_cmp_0@var{mode}} | |
8356 | @itemx @samp{atomic_and_fetch_cmp_0@var{mode}} | |
8357 | @itemx @samp{atomic_or_fetch_cmp_0@var{mode}} | |
8358 | @itemx @samp{atomic_xor_fetch_cmp_0@var{mode}} | |
8359 | These patterns emit code for an atomic operation on memory with memory | |
8360 | model semantics if the fetch result is used only in a comparison against | |
8361 | zero. | |
8362 | Operand 0 is an output operand which contains a boolean result of comparison | |
8363 | of the value after the operation against zero. Operand 1 is the memory on | |
8364 | which the atomic operation is performed. Operand 2 is the second operand | |
8365 | to the binary operator. Operand 3 is the memory model to be used by the | |
8366 | operation. Operand 4 is an integer holding the comparison code, one of | |
8367 | @code{EQ}, @code{NE}, @code{LT}, @code{GT}, @code{LE} or @code{GE}. | |
8368 | ||
8369 | If these patterns are not defined, attempts will be made to use separate | |
8370 | atomic operation and fetch pattern followed by comparison of the result | |
8371 | against zero. | |
8372 | ||
8373 | @cindex @code{mem_thread_fence} instruction pattern | |
8374 | @item @samp{mem_thread_fence} | |
8375 | This pattern emits code required to implement a thread fence with | |
8376 | memory model semantics. Operand 0 is the memory model to be used. | |
8377 | ||
8378 | For the @code{__ATOMIC_RELAXED} model no instructions need to be issued | |
8379 | and this expansion is not invoked. | |
8380 | ||
8381 | The compiler always emits a compiler memory barrier regardless of what | |
8382 | expanding this pattern produced. | |
8383 | ||
8384 | If this pattern is not defined, the compiler falls back to expanding the | |
8385 | @code{memory_barrier} pattern, then to emitting @code{__sync_synchronize} | |
8386 | library call, and finally to just placing a compiler memory barrier. | |
8387 | ||
8388 | @cindex @code{get_thread_pointer@var{mode}} instruction pattern | |
8389 | @cindex @code{set_thread_pointer@var{mode}} instruction pattern | |
8390 | @item @samp{get_thread_pointer@var{mode}} | |
8391 | @itemx @samp{set_thread_pointer@var{mode}} | |
8392 | These patterns emit code that reads/sets the TLS thread pointer. Currently, | |
8393 | these are only needed if the target needs to support the | |
8394 | @code{__builtin_thread_pointer} and @code{__builtin_set_thread_pointer} | |
8395 | builtins. | |
8396 | ||
8397 | The get/set patterns have a single output/input operand respectively, | |
8398 | with @var{mode} intended to be @code{Pmode}. | |
8399 | ||
8400 | @cindex @code{stack_protect_combined_set} instruction pattern | |
8401 | @item @samp{stack_protect_combined_set} | |
8402 | This pattern, if defined, moves a @code{ptr_mode} value from an address | |
8403 | whose declaration RTX is given in operand 1 to the memory in operand 0 | |
8404 | without leaving the value in a register afterward. If several | |
8405 | instructions are needed by the target to perform the operation (eg. to | |
8406 | load the address from a GOT entry then load the @code{ptr_mode} value | |
8407 | and finally store it), it is the backend's responsibility to ensure no | |
8408 | intermediate result gets spilled. This is to avoid leaking the value | |
8409 | some place that an attacker might use to rewrite the stack guard slot | |
8410 | after having clobbered it. | |
8411 | ||
8412 | If this pattern is not defined, then the address declaration is | |
8413 | expanded first in the standard way and a @code{stack_protect_set} | |
8414 | pattern is then generated to move the value from that address to the | |
8415 | address in operand 0. | |
8416 | ||
8417 | @cindex @code{stack_protect_set} instruction pattern | |
8418 | @item @samp{stack_protect_set} | |
8419 | This pattern, if defined, moves a @code{ptr_mode} value from the valid | |
8420 | memory location in operand 1 to the memory in operand 0 without leaving | |
8421 | the value in a register afterward. This is to avoid leaking the value | |
8422 | some place that an attacker might use to rewrite the stack guard slot | |
8423 | after having clobbered it. | |
8424 | ||
8425 | Note: on targets where the addressing modes do not allow to load | |
8426 | directly from stack guard address, the address is expanded in a standard | |
8427 | way first which could cause some spills. | |
8428 | ||
8429 | If this pattern is not defined, then a plain move pattern is generated. | |
8430 | ||
8431 | @cindex @code{stack_protect_combined_test} instruction pattern | |
8432 | @item @samp{stack_protect_combined_test} | |
8433 | This pattern, if defined, compares a @code{ptr_mode} value from an | |
8434 | address whose declaration RTX is given in operand 1 with the memory in | |
8435 | operand 0 without leaving the value in a register afterward and | |
8436 | branches to operand 2 if the values were equal. If several | |
8437 | instructions are needed by the target to perform the operation (eg. to | |
8438 | load the address from a GOT entry then load the @code{ptr_mode} value | |
8439 | and finally store it), it is the backend's responsibility to ensure no | |
8440 | intermediate result gets spilled. This is to avoid leaking the value | |
8441 | some place that an attacker might use to rewrite the stack guard slot | |
8442 | after having clobbered it. | |
8443 | ||
8444 | If this pattern is not defined, then the address declaration is | |
8445 | expanded first in the standard way and a @code{stack_protect_test} | |
8446 | pattern is then generated to compare the value from that address to the | |
8447 | value at the memory in operand 0. | |
8448 | ||
8449 | @cindex @code{stack_protect_test} instruction pattern | |
8450 | @item @samp{stack_protect_test} | |
8451 | This pattern, if defined, compares a @code{ptr_mode} value from the | |
8452 | valid memory location in operand 1 with the memory in operand 0 without | |
8453 | leaving the value in a register afterward and branches to operand 2 if | |
8454 | the values were equal. | |
8455 | ||
8456 | If this pattern is not defined, then a plain compare pattern and | |
8457 | conditional branch pattern is used. | |
8458 | ||
8459 | @cindex @code{clear_cache} instruction pattern | |
8460 | @item @samp{clear_cache} | |
8461 | This pattern, if defined, flushes the instruction cache for a region of | |
8462 | memory. The region is bounded to by the Pmode pointers in operand 0 | |
8463 | inclusive and operand 1 exclusive. | |
8464 | ||
8465 | If this pattern is not defined, a call to the library function | |
8466 | @code{__clear_cache} is used. | |
8467 | ||
8468 | @cindex @code{spaceship@var{m}3} instruction pattern | |
8469 | @item @samp{spaceship@var{m}3} | |
8470 | Initialize output operand 0 with mode of integer type to -1, 0, 1 or 2 | |
8471 | if operand 1 with mode @var{m} compares less than operand 2, equal to | |
8472 | operand 2, greater than operand 2 or is unordered with operand 2. | |
8473 | @var{m} should be a scalar floating point mode. | |
8474 | ||
8475 | This pattern is not allowed to @code{FAIL}. | |
8476 | ||
8477 | @end table | |
8478 | ||
8479 | @end ifset | |
8480 | @c Each of the following nodes are wrapped in separate | |
8481 | @c "@ifset INTERNALS" to work around memory limits for the default | |
8482 | @c configuration in older tetex distributions. Known to not work: | |
8483 | @c tetex-1.0.7, known to work: tetex-2.0.2. | |
8484 | @ifset INTERNALS | |
8485 | @node Pattern Ordering | |
8486 | @section When the Order of Patterns Matters | |
8487 | @cindex Pattern Ordering | |
8488 | @cindex Ordering of Patterns | |
8489 | ||
8490 | Sometimes an insn can match more than one instruction pattern. Then the | |
8491 | pattern that appears first in the machine description is the one used. | |
8492 | Therefore, more specific patterns (patterns that will match fewer things) | |
8493 | and faster instructions (those that will produce better code when they | |
8494 | do match) should usually go first in the description. | |
8495 | ||
8496 | In some cases the effect of ordering the patterns can be used to hide | |
8497 | a pattern when it is not valid. For example, the 68000 has an | |
8498 | instruction for converting a fullword to floating point and another | |
8499 | for converting a byte to floating point. An instruction converting | |
8500 | an integer to floating point could match either one. We put the | |
8501 | pattern to convert the fullword first to make sure that one will | |
8502 | be used rather than the other. (Otherwise a large integer might | |
8503 | be generated as a single-byte immediate quantity, which would not work.) | |
8504 | Instead of using this pattern ordering it would be possible to make the | |
8505 | pattern for convert-a-byte smart enough to deal properly with any | |
8506 | constant value. | |
8507 | ||
8508 | @end ifset | |
8509 | @ifset INTERNALS | |
8510 | @node Dependent Patterns | |
8511 | @section Interdependence of Patterns | |
8512 | @cindex Dependent Patterns | |
8513 | @cindex Interdependence of Patterns | |
8514 | ||
8515 | In some cases machines support instructions identical except for the | |
8516 | machine mode of one or more operands. For example, there may be | |
8517 | ``sign-extend halfword'' and ``sign-extend byte'' instructions whose | |
8518 | patterns are | |
8519 | ||
8520 | @smallexample | |
8521 | (set (match_operand:SI 0 @dots{}) | |
8522 | (extend:SI (match_operand:HI 1 @dots{}))) | |
8523 | ||
8524 | (set (match_operand:SI 0 @dots{}) | |
8525 | (extend:SI (match_operand:QI 1 @dots{}))) | |
8526 | @end smallexample | |
8527 | ||
8528 | @noindent | |
8529 | Constant integers do not specify a machine mode, so an instruction to | |
8530 | extend a constant value could match either pattern. The pattern it | |
8531 | actually will match is the one that appears first in the file. For correct | |
8532 | results, this must be the one for the widest possible mode (@code{HImode}, | |
8533 | here). If the pattern matches the @code{QImode} instruction, the results | |
8534 | will be incorrect if the constant value does not actually fit that mode. | |
8535 | ||
8536 | Such instructions to extend constants are rarely generated because they are | |
8537 | optimized away, but they do occasionally happen in nonoptimized | |
8538 | compilations. | |
8539 | ||
8540 | If a constraint in a pattern allows a constant, the reload pass may | |
8541 | replace a register with a constant permitted by the constraint in some | |
8542 | cases. Similarly for memory references. Because of this substitution, | |
8543 | you should not provide separate patterns for increment and decrement | |
8544 | instructions. Instead, they should be generated from the same pattern | |
8545 | that supports register-register add insns by examining the operands and | |
8546 | generating the appropriate machine instruction. | |
8547 | ||
8548 | @end ifset | |
8549 | @ifset INTERNALS | |
8550 | @node Jump Patterns | |
8551 | @section Defining Jump Instruction Patterns | |
8552 | @cindex jump instruction patterns | |
8553 | @cindex defining jump instruction patterns | |
8554 | ||
8555 | GCC does not assume anything about how the machine realizes jumps. | |
8556 | The machine description should define a single pattern, usually | |
8557 | a @code{define_expand}, which expands to all the required insns. | |
8558 | ||
8559 | Usually, this would be a comparison insn to set the condition code | |
8560 | and a separate branch insn testing the condition code and branching | |
8561 | or not according to its value. For many machines, however, | |
8562 | separating compares and branches is limiting, which is why the | |
8563 | more flexible approach with one @code{define_expand} is used in GCC. | |
8564 | The machine description becomes clearer for architectures that | |
8565 | have compare-and-branch instructions but no condition code. It also | |
8566 | works better when different sets of comparison operators are supported | |
8567 | by different kinds of conditional branches (e.g.@: integer vs.@: | |
8568 | floating-point), or by conditional branches with respect to conditional stores. | |
8569 | ||
8570 | Two separate insns are always used on most machines that use a separate | |
8571 | condition code register (@pxref{Condition Code}). | |
8572 | ||
8573 | Even in this case having a single entry point for conditional branches | |
8574 | is advantageous, because it handles equally well the case where a single | |
8575 | comparison instruction records the results of both signed and unsigned | |
8576 | comparison of the given operands (with the branch insns coming in distinct | |
8577 | signed and unsigned flavors) as in the x86 or SPARC, and the case where | |
8578 | there are distinct signed and unsigned compare instructions and only | |
8579 | one set of conditional branch instructions as in the PowerPC. | |
8580 | ||
8581 | @end ifset | |
8582 | @ifset INTERNALS | |
8583 | @node Looping Patterns | |
8584 | @section Defining Looping Instruction Patterns | |
8585 | @cindex looping instruction patterns | |
8586 | @cindex defining looping instruction patterns | |
8587 | ||
8588 | Some machines have special jump instructions that can be utilized to | |
8589 | make loops more efficient. A common example is the 68000 @samp{dbra} | |
8590 | instruction which performs a decrement of a register and a branch if the | |
8591 | result was greater than zero. Other machines, in particular digital | |
8592 | signal processors (DSPs), have special block repeat instructions to | |
8593 | provide low-overhead loop support. For example, the TI TMS320C3x/C4x | |
8594 | DSPs have a block repeat instruction that loads special registers to | |
8595 | mark the top and end of a loop and to count the number of loop | |
8596 | iterations. This avoids the need for fetching and executing a | |
8597 | @samp{dbra}-like instruction and avoids pipeline stalls associated with | |
8598 | the jump. | |
8599 | ||
8600 | GCC has two special named patterns to support low overhead looping. | |
8601 | They are @samp{doloop_begin} and @samp{doloop_end}. These are emitted | |
8602 | by the loop optimizer for certain well-behaved loops with a finite | |
8603 | number of loop iterations using information collected during strength | |
8604 | reduction. | |
8605 | ||
8606 | The @samp{doloop_end} pattern describes the actual looping instruction | |
8607 | (or the implicit looping operation) and the @samp{doloop_begin} pattern | |
8608 | is an optional companion pattern that can be used for initialization | |
8609 | needed for some low-overhead looping instructions. | |
8610 | ||
8611 | Note that some machines require the actual looping instruction to be | |
8612 | emitted at the top of the loop (e.g., the TMS320C3x/C4x DSPs). Emitting | |
8613 | the true RTL for a looping instruction at the top of the loop can cause | |
8614 | problems with flow analysis. So instead, a dummy @code{doloop} insn is | |
8615 | emitted at the end of the loop. The machine dependent reorg pass checks | |
8616 | for the presence of this @code{doloop} insn and then searches back to | |
8617 | the top of the loop, where it inserts the true looping insn (provided | |
8618 | there are no instructions in the loop which would cause problems). Any | |
8619 | additional labels can be emitted at this point. In addition, if the | |
8620 | desired special iteration counter register was not allocated, this | |
8621 | machine dependent reorg pass could emit a traditional compare and jump | |
8622 | instruction pair. | |
8623 | ||
8624 | For the @samp{doloop_end} pattern, the loop optimizer allocates an | |
8625 | additional pseudo register as an iteration counter. This pseudo | |
8626 | register cannot be used within the loop (i.e., general induction | |
8627 | variables cannot be derived from it), however, in many cases the loop | |
8628 | induction variable may become redundant and removed by the flow pass. | |
8629 | ||
8630 | The @samp{doloop_end} pattern must have a specific structure to be | |
8631 | handled correctly by GCC. The example below is taken (slightly | |
8632 | simplified) from the PDP-11 target: | |
8633 | ||
8634 | @smallexample | |
8635 | @group | |
8636 | (define_expand "doloop_end" | |
8637 | [(parallel [(set (pc) | |
8638 | (if_then_else | |
8639 | (ne (match_operand:HI 0 "nonimmediate_operand" "+r,!m") | |
8640 | (const_int 1)) | |
8641 | (label_ref (match_operand 1 "" "")) | |
8642 | (pc))) | |
8643 | (set (match_dup 0) | |
8644 | (plus:HI (match_dup 0) | |
8645 | (const_int -1)))])] | |
8646 | "" | |
8647 | "@{ | |
8648 | if (GET_MODE (operands[0]) != HImode) | |
8649 | FAIL; | |
8650 | @}") | |
8651 | ||
8652 | (define_insn "doloop_end_insn" | |
8653 | [(set (pc) | |
8654 | (if_then_else | |
8655 | (ne (match_operand:HI 0 "nonimmediate_operand" "+r,!m") | |
8656 | (const_int 1)) | |
8657 | (label_ref (match_operand 1 "" "")) | |
8658 | (pc))) | |
8659 | (set (match_dup 0) | |
8660 | (plus:HI (match_dup 0) | |
8661 | (const_int -1)))] | |
8662 | "" | |
8663 | ||
8664 | @{ | |
8665 | if (which_alternative == 0) | |
8666 | return "sob %0,%l1"; | |
8667 | ||
8668 | /* emulate sob */ | |
8669 | output_asm_insn ("dec %0", operands); | |
8670 | return "bne %l1"; | |
8671 | @}) | |
8672 | @end group | |
8673 | @end smallexample | |
8674 | ||
8675 | The first part of the pattern describes the branch condition. GCC | |
8676 | supports three cases for the way the target machine handles the loop | |
8677 | counter: | |
8678 | @itemize @bullet | |
8679 | @item Loop terminates when the loop register decrements to zero. This | |
8680 | is represented by a @code{ne} comparison of the register (its old value) | |
8681 | with constant 1 (as in the example above). | |
8682 | @item Loop terminates when the loop register decrements to @minus{}1. | |
8683 | This is represented by a @code{ne} comparison of the register with | |
8684 | constant zero. | |
8685 | @item Loop terminates when the loop register decrements to a negative | |
8686 | value. This is represented by a @code{ge} comparison of the register | |
8687 | with constant zero. For this case, GCC will attach a @code{REG_NONNEG} | |
8688 | note to the @code{doloop_end} insn if it can determine that the register | |
8689 | will be non-negative. | |
8690 | @end itemize | |
8691 | ||
8692 | Since the @code{doloop_end} insn is a jump insn that also has an output, | |
8693 | the reload pass does not handle the output operand. Therefore, the | |
8694 | constraint must allow for that operand to be in memory rather than a | |
8695 | register. In the example shown above, that is handled (in the | |
8696 | @code{doloop_end_insn} pattern) by using a loop instruction sequence | |
8697 | that can handle memory operands when the memory alternative appears. | |
8698 | ||
8699 | GCC does not check the mode of the loop register operand when generating | |
8700 | the @code{doloop_end} pattern. If the pattern is only valid for some | |
8701 | modes but not others, the pattern should be a @code{define_expand} | |
8702 | pattern that checks the operand mode in the preparation code, and issues | |
8703 | @code{FAIL} if an unsupported mode is found. The example above does | |
8704 | this, since the machine instruction to be used only exists for | |
8705 | @code{HImode}. | |
8706 | ||
8707 | If the @code{doloop_end} pattern is a @code{define_expand}, there must | |
8708 | also be a @code{define_insn} or @code{define_insn_and_split} matching | |
8709 | the generated pattern. Otherwise, the compiler will fail during loop | |
8710 | optimization. | |
8711 | ||
8712 | @end ifset | |
8713 | @ifset INTERNALS | |
8714 | @node Insn Canonicalizations | |
8715 | @section Canonicalization of Instructions | |
8716 | @cindex canonicalization of instructions | |
8717 | @cindex insn canonicalization | |
8718 | ||
8719 | There are often cases where multiple RTL expressions could represent an | |
8720 | operation performed by a single machine instruction. This situation is | |
8721 | most commonly encountered with logical, branch, and multiply-accumulate | |
8722 | instructions. In such cases, the compiler attempts to convert these | |
8723 | multiple RTL expressions into a single canonical form to reduce the | |
8724 | number of insn patterns required. | |
8725 | ||
8726 | In addition to algebraic simplifications, following canonicalizations | |
8727 | are performed: | |
8728 | ||
8729 | @itemize @bullet | |
8730 | @item | |
8731 | For commutative and comparison operators, a constant is always made the | |
8732 | second operand. If a machine only supports a constant as the second | |
8733 | operand, only patterns that match a constant in the second operand need | |
8734 | be supplied. | |
8735 | ||
23b60aeb | 8736 | @cindex @code{vec_merge}, canonicalization of |
8737 | @item | |
8738 | For the @code{vec_merge} with constant mask(the third operand), the first | |
8739 | and the second operand can be exchanged by inverting the mask. In such cases, | |
8740 | a constant is always made the second operand, otherwise the least significant | |
8741 | bit of the mask is always set(select the first operand first). | |
8742 | ||
d77de738 ML |
8743 | @item |
8744 | For associative operators, a sequence of operators will always chain | |
8745 | to the left; for instance, only the left operand of an integer @code{plus} | |
8746 | can itself be a @code{plus}. @code{and}, @code{ior}, @code{xor}, | |
8747 | @code{plus}, @code{mult}, @code{smin}, @code{smax}, @code{umin}, and | |
8748 | @code{umax} are associative when applied to integers, and sometimes to | |
8749 | floating-point. | |
8750 | ||
d77de738 ML |
8751 | @cindex @code{neg}, canonicalization of |
8752 | @cindex @code{not}, canonicalization of | |
8753 | @cindex @code{mult}, canonicalization of | |
8754 | @cindex @code{plus}, canonicalization of | |
8755 | @cindex @code{minus}, canonicalization of | |
f33d7a88 | 8756 | @item |
d77de738 ML |
8757 | For these operators, if only one operand is a @code{neg}, @code{not}, |
8758 | @code{mult}, @code{plus}, or @code{minus} expression, it will be the | |
8759 | first operand. | |
8760 | ||
8761 | @item | |
8762 | In combinations of @code{neg}, @code{mult}, @code{plus}, and | |
8763 | @code{minus}, the @code{neg} operations (if any) will be moved inside | |
8764 | the operations as far as possible. For instance, | |
8765 | @code{(neg (mult A B))} is canonicalized as @code{(mult (neg A) B)}, but | |
8766 | @code{(plus (mult (neg B) C) A)} is canonicalized as | |
8767 | @code{(minus A (mult B C))}. | |
8768 | ||
8769 | @cindex @code{compare}, canonicalization of | |
8770 | @item | |
8771 | For the @code{compare} operator, a constant is always the second operand | |
8772 | if the first argument is a condition code register. | |
8773 | ||
8774 | @item | |
8775 | For instructions that inherently set a condition code register, the | |
8776 | @code{compare} operator is always written as the first RTL expression of | |
8777 | the @code{parallel} instruction pattern. For example, | |
8778 | ||
8779 | @smallexample | |
8780 | (define_insn "" | |
8781 | [(set (reg:CCZ FLAGS_REG) | |
8782 | (compare:CCZ | |
8783 | (plus:SI | |
8784 | (match_operand:SI 1 "register_operand" "%r") | |
8785 | (match_operand:SI 2 "register_operand" "r")) | |
8786 | (const_int 0))) | |
8787 | (set (match_operand:SI 0 "register_operand" "=r") | |
8788 | (plus:SI (match_dup 1) (match_dup 2)))] | |
8789 | "" | |
8790 | "addl %0, %1, %2") | |
8791 | @end smallexample | |
8792 | ||
8793 | @item | |
8794 | An operand of @code{neg}, @code{not}, @code{mult}, @code{plus}, or | |
8795 | @code{minus} is made the first operand under the same conditions as | |
8796 | above. | |
8797 | ||
8798 | @item | |
8799 | @code{(ltu (plus @var{a} @var{b}) @var{b})} is converted to | |
8800 | @code{(ltu (plus @var{a} @var{b}) @var{a})}. Likewise with @code{geu} instead | |
8801 | of @code{ltu}. | |
8802 | ||
8803 | @item | |
8804 | @code{(minus @var{x} (const_int @var{n}))} is converted to | |
8805 | @code{(plus @var{x} (const_int @var{-n}))}. | |
8806 | ||
8807 | @item | |
8808 | Within address computations (i.e., inside @code{mem}), a left shift is | |
8809 | converted into the appropriate multiplication by a power of two. | |
8810 | ||
8811 | @cindex @code{ior}, canonicalization of | |
8812 | @cindex @code{and}, canonicalization of | |
8813 | @cindex De Morgan's law | |
8814 | @item | |
8815 | De Morgan's Law is used to move bitwise negation inside a bitwise | |
8816 | logical-and or logical-or operation. If this results in only one | |
8817 | operand being a @code{not} expression, it will be the first one. | |
8818 | ||
8819 | A machine that has an instruction that performs a bitwise logical-and of one | |
8820 | operand with the bitwise negation of the other should specify the pattern | |
8821 | for that instruction as | |
8822 | ||
8823 | @smallexample | |
8824 | (define_insn "" | |
8825 | [(set (match_operand:@var{m} 0 @dots{}) | |
8826 | (and:@var{m} (not:@var{m} (match_operand:@var{m} 1 @dots{})) | |
8827 | (match_operand:@var{m} 2 @dots{})))] | |
8828 | "@dots{}" | |
8829 | "@dots{}") | |
8830 | @end smallexample | |
8831 | ||
8832 | @noindent | |
8833 | Similarly, a pattern for a ``NAND'' instruction should be written | |
8834 | ||
8835 | @smallexample | |
8836 | (define_insn "" | |
8837 | [(set (match_operand:@var{m} 0 @dots{}) | |
8838 | (ior:@var{m} (not:@var{m} (match_operand:@var{m} 1 @dots{})) | |
8839 | (not:@var{m} (match_operand:@var{m} 2 @dots{}))))] | |
8840 | "@dots{}" | |
8841 | "@dots{}") | |
8842 | @end smallexample | |
8843 | ||
8844 | In both cases, it is not necessary to include patterns for the many | |
8845 | logically equivalent RTL expressions. | |
8846 | ||
8847 | @cindex @code{xor}, canonicalization of | |
8848 | @item | |
8849 | The only possible RTL expressions involving both bitwise exclusive-or | |
8850 | and bitwise negation are @code{(xor:@var{m} @var{x} @var{y})} | |
8851 | and @code{(not:@var{m} (xor:@var{m} @var{x} @var{y}))}. | |
8852 | ||
8853 | @item | |
8854 | The sum of three items, one of which is a constant, will only appear in | |
8855 | the form | |
8856 | ||
8857 | @smallexample | |
8858 | (plus:@var{m} (plus:@var{m} @var{x} @var{y}) @var{constant}) | |
8859 | @end smallexample | |
8860 | ||
8861 | @cindex @code{zero_extract}, canonicalization of | |
8862 | @cindex @code{sign_extract}, canonicalization of | |
8863 | @item | |
8864 | Equality comparisons of a group of bits (usually a single bit) with zero | |
8865 | will be written using @code{zero_extract} rather than the equivalent | |
8866 | @code{and} or @code{sign_extract} operations. | |
8867 | ||
8868 | @cindex @code{mult}, canonicalization of | |
8869 | @item | |
8870 | @code{(sign_extend:@var{m1} (mult:@var{m2} (sign_extend:@var{m2} @var{x}) | |
8871 | (sign_extend:@var{m2} @var{y})))} is converted to @code{(mult:@var{m1} | |
8872 | (sign_extend:@var{m1} @var{x}) (sign_extend:@var{m1} @var{y}))}, and likewise | |
8873 | for @code{zero_extend}. | |
8874 | ||
8875 | @item | |
8876 | @code{(sign_extend:@var{m1} (mult:@var{m2} (ashiftrt:@var{m2} | |
8877 | @var{x} @var{s}) (sign_extend:@var{m2} @var{y})))} is converted | |
8878 | to @code{(mult:@var{m1} (sign_extend:@var{m1} (ashiftrt:@var{m2} | |
8879 | @var{x} @var{s})) (sign_extend:@var{m1} @var{y}))}, and likewise for | |
8880 | patterns using @code{zero_extend} and @code{lshiftrt}. If the second | |
8881 | operand of @code{mult} is also a shift, then that is extended also. | |
8882 | This transformation is only applied when it can be proven that the | |
8883 | original operation had sufficient precision to prevent overflow. | |
8884 | ||
8885 | @end itemize | |
8886 | ||
8887 | Further canonicalization rules are defined in the function | |
8888 | @code{commutative_operand_precedence} in @file{gcc/rtlanal.cc}. | |
8889 | ||
8890 | @end ifset | |
8891 | @ifset INTERNALS | |
8892 | @node Expander Definitions | |
8893 | @section Defining RTL Sequences for Code Generation | |
8894 | @cindex expander definitions | |
8895 | @cindex code generation RTL sequences | |
8896 | @cindex defining RTL sequences for code generation | |
8897 | ||
8898 | On some target machines, some standard pattern names for RTL generation | |
8899 | cannot be handled with single insn, but a sequence of RTL insns can | |
8900 | represent them. For these target machines, you can write a | |
8901 | @code{define_expand} to specify how to generate the sequence of RTL@. | |
8902 | ||
8903 | @findex define_expand | |
8904 | A @code{define_expand} is an RTL expression that looks almost like a | |
8905 | @code{define_insn}; but, unlike the latter, a @code{define_expand} is used | |
8906 | only for RTL generation and it can produce more than one RTL insn. | |
8907 | ||
8908 | A @code{define_expand} RTX has four operands: | |
8909 | ||
8910 | @itemize @bullet | |
8911 | @item | |
8912 | The name. Each @code{define_expand} must have a name, since the only | |
8913 | use for it is to refer to it by name. | |
8914 | ||
8915 | @item | |
8916 | The RTL template. This is a vector of RTL expressions representing | |
8917 | a sequence of separate instructions. Unlike @code{define_insn}, there | |
8918 | is no implicit surrounding @code{PARALLEL}. | |
8919 | ||
8920 | @item | |
8921 | The condition, a string containing a C expression. This expression is | |
8922 | used to express how the availability of this pattern depends on | |
8923 | subclasses of target machine, selected by command-line options when GCC | |
8924 | is run. This is just like the condition of a @code{define_insn} that | |
8925 | has a standard name. Therefore, the condition (if present) may not | |
8926 | depend on the data in the insn being matched, but only the | |
8927 | target-machine-type flags. The compiler needs to test these conditions | |
8928 | during initialization in order to learn exactly which named instructions | |
8929 | are available in a particular run. | |
8930 | ||
8931 | @item | |
8932 | The preparation statements, a string containing zero or more C | |
8933 | statements which are to be executed before RTL code is generated from | |
8934 | the RTL template. | |
8935 | ||
8936 | Usually these statements prepare temporary registers for use as | |
8937 | internal operands in the RTL template, but they can also generate RTL | |
8938 | insns directly by calling routines such as @code{emit_insn}, etc. | |
8939 | Any such insns precede the ones that come from the RTL template. | |
8940 | ||
8941 | @item | |
8942 | Optionally, a vector containing the values of attributes. @xref{Insn | |
8943 | Attributes}. | |
8944 | @end itemize | |
8945 | ||
8946 | Every RTL insn emitted by a @code{define_expand} must match some | |
8947 | @code{define_insn} in the machine description. Otherwise, the compiler | |
8948 | will crash when trying to generate code for the insn or trying to optimize | |
8949 | it. | |
8950 | ||
8951 | The RTL template, in addition to controlling generation of RTL insns, | |
8952 | also describes the operands that need to be specified when this pattern | |
8953 | is used. In particular, it gives a predicate for each operand. | |
8954 | ||
8955 | A true operand, which needs to be specified in order to generate RTL from | |
8956 | the pattern, should be described with a @code{match_operand} in its first | |
8957 | occurrence in the RTL template. This enters information on the operand's | |
8958 | predicate into the tables that record such things. GCC uses the | |
8959 | information to preload the operand into a register if that is required for | |
8960 | valid RTL code. If the operand is referred to more than once, subsequent | |
8961 | references should use @code{match_dup}. | |
8962 | ||
8963 | The RTL template may also refer to internal ``operands'' which are | |
8964 | temporary registers or labels used only within the sequence made by the | |
8965 | @code{define_expand}. Internal operands are substituted into the RTL | |
8966 | template with @code{match_dup}, never with @code{match_operand}. The | |
8967 | values of the internal operands are not passed in as arguments by the | |
8968 | compiler when it requests use of this pattern. Instead, they are computed | |
8969 | within the pattern, in the preparation statements. These statements | |
8970 | compute the values and store them into the appropriate elements of | |
8971 | @code{operands} so that @code{match_dup} can find them. | |
8972 | ||
8973 | There are two special macros defined for use in the preparation statements: | |
8974 | @code{DONE} and @code{FAIL}. Use them with a following semicolon, | |
8975 | as a statement. | |
8976 | ||
8977 | @table @code | |
8978 | ||
8979 | @findex DONE | |
8980 | @item DONE | |
8981 | Use the @code{DONE} macro to end RTL generation for the pattern. The | |
8982 | only RTL insns resulting from the pattern on this occasion will be | |
8983 | those already emitted by explicit calls to @code{emit_insn} within the | |
8984 | preparation statements; the RTL template will not be generated. | |
8985 | ||
8986 | @findex FAIL | |
8987 | @item FAIL | |
8988 | Make the pattern fail on this occasion. When a pattern fails, it means | |
8989 | that the pattern was not truly available. The calling routines in the | |
8990 | compiler will try other strategies for code generation using other patterns. | |
8991 | ||
8992 | Failure is currently supported only for binary (addition, multiplication, | |
8993 | shifting, etc.) and bit-field (@code{extv}, @code{extzv}, and @code{insv}) | |
8994 | operations. | |
8995 | @end table | |
8996 | ||
8997 | If the preparation falls through (invokes neither @code{DONE} nor | |
8998 | @code{FAIL}), then the @code{define_expand} acts like a | |
8999 | @code{define_insn} in that the RTL template is used to generate the | |
9000 | insn. | |
9001 | ||
9002 | The RTL template is not used for matching, only for generating the | |
9003 | initial insn list. If the preparation statement always invokes | |
9004 | @code{DONE} or @code{FAIL}, the RTL template may be reduced to a simple | |
9005 | list of operands, such as this example: | |
9006 | ||
9007 | @smallexample | |
9008 | @group | |
9009 | (define_expand "addsi3" | |
9010 | [(match_operand:SI 0 "register_operand" "") | |
9011 | (match_operand:SI 1 "register_operand" "") | |
9012 | (match_operand:SI 2 "register_operand" "")] | |
9013 | "" | |
9014 | " | |
9015 | @{ | |
9016 | handle_add (operands[0], operands[1], operands[2]); | |
9017 | DONE; | |
9018 | @}") | |
9019 | @end group | |
9020 | @end smallexample | |
9021 | ||
9022 | Here is an example, the definition of left-shift for the SPUR chip: | |
9023 | ||
9024 | @smallexample | |
9025 | @group | |
9026 | (define_expand "ashlsi3" | |
9027 | [(set (match_operand:SI 0 "register_operand" "") | |
9028 | (ashift:SI | |
9029 | (match_operand:SI 1 "register_operand" "") | |
9030 | (match_operand:SI 2 "nonmemory_operand" "")))] | |
9031 | "" | |
9032 | " | |
9033 | @{ | |
9034 | if (GET_CODE (operands[2]) != CONST_INT | |
9035 | || (unsigned) INTVAL (operands[2]) > 3) | |
9036 | FAIL; | |
9037 | @}") | |
9038 | @end group | |
9039 | @end smallexample | |
9040 | ||
9041 | @noindent | |
9042 | This example uses @code{define_expand} so that it can generate an RTL insn | |
9043 | for shifting when the shift-count is in the supported range of 0 to 3 but | |
9044 | fail in other cases where machine insns aren't available. When it fails, | |
9045 | the compiler tries another strategy using different patterns (such as, a | |
9046 | library call). | |
9047 | ||
9048 | If the compiler were able to handle nontrivial condition-strings in | |
9049 | patterns with names, then it would be possible to use a | |
9050 | @code{define_insn} in that case. Here is another case (zero-extension | |
9051 | on the 68000) which makes more use of the power of @code{define_expand}: | |
9052 | ||
9053 | @smallexample | |
9054 | (define_expand "zero_extendhisi2" | |
9055 | [(set (match_operand:SI 0 "general_operand" "") | |
9056 | (const_int 0)) | |
9057 | (set (strict_low_part | |
9058 | (subreg:HI | |
9059 | (match_dup 0) | |
9060 | 0)) | |
9061 | (match_operand:HI 1 "general_operand" ""))] | |
9062 | "" | |
9063 | "operands[1] = make_safe_from (operands[1], operands[0]);") | |
9064 | @end smallexample | |
9065 | ||
9066 | @noindent | |
9067 | @findex make_safe_from | |
9068 | Here two RTL insns are generated, one to clear the entire output operand | |
9069 | and the other to copy the input operand into its low half. This sequence | |
9070 | is incorrect if the input operand refers to [the old value of] the output | |
9071 | operand, so the preparation statement makes sure this isn't so. The | |
9072 | function @code{make_safe_from} copies the @code{operands[1]} into a | |
9073 | temporary register if it refers to @code{operands[0]}. It does this | |
9074 | by emitting another RTL insn. | |
9075 | ||
9076 | Finally, a third example shows the use of an internal operand. | |
9077 | Zero-extension on the SPUR chip is done by @code{and}-ing the result | |
9078 | against a halfword mask. But this mask cannot be represented by a | |
9079 | @code{const_int} because the constant value is too large to be legitimate | |
9080 | on this machine. So it must be copied into a register with | |
9081 | @code{force_reg} and then the register used in the @code{and}. | |
9082 | ||
9083 | @smallexample | |
9084 | (define_expand "zero_extendhisi2" | |
9085 | [(set (match_operand:SI 0 "register_operand" "") | |
9086 | (and:SI (subreg:SI | |
9087 | (match_operand:HI 1 "register_operand" "") | |
9088 | 0) | |
9089 | (match_dup 2)))] | |
9090 | "" | |
9091 | "operands[2] | |
9092 | = force_reg (SImode, GEN_INT (65535)); ") | |
9093 | @end smallexample | |
9094 | ||
9095 | @emph{Note:} If the @code{define_expand} is used to serve a | |
9096 | standard binary or unary arithmetic operation or a bit-field operation, | |
9097 | then the last insn it generates must not be a @code{code_label}, | |
9098 | @code{barrier} or @code{note}. It must be an @code{insn}, | |
9099 | @code{jump_insn} or @code{call_insn}. If you don't need a real insn | |
9100 | at the end, emit an insn to copy the result of the operation into | |
9101 | itself. Such an insn will generate no code, but it can avoid problems | |
9102 | in the compiler. | |
9103 | ||
9104 | @end ifset | |
9105 | @ifset INTERNALS | |
9106 | @node Insn Splitting | |
9107 | @section Defining How to Split Instructions | |
9108 | @cindex insn splitting | |
9109 | @cindex instruction splitting | |
9110 | @cindex splitting instructions | |
9111 | ||
9112 | There are two cases where you should specify how to split a pattern | |
9113 | into multiple insns. On machines that have instructions requiring | |
9114 | delay slots (@pxref{Delay Slots}) or that have instructions whose | |
9115 | output is not available for multiple cycles (@pxref{Processor pipeline | |
9116 | description}), the compiler phases that optimize these cases need to | |
9117 | be able to move insns into one-instruction delay slots. However, some | |
9118 | insns may generate more than one machine instruction. These insns | |
9119 | cannot be placed into a delay slot. | |
9120 | ||
9121 | Often you can rewrite the single insn as a list of individual insns, | |
9122 | each corresponding to one machine instruction. The disadvantage of | |
9123 | doing so is that it will cause the compilation to be slower and require | |
9124 | more space. If the resulting insns are too complex, it may also | |
9125 | suppress some optimizations. The compiler splits the insn if there is a | |
9126 | reason to believe that it might improve instruction or delay slot | |
9127 | scheduling. | |
9128 | ||
9129 | The insn combiner phase also splits putative insns. If three insns are | |
9130 | merged into one insn with a complex expression that cannot be matched by | |
9131 | some @code{define_insn} pattern, the combiner phase attempts to split | |
9132 | the complex pattern into two insns that are recognized. Usually it can | |
9133 | break the complex pattern into two patterns by splitting out some | |
9134 | subexpression. However, in some other cases, such as performing an | |
9135 | addition of a large constant in two insns on a RISC machine, the way to | |
9136 | split the addition into two insns is machine-dependent. | |
9137 | ||
9138 | @findex define_split | |
9139 | The @code{define_split} definition tells the compiler how to split a | |
9140 | complex insn into several simpler insns. It looks like this: | |
9141 | ||
9142 | @smallexample | |
9143 | (define_split | |
9144 | [@var{insn-pattern}] | |
9145 | "@var{condition}" | |
9146 | [@var{new-insn-pattern-1} | |
9147 | @var{new-insn-pattern-2} | |
9148 | @dots{}] | |
9149 | "@var{preparation-statements}") | |
9150 | @end smallexample | |
9151 | ||
9152 | @var{insn-pattern} is a pattern that needs to be split and | |
9153 | @var{condition} is the final condition to be tested, as in a | |
9154 | @code{define_insn}. When an insn matching @var{insn-pattern} and | |
9155 | satisfying @var{condition} is found, it is replaced in the insn list | |
9156 | with the insns given by @var{new-insn-pattern-1}, | |
9157 | @var{new-insn-pattern-2}, etc. | |
9158 | ||
9159 | The @var{preparation-statements} are similar to those statements that | |
9160 | are specified for @code{define_expand} (@pxref{Expander Definitions}) | |
9161 | and are executed before the new RTL is generated to prepare for the | |
9162 | generated code or emit some insns whose pattern is not fixed. Unlike | |
9163 | those in @code{define_expand}, however, these statements must not | |
9164 | generate any new pseudo-registers. Once reload has completed, they also | |
9165 | must not allocate any space in the stack frame. | |
9166 | ||
9167 | There are two special macros defined for use in the preparation statements: | |
9168 | @code{DONE} and @code{FAIL}. Use them with a following semicolon, | |
9169 | as a statement. | |
9170 | ||
9171 | @table @code | |
9172 | ||
9173 | @findex DONE | |
9174 | @item DONE | |
9175 | Use the @code{DONE} macro to end RTL generation for the splitter. The | |
9176 | only RTL insns generated as replacement for the matched input insn will | |
9177 | be those already emitted by explicit calls to @code{emit_insn} within | |
9178 | the preparation statements; the replacement pattern is not used. | |
9179 | ||
9180 | @findex FAIL | |
9181 | @item FAIL | |
9182 | Make the @code{define_split} fail on this occasion. When a @code{define_split} | |
9183 | fails, it means that the splitter was not truly available for the inputs | |
9184 | it was given, and the input insn will not be split. | |
9185 | @end table | |
9186 | ||
9187 | If the preparation falls through (invokes neither @code{DONE} nor | |
9188 | @code{FAIL}), then the @code{define_split} uses the replacement | |
9189 | template. | |
9190 | ||
9191 | Patterns are matched against @var{insn-pattern} in two different | |
9192 | circumstances. If an insn needs to be split for delay slot scheduling | |
9193 | or insn scheduling, the insn is already known to be valid, which means | |
9194 | that it must have been matched by some @code{define_insn} and, if | |
9195 | @code{reload_completed} is nonzero, is known to satisfy the constraints | |
9196 | of that @code{define_insn}. In that case, the new insn patterns must | |
9197 | also be insns that are matched by some @code{define_insn} and, if | |
9198 | @code{reload_completed} is nonzero, must also satisfy the constraints | |
9199 | of those definitions. | |
9200 | ||
9201 | As an example of this usage of @code{define_split}, consider the following | |
9202 | example from @file{a29k.md}, which splits a @code{sign_extend} from | |
9203 | @code{HImode} to @code{SImode} into a pair of shift insns: | |
9204 | ||
9205 | @smallexample | |
9206 | (define_split | |
9207 | [(set (match_operand:SI 0 "gen_reg_operand" "") | |
9208 | (sign_extend:SI (match_operand:HI 1 "gen_reg_operand" "")))] | |
9209 | "" | |
9210 | [(set (match_dup 0) | |
9211 | (ashift:SI (match_dup 1) | |
9212 | (const_int 16))) | |
9213 | (set (match_dup 0) | |
9214 | (ashiftrt:SI (match_dup 0) | |
9215 | (const_int 16)))] | |
9216 | " | |
9217 | @{ operands[1] = gen_lowpart (SImode, operands[1]); @}") | |
9218 | @end smallexample | |
9219 | ||
9220 | When the combiner phase tries to split an insn pattern, it is always the | |
9221 | case that the pattern is @emph{not} matched by any @code{define_insn}. | |
9222 | The combiner pass first tries to split a single @code{set} expression | |
9223 | and then the same @code{set} expression inside a @code{parallel}, but | |
9224 | followed by a @code{clobber} of a pseudo-reg to use as a scratch | |
9225 | register. In these cases, the combiner expects exactly one or two new insn | |
9226 | patterns to be generated. It will verify that these patterns match some | |
9227 | @code{define_insn} definitions, so you need not do this test in the | |
9228 | @code{define_split} (of course, there is no point in writing a | |
9229 | @code{define_split} that will never produce insns that match). | |
9230 | ||
9231 | Here is an example of this use of @code{define_split}, taken from | |
9232 | @file{rs6000.md}: | |
9233 | ||
9234 | @smallexample | |
9235 | (define_split | |
9236 | [(set (match_operand:SI 0 "gen_reg_operand" "") | |
9237 | (plus:SI (match_operand:SI 1 "gen_reg_operand" "") | |
9238 | (match_operand:SI 2 "non_add_cint_operand" "")))] | |
9239 | "" | |
9240 | [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3))) | |
9241 | (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))] | |
9242 | " | |
9243 | @{ | |
9244 | int low = INTVAL (operands[2]) & 0xffff; | |
9245 | int high = (unsigned) INTVAL (operands[2]) >> 16; | |
9246 | ||
9247 | if (low & 0x8000) | |
9248 | high++, low |= 0xffff0000; | |
9249 | ||
9250 | operands[3] = GEN_INT (high << 16); | |
9251 | operands[4] = GEN_INT (low); | |
9252 | @}") | |
9253 | @end smallexample | |
9254 | ||
9255 | Here the predicate @code{non_add_cint_operand} matches any | |
9256 | @code{const_int} that is @emph{not} a valid operand of a single add | |
9257 | insn. The add with the smaller displacement is written so that it | |
9258 | can be substituted into the address of a subsequent operation. | |
9259 | ||
9260 | An example that uses a scratch register, from the same file, generates | |
9261 | an equality comparison of a register and a large constant: | |
9262 | ||
9263 | @smallexample | |
9264 | (define_split | |
9265 | [(set (match_operand:CC 0 "cc_reg_operand" "") | |
9266 | (compare:CC (match_operand:SI 1 "gen_reg_operand" "") | |
9267 | (match_operand:SI 2 "non_short_cint_operand" ""))) | |
9268 | (clobber (match_operand:SI 3 "gen_reg_operand" ""))] | |
9269 | "find_single_use (operands[0], insn, 0) | |
9270 | && (GET_CODE (*find_single_use (operands[0], insn, 0)) == EQ | |
9271 | || GET_CODE (*find_single_use (operands[0], insn, 0)) == NE)" | |
9272 | [(set (match_dup 3) (xor:SI (match_dup 1) (match_dup 4))) | |
9273 | (set (match_dup 0) (compare:CC (match_dup 3) (match_dup 5)))] | |
9274 | " | |
9275 | @{ | |
9276 | /* @r{Get the constant we are comparing against, C, and see what it | |
9277 | looks like sign-extended to 16 bits. Then see what constant | |
9278 | could be XOR'ed with C to get the sign-extended value.} */ | |
9279 | ||
9280 | int c = INTVAL (operands[2]); | |
9281 | int sextc = (c << 16) >> 16; | |
9282 | int xorv = c ^ sextc; | |
9283 | ||
9284 | operands[4] = GEN_INT (xorv); | |
9285 | operands[5] = GEN_INT (sextc); | |
9286 | @}") | |
9287 | @end smallexample | |
9288 | ||
9289 | To avoid confusion, don't write a single @code{define_split} that | |
9290 | accepts some insns that match some @code{define_insn} as well as some | |
9291 | insns that don't. Instead, write two separate @code{define_split} | |
9292 | definitions, one for the insns that are valid and one for the insns that | |
9293 | are not valid. | |
9294 | ||
59b4a555 HPN |
9295 | The splitter is allowed to split jump instructions into a sequence of jumps or |
9296 | create new jumps while splitting non-jump instructions. As the control flow | |
9297 | graph and branch prediction information needs to be updated after the splitter | |
9298 | runs, several restrictions apply. | |
9299 | ||
9300 | Splitting of a jump instruction into a sequence that has another jump | |
9301 | instruction to the same label is always valid, as the compiler expects | |
9302 | identical behavior of the new jump. When the new sequence contains multiple | |
9303 | jump instructions or new labels, more assistance is needed. The splitter is | |
9304 | permitted to create only unconditional jumps, or simple conditional jump | |
9305 | instructions. Additionally it must attach a @code{REG_BR_PROB} note to each | |
9306 | conditional jump. A global variable @code{split_branch_probability} holds the | |
9307 | probability of the original branch in case it was a simple conditional jump, | |
9308 | @minus{}1 otherwise. To simplify recomputing of edge frequencies, the new | |
9309 | sequence is permitted to have only forward jumps to the newly-created labels. | |
d77de738 ML |
9310 | |
9311 | @findex define_insn_and_split | |
9312 | For the common case where the pattern of a define_split exactly matches the | |
9313 | pattern of a define_insn, use @code{define_insn_and_split}. It looks like | |
9314 | this: | |
9315 | ||
9316 | @smallexample | |
9317 | (define_insn_and_split | |
9318 | [@var{insn-pattern}] | |
9319 | "@var{condition}" | |
9320 | "@var{output-template}" | |
9321 | "@var{split-condition}" | |
9322 | [@var{new-insn-pattern-1} | |
9323 | @var{new-insn-pattern-2} | |
9324 | @dots{}] | |
9325 | "@var{preparation-statements}" | |
9326 | [@var{insn-attributes}]) | |
9327 | ||
9328 | @end smallexample | |
9329 | ||
9330 | @var{insn-pattern}, @var{condition}, @var{output-template}, and | |
9331 | @var{insn-attributes} are used as in @code{define_insn}. The | |
9332 | @var{new-insn-pattern} vector and the @var{preparation-statements} are used as | |
9333 | in a @code{define_split}. The @var{split-condition} is also used as in | |
9334 | @code{define_split}, with the additional behavior that if the condition starts | |
9335 | with @samp{&&}, the condition used for the split will be the constructed as a | |
9336 | logical ``and'' of the split condition with the insn condition. For example, | |
9337 | from i386.md: | |
9338 | ||
9339 | @smallexample | |
9340 | (define_insn_and_split "zero_extendhisi2_and" | |
9341 | [(set (match_operand:SI 0 "register_operand" "=r") | |
9342 | (zero_extend:SI (match_operand:HI 1 "register_operand" "0"))) | |
9343 | (clobber (reg:CC 17))] | |
9344 | "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size" | |
9345 | "#" | |
9346 | "&& reload_completed" | |
9347 | [(parallel [(set (match_dup 0) | |
9348 | (and:SI (match_dup 0) (const_int 65535))) | |
9349 | (clobber (reg:CC 17))])] | |
9350 | "" | |
9351 | [(set_attr "type" "alu1")]) | |
9352 | ||
9353 | @end smallexample | |
9354 | ||
9355 | In this case, the actual split condition will be | |
9356 | @samp{TARGET_ZERO_EXTEND_WITH_AND && !optimize_size && reload_completed}. | |
9357 | ||
9358 | The @code{define_insn_and_split} construction provides exactly the same | |
9359 | functionality as two separate @code{define_insn} and @code{define_split} | |
9360 | patterns. It exists for compactness, and as a maintenance tool to prevent | |
9361 | having to ensure the two patterns' templates match. | |
9362 | ||
9363 | @findex define_insn_and_rewrite | |
9364 | It is sometimes useful to have a @code{define_insn_and_split} | |
9365 | that replaces specific operands of an instruction but leaves the | |
9366 | rest of the instruction pattern unchanged. You can do this directly | |
9367 | with a @code{define_insn_and_split}, but it requires a | |
9368 | @var{new-insn-pattern-1} that repeats most of the original @var{insn-pattern}. | |
9369 | There is also the complication that an implicit @code{parallel} in | |
9370 | @var{insn-pattern} must become an explicit @code{parallel} in | |
9371 | @var{new-insn-pattern-1}, which is easy to overlook. | |
9372 | A simpler alternative is to use @code{define_insn_and_rewrite}, which | |
9373 | is a form of @code{define_insn_and_split} that automatically generates | |
9374 | @var{new-insn-pattern-1} by replacing each @code{match_operand} | |
9375 | in @var{insn-pattern} with a corresponding @code{match_dup}, and each | |
9376 | @code{match_operator} in the pattern with a corresponding @code{match_op_dup}. | |
9377 | The arguments are otherwise identical to @code{define_insn_and_split}: | |
9378 | ||
9379 | @smallexample | |
9380 | (define_insn_and_rewrite | |
9381 | [@var{insn-pattern}] | |
9382 | "@var{condition}" | |
9383 | "@var{output-template}" | |
9384 | "@var{split-condition}" | |
9385 | "@var{preparation-statements}" | |
9386 | [@var{insn-attributes}]) | |
9387 | @end smallexample | |
9388 | ||
9389 | The @code{match_dup}s and @code{match_op_dup}s in the new | |
9390 | instruction pattern use any new operand values that the | |
9391 | @var{preparation-statements} store in the @code{operands} array, | |
9392 | as for a normal @code{define_insn_and_split}. @var{preparation-statements} | |
9393 | can also emit additional instructions before the new instruction. | |
9394 | They can even emit an entirely different sequence of instructions and | |
9395 | use @code{DONE} to avoid emitting a new form of the original | |
9396 | instruction. | |
9397 | ||
9398 | The split in a @code{define_insn_and_rewrite} is only intended | |
9399 | to apply to existing instructions that match @var{insn-pattern}. | |
9400 | @var{split-condition} must therefore start with @code{&&}, | |
9401 | so that the split condition applies on top of @var{condition}. | |
9402 | ||
9403 | Here is an example from the AArch64 SVE port, in which operand 1 is | |
9404 | known to be equivalent to an all-true constant and isn't used by the | |
9405 | output template: | |
9406 | ||
9407 | @smallexample | |
9408 | (define_insn_and_rewrite "*while_ult<GPI:mode><PRED_ALL:mode>_cc" | |
9409 | [(set (reg:CC CC_REGNUM) | |
9410 | (compare:CC | |
9411 | (unspec:SI [(match_operand:PRED_ALL 1) | |
9412 | (unspec:PRED_ALL | |
9413 | [(match_operand:GPI 2 "aarch64_reg_or_zero" "rZ") | |
9414 | (match_operand:GPI 3 "aarch64_reg_or_zero" "rZ")] | |
9415 | UNSPEC_WHILE_LO)] | |
9416 | UNSPEC_PTEST_PTRUE) | |
9417 | (const_int 0))) | |
9418 | (set (match_operand:PRED_ALL 0 "register_operand" "=Upa") | |
9419 | (unspec:PRED_ALL [(match_dup 2) | |
9420 | (match_dup 3)] | |
9421 | UNSPEC_WHILE_LO))] | |
9422 | "TARGET_SVE" | |
9423 | "whilelo\t%0.<PRED_ALL:Vetype>, %<w>2, %<w>3" | |
9424 | ;; Force the compiler to drop the unused predicate operand, so that we | |
9425 | ;; don't have an unnecessary PTRUE. | |
9426 | "&& !CONSTANT_P (operands[1])" | |
9427 | @{ | |
9428 | operands[1] = CONSTM1_RTX (<MODE>mode); | |
9429 | @} | |
9430 | ) | |
9431 | @end smallexample | |
9432 | ||
9433 | The splitter in this case simply replaces operand 1 with the constant | |
9434 | value that it is known to have. The equivalent @code{define_insn_and_split} | |
9435 | would be: | |
9436 | ||
9437 | @smallexample | |
9438 | (define_insn_and_split "*while_ult<GPI:mode><PRED_ALL:mode>_cc" | |
9439 | [(set (reg:CC CC_REGNUM) | |
9440 | (compare:CC | |
9441 | (unspec:SI [(match_operand:PRED_ALL 1) | |
9442 | (unspec:PRED_ALL | |
9443 | [(match_operand:GPI 2 "aarch64_reg_or_zero" "rZ") | |
9444 | (match_operand:GPI 3 "aarch64_reg_or_zero" "rZ")] | |
9445 | UNSPEC_WHILE_LO)] | |
9446 | UNSPEC_PTEST_PTRUE) | |
9447 | (const_int 0))) | |
9448 | (set (match_operand:PRED_ALL 0 "register_operand" "=Upa") | |
9449 | (unspec:PRED_ALL [(match_dup 2) | |
9450 | (match_dup 3)] | |
9451 | UNSPEC_WHILE_LO))] | |
9452 | "TARGET_SVE" | |
9453 | "whilelo\t%0.<PRED_ALL:Vetype>, %<w>2, %<w>3" | |
9454 | ;; Force the compiler to drop the unused predicate operand, so that we | |
9455 | ;; don't have an unnecessary PTRUE. | |
9456 | "&& !CONSTANT_P (operands[1])" | |
9457 | [(parallel | |
9458 | [(set (reg:CC CC_REGNUM) | |
9459 | (compare:CC | |
9460 | (unspec:SI [(match_dup 1) | |
9461 | (unspec:PRED_ALL [(match_dup 2) | |
9462 | (match_dup 3)] | |
9463 | UNSPEC_WHILE_LO)] | |
9464 | UNSPEC_PTEST_PTRUE) | |
9465 | (const_int 0))) | |
9466 | (set (match_dup 0) | |
9467 | (unspec:PRED_ALL [(match_dup 2) | |
9468 | (match_dup 3)] | |
9469 | UNSPEC_WHILE_LO))])] | |
9470 | @{ | |
9471 | operands[1] = CONSTM1_RTX (<MODE>mode); | |
9472 | @} | |
9473 | ) | |
9474 | @end smallexample | |
9475 | ||
9476 | @end ifset | |
9477 | @ifset INTERNALS | |
9478 | @node Including Patterns | |
9479 | @section Including Patterns in Machine Descriptions. | |
9480 | @cindex insn includes | |
9481 | ||
9482 | @findex include | |
9483 | The @code{include} pattern tells the compiler tools where to | |
9484 | look for patterns that are in files other than in the file | |
9485 | @file{.md}. This is used only at build time and there is no preprocessing allowed. | |
9486 | ||
9487 | It looks like: | |
9488 | ||
9489 | @smallexample | |
9490 | ||
099515c7 | 9491 | (include @var{pathname}) |
d77de738 ML |
9492 | @end smallexample |
9493 | ||
9494 | For example: | |
9495 | ||
9496 | @smallexample | |
9497 | ||
9498 | (include "filestuff") | |
9499 | ||
9500 | @end smallexample | |
9501 | ||
9502 | Where @var{pathname} is a string that specifies the location of the file, | |
9503 | specifies the include file to be in @file{gcc/config/target/filestuff}. The | |
9504 | directory @file{gcc/config/target} is regarded as the default directory. | |
9505 | ||
9506 | ||
9507 | Machine descriptions may be split up into smaller more manageable subsections | |
9508 | and placed into subdirectories. | |
9509 | ||
9510 | By specifying: | |
9511 | ||
9512 | @smallexample | |
9513 | ||
9514 | (include "BOGUS/filestuff") | |
9515 | ||
9516 | @end smallexample | |
9517 | ||
9518 | the include file is specified to be in @file{gcc/config/@var{target}/BOGUS/filestuff}. | |
9519 | ||
9520 | Specifying an absolute path for the include file such as; | |
9521 | @smallexample | |
9522 | ||
9523 | (include "/u2/BOGUS/filestuff") | |
9524 | ||
9525 | @end smallexample | |
9526 | is permitted but is not encouraged. | |
9527 | ||
9528 | @subsection RTL Generation Tool Options for Directory Search | |
9529 | @cindex directory options .md | |
9530 | @cindex options, directory search | |
9531 | @cindex search options | |
9532 | ||
9533 | The @option{-I@var{dir}} option specifies directories to search for machine descriptions. | |
9534 | For example: | |
9535 | ||
9536 | @smallexample | |
9537 | ||
9538 | genrecog -I/p1/abc/proc1 -I/p2/abcd/pro2 target.md | |
9539 | ||
9540 | @end smallexample | |
9541 | ||
9542 | ||
9543 | Add the directory @var{dir} to the head of the list of directories to be | |
9544 | searched for header files. This can be used to override a system machine definition | |
9545 | file, substituting your own version, since these directories are | |
9546 | searched before the default machine description file directories. If you use more than | |
9547 | one @option{-I} option, the directories are scanned in left-to-right | |
9548 | order; the standard default directory come after. | |
9549 | ||
9550 | ||
9551 | @end ifset | |
9552 | @ifset INTERNALS | |
9553 | @node Peephole Definitions | |
9554 | @section Machine-Specific Peephole Optimizers | |
9555 | @cindex peephole optimizer definitions | |
9556 | @cindex defining peephole optimizers | |
9557 | ||
9558 | In addition to instruction patterns the @file{md} file may contain | |
9559 | definitions of machine-specific peephole optimizations. | |
9560 | ||
9561 | The combiner does not notice certain peephole optimizations when the data | |
9562 | flow in the program does not suggest that it should try them. For example, | |
9563 | sometimes two consecutive insns related in purpose can be combined even | |
9564 | though the second one does not appear to use a register computed in the | |
9565 | first one. A machine-specific peephole optimizer can detect such | |
9566 | opportunities. | |
9567 | ||
9568 | There are two forms of peephole definitions that may be used. The | |
9569 | original @code{define_peephole} is run at assembly output time to | |
9570 | match insns and substitute assembly text. Use of @code{define_peephole} | |
9571 | is deprecated. | |
9572 | ||
9573 | A newer @code{define_peephole2} matches insns and substitutes new | |
9574 | insns. The @code{peephole2} pass is run after register allocation | |
9575 | but before scheduling, which may result in much better code for | |
9576 | targets that do scheduling. | |
9577 | ||
9578 | @menu | |
9579 | * define_peephole:: RTL to Text Peephole Optimizers | |
9580 | * define_peephole2:: RTL to RTL Peephole Optimizers | |
9581 | @end menu | |
9582 | ||
9583 | @end ifset | |
9584 | @ifset INTERNALS | |
9585 | @node define_peephole | |
9586 | @subsection RTL to Text Peephole Optimizers | |
9587 | @findex define_peephole | |
9588 | ||
9589 | @need 1000 | |
9590 | A definition looks like this: | |
9591 | ||
9592 | @smallexample | |
9593 | (define_peephole | |
9594 | [@var{insn-pattern-1} | |
9595 | @var{insn-pattern-2} | |
9596 | @dots{}] | |
9597 | "@var{condition}" | |
9598 | "@var{template}" | |
9599 | "@var{optional-insn-attributes}") | |
9600 | @end smallexample | |
9601 | ||
9602 | @noindent | |
9603 | The last string operand may be omitted if you are not using any | |
9604 | machine-specific information in this machine description. If present, | |
9605 | it must obey the same rules as in a @code{define_insn}. | |
9606 | ||
9607 | In this skeleton, @var{insn-pattern-1} and so on are patterns to match | |
9608 | consecutive insns. The optimization applies to a sequence of insns when | |
9609 | @var{insn-pattern-1} matches the first one, @var{insn-pattern-2} matches | |
9610 | the next, and so on. | |
9611 | ||
9612 | Each of the insns matched by a peephole must also match a | |
9613 | @code{define_insn}. Peepholes are checked only at the last stage just | |
9614 | before code generation, and only optionally. Therefore, any insn which | |
9615 | would match a peephole but no @code{define_insn} will cause a crash in code | |
9616 | generation in an unoptimized compilation, or at various optimization | |
9617 | stages. | |
9618 | ||
9619 | The operands of the insns are matched with @code{match_operands}, | |
9620 | @code{match_operator}, and @code{match_dup}, as usual. What is not | |
9621 | usual is that the operand numbers apply to all the insn patterns in the | |
9622 | definition. So, you can check for identical operands in two insns by | |
9623 | using @code{match_operand} in one insn and @code{match_dup} in the | |
9624 | other. | |
9625 | ||
9626 | The operand constraints used in @code{match_operand} patterns do not have | |
9627 | any direct effect on the applicability of the peephole, but they will | |
9628 | be validated afterward, so make sure your constraints are general enough | |
9629 | to apply whenever the peephole matches. If the peephole matches | |
9630 | but the constraints are not satisfied, the compiler will crash. | |
9631 | ||
9632 | It is safe to omit constraints in all the operands of the peephole; or | |
9633 | you can write constraints which serve as a double-check on the criteria | |
9634 | previously tested. | |
9635 | ||
9636 | Once a sequence of insns matches the patterns, the @var{condition} is | |
9637 | checked. This is a C expression which makes the final decision whether to | |
9638 | perform the optimization (we do so if the expression is nonzero). If | |
9639 | @var{condition} is omitted (in other words, the string is empty) then the | |
9640 | optimization is applied to every sequence of insns that matches the | |
9641 | patterns. | |
9642 | ||
9643 | The defined peephole optimizations are applied after register allocation | |
9644 | is complete. Therefore, the peephole definition can check which | |
9645 | operands have ended up in which kinds of registers, just by looking at | |
9646 | the operands. | |
9647 | ||
9648 | @findex prev_active_insn | |
9649 | The way to refer to the operands in @var{condition} is to write | |
9650 | @code{operands[@var{i}]} for operand number @var{i} (as matched by | |
9651 | @code{(match_operand @var{i} @dots{})}). Use the variable @code{insn} | |
9652 | to refer to the last of the insns being matched; use | |
9653 | @code{prev_active_insn} to find the preceding insns. | |
9654 | ||
9655 | @findex dead_or_set_p | |
9656 | When optimizing computations with intermediate results, you can use | |
9657 | @var{condition} to match only when the intermediate results are not used | |
9658 | elsewhere. Use the C expression @code{dead_or_set_p (@var{insn}, | |
9659 | @var{op})}, where @var{insn} is the insn in which you expect the value | |
9660 | to be used for the last time (from the value of @code{insn}, together | |
9661 | with use of @code{prev_nonnote_insn}), and @var{op} is the intermediate | |
9662 | value (from @code{operands[@var{i}]}). | |
9663 | ||
9664 | Applying the optimization means replacing the sequence of insns with one | |
9665 | new insn. The @var{template} controls ultimate output of assembler code | |
9666 | for this combined insn. It works exactly like the template of a | |
9667 | @code{define_insn}. Operand numbers in this template are the same ones | |
9668 | used in matching the original sequence of insns. | |
9669 | ||
9670 | The result of a defined peephole optimizer does not need to match any of | |
9671 | the insn patterns in the machine description; it does not even have an | |
9672 | opportunity to match them. The peephole optimizer definition itself serves | |
9673 | as the insn pattern to control how the insn is output. | |
9674 | ||
9675 | Defined peephole optimizers are run as assembler code is being output, | |
9676 | so the insns they produce are never combined or rearranged in any way. | |
9677 | ||
9678 | Here is an example, taken from the 68000 machine description: | |
9679 | ||
9680 | @smallexample | |
9681 | (define_peephole | |
9682 | [(set (reg:SI 15) (plus:SI (reg:SI 15) (const_int 4))) | |
9683 | (set (match_operand:DF 0 "register_operand" "=f") | |
9684 | (match_operand:DF 1 "register_operand" "ad"))] | |
9685 | "FP_REG_P (operands[0]) && ! FP_REG_P (operands[1])" | |
9686 | @{ | |
9687 | rtx xoperands[2]; | |
9688 | xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1); | |
9689 | #ifdef MOTOROLA | |
9690 | output_asm_insn ("move.l %1,(sp)", xoperands); | |
9691 | output_asm_insn ("move.l %1,-(sp)", operands); | |
9692 | return "fmove.d (sp)+,%0"; | |
9693 | #else | |
9694 | output_asm_insn ("movel %1,sp@@", xoperands); | |
9695 | output_asm_insn ("movel %1,sp@@-", operands); | |
9696 | return "fmoved sp@@+,%0"; | |
9697 | #endif | |
9698 | @}) | |
9699 | @end smallexample | |
9700 | ||
9701 | @need 1000 | |
9702 | The effect of this optimization is to change | |
9703 | ||
9704 | @smallexample | |
9705 | @group | |
9706 | jbsr _foobar | |
9707 | addql #4,sp | |
9708 | movel d1,sp@@- | |
9709 | movel d0,sp@@- | |
9710 | fmoved sp@@+,fp0 | |
9711 | @end group | |
9712 | @end smallexample | |
9713 | ||
9714 | @noindent | |
9715 | into | |
9716 | ||
9717 | @smallexample | |
9718 | @group | |
9719 | jbsr _foobar | |
9720 | movel d1,sp@@ | |
9721 | movel d0,sp@@- | |
9722 | fmoved sp@@+,fp0 | |
9723 | @end group | |
9724 | @end smallexample | |
9725 | ||
9726 | @ignore | |
9727 | @findex CC_REVERSED | |
9728 | If a peephole matches a sequence including one or more jump insns, you must | |
9729 | take account of the flags such as @code{CC_REVERSED} which specify that the | |
9730 | condition codes are represented in an unusual manner. The compiler | |
9731 | automatically alters any ordinary conditional jumps which occur in such | |
9732 | situations, but the compiler cannot alter jumps which have been replaced by | |
9733 | peephole optimizations. So it is up to you to alter the assembler code | |
9734 | that the peephole produces. Supply C code to write the assembler output, | |
9735 | and in this C code check the condition code status flags and change the | |
9736 | assembler code as appropriate. | |
9737 | @end ignore | |
9738 | ||
9739 | @var{insn-pattern-1} and so on look @emph{almost} like the second | |
9740 | operand of @code{define_insn}. There is one important difference: the | |
9741 | second operand of @code{define_insn} consists of one or more RTX's | |
9742 | enclosed in square brackets. Usually, there is only one: then the same | |
9743 | action can be written as an element of a @code{define_peephole}. But | |
9744 | when there are multiple actions in a @code{define_insn}, they are | |
9745 | implicitly enclosed in a @code{parallel}. Then you must explicitly | |
9746 | write the @code{parallel}, and the square brackets within it, in the | |
9747 | @code{define_peephole}. Thus, if an insn pattern looks like this, | |
9748 | ||
9749 | @smallexample | |
9750 | (define_insn "divmodsi4" | |
9751 | [(set (match_operand:SI 0 "general_operand" "=d") | |
9752 | (div:SI (match_operand:SI 1 "general_operand" "0") | |
9753 | (match_operand:SI 2 "general_operand" "dmsK"))) | |
9754 | (set (match_operand:SI 3 "general_operand" "=d") | |
9755 | (mod:SI (match_dup 1) (match_dup 2)))] | |
9756 | "TARGET_68020" | |
9757 | "divsl%.l %2,%3:%0") | |
9758 | @end smallexample | |
9759 | ||
9760 | @noindent | |
9761 | then the way to mention this insn in a peephole is as follows: | |
9762 | ||
9763 | @smallexample | |
9764 | (define_peephole | |
9765 | [@dots{} | |
9766 | (parallel | |
9767 | [(set (match_operand:SI 0 "general_operand" "=d") | |
9768 | (div:SI (match_operand:SI 1 "general_operand" "0") | |
9769 | (match_operand:SI 2 "general_operand" "dmsK"))) | |
9770 | (set (match_operand:SI 3 "general_operand" "=d") | |
9771 | (mod:SI (match_dup 1) (match_dup 2)))]) | |
9772 | @dots{}] | |
9773 | @dots{}) | |
9774 | @end smallexample | |
9775 | ||
9776 | @end ifset | |
9777 | @ifset INTERNALS | |
9778 | @node define_peephole2 | |
9779 | @subsection RTL to RTL Peephole Optimizers | |
9780 | @findex define_peephole2 | |
9781 | ||
9782 | The @code{define_peephole2} definition tells the compiler how to | |
9783 | substitute one sequence of instructions for another sequence, | |
9784 | what additional scratch registers may be needed and what their | |
9785 | lifetimes must be. | |
9786 | ||
9787 | @smallexample | |
9788 | (define_peephole2 | |
9789 | [@var{insn-pattern-1} | |
9790 | @var{insn-pattern-2} | |
9791 | @dots{}] | |
9792 | "@var{condition}" | |
9793 | [@var{new-insn-pattern-1} | |
9794 | @var{new-insn-pattern-2} | |
9795 | @dots{}] | |
9796 | "@var{preparation-statements}") | |
9797 | @end smallexample | |
9798 | ||
9799 | The definition is almost identical to @code{define_split} | |
9800 | (@pxref{Insn Splitting}) except that the pattern to match is not a | |
9801 | single instruction, but a sequence of instructions. | |
9802 | ||
9803 | It is possible to request additional scratch registers for use in the | |
9804 | output template. If appropriate registers are not free, the pattern | |
9805 | will simply not match. | |
9806 | ||
9807 | @findex match_scratch | |
9808 | @findex match_dup | |
9809 | Scratch registers are requested with a @code{match_scratch} pattern at | |
9810 | the top level of the input pattern. The allocated register (initially) will | |
9811 | be dead at the point requested within the original sequence. If the scratch | |
9812 | is used at more than a single point, a @code{match_dup} pattern at the | |
9813 | top level of the input pattern marks the last position in the input sequence | |
9814 | at which the register must be available. | |
9815 | ||
9816 | Here is an example from the IA-32 machine description: | |
9817 | ||
9818 | @smallexample | |
9819 | (define_peephole2 | |
9820 | [(match_scratch:SI 2 "r") | |
9821 | (parallel [(set (match_operand:SI 0 "register_operand" "") | |
9822 | (match_operator:SI 3 "arith_or_logical_operator" | |
9823 | [(match_dup 0) | |
9824 | (match_operand:SI 1 "memory_operand" "")])) | |
9825 | (clobber (reg:CC 17))])] | |
9826 | "! optimize_size && ! TARGET_READ_MODIFY" | |
9827 | [(set (match_dup 2) (match_dup 1)) | |
9828 | (parallel [(set (match_dup 0) | |
9829 | (match_op_dup 3 [(match_dup 0) (match_dup 2)])) | |
9830 | (clobber (reg:CC 17))])] | |
9831 | "") | |
9832 | @end smallexample | |
9833 | ||
9834 | @noindent | |
9835 | This pattern tries to split a load from its use in the hopes that we'll be | |
9836 | able to schedule around the memory load latency. It allocates a single | |
9837 | @code{SImode} register of class @code{GENERAL_REGS} (@code{"r"}) that needs | |
9838 | to be live only at the point just before the arithmetic. | |
9839 | ||
9840 | A real example requiring extended scratch lifetimes is harder to come by, | |
9841 | so here's a silly made-up example: | |
9842 | ||
9843 | @smallexample | |
9844 | (define_peephole2 | |
9845 | [(match_scratch:SI 4 "r") | |
9846 | (set (match_operand:SI 0 "" "") (match_operand:SI 1 "" "")) | |
9847 | (set (match_operand:SI 2 "" "") (match_dup 1)) | |
9848 | (match_dup 4) | |
9849 | (set (match_operand:SI 3 "" "") (match_dup 1))] | |
9850 | "/* @r{determine 1 does not overlap 0 and 2} */" | |
9851 | [(set (match_dup 4) (match_dup 1)) | |
9852 | (set (match_dup 0) (match_dup 4)) | |
9853 | (set (match_dup 2) (match_dup 4)) | |
9854 | (set (match_dup 3) (match_dup 4))] | |
9855 | "") | |
9856 | @end smallexample | |
9857 | ||
74544bda AC |
9858 | @noindent |
9859 | If we had not added the @code{(match_dup 4)} in the middle of the input | |
9860 | sequence, it might have been the case that the register we chose at the | |
9861 | beginning of the sequence is killed by the first or second @code{set}. | |
9862 | ||
d77de738 ML |
9863 | There are two special macros defined for use in the preparation statements: |
9864 | @code{DONE} and @code{FAIL}. Use them with a following semicolon, | |
9865 | as a statement. | |
9866 | ||
9867 | @table @code | |
9868 | ||
9869 | @findex DONE | |
9870 | @item DONE | |
9871 | Use the @code{DONE} macro to end RTL generation for the peephole. The | |
9872 | only RTL insns generated as replacement for the matched input insn will | |
9873 | be those already emitted by explicit calls to @code{emit_insn} within | |
9874 | the preparation statements; the replacement pattern is not used. | |
9875 | ||
9876 | @findex FAIL | |
9877 | @item FAIL | |
9878 | Make the @code{define_peephole2} fail on this occasion. When a @code{define_peephole2} | |
9879 | fails, it means that the replacement was not truly available for the | |
9880 | particular inputs it was given. In that case, GCC may still apply a | |
9881 | later @code{define_peephole2} that also matches the given insn pattern. | |
9882 | (Note that this is different from @code{define_split}, where @code{FAIL} | |
9883 | prevents the input insn from being split at all.) | |
9884 | @end table | |
9885 | ||
9886 | If the preparation falls through (invokes neither @code{DONE} nor | |
9887 | @code{FAIL}), then the @code{define_peephole2} uses the replacement | |
9888 | template. | |
9889 | ||
07527e3e HPN |
9890 | Insns are scanned in forward order from beginning to end for each basic |
9891 | block. Matches are attempted in order of @code{define_peephole2} | |
9892 | appearance in the @file{md} file. After a successful replacement, | |
9893 | scanning for further opportunities for @code{define_peephole2}, resumes | |
9894 | with the first generated replacement insn as the first insn to be | |
9895 | matched against all @code{define_peephole2}. For the example above, | |
9896 | after its successful replacement, the first insn that can be matched by | |
9897 | a @code{define_peephole2} is @code{(set (match_dup 4) (match_dup 1))}. | |
9898 | ||
d77de738 ML |
9899 | @end ifset |
9900 | @ifset INTERNALS | |
9901 | @node Insn Attributes | |
9902 | @section Instruction Attributes | |
9903 | @cindex insn attributes | |
9904 | @cindex instruction attributes | |
9905 | ||
9906 | In addition to describing the instruction supported by the target machine, | |
9907 | the @file{md} file also defines a group of @dfn{attributes} and a set of | |
9908 | values for each. Every generated insn is assigned a value for each attribute. | |
9909 | One possible attribute would be the effect that the insn has on the machine's | |
9910 | condition code. | |
9911 | ||
9912 | @menu | |
9913 | * Defining Attributes:: Specifying attributes and their values. | |
9914 | * Expressions:: Valid expressions for attribute values. | |
9915 | * Tagging Insns:: Assigning attribute values to insns. | |
9916 | * Attr Example:: An example of assigning attributes. | |
9917 | * Insn Lengths:: Computing the length of insns. | |
9918 | * Constant Attributes:: Defining attributes that are constant. | |
9919 | * Mnemonic Attribute:: Obtain the instruction mnemonic as attribute value. | |
9920 | * Delay Slots:: Defining delay slots required for a machine. | |
9921 | * Processor pipeline description:: Specifying information for insn scheduling. | |
9922 | @end menu | |
9923 | ||
9924 | @end ifset | |
9925 | @ifset INTERNALS | |
9926 | @node Defining Attributes | |
9927 | @subsection Defining Attributes and their Values | |
9928 | @cindex defining attributes and their values | |
9929 | @cindex attributes, defining | |
9930 | ||
9931 | @findex define_attr | |
9932 | The @code{define_attr} expression is used to define each attribute required | |
9933 | by the target machine. It looks like: | |
9934 | ||
9935 | @smallexample | |
9936 | (define_attr @var{name} @var{list-of-values} @var{default}) | |
9937 | @end smallexample | |
9938 | ||
9939 | @var{name} is a string specifying the name of the attribute being | |
9940 | defined. Some attributes are used in a special way by the rest of the | |
9941 | compiler. The @code{enabled} attribute can be used to conditionally | |
9942 | enable or disable insn alternatives (@pxref{Disable Insn | |
9943 | Alternatives}). The @code{predicable} attribute, together with a | |
9944 | suitable @code{define_cond_exec} (@pxref{Conditional Execution}), can | |
9945 | be used to automatically generate conditional variants of instruction | |
9946 | patterns. The @code{mnemonic} attribute can be used to check for the | |
9947 | instruction mnemonic (@pxref{Mnemonic Attribute}). The compiler | |
9948 | internally uses the names @code{ce_enabled} and @code{nonce_enabled}, | |
9949 | so they should not be used elsewhere as alternative names. | |
9950 | ||
9951 | @var{list-of-values} is either a string that specifies a comma-separated | |
9952 | list of values that can be assigned to the attribute, or a null string to | |
9953 | indicate that the attribute takes numeric values. | |
9954 | ||
9955 | @var{default} is an attribute expression that gives the value of this | |
9956 | attribute for insns that match patterns whose definition does not include | |
9957 | an explicit value for this attribute. @xref{Attr Example}, for more | |
9958 | information on the handling of defaults. @xref{Constant Attributes}, | |
9959 | for information on attributes that do not depend on any particular insn. | |
9960 | ||
9961 | @findex insn-attr.h | |
9962 | For each defined attribute, a number of definitions are written to the | |
9963 | @file{insn-attr.h} file. For cases where an explicit set of values is | |
9964 | specified for an attribute, the following are defined: | |
9965 | ||
9966 | @itemize @bullet | |
9967 | @item | |
9968 | A @samp{#define} is written for the symbol @samp{HAVE_ATTR_@var{name}}. | |
9969 | ||
9970 | @item | |
9971 | An enumerated class is defined for @samp{attr_@var{name}} with | |
9972 | elements of the form @samp{@var{upper-name}_@var{upper-value}} where | |
9973 | the attribute name and value are first converted to uppercase. | |
9974 | ||
9975 | @item | |
9976 | A function @samp{get_attr_@var{name}} is defined that is passed an insn and | |
9977 | returns the attribute value for that insn. | |
9978 | @end itemize | |
9979 | ||
9980 | For example, if the following is present in the @file{md} file: | |
9981 | ||
9982 | @smallexample | |
9983 | (define_attr "type" "branch,fp,load,store,arith" @dots{}) | |
9984 | @end smallexample | |
9985 | ||
9986 | @noindent | |
9987 | the following lines will be written to the file @file{insn-attr.h}. | |
9988 | ||
9989 | @smallexample | |
9990 | #define HAVE_ATTR_type 1 | |
9991 | enum attr_type @{TYPE_BRANCH, TYPE_FP, TYPE_LOAD, | |
9992 | TYPE_STORE, TYPE_ARITH@}; | |
9993 | extern enum attr_type get_attr_type (); | |
9994 | @end smallexample | |
9995 | ||
9996 | If the attribute takes numeric values, no @code{enum} type will be | |
9997 | defined and the function to obtain the attribute's value will return | |
9998 | @code{int}. | |
9999 | ||
10000 | There are attributes which are tied to a specific meaning. These | |
10001 | attributes are not free to use for other purposes: | |
10002 | ||
10003 | @table @code | |
10004 | @item length | |
10005 | The @code{length} attribute is used to calculate the length of emitted | |
10006 | code chunks. This is especially important when verifying branch | |
10007 | distances. @xref{Insn Lengths}. | |
10008 | ||
10009 | @item enabled | |
10010 | The @code{enabled} attribute can be defined to prevent certain | |
10011 | alternatives of an insn definition from being used during code | |
10012 | generation. @xref{Disable Insn Alternatives}. | |
10013 | ||
10014 | @item mnemonic | |
10015 | The @code{mnemonic} attribute can be defined to implement instruction | |
10016 | specific checks in e.g.@: the pipeline description. | |
10017 | @xref{Mnemonic Attribute}. | |
10018 | @end table | |
10019 | ||
10020 | For each of these special attributes, the corresponding | |
10021 | @samp{HAVE_ATTR_@var{name}} @samp{#define} is also written when the | |
10022 | attribute is not defined; in that case, it is defined as @samp{0}. | |
10023 | ||
10024 | @findex define_enum_attr | |
10025 | @anchor{define_enum_attr} | |
10026 | Another way of defining an attribute is to use: | |
10027 | ||
10028 | @smallexample | |
10029 | (define_enum_attr "@var{attr}" "@var{enum}" @var{default}) | |
10030 | @end smallexample | |
10031 | ||
10032 | This works in just the same way as @code{define_attr}, except that | |
10033 | the list of values is taken from a separate enumeration called | |
10034 | @var{enum} (@pxref{define_enum}). This form allows you to use | |
10035 | the same list of values for several attributes without having to | |
10036 | repeat the list each time. For example: | |
10037 | ||
10038 | @smallexample | |
10039 | (define_enum "processor" [ | |
10040 | model_a | |
10041 | model_b | |
10042 | @dots{} | |
10043 | ]) | |
10044 | (define_enum_attr "arch" "processor" | |
10045 | (const (symbol_ref "target_arch"))) | |
10046 | (define_enum_attr "tune" "processor" | |
10047 | (const (symbol_ref "target_tune"))) | |
10048 | @end smallexample | |
10049 | ||
10050 | defines the same attributes as: | |
10051 | ||
10052 | @smallexample | |
10053 | (define_attr "arch" "model_a,model_b,@dots{}" | |
10054 | (const (symbol_ref "target_arch"))) | |
10055 | (define_attr "tune" "model_a,model_b,@dots{}" | |
10056 | (const (symbol_ref "target_tune"))) | |
10057 | @end smallexample | |
10058 | ||
10059 | but without duplicating the processor list. The second example defines two | |
10060 | separate C enums (@code{attr_arch} and @code{attr_tune}) whereas the first | |
10061 | defines a single C enum (@code{processor}). | |
10062 | @end ifset | |
10063 | @ifset INTERNALS | |
10064 | @node Expressions | |
10065 | @subsection Attribute Expressions | |
10066 | @cindex attribute expressions | |
10067 | ||
10068 | RTL expressions used to define attributes use the codes described above | |
10069 | plus a few specific to attribute definitions, to be discussed below. | |
10070 | Attribute value expressions must have one of the following forms: | |
10071 | ||
10072 | @table @code | |
10073 | @cindex @code{const_int} and attributes | |
10074 | @item (const_int @var{i}) | |
10075 | The integer @var{i} specifies the value of a numeric attribute. @var{i} | |
10076 | must be non-negative. | |
10077 | ||
10078 | The value of a numeric attribute can be specified either with a | |
10079 | @code{const_int}, or as an integer represented as a string in | |
10080 | @code{const_string}, @code{eq_attr} (see below), @code{attr}, | |
10081 | @code{symbol_ref}, simple arithmetic expressions, and @code{set_attr} | |
10082 | overrides on specific instructions (@pxref{Tagging Insns}). | |
10083 | ||
10084 | @cindex @code{const_string} and attributes | |
10085 | @item (const_string @var{value}) | |
10086 | The string @var{value} specifies a constant attribute value. | |
10087 | If @var{value} is specified as @samp{"*"}, it means that the default value of | |
10088 | the attribute is to be used for the insn containing this expression. | |
10089 | @samp{"*"} obviously cannot be used in the @var{default} expression | |
10090 | of a @code{define_attr}. | |
10091 | ||
10092 | If the attribute whose value is being specified is numeric, @var{value} | |
10093 | must be a string containing a non-negative integer (normally | |
10094 | @code{const_int} would be used in this case). Otherwise, it must | |
10095 | contain one of the valid values for the attribute. | |
10096 | ||
10097 | @cindex @code{if_then_else} and attributes | |
10098 | @item (if_then_else @var{test} @var{true-value} @var{false-value}) | |
10099 | @var{test} specifies an attribute test, whose format is defined below. | |
10100 | The value of this expression is @var{true-value} if @var{test} is true, | |
10101 | otherwise it is @var{false-value}. | |
10102 | ||
10103 | @cindex @code{cond} and attributes | |
10104 | @item (cond [@var{test1} @var{value1} @dots{}] @var{default}) | |
10105 | The first operand of this expression is a vector containing an even | |
10106 | number of expressions and consisting of pairs of @var{test} and @var{value} | |
10107 | expressions. The value of the @code{cond} expression is that of the | |
10108 | @var{value} corresponding to the first true @var{test} expression. If | |
10109 | none of the @var{test} expressions are true, the value of the @code{cond} | |
10110 | expression is that of the @var{default} expression. | |
10111 | @end table | |
10112 | ||
10113 | @var{test} expressions can have one of the following forms: | |
10114 | ||
10115 | @table @code | |
10116 | @cindex @code{const_int} and attribute tests | |
10117 | @item (const_int @var{i}) | |
10118 | This test is true if @var{i} is nonzero and false otherwise. | |
10119 | ||
10120 | @cindex @code{not} and attributes | |
10121 | @cindex @code{ior} and attributes | |
10122 | @cindex @code{and} and attributes | |
10123 | @item (not @var{test}) | |
10124 | @itemx (ior @var{test1} @var{test2}) | |
10125 | @itemx (and @var{test1} @var{test2}) | |
10126 | These tests are true if the indicated logical function is true. | |
10127 | ||
10128 | @cindex @code{match_operand} and attributes | |
10129 | @item (match_operand:@var{m} @var{n} @var{pred} @var{constraints}) | |
10130 | This test is true if operand @var{n} of the insn whose attribute value | |
10131 | is being determined has mode @var{m} (this part of the test is ignored | |
10132 | if @var{m} is @code{VOIDmode}) and the function specified by the string | |
10133 | @var{pred} returns a nonzero value when passed operand @var{n} and mode | |
10134 | @var{m} (this part of the test is ignored if @var{pred} is the null | |
10135 | string). | |
10136 | ||
10137 | The @var{constraints} operand is ignored and should be the null string. | |
10138 | ||
10139 | @cindex @code{match_test} and attributes | |
10140 | @item (match_test @var{c-expr}) | |
10141 | The test is true if C expression @var{c-expr} is true. In non-constant | |
10142 | attributes, @var{c-expr} has access to the following variables: | |
10143 | ||
10144 | @table @var | |
10145 | @item insn | |
10146 | The rtl instruction under test. | |
10147 | @item which_alternative | |
10148 | The @code{define_insn} alternative that @var{insn} matches. | |
10149 | @xref{Output Statement}. | |
10150 | @item operands | |
10151 | An array of @var{insn}'s rtl operands. | |
10152 | @end table | |
10153 | ||
10154 | @var{c-expr} behaves like the condition in a C @code{if} statement, | |
10155 | so there is no need to explicitly convert the expression into a boolean | |
10156 | 0 or 1 value. For example, the following two tests are equivalent: | |
10157 | ||
10158 | @smallexample | |
10159 | (match_test "x & 2") | |
10160 | (match_test "(x & 2) != 0") | |
10161 | @end smallexample | |
10162 | ||
10163 | @cindex @code{le} and attributes | |
10164 | @cindex @code{leu} and attributes | |
10165 | @cindex @code{lt} and attributes | |
10166 | @cindex @code{gt} and attributes | |
10167 | @cindex @code{gtu} and attributes | |
10168 | @cindex @code{ge} and attributes | |
10169 | @cindex @code{geu} and attributes | |
10170 | @cindex @code{ne} and attributes | |
10171 | @cindex @code{eq} and attributes | |
10172 | @cindex @code{plus} and attributes | |
10173 | @cindex @code{minus} and attributes | |
10174 | @cindex @code{mult} and attributes | |
10175 | @cindex @code{div} and attributes | |
10176 | @cindex @code{mod} and attributes | |
10177 | @cindex @code{abs} and attributes | |
10178 | @cindex @code{neg} and attributes | |
10179 | @cindex @code{ashift} and attributes | |
10180 | @cindex @code{lshiftrt} and attributes | |
10181 | @cindex @code{ashiftrt} and attributes | |
10182 | @item (le @var{arith1} @var{arith2}) | |
10183 | @itemx (leu @var{arith1} @var{arith2}) | |
10184 | @itemx (lt @var{arith1} @var{arith2}) | |
10185 | @itemx (ltu @var{arith1} @var{arith2}) | |
10186 | @itemx (gt @var{arith1} @var{arith2}) | |
10187 | @itemx (gtu @var{arith1} @var{arith2}) | |
10188 | @itemx (ge @var{arith1} @var{arith2}) | |
10189 | @itemx (geu @var{arith1} @var{arith2}) | |
10190 | @itemx (ne @var{arith1} @var{arith2}) | |
10191 | @itemx (eq @var{arith1} @var{arith2}) | |
10192 | These tests are true if the indicated comparison of the two arithmetic | |
10193 | expressions is true. Arithmetic expressions are formed with | |
10194 | @code{plus}, @code{minus}, @code{mult}, @code{div}, @code{mod}, | |
10195 | @code{abs}, @code{neg}, @code{and}, @code{ior}, @code{xor}, @code{not}, | |
10196 | @code{ashift}, @code{lshiftrt}, and @code{ashiftrt} expressions. | |
10197 | ||
10198 | @findex get_attr | |
10199 | @code{const_int} and @code{symbol_ref} are always valid terms (@pxref{Insn | |
10200 | Lengths},for additional forms). @code{symbol_ref} is a string | |
10201 | denoting a C expression that yields an @code{int} when evaluated by the | |
10202 | @samp{get_attr_@dots{}} routine. It should normally be a global | |
10203 | variable. | |
10204 | ||
10205 | @findex eq_attr | |
10206 | @item (eq_attr @var{name} @var{value}) | |
10207 | @var{name} is a string specifying the name of an attribute. | |
10208 | ||
10209 | @var{value} is a string that is either a valid value for attribute | |
10210 | @var{name}, a comma-separated list of values, or @samp{!} followed by a | |
10211 | value or list. If @var{value} does not begin with a @samp{!}, this | |
10212 | test is true if the value of the @var{name} attribute of the current | |
10213 | insn is in the list specified by @var{value}. If @var{value} begins | |
10214 | with a @samp{!}, this test is true if the attribute's value is | |
10215 | @emph{not} in the specified list. | |
10216 | ||
10217 | For example, | |
10218 | ||
10219 | @smallexample | |
10220 | (eq_attr "type" "load,store") | |
10221 | @end smallexample | |
10222 | ||
10223 | @noindent | |
10224 | is equivalent to | |
10225 | ||
10226 | @smallexample | |
10227 | (ior (eq_attr "type" "load") (eq_attr "type" "store")) | |
10228 | @end smallexample | |
10229 | ||
10230 | If @var{name} specifies an attribute of @samp{alternative}, it refers to the | |
10231 | value of the compiler variable @code{which_alternative} | |
10232 | (@pxref{Output Statement}) and the values must be small integers. For | |
10233 | example, | |
10234 | ||
10235 | @smallexample | |
10236 | (eq_attr "alternative" "2,3") | |
10237 | @end smallexample | |
10238 | ||
10239 | @noindent | |
10240 | is equivalent to | |
10241 | ||
10242 | @smallexample | |
10243 | (ior (eq (symbol_ref "which_alternative") (const_int 2)) | |
10244 | (eq (symbol_ref "which_alternative") (const_int 3))) | |
10245 | @end smallexample | |
10246 | ||
10247 | Note that, for most attributes, an @code{eq_attr} test is simplified in cases | |
10248 | where the value of the attribute being tested is known for all insns matching | |
10249 | a particular pattern. This is by far the most common case. | |
10250 | ||
10251 | @findex attr_flag | |
10252 | @item (attr_flag @var{name}) | |
10253 | The value of an @code{attr_flag} expression is true if the flag | |
10254 | specified by @var{name} is true for the @code{insn} currently being | |
10255 | scheduled. | |
10256 | ||
10257 | @var{name} is a string specifying one of a fixed set of flags to test. | |
10258 | Test the flags @code{forward} and @code{backward} to determine the | |
10259 | direction of a conditional branch. | |
10260 | ||
10261 | This example describes a conditional branch delay slot which | |
10262 | can be nullified for forward branches that are taken (annul-true) or | |
10263 | for backward branches which are not taken (annul-false). | |
10264 | ||
10265 | @smallexample | |
10266 | (define_delay (eq_attr "type" "cbranch") | |
10267 | [(eq_attr "in_branch_delay" "true") | |
10268 | (and (eq_attr "in_branch_delay" "true") | |
10269 | (attr_flag "forward")) | |
10270 | (and (eq_attr "in_branch_delay" "true") | |
10271 | (attr_flag "backward"))]) | |
10272 | @end smallexample | |
10273 | ||
10274 | The @code{forward} and @code{backward} flags are false if the current | |
10275 | @code{insn} being scheduled is not a conditional branch. | |
10276 | ||
10277 | @code{attr_flag} is only used during delay slot scheduling and has no | |
10278 | meaning to other passes of the compiler. | |
10279 | ||
10280 | @findex attr | |
10281 | @item (attr @var{name}) | |
10282 | The value of another attribute is returned. This is most useful | |
10283 | for numeric attributes, as @code{eq_attr} and @code{attr_flag} | |
10284 | produce more efficient code for non-numeric attributes. | |
10285 | @end table | |
10286 | ||
10287 | @end ifset | |
10288 | @ifset INTERNALS | |
10289 | @node Tagging Insns | |
10290 | @subsection Assigning Attribute Values to Insns | |
10291 | @cindex tagging insns | |
10292 | @cindex assigning attribute values to insns | |
10293 | ||
10294 | The value assigned to an attribute of an insn is primarily determined by | |
10295 | which pattern is matched by that insn (or which @code{define_peephole} | |
10296 | generated it). Every @code{define_insn} and @code{define_peephole} can | |
10297 | have an optional last argument to specify the values of attributes for | |
10298 | matching insns. The value of any attribute not specified in a particular | |
10299 | insn is set to the default value for that attribute, as specified in its | |
10300 | @code{define_attr}. Extensive use of default values for attributes | |
10301 | permits the specification of the values for only one or two attributes | |
10302 | in the definition of most insn patterns, as seen in the example in the | |
10303 | next section. | |
10304 | ||
10305 | The optional last argument of @code{define_insn} and | |
10306 | @code{define_peephole} is a vector of expressions, each of which defines | |
10307 | the value for a single attribute. The most general way of assigning an | |
10308 | attribute's value is to use a @code{set} expression whose first operand is an | |
10309 | @code{attr} expression giving the name of the attribute being set. The | |
10310 | second operand of the @code{set} is an attribute expression | |
10311 | (@pxref{Expressions}) giving the value of the attribute. | |
10312 | ||
10313 | When the attribute value depends on the @samp{alternative} attribute | |
10314 | (i.e., which is the applicable alternative in the constraint of the | |
10315 | insn), the @code{set_attr_alternative} expression can be used. It | |
10316 | allows the specification of a vector of attribute expressions, one for | |
10317 | each alternative. | |
10318 | ||
10319 | @findex set_attr | |
10320 | When the generality of arbitrary attribute expressions is not required, | |
10321 | the simpler @code{set_attr} expression can be used, which allows | |
10322 | specifying a string giving either a single attribute value or a list | |
10323 | of attribute values, one for each alternative. | |
10324 | ||
10325 | The form of each of the above specifications is shown below. In each case, | |
10326 | @var{name} is a string specifying the attribute to be set. | |
10327 | ||
10328 | @table @code | |
10329 | @item (set_attr @var{name} @var{value-string}) | |
10330 | @var{value-string} is either a string giving the desired attribute value, | |
10331 | or a string containing a comma-separated list giving the values for | |
10332 | succeeding alternatives. The number of elements must match the number | |
10333 | of alternatives in the constraint of the insn pattern. | |
10334 | ||
10335 | Note that it may be useful to specify @samp{*} for some alternative, in | |
10336 | which case the attribute will assume its default value for insns matching | |
10337 | that alternative. | |
10338 | ||
10339 | @findex set_attr_alternative | |
10340 | @item (set_attr_alternative @var{name} [@var{value1} @var{value2} @dots{}]) | |
10341 | Depending on the alternative of the insn, the value will be one of the | |
10342 | specified values. This is a shorthand for using a @code{cond} with | |
10343 | tests on the @samp{alternative} attribute. | |
10344 | ||
10345 | @findex attr | |
10346 | @item (set (attr @var{name}) @var{value}) | |
10347 | The first operand of this @code{set} must be the special RTL expression | |
10348 | @code{attr}, whose sole operand is a string giving the name of the | |
10349 | attribute being set. @var{value} is the value of the attribute. | |
10350 | @end table | |
10351 | ||
10352 | The following shows three different ways of representing the same | |
10353 | attribute value specification: | |
10354 | ||
10355 | @smallexample | |
10356 | (set_attr "type" "load,store,arith") | |
10357 | ||
10358 | (set_attr_alternative "type" | |
10359 | [(const_string "load") (const_string "store") | |
10360 | (const_string "arith")]) | |
10361 | ||
10362 | (set (attr "type") | |
10363 | (cond [(eq_attr "alternative" "1") (const_string "load") | |
10364 | (eq_attr "alternative" "2") (const_string "store")] | |
10365 | (const_string "arith"))) | |
10366 | @end smallexample | |
10367 | ||
10368 | @need 1000 | |
10369 | @findex define_asm_attributes | |
10370 | The @code{define_asm_attributes} expression provides a mechanism to | |
10371 | specify the attributes assigned to insns produced from an @code{asm} | |
10372 | statement. It has the form: | |
10373 | ||
10374 | @smallexample | |
10375 | (define_asm_attributes [@var{attr-sets}]) | |
10376 | @end smallexample | |
10377 | ||
10378 | @noindent | |
10379 | where @var{attr-sets} is specified the same as for both the | |
10380 | @code{define_insn} and the @code{define_peephole} expressions. | |
10381 | ||
10382 | These values will typically be the ``worst case'' attribute values. For | |
10383 | example, they might indicate that the condition code will be clobbered. | |
10384 | ||
10385 | A specification for a @code{length} attribute is handled specially. The | |
10386 | way to compute the length of an @code{asm} insn is to multiply the | |
10387 | length specified in the expression @code{define_asm_attributes} by the | |
10388 | number of machine instructions specified in the @code{asm} statement, | |
10389 | determined by counting the number of semicolons and newlines in the | |
10390 | string. Therefore, the value of the @code{length} attribute specified | |
10391 | in a @code{define_asm_attributes} should be the maximum possible length | |
10392 | of a single machine instruction. | |
10393 | ||
10394 | @end ifset | |
10395 | @ifset INTERNALS | |
10396 | @node Attr Example | |
10397 | @subsection Example of Attribute Specifications | |
10398 | @cindex attribute specifications example | |
10399 | @cindex attribute specifications | |
10400 | ||
10401 | The judicious use of defaulting is important in the efficient use of | |
10402 | insn attributes. Typically, insns are divided into @dfn{types} and an | |
10403 | attribute, customarily called @code{type}, is used to represent this | |
10404 | value. This attribute is normally used only to define the default value | |
10405 | for other attributes. An example will clarify this usage. | |
10406 | ||
10407 | Assume we have a RISC machine with a condition code and in which only | |
10408 | full-word operations are performed in registers. Let us assume that we | |
10409 | can divide all insns into loads, stores, (integer) arithmetic | |
10410 | operations, floating point operations, and branches. | |
10411 | ||
10412 | Here we will concern ourselves with determining the effect of an insn on | |
10413 | the condition code and will limit ourselves to the following possible | |
10414 | effects: The condition code can be set unpredictably (clobbered), not | |
10415 | be changed, be set to agree with the results of the operation, or only | |
10416 | changed if the item previously set into the condition code has been | |
10417 | modified. | |
10418 | ||
10419 | Here is part of a sample @file{md} file for such a machine: | |
10420 | ||
10421 | @smallexample | |
10422 | (define_attr "type" "load,store,arith,fp,branch" (const_string "arith")) | |
10423 | ||
10424 | (define_attr "cc" "clobber,unchanged,set,change0" | |
10425 | (cond [(eq_attr "type" "load") | |
10426 | (const_string "change0") | |
10427 | (eq_attr "type" "store,branch") | |
10428 | (const_string "unchanged") | |
10429 | (eq_attr "type" "arith") | |
10430 | (if_then_else (match_operand:SI 0 "" "") | |
10431 | (const_string "set") | |
10432 | (const_string "clobber"))] | |
10433 | (const_string "clobber"))) | |
10434 | ||
10435 | (define_insn "" | |
10436 | [(set (match_operand:SI 0 "general_operand" "=r,r,m") | |
10437 | (match_operand:SI 1 "general_operand" "r,m,r"))] | |
10438 | "" | |
10439 | "@@ | |
10440 | move %0,%1 | |
10441 | load %0,%1 | |
10442 | store %0,%1" | |
10443 | [(set_attr "type" "arith,load,store")]) | |
10444 | @end smallexample | |
10445 | ||
10446 | Note that we assume in the above example that arithmetic operations | |
10447 | performed on quantities smaller than a machine word clobber the condition | |
10448 | code since they will set the condition code to a value corresponding to the | |
10449 | full-word result. | |
10450 | ||
10451 | @end ifset | |
10452 | @ifset INTERNALS | |
10453 | @node Insn Lengths | |
10454 | @subsection Computing the Length of an Insn | |
10455 | @cindex insn lengths, computing | |
10456 | @cindex computing the length of an insn | |
10457 | ||
10458 | For many machines, multiple types of branch instructions are provided, each | |
10459 | for different length branch displacements. In most cases, the assembler | |
10460 | will choose the correct instruction to use. However, when the assembler | |
10461 | cannot do so, GCC can when a special attribute, the @code{length} | |
10462 | attribute, is defined. This attribute must be defined to have numeric | |
10463 | values by specifying a null string in its @code{define_attr}. | |
10464 | ||
10465 | In the case of the @code{length} attribute, two additional forms of | |
10466 | arithmetic terms are allowed in test expressions: | |
10467 | ||
10468 | @table @code | |
10469 | @cindex @code{match_dup} and attributes | |
10470 | @item (match_dup @var{n}) | |
10471 | This refers to the address of operand @var{n} of the current insn, which | |
10472 | must be a @code{label_ref}. | |
10473 | ||
10474 | @cindex @code{pc} and attributes | |
10475 | @item (pc) | |
10476 | For non-branch instructions and backward branch instructions, this refers | |
10477 | to the address of the current insn. But for forward branch instructions, | |
10478 | this refers to the address of the next insn, because the length of the | |
10479 | current insn is to be computed. | |
10480 | @end table | |
10481 | ||
10482 | @cindex @code{addr_vec}, length of | |
10483 | @cindex @code{addr_diff_vec}, length of | |
10484 | For normal insns, the length will be determined by value of the | |
10485 | @code{length} attribute. In the case of @code{addr_vec} and | |
10486 | @code{addr_diff_vec} insn patterns, the length is computed as | |
10487 | the number of vectors multiplied by the size of each vector. | |
10488 | ||
10489 | Lengths are measured in addressable storage units (bytes). | |
10490 | ||
10491 | Note that it is possible to call functions via the @code{symbol_ref} | |
10492 | mechanism to compute the length of an insn. However, if you use this | |
10493 | mechanism you must provide dummy clauses to express the maximum length | |
10494 | without using the function call. You can see an example of this in the | |
10495 | @code{pa} machine description for the @code{call_symref} pattern. | |
10496 | ||
10497 | The following macros can be used to refine the length computation: | |
10498 | ||
10499 | @table @code | |
10500 | @findex ADJUST_INSN_LENGTH | |
10501 | @item ADJUST_INSN_LENGTH (@var{insn}, @var{length}) | |
10502 | If defined, modifies the length assigned to instruction @var{insn} as a | |
10503 | function of the context in which it is used. @var{length} is an lvalue | |
10504 | that contains the initially computed length of the insn and should be | |
10505 | updated with the correct length of the insn. | |
10506 | ||
10507 | This macro will normally not be required. A case in which it is | |
10508 | required is the ROMP@. On this machine, the size of an @code{addr_vec} | |
10509 | insn must be increased by two to compensate for the fact that alignment | |
10510 | may be required. | |
10511 | @end table | |
10512 | ||
10513 | @findex get_attr_length | |
10514 | The routine that returns @code{get_attr_length} (the value of the | |
10515 | @code{length} attribute) can be used by the output routine to | |
10516 | determine the form of the branch instruction to be written, as the | |
10517 | example below illustrates. | |
10518 | ||
10519 | As an example of the specification of variable-length branches, consider | |
10520 | the IBM 360. If we adopt the convention that a register will be set to | |
10521 | the starting address of a function, we can jump to labels within 4k of | |
10522 | the start using a four-byte instruction. Otherwise, we need a six-byte | |
10523 | sequence to load the address from memory and then branch to it. | |
10524 | ||
10525 | On such a machine, a pattern for a branch instruction might be specified | |
10526 | as follows: | |
10527 | ||
10528 | @smallexample | |
10529 | (define_insn "jump" | |
10530 | [(set (pc) | |
10531 | (label_ref (match_operand 0 "" "")))] | |
10532 | "" | |
10533 | @{ | |
10534 | return (get_attr_length (insn) == 4 | |
10535 | ? "b %l0" : "l r15,=a(%l0); br r15"); | |
10536 | @} | |
10537 | [(set (attr "length") | |
10538 | (if_then_else (lt (match_dup 0) (const_int 4096)) | |
10539 | (const_int 4) | |
10540 | (const_int 6)))]) | |
10541 | @end smallexample | |
10542 | ||
10543 | @end ifset | |
10544 | @ifset INTERNALS | |
10545 | @node Constant Attributes | |
10546 | @subsection Constant Attributes | |
10547 | @cindex constant attributes | |
10548 | ||
10549 | A special form of @code{define_attr}, where the expression for the | |
10550 | default value is a @code{const} expression, indicates an attribute that | |
10551 | is constant for a given run of the compiler. Constant attributes may be | |
10552 | used to specify which variety of processor is used. For example, | |
10553 | ||
10554 | @smallexample | |
10555 | (define_attr "cpu" "m88100,m88110,m88000" | |
10556 | (const | |
10557 | (cond [(symbol_ref "TARGET_88100") (const_string "m88100") | |
10558 | (symbol_ref "TARGET_88110") (const_string "m88110")] | |
10559 | (const_string "m88000")))) | |
10560 | ||
10561 | (define_attr "memory" "fast,slow" | |
10562 | (const | |
10563 | (if_then_else (symbol_ref "TARGET_FAST_MEM") | |
10564 | (const_string "fast") | |
10565 | (const_string "slow")))) | |
10566 | @end smallexample | |
10567 | ||
10568 | The routine generated for constant attributes has no parameters as it | |
10569 | does not depend on any particular insn. RTL expressions used to define | |
10570 | the value of a constant attribute may use the @code{symbol_ref} form, | |
10571 | but may not use either the @code{match_operand} form or @code{eq_attr} | |
10572 | forms involving insn attributes. | |
10573 | ||
10574 | @end ifset | |
10575 | @ifset INTERNALS | |
10576 | @node Mnemonic Attribute | |
10577 | @subsection Mnemonic Attribute | |
10578 | @cindex mnemonic attribute | |
10579 | ||
10580 | The @code{mnemonic} attribute is a string type attribute holding the | |
10581 | instruction mnemonic for an insn alternative. The attribute values | |
10582 | will automatically be generated by the machine description parser if | |
10583 | there is an attribute definition in the md file: | |
10584 | ||
10585 | @smallexample | |
10586 | (define_attr "mnemonic" "unknown" (const_string "unknown")) | |
10587 | @end smallexample | |
10588 | ||
10589 | The default value can be freely chosen as long as it does not collide | |
10590 | with any of the instruction mnemonics. This value will be used | |
10591 | whenever the machine description parser is not able to determine the | |
10592 | mnemonic string. This might be the case for output templates | |
10593 | containing more than a single instruction as in | |
10594 | @code{"mvcle\t%0,%1,0\;jo\t.-4"}. | |
10595 | ||
10596 | The @code{mnemonic} attribute set is not generated automatically if the | |
10597 | instruction string is generated via C code. | |
10598 | ||
10599 | An existing @code{mnemonic} attribute set in an insn definition will not | |
10600 | be overriden by the md file parser. That way it is possible to | |
10601 | manually set the instruction mnemonics for the cases where the md file | |
10602 | parser fails to determine it automatically. | |
10603 | ||
10604 | The @code{mnemonic} attribute is useful for dealing with instruction | |
10605 | specific properties in the pipeline description without defining | |
10606 | additional insn attributes. | |
10607 | ||
10608 | @smallexample | |
10609 | (define_attr "ooo_expanded" "" | |
10610 | (cond [(eq_attr "mnemonic" "dlr,dsgr,d,dsgf,stam,dsgfr,dlgr") | |
10611 | (const_int 1)] | |
10612 | (const_int 0))) | |
10613 | @end smallexample | |
10614 | ||
10615 | @end ifset | |
10616 | @ifset INTERNALS | |
10617 | @node Delay Slots | |
10618 | @subsection Delay Slot Scheduling | |
10619 | @cindex delay slots, defining | |
10620 | ||
10621 | The insn attribute mechanism can be used to specify the requirements for | |
10622 | delay slots, if any, on a target machine. An instruction is said to | |
10623 | require a @dfn{delay slot} if some instructions that are physically | |
10624 | after the instruction are executed as if they were located before it. | |
10625 | Classic examples are branch and call instructions, which often execute | |
10626 | the following instruction before the branch or call is performed. | |
10627 | ||
10628 | On some machines, conditional branch instructions can optionally | |
10629 | @dfn{annul} instructions in the delay slot. This means that the | |
10630 | instruction will not be executed for certain branch outcomes. Both | |
10631 | instructions that annul if the branch is true and instructions that | |
10632 | annul if the branch is false are supported. | |
10633 | ||
10634 | Delay slot scheduling differs from instruction scheduling in that | |
10635 | determining whether an instruction needs a delay slot is dependent only | |
10636 | on the type of instruction being generated, not on data flow between the | |
10637 | instructions. See the next section for a discussion of data-dependent | |
10638 | instruction scheduling. | |
10639 | ||
10640 | @findex define_delay | |
10641 | The requirement of an insn needing one or more delay slots is indicated | |
10642 | via the @code{define_delay} expression. It has the following form: | |
10643 | ||
10644 | @smallexample | |
10645 | (define_delay @var{test} | |
10646 | [@var{delay-1} @var{annul-true-1} @var{annul-false-1} | |
10647 | @var{delay-2} @var{annul-true-2} @var{annul-false-2} | |
10648 | @dots{}]) | |
10649 | @end smallexample | |
10650 | ||
10651 | @var{test} is an attribute test that indicates whether this | |
10652 | @code{define_delay} applies to a particular insn. If so, the number of | |
10653 | required delay slots is determined by the length of the vector specified | |
10654 | as the second argument. An insn placed in delay slot @var{n} must | |
10655 | satisfy attribute test @var{delay-n}. @var{annul-true-n} is an | |
10656 | attribute test that specifies which insns may be annulled if the branch | |
10657 | is true. Similarly, @var{annul-false-n} specifies which insns in the | |
10658 | delay slot may be annulled if the branch is false. If annulling is not | |
10659 | supported for that delay slot, @code{(nil)} should be coded. | |
10660 | ||
10661 | For example, in the common case where branch and call insns require | |
10662 | a single delay slot, which may contain any insn other than a branch or | |
10663 | call, the following would be placed in the @file{md} file: | |
10664 | ||
10665 | @smallexample | |
10666 | (define_delay (eq_attr "type" "branch,call") | |
10667 | [(eq_attr "type" "!branch,call") (nil) (nil)]) | |
10668 | @end smallexample | |
10669 | ||
10670 | Multiple @code{define_delay} expressions may be specified. In this | |
10671 | case, each such expression specifies different delay slot requirements | |
10672 | and there must be no insn for which tests in two @code{define_delay} | |
10673 | expressions are both true. | |
10674 | ||
10675 | For example, if we have a machine that requires one delay slot for branches | |
10676 | but two for calls, no delay slot can contain a branch or call insn, | |
10677 | and any valid insn in the delay slot for the branch can be annulled if the | |
10678 | branch is true, we might represent this as follows: | |
10679 | ||
10680 | @smallexample | |
10681 | (define_delay (eq_attr "type" "branch") | |
10682 | [(eq_attr "type" "!branch,call") | |
10683 | (eq_attr "type" "!branch,call") | |
10684 | (nil)]) | |
10685 | ||
10686 | (define_delay (eq_attr "type" "call") | |
10687 | [(eq_attr "type" "!branch,call") (nil) (nil) | |
10688 | (eq_attr "type" "!branch,call") (nil) (nil)]) | |
10689 | @end smallexample | |
10690 | @c the above is *still* too long. --mew 4feb93 | |
10691 | ||
10692 | @end ifset | |
10693 | @ifset INTERNALS | |
10694 | @node Processor pipeline description | |
10695 | @subsection Specifying processor pipeline description | |
10696 | @cindex processor pipeline description | |
10697 | @cindex processor functional units | |
10698 | @cindex instruction latency time | |
10699 | @cindex interlock delays | |
10700 | @cindex data dependence delays | |
10701 | @cindex reservation delays | |
10702 | @cindex pipeline hazard recognizer | |
10703 | @cindex automaton based pipeline description | |
10704 | @cindex regular expressions | |
10705 | @cindex deterministic finite state automaton | |
10706 | @cindex automaton based scheduler | |
10707 | @cindex RISC | |
10708 | @cindex VLIW | |
10709 | ||
10710 | To achieve better performance, most modern processors | |
10711 | (super-pipelined, superscalar @acronym{RISC}, and @acronym{VLIW} | |
10712 | processors) have many @dfn{functional units} on which several | |
10713 | instructions can be executed simultaneously. An instruction starts | |
10714 | execution if its issue conditions are satisfied. If not, the | |
10715 | instruction is stalled until its conditions are satisfied. Such | |
10716 | @dfn{interlock (pipeline) delay} causes interruption of the fetching | |
10717 | of successor instructions (or demands nop instructions, e.g.@: for some | |
10718 | MIPS processors). | |
10719 | ||
10720 | There are two major kinds of interlock delays in modern processors. | |
10721 | The first one is a data dependence delay determining @dfn{instruction | |
10722 | latency time}. The instruction execution is not started until all | |
10723 | source data have been evaluated by prior instructions (there are more | |
10724 | complex cases when the instruction execution starts even when the data | |
10725 | are not available but will be ready in given time after the | |
10726 | instruction execution start). Taking the data dependence delays into | |
10727 | account is simple. The data dependence (true, output, and | |
10728 | anti-dependence) delay between two instructions is given by a | |
10729 | constant. In most cases this approach is adequate. The second kind | |
10730 | of interlock delays is a reservation delay. The reservation delay | |
10731 | means that two instructions under execution will be in need of shared | |
10732 | processors resources, i.e.@: buses, internal registers, and/or | |
10733 | functional units, which are reserved for some time. Taking this kind | |
10734 | of delay into account is complex especially for modern @acronym{RISC} | |
10735 | processors. | |
10736 | ||
10737 | The task of exploiting more processor parallelism is solved by an | |
10738 | instruction scheduler. For a better solution to this problem, the | |
10739 | instruction scheduler has to have an adequate description of the | |
10740 | processor parallelism (or @dfn{pipeline description}). GCC | |
10741 | machine descriptions describe processor parallelism and functional | |
10742 | unit reservations for groups of instructions with the aid of | |
10743 | @dfn{regular expressions}. | |
10744 | ||
10745 | The GCC instruction scheduler uses a @dfn{pipeline hazard recognizer} to | |
10746 | figure out the possibility of the instruction issue by the processor | |
10747 | on a given simulated processor cycle. The pipeline hazard recognizer is | |
10748 | automatically generated from the processor pipeline description. The | |
10749 | pipeline hazard recognizer generated from the machine description | |
10750 | is based on a deterministic finite state automaton (@acronym{DFA}): | |
10751 | the instruction issue is possible if there is a transition from one | |
10752 | automaton state to another one. This algorithm is very fast, and | |
10753 | furthermore, its speed is not dependent on processor | |
10754 | complexity@footnote{However, the size of the automaton depends on | |
10755 | processor complexity. To limit this effect, machine descriptions | |
10756 | can split orthogonal parts of the machine description among several | |
10757 | automata: but then, since each of these must be stepped independently, | |
10758 | this does cause a small decrease in the algorithm's performance.}. | |
10759 | ||
10760 | @cindex automaton based pipeline description | |
10761 | The rest of this section describes the directives that constitute | |
10762 | an automaton-based processor pipeline description. The order of | |
10763 | these constructions within the machine description file is not | |
10764 | important. | |
10765 | ||
10766 | @findex define_automaton | |
10767 | @cindex pipeline hazard recognizer | |
10768 | The following optional construction describes names of automata | |
10769 | generated and used for the pipeline hazards recognition. Sometimes | |
10770 | the generated finite state automaton used by the pipeline hazard | |
10771 | recognizer is large. If we use more than one automaton and bind functional | |
10772 | units to the automata, the total size of the automata is usually | |
10773 | less than the size of the single automaton. If there is no one such | |
10774 | construction, only one finite state automaton is generated. | |
10775 | ||
10776 | @smallexample | |
10777 | (define_automaton @var{automata-names}) | |
10778 | @end smallexample | |
10779 | ||
10780 | @var{automata-names} is a string giving names of the automata. The | |
10781 | names are separated by commas. All the automata should have unique names. | |
10782 | The automaton name is used in the constructions @code{define_cpu_unit} and | |
10783 | @code{define_query_cpu_unit}. | |
10784 | ||
10785 | @findex define_cpu_unit | |
10786 | @cindex processor functional units | |
10787 | Each processor functional unit used in the description of instruction | |
10788 | reservations should be described by the following construction. | |
10789 | ||
10790 | @smallexample | |
10791 | (define_cpu_unit @var{unit-names} [@var{automaton-name}]) | |
10792 | @end smallexample | |
10793 | ||
10794 | @var{unit-names} is a string giving the names of the functional units | |
10795 | separated by commas. Don't use name @samp{nothing}, it is reserved | |
10796 | for other goals. | |
10797 | ||
10798 | @var{automaton-name} is a string giving the name of the automaton with | |
10799 | which the unit is bound. The automaton should be described in | |
10800 | construction @code{define_automaton}. You should give | |
10801 | @dfn{automaton-name}, if there is a defined automaton. | |
10802 | ||
10803 | The assignment of units to automata are constrained by the uses of the | |
10804 | units in insn reservations. The most important constraint is: if a | |
10805 | unit reservation is present on a particular cycle of an alternative | |
10806 | for an insn reservation, then some unit from the same automaton must | |
10807 | be present on the same cycle for the other alternatives of the insn | |
10808 | reservation. The rest of the constraints are mentioned in the | |
10809 | description of the subsequent constructions. | |
10810 | ||
10811 | @findex define_query_cpu_unit | |
10812 | @cindex querying function unit reservations | |
10813 | The following construction describes CPU functional units analogously | |
10814 | to @code{define_cpu_unit}. The reservation of such units can be | |
10815 | queried for an automaton state. The instruction scheduler never | |
10816 | queries reservation of functional units for given automaton state. So | |
10817 | as a rule, you don't need this construction. This construction could | |
10818 | be used for future code generation goals (e.g.@: to generate | |
10819 | @acronym{VLIW} insn templates). | |
10820 | ||
10821 | @smallexample | |
10822 | (define_query_cpu_unit @var{unit-names} [@var{automaton-name}]) | |
10823 | @end smallexample | |
10824 | ||
10825 | @var{unit-names} is a string giving names of the functional units | |
10826 | separated by commas. | |
10827 | ||
10828 | @var{automaton-name} is a string giving the name of the automaton with | |
10829 | which the unit is bound. | |
10830 | ||
10831 | @findex define_insn_reservation | |
10832 | @cindex instruction latency time | |
10833 | @cindex regular expressions | |
10834 | @cindex data bypass | |
10835 | The following construction is the major one to describe pipeline | |
10836 | characteristics of an instruction. | |
10837 | ||
10838 | @smallexample | |
10839 | (define_insn_reservation @var{insn-name} @var{default_latency} | |
10840 | @var{condition} @var{regexp}) | |
10841 | @end smallexample | |
10842 | ||
10843 | @var{default_latency} is a number giving latency time of the | |
10844 | instruction. There is an important difference between the old | |
10845 | description and the automaton based pipeline description. The latency | |
10846 | time is used for all dependencies when we use the old description. In | |
10847 | the automaton based pipeline description, the given latency time is only | |
10848 | used for true dependencies. The cost of anti-dependencies is always | |
10849 | zero and the cost of output dependencies is the difference between | |
10850 | latency times of the producing and consuming insns (if the difference | |
10851 | is negative, the cost is considered to be zero). You can always | |
10852 | change the default costs for any description by using the target hook | |
10853 | @code{TARGET_SCHED_ADJUST_COST} (@pxref{Scheduling}). | |
10854 | ||
10855 | @var{insn-name} is a string giving the internal name of the insn. The | |
10856 | internal names are used in constructions @code{define_bypass} and in | |
10857 | the automaton description file generated for debugging. The internal | |
10858 | name has nothing in common with the names in @code{define_insn}. It is a | |
10859 | good practice to use insn classes described in the processor manual. | |
10860 | ||
10861 | @var{condition} defines what RTL insns are described by this | |
10862 | construction. You should remember that you will be in trouble if | |
10863 | @var{condition} for two or more different | |
10864 | @code{define_insn_reservation} constructions is TRUE for an insn. In | |
10865 | this case what reservation will be used for the insn is not defined. | |
10866 | Such cases are not checked during generation of the pipeline hazards | |
10867 | recognizer because in general recognizing that two conditions may have | |
10868 | the same value is quite difficult (especially if the conditions | |
10869 | contain @code{symbol_ref}). It is also not checked during the | |
10870 | pipeline hazard recognizer work because it would slow down the | |
10871 | recognizer considerably. | |
10872 | ||
10873 | @var{regexp} is a string describing the reservation of the cpu's functional | |
10874 | units by the instruction. The reservations are described by a regular | |
10875 | expression according to the following syntax: | |
10876 | ||
10877 | @smallexample | |
10878 | regexp = regexp "," oneof | |
10879 | | oneof | |
10880 | ||
10881 | oneof = oneof "|" allof | |
10882 | | allof | |
10883 | ||
10884 | allof = allof "+" repeat | |
10885 | | repeat | |
10886 | ||
10887 | repeat = element "*" number | |
10888 | | element | |
10889 | ||
10890 | element = cpu_function_unit_name | |
10891 | | reservation_name | |
10892 | | result_name | |
10893 | | "nothing" | |
10894 | | "(" regexp ")" | |
10895 | @end smallexample | |
10896 | ||
10897 | @itemize @bullet | |
10898 | @item | |
10899 | @samp{,} is used for describing the start of the next cycle in | |
10900 | the reservation. | |
10901 | ||
10902 | @item | |
10903 | @samp{|} is used for describing a reservation described by the first | |
10904 | regular expression @strong{or} a reservation described by the second | |
10905 | regular expression @strong{or} etc. | |
10906 | ||
10907 | @item | |
10908 | @samp{+} is used for describing a reservation described by the first | |
10909 | regular expression @strong{and} a reservation described by the | |
10910 | second regular expression @strong{and} etc. | |
10911 | ||
10912 | @item | |
10913 | @samp{*} is used for convenience and simply means a sequence in which | |
10914 | the regular expression are repeated @var{number} times with cycle | |
10915 | advancing (see @samp{,}). | |
10916 | ||
10917 | @item | |
10918 | @samp{cpu_function_unit_name} denotes reservation of the named | |
10919 | functional unit. | |
10920 | ||
10921 | @item | |
10922 | @samp{reservation_name} --- see description of construction | |
10923 | @samp{define_reservation}. | |
10924 | ||
10925 | @item | |
10926 | @samp{nothing} denotes no unit reservations. | |
10927 | @end itemize | |
10928 | ||
10929 | @findex define_reservation | |
10930 | Sometimes unit reservations for different insns contain common parts. | |
10931 | In such case, you can simplify the pipeline description by describing | |
10932 | the common part by the following construction | |
10933 | ||
10934 | @smallexample | |
10935 | (define_reservation @var{reservation-name} @var{regexp}) | |
10936 | @end smallexample | |
10937 | ||
10938 | @var{reservation-name} is a string giving name of @var{regexp}. | |
10939 | Functional unit names and reservation names are in the same name | |
10940 | space. So the reservation names should be different from the | |
10941 | functional unit names and cannot be the reserved name @samp{nothing}. | |
10942 | ||
10943 | @findex define_bypass | |
10944 | @cindex instruction latency time | |
10945 | @cindex data bypass | |
10946 | The following construction is used to describe exceptions in the | |
10947 | latency time for given instruction pair. This is so called bypasses. | |
10948 | ||
10949 | @smallexample | |
10950 | (define_bypass @var{number} @var{out_insn_names} @var{in_insn_names} | |
10951 | [@var{guard}]) | |
10952 | @end smallexample | |
10953 | ||
10954 | @var{number} defines when the result generated by the instructions | |
10955 | given in string @var{out_insn_names} will be ready for the | |
10956 | instructions given in string @var{in_insn_names}. Each of these | |
10957 | strings is a comma-separated list of filename-style globs and | |
10958 | they refer to the names of @code{define_insn_reservation}s. | |
10959 | For example: | |
10960 | @smallexample | |
10961 | (define_bypass 1 "cpu1_load_*, cpu1_store_*" "cpu1_load_*") | |
10962 | @end smallexample | |
10963 | defines a bypass between instructions that start with | |
10964 | @samp{cpu1_load_} or @samp{cpu1_store_} and those that start with | |
10965 | @samp{cpu1_load_}. | |
10966 | ||
10967 | @var{guard} is an optional string giving the name of a C function which | |
10968 | defines an additional guard for the bypass. The function will get the | |
10969 | two insns as parameters. If the function returns zero the bypass will | |
10970 | be ignored for this case. The additional guard is necessary to | |
10971 | recognize complicated bypasses, e.g.@: when the consumer is only an address | |
10972 | of insn @samp{store} (not a stored value). | |
10973 | ||
10974 | If there are more one bypass with the same output and input insns, the | |
10975 | chosen bypass is the first bypass with a guard in description whose | |
10976 | guard function returns nonzero. If there is no such bypass, then | |
10977 | bypass without the guard function is chosen. | |
10978 | ||
10979 | @findex exclusion_set | |
10980 | @findex presence_set | |
10981 | @findex final_presence_set | |
10982 | @findex absence_set | |
10983 | @findex final_absence_set | |
10984 | @cindex VLIW | |
10985 | @cindex RISC | |
10986 | The following five constructions are usually used to describe | |
10987 | @acronym{VLIW} processors, or more precisely, to describe a placement | |
10988 | of small instructions into @acronym{VLIW} instruction slots. They | |
10989 | can be used for @acronym{RISC} processors, too. | |
10990 | ||
10991 | @smallexample | |
10992 | (exclusion_set @var{unit-names} @var{unit-names}) | |
10993 | (presence_set @var{unit-names} @var{patterns}) | |
10994 | (final_presence_set @var{unit-names} @var{patterns}) | |
10995 | (absence_set @var{unit-names} @var{patterns}) | |
10996 | (final_absence_set @var{unit-names} @var{patterns}) | |
10997 | @end smallexample | |
10998 | ||
10999 | @var{unit-names} is a string giving names of functional units | |
11000 | separated by commas. | |
11001 | ||
11002 | @var{patterns} is a string giving patterns of functional units | |
11003 | separated by comma. Currently pattern is one unit or units | |
11004 | separated by white-spaces. | |
11005 | ||
11006 | The first construction (@samp{exclusion_set}) means that each | |
11007 | functional unit in the first string cannot be reserved simultaneously | |
11008 | with a unit whose name is in the second string and vice versa. For | |
11009 | example, the construction is useful for describing processors | |
11010 | (e.g.@: some SPARC processors) with a fully pipelined floating point | |
11011 | functional unit which can execute simultaneously only single floating | |
11012 | point insns or only double floating point insns. | |
11013 | ||
11014 | The second construction (@samp{presence_set}) means that each | |
11015 | functional unit in the first string cannot be reserved unless at | |
11016 | least one of pattern of units whose names are in the second string is | |
11017 | reserved. This is an asymmetric relation. For example, it is useful | |
11018 | for description that @acronym{VLIW} @samp{slot1} is reserved after | |
11019 | @samp{slot0} reservation. We could describe it by the following | |
11020 | construction | |
11021 | ||
11022 | @smallexample | |
11023 | (presence_set "slot1" "slot0") | |
11024 | @end smallexample | |
11025 | ||
11026 | Or @samp{slot1} is reserved only after @samp{slot0} and unit @samp{b0} | |
11027 | reservation. In this case we could write | |
11028 | ||
11029 | @smallexample | |
11030 | (presence_set "slot1" "slot0 b0") | |
11031 | @end smallexample | |
11032 | ||
11033 | The third construction (@samp{final_presence_set}) is analogous to | |
11034 | @samp{presence_set}. The difference between them is when checking is | |
11035 | done. When an instruction is issued in given automaton state | |
11036 | reflecting all current and planned unit reservations, the automaton | |
11037 | state is changed. The first state is a source state, the second one | |
11038 | is a result state. Checking for @samp{presence_set} is done on the | |
11039 | source state reservation, checking for @samp{final_presence_set} is | |
11040 | done on the result reservation. This construction is useful to | |
11041 | describe a reservation which is actually two subsequent reservations. | |
11042 | For example, if we use | |
11043 | ||
11044 | @smallexample | |
11045 | (presence_set "slot1" "slot0") | |
11046 | @end smallexample | |
11047 | ||
11048 | the following insn will be never issued (because @samp{slot1} requires | |
11049 | @samp{slot0} which is absent in the source state). | |
11050 | ||
11051 | @smallexample | |
11052 | (define_reservation "insn_and_nop" "slot0 + slot1") | |
11053 | @end smallexample | |
11054 | ||
11055 | but it can be issued if we use analogous @samp{final_presence_set}. | |
11056 | ||
11057 | The forth construction (@samp{absence_set}) means that each functional | |
11058 | unit in the first string can be reserved only if each pattern of units | |
11059 | whose names are in the second string is not reserved. This is an | |
11060 | asymmetric relation (actually @samp{exclusion_set} is analogous to | |
11061 | this one but it is symmetric). For example it might be useful in a | |
11062 | @acronym{VLIW} description to say that @samp{slot0} cannot be reserved | |
11063 | after either @samp{slot1} or @samp{slot2} have been reserved. This | |
11064 | can be described as: | |
11065 | ||
11066 | @smallexample | |
11067 | (absence_set "slot0" "slot1, slot2") | |
11068 | @end smallexample | |
11069 | ||
11070 | Or @samp{slot2} cannot be reserved if @samp{slot0} and unit @samp{b0} | |
11071 | are reserved or @samp{slot1} and unit @samp{b1} are reserved. In | |
11072 | this case we could write | |
11073 | ||
11074 | @smallexample | |
11075 | (absence_set "slot2" "slot0 b0, slot1 b1") | |
11076 | @end smallexample | |
11077 | ||
11078 | All functional units mentioned in a set should belong to the same | |
11079 | automaton. | |
11080 | ||
11081 | The last construction (@samp{final_absence_set}) is analogous to | |
11082 | @samp{absence_set} but checking is done on the result (state) | |
11083 | reservation. See comments for @samp{final_presence_set}. | |
11084 | ||
11085 | @findex automata_option | |
11086 | @cindex deterministic finite state automaton | |
11087 | @cindex nondeterministic finite state automaton | |
11088 | @cindex finite state automaton minimization | |
11089 | You can control the generator of the pipeline hazard recognizer with | |
11090 | the following construction. | |
11091 | ||
11092 | @smallexample | |
11093 | (automata_option @var{options}) | |
11094 | @end smallexample | |
11095 | ||
11096 | @var{options} is a string giving options which affect the generated | |
11097 | code. Currently there are the following options: | |
11098 | ||
11099 | @itemize @bullet | |
11100 | @item | |
11101 | @dfn{no-minimization} makes no minimization of the automaton. This is | |
11102 | only worth to do when we are debugging the description and need to | |
11103 | look more accurately at reservations of states. | |
11104 | ||
11105 | @item | |
11106 | @dfn{time} means printing time statistics about the generation of | |
11107 | automata. | |
11108 | ||
11109 | @item | |
11110 | @dfn{stats} means printing statistics about the generated automata | |
11111 | such as the number of DFA states, NDFA states and arcs. | |
11112 | ||
11113 | @item | |
11114 | @dfn{v} means a generation of the file describing the result automata. | |
11115 | The file has suffix @samp{.dfa} and can be used for the description | |
11116 | verification and debugging. | |
11117 | ||
11118 | @item | |
11119 | @dfn{w} means a generation of warning instead of error for | |
11120 | non-critical errors. | |
11121 | ||
11122 | @item | |
11123 | @dfn{no-comb-vect} prevents the automaton generator from generating | |
11124 | two data structures and comparing them for space efficiency. Using | |
11125 | a comb vector to represent transitions may be better, but it can be | |
11126 | very expensive to construct. This option is useful if the build | |
11127 | process spends an unacceptably long time in genautomata. | |
11128 | ||
11129 | @item | |
11130 | @dfn{ndfa} makes nondeterministic finite state automata. This affects | |
11131 | the treatment of operator @samp{|} in the regular expressions. The | |
11132 | usual treatment of the operator is to try the first alternative and, | |
11133 | if the reservation is not possible, the second alternative. The | |
11134 | nondeterministic treatment means trying all alternatives, some of them | |
11135 | may be rejected by reservations in the subsequent insns. | |
11136 | ||
11137 | @item | |
11138 | @dfn{collapse-ndfa} modifies the behavior of the generator when | |
11139 | producing an automaton. An additional state transition to collapse a | |
11140 | nondeterministic @acronym{NDFA} state to a deterministic @acronym{DFA} | |
11141 | state is generated. It can be triggered by passing @code{const0_rtx} to | |
11142 | state_transition. In such an automaton, cycle advance transitions are | |
11143 | available only for these collapsed states. This option is useful for | |
11144 | ports that want to use the @code{ndfa} option, but also want to use | |
11145 | @code{define_query_cpu_unit} to assign units to insns issued in a cycle. | |
11146 | ||
11147 | @item | |
11148 | @dfn{progress} means output of a progress bar showing how many states | |
11149 | were generated so far for automaton being processed. This is useful | |
11150 | during debugging a @acronym{DFA} description. If you see too many | |
11151 | generated states, you could interrupt the generator of the pipeline | |
11152 | hazard recognizer and try to figure out a reason for generation of the | |
11153 | huge automaton. | |
11154 | @end itemize | |
11155 | ||
11156 | As an example, consider a superscalar @acronym{RISC} machine which can | |
11157 | issue three insns (two integer insns and one floating point insn) on | |
11158 | the cycle but can finish only two insns. To describe this, we define | |
11159 | the following functional units. | |
11160 | ||
11161 | @smallexample | |
11162 | (define_cpu_unit "i0_pipeline, i1_pipeline, f_pipeline") | |
11163 | (define_cpu_unit "port0, port1") | |
11164 | @end smallexample | |
11165 | ||
11166 | All simple integer insns can be executed in any integer pipeline and | |
11167 | their result is ready in two cycles. The simple integer insns are | |
11168 | issued into the first pipeline unless it is reserved, otherwise they | |
11169 | are issued into the second pipeline. Integer division and | |
11170 | multiplication insns can be executed only in the second integer | |
11171 | pipeline and their results are ready correspondingly in 9 and 4 | |
11172 | cycles. The integer division is not pipelined, i.e.@: the subsequent | |
11173 | integer division insn cannot be issued until the current division | |
11174 | insn finished. Floating point insns are fully pipelined and their | |
11175 | results are ready in 3 cycles. Where the result of a floating point | |
11176 | insn is used by an integer insn, an additional delay of one cycle is | |
11177 | incurred. To describe all of this we could specify | |
11178 | ||
11179 | @smallexample | |
11180 | (define_cpu_unit "div") | |
11181 | ||
11182 | (define_insn_reservation "simple" 2 (eq_attr "type" "int") | |
11183 | "(i0_pipeline | i1_pipeline), (port0 | port1)") | |
11184 | ||
11185 | (define_insn_reservation "mult" 4 (eq_attr "type" "mult") | |
11186 | "i1_pipeline, nothing*2, (port0 | port1)") | |
11187 | ||
11188 | (define_insn_reservation "div" 9 (eq_attr "type" "div") | |
11189 | "i1_pipeline, div*7, div + (port0 | port1)") | |
11190 | ||
11191 | (define_insn_reservation "float" 3 (eq_attr "type" "float") | |
11192 | "f_pipeline, nothing, (port0 | port1)) | |
11193 | ||
11194 | (define_bypass 4 "float" "simple,mult,div") | |
11195 | @end smallexample | |
11196 | ||
11197 | To simplify the description we could describe the following reservation | |
11198 | ||
11199 | @smallexample | |
11200 | (define_reservation "finish" "port0|port1") | |
11201 | @end smallexample | |
11202 | ||
11203 | and use it in all @code{define_insn_reservation} as in the following | |
11204 | construction | |
11205 | ||
11206 | @smallexample | |
11207 | (define_insn_reservation "simple" 2 (eq_attr "type" "int") | |
11208 | "(i0_pipeline | i1_pipeline), finish") | |
11209 | @end smallexample | |
11210 | ||
11211 | ||
11212 | @end ifset | |
11213 | @ifset INTERNALS | |
11214 | @node Conditional Execution | |
11215 | @section Conditional Execution | |
11216 | @cindex conditional execution | |
11217 | @cindex predication | |
11218 | ||
11219 | A number of architectures provide for some form of conditional | |
11220 | execution, or predication. The hallmark of this feature is the | |
11221 | ability to nullify most of the instructions in the instruction set. | |
11222 | When the instruction set is large and not entirely symmetric, it | |
11223 | can be quite tedious to describe these forms directly in the | |
11224 | @file{.md} file. An alternative is the @code{define_cond_exec} template. | |
11225 | ||
11226 | @findex define_cond_exec | |
11227 | @smallexample | |
11228 | (define_cond_exec | |
11229 | [@var{predicate-pattern}] | |
11230 | "@var{condition}" | |
11231 | "@var{output-template}" | |
11232 | "@var{optional-insn-attribues}") | |
11233 | @end smallexample | |
11234 | ||
11235 | @var{predicate-pattern} is the condition that must be true for the | |
11236 | insn to be executed at runtime and should match a relational operator. | |
11237 | One can use @code{match_operator} to match several relational operators | |
11238 | at once. Any @code{match_operand} operands must have no more than one | |
11239 | alternative. | |
11240 | ||
11241 | @var{condition} is a C expression that must be true for the generated | |
11242 | pattern to match. | |
11243 | ||
11244 | @findex current_insn_predicate | |
11245 | @var{output-template} is a string similar to the @code{define_insn} | |
11246 | output template (@pxref{Output Template}), except that the @samp{*} | |
11247 | and @samp{@@} special cases do not apply. This is only useful if the | |
11248 | assembly text for the predicate is a simple prefix to the main insn. | |
11249 | In order to handle the general case, there is a global variable | |
11250 | @code{current_insn_predicate} that will contain the entire predicate | |
11251 | if the current insn is predicated, and will otherwise be @code{NULL}. | |
11252 | ||
11253 | @var{optional-insn-attributes} is an optional vector of attributes that gets | |
11254 | appended to the insn attributes of the produced cond_exec rtx. It can | |
11255 | be used to add some distinguishing attribute to cond_exec rtxs produced | |
11256 | that way. An example usage would be to use this attribute in conjunction | |
11257 | with attributes on the main pattern to disable particular alternatives under | |
11258 | certain conditions. | |
11259 | ||
11260 | When @code{define_cond_exec} is used, an implicit reference to | |
11261 | the @code{predicable} instruction attribute is made. | |
11262 | @xref{Insn Attributes}. This attribute must be a boolean (i.e.@: have | |
11263 | exactly two elements in its @var{list-of-values}), with the possible | |
11264 | values being @code{no} and @code{yes}. The default and all uses in | |
11265 | the insns must be a simple constant, not a complex expressions. It | |
11266 | may, however, depend on the alternative, by using a comma-separated | |
11267 | list of values. If that is the case, the port should also define an | |
11268 | @code{enabled} attribute (@pxref{Disable Insn Alternatives}), which | |
11269 | should also allow only @code{no} and @code{yes} as its values. | |
11270 | ||
11271 | For each @code{define_insn} for which the @code{predicable} | |
11272 | attribute is true, a new @code{define_insn} pattern will be | |
11273 | generated that matches a predicated version of the instruction. | |
11274 | For example, | |
11275 | ||
11276 | @smallexample | |
11277 | (define_insn "addsi" | |
11278 | [(set (match_operand:SI 0 "register_operand" "r") | |
11279 | (plus:SI (match_operand:SI 1 "register_operand" "r") | |
11280 | (match_operand:SI 2 "register_operand" "r")))] | |
11281 | "@var{test1}" | |
11282 | "add %2,%1,%0") | |
11283 | ||
11284 | (define_cond_exec | |
11285 | [(ne (match_operand:CC 0 "register_operand" "c") | |
11286 | (const_int 0))] | |
11287 | "@var{test2}" | |
11288 | "(%0)") | |
11289 | @end smallexample | |
11290 | ||
11291 | @noindent | |
11292 | generates a new pattern | |
11293 | ||
11294 | @smallexample | |
11295 | (define_insn "" | |
11296 | [(cond_exec | |
11297 | (ne (match_operand:CC 3 "register_operand" "c") (const_int 0)) | |
11298 | (set (match_operand:SI 0 "register_operand" "r") | |
11299 | (plus:SI (match_operand:SI 1 "register_operand" "r") | |
11300 | (match_operand:SI 2 "register_operand" "r"))))] | |
11301 | "(@var{test2}) && (@var{test1})" | |
11302 | "(%3) add %2,%1,%0") | |
11303 | @end smallexample | |
11304 | ||
11305 | @end ifset | |
11306 | @ifset INTERNALS | |
11307 | @node Define Subst | |
11308 | @section RTL Templates Transformations | |
11309 | @cindex define_subst | |
11310 | ||
11311 | For some hardware architectures there are common cases when the RTL | |
11312 | templates for the instructions can be derived from the other RTL | |
11313 | templates using simple transformations. E.g., @file{i386.md} contains | |
11314 | an RTL template for the ordinary @code{sub} instruction--- | |
11315 | @code{*subsi_1}, and for the @code{sub} instruction with subsequent | |
11316 | zero-extension---@code{*subsi_1_zext}. Such cases can be easily | |
11317 | implemented by a single meta-template capable of generating a modified | |
11318 | case based on the initial one: | |
11319 | ||
11320 | @findex define_subst | |
11321 | @smallexample | |
11322 | (define_subst "@var{name}" | |
11323 | [@var{input-template}] | |
11324 | "@var{condition}" | |
11325 | [@var{output-template}]) | |
11326 | @end smallexample | |
11327 | @var{input-template} is a pattern describing the source RTL template, | |
11328 | which will be transformed. | |
11329 | ||
11330 | @var{condition} is a C expression that is conjunct with the condition | |
11331 | from the input-template to generate a condition to be used in the | |
11332 | output-template. | |
11333 | ||
11334 | @var{output-template} is a pattern that will be used in the resulting | |
11335 | template. | |
11336 | ||
11337 | @code{define_subst} mechanism is tightly coupled with the notion of the | |
11338 | subst attribute (@pxref{Subst Iterators}). The use of | |
11339 | @code{define_subst} is triggered by a reference to a subst attribute in | |
11340 | the transforming RTL template. This reference initiates duplication of | |
11341 | the source RTL template and substitution of the attributes with their | |
11342 | values. The source RTL template is left unchanged, while the copy is | |
11343 | transformed by @code{define_subst}. This transformation can fail in the | |
11344 | case when the source RTL template is not matched against the | |
11345 | input-template of the @code{define_subst}. In such case the copy is | |
11346 | deleted. | |
11347 | ||
11348 | @code{define_subst} can be used only in @code{define_insn} and | |
11349 | @code{define_expand}, it cannot be used in other expressions (e.g.@: in | |
11350 | @code{define_insn_and_split}). | |
11351 | ||
11352 | @menu | |
11353 | * Define Subst Example:: Example of @code{define_subst} work. | |
11354 | * Define Subst Pattern Matching:: Process of template comparison. | |
11355 | * Define Subst Output Template:: Generation of output template. | |
11356 | @end menu | |
11357 | ||
11358 | @node Define Subst Example | |
11359 | @subsection @code{define_subst} Example | |
11360 | @cindex define_subst | |
11361 | ||
11362 | To illustrate how @code{define_subst} works, let us examine a simple | |
11363 | template transformation. | |
11364 | ||
11365 | Suppose there are two kinds of instructions: one that touches flags and | |
11366 | the other that does not. The instructions of the second type could be | |
11367 | generated with the following @code{define_subst}: | |
11368 | ||
11369 | @smallexample | |
11370 | (define_subst "add_clobber_subst" | |
11371 | [(set (match_operand:SI 0 "" "") | |
11372 | (match_operand:SI 1 "" ""))] | |
11373 | "" | |
11374 | [(set (match_dup 0) | |
11375 | (match_dup 1)) | |
11376 | (clobber (reg:CC FLAGS_REG))]) | |
11377 | @end smallexample | |
11378 | ||
11379 | This @code{define_subst} can be applied to any RTL pattern containing | |
11380 | @code{set} of mode SI and generates a copy with clobber when it is | |
11381 | applied. | |
11382 | ||
11383 | Assume there is an RTL template for a @code{max} instruction to be used | |
11384 | in @code{define_subst} mentioned above: | |
11385 | ||
11386 | @smallexample | |
11387 | (define_insn "maxsi" | |
11388 | [(set (match_operand:SI 0 "register_operand" "=r") | |
11389 | (max:SI | |
11390 | (match_operand:SI 1 "register_operand" "r") | |
11391 | (match_operand:SI 2 "register_operand" "r")))] | |
11392 | "" | |
11393 | "max\t@{%2, %1, %0|%0, %1, %2@}" | |
11394 | [@dots{}]) | |
11395 | @end smallexample | |
11396 | ||
11397 | To mark the RTL template for @code{define_subst} application, | |
11398 | subst-attributes are used. They should be declared in advance: | |
11399 | ||
11400 | @smallexample | |
11401 | (define_subst_attr "add_clobber_name" "add_clobber_subst" "_noclobber" "_clobber") | |
11402 | @end smallexample | |
11403 | ||
11404 | Here @samp{add_clobber_name} is the attribute name, | |
11405 | @samp{add_clobber_subst} is the name of the corresponding | |
11406 | @code{define_subst}, the third argument (@samp{_noclobber}) is the | |
11407 | attribute value that would be substituted into the unchanged version of | |
11408 | the source RTL template, and the last argument (@samp{_clobber}) is the | |
11409 | value that would be substituted into the second, transformed, | |
11410 | version of the RTL template. | |
11411 | ||
11412 | Once the subst-attribute has been defined, it should be used in RTL | |
11413 | templates which need to be processed by the @code{define_subst}. So, | |
11414 | the original RTL template should be changed: | |
11415 | ||
11416 | @smallexample | |
11417 | (define_insn "maxsi<add_clobber_name>" | |
11418 | [(set (match_operand:SI 0 "register_operand" "=r") | |
11419 | (max:SI | |
11420 | (match_operand:SI 1 "register_operand" "r") | |
11421 | (match_operand:SI 2 "register_operand" "r")))] | |
11422 | "" | |
11423 | "max\t@{%2, %1, %0|%0, %1, %2@}" | |
11424 | [@dots{}]) | |
11425 | @end smallexample | |
11426 | ||
11427 | The result of the @code{define_subst} usage would look like the following: | |
11428 | ||
11429 | @smallexample | |
11430 | (define_insn "maxsi_noclobber" | |
11431 | [(set (match_operand:SI 0 "register_operand" "=r") | |
11432 | (max:SI | |
11433 | (match_operand:SI 1 "register_operand" "r") | |
11434 | (match_operand:SI 2 "register_operand" "r")))] | |
11435 | "" | |
11436 | "max\t@{%2, %1, %0|%0, %1, %2@}" | |
11437 | [@dots{}]) | |
11438 | (define_insn "maxsi_clobber" | |
11439 | [(set (match_operand:SI 0 "register_operand" "=r") | |
11440 | (max:SI | |
11441 | (match_operand:SI 1 "register_operand" "r") | |
11442 | (match_operand:SI 2 "register_operand" "r"))) | |
11443 | (clobber (reg:CC FLAGS_REG))] | |
11444 | "" | |
11445 | "max\t@{%2, %1, %0|%0, %1, %2@}" | |
11446 | [@dots{}]) | |
11447 | @end smallexample | |
11448 | ||
11449 | @node Define Subst Pattern Matching | |
11450 | @subsection Pattern Matching in @code{define_subst} | |
11451 | @cindex define_subst | |
11452 | ||
11453 | All expressions, allowed in @code{define_insn} or @code{define_expand}, | |
11454 | are allowed in the input-template of @code{define_subst}, except | |
11455 | @code{match_par_dup}, @code{match_scratch}, @code{match_parallel}. The | |
11456 | meanings of expressions in the input-template were changed: | |
11457 | ||
11458 | @code{match_operand} matches any expression (possibly, a subtree in | |
11459 | RTL-template), if modes of the @code{match_operand} and this expression | |
11460 | are the same, or mode of the @code{match_operand} is @code{VOIDmode}, or | |
11461 | this expression is @code{match_dup}, @code{match_op_dup}. If the | |
11462 | expression is @code{match_operand} too, and predicate of | |
11463 | @code{match_operand} from the input pattern is not empty, then the | |
11464 | predicates are compared. That can be used for more accurate filtering | |
11465 | of accepted RTL-templates. | |
11466 | ||
11467 | @code{match_operator} matches common operators (like @code{plus}, | |
11468 | @code{minus}), @code{unspec}, @code{unspec_volatile} operators and | |
11469 | @code{match_operator}s from the original pattern if the modes match and | |
11470 | @code{match_operator} from the input pattern has the same number of | |
11471 | operands as the operator from the original pattern. | |
11472 | ||
11473 | @node Define Subst Output Template | |
11474 | @subsection Generation of output template in @code{define_subst} | |
11475 | @cindex define_subst | |
11476 | ||
11477 | If all necessary checks for @code{define_subst} application pass, a new | |
11478 | RTL-pattern, based on the output-template, is created to replace the old | |
11479 | template. Like in input-patterns, meanings of some RTL expressions are | |
11480 | changed when they are used in output-patterns of a @code{define_subst}. | |
11481 | Thus, @code{match_dup} is used for copying the whole expression from the | |
11482 | original pattern, which matched corresponding @code{match_operand} from | |
11483 | the input pattern. | |
11484 | ||
11485 | @code{match_dup N} is used in the output template to be replaced with | |
11486 | the expression from the original pattern, which matched | |
11487 | @code{match_operand N} from the input pattern. As a consequence, | |
11488 | @code{match_dup} cannot be used to point to @code{match_operand}s from | |
11489 | the output pattern, it should always refer to a @code{match_operand} | |
11490 | from the input pattern. If a @code{match_dup N} occurs more than once | |
11491 | in the output template, its first occurrence is replaced with the | |
11492 | expression from the original pattern, and the subsequent expressions | |
11493 | are replaced with @code{match_dup N}, i.e., a reference to the first | |
11494 | expression. | |
11495 | ||
11496 | In the output template one can refer to the expressions from the | |
11497 | original pattern and create new ones. For instance, some operands could | |
11498 | be added by means of standard @code{match_operand}. | |
11499 | ||
11500 | After replacing @code{match_dup} with some RTL-subtree from the original | |
11501 | pattern, it could happen that several @code{match_operand}s in the | |
11502 | output pattern have the same indexes. It is unknown, how many and what | |
11503 | indexes would be used in the expression which would replace | |
11504 | @code{match_dup}, so such conflicts in indexes are inevitable. To | |
11505 | overcome this issue, @code{match_operands} and @code{match_operators}, | |
11506 | which were introduced into the output pattern, are renumerated when all | |
11507 | @code{match_dup}s are replaced. | |
11508 | ||
11509 | Number of alternatives in @code{match_operand}s introduced into the | |
11510 | output template @code{M} could differ from the number of alternatives in | |
11511 | the original pattern @code{N}, so in the resultant pattern there would | |
11512 | be @code{N*M} alternatives. Thus, constraints from the original pattern | |
11513 | would be duplicated @code{N} times, constraints from the output pattern | |
11514 | would be duplicated @code{M} times, producing all possible combinations. | |
11515 | @end ifset | |
11516 | ||
11517 | @ifset INTERNALS | |
11518 | @node Constant Definitions | |
11519 | @section Constant Definitions | |
11520 | @cindex constant definitions | |
11521 | @findex define_constants | |
11522 | ||
11523 | Using literal constants inside instruction patterns reduces legibility and | |
11524 | can be a maintenance problem. | |
11525 | ||
11526 | To overcome this problem, you may use the @code{define_constants} | |
11527 | expression. It contains a vector of name-value pairs. From that | |
11528 | point on, wherever any of the names appears in the MD file, it is as | |
11529 | if the corresponding value had been written instead. You may use | |
11530 | @code{define_constants} multiple times; each appearance adds more | |
11531 | constants to the table. It is an error to redefine a constant with | |
11532 | a different value. | |
11533 | ||
11534 | To come back to the a29k load multiple example, instead of | |
11535 | ||
11536 | @smallexample | |
11537 | (define_insn "" | |
11538 | [(match_parallel 0 "load_multiple_operation" | |
11539 | [(set (match_operand:SI 1 "gpc_reg_operand" "=r") | |
11540 | (match_operand:SI 2 "memory_operand" "m")) | |
11541 | (use (reg:SI 179)) | |
11542 | (clobber (reg:SI 179))])] | |
11543 | "" | |
11544 | "loadm 0,0,%1,%2") | |
11545 | @end smallexample | |
11546 | ||
11547 | You could write: | |
11548 | ||
11549 | @smallexample | |
11550 | (define_constants [ | |
11551 | (R_BP 177) | |
11552 | (R_FC 178) | |
11553 | (R_CR 179) | |
11554 | (R_Q 180) | |
11555 | ]) | |
11556 | ||
11557 | (define_insn "" | |
11558 | [(match_parallel 0 "load_multiple_operation" | |
11559 | [(set (match_operand:SI 1 "gpc_reg_operand" "=r") | |
11560 | (match_operand:SI 2 "memory_operand" "m")) | |
11561 | (use (reg:SI R_CR)) | |
11562 | (clobber (reg:SI R_CR))])] | |
11563 | "" | |
11564 | "loadm 0,0,%1,%2") | |
11565 | @end smallexample | |
11566 | ||
11567 | The constants that are defined with a define_constant are also output | |
11568 | in the insn-codes.h header file as #defines. | |
11569 | ||
11570 | @cindex enumerations | |
11571 | @findex define_c_enum | |
11572 | You can also use the machine description file to define enumerations. | |
11573 | Like the constants defined by @code{define_constant}, these enumerations | |
11574 | are visible to both the machine description file and the main C code. | |
11575 | ||
11576 | The syntax is as follows: | |
11577 | ||
11578 | @smallexample | |
11579 | (define_c_enum "@var{name}" [ | |
11580 | @var{value0} | |
11581 | @var{value1} | |
11582 | (@var{value32} 32) | |
11583 | @var{value33} | |
11584 | @dots{} | |
11585 | @var{valuen} | |
11586 | ]) | |
11587 | @end smallexample | |
11588 | ||
11589 | This definition causes the equivalent of the following C code to appear | |
11590 | in @file{insn-constants.h}: | |
11591 | ||
11592 | @smallexample | |
11593 | enum @var{name} @{ | |
11594 | @var{value0} = 0, | |
11595 | @var{value1} = 1, | |
11596 | @var{value32} = 32, | |
11597 | @var{value33} = 33, | |
11598 | @dots{} | |
11599 | @var{valuen} = @var{n} | |
11600 | @}; | |
11601 | #define NUM_@var{cname}_VALUES (@var{n} + 1) | |
11602 | @end smallexample | |
11603 | ||
11604 | where @var{cname} is the capitalized form of @var{name}. | |
11605 | It also makes each @var{valuei} available in the machine description | |
11606 | file, just as if it had been declared with: | |
11607 | ||
11608 | @smallexample | |
11609 | (define_constants [(@var{valuei} @var{i})]) | |
11610 | @end smallexample | |
11611 | ||
11612 | Each @var{valuei} is usually an upper-case identifier and usually | |
11613 | begins with @var{cname}. | |
11614 | ||
11615 | You can split the enumeration definition into as many statements as | |
11616 | you like. The above example is directly equivalent to: | |
11617 | ||
11618 | @smallexample | |
11619 | (define_c_enum "@var{name}" [@var{value0}]) | |
11620 | (define_c_enum "@var{name}" [@var{value1}]) | |
11621 | @dots{} | |
11622 | (define_c_enum "@var{name}" [@var{valuen}]) | |
11623 | @end smallexample | |
11624 | ||
11625 | Splitting the enumeration helps to improve the modularity of each | |
11626 | individual @code{.md} file. For example, if a port defines its | |
11627 | synchronization instructions in a separate @file{sync.md} file, | |
11628 | it is convenient to define all synchronization-specific enumeration | |
11629 | values in @file{sync.md} rather than in the main @file{.md} file. | |
11630 | ||
11631 | Some enumeration names have special significance to GCC: | |
11632 | ||
11633 | @table @code | |
d77de738 | 11634 | @findex unspec_volatile |
f33d7a88 | 11635 | @item unspecv |
d77de738 ML |
11636 | If an enumeration called @code{unspecv} is defined, GCC will use it |
11637 | when printing out @code{unspec_volatile} expressions. For example: | |
11638 | ||
11639 | @smallexample | |
11640 | (define_c_enum "unspecv" [ | |
11641 | UNSPECV_BLOCKAGE | |
11642 | ]) | |
11643 | @end smallexample | |
11644 | ||
11645 | causes GCC to print @samp{(unspec_volatile @dots{} 0)} as: | |
11646 | ||
11647 | @smallexample | |
11648 | (unspec_volatile ... UNSPECV_BLOCKAGE) | |
11649 | @end smallexample | |
11650 | ||
d77de738 | 11651 | @findex unspec |
f33d7a88 | 11652 | @item unspec |
d77de738 ML |
11653 | If an enumeration called @code{unspec} is defined, GCC will use |
11654 | it when printing out @code{unspec} expressions. GCC will also use | |
11655 | it when printing out @code{unspec_volatile} expressions unless an | |
11656 | @code{unspecv} enumeration is also defined. You can therefore | |
11657 | decide whether to keep separate enumerations for volatile and | |
11658 | non-volatile expressions or whether to use the same enumeration | |
11659 | for both. | |
11660 | @end table | |
11661 | ||
11662 | @findex define_enum | |
11663 | @anchor{define_enum} | |
11664 | Another way of defining an enumeration is to use @code{define_enum}: | |
11665 | ||
11666 | @smallexample | |
11667 | (define_enum "@var{name}" [ | |
11668 | @var{value0} | |
11669 | @var{value1} | |
11670 | @dots{} | |
11671 | @var{valuen} | |
11672 | ]) | |
11673 | @end smallexample | |
11674 | ||
11675 | This directive implies: | |
11676 | ||
11677 | @smallexample | |
11678 | (define_c_enum "@var{name}" [ | |
11679 | @var{cname}_@var{cvalue0} | |
11680 | @var{cname}_@var{cvalue1} | |
11681 | @dots{} | |
11682 | @var{cname}_@var{cvaluen} | |
11683 | ]) | |
11684 | @end smallexample | |
11685 | ||
11686 | @findex define_enum_attr | |
11687 | where @var{cvaluei} is the capitalized form of @var{valuei}. | |
11688 | However, unlike @code{define_c_enum}, the enumerations defined | |
11689 | by @code{define_enum} can be used in attribute specifications | |
11690 | (@pxref{define_enum_attr}). | |
11691 | @end ifset | |
11692 | @ifset INTERNALS | |
11693 | @node Iterators | |
11694 | @section Iterators | |
11695 | @cindex iterators in @file{.md} files | |
11696 | ||
11697 | Ports often need to define similar patterns for more than one machine | |
11698 | mode or for more than one rtx code. GCC provides some simple iterator | |
11699 | facilities to make this process easier. | |
11700 | ||
11701 | @menu | |
11702 | * Mode Iterators:: Generating variations of patterns for different modes. | |
11703 | * Code Iterators:: Doing the same for codes. | |
11704 | * Int Iterators:: Doing the same for integers. | |
11705 | * Subst Iterators:: Generating variations of patterns for define_subst. | |
11706 | * Parameterized Names:: Specifying iterator values in C++ code. | |
11707 | @end menu | |
11708 | ||
11709 | @node Mode Iterators | |
11710 | @subsection Mode Iterators | |
11711 | @cindex mode iterators in @file{.md} files | |
11712 | ||
11713 | Ports often need to define similar patterns for two or more different modes. | |
11714 | For example: | |
11715 | ||
11716 | @itemize @bullet | |
11717 | @item | |
11718 | If a processor has hardware support for both single and double | |
11719 | floating-point arithmetic, the @code{SFmode} patterns tend to be | |
11720 | very similar to the @code{DFmode} ones. | |
11721 | ||
11722 | @item | |
11723 | If a port uses @code{SImode} pointers in one configuration and | |
11724 | @code{DImode} pointers in another, it will usually have very similar | |
11725 | @code{SImode} and @code{DImode} patterns for manipulating pointers. | |
11726 | @end itemize | |
11727 | ||
11728 | Mode iterators allow several patterns to be instantiated from one | |
11729 | @file{.md} file template. They can be used with any type of | |
11730 | rtx-based construct, such as a @code{define_insn}, | |
11731 | @code{define_split}, or @code{define_peephole2}. | |
11732 | ||
11733 | @menu | |
11734 | * Defining Mode Iterators:: Defining a new mode iterator. | |
11735 | * Substitutions:: Combining mode iterators with substitutions | |
11736 | * Examples:: Examples | |
11737 | @end menu | |
11738 | ||
11739 | @node Defining Mode Iterators | |
11740 | @subsubsection Defining Mode Iterators | |
11741 | @findex define_mode_iterator | |
11742 | ||
11743 | The syntax for defining a mode iterator is: | |
11744 | ||
11745 | @smallexample | |
11746 | (define_mode_iterator @var{name} [(@var{mode1} "@var{cond1}") @dots{} (@var{moden} "@var{condn}")]) | |
11747 | @end smallexample | |
11748 | ||
11749 | This allows subsequent @file{.md} file constructs to use the mode suffix | |
11750 | @code{:@var{name}}. Every construct that does so will be expanded | |
11751 | @var{n} times, once with every use of @code{:@var{name}} replaced by | |
11752 | @code{:@var{mode1}}, once with every use replaced by @code{:@var{mode2}}, | |
11753 | and so on. In the expansion for a particular @var{modei}, every | |
11754 | C condition will also require that @var{condi} be true. | |
11755 | ||
11756 | For example: | |
11757 | ||
11758 | @smallexample | |
11759 | (define_mode_iterator P [(SI "Pmode == SImode") (DI "Pmode == DImode")]) | |
11760 | @end smallexample | |
11761 | ||
11762 | defines a new mode suffix @code{:P}. Every construct that uses | |
11763 | @code{:P} will be expanded twice, once with every @code{:P} replaced | |
11764 | by @code{:SI} and once with every @code{:P} replaced by @code{:DI}. | |
11765 | The @code{:SI} version will only apply if @code{Pmode == SImode} and | |
11766 | the @code{:DI} version will only apply if @code{Pmode == DImode}. | |
11767 | ||
11768 | As with other @file{.md} conditions, an empty string is treated | |
11769 | as ``always true''. @code{(@var{mode} "")} can also be abbreviated | |
11770 | to @code{@var{mode}}. For example: | |
11771 | ||
11772 | @smallexample | |
11773 | (define_mode_iterator GPR [SI (DI "TARGET_64BIT")]) | |
11774 | @end smallexample | |
11775 | ||
11776 | means that the @code{:DI} expansion only applies if @code{TARGET_64BIT} | |
11777 | but that the @code{:SI} expansion has no such constraint. | |
11778 | ||
11779 | Iterators are applied in the order they are defined. This can be | |
11780 | significant if two iterators are used in a construct that requires | |
11781 | substitutions. @xref{Substitutions}. | |
11782 | ||
11783 | @node Substitutions | |
11784 | @subsubsection Substitution in Mode Iterators | |
11785 | @findex define_mode_attr | |
11786 | ||
11787 | If an @file{.md} file construct uses mode iterators, each version of the | |
11788 | construct will often need slightly different strings or modes. For | |
11789 | example: | |
11790 | ||
11791 | @itemize @bullet | |
11792 | @item | |
11793 | When a @code{define_expand} defines several @code{add@var{m}3} patterns | |
11794 | (@pxref{Standard Names}), each expander will need to use the | |
11795 | appropriate mode name for @var{m}. | |
11796 | ||
11797 | @item | |
11798 | When a @code{define_insn} defines several instruction patterns, | |
11799 | each instruction will often use a different assembler mnemonic. | |
11800 | ||
11801 | @item | |
11802 | When a @code{define_insn} requires operands with different modes, | |
11803 | using an iterator for one of the operand modes usually requires a specific | |
11804 | mode for the other operand(s). | |
11805 | @end itemize | |
11806 | ||
11807 | GCC supports such variations through a system of ``mode attributes''. | |
11808 | There are two standard attributes: @code{mode}, which is the name of | |
11809 | the mode in lower case, and @code{MODE}, which is the same thing in | |
11810 | upper case. You can define other attributes using: | |
11811 | ||
11812 | @smallexample | |
11813 | (define_mode_attr @var{name} [(@var{mode1} "@var{value1}") @dots{} (@var{moden} "@var{valuen}")]) | |
11814 | @end smallexample | |
11815 | ||
11816 | where @var{name} is the name of the attribute and @var{valuei} | |
11817 | is the value associated with @var{modei}. | |
11818 | ||
11819 | When GCC replaces some @var{:iterator} with @var{:mode}, it will scan | |
11820 | each string and mode in the pattern for sequences of the form | |
11821 | @code{<@var{iterator}:@var{attr}>}, where @var{attr} is the name of a | |
11822 | mode attribute. If the attribute is defined for @var{mode}, the whole | |
11823 | @code{<@dots{}>} sequence will be replaced by the appropriate attribute | |
11824 | value. | |
11825 | ||
11826 | For example, suppose an @file{.md} file has: | |
11827 | ||
11828 | @smallexample | |
11829 | (define_mode_iterator P [(SI "Pmode == SImode") (DI "Pmode == DImode")]) | |
11830 | (define_mode_attr load [(SI "lw") (DI "ld")]) | |
11831 | @end smallexample | |
11832 | ||
11833 | If one of the patterns that uses @code{:P} contains the string | |
11834 | @code{"<P:load>\t%0,%1"}, the @code{SI} version of that pattern | |
11835 | will use @code{"lw\t%0,%1"} and the @code{DI} version will use | |
11836 | @code{"ld\t%0,%1"}. | |
11837 | ||
11838 | Here is an example of using an attribute for a mode: | |
11839 | ||
11840 | @smallexample | |
11841 | (define_mode_iterator LONG [SI DI]) | |
11842 | (define_mode_attr SHORT [(SI "HI") (DI "SI")]) | |
11843 | (define_insn @dots{} | |
11844 | (sign_extend:LONG (match_operand:<LONG:SHORT> @dots{})) @dots{}) | |
11845 | @end smallexample | |
11846 | ||
11847 | The @code{@var{iterator}:} prefix may be omitted, in which case the | |
11848 | substitution will be attempted for every iterator expansion. | |
11849 | ||
11850 | @node Examples | |
11851 | @subsubsection Mode Iterator Examples | |
11852 | ||
11853 | Here is an example from the MIPS port. It defines the following | |
11854 | modes and attributes (among others): | |
11855 | ||
11856 | @smallexample | |
11857 | (define_mode_iterator GPR [SI (DI "TARGET_64BIT")]) | |
11858 | (define_mode_attr d [(SI "") (DI "d")]) | |
11859 | @end smallexample | |
11860 | ||
11861 | and uses the following template to define both @code{subsi3} | |
11862 | and @code{subdi3}: | |
11863 | ||
11864 | @smallexample | |
11865 | (define_insn "sub<mode>3" | |
11866 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
11867 | (minus:GPR (match_operand:GPR 1 "register_operand" "d") | |
11868 | (match_operand:GPR 2 "register_operand" "d")))] | |
11869 | "" | |
11870 | "<d>subu\t%0,%1,%2" | |
11871 | [(set_attr "type" "arith") | |
11872 | (set_attr "mode" "<MODE>")]) | |
11873 | @end smallexample | |
11874 | ||
11875 | This is exactly equivalent to: | |
11876 | ||
11877 | @smallexample | |
11878 | (define_insn "subsi3" | |
11879 | [(set (match_operand:SI 0 "register_operand" "=d") | |
11880 | (minus:SI (match_operand:SI 1 "register_operand" "d") | |
11881 | (match_operand:SI 2 "register_operand" "d")))] | |
11882 | "" | |
11883 | "subu\t%0,%1,%2" | |
11884 | [(set_attr "type" "arith") | |
11885 | (set_attr "mode" "SI")]) | |
11886 | ||
11887 | (define_insn "subdi3" | |
11888 | [(set (match_operand:DI 0 "register_operand" "=d") | |
11889 | (minus:DI (match_operand:DI 1 "register_operand" "d") | |
11890 | (match_operand:DI 2 "register_operand" "d")))] | |
11891 | "TARGET_64BIT" | |
11892 | "dsubu\t%0,%1,%2" | |
11893 | [(set_attr "type" "arith") | |
11894 | (set_attr "mode" "DI")]) | |
11895 | @end smallexample | |
11896 | ||
11897 | @node Code Iterators | |
11898 | @subsection Code Iterators | |
11899 | @cindex code iterators in @file{.md} files | |
11900 | @findex define_code_iterator | |
11901 | @findex define_code_attr | |
11902 | ||
11903 | Code iterators operate in a similar way to mode iterators. @xref{Mode Iterators}. | |
11904 | ||
11905 | The construct: | |
11906 | ||
11907 | @smallexample | |
11908 | (define_code_iterator @var{name} [(@var{code1} "@var{cond1}") @dots{} (@var{coden} "@var{condn}")]) | |
11909 | @end smallexample | |
11910 | ||
11911 | defines a pseudo rtx code @var{name} that can be instantiated as | |
11912 | @var{codei} if condition @var{condi} is true. Each @var{codei} | |
11913 | must have the same rtx format. @xref{RTL Classes}. | |
11914 | ||
11915 | As with mode iterators, each pattern that uses @var{name} will be | |
11916 | expanded @var{n} times, once with all uses of @var{name} replaced by | |
11917 | @var{code1}, once with all uses replaced by @var{code2}, and so on. | |
11918 | @xref{Defining Mode Iterators}. | |
11919 | ||
11920 | It is possible to define attributes for codes as well as for modes. | |
11921 | There are two standard code attributes: @code{code}, the name of the | |
11922 | code in lower case, and @code{CODE}, the name of the code in upper case. | |
11923 | Other attributes are defined using: | |
11924 | ||
11925 | @smallexample | |
11926 | (define_code_attr @var{name} [(@var{code1} "@var{value1}") @dots{} (@var{coden} "@var{valuen}")]) | |
11927 | @end smallexample | |
11928 | ||
11929 | Instruction patterns can use code attributes as rtx codes, which can be | |
11930 | useful if two sets of codes act in tandem. For example, the following | |
11931 | @code{define_insn} defines two patterns, one calculating a signed absolute | |
11932 | difference and another calculating an unsigned absolute difference: | |
11933 | ||
11934 | @smallexample | |
11935 | (define_code_iterator any_max [smax umax]) | |
11936 | (define_code_attr paired_min [(smax "smin") (umax "umin")]) | |
11937 | (define_insn @dots{} | |
11938 | [(set (match_operand:SI 0 @dots{}) | |
11939 | (minus:SI (any_max:SI (match_operand:SI 1 @dots{}) | |
11940 | (match_operand:SI 2 @dots{})) | |
11941 | (<paired_min>:SI (match_dup 1) (match_dup 2))))] | |
11942 | @dots{}) | |
11943 | @end smallexample | |
11944 | ||
11945 | The signed version of the instruction uses @code{smax} and @code{smin} | |
11946 | while the unsigned version uses @code{umax} and @code{umin}. There | |
11947 | are no versions that pair @code{smax} with @code{umin} or @code{umax} | |
11948 | with @code{smin}. | |
11949 | ||
11950 | Here's an example of code iterators in action, taken from the MIPS port: | |
11951 | ||
11952 | @smallexample | |
11953 | (define_code_iterator any_cond [unordered ordered unlt unge uneq ltgt unle ungt | |
11954 | eq ne gt ge lt le gtu geu ltu leu]) | |
11955 | ||
11956 | (define_expand "b<code>" | |
11957 | [(set (pc) | |
11958 | (if_then_else (any_cond:CC (cc0) | |
11959 | (const_int 0)) | |
11960 | (label_ref (match_operand 0 "")) | |
11961 | (pc)))] | |
11962 | "" | |
11963 | @{ | |
11964 | gen_conditional_branch (operands, <CODE>); | |
11965 | DONE; | |
11966 | @}) | |
11967 | @end smallexample | |
11968 | ||
11969 | This is equivalent to: | |
11970 | ||
11971 | @smallexample | |
11972 | (define_expand "bunordered" | |
11973 | [(set (pc) | |
11974 | (if_then_else (unordered:CC (cc0) | |
11975 | (const_int 0)) | |
11976 | (label_ref (match_operand 0 "")) | |
11977 | (pc)))] | |
11978 | "" | |
11979 | @{ | |
11980 | gen_conditional_branch (operands, UNORDERED); | |
11981 | DONE; | |
11982 | @}) | |
11983 | ||
11984 | (define_expand "bordered" | |
11985 | [(set (pc) | |
11986 | (if_then_else (ordered:CC (cc0) | |
11987 | (const_int 0)) | |
11988 | (label_ref (match_operand 0 "")) | |
11989 | (pc)))] | |
11990 | "" | |
11991 | @{ | |
11992 | gen_conditional_branch (operands, ORDERED); | |
11993 | DONE; | |
11994 | @}) | |
11995 | ||
11996 | @dots{} | |
11997 | @end smallexample | |
11998 | ||
11999 | @node Int Iterators | |
12000 | @subsection Int Iterators | |
12001 | @cindex int iterators in @file{.md} files | |
12002 | @findex define_int_iterator | |
12003 | @findex define_int_attr | |
12004 | ||
12005 | Int iterators operate in a similar way to code iterators. @xref{Code Iterators}. | |
12006 | ||
12007 | The construct: | |
12008 | ||
12009 | @smallexample | |
12010 | (define_int_iterator @var{name} [(@var{int1} "@var{cond1}") @dots{} (@var{intn} "@var{condn}")]) | |
12011 | @end smallexample | |
12012 | ||
12013 | defines a pseudo integer constant @var{name} that can be instantiated as | |
b0ad9159 RS |
12014 | @var{inti} if condition @var{condi} is true. Int iterators can appear in |
12015 | only those rtx fields that have `i', `n', `w', or `p' as the specifier. | |
12016 | This means that each @var{int} has to be a constant defined using | |
12017 | @samp{define_constant} or @samp{define_c_enum}. | |
d77de738 ML |
12018 | |
12019 | As with mode and code iterators, each pattern that uses @var{name} will be | |
12020 | expanded @var{n} times, once with all uses of @var{name} replaced by | |
12021 | @var{int1}, once with all uses replaced by @var{int2}, and so on. | |
12022 | @xref{Defining Mode Iterators}. | |
12023 | ||
12024 | It is possible to define attributes for ints as well as for codes and modes. | |
12025 | Attributes are defined using: | |
12026 | ||
12027 | @smallexample | |
b0ad9159 | 12028 | (define_int_attr @var{attr_name} [(@var{int1} "@var{value1}") @dots{} (@var{intn} "@var{valuen}")]) |
d77de738 ML |
12029 | @end smallexample |
12030 | ||
b0ad9159 RS |
12031 | In additon to these user-defined attributes, it is possible to use |
12032 | @samp{<@var{name}>} to refer to the current expansion of iterator | |
12033 | @var{name} (such as @var{int1}, @var{int2}, and so on). | |
12034 | ||
d77de738 ML |
12035 | Here's an example of int iterators in action, taken from the ARM port: |
12036 | ||
12037 | @smallexample | |
12038 | (define_int_iterator QABSNEG [UNSPEC_VQABS UNSPEC_VQNEG]) | |
12039 | ||
12040 | (define_int_attr absneg [(UNSPEC_VQABS "abs") (UNSPEC_VQNEG "neg")]) | |
12041 | ||
12042 | (define_insn "neon_vq<absneg><mode>" | |
12043 | [(set (match_operand:VDQIW 0 "s_register_operand" "=w") | |
12044 | (unspec:VDQIW [(match_operand:VDQIW 1 "s_register_operand" "w") | |
12045 | (match_operand:SI 2 "immediate_operand" "i")] | |
12046 | QABSNEG))] | |
12047 | "TARGET_NEON" | |
12048 | "vq<absneg>.<V_s_elem>\t%<V_reg>0, %<V_reg>1" | |
12049 | [(set_attr "type" "neon_vqneg_vqabs")] | |
12050 | ) | |
12051 | ||
12052 | @end smallexample | |
12053 | ||
12054 | This is equivalent to: | |
12055 | ||
12056 | @smallexample | |
12057 | (define_insn "neon_vqabs<mode>" | |
12058 | [(set (match_operand:VDQIW 0 "s_register_operand" "=w") | |
12059 | (unspec:VDQIW [(match_operand:VDQIW 1 "s_register_operand" "w") | |
12060 | (match_operand:SI 2 "immediate_operand" "i")] | |
12061 | UNSPEC_VQABS))] | |
12062 | "TARGET_NEON" | |
12063 | "vqabs.<V_s_elem>\t%<V_reg>0, %<V_reg>1" | |
12064 | [(set_attr "type" "neon_vqneg_vqabs")] | |
12065 | ) | |
12066 | ||
12067 | (define_insn "neon_vqneg<mode>" | |
12068 | [(set (match_operand:VDQIW 0 "s_register_operand" "=w") | |
12069 | (unspec:VDQIW [(match_operand:VDQIW 1 "s_register_operand" "w") | |
12070 | (match_operand:SI 2 "immediate_operand" "i")] | |
12071 | UNSPEC_VQNEG))] | |
12072 | "TARGET_NEON" | |
12073 | "vqneg.<V_s_elem>\t%<V_reg>0, %<V_reg>1" | |
12074 | [(set_attr "type" "neon_vqneg_vqabs")] | |
12075 | ) | |
12076 | ||
12077 | @end smallexample | |
12078 | ||
12079 | @node Subst Iterators | |
12080 | @subsection Subst Iterators | |
12081 | @cindex subst iterators in @file{.md} files | |
12082 | @findex define_subst | |
12083 | @findex define_subst_attr | |
12084 | ||
12085 | Subst iterators are special type of iterators with the following | |
12086 | restrictions: they could not be declared explicitly, they always have | |
12087 | only two values, and they do not have explicit dedicated name. | |
12088 | Subst-iterators are triggered only when corresponding subst-attribute is | |
12089 | used in RTL-pattern. | |
12090 | ||
12091 | Subst iterators transform templates in the following way: the templates | |
12092 | are duplicated, the subst-attributes in these templates are replaced | |
12093 | with the corresponding values, and a new attribute is implicitly added | |
12094 | to the given @code{define_insn}/@code{define_expand}. The name of the | |
12095 | added attribute matches the name of @code{define_subst}. Such | |
12096 | attributes are declared implicitly, and it is not allowed to have a | |
12097 | @code{define_attr} named as a @code{define_subst}. | |
12098 | ||
12099 | Each subst iterator is linked to a @code{define_subst}. It is declared | |
12100 | implicitly by the first appearance of the corresponding | |
12101 | @code{define_subst_attr}, and it is not allowed to define it explicitly. | |
12102 | ||
12103 | Declarations of subst-attributes have the following syntax: | |
12104 | ||
12105 | @findex define_subst_attr | |
12106 | @smallexample | |
12107 | (define_subst_attr "@var{name}" | |
12108 | "@var{subst-name}" | |
12109 | "@var{no-subst-value}" | |
12110 | "@var{subst-applied-value}") | |
12111 | @end smallexample | |
12112 | ||
12113 | @var{name} is a string with which the given subst-attribute could be | |
12114 | referred to. | |
12115 | ||
12116 | @var{subst-name} shows which @code{define_subst} should be applied to an | |
12117 | RTL-template if the given subst-attribute is present in the | |
12118 | RTL-template. | |
12119 | ||
12120 | @var{no-subst-value} is a value with which subst-attribute would be | |
12121 | replaced in the first copy of the original RTL-template. | |
12122 | ||
12123 | @var{subst-applied-value} is a value with which subst-attribute would be | |
12124 | replaced in the second copy of the original RTL-template. | |
12125 | ||
12126 | @node Parameterized Names | |
12127 | @subsection Parameterized Names | |
12128 | @cindex @samp{@@} in instruction pattern names | |
12129 | Ports sometimes need to apply iterators using C++ code, in order to | |
12130 | get the code or RTL pattern for a specific instruction. For example, | |
12131 | suppose we have the @samp{neon_vq<absneg><mode>} pattern given above: | |
12132 | ||
12133 | @smallexample | |
12134 | (define_int_iterator QABSNEG [UNSPEC_VQABS UNSPEC_VQNEG]) | |
12135 | ||
12136 | (define_int_attr absneg [(UNSPEC_VQABS "abs") (UNSPEC_VQNEG "neg")]) | |
12137 | ||
12138 | (define_insn "neon_vq<absneg><mode>" | |
12139 | [(set (match_operand:VDQIW 0 "s_register_operand" "=w") | |
12140 | (unspec:VDQIW [(match_operand:VDQIW 1 "s_register_operand" "w") | |
12141 | (match_operand:SI 2 "immediate_operand" "i")] | |
12142 | QABSNEG))] | |
12143 | @dots{} | |
12144 | ) | |
12145 | @end smallexample | |
12146 | ||
12147 | A port might need to generate this pattern for a variable | |
12148 | @samp{QABSNEG} value and a variable @samp{VDQIW} mode. There are two | |
12149 | ways of doing this. The first is to build the rtx for the pattern | |
12150 | directly from C++ code; this is a valid technique and avoids any risk | |
12151 | of combinatorial explosion. The second is to prefix the instruction | |
12152 | name with the special character @samp{@@}, which tells GCC to generate | |
12153 | the four additional functions below. In each case, @var{name} is the | |
12154 | name of the instruction without the leading @samp{@@} character, | |
12155 | without the @samp{<@dots{}>} placeholders, and with any underscore | |
12156 | before a @samp{<@dots{}>} placeholder removed if keeping it would | |
12157 | lead to a double or trailing underscore. | |
12158 | ||
12159 | @table @samp | |
12160 | @item insn_code maybe_code_for_@var{name} (@var{i1}, @var{i2}, @dots{}) | |
12161 | See whether replacing the first @samp{<@dots{}>} placeholder with | |
12162 | iterator value @var{i1}, the second with iterator value @var{i2}, and | |
12163 | so on, gives a valid instruction. Return its code if so, otherwise | |
12164 | return @code{CODE_FOR_nothing}. | |
12165 | ||
12166 | @item insn_code code_for_@var{name} (@var{i1}, @var{i2}, @dots{}) | |
12167 | Same, but abort the compiler if the requested instruction does not exist. | |
12168 | ||
12169 | @item rtx maybe_gen_@var{name} (@var{i1}, @var{i2}, @dots{}, @var{op0}, @var{op1}, @dots{}) | |
12170 | Check for a valid instruction in the same way as | |
12171 | @code{maybe_code_for_@var{name}}. If the instruction exists, | |
12172 | generate an instance of it using the operand values given by @var{op0}, | |
12173 | @var{op1}, and so on, otherwise return null. | |
12174 | ||
12175 | @item rtx gen_@var{name} (@var{i1}, @var{i2}, @dots{}, @var{op0}, @var{op1}, @dots{}) | |
12176 | Same, but abort the compiler if the requested instruction does not exist, | |
12177 | or if the instruction generator invoked the @code{FAIL} macro. | |
12178 | @end table | |
12179 | ||
12180 | For example, changing the pattern above to: | |
12181 | ||
12182 | @smallexample | |
12183 | (define_insn "@@neon_vq<absneg><mode>" | |
12184 | [(set (match_operand:VDQIW 0 "s_register_operand" "=w") | |
12185 | (unspec:VDQIW [(match_operand:VDQIW 1 "s_register_operand" "w") | |
12186 | (match_operand:SI 2 "immediate_operand" "i")] | |
12187 | QABSNEG))] | |
12188 | @dots{} | |
12189 | ) | |
12190 | @end smallexample | |
12191 | ||
12192 | would define the same patterns as before, but in addition would generate | |
12193 | the four functions below: | |
12194 | ||
12195 | @smallexample | |
12196 | insn_code maybe_code_for_neon_vq (int, machine_mode); | |
12197 | insn_code code_for_neon_vq (int, machine_mode); | |
12198 | rtx maybe_gen_neon_vq (int, machine_mode, rtx, rtx, rtx); | |
12199 | rtx gen_neon_vq (int, machine_mode, rtx, rtx, rtx); | |
12200 | @end smallexample | |
12201 | ||
12202 | Calling @samp{code_for_neon_vq (UNSPEC_VQABS, V8QImode)} | |
12203 | would then give @code{CODE_FOR_neon_vqabsv8qi}. | |
12204 | ||
12205 | It is possible to have multiple @samp{@@} patterns with the same | |
12206 | name and same types of iterator. For example: | |
12207 | ||
12208 | @smallexample | |
12209 | (define_insn "@@some_arithmetic_op<mode>" | |
12210 | [(set (match_operand:INTEGER_MODES 0 "register_operand") @dots{})] | |
12211 | @dots{} | |
12212 | ) | |
12213 | ||
12214 | (define_insn "@@some_arithmetic_op<mode>" | |
12215 | [(set (match_operand:FLOAT_MODES 0 "register_operand") @dots{})] | |
12216 | @dots{} | |
12217 | ) | |
12218 | @end smallexample | |
12219 | ||
12220 | would produce a single set of functions that handles both | |
12221 | @code{INTEGER_MODES} and @code{FLOAT_MODES}. | |
12222 | ||
12223 | It is also possible for these @samp{@@} patterns to have different | |
12224 | numbers of operands from each other. For example, patterns with | |
12225 | a binary rtl code might take three operands (one output and two inputs) | |
12226 | while patterns with a ternary rtl code might take four operands (one | |
12227 | output and three inputs). This combination would produce separate | |
12228 | @samp{maybe_gen_@var{name}} and @samp{gen_@var{name}} functions for | |
12229 | each operand count, but it would still produce a single | |
12230 | @samp{maybe_code_for_@var{name}} and a single @samp{code_for_@var{name}}. | |
12231 | ||
12232 | @end ifset |