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1 | @c Copyright (C) 1988, 1989, 1992, 1993, 1994, 1996, 1998, 2000, 2001 |
2 | @c Free Software Foundation, Inc. | |
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3 | @c This is part of the GCC manual. |
4 | @c For copying conditions, see the file gcc.texi. | |
5 | ||
6 | @ifset INTERNALS | |
7 | @node Machine Desc | |
8 | @chapter Machine Descriptions | |
9 | @cindex machine descriptions | |
10 | ||
11 | A machine description has two parts: a file of instruction patterns | |
12 | (@file{.md} file) and a C header file of macro definitions. | |
13 | ||
14 | The @file{.md} file for a target machine contains a pattern for each | |
15 | instruction that the target machine supports (or at least each instruction | |
16 | that is worth telling the compiler about). It may also contain comments. | |
17 | A semicolon causes the rest of the line to be a comment, unless the semicolon | |
18 | is inside a quoted string. | |
19 | ||
20 | See the next chapter for information on the C header file. | |
21 | ||
22 | @menu | |
55e4756f | 23 | * Overview:: How the machine description is used. |
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24 | * Patterns:: How to write instruction patterns. |
25 | * Example:: An explained example of a @code{define_insn} pattern. | |
26 | * RTL Template:: The RTL template defines what insns match a pattern. | |
27 | * Output Template:: The output template says how to make assembler code | |
28 | from such an insn. | |
29 | * Output Statement:: For more generality, write C code to output | |
30 | the assembler code. | |
31 | * Constraints:: When not all operands are general operands. | |
32 | * Standard Names:: Names mark patterns to use for code generation. | |
33 | * Pattern Ordering:: When the order of patterns makes a difference. | |
34 | * Dependent Patterns:: Having one pattern may make you need another. | |
35 | * Jump Patterns:: Special considerations for patterns for jump insns. | |
6e4fcc95 | 36 | * Looping Patterns:: How to define patterns for special looping insns. |
03dda8e3 | 37 | * Insn Canonicalizations::Canonicalization of Instructions |
03dda8e3 | 38 | * Expander Definitions::Generating a sequence of several RTL insns |
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39 | for a standard operation. |
40 | * Insn Splitting:: Splitting Instructions into Multiple Instructions. | |
41 | * Peephole Definitions::Defining machine-specific peephole optimizations. | |
03dda8e3 | 42 | * Insn Attributes:: Specifying the value of attributes for generated insns. |
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43 | * Conditional Execution::Generating @code{define_insn} patterns for |
44 | predication. | |
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45 | * Constant Definitions::Defining symbolic constants that can be used in the |
46 | md file. | |
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47 | @end menu |
48 | ||
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49 | @node Overview |
50 | @section Overview of How the Machine Description is Used | |
51 | ||
52 | There are three main conversions that happen in the compiler: | |
53 | ||
54 | @enumerate | |
55 | ||
56 | @item | |
57 | The front end reads the source code and builds a parse tree. | |
58 | ||
59 | @item | |
60 | The parse tree is used to generate an RTL insn list based on named | |
61 | instruction patterns. | |
62 | ||
63 | @item | |
64 | The insn list is matched against the RTL templates to produce assembler | |
65 | code. | |
66 | ||
67 | @end enumerate | |
68 | ||
69 | For the generate pass, only the names of the insns matter, from either a | |
70 | named @code{define_insn} or a @code{define_expand}. The compiler will | |
71 | choose the pattern with the right name and apply the operands according | |
72 | to the documentation later in this chapter, without regard for the RTL | |
73 | template or operand constraints. Note that the names the compiler looks | |
74 | for are hard-coded in the compiler - it will ignore unnamed patterns and | |
75 | patterns with names it doesn't know about, but if you don't provide a | |
76 | named pattern it needs, it will abort. | |
77 | ||
78 | If a @code{define_insn} is used, the template given is inserted into the | |
79 | insn list. If a @code{define_expand} is used, one of three things | |
80 | happens, based on the condition logic. The condition logic may manually | |
81 | create new insns for the insn list, say via @code{emit_insn()}, and | |
82 | invoke DONE. For certain named patterns, it may invoke FAIL to tell the | |
83 | compiler to use an alternate way of performing that task. If it invokes | |
84 | neither @code{DONE} nor @code{FAIL}, the template given in the pattern | |
85 | is inserted, as if the @code{define_expand} were a @code{define_insn}. | |
86 | ||
87 | Once the insn list is generated, various optimization passes convert, | |
88 | replace, and rearrange the insns in the insn list. This is where the | |
89 | @code{define_split} and @code{define_peephole} patterns get used, for | |
90 | example. | |
91 | ||
92 | Finally, the insn list's RTL is matched up with the RTL templates in the | |
93 | @code{define_insn} patterns, and those patterns are used to emit the | |
94 | final assembly code. For this purpose, each named @code{define_insn} | |
95 | acts like it's unnamed, since the names are ignored. | |
96 | ||
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97 | @node Patterns |
98 | @section Everything about Instruction Patterns | |
99 | @cindex patterns | |
100 | @cindex instruction patterns | |
101 | ||
102 | @findex define_insn | |
103 | Each instruction pattern contains an incomplete RTL expression, with pieces | |
104 | to be filled in later, operand constraints that restrict how the pieces can | |
105 | be filled in, and an output pattern or C code to generate the assembler | |
106 | output, all wrapped up in a @code{define_insn} expression. | |
107 | ||
108 | A @code{define_insn} is an RTL expression containing four or five operands: | |
109 | ||
110 | @enumerate | |
111 | @item | |
112 | An optional name. The presence of a name indicate that this instruction | |
113 | pattern can perform a certain standard job for the RTL-generation | |
114 | pass of the compiler. This pass knows certain names and will use | |
115 | the instruction patterns with those names, if the names are defined | |
116 | in the machine description. | |
117 | ||
118 | The absence of a name is indicated by writing an empty string | |
119 | where the name should go. Nameless instruction patterns are never | |
120 | used for generating RTL code, but they may permit several simpler insns | |
121 | to be combined later on. | |
122 | ||
123 | Names that are not thus known and used in RTL-generation have no | |
124 | effect; they are equivalent to no name at all. | |
125 | ||
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126 | For the purpose of debugging the compiler, you may also specify a |
127 | name beginning with the @samp{*} character. Such a name is used only | |
128 | for identifying the instruction in RTL dumps; it is entirely equivalent | |
129 | to having a nameless pattern for all other purposes. | |
130 | ||
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131 | @item |
132 | The @dfn{RTL template} (@pxref{RTL Template}) is a vector of incomplete | |
133 | RTL expressions which show what the instruction should look like. It is | |
134 | incomplete because it may contain @code{match_operand}, | |
135 | @code{match_operator}, and @code{match_dup} expressions that stand for | |
136 | operands of the instruction. | |
137 | ||
138 | If the vector has only one element, that element is the template for the | |
139 | instruction pattern. If the vector has multiple elements, then the | |
140 | instruction pattern is a @code{parallel} expression containing the | |
141 | elements described. | |
142 | ||
143 | @item | |
144 | @cindex pattern conditions | |
145 | @cindex conditions, in patterns | |
146 | A condition. This is a string which contains a C expression that is | |
147 | the final test to decide whether an insn body matches this pattern. | |
148 | ||
149 | @cindex named patterns and conditions | |
150 | For a named pattern, the condition (if present) may not depend on | |
151 | the data in the insn being matched, but only the target-machine-type | |
152 | flags. The compiler needs to test these conditions during | |
153 | initialization in order to learn exactly which named instructions are | |
154 | available in a particular run. | |
155 | ||
156 | @findex operands | |
157 | For nameless patterns, the condition is applied only when matching an | |
158 | individual insn, and only after the insn has matched the pattern's | |
159 | recognition template. The insn's operands may be found in the vector | |
160 | @code{operands}. | |
161 | ||
162 | @item | |
163 | The @dfn{output template}: a string that says how to output matching | |
164 | insns as assembler code. @samp{%} in this string specifies where | |
165 | to substitute the value of an operand. @xref{Output Template}. | |
166 | ||
167 | When simple substitution isn't general enough, you can specify a piece | |
168 | of C code to compute the output. @xref{Output Statement}. | |
169 | ||
170 | @item | |
171 | Optionally, a vector containing the values of attributes for insns matching | |
172 | this pattern. @xref{Insn Attributes}. | |
173 | @end enumerate | |
174 | ||
175 | @node Example | |
176 | @section Example of @code{define_insn} | |
177 | @cindex @code{define_insn} example | |
178 | ||
179 | Here is an actual example of an instruction pattern, for the 68000/68020. | |
180 | ||
181 | @example | |
182 | (define_insn "tstsi" | |
183 | [(set (cc0) | |
184 | (match_operand:SI 0 "general_operand" "rm"))] | |
185 | "" | |
186 | "* | |
187 | @{ if (TARGET_68020 || ! ADDRESS_REG_P (operands[0])) | |
188 | return \"tstl %0\"; | |
189 | return \"cmpl #0,%0\"; @}") | |
190 | @end example | |
191 | ||
192 | This is an instruction that sets the condition codes based on the value of | |
193 | a general operand. It has no condition, so any insn whose RTL description | |
194 | has the form shown may be handled according to this pattern. The name | |
195 | @samp{tstsi} means ``test a @code{SImode} value'' and tells the RTL generation | |
196 | pass that, when it is necessary to test such a value, an insn to do so | |
197 | can be constructed using this pattern. | |
198 | ||
199 | The output control string is a piece of C code which chooses which | |
200 | output template to return based on the kind of operand and the specific | |
201 | type of CPU for which code is being generated. | |
202 | ||
203 | @samp{"rm"} is an operand constraint. Its meaning is explained below. | |
204 | ||
205 | @node RTL Template | |
206 | @section RTL Template | |
207 | @cindex RTL insn template | |
208 | @cindex generating insns | |
209 | @cindex insns, generating | |
210 | @cindex recognizing insns | |
211 | @cindex insns, recognizing | |
212 | ||
213 | The RTL template is used to define which insns match the particular pattern | |
214 | and how to find their operands. For named patterns, the RTL template also | |
215 | says how to construct an insn from specified operands. | |
216 | ||
217 | Construction involves substituting specified operands into a copy of the | |
218 | template. Matching involves determining the values that serve as the | |
219 | operands in the insn being matched. Both of these activities are | |
220 | controlled by special expression types that direct matching and | |
221 | substitution of the operands. | |
222 | ||
223 | @table @code | |
224 | @findex match_operand | |
225 | @item (match_operand:@var{m} @var{n} @var{predicate} @var{constraint}) | |
226 | This expression is a placeholder for operand number @var{n} of | |
227 | the insn. When constructing an insn, operand number @var{n} | |
228 | will be substituted at this point. When matching an insn, whatever | |
229 | appears at this position in the insn will be taken as operand | |
230 | number @var{n}; but it must satisfy @var{predicate} or this instruction | |
231 | pattern will not match at all. | |
232 | ||
233 | Operand numbers must be chosen consecutively counting from zero in | |
234 | each instruction pattern. There may be only one @code{match_operand} | |
235 | expression in the pattern for each operand number. Usually operands | |
236 | are numbered in the order of appearance in @code{match_operand} | |
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237 | expressions. In the case of a @code{define_expand}, any operand numbers |
238 | used only in @code{match_dup} expressions have higher values than all | |
239 | other operand numbers. | |
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240 | |
241 | @var{predicate} is a string that is the name of a C function that accepts two | |
242 | arguments, an expression and a machine mode. During matching, the | |
243 | function will be called with the putative operand as the expression and | |
244 | @var{m} as the mode argument (if @var{m} is not specified, | |
245 | @code{VOIDmode} will be used, which normally causes @var{predicate} to accept | |
246 | any mode). If it returns zero, this instruction pattern fails to match. | |
247 | @var{predicate} may be an empty string; then it means no test is to be done | |
248 | on the operand, so anything which occurs in this position is valid. | |
249 | ||
250 | Most of the time, @var{predicate} will reject modes other than @var{m}---but | |
251 | not always. For example, the predicate @code{address_operand} uses | |
252 | @var{m} as the mode of memory ref that the address should be valid for. | |
253 | Many predicates accept @code{const_int} nodes even though their mode is | |
254 | @code{VOIDmode}. | |
255 | ||
256 | @var{constraint} controls reloading and the choice of the best register | |
257 | class to use for a value, as explained later (@pxref{Constraints}). | |
258 | ||
259 | People are often unclear on the difference between the constraint and the | |
260 | predicate. The predicate helps decide whether a given insn matches the | |
261 | pattern. The constraint plays no role in this decision; instead, it | |
262 | controls various decisions in the case of an insn which does match. | |
263 | ||
264 | @findex general_operand | |
265 | On CISC machines, the most common @var{predicate} is | |
266 | @code{"general_operand"}. This function checks that the putative | |
267 | operand is either a constant, a register or a memory reference, and that | |
268 | it is valid for mode @var{m}. | |
269 | ||
270 | @findex register_operand | |
271 | For an operand that must be a register, @var{predicate} should be | |
272 | @code{"register_operand"}. Using @code{"general_operand"} would be | |
273 | valid, since the reload pass would copy any non-register operands | |
274 | through registers, but this would make GNU CC do extra work, it would | |
275 | prevent invariant operands (such as constant) from being removed from | |
276 | loops, and it would prevent the register allocator from doing the best | |
277 | possible job. On RISC machines, it is usually most efficient to allow | |
278 | @var{predicate} to accept only objects that the constraints allow. | |
279 | ||
280 | @findex immediate_operand | |
281 | For an operand that must be a constant, you must be sure to either use | |
282 | @code{"immediate_operand"} for @var{predicate}, or make the instruction | |
283 | pattern's extra condition require a constant, or both. You cannot | |
284 | expect the constraints to do this work! If the constraints allow only | |
285 | constants, but the predicate allows something else, the compiler will | |
286 | crash when that case arises. | |
287 | ||
288 | @findex match_scratch | |
289 | @item (match_scratch:@var{m} @var{n} @var{constraint}) | |
290 | This expression is also a placeholder for operand number @var{n} | |
291 | and indicates that operand must be a @code{scratch} or @code{reg} | |
292 | expression. | |
293 | ||
294 | When matching patterns, this is equivalent to | |
295 | ||
296 | @smallexample | |
297 | (match_operand:@var{m} @var{n} "scratch_operand" @var{pred}) | |
298 | @end smallexample | |
299 | ||
300 | but, when generating RTL, it produces a (@code{scratch}:@var{m}) | |
301 | expression. | |
302 | ||
303 | If the last few expressions in a @code{parallel} are @code{clobber} | |
304 | expressions whose operands are either a hard register or | |
305 | @code{match_scratch}, the combiner can add or delete them when | |
306 | necessary. @xref{Side Effects}. | |
307 | ||
308 | @findex match_dup | |
309 | @item (match_dup @var{n}) | |
310 | This expression is also a placeholder for operand number @var{n}. | |
311 | It is used when the operand needs to appear more than once in the | |
312 | insn. | |
313 | ||
314 | In construction, @code{match_dup} acts just like @code{match_operand}: | |
315 | the operand is substituted into the insn being constructed. But in | |
316 | matching, @code{match_dup} behaves differently. It assumes that operand | |
317 | number @var{n} has already been determined by a @code{match_operand} | |
318 | appearing earlier in the recognition template, and it matches only an | |
319 | identical-looking expression. | |
320 | ||
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321 | Note that @code{match_dup} should not be used to tell the compiler that |
322 | a particular register is being used for two operands (example: | |
323 | @code{add} that adds one register to another; the second register is | |
324 | both an input operand and the output operand). Use a matching | |
325 | constraint (@pxref{Simple Constraints}) for those. @code{match_dup} is for the cases where one | |
326 | operand is used in two places in the template, such as an instruction | |
327 | that computes both a quotient and a remainder, where the opcode takes | |
328 | two input operands but the RTL template has to refer to each of those | |
329 | twice; once for the quotient pattern and once for the remainder pattern. | |
330 | ||
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331 | @findex match_operator |
332 | @item (match_operator:@var{m} @var{n} @var{predicate} [@var{operands}@dots{}]) | |
333 | This pattern is a kind of placeholder for a variable RTL expression | |
334 | code. | |
335 | ||
336 | When constructing an insn, it stands for an RTL expression whose | |
337 | expression code is taken from that of operand @var{n}, and whose | |
338 | operands are constructed from the patterns @var{operands}. | |
339 | ||
340 | When matching an expression, it matches an expression if the function | |
341 | @var{predicate} returns nonzero on that expression @emph{and} the | |
342 | patterns @var{operands} match the operands of the expression. | |
343 | ||
344 | Suppose that the function @code{commutative_operator} is defined as | |
345 | follows, to match any expression whose operator is one of the | |
346 | commutative arithmetic operators of RTL and whose mode is @var{mode}: | |
347 | ||
348 | @smallexample | |
349 | int | |
350 | commutative_operator (x, mode) | |
351 | rtx x; | |
352 | enum machine_mode mode; | |
353 | @{ | |
354 | enum rtx_code code = GET_CODE (x); | |
355 | if (GET_MODE (x) != mode) | |
356 | return 0; | |
357 | return (GET_RTX_CLASS (code) == 'c' | |
358 | || code == EQ || code == NE); | |
359 | @} | |
360 | @end smallexample | |
361 | ||
362 | Then the following pattern will match any RTL expression consisting | |
363 | of a commutative operator applied to two general operands: | |
364 | ||
365 | @smallexample | |
366 | (match_operator:SI 3 "commutative_operator" | |
367 | [(match_operand:SI 1 "general_operand" "g") | |
368 | (match_operand:SI 2 "general_operand" "g")]) | |
369 | @end smallexample | |
370 | ||
371 | Here the vector @code{[@var{operands}@dots{}]} contains two patterns | |
372 | because the expressions to be matched all contain two operands. | |
373 | ||
374 | When this pattern does match, the two operands of the commutative | |
375 | operator are recorded as operands 1 and 2 of the insn. (This is done | |
376 | by the two instances of @code{match_operand}.) Operand 3 of the insn | |
377 | will be the entire commutative expression: use @code{GET_CODE | |
378 | (operands[3])} to see which commutative operator was used. | |
379 | ||
380 | The machine mode @var{m} of @code{match_operator} works like that of | |
381 | @code{match_operand}: it is passed as the second argument to the | |
382 | predicate function, and that function is solely responsible for | |
383 | deciding whether the expression to be matched ``has'' that mode. | |
384 | ||
385 | When constructing an insn, argument 3 of the gen-function will specify | |
386 | the operation (i.e. the expression code) for the expression to be | |
387 | made. It should be an RTL expression, whose expression code is copied | |
388 | into a new expression whose operands are arguments 1 and 2 of the | |
389 | gen-function. The subexpressions of argument 3 are not used; | |
390 | only its expression code matters. | |
391 | ||
392 | When @code{match_operator} is used in a pattern for matching an insn, | |
393 | it usually best if the operand number of the @code{match_operator} | |
394 | is higher than that of the actual operands of the insn. This improves | |
395 | register allocation because the register allocator often looks at | |
396 | operands 1 and 2 of insns to see if it can do register tying. | |
397 | ||
398 | There is no way to specify constraints in @code{match_operator}. The | |
399 | operand of the insn which corresponds to the @code{match_operator} | |
400 | never has any constraints because it is never reloaded as a whole. | |
401 | However, if parts of its @var{operands} are matched by | |
402 | @code{match_operand} patterns, those parts may have constraints of | |
403 | their own. | |
404 | ||
405 | @findex match_op_dup | |
406 | @item (match_op_dup:@var{m} @var{n}[@var{operands}@dots{}]) | |
407 | Like @code{match_dup}, except that it applies to operators instead of | |
408 | operands. When constructing an insn, operand number @var{n} will be | |
409 | substituted at this point. But in matching, @code{match_op_dup} behaves | |
410 | differently. It assumes that operand number @var{n} has already been | |
411 | determined by a @code{match_operator} appearing earlier in the | |
412 | recognition template, and it matches only an identical-looking | |
413 | expression. | |
414 | ||
415 | @findex match_parallel | |
416 | @item (match_parallel @var{n} @var{predicate} [@var{subpat}@dots{}]) | |
417 | This pattern is a placeholder for an insn that consists of a | |
418 | @code{parallel} expression with a variable number of elements. This | |
419 | expression should only appear at the top level of an insn pattern. | |
420 | ||
421 | When constructing an insn, operand number @var{n} will be substituted at | |
422 | this point. When matching an insn, it matches if the body of the insn | |
423 | is a @code{parallel} expression with at least as many elements as the | |
424 | vector of @var{subpat} expressions in the @code{match_parallel}, if each | |
425 | @var{subpat} matches the corresponding element of the @code{parallel}, | |
426 | @emph{and} the function @var{predicate} returns nonzero on the | |
427 | @code{parallel} that is the body of the insn. It is the responsibility | |
428 | of the predicate to validate elements of the @code{parallel} beyond | |
429 | those listed in the @code{match_parallel}.@refill | |
430 | ||
431 | A typical use of @code{match_parallel} is to match load and store | |
432 | multiple expressions, which can contain a variable number of elements | |
433 | in a @code{parallel}. For example, | |
434 | @c the following is *still* going over. need to change the code. | |
435 | @c also need to work on grouping of this example. --mew 1feb93 | |
436 | ||
437 | @smallexample | |
438 | (define_insn "" | |
439 | [(match_parallel 0 "load_multiple_operation" | |
440 | [(set (match_operand:SI 1 "gpc_reg_operand" "=r") | |
441 | (match_operand:SI 2 "memory_operand" "m")) | |
442 | (use (reg:SI 179)) | |
443 | (clobber (reg:SI 179))])] | |
444 | "" | |
445 | "loadm 0,0,%1,%2") | |
446 | @end smallexample | |
447 | ||
448 | This example comes from @file{a29k.md}. The function | |
449 | @code{load_multiple_operations} is defined in @file{a29k.c} and checks | |
450 | that subsequent elements in the @code{parallel} are the same as the | |
451 | @code{set} in the pattern, except that they are referencing subsequent | |
452 | registers and memory locations. | |
453 | ||
454 | An insn that matches this pattern might look like: | |
455 | ||
456 | @smallexample | |
457 | (parallel | |
458 | [(set (reg:SI 20) (mem:SI (reg:SI 100))) | |
459 | (use (reg:SI 179)) | |
460 | (clobber (reg:SI 179)) | |
461 | (set (reg:SI 21) | |
462 | (mem:SI (plus:SI (reg:SI 100) | |
463 | (const_int 4)))) | |
464 | (set (reg:SI 22) | |
465 | (mem:SI (plus:SI (reg:SI 100) | |
466 | (const_int 8))))]) | |
467 | @end smallexample | |
468 | ||
469 | @findex match_par_dup | |
470 | @item (match_par_dup @var{n} [@var{subpat}@dots{}]) | |
471 | Like @code{match_op_dup}, but for @code{match_parallel} instead of | |
472 | @code{match_operator}. | |
473 | ||
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474 | @findex match_insn |
475 | @item (match_insn @var{predicate}) | |
476 | Match a complete insn. Unlike the other @code{match_*} recognizers, | |
477 | @code{match_insn} does not take an operand number. | |
478 | ||
479 | The machine mode @var{m} of @code{match_insn} works like that of | |
480 | @code{match_operand}: it is passed as the second argument to the | |
481 | predicate function, and that function is solely responsible for | |
482 | deciding whether the expression to be matched ``has'' that mode. | |
483 | ||
484 | @findex match_insn2 | |
485 | @item (match_insn2 @var{n} @var{predicate}) | |
486 | Match a complete insn. | |
487 | ||
488 | The machine mode @var{m} of @code{match_insn2} works like that of | |
489 | @code{match_operand}: it is passed as the second argument to the | |
490 | predicate function, and that function is solely responsible for | |
491 | deciding whether the expression to be matched ``has'' that mode. | |
492 | ||
03dda8e3 RK |
493 | @end table |
494 | ||
495 | @node Output Template | |
496 | @section Output Templates and Operand Substitution | |
497 | @cindex output templates | |
498 | @cindex operand substitution | |
499 | ||
500 | @cindex @samp{%} in template | |
501 | @cindex percent sign | |
502 | The @dfn{output template} is a string which specifies how to output the | |
503 | assembler code for an instruction pattern. Most of the template is a | |
504 | fixed string which is output literally. The character @samp{%} is used | |
505 | to specify where to substitute an operand; it can also be used to | |
506 | identify places where different variants of the assembler require | |
507 | different syntax. | |
508 | ||
509 | In the simplest case, a @samp{%} followed by a digit @var{n} says to output | |
510 | operand @var{n} at that point in the string. | |
511 | ||
512 | @samp{%} followed by a letter and a digit says to output an operand in an | |
513 | alternate fashion. Four letters have standard, built-in meanings described | |
514 | below. The machine description macro @code{PRINT_OPERAND} can define | |
515 | additional letters with nonstandard meanings. | |
516 | ||
517 | @samp{%c@var{digit}} can be used to substitute an operand that is a | |
518 | constant value without the syntax that normally indicates an immediate | |
519 | operand. | |
520 | ||
521 | @samp{%n@var{digit}} is like @samp{%c@var{digit}} except that the value of | |
522 | the constant is negated before printing. | |
523 | ||
524 | @samp{%a@var{digit}} can be used to substitute an operand as if it were a | |
525 | memory reference, with the actual operand treated as the address. This may | |
526 | be useful when outputting a ``load address'' instruction, because often the | |
527 | assembler syntax for such an instruction requires you to write the operand | |
528 | as if it were a memory reference. | |
529 | ||
530 | @samp{%l@var{digit}} is used to substitute a @code{label_ref} into a jump | |
531 | instruction. | |
532 | ||
533 | @samp{%=} outputs a number which is unique to each instruction in the | |
534 | entire compilation. This is useful for making local labels to be | |
535 | referred to more than once in a single template that generates multiple | |
536 | assembler instructions. | |
537 | ||
538 | @samp{%} followed by a punctuation character specifies a substitution that | |
539 | does not use an operand. Only one case is standard: @samp{%%} outputs a | |
540 | @samp{%} into the assembler code. Other nonstandard cases can be | |
541 | defined in the @code{PRINT_OPERAND} macro. You must also define | |
542 | which punctuation characters are valid with the | |
543 | @code{PRINT_OPERAND_PUNCT_VALID_P} macro. | |
544 | ||
545 | @cindex \ | |
546 | @cindex backslash | |
547 | The template may generate multiple assembler instructions. Write the text | |
548 | for the instructions, with @samp{\;} between them. | |
549 | ||
550 | @cindex matching operands | |
551 | When the RTL contains two operands which are required by constraint to match | |
552 | each other, the output template must refer only to the lower-numbered operand. | |
553 | Matching operands are not always identical, and the rest of the compiler | |
554 | arranges to put the proper RTL expression for printing into the lower-numbered | |
555 | operand. | |
556 | ||
557 | One use of nonstandard letters or punctuation following @samp{%} is to | |
558 | distinguish between different assembler languages for the same machine; for | |
559 | example, Motorola syntax versus MIT syntax for the 68000. Motorola syntax | |
560 | requires periods in most opcode names, while MIT syntax does not. For | |
561 | example, the opcode @samp{movel} in MIT syntax is @samp{move.l} in Motorola | |
562 | syntax. The same file of patterns is used for both kinds of output syntax, | |
563 | but the character sequence @samp{%.} is used in each place where Motorola | |
564 | syntax wants a period. The @code{PRINT_OPERAND} macro for Motorola syntax | |
565 | defines the sequence to output a period; the macro for MIT syntax defines | |
566 | it to do nothing. | |
567 | ||
568 | @cindex @code{#} in template | |
569 | As a special case, a template consisting of the single character @code{#} | |
570 | instructs the compiler to first split the insn, and then output the | |
571 | resulting instructions separately. This helps eliminate redundancy in the | |
572 | output templates. If you have a @code{define_insn} that needs to emit | |
573 | multiple assembler instructions, and there is an matching @code{define_split} | |
574 | already defined, then you can simply use @code{#} as the output template | |
575 | instead of writing an output template that emits the multiple assembler | |
576 | instructions. | |
577 | ||
578 | If the macro @code{ASSEMBLER_DIALECT} is defined, you can use construct | |
579 | of the form @samp{@{option0|option1|option2@}} in the templates. These | |
580 | describe multiple variants of assembler language syntax. | |
581 | @xref{Instruction Output}. | |
582 | ||
583 | @node Output Statement | |
584 | @section C Statements for Assembler Output | |
585 | @cindex output statements | |
586 | @cindex C statements for assembler output | |
587 | @cindex generating assembler output | |
588 | ||
589 | Often a single fixed template string cannot produce correct and efficient | |
590 | assembler code for all the cases that are recognized by a single | |
591 | instruction pattern. For example, the opcodes may depend on the kinds of | |
592 | operands; or some unfortunate combinations of operands may require extra | |
593 | machine instructions. | |
594 | ||
595 | If the output control string starts with a @samp{@@}, then it is actually | |
596 | a series of templates, each on a separate line. (Blank lines and | |
597 | leading spaces and tabs are ignored.) The templates correspond to the | |
598 | pattern's constraint alternatives (@pxref{Multi-Alternative}). For example, | |
599 | if a target machine has a two-address add instruction @samp{addr} to add | |
600 | into a register and another @samp{addm} to add a register to memory, you | |
601 | might write this pattern: | |
602 | ||
603 | @smallexample | |
604 | (define_insn "addsi3" | |
605 | [(set (match_operand:SI 0 "general_operand" "=r,m") | |
606 | (plus:SI (match_operand:SI 1 "general_operand" "0,0") | |
607 | (match_operand:SI 2 "general_operand" "g,r")))] | |
608 | "" | |
609 | "@@ | |
610 | addr %2,%0 | |
611 | addm %2,%0") | |
612 | @end smallexample | |
613 | ||
614 | @cindex @code{*} in template | |
615 | @cindex asterisk in template | |
616 | If the output control string starts with a @samp{*}, then it is not an | |
617 | output template but rather a piece of C program that should compute a | |
618 | template. It should execute a @code{return} statement to return the | |
619 | template-string you want. Most such templates use C string literals, which | |
620 | require doublequote characters to delimit them. To include these | |
621 | doublequote characters in the string, prefix each one with @samp{\}. | |
622 | ||
623 | The operands may be found in the array @code{operands}, whose C data type | |
624 | is @code{rtx []}. | |
625 | ||
626 | It is very common to select different ways of generating assembler code | |
627 | based on whether an immediate operand is within a certain range. Be | |
628 | careful when doing this, because the result of @code{INTVAL} is an | |
629 | integer on the host machine. If the host machine has more bits in an | |
630 | @code{int} than the target machine has in the mode in which the constant | |
631 | will be used, then some of the bits you get from @code{INTVAL} will be | |
632 | superfluous. For proper results, you must carefully disregard the | |
633 | values of those bits. | |
634 | ||
635 | @findex output_asm_insn | |
636 | It is possible to output an assembler instruction and then go on to output | |
637 | or compute more of them, using the subroutine @code{output_asm_insn}. This | |
638 | receives two arguments: a template-string and a vector of operands. The | |
639 | vector may be @code{operands}, or it may be another array of @code{rtx} | |
640 | that you declare locally and initialize yourself. | |
641 | ||
642 | @findex which_alternative | |
643 | When an insn pattern has multiple alternatives in its constraints, often | |
644 | the appearance of the assembler code is determined mostly by which alternative | |
645 | was matched. When this is so, the C code can test the variable | |
646 | @code{which_alternative}, which is the ordinal number of the alternative | |
647 | that was actually satisfied (0 for the first, 1 for the second alternative, | |
648 | etc.). | |
649 | ||
650 | For example, suppose there are two opcodes for storing zero, @samp{clrreg} | |
651 | for registers and @samp{clrmem} for memory locations. Here is how | |
652 | a pattern could use @code{which_alternative} to choose between them: | |
653 | ||
654 | @smallexample | |
655 | (define_insn "" | |
656 | [(set (match_operand:SI 0 "general_operand" "=r,m") | |
657 | (const_int 0))] | |
658 | "" | |
659 | "* | |
660 | return (which_alternative == 0 | |
661 | ? \"clrreg %0\" : \"clrmem %0\"); | |
662 | ") | |
663 | @end smallexample | |
664 | ||
665 | The example above, where the assembler code to generate was | |
666 | @emph{solely} determined by the alternative, could also have been specified | |
667 | as follows, having the output control string start with a @samp{@@}: | |
668 | ||
669 | @smallexample | |
670 | @group | |
671 | (define_insn "" | |
672 | [(set (match_operand:SI 0 "general_operand" "=r,m") | |
673 | (const_int 0))] | |
674 | "" | |
675 | "@@ | |
676 | clrreg %0 | |
677 | clrmem %0") | |
678 | @end group | |
679 | @end smallexample | |
680 | @end ifset | |
681 | ||
682 | @c Most of this node appears by itself (in a different place) even | |
683 | @c when the INTERNALS flag is clear. Passages that require the full | |
684 | @c manual's context are conditionalized to appear only in the full manual. | |
685 | @ifset INTERNALS | |
686 | @node Constraints | |
687 | @section Operand Constraints | |
688 | @cindex operand constraints | |
689 | @cindex constraints | |
690 | ||
691 | Each @code{match_operand} in an instruction pattern can specify a | |
692 | constraint for the type of operands allowed. | |
693 | @end ifset | |
694 | @ifclear INTERNALS | |
695 | @node Constraints | |
696 | @section Constraints for @code{asm} Operands | |
697 | @cindex operand constraints, @code{asm} | |
698 | @cindex constraints, @code{asm} | |
699 | @cindex @code{asm} constraints | |
700 | ||
701 | Here are specific details on what constraint letters you can use with | |
702 | @code{asm} operands. | |
703 | @end ifclear | |
704 | Constraints can say whether | |
705 | an operand may be in a register, and which kinds of register; whether the | |
706 | operand can be a memory reference, and which kinds of address; whether the | |
707 | operand may be an immediate constant, and which possible values it may | |
708 | have. Constraints can also require two operands to match. | |
709 | ||
710 | @ifset INTERNALS | |
711 | @menu | |
712 | * Simple Constraints:: Basic use of constraints. | |
713 | * Multi-Alternative:: When an insn has two alternative constraint-patterns. | |
714 | * Class Preferences:: Constraints guide which hard register to put things in. | |
715 | * Modifiers:: More precise control over effects of constraints. | |
716 | * Machine Constraints:: Existing constraints for some particular machines. | |
03dda8e3 RK |
717 | @end menu |
718 | @end ifset | |
719 | ||
720 | @ifclear INTERNALS | |
721 | @menu | |
722 | * Simple Constraints:: Basic use of constraints. | |
723 | * Multi-Alternative:: When an insn has two alternative constraint-patterns. | |
724 | * Modifiers:: More precise control over effects of constraints. | |
725 | * Machine Constraints:: Special constraints for some particular machines. | |
726 | @end menu | |
727 | @end ifclear | |
728 | ||
729 | @node Simple Constraints | |
730 | @subsection Simple Constraints | |
731 | @cindex simple constraints | |
732 | ||
733 | The simplest kind of constraint is a string full of letters, each of | |
734 | which describes one kind of operand that is permitted. Here are | |
735 | the letters that are allowed: | |
736 | ||
737 | @table @asis | |
88a56c2e HPN |
738 | @item whitespace |
739 | Whitespace characters are ignored and can be inserted at any position | |
740 | except the first. This enables each alternative for different operands to | |
741 | be visually aligned in the machine description even if they have different | |
742 | number of constraints and modifiers. | |
743 | ||
03dda8e3 RK |
744 | @cindex @samp{m} in constraint |
745 | @cindex memory references in constraints | |
746 | @item @samp{m} | |
747 | A memory operand is allowed, with any kind of address that the machine | |
748 | supports in general. | |
749 | ||
750 | @cindex offsettable address | |
751 | @cindex @samp{o} in constraint | |
752 | @item @samp{o} | |
753 | A memory operand is allowed, but only if the address is | |
754 | @dfn{offsettable}. This means that adding a small integer (actually, | |
755 | the width in bytes of the operand, as determined by its machine mode) | |
756 | may be added to the address and the result is also a valid memory | |
757 | address. | |
758 | ||
759 | @cindex autoincrement/decrement addressing | |
760 | For example, an address which is constant is offsettable; so is an | |
761 | address that is the sum of a register and a constant (as long as a | |
762 | slightly larger constant is also within the range of address-offsets | |
763 | supported by the machine); but an autoincrement or autodecrement | |
764 | address is not offsettable. More complicated indirect/indexed | |
765 | addresses may or may not be offsettable depending on the other | |
766 | addressing modes that the machine supports. | |
767 | ||
768 | Note that in an output operand which can be matched by another | |
769 | operand, the constraint letter @samp{o} is valid only when accompanied | |
770 | by both @samp{<} (if the target machine has predecrement addressing) | |
771 | and @samp{>} (if the target machine has preincrement addressing). | |
772 | ||
773 | @cindex @samp{V} in constraint | |
774 | @item @samp{V} | |
775 | A memory operand that is not offsettable. In other words, anything that | |
776 | would fit the @samp{m} constraint but not the @samp{o} constraint. | |
777 | ||
778 | @cindex @samp{<} in constraint | |
779 | @item @samp{<} | |
780 | A memory operand with autodecrement addressing (either predecrement or | |
781 | postdecrement) is allowed. | |
782 | ||
783 | @cindex @samp{>} in constraint | |
784 | @item @samp{>} | |
785 | A memory operand with autoincrement addressing (either preincrement or | |
786 | postincrement) is allowed. | |
787 | ||
788 | @cindex @samp{r} in constraint | |
789 | @cindex registers in constraints | |
790 | @item @samp{r} | |
791 | A register operand is allowed provided that it is in a general | |
792 | register. | |
793 | ||
03dda8e3 RK |
794 | @cindex constants in constraints |
795 | @cindex @samp{i} in constraint | |
796 | @item @samp{i} | |
797 | An immediate integer operand (one with constant value) is allowed. | |
798 | This includes symbolic constants whose values will be known only at | |
799 | assembly time. | |
800 | ||
801 | @cindex @samp{n} in constraint | |
802 | @item @samp{n} | |
803 | An immediate integer operand with a known numeric value is allowed. | |
804 | Many systems cannot support assembly-time constants for operands less | |
805 | than a word wide. Constraints for these operands should use @samp{n} | |
806 | rather than @samp{i}. | |
807 | ||
808 | @cindex @samp{I} in constraint | |
809 | @item @samp{I}, @samp{J}, @samp{K}, @dots{} @samp{P} | |
810 | Other letters in the range @samp{I} through @samp{P} may be defined in | |
811 | a machine-dependent fashion to permit immediate integer operands with | |
812 | explicit integer values in specified ranges. For example, on the | |
813 | 68000, @samp{I} is defined to stand for the range of values 1 to 8. | |
814 | This is the range permitted as a shift count in the shift | |
815 | instructions. | |
816 | ||
817 | @cindex @samp{E} in constraint | |
818 | @item @samp{E} | |
819 | An immediate floating operand (expression code @code{const_double}) is | |
820 | allowed, but only if the target floating point format is the same as | |
821 | that of the host machine (on which the compiler is running). | |
822 | ||
823 | @cindex @samp{F} in constraint | |
824 | @item @samp{F} | |
825 | An immediate floating operand (expression code @code{const_double}) is | |
826 | allowed. | |
827 | ||
828 | @cindex @samp{G} in constraint | |
829 | @cindex @samp{H} in constraint | |
830 | @item @samp{G}, @samp{H} | |
831 | @samp{G} and @samp{H} may be defined in a machine-dependent fashion to | |
832 | permit immediate floating operands in particular ranges of values. | |
833 | ||
834 | @cindex @samp{s} in constraint | |
835 | @item @samp{s} | |
836 | An immediate integer operand whose value is not an explicit integer is | |
837 | allowed. | |
838 | ||
839 | This might appear strange; if an insn allows a constant operand with a | |
840 | value not known at compile time, it certainly must allow any known | |
841 | value. So why use @samp{s} instead of @samp{i}? Sometimes it allows | |
842 | better code to be generated. | |
843 | ||
844 | For example, on the 68000 in a fullword instruction it is possible to | |
845 | use an immediate operand; but if the immediate value is between -128 | |
846 | and 127, better code results from loading the value into a register and | |
847 | using the register. This is because the load into the register can be | |
848 | done with a @samp{moveq} instruction. We arrange for this to happen | |
849 | by defining the letter @samp{K} to mean ``any integer outside the | |
850 | range -128 to 127'', and then specifying @samp{Ks} in the operand | |
851 | constraints. | |
852 | ||
853 | @cindex @samp{g} in constraint | |
854 | @item @samp{g} | |
855 | Any register, memory or immediate integer operand is allowed, except for | |
856 | registers that are not general registers. | |
857 | ||
858 | @cindex @samp{X} in constraint | |
859 | @item @samp{X} | |
860 | @ifset INTERNALS | |
861 | Any operand whatsoever is allowed, even if it does not satisfy | |
862 | @code{general_operand}. This is normally used in the constraint of | |
863 | a @code{match_scratch} when certain alternatives will not actually | |
864 | require a scratch register. | |
865 | @end ifset | |
866 | @ifclear INTERNALS | |
867 | Any operand whatsoever is allowed. | |
868 | @end ifclear | |
869 | ||
870 | @cindex @samp{0} in constraint | |
871 | @cindex digits in constraint | |
872 | @item @samp{0}, @samp{1}, @samp{2}, @dots{} @samp{9} | |
873 | An operand that matches the specified operand number is allowed. If a | |
874 | digit is used together with letters within the same alternative, the | |
875 | digit should come last. | |
876 | ||
877 | @cindex matching constraint | |
878 | @cindex constraint, matching | |
879 | This is called a @dfn{matching constraint} and what it really means is | |
880 | that the assembler has only a single operand that fills two roles | |
881 | @ifset INTERNALS | |
882 | considered separate in the RTL insn. For example, an add insn has two | |
883 | input operands and one output operand in the RTL, but on most CISC | |
884 | @end ifset | |
885 | @ifclear INTERNALS | |
886 | which @code{asm} distinguishes. For example, an add instruction uses | |
887 | two input operands and an output operand, but on most CISC | |
888 | @end ifclear | |
889 | machines an add instruction really has only two operands, one of them an | |
890 | input-output operand: | |
891 | ||
892 | @smallexample | |
893 | addl #35,r12 | |
894 | @end smallexample | |
895 | ||
896 | Matching constraints are used in these circumstances. | |
897 | More precisely, the two operands that match must include one input-only | |
898 | operand and one output-only operand. Moreover, the digit must be a | |
899 | smaller number than the number of the operand that uses it in the | |
900 | constraint. | |
901 | ||
902 | @ifset INTERNALS | |
903 | For operands to match in a particular case usually means that they | |
904 | are identical-looking RTL expressions. But in a few special cases | |
905 | specific kinds of dissimilarity are allowed. For example, @code{*x} | |
906 | as an input operand will match @code{*x++} as an output operand. | |
907 | For proper results in such cases, the output template should always | |
908 | use the output-operand's number when printing the operand. | |
909 | @end ifset | |
910 | ||
911 | @cindex load address instruction | |
912 | @cindex push address instruction | |
913 | @cindex address constraints | |
914 | @cindex @samp{p} in constraint | |
915 | @item @samp{p} | |
916 | An operand that is a valid memory address is allowed. This is | |
917 | for ``load address'' and ``push address'' instructions. | |
918 | ||
919 | @findex address_operand | |
920 | @samp{p} in the constraint must be accompanied by @code{address_operand} | |
921 | as the predicate in the @code{match_operand}. This predicate interprets | |
922 | the mode specified in the @code{match_operand} as the mode of the memory | |
923 | reference for which the address would be valid. | |
924 | ||
c2cba7a9 | 925 | @cindex other register constraints |
03dda8e3 | 926 | @cindex extensible constraints |
c2cba7a9 RH |
927 | @item @var{other letters} |
928 | Other letters can be defined in machine-dependent fashion to stand for | |
929 | particular classes of registers or other arbitrary operand types. | |
930 | @samp{d}, @samp{a} and @samp{f} are defined on the 68000/68020 to stand | |
931 | for data, address and floating point registers. | |
03dda8e3 | 932 | |
c2cba7a9 RH |
933 | @ifset INTERNALS |
934 | The machine description macro @code{REG_CLASS_FROM_LETTER} has first | |
935 | cut at the otherwise unused letters. If it evaluates to @code{NO_REGS}, | |
936 | then @code{EXTRA_CONSTRAINT} is evaluated. | |
03dda8e3 | 937 | |
c2cba7a9 RH |
938 | A typical use for @code{EXTRA_CONSTRANT} would be to distinguish certain |
939 | types of memory references that affect other insn operands. | |
03dda8e3 RK |
940 | @end ifset |
941 | @end table | |
942 | ||
943 | @ifset INTERNALS | |
944 | In order to have valid assembler code, each operand must satisfy | |
945 | its constraint. But a failure to do so does not prevent the pattern | |
946 | from applying to an insn. Instead, it directs the compiler to modify | |
947 | the code so that the constraint will be satisfied. Usually this is | |
948 | done by copying an operand into a register. | |
949 | ||
950 | Contrast, therefore, the two instruction patterns that follow: | |
951 | ||
952 | @smallexample | |
953 | (define_insn "" | |
954 | [(set (match_operand:SI 0 "general_operand" "=r") | |
955 | (plus:SI (match_dup 0) | |
956 | (match_operand:SI 1 "general_operand" "r")))] | |
957 | "" | |
958 | "@dots{}") | |
959 | @end smallexample | |
960 | ||
961 | @noindent | |
962 | which has two operands, one of which must appear in two places, and | |
963 | ||
964 | @smallexample | |
965 | (define_insn "" | |
966 | [(set (match_operand:SI 0 "general_operand" "=r") | |
967 | (plus:SI (match_operand:SI 1 "general_operand" "0") | |
968 | (match_operand:SI 2 "general_operand" "r")))] | |
969 | "" | |
970 | "@dots{}") | |
971 | @end smallexample | |
972 | ||
973 | @noindent | |
974 | which has three operands, two of which are required by a constraint to be | |
975 | identical. If we are considering an insn of the form | |
976 | ||
977 | @smallexample | |
978 | (insn @var{n} @var{prev} @var{next} | |
979 | (set (reg:SI 3) | |
980 | (plus:SI (reg:SI 6) (reg:SI 109))) | |
981 | @dots{}) | |
982 | @end smallexample | |
983 | ||
984 | @noindent | |
985 | the first pattern would not apply at all, because this insn does not | |
986 | contain two identical subexpressions in the right place. The pattern would | |
987 | say, ``That does not look like an add instruction; try other patterns.'' | |
988 | The second pattern would say, ``Yes, that's an add instruction, but there | |
989 | is something wrong with it.'' It would direct the reload pass of the | |
990 | compiler to generate additional insns to make the constraint true. The | |
991 | results might look like this: | |
992 | ||
993 | @smallexample | |
994 | (insn @var{n2} @var{prev} @var{n} | |
995 | (set (reg:SI 3) (reg:SI 6)) | |
996 | @dots{}) | |
997 | ||
998 | (insn @var{n} @var{n2} @var{next} | |
999 | (set (reg:SI 3) | |
1000 | (plus:SI (reg:SI 3) (reg:SI 109))) | |
1001 | @dots{}) | |
1002 | @end smallexample | |
1003 | ||
1004 | It is up to you to make sure that each operand, in each pattern, has | |
1005 | constraints that can handle any RTL expression that could be present for | |
1006 | that operand. (When multiple alternatives are in use, each pattern must, | |
1007 | for each possible combination of operand expressions, have at least one | |
1008 | alternative which can handle that combination of operands.) The | |
1009 | constraints don't need to @emph{allow} any possible operand---when this is | |
1010 | the case, they do not constrain---but they must at least point the way to | |
1011 | reloading any possible operand so that it will fit. | |
1012 | ||
1013 | @itemize @bullet | |
1014 | @item | |
1015 | If the constraint accepts whatever operands the predicate permits, | |
1016 | there is no problem: reloading is never necessary for this operand. | |
1017 | ||
1018 | For example, an operand whose constraints permit everything except | |
1019 | registers is safe provided its predicate rejects registers. | |
1020 | ||
1021 | An operand whose predicate accepts only constant values is safe | |
1022 | provided its constraints include the letter @samp{i}. If any possible | |
1023 | constant value is accepted, then nothing less than @samp{i} will do; | |
1024 | if the predicate is more selective, then the constraints may also be | |
1025 | more selective. | |
1026 | ||
1027 | @item | |
1028 | Any operand expression can be reloaded by copying it into a register. | |
1029 | So if an operand's constraints allow some kind of register, it is | |
1030 | certain to be safe. It need not permit all classes of registers; the | |
1031 | compiler knows how to copy a register into another register of the | |
1032 | proper class in order to make an instruction valid. | |
1033 | ||
1034 | @cindex nonoffsettable memory reference | |
1035 | @cindex memory reference, nonoffsettable | |
1036 | @item | |
1037 | A nonoffsettable memory reference can be reloaded by copying the | |
1038 | address into a register. So if the constraint uses the letter | |
1039 | @samp{o}, all memory references are taken care of. | |
1040 | ||
1041 | @item | |
1042 | A constant operand can be reloaded by allocating space in memory to | |
1043 | hold it as preinitialized data. Then the memory reference can be used | |
1044 | in place of the constant. So if the constraint uses the letters | |
1045 | @samp{o} or @samp{m}, constant operands are not a problem. | |
1046 | ||
1047 | @item | |
1048 | If the constraint permits a constant and a pseudo register used in an insn | |
1049 | was not allocated to a hard register and is equivalent to a constant, | |
1050 | the register will be replaced with the constant. If the predicate does | |
1051 | not permit a constant and the insn is re-recognized for some reason, the | |
1052 | compiler will crash. Thus the predicate must always recognize any | |
1053 | objects allowed by the constraint. | |
1054 | @end itemize | |
1055 | ||
1056 | If the operand's predicate can recognize registers, but the constraint does | |
1057 | not permit them, it can make the compiler crash. When this operand happens | |
1058 | to be a register, the reload pass will be stymied, because it does not know | |
1059 | how to copy a register temporarily into memory. | |
1060 | ||
1061 | If the predicate accepts a unary operator, the constraint applies to the | |
1062 | operand. For example, the MIPS processor at ISA level 3 supports an | |
1063 | instruction which adds two registers in @code{SImode} to produce a | |
1064 | @code{DImode} result, but only if the registers are correctly sign | |
1065 | extended. This predicate for the input operands accepts a | |
1066 | @code{sign_extend} of an @code{SImode} register. Write the constraint | |
1067 | to indicate the type of register that is required for the operand of the | |
1068 | @code{sign_extend}. | |
1069 | @end ifset | |
1070 | ||
1071 | @node Multi-Alternative | |
1072 | @subsection Multiple Alternative Constraints | |
1073 | @cindex multiple alternative constraints | |
1074 | ||
1075 | Sometimes a single instruction has multiple alternative sets of possible | |
1076 | operands. For example, on the 68000, a logical-or instruction can combine | |
1077 | register or an immediate value into memory, or it can combine any kind of | |
1078 | operand into a register; but it cannot combine one memory location into | |
1079 | another. | |
1080 | ||
1081 | These constraints are represented as multiple alternatives. An alternative | |
1082 | can be described by a series of letters for each operand. The overall | |
1083 | constraint for an operand is made from the letters for this operand | |
1084 | from the first alternative, a comma, the letters for this operand from | |
1085 | the second alternative, a comma, and so on until the last alternative. | |
1086 | @ifset INTERNALS | |
1087 | Here is how it is done for fullword logical-or on the 68000: | |
1088 | ||
1089 | @smallexample | |
1090 | (define_insn "iorsi3" | |
1091 | [(set (match_operand:SI 0 "general_operand" "=m,d") | |
1092 | (ior:SI (match_operand:SI 1 "general_operand" "%0,0") | |
1093 | (match_operand:SI 2 "general_operand" "dKs,dmKs")))] | |
1094 | @dots{}) | |
1095 | @end smallexample | |
1096 | ||
1097 | The first alternative has @samp{m} (memory) for operand 0, @samp{0} for | |
1098 | operand 1 (meaning it must match operand 0), and @samp{dKs} for operand | |
1099 | 2. The second alternative has @samp{d} (data register) for operand 0, | |
1100 | @samp{0} for operand 1, and @samp{dmKs} for operand 2. The @samp{=} and | |
1101 | @samp{%} in the constraints apply to all the alternatives; their | |
1102 | meaning is explained in the next section (@pxref{Class Preferences}). | |
1103 | @end ifset | |
1104 | ||
1105 | @c FIXME Is this ? and ! stuff of use in asm()? If not, hide unless INTERNAL | |
1106 | If all the operands fit any one alternative, the instruction is valid. | |
1107 | Otherwise, for each alternative, the compiler counts how many instructions | |
1108 | must be added to copy the operands so that that alternative applies. | |
1109 | The alternative requiring the least copying is chosen. If two alternatives | |
1110 | need the same amount of copying, the one that comes first is chosen. | |
1111 | These choices can be altered with the @samp{?} and @samp{!} characters: | |
1112 | ||
1113 | @table @code | |
1114 | @cindex @samp{?} in constraint | |
1115 | @cindex question mark | |
1116 | @item ? | |
1117 | Disparage slightly the alternative that the @samp{?} appears in, | |
1118 | as a choice when no alternative applies exactly. The compiler regards | |
1119 | this alternative as one unit more costly for each @samp{?} that appears | |
1120 | in it. | |
1121 | ||
1122 | @cindex @samp{!} in constraint | |
1123 | @cindex exclamation point | |
1124 | @item ! | |
1125 | Disparage severely the alternative that the @samp{!} appears in. | |
1126 | This alternative can still be used if it fits without reloading, | |
1127 | but if reloading is needed, some other alternative will be used. | |
1128 | @end table | |
1129 | ||
1130 | @ifset INTERNALS | |
1131 | When an insn pattern has multiple alternatives in its constraints, often | |
1132 | the appearance of the assembler code is determined mostly by which | |
1133 | alternative was matched. When this is so, the C code for writing the | |
1134 | assembler code can use the variable @code{which_alternative}, which is | |
1135 | the ordinal number of the alternative that was actually satisfied (0 for | |
1136 | the first, 1 for the second alternative, etc.). @xref{Output Statement}. | |
1137 | @end ifset | |
1138 | ||
1139 | @ifset INTERNALS | |
1140 | @node Class Preferences | |
1141 | @subsection Register Class Preferences | |
1142 | @cindex class preference constraints | |
1143 | @cindex register class preference constraints | |
1144 | ||
1145 | @cindex voting between constraint alternatives | |
1146 | The operand constraints have another function: they enable the compiler | |
1147 | to decide which kind of hardware register a pseudo register is best | |
1148 | allocated to. The compiler examines the constraints that apply to the | |
1149 | insns that use the pseudo register, looking for the machine-dependent | |
1150 | letters such as @samp{d} and @samp{a} that specify classes of registers. | |
1151 | The pseudo register is put in whichever class gets the most ``votes''. | |
1152 | The constraint letters @samp{g} and @samp{r} also vote: they vote in | |
1153 | favor of a general register. The machine description says which registers | |
1154 | are considered general. | |
1155 | ||
1156 | Of course, on some machines all registers are equivalent, and no register | |
1157 | classes are defined. Then none of this complexity is relevant. | |
1158 | @end ifset | |
1159 | ||
1160 | @node Modifiers | |
1161 | @subsection Constraint Modifier Characters | |
1162 | @cindex modifiers in constraints | |
1163 | @cindex constraint modifier characters | |
1164 | ||
1165 | @c prevent bad page break with this line | |
1166 | Here are constraint modifier characters. | |
1167 | ||
1168 | @table @samp | |
1169 | @cindex @samp{=} in constraint | |
1170 | @item = | |
1171 | Means that this operand is write-only for this instruction: the previous | |
1172 | value is discarded and replaced by output data. | |
1173 | ||
1174 | @cindex @samp{+} in constraint | |
1175 | @item + | |
1176 | Means that this operand is both read and written by the instruction. | |
1177 | ||
1178 | When the compiler fixes up the operands to satisfy the constraints, | |
1179 | it needs to know which operands are inputs to the instruction and | |
1180 | which are outputs from it. @samp{=} identifies an output; @samp{+} | |
1181 | identifies an operand that is both input and output; all other operands | |
1182 | are assumed to be input only. | |
1183 | ||
c5c76735 JL |
1184 | If you specify @samp{=} or @samp{+} in a constraint, you put it in the |
1185 | first character of the constraint string. | |
1186 | ||
03dda8e3 RK |
1187 | @cindex @samp{&} in constraint |
1188 | @cindex earlyclobber operand | |
1189 | @item & | |
1190 | Means (in a particular alternative) that this operand is an | |
1191 | @dfn{earlyclobber} operand, which is modified before the instruction is | |
1192 | finished using the input operands. Therefore, this operand may not lie | |
1193 | in a register that is used as an input operand or as part of any memory | |
1194 | address. | |
1195 | ||
1196 | @samp{&} applies only to the alternative in which it is written. In | |
1197 | constraints with multiple alternatives, sometimes one alternative | |
1198 | requires @samp{&} while others do not. See, for example, the | |
1199 | @samp{movdf} insn of the 68000. | |
1200 | ||
ebb48a4d | 1201 | An input operand can be tied to an earlyclobber operand if its only |
03dda8e3 RK |
1202 | use as an input occurs before the early result is written. Adding |
1203 | alternatives of this form often allows GCC to produce better code | |
ebb48a4d | 1204 | when only some of the inputs can be affected by the earlyclobber. |
03dda8e3 RK |
1205 | See, for example, the @samp{mulsi3} insn of the ARM. |
1206 | ||
1207 | @samp{&} does not obviate the need to write @samp{=}. | |
1208 | ||
1209 | @cindex @samp{%} in constraint | |
1210 | @item % | |
1211 | Declares the instruction to be commutative for this operand and the | |
1212 | following operand. This means that the compiler may interchange the | |
1213 | two operands if that is the cheapest way to make all operands fit the | |
1214 | constraints. | |
1215 | @ifset INTERNALS | |
1216 | This is often used in patterns for addition instructions | |
1217 | that really have only two operands: the result must go in one of the | |
1218 | arguments. Here for example, is how the 68000 halfword-add | |
1219 | instruction is defined: | |
1220 | ||
1221 | @smallexample | |
1222 | (define_insn "addhi3" | |
1223 | [(set (match_operand:HI 0 "general_operand" "=m,r") | |
1224 | (plus:HI (match_operand:HI 1 "general_operand" "%0,0") | |
1225 | (match_operand:HI 2 "general_operand" "di,g")))] | |
1226 | @dots{}) | |
1227 | @end smallexample | |
1228 | @end ifset | |
1229 | ||
1230 | @cindex @samp{#} in constraint | |
1231 | @item # | |
1232 | Says that all following characters, up to the next comma, are to be | |
1233 | ignored as a constraint. They are significant only for choosing | |
1234 | register preferences. | |
1235 | ||
1236 | @ifset INTERNALS | |
1237 | @cindex @samp{*} in constraint | |
1238 | @item * | |
1239 | Says that the following character should be ignored when choosing | |
1240 | register preferences. @samp{*} has no effect on the meaning of the | |
1241 | constraint as a constraint, and no effect on reloading. | |
1242 | ||
1243 | Here is an example: the 68000 has an instruction to sign-extend a | |
1244 | halfword in a data register, and can also sign-extend a value by | |
1245 | copying it into an address register. While either kind of register is | |
1246 | acceptable, the constraints on an address-register destination are | |
1247 | less strict, so it is best if register allocation makes an address | |
1248 | register its goal. Therefore, @samp{*} is used so that the @samp{d} | |
1249 | constraint letter (for data register) is ignored when computing | |
1250 | register preferences. | |
1251 | ||
1252 | @smallexample | |
1253 | (define_insn "extendhisi2" | |
1254 | [(set (match_operand:SI 0 "general_operand" "=*d,a") | |
1255 | (sign_extend:SI | |
1256 | (match_operand:HI 1 "general_operand" "0,g")))] | |
1257 | @dots{}) | |
1258 | @end smallexample | |
1259 | @end ifset | |
1260 | @end table | |
1261 | ||
1262 | @node Machine Constraints | |
1263 | @subsection Constraints for Particular Machines | |
1264 | @cindex machine specific constraints | |
1265 | @cindex constraints, machine specific | |
1266 | ||
1267 | Whenever possible, you should use the general-purpose constraint letters | |
1268 | in @code{asm} arguments, since they will convey meaning more readily to | |
1269 | people reading your code. Failing that, use the constraint letters | |
1270 | that usually have very similar meanings across architectures. The most | |
1271 | commonly used constraints are @samp{m} and @samp{r} (for memory and | |
1272 | general-purpose registers respectively; @pxref{Simple Constraints}), and | |
1273 | @samp{I}, usually the letter indicating the most common | |
1274 | immediate-constant format. | |
1275 | ||
1276 | For each machine architecture, the @file{config/@var{machine}.h} file | |
1277 | defines additional constraints. These constraints are used by the | |
1278 | compiler itself for instruction generation, as well as for @code{asm} | |
1279 | statements; therefore, some of the constraints are not particularly | |
1280 | interesting for @code{asm}. The constraints are defined through these | |
1281 | macros: | |
1282 | ||
1283 | @table @code | |
1284 | @item REG_CLASS_FROM_LETTER | |
1285 | Register class constraints (usually lower case). | |
1286 | ||
1287 | @item CONST_OK_FOR_LETTER_P | |
1288 | Immediate constant constraints, for non-floating point constants of | |
1289 | word size or smaller precision (usually upper case). | |
1290 | ||
1291 | @item CONST_DOUBLE_OK_FOR_LETTER_P | |
1292 | Immediate constant constraints, for all floating point constants and for | |
1293 | constants of greater than word size precision (usually upper case). | |
1294 | ||
1295 | @item EXTRA_CONSTRAINT | |
1296 | Special cases of registers or memory. This macro is not required, and | |
1297 | is only defined for some machines. | |
1298 | @end table | |
1299 | ||
1300 | Inspecting these macro definitions in the compiler source for your | |
1301 | machine is the best way to be certain you have the right constraints. | |
1302 | However, here is a summary of the machine-dependent constraints | |
1303 | available on some particular machines. | |
1304 | ||
1305 | @table @emph | |
1306 | @item ARM family---@file{arm.h} | |
1307 | @table @code | |
1308 | @item f | |
1309 | Floating-point register | |
1310 | ||
1311 | @item F | |
1312 | One of the floating-point constants 0.0, 0.5, 1.0, 2.0, 3.0, 4.0, 5.0 | |
1313 | or 10.0 | |
1314 | ||
1315 | @item G | |
1316 | Floating-point constant that would satisfy the constraint @samp{F} if it | |
1317 | were negated | |
1318 | ||
1319 | @item I | |
1320 | Integer that is valid as an immediate operand in a data processing | |
1321 | instruction. That is, an integer in the range 0 to 255 rotated by a | |
1322 | multiple of 2 | |
1323 | ||
1324 | @item J | |
1325 | Integer in the range -4095 to 4095 | |
1326 | ||
1327 | @item K | |
1328 | Integer that satisfies constraint @samp{I} when inverted (ones complement) | |
1329 | ||
1330 | @item L | |
1331 | Integer that satisfies constraint @samp{I} when negated (twos complement) | |
1332 | ||
1333 | @item M | |
1334 | Integer in the range 0 to 32 | |
1335 | ||
1336 | @item Q | |
1337 | A memory reference where the exact address is in a single register | |
1338 | (`@samp{m}' is preferable for @code{asm} statements) | |
1339 | ||
1340 | @item R | |
1341 | An item in the constant pool | |
1342 | ||
1343 | @item S | |
1344 | A symbol in the text segment of the current file | |
1345 | @end table | |
1346 | ||
1347 | @item AMD 29000 family---@file{a29k.h} | |
1348 | @table @code | |
1349 | @item l | |
1350 | Local register 0 | |
1351 | ||
1352 | @item b | |
1353 | Byte Pointer (@samp{BP}) register | |
1354 | ||
1355 | @item q | |
1356 | @samp{Q} register | |
1357 | ||
1358 | @item h | |
1359 | Special purpose register | |
1360 | ||
1361 | @item A | |
1362 | First accumulator register | |
1363 | ||
1364 | @item a | |
1365 | Other accumulator register | |
1366 | ||
1367 | @item f | |
1368 | Floating point register | |
1369 | ||
1370 | @item I | |
1371 | Constant greater than 0, less than 0x100 | |
1372 | ||
1373 | @item J | |
1374 | Constant greater than 0, less than 0x10000 | |
1375 | ||
1376 | @item K | |
1377 | Constant whose high 24 bits are on (1) | |
1378 | ||
1379 | @item L | |
1e5f973d | 1380 | 16-bit constant whose high 8 bits are on (1) |
03dda8e3 RK |
1381 | |
1382 | @item M | |
1e5f973d | 1383 | 32-bit constant whose high 16 bits are on (1) |
03dda8e3 RK |
1384 | |
1385 | @item N | |
1e5f973d | 1386 | 32-bit negative constant that fits in 8 bits |
03dda8e3 RK |
1387 | |
1388 | @item O | |
1e5f973d | 1389 | The constant 0x80000000 or, on the 29050, any 32-bit constant |
03dda8e3 RK |
1390 | whose low 16 bits are 0. |
1391 | ||
1392 | @item P | |
1e5f973d | 1393 | 16-bit negative constant that fits in 8 bits |
03dda8e3 RK |
1394 | |
1395 | @item G | |
1396 | @itemx H | |
1397 | A floating point constant (in @code{asm} statements, use the machine | |
1398 | independent @samp{E} or @samp{F} instead) | |
1399 | @end table | |
1400 | ||
052a4b28 DC |
1401 | @item AVR family---@file{avr.h} |
1402 | @table @code | |
1403 | @item l | |
1404 | Registers from r0 to r15 | |
1405 | ||
1406 | @item a | |
1407 | Registers from r16 to r23 | |
1408 | ||
1409 | @item d | |
1410 | Registers from r16 to r31 | |
1411 | ||
1412 | @item w | |
3a69a7d5 | 1413 | Registers from r24 to r31. These registers can be used in @samp{adiw} command |
052a4b28 DC |
1414 | |
1415 | @item e | |
1416 | Pointer register (r26 - r31) | |
1417 | ||
1418 | @item b | |
1419 | Base pointer register (r28 - r31) | |
1420 | ||
3a69a7d5 MM |
1421 | @item q |
1422 | Stack pointer register (SPH:SPL) | |
1423 | ||
052a4b28 DC |
1424 | @item t |
1425 | Temporary register r0 | |
1426 | ||
1427 | @item x | |
1428 | Register pair X (r27:r26) | |
1429 | ||
1430 | @item y | |
1431 | Register pair Y (r29:r28) | |
1432 | ||
1433 | @item z | |
1434 | Register pair Z (r31:r30) | |
1435 | ||
1436 | @item I | |
1437 | Constant greater than -1, less than 64 | |
1438 | ||
1439 | @item J | |
1440 | Constant greater than -64, less than 1 | |
1441 | ||
1442 | @item K | |
1443 | Constant integer 2 | |
1444 | ||
1445 | @item L | |
1446 | Constant integer 0 | |
1447 | ||
1448 | @item M | |
1449 | Constant that fits in 8 bits | |
1450 | ||
1451 | @item N | |
1452 | Constant integer -1 | |
1453 | ||
1454 | @item O | |
3a69a7d5 | 1455 | Constant integer 8, 16, or 24 |
052a4b28 DC |
1456 | |
1457 | @item P | |
1458 | Constant integer 1 | |
1459 | ||
1460 | @item G | |
1461 | A floating point constant 0.0 | |
1462 | @end table | |
1463 | ||
03dda8e3 RK |
1464 | @item IBM RS6000---@file{rs6000.h} |
1465 | @table @code | |
1466 | @item b | |
1467 | Address base register | |
1468 | ||
1469 | @item f | |
1470 | Floating point register | |
1471 | ||
1472 | @item h | |
1473 | @samp{MQ}, @samp{CTR}, or @samp{LINK} register | |
1474 | ||
1475 | @item q | |
1476 | @samp{MQ} register | |
1477 | ||
1478 | @item c | |
1479 | @samp{CTR} register | |
1480 | ||
1481 | @item l | |
1482 | @samp{LINK} register | |
1483 | ||
1484 | @item x | |
1485 | @samp{CR} register (condition register) number 0 | |
1486 | ||
1487 | @item y | |
1488 | @samp{CR} register (condition register) | |
1489 | ||
8f685459 DE |
1490 | @item z |
1491 | @samp{FPMEM} stack memory for FPR-GPR transfers | |
1492 | ||
03dda8e3 | 1493 | @item I |
1e5f973d | 1494 | Signed 16-bit constant |
03dda8e3 RK |
1495 | |
1496 | @item J | |
ebb48a4d | 1497 | Unsigned 16-bit constant shifted left 16 bits (use @samp{L} instead for |
5f59ecb7 | 1498 | @code{SImode} constants) |
03dda8e3 RK |
1499 | |
1500 | @item K | |
1e5f973d | 1501 | Unsigned 16-bit constant |
03dda8e3 RK |
1502 | |
1503 | @item L | |
1e5f973d | 1504 | Signed 16-bit constant shifted left 16 bits |
03dda8e3 RK |
1505 | |
1506 | @item M | |
1507 | Constant larger than 31 | |
1508 | ||
1509 | @item N | |
1510 | Exact power of 2 | |
1511 | ||
1512 | @item O | |
1513 | Zero | |
1514 | ||
1515 | @item P | |
1e5f973d | 1516 | Constant whose negation is a signed 16-bit constant |
03dda8e3 RK |
1517 | |
1518 | @item G | |
1519 | Floating point constant that can be loaded into a register with one | |
1520 | instruction per word | |
1521 | ||
1522 | @item Q | |
1523 | Memory operand that is an offset from a register (@samp{m} is preferable | |
1524 | for @code{asm} statements) | |
1525 | ||
1526 | @item R | |
1527 | AIX TOC entry | |
1528 | ||
1529 | @item S | |
8f685459 | 1530 | Constant suitable as a 64-bit mask operand |
03dda8e3 | 1531 | |
5f59ecb7 DE |
1532 | @item T |
1533 | Constant suitable as a 32-bit mask operand | |
1534 | ||
03dda8e3 RK |
1535 | @item U |
1536 | System V Release 4 small data area reference | |
1537 | @end table | |
1538 | ||
1539 | @item Intel 386---@file{i386.h} | |
1540 | @table @code | |
1541 | @item q | |
0c56474e | 1542 | @samp{a}, @code{b}, @code{c}, or @code{d} register for the i386. |
1e5f973d | 1543 | For x86-64 it is equivalent to @samp{r} class. (for 8-bit instructions that |
0c56474e JH |
1544 | do not use upper halves) |
1545 | ||
1546 | @item Q | |
1e5f973d | 1547 | @samp{a}, @code{b}, @code{c}, or @code{d} register. (for 8-bit instructions, |
0c56474e JH |
1548 | that do use upper halves) |
1549 | ||
1550 | @item R | |
1551 | Legacy register --- equivalent to @code{r} class in i386 mode. | |
1e5f973d | 1552 | (for non-8-bit registers used together with 8-bit upper halves in a single |
0c56474e | 1553 | instruction) |
03dda8e3 RK |
1554 | |
1555 | @item A | |
994682b9 AJ |
1556 | Specifies the @samp{a} or @samp{d} registers. This is primarily useful |
1557 | for 64-bit integer values (when in 32-bit mode) intended to be returned | |
1558 | with the @samp{d} register holding the most significant bits and the | |
1559 | @samp{a} register holding the least significant bits. | |
03dda8e3 RK |
1560 | |
1561 | @item f | |
1562 | Floating point register | |
1563 | ||
1564 | @item t | |
1565 | First (top of stack) floating point register | |
1566 | ||
1567 | @item u | |
1568 | Second floating point register | |
1569 | ||
1570 | @item a | |
1571 | @samp{a} register | |
1572 | ||
1573 | @item b | |
1574 | @samp{b} register | |
1575 | ||
1576 | @item c | |
1577 | @samp{c} register | |
1578 | ||
1579 | @item d | |
1580 | @samp{d} register | |
1581 | ||
1582 | @item D | |
1583 | @samp{di} register | |
1584 | ||
1585 | @item S | |
1586 | @samp{si} register | |
1587 | ||
994682b9 AJ |
1588 | @item x |
1589 | @samp{xmm} SSE register | |
1590 | ||
1591 | @item y | |
1592 | MMX register | |
1593 | ||
03dda8e3 | 1594 | @item I |
1e5f973d | 1595 | Constant in range 0 to 31 (for 32-bit shifts) |
03dda8e3 RK |
1596 | |
1597 | @item J | |
1e5f973d | 1598 | Constant in range 0 to 63 (for 64-bit shifts) |
03dda8e3 RK |
1599 | |
1600 | @item K | |
1601 | @samp{0xff} | |
1602 | ||
1603 | @item L | |
1604 | @samp{0xffff} | |
1605 | ||
1606 | @item M | |
1607 | 0, 1, 2, or 3 (shifts for @code{lea} instruction) | |
1608 | ||
1609 | @item N | |
1610 | Constant in range 0 to 255 (for @code{out} instruction) | |
1611 | ||
0c56474e JH |
1612 | @item Z |
1613 | Constant in range 0 to 0xffffffff or symbolic reference known to fit specified range. | |
1e5f973d | 1614 | (for using immediates in zero extending 32-bit to 64-bit x86-64 instructions) |
0c56474e JH |
1615 | |
1616 | @item e | |
1617 | Constant in range -2147483648 to 2147483647 or symbolic reference known to fit specified range. | |
1e5f973d | 1618 | (for using immediates in 64-bit x86-64 instructions) |
0c56474e | 1619 | |
03dda8e3 RK |
1620 | @item G |
1621 | Standard 80387 floating point constant | |
1622 | @end table | |
1623 | ||
1624 | @item Intel 960---@file{i960.h} | |
1625 | @table @code | |
1626 | @item f | |
1627 | Floating point register (@code{fp0} to @code{fp3}) | |
1628 | ||
1629 | @item l | |
1630 | Local register (@code{r0} to @code{r15}) | |
1631 | ||
1632 | @item b | |
1633 | Global register (@code{g0} to @code{g15}) | |
1634 | ||
1635 | @item d | |
1636 | Any local or global register | |
1637 | ||
1638 | @item I | |
1639 | Integers from 0 to 31 | |
1640 | ||
1641 | @item J | |
1642 | 0 | |
1643 | ||
1644 | @item K | |
1645 | Integers from -31 to 0 | |
1646 | ||
1647 | @item G | |
1648 | Floating point 0 | |
1649 | ||
1650 | @item H | |
1651 | Floating point 1 | |
1652 | @end table | |
1653 | ||
1654 | @item MIPS---@file{mips.h} | |
1655 | @table @code | |
1656 | @item d | |
1657 | General-purpose integer register | |
1658 | ||
1659 | @item f | |
1660 | Floating-point register (if available) | |
1661 | ||
1662 | @item h | |
1663 | @samp{Hi} register | |
1664 | ||
1665 | @item l | |
1666 | @samp{Lo} register | |
1667 | ||
1668 | @item x | |
1669 | @samp{Hi} or @samp{Lo} register | |
1670 | ||
1671 | @item y | |
1672 | General-purpose integer register | |
1673 | ||
1674 | @item z | |
1675 | Floating-point status register | |
1676 | ||
1677 | @item I | |
1e5f973d | 1678 | Signed 16-bit constant (for arithmetic instructions) |
03dda8e3 RK |
1679 | |
1680 | @item J | |
1681 | Zero | |
1682 | ||
1683 | @item K | |
1684 | Zero-extended 16-bit constant (for logic instructions) | |
1685 | ||
1686 | @item L | |
1687 | Constant with low 16 bits zero (can be loaded with @code{lui}) | |
1688 | ||
1689 | @item M | |
1e5f973d | 1690 | 32-bit constant which requires two instructions to load (a constant |
03dda8e3 RK |
1691 | which is not @samp{I}, @samp{K}, or @samp{L}) |
1692 | ||
1693 | @item N | |
1e5f973d | 1694 | Negative 16-bit constant |
03dda8e3 RK |
1695 | |
1696 | @item O | |
1697 | Exact power of two | |
1698 | ||
1699 | @item P | |
1e5f973d | 1700 | Positive 16-bit constant |
03dda8e3 RK |
1701 | |
1702 | @item G | |
1703 | Floating point zero | |
1704 | ||
1705 | @item Q | |
1706 | Memory reference that can be loaded with more than one instruction | |
1707 | (@samp{m} is preferable for @code{asm} statements) | |
1708 | ||
1709 | @item R | |
1710 | Memory reference that can be loaded with one instruction | |
1711 | (@samp{m} is preferable for @code{asm} statements) | |
1712 | ||
1713 | @item S | |
1714 | Memory reference in external OSF/rose PIC format | |
1715 | (@samp{m} is preferable for @code{asm} statements) | |
1716 | @end table | |
1717 | ||
1718 | @item Motorola 680x0---@file{m68k.h} | |
1719 | @table @code | |
1720 | @item a | |
1721 | Address register | |
1722 | ||
1723 | @item d | |
1724 | Data register | |
1725 | ||
1726 | @item f | |
1727 | 68881 floating-point register, if available | |
1728 | ||
1729 | @item x | |
1730 | Sun FPA (floating-point) register, if available | |
1731 | ||
1732 | @item y | |
1733 | First 16 Sun FPA registers, if available | |
1734 | ||
1735 | @item I | |
1736 | Integer in the range 1 to 8 | |
1737 | ||
1738 | @item J | |
1e5f973d | 1739 | 16-bit signed number |
03dda8e3 RK |
1740 | |
1741 | @item K | |
1742 | Signed number whose magnitude is greater than 0x80 | |
1743 | ||
1744 | @item L | |
1745 | Integer in the range -8 to -1 | |
1746 | ||
1747 | @item M | |
1748 | Signed number whose magnitude is greater than 0x100 | |
1749 | ||
1750 | @item G | |
1751 | Floating point constant that is not a 68881 constant | |
1752 | ||
1753 | @item H | |
1754 | Floating point constant that can be used by Sun FPA | |
1755 | @end table | |
1756 | ||
2856c3e3 SC |
1757 | @item Motorola 68HC11 & 68HC12 families---@file{m68hc11.h} |
1758 | @table @code | |
1759 | @item a | |
1760 | Register 'a' | |
1761 | ||
1762 | @item b | |
1763 | Register 'b' | |
1764 | ||
1765 | @item d | |
1766 | Register 'd' | |
1767 | ||
1768 | @item q | |
1769 | An 8-bit register | |
1770 | ||
1771 | @item t | |
1772 | Temporary soft register _.tmp | |
1773 | ||
1774 | @item u | |
1775 | A soft register _.d1 to _.d31 | |
1776 | ||
1777 | @item w | |
1778 | Stack pointer register | |
1779 | ||
1780 | @item x | |
1781 | Register 'x' | |
1782 | ||
1783 | @item y | |
1784 | Register 'y' | |
1785 | ||
1786 | @item z | |
1787 | Pseudo register 'z' (replaced by 'x' or 'y' at the end) | |
1788 | ||
1789 | @item A | |
1790 | An address register: x, y or z | |
1791 | ||
1792 | @item B | |
1793 | An address register: x or y | |
1794 | ||
1795 | @item D | |
1796 | Register pair (x:d) to form a 32-bit value | |
1797 | ||
1798 | @item L | |
1799 | Constants in the range -65536 to 65535 | |
1800 | ||
1801 | @item M | |
1802 | Constants whose 16-bit low part is zero | |
1803 | ||
1804 | @item N | |
1805 | Constant integer 1 or -1 | |
1806 | ||
1807 | @item O | |
1808 | Constant integer 16 | |
1809 | ||
1810 | @item P | |
1811 | Constants in the range -8 to 2 | |
1812 | ||
1813 | @end table | |
1814 | ||
03dda8e3 RK |
1815 | @need 1000 |
1816 | @item SPARC---@file{sparc.h} | |
1817 | @table @code | |
1818 | @item f | |
1e5f973d | 1819 | Floating-point register that can hold 32- or 64-bit values. |
03dda8e3 RK |
1820 | |
1821 | @item e | |
1e5f973d | 1822 | Floating-point register that can hold 64- or 128-bit values. |
03dda8e3 RK |
1823 | |
1824 | @item I | |
1e5f973d | 1825 | Signed 13-bit constant |
03dda8e3 RK |
1826 | |
1827 | @item J | |
1828 | Zero | |
1829 | ||
1830 | @item K | |
1e5f973d | 1831 | 32-bit constant with the low 12 bits clear (a constant that can be |
03dda8e3 RK |
1832 | loaded with the @code{sethi} instruction) |
1833 | ||
1834 | @item G | |
1835 | Floating-point zero | |
1836 | ||
1837 | @item H | |
1e5f973d | 1838 | Signed 13-bit constant, sign-extended to 32 or 64 bits |
03dda8e3 RK |
1839 | |
1840 | @item Q | |
62190128 DM |
1841 | Floating-point constant whose integral representation can |
1842 | be moved into an integer register using a single sethi | |
1843 | instruction | |
1844 | ||
1845 | @item R | |
1846 | Floating-point constant whose integral representation can | |
1847 | be moved into an integer register using a single mov | |
1848 | instruction | |
03dda8e3 RK |
1849 | |
1850 | @item S | |
62190128 DM |
1851 | Floating-point constant whose integral representation can |
1852 | be moved into an integer register using a high/lo_sum | |
1853 | instruction sequence | |
03dda8e3 RK |
1854 | |
1855 | @item T | |
1856 | Memory address aligned to an 8-byte boundary | |
1857 | ||
1858 | @item U | |
1859 | Even register | |
6ca30df6 MH |
1860 | |
1861 | @end table | |
1862 | ||
1863 | @item TMS320C3x/C4x---@file{c4x.h} | |
1864 | @table @code | |
1865 | @item a | |
1866 | Auxiliary (address) register (ar0-ar7) | |
1867 | ||
1868 | @item b | |
1869 | Stack pointer register (sp) | |
1870 | ||
1871 | @item c | |
1e5f973d | 1872 | Standard (32-bit) precision integer register |
6ca30df6 MH |
1873 | |
1874 | @item f | |
1e5f973d | 1875 | Extended (40-bit) precision register (r0-r11) |
6ca30df6 MH |
1876 | |
1877 | @item k | |
1878 | Block count register (bk) | |
1879 | ||
1880 | @item q | |
1e5f973d | 1881 | Extended (40-bit) precision low register (r0-r7) |
6ca30df6 MH |
1882 | |
1883 | @item t | |
1e5f973d | 1884 | Extended (40-bit) precision register (r0-r1) |
6ca30df6 MH |
1885 | |
1886 | @item u | |
1e5f973d | 1887 | Extended (40-bit) precision register (r2-r3) |
6ca30df6 MH |
1888 | |
1889 | @item v | |
1890 | Repeat count register (rc) | |
1891 | ||
1892 | @item x | |
1893 | Index register (ir0-ir1) | |
1894 | ||
1895 | @item y | |
1896 | Status (condition code) register (st) | |
1897 | ||
1898 | @item z | |
1899 | Data page register (dp) | |
1900 | ||
1901 | @item G | |
1902 | Floating-point zero | |
1903 | ||
1904 | @item H | |
1e5f973d | 1905 | Immediate 16-bit floating-point constant |
6ca30df6 MH |
1906 | |
1907 | @item I | |
1e5f973d | 1908 | Signed 16-bit constant |
6ca30df6 MH |
1909 | |
1910 | @item J | |
1e5f973d | 1911 | Signed 8-bit constant |
6ca30df6 MH |
1912 | |
1913 | @item K | |
1e5f973d | 1914 | Signed 5-bit constant |
6ca30df6 MH |
1915 | |
1916 | @item L | |
1e5f973d | 1917 | Unsigned 16-bit constant |
6ca30df6 MH |
1918 | |
1919 | @item M | |
1e5f973d | 1920 | Unsigned 8-bit constant |
6ca30df6 MH |
1921 | |
1922 | @item N | |
1e5f973d | 1923 | Ones complement of unsigned 16-bit constant |
6ca30df6 MH |
1924 | |
1925 | @item O | |
1e5f973d | 1926 | High 16-bit constant (32-bit constant with 16 LSBs zero) |
6ca30df6 MH |
1927 | |
1928 | @item Q | |
ebb48a4d | 1929 | Indirect memory reference with signed 8-bit or index register displacement |
6ca30df6 MH |
1930 | |
1931 | @item R | |
1e5f973d | 1932 | Indirect memory reference with unsigned 5-bit displacement |
6ca30df6 MH |
1933 | |
1934 | @item S | |
ebb48a4d | 1935 | Indirect memory reference with 1 bit or index register displacement |
6ca30df6 MH |
1936 | |
1937 | @item T | |
1938 | Direct memory reference | |
1939 | ||
1940 | @item U | |
1941 | Symbolic address | |
1942 | ||
03dda8e3 RK |
1943 | @end table |
1944 | @end table | |
1945 | ||
03dda8e3 RK |
1946 | @ifset INTERNALS |
1947 | @node Standard Names | |
1948 | @section Standard Pattern Names For Generation | |
1949 | @cindex standard pattern names | |
1950 | @cindex pattern names | |
1951 | @cindex names, pattern | |
1952 | ||
1953 | Here is a table of the instruction names that are meaningful in the RTL | |
1954 | generation pass of the compiler. Giving one of these names to an | |
1955 | instruction pattern tells the RTL generation pass that it can use the | |
556e0f21 | 1956 | pattern to accomplish a certain task. |
03dda8e3 RK |
1957 | |
1958 | @table @asis | |
1959 | @cindex @code{mov@var{m}} instruction pattern | |
1960 | @item @samp{mov@var{m}} | |
1961 | Here @var{m} stands for a two-letter machine mode name, in lower case. | |
1962 | This instruction pattern moves data with that machine mode from operand | |
1963 | 1 to operand 0. For example, @samp{movsi} moves full-word data. | |
1964 | ||
1965 | If operand 0 is a @code{subreg} with mode @var{m} of a register whose | |
1966 | own mode is wider than @var{m}, the effect of this instruction is | |
1967 | to store the specified value in the part of the register that corresponds | |
1968 | to mode @var{m}. The effect on the rest of the register is undefined. | |
1969 | ||
1970 | This class of patterns is special in several ways. First of all, each | |
65945ec1 HPN |
1971 | of these names up to and including full word size @emph{must} be defined, |
1972 | because there is no other way to copy a datum from one place to another. | |
1973 | If there are patterns accepting operands in larger modes, | |
1974 | @samp{mov@var{m}} must be defined for integer modes of those sizes. | |
03dda8e3 RK |
1975 | |
1976 | Second, these patterns are not used solely in the RTL generation pass. | |
1977 | Even the reload pass can generate move insns to copy values from stack | |
1978 | slots into temporary registers. When it does so, one of the operands is | |
1979 | a hard register and the other is an operand that can need to be reloaded | |
1980 | into a register. | |
1981 | ||
1982 | @findex force_reg | |
1983 | Therefore, when given such a pair of operands, the pattern must generate | |
1984 | RTL which needs no reloading and needs no temporary registers---no | |
1985 | registers other than the operands. For example, if you support the | |
1986 | pattern with a @code{define_expand}, then in such a case the | |
1987 | @code{define_expand} mustn't call @code{force_reg} or any other such | |
1988 | function which might generate new pseudo registers. | |
1989 | ||
1990 | This requirement exists even for subword modes on a RISC machine where | |
1991 | fetching those modes from memory normally requires several insns and | |
39ed8974 | 1992 | some temporary registers. |
03dda8e3 RK |
1993 | |
1994 | @findex change_address | |
1995 | During reload a memory reference with an invalid address may be passed | |
1996 | as an operand. Such an address will be replaced with a valid address | |
1997 | later in the reload pass. In this case, nothing may be done with the | |
1998 | address except to use it as it stands. If it is copied, it will not be | |
1999 | replaced with a valid address. No attempt should be made to make such | |
2000 | an address into a valid address and no routine (such as | |
2001 | @code{change_address}) that will do so may be called. Note that | |
2002 | @code{general_operand} will fail when applied to such an address. | |
2003 | ||
2004 | @findex reload_in_progress | |
2005 | The global variable @code{reload_in_progress} (which must be explicitly | |
2006 | declared if required) can be used to determine whether such special | |
2007 | handling is required. | |
2008 | ||
2009 | The variety of operands that have reloads depends on the rest of the | |
2010 | machine description, but typically on a RISC machine these can only be | |
2011 | pseudo registers that did not get hard registers, while on other | |
2012 | machines explicit memory references will get optional reloads. | |
2013 | ||
2014 | If a scratch register is required to move an object to or from memory, | |
f1db3576 JL |
2015 | it can be allocated using @code{gen_reg_rtx} prior to life analysis. |
2016 | ||
2017 | If there are cases needing | |
03dda8e3 RK |
2018 | scratch registers after reload, you must define |
2019 | @code{SECONDARY_INPUT_RELOAD_CLASS} and perhaps also | |
2020 | @code{SECONDARY_OUTPUT_RELOAD_CLASS} to detect them, and provide | |
2021 | patterns @samp{reload_in@var{m}} or @samp{reload_out@var{m}} to handle | |
2022 | them. @xref{Register Classes}. | |
2023 | ||
f1db3576 JL |
2024 | @findex no_new_pseudos |
2025 | The global variable @code{no_new_pseudos} can be used to determine if it | |
2026 | is unsafe to create new pseudo registers. If this variable is nonzero, then | |
2027 | it is unsafe to call @code{gen_reg_rtx} to allocate a new pseudo. | |
2028 | ||
956d6950 | 2029 | The constraints on a @samp{mov@var{m}} must permit moving any hard |
03dda8e3 RK |
2030 | register to any other hard register provided that |
2031 | @code{HARD_REGNO_MODE_OK} permits mode @var{m} in both registers and | |
2032 | @code{REGISTER_MOVE_COST} applied to their classes returns a value of 2. | |
2033 | ||
956d6950 | 2034 | It is obligatory to support floating point @samp{mov@var{m}} |
03dda8e3 RK |
2035 | instructions into and out of any registers that can hold fixed point |
2036 | values, because unions and structures (which have modes @code{SImode} or | |
2037 | @code{DImode}) can be in those registers and they may have floating | |
2038 | point members. | |
2039 | ||
956d6950 | 2040 | There may also be a need to support fixed point @samp{mov@var{m}} |
03dda8e3 RK |
2041 | instructions in and out of floating point registers. Unfortunately, I |
2042 | have forgotten why this was so, and I don't know whether it is still | |
2043 | true. If @code{HARD_REGNO_MODE_OK} rejects fixed point values in | |
2044 | floating point registers, then the constraints of the fixed point | |
956d6950 | 2045 | @samp{mov@var{m}} instructions must be designed to avoid ever trying to |
03dda8e3 RK |
2046 | reload into a floating point register. |
2047 | ||
2048 | @cindex @code{reload_in} instruction pattern | |
2049 | @cindex @code{reload_out} instruction pattern | |
2050 | @item @samp{reload_in@var{m}} | |
2051 | @itemx @samp{reload_out@var{m}} | |
2052 | Like @samp{mov@var{m}}, but used when a scratch register is required to | |
2053 | move between operand 0 and operand 1. Operand 2 describes the scratch | |
2054 | register. See the discussion of the @code{SECONDARY_RELOAD_CLASS} | |
2055 | macro in @pxref{Register Classes}. | |
2056 | ||
2057 | @cindex @code{movstrict@var{m}} instruction pattern | |
2058 | @item @samp{movstrict@var{m}} | |
2059 | Like @samp{mov@var{m}} except that if operand 0 is a @code{subreg} | |
2060 | with mode @var{m} of a register whose natural mode is wider, | |
2061 | the @samp{movstrict@var{m}} instruction is guaranteed not to alter | |
2062 | any of the register except the part which belongs to mode @var{m}. | |
2063 | ||
2064 | @cindex @code{load_multiple} instruction pattern | |
2065 | @item @samp{load_multiple} | |
2066 | Load several consecutive memory locations into consecutive registers. | |
2067 | Operand 0 is the first of the consecutive registers, operand 1 | |
2068 | is the first memory location, and operand 2 is a constant: the | |
2069 | number of consecutive registers. | |
2070 | ||
2071 | Define this only if the target machine really has such an instruction; | |
2072 | do not define this if the most efficient way of loading consecutive | |
2073 | registers from memory is to do them one at a time. | |
2074 | ||
2075 | On some machines, there are restrictions as to which consecutive | |
2076 | registers can be stored into memory, such as particular starting or | |
2077 | ending register numbers or only a range of valid counts. For those | |
2078 | machines, use a @code{define_expand} (@pxref{Expander Definitions}) | |
2079 | and make the pattern fail if the restrictions are not met. | |
2080 | ||
2081 | Write the generated insn as a @code{parallel} with elements being a | |
2082 | @code{set} of one register from the appropriate memory location (you may | |
2083 | also need @code{use} or @code{clobber} elements). Use a | |
2084 | @code{match_parallel} (@pxref{RTL Template}) to recognize the insn. See | |
2085 | @file{a29k.md} and @file{rs6000.md} for examples of the use of this insn | |
2086 | pattern. | |
2087 | ||
2088 | @cindex @samp{store_multiple} instruction pattern | |
2089 | @item @samp{store_multiple} | |
2090 | Similar to @samp{load_multiple}, but store several consecutive registers | |
2091 | into consecutive memory locations. Operand 0 is the first of the | |
2092 | consecutive memory locations, operand 1 is the first register, and | |
2093 | operand 2 is a constant: the number of consecutive registers. | |
2094 | ||
2095 | @cindex @code{add@var{m}3} instruction pattern | |
2096 | @item @samp{add@var{m}3} | |
2097 | Add operand 2 and operand 1, storing the result in operand 0. All operands | |
2098 | must have mode @var{m}. This can be used even on two-address machines, by | |
2099 | means of constraints requiring operands 1 and 0 to be the same location. | |
2100 | ||
2101 | @cindex @code{sub@var{m}3} instruction pattern | |
2102 | @cindex @code{mul@var{m}3} instruction pattern | |
2103 | @cindex @code{div@var{m}3} instruction pattern | |
2104 | @cindex @code{udiv@var{m}3} instruction pattern | |
2105 | @cindex @code{mod@var{m}3} instruction pattern | |
2106 | @cindex @code{umod@var{m}3} instruction pattern | |
2107 | @cindex @code{smin@var{m}3} instruction pattern | |
2108 | @cindex @code{smax@var{m}3} instruction pattern | |
2109 | @cindex @code{umin@var{m}3} instruction pattern | |
2110 | @cindex @code{umax@var{m}3} instruction pattern | |
2111 | @cindex @code{and@var{m}3} instruction pattern | |
2112 | @cindex @code{ior@var{m}3} instruction pattern | |
2113 | @cindex @code{xor@var{m}3} instruction pattern | |
2114 | @item @samp{sub@var{m}3}, @samp{mul@var{m}3} | |
2115 | @itemx @samp{div@var{m}3}, @samp{udiv@var{m}3}, @samp{mod@var{m}3}, @samp{umod@var{m}3} | |
2116 | @itemx @samp{smin@var{m}3}, @samp{smax@var{m}3}, @samp{umin@var{m}3}, @samp{umax@var{m}3} | |
2117 | @itemx @samp{and@var{m}3}, @samp{ior@var{m}3}, @samp{xor@var{m}3} | |
2118 | Similar, for other arithmetic operations. | |
b71b019a JH |
2119 | @cindex @code{min@var{m}3} instruction pattern |
2120 | @cindex @code{max@var{m}3} instruction pattern | |
2121 | @itemx @samp{min@var{m}3}, @samp{max@var{m}3} | |
2122 | Floating point min and max operations. If both operands are zeros, | |
2123 | or if either operand is NaN, then it is unspecified which of the two | |
2124 | operands is returned as the result. | |
2125 | ||
03dda8e3 RK |
2126 | |
2127 | @cindex @code{mulhisi3} instruction pattern | |
2128 | @item @samp{mulhisi3} | |
2129 | Multiply operands 1 and 2, which have mode @code{HImode}, and store | |
2130 | a @code{SImode} product in operand 0. | |
2131 | ||
2132 | @cindex @code{mulqihi3} instruction pattern | |
2133 | @cindex @code{mulsidi3} instruction pattern | |
2134 | @item @samp{mulqihi3}, @samp{mulsidi3} | |
2135 | Similar widening-multiplication instructions of other widths. | |
2136 | ||
2137 | @cindex @code{umulqihi3} instruction pattern | |
2138 | @cindex @code{umulhisi3} instruction pattern | |
2139 | @cindex @code{umulsidi3} instruction pattern | |
2140 | @item @samp{umulqihi3}, @samp{umulhisi3}, @samp{umulsidi3} | |
2141 | Similar widening-multiplication instructions that do unsigned | |
2142 | multiplication. | |
2143 | ||
2144 | @cindex @code{smul@var{m}3_highpart} instruction pattern | |
759c58af | 2145 | @item @samp{smul@var{m}3_highpart} |
03dda8e3 RK |
2146 | Perform a signed multiplication of operands 1 and 2, which have mode |
2147 | @var{m}, and store the most significant half of the product in operand 0. | |
2148 | The least significant half of the product is discarded. | |
2149 | ||
2150 | @cindex @code{umul@var{m}3_highpart} instruction pattern | |
2151 | @item @samp{umul@var{m}3_highpart} | |
2152 | Similar, but the multiplication is unsigned. | |
2153 | ||
2154 | @cindex @code{divmod@var{m}4} instruction pattern | |
2155 | @item @samp{divmod@var{m}4} | |
2156 | Signed division that produces both a quotient and a remainder. | |
2157 | Operand 1 is divided by operand 2 to produce a quotient stored | |
2158 | in operand 0 and a remainder stored in operand 3. | |
2159 | ||
2160 | For machines with an instruction that produces both a quotient and a | |
2161 | remainder, provide a pattern for @samp{divmod@var{m}4} but do not | |
2162 | provide patterns for @samp{div@var{m}3} and @samp{mod@var{m}3}. This | |
2163 | allows optimization in the relatively common case when both the quotient | |
2164 | and remainder are computed. | |
2165 | ||
2166 | If an instruction that just produces a quotient or just a remainder | |
2167 | exists and is more efficient than the instruction that produces both, | |
2168 | write the output routine of @samp{divmod@var{m}4} to call | |
2169 | @code{find_reg_note} and look for a @code{REG_UNUSED} note on the | |
2170 | quotient or remainder and generate the appropriate instruction. | |
2171 | ||
2172 | @cindex @code{udivmod@var{m}4} instruction pattern | |
2173 | @item @samp{udivmod@var{m}4} | |
2174 | Similar, but does unsigned division. | |
2175 | ||
2176 | @cindex @code{ashl@var{m}3} instruction pattern | |
2177 | @item @samp{ashl@var{m}3} | |
2178 | Arithmetic-shift operand 1 left by a number of bits specified by operand | |
2179 | 2, and store the result in operand 0. Here @var{m} is the mode of | |
2180 | operand 0 and operand 1; operand 2's mode is specified by the | |
2181 | instruction pattern, and the compiler will convert the operand to that | |
2182 | mode before generating the instruction. | |
2183 | ||
2184 | @cindex @code{ashr@var{m}3} instruction pattern | |
2185 | @cindex @code{lshr@var{m}3} instruction pattern | |
2186 | @cindex @code{rotl@var{m}3} instruction pattern | |
2187 | @cindex @code{rotr@var{m}3} instruction pattern | |
2188 | @item @samp{ashr@var{m}3}, @samp{lshr@var{m}3}, @samp{rotl@var{m}3}, @samp{rotr@var{m}3} | |
2189 | Other shift and rotate instructions, analogous to the | |
2190 | @code{ashl@var{m}3} instructions. | |
2191 | ||
2192 | @cindex @code{neg@var{m}2} instruction pattern | |
2193 | @item @samp{neg@var{m}2} | |
2194 | Negate operand 1 and store the result in operand 0. | |
2195 | ||
2196 | @cindex @code{abs@var{m}2} instruction pattern | |
2197 | @item @samp{abs@var{m}2} | |
2198 | Store the absolute value of operand 1 into operand 0. | |
2199 | ||
2200 | @cindex @code{sqrt@var{m}2} instruction pattern | |
2201 | @item @samp{sqrt@var{m}2} | |
2202 | Store the square root of operand 1 into operand 0. | |
2203 | ||
2204 | The @code{sqrt} built-in function of C always uses the mode which | |
2205 | corresponds to the C data type @code{double}. | |
2206 | ||
2207 | @cindex @code{ffs@var{m}2} instruction pattern | |
2208 | @item @samp{ffs@var{m}2} | |
2209 | Store into operand 0 one plus the index of the least significant 1-bit | |
2210 | of operand 1. If operand 1 is zero, store zero. @var{m} is the mode | |
2211 | of operand 0; operand 1's mode is specified by the instruction | |
2212 | pattern, and the compiler will convert the operand to that mode before | |
2213 | generating the instruction. | |
2214 | ||
2215 | The @code{ffs} built-in function of C always uses the mode which | |
2216 | corresponds to the C data type @code{int}. | |
2217 | ||
2218 | @cindex @code{one_cmpl@var{m}2} instruction pattern | |
2219 | @item @samp{one_cmpl@var{m}2} | |
2220 | Store the bitwise-complement of operand 1 into operand 0. | |
2221 | ||
2222 | @cindex @code{cmp@var{m}} instruction pattern | |
2223 | @item @samp{cmp@var{m}} | |
2224 | Compare operand 0 and operand 1, and set the condition codes. | |
2225 | The RTL pattern should look like this: | |
2226 | ||
2227 | @smallexample | |
2228 | (set (cc0) (compare (match_operand:@var{m} 0 @dots{}) | |
2229 | (match_operand:@var{m} 1 @dots{}))) | |
2230 | @end smallexample | |
2231 | ||
2232 | @cindex @code{tst@var{m}} instruction pattern | |
2233 | @item @samp{tst@var{m}} | |
2234 | Compare operand 0 against zero, and set the condition codes. | |
2235 | The RTL pattern should look like this: | |
2236 | ||
2237 | @smallexample | |
2238 | (set (cc0) (match_operand:@var{m} 0 @dots{})) | |
2239 | @end smallexample | |
2240 | ||
2241 | @samp{tst@var{m}} patterns should not be defined for machines that do | |
2242 | not use @code{(cc0)}. Doing so would confuse the optimizer since it | |
2243 | would no longer be clear which @code{set} operations were comparisons. | |
2244 | The @samp{cmp@var{m}} patterns should be used instead. | |
2245 | ||
2246 | @cindex @code{movstr@var{m}} instruction pattern | |
2247 | @item @samp{movstr@var{m}} | |
2248 | Block move instruction. The addresses of the destination and source | |
2249 | strings are the first two operands, and both are in mode @code{Pmode}. | |
e5e809f4 | 2250 | |
03dda8e3 | 2251 | The number of bytes to move is the third operand, in mode @var{m}. |
e5e809f4 JL |
2252 | Usually, you specify @code{word_mode} for @var{m}. However, if you can |
2253 | generate better code knowing the range of valid lengths is smaller than | |
2254 | those representable in a full word, you should provide a pattern with a | |
2255 | mode corresponding to the range of values you can handle efficiently | |
2256 | (e.g., @code{QImode} for values in the range 0--127; note we avoid numbers | |
2257 | that appear negative) and also a pattern with @code{word_mode}. | |
03dda8e3 RK |
2258 | |
2259 | The fourth operand is the known shared alignment of the source and | |
2260 | destination, in the form of a @code{const_int} rtx. Thus, if the | |
2261 | compiler knows that both source and destination are word-aligned, | |
2262 | it may provide the value 4 for this operand. | |
2263 | ||
8c01d9b6 | 2264 | Descriptions of multiple @code{movstr@var{m}} patterns can only be |
4693911f | 2265 | beneficial if the patterns for smaller modes have fewer restrictions |
8c01d9b6 JL |
2266 | on their first, second and fourth operands. Note that the mode @var{m} |
2267 | in @code{movstr@var{m}} does not impose any restriction on the mode of | |
2268 | individually moved data units in the block. | |
2269 | ||
03dda8e3 RK |
2270 | These patterns need not give special consideration to the possibility |
2271 | that the source and destination strings might overlap. | |
2272 | ||
2273 | @cindex @code{clrstr@var{m}} instruction pattern | |
2274 | @item @samp{clrstr@var{m}} | |
2275 | Block clear instruction. The addresses of the destination string is the | |
2276 | first operand, in mode @code{Pmode}. The number of bytes to clear is | |
e5e809f4 JL |
2277 | the second operand, in mode @var{m}. See @samp{movstr@var{m}} for |
2278 | a discussion of the choice of mode. | |
03dda8e3 RK |
2279 | |
2280 | The third operand is the known alignment of the destination, in the form | |
2281 | of a @code{const_int} rtx. Thus, if the compiler knows that the | |
2282 | destination is word-aligned, it may provide the value 4 for this | |
2283 | operand. | |
2284 | ||
8c01d9b6 JL |
2285 | The use for multiple @code{clrstr@var{m}} is as for @code{movstr@var{m}}. |
2286 | ||
03dda8e3 RK |
2287 | @cindex @code{cmpstr@var{m}} instruction pattern |
2288 | @item @samp{cmpstr@var{m}} | |
2289 | Block compare instruction, with five operands. Operand 0 is the output; | |
2290 | it has mode @var{m}. The remaining four operands are like the operands | |
2291 | of @samp{movstr@var{m}}. The two memory blocks specified are compared | |
2292 | byte by byte in lexicographic order. The effect of the instruction is | |
2293 | to store a value in operand 0 whose sign indicates the result of the | |
2294 | comparison. | |
2295 | ||
2296 | @cindex @code{strlen@var{m}} instruction pattern | |
2297 | @item @samp{strlen@var{m}} | |
2298 | Compute the length of a string, with three operands. | |
2299 | Operand 0 is the result (of mode @var{m}), operand 1 is | |
2300 | a @code{mem} referring to the first character of the string, | |
2301 | operand 2 is the character to search for (normally zero), | |
2302 | and operand 3 is a constant describing the known alignment | |
2303 | of the beginning of the string. | |
2304 | ||
2305 | @cindex @code{float@var{mn}2} instruction pattern | |
2306 | @item @samp{float@var{m}@var{n}2} | |
2307 | Convert signed integer operand 1 (valid for fixed point mode @var{m}) to | |
2308 | floating point mode @var{n} and store in operand 0 (which has mode | |
2309 | @var{n}). | |
2310 | ||
2311 | @cindex @code{floatuns@var{mn}2} instruction pattern | |
2312 | @item @samp{floatuns@var{m}@var{n}2} | |
2313 | Convert unsigned integer operand 1 (valid for fixed point mode @var{m}) | |
2314 | to floating point mode @var{n} and store in operand 0 (which has mode | |
2315 | @var{n}). | |
2316 | ||
2317 | @cindex @code{fix@var{mn}2} instruction pattern | |
2318 | @item @samp{fix@var{m}@var{n}2} | |
2319 | Convert operand 1 (valid for floating point mode @var{m}) to fixed | |
2320 | point mode @var{n} as a signed number and store in operand 0 (which | |
2321 | has mode @var{n}). This instruction's result is defined only when | |
2322 | the value of operand 1 is an integer. | |
2323 | ||
2324 | @cindex @code{fixuns@var{mn}2} instruction pattern | |
2325 | @item @samp{fixuns@var{m}@var{n}2} | |
2326 | Convert operand 1 (valid for floating point mode @var{m}) to fixed | |
2327 | point mode @var{n} as an unsigned number and store in operand 0 (which | |
2328 | has mode @var{n}). This instruction's result is defined only when the | |
2329 | value of operand 1 is an integer. | |
2330 | ||
2331 | @cindex @code{ftrunc@var{m}2} instruction pattern | |
2332 | @item @samp{ftrunc@var{m}2} | |
2333 | Convert operand 1 (valid for floating point mode @var{m}) to an | |
2334 | integer value, still represented in floating point mode @var{m}, and | |
2335 | store it in operand 0 (valid for floating point mode @var{m}). | |
2336 | ||
2337 | @cindex @code{fix_trunc@var{mn}2} instruction pattern | |
2338 | @item @samp{fix_trunc@var{m}@var{n}2} | |
2339 | Like @samp{fix@var{m}@var{n}2} but works for any floating point value | |
2340 | of mode @var{m} by converting the value to an integer. | |
2341 | ||
2342 | @cindex @code{fixuns_trunc@var{mn}2} instruction pattern | |
2343 | @item @samp{fixuns_trunc@var{m}@var{n}2} | |
2344 | Like @samp{fixuns@var{m}@var{n}2} but works for any floating point | |
2345 | value of mode @var{m} by converting the value to an integer. | |
2346 | ||
2347 | @cindex @code{trunc@var{mn}2} instruction pattern | |
2348 | @item @samp{trunc@var{m}@var{n}2} | |
2349 | Truncate operand 1 (valid for mode @var{m}) to mode @var{n} and | |
2350 | store in operand 0 (which has mode @var{n}). Both modes must be fixed | |
2351 | point or both floating point. | |
2352 | ||
2353 | @cindex @code{extend@var{mn}2} instruction pattern | |
2354 | @item @samp{extend@var{m}@var{n}2} | |
2355 | Sign-extend operand 1 (valid for mode @var{m}) to mode @var{n} and | |
2356 | store in operand 0 (which has mode @var{n}). Both modes must be fixed | |
2357 | point or both floating point. | |
2358 | ||
2359 | @cindex @code{zero_extend@var{mn}2} instruction pattern | |
2360 | @item @samp{zero_extend@var{m}@var{n}2} | |
2361 | Zero-extend operand 1 (valid for mode @var{m}) to mode @var{n} and | |
2362 | store in operand 0 (which has mode @var{n}). Both modes must be fixed | |
2363 | point. | |
2364 | ||
2365 | @cindex @code{extv} instruction pattern | |
2366 | @item @samp{extv} | |
2367 | Extract a bit field from operand 1 (a register or memory operand), where | |
2368 | operand 2 specifies the width in bits and operand 3 the starting bit, | |
2369 | and store it in operand 0. Operand 0 must have mode @code{word_mode}. | |
2370 | Operand 1 may have mode @code{byte_mode} or @code{word_mode}; often | |
2371 | @code{word_mode} is allowed only for registers. Operands 2 and 3 must | |
2372 | be valid for @code{word_mode}. | |
2373 | ||
2374 | The RTL generation pass generates this instruction only with constants | |
2375 | for operands 2 and 3. | |
2376 | ||
2377 | The bit-field value is sign-extended to a full word integer | |
2378 | before it is stored in operand 0. | |
2379 | ||
2380 | @cindex @code{extzv} instruction pattern | |
2381 | @item @samp{extzv} | |
2382 | Like @samp{extv} except that the bit-field value is zero-extended. | |
2383 | ||
2384 | @cindex @code{insv} instruction pattern | |
2385 | @item @samp{insv} | |
2386 | Store operand 3 (which must be valid for @code{word_mode}) into a bit | |
2387 | field in operand 0, where operand 1 specifies the width in bits and | |
2388 | operand 2 the starting bit. Operand 0 may have mode @code{byte_mode} or | |
2389 | @code{word_mode}; often @code{word_mode} is allowed only for registers. | |
2390 | Operands 1 and 2 must be valid for @code{word_mode}. | |
2391 | ||
2392 | The RTL generation pass generates this instruction only with constants | |
2393 | for operands 1 and 2. | |
2394 | ||
2395 | @cindex @code{mov@var{mode}cc} instruction pattern | |
2396 | @item @samp{mov@var{mode}cc} | |
2397 | Conditionally move operand 2 or operand 3 into operand 0 according to the | |
2398 | comparison in operand 1. If the comparison is true, operand 2 is moved | |
2399 | into operand 0, otherwise operand 3 is moved. | |
2400 | ||
2401 | The mode of the operands being compared need not be the same as the operands | |
2402 | being moved. Some machines, sparc64 for example, have instructions that | |
2403 | conditionally move an integer value based on the floating point condition | |
2404 | codes and vice versa. | |
2405 | ||
2406 | If the machine does not have conditional move instructions, do not | |
2407 | define these patterns. | |
2408 | ||
2409 | @cindex @code{s@var{cond}} instruction pattern | |
2410 | @item @samp{s@var{cond}} | |
2411 | Store zero or nonzero in the operand according to the condition codes. | |
2412 | Value stored is nonzero iff the condition @var{cond} is true. | |
2413 | @var{cond} is the name of a comparison operation expression code, such | |
2414 | as @code{eq}, @code{lt} or @code{leu}. | |
2415 | ||
2416 | You specify the mode that the operand must have when you write the | |
2417 | @code{match_operand} expression. The compiler automatically sees | |
2418 | which mode you have used and supplies an operand of that mode. | |
2419 | ||
2420 | The value stored for a true condition must have 1 as its low bit, or | |
2421 | else must be negative. Otherwise the instruction is not suitable and | |
2422 | you should omit it from the machine description. You describe to the | |
2423 | compiler exactly which value is stored by defining the macro | |
2424 | @code{STORE_FLAG_VALUE} (@pxref{Misc}). If a description cannot be | |
2425 | found that can be used for all the @samp{s@var{cond}} patterns, you | |
2426 | should omit those operations from the machine description. | |
2427 | ||
2428 | These operations may fail, but should do so only in relatively | |
2429 | uncommon cases; if they would fail for common cases involving | |
2430 | integer comparisons, it is best to omit these patterns. | |
2431 | ||
2432 | If these operations are omitted, the compiler will usually generate code | |
2433 | that copies the constant one to the target and branches around an | |
2434 | assignment of zero to the target. If this code is more efficient than | |
2435 | the potential instructions used for the @samp{s@var{cond}} pattern | |
2436 | followed by those required to convert the result into a 1 or a zero in | |
2437 | @code{SImode}, you should omit the @samp{s@var{cond}} operations from | |
2438 | the machine description. | |
2439 | ||
2440 | @cindex @code{b@var{cond}} instruction pattern | |
2441 | @item @samp{b@var{cond}} | |
2442 | Conditional branch instruction. Operand 0 is a @code{label_ref} that | |
2443 | refers to the label to jump to. Jump if the condition codes meet | |
2444 | condition @var{cond}. | |
2445 | ||
2446 | Some machines do not follow the model assumed here where a comparison | |
2447 | instruction is followed by a conditional branch instruction. In that | |
2448 | case, the @samp{cmp@var{m}} (and @samp{tst@var{m}}) patterns should | |
2449 | simply store the operands away and generate all the required insns in a | |
2450 | @code{define_expand} (@pxref{Expander Definitions}) for the conditional | |
2451 | branch operations. All calls to expand @samp{b@var{cond}} patterns are | |
2452 | immediately preceded by calls to expand either a @samp{cmp@var{m}} | |
2453 | pattern or a @samp{tst@var{m}} pattern. | |
2454 | ||
2455 | Machines that use a pseudo register for the condition code value, or | |
2456 | where the mode used for the comparison depends on the condition being | |
0b433de6 | 2457 | tested, should also use the above mechanism. @xref{Jump Patterns}. |
03dda8e3 RK |
2458 | |
2459 | The above discussion also applies to the @samp{mov@var{mode}cc} and | |
2460 | @samp{s@var{cond}} patterns. | |
2461 | ||
d26eedb6 HPN |
2462 | @cindex @code{jump} instruction pattern |
2463 | @item @samp{jump} | |
2464 | A jump inside a function; an unconditional branch. Operand 0 is the | |
2465 | @code{label_ref} of the label to jump to. This pattern name is mandatory | |
2466 | on all machines. | |
2467 | ||
03dda8e3 RK |
2468 | @cindex @code{call} instruction pattern |
2469 | @item @samp{call} | |
2470 | Subroutine call instruction returning no value. Operand 0 is the | |
2471 | function to call; operand 1 is the number of bytes of arguments pushed | |
f5963e61 JL |
2472 | as a @code{const_int}; operand 2 is the number of registers used as |
2473 | operands. | |
03dda8e3 RK |
2474 | |
2475 | On most machines, operand 2 is not actually stored into the RTL | |
2476 | pattern. It is supplied for the sake of some RISC machines which need | |
2477 | to put this information into the assembler code; they can put it in | |
2478 | the RTL instead of operand 1. | |
2479 | ||
2480 | Operand 0 should be a @code{mem} RTX whose address is the address of the | |
2481 | function. Note, however, that this address can be a @code{symbol_ref} | |
2482 | expression even if it would not be a legitimate memory address on the | |
2483 | target machine. If it is also not a valid argument for a call | |
2484 | instruction, the pattern for this operation should be a | |
2485 | @code{define_expand} (@pxref{Expander Definitions}) that places the | |
2486 | address into a register and uses that register in the call instruction. | |
2487 | ||
2488 | @cindex @code{call_value} instruction pattern | |
2489 | @item @samp{call_value} | |
2490 | Subroutine call instruction returning a value. Operand 0 is the hard | |
2491 | register in which the value is returned. There are three more | |
2492 | operands, the same as the three operands of the @samp{call} | |
2493 | instruction (but with numbers increased by one). | |
2494 | ||
2495 | Subroutines that return @code{BLKmode} objects use the @samp{call} | |
2496 | insn. | |
2497 | ||
2498 | @cindex @code{call_pop} instruction pattern | |
2499 | @cindex @code{call_value_pop} instruction pattern | |
2500 | @item @samp{call_pop}, @samp{call_value_pop} | |
2501 | Similar to @samp{call} and @samp{call_value}, except used if defined and | |
2502 | if @code{RETURN_POPS_ARGS} is non-zero. They should emit a @code{parallel} | |
2503 | that contains both the function call and a @code{set} to indicate the | |
2504 | adjustment made to the frame pointer. | |
2505 | ||
2506 | For machines where @code{RETURN_POPS_ARGS} can be non-zero, the use of these | |
2507 | patterns increases the number of functions for which the frame pointer | |
2508 | can be eliminated, if desired. | |
2509 | ||
2510 | @cindex @code{untyped_call} instruction pattern | |
2511 | @item @samp{untyped_call} | |
2512 | Subroutine call instruction returning a value of any type. Operand 0 is | |
2513 | the function to call; operand 1 is a memory location where the result of | |
2514 | calling the function is to be stored; operand 2 is a @code{parallel} | |
2515 | expression where each element is a @code{set} expression that indicates | |
2516 | the saving of a function return value into the result block. | |
2517 | ||
2518 | This instruction pattern should be defined to support | |
2519 | @code{__builtin_apply} on machines where special instructions are needed | |
2520 | to call a subroutine with arbitrary arguments or to save the value | |
2521 | returned. This instruction pattern is required on machines that have | |
2522 | multiple registers that can hold a return value (i.e. | |
2523 | @code{FUNCTION_VALUE_REGNO_P} is true for more than one register). | |
2524 | ||
2525 | @cindex @code{return} instruction pattern | |
2526 | @item @samp{return} | |
2527 | Subroutine return instruction. This instruction pattern name should be | |
2528 | defined only if a single instruction can do all the work of returning | |
2529 | from a function. | |
2530 | ||
2531 | Like the @samp{mov@var{m}} patterns, this pattern is also used after the | |
2532 | RTL generation phase. In this case it is to support machines where | |
2533 | multiple instructions are usually needed to return from a function, but | |
2534 | some class of functions only requires one instruction to implement a | |
2535 | return. Normally, the applicable functions are those which do not need | |
2536 | to save any registers or allocate stack space. | |
2537 | ||
2538 | @findex reload_completed | |
2539 | @findex leaf_function_p | |
2540 | For such machines, the condition specified in this pattern should only | |
2541 | be true when @code{reload_completed} is non-zero and the function's | |
2542 | epilogue would only be a single instruction. For machines with register | |
2543 | windows, the routine @code{leaf_function_p} may be used to determine if | |
2544 | a register window push is required. | |
2545 | ||
2546 | Machines that have conditional return instructions should define patterns | |
2547 | such as | |
2548 | ||
2549 | @smallexample | |
2550 | (define_insn "" | |
2551 | [(set (pc) | |
2552 | (if_then_else (match_operator | |
2553 | 0 "comparison_operator" | |
2554 | [(cc0) (const_int 0)]) | |
2555 | (return) | |
2556 | (pc)))] | |
2557 | "@var{condition}" | |
2558 | "@dots{}") | |
2559 | @end smallexample | |
2560 | ||
2561 | where @var{condition} would normally be the same condition specified on the | |
2562 | named @samp{return} pattern. | |
2563 | ||
2564 | @cindex @code{untyped_return} instruction pattern | |
2565 | @item @samp{untyped_return} | |
2566 | Untyped subroutine return instruction. This instruction pattern should | |
2567 | be defined to support @code{__builtin_return} on machines where special | |
2568 | instructions are needed to return a value of any type. | |
2569 | ||
2570 | Operand 0 is a memory location where the result of calling a function | |
2571 | with @code{__builtin_apply} is stored; operand 1 is a @code{parallel} | |
2572 | expression where each element is a @code{set} expression that indicates | |
2573 | the restoring of a function return value from the result block. | |
2574 | ||
2575 | @cindex @code{nop} instruction pattern | |
2576 | @item @samp{nop} | |
2577 | No-op instruction. This instruction pattern name should always be defined | |
2578 | to output a no-op in assembler code. @code{(const_int 0)} will do as an | |
2579 | RTL pattern. | |
2580 | ||
2581 | @cindex @code{indirect_jump} instruction pattern | |
2582 | @item @samp{indirect_jump} | |
2583 | An instruction to jump to an address which is operand zero. | |
2584 | This pattern name is mandatory on all machines. | |
2585 | ||
2586 | @cindex @code{casesi} instruction pattern | |
2587 | @item @samp{casesi} | |
2588 | Instruction to jump through a dispatch table, including bounds checking. | |
2589 | This instruction takes five operands: | |
2590 | ||
2591 | @enumerate | |
2592 | @item | |
2593 | The index to dispatch on, which has mode @code{SImode}. | |
2594 | ||
2595 | @item | |
2596 | The lower bound for indices in the table, an integer constant. | |
2597 | ||
2598 | @item | |
2599 | The total range of indices in the table---the largest index | |
2600 | minus the smallest one (both inclusive). | |
2601 | ||
2602 | @item | |
2603 | A label that precedes the table itself. | |
2604 | ||
2605 | @item | |
2606 | A label to jump to if the index has a value outside the bounds. | |
2607 | (If the machine-description macro @code{CASE_DROPS_THROUGH} is defined, | |
2608 | then an out-of-bounds index drops through to the code following | |
2609 | the jump table instead of jumping to this label. In that case, | |
2610 | this label is not actually used by the @samp{casesi} instruction, | |
2611 | but it is always provided as an operand.) | |
2612 | @end enumerate | |
2613 | ||
2614 | The table is a @code{addr_vec} or @code{addr_diff_vec} inside of a | |
2615 | @code{jump_insn}. The number of elements in the table is one plus the | |
2616 | difference between the upper bound and the lower bound. | |
2617 | ||
2618 | @cindex @code{tablejump} instruction pattern | |
2619 | @item @samp{tablejump} | |
2620 | Instruction to jump to a variable address. This is a low-level | |
2621 | capability which can be used to implement a dispatch table when there | |
2622 | is no @samp{casesi} pattern. | |
2623 | ||
2624 | This pattern requires two operands: the address or offset, and a label | |
2625 | which should immediately precede the jump table. If the macro | |
f1f5f142 JL |
2626 | @code{CASE_VECTOR_PC_RELATIVE} evaluates to a nonzero value then the first |
2627 | operand is an offset which counts from the address of the table; otherwise, | |
2628 | it is an absolute address to jump to. In either case, the first operand has | |
03dda8e3 RK |
2629 | mode @code{Pmode}. |
2630 | ||
2631 | The @samp{tablejump} insn is always the last insn before the jump | |
2632 | table it uses. Its assembler code normally has no need to use the | |
2633 | second operand, but you should incorporate it in the RTL pattern so | |
2634 | that the jump optimizer will not delete the table as unreachable code. | |
2635 | ||
6e4fcc95 MH |
2636 | |
2637 | @cindex @code{decrement_and_branch_until_zero} instruction pattern | |
2638 | @item @samp{decrement_and_branch_until_zero} | |
2639 | Conditional branch instruction that decrements a register and | |
2640 | jumps if the register is non-zero. Operand 0 is the register to | |
2641 | decrement and test; operand 1 is the label to jump to if the | |
5c25e11d | 2642 | register is non-zero. @xref{Looping Patterns}. |
6e4fcc95 MH |
2643 | |
2644 | This optional instruction pattern is only used by the combiner, | |
2645 | typically for loops reversed by the loop optimizer when strength | |
2646 | reduction is enabled. | |
2647 | ||
2648 | @cindex @code{doloop_end} instruction pattern | |
2649 | @item @samp{doloop_end} | |
2650 | Conditional branch instruction that decrements a register and jumps if | |
2651 | the register is non-zero. This instruction takes five operands: Operand | |
2652 | 0 is the register to decrement and test; operand 1 is the number of loop | |
2653 | iterations as a @code{const_int} or @code{const0_rtx} if this cannot be | |
2654 | determined until run-time; operand 2 is the actual or estimated maximum | |
2655 | number of iterations as a @code{const_int}; operand 3 is the number of | |
2656 | enclosed loops as a @code{const_int} (an innermost loop has a value of | |
2657 | 1); operand 4 is the label to jump to if the register is non-zero. | |
5c25e11d | 2658 | @xref{Looping Patterns}. |
6e4fcc95 MH |
2659 | |
2660 | This optional instruction pattern should be defined for machines with | |
2661 | low-overhead looping instructions as the loop optimizer will try to | |
2662 | modify suitable loops to utilize it. If nested low-overhead looping is | |
2663 | not supported, use a @code{define_expand} (@pxref{Expander Definitions}) | |
2664 | and make the pattern fail if operand 3 is not @code{const1_rtx}. | |
2665 | Similarly, if the actual or estimated maximum number of iterations is | |
2666 | too large for this instruction, make it fail. | |
2667 | ||
2668 | @cindex @code{doloop_begin} instruction pattern | |
2669 | @item @samp{doloop_begin} | |
2670 | Companion instruction to @code{doloop_end} required for machines that | |
2671 | need to perform some initialisation, such as loading special registers | |
2672 | used by a low-overhead looping instruction. If initialisation insns do | |
2673 | not always need to be emitted, use a @code{define_expand} | |
2674 | (@pxref{Expander Definitions}) and make it fail. | |
2675 | ||
2676 | ||
03dda8e3 RK |
2677 | @cindex @code{canonicalize_funcptr_for_compare} instruction pattern |
2678 | @item @samp{canonicalize_funcptr_for_compare} | |
2679 | Canonicalize the function pointer in operand 1 and store the result | |
2680 | into operand 0. | |
2681 | ||
2682 | Operand 0 is always a @code{reg} and has mode @code{Pmode}; operand 1 | |
2683 | may be a @code{reg}, @code{mem}, @code{symbol_ref}, @code{const_int}, etc | |
2684 | and also has mode @code{Pmode}. | |
2685 | ||
2686 | Canonicalization of a function pointer usually involves computing | |
2687 | the address of the function which would be called if the function | |
2688 | pointer were used in an indirect call. | |
2689 | ||
2690 | Only define this pattern if function pointers on the target machine | |
2691 | can have different values but still call the same function when | |
2692 | used in an indirect call. | |
2693 | ||
2694 | @cindex @code{save_stack_block} instruction pattern | |
2695 | @cindex @code{save_stack_function} instruction pattern | |
2696 | @cindex @code{save_stack_nonlocal} instruction pattern | |
2697 | @cindex @code{restore_stack_block} instruction pattern | |
2698 | @cindex @code{restore_stack_function} instruction pattern | |
2699 | @cindex @code{restore_stack_nonlocal} instruction pattern | |
2700 | @item @samp{save_stack_block} | |
2701 | @itemx @samp{save_stack_function} | |
2702 | @itemx @samp{save_stack_nonlocal} | |
2703 | @itemx @samp{restore_stack_block} | |
2704 | @itemx @samp{restore_stack_function} | |
2705 | @itemx @samp{restore_stack_nonlocal} | |
2706 | Most machines save and restore the stack pointer by copying it to or | |
2707 | from an object of mode @code{Pmode}. Do not define these patterns on | |
2708 | such machines. | |
2709 | ||
2710 | Some machines require special handling for stack pointer saves and | |
2711 | restores. On those machines, define the patterns corresponding to the | |
2712 | non-standard cases by using a @code{define_expand} (@pxref{Expander | |
2713 | Definitions}) that produces the required insns. The three types of | |
2714 | saves and restores are: | |
2715 | ||
2716 | @enumerate | |
2717 | @item | |
2718 | @samp{save_stack_block} saves the stack pointer at the start of a block | |
2719 | that allocates a variable-sized object, and @samp{restore_stack_block} | |
2720 | restores the stack pointer when the block is exited. | |
2721 | ||
2722 | @item | |
2723 | @samp{save_stack_function} and @samp{restore_stack_function} do a | |
2724 | similar job for the outermost block of a function and are used when the | |
2725 | function allocates variable-sized objects or calls @code{alloca}. Only | |
2726 | the epilogue uses the restored stack pointer, allowing a simpler save or | |
2727 | restore sequence on some machines. | |
2728 | ||
2729 | @item | |
2730 | @samp{save_stack_nonlocal} is used in functions that contain labels | |
2731 | branched to by nested functions. It saves the stack pointer in such a | |
2732 | way that the inner function can use @samp{restore_stack_nonlocal} to | |
2733 | restore the stack pointer. The compiler generates code to restore the | |
2734 | frame and argument pointer registers, but some machines require saving | |
2735 | and restoring additional data such as register window information or | |
2736 | stack backchains. Place insns in these patterns to save and restore any | |
2737 | such required data. | |
2738 | @end enumerate | |
2739 | ||
2740 | When saving the stack pointer, operand 0 is the save area and operand 1 | |
73c8090f DE |
2741 | is the stack pointer. The mode used to allocate the save area defaults |
2742 | to @code{Pmode} but you can override that choice by defining the | |
7e390c9d | 2743 | @code{STACK_SAVEAREA_MODE} macro (@pxref{Storage Layout}). You must |
73c8090f DE |
2744 | specify an integral mode, or @code{VOIDmode} if no save area is needed |
2745 | for a particular type of save (either because no save is needed or | |
2746 | because a machine-specific save area can be used). Operand 0 is the | |
2747 | stack pointer and operand 1 is the save area for restore operations. If | |
2748 | @samp{save_stack_block} is defined, operand 0 must not be | |
2749 | @code{VOIDmode} since these saves can be arbitrarily nested. | |
03dda8e3 RK |
2750 | |
2751 | A save area is a @code{mem} that is at a constant offset from | |
2752 | @code{virtual_stack_vars_rtx} when the stack pointer is saved for use by | |
2753 | nonlocal gotos and a @code{reg} in the other two cases. | |
2754 | ||
2755 | @cindex @code{allocate_stack} instruction pattern | |
2756 | @item @samp{allocate_stack} | |
72938a4c | 2757 | Subtract (or add if @code{STACK_GROWS_DOWNWARD} is undefined) operand 1 from |
03dda8e3 RK |
2758 | the stack pointer to create space for dynamically allocated data. |
2759 | ||
72938a4c MM |
2760 | Store the resultant pointer to this space into operand 0. If you |
2761 | are allocating space from the main stack, do this by emitting a | |
2762 | move insn to copy @code{virtual_stack_dynamic_rtx} to operand 0. | |
2763 | If you are allocating the space elsewhere, generate code to copy the | |
2764 | location of the space to operand 0. In the latter case, you must | |
956d6950 | 2765 | ensure this space gets freed when the corresponding space on the main |
72938a4c MM |
2766 | stack is free. |
2767 | ||
03dda8e3 RK |
2768 | Do not define this pattern if all that must be done is the subtraction. |
2769 | Some machines require other operations such as stack probes or | |
2770 | maintaining the back chain. Define this pattern to emit those | |
2771 | operations in addition to updating the stack pointer. | |
2772 | ||
2773 | @cindex @code{probe} instruction pattern | |
2774 | @item @samp{probe} | |
2775 | Some machines require instructions to be executed after space is | |
2776 | allocated from the stack, for example to generate a reference at | |
2777 | the bottom of the stack. | |
2778 | ||
2779 | If you need to emit instructions before the stack has been adjusted, | |
2780 | put them into the @samp{allocate_stack} pattern. Otherwise, define | |
2781 | this pattern to emit the required instructions. | |
2782 | ||
2783 | No operands are provided. | |
2784 | ||
861bb6c1 JL |
2785 | @cindex @code{check_stack} instruction pattern |
2786 | @item @samp{check_stack} | |
2787 | If stack checking cannot be done on your system by probing the stack with | |
2788 | a load or store instruction (@pxref{Stack Checking}), define this pattern | |
2789 | to perform the needed check and signaling an error if the stack | |
2790 | has overflowed. The single operand is the location in the stack furthest | |
2791 | from the current stack pointer that you need to validate. Normally, | |
2792 | on machines where this pattern is needed, you would obtain the stack | |
2793 | limit from a global or thread-specific variable or register. | |
2794 | ||
03dda8e3 RK |
2795 | @cindex @code{nonlocal_goto} instruction pattern |
2796 | @item @samp{nonlocal_goto} | |
2797 | Emit code to generate a non-local goto, e.g., a jump from one function | |
2798 | to a label in an outer function. This pattern has four arguments, | |
2799 | each representing a value to be used in the jump. The first | |
45bb86fd | 2800 | argument is to be loaded into the frame pointer, the second is |
03dda8e3 RK |
2801 | the address to branch to (code to dispatch to the actual label), |
2802 | the third is the address of a location where the stack is saved, | |
2803 | and the last is the address of the label, to be placed in the | |
2804 | location for the incoming static chain. | |
2805 | ||
2806 | On most machines you need not define this pattern, since GNU CC will | |
2807 | already generate the correct code, which is to load the frame pointer | |
2808 | and static chain, restore the stack (using the | |
2809 | @samp{restore_stack_nonlocal} pattern, if defined), and jump indirectly | |
2810 | to the dispatcher. You need only define this pattern if this code will | |
2811 | not work on your machine. | |
2812 | ||
2813 | @cindex @code{nonlocal_goto_receiver} instruction pattern | |
2814 | @item @samp{nonlocal_goto_receiver} | |
2815 | This pattern, if defined, contains code needed at the target of a | |
2816 | nonlocal goto after the code already generated by GNU CC. You will not | |
2817 | normally need to define this pattern. A typical reason why you might | |
2818 | need this pattern is if some value, such as a pointer to a global table, | |
c30ddbc9 | 2819 | must be restored when the frame pointer is restored. Note that a nonlocal |
89bcce1b | 2820 | goto only occurs within a unit-of-translation, so a global table pointer |
c30ddbc9 RH |
2821 | that is shared by all functions of a given module need not be restored. |
2822 | There are no arguments. | |
861bb6c1 JL |
2823 | |
2824 | @cindex @code{exception_receiver} instruction pattern | |
2825 | @item @samp{exception_receiver} | |
2826 | This pattern, if defined, contains code needed at the site of an | |
2827 | exception handler that isn't needed at the site of a nonlocal goto. You | |
2828 | will not normally need to define this pattern. A typical reason why you | |
2829 | might need this pattern is if some value, such as a pointer to a global | |
2830 | table, must be restored after control flow is branched to the handler of | |
2831 | an exception. There are no arguments. | |
c85f7c16 | 2832 | |
c30ddbc9 RH |
2833 | @cindex @code{builtin_setjmp_setup} instruction pattern |
2834 | @item @samp{builtin_setjmp_setup} | |
2835 | This pattern, if defined, contains additional code needed to initialize | |
2836 | the @code{jmp_buf}. You will not normally need to define this pattern. | |
2837 | A typical reason why you might need this pattern is if some value, such | |
2838 | as a pointer to a global table, must be restored. Though it is | |
2839 | preferred that the pointer value be recalculated if possible (given the | |
2840 | address of a label for instance). The single argument is a pointer to | |
2841 | the @code{jmp_buf}. Note that the buffer is five words long and that | |
2842 | the first three are normally used by the generic mechanism. | |
2843 | ||
c85f7c16 JL |
2844 | @cindex @code{builtin_setjmp_receiver} instruction pattern |
2845 | @item @samp{builtin_setjmp_receiver} | |
2846 | This pattern, if defined, contains code needed at the site of an | |
2847 | builtin setjmp that isn't needed at the site of a nonlocal goto. You | |
2848 | will not normally need to define this pattern. A typical reason why you | |
2849 | might need this pattern is if some value, such as a pointer to a global | |
c30ddbc9 RH |
2850 | table, must be restored. It takes one argument, which is the label |
2851 | to which builtin_longjmp transfered control; this pattern may be emitted | |
2852 | at a small offset from that label. | |
2853 | ||
2854 | @cindex @code{builtin_longjmp} instruction pattern | |
2855 | @item @samp{builtin_longjmp} | |
2856 | This pattern, if defined, performs the entire action of the longjmp. | |
2857 | You will not normally need to define this pattern unless you also define | |
2858 | @code{builtin_setjmp_setup}. The single argument is a pointer to the | |
2859 | @code{jmp_buf}. | |
f69864aa | 2860 | |
52a11cbf RH |
2861 | @cindex @code{eh_return} instruction pattern |
2862 | @item @samp{eh_return} | |
f69864aa | 2863 | This pattern, if defined, affects the way @code{__builtin_eh_return}, |
52a11cbf RH |
2864 | and thence the call frame exception handling library routines, are |
2865 | built. It is intended to handle non-trivial actions needed along | |
2866 | the abnormal return path. | |
2867 | ||
2868 | The pattern takes two arguments. The first is an offset to be applied | |
2869 | to the stack pointer. It will have been copied to some appropriate | |
2870 | location (typically @code{EH_RETURN_STACKADJ_RTX}) which will survive | |
ebb48a4d | 2871 | until after reload to when the normal epilogue is generated. |
52a11cbf | 2872 | The second argument is the address of the exception handler to which |
f69864aa | 2873 | the function should return. This will normally need to copied by the |
52a11cbf | 2874 | pattern to some special register or memory location. |
f69864aa | 2875 | |
52a11cbf RH |
2876 | This pattern only needs to be defined if call frame exception handling |
2877 | is to be used, and simple moves to @code{EH_RETURN_STACKADJ_RTX} and | |
2878 | @code{EH_RETURN_HANDLER_RTX} are not sufficient. | |
0b433de6 JL |
2879 | |
2880 | @cindex @code{prologue} instruction pattern | |
2881 | @item @samp{prologue} | |
2882 | This pattern, if defined, emits RTL for entry to a function. The function | |
b192711e | 2883 | entry is responsible for setting up the stack frame, initializing the frame |
0b433de6 JL |
2884 | pointer register, saving callee saved registers, etc. |
2885 | ||
2886 | Using a prologue pattern is generally preferred over defining | |
2887 | @code{FUNCTION_PROLOGUE} to emit assembly code for the prologue. | |
2888 | ||
2889 | The @code{prologue} pattern is particularly useful for targets which perform | |
2890 | instruction scheduling. | |
2891 | ||
2892 | @cindex @code{epilogue} instruction pattern | |
2893 | @item @samp{epilogue} | |
2894 | This pattern, if defined, emits RTL for exit from a function. The function | |
b192711e | 2895 | exit is responsible for deallocating the stack frame, restoring callee saved |
0b433de6 JL |
2896 | registers and emitting the return instruction. |
2897 | ||
2898 | Using an epilogue pattern is generally preferred over defining | |
2899 | @code{FUNCTION_EPILOGUE} to emit assembly code for the prologue. | |
2900 | ||
2901 | The @code{epilogue} pattern is particularly useful for targets which perform | |
2902 | instruction scheduling or which have delay slots for their return instruction. | |
2903 | ||
2904 | @cindex @code{sibcall_epilogue} instruction pattern | |
2905 | @item @samp{sibcall_epilogue} | |
2906 | This pattern, if defined, emits RTL for exit from a function without the final | |
2907 | branch back to the calling function. This pattern will be emitted before any | |
2908 | sibling call (aka tail call) sites. | |
2909 | ||
2910 | The @code{sibcall_epilogue} pattern must not clobber any arguments used for | |
2911 | parameter passing or any stack slots for arguments passed to the current | |
ebb48a4d | 2912 | function. |
a157febd GK |
2913 | |
2914 | @cindex @code{trap} instruction pattern | |
2915 | @item @samp{trap} | |
2916 | This pattern, if defined, signals an error, typically by causing some | |
2917 | kind of signal to be raised. Among other places, it is used by the Java | |
2918 | frontend to signal `invalid array index' exceptions. | |
2919 | ||
2920 | @cindex @code{conditional_trap} instruction pattern | |
2921 | @item @samp{conditional_trap} | |
2922 | Conditional trap instruction. Operand 0 is a piece of RTL which | |
2923 | performs a comparison. Operand 1 is the trap code, an integer. | |
2924 | ||
2925 | A typical @code{conditional_trap} pattern looks like | |
2926 | ||
2927 | @smallexample | |
2928 | (define_insn "conditional_trap" | |
ebb48a4d | 2929 | [(trap_if (match_operator 0 "trap_operator" |
a157febd GK |
2930 | [(cc0) (const_int 0)]) |
2931 | (match_operand 1 "const_int_operand" "i"))] | |
2932 | "" | |
2933 | "@dots{}") | |
2934 | @end smallexample | |
2935 | ||
79c2ffde BS |
2936 | @cindex @code{cycle_display} instruction pattern |
2937 | @item @samp{cycle_display} | |
2938 | ||
2939 | This pattern, if present, will be emitted by the instruction scheduler at | |
2940 | the beginning of each new clock cycle. This can be used for annotating the | |
2941 | assembler output with cycle counts. Operand 0 is a @code{const_int} that | |
2942 | holds the clock cycle. | |
2943 | ||
03dda8e3 RK |
2944 | @end table |
2945 | ||
2946 | @node Pattern Ordering | |
2947 | @section When the Order of Patterns Matters | |
2948 | @cindex Pattern Ordering | |
2949 | @cindex Ordering of Patterns | |
2950 | ||
2951 | Sometimes an insn can match more than one instruction pattern. Then the | |
2952 | pattern that appears first in the machine description is the one used. | |
2953 | Therefore, more specific patterns (patterns that will match fewer things) | |
2954 | and faster instructions (those that will produce better code when they | |
2955 | do match) should usually go first in the description. | |
2956 | ||
2957 | In some cases the effect of ordering the patterns can be used to hide | |
2958 | a pattern when it is not valid. For example, the 68000 has an | |
2959 | instruction for converting a fullword to floating point and another | |
2960 | for converting a byte to floating point. An instruction converting | |
2961 | an integer to floating point could match either one. We put the | |
2962 | pattern to convert the fullword first to make sure that one will | |
2963 | be used rather than the other. (Otherwise a large integer might | |
2964 | be generated as a single-byte immediate quantity, which would not work.) | |
2965 | Instead of using this pattern ordering it would be possible to make the | |
2966 | pattern for convert-a-byte smart enough to deal properly with any | |
2967 | constant value. | |
2968 | ||
2969 | @node Dependent Patterns | |
2970 | @section Interdependence of Patterns | |
2971 | @cindex Dependent Patterns | |
2972 | @cindex Interdependence of Patterns | |
2973 | ||
2974 | Every machine description must have a named pattern for each of the | |
2975 | conditional branch names @samp{b@var{cond}}. The recognition template | |
2976 | must always have the form | |
2977 | ||
2978 | @example | |
2979 | (set (pc) | |
2980 | (if_then_else (@var{cond} (cc0) (const_int 0)) | |
2981 | (label_ref (match_operand 0 "" "")) | |
2982 | (pc))) | |
2983 | @end example | |
2984 | ||
2985 | @noindent | |
2986 | In addition, every machine description must have an anonymous pattern | |
2987 | for each of the possible reverse-conditional branches. Their templates | |
2988 | look like | |
2989 | ||
2990 | @example | |
2991 | (set (pc) | |
2992 | (if_then_else (@var{cond} (cc0) (const_int 0)) | |
2993 | (pc) | |
2994 | (label_ref (match_operand 0 "" "")))) | |
2995 | @end example | |
2996 | ||
2997 | @noindent | |
2998 | They are necessary because jump optimization can turn direct-conditional | |
2999 | branches into reverse-conditional branches. | |
3000 | ||
3001 | It is often convenient to use the @code{match_operator} construct to | |
3002 | reduce the number of patterns that must be specified for branches. For | |
3003 | example, | |
3004 | ||
3005 | @example | |
3006 | (define_insn "" | |
3007 | [(set (pc) | |
3008 | (if_then_else (match_operator 0 "comparison_operator" | |
3009 | [(cc0) (const_int 0)]) | |
3010 | (pc) | |
3011 | (label_ref (match_operand 1 "" ""))))] | |
3012 | "@var{condition}" | |
3013 | "@dots{}") | |
3014 | @end example | |
3015 | ||
3016 | In some cases machines support instructions identical except for the | |
3017 | machine mode of one or more operands. For example, there may be | |
3018 | ``sign-extend halfword'' and ``sign-extend byte'' instructions whose | |
3019 | patterns are | |
3020 | ||
3021 | @example | |
3022 | (set (match_operand:SI 0 @dots{}) | |
3023 | (extend:SI (match_operand:HI 1 @dots{}))) | |
3024 | ||
3025 | (set (match_operand:SI 0 @dots{}) | |
3026 | (extend:SI (match_operand:QI 1 @dots{}))) | |
3027 | @end example | |
3028 | ||
3029 | @noindent | |
3030 | Constant integers do not specify a machine mode, so an instruction to | |
3031 | extend a constant value could match either pattern. The pattern it | |
3032 | actually will match is the one that appears first in the file. For correct | |
3033 | results, this must be the one for the widest possible mode (@code{HImode}, | |
3034 | here). If the pattern matches the @code{QImode} instruction, the results | |
3035 | will be incorrect if the constant value does not actually fit that mode. | |
3036 | ||
3037 | Such instructions to extend constants are rarely generated because they are | |
3038 | optimized away, but they do occasionally happen in nonoptimized | |
3039 | compilations. | |
3040 | ||
3041 | If a constraint in a pattern allows a constant, the reload pass may | |
3042 | replace a register with a constant permitted by the constraint in some | |
3043 | cases. Similarly for memory references. Because of this substitution, | |
3044 | you should not provide separate patterns for increment and decrement | |
3045 | instructions. Instead, they should be generated from the same pattern | |
3046 | that supports register-register add insns by examining the operands and | |
3047 | generating the appropriate machine instruction. | |
3048 | ||
3049 | @node Jump Patterns | |
3050 | @section Defining Jump Instruction Patterns | |
3051 | @cindex jump instruction patterns | |
3052 | @cindex defining jump instruction patterns | |
3053 | ||
3054 | For most machines, GNU CC assumes that the machine has a condition code. | |
3055 | A comparison insn sets the condition code, recording the results of both | |
3056 | signed and unsigned comparison of the given operands. A separate branch | |
3057 | insn tests the condition code and branches or not according its value. | |
3058 | The branch insns come in distinct signed and unsigned flavors. Many | |
3059 | common machines, such as the Vax, the 68000 and the 32000, work this | |
3060 | way. | |
3061 | ||
3062 | Some machines have distinct signed and unsigned compare instructions, and | |
3063 | only one set of conditional branch instructions. The easiest way to handle | |
3064 | these machines is to treat them just like the others until the final stage | |
3065 | where assembly code is written. At this time, when outputting code for the | |
3066 | compare instruction, peek ahead at the following branch using | |
3067 | @code{next_cc0_user (insn)}. (The variable @code{insn} refers to the insn | |
3068 | being output, in the output-writing code in an instruction pattern.) If | |
3069 | the RTL says that is an unsigned branch, output an unsigned compare; | |
3070 | otherwise output a signed compare. When the branch itself is output, you | |
3071 | can treat signed and unsigned branches identically. | |
3072 | ||
3073 | The reason you can do this is that GNU CC always generates a pair of | |
3074 | consecutive RTL insns, possibly separated by @code{note} insns, one to | |
3075 | set the condition code and one to test it, and keeps the pair inviolate | |
3076 | until the end. | |
3077 | ||
3078 | To go with this technique, you must define the machine-description macro | |
3079 | @code{NOTICE_UPDATE_CC} to do @code{CC_STATUS_INIT}; in other words, no | |
3080 | compare instruction is superfluous. | |
3081 | ||
3082 | Some machines have compare-and-branch instructions and no condition code. | |
3083 | A similar technique works for them. When it is time to ``output'' a | |
3084 | compare instruction, record its operands in two static variables. When | |
3085 | outputting the branch-on-condition-code instruction that follows, actually | |
3086 | output a compare-and-branch instruction that uses the remembered operands. | |
3087 | ||
3088 | It also works to define patterns for compare-and-branch instructions. | |
3089 | In optimizing compilation, the pair of compare and branch instructions | |
3090 | will be combined according to these patterns. But this does not happen | |
3091 | if optimization is not requested. So you must use one of the solutions | |
3092 | above in addition to any special patterns you define. | |
3093 | ||
3094 | In many RISC machines, most instructions do not affect the condition | |
3095 | code and there may not even be a separate condition code register. On | |
3096 | these machines, the restriction that the definition and use of the | |
3097 | condition code be adjacent insns is not necessary and can prevent | |
3098 | important optimizations. For example, on the IBM RS/6000, there is a | |
3099 | delay for taken branches unless the condition code register is set three | |
3100 | instructions earlier than the conditional branch. The instruction | |
3101 | scheduler cannot perform this optimization if it is not permitted to | |
3102 | separate the definition and use of the condition code register. | |
3103 | ||
3104 | On these machines, do not use @code{(cc0)}, but instead use a register | |
3105 | to represent the condition code. If there is a specific condition code | |
3106 | register in the machine, use a hard register. If the condition code or | |
3107 | comparison result can be placed in any general register, or if there are | |
3108 | multiple condition registers, use a pseudo register. | |
3109 | ||
3110 | @findex prev_cc0_setter | |
3111 | @findex next_cc0_user | |
3112 | On some machines, the type of branch instruction generated may depend on | |
3113 | the way the condition code was produced; for example, on the 68k and | |
3114 | Sparc, setting the condition code directly from an add or subtract | |
3115 | instruction does not clear the overflow bit the way that a test | |
3116 | instruction does, so a different branch instruction must be used for | |
3117 | some conditional branches. For machines that use @code{(cc0)}, the set | |
3118 | and use of the condition code must be adjacent (separated only by | |
3119 | @code{note} insns) allowing flags in @code{cc_status} to be used. | |
3120 | (@xref{Condition Code}.) Also, the comparison and branch insns can be | |
3121 | located from each other by using the functions @code{prev_cc0_setter} | |
3122 | and @code{next_cc0_user}. | |
3123 | ||
3124 | However, this is not true on machines that do not use @code{(cc0)}. On | |
3125 | those machines, no assumptions can be made about the adjacency of the | |
3126 | compare and branch insns and the above methods cannot be used. Instead, | |
3127 | we use the machine mode of the condition code register to record | |
3128 | different formats of the condition code register. | |
3129 | ||
3130 | Registers used to store the condition code value should have a mode that | |
3131 | is in class @code{MODE_CC}. Normally, it will be @code{CCmode}. If | |
3132 | additional modes are required (as for the add example mentioned above in | |
3133 | the Sparc), define the macro @code{EXTRA_CC_MODES} to list the | |
3134 | additional modes required (@pxref{Condition Code}). Also define | |
03dda8e3 RK |
3135 | @code{SELECT_CC_MODE} to choose a mode given an operand of a compare. |
3136 | ||
3137 | If it is known during RTL generation that a different mode will be | |
3138 | required (for example, if the machine has separate compare instructions | |
3139 | for signed and unsigned quantities, like most IBM processors), they can | |
3140 | be specified at that time. | |
3141 | ||
3142 | If the cases that require different modes would be made by instruction | |
3143 | combination, the macro @code{SELECT_CC_MODE} determines which machine | |
3144 | mode should be used for the comparison result. The patterns should be | |
3145 | written using that mode. To support the case of the add on the Sparc | |
3146 | discussed above, we have the pattern | |
3147 | ||
3148 | @smallexample | |
3149 | (define_insn "" | |
3150 | [(set (reg:CC_NOOV 0) | |
3151 | (compare:CC_NOOV | |
3152 | (plus:SI (match_operand:SI 0 "register_operand" "%r") | |
3153 | (match_operand:SI 1 "arith_operand" "rI")) | |
3154 | (const_int 0)))] | |
3155 | "" | |
3156 | "@dots{}") | |
3157 | @end smallexample | |
3158 | ||
3159 | The @code{SELECT_CC_MODE} macro on the Sparc returns @code{CC_NOOVmode} | |
3160 | for comparisons whose argument is a @code{plus}. | |
3161 | ||
6e4fcc95 MH |
3162 | @node Looping Patterns |
3163 | @section Defining Looping Instruction Patterns | |
3164 | @cindex looping instruction patterns | |
3165 | @cindex defining looping instruction patterns | |
3166 | ||
3167 | Some machines have special jump instructions that can be utilised to | |
3168 | make loops more efficient. A common example is the 68000 @samp{dbra} | |
3169 | instruction which performs a decrement of a register and a branch if the | |
3170 | result was greater than zero. Other machines, in particular digital | |
3171 | signal processors (DSPs), have special block repeat instructions to | |
3172 | provide low-overhead loop support. For example, the TI TMS320C3x/C4x | |
3173 | DSPs have a block repeat instruction that loads special registers to | |
3174 | mark the top and end of a loop and to count the number of loop | |
3175 | iterations. This avoids the need for fetching and executing a | |
3176 | @samp{dbra}-like instruction and avoids pipeline stalls asociated with | |
3177 | the jump. | |
3178 | ||
3179 | GNU CC has three special named patterns to support low overhead looping, | |
3180 | @samp{decrement_and_branch_until_zero}, @samp{doloop_begin}, and | |
3181 | @samp{doloop_end}. The first pattern, | |
3182 | @samp{decrement_and_branch_until_zero}, is not emitted during RTL | |
3183 | generation but may be emitted during the instruction combination phase. | |
3184 | This requires the assistance of the loop optimizer, using information | |
3185 | collected during strength reduction, to reverse a loop to count down to | |
3186 | zero. Some targets also require the loop optimizer to add a | |
3187 | @code{REG_NONNEG} note to indicate that the iteration count is always | |
3188 | positive. This is needed if the target performs a signed loop | |
3189 | termination test. For example, the 68000 uses a pattern similar to the | |
3190 | following for its @code{dbra} instruction: | |
3191 | ||
3192 | @smallexample | |
3193 | @group | |
3194 | (define_insn "decrement_and_branch_until_zero" | |
3195 | [(set (pc) | |
3196 | (if_then_else | |
3197 | (ge (plus:SI (match_operand:SI 0 "general_operand" "+d*am") | |
3198 | (const_int -1)) | |
3199 | (const_int 0)) | |
3200 | (label_ref (match_operand 1 "" "")) | |
3201 | (pc))) | |
3202 | (set (match_dup 0) | |
3203 | (plus:SI (match_dup 0) | |
3204 | (const_int -1)))] | |
3205 | "find_reg_note (insn, REG_NONNEG, 0)" | |
3206 | "...") | |
3207 | @end group | |
3208 | @end smallexample | |
3209 | ||
3210 | Note that since the insn is both a jump insn and has an output, it must | |
3211 | deal with its own reloads, hence the `m' constraints. Also note that | |
3212 | since this insn is generated by the instruction combination phase | |
3213 | combining two sequential insns together into an implicit parallel insn, | |
3214 | the iteration counter needs to be biased by the same amount as the | |
3215 | decrement operation, in this case -1. Note that the following similar | |
3216 | pattern will not be matched by the combiner. | |
3217 | ||
3218 | @smallexample | |
3219 | @group | |
3220 | (define_insn "decrement_and_branch_until_zero" | |
3221 | [(set (pc) | |
3222 | (if_then_else | |
3223 | (ge (match_operand:SI 0 "general_operand" "+d*am") | |
3224 | (const_int 1)) | |
3225 | (label_ref (match_operand 1 "" "")) | |
3226 | (pc))) | |
3227 | (set (match_dup 0) | |
3228 | (plus:SI (match_dup 0) | |
3229 | (const_int -1)))] | |
3230 | "find_reg_note (insn, REG_NONNEG, 0)" | |
3231 | "...") | |
3232 | @end group | |
3233 | @end smallexample | |
3234 | ||
3235 | The other two special looping patterns, @samp{doloop_begin} and | |
3236 | @samp{doloop_end}, are emitted by the loop optimiser for certain | |
3237 | well-behaved loops with a finite number of loop iterations using | |
ebb48a4d | 3238 | information collected during strength reduction. |
6e4fcc95 MH |
3239 | |
3240 | The @samp{doloop_end} pattern describes the actual looping instruction | |
3241 | (or the implicit looping operation) and the @samp{doloop_begin} pattern | |
3242 | is an optional companion pattern that can be used for initialisation | |
3243 | needed for some low-overhead looping instructions. | |
3244 | ||
3245 | Note that some machines require the actual looping instruction to be | |
3246 | emitted at the top of the loop (e.g., the TMS320C3x/C4x DSPs). Emitting | |
3247 | the true RTL for a looping instruction at the top of the loop can cause | |
3248 | problems with flow analysis. So instead, a dummy @code{doloop} insn is | |
3249 | emitted at the end of the loop. The machine dependent reorg pass checks | |
3250 | for the presence of this @code{doloop} insn and then searches back to | |
3251 | the top of the loop, where it inserts the true looping insn (provided | |
3252 | there are no instructions in the loop which would cause problems). Any | |
3253 | additional labels can be emitted at this point. In addition, if the | |
3254 | desired special iteration counter register was not allocated, this | |
3255 | machine dependent reorg pass could emit a traditional compare and jump | |
3256 | instruction pair. | |
3257 | ||
3258 | The essential difference between the | |
3259 | @samp{decrement_and_branch_until_zero} and the @samp{doloop_end} | |
3260 | patterns is that the loop optimizer allocates an additional pseudo | |
3261 | register for the latter as an iteration counter. This pseudo register | |
3262 | cannot be used within the loop (i.e., general induction variables cannot | |
3263 | be derived from it), however, in many cases the loop induction variable | |
3264 | may become redundant and removed by the flow pass. | |
3265 | ||
3266 | ||
03dda8e3 RK |
3267 | @node Insn Canonicalizations |
3268 | @section Canonicalization of Instructions | |
3269 | @cindex canonicalization of instructions | |
3270 | @cindex insn canonicalization | |
3271 | ||
3272 | There are often cases where multiple RTL expressions could represent an | |
3273 | operation performed by a single machine instruction. This situation is | |
3274 | most commonly encountered with logical, branch, and multiply-accumulate | |
3275 | instructions. In such cases, the compiler attempts to convert these | |
3276 | multiple RTL expressions into a single canonical form to reduce the | |
3277 | number of insn patterns required. | |
3278 | ||
3279 | In addition to algebraic simplifications, following canonicalizations | |
3280 | are performed: | |
3281 | ||
3282 | @itemize @bullet | |
3283 | @item | |
3284 | For commutative and comparison operators, a constant is always made the | |
3285 | second operand. If a machine only supports a constant as the second | |
3286 | operand, only patterns that match a constant in the second operand need | |
3287 | be supplied. | |
3288 | ||
3289 | @cindex @code{neg}, canonicalization of | |
3290 | @cindex @code{not}, canonicalization of | |
3291 | @cindex @code{mult}, canonicalization of | |
3292 | @cindex @code{plus}, canonicalization of | |
3293 | @cindex @code{minus}, canonicalization of | |
3294 | For these operators, if only one operand is a @code{neg}, @code{not}, | |
3295 | @code{mult}, @code{plus}, or @code{minus} expression, it will be the | |
3296 | first operand. | |
3297 | ||
3298 | @cindex @code{compare}, canonicalization of | |
3299 | @item | |
3300 | For the @code{compare} operator, a constant is always the second operand | |
3301 | on machines where @code{cc0} is used (@pxref{Jump Patterns}). On other | |
3302 | machines, there are rare cases where the compiler might want to construct | |
3303 | a @code{compare} with a constant as the first operand. However, these | |
3304 | cases are not common enough for it to be worthwhile to provide a pattern | |
3305 | matching a constant as the first operand unless the machine actually has | |
3306 | such an instruction. | |
3307 | ||
3308 | An operand of @code{neg}, @code{not}, @code{mult}, @code{plus}, or | |
3309 | @code{minus} is made the first operand under the same conditions as | |
3310 | above. | |
3311 | ||
3312 | @item | |
3313 | @code{(minus @var{x} (const_int @var{n}))} is converted to | |
3314 | @code{(plus @var{x} (const_int @var{-n}))}. | |
3315 | ||
3316 | @item | |
3317 | Within address computations (i.e., inside @code{mem}), a left shift is | |
3318 | converted into the appropriate multiplication by a power of two. | |
3319 | ||
3320 | @cindex @code{ior}, canonicalization of | |
3321 | @cindex @code{and}, canonicalization of | |
3322 | @cindex De Morgan's law | |
72938a4c | 3323 | @item |
03dda8e3 RK |
3324 | De`Morgan's Law is used to move bitwise negation inside a bitwise |
3325 | logical-and or logical-or operation. If this results in only one | |
3326 | operand being a @code{not} expression, it will be the first one. | |
3327 | ||
3328 | A machine that has an instruction that performs a bitwise logical-and of one | |
3329 | operand with the bitwise negation of the other should specify the pattern | |
3330 | for that instruction as | |
3331 | ||
3332 | @example | |
3333 | (define_insn "" | |
3334 | [(set (match_operand:@var{m} 0 @dots{}) | |
3335 | (and:@var{m} (not:@var{m} (match_operand:@var{m} 1 @dots{})) | |
3336 | (match_operand:@var{m} 2 @dots{})))] | |
3337 | "@dots{}" | |
3338 | "@dots{}") | |
3339 | @end example | |
3340 | ||
3341 | @noindent | |
3342 | Similarly, a pattern for a ``NAND'' instruction should be written | |
3343 | ||
3344 | @example | |
3345 | (define_insn "" | |
3346 | [(set (match_operand:@var{m} 0 @dots{}) | |
3347 | (ior:@var{m} (not:@var{m} (match_operand:@var{m} 1 @dots{})) | |
3348 | (not:@var{m} (match_operand:@var{m} 2 @dots{}))))] | |
3349 | "@dots{}" | |
3350 | "@dots{}") | |
3351 | @end example | |
3352 | ||
3353 | In both cases, it is not necessary to include patterns for the many | |
3354 | logically equivalent RTL expressions. | |
3355 | ||
3356 | @cindex @code{xor}, canonicalization of | |
3357 | @item | |
3358 | The only possible RTL expressions involving both bitwise exclusive-or | |
3359 | and bitwise negation are @code{(xor:@var{m} @var{x} @var{y})} | |
3360 | and @code{(not:@var{m} (xor:@var{m} @var{x} @var{y}))}.@refill | |
3361 | ||
3362 | @item | |
3363 | The sum of three items, one of which is a constant, will only appear in | |
3364 | the form | |
3365 | ||
3366 | @example | |
3367 | (plus:@var{m} (plus:@var{m} @var{x} @var{y}) @var{constant}) | |
3368 | @end example | |
3369 | ||
3370 | @item | |
3371 | On machines that do not use @code{cc0}, | |
3372 | @code{(compare @var{x} (const_int 0))} will be converted to | |
3373 | @var{x}.@refill | |
3374 | ||
3375 | @cindex @code{zero_extract}, canonicalization of | |
3376 | @cindex @code{sign_extract}, canonicalization of | |
3377 | @item | |
3378 | Equality comparisons of a group of bits (usually a single bit) with zero | |
3379 | will be written using @code{zero_extract} rather than the equivalent | |
3380 | @code{and} or @code{sign_extract} operations. | |
3381 | ||
3382 | @end itemize | |
3383 | ||
03dda8e3 RK |
3384 | @node Expander Definitions |
3385 | @section Defining RTL Sequences for Code Generation | |
3386 | @cindex expander definitions | |
3387 | @cindex code generation RTL sequences | |
3388 | @cindex defining RTL sequences for code generation | |
3389 | ||
3390 | On some target machines, some standard pattern names for RTL generation | |
3391 | cannot be handled with single insn, but a sequence of RTL insns can | |
3392 | represent them. For these target machines, you can write a | |
3393 | @code{define_expand} to specify how to generate the sequence of RTL. | |
3394 | ||
3395 | @findex define_expand | |
3396 | A @code{define_expand} is an RTL expression that looks almost like a | |
3397 | @code{define_insn}; but, unlike the latter, a @code{define_expand} is used | |
3398 | only for RTL generation and it can produce more than one RTL insn. | |
3399 | ||
3400 | A @code{define_expand} RTX has four operands: | |
3401 | ||
3402 | @itemize @bullet | |
3403 | @item | |
3404 | The name. Each @code{define_expand} must have a name, since the only | |
3405 | use for it is to refer to it by name. | |
3406 | ||
03dda8e3 | 3407 | @item |
f3a3d0d3 RH |
3408 | The RTL template. This is a vector of RTL expressions representing |
3409 | a sequence of separate instructions. Unlike @code{define_insn}, there | |
3410 | is no implicit surrounding @code{PARALLEL}. | |
03dda8e3 RK |
3411 | |
3412 | @item | |
3413 | The condition, a string containing a C expression. This expression is | |
3414 | used to express how the availability of this pattern depends on | |
3415 | subclasses of target machine, selected by command-line options when GNU | |
3416 | CC is run. This is just like the condition of a @code{define_insn} that | |
3417 | has a standard name. Therefore, the condition (if present) may not | |
3418 | depend on the data in the insn being matched, but only the | |
3419 | target-machine-type flags. The compiler needs to test these conditions | |
3420 | during initialization in order to learn exactly which named instructions | |
3421 | are available in a particular run. | |
3422 | ||
3423 | @item | |
3424 | The preparation statements, a string containing zero or more C | |
3425 | statements which are to be executed before RTL code is generated from | |
3426 | the RTL template. | |
3427 | ||
3428 | Usually these statements prepare temporary registers for use as | |
3429 | internal operands in the RTL template, but they can also generate RTL | |
3430 | insns directly by calling routines such as @code{emit_insn}, etc. | |
3431 | Any such insns precede the ones that come from the RTL template. | |
3432 | @end itemize | |
3433 | ||
3434 | Every RTL insn emitted by a @code{define_expand} must match some | |
3435 | @code{define_insn} in the machine description. Otherwise, the compiler | |
3436 | will crash when trying to generate code for the insn or trying to optimize | |
3437 | it. | |
3438 | ||
3439 | The RTL template, in addition to controlling generation of RTL insns, | |
3440 | also describes the operands that need to be specified when this pattern | |
3441 | is used. In particular, it gives a predicate for each operand. | |
3442 | ||
3443 | A true operand, which needs to be specified in order to generate RTL from | |
3444 | the pattern, should be described with a @code{match_operand} in its first | |
3445 | occurrence in the RTL template. This enters information on the operand's | |
3446 | predicate into the tables that record such things. GNU CC uses the | |
3447 | information to preload the operand into a register if that is required for | |
3448 | valid RTL code. If the operand is referred to more than once, subsequent | |
3449 | references should use @code{match_dup}. | |
3450 | ||
3451 | The RTL template may also refer to internal ``operands'' which are | |
3452 | temporary registers or labels used only within the sequence made by the | |
3453 | @code{define_expand}. Internal operands are substituted into the RTL | |
3454 | template with @code{match_dup}, never with @code{match_operand}. The | |
3455 | values of the internal operands are not passed in as arguments by the | |
3456 | compiler when it requests use of this pattern. Instead, they are computed | |
3457 | within the pattern, in the preparation statements. These statements | |
3458 | compute the values and store them into the appropriate elements of | |
3459 | @code{operands} so that @code{match_dup} can find them. | |
3460 | ||
3461 | There are two special macros defined for use in the preparation statements: | |
3462 | @code{DONE} and @code{FAIL}. Use them with a following semicolon, | |
3463 | as a statement. | |
3464 | ||
3465 | @table @code | |
3466 | ||
3467 | @findex DONE | |
3468 | @item DONE | |
3469 | Use the @code{DONE} macro to end RTL generation for the pattern. The | |
3470 | only RTL insns resulting from the pattern on this occasion will be | |
3471 | those already emitted by explicit calls to @code{emit_insn} within the | |
3472 | preparation statements; the RTL template will not be generated. | |
3473 | ||
3474 | @findex FAIL | |
3475 | @item FAIL | |
3476 | Make the pattern fail on this occasion. When a pattern fails, it means | |
3477 | that the pattern was not truly available. The calling routines in the | |
3478 | compiler will try other strategies for code generation using other patterns. | |
3479 | ||
3480 | Failure is currently supported only for binary (addition, multiplication, | |
3481 | shifting, etc.) and bitfield (@code{extv}, @code{extzv}, and @code{insv}) | |
3482 | operations. | |
3483 | @end table | |
3484 | ||
55e4756f DD |
3485 | If the preparation falls through (invokes neither @code{DONE} nor |
3486 | @code{FAIL}), then the @code{define_expand} acts like a | |
3487 | @code{define_insn} in that the RTL template is used to generate the | |
3488 | insn. | |
3489 | ||
3490 | The RTL template is not used for matching, only for generating the | |
3491 | initial insn list. If the preparation statement always invokes | |
3492 | @code{DONE} or @code{FAIL}, the RTL template may be reduced to a simple | |
3493 | list of operands, such as this example: | |
3494 | ||
3495 | @smallexample | |
3496 | @group | |
3497 | (define_expand "addsi3" | |
3498 | [(match_operand:SI 0 "register_operand" "") | |
3499 | (match_operand:SI 1 "register_operand" "") | |
3500 | (match_operand:SI 2 "register_operand" "")] | |
3501 | @end group | |
3502 | @group | |
3503 | "" | |
3504 | " | |
58097133 | 3505 | @{ |
55e4756f DD |
3506 | handle_add (operands[0], operands[1], operands[2]); |
3507 | DONE; | |
58097133 | 3508 | @}") |
55e4756f DD |
3509 | @end group |
3510 | @end smallexample | |
3511 | ||
03dda8e3 RK |
3512 | Here is an example, the definition of left-shift for the SPUR chip: |
3513 | ||
3514 | @smallexample | |
3515 | @group | |
3516 | (define_expand "ashlsi3" | |
3517 | [(set (match_operand:SI 0 "register_operand" "") | |
3518 | (ashift:SI | |
3519 | @end group | |
3520 | @group | |
3521 | (match_operand:SI 1 "register_operand" "") | |
3522 | (match_operand:SI 2 "nonmemory_operand" "")))] | |
3523 | "" | |
3524 | " | |
3525 | @end group | |
3526 | @end smallexample | |
3527 | ||
3528 | @smallexample | |
3529 | @group | |
3530 | @{ | |
3531 | if (GET_CODE (operands[2]) != CONST_INT | |
3532 | || (unsigned) INTVAL (operands[2]) > 3) | |
3533 | FAIL; | |
3534 | @}") | |
3535 | @end group | |
3536 | @end smallexample | |
3537 | ||
3538 | @noindent | |
3539 | This example uses @code{define_expand} so that it can generate an RTL insn | |
3540 | for shifting when the shift-count is in the supported range of 0 to 3 but | |
3541 | fail in other cases where machine insns aren't available. When it fails, | |
3542 | the compiler tries another strategy using different patterns (such as, a | |
3543 | library call). | |
3544 | ||
3545 | If the compiler were able to handle nontrivial condition-strings in | |
3546 | patterns with names, then it would be possible to use a | |
3547 | @code{define_insn} in that case. Here is another case (zero-extension | |
3548 | on the 68000) which makes more use of the power of @code{define_expand}: | |
3549 | ||
3550 | @smallexample | |
3551 | (define_expand "zero_extendhisi2" | |
3552 | [(set (match_operand:SI 0 "general_operand" "") | |
3553 | (const_int 0)) | |
3554 | (set (strict_low_part | |
3555 | (subreg:HI | |
3556 | (match_dup 0) | |
3557 | 0)) | |
3558 | (match_operand:HI 1 "general_operand" ""))] | |
3559 | "" | |
3560 | "operands[1] = make_safe_from (operands[1], operands[0]);") | |
3561 | @end smallexample | |
3562 | ||
3563 | @noindent | |
3564 | @findex make_safe_from | |
3565 | Here two RTL insns are generated, one to clear the entire output operand | |
3566 | and the other to copy the input operand into its low half. This sequence | |
3567 | is incorrect if the input operand refers to [the old value of] the output | |
3568 | operand, so the preparation statement makes sure this isn't so. The | |
3569 | function @code{make_safe_from} copies the @code{operands[1]} into a | |
3570 | temporary register if it refers to @code{operands[0]}. It does this | |
3571 | by emitting another RTL insn. | |
3572 | ||
3573 | Finally, a third example shows the use of an internal operand. | |
3574 | Zero-extension on the SPUR chip is done by @code{and}-ing the result | |
3575 | against a halfword mask. But this mask cannot be represented by a | |
3576 | @code{const_int} because the constant value is too large to be legitimate | |
3577 | on this machine. So it must be copied into a register with | |
3578 | @code{force_reg} and then the register used in the @code{and}. | |
3579 | ||
3580 | @smallexample | |
3581 | (define_expand "zero_extendhisi2" | |
3582 | [(set (match_operand:SI 0 "register_operand" "") | |
3583 | (and:SI (subreg:SI | |
3584 | (match_operand:HI 1 "register_operand" "") | |
3585 | 0) | |
3586 | (match_dup 2)))] | |
3587 | "" | |
3588 | "operands[2] | |
3a598fbe | 3589 | = force_reg (SImode, GEN_INT (65535)); ") |
03dda8e3 RK |
3590 | @end smallexample |
3591 | ||
3592 | @strong{Note:} If the @code{define_expand} is used to serve a | |
3593 | standard binary or unary arithmetic operation or a bitfield operation, | |
3594 | then the last insn it generates must not be a @code{code_label}, | |
3595 | @code{barrier} or @code{note}. It must be an @code{insn}, | |
3596 | @code{jump_insn} or @code{call_insn}. If you don't need a real insn | |
3597 | at the end, emit an insn to copy the result of the operation into | |
3598 | itself. Such an insn will generate no code, but it can avoid problems | |
3599 | in the compiler.@refill | |
3600 | ||
3601 | @node Insn Splitting | |
3602 | @section Defining How to Split Instructions | |
3603 | @cindex insn splitting | |
3604 | @cindex instruction splitting | |
3605 | @cindex splitting instructions | |
3606 | ||
3607 | There are two cases where you should specify how to split a pattern into | |
3608 | multiple insns. On machines that have instructions requiring delay | |
3609 | slots (@pxref{Delay Slots}) or that have instructions whose output is | |
3610 | not available for multiple cycles (@pxref{Function Units}), the compiler | |
3611 | phases that optimize these cases need to be able to move insns into | |
3612 | one-instruction delay slots. However, some insns may generate more than one | |
3613 | machine instruction. These insns cannot be placed into a delay slot. | |
3614 | ||
3615 | Often you can rewrite the single insn as a list of individual insns, | |
3616 | each corresponding to one machine instruction. The disadvantage of | |
3617 | doing so is that it will cause the compilation to be slower and require | |
3618 | more space. If the resulting insns are too complex, it may also | |
3619 | suppress some optimizations. The compiler splits the insn if there is a | |
3620 | reason to believe that it might improve instruction or delay slot | |
3621 | scheduling. | |
3622 | ||
3623 | The insn combiner phase also splits putative insns. If three insns are | |
3624 | merged into one insn with a complex expression that cannot be matched by | |
3625 | some @code{define_insn} pattern, the combiner phase attempts to split | |
3626 | the complex pattern into two insns that are recognized. Usually it can | |
3627 | break the complex pattern into two patterns by splitting out some | |
3628 | subexpression. However, in some other cases, such as performing an | |
3629 | addition of a large constant in two insns on a RISC machine, the way to | |
3630 | split the addition into two insns is machine-dependent. | |
3631 | ||
f3a3d0d3 | 3632 | @findex define_split |
03dda8e3 RK |
3633 | The @code{define_split} definition tells the compiler how to split a |
3634 | complex insn into several simpler insns. It looks like this: | |
3635 | ||
3636 | @smallexample | |
3637 | (define_split | |
3638 | [@var{insn-pattern}] | |
3639 | "@var{condition}" | |
3640 | [@var{new-insn-pattern-1} | |
3641 | @var{new-insn-pattern-2} | |
3642 | @dots{}] | |
3643 | "@var{preparation statements}") | |
3644 | @end smallexample | |
3645 | ||
3646 | @var{insn-pattern} is a pattern that needs to be split and | |
3647 | @var{condition} is the final condition to be tested, as in a | |
3648 | @code{define_insn}. When an insn matching @var{insn-pattern} and | |
3649 | satisfying @var{condition} is found, it is replaced in the insn list | |
3650 | with the insns given by @var{new-insn-pattern-1}, | |
3651 | @var{new-insn-pattern-2}, etc. | |
3652 | ||
3653 | The @var{preparation statements} are similar to those statements that | |
3654 | are specified for @code{define_expand} (@pxref{Expander Definitions}) | |
3655 | and are executed before the new RTL is generated to prepare for the | |
3656 | generated code or emit some insns whose pattern is not fixed. Unlike | |
3657 | those in @code{define_expand}, however, these statements must not | |
3658 | generate any new pseudo-registers. Once reload has completed, they also | |
3659 | must not allocate any space in the stack frame. | |
3660 | ||
3661 | Patterns are matched against @var{insn-pattern} in two different | |
3662 | circumstances. If an insn needs to be split for delay slot scheduling | |
3663 | or insn scheduling, the insn is already known to be valid, which means | |
3664 | that it must have been matched by some @code{define_insn} and, if | |
3665 | @code{reload_completed} is non-zero, is known to satisfy the constraints | |
3666 | of that @code{define_insn}. In that case, the new insn patterns must | |
3667 | also be insns that are matched by some @code{define_insn} and, if | |
3668 | @code{reload_completed} is non-zero, must also satisfy the constraints | |
3669 | of those definitions. | |
3670 | ||
3671 | As an example of this usage of @code{define_split}, consider the following | |
3672 | example from @file{a29k.md}, which splits a @code{sign_extend} from | |
3673 | @code{HImode} to @code{SImode} into a pair of shift insns: | |
3674 | ||
3675 | @smallexample | |
3676 | (define_split | |
3677 | [(set (match_operand:SI 0 "gen_reg_operand" "") | |
3678 | (sign_extend:SI (match_operand:HI 1 "gen_reg_operand" "")))] | |
3679 | "" | |
3680 | [(set (match_dup 0) | |
3681 | (ashift:SI (match_dup 1) | |
3682 | (const_int 16))) | |
3683 | (set (match_dup 0) | |
3684 | (ashiftrt:SI (match_dup 0) | |
3685 | (const_int 16)))] | |
3686 | " | |
3687 | @{ operands[1] = gen_lowpart (SImode, operands[1]); @}") | |
3688 | @end smallexample | |
3689 | ||
3690 | When the combiner phase tries to split an insn pattern, it is always the | |
3691 | case that the pattern is @emph{not} matched by any @code{define_insn}. | |
3692 | The combiner pass first tries to split a single @code{set} expression | |
3693 | and then the same @code{set} expression inside a @code{parallel}, but | |
3694 | followed by a @code{clobber} of a pseudo-reg to use as a scratch | |
3695 | register. In these cases, the combiner expects exactly two new insn | |
3696 | patterns to be generated. It will verify that these patterns match some | |
3697 | @code{define_insn} definitions, so you need not do this test in the | |
3698 | @code{define_split} (of course, there is no point in writing a | |
3699 | @code{define_split} that will never produce insns that match). | |
3700 | ||
3701 | Here is an example of this use of @code{define_split}, taken from | |
3702 | @file{rs6000.md}: | |
3703 | ||
3704 | @smallexample | |
3705 | (define_split | |
3706 | [(set (match_operand:SI 0 "gen_reg_operand" "") | |
3707 | (plus:SI (match_operand:SI 1 "gen_reg_operand" "") | |
3708 | (match_operand:SI 2 "non_add_cint_operand" "")))] | |
3709 | "" | |
3710 | [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3))) | |
3711 | (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))] | |
3712 | " | |
3713 | @{ | |
3714 | int low = INTVAL (operands[2]) & 0xffff; | |
3715 | int high = (unsigned) INTVAL (operands[2]) >> 16; | |
3716 | ||
3717 | if (low & 0x8000) | |
3718 | high++, low |= 0xffff0000; | |
3719 | ||
3a598fbe JL |
3720 | operands[3] = GEN_INT (high << 16); |
3721 | operands[4] = GEN_INT (low); | |
03dda8e3 RK |
3722 | @}") |
3723 | @end smallexample | |
3724 | ||
3725 | Here the predicate @code{non_add_cint_operand} matches any | |
3726 | @code{const_int} that is @emph{not} a valid operand of a single add | |
3727 | insn. The add with the smaller displacement is written so that it | |
3728 | can be substituted into the address of a subsequent operation. | |
3729 | ||
3730 | An example that uses a scratch register, from the same file, generates | |
3731 | an equality comparison of a register and a large constant: | |
3732 | ||
3733 | @smallexample | |
3734 | (define_split | |
3735 | [(set (match_operand:CC 0 "cc_reg_operand" "") | |
3736 | (compare:CC (match_operand:SI 1 "gen_reg_operand" "") | |
3737 | (match_operand:SI 2 "non_short_cint_operand" ""))) | |
3738 | (clobber (match_operand:SI 3 "gen_reg_operand" ""))] | |
3739 | "find_single_use (operands[0], insn, 0) | |
3740 | && (GET_CODE (*find_single_use (operands[0], insn, 0)) == EQ | |
3741 | || GET_CODE (*find_single_use (operands[0], insn, 0)) == NE)" | |
3742 | [(set (match_dup 3) (xor:SI (match_dup 1) (match_dup 4))) | |
3743 | (set (match_dup 0) (compare:CC (match_dup 3) (match_dup 5)))] | |
3744 | " | |
3745 | @{ | |
3746 | /* Get the constant we are comparing against, C, and see what it | |
3747 | looks like sign-extended to 16 bits. Then see what constant | |
3748 | could be XOR'ed with C to get the sign-extended value. */ | |
3749 | ||
3750 | int c = INTVAL (operands[2]); | |
3751 | int sextc = (c << 16) >> 16; | |
3752 | int xorv = c ^ sextc; | |
3753 | ||
3a598fbe JL |
3754 | operands[4] = GEN_INT (xorv); |
3755 | operands[5] = GEN_INT (sextc); | |
03dda8e3 RK |
3756 | @}") |
3757 | @end smallexample | |
3758 | ||
3759 | To avoid confusion, don't write a single @code{define_split} that | |
3760 | accepts some insns that match some @code{define_insn} as well as some | |
3761 | insns that don't. Instead, write two separate @code{define_split} | |
3762 | definitions, one for the insns that are valid and one for the insns that | |
3763 | are not valid. | |
3764 | ||
c88c0d42 CP |
3765 | For the common case where the pattern of a define_split exactly matches the |
3766 | pattern of a define_insn, use @code{define_insn_and_split}. It looks like | |
3767 | this: | |
3768 | ||
3769 | @smallexample | |
3770 | (define_insn_and_split | |
3771 | [@var{insn-pattern}] | |
3772 | "@var{condition}" | |
3773 | "@var{output-template}" | |
3774 | "@var{split-condition}" | |
3775 | [@var{new-insn-pattern-1} | |
3776 | @var{new-insn-pattern-2} | |
3777 | @dots{}] | |
3778 | "@var{preparation statements}" | |
3779 | [@var{insn-attributes}]) | |
3780 | ||
3781 | @end smallexample | |
3782 | ||
3783 | @var{insn-pattern}, @var{condition}, @var{output-template}, and | |
3784 | @var{insn-attributes} are used as in @code{define_insn}. The | |
3785 | @var{new-insn-pattern} vector and the @var{preparation-statements} are used as | |
3786 | in a @code{define_split}. The @var{split-condition} is also used as in | |
3787 | @code{define_split}, with the additional behavior that if the condition starts | |
3788 | with @samp{&&}, the condition used for the split will be the constructed as a | |
3789 | logical "and" of the split condition with the insn condition. For example, | |
3790 | from i386.md: | |
3791 | ||
3792 | @smallexample | |
3793 | (define_insn_and_split "zero_extendhisi2_and" | |
3794 | [(set (match_operand:SI 0 "register_operand" "=r") | |
3795 | (zero_extend:SI (match_operand:HI 1 "register_operand" "0"))) | |
3796 | (clobber (reg:CC 17))] | |
3797 | "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size" | |
3798 | "#" | |
3799 | "&& reload_completed" | |
3800 | [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (const_int 65535))) | |
3801 | (clobber (reg:CC 17))])] | |
3802 | "" | |
3803 | [(set_attr "type" "alu1")]) | |
3804 | ||
3805 | @end smallexample | |
3806 | ||
ebb48a4d | 3807 | In this case, the actual split condition will be |
c88c0d42 CP |
3808 | "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size && reload_completed." |
3809 | ||
3810 | The @code{define_insn_and_split} construction provides exactly the same | |
3811 | functionality as two separate @code{define_insn} and @code{define_split} | |
3812 | patterns. It exists for compactness, and as a maintenance tool to prevent | |
3813 | having to ensure the two patterns' templates match. | |
3814 | ||
f3a3d0d3 RH |
3815 | @node Peephole Definitions |
3816 | @section Machine-Specific Peephole Optimizers | |
3817 | @cindex peephole optimizer definitions | |
3818 | @cindex defining peephole optimizers | |
3819 | ||
3820 | In addition to instruction patterns the @file{md} file may contain | |
3821 | definitions of machine-specific peephole optimizations. | |
3822 | ||
3823 | The combiner does not notice certain peephole optimizations when the data | |
3824 | flow in the program does not suggest that it should try them. For example, | |
3825 | sometimes two consecutive insns related in purpose can be combined even | |
3826 | though the second one does not appear to use a register computed in the | |
3827 | first one. A machine-specific peephole optimizer can detect such | |
3828 | opportunities. | |
3829 | ||
3830 | There are two forms of peephole definitions that may be used. The | |
3831 | original @code{define_peephole} is run at assembly output time to | |
3832 | match insns and substitute assembly text. Use of @code{define_peephole} | |
3833 | is deprecated. | |
3834 | ||
3835 | A newer @code{define_peephole2} matches insns and substitutes new | |
3836 | insns. The @code{peephole2} pass is run after register allocation | |
ebb48a4d | 3837 | but before scheduling, which may result in much better code for |
f3a3d0d3 RH |
3838 | targets that do scheduling. |
3839 | ||
3840 | @menu | |
3841 | * define_peephole:: RTL to Text Peephole Optimizers | |
3842 | * define_peephole2:: RTL to RTL Peephole Optimizers | |
3843 | @end menu | |
3844 | ||
3845 | @node define_peephole | |
3846 | @subsection RTL to Text Peephole Optimizers | |
3847 | @findex define_peephole | |
3848 | ||
3849 | @need 1000 | |
3850 | A definition looks like this: | |
3851 | ||
3852 | @smallexample | |
3853 | (define_peephole | |
3854 | [@var{insn-pattern-1} | |
3855 | @var{insn-pattern-2} | |
3856 | @dots{}] | |
3857 | "@var{condition}" | |
3858 | "@var{template}" | |
3859 | "@var{optional insn-attributes}") | |
3860 | @end smallexample | |
3861 | ||
3862 | @noindent | |
3863 | The last string operand may be omitted if you are not using any | |
3864 | machine-specific information in this machine description. If present, | |
3865 | it must obey the same rules as in a @code{define_insn}. | |
3866 | ||
3867 | In this skeleton, @var{insn-pattern-1} and so on are patterns to match | |
3868 | consecutive insns. The optimization applies to a sequence of insns when | |
3869 | @var{insn-pattern-1} matches the first one, @var{insn-pattern-2} matches | |
3870 | the next, and so on.@refill | |
3871 | ||
3872 | Each of the insns matched by a peephole must also match a | |
3873 | @code{define_insn}. Peepholes are checked only at the last stage just | |
3874 | before code generation, and only optionally. Therefore, any insn which | |
3875 | would match a peephole but no @code{define_insn} will cause a crash in code | |
3876 | generation in an unoptimized compilation, or at various optimization | |
3877 | stages. | |
3878 | ||
3879 | The operands of the insns are matched with @code{match_operands}, | |
3880 | @code{match_operator}, and @code{match_dup}, as usual. What is not | |
3881 | usual is that the operand numbers apply to all the insn patterns in the | |
3882 | definition. So, you can check for identical operands in two insns by | |
3883 | using @code{match_operand} in one insn and @code{match_dup} in the | |
3884 | other. | |
3885 | ||
3886 | The operand constraints used in @code{match_operand} patterns do not have | |
3887 | any direct effect on the applicability of the peephole, but they will | |
3888 | be validated afterward, so make sure your constraints are general enough | |
3889 | to apply whenever the peephole matches. If the peephole matches | |
3890 | but the constraints are not satisfied, the compiler will crash. | |
3891 | ||
3892 | It is safe to omit constraints in all the operands of the peephole; or | |
3893 | you can write constraints which serve as a double-check on the criteria | |
3894 | previously tested. | |
3895 | ||
3896 | Once a sequence of insns matches the patterns, the @var{condition} is | |
3897 | checked. This is a C expression which makes the final decision whether to | |
3898 | perform the optimization (we do so if the expression is nonzero). If | |
3899 | @var{condition} is omitted (in other words, the string is empty) then the | |
3900 | optimization is applied to every sequence of insns that matches the | |
3901 | patterns. | |
3902 | ||
3903 | The defined peephole optimizations are applied after register allocation | |
3904 | is complete. Therefore, the peephole definition can check which | |
3905 | operands have ended up in which kinds of registers, just by looking at | |
3906 | the operands. | |
3907 | ||
3908 | @findex prev_active_insn | |
3909 | The way to refer to the operands in @var{condition} is to write | |
3910 | @code{operands[@var{i}]} for operand number @var{i} (as matched by | |
3911 | @code{(match_operand @var{i} @dots{})}). Use the variable @code{insn} | |
3912 | to refer to the last of the insns being matched; use | |
3913 | @code{prev_active_insn} to find the preceding insns. | |
3914 | ||
3915 | @findex dead_or_set_p | |
3916 | When optimizing computations with intermediate results, you can use | |
3917 | @var{condition} to match only when the intermediate results are not used | |
3918 | elsewhere. Use the C expression @code{dead_or_set_p (@var{insn}, | |
3919 | @var{op})}, where @var{insn} is the insn in which you expect the value | |
3920 | to be used for the last time (from the value of @code{insn}, together | |
3921 | with use of @code{prev_nonnote_insn}), and @var{op} is the intermediate | |
3922 | value (from @code{operands[@var{i}]}).@refill | |
3923 | ||
3924 | Applying the optimization means replacing the sequence of insns with one | |
3925 | new insn. The @var{template} controls ultimate output of assembler code | |
3926 | for this combined insn. It works exactly like the template of a | |
3927 | @code{define_insn}. Operand numbers in this template are the same ones | |
3928 | used in matching the original sequence of insns. | |
3929 | ||
3930 | The result of a defined peephole optimizer does not need to match any of | |
3931 | the insn patterns in the machine description; it does not even have an | |
3932 | opportunity to match them. The peephole optimizer definition itself serves | |
3933 | as the insn pattern to control how the insn is output. | |
3934 | ||
3935 | Defined peephole optimizers are run as assembler code is being output, | |
3936 | so the insns they produce are never combined or rearranged in any way. | |
3937 | ||
3938 | Here is an example, taken from the 68000 machine description: | |
3939 | ||
3940 | @smallexample | |
3941 | (define_peephole | |
3942 | [(set (reg:SI 15) (plus:SI (reg:SI 15) (const_int 4))) | |
3943 | (set (match_operand:DF 0 "register_operand" "=f") | |
3944 | (match_operand:DF 1 "register_operand" "ad"))] | |
3945 | "FP_REG_P (operands[0]) && ! FP_REG_P (operands[1])" | |
3946 | "* | |
3947 | @{ | |
3948 | rtx xoperands[2]; | |
3949 | xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1); | |
3950 | #ifdef MOTOROLA | |
3951 | output_asm_insn (\"move.l %1,(sp)\", xoperands); | |
3952 | output_asm_insn (\"move.l %1,-(sp)\", operands); | |
3953 | return \"fmove.d (sp)+,%0\"; | |
3954 | #else | |
3955 | output_asm_insn (\"movel %1,sp@@\", xoperands); | |
3956 | output_asm_insn (\"movel %1,sp@@-\", operands); | |
3957 | return \"fmoved sp@@+,%0\"; | |
3958 | #endif | |
3959 | @} | |
3960 | ") | |
3961 | @end smallexample | |
3962 | ||
3963 | @need 1000 | |
3964 | The effect of this optimization is to change | |
3965 | ||
3966 | @smallexample | |
3967 | @group | |
3968 | jbsr _foobar | |
3969 | addql #4,sp | |
3970 | movel d1,sp@@- | |
3971 | movel d0,sp@@- | |
3972 | fmoved sp@@+,fp0 | |
3973 | @end group | |
3974 | @end smallexample | |
3975 | ||
3976 | @noindent | |
3977 | into | |
3978 | ||
3979 | @smallexample | |
3980 | @group | |
3981 | jbsr _foobar | |
3982 | movel d1,sp@@ | |
3983 | movel d0,sp@@- | |
3984 | fmoved sp@@+,fp0 | |
3985 | @end group | |
3986 | @end smallexample | |
3987 | ||
3988 | @ignore | |
3989 | @findex CC_REVERSED | |
3990 | If a peephole matches a sequence including one or more jump insns, you must | |
3991 | take account of the flags such as @code{CC_REVERSED} which specify that the | |
3992 | condition codes are represented in an unusual manner. The compiler | |
3993 | automatically alters any ordinary conditional jumps which occur in such | |
3994 | situations, but the compiler cannot alter jumps which have been replaced by | |
3995 | peephole optimizations. So it is up to you to alter the assembler code | |
3996 | that the peephole produces. Supply C code to write the assembler output, | |
3997 | and in this C code check the condition code status flags and change the | |
3998 | assembler code as appropriate. | |
3999 | @end ignore | |
4000 | ||
4001 | @var{insn-pattern-1} and so on look @emph{almost} like the second | |
4002 | operand of @code{define_insn}. There is one important difference: the | |
4003 | second operand of @code{define_insn} consists of one or more RTX's | |
4004 | enclosed in square brackets. Usually, there is only one: then the same | |
4005 | action can be written as an element of a @code{define_peephole}. But | |
4006 | when there are multiple actions in a @code{define_insn}, they are | |
4007 | implicitly enclosed in a @code{parallel}. Then you must explicitly | |
4008 | write the @code{parallel}, and the square brackets within it, in the | |
4009 | @code{define_peephole}. Thus, if an insn pattern looks like this, | |
4010 | ||
4011 | @smallexample | |
4012 | (define_insn "divmodsi4" | |
4013 | [(set (match_operand:SI 0 "general_operand" "=d") | |
4014 | (div:SI (match_operand:SI 1 "general_operand" "0") | |
4015 | (match_operand:SI 2 "general_operand" "dmsK"))) | |
4016 | (set (match_operand:SI 3 "general_operand" "=d") | |
4017 | (mod:SI (match_dup 1) (match_dup 2)))] | |
4018 | "TARGET_68020" | |
4019 | "divsl%.l %2,%3:%0") | |
4020 | @end smallexample | |
4021 | ||
4022 | @noindent | |
4023 | then the way to mention this insn in a peephole is as follows: | |
4024 | ||
4025 | @smallexample | |
4026 | (define_peephole | |
4027 | [@dots{} | |
4028 | (parallel | |
4029 | [(set (match_operand:SI 0 "general_operand" "=d") | |
4030 | (div:SI (match_operand:SI 1 "general_operand" "0") | |
4031 | (match_operand:SI 2 "general_operand" "dmsK"))) | |
4032 | (set (match_operand:SI 3 "general_operand" "=d") | |
4033 | (mod:SI (match_dup 1) (match_dup 2)))]) | |
4034 | @dots{}] | |
4035 | @dots{}) | |
4036 | @end smallexample | |
4037 | ||
4038 | @node define_peephole2 | |
4039 | @subsection RTL to RTL Peephole Optimizers | |
4040 | @findex define_peephole2 | |
4041 | ||
4042 | The @code{define_peephole2} definition tells the compiler how to | |
ebb48a4d | 4043 | substitute one sequence of instructions for another sequence, |
f3a3d0d3 RH |
4044 | what additional scratch registers may be needed and what their |
4045 | lifetimes must be. | |
4046 | ||
4047 | @smallexample | |
4048 | (define_peephole2 | |
4049 | [@var{insn-pattern-1} | |
4050 | @var{insn-pattern-2} | |
4051 | @dots{}] | |
4052 | "@var{condition}" | |
4053 | [@var{new-insn-pattern-1} | |
4054 | @var{new-insn-pattern-2} | |
4055 | @dots{}] | |
4056 | "@var{preparation statements}") | |
4057 | @end smallexample | |
4058 | ||
4059 | The definition is almost identical to @code{define_split} | |
4060 | (@pxref{Insn Splitting}) except that the pattern to match is not a | |
4061 | single instruction, but a sequence of instructions. | |
4062 | ||
4063 | It is possible to request additional scratch registers for use in the | |
4064 | output template. If appropriate registers are not free, the pattern | |
4065 | will simply not match. | |
4066 | ||
4067 | @findex match_scratch | |
4068 | @findex match_dup | |
4069 | Scratch registers are requested with a @code{match_scratch} pattern at | |
4070 | the top level of the input pattern. The allocated register (initially) will | |
4071 | be dead at the point requested within the original sequence. If the scratch | |
4072 | is used at more than a single point, a @code{match_dup} pattern at the | |
4073 | top level of the input pattern marks the last position in the input sequence | |
4074 | at which the register must be available. | |
4075 | ||
4076 | Here is an example from the IA-32 machine description: | |
4077 | ||
4078 | @smallexample | |
4079 | (define_peephole2 | |
4080 | [(match_scratch:SI 2 "r") | |
4081 | (parallel [(set (match_operand:SI 0 "register_operand" "") | |
4082 | (match_operator:SI 3 "arith_or_logical_operator" | |
4083 | [(match_dup 0) | |
4084 | (match_operand:SI 1 "memory_operand" "")])) | |
4085 | (clobber (reg:CC 17))])] | |
4086 | "! optimize_size && ! TARGET_READ_MODIFY" | |
4087 | [(set (match_dup 2) (match_dup 1)) | |
4088 | (parallel [(set (match_dup 0) | |
4089 | (match_op_dup 3 [(match_dup 0) (match_dup 2)])) | |
4090 | (clobber (reg:CC 17))])] | |
4091 | "") | |
4092 | @end smallexample | |
4093 | ||
4094 | @noindent | |
4095 | This pattern tries to split a load from its use in the hopes that we'll be | |
4096 | able to schedule around the memory load latency. It allocates a single | |
4097 | @code{SImode} register of class @code{GENERAL_REGS} (@code{"r"}) that needs | |
4098 | to be live only at the point just before the arithmetic. | |
4099 | ||
b192711e | 4100 | A real example requiring extended scratch lifetimes is harder to come by, |
f3a3d0d3 RH |
4101 | so here's a silly made-up example: |
4102 | ||
4103 | @smallexample | |
4104 | (define_peephole2 | |
4105 | [(match_scratch:SI 4 "r") | |
4106 | (set (match_operand:SI 0 "" "") (match_operand:SI 1 "" "")) | |
4107 | (set (match_operand:SI 2 "" "") (match_dup 1)) | |
4108 | (match_dup 4) | |
4109 | (set (match_operand:SI 3 "" "") (match_dup 1))] | |
4110 | "@var{determine 1 does not overlap 0 and 2}" | |
4111 | [(set (match_dup 4) (match_dup 1)) | |
4112 | (set (match_dup 0) (match_dup 4)) | |
4113 | (set (match_dup 2) (match_dup 4))] | |
4114 | (set (match_dup 3) (match_dup 4))] | |
4115 | "") | |
4116 | @end smallexample | |
4117 | ||
4118 | @noindent | |
a628d195 RH |
4119 | If we had not added the @code{(match_dup 4)} in the middle of the input |
4120 | sequence, it might have been the case that the register we chose at the | |
4121 | beginning of the sequence is killed by the first or second @code{set}. | |
f3a3d0d3 | 4122 | |
03dda8e3 RK |
4123 | @node Insn Attributes |
4124 | @section Instruction Attributes | |
4125 | @cindex insn attributes | |
4126 | @cindex instruction attributes | |
4127 | ||
4128 | In addition to describing the instruction supported by the target machine, | |
4129 | the @file{md} file also defines a group of @dfn{attributes} and a set of | |
4130 | values for each. Every generated insn is assigned a value for each attribute. | |
4131 | One possible attribute would be the effect that the insn has on the machine's | |
4132 | condition code. This attribute can then be used by @code{NOTICE_UPDATE_CC} | |
4133 | to track the condition codes. | |
4134 | ||
4135 | @menu | |
4136 | * Defining Attributes:: Specifying attributes and their values. | |
4137 | * Expressions:: Valid expressions for attribute values. | |
4138 | * Tagging Insns:: Assigning attribute values to insns. | |
4139 | * Attr Example:: An example of assigning attributes. | |
4140 | * Insn Lengths:: Computing the length of insns. | |
4141 | * Constant Attributes:: Defining attributes that are constant. | |
4142 | * Delay Slots:: Defining delay slots required for a machine. | |
4143 | * Function Units:: Specifying information for insn scheduling. | |
4144 | @end menu | |
4145 | ||
4146 | @node Defining Attributes | |
4147 | @subsection Defining Attributes and their Values | |
4148 | @cindex defining attributes and their values | |
4149 | @cindex attributes, defining | |
4150 | ||
4151 | @findex define_attr | |
4152 | The @code{define_attr} expression is used to define each attribute required | |
4153 | by the target machine. It looks like: | |
4154 | ||
4155 | @smallexample | |
4156 | (define_attr @var{name} @var{list-of-values} @var{default}) | |
4157 | @end smallexample | |
4158 | ||
4159 | @var{name} is a string specifying the name of the attribute being defined. | |
4160 | ||
4161 | @var{list-of-values} is either a string that specifies a comma-separated | |
4162 | list of values that can be assigned to the attribute, or a null string to | |
4163 | indicate that the attribute takes numeric values. | |
4164 | ||
4165 | @var{default} is an attribute expression that gives the value of this | |
4166 | attribute for insns that match patterns whose definition does not include | |
4167 | an explicit value for this attribute. @xref{Attr Example}, for more | |
4168 | information on the handling of defaults. @xref{Constant Attributes}, | |
4169 | for information on attributes that do not depend on any particular insn. | |
4170 | ||
4171 | @findex insn-attr.h | |
4172 | For each defined attribute, a number of definitions are written to the | |
4173 | @file{insn-attr.h} file. For cases where an explicit set of values is | |
4174 | specified for an attribute, the following are defined: | |
4175 | ||
4176 | @itemize @bullet | |
4177 | @item | |
4178 | A @samp{#define} is written for the symbol @samp{HAVE_ATTR_@var{name}}. | |
4179 | ||
4180 | @item | |
4181 | An enumeral class is defined for @samp{attr_@var{name}} with | |
4182 | elements of the form @samp{@var{upper-name}_@var{upper-value}} where | |
4183 | the attribute name and value are first converted to upper case. | |
4184 | ||
4185 | @item | |
4186 | A function @samp{get_attr_@var{name}} is defined that is passed an insn and | |
4187 | returns the attribute value for that insn. | |
4188 | @end itemize | |
4189 | ||
4190 | For example, if the following is present in the @file{md} file: | |
4191 | ||
4192 | @smallexample | |
4193 | (define_attr "type" "branch,fp,load,store,arith" @dots{}) | |
4194 | @end smallexample | |
4195 | ||
4196 | @noindent | |
4197 | the following lines will be written to the file @file{insn-attr.h}. | |
4198 | ||
4199 | @smallexample | |
4200 | #define HAVE_ATTR_type | |
4201 | enum attr_type @{TYPE_BRANCH, TYPE_FP, TYPE_LOAD, | |
4202 | TYPE_STORE, TYPE_ARITH@}; | |
4203 | extern enum attr_type get_attr_type (); | |
4204 | @end smallexample | |
4205 | ||
4206 | If the attribute takes numeric values, no @code{enum} type will be | |
4207 | defined and the function to obtain the attribute's value will return | |
4208 | @code{int}. | |
4209 | ||
4210 | @node Expressions | |
4211 | @subsection Attribute Expressions | |
4212 | @cindex attribute expressions | |
4213 | ||
4214 | RTL expressions used to define attributes use the codes described above | |
4215 | plus a few specific to attribute definitions, to be discussed below. | |
4216 | Attribute value expressions must have one of the following forms: | |
4217 | ||
4218 | @table @code | |
4219 | @cindex @code{const_int} and attributes | |
4220 | @item (const_int @var{i}) | |
4221 | The integer @var{i} specifies the value of a numeric attribute. @var{i} | |
4222 | must be non-negative. | |
4223 | ||
4224 | The value of a numeric attribute can be specified either with a | |
00bc45c1 RH |
4225 | @code{const_int}, or as an integer represented as a string in |
4226 | @code{const_string}, @code{eq_attr} (see below), @code{attr}, | |
4227 | @code{symbol_ref}, simple arithmetic expressions, and @code{set_attr} | |
4228 | overrides on specific instructions (@pxref{Tagging Insns}). | |
03dda8e3 RK |
4229 | |
4230 | @cindex @code{const_string} and attributes | |
4231 | @item (const_string @var{value}) | |
4232 | The string @var{value} specifies a constant attribute value. | |
4233 | If @var{value} is specified as @samp{"*"}, it means that the default value of | |
4234 | the attribute is to be used for the insn containing this expression. | |
4235 | @samp{"*"} obviously cannot be used in the @var{default} expression | |
4236 | of a @code{define_attr}.@refill | |
4237 | ||
4238 | If the attribute whose value is being specified is numeric, @var{value} | |
4239 | must be a string containing a non-negative integer (normally | |
4240 | @code{const_int} would be used in this case). Otherwise, it must | |
4241 | contain one of the valid values for the attribute. | |
4242 | ||
4243 | @cindex @code{if_then_else} and attributes | |
4244 | @item (if_then_else @var{test} @var{true-value} @var{false-value}) | |
4245 | @var{test} specifies an attribute test, whose format is defined below. | |
4246 | The value of this expression is @var{true-value} if @var{test} is true, | |
4247 | otherwise it is @var{false-value}. | |
4248 | ||
4249 | @cindex @code{cond} and attributes | |
4250 | @item (cond [@var{test1} @var{value1} @dots{}] @var{default}) | |
4251 | The first operand of this expression is a vector containing an even | |
4252 | number of expressions and consisting of pairs of @var{test} and @var{value} | |
4253 | expressions. The value of the @code{cond} expression is that of the | |
4254 | @var{value} corresponding to the first true @var{test} expression. If | |
4255 | none of the @var{test} expressions are true, the value of the @code{cond} | |
4256 | expression is that of the @var{default} expression. | |
4257 | @end table | |
4258 | ||
4259 | @var{test} expressions can have one of the following forms: | |
4260 | ||
4261 | @table @code | |
4262 | @cindex @code{const_int} and attribute tests | |
4263 | @item (const_int @var{i}) | |
4264 | This test is true if @var{i} is non-zero and false otherwise. | |
4265 | ||
4266 | @cindex @code{not} and attributes | |
4267 | @cindex @code{ior} and attributes | |
4268 | @cindex @code{and} and attributes | |
4269 | @item (not @var{test}) | |
4270 | @itemx (ior @var{test1} @var{test2}) | |
4271 | @itemx (and @var{test1} @var{test2}) | |
4272 | These tests are true if the indicated logical function is true. | |
4273 | ||
4274 | @cindex @code{match_operand} and attributes | |
4275 | @item (match_operand:@var{m} @var{n} @var{pred} @var{constraints}) | |
4276 | This test is true if operand @var{n} of the insn whose attribute value | |
4277 | is being determined has mode @var{m} (this part of the test is ignored | |
4278 | if @var{m} is @code{VOIDmode}) and the function specified by the string | |
4279 | @var{pred} returns a non-zero value when passed operand @var{n} and mode | |
4280 | @var{m} (this part of the test is ignored if @var{pred} is the null | |
4281 | string). | |
4282 | ||
4283 | The @var{constraints} operand is ignored and should be the null string. | |
4284 | ||
4285 | @cindex @code{le} and attributes | |
4286 | @cindex @code{leu} and attributes | |
4287 | @cindex @code{lt} and attributes | |
4288 | @cindex @code{gt} and attributes | |
4289 | @cindex @code{gtu} and attributes | |
4290 | @cindex @code{ge} and attributes | |
4291 | @cindex @code{geu} and attributes | |
4292 | @cindex @code{ne} and attributes | |
4293 | @cindex @code{eq} and attributes | |
4294 | @cindex @code{plus} and attributes | |
4295 | @cindex @code{minus} and attributes | |
4296 | @cindex @code{mult} and attributes | |
4297 | @cindex @code{div} and attributes | |
4298 | @cindex @code{mod} and attributes | |
4299 | @cindex @code{abs} and attributes | |
4300 | @cindex @code{neg} and attributes | |
4301 | @cindex @code{ashift} and attributes | |
4302 | @cindex @code{lshiftrt} and attributes | |
4303 | @cindex @code{ashiftrt} and attributes | |
4304 | @item (le @var{arith1} @var{arith2}) | |
4305 | @itemx (leu @var{arith1} @var{arith2}) | |
4306 | @itemx (lt @var{arith1} @var{arith2}) | |
4307 | @itemx (ltu @var{arith1} @var{arith2}) | |
4308 | @itemx (gt @var{arith1} @var{arith2}) | |
4309 | @itemx (gtu @var{arith1} @var{arith2}) | |
4310 | @itemx (ge @var{arith1} @var{arith2}) | |
4311 | @itemx (geu @var{arith1} @var{arith2}) | |
4312 | @itemx (ne @var{arith1} @var{arith2}) | |
4313 | @itemx (eq @var{arith1} @var{arith2}) | |
4314 | These tests are true if the indicated comparison of the two arithmetic | |
4315 | expressions is true. Arithmetic expressions are formed with | |
4316 | @code{plus}, @code{minus}, @code{mult}, @code{div}, @code{mod}, | |
4317 | @code{abs}, @code{neg}, @code{and}, @code{ior}, @code{xor}, @code{not}, | |
4318 | @code{ashift}, @code{lshiftrt}, and @code{ashiftrt} expressions.@refill | |
4319 | ||
4320 | @findex get_attr | |
4321 | @code{const_int} and @code{symbol_ref} are always valid terms (@pxref{Insn | |
4322 | Lengths},for additional forms). @code{symbol_ref} is a string | |
4323 | denoting a C expression that yields an @code{int} when evaluated by the | |
4324 | @samp{get_attr_@dots{}} routine. It should normally be a global | |
4325 | variable.@refill | |
4326 | ||
4327 | @findex eq_attr | |
4328 | @item (eq_attr @var{name} @var{value}) | |
4329 | @var{name} is a string specifying the name of an attribute. | |
4330 | ||
4331 | @var{value} is a string that is either a valid value for attribute | |
4332 | @var{name}, a comma-separated list of values, or @samp{!} followed by a | |
4333 | value or list. If @var{value} does not begin with a @samp{!}, this | |
4334 | test is true if the value of the @var{name} attribute of the current | |
4335 | insn is in the list specified by @var{value}. If @var{value} begins | |
4336 | with a @samp{!}, this test is true if the attribute's value is | |
4337 | @emph{not} in the specified list. | |
4338 | ||
4339 | For example, | |
4340 | ||
4341 | @smallexample | |
4342 | (eq_attr "type" "load,store") | |
4343 | @end smallexample | |
4344 | ||
4345 | @noindent | |
4346 | is equivalent to | |
4347 | ||
4348 | @smallexample | |
4349 | (ior (eq_attr "type" "load") (eq_attr "type" "store")) | |
4350 | @end smallexample | |
4351 | ||
4352 | If @var{name} specifies an attribute of @samp{alternative}, it refers to the | |
4353 | value of the compiler variable @code{which_alternative} | |
4354 | (@pxref{Output Statement}) and the values must be small integers. For | |
4355 | example,@refill | |
4356 | ||
4357 | @smallexample | |
4358 | (eq_attr "alternative" "2,3") | |
4359 | @end smallexample | |
4360 | ||
4361 | @noindent | |
4362 | is equivalent to | |
4363 | ||
4364 | @smallexample | |
4365 | (ior (eq (symbol_ref "which_alternative") (const_int 2)) | |
4366 | (eq (symbol_ref "which_alternative") (const_int 3))) | |
4367 | @end smallexample | |
4368 | ||
4369 | Note that, for most attributes, an @code{eq_attr} test is simplified in cases | |
4370 | where the value of the attribute being tested is known for all insns matching | |
4371 | a particular pattern. This is by far the most common case.@refill | |
4372 | ||
4373 | @findex attr_flag | |
4374 | @item (attr_flag @var{name}) | |
4375 | The value of an @code{attr_flag} expression is true if the flag | |
4376 | specified by @var{name} is true for the @code{insn} currently being | |
4377 | scheduled. | |
4378 | ||
4379 | @var{name} is a string specifying one of a fixed set of flags to test. | |
4380 | Test the flags @code{forward} and @code{backward} to determine the | |
4381 | direction of a conditional branch. Test the flags @code{very_likely}, | |
4382 | @code{likely}, @code{very_unlikely}, and @code{unlikely} to determine | |
4383 | if a conditional branch is expected to be taken. | |
4384 | ||
4385 | If the @code{very_likely} flag is true, then the @code{likely} flag is also | |
4386 | true. Likewise for the @code{very_unlikely} and @code{unlikely} flags. | |
4387 | ||
4388 | This example describes a conditional branch delay slot which | |
4389 | can be nullified for forward branches that are taken (annul-true) or | |
4390 | for backward branches which are not taken (annul-false). | |
4391 | ||
4392 | @smallexample | |
4393 | (define_delay (eq_attr "type" "cbranch") | |
4394 | [(eq_attr "in_branch_delay" "true") | |
4395 | (and (eq_attr "in_branch_delay" "true") | |
4396 | (attr_flag "forward")) | |
4397 | (and (eq_attr "in_branch_delay" "true") | |
4398 | (attr_flag "backward"))]) | |
4399 | @end smallexample | |
4400 | ||
4401 | The @code{forward} and @code{backward} flags are false if the current | |
4402 | @code{insn} being scheduled is not a conditional branch. | |
4403 | ||
4404 | The @code{very_likely} and @code{likely} flags are true if the | |
4405 | @code{insn} being scheduled is not a conditional branch. | |
4406 | The @code{very_unlikely} and @code{unlikely} flags are false if the | |
4407 | @code{insn} being scheduled is not a conditional branch. | |
4408 | ||
4409 | @code{attr_flag} is only used during delay slot scheduling and has no | |
4410 | meaning to other passes of the compiler. | |
00bc45c1 RH |
4411 | |
4412 | @findex attr | |
4413 | @item (attr @var{name}) | |
4414 | The value of another attribute is returned. This is most useful | |
4415 | for numeric attributes, as @code{eq_attr} and @code{attr_flag} | |
4416 | produce more efficient code for non-numeric attributes. | |
03dda8e3 RK |
4417 | @end table |
4418 | ||
4419 | @node Tagging Insns | |
4420 | @subsection Assigning Attribute Values to Insns | |
4421 | @cindex tagging insns | |
4422 | @cindex assigning attribute values to insns | |
4423 | ||
4424 | The value assigned to an attribute of an insn is primarily determined by | |
4425 | which pattern is matched by that insn (or which @code{define_peephole} | |
4426 | generated it). Every @code{define_insn} and @code{define_peephole} can | |
4427 | have an optional last argument to specify the values of attributes for | |
4428 | matching insns. The value of any attribute not specified in a particular | |
4429 | insn is set to the default value for that attribute, as specified in its | |
4430 | @code{define_attr}. Extensive use of default values for attributes | |
4431 | permits the specification of the values for only one or two attributes | |
4432 | in the definition of most insn patterns, as seen in the example in the | |
4433 | next section.@refill | |
4434 | ||
4435 | The optional last argument of @code{define_insn} and | |
4436 | @code{define_peephole} is a vector of expressions, each of which defines | |
4437 | the value for a single attribute. The most general way of assigning an | |
4438 | attribute's value is to use a @code{set} expression whose first operand is an | |
4439 | @code{attr} expression giving the name of the attribute being set. The | |
4440 | second operand of the @code{set} is an attribute expression | |
4441 | (@pxref{Expressions}) giving the value of the attribute.@refill | |
4442 | ||
4443 | When the attribute value depends on the @samp{alternative} attribute | |
4444 | (i.e., which is the applicable alternative in the constraint of the | |
4445 | insn), the @code{set_attr_alternative} expression can be used. It | |
4446 | allows the specification of a vector of attribute expressions, one for | |
4447 | each alternative. | |
4448 | ||
4449 | @findex set_attr | |
4450 | When the generality of arbitrary attribute expressions is not required, | |
4451 | the simpler @code{set_attr} expression can be used, which allows | |
4452 | specifying a string giving either a single attribute value or a list | |
4453 | of attribute values, one for each alternative. | |
4454 | ||
4455 | The form of each of the above specifications is shown below. In each case, | |
4456 | @var{name} is a string specifying the attribute to be set. | |
4457 | ||
4458 | @table @code | |
4459 | @item (set_attr @var{name} @var{value-string}) | |
4460 | @var{value-string} is either a string giving the desired attribute value, | |
4461 | or a string containing a comma-separated list giving the values for | |
4462 | succeeding alternatives. The number of elements must match the number | |
4463 | of alternatives in the constraint of the insn pattern. | |
4464 | ||
4465 | Note that it may be useful to specify @samp{*} for some alternative, in | |
4466 | which case the attribute will assume its default value for insns matching | |
4467 | that alternative. | |
4468 | ||
4469 | @findex set_attr_alternative | |
4470 | @item (set_attr_alternative @var{name} [@var{value1} @var{value2} @dots{}]) | |
4471 | Depending on the alternative of the insn, the value will be one of the | |
4472 | specified values. This is a shorthand for using a @code{cond} with | |
4473 | tests on the @samp{alternative} attribute. | |
4474 | ||
4475 | @findex attr | |
4476 | @item (set (attr @var{name}) @var{value}) | |
4477 | The first operand of this @code{set} must be the special RTL expression | |
4478 | @code{attr}, whose sole operand is a string giving the name of the | |
4479 | attribute being set. @var{value} is the value of the attribute. | |
4480 | @end table | |
4481 | ||
4482 | The following shows three different ways of representing the same | |
4483 | attribute value specification: | |
4484 | ||
4485 | @smallexample | |
4486 | (set_attr "type" "load,store,arith") | |
4487 | ||
4488 | (set_attr_alternative "type" | |
4489 | [(const_string "load") (const_string "store") | |
4490 | (const_string "arith")]) | |
4491 | ||
4492 | (set (attr "type") | |
4493 | (cond [(eq_attr "alternative" "1") (const_string "load") | |
4494 | (eq_attr "alternative" "2") (const_string "store")] | |
4495 | (const_string "arith"))) | |
4496 | @end smallexample | |
4497 | ||
4498 | @need 1000 | |
4499 | @findex define_asm_attributes | |
4500 | The @code{define_asm_attributes} expression provides a mechanism to | |
4501 | specify the attributes assigned to insns produced from an @code{asm} | |
4502 | statement. It has the form: | |
4503 | ||
4504 | @smallexample | |
4505 | (define_asm_attributes [@var{attr-sets}]) | |
4506 | @end smallexample | |
4507 | ||
4508 | @noindent | |
4509 | where @var{attr-sets} is specified the same as for both the | |
4510 | @code{define_insn} and the @code{define_peephole} expressions. | |
4511 | ||
4512 | These values will typically be the ``worst case'' attribute values. For | |
4513 | example, they might indicate that the condition code will be clobbered. | |
4514 | ||
4515 | A specification for a @code{length} attribute is handled specially. The | |
4516 | way to compute the length of an @code{asm} insn is to multiply the | |
4517 | length specified in the expression @code{define_asm_attributes} by the | |
4518 | number of machine instructions specified in the @code{asm} statement, | |
4519 | determined by counting the number of semicolons and newlines in the | |
4520 | string. Therefore, the value of the @code{length} attribute specified | |
4521 | in a @code{define_asm_attributes} should be the maximum possible length | |
4522 | of a single machine instruction. | |
4523 | ||
4524 | @node Attr Example | |
4525 | @subsection Example of Attribute Specifications | |
4526 | @cindex attribute specifications example | |
4527 | @cindex attribute specifications | |
4528 | ||
4529 | The judicious use of defaulting is important in the efficient use of | |
4530 | insn attributes. Typically, insns are divided into @dfn{types} and an | |
4531 | attribute, customarily called @code{type}, is used to represent this | |
4532 | value. This attribute is normally used only to define the default value | |
4533 | for other attributes. An example will clarify this usage. | |
4534 | ||
4535 | Assume we have a RISC machine with a condition code and in which only | |
4536 | full-word operations are performed in registers. Let us assume that we | |
4537 | can divide all insns into loads, stores, (integer) arithmetic | |
4538 | operations, floating point operations, and branches. | |
4539 | ||
4540 | Here we will concern ourselves with determining the effect of an insn on | |
4541 | the condition code and will limit ourselves to the following possible | |
4542 | effects: The condition code can be set unpredictably (clobbered), not | |
4543 | be changed, be set to agree with the results of the operation, or only | |
4544 | changed if the item previously set into the condition code has been | |
4545 | modified. | |
4546 | ||
4547 | Here is part of a sample @file{md} file for such a machine: | |
4548 | ||
4549 | @smallexample | |
4550 | (define_attr "type" "load,store,arith,fp,branch" (const_string "arith")) | |
4551 | ||
4552 | (define_attr "cc" "clobber,unchanged,set,change0" | |
4553 | (cond [(eq_attr "type" "load") | |
4554 | (const_string "change0") | |
4555 | (eq_attr "type" "store,branch") | |
4556 | (const_string "unchanged") | |
4557 | (eq_attr "type" "arith") | |
4558 | (if_then_else (match_operand:SI 0 "" "") | |
4559 | (const_string "set") | |
4560 | (const_string "clobber"))] | |
4561 | (const_string "clobber"))) | |
4562 | ||
4563 | (define_insn "" | |
4564 | [(set (match_operand:SI 0 "general_operand" "=r,r,m") | |
4565 | (match_operand:SI 1 "general_operand" "r,m,r"))] | |
4566 | "" | |
4567 | "@@ | |
4568 | move %0,%1 | |
4569 | load %0,%1 | |
4570 | store %0,%1" | |
4571 | [(set_attr "type" "arith,load,store")]) | |
4572 | @end smallexample | |
4573 | ||
4574 | Note that we assume in the above example that arithmetic operations | |
4575 | performed on quantities smaller than a machine word clobber the condition | |
4576 | code since they will set the condition code to a value corresponding to the | |
4577 | full-word result. | |
4578 | ||
4579 | @node Insn Lengths | |
4580 | @subsection Computing the Length of an Insn | |
4581 | @cindex insn lengths, computing | |
4582 | @cindex computing the length of an insn | |
4583 | ||
4584 | For many machines, multiple types of branch instructions are provided, each | |
4585 | for different length branch displacements. In most cases, the assembler | |
4586 | will choose the correct instruction to use. However, when the assembler | |
4587 | cannot do so, GCC can when a special attribute, the @samp{length} | |
4588 | attribute, is defined. This attribute must be defined to have numeric | |
4589 | values by specifying a null string in its @code{define_attr}. | |
4590 | ||
4591 | In the case of the @samp{length} attribute, two additional forms of | |
4592 | arithmetic terms are allowed in test expressions: | |
4593 | ||
4594 | @table @code | |
4595 | @cindex @code{match_dup} and attributes | |
4596 | @item (match_dup @var{n}) | |
4597 | This refers to the address of operand @var{n} of the current insn, which | |
4598 | must be a @code{label_ref}. | |
4599 | ||
4600 | @cindex @code{pc} and attributes | |
4601 | @item (pc) | |
4602 | This refers to the address of the @emph{current} insn. It might have | |
4603 | been more consistent with other usage to make this the address of the | |
4604 | @emph{next} insn but this would be confusing because the length of the | |
4605 | current insn is to be computed. | |
4606 | @end table | |
4607 | ||
4608 | @cindex @code{addr_vec}, length of | |
4609 | @cindex @code{addr_diff_vec}, length of | |
4610 | For normal insns, the length will be determined by value of the | |
4611 | @samp{length} attribute. In the case of @code{addr_vec} and | |
4612 | @code{addr_diff_vec} insn patterns, the length is computed as | |
4613 | the number of vectors multiplied by the size of each vector. | |
4614 | ||
4615 | Lengths are measured in addressable storage units (bytes). | |
4616 | ||
4617 | The following macros can be used to refine the length computation: | |
4618 | ||
4619 | @table @code | |
4620 | @findex FIRST_INSN_ADDRESS | |
4621 | @item FIRST_INSN_ADDRESS | |
4622 | When the @code{length} insn attribute is used, this macro specifies the | |
4623 | value to be assigned to the address of the first insn in a function. If | |
4624 | not specified, 0 is used. | |
4625 | ||
4626 | @findex ADJUST_INSN_LENGTH | |
4627 | @item ADJUST_INSN_LENGTH (@var{insn}, @var{length}) | |
4628 | If defined, modifies the length assigned to instruction @var{insn} as a | |
4629 | function of the context in which it is used. @var{length} is an lvalue | |
4630 | that contains the initially computed length of the insn and should be | |
a8aa4e0b | 4631 | updated with the correct length of the insn. |
03dda8e3 RK |
4632 | |
4633 | This macro will normally not be required. A case in which it is | |
4634 | required is the ROMP. On this machine, the size of an @code{addr_vec} | |
4635 | insn must be increased by two to compensate for the fact that alignment | |
4636 | may be required. | |
4637 | @end table | |
4638 | ||
4639 | @findex get_attr_length | |
4640 | The routine that returns @code{get_attr_length} (the value of the | |
4641 | @code{length} attribute) can be used by the output routine to | |
4642 | determine the form of the branch instruction to be written, as the | |
4643 | example below illustrates. | |
4644 | ||
4645 | As an example of the specification of variable-length branches, consider | |
4646 | the IBM 360. If we adopt the convention that a register will be set to | |
4647 | the starting address of a function, we can jump to labels within 4k of | |
4648 | the start using a four-byte instruction. Otherwise, we need a six-byte | |
4649 | sequence to load the address from memory and then branch to it. | |
4650 | ||
4651 | On such a machine, a pattern for a branch instruction might be specified | |
4652 | as follows: | |
4653 | ||
4654 | @smallexample | |
4655 | (define_insn "jump" | |
4656 | [(set (pc) | |
4657 | (label_ref (match_operand 0 "" "")))] | |
4658 | "" | |
4659 | "* | |
4660 | @{ | |
4661 | return (get_attr_length (insn) == 4 | |
4662 | ? \"b %l0\" : \"l r15,=a(%l0); br r15\"); | |
4663 | @}" | |
4664 | [(set (attr "length") (if_then_else (lt (match_dup 0) (const_int 4096)) | |
4665 | (const_int 4) | |
4666 | (const_int 6)))]) | |
4667 | @end smallexample | |
4668 | ||
4669 | @node Constant Attributes | |
4670 | @subsection Constant Attributes | |
4671 | @cindex constant attributes | |
4672 | ||
4673 | A special form of @code{define_attr}, where the expression for the | |
4674 | default value is a @code{const} expression, indicates an attribute that | |
4675 | is constant for a given run of the compiler. Constant attributes may be | |
4676 | used to specify which variety of processor is used. For example, | |
4677 | ||
4678 | @smallexample | |
4679 | (define_attr "cpu" "m88100,m88110,m88000" | |
4680 | (const | |
4681 | (cond [(symbol_ref "TARGET_88100") (const_string "m88100") | |
4682 | (symbol_ref "TARGET_88110") (const_string "m88110")] | |
4683 | (const_string "m88000")))) | |
4684 | ||
4685 | (define_attr "memory" "fast,slow" | |
4686 | (const | |
4687 | (if_then_else (symbol_ref "TARGET_FAST_MEM") | |
4688 | (const_string "fast") | |
4689 | (const_string "slow")))) | |
4690 | @end smallexample | |
4691 | ||
4692 | The routine generated for constant attributes has no parameters as it | |
4693 | does not depend on any particular insn. RTL expressions used to define | |
4694 | the value of a constant attribute may use the @code{symbol_ref} form, | |
4695 | but may not use either the @code{match_operand} form or @code{eq_attr} | |
4696 | forms involving insn attributes. | |
4697 | ||
4698 | @node Delay Slots | |
4699 | @subsection Delay Slot Scheduling | |
4700 | @cindex delay slots, defining | |
4701 | ||
4702 | The insn attribute mechanism can be used to specify the requirements for | |
4703 | delay slots, if any, on a target machine. An instruction is said to | |
4704 | require a @dfn{delay slot} if some instructions that are physically | |
4705 | after the instruction are executed as if they were located before it. | |
4706 | Classic examples are branch and call instructions, which often execute | |
4707 | the following instruction before the branch or call is performed. | |
4708 | ||
4709 | On some machines, conditional branch instructions can optionally | |
4710 | @dfn{annul} instructions in the delay slot. This means that the | |
4711 | instruction will not be executed for certain branch outcomes. Both | |
4712 | instructions that annul if the branch is true and instructions that | |
4713 | annul if the branch is false are supported. | |
4714 | ||
4715 | Delay slot scheduling differs from instruction scheduling in that | |
4716 | determining whether an instruction needs a delay slot is dependent only | |
4717 | on the type of instruction being generated, not on data flow between the | |
4718 | instructions. See the next section for a discussion of data-dependent | |
4719 | instruction scheduling. | |
4720 | ||
4721 | @findex define_delay | |
4722 | The requirement of an insn needing one or more delay slots is indicated | |
4723 | via the @code{define_delay} expression. It has the following form: | |
4724 | ||
4725 | @smallexample | |
4726 | (define_delay @var{test} | |
4727 | [@var{delay-1} @var{annul-true-1} @var{annul-false-1} | |
4728 | @var{delay-2} @var{annul-true-2} @var{annul-false-2} | |
4729 | @dots{}]) | |
4730 | @end smallexample | |
4731 | ||
4732 | @var{test} is an attribute test that indicates whether this | |
4733 | @code{define_delay} applies to a particular insn. If so, the number of | |
4734 | required delay slots is determined by the length of the vector specified | |
4735 | as the second argument. An insn placed in delay slot @var{n} must | |
4736 | satisfy attribute test @var{delay-n}. @var{annul-true-n} is an | |
4737 | attribute test that specifies which insns may be annulled if the branch | |
4738 | is true. Similarly, @var{annul-false-n} specifies which insns in the | |
4739 | delay slot may be annulled if the branch is false. If annulling is not | |
4740 | supported for that delay slot, @code{(nil)} should be coded.@refill | |
4741 | ||
4742 | For example, in the common case where branch and call insns require | |
4743 | a single delay slot, which may contain any insn other than a branch or | |
4744 | call, the following would be placed in the @file{md} file: | |
4745 | ||
4746 | @smallexample | |
4747 | (define_delay (eq_attr "type" "branch,call") | |
4748 | [(eq_attr "type" "!branch,call") (nil) (nil)]) | |
4749 | @end smallexample | |
4750 | ||
4751 | Multiple @code{define_delay} expressions may be specified. In this | |
4752 | case, each such expression specifies different delay slot requirements | |
4753 | and there must be no insn for which tests in two @code{define_delay} | |
4754 | expressions are both true. | |
4755 | ||
4756 | For example, if we have a machine that requires one delay slot for branches | |
4757 | but two for calls, no delay slot can contain a branch or call insn, | |
4758 | and any valid insn in the delay slot for the branch can be annulled if the | |
4759 | branch is true, we might represent this as follows: | |
4760 | ||
4761 | @smallexample | |
4762 | (define_delay (eq_attr "type" "branch") | |
4763 | [(eq_attr "type" "!branch,call") | |
4764 | (eq_attr "type" "!branch,call") | |
4765 | (nil)]) | |
4766 | ||
4767 | (define_delay (eq_attr "type" "call") | |
4768 | [(eq_attr "type" "!branch,call") (nil) (nil) | |
4769 | (eq_attr "type" "!branch,call") (nil) (nil)]) | |
4770 | @end smallexample | |
4771 | @c the above is *still* too long. --mew 4feb93 | |
4772 | ||
4773 | @node Function Units | |
4774 | @subsection Specifying Function Units | |
4775 | @cindex function units, for scheduling | |
4776 | ||
4777 | On most RISC machines, there are instructions whose results are not | |
4778 | available for a specific number of cycles. Common cases are instructions | |
4779 | that load data from memory. On many machines, a pipeline stall will result | |
4780 | if the data is referenced too soon after the load instruction. | |
4781 | ||
4782 | In addition, many newer microprocessors have multiple function units, usually | |
4783 | one for integer and one for floating point, and often will incur pipeline | |
4784 | stalls when a result that is needed is not yet ready. | |
4785 | ||
4786 | The descriptions in this section allow the specification of how much | |
4787 | time must elapse between the execution of an instruction and the time | |
4788 | when its result is used. It also allows specification of when the | |
4789 | execution of an instruction will delay execution of similar instructions | |
4790 | due to function unit conflicts. | |
4791 | ||
4792 | For the purposes of the specifications in this section, a machine is | |
4793 | divided into @dfn{function units}, each of which execute a specific | |
4794 | class of instructions in first-in-first-out order. Function units that | |
4795 | accept one instruction each cycle and allow a result to be used in the | |
4796 | succeeding instruction (usually via forwarding) need not be specified. | |
4797 | Classic RISC microprocessors will normally have a single function unit, | |
4798 | which we can call @samp{memory}. The newer ``superscalar'' processors | |
4799 | will often have function units for floating point operations, usually at | |
4800 | least a floating point adder and multiplier. | |
4801 | ||
4802 | @findex define_function_unit | |
4803 | Each usage of a function units by a class of insns is specified with a | |
4804 | @code{define_function_unit} expression, which looks like this: | |
4805 | ||
4806 | @smallexample | |
4807 | (define_function_unit @var{name} @var{multiplicity} @var{simultaneity} | |
4808 | @var{test} @var{ready-delay} @var{issue-delay} | |
4809 | [@var{conflict-list}]) | |
4810 | @end smallexample | |
4811 | ||
4812 | @var{name} is a string giving the name of the function unit. | |
4813 | ||
4814 | @var{multiplicity} is an integer specifying the number of identical | |
4815 | units in the processor. If more than one unit is specified, they will | |
4816 | be scheduled independently. Only truly independent units should be | |
4817 | counted; a pipelined unit should be specified as a single unit. (The | |
4818 | only common example of a machine that has multiple function units for a | |
4819 | single instruction class that are truly independent and not pipelined | |
4820 | are the two multiply and two increment units of the CDC 6600.) | |
4821 | ||
4822 | @var{simultaneity} specifies the maximum number of insns that can be | |
4823 | executing in each instance of the function unit simultaneously or zero | |
4824 | if the unit is pipelined and has no limit. | |
4825 | ||
4826 | All @code{define_function_unit} definitions referring to function unit | |
4827 | @var{name} must have the same name and values for @var{multiplicity} and | |
4828 | @var{simultaneity}. | |
4829 | ||
4830 | @var{test} is an attribute test that selects the insns we are describing | |
4831 | in this definition. Note that an insn may use more than one function | |
4832 | unit and a function unit may be specified in more than one | |
4833 | @code{define_function_unit}. | |
4834 | ||
4835 | @var{ready-delay} is an integer that specifies the number of cycles | |
4836 | after which the result of the instruction can be used without | |
4837 | introducing any stalls. | |
4838 | ||
4839 | @var{issue-delay} is an integer that specifies the number of cycles | |
4840 | after the instruction matching the @var{test} expression begins using | |
4841 | this unit until a subsequent instruction can begin. A cost of @var{N} | |
4842 | indicates an @var{N-1} cycle delay. A subsequent instruction may also | |
4843 | be delayed if an earlier instruction has a longer @var{ready-delay} | |
4844 | value. This blocking effect is computed using the @var{simultaneity}, | |
4845 | @var{ready-delay}, @var{issue-delay}, and @var{conflict-list} terms. | |
4846 | For a normal non-pipelined function unit, @var{simultaneity} is one, the | |
4847 | unit is taken to block for the @var{ready-delay} cycles of the executing | |
4848 | insn, and smaller values of @var{issue-delay} are ignored. | |
4849 | ||
4850 | @var{conflict-list} is an optional list giving detailed conflict costs | |
4851 | for this unit. If specified, it is a list of condition test expressions | |
4852 | to be applied to insns chosen to execute in @var{name} following the | |
4853 | particular insn matching @var{test} that is already executing in | |
4854 | @var{name}. For each insn in the list, @var{issue-delay} specifies the | |
4855 | conflict cost; for insns not in the list, the cost is zero. If not | |
4856 | specified, @var{conflict-list} defaults to all instructions that use the | |
4857 | function unit. | |
4858 | ||
4859 | Typical uses of this vector are where a floating point function unit can | |
4860 | pipeline either single- or double-precision operations, but not both, or | |
4861 | where a memory unit can pipeline loads, but not stores, etc. | |
4862 | ||
4863 | As an example, consider a classic RISC machine where the result of a | |
4864 | load instruction is not available for two cycles (a single ``delay'' | |
4865 | instruction is required) and where only one load instruction can be executed | |
4866 | simultaneously. This would be specified as: | |
4867 | ||
4868 | @smallexample | |
4869 | (define_function_unit "memory" 1 1 (eq_attr "type" "load") 2 0) | |
4870 | @end smallexample | |
4871 | ||
4872 | For the case of a floating point function unit that can pipeline either | |
4873 | single or double precision, but not both, the following could be specified: | |
4874 | ||
4875 | @smallexample | |
4876 | (define_function_unit | |
4877 | "fp" 1 0 (eq_attr "type" "sp_fp") 4 4 [(eq_attr "type" "dp_fp")]) | |
4878 | (define_function_unit | |
4879 | "fp" 1 0 (eq_attr "type" "dp_fp") 4 4 [(eq_attr "type" "sp_fp")]) | |
4880 | @end smallexample | |
4881 | ||
4882 | @strong{Note:} The scheduler attempts to avoid function unit conflicts | |
4883 | and uses all the specifications in the @code{define_function_unit} | |
4884 | expression. It has recently come to our attention that these | |
4885 | specifications may not allow modeling of some of the newer | |
4886 | ``superscalar'' processors that have insns using multiple pipelined | |
4887 | units. These insns will cause a potential conflict for the second unit | |
4888 | used during their execution and there is no way of representing that | |
4889 | conflict. We welcome any examples of how function unit conflicts work | |
4890 | in such processors and suggestions for their representation. | |
4891 | @end ifset | |
3262c1f5 RH |
4892 | |
4893 | @node Conditional Execution | |
4894 | @section Conditional Execution | |
4895 | @cindex conditional execution | |
4896 | @cindex predication | |
4897 | ||
4898 | A number of architectures provide for some form of conditional | |
4899 | execution, or predication. The hallmark of this feature is the | |
4900 | ability to nullify most of the instructions in the instruction set. | |
4901 | When the instruction set is large and not entirely symmetric, it | |
4902 | can be quite tedious to describe these forms directly in the | |
4903 | @file{.md} file. An alternative is the @code{define_cond_exec} template. | |
4904 | ||
4905 | @findex define_cond_exec | |
4906 | @smallexample | |
4907 | (define_cond_exec | |
4908 | [@var{predicate-pattern}] | |
4909 | "@var{condition}" | |
4910 | "@var{output template}") | |
4911 | @end smallexample | |
4912 | ||
4913 | @var{predicate-pattern} is the condition that must be true for the | |
4914 | insn to be executed at runtime and should match a relational operator. | |
4915 | One can use @code{match_operator} to match several relational operators | |
4916 | at once. Any @code{match_operand} operands must have no more than one | |
4917 | alternative. | |
4918 | ||
4919 | @var{condition} is a C expression that must be true for the generated | |
4920 | pattern to match. | |
4921 | ||
4922 | @findex current_insn_predicate | |
4923 | @var{output template} is a string similar to the @code{define_insn} | |
4924 | output template (@pxref{Output Template}), except that the @samp{*} | |
4925 | and @samp{@@} special cases do not apply. This is only useful if the | |
4926 | assembly text for the predicate is a simple prefix to the main insn. | |
4927 | In order to handle the general case, there is a global variable | |
4928 | @code{current_insn_predicate} that will contain the entire predicate | |
4929 | if the current insn is predicated, and will otherwise be @code{NULL}. | |
4930 | ||
ebb48a4d JM |
4931 | When @code{define_cond_exec} is used, an implicit reference to |
4932 | the @code{predicable} instruction attribute is made. | |
3262c1f5 RH |
4933 | @xref{Insn Attributes}. This attribute must be boolean (i.e. have |
4934 | exactly two elements in its @var{list-of-values}). Further, it must | |
4935 | not be used with complex expressions. That is, the default and all | |
ebb48a4d | 4936 | uses in the insns must be a simple constant, not dependent on the |
3262c1f5 RH |
4937 | alternative or anything else. |
4938 | ||
ebb48a4d | 4939 | For each @code{define_insn} for which the @code{predicable} |
3262c1f5 RH |
4940 | attribute is true, a new @code{define_insn} pattern will be |
4941 | generated that matches a predicated version of the instruction. | |
4942 | For example, | |
4943 | ||
4944 | @smallexample | |
4945 | (define_insn "addsi" | |
4946 | [(set (match_operand:SI 0 "register_operand" "r") | |
4947 | (plus:SI (match_operand:SI 1 "register_operand" "r") | |
4948 | (match_operand:SI 2 "register_operand" "r")))] | |
4949 | "@var{test1}" | |
4950 | "add %2,%1,%0") | |
4951 | ||
4952 | (define_cond_exec | |
4953 | [(ne (match_operand:CC 0 "register_operand" "c") | |
4954 | (const_int 0))] | |
4955 | "@var{test2}" | |
4956 | "(%0)") | |
4957 | @end smallexample | |
4958 | ||
4959 | @noindent | |
4960 | generates a new pattern | |
4961 | ||
4962 | @smallexample | |
4963 | (define_insn "" | |
4964 | [(cond_exec | |
4965 | (ne (match_operand:CC 3 "register_operand" "c") (const_int 0)) | |
4966 | (set (match_operand:SI 0 "register_operand" "r") | |
4967 | (plus:SI (match_operand:SI 1 "register_operand" "r") | |
4968 | (match_operand:SI 2 "register_operand" "r"))))] | |
4969 | "(@var{test2}) && (@var{test1})" | |
4970 | "(%3) add %2,%1,%0") | |
4971 | @end smallexample | |
c25c12b8 R |
4972 | |
4973 | @node Constant Definitions | |
4974 | @section Constant Definitions | |
4975 | @cindex constant definitions | |
4976 | @findex define_constants | |
4977 | ||
4978 | Using literal constants inside instruction patterns reduces legibility and | |
4979 | can be a maintenance problem. | |
4980 | ||
4981 | To overcome this problem, you may use the @code{define_constants} | |
4982 | expression. It contains a vector of name-value pairs. From that | |
4983 | point on, wherever any of the names appears in the MD file, it is as | |
4984 | if the corresponding value had been written instead. You may use | |
4985 | @code{define_constants} multiple times; each appearance adds more | |
4986 | constants to the table. It is an error to redefine a constant with | |
4987 | a different value. | |
4988 | ||
4989 | To come back to the a29k load multiple example, instead of | |
4990 | ||
4991 | @smallexample | |
4992 | (define_insn "" | |
4993 | [(match_parallel 0 "load_multiple_operation" | |
4994 | [(set (match_operand:SI 1 "gpc_reg_operand" "=r") | |
4995 | (match_operand:SI 2 "memory_operand" "m")) | |
4996 | (use (reg:SI 179)) | |
4997 | (clobber (reg:SI 179))])] | |
4998 | "" | |
4999 | "loadm 0,0,%1,%2") | |
5000 | @end smallexample | |
5001 | ||
5002 | You could write: | |
5003 | ||
5004 | @smallexample | |
5005 | (define_constants [ | |
5006 | (R_BP 177) | |
5007 | (R_FC 178) | |
5008 | (R_CR 179) | |
5009 | (R_Q 180) | |
5010 | ]) | |
5011 | ||
5012 | (define_insn "" | |
5013 | [(match_parallel 0 "load_multiple_operation" | |
5014 | [(set (match_operand:SI 1 "gpc_reg_operand" "=r") | |
5015 | (match_operand:SI 2 "memory_operand" "m")) | |
5016 | (use (reg:SI R_CR)) | |
5017 | (clobber (reg:SI R_CR))])] | |
5018 | "" | |
5019 | "loadm 0,0,%1,%2") | |
5020 | @end smallexample | |
5021 | ||
5022 | The constants that are defined with a define_constant are also output | |
5023 | in the insn-codes.h header file as #defines. |