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1 | /* Subroutines for insn-output.c for Vax. |
2 | Copyright (C) 1987 Free Software Foundation, Inc. | |
3 | ||
4 | This file is part of GNU CC. | |
5 | ||
6 | GNU CC is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
8 | the Free Software Foundation; either version 2, or (at your option) | |
9 | any later version. | |
10 | ||
11 | GNU CC is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with GNU CC; see the file COPYING. If not, write to | |
18 | the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ | |
19 | ||
20 | #include <stdio.h> | |
21 | #include "config.h" | |
22 | #include "rtl.h" | |
23 | #include "regs.h" | |
24 | #include "hard-reg-set.h" | |
25 | #include "real.h" | |
26 | #include "insn-config.h" | |
27 | #include "conditions.h" | |
28 | #include "insn-flags.h" | |
29 | #include "output.h" | |
30 | #include "insn-attr.h" | |
31 | ||
9c21a7e7 RS |
32 | |
33 | void | |
34 | split_quadword_operands (operands, low, n) | |
35 | rtx *operands, *low; | |
b4ac57ab | 36 | This is nonimmediate_operand with a restriction on the type of MEM. */ |
9c21a7e7 RS |
37 | { |
38 | int i; | |
39 | /* Split operands. */ | |
40 | ||
41 | low[0] = low[1] = low[2] = 0; | |
42 | for (i = 0; i < 3; i++) | |
43 | { | |
44 | if (low[i]) | |
45 | /* it's already been figured out */; | |
46 | else if (GET_CODE (operands[i]) == MEM | |
47 | && (GET_CODE (XEXP (operands[i], 0)) == POST_INC)) | |
48 | { | |
49 | rtx addr = XEXP (operands[i], 0); | |
50 | operands[i] = low[i] = gen_rtx (MEM, SImode, addr); | |
51 | if (which_alternative == 0 && i == 0) | |
52 | { | |
53 | addr = XEXP (operands[i], 0); | |
54 | operands[i+1] = low[i+1] = gen_rtx (MEM, SImode, addr); | |
55 | } | |
56 | } | |
57 | else | |
58 | { | |
59 | low[i] = operand_subword (operands[i], 0, 0, DImode); | |
60 | operands[i] = operand_subword (operands[i], 1, 0, DImode); | |
61 | } | |
62 | } | |
63 | } | |
64 | \f | |
65 | print_operand_address (file, addr) | |
66 | FILE *file; | |
67 | register rtx addr; | |
68 | { | |
69 | register rtx reg1, reg2, breg, ireg; | |
70 | rtx offset; | |
71 | ||
72 | retry: | |
73 | switch (GET_CODE (addr)) | |
74 | { | |
75 | case MEM: | |
76 | fprintf (file, "*"); | |
77 | addr = XEXP (addr, 0); | |
78 | goto retry; | |
79 | ||
80 | case REG: | |
81 | fprintf (file, "(%s)", reg_names[REGNO (addr)]); | |
82 | break; | |
83 | ||
84 | case PRE_DEC: | |
85 | fprintf (file, "-(%s)", reg_names[REGNO (XEXP (addr, 0))]); | |
86 | break; | |
87 | ||
88 | case POST_INC: | |
89 | fprintf (file, "(%s)+", reg_names[REGNO (XEXP (addr, 0))]); | |
90 | break; | |
91 | ||
92 | case PLUS: | |
93 | /* There can be either two or three things added here. One must be a | |
94 | REG. One can be either a REG or a MULT of a REG and an appropriate | |
95 | constant, and the third can only be a constant or a MEM. | |
96 | ||
97 | We get these two or three things and put the constant or MEM in | |
98 | OFFSET, the MULT or REG in IREG, and the REG in BREG. If we have | |
99 | a register and can't tell yet if it is a base or index register, | |
100 | put it into REG1. */ | |
101 | ||
102 | reg1 = 0; ireg = 0; breg = 0; offset = 0; | |
103 | ||
104 | if (CONSTANT_ADDRESS_P (XEXP (addr, 0)) | |
105 | || GET_CODE (XEXP (addr, 0)) == MEM) | |
106 | { | |
107 | offset = XEXP (addr, 0); | |
108 | addr = XEXP (addr, 1); | |
109 | } | |
110 | else if (CONSTANT_ADDRESS_P (XEXP (addr, 1)) | |
111 | || GET_CODE (XEXP (addr, 1)) == MEM) | |
112 | { | |
113 | offset = XEXP (addr, 1); | |
114 | addr = XEXP (addr, 0); | |
115 | } | |
116 | else if (GET_CODE (XEXP (addr, 1)) == MULT) | |
117 | { | |
118 | ireg = XEXP (addr, 1); | |
119 | addr = XEXP (addr, 0); | |
120 | } | |
121 | else if (GET_CODE (XEXP (addr, 0)) == MULT) | |
122 | { | |
123 | ireg = XEXP (addr, 0); | |
124 | addr = XEXP (addr, 1); | |
125 | } | |
126 | else if (GET_CODE (XEXP (addr, 1)) == REG) | |
127 | { | |
128 | reg1 = XEXP (addr, 1); | |
129 | addr = XEXP (addr, 0); | |
130 | } | |
2d6cb879 TW |
131 | else if (GET_CODE (XEXP (addr, 0)) == REG) |
132 | { | |
133 | reg1 = XEXP (addr, 0); | |
134 | addr = XEXP (addr, 1); | |
135 | } | |
9c21a7e7 RS |
136 | else |
137 | abort (); | |
138 | ||
139 | if (GET_CODE (addr) == REG) | |
140 | { | |
141 | if (reg1) | |
142 | ireg = addr; | |
143 | else | |
144 | reg1 = addr; | |
145 | } | |
146 | else if (GET_CODE (addr) == MULT) | |
147 | ireg = addr; | |
148 | else if (GET_CODE (addr) == PLUS) | |
149 | { | |
150 | if (CONSTANT_ADDRESS_P (XEXP (addr, 0)) | |
151 | || GET_CODE (XEXP (addr, 0)) == MEM) | |
152 | { | |
153 | if (offset) | |
154 | { | |
155 | if (GET_CODE (offset) == CONST_INT) | |
156 | offset = plus_constant (XEXP (addr, 0), INTVAL (offset)); | |
157 | else if (GET_CODE (XEXP (addr, 0)) == CONST_INT) | |
158 | offset = plus_constant (offset, INTVAL (XEXP (addr, 0))); | |
159 | else | |
160 | abort (); | |
161 | } | |
162 | offset = XEXP (addr, 0); | |
163 | } | |
164 | else if (GET_CODE (XEXP (addr, 0)) == REG) | |
165 | { | |
166 | if (reg1) | |
167 | ireg = reg1, breg = XEXP (addr, 0), reg1 = 0; | |
168 | else | |
169 | reg1 = XEXP (addr, 0); | |
170 | } | |
171 | else if (GET_CODE (XEXP (addr, 0)) == MULT) | |
172 | { | |
173 | if (ireg) | |
174 | abort (); | |
175 | ireg = XEXP (addr, 0); | |
176 | } | |
177 | else | |
178 | abort (); | |
179 | ||
180 | if (CONSTANT_ADDRESS_P (XEXP (addr, 1)) | |
181 | || GET_CODE (XEXP (addr, 1)) == MEM) | |
182 | { | |
183 | if (offset) | |
184 | { | |
185 | if (GET_CODE (offset) == CONST_INT) | |
186 | offset = plus_constant (XEXP (addr, 1), INTVAL (offset)); | |
187 | else if (GET_CODE (XEXP (addr, 1)) == CONST_INT) | |
188 | offset = plus_constant (offset, INTVAL (XEXP (addr, 1))); | |
189 | else | |
190 | abort (); | |
191 | } | |
192 | offset = XEXP (addr, 1); | |
193 | } | |
194 | else if (GET_CODE (XEXP (addr, 1)) == REG) | |
195 | { | |
196 | if (reg1) | |
197 | ireg = reg1, breg = XEXP (addr, 1), reg1 = 0; | |
198 | else | |
199 | reg1 = XEXP (addr, 1); | |
200 | } | |
201 | else if (GET_CODE (XEXP (addr, 1)) == MULT) | |
202 | { | |
203 | if (ireg) | |
204 | abort (); | |
205 | ireg = XEXP (addr, 1); | |
206 | } | |
207 | else | |
208 | abort (); | |
209 | } | |
210 | else | |
211 | abort (); | |
212 | ||
213 | /* If REG1 is non-zero, figure out if it is a base or index register. */ | |
214 | if (reg1) | |
215 | { | |
216 | if (breg != 0 || (offset && GET_CODE (offset) == MEM)) | |
217 | { | |
218 | if (ireg) | |
219 | abort (); | |
220 | ireg = reg1; | |
221 | } | |
222 | else | |
223 | breg = reg1; | |
224 | } | |
225 | ||
226 | if (offset != 0) | |
227 | output_address (offset); | |
228 | ||
229 | if (breg != 0) | |
230 | fprintf (file, "(%s)", reg_names[REGNO (breg)]); | |
231 | ||
232 | if (ireg != 0) | |
233 | { | |
234 | if (GET_CODE (ireg) == MULT) | |
235 | ireg = XEXP (ireg, 0); | |
236 | if (GET_CODE (ireg) != REG) | |
237 | abort (); | |
238 | fprintf (file, "[%s]", reg_names[REGNO (ireg)]); | |
239 | } | |
240 | break; | |
241 | ||
242 | default: | |
243 | output_addr_const (file, addr); | |
244 | } | |
245 | } | |
246 | \f | |
247 | char * | |
248 | rev_cond_name (op) | |
249 | rtx op; | |
250 | { | |
251 | switch (GET_CODE (op)) | |
252 | { | |
253 | case EQ: | |
254 | return "neq"; | |
255 | case NE: | |
256 | return "eql"; | |
257 | case LT: | |
258 | return "geq"; | |
259 | case LE: | |
260 | return "gtr"; | |
261 | case GT: | |
262 | return "leq"; | |
263 | case GE: | |
264 | return "lss"; | |
265 | case LTU: | |
266 | return "gequ"; | |
267 | case LEU: | |
268 | return "gtru"; | |
269 | case GTU: | |
270 | return "lequ"; | |
271 | case GEU: | |
272 | return "lssu"; | |
273 | ||
274 | default: | |
275 | abort (); | |
276 | } | |
277 | } |