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1bb87f28 | 1 | /* Definitions of target machine for GNU compiler, for Sun SPARC. |
b331b745 | 2 | Copyright (C) 1987, 1988, 1989, 1992, 1994 Free Software Foundation, Inc. |
1bb87f28 | 3 | Contributed by Michael Tiemann (tiemann@cygnus.com). |
7a6cf439 DE |
4 | 64 bit SPARC V9 support by Michael Tiemann, Jim Wilson, and Doug Evans, |
5 | at Cygnus Support. | |
1bb87f28 JW |
6 | |
7 | This file is part of GNU CC. | |
8 | ||
9 | GNU CC is free software; you can redistribute it and/or modify | |
10 | it under the terms of the GNU General Public License as published by | |
11 | the Free Software Foundation; either version 2, or (at your option) | |
12 | any later version. | |
13 | ||
14 | GNU CC is distributed in the hope that it will be useful, | |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
18 | ||
19 | You should have received a copy of the GNU General Public License | |
20 | along with GNU CC; see the file COPYING. If not, write to | |
21 | the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ | |
22 | ||
23 | /* Note that some other tm.h files include this one and then override | |
24 | many of the definitions that relate to assembler syntax. */ | |
25 | ||
7a6cf439 DE |
26 | /* Sparc64 support has been added by trying to allow for a day when one |
27 | compiler can handle both v8 and v9. There are a few cases where this | |
28 | isn't doable, but keep them to a minimum! Two macros are used to help out: | |
29 | TARGET_V9 is used to select (at runtime) !v9-ness or v9-ness. | |
30 | SPARCV9 is defined when compiling for sparc64 only. | |
31 | In places where it is possible to choose between the two at runtime, use | |
32 | TARGET_V9. In places where it is currently not possible to select | |
33 | between the two at runtime use SPARCV9. Again, keep uses of SPARCV9 to a | |
34 | minimum. No attempt is made to support both v8 and v9 in the v9 compiler. | |
35 | ||
36 | If a combination v8/v9 compiler is too slow, it should always be possible | |
37 | to #define TARGET_V9 as 0 (and potentially other v9-only options), and | |
38 | #undef SPARCV9. */ | |
39 | ||
bef8d8c7 JW |
40 | /* What architecture we're compiling for. This must coincide with the |
41 | `arch_type' attribute in the .md file. The names were chosen to avoid | |
42 | potential misunderstandings with the various 32 bit flavors (v7, v8, etc.): | |
43 | if we used ARCH_V9 then we'd want to use something like ARCH_V8 but that | |
44 | could be misleading and ARCH_NOTV9 sounds klunky. */ | |
45 | enum arch_type { ARCH_32BIT, ARCH_64BIT }; | |
46 | extern enum arch_type sparc_arch_type; | |
7a6cf439 DE |
47 | |
48 | /* Names to predefine in the preprocessor for this target machine. */ | |
49 | ||
50 | /* ??? The GCC_NEW_VARARGS macro is now obsolete, because gcc always uses | |
51 | the right varags.h file when bootstrapping. */ | |
52 | ||
53 | #ifdef SPARCV9 | |
54 | #define CPP_PREDEFINES \ | |
55 | "-Dsparc -Dsun -Dunix -D__sparc_v9__ \ | |
56 | -Asystem(unix) -Asystem(bsd) -Acpu(sparc64) -Amachine(sparc64)" | |
57 | #else | |
58 | #define CPP_PREDEFINES \ | |
59 | "-Dsparc -Dsun -Dunix -D__GCC_NEW_VARARGS__ \ | |
857458c4 | 60 | -Asystem(unix) -Asystem(bsd) -Acpu(sparc) -Amachine(sparc)" |
7a6cf439 DE |
61 | #endif |
62 | ||
68d69835 | 63 | #define LIB_SPEC "%{!shared:%{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p} %{g:-lg}}" |
1bb87f28 | 64 | |
98ccf8fe | 65 | /* Provide required defaults for linker -e and -d switches. */ |
1bb87f28 | 66 | |
d6f04508 | 67 | #define LINK_SPEC \ |
68d69835 JM |
68 | "%{!shared:%{!nostdlib:%{!r*:%{!e*:-e start}}} -dc -dp} %{static:-Bstatic} \ |
69 | %{assert*} %{shared:-assert pure-text}" | |
1bb87f28 JW |
70 | |
71 | /* Special flags to the Sun-4 assembler when using pipe for input. */ | |
72 | ||
b877b5ab | 73 | #define ASM_SPEC " %| %{!pg:%{!p:%{fpic:-k} %{fPIC:-k}}}" |
1bb87f28 | 74 | |
885d8175 | 75 | /* Define macros to distinguish architectures. */ |
857458c4 DE |
76 | |
77 | #ifdef SPARCV9 | |
78 | #define CPP_SPEC "\ | |
79 | %{mint64:-D__INT_MAX__=9223372036854775807LL -D__LONG_MAX__=9223372036854775807LL} \ | |
80 | %{mlong64:-D__LONG_MAX__=9223372036854775807LL} \ | |
81 | " | |
82 | #else | |
7a6cf439 DE |
83 | #define CPP_SPEC "\ |
84 | %{msparclite:-D__sparclite__} \ | |
85 | %{mf930:-D__sparclite__} %{mf934:-D__sparclite__} \ | |
86 | %{mv8:-D__sparc_v8__} \ | |
bef8d8c7 | 87 | %{msupersparc:-D__supersparc__ -D__sparc_v8__} \ |
7a6cf439 | 88 | " |
857458c4 | 89 | #endif |
885d8175 | 90 | |
b1fc14e5 RS |
91 | /* Prevent error on `-sun4' and `-target sun4' options. */ |
92 | /* This used to translate -dalign to -malign, but that is no good | |
93 | because it can't turn off the usual meaning of making debugging dumps. */ | |
1bb87f28 | 94 | |
b1fc14e5 | 95 | #define CC1_SPEC "%{sun4:} %{target:}" |
1bb87f28 | 96 | |
857458c4 DE |
97 | #ifdef SPARCV9 |
98 | #define PTRDIFF_TYPE "long long int" | |
99 | #define SIZE_TYPE "long long unsigned int" | |
100 | #else | |
101 | #define PTRDIFF_TYPE "int" | |
102 | /* In 2.4 it should work to delete this. | |
103 | #define SIZE_TYPE "int" */ | |
104 | #endif | |
7a6cf439 DE |
105 | |
106 | /* ??? This should be 32 bits for v9 but what can we do? */ | |
1bb87f28 JW |
107 | #define WCHAR_TYPE "short unsigned int" |
108 | #define WCHAR_TYPE_SIZE 16 | |
7a6cf439 | 109 | #define MAX_WCHAR_TYPE_SIZE 16 |
1bb87f28 | 110 | |
4f074454 RK |
111 | /* Show we can debug even without a frame pointer. */ |
112 | #define CAN_DEBUG_WITHOUT_FP | |
1bb87f28 | 113 | |
5b485d2c JW |
114 | /* To make profiling work with -f{pic,PIC}, we need to emit the profiling |
115 | code into the rtl. Also, if we are profiling, we cannot eliminate | |
116 | the frame pointer (because the return address will get smashed). */ | |
117 | ||
7a6cf439 DE |
118 | void sparc_override_options (); |
119 | ||
5b485d2c | 120 | #define OVERRIDE_OPTIONS \ |
7a6cf439 DE |
121 | do { \ |
122 | if (profile_flag || profile_block_flag) \ | |
123 | { \ | |
124 | if (flag_pic) \ | |
125 | { \ | |
126 | char *pic_string = (flag_pic == 1) ? "-fpic" : "-fPIC"; \ | |
127 | warning ("%s and profiling conflict: disabling %s", \ | |
128 | pic_string, pic_string); \ | |
129 | flag_pic = 0; \ | |
130 | } \ | |
131 | flag_omit_frame_pointer = 0; \ | |
132 | } \ | |
133 | SUBTARGET_OVERRIDE_OPTIONS \ | |
134 | sparc_override_options (); \ | |
135 | } while (0) | |
84ab3bfb JW |
136 | |
137 | /* This is meant to be redefined in the host dependent files */ | |
138 | #define SUBTARGET_OVERRIDE_OPTIONS | |
5b485d2c | 139 | |
1bb87f28 JW |
140 | /* These compiler options take an argument. We ignore -target for now. */ |
141 | ||
142 | #define WORD_SWITCH_TAKES_ARG(STR) \ | |
3b39b94f ILT |
143 | (DEFAULT_WORD_SWITCH_TAKES_ARG (STR) \ |
144 | || !strcmp (STR, "target") || !strcmp (STR, "assert")) | |
1bb87f28 | 145 | |
1bb87f28 JW |
146 | /* Print subsidiary information on the compiler version in use. */ |
147 | ||
148 | #define TARGET_VERSION fprintf (stderr, " (sparc)"); | |
149 | ||
150 | /* Generate DBX debugging information. */ | |
151 | ||
152 | #define DBX_DEBUGGING_INFO | |
7a6cf439 | 153 | \f |
1bb87f28 JW |
154 | /* Run-time compilation parameters selecting different hardware subsets. */ |
155 | ||
156 | extern int target_flags; | |
157 | ||
158 | /* Nonzero if we should generate code to use the fpu. */ | |
7a6cf439 DE |
159 | #define MASK_FPU 1 |
160 | #define TARGET_FPU (target_flags & MASK_FPU) | |
1bb87f28 JW |
161 | |
162 | /* Nonzero if we should use FUNCTION_EPILOGUE. Otherwise, we | |
163 | use fast return insns, but lose some generality. */ | |
7a6cf439 DE |
164 | #define MASK_EPILOGUE 2 |
165 | #define TARGET_EPILOGUE (target_flags & MASK_EPILOGUE) | |
1bb87f28 | 166 | |
95dea81f JW |
167 | /* Nonzero if we should assume that double pointers might be unaligned. |
168 | This can happen when linking gcc compiled code with other compilers, | |
169 | because the ABI only guarantees 4 byte alignment. */ | |
7a6cf439 DE |
170 | #define MASK_UNALIGNED_DOUBLES 4 |
171 | #define TARGET_UNALIGNED_DOUBLES (target_flags & MASK_UNALIGNED_DOUBLES) | |
172 | ||
bef8d8c7 JW |
173 | /* ??? Bits 0x18 are currently unused. */ |
174 | ||
175 | /* Nonzero means we should schedule code for the TMS390Z55 SuperSparc chip. */ | |
176 | #define MASK_SUPERSPARC 0x20 | |
177 | #define TARGET_SUPERSPARC (target_flags & MASK_SUPERSPARC) | |
1bb87f28 | 178 | |
885d8175 | 179 | /* Nonzero means that we should generate code for a v8 sparc. */ |
7a6cf439 DE |
180 | #define MASK_V8 0x40 |
181 | #define TARGET_V8 (target_flags & MASK_V8) | |
885d8175 | 182 | |
bc9e02ae JW |
183 | /* Nonzero means that we should generate code for a sparclite. |
184 | This enables the sparclite specific instructions, but does not affect | |
185 | whether FPU instructions are emitted. */ | |
7a6cf439 DE |
186 | #define MASK_SPARCLITE 0x80 |
187 | #define TARGET_SPARCLITE (target_flags & MASK_SPARCLITE) | |
885d8175 | 188 | |
5b485d2c | 189 | /* Nonzero means that we should generate code using a flat register window |
9a1c7cd7 JW |
190 | model, i.e. no save/restore instructions are generated, in the most |
191 | efficient manner. This code is not compatible with normal sparc code. */ | |
192 | /* This is not a user selectable option yet, because it requires changes | |
193 | that are not yet switchable via command line arguments. */ | |
5c56efde | 194 | /* ??? This flag is deprecated and may disappear at some point. */ |
7a6cf439 DE |
195 | #define MASK_FRW 0x100 |
196 | #define TARGET_FRW (target_flags & MASK_FRW) | |
5b485d2c | 197 | |
9a1c7cd7 JW |
198 | /* Nonzero means that we should generate code using a flat register window |
199 | model, i.e. no save/restore instructions are generated, but which is | |
200 | compatible with normal sparc code. This is the same as above, except | |
5c56efde DE |
201 | that the frame pointer is %i7 instead of %fp. */ |
202 | /* ??? This use to be named TARGET_FRW_COMPAT. At some point TARGET_FRW will | |
203 | go away, but until that time only use this one when necessary. | |
204 | -mflat sets both. */ | |
7a6cf439 DE |
205 | #define MASK_FLAT 0x200 |
206 | #define TARGET_FLAT (target_flags & MASK_FLAT) | |
9a1c7cd7 | 207 | |
34ad7aaf | 208 | /* Nonzero means use the registers that the Sparc ABI reserves for |
7a6cf439 DE |
209 | application software. This is the default for v8, but not v9. */ |
210 | #define MASK_APP_REGS 0x400 | |
211 | #define TARGET_APP_REGS (target_flags & MASK_APP_REGS) | |
34ad7aaf | 212 | |
8248e2bc JW |
213 | /* Option to select how quad word floating point is implemented. |
214 | When TARGET_HARD_QUAD is true, we use the hardware quad instructions. | |
215 | Otherwise, we use the SPARC ABI quad library functions. */ | |
7a6cf439 DE |
216 | #define MASK_HARD_QUAD 0x800 |
217 | #define TARGET_HARD_QUAD (target_flags & MASK_HARD_QUAD) | |
218 | ||
219 | /* Nonzero if we're compiling for 64 bit sparc. */ | |
220 | #define MASK_V9 0x1000 | |
221 | #define TARGET_V9 (target_flags & MASK_V9) | |
222 | ||
223 | /* Nonzero if ints are 64 bits. | |
224 | This automatically implies longs are 64 bits too. | |
225 | This option is for v9 only. */ | |
226 | #define MASK_INT64 0x2000 | |
227 | #define TARGET_INT64 (target_flags & MASK_INT64) | |
228 | ||
229 | /* Nonzero if longs are 64 bits. | |
230 | This option is for v9 only. */ | |
231 | #define MASK_LONG64 0x4000 | |
232 | #define TARGET_LONG64 (target_flags & MASK_LONG64) | |
233 | ||
234 | /* Nonzero if pointers are 64 bits. | |
857458c4 DE |
235 | This is not a user selectable option, though it may be one day - |
236 | so it is used to determine pointer size instead of an architecture flag. */ | |
7a6cf439 DE |
237 | #define MASK_PTR64 0x8000 |
238 | #define TARGET_PTR64 (target_flags & MASK_PTR64) | |
239 | ||
240 | /* Nonzero if we are generating code to be tested in a 32 bit environment. | |
241 | Hence, we assume the upper 32 bits of symbolic addresses are zero, and | |
242 | avoid generating %uhi and %ulo terms. | |
243 | Pointers are still 64 bits though! This option is for v9 only. */ | |
2454c8d4 | 244 | /* ??? This option is deprecated. Try to use -mmedlow. */ |
7a6cf439 DE |
245 | #define MASK_ENV32 0x10000 |
246 | #define TARGET_ENV32 (target_flags & MASK_ENV32) | |
247 | ||
248 | /* Memory models. | |
249 | Two memory models are supported: | |
250 | TARGET_MEDLOW: 32 bit address space, top 32 bits = 0 | |
857458c4 | 251 | (pointers still 64 bits) |
7a6cf439 DE |
252 | TARGET_MEDANY: 32 bit address space, data segment loaded anywhere |
253 | (use %g4 as offset). | |
254 | TARGET_FULLANY: not supported yet. | |
255 | These options are for v9 only. All mask values are nonzero so the v8 | |
256 | compiler can assume this stuff won't interfere. */ | |
257 | #define MASK_MEDLOW 0x20000 | |
258 | #define MASK_MEDANY 0x40000 | |
259 | #define MASK_FULLANY 0x60000 | |
260 | #define MASK_CODE_MODEL (MASK_MEDLOW + MASK_MEDANY) | |
261 | #define TARGET_MEDLOW ((target_flags & MASK_CODE_MODEL) == MASK_MEDLOW) | |
262 | #define TARGET_MEDANY ((target_flags & MASK_CODE_MODEL) == MASK_MEDANY) | |
263 | #define TARGET_FULLANY ((target_flags & MASK_CODE_MODEL) == MASK_FULLANY) | |
264 | ||
265 | /* ??? There are hardcoded references to this reg in the .md file. */ | |
266 | #define MEDANY_BASE_REG "%g4" | |
267 | ||
268 | /* Non-zero means use a stack bias of 2047. Stack offsets are obtained by | |
269 | adding 2047 to %sp. This option is for v9 only and is the default. */ | |
270 | #define MASK_STACK_BIAS 0x80000 | |
271 | #define TARGET_STACK_BIAS (target_flags & MASK_STACK_BIAS) | |
8248e2bc | 272 | |
1bb87f28 JW |
273 | /* Macro to define tables used to set the flags. |
274 | This is a list in braces of pairs in braces, | |
275 | each pair being { "NAME", VALUE } | |
276 | where VALUE is the bits to set or minus the bits to clear. | |
277 | An empty string NAME is used to identify the default VALUE. */ | |
278 | ||
bc9e02ae | 279 | /* The Fujitsu MB86930 is the original sparclite chip, with no fpu. |
7a6cf439 | 280 | The Fujitsu MB86934 is the recent sparclite chip, with an fpu. |
bc9e02ae JW |
281 | We use -mf930 and -mf934 options to choose which. |
282 | ??? These should perhaps be -mcpu= options. */ | |
283 | ||
1bb87f28 | 284 | #define TARGET_SWITCHES \ |
7a6cf439 DE |
285 | { {"fpu", MASK_FPU}, \ |
286 | {"no-fpu", -MASK_FPU}, \ | |
287 | {"hard-float", MASK_FPU}, \ | |
288 | {"soft-float", -MASK_FPU}, \ | |
289 | {"epilogue", MASK_EPILOGUE}, \ | |
290 | {"no-epilogue", -MASK_EPILOGUE}, \ | |
291 | {"unaligned-doubles", MASK_UNALIGNED_DOUBLES}, \ | |
292 | {"no-unaligned-doubles", -MASK_UNALIGNED_DOUBLES}, \ | |
bef8d8c7 JW |
293 | {"supersparc", MASK_SUPERSPARC+MASK_V8}, \ |
294 | {"cypress", -MASK_SUPERSPARC-MASK_V8}, \ | |
7a6cf439 DE |
295 | {"v8", MASK_V8}, \ |
296 | {"no-v8", -MASK_V8}, \ | |
297 | {"sparclite", MASK_SPARCLITE}, \ | |
298 | {"no-sparclite", -MASK_SPARCLITE}, \ | |
299 | {"f930", MASK_SPARCLITE}, \ | |
300 | {"f930", -MASK_FPU}, \ | |
301 | {"f934", MASK_SPARCLITE}, \ | |
302 | {"flat", MASK_FRW+MASK_FLAT}, \ | |
303 | {"no-flat", -(MASK_FRW+MASK_FLAT)}, \ | |
304 | {"app-regs", MASK_APP_REGS}, \ | |
305 | {"no-app-regs", -MASK_APP_REGS}, \ | |
306 | {"hard-quad-float", MASK_HARD_QUAD}, \ | |
307 | {"soft-quad-float", -MASK_HARD_QUAD}, \ | |
308 | SUBTARGET_SWITCHES \ | |
309 | V9_SWITCHES \ | |
b1fc14e5 | 310 | { "", TARGET_DEFAULT}} |
1bb87f28 | 311 | |
7a6cf439 | 312 | #define TARGET_DEFAULT (MASK_APP_REGS + MASK_EPILOGUE + MASK_FPU) |
84ab3bfb JW |
313 | |
314 | /* This is meant to be redefined in the host dependent files */ | |
315 | #define SUBTARGET_SWITCHES | |
1bb87f28 | 316 | |
7a6cf439 DE |
317 | /* ??? Until we support a combination v8/v9 compiler, the v9 specific options |
318 | are only defined for the v9 compiler. */ | |
7a6cf439 DE |
319 | #ifdef SPARCV9 |
320 | #define V9_SWITCHES \ | |
fa653e40 | 321 | /* {"v9", MASK_V9}, */ \ |
7a6cf439 DE |
322 | {"int64", MASK_INT64+MASK_LONG64}, \ |
323 | {"int32", -MASK_INT64}, \ | |
fa653e40 DE |
324 | {"int32", MASK_LONG64}, \ |
325 | {"long64", -MASK_INT64}, \ | |
7a6cf439 | 326 | {"long64", MASK_LONG64}, \ |
fa653e40 DE |
327 | {"long32", -(MASK_INT64+MASK_LONG64)}, \ |
328 | /* {"ptr64", MASK_PTR64}, */ \ | |
329 | /* {"ptr32", -MASK_PTR64}, */ \ | |
7a6cf439 | 330 | {"stack-bias", MASK_STACK_BIAS}, \ |
2454c8d4 JW |
331 | {"no-stack-bias", -MASK_STACK_BIAS}, \ |
332 | {"medlow", -MASK_CODE_MODEL}, \ | |
333 | {"medlow", MASK_MEDLOW}, \ | |
334 | {"medany", -MASK_CODE_MODEL}, \ | |
335 | {"medany", MASK_MEDANY}, | |
7a6cf439 DE |
336 | #else |
337 | #define V9_SWITCHES | |
360b1451 | 338 | #endif |
7a6cf439 DE |
339 | \f |
340 | /* target machine storage layout */ | |
341 | ||
d667538b JW |
342 | /* Define for cross-compilation to a sparc target with no TFmode from a host |
343 | with a different float format (e.g. VAX). */ | |
344 | #define REAL_ARITHMETIC | |
345 | ||
1bb87f28 JW |
346 | /* Define this if most significant bit is lowest numbered |
347 | in instructions that operate on numbered bit-fields. */ | |
348 | #define BITS_BIG_ENDIAN 1 | |
349 | ||
350 | /* Define this if most significant byte of a word is the lowest numbered. */ | |
351 | /* This is true on the SPARC. */ | |
352 | #define BYTES_BIG_ENDIAN 1 | |
353 | ||
354 | /* Define this if most significant word of a multiword number is the lowest | |
355 | numbered. */ | |
356 | /* Doubles are stored in memory with the high order word first. This | |
357 | matters when cross-compiling. */ | |
358 | #define WORDS_BIG_ENDIAN 1 | |
359 | ||
b4ac57ab | 360 | /* number of bits in an addressable storage unit */ |
1bb87f28 JW |
361 | #define BITS_PER_UNIT 8 |
362 | ||
363 | /* Width in bits of a "word", which is the contents of a machine register. | |
364 | Note that this is not necessarily the width of data type `int'; | |
365 | if using 16-bit ints on a 68000, this would still be 32. | |
366 | But on a machine with 16-bit registers, this would be 16. */ | |
7a6cf439 DE |
367 | #define BITS_PER_WORD (TARGET_V9 ? 64 : 32) |
368 | #define MAX_BITS_PER_WORD 64 | |
1bb87f28 JW |
369 | |
370 | /* Width of a word, in units (bytes). */ | |
7a6cf439 DE |
371 | #define UNITS_PER_WORD (TARGET_V9 ? 8 : 4) |
372 | #define MAX_UNITS_PER_WORD 8 | |
373 | ||
374 | /* Now define the sizes of the C data types. */ | |
375 | ||
376 | #define SHORT_TYPE_SIZE 16 | |
377 | #define INT_TYPE_SIZE (TARGET_INT64 ? 64 : 32) | |
378 | #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32) | |
379 | #define LONG_LONG_TYPE_SIZE 64 | |
380 | #define FLOAT_TYPE_SIZE 32 | |
381 | #define DOUBLE_TYPE_SIZE 64 | |
382 | ||
383 | #define MAX_INT_TYPE_SIZE 64 | |
384 | #define MAX_LONG_TYPE_SIZE 64 | |
385 | ||
386 | #ifdef SPARCV9 | |
387 | /* ??? This does not work in SunOS 4.x, so it is not enabled here. | |
388 | Instead, it is enabled in sol2.h, because it does work under Solaris. */ | |
389 | /* Define for support of TFmode long double and REAL_ARITHMETIC. | |
390 | Sparc ABI says that long double is 4 words. */ | |
391 | #define LONG_DOUBLE_TYPE_SIZE 128 | |
392 | #endif | |
1bb87f28 JW |
393 | |
394 | /* Width in bits of a pointer. | |
395 | See also the macro `Pmode' defined below. */ | |
7a6cf439 | 396 | #define POINTER_SIZE (TARGET_PTR64 ? 64 : 32) |
1bb87f28 JW |
397 | |
398 | /* Allocation boundary (in *bits*) for storing arguments in argument list. */ | |
7a6cf439 | 399 | #define PARM_BOUNDARY (TARGET_V9 ? 64 : 32) |
1bb87f28 JW |
400 | |
401 | /* Boundary (in *bits*) on which stack pointer should be aligned. */ | |
7a6cf439 | 402 | #define STACK_BOUNDARY (TARGET_V9 ? 128 : 64) |
1bb87f28 | 403 | |
10d1b70f JW |
404 | /* ALIGN FRAMES on double word boundaries */ |
405 | ||
7a6cf439 DE |
406 | #define SPARC_STACK_ALIGN(LOC) \ |
407 | (TARGET_V9 ? (((LOC)+15) & ~15) : (((LOC)+7) & ~7)) | |
10d1b70f | 408 | |
1bb87f28 JW |
409 | /* Allocation boundary (in *bits*) for the code of a function. */ |
410 | #define FUNCTION_BOUNDARY 32 | |
411 | ||
412 | /* Alignment of field after `int : 0' in a structure. */ | |
7a6cf439 DE |
413 | /* ??? Should this be based on TARGET_INT64? */ |
414 | #define EMPTY_FIELD_BOUNDARY (TARGET_V9 ? 64 : 32) | |
1bb87f28 JW |
415 | |
416 | /* Every structure's size must be a multiple of this. */ | |
417 | #define STRUCTURE_SIZE_BOUNDARY 8 | |
418 | ||
419 | /* A bitfield declared as `int' forces `int' alignment for the struct. */ | |
420 | #define PCC_BITFIELD_TYPE_MATTERS 1 | |
421 | ||
422 | /* No data type wants to be aligned rounder than this. */ | |
7a6cf439 | 423 | #define BIGGEST_ALIGNMENT (TARGET_V9 ? 128 : 64) |
1bb87f28 | 424 | |
77a02b01 JW |
425 | /* The best alignment to use in cases where we have a choice. */ |
426 | #define FASTEST_ALIGNMENT 64 | |
427 | ||
1bb87f28 JW |
428 | /* Make strings word-aligned so strcpy from constants will be faster. */ |
429 | #define CONSTANT_ALIGNMENT(EXP, ALIGN) \ | |
d2a8e680 RS |
430 | ((TREE_CODE (EXP) == STRING_CST \ |
431 | && (ALIGN) < FASTEST_ALIGNMENT) \ | |
432 | ? FASTEST_ALIGNMENT : (ALIGN)) | |
1bb87f28 JW |
433 | |
434 | /* Make arrays of chars word-aligned for the same reasons. */ | |
435 | #define DATA_ALIGNMENT(TYPE, ALIGN) \ | |
436 | (TREE_CODE (TYPE) == ARRAY_TYPE \ | |
437 | && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \ | |
77a02b01 | 438 | && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN)) |
1bb87f28 | 439 | |
b4ac57ab | 440 | /* Set this nonzero if move instructions will actually fail to work |
1bb87f28 | 441 | when given unaligned data. */ |
b4ac57ab | 442 | #define STRICT_ALIGNMENT 1 |
1bb87f28 JW |
443 | |
444 | /* Things that must be doubleword aligned cannot go in the text section, | |
445 | because the linker fails to align the text section enough! | |
7a6cf439 | 446 | Put them in the data section. This macro is only used in this file. */ |
1bb87f28 JW |
447 | #define MAX_TEXT_ALIGN 32 |
448 | ||
68d69835 JM |
449 | /* This forces all variables and constants to the data section when PIC. |
450 | This is because the SunOS 4 shared library scheme thinks everything in | |
451 | text is a function, and patches the address to point to a loader stub. */ | |
452 | /* This is defined to zero for every system which doesn't use the a.out object | |
453 | file format. */ | |
454 | #ifndef SUNOS4_SHARED_LIBRARIES | |
455 | #define SUNOS4_SHARED_LIBRARIES 0 | |
456 | #endif | |
457 | ||
7a6cf439 | 458 | /* This is defined differently for v9 in a cover file. */ |
1bb87f28 JW |
459 | #define SELECT_SECTION(T,RELOC) \ |
460 | { \ | |
461 | if (TREE_CODE (T) == VAR_DECL) \ | |
462 | { \ | |
463 | if (TREE_READONLY (T) && ! TREE_SIDE_EFFECTS (T) \ | |
ed8969fa JW |
464 | && DECL_INITIAL (T) \ |
465 | && (DECL_INITIAL (T) == error_mark_node \ | |
466 | || TREE_CONSTANT (DECL_INITIAL (T))) \ | |
1bb87f28 | 467 | && DECL_ALIGN (T) <= MAX_TEXT_ALIGN \ |
68d69835 | 468 | && ! (flag_pic && ((RELOC) || SUNOS4_SHARED_LIBRARIES))) \ |
1bb87f28 JW |
469 | text_section (); \ |
470 | else \ | |
471 | data_section (); \ | |
472 | } \ | |
473 | else if (TREE_CODE (T) == CONSTRUCTOR) \ | |
474 | { \ | |
68d69835 | 475 | if (flag_pic && ((RELOC) || SUNOS4_SHARED_LIBRARIES)) \ |
1bb87f28 JW |
476 | data_section (); \ |
477 | } \ | |
478 | else if (*tree_code_type[(int) TREE_CODE (T)] == 'c') \ | |
479 | { \ | |
480 | if ((TREE_CODE (T) == STRING_CST && flag_writable_strings) \ | |
68d69835 JM |
481 | || TYPE_ALIGN (TREE_TYPE (T)) > MAX_TEXT_ALIGN \ |
482 | || (flag_pic && ((RELOC) || SUNOS4_SHARED_LIBRARIES))) \ | |
1bb87f28 JW |
483 | data_section (); \ |
484 | else \ | |
485 | text_section (); \ | |
486 | } \ | |
487 | } | |
488 | ||
489 | /* Use text section for a constant | |
490 | unless we need more alignment than that offers. */ | |
7a6cf439 | 491 | /* This is defined differently for v9 in a cover file. */ |
1bb87f28 JW |
492 | #define SELECT_RTX_SECTION(MODE, X) \ |
493 | { \ | |
494 | if (GET_MODE_BITSIZE (MODE) <= MAX_TEXT_ALIGN \ | |
68d69835 | 495 | && ! (flag_pic && (symbolic_operand (X) || SUNOS4_SHARED_LIBRARIES))) \ |
1bb87f28 JW |
496 | text_section (); \ |
497 | else \ | |
498 | data_section (); \ | |
499 | } | |
500 | \f | |
501 | /* Standard register usage. */ | |
502 | ||
503 | /* Number of actual hardware registers. | |
504 | The hardware registers are assigned numbers for the compiler | |
505 | from 0 to just below FIRST_PSEUDO_REGISTER. | |
506 | All registers that the compiler knows about must be given numbers, | |
507 | even those that are not normally considered general registers. | |
508 | ||
7a6cf439 DE |
509 | SPARC has 32 integer registers and 32 floating point registers. |
510 | 64 bit SPARC has 32 additional fp regs, but the odd numbered ones are not | |
511 | accessible. We still account for them to simplify register computations | |
512 | (eg: in CLASS_MAX_NREGS). There are also 4 fp condition code registers, so | |
513 | 32+32+32+4 == 100. | |
514 | Register 0 is used as the integer condition code register. */ | |
1bb87f28 | 515 | |
7a6cf439 DE |
516 | #ifdef SPARCV9 |
517 | #define FIRST_PSEUDO_REGISTER 100 | |
518 | #else | |
1bb87f28 | 519 | #define FIRST_PSEUDO_REGISTER 64 |
7a6cf439 | 520 | #endif |
1bb87f28 JW |
521 | |
522 | /* 1 for registers that have pervasive standard uses | |
523 | and are not available for the register allocator. | |
5b485d2c | 524 | g0 is used for the condition code and not to represent %g0, which is |
1bb87f28 | 525 | hardwired to 0, so reg 0 is *not* fixed. |
7a6cf439 | 526 | On non-v9 systems: |
34ad7aaf JW |
527 | g1 is free to use as temporary. |
528 | g2-g4 are reserved for applications. Gcc normally uses them as | |
529 | temporaries, but this can be disabled via the -mno-app-regs option. | |
7a6cf439 DE |
530 | g5 through g7 are reserved for the operating system. |
531 | On v9 systems: | |
532 | g1 and g5 are free to use as temporaries. | |
533 | g2-g4 are reserved for applications (the compiler will not normally use | |
534 | them, but they can be used as temporaries with -mapp-regs). | |
535 | g6-g7 are reserved for the operating system. | |
536 | ??? Register 1 is used as a temporary by the 64 bit sethi pattern, so must | |
537 | currently be a fixed register until this pattern is rewritten. | |
538 | Register 1 is also used when restoring call-preserved registers in large | |
539 | stack frames. */ | |
540 | ||
541 | #ifdef SPARCV9 | |
542 | #define FIXED_REGISTERS \ | |
543 | {0, 1, 1, 1, 1, 0, 1, 1, \ | |
544 | 0, 0, 0, 0, 0, 0, 1, 0, \ | |
545 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
546 | 0, 0, 0, 0, 0, 0, 1, 1, \ | |
547 | \ | |
548 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
549 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
550 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
551 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
552 | \ | |
553 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
554 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
555 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
556 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
557 | \ | |
558 | 0, 0, 0, 0} | |
559 | #else | |
1bb87f28 | 560 | #define FIXED_REGISTERS \ |
d9ca49d5 | 561 | {0, 0, 0, 0, 0, 1, 1, 1, \ |
1bb87f28 JW |
562 | 0, 0, 0, 0, 0, 0, 1, 0, \ |
563 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
564 | 0, 0, 0, 0, 0, 0, 1, 1, \ | |
565 | \ | |
566 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
567 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
568 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
569 | 0, 0, 0, 0, 0, 0, 0, 0} | |
7a6cf439 | 570 | #endif |
1bb87f28 JW |
571 | |
572 | /* 1 for registers not available across function calls. | |
573 | These must include the FIXED_REGISTERS and also any | |
574 | registers that can be used without being saved. | |
575 | The latter must include the registers where values are returned | |
576 | and the register where structure-value addresses are passed. | |
577 | Aside from that, you can include as many other registers as you like. */ | |
7a6cf439 DE |
578 | |
579 | #ifdef SPARCV9 | |
580 | #define CALL_USED_REGISTERS \ | |
581 | {1, 1, 1, 1, 1, 1, 1, 1, \ | |
582 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
583 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
584 | 0, 0, 0, 0, 0, 0, 1, 1, \ | |
585 | \ | |
586 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
587 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
588 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
589 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
590 | \ | |
591 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
592 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
593 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
594 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
595 | \ | |
596 | 1, 1, 1, 1} | |
597 | #else | |
1bb87f28 JW |
598 | #define CALL_USED_REGISTERS \ |
599 | {1, 1, 1, 1, 1, 1, 1, 1, \ | |
600 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
601 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
602 | 0, 0, 0, 0, 0, 0, 1, 1, \ | |
603 | \ | |
604 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
605 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
606 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
607 | 1, 1, 1, 1, 1, 1, 1, 1} | |
7a6cf439 | 608 | #endif |
1bb87f28 | 609 | |
26c5587d | 610 | /* If !TARGET_FPU, then make the fp registers fixed so that they won't |
7a6cf439 | 611 | be allocated. On v9, also make the fp cc regs fixed. */ |
26c5587d JW |
612 | |
613 | #define CONDITIONAL_REGISTER_USAGE \ | |
614 | do \ | |
615 | { \ | |
616 | if (! TARGET_FPU) \ | |
617 | { \ | |
618 | int regno; \ | |
7a6cf439 | 619 | for (regno = 32; regno < FIRST_PSEUDO_REGISTER; regno++) \ |
26c5587d JW |
620 | fixed_regs[regno] = 1; \ |
621 | } \ | |
34ad7aaf JW |
622 | if (! TARGET_APP_REGS) \ |
623 | { \ | |
624 | fixed_regs[2] = 1; \ | |
625 | fixed_regs[3] = 1; \ | |
626 | fixed_regs[4] = 1; \ | |
627 | } \ | |
7a6cf439 DE |
628 | else \ |
629 | { \ | |
630 | fixed_regs[2] = 0; \ | |
631 | fixed_regs[3] = 0; \ | |
2454c8d4 | 632 | fixed_regs[4] = TARGET_MEDANY != 0; \ |
7a6cf439 | 633 | } \ |
5c56efde DE |
634 | if (TARGET_FLAT) \ |
635 | { \ | |
636 | /* Let the compiler believe the frame pointer is still \ | |
637 | %fp, but output it as %i7. */ \ | |
638 | fixed_regs[31] = 1; \ | |
639 | reg_names[FRAME_POINTER_REGNUM] = "%i7"; \ | |
640 | /* ??? This is a hack to disable leaf functions. */ \ | |
641 | global_regs[7] = 1; \ | |
642 | } \ | |
9ee6230c JW |
643 | if (profile_block_flag) \ |
644 | { \ | |
645 | /* %g1 and %g2 must be fixed, because BLOCK_PROFILER \ | |
646 | uses them. */ \ | |
647 | fixed_regs[1] = 1; \ | |
648 | fixed_regs[2] = 1; \ | |
649 | } \ | |
26c5587d JW |
650 | } \ |
651 | while (0) | |
652 | ||
1bb87f28 JW |
653 | /* Return number of consecutive hard regs needed starting at reg REGNO |
654 | to hold something of mode MODE. | |
655 | This is ordinarily the length in words of a value of mode MODE | |
656 | but can be less for certain modes in special long registers. | |
657 | ||
658 | On SPARC, ordinary registers hold 32 bits worth; | |
659 | this means both integer and floating point registers. | |
7a6cf439 DE |
660 | On v9, integer regs hold 64 bits worth; floating point regs hold |
661 | 32 bits worth (this includes the new fp regs as even the odd ones are | |
662 | included in the hard register count). */ | |
1bb87f28 | 663 | |
7a6cf439 DE |
664 | #define HARD_REGNO_NREGS(REGNO, MODE) \ |
665 | (TARGET_V9 \ | |
666 | ? ((REGNO) < 32 \ | |
667 | ? (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD \ | |
668 | : (GET_MODE_SIZE (MODE) + 3) / 4) \ | |
669 | : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) | |
1bb87f28 JW |
670 | |
671 | /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. | |
923a8d06 | 672 | See sparc.c for how we initialize this. */ |
7a6cf439 DE |
673 | extern int *hard_regno_mode_classes; |
674 | extern int sparc_mode_class[]; | |
1bb87f28 | 675 | #define HARD_REGNO_MODE_OK(REGNO, MODE) \ |
7a6cf439 | 676 | ((hard_regno_mode_classes[REGNO] & sparc_mode_class[MODE]) != 0) |
1bb87f28 JW |
677 | |
678 | /* Value is 1 if it is a good idea to tie two pseudo registers | |
679 | when one has mode MODE1 and one has mode MODE2. | |
680 | If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, | |
7a6cf439 DE |
681 | for any hard reg, then this must be 0 for correct output. |
682 | ||
683 | For V9: SFmode can't be combined with other float modes, because they can't | |
684 | be allocated to the %d registers. Also, DFmode won't fit in odd %f | |
685 | registers, but SFmode will. */ | |
1bb87f28 | 686 | #define MODES_TIEABLE_P(MODE1, MODE2) \ |
7a6cf439 DE |
687 | ((MODE1) == (MODE2) \ |
688 | || (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2) \ | |
689 | && (! TARGET_V9 \ | |
690 | || (GET_MODE_CLASS (MODE1) != MODE_FLOAT \ | |
691 | || (MODE1 != SFmode && MODE2 != SFmode))))) | |
1bb87f28 JW |
692 | |
693 | /* Specify the registers used for certain standard purposes. | |
694 | The values of these macros are register numbers. */ | |
695 | ||
696 | /* SPARC pc isn't overloaded on a register that the compiler knows about. */ | |
697 | /* #define PC_REGNUM */ | |
698 | ||
699 | /* Register to use for pushing function arguments. */ | |
700 | #define STACK_POINTER_REGNUM 14 | |
701 | ||
7a6cf439 DE |
702 | /* Actual top-of-stack address is 92/136 greater than the contents of the |
703 | stack pointer register for !v9/v9. That is: | |
704 | - !v9: 64 bytes for the in and local registers, 4 bytes for structure return | |
705 | address, and 24 bytes for the 6 register parameters. | |
706 | - v9: 128 bytes for the in and local registers + 8 bytes reserved. */ | |
1bb87f28 JW |
707 | #define STACK_POINTER_OFFSET FIRST_PARM_OFFSET(0) |
708 | ||
7a6cf439 DE |
709 | /* The stack bias (amount by which the hardware register is offset by). */ |
710 | #define SPARC_STACK_BIAS (TARGET_STACK_BIAS ? 2047 : 0) | |
711 | ||
1bb87f28 JW |
712 | /* Base register for access to local variables of the function. */ |
713 | #define FRAME_POINTER_REGNUM 30 | |
714 | ||
715 | #if 0 | |
716 | /* Register that is used for the return address. */ | |
717 | #define RETURN_ADDR_REGNUM 15 | |
718 | #endif | |
719 | ||
720 | /* Value should be nonzero if functions must have frame pointers. | |
721 | Zero means the frame pointer need not be set up (and parms | |
722 | may be accessed via the stack pointer) in functions that seem suitable. | |
723 | This is computed in `reload', in reload1.c. | |
a061b9fa | 724 | Used in flow.c, global.c, and reload1.c. |
1bb87f28 | 725 | |
a061b9fa DE |
726 | Being a non-leaf function does not mean a frame pointer is needed in the |
727 | flat window model. However, the debugger won't be able to backtrace through | |
728 | us with out it. */ | |
1bb87f28 | 729 | #define FRAME_POINTER_REQUIRED \ |
a061b9fa DE |
730 | (TARGET_FRW ? (current_function_calls_alloca || current_function_varargs \ |
731 | || !leaf_function_p ()) \ | |
5c56efde | 732 | : ! (leaf_function_p () && only_leaf_regs_used ())) |
1bb87f28 JW |
733 | |
734 | /* C statement to store the difference between the frame pointer | |
735 | and the stack pointer values immediately after the function prologue. | |
736 | ||
737 | Note, we always pretend that this is a leaf function because if | |
738 | it's not, there's no point in trying to eliminate the | |
739 | frame pointer. If it is a leaf function, we guessed right! */ | |
740 | #define INITIAL_FRAME_POINTER_OFFSET(VAR) \ | |
5c56efde | 741 | ((VAR) = (TARGET_FRW ? sparc_flat_compute_frame_size (get_frame_size ()) \ |
5b485d2c | 742 | : compute_frame_size (get_frame_size (), 1))) |
1bb87f28 JW |
743 | |
744 | /* Base register for access to arguments of the function. */ | |
5c56efde | 745 | #define ARG_POINTER_REGNUM FRAME_POINTER_REGNUM |
1bb87f28 | 746 | |
6098b63e | 747 | /* Register in which static-chain is passed to a function. This must |
7a6cf439 DE |
748 | not be a register used by the prologue. |
749 | ??? v9: Since %g2 is reserved but %g5 is available, perhaps use %g5. */ | |
6098b63e | 750 | #define STATIC_CHAIN_REGNUM 2 |
1bb87f28 JW |
751 | |
752 | /* Register which holds offset table for position-independent | |
753 | data references. */ | |
754 | ||
755 | #define PIC_OFFSET_TABLE_REGNUM 23 | |
756 | ||
757 | #define INITIALIZE_PIC initialize_pic () | |
758 | #define FINALIZE_PIC finalize_pic () | |
759 | ||
d9ca49d5 | 760 | /* Sparc ABI says that quad-precision floats and all structures are returned |
7a6cf439 DE |
761 | in memory. |
762 | For v9, all aggregates are returned in memory. */ | |
686667bf JW |
763 | #define RETURN_IN_MEMORY(TYPE) \ |
764 | (TYPE_MODE (TYPE) == BLKmode \ | |
765 | || (! TARGET_V9 && (TYPE_MODE (TYPE) == TFmode \ | |
766 | || TYPE_MODE (TYPE) == TCmode))) | |
d9ca49d5 | 767 | |
1bb87f28 JW |
768 | /* Functions which return large structures get the address |
769 | to place the wanted value at offset 64 from the frame. | |
7a6cf439 DE |
770 | Must reserve 64 bytes for the in and local registers. |
771 | v9: Functions which return large structures get the address to place the | |
772 | wanted value from an invisible first argument. */ | |
1bb87f28 JW |
773 | /* Used only in other #defines in this file. */ |
774 | #define STRUCT_VALUE_OFFSET 64 | |
775 | ||
776 | #define STRUCT_VALUE \ | |
7a6cf439 DE |
777 | (TARGET_V9 \ |
778 | ? 0 \ | |
779 | : gen_rtx (MEM, Pmode, \ | |
780 | gen_rtx (PLUS, Pmode, stack_pointer_rtx, \ | |
781 | gen_rtx (CONST_INT, VOIDmode, STRUCT_VALUE_OFFSET)))) | |
1bb87f28 | 782 | #define STRUCT_VALUE_INCOMING \ |
7a6cf439 DE |
783 | (TARGET_V9 \ |
784 | ? 0 \ | |
785 | : gen_rtx (MEM, Pmode, \ | |
786 | gen_rtx (PLUS, Pmode, frame_pointer_rtx, \ | |
787 | gen_rtx (CONST_INT, VOIDmode, STRUCT_VALUE_OFFSET)))) | |
1bb87f28 JW |
788 | \f |
789 | /* Define the classes of registers for register constraints in the | |
790 | machine description. Also define ranges of constants. | |
791 | ||
792 | One of the classes must always be named ALL_REGS and include all hard regs. | |
793 | If there is more than one class, another class must be named NO_REGS | |
794 | and contain no registers. | |
795 | ||
796 | The name GENERAL_REGS must be the name of a class (or an alias for | |
797 | another name such as ALL_REGS). This is the class of registers | |
798 | that is allowed by "g" or "r" in a register constraint. | |
799 | Also, registers outside this class are allocated only when | |
800 | instructions express preferences for them. | |
801 | ||
802 | The classes must be numbered in nondecreasing order; that is, | |
803 | a larger-numbered class must never be contained completely | |
804 | in a smaller-numbered class. | |
805 | ||
806 | For any two classes, it is very desirable that there be another | |
807 | class that represents their union. */ | |
808 | ||
7a6cf439 | 809 | /* The SPARC has two kinds of registers, general and floating point. |
24b63396 JW |
810 | |
811 | For v9 we must distinguish between the upper and lower floating point | |
812 | registers because the upper ones can't hold SFmode values. | |
813 | HARD_REGNO_MODE_OK won't help here because reload assumes that register(s) | |
814 | satisfying a group need for a class will also satisfy a single need for | |
815 | that class. EXTRA_FP_REGS is a bit of a misnomer as it covers all 64 fp | |
816 | regs. | |
817 | ||
818 | It is important that one class contains all the general and all the standard | |
819 | fp regs. Otherwise find_reg() won't properly allocate int regs for moves, | |
820 | because reg_class_record() will bias the selection in favor of fp regs, | |
821 | because reg_class_subunion[GENERAL_REGS][FP_REGS] will yield FP_REGS, | |
822 | because FP_REGS > GENERAL_REGS. | |
823 | ||
824 | It is also important that one class contain all the general and all the | |
825 | fp regs. Otherwise when spilling a DFmode reg, it may be from EXTRA_FP_REGS | |
826 | but find_reloads() may use class GENERAL_OR_FP_REGS. This will cause | |
827 | allocate_reload_reg() to bypass it causing an abort because the compiler | |
828 | thinks it doesn't have a spill reg when in fact it does. | |
829 | ||
7a6cf439 DE |
830 | v9 also has 4 floating point condition code registers. Since we don't |
831 | have a class that is the union of FPCC_REGS with either of the others, | |
832 | it is important that it appear first. Otherwise the compiler will die | |
833 | trying to compile _fixunsdfsi because fix_truncdfsi2 won't match its | |
834 | constraints. */ | |
7a6cf439 DE |
835 | |
836 | #ifdef SPARCV9 | |
24b63396 JW |
837 | enum reg_class { NO_REGS, FPCC_REGS, GENERAL_REGS, FP_REGS, EXTRA_FP_REGS, |
838 | GENERAL_OR_FP_REGS, GENERAL_OR_EXTRA_FP_REGS, | |
7a6cf439 DE |
839 | ALL_REGS, LIM_REG_CLASSES }; |
840 | #else | |
1bb87f28 | 841 | enum reg_class { NO_REGS, GENERAL_REGS, FP_REGS, ALL_REGS, LIM_REG_CLASSES }; |
7a6cf439 | 842 | #endif |
1bb87f28 JW |
843 | |
844 | #define N_REG_CLASSES (int) LIM_REG_CLASSES | |
845 | ||
846 | /* Give names of register classes as strings for dump file. */ | |
847 | ||
7a6cf439 | 848 | #ifdef SPARCV9 |
1bb87f28 | 849 | #define REG_CLASS_NAMES \ |
24b63396 JW |
850 | { "NO_REGS", "FPCC_REGS", "GENERAL_REGS", "FP_REGS", "EXTRA_FP_REGS", \ |
851 | "GENERAL_OR_FP_REGS", "GENERAL_OR_EXTRA_FP_REGS", "ALL_REGS" } | |
7a6cf439 DE |
852 | #else |
853 | #define REG_CLASS_NAMES \ | |
24b63396 | 854 | { "NO_REGS", "GENERAL_REGS", "FP_REGS", "ALL_REGS" } |
7a6cf439 | 855 | #endif |
1bb87f28 JW |
856 | |
857 | /* Define which registers fit in which classes. | |
858 | This is an initializer for a vector of HARD_REG_SET | |
859 | of length N_REG_CLASSES. */ | |
860 | ||
7a6cf439 DE |
861 | #ifdef SPARCV9 |
862 | #define REG_CLASS_CONTENTS \ | |
24b63396 JW |
863 | {{0, 0, 0, 0}, {0, 0, 0, 0xf}, {-2, 0, 0, 0}, \ |
864 | {0, -1, 0, 0}, {0, -1, -1, 0}, {-2, -1, 0, 0}, {-2, -1, -1, 0}, \ | |
865 | {-2, -1, -1, 0xf}} | |
7a6cf439 | 866 | #else |
1bb87f28 JW |
867 | #if 0 && defined (__GNUC__) |
868 | #define REG_CLASS_CONTENTS {0LL, 0xfffffffeLL, 0xffffffff00000000LL, 0xfffffffffffffffeLL} | |
869 | #else | |
870 | #define REG_CLASS_CONTENTS {{0, 0}, {-2, 0}, {0, -1}, {-2, -1}} | |
871 | #endif | |
7a6cf439 | 872 | #endif |
1bb87f28 JW |
873 | |
874 | /* The same information, inverted: | |
875 | Return the class number of the smallest class containing | |
876 | reg number REGNO. This could be a conditional expression | |
877 | or could index an array. */ | |
878 | ||
7a6cf439 | 879 | #ifdef SPARCV9 |
24b63396 JW |
880 | #define REGNO_REG_CLASS(REGNO) \ |
881 | ((REGNO) == 0 ? NO_REGS \ | |
882 | : (REGNO) < 32 ? GENERAL_REGS \ | |
883 | : (REGNO) < 64 ? FP_REGS \ | |
884 | : (REGNO) < 96 ? EXTRA_FP_REGS \ | |
885 | : FPCC_REGS) | |
7a6cf439 | 886 | #else |
1bb87f28 JW |
887 | #define REGNO_REG_CLASS(REGNO) \ |
888 | ((REGNO) >= 32 ? FP_REGS : (REGNO) == 0 ? NO_REGS : GENERAL_REGS) | |
7a6cf439 | 889 | #endif |
1bb87f28 | 890 | |
7a6cf439 | 891 | /* This is the order in which to allocate registers normally. |
51f0e748 JW |
892 | |
893 | We put %f0/%f1 last among the float registers, so as to make it more | |
6a4bb1fa | 894 | likely that a pseudo-register which dies in the float return register |
51f0e748 | 895 | will get allocated to the float return register, thus saving a move |
7a6cf439 DE |
896 | instruction at the end of the function. |
897 | ||
898 | On v9, the float registers are ordered a little "funny" because some | |
899 | of them (%f16-%f47) are call-preserved. */ | |
900 | #ifdef SPARCV9 | |
901 | #define REG_ALLOC_ORDER \ | |
902 | { 8, 9, 10, 11, 12, 13, \ | |
903 | 15, 16, 17, 18, 19, 20, 21, 22, \ | |
904 | 23, 24, 25, 26, 27, 28, 29, 31, \ | |
905 | 34, 35, 36, 37, 38, 39, /* %f2-%f7 */ \ | |
906 | 40, 41, 42, 43, 44, 45, 46, 47, /* %f8-%f15 */ \ | |
907 | 80, 81, 82, 83, 84, 85, 86, 87, /* %f48-%f55 */ \ | |
908 | 88, 89, 90, 91, 92, 93, 94, 95, /* %f56-%f63 */ \ | |
909 | 48, 49, 50, 51, 52, 53, 54, 55, /* %f16-%f23 */ \ | |
910 | 56, 57, 58, 59, 60, 61, 62, 63, /* %f24-%f31 */ \ | |
911 | 64, 65, 66, 67, 68, 69, 70, 71, /* %f32-%f39 */ \ | |
912 | 72, 73, 74, 75, 76, 77, 78, 79, /* %f40-%f47 */ \ | |
913 | 32, 33, /* %f0,%f1 */ \ | |
914 | 96, 97, 98, 99, /* %fcc0-3 */ \ | |
915 | 1, 5, 2, 3, 4, 6, 7, 0, 14, 30} | |
916 | #else | |
1bb87f28 | 917 | #define REG_ALLOC_ORDER \ |
b4ac57ab RS |
918 | { 8, 9, 10, 11, 12, 13, 2, 3, \ |
919 | 15, 16, 17, 18, 19, 20, 21, 22, \ | |
920 | 23, 24, 25, 26, 27, 28, 29, 31, \ | |
51f0e748 | 921 | 34, 35, 36, 37, 38, 39, \ |
1bb87f28 JW |
922 | 40, 41, 42, 43, 44, 45, 46, 47, \ |
923 | 48, 49, 50, 51, 52, 53, 54, 55, \ | |
924 | 56, 57, 58, 59, 60, 61, 62, 63, \ | |
51f0e748 | 925 | 32, 33, \ |
4b69d2a3 | 926 | 1, 4, 5, 6, 7, 0, 14, 30} |
7a6cf439 | 927 | #endif |
1bb87f28 JW |
928 | |
929 | /* This is the order in which to allocate registers for | |
930 | leaf functions. If all registers can fit in the "i" registers, | |
7a6cf439 DE |
931 | then we have the possibility of having a leaf function. |
932 | v9: The floating point registers are ordered a little "funny" because some | |
933 | of them (%f16-%f47) are call-preserved. */ | |
934 | #ifdef SPARCV9 | |
935 | #define REG_LEAF_ALLOC_ORDER \ | |
936 | { 24, 25, 26, 27, 28, 29, \ | |
937 | 15, 8, 9, 10, 11, 12, 13, \ | |
938 | 16, 17, 18, 19, 20, 21, 22, 23, \ | |
939 | 34, 35, 36, 37, 38, 39, \ | |
940 | 40, 41, 42, 43, 44, 45, 46, 47, \ | |
941 | 80, 81, 82, 83, 84, 85, 86, 87, \ | |
942 | 88, 89, 90, 91, 92, 93, 94, 95, \ | |
943 | 48, 49, 50, 51, 52, 53, 54, 55, \ | |
944 | 56, 57, 58, 59, 60, 61, 62, 63, \ | |
945 | 64, 65, 66, 67, 68, 69, 70, 71, \ | |
946 | 72, 73, 74, 75, 76, 77, 78, 79, \ | |
947 | 32, 33, \ | |
948 | 96, 97, 98, 99, \ | |
949 | 1, 5, 2, 3, 4, 6, 7, 0, 14, 30, 31} | |
950 | #else | |
1bb87f28 JW |
951 | #define REG_LEAF_ALLOC_ORDER \ |
952 | { 2, 3, 24, 25, 26, 27, 28, 29, \ | |
953 | 15, 8, 9, 10, 11, 12, 13, \ | |
954 | 16, 17, 18, 19, 20, 21, 22, 23, \ | |
51f0e748 | 955 | 34, 35, 36, 37, 38, 39, \ |
1bb87f28 JW |
956 | 40, 41, 42, 43, 44, 45, 46, 47, \ |
957 | 48, 49, 50, 51, 52, 53, 54, 55, \ | |
958 | 56, 57, 58, 59, 60, 61, 62, 63, \ | |
51f0e748 | 959 | 32, 33, \ |
4b69d2a3 | 960 | 1, 4, 5, 6, 7, 0, 14, 30, 31} |
7a6cf439 | 961 | #endif |
1bb87f28 JW |
962 | |
963 | #define ORDER_REGS_FOR_LOCAL_ALLOC order_regs_for_local_alloc () | |
964 | ||
5c56efde DE |
965 | /* ??? %g7 is not a leaf register to effectively #undef LEAF_REGISTERS when |
966 | -mflat is used. Function only_leaf_regs_used will return 0 if a global | |
967 | register is used and is not permitted in a leaf function. We make %g7 | |
968 | a global reg if -mflat and voila. Since %g7 is a system register and is | |
969 | fixed it won't be used by gcc anyway. */ | |
7a6cf439 DE |
970 | #ifdef SPARCV9 |
971 | #define LEAF_REGISTERS \ | |
972 | { 1, 1, 1, 1, 1, 1, 1, 0, \ | |
973 | 0, 0, 0, 0, 0, 0, 1, 0, \ | |
974 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
975 | 1, 1, 1, 1, 1, 1, 0, 1, \ | |
976 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
977 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
978 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
979 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
980 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
981 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
982 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
983 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
984 | 1, 1, 1, 1} | |
985 | #else | |
1bb87f28 | 986 | #define LEAF_REGISTERS \ |
5c56efde | 987 | { 1, 1, 1, 1, 1, 1, 1, 0, \ |
1bb87f28 JW |
988 | 0, 0, 0, 0, 0, 0, 1, 0, \ |
989 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
990 | 1, 1, 1, 1, 1, 1, 0, 1, \ | |
991 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
992 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
993 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
4b69d2a3 | 994 | 1, 1, 1, 1, 1, 1, 1, 1} |
7a6cf439 | 995 | #endif |
1bb87f28 JW |
996 | |
997 | extern char leaf_reg_remap[]; | |
998 | #define LEAF_REG_REMAP(REGNO) (leaf_reg_remap[REGNO]) | |
1bb87f28 | 999 | |
1bb87f28 JW |
1000 | /* The class value for index registers, and the one for base regs. */ |
1001 | #define INDEX_REG_CLASS GENERAL_REGS | |
1002 | #define BASE_REG_CLASS GENERAL_REGS | |
1003 | ||
24b63396 JW |
1004 | /* Local macro to handle the two v9 classes of FP regs. */ |
1005 | #ifdef SPARCV9 | |
1006 | #define FP_REG_CLASS_P(CLASS) ((CLASS) == FP_REGS || (CLASS) == EXTRA_FP_REGS) | |
1007 | #else | |
1008 | #define FP_REG_CLASS_P(CLASS) ((CLASS) == FP_REGS) | |
1009 | #endif | |
1010 | ||
1bb87f28 JW |
1011 | /* Get reg_class from a letter such as appears in the machine description. */ |
1012 | ||
7a6cf439 DE |
1013 | #ifdef SPARCV9 |
1014 | #define REG_CLASS_FROM_LETTER(C) \ | |
24b63396 JW |
1015 | ((C) == 'f' ? FP_REGS \ |
1016 | : (C) == 'e' ? EXTRA_FP_REGS \ | |
1017 | : (C) == 'c' ? FPCC_REGS \ | |
1018 | : NO_REGS) | |
7a6cf439 | 1019 | #else |
24b63396 JW |
1020 | /* Coerce v9's 'e' class to 'f', so we can use 'e' in the .md file for |
1021 | v8 and v9. */ | |
1bb87f28 | 1022 | #define REG_CLASS_FROM_LETTER(C) \ |
24b63396 | 1023 | ((C) == 'f' ? FP_REGS : (C) == 'e' ? FP_REGS : NO_REGS) |
7a6cf439 | 1024 | #endif |
1bb87f28 JW |
1025 | |
1026 | /* The letters I, J, K, L and M in a register constraint string | |
1027 | can be used to stand for particular ranges of immediate operands. | |
1028 | This macro defines what the ranges are. | |
1029 | C is the letter, and VALUE is a constant value. | |
1030 | Return 1 if VALUE is in the range specified by C. | |
1031 | ||
1032 | For SPARC, `I' is used for the range of constants an insn | |
1033 | can actually contain. | |
1034 | `J' is used for the range which is just zero (since that is R0). | |
9ad2c692 | 1035 | `K' is used for constants which can be loaded with a single sethi insn. */ |
1bb87f28 JW |
1036 | |
1037 | #define SMALL_INT(X) ((unsigned) (INTVAL (X) + 0x1000) < 0x2000) | |
1038 | ||
1039 | #define CONST_OK_FOR_LETTER_P(VALUE, C) \ | |
1040 | ((C) == 'I' ? (unsigned) ((VALUE) + 0x1000) < 0x2000 \ | |
1041 | : (C) == 'J' ? (VALUE) == 0 \ | |
1042 | : (C) == 'K' ? ((VALUE) & 0x3ff) == 0 \ | |
1043 | : 0) | |
1044 | ||
1045 | /* Similar, but for floating constants, and defining letters G and H. | |
1046 | Here VALUE is the CONST_DOUBLE rtx itself. */ | |
1047 | ||
1048 | #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \ | |
96f69de5 | 1049 | ((C) == 'G' ? fp_zero_operand (VALUE) \ |
1bb87f28 JW |
1050 | : (C) == 'H' ? arith_double_operand (VALUE, DImode) \ |
1051 | : 0) | |
1052 | ||
1053 | /* Given an rtx X being reloaded into a reg required to be | |
1054 | in class CLASS, return the class of reg to actually use. | |
1055 | In general this is just CLASS; but on some machines | |
1056 | in some cases it is preferable to use a more restrictive class. */ | |
2b9a9aea JW |
1057 | /* We can't load constants into FP registers. We can't load any FP constant |
1058 | if an 'E' constraint fails to match it. */ | |
1059 | #define PREFERRED_RELOAD_CLASS(X,CLASS) \ | |
1060 | (CONSTANT_P (X) \ | |
24b63396 | 1061 | && (FP_REG_CLASS_P (CLASS) \ |
2b9a9aea JW |
1062 | || (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \ |
1063 | && (HOST_FLOAT_FORMAT != IEEE_FLOAT_FORMAT \ | |
1064 | || HOST_BITS_PER_INT != BITS_PER_WORD))) \ | |
1065 | ? NO_REGS : (CLASS)) | |
1bb87f28 JW |
1066 | |
1067 | /* Return the register class of a scratch register needed to load IN into | |
1068 | a register of class CLASS in MODE. | |
1069 | ||
1070 | On the SPARC, when PIC, we need a temporary when loading some addresses | |
ae51bd97 | 1071 | into a register. |
1bb87f28 | 1072 | |
ae51bd97 JW |
1073 | Also, we need a temporary when loading/storing a HImode/QImode value |
1074 | between memory and the FPU registers. This can happen when combine puts | |
1075 | a paradoxical subreg in a float/fix conversion insn. */ | |
1076 | ||
1077 | #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, IN) \ | |
24b63396 JW |
1078 | ((FP_REG_CLASS_P (CLASS) && ((MODE) == HImode || (MODE) == QImode) \ |
1079 | && (GET_CODE (IN) == MEM \ | |
1080 | || ((GET_CODE (IN) == REG || GET_CODE (IN) == SUBREG) \ | |
1081 | && true_regnum (IN) == -1))) ? GENERAL_REGS : NO_REGS) | |
ae51bd97 JW |
1082 | |
1083 | #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, IN) \ | |
24b63396 JW |
1084 | ((FP_REG_CLASS_P (CLASS) && ((MODE) == HImode || (MODE) == QImode) \ |
1085 | && (GET_CODE (IN) == MEM \ | |
1086 | || ((GET_CODE (IN) == REG || GET_CODE (IN) == SUBREG) \ | |
1087 | && true_regnum (IN) == -1))) ? GENERAL_REGS : NO_REGS) | |
1bb87f28 | 1088 | |
b924cef0 JW |
1089 | /* On SPARC it is not possible to directly move data between |
1090 | GENERAL_REGS and FP_REGS. */ | |
24b63396 JW |
1091 | #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \ |
1092 | (FP_REG_CLASS_P (CLASS1) != FP_REG_CLASS_P (CLASS2)) | |
b924cef0 | 1093 | |
55be783d JW |
1094 | /* Return the stack location to use for secondary memory needed reloads. |
1095 | We want to use the reserved location just below the frame pointer. | |
1096 | However, we must ensure that there is a frame, so use assign_stack_local | |
1097 | if the frame size is zero. */ | |
fe1f7f24 | 1098 | #define SECONDARY_MEMORY_NEEDED_RTX(MODE) \ |
55be783d | 1099 | (get_frame_size () == 0 \ |
fb3eb6f6 | 1100 | ? assign_stack_local (MODE, GET_MODE_SIZE (MODE), 0) \ |
55be783d JW |
1101 | : gen_rtx (MEM, MODE, gen_rtx (PLUS, Pmode, frame_pointer_rtx, \ |
1102 | GEN_INT (STARTING_FRAME_OFFSET)))) | |
fe1f7f24 | 1103 | |
7a6cf439 DE |
1104 | /* Get_secondary_mem widens it's argument to BITS_PER_WORD which loses on v9 |
1105 | because the movsi and movsf patterns don't handle r/f moves. | |
1106 | For v8 we copy the default definition. */ | |
1107 | #define SECONDARY_MEMORY_NEEDED_MODE(MODE) \ | |
1108 | (TARGET_V9 \ | |
fb3eb6f6 JW |
1109 | ? (GET_MODE_BITSIZE (MODE) < 32 \ |
1110 | ? mode_for_size (32, GET_MODE_CLASS (MODE), 0) \ | |
7a6cf439 | 1111 | : MODE) \ |
fb3eb6f6 JW |
1112 | : (GET_MODE_BITSIZE (MODE) < BITS_PER_WORD \ |
1113 | ? mode_for_size (BITS_PER_WORD, GET_MODE_CLASS (MODE), 0) \ | |
7a6cf439 DE |
1114 | : MODE)) |
1115 | ||
1bb87f28 JW |
1116 | /* Return the maximum number of consecutive registers |
1117 | needed to represent mode MODE in a register of class CLASS. */ | |
1118 | /* On SPARC, this is the size of MODE in words. */ | |
1119 | #define CLASS_MAX_NREGS(CLASS, MODE) \ | |
24b63396 | 1120 | (FP_REG_CLASS_P (CLASS) ? (GET_MODE_SIZE (MODE) + 3) / 4 \ |
7a6cf439 | 1121 | : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) |
1bb87f28 JW |
1122 | \f |
1123 | /* Stack layout; function entry, exit and calling. */ | |
1124 | ||
1125 | /* Define the number of register that can hold parameters. | |
7a6cf439 DE |
1126 | These two macros are used only in other macro definitions below. |
1127 | MODE is the mode of the argument. | |
1128 | !v9: All args are passed in %o0-%o5. | |
1129 | v9: Non-float args are passed in %o0-5 and float args are passed in | |
1130 | %f0-%f15. */ | |
1131 | #define NPARM_REGS(MODE) \ | |
1132 | (TARGET_V9 ? (GET_MODE_CLASS (MODE) == MODE_FLOAT ? 16 : 6) : 6) | |
1bb87f28 JW |
1133 | |
1134 | /* Define this if pushing a word on the stack | |
1135 | makes the stack pointer a smaller address. */ | |
1136 | #define STACK_GROWS_DOWNWARD | |
1137 | ||
1138 | /* Define this if the nominal address of the stack frame | |
1139 | is at the high-address end of the local variables; | |
1140 | that is, each additional local variable allocated | |
1141 | goes at a more negative offset in the frame. */ | |
1142 | #define FRAME_GROWS_DOWNWARD | |
1143 | ||
1144 | /* Offset within stack frame to start allocating local variables at. | |
1145 | If FRAME_GROWS_DOWNWARD, this is the offset to the END of the | |
1146 | first local allocated. Otherwise, it is the offset to the BEGINNING | |
1147 | of the first local allocated. */ | |
7238ce3a JW |
1148 | /* This allows space for one TFmode floating point value. */ |
1149 | #define STARTING_FRAME_OFFSET \ | |
7a6cf439 DE |
1150 | (TARGET_V9 ? (SPARC_STACK_BIAS - 16) \ |
1151 | : (-SPARC_STACK_ALIGN (LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT))) | |
1bb87f28 JW |
1152 | |
1153 | /* If we generate an insn to push BYTES bytes, | |
1154 | this says how many the stack pointer really advances by. | |
1155 | On SPARC, don't define this because there are no push insns. */ | |
1156 | /* #define PUSH_ROUNDING(BYTES) */ | |
1157 | ||
1158 | /* Offset of first parameter from the argument pointer register value. | |
7a6cf439 DE |
1159 | !v9: This is 64 for the ins and locals, plus 4 for the struct-return reg |
1160 | even if this function isn't going to use it. | |
1161 | v9: This is 128 for the ins and locals, plus a reserved space of 8. */ | |
1162 | #define FIRST_PARM_OFFSET(FNDECL) \ | |
1163 | (TARGET_V9 ? (SPARC_STACK_BIAS + 136) \ | |
1164 | : (STRUCT_VALUE_OFFSET + UNITS_PER_WORD)) | |
1bb87f28 JW |
1165 | |
1166 | /* When a parameter is passed in a register, stack space is still | |
1167 | allocated for it. */ | |
7a6cf439 DE |
1168 | #ifndef SPARCV9 |
1169 | #define REG_PARM_STACK_SPACE(DECL) (NPARM_REGS (SImode) * UNITS_PER_WORD) | |
1170 | #endif | |
1bb87f28 JW |
1171 | |
1172 | /* Keep the stack pointer constant throughout the function. | |
b4ac57ab | 1173 | This is both an optimization and a necessity: longjmp |
1bb87f28 JW |
1174 | doesn't behave itself when the stack pointer moves within |
1175 | the function! */ | |
1176 | #define ACCUMULATE_OUTGOING_ARGS | |
1177 | ||
1178 | /* Value is the number of bytes of arguments automatically | |
1179 | popped when returning from a subroutine call. | |
1180 | FUNTYPE is the data type of the function (as a tree), | |
1181 | or for a library call it is an identifier node for the subroutine name. | |
1182 | SIZE is the number of bytes of arguments passed on the stack. */ | |
1183 | ||
1184 | #define RETURN_POPS_ARGS(FUNTYPE,SIZE) 0 | |
1185 | ||
5b485d2c JW |
1186 | /* Some subroutine macros specific to this machine. |
1187 | When !TARGET_FPU, put float return values in the general registers, | |
1188 | since we don't have any fp registers. */ | |
1bb87f28 | 1189 | #define BASE_RETURN_VALUE_REG(MODE) \ |
7a6cf439 DE |
1190 | (TARGET_V9 ? (TARGET_FPU && GET_MODE_CLASS (MODE) == MODE_FLOAT ? 32 : 8) \ |
1191 | : (((MODE) == SFmode || (MODE) == DFmode) && TARGET_FPU ? 32 : 8)) | |
1bb87f28 | 1192 | #define BASE_OUTGOING_VALUE_REG(MODE) \ |
7a6cf439 DE |
1193 | (TARGET_V9 ? (TARGET_FPU && GET_MODE_CLASS (MODE) == MODE_FLOAT ? 32 \ |
1194 | : TARGET_FRW ? 8 : 24) \ | |
1195 | : (((MODE) == SFmode || (MODE) == DFmode) && TARGET_FPU ? 32 \ | |
1196 | : (TARGET_FRW ? 8 : 24))) | |
1197 | #define BASE_PASSING_ARG_REG(MODE) \ | |
1198 | (TARGET_V9 ? (TARGET_FPU && GET_MODE_CLASS (MODE) == MODE_FLOAT ? 32 : 8) \ | |
1199 | : (8)) | |
1200 | #define BASE_INCOMING_ARG_REG(MODE) \ | |
1201 | (TARGET_V9 ? (TARGET_FPU && GET_MODE_CLASS (MODE) == MODE_FLOAT ? 32 \ | |
1202 | : TARGET_FRW ? 8 : 24) \ | |
1203 | : (TARGET_FRW ? 8 : 24)) | |
1bb87f28 | 1204 | |
92ea370b TW |
1205 | /* Define this macro if the target machine has "register windows". This |
1206 | C expression returns the register number as seen by the called function | |
1207 | corresponding to register number OUT as seen by the calling function. | |
1208 | Return OUT if register number OUT is not an outbound register. */ | |
1209 | ||
1210 | #define INCOMING_REGNO(OUT) \ | |
1211 | ((TARGET_FRW || (OUT) < 8 || (OUT) > 15) ? (OUT) : (OUT) + 16) | |
1212 | ||
1213 | /* Define this macro if the target machine has "register windows". This | |
1214 | C expression returns the register number as seen by the calling function | |
1215 | corresponding to register number IN as seen by the called function. | |
1216 | Return IN if register number IN is not an inbound register. */ | |
1217 | ||
1218 | #define OUTGOING_REGNO(IN) \ | |
1219 | ((TARGET_FRW || (IN) < 24 || (IN) > 31) ? (IN) : (IN) - 16) | |
1220 | ||
1bb87f28 JW |
1221 | /* Define how to find the value returned by a function. |
1222 | VALTYPE is the data type of the value (as a tree). | |
1223 | If the precise function being called is known, FUNC is its FUNCTION_DECL; | |
1224 | otherwise, FUNC is 0. */ | |
1225 | ||
1226 | /* On SPARC the value is found in the first "output" register. */ | |
1227 | ||
1228 | #define FUNCTION_VALUE(VALTYPE, FUNC) \ | |
1229 | gen_rtx (REG, TYPE_MODE (VALTYPE), BASE_RETURN_VALUE_REG (TYPE_MODE (VALTYPE))) | |
1230 | ||
1231 | /* But the called function leaves it in the first "input" register. */ | |
1232 | ||
1233 | #define FUNCTION_OUTGOING_VALUE(VALTYPE, FUNC) \ | |
1234 | gen_rtx (REG, TYPE_MODE (VALTYPE), BASE_OUTGOING_VALUE_REG (TYPE_MODE (VALTYPE))) | |
1235 | ||
1236 | /* Define how to find the value returned by a library function | |
1237 | assuming the value has mode MODE. */ | |
1238 | ||
1239 | #define LIBCALL_VALUE(MODE) \ | |
1240 | gen_rtx (REG, MODE, BASE_RETURN_VALUE_REG (MODE)) | |
1241 | ||
1242 | /* 1 if N is a possible register number for a function value | |
1243 | as seen by the caller. | |
1244 | On SPARC, the first "output" reg is used for integer values, | |
1245 | and the first floating point register is used for floating point values. */ | |
1246 | ||
1247 | #define FUNCTION_VALUE_REGNO_P(N) ((N) == 8 || (N) == 32) | |
1248 | ||
34aaacec JW |
1249 | /* Define the size of space to allocate for the return value of an |
1250 | untyped_call. */ | |
1251 | ||
1252 | #define APPLY_RESULT_SIZE 16 | |
1253 | ||
1bb87f28 | 1254 | /* 1 if N is a possible register number for function argument passing. |
7a6cf439 | 1255 | On SPARC, these are the "output" registers. v9 also uses %f0-%f15. */ |
1bb87f28 | 1256 | |
7a6cf439 DE |
1257 | #define FUNCTION_ARG_REGNO_P(N) \ |
1258 | (TARGET_V9 ? (((N) < 14 && (N) > 7) || (N) > 31 && (N) < 48) \ | |
1259 | : ((N) < 14 && (N) > 7)) | |
1bb87f28 JW |
1260 | \f |
1261 | /* Define a data type for recording info about an argument list | |
1262 | during the scan of that argument list. This data type should | |
1263 | hold all necessary information about the function itself | |
1264 | and about the args processed so far, enough to enable macros | |
1265 | such as FUNCTION_ARG to determine where the next arg should go. | |
1266 | ||
7a6cf439 | 1267 | On SPARC (!v9), this is a single integer, which is a number of words |
1bb87f28 JW |
1268 | of arguments scanned so far (including the invisible argument, |
1269 | if any, which holds the structure-value-address). | |
7a6cf439 DE |
1270 | Thus 7 or more means all following args should go on the stack. |
1271 | ||
1272 | For v9, we record how many of each type has been passed. Different | |
1273 | types get passed differently. | |
1274 | ||
1275 | - Float args are passed in %f0-15, after which they go to the stack | |
1276 | where floats and doubles are passed 8 byte aligned and long doubles | |
1277 | are passed 16 byte aligned. | |
1278 | - All aggregates are passed by reference. The callee copies | |
1279 | the structure if necessary, except if stdarg/varargs and the struct | |
1280 | matches the ellipse in which case the caller makes a copy. | |
1281 | - Any non-float argument might be split between memory and reg %o5. | |
1282 | ??? I don't think this can ever happen now that structs are no | |
1283 | longer passed in regs. | |
1284 | ||
1285 | For v9 return values: | |
1286 | ||
1287 | - For all aggregates, the caller allocates space for the return value, | |
1288 | and passes the pointer as an implicit first argument, which is | |
1289 | allocated like all other arguments. | |
1290 | - The unimp instruction stuff for structure returns is gone. */ | |
1291 | ||
1292 | #ifdef SPARCV9 | |
1293 | enum sparc_arg_class { SPARC_ARG_INT = 0, SPARC_ARG_FLOAT = 1 }; | |
1294 | struct sparc_args { | |
1295 | int arg_count[2]; /* must be int! (for __builtin_args_info) */ | |
1296 | }; | |
1297 | #define CUMULATIVE_ARGS struct sparc_args | |
1298 | ||
1299 | /* Return index into CUMULATIVE_ARGS. */ | |
1300 | ||
1301 | #define GET_SPARC_ARG_CLASS(MODE) \ | |
1302 | (GET_MODE_CLASS (MODE) == MODE_FLOAT ? SPARC_ARG_FLOAT : SPARC_ARG_INT) | |
1bb87f28 | 1303 | |
7a6cf439 DE |
1304 | /* Round a register number up to a proper boundary for an arg of mode MODE. |
1305 | This macro is only used in this file. | |
1306 | ||
1307 | The "& (0x10000 - ...)" is used to round up to the next appropriate reg. */ | |
1308 | ||
1309 | #define ROUND_REG(CUM, MODE) \ | |
1310 | (GET_MODE_CLASS (MODE) != MODE_FLOAT \ | |
1311 | ? (CUM).arg_count[(int) GET_SPARC_ARG_CLASS (MODE)] \ | |
1312 | : ((CUM).arg_count[(int) GET_SPARC_ARG_CLASS (MODE)] \ | |
1313 | + GET_MODE_UNIT_SIZE (MODE) / 4 - 1) \ | |
1314 | & (0x10000 - GET_MODE_UNIT_SIZE (MODE) / 4)) | |
1315 | ||
1316 | #define ROUND_ADVANCE(SIZE) \ | |
1317 | (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) | |
1318 | ||
1319 | #else /* ! SPARCV9 */ | |
1bb87f28 JW |
1320 | #define CUMULATIVE_ARGS int |
1321 | ||
7a6cf439 DE |
1322 | #define ROUND_REG(CUM, MODE) (CUM) |
1323 | ||
1bb87f28 | 1324 | #define ROUND_ADVANCE(SIZE) \ |
b1fc14e5 | 1325 | ((SIZE + UNITS_PER_WORD - 1) / UNITS_PER_WORD) |
7a6cf439 | 1326 | #endif /* ! SPARCV9 */ |
b1fc14e5 | 1327 | |
1bb87f28 JW |
1328 | /* Initialize a variable CUM of type CUMULATIVE_ARGS |
1329 | for a call to a function whose data type is FNTYPE. | |
1330 | For a library call, FNTYPE is 0. | |
1331 | ||
1332 | On SPARC, the offset always starts at 0: the first parm reg is always | |
1333 | the same reg. */ | |
1334 | ||
7a6cf439 DE |
1335 | #ifdef SPARCV9 |
1336 | extern int sparc_arg_count,sparc_n_named_args; | |
1337 | #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME) \ | |
1338 | do { \ | |
1339 | (CUM).arg_count[(int) SPARC_ARG_INT] = 0; \ | |
1340 | (CUM).arg_count[(int) SPARC_ARG_FLOAT] = 0; \ | |
1341 | sparc_arg_count = 0; \ | |
1342 | sparc_n_named_args = \ | |
1343 | ((FNTYPE) && TYPE_ARG_TYPES (FNTYPE) \ | |
1344 | ? (list_length (TYPE_ARG_TYPES (FNTYPE)) \ | |
1345 | + (TREE_CODE (TREE_TYPE (FNTYPE)) == RECORD_TYPE \ | |
1346 | || TREE_CODE (TREE_TYPE (FNTYPE)) == UNION_TYPE)) \ | |
1347 | /* Can't tell, treat 'em all as named. */ \ | |
1348 | : 10000); \ | |
1349 | } while (0) | |
1350 | #else | |
1bb87f28 | 1351 | #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME) ((CUM) = 0) |
7a6cf439 | 1352 | #endif |
1bb87f28 JW |
1353 | |
1354 | /* Update the data in CUM to advance over an argument | |
1355 | of mode MODE and data type TYPE. | |
1356 | (TYPE is null for libcalls where that information may not be available.) */ | |
1357 | ||
7a6cf439 DE |
1358 | #ifdef SPARCV9 |
1359 | #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ | |
1360 | do { \ | |
1361 | (CUM).arg_count[(int) GET_SPARC_ARG_CLASS (MODE)] = \ | |
1362 | ROUND_REG ((CUM), (MODE)) \ | |
1363 | + (GET_MODE_CLASS (MODE) == MODE_FLOAT \ | |
1364 | ? GET_MODE_SIZE (MODE) / 4 \ | |
1365 | : ROUND_ADVANCE ((MODE) == BLKmode \ | |
1366 | ? GET_MODE_SIZE (Pmode) \ | |
1367 | : GET_MODE_SIZE (MODE))); \ | |
1368 | sparc_arg_count++; \ | |
1369 | } while (0) | |
1370 | #else | |
1bb87f28 | 1371 | #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ |
95dea81f JW |
1372 | ((CUM) += ((MODE) != BLKmode \ |
1373 | ? ROUND_ADVANCE (GET_MODE_SIZE (MODE)) \ | |
1374 | : ROUND_ADVANCE (int_size_in_bytes (TYPE)))) | |
7a6cf439 DE |
1375 | #endif |
1376 | ||
1377 | /* Return boolean indicating arg of mode MODE will be passed in a reg. | |
1378 | This macro is only used in this file. */ | |
1379 | ||
1380 | #ifdef SPARCV9 | |
1381 | #define PASS_IN_REG_P(CUM, MODE, TYPE) \ | |
1382 | (ROUND_REG ((CUM), (MODE)) < NPARM_REGS (MODE) \ | |
1383 | && ((TYPE)==0 || ! TREE_ADDRESSABLE ((tree)(TYPE))) \ | |
1384 | && ((TYPE)==0 || (MODE) != BLKmode)) | |
1385 | #else | |
1386 | #define PASS_IN_REG_P(CUM, MODE, TYPE) \ | |
1387 | ((CUM) < NPARM_REGS (SImode) \ | |
1388 | && ((TYPE)==0 || ! TREE_ADDRESSABLE ((tree)(TYPE))) \ | |
1389 | && ((TYPE)==0 || (MODE) != BLKmode \ | |
1390 | || (TYPE_ALIGN (TYPE) % PARM_BOUNDARY == 0))) | |
1391 | #endif | |
1bb87f28 JW |
1392 | |
1393 | /* Determine where to put an argument to a function. | |
1394 | Value is zero to push the argument on the stack, | |
1395 | or a hard register in which to store the argument. | |
1396 | ||
1397 | MODE is the argument's machine mode. | |
1398 | TYPE is the data type of the argument (as a tree). | |
1399 | This is null for libcalls where that information may | |
1400 | not be available. | |
1401 | CUM is a variable of type CUMULATIVE_ARGS which gives info about | |
1402 | the preceding args and about the function being called. | |
1403 | NAMED is nonzero if this argument is a named parameter | |
1404 | (otherwise it is an extra parameter matching an ellipsis). */ | |
1405 | ||
1406 | /* On SPARC the first six args are normally in registers | |
1407 | and the rest are pushed. Any arg that starts within the first 6 words | |
7a6cf439 DE |
1408 | is at least partially passed in a register unless its data type forbids. |
1409 | For v9, the first 6 int args are passed in regs and the first N | |
1410 | float args are passed in regs (where N is such that %f0-15 are filled). | |
1411 | The rest are pushed. Any arg that starts within the first 6 words | |
1bb87f28 JW |
1412 | is at least partially passed in a register unless its data type forbids. */ |
1413 | ||
1414 | #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ | |
7a6cf439 DE |
1415 | (PASS_IN_REG_P ((CUM), (MODE), (TYPE)) \ |
1416 | ? gen_rtx (REG, (MODE), \ | |
1417 | (BASE_PASSING_ARG_REG (MODE) + ROUND_REG ((CUM), (MODE))))\ | |
1418 | : 0) | |
1bb87f28 JW |
1419 | |
1420 | /* Define where a function finds its arguments. | |
1421 | This is different from FUNCTION_ARG because of register windows. */ | |
1422 | ||
1423 | #define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED) \ | |
7a6cf439 DE |
1424 | (PASS_IN_REG_P ((CUM), (MODE), (TYPE)) \ |
1425 | ? gen_rtx (REG, (MODE), \ | |
1426 | (BASE_INCOMING_ARG_REG (MODE) + ROUND_REG ((CUM), (MODE))))\ | |
1427 | : 0) | |
1bb87f28 JW |
1428 | |
1429 | /* For an arg passed partly in registers and partly in memory, | |
1430 | this is the number of registers used. | |
1431 | For args passed entirely in registers or entirely in memory, zero. | |
1432 | Any arg that starts in the first 6 regs but won't entirely fit in them | |
7a6cf439 DE |
1433 | needs partial registers on the Sparc (!v9). On v9, there are no arguments |
1434 | that are passed partially in registers (??? complex values?). */ | |
1bb87f28 | 1435 | |
7a6cf439 | 1436 | #ifndef SPARCV9 |
1bb87f28 | 1437 | #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \ |
7a6cf439 DE |
1438 | (PASS_IN_REG_P ((CUM), (MODE), (TYPE)) \ |
1439 | && ((CUM) + ((MODE) == BLKmode \ | |
1440 | ? ROUND_ADVANCE (int_size_in_bytes (TYPE)) \ | |
1441 | : ROUND_ADVANCE (GET_MODE_SIZE (MODE))) - NPARM_REGS (SImode) > 0)\ | |
1442 | ? (NPARM_REGS (SImode) - (CUM)) \ | |
1bb87f28 | 1443 | : 0) |
7a6cf439 | 1444 | #endif |
1bb87f28 | 1445 | |
d9ca49d5 | 1446 | /* The SPARC ABI stipulates passing struct arguments (of any size) and |
7a6cf439 | 1447 | (!v9) quad-precision floats by invisible reference. |
87ac3809 | 1448 | For Pascal, also pass arrays by reference. */ |
1bb87f28 | 1449 | #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \ |
d9ca49d5 | 1450 | ((TYPE && (TREE_CODE (TYPE) == RECORD_TYPE \ |
87ac3809 JW |
1451 | || TREE_CODE (TYPE) == UNION_TYPE \ |
1452 | || TREE_CODE (TYPE) == ARRAY_TYPE)) \ | |
7a6cf439 DE |
1453 | || (!TARGET_V9 && MODE == TFmode)) |
1454 | ||
1455 | /* A C expression that indicates when it is the called function's | |
1456 | responsibility to make copies of arguments passed by reference. | |
1457 | If the callee can determine that the argument won't be modified, it can | |
1458 | avoid the copy. */ | |
1459 | /* ??? We'd love to be able to use NAMED here. Unfortunately, it doesn't | |
1460 | include the last named argument so we keep track of the args ourselves. */ | |
1461 | ||
1462 | #ifdef SPARCV9 | |
1463 | #define FUNCTION_ARG_CALLEE_COPIES(CUM, MODE, TYPE, NAMED) \ | |
1464 | (sparc_arg_count < sparc_n_named_args) | |
1465 | #endif | |
1466 | \f | |
1467 | /* Initialize data used by insn expanders. This is called from | |
1468 | init_emit, once for each function, before code is generated. | |
1469 | For v9, clear the temp slot used by float/int DImode conversions. | |
1470 | ??? There is the 16 bytes at [%fp-16], however we'd like to delete this | |
1471 | space at some point. | |
1472 | ??? Use assign_stack_temp? */ | |
1473 | ||
1474 | extern void sparc64_init_expanders (); | |
1475 | extern struct rtx_def *sparc64_fpconv_stack_temp (); | |
1476 | #ifdef SPARCV9 | |
1477 | #define INIT_EXPANDERS sparc64_init_expanders () | |
1478 | #endif | |
1bb87f28 JW |
1479 | |
1480 | /* Define the information needed to generate branch and scc insns. This is | |
1481 | stored from the compare operation. Note that we can't use "rtx" here | |
1482 | since it hasn't been defined! */ | |
1483 | ||
1484 | extern struct rtx_def *sparc_compare_op0, *sparc_compare_op1; | |
1485 | ||
1486 | /* Define the function that build the compare insn for scc and bcc. */ | |
1487 | ||
1488 | extern struct rtx_def *gen_compare_reg (); | |
7a6cf439 DE |
1489 | |
1490 | /* This function handles all v9 scc insns */ | |
1491 | ||
1492 | extern int gen_v9_scc (); | |
1bb87f28 | 1493 | \f |
4b69d2a3 RS |
1494 | /* Generate the special assembly code needed to tell the assembler whatever |
1495 | it might need to know about the return value of a function. | |
1496 | ||
1497 | For Sparc assemblers, we need to output a .proc pseudo-op which conveys | |
1498 | information to the assembler relating to peephole optimization (done in | |
1499 | the assembler). */ | |
1500 | ||
1501 | #define ASM_DECLARE_RESULT(FILE, RESULT) \ | |
1502 | fprintf ((FILE), "\t.proc\t0%o\n", sparc_type_code (TREE_TYPE (RESULT))) | |
1503 | ||
1bb87f28 JW |
1504 | /* Output the label for a function definition. */ |
1505 | ||
4b69d2a3 RS |
1506 | #define ASM_DECLARE_FUNCTION_NAME(FILE, NAME, DECL) \ |
1507 | do { \ | |
1508 | ASM_DECLARE_RESULT (FILE, DECL_RESULT (DECL)); \ | |
1509 | ASM_OUTPUT_LABEL (FILE, NAME); \ | |
1510 | } while (0) | |
1bb87f28 | 1511 | |
1bb87f28 JW |
1512 | /* This macro generates the assembly code for function entry. |
1513 | FILE is a stdio stream to output the code to. | |
1514 | SIZE is an int: how many units of temporary storage to allocate. | |
1515 | Refer to the array `regs_ever_live' to determine which registers | |
1516 | to save; `regs_ever_live[I]' is nonzero if register number I | |
1517 | is ever used in the function. This macro is responsible for | |
1518 | knowing which registers should not be saved even if used. */ | |
1519 | ||
1520 | /* On SPARC, move-double insns between fpu and cpu need an 8-byte block | |
1521 | of memory. If any fpu reg is used in the function, we allocate | |
1522 | such a block here, at the bottom of the frame, just in case it's needed. | |
1523 | ||
1524 | If this function is a leaf procedure, then we may choose not | |
1525 | to do a "save" insn. The decision about whether or not | |
1526 | to do this is made in regclass.c. */ | |
1527 | ||
a061b9fa | 1528 | extern int leaf_function; |
1bb87f28 | 1529 | #define FUNCTION_PROLOGUE(FILE, SIZE) \ |
5c56efde | 1530 | (TARGET_FRW ? sparc_flat_output_function_prologue (FILE, SIZE) \ |
5b485d2c | 1531 | : output_function_prologue (FILE, SIZE, leaf_function)) |
1bb87f28 JW |
1532 | |
1533 | /* Output assembler code to FILE to increment profiler label # LABELNO | |
1534 | for profiling a function entry. */ | |
1535 | ||
d2a8e680 RS |
1536 | #define FUNCTION_PROFILER(FILE, LABELNO) \ |
1537 | do { \ | |
1538 | fputs ("\tsethi %hi(", (FILE)); \ | |
1539 | ASM_OUTPUT_INTERNAL_LABELREF (FILE, "LP", LABELNO); \ | |
7a6cf439 DE |
1540 | fputs ("),%o0\n", (FILE)); \ |
1541 | if (TARGET_MEDANY) \ | |
1542 | fprintf (FILE, "\tadd %%o0,%s,%%o0\n", \ | |
1543 | MEDANY_BASE_REG); \ | |
1544 | fputs ("\tcall mcount\n\tadd %lo(", (FILE)); \ | |
d2a8e680 RS |
1545 | ASM_OUTPUT_INTERNAL_LABELREF (FILE, "LP", LABELNO); \ |
1546 | fputs ("),%o0,%o0\n", (FILE)); \ | |
1547 | } while (0) | |
1bb87f28 JW |
1548 | |
1549 | /* Output assembler code to FILE to initialize this source file's | |
1550 | basic block profiling info, if that has not already been done. */ | |
1551 | ||
1552 | #define FUNCTION_BLOCK_PROFILER(FILE, LABELNO) \ | |
7a6cf439 DE |
1553 | do { \ |
1554 | if (TARGET_MEDANY) \ | |
1555 | fprintf (FILE, "\tsethi %%hi(LPBX0),%%o0\n\tor %%0,%%lo(LPBX0),%%o0\n\tld [%s+%%o0],%%o1\n\ttst %%o1\n\tbne LPY%d\n\tadd %%o0,%s,%%o0\n\tcall ___bb_init_func\n\tnop\nLPY%d:\n", \ | |
1556 | MEDANY_BASE_REG, (LABELNO), MEDANY_BASE_REG, (LABELNO)); \ | |
1557 | else \ | |
1558 | fprintf (FILE, "\tsethi %%hi(LPBX0),%%o0\n\tld [%%lo(LPBX0)+%%o0],%%o1\n\ttst %%o1\n\tbne LPY%d\n\tadd %%o0,%%lo(LPBX0),%%o0\n\tcall ___bb_init_func\n\tnop\nLPY%d:\n", \ | |
1559 | (LABELNO), (LABELNO)); \ | |
1560 | } while (0) | |
1bb87f28 JW |
1561 | |
1562 | /* Output assembler code to FILE to increment the entry-count for | |
1563 | the BLOCKNO'th basic block in this source file. */ | |
1564 | ||
1565 | #define BLOCK_PROFILER(FILE, BLOCKNO) \ | |
7a6cf439 DE |
1566 | { \ |
1567 | int blockn = (BLOCKNO); \ | |
1568 | if (TARGET_MEDANY) \ | |
1569 | fprintf (FILE, "\tsethi %%hi(LPBX2+%d),%%g1\n\tor %%g1,%%lo(LPBX2+%d),%%g1\n\tld [%%g1+%s],%%g2\n\tadd %%g2,1,%%g2\n\tst %%g2,[%%g1+%s]\n", \ | |
1570 | 4 * blockn, 4 * blockn, MEDANY_BASE_REG, MEDANY_BASE_REG); \ | |
1571 | else \ | |
1572 | fprintf (FILE, "\tsethi %%hi(LPBX2+%d),%%g1\n\tld [%%lo(LPBX2+%d)+%%g1],%%g2\n\ | |
1573 | \tadd %%g2,1,%%g2\n\tst %%g2,[%%lo(LPBX2+%d)+%%g1]\n", \ | |
1574 | 4 * blockn, 4 * blockn, 4 * blockn); \ | |
1bb87f28 JW |
1575 | } |
1576 | ||
1bb87f28 JW |
1577 | /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, |
1578 | the stack pointer does not matter. The value is tested only in | |
1579 | functions that have frame pointers. | |
1580 | No definition is equivalent to always zero. */ | |
1581 | ||
1582 | extern int current_function_calls_alloca; | |
1583 | extern int current_function_outgoing_args_size; | |
1584 | ||
1585 | #define EXIT_IGNORE_STACK \ | |
1586 | (get_frame_size () != 0 \ | |
1587 | || current_function_calls_alloca || current_function_outgoing_args_size) | |
1588 | ||
1589 | /* This macro generates the assembly code for function exit, | |
1590 | on machines that need it. If FUNCTION_EPILOGUE is not defined | |
1591 | then individual return instructions are generated for each | |
1592 | return statement. Args are same as for FUNCTION_PROLOGUE. | |
1593 | ||
1594 | The function epilogue should not depend on the current stack pointer! | |
1595 | It should use the frame pointer only. This is mandatory because | |
1596 | of alloca; we also take advantage of it to omit stack adjustments | |
1597 | before returning. */ | |
1598 | ||
1599 | /* This declaration is needed due to traditional/ANSI | |
1600 | incompatibilities which cannot be #ifdefed away | |
1601 | because they occur inside of macros. Sigh. */ | |
1602 | extern union tree_node *current_function_decl; | |
1603 | ||
1604 | #define FUNCTION_EPILOGUE(FILE, SIZE) \ | |
5c56efde | 1605 | (TARGET_FRW ? sparc_flat_output_function_epilogue (FILE, SIZE) \ |
5b485d2c | 1606 | : output_function_epilogue (FILE, SIZE, leaf_function)) |
1bb87f28 | 1607 | |
5b485d2c | 1608 | #define DELAY_SLOTS_FOR_EPILOGUE \ |
5c56efde | 1609 | (TARGET_FRW ? sparc_flat_epilogue_delay_slots () : 1) |
1bb87f28 | 1610 | #define ELIGIBLE_FOR_EPILOGUE_DELAY(trial, slots_filled) \ |
5c56efde | 1611 | (TARGET_FRW ? sparc_flat_eligible_for_epilogue_delay (trial, slots_filled) \ |
5b485d2c | 1612 | : eligible_for_epilogue_delay (trial, slots_filled)) |
6a4bb1fa | 1613 | \f |
1bb87f28 JW |
1614 | /* Output assembler code for a block containing the constant parts |
1615 | of a trampoline, leaving space for the variable parts. */ | |
1616 | ||
1617 | /* On the sparc, the trampoline contains five instructions: | |
6098b63e RK |
1618 | sethi #TOP_OF_FUNCTION,%g1 |
1619 | or #BOTTOM_OF_FUNCTION,%g1,%g1 | |
1620 | sethi #TOP_OF_STATIC,%g2 | |
1621 | jmp g1 | |
1622 | or #BOTTOM_OF_STATIC,%g2,%g2 */ | |
1bb87f28 JW |
1623 | #define TRAMPOLINE_TEMPLATE(FILE) \ |
1624 | { \ | |
1625 | ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x00000000)); \ | |
1626 | ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x00000000)); \ | |
1627 | ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x00000000)); \ | |
6098b63e | 1628 | ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x81C04000)); \ |
1bb87f28 JW |
1629 | ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x00000000)); \ |
1630 | } | |
1631 | ||
1632 | /* Length in units of the trampoline for entering a nested function. */ | |
1633 | ||
1634 | #define TRAMPOLINE_SIZE 20 | |
1635 | ||
1636 | /* Emit RTL insns to initialize the variable parts of a trampoline. | |
1637 | FNADDR is an RTX for the address of the function's pure code. | |
7a6cf439 | 1638 | CXT is an RTX for the static chain value for the function. */ |
1bb87f28 | 1639 | |
7a6cf439 DE |
1640 | void sparc_initialize_trampoline (); |
1641 | void sparc64_initialize_trampoline (); | |
1642 | #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ | |
1643 | do { \ | |
1644 | if (TARGET_V9) \ | |
1645 | sparc64_initialize_trampoline (TRAMP, FNADDR, CXT); \ | |
1646 | else \ | |
1647 | sparc_initialize_trampoline (TRAMP, FNADDR, CXT); \ | |
1648 | } while (0) | |
6a4bb1fa | 1649 | \f |
9a1c7cd7 JW |
1650 | /* Generate necessary RTL for __builtin_saveregs(). |
1651 | ARGLIST is the argument list; see expr.c. */ | |
1652 | extern struct rtx_def *sparc_builtin_saveregs (); | |
1653 | #define EXPAND_BUILTIN_SAVEREGS(ARGLIST) sparc_builtin_saveregs (ARGLIST) | |
953fe179 JW |
1654 | |
1655 | /* Generate RTL to flush the register windows so as to make arbitrary frames | |
1656 | available. */ | |
1657 | #define SETUP_FRAME_ADDRESSES() \ | |
1658 | emit_insn (gen_flush_register_windows ()) | |
1659 | ||
1660 | /* Given an rtx for the address of a frame, | |
1661 | return an rtx for the address of the word in the frame | |
7a6cf439 DE |
1662 | that holds the dynamic chain--the previous frame's address. |
1663 | ??? -mflat support? */ | |
953fe179 | 1664 | #define DYNAMIC_CHAIN_ADDRESS(frame) \ |
7a6cf439 | 1665 | gen_rtx (PLUS, Pmode, frame, gen_rtx (CONST_INT, VOIDmode, 14 * UNITS_PER_WORD)) |
953fe179 JW |
1666 | |
1667 | /* The return address isn't on the stack, it is in a register, so we can't | |
1668 | access it from the current frame pointer. We can access it from the | |
1669 | previous frame pointer though by reading a value from the register window | |
1670 | save area. */ | |
1671 | #define RETURN_ADDR_IN_PREVIOUS_FRAME | |
1672 | ||
1673 | /* The current return address is in %i7. The return address of anything | |
1674 | farther back is in the register window save area at [%fp+60]. */ | |
1675 | /* ??? This ignores the fact that the actual return address is +8 for normal | |
1676 | returns, and +12 for structure returns. */ | |
1677 | #define RETURN_ADDR_RTX(count, frame) \ | |
1678 | ((count == -1) \ | |
1679 | ? gen_rtx (REG, Pmode, 31) \ | |
1680 | : copy_to_reg (gen_rtx (MEM, Pmode, \ | |
7a6cf439 | 1681 | memory_address (Pmode, plus_constant (frame, 15 * UNITS_PER_WORD))))) |
1bb87f28 JW |
1682 | \f |
1683 | /* Addressing modes, and classification of registers for them. */ | |
1684 | ||
1685 | /* #define HAVE_POST_INCREMENT */ | |
1686 | /* #define HAVE_POST_DECREMENT */ | |
1687 | ||
1688 | /* #define HAVE_PRE_DECREMENT */ | |
1689 | /* #define HAVE_PRE_INCREMENT */ | |
1690 | ||
1691 | /* Macros to check register numbers against specific register classes. */ | |
1692 | ||
1693 | /* These assume that REGNO is a hard or pseudo reg number. | |
1694 | They give nonzero only if REGNO is a hard reg of the suitable class | |
1695 | or a pseudo reg currently allocated to a suitable hard reg. | |
1696 | Since they use reg_renumber, they are safe only once reg_renumber | |
1697 | has been allocated, which happens in local-alloc.c. */ | |
1698 | ||
1699 | #define REGNO_OK_FOR_INDEX_P(REGNO) \ | |
1700 | (((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32) && (REGNO) != 0) | |
1701 | #define REGNO_OK_FOR_BASE_P(REGNO) \ | |
1702 | (((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32) && (REGNO) != 0) | |
1703 | #define REGNO_OK_FOR_FP_P(REGNO) \ | |
7a6cf439 DE |
1704 | (((unsigned) (REGNO) - 32 < (TARGET_V9 ? 64 : 32)) \ |
1705 | || ((unsigned) reg_renumber[REGNO] - 32 < (TARGET_V9 ? 64 : 32))) | |
1706 | #define REGNO_OK_FOR_CCFP_P(REGNO) \ | |
1707 | (TARGET_V9 \ | |
1708 | && ((unsigned) (REGNO) - 96 < 4) || ((unsigned) reg_renumber[REGNO] - 96 < 4)) | |
1bb87f28 JW |
1709 | |
1710 | /* Now macros that check whether X is a register and also, | |
1711 | strictly, whether it is in a specified class. | |
1712 | ||
1713 | These macros are specific to the SPARC, and may be used only | |
1714 | in code for printing assembler insns and in conditions for | |
1715 | define_optimization. */ | |
1716 | ||
1717 | /* 1 if X is an fp register. */ | |
1718 | ||
1719 | #define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X))) | |
1720 | \f | |
1721 | /* Maximum number of registers that can appear in a valid memory address. */ | |
1722 | ||
1723 | #define MAX_REGS_PER_ADDRESS 2 | |
1724 | ||
7aca9b9c JW |
1725 | /* Recognize any constant value that is a valid address. |
1726 | When PIC, we do not accept an address that would require a scratch reg | |
1727 | to load into a register. */ | |
1bb87f28 | 1728 | |
6eff269e BK |
1729 | #define CONSTANT_ADDRESS_P(X) \ |
1730 | (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \ | |
7aca9b9c JW |
1731 | || GET_CODE (X) == CONST_INT || GET_CODE (X) == HIGH \ |
1732 | || (GET_CODE (X) == CONST \ | |
1733 | && ! (flag_pic && pic_address_needs_scratch (X)))) | |
1734 | ||
1735 | /* Define this, so that when PIC, reload won't try to reload invalid | |
1736 | addresses which require two reload registers. */ | |
1737 | ||
1738 | #define LEGITIMATE_PIC_OPERAND_P(X) (! pic_address_needs_scratch (X)) | |
1bb87f28 JW |
1739 | |
1740 | /* Nonzero if the constant value X is a legitimate general operand. | |
1741 | Anything can be made to work except floating point constants. */ | |
1742 | ||
1743 | #define LEGITIMATE_CONSTANT_P(X) \ | |
1744 | (GET_CODE (X) != CONST_DOUBLE || GET_MODE (X) == VOIDmode) | |
1745 | ||
1746 | /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx | |
1747 | and check its validity for a certain class. | |
1748 | We have two alternate definitions for each of them. | |
1749 | The usual definition accepts all pseudo regs; the other rejects | |
1750 | them unless they have been allocated suitable hard regs. | |
1751 | The symbol REG_OK_STRICT causes the latter definition to be used. | |
1752 | ||
1753 | Most source files want to accept pseudo regs in the hope that | |
1754 | they will get allocated to the class that the insn wants them to be in. | |
1755 | Source files for reload pass need to be strict. | |
1756 | After reload, it makes no difference, since pseudo regs have | |
1757 | been eliminated by then. */ | |
1758 | ||
1759 | /* Optional extra constraints for this machine. Borrowed from romp.h. | |
1760 | ||
1761 | For the SPARC, `Q' means that this is a memory operand but not a | |
1762 | symbolic memory operand. Note that an unassigned pseudo register | |
1763 | is such a memory operand. Needed because reload will generate | |
1764 | these things in insns and then not re-recognize the insns, causing | |
1765 | constrain_operands to fail. | |
1766 | ||
7a6cf439 | 1767 | `S' handles constraints for calls. ??? So where is it? */ |
1bb87f28 JW |
1768 | |
1769 | #ifndef REG_OK_STRICT | |
1770 | ||
1771 | /* Nonzero if X is a hard reg that can be used as an index | |
1772 | or if it is a pseudo reg. */ | |
7a6cf439 DE |
1773 | #define REG_OK_FOR_INDEX_P(X) \ |
1774 | (((unsigned) REGNO (X)) - 32 >= (FIRST_PSEUDO_REGISTER - 32) && REGNO (X) != 0) | |
1bb87f28 JW |
1775 | /* Nonzero if X is a hard reg that can be used as a base reg |
1776 | or if it is a pseudo reg. */ | |
7a6cf439 DE |
1777 | #define REG_OK_FOR_BASE_P(X) \ |
1778 | (((unsigned) REGNO (X)) - 32 >= (FIRST_PSEUDO_REGISTER - 32) && REGNO (X) != 0) | |
1779 | ||
1780 | /* 'T', 'U' are for aligned memory loads which aren't needed for v9. */ | |
1bb87f28 JW |
1781 | |
1782 | #define EXTRA_CONSTRAINT(OP, C) \ | |
db5e449c RS |
1783 | ((C) == 'Q' \ |
1784 | ? ((GET_CODE (OP) == MEM \ | |
7a6cf439 | 1785 | && memory_address_p (GET_MODE (OP), XEXP (OP, 0)) \ |
db5e449c RS |
1786 | && ! symbolic_memory_operand (OP, VOIDmode)) \ |
1787 | || (reload_in_progress && GET_CODE (OP) == REG \ | |
1788 | && REGNO (OP) >= FIRST_PSEUDO_REGISTER)) \ | |
7a6cf439 | 1789 | : ! TARGET_V9 && (C) == 'T' \ |
19858600 | 1790 | ? (mem_aligned_8 (OP)) \ |
7a6cf439 | 1791 | : ! TARGET_V9 && (C) == 'U' \ |
19858600 | 1792 | ? (register_ok_for_ldd (OP)) \ |
db5e449c | 1793 | : 0) |
19858600 | 1794 | |
1bb87f28 JW |
1795 | #else |
1796 | ||
1797 | /* Nonzero if X is a hard reg that can be used as an index. */ | |
1798 | #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) | |
1799 | /* Nonzero if X is a hard reg that can be used as a base reg. */ | |
1800 | #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) | |
1801 | ||
1802 | #define EXTRA_CONSTRAINT(OP, C) \ | |
9ad2c692 JW |
1803 | ((C) == 'Q' \ |
1804 | ? (GET_CODE (OP) == REG \ | |
1805 | ? (REGNO (OP) >= FIRST_PSEUDO_REGISTER \ | |
1806 | && reg_renumber[REGNO (OP)] < 0) \ | |
1807 | : GET_CODE (OP) == MEM) \ | |
7a6cf439 | 1808 | : ! TARGET_V9 && (C) == 'T' \ |
b165d471 | 1809 | ? mem_aligned_8 (OP) && strict_memory_address_p (Pmode, XEXP (OP, 0)) \ |
7a6cf439 | 1810 | : ! TARGET_V9 && (C) == 'U' \ |
b165d471 JW |
1811 | ? (GET_CODE (OP) == REG \ |
1812 | && (REGNO (OP) < FIRST_PSEUDO_REGISTER \ | |
1813 | || reg_renumber[REGNO (OP)] > 0) \ | |
1814 | && register_ok_for_ldd (OP)) : 0) | |
1bb87f28 JW |
1815 | #endif |
1816 | \f | |
1817 | /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression | |
1818 | that is a valid memory address for an instruction. | |
1819 | The MODE argument is the machine mode for the MEM expression | |
1820 | that wants to use this address. | |
1821 | ||
1822 | On SPARC, the actual legitimate addresses must be REG+REG or REG+SMALLINT | |
1823 | ordinarily. This changes a bit when generating PIC. | |
1824 | ||
1825 | If you change this, execute "rm explow.o recog.o reload.o". */ | |
1826 | ||
bec2e359 JW |
1827 | #define RTX_OK_FOR_BASE_P(X) \ |
1828 | ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \ | |
1829 | || (GET_CODE (X) == SUBREG \ | |
1830 | && GET_CODE (SUBREG_REG (X)) == REG \ | |
1831 | && REG_OK_FOR_BASE_P (SUBREG_REG (X)))) | |
1832 | ||
1833 | #define RTX_OK_FOR_INDEX_P(X) \ | |
1834 | ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \ | |
1835 | || (GET_CODE (X) == SUBREG \ | |
1836 | && GET_CODE (SUBREG_REG (X)) == REG \ | |
1837 | && REG_OK_FOR_INDEX_P (SUBREG_REG (X)))) | |
1838 | ||
1839 | #define RTX_OK_FOR_OFFSET_P(X) \ | |
1840 | (GET_CODE (X) == CONST_INT && INTVAL (X) >= -0x1000 && INTVAL (X) < 0x1000) | |
1841 | ||
1bb87f28 | 1842 | #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ |
bec2e359 JW |
1843 | { if (RTX_OK_FOR_BASE_P (X)) \ |
1844 | goto ADDR; \ | |
1bb87f28 JW |
1845 | else if (GET_CODE (X) == PLUS) \ |
1846 | { \ | |
bec2e359 JW |
1847 | register rtx op0 = XEXP (X, 0); \ |
1848 | register rtx op1 = XEXP (X, 1); \ | |
1849 | if (flag_pic && op0 == pic_offset_table_rtx) \ | |
1bb87f28 | 1850 | { \ |
bec2e359 | 1851 | if (RTX_OK_FOR_BASE_P (op1)) \ |
1bb87f28 JW |
1852 | goto ADDR; \ |
1853 | else if (flag_pic == 1 \ | |
bec2e359 JW |
1854 | && GET_CODE (op1) != REG \ |
1855 | && GET_CODE (op1) != LO_SUM \ | |
7aca9b9c JW |
1856 | && GET_CODE (op1) != MEM \ |
1857 | && (GET_CODE (op1) != CONST_INT \ | |
1858 | || SMALL_INT (op1))) \ | |
1bb87f28 JW |
1859 | goto ADDR; \ |
1860 | } \ | |
bec2e359 | 1861 | else if (RTX_OK_FOR_BASE_P (op0)) \ |
1bb87f28 | 1862 | { \ |
bec2e359 JW |
1863 | if (RTX_OK_FOR_INDEX_P (op1) \ |
1864 | || RTX_OK_FOR_OFFSET_P (op1)) \ | |
1bb87f28 JW |
1865 | goto ADDR; \ |
1866 | } \ | |
bec2e359 | 1867 | else if (RTX_OK_FOR_BASE_P (op1)) \ |
1bb87f28 | 1868 | { \ |
bec2e359 JW |
1869 | if (RTX_OK_FOR_INDEX_P (op0) \ |
1870 | || RTX_OK_FOR_OFFSET_P (op0)) \ | |
1bb87f28 JW |
1871 | goto ADDR; \ |
1872 | } \ | |
1873 | } \ | |
bec2e359 JW |
1874 | else if (GET_CODE (X) == LO_SUM) \ |
1875 | { \ | |
1876 | register rtx op0 = XEXP (X, 0); \ | |
1877 | register rtx op1 = XEXP (X, 1); \ | |
1878 | if (RTX_OK_FOR_BASE_P (op0) \ | |
2f0da906 JW |
1879 | && CONSTANT_P (op1) \ |
1880 | /* We can't allow TFmode, because an offset \ | |
1881 | greater than or equal to the alignment (8) \ | |
1882 | may cause the LO_SUM to overflow. */ \ | |
1883 | && MODE != TFmode) \ | |
bec2e359 JW |
1884 | goto ADDR; \ |
1885 | } \ | |
1bb87f28 JW |
1886 | else if (GET_CODE (X) == CONST_INT && SMALL_INT (X)) \ |
1887 | goto ADDR; \ | |
1888 | } | |
1889 | \f | |
1890 | /* Try machine-dependent ways of modifying an illegitimate address | |
1891 | to be legitimate. If we find one, return the new, valid address. | |
1892 | This macro is used in only one place: `memory_address' in explow.c. | |
1893 | ||
1894 | OLDX is the address as it was before break_out_memory_refs was called. | |
1895 | In some cases it is useful to look at this to decide what needs to be done. | |
1896 | ||
1897 | MODE and WIN are passed so that this macro can use | |
1898 | GO_IF_LEGITIMATE_ADDRESS. | |
1899 | ||
1900 | It is always safe for this macro to do nothing. It exists to recognize | |
1901 | opportunities to optimize the output. */ | |
1902 | ||
1903 | /* On SPARC, change REG+N into REG+REG, and REG+(X*Y) into REG+REG. */ | |
1904 | extern struct rtx_def *legitimize_pic_address (); | |
1905 | #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \ | |
1906 | { rtx sparc_x = (X); \ | |
1907 | if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == MULT) \ | |
1908 | (X) = gen_rtx (PLUS, Pmode, XEXP (X, 1), \ | |
a015279e | 1909 | force_operand (XEXP (X, 0), NULL_RTX)); \ |
1bb87f28 JW |
1910 | if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 1)) == MULT) \ |
1911 | (X) = gen_rtx (PLUS, Pmode, XEXP (X, 0), \ | |
a015279e | 1912 | force_operand (XEXP (X, 1), NULL_RTX)); \ |
1bb87f28 | 1913 | if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == PLUS) \ |
a015279e | 1914 | (X) = gen_rtx (PLUS, Pmode, force_operand (XEXP (X, 0), NULL_RTX),\ |
1bb87f28 JW |
1915 | XEXP (X, 1)); \ |
1916 | if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 1)) == PLUS) \ | |
1917 | (X) = gen_rtx (PLUS, Pmode, XEXP (X, 0), \ | |
a015279e | 1918 | force_operand (XEXP (X, 1), NULL_RTX)); \ |
1bb87f28 JW |
1919 | if (sparc_x != (X) && memory_address_p (MODE, X)) \ |
1920 | goto WIN; \ | |
7aca9b9c | 1921 | if (flag_pic) (X) = legitimize_pic_address (X, MODE, 0); \ |
1bb87f28 JW |
1922 | else if (GET_CODE (X) == PLUS && CONSTANT_ADDRESS_P (XEXP (X, 1))) \ |
1923 | (X) = gen_rtx (PLUS, Pmode, XEXP (X, 0), \ | |
1924 | copy_to_mode_reg (Pmode, XEXP (X, 1))); \ | |
1925 | else if (GET_CODE (X) == PLUS && CONSTANT_ADDRESS_P (XEXP (X, 0))) \ | |
1926 | (X) = gen_rtx (PLUS, Pmode, XEXP (X, 1), \ | |
1927 | copy_to_mode_reg (Pmode, XEXP (X, 0))); \ | |
1928 | else if (GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == CONST \ | |
1929 | || GET_CODE (X) == LABEL_REF) \ | |
1930 | (X) = gen_rtx (LO_SUM, Pmode, \ | |
1931 | copy_to_mode_reg (Pmode, gen_rtx (HIGH, Pmode, X)), X); \ | |
1932 | if (memory_address_p (MODE, X)) \ | |
1933 | goto WIN; } | |
1934 | ||
1935 | /* Go to LABEL if ADDR (a legitimate address expression) | |
1936 | has an effect that depends on the machine mode it is used for. | |
1937 | On the SPARC this is never true. */ | |
1938 | ||
1939 | #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) | |
7a6cf439 DE |
1940 | |
1941 | /* If we are referencing a function make the SYMBOL_REF special. | |
1942 | In the Medium/Anywhere code model, %g4 points to the data segment so we | |
1943 | must not add it to function addresses. */ | |
1944 | ||
1945 | #define ENCODE_SECTION_INFO(DECL) \ | |
1946 | do { \ | |
1947 | if (TARGET_MEDANY && TREE_CODE (DECL) == FUNCTION_DECL) \ | |
1948 | SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1; \ | |
1949 | } while (0) | |
1bb87f28 JW |
1950 | \f |
1951 | /* Specify the machine mode that this machine uses | |
1952 | for the index in the tablejump instruction. */ | |
7a6cf439 | 1953 | #define CASE_VECTOR_MODE Pmode |
1bb87f28 JW |
1954 | |
1955 | /* Define this if the tablejump instruction expects the table | |
1956 | to contain offsets from the address of the table. | |
1957 | Do not define this if the table should contain absolute addresses. */ | |
1958 | /* #define CASE_VECTOR_PC_RELATIVE */ | |
1959 | ||
1960 | /* Specify the tree operation to be used to convert reals to integers. */ | |
1961 | #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR | |
1962 | ||
1963 | /* This is the kind of divide that is easiest to do in the general case. */ | |
1964 | #define EASY_DIV_EXPR TRUNC_DIV_EXPR | |
1965 | ||
1966 | /* Define this as 1 if `char' should by default be signed; else as 0. */ | |
1967 | #define DEFAULT_SIGNED_CHAR 1 | |
1968 | ||
1969 | /* Max number of bytes we can move from memory to memory | |
1970 | in one reasonably fast instruction. */ | |
2eef2ef1 | 1971 | #define MOVE_MAX 8 |
1bb87f28 | 1972 | |
0fb5a69e | 1973 | #if 0 /* Sun 4 has matherr, so this is no good. */ |
24e2a2bf RS |
1974 | /* This is the value of the error code EDOM for this machine, |
1975 | used by the sqrt instruction. */ | |
1976 | #define TARGET_EDOM 33 | |
1977 | ||
1978 | /* This is how to refer to the variable errno. */ | |
1979 | #define GEN_ERRNO_RTX \ | |
1980 | gen_rtx (MEM, SImode, gen_rtx (SYMBOL_REF, Pmode, "errno")) | |
0fb5a69e | 1981 | #endif /* 0 */ |
24e2a2bf | 1982 | |
9a63901f RK |
1983 | /* Define if operations between registers always perform the operation |
1984 | on the full register even if a narrower mode is specified. */ | |
1985 | #define WORD_REGISTER_OPERATIONS | |
1986 | ||
1987 | /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD | |
1988 | will either zero-extend or sign-extend. The value of this macro should | |
1989 | be the code that says which one of the two operations is implicitly | |
1990 | done, NIL if none. */ | |
1991 | #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND | |
1bb87f28 JW |
1992 | |
1993 | /* Nonzero if access to memory by bytes is slow and undesirable. | |
1994 | For RISC chips, it means that access to memory by bytes is no | |
1995 | better than access by words when possible, so grab a whole word | |
1996 | and maybe make use of that. */ | |
1997 | #define SLOW_BYTE_ACCESS 1 | |
1998 | ||
1999 | /* We assume that the store-condition-codes instructions store 0 for false | |
2000 | and some other value for true. This is the value stored for true. */ | |
2001 | ||
2002 | #define STORE_FLAG_VALUE 1 | |
2003 | ||
2004 | /* When a prototype says `char' or `short', really pass an `int'. */ | |
2005 | #define PROMOTE_PROTOTYPES | |
2006 | ||
d969caf8 RK |
2007 | /* Define this to be nonzero if shift instructions ignore all but the low-order |
2008 | few bits. */ | |
2009 | #define SHIFT_COUNT_TRUNCATED 1 | |
1bb87f28 JW |
2010 | |
2011 | /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits | |
2012 | is done just by pretending it is already truncated. */ | |
2013 | #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 | |
2014 | ||
2015 | /* Specify the machine mode that pointers have. | |
2016 | After generation of rtl, the compiler makes no further distinction | |
2017 | between pointers and any other objects of this machine mode. */ | |
7a6cf439 | 2018 | #define Pmode (TARGET_PTR64 ? DImode : SImode) |
1bb87f28 | 2019 | |
b4ac57ab RS |
2020 | /* Generate calls to memcpy, memcmp and memset. */ |
2021 | #define TARGET_MEM_FUNCTIONS | |
2022 | ||
1bb87f28 JW |
2023 | /* Add any extra modes needed to represent the condition code. |
2024 | ||
2025 | On the Sparc, we have a "no-overflow" mode which is used when an add or | |
2026 | subtract insn is used to set the condition code. Different branches are | |
2027 | used in this case for some operations. | |
2028 | ||
4d449554 JW |
2029 | We also have two modes to indicate that the relevant condition code is |
2030 | in the floating-point condition code register. One for comparisons which | |
2031 | will generate an exception if the result is unordered (CCFPEmode) and | |
2032 | one for comparisons which will never trap (CCFPmode). This really should | |
7a6cf439 DE |
2033 | be a separate register, but we don't want to go to 65 registers. |
2034 | ||
2035 | CCXmode and CCX_NOOVmode are only used by v9. */ | |
2036 | ||
2037 | #define EXTRA_CC_MODES CCXmode, CC_NOOVmode, CCX_NOOVmode, CCFPmode, CCFPEmode | |
1bb87f28 JW |
2038 | |
2039 | /* Define the names for the modes specified above. */ | |
7a6cf439 DE |
2040 | |
2041 | #define EXTRA_CC_NAMES "CCX", "CC_NOOV", "CCX_NOOV", "CCFP", "CCFPE" | |
1bb87f28 JW |
2042 | |
2043 | /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, | |
4d449554 JW |
2044 | return the mode to be used for the comparison. For floating-point, |
2045 | CCFP[E]mode is used. CC_NOOVmode should be used when the first operand is a | |
922bd191 JW |
2046 | PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special |
2047 | processing is needed. */ | |
679655e6 | 2048 | #define SELECT_CC_MODE(OP,X,Y) \ |
4d449554 | 2049 | (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \ |
922bd191 JW |
2050 | ? ((OP == EQ || OP == NE) ? CCFPmode : CCFPEmode) \ |
2051 | : ((GET_CODE (X) == PLUS || GET_CODE (X) == MINUS \ | |
2052 | || GET_CODE (X) == NEG || GET_CODE (X) == ASHIFT) \ | |
7a6cf439 DE |
2053 | ? (TARGET_V9 && GET_MODE (X) == DImode ? CCX_NOOVmode : CC_NOOVmode) \ |
2054 | : (TARGET_V9 && GET_MODE (X) == DImode ? CCXmode : CCmode))) | |
1bb87f28 | 2055 | |
b331b745 RK |
2056 | /* Return non-zero if SELECT_CC_MODE will never return MODE for a |
2057 | floating point inequality comparison. */ | |
2058 | ||
2059 | #define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode) | |
2060 | ||
1bb87f28 JW |
2061 | /* A function address in a call instruction |
2062 | is a byte address (for indexing purposes) | |
2063 | so give the MEM rtx a byte's mode. */ | |
2064 | #define FUNCTION_MODE SImode | |
2065 | ||
2066 | /* Define this if addresses of constant functions | |
2067 | shouldn't be put through pseudo regs where they can be cse'd. | |
2068 | Desirable on machines where ordinary constants are expensive | |
2069 | but a CALL with constant address is cheap. */ | |
2070 | #define NO_FUNCTION_CSE | |
2071 | ||
2072 | /* alloca should avoid clobbering the old register save area. */ | |
2073 | #define SETJMP_VIA_SAVE_AREA | |
2074 | ||
2075 | /* Define subroutines to call to handle multiply and divide. | |
2076 | Use the subroutines that Sun's library provides. | |
2077 | The `*' prevents an underscore from being prepended by the compiler. */ | |
2078 | ||
2079 | #define DIVSI3_LIBCALL "*.div" | |
2080 | #define UDIVSI3_LIBCALL "*.udiv" | |
2081 | #define MODSI3_LIBCALL "*.rem" | |
2082 | #define UMODSI3_LIBCALL "*.urem" | |
2083 | /* .umul is a little faster than .mul. */ | |
2084 | #define MULSI3_LIBCALL "*.umul" | |
2085 | ||
8248e2bc JW |
2086 | /* Define library calls for quad FP operations. These are all part of the |
2087 | SPARC ABI. */ | |
b3f741ed JW |
2088 | #define ADDTF3_LIBCALL "_Q_add" |
2089 | #define SUBTF3_LIBCALL "_Q_sub" | |
2090 | #define MULTF3_LIBCALL "_Q_mul" | |
2091 | #define DIVTF3_LIBCALL "_Q_div" | |
b3f741ed JW |
2092 | #define FLOATSITF2_LIBCALL "_Q_itoq" |
2093 | #define FIX_TRUNCTFSI2_LIBCALL "_Q_qtoi" | |
2094 | #define FIXUNS_TRUNCTFSI2_LIBCALL "_Q_qtou" | |
2095 | #define EXTENDSFTF2_LIBCALL "_Q_stoq" | |
2096 | #define TRUNCTFSF2_LIBCALL "_Q_qtos" | |
2097 | #define EXTENDDFTF2_LIBCALL "_Q_dtoq" | |
2098 | #define TRUNCTFDF2_LIBCALL "_Q_qtod" | |
2099 | #define EQTF2_LIBCALL "_Q_feq" | |
2100 | #define NETF2_LIBCALL "_Q_fne" | |
2101 | #define GTTF2_LIBCALL "_Q_fgt" | |
2102 | #define GETF2_LIBCALL "_Q_fge" | |
2103 | #define LTTF2_LIBCALL "_Q_flt" | |
2104 | #define LETF2_LIBCALL "_Q_fle" | |
8248e2bc | 2105 | |
78e9b5df JW |
2106 | /* We can define the TFmode sqrt optab only if TARGET_FPU. This is because |
2107 | with soft-float, the SFmode and DFmode sqrt instructions will be absent, | |
2108 | and the compiler will notice and try to use the TFmode sqrt instruction | |
2109 | for calls to the builtin function sqrt, but this fails. */ | |
2110 | #define INIT_TARGET_OPTABS \ | |
2111 | do { \ | |
2112 | INIT_SUBTARGET_OPTABS; \ | |
2113 | if (TARGET_FPU) \ | |
2114 | sqrt_optab->handlers[(int) TFmode].libfunc = gen_rtx (SYMBOL_REF, Pmode, "_Q_sqrt"); \ | |
2115 | } while (0) | |
2116 | ||
2117 | /* This is meant to be redefined in the host dependent files */ | |
2118 | #define INIT_SUBTARGET_OPTABS | |
2119 | ||
1bb87f28 JW |
2120 | /* Compute the cost of computing a constant rtl expression RTX |
2121 | whose rtx-code is CODE. The body of this macro is a portion | |
2122 | of a switch statement. If the code is computed here, | |
2123 | return it with a return statement. Otherwise, break from the switch. */ | |
2124 | ||
3bb22aee | 2125 | #define CONST_COSTS(RTX,CODE,OUTER_CODE) \ |
1bb87f28 | 2126 | case CONST_INT: \ |
1bb87f28 | 2127 | if (INTVAL (RTX) < 0x1000 && INTVAL (RTX) >= -0x1000) \ |
5b485d2c | 2128 | return 0; \ |
1bb87f28 JW |
2129 | case HIGH: \ |
2130 | return 2; \ | |
2131 | case CONST: \ | |
2132 | case LABEL_REF: \ | |
2133 | case SYMBOL_REF: \ | |
2134 | return 4; \ | |
2135 | case CONST_DOUBLE: \ | |
2136 | if (GET_MODE (RTX) == DImode) \ | |
2137 | if ((XINT (RTX, 3) == 0 \ | |
2138 | && (unsigned) XINT (RTX, 2) < 0x1000) \ | |
2139 | || (XINT (RTX, 3) == -1 \ | |
2140 | && XINT (RTX, 2) < 0 \ | |
2141 | && XINT (RTX, 2) >= -0x1000)) \ | |
5b485d2c | 2142 | return 0; \ |
1bb87f28 JW |
2143 | return 8; |
2144 | ||
a0a74fda | 2145 | /* Compute the cost of an address. For the sparc, all valid addresses are |
7a6cf439 DE |
2146 | the same cost. |
2147 | ??? Is this true for v9? */ | |
1bb87f28 | 2148 | |
a0a74fda | 2149 | #define ADDRESS_COST(RTX) 1 |
1bb87f28 JW |
2150 | |
2151 | /* Compute extra cost of moving data between one register class | |
7a6cf439 DE |
2152 | and another. |
2153 | ??? v9: We ignore FPCC_REGS on the assumption they'll never be seen. */ | |
1bb87f28 | 2154 | #define REGISTER_MOVE_COST(CLASS1, CLASS2) \ |
24b63396 JW |
2155 | (((FP_REG_CLASS_P (CLASS1) && (CLASS2) == GENERAL_REGS) \ |
2156 | || ((CLASS1) == GENERAL_REGS && FP_REG_CLASS_P (CLASS2))) ? 6 : 2) | |
1bb87f28 JW |
2157 | |
2158 | /* Provide the costs of a rtl expression. This is in the body of a | |
2159 | switch on CODE. The purpose for the cost of MULT is to encourage | |
2160 | `synth_mult' to find a synthetic multiply when reasonable. | |
2161 | ||
2162 | If we need more than 12 insns to do a multiply, then go out-of-line, | |
2163 | since the call overhead will be < 10% of the cost of the multiply. */ | |
2164 | ||
3bb22aee | 2165 | #define RTX_COSTS(X,CODE,OUTER_CODE) \ |
1bb87f28 | 2166 | case MULT: \ |
7a6cf439 | 2167 | return (TARGET_V8 || TARGET_V9) ? COSTS_N_INSNS (5) : COSTS_N_INSNS (25); \ |
1bb87f28 JW |
2168 | case DIV: \ |
2169 | case UDIV: \ | |
2170 | case MOD: \ | |
2171 | case UMOD: \ | |
5b485d2c JW |
2172 | return COSTS_N_INSNS (25); \ |
2173 | /* Make FLOAT and FIX more expensive than CONST_DOUBLE,\ | |
1bb87f28 JW |
2174 | so that cse will favor the latter. */ \ |
2175 | case FLOAT: \ | |
5b485d2c | 2176 | case FIX: \ |
1bb87f28 JW |
2177 | return 19; |
2178 | ||
bef8d8c7 JW |
2179 | /* Adjust the cost of dependencies. */ |
2180 | #define ADJUST_COST(INSN,LINK,DEP,COST) \ | |
2181 | if (TARGET_SUPERSPARC) \ | |
2182 | (COST) = supersparc_adjust_cost (INSN, LINK, DEP, COST) | |
2183 | ||
1bb87f28 JW |
2184 | /* Conditional branches with empty delay slots have a length of two. */ |
2185 | #define ADJUST_INSN_LENGTH(INSN, LENGTH) \ | |
2186 | if (GET_CODE (INSN) == CALL_INSN \ | |
2187 | || (GET_CODE (INSN) == JUMP_INSN && ! simplejump_p (insn))) \ | |
2188 | LENGTH += 1; | |
2189 | \f | |
2190 | /* Control the assembler format that we output. */ | |
2191 | ||
2192 | /* Output at beginning of assembler file. */ | |
2193 | ||
2194 | #define ASM_FILE_START(file) | |
2195 | ||
2196 | /* Output to assembler file text saying following lines | |
2197 | may contain character constants, extra white space, comments, etc. */ | |
2198 | ||
2199 | #define ASM_APP_ON "" | |
2200 | ||
2201 | /* Output to assembler file text saying following lines | |
2202 | no longer contain unusual constructs. */ | |
2203 | ||
2204 | #define ASM_APP_OFF "" | |
2205 | ||
7a6cf439 DE |
2206 | /* ??? Try to make the style consistent here (_OP?). */ |
2207 | ||
2208 | #define ASM_LONGLONG ".xword" | |
303d524a JW |
2209 | #define ASM_LONG ".word" |
2210 | #define ASM_SHORT ".half" | |
2211 | #define ASM_BYTE_OP ".byte" | |
7a6cf439 DE |
2212 | #define ASM_FLOAT ".single" |
2213 | #define ASM_DOUBLE ".double" | |
2214 | #define ASM_LONGDOUBLE ".xxx" /* ??? Not known (or used yet). */ | |
303d524a | 2215 | |
1bb87f28 JW |
2216 | /* Output before read-only data. */ |
2217 | ||
2218 | #define TEXT_SECTION_ASM_OP ".text" | |
2219 | ||
2220 | /* Output before writable data. */ | |
2221 | ||
2222 | #define DATA_SECTION_ASM_OP ".data" | |
2223 | ||
2224 | /* How to refer to registers in assembler output. | |
2225 | This sequence is indexed by compiler's hard-register-number (see above). */ | |
2226 | ||
7a6cf439 DE |
2227 | #ifdef SPARCV9 |
2228 | #define REGISTER_NAMES \ | |
2229 | {"%g0", "%g1", "%g2", "%g3", "%g4", "%g5", "%g6", "%g7", \ | |
2230 | "%o0", "%o1", "%o2", "%o3", "%o4", "%o5", "%sp", "%o7", \ | |
2231 | "%l0", "%l1", "%l2", "%l3", "%l4", "%l5", "%l6", "%l7", \ | |
2232 | "%i0", "%i1", "%i2", "%i3", "%i4", "%i5", "%fp", "%i7", \ | |
2233 | "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7", \ | |
2234 | "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15", \ | |
2235 | "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23", \ | |
2236 | "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31", \ | |
2237 | "%f32", "%f33", "%f34", "%f35", "%f36", "%f37", "%f38", "%f39", \ | |
2238 | "%f40", "%f41", "%f42", "%f43", "%f44", "%f45", "%f46", "%f47", \ | |
2239 | "%f48", "%f49", "%f50", "%f51", "%f52", "%f53", "%f54", "%f55", \ | |
2240 | "%f56", "%f57", "%f58", "%f59", "%f60", "%f61", "%f62", "%f63", \ | |
2241 | "%fcc0", "%fcc1", "%fcc2", "%fcc3"} | |
2242 | #else | |
1bb87f28 JW |
2243 | #define REGISTER_NAMES \ |
2244 | {"%g0", "%g1", "%g2", "%g3", "%g4", "%g5", "%g6", "%g7", \ | |
2245 | "%o0", "%o1", "%o2", "%o3", "%o4", "%o5", "%sp", "%o7", \ | |
2246 | "%l0", "%l1", "%l2", "%l3", "%l4", "%l5", "%l6", "%l7", \ | |
2247 | "%i0", "%i1", "%i2", "%i3", "%i4", "%i5", "%fp", "%i7", \ | |
2248 | "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7", \ | |
2249 | "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15", \ | |
2250 | "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23", \ | |
2251 | "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31"} | |
7a6cf439 | 2252 | #endif |
1bb87f28 | 2253 | |
ea3fa5f7 JW |
2254 | /* Define additional names for use in asm clobbers and asm declarations. |
2255 | ||
2256 | We define the fake Condition Code register as an alias for reg 0 (which | |
2257 | is our `condition code' register), so that condition codes can easily | |
2258 | be clobbered by an asm. No such register actually exists. Condition | |
2259 | codes are partly stored in the PSR and partly in the FSR. */ | |
2260 | ||
0eb9f40e | 2261 | #define ADDITIONAL_REGISTER_NAMES {"ccr", 0, "cc", 0} |
ea3fa5f7 | 2262 | |
1bb87f28 JW |
2263 | /* How to renumber registers for dbx and gdb. */ |
2264 | ||
2265 | #define DBX_REGISTER_NUMBER(REGNO) (REGNO) | |
2266 | ||
2267 | /* On Sun 4, this limit is 2048. We use 1500 to be safe, | |
2268 | since the length can run past this up to a continuation point. */ | |
2269 | #define DBX_CONTIN_LENGTH 1500 | |
2270 | ||
2271 | /* This is how to output a note to DBX telling it the line number | |
2272 | to which the following sequence of instructions corresponds. | |
2273 | ||
2274 | This is needed for SunOS 4.0, and should not hurt for 3.2 | |
2275 | versions either. */ | |
2276 | #define ASM_OUTPUT_SOURCE_LINE(file, line) \ | |
2277 | { static int sym_lineno = 1; \ | |
2278 | fprintf (file, ".stabn 68,0,%d,LM%d\nLM%d:\n", \ | |
2279 | line, sym_lineno, sym_lineno); \ | |
2280 | sym_lineno += 1; } | |
2281 | ||
2282 | /* This is how to output the definition of a user-level label named NAME, | |
2283 | such as the label on a static function or variable NAME. */ | |
2284 | ||
2285 | #define ASM_OUTPUT_LABEL(FILE,NAME) \ | |
2286 | do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0) | |
2287 | ||
2288 | /* This is how to output a command to make the user-level label named NAME | |
2289 | defined for reference from other files. */ | |
2290 | ||
2291 | #define ASM_GLOBALIZE_LABEL(FILE,NAME) \ | |
2292 | do { fputs ("\t.global ", FILE); assemble_name (FILE, NAME); fputs ("\n", FILE);} while (0) | |
2293 | ||
2294 | /* This is how to output a reference to a user-level label named NAME. | |
2295 | `assemble_name' uses this. */ | |
2296 | ||
2297 | #define ASM_OUTPUT_LABELREF(FILE,NAME) \ | |
2298 | fprintf (FILE, "_%s", NAME) | |
2299 | ||
d2a8e680 | 2300 | /* This is how to output a definition of an internal numbered label where |
1bb87f28 JW |
2301 | PREFIX is the class of label and NUM is the number within the class. */ |
2302 | ||
2303 | #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \ | |
2304 | fprintf (FILE, "%s%d:\n", PREFIX, NUM) | |
2305 | ||
d2a8e680 RS |
2306 | /* This is how to output a reference to an internal numbered label where |
2307 | PREFIX is the class of label and NUM is the number within the class. */ | |
2308 | /* FIXME: This should be used throughout gcc, and documented in the texinfo | |
2309 | files. There is no reason you should have to allocate a buffer and | |
2310 | `sprintf' to reference an internal label (as opposed to defining it). */ | |
2311 | ||
2312 | #define ASM_OUTPUT_INTERNAL_LABELREF(FILE,PREFIX,NUM) \ | |
2313 | fprintf (FILE, "%s%d", PREFIX, NUM) | |
2314 | ||
1bb87f28 JW |
2315 | /* This is how to store into the string LABEL |
2316 | the symbol_ref name of an internal numbered label where | |
2317 | PREFIX is the class of label and NUM is the number within the class. | |
2318 | This is suitable for output with `assemble_name'. */ | |
2319 | ||
2320 | #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \ | |
2321 | sprintf (LABEL, "*%s%d", PREFIX, NUM) | |
2322 | ||
2323 | /* This is how to output an assembler line defining a `double' constant. */ | |
2324 | ||
2325 | #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \ | |
2326 | { \ | |
2e7ac77c JW |
2327 | long t[2]; \ |
2328 | REAL_VALUE_TO_TARGET_DOUBLE ((VALUE), t); \ | |
2329 | fprintf (FILE, "\t%s\t0x%lx\n\t%s\t0x%lx\n", \ | |
2330 | ASM_LONG, t[0], ASM_LONG, t[1]); \ | |
1bb87f28 JW |
2331 | } |
2332 | ||
2333 | /* This is how to output an assembler line defining a `float' constant. */ | |
2334 | ||
2335 | #define ASM_OUTPUT_FLOAT(FILE,VALUE) \ | |
2336 | { \ | |
2e7ac77c JW |
2337 | long t; \ |
2338 | REAL_VALUE_TO_TARGET_SINGLE ((VALUE), t); \ | |
2339 | fprintf (FILE, "\t%s\t0x%lx\n", ASM_LONG, t); \ | |
2340 | } \ | |
1bb87f28 | 2341 | |
0cd02cbb DE |
2342 | /* This is how to output an assembler line defining a `long double' |
2343 | constant. */ | |
2344 | ||
2345 | #define ASM_OUTPUT_LONG_DOUBLE(FILE,VALUE) \ | |
2346 | { \ | |
2347 | long t[4]; \ | |
2348 | REAL_VALUE_TO_TARGET_LONG_DOUBLE ((VALUE), t); \ | |
2349 | fprintf (FILE, "\t%s\t0x%lx\n\t%s\t0x%lx\n\t%s\t0x%lx\n\t%s\t0x%lx\n", \ | |
2350 | ASM_LONG, t[0], ASM_LONG, t[1], ASM_LONG, t[2], ASM_LONG, t[3]); \ | |
2351 | } | |
2352 | ||
1bb87f28 JW |
2353 | /* This is how to output an assembler line defining an `int' constant. */ |
2354 | ||
2355 | #define ASM_OUTPUT_INT(FILE,VALUE) \ | |
303d524a | 2356 | ( fprintf (FILE, "\t%s\t", ASM_LONG), \ |
1bb87f28 JW |
2357 | output_addr_const (FILE, (VALUE)), \ |
2358 | fprintf (FILE, "\n")) | |
2359 | ||
2360 | /* This is how to output an assembler line defining a DImode constant. */ | |
2361 | #define ASM_OUTPUT_DOUBLE_INT(FILE,VALUE) \ | |
2362 | output_double_int (FILE, VALUE) | |
2363 | ||
2364 | /* Likewise for `char' and `short' constants. */ | |
2365 | ||
2366 | #define ASM_OUTPUT_SHORT(FILE,VALUE) \ | |
303d524a | 2367 | ( fprintf (FILE, "\t%s\t", ASM_SHORT), \ |
1bb87f28 JW |
2368 | output_addr_const (FILE, (VALUE)), \ |
2369 | fprintf (FILE, "\n")) | |
2370 | ||
2371 | #define ASM_OUTPUT_CHAR(FILE,VALUE) \ | |
303d524a | 2372 | ( fprintf (FILE, "\t%s\t", ASM_BYTE_OP), \ |
1bb87f28 JW |
2373 | output_addr_const (FILE, (VALUE)), \ |
2374 | fprintf (FILE, "\n")) | |
2375 | ||
2376 | /* This is how to output an assembler line for a numeric constant byte. */ | |
2377 | ||
2378 | #define ASM_OUTPUT_BYTE(FILE,VALUE) \ | |
303d524a | 2379 | fprintf (FILE, "\t%s\t0x%x\n", ASM_BYTE_OP, (VALUE)) |
1bb87f28 JW |
2380 | |
2381 | /* This is how to output an element of a case-vector that is absolute. */ | |
2382 | ||
2383 | #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ | |
4b69d2a3 RS |
2384 | do { \ |
2385 | char label[30]; \ | |
2386 | ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \ | |
7a6cf439 DE |
2387 | if (Pmode == SImode) \ |
2388 | fprintf (FILE, "\t.word\t"); \ | |
2389 | else if (TARGET_ENV32) \ | |
2390 | fprintf (FILE, "\t.word\t0\n\t.word\t"); \ | |
2391 | else \ | |
2392 | fprintf (FILE, "\t.xword\t"); \ | |
4b69d2a3 RS |
2393 | assemble_name (FILE, label); \ |
2394 | fprintf (FILE, "\n"); \ | |
2395 | } while (0) | |
1bb87f28 JW |
2396 | |
2397 | /* This is how to output an element of a case-vector that is relative. | |
2398 | (SPARC uses such vectors only when generating PIC.) */ | |
2399 | ||
4b69d2a3 RS |
2400 | #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) \ |
2401 | do { \ | |
2402 | char label[30]; \ | |
2403 | ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \ | |
7a6cf439 DE |
2404 | if (Pmode == SImode) \ |
2405 | fprintf (FILE, "\t.word\t"); \ | |
2406 | else if (TARGET_ENV32) \ | |
2407 | fprintf (FILE, "\t.word\t0\n\t.word\t"); \ | |
2408 | else \ | |
2409 | fprintf (FILE, "\t.xword\t"); \ | |
4b69d2a3 RS |
2410 | assemble_name (FILE, label); \ |
2411 | fprintf (FILE, "-1b\n"); \ | |
2412 | } while (0) | |
1bb87f28 JW |
2413 | |
2414 | /* This is how to output an assembler line | |
2415 | that says to advance the location counter | |
2416 | to a multiple of 2**LOG bytes. */ | |
2417 | ||
2418 | #define ASM_OUTPUT_ALIGN(FILE,LOG) \ | |
2419 | if ((LOG) != 0) \ | |
2420 | fprintf (FILE, "\t.align %d\n", (1<<(LOG))) | |
2421 | ||
2422 | #define ASM_OUTPUT_SKIP(FILE,SIZE) \ | |
2423 | fprintf (FILE, "\t.skip %u\n", (SIZE)) | |
2424 | ||
2425 | /* This says how to output an assembler line | |
2426 | to define a global common symbol. */ | |
2427 | ||
2428 | #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \ | |
b277ceaf | 2429 | ( fputs ("\t.common ", (FILE)), \ |
1bb87f28 | 2430 | assemble_name ((FILE), (NAME)), \ |
b277ceaf | 2431 | fprintf ((FILE), ",%u,\"bss\"\n", (SIZE))) |
1bb87f28 | 2432 | |
b277ceaf JW |
2433 | /* This says how to output an assembler line to define a local common |
2434 | symbol. */ | |
1bb87f28 | 2435 | |
b277ceaf JW |
2436 | #define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGNED) \ |
2437 | ( fputs ("\t.reserve ", (FILE)), \ | |
2438 | assemble_name ((FILE), (NAME)), \ | |
2439 | fprintf ((FILE), ",%u,\"bss\",%u\n", \ | |
2440 | (SIZE), ((ALIGNED) / BITS_PER_UNIT))) | |
1bb87f28 JW |
2441 | |
2442 | /* Store in OUTPUT a string (made with alloca) containing | |
2443 | an assembler-name for a local static variable named NAME. | |
2444 | LABELNO is an integer which is different for each call. */ | |
2445 | ||
2446 | #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \ | |
2447 | ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \ | |
2448 | sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO))) | |
2449 | ||
c14f2655 RS |
2450 | #define IDENT_ASM_OP ".ident" |
2451 | ||
2452 | /* Output #ident as a .ident. */ | |
2453 | ||
2454 | #define ASM_OUTPUT_IDENT(FILE, NAME) \ | |
2455 | fprintf (FILE, "\t%s\t\"%s\"\n", IDENT_ASM_OP, NAME); | |
2456 | ||
1bb87f28 JW |
2457 | /* Define the parentheses used to group arithmetic operations |
2458 | in assembler code. */ | |
2459 | ||
2460 | #define ASM_OPEN_PAREN "(" | |
2461 | #define ASM_CLOSE_PAREN ")" | |
2462 | ||
2463 | /* Define results of standard character escape sequences. */ | |
2464 | #define TARGET_BELL 007 | |
2465 | #define TARGET_BS 010 | |
2466 | #define TARGET_TAB 011 | |
2467 | #define TARGET_NEWLINE 012 | |
2468 | #define TARGET_VT 013 | |
2469 | #define TARGET_FF 014 | |
2470 | #define TARGET_CR 015 | |
2471 | ||
2472 | #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \ | |
2ccdef65 | 2473 | ((CHAR) == '#' || (CHAR) == '*' || (CHAR) == '^' || (CHAR) == '(') |
1bb87f28 JW |
2474 | |
2475 | /* Print operand X (an rtx) in assembler syntax to file FILE. | |
2476 | CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. | |
2477 | For `%' followed by punctuation, CODE is the punctuation and X is null. */ | |
2478 | ||
2479 | #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE) | |
2480 | ||
2481 | /* Print a memory address as an operand to reference that memory location. */ | |
2482 | ||
2483 | #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \ | |
2484 | { register rtx base, index = 0; \ | |
2485 | int offset = 0; \ | |
2486 | register rtx addr = ADDR; \ | |
2487 | if (GET_CODE (addr) == REG) \ | |
2488 | fputs (reg_names[REGNO (addr)], FILE); \ | |
2489 | else if (GET_CODE (addr) == PLUS) \ | |
2490 | { \ | |
2491 | if (GET_CODE (XEXP (addr, 0)) == CONST_INT) \ | |
2492 | offset = INTVAL (XEXP (addr, 0)), base = XEXP (addr, 1);\ | |
2493 | else if (GET_CODE (XEXP (addr, 1)) == CONST_INT) \ | |
2494 | offset = INTVAL (XEXP (addr, 1)), base = XEXP (addr, 0);\ | |
2495 | else \ | |
2496 | base = XEXP (addr, 0), index = XEXP (addr, 1); \ | |
2497 | fputs (reg_names[REGNO (base)], FILE); \ | |
2498 | if (index == 0) \ | |
2499 | fprintf (FILE, "%+d", offset); \ | |
2500 | else if (GET_CODE (index) == REG) \ | |
2501 | fprintf (FILE, "+%s", reg_names[REGNO (index)]); \ | |
2502 | else if (GET_CODE (index) == SYMBOL_REF) \ | |
2503 | fputc ('+', FILE), output_addr_const (FILE, index); \ | |
2504 | else abort (); \ | |
2505 | } \ | |
2506 | else if (GET_CODE (addr) == MINUS \ | |
2507 | && GET_CODE (XEXP (addr, 1)) == LABEL_REF) \ | |
2508 | { \ | |
2509 | output_addr_const (FILE, XEXP (addr, 0)); \ | |
2510 | fputs ("-(", FILE); \ | |
2511 | output_addr_const (FILE, XEXP (addr, 1)); \ | |
2512 | fputs ("-.)", FILE); \ | |
2513 | } \ | |
2514 | else if (GET_CODE (addr) == LO_SUM) \ | |
2515 | { \ | |
2516 | output_operand (XEXP (addr, 0), 0); \ | |
2517 | fputs ("+%lo(", FILE); \ | |
2518 | output_address (XEXP (addr, 1)); \ | |
2519 | fputc (')', FILE); \ | |
2520 | } \ | |
2521 | else if (flag_pic && GET_CODE (addr) == CONST \ | |
2522 | && GET_CODE (XEXP (addr, 0)) == MINUS \ | |
2523 | && GET_CODE (XEXP (XEXP (addr, 0), 1)) == CONST \ | |
2524 | && GET_CODE (XEXP (XEXP (XEXP (addr, 0), 1), 0)) == MINUS \ | |
2525 | && XEXP (XEXP (XEXP (XEXP (addr, 0), 1), 0), 1) == pc_rtx) \ | |
2526 | { \ | |
2527 | addr = XEXP (addr, 0); \ | |
2528 | output_addr_const (FILE, XEXP (addr, 0)); \ | |
2529 | /* Group the args of the second CONST in parenthesis. */ \ | |
2530 | fputs ("-(", FILE); \ | |
2531 | /* Skip past the second CONST--it does nothing for us. */\ | |
2532 | output_addr_const (FILE, XEXP (XEXP (addr, 1), 0)); \ | |
2533 | /* Close the parenthesis. */ \ | |
2534 | fputc (')', FILE); \ | |
2535 | } \ | |
2536 | else \ | |
2537 | { \ | |
2538 | output_addr_const (FILE, addr); \ | |
2539 | } \ | |
2540 | } | |
2541 | ||
2542 | /* Declare functions defined in sparc.c and used in templates. */ | |
2543 | ||
2544 | extern char *singlemove_string (); | |
2545 | extern char *output_move_double (); | |
795068a4 | 2546 | extern char *output_move_quad (); |
1bb87f28 | 2547 | extern char *output_fp_move_double (); |
795068a4 | 2548 | extern char *output_fp_move_quad (); |
1bb87f28 JW |
2549 | extern char *output_block_move (); |
2550 | extern char *output_scc_insn (); | |
2551 | extern char *output_cbranch (); | |
7a6cf439 | 2552 | extern char *output_v9branch (); |
1bb87f28 | 2553 | extern char *output_return (); |
1bb87f28 JW |
2554 | |
2555 | /* Defined in flags.h, but insn-emit.c does not include flags.h. */ | |
2556 | ||
2557 | extern int flag_pic; |