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1bb87f28 JW |
1 | /* Definitions of target machine for GNU compiler, for Sun SPARC. |
2 | Copyright (C) 1987, 1988, 1989, 1992 Free Software Foundation, Inc. | |
3 | Contributed by Michael Tiemann (tiemann@cygnus.com). | |
4 | ||
5 | This file is part of GNU CC. | |
6 | ||
7 | GNU CC is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2, or (at your option) | |
10 | any later version. | |
11 | ||
12 | GNU CC is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GNU CC; see the file COPYING. If not, write to | |
19 | the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ | |
20 | ||
21 | /* Note that some other tm.h files include this one and then override | |
22 | many of the definitions that relate to assembler syntax. */ | |
23 | ||
d95c3733 JW |
24 | #define LIB_SPEC "%{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p} %{g:-lg} \ |
25 | %{a:/usr/lib/bb_link.o}" | |
1bb87f28 | 26 | |
98ccf8fe | 27 | /* Provide required defaults for linker -e and -d switches. */ |
1bb87f28 | 28 | |
d6f04508 | 29 | #define LINK_SPEC \ |
197a1140 | 30 | "%{!nostdlib:%{!r*:%{!e*:-e start}}} -dc -dp %{static:-Bstatic} %{assert*}" |
1bb87f28 JW |
31 | |
32 | /* Special flags to the Sun-4 assembler when using pipe for input. */ | |
33 | ||
cf8a904b | 34 | #define ASM_SPEC " %| %{fpic:-k} %{fPIC:-k}" |
1bb87f28 | 35 | |
885d8175 | 36 | /* Define macros to distinguish architectures. */ |
bc9e02ae JW |
37 | #define CPP_SPEC "%{msparclite:-D__sparclite__} %{mf930:-D__sparclite__} \ |
38 | %{mf934:-D__sparclite__} %{mv8:-D__sparc_v8__}" | |
885d8175 | 39 | |
b1fc14e5 RS |
40 | /* Prevent error on `-sun4' and `-target sun4' options. */ |
41 | /* This used to translate -dalign to -malign, but that is no good | |
42 | because it can't turn off the usual meaning of making debugging dumps. */ | |
1bb87f28 | 43 | |
b1fc14e5 | 44 | #define CC1_SPEC "%{sun4:} %{target:}" |
1bb87f28 JW |
45 | |
46 | #define PTRDIFF_TYPE "int" | |
1ede52a6 RS |
47 | /* In 2.4 it should work to delete this. |
48 | #define SIZE_TYPE "int" */ | |
1bb87f28 JW |
49 | #define WCHAR_TYPE "short unsigned int" |
50 | #define WCHAR_TYPE_SIZE 16 | |
51 | ||
98ccf8fe RK |
52 | /* Omit frame pointer at high optimization levels. */ |
53 | ||
1bb87f28 JW |
54 | #define OPTIMIZATION_OPTIONS(OPTIMIZE) \ |
55 | { \ | |
56 | if (OPTIMIZE >= 2) \ | |
57 | { \ | |
58 | flag_omit_frame_pointer = 1; \ | |
1bb87f28 JW |
59 | } \ |
60 | } | |
61 | ||
5b485d2c JW |
62 | /* To make profiling work with -f{pic,PIC}, we need to emit the profiling |
63 | code into the rtl. Also, if we are profiling, we cannot eliminate | |
64 | the frame pointer (because the return address will get smashed). */ | |
65 | ||
66 | #define OVERRIDE_OPTIONS \ | |
84ab3bfb JW |
67 | { \ |
68 | if (profile_flag || profile_block_flag) \ | |
69 | flag_omit_frame_pointer = 0, flag_pic = 0; \ | |
70 | SUBTARGET_OVERRIDE_OPTIONS \ | |
71 | } | |
72 | ||
73 | /* This is meant to be redefined in the host dependent files */ | |
74 | #define SUBTARGET_OVERRIDE_OPTIONS | |
5b485d2c | 75 | |
1bb87f28 JW |
76 | /* These compiler options take an argument. We ignore -target for now. */ |
77 | ||
78 | #define WORD_SWITCH_TAKES_ARG(STR) \ | |
3b39b94f ILT |
79 | (DEFAULT_WORD_SWITCH_TAKES_ARG (STR) \ |
80 | || !strcmp (STR, "target") || !strcmp (STR, "assert")) | |
1bb87f28 JW |
81 | |
82 | /* Names to predefine in the preprocessor for this target machine. */ | |
83 | ||
f19c1a78 JW |
84 | /* The GCC_NEW_VARARGS macro is so that old versions of gcc can compile |
85 | new versions, which have an incompatible va-sparc.h file. This matters | |
86 | because gcc does "gvarargs.h" instead of <varargs.h>, and thus gets the | |
87 | wrong varargs file when it is compiled with a different version of gcc. */ | |
88 | ||
65c42379 DE |
89 | #define CPP_PREDEFINES \ |
90 | "-Dsparc -Dsun -Dunix -D__GCC_NEW_VARARGS__ \ | |
91 | -Asystem(unix) -Asystem(bsd) -Acpu(sparc) -Amachine(sparc)" | |
1bb87f28 JW |
92 | |
93 | /* Print subsidiary information on the compiler version in use. */ | |
94 | ||
95 | #define TARGET_VERSION fprintf (stderr, " (sparc)"); | |
96 | ||
97 | /* Generate DBX debugging information. */ | |
98 | ||
99 | #define DBX_DEBUGGING_INFO | |
100 | ||
101 | /* Run-time compilation parameters selecting different hardware subsets. */ | |
102 | ||
103 | extern int target_flags; | |
104 | ||
105 | /* Nonzero if we should generate code to use the fpu. */ | |
106 | #define TARGET_FPU (target_flags & 1) | |
107 | ||
108 | /* Nonzero if we should use FUNCTION_EPILOGUE. Otherwise, we | |
109 | use fast return insns, but lose some generality. */ | |
110 | #define TARGET_EPILOGUE (target_flags & 2) | |
111 | ||
95dea81f JW |
112 | /* Nonzero if we should assume that double pointers might be unaligned. |
113 | This can happen when linking gcc compiled code with other compilers, | |
114 | because the ABI only guarantees 4 byte alignment. */ | |
115 | #define TARGET_UNALIGNED_DOUBLES (target_flags & 4) | |
1bb87f28 | 116 | |
885d8175 JW |
117 | /* Nonzero means that we should generate code for a v8 sparc. */ |
118 | #define TARGET_V8 (target_flags & 64) | |
119 | ||
bc9e02ae JW |
120 | /* Nonzero means that we should generate code for a sparclite. |
121 | This enables the sparclite specific instructions, but does not affect | |
122 | whether FPU instructions are emitted. */ | |
885d8175 JW |
123 | #define TARGET_SPARCLITE (target_flags & 128) |
124 | ||
5b485d2c | 125 | /* Nonzero means that we should generate code using a flat register window |
9a1c7cd7 JW |
126 | model, i.e. no save/restore instructions are generated, in the most |
127 | efficient manner. This code is not compatible with normal sparc code. */ | |
128 | /* This is not a user selectable option yet, because it requires changes | |
129 | that are not yet switchable via command line arguments. */ | |
5b485d2c JW |
130 | #define TARGET_FRW (target_flags & 256) |
131 | ||
9a1c7cd7 JW |
132 | /* Nonzero means that we should generate code using a flat register window |
133 | model, i.e. no save/restore instructions are generated, but which is | |
134 | compatible with normal sparc code. This is the same as above, except | |
135 | that the frame pointer is %l6 instead of %fp. This code is not as efficient | |
136 | as TARGET_FRW, because it has one less allocatable register. */ | |
137 | /* This is not a user selectable option yet, because it requires changes | |
138 | that are not yet switchable via command line arguments. */ | |
139 | #define TARGET_FRW_COMPAT (target_flags & 512) | |
140 | ||
1bb87f28 JW |
141 | /* Macro to define tables used to set the flags. |
142 | This is a list in braces of pairs in braces, | |
143 | each pair being { "NAME", VALUE } | |
144 | where VALUE is the bits to set or minus the bits to clear. | |
145 | An empty string NAME is used to identify the default VALUE. */ | |
146 | ||
bc9e02ae JW |
147 | /* The Fujitsu MB86930 is the original sparclite chip, with no fpu. |
148 | The Fujitsu MB86934 is the recent sparclite chip, with an fup. | |
149 | We use -mf930 and -mf934 options to choose which. | |
150 | ??? These should perhaps be -mcpu= options. */ | |
151 | ||
1bb87f28 JW |
152 | #define TARGET_SWITCHES \ |
153 | { {"fpu", 1}, \ | |
26c5587d JW |
154 | {"no-fpu", -1}, \ |
155 | {"hard-float", 1}, \ | |
1bb87f28 JW |
156 | {"soft-float", -1}, \ |
157 | {"epilogue", 2}, \ | |
158 | {"no-epilogue", -2}, \ | |
95dea81f JW |
159 | {"unaligned-doubles", 4}, \ |
160 | {"no-unaligned-doubles", -4},\ | |
885d8175 JW |
161 | {"v8", 64}, \ |
162 | {"no-v8", -64}, \ | |
163 | {"sparclite", 128}, \ | |
164 | {"no-sparclite", -128}, \ | |
9a1c7cd7 JW |
165 | /* {"frw", 256}, */ \ |
166 | /* {"no-frw", -256}, */ \ | |
167 | /* {"frw-compat", 256+512}, */ \ | |
168 | /* {"no-frw-compat", -(256+512)}, */ \ | |
bc9e02ae JW |
169 | {"f930", 128}, \ |
170 | {"f930", -1}, \ | |
171 | {"f934", 128}, \ | |
84ab3bfb | 172 | SUBTARGET_SWITCHES \ |
b1fc14e5 | 173 | { "", TARGET_DEFAULT}} |
1bb87f28 JW |
174 | |
175 | #define TARGET_DEFAULT 3 | |
84ab3bfb JW |
176 | |
177 | /* This is meant to be redefined in the host dependent files */ | |
178 | #define SUBTARGET_SWITCHES | |
1bb87f28 JW |
179 | \f |
180 | /* target machine storage layout */ | |
181 | ||
d667538b JW |
182 | /* Define for support of TFmode long double and REAL_ARITHMETIC. |
183 | Sparc ABI says that long double is 4 words. */ | |
184 | #define LONG_DOUBLE_TYPE_SIZE 128 | |
d667538b JW |
185 | |
186 | /* Define for cross-compilation to a sparc target with no TFmode from a host | |
187 | with a different float format (e.g. VAX). */ | |
188 | #define REAL_ARITHMETIC | |
189 | ||
1bb87f28 JW |
190 | /* Define this if most significant bit is lowest numbered |
191 | in instructions that operate on numbered bit-fields. */ | |
192 | #define BITS_BIG_ENDIAN 1 | |
193 | ||
194 | /* Define this if most significant byte of a word is the lowest numbered. */ | |
195 | /* This is true on the SPARC. */ | |
196 | #define BYTES_BIG_ENDIAN 1 | |
197 | ||
198 | /* Define this if most significant word of a multiword number is the lowest | |
199 | numbered. */ | |
200 | /* Doubles are stored in memory with the high order word first. This | |
201 | matters when cross-compiling. */ | |
202 | #define WORDS_BIG_ENDIAN 1 | |
203 | ||
b4ac57ab | 204 | /* number of bits in an addressable storage unit */ |
1bb87f28 JW |
205 | #define BITS_PER_UNIT 8 |
206 | ||
207 | /* Width in bits of a "word", which is the contents of a machine register. | |
208 | Note that this is not necessarily the width of data type `int'; | |
209 | if using 16-bit ints on a 68000, this would still be 32. | |
210 | But on a machine with 16-bit registers, this would be 16. */ | |
211 | #define BITS_PER_WORD 32 | |
212 | #define MAX_BITS_PER_WORD 32 | |
213 | ||
214 | /* Width of a word, in units (bytes). */ | |
215 | #define UNITS_PER_WORD 4 | |
216 | ||
217 | /* Width in bits of a pointer. | |
218 | See also the macro `Pmode' defined below. */ | |
219 | #define POINTER_SIZE 32 | |
220 | ||
221 | /* Allocation boundary (in *bits*) for storing arguments in argument list. */ | |
222 | #define PARM_BOUNDARY 32 | |
223 | ||
224 | /* Boundary (in *bits*) on which stack pointer should be aligned. */ | |
225 | #define STACK_BOUNDARY 64 | |
226 | ||
10d1b70f JW |
227 | /* ALIGN FRAMES on double word boundaries */ |
228 | ||
229 | #define SPARC_STACK_ALIGN(LOC) (((LOC)+7) & 0xfffffff8) | |
230 | ||
1bb87f28 JW |
231 | /* Allocation boundary (in *bits*) for the code of a function. */ |
232 | #define FUNCTION_BOUNDARY 32 | |
233 | ||
234 | /* Alignment of field after `int : 0' in a structure. */ | |
235 | #define EMPTY_FIELD_BOUNDARY 32 | |
236 | ||
237 | /* Every structure's size must be a multiple of this. */ | |
238 | #define STRUCTURE_SIZE_BOUNDARY 8 | |
239 | ||
240 | /* A bitfield declared as `int' forces `int' alignment for the struct. */ | |
241 | #define PCC_BITFIELD_TYPE_MATTERS 1 | |
242 | ||
243 | /* No data type wants to be aligned rounder than this. */ | |
244 | #define BIGGEST_ALIGNMENT 64 | |
245 | ||
77a02b01 JW |
246 | /* The best alignment to use in cases where we have a choice. */ |
247 | #define FASTEST_ALIGNMENT 64 | |
248 | ||
1bb87f28 JW |
249 | /* Make strings word-aligned so strcpy from constants will be faster. */ |
250 | #define CONSTANT_ALIGNMENT(EXP, ALIGN) \ | |
d2a8e680 RS |
251 | ((TREE_CODE (EXP) == STRING_CST \ |
252 | && (ALIGN) < FASTEST_ALIGNMENT) \ | |
253 | ? FASTEST_ALIGNMENT : (ALIGN)) | |
1bb87f28 JW |
254 | |
255 | /* Make arrays of chars word-aligned for the same reasons. */ | |
256 | #define DATA_ALIGNMENT(TYPE, ALIGN) \ | |
257 | (TREE_CODE (TYPE) == ARRAY_TYPE \ | |
258 | && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \ | |
77a02b01 | 259 | && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN)) |
1bb87f28 | 260 | |
b4ac57ab | 261 | /* Set this nonzero if move instructions will actually fail to work |
1bb87f28 | 262 | when given unaligned data. */ |
b4ac57ab | 263 | #define STRICT_ALIGNMENT 1 |
1bb87f28 JW |
264 | |
265 | /* Things that must be doubleword aligned cannot go in the text section, | |
266 | because the linker fails to align the text section enough! | |
267 | Put them in the data section. */ | |
268 | #define MAX_TEXT_ALIGN 32 | |
269 | ||
270 | #define SELECT_SECTION(T,RELOC) \ | |
271 | { \ | |
272 | if (TREE_CODE (T) == VAR_DECL) \ | |
273 | { \ | |
274 | if (TREE_READONLY (T) && ! TREE_SIDE_EFFECTS (T) \ | |
275 | && DECL_ALIGN (T) <= MAX_TEXT_ALIGN \ | |
276 | && ! (flag_pic && (RELOC))) \ | |
277 | text_section (); \ | |
278 | else \ | |
279 | data_section (); \ | |
280 | } \ | |
281 | else if (TREE_CODE (T) == CONSTRUCTOR) \ | |
282 | { \ | |
283 | if (flag_pic != 0 && (RELOC) != 0) \ | |
284 | data_section (); \ | |
285 | } \ | |
286 | else if (*tree_code_type[(int) TREE_CODE (T)] == 'c') \ | |
287 | { \ | |
288 | if ((TREE_CODE (T) == STRING_CST && flag_writable_strings) \ | |
289 | || TYPE_ALIGN (TREE_TYPE (T)) > MAX_TEXT_ALIGN) \ | |
290 | data_section (); \ | |
291 | else \ | |
292 | text_section (); \ | |
293 | } \ | |
294 | } | |
295 | ||
296 | /* Use text section for a constant | |
297 | unless we need more alignment than that offers. */ | |
298 | #define SELECT_RTX_SECTION(MODE, X) \ | |
299 | { \ | |
300 | if (GET_MODE_BITSIZE (MODE) <= MAX_TEXT_ALIGN \ | |
301 | && ! (flag_pic && symbolic_operand (X))) \ | |
302 | text_section (); \ | |
303 | else \ | |
304 | data_section (); \ | |
305 | } | |
306 | \f | |
307 | /* Standard register usage. */ | |
308 | ||
309 | /* Number of actual hardware registers. | |
310 | The hardware registers are assigned numbers for the compiler | |
311 | from 0 to just below FIRST_PSEUDO_REGISTER. | |
312 | All registers that the compiler knows about must be given numbers, | |
313 | even those that are not normally considered general registers. | |
314 | ||
315 | SPARC has 32 integer registers and 32 floating point registers. */ | |
316 | ||
317 | #define FIRST_PSEUDO_REGISTER 64 | |
318 | ||
319 | /* 1 for registers that have pervasive standard uses | |
320 | and are not available for the register allocator. | |
5b485d2c | 321 | g0 is used for the condition code and not to represent %g0, which is |
1bb87f28 | 322 | hardwired to 0, so reg 0 is *not* fixed. |
d9ca49d5 JW |
323 | g1 through g4 are free to use as temporaries. |
324 | g5 through g7 are reserved for the operating system. */ | |
1bb87f28 | 325 | #define FIXED_REGISTERS \ |
d9ca49d5 | 326 | {0, 0, 0, 0, 0, 1, 1, 1, \ |
1bb87f28 JW |
327 | 0, 0, 0, 0, 0, 0, 1, 0, \ |
328 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
329 | 0, 0, 0, 0, 0, 0, 1, 1, \ | |
330 | \ | |
331 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
332 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
333 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
334 | 0, 0, 0, 0, 0, 0, 0, 0} | |
335 | ||
336 | /* 1 for registers not available across function calls. | |
337 | These must include the FIXED_REGISTERS and also any | |
338 | registers that can be used without being saved. | |
339 | The latter must include the registers where values are returned | |
340 | and the register where structure-value addresses are passed. | |
341 | Aside from that, you can include as many other registers as you like. */ | |
342 | #define CALL_USED_REGISTERS \ | |
343 | {1, 1, 1, 1, 1, 1, 1, 1, \ | |
344 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
345 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
346 | 0, 0, 0, 0, 0, 0, 1, 1, \ | |
347 | \ | |
348 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
349 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
350 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
351 | 1, 1, 1, 1, 1, 1, 1, 1} | |
352 | ||
26c5587d JW |
353 | /* If !TARGET_FPU, then make the fp registers fixed so that they won't |
354 | be allocated. */ | |
355 | ||
356 | #define CONDITIONAL_REGISTER_USAGE \ | |
357 | do \ | |
358 | { \ | |
359 | if (! TARGET_FPU) \ | |
360 | { \ | |
361 | int regno; \ | |
362 | for (regno = 32; regno < 64; regno++) \ | |
363 | fixed_regs[regno] = 1; \ | |
364 | } \ | |
365 | } \ | |
366 | while (0) | |
367 | ||
1bb87f28 JW |
368 | /* Return number of consecutive hard regs needed starting at reg REGNO |
369 | to hold something of mode MODE. | |
370 | This is ordinarily the length in words of a value of mode MODE | |
371 | but can be less for certain modes in special long registers. | |
372 | ||
373 | On SPARC, ordinary registers hold 32 bits worth; | |
374 | this means both integer and floating point registers. | |
375 | ||
376 | We use vectors to keep this information about registers. */ | |
377 | ||
378 | /* How many hard registers it takes to make a register of this mode. */ | |
379 | extern int hard_regno_nregs[]; | |
380 | ||
381 | #define HARD_REGNO_NREGS(REGNO, MODE) \ | |
382 | ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) | |
383 | ||
384 | /* Value is 1 if register/mode pair is acceptable on sparc. */ | |
385 | extern int hard_regno_mode_ok[FIRST_PSEUDO_REGISTER]; | |
386 | ||
387 | /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. | |
388 | On SPARC, the cpu registers can hold any mode but the float registers | |
389 | can only hold SFmode or DFmode. See sparc.c for how we | |
390 | initialize this. */ | |
391 | #define HARD_REGNO_MODE_OK(REGNO, MODE) \ | |
392 | ((hard_regno_mode_ok[REGNO] & (1<<(int)(MODE))) != 0) | |
393 | ||
394 | /* Value is 1 if it is a good idea to tie two pseudo registers | |
395 | when one has mode MODE1 and one has mode MODE2. | |
396 | If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, | |
397 | for any hard reg, then this must be 0 for correct output. */ | |
398 | #define MODES_TIEABLE_P(MODE1, MODE2) \ | |
399 | ((MODE1) == (MODE2) || GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2)) | |
400 | ||
401 | /* Specify the registers used for certain standard purposes. | |
402 | The values of these macros are register numbers. */ | |
403 | ||
404 | /* SPARC pc isn't overloaded on a register that the compiler knows about. */ | |
405 | /* #define PC_REGNUM */ | |
406 | ||
407 | /* Register to use for pushing function arguments. */ | |
408 | #define STACK_POINTER_REGNUM 14 | |
409 | ||
410 | /* Actual top-of-stack address is 92 greater than the contents | |
411 | of the stack pointer register. 92 = 68 + 24. 64 bytes reserving space | |
412 | for the ins and local registers, 4 byte for structure return address, and | |
413 | 24 bytes for the 6 register parameters. */ | |
414 | #define STACK_POINTER_OFFSET FIRST_PARM_OFFSET(0) | |
415 | ||
416 | /* Base register for access to local variables of the function. */ | |
417 | #define FRAME_POINTER_REGNUM 30 | |
418 | ||
419 | #if 0 | |
420 | /* Register that is used for the return address. */ | |
421 | #define RETURN_ADDR_REGNUM 15 | |
422 | #endif | |
423 | ||
424 | /* Value should be nonzero if functions must have frame pointers. | |
425 | Zero means the frame pointer need not be set up (and parms | |
426 | may be accessed via the stack pointer) in functions that seem suitable. | |
427 | This is computed in `reload', in reload1.c. | |
428 | ||
c0524a34 | 429 | Used in flow.c, global.c, and reload1.c. */ |
1bb87f28 JW |
430 | extern int leaf_function; |
431 | ||
432 | #define FRAME_POINTER_REQUIRED \ | |
a72cb8ec | 433 | (! (leaf_function_p () && only_leaf_regs_used ())) |
1bb87f28 JW |
434 | |
435 | /* C statement to store the difference between the frame pointer | |
436 | and the stack pointer values immediately after the function prologue. | |
437 | ||
438 | Note, we always pretend that this is a leaf function because if | |
439 | it's not, there's no point in trying to eliminate the | |
440 | frame pointer. If it is a leaf function, we guessed right! */ | |
441 | #define INITIAL_FRAME_POINTER_OFFSET(VAR) \ | |
5b485d2c JW |
442 | ((VAR) = (TARGET_FRW ? sparc_frw_compute_frame_size (get_frame_size ()) \ |
443 | : compute_frame_size (get_frame_size (), 1))) | |
1bb87f28 JW |
444 | |
445 | /* Base register for access to arguments of the function. */ | |
446 | #define ARG_POINTER_REGNUM 30 | |
447 | ||
448 | /* Register in which static-chain is passed to a function. */ | |
449 | /* ??? */ | |
450 | #define STATIC_CHAIN_REGNUM 1 | |
451 | ||
452 | /* Register which holds offset table for position-independent | |
453 | data references. */ | |
454 | ||
455 | #define PIC_OFFSET_TABLE_REGNUM 23 | |
456 | ||
457 | #define INITIALIZE_PIC initialize_pic () | |
458 | #define FINALIZE_PIC finalize_pic () | |
459 | ||
d9ca49d5 | 460 | /* Sparc ABI says that quad-precision floats and all structures are returned |
59d7764f | 461 | in memory. */ |
d9ca49d5 | 462 | #define RETURN_IN_MEMORY(TYPE) \ |
e14fa9c4 | 463 | (TYPE_MODE (TYPE) == BLKmode || TYPE_MODE (TYPE) == TFmode) |
d9ca49d5 | 464 | |
1bb87f28 JW |
465 | /* Functions which return large structures get the address |
466 | to place the wanted value at offset 64 from the frame. | |
467 | Must reserve 64 bytes for the in and local registers. */ | |
468 | /* Used only in other #defines in this file. */ | |
469 | #define STRUCT_VALUE_OFFSET 64 | |
470 | ||
471 | #define STRUCT_VALUE \ | |
472 | gen_rtx (MEM, Pmode, \ | |
473 | gen_rtx (PLUS, Pmode, stack_pointer_rtx, \ | |
474 | gen_rtx (CONST_INT, VOIDmode, STRUCT_VALUE_OFFSET))) | |
475 | #define STRUCT_VALUE_INCOMING \ | |
476 | gen_rtx (MEM, Pmode, \ | |
477 | gen_rtx (PLUS, Pmode, frame_pointer_rtx, \ | |
478 | gen_rtx (CONST_INT, VOIDmode, STRUCT_VALUE_OFFSET))) | |
479 | \f | |
480 | /* Define the classes of registers for register constraints in the | |
481 | machine description. Also define ranges of constants. | |
482 | ||
483 | One of the classes must always be named ALL_REGS and include all hard regs. | |
484 | If there is more than one class, another class must be named NO_REGS | |
485 | and contain no registers. | |
486 | ||
487 | The name GENERAL_REGS must be the name of a class (or an alias for | |
488 | another name such as ALL_REGS). This is the class of registers | |
489 | that is allowed by "g" or "r" in a register constraint. | |
490 | Also, registers outside this class are allocated only when | |
491 | instructions express preferences for them. | |
492 | ||
493 | The classes must be numbered in nondecreasing order; that is, | |
494 | a larger-numbered class must never be contained completely | |
495 | in a smaller-numbered class. | |
496 | ||
497 | For any two classes, it is very desirable that there be another | |
498 | class that represents their union. */ | |
499 | ||
500 | /* The SPARC has two kinds of registers, general and floating point. */ | |
501 | ||
502 | enum reg_class { NO_REGS, GENERAL_REGS, FP_REGS, ALL_REGS, LIM_REG_CLASSES }; | |
503 | ||
504 | #define N_REG_CLASSES (int) LIM_REG_CLASSES | |
505 | ||
506 | /* Give names of register classes as strings for dump file. */ | |
507 | ||
508 | #define REG_CLASS_NAMES \ | |
509 | {"NO_REGS", "GENERAL_REGS", "FP_REGS", "ALL_REGS" } | |
510 | ||
511 | /* Define which registers fit in which classes. | |
512 | This is an initializer for a vector of HARD_REG_SET | |
513 | of length N_REG_CLASSES. */ | |
514 | ||
515 | #if 0 && defined (__GNUC__) | |
516 | #define REG_CLASS_CONTENTS {0LL, 0xfffffffeLL, 0xffffffff00000000LL, 0xfffffffffffffffeLL} | |
517 | #else | |
518 | #define REG_CLASS_CONTENTS {{0, 0}, {-2, 0}, {0, -1}, {-2, -1}} | |
519 | #endif | |
520 | ||
521 | /* The same information, inverted: | |
522 | Return the class number of the smallest class containing | |
523 | reg number REGNO. This could be a conditional expression | |
524 | or could index an array. */ | |
525 | ||
526 | #define REGNO_REG_CLASS(REGNO) \ | |
527 | ((REGNO) >= 32 ? FP_REGS : (REGNO) == 0 ? NO_REGS : GENERAL_REGS) | |
528 | ||
529 | /* This is the order in which to allocate registers | |
51f0e748 JW |
530 | normally. |
531 | ||
532 | We put %f0/%f1 last among the float registers, so as to make it more | |
6a4bb1fa | 533 | likely that a pseudo-register which dies in the float return register |
51f0e748 JW |
534 | will get allocated to the float return register, thus saving a move |
535 | instruction at the end of the function. */ | |
1bb87f28 | 536 | #define REG_ALLOC_ORDER \ |
b4ac57ab RS |
537 | { 8, 9, 10, 11, 12, 13, 2, 3, \ |
538 | 15, 16, 17, 18, 19, 20, 21, 22, \ | |
539 | 23, 24, 25, 26, 27, 28, 29, 31, \ | |
51f0e748 | 540 | 34, 35, 36, 37, 38, 39, \ |
1bb87f28 JW |
541 | 40, 41, 42, 43, 44, 45, 46, 47, \ |
542 | 48, 49, 50, 51, 52, 53, 54, 55, \ | |
543 | 56, 57, 58, 59, 60, 61, 62, 63, \ | |
51f0e748 | 544 | 32, 33, \ |
4b69d2a3 | 545 | 1, 4, 5, 6, 7, 0, 14, 30} |
1bb87f28 JW |
546 | |
547 | /* This is the order in which to allocate registers for | |
548 | leaf functions. If all registers can fit in the "i" registers, | |
549 | then we have the possibility of having a leaf function. */ | |
550 | #define REG_LEAF_ALLOC_ORDER \ | |
551 | { 2, 3, 24, 25, 26, 27, 28, 29, \ | |
552 | 15, 8, 9, 10, 11, 12, 13, \ | |
553 | 16, 17, 18, 19, 20, 21, 22, 23, \ | |
51f0e748 | 554 | 34, 35, 36, 37, 38, 39, \ |
1bb87f28 JW |
555 | 40, 41, 42, 43, 44, 45, 46, 47, \ |
556 | 48, 49, 50, 51, 52, 53, 54, 55, \ | |
557 | 56, 57, 58, 59, 60, 61, 62, 63, \ | |
51f0e748 | 558 | 32, 33, \ |
4b69d2a3 | 559 | 1, 4, 5, 6, 7, 0, 14, 30, 31} |
1bb87f28 JW |
560 | |
561 | #define ORDER_REGS_FOR_LOCAL_ALLOC order_regs_for_local_alloc () | |
562 | ||
563 | #define LEAF_REGISTERS \ | |
564 | { 1, 1, 1, 1, 1, 1, 1, 1, \ | |
565 | 0, 0, 0, 0, 0, 0, 1, 0, \ | |
566 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
567 | 1, 1, 1, 1, 1, 1, 0, 1, \ | |
568 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
569 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
570 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
4b69d2a3 | 571 | 1, 1, 1, 1, 1, 1, 1, 1} |
1bb87f28 JW |
572 | |
573 | extern char leaf_reg_remap[]; | |
574 | #define LEAF_REG_REMAP(REGNO) (leaf_reg_remap[REGNO]) | |
575 | extern char leaf_reg_backmap[]; | |
576 | #define LEAF_REG_BACKMAP(REGNO) (leaf_reg_backmap[REGNO]) | |
577 | ||
1bb87f28 JW |
578 | /* The class value for index registers, and the one for base regs. */ |
579 | #define INDEX_REG_CLASS GENERAL_REGS | |
580 | #define BASE_REG_CLASS GENERAL_REGS | |
581 | ||
582 | /* Get reg_class from a letter such as appears in the machine description. */ | |
583 | ||
584 | #define REG_CLASS_FROM_LETTER(C) \ | |
585 | ((C) == 'f' ? FP_REGS : (C) == 'r' ? GENERAL_REGS : NO_REGS) | |
586 | ||
587 | /* The letters I, J, K, L and M in a register constraint string | |
588 | can be used to stand for particular ranges of immediate operands. | |
589 | This macro defines what the ranges are. | |
590 | C is the letter, and VALUE is a constant value. | |
591 | Return 1 if VALUE is in the range specified by C. | |
592 | ||
593 | For SPARC, `I' is used for the range of constants an insn | |
594 | can actually contain. | |
595 | `J' is used for the range which is just zero (since that is R0). | |
9ad2c692 | 596 | `K' is used for constants which can be loaded with a single sethi insn. */ |
1bb87f28 JW |
597 | |
598 | #define SMALL_INT(X) ((unsigned) (INTVAL (X) + 0x1000) < 0x2000) | |
599 | ||
600 | #define CONST_OK_FOR_LETTER_P(VALUE, C) \ | |
601 | ((C) == 'I' ? (unsigned) ((VALUE) + 0x1000) < 0x2000 \ | |
602 | : (C) == 'J' ? (VALUE) == 0 \ | |
603 | : (C) == 'K' ? ((VALUE) & 0x3ff) == 0 \ | |
604 | : 0) | |
605 | ||
606 | /* Similar, but for floating constants, and defining letters G and H. | |
607 | Here VALUE is the CONST_DOUBLE rtx itself. */ | |
608 | ||
609 | #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \ | |
96f69de5 | 610 | ((C) == 'G' ? fp_zero_operand (VALUE) \ |
1bb87f28 JW |
611 | : (C) == 'H' ? arith_double_operand (VALUE, DImode) \ |
612 | : 0) | |
613 | ||
614 | /* Given an rtx X being reloaded into a reg required to be | |
615 | in class CLASS, return the class of reg to actually use. | |
616 | In general this is just CLASS; but on some machines | |
617 | in some cases it is preferable to use a more restrictive class. */ | |
2b9a9aea JW |
618 | /* We can't load constants into FP registers. We can't load any FP constant |
619 | if an 'E' constraint fails to match it. */ | |
620 | #define PREFERRED_RELOAD_CLASS(X,CLASS) \ | |
621 | (CONSTANT_P (X) \ | |
622 | && ((CLASS) == FP_REGS \ | |
623 | || (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \ | |
624 | && (HOST_FLOAT_FORMAT != IEEE_FLOAT_FORMAT \ | |
625 | || HOST_BITS_PER_INT != BITS_PER_WORD))) \ | |
626 | ? NO_REGS : (CLASS)) | |
1bb87f28 JW |
627 | |
628 | /* Return the register class of a scratch register needed to load IN into | |
629 | a register of class CLASS in MODE. | |
630 | ||
631 | On the SPARC, when PIC, we need a temporary when loading some addresses | |
ae51bd97 | 632 | into a register. |
1bb87f28 | 633 | |
ae51bd97 JW |
634 | Also, we need a temporary when loading/storing a HImode/QImode value |
635 | between memory and the FPU registers. This can happen when combine puts | |
636 | a paradoxical subreg in a float/fix conversion insn. */ | |
637 | ||
638 | #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, IN) \ | |
7aca9b9c | 639 | (((CLASS) == FP_REGS && ((MODE) == HImode || (MODE) == QImode)\ |
ae51bd97 JW |
640 | && (GET_CODE (IN) == MEM \ |
641 | || ((GET_CODE (IN) == REG || GET_CODE (IN) == SUBREG) \ | |
642 | && true_regnum (IN) == -1))) ? GENERAL_REGS : NO_REGS) | |
643 | ||
644 | #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, IN) \ | |
645 | ((CLASS) == FP_REGS && ((MODE) == HImode || (MODE) == QImode) \ | |
646 | && (GET_CODE (IN) == MEM \ | |
647 | || ((GET_CODE (IN) == REG || GET_CODE (IN) == SUBREG) \ | |
648 | && true_regnum (IN) == -1)) ? GENERAL_REGS : NO_REGS) | |
1bb87f28 | 649 | |
b924cef0 JW |
650 | /* On SPARC it is not possible to directly move data between |
651 | GENERAL_REGS and FP_REGS. */ | |
652 | #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \ | |
ae51bd97 JW |
653 | (((CLASS1) == FP_REGS && (CLASS2) == GENERAL_REGS) \ |
654 | || ((CLASS1) == GENERAL_REGS && (CLASS2) == FP_REGS)) | |
b924cef0 | 655 | |
fe1f7f24 JW |
656 | /* Return the stack location to use for secondary memory needed reloads. */ |
657 | #define SECONDARY_MEMORY_NEEDED_RTX(MODE) \ | |
15f67e06 JW |
658 | gen_rtx (MEM, MODE, gen_rtx (PLUS, Pmode, frame_pointer_rtx, \ |
659 | GEN_INT (STARTING_FRAME_OFFSET))) | |
fe1f7f24 | 660 | |
1bb87f28 JW |
661 | /* Return the maximum number of consecutive registers |
662 | needed to represent mode MODE in a register of class CLASS. */ | |
663 | /* On SPARC, this is the size of MODE in words. */ | |
664 | #define CLASS_MAX_NREGS(CLASS, MODE) \ | |
665 | ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) | |
666 | \f | |
667 | /* Stack layout; function entry, exit and calling. */ | |
668 | ||
669 | /* Define the number of register that can hold parameters. | |
670 | These two macros are used only in other macro definitions below. */ | |
671 | #define NPARM_REGS 6 | |
672 | ||
673 | /* Define this if pushing a word on the stack | |
674 | makes the stack pointer a smaller address. */ | |
675 | #define STACK_GROWS_DOWNWARD | |
676 | ||
677 | /* Define this if the nominal address of the stack frame | |
678 | is at the high-address end of the local variables; | |
679 | that is, each additional local variable allocated | |
680 | goes at a more negative offset in the frame. */ | |
681 | #define FRAME_GROWS_DOWNWARD | |
682 | ||
683 | /* Offset within stack frame to start allocating local variables at. | |
684 | If FRAME_GROWS_DOWNWARD, this is the offset to the END of the | |
685 | first local allocated. Otherwise, it is the offset to the BEGINNING | |
686 | of the first local allocated. */ | |
15f67e06 JW |
687 | /* This is 16 to allow space for one TFmode floating point value. */ |
688 | #define STARTING_FRAME_OFFSET (-16) | |
1bb87f28 JW |
689 | |
690 | /* If we generate an insn to push BYTES bytes, | |
691 | this says how many the stack pointer really advances by. | |
692 | On SPARC, don't define this because there are no push insns. */ | |
693 | /* #define PUSH_ROUNDING(BYTES) */ | |
694 | ||
695 | /* Offset of first parameter from the argument pointer register value. | |
696 | This is 64 for the ins and locals, plus 4 for the struct-return reg | |
95dea81f JW |
697 | even if this function isn't going to use it. */ |
698 | #define FIRST_PARM_OFFSET(FNDECL) (STRUCT_VALUE_OFFSET + UNITS_PER_WORD) | |
1bb87f28 JW |
699 | |
700 | /* When a parameter is passed in a register, stack space is still | |
701 | allocated for it. */ | |
702 | #define REG_PARM_STACK_SPACE(DECL) (NPARM_REGS * UNITS_PER_WORD) | |
703 | ||
704 | /* Keep the stack pointer constant throughout the function. | |
b4ac57ab | 705 | This is both an optimization and a necessity: longjmp |
1bb87f28 JW |
706 | doesn't behave itself when the stack pointer moves within |
707 | the function! */ | |
708 | #define ACCUMULATE_OUTGOING_ARGS | |
709 | ||
710 | /* Value is the number of bytes of arguments automatically | |
711 | popped when returning from a subroutine call. | |
712 | FUNTYPE is the data type of the function (as a tree), | |
713 | or for a library call it is an identifier node for the subroutine name. | |
714 | SIZE is the number of bytes of arguments passed on the stack. */ | |
715 | ||
716 | #define RETURN_POPS_ARGS(FUNTYPE,SIZE) 0 | |
717 | ||
5b485d2c JW |
718 | /* Some subroutine macros specific to this machine. |
719 | When !TARGET_FPU, put float return values in the general registers, | |
720 | since we don't have any fp registers. */ | |
1bb87f28 | 721 | #define BASE_RETURN_VALUE_REG(MODE) \ |
26c5587d | 722 | (((MODE) == SFmode || (MODE) == DFmode) && TARGET_FPU ? 32 : 8) |
1bb87f28 | 723 | #define BASE_OUTGOING_VALUE_REG(MODE) \ |
5b485d2c JW |
724 | (((MODE) == SFmode || (MODE) == DFmode) && TARGET_FPU ? 32 \ |
725 | : (TARGET_FRW ? 8 : 24)) | |
1bb87f28 | 726 | #define BASE_PASSING_ARG_REG(MODE) (8) |
5b485d2c | 727 | #define BASE_INCOMING_ARG_REG(MODE) (TARGET_FRW ? 8 : 24) |
1bb87f28 | 728 | |
92ea370b TW |
729 | /* Define this macro if the target machine has "register windows". This |
730 | C expression returns the register number as seen by the called function | |
731 | corresponding to register number OUT as seen by the calling function. | |
732 | Return OUT if register number OUT is not an outbound register. */ | |
733 | ||
734 | #define INCOMING_REGNO(OUT) \ | |
735 | ((TARGET_FRW || (OUT) < 8 || (OUT) > 15) ? (OUT) : (OUT) + 16) | |
736 | ||
737 | /* Define this macro if the target machine has "register windows". This | |
738 | C expression returns the register number as seen by the calling function | |
739 | corresponding to register number IN as seen by the called function. | |
740 | Return IN if register number IN is not an inbound register. */ | |
741 | ||
742 | #define OUTGOING_REGNO(IN) \ | |
743 | ((TARGET_FRW || (IN) < 24 || (IN) > 31) ? (IN) : (IN) - 16) | |
744 | ||
1bb87f28 JW |
745 | /* Define how to find the value returned by a function. |
746 | VALTYPE is the data type of the value (as a tree). | |
747 | If the precise function being called is known, FUNC is its FUNCTION_DECL; | |
748 | otherwise, FUNC is 0. */ | |
749 | ||
750 | /* On SPARC the value is found in the first "output" register. */ | |
751 | ||
752 | #define FUNCTION_VALUE(VALTYPE, FUNC) \ | |
753 | gen_rtx (REG, TYPE_MODE (VALTYPE), BASE_RETURN_VALUE_REG (TYPE_MODE (VALTYPE))) | |
754 | ||
755 | /* But the called function leaves it in the first "input" register. */ | |
756 | ||
757 | #define FUNCTION_OUTGOING_VALUE(VALTYPE, FUNC) \ | |
758 | gen_rtx (REG, TYPE_MODE (VALTYPE), BASE_OUTGOING_VALUE_REG (TYPE_MODE (VALTYPE))) | |
759 | ||
760 | /* Define how to find the value returned by a library function | |
761 | assuming the value has mode MODE. */ | |
762 | ||
763 | #define LIBCALL_VALUE(MODE) \ | |
764 | gen_rtx (REG, MODE, BASE_RETURN_VALUE_REG (MODE)) | |
765 | ||
766 | /* 1 if N is a possible register number for a function value | |
767 | as seen by the caller. | |
768 | On SPARC, the first "output" reg is used for integer values, | |
769 | and the first floating point register is used for floating point values. */ | |
770 | ||
771 | #define FUNCTION_VALUE_REGNO_P(N) ((N) == 8 || (N) == 32) | |
772 | ||
773 | /* 1 if N is a possible register number for function argument passing. | |
774 | On SPARC, these are the "output" registers. */ | |
775 | ||
776 | #define FUNCTION_ARG_REGNO_P(N) ((N) < 14 && (N) > 7) | |
777 | \f | |
778 | /* Define a data type for recording info about an argument list | |
779 | during the scan of that argument list. This data type should | |
780 | hold all necessary information about the function itself | |
781 | and about the args processed so far, enough to enable macros | |
782 | such as FUNCTION_ARG to determine where the next arg should go. | |
783 | ||
784 | On SPARC, this is a single integer, which is a number of words | |
785 | of arguments scanned so far (including the invisible argument, | |
786 | if any, which holds the structure-value-address). | |
787 | Thus 7 or more means all following args should go on the stack. */ | |
788 | ||
789 | #define CUMULATIVE_ARGS int | |
790 | ||
791 | #define ROUND_ADVANCE(SIZE) \ | |
b1fc14e5 RS |
792 | ((SIZE + UNITS_PER_WORD - 1) / UNITS_PER_WORD) |
793 | ||
1bb87f28 JW |
794 | /* Initialize a variable CUM of type CUMULATIVE_ARGS |
795 | for a call to a function whose data type is FNTYPE. | |
796 | For a library call, FNTYPE is 0. | |
797 | ||
798 | On SPARC, the offset always starts at 0: the first parm reg is always | |
799 | the same reg. */ | |
800 | ||
801 | #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME) ((CUM) = 0) | |
802 | ||
803 | /* Update the data in CUM to advance over an argument | |
804 | of mode MODE and data type TYPE. | |
805 | (TYPE is null for libcalls where that information may not be available.) */ | |
806 | ||
807 | #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ | |
95dea81f JW |
808 | ((CUM) += ((MODE) != BLKmode \ |
809 | ? ROUND_ADVANCE (GET_MODE_SIZE (MODE)) \ | |
810 | : ROUND_ADVANCE (int_size_in_bytes (TYPE)))) | |
1bb87f28 JW |
811 | |
812 | /* Determine where to put an argument to a function. | |
813 | Value is zero to push the argument on the stack, | |
814 | or a hard register in which to store the argument. | |
815 | ||
816 | MODE is the argument's machine mode. | |
817 | TYPE is the data type of the argument (as a tree). | |
818 | This is null for libcalls where that information may | |
819 | not be available. | |
820 | CUM is a variable of type CUMULATIVE_ARGS which gives info about | |
821 | the preceding args and about the function being called. | |
822 | NAMED is nonzero if this argument is a named parameter | |
823 | (otherwise it is an extra parameter matching an ellipsis). */ | |
824 | ||
825 | /* On SPARC the first six args are normally in registers | |
826 | and the rest are pushed. Any arg that starts within the first 6 words | |
827 | is at least partially passed in a register unless its data type forbids. */ | |
828 | ||
829 | #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ | |
95dea81f | 830 | ((CUM) < NPARM_REGS \ |
1bb87f28 | 831 | && ((TYPE)==0 || ! TREE_ADDRESSABLE ((tree)(TYPE))) \ |
b1fc14e5 RS |
832 | && ((TYPE)==0 || (MODE) != BLKmode \ |
833 | || (TYPE_ALIGN ((TYPE)) % PARM_BOUNDARY == 0)) \ | |
95dea81f | 834 | ? gen_rtx (REG, (MODE), (BASE_PASSING_ARG_REG (MODE) + (CUM))) \ |
b1fc14e5 | 835 | : 0) |
1bb87f28 JW |
836 | |
837 | /* Define where a function finds its arguments. | |
838 | This is different from FUNCTION_ARG because of register windows. */ | |
839 | ||
840 | #define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED) \ | |
95dea81f | 841 | ((CUM) < NPARM_REGS \ |
1bb87f28 | 842 | && ((TYPE)==0 || ! TREE_ADDRESSABLE ((tree)(TYPE))) \ |
b1fc14e5 RS |
843 | && ((TYPE)==0 || (MODE) != BLKmode \ |
844 | || (TYPE_ALIGN ((TYPE)) % PARM_BOUNDARY == 0)) \ | |
95dea81f | 845 | ? gen_rtx (REG, (MODE), (BASE_INCOMING_ARG_REG (MODE) + (CUM))) \ |
b1fc14e5 | 846 | : 0) |
1bb87f28 JW |
847 | |
848 | /* For an arg passed partly in registers and partly in memory, | |
849 | this is the number of registers used. | |
850 | For args passed entirely in registers or entirely in memory, zero. | |
851 | Any arg that starts in the first 6 regs but won't entirely fit in them | |
852 | needs partial registers on the Sparc. */ | |
853 | ||
854 | #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \ | |
95dea81f | 855 | ((CUM) < NPARM_REGS \ |
1bb87f28 | 856 | && ((TYPE)==0 || ! TREE_ADDRESSABLE ((tree)(TYPE))) \ |
b1fc14e5 RS |
857 | && ((TYPE)==0 || (MODE) != BLKmode \ |
858 | || (TYPE_ALIGN ((TYPE)) % PARM_BOUNDARY == 0)) \ | |
95dea81f JW |
859 | && ((CUM) + ((MODE) == BLKmode \ |
860 | ? ROUND_ADVANCE (int_size_in_bytes (TYPE)) \ | |
861 | : ROUND_ADVANCE (GET_MODE_SIZE (MODE))) - NPARM_REGS > 0)\ | |
862 | ? (NPARM_REGS - (CUM)) \ | |
1bb87f28 JW |
863 | : 0) |
864 | ||
d9ca49d5 JW |
865 | /* The SPARC ABI stipulates passing struct arguments (of any size) and |
866 | quad-precision floats by invisible reference. */ | |
1bb87f28 | 867 | #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \ |
d9ca49d5 JW |
868 | ((TYPE && (TREE_CODE (TYPE) == RECORD_TYPE \ |
869 | || TREE_CODE (TYPE) == UNION_TYPE)) \ | |
870 | || (MODE == TFmode)) | |
1bb87f28 JW |
871 | |
872 | /* Define the information needed to generate branch and scc insns. This is | |
873 | stored from the compare operation. Note that we can't use "rtx" here | |
874 | since it hasn't been defined! */ | |
875 | ||
876 | extern struct rtx_def *sparc_compare_op0, *sparc_compare_op1; | |
877 | ||
878 | /* Define the function that build the compare insn for scc and bcc. */ | |
879 | ||
880 | extern struct rtx_def *gen_compare_reg (); | |
881 | \f | |
4b69d2a3 RS |
882 | /* Generate the special assembly code needed to tell the assembler whatever |
883 | it might need to know about the return value of a function. | |
884 | ||
885 | For Sparc assemblers, we need to output a .proc pseudo-op which conveys | |
886 | information to the assembler relating to peephole optimization (done in | |
887 | the assembler). */ | |
888 | ||
889 | #define ASM_DECLARE_RESULT(FILE, RESULT) \ | |
890 | fprintf ((FILE), "\t.proc\t0%o\n", sparc_type_code (TREE_TYPE (RESULT))) | |
891 | ||
1bb87f28 JW |
892 | /* Output the label for a function definition. */ |
893 | ||
4b69d2a3 RS |
894 | #define ASM_DECLARE_FUNCTION_NAME(FILE, NAME, DECL) \ |
895 | do { \ | |
896 | ASM_DECLARE_RESULT (FILE, DECL_RESULT (DECL)); \ | |
897 | ASM_OUTPUT_LABEL (FILE, NAME); \ | |
898 | } while (0) | |
1bb87f28 | 899 | |
1bb87f28 JW |
900 | /* This macro generates the assembly code for function entry. |
901 | FILE is a stdio stream to output the code to. | |
902 | SIZE is an int: how many units of temporary storage to allocate. | |
903 | Refer to the array `regs_ever_live' to determine which registers | |
904 | to save; `regs_ever_live[I]' is nonzero if register number I | |
905 | is ever used in the function. This macro is responsible for | |
906 | knowing which registers should not be saved even if used. */ | |
907 | ||
908 | /* On SPARC, move-double insns between fpu and cpu need an 8-byte block | |
909 | of memory. If any fpu reg is used in the function, we allocate | |
910 | such a block here, at the bottom of the frame, just in case it's needed. | |
911 | ||
912 | If this function is a leaf procedure, then we may choose not | |
913 | to do a "save" insn. The decision about whether or not | |
914 | to do this is made in regclass.c. */ | |
915 | ||
916 | #define FUNCTION_PROLOGUE(FILE, SIZE) \ | |
5b485d2c JW |
917 | (TARGET_FRW ? sparc_frw_output_function_prologue (FILE, SIZE, leaf_function)\ |
918 | : output_function_prologue (FILE, SIZE, leaf_function)) | |
1bb87f28 JW |
919 | |
920 | /* Output assembler code to FILE to increment profiler label # LABELNO | |
921 | for profiling a function entry. */ | |
922 | ||
d2a8e680 RS |
923 | #define FUNCTION_PROFILER(FILE, LABELNO) \ |
924 | do { \ | |
925 | fputs ("\tsethi %hi(", (FILE)); \ | |
926 | ASM_OUTPUT_INTERNAL_LABELREF (FILE, "LP", LABELNO); \ | |
927 | fputs ("),%o0\n\tcall mcount\n\tor %lo(", (FILE)); \ | |
928 | ASM_OUTPUT_INTERNAL_LABELREF (FILE, "LP", LABELNO); \ | |
929 | fputs ("),%o0,%o0\n", (FILE)); \ | |
930 | } while (0) | |
1bb87f28 JW |
931 | |
932 | /* Output assembler code to FILE to initialize this source file's | |
933 | basic block profiling info, if that has not already been done. */ | |
d2a8e680 RS |
934 | /* FIXME -- this does not parameterize how it generates labels (like the |
935 | above FUNCTION_PROFILER). Broken on Solaris-2. --gnu@cygnus.com */ | |
1bb87f28 JW |
936 | |
937 | #define FUNCTION_BLOCK_PROFILER(FILE, LABELNO) \ | |
938 | fprintf (FILE, "\tsethi %%hi(LPBX0),%%o0\n\tld [%%lo(LPBX0)+%%o0],%%o1\n\ttst %%o1\n\tbne LPY%d\n\tadd %%o0,%%lo(LPBX0),%%o0\n\tcall ___bb_init_func\n\tnop\nLPY%d:\n", \ | |
939 | (LABELNO), (LABELNO)) | |
940 | ||
941 | /* Output assembler code to FILE to increment the entry-count for | |
942 | the BLOCKNO'th basic block in this source file. */ | |
943 | ||
944 | #define BLOCK_PROFILER(FILE, BLOCKNO) \ | |
945 | { \ | |
946 | int blockn = (BLOCKNO); \ | |
947 | fprintf (FILE, "\tsethi %%hi(LPBX2+%d),%%g1\n\tld [%%lo(LPBX2+%d)+%%g1],%%g2\n\ | |
948 | \tadd %%g2,1,%%g2\n\tst %%g2,[%%lo(LPBX2+%d)+%%g1]\n", \ | |
949 | 4 * blockn, 4 * blockn, 4 * blockn); \ | |
950 | } | |
951 | ||
1bb87f28 JW |
952 | /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, |
953 | the stack pointer does not matter. The value is tested only in | |
954 | functions that have frame pointers. | |
955 | No definition is equivalent to always zero. */ | |
956 | ||
957 | extern int current_function_calls_alloca; | |
958 | extern int current_function_outgoing_args_size; | |
959 | ||
960 | #define EXIT_IGNORE_STACK \ | |
961 | (get_frame_size () != 0 \ | |
962 | || current_function_calls_alloca || current_function_outgoing_args_size) | |
963 | ||
964 | /* This macro generates the assembly code for function exit, | |
965 | on machines that need it. If FUNCTION_EPILOGUE is not defined | |
966 | then individual return instructions are generated for each | |
967 | return statement. Args are same as for FUNCTION_PROLOGUE. | |
968 | ||
969 | The function epilogue should not depend on the current stack pointer! | |
970 | It should use the frame pointer only. This is mandatory because | |
971 | of alloca; we also take advantage of it to omit stack adjustments | |
972 | before returning. */ | |
973 | ||
974 | /* This declaration is needed due to traditional/ANSI | |
975 | incompatibilities which cannot be #ifdefed away | |
976 | because they occur inside of macros. Sigh. */ | |
977 | extern union tree_node *current_function_decl; | |
978 | ||
979 | #define FUNCTION_EPILOGUE(FILE, SIZE) \ | |
5b485d2c JW |
980 | (TARGET_FRW ? sparc_frw_output_function_epilogue (FILE, SIZE, leaf_function)\ |
981 | : output_function_epilogue (FILE, SIZE, leaf_function)) | |
1bb87f28 | 982 | |
5b485d2c JW |
983 | #define DELAY_SLOTS_FOR_EPILOGUE \ |
984 | (TARGET_FRW ? sparc_frw_epilogue_delay_slots () : 1) | |
1bb87f28 | 985 | #define ELIGIBLE_FOR_EPILOGUE_DELAY(trial, slots_filled) \ |
5b485d2c JW |
986 | (TARGET_FRW ? sparc_frw_eligible_for_epilogue_delay (trial, slots_filled) \ |
987 | : eligible_for_epilogue_delay (trial, slots_filled)) | |
6a4bb1fa | 988 | \f |
1bb87f28 JW |
989 | /* Output assembler code for a block containing the constant parts |
990 | of a trampoline, leaving space for the variable parts. */ | |
991 | ||
992 | /* On the sparc, the trampoline contains five instructions: | |
993 | sethi #TOP_OF_FUNCTION,%g2 | |
994 | or #BOTTOM_OF_FUNCTION,%g2,%g2 | |
995 | sethi #TOP_OF_STATIC,%g1 | |
996 | jmp g2 | |
997 | or #BOTTOM_OF_STATIC,%g1,%g1 */ | |
998 | #define TRAMPOLINE_TEMPLATE(FILE) \ | |
999 | { \ | |
1000 | ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x00000000)); \ | |
1001 | ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x00000000)); \ | |
1002 | ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x00000000)); \ | |
1003 | ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x81C08000)); \ | |
1004 | ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x00000000)); \ | |
1005 | } | |
1006 | ||
1007 | /* Length in units of the trampoline for entering a nested function. */ | |
1008 | ||
1009 | #define TRAMPOLINE_SIZE 20 | |
1010 | ||
1011 | /* Emit RTL insns to initialize the variable parts of a trampoline. | |
1012 | FNADDR is an RTX for the address of the function's pure code. | |
1013 | CXT is an RTX for the static chain value for the function. | |
1014 | ||
1015 | This takes 16 insns: 2 shifts & 2 ands (to split up addresses), 4 sethi | |
1016 | (to load in opcodes), 4 iors (to merge address and opcodes), and 4 writes | |
1017 | (to store insns). This is a bit excessive. Perhaps a different | |
1018 | mechanism would be better here. */ | |
1019 | ||
1020 | #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ | |
1021 | { \ | |
1022 | rtx high_cxt = expand_shift (RSHIFT_EXPR, SImode, CXT, \ | |
1023 | size_int (10), 0, 1); \ | |
1024 | rtx high_fn = expand_shift (RSHIFT_EXPR, SImode, FNADDR, \ | |
1025 | size_int (10), 0, 1); \ | |
1026 | rtx low_cxt = expand_and (CXT, gen_rtx (CONST_INT, VOIDmode, 0x3ff), 0); \ | |
1027 | rtx low_fn = expand_and (FNADDR, gen_rtx (CONST_INT, VOIDmode, 0x3ff), 0); \ | |
1028 | rtx g1_sethi = gen_rtx (HIGH, SImode, \ | |
1029 | gen_rtx (CONST_INT, VOIDmode, 0x03000000)); \ | |
1030 | rtx g2_sethi = gen_rtx (HIGH, SImode, \ | |
1031 | gen_rtx (CONST_INT, VOIDmode, 0x05000000)); \ | |
1032 | rtx g1_ori = gen_rtx (HIGH, SImode, \ | |
1033 | gen_rtx (CONST_INT, VOIDmode, 0x82106000)); \ | |
1034 | rtx g2_ori = gen_rtx (HIGH, SImode, \ | |
1035 | gen_rtx (CONST_INT, VOIDmode, 0x8410A000)); \ | |
1036 | rtx tem = gen_reg_rtx (SImode); \ | |
1037 | emit_move_insn (tem, g2_sethi); \ | |
1038 | emit_insn (gen_iorsi3 (high_fn, high_fn, tem)); \ | |
1039 | emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 0)), high_fn);\ | |
1040 | emit_move_insn (tem, g2_ori); \ | |
1041 | emit_insn (gen_iorsi3 (low_fn, low_fn, tem)); \ | |
1042 | emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 4)), low_fn);\ | |
1043 | emit_move_insn (tem, g1_sethi); \ | |
1044 | emit_insn (gen_iorsi3 (high_cxt, high_cxt, tem)); \ | |
1045 | emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 8)), high_cxt);\ | |
1046 | emit_move_insn (tem, g1_ori); \ | |
1047 | emit_insn (gen_iorsi3 (low_cxt, low_cxt, tem)); \ | |
1048 | emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 16)), low_cxt);\ | |
1049 | } | |
6a4bb1fa | 1050 | \f |
9a1c7cd7 JW |
1051 | /* Generate necessary RTL for __builtin_saveregs(). |
1052 | ARGLIST is the argument list; see expr.c. */ | |
1053 | extern struct rtx_def *sparc_builtin_saveregs (); | |
1054 | #define EXPAND_BUILTIN_SAVEREGS(ARGLIST) sparc_builtin_saveregs (ARGLIST) | |
953fe179 JW |
1055 | |
1056 | /* Generate RTL to flush the register windows so as to make arbitrary frames | |
1057 | available. */ | |
1058 | #define SETUP_FRAME_ADDRESSES() \ | |
1059 | emit_insn (gen_flush_register_windows ()) | |
1060 | ||
1061 | /* Given an rtx for the address of a frame, | |
1062 | return an rtx for the address of the word in the frame | |
1063 | that holds the dynamic chain--the previous frame's address. */ | |
1064 | #define DYNAMIC_CHAIN_ADDRESS(frame) \ | |
1065 | gen_rtx (PLUS, Pmode, frame, gen_rtx (CONST_INT, VOIDmode, 56)) | |
1066 | ||
1067 | /* The return address isn't on the stack, it is in a register, so we can't | |
1068 | access it from the current frame pointer. We can access it from the | |
1069 | previous frame pointer though by reading a value from the register window | |
1070 | save area. */ | |
1071 | #define RETURN_ADDR_IN_PREVIOUS_FRAME | |
1072 | ||
1073 | /* The current return address is in %i7. The return address of anything | |
1074 | farther back is in the register window save area at [%fp+60]. */ | |
1075 | /* ??? This ignores the fact that the actual return address is +8 for normal | |
1076 | returns, and +12 for structure returns. */ | |
1077 | #define RETURN_ADDR_RTX(count, frame) \ | |
1078 | ((count == -1) \ | |
1079 | ? gen_rtx (REG, Pmode, 31) \ | |
1080 | : copy_to_reg (gen_rtx (MEM, Pmode, \ | |
1081 | memory_address (Pmode, plus_constant (frame, 60))))) | |
1bb87f28 JW |
1082 | \f |
1083 | /* Addressing modes, and classification of registers for them. */ | |
1084 | ||
1085 | /* #define HAVE_POST_INCREMENT */ | |
1086 | /* #define HAVE_POST_DECREMENT */ | |
1087 | ||
1088 | /* #define HAVE_PRE_DECREMENT */ | |
1089 | /* #define HAVE_PRE_INCREMENT */ | |
1090 | ||
1091 | /* Macros to check register numbers against specific register classes. */ | |
1092 | ||
1093 | /* These assume that REGNO is a hard or pseudo reg number. | |
1094 | They give nonzero only if REGNO is a hard reg of the suitable class | |
1095 | or a pseudo reg currently allocated to a suitable hard reg. | |
1096 | Since they use reg_renumber, they are safe only once reg_renumber | |
1097 | has been allocated, which happens in local-alloc.c. */ | |
1098 | ||
1099 | #define REGNO_OK_FOR_INDEX_P(REGNO) \ | |
1100 | (((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32) && (REGNO) != 0) | |
1101 | #define REGNO_OK_FOR_BASE_P(REGNO) \ | |
1102 | (((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32) && (REGNO) != 0) | |
1103 | #define REGNO_OK_FOR_FP_P(REGNO) \ | |
1104 | (((REGNO) ^ 0x20) < 32 \ | |
1105 | || (((REGNO) != 0) && (unsigned) (reg_renumber[REGNO] ^ 0x20) < 32)) | |
1106 | ||
1107 | /* Now macros that check whether X is a register and also, | |
1108 | strictly, whether it is in a specified class. | |
1109 | ||
1110 | These macros are specific to the SPARC, and may be used only | |
1111 | in code for printing assembler insns and in conditions for | |
1112 | define_optimization. */ | |
1113 | ||
1114 | /* 1 if X is an fp register. */ | |
1115 | ||
1116 | #define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X))) | |
1117 | \f | |
1118 | /* Maximum number of registers that can appear in a valid memory address. */ | |
1119 | ||
1120 | #define MAX_REGS_PER_ADDRESS 2 | |
1121 | ||
7aca9b9c JW |
1122 | /* Recognize any constant value that is a valid address. |
1123 | When PIC, we do not accept an address that would require a scratch reg | |
1124 | to load into a register. */ | |
1bb87f28 | 1125 | |
6eff269e BK |
1126 | #define CONSTANT_ADDRESS_P(X) \ |
1127 | (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \ | |
7aca9b9c JW |
1128 | || GET_CODE (X) == CONST_INT || GET_CODE (X) == HIGH \ |
1129 | || (GET_CODE (X) == CONST \ | |
1130 | && ! (flag_pic && pic_address_needs_scratch (X)))) | |
1131 | ||
1132 | /* Define this, so that when PIC, reload won't try to reload invalid | |
1133 | addresses which require two reload registers. */ | |
1134 | ||
1135 | #define LEGITIMATE_PIC_OPERAND_P(X) (! pic_address_needs_scratch (X)) | |
1bb87f28 JW |
1136 | |
1137 | /* Nonzero if the constant value X is a legitimate general operand. | |
1138 | Anything can be made to work except floating point constants. */ | |
1139 | ||
1140 | #define LEGITIMATE_CONSTANT_P(X) \ | |
1141 | (GET_CODE (X) != CONST_DOUBLE || GET_MODE (X) == VOIDmode) | |
1142 | ||
1143 | /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx | |
1144 | and check its validity for a certain class. | |
1145 | We have two alternate definitions for each of them. | |
1146 | The usual definition accepts all pseudo regs; the other rejects | |
1147 | them unless they have been allocated suitable hard regs. | |
1148 | The symbol REG_OK_STRICT causes the latter definition to be used. | |
1149 | ||
1150 | Most source files want to accept pseudo regs in the hope that | |
1151 | they will get allocated to the class that the insn wants them to be in. | |
1152 | Source files for reload pass need to be strict. | |
1153 | After reload, it makes no difference, since pseudo regs have | |
1154 | been eliminated by then. */ | |
1155 | ||
1156 | /* Optional extra constraints for this machine. Borrowed from romp.h. | |
1157 | ||
1158 | For the SPARC, `Q' means that this is a memory operand but not a | |
1159 | symbolic memory operand. Note that an unassigned pseudo register | |
1160 | is such a memory operand. Needed because reload will generate | |
1161 | these things in insns and then not re-recognize the insns, causing | |
1162 | constrain_operands to fail. | |
1163 | ||
1bb87f28 JW |
1164 | `S' handles constraints for calls. */ |
1165 | ||
1166 | #ifndef REG_OK_STRICT | |
1167 | ||
1168 | /* Nonzero if X is a hard reg that can be used as an index | |
1169 | or if it is a pseudo reg. */ | |
1170 | #define REG_OK_FOR_INDEX_P(X) (((unsigned) REGNO (X)) - 32 >= 32 && REGNO (X) != 0) | |
1171 | /* Nonzero if X is a hard reg that can be used as a base reg | |
1172 | or if it is a pseudo reg. */ | |
1173 | #define REG_OK_FOR_BASE_P(X) (((unsigned) REGNO (X)) - 32 >= 32 && REGNO (X) != 0) | |
1174 | ||
1175 | #define EXTRA_CONSTRAINT(OP, C) \ | |
db5e449c RS |
1176 | ((C) == 'Q' \ |
1177 | ? ((GET_CODE (OP) == MEM \ | |
1178 | && memory_address_p (GET_MODE (OP), XEXP (OP, 0)) \ | |
1179 | && ! symbolic_memory_operand (OP, VOIDmode)) \ | |
1180 | || (reload_in_progress && GET_CODE (OP) == REG \ | |
1181 | && REGNO (OP) >= FIRST_PSEUDO_REGISTER)) \ | |
19858600 JL |
1182 | : (C) == 'T' \ |
1183 | ? (mem_aligned_8 (OP)) \ | |
1184 | : (C) == 'U' \ | |
1185 | ? (register_ok_for_ldd (OP)) \ | |
db5e449c | 1186 | : 0) |
19858600 | 1187 | |
1bb87f28 JW |
1188 | #else |
1189 | ||
1190 | /* Nonzero if X is a hard reg that can be used as an index. */ | |
1191 | #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) | |
1192 | /* Nonzero if X is a hard reg that can be used as a base reg. */ | |
1193 | #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) | |
1194 | ||
1195 | #define EXTRA_CONSTRAINT(OP, C) \ | |
9ad2c692 JW |
1196 | ((C) == 'Q' \ |
1197 | ? (GET_CODE (OP) == REG \ | |
1198 | ? (REGNO (OP) >= FIRST_PSEUDO_REGISTER \ | |
1199 | && reg_renumber[REGNO (OP)] < 0) \ | |
1200 | : GET_CODE (OP) == MEM) \ | |
9ad2c692 | 1201 | : (C) == 'T' \ |
b165d471 | 1202 | ? mem_aligned_8 (OP) && strict_memory_address_p (Pmode, XEXP (OP, 0)) \ |
9ad2c692 | 1203 | : (C) == 'U' \ |
b165d471 JW |
1204 | ? (GET_CODE (OP) == REG \ |
1205 | && (REGNO (OP) < FIRST_PSEUDO_REGISTER \ | |
1206 | || reg_renumber[REGNO (OP)] > 0) \ | |
1207 | && register_ok_for_ldd (OP)) : 0) | |
1bb87f28 JW |
1208 | #endif |
1209 | \f | |
1210 | /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression | |
1211 | that is a valid memory address for an instruction. | |
1212 | The MODE argument is the machine mode for the MEM expression | |
1213 | that wants to use this address. | |
1214 | ||
1215 | On SPARC, the actual legitimate addresses must be REG+REG or REG+SMALLINT | |
1216 | ordinarily. This changes a bit when generating PIC. | |
1217 | ||
1218 | If you change this, execute "rm explow.o recog.o reload.o". */ | |
1219 | ||
bec2e359 JW |
1220 | #define RTX_OK_FOR_BASE_P(X) \ |
1221 | ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \ | |
1222 | || (GET_CODE (X) == SUBREG \ | |
1223 | && GET_CODE (SUBREG_REG (X)) == REG \ | |
1224 | && REG_OK_FOR_BASE_P (SUBREG_REG (X)))) | |
1225 | ||
1226 | #define RTX_OK_FOR_INDEX_P(X) \ | |
1227 | ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \ | |
1228 | || (GET_CODE (X) == SUBREG \ | |
1229 | && GET_CODE (SUBREG_REG (X)) == REG \ | |
1230 | && REG_OK_FOR_INDEX_P (SUBREG_REG (X)))) | |
1231 | ||
1232 | #define RTX_OK_FOR_OFFSET_P(X) \ | |
1233 | (GET_CODE (X) == CONST_INT && INTVAL (X) >= -0x1000 && INTVAL (X) < 0x1000) | |
1234 | ||
1bb87f28 | 1235 | #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ |
bec2e359 JW |
1236 | { if (RTX_OK_FOR_BASE_P (X)) \ |
1237 | goto ADDR; \ | |
1bb87f28 JW |
1238 | else if (GET_CODE (X) == PLUS) \ |
1239 | { \ | |
bec2e359 JW |
1240 | register rtx op0 = XEXP (X, 0); \ |
1241 | register rtx op1 = XEXP (X, 1); \ | |
1242 | if (flag_pic && op0 == pic_offset_table_rtx) \ | |
1bb87f28 | 1243 | { \ |
bec2e359 | 1244 | if (RTX_OK_FOR_BASE_P (op1)) \ |
1bb87f28 JW |
1245 | goto ADDR; \ |
1246 | else if (flag_pic == 1 \ | |
bec2e359 JW |
1247 | && GET_CODE (op1) != REG \ |
1248 | && GET_CODE (op1) != LO_SUM \ | |
7aca9b9c JW |
1249 | && GET_CODE (op1) != MEM \ |
1250 | && (GET_CODE (op1) != CONST_INT \ | |
1251 | || SMALL_INT (op1))) \ | |
1bb87f28 JW |
1252 | goto ADDR; \ |
1253 | } \ | |
bec2e359 | 1254 | else if (RTX_OK_FOR_BASE_P (op0)) \ |
1bb87f28 | 1255 | { \ |
bec2e359 JW |
1256 | if (RTX_OK_FOR_INDEX_P (op1) \ |
1257 | || RTX_OK_FOR_OFFSET_P (op1)) \ | |
1bb87f28 JW |
1258 | goto ADDR; \ |
1259 | } \ | |
bec2e359 | 1260 | else if (RTX_OK_FOR_BASE_P (op1)) \ |
1bb87f28 | 1261 | { \ |
bec2e359 JW |
1262 | if (RTX_OK_FOR_INDEX_P (op0) \ |
1263 | || RTX_OK_FOR_OFFSET_P (op0)) \ | |
1bb87f28 JW |
1264 | goto ADDR; \ |
1265 | } \ | |
1266 | } \ | |
bec2e359 JW |
1267 | else if (GET_CODE (X) == LO_SUM) \ |
1268 | { \ | |
1269 | register rtx op0 = XEXP (X, 0); \ | |
1270 | register rtx op1 = XEXP (X, 1); \ | |
1271 | if (RTX_OK_FOR_BASE_P (op0) \ | |
1272 | && CONSTANT_P (op1)) \ | |
1273 | goto ADDR; \ | |
1274 | } \ | |
1bb87f28 JW |
1275 | else if (GET_CODE (X) == CONST_INT && SMALL_INT (X)) \ |
1276 | goto ADDR; \ | |
1277 | } | |
1278 | \f | |
1279 | /* Try machine-dependent ways of modifying an illegitimate address | |
1280 | to be legitimate. If we find one, return the new, valid address. | |
1281 | This macro is used in only one place: `memory_address' in explow.c. | |
1282 | ||
1283 | OLDX is the address as it was before break_out_memory_refs was called. | |
1284 | In some cases it is useful to look at this to decide what needs to be done. | |
1285 | ||
1286 | MODE and WIN are passed so that this macro can use | |
1287 | GO_IF_LEGITIMATE_ADDRESS. | |
1288 | ||
1289 | It is always safe for this macro to do nothing. It exists to recognize | |
1290 | opportunities to optimize the output. */ | |
1291 | ||
1292 | /* On SPARC, change REG+N into REG+REG, and REG+(X*Y) into REG+REG. */ | |
1293 | extern struct rtx_def *legitimize_pic_address (); | |
1294 | #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \ | |
1295 | { rtx sparc_x = (X); \ | |
1296 | if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == MULT) \ | |
1297 | (X) = gen_rtx (PLUS, Pmode, XEXP (X, 1), \ | |
a015279e | 1298 | force_operand (XEXP (X, 0), NULL_RTX)); \ |
1bb87f28 JW |
1299 | if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 1)) == MULT) \ |
1300 | (X) = gen_rtx (PLUS, Pmode, XEXP (X, 0), \ | |
a015279e | 1301 | force_operand (XEXP (X, 1), NULL_RTX)); \ |
1bb87f28 | 1302 | if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == PLUS) \ |
a015279e | 1303 | (X) = gen_rtx (PLUS, Pmode, force_operand (XEXP (X, 0), NULL_RTX),\ |
1bb87f28 JW |
1304 | XEXP (X, 1)); \ |
1305 | if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 1)) == PLUS) \ | |
1306 | (X) = gen_rtx (PLUS, Pmode, XEXP (X, 0), \ | |
a015279e | 1307 | force_operand (XEXP (X, 1), NULL_RTX)); \ |
1bb87f28 JW |
1308 | if (sparc_x != (X) && memory_address_p (MODE, X)) \ |
1309 | goto WIN; \ | |
7aca9b9c | 1310 | if (flag_pic) (X) = legitimize_pic_address (X, MODE, 0); \ |
1bb87f28 JW |
1311 | else if (GET_CODE (X) == PLUS && CONSTANT_ADDRESS_P (XEXP (X, 1))) \ |
1312 | (X) = gen_rtx (PLUS, Pmode, XEXP (X, 0), \ | |
1313 | copy_to_mode_reg (Pmode, XEXP (X, 1))); \ | |
1314 | else if (GET_CODE (X) == PLUS && CONSTANT_ADDRESS_P (XEXP (X, 0))) \ | |
1315 | (X) = gen_rtx (PLUS, Pmode, XEXP (X, 1), \ | |
1316 | copy_to_mode_reg (Pmode, XEXP (X, 0))); \ | |
1317 | else if (GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == CONST \ | |
1318 | || GET_CODE (X) == LABEL_REF) \ | |
1319 | (X) = gen_rtx (LO_SUM, Pmode, \ | |
1320 | copy_to_mode_reg (Pmode, gen_rtx (HIGH, Pmode, X)), X); \ | |
1321 | if (memory_address_p (MODE, X)) \ | |
1322 | goto WIN; } | |
1323 | ||
1324 | /* Go to LABEL if ADDR (a legitimate address expression) | |
1325 | has an effect that depends on the machine mode it is used for. | |
1326 | On the SPARC this is never true. */ | |
1327 | ||
1328 | #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) | |
1329 | \f | |
1330 | /* Specify the machine mode that this machine uses | |
1331 | for the index in the tablejump instruction. */ | |
1332 | #define CASE_VECTOR_MODE SImode | |
1333 | ||
1334 | /* Define this if the tablejump instruction expects the table | |
1335 | to contain offsets from the address of the table. | |
1336 | Do not define this if the table should contain absolute addresses. */ | |
1337 | /* #define CASE_VECTOR_PC_RELATIVE */ | |
1338 | ||
1339 | /* Specify the tree operation to be used to convert reals to integers. */ | |
1340 | #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR | |
1341 | ||
1342 | /* This is the kind of divide that is easiest to do in the general case. */ | |
1343 | #define EASY_DIV_EXPR TRUNC_DIV_EXPR | |
1344 | ||
1345 | /* Define this as 1 if `char' should by default be signed; else as 0. */ | |
1346 | #define DEFAULT_SIGNED_CHAR 1 | |
1347 | ||
1348 | /* Max number of bytes we can move from memory to memory | |
1349 | in one reasonably fast instruction. */ | |
2eef2ef1 | 1350 | #define MOVE_MAX 8 |
1bb87f28 | 1351 | |
0fb5a69e | 1352 | #if 0 /* Sun 4 has matherr, so this is no good. */ |
24e2a2bf RS |
1353 | /* This is the value of the error code EDOM for this machine, |
1354 | used by the sqrt instruction. */ | |
1355 | #define TARGET_EDOM 33 | |
1356 | ||
1357 | /* This is how to refer to the variable errno. */ | |
1358 | #define GEN_ERRNO_RTX \ | |
1359 | gen_rtx (MEM, SImode, gen_rtx (SYMBOL_REF, Pmode, "errno")) | |
0fb5a69e | 1360 | #endif /* 0 */ |
24e2a2bf | 1361 | |
9a63901f RK |
1362 | /* Define if operations between registers always perform the operation |
1363 | on the full register even if a narrower mode is specified. */ | |
1364 | #define WORD_REGISTER_OPERATIONS | |
1365 | ||
1366 | /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD | |
1367 | will either zero-extend or sign-extend. The value of this macro should | |
1368 | be the code that says which one of the two operations is implicitly | |
1369 | done, NIL if none. */ | |
1370 | #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND | |
1bb87f28 JW |
1371 | |
1372 | /* Nonzero if access to memory by bytes is slow and undesirable. | |
1373 | For RISC chips, it means that access to memory by bytes is no | |
1374 | better than access by words when possible, so grab a whole word | |
1375 | and maybe make use of that. */ | |
1376 | #define SLOW_BYTE_ACCESS 1 | |
1377 | ||
1378 | /* We assume that the store-condition-codes instructions store 0 for false | |
1379 | and some other value for true. This is the value stored for true. */ | |
1380 | ||
1381 | #define STORE_FLAG_VALUE 1 | |
1382 | ||
1383 | /* When a prototype says `char' or `short', really pass an `int'. */ | |
1384 | #define PROMOTE_PROTOTYPES | |
1385 | ||
1386 | /* Define if shifts truncate the shift count | |
1387 | which implies one can omit a sign-extension or zero-extension | |
1388 | of a shift count. */ | |
1389 | #define SHIFT_COUNT_TRUNCATED | |
1390 | ||
1391 | /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits | |
1392 | is done just by pretending it is already truncated. */ | |
1393 | #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 | |
1394 | ||
1395 | /* Specify the machine mode that pointers have. | |
1396 | After generation of rtl, the compiler makes no further distinction | |
1397 | between pointers and any other objects of this machine mode. */ | |
1398 | #define Pmode SImode | |
1399 | ||
b4ac57ab RS |
1400 | /* Generate calls to memcpy, memcmp and memset. */ |
1401 | #define TARGET_MEM_FUNCTIONS | |
1402 | ||
1bb87f28 JW |
1403 | /* Add any extra modes needed to represent the condition code. |
1404 | ||
1405 | On the Sparc, we have a "no-overflow" mode which is used when an add or | |
1406 | subtract insn is used to set the condition code. Different branches are | |
1407 | used in this case for some operations. | |
1408 | ||
4d449554 JW |
1409 | We also have two modes to indicate that the relevant condition code is |
1410 | in the floating-point condition code register. One for comparisons which | |
1411 | will generate an exception if the result is unordered (CCFPEmode) and | |
1412 | one for comparisons which will never trap (CCFPmode). This really should | |
1413 | be a separate register, but we don't want to go to 65 registers. */ | |
1414 | #define EXTRA_CC_MODES CC_NOOVmode, CCFPmode, CCFPEmode | |
1bb87f28 JW |
1415 | |
1416 | /* Define the names for the modes specified above. */ | |
4d449554 | 1417 | #define EXTRA_CC_NAMES "CC_NOOV", "CCFP", "CCFPE" |
1bb87f28 JW |
1418 | |
1419 | /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, | |
4d449554 JW |
1420 | return the mode to be used for the comparison. For floating-point, |
1421 | CCFP[E]mode is used. CC_NOOVmode should be used when the first operand is a | |
922bd191 JW |
1422 | PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special |
1423 | processing is needed. */ | |
679655e6 | 1424 | #define SELECT_CC_MODE(OP,X,Y) \ |
4d449554 | 1425 | (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \ |
922bd191 JW |
1426 | ? ((OP == EQ || OP == NE) ? CCFPmode : CCFPEmode) \ |
1427 | : ((GET_CODE (X) == PLUS || GET_CODE (X) == MINUS \ | |
1428 | || GET_CODE (X) == NEG || GET_CODE (X) == ASHIFT) \ | |
4d449554 | 1429 | ? CC_NOOVmode : CCmode)) |
1bb87f28 JW |
1430 | |
1431 | /* A function address in a call instruction | |
1432 | is a byte address (for indexing purposes) | |
1433 | so give the MEM rtx a byte's mode. */ | |
1434 | #define FUNCTION_MODE SImode | |
1435 | ||
1436 | /* Define this if addresses of constant functions | |
1437 | shouldn't be put through pseudo regs where they can be cse'd. | |
1438 | Desirable on machines where ordinary constants are expensive | |
1439 | but a CALL with constant address is cheap. */ | |
1440 | #define NO_FUNCTION_CSE | |
1441 | ||
1442 | /* alloca should avoid clobbering the old register save area. */ | |
1443 | #define SETJMP_VIA_SAVE_AREA | |
1444 | ||
1445 | /* Define subroutines to call to handle multiply and divide. | |
1446 | Use the subroutines that Sun's library provides. | |
1447 | The `*' prevents an underscore from being prepended by the compiler. */ | |
1448 | ||
1449 | #define DIVSI3_LIBCALL "*.div" | |
1450 | #define UDIVSI3_LIBCALL "*.udiv" | |
1451 | #define MODSI3_LIBCALL "*.rem" | |
1452 | #define UMODSI3_LIBCALL "*.urem" | |
1453 | /* .umul is a little faster than .mul. */ | |
1454 | #define MULSI3_LIBCALL "*.umul" | |
1455 | ||
1456 | /* Compute the cost of computing a constant rtl expression RTX | |
1457 | whose rtx-code is CODE. The body of this macro is a portion | |
1458 | of a switch statement. If the code is computed here, | |
1459 | return it with a return statement. Otherwise, break from the switch. */ | |
1460 | ||
3bb22aee | 1461 | #define CONST_COSTS(RTX,CODE,OUTER_CODE) \ |
1bb87f28 | 1462 | case CONST_INT: \ |
1bb87f28 | 1463 | if (INTVAL (RTX) < 0x1000 && INTVAL (RTX) >= -0x1000) \ |
5b485d2c | 1464 | return 0; \ |
1bb87f28 JW |
1465 | case HIGH: \ |
1466 | return 2; \ | |
1467 | case CONST: \ | |
1468 | case LABEL_REF: \ | |
1469 | case SYMBOL_REF: \ | |
1470 | return 4; \ | |
1471 | case CONST_DOUBLE: \ | |
1472 | if (GET_MODE (RTX) == DImode) \ | |
1473 | if ((XINT (RTX, 3) == 0 \ | |
1474 | && (unsigned) XINT (RTX, 2) < 0x1000) \ | |
1475 | || (XINT (RTX, 3) == -1 \ | |
1476 | && XINT (RTX, 2) < 0 \ | |
1477 | && XINT (RTX, 2) >= -0x1000)) \ | |
5b485d2c | 1478 | return 0; \ |
1bb87f28 JW |
1479 | return 8; |
1480 | ||
1481 | /* SPARC offers addressing modes which are "as cheap as a register". | |
1482 | See sparc.c (or gcc.texinfo) for details. */ | |
1483 | ||
1484 | #define ADDRESS_COST(RTX) \ | |
1485 | (GET_CODE (RTX) == REG ? 1 : sparc_address_cost (RTX)) | |
1486 | ||
1487 | /* Compute extra cost of moving data between one register class | |
1488 | and another. */ | |
1489 | #define REGISTER_MOVE_COST(CLASS1, CLASS2) \ | |
1490 | (((CLASS1 == FP_REGS && CLASS2 == GENERAL_REGS) \ | |
1491 | || (CLASS1 == GENERAL_REGS && CLASS2 == FP_REGS)) ? 6 : 2) | |
1492 | ||
1493 | /* Provide the costs of a rtl expression. This is in the body of a | |
1494 | switch on CODE. The purpose for the cost of MULT is to encourage | |
1495 | `synth_mult' to find a synthetic multiply when reasonable. | |
1496 | ||
1497 | If we need more than 12 insns to do a multiply, then go out-of-line, | |
1498 | since the call overhead will be < 10% of the cost of the multiply. */ | |
1499 | ||
3bb22aee | 1500 | #define RTX_COSTS(X,CODE,OUTER_CODE) \ |
1bb87f28 | 1501 | case MULT: \ |
6ffeae97 | 1502 | return TARGET_V8 ? COSTS_N_INSNS (5) : COSTS_N_INSNS (25); \ |
1bb87f28 JW |
1503 | case DIV: \ |
1504 | case UDIV: \ | |
1505 | case MOD: \ | |
1506 | case UMOD: \ | |
5b485d2c JW |
1507 | return COSTS_N_INSNS (25); \ |
1508 | /* Make FLOAT and FIX more expensive than CONST_DOUBLE,\ | |
1bb87f28 JW |
1509 | so that cse will favor the latter. */ \ |
1510 | case FLOAT: \ | |
5b485d2c | 1511 | case FIX: \ |
1bb87f28 JW |
1512 | return 19; |
1513 | ||
1514 | /* Conditional branches with empty delay slots have a length of two. */ | |
1515 | #define ADJUST_INSN_LENGTH(INSN, LENGTH) \ | |
1516 | if (GET_CODE (INSN) == CALL_INSN \ | |
1517 | || (GET_CODE (INSN) == JUMP_INSN && ! simplejump_p (insn))) \ | |
1518 | LENGTH += 1; | |
1519 | \f | |
1520 | /* Control the assembler format that we output. */ | |
1521 | ||
1522 | /* Output at beginning of assembler file. */ | |
1523 | ||
1524 | #define ASM_FILE_START(file) | |
1525 | ||
1526 | /* Output to assembler file text saying following lines | |
1527 | may contain character constants, extra white space, comments, etc. */ | |
1528 | ||
1529 | #define ASM_APP_ON "" | |
1530 | ||
1531 | /* Output to assembler file text saying following lines | |
1532 | no longer contain unusual constructs. */ | |
1533 | ||
1534 | #define ASM_APP_OFF "" | |
1535 | ||
303d524a JW |
1536 | #define ASM_LONG ".word" |
1537 | #define ASM_SHORT ".half" | |
1538 | #define ASM_BYTE_OP ".byte" | |
1539 | ||
1bb87f28 JW |
1540 | /* Output before read-only data. */ |
1541 | ||
1542 | #define TEXT_SECTION_ASM_OP ".text" | |
1543 | ||
1544 | /* Output before writable data. */ | |
1545 | ||
1546 | #define DATA_SECTION_ASM_OP ".data" | |
1547 | ||
1548 | /* How to refer to registers in assembler output. | |
1549 | This sequence is indexed by compiler's hard-register-number (see above). */ | |
1550 | ||
1551 | #define REGISTER_NAMES \ | |
1552 | {"%g0", "%g1", "%g2", "%g3", "%g4", "%g5", "%g6", "%g7", \ | |
1553 | "%o0", "%o1", "%o2", "%o3", "%o4", "%o5", "%sp", "%o7", \ | |
1554 | "%l0", "%l1", "%l2", "%l3", "%l4", "%l5", "%l6", "%l7", \ | |
1555 | "%i0", "%i1", "%i2", "%i3", "%i4", "%i5", "%fp", "%i7", \ | |
1556 | "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7", \ | |
1557 | "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15", \ | |
1558 | "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23", \ | |
1559 | "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31"} | |
1560 | ||
ea3fa5f7 JW |
1561 | /* Define additional names for use in asm clobbers and asm declarations. |
1562 | ||
1563 | We define the fake Condition Code register as an alias for reg 0 (which | |
1564 | is our `condition code' register), so that condition codes can easily | |
1565 | be clobbered by an asm. No such register actually exists. Condition | |
1566 | codes are partly stored in the PSR and partly in the FSR. */ | |
1567 | ||
0eb9f40e | 1568 | #define ADDITIONAL_REGISTER_NAMES {"ccr", 0, "cc", 0} |
ea3fa5f7 | 1569 | |
1bb87f28 JW |
1570 | /* How to renumber registers for dbx and gdb. */ |
1571 | ||
1572 | #define DBX_REGISTER_NUMBER(REGNO) (REGNO) | |
1573 | ||
1574 | /* On Sun 4, this limit is 2048. We use 1500 to be safe, | |
1575 | since the length can run past this up to a continuation point. */ | |
1576 | #define DBX_CONTIN_LENGTH 1500 | |
1577 | ||
1578 | /* This is how to output a note to DBX telling it the line number | |
1579 | to which the following sequence of instructions corresponds. | |
1580 | ||
1581 | This is needed for SunOS 4.0, and should not hurt for 3.2 | |
1582 | versions either. */ | |
1583 | #define ASM_OUTPUT_SOURCE_LINE(file, line) \ | |
1584 | { static int sym_lineno = 1; \ | |
1585 | fprintf (file, ".stabn 68,0,%d,LM%d\nLM%d:\n", \ | |
1586 | line, sym_lineno, sym_lineno); \ | |
1587 | sym_lineno += 1; } | |
1588 | ||
1589 | /* This is how to output the definition of a user-level label named NAME, | |
1590 | such as the label on a static function or variable NAME. */ | |
1591 | ||
1592 | #define ASM_OUTPUT_LABEL(FILE,NAME) \ | |
1593 | do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0) | |
1594 | ||
1595 | /* This is how to output a command to make the user-level label named NAME | |
1596 | defined for reference from other files. */ | |
1597 | ||
1598 | #define ASM_GLOBALIZE_LABEL(FILE,NAME) \ | |
1599 | do { fputs ("\t.global ", FILE); assemble_name (FILE, NAME); fputs ("\n", FILE);} while (0) | |
1600 | ||
1601 | /* This is how to output a reference to a user-level label named NAME. | |
1602 | `assemble_name' uses this. */ | |
1603 | ||
1604 | #define ASM_OUTPUT_LABELREF(FILE,NAME) \ | |
1605 | fprintf (FILE, "_%s", NAME) | |
1606 | ||
d2a8e680 | 1607 | /* This is how to output a definition of an internal numbered label where |
1bb87f28 JW |
1608 | PREFIX is the class of label and NUM is the number within the class. */ |
1609 | ||
1610 | #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \ | |
1611 | fprintf (FILE, "%s%d:\n", PREFIX, NUM) | |
1612 | ||
d2a8e680 RS |
1613 | /* This is how to output a reference to an internal numbered label where |
1614 | PREFIX is the class of label and NUM is the number within the class. */ | |
1615 | /* FIXME: This should be used throughout gcc, and documented in the texinfo | |
1616 | files. There is no reason you should have to allocate a buffer and | |
1617 | `sprintf' to reference an internal label (as opposed to defining it). */ | |
1618 | ||
1619 | #define ASM_OUTPUT_INTERNAL_LABELREF(FILE,PREFIX,NUM) \ | |
1620 | fprintf (FILE, "%s%d", PREFIX, NUM) | |
1621 | ||
1bb87f28 JW |
1622 | /* This is how to store into the string LABEL |
1623 | the symbol_ref name of an internal numbered label where | |
1624 | PREFIX is the class of label and NUM is the number within the class. | |
1625 | This is suitable for output with `assemble_name'. */ | |
1626 | ||
1627 | #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \ | |
1628 | sprintf (LABEL, "*%s%d", PREFIX, NUM) | |
1629 | ||
1630 | /* This is how to output an assembler line defining a `double' constant. */ | |
1631 | ||
1632 | #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \ | |
1633 | { \ | |
2e7ac77c JW |
1634 | long t[2]; \ |
1635 | REAL_VALUE_TO_TARGET_DOUBLE ((VALUE), t); \ | |
1636 | fprintf (FILE, "\t%s\t0x%lx\n\t%s\t0x%lx\n", \ | |
1637 | ASM_LONG, t[0], ASM_LONG, t[1]); \ | |
1bb87f28 JW |
1638 | } |
1639 | ||
1640 | /* This is how to output an assembler line defining a `float' constant. */ | |
1641 | ||
1642 | #define ASM_OUTPUT_FLOAT(FILE,VALUE) \ | |
1643 | { \ | |
2e7ac77c JW |
1644 | long t; \ |
1645 | REAL_VALUE_TO_TARGET_SINGLE ((VALUE), t); \ | |
1646 | fprintf (FILE, "\t%s\t0x%lx\n", ASM_LONG, t); \ | |
1647 | } \ | |
1bb87f28 | 1648 | |
0cd02cbb DE |
1649 | /* This is how to output an assembler line defining a `long double' |
1650 | constant. */ | |
1651 | ||
1652 | #define ASM_OUTPUT_LONG_DOUBLE(FILE,VALUE) \ | |
1653 | { \ | |
1654 | long t[4]; \ | |
1655 | REAL_VALUE_TO_TARGET_LONG_DOUBLE ((VALUE), t); \ | |
1656 | fprintf (FILE, "\t%s\t0x%lx\n\t%s\t0x%lx\n\t%s\t0x%lx\n\t%s\t0x%lx\n", \ | |
1657 | ASM_LONG, t[0], ASM_LONG, t[1], ASM_LONG, t[2], ASM_LONG, t[3]); \ | |
1658 | } | |
1659 | ||
1bb87f28 JW |
1660 | /* This is how to output an assembler line defining an `int' constant. */ |
1661 | ||
1662 | #define ASM_OUTPUT_INT(FILE,VALUE) \ | |
303d524a | 1663 | ( fprintf (FILE, "\t%s\t", ASM_LONG), \ |
1bb87f28 JW |
1664 | output_addr_const (FILE, (VALUE)), \ |
1665 | fprintf (FILE, "\n")) | |
1666 | ||
1667 | /* This is how to output an assembler line defining a DImode constant. */ | |
1668 | #define ASM_OUTPUT_DOUBLE_INT(FILE,VALUE) \ | |
1669 | output_double_int (FILE, VALUE) | |
1670 | ||
1671 | /* Likewise for `char' and `short' constants. */ | |
1672 | ||
1673 | #define ASM_OUTPUT_SHORT(FILE,VALUE) \ | |
303d524a | 1674 | ( fprintf (FILE, "\t%s\t", ASM_SHORT), \ |
1bb87f28 JW |
1675 | output_addr_const (FILE, (VALUE)), \ |
1676 | fprintf (FILE, "\n")) | |
1677 | ||
1678 | #define ASM_OUTPUT_CHAR(FILE,VALUE) \ | |
303d524a | 1679 | ( fprintf (FILE, "\t%s\t", ASM_BYTE_OP), \ |
1bb87f28 JW |
1680 | output_addr_const (FILE, (VALUE)), \ |
1681 | fprintf (FILE, "\n")) | |
1682 | ||
1683 | /* This is how to output an assembler line for a numeric constant byte. */ | |
1684 | ||
1685 | #define ASM_OUTPUT_BYTE(FILE,VALUE) \ | |
303d524a | 1686 | fprintf (FILE, "\t%s\t0x%x\n", ASM_BYTE_OP, (VALUE)) |
1bb87f28 JW |
1687 | |
1688 | /* This is how to output an element of a case-vector that is absolute. */ | |
1689 | ||
1690 | #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ | |
4b69d2a3 RS |
1691 | do { \ |
1692 | char label[30]; \ | |
1693 | ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \ | |
1694 | fprintf (FILE, "\t.word\t"); \ | |
1695 | assemble_name (FILE, label); \ | |
1696 | fprintf (FILE, "\n"); \ | |
1697 | } while (0) | |
1bb87f28 JW |
1698 | |
1699 | /* This is how to output an element of a case-vector that is relative. | |
1700 | (SPARC uses such vectors only when generating PIC.) */ | |
1701 | ||
4b69d2a3 RS |
1702 | #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) \ |
1703 | do { \ | |
1704 | char label[30]; \ | |
1705 | ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \ | |
1706 | fprintf (FILE, "\t.word\t"); \ | |
1707 | assemble_name (FILE, label); \ | |
1708 | fprintf (FILE, "-1b\n"); \ | |
1709 | } while (0) | |
1bb87f28 JW |
1710 | |
1711 | /* This is how to output an assembler line | |
1712 | that says to advance the location counter | |
1713 | to a multiple of 2**LOG bytes. */ | |
1714 | ||
1715 | #define ASM_OUTPUT_ALIGN(FILE,LOG) \ | |
1716 | if ((LOG) != 0) \ | |
1717 | fprintf (FILE, "\t.align %d\n", (1<<(LOG))) | |
1718 | ||
1719 | #define ASM_OUTPUT_SKIP(FILE,SIZE) \ | |
1720 | fprintf (FILE, "\t.skip %u\n", (SIZE)) | |
1721 | ||
1722 | /* This says how to output an assembler line | |
1723 | to define a global common symbol. */ | |
1724 | ||
1725 | #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \ | |
1726 | ( fputs ("\t.global ", (FILE)), \ | |
1727 | assemble_name ((FILE), (NAME)), \ | |
1728 | fputs ("\n\t.common ", (FILE)), \ | |
1729 | assemble_name ((FILE), (NAME)), \ | |
1730 | fprintf ((FILE), ",%u,\"bss\"\n", (ROUNDED))) | |
1731 | ||
1732 | /* This says how to output an assembler line | |
1733 | to define a local common symbol. */ | |
1734 | ||
1735 | #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \ | |
1736 | ( fputs ("\n\t.reserve ", (FILE)), \ | |
1737 | assemble_name ((FILE), (NAME)), \ | |
1738 | fprintf ((FILE), ",%u,\"bss\"\n", (ROUNDED))) | |
1739 | ||
1740 | /* Store in OUTPUT a string (made with alloca) containing | |
1741 | an assembler-name for a local static variable named NAME. | |
1742 | LABELNO is an integer which is different for each call. */ | |
1743 | ||
1744 | #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \ | |
1745 | ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \ | |
1746 | sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO))) | |
1747 | ||
c14f2655 RS |
1748 | #define IDENT_ASM_OP ".ident" |
1749 | ||
1750 | /* Output #ident as a .ident. */ | |
1751 | ||
1752 | #define ASM_OUTPUT_IDENT(FILE, NAME) \ | |
1753 | fprintf (FILE, "\t%s\t\"%s\"\n", IDENT_ASM_OP, NAME); | |
1754 | ||
1bb87f28 JW |
1755 | /* Define the parentheses used to group arithmetic operations |
1756 | in assembler code. */ | |
1757 | ||
1758 | #define ASM_OPEN_PAREN "(" | |
1759 | #define ASM_CLOSE_PAREN ")" | |
1760 | ||
1761 | /* Define results of standard character escape sequences. */ | |
1762 | #define TARGET_BELL 007 | |
1763 | #define TARGET_BS 010 | |
1764 | #define TARGET_TAB 011 | |
1765 | #define TARGET_NEWLINE 012 | |
1766 | #define TARGET_VT 013 | |
1767 | #define TARGET_FF 014 | |
1768 | #define TARGET_CR 015 | |
1769 | ||
1770 | #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \ | |
2ccdef65 | 1771 | ((CHAR) == '#' || (CHAR) == '*' || (CHAR) == '^' || (CHAR) == '(') |
1bb87f28 JW |
1772 | |
1773 | /* Print operand X (an rtx) in assembler syntax to file FILE. | |
1774 | CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. | |
1775 | For `%' followed by punctuation, CODE is the punctuation and X is null. */ | |
1776 | ||
1777 | #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE) | |
1778 | ||
1779 | /* Print a memory address as an operand to reference that memory location. */ | |
1780 | ||
1781 | #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \ | |
1782 | { register rtx base, index = 0; \ | |
1783 | int offset = 0; \ | |
1784 | register rtx addr = ADDR; \ | |
1785 | if (GET_CODE (addr) == REG) \ | |
1786 | fputs (reg_names[REGNO (addr)], FILE); \ | |
1787 | else if (GET_CODE (addr) == PLUS) \ | |
1788 | { \ | |
1789 | if (GET_CODE (XEXP (addr, 0)) == CONST_INT) \ | |
1790 | offset = INTVAL (XEXP (addr, 0)), base = XEXP (addr, 1);\ | |
1791 | else if (GET_CODE (XEXP (addr, 1)) == CONST_INT) \ | |
1792 | offset = INTVAL (XEXP (addr, 1)), base = XEXP (addr, 0);\ | |
1793 | else \ | |
1794 | base = XEXP (addr, 0), index = XEXP (addr, 1); \ | |
1795 | fputs (reg_names[REGNO (base)], FILE); \ | |
1796 | if (index == 0) \ | |
1797 | fprintf (FILE, "%+d", offset); \ | |
1798 | else if (GET_CODE (index) == REG) \ | |
1799 | fprintf (FILE, "+%s", reg_names[REGNO (index)]); \ | |
1800 | else if (GET_CODE (index) == SYMBOL_REF) \ | |
1801 | fputc ('+', FILE), output_addr_const (FILE, index); \ | |
1802 | else abort (); \ | |
1803 | } \ | |
1804 | else if (GET_CODE (addr) == MINUS \ | |
1805 | && GET_CODE (XEXP (addr, 1)) == LABEL_REF) \ | |
1806 | { \ | |
1807 | output_addr_const (FILE, XEXP (addr, 0)); \ | |
1808 | fputs ("-(", FILE); \ | |
1809 | output_addr_const (FILE, XEXP (addr, 1)); \ | |
1810 | fputs ("-.)", FILE); \ | |
1811 | } \ | |
1812 | else if (GET_CODE (addr) == LO_SUM) \ | |
1813 | { \ | |
1814 | output_operand (XEXP (addr, 0), 0); \ | |
1815 | fputs ("+%lo(", FILE); \ | |
1816 | output_address (XEXP (addr, 1)); \ | |
1817 | fputc (')', FILE); \ | |
1818 | } \ | |
1819 | else if (flag_pic && GET_CODE (addr) == CONST \ | |
1820 | && GET_CODE (XEXP (addr, 0)) == MINUS \ | |
1821 | && GET_CODE (XEXP (XEXP (addr, 0), 1)) == CONST \ | |
1822 | && GET_CODE (XEXP (XEXP (XEXP (addr, 0), 1), 0)) == MINUS \ | |
1823 | && XEXP (XEXP (XEXP (XEXP (addr, 0), 1), 0), 1) == pc_rtx) \ | |
1824 | { \ | |
1825 | addr = XEXP (addr, 0); \ | |
1826 | output_addr_const (FILE, XEXP (addr, 0)); \ | |
1827 | /* Group the args of the second CONST in parenthesis. */ \ | |
1828 | fputs ("-(", FILE); \ | |
1829 | /* Skip past the second CONST--it does nothing for us. */\ | |
1830 | output_addr_const (FILE, XEXP (XEXP (addr, 1), 0)); \ | |
1831 | /* Close the parenthesis. */ \ | |
1832 | fputc (')', FILE); \ | |
1833 | } \ | |
1834 | else \ | |
1835 | { \ | |
1836 | output_addr_const (FILE, addr); \ | |
1837 | } \ | |
1838 | } | |
1839 | ||
1840 | /* Declare functions defined in sparc.c and used in templates. */ | |
1841 | ||
1842 | extern char *singlemove_string (); | |
1843 | extern char *output_move_double (); | |
795068a4 | 1844 | extern char *output_move_quad (); |
1bb87f28 | 1845 | extern char *output_fp_move_double (); |
795068a4 | 1846 | extern char *output_fp_move_quad (); |
1bb87f28 JW |
1847 | extern char *output_block_move (); |
1848 | extern char *output_scc_insn (); | |
1849 | extern char *output_cbranch (); | |
1850 | extern char *output_return (); | |
1bb87f28 JW |
1851 | |
1852 | /* Defined in flags.h, but insn-emit.c does not include flags.h. */ | |
1853 | ||
1854 | extern int flag_pic; |