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1bb87f28 JW |
1 | /* Definitions of target machine for GNU compiler, for Sun SPARC. |
2 | Copyright (C) 1987, 1988, 1989, 1992 Free Software Foundation, Inc. | |
3 | Contributed by Michael Tiemann (tiemann@cygnus.com). | |
4 | ||
5 | This file is part of GNU CC. | |
6 | ||
7 | GNU CC is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2, or (at your option) | |
10 | any later version. | |
11 | ||
12 | GNU CC is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GNU CC; see the file COPYING. If not, write to | |
19 | the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ | |
20 | ||
21 | /* Note that some other tm.h files include this one and then override | |
22 | many of the definitions that relate to assembler syntax. */ | |
23 | ||
24 | #define LIB_SPEC "%{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p} %{g:-lg}" | |
25 | ||
98ccf8fe | 26 | /* Provide required defaults for linker -e and -d switches. */ |
1bb87f28 | 27 | |
d6f04508 | 28 | #define LINK_SPEC \ |
2defae7d | 29 | "%{!nostdlib:%{!e*:-e start}} -dc -dp %{static:-Bstatic} %{assert*}" |
1bb87f28 JW |
30 | |
31 | /* Special flags to the Sun-4 assembler when using pipe for input. */ | |
32 | ||
33 | #define ASM_SPEC " %{pipe:-} %{fpic:-k} %{fPIC:-k}" | |
34 | ||
885d8175 JW |
35 | /* Define macros to distinguish architectures. */ |
36 | #define CPP_SPEC "%{msparclite:-D__sparclite__} %{mv8:-D__sparcv8__}" | |
37 | ||
b1fc14e5 RS |
38 | /* Prevent error on `-sun4' and `-target sun4' options. */ |
39 | /* This used to translate -dalign to -malign, but that is no good | |
40 | because it can't turn off the usual meaning of making debugging dumps. */ | |
1bb87f28 | 41 | |
b1fc14e5 | 42 | #define CC1_SPEC "%{sun4:} %{target:}" |
1bb87f28 | 43 | |
d9ca49d5 JW |
44 | #if 0 |
45 | /* Sparc ABI says that long double is 4 words. | |
46 | ??? This doesn't work yet. */ | |
47 | #define LONG_DOUBLE_TYPE_SIZE 128 | |
48 | #endif | |
49 | ||
1bb87f28 JW |
50 | #define PTRDIFF_TYPE "int" |
51 | #define SIZE_TYPE "int" | |
52 | #define WCHAR_TYPE "short unsigned int" | |
53 | #define WCHAR_TYPE_SIZE 16 | |
54 | ||
98ccf8fe RK |
55 | /* Omit frame pointer at high optimization levels. */ |
56 | ||
1bb87f28 JW |
57 | #define OPTIMIZATION_OPTIONS(OPTIMIZE) \ |
58 | { \ | |
59 | if (OPTIMIZE >= 2) \ | |
60 | { \ | |
61 | flag_omit_frame_pointer = 1; \ | |
1bb87f28 JW |
62 | } \ |
63 | } | |
64 | ||
65 | /* These compiler options take an argument. We ignore -target for now. */ | |
66 | ||
67 | #define WORD_SWITCH_TAKES_ARG(STR) \ | |
68 | (!strcmp (STR, "Tdata") || !strcmp (STR, "include") \ | |
69 | || !strcmp (STR, "imacros") || !strcmp (STR, "target") \ | |
b1fc14e5 | 70 | || !strcmp (STR, "assert") || !strcmp (STR, "aux-info")) |
1bb87f28 JW |
71 | |
72 | /* Names to predefine in the preprocessor for this target machine. */ | |
73 | ||
74 | #define CPP_PREDEFINES "-Dsparc -Dsun -Dunix" | |
75 | ||
76 | /* Print subsidiary information on the compiler version in use. */ | |
77 | ||
78 | #define TARGET_VERSION fprintf (stderr, " (sparc)"); | |
79 | ||
80 | /* Generate DBX debugging information. */ | |
81 | ||
82 | #define DBX_DEBUGGING_INFO | |
83 | ||
84 | /* Run-time compilation parameters selecting different hardware subsets. */ | |
85 | ||
86 | extern int target_flags; | |
87 | ||
88 | /* Nonzero if we should generate code to use the fpu. */ | |
89 | #define TARGET_FPU (target_flags & 1) | |
90 | ||
91 | /* Nonzero if we should use FUNCTION_EPILOGUE. Otherwise, we | |
92 | use fast return insns, but lose some generality. */ | |
93 | #define TARGET_EPILOGUE (target_flags & 2) | |
94 | ||
b1fc14e5 RS |
95 | /* Nonzero means that reference doublewords as if they were guaranteed |
96 | to be aligned...if they aren't, too bad for the user! | |
eadf0fe6 | 97 | Like -dalign in Sun cc. */ |
b1fc14e5 RS |
98 | #define TARGET_HOPE_ALIGN (target_flags & 16) |
99 | ||
0be8e859 JW |
100 | /* Nonzero means make sure all doubles are on 8-byte boundaries. |
101 | This option results in a calling convention that is incompatible with | |
102 | every other sparc compiler in the world, and thus should only ever be | |
103 | used for experimenting. Also, varargs won't work with it, but it doesn't | |
104 | seem worth trying to fix. */ | |
b1fc14e5 | 105 | #define TARGET_FORCE_ALIGN (target_flags & 32) |
1bb87f28 | 106 | |
885d8175 JW |
107 | /* Nonzero means that we should generate code for a v8 sparc. */ |
108 | #define TARGET_V8 (target_flags & 64) | |
109 | ||
110 | /* Nonzero means that we should generate code for a sparclite. */ | |
111 | #define TARGET_SPARCLITE (target_flags & 128) | |
112 | ||
1bb87f28 JW |
113 | /* Macro to define tables used to set the flags. |
114 | This is a list in braces of pairs in braces, | |
115 | each pair being { "NAME", VALUE } | |
116 | where VALUE is the bits to set or minus the bits to clear. | |
117 | An empty string NAME is used to identify the default VALUE. */ | |
118 | ||
119 | #define TARGET_SWITCHES \ | |
120 | { {"fpu", 1}, \ | |
121 | {"soft-float", -1}, \ | |
122 | {"epilogue", 2}, \ | |
123 | {"no-epilogue", -2}, \ | |
b1fc14e5 RS |
124 | {"hope-align", 16}, \ |
125 | {"force-align", 48}, \ | |
885d8175 JW |
126 | {"v8", 64}, \ |
127 | {"no-v8", -64}, \ | |
128 | {"sparclite", 128}, \ | |
129 | {"no-sparclite", -128}, \ | |
b1fc14e5 | 130 | { "", TARGET_DEFAULT}} |
1bb87f28 JW |
131 | |
132 | #define TARGET_DEFAULT 3 | |
133 | \f | |
134 | /* target machine storage layout */ | |
135 | ||
136 | /* Define this if most significant bit is lowest numbered | |
137 | in instructions that operate on numbered bit-fields. */ | |
138 | #define BITS_BIG_ENDIAN 1 | |
139 | ||
140 | /* Define this if most significant byte of a word is the lowest numbered. */ | |
141 | /* This is true on the SPARC. */ | |
142 | #define BYTES_BIG_ENDIAN 1 | |
143 | ||
144 | /* Define this if most significant word of a multiword number is the lowest | |
145 | numbered. */ | |
146 | /* Doubles are stored in memory with the high order word first. This | |
147 | matters when cross-compiling. */ | |
148 | #define WORDS_BIG_ENDIAN 1 | |
149 | ||
b4ac57ab | 150 | /* number of bits in an addressable storage unit */ |
1bb87f28 JW |
151 | #define BITS_PER_UNIT 8 |
152 | ||
153 | /* Width in bits of a "word", which is the contents of a machine register. | |
154 | Note that this is not necessarily the width of data type `int'; | |
155 | if using 16-bit ints on a 68000, this would still be 32. | |
156 | But on a machine with 16-bit registers, this would be 16. */ | |
157 | #define BITS_PER_WORD 32 | |
158 | #define MAX_BITS_PER_WORD 32 | |
159 | ||
160 | /* Width of a word, in units (bytes). */ | |
161 | #define UNITS_PER_WORD 4 | |
162 | ||
163 | /* Width in bits of a pointer. | |
164 | See also the macro `Pmode' defined below. */ | |
165 | #define POINTER_SIZE 32 | |
166 | ||
167 | /* Allocation boundary (in *bits*) for storing arguments in argument list. */ | |
168 | #define PARM_BOUNDARY 32 | |
169 | ||
170 | /* Boundary (in *bits*) on which stack pointer should be aligned. */ | |
171 | #define STACK_BOUNDARY 64 | |
172 | ||
173 | /* Allocation boundary (in *bits*) for the code of a function. */ | |
174 | #define FUNCTION_BOUNDARY 32 | |
175 | ||
176 | /* Alignment of field after `int : 0' in a structure. */ | |
177 | #define EMPTY_FIELD_BOUNDARY 32 | |
178 | ||
179 | /* Every structure's size must be a multiple of this. */ | |
180 | #define STRUCTURE_SIZE_BOUNDARY 8 | |
181 | ||
182 | /* A bitfield declared as `int' forces `int' alignment for the struct. */ | |
183 | #define PCC_BITFIELD_TYPE_MATTERS 1 | |
184 | ||
185 | /* No data type wants to be aligned rounder than this. */ | |
186 | #define BIGGEST_ALIGNMENT 64 | |
187 | ||
77a02b01 JW |
188 | /* The best alignment to use in cases where we have a choice. */ |
189 | #define FASTEST_ALIGNMENT 64 | |
190 | ||
1bb87f28 JW |
191 | /* Make strings word-aligned so strcpy from constants will be faster. */ |
192 | #define CONSTANT_ALIGNMENT(EXP, ALIGN) \ | |
193 | (TREE_CODE (EXP) == STRING_CST \ | |
77a02b01 | 194 | && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN)) |
1bb87f28 JW |
195 | |
196 | /* Make arrays of chars word-aligned for the same reasons. */ | |
197 | #define DATA_ALIGNMENT(TYPE, ALIGN) \ | |
198 | (TREE_CODE (TYPE) == ARRAY_TYPE \ | |
199 | && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \ | |
77a02b01 | 200 | && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN)) |
1bb87f28 | 201 | |
b4ac57ab | 202 | /* Set this nonzero if move instructions will actually fail to work |
1bb87f28 | 203 | when given unaligned data. */ |
b4ac57ab | 204 | #define STRICT_ALIGNMENT 1 |
1bb87f28 JW |
205 | |
206 | /* Things that must be doubleword aligned cannot go in the text section, | |
207 | because the linker fails to align the text section enough! | |
208 | Put them in the data section. */ | |
209 | #define MAX_TEXT_ALIGN 32 | |
210 | ||
211 | #define SELECT_SECTION(T,RELOC) \ | |
212 | { \ | |
213 | if (TREE_CODE (T) == VAR_DECL) \ | |
214 | { \ | |
215 | if (TREE_READONLY (T) && ! TREE_SIDE_EFFECTS (T) \ | |
216 | && DECL_ALIGN (T) <= MAX_TEXT_ALIGN \ | |
217 | && ! (flag_pic && (RELOC))) \ | |
218 | text_section (); \ | |
219 | else \ | |
220 | data_section (); \ | |
221 | } \ | |
222 | else if (TREE_CODE (T) == CONSTRUCTOR) \ | |
223 | { \ | |
224 | if (flag_pic != 0 && (RELOC) != 0) \ | |
225 | data_section (); \ | |
226 | } \ | |
227 | else if (*tree_code_type[(int) TREE_CODE (T)] == 'c') \ | |
228 | { \ | |
229 | if ((TREE_CODE (T) == STRING_CST && flag_writable_strings) \ | |
230 | || TYPE_ALIGN (TREE_TYPE (T)) > MAX_TEXT_ALIGN) \ | |
231 | data_section (); \ | |
232 | else \ | |
233 | text_section (); \ | |
234 | } \ | |
235 | } | |
236 | ||
237 | /* Use text section for a constant | |
238 | unless we need more alignment than that offers. */ | |
239 | #define SELECT_RTX_SECTION(MODE, X) \ | |
240 | { \ | |
241 | if (GET_MODE_BITSIZE (MODE) <= MAX_TEXT_ALIGN \ | |
242 | && ! (flag_pic && symbolic_operand (X))) \ | |
243 | text_section (); \ | |
244 | else \ | |
245 | data_section (); \ | |
246 | } | |
247 | \f | |
248 | /* Standard register usage. */ | |
249 | ||
250 | /* Number of actual hardware registers. | |
251 | The hardware registers are assigned numbers for the compiler | |
252 | from 0 to just below FIRST_PSEUDO_REGISTER. | |
253 | All registers that the compiler knows about must be given numbers, | |
254 | even those that are not normally considered general registers. | |
255 | ||
256 | SPARC has 32 integer registers and 32 floating point registers. */ | |
257 | ||
258 | #define FIRST_PSEUDO_REGISTER 64 | |
259 | ||
260 | /* 1 for registers that have pervasive standard uses | |
261 | and are not available for the register allocator. | |
262 | 0 is used for the condition code and not to represent %g0, which is | |
263 | hardwired to 0, so reg 0 is *not* fixed. | |
d9ca49d5 JW |
264 | g1 through g4 are free to use as temporaries. |
265 | g5 through g7 are reserved for the operating system. */ | |
1bb87f28 | 266 | #define FIXED_REGISTERS \ |
d9ca49d5 | 267 | {0, 0, 0, 0, 0, 1, 1, 1, \ |
1bb87f28 JW |
268 | 0, 0, 0, 0, 0, 0, 1, 0, \ |
269 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
270 | 0, 0, 0, 0, 0, 0, 1, 1, \ | |
271 | \ | |
272 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
273 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
274 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
275 | 0, 0, 0, 0, 0, 0, 0, 0} | |
276 | ||
277 | /* 1 for registers not available across function calls. | |
278 | These must include the FIXED_REGISTERS and also any | |
279 | registers that can be used without being saved. | |
280 | The latter must include the registers where values are returned | |
281 | and the register where structure-value addresses are passed. | |
282 | Aside from that, you can include as many other registers as you like. */ | |
283 | #define CALL_USED_REGISTERS \ | |
284 | {1, 1, 1, 1, 1, 1, 1, 1, \ | |
285 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
286 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
287 | 0, 0, 0, 0, 0, 0, 1, 1, \ | |
288 | \ | |
289 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
290 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
291 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
292 | 1, 1, 1, 1, 1, 1, 1, 1} | |
293 | ||
294 | /* Return number of consecutive hard regs needed starting at reg REGNO | |
295 | to hold something of mode MODE. | |
296 | This is ordinarily the length in words of a value of mode MODE | |
297 | but can be less for certain modes in special long registers. | |
298 | ||
299 | On SPARC, ordinary registers hold 32 bits worth; | |
300 | this means both integer and floating point registers. | |
301 | ||
302 | We use vectors to keep this information about registers. */ | |
303 | ||
304 | /* How many hard registers it takes to make a register of this mode. */ | |
305 | extern int hard_regno_nregs[]; | |
306 | ||
307 | #define HARD_REGNO_NREGS(REGNO, MODE) \ | |
308 | ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) | |
309 | ||
310 | /* Value is 1 if register/mode pair is acceptable on sparc. */ | |
311 | extern int hard_regno_mode_ok[FIRST_PSEUDO_REGISTER]; | |
312 | ||
313 | /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. | |
314 | On SPARC, the cpu registers can hold any mode but the float registers | |
315 | can only hold SFmode or DFmode. See sparc.c for how we | |
316 | initialize this. */ | |
317 | #define HARD_REGNO_MODE_OK(REGNO, MODE) \ | |
318 | ((hard_regno_mode_ok[REGNO] & (1<<(int)(MODE))) != 0) | |
319 | ||
320 | /* Value is 1 if it is a good idea to tie two pseudo registers | |
321 | when one has mode MODE1 and one has mode MODE2. | |
322 | If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, | |
323 | for any hard reg, then this must be 0 for correct output. */ | |
324 | #define MODES_TIEABLE_P(MODE1, MODE2) \ | |
325 | ((MODE1) == (MODE2) || GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2)) | |
326 | ||
327 | /* Specify the registers used for certain standard purposes. | |
328 | The values of these macros are register numbers. */ | |
329 | ||
330 | /* SPARC pc isn't overloaded on a register that the compiler knows about. */ | |
331 | /* #define PC_REGNUM */ | |
332 | ||
333 | /* Register to use for pushing function arguments. */ | |
334 | #define STACK_POINTER_REGNUM 14 | |
335 | ||
336 | /* Actual top-of-stack address is 92 greater than the contents | |
337 | of the stack pointer register. 92 = 68 + 24. 64 bytes reserving space | |
338 | for the ins and local registers, 4 byte for structure return address, and | |
339 | 24 bytes for the 6 register parameters. */ | |
340 | #define STACK_POINTER_OFFSET FIRST_PARM_OFFSET(0) | |
341 | ||
342 | /* Base register for access to local variables of the function. */ | |
343 | #define FRAME_POINTER_REGNUM 30 | |
344 | ||
345 | #if 0 | |
346 | /* Register that is used for the return address. */ | |
347 | #define RETURN_ADDR_REGNUM 15 | |
348 | #endif | |
349 | ||
350 | /* Value should be nonzero if functions must have frame pointers. | |
351 | Zero means the frame pointer need not be set up (and parms | |
352 | may be accessed via the stack pointer) in functions that seem suitable. | |
353 | This is computed in `reload', in reload1.c. | |
354 | ||
355 | Used in flow.c, global-alloc.c, and reload1.c. */ | |
356 | extern int leaf_function; | |
357 | ||
358 | #define FRAME_POINTER_REQUIRED \ | |
a72cb8ec | 359 | (! (leaf_function_p () && only_leaf_regs_used ())) |
1bb87f28 JW |
360 | |
361 | /* C statement to store the difference between the frame pointer | |
362 | and the stack pointer values immediately after the function prologue. | |
363 | ||
364 | Note, we always pretend that this is a leaf function because if | |
365 | it's not, there's no point in trying to eliminate the | |
366 | frame pointer. If it is a leaf function, we guessed right! */ | |
367 | #define INITIAL_FRAME_POINTER_OFFSET(VAR) \ | |
368 | do { (VAR) = compute_frame_size (get_frame_size (), 1); } while (0) | |
369 | ||
370 | /* Base register for access to arguments of the function. */ | |
371 | #define ARG_POINTER_REGNUM 30 | |
372 | ||
373 | /* Register in which static-chain is passed to a function. */ | |
374 | /* ??? */ | |
375 | #define STATIC_CHAIN_REGNUM 1 | |
376 | ||
377 | /* Register which holds offset table for position-independent | |
378 | data references. */ | |
379 | ||
380 | #define PIC_OFFSET_TABLE_REGNUM 23 | |
381 | ||
382 | #define INITIALIZE_PIC initialize_pic () | |
383 | #define FINALIZE_PIC finalize_pic () | |
384 | ||
d9ca49d5 | 385 | /* Sparc ABI says that quad-precision floats and all structures are returned |
dafe6cf1 RS |
386 | in memory. We go along regarding floats, but for structures |
387 | we follow GCC's normal policy. Use -fpcc-struct-value | |
388 | if you want to follow the ABI. */ | |
d9ca49d5 | 389 | #define RETURN_IN_MEMORY(TYPE) \ |
dafe6cf1 | 390 | (TYPE_MODE (TYPE) == TFmode) |
d9ca49d5 | 391 | |
1bb87f28 JW |
392 | /* Functions which return large structures get the address |
393 | to place the wanted value at offset 64 from the frame. | |
394 | Must reserve 64 bytes for the in and local registers. */ | |
395 | /* Used only in other #defines in this file. */ | |
396 | #define STRUCT_VALUE_OFFSET 64 | |
397 | ||
398 | #define STRUCT_VALUE \ | |
399 | gen_rtx (MEM, Pmode, \ | |
400 | gen_rtx (PLUS, Pmode, stack_pointer_rtx, \ | |
401 | gen_rtx (CONST_INT, VOIDmode, STRUCT_VALUE_OFFSET))) | |
402 | #define STRUCT_VALUE_INCOMING \ | |
403 | gen_rtx (MEM, Pmode, \ | |
404 | gen_rtx (PLUS, Pmode, frame_pointer_rtx, \ | |
405 | gen_rtx (CONST_INT, VOIDmode, STRUCT_VALUE_OFFSET))) | |
406 | \f | |
407 | /* Define the classes of registers for register constraints in the | |
408 | machine description. Also define ranges of constants. | |
409 | ||
410 | One of the classes must always be named ALL_REGS and include all hard regs. | |
411 | If there is more than one class, another class must be named NO_REGS | |
412 | and contain no registers. | |
413 | ||
414 | The name GENERAL_REGS must be the name of a class (or an alias for | |
415 | another name such as ALL_REGS). This is the class of registers | |
416 | that is allowed by "g" or "r" in a register constraint. | |
417 | Also, registers outside this class are allocated only when | |
418 | instructions express preferences for them. | |
419 | ||
420 | The classes must be numbered in nondecreasing order; that is, | |
421 | a larger-numbered class must never be contained completely | |
422 | in a smaller-numbered class. | |
423 | ||
424 | For any two classes, it is very desirable that there be another | |
425 | class that represents their union. */ | |
426 | ||
427 | /* The SPARC has two kinds of registers, general and floating point. */ | |
428 | ||
429 | enum reg_class { NO_REGS, GENERAL_REGS, FP_REGS, ALL_REGS, LIM_REG_CLASSES }; | |
430 | ||
431 | #define N_REG_CLASSES (int) LIM_REG_CLASSES | |
432 | ||
433 | /* Give names of register classes as strings for dump file. */ | |
434 | ||
435 | #define REG_CLASS_NAMES \ | |
436 | {"NO_REGS", "GENERAL_REGS", "FP_REGS", "ALL_REGS" } | |
437 | ||
438 | /* Define which registers fit in which classes. | |
439 | This is an initializer for a vector of HARD_REG_SET | |
440 | of length N_REG_CLASSES. */ | |
441 | ||
442 | #if 0 && defined (__GNUC__) | |
443 | #define REG_CLASS_CONTENTS {0LL, 0xfffffffeLL, 0xffffffff00000000LL, 0xfffffffffffffffeLL} | |
444 | #else | |
445 | #define REG_CLASS_CONTENTS {{0, 0}, {-2, 0}, {0, -1}, {-2, -1}} | |
446 | #endif | |
447 | ||
448 | /* The same information, inverted: | |
449 | Return the class number of the smallest class containing | |
450 | reg number REGNO. This could be a conditional expression | |
451 | or could index an array. */ | |
452 | ||
453 | #define REGNO_REG_CLASS(REGNO) \ | |
454 | ((REGNO) >= 32 ? FP_REGS : (REGNO) == 0 ? NO_REGS : GENERAL_REGS) | |
455 | ||
456 | /* This is the order in which to allocate registers | |
457 | normally. */ | |
458 | #define REG_ALLOC_ORDER \ | |
b4ac57ab RS |
459 | { 8, 9, 10, 11, 12, 13, 2, 3, \ |
460 | 15, 16, 17, 18, 19, 20, 21, 22, \ | |
461 | 23, 24, 25, 26, 27, 28, 29, 31, \ | |
1bb87f28 JW |
462 | 32, 33, 34, 35, 36, 37, 38, 39, \ |
463 | 40, 41, 42, 43, 44, 45, 46, 47, \ | |
464 | 48, 49, 50, 51, 52, 53, 54, 55, \ | |
465 | 56, 57, 58, 59, 60, 61, 62, 63, \ | |
4b69d2a3 | 466 | 1, 4, 5, 6, 7, 0, 14, 30} |
1bb87f28 JW |
467 | |
468 | /* This is the order in which to allocate registers for | |
469 | leaf functions. If all registers can fit in the "i" registers, | |
470 | then we have the possibility of having a leaf function. */ | |
471 | #define REG_LEAF_ALLOC_ORDER \ | |
472 | { 2, 3, 24, 25, 26, 27, 28, 29, \ | |
473 | 15, 8, 9, 10, 11, 12, 13, \ | |
474 | 16, 17, 18, 19, 20, 21, 22, 23, \ | |
475 | 32, 33, 34, 35, 36, 37, 38, 39, \ | |
476 | 40, 41, 42, 43, 44, 45, 46, 47, \ | |
477 | 48, 49, 50, 51, 52, 53, 54, 55, \ | |
478 | 56, 57, 58, 59, 60, 61, 62, 63, \ | |
4b69d2a3 | 479 | 1, 4, 5, 6, 7, 0, 14, 30, 31} |
1bb87f28 JW |
480 | |
481 | #define ORDER_REGS_FOR_LOCAL_ALLOC order_regs_for_local_alloc () | |
482 | ||
483 | #define LEAF_REGISTERS \ | |
484 | { 1, 1, 1, 1, 1, 1, 1, 1, \ | |
485 | 0, 0, 0, 0, 0, 0, 1, 0, \ | |
486 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
487 | 1, 1, 1, 1, 1, 1, 0, 1, \ | |
488 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
489 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
490 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
4b69d2a3 | 491 | 1, 1, 1, 1, 1, 1, 1, 1} |
1bb87f28 JW |
492 | |
493 | extern char leaf_reg_remap[]; | |
494 | #define LEAF_REG_REMAP(REGNO) (leaf_reg_remap[REGNO]) | |
495 | extern char leaf_reg_backmap[]; | |
496 | #define LEAF_REG_BACKMAP(REGNO) (leaf_reg_backmap[REGNO]) | |
497 | ||
498 | #define REG_USED_SO_FAR(REGNO) \ | |
499 | ((REGNO) >= 24 && (REGNO) < 30 \ | |
500 | ? (regs_ever_live[24] \ | |
501 | || regs_ever_live[25] \ | |
502 | || regs_ever_live[26] \ | |
503 | || regs_ever_live[27] \ | |
504 | || regs_ever_live[28] \ | |
505 | || regs_ever_live[29]) : 0) | |
506 | ||
507 | /* The class value for index registers, and the one for base regs. */ | |
508 | #define INDEX_REG_CLASS GENERAL_REGS | |
509 | #define BASE_REG_CLASS GENERAL_REGS | |
510 | ||
511 | /* Get reg_class from a letter such as appears in the machine description. */ | |
512 | ||
513 | #define REG_CLASS_FROM_LETTER(C) \ | |
514 | ((C) == 'f' ? FP_REGS : (C) == 'r' ? GENERAL_REGS : NO_REGS) | |
515 | ||
516 | /* The letters I, J, K, L and M in a register constraint string | |
517 | can be used to stand for particular ranges of immediate operands. | |
518 | This macro defines what the ranges are. | |
519 | C is the letter, and VALUE is a constant value. | |
520 | Return 1 if VALUE is in the range specified by C. | |
521 | ||
522 | For SPARC, `I' is used for the range of constants an insn | |
523 | can actually contain. | |
524 | `J' is used for the range which is just zero (since that is R0). | |
525 | `K' is used for the 5-bit operand of a compare insns. */ | |
526 | ||
527 | #define SMALL_INT(X) ((unsigned) (INTVAL (X) + 0x1000) < 0x2000) | |
528 | ||
529 | #define CONST_OK_FOR_LETTER_P(VALUE, C) \ | |
530 | ((C) == 'I' ? (unsigned) ((VALUE) + 0x1000) < 0x2000 \ | |
531 | : (C) == 'J' ? (VALUE) == 0 \ | |
532 | : (C) == 'K' ? ((VALUE) & 0x3ff) == 0 \ | |
533 | : 0) | |
534 | ||
535 | /* Similar, but for floating constants, and defining letters G and H. | |
536 | Here VALUE is the CONST_DOUBLE rtx itself. */ | |
537 | ||
538 | #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \ | |
539 | ((C) == 'G' ? CONST_DOUBLE_HIGH (VALUE) == 0 \ | |
540 | && CONST_DOUBLE_LOW (VALUE) == 0 \ | |
541 | : (C) == 'H' ? arith_double_operand (VALUE, DImode) \ | |
542 | : 0) | |
543 | ||
544 | /* Given an rtx X being reloaded into a reg required to be | |
545 | in class CLASS, return the class of reg to actually use. | |
546 | In general this is just CLASS; but on some machines | |
547 | in some cases it is preferable to use a more restrictive class. */ | |
2b9a9aea JW |
548 | /* We can't load constants into FP registers. We can't load any FP constant |
549 | if an 'E' constraint fails to match it. */ | |
550 | #define PREFERRED_RELOAD_CLASS(X,CLASS) \ | |
551 | (CONSTANT_P (X) \ | |
552 | && ((CLASS) == FP_REGS \ | |
553 | || (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \ | |
554 | && (HOST_FLOAT_FORMAT != IEEE_FLOAT_FORMAT \ | |
555 | || HOST_BITS_PER_INT != BITS_PER_WORD))) \ | |
556 | ? NO_REGS : (CLASS)) | |
1bb87f28 JW |
557 | |
558 | /* Return the register class of a scratch register needed to load IN into | |
559 | a register of class CLASS in MODE. | |
560 | ||
561 | On the SPARC, when PIC, we need a temporary when loading some addresses | |
562 | into a register. */ | |
563 | ||
564 | #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, IN) \ | |
565 | (flag_pic && pic_address_needs_scratch (IN) ? GENERAL_REGS : NO_REGS) | |
566 | ||
567 | /* Return the maximum number of consecutive registers | |
568 | needed to represent mode MODE in a register of class CLASS. */ | |
569 | /* On SPARC, this is the size of MODE in words. */ | |
570 | #define CLASS_MAX_NREGS(CLASS, MODE) \ | |
571 | ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) | |
572 | \f | |
573 | /* Stack layout; function entry, exit and calling. */ | |
574 | ||
575 | /* Define the number of register that can hold parameters. | |
576 | These two macros are used only in other macro definitions below. */ | |
577 | #define NPARM_REGS 6 | |
578 | ||
579 | /* Define this if pushing a word on the stack | |
580 | makes the stack pointer a smaller address. */ | |
581 | #define STACK_GROWS_DOWNWARD | |
582 | ||
583 | /* Define this if the nominal address of the stack frame | |
584 | is at the high-address end of the local variables; | |
585 | that is, each additional local variable allocated | |
586 | goes at a more negative offset in the frame. */ | |
587 | #define FRAME_GROWS_DOWNWARD | |
588 | ||
589 | /* Offset within stack frame to start allocating local variables at. | |
590 | If FRAME_GROWS_DOWNWARD, this is the offset to the END of the | |
591 | first local allocated. Otherwise, it is the offset to the BEGINNING | |
592 | of the first local allocated. */ | |
593 | #define STARTING_FRAME_OFFSET (-16) | |
594 | ||
595 | /* If we generate an insn to push BYTES bytes, | |
596 | this says how many the stack pointer really advances by. | |
597 | On SPARC, don't define this because there are no push insns. */ | |
598 | /* #define PUSH_ROUNDING(BYTES) */ | |
599 | ||
600 | /* Offset of first parameter from the argument pointer register value. | |
601 | This is 64 for the ins and locals, plus 4 for the struct-return reg | |
0be8e859 JW |
602 | even if this function isn't going to use it. |
603 | If TARGET_FORCE_ALIGN, we must reserve 4 more bytes to ensure that the | |
604 | stack remains aligned. */ | |
605 | #define FIRST_PARM_OFFSET(FNDECL) \ | |
606 | (STRUCT_VALUE_OFFSET + UNITS_PER_WORD + (TARGET_FORCE_ALIGN ? 4 : 0)) | |
1bb87f28 JW |
607 | |
608 | /* When a parameter is passed in a register, stack space is still | |
609 | allocated for it. */ | |
610 | #define REG_PARM_STACK_SPACE(DECL) (NPARM_REGS * UNITS_PER_WORD) | |
611 | ||
612 | /* Keep the stack pointer constant throughout the function. | |
b4ac57ab | 613 | This is both an optimization and a necessity: longjmp |
1bb87f28 JW |
614 | doesn't behave itself when the stack pointer moves within |
615 | the function! */ | |
616 | #define ACCUMULATE_OUTGOING_ARGS | |
617 | ||
618 | /* Value is the number of bytes of arguments automatically | |
619 | popped when returning from a subroutine call. | |
620 | FUNTYPE is the data type of the function (as a tree), | |
621 | or for a library call it is an identifier node for the subroutine name. | |
622 | SIZE is the number of bytes of arguments passed on the stack. */ | |
623 | ||
624 | #define RETURN_POPS_ARGS(FUNTYPE,SIZE) 0 | |
625 | ||
626 | /* Some subroutine macros specific to this machine. */ | |
627 | #define BASE_RETURN_VALUE_REG(MODE) \ | |
628 | ((MODE) == SFmode || (MODE) == DFmode ? 32 : 8) | |
629 | #define BASE_OUTGOING_VALUE_REG(MODE) \ | |
630 | ((MODE) == SFmode || (MODE) == DFmode ? 32 : 24) | |
631 | #define BASE_PASSING_ARG_REG(MODE) (8) | |
632 | #define BASE_INCOMING_ARG_REG(MODE) (24) | |
633 | ||
634 | /* Define how to find the value returned by a function. | |
635 | VALTYPE is the data type of the value (as a tree). | |
636 | If the precise function being called is known, FUNC is its FUNCTION_DECL; | |
637 | otherwise, FUNC is 0. */ | |
638 | ||
639 | /* On SPARC the value is found in the first "output" register. */ | |
640 | ||
641 | #define FUNCTION_VALUE(VALTYPE, FUNC) \ | |
642 | gen_rtx (REG, TYPE_MODE (VALTYPE), BASE_RETURN_VALUE_REG (TYPE_MODE (VALTYPE))) | |
643 | ||
644 | /* But the called function leaves it in the first "input" register. */ | |
645 | ||
646 | #define FUNCTION_OUTGOING_VALUE(VALTYPE, FUNC) \ | |
647 | gen_rtx (REG, TYPE_MODE (VALTYPE), BASE_OUTGOING_VALUE_REG (TYPE_MODE (VALTYPE))) | |
648 | ||
649 | /* Define how to find the value returned by a library function | |
650 | assuming the value has mode MODE. */ | |
651 | ||
652 | #define LIBCALL_VALUE(MODE) \ | |
653 | gen_rtx (REG, MODE, BASE_RETURN_VALUE_REG (MODE)) | |
654 | ||
655 | /* 1 if N is a possible register number for a function value | |
656 | as seen by the caller. | |
657 | On SPARC, the first "output" reg is used for integer values, | |
658 | and the first floating point register is used for floating point values. */ | |
659 | ||
660 | #define FUNCTION_VALUE_REGNO_P(N) ((N) == 8 || (N) == 32) | |
661 | ||
662 | /* 1 if N is a possible register number for function argument passing. | |
663 | On SPARC, these are the "output" registers. */ | |
664 | ||
665 | #define FUNCTION_ARG_REGNO_P(N) ((N) < 14 && (N) > 7) | |
666 | \f | |
667 | /* Define a data type for recording info about an argument list | |
668 | during the scan of that argument list. This data type should | |
669 | hold all necessary information about the function itself | |
670 | and about the args processed so far, enough to enable macros | |
671 | such as FUNCTION_ARG to determine where the next arg should go. | |
672 | ||
673 | On SPARC, this is a single integer, which is a number of words | |
674 | of arguments scanned so far (including the invisible argument, | |
675 | if any, which holds the structure-value-address). | |
676 | Thus 7 or more means all following args should go on the stack. */ | |
677 | ||
678 | #define CUMULATIVE_ARGS int | |
679 | ||
680 | #define ROUND_ADVANCE(SIZE) \ | |
b1fc14e5 RS |
681 | ((SIZE + UNITS_PER_WORD - 1) / UNITS_PER_WORD) |
682 | ||
683 | /* Round a register number up to a proper boundary for an arg of mode MODE. | |
684 | Note that we need an odd/even pair for a two-word arg, | |
685 | since that will become 8-byte aligned when stored in memory. */ | |
686 | #define ROUND_REG(X, MODE) \ | |
687 | (TARGET_FORCE_ALIGN && GET_MODE_UNIT_SIZE ((MODE)) > 4 \ | |
688 | ? ((X) + ! ((X) & 1)) : (X)) | |
1bb87f28 JW |
689 | |
690 | /* Initialize a variable CUM of type CUMULATIVE_ARGS | |
691 | for a call to a function whose data type is FNTYPE. | |
692 | For a library call, FNTYPE is 0. | |
693 | ||
694 | On SPARC, the offset always starts at 0: the first parm reg is always | |
695 | the same reg. */ | |
696 | ||
697 | #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME) ((CUM) = 0) | |
698 | ||
699 | /* Update the data in CUM to advance over an argument | |
700 | of mode MODE and data type TYPE. | |
701 | (TYPE is null for libcalls where that information may not be available.) */ | |
702 | ||
703 | #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ | |
b1fc14e5 RS |
704 | ((CUM) = (ROUND_REG ((CUM), (MODE)) \ |
705 | + ((MODE) != BLKmode \ | |
706 | ? ROUND_ADVANCE (GET_MODE_SIZE (MODE)) \ | |
707 | : ROUND_ADVANCE (int_size_in_bytes (TYPE))))) | |
1bb87f28 JW |
708 | |
709 | /* Determine where to put an argument to a function. | |
710 | Value is zero to push the argument on the stack, | |
711 | or a hard register in which to store the argument. | |
712 | ||
713 | MODE is the argument's machine mode. | |
714 | TYPE is the data type of the argument (as a tree). | |
715 | This is null for libcalls where that information may | |
716 | not be available. | |
717 | CUM is a variable of type CUMULATIVE_ARGS which gives info about | |
718 | the preceding args and about the function being called. | |
719 | NAMED is nonzero if this argument is a named parameter | |
720 | (otherwise it is an extra parameter matching an ellipsis). */ | |
721 | ||
722 | /* On SPARC the first six args are normally in registers | |
723 | and the rest are pushed. Any arg that starts within the first 6 words | |
724 | is at least partially passed in a register unless its data type forbids. */ | |
725 | ||
726 | #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ | |
b1fc14e5 | 727 | (ROUND_REG ((CUM), (MODE)) < NPARM_REGS \ |
1bb87f28 | 728 | && ((TYPE)==0 || ! TREE_ADDRESSABLE ((tree)(TYPE))) \ |
b1fc14e5 RS |
729 | && ((TYPE)==0 || (MODE) != BLKmode \ |
730 | || (TYPE_ALIGN ((TYPE)) % PARM_BOUNDARY == 0)) \ | |
731 | ? gen_rtx (REG, (MODE), \ | |
732 | (BASE_PASSING_ARG_REG (MODE) + ROUND_REG ((CUM), (MODE)))) \ | |
733 | : 0) | |
1bb87f28 JW |
734 | |
735 | /* Define where a function finds its arguments. | |
736 | This is different from FUNCTION_ARG because of register windows. */ | |
737 | ||
738 | #define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED) \ | |
b1fc14e5 | 739 | (ROUND_REG ((CUM), (MODE)) < NPARM_REGS \ |
1bb87f28 | 740 | && ((TYPE)==0 || ! TREE_ADDRESSABLE ((tree)(TYPE))) \ |
b1fc14e5 RS |
741 | && ((TYPE)==0 || (MODE) != BLKmode \ |
742 | || (TYPE_ALIGN ((TYPE)) % PARM_BOUNDARY == 0)) \ | |
743 | ? gen_rtx (REG, (MODE), \ | |
744 | (BASE_INCOMING_ARG_REG (MODE) + ROUND_REG ((CUM), (MODE)))) \ | |
745 | : 0) | |
1bb87f28 JW |
746 | |
747 | /* For an arg passed partly in registers and partly in memory, | |
748 | this is the number of registers used. | |
749 | For args passed entirely in registers or entirely in memory, zero. | |
750 | Any arg that starts in the first 6 regs but won't entirely fit in them | |
751 | needs partial registers on the Sparc. */ | |
752 | ||
753 | #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \ | |
b1fc14e5 | 754 | ((ROUND_REG ((CUM), (MODE)) < NPARM_REGS \ |
1bb87f28 | 755 | && ((TYPE)==0 || ! TREE_ADDRESSABLE ((tree)(TYPE))) \ |
b1fc14e5 RS |
756 | && ((TYPE)==0 || (MODE) != BLKmode \ |
757 | || (TYPE_ALIGN ((TYPE)) % PARM_BOUNDARY == 0)) \ | |
758 | && (ROUND_REG ((CUM), (MODE)) \ | |
1bb87f28 JW |
759 | + ((MODE) == BLKmode \ |
760 | ? ROUND_ADVANCE (int_size_in_bytes (TYPE)) \ | |
b1fc14e5 RS |
761 | : ROUND_ADVANCE (GET_MODE_SIZE (MODE)))) - NPARM_REGS > 0) \ |
762 | ? (NPARM_REGS - ROUND_REG ((CUM), (MODE))) \ | |
1bb87f28 JW |
763 | : 0) |
764 | ||
d9ca49d5 JW |
765 | /* The SPARC ABI stipulates passing struct arguments (of any size) and |
766 | quad-precision floats by invisible reference. */ | |
1bb87f28 | 767 | #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \ |
d9ca49d5 JW |
768 | ((TYPE && (TREE_CODE (TYPE) == RECORD_TYPE \ |
769 | || TREE_CODE (TYPE) == UNION_TYPE)) \ | |
770 | || (MODE == TFmode)) | |
1bb87f28 | 771 | |
b1fc14e5 RS |
772 | /* If defined, a C expression that gives the alignment boundary, in |
773 | bits, of an argument with the specified mode and type. If it is | |
774 | not defined, `PARM_BOUNDARY' is used for all arguments. | |
775 | ||
776 | This definition does nothing special unless TARGET_FORCE_ALIGN; | |
777 | in that case, it aligns each arg to the natural boundary. */ | |
778 | ||
779 | #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \ | |
780 | (! TARGET_FORCE_ALIGN \ | |
781 | ? PARM_BOUNDARY \ | |
782 | : (((TYPE) != 0) \ | |
783 | ? (TYPE_ALIGN (TYPE) <= PARM_BOUNDARY \ | |
784 | ? PARM_BOUNDARY \ | |
785 | : TYPE_ALIGN (TYPE)) \ | |
786 | : (GET_MODE_ALIGNMENT (MODE) <= PARM_BOUNDARY \ | |
787 | ? PARM_BOUNDARY \ | |
788 | : GET_MODE_ALIGNMENT (MODE)))) | |
789 | ||
1bb87f28 JW |
790 | /* Define the information needed to generate branch and scc insns. This is |
791 | stored from the compare operation. Note that we can't use "rtx" here | |
792 | since it hasn't been defined! */ | |
793 | ||
794 | extern struct rtx_def *sparc_compare_op0, *sparc_compare_op1; | |
795 | ||
796 | /* Define the function that build the compare insn for scc and bcc. */ | |
797 | ||
798 | extern struct rtx_def *gen_compare_reg (); | |
799 | \f | |
4b69d2a3 RS |
800 | /* Generate the special assembly code needed to tell the assembler whatever |
801 | it might need to know about the return value of a function. | |
802 | ||
803 | For Sparc assemblers, we need to output a .proc pseudo-op which conveys | |
804 | information to the assembler relating to peephole optimization (done in | |
805 | the assembler). */ | |
806 | ||
807 | #define ASM_DECLARE_RESULT(FILE, RESULT) \ | |
808 | fprintf ((FILE), "\t.proc\t0%o\n", sparc_type_code (TREE_TYPE (RESULT))) | |
809 | ||
1bb87f28 JW |
810 | /* Output the label for a function definition. */ |
811 | ||
4b69d2a3 RS |
812 | #define ASM_DECLARE_FUNCTION_NAME(FILE, NAME, DECL) \ |
813 | do { \ | |
814 | ASM_DECLARE_RESULT (FILE, DECL_RESULT (DECL)); \ | |
815 | ASM_OUTPUT_LABEL (FILE, NAME); \ | |
816 | } while (0) | |
1bb87f28 JW |
817 | |
818 | /* Two views of the size of the current frame. */ | |
819 | extern int actual_fsize; | |
820 | extern int apparent_fsize; | |
821 | ||
822 | /* This macro generates the assembly code for function entry. | |
823 | FILE is a stdio stream to output the code to. | |
824 | SIZE is an int: how many units of temporary storage to allocate. | |
825 | Refer to the array `regs_ever_live' to determine which registers | |
826 | to save; `regs_ever_live[I]' is nonzero if register number I | |
827 | is ever used in the function. This macro is responsible for | |
828 | knowing which registers should not be saved even if used. */ | |
829 | ||
830 | /* On SPARC, move-double insns between fpu and cpu need an 8-byte block | |
831 | of memory. If any fpu reg is used in the function, we allocate | |
832 | such a block here, at the bottom of the frame, just in case it's needed. | |
833 | ||
834 | If this function is a leaf procedure, then we may choose not | |
835 | to do a "save" insn. The decision about whether or not | |
836 | to do this is made in regclass.c. */ | |
837 | ||
838 | #define FUNCTION_PROLOGUE(FILE, SIZE) \ | |
839 | output_function_prologue (FILE, SIZE, leaf_function) | |
840 | ||
841 | /* Output assembler code to FILE to increment profiler label # LABELNO | |
842 | for profiling a function entry. */ | |
843 | ||
844 | #define FUNCTION_PROFILER(FILE, LABELNO) \ | |
845 | fprintf (FILE, "\tsethi %%hi(LP%d),%%o0\n\tcall mcount\n\tor %%lo(LP%d),%%o0,%%o0\n", \ | |
846 | (LABELNO), (LABELNO)) | |
847 | ||
848 | /* Output assembler code to FILE to initialize this source file's | |
849 | basic block profiling info, if that has not already been done. */ | |
850 | ||
851 | #define FUNCTION_BLOCK_PROFILER(FILE, LABELNO) \ | |
852 | fprintf (FILE, "\tsethi %%hi(LPBX0),%%o0\n\tld [%%lo(LPBX0)+%%o0],%%o1\n\ttst %%o1\n\tbne LPY%d\n\tadd %%o0,%%lo(LPBX0),%%o0\n\tcall ___bb_init_func\n\tnop\nLPY%d:\n", \ | |
853 | (LABELNO), (LABELNO)) | |
854 | ||
855 | /* Output assembler code to FILE to increment the entry-count for | |
856 | the BLOCKNO'th basic block in this source file. */ | |
857 | ||
858 | #define BLOCK_PROFILER(FILE, BLOCKNO) \ | |
859 | { \ | |
860 | int blockn = (BLOCKNO); \ | |
861 | fprintf (FILE, "\tsethi %%hi(LPBX2+%d),%%g1\n\tld [%%lo(LPBX2+%d)+%%g1],%%g2\n\ | |
862 | \tadd %%g2,1,%%g2\n\tst %%g2,[%%lo(LPBX2+%d)+%%g1]\n", \ | |
863 | 4 * blockn, 4 * blockn, 4 * blockn); \ | |
864 | } | |
865 | ||
866 | /* Output rtl to increment the entry-count for the LABELNO'th instrumented | |
867 | arc in this source file. */ | |
868 | ||
869 | #define ARC_PROFILER(ARCNO, INSERT_AFTER) \ | |
870 | output_arc_profiler (ARCNO, INSERT_AFTER) | |
871 | ||
872 | /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, | |
873 | the stack pointer does not matter. The value is tested only in | |
874 | functions that have frame pointers. | |
875 | No definition is equivalent to always zero. */ | |
876 | ||
877 | extern int current_function_calls_alloca; | |
878 | extern int current_function_outgoing_args_size; | |
879 | ||
880 | #define EXIT_IGNORE_STACK \ | |
881 | (get_frame_size () != 0 \ | |
882 | || current_function_calls_alloca || current_function_outgoing_args_size) | |
883 | ||
884 | /* This macro generates the assembly code for function exit, | |
885 | on machines that need it. If FUNCTION_EPILOGUE is not defined | |
886 | then individual return instructions are generated for each | |
887 | return statement. Args are same as for FUNCTION_PROLOGUE. | |
888 | ||
889 | The function epilogue should not depend on the current stack pointer! | |
890 | It should use the frame pointer only. This is mandatory because | |
891 | of alloca; we also take advantage of it to omit stack adjustments | |
892 | before returning. */ | |
893 | ||
894 | /* This declaration is needed due to traditional/ANSI | |
895 | incompatibilities which cannot be #ifdefed away | |
896 | because they occur inside of macros. Sigh. */ | |
897 | extern union tree_node *current_function_decl; | |
898 | ||
899 | #define FUNCTION_EPILOGUE(FILE, SIZE) \ | |
ef8200df | 900 | output_function_epilogue (FILE, SIZE, leaf_function) |
1bb87f28 JW |
901 | |
902 | #define DELAY_SLOTS_FOR_EPILOGUE 1 | |
903 | #define ELIGIBLE_FOR_EPILOGUE_DELAY(trial, slots_filled) \ | |
904 | eligible_for_epilogue_delay (trial, slots_filled) | |
905 | ||
906 | /* Output assembler code for a block containing the constant parts | |
907 | of a trampoline, leaving space for the variable parts. */ | |
908 | ||
909 | /* On the sparc, the trampoline contains five instructions: | |
910 | sethi #TOP_OF_FUNCTION,%g2 | |
911 | or #BOTTOM_OF_FUNCTION,%g2,%g2 | |
912 | sethi #TOP_OF_STATIC,%g1 | |
913 | jmp g2 | |
914 | or #BOTTOM_OF_STATIC,%g1,%g1 */ | |
915 | #define TRAMPOLINE_TEMPLATE(FILE) \ | |
916 | { \ | |
917 | ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x00000000)); \ | |
918 | ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x00000000)); \ | |
919 | ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x00000000)); \ | |
920 | ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x81C08000)); \ | |
921 | ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x00000000)); \ | |
922 | } | |
923 | ||
924 | /* Length in units of the trampoline for entering a nested function. */ | |
925 | ||
926 | #define TRAMPOLINE_SIZE 20 | |
927 | ||
928 | /* Emit RTL insns to initialize the variable parts of a trampoline. | |
929 | FNADDR is an RTX for the address of the function's pure code. | |
930 | CXT is an RTX for the static chain value for the function. | |
931 | ||
932 | This takes 16 insns: 2 shifts & 2 ands (to split up addresses), 4 sethi | |
933 | (to load in opcodes), 4 iors (to merge address and opcodes), and 4 writes | |
934 | (to store insns). This is a bit excessive. Perhaps a different | |
935 | mechanism would be better here. */ | |
936 | ||
937 | #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ | |
938 | { \ | |
939 | rtx high_cxt = expand_shift (RSHIFT_EXPR, SImode, CXT, \ | |
940 | size_int (10), 0, 1); \ | |
941 | rtx high_fn = expand_shift (RSHIFT_EXPR, SImode, FNADDR, \ | |
942 | size_int (10), 0, 1); \ | |
943 | rtx low_cxt = expand_and (CXT, gen_rtx (CONST_INT, VOIDmode, 0x3ff), 0); \ | |
944 | rtx low_fn = expand_and (FNADDR, gen_rtx (CONST_INT, VOIDmode, 0x3ff), 0); \ | |
945 | rtx g1_sethi = gen_rtx (HIGH, SImode, \ | |
946 | gen_rtx (CONST_INT, VOIDmode, 0x03000000)); \ | |
947 | rtx g2_sethi = gen_rtx (HIGH, SImode, \ | |
948 | gen_rtx (CONST_INT, VOIDmode, 0x05000000)); \ | |
949 | rtx g1_ori = gen_rtx (HIGH, SImode, \ | |
950 | gen_rtx (CONST_INT, VOIDmode, 0x82106000)); \ | |
951 | rtx g2_ori = gen_rtx (HIGH, SImode, \ | |
952 | gen_rtx (CONST_INT, VOIDmode, 0x8410A000)); \ | |
953 | rtx tem = gen_reg_rtx (SImode); \ | |
954 | emit_move_insn (tem, g2_sethi); \ | |
955 | emit_insn (gen_iorsi3 (high_fn, high_fn, tem)); \ | |
956 | emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 0)), high_fn);\ | |
957 | emit_move_insn (tem, g2_ori); \ | |
958 | emit_insn (gen_iorsi3 (low_fn, low_fn, tem)); \ | |
959 | emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 4)), low_fn);\ | |
960 | emit_move_insn (tem, g1_sethi); \ | |
961 | emit_insn (gen_iorsi3 (high_cxt, high_cxt, tem)); \ | |
962 | emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 8)), high_cxt);\ | |
963 | emit_move_insn (tem, g1_ori); \ | |
964 | emit_insn (gen_iorsi3 (low_cxt, low_cxt, tem)); \ | |
965 | emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 16)), low_cxt);\ | |
966 | } | |
967 | ||
968 | /* Emit code for a call to builtin_saveregs. We must emit USE insns which | |
969 | reference the 6 input registers. Ordinarily they are not call used | |
970 | registers, but they are for _builtin_saveregs, so we must make this | |
971 | explicit. */ | |
972 | ||
973 | #define EXPAND_BUILTIN_SAVEREGS(ARGLIST) \ | |
974 | (emit_insn (gen_rtx (USE, VOIDmode, gen_rtx (REG, TImode, 24))), \ | |
975 | emit_insn (gen_rtx (USE, VOIDmode, gen_rtx (REG, DImode, 28))), \ | |
976 | expand_call (exp, target, ignore)) | |
977 | \f | |
978 | /* Addressing modes, and classification of registers for them. */ | |
979 | ||
980 | /* #define HAVE_POST_INCREMENT */ | |
981 | /* #define HAVE_POST_DECREMENT */ | |
982 | ||
983 | /* #define HAVE_PRE_DECREMENT */ | |
984 | /* #define HAVE_PRE_INCREMENT */ | |
985 | ||
986 | /* Macros to check register numbers against specific register classes. */ | |
987 | ||
988 | /* These assume that REGNO is a hard or pseudo reg number. | |
989 | They give nonzero only if REGNO is a hard reg of the suitable class | |
990 | or a pseudo reg currently allocated to a suitable hard reg. | |
991 | Since they use reg_renumber, they are safe only once reg_renumber | |
992 | has been allocated, which happens in local-alloc.c. */ | |
993 | ||
994 | #define REGNO_OK_FOR_INDEX_P(REGNO) \ | |
995 | (((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32) && (REGNO) != 0) | |
996 | #define REGNO_OK_FOR_BASE_P(REGNO) \ | |
997 | (((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32) && (REGNO) != 0) | |
998 | #define REGNO_OK_FOR_FP_P(REGNO) \ | |
999 | (((REGNO) ^ 0x20) < 32 \ | |
1000 | || (((REGNO) != 0) && (unsigned) (reg_renumber[REGNO] ^ 0x20) < 32)) | |
1001 | ||
1002 | /* Now macros that check whether X is a register and also, | |
1003 | strictly, whether it is in a specified class. | |
1004 | ||
1005 | These macros are specific to the SPARC, and may be used only | |
1006 | in code for printing assembler insns and in conditions for | |
1007 | define_optimization. */ | |
1008 | ||
1009 | /* 1 if X is an fp register. */ | |
1010 | ||
1011 | #define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X))) | |
1012 | \f | |
1013 | /* Maximum number of registers that can appear in a valid memory address. */ | |
1014 | ||
1015 | #define MAX_REGS_PER_ADDRESS 2 | |
1016 | ||
1017 | /* Recognize any constant value that is a valid address. */ | |
1018 | ||
1019 | #define CONSTANT_ADDRESS_P(X) (CONSTANT_P (X)) | |
1020 | ||
1021 | /* Nonzero if the constant value X is a legitimate general operand. | |
1022 | Anything can be made to work except floating point constants. */ | |
1023 | ||
1024 | #define LEGITIMATE_CONSTANT_P(X) \ | |
1025 | (GET_CODE (X) != CONST_DOUBLE || GET_MODE (X) == VOIDmode) | |
1026 | ||
1027 | /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx | |
1028 | and check its validity for a certain class. | |
1029 | We have two alternate definitions for each of them. | |
1030 | The usual definition accepts all pseudo regs; the other rejects | |
1031 | them unless they have been allocated suitable hard regs. | |
1032 | The symbol REG_OK_STRICT causes the latter definition to be used. | |
1033 | ||
1034 | Most source files want to accept pseudo regs in the hope that | |
1035 | they will get allocated to the class that the insn wants them to be in. | |
1036 | Source files for reload pass need to be strict. | |
1037 | After reload, it makes no difference, since pseudo regs have | |
1038 | been eliminated by then. */ | |
1039 | ||
1040 | /* Optional extra constraints for this machine. Borrowed from romp.h. | |
1041 | ||
1042 | For the SPARC, `Q' means that this is a memory operand but not a | |
1043 | symbolic memory operand. Note that an unassigned pseudo register | |
1044 | is such a memory operand. Needed because reload will generate | |
1045 | these things in insns and then not re-recognize the insns, causing | |
1046 | constrain_operands to fail. | |
1047 | ||
1048 | `R' handles the LO_SUM which can be an address for `Q'. | |
1049 | ||
1050 | `S' handles constraints for calls. */ | |
1051 | ||
1052 | #ifndef REG_OK_STRICT | |
1053 | ||
1054 | /* Nonzero if X is a hard reg that can be used as an index | |
1055 | or if it is a pseudo reg. */ | |
1056 | #define REG_OK_FOR_INDEX_P(X) (((unsigned) REGNO (X)) - 32 >= 32 && REGNO (X) != 0) | |
1057 | /* Nonzero if X is a hard reg that can be used as a base reg | |
1058 | or if it is a pseudo reg. */ | |
1059 | #define REG_OK_FOR_BASE_P(X) (((unsigned) REGNO (X)) - 32 >= 32 && REGNO (X) != 0) | |
1060 | ||
1061 | #define EXTRA_CONSTRAINT(OP, C) \ | |
1062 | ((C) == 'Q' ? \ | |
1063 | ((GET_CODE (OP) == MEM \ | |
1064 | && memory_address_p (GET_MODE (OP), XEXP (OP, 0)) \ | |
1065 | && ! symbolic_memory_operand (OP, VOIDmode))) \ | |
1066 | : ((C) == 'R' ? \ | |
1067 | (GET_CODE (OP) == LO_SUM \ | |
1068 | && GET_CODE (XEXP (OP, 0)) == REG \ | |
1069 | && REG_OK_FOR_BASE_P (XEXP (OP, 0))) \ | |
1070 | : ((C) == 'S' \ | |
1071 | ? CONSTANT_P (OP) || memory_address_p (Pmode, OP) : 0))) | |
1072 | ||
1073 | #else | |
1074 | ||
1075 | /* Nonzero if X is a hard reg that can be used as an index. */ | |
1076 | #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) | |
1077 | /* Nonzero if X is a hard reg that can be used as a base reg. */ | |
1078 | #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) | |
1079 | ||
1080 | #define EXTRA_CONSTRAINT(OP, C) \ | |
1081 | ((C) == 'Q' ? \ | |
1082 | (GET_CODE (OP) == REG ? \ | |
1083 | (REGNO (OP) >= FIRST_PSEUDO_REGISTER \ | |
1084 | && reg_renumber[REGNO (OP)] < 0) \ | |
1085 | : GET_CODE (OP) == MEM) \ | |
1086 | : ((C) == 'R' ? \ | |
1087 | (GET_CODE (OP) == LO_SUM \ | |
1088 | && GET_CODE (XEXP (OP, 0)) == REG \ | |
1089 | && REG_OK_FOR_BASE_P (XEXP (OP, 0))) \ | |
1090 | : ((C) == 'S' \ | |
1091 | ? (CONSTANT_P (OP) \ | |
1092 | || (GET_CODE (OP) == REG && reg_renumber[REGNO (OP)] > 0)\ | |
1093 | || strict_memory_address_p (Pmode, OP)) : 0))) | |
1094 | #endif | |
1095 | \f | |
1096 | /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression | |
1097 | that is a valid memory address for an instruction. | |
1098 | The MODE argument is the machine mode for the MEM expression | |
1099 | that wants to use this address. | |
1100 | ||
1101 | On SPARC, the actual legitimate addresses must be REG+REG or REG+SMALLINT | |
1102 | ordinarily. This changes a bit when generating PIC. | |
1103 | ||
1104 | If you change this, execute "rm explow.o recog.o reload.o". */ | |
1105 | ||
bec2e359 JW |
1106 | #define RTX_OK_FOR_BASE_P(X) \ |
1107 | ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \ | |
1108 | || (GET_CODE (X) == SUBREG \ | |
1109 | && GET_CODE (SUBREG_REG (X)) == REG \ | |
1110 | && REG_OK_FOR_BASE_P (SUBREG_REG (X)))) | |
1111 | ||
1112 | #define RTX_OK_FOR_INDEX_P(X) \ | |
1113 | ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \ | |
1114 | || (GET_CODE (X) == SUBREG \ | |
1115 | && GET_CODE (SUBREG_REG (X)) == REG \ | |
1116 | && REG_OK_FOR_INDEX_P (SUBREG_REG (X)))) | |
1117 | ||
1118 | #define RTX_OK_FOR_OFFSET_P(X) \ | |
1119 | (GET_CODE (X) == CONST_INT && INTVAL (X) >= -0x1000 && INTVAL (X) < 0x1000) | |
1120 | ||
1bb87f28 | 1121 | #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ |
bec2e359 JW |
1122 | { if (RTX_OK_FOR_BASE_P (X)) \ |
1123 | goto ADDR; \ | |
1bb87f28 JW |
1124 | else if (GET_CODE (X) == PLUS) \ |
1125 | { \ | |
bec2e359 JW |
1126 | register rtx op0 = XEXP (X, 0); \ |
1127 | register rtx op1 = XEXP (X, 1); \ | |
1128 | if (flag_pic && op0 == pic_offset_table_rtx) \ | |
1bb87f28 | 1129 | { \ |
bec2e359 | 1130 | if (RTX_OK_FOR_BASE_P (op1)) \ |
1bb87f28 JW |
1131 | goto ADDR; \ |
1132 | else if (flag_pic == 1 \ | |
bec2e359 JW |
1133 | && GET_CODE (op1) != REG \ |
1134 | && GET_CODE (op1) != LO_SUM \ | |
1135 | && GET_CODE (op1) != MEM) \ | |
1bb87f28 JW |
1136 | goto ADDR; \ |
1137 | } \ | |
bec2e359 | 1138 | else if (RTX_OK_FOR_BASE_P (op0)) \ |
1bb87f28 | 1139 | { \ |
bec2e359 JW |
1140 | if (RTX_OK_FOR_INDEX_P (op1) \ |
1141 | || RTX_OK_FOR_OFFSET_P (op1)) \ | |
1bb87f28 JW |
1142 | goto ADDR; \ |
1143 | } \ | |
bec2e359 | 1144 | else if (RTX_OK_FOR_BASE_P (op1)) \ |
1bb87f28 | 1145 | { \ |
bec2e359 JW |
1146 | if (RTX_OK_FOR_INDEX_P (op0) \ |
1147 | || RTX_OK_FOR_OFFSET_P (op0)) \ | |
1bb87f28 JW |
1148 | goto ADDR; \ |
1149 | } \ | |
1150 | } \ | |
bec2e359 JW |
1151 | else if (GET_CODE (X) == LO_SUM) \ |
1152 | { \ | |
1153 | register rtx op0 = XEXP (X, 0); \ | |
1154 | register rtx op1 = XEXP (X, 1); \ | |
1155 | if (RTX_OK_FOR_BASE_P (op0) \ | |
1156 | && CONSTANT_P (op1)) \ | |
1157 | goto ADDR; \ | |
1158 | } \ | |
1bb87f28 JW |
1159 | else if (GET_CODE (X) == CONST_INT && SMALL_INT (X)) \ |
1160 | goto ADDR; \ | |
1161 | } | |
1162 | \f | |
1163 | /* Try machine-dependent ways of modifying an illegitimate address | |
1164 | to be legitimate. If we find one, return the new, valid address. | |
1165 | This macro is used in only one place: `memory_address' in explow.c. | |
1166 | ||
1167 | OLDX is the address as it was before break_out_memory_refs was called. | |
1168 | In some cases it is useful to look at this to decide what needs to be done. | |
1169 | ||
1170 | MODE and WIN are passed so that this macro can use | |
1171 | GO_IF_LEGITIMATE_ADDRESS. | |
1172 | ||
1173 | It is always safe for this macro to do nothing. It exists to recognize | |
1174 | opportunities to optimize the output. */ | |
1175 | ||
1176 | /* On SPARC, change REG+N into REG+REG, and REG+(X*Y) into REG+REG. */ | |
1177 | extern struct rtx_def *legitimize_pic_address (); | |
1178 | #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \ | |
1179 | { rtx sparc_x = (X); \ | |
1180 | if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == MULT) \ | |
1181 | (X) = gen_rtx (PLUS, Pmode, XEXP (X, 1), \ | |
1182 | force_operand (XEXP (X, 0), 0)); \ | |
1183 | if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 1)) == MULT) \ | |
1184 | (X) = gen_rtx (PLUS, Pmode, XEXP (X, 0), \ | |
1185 | force_operand (XEXP (X, 1), 0)); \ | |
1186 | if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == PLUS) \ | |
1187 | (X) = gen_rtx (PLUS, Pmode, force_operand (XEXP (X, 0), 0),\ | |
1188 | XEXP (X, 1)); \ | |
1189 | if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 1)) == PLUS) \ | |
1190 | (X) = gen_rtx (PLUS, Pmode, XEXP (X, 0), \ | |
1191 | force_operand (XEXP (X, 1), 0)); \ | |
1192 | if (sparc_x != (X) && memory_address_p (MODE, X)) \ | |
1193 | goto WIN; \ | |
1194 | if (flag_pic) (X) = legitimize_pic_address (X, MODE, 0, 0); \ | |
1195 | else if (GET_CODE (X) == PLUS && CONSTANT_ADDRESS_P (XEXP (X, 1))) \ | |
1196 | (X) = gen_rtx (PLUS, Pmode, XEXP (X, 0), \ | |
1197 | copy_to_mode_reg (Pmode, XEXP (X, 1))); \ | |
1198 | else if (GET_CODE (X) == PLUS && CONSTANT_ADDRESS_P (XEXP (X, 0))) \ | |
1199 | (X) = gen_rtx (PLUS, Pmode, XEXP (X, 1), \ | |
1200 | copy_to_mode_reg (Pmode, XEXP (X, 0))); \ | |
1201 | else if (GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == CONST \ | |
1202 | || GET_CODE (X) == LABEL_REF) \ | |
1203 | (X) = gen_rtx (LO_SUM, Pmode, \ | |
1204 | copy_to_mode_reg (Pmode, gen_rtx (HIGH, Pmode, X)), X); \ | |
1205 | if (memory_address_p (MODE, X)) \ | |
1206 | goto WIN; } | |
1207 | ||
1208 | /* Go to LABEL if ADDR (a legitimate address expression) | |
1209 | has an effect that depends on the machine mode it is used for. | |
1210 | On the SPARC this is never true. */ | |
1211 | ||
1212 | #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) | |
1213 | \f | |
1214 | /* Specify the machine mode that this machine uses | |
1215 | for the index in the tablejump instruction. */ | |
1216 | #define CASE_VECTOR_MODE SImode | |
1217 | ||
1218 | /* Define this if the tablejump instruction expects the table | |
1219 | to contain offsets from the address of the table. | |
1220 | Do not define this if the table should contain absolute addresses. */ | |
1221 | /* #define CASE_VECTOR_PC_RELATIVE */ | |
1222 | ||
1223 | /* Specify the tree operation to be used to convert reals to integers. */ | |
1224 | #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR | |
1225 | ||
1226 | /* This is the kind of divide that is easiest to do in the general case. */ | |
1227 | #define EASY_DIV_EXPR TRUNC_DIV_EXPR | |
1228 | ||
1229 | /* Define this as 1 if `char' should by default be signed; else as 0. */ | |
1230 | #define DEFAULT_SIGNED_CHAR 1 | |
1231 | ||
1232 | /* Max number of bytes we can move from memory to memory | |
1233 | in one reasonably fast instruction. */ | |
2eef2ef1 | 1234 | #define MOVE_MAX 8 |
1bb87f28 JW |
1235 | |
1236 | /* Define if normal loads of shorter-than-word items from memory clears | |
1237 | the rest of the bigs in the register. */ | |
1238 | #define BYTE_LOADS_ZERO_EXTEND | |
1239 | ||
1240 | /* Nonzero if access to memory by bytes is slow and undesirable. | |
1241 | For RISC chips, it means that access to memory by bytes is no | |
1242 | better than access by words when possible, so grab a whole word | |
1243 | and maybe make use of that. */ | |
1244 | #define SLOW_BYTE_ACCESS 1 | |
1245 | ||
1246 | /* We assume that the store-condition-codes instructions store 0 for false | |
1247 | and some other value for true. This is the value stored for true. */ | |
1248 | ||
1249 | #define STORE_FLAG_VALUE 1 | |
1250 | ||
1251 | /* When a prototype says `char' or `short', really pass an `int'. */ | |
1252 | #define PROMOTE_PROTOTYPES | |
1253 | ||
1254 | /* Define if shifts truncate the shift count | |
1255 | which implies one can omit a sign-extension or zero-extension | |
1256 | of a shift count. */ | |
1257 | #define SHIFT_COUNT_TRUNCATED | |
1258 | ||
1259 | /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits | |
1260 | is done just by pretending it is already truncated. */ | |
1261 | #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 | |
1262 | ||
1263 | /* Specify the machine mode that pointers have. | |
1264 | After generation of rtl, the compiler makes no further distinction | |
1265 | between pointers and any other objects of this machine mode. */ | |
1266 | #define Pmode SImode | |
1267 | ||
b4ac57ab RS |
1268 | /* Generate calls to memcpy, memcmp and memset. */ |
1269 | #define TARGET_MEM_FUNCTIONS | |
1270 | ||
1bb87f28 JW |
1271 | /* Add any extra modes needed to represent the condition code. |
1272 | ||
1273 | On the Sparc, we have a "no-overflow" mode which is used when an add or | |
1274 | subtract insn is used to set the condition code. Different branches are | |
1275 | used in this case for some operations. | |
1276 | ||
4d449554 JW |
1277 | We also have two modes to indicate that the relevant condition code is |
1278 | in the floating-point condition code register. One for comparisons which | |
1279 | will generate an exception if the result is unordered (CCFPEmode) and | |
1280 | one for comparisons which will never trap (CCFPmode). This really should | |
1281 | be a separate register, but we don't want to go to 65 registers. */ | |
1282 | #define EXTRA_CC_MODES CC_NOOVmode, CCFPmode, CCFPEmode | |
1bb87f28 JW |
1283 | |
1284 | /* Define the names for the modes specified above. */ | |
4d449554 | 1285 | #define EXTRA_CC_NAMES "CC_NOOV", "CCFP", "CCFPE" |
1bb87f28 JW |
1286 | |
1287 | /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, | |
4d449554 JW |
1288 | return the mode to be used for the comparison. For floating-point, |
1289 | CCFP[E]mode is used. CC_NOOVmode should be used when the first operand is a | |
1bb87f28 JW |
1290 | PLUS, MINUS, or NEG. CCmode should be used when no special processing is |
1291 | needed. */ | |
1292 | #define SELECT_CC_MODE(OP,X) \ | |
4d449554 JW |
1293 | (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \ |
1294 | ? ((OP == EQ || OP == NE) ? CCFPmode : CCFPEmode) \ | |
1295 | : ((GET_CODE (X) == PLUS || GET_CODE (X) == MINUS || GET_CODE (X) == NEG) \ | |
1296 | ? CC_NOOVmode : CCmode)) | |
1bb87f28 JW |
1297 | |
1298 | /* A function address in a call instruction | |
1299 | is a byte address (for indexing purposes) | |
1300 | so give the MEM rtx a byte's mode. */ | |
1301 | #define FUNCTION_MODE SImode | |
1302 | ||
1303 | /* Define this if addresses of constant functions | |
1304 | shouldn't be put through pseudo regs where they can be cse'd. | |
1305 | Desirable on machines where ordinary constants are expensive | |
1306 | but a CALL with constant address is cheap. */ | |
1307 | #define NO_FUNCTION_CSE | |
1308 | ||
1309 | /* alloca should avoid clobbering the old register save area. */ | |
1310 | #define SETJMP_VIA_SAVE_AREA | |
1311 | ||
1312 | /* Define subroutines to call to handle multiply and divide. | |
1313 | Use the subroutines that Sun's library provides. | |
1314 | The `*' prevents an underscore from being prepended by the compiler. */ | |
1315 | ||
1316 | #define DIVSI3_LIBCALL "*.div" | |
1317 | #define UDIVSI3_LIBCALL "*.udiv" | |
1318 | #define MODSI3_LIBCALL "*.rem" | |
1319 | #define UMODSI3_LIBCALL "*.urem" | |
1320 | /* .umul is a little faster than .mul. */ | |
1321 | #define MULSI3_LIBCALL "*.umul" | |
1322 | ||
1323 | /* Compute the cost of computing a constant rtl expression RTX | |
1324 | whose rtx-code is CODE. The body of this macro is a portion | |
1325 | of a switch statement. If the code is computed here, | |
1326 | return it with a return statement. Otherwise, break from the switch. */ | |
1327 | ||
3bb22aee | 1328 | #define CONST_COSTS(RTX,CODE,OUTER_CODE) \ |
1bb87f28 JW |
1329 | case CONST_INT: \ |
1330 | if (INTVAL (RTX) == 0) \ | |
1331 | return 0; \ | |
1332 | if (INTVAL (RTX) < 0x1000 && INTVAL (RTX) >= -0x1000) \ | |
1333 | return 1; \ | |
1334 | case HIGH: \ | |
1335 | return 2; \ | |
1336 | case CONST: \ | |
1337 | case LABEL_REF: \ | |
1338 | case SYMBOL_REF: \ | |
1339 | return 4; \ | |
1340 | case CONST_DOUBLE: \ | |
1341 | if (GET_MODE (RTX) == DImode) \ | |
1342 | if ((XINT (RTX, 3) == 0 \ | |
1343 | && (unsigned) XINT (RTX, 2) < 0x1000) \ | |
1344 | || (XINT (RTX, 3) == -1 \ | |
1345 | && XINT (RTX, 2) < 0 \ | |
1346 | && XINT (RTX, 2) >= -0x1000)) \ | |
1347 | return 1; \ | |
1348 | return 8; | |
1349 | ||
1350 | /* SPARC offers addressing modes which are "as cheap as a register". | |
1351 | See sparc.c (or gcc.texinfo) for details. */ | |
1352 | ||
1353 | #define ADDRESS_COST(RTX) \ | |
1354 | (GET_CODE (RTX) == REG ? 1 : sparc_address_cost (RTX)) | |
1355 | ||
1356 | /* Compute extra cost of moving data between one register class | |
1357 | and another. */ | |
1358 | #define REGISTER_MOVE_COST(CLASS1, CLASS2) \ | |
1359 | (((CLASS1 == FP_REGS && CLASS2 == GENERAL_REGS) \ | |
1360 | || (CLASS1 == GENERAL_REGS && CLASS2 == FP_REGS)) ? 6 : 2) | |
1361 | ||
1362 | /* Provide the costs of a rtl expression. This is in the body of a | |
1363 | switch on CODE. The purpose for the cost of MULT is to encourage | |
1364 | `synth_mult' to find a synthetic multiply when reasonable. | |
1365 | ||
1366 | If we need more than 12 insns to do a multiply, then go out-of-line, | |
1367 | since the call overhead will be < 10% of the cost of the multiply. */ | |
1368 | ||
3bb22aee | 1369 | #define RTX_COSTS(X,CODE,OUTER_CODE) \ |
1bb87f28 JW |
1370 | case MULT: \ |
1371 | return COSTS_N_INSNS (25); \ | |
1372 | case DIV: \ | |
1373 | case UDIV: \ | |
1374 | case MOD: \ | |
1375 | case UMOD: \ | |
1376 | return COSTS_N_INSNS (20); \ | |
1377 | /* Make FLOAT more expensive than CONST_DOUBLE, \ | |
1378 | so that cse will favor the latter. */ \ | |
1379 | case FLOAT: \ | |
1380 | return 19; | |
1381 | ||
1382 | /* Conditional branches with empty delay slots have a length of two. */ | |
1383 | #define ADJUST_INSN_LENGTH(INSN, LENGTH) \ | |
1384 | if (GET_CODE (INSN) == CALL_INSN \ | |
1385 | || (GET_CODE (INSN) == JUMP_INSN && ! simplejump_p (insn))) \ | |
1386 | LENGTH += 1; | |
1387 | \f | |
1388 | /* Control the assembler format that we output. */ | |
1389 | ||
1390 | /* Output at beginning of assembler file. */ | |
1391 | ||
1392 | #define ASM_FILE_START(file) | |
1393 | ||
1394 | /* Output to assembler file text saying following lines | |
1395 | may contain character constants, extra white space, comments, etc. */ | |
1396 | ||
1397 | #define ASM_APP_ON "" | |
1398 | ||
1399 | /* Output to assembler file text saying following lines | |
1400 | no longer contain unusual constructs. */ | |
1401 | ||
1402 | #define ASM_APP_OFF "" | |
1403 | ||
1404 | /* Output before read-only data. */ | |
1405 | ||
1406 | #define TEXT_SECTION_ASM_OP ".text" | |
1407 | ||
1408 | /* Output before writable data. */ | |
1409 | ||
1410 | #define DATA_SECTION_ASM_OP ".data" | |
1411 | ||
1412 | /* How to refer to registers in assembler output. | |
1413 | This sequence is indexed by compiler's hard-register-number (see above). */ | |
1414 | ||
1415 | #define REGISTER_NAMES \ | |
1416 | {"%g0", "%g1", "%g2", "%g3", "%g4", "%g5", "%g6", "%g7", \ | |
1417 | "%o0", "%o1", "%o2", "%o3", "%o4", "%o5", "%sp", "%o7", \ | |
1418 | "%l0", "%l1", "%l2", "%l3", "%l4", "%l5", "%l6", "%l7", \ | |
1419 | "%i0", "%i1", "%i2", "%i3", "%i4", "%i5", "%fp", "%i7", \ | |
1420 | "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7", \ | |
1421 | "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15", \ | |
1422 | "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23", \ | |
1423 | "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31"} | |
1424 | ||
ea3fa5f7 JW |
1425 | /* Define additional names for use in asm clobbers and asm declarations. |
1426 | ||
1427 | We define the fake Condition Code register as an alias for reg 0 (which | |
1428 | is our `condition code' register), so that condition codes can easily | |
1429 | be clobbered by an asm. No such register actually exists. Condition | |
1430 | codes are partly stored in the PSR and partly in the FSR. */ | |
1431 | ||
0eb9f40e | 1432 | #define ADDITIONAL_REGISTER_NAMES {"ccr", 0, "cc", 0} |
ea3fa5f7 | 1433 | |
1bb87f28 JW |
1434 | /* How to renumber registers for dbx and gdb. */ |
1435 | ||
1436 | #define DBX_REGISTER_NUMBER(REGNO) (REGNO) | |
1437 | ||
1438 | /* On Sun 4, this limit is 2048. We use 1500 to be safe, | |
1439 | since the length can run past this up to a continuation point. */ | |
1440 | #define DBX_CONTIN_LENGTH 1500 | |
1441 | ||
1442 | /* This is how to output a note to DBX telling it the line number | |
1443 | to which the following sequence of instructions corresponds. | |
1444 | ||
1445 | This is needed for SunOS 4.0, and should not hurt for 3.2 | |
1446 | versions either. */ | |
1447 | #define ASM_OUTPUT_SOURCE_LINE(file, line) \ | |
1448 | { static int sym_lineno = 1; \ | |
1449 | fprintf (file, ".stabn 68,0,%d,LM%d\nLM%d:\n", \ | |
1450 | line, sym_lineno, sym_lineno); \ | |
1451 | sym_lineno += 1; } | |
1452 | ||
1453 | /* This is how to output the definition of a user-level label named NAME, | |
1454 | such as the label on a static function or variable NAME. */ | |
1455 | ||
1456 | #define ASM_OUTPUT_LABEL(FILE,NAME) \ | |
1457 | do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0) | |
1458 | ||
1459 | /* This is how to output a command to make the user-level label named NAME | |
1460 | defined for reference from other files. */ | |
1461 | ||
1462 | #define ASM_GLOBALIZE_LABEL(FILE,NAME) \ | |
1463 | do { fputs ("\t.global ", FILE); assemble_name (FILE, NAME); fputs ("\n", FILE);} while (0) | |
1464 | ||
1465 | /* This is how to output a reference to a user-level label named NAME. | |
1466 | `assemble_name' uses this. */ | |
1467 | ||
1468 | #define ASM_OUTPUT_LABELREF(FILE,NAME) \ | |
1469 | fprintf (FILE, "_%s", NAME) | |
1470 | ||
1471 | /* This is how to output an internal numbered label where | |
1472 | PREFIX is the class of label and NUM is the number within the class. */ | |
1473 | ||
1474 | #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \ | |
1475 | fprintf (FILE, "%s%d:\n", PREFIX, NUM) | |
1476 | ||
1477 | /* This is how to store into the string LABEL | |
1478 | the symbol_ref name of an internal numbered label where | |
1479 | PREFIX is the class of label and NUM is the number within the class. | |
1480 | This is suitable for output with `assemble_name'. */ | |
1481 | ||
1482 | #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \ | |
1483 | sprintf (LABEL, "*%s%d", PREFIX, NUM) | |
1484 | ||
1485 | /* This is how to output an assembler line defining a `double' constant. */ | |
1486 | ||
b1fc14e5 RS |
1487 | /* Assemblers (both gas 1.35 and as in 4.0.3) |
1488 | seem to treat -0.0 as if it were 0.0. | |
1489 | They reject 99e9999, but accept inf. */ | |
1bb87f28 JW |
1490 | #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \ |
1491 | { \ | |
1492 | if (REAL_VALUE_ISINF (VALUE)) \ | |
b1fc14e5 RS |
1493 | fprintf (FILE, "\t.double 0r%sinf\n", (VALUE) > 0 ? "" : "-"); \ |
1494 | else if (REAL_VALUE_ISNAN (VALUE) \ | |
1495 | || REAL_VALUE_MINUS_ZERO (VALUE)) \ | |
1bb87f28 JW |
1496 | { \ |
1497 | union { double d; long l[2];} t; \ | |
1498 | t.d = (VALUE); \ | |
1499 | fprintf (FILE, "\t.word 0x%lx\n\t.word 0x%lx\n", t.l[0], t.l[1]); \ | |
1500 | } \ | |
1501 | else \ | |
1502 | fprintf (FILE, "\t.double 0r%.17g\n", VALUE); \ | |
1503 | } | |
1504 | ||
1505 | /* This is how to output an assembler line defining a `float' constant. */ | |
1506 | ||
1507 | #define ASM_OUTPUT_FLOAT(FILE,VALUE) \ | |
1508 | { \ | |
1509 | if (REAL_VALUE_ISINF (VALUE)) \ | |
b1fc14e5 RS |
1510 | fprintf (FILE, "\t.single 0r%sinf\n", (VALUE) > 0 ? "" : "-"); \ |
1511 | else if (REAL_VALUE_ISNAN (VALUE) \ | |
1512 | || REAL_VALUE_MINUS_ZERO (VALUE)) \ | |
1bb87f28 JW |
1513 | { \ |
1514 | union { float f; long l;} t; \ | |
1515 | t.f = (VALUE); \ | |
1516 | fprintf (FILE, "\t.word 0x%lx\n", t.l); \ | |
1517 | } \ | |
1518 | else \ | |
1519 | fprintf (FILE, "\t.single 0r%.9g\n", VALUE); \ | |
1520 | } | |
1521 | ||
1522 | /* This is how to output an assembler line defining an `int' constant. */ | |
1523 | ||
1524 | #define ASM_OUTPUT_INT(FILE,VALUE) \ | |
1525 | ( fprintf (FILE, "\t.word "), \ | |
1526 | output_addr_const (FILE, (VALUE)), \ | |
1527 | fprintf (FILE, "\n")) | |
1528 | ||
1529 | /* This is how to output an assembler line defining a DImode constant. */ | |
1530 | #define ASM_OUTPUT_DOUBLE_INT(FILE,VALUE) \ | |
1531 | output_double_int (FILE, VALUE) | |
1532 | ||
1533 | /* Likewise for `char' and `short' constants. */ | |
1534 | ||
1535 | #define ASM_OUTPUT_SHORT(FILE,VALUE) \ | |
1536 | ( fprintf (FILE, "\t.half "), \ | |
1537 | output_addr_const (FILE, (VALUE)), \ | |
1538 | fprintf (FILE, "\n")) | |
1539 | ||
1540 | #define ASM_OUTPUT_CHAR(FILE,VALUE) \ | |
1541 | ( fprintf (FILE, "\t.byte "), \ | |
1542 | output_addr_const (FILE, (VALUE)), \ | |
1543 | fprintf (FILE, "\n")) | |
1544 | ||
1545 | /* This is how to output an assembler line for a numeric constant byte. */ | |
1546 | ||
1547 | #define ASM_OUTPUT_BYTE(FILE,VALUE) \ | |
1548 | fprintf (FILE, "\t.byte 0x%x\n", (VALUE)) | |
1549 | ||
1550 | /* This is how to output an element of a case-vector that is absolute. */ | |
1551 | ||
1552 | #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ | |
4b69d2a3 RS |
1553 | do { \ |
1554 | char label[30]; \ | |
1555 | ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \ | |
1556 | fprintf (FILE, "\t.word\t"); \ | |
1557 | assemble_name (FILE, label); \ | |
1558 | fprintf (FILE, "\n"); \ | |
1559 | } while (0) | |
1bb87f28 JW |
1560 | |
1561 | /* This is how to output an element of a case-vector that is relative. | |
1562 | (SPARC uses such vectors only when generating PIC.) */ | |
1563 | ||
4b69d2a3 RS |
1564 | #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) \ |
1565 | do { \ | |
1566 | char label[30]; \ | |
1567 | ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \ | |
1568 | fprintf (FILE, "\t.word\t"); \ | |
1569 | assemble_name (FILE, label); \ | |
1570 | fprintf (FILE, "-1b\n"); \ | |
1571 | } while (0) | |
1bb87f28 JW |
1572 | |
1573 | /* This is how to output an assembler line | |
1574 | that says to advance the location counter | |
1575 | to a multiple of 2**LOG bytes. */ | |
1576 | ||
1577 | #define ASM_OUTPUT_ALIGN(FILE,LOG) \ | |
1578 | if ((LOG) != 0) \ | |
1579 | fprintf (FILE, "\t.align %d\n", (1<<(LOG))) | |
1580 | ||
1581 | #define ASM_OUTPUT_SKIP(FILE,SIZE) \ | |
1582 | fprintf (FILE, "\t.skip %u\n", (SIZE)) | |
1583 | ||
1584 | /* This says how to output an assembler line | |
1585 | to define a global common symbol. */ | |
1586 | ||
1587 | #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \ | |
1588 | ( fputs ("\t.global ", (FILE)), \ | |
1589 | assemble_name ((FILE), (NAME)), \ | |
1590 | fputs ("\n\t.common ", (FILE)), \ | |
1591 | assemble_name ((FILE), (NAME)), \ | |
1592 | fprintf ((FILE), ",%u,\"bss\"\n", (ROUNDED))) | |
1593 | ||
1594 | /* This says how to output an assembler line | |
1595 | to define a local common symbol. */ | |
1596 | ||
1597 | #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \ | |
1598 | ( fputs ("\n\t.reserve ", (FILE)), \ | |
1599 | assemble_name ((FILE), (NAME)), \ | |
1600 | fprintf ((FILE), ",%u,\"bss\"\n", (ROUNDED))) | |
1601 | ||
1602 | /* Store in OUTPUT a string (made with alloca) containing | |
1603 | an assembler-name for a local static variable named NAME. | |
1604 | LABELNO is an integer which is different for each call. */ | |
1605 | ||
1606 | #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \ | |
1607 | ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \ | |
1608 | sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO))) | |
1609 | ||
1610 | /* Define the parentheses used to group arithmetic operations | |
1611 | in assembler code. */ | |
1612 | ||
1613 | #define ASM_OPEN_PAREN "(" | |
1614 | #define ASM_CLOSE_PAREN ")" | |
1615 | ||
1616 | /* Define results of standard character escape sequences. */ | |
1617 | #define TARGET_BELL 007 | |
1618 | #define TARGET_BS 010 | |
1619 | #define TARGET_TAB 011 | |
1620 | #define TARGET_NEWLINE 012 | |
1621 | #define TARGET_VT 013 | |
1622 | #define TARGET_FF 014 | |
1623 | #define TARGET_CR 015 | |
1624 | ||
1625 | #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \ | |
1626 | ((CHAR) == '@' || (CHAR) == '#' || (CHAR) == '*' || (CHAR) == '^') | |
1627 | ||
1628 | /* Print operand X (an rtx) in assembler syntax to file FILE. | |
1629 | CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. | |
1630 | For `%' followed by punctuation, CODE is the punctuation and X is null. */ | |
1631 | ||
1632 | #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE) | |
1633 | ||
1634 | /* Print a memory address as an operand to reference that memory location. */ | |
1635 | ||
1636 | #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \ | |
1637 | { register rtx base, index = 0; \ | |
1638 | int offset = 0; \ | |
1639 | register rtx addr = ADDR; \ | |
1640 | if (GET_CODE (addr) == REG) \ | |
1641 | fputs (reg_names[REGNO (addr)], FILE); \ | |
1642 | else if (GET_CODE (addr) == PLUS) \ | |
1643 | { \ | |
1644 | if (GET_CODE (XEXP (addr, 0)) == CONST_INT) \ | |
1645 | offset = INTVAL (XEXP (addr, 0)), base = XEXP (addr, 1);\ | |
1646 | else if (GET_CODE (XEXP (addr, 1)) == CONST_INT) \ | |
1647 | offset = INTVAL (XEXP (addr, 1)), base = XEXP (addr, 0);\ | |
1648 | else \ | |
1649 | base = XEXP (addr, 0), index = XEXP (addr, 1); \ | |
1650 | fputs (reg_names[REGNO (base)], FILE); \ | |
1651 | if (index == 0) \ | |
1652 | fprintf (FILE, "%+d", offset); \ | |
1653 | else if (GET_CODE (index) == REG) \ | |
1654 | fprintf (FILE, "+%s", reg_names[REGNO (index)]); \ | |
1655 | else if (GET_CODE (index) == SYMBOL_REF) \ | |
1656 | fputc ('+', FILE), output_addr_const (FILE, index); \ | |
1657 | else abort (); \ | |
1658 | } \ | |
1659 | else if (GET_CODE (addr) == MINUS \ | |
1660 | && GET_CODE (XEXP (addr, 1)) == LABEL_REF) \ | |
1661 | { \ | |
1662 | output_addr_const (FILE, XEXP (addr, 0)); \ | |
1663 | fputs ("-(", FILE); \ | |
1664 | output_addr_const (FILE, XEXP (addr, 1)); \ | |
1665 | fputs ("-.)", FILE); \ | |
1666 | } \ | |
1667 | else if (GET_CODE (addr) == LO_SUM) \ | |
1668 | { \ | |
1669 | output_operand (XEXP (addr, 0), 0); \ | |
1670 | fputs ("+%lo(", FILE); \ | |
1671 | output_address (XEXP (addr, 1)); \ | |
1672 | fputc (')', FILE); \ | |
1673 | } \ | |
1674 | else if (flag_pic && GET_CODE (addr) == CONST \ | |
1675 | && GET_CODE (XEXP (addr, 0)) == MINUS \ | |
1676 | && GET_CODE (XEXP (XEXP (addr, 0), 1)) == CONST \ | |
1677 | && GET_CODE (XEXP (XEXP (XEXP (addr, 0), 1), 0)) == MINUS \ | |
1678 | && XEXP (XEXP (XEXP (XEXP (addr, 0), 1), 0), 1) == pc_rtx) \ | |
1679 | { \ | |
1680 | addr = XEXP (addr, 0); \ | |
1681 | output_addr_const (FILE, XEXP (addr, 0)); \ | |
1682 | /* Group the args of the second CONST in parenthesis. */ \ | |
1683 | fputs ("-(", FILE); \ | |
1684 | /* Skip past the second CONST--it does nothing for us. */\ | |
1685 | output_addr_const (FILE, XEXP (XEXP (addr, 1), 0)); \ | |
1686 | /* Close the parenthesis. */ \ | |
1687 | fputc (')', FILE); \ | |
1688 | } \ | |
1689 | else \ | |
1690 | { \ | |
1691 | output_addr_const (FILE, addr); \ | |
1692 | } \ | |
1693 | } | |
1694 | ||
1695 | /* Declare functions defined in sparc.c and used in templates. */ | |
1696 | ||
1697 | extern char *singlemove_string (); | |
1698 | extern char *output_move_double (); | |
795068a4 | 1699 | extern char *output_move_quad (); |
1bb87f28 | 1700 | extern char *output_fp_move_double (); |
795068a4 | 1701 | extern char *output_fp_move_quad (); |
1bb87f28 JW |
1702 | extern char *output_block_move (); |
1703 | extern char *output_scc_insn (); | |
1704 | extern char *output_cbranch (); | |
1705 | extern char *output_return (); | |
1706 | extern char *output_floatsisf2 (); | |
1707 | extern char *output_floatsidf2 (); | |
795068a4 | 1708 | extern char *output_floatsitf2 (); |
1bb87f28 JW |
1709 | |
1710 | /* Defined in flags.h, but insn-emit.c does not include flags.h. */ | |
1711 | ||
1712 | extern int flag_pic; |