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ab835497 1/* Subroutines for insn-output.c for Sun SPARC.
b73bf65f 2 Copyright (C) 1987, 88, 89, 92-98, 1999 Free Software Foundation, Inc.
ab835497 3 Contributed by Michael Tiemann (tiemann@cygnus.com)
61a55e8b
DE		 4 64 bit SPARC V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
5 at Cygnus Support.
ab835497
RK		 6
7This file is part of GNU CC.
8
9GNU CC is free software; you can redistribute it and/or modify
10it under the terms of the GNU General Public License as published by
11the Free Software Foundation; either version 2, or (at your option)
12any later version.
13
14GNU CC is distributed in the hope that it will be useful,
15but WITHOUT ANY WARRANTY; without even the implied warranty of
16MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17GNU General Public License for more details.
18
19You should have received a copy of the GNU General Public License
20along with GNU CC; see the file COPYING. If not, write to
c15c9075
RK		 21the Free Software Foundation, 59 Temple Place - Suite 330,
22Boston, MA 02111-1307, USA. */
ab835497 23
ab835497 24#include "config.h"
284d86e9 25#include "system.h"
210aa14a 26#include "tree.h"
ab835497
RK		 27#include "rtl.h"
28#include "regs.h"
29#include "hard-reg-set.h"
30#include "real.h"
31#include "insn-config.h"
32#include "conditions.h"
33#include "insn-flags.h"
34#include "output.h"
35#include "insn-attr.h"
36#include "flags.h"
49ad7cfa 37#include "function.h"
ab835497
RK		 38#include "expr.h"
39#include "recog.h"
487a6e06 40#include "toplev.h"
d07d525a 41#include "ggc.h"
b1474bb7 42#include "tm_p.h"
ab835497 43
61a55e8b
DE		 44/* 1 if the caller has placed an "unimp" insn immediately after the call.
45 This is used in v8 code when calling a function that returns a structure.
06b967f9
RK		 46 v9 doesn't have this. Be careful to have this test be the same as that
47 used on the call. */
48
49#define SKIP_CALLERS_UNIMP_P \
50(!TARGET_ARCH64 && current_function_returns_struct \
51 && ! integer_zerop (DECL_SIZE (DECL_RESULT (current_function_decl))) \
52 && (TREE_CODE (DECL_SIZE (DECL_RESULT (current_function_decl))) \
53 == INTEGER_CST))
61a55e8b 54
ab835497
RK		 55/* Global variables for machine-dependent things. */
56
61a55e8b
DE		 57/* Size of frame. Need to know this to emit return insns from leaf procedures.
58 ACTUAL_FSIZE is set by compute_frame_size() which is called during the
59 reload pass. This is important as the value is later used in insn
60 scheduling (to see what can go in a delay slot).
61 APPARENT_FSIZE is the size of the stack less the register save area and less
62 the outgoing argument area. It is used when saving call preserved regs. */
63static int apparent_fsize;
64static int actual_fsize;
65
ab835497
RK		 66/* Save the operands last given to a compare for use when we
67 generate a scc or bcc insn. */
68
69rtx sparc_compare_op0, sparc_compare_op1;
70
71/* We may need an epilogue if we spill too many registers.
72 If this is non-zero, then we branch here for the epilogue. */
73static rtx leaf_label;
74
75#ifdef LEAF_REGISTERS
76
77/* Vector to say how input registers are mapped to output
78 registers. FRAME_POINTER_REGNUM cannot be remapped by
79 this function to eliminate it. You must use -fomit-frame-pointer
80 to get that. */
81char leaf_reg_remap[] =
82{ 0, 1, 2, 3, 4, 5, 6, 7,
83 -1, -1, -1, -1, -1, -1, 14, -1,
84 -1, -1, -1, -1, -1, -1, -1, -1,
85 8, 9, 10, 11, 12, 13, -1, 15,
86
87 32, 33, 34, 35, 36, 37, 38, 39,
88 40, 41, 42, 43, 44, 45, 46, 47,
89 48, 49, 50, 51, 52, 53, 54, 55,
61a55e8b
DE		 90 56, 57, 58, 59, 60, 61, 62, 63,
91 64, 65, 66, 67, 68, 69, 70, 71,
92 72, 73, 74, 75, 76, 77, 78, 79,
93 80, 81, 82, 83, 84, 85, 86, 87,
94 88, 89, 90, 91, 92, 93, 94, 95,
c4ce6853 95 96, 97, 98, 99, 100};
ab835497 96
6a4bb1fa 97#endif
ab835497 98
ab835497
RK		 99/* Name of where we pretend to think the frame pointer points.
100 Normally, this is "%fp", but if we are in a leaf procedure,
61a55e8b
DE		 101 this is "%sp+something". We record "something" separately as it may be
102 too big for reg+constant addressing. */
103
3bb5de61 104static const char *frame_base_name;
61a55e8b 105static int frame_base_offset;
ab835497 106
c85f7c16 107static rtx pic_setup_code PROTO((void));
c85f7c16 108static void sparc_init_modes PROTO((void));
3bb5de61 109static int save_regs PROTO((FILE *, int, int, const char *,
c85f7c16 110 int, int, int));
3bb5de61
KG		 111static int restore_regs PROTO((FILE *, int, int, const char *, int, int));
112static void build_big_number PROTO((FILE *, int, const char *));
5e9defae 113static int function_arg_slotno PROTO((const CUMULATIVE_ARGS *,
c85f7c16
JL		 114 enum machine_mode, tree, int, int,
115 int *, int *));
8947065c
RH		 116
117static int supersparc_adjust_cost PROTO((rtx, rtx, rtx, int));
118static int hypersparc_adjust_cost PROTO((rtx, rtx, rtx, int));
119static int ultrasparc_adjust_cost PROTO((rtx, rtx, rtx, int));
120
e0d80184
DM		 121static void sparc_output_addr_vec PROTO((rtx));
122static void sparc_output_addr_diff_vec PROTO((rtx));
123static void sparc_output_deferred_case_vectors PROTO((void));
d07d525a
MM		 124static void sparc_add_gc_roots PROTO ((void));
125static void mark_ultrasparc_pipeline_state PROTO ((void *));
b1474bb7
KG		 126static int check_return_regs PROTO ((rtx));
127static void epilogue_renumber PROTO ((rtx *));
128static int ultra_cmove_results_ready_p PROTO ((rtx));
129static int ultra_fpmode_conflict_exists PROTO ((enum machine_mode));
130static rtx *ultra_find_type PROTO ((int, rtx *, int));
131static void ultra_build_types_avail PROTO ((rtx *, int));
132static void ultra_flush_pipeline PROTO ((void));
133static void ultra_rescan_pipeline_state PROTO ((rtx *, int));
134static int set_extends PROTO ((rtx, rtx));
61a55e8b
DE		 135\f
136/* Option handling. */
137
a0a301fc 138/* Code model option as passed by user. */
3bb5de61 139const char *sparc_cmodel_string;
a0a301fc
DE		 140/* Parsed value. */
141enum cmodel sparc_cmodel;
142
1cb36a98
RH		 143char sparc_hard_reg_printed[8];
144
16956f6e
DE		 145struct sparc_cpu_select sparc_select[] =
146{
147 /* switch name, tune arch */
148 { (char *)0, "default", 1, 1 },
149 { (char *)0, "-mcpu=", 1, 1 },
150 { (char *)0, "-mtune=", 1, 0 },
db3d4438 151 { 0, 0, 0, 0 }
16956f6e 152};
733f53f5 153
16956f6e
DE		 154/* CPU type. This is set from TARGET_CPU_DEFAULT and -m{cpu,tune}=xxx. */
155enum processor_type sparc_cpu;
733f53f5 156
61a55e8b
DE		 157/* Validate and override various options, and do some machine dependent
158 initialization. */
159
160void
161sparc_override_options ()
162{
a0a301fc 163 static struct code_model {
3bb5de61 164 const char *name;
a0a301fc
DE		 165 int value;
166 } cmodels[] = {
167 { "32", CM_32 },
168 { "medlow", CM_MEDLOW },
169 { "medmid", CM_MEDMID },
170 { "medany", CM_MEDANY },
171 { "embmedany", CM_EMBMEDANY },
172 { 0, 0 }
173 };
174 struct code_model *cmodel;
16956f6e 175 /* Map TARGET_CPU_DEFAULT to value for -m{arch,tune}=. */
733f53f5
DE		 176 static struct cpu_default {
177 int cpu;
3bb5de61 178 const char *name;
733f53f5 179 } cpu_default[] = {
a0a301fc 180 /* There must be one entry here for each TARGET_CPU value. */
16956f6e 181 { TARGET_CPU_sparc, "cypress" },
3592ea0d 182 { TARGET_CPU_sparclet, "tsc701" },
16956f6e 183 { TARGET_CPU_sparclite, "f930" },
a0a301fc 184 { TARGET_CPU_v8, "v8" },
8947065c
RH		 185 { TARGET_CPU_hypersparc, "hypersparc" },
186 { TARGET_CPU_sparclite86x, "sparclite86x" },
a0a301fc
DE		 187 { TARGET_CPU_supersparc, "supersparc" },
188 { TARGET_CPU_v9, "v9" },
ba542005 189 { TARGET_CPU_ultrasparc, "ultrasparc" },
db3d4438 190 { 0, 0 }
733f53f5 191 };
16956f6e
DE		 192 struct cpu_default *def;
193 /* Table of values for -m{cpu,tune}=. */
733f53f5 194 static struct cpu_table {
3bb5de61 195 const char *name;
16956f6e 196 enum processor_type processor;
733f53f5
DE		 197 int disable;
198 int enable;
199 } cpu_table[] = {
16956f6e
DE		 200 { "v7", PROCESSOR_V7, MASK_ISA, 0 },
201 { "cypress", PROCESSOR_CYPRESS, MASK_ISA, 0 },
202 { "v8", PROCESSOR_V8, MASK_ISA, MASK_V8 },
733f53f5 203 /* TI TMS390Z55 supersparc */
16956f6e
DE		 204 { "supersparc", PROCESSOR_SUPERSPARC, MASK_ISA, MASK_V8 },
205 { "sparclite", PROCESSOR_SPARCLITE, MASK_ISA, MASK_SPARCLITE },
733f53f5
DE		 206 /* The Fujitsu MB86930 is the original sparclite chip, with no fpu.
207 The Fujitsu MB86934 is the recent sparclite chip, with an fpu. */
16956f6e
DE		 208 { "f930", PROCESSOR_F930, MASK_ISA|MASK_FPU, MASK_SPARCLITE },
209 { "f934", PROCESSOR_F934, MASK_ISA, MASK_SPARCLITE|MASK_FPU },
8947065c 210 { "hypersparc", PROCESSOR_HYPERSPARC, MASK_ISA, MASK_V8|MASK_FPU },
d3ec6b06
VM		 211 { "sparclite86x", PROCESSOR_SPARCLITE86X, MASK_ISA|MASK_FPU,
212 MASK_SPARCLITE },
16956f6e 213 { "sparclet", PROCESSOR_SPARCLET, MASK_ISA, MASK_SPARCLET },
733f53f5 214 /* TEMIC sparclet */
3592ea0d 215 { "tsc701", PROCESSOR_TSC701, MASK_ISA, MASK_SPARCLET },
16956f6e 216 { "v9", PROCESSOR_V9, MASK_ISA, MASK_V9 },
5cb01b65
JJ		 217 /* TI ultrasparc I, II, IIi */
218 { "ultrasparc", PROCESSOR_ULTRASPARC, MASK_ISA, MASK_V9
219 /* Although insns using %y are deprecated, it is a clear win on current
220 ultrasparcs. */
221 |MASK_DEPRECATED_V8_INSNS },
db3d4438 222 { 0, 0, 0, 0 }
733f53f5 223 };
16956f6e
DE		 224 struct cpu_table *cpu;
225 struct sparc_cpu_select *sel;
a0a301fc 226 int fpu;
345a6161 227
a0a301fc
DE		 228#ifndef SPARC_BI_ARCH
229 /* Check for unsupported architecture size. */
230 if (! TARGET_64BIT != DEFAULT_ARCH32_P)
231 {
232 error ("%s is not supported by this configuration",
233 DEFAULT_ARCH32_P ? "-m64" : "-m32");
234 }
235#endif
236
345a6161
DM		 237 /* At the moment we don't allow different pointer size and architecture */
238 if (! TARGET_64BIT != ! TARGET_PTR64)
239 {
240 error ("-mptr%d not allowed on -m%d",
241 TARGET_PTR64 ? 64 : 32, TARGET_64BIT ? 64 : 32);
242 if (TARGET_64BIT)
243 target_flags |= MASK_PTR64;
244 else
245 target_flags &= ~MASK_PTR64;
246 }
247
a0a301fc
DE		 248 /* Code model selection. */
249 sparc_cmodel = SPARC_DEFAULT_CMODEL;
345a6161
DM		 250
251#ifdef SPARC_BI_ARCH
252 if (TARGET_ARCH32)
253 sparc_cmodel = CM_32;
254#endif
255
a0a301fc
DE		 256 if (sparc_cmodel_string != NULL)
257 {
258 if (TARGET_ARCH64)
259 {
260 for (cmodel = &cmodels[0]; cmodel->name; cmodel++)
261 if (strcmp (sparc_cmodel_string, cmodel->name) == 0)
262 break;
263 if (cmodel->name == NULL)
264 error ("bad value (%s) for -mcmodel= switch", sparc_cmodel_string);
265 else
266 sparc_cmodel = cmodel->value;
267 }
268 else
269 error ("-mcmodel= is not supported on 32 bit systems");
270 }
16956f6e 271
a0a301fc 272 fpu = TARGET_FPU; /* save current -mfpu status */
1f1406b4 273
a0a301fc 274 /* Set the default CPU. */
16956f6e
DE		 275 for (def = &cpu_default[0]; def->name; ++def)
276 if (def->cpu == TARGET_CPU_DEFAULT)
277 break;
278 if (! def->name)
279 abort ();
280 sparc_select[0].string = def->name;
281
282 for (sel = &sparc_select[0]; sel->name; ++sel)
61a55e8b 283 {
16956f6e 284 if (sel->string)
733f53f5 285 {
16956f6e
DE		 286 for (cpu = &cpu_table[0]; cpu->name; ++cpu)
287 if (! strcmp (sel->string, cpu->name))
288 {
289 if (sel->set_tune_p)
290 sparc_cpu = cpu->processor;
291
292 if (sel->set_arch_p)
293 {
294 target_flags &= ~cpu->disable;
295 target_flags |= cpu->enable;
296 }
297 break;
298 }
299
300 if (! cpu->name)
301 error ("bad value (%s) for %s switch", sel->string, sel->name);
733f53f5 302 }
61a55e8b 303 }
97da85b7 304
1f1406b4 305 /* If -mfpu or -mno-fpu was explicitly used, don't override with
46cc13b3
RO		 306 the processor default. Clear MASK_FPU_SET to avoid confusing
307 the reverse mapping from switch values to names. */
1f1406b4 308 if (TARGET_FPU_SET)
46cc13b3
RO		 309 {
310 target_flags = (target_flags & ~MASK_FPU) | fpu;
311 target_flags &= ~MASK_FPU_SET;
312 }
1f1406b4 313
16956f6e
DE		 314 /* Use the deprecated v8 insns for sparc64 in 32 bit mode. */
315 if (TARGET_V9 && TARGET_ARCH32)
733f53f5 316 target_flags |= MASK_DEPRECATED_V8_INSNS;
61a55e8b 317
345a6161
DM		 318 /* V8PLUS requires V9, makes no sense in 64 bit mode. */
319 if (! TARGET_V9 || TARGET_ARCH64)
284d86e9
JC		 320 target_flags &= ~MASK_V8PLUS;
321
82d6b402
RH		 322 /* Don't use stack biasing in 32 bit mode. */
323 if (TARGET_ARCH32)
324 target_flags &= ~MASK_STACK_BIAS;
f952a238
JJ		 325
326 /* Don't allow -mvis if FPU is disabled. */
327 if (! TARGET_FPU)
328 target_flags &= ~MASK_VIS;
82d6b402 329
efa3896a
GK		 330 /* Supply a default value for align_functions. */
331 if (align_functions == 0 && sparc_cpu == PROCESSOR_ULTRASPARC)
332 align_functions = 32;
bf62bbf1 333
82d6b402
RH		 334 /* Validate PCC_STRUCT_RETURN. */
335 if (flag_pcc_struct_return == DEFAULT_PCC_STRUCT_RETURN)
336 flag_pcc_struct_return = (TARGET_ARCH64 ? 0 : 1);
337
61a55e8b
DE		 338 /* Do various machine dependent initializations. */
339 sparc_init_modes ();
2be15d0f
RH		 340
341 if ((profile_flag || profile_block_flag)
342 && sparc_cmodel != CM_MEDLOW)
343 {
344 error ("profiling does not support code models other than medlow");
345 }
d07d525a
MM		 346
347 /* Register global variables with the garbage collector. */
348 sparc_add_gc_roots ();
61a55e8b
DE		 349}
350\f
cd5fb1ee
DE		 351/* Miscellaneous utilities. */
352
353/* Nonzero if CODE, a comparison, is suitable for use in v9 conditional move
354 or branch on register contents instructions. */
355
356int
357v9_regcmp_p (code)
358 enum rtx_code code;
359{
360 return (code == EQ || code == NE || code == GE || code == LT
361 || code == LE || code == GT);
362}
bfd6bc60 363
cd5fb1ee
DE		 364\f
365/* Operand constraints. */
366
ab835497 367/* Return non-zero only if OP is a register of mode MODE,
c4ce6853
DE		 368 or const0_rtx. Don't allow const0_rtx if TARGET_LIVE_G0 because
369 %g0 may contain anything. */
370
ab835497
RK		 371int
372reg_or_0_operand (op, mode)
373 rtx op;
374 enum machine_mode mode;
375{
c4ce6853
DE		 376 if (register_operand (op, mode))
377 return 1;
378 if (TARGET_LIVE_G0)
379 return 0;
380 if (op == const0_rtx)
ab835497 381 return 1;
5b486ce0 382 if (GET_MODE (op) == VOIDmode && GET_CODE (op) == CONST_DOUBLE
ab835497
RK		 383 && CONST_DOUBLE_HIGH (op) == 0
384 && CONST_DOUBLE_LOW (op) == 0)
385 return 1;
302484ff
JW		 386 if (GET_MODE_CLASS (GET_MODE (op)) == MODE_FLOAT
387 && GET_CODE (op) == CONST_DOUBLE
388 && fp_zero_operand (op))
389 return 1;
ab835497
RK		 390 return 0;
391}
392
302484ff 393/* Nonzero if OP is a floating point value with value 0.0. */
c4ce6853 394
302484ff
JW		 395int
396fp_zero_operand (op)
397 rtx op;
398{
399 REAL_VALUE_TYPE r;
400
401 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
d61ba4f4 402 return (REAL_VALUES_EQUAL (r, dconst0) && ! REAL_VALUE_MINUS_ZERO (r));
302484ff
JW		 403}
404
61a55e8b
DE		 405/* Nonzero if OP is an integer register. */
406
407int
408intreg_operand (op, mode)
409 rtx op;
487a6e06 410 enum machine_mode mode ATTRIBUTE_UNUSED;
61a55e8b
DE		 411{
412 return (register_operand (op, SImode)
a9e27770 413 || (TARGET_ARCH64 && register_operand (op, DImode)));
61a55e8b
DE		 414}
415
416/* Nonzero if OP is a floating point condition code register. */
417
418int
c4ce6853 419fcc_reg_operand (op, mode)
61a55e8b
DE		 420 rtx op;
421 enum machine_mode mode;
422{
423 /* This can happen when recog is called from combine. Op may be a MEM.
424 Fail instead of calling abort in this case. */
c4ce6853 425 if (GET_CODE (op) != REG)
61a55e8b 426 return 0;
304b7a23 427
c4ce6853 428 if (mode != VOIDmode && mode != GET_MODE (op))
61a55e8b 429 return 0;
304b7a23
DE		 430 if (mode == VOIDmode
431 && (GET_MODE (op) != CCFPmode && GET_MODE (op) != CCFPEmode))
432 return 0;
61a55e8b 433
c4ce6853 434#if 0 /* ??? ==> 1 when %fcc0-3 are pseudos first. See gen_compare_reg(). */
61a55e8b
DE		 435 if (reg_renumber == 0)
436 return REGNO (op) >= FIRST_PSEUDO_REGISTER;
437 return REGNO_OK_FOR_CCFP_P (REGNO (op));
438#else
c4ce6853 439 return (unsigned) REGNO (op) - SPARC_FIRST_V9_FCC_REG < 4;
61a55e8b
DE		 440#endif
441}
442
c4ce6853
DE		 443/* Nonzero if OP is an integer or floating point condition code register. */
444
445int
446icc_or_fcc_reg_operand (op, mode)
447 rtx op;
448 enum machine_mode mode;
449{
450 if (GET_CODE (op) == REG && REGNO (op) == SPARC_ICC_REG)
304b7a23
DE		 451 {
452 if (mode != VOIDmode && mode != GET_MODE (op))
453 return 0;
454 if (mode == VOIDmode
455 && GET_MODE (op) != CCmode && GET_MODE (op) != CCXmode)
456 return 0;
457 return 1;
458 }
459
c4ce6853
DE		 460 return fcc_reg_operand (op, mode);
461}
462
ab835497
RK		 463/* Nonzero if OP can appear as the dest of a RESTORE insn. */
464int
465restore_operand (op, mode)
466 rtx op;
467 enum machine_mode mode;
468{
469 return (GET_CODE (op) == REG && GET_MODE (op) == mode
470 && (REGNO (op) < 8 || (REGNO (op) >= 24 && REGNO (op) < 32)));
471}
472
401cec23
JW		 473/* Call insn on SPARC can take a PC-relative constant address, or any regular
474 memory address. */
ab835497
RK		 475
476int
477call_operand (op, mode)
478 rtx op;
479 enum machine_mode mode;
480{
481 if (GET_CODE (op) != MEM)
482 abort ();
483 op = XEXP (op, 0);
2445f289 484 return (symbolic_operand (op, mode) || memory_address_p (Pmode, op));
ab835497
RK		 485}
486
487int
488call_operand_address (op, mode)
489 rtx op;
490 enum machine_mode mode;
491{
2445f289 492 return (symbolic_operand (op, mode) || memory_address_p (Pmode, op));
ab835497
RK		 493}
494
495/* Returns 1 if OP is either a symbol reference or a sum of a symbol
496 reference and a constant. */
497
498int
499symbolic_operand (op, mode)
500 register rtx op;
501 enum machine_mode mode;
502{
6871dd65
RH		 503 enum machine_mode omode = GET_MODE (op);
504
505 if (omode != mode && omode != VOIDmode && mode != VOIDmode)
506 return 0;
507
ab835497
RK		 508 switch (GET_CODE (op))
509 {
510 case SYMBOL_REF:
511 case LABEL_REF:
512 return 1;
513
514 case CONST:
515 op = XEXP (op, 0);
516 return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
517 || GET_CODE (XEXP (op, 0)) == LABEL_REF)
518 && GET_CODE (XEXP (op, 1)) == CONST_INT);
519
ab835497
RK		 520 default:
521 return 0;
522 }
523}
524
525/* Return truth value of statement that OP is a symbolic memory
526 operand of mode MODE. */
527
528int
529symbolic_memory_operand (op, mode)
530 rtx op;
487a6e06 531 enum machine_mode mode ATTRIBUTE_UNUSED;
ab835497
RK		 532{
533 if (GET_CODE (op) == SUBREG)
534 op = SUBREG_REG (op);
535 if (GET_CODE (op) != MEM)
536 return 0;
537 op = XEXP (op, 0);
538 return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST
539 || GET_CODE (op) == HIGH || GET_CODE (op) == LABEL_REF);
540}
541
5ab7138b
DE		 542/* Return truth value of statement that OP is a LABEL_REF of mode MODE. */
543
544int
545label_ref_operand (op, mode)
546 rtx op;
547 enum machine_mode mode;
548{
549 if (GET_CODE (op) != LABEL_REF)
550 return 0;
551 if (GET_MODE (op) != mode)
552 return 0;
553 return 1;
554}
555
95726648
DE		 556/* Return 1 if the operand is an argument used in generating pic references
557 in either the medium/low or medium/anywhere code models of sparc64. */
558
559int
560sp64_medium_pic_operand (op, mode)
561 rtx op;
487a6e06 562 enum machine_mode mode ATTRIBUTE_UNUSED;
95726648
DE		 563{
564 /* Check for (const (minus (symbol_ref:GOT)
565 (const (minus (label) (pc))))). */
566 if (GET_CODE (op) != CONST)
567 return 0;
568 op = XEXP (op, 0);
569 if (GET_CODE (op) != MINUS)
570 return 0;
571 if (GET_CODE (XEXP (op, 0)) != SYMBOL_REF)
572 return 0;
573 /* ??? Ensure symbol is GOT. */
574 if (GET_CODE (XEXP (op, 1)) != CONST)
575 return 0;
576 if (GET_CODE (XEXP (XEXP (op, 1), 0)) != MINUS)
577 return 0;
578 return 1;
579}
580
61a55e8b
DE		 581/* Return 1 if the operand is a data segment reference. This includes
582 the readonly data segment, or in other words anything but the text segment.
583 This is needed in the medium/anywhere code model on v9. These values
a0a301fc 584 are accessed with EMBMEDANY_BASE_REG. */
61a55e8b
DE		 585
586int
587data_segment_operand (op, mode)
588 rtx op;
487a6e06 589 enum machine_mode mode ATTRIBUTE_UNUSED;
61a55e8b
DE		 590{
591 switch (GET_CODE (op))
592 {
593 case SYMBOL_REF :
594 return ! SYMBOL_REF_FLAG (op);
595 case PLUS :
95726648
DE		 596 /* Assume canonical format of symbol + constant.
597 Fall through. */
61a55e8b 598 case CONST :
b1474bb7 599 return data_segment_operand (XEXP (op, 0), VOIDmode);
61a55e8b
DE		 600 default :
601 return 0;
602 }
603}
604
605/* Return 1 if the operand is a text segment reference.
606 This is needed in the medium/anywhere code model on v9. */
607
608int
609text_segment_operand (op, mode)
610 rtx op;
487a6e06 611 enum machine_mode mode ATTRIBUTE_UNUSED;
61a55e8b
DE		 612{
613 switch (GET_CODE (op))
614 {
615 case LABEL_REF :
616 return 1;
617 case SYMBOL_REF :
618 return SYMBOL_REF_FLAG (op);
619 case PLUS :
95726648
DE		 620 /* Assume canonical format of symbol + constant.
621 Fall through. */
61a55e8b 622 case CONST :
b1474bb7 623 return text_segment_operand (XEXP (op, 0), VOIDmode);
61a55e8b
DE		 624 default :
625 return 0;
626 }
627}
628
ab835497
RK		 629/* Return 1 if the operand is either a register or a memory operand that is
630 not symbolic. */
631
632int
633reg_or_nonsymb_mem_operand (op, mode)
634 register rtx op;
635 enum machine_mode mode;
636{
637 if (register_operand (op, mode))
638 return 1;
639
640 if (memory_operand (op, mode) && ! symbolic_memory_operand (op, mode))
641 return 1;
642
643 return 0;
644}
645
ab835497 646int
6ac34277 647splittable_symbolic_memory_operand (op, mode)
ab835497 648 rtx op;
487a6e06 649 enum machine_mode mode ATTRIBUTE_UNUSED;
ab835497 650{
6ac34277
DE		 651 if (GET_CODE (op) != MEM)
652 return 0;
653 if (! symbolic_operand (XEXP (op, 0), Pmode))
654 return 0;
655 return 1;
656}
657
658int
659splittable_immediate_memory_operand (op, mode)
660 rtx op;
487a6e06 661 enum machine_mode mode ATTRIBUTE_UNUSED;
6ac34277
DE		 662{
663 if (GET_CODE (op) != MEM)
664 return 0;
665 if (! immediate_operand (XEXP (op, 0), Pmode))
666 return 0;
667 return 1;
ab835497
RK		 668}
669
670/* Return truth value of whether OP is EQ or NE. */
671
672int
673eq_or_neq (op, mode)
674 rtx op;
487a6e06 675 enum machine_mode mode ATTRIBUTE_UNUSED;
ab835497
RK		 676{
677 return (GET_CODE (op) == EQ || GET_CODE (op) == NE);
678}
679
680/* Return 1 if this is a comparison operator, but not an EQ, NE, GEU,
681 or LTU for non-floating-point. We handle those specially. */
682
683int
684normal_comp_operator (op, mode)
685 rtx op;
487a6e06 686 enum machine_mode mode ATTRIBUTE_UNUSED;
ab835497
RK		 687{
688 enum rtx_code code = GET_CODE (op);
689
690 if (GET_RTX_CLASS (code) != '<')
691 return 0;
692
4d449554
JW		 693 if (GET_MODE (XEXP (op, 0)) == CCFPmode
694 || GET_MODE (XEXP (op, 0)) == CCFPEmode)
ab835497
RK		 695 return 1;
696
697 return (code != NE && code != EQ && code != GEU && code != LTU);
698}
699
700/* Return 1 if this is a comparison operator. This allows the use of
701 MATCH_OPERATOR to recognize all the branch insns. */
702
703int
704noov_compare_op (op, mode)
705 register rtx op;
487a6e06 706 enum machine_mode mode ATTRIBUTE_UNUSED;
ab835497
RK		 707{
708 enum rtx_code code = GET_CODE (op);
709
710 if (GET_RTX_CLASS (code) != '<')
711 return 0;
712
713 if (GET_MODE (XEXP (op, 0)) == CC_NOOVmode)
714 /* These are the only branches which work with CC_NOOVmode. */
715 return (code == EQ || code == NE || code == GE || code == LT);
716 return 1;
717}
718
61a55e8b
DE		 719/* Nonzero if OP is a comparison operator suitable for use in v9
720 conditional move or branch on register contents instructions. */
721
722int
723v9_regcmp_op (op, mode)
724 register rtx op;
487a6e06 725 enum machine_mode mode ATTRIBUTE_UNUSED;
61a55e8b
DE		 726{
727 enum rtx_code code = GET_CODE (op);
728
729 if (GET_RTX_CLASS (code) != '<')
730 return 0;
731
cd5fb1ee 732 return v9_regcmp_p (code);
61a55e8b
DE		 733}
734
ab835497
RK		 735/* Return 1 if this is a SIGN_EXTEND or ZERO_EXTEND operation. */
736
737int
738extend_op (op, mode)
739 rtx op;
487a6e06 740 enum machine_mode mode ATTRIBUTE_UNUSED;
ab835497
RK		 741{
742 return GET_CODE (op) == SIGN_EXTEND || GET_CODE (op) == ZERO_EXTEND;
743}
744
745/* Return nonzero if OP is an operator of mode MODE which can set
746 the condition codes explicitly. We do not include PLUS and MINUS
747 because these require CC_NOOVmode, which we handle explicitly. */
748
749int
750cc_arithop (op, mode)
751 rtx op;
487a6e06 752 enum machine_mode mode ATTRIBUTE_UNUSED;
ab835497
RK		 753{
754 if (GET_CODE (op) == AND
755 || GET_CODE (op) == IOR
756 || GET_CODE (op) == XOR)
757 return 1;
758
759 return 0;
760}
761
762/* Return nonzero if OP is an operator of mode MODE which can bitwise
763 complement its second operand and set the condition codes explicitly. */
764
765int
766cc_arithopn (op, mode)
767 rtx op;
487a6e06 768 enum machine_mode mode ATTRIBUTE_UNUSED;
ab835497
RK		 769{
770 /* XOR is not here because combine canonicalizes (xor (not ...) ...)
771 and (xor ... (not ...)) to (not (xor ...)). */
772 return (GET_CODE (op) == AND
773 || GET_CODE (op) == IOR);
774}
775\f
58cbf20e
DE		 776/* Return true if OP is a register, or is a CONST_INT that can fit in a
777 signed 13 bit immediate field. This is an acceptable SImode operand for
778 most 3 address instructions. */
ab835497
RK		 779
780int
781arith_operand (op, mode)
782 rtx op;
783 enum machine_mode mode;
784{
284d86e9 785 int val;
11301057 786 if (register_operand (op, mode))
284d86e9
JC		 787 return 1;
788 if (GET_CODE (op) != CONST_INT)
789 return 0;
790 val = INTVAL (op) & 0xffffffff;
791 return SPARC_SIMM13_P (val);
ab835497
RK		 792}
793
5d6d3339
JJ		 794/* Return true if OP is a constant 4096 */
795
796int
797arith_4096_operand (op, mode)
798 rtx op;
ddf80874 799 enum machine_mode mode ATTRIBUTE_UNUSED;
5d6d3339
JJ		 800{
801 int val;
802 if (GET_CODE (op) != CONST_INT)
803 return 0;
804 val = INTVAL (op) & 0xffffffff;
805 return val == 4096;
806}
807
808/* Return true if OP is suitable as second operand for add/sub */
809
810int
811arith_add_operand (op, mode)
812 rtx op;
813 enum machine_mode mode;
814{
815 return arith_operand (op, mode) || arith_4096_operand (op, mode);
816}
817
89e65674
DM		 818/* Return true if OP is a CONST_INT or a CONST_DOUBLE which can fit in the
819 immediate field of OR and XOR instructions. Used for 64-bit
820 constant formation patterns. */
821int
822const64_operand (op, mode)
823 rtx op;
ddf80874 824 enum machine_mode mode ATTRIBUTE_UNUSED;
89e65674
DM		 825{
826 return ((GET_CODE (op) == CONST_INT
827 && SPARC_SIMM13_P (INTVAL (op)))
9208e4b2 828#if HOST_BITS_PER_WIDE_INT != 64
89e65674 829 || (GET_CODE (op) == CONST_DOUBLE
9208e4b2
DM		 830 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op))
831 && (CONST_DOUBLE_HIGH (op) ==
832 ((CONST_DOUBLE_LOW (op) & 0x80000000) != 0 ?
ddf80874 833 (HOST_WIDE_INT)0xffffffff : 0)))
9208e4b2 834#endif
11301057 835 );
89e65674
DM		 836}
837
9208e4b2 838/* The same, but only for sethi instructions. */
89e65674
DM		 839int
840const64_high_operand (op, mode)
841 rtx op;
ddf80874 842 enum machine_mode mode ATTRIBUTE_UNUSED;
89e65674
DM		 843{
844 return ((GET_CODE (op) == CONST_INT
9208e4b2
DM		 845 && (INTVAL (op) & 0xfffffc00) != 0
846 && SPARC_SETHI_P (INTVAL (op))
847#if HOST_BITS_PER_WIDE_INT != 64
848 /* Must be positive on non-64bit host else the
849 optimizer is fooled into thinking that sethi
850 sign extends, even though it does not. */
851 && INTVAL (op) >= 0
852#endif
853 )
89e65674
DM		 854 || (GET_CODE (op) == CONST_DOUBLE
855 && CONST_DOUBLE_HIGH (op) == 0
9208e4b2 856 && (CONST_DOUBLE_LOW (op) & 0xfffffc00) != 0
11301057 857 && SPARC_SETHI_P (CONST_DOUBLE_LOW (op))));
89e65674
DM		 858}
859
58cbf20e
DE		 860/* Return true if OP is a register, or is a CONST_INT that can fit in a
861 signed 11 bit immediate field. This is an acceptable SImode operand for
862 the movcc instructions. */
61a55e8b
DE		 863
864int
865arith11_operand (op, mode)
866 rtx op;
867 enum machine_mode mode;
868{
869 return (register_operand (op, mode)
58cbf20e 870 || (GET_CODE (op) == CONST_INT && SPARC_SIMM11_P (INTVAL (op))));
61a55e8b
DE		 871}
872
58cbf20e
DE		 873/* Return true if OP is a register, or is a CONST_INT that can fit in a
874 signed 10 bit immediate field. This is an acceptable SImode operand for
875 the movrcc instructions. */
61a55e8b
DE		 876
877int
878arith10_operand (op, mode)
879 rtx op;
880 enum machine_mode mode;
881{
882 return (register_operand (op, mode)
58cbf20e 883 || (GET_CODE (op) == CONST_INT && SPARC_SIMM10_P (INTVAL (op))));
61a55e8b
DE		 884}
885
23b8a89f
JW		 886/* Return true if OP is a register, is a CONST_INT that fits in a 13 bit
887 immediate field, or is a CONST_DOUBLE whose both parts fit in a 13 bit
61a55e8b
DE		 888 immediate field.
889 v9: Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
890 can fit in a 13 bit immediate field. This is an acceptable DImode operand
891 for most 3 address instructions. */
ab835497
RK		 892
893int
894arith_double_operand (op, mode)
895 rtx op;
896 enum machine_mode mode;
897{
898 return (register_operand (op, mode)
23b8a89f 899 || (GET_CODE (op) == CONST_INT && SMALL_INT (op))
a9e27770 900 || (! TARGET_ARCH64
61a55e8b 901 && GET_CODE (op) == CONST_DOUBLE
bf62bbf1
DE		 902 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x1000) < 0x2000
903 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_HIGH (op) + 0x1000) < 0x2000)
a9e27770 904 || (TARGET_ARCH64
61a55e8b 905 && GET_CODE (op) == CONST_DOUBLE
bf62bbf1 906 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x1000) < 0x2000
61a55e8b
DE		 907 && ((CONST_DOUBLE_HIGH (op) == -1
908 && (CONST_DOUBLE_LOW (op) & 0x1000) == 0x1000)
909 || (CONST_DOUBLE_HIGH (op) == 0
910 && (CONST_DOUBLE_LOW (op) & 0x1000) == 0))));
911}
912
5d6d3339
JJ		 913/* Return true if OP is a constant 4096 for DImode on ARCH64 */
914
915int
916arith_double_4096_operand (op, mode)
917 rtx op;
ddf80874 918 enum machine_mode mode ATTRIBUTE_UNUSED;
5d6d3339
JJ		 919{
920 return (TARGET_ARCH64 &&
921 ((GET_CODE (op) == CONST_INT && INTVAL (op) == 4096) ||
922 (GET_CODE (op) == CONST_DOUBLE &&
923 CONST_DOUBLE_LOW (op) == 4096 &&
924 CONST_DOUBLE_HIGH (op) == 0)));
925}
926
927/* Return true if OP is suitable as second operand for add/sub in DImode */
928
929int
930arith_double_add_operand (op, mode)
931 rtx op;
932 enum machine_mode mode;
933{
934 return arith_double_operand (op, mode) || arith_double_4096_operand (op, mode);
935}
936
61a55e8b
DE		 937/* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
938 can fit in an 11 bit immediate field. This is an acceptable DImode
939 operand for the movcc instructions. */
940/* ??? Replace with arith11_operand? */
941
942int
943arith11_double_operand (op, mode)
944 rtx op;
945 enum machine_mode mode;
946{
947 return (register_operand (op, mode)
948 || (GET_CODE (op) == CONST_DOUBLE
949 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
bf62bbf1 950 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x400) < 0x800
61a55e8b
DE		 951 && ((CONST_DOUBLE_HIGH (op) == -1
952 && (CONST_DOUBLE_LOW (op) & 0x400) == 0x400)
953 || (CONST_DOUBLE_HIGH (op) == 0
954 && (CONST_DOUBLE_LOW (op) & 0x400) == 0)))
955 || (GET_CODE (op) == CONST_INT
956 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
bf62bbf1 957 && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x400) < 0x800));
61a55e8b
DE		 958}
959
960/* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
961 can fit in an 10 bit immediate field. This is an acceptable DImode
962 operand for the movrcc instructions. */
963/* ??? Replace with arith10_operand? */
964
965int
966arith10_double_operand (op, mode)
967 rtx op;
968 enum machine_mode mode;
969{
970 return (register_operand (op, mode)
971 || (GET_CODE (op) == CONST_DOUBLE
972 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
973 && (unsigned) (CONST_DOUBLE_LOW (op) + 0x200) < 0x400
974 && ((CONST_DOUBLE_HIGH (op) == -1
975 && (CONST_DOUBLE_LOW (op) & 0x200) == 0x200)
976 || (CONST_DOUBLE_HIGH (op) == 0
977 && (CONST_DOUBLE_LOW (op) & 0x200) == 0)))
978 || (GET_CODE (op) == CONST_INT
979 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
bf62bbf1 980 && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x200) < 0x400));
ab835497
RK		 981}
982
983/* Return truth value of whether OP is a integer which fits the
228b4037
JW		 984 range constraining immediate operands in most three-address insns,
985 which have a 13 bit immediate field. */
ab835497
RK		 986
987int
988small_int (op, mode)
989 rtx op;
487a6e06 990 enum machine_mode mode ATTRIBUTE_UNUSED;
ab835497 991{
11301057 992 return (GET_CODE (op) == CONST_INT && SMALL_INT (op));
ab835497
RK		 993}
994
e0d80184
DM		 995int
996small_int_or_double (op, mode)
997 rtx op;
998 enum machine_mode mode ATTRIBUTE_UNUSED;
999{
1000 return ((GET_CODE (op) == CONST_INT && SMALL_INT (op))
1001 || (GET_CODE (op) == CONST_DOUBLE
1002 && CONST_DOUBLE_HIGH (op) == 0
11301057 1003 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op))));
e0d80184
DM		 1004}
1005
9b3fad96
JW		 1006/* Recognize operand values for the umul instruction. That instruction sign
1007 extends immediate values just like all other sparc instructions, but
1008 interprets the extended result as an unsigned number. */
1009
1010int
1011uns_small_int (op, mode)
1012 rtx op;
487a6e06 1013 enum machine_mode mode ATTRIBUTE_UNUSED;
9b3fad96
JW		 1014{
1015#if HOST_BITS_PER_WIDE_INT > 32
1016 /* All allowed constants will fit a CONST_INT. */
11301057
RH		 1017 return (GET_CODE (op) == CONST_INT
1018 && ((INTVAL (op) >= 0 && INTVAL (op) < 0x1000)
1019 || (INTVAL (op) >= 0xFFFFF000
1020 && INTVAL (op) < 0x100000000)));
9b3fad96 1021#else
11301057
RH		 1022 return ((GET_CODE (op) == CONST_INT && (unsigned) INTVAL (op) < 0x1000)
1023 || (GET_CODE (op) == CONST_DOUBLE
1024 && CONST_DOUBLE_HIGH (op) == 0
1025 && (unsigned) CONST_DOUBLE_LOW (op) - 0xFFFFF000 < 0x1000));
9b3fad96
JW		 1026#endif
1027}
1028
1029int
1030uns_arith_operand (op, mode)
1031 rtx op;
1032 enum machine_mode mode;
1033{
1034 return register_operand (op, mode) || uns_small_int (op, mode);
1035}
1036
ab835497
RK		 1037/* Return truth value of statement that OP is a call-clobbered register. */
1038int
1039clobbered_register (op, mode)
1040 rtx op;
487a6e06 1041 enum machine_mode mode ATTRIBUTE_UNUSED;
ab835497
RK		 1042{
1043 return (GET_CODE (op) == REG && call_used_regs[REGNO (op)]);
1044}
ab835497 1045
e0d80184
DM		 1046/* Return 1 if OP is const0_rtx, used for TARGET_LIVE_G0 insns. */
1047
1048int
1049zero_operand (op, mode)
1050 rtx op;
1051 enum machine_mode mode ATTRIBUTE_UNUSED;
ab835497 1052{
11301057 1053 return op == const0_rtx;
e0d80184 1054}
61a55e8b 1055
e0d80184 1056/* Return 1 if OP is a valid operand for the source of a move insn. */
61a55e8b 1057
e0d80184
DM		 1058int
1059input_operand (op, mode)
1060 rtx op;
1061 enum machine_mode mode;
1062{
1063 /* If both modes are non-void they must be the same. */
1064 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op))
1065 return 0;
61a55e8b 1066
11301057
RH		 1067 /* Only a tiny bit of handling for CONSTANT_P_RTX is necessary. */
1068 if (GET_CODE (op) == CONST && GET_CODE (XEXP (op, 0)) == CONSTANT_P_RTX)
1069 return 1;
1070
e0d80184
DM		 1071 /* Allow any one instruction integer constant, and all CONST_INT
1072 variants when we are working in DImode and !arch64. */
1073 if (GET_MODE_CLASS (mode) == MODE_INT
9208e4b2
DM		 1074 && ((GET_CODE (op) == CONST_INT
1075 && ((SPARC_SETHI_P (INTVAL (op))
1076 && (! TARGET_ARCH64
1077 || (INTVAL (op) >= 0)
1078 || mode == SImode))
1079 || SPARC_SIMM13_P (INTVAL (op))
1080 || (mode == DImode
1081 && ! TARGET_ARCH64)))
1082 || (TARGET_ARCH64
1083 && GET_CODE (op) == CONST_DOUBLE
1084 && ((CONST_DOUBLE_HIGH (op) == 0
1085 && SPARC_SETHI_P (CONST_DOUBLE_LOW (op)))
1086 ||
1087#if HOST_BITS_PER_WIDE_INT == 64
1088 (CONST_DOUBLE_HIGH (op) == 0
1089 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op)))
1090#else
1091 (SPARC_SIMM13_P (CONST_DOUBLE_LOW (op))
1092 && (((CONST_DOUBLE_LOW (op) & 0x80000000) == 0
1093 && CONST_DOUBLE_HIGH (op) == 0)
1094 || (CONST_DOUBLE_HIGH (op) == -1)))
1095#endif
1096 ))))
e0d80184
DM		 1097 return 1;
1098
e0d80184
DM		 1099 /* If !arch64 and this is a DImode const, allow it so that
1100 the splits can be generated. */
1101 if (! TARGET_ARCH64
1102 && mode == DImode
1103 && GET_CODE (op) == CONST_DOUBLE)
1104 return 1;
1105
1106 if (register_operand (op, mode))
1107 return 1;
1108
1109 /* If this is a SUBREG, look inside so that we handle
1110 paradoxical ones. */
1111 if (GET_CODE (op) == SUBREG)
1112 op = SUBREG_REG (op);
1113
1114 /* Check for valid MEM forms. */
1115 if (GET_CODE (op) == MEM)
61a55e8b 1116 {
e0d80184 1117 rtx inside = XEXP (op, 0);
61a55e8b 1118
e0d80184 1119 if (GET_CODE (inside) == LO_SUM)
03ad6f4d
DM		 1120 {
1121 /* We can't allow these because all of the splits
1122 (eventually as they trickle down into DFmode
1123 splits) require offsettable memory references. */
1124 if (! TARGET_V9
1125 && GET_MODE (op) == TFmode)
1126 return 0;
1127
1128 return (register_operand (XEXP (inside, 0), Pmode)
1129 && CONSTANT_P (XEXP (inside, 1)));
1130 }
e0d80184 1131 return memory_address_p (mode, inside);
61a55e8b 1132 }
ab835497 1133
e0d80184
DM		 1134 return 0;
1135}
1136
1137\f
1138/* We know it can't be done in one insn when we get here,
1139 the movsi expander guarentees this. */
1140void
1141sparc_emit_set_const32 (op0, op1)
1142 rtx op0;
1143 rtx op1;
1144{
1145 enum machine_mode mode = GET_MODE (op0);
1146 rtx temp;
1147
1148 if (GET_CODE (op1) == CONST_INT)
284d86e9 1149 {
2a01c939 1150 HOST_WIDE_INT value = INTVAL (op1);
e0d80184
DM		 1151
1152 if (SPARC_SETHI_P (value)
1153 || SPARC_SIMM13_P (value))
1154 abort ();
284d86e9 1155 }
e0d80184
DM		 1156
1157 /* Full 2-insn decomposition is needed. */
1158 if (reload_in_progress || reload_completed)
1159 temp = op0;
284d86e9 1160 else
e0d80184
DM		 1161 temp = gen_reg_rtx (mode);
1162
71648202
DM		 1163 if (GET_CODE (op1) == CONST_INT)
1164 {
1165 /* Emit them as real moves instead of a HIGH/LO_SUM,
1166 this way CSE can see everything and reuse intermediate
1167 values if it wants. */
1168 if (TARGET_ARCH64
1169 && HOST_BITS_PER_WIDE_INT != 64
1170 && (INTVAL (op1) & 0x80000000) != 0)
1171 {
1172 emit_insn (gen_rtx_SET (VOIDmode,
1173 temp,
1174 gen_rtx_CONST_DOUBLE (VOIDmode, const0_rtx,
1175 INTVAL (op1) & 0xfffffc00, 0)));
1176 }
1177 else
1178 {
1179 emit_insn (gen_rtx_SET (VOIDmode,
1180 temp,
1181 GEN_INT (INTVAL (op1) & 0xfffffc00)));
1182 }
1183 emit_insn (gen_rtx_SET (VOIDmode,
1184 op0,
1185 gen_rtx_IOR (mode,
1186 temp,
1187 GEN_INT (INTVAL (op1) & 0x3ff))));
1188 }
1189 else
1190 {
1191 /* A symbol, emit in the traditional way. */
1192 emit_insn (gen_rtx_SET (VOIDmode,
1193 temp,
1194 gen_rtx_HIGH (mode,
1195 op1)));
1196 emit_insn (gen_rtx_SET (VOIDmode,
1197 op0,
1198 gen_rtx_LO_SUM (mode,
1199 temp,
1200 op1)));
1201
1202 }
e0d80184
DM		 1203}
1204
1205\f
1206/* Sparc-v9 code-model support. */
1207void
1208sparc_emit_set_symbolic_const64 (op0, op1, temp1)
1209 rtx op0;
1210 rtx op1;
1211 rtx temp1;
1212{
1213 switch (sparc_cmodel)
284d86e9 1214 {
e0d80184
DM		 1215 case CM_MEDLOW:
1216 /* The range spanned by all instructions in the object is less
1217 than 2^31 bytes (2GB) and the distance from any instruction
1218 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1219 than 2^31 bytes (2GB).
ab835497 1220
e0d80184
DM		 1221 The executable must be in the low 4TB of the virtual address
1222 space.
61a55e8b 1223
e0d80184
DM		 1224 sethi %hi(symbol), %temp
1225 or %temp, %lo(symbol), %reg */
9208e4b2
DM		 1226 emit_insn (gen_rtx_SET (VOIDmode, temp1, gen_rtx_HIGH (DImode, op1)));
1227 emit_insn (gen_rtx_SET (VOIDmode, op0, gen_rtx_LO_SUM (DImode, temp1, op1)));
e0d80184 1228 break;
61a55e8b 1229
e0d80184
DM		 1230 case CM_MEDMID:
1231 /* The range spanned by all instructions in the object is less
1232 than 2^31 bytes (2GB) and the distance from any instruction
1233 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1234 than 2^31 bytes (2GB).
1235
1236 The executable must be in the low 16TB of the virtual address
1237 space.
1238
1239 sethi %h44(symbol), %temp1
1240 or %temp1, %m44(symbol), %temp2
1241 sllx %temp2, 12, %temp3
1242 or %temp3, %l44(symbol), %reg */
1243 emit_insn (gen_seth44 (op0, op1));
1244 emit_insn (gen_setm44 (op0, op0, op1));
9208e4b2 1245 emit_insn (gen_rtx_SET (VOIDmode, temp1,
e0d80184
DM		 1246 gen_rtx_ASHIFT (DImode, op0, GEN_INT (12))));
1247 emit_insn (gen_setl44 (op0, temp1, op1));
1248 break;
61a55e8b 1249
e0d80184
DM		 1250 case CM_MEDANY:
1251 /* The range spanned by all instructions in the object is less
1252 than 2^31 bytes (2GB) and the distance from any instruction
1253 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1254 than 2^31 bytes (2GB).
1255
1256 The executable can be placed anywhere in the virtual address
1257 space.
1258
1259 sethi %hh(symbol), %temp1
1260 sethi %lm(symbol), %temp2
1261 or %temp1, %hm(symbol), %temp3
1262 or %temp2, %lo(symbol), %temp4
1263 sllx %temp3, 32, %temp5
1264 or %temp4, %temp5, %reg */
1265
1266 /* Getting this right wrt. reloading is really tricky.
5722d61c 1267 We _MUST_ have a separate temporary at this point,
e0d80184
DM		 1268 if we don't barf immediately instead of generating
1269 incorrect code. */
1270 if (temp1 == op0)
1271 abort ();
61a55e8b 1272
e0d80184
DM		 1273 emit_insn (gen_sethh (op0, op1));
1274 emit_insn (gen_setlm (temp1, op1));
1275 emit_insn (gen_sethm (op0, op0, op1));
9208e4b2 1276 emit_insn (gen_rtx_SET (VOIDmode, op0,
e0d80184 1277 gen_rtx_ASHIFT (DImode, op0, GEN_INT (32))));
9208e4b2 1278 emit_insn (gen_rtx_SET (VOIDmode, op0,
e0d80184
DM		 1279 gen_rtx_PLUS (DImode, op0, temp1)));
1280 emit_insn (gen_setlo (op0, op0, op1));
1281 break;
61a55e8b 1282
e0d80184
DM		 1283 case CM_EMBMEDANY:
1284 /* Old old old backwards compatibility kruft here.
1285 Essentially it is MEDLOW with a fixed 64-bit
1286 virtual base added to all data segment addresses.
1287 Text-segment stuff is computed like MEDANY, we can't
1288 reuse the code above because the relocation knobs
1289 look different.
1290
1291 Data segment: sethi %hi(symbol), %temp1
1292 or %temp1, %lo(symbol), %temp2
1293 add %temp2, EMBMEDANY_BASE_REG, %reg
1294
1295 Text segment: sethi %uhi(symbol), %temp1
1296 sethi %hi(symbol), %temp2
1297 or %temp1, %ulo(symbol), %temp3
1298 or %temp2, %lo(symbol), %temp4
1299 sllx %temp3, 32, %temp5
1300 or %temp4, %temp5, %reg */
1301 if (data_segment_operand (op1, GET_MODE (op1)))
1302 {
1303 emit_insn (gen_embmedany_sethi (temp1, op1));
1304 emit_insn (gen_embmedany_brsum (op0, temp1));
1305 emit_insn (gen_embmedany_losum (op0, op0, op1));
1306 }
1307 else
1308 {
1309 /* Getting this right wrt. reloading is really tricky.
5722d61c 1310 We _MUST_ have a separate temporary at this point,
f710f868 1311 so we barf immediately instead of generating
e0d80184
DM		 1312 incorrect code. */
1313 if (temp1 == op0)
1314 abort ();
61a55e8b 1315
e0d80184
DM		 1316 emit_insn (gen_embmedany_textuhi (op0, op1));
1317 emit_insn (gen_embmedany_texthi (temp1, op1));
1318 emit_insn (gen_embmedany_textulo (op0, op0, op1));
9208e4b2 1319 emit_insn (gen_rtx_SET (VOIDmode, op0,
e0d80184 1320 gen_rtx_ASHIFT (DImode, op0, GEN_INT (32))));
9208e4b2 1321 emit_insn (gen_rtx_SET (VOIDmode, op0,
e0d80184
DM		 1322 gen_rtx_PLUS (DImode, op0, temp1)));
1323 emit_insn (gen_embmedany_textlo (op0, op0, op1));
1324 }
1325 break;
1326
1327 default:
1328 abort();
1329 }
1330}
1331
9208e4b2
DM		 1332/* These avoid problems when cross compiling. If we do not
1333 go through all this hair then the optimizer will see
1334 invalid REG_EQUAL notes or in some cases none at all. */
1335static void sparc_emit_set_safe_HIGH64 PROTO ((rtx, HOST_WIDE_INT));
1336static rtx gen_safe_SET64 PROTO ((rtx, HOST_WIDE_INT));
1337static rtx gen_safe_OR64 PROTO ((rtx, HOST_WIDE_INT));
1338static rtx gen_safe_XOR64 PROTO ((rtx, HOST_WIDE_INT));
1339
1340#if HOST_BITS_PER_WIDE_INT == 64
1341#define GEN_HIGHINT64(__x) GEN_INT ((__x) & 0xfffffc00)
1342#define GEN_INT64(__x) GEN_INT (__x)
1343#else
1344#define GEN_HIGHINT64(__x) \
1345 gen_rtx_CONST_DOUBLE (VOIDmode, const0_rtx, \
1346 (__x) & 0xfffffc00, 0)
1347#define GEN_INT64(__x) \
1348 gen_rtx_CONST_DOUBLE (VOIDmode, const0_rtx, \
1349 (__x) & 0xffffffff, \
1350 ((__x) & 0x80000000 \
1351 ? 0xffffffff : 0))
1352#endif
1353
1354/* The optimizer is not to assume anything about exactly
1355 which bits are set for a HIGH, they are unspecified.
1356 Unfortunately this leads to many missed optimizations
1357 during CSE. We mask out the non-HIGH bits, and matches
1358 a plain movdi, to alleviate this problem. */
1359static void
1360sparc_emit_set_safe_HIGH64 (dest, val)
1361 rtx dest;
1362 HOST_WIDE_INT val;
1363{
1364 emit_insn (gen_rtx_SET (VOIDmode, dest, GEN_HIGHINT64 (val)));
1365}
2a01c939 1366
e0d80184 1367static rtx
9208e4b2
DM		 1368gen_safe_SET64 (dest, val)
1369 rtx dest;
e0d80184 1370 HOST_WIDE_INT val;
61a55e8b 1371{
9208e4b2
DM		 1372 return gen_rtx_SET (VOIDmode, dest, GEN_INT64 (val));
1373}
1374
1375static rtx
1376gen_safe_OR64 (src, val)
1377 rtx src;
1378 HOST_WIDE_INT val;
1379{
1380 return gen_rtx_IOR (DImode, src, GEN_INT64 (val));
1381}
1382
1383static rtx
1384gen_safe_XOR64 (src, val)
1385 rtx src;
1386 HOST_WIDE_INT val;
1387{
1388 return gen_rtx_XOR (DImode, src, GEN_INT64 (val));
e0d80184 1389}
61a55e8b 1390
e0d80184
DM		 1391/* Worker routines for 64-bit constant formation on arch64.
1392 One of the key things to be doing in these emissions is
1393 to create as many temp REGs as possible. This makes it
1394 possible for half-built constants to be used later when
1395 such values are similar to something required later on.
1396 Without doing this, the optimizer cannot see such
1397 opportunities. */
2a01c939
DM		 1398
1399static void sparc_emit_set_const64_quick1
1400 PROTO((rtx, rtx, unsigned HOST_WIDE_INT, int));
1401
e0d80184
DM		 1402static void
1403sparc_emit_set_const64_quick1 (op0, temp, low_bits, is_neg)
1404 rtx op0;
1405 rtx temp;
2a01c939 1406 unsigned HOST_WIDE_INT low_bits;
e0d80184
DM		 1407 int is_neg;
1408{
2a01c939 1409 unsigned HOST_WIDE_INT high_bits;
a9e27770 1410
e0d80184 1411 if (is_neg)
2a01c939 1412 high_bits = (~low_bits) & 0xffffffff;
31bc9eba 1413 else
e0d80184 1414 high_bits = low_bits;
31bc9eba 1415
9208e4b2 1416 sparc_emit_set_safe_HIGH64 (temp, high_bits);
e0d80184 1417 if (!is_neg)
5108f3e5
DM		 1418 {
1419 emit_insn (gen_rtx_SET (VOIDmode, op0,
1420 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
1421 }
e0d80184 1422 else
5108f3e5
DM		 1423 {
1424 /* If we are XOR'ing with -1, then we should emit a one's complement
1425 instead. This way the combiner will notice logical operations
1426 such as ANDN later on and substitute. */
1427 if ((low_bits & 0x3ff) == 0x3ff)
1428 {
1429 emit_insn (gen_rtx_SET (VOIDmode, op0,
1430 gen_rtx_NOT (DImode, temp)));
1431 }
1432 else
1433 {
1434 emit_insn (gen_rtx_SET (VOIDmode, op0,
1435 gen_safe_XOR64 (temp,
1436 (-0x400 | (low_bits & 0x3ff)))));
1437 }
1438 }
e0d80184 1439}
61a55e8b 1440
2a01c939
DM		 1441static void sparc_emit_set_const64_quick2
1442 PROTO((rtx, rtx, unsigned HOST_WIDE_INT,
1443 unsigned HOST_WIDE_INT, int));
1444
e0d80184
DM		 1445static void
1446sparc_emit_set_const64_quick2 (op0, temp, high_bits, low_immediate, shift_count)
1447 rtx op0;
1448 rtx temp;
2a01c939
DM		 1449 unsigned HOST_WIDE_INT high_bits;
1450 unsigned HOST_WIDE_INT low_immediate;
e0d80184
DM		 1451 int shift_count;
1452{
1453 rtx temp2 = op0;
61a55e8b 1454
e0d80184
DM		 1455 if ((high_bits & 0xfffffc00) != 0)
1456 {
9208e4b2 1457 sparc_emit_set_safe_HIGH64 (temp, high_bits);
e0d80184 1458 if ((high_bits & ~0xfffffc00) != 0)
9208e4b2
DM		 1459 emit_insn (gen_rtx_SET (VOIDmode, op0,
1460 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
61a55e8b 1461 else
e0d80184 1462 temp2 = temp;
61a55e8b
DE		 1463 }
1464 else
1465 {
f710f868 1466 emit_insn (gen_safe_SET64 (temp, high_bits));
e0d80184
DM		 1467 temp2 = temp;
1468 }
61a55e8b 1469
e0d80184 1470 /* Now shift it up into place. */
9208e4b2 1471 emit_insn (gen_rtx_SET (VOIDmode, op0,
e0d80184
DM		 1472 gen_rtx_ASHIFT (DImode, temp2,
1473 GEN_INT (shift_count))));
61a55e8b 1474
e0d80184
DM		 1475 /* If there is a low immediate part piece, finish up by
1476 putting that in as well. */
1477 if (low_immediate != 0)
9208e4b2
DM		 1478 emit_insn (gen_rtx_SET (VOIDmode, op0,
1479 gen_safe_OR64 (op0, low_immediate)));
ab835497
RK		 1480}
1481
2a01c939
DM		 1482static void sparc_emit_set_const64_longway
1483 PROTO((rtx, rtx, unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT));
1484
e0d80184
DM		 1485/* Full 64-bit constant decomposition. Even though this is the
1486 'worst' case, we still optimize a few things away. */
1487static void
1488sparc_emit_set_const64_longway (op0, temp, high_bits, low_bits)
1489 rtx op0;
1490 rtx temp;
2a01c939
DM		 1491 unsigned HOST_WIDE_INT high_bits;
1492 unsigned HOST_WIDE_INT low_bits;
ab835497 1493{
e0d80184 1494 rtx sub_temp;
4bf7135b 1495
e0d80184
DM		 1496 if (reload_in_progress || reload_completed)
1497 sub_temp = op0;
1498 else
1499 sub_temp = gen_reg_rtx (DImode);
1500
1501 if ((high_bits & 0xfffffc00) != 0)
1502 {
9208e4b2 1503 sparc_emit_set_safe_HIGH64 (temp, high_bits);
e0d80184 1504 if ((high_bits & ~0xfffffc00) != 0)
9208e4b2 1505 emit_insn (gen_rtx_SET (VOIDmode,
e0d80184 1506 sub_temp,
9208e4b2 1507 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
e0d80184
DM		 1508 else
1509 sub_temp = temp;
1510 }
1511 else
ab835497 1512 {
f710f868 1513 emit_insn (gen_safe_SET64 (temp, high_bits));
e0d80184 1514 sub_temp = temp;
ab835497 1515 }
4bf7135b 1516
e0d80184 1517 if (!reload_in_progress && !reload_completed)
284d86e9 1518 {
e0d80184
DM		 1519 rtx temp2 = gen_reg_rtx (DImode);
1520 rtx temp3 = gen_reg_rtx (DImode);
1521 rtx temp4 = gen_reg_rtx (DImode);
284d86e9 1522
9208e4b2 1523 emit_insn (gen_rtx_SET (VOIDmode, temp4,
e0d80184
DM		 1524 gen_rtx_ASHIFT (DImode, sub_temp,
1525 GEN_INT (32))));
4bf7135b 1526
9208e4b2 1527 sparc_emit_set_safe_HIGH64 (temp2, low_bits);
e0d80184 1528 if ((low_bits & ~0xfffffc00) != 0)
f710f868
DM		 1529 {
1530 emit_insn (gen_rtx_SET (VOIDmode, temp3,
1531 gen_safe_OR64 (temp2, (low_bits & 0x3ff))));
1532 emit_insn (gen_rtx_SET (VOIDmode, op0,
1533 gen_rtx_PLUS (DImode, temp4, temp3)));
1534 }
1535 else
1536 {
1537 emit_insn (gen_rtx_SET (VOIDmode, op0,
1538 gen_rtx_PLUS (DImode, temp4, temp2)));
1539 }
284d86e9 1540 }
e0d80184
DM		 1541 else
1542 {
9208e4b2
DM		 1543 rtx low1 = GEN_INT ((low_bits >> (32 - 12)) & 0xfff);
1544 rtx low2 = GEN_INT ((low_bits >> (32 - 12 - 12)) & 0xfff);
1545 rtx low3 = GEN_INT ((low_bits >> (32 - 12 - 12 - 8)) & 0x0ff);
e0d80184 1546 int to_shift = 12;
284d86e9 1547
e0d80184
DM		 1548 /* We are in the middle of reload, so this is really
1549 painful. However we do still make an attempt to
5108f3e5 1550 avoid emitting truly stupid code. */
e0d80184
DM		 1551 if (low1 != const0_rtx)
1552 {
9208e4b2 1553 emit_insn (gen_rtx_SET (VOIDmode, op0,
e0d80184 1554 gen_rtx_ASHIFT (DImode, sub_temp,
2a01c939 1555 GEN_INT (to_shift))));
9208e4b2 1556 emit_insn (gen_rtx_SET (VOIDmode, op0,
e0d80184
DM		 1557 gen_rtx_IOR (DImode, op0, low1)));
1558 sub_temp = op0;
1559 to_shift = 12;
1560 }
1561 else
1562 {
1563 to_shift += 12;
1564 }
1565 if (low2 != const0_rtx)
1566 {
9208e4b2 1567 emit_insn (gen_rtx_SET (VOIDmode, op0,
e0d80184
DM		 1568 gen_rtx_ASHIFT (DImode, sub_temp,
1569 GEN_INT (to_shift))));
9208e4b2 1570 emit_insn (gen_rtx_SET (VOIDmode, op0,
e0d80184
DM		 1571 gen_rtx_IOR (DImode, op0, low2)));
1572 sub_temp = op0;
1573 to_shift = 8;
1574 }
1575 else
1576 {
1577 to_shift += 8;
1578 }
9208e4b2 1579 emit_insn (gen_rtx_SET (VOIDmode, op0,
e0d80184
DM		 1580 gen_rtx_ASHIFT (DImode, sub_temp,
1581 GEN_INT (to_shift))));
1582 if (low3 != const0_rtx)
9208e4b2 1583 emit_insn (gen_rtx_SET (VOIDmode, op0,
e0d80184
DM		 1584 gen_rtx_IOR (DImode, op0, low3)));
1585 /* phew... */
1586 }
284d86e9
JC		 1587}
1588
e0d80184 1589/* Analyze a 64-bit constant for certain properties. */
2a01c939
DM		 1590static void analyze_64bit_constant
1591 PROTO((unsigned HOST_WIDE_INT,
1592 unsigned HOST_WIDE_INT,
1593 int *, int *, int *));
1594
e0d80184
DM		 1595static void
1596analyze_64bit_constant (high_bits, low_bits, hbsp, lbsp, abbasp)
2a01c939 1597 unsigned HOST_WIDE_INT high_bits, low_bits;
e0d80184 1598 int *hbsp, *lbsp, *abbasp;
ab835497 1599{
e0d80184
DM		 1600 int lowest_bit_set, highest_bit_set, all_bits_between_are_set;
1601 int i;
ab835497 1602
e0d80184
DM		 1603 lowest_bit_set = highest_bit_set = -1;
1604 i = 0;
1605 do
ab835497 1606 {
e0d80184
DM		 1607 if ((lowest_bit_set == -1)
1608 && ((low_bits >> i) & 1))
1609 lowest_bit_set = i;
1610 if ((highest_bit_set == -1)
1611 && ((high_bits >> (32 - i - 1)) & 1))
1612 highest_bit_set = (64 - i - 1);
1613 }
1614 while (++i < 32
1615 && ((highest_bit_set == -1)
1616 || (lowest_bit_set == -1)));
1617 if (i == 32)
1618 {
1619 i = 0;
1620 do
ab835497 1621 {
e0d80184
DM		 1622 if ((lowest_bit_set == -1)
1623 && ((high_bits >> i) & 1))
1624 lowest_bit_set = i + 32;
1625 if ((highest_bit_set == -1)
1626 && ((low_bits >> (32 - i - 1)) & 1))
1627 highest_bit_set = 32 - i - 1;
ab835497 1628 }
e0d80184
DM		 1629 while (++i < 32
1630 && ((highest_bit_set == -1)
1631 || (lowest_bit_set == -1)));
1632 }
1633 /* If there are no bits set this should have gone out
1634 as one instruction! */
1635 if (lowest_bit_set == -1
1636 || highest_bit_set == -1)
9208e4b2 1637 abort ();
e0d80184
DM		 1638 all_bits_between_are_set = 1;
1639 for (i = lowest_bit_set; i <= highest_bit_set; i++)
1640 {
1641 if (i < 32)
1642 {
1643 if ((low_bits & (1 << i)) != 0)
1644 continue;
1645 }
1646 else
1647 {
1648 if ((high_bits & (1 << (i - 32))) != 0)
1649 continue;
1650 }
1651 all_bits_between_are_set = 0;
1652 break;
ab835497 1653 }
e0d80184
DM		 1654 *hbsp = highest_bit_set;
1655 *lbsp = lowest_bit_set;
1656 *abbasp = all_bits_between_are_set;
ab835497 1657}
6a4bb1fa 1658
2a01c939
DM		 1659static int const64_is_2insns
1660 PROTO((unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT));
1661
e0d80184
DM		 1662static int
1663const64_is_2insns (high_bits, low_bits)
2a01c939 1664 unsigned HOST_WIDE_INT high_bits, low_bits;
e0d80184
DM		 1665{
1666 int highest_bit_set, lowest_bit_set, all_bits_between_are_set;
284d86e9 1667
e0d80184 1668 if (high_bits == 0
2a01c939 1669 || high_bits == 0xffffffff)
e0d80184 1670 return 1;
6a4bb1fa 1671
e0d80184
DM		 1672 analyze_64bit_constant (high_bits, low_bits,
1673 &highest_bit_set, &lowest_bit_set,
1674 &all_bits_between_are_set);
6a4bb1fa 1675
f710f868
DM		 1676 if ((highest_bit_set == 63
1677 || lowest_bit_set == 0)
e0d80184
DM		 1678 && all_bits_between_are_set != 0)
1679 return 1;
6a4bb1fa 1680
9208e4b2
DM		 1681 if ((highest_bit_set - lowest_bit_set) < 21)
1682 return 1;
1683
6a4bb1fa
DE		 1684 return 0;
1685}
1686
2a01c939
DM		 1687static unsigned HOST_WIDE_INT create_simple_focus_bits
1688 PROTO((unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT,
ddf80874 1689 int, int));
2a01c939
DM		 1690
1691static unsigned HOST_WIDE_INT
ddf80874 1692create_simple_focus_bits (high_bits, low_bits, lowest_bit_set, shift)
2a01c939 1693 unsigned HOST_WIDE_INT high_bits, low_bits;
ddf80874 1694 int lowest_bit_set, shift;
ab835497 1695{
f710f868 1696 HOST_WIDE_INT hi, lo;
ab835497 1697
e0d80184
DM		 1698 if (lowest_bit_set < 32)
1699 {
1700 lo = (low_bits >> lowest_bit_set) << shift;
1701 hi = ((high_bits << (32 - lowest_bit_set)) << shift);
1702 }
1703 else
1704 {
1705 lo = 0;
1706 hi = ((high_bits >> (lowest_bit_set - 32)) << shift);
1707 }
1708 if (hi & lo)
9208e4b2 1709 abort ();
e0d80184
DM		 1710 return (hi | lo);
1711}
ab835497 1712
e0d80184
DM		 1713/* Here we are sure to be arch64 and this is an integer constant
1714 being loaded into a register. Emit the most efficient
1715 insn sequence possible. Detection of all the 1-insn cases
1716 has been done already. */
1717void
1718sparc_emit_set_const64 (op0, op1)
1719 rtx op0;
1720 rtx op1;
1721{
2a01c939 1722 unsigned HOST_WIDE_INT high_bits, low_bits;
e0d80184
DM		 1723 int lowest_bit_set, highest_bit_set;
1724 int all_bits_between_are_set;
e0d80184 1725 rtx temp;
ab835497 1726
e0d80184
DM		 1727 /* Sanity check that we know what we are working with. */
1728 if (! TARGET_ARCH64
1729 || GET_CODE (op0) != REG
1730 || (REGNO (op0) >= SPARC_FIRST_FP_REG
1731 && REGNO (op0) <= SPARC_LAST_V9_FP_REG))
9208e4b2 1732 abort ();
95726648 1733
f710f868
DM		 1734 if (reload_in_progress || reload_completed)
1735 temp = op0;
1736 else
1737 temp = gen_reg_rtx (DImode);
1738
e0d80184
DM		 1739 if (GET_CODE (op1) != CONST_DOUBLE
1740 && GET_CODE (op1) != CONST_INT)
1741 {
5f78aa30
JC		 1742 sparc_emit_set_symbolic_const64 (op0, op1, temp);
1743 return;
e0d80184 1744 }
ab835497 1745
e0d80184
DM		 1746 if (GET_CODE (op1) == CONST_DOUBLE)
1747 {
1748#if HOST_BITS_PER_WIDE_INT == 64
2a01c939 1749 high_bits = (CONST_DOUBLE_LOW (op1) >> 32) & 0xffffffff;
e0d80184
DM		 1750 low_bits = CONST_DOUBLE_LOW (op1) & 0xffffffff;
1751#else
1752 high_bits = CONST_DOUBLE_HIGH (op1);
1753 low_bits = CONST_DOUBLE_LOW (op1);
1754#endif
ab835497 1755 }
e0d80184 1756 else
ab835497 1757 {
e0d80184 1758#if HOST_BITS_PER_WIDE_INT == 64
2a01c939 1759 high_bits = ((INTVAL (op1) >> 32) & 0xffffffff);
e0d80184
DM		 1760 low_bits = (INTVAL (op1) & 0xffffffff);
1761#else
1762 high_bits = ((INTVAL (op1) < 0) ?
1763 0xffffffff :
1764 0x00000000);
1765 low_bits = INTVAL (op1);
1766#endif
1767 }
ab835497 1768
e0d80184
DM		 1769 /* low_bits bits 0 --> 31
1770 high_bits bits 32 --> 63 */
ab835497 1771
e0d80184
DM		 1772 analyze_64bit_constant (high_bits, low_bits,
1773 &highest_bit_set, &lowest_bit_set,
1774 &all_bits_between_are_set);
1775
1776 /* First try for a 2-insn sequence. */
1777
1778 /* These situations are preferred because the optimizer can
1779 * do more things with them:
1780 * 1) mov -1, %reg
1781 * sllx %reg, shift, %reg
1782 * 2) mov -1, %reg
1783 * srlx %reg, shift, %reg
1784 * 3) mov some_small_const, %reg
1785 * sllx %reg, shift, %reg
1786 */
1787 if (((highest_bit_set == 63
1788 || lowest_bit_set == 0)
1789 && all_bits_between_are_set != 0)
2a01c939 1790 || ((highest_bit_set - lowest_bit_set) < 12))
e0d80184 1791 {
9208e4b2 1792 HOST_WIDE_INT the_const = -1;
e0d80184
DM		 1793 int shift = lowest_bit_set;
1794
f710f868
DM		 1795 if ((highest_bit_set != 63
1796 && lowest_bit_set != 0)
1797 || all_bits_between_are_set == 0)
ab835497 1798 {
e0d80184 1799 the_const =
9208e4b2 1800 create_simple_focus_bits (high_bits, low_bits,
9208e4b2 1801 lowest_bit_set, 0);
ab835497 1802 }
e0d80184 1803 else if (lowest_bit_set == 0)
9208e4b2 1804 shift = -(63 - highest_bit_set);
e0d80184 1805
f710f868
DM		 1806 if (! SPARC_SIMM13_P (the_const))
1807 abort ();
1808
9208e4b2 1809 emit_insn (gen_safe_SET64 (temp, the_const));
e0d80184 1810 if (shift > 0)
9208e4b2 1811 emit_insn (gen_rtx_SET (VOIDmode,
e0d80184
DM		 1812 op0,
1813 gen_rtx_ASHIFT (DImode,
1814 temp,
1815 GEN_INT (shift))));
1816 else if (shift < 0)
9208e4b2 1817 emit_insn (gen_rtx_SET (VOIDmode,
e0d80184 1818 op0,
9208e4b2 1819 gen_rtx_LSHIFTRT (DImode,
e0d80184
DM		 1820 temp,
1821 GEN_INT (-shift))));
ab835497
RK		 1822 else
1823 abort ();
e0d80184
DM		 1824 return;
1825 }
ab835497 1826
e0d80184
DM		 1827 /* Now a range of 22 or less bits set somewhere.
1828 * 1) sethi %hi(focus_bits), %reg
1829 * sllx %reg, shift, %reg
1830 * 2) sethi %hi(focus_bits), %reg
1831 * srlx %reg, shift, %reg
1832 */
2a01c939 1833 if ((highest_bit_set - lowest_bit_set) < 21)
e0d80184 1834 {
2a01c939 1835 unsigned HOST_WIDE_INT focus_bits =
e0d80184 1836 create_simple_focus_bits (high_bits, low_bits,
ddf80874 1837 lowest_bit_set, 10);
f710f868
DM		 1838
1839 if (! SPARC_SETHI_P (focus_bits))
1840 abort ();
1841
9208e4b2 1842 sparc_emit_set_safe_HIGH64 (temp, focus_bits);
e0d80184 1843
9208e4b2 1844 /* If lowest_bit_set == 10 then a sethi alone could have done it. */
e0d80184 1845 if (lowest_bit_set < 10)
9208e4b2 1846 emit_insn (gen_rtx_SET (VOIDmode,
e0d80184 1847 op0,
9208e4b2 1848 gen_rtx_LSHIFTRT (DImode, temp,
e0d80184 1849 GEN_INT (10 - lowest_bit_set))));
9208e4b2
DM		 1850 else if (lowest_bit_set > 10)
1851 emit_insn (gen_rtx_SET (VOIDmode,
e0d80184
DM		 1852 op0,
1853 gen_rtx_ASHIFT (DImode, temp,
1854 GEN_INT (lowest_bit_set - 10))));
1855 else
9208e4b2 1856 abort ();
e0d80184
DM		 1857 return;
1858 }
1859
1860 /* 1) sethi %hi(low_bits), %reg
1861 * or %reg, %lo(low_bits), %reg
1862 * 2) sethi %hi(~low_bits), %reg
1863 * xor %reg, %lo(-0x400 | (low_bits & 0x3ff)), %reg
1864 */
1865 if (high_bits == 0
2a01c939 1866 || high_bits == 0xffffffff)
5f78aa30
JC		 1867 {
1868 sparc_emit_set_const64_quick1 (op0, temp, low_bits,
1869 (high_bits == 0xffffffff));
1870 return;
1871 }
e0d80184 1872
f710f868
DM		 1873 /* Now, try 3-insn sequences. */
1874
e0d80184
DM		 1875 /* 1) sethi %hi(high_bits), %reg
1876 * or %reg, %lo(high_bits), %reg
1877 * sllx %reg, 32, %reg
1878 */
f710f868 1879 if (low_bits == 0)
5f78aa30 1880 {
f710f868 1881 sparc_emit_set_const64_quick2 (op0, temp, high_bits, 0, 32);
5f78aa30
JC		 1882 return;
1883 }
e0d80184 1884
f710f868
DM		 1885 /* We may be able to do something quick
1886 when the constant is negated, so try that. */
e0d80184
DM		 1887 if (const64_is_2insns ((~high_bits) & 0xffffffff,
1888 (~low_bits) & 0xfffffc00))
1889 {
5108f3e5
DM		 1890 /* NOTE: The trailing bits get XOR'd so we need the
1891 non-negated bits, not the negated ones. */
1892 unsigned HOST_WIDE_INT trailing_bits = low_bits & 0x3ff;
e0d80184
DM		 1893
1894 if ((((~high_bits) & 0xffffffff) == 0
1895 && ((~low_bits) & 0x80000000) == 0)
1896 || (((~high_bits) & 0xffffffff) == 0xffffffff
1897 && ((~low_bits) & 0x80000000) != 0))
ab835497 1898 {
5108f3e5 1899 int fast_int = (~low_bits & 0xffffffff);
e0d80184 1900
5108f3e5
DM		 1901 if ((SPARC_SETHI_P (fast_int)
1902 && (~high_bits & 0xffffffff) == 0)
1903 || SPARC_SIMM13_P (fast_int))
9208e4b2 1904 emit_insn (gen_safe_SET64 (temp, fast_int));
ab835497 1905 else
9208e4b2 1906 sparc_emit_set_const64 (temp, GEN_INT64 (fast_int));
ab835497 1907 }
e0d80184
DM		 1908 else
1909 {
1910 rtx negated_const;
1911#if HOST_BITS_PER_WIDE_INT == 64
1912 negated_const = GEN_INT (((~low_bits) & 0xfffffc00) |
1913 (((HOST_WIDE_INT)((~high_bits) & 0xffffffff))<<32));
1914#else
9208e4b2 1915 negated_const = gen_rtx_CONST_DOUBLE (DImode, const0_rtx,
e0d80184
DM		 1916 (~low_bits) & 0xfffffc00,
1917 (~high_bits) & 0xffffffff);
1918#endif
1919 sparc_emit_set_const64 (temp, negated_const);
1920 }
5108f3e5
DM		 1921
1922 /* If we are XOR'ing with -1, then we should emit a one's complement
1923 instead. This way the combiner will notice logical operations
1924 such as ANDN later on and substitute. */
1925 if (trailing_bits == 0x3ff)
1926 {
1927 emit_insn (gen_rtx_SET (VOIDmode, op0,
1928 gen_rtx_NOT (DImode, temp)));
1929 }
1930 else
1931 {
1932 emit_insn (gen_rtx_SET (VOIDmode,
1933 op0,
1934 gen_safe_XOR64 (temp,
1935 (-0x400 | trailing_bits))));
1936 }
e0d80184 1937 return;
ab835497 1938 }
ab835497 1939
e0d80184
DM		 1940 /* 1) sethi %hi(xxx), %reg
1941 * or %reg, %lo(xxx), %reg
1942 * sllx %reg, yyy, %reg
f710f868
DM		 1943 *
1944 * ??? This is just a generalized version of the low_bits==0
1945 * thing above, FIXME...
e0d80184
DM		 1946 */
1947 if ((highest_bit_set - lowest_bit_set) < 32)
1948 {
f710f868
DM		 1949 unsigned HOST_WIDE_INT focus_bits =
1950 create_simple_focus_bits (high_bits, low_bits,
ddf80874 1951 lowest_bit_set, 0);
ab835497 1952
e0d80184
DM		 1953 /* We can't get here in this state. */
1954 if (highest_bit_set < 32
1955 || lowest_bit_set >= 32)
9208e4b2 1956 abort ();
95726648 1957
e0d80184
DM		 1958 /* So what we know is that the set bits straddle the
1959 middle of the 64-bit word. */
5f78aa30
JC		 1960 sparc_emit_set_const64_quick2 (op0, temp,
1961 focus_bits, 0,
1962 lowest_bit_set);
1963 return;
e0d80184 1964 }
c85f7c16 1965
f710f868
DM		 1966 /* 1) sethi %hi(high_bits), %reg
1967 * or %reg, %lo(high_bits), %reg
1968 * sllx %reg, 32, %reg
1969 * or %reg, low_bits, %reg
1970 */
1971 if (SPARC_SIMM13_P(low_bits)
1972 && ((int)low_bits > 0))
1973 {
1974 sparc_emit_set_const64_quick2 (op0, temp, high_bits, low_bits, 32);
1975 return;
1976 }
1977
e0d80184
DM		 1978 /* The easiest way when all else fails, is full decomposition. */
1979#if 0
1980 printf ("sparc_emit_set_const64: Hard constant [%08lx%08lx] neg[%08lx%08lx]\n",
1981 high_bits, low_bits, ~high_bits, ~low_bits);
1982#endif
1983 sparc_emit_set_const64_longway (op0, temp, high_bits, low_bits);
c85f7c16
JL		 1984}
1985
e0d80184
DM		 1986/* X and Y are two things to compare using CODE. Emit the compare insn and
1987 return the rtx for the cc reg in the proper mode. */
c85f7c16 1988
e0d80184
DM		 1989rtx
1990gen_compare_reg (code, x, y)
1991 enum rtx_code code;
1992 rtx x, y;
c85f7c16 1993{
e0d80184
DM		 1994 enum machine_mode mode = SELECT_CC_MODE (code, x, y);
1995 rtx cc_reg;
c85f7c16 1996
e0d80184
DM		 1997 /* ??? We don't have movcc patterns so we cannot generate pseudo regs for the
1998 fcc regs (cse can't tell they're really call clobbered regs and will
1999 remove a duplicate comparison even if there is an intervening function
2000 call - it will then try to reload the cc reg via an int reg which is why
2001 we need the movcc patterns). It is possible to provide the movcc
2002 patterns by using the ldxfsr/stxfsr v9 insns. I tried it: you need two
2003 registers (say %g1,%g5) and it takes about 6 insns. A better fix would be
2004 to tell cse that CCFPE mode registers (even pseudos) are call
2005 clobbered. */
c85f7c16 2006
e0d80184
DM		 2007 /* ??? This is an experiment. Rather than making changes to cse which may
2008 or may not be easy/clean, we do our own cse. This is possible because
2009 we will generate hard registers. Cse knows they're call clobbered (it
2010 doesn't know the same thing about pseudos). If we guess wrong, no big
2011 deal, but if we win, great! */
c85f7c16 2012
e0d80184
DM		 2013 if (TARGET_V9 && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2014#if 1 /* experiment */
284d86e9 2015 {
e0d80184
DM		 2016 int reg;
2017 /* We cycle through the registers to ensure they're all exercised. */
2018 static int next_fcc_reg = 0;
2019 /* Previous x,y for each fcc reg. */
2020 static rtx prev_args[4][2];
284d86e9 2021
e0d80184
DM		 2022 /* Scan prev_args for x,y. */
2023 for (reg = 0; reg < 4; reg++)
2024 if (prev_args[reg][0] == x && prev_args[reg][1] == y)
2025 break;
2026 if (reg == 4)
2027 {
2028 reg = next_fcc_reg;
2029 prev_args[reg][0] = x;
2030 prev_args[reg][1] = y;
2031 next_fcc_reg = (next_fcc_reg + 1) & 3;
2032 }
2033 cc_reg = gen_rtx_REG (mode, reg + SPARC_FIRST_V9_FCC_REG);
284d86e9 2034 }
e0d80184
DM		 2035#else
2036 cc_reg = gen_reg_rtx (mode);
2037#endif /* ! experiment */
2038 else if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2039 cc_reg = gen_rtx_REG (mode, SPARC_FCC_REG);
2040 else
2041 cc_reg = gen_rtx_REG (mode, SPARC_ICC_REG);
284d86e9 2042
e0d80184
DM		 2043 emit_insn (gen_rtx_SET (VOIDmode, cc_reg,
2044 gen_rtx_COMPARE (mode, x, y)));
c85f7c16 2045
e0d80184
DM		 2046 return cc_reg;
2047}
c85f7c16 2048
e0d80184
DM		 2049/* This function is used for v9 only.
2050 CODE is the code for an Scc's comparison.
2051 OPERANDS[0] is the target of the Scc insn.
2052 OPERANDS[1] is the value we compare against const0_rtx (which hasn't
2053 been generated yet).
c85f7c16 2054
e0d80184 2055 This function is needed to turn
ab835497 2056
e0d80184
DM		 2057 (set (reg:SI 110)
2058 (gt (reg:CCX 100 %icc)
2059 (const_int 0)))
2060 into
2061 (set (reg:SI 110)
2062 (gt:DI (reg:CCX 100 %icc)
2063 (const_int 0)))
2064
2065 IE: The instruction recognizer needs to see the mode of the comparison to
2066 find the right instruction. We could use "gt:DI" right in the
2067 define_expand, but leaving it out allows us to handle DI, SI, etc.
ab835497 2068
e0d80184
DM		 2069 We refer to the global sparc compare operands sparc_compare_op0 and
2070 sparc_compare_op1. */
ab835497
RK		 2071
2072int
e0d80184
DM		 2073gen_v9_scc (compare_code, operands)
2074 enum rtx_code compare_code;
2075 register rtx *operands;
ab835497 2076{
e0d80184 2077 rtx temp, op0, op1;
ab835497 2078
e0d80184
DM		 2079 if (! TARGET_ARCH64
2080 && (GET_MODE (sparc_compare_op0) == DImode
2081 || GET_MODE (operands[0]) == DImode))
2082 return 0;
7e2feebf 2083
e0d80184
DM		 2084 /* Handle the case where operands[0] == sparc_compare_op0.
2085 We "early clobber" the result. */
2086 if (REGNO (operands[0]) == REGNO (sparc_compare_op0))
ab835497 2087 {
e0d80184
DM		 2088 op0 = gen_reg_rtx (GET_MODE (sparc_compare_op0));
2089 emit_move_insn (op0, sparc_compare_op0);
ab835497 2090 }
e0d80184
DM		 2091 else
2092 op0 = sparc_compare_op0;
2093 /* For consistency in the following. */
2094 op1 = sparc_compare_op1;
2095
2096 /* Try to use the movrCC insns. */
2097 if (TARGET_ARCH64
2098 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
2099 && op1 == const0_rtx
2100 && v9_regcmp_p (compare_code))
ab835497 2101 {
e0d80184
DM		 2102 /* Special case for op0 != 0. This can be done with one instruction if
2103 operands[0] == sparc_compare_op0. We don't assume they are equal
2104 now though. */
2105
2106 if (compare_code == NE
2107 && GET_MODE (operands[0]) == DImode
2108 && GET_MODE (op0) == DImode)
ab835497 2109 {
e0d80184
DM		 2110 emit_insn (gen_rtx_SET (VOIDmode, operands[0], op0));
2111 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2112 gen_rtx_IF_THEN_ELSE (DImode,
2113 gen_rtx_fmt_ee (compare_code, DImode,
2114 op0, const0_rtx),
2115 const1_rtx,
2116 operands[0])));
ab835497
RK		 2117 return 1;
2118 }
e0d80184
DM		 2119
2120 emit_insn (gen_rtx_SET (VOIDmode, operands[0], const0_rtx));
2121 if (GET_MODE (op0) != DImode)
ab835497 2122 {
e0d80184
DM		 2123 temp = gen_reg_rtx (DImode);
2124 convert_move (temp, op0, 0);
ab835497 2125 }
e0d80184
DM		 2126 else
2127 temp = op0;
2128 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2129 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]),
2130 gen_rtx_fmt_ee (compare_code, DImode,
2131 temp, const0_rtx),
2132 const1_rtx,
2133 operands[0])));
95726648
DE		 2134 return 1;
2135 }
e0d80184 2136 else
ab835497 2137 {
e0d80184 2138 operands[1] = gen_compare_reg (compare_code, op0, op1);
ab835497 2139
e0d80184 2140 switch (GET_MODE (operands[1]))
ab835497 2141 {
e0d80184
DM		 2142 case CCmode :
2143 case CCXmode :
2144 case CCFPEmode :
2145 case CCFPmode :
2146 break;
2147 default :
2148 abort ();
ab835497 2149 }
e0d80184
DM		 2150 emit_insn (gen_rtx_SET (VOIDmode, operands[0], const0_rtx));
2151 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2152 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]),
2153 gen_rtx_fmt_ee (compare_code,
2154 GET_MODE (operands[1]),
2155 operands[1], const0_rtx),
2156 const1_rtx, operands[0])));
2157 return 1;
ab835497 2158 }
ab835497 2159}
4fb4e4b8 2160
e0d80184
DM		 2161/* Emit a conditional jump insn for the v9 architecture using comparison code
2162 CODE and jump target LABEL.
2163 This function exists to take advantage of the v9 brxx insns. */
ab835497 2164
e0d80184
DM		 2165void
2166emit_v9_brxx_insn (code, op0, label)
2167 enum rtx_code code;
2168 rtx op0, label;
ab835497 2169{
e0d80184
DM		 2170 emit_jump_insn (gen_rtx_SET (VOIDmode,
2171 pc_rtx,
2172 gen_rtx_IF_THEN_ELSE (VOIDmode,
2173 gen_rtx_fmt_ee (code, GET_MODE (op0),
2174 op0, const0_rtx),
2175 gen_rtx_LABEL_REF (VOIDmode, label),
2176 pc_rtx)));
2177}
2178\f
2179/* Return nonzero if a return peephole merging return with
2180 setting of output register is ok. */
2181int
2182leaf_return_peephole_ok ()
2183{
2184 return (actual_fsize == 0);
2185}
284d86e9 2186
e0d80184
DM		 2187/* Return nonzero if TRIAL can go into the function epilogue's
2188 delay slot. SLOT is the slot we are trying to fill. */
ab835497 2189
e0d80184
DM		 2190int
2191eligible_for_epilogue_delay (trial, slot)
2192 rtx trial;
2193 int slot;
2194{
2195 rtx pat, src;
4fb4e4b8 2196
e0d80184
DM		 2197 if (slot >= 1)
2198 return 0;
4fb4e4b8 2199
e0d80184
DM		 2200 if (GET_CODE (trial) != INSN || GET_CODE (PATTERN (trial)) != SET)
2201 return 0;
4fb4e4b8 2202
e0d80184
DM		 2203 if (get_attr_length (trial) != 1)
2204 return 0;
4fb4e4b8 2205
e0d80184
DM		 2206 /* If %g0 is live, there are lots of things we can't handle.
2207 Rather than trying to find them all now, let's punt and only
2208 optimize things as necessary. */
2209 if (TARGET_LIVE_G0)
2210 return 0;
4fb4e4b8 2211
e0d80184
DM		 2212 /* In the case of a true leaf function, anything can go into the delay slot.
2213 A delay slot only exists however if the frame size is zero, otherwise
2214 we will put an insn to adjust the stack after the return. */
54ff41b7 2215 if (current_function_uses_only_leaf_regs)
4fb4e4b8 2216 {
e0d80184
DM		 2217 if (leaf_return_peephole_ok ())
2218 return ((get_attr_in_uncond_branch_delay (trial)
2219 == IN_BRANCH_DELAY_TRUE));
2220 return 0;
4fb4e4b8 2221 }
4fb4e4b8 2222
e0d80184
DM		 2223 /* If only trivial `restore' insns work, nothing can go in the
2224 delay slot. */
2225 else if (TARGET_BROKEN_SAVERESTORE)
2226 return 0;
795068a4 2227
e0d80184 2228 pat = PATTERN (trial);
795068a4 2229
e0d80184
DM		 2230 /* Otherwise, only operations which can be done in tandem with
2231 a `restore' insn can go into the delay slot. */
2232 if (GET_CODE (SET_DEST (pat)) != REG
2233 || REGNO (SET_DEST (pat)) >= 32
2234 || REGNO (SET_DEST (pat)) < 24)
2235 return 0;
795068a4 2236
e0d80184
DM		 2237 /* The set of insns matched here must agree precisely with the set of
2238 patterns paired with a RETURN in sparc.md. */
795068a4 2239
e0d80184 2240 src = SET_SRC (pat);
795068a4 2241
3c6088d2 2242 /* This matches "*return_[qhs]i" or even "*return_di" on TARGET_ARCH64. */
e0d80184 2243 if (arith_operand (src, GET_MODE (src)))
3c6088d2
JJ		 2244 {
2245 if (TARGET_ARCH64)
2246 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
2247 else
2248 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (SImode);
2249 }
e0d80184
DM		 2250
2251 /* This matches "*return_di". */
2252 else if (arith_double_operand (src, GET_MODE (src)))
2253 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
795068a4 2254
e0d80184
DM		 2255 /* This matches "*return_sf_no_fpu". */
2256 else if (! TARGET_FPU && restore_operand (SET_DEST (pat), SFmode)
2257 && register_operand (src, SFmode))
2258 return 1;
f5da225e 2259
e0d80184
DM		 2260 /* This matches "*return_addsi". */
2261 else if (GET_CODE (src) == PLUS
2262 && arith_operand (XEXP (src, 0), SImode)
2263 && arith_operand (XEXP (src, 1), SImode)
2264 && (register_operand (XEXP (src, 0), SImode)
2265 || register_operand (XEXP (src, 1), SImode)))
2266 return 1;
2267
2268 /* This matches "*return_adddi". */
2269 else if (GET_CODE (src) == PLUS
2270 && arith_double_operand (XEXP (src, 0), DImode)
2271 && arith_double_operand (XEXP (src, 1), DImode)
2272 && (register_operand (XEXP (src, 0), DImode)
2273 || register_operand (XEXP (src, 1), DImode)))
795068a4 2274 return 1;
795068a4 2275
795068a4
JW		 2276 return 0;
2277}
2278
e0d80184
DM		 2279static int
2280check_return_regs (x)
2281 rtx x;
ab835497 2282{
e0d80184
DM		 2283 switch (GET_CODE (x))
2284 {
2285 case REG:
2286 return IN_OR_GLOBAL_P (x);
ab835497 2287
e0d80184
DM		 2288 case CONST_INT:
2289 case CONST_DOUBLE:
2290 case CONST:
2291 case SYMBOL_REF:
2292 case LABEL_REF:
2293 return 1;
ab835497 2294
e0d80184
DM		 2295 case SET:
2296 case IOR:
2297 case AND:
2298 case XOR:
2299 case PLUS:
2300 case MINUS:
2301 if (check_return_regs (XEXP (x, 1)) == 0)
2302 return 0;
2303 case NOT:
2304 case NEG:
2305 case MEM:
2306 return check_return_regs (XEXP (x, 0));
2307
2308 default:
2309 return 0;
2310 }
ab835497 2311
e0d80184 2312}
ab835497 2313
e0d80184
DM		 2314/* Return 1 if TRIAL references only in and global registers. */
2315int
2316eligible_for_return_delay (trial)
2317 rtx trial;
2318{
2319 if (GET_CODE (PATTERN (trial)) != SET)
2320 return 0;
ab835497 2321
e0d80184
DM		 2322 return check_return_regs (PATTERN (trial));
2323}
ab835497 2324
e0d80184
DM		 2325int
2326short_branch (uid1, uid2)
2327 int uid1, uid2;
2328{
2329 unsigned int delta = insn_addresses[uid1] - insn_addresses[uid2];
2330 if (delta + 1024 < 2048)
2331 return 1;
2332 /* warning ("long branch, distance %d", delta); */
2333 return 0;
2334}
ab835497 2335
e0d80184
DM		 2336/* Return non-zero if REG is not used after INSN.
2337 We assume REG is a reload reg, and therefore does
2338 not live past labels or calls or jumps. */
2339int
2340reg_unused_after (reg, insn)
2341 rtx reg;
2342 rtx insn;
2343{
2344 enum rtx_code code, prev_code = UNKNOWN;
ab835497 2345
e0d80184 2346 while ((insn = NEXT_INSN (insn)))
61a55e8b 2347 {
e0d80184
DM		 2348 if (prev_code == CALL_INSN && call_used_regs[REGNO (reg)])
2349 return 1;
ab835497 2350
e0d80184
DM		 2351 code = GET_CODE (insn);
2352 if (GET_CODE (insn) == CODE_LABEL)
2353 return 1;
bc961ed7 2354
e0d80184 2355 if (GET_RTX_CLASS (code) == 'i')
61a55e8b 2356 {
e0d80184
DM		 2357 rtx set = single_set (insn);
2358 int in_src = set && reg_overlap_mentioned_p (reg, SET_SRC (set));
2359 if (set && in_src)
2360 return 0;
2361 if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
2362 return 1;
2363 if (set == 0 && reg_overlap_mentioned_p (reg, PATTERN (insn)))
2364 return 0;
61a55e8b 2365 }
e0d80184 2366 prev_code = code;
61a55e8b 2367 }
e0d80184
DM		 2368 return 1;
2369}
2370\f
2371/* The table we use to reference PIC data. */
2372static rtx global_offset_table;
bc961ed7 2373
e0d80184
DM		 2374/* The function we use to get at it. */
2375static rtx get_pc_symbol;
2376static char get_pc_symbol_name[256];
ab835497 2377
e0d80184 2378/* Ensure that we are not using patterns that are not OK with PIC. */
795068a4 2379
e0d80184
DM		 2380int
2381check_pic (i)
2382 int i;
2383{
2384 switch (flag_pic)
ab835497 2385 {
e0d80184 2386 case 1:
1ccbefce
RH		 2387 if (GET_CODE (recog_data.operand[i]) == SYMBOL_REF
2388 || (GET_CODE (recog_data.operand[i]) == CONST
2389 && ! (GET_CODE (XEXP (recog_data.operand[i], 0)) == MINUS
2390 && (XEXP (XEXP (recog_data.operand[i], 0), 0)
e0d80184 2391 == global_offset_table)
1ccbefce 2392 && (GET_CODE (XEXP (XEXP (recog_data.operand[i], 0), 1))
e0d80184
DM		 2393 == CONST))))
2394 abort ();
2395 case 2:
2396 default:
2397 return 1;
ab835497 2398 }
ab835497 2399}
795068a4 2400
e0d80184
DM		 2401/* Return true if X is an address which needs a temporary register when
2402 reloaded while generating PIC code. */
795068a4 2403
e0d80184
DM		 2404int
2405pic_address_needs_scratch (x)
2406 rtx x;
795068a4 2407{
e0d80184
DM		 2408 /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */
2409 if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS
2410 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
2411 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2412 && ! SMALL_INT (XEXP (XEXP (x, 0), 1)))
2413 return 1;
795068a4 2414
e0d80184
DM		 2415 return 0;
2416}
795068a4 2417
e0d80184
DM		 2418/* Legitimize PIC addresses. If the address is already position-independent,
2419 we return ORIG. Newly generated position-independent addresses go into a
2420 reg. This is REG if non zero, otherwise we allocate register(s) as
2421 necessary. */
795068a4 2422
e0d80184
DM		 2423rtx
2424legitimize_pic_address (orig, mode, reg)
2425 rtx orig;
2426 enum machine_mode mode ATTRIBUTE_UNUSED;
2427 rtx reg;
2428{
2429 if (GET_CODE (orig) == SYMBOL_REF)
82d6b402 2430 {
e0d80184
DM		 2431 rtx pic_ref, address;
2432 rtx insn;
82d6b402 2433
e0d80184 2434 if (reg == 0)
82d6b402 2435 {
e0d80184
DM		 2436 if (reload_in_progress || reload_completed)
2437 abort ();
2438 else
2439 reg = gen_reg_rtx (Pmode);
82d6b402 2440 }
795068a4 2441
e0d80184 2442 if (flag_pic == 2)
4fb4e4b8 2443 {
e0d80184
DM		 2444 /* If not during reload, allocate another temp reg here for loading
2445 in the address, so that these instructions can be optimized
2446 properly. */
2447 rtx temp_reg = ((reload_in_progress || reload_completed)
2448 ? reg : gen_reg_rtx (Pmode));
2449
2450 /* Must put the SYMBOL_REF inside an UNSPEC here so that cse
2451 won't get confused into thinking that these two instructions
2452 are loading in the true address of the symbol. If in the
2453 future a PIC rtx exists, that should be used instead. */
be3f1ff5
DM		 2454 if (Pmode == SImode)
2455 {
2456 emit_insn (gen_movsi_high_pic (temp_reg, orig));
2457 emit_insn (gen_movsi_lo_sum_pic (temp_reg, temp_reg, orig));
2458 }
2459 else
2460 {
2461 emit_insn (gen_movdi_high_pic (temp_reg, orig));
2462 emit_insn (gen_movdi_lo_sum_pic (temp_reg, temp_reg, orig));
2463 }
e0d80184 2464 address = temp_reg;
4fb4e4b8
DE		 2465 }
2466 else
e0d80184
DM		 2467 address = orig;
2468
2469 pic_ref = gen_rtx_MEM (Pmode,
2470 gen_rtx_PLUS (Pmode,
2471 pic_offset_table_rtx, address));
2472 current_function_uses_pic_offset_table = 1;
2473 RTX_UNCHANGING_P (pic_ref) = 1;
2474 insn = emit_move_insn (reg, pic_ref);
2475 /* Put a REG_EQUAL note on this insn, so that it can be optimized
2476 by loop. */
2477 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, orig,
2478 REG_NOTES (insn));
2479 return reg;
795068a4 2480 }
e0d80184 2481 else if (GET_CODE (orig) == CONST)
795068a4 2482 {
e0d80184 2483 rtx base, offset;
795068a4 2484
e0d80184
DM		 2485 if (GET_CODE (XEXP (orig, 0)) == PLUS
2486 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
2487 return orig;
82d6b402 2488
e0d80184 2489 if (reg == 0)
4fb4e4b8 2490 {
e0d80184
DM		 2491 if (reload_in_progress || reload_completed)
2492 abort ();
2493 else
2494 reg = gen_reg_rtx (Pmode);
4fb4e4b8 2495 }
e0d80184
DM		 2496
2497 if (GET_CODE (XEXP (orig, 0)) == PLUS)
4fb4e4b8 2498 {
e0d80184
DM		 2499 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
2500 offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
2501 base == reg ? 0 : reg);
4fb4e4b8
DE		 2502 }
2503 else
61a66555
JW		 2504 abort ();
2505
e0d80184
DM		 2506 if (GET_CODE (offset) == CONST_INT)
2507 {
2508 if (SMALL_INT (offset))
2509 return plus_constant_for_output (base, INTVAL (offset));
2510 else if (! reload_in_progress && ! reload_completed)
2511 offset = force_reg (Pmode, offset);
2512 else
2513 /* If we reach here, then something is seriously wrong. */
2514 abort ();
2515 }
2516 return gen_rtx_PLUS (Pmode, base, offset);
795068a4 2517 }
e0d80184
DM		 2518 else if (GET_CODE (orig) == LABEL_REF)
2519 /* ??? Why do we do this? */
2520 /* Now movsi_pic_label_ref uses it, but we ought to be checking that
2521 the register is live instead, in case it is eliminated. */
2522 current_function_uses_pic_offset_table = 1;
795068a4 2523
e0d80184
DM		 2524 return orig;
2525}
795068a4 2526
e0d80184
DM		 2527/* Return the RTX for insns to set the PIC register. */
2528
2529static rtx
2530pic_setup_code ()
2531{
2532 rtx seq;
2533
2534 start_sequence ();
2535 emit_insn (gen_get_pc (pic_offset_table_rtx, global_offset_table,
2536 get_pc_symbol));
2537 seq = gen_sequence ();
2538 end_sequence ();
82d6b402 2539
e0d80184
DM		 2540 return seq;
2541}
795068a4 2542
e0d80184 2543/* Emit special PIC prologues and epilogues. */
795068a4 2544
e0d80184
DM		 2545void
2546finalize_pic ()
2547{
2548 /* Labels to get the PC in the prologue of this function. */
2549 int orig_flag_pic = flag_pic;
2550 rtx insn;
4fb4e4b8 2551
e0d80184
DM		 2552 if (current_function_uses_pic_offset_table == 0)
2553 return;
795068a4 2554
e0d80184
DM		 2555 if (! flag_pic)
2556 abort ();
2557
2558 /* If we havn't emitted the special get_pc helper function, do so now. */
2559 if (get_pc_symbol_name[0] == 0)
4fb4e4b8 2560 {
d676da68 2561 int align;
82d6b402 2562
d676da68 2563 ASM_GENERATE_INTERNAL_LABEL (get_pc_symbol_name, "LGETPC", 0);
e0d80184 2564 text_section ();
d676da68
DM		 2565
2566 align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT);
2567 if (align > 0)
2568 ASM_OUTPUT_ALIGN (asm_out_file, align);
e0d80184
DM		 2569 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "LGETPC", 0);
2570 fputs ("\tretl\n\tadd %o7,%l7,%l7\n", asm_out_file);
2571 }
82d6b402 2572
e0d80184
DM		 2573 /* Initialize every time through, since we can't easily
2574 know this to be permanent. */
2575 global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
2576 get_pc_symbol = gen_rtx_SYMBOL_REF (Pmode, get_pc_symbol_name);
2577 flag_pic = 0;
82d6b402 2578
e0d80184 2579 emit_insn_after (pic_setup_code (), get_insns ());
82d6b402 2580
24a43d7b
DM		 2581 /* Insert the code in each nonlocal goto receiver.
2582 If you make changes here or to the nonlocal_goto_receiver
2583 pattern, make sure the unspec_volatile numbers still
2584 match. */
e0d80184
DM		 2585 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
2586 if (GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == UNSPEC_VOLATILE
24a43d7b 2587 && XINT (PATTERN (insn), 1) == 5)
e0d80184 2588 emit_insn_after (pic_setup_code (), insn);
82d6b402 2589
e0d80184 2590 flag_pic = orig_flag_pic;
82d6b402 2591
e0d80184
DM		 2592 /* Need to emit this whether or not we obey regdecls,
2593 since setjmp/longjmp can cause life info to screw up.
2594 ??? In the case where we don't obey regdecls, this is not sufficient
2595 since we may not fall out the bottom. */
2596 emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx));
795068a4 2597}
ab835497 2598\f
e0d80184
DM		 2599/* Return 1 if RTX is a MEM which is known to be aligned to at
2600 least an 8 byte boundary. */
a3ee5899 2601
e0d80184
DM		 2602int
2603mem_min_alignment (mem, desired)
2604 rtx mem;
2605 int desired;
ab835497 2606{
e0d80184
DM		 2607 rtx addr, base, offset;
2608
2609 /* If it's not a MEM we can't accept it. */
2610 if (GET_CODE (mem) != MEM)
2611 return 0;
2612
2613 addr = XEXP (mem, 0);
2614 base = offset = NULL_RTX;
2615 if (GET_CODE (addr) == PLUS)
ab835497 2616 {
e0d80184 2617 if (GET_CODE (XEXP (addr, 0)) == REG)
61a55e8b 2618 {
e0d80184
DM		 2619 base = XEXP (addr, 0);
2620
2621 /* What we are saying here is that if the base
2622 REG is aligned properly, the compiler will make
2623 sure any REG based index upon it will be so
2624 as well. */
2625 if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
2626 offset = XEXP (addr, 1);
61a55e8b 2627 else
e0d80184 2628 offset = const0_rtx;
61a55e8b 2629 }
ab835497 2630 }
e0d80184 2631 else if (GET_CODE (addr) == REG)
ab835497 2632 {
e0d80184
DM		 2633 base = addr;
2634 offset = const0_rtx;
ab835497 2635 }
82d6b402 2636
e0d80184 2637 if (base != NULL_RTX)
795068a4 2638 {
e0d80184
DM		 2639 int regno = REGNO (base);
2640
2641 if (regno != FRAME_POINTER_REGNUM
2642 && regno != STACK_POINTER_REGNUM)
61a55e8b 2643 {
e0d80184
DM		 2644 /* Check if the compiler has recorded some information
2645 about the alignment of the base REG. If reload has
2646 completed, we already matched with proper alignments. */
49ad7cfa 2647 if (((current_function != 0
e0d80184
DM		 2648 && REGNO_POINTER_ALIGN (regno) >= desired)
2649 || reload_completed)
2650 && ((INTVAL (offset) & (desired - 1)) == 0))
2651 return 1;
61a55e8b 2652 }
795068a4 2653 else
e0d80184
DM		 2654 {
2655 if (((INTVAL (offset) - SPARC_STACK_BIAS) & (desired - 1)) == 0)
2656 return 1;
2657 }
795068a4 2658 }
e0d80184
DM		 2659 else if (! TARGET_UNALIGNED_DOUBLES
2660 || CONSTANT_P (addr)
2661 || GET_CODE (addr) == LO_SUM)
795068a4 2662 {
e0d80184
DM		 2663 /* Anything else we know is properly aligned unless TARGET_UNALIGNED_DOUBLES
2664 is true, in which case we can only assume that an access is aligned if
2665 it is to a constant address, or the address involves a LO_SUM. */
2666 return 1;
795068a4 2667 }
e0d80184
DM		 2668
2669 /* An obviously unaligned address. */
2670 return 0;
795068a4 2671}
e0d80184 2672
ab835497 2673\f
61a55e8b
DE		 2674/* Vectors to keep interesting information about registers where it can easily
2675 be got. We use to use the actual mode value as the bit number, but there
2676 are more than 32 modes now. Instead we use two tables: one indexed by
2677 hard register number, and one indexed by mode. */
2678
2679/* The purpose of sparc_mode_class is to shrink the range of modes so that
2680 they all fit (as bit numbers) in a 32 bit word (again). Each real mode is
2681 mapped into one sparc_mode_class mode. */
2682
2683enum sparc_mode_class {
61a55e8b 2684 S_MODE, D_MODE, T_MODE, O_MODE,
c4ce6853
DE		 2685 SF_MODE, DF_MODE, TF_MODE, OF_MODE,
2686 CC_MODE, CCFP_MODE
61a55e8b 2687};
ab835497 2688
61a55e8b
DE		 2689/* Modes for single-word and smaller quantities. */
2690#define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE))
2691
2692/* Modes for double-word and smaller quantities. */
2693#define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
2694
2695/* Modes for quad-word and smaller quantities. */
2696#define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
ab835497 2697
1e4eb8d1
JW		 2698/* Modes for single-float quantities. We must allow any single word or
2699 smaller quantity. This is because the fix/float conversion instructions
2700 take integer inputs/outputs from the float registers. */
2701#define SF_MODES (S_MODES)
ab835497 2702
61a55e8b
DE		 2703/* Modes for double-float and smaller quantities. */
2704#define DF_MODES (S_MODES | D_MODES)
2705
284d86e9 2706#define DF_MODES64 DF_MODES
61a55e8b
DE		 2707
2708/* Modes for double-float only quantities. */
284d86e9 2709#define DF_ONLY_MODES ((1 << (int) DF_MODE) | (1 << (int) D_MODE))
61a55e8b
DE		 2710
2711/* Modes for double-float and larger quantities. */
2712#define DF_UP_MODES (DF_ONLY_MODES | TF_ONLY_MODES)
ab835497 2713
61a55e8b
DE		 2714/* Modes for quad-float only quantities. */
2715#define TF_ONLY_MODES (1 << (int) TF_MODE)
2716
2717/* Modes for quad-float and smaller quantities. */
2718#define TF_MODES (DF_MODES | TF_ONLY_MODES)
2719
61a55e8b 2720#define TF_MODES64 (DF_MODES64 | TF_ONLY_MODES)
ab835497 2721
c4ce6853
DE		 2722/* Modes for condition codes. */
2723#define CC_MODES (1 << (int) CC_MODE)
2724#define CCFP_MODES (1 << (int) CCFP_MODE)
2725
ab835497
RK		 2726/* Value is 1 if register/mode pair is acceptable on sparc.
2727 The funny mixture of D and T modes is because integer operations
2728 do not specially operate on tetra quantities, so non-quad-aligned
2729 registers can hold quadword quantities (except %o4 and %i4 because
c4ce6853 2730 they cross fixed registers). */
ab835497 2731
61a55e8b
DE		 2732/* This points to either the 32 bit or the 64 bit version. */
2733int *hard_regno_mode_classes;
2734
2735static int hard_32bit_mode_classes[] = {
c4ce6853 2736 S_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
ab835497
RK		 2737 T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES,
2738 T_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
2739 T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES,
2740
2741 TF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES,
2742 TF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES,
2743 TF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES,
61a55e8b 2744 TF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES,
a9e27770
DE		 2745
2746 /* FP regs f32 to f63. Only the even numbered registers actually exist,
2747 and none can hold SFmode/SImode values. */
2748 DF_UP_MODES, 0, DF_ONLY_MODES, 0, DF_UP_MODES, 0, DF_ONLY_MODES, 0,
2749 DF_UP_MODES, 0, DF_ONLY_MODES, 0, DF_UP_MODES, 0, DF_ONLY_MODES, 0,
2750 DF_UP_MODES, 0, DF_ONLY_MODES, 0, DF_UP_MODES, 0, DF_ONLY_MODES, 0,
2751 DF_UP_MODES, 0, DF_ONLY_MODES, 0, DF_UP_MODES, 0, DF_ONLY_MODES, 0,
2752
2753 /* %fcc[0123] */
c4ce6853
DE		 2754 CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES,
2755
2756 /* %icc */
2757 CC_MODES
61a55e8b
DE		 2758};
2759
2760static int hard_64bit_mode_classes[] = {
c4ce6853 2761 D_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
61a55e8b
DE		 2762 T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
2763 T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
2764 T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
2765
2766 TF_MODES64, SF_MODES, DF_MODES64, SF_MODES, TF_MODES64, SF_MODES, DF_MODES64, SF_MODES,
2767 TF_MODES64, SF_MODES, DF_MODES64, SF_MODES, TF_MODES64, SF_MODES, DF_MODES64, SF_MODES,
2768 TF_MODES64, SF_MODES, DF_MODES64, SF_MODES, TF_MODES64, SF_MODES, DF_MODES64, SF_MODES,
2769 TF_MODES64, SF_MODES, DF_MODES64, SF_MODES, TF_MODES64, SF_MODES, DF_MODES64, SF_MODES,
2770
a9e27770 2771 /* FP regs f32 to f63. Only the even numbered registers actually exist,
61a55e8b
DE		 2772 and none can hold SFmode/SImode values. */
2773 DF_UP_MODES, 0, DF_ONLY_MODES, 0, DF_UP_MODES, 0, DF_ONLY_MODES, 0,
2774 DF_UP_MODES, 0, DF_ONLY_MODES, 0, DF_UP_MODES, 0, DF_ONLY_MODES, 0,
2775 DF_UP_MODES, 0, DF_ONLY_MODES, 0, DF_UP_MODES, 0, DF_ONLY_MODES, 0,
2776 DF_UP_MODES, 0, DF_ONLY_MODES, 0, DF_UP_MODES, 0, DF_ONLY_MODES, 0,
2777
2778 /* %fcc[0123] */
c4ce6853
DE		 2779 CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES,
2780
2781 /* %icc */
2782 CC_MODES
61a55e8b
DE		 2783};
2784
2785int sparc_mode_class [NUM_MACHINE_MODES];
2786
c4ce6853
DE		 2787enum reg_class sparc_regno_reg_class[FIRST_PSEUDO_REGISTER];
2788
61a55e8b
DE		 2789static void
2790sparc_init_modes ()
2791{
2792 int i;
2793
61a55e8b
DE		 2794 for (i = 0; i < NUM_MACHINE_MODES; i++)
2795 {
2796 switch (GET_MODE_CLASS (i))
2797 {
2798 case MODE_INT:
2799 case MODE_PARTIAL_INT:
2800 case MODE_COMPLEX_INT:
2801 if (GET_MODE_SIZE (i) <= 4)
2802 sparc_mode_class[i] = 1 << (int) S_MODE;
2803 else if (GET_MODE_SIZE (i) == 8)
2804 sparc_mode_class[i] = 1 << (int) D_MODE;
2805 else if (GET_MODE_SIZE (i) == 16)
2806 sparc_mode_class[i] = 1 << (int) T_MODE;
2807 else if (GET_MODE_SIZE (i) == 32)
2808 sparc_mode_class[i] = 1 << (int) O_MODE;
2809 else
2810 sparc_mode_class[i] = 0;
2811 break;
2812 case MODE_FLOAT:
2813 case MODE_COMPLEX_FLOAT:
2814 if (GET_MODE_SIZE (i) <= 4)
2815 sparc_mode_class[i] = 1 << (int) SF_MODE;
2816 else if (GET_MODE_SIZE (i) == 8)
2817 sparc_mode_class[i] = 1 << (int) DF_MODE;
2818 else if (GET_MODE_SIZE (i) == 16)
2819 sparc_mode_class[i] = 1 << (int) TF_MODE;
2820 else if (GET_MODE_SIZE (i) == 32)
2821 sparc_mode_class[i] = 1 << (int) OF_MODE;
2822 else
2823 sparc_mode_class[i] = 0;
2824 break;
2825 case MODE_CC:
2826 default:
2827 /* mode_class hasn't been initialized yet for EXTRA_CC_MODES, so
2828 we must explicitly check for them here. */
2829 if (i == (int) CCFPmode || i == (int) CCFPEmode)
2830 sparc_mode_class[i] = 1 << (int) CCFP_MODE;
2831 else if (i == (int) CCmode || i == (int) CC_NOOVmode
a9e27770 2832 || i == (int) CCXmode || i == (int) CCX_NOOVmode)
c4ce6853 2833 sparc_mode_class[i] = 1 << (int) CC_MODE;
61a55e8b
DE		 2834 else
2835 sparc_mode_class[i] = 0;
2836 break;
2837 }
2838 }
2839
a9e27770 2840 if (TARGET_ARCH64)
61a55e8b
DE		 2841 hard_regno_mode_classes = hard_64bit_mode_classes;
2842 else
2843 hard_regno_mode_classes = hard_32bit_mode_classes;
c4ce6853
DE		 2844
2845 /* Initialize the array used by REGNO_REG_CLASS. */
2846 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
2847 {
284d86e9
JC		 2848 if (i < 16 && TARGET_V8PLUS)
2849 sparc_regno_reg_class[i] = I64_REGS;
2850 else if (i < 32)
c4ce6853
DE		 2851 sparc_regno_reg_class[i] = GENERAL_REGS;
2852 else if (i < 64)
2853 sparc_regno_reg_class[i] = FP_REGS;
2854 else if (i < 96)
2855 sparc_regno_reg_class[i] = EXTRA_FP_REGS;
2856 else if (i < 100)
2857 sparc_regno_reg_class[i] = FPCC_REGS;
2858 else
2859 sparc_regno_reg_class[i] = NO_REGS;
2860 }
61a55e8b 2861}
ab835497 2862\f
61a55e8b
DE		 2863/* Save non call used registers from LOW to HIGH at BASE+OFFSET.
2864 N_REGS is the number of 4-byte regs saved thus far. This applies even to
2865 v9 int regs as it simplifies the code. */
2866
ab835497 2867static int
c53aa195 2868save_regs (file, low, high, base, offset, n_regs, real_offset)
ab835497
RK		 2869 FILE *file;
2870 int low, high;
3bb5de61 2871 const char *base;
ab835497 2872 int offset;
61a55e8b 2873 int n_regs;
c53aa195 2874 int real_offset;
ab835497
RK		 2875{
2876 int i;
2877
a9e27770 2878 if (TARGET_ARCH64 && high <= 32)
ab835497 2879 {
61a55e8b
DE		 2880 for (i = low; i < high; i++)
2881 {
2882 if (regs_ever_live[i] && ! call_used_regs[i])
c53aa195 2883 {
e0d80184 2884 fprintf (file, "\tstx\t%s, [%s+%d]\n",
c53aa195 2885 reg_names[i], base, offset + 4 * n_regs);
0021b564 2886 if (dwarf2out_do_frame ())
c53aa195 2887 dwarf2out_reg_save ("", i, real_offset + 4 * n_regs);
c53aa195
JM		 2888 n_regs += 2;
2889 }
61a55e8b 2890 }
ab835497 2891 }
61a55e8b
DE		 2892 else
2893 {
2894 for (i = low; i < high; i += 2)
2895 {
2896 if (regs_ever_live[i] && ! call_used_regs[i])
c53aa195 2897 {
5e9defae
KG		 2898 if (regs_ever_live[i+1] && ! call_used_regs[i+1])
2899 {
e0d80184 2900 fprintf (file, "\tstd\t%s, [%s+%d]\n",
5e9defae
KG		 2901 reg_names[i], base, offset + 4 * n_regs);
2902 if (dwarf2out_do_frame ())
2903 {
2904 char *l = dwarf2out_cfi_label ();
2905 dwarf2out_reg_save (l, i, real_offset + 4 * n_regs);
2906 dwarf2out_reg_save (l, i+1, real_offset + 4 * n_regs + 4);
2907 }
2908 n_regs += 2;
2909 }
2910 else
2911 {
e0d80184 2912 fprintf (file, "\tst\t%s, [%s+%d]\n",
5e9defae
KG		 2913 reg_names[i], base, offset + 4 * n_regs);
2914 if (dwarf2out_do_frame ())
2915 dwarf2out_reg_save ("", i, real_offset + 4 * n_regs);
2916 n_regs += 2;
2917 }
2918 }
2919 else
2920 {
2921 if (regs_ever_live[i+1] && ! call_used_regs[i+1])
2922 {
e0d80184 2923 fprintf (file, "\tst\t%s, [%s+%d]\n",
5e9defae
KG		 2924 reg_names[i+1], base, offset + 4 * n_regs + 4);
2925 if (dwarf2out_do_frame ())
2926 dwarf2out_reg_save ("", i + 1, real_offset + 4 * n_regs + 4);
2927 n_regs += 2;
2928 }
c53aa195 2929 }
61a55e8b
DE		 2930 }
2931 }
2932 return n_regs;
ab835497
RK		 2933}
2934
61a55e8b
DE		 2935/* Restore non call used registers from LOW to HIGH at BASE+OFFSET.
2936
2937 N_REGS is the number of 4-byte regs saved thus far. This applies even to
2938 v9 int regs as it simplifies the code. */
2939
ab835497 2940static int
61a55e8b 2941restore_regs (file, low, high, base, offset, n_regs)
ab835497
RK		 2942 FILE *file;
2943 int low, high;
3bb5de61 2944 const char *base;
ab835497 2945 int offset;
61a55e8b 2946 int n_regs;
ab835497
RK		 2947{
2948 int i;
2949
a9e27770 2950 if (TARGET_ARCH64 && high <= 32)
61a55e8b
DE		 2951 {
2952 for (i = low; i < high; i++)
2953 {
2954 if (regs_ever_live[i] && ! call_used_regs[i])
e0d80184 2955 fprintf (file, "\tldx\t[%s+%d], %s\n",
61a55e8b
DE		 2956 base, offset + 4 * n_regs, reg_names[i]),
2957 n_regs += 2;
2958 }
2959 }
2960 else
ab835497 2961 {
61a55e8b
DE		 2962 for (i = low; i < high; i += 2)
2963 {
2964 if (regs_ever_live[i] && ! call_used_regs[i])
2965 if (regs_ever_live[i+1] && ! call_used_regs[i+1])
e0d80184 2966 fprintf (file, "\tldd\t[%s+%d], %s\n",
61a55e8b
DE		 2967 base, offset + 4 * n_regs, reg_names[i]),
2968 n_regs += 2;
2969 else
e0d80184 2970 fprintf (file, "\tld\t[%s+%d],%s\n",
61a55e8b
DE		 2971 base, offset + 4 * n_regs, reg_names[i]),
2972 n_regs += 2;
2973 else if (regs_ever_live[i+1] && ! call_used_regs[i+1])
e0d80184 2974 fprintf (file, "\tld\t[%s+%d],%s\n",
61a55e8b
DE		 2975 base, offset + 4 * n_regs + 4, reg_names[i+1]),
2976 n_regs += 2;
2977 }
ab835497 2978 }
61a55e8b 2979 return n_regs;
ab835497
RK		 2980}
2981
2982/* Static variables we want to share between prologue and epilogue. */
2983
61a55e8b
DE		 2984/* Number of live general or floating point registers needed to be saved
2985 (as 4-byte quantities). This is only done if TARGET_EPILOGUE. */
2986static int num_gfregs;
2987
2988/* Compute the frame size required by the function. This function is called
2989 during the reload pass and also by output_function_prologue(). */
ab835497 2990
ab835497
RK		 2991int
2992compute_frame_size (size, leaf_function)
2993 int size;
2994 int leaf_function;
2995{
61a55e8b 2996 int n_regs = 0, i;
ab835497 2997 int outgoing_args_size = (current_function_outgoing_args_size
4fb4e4b8 2998 + REG_PARM_STACK_SPACE (current_function_decl));
ab835497 2999
61a55e8b 3000 if (TARGET_EPILOGUE)
ab835497 3001 {
61a55e8b
DE		 3002 /* N_REGS is the number of 4-byte regs saved thus far. This applies
3003 even to v9 int regs to be consistent with save_regs/restore_regs. */
3004
a9e27770 3005 if (TARGET_ARCH64)
61a55e8b
DE		 3006 {
3007 for (i = 0; i < 8; i++)
3008 if (regs_ever_live[i] && ! call_used_regs[i])
3009 n_regs += 2;
3010 }
3011 else
3012 {
3013 for (i = 0; i < 8; i += 2)
3014 if ((regs_ever_live[i] && ! call_used_regs[i])
3015 || (regs_ever_live[i+1] && ! call_used_regs[i+1]))
3016 n_regs += 2;
3017 }
3018
3019 for (i = 32; i < (TARGET_V9 ? 96 : 64); i += 2)
ab835497
RK		 3020 if ((regs_ever_live[i] && ! call_used_regs[i])
3021 || (regs_ever_live[i+1] && ! call_used_regs[i+1]))
61a55e8b 3022 n_regs += 2;
ab835497
RK		 3023 }
3024
3025 /* Set up values for use in `function_epilogue'. */
61a55e8b 3026 num_gfregs = n_regs;
ab835497 3027
61a55e8b
DE		 3028 if (leaf_function && n_regs == 0
3029 && size == 0 && current_function_outgoing_args_size == 0)
3030 {
3031 actual_fsize = apparent_fsize = 0;
3032 }
3033 else
3034 {
3035 /* We subtract STARTING_FRAME_OFFSET, remember it's negative.
3036 The stack bias (if any) is taken out to undo its effects. */
3037 apparent_fsize = (size - STARTING_FRAME_OFFSET + SPARC_STACK_BIAS + 7) & -8;
3038 apparent_fsize += n_regs * 4;
3039 actual_fsize = apparent_fsize + ((outgoing_args_size + 7) & -8);
3040 }
ab835497
RK		 3041
3042 /* Make sure nothing can clobber our register windows.
3043 If a SAVE must be done, or there is a stack-local variable,
61a55e8b 3044 the register window area must be allocated.
4fb4e4b8 3045 ??? For v8 we apparently need an additional 8 bytes of reserved space. */
ab835497 3046 if (leaf_function == 0 || size > 0)
4fb4e4b8 3047 actual_fsize += (16 * UNITS_PER_WORD) + (TARGET_ARCH64 ? 0 : 8);
ab835497 3048
61a55e8b
DE		 3049 return SPARC_STACK_ALIGN (actual_fsize);
3050}
3051
3052/* Build a (32 bit) big number in a register. */
86735b02 3053/* ??? We may be able to use the set macro here too. */
61a55e8b
DE		 3054
3055static void
3056build_big_number (file, num, reg)
3057 FILE *file;
3058 int num;
3bb5de61 3059 const char *reg;
61a55e8b 3060{
a9e27770 3061 if (num >= 0 || ! TARGET_ARCH64)
61a55e8b 3062 {
e0d80184 3063 fprintf (file, "\tsethi\t%%hi(%d), %s\n", num, reg);
61a55e8b 3064 if ((num & 0x3ff) != 0)
e0d80184 3065 fprintf (file, "\tor\t%s, %%lo(%d), %s\n", reg, num, reg);
61a55e8b 3066 }
a9e27770 3067 else /* num < 0 && TARGET_ARCH64 */
61a55e8b
DE		 3068 {
3069 /* Sethi does not sign extend, so we must use a little trickery
3070 to use it for negative numbers. Invert the constant before
3071 loading it in, then use xor immediate to invert the loaded bits
3072 (along with the upper 32 bits) to the desired constant. This
3073 works because the sethi and immediate fields overlap. */
3074 int asize = num;
3075 int inv = ~asize;
3076 int low = -0x400 + (asize & 0x3FF);
3077
e0d80184 3078 fprintf (file, "\tsethi\t%%hi(%d), %s\n\txor\t%s, %d, %s\n",
61a55e8b
DE		 3079 inv, reg, reg, low, reg);
3080 }
ab835497
RK		 3081}
3082
1cb36a98
RH		 3083/* Output any necessary .register pseudo-ops. */
3084void
3085sparc_output_scratch_registers (file)
3086 FILE *file;
3087{
3088#ifdef HAVE_AS_REGISTER_PSEUDO_OP
3089 int i;
3090
3091 if (TARGET_ARCH32)
3092 return;
3093
3094 /* Check if %g[2367] were used without
3095 .register being printed for them already. */
3096 for (i = 2; i < 8; i++)
3097 {
3098 if (regs_ever_live [i]
3099 && ! sparc_hard_reg_printed [i])
3100 {
3101 sparc_hard_reg_printed [i] = 1;
3102 fprintf (file, "\t.register\t%%g%d, #scratch\n", i);
3103 }
3104 if (i == 3) i = 5;
3105 }
3106#endif
3107}
3108
915f619f
JW		 3109/* Output code for the function prologue. */
3110
ab835497
RK		 3111void
3112output_function_prologue (file, size, leaf_function)
3113 FILE *file;
3114 int size;
915f619f 3115 int leaf_function;
ab835497 3116{
1cb36a98
RH		 3117 sparc_output_scratch_registers (file);
3118
915f619f
JW		 3119 /* Need to use actual_fsize, since we are also allocating
3120 space for our callee (and our own register save area). */
ab835497
RK		 3121 actual_fsize = compute_frame_size (size, leaf_function);
3122
61a55e8b
DE		 3123 if (leaf_function)
3124 {
3125 frame_base_name = "%sp";
3126 frame_base_offset = actual_fsize + SPARC_STACK_BIAS;
3127 }
3128 else
3129 {
3130 frame_base_name = "%fp";
3131 frame_base_offset = SPARC_STACK_BIAS;
3132 }
3133
c6aa9ce1 3134 /* This is only for the human reader. */
bf62bbf1 3135 fprintf (file, "\t%s#PROLOGUE# 0\n", ASM_COMMENT_START);
c6aa9ce1 3136
915f619f
JW		 3137 if (actual_fsize == 0)
3138 /* do nothing. */ ;
3592ea0d 3139 else if (! leaf_function && ! TARGET_BROKEN_SAVERESTORE)
ab835497 3140 {
3592ea0d 3141 if (actual_fsize <= 4096)
e0d80184 3142 fprintf (file, "\tsave\t%%sp, -%d, %%sp\n", actual_fsize);
3592ea0d 3143 else if (actual_fsize <= 8192)
915f619f 3144 {
e0d80184
DM		 3145 fprintf (file, "\tsave\t%%sp, -4096, %%sp\n");
3146 fprintf (file, "\tadd\t%%sp, -%d, %%sp\n", actual_fsize - 4096);
915f619f
JW		 3147 }
3148 else
3149 {
3592ea0d 3150 build_big_number (file, -actual_fsize, "%g1");
e0d80184 3151 fprintf (file, "\tsave\t%%sp, %%g1, %%sp\n");
915f619f 3152 }
ab835497 3153 }
5f4241d5 3154 else if (! leaf_function && TARGET_BROKEN_SAVERESTORE)
ab835497 3155 {
5f4241d5 3156 /* We assume the environment will properly handle or otherwise avoid
956d6950
JL		 3157 trouble associated with an interrupt occurring after the `save' or
3158 trap occurring during it. */
5f4241d5 3159 fprintf (file, "\tsave\n");
3592ea0d 3160
5f4241d5 3161 if (actual_fsize <= 4096)
e0d80184 3162 fprintf (file, "\tadd\t%%fp, -%d, %%sp\n", actual_fsize);
5f4241d5
DE		 3163 else if (actual_fsize <= 8192)
3164 {
e0d80184
DM		 3165 fprintf (file, "\tadd\t%%fp, -4096, %%sp\n");
3166 fprintf (file, "\tadd\t%%fp, -%d, %%sp\n", actual_fsize - 4096);
5f4241d5
DE		 3167 }
3168 else
3169 {
3170 build_big_number (file, -actual_fsize, "%g1");
e0d80184 3171 fprintf (file, "\tadd\t%%fp, %%g1, %%sp\n");
5f4241d5
DE		 3172 }
3173 }
3174 else /* leaf function */
3175 {
3592ea0d 3176 if (actual_fsize <= 4096)
e0d80184 3177 fprintf (file, "\tadd\t%%sp, -%d, %%sp\n", actual_fsize);
3592ea0d
DE		 3178 else if (actual_fsize <= 8192)
3179 {
e0d80184
DM		 3180 fprintf (file, "\tadd\t%%sp, -4096, %%sp\n");
3181 fprintf (file, "\tadd\t%%sp, -%d, %%sp\n", actual_fsize - 4096);
3592ea0d 3182 }
915f619f 3183 else
3592ea0d
DE		 3184 {
3185 build_big_number (file, -actual_fsize, "%g1");
e0d80184 3186 fprintf (file, "\tadd\t%%sp, %%g1, %%sp\n");
3592ea0d 3187 }
ab835497
RK		 3188 }
3189
0021b564 3190 if (dwarf2out_do_frame () && actual_fsize)
c53aa195 3191 {
96987e96 3192 char *label = dwarf2out_cfi_label ();
c53aa195
JM		 3193
3194 /* The canonical frame address refers to the top of the frame. */
3195 dwarf2out_def_cfa (label, (leaf_function ? STACK_POINTER_REGNUM
3196 : FRAME_POINTER_REGNUM),
3197 frame_base_offset);
3198
3199 if (! leaf_function)
3200 {
3201 /* Note the register window save. This tells the unwinder that
3202 it needs to restore the window registers from the previous
3203 frame's window save area at 0(cfa). */
3204 dwarf2out_window_save (label);
3205
3206 /* The return address (-8) is now in %i7. */
3207 dwarf2out_return_reg (label, 31);
3208 }
3209 }
c53aa195 3210
ab835497
RK		 3211 /* If doing anything with PIC, do it now. */
3212 if (! flag_pic)
bf62bbf1 3213 fprintf (file, "\t%s#PROLOGUE# 1\n", ASM_COMMENT_START);
ab835497 3214
61a55e8b
DE		 3215 /* Call saved registers are saved just above the outgoing argument area. */
3216 if (num_gfregs)
ab835497 3217 {
c53aa195 3218 int offset, real_offset, n_regs;
3bb5de61 3219 const char *base;
ab835497 3220
84e884e9
JM		 3221 real_offset = -apparent_fsize;
3222 offset = -apparent_fsize + frame_base_offset;
61a55e8b
DE		 3223 if (offset < -4096 || offset + num_gfregs * 4 > 4096)
3224 {
3225 /* ??? This might be optimized a little as %g1 might already have a
3226 value close enough that a single add insn will do. */
3227 /* ??? Although, all of this is probably only a temporary fix
3228 because if %g1 can hold a function result, then
3229 output_function_epilogue will lose (the result will get
3230 clobbered). */
3231 build_big_number (file, offset, "%g1");
e0d80184 3232 fprintf (file, "\tadd\t%s, %%g1, %%g1\n", frame_base_name);
61a55e8b
DE		 3233 base = "%g1";
3234 offset = 0;
3235 }
ab835497 3236 else
61a55e8b
DE		 3237 {
3238 base = frame_base_name;
3239 }
ab835497 3240
db3d4438 3241 n_regs = 0;
ab835497 3242 if (TARGET_EPILOGUE && ! leaf_function)
61a55e8b 3243 /* ??? Originally saved regs 0-15 here. */
c53aa195 3244 n_regs = save_regs (file, 0, 8, base, offset, 0, real_offset);
ab835497 3245 else if (leaf_function)
61a55e8b 3246 /* ??? Originally saved regs 0-31 here. */
c53aa195 3247 n_regs = save_regs (file, 0, 8, base, offset, 0, real_offset);
ab835497 3248 if (TARGET_EPILOGUE)
c53aa195
JM		 3249 save_regs (file, 32, TARGET_V9 ? 96 : 64, base, offset, n_regs,
3250 real_offset);
ab835497
RK		 3251 }
3252
ab835497
RK		 3253 leaf_label = 0;
3254 if (leaf_function && actual_fsize != 0)
3255 {
3256 /* warning ("leaf procedure with frame size %d", actual_fsize); */
3257 if (! TARGET_EPILOGUE)
3258 leaf_label = gen_label_rtx ();
3259 }
3260}
3261
915f619f
JW		 3262/* Output code for the function epilogue. */
3263
ab835497 3264void
ef8200df 3265output_function_epilogue (file, size, leaf_function)
ab835497 3266 FILE *file;
db3d4438 3267 int size ATTRIBUTE_UNUSED;
ef8200df 3268 int leaf_function;
ab835497 3269{
3bb5de61 3270 const char *ret;
ab835497
RK		 3271
3272 if (leaf_label)
3273 {
ab835497
RK		 3274 emit_label_after (leaf_label, get_last_insn ());
3275 final_scan_insn (get_last_insn (), file, 0, 0, 1);
3276 }
3277
b69649e4
RK		 3278#ifdef FUNCTION_BLOCK_PROFILER_EXIT
3279 else if (profile_block_flag == 2)
3280 {
3281 FUNCTION_BLOCK_PROFILER_EXIT(file);
3282 }
3283#endif
3284
bfd6bc60
JC		 3285 else if (current_function_epilogue_delay_list == 0)
3286 {
e0d80184
DM		 3287 /* If code does not drop into the epilogue, we need
3288 do nothing except output pending case vectors. */
bfd6bc60
JC		 3289 rtx insn = get_last_insn ();
3290 if (GET_CODE (insn) == NOTE)
3291 insn = prev_nonnote_insn (insn);
3292 if (insn && GET_CODE (insn) == BARRIER)
e0d80184 3293 goto output_vectors;
bfd6bc60
JC		 3294 }
3295
61a55e8b
DE		 3296 /* Restore any call saved registers. */
3297 if (num_gfregs)
ab835497 3298 {
61a55e8b 3299 int offset, n_regs;
3bb5de61 3300 const char *base;
ab835497 3301
61a55e8b
DE		 3302 offset = -apparent_fsize + frame_base_offset;
3303 if (offset < -4096 || offset + num_gfregs * 4 > 4096 - 8 /*double*/)
3304 {
3305 build_big_number (file, offset, "%g1");
e0d80184 3306 fprintf (file, "\tadd\t%s, %%g1, %%g1\n", frame_base_name);
61a55e8b
DE		 3307 base = "%g1";
3308 offset = 0;
3309 }
ab835497 3310 else
61a55e8b
DE		 3311 {
3312 base = frame_base_name;
3313 }
ab835497 3314
db3d4438 3315 n_regs = 0;
ab835497 3316 if (TARGET_EPILOGUE && ! leaf_function)
61a55e8b
DE		 3317 /* ??? Originally saved regs 0-15 here. */
3318 n_regs = restore_regs (file, 0, 8, base, offset, 0);
ab835497 3319 else if (leaf_function)
61a55e8b
DE		 3320 /* ??? Originally saved regs 0-31 here. */
3321 n_regs = restore_regs (file, 0, 8, base, offset, 0);
ab835497 3322 if (TARGET_EPILOGUE)
61a55e8b 3323 restore_regs (file, 32, TARGET_V9 ? 96 : 64, base, offset, n_regs);
ab835497
RK		 3324 }
3325
3326 /* Work out how to skip the caller's unimp instruction if required. */
3327 if (leaf_function)
e0d80184 3328 ret = (SKIP_CALLERS_UNIMP_P ? "jmp\t%o7+12" : "retl");
ab835497 3329 else
e0d80184 3330 ret = (SKIP_CALLERS_UNIMP_P ? "jmp\t%i7+12" : "ret");
ab835497 3331
ef8200df 3332 if (TARGET_EPILOGUE || leaf_label)
ab835497 3333 {
ef8200df
JW		 3334 int old_target_epilogue = TARGET_EPILOGUE;
3335 target_flags &= ~old_target_epilogue;
ab835497 3336
ef8200df
JW		 3337 if (! leaf_function)
3338 {
3339 /* If we wound up with things in our delay slot, flush them here. */
3340 if (current_function_epilogue_delay_list)
ab835497 3341 {
254110c2 3342 rtx insn = emit_jump_insn_after (gen_rtx_RETURN (VOIDmode),
ef8200df 3343 get_last_insn ());
254110c2 3344 PATTERN (insn) = gen_rtx_PARALLEL (VOIDmode,
ef8200df
JW		 3345 gen_rtvec (2,
3346 PATTERN (XEXP (current_function_epilogue_delay_list, 0)),
3347 PATTERN (insn)));
3348 final_scan_insn (insn, file, 1, 0, 1);
ab835497 3349 }
284d86e9 3350 else if (TARGET_V9 && ! SKIP_CALLERS_UNIMP_P)
e0d80184 3351 fputs ("\treturn\t%i7+8\n\tnop\n", file);
ab835497 3352 else
ef8200df
JW		 3353 fprintf (file, "\t%s\n\trestore\n", ret);
3354 }
915f619f
JW		 3355 /* All of the following cases are for leaf functions. */
3356 else if (current_function_epilogue_delay_list)
ef8200df 3357 {
915f619f
JW		 3358 /* eligible_for_epilogue_delay_slot ensures that if this is a
3359 leaf function, then we will only have insn in the delay slot
3360 if the frame size is zero, thus no adjust for the stack is
3361 needed here. */
3362 if (actual_fsize != 0)
ef8200df 3363 abort ();
915f619f
JW		 3364 fprintf (file, "\t%s\n", ret);
3365 final_scan_insn (XEXP (current_function_epilogue_delay_list, 0),
3366 file, 1, 0, 1);
ab835497 3367 }
9bb7ffda
JW		 3368 /* Output 'nop' instead of 'sub %sp,-0,%sp' when no frame, so as to
3369 avoid generating confusing assembly language output. */
3370 else if (actual_fsize == 0)
3371 fprintf (file, "\t%s\n\tnop\n", ret);
915f619f 3372 else if (actual_fsize <= 4096)
e0d80184 3373 fprintf (file, "\t%s\n\tsub\t%%sp, -%d, %%sp\n", ret, actual_fsize);
915f619f 3374 else if (actual_fsize <= 8192)
e0d80184 3375 fprintf (file, "\tsub\t%%sp, -4096, %%sp\n\t%s\n\tsub\t%%sp, -%d, %%sp\n",
915f619f
JW		 3376 ret, actual_fsize - 4096);
3377 else if ((actual_fsize & 0x3ff) == 0)
e0d80184 3378 fprintf (file, "\tsethi\t%%hi(%d), %%g1\n\t%s\n\tadd\t%%sp, %%g1, %%sp\n",
915f619f
JW		 3379 actual_fsize, ret);
3380 else
e0d80184 3381 fprintf (file, "\tsethi\t%%hi(%d), %%g1\n\tor\t%%g1, %%lo(%d), %%g1\n\t%s\n\tadd\t%%sp, %%g1, %%sp\n",
915f619f 3382 actual_fsize, actual_fsize, ret);
ef8200df 3383 target_flags |= old_target_epilogue;
ab835497 3384 }
e0d80184
DM		 3385
3386 output_vectors:
3387 sparc_output_deferred_case_vectors ();
ab835497 3388}
4fb4e4b8
DE		 3389\f
3390/* Functions for handling argument passing.
3391
3392 For v8 the first six args are normally in registers and the rest are
3393 pushed. Any arg that starts within the first 6 words is at least
3394 partially passed in a register unless its data type forbids.
3395
3396 For v9, the argument registers are laid out as an array of 16 elements
3397 and arguments are added sequentially. The first 6 int args and up to the
3398 first 16 fp args (depending on size) are passed in regs.
3399
3400 Slot Stack Integral Float Float in structure Double Long Double
3401 ---- ----- -------- ----- ------------------ ------ -----------
3402 15 [SP+248] %f31 %f30,%f31 %d30
3403 14 [SP+240] %f29 %f28,%f29 %d28 %q28
3404 13 [SP+232] %f27 %f26,%f27 %d26
3405 12 [SP+224] %f25 %f24,%f25 %d24 %q24
3406 11 [SP+216] %f23 %f22,%f23 %d22
3407 10 [SP+208] %f21 %f20,%f21 %d20 %q20
3408 9 [SP+200] %f19 %f18,%f19 %d18
3409 8 [SP+192] %f17 %f16,%f17 %d16 %q16
3410 7 [SP+184] %f15 %f14,%f15 %d14
3411 6 [SP+176] %f13 %f12,%f13 %d12 %q12
3412 5 [SP+168] %o5 %f11 %f10,%f11 %d10
3413 4 [SP+160] %o4 %f9 %f8,%f9 %d8 %q8
3414 3 [SP+152] %o3 %f7 %f6,%f7 %d6
3415 2 [SP+144] %o2 %f5 %f4,%f5 %d4 %q4
3416 1 [SP+136] %o1 %f3 %f2,%f3 %d2
3417 0 [SP+128] %o0 %f1 %f0,%f1 %d0 %q0
3418
3419 Here SP = %sp if -mno-stack-bias or %sp+stack_bias otherwise.
3420
3421 Integral arguments are always passed as 64 bit quantities appropriately
3422 extended.
3423
3424 Passing of floating point values is handled as follows.
3425 If a prototype is in scope:
3426 If the value is in a named argument (i.e. not a stdarg function or a
3427 value not part of the `...') then the value is passed in the appropriate
3428 fp reg.
3429 If the value is part of the `...' and is passed in one of the first 6
3430 slots then the value is passed in the appropriate int reg.
3431 If the value is part of the `...' and is not passed in one of the first 6
3432 slots then the value is passed in memory.
3433 If a prototype is not in scope:
3434 If the value is one of the first 6 arguments the value is passed in the
3435 appropriate integer reg and the appropriate fp reg.
3436 If the value is not one of the first 6 arguments the value is passed in
3437 the appropriate fp reg and in memory.
3438 */
3439
3440/* Maximum number of int regs for args. */
3441#define SPARC_INT_ARG_MAX 6
3442/* Maximum number of fp regs for args. */
3443#define SPARC_FP_ARG_MAX 16
3444
3445#define ROUND_ADVANCE(SIZE) (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
3446
3447/* Handle the INIT_CUMULATIVE_ARGS macro.
3448 Initialize a variable CUM of type CUMULATIVE_ARGS
3449 for a call to a function whose data type is FNTYPE.
3450 For a library call, FNTYPE is 0. */
3ea1fdd3 3451
4fb4e4b8
DE		 3452void
3453init_cumulative_args (cum, fntype, libname, indirect)
3454 CUMULATIVE_ARGS *cum;
db3d4438
DM		 3455 tree fntype;
3456 tree libname ATTRIBUTE_UNUSED;
3457 int indirect ATTRIBUTE_UNUSED;
4fb4e4b8
DE		 3458{
3459 cum->words = 0;
3460 cum->prototype_p = fntype && TYPE_ARG_TYPES (fntype);
3461 cum->libcall_p = fntype == 0;
3462}
61a55e8b 3463
4fb4e4b8
DE		 3464/* Compute the slot number to pass an argument in.
3465 Returns the slot number or -1 if passing on the stack.
3466
3467 CUM is a variable of type CUMULATIVE_ARGS which gives info about
3468 the preceding args and about the function being called.
3469 MODE is the argument's machine mode.
3470 TYPE is the data type of the argument (as a tree).
3471 This is null for libcalls where that information may
3472 not be available.
3473 NAMED is nonzero if this argument is a named parameter
3474 (otherwise it is an extra parameter matching an ellipsis).
3475 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG.
3476 *PREGNO records the register number to use if scalar type.
3477 *PPADDING records the amount of padding needed in words. */
3478
3479static int
3480function_arg_slotno (cum, mode, type, named, incoming_p, pregno, ppadding)
3481 const CUMULATIVE_ARGS *cum;
3482 enum machine_mode mode;
3483 tree type;
3484 int named;
3485 int incoming_p;
3486 int *pregno;
3487 int *ppadding;
3488{
3489 int regbase = (incoming_p
3490 ? SPARC_INCOMING_INT_ARG_FIRST
3491 : SPARC_OUTGOING_INT_ARG_FIRST);
3492 int slotno = cum->words;
3493 int regno;
3494
3495 *ppadding = 0;
3496
3497 if (type != 0 && TREE_ADDRESSABLE (type))
3498 return -1;
3499 if (TARGET_ARCH32
3500 && type != 0 && mode == BLKmode
3501 && TYPE_ALIGN (type) % PARM_BOUNDARY != 0)
3502 return -1;
3503
3504 switch (mode)
3505 {
3506 case VOIDmode :
3507 /* MODE is VOIDmode when generating the actual call.
3508 See emit_call_1. */
3509 return -1;
3510
3511 case QImode : case CQImode :
3512 case HImode : case CHImode :
3513 case SImode : case CSImode :
3514 case DImode : case CDImode :
3515 if (slotno >= SPARC_INT_ARG_MAX)
3516 return -1;
3517 regno = regbase + slotno;
3518 break;
3519
3520 case SFmode : case SCmode :
3521 case DFmode : case DCmode :
3522 case TFmode : case TCmode :
3523 if (TARGET_ARCH32)
3524 {
3525 if (slotno >= SPARC_INT_ARG_MAX)
3526 return -1;
3527 regno = regbase + slotno;
3528 }
3529 else
3530 {
3531 if ((mode == TFmode || mode == TCmode)
3532 && (slotno & 1) != 0)
3533 slotno++, *ppadding = 1;
3534 if (TARGET_FPU && named)
3535 {
3536 if (slotno >= SPARC_FP_ARG_MAX)
82d6b402 3537 return -1;
4fb4e4b8
DE		 3538 regno = SPARC_FP_ARG_FIRST + slotno * 2;
3539 if (mode == SFmode)
3540 regno++;
3541 }
3542 else
3543 {
3544 if (slotno >= SPARC_INT_ARG_MAX)
3545 return -1;
3546 regno = regbase + slotno;
3547 }
3548 }
3549 break;
3550
3551 case BLKmode :
3552 /* For sparc64, objects requiring 16 byte alignment get it. */
3553 if (TARGET_ARCH64)
3554 {
3555 if (type && TYPE_ALIGN (type) == 128 && (slotno & 1) != 0)
3556 slotno++, *ppadding = 1;
3557 }
3558
3559 if (TARGET_ARCH32
5e9defae 3560 || (type && TREE_CODE (type) == UNION_TYPE))
4fb4e4b8
DE		 3561 {
3562 if (slotno >= SPARC_INT_ARG_MAX)
3563 return -1;
3564 regno = regbase + slotno;
3565 }
3566 else
3567 {
3568 tree field;
3569 int intregs_p = 0, fpregs_p = 0;
3570 /* The ABI obviously doesn't specify how packed
3571 structures are passed. These are defined to be passed
3572 in int regs if possible, otherwise memory. */
3573 int packed_p = 0;
3574
3575 /* First see what kinds of registers we need. */
3576 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
3577 {
3578 if (TREE_CODE (field) == FIELD_DECL)
3579 {
3580 if (TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
3581 && TARGET_FPU)
3582 fpregs_p = 1;
3583 else
3584 intregs_p = 1;
3585 if (DECL_PACKED (field))
3586 packed_p = 1;
3587 }
3588 }
3589 if (packed_p || !named)
3590 fpregs_p = 0, intregs_p = 1;
3591
3592 /* If all arg slots are filled, then must pass on stack. */
3593 if (fpregs_p && slotno >= SPARC_FP_ARG_MAX)
3594 return -1;
3595 /* If there are only int args and all int arg slots are filled,
3596 then must pass on stack. */
3597 if (!fpregs_p && intregs_p && slotno >= SPARC_INT_ARG_MAX)
3598 return -1;
3599 /* Note that even if all int arg slots are filled, fp members may
3600 still be passed in regs if such regs are available.
3601 *PREGNO isn't set because there may be more than one, it's up
3602 to the caller to compute them. */
3603 return slotno;
3604 }
3605 break;
3606
3607 default :
3608 abort ();
3609 }
3610
3611 *pregno = regno;
3612 return slotno;
3613}
3614
82d6b402
RH		 3615/* Handle recursive register counting for structure field layout. */
3616
3617struct function_arg_record_value_parms
3618{
3619 rtx ret;
3620 int slotno, named, regbase;
3621 int nregs, intoffset;
3622};
3623
2a01c939
DM		 3624static void function_arg_record_value_3
3625 PROTO((int, struct function_arg_record_value_parms *));
3626static void function_arg_record_value_2
3627 PROTO((tree, int, struct function_arg_record_value_parms *));
b1474bb7
KG		 3628static void function_arg_record_value_1
3629 PROTO((tree, int, struct function_arg_record_value_parms *));
2a01c939
DM		 3630static rtx function_arg_record_value
3631 PROTO((tree, enum machine_mode, int, int, int));
3632
82d6b402
RH		 3633static void
3634function_arg_record_value_1 (type, startbitpos, parms)
3635 tree type;
3636 int startbitpos;
3637 struct function_arg_record_value_parms *parms;
3638{
3639 tree field;
3640
3641 /* The ABI obviously doesn't specify how packed structures are
3642 passed. These are defined to be passed in int regs if possible,
3643 otherwise memory. */
3644 int packed_p = 0;
3645
3646 /* We need to compute how many registers are needed so we can
3647 allocate the PARALLEL but before we can do that we need to know
3648 whether there are any packed fields. If there are, int regs are
3649 used regardless of whether there are fp values present. */
3650 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
3651 {
3652 if (TREE_CODE (field) == FIELD_DECL && DECL_PACKED (field))
3653 {
3654 packed_p = 1;
3655 break;
3656 }
3657 }
3658
3659 /* Compute how many registers we need. */
3660 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
3661 {
3662 if (TREE_CODE (field) == FIELD_DECL)
3663 {
3664 int bitpos = startbitpos;
3665 if (DECL_FIELD_BITPOS (field))
3666 bitpos += TREE_INT_CST_LOW (DECL_FIELD_BITPOS (field));
3667 /* ??? FIXME: else assume zero offset. */
3668
3669 if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE)
3670 {
3671 function_arg_record_value_1 (TREE_TYPE (field), bitpos, parms);
3672 }
3673 else if (TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
3674 && TARGET_FPU
3675 && ! packed_p
3676 && parms->named)
3677 {
3678 if (parms->intoffset != -1)
3679 {
3680 int intslots, this_slotno;
3681
3682 intslots = (bitpos - parms->intoffset + BITS_PER_WORD - 1)
3683 / BITS_PER_WORD;
3684 this_slotno = parms->slotno + parms->intoffset
3685 / BITS_PER_WORD;
3686
3687 intslots = MIN (intslots, SPARC_INT_ARG_MAX - this_slotno);
3688 intslots = MAX (intslots, 0);
3689 parms->nregs += intslots;
3690 parms->intoffset = -1;
3691 }
3692
3693 /* There's no need to check this_slotno < SPARC_FP_ARG MAX.
3694 If it wasn't true we wouldn't be here. */
3695 parms->nregs += 1;
3696 }
3697 else
3698 {
3699 if (parms->intoffset == -1)
3700 parms->intoffset = bitpos;
3701 }
3702 }
3703 }
3704}
3705
3706/* Handle recursive structure field register assignment. */
3707
3708static void
3709function_arg_record_value_3 (bitpos, parms)
3710 int bitpos;
3711 struct function_arg_record_value_parms *parms;
3712{
3713 enum machine_mode mode;
3714 int regno, this_slotno, intslots, intoffset;
3715 rtx reg;
3716
3717 if (parms->intoffset == -1)
3718 return;
3719 intoffset = parms->intoffset;
3720 parms->intoffset = -1;
3721
3722 intslots = (bitpos - intoffset + BITS_PER_WORD - 1) / BITS_PER_WORD;
3723 this_slotno = parms->slotno + intoffset / BITS_PER_WORD;
3724
3725 intslots = MIN (intslots, SPARC_INT_ARG_MAX - this_slotno);
3726 if (intslots <= 0)
3727 return;
3728
3729 /* If this is the trailing part of a word, only load that much into
3730 the register. Otherwise load the whole register. Note that in
3731 the latter case we may pick up unwanted bits. It's not a problem
3732 at the moment but may wish to revisit. */
3733
3734 if (intoffset % BITS_PER_WORD != 0)
3735 {
3736 mode = mode_for_size (BITS_PER_WORD - intoffset%BITS_PER_WORD,
3737 MODE_INT, 0);
3738 }
3739 else
3740 mode = word_mode;
3741
3742 intoffset /= BITS_PER_UNIT;
3743 do
3744 {
3745 regno = parms->regbase + this_slotno;
254110c2 3746 reg = gen_rtx_REG (mode, regno);
82d6b402 3747 XVECEXP (parms->ret, 0, parms->nregs)
254110c2 3748 = gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset));
82d6b402
RH		 3749
3750 this_slotno += 1;
3751 intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1;
3752 parms->nregs += 1;
3753 intslots -= 1;
3754 }
3755 while (intslots > 0);
3756}
3757
3758static void
3759function_arg_record_value_2 (type, startbitpos, parms)
3760 tree type;
3761 int startbitpos;
3762 struct function_arg_record_value_parms *parms;
3763{
3764 tree field;
3765 int packed_p = 0;
3766
3767 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
3768 {
3769 if (TREE_CODE (field) == FIELD_DECL && DECL_PACKED (field))
3770 {
3771 packed_p = 1;
3772 break;
3773 }
3774 }
3775
3776 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
3777 {
3778 if (TREE_CODE (field) == FIELD_DECL)
3779 {
3780 int bitpos = startbitpos;
3781 if (DECL_FIELD_BITPOS (field))
3782 bitpos += TREE_INT_CST_LOW (DECL_FIELD_BITPOS (field));
3783 /* ??? FIXME: else assume zero offset. */
3784
3785 if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE)
3786 {
3787 function_arg_record_value_2 (TREE_TYPE (field), bitpos, parms);
3788 }
3789 else if (TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
3790 && TARGET_FPU
3791 && ! packed_p
3792 && parms->named)
3793 {
3794 int this_slotno = parms->slotno + bitpos / BITS_PER_WORD;
3795 rtx reg;
3796
3797 function_arg_record_value_3 (bitpos, parms);
3798
254110c2 3799 reg = gen_rtx_REG (DECL_MODE (field),
82d6b402
RH		 3800 (SPARC_FP_ARG_FIRST + this_slotno * 2
3801 + (DECL_MODE (field) == SFmode
3802 && (bitpos & 32) != 0)));
3803 XVECEXP (parms->ret, 0, parms->nregs)
254110c2 3804 = gen_rtx_EXPR_LIST (VOIDmode, reg,
82d6b402
RH		 3805 GEN_INT (bitpos / BITS_PER_UNIT));
3806 parms->nregs += 1;
3807 }
3808 else
3809 {
3810 if (parms->intoffset == -1)
3811 parms->intoffset = bitpos;
3812 }
3813 }
3814 }
3815}
3816
3817static rtx
1eac9f59 3818function_arg_record_value (type, mode, slotno, named, regbase)
82d6b402 3819 tree type;
1eac9f59 3820 enum machine_mode mode;
82d6b402
RH		 3821 int slotno, named, regbase;
3822{
3823 HOST_WIDE_INT typesize = int_size_in_bytes (type);
3824 struct function_arg_record_value_parms parms;
3825 int nregs;
3826
3827 parms.ret = NULL_RTX;
3828 parms.slotno = slotno;
3829 parms.named = named;
3830 parms.regbase = regbase;
3831
3832 /* Compute how many registers we need. */
3833 parms.nregs = 0;
3834 parms.intoffset = 0;
3835 function_arg_record_value_1 (type, 0, &parms);
3836
3837 if (parms.intoffset != -1)
3838 {
3839 int intslots, this_slotno;
3840
3841 intslots = (typesize*BITS_PER_UNIT - parms.intoffset + BITS_PER_WORD - 1)
3842 / BITS_PER_WORD;
3843 this_slotno = slotno + parms.intoffset / BITS_PER_WORD;
3844
3845 intslots = MIN (intslots, SPARC_INT_ARG_MAX - this_slotno);
3846 intslots = MAX (intslots, 0);
3847
3848 parms.nregs += intslots;
3849 }
3850 nregs = parms.nregs;
3851
3852 /* Allocate the vector and handle some annoying special cases. */
3853 if (nregs == 0)
3854 {
3855 /* ??? Empty structure has no value? Duh? */
3856 if (typesize <= 0)
3857 {
3858 /* Though there's nothing really to store, return a word register
3859 anyway so the rest of gcc doesn't go nuts. Returning a PARALLEL
3860 leads to breakage due to the fact that there are zero bytes to
3861 load. */
1eac9f59 3862 return gen_rtx_REG (mode, regbase);
82d6b402
RH		 3863 }
3864 else
3865 {
3866 /* ??? C++ has structures with no fields, and yet a size. Give up
3867 for now and pass everything back in integer registers. */
3868 nregs = (typesize + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3869 }
3870 if (nregs + slotno > SPARC_INT_ARG_MAX)
3871 nregs = SPARC_INT_ARG_MAX - slotno;
3872 }
3873 if (nregs == 0)
9208e4b2 3874 abort ();
82d6b402 3875
1eac9f59 3876 parms.ret = gen_rtx_PARALLEL (mode, rtvec_alloc (nregs));
82d6b402
RH		 3877
3878 /* Fill in the entries. */
3879 parms.nregs = 0;
3880 parms.intoffset = 0;
3881 function_arg_record_value_2 (type, 0, &parms);
3882 function_arg_record_value_3 (typesize * BITS_PER_UNIT, &parms);
3883
3884 if (parms.nregs != nregs)
3885 abort ();
3886
3887 return parms.ret;
3888}
3889
4fb4e4b8
DE		 3890/* Handle the FUNCTION_ARG macro.
3891 Determine where to put an argument to a function.
3892 Value is zero to push the argument on the stack,
3893 or a hard register in which to store the argument.
3894
3895 CUM is a variable of type CUMULATIVE_ARGS which gives info about
3896 the preceding args and about the function being called.
3897 MODE is the argument's machine mode.
3898 TYPE is the data type of the argument (as a tree).
3899 This is null for libcalls where that information may
3900 not be available.
3901 NAMED is nonzero if this argument is a named parameter
3902 (otherwise it is an extra parameter matching an ellipsis).
3903 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG. */
61a55e8b
DE		 3904
3905rtx
4fb4e4b8
DE		 3906function_arg (cum, mode, type, named, incoming_p)
3907 const CUMULATIVE_ARGS *cum;
3908 enum machine_mode mode;
3909 tree type;
3910 int named;
3911 int incoming_p;
61a55e8b 3912{
4fb4e4b8
DE		 3913 int regbase = (incoming_p
3914 ? SPARC_INCOMING_INT_ARG_FIRST
3915 : SPARC_OUTGOING_INT_ARG_FIRST);
3916 int slotno, regno, padding;
3917 rtx reg;
3918
3919 slotno = function_arg_slotno (cum, mode, type, named, incoming_p,
3920 &regno, &padding);
3921
3922 if (slotno == -1)
3923 return 0;
3924
3925 if (TARGET_ARCH32)
3926 {
254110c2 3927 reg = gen_rtx_REG (mode, regno);
4fb4e4b8
DE		 3928 return reg;
3929 }
3930
3931 /* v9 fp args in reg slots beyond the int reg slots get passed in regs
3932 but also have the slot allocated for them.
3933 If no prototype is in scope fp values in register slots get passed
3934 in two places, either fp regs and int regs or fp regs and memory. */
3935 if ((GET_MODE_CLASS (mode) == MODE_FLOAT
3936 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
3937 && SPARC_FP_REG_P (regno))
3938 {
254110c2 3939 reg = gen_rtx_REG (mode, regno);
4fb4e4b8
DE		 3940 if (cum->prototype_p || cum->libcall_p)
3941 {
3942 /* "* 2" because fp reg numbers are recorded in 4 byte
3943 quantities. */
82d6b402 3944#if 0
4fb4e4b8
DE		 3945 /* ??? This will cause the value to be passed in the fp reg and
3946 in the stack. When a prototype exists we want to pass the
3947 value in the reg but reserve space on the stack. That's an
956d6950 3948 optimization, and is deferred [for a bit]. */
4fb4e4b8 3949 if ((regno - SPARC_FP_ARG_FIRST) >= SPARC_INT_ARG_MAX * 2)
254110c2 3950 return gen_rtx_PARALLEL (mode,
4fb4e4b8 3951 gen_rtvec (2,
254110c2 3952 gen_rtx_EXPR_LIST (VOIDmode,
4fb4e4b8 3953 NULL_RTX, const0_rtx),
254110c2 3954 gen_rtx_EXPR_LIST (VOIDmode,
4fb4e4b8
DE		 3955 reg, const0_rtx)));
3956 else
82d6b402
RH		 3957#else
3958 /* ??? It seems that passing back a register even when past
3959 the area declared by REG_PARM_STACK_SPACE will allocate
3960 space appropriately, and will not copy the data onto the
3961 stack, exactly as we desire.
3962
3963 This is due to locate_and_pad_parm being called in
3964 expand_call whenever reg_parm_stack_space > 0, which
3965 while benefical to our example here, would seem to be
3966 in error from what had been intended. Ho hum... -- r~ */
3967#endif
4fb4e4b8
DE		 3968 return reg;
3969 }
3970 else
3971 {
82d6b402
RH		 3972 rtx v0, v1;
3973
4fb4e4b8
DE		 3974 if ((regno - SPARC_FP_ARG_FIRST) < SPARC_INT_ARG_MAX * 2)
3975 {
82d6b402
RH		 3976 int intreg;
3977
3978 /* On incoming, we don't need to know that the value
3979 is passed in %f0 and %i0, and it confuses other parts
3980 causing needless spillage even on the simplest cases. */
3981 if (incoming_p)
3982 return reg;
3983
3984 intreg = (SPARC_OUTGOING_INT_ARG_FIRST
3985 + (regno - SPARC_FP_ARG_FIRST) / 2);
3986
3987 v0 = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx);
3988 v1 = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_REG (mode, intreg),
3989 const0_rtx);
3990 return gen_rtx_PARALLEL (mode, gen_rtvec (2, v0, v1));
4fb4e4b8
DE		 3991 }
3992 else
82d6b402
RH		 3993 {
3994 v0 = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
3995 v1 = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx);
3996 return gen_rtx_PARALLEL (mode, gen_rtvec (2, v0, v1));
3997 }
4fb4e4b8
DE		 3998 }
3999 }
4000 else if (type && TREE_CODE (type) == RECORD_TYPE)
4001 {
4002 /* Structures up to 16 bytes in size are passed in arg slots on the
4003 stack and are promoted to registers where possible. */
4fb4e4b8
DE		 4004
4005 if (int_size_in_bytes (type) > 16)
4006 abort (); /* shouldn't get here */
4007
1eac9f59 4008 return function_arg_record_value (type, mode, slotno, named, regbase);
4fb4e4b8
DE		 4009 }
4010 else if (type && TREE_CODE (type) == UNION_TYPE)
4011 {
4012 enum machine_mode mode;
4013 int bytes = int_size_in_bytes (type);
4014
4015 if (bytes > 16)
4016 abort ();
4017
4018 mode = mode_for_size (bytes * BITS_PER_UNIT, MODE_INT, 0);
254110c2 4019 reg = gen_rtx_REG (mode, regno);
4fb4e4b8 4020 }
a7acd911 4021 else
4fb4e4b8
DE		 4022 {
4023 /* Scalar or complex int. */
254110c2 4024 reg = gen_rtx_REG (mode, regno);
4fb4e4b8
DE		 4025 }
4026
4027 return reg;
4028}
a7acd911 4029
4fb4e4b8
DE		 4030/* Handle the FUNCTION_ARG_PARTIAL_NREGS macro.
4031 For an arg passed partly in registers and partly in memory,
4032 this is the number of registers used.
4033 For args passed entirely in registers or entirely in memory, zero.
61a55e8b 4034
4fb4e4b8
DE		 4035 Any arg that starts in the first 6 regs but won't entirely fit in them
4036 needs partial registers on v8. On v9, structures with integer
4037 values in arg slots 5,6 will be passed in %o5 and SP+176, and complex fp
4038 values that begin in the last fp reg [where "last fp reg" varies with the
4039 mode] will be split between that reg and memory. */
61a55e8b 4040
4fb4e4b8
DE		 4041int
4042function_arg_partial_nregs (cum, mode, type, named)
4043 const CUMULATIVE_ARGS *cum;
4044 enum machine_mode mode;
4045 tree type;
4046 int named;
4047{
4048 int slotno, regno, padding;
61a55e8b 4049
4fb4e4b8
DE		 4050 /* We pass 0 for incoming_p here, it doesn't matter. */
4051 slotno = function_arg_slotno (cum, mode, type, named, 0, &regno, &padding);
4052
4053 if (slotno == -1)
4054 return 0;
4055
4056 if (TARGET_ARCH32)
bf62bbf1 4057 {
4fb4e4b8
DE		 4058 if ((slotno + (mode == BLKmode
4059 ? ROUND_ADVANCE (int_size_in_bytes (type))
4060 : ROUND_ADVANCE (GET_MODE_SIZE (mode))))
4061 > NPARM_REGS (SImode))
4062 return NPARM_REGS (SImode) - slotno;
4063 return 0;
4064 }
4065 else
4066 {
4067 if (type && AGGREGATE_TYPE_P (type))
4068 {
4069 int size = int_size_in_bytes (type);
4070 int align = TYPE_ALIGN (type);
bf62bbf1 4071
4fb4e4b8
DE		 4072 if (align == 16)
4073 slotno += slotno & 1;
4074 if (size > 8 && size <= 16
4075 && slotno == SPARC_INT_ARG_MAX - 1)
4076 return 1;
4077 }
4078 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_INT
4079 || (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
4080 && ! TARGET_FPU))
4081 {
4082 if (GET_MODE_ALIGNMENT (mode) == 128)
4083 {
4084 slotno += slotno & 1;
4085 if (slotno == SPARC_INT_ARG_MAX - 2)
4086 return 1;
4087 }
4088 else
4089 {
4090 if (slotno == SPARC_INT_ARG_MAX - 1)
4091 return 1;
4092 }
4093 }
4094 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
4095 {
4096 if (GET_MODE_ALIGNMENT (mode) == 128)
4097 slotno += slotno & 1;
4098 if ((slotno + GET_MODE_SIZE (mode) / UNITS_PER_WORD)
4099 > SPARC_FP_ARG_MAX)
4100 return 1;
4101 }
4102 return 0;
bf62bbf1 4103 }
4fb4e4b8 4104}
61a55e8b 4105
4fb4e4b8
DE		 4106/* Handle the FUNCTION_ARG_PASS_BY_REFERENCE macro.
4107 !v9: The SPARC ABI stipulates passing struct arguments (of any size) and
4108 quad-precision floats by invisible reference.
82d6b402 4109 v9: Aggregates greater than 16 bytes are passed by reference.
4fb4e4b8
DE		 4110 For Pascal, also pass arrays by reference. */
4111
4112int
4113function_arg_pass_by_reference (cum, mode, type, named)
db3d4438 4114 const CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED;
4fb4e4b8
DE		 4115 enum machine_mode mode;
4116 tree type;
db3d4438 4117 int named ATTRIBUTE_UNUSED;
4fb4e4b8
DE		 4118{
4119 if (TARGET_ARCH32)
eadceb59 4120 {
5e9defae 4121 return ((type && AGGREGATE_TYPE_P (type))
4fb4e4b8
DE		 4122 || mode == TFmode || mode == TCmode);
4123 }
4124 else
4125 {
4126 return ((type && TREE_CODE (type) == ARRAY_TYPE)
82d6b402
RH		 4127 /* Consider complex values as aggregates, so care for TCmode. */
4128 || GET_MODE_SIZE (mode) > 16
4fb4e4b8
DE		 4129 || (type && AGGREGATE_TYPE_P (type)
4130 && int_size_in_bytes (type) > 16));
4131 }
4132}
4133
4134/* Handle the FUNCTION_ARG_ADVANCE macro.
4135 Update the data in CUM to advance over an argument
4136 of mode MODE and data type TYPE.
4137 TYPE is null for libcalls where that information may not be available. */
4138
4139void
4140function_arg_advance (cum, mode, type, named)
4141 CUMULATIVE_ARGS *cum;
4142 enum machine_mode mode;
4143 tree type;
4144 int named;
4145{
4146 int slotno, regno, padding;
4147
4148 /* We pass 0 for incoming_p here, it doesn't matter. */
4149 slotno = function_arg_slotno (cum, mode, type, named, 0, &regno, &padding);
4150
4151 /* If register required leading padding, add it. */
4152 if (slotno != -1)
4153 cum->words += padding;
eadceb59 4154
4fb4e4b8
DE		 4155 if (TARGET_ARCH32)
4156 {
4157 cum->words += (mode != BLKmode
4158 ? ROUND_ADVANCE (GET_MODE_SIZE (mode))
4159 : ROUND_ADVANCE (int_size_in_bytes (type)));
4160 }
4161 else
4162 {
4163 if (type && AGGREGATE_TYPE_P (type))
4164 {
4165 int size = int_size_in_bytes (type);
4166
4167 if (size <= 8)
4168 ++cum->words;
4169 else if (size <= 16)
4170 cum->words += 2;
4171 else /* passed by reference */
4172 ++cum->words;
4173 }
4174 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_INT)
4175 {
4176 cum->words += 2;
4177 }
4178 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
4179 {
4180 cum->words += GET_MODE_SIZE (mode) / UNITS_PER_WORD;
4181 }
4182 else
4183 {
4184 cum->words += (mode != BLKmode
4185 ? ROUND_ADVANCE (GET_MODE_SIZE (mode))
4186 : ROUND_ADVANCE (int_size_in_bytes (type)));
4187 }
eadceb59 4188 }
4fb4e4b8 4189}
eadceb59 4190
4fb4e4b8
DE		 4191/* Handle the FUNCTION_ARG_PADDING macro.
4192 For the 64 bit ABI structs are always stored left shifted in their
4193 argument slot. */
4194
4195enum direction
4196function_arg_padding (mode, type)
4197 enum machine_mode mode;
4198 tree type;
4199{
c85f7c16
JL		 4200 if (TARGET_ARCH64 && type != 0 && AGGREGATE_TYPE_P (type))
4201 return upward;
61a55e8b 4202
4fb4e4b8
DE		 4203 /* This is the default definition. */
4204 return (! BYTES_BIG_ENDIAN
4205 ? upward
4206 : ((mode == BLKmode
4207 ? (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
4208 && int_size_in_bytes (type) < (PARM_BOUNDARY / BITS_PER_UNIT))
4209 : GET_MODE_BITSIZE (mode) < PARM_BOUNDARY)
4210 ? downward : upward));
61a55e8b 4211}
82d6b402
RH		 4212
4213/* Handle FUNCTION_VALUE, FUNCTION_OUTGOING_VALUE, and LIBCALL_VALUE macros.
4214 For v9, function return values are subject to the same rules as arguments,
4215 except that up to 32-bytes may be returned in registers. */
4216
4217rtx
4218function_value (type, mode, incoming_p)
4219 tree type;
4220 enum machine_mode mode;
4221 int incoming_p;
4222{
4223 int regno;
4224 int regbase = (incoming_p
4225 ? SPARC_OUTGOING_INT_ARG_FIRST
4226 : SPARC_INCOMING_INT_ARG_FIRST);
4227
4228 if (TARGET_ARCH64 && type)
4229 {
4230 if (TREE_CODE (type) == RECORD_TYPE)
4231 {
4232 /* Structures up to 32 bytes in size are passed in registers,
4233 promoted to fp registers where possible. */
4234
4235 if (int_size_in_bytes (type) > 32)
4236 abort (); /* shouldn't get here */
4237
1eac9f59 4238 return function_arg_record_value (type, mode, 0, 1, regbase);
82d6b402
RH		 4239 }
4240 else if (TREE_CODE (type) == UNION_TYPE)
4241 {
4242 int bytes = int_size_in_bytes (type);
4243
4244 if (bytes > 32)
4245 abort ();
4246
4247 mode = mode_for_size (bytes * BITS_PER_UNIT, MODE_INT, 0);
4248 }
4249 }
3c6088d2
JJ		 4250
4251 if (TARGET_ARCH64
4252 && GET_MODE_CLASS (mode) == MODE_INT
4253 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
4254 && type && TREE_CODE (type) != UNION_TYPE)
4255 mode = DImode;
82d6b402
RH		 4256
4257 if (incoming_p)
4258 regno = BASE_RETURN_VALUE_REG (mode);
4259 else
4260 regno = BASE_OUTGOING_VALUE_REG (mode);
4261
254110c2 4262 return gen_rtx_REG (mode, regno);
82d6b402
RH		 4263}
4264
648d2ffc
RH		 4265/* Do what is necessary for `va_start'. We look at the current function
4266 to determine if stdarg or varargs is used and return the address of
4267 the first unnamed parameter. */
3ea1fdd3
JW		 4268
4269rtx
648d2ffc 4270sparc_builtin_saveregs ()
3ea1fdd3 4271{
4fb4e4b8 4272 int first_reg = current_function_args_info.words;
3ea1fdd3
JW		 4273 rtx address;
4274 int regno;
4275
4fb4e4b8 4276 for (regno = first_reg; regno < NPARM_REGS (word_mode); regno++)
254110c2
DM		 4277 emit_move_insn (gen_rtx_MEM (word_mode,
4278 gen_rtx_PLUS (Pmode,
3ea1fdd3
JW		 4279 frame_pointer_rtx,
4280 GEN_INT (STACK_POINTER_OFFSET
4281 + UNITS_PER_WORD * regno))),
254110c2 4282 gen_rtx_REG (word_mode,
4fb4e4b8 4283 BASE_INCOMING_ARG_REG (word_mode) + regno));
3ea1fdd3 4284
254110c2 4285 address = gen_rtx_PLUS (Pmode,
3ea1fdd3
JW		 4286 frame_pointer_rtx,
4287 GEN_INT (STACK_POINTER_OFFSET
4288 + UNITS_PER_WORD * first_reg));
4289
7d384cc0 4290 if (current_function_check_memory_usage
4fb4e4b8 4291 && first_reg < NPARM_REGS (word_mode))
eadceb59
RK		 4292 emit_library_call (chkr_set_right_libfunc, 1, VOIDmode, 3,
4293 address, ptr_mode,
4294 GEN_INT (UNITS_PER_WORD
4fb4e4b8 4295 * (NPARM_REGS (word_mode) - first_reg)),
956d6950
JL		 4296 TYPE_MODE (sizetype), GEN_INT (MEMORY_USE_RW),
4297 TYPE_MODE (integer_type_node));
eadceb59 4298
3ea1fdd3
JW		 4299 return address;
4300}
a8b2c8a1
RH		 4301
4302/* Implement `va_start' for varargs and stdarg. */
4303
4304void
4305sparc_va_start (stdarg_p, valist, nextarg)
4306 int stdarg_p ATTRIBUTE_UNUSED;
4307 tree valist;
4308 rtx nextarg;
4309{
4310 nextarg = expand_builtin_saveregs ();
4311 std_expand_builtin_va_start (1, valist, nextarg);
4312}
4313
4314/* Implement `va_arg'. */
4315
4316rtx
4317sparc_va_arg (valist, type)
4318 tree valist, type;
4319{
4320 HOST_WIDE_INT size, rsize, align;
da09e317 4321 tree addr, incr;
a8b2c8a1
RH		 4322 rtx addr_rtx;
4323 int indirect = 0;
4324
4325 /* Round up sizeof(type) to a word. */
4326 size = int_size_in_bytes (type);
4327 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
4328 align = 0;
4329
4330 if (TARGET_ARCH64)
4331 {
4332 if (TYPE_ALIGN (type) >= 2 * BITS_PER_WORD)
4333 align = 2 * UNITS_PER_WORD;
4334
4335 if (AGGREGATE_TYPE_P (type) && size > 16)
4336 {
4337 indirect = 1;
4338 size = rsize = UNITS_PER_WORD;
4339 }
4340 }
4341 else
4342 {
4343 if (AGGREGATE_TYPE_P (type)
4344 || TYPE_MODE (type) == TFmode
4345 || TYPE_MODE (type) == TCmode)
4346 {
4347 indirect = 1;
4348 size = rsize = UNITS_PER_WORD;
4349 }
4350 else
4351 {
4352 /* ??? The old va-sparc.h implementation, for 8 byte objects
4353 copied stuff to a temporary -- I don't see that that
4354 provides any more alignment than the stack slot did. */
4355 }
4356 }
4357
4358 incr = valist;
4359 if (align)
4360 {
4361 incr = fold (build (PLUS_EXPR, ptr_type_node, incr,
4362 build_int_2 (align - 1, 0)));
4363 incr = fold (build (BIT_AND_EXPR, ptr_type_node, incr,
4364 build_int_2 (-align, -1)));
4365 }
4366
4367 addr = incr = save_expr (incr);
4368 if (BYTES_BIG_ENDIAN && size < rsize)
4369 {
4370 addr = fold (build (PLUS_EXPR, ptr_type_node, incr,
4371 build_int_2 (rsize - size, 0)));
4372 }
4373 incr = fold (build (PLUS_EXPR, ptr_type_node, incr,
4374 build_int_2 (rsize, 0)));
4375
4376 incr = build (MODIFY_EXPR, ptr_type_node, valist, incr);
4377 TREE_SIDE_EFFECTS (incr) = 1;
4378 expand_expr (incr, const0_rtx, VOIDmode, EXPAND_NORMAL);
4379
4380 addr_rtx = expand_expr (addr, NULL, Pmode, EXPAND_NORMAL);
4381
4382 if (indirect)
4383 {
4384 addr_rtx = force_reg (Pmode, addr_rtx);
4385 addr_rtx = gen_rtx_MEM (Pmode, addr_rtx);
4386 MEM_ALIAS_SET (addr_rtx) = get_varargs_alias_set ();
4387 }
4388
4389 return addr_rtx;
4390}
ab835497
RK		 4391\f
4392/* Return the string to output a conditional branch to LABEL, which is
c4ce6853
DE		 4393 the operand number of the label. OP is the conditional expression.
4394 XEXP (OP, 0) is assumed to be a condition code register (integer or
4395 floating point) and its mode specifies what kind of comparison we made.
61a55e8b 4396
ab835497
RK		 4397 REVERSED is non-zero if we should reverse the sense of the comparison.
4398
4399 ANNUL is non-zero if we should generate an annulling branch.
4400
c6b0465b
JC		 4401 NOOP is non-zero if we have to follow this branch by a noop.
4402
4403 INSN, if set, is the insn. */
ab835497
RK		 4404
4405char *
c6b0465b 4406output_cbranch (op, label, reversed, annul, noop, insn)
c4ce6853 4407 rtx op;
ab835497
RK		 4408 int label;
4409 int reversed, annul, noop;
c6b0465b 4410 rtx insn;
ab835497 4411{
e0d80184 4412 static char string[32];
ab835497 4413 enum rtx_code code = GET_CODE (op);
c4ce6853
DE		 4414 rtx cc_reg = XEXP (op, 0);
4415 enum machine_mode mode = GET_MODE (cc_reg);
e0d80184
DM		 4416 static char v8_labelno[] = "%lX";
4417 static char v9_icc_labelno[] = "%%icc, %lX";
4418 static char v9_xcc_labelno[] = "%%xcc, %lX";
4419 static char v9_fcc_labelno[] = "%%fccX, %lY";
61a55e8b 4420 char *labelno;
e0d80184 4421 int labeloff, spaces = 8;
61a55e8b
DE		 4422
4423 /* ??? !v9: FP branches cannot be preceded by another floating point insn.
ab835497
RK		 4424 Because there is currently no concept of pre-delay slots, we can fix
4425 this only by always emitting a nop before a floating point branch. */
4426
61a55e8b 4427 if ((mode == CCFPmode || mode == CCFPEmode) && ! TARGET_V9)
ab835497 4428 strcpy (string, "nop\n\t");
61a55e8b
DE		 4429 else
4430 string[0] = '\0';
ab835497
RK		 4431
4432 /* If not floating-point or if EQ or NE, we can just reverse the code. */
4d449554
JW		 4433 if (reversed
4434 && ((mode != CCFPmode && mode != CCFPEmode) || code == EQ || code == NE))
ab835497
RK		 4435 code = reverse_condition (code), reversed = 0;
4436
4437 /* Start by writing the branch condition. */
4438 switch (code)
4439 {
4440 case NE:
4d449554 4441 if (mode == CCFPmode || mode == CCFPEmode)
e0d80184
DM		 4442 {
4443 strcat (string, "fbne");
4444 spaces -= 4;
4445 }
ab835497 4446 else
e0d80184
DM		 4447 {
4448 strcpy (string, "bne");
4449 spaces -= 3;
4450 }
ab835497
RK		 4451 break;
4452
4453 case EQ:
4d449554 4454 if (mode == CCFPmode || mode == CCFPEmode)
e0d80184
DM		 4455 {
4456 strcat (string, "fbe");
4457 spaces -= 3;
4458 }
ab835497 4459 else
e0d80184
DM		 4460 {
4461 strcpy (string, "be");
4462 spaces -= 2;
4463 }
ab835497
RK		 4464 break;
4465
4466 case GE:
4d449554 4467 if (mode == CCFPmode || mode == CCFPEmode)
ab835497
RK		 4468 {
4469 if (reversed)
4470 strcat (string, "fbul");
4471 else
4472 strcat (string, "fbge");
e0d80184 4473 spaces -= 4;
ab835497
RK		 4474 }
4475 else if (mode == CC_NOOVmode)
e0d80184
DM		 4476 {
4477 strcpy (string, "bpos");
4478 spaces -= 4;
4479 }
ab835497 4480 else
e0d80184
DM		 4481 {
4482 strcpy (string, "bge");
4483 spaces -= 3;
4484 }
ab835497
RK		 4485 break;
4486
4487 case GT:
4d449554 4488 if (mode == CCFPmode || mode == CCFPEmode)
ab835497
RK		 4489 {
4490 if (reversed)
e0d80184
DM		 4491 {
4492 strcat (string, "fbule");
4493 spaces -= 5;
4494 }
ab835497 4495 else
e0d80184
DM		 4496 {
4497 strcat (string, "fbg");
4498 spaces -= 3;
4499 }
ab835497
RK		 4500 }
4501 else
e0d80184
DM		 4502 {
4503 strcpy (string, "bg");
4504 spaces -= 2;
4505 }
ab835497
RK		 4506 break;
4507
4508 case LE:
4d449554 4509 if (mode == CCFPmode || mode == CCFPEmode)
ab835497
RK		 4510 {
4511 if (reversed)
4512 strcat (string, "fbug");
4513 else
4514 strcat (string, "fble");
e0d80184 4515 spaces -= 4;
ab835497
RK		 4516 }
4517 else
e0d80184
DM		 4518 {
4519 strcpy (string, "ble");
4520 spaces -= 3;
4521 }
ab835497
RK		 4522 break;
4523
4524 case LT:
4d449554 4525 if (mode == CCFPmode || mode == CCFPEmode)
ab835497
RK		 4526 {
4527 if (reversed)
e0d80184
DM		 4528 {
4529 strcat (string, "fbuge");
4530 spaces -= 5;
4531 }
ab835497 4532 else
e0d80184
DM		 4533 {
4534 strcat (string, "fbl");
4535 spaces -= 3;
4536 }
ab835497
RK		 4537 }
4538 else if (mode == CC_NOOVmode)
e0d80184
DM		 4539 {
4540 strcpy (string, "bneg");
4541 spaces -= 4;
4542 }
ab835497 4543 else
e0d80184
DM		 4544 {
4545 strcpy (string, "bl");
4546 spaces -= 2;
4547 }
ab835497
RK		 4548 break;
4549
4550 case GEU:
4551 strcpy (string, "bgeu");
e0d80184 4552 spaces -= 4;
ab835497
RK		 4553 break;
4554
4555 case GTU:
4556 strcpy (string, "bgu");
e0d80184 4557 spaces -= 3;
ab835497
RK		 4558 break;
4559
4560 case LEU:
4561 strcpy (string, "bleu");
e0d80184 4562 spaces -= 4;
ab835497
RK		 4563 break;
4564
4565 case LTU:
4566 strcpy (string, "blu");
e0d80184 4567 spaces -= 3;
ab835497 4568 break;
91a51951
KG		 4569
4570 default:
e0d80184 4571 abort ();
ab835497
RK		 4572 }
4573
4574 /* Now add the annulling, the label, and a possible noop. */
4575 if (annul)
e0d80184
DM		 4576 {
4577 strcat (string, ",a");
4578 spaces -= 2;
4579 }
ab835497 4580
61a55e8b
DE		 4581 if (! TARGET_V9)
4582 {
e0d80184 4583 labeloff = 2;
61a55e8b
DE		 4584 labelno = v8_labelno;
4585 }
4586 else
4587 {
c6b0465b
JC		 4588 rtx note;
4589
4590 if (insn && (note = find_reg_note (insn, REG_BR_PRED, NULL_RTX)))
e0d80184
DM		 4591 {
4592 strcat (string,
4593 INTVAL (XEXP (note, 0)) & ATTR_FLAG_likely ? ",pt" : ",pn");
4594 spaces -= 3;
4595 }
c6b0465b 4596
61a55e8b
DE		 4597 labeloff = 9;
4598 if (mode == CCFPmode || mode == CCFPEmode)
4599 {
4600 labeloff = 10;
4601 labelno = v9_fcc_labelno;
4602 /* Set the char indicating the number of the fcc reg to use. */
e0d80184 4603 labelno[5] = REGNO (cc_reg) - SPARC_FIRST_V9_FCC_REG + '0';
61a55e8b
DE		 4604 }
4605 else if (mode == CCXmode || mode == CCX_NOOVmode)
4606 labelno = v9_xcc_labelno;
4607 else
4608 labelno = v9_icc_labelno;
4609 }
4610 /* Set the char indicating the number of the operand containing the
4611 label_ref. */
4612 labelno[labeloff] = label + '0';
e0d80184
DM		 4613 if (spaces > 0)
4614 strcat (string, "\t");
4615 else
4616 strcat (string, " ");
61a55e8b
DE		 4617 strcat (string, labelno);
4618
4619 if (noop)
4620 strcat (string, "\n\tnop");
4621
4622 return string;
4623}
4624
4625/* Return the string to output a conditional branch to LABEL, testing
4626 register REG. LABEL is the operand number of the label; REG is the
4627 operand number of the reg. OP is the conditional expression. The mode
4628 of REG says what kind of comparison we made.
4629
4630 REVERSED is non-zero if we should reverse the sense of the comparison.
4631
4632 ANNUL is non-zero if we should generate an annulling branch.
4633
4634 NOOP is non-zero if we have to follow this branch by a noop. */
4635
4636char *
e0d80184 4637output_v9branch (op, reg, label, reversed, annul, noop, insn)
61a55e8b
DE		 4638 rtx op;
4639 int reg, label;
4640 int reversed, annul, noop;
e0d80184 4641 rtx insn;
61a55e8b
DE		 4642{
4643 static char string[20];
4644 enum rtx_code code = GET_CODE (op);
4645 enum machine_mode mode = GET_MODE (XEXP (op, 0));
e0d80184
DM		 4646 static char labelno[] = "%X, %lX";
4647 rtx note;
4648 int spaces = 8;
61a55e8b
DE		 4649
4650 /* If not floating-point or if EQ or NE, we can just reverse the code. */
4651 if (reversed)
4652 code = reverse_condition (code), reversed = 0;
4653
4654 /* Only 64 bit versions of these instructions exist. */
4655 if (mode != DImode)
4656 abort ();
4657
4658 /* Start by writing the branch condition. */
4659
4660 switch (code)
4661 {
4662 case NE:
4663 strcpy (string, "brnz");
e0d80184 4664 spaces -= 4;
61a55e8b
DE		 4665 break;
4666
4667 case EQ:
4668 strcpy (string, "brz");
e0d80184 4669 spaces -= 3;
61a55e8b
DE		 4670 break;
4671
4672 case GE:
4673 strcpy (string, "brgez");
e0d80184 4674 spaces -= 5;
61a55e8b
DE		 4675 break;
4676
4677 case LT:
4678 strcpy (string, "brlz");
e0d80184 4679 spaces -= 4;
61a55e8b
DE		 4680 break;
4681
4682 case LE:
4683 strcpy (string, "brlez");
e0d80184 4684 spaces -= 5;
61a55e8b
DE		 4685 break;
4686
4687 case GT:
4688 strcpy (string, "brgz");
e0d80184 4689 spaces -= 4;
61a55e8b
DE		 4690 break;
4691
4692 default:
4693 abort ();
4694 }
4695
4696 /* Now add the annulling, reg, label, and nop. */
4697 if (annul)
e0d80184
DM		 4698 {
4699 strcat (string, ",a");
4700 spaces -= 2;
4701 }
61a55e8b 4702
e0d80184
DM		 4703 if (insn && (note = find_reg_note (insn, REG_BR_PRED, NULL_RTX)))
4704 {
4705 strcat (string,
4706 INTVAL (XEXP (note, 0)) & ATTR_FLAG_likely ? ",pt" : ",pn");
4707 spaces -= 3;
4708 }
61a55e8b 4709
e0d80184 4710 labelno[1] = reg + '0';
61a55e8b 4711 labelno[6] = label + '0';
e0d80184
DM		 4712 if (spaces > 0)
4713 strcat (string, "\t");
4714 else
4715 strcat (string, " ");
ab835497
RK		 4716 strcat (string, labelno);
4717
4718 if (noop)
4719 strcat (string, "\n\tnop");
4720
4721 return string;
4722}
4723
284d86e9
JC		 4724/* Renumber registers in delay slot. Replace registers instead of
4725 renumbering because they may be shared.
795068a4 4726
284d86e9
JC		 4727 This does not handle instructions other than move. */
4728
4729static void
4730epilogue_renumber (where)
4731 rtx *where;
4732{
4733 rtx x = *where;
4734 enum rtx_code code = GET_CODE (x);
4735
4736 switch (code)
4737 {
4738 case MEM:
4739 *where = x = copy_rtx (x);
4740 epilogue_renumber (&XEXP (x, 0));
4741 return;
4742
4743 case REG:
4744 {
4745 int regno = REGNO (x);
4746 if (regno > 8 && regno < 24)
4747 abort ();
4748 if (regno >= 24 && regno < 32)
4749 *where = gen_rtx_REG (GET_MODE (x), regno - 16);
4750 return;
4751 }
4752 case CONST_INT:
4753 case CONST_DOUBLE:
4754 case CONST:
4755 case SYMBOL_REF:
4756 case LABEL_REF:
4757 return;
4758
4759 case IOR:
4760 case AND:
4761 case XOR:
4762 case PLUS:
4763 case MINUS:
4764 epilogue_renumber (&XEXP (x, 1));
4765 case NEG:
4766 case NOT:
4767 epilogue_renumber (&XEXP (x, 0));
4768 return;
4769
4770 default:
4771 debug_rtx (*where);
9208e4b2 4772 abort ();
284d86e9
JC		 4773 }
4774}
4775
4776/* Output assembler code to return from a function. */
61a55e8b 4777
3bb5de61 4778const char *
ab835497
RK		 4779output_return (operands)
4780 rtx *operands;
4781{
284d86e9
JC		 4782 rtx delay = final_sequence ? XVECEXP (final_sequence, 0, 1) : 0;
4783
ab835497
RK		 4784 if (leaf_label)
4785 {
4786 operands[0] = leaf_label;
284d86e9 4787 return "b%* %l0%(";
ab835497 4788 }
54ff41b7 4789 else if (current_function_uses_only_leaf_regs)
ab835497 4790 {
284d86e9
JC		 4791 /* No delay slot in a leaf function. */
4792 if (delay)
4793 abort ();
4794
915f619f
JW		 4795 /* If we didn't allocate a frame pointer for the current function,
4796 the stack pointer might have been adjusted. Output code to
4797 restore it now. */
4798
3a598fbe 4799 operands[0] = GEN_INT (actual_fsize);
915f619f
JW		 4800
4801 /* Use sub of negated value in first two cases instead of add to
4802 allow actual_fsize == 4096. */
4803
4804 if (actual_fsize <= 4096)
ab835497 4805 {
61a55e8b 4806 if (SKIP_CALLERS_UNIMP_P)
e0d80184 4807 return "jmp\t%%o7+12\n\tsub\t%%sp, -%0, %%sp";
ab835497 4808 else
e0d80184 4809 return "retl\n\tsub\t%%sp, -%0, %%sp";
ab835497 4810 }
915f619f 4811 else if (actual_fsize <= 8192)
ab835497 4812 {
3a598fbe 4813 operands[0] = GEN_INT (actual_fsize - 4096);
61a55e8b 4814 if (SKIP_CALLERS_UNIMP_P)
e0d80184 4815 return "sub\t%%sp, -4096, %%sp\n\tjmp\t%%o7+12\n\tsub\t%%sp, -%0, %%sp";
915f619f 4816 else
e0d80184 4817 return "sub\t%%sp, -4096, %%sp\n\tretl\n\tsub\t%%sp, -%0, %%sp";
915f619f 4818 }
61a55e8b 4819 else if (SKIP_CALLERS_UNIMP_P)
915f619f
JW		 4820 {
4821 if ((actual_fsize & 0x3ff) != 0)
e0d80184 4822 return "sethi\t%%hi(%a0), %%g1\n\tor\t%%g1, %%lo(%a0), %%g1\n\tjmp\t%%o7+12\n\tadd\t%%sp, %%g1, %%sp";
ab835497 4823 else
e0d80184 4824 return "sethi\t%%hi(%a0), %%g1\n\tjmp\t%%o7+12\n\tadd\t%%sp, %%g1, %%sp";
915f619f
JW		 4825 }
4826 else
4827 {
4828 if ((actual_fsize & 0x3ff) != 0)
ab835497 4829 return "sethi %%hi(%a0),%%g1\n\tor %%g1,%%lo(%a0),%%g1\n\tretl\n\tadd %%sp,%%g1,%%sp";
915f619f
JW		 4830 else
4831 return "sethi %%hi(%a0),%%g1\n\tretl\n\tadd %%sp,%%g1,%%sp";
ab835497
RK		 4832 }
4833 }
284d86e9
JC		 4834 else if (TARGET_V9)
4835 {
4836 if (delay)
4837 {
4838 epilogue_renumber (&SET_DEST (PATTERN (delay)));
4839 epilogue_renumber (&SET_SRC (PATTERN (delay)));
4840 }
4841 if (SKIP_CALLERS_UNIMP_P)
e0d80184 4842 return "return\t%%i7+12%#";
284d86e9 4843 else
e0d80184 4844 return "return\t%%i7+8%#";
284d86e9 4845 }
ab835497
RK		 4846 else
4847 {
284d86e9
JC		 4848 if (delay)
4849 abort ();
61a55e8b 4850 if (SKIP_CALLERS_UNIMP_P)
e0d80184 4851 return "jmp\t%%i7+12\n\trestore";
ab835497
RK		 4852 else
4853 return "ret\n\trestore";
4854 }
4855}
ab835497
RK		 4856\f
4857/* Leaf functions and non-leaf functions have different needs. */
4858
4859static int
4860reg_leaf_alloc_order[] = REG_LEAF_ALLOC_ORDER;
4861
4862static int
4863reg_nonleaf_alloc_order[] = REG_ALLOC_ORDER;
4864
4865static int *reg_alloc_orders[] = {
4866 reg_leaf_alloc_order,
4867 reg_nonleaf_alloc_order};
4868
4869void
4870order_regs_for_local_alloc ()
4871{
4872 static int last_order_nonleaf = 1;
4873
4874 if (regs_ever_live[15] != last_order_nonleaf)
4875 {
4876 last_order_nonleaf = !last_order_nonleaf;
d2889939
RK		 4877 bcopy ((char *) reg_alloc_orders[last_order_nonleaf],
4878 (char *) reg_alloc_order, FIRST_PSEUDO_REGISTER * sizeof (int));
ab835497
RK		 4879 }
4880}
4881\f
e0d80184
DM		 4882/* Return 1 if REG and MEM are legitimate enough to allow the various
4883 mem<-->reg splits to be run. */
4884
4885int
e61c29e9 4886sparc_splitdi_legitimate (reg, mem)
e0d80184
DM		 4887 rtx reg;
4888 rtx mem;
4889{
e0d80184
DM		 4890 /* Punt if we are here by mistake. */
4891 if (! reload_completed)
9208e4b2 4892 abort ();
e0d80184
DM		 4893
4894 /* We must have an offsettable memory reference. */
4895 if (! offsettable_memref_p (mem))
4896 return 0;
4897
4898 /* If we have legitimate args for ldd/std, we do not want
4899 the split to happen. */
4900 if ((REGNO (reg) % 2) == 0
4901 && mem_min_alignment (mem, 8))
4902 return 0;
4903
4904 /* Success. */
4905 return 1;
4906}
4907
e61c29e9
DM		 4908/* Return 1 if x and y are some kind of REG and they refer to
4909 different hard registers. This test is guarenteed to be
4910 run after reload. */
4911
4912int
4913sparc_absnegfloat_split_legitimate (x, y)
4914 rtx x, y;
4915{
4916 if (GET_CODE (x) == SUBREG)
4917 x = alter_subreg (x);
4918 if (GET_CODE (x) != REG)
4919 return 0;
4920 if (GET_CODE (y) == SUBREG)
4921 y = alter_subreg (y);
4922 if (GET_CODE (y) != REG)
4923 return 0;
4924 if (REGNO (x) == REGNO (y))
4925 return 0;
4926 return 1;
4927}
4928
35016322
JW		 4929/* Return 1 if REGNO (reg1) is even and REGNO (reg1) == REGNO (reg2) - 1.
4930 This makes them candidates for using ldd and std insns.
4931
bfd6bc60 4932 Note reg1 and reg2 *must* be hard registers. */
35016322
JW		 4933
4934int
7c56249d 4935registers_ok_for_ldd_peep (reg1, reg2)
35016322
JW		 4936 rtx reg1, reg2;
4937{
35016322
JW		 4938 /* We might have been passed a SUBREG. */
4939 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
4940 return 0;
4941
35016322
JW		 4942 if (REGNO (reg1) % 2 != 0)
4943 return 0;
4944
bfd6bc60
JC		 4945 /* Integer ldd is deprecated in SPARC V9 */
4946 if (TARGET_V9 && REGNO (reg1) < 32)
4947 return 0;
4948
35016322 4949 return (REGNO (reg1) == REGNO (reg2) - 1);
35016322
JW		 4950}
4951
4952/* Return 1 if addr1 and addr2 are suitable for use in an ldd or
4953 std insn.
4954
4955 This can only happen when addr1 and addr2 are consecutive memory
4956 locations (addr1 + 4 == addr2). addr1 must also be aligned on a
4957 64 bit boundary (addr1 % 8 == 0).
4958
4959 We know %sp and %fp are kept aligned on a 64 bit boundary. Other
4960 registers are assumed to *never* be properly aligned and are
4961 rejected.
4962
4963 Knowing %sp and %fp are kept aligned on a 64 bit boundary, we
4964 need only check that the offset for addr1 % 8 == 0. */
4965
4966int
7c56249d 4967addrs_ok_for_ldd_peep (addr1, addr2)
35016322
JW		 4968 rtx addr1, addr2;
4969{
4970 int reg1, offset1;
4971
4972 /* Extract a register number and offset (if used) from the first addr. */
4973 if (GET_CODE (addr1) == PLUS)
4974 {
4975 /* If not a REG, return zero. */
4976 if (GET_CODE (XEXP (addr1, 0)) != REG)
4977 return 0;
4978 else
4979 {
4980 reg1 = REGNO (XEXP (addr1, 0));
4981 /* The offset must be constant! */
4982 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
4983 return 0;
4984 offset1 = INTVAL (XEXP (addr1, 1));
4985 }
4986 }
4987 else if (GET_CODE (addr1) != REG)
4988 return 0;
4989 else
4990 {
4991 reg1 = REGNO (addr1);
4992 /* This was a simple (mem (reg)) expression. Offset is 0. */
4993 offset1 = 0;
4994 }
4995
4996 /* Make sure the second address is a (mem (plus (reg) (const_int). */
4997 if (GET_CODE (addr2) != PLUS)
4998 return 0;
4999
5000 if (GET_CODE (XEXP (addr2, 0)) != REG
5001 || GET_CODE (XEXP (addr2, 1)) != CONST_INT)
5002 return 0;
5003
5004 /* Only %fp and %sp are allowed. Additionally both addresses must
5005 use the same register. */
5006 if (reg1 != FRAME_POINTER_REGNUM && reg1 != STACK_POINTER_REGNUM)
5007 return 0;
5008
5009 if (reg1 != REGNO (XEXP (addr2, 0)))
5010 return 0;
5011
2296cba3 5012 /* The first offset must be evenly divisible by 8 to ensure the
35016322
JW		 5013 address is 64 bit aligned. */
5014 if (offset1 % 8 != 0)
5015 return 0;
5016
5017 /* The offset for the second addr must be 4 more than the first addr. */
5018 if (INTVAL (XEXP (addr2, 1)) != offset1 + 4)
5019 return 0;
5020
5021 /* All the tests passed. addr1 and addr2 are valid for ldd and std
5022 instructions. */
5023 return 1;
5024}
7c56249d
JL		 5025
5026/* Return 1 if reg is a pseudo, or is the first register in
5027 a hard register pair. This makes it a candidate for use in
5028 ldd and std insns. */
5029
5030int
5031register_ok_for_ldd (reg)
5032 rtx reg;
5033{
7c56249d
JL		 5034 /* We might have been passed a SUBREG. */
5035 if (GET_CODE (reg) != REG)
5036 return 0;
5037
5038 if (REGNO (reg) < FIRST_PSEUDO_REGISTER)
5039 return (REGNO (reg) % 2 == 0);
5040 else
5041 return 1;
7c56249d 5042}
ab835497 5043\f
ab835497
RK		 5044/* Print operand X (an rtx) in assembler syntax to file FILE.
5045 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
5046 For `%' followed by punctuation, CODE is the punctuation and X is null. */
5047
5048void
5049print_operand (file, x, code)
5050 FILE *file;
5051 rtx x;
5052 int code;
5053{
5054 switch (code)
5055 {
5056 case '#':
5057 /* Output a 'nop' if there's nothing for the delay slot. */
5058 if (dbr_sequence_length () == 0)
e0d80184 5059 fputs ("\n\t nop", file);
ab835497
RK		 5060 return;
5061 case '*':
c6ce0969
JW		 5062 /* Output an annul flag if there's nothing for the delay slot and we
5063 are optimizing. This is always used with '(' below. */
5064 /* Sun OS 4.1.1 dbx can't handle an annulled unconditional branch;
5065 this is a dbx bug. So, we only do this when optimizing. */
bfd6bc60
JC		 5066 /* On UltraSPARC, a branch in a delay slot causes a pipeline flush.
5067 Always emit a nop in case the next instruction is a branch. */
5068 if (dbr_sequence_length () == 0
284d86e9 5069 && (optimize && (int)sparc_cpu < PROCESSOR_V9))
c6ce0969
JW		 5070 fputs (",a", file);
5071 return;
5072 case '(':
5073 /* Output a 'nop' if there's nothing for the delay slot and we are
5074 not optimizing. This is always used with '*' above. */
bfd6bc60 5075 if (dbr_sequence_length () == 0
284d86e9 5076 && ! (optimize && (int)sparc_cpu < PROCESSOR_V9))
e0d80184 5077 fputs ("\n\t nop", file);
ab835497 5078 return;
61a55e8b 5079 case '_':
a0a301fc
DE		 5080 /* Output the Embedded Medium/Anywhere code model base register. */
5081 fputs (EMBMEDANY_BASE_REG, file);
61a55e8b
DE		 5082 return;
5083 case '@':
5084 /* Print out what we are using as the frame pointer. This might
5085 be %fp, or might be %sp+offset. */
5086 /* ??? What if offset is too big? Perhaps the caller knows it isn't? */
5087 fprintf (file, "%s+%d", frame_base_name, frame_base_offset);
5088 return;
ab835497
RK		 5089 case 'Y':
5090 /* Adjust the operand to take into account a RESTORE operation. */
bfd6bc60
JC		 5091 if (GET_CODE (x) == CONST_INT)
5092 break;
5093 else if (GET_CODE (x) != REG)
b3b1e8bd
JW		 5094 output_operand_lossage ("Invalid %%Y operand");
5095 else if (REGNO (x) < 8)
ab835497
RK		 5096 fputs (reg_names[REGNO (x)], file);
5097 else if (REGNO (x) >= 24 && REGNO (x) < 32)
5098 fputs (reg_names[REGNO (x)-16], file);
5099 else
b3b1e8bd 5100 output_operand_lossage ("Invalid %%Y operand");
ab835497 5101 return;
0f39a9aa
DE		 5102 case 'L':
5103 /* Print out the low order register name of a register pair. */
5104 if (WORDS_BIG_ENDIAN)
5105 fputs (reg_names[REGNO (x)+1], file);
5106 else
5107 fputs (reg_names[REGNO (x)], file);
5108 return;
5109 case 'H':
5110 /* Print out the high order register name of a register pair. */
5111 if (WORDS_BIG_ENDIAN)
5112 fputs (reg_names[REGNO (x)], file);
5113 else
5114 fputs (reg_names[REGNO (x)+1], file);
5115 return;
ab835497 5116 case 'R':
795068a4 5117 /* Print out the second register name of a register pair or quad.
ab835497
RK		 5118 I.e., R (%o0) => %o1. */
5119 fputs (reg_names[REGNO (x)+1], file);
5120 return;
795068a4
JW		 5121 case 'S':
5122 /* Print out the third register name of a register quad.
5123 I.e., S (%o0) => %o2. */
5124 fputs (reg_names[REGNO (x)+2], file);
5125 return;
5126 case 'T':
5127 /* Print out the fourth register name of a register quad.
5128 I.e., T (%o0) => %o3. */
5129 fputs (reg_names[REGNO (x)+3], file);
5130 return;
304b7a23
DE		 5131 case 'x':
5132 /* Print a condition code register. */
5133 if (REGNO (x) == SPARC_ICC_REG)
5134 {
5135 /* We don't handle CC[X]_NOOVmode because they're not supposed
5136 to occur here. */
5137 if (GET_MODE (x) == CCmode)
5138 fputs ("%icc", file);
5139 else if (GET_MODE (x) == CCXmode)
5140 fputs ("%xcc", file);
5141 else
5142 abort ();
5143 }
5144 else
5145 /* %fccN register */
5146 fputs (reg_names[REGNO (x)], file);
5147 return;
ab835497
RK		 5148 case 'm':
5149 /* Print the operand's address only. */
5150 output_address (XEXP (x, 0));
5151 return;
5152 case 'r':
5153 /* In this case we need a register. Use %g0 if the
77a02b01 5154 operand is const0_rtx. */
76052e74
RS		 5155 if (x == const0_rtx
5156 || (GET_MODE (x) != VOIDmode && x == CONST0_RTX (GET_MODE (x))))
ab835497
RK		 5157 {
5158 fputs ("%g0", file);
5159 return;
5160 }
5161 else
5162 break;
5163
61a55e8b 5164 case 'A':
ab835497
RK		 5165 switch (GET_CODE (x))
5166 {
5167 case IOR: fputs ("or", file); break;
5168 case AND: fputs ("and", file); break;
5169 case XOR: fputs ("xor", file); break;
b3b1e8bd 5170 default: output_operand_lossage ("Invalid %%A operand");
ab835497
RK		 5171 }
5172 return;
5173
5174 case 'B':
5175 switch (GET_CODE (x))
5176 {
5177 case IOR: fputs ("orn", file); break;
5178 case AND: fputs ("andn", file); break;
5179 case XOR: fputs ("xnor", file); break;
b3b1e8bd 5180 default: output_operand_lossage ("Invalid %%B operand");
ab835497
RK		 5181 }
5182 return;
5183
304b7a23
DE		 5184 /* These are used by the conditional move instructions. */
5185 case 'c' :
61a55e8b 5186 case 'C':
304b7a23
DE		 5187 {
5188 enum rtx_code rc = (code == 'c'
5189 ? reverse_condition (GET_CODE (x))
5190 : GET_CODE (x));
5191 switch (rc)
5192 {
5193 case NE: fputs ("ne", file); break;
5194 case EQ: fputs ("e", file); break;
5195 case GE: fputs ("ge", file); break;
5196 case GT: fputs ("g", file); break;
5197 case LE: fputs ("le", file); break;
5198 case LT: fputs ("l", file); break;
5199 case GEU: fputs ("geu", file); break;
5200 case GTU: fputs ("gu", file); break;
5201 case LEU: fputs ("leu", file); break;
5202 case LTU: fputs ("lu", file); break;
5203 default: output_operand_lossage (code == 'c'
5204 ? "Invalid %%c operand"
5205 : "Invalid %%C operand");
5206 }
5207 return;
5208 }
5209
5210 /* These are used by the movr instruction pattern. */
5211 case 'd':
61a55e8b 5212 case 'D':
304b7a23
DE		 5213 {
5214 enum rtx_code rc = (code == 'd'
5215 ? reverse_condition (GET_CODE (x))
5216 : GET_CODE (x));
5217 switch (rc)
5218 {
5219 case NE: fputs ("ne", file); break;
5220 case EQ: fputs ("e", file); break;
5221 case GE: fputs ("gez", file); break;
5222 case LT: fputs ("lz", file); break;
5223 case LE: fputs ("lez", file); break;
5224 case GT: fputs ("gz", file); break;
5225 default: output_operand_lossage (code == 'd'
5226 ? "Invalid %%d operand"
5227 : "Invalid %%D operand");
5228 }
5229 return;
5230 }
61a55e8b 5231
ab835497
RK		 5232 case 'b':
5233 {
5234 /* Print a sign-extended character. */
5235 int i = INTVAL (x) & 0xff;
5236 if (i & 0x80)
5237 i |= 0xffffff00;
5238 fprintf (file, "%d", i);
5239 return;
5240 }
5241
d2889939
RK		 5242 case 'f':
5243 /* Operand must be a MEM; write its address. */
5244 if (GET_CODE (x) != MEM)
5245 output_operand_lossage ("Invalid %%f operand");
5246 output_address (XEXP (x, 0));
5247 return;
5248
ab835497
RK		 5249 case 0:
5250 /* Do nothing special. */
5251 break;
5252
5253 default:
5254 /* Undocumented flag. */
415f583e 5255 output_operand_lossage ("invalid operand output code");
ab835497
RK		 5256 }
5257
5258 if (GET_CODE (x) == REG)
5259 fputs (reg_names[REGNO (x)], file);
5260 else if (GET_CODE (x) == MEM)
5261 {
5262 fputc ('[', file);
ab835497 5263 /* Poor Sun assembler doesn't understand absolute addressing. */
c4ce6853
DE		 5264 if (CONSTANT_P (XEXP (x, 0))
5265 && ! TARGET_LIVE_G0)
ab835497
RK		 5266 fputs ("%g0+", file);
5267 output_address (XEXP (x, 0));
5268 fputc (']', file);
5269 }
5270 else if (GET_CODE (x) == HIGH)
5271 {
5272 fputs ("%hi(", file);
5273 output_addr_const (file, XEXP (x, 0));
5274 fputc (')', file);
5275 }
5276 else if (GET_CODE (x) == LO_SUM)
5277 {
5278 print_operand (file, XEXP (x, 0), 0);
e0d80184
DM		 5279 if (TARGET_CM_MEDMID)
5280 fputs ("+%l44(", file);
5281 else
5282 fputs ("+%lo(", file);
ab835497
RK		 5283 output_addr_const (file, XEXP (x, 1));
5284 fputc (')', file);
5285 }
e601abce
JW		 5286 else if (GET_CODE (x) == CONST_DOUBLE
5287 && (GET_MODE (x) == VOIDmode
5288 || GET_MODE_CLASS (GET_MODE (x)) == MODE_INT))
ab835497
RK		 5289 {
5290 if (CONST_DOUBLE_HIGH (x) == 0)
5291 fprintf (file, "%u", CONST_DOUBLE_LOW (x));
5292 else if (CONST_DOUBLE_HIGH (x) == -1
5293 && CONST_DOUBLE_LOW (x) < 0)
5294 fprintf (file, "%d", CONST_DOUBLE_LOW (x));
5295 else
e601abce 5296 output_operand_lossage ("long long constant not a valid immediate operand");
ab835497 5297 }
e601abce
JW		 5298 else if (GET_CODE (x) == CONST_DOUBLE)
5299 output_operand_lossage ("floating point constant not a valid immediate operand");
ab835497
RK		 5300 else { output_addr_const (file, x); }
5301}
5302\f
5303/* This function outputs assembler code for VALUE to FILE, where VALUE is
5304 a 64 bit (DImode) value. */
5305
5306/* ??? If there is a 64 bit counterpart to .word that the assembler
5307 understands, then using that would simply this code greatly. */
61a55e8b
DE		 5308/* ??? We only output .xword's for symbols and only then in environments
5309 where the assembler can handle them. */
ab835497
RK		 5310
5311void
5312output_double_int (file, value)
5313 FILE *file;
5314 rtx value;
5315{
5316 if (GET_CODE (value) == CONST_INT)
5317 {
f4f8e370
DE		 5318 /* ??? This has endianness issues. */
5319#if HOST_BITS_PER_WIDE_INT == 64
5320 HOST_WIDE_INT xword = INTVAL (value);
5321 HOST_WIDE_INT high, low;
5322
5323 high = (xword >> 32) & 0xffffffff;
5324 low = xword & 0xffffffff;
3a598fbe
JL		 5325 ASM_OUTPUT_INT (file, GEN_INT (high));
5326 ASM_OUTPUT_INT (file, GEN_INT (low));
f4f8e370 5327#else
ab835497
RK		 5328 if (INTVAL (value) < 0)
5329 ASM_OUTPUT_INT (file, constm1_rtx);
5330 else
5331 ASM_OUTPUT_INT (file, const0_rtx);
5332 ASM_OUTPUT_INT (file, value);
f4f8e370 5333#endif
ab835497
RK		 5334 }
5335 else if (GET_CODE (value) == CONST_DOUBLE)
5336 {
3a598fbe
JL		 5337 ASM_OUTPUT_INT (file, GEN_INT (CONST_DOUBLE_HIGH (value)));
5338 ASM_OUTPUT_INT (file, GEN_INT (CONST_DOUBLE_LOW (value)));
ab835497
RK		 5339 }
5340 else if (GET_CODE (value) == SYMBOL_REF
5341 || GET_CODE (value) == CONST
61a55e8b 5342 || GET_CODE (value) == PLUS
a9e27770 5343 || (TARGET_ARCH64 &&
61a55e8b 5344 (GET_CODE (value) == LABEL_REF
9fa9626b 5345 || GET_CODE (value) == CODE_LABEL
61a55e8b 5346 || GET_CODE (value) == MINUS)))
ab835497 5347 {
f3b8847b 5348 if (! TARGET_V9)
61a55e8b
DE		 5349 {
5350 ASM_OUTPUT_INT (file, const0_rtx);
5351 ASM_OUTPUT_INT (file, value);
5352 }
5353 else
5354 {
5355 fprintf (file, "\t%s\t", ASM_LONGLONG);
5356 output_addr_const (file, value);
5357 fprintf (file, "\n");
5358 }
ab835497
RK		 5359 }
5360 else
5361 abort ();
5362}
210aa14a 5363\f
b0468b84
RK		 5364/* Return the value of a code used in the .proc pseudo-op that says
5365 what kind of result this function returns. For non-C types, we pick
5366 the closest C type. */
5367
77a02b01
JW		 5368#ifndef CHAR_TYPE_SIZE
5369#define CHAR_TYPE_SIZE BITS_PER_UNIT
5370#endif
5371
5372#ifndef SHORT_TYPE_SIZE
5373#define SHORT_TYPE_SIZE (BITS_PER_UNIT * 2)
5374#endif
5375
5376#ifndef INT_TYPE_SIZE
5377#define INT_TYPE_SIZE BITS_PER_WORD
5378#endif
5379
5380#ifndef LONG_TYPE_SIZE
5381#define LONG_TYPE_SIZE BITS_PER_WORD
5382#endif
5383
5384#ifndef LONG_LONG_TYPE_SIZE
5385#define LONG_LONG_TYPE_SIZE (BITS_PER_WORD * 2)
5386#endif
5387
5388#ifndef FLOAT_TYPE_SIZE
5389#define FLOAT_TYPE_SIZE BITS_PER_WORD
5390#endif
5391
5392#ifndef DOUBLE_TYPE_SIZE
5393#define DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
5394#endif
5395
5396#ifndef LONG_DOUBLE_TYPE_SIZE
5397#define LONG_DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
5398#endif
210aa14a
RS		 5399
5400unsigned long
5401sparc_type_code (type)
5402 register tree type;
5403{
5404 register unsigned long qualifiers = 0;
e5e809f4 5405 register unsigned shift;
210aa14a 5406
abc95ed3 5407 /* Only the first 30 bits of the qualifier are valid. We must refrain from
aee2c3c5
JW		 5408 setting more, since some assemblers will give an error for this. Also,
5409 we must be careful to avoid shifts of 32 bits or more to avoid getting
5410 unpredictable results. */
5411
e5e809f4 5412 for (shift = 6; shift < 30; shift += 2, type = TREE_TYPE (type))
210aa14a
RS		 5413 {
5414 switch (TREE_CODE (type))
5415 {
5416 case ERROR_MARK:
5417 return qualifiers;
5418
5419 case ARRAY_TYPE:
e5e809f4 5420 qualifiers |= (3 << shift);
210aa14a
RS		 5421 break;
5422
5423 case FUNCTION_TYPE:
5424 case METHOD_TYPE:
e5e809f4 5425 qualifiers |= (2 << shift);
210aa14a
RS		 5426 break;
5427
5428 case POINTER_TYPE:
5429 case REFERENCE_TYPE:
5430 case OFFSET_TYPE:
e5e809f4 5431 qualifiers |= (1 << shift);
210aa14a 5432 break;
ab835497 5433
210aa14a
RS		 5434 case RECORD_TYPE:
5435 return (qualifiers | 8);
5436
5437 case UNION_TYPE:
b0468b84 5438 case QUAL_UNION_TYPE:
210aa14a
RS		 5439 return (qualifiers | 9);
5440
5441 case ENUMERAL_TYPE:
5442 return (qualifiers | 10);
5443
5444 case VOID_TYPE:
5445 return (qualifiers | 16);
5446
5447 case INTEGER_TYPE:
654209e6
JW		 5448 /* If this is a range type, consider it to be the underlying
5449 type. */
5450 if (TREE_TYPE (type) != 0)
e5e809f4 5451 break;
654209e6 5452
77a02b01 5453 /* Carefully distinguish all the standard types of C,
b0468b84
RK		 5454 without messing up if the language is not C. We do this by
5455 testing TYPE_PRECISION and TREE_UNSIGNED. The old code used to
5456 look at both the names and the above fields, but that's redundant.
5457 Any type whose size is between two C types will be considered
5458 to be the wider of the two types. Also, we do not have a
5459 special code to use for "long long", so anything wider than
5460 long is treated the same. Note that we can't distinguish
5461 between "int" and "long" in this code if they are the same
5462 size, but that's fine, since neither can the assembler. */
5463
5464 if (TYPE_PRECISION (type) <= CHAR_TYPE_SIZE)
5465 return (qualifiers | (TREE_UNSIGNED (type) ? 12 : 2));
77a02b01 5466
b0468b84
RK		 5467 else if (TYPE_PRECISION (type) <= SHORT_TYPE_SIZE)
5468 return (qualifiers | (TREE_UNSIGNED (type) ? 13 : 3));
77a02b01 5469
b0468b84 5470 else if (TYPE_PRECISION (type) <= INT_TYPE_SIZE)
77a02b01
JW		 5471 return (qualifiers | (TREE_UNSIGNED (type) ? 14 : 4));
5472
b0468b84 5473 else
77a02b01
JW		 5474 return (qualifiers | (TREE_UNSIGNED (type) ? 15 : 5));
5475
210aa14a 5476 case REAL_TYPE:
e5e809f4
JL		 5477 /* If this is a range type, consider it to be the underlying
5478 type. */
5479 if (TREE_TYPE (type) != 0)
5480 break;
5481
77a02b01
JW		 5482 /* Carefully distinguish all the standard types of C,
5483 without messing up if the language is not C. */
b0468b84 5484
77a02b01 5485 if (TYPE_PRECISION (type) == FLOAT_TYPE_SIZE)
210aa14a 5486 return (qualifiers | 6);
b0468b84
RK		 5487
5488 else
5489 return (qualifiers | 7);
210aa14a
RS		 5490
5491 case COMPLEX_TYPE: /* GNU Fortran COMPLEX type. */
13d39dbc 5492 /* ??? We need to distinguish between double and float complex types,
c82aa69a
JW		 5493 but I don't know how yet because I can't reach this code from
5494 existing front-ends. */
5495 return (qualifiers | 7); /* Who knows? */
5496
210aa14a
RS		 5497 case CHAR_TYPE: /* GNU Pascal CHAR type. Not used in C. */
5498 case BOOLEAN_TYPE: /* GNU Fortran BOOLEAN type. */
5499 case FILE_TYPE: /* GNU Pascal FILE type. */
26902ae0 5500 case SET_TYPE: /* GNU Pascal SET type. */
210aa14a 5501 case LANG_TYPE: /* ? */
26902ae0 5502 return qualifiers;
210aa14a
RS		 5503
5504 default:
5505 abort (); /* Not a type! */
5506 }
5507 }
e5e809f4
JL		 5508
5509 return qualifiers;
210aa14a 5510}
ead69aea 5511\f
61a55e8b
DE		 5512/* Nested function support. */
5513
5514/* Emit RTL insns to initialize the variable parts of a trampoline.
5515 FNADDR is an RTX for the address of the function's pure code.
5516 CXT is an RTX for the static chain value for the function.
5517
5518 This takes 16 insns: 2 shifts & 2 ands (to split up addresses), 4 sethi
5519 (to load in opcodes), 4 iors (to merge address and opcodes), and 4 writes
5520 (to store insns). This is a bit excessive. Perhaps a different
5521 mechanism would be better here.
5522
849a528d 5523 Emit enough FLUSH insns to synchronize the data and instruction caches. */
61a55e8b
DE		 5524
5525void
5526sparc_initialize_trampoline (tramp, fnaddr, cxt)
5527 rtx tramp, fnaddr, cxt;
5528{
c6b0465b
JC		 5529 /* SPARC 32 bit trampoline:
5530
e0d80184
DM		 5531 sethi %hi(fn), %g1
5532 sethi %hi(static), %g2
5533 jmp %g1+%lo(fn)
5534 or %g2, %lo(static), %g2
c6b0465b
JC		 5535
5536 SETHI i,r = 00rr rrr1 00ii iiii iiii iiii iiii iiii
5537 JMPL r+i,d = 10dd ddd1 1100 0rrr rr1i iiii iiii iiii
5538 */
959eb758
DM		 5539#ifdef TRANSFER_FROM_TRAMPOLINE
5540 emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "__enable_execute_stack"),
5541 0, VOIDmode, 1, tramp, Pmode);
5542#endif
c6b0465b
JC		 5543
5544 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 0)),
5545 expand_binop (SImode, ior_optab,
5546 expand_shift (RSHIFT_EXPR, SImode, fnaddr,
5547 size_int (10), 0, 1),
5548 GEN_INT (0x03000000),
5549 NULL_RTX, 1, OPTAB_DIRECT));
5550
5551 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 4)),
5552 expand_binop (SImode, ior_optab,
5553 expand_shift (RSHIFT_EXPR, SImode, cxt,
5554 size_int (10), 0, 1),
5555 GEN_INT (0x05000000),
5556 NULL_RTX, 1, OPTAB_DIRECT));
5557
5558 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 8)),
5559 expand_binop (SImode, ior_optab,
5560 expand_and (fnaddr, GEN_INT (0x3ff), NULL_RTX),
5561 GEN_INT (0x81c06000),
5562 NULL_RTX, 1, OPTAB_DIRECT));
5563
5564 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 12)),
5565 expand_binop (SImode, ior_optab,
5566 expand_and (cxt, GEN_INT (0x3ff), NULL_RTX),
5567 GEN_INT (0x8410a000),
5568 NULL_RTX, 1, OPTAB_DIRECT));
5569
254110c2 5570 emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode, tramp))));
c6b0465b
JC		 5571 /* On UltraSPARC a flush flushes an entire cache line. The trampoline is
5572 aligned on a 16 byte boundary so one flush clears it all. */
5573 if (sparc_cpu != PROCESSOR_ULTRASPARC)
5574 emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode,
5575 plus_constant (tramp, 8)))));
61a55e8b
DE		 5576}
5577
849a528d
RK		 5578/* The 64 bit version is simpler because it makes more sense to load the
5579 values as "immediate" data out of the trampoline. It's also easier since
5580 we can read the PC without clobbering a register. */
5581
61a55e8b
DE		 5582void
5583sparc64_initialize_trampoline (tramp, fnaddr, cxt)
5584 rtx tramp, fnaddr, cxt;
5585{
345a6161
DM		 5586#ifdef TRANSFER_FROM_TRAMPOLINE
5587 emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "__enable_execute_stack"),
5588 0, VOIDmode, 1, tramp, Pmode);
5589#endif
5590
c6b0465b 5591 /*
e0d80184
DM		 5592 rd %pc, %g1
5593 ldx [%g1+24], %g5
5594 jmp %g5
5595 ldx [%g1+16], %g5
c6b0465b
JC		 5596 +16 bytes data
5597 */
5598
5599 emit_move_insn (gen_rtx_MEM (SImode, tramp),
5600 GEN_INT (0x83414000));
5601 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 4)),
5602 GEN_INT (0xca586018));
5603 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 8)),
345a6161 5604 GEN_INT (0x81c14000));
c6b0465b
JC		 5605 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 12)),
5606 GEN_INT (0xca586010));
5607 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 16)), cxt);
345a6161 5608 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 24)), fnaddr);
254110c2 5609 emit_insn (gen_flush (validize_mem (gen_rtx_MEM (DImode, tramp))));
345a6161 5610
c6b0465b
JC		 5611 if (sparc_cpu != PROCESSOR_ULTRASPARC)
5612 emit_insn (gen_flush (validize_mem (gen_rtx_MEM (DImode, plus_constant (tramp, 8)))));
61a55e8b
DE		 5613}
5614\f
c819be5b
JW		 5615/* Subroutines to support a flat (single) register window calling
5616 convention. */
5617
5618/* Single-register window sparc stack frames look like:
5619
5620 Before call After call
5621 +-----------------------+ +-----------------------+
86735b02
DE		 5622 high | | | |
5623 mem | caller's temps. | | caller's temps. |
c819be5b
JW		 5624 | | | |
5625 +-----------------------+ +-----------------------+
5626 | | | |
5627 | arguments on stack. | | arguments on stack. |
86735b02
DE		 5628 | | | |
5629 +-----------------------+FP+92->+-----------------------+
c819be5b
JW		 5630 | 6 words to save | | 6 words to save |
5631 | arguments passed | | arguments passed |
5632 | in registers, even | | in registers, even |
86735b02
DE		 5633 | if not passed. | | if not passed. |
5634 SP+68->+-----------------------+FP+68->+-----------------------+
5635 | 1 word struct addr | | 1 word struct addr |
5636 +-----------------------+FP+64->+-----------------------+
5637 | | | |
5638 | 16 word reg save area | | 16 word reg save area |
5639 | | | |
5640 SP->+-----------------------+ FP->+-----------------------+
5641 | 4 word area for |
5642 | fp/alu reg moves |
5643 FP-16->+-----------------------+
5644 | |
5645 | local variables |
5646 | |
5647 +-----------------------+
5648 | |
c819be5b 5649 | fp register save |
86735b02
DE		 5650 | |
5651 +-----------------------+
5652 | |
c819be5b
JW		 5653 | gp register save |
5654 | |
86735b02
DE		 5655 +-----------------------+
5656 | |
c819be5b 5657 | alloca allocations |
86735b02
DE		 5658 | |
5659 +-----------------------+
5660 | |
c819be5b 5661 | arguments on stack |
86735b02
DE		 5662 | |
5663 SP+92->+-----------------------+
c819be5b 5664 | 6 words to save |
86735b02 5665 | arguments passed |
c819be5b 5666 | in registers, even |
86735b02
DE		 5667 low | if not passed. |
5668 memory SP+68->+-----------------------+
5669 | 1 word struct addr |
5670 SP+64->+-----------------------+
5671 | |
5672 I 16 word reg save area |
5673 | |
5674 SP->+-----------------------+ */
c819be5b 5675
c6aa9ce1 5676/* Structure to be filled in by sparc_flat_compute_frame_size with register
c819be5b
JW		 5677 save masks, and offsets for the current function. */
5678
5679struct sparc_frame_info
5680{
5681 unsigned long total_size; /* # bytes that the entire frame takes up. */
5682 unsigned long var_size; /* # bytes that variables take up. */
5683 unsigned long args_size; /* # bytes that outgoing arguments take up. */
5684 unsigned long extra_size; /* # bytes of extra gunk. */
5685 unsigned int gp_reg_size; /* # bytes needed to store gp regs. */
5686 unsigned int fp_reg_size; /* # bytes needed to store fp regs. */
86735b02 5687 unsigned long gmask; /* Mask of saved gp registers. */
c819be5b 5688 unsigned long fmask; /* Mask of saved fp registers. */
86735b02 5689 unsigned long reg_offset; /* Offset from new sp to store regs. */
c819be5b
JW		 5690 int initialized; /* Nonzero if frame size already calculated. */
5691};
5692
c6aa9ce1 5693/* Current frame information calculated by sparc_flat_compute_frame_size. */
c819be5b
JW		 5694struct sparc_frame_info current_frame_info;
5695
5696/* Zero structure to initialize current_frame_info. */
5697struct sparc_frame_info zero_frame_info;
5698
5699/* Tell prologue and epilogue if register REGNO should be saved / restored. */
5700
86735b02
DE		 5701#define RETURN_ADDR_REGNUM 15
5702#define FRAME_POINTER_MASK (1 << (FRAME_POINTER_REGNUM))
5703#define RETURN_ADDR_MASK (1 << (RETURN_ADDR_REGNUM))
5704
c819be5b
JW		 5705#define MUST_SAVE_REGISTER(regno) \
5706 ((regs_ever_live[regno] && !call_used_regs[regno]) \
5707 || (regno == FRAME_POINTER_REGNUM && frame_pointer_needed) \
86735b02 5708 || (regno == RETURN_ADDR_REGNUM && regs_ever_live[RETURN_ADDR_REGNUM]))
c819be5b
JW		 5709
5710/* Return the bytes needed to compute the frame pointer from the current
5711 stack pointer. */
5712
5713unsigned long
c6aa9ce1 5714sparc_flat_compute_frame_size (size)
c819be5b
JW		 5715 int size; /* # of var. bytes allocated. */
5716{
5717 int regno;
5718 unsigned long total_size; /* # bytes that the entire frame takes up. */
5719 unsigned long var_size; /* # bytes that variables take up. */
5720 unsigned long args_size; /* # bytes that outgoing arguments take up. */
5721 unsigned long extra_size; /* # extra bytes. */
5722 unsigned int gp_reg_size; /* # bytes needed to store gp regs. */
5723 unsigned int fp_reg_size; /* # bytes needed to store fp regs. */
86735b02 5724 unsigned long gmask; /* Mask of saved gp registers. */
c819be5b 5725 unsigned long fmask; /* Mask of saved fp registers. */
86735b02
DE		 5726 unsigned long reg_offset; /* Offset to register save area. */
5727 int need_aligned_p; /* 1 if need the save area 8 byte aligned. */
c819be5b
JW		 5728
5729 /* This is the size of the 16 word reg save area, 1 word struct addr
5730 area, and 4 word fp/alu register copy area. */
8c64be75
SC		 5731 extra_size = -STARTING_FRAME_OFFSET + FIRST_PARM_OFFSET(0);
5732 var_size = size;
5733 gp_reg_size = 0;
5734 fp_reg_size = 0;
5735 gmask = 0;
5736 fmask = 0;
5737 reg_offset = 0;
86735b02 5738 need_aligned_p = 0;
c819be5b 5739
8c64be75
SC		 5740 args_size = 0;
5741 if (!leaf_function_p ())
5742 {
5743 /* Also include the size needed for the 6 parameter registers. */
5744 args_size = current_function_outgoing_args_size + 24;
5745 }
5746 total_size = var_size + args_size;
5747
c819be5b
JW		 5748 /* Calculate space needed for gp registers. */
5749 for (regno = 1; regno <= 31; regno++)
5750 {
5751 if (MUST_SAVE_REGISTER (regno))
5752 {
86735b02
DE		 5753 /* If we need to save two regs in a row, ensure there's room to bump
5754 up the address to align it to a doubleword boundary. */
c819be5b
JW		 5755 if ((regno & 0x1) == 0 && MUST_SAVE_REGISTER (regno+1))
5756 {
5757 if (gp_reg_size % 8 != 0)
86735b02 5758 gp_reg_size += 4;
c819be5b 5759 gp_reg_size += 2 * UNITS_PER_WORD;
86735b02 5760 gmask |= 3 << regno;
c819be5b 5761 regno++;
86735b02 5762 need_aligned_p = 1;
c819be5b
JW		 5763 }
5764 else
5765 {
5766 gp_reg_size += UNITS_PER_WORD;
86735b02 5767 gmask |= 1 << regno;
c819be5b
JW		 5768 }
5769 }
5770 }
c819be5b
JW		 5771
5772 /* Calculate space needed for fp registers. */
5773 for (regno = 32; regno <= 63; regno++)
5774 {
5775 if (regs_ever_live[regno] && !call_used_regs[regno])
5776 {
5777 fp_reg_size += UNITS_PER_WORD;
5778 fmask |= 1 << (regno - 32);
5779 }
5780 }
5781
86735b02
DE		 5782 if (gmask || fmask)
5783 {
5784 int n;
5785 reg_offset = FIRST_PARM_OFFSET(0) + args_size;
5786 /* Ensure save area is 8 byte aligned if we need it. */
5787 n = reg_offset % 8;
5788 if (need_aligned_p && n != 0)
5789 {
5790 total_size += 8 - n;
5791 reg_offset += 8 - n;
5792 }
5793 total_size += gp_reg_size + fp_reg_size;
5794 }
c819be5b 5795
8c64be75
SC		 5796 /* If we must allocate a stack frame at all, we must also allocate
5797 room for register window spillage, so as to be binary compatible
5798 with libraries and operating systems that do not use -mflat. */
5799 if (total_size > 0)
5800 total_size += extra_size;
5801 else
5802 extra_size = 0;
c819be5b
JW		 5803
5804 total_size = SPARC_STACK_ALIGN (total_size);
5805
5806 /* Save other computed information. */
5807 current_frame_info.total_size = total_size;
5808 current_frame_info.var_size = var_size;
5809 current_frame_info.args_size = args_size;
5810 current_frame_info.extra_size = extra_size;
5811 current_frame_info.gp_reg_size = gp_reg_size;
5812 current_frame_info.fp_reg_size = fp_reg_size;
86735b02 5813 current_frame_info.gmask = gmask;
c819be5b 5814 current_frame_info.fmask = fmask;
86735b02 5815 current_frame_info.reg_offset = reg_offset;
c819be5b
JW		 5816 current_frame_info.initialized = reload_completed;
5817
c819be5b
JW		 5818 /* Ok, we're done. */
5819 return total_size;
5820}
5821\f
86735b02
DE		 5822/* Save/restore registers in GMASK and FMASK at register BASE_REG plus offset
5823 OFFSET.
5824
5825 BASE_REG must be 8 byte aligned. This allows us to test OFFSET for
5826 appropriate alignment and use DOUBLEWORD_OP when we can. We assume
5827 [BASE_REG+OFFSET] will always be a valid address.
5828
5829 WORD_OP is either "st" for save, "ld" for restore.
5830 DOUBLEWORD_OP is either "std" for save, "ldd" for restore. */
c819be5b
JW		 5831
5832void
96987e96
DE		 5833sparc_flat_save_restore (file, base_reg, offset, gmask, fmask, word_op,
5834 doubleword_op, base_offset)
86735b02 5835 FILE *file;
b1474bb7 5836 const char *base_reg;
86735b02
DE		 5837 unsigned int offset;
5838 unsigned long gmask;
5839 unsigned long fmask;
b1474bb7
KG		 5840 const char *word_op;
5841 const char *doubleword_op;
c53aa195 5842 unsigned long base_offset;
c819be5b
JW		 5843{
5844 int regno;
c819be5b 5845
86735b02
DE		 5846 if (gmask == 0 && fmask == 0)
5847 return;
c819be5b 5848
86735b02
DE		 5849 /* Save registers starting from high to low. We've already saved the
5850 previous frame pointer and previous return address for the debugger's
5851 sake. The debugger allows us to not need a nop in the epilog if at least
5852 one register is reloaded in addition to return address. */
c819be5b 5853
86735b02 5854 if (gmask)
c819be5b
JW		 5855 {
5856 for (regno = 1; regno <= 31; regno++)
5857 {
86735b02 5858 if ((gmask & (1L << regno)) != 0)
c819be5b 5859 {
86735b02 5860 if ((regno & 0x1) == 0 && ((gmask & (1L << (regno+1))) != 0))
c819be5b 5861 {
86735b02
DE		 5862 /* We can save two registers in a row. If we're not at a
5863 double word boundary, move to one.
5864 sparc_flat_compute_frame_size ensures there's room to do
5865 this. */
5866 if (offset % 8 != 0)
5867 offset += UNITS_PER_WORD;
5868
c819be5b 5869 if (word_op[0] == 's')
c53aa195 5870 {
e0d80184 5871 fprintf (file, "\t%s\t%s, [%s+%d]\n",
c53aa195
JM		 5872 doubleword_op, reg_names[regno],
5873 base_reg, offset);
0021b564 5874 if (dwarf2out_do_frame ())
c53aa195 5875 {
96987e96 5876 char *l = dwarf2out_cfi_label ();
c53aa195
JM		 5877 dwarf2out_reg_save (l, regno, offset + base_offset);
5878 dwarf2out_reg_save
5879 (l, regno+1, offset+base_offset + UNITS_PER_WORD);
5880 }
c53aa195 5881 }
c819be5b 5882 else
e0d80184 5883 fprintf (file, "\t%s\t[%s+%d], %s\n",
86735b02 5884 doubleword_op, base_reg, offset,
c819be5b
JW		 5885 reg_names[regno]);
5886
86735b02 5887 offset += 2 * UNITS_PER_WORD;
c819be5b
JW		 5888 regno++;
5889 }
5890 else
5891 {
5892 if (word_op[0] == 's')
c53aa195 5893 {
e0d80184 5894 fprintf (file, "\t%s\t%s, [%s+%d]\n",
c53aa195
JM		 5895 word_op, reg_names[regno],
5896 base_reg, offset);
0021b564 5897 if (dwarf2out_do_frame ())
c53aa195 5898 dwarf2out_reg_save ("", regno, offset + base_offset);
c53aa195 5899 }
c819be5b 5900 else
e0d80184 5901 fprintf (file, "\t%s\t[%s+%d], %s\n",
86735b02 5902 word_op, base_reg, offset, reg_names[regno]);
c819be5b 5903
86735b02 5904 offset += UNITS_PER_WORD;
c819be5b
JW		 5905 }
5906 }
5907 }
5908 }
5909
5910 if (fmask)
5911 {
5912 for (regno = 32; regno <= 63; regno++)
5913 {
5914 if ((fmask & (1L << (regno - 32))) != 0)
5915 {
5916 if (word_op[0] == 's')
c53aa195 5917 {
e0d80184 5918 fprintf (file, "\t%s\t%s, [%s+%d]\n",
c53aa195
JM		 5919 word_op, reg_names[regno],
5920 base_reg, offset);
0021b564 5921 if (dwarf2out_do_frame ())
c53aa195 5922 dwarf2out_reg_save ("", regno, offset + base_offset);
c53aa195 5923 }
c819be5b 5924 else
e0d80184 5925 fprintf (file, "\t%s\t[%s+%d], %s\n",
86735b02 5926 word_op, base_reg, offset, reg_names[regno]);
c819be5b 5927
86735b02 5928 offset += UNITS_PER_WORD;
c819be5b
JW		 5929 }
5930 }
5931 }
5932}
5933\f
5934/* Set up the stack and frame (if desired) for the function. */
5935
5936void
c6aa9ce1 5937sparc_flat_output_function_prologue (file, size)
c819be5b
JW		 5938 FILE *file;
5939 int size;
5940{
c819be5b 5941 char *sp_str = reg_names[STACK_POINTER_REGNUM];
86735b02 5942 unsigned long gmask = current_frame_info.gmask;
a07c1915 5943
1cb36a98
RH		 5944 sparc_output_scratch_registers (file);
5945
c6aa9ce1 5946 /* This is only for the human reader. */
bf62bbf1 5947 fprintf (file, "\t%s#PROLOGUE# 0\n", ASM_COMMENT_START);
5e9defae 5948 fprintf (file, "\t%s# vars= %ld, regs= %d/%d, args= %d, extra= %ld\n",
bf62bbf1 5949 ASM_COMMENT_START,
86735b02
DE		 5950 current_frame_info.var_size,
5951 current_frame_info.gp_reg_size / 4,
9f8b85b8 5952 current_frame_info.fp_reg_size / 4,
86735b02
DE		 5953 current_function_outgoing_args_size,
5954 current_frame_info.extra_size);
c819be5b
JW		 5955
5956 size = SPARC_STACK_ALIGN (size);
86735b02
DE		 5957 size = (! current_frame_info.initialized
5958 ? sparc_flat_compute_frame_size (size)
5959 : current_frame_info.total_size);
c819be5b 5960
86735b02
DE		 5961 /* These cases shouldn't happen. Catch them now. */
5962 if (size == 0 && (gmask || current_frame_info.fmask))
5963 abort ();
c819be5b 5964
86735b02
DE		 5965 /* Allocate our stack frame by decrementing %sp.
5966 At present, the only algorithm gdb can use to determine if this is a
5967 flat frame is if we always set %i7 if we set %sp. This can be optimized
5968 in the future by putting in some sort of debugging information that says
5969 this is a `flat' function. However, there is still the case of debugging
5970 code without such debugging information (including cases where most fns
5971 have such info, but there is one that doesn't). So, always do this now
5972 so we don't get a lot of code out there that gdb can't handle.
5973 If the frame pointer isn't needn't then that's ok - gdb won't be able to
5974 distinguish us from a non-flat function but there won't (and shouldn't)
5975 be any differences anyway. The return pc is saved (if necessary) right
5976 after %i7 so gdb won't have to look too far to find it. */
5977 if (size > 0)
c819be5b 5978 {
86735b02 5979 unsigned int reg_offset = current_frame_info.reg_offset;
c6aa9ce1 5980 char *fp_str = reg_names[FRAME_POINTER_REGNUM];
3bb5de61 5981 const char *t1_str = "%g1";
86735b02
DE		 5982
5983 /* Things get a little tricky if local variables take up more than ~4096
5984 bytes and outgoing arguments take up more than ~4096 bytes. When that
5985 happens, the register save area can't be accessed from either end of
5986 the frame. Handle this by decrementing %sp to the start of the gp
5987 register save area, save the regs, update %i7, and then set %sp to its
5988 final value. Given that we only have one scratch register to play
5989 with it is the cheapest solution, and it helps gdb out as it won't
5990 slow down recognition of flat functions.
5991 Don't change the order of insns emitted here without checking with
5992 the gdb folk first. */
5993
ddd5a7c1 5994 /* Is the entire register save area offsettable from %sp? */
86735b02
DE		 5995 if (reg_offset < 4096 - 64 * UNITS_PER_WORD)
5996 {
5997 if (size <= 4096)
5998 {
e0d80184 5999 fprintf (file, "\tadd\t%s, %d, %s\n",
86735b02
DE		 6000 sp_str, -size, sp_str);
6001 if (gmask & FRAME_POINTER_MASK)
6002 {
e0d80184 6003 fprintf (file, "\tst\t%s, [%s+%d]\n",
86735b02 6004 fp_str, sp_str, reg_offset);
e0d80184 6005 fprintf (file, "\tsub\t%s, %d, %s\t%s# set up frame pointer\n",
bf62bbf1 6006 sp_str, -size, fp_str, ASM_COMMENT_START);
86735b02
DE		 6007 reg_offset += 4;
6008 }
6009 }
6010 else
6011 {
e0d80184 6012 fprintf (file, "\tset\t%d, %s\n\tsub\t%s, %s, %s\n",
86735b02
DE		 6013 size, t1_str, sp_str, t1_str, sp_str);
6014 if (gmask & FRAME_POINTER_MASK)
6015 {
e0d80184 6016 fprintf (file, "\tst\t%s, [%s+%d]\n",
86735b02 6017 fp_str, sp_str, reg_offset);
e0d80184 6018 fprintf (file, "\tadd\t%s, %s, %s\t%s# set up frame pointer\n",
bf62bbf1 6019 sp_str, t1_str, fp_str, ASM_COMMENT_START);
86735b02
DE		 6020 reg_offset += 4;
6021 }
6022 }
0021b564 6023 if (dwarf2out_do_frame ())
c53aa195 6024 {
96987e96 6025 char *l = dwarf2out_cfi_label ();
c53aa195
JM		 6026 if (gmask & FRAME_POINTER_MASK)
6027 {
6028 dwarf2out_reg_save (l, FRAME_POINTER_REGNUM,
6029 reg_offset - 4 - size);
6030 dwarf2out_def_cfa (l, FRAME_POINTER_REGNUM, 0);
6031 }
6032 else
6033 dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, size);
6034 }
86735b02
DE		 6035 if (gmask & RETURN_ADDR_MASK)
6036 {
e0d80184 6037 fprintf (file, "\tst\t%s, [%s+%d]\n",
86735b02 6038 reg_names[RETURN_ADDR_REGNUM], sp_str, reg_offset);
0021b564 6039 if (dwarf2out_do_frame ())
c53aa195 6040 dwarf2out_return_save ("", reg_offset - size);
86735b02
DE		 6041 reg_offset += 4;
6042 }
6043 sparc_flat_save_restore (file, sp_str, reg_offset,
6044 gmask & ~(FRAME_POINTER_MASK | RETURN_ADDR_MASK),
6045 current_frame_info.fmask,
84e884e9 6046 "st", "std", -size);
86735b02 6047 }
c819be5b 6048 else
86735b02
DE		 6049 {
6050 /* Subtract %sp in two steps, but make sure there is always a
6051 64 byte register save area, and %sp is properly aligned. */
6052 /* Amount to decrement %sp by, the first time. */
6053 unsigned int size1 = ((size - reg_offset + 64) + 15) & -16;
6054 /* Offset to register save area from %sp. */
6055 unsigned int offset = size1 - (size - reg_offset);
6056
6057 if (size1 <= 4096)
6058 {
e0d80184 6059 fprintf (file, "\tadd\t%s, %d, %s\n",
86735b02
DE		 6060 sp_str, -size1, sp_str);
6061 if (gmask & FRAME_POINTER_MASK)
6062 {
e0d80184 6063 fprintf (file, "\tst\t%s, [%s+%d]\n\tsub\t%s, %d, %s\t%s# set up frame pointer\n",
bf62bbf1
DE		 6064 fp_str, sp_str, offset, sp_str, -size1, fp_str,
6065 ASM_COMMENT_START);
86735b02
DE		 6066 offset += 4;
6067 }
6068 }
6069 else
6070 {
e0d80184 6071 fprintf (file, "\tset\t%d, %s\n\tsub\t%s, %s, %s\n",
86735b02
DE		 6072 size1, t1_str, sp_str, t1_str, sp_str);
6073 if (gmask & FRAME_POINTER_MASK)
6074 {
e0d80184 6075 fprintf (file, "\tst\t%s, [%s+%d]\n\tadd\t%s, %s, %s\t%s# set up frame pointer\n",
bf62bbf1
DE		 6076 fp_str, sp_str, offset, sp_str, t1_str, fp_str,
6077 ASM_COMMENT_START);
86735b02
DE		 6078 offset += 4;
6079 }
6080 }
0021b564 6081 if (dwarf2out_do_frame ())
c53aa195 6082 {
96987e96 6083 char *l = dwarf2out_cfi_label ();
c53aa195
JM		 6084 if (gmask & FRAME_POINTER_MASK)
6085 {
6086 dwarf2out_reg_save (l, FRAME_POINTER_REGNUM,
6087 offset - 4 - size1);
6088 dwarf2out_def_cfa (l, FRAME_POINTER_REGNUM, 0);
6089 }
6090 else
6091 dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, size1);
6092 }
86735b02
DE		 6093 if (gmask & RETURN_ADDR_MASK)
6094 {
e0d80184 6095 fprintf (file, "\tst\t%s, [%s+%d]\n",
86735b02 6096 reg_names[RETURN_ADDR_REGNUM], sp_str, offset);
0021b564 6097 if (dwarf2out_do_frame ())
c53aa195
JM		 6098 /* offset - size1 == reg_offset - size
6099 if reg_offset were updated above like offset. */
6100 dwarf2out_return_save ("", offset - size1);
86735b02
DE		 6101 offset += 4;
6102 }
6103 sparc_flat_save_restore (file, sp_str, offset,
6104 gmask & ~(FRAME_POINTER_MASK | RETURN_ADDR_MASK),
6105 current_frame_info.fmask,
84e884e9 6106 "st", "std", -size1);
e0d80184 6107 fprintf (file, "\tset\t%d, %s\n\tsub\t%s, %s, %s\n",
86735b02 6108 size - size1, t1_str, sp_str, t1_str, sp_str);
0021b564 6109 if (dwarf2out_do_frame ())
c53aa195
JM		 6110 if (! (gmask & FRAME_POINTER_MASK))
6111 dwarf2out_def_cfa ("", STACK_POINTER_REGNUM, size);
86735b02 6112 }
c819be5b 6113 }
c6aa9ce1 6114
bf62bbf1 6115 fprintf (file, "\t%s#PROLOGUE# 1\n", ASM_COMMENT_START);
c819be5b
JW		 6116}
6117\f
6118/* Do any necessary cleanup after a function to restore stack, frame,
6119 and regs. */
6120
6121void
c6aa9ce1 6122sparc_flat_output_function_epilogue (file, size)
c819be5b
JW		 6123 FILE *file;
6124 int size;
6125{
c819be5b
JW		 6126 rtx epilogue_delay = current_function_epilogue_delay_list;
6127 int noepilogue = FALSE;
c819be5b 6128
c6aa9ce1 6129 /* This is only for the human reader. */
bf62bbf1 6130 fprintf (file, "\t%s#EPILOGUE#\n", ASM_COMMENT_START);
c6aa9ce1 6131
c819be5b
JW		 6132 /* The epilogue does not depend on any registers, but the stack
6133 registers, so we assume that if we have 1 pending nop, it can be
6134 ignored, and 2 it must be filled (2 nops occur for integer
6135 multiply and divide). */
6136
6137 size = SPARC_STACK_ALIGN (size);
86735b02 6138 size = (!current_frame_info.initialized
c6aa9ce1 6139 ? sparc_flat_compute_frame_size (size)
c819be5b
JW		 6140 : current_frame_info.total_size);
6141
86735b02 6142 if (size == 0 && epilogue_delay == 0)
c819be5b
JW		 6143 {
6144 rtx insn = get_last_insn ();
6145
6146 /* If the last insn was a BARRIER, we don't have to write any code
6147 because a jump (aka return) was put there. */
6148 if (GET_CODE (insn) == NOTE)
6149 insn = prev_nonnote_insn (insn);
6150 if (insn && GET_CODE (insn) == BARRIER)
6151 noepilogue = TRUE;
6152 }
6153
6154 if (!noepilogue)
6155 {
86735b02
DE		 6156 unsigned int reg_offset = current_frame_info.reg_offset;
6157 unsigned int size1;
6158 char *sp_str = reg_names[STACK_POINTER_REGNUM];
6159 char *fp_str = reg_names[FRAME_POINTER_REGNUM];
3bb5de61 6160 const char *t1_str = "%g1";
86735b02 6161
c819be5b
JW		 6162 /* In the reload sequence, we don't need to fill the load delay
6163 slots for most of the loads, also see if we can fill the final
6164 delay slot if not otherwise filled by the reload sequence. */
6165
86735b02 6166 if (size > 4095)
e0d80184 6167 fprintf (file, "\tset\t%d, %s\n", size, t1_str);
c819be5b
JW		 6168
6169 if (frame_pointer_needed)
6170 {
86735b02 6171 if (size > 4095)
e0d80184 6172 fprintf (file,"\tsub\t%s, %s, %s\t\t%s# sp not trusted here\n",
bf62bbf1 6173 fp_str, t1_str, sp_str, ASM_COMMENT_START);
c819be5b 6174 else
e0d80184 6175 fprintf (file,"\tsub\t%s, %d, %s\t\t%s# sp not trusted here\n",
bf62bbf1 6176 fp_str, size, sp_str, ASM_COMMENT_START);
c819be5b
JW		 6177 }
6178
ddd5a7c1 6179 /* Is the entire register save area offsettable from %sp? */
86735b02
DE		 6180 if (reg_offset < 4096 - 64 * UNITS_PER_WORD)
6181 {
6182 size1 = 0;
6183 }
6184 else
6185 {
6186 /* Restore %sp in two steps, but make sure there is always a
6187 64 byte register save area, and %sp is properly aligned. */
6188 /* Amount to increment %sp by, the first time. */
6189 size1 = ((reg_offset - 64 - 16) + 15) & -16;
6190 /* Offset to register save area from %sp. */
6191 reg_offset = size1 - reg_offset;
6192
e0d80184 6193 fprintf (file, "\tset\t%d, %s\n\tadd\t%s, %s, %s\n",
86735b02
DE		 6194 size1, t1_str, sp_str, t1_str, sp_str);
6195 }
6196
6197 /* We must restore the frame pointer and return address reg first
6198 because they are treated specially by the prologue output code. */
6199 if (current_frame_info.gmask & FRAME_POINTER_MASK)
6200 {
e0d80184 6201 fprintf (file, "\tld\t[%s+%d], %s\n",
86735b02
DE		 6202 sp_str, reg_offset, fp_str);
6203 reg_offset += 4;
6204 }
6205 if (current_frame_info.gmask & RETURN_ADDR_MASK)
6206 {
e0d80184 6207 fprintf (file, "\tld\t[%s+%d], %s\n",
86735b02
DE		 6208 sp_str, reg_offset, reg_names[RETURN_ADDR_REGNUM]);
6209 reg_offset += 4;
6210 }
6211
6212 /* Restore any remaining saved registers. */
6213 sparc_flat_save_restore (file, sp_str, reg_offset,
6214 current_frame_info.gmask & ~(FRAME_POINTER_MASK | RETURN_ADDR_MASK),
6215 current_frame_info.fmask,
c53aa195 6216 "ld", "ldd", 0);
86735b02
DE		 6217
6218 /* If we had to increment %sp in two steps, record it so the second
6219 restoration in the epilogue finishes up. */
6220 if (size1 > 0)
6221 {
6222 size -= size1;
6223 if (size > 4095)
e0d80184 6224 fprintf (file, "\tset\t%d, %s\n",
86735b02
DE		 6225 size, t1_str);
6226 }
c819be5b 6227
c819be5b 6228 if (current_function_returns_struct)
e0d80184 6229 fprintf (file, "\tjmp\t%%o7+12\n");
c819be5b
JW		 6230 else
6231 fprintf (file, "\tretl\n");
6232
6233 /* If the only register saved is the return address, we need a
6234 nop, unless we have an instruction to put into it. Otherwise
6235 we don't since reloading multiple registers doesn't reference
6236 the register being loaded. */
6237
6238 if (epilogue_delay)
6239 {
86735b02 6240 if (size)
c819be5b
JW		 6241 abort ();
6242 final_scan_insn (XEXP (epilogue_delay, 0), file, 1, -2, 1);
6243 }
6244
86735b02 6245 else if (size > 4095)
e0d80184 6246 fprintf (file, "\tadd\t%s, %s, %s\n", sp_str, t1_str, sp_str);
c819be5b 6247
86735b02 6248 else if (size > 0)
e0d80184 6249 fprintf (file, "\tadd\t%s, %d, %s\n", sp_str, size, sp_str);
c819be5b
JW		 6250
6251 else
6252 fprintf (file, "\tnop\n");
6253 }
6254
6255 /* Reset state info for each function. */
6256 current_frame_info = zero_frame_info;
e0d80184
DM		 6257
6258 sparc_output_deferred_case_vectors ();
c819be5b
JW		 6259}
6260\f
6261/* Define the number of delay slots needed for the function epilogue.
6262
6263 On the sparc, we need a slot if either no stack has been allocated,
6264 or the only register saved is the return register. */
6265
6266int
c6aa9ce1 6267sparc_flat_epilogue_delay_slots ()
c819be5b
JW		 6268{
6269 if (!current_frame_info.initialized)
c6aa9ce1 6270 (void) sparc_flat_compute_frame_size (get_frame_size ());
c819be5b
JW		 6271
6272 if (current_frame_info.total_size == 0)
6273 return 1;
6274
c819be5b
JW		 6275 return 0;
6276}
6277
6278/* Return true is TRIAL is a valid insn for the epilogue delay slot.
6279 Any single length instruction which doesn't reference the stack or frame
6280 pointer is OK. */
6281
6282int
c6aa9ce1 6283sparc_flat_eligible_for_epilogue_delay (trial, slot)
c819be5b 6284 rtx trial;
db3d4438 6285 int slot ATTRIBUTE_UNUSED;
c819be5b 6286{
c4ce6853
DE		 6287 rtx pat = PATTERN (trial);
6288
6289 if (get_attr_length (trial) != 1)
6290 return 0;
6291
6292 /* If %g0 is live, there are lots of things we can't handle.
6293 Rather than trying to find them all now, let's punt and only
6294 optimize things as necessary. */
6295 if (TARGET_LIVE_G0)
6296 return 0;
6297
6298 if (! reg_mentioned_p (stack_pointer_rtx, pat)
6299 && ! reg_mentioned_p (frame_pointer_rtx, pat))
c819be5b 6300 return 1;
c4ce6853 6301
c819be5b
JW		 6302 return 0;
6303}
dbb54862
JW		 6304\f
6305/* Adjust the cost of a scheduling dependency. Return the new cost of
6306 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
6307
8947065c 6308static int
dbb54862
JW		 6309supersparc_adjust_cost (insn, link, dep_insn, cost)
6310 rtx insn;
6311 rtx link;
6312 rtx dep_insn;
6313 int cost;
6314{
6315 enum attr_type insn_type;
6316
6317 if (! recog_memoized (insn))
6318 return 0;
6319
6320 insn_type = get_attr_type (insn);
6321
6322 if (REG_NOTE_KIND (link) == 0)
6323 {
6324 /* Data dependency; DEP_INSN writes a register that INSN reads some
6325 cycles later. */
6326
6327 /* if a load, then the dependence must be on the memory address;
3bc8b61e
DM		 6328 add an extra "cycle". Note that the cost could be two cycles
6329 if the reg was written late in an instruction group; we ca not tell
dbb54862
JW		 6330 here. */
6331 if (insn_type == TYPE_LOAD || insn_type == TYPE_FPLOAD)
6332 return cost + 3;
6333
6334 /* Get the delay only if the address of the store is the dependence. */
6335 if (insn_type == TYPE_STORE || insn_type == TYPE_FPSTORE)
6336 {
6337 rtx pat = PATTERN(insn);
6338 rtx dep_pat = PATTERN (dep_insn);
6339
6340 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
3bc8b61e 6341 return cost; /* This should not happen! */
dbb54862
JW		 6342
6343 /* The dependency between the two instructions was on the data that
6344 is being stored. Assume that this implies that the address of the
6345 store is not dependent. */
6346 if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat)))
6347 return cost;
6348
6349 return cost + 3; /* An approximation. */
6350 }
6351
6352 /* A shift instruction cannot receive its data from an instruction
6353 in the same cycle; add a one cycle penalty. */
6354 if (insn_type == TYPE_SHIFT)
6355 return cost + 3; /* Split before cascade into shift. */
6356 }
6357 else
6358 {
6359 /* Anti- or output- dependency; DEP_INSN reads/writes a register that
6360 INSN writes some cycles later. */
6361
6362 /* These are only significant for the fpu unit; writing a fp reg before
6363 the fpu has finished with it stalls the processor. */
6364
6365 /* Reusing an integer register causes no problems. */
6366 if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT)
6367 return 0;
6368 }
6369
6370 return cost;
6371}
bfd6bc60 6372
8947065c
RH		 6373static int
6374hypersparc_adjust_cost (insn, link, dep_insn, cost)
6375 rtx insn;
6376 rtx link;
6377 rtx dep_insn;
6378 int cost;
6379{
6380 enum attr_type insn_type, dep_type;
6381 rtx pat = PATTERN(insn);
6382 rtx dep_pat = PATTERN (dep_insn);
6383
6384 if (recog_memoized (insn) < 0 || recog_memoized (dep_insn) < 0)
6385 return cost;
6386
6387 insn_type = get_attr_type (insn);
6388 dep_type = get_attr_type (dep_insn);
6389
6390 switch (REG_NOTE_KIND (link))
6391 {
6392 case 0:
6393 /* Data dependency; DEP_INSN writes a register that INSN reads some
6394 cycles later. */
6395
6396 switch (insn_type)
6397 {
6398 case TYPE_STORE:
6399 case TYPE_FPSTORE:
6400 /* Get the delay iff the address of the store is the dependence. */
6401 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
6402 return cost;
6403
6404 if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat)))
6405 return cost;
6406 return cost + 3;
6407
6408 case TYPE_LOAD:
6409 case TYPE_SLOAD:
6410 case TYPE_FPLOAD:
6411 /* If a load, then the dependence must be on the memory address. If
6412 the addresses aren't equal, then it might be a false dependency */
6413 if (dep_type == TYPE_STORE || dep_type == TYPE_FPSTORE)
6414 {
6415 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET
6416 || GET_CODE (SET_DEST (dep_pat)) != MEM
6417 || GET_CODE (SET_SRC (pat)) != MEM
6418 || ! rtx_equal_p (XEXP (SET_DEST (dep_pat), 0),
6419 XEXP (SET_SRC (pat), 0)))
6420 return cost + 2;
6421
6422 return cost + 8;
6423 }
6424 break;
6425
6426 case TYPE_BRANCH:
6427 /* Compare to branch latency is 0. There is no benefit from
6428 separating compare and branch. */
6429 if (dep_type == TYPE_COMPARE)
6430 return 0;
6431 /* Floating point compare to branch latency is less than
6432 compare to conditional move. */
6433 if (dep_type == TYPE_FPCMP)
6434 return cost - 1;
6435 break;
3bb5de61
KG		 6436 default:
6437 break;
8947065c
RH		 6438 }
6439 break;
6440
6441 case REG_DEP_ANTI:
6442 /* Anti-dependencies only penalize the fpu unit. */
6443 if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT)
6444 return 0;
6445 break;
6446
6447 default:
6448 break;
6449 }
6450
6451 return cost;
6452}
6453
6454static int
6455ultrasparc_adjust_cost (insn, link, dep_insn, cost)
6456 rtx insn;
6457 rtx link;
6458 rtx dep_insn;
6459 int cost;
6460{
6461 enum attr_type insn_type, dep_type;
6462 rtx pat = PATTERN(insn);
6463 rtx dep_pat = PATTERN (dep_insn);
6464
6465 if (recog_memoized (insn) < 0 || recog_memoized (dep_insn) < 0)
6466 return cost;
6467
6468 insn_type = get_attr_type (insn);
6469 dep_type = get_attr_type (dep_insn);
6470
6471 /* Nothing issues in parallel with integer multiplies, so
6472 mark as zero cost since the scheduler can not do anything
6473 about it. */
6474 if (insn_type == TYPE_IMUL)
6475 return 0;
6476
6477#define SLOW_FP(dep_type) \
6478(dep_type == TYPE_FPSQRT || dep_type == TYPE_FPDIVS || dep_type == TYPE_FPDIVD)
6479
6480 switch (REG_NOTE_KIND (link))
6481 {
6482 case 0:
6483 /* Data dependency; DEP_INSN writes a register that INSN reads some
6484 cycles later. */
6485
6486 if (dep_type == TYPE_CMOVE)
6487 {
6488 /* Instructions that read the result of conditional moves cannot
6489 be in the same group or the following group. */
6490 return cost + 1;
6491 }
6492
6493 switch (insn_type)
6494 {
6495 /* UltraSPARC can dual issue a store and an instruction setting
6496 the value stored, except for divide and square root. */
6497 case TYPE_FPSTORE:
6498 if (! SLOW_FP (dep_type))
6499 return 0;
6500 return cost;
6501
6502 case TYPE_STORE:
6503 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
6504 return cost;
6505
6506 if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat)))
6507 /* The dependency between the two instructions is on the data
6508 that is being stored. Assume that the address of the store
6509 is not also dependent. */
6510 return 0;
6511 return cost;
6512
6513 case TYPE_LOAD:
6514 case TYPE_SLOAD:
6515 case TYPE_FPLOAD:
6516 /* A load does not return data until at least 11 cycles after
6517 a store to the same location. 3 cycles are accounted for
6518 in the load latency; add the other 8 here. */
6519 if (dep_type == TYPE_STORE || dep_type == TYPE_FPSTORE)
6520 {
6521 /* If the addresses are not equal this may be a false
6522 dependency because pointer aliasing could not be
6523 determined. Add only 2 cycles in that case. 2 is
6524 an arbitrary compromise between 8, which would cause
6525 the scheduler to generate worse code elsewhere to
6526 compensate for a dependency which might not really
6527 exist, and 0. */
6528 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET
6529 || GET_CODE (SET_SRC (pat)) != MEM
6530 || GET_CODE (SET_DEST (dep_pat)) != MEM
6531 || ! rtx_equal_p (XEXP (SET_SRC (pat), 0),
6532 XEXP (SET_DEST (dep_pat), 0)))
6533 return cost + 2;
6534
6535 return cost + 8;
6536 }
6537 return cost;
6538
6539 case TYPE_BRANCH:
6540 /* Compare to branch latency is 0. There is no benefit from
6541 separating compare and branch. */
6542 if (dep_type == TYPE_COMPARE)
6543 return 0;
6544 /* Floating point compare to branch latency is less than
6545 compare to conditional move. */
6546 if (dep_type == TYPE_FPCMP)
6547 return cost - 1;
6548 return cost;
6549
6550 case TYPE_FPCMOVE:
6551 /* FMOVR class instructions can not issue in the same cycle
6552 or the cycle after an instruction which writes any
6553 integer register. Model this as cost 2 for dependent
6554 instructions. */
6555 if ((dep_type == TYPE_IALU || dep_type == TYPE_UNARY
6556 || dep_type == TYPE_BINARY)
6557 && cost < 2)
6558 return 2;
6559 /* Otherwise check as for integer conditional moves. */
6560
6561 case TYPE_CMOVE:
6562 /* Conditional moves involving integer registers wait until
6563 3 cycles after loads return data. The interlock applies
6564 to all loads, not just dependent loads, but that is hard
6565 to model. */
6566 if (dep_type == TYPE_LOAD || dep_type == TYPE_SLOAD)
6567 return cost + 3;
6568 return cost;
6569
6570 default:
6571 break;
6572 }
6573 break;
6574
6575 case REG_DEP_ANTI:
6576 /* Divide and square root lock destination registers for full latency. */
6577 if (! SLOW_FP (dep_type))
6578 return 0;
6579 break;
6580
6581 case REG_DEP_OUTPUT:
6582 /* IEU and FPU instruction that have the same destination
6583 register cannot be grouped together. */
6584 return cost + 1;
6585
6586 default:
6587 break;
6588 }
6589
6590 /* Other costs not accounted for:
6591 - Single precision floating point loads lock the other half of
6592 the even/odd register pair.
6593 - Several hazards associated with ldd/std are ignored because these
6594 instructions are rarely generated for V9.
6595 - The floating point pipeline can not have both a single and double
6596 precision operation active at the same time. Format conversions
6597 and graphics instructions are given honorary double precision status.
6598 - call and jmpl are always the first instruction in a group. */
6599
6600 return cost;
6601
6602#undef SLOW_FP
6603}
6604
6605int
6606sparc_adjust_cost(insn, link, dep, cost)
6607 rtx insn;
6608 rtx link;
6609 rtx dep;
6610 int cost;
6611{
6612 switch (sparc_cpu)
6613 {
6614 case PROCESSOR_SUPERSPARC:
6615 cost = supersparc_adjust_cost (insn, link, dep, cost);
6616 break;
6617 case PROCESSOR_HYPERSPARC:
6618 case PROCESSOR_SPARCLITE86X:
6619 cost = hypersparc_adjust_cost (insn, link, dep, cost);
6620 break;
6621 case PROCESSOR_ULTRASPARC:
6622 cost = ultrasparc_adjust_cost (insn, link, dep, cost);
6623 break;
6624 default:
6625 break;
6626 }
6627 return cost;
6628}
6629
3bc8b61e
DM		 6630/* This describes the state of the UltraSPARC pipeline during
6631 instruction scheduling. */
6632
b96a5ea5
KG		 6633#define TMASK(__x) ((unsigned)1 << ((int)(__x)))
6634#define UMASK(__x) ((unsigned)1 << ((int)(__x)))
3bc8b61e
DM		 6635
6636enum ultra_code { NONE=0, /* no insn at all */
6637 IEU0, /* shifts and conditional moves */
6638 IEU1, /* condition code setting insns, calls+jumps */
6639 IEUN, /* all other single cycle ieu insns */
6640 LSU, /* loads and stores */
6641 CTI, /* branches */
6642 FPM, /* FPU pipeline 1, multiplies and divides */
6643 FPA, /* FPU pipeline 2, all other operations */
6644 SINGLE, /* single issue instructions */
6645 NUM_ULTRA_CODES };
6646
b1474bb7
KG		 6647static enum ultra_code ultra_code_from_mask PROTO ((int));
6648static void ultra_schedule_insn PROTO ((rtx *, rtx *, int, enum ultra_code));
6649
3bb5de61 6650static const char *ultra_code_names[NUM_ULTRA_CODES] = {
3bc8b61e
DM		 6651 "NONE", "IEU0", "IEU1", "IEUN", "LSU", "CTI",
6652 "FPM", "FPA", "SINGLE" };
6653
6654struct ultrasparc_pipeline_state {
6655 /* The insns in this group. */
6656 rtx group[4];
6657
6658 /* The code for each insn. */
6659 enum ultra_code codes[4];
6660
6661 /* Which insns in this group have been committed by the
6662 scheduler. This is how we determine how many more
6663 can issue this cycle. */
6664 char commit[4];
6665
6666 /* How many insns in this group. */
6667 char group_size;
6668
6669 /* Mask of free slots still in this group. */
6670 char free_slot_mask;
6671
6672 /* The slotter uses the following to determine what other
6673 insn types can still make their way into this group. */
6674 char contents [NUM_ULTRA_CODES];
6675 char num_ieu_insns;
6676};
6677
6678#define ULTRA_NUM_HIST 8
6679static struct ultrasparc_pipeline_state ultra_pipe_hist[ULTRA_NUM_HIST];
6680static int ultra_cur_hist;
6681static int ultra_cycles_elapsed;
6682
6683#define ultra_pipe (ultra_pipe_hist[ultra_cur_hist])
6684
6685/* Given TYPE_MASK compute the ultra_code it has. */
6686static enum ultra_code
6687ultra_code_from_mask (type_mask)
6688 int type_mask;
6689{
3bc8b61e
DM		 6690 if (type_mask & (TMASK (TYPE_SHIFT) | TMASK (TYPE_CMOVE)))
6691 return IEU0;
6692 else if (type_mask & (TMASK (TYPE_COMPARE) |
6693 TMASK (TYPE_CALL) |
6694 TMASK (TYPE_UNCOND_BRANCH)))
6695 return IEU1;
6696 else if (type_mask & (TMASK (TYPE_IALU) | TMASK (TYPE_BINARY) |
6697 TMASK (TYPE_MOVE) | TMASK (TYPE_UNARY)))
6698 return IEUN;
6699 else if (type_mask & (TMASK (TYPE_LOAD) | TMASK (TYPE_SLOAD) |
6700 TMASK (TYPE_STORE) | TMASK (TYPE_FPLOAD) |
6701 TMASK (TYPE_FPSTORE)))
6702 return LSU;
6703 else if (type_mask & (TMASK (TYPE_FPMUL) | TMASK (TYPE_FPDIVS) |
6704 TMASK (TYPE_FPDIVD) | TMASK (TYPE_FPSQRT)))
6705 return FPM;
6706 else if (type_mask & (TMASK (TYPE_FPMOVE) | TMASK (TYPE_FPCMOVE) |
6707 TMASK (TYPE_FP) | TMASK (TYPE_FPCMP)))
6708 return FPA;
6709 else if (type_mask & TMASK (TYPE_BRANCH))
6710 return CTI;
6711
6712 return SINGLE;
6713}
6714
6715/* Check INSN (a conditional move) and make sure that it's
6716 results are available at this cycle. Return 1 if the
6717 results are in fact ready. */
6718static int
6719ultra_cmove_results_ready_p (insn)
6720 rtx insn;
6721{
6722 struct ultrasparc_pipeline_state *up;
6723 int entry, slot;
6724
6725 /* If this got dispatched in the previous
6726 group, the results are not ready. */
ddf80874 6727 entry = (ultra_cur_hist - 1) % (ULTRA_NUM_HIST - 1);
3bc8b61e
DM		 6728 up = &ultra_pipe_hist[entry];
6729 slot = 4;
6730 while (--slot >= 0)
6731 if (up->group[slot] == insn)
c305b1a7 6732 return 0;
3bc8b61e 6733
c305b1a7 6734 return 1;
3bc8b61e
DM		 6735}
6736
6737/* Walk backwards in pipeline history looking for FPU
6738 operations which use a mode different than FPMODE and
6739 will create a stall if an insn using FPMODE were to be
6740 dispatched this cycle. */
6741static int
6742ultra_fpmode_conflict_exists (fpmode)
6743 enum machine_mode fpmode;
6744{
6745 int hist_ent;
6746 int hist_lim;
6747
ddf80874 6748 hist_ent = (ultra_cur_hist - 1) % (ULTRA_NUM_HIST - 1);
3bc8b61e
DM		 6749 if (ultra_cycles_elapsed < 4)
6750 hist_lim = ultra_cycles_elapsed;
6751 else
6752 hist_lim = 4;
6753 while (hist_lim > 0)
6754 {
6755 struct ultrasparc_pipeline_state *up = &ultra_pipe_hist[hist_ent];
6756 int slot = 4;
6757
6758 while (--slot >= 0)
6759 {
6760 rtx insn = up->group[slot];
6761 enum machine_mode this_mode;
3bc8b61e
DM		 6762 rtx pat;
6763
6764 if (! insn
6765 || GET_CODE (insn) != INSN
6766 || (pat = PATTERN (insn)) == 0
6767 || GET_CODE (pat) != SET)
6768 continue;
6769
6770 this_mode = GET_MODE (SET_DEST (pat));
6771 if ((this_mode != SFmode
6772 && this_mode != DFmode)
6773 || this_mode == fpmode)
6774 continue;
6775
6776 /* If it is not FMOV, FABS, FNEG, FDIV, or FSQRT then
ddf80874
DM		 6777 we will get a stall. Loads and stores are independant
6778 of these rules. */
3bc8b61e
DM		 6779 if (GET_CODE (SET_SRC (pat)) != ABS
6780 && GET_CODE (SET_SRC (pat)) != NEG
6781 && ((TMASK (get_attr_type (insn)) &
6782 (TMASK (TYPE_FPDIVS) | TMASK (TYPE_FPDIVD) |
ddf80874
DM		 6783 TMASK (TYPE_FPMOVE) | TMASK (TYPE_FPSQRT) |
6784 TMASK (TYPE_LOAD) | TMASK (TYPE_STORE))) == 0))
3bc8b61e
DM		 6785 return 1;
6786 }
6787 hist_lim--;
ddf80874 6788 hist_ent = (hist_ent - 1) % (ULTRA_NUM_HIST - 1);
3bc8b61e
DM		 6789 }
6790
6791 /* No conflicts, safe to dispatch. */
6792 return 0;
6793}
6794
6795/* Find an instruction in LIST which has one of the
6796 type attributes enumerated in TYPE_MASK. START
6797 says where to begin the search.
6798
6799 NOTE: This scheme depends upon the fact that we
6800 have less than 32 distinct type attributes. */
5a5325cb
DM		 6801
6802static int ultra_types_avail;
6803
3bc8b61e
DM		 6804static rtx *
6805ultra_find_type (type_mask, list, start)
6806 int type_mask;
6807 rtx *list;
6808 int start;
6809{
6810 int i;
6811
5a5325cb
DM		 6812 /* Short circuit if no such insn exists in the ready
6813 at the moment. */
6814 if ((type_mask & ultra_types_avail) == 0)
6815 return 0;
6816
3bc8b61e
DM		 6817 for (i = start; i >= 0; i--)
6818 {
6819 rtx insn = list[i];
6820
6821 if (recog_memoized (insn) >= 0
6822 && (TMASK(get_attr_type (insn)) & type_mask))
6823 {
ddf80874 6824 enum machine_mode fpmode = SFmode;
3bc8b61e
DM		 6825 rtx pat = 0;
6826 int slot;
6827 int check_depend = 0;
6828 int check_fpmode_conflict = 0;
6829
6830 if (GET_CODE (insn) == INSN
6831 && (pat = PATTERN(insn)) != 0
6832 && GET_CODE (pat) == SET
6833 && !(type_mask & (TMASK (TYPE_STORE) |
6834 TMASK (TYPE_FPSTORE))))
6835 {
6836 check_depend = 1;
6837 if (GET_MODE (SET_DEST (pat)) == SFmode
6838 || GET_MODE (SET_DEST (pat)) == DFmode)
6839 {
6840 fpmode = GET_MODE (SET_DEST (pat));
6841 check_fpmode_conflict = 1;
6842 }
6843 }
6844
6845 slot = 4;
6846 while(--slot >= 0)
6847 {
6848 rtx slot_insn = ultra_pipe.group[slot];
6849 rtx slot_pat;
6850
6851 /* Already issued, bad dependency, or FPU
6852 mode conflict. */
6853 if (slot_insn != 0
6854 && (slot_pat = PATTERN (slot_insn)) != 0
6855 && ((insn == slot_insn)
6856 || (check_depend == 1
6857 && GET_CODE (slot_insn) == INSN
6858 && GET_CODE (slot_pat) == SET
5a5325cb
DM		 6859 && ((GET_CODE (SET_DEST (slot_pat)) == REG
6860 && GET_CODE (SET_SRC (pat)) == REG
6861 && REGNO (SET_DEST (slot_pat)) ==
6862 REGNO (SET_SRC (pat)))
6863 || (GET_CODE (SET_DEST (slot_pat)) == SUBREG
6864 && GET_CODE (SET_SRC (pat)) == SUBREG
6865 && REGNO (SUBREG_REG (SET_DEST (slot_pat))) ==
6866 REGNO (SUBREG_REG (SET_SRC (pat)))
6867 && SUBREG_WORD (SET_DEST (slot_pat)) ==
ddf80874 6868 SUBREG_WORD (SET_SRC (pat)))))
3bc8b61e
DM		 6869 || (check_fpmode_conflict == 1
6870 && GET_CODE (slot_insn) == INSN
6871 && GET_CODE (slot_pat) == SET
ddf80874
DM		 6872 && (GET_MODE (SET_DEST (slot_pat)) == SFmode
6873 || GET_MODE (SET_DEST (slot_pat)) == DFmode)
6874 && GET_MODE (SET_DEST (slot_pat)) != fpmode)))
3bc8b61e
DM		 6875 goto next;
6876 }
6877
6878 /* Check for peculiar result availability and dispatch
6879 interference situations. */
6880 if (pat != 0
6881 && ultra_cycles_elapsed > 0)
6882 {
6883 rtx link;
6884
6885 for (link = LOG_LINKS (insn); link; link = XEXP (link, 1))
6886 {
6887 rtx link_insn = XEXP (link, 0);
6888 if (GET_CODE (link_insn) == INSN
6889 && recog_memoized (link_insn) >= 0
6890 && (TMASK (get_attr_type (link_insn)) &
6891 (TMASK (TYPE_CMOVE) | TMASK (TYPE_FPCMOVE)))
6892 && ! ultra_cmove_results_ready_p (link_insn))
6893 goto next;
6894 }
6895
6896 if (check_fpmode_conflict
6897 && ultra_fpmode_conflict_exists (fpmode))
6898 goto next;
6899 }
6900
6901 return &list[i];
6902 }
6903 next:
5a5325cb 6904 ;
3bc8b61e
DM		 6905 }
6906 return 0;
6907}
6908
5a5325cb
DM		 6909static void
6910ultra_build_types_avail (ready, n_ready)
6911 rtx *ready;
6912 int n_ready;
6913{
6914 int i = n_ready - 1;
6915
6916 ultra_types_avail = 0;
6917 while(i >= 0)
6918 {
6919 rtx insn = ready[i];
6920
6921 if (recog_memoized (insn) >= 0)
6922 ultra_types_avail |= TMASK (get_attr_type (insn));
6923
6924 i -= 1;
6925 }
6926}
6927
3bc8b61e
DM		 6928/* Place insn pointed to my IP into the pipeline.
6929 Make element THIS of READY be that insn if it
6930 is not already. TYPE indicates the pipeline class
6931 this insn falls into. */
6932static void
6933ultra_schedule_insn (ip, ready, this, type)
6934 rtx *ip;
6935 rtx *ready;
6936 int this;
6937 enum ultra_code type;
6938{
6939 int pipe_slot;
6940 char mask = ultra_pipe.free_slot_mask;
6941
6942 /* Obtain free slot. */
6943 for (pipe_slot = 0; pipe_slot < 4; pipe_slot++)
6944 if ((mask & (1 << pipe_slot)) != 0)
6945 break;
6946 if (pipe_slot == 4)
6947 abort ();
6948
6949 /* In it goes, and it hasn't been committed yet. */
6950 ultra_pipe.group[pipe_slot] = *ip;
6951 ultra_pipe.codes[pipe_slot] = type;
6952 ultra_pipe.contents[type] = 1;
6953 if (UMASK (type) &
6954 (UMASK (IEUN) | UMASK (IEU0) | UMASK (IEU1)))
6955 ultra_pipe.num_ieu_insns += 1;
6956
6957 ultra_pipe.free_slot_mask = (mask & ~(1 << pipe_slot));
6958 ultra_pipe.group_size += 1;
6959 ultra_pipe.commit[pipe_slot] = 0;
6960
6961 /* Update ready list. */
6962 if (ip != &ready[this])
6963 {
6964 rtx temp = *ip;
6965
6966 *ip = ready[this];
6967 ready[this] = temp;
6968 }
6969}
6970
6971/* Advance to the next pipeline group. */
6972static void
6973ultra_flush_pipeline ()
6974{
ddf80874 6975 ultra_cur_hist = (ultra_cur_hist + 1) % (ULTRA_NUM_HIST - 1);
3bc8b61e
DM		 6976 ultra_cycles_elapsed += 1;
6977 bzero ((char *) &ultra_pipe, sizeof ultra_pipe);
6978 ultra_pipe.free_slot_mask = 0xf;
6979}
6980
3bc8b61e
DM		 6981/* Init our data structures for this current block. */
6982void
6983ultrasparc_sched_init (dump, sched_verbose)
ddf80874
DM		 6984 FILE *dump ATTRIBUTE_UNUSED;
6985 int sched_verbose ATTRIBUTE_UNUSED;
3bc8b61e 6986{
b96a5ea5 6987 bzero ((char *) ultra_pipe_hist, sizeof ultra_pipe_hist);
3bc8b61e
DM		 6988 ultra_cur_hist = 0;
6989 ultra_cycles_elapsed = 0;
ddf80874 6990 ultra_pipe.free_slot_mask = 0xf;
3bc8b61e
DM		 6991}
6992
6993/* INSN has been scheduled, update pipeline commit state
6994 and return how many instructions are still to be
6995 scheduled in this group. */
bfd6bc60 6996int
3bc8b61e
DM		 6997ultrasparc_variable_issue (insn)
6998 rtx insn;
6999{
7000 struct ultrasparc_pipeline_state *up = &ultra_pipe;
7001 int i, left_to_fire;
7002
7003 left_to_fire = 0;
7004 for (i = 0; i < 4; i++)
7005 {
7006 if (up->group[i] == 0)
7007 continue;
7008
7009 if (up->group[i] == insn)
7010 {
7011 up->commit[i] = 1;
7012 }
7013 else if (! up->commit[i])
7014 left_to_fire++;
7015 }
7016
7017 return left_to_fire;
7018}
7019
7020/* In actual_hazard_this_instance, we may have yanked some
7021 instructions from the ready list due to conflict cost
7022 adjustments. If so, and such an insn was in our pipeline
7023 group, remove it and update state. */
7024static void
7025ultra_rescan_pipeline_state (ready, n_ready)
7026 rtx *ready;
7027 int n_ready;
7028{
7029 struct ultrasparc_pipeline_state *up = &ultra_pipe;
7030 int i;
7031
7032 for (i = 0; i < 4; i++)
7033 {
7034 rtx insn = up->group[i];
3bc8b61e
DM		 7035 int j;
7036
7037 if (! insn)
7038 continue;
7039
7040 /* If it has been committed, then it was removed from
7041 the ready list because it was actually scheduled,
7042 and that is not the case we are searching for here. */
7043 if (up->commit[i] != 0)
7044 continue;
7045
7046 for (j = n_ready - 1; j >= 0; j--)
7047 if (ready[j] == insn)
7048 break;
7049
7050 /* If we didn't find it, toss it. */
7051 if (j < 0)
7052 {
7053 enum ultra_code ucode = up->codes[i];
7054
7055 up->group[i] = 0;
7056 up->codes[i] = NONE;
7057 up->contents[ucode] = 0;
7058 if (UMASK (ucode) &
7059 (UMASK (IEUN) | UMASK (IEU0) | UMASK (IEU1)))
7060 up->num_ieu_insns -= 1;
7061
7062 up->free_slot_mask |= (1 << i);
7063 up->group_size -= 1;
7064 up->commit[i] = 0;
7065 }
7066 }
7067}
7068
7069void
7070ultrasparc_sched_reorder (dump, sched_verbose, ready, n_ready)
7071 FILE *dump;
7072 int sched_verbose;
7073 rtx *ready;
7074 int n_ready;
7075{
7076 struct ultrasparc_pipeline_state *up = &ultra_pipe;
7077 int i, this_insn;
7078
3bc8b61e
DM		 7079 if (sched_verbose)
7080 {
7081 int n;
7082
7083 fprintf (dump, "\n;;\tUltraSPARC Looking at [");
7084 for (n = n_ready - 1; n >= 0; n--)
7085 {
7086 rtx insn = ready[n];
7087 enum ultra_code ucode;
7088
7089 if (recog_memoized (insn) < 0)
7090 continue;
7091 ucode = ultra_code_from_mask (TMASK (get_attr_type (insn)));
7092 if (n != 0)
7093 fprintf (dump, "%s(%d) ",
7094 ultra_code_names[ucode],
7095 INSN_UID (insn));
7096 else
7097 fprintf (dump, "%s(%d)",
7098 ultra_code_names[ucode],
7099 INSN_UID (insn));
7100 }
7101 fprintf (dump, "]\n");
7102 }
7103
7104 this_insn = n_ready - 1;
7105
7106 /* Skip over junk we don't understand. */
7107 while ((this_insn >= 0)
7108 && recog_memoized (ready[this_insn]) < 0)
7109 this_insn--;
7110
5a5325cb
DM		 7111 ultra_build_types_avail (ready, this_insn + 1);
7112
3bc8b61e
DM		 7113 while (this_insn >= 0) {
7114 int old_group_size = up->group_size;
7115
7116 if (up->group_size != 0)
7117 {
7118 int num_committed;
7119
7120 num_committed = (up->commit[0] + up->commit[1] +
7121 up->commit[2] + up->commit[3]);
7122 /* If nothing has been commited from our group, or all of
7123 them have. Clear out the (current cycle's) pipeline
7124 state and start afresh. */
7125 if (num_committed == 0
7126 || num_committed == up->group_size)
7127 {
ddf80874
DM		 7128 ultra_flush_pipeline ();
7129 up = &ultra_pipe;
3bc8b61e
DM		 7130 old_group_size = 0;
7131 }
7132 else
7133 {
7134 /* OK, some ready list insns got requeued and thus removed
7135 from the ready list. Account for this fact. */
7136 ultra_rescan_pipeline_state (ready, n_ready);
7137
7138 /* Something "changed", make this look like a newly
7139 formed group so the code at the end of the loop
7140 knows that progress was in fact made. */
7141 if (up->group_size != old_group_size)
ddf80874 7142 old_group_size = 0;
3bc8b61e
DM		 7143 }
7144 }
7145
7146 if (up->group_size == 0)
7147 {
7148 /* If the pipeline is (still) empty and we have any single
7149 group insns, get them out now as this is a good time. */
7150 rtx *ip = ultra_find_type ((TMASK (TYPE_RETURN) | TMASK (TYPE_ADDRESS) |
7151 TMASK (TYPE_IMUL) | TMASK (TYPE_CMOVE) |
7152 TMASK (TYPE_MULTI) | TMASK (TYPE_MISC)),
7153 ready, this_insn);
7154 if (ip)
7155 {
7156 ultra_schedule_insn (ip, ready, this_insn, SINGLE);
7157 break;
7158 }
7159
7160 /* If we are not in the process of emptying out the pipe, try to
7161 obtain an instruction which must be the first in it's group. */
7162 ip = ultra_find_type ((TMASK (TYPE_CALL) |
7163 TMASK (TYPE_CALL_NO_DELAY_SLOT) |
7164 TMASK (TYPE_UNCOND_BRANCH)),
7165 ready, this_insn);
7166 if (ip)
7167 {
7168 ultra_schedule_insn (ip, ready, this_insn, IEU1);
7169 this_insn--;
7170 }
7171 else if ((ip = ultra_find_type ((TMASK (TYPE_FPDIVS) |
7172 TMASK (TYPE_FPDIVD) |
7173 TMASK (TYPE_FPSQRT)),
7174 ready, this_insn)) != 0)
7175 {
7176 ultra_schedule_insn (ip, ready, this_insn, FPM);
7177 this_insn--;
7178 }
7179 }
7180
7181 /* Try to fill the integer pipeline. First, look for an IEU0 specific
7182 operation. We can't do more IEU operations if the first 3 slots are
7183 all full or we have dispatched two IEU insns already. */
7184 if ((up->free_slot_mask & 0x7) != 0
7185 && up->num_ieu_insns < 2
7186 && up->contents[IEU0] == 0
7187 && up->contents[IEUN] == 0)
7188 {
7189 rtx *ip = ultra_find_type (TMASK(TYPE_SHIFT), ready, this_insn);
7190 if (ip)
7191 {
7192 ultra_schedule_insn (ip, ready, this_insn, IEU0);
7193 this_insn--;
7194 }
7195 }
7196
7197 /* If we can, try to find an IEU1 specific or an unnamed
7198 IEU instruction. */
7199 if ((up->free_slot_mask & 0x7) != 0
7200 && up->num_ieu_insns < 2)
7201 {
7202 rtx *ip = ultra_find_type ((TMASK (TYPE_IALU) | TMASK (TYPE_BINARY) |
7203 TMASK (TYPE_MOVE) | TMASK (TYPE_UNARY) |
7204 (up->contents[IEU1] == 0 ? TMASK (TYPE_COMPARE) : 0)),
7205 ready, this_insn);
7206 if (ip)
7207 {
7208 rtx insn = *ip;
7209
7210 ultra_schedule_insn (ip, ready, this_insn,
7211 (!up->contents[IEU1]
7212 && get_attr_type (insn) == TYPE_COMPARE)
7213 ? IEU1 : IEUN);
7214 this_insn--;
7215 }
7216 }
7217
7218 /* If only one IEU insn has been found, try to find another unnamed
7219 IEU operation or an IEU1 specific one. */
7220 if ((up->free_slot_mask & 0x7) != 0
7221 && up->num_ieu_insns < 2)
7222 {
7223 rtx *ip;
7224 int tmask = (TMASK (TYPE_IALU) | TMASK (TYPE_BINARY) |
7225 TMASK (TYPE_MOVE) | TMASK (TYPE_UNARY));
7226
7227 if (!up->contents[IEU1])
7228 tmask |= TMASK (TYPE_COMPARE);
7229 ip = ultra_find_type (tmask, ready, this_insn);
7230 if (ip)
7231 {
7232 rtx insn = *ip;
7233
7234 ultra_schedule_insn (ip, ready, this_insn,
7235 (!up->contents[IEU1]
7236 && get_attr_type (insn) == TYPE_COMPARE)
7237 ? IEU1 : IEUN);
7238 this_insn--;
7239 }
7240 }
7241
7242 /* Try for a load or store, but such an insn can only be issued
7243 if it is within' one of the first 3 slots. */
7244 if ((up->free_slot_mask & 0x7) != 0
7245 && up->contents[LSU] == 0)
7246 {
7247 rtx *ip = ultra_find_type ((TMASK (TYPE_LOAD) | TMASK (TYPE_SLOAD) |
7248 TMASK (TYPE_STORE) | TMASK (TYPE_FPLOAD) |
7249 TMASK (TYPE_FPSTORE)), ready, this_insn);
7250 if (ip)
7251 {
7252 ultra_schedule_insn (ip, ready, this_insn, LSU);
7253 this_insn--;
7254 }
7255 }
7256
7257 /* Now find FPU operations, first FPM class. But not divisions or
7258 square-roots because those will break the group up. Unlike all
7259 the previous types, these can go in any slot. */
7260 if (up->free_slot_mask != 0
7261 && up->contents[FPM] == 0)
7262 {
7263 rtx *ip = ultra_find_type (TMASK (TYPE_FPMUL), ready, this_insn);
7264 if (ip)
7265 {
7266 ultra_schedule_insn (ip, ready, this_insn, FPM);
7267 this_insn--;
7268 }
7269 }
7270
7271 /* Continue on with FPA class if we have not filled the group already. */
7272 if (up->free_slot_mask != 0
7273 && up->contents[FPA] == 0)
7274 {
7275 rtx *ip = ultra_find_type ((TMASK (TYPE_FPMOVE) | TMASK (TYPE_FPCMOVE) |
7276 TMASK (TYPE_FP) | TMASK (TYPE_FPCMP)),
7277 ready, this_insn);
7278 if (ip)
7279 {
7280 ultra_schedule_insn (ip, ready, this_insn, FPA);
7281 this_insn--;
7282 }
7283 }
7284
7285 /* Finally, maybe stick a branch in here. */
7286 if (up->free_slot_mask != 0
7287 && up->contents[CTI] == 0)
7288 {
7289 rtx *ip = ultra_find_type (TMASK (TYPE_BRANCH), ready, this_insn);
7290
7291 /* Try to slip in a branch only if it is one of the
7292 next 2 in the ready list. */
7293 if (ip && ((&ready[this_insn] - ip) < 2))
7294 {
7295 ultra_schedule_insn (ip, ready, this_insn, CTI);
7296 this_insn--;
7297 }
7298 }
7299
7300 up->group_size = 0;
7301 for (i = 0; i < 4; i++)
7302 if ((up->free_slot_mask & (1 << i)) == 0)
7303 up->group_size++;
7304
7305 /* See if we made any progress... */
7306 if (old_group_size != up->group_size)
7307 break;
7308
7309 /* Clean out the (current cycle's) pipeline state
ddf80874
DM		 7310 and try once more. If we placed no instructions
7311 into the pipeline at all, it means a real hard
7312 conflict exists with some earlier issued instruction
7313 so we must advance to the next cycle to clear it up. */
7314 if (up->group_size == 0)
7315 {
7316 ultra_flush_pipeline ();
7317 up = &ultra_pipe;
7318 }
7319 else
7320 {
7321 bzero ((char *) &ultra_pipe, sizeof ultra_pipe);
7322 ultra_pipe.free_slot_mask = 0xf;
7323 }
3bc8b61e
DM		 7324 }
7325
7326 if (sched_verbose)
7327 {
7328 int n, gsize;
7329
7330 fprintf (dump, ";;\tUltraSPARC Launched [");
7331 gsize = up->group_size;
7332 for (n = 0; n < 4; n++)
7333 {
7334 rtx insn = up->group[n];
7335
7336 if (! insn)
7337 continue;
7338
7339 gsize -= 1;
7340 if (gsize != 0)
7341 fprintf (dump, "%s(%d) ",
7342 ultra_code_names[up->codes[n]],
7343 INSN_UID (insn));
7344 else
7345 fprintf (dump, "%s(%d)",
7346 ultra_code_names[up->codes[n]],
7347 INSN_UID (insn));
7348 }
7349 fprintf (dump, "]\n");
7350 }
7351}
7352
bfd6bc60
JC		 7353int
7354sparc_issue_rate ()
7355{
7356 switch (sparc_cpu)
7357 {
7358 default:
7359 return 1;
bfd6bc60 7360 case PROCESSOR_V9:
284d86e9 7361 /* Assume V9 processors are capable of at least dual-issue. */
bfd6bc60
JC		 7362 return 2;
7363 case PROCESSOR_SUPERSPARC:
7364 return 3;
393049a9
RH		 7365 case PROCESSOR_HYPERSPARC:
7366 case PROCESSOR_SPARCLITE86X:
7367 return 2;
bfd6bc60
JC		 7368 case PROCESSOR_ULTRASPARC:
7369 return 4;
7370 }
7371}
284d86e9
JC		 7372
7373static int
7374set_extends(x, insn)
7375 rtx x, insn;
7376{
7377 register rtx pat = PATTERN (insn);
7378
7379 switch (GET_CODE (SET_SRC (pat)))
7380 {
7381 /* Load and some shift instructions zero extend. */
7382 case MEM:
7383 case ZERO_EXTEND:
7384 /* sethi clears the high bits */
7385 case HIGH:
7386 /* LO_SUM is used with sethi. sethi cleared the high
7387 bits and the values used with lo_sum are positive */
7388 case LO_SUM:
284d86e9
JC		 7389 /* Store flag stores 0 or 1 */
7390 case LT: case LTU:
7391 case GT: case GTU:
7392 case LE: case LEU:
7393 case GE: case GEU:
7394 case EQ:
7395 case NE:
7396 return 1;
7397 case AND:
7398 {
7399 rtx op1 = XEXP (SET_SRC (pat), 1);
7400 if (GET_CODE (op1) == CONST_INT)
7401 return INTVAL (op1) >= 0;
7402 if (GET_CODE (XEXP (SET_SRC (pat), 0)) == REG
7403 && sparc_check_64 (XEXP (SET_SRC (pat), 0), insn) == 1)
7404 return 1;
7405 if (GET_CODE (op1) == REG
7406 && sparc_check_64 ((op1), insn) == 1)
7407 return 1;
7408 }
7409 case ASHIFT:
7410 case LSHIFTRT:
7411 return GET_MODE (SET_SRC (pat)) == SImode;
7412 /* Positive integers leave the high bits zero. */
7413 case CONST_DOUBLE:
7414 return ! (CONST_DOUBLE_LOW (x) & 0x80000000);
7415 case CONST_INT:
7416 return ! (INTVAL (x) & 0x80000000);
7417 case ASHIFTRT:
7418 case SIGN_EXTEND:
7419 return - (GET_MODE (SET_SRC (pat)) == SImode);
7420 default:
7421 return 0;
7422 }
7423}
7424
e0d80184
DM		 7425/* We _ought_ to have only one kind per function, but... */
7426static rtx sparc_addr_diff_list;
7427static rtx sparc_addr_list;
7428
7429void
7430sparc_defer_case_vector (lab, vec, diff)
7431 rtx lab, vec;
7432 int diff;
7433{
7434 vec = gen_rtx_EXPR_LIST (VOIDmode, lab, vec);
7435 if (diff)
7436 sparc_addr_diff_list
7437 = gen_rtx_EXPR_LIST (VOIDmode, vec, sparc_addr_diff_list);
7438 else
7439 sparc_addr_list = gen_rtx_EXPR_LIST (VOIDmode, vec, sparc_addr_list);
7440}
7441
7442static void
7443sparc_output_addr_vec (vec)
7444 rtx vec;
7445{
7446 rtx lab = XEXP (vec, 0), body = XEXP (vec, 1);
7447 int idx, vlen = XVECLEN (body, 0);
7448
d1accaa3
JJ		 7449#ifdef ASM_OUTPUT_ADDR_VEC_START
7450 ASM_OUTPUT_ADDR_VEC_START (asm_out_file);
7451#endif
7452
e0d80184
DM		 7453#ifdef ASM_OUTPUT_CASE_LABEL
7454 ASM_OUTPUT_CASE_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab),
7455 NEXT_INSN (lab));
7456#else
7457 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab));
7458#endif
7459
7460 for (idx = 0; idx < vlen; idx++)
7461 {
7462 ASM_OUTPUT_ADDR_VEC_ELT
7463 (asm_out_file, CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 0, idx), 0)));
7464 }
d1accaa3
JJ		 7465
7466#ifdef ASM_OUTPUT_ADDR_VEC_END
7467 ASM_OUTPUT_ADDR_VEC_END (asm_out_file);
7468#endif
e0d80184
DM		 7469}
7470
7471static void
7472sparc_output_addr_diff_vec (vec)
7473 rtx vec;
7474{
7475 rtx lab = XEXP (vec, 0), body = XEXP (vec, 1);
7476 rtx base = XEXP (XEXP (body, 0), 0);
7477 int idx, vlen = XVECLEN (body, 1);
7478
d1accaa3
JJ		 7479#ifdef ASM_OUTPUT_ADDR_VEC_START
7480 ASM_OUTPUT_ADDR_VEC_START (asm_out_file);
7481#endif
7482
e0d80184
DM		 7483#ifdef ASM_OUTPUT_CASE_LABEL
7484 ASM_OUTPUT_CASE_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab),
7485 NEXT_INSN (lab));
7486#else
7487 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab));
7488#endif
7489
7490 for (idx = 0; idx < vlen; idx++)
7491 {
7492 ASM_OUTPUT_ADDR_DIFF_ELT
7493 (asm_out_file,
7494 body,
7495 CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 1, idx), 0)),
7496 CODE_LABEL_NUMBER (base));
7497 }
d1accaa3
JJ		 7498
7499#ifdef ASM_OUTPUT_ADDR_VEC_END
7500 ASM_OUTPUT_ADDR_VEC_END (asm_out_file);
7501#endif
e0d80184
DM		 7502}
7503
7504static void
7505sparc_output_deferred_case_vectors ()
7506{
7507 rtx t;
d676da68 7508 int align;
e0d80184 7509
f3b8847b
DM		 7510 if (sparc_addr_list == NULL_RTX
7511 && sparc_addr_diff_list == NULL_RTX)
7512 return;
7513
e0d80184
DM		 7514 /* Align to cache line in the function's code section. */
7515 function_section (current_function_decl);
d676da68
DM		 7516
7517 align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT);
7518 if (align > 0)
f3b8847b 7519 ASM_OUTPUT_ALIGN (asm_out_file, align);
e0d80184
DM		 7520
7521 for (t = sparc_addr_list; t ; t = XEXP (t, 1))
7522 sparc_output_addr_vec (XEXP (t, 0));
7523 for (t = sparc_addr_diff_list; t ; t = XEXP (t, 1))
7524 sparc_output_addr_diff_vec (XEXP (t, 0));
7525
7526 sparc_addr_list = sparc_addr_diff_list = NULL_RTX;
7527}
7528
284d86e9
JC		 7529/* Return 0 if the high 32 bits of X (the low word of X, if DImode) are
7530 unknown. Return 1 if the high bits are zero, -1 if the register is
7531 sign extended. */
7532int
7533sparc_check_64 (x, insn)
7534 rtx x, insn;
7535{
7536 /* If a register is set only once it is safe to ignore insns this
7537 code does not know how to handle. The loop will either recognize
7538 the single set and return the correct value or fail to recognize
7539 it and return 0. */
7540 int set_once = 0;
7541
7542 if (GET_CODE (x) == REG
7543 && flag_expensive_optimizations
7544 && REG_N_SETS (REGNO (x)) == 1)
7545 set_once = 1;
7546
7547 if (insn == 0)
d6f4ec51
KG		 7548 {
7549 if (set_once)
7550 insn = get_last_insn_anywhere ();
7551 else
7552 return 0;
7553 }
284d86e9 7554
d6f4ec51 7555 while ((insn = PREV_INSN (insn)))
284d86e9
JC		 7556 {
7557 switch (GET_CODE (insn))
7558 {
7559 case JUMP_INSN:
7560 case NOTE:
7561 break;
7562 case CODE_LABEL:
7563 case CALL_INSN:
7564 default:
7565 if (! set_once)
7566 return 0;
7567 break;
7568 case INSN:
7569 {
7570 rtx pat = PATTERN (insn);
7571 if (GET_CODE (pat) != SET)
7572 return 0;
7573 if (rtx_equal_p (x, SET_DEST (pat)))
7574 return set_extends (x, insn);
7575 if (reg_overlap_mentioned_p (SET_DEST (pat), x))
7576 return 0;
7577 }
7578 }
7579 }
7580 return 0;
7581}
7582
7583char *
7584sparc_v8plus_shift (operands, insn, opcode)
7585 rtx *operands;
7586 rtx insn;
b1474bb7 7587 const char *opcode;
284d86e9
JC		 7588{
7589 static char asm_code[60];
7590
7591 if (GET_CODE (operands[3]) == SCRATCH)
7592 operands[3] = operands[0];
c6b0465b
JC		 7593 if (GET_CODE (operands[1]) == CONST_INT)
7594 {
7595 output_asm_insn ("mov %1,%3", operands);
7596 }
7597 else
7598 {
7599 output_asm_insn ("sllx %H1,32,%3", operands);
7600 if (sparc_check_64 (operands[1], insn) <= 0)
7601 output_asm_insn ("srl %L1,0,%L1", operands);
7602 output_asm_insn ("or %L1,%3,%3", operands);
7603 }
284d86e9
JC		 7604
7605 strcpy(asm_code, opcode);
7606 if (which_alternative != 2)
7607 return strcat (asm_code, " %0,%2,%L0\n\tsrlx %L0,32,%H0");
7608 else
7609 return strcat (asm_code, " %3,%2,%3\n\tsrlx %3,32,%H0\n\tmov %3,%L0");
7610}
7611
7612
7613/* Return 1 if DEST and SRC reference only global and in registers. */
7614
7615int
7616sparc_return_peephole_ok (dest, src)
7617 rtx dest, src;
7618{
7619 if (! TARGET_V9)
7620 return 0;
54ff41b7 7621 if (current_function_uses_only_leaf_regs)
284d86e9
JC		 7622 return 0;
7623 if (GET_CODE (src) != CONST_INT
7624 && (GET_CODE (src) != REG || ! IN_OR_GLOBAL_P (src)))
7625 return 0;
7626 return IN_OR_GLOBAL_P (dest);
7627}
2be15d0f
RH		 7628\f
7629/* Output assembler code to FILE to increment profiler label # LABELNO
7630 for profiling a function entry.
7631
7632 32 bit sparc uses %g2 as the STATIC_CHAIN_REGNUM which gets clobbered
7633 during profiling so we need to save/restore it around the call to mcount.
7634 We're guaranteed that a save has just been done, and we use the space
7635 allocated for intreg/fpreg value passing. */
7636
7637void
7638sparc_function_profiler (file, labelno)
7639 FILE *file;
7640 int labelno;
7641{
7642 char buf[32];
7643 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
7644
7645 if (! TARGET_ARCH64)
7646 fputs ("\tst\t%g2,[%fp-4]\n", file);
7647
7648 fputs ("\tsethi\t%hi(", file);
7649 assemble_name (file, buf);
7650 fputs ("),%o0\n", file);
7651
7652 fputs ("\tcall\t", file);
7653 assemble_name (file, MCOUNT_FUNCTION);
7654 putc ('\n', file);
7655
7656 fputs ("\t or\t%o0,%lo(", file);
7657 assemble_name (file, buf);
7658 fputs ("),%o0\n", file);
7659
7660 if (! TARGET_ARCH64)
7661 fputs ("\tld\t[%fp-4],%g2\n", file);
7662}
7663
7664
7665/* The following macro shall output assembler code to FILE
7666 to initialize basic-block profiling.
7667
7668 If profile_block_flag == 2
7669
7670 Output code to call the subroutine `__bb_init_trace_func'
7671 and pass two parameters to it. The first parameter is
7672 the address of a block allocated in the object module.
7673 The second parameter is the number of the first basic block
7674 of the function.
7675
7676 The name of the block is a local symbol made with this statement:
7677
7678 ASM_GENERATE_INTERNAL_LABEL (BUFFER, "LPBX", 0);
7679
7680 Of course, since you are writing the definition of
7681 `ASM_GENERATE_INTERNAL_LABEL' as well as that of this macro, you
7682 can take a short cut in the definition of this macro and use the
7683 name that you know will result.
7684
7685 The number of the first basic block of the function is
7686 passed to the macro in BLOCK_OR_LABEL.
7687
7688 If described in a virtual assembler language the code to be
7689 output looks like:
7690
7691 parameter1 <- LPBX0
7692 parameter2 <- BLOCK_OR_LABEL
7693 call __bb_init_trace_func
7694
7695 else if profile_block_flag != 0
7696
7697 Output code to call the subroutine `__bb_init_func'
7698 and pass one single parameter to it, which is the same
7699 as the first parameter to `__bb_init_trace_func'.
7700
7701 The first word of this parameter is a flag which will be nonzero if
7702 the object module has already been initialized. So test this word
7703 first, and do not call `__bb_init_func' if the flag is nonzero.
7704 Note: When profile_block_flag == 2 the test need not be done
7705 but `__bb_init_trace_func' *must* be called.
7706
7707 BLOCK_OR_LABEL may be used to generate a label number as a
7708 branch destination in case `__bb_init_func' will not be called.
7709
7710 If described in a virtual assembler language the code to be
7711 output looks like:
7712
7713 cmp (LPBX0),0
7714 jne local_label
7715 parameter1 <- LPBX0
7716 call __bb_init_func
7717 local_label:
7718
7719*/
7720
7721void
7722sparc_function_block_profiler(file, block_or_label)
7723 FILE *file;
7724 int block_or_label;
7725{
7726 char LPBX[32];
7727 ASM_GENERATE_INTERNAL_LABEL (LPBX, "LPBX", 0);
7728
7729 if (profile_block_flag == 2)
7730 {
7731 fputs ("\tsethi\t%hi(", file);
7732 assemble_name (file, LPBX);
7733 fputs ("),%o0\n", file);
7734
7735 fprintf (file, "\tsethi\t%%hi(%d),%%o1\n", block_or_label);
7736
7737 fputs ("\tor\t%o0,%lo(", file);
7738 assemble_name (file, LPBX);
7739 fputs ("),%o0\n", file);
7740
7741 fprintf (file, "\tcall\t%s__bb_init_trace_func\n", user_label_prefix);
7742
7743 fprintf (file, "\t or\t%%o1,%%lo(%d),%%o1\n", block_or_label);
7744 }
7745 else if (profile_block_flag != 0)
7746 {
7747 char LPBY[32];
7748 ASM_GENERATE_INTERNAL_LABEL (LPBY, "LPBY", block_or_label);
7749
7750 fputs ("\tsethi\t%hi(", file);
7751 assemble_name (file, LPBX);
7752 fputs ("),%o0\n", file);
7753
7754 fputs ("\tld\t[%lo(", file);
7755 assemble_name (file, LPBX);
7756 fputs (")+%o0],%o1\n", file);
7757
7758 fputs ("\ttst\t%o1\n", file);
7759
7760 if (TARGET_V9)
7761 {
7762 fputs ("\tbne,pn\t%icc,", file);
7763 assemble_name (file, LPBY);
7764 putc ('\n', file);
7765 }
7766 else
7767 {
7768 fputs ("\tbne\t", file);
7769 assemble_name (file, LPBY);
7770 putc ('\n', file);
7771 }
7772
7773 fputs ("\t or\t%o0,%lo(", file);
7774 assemble_name (file, LPBX);
7775 fputs ("),%o0\n", file);
7776
7777 fprintf (file, "\tcall\t%s__bb_init_func\n\t nop\n", user_label_prefix);
7778
7779 ASM_OUTPUT_INTERNAL_LABEL (file, "LPBY", block_or_label);
7780 }
7781}
7782
7783/* The following macro shall output assembler code to FILE
7784 to increment a counter associated with basic block number BLOCKNO.
7785
7786 If profile_block_flag == 2
7787
7788 Output code to initialize the global structure `__bb' and
7789 call the function `__bb_trace_func' which will increment the
7790 counter.
7791
7792 `__bb' consists of two words. In the first word the number
7793 of the basic block has to be stored. In the second word
7794 the address of a block allocated in the object module
7795 has to be stored.
7796
7797 The basic block number is given by BLOCKNO.
7798
7799 The address of the block is given by the label created with
7800
7801 ASM_GENERATE_INTERNAL_LABEL (BUFFER, "LPBX", 0);
7802
7803 by FUNCTION_BLOCK_PROFILER.
7804
7805 Of course, since you are writing the definition of
7806 `ASM_GENERATE_INTERNAL_LABEL' as well as that of this macro, you
7807 can take a short cut in the definition of this macro and use the
7808 name that you know will result.
7809
7810 If described in a virtual assembler language the code to be
7811 output looks like:
7812
7813 move BLOCKNO -> (__bb)
7814 move LPBX0 -> (__bb+4)
7815 call __bb_trace_func
7816
7817 Note that function `__bb_trace_func' must not change the
7818 machine state, especially the flag register. To grant
7819 this, you must output code to save and restore registers
7820 either in this macro or in the macros MACHINE_STATE_SAVE
7821 and MACHINE_STATE_RESTORE. The last two macros will be
7822 used in the function `__bb_trace_func', so you must make
7823 sure that the function prologue does not change any
7824 register prior to saving it with MACHINE_STATE_SAVE.
7825
7826 else if profile_block_flag != 0
7827
7828 Output code to increment the counter directly.
7829 Basic blocks are numbered separately from zero within each
7830 compiled object module. The count associated with block number
7831 BLOCKNO is at index BLOCKNO in an array of words; the name of
7832 this array is a local symbol made with this statement:
7833
7834 ASM_GENERATE_INTERNAL_LABEL (BUFFER, "LPBX", 2);
7835
7836 Of course, since you are writing the definition of
7837 `ASM_GENERATE_INTERNAL_LABEL' as well as that of this macro, you
7838 can take a short cut in the definition of this macro and use the
7839 name that you know will result.
7840
7841 If described in a virtual assembler language, the code to be
7842 output looks like:
7843
7844 inc (LPBX2+4*BLOCKNO)
7845
7846*/
7847
7848void
7849sparc_block_profiler(file, blockno)
7850 FILE *file;
7851 int blockno;
7852{
7853 char LPBX[32];
7854
7855 if (profile_block_flag == 2)
7856 {
7857 ASM_GENERATE_INTERNAL_LABEL (LPBX, "LPBX", 0);
7858
7859 fprintf (file, "\tsethi\t%%hi(%s__bb),%%g1\n", user_label_prefix);
7860 fprintf (file, "\tsethi\t%%hi(%d),%%g2\n", blockno);
7861 fprintf (file, "\tor\t%%g1,%%lo(%s__bb),%%g1\n", user_label_prefix);
7862 fprintf (file, "\tor\t%%g2,%%lo(%d),%%g2\n", blockno);
7863
7864 fputs ("\tst\t%g2,[%g1]\n", file);
7865
7866 fputs ("\tsethi\t%hi(", file);
7867 assemble_name (file, LPBX);
7868 fputs ("),%g2\n", file);
7869
110b0302 7870 fputs ("\tor\t%o2,%lo(", file);
2be15d0f
RH		 7871 assemble_name (file, LPBX);
7872 fputs ("),%g2\n", file);
7873
7874 fputs ("\tst\t%g2,[%g1+4]\n", file);
7875 fputs ("\tmov\t%o7,%g2\n", file);
7876
7877 fprintf (file, "\tcall\t%s__bb_trace_func\n\t nop\n", user_label_prefix);
7878
7879 fputs ("\tmov\t%g2,%o7\n", file);
7880 }
7881 else if (profile_block_flag != 0)
7882 {
7883 ASM_GENERATE_INTERNAL_LABEL (LPBX, "LPBX", 2);
7884
7885 fputs ("\tsethi\t%hi(", file);
7886 assemble_name (file, LPBX);
7887 fprintf (file, "+%d),%%g1\n", blockno*4);
7888
7889 fputs ("\tld\t[%g1+%lo(", file);
7890 assemble_name (file, LPBX);
7891 fprintf (file, "+%d)],%%g2\n", blockno*4);
7892
7893 fputs ("\tadd\t%g2,1,%g2\n", file);
7894
7895 fputs ("\tst\t%g2,[%g1+%lo(", file);
7896 assemble_name (file, LPBX);
7897 fprintf (file, "+%d)]\n", blockno*4);
7898 }
7899}
7900
7901/* The following macro shall output assembler code to FILE
7902 to indicate a return from function during basic-block profiling.
7903
7904 If profile_block_flag == 2:
7905
7906 Output assembler code to call function `__bb_trace_ret'.
7907
7908 Note that function `__bb_trace_ret' must not change the
7909 machine state, especially the flag register. To grant
7910 this, you must output code to save and restore registers
7911 either in this macro or in the macros MACHINE_STATE_SAVE_RET
7912 and MACHINE_STATE_RESTORE_RET. The last two macros will be
7913 used in the function `__bb_trace_ret', so you must make
7914 sure that the function prologue does not change any
7915 register prior to saving it with MACHINE_STATE_SAVE_RET.
7916
7917 else if profile_block_flag != 0:
7918
7919 The macro will not be used, so it need not distinguish
7920 these cases.
7921*/
7922
7923void
7924sparc_function_block_profiler_exit(file)
7925 FILE *file;
7926{
7927 if (profile_block_flag == 2)
7928 fprintf (file, "\tcall\t%s__bb_trace_ret\n\t nop\n", user_label_prefix);
7929 else
7930 abort ();
7931}
d07d525a
MM		 7932
7933/* Mark ARG, which is really a struct ultrasparc_pipline_state *, for
7934 GC. */
7935
7936static void
7937mark_ultrasparc_pipeline_state (arg)
7938 void *arg;
7939{
7940 struct ultrasparc_pipeline_state *ups;
7941 size_t i;
7942
7943 ups = (struct ultrasparc_pipeline_state *) arg;
7944 for (i = 0; i < sizeof (ups->group) / sizeof (rtx); ++i)
7945 ggc_mark_rtx (ups->group[i]);
7946}
7947
7948/* Called to register all of our global variables with the garbage
7949 collector. */
7950
7951static void
7952sparc_add_gc_roots ()
7953{
7954 ggc_add_rtx_root (&sparc_compare_op0, 1);
7955 ggc_add_rtx_root (&sparc_compare_op1, 1);
7956 ggc_add_rtx_root (&leaf_label, 1);
7957 ggc_add_rtx_root (&global_offset_table, 1);
7958 ggc_add_rtx_root (&get_pc_symbol, 1);
7959 ggc_add_rtx_root (&sparc_addr_diff_list, 1);
7960 ggc_add_rtx_root (&sparc_addr_list, 1);
7961 ggc_add_root (ultra_pipe_hist,
7962 sizeof (ultra_pipe_hist) / sizeof (ultra_pipe_hist[0]),
7963 sizeof (ultra_pipe_hist[0]),
7964 &mark_ultrasparc_pipeline_state);
7965}
GNU Compiler Collection
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