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ab835497 | 1 | /* Subroutines for insn-output.c for Sun SPARC. |
d2889939 | 2 | Copyright (C) 1987, 88, 89, 92, 93, 94, 1995 Free Software Foundation, Inc. |
ab835497 | 3 | Contributed by Michael Tiemann (tiemann@cygnus.com) |
61a55e8b DE |
4 | 64 bit SPARC V9 support by Michael Tiemann, Jim Wilson, and Doug Evans, |
5 | at Cygnus Support. | |
ab835497 RK |
6 | |
7 | This file is part of GNU CC. | |
8 | ||
9 | GNU CC is free software; you can redistribute it and/or modify | |
10 | it under the terms of the GNU General Public License as published by | |
11 | the Free Software Foundation; either version 2, or (at your option) | |
12 | any later version. | |
13 | ||
14 | GNU CC is distributed in the hope that it will be useful, | |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
18 | ||
19 | You should have received a copy of the GNU General Public License | |
20 | along with GNU CC; see the file COPYING. If not, write to | |
21 | the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ | |
22 | ||
23 | #include <stdio.h> | |
24 | #include "config.h" | |
210aa14a | 25 | #include "tree.h" |
ab835497 RK |
26 | #include "rtl.h" |
27 | #include "regs.h" | |
28 | #include "hard-reg-set.h" | |
29 | #include "real.h" | |
30 | #include "insn-config.h" | |
31 | #include "conditions.h" | |
32 | #include "insn-flags.h" | |
33 | #include "output.h" | |
34 | #include "insn-attr.h" | |
35 | #include "flags.h" | |
36 | #include "expr.h" | |
37 | #include "recog.h" | |
38 | ||
61a55e8b DE |
39 | /* 1 if the caller has placed an "unimp" insn immediately after the call. |
40 | This is used in v8 code when calling a function that returns a structure. | |
41 | v9 doesn't have this. */ | |
42 | ||
43 | #define SKIP_CALLERS_UNIMP_P (!TARGET_V9 && current_function_returns_struct) | |
44 | ||
ab835497 RK |
45 | /* Global variables for machine-dependent things. */ |
46 | ||
dbb54862 JW |
47 | /* Says what architecture we're compiling for. */ |
48 | enum arch_type sparc_arch_type; | |
61a55e8b DE |
49 | |
50 | /* Size of frame. Need to know this to emit return insns from leaf procedures. | |
51 | ACTUAL_FSIZE is set by compute_frame_size() which is called during the | |
52 | reload pass. This is important as the value is later used in insn | |
53 | scheduling (to see what can go in a delay slot). | |
54 | APPARENT_FSIZE is the size of the stack less the register save area and less | |
55 | the outgoing argument area. It is used when saving call preserved regs. */ | |
56 | static int apparent_fsize; | |
57 | static int actual_fsize; | |
58 | ||
ab835497 RK |
59 | /* Save the operands last given to a compare for use when we |
60 | generate a scc or bcc insn. */ | |
61 | ||
62 | rtx sparc_compare_op0, sparc_compare_op1; | |
63 | ||
61a55e8b DE |
64 | /* Count of named arguments (v9 only). |
65 | ??? INIT_CUMULATIVE_ARGS initializes these, and FUNCTION_ARG_ADVANCE | |
66 | increments SPARC_ARG_COUNT. They are then used by | |
67 | FUNCTION_ARG_CALLEE_COPIES to determine if the argument is really a named | |
68 | argument or not. This hack is necessary because the NAMED argument to the | |
69 | FUNCTION_ARG_XXX macros is not what it says it is: it does not include the | |
70 | last named argument. */ | |
71 | ||
72 | int sparc_arg_count; | |
73 | int sparc_n_named_args; | |
74 | ||
ab835497 RK |
75 | /* We may need an epilogue if we spill too many registers. |
76 | If this is non-zero, then we branch here for the epilogue. */ | |
77 | static rtx leaf_label; | |
78 | ||
79 | #ifdef LEAF_REGISTERS | |
80 | ||
81 | /* Vector to say how input registers are mapped to output | |
82 | registers. FRAME_POINTER_REGNUM cannot be remapped by | |
83 | this function to eliminate it. You must use -fomit-frame-pointer | |
84 | to get that. */ | |
85 | char leaf_reg_remap[] = | |
86 | { 0, 1, 2, 3, 4, 5, 6, 7, | |
87 | -1, -1, -1, -1, -1, -1, 14, -1, | |
88 | -1, -1, -1, -1, -1, -1, -1, -1, | |
89 | 8, 9, 10, 11, 12, 13, -1, 15, | |
90 | ||
91 | 32, 33, 34, 35, 36, 37, 38, 39, | |
92 | 40, 41, 42, 43, 44, 45, 46, 47, | |
93 | 48, 49, 50, 51, 52, 53, 54, 55, | |
61a55e8b DE |
94 | 56, 57, 58, 59, 60, 61, 62, 63, |
95 | 64, 65, 66, 67, 68, 69, 70, 71, | |
96 | 72, 73, 74, 75, 76, 77, 78, 79, | |
97 | 80, 81, 82, 83, 84, 85, 86, 87, | |
98 | 88, 89, 90, 91, 92, 93, 94, 95, | |
99 | 96, 97, 98, 99}; | |
ab835497 | 100 | |
6a4bb1fa | 101 | #endif |
ab835497 | 102 | |
ab835497 RK |
103 | /* Name of where we pretend to think the frame pointer points. |
104 | Normally, this is "%fp", but if we are in a leaf procedure, | |
61a55e8b DE |
105 | this is "%sp+something". We record "something" separately as it may be |
106 | too big for reg+constant addressing. */ | |
107 | ||
108 | static char *frame_base_name; | |
109 | static int frame_base_offset; | |
ab835497 RK |
110 | |
111 | static rtx find_addr_reg (); | |
61a55e8b DE |
112 | static void sparc_init_modes (); |
113 | \f | |
114 | /* Option handling. */ | |
115 | ||
61a55e8b DE |
116 | /* Validate and override various options, and do some machine dependent |
117 | initialization. */ | |
118 | ||
119 | void | |
120 | sparc_override_options () | |
121 | { | |
61a55e8b DE |
122 | /* Check for any conflicts in the choice of options. */ |
123 | /* ??? This stuff isn't really usable yet. */ | |
124 | ||
125 | if (! TARGET_V9) | |
126 | { | |
00dc0e0a JW |
127 | if (target_flags & MASK_CODE_MODEL) |
128 | error ("code model support is only available with -mv9"); | |
61a55e8b DE |
129 | if (TARGET_INT64) |
130 | error ("-mint64 is only available with -mv9"); | |
131 | if (TARGET_LONG64) | |
132 | error ("-mlong64 is only available with -mv9"); | |
133 | if (TARGET_PTR64) | |
134 | error ("-mptr64 is only available with -mv9"); | |
135 | if (TARGET_ENV32) | |
136 | error ("-menv32 is only available with -mv9"); | |
137 | if (TARGET_STACK_BIAS) | |
138 | error ("-mstack-bias is only available with -mv9"); | |
139 | } | |
140 | else | |
141 | { | |
142 | /* ??? Are there any options that aren't usable with v9. | |
143 | -munaligned-doubles? */ | |
144 | } | |
145 | ||
146 | /* Check for conflicts in cpu specification. | |
147 | If we use -mcpu=xxx, this can be removed. */ | |
148 | ||
149 | if ((TARGET_V8 != 0) + (TARGET_SPARCLITE != 0) + (TARGET_V9 != 0) > 1) | |
150 | error ("conflicting architectures defined"); | |
151 | ||
152 | /* Do various machine dependent initializations. */ | |
153 | sparc_init_modes (); | |
154 | } | |
155 | \f | |
156 | /* Float conversions (v9 only). | |
157 | ||
158 | The floating point registers cannot hold DImode values because SUBREG's | |
159 | on them get the wrong register. "(subreg:SI (reg:DI M int-reg) 0)" is the | |
160 | same as "(subreg:SI (reg:DI N float-reg) 1)", but gcc doesn't know how to | |
161 | turn the "0" to a "1". Therefore, we must explicitly do the conversions | |
162 | to/from int/fp regs. `sparc64_fpconv_stack_slot' is the address of an | |
163 | 8 byte stack slot used during the transfer. | |
164 | ??? I could have used [%fp-16] but I didn't want to add yet another | |
165 | dependence on this. */ | |
166 | /* ??? Can we use assign_stack_temp here? */ | |
167 | ||
168 | static rtx fpconv_stack_temp; | |
169 | ||
170 | /* Called once for each function. */ | |
171 | ||
172 | void | |
173 | sparc64_init_expanders () | |
174 | { | |
175 | fpconv_stack_temp = NULL_RTX; | |
176 | } | |
177 | ||
178 | /* Assign a stack temp for fp/int DImode conversions. */ | |
ab835497 | 179 | |
61a55e8b DE |
180 | rtx |
181 | sparc64_fpconv_stack_temp () | |
182 | { | |
183 | if (fpconv_stack_temp == NULL_RTX) | |
184 | fpconv_stack_temp = | |
185 | assign_stack_local (DImode, GET_MODE_SIZE (DImode), 0); | |
186 | ||
187 | return fpconv_stack_temp; | |
188 | } | |
189 | \f | |
cd5fb1ee DE |
190 | /* Miscellaneous utilities. */ |
191 | ||
192 | /* Nonzero if CODE, a comparison, is suitable for use in v9 conditional move | |
193 | or branch on register contents instructions. */ | |
194 | ||
195 | int | |
196 | v9_regcmp_p (code) | |
197 | enum rtx_code code; | |
198 | { | |
199 | return (code == EQ || code == NE || code == GE || code == LT | |
200 | || code == LE || code == GT); | |
201 | } | |
202 | \f | |
203 | /* Operand constraints. */ | |
204 | ||
ab835497 RK |
205 | /* Return non-zero only if OP is a register of mode MODE, |
206 | or const0_rtx. */ | |
207 | int | |
208 | reg_or_0_operand (op, mode) | |
209 | rtx op; | |
210 | enum machine_mode mode; | |
211 | { | |
212 | if (op == const0_rtx || register_operand (op, mode)) | |
213 | return 1; | |
5b486ce0 | 214 | if (GET_MODE (op) == VOIDmode && GET_CODE (op) == CONST_DOUBLE |
ab835497 RK |
215 | && CONST_DOUBLE_HIGH (op) == 0 |
216 | && CONST_DOUBLE_LOW (op) == 0) | |
217 | return 1; | |
302484ff JW |
218 | if (GET_MODE_CLASS (GET_MODE (op)) == MODE_FLOAT |
219 | && GET_CODE (op) == CONST_DOUBLE | |
220 | && fp_zero_operand (op)) | |
221 | return 1; | |
ab835497 RK |
222 | return 0; |
223 | } | |
224 | ||
302484ff JW |
225 | /* Nonzero if OP is a floating point value with value 0.0. */ |
226 | int | |
227 | fp_zero_operand (op) | |
228 | rtx op; | |
229 | { | |
230 | REAL_VALUE_TYPE r; | |
231 | ||
232 | REAL_VALUE_FROM_CONST_DOUBLE (r, op); | |
233 | return REAL_VALUES_EQUAL (r, dconst0); | |
234 | } | |
235 | ||
61a55e8b DE |
236 | /* Nonzero if OP is an integer register. */ |
237 | ||
238 | int | |
239 | intreg_operand (op, mode) | |
240 | rtx op; | |
241 | enum machine_mode mode; | |
242 | { | |
243 | return (register_operand (op, SImode) | |
244 | || (TARGET_V9 && register_operand (op, DImode))); | |
245 | } | |
246 | ||
247 | /* Nonzero if OP is a floating point condition code register. */ | |
248 | ||
249 | int | |
250 | ccfp_reg_operand (op, mode) | |
251 | rtx op; | |
252 | enum machine_mode mode; | |
253 | { | |
254 | /* This can happen when recog is called from combine. Op may be a MEM. | |
255 | Fail instead of calling abort in this case. */ | |
256 | if (GET_CODE (op) != REG || REGNO (op) == 0) | |
257 | return 0; | |
258 | if (GET_MODE (op) != mode) | |
259 | return 0; | |
260 | ||
261 | #if 0 /* ??? ==> 1 when %fcc1-3 are pseudos first. See gen_compare_reg(). */ | |
262 | if (reg_renumber == 0) | |
263 | return REGNO (op) >= FIRST_PSEUDO_REGISTER; | |
264 | return REGNO_OK_FOR_CCFP_P (REGNO (op)); | |
265 | #else | |
266 | return (unsigned) REGNO (op) - 96 < 4; | |
267 | #endif | |
268 | } | |
269 | ||
ab835497 RK |
270 | /* Nonzero if OP can appear as the dest of a RESTORE insn. */ |
271 | int | |
272 | restore_operand (op, mode) | |
273 | rtx op; | |
274 | enum machine_mode mode; | |
275 | { | |
276 | return (GET_CODE (op) == REG && GET_MODE (op) == mode | |
277 | && (REGNO (op) < 8 || (REGNO (op) >= 24 && REGNO (op) < 32))); | |
278 | } | |
279 | ||
401cec23 JW |
280 | /* Call insn on SPARC can take a PC-relative constant address, or any regular |
281 | memory address. */ | |
ab835497 RK |
282 | |
283 | int | |
284 | call_operand (op, mode) | |
285 | rtx op; | |
286 | enum machine_mode mode; | |
287 | { | |
288 | if (GET_CODE (op) != MEM) | |
289 | abort (); | |
290 | op = XEXP (op, 0); | |
2445f289 | 291 | return (symbolic_operand (op, mode) || memory_address_p (Pmode, op)); |
ab835497 RK |
292 | } |
293 | ||
294 | int | |
295 | call_operand_address (op, mode) | |
296 | rtx op; | |
297 | enum machine_mode mode; | |
298 | { | |
2445f289 | 299 | return (symbolic_operand (op, mode) || memory_address_p (Pmode, op)); |
ab835497 RK |
300 | } |
301 | ||
302 | /* Returns 1 if OP is either a symbol reference or a sum of a symbol | |
303 | reference and a constant. */ | |
304 | ||
305 | int | |
306 | symbolic_operand (op, mode) | |
307 | register rtx op; | |
308 | enum machine_mode mode; | |
309 | { | |
310 | switch (GET_CODE (op)) | |
311 | { | |
312 | case SYMBOL_REF: | |
313 | case LABEL_REF: | |
314 | return 1; | |
315 | ||
316 | case CONST: | |
317 | op = XEXP (op, 0); | |
318 | return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF | |
319 | || GET_CODE (XEXP (op, 0)) == LABEL_REF) | |
320 | && GET_CODE (XEXP (op, 1)) == CONST_INT); | |
321 | ||
228b4037 | 322 | /* ??? This clause seems to be irrelevant. */ |
ab835497 RK |
323 | case CONST_DOUBLE: |
324 | return GET_MODE (op) == mode; | |
325 | ||
326 | default: | |
327 | return 0; | |
328 | } | |
329 | } | |
330 | ||
331 | /* Return truth value of statement that OP is a symbolic memory | |
332 | operand of mode MODE. */ | |
333 | ||
334 | int | |
335 | symbolic_memory_operand (op, mode) | |
336 | rtx op; | |
337 | enum machine_mode mode; | |
338 | { | |
339 | if (GET_CODE (op) == SUBREG) | |
340 | op = SUBREG_REG (op); | |
341 | if (GET_CODE (op) != MEM) | |
342 | return 0; | |
343 | op = XEXP (op, 0); | |
344 | return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST | |
345 | || GET_CODE (op) == HIGH || GET_CODE (op) == LABEL_REF); | |
346 | } | |
347 | ||
61a55e8b DE |
348 | /* Return 1 if the operand is a data segment reference. This includes |
349 | the readonly data segment, or in other words anything but the text segment. | |
350 | This is needed in the medium/anywhere code model on v9. These values | |
351 | are accessed with MEDANY_BASE_REG. */ | |
352 | ||
353 | int | |
354 | data_segment_operand (op, mode) | |
355 | rtx op; | |
356 | enum machine_mode mode; | |
357 | { | |
358 | switch (GET_CODE (op)) | |
359 | { | |
360 | case SYMBOL_REF : | |
361 | return ! SYMBOL_REF_FLAG (op); | |
362 | case PLUS : | |
363 | /* Assume canonical format of symbol + constant. */ | |
364 | case CONST : | |
365 | return data_segment_operand (XEXP (op, 0)); | |
366 | default : | |
367 | return 0; | |
368 | } | |
369 | } | |
370 | ||
371 | /* Return 1 if the operand is a text segment reference. | |
372 | This is needed in the medium/anywhere code model on v9. */ | |
373 | ||
374 | int | |
375 | text_segment_operand (op, mode) | |
376 | rtx op; | |
377 | enum machine_mode mode; | |
378 | { | |
379 | switch (GET_CODE (op)) | |
380 | { | |
381 | case LABEL_REF : | |
382 | return 1; | |
383 | case SYMBOL_REF : | |
384 | return SYMBOL_REF_FLAG (op); | |
385 | case PLUS : | |
386 | /* Assume canonical format of symbol + constant. */ | |
387 | case CONST : | |
388 | return text_segment_operand (XEXP (op, 0)); | |
389 | default : | |
390 | return 0; | |
391 | } | |
392 | } | |
393 | ||
ab835497 RK |
394 | /* Return 1 if the operand is either a register or a memory operand that is |
395 | not symbolic. */ | |
396 | ||
397 | int | |
398 | reg_or_nonsymb_mem_operand (op, mode) | |
399 | register rtx op; | |
400 | enum machine_mode mode; | |
401 | { | |
402 | if (register_operand (op, mode)) | |
403 | return 1; | |
404 | ||
405 | if (memory_operand (op, mode) && ! symbolic_memory_operand (op, mode)) | |
406 | return 1; | |
407 | ||
408 | return 0; | |
409 | } | |
410 | ||
411 | int | |
412 | sparc_operand (op, mode) | |
413 | rtx op; | |
414 | enum machine_mode mode; | |
415 | { | |
416 | if (register_operand (op, mode)) | |
417 | return 1; | |
418 | if (GET_CODE (op) == CONST_INT) | |
419 | return SMALL_INT (op); | |
420 | if (GET_MODE (op) != mode) | |
421 | return 0; | |
422 | if (GET_CODE (op) == SUBREG) | |
423 | op = SUBREG_REG (op); | |
424 | if (GET_CODE (op) != MEM) | |
425 | return 0; | |
426 | ||
427 | op = XEXP (op, 0); | |
428 | if (GET_CODE (op) == LO_SUM) | |
429 | return (GET_CODE (XEXP (op, 0)) == REG | |
430 | && symbolic_operand (XEXP (op, 1), Pmode)); | |
431 | return memory_address_p (mode, op); | |
432 | } | |
433 | ||
434 | int | |
435 | move_operand (op, mode) | |
436 | rtx op; | |
437 | enum machine_mode mode; | |
438 | { | |
439 | if (mode == DImode && arith_double_operand (op, mode)) | |
440 | return 1; | |
441 | if (register_operand (op, mode)) | |
442 | return 1; | |
443 | if (GET_CODE (op) == CONST_INT) | |
444 | return (SMALL_INT (op) || (INTVAL (op) & 0x3ff) == 0); | |
445 | ||
446 | if (GET_MODE (op) != mode) | |
447 | return 0; | |
448 | if (GET_CODE (op) == SUBREG) | |
449 | op = SUBREG_REG (op); | |
450 | if (GET_CODE (op) != MEM) | |
451 | return 0; | |
452 | op = XEXP (op, 0); | |
453 | if (GET_CODE (op) == LO_SUM) | |
454 | return (register_operand (XEXP (op, 0), Pmode) | |
455 | && CONSTANT_P (XEXP (op, 1))); | |
456 | return memory_address_p (mode, op); | |
457 | } | |
458 | ||
459 | int | |
460 | move_pic_label (op, mode) | |
461 | rtx op; | |
462 | enum machine_mode mode; | |
463 | { | |
464 | /* Special case for PIC. */ | |
465 | if (flag_pic && GET_CODE (op) == LABEL_REF) | |
466 | return 1; | |
467 | return 0; | |
468 | } | |
ab835497 RK |
469 | |
470 | int | |
6ac34277 | 471 | splittable_symbolic_memory_operand (op, mode) |
ab835497 RK |
472 | rtx op; |
473 | enum machine_mode mode; | |
474 | { | |
6ac34277 DE |
475 | if (GET_CODE (op) != MEM) |
476 | return 0; | |
477 | if (! symbolic_operand (XEXP (op, 0), Pmode)) | |
478 | return 0; | |
479 | return 1; | |
480 | } | |
481 | ||
482 | int | |
483 | splittable_immediate_memory_operand (op, mode) | |
484 | rtx op; | |
485 | enum machine_mode mode; | |
486 | { | |
487 | if (GET_CODE (op) != MEM) | |
488 | return 0; | |
489 | if (! immediate_operand (XEXP (op, 0), Pmode)) | |
490 | return 0; | |
491 | return 1; | |
ab835497 RK |
492 | } |
493 | ||
494 | /* Return truth value of whether OP is EQ or NE. */ | |
495 | ||
496 | int | |
497 | eq_or_neq (op, mode) | |
498 | rtx op; | |
499 | enum machine_mode mode; | |
500 | { | |
501 | return (GET_CODE (op) == EQ || GET_CODE (op) == NE); | |
502 | } | |
503 | ||
504 | /* Return 1 if this is a comparison operator, but not an EQ, NE, GEU, | |
505 | or LTU for non-floating-point. We handle those specially. */ | |
506 | ||
507 | int | |
508 | normal_comp_operator (op, mode) | |
509 | rtx op; | |
510 | enum machine_mode mode; | |
511 | { | |
512 | enum rtx_code code = GET_CODE (op); | |
513 | ||
514 | if (GET_RTX_CLASS (code) != '<') | |
515 | return 0; | |
516 | ||
4d449554 JW |
517 | if (GET_MODE (XEXP (op, 0)) == CCFPmode |
518 | || GET_MODE (XEXP (op, 0)) == CCFPEmode) | |
ab835497 RK |
519 | return 1; |
520 | ||
521 | return (code != NE && code != EQ && code != GEU && code != LTU); | |
522 | } | |
523 | ||
524 | /* Return 1 if this is a comparison operator. This allows the use of | |
525 | MATCH_OPERATOR to recognize all the branch insns. */ | |
526 | ||
527 | int | |
528 | noov_compare_op (op, mode) | |
529 | register rtx op; | |
530 | enum machine_mode mode; | |
531 | { | |
532 | enum rtx_code code = GET_CODE (op); | |
533 | ||
534 | if (GET_RTX_CLASS (code) != '<') | |
535 | return 0; | |
536 | ||
537 | if (GET_MODE (XEXP (op, 0)) == CC_NOOVmode) | |
538 | /* These are the only branches which work with CC_NOOVmode. */ | |
539 | return (code == EQ || code == NE || code == GE || code == LT); | |
540 | return 1; | |
541 | } | |
542 | ||
61a55e8b DE |
543 | /* Nonzero if OP is a comparison operator suitable for use in v9 |
544 | conditional move or branch on register contents instructions. */ | |
545 | ||
546 | int | |
547 | v9_regcmp_op (op, mode) | |
548 | register rtx op; | |
549 | enum machine_mode mode; | |
550 | { | |
551 | enum rtx_code code = GET_CODE (op); | |
552 | ||
553 | if (GET_RTX_CLASS (code) != '<') | |
554 | return 0; | |
555 | ||
cd5fb1ee | 556 | return v9_regcmp_p (code); |
61a55e8b DE |
557 | } |
558 | ||
ab835497 RK |
559 | /* Return 1 if this is a SIGN_EXTEND or ZERO_EXTEND operation. */ |
560 | ||
561 | int | |
562 | extend_op (op, mode) | |
563 | rtx op; | |
564 | enum machine_mode mode; | |
565 | { | |
566 | return GET_CODE (op) == SIGN_EXTEND || GET_CODE (op) == ZERO_EXTEND; | |
567 | } | |
568 | ||
569 | /* Return nonzero if OP is an operator of mode MODE which can set | |
570 | the condition codes explicitly. We do not include PLUS and MINUS | |
571 | because these require CC_NOOVmode, which we handle explicitly. */ | |
572 | ||
573 | int | |
574 | cc_arithop (op, mode) | |
575 | rtx op; | |
576 | enum machine_mode mode; | |
577 | { | |
578 | if (GET_CODE (op) == AND | |
579 | || GET_CODE (op) == IOR | |
580 | || GET_CODE (op) == XOR) | |
581 | return 1; | |
582 | ||
583 | return 0; | |
584 | } | |
585 | ||
586 | /* Return nonzero if OP is an operator of mode MODE which can bitwise | |
587 | complement its second operand and set the condition codes explicitly. */ | |
588 | ||
589 | int | |
590 | cc_arithopn (op, mode) | |
591 | rtx op; | |
592 | enum machine_mode mode; | |
593 | { | |
594 | /* XOR is not here because combine canonicalizes (xor (not ...) ...) | |
595 | and (xor ... (not ...)) to (not (xor ...)). */ | |
596 | return (GET_CODE (op) == AND | |
597 | || GET_CODE (op) == IOR); | |
598 | } | |
599 | \f | |
228b4037 JW |
600 | /* Return true if OP is a register, or is a CONST_INT that can fit in a 13 |
601 | bit immediate field. This is an acceptable SImode operand for most 3 | |
602 | address instructions. */ | |
ab835497 RK |
603 | |
604 | int | |
605 | arith_operand (op, mode) | |
606 | rtx op; | |
607 | enum machine_mode mode; | |
608 | { | |
609 | return (register_operand (op, mode) | |
610 | || (GET_CODE (op) == CONST_INT && SMALL_INT (op))); | |
611 | } | |
612 | ||
61a55e8b DE |
613 | /* Return true if OP is a register, or is a CONST_INT that can fit in an 11 |
614 | bit immediate field. This is an acceptable SImode operand for the movcc | |
615 | instructions. */ | |
616 | ||
617 | int | |
618 | arith11_operand (op, mode) | |
619 | rtx op; | |
620 | enum machine_mode mode; | |
621 | { | |
622 | return (register_operand (op, mode) | |
623 | || (GET_CODE (op) == CONST_INT | |
624 | && ((unsigned) (INTVAL (op) + 0x400) < 0x800))); | |
625 | } | |
626 | ||
627 | /* Return true if OP is a register, or is a CONST_INT that can fit in an 10 | |
628 | bit immediate field. This is an acceptable SImode operand for the movrcc | |
629 | instructions. */ | |
630 | ||
631 | int | |
632 | arith10_operand (op, mode) | |
633 | rtx op; | |
634 | enum machine_mode mode; | |
635 | { | |
636 | return (register_operand (op, mode) | |
637 | || (GET_CODE (op) == CONST_INT | |
638 | && ((unsigned) (INTVAL (op) + 0x200) < 0x400))); | |
639 | } | |
640 | ||
23b8a89f JW |
641 | /* Return true if OP is a register, is a CONST_INT that fits in a 13 bit |
642 | immediate field, or is a CONST_DOUBLE whose both parts fit in a 13 bit | |
61a55e8b DE |
643 | immediate field. |
644 | v9: Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that | |
645 | can fit in a 13 bit immediate field. This is an acceptable DImode operand | |
646 | for most 3 address instructions. */ | |
ab835497 RK |
647 | |
648 | int | |
649 | arith_double_operand (op, mode) | |
650 | rtx op; | |
651 | enum machine_mode mode; | |
652 | { | |
653 | return (register_operand (op, mode) | |
23b8a89f | 654 | || (GET_CODE (op) == CONST_INT && SMALL_INT (op)) |
61a55e8b DE |
655 | || (! TARGET_V9 |
656 | && GET_CODE (op) == CONST_DOUBLE | |
ab835497 | 657 | && (unsigned) (CONST_DOUBLE_LOW (op) + 0x1000) < 0x2000 |
61a55e8b DE |
658 | && (unsigned) (CONST_DOUBLE_HIGH (op) + 0x1000) < 0x2000) |
659 | || (TARGET_V9 | |
660 | && GET_CODE (op) == CONST_DOUBLE | |
661 | && (unsigned) (CONST_DOUBLE_LOW (op) + 0x1000) < 0x2000 | |
662 | && ((CONST_DOUBLE_HIGH (op) == -1 | |
663 | && (CONST_DOUBLE_LOW (op) & 0x1000) == 0x1000) | |
664 | || (CONST_DOUBLE_HIGH (op) == 0 | |
665 | && (CONST_DOUBLE_LOW (op) & 0x1000) == 0)))); | |
666 | } | |
667 | ||
668 | /* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that | |
669 | can fit in an 11 bit immediate field. This is an acceptable DImode | |
670 | operand for the movcc instructions. */ | |
671 | /* ??? Replace with arith11_operand? */ | |
672 | ||
673 | int | |
674 | arith11_double_operand (op, mode) | |
675 | rtx op; | |
676 | enum machine_mode mode; | |
677 | { | |
678 | return (register_operand (op, mode) | |
679 | || (GET_CODE (op) == CONST_DOUBLE | |
680 | && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode) | |
681 | && (unsigned) (CONST_DOUBLE_LOW (op) + 0x400) < 0x800 | |
682 | && ((CONST_DOUBLE_HIGH (op) == -1 | |
683 | && (CONST_DOUBLE_LOW (op) & 0x400) == 0x400) | |
684 | || (CONST_DOUBLE_HIGH (op) == 0 | |
685 | && (CONST_DOUBLE_LOW (op) & 0x400) == 0))) | |
686 | || (GET_CODE (op) == CONST_INT | |
687 | && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode) | |
688 | && (unsigned) (INTVAL (op) + 0x400) < 0x800)); | |
689 | } | |
690 | ||
691 | /* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that | |
692 | can fit in an 10 bit immediate field. This is an acceptable DImode | |
693 | operand for the movrcc instructions. */ | |
694 | /* ??? Replace with arith10_operand? */ | |
695 | ||
696 | int | |
697 | arith10_double_operand (op, mode) | |
698 | rtx op; | |
699 | enum machine_mode mode; | |
700 | { | |
701 | return (register_operand (op, mode) | |
702 | || (GET_CODE (op) == CONST_DOUBLE | |
703 | && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode) | |
704 | && (unsigned) (CONST_DOUBLE_LOW (op) + 0x200) < 0x400 | |
705 | && ((CONST_DOUBLE_HIGH (op) == -1 | |
706 | && (CONST_DOUBLE_LOW (op) & 0x200) == 0x200) | |
707 | || (CONST_DOUBLE_HIGH (op) == 0 | |
708 | && (CONST_DOUBLE_LOW (op) & 0x200) == 0))) | |
709 | || (GET_CODE (op) == CONST_INT | |
710 | && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode) | |
711 | && (unsigned) (INTVAL (op) + 0x200) < 0x400)); | |
ab835497 RK |
712 | } |
713 | ||
714 | /* Return truth value of whether OP is a integer which fits the | |
228b4037 JW |
715 | range constraining immediate operands in most three-address insns, |
716 | which have a 13 bit immediate field. */ | |
ab835497 RK |
717 | |
718 | int | |
719 | small_int (op, mode) | |
720 | rtx op; | |
721 | enum machine_mode mode; | |
722 | { | |
723 | return (GET_CODE (op) == CONST_INT && SMALL_INT (op)); | |
724 | } | |
725 | ||
9b3fad96 JW |
726 | /* Recognize operand values for the umul instruction. That instruction sign |
727 | extends immediate values just like all other sparc instructions, but | |
728 | interprets the extended result as an unsigned number. */ | |
729 | ||
730 | int | |
731 | uns_small_int (op, mode) | |
732 | rtx op; | |
733 | enum machine_mode mode; | |
734 | { | |
735 | #if HOST_BITS_PER_WIDE_INT > 32 | |
736 | /* All allowed constants will fit a CONST_INT. */ | |
737 | return (GET_CODE (op) == CONST_INT | |
738 | && ((INTVAL (op) >= 0 && INTVAL (op) < 0x1000) | |
739 | || (INTVAL (op) >= 0xFFFFF000 && INTVAL (op) < 0x100000000L))); | |
740 | #else | |
741 | return ((GET_CODE (op) == CONST_INT && (unsigned) INTVAL (op) < 0x1000) | |
742 | || (GET_CODE (op) == CONST_DOUBLE | |
743 | && CONST_DOUBLE_HIGH (op) == 0 | |
744 | && (unsigned) CONST_DOUBLE_LOW (op) - 0xFFFFF000 < 0x1000)); | |
745 | #endif | |
746 | } | |
747 | ||
748 | int | |
749 | uns_arith_operand (op, mode) | |
750 | rtx op; | |
751 | enum machine_mode mode; | |
752 | { | |
753 | return register_operand (op, mode) || uns_small_int (op, mode); | |
754 | } | |
755 | ||
ab835497 RK |
756 | /* Return truth value of statement that OP is a call-clobbered register. */ |
757 | int | |
758 | clobbered_register (op, mode) | |
759 | rtx op; | |
760 | enum machine_mode mode; | |
761 | { | |
762 | return (GET_CODE (op) == REG && call_used_regs[REGNO (op)]); | |
763 | } | |
764 | \f | |
765 | /* X and Y are two things to compare using CODE. Emit the compare insn and | |
61a55e8b | 766 | return the rtx for the cc reg in the proper mode. */ |
ab835497 RK |
767 | |
768 | rtx | |
769 | gen_compare_reg (code, x, y) | |
770 | enum rtx_code code; | |
771 | rtx x, y; | |
772 | { | |
679655e6 | 773 | enum machine_mode mode = SELECT_CC_MODE (code, x, y); |
61a55e8b DE |
774 | rtx cc_reg; |
775 | ||
776 | /* ??? We don't have movcc patterns so we cannot generate pseudo regs for the | |
777 | fpcc regs (cse can't tell they're really call clobbered regs and will | |
778 | remove a duplicate comparison even if there is an intervening function | |
779 | call - it will then try to reload the cc reg via an int reg which is why | |
780 | we need the movcc patterns). It is possible to provide the movcc | |
781 | patterns by using the ldxfsr/stxfsr v9 insns. I tried it: you need two | |
782 | registers (say %g1,%g5) and it takes about 6 insns. A better fix would be | |
ddd5a7c1 | 783 | to tell cse that CCFPE mode registers (even pseudos) are call |
61a55e8b DE |
784 | clobbered. */ |
785 | ||
786 | /* ??? This is an experiment. Rather than making changes to cse which may | |
787 | or may not be easy/clean, we do our own cse. This is possible because | |
788 | we will generate hard registers. Cse knows they're call clobbered (it | |
789 | doesn't know the same thing about pseudos). If we guess wrong, no big | |
790 | deal, but if we win, great! */ | |
791 | ||
792 | if (TARGET_V9 && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) | |
793 | #if 1 /* experiment */ | |
794 | { | |
795 | int reg; | |
796 | /* We cycle through the registers to ensure they're all exercised. */ | |
797 | static int next_fpcc_reg = 0; | |
798 | /* Previous x,y for each fpcc reg. */ | |
799 | static rtx prev_args[4][2]; | |
800 | ||
801 | /* Scan prev_args for x,y. */ | |
802 | for (reg = 0; reg < 4; reg++) | |
803 | if (prev_args[reg][0] == x && prev_args[reg][1] == y) | |
804 | break; | |
805 | if (reg == 4) | |
806 | { | |
807 | reg = next_fpcc_reg; | |
808 | prev_args[reg][0] = x; | |
809 | prev_args[reg][1] = y; | |
810 | next_fpcc_reg = (next_fpcc_reg + 1) & 3; | |
811 | } | |
812 | cc_reg = gen_rtx (REG, mode, reg + 96); | |
813 | } | |
814 | #else | |
815 | cc_reg = gen_reg_rtx (mode); | |
816 | #endif /* ! experiment */ | |
817 | else | |
818 | cc_reg = gen_rtx (REG, mode, 0); | |
ab835497 RK |
819 | |
820 | emit_insn (gen_rtx (SET, VOIDmode, cc_reg, | |
821 | gen_rtx (COMPARE, mode, x, y))); | |
822 | ||
823 | return cc_reg; | |
824 | } | |
61a55e8b DE |
825 | |
826 | /* This function is used for v9 only. | |
827 | CODE is the code for an Scc's comparison. | |
828 | OPERANDS[0] is the target of the Scc insn. | |
829 | OPERANDS[1] is the value we compare against const0_rtx (which hasn't | |
830 | been generated yet). | |
831 | ||
832 | This function is needed to turn | |
833 | ||
834 | (set (reg:SI 110) | |
835 | (gt (reg:CCX 0 %g0) | |
836 | (const_int 0))) | |
837 | into | |
838 | (set (reg:SI 110) | |
839 | (gt:DI (reg:CCX 0 %g0) | |
840 | (const_int 0))) | |
841 | ||
842 | IE: The instruction recognizer needs to see the mode of the comparison to | |
843 | find the right instruction. We could use "gt:DI" right in the | |
844 | define_expand, but leaving it out allows us to handle DI, SI, etc. | |
845 | ||
846 | We refer to the global sparc compare operands sparc_compare_op0 and | |
847 | sparc_compare_op1. | |
848 | ||
849 | ??? Some of this is outdated as the scc insns set the mode of the | |
850 | comparison now. | |
851 | ||
852 | ??? We optimize for the case where op1 is 0 and the comparison allows us to | |
853 | use the "movrCC" insns. This reduces the generated code from three to two | |
854 | insns. This way seems too brute force though. Is there a more elegant way | |
855 | to achieve the same effect? | |
856 | ||
857 | Currently, this function always returns 1. ??? Can it ever fail? */ | |
858 | ||
859 | int | |
860 | gen_v9_scc (compare_code, operands) | |
861 | enum rtx_code compare_code; | |
862 | register rtx *operands; | |
863 | { | |
864 | rtx temp; | |
865 | ||
866 | if (GET_MODE_CLASS (GET_MODE (sparc_compare_op0)) == MODE_INT | |
867 | && sparc_compare_op1 == const0_rtx | |
868 | && (compare_code == EQ || compare_code == NE | |
869 | || compare_code == LT || compare_code == LE | |
870 | || compare_code == GT || compare_code == GE)) | |
871 | { | |
872 | /* Special case for op0 != 0. This can be done with one instruction if | |
873 | op0 can be clobbered. We store to a temp, and then clobber the temp, | |
874 | but the combiner will remove the first insn. */ | |
875 | ||
876 | if (compare_code == NE | |
877 | && GET_MODE (operands[0]) == DImode | |
878 | && GET_MODE (sparc_compare_op0) == DImode) | |
879 | { | |
880 | emit_insn (gen_rtx (SET, VOIDmode, operands[0], sparc_compare_op0)); | |
881 | emit_insn (gen_rtx (SET, VOIDmode, operands[0], | |
882 | gen_rtx (IF_THEN_ELSE, VOIDmode, | |
883 | gen_rtx (compare_code, DImode, | |
884 | sparc_compare_op0, const0_rtx), | |
885 | const1_rtx, | |
886 | operands[0]))); | |
887 | return 1; | |
888 | } | |
889 | ||
890 | emit_insn (gen_rtx (SET, VOIDmode, operands[0], const0_rtx)); | |
891 | if (GET_MODE (sparc_compare_op0) != DImode) | |
892 | { | |
893 | temp = gen_reg_rtx (DImode); | |
894 | convert_move (temp, sparc_compare_op0, 0); | |
895 | } | |
896 | else | |
897 | { | |
898 | temp = sparc_compare_op0; | |
899 | } | |
900 | emit_insn (gen_rtx (SET, VOIDmode, operands[0], | |
901 | gen_rtx (IF_THEN_ELSE, VOIDmode, | |
902 | gen_rtx (compare_code, DImode, | |
903 | temp, const0_rtx), | |
904 | const1_rtx, | |
905 | operands[0]))); | |
906 | return 1; | |
907 | } | |
908 | else | |
909 | { | |
910 | operands[1] = gen_compare_reg (compare_code, | |
911 | sparc_compare_op0, sparc_compare_op1); | |
912 | ||
913 | switch (GET_MODE (operands[1])) | |
914 | { | |
915 | case CCmode : | |
916 | case CCXmode : | |
917 | case CCFPEmode : | |
918 | case CCFPmode : | |
919 | break; | |
920 | default : | |
921 | abort (); | |
922 | } | |
923 | emit_insn (gen_rtx (SET, VOIDmode, operands[0], const0_rtx)); | |
924 | emit_insn (gen_rtx (SET, VOIDmode, operands[0], | |
925 | gen_rtx (IF_THEN_ELSE, VOIDmode, | |
926 | gen_rtx (compare_code, | |
927 | GET_MODE (operands[1]), | |
928 | operands[1], const0_rtx), | |
929 | const1_rtx, operands[0]))); | |
930 | return 1; | |
931 | } | |
932 | } | |
933 | ||
934 | /* Emit a conditional jump insn for the v9 architecture using comparison code | |
935 | CODE and jump target LABEL. | |
936 | This function exists to take advantage of the v9 brxx insns. */ | |
937 | ||
938 | void | |
939 | emit_v9_brxx_insn (code, op0, label) | |
940 | enum rtx_code code; | |
941 | rtx op0, label; | |
942 | { | |
943 | emit_jump_insn (gen_rtx (SET, VOIDmode, | |
944 | pc_rtx, | |
945 | gen_rtx (IF_THEN_ELSE, VOIDmode, | |
946 | gen_rtx (code, GET_MODE (op0), | |
947 | op0, const0_rtx), | |
948 | gen_rtx (LABEL_REF, VOIDmode, label), | |
949 | pc_rtx))); | |
950 | } | |
ab835497 RK |
951 | \f |
952 | /* Return nonzero if a return peephole merging return with | |
953 | setting of output register is ok. */ | |
954 | int | |
955 | leaf_return_peephole_ok () | |
956 | { | |
957 | return (actual_fsize == 0); | |
958 | } | |
959 | ||
960 | /* Return nonzero if TRIAL can go into the function epilogue's | |
961 | delay slot. SLOT is the slot we are trying to fill. */ | |
962 | ||
963 | int | |
964 | eligible_for_epilogue_delay (trial, slot) | |
965 | rtx trial; | |
966 | int slot; | |
967 | { | |
ab835497 RK |
968 | rtx pat, src; |
969 | ||
970 | if (slot >= 1) | |
971 | return 0; | |
972 | if (GET_CODE (trial) != INSN | |
973 | || GET_CODE (PATTERN (trial)) != SET) | |
974 | return 0; | |
975 | if (get_attr_length (trial) != 1) | |
976 | return 0; | |
977 | ||
915f619f JW |
978 | /* In the case of a true leaf function, anything can go into the delay slot. |
979 | A delay slot only exists however if the frame size is zero, otherwise | |
980 | we will put an insn to adjust the stack after the return. */ | |
ab835497 RK |
981 | if (leaf_function) |
982 | { | |
983 | if (leaf_return_peephole_ok ()) | |
7c56249d | 984 | return (get_attr_in_uncond_branch_delay (trial) == IN_BRANCH_DELAY_TRUE); |
ab835497 RK |
985 | return 0; |
986 | } | |
987 | ||
988 | /* Otherwise, only operations which can be done in tandem with | |
989 | a `restore' insn can go into the delay slot. */ | |
990 | pat = PATTERN (trial); | |
991 | if (GET_CODE (SET_DEST (pat)) != REG | |
992 | || REGNO (SET_DEST (pat)) == 0 | |
915f619f JW |
993 | || REGNO (SET_DEST (pat)) >= 32 |
994 | || REGNO (SET_DEST (pat)) < 24) | |
ab835497 | 995 | return 0; |
915f619f | 996 | |
ab835497 RK |
997 | src = SET_SRC (pat); |
998 | if (arith_operand (src, GET_MODE (src))) | |
999 | return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (SImode); | |
1000 | if (arith_double_operand (src, GET_MODE (src))) | |
1001 | return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode); | |
1002 | if (GET_CODE (src) == PLUS) | |
1003 | { | |
1004 | if (register_operand (XEXP (src, 0), SImode) | |
1005 | && arith_operand (XEXP (src, 1), SImode)) | |
1006 | return 1; | |
1007 | if (register_operand (XEXP (src, 1), SImode) | |
1008 | && arith_operand (XEXP (src, 0), SImode)) | |
1009 | return 1; | |
1010 | if (register_operand (XEXP (src, 0), DImode) | |
1011 | && arith_double_operand (XEXP (src, 1), DImode)) | |
1012 | return 1; | |
1013 | if (register_operand (XEXP (src, 1), DImode) | |
1014 | && arith_double_operand (XEXP (src, 0), DImode)) | |
1015 | return 1; | |
1016 | } | |
1017 | if (GET_CODE (src) == MINUS | |
1018 | && register_operand (XEXP (src, 0), SImode) | |
1019 | && small_int (XEXP (src, 1), VOIDmode)) | |
1020 | return 1; | |
1021 | if (GET_CODE (src) == MINUS | |
1022 | && register_operand (XEXP (src, 0), DImode) | |
1023 | && !register_operand (XEXP (src, 1), DImode) | |
1024 | && arith_double_operand (XEXP (src, 1), DImode)) | |
1025 | return 1; | |
1026 | return 0; | |
1027 | } | |
1028 | ||
1029 | int | |
1030 | short_branch (uid1, uid2) | |
1031 | int uid1, uid2; | |
1032 | { | |
1033 | unsigned int delta = insn_addresses[uid1] - insn_addresses[uid2]; | |
1034 | if (delta + 1024 < 2048) | |
1035 | return 1; | |
1036 | /* warning ("long branch, distance %d", delta); */ | |
1037 | return 0; | |
1038 | } | |
1039 | ||
1040 | /* Return non-zero if REG is not used after INSN. | |
1041 | We assume REG is a reload reg, and therefore does | |
1042 | not live past labels or calls or jumps. */ | |
1043 | int | |
1044 | reg_unused_after (reg, insn) | |
1045 | rtx reg; | |
1046 | rtx insn; | |
1047 | { | |
1048 | enum rtx_code code, prev_code = UNKNOWN; | |
1049 | ||
1050 | while (insn = NEXT_INSN (insn)) | |
1051 | { | |
1052 | if (prev_code == CALL_INSN && call_used_regs[REGNO (reg)]) | |
1053 | return 1; | |
1054 | ||
1055 | code = GET_CODE (insn); | |
1056 | if (GET_CODE (insn) == CODE_LABEL) | |
1057 | return 1; | |
1058 | ||
1059 | if (GET_RTX_CLASS (code) == 'i') | |
1060 | { | |
1061 | rtx set = single_set (insn); | |
1062 | int in_src = set && reg_overlap_mentioned_p (reg, SET_SRC (set)); | |
1063 | if (set && in_src) | |
1064 | return 0; | |
1065 | if (set && reg_overlap_mentioned_p (reg, SET_DEST (set))) | |
1066 | return 1; | |
1067 | if (set == 0 && reg_overlap_mentioned_p (reg, PATTERN (insn))) | |
1068 | return 0; | |
1069 | } | |
1070 | prev_code = code; | |
1071 | } | |
1072 | return 1; | |
1073 | } | |
1074 | \f | |
6a4bb1fa DE |
1075 | /* The rtx for the global offset table which is a special form |
1076 | that *is* a position independent symbolic constant. */ | |
1077 | static rtx pic_pc_rtx; | |
1078 | ||
1079 | /* Ensure that we are not using patterns that are not OK with PIC. */ | |
1080 | ||
1081 | int | |
1082 | check_pic (i) | |
1083 | int i; | |
1084 | { | |
1085 | switch (flag_pic) | |
1086 | { | |
1087 | case 1: | |
1088 | if (GET_CODE (recog_operand[i]) == SYMBOL_REF | |
1089 | || (GET_CODE (recog_operand[i]) == CONST | |
1090 | && ! rtx_equal_p (pic_pc_rtx, recog_operand[i]))) | |
1091 | abort (); | |
1092 | case 2: | |
1093 | default: | |
1094 | return 1; | |
1095 | } | |
1096 | } | |
1097 | ||
1098 | /* Return true if X is an address which needs a temporary register when | |
1099 | reloaded while generating PIC code. */ | |
1100 | ||
1101 | int | |
1102 | pic_address_needs_scratch (x) | |
1103 | rtx x; | |
1104 | { | |
1105 | /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */ | |
1106 | if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS | |
1107 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF | |
1108 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT | |
1109 | && ! SMALL_INT (XEXP (XEXP (x, 0), 1))) | |
1110 | return 1; | |
1111 | ||
1112 | return 0; | |
1113 | } | |
1114 | ||
ab835497 RK |
1115 | /* Legitimize PIC addresses. If the address is already position-independent, |
1116 | we return ORIG. Newly generated position-independent addresses go into a | |
1117 | reg. This is REG if non zero, otherwise we allocate register(s) as | |
7e2feebf | 1118 | necessary. */ |
ab835497 RK |
1119 | |
1120 | rtx | |
7e2feebf | 1121 | legitimize_pic_address (orig, mode, reg) |
ab835497 RK |
1122 | rtx orig; |
1123 | enum machine_mode mode; | |
7e2feebf | 1124 | rtx reg; |
ab835497 RK |
1125 | { |
1126 | if (GET_CODE (orig) == SYMBOL_REF) | |
1127 | { | |
1128 | rtx pic_ref, address; | |
1129 | rtx insn; | |
1130 | ||
1131 | if (reg == 0) | |
1132 | { | |
01c0e9dc | 1133 | if (reload_in_progress || reload_completed) |
ab835497 RK |
1134 | abort (); |
1135 | else | |
1136 | reg = gen_reg_rtx (Pmode); | |
1137 | } | |
1138 | ||
1139 | if (flag_pic == 2) | |
1140 | { | |
1141 | /* If not during reload, allocate another temp reg here for loading | |
1142 | in the address, so that these instructions can be optimized | |
1143 | properly. */ | |
01c0e9dc JW |
1144 | rtx temp_reg = ((reload_in_progress || reload_completed) |
1145 | ? reg : gen_reg_rtx (Pmode)); | |
ab835497 | 1146 | |
b4ac57ab RS |
1147 | /* Must put the SYMBOL_REF inside an UNSPEC here so that cse |
1148 | won't get confused into thinking that these two instructions | |
1149 | are loading in the true address of the symbol. If in the | |
1150 | future a PIC rtx exists, that should be used instead. */ | |
ab835497 | 1151 | emit_insn (gen_rtx (SET, VOIDmode, temp_reg, |
b4ac57ab RS |
1152 | gen_rtx (HIGH, Pmode, |
1153 | gen_rtx (UNSPEC, Pmode, | |
1154 | gen_rtvec (1, orig), | |
1155 | 0)))); | |
ab835497 | 1156 | emit_insn (gen_rtx (SET, VOIDmode, temp_reg, |
b4ac57ab RS |
1157 | gen_rtx (LO_SUM, Pmode, temp_reg, |
1158 | gen_rtx (UNSPEC, Pmode, | |
1159 | gen_rtvec (1, orig), | |
1160 | 0)))); | |
ab835497 RK |
1161 | address = temp_reg; |
1162 | } | |
1163 | else | |
1164 | address = orig; | |
1165 | ||
1166 | pic_ref = gen_rtx (MEM, Pmode, | |
1167 | gen_rtx (PLUS, Pmode, | |
1168 | pic_offset_table_rtx, address)); | |
1169 | current_function_uses_pic_offset_table = 1; | |
1170 | RTX_UNCHANGING_P (pic_ref) = 1; | |
1171 | insn = emit_move_insn (reg, pic_ref); | |
1172 | /* Put a REG_EQUAL note on this insn, so that it can be optimized | |
1173 | by loop. */ | |
1174 | REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_EQUAL, orig, | |
1175 | REG_NOTES (insn)); | |
1176 | return reg; | |
1177 | } | |
1178 | else if (GET_CODE (orig) == CONST) | |
1179 | { | |
1180 | rtx base, offset; | |
1181 | ||
1182 | if (GET_CODE (XEXP (orig, 0)) == PLUS | |
1183 | && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx) | |
1184 | return orig; | |
1185 | ||
1186 | if (reg == 0) | |
1187 | { | |
01c0e9dc | 1188 | if (reload_in_progress || reload_completed) |
ab835497 RK |
1189 | abort (); |
1190 | else | |
1191 | reg = gen_reg_rtx (Pmode); | |
1192 | } | |
1193 | ||
1194 | if (GET_CODE (XEXP (orig, 0)) == PLUS) | |
1195 | { | |
7e2feebf | 1196 | base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg); |
ab835497 | 1197 | offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode, |
7e2feebf | 1198 | base == reg ? 0 : reg); |
ab835497 RK |
1199 | } |
1200 | else | |
1201 | abort (); | |
1202 | ||
1203 | if (GET_CODE (offset) == CONST_INT) | |
1204 | { | |
1205 | if (SMALL_INT (offset)) | |
1206 | return plus_constant_for_output (base, INTVAL (offset)); | |
01c0e9dc | 1207 | else if (! reload_in_progress && ! reload_completed) |
ab835497 | 1208 | offset = force_reg (Pmode, offset); |
ab835497 | 1209 | else |
7e2feebf | 1210 | /* If we reach here, then something is seriously wrong. */ |
ab835497 RK |
1211 | abort (); |
1212 | } | |
1213 | return gen_rtx (PLUS, Pmode, base, offset); | |
1214 | } | |
1215 | else if (GET_CODE (orig) == LABEL_REF) | |
1216 | current_function_uses_pic_offset_table = 1; | |
1217 | ||
1218 | return orig; | |
1219 | } | |
1220 | ||
1221 | /* Set up PIC-specific rtl. This should not cause any insns | |
1222 | to be emitted. */ | |
1223 | ||
1224 | void | |
1225 | initialize_pic () | |
1226 | { | |
1227 | } | |
1228 | ||
1229 | /* Emit special PIC prologues and epilogues. */ | |
1230 | ||
1231 | void | |
1232 | finalize_pic () | |
1233 | { | |
1234 | /* The table we use to reference PIC data. */ | |
1235 | rtx global_offset_table; | |
1236 | /* Labels to get the PC in the prologue of this function. */ | |
1237 | rtx l1, l2; | |
1238 | rtx seq; | |
1239 | int orig_flag_pic = flag_pic; | |
1240 | ||
1241 | if (current_function_uses_pic_offset_table == 0) | |
1242 | return; | |
1243 | ||
1244 | if (! flag_pic) | |
1245 | abort (); | |
1246 | ||
1247 | flag_pic = 0; | |
1248 | l1 = gen_label_rtx (); | |
1249 | l2 = gen_label_rtx (); | |
1250 | ||
1251 | start_sequence (); | |
1252 | ||
1253 | emit_label (l1); | |
1254 | /* Note that we pun calls and jumps here! */ | |
1255 | emit_jump_insn (gen_rtx (PARALLEL, VOIDmode, | |
1256 | gen_rtvec (2, | |
1257 | gen_rtx (SET, VOIDmode, pc_rtx, gen_rtx (LABEL_REF, VOIDmode, l2)), | |
1258 | gen_rtx (SET, VOIDmode, gen_rtx (REG, SImode, 15), gen_rtx (LABEL_REF, VOIDmode, l2))))); | |
1259 | emit_label (l2); | |
1260 | ||
1261 | /* Initialize every time through, since we can't easily | |
1262 | know this to be permanent. */ | |
c4eb2bd7 | 1263 | global_offset_table = gen_rtx (SYMBOL_REF, Pmode, "_GLOBAL_OFFSET_TABLE_"); |
ab835497 RK |
1264 | pic_pc_rtx = gen_rtx (CONST, Pmode, |
1265 | gen_rtx (MINUS, Pmode, | |
1266 | global_offset_table, | |
1267 | gen_rtx (CONST, Pmode, | |
1268 | gen_rtx (MINUS, Pmode, | |
1269 | gen_rtx (LABEL_REF, VOIDmode, l1), | |
1270 | pc_rtx)))); | |
1271 | ||
61a55e8b DE |
1272 | if (Pmode == DImode) |
1273 | emit_insn (gen_rtx (PARALLEL, VOIDmode, | |
1274 | gen_rtvec (2, | |
1275 | gen_rtx (SET, VOIDmode, pic_offset_table_rtx, | |
1276 | gen_rtx (HIGH, Pmode, pic_pc_rtx)), | |
1277 | gen_rtx (CLOBBER, VOIDmode, gen_rtx (REG, Pmode, 1))))); | |
1278 | else | |
1279 | emit_insn (gen_rtx (SET, VOIDmode, pic_offset_table_rtx, | |
1280 | gen_rtx (HIGH, Pmode, pic_pc_rtx))); | |
1281 | ||
ab835497 RK |
1282 | emit_insn (gen_rtx (SET, VOIDmode, |
1283 | pic_offset_table_rtx, | |
1284 | gen_rtx (LO_SUM, Pmode, | |
1285 | pic_offset_table_rtx, pic_pc_rtx))); | |
1286 | emit_insn (gen_rtx (SET, VOIDmode, | |
1287 | pic_offset_table_rtx, | |
1288 | gen_rtx (PLUS, Pmode, | |
1289 | pic_offset_table_rtx, gen_rtx (REG, Pmode, 15)))); | |
1290 | /* emit_insn (gen_rtx (ASM_INPUT, VOIDmode, "!#PROLOGUE# 1")); */ | |
1291 | LABEL_PRESERVE_P (l1) = 1; | |
1292 | LABEL_PRESERVE_P (l2) = 1; | |
1293 | flag_pic = orig_flag_pic; | |
1294 | ||
1295 | seq = gen_sequence (); | |
1296 | end_sequence (); | |
1297 | emit_insn_after (seq, get_insns ()); | |
1298 | ||
1299 | /* Need to emit this whether or not we obey regdecls, | |
1300 | since setjmp/longjmp can cause life info to screw up. */ | |
1301 | emit_insn (gen_rtx (USE, VOIDmode, pic_offset_table_rtx)); | |
1302 | } | |
1303 | \f | |
ab835497 RK |
1304 | /* Emit insns to move operands[1] into operands[0]. |
1305 | ||
1306 | Return 1 if we have written out everything that needs to be done to | |
1307 | do the move. Otherwise, return 0 and the caller will emit the move | |
7e2feebf | 1308 | normally. */ |
ab835497 RK |
1309 | |
1310 | int | |
7e2feebf | 1311 | emit_move_sequence (operands, mode) |
ab835497 RK |
1312 | rtx *operands; |
1313 | enum machine_mode mode; | |
ab835497 RK |
1314 | { |
1315 | register rtx operand0 = operands[0]; | |
1316 | register rtx operand1 = operands[1]; | |
1317 | ||
7e2feebf JW |
1318 | if (CONSTANT_P (operand1) && flag_pic |
1319 | && pic_address_needs_scratch (operand1)) | |
1320 | operands[1] = operand1 = legitimize_pic_address (operand1, mode, 0); | |
1321 | ||
ab835497 RK |
1322 | /* Handle most common case first: storing into a register. */ |
1323 | if (register_operand (operand0, mode)) | |
1324 | { | |
1325 | if (register_operand (operand1, mode) | |
1326 | || (GET_CODE (operand1) == CONST_INT && SMALL_INT (operand1)) | |
1327 | || (GET_CODE (operand1) == CONST_DOUBLE | |
1328 | && arith_double_operand (operand1, DImode)) | |
1329 | || (GET_CODE (operand1) == HIGH && GET_MODE (operand1) != DImode) | |
1330 | /* Only `general_operands' can come here, so MEM is ok. */ | |
1331 | || GET_CODE (operand1) == MEM) | |
1332 | { | |
1333 | /* Run this case quickly. */ | |
1334 | emit_insn (gen_rtx (SET, VOIDmode, operand0, operand1)); | |
1335 | return 1; | |
1336 | } | |
1337 | } | |
1338 | else if (GET_CODE (operand0) == MEM) | |
1339 | { | |
1340 | if (register_operand (operand1, mode) || operand1 == const0_rtx) | |
1341 | { | |
1342 | /* Run this case quickly. */ | |
1343 | emit_insn (gen_rtx (SET, VOIDmode, operand0, operand1)); | |
1344 | return 1; | |
1345 | } | |
1346 | if (! reload_in_progress) | |
1347 | { | |
1348 | operands[0] = validize_mem (operand0); | |
1349 | operands[1] = operand1 = force_reg (mode, operand1); | |
1350 | } | |
1351 | } | |
1352 | ||
1353 | /* Simplify the source if we need to. Must handle DImode HIGH operators | |
1354 | here because such a move needs a clobber added. */ | |
1355 | if ((GET_CODE (operand1) != HIGH && immediate_operand (operand1, mode)) | |
1356 | || (GET_CODE (operand1) == HIGH && GET_MODE (operand1) == DImode)) | |
1357 | { | |
1358 | if (flag_pic && symbolic_operand (operand1, mode)) | |
1359 | { | |
1360 | rtx temp_reg = reload_in_progress ? operand0 : 0; | |
1361 | ||
7e2feebf | 1362 | operands[1] = legitimize_pic_address (operand1, mode, temp_reg); |
ab835497 RK |
1363 | } |
1364 | else if (GET_CODE (operand1) == CONST_INT | |
1365 | ? (! SMALL_INT (operand1) | |
1366 | && (INTVAL (operand1) & 0x3ff) != 0) | |
1367 | : (GET_CODE (operand1) == CONST_DOUBLE | |
1368 | ? ! arith_double_operand (operand1, DImode) | |
1369 | : 1)) | |
1370 | { | |
1371 | /* For DImode values, temp must be operand0 because of the way | |
1372 | HI and LO_SUM work. The LO_SUM operator only copies half of | |
1373 | the LSW from the dest of the HI operator. If the LO_SUM dest is | |
1374 | not the same as the HI dest, then the MSW of the LO_SUM dest will | |
1375 | never be set. | |
1376 | ||
1377 | ??? The real problem here is that the ...(HI:DImode pattern emits | |
1378 | multiple instructions, and the ...(LO_SUM:DImode pattern emits | |
1379 | one instruction. This fails, because the compiler assumes that | |
1380 | LO_SUM copies all bits of the first operand to its dest. Better | |
1381 | would be to have the HI pattern emit one instruction and the | |
1382 | LO_SUM pattern multiple instructions. Even better would be | |
1383 | to use four rtl insns. */ | |
1384 | rtx temp = ((reload_in_progress || mode == DImode) | |
1385 | ? operand0 : gen_reg_rtx (mode)); | |
1386 | ||
61a55e8b DE |
1387 | if (TARGET_V9 && mode == DImode) |
1388 | { | |
1389 | int high_operand = 0; | |
1390 | ||
1391 | /* If the operand is already a HIGH, then remove the HIGH so | |
1392 | that we won't get duplicate HIGH operators in this insn. | |
1393 | Also, we must store the result into the original dest, | |
1394 | because that is where the following LO_SUM expects it. */ | |
1395 | if (GET_CODE (operand1) == HIGH) | |
1396 | { | |
1397 | operand1 = XEXP (operand1, 0); | |
1398 | high_operand = 1; | |
1399 | } | |
1400 | ||
1401 | emit_insn (gen_rtx (PARALLEL, VOIDmode, | |
1402 | gen_rtvec (2, | |
1403 | gen_rtx (SET, VOIDmode, temp, | |
1404 | gen_rtx (HIGH, mode, operand1)), | |
1405 | gen_rtx (CLOBBER, VOIDmode, gen_rtx (REG, DImode, 1))))); | |
1406 | ||
1407 | /* If this was a high operand, then we are now finished. */ | |
1408 | if (high_operand) | |
1409 | return 1; | |
1410 | } | |
1411 | else | |
1412 | emit_insn (gen_rtx (SET, VOIDmode, temp, | |
1413 | gen_rtx (HIGH, mode, operand1))); | |
1414 | ||
ab835497 RK |
1415 | operands[1] = gen_rtx (LO_SUM, mode, temp, operand1); |
1416 | } | |
1417 | } | |
1418 | ||
1419 | if (GET_CODE (operand1) == LABEL_REF && flag_pic) | |
1420 | { | |
1421 | /* The procedure for doing this involves using a call instruction to | |
1422 | get the pc into o7. We need to indicate this explicitly because | |
1423 | the tablejump pattern assumes that it can use this value also. */ | |
1424 | emit_insn (gen_rtx (PARALLEL, VOIDmode, | |
1425 | gen_rtvec (2, | |
1426 | gen_rtx (SET, VOIDmode, operand0, | |
1427 | operand1), | |
1428 | gen_rtx (SET, VOIDmode, | |
1429 | gen_rtx (REG, mode, 15), | |
1430 | pc_rtx)))); | |
1431 | return 1; | |
1432 | } | |
1433 | ||
1434 | /* Now have insn-emit do whatever it normally does. */ | |
1435 | return 0; | |
1436 | } | |
1437 | \f | |
1438 | /* Return the best assembler insn template | |
1439 | for moving operands[1] into operands[0] as a fullword. */ | |
1440 | ||
1441 | char * | |
1442 | singlemove_string (operands) | |
1443 | rtx *operands; | |
1444 | { | |
1445 | if (GET_CODE (operands[0]) == MEM) | |
1446 | { | |
1447 | if (GET_CODE (operands[1]) != MEM) | |
1448 | return "st %r1,%0"; | |
1449 | else | |
1450 | abort (); | |
1451 | } | |
2b9a9aea | 1452 | else if (GET_CODE (operands[1]) == MEM) |
ab835497 | 1453 | return "ld %1,%0"; |
2b9a9aea JW |
1454 | else if (GET_CODE (operands[1]) == CONST_DOUBLE) |
1455 | { | |
c90fb4e6 JW |
1456 | REAL_VALUE_TYPE r; |
1457 | long i; | |
2b9a9aea JW |
1458 | |
1459 | /* Must be SFmode, otherwise this doesn't make sense. */ | |
1460 | if (GET_MODE (operands[1]) != SFmode) | |
1461 | abort (); | |
1462 | ||
c90fb4e6 JW |
1463 | REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]); |
1464 | REAL_VALUE_TO_TARGET_SINGLE (r, i); | |
2b9a9aea JW |
1465 | operands[1] = gen_rtx (CONST_INT, VOIDmode, i); |
1466 | ||
1467 | if (CONST_OK_FOR_LETTER_P (i, 'I')) | |
1468 | return "mov %1,%0"; | |
1469 | else if ((i & 0x000003FF) != 0) | |
1470 | return "sethi %%hi(%a1),%0\n\tor %0,%%lo(%a1),%0"; | |
1471 | else | |
1472 | return "sethi %%hi(%a1),%0"; | |
1473 | } | |
1474 | else if (GET_CODE (operands[1]) == CONST_INT | |
1475 | && ! CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'I')) | |
ab835497 RK |
1476 | { |
1477 | int i = INTVAL (operands[1]); | |
1478 | ||
915f619f | 1479 | /* If all low order 10 bits are clear, then we only need a single |
ab835497 | 1480 | sethi insn to load the constant. */ |
915f619f | 1481 | if ((i & 0x000003FF) != 0) |
ab835497 RK |
1482 | return "sethi %%hi(%a1),%0\n\tor %0,%%lo(%a1),%0"; |
1483 | else | |
1484 | return "sethi %%hi(%a1),%0"; | |
1485 | } | |
2b9a9aea | 1486 | /* Operand 1 must be a register, or a 'I' type CONST_INT. */ |
ab835497 RK |
1487 | return "mov %1,%0"; |
1488 | } | |
1489 | \f | |
795068a4 JW |
1490 | /* Return non-zero if it is OK to assume that the given memory operand is |
1491 | aligned at least to a 8-byte boundary. This should only be called | |
1492 | for memory accesses whose size is 8 bytes or larger. */ | |
1493 | ||
7c56249d | 1494 | int |
795068a4 JW |
1495 | mem_aligned_8 (mem) |
1496 | register rtx mem; | |
1497 | { | |
1498 | register rtx addr; | |
1499 | register rtx base; | |
1500 | register rtx offset; | |
1501 | ||
1502 | if (GET_CODE (mem) != MEM) | |
7c56249d | 1503 | return 0; /* It's gotta be a MEM! */ |
795068a4 JW |
1504 | |
1505 | addr = XEXP (mem, 0); | |
1506 | ||
795068a4 | 1507 | /* Now that all misaligned double parms are copied on function entry, |
1934ceca JW |
1508 | we can assume any 64-bit object is 64-bit aligned except those which |
1509 | are at unaligned offsets from the stack or frame pointer. If the | |
1510 | TARGET_UNALIGNED_DOUBLES switch is given, we do not make this | |
1511 | assumption. */ | |
795068a4 JW |
1512 | |
1513 | /* See what register we use in the address. */ | |
1514 | base = 0; | |
1515 | if (GET_CODE (addr) == PLUS) | |
1516 | { | |
1517 | if (GET_CODE (XEXP (addr, 0)) == REG | |
1518 | && GET_CODE (XEXP (addr, 1)) == CONST_INT) | |
1519 | { | |
1520 | base = XEXP (addr, 0); | |
1521 | offset = XEXP (addr, 1); | |
1522 | } | |
1523 | } | |
1524 | else if (GET_CODE (addr) == REG) | |
1525 | { | |
1526 | base = addr; | |
1527 | offset = const0_rtx; | |
1528 | } | |
1529 | ||
1530 | /* If it's the stack or frame pointer, check offset alignment. | |
2296cba3 | 1531 | We can have improper alignment in the function entry code. */ |
795068a4 JW |
1532 | if (base |
1533 | && (REGNO (base) == FRAME_POINTER_REGNUM | |
1534 | || REGNO (base) == STACK_POINTER_REGNUM)) | |
1535 | { | |
61a55e8b | 1536 | if (((INTVAL (offset) - SPARC_STACK_BIAS) & 0x7) == 0) |
795068a4 JW |
1537 | return 1; |
1538 | } | |
1934ceca JW |
1539 | /* Anything else we know is properly aligned unless TARGET_UNALIGNED_DOUBLES |
1540 | is true, in which case we can only assume that an access is aligned if | |
f5da225e JW |
1541 | it is to a constant address, or the address involves a LO_SUM. |
1542 | ||
1543 | We used to assume an address was aligned if MEM_IN_STRUCT_P was true. | |
1544 | That assumption was deleted so that gcc generated code can be used with | |
1545 | memory allocators that only guarantee 4 byte alignment. */ | |
1546 | else if (! TARGET_UNALIGNED_DOUBLES || CONSTANT_P (addr) | |
1547 | || GET_CODE (addr) == LO_SUM) | |
795068a4 | 1548 | return 1; |
795068a4 JW |
1549 | |
1550 | /* An obviously unaligned address. */ | |
1551 | return 0; | |
1552 | } | |
1553 | ||
1554 | enum optype { REGOP, OFFSOP, MEMOP, PUSHOP, POPOP, CNSTOP, RNDOP }; | |
1555 | ||
ab835497 | 1556 | /* Output assembler code to perform a doubleword move insn |
795068a4 JW |
1557 | with operands OPERANDS. This is very similar to the following |
1558 | output_move_quad function. */ | |
ab835497 RK |
1559 | |
1560 | char * | |
1561 | output_move_double (operands) | |
1562 | rtx *operands; | |
1563 | { | |
795068a4 JW |
1564 | register rtx op0 = operands[0]; |
1565 | register rtx op1 = operands[1]; | |
1566 | register enum optype optype0; | |
1567 | register enum optype optype1; | |
ab835497 | 1568 | rtx latehalf[2]; |
795068a4 JW |
1569 | rtx addreg0 = 0; |
1570 | rtx addreg1 = 0; | |
3b76513a | 1571 | int highest_first = 0; |
f3a9d1e6 | 1572 | int no_addreg1_decrement = 0; |
ab835497 RK |
1573 | |
1574 | /* First classify both operands. */ | |
1575 | ||
795068a4 | 1576 | if (REG_P (op0)) |
ab835497 | 1577 | optype0 = REGOP; |
795068a4 | 1578 | else if (offsettable_memref_p (op0)) |
ab835497 | 1579 | optype0 = OFFSOP; |
795068a4 | 1580 | else if (GET_CODE (op0) == MEM) |
ab835497 RK |
1581 | optype0 = MEMOP; |
1582 | else | |
1583 | optype0 = RNDOP; | |
1584 | ||
795068a4 | 1585 | if (REG_P (op1)) |
ab835497 | 1586 | optype1 = REGOP; |
795068a4 | 1587 | else if (CONSTANT_P (op1)) |
ab835497 | 1588 | optype1 = CNSTOP; |
795068a4 | 1589 | else if (offsettable_memref_p (op1)) |
ab835497 | 1590 | optype1 = OFFSOP; |
795068a4 | 1591 | else if (GET_CODE (op1) == MEM) |
ab835497 RK |
1592 | optype1 = MEMOP; |
1593 | else | |
1594 | optype1 = RNDOP; | |
1595 | ||
1596 | /* Check for the cases that the operand constraints are not | |
1597 | supposed to allow to happen. Abort if we get one, | |
1598 | because generating code for these cases is painful. */ | |
1599 | ||
795068a4 JW |
1600 | if (optype0 == RNDOP || optype1 == RNDOP |
1601 | || (optype0 == MEM && optype1 == MEM)) | |
ab835497 RK |
1602 | abort (); |
1603 | ||
1604 | /* If an operand is an unoffsettable memory ref, find a register | |
1605 | we can increment temporarily to make it refer to the second word. */ | |
1606 | ||
1607 | if (optype0 == MEMOP) | |
795068a4 | 1608 | addreg0 = find_addr_reg (XEXP (op0, 0)); |
ab835497 RK |
1609 | |
1610 | if (optype1 == MEMOP) | |
795068a4 | 1611 | addreg1 = find_addr_reg (XEXP (op1, 0)); |
ab835497 RK |
1612 | |
1613 | /* Ok, we can do one word at a time. | |
795068a4 | 1614 | Set up in LATEHALF the operands to use for the |
ab835497 RK |
1615 | high-numbered (least significant) word and in some cases alter the |
1616 | operands in OPERANDS to be suitable for the low-numbered word. */ | |
1617 | ||
1618 | if (optype0 == REGOP) | |
795068a4 | 1619 | latehalf[0] = gen_rtx (REG, SImode, REGNO (op0) + 1); |
ab835497 | 1620 | else if (optype0 == OFFSOP) |
795068a4 | 1621 | latehalf[0] = adj_offsettable_operand (op0, 4); |
ab835497 | 1622 | else |
795068a4 | 1623 | latehalf[0] = op0; |
ab835497 RK |
1624 | |
1625 | if (optype1 == REGOP) | |
795068a4 | 1626 | latehalf[1] = gen_rtx (REG, SImode, REGNO (op1) + 1); |
ab835497 | 1627 | else if (optype1 == OFFSOP) |
795068a4 | 1628 | latehalf[1] = adj_offsettable_operand (op1, 4); |
ab835497 | 1629 | else if (optype1 == CNSTOP) |
61a55e8b DE |
1630 | { |
1631 | if (TARGET_V9) | |
1632 | { | |
1633 | if (arith_double_operand (op1, DImode)) | |
1634 | { | |
1635 | operands[1] = gen_rtx (CONST_INT, VOIDmode, | |
1636 | CONST_DOUBLE_LOW (op1)); | |
1637 | return "mov %1,%0"; | |
1638 | } | |
1639 | else | |
1640 | { | |
1641 | /* The only way to handle CONST_DOUBLEs or other 64 bit | |
1642 | constants here is to use a temporary, such as is done | |
1643 | for the V9 DImode sethi insn pattern. This is not | |
1644 | a practical solution, so abort if we reach here. | |
1645 | The md file should always force such constants to | |
1646 | memory. */ | |
1647 | abort (); | |
1648 | } | |
1649 | } | |
1650 | else | |
1651 | split_double (op1, &operands[1], &latehalf[1]); | |
1652 | } | |
ab835497 | 1653 | else |
795068a4 | 1654 | latehalf[1] = op1; |
ab835497 | 1655 | |
795068a4 JW |
1656 | /* Easy case: try moving both words at once. Check for moving between |
1657 | an even/odd register pair and a memory location. */ | |
ab835497 | 1658 | if ((optype0 == REGOP && optype1 != REGOP && optype1 != CNSTOP |
61a55e8b | 1659 | && (TARGET_V9 || (REGNO (op0) & 1) == 0)) |
ab835497 | 1660 | || (optype0 != REGOP && optype0 != CNSTOP && optype1 == REGOP |
61a55e8b | 1661 | && (TARGET_V9 || (REGNO (op1) & 1) == 0))) |
ab835497 | 1662 | { |
61a55e8b | 1663 | register rtx mem,reg; |
bc961ed7 RS |
1664 | |
1665 | if (optype0 == REGOP) | |
61a55e8b | 1666 | mem = op1, reg = op0; |
bc961ed7 | 1667 | else |
61a55e8b DE |
1668 | mem = op0, reg = op1; |
1669 | ||
1670 | /* In v9, ldd can be used for word aligned addresses, so technically | |
1671 | some of this logic is unneeded. We still avoid ldd if the address | |
1672 | is obviously unaligned though. */ | |
1673 | ||
1674 | if (mem_aligned_8 (mem) | |
1675 | /* If this is a floating point register higher than %f31, | |
1676 | then we *must* use an aligned load, since `ld' will not accept | |
1677 | the register number. */ | |
1678 | || (TARGET_V9 && REGNO (reg) >= 64)) | |
1679 | { | |
1680 | if (FP_REG_P (reg) || ! TARGET_V9) | |
1681 | return (mem == op1 ? "ldd %1,%0" : "std %1,%0"); | |
1682 | else | |
1683 | return (mem == op1 ? "ldx %1,%0" : "stx %1,%0"); | |
1684 | } | |
1685 | } | |
bc961ed7 | 1686 | |
61a55e8b DE |
1687 | if (TARGET_V9) |
1688 | { | |
1689 | if (optype0 == REGOP && optype1 == REGOP) | |
1690 | { | |
1691 | if (FP_REG_P (op0)) | |
1692 | return "fmovd %1,%0"; | |
1693 | else | |
1694 | return "mov %1,%0"; | |
1695 | } | |
ab835497 RK |
1696 | } |
1697 | ||
795068a4 JW |
1698 | /* If the first move would clobber the source of the second one, |
1699 | do them in the other order. */ | |
1700 | ||
1701 | /* Overlapping registers. */ | |
ab835497 | 1702 | if (optype0 == REGOP && optype1 == REGOP |
795068a4 | 1703 | && REGNO (op0) == REGNO (latehalf[1])) |
ab835497 | 1704 | { |
ab835497 RK |
1705 | /* Do that word. */ |
1706 | output_asm_insn (singlemove_string (latehalf), latehalf); | |
ab835497 RK |
1707 | /* Do low-numbered word. */ |
1708 | return singlemove_string (operands); | |
1709 | } | |
795068a4 | 1710 | /* Loading into a register which overlaps a register used in the address. */ |
ab835497 | 1711 | else if (optype0 == REGOP && optype1 != REGOP |
795068a4 | 1712 | && reg_overlap_mentioned_p (op0, op1)) |
ab835497 | 1713 | { |
f3a9d1e6 JW |
1714 | /* If both halves of dest are used in the src memory address, |
1715 | add the two regs and put them in the low reg (op0). | |
1716 | Then it works to load latehalf first. */ | |
bdec790c RS |
1717 | if (reg_mentioned_p (op0, XEXP (op1, 0)) |
1718 | && reg_mentioned_p (latehalf[0], XEXP (op1, 0))) | |
1719 | { | |
bdec790c RS |
1720 | rtx xops[2]; |
1721 | xops[0] = latehalf[0]; | |
1722 | xops[1] = op0; | |
1723 | output_asm_insn ("add %1,%0,%1", xops); | |
3b76513a | 1724 | operands[1] = gen_rtx (MEM, DImode, op0); |
bdec790c | 1725 | latehalf[1] = adj_offsettable_operand (operands[1], 4); |
3b76513a | 1726 | addreg1 = 0; |
f3a9d1e6 | 1727 | highest_first = 1; |
bdec790c | 1728 | } |
f3a9d1e6 JW |
1729 | /* Only one register in the dest is used in the src memory address, |
1730 | and this is the first register of the dest, so we want to do | |
1731 | the late half first here also. */ | |
1732 | else if (! reg_mentioned_p (latehalf[0], XEXP (op1, 0))) | |
1733 | highest_first = 1; | |
1734 | /* Only one register in the dest is used in the src memory address, | |
1735 | and this is the second register of the dest, so we want to do | |
1736 | the late half last. If addreg1 is set, and addreg1 is the same | |
1737 | register as latehalf, then we must suppress the trailing decrement, | |
1738 | because it would clobber the value just loaded. */ | |
1739 | else if (addreg1 && reg_mentioned_p (addreg1, latehalf[0])) | |
1740 | no_addreg1_decrement = 1; | |
ab835497 RK |
1741 | } |
1742 | ||
3b76513a RS |
1743 | /* Normal case: do the two words, low-numbered first. |
1744 | Overlap case (highest_first set): do high-numbered word first. */ | |
ab835497 | 1745 | |
3b76513a RS |
1746 | if (! highest_first) |
1747 | output_asm_insn (singlemove_string (operands), operands); | |
ab835497 RK |
1748 | |
1749 | /* Make any unoffsettable addresses point at high-numbered word. */ | |
1750 | if (addreg0) | |
1751 | output_asm_insn ("add %0,0x4,%0", &addreg0); | |
1752 | if (addreg1) | |
1753 | output_asm_insn ("add %0,0x4,%0", &addreg1); | |
1754 | ||
1755 | /* Do that word. */ | |
1756 | output_asm_insn (singlemove_string (latehalf), latehalf); | |
1757 | ||
1758 | /* Undo the adds we just did. */ | |
1759 | if (addreg0) | |
1760 | output_asm_insn ("add %0,-0x4,%0", &addreg0); | |
f3a9d1e6 | 1761 | if (addreg1 && ! no_addreg1_decrement) |
ab835497 RK |
1762 | output_asm_insn ("add %0,-0x4,%0", &addreg1); |
1763 | ||
3b76513a RS |
1764 | if (highest_first) |
1765 | output_asm_insn (singlemove_string (operands), operands); | |
1766 | ||
ab835497 RK |
1767 | return ""; |
1768 | } | |
795068a4 JW |
1769 | |
1770 | /* Output assembler code to perform a quadword move insn | |
2296cba3 | 1771 | with operands OPERANDS. This is very similar to the preceding |
795068a4 JW |
1772 | output_move_double function. */ |
1773 | ||
1774 | char * | |
1775 | output_move_quad (operands) | |
1776 | rtx *operands; | |
1777 | { | |
1778 | register rtx op0 = operands[0]; | |
1779 | register rtx op1 = operands[1]; | |
1780 | register enum optype optype0; | |
1781 | register enum optype optype1; | |
1782 | rtx wordpart[4][2]; | |
1783 | rtx addreg0 = 0; | |
1784 | rtx addreg1 = 0; | |
1785 | ||
1786 | /* First classify both operands. */ | |
1787 | ||
1788 | if (REG_P (op0)) | |
1789 | optype0 = REGOP; | |
1790 | else if (offsettable_memref_p (op0)) | |
1791 | optype0 = OFFSOP; | |
1792 | else if (GET_CODE (op0) == MEM) | |
1793 | optype0 = MEMOP; | |
1794 | else | |
1795 | optype0 = RNDOP; | |
1796 | ||
1797 | if (REG_P (op1)) | |
1798 | optype1 = REGOP; | |
1799 | else if (CONSTANT_P (op1)) | |
1800 | optype1 = CNSTOP; | |
1801 | else if (offsettable_memref_p (op1)) | |
1802 | optype1 = OFFSOP; | |
1803 | else if (GET_CODE (op1) == MEM) | |
1804 | optype1 = MEMOP; | |
1805 | else | |
1806 | optype1 = RNDOP; | |
1807 | ||
1808 | /* Check for the cases that the operand constraints are not | |
1809 | supposed to allow to happen. Abort if we get one, | |
1810 | because generating code for these cases is painful. */ | |
1811 | ||
1812 | if (optype0 == RNDOP || optype1 == RNDOP | |
1813 | || (optype0 == MEM && optype1 == MEM)) | |
1814 | abort (); | |
1815 | ||
1816 | /* If an operand is an unoffsettable memory ref, find a register | |
1817 | we can increment temporarily to make it refer to the later words. */ | |
1818 | ||
1819 | if (optype0 == MEMOP) | |
1820 | addreg0 = find_addr_reg (XEXP (op0, 0)); | |
1821 | ||
1822 | if (optype1 == MEMOP) | |
1823 | addreg1 = find_addr_reg (XEXP (op1, 0)); | |
1824 | ||
1825 | /* Ok, we can do one word at a time. | |
1826 | Set up in wordpart the operands to use for each word of the arguments. */ | |
1827 | ||
1828 | if (optype0 == REGOP) | |
1829 | { | |
1830 | wordpart[0][0] = gen_rtx (REG, SImode, REGNO (op0) + 0); | |
1831 | wordpart[1][0] = gen_rtx (REG, SImode, REGNO (op0) + 1); | |
1832 | wordpart[2][0] = gen_rtx (REG, SImode, REGNO (op0) + 2); | |
1833 | wordpart[3][0] = gen_rtx (REG, SImode, REGNO (op0) + 3); | |
1834 | } | |
1835 | else if (optype0 == OFFSOP) | |
1836 | { | |
1837 | wordpart[0][0] = adj_offsettable_operand (op0, 0); | |
1838 | wordpart[1][0] = adj_offsettable_operand (op0, 4); | |
1839 | wordpart[2][0] = adj_offsettable_operand (op0, 8); | |
1840 | wordpart[3][0] = adj_offsettable_operand (op0, 12); | |
1841 | } | |
1842 | else | |
1843 | { | |
1844 | wordpart[0][0] = op0; | |
1845 | wordpart[1][0] = op0; | |
1846 | wordpart[2][0] = op0; | |
1847 | wordpart[3][0] = op0; | |
1848 | } | |
1849 | ||
1850 | if (optype1 == REGOP) | |
1851 | { | |
1852 | wordpart[0][1] = gen_rtx (REG, SImode, REGNO (op1) + 0); | |
1853 | wordpart[1][1] = gen_rtx (REG, SImode, REGNO (op1) + 1); | |
1854 | wordpart[2][1] = gen_rtx (REG, SImode, REGNO (op1) + 2); | |
1855 | wordpart[3][1] = gen_rtx (REG, SImode, REGNO (op1) + 3); | |
1856 | } | |
1857 | else if (optype1 == OFFSOP) | |
1858 | { | |
1859 | wordpart[0][1] = adj_offsettable_operand (op1, 0); | |
1860 | wordpart[1][1] = adj_offsettable_operand (op1, 4); | |
1861 | wordpart[2][1] = adj_offsettable_operand (op1, 8); | |
1862 | wordpart[3][1] = adj_offsettable_operand (op1, 12); | |
1863 | } | |
1864 | else if (optype1 == CNSTOP) | |
1865 | { | |
61a66555 JW |
1866 | REAL_VALUE_TYPE r; |
1867 | long l[4]; | |
1868 | ||
1869 | /* This only works for TFmode floating point constants. */ | |
1870 | if (GET_CODE (op1) != CONST_DOUBLE || GET_MODE (op1) != TFmode) | |
1871 | abort (); | |
1872 | ||
1873 | REAL_VALUE_FROM_CONST_DOUBLE (r, op1); | |
1874 | REAL_VALUE_TO_TARGET_LONG_DOUBLE (r, l); | |
1875 | ||
1876 | wordpart[0][1] = GEN_INT (l[0]); | |
1877 | wordpart[1][1] = GEN_INT (l[1]); | |
1878 | wordpart[2][1] = GEN_INT (l[2]); | |
1879 | wordpart[3][1] = GEN_INT (l[3]); | |
795068a4 JW |
1880 | } |
1881 | else | |
1882 | { | |
1883 | wordpart[0][1] = op1; | |
1884 | wordpart[1][1] = op1; | |
1885 | wordpart[2][1] = op1; | |
1886 | wordpart[3][1] = op1; | |
1887 | } | |
1888 | ||
1889 | /* Easy case: try moving the quad as two pairs. Check for moving between | |
61a55e8b DE |
1890 | an even/odd register pair and a memory location. |
1891 | Also handle new v9 fp regs here. */ | |
795068a4 JW |
1892 | /* ??? Should also handle the case of non-offsettable addresses here. |
1893 | We can at least do the first pair as a ldd/std, and then do the third | |
1894 | and fourth words individually. */ | |
1895 | if ((optype0 == REGOP && optype1 == OFFSOP && (REGNO (op0) & 1) == 0) | |
1896 | || (optype0 == OFFSOP && optype1 == REGOP && (REGNO (op1) & 1) == 0)) | |
1897 | { | |
61a55e8b | 1898 | rtx mem, reg; |
795068a4 JW |
1899 | |
1900 | if (optype0 == REGOP) | |
61a55e8b | 1901 | mem = op1, reg = op0; |
795068a4 | 1902 | else |
61a55e8b | 1903 | mem = op0, reg = op1; |
795068a4 | 1904 | |
61a55e8b DE |
1905 | if (mem_aligned_8 (mem) |
1906 | /* If this is a floating point register higher than %f31, | |
1907 | then we *must* use an aligned load, since `ld' will not accept | |
1908 | the register number. */ | |
1909 | || (TARGET_V9 && REGNO (reg) >= 64)) | |
795068a4 | 1910 | { |
61a55e8b DE |
1911 | if (TARGET_V9 && FP_REG_P (reg)) |
1912 | { | |
1913 | if ((REGNO (reg) & 3) != 0) | |
1914 | abort (); | |
1915 | return (mem == op1 ? "ldq %1,%0" : "stq %1,%0"); | |
1916 | } | |
795068a4 JW |
1917 | operands[2] = adj_offsettable_operand (mem, 8); |
1918 | if (mem == op1) | |
61a55e8b | 1919 | return TARGET_V9 ? "ldx %1,%0;ldx %2,%R0" : "ldd %1,%0;ldd %2,%S0"; |
795068a4 | 1920 | else |
61a55e8b | 1921 | return TARGET_V9 ? "stx %1,%0;stx %R1,%2" : "std %1,%0;std %S1,%2"; |
795068a4 JW |
1922 | } |
1923 | } | |
1924 | ||
1925 | /* If the first move would clobber the source of the second one, | |
1926 | do them in the other order. */ | |
1927 | ||
1928 | /* Overlapping registers. */ | |
1929 | if (optype0 == REGOP && optype1 == REGOP | |
1930 | && (REGNO (op0) == REGNO (wordpart[1][3]) | |
1931 | || REGNO (op0) == REGNO (wordpart[1][2]) | |
1932 | || REGNO (op0) == REGNO (wordpart[1][1]))) | |
1933 | { | |
1934 | /* Do fourth word. */ | |
1935 | output_asm_insn (singlemove_string (wordpart[3]), wordpart[3]); | |
1936 | /* Do the third word. */ | |
1937 | output_asm_insn (singlemove_string (wordpart[2]), wordpart[2]); | |
1938 | /* Do the second word. */ | |
1939 | output_asm_insn (singlemove_string (wordpart[1]), wordpart[1]); | |
1940 | /* Do lowest-numbered word. */ | |
1941 | return singlemove_string (wordpart[0]); | |
1942 | } | |
1943 | /* Loading into a register which overlaps a register used in the address. */ | |
1944 | if (optype0 == REGOP && optype1 != REGOP | |
1945 | && reg_overlap_mentioned_p (op0, op1)) | |
1946 | { | |
1947 | /* ??? Not implemented yet. This is a bit complicated, because we | |
1948 | must load which ever part overlaps the address last. If the address | |
1949 | is a double-reg address, then there are two parts which need to | |
1950 | be done last, which is impossible. We would need a scratch register | |
1951 | in that case. */ | |
1952 | abort (); | |
1953 | } | |
1954 | ||
ddd5a7c1 | 1955 | /* Normal case: move the four words in lowest to highest address order. */ |
795068a4 JW |
1956 | |
1957 | output_asm_insn (singlemove_string (wordpart[0]), wordpart[0]); | |
1958 | ||
1959 | /* Make any unoffsettable addresses point at the second word. */ | |
1960 | if (addreg0) | |
1961 | output_asm_insn ("add %0,0x4,%0", &addreg0); | |
1962 | if (addreg1) | |
1963 | output_asm_insn ("add %0,0x4,%0", &addreg1); | |
1964 | ||
1965 | /* Do the second word. */ | |
1966 | output_asm_insn (singlemove_string (wordpart[1]), wordpart[1]); | |
1967 | ||
1968 | /* Make any unoffsettable addresses point at the third word. */ | |
1969 | if (addreg0) | |
1970 | output_asm_insn ("add %0,0x4,%0", &addreg0); | |
1971 | if (addreg1) | |
1972 | output_asm_insn ("add %0,0x4,%0", &addreg1); | |
1973 | ||
1974 | /* Do the third word. */ | |
1975 | output_asm_insn (singlemove_string (wordpart[2]), wordpart[2]); | |
1976 | ||
1977 | /* Make any unoffsettable addresses point at the fourth word. */ | |
1978 | if (addreg0) | |
1979 | output_asm_insn ("add %0,0x4,%0", &addreg0); | |
1980 | if (addreg1) | |
1981 | output_asm_insn ("add %0,0x4,%0", &addreg1); | |
1982 | ||
1983 | /* Do the fourth word. */ | |
1984 | output_asm_insn (singlemove_string (wordpart[3]), wordpart[3]); | |
1985 | ||
1986 | /* Undo the adds we just did. */ | |
1987 | if (addreg0) | |
1988 | output_asm_insn ("add %0,-0xc,%0", &addreg0); | |
1989 | if (addreg1) | |
1990 | output_asm_insn ("add %0,-0xc,%0", &addreg1); | |
1991 | ||
1992 | return ""; | |
1993 | } | |
ab835497 | 1994 | \f |
795068a4 | 1995 | /* Output assembler code to perform a doubleword move insn with operands |
a3ee5899 JW |
1996 | OPERANDS, one of which must be a floating point register. */ |
1997 | ||
ab835497 RK |
1998 | char * |
1999 | output_fp_move_double (operands) | |
2000 | rtx *operands; | |
2001 | { | |
ab835497 RK |
2002 | if (FP_REG_P (operands[0])) |
2003 | { | |
2004 | if (FP_REG_P (operands[1])) | |
61a55e8b DE |
2005 | { |
2006 | if (TARGET_V9) | |
2007 | return "fmovd %1,%0"; | |
2008 | else | |
2009 | return "fmovs %1,%0\n\tfmovs %R1,%R0"; | |
2010 | } | |
a3ee5899 | 2011 | else if (GET_CODE (operands[1]) == REG) |
019c2b24 | 2012 | abort (); |
a3ee5899 JW |
2013 | else |
2014 | return output_move_double (operands); | |
ab835497 RK |
2015 | } |
2016 | else if (FP_REG_P (operands[1])) | |
2017 | { | |
2018 | if (GET_CODE (operands[0]) == REG) | |
019c2b24 | 2019 | abort (); |
a3ee5899 JW |
2020 | else |
2021 | return output_move_double (operands); | |
ab835497 RK |
2022 | } |
2023 | else abort (); | |
2024 | } | |
795068a4 JW |
2025 | |
2026 | /* Output assembler code to perform a quadword move insn with operands | |
2027 | OPERANDS, one of which must be a floating point register. */ | |
2028 | ||
2029 | char * | |
2030 | output_fp_move_quad (operands) | |
2031 | rtx *operands; | |
2032 | { | |
2033 | register rtx op0 = operands[0]; | |
2034 | register rtx op1 = operands[1]; | |
795068a4 JW |
2035 | |
2036 | if (FP_REG_P (op0)) | |
2037 | { | |
2038 | if (FP_REG_P (op1)) | |
61a55e8b DE |
2039 | { |
2040 | if (TARGET_V9) | |
2041 | return "fmovq %1,%0"; | |
2042 | else | |
2043 | return "fmovs %1,%0\n\tfmovs %R1,%R0\n\tfmovs %S1,%S0\n\tfmovs %T1,%T0"; | |
2044 | } | |
019c2b24 JW |
2045 | else if (GET_CODE (op1) == REG) |
2046 | abort (); | |
795068a4 JW |
2047 | else |
2048 | return output_move_quad (operands); | |
2049 | } | |
2050 | else if (FP_REG_P (op1)) | |
2051 | { | |
2052 | if (GET_CODE (op0) == REG) | |
019c2b24 | 2053 | abort (); |
795068a4 JW |
2054 | else |
2055 | return output_move_quad (operands); | |
2056 | } | |
2057 | else | |
2058 | abort (); | |
2059 | } | |
ab835497 RK |
2060 | \f |
2061 | /* Return a REG that occurs in ADDR with coefficient 1. | |
2062 | ADDR can be effectively incremented by incrementing REG. */ | |
2063 | ||
2064 | static rtx | |
2065 | find_addr_reg (addr) | |
2066 | rtx addr; | |
2067 | { | |
2068 | while (GET_CODE (addr) == PLUS) | |
2069 | { | |
2070 | /* We absolutely can not fudge the frame pointer here, because the | |
2071 | frame pointer must always be 8 byte aligned. It also confuses | |
2072 | debuggers. */ | |
2073 | if (GET_CODE (XEXP (addr, 0)) == REG | |
2074 | && REGNO (XEXP (addr, 0)) != FRAME_POINTER_REGNUM) | |
2075 | addr = XEXP (addr, 0); | |
2076 | else if (GET_CODE (XEXP (addr, 1)) == REG | |
2077 | && REGNO (XEXP (addr, 1)) != FRAME_POINTER_REGNUM) | |
2078 | addr = XEXP (addr, 1); | |
2079 | else if (CONSTANT_P (XEXP (addr, 0))) | |
2080 | addr = XEXP (addr, 1); | |
2081 | else if (CONSTANT_P (XEXP (addr, 1))) | |
2082 | addr = XEXP (addr, 0); | |
2083 | else | |
2084 | abort (); | |
2085 | } | |
2086 | if (GET_CODE (addr) == REG) | |
2087 | return addr; | |
2088 | abort (); | |
2089 | } | |
2090 | ||
6a4bb1fa DE |
2091 | #if 0 /* not currently used */ |
2092 | ||
ab835497 RK |
2093 | void |
2094 | output_sized_memop (opname, mode, signedp) | |
2095 | char *opname; | |
2096 | enum machine_mode mode; | |
2097 | int signedp; | |
2098 | { | |
2099 | static char *ld_size_suffix_u[] = { "ub", "uh", "", "?", "d" }; | |
2100 | static char *ld_size_suffix_s[] = { "sb", "sh", "", "?", "d" }; | |
2101 | static char *st_size_suffix[] = { "b", "h", "", "?", "d" }; | |
2102 | char **opnametab, *modename; | |
2103 | ||
2104 | if (opname[0] == 'l') | |
2105 | if (signedp) | |
2106 | opnametab = ld_size_suffix_s; | |
2107 | else | |
2108 | opnametab = ld_size_suffix_u; | |
2109 | else | |
2110 | opnametab = st_size_suffix; | |
2111 | modename = opnametab[GET_MODE_SIZE (mode) >> 1]; | |
2112 | ||
2113 | fprintf (asm_out_file, "\t%s%s", opname, modename); | |
2114 | } | |
2115 | \f | |
2116 | void | |
2117 | output_move_with_extension (operands) | |
2118 | rtx *operands; | |
2119 | { | |
2120 | if (GET_MODE (operands[2]) == HImode) | |
2121 | output_asm_insn ("sll %2,0x10,%0", operands); | |
2122 | else if (GET_MODE (operands[2]) == QImode) | |
2123 | output_asm_insn ("sll %2,0x18,%0", operands); | |
2124 | else | |
2125 | abort (); | |
2126 | } | |
6a4bb1fa | 2127 | #endif /* not currently used */ |
ab835497 | 2128 | \f |
09aa6559 JW |
2129 | #if 0 |
2130 | /* ??? These are only used by the movstrsi pattern, but we get better code | |
2131 | in general without that, because emit_block_move can do just as good a | |
2132 | job as this function does when alignment and size are known. When they | |
2133 | aren't known, a call to strcpy may be faster anyways, because it is | |
2134 | likely to be carefully crafted assembly language code, and below we just | |
2135 | do a byte-wise copy. | |
2136 | ||
2137 | Also, emit_block_move expands into multiple read/write RTL insns, which | |
2138 | can then be optimized, whereas our movstrsi pattern can not be optimized | |
2139 | at all. */ | |
2140 | ||
ab835497 RK |
2141 | /* Load the address specified by OPERANDS[3] into the register |
2142 | specified by OPERANDS[0]. | |
2143 | ||
2144 | OPERANDS[3] may be the result of a sum, hence it could either be: | |
2145 | ||
2146 | (1) CONST | |
2147 | (2) REG | |
2148 | (2) REG + CONST_INT | |
2149 | (3) REG + REG + CONST_INT | |
2150 | (4) REG + REG (special case of 3). | |
2151 | ||
2152 | Note that (3) is not a legitimate address. | |
2153 | All cases are handled here. */ | |
2154 | ||
2155 | void | |
2156 | output_load_address (operands) | |
2157 | rtx *operands; | |
2158 | { | |
2159 | rtx base, offset; | |
2160 | ||
2161 | if (CONSTANT_P (operands[3])) | |
2162 | { | |
2163 | output_asm_insn ("set %3,%0", operands); | |
2164 | return; | |
2165 | } | |
2166 | ||
2167 | if (REG_P (operands[3])) | |
2168 | { | |
2169 | if (REGNO (operands[0]) != REGNO (operands[3])) | |
2170 | output_asm_insn ("mov %3,%0", operands); | |
2171 | return; | |
2172 | } | |
2173 | ||
2174 | if (GET_CODE (operands[3]) != PLUS) | |
2175 | abort (); | |
2176 | ||
2177 | base = XEXP (operands[3], 0); | |
2178 | offset = XEXP (operands[3], 1); | |
2179 | ||
2180 | if (GET_CODE (base) == CONST_INT) | |
2181 | { | |
2182 | rtx tmp = base; | |
2183 | base = offset; | |
2184 | offset = tmp; | |
2185 | } | |
2186 | ||
2187 | if (GET_CODE (offset) != CONST_INT) | |
2188 | { | |
2189 | /* Operand is (PLUS (REG) (REG)). */ | |
2190 | base = operands[3]; | |
2191 | offset = const0_rtx; | |
2192 | } | |
2193 | ||
2194 | if (REG_P (base)) | |
2195 | { | |
2196 | operands[6] = base; | |
2197 | operands[7] = offset; | |
2198 | if (SMALL_INT (offset)) | |
2199 | output_asm_insn ("add %6,%7,%0", operands); | |
2200 | else | |
2201 | output_asm_insn ("set %7,%0\n\tadd %0,%6,%0", operands); | |
2202 | } | |
2203 | else if (GET_CODE (base) == PLUS) | |
2204 | { | |
2205 | operands[6] = XEXP (base, 0); | |
2206 | operands[7] = XEXP (base, 1); | |
2207 | operands[8] = offset; | |
2208 | ||
2209 | if (SMALL_INT (offset)) | |
2210 | output_asm_insn ("add %6,%7,%0\n\tadd %0,%8,%0", operands); | |
2211 | else | |
2212 | output_asm_insn ("set %8,%0\n\tadd %0,%6,%0\n\tadd %0,%7,%0", operands); | |
2213 | } | |
2214 | else | |
2215 | abort (); | |
2216 | } | |
2217 | ||
2218 | /* Output code to place a size count SIZE in register REG. | |
2219 | ALIGN is the size of the unit of transfer. | |
2220 | ||
2221 | Because block moves are pipelined, we don't include the | |
2222 | first element in the transfer of SIZE to REG. */ | |
2223 | ||
2224 | static void | |
2225 | output_size_for_block_move (size, reg, align) | |
2226 | rtx size, reg; | |
2227 | rtx align; | |
2228 | { | |
2229 | rtx xoperands[3]; | |
2230 | ||
2231 | xoperands[0] = reg; | |
2232 | xoperands[1] = size; | |
2233 | xoperands[2] = align; | |
2234 | if (GET_CODE (size) == REG) | |
2235 | output_asm_insn ("sub %1,%2,%0", xoperands); | |
2236 | else | |
2237 | { | |
2238 | xoperands[1] | |
2239 | = gen_rtx (CONST_INT, VOIDmode, INTVAL (size) - INTVAL (align)); | |
2240 | output_asm_insn ("set %1,%0", xoperands); | |
2241 | } | |
2242 | } | |
2243 | ||
2244 | /* Emit code to perform a block move. | |
2245 | ||
2246 | OPERANDS[0] is the destination. | |
2247 | OPERANDS[1] is the source. | |
2248 | OPERANDS[2] is the size. | |
2249 | OPERANDS[3] is the alignment safe to use. | |
2250 | OPERANDS[4] is a register we can safely clobber as a temp. */ | |
2251 | ||
2252 | char * | |
2253 | output_block_move (operands) | |
2254 | rtx *operands; | |
2255 | { | |
2256 | /* A vector for our computed operands. Note that load_output_address | |
2257 | makes use of (and can clobber) up to the 8th element of this vector. */ | |
2258 | rtx xoperands[10]; | |
2259 | rtx zoperands[10]; | |
2260 | static int movstrsi_label = 0; | |
2261 | int i; | |
2262 | rtx temp1 = operands[4]; | |
2263 | rtx sizertx = operands[2]; | |
2264 | rtx alignrtx = operands[3]; | |
2265 | int align = INTVAL (alignrtx); | |
210aa14a | 2266 | char label3[30], label5[30]; |
ab835497 RK |
2267 | |
2268 | xoperands[0] = operands[0]; | |
2269 | xoperands[1] = operands[1]; | |
2270 | xoperands[2] = temp1; | |
2271 | ||
391b99c9 RS |
2272 | /* We can't move more than this many bytes at a time because we have only |
2273 | one register, %g1, to move them through. */ | |
2274 | if (align > UNITS_PER_WORD) | |
ab835497 | 2275 | { |
391b99c9 RS |
2276 | align = UNITS_PER_WORD; |
2277 | alignrtx = gen_rtx (CONST_INT, VOIDmode, UNITS_PER_WORD); | |
ab835497 RK |
2278 | } |
2279 | ||
391b99c9 RS |
2280 | /* We consider 8 ld/st pairs, for a total of 16 inline insns to be |
2281 | reasonable here. (Actually will emit a maximum of 18 inline insns for | |
2282 | the case of size == 31 and align == 4). */ | |
2283 | ||
2284 | if (GET_CODE (sizertx) == CONST_INT && (INTVAL (sizertx) / align) <= 8 | |
2285 | && memory_address_p (QImode, plus_constant_for_output (xoperands[0], | |
2286 | INTVAL (sizertx))) | |
2287 | && memory_address_p (QImode, plus_constant_for_output (xoperands[1], | |
2288 | INTVAL (sizertx)))) | |
ab835497 RK |
2289 | { |
2290 | int size = INTVAL (sizertx); | |
391b99c9 | 2291 | int offset = 0; |
ab835497 | 2292 | |
391b99c9 RS |
2293 | /* We will store different integers into this particular RTX. */ |
2294 | xoperands[2] = rtx_alloc (CONST_INT); | |
2295 | PUT_MODE (xoperands[2], VOIDmode); | |
ab835497 | 2296 | |
391b99c9 RS |
2297 | /* This case is currently not handled. Abort instead of generating |
2298 | bad code. */ | |
61a55e8b | 2299 | if (align > UNITS_PER_WORD) |
391b99c9 | 2300 | abort (); |
ab835497 | 2301 | |
61a55e8b DE |
2302 | if (TARGET_V9 && align >= 8) |
2303 | { | |
2304 | for (i = (size >> 3) - 1; i >= 0; i--) | |
2305 | { | |
2306 | INTVAL (xoperands[2]) = (i << 3) + offset; | |
2307 | output_asm_insn ("ldx [%a1+%2],%%g1\n\tstx %%g1,[%a0+%2]", | |
2308 | xoperands); | |
2309 | } | |
2310 | offset += (size & ~0x7); | |
2311 | size = size & 0x7; | |
2312 | if (size == 0) | |
2313 | return ""; | |
2314 | } | |
2315 | ||
391b99c9 | 2316 | if (align >= 4) |
ab835497 | 2317 | { |
391b99c9 | 2318 | for (i = (size >> 2) - 1; i >= 0; i--) |
ab835497 | 2319 | { |
391b99c9 RS |
2320 | INTVAL (xoperands[2]) = (i << 2) + offset; |
2321 | output_asm_insn ("ld [%a1+%2],%%g1\n\tst %%g1,[%a0+%2]", | |
2322 | xoperands); | |
ab835497 | 2323 | } |
391b99c9 RS |
2324 | offset += (size & ~0x3); |
2325 | size = size & 0x3; | |
2326 | if (size == 0) | |
2327 | return ""; | |
ab835497 | 2328 | } |
391b99c9 RS |
2329 | |
2330 | if (align >= 2) | |
ab835497 | 2331 | { |
391b99c9 | 2332 | for (i = (size >> 1) - 1; i >= 0; i--) |
ab835497 | 2333 | { |
391b99c9 RS |
2334 | INTVAL (xoperands[2]) = (i << 1) + offset; |
2335 | output_asm_insn ("lduh [%a1+%2],%%g1\n\tsth %%g1,[%a0+%2]", | |
2336 | xoperands); | |
ab835497 | 2337 | } |
391b99c9 RS |
2338 | offset += (size & ~0x1); |
2339 | size = size & 0x1; | |
2340 | if (size == 0) | |
2341 | return ""; | |
ab835497 | 2342 | } |
391b99c9 RS |
2343 | |
2344 | if (align >= 1) | |
ab835497 | 2345 | { |
391b99c9 | 2346 | for (i = size - 1; i >= 0; i--) |
ab835497 | 2347 | { |
391b99c9 RS |
2348 | INTVAL (xoperands[2]) = i + offset; |
2349 | output_asm_insn ("ldub [%a1+%2],%%g1\n\tstb %%g1,[%a0+%2]", | |
2350 | xoperands); | |
ab835497 | 2351 | } |
391b99c9 | 2352 | return ""; |
ab835497 | 2353 | } |
391b99c9 RS |
2354 | |
2355 | /* We should never reach here. */ | |
2356 | abort (); | |
ab835497 RK |
2357 | } |
2358 | ||
391b99c9 RS |
2359 | /* If the size isn't known to be a multiple of the alignment, |
2360 | we have to do it in smaller pieces. If we could determine that | |
2361 | the size was a multiple of 2 (or whatever), we could be smarter | |
2362 | about this. */ | |
2363 | if (GET_CODE (sizertx) != CONST_INT) | |
2364 | align = 1; | |
2365 | else | |
2366 | { | |
2367 | int size = INTVAL (sizertx); | |
2368 | while (size % align) | |
2369 | align >>= 1; | |
2370 | } | |
2371 | ||
2372 | if (align != INTVAL (alignrtx)) | |
2373 | alignrtx = gen_rtx (CONST_INT, VOIDmode, align); | |
2374 | ||
ab835497 RK |
2375 | xoperands[3] = gen_rtx (CONST_INT, VOIDmode, movstrsi_label++); |
2376 | xoperands[4] = gen_rtx (CONST_INT, VOIDmode, align); | |
2377 | xoperands[5] = gen_rtx (CONST_INT, VOIDmode, movstrsi_label++); | |
2378 | ||
210aa14a RS |
2379 | ASM_GENERATE_INTERNAL_LABEL (label3, "Lm", INTVAL (xoperands[3])); |
2380 | ASM_GENERATE_INTERNAL_LABEL (label5, "Lm", INTVAL (xoperands[5])); | |
2381 | ||
391b99c9 RS |
2382 | /* This is the size of the transfer. Emit code to decrement the size |
2383 | value by ALIGN, and store the result in the temp1 register. */ | |
ab835497 RK |
2384 | output_size_for_block_move (sizertx, temp1, alignrtx); |
2385 | ||
2386 | /* Must handle the case when the size is zero or negative, so the first thing | |
2387 | we do is compare the size against zero, and only copy bytes if it is | |
2388 | zero or greater. Note that we have already subtracted off the alignment | |
2389 | once, so we must copy 1 alignment worth of bytes if the size is zero | |
2390 | here. | |
2391 | ||
2392 | The SUN assembler complains about labels in branch delay slots, so we | |
b4ac57ab | 2393 | do this before outputting the load address, so that there will always |
ab835497 RK |
2394 | be a harmless insn between the branch here and the next label emitted |
2395 | below. */ | |
2396 | ||
210aa14a RS |
2397 | { |
2398 | char pattern[100]; | |
2399 | ||
2400 | sprintf (pattern, "cmp %%2,0\n\tbl %s", &label5[1]); | |
2401 | output_asm_insn (pattern, xoperands); | |
2402 | } | |
ab835497 RK |
2403 | |
2404 | zoperands[0] = operands[0]; | |
2405 | zoperands[3] = plus_constant_for_output (operands[0], align); | |
2406 | output_load_address (zoperands); | |
2407 | ||
2408 | /* ??? This might be much faster if the loops below were preconditioned | |
2409 | and unrolled. | |
2410 | ||
2411 | That is, at run time, copy enough bytes one at a time to ensure that the | |
2412 | target and source addresses are aligned to the the largest possible | |
2413 | alignment. Then use a preconditioned unrolled loop to copy say 16 | |
2414 | bytes at a time. Then copy bytes one at a time until finish the rest. */ | |
2415 | ||
2416 | /* Output the first label separately, so that it is spaced properly. */ | |
2417 | ||
ab835497 | 2418 | ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "Lm", INTVAL (xoperands[3])); |
ab835497 | 2419 | |
210aa14a RS |
2420 | { |
2421 | char pattern[200]; | |
61a55e8b DE |
2422 | register char *ld_suffix = ((align == 1) ? "ub" : (align == 2) ? "uh" |
2423 | : (align == 8 && TARGET_V9) ? "x" : ""); | |
2424 | register char *st_suffix = ((align == 1) ? "b" : (align == 2) ? "h" | |
2425 | : (align == 8 && TARGET_V9) ? "x" : ""); | |
210aa14a RS |
2426 | |
2427 | sprintf (pattern, "ld%s [%%1+%%2],%%%%g1\n\tsubcc %%2,%%4,%%2\n\tbge %s\n\tst%s %%%%g1,[%%0+%%2]\n%s:", ld_suffix, &label3[1], st_suffix, &label5[1]); | |
2428 | output_asm_insn (pattern, xoperands); | |
2429 | } | |
2430 | ||
ab835497 | 2431 | return ""; |
ab835497 | 2432 | } |
09aa6559 | 2433 | #endif |
ab835497 RK |
2434 | \f |
2435 | /* Output reasonable peephole for set-on-condition-code insns. | |
2436 | Note that these insns assume a particular way of defining | |
2437 | labels. Therefore, *both* sparc.h and this function must | |
2438 | be changed if a new syntax is needed. */ | |
2439 | ||
2440 | char * | |
2441 | output_scc_insn (operands, insn) | |
2442 | rtx operands[]; | |
2443 | rtx insn; | |
2444 | { | |
2445 | static char string[100]; | |
2446 | rtx label = 0, next = insn; | |
2447 | int need_label = 0; | |
2448 | ||
2449 | /* Try doing a jump optimization which jump.c can't do for us | |
2450 | because we did not expose that setcc works by using branches. | |
2451 | ||
2452 | If this scc insn is followed by an unconditional branch, then have | |
2453 | the jump insn emitted here jump to that location, instead of to | |
2454 | the end of the scc sequence as usual. */ | |
2455 | ||
2456 | do | |
2457 | { | |
2458 | if (GET_CODE (next) == CODE_LABEL) | |
2459 | label = next; | |
2460 | next = NEXT_INSN (next); | |
2461 | if (next == 0) | |
2462 | break; | |
2463 | } | |
2464 | while (GET_CODE (next) == NOTE || GET_CODE (next) == CODE_LABEL); | |
2465 | ||
2466 | /* If we are in a sequence, and the following insn is a sequence also, | |
2467 | then just following the current insn's next field will take us to the | |
2468 | first insn of the next sequence, which is the wrong place. We don't | |
2469 | want to optimize with a branch that has had its delay slot filled. | |
2470 | Avoid this by verifying that NEXT_INSN (PREV_INSN (next)) == next | |
2471 | which fails only if NEXT is such a branch. */ | |
2472 | ||
2473 | if (next && GET_CODE (next) == JUMP_INSN && simplejump_p (next) | |
2474 | && (! final_sequence || NEXT_INSN (PREV_INSN (next)) == next)) | |
2475 | label = JUMP_LABEL (next); | |
2476 | /* If not optimizing, jump label fields are not set. To be safe, always | |
2477 | check here to whether label is still zero. */ | |
2478 | if (label == 0) | |
2479 | { | |
2480 | label = gen_label_rtx (); | |
2481 | need_label = 1; | |
2482 | } | |
2483 | ||
2484 | LABEL_NUSES (label) += 1; | |
2485 | ||
2486 | operands[2] = label; | |
2487 | ||
2488 | /* If we are in a delay slot, assume it is the delay slot of an fpcc | |
2489 | insn since our type isn't allowed anywhere else. */ | |
2490 | ||
2491 | /* ??? Fpcc instructions no longer have delay slots, so this code is | |
2492 | probably obsolete. */ | |
2493 | ||
2494 | /* The fastest way to emit code for this is an annulled branch followed | |
2495 | by two move insns. This will take two cycles if the branch is taken, | |
2496 | and three cycles if the branch is not taken. | |
2497 | ||
2498 | However, if we are in the delay slot of another branch, this won't work, | |
2499 | because we can't put a branch in the delay slot of another branch. | |
2500 | The above sequence would effectively take 3 or 4 cycles respectively | |
2501 | since a no op would have be inserted between the two branches. | |
2502 | In this case, we want to emit a move, annulled branch, and then the | |
2503 | second move. This sequence always takes 3 cycles, and hence is faster | |
2504 | when we are in a branch delay slot. */ | |
2505 | ||
2506 | if (final_sequence) | |
2507 | { | |
2508 | strcpy (string, "mov 0,%0\n\t"); | |
61a55e8b | 2509 | strcat (string, output_cbranch (operands[1], 0, 2, 0, 1, 0)); |
ab835497 RK |
2510 | strcat (string, "\n\tmov 1,%0"); |
2511 | } | |
2512 | else | |
2513 | { | |
61a55e8b | 2514 | strcpy (string, output_cbranch (operands[1], 0, 2, 0, 1, 0)); |
ab835497 RK |
2515 | strcat (string, "\n\tmov 1,%0\n\tmov 0,%0"); |
2516 | } | |
2517 | ||
2518 | if (need_label) | |
2519 | strcat (string, "\n%l2:"); | |
2520 | ||
2521 | return string; | |
2522 | } | |
2523 | \f | |
61a55e8b DE |
2524 | /* Vectors to keep interesting information about registers where it can easily |
2525 | be got. We use to use the actual mode value as the bit number, but there | |
2526 | are more than 32 modes now. Instead we use two tables: one indexed by | |
2527 | hard register number, and one indexed by mode. */ | |
2528 | ||
2529 | /* The purpose of sparc_mode_class is to shrink the range of modes so that | |
2530 | they all fit (as bit numbers) in a 32 bit word (again). Each real mode is | |
2531 | mapped into one sparc_mode_class mode. */ | |
2532 | ||
2533 | enum sparc_mode_class { | |
2534 | C_MODE, CCFP_MODE, | |
2535 | S_MODE, D_MODE, T_MODE, O_MODE, | |
2536 | SF_MODE, DF_MODE, TF_MODE, OF_MODE | |
2537 | }; | |
ab835497 RK |
2538 | |
2539 | /* Modes for condition codes. */ | |
61a55e8b DE |
2540 | #define C_MODES ((1 << (int) C_MODE) | (1 << (int) CCFP_MODE)) |
2541 | #define CCFP_MODES (1 << (int) CCFP_MODE) | |
2542 | ||
2543 | /* Modes for single-word and smaller quantities. */ | |
2544 | #define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE)) | |
2545 | ||
2546 | /* Modes for double-word and smaller quantities. */ | |
2547 | #define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE)) | |
2548 | ||
2549 | /* Modes for quad-word and smaller quantities. */ | |
2550 | #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE)) | |
ab835497 | 2551 | |
1e4eb8d1 JW |
2552 | /* Modes for single-float quantities. We must allow any single word or |
2553 | smaller quantity. This is because the fix/float conversion instructions | |
2554 | take integer inputs/outputs from the float registers. */ | |
2555 | #define SF_MODES (S_MODES) | |
ab835497 | 2556 | |
61a55e8b DE |
2557 | /* Modes for double-float and smaller quantities. */ |
2558 | #define DF_MODES (S_MODES | D_MODES) | |
2559 | ||
2560 | /* ??? Sparc64 fp regs cannot hold DImode values. */ | |
2561 | #define DF_MODES64 (SF_MODES | DF_MODE /* | D_MODE*/) | |
2562 | ||
2563 | /* Modes for double-float only quantities. */ | |
2564 | /* ??? Sparc64 fp regs cannot hold DImode values. */ | |
2565 | #define DF_ONLY_MODES ((1 << (int) DF_MODE) /*| (1 << (int) D_MODE)*/) | |
2566 | ||
2567 | /* Modes for double-float and larger quantities. */ | |
2568 | #define DF_UP_MODES (DF_ONLY_MODES | TF_ONLY_MODES) | |
ab835497 | 2569 | |
61a55e8b DE |
2570 | /* Modes for quad-float only quantities. */ |
2571 | #define TF_ONLY_MODES (1 << (int) TF_MODE) | |
2572 | ||
2573 | /* Modes for quad-float and smaller quantities. */ | |
2574 | #define TF_MODES (DF_MODES | TF_ONLY_MODES) | |
2575 | ||
2576 | /* ??? Sparc64 fp regs cannot hold DImode values. */ | |
2577 | #define TF_MODES64 (DF_MODES64 | TF_ONLY_MODES) | |
ab835497 RK |
2578 | |
2579 | /* Value is 1 if register/mode pair is acceptable on sparc. | |
2580 | The funny mixture of D and T modes is because integer operations | |
2581 | do not specially operate on tetra quantities, so non-quad-aligned | |
2582 | registers can hold quadword quantities (except %o4 and %i4 because | |
2583 | they cross fixed registers. */ | |
2584 | ||
61a55e8b DE |
2585 | /* This points to either the 32 bit or the 64 bit version. */ |
2586 | int *hard_regno_mode_classes; | |
2587 | ||
2588 | static int hard_32bit_mode_classes[] = { | |
ab835497 RK |
2589 | C_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, |
2590 | T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES, | |
2591 | T_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, | |
2592 | T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES, | |
2593 | ||
2594 | TF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES, | |
2595 | TF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES, | |
2596 | TF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES, | |
61a55e8b DE |
2597 | TF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES, |
2598 | }; | |
2599 | ||
2600 | static int hard_64bit_mode_classes[] = { | |
2601 | C_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, | |
2602 | T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, | |
2603 | T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, | |
2604 | T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, | |
2605 | ||
2606 | TF_MODES64, SF_MODES, DF_MODES64, SF_MODES, TF_MODES64, SF_MODES, DF_MODES64, SF_MODES, | |
2607 | TF_MODES64, SF_MODES, DF_MODES64, SF_MODES, TF_MODES64, SF_MODES, DF_MODES64, SF_MODES, | |
2608 | TF_MODES64, SF_MODES, DF_MODES64, SF_MODES, TF_MODES64, SF_MODES, DF_MODES64, SF_MODES, | |
2609 | TF_MODES64, SF_MODES, DF_MODES64, SF_MODES, TF_MODES64, SF_MODES, DF_MODES64, SF_MODES, | |
2610 | ||
2611 | /* The remaining registers do not exist on a non-v9 sparc machine. | |
2612 | FP regs f32 to f63. Only the even numbered registers actually exist, | |
2613 | and none can hold SFmode/SImode values. */ | |
2614 | DF_UP_MODES, 0, DF_ONLY_MODES, 0, DF_UP_MODES, 0, DF_ONLY_MODES, 0, | |
2615 | DF_UP_MODES, 0, DF_ONLY_MODES, 0, DF_UP_MODES, 0, DF_ONLY_MODES, 0, | |
2616 | DF_UP_MODES, 0, DF_ONLY_MODES, 0, DF_UP_MODES, 0, DF_ONLY_MODES, 0, | |
2617 | DF_UP_MODES, 0, DF_ONLY_MODES, 0, DF_UP_MODES, 0, DF_ONLY_MODES, 0, | |
2618 | ||
2619 | /* %fcc[0123] */ | |
2620 | CCFP_MODE, CCFP_MODE, CCFP_MODE, CCFP_MODE | |
2621 | }; | |
2622 | ||
2623 | int sparc_mode_class [NUM_MACHINE_MODES]; | |
2624 | ||
2625 | static void | |
2626 | sparc_init_modes () | |
2627 | { | |
2628 | int i; | |
2629 | ||
dbb54862 | 2630 | sparc_arch_type = TARGET_V9 ? ARCH_64BIT : ARCH_32BIT; |
61a55e8b DE |
2631 | |
2632 | for (i = 0; i < NUM_MACHINE_MODES; i++) | |
2633 | { | |
2634 | switch (GET_MODE_CLASS (i)) | |
2635 | { | |
2636 | case MODE_INT: | |
2637 | case MODE_PARTIAL_INT: | |
2638 | case MODE_COMPLEX_INT: | |
2639 | if (GET_MODE_SIZE (i) <= 4) | |
2640 | sparc_mode_class[i] = 1 << (int) S_MODE; | |
2641 | else if (GET_MODE_SIZE (i) == 8) | |
2642 | sparc_mode_class[i] = 1 << (int) D_MODE; | |
2643 | else if (GET_MODE_SIZE (i) == 16) | |
2644 | sparc_mode_class[i] = 1 << (int) T_MODE; | |
2645 | else if (GET_MODE_SIZE (i) == 32) | |
2646 | sparc_mode_class[i] = 1 << (int) O_MODE; | |
2647 | else | |
2648 | sparc_mode_class[i] = 0; | |
2649 | break; | |
2650 | case MODE_FLOAT: | |
2651 | case MODE_COMPLEX_FLOAT: | |
2652 | if (GET_MODE_SIZE (i) <= 4) | |
2653 | sparc_mode_class[i] = 1 << (int) SF_MODE; | |
2654 | else if (GET_MODE_SIZE (i) == 8) | |
2655 | sparc_mode_class[i] = 1 << (int) DF_MODE; | |
2656 | else if (GET_MODE_SIZE (i) == 16) | |
2657 | sparc_mode_class[i] = 1 << (int) TF_MODE; | |
2658 | else if (GET_MODE_SIZE (i) == 32) | |
2659 | sparc_mode_class[i] = 1 << (int) OF_MODE; | |
2660 | else | |
2661 | sparc_mode_class[i] = 0; | |
2662 | break; | |
2663 | case MODE_CC: | |
2664 | default: | |
2665 | /* mode_class hasn't been initialized yet for EXTRA_CC_MODES, so | |
2666 | we must explicitly check for them here. */ | |
2667 | if (i == (int) CCFPmode || i == (int) CCFPEmode) | |
2668 | sparc_mode_class[i] = 1 << (int) CCFP_MODE; | |
2669 | else if (i == (int) CCmode || i == (int) CC_NOOVmode | |
2670 | #ifdef SPARCV9 | |
2671 | || i == (int) CCXmode | |
2672 | || i == (int) CCX_NOOVmode | |
2673 | #endif | |
2674 | ) | |
2675 | sparc_mode_class[i] = 1 << (int) C_MODE; | |
2676 | else | |
2677 | sparc_mode_class[i] = 0; | |
2678 | break; | |
2679 | } | |
2680 | } | |
2681 | ||
2682 | if (TARGET_V9) | |
2683 | hard_regno_mode_classes = hard_64bit_mode_classes; | |
2684 | else | |
2685 | hard_regno_mode_classes = hard_32bit_mode_classes; | |
2686 | } | |
ab835497 | 2687 | \f |
61a55e8b DE |
2688 | /* Save non call used registers from LOW to HIGH at BASE+OFFSET. |
2689 | N_REGS is the number of 4-byte regs saved thus far. This applies even to | |
2690 | v9 int regs as it simplifies the code. */ | |
2691 | ||
ab835497 | 2692 | #ifdef __GNUC__ |
99c7b2f6 | 2693 | __inline__ |
ab835497 RK |
2694 | #endif |
2695 | static int | |
61a55e8b | 2696 | save_regs (file, low, high, base, offset, n_regs) |
ab835497 RK |
2697 | FILE *file; |
2698 | int low, high; | |
2699 | char *base; | |
2700 | int offset; | |
61a55e8b | 2701 | int n_regs; |
ab835497 RK |
2702 | { |
2703 | int i; | |
2704 | ||
61a55e8b | 2705 | if (TARGET_V9 && high <= 32) |
ab835497 | 2706 | { |
61a55e8b DE |
2707 | for (i = low; i < high; i++) |
2708 | { | |
2709 | if (regs_ever_live[i] && ! call_used_regs[i]) | |
2710 | fprintf (file, "\tstx %s,[%s+%d]\n", | |
2711 | reg_names[i], base, offset + 4 * n_regs), | |
2712 | n_regs += 2; | |
2713 | } | |
ab835497 | 2714 | } |
61a55e8b DE |
2715 | else |
2716 | { | |
2717 | for (i = low; i < high; i += 2) | |
2718 | { | |
2719 | if (regs_ever_live[i] && ! call_used_regs[i]) | |
2720 | if (regs_ever_live[i+1] && ! call_used_regs[i+1]) | |
2721 | fprintf (file, "\tstd %s,[%s+%d]\n", | |
2722 | reg_names[i], base, offset + 4 * n_regs), | |
2723 | n_regs += 2; | |
2724 | else | |
2725 | fprintf (file, "\tst %s,[%s+%d]\n", | |
2726 | reg_names[i], base, offset + 4 * n_regs), | |
2727 | n_regs += 2; | |
2728 | else if (regs_ever_live[i+1] && ! call_used_regs[i+1]) | |
2729 | fprintf (file, "\tst %s,[%s+%d]\n", | |
2730 | reg_names[i+1], base, offset + 4 * n_regs + 4), | |
2731 | n_regs += 2; | |
2732 | } | |
2733 | } | |
2734 | return n_regs; | |
ab835497 RK |
2735 | } |
2736 | ||
61a55e8b DE |
2737 | /* Restore non call used registers from LOW to HIGH at BASE+OFFSET. |
2738 | ||
2739 | N_REGS is the number of 4-byte regs saved thus far. This applies even to | |
2740 | v9 int regs as it simplifies the code. */ | |
2741 | ||
ab835497 | 2742 | #ifdef __GNUC__ |
99c7b2f6 | 2743 | __inline__ |
ab835497 RK |
2744 | #endif |
2745 | static int | |
61a55e8b | 2746 | restore_regs (file, low, high, base, offset, n_regs) |
ab835497 RK |
2747 | FILE *file; |
2748 | int low, high; | |
2749 | char *base; | |
2750 | int offset; | |
61a55e8b | 2751 | int n_regs; |
ab835497 RK |
2752 | { |
2753 | int i; | |
2754 | ||
61a55e8b DE |
2755 | if (TARGET_V9 && high <= 32) |
2756 | { | |
2757 | for (i = low; i < high; i++) | |
2758 | { | |
2759 | if (regs_ever_live[i] && ! call_used_regs[i]) | |
2760 | fprintf (file, "\tldx [%s+%d], %s\n", | |
2761 | base, offset + 4 * n_regs, reg_names[i]), | |
2762 | n_regs += 2; | |
2763 | } | |
2764 | } | |
2765 | else | |
ab835497 | 2766 | { |
61a55e8b DE |
2767 | for (i = low; i < high; i += 2) |
2768 | { | |
2769 | if (regs_ever_live[i] && ! call_used_regs[i]) | |
2770 | if (regs_ever_live[i+1] && ! call_used_regs[i+1]) | |
2771 | fprintf (file, "\tldd [%s+%d], %s\n", | |
2772 | base, offset + 4 * n_regs, reg_names[i]), | |
2773 | n_regs += 2; | |
2774 | else | |
2775 | fprintf (file, "\tld [%s+%d],%s\n", | |
2776 | base, offset + 4 * n_regs, reg_names[i]), | |
2777 | n_regs += 2; | |
2778 | else if (regs_ever_live[i+1] && ! call_used_regs[i+1]) | |
2779 | fprintf (file, "\tld [%s+%d],%s\n", | |
2780 | base, offset + 4 * n_regs + 4, reg_names[i+1]), | |
2781 | n_regs += 2; | |
2782 | } | |
ab835497 | 2783 | } |
61a55e8b | 2784 | return n_regs; |
ab835497 RK |
2785 | } |
2786 | ||
2787 | /* Static variables we want to share between prologue and epilogue. */ | |
2788 | ||
61a55e8b DE |
2789 | /* Number of live general or floating point registers needed to be saved |
2790 | (as 4-byte quantities). This is only done if TARGET_EPILOGUE. */ | |
2791 | static int num_gfregs; | |
2792 | ||
2793 | /* Compute the frame size required by the function. This function is called | |
2794 | during the reload pass and also by output_function_prologue(). */ | |
ab835497 | 2795 | |
ab835497 RK |
2796 | int |
2797 | compute_frame_size (size, leaf_function) | |
2798 | int size; | |
2799 | int leaf_function; | |
2800 | { | |
61a55e8b | 2801 | int n_regs = 0, i; |
ab835497 | 2802 | int outgoing_args_size = (current_function_outgoing_args_size |
61a55e8b DE |
2803 | #ifndef SPARCV9 |
2804 | + REG_PARM_STACK_SPACE (current_function_decl) | |
2805 | #endif | |
2806 | ); | |
ab835497 | 2807 | |
61a55e8b | 2808 | if (TARGET_EPILOGUE) |
ab835497 | 2809 | { |
61a55e8b DE |
2810 | /* N_REGS is the number of 4-byte regs saved thus far. This applies |
2811 | even to v9 int regs to be consistent with save_regs/restore_regs. */ | |
2812 | ||
2813 | if (TARGET_V9) | |
2814 | { | |
2815 | for (i = 0; i < 8; i++) | |
2816 | if (regs_ever_live[i] && ! call_used_regs[i]) | |
2817 | n_regs += 2; | |
2818 | } | |
2819 | else | |
2820 | { | |
2821 | for (i = 0; i < 8; i += 2) | |
2822 | if ((regs_ever_live[i] && ! call_used_regs[i]) | |
2823 | || (regs_ever_live[i+1] && ! call_used_regs[i+1])) | |
2824 | n_regs += 2; | |
2825 | } | |
2826 | ||
2827 | for (i = 32; i < (TARGET_V9 ? 96 : 64); i += 2) | |
ab835497 RK |
2828 | if ((regs_ever_live[i] && ! call_used_regs[i]) |
2829 | || (regs_ever_live[i+1] && ! call_used_regs[i+1])) | |
61a55e8b | 2830 | n_regs += 2; |
ab835497 RK |
2831 | } |
2832 | ||
2833 | /* Set up values for use in `function_epilogue'. */ | |
61a55e8b | 2834 | num_gfregs = n_regs; |
ab835497 | 2835 | |
61a55e8b DE |
2836 | if (leaf_function && n_regs == 0 |
2837 | && size == 0 && current_function_outgoing_args_size == 0) | |
2838 | { | |
2839 | actual_fsize = apparent_fsize = 0; | |
2840 | } | |
2841 | else | |
2842 | { | |
2843 | /* We subtract STARTING_FRAME_OFFSET, remember it's negative. | |
2844 | The stack bias (if any) is taken out to undo its effects. */ | |
2845 | apparent_fsize = (size - STARTING_FRAME_OFFSET + SPARC_STACK_BIAS + 7) & -8; | |
2846 | apparent_fsize += n_regs * 4; | |
2847 | actual_fsize = apparent_fsize + ((outgoing_args_size + 7) & -8); | |
2848 | } | |
ab835497 RK |
2849 | |
2850 | /* Make sure nothing can clobber our register windows. | |
2851 | If a SAVE must be done, or there is a stack-local variable, | |
61a55e8b DE |
2852 | the register window area must be allocated. |
2853 | ??? For v9 we need an additional 8 bytes of reserved space, apparently | |
2854 | it's needed by v8 as well. */ | |
ab835497 | 2855 | if (leaf_function == 0 || size > 0) |
61a55e8b | 2856 | actual_fsize += (16 * UNITS_PER_WORD) + 8; |
ab835497 | 2857 | |
61a55e8b DE |
2858 | return SPARC_STACK_ALIGN (actual_fsize); |
2859 | } | |
2860 | ||
2861 | /* Build a (32 bit) big number in a register. */ | |
86735b02 | 2862 | /* ??? We may be able to use the set macro here too. */ |
61a55e8b DE |
2863 | |
2864 | static void | |
2865 | build_big_number (file, num, reg) | |
2866 | FILE *file; | |
2867 | int num; | |
2868 | char *reg; | |
2869 | { | |
2870 | if (num >= 0 || ! TARGET_V9) | |
2871 | { | |
2872 | fprintf (file, "\tsethi %%hi(%d),%s\n", num, reg); | |
2873 | if ((num & 0x3ff) != 0) | |
2874 | fprintf (file, "\tor %s,%%lo(%d),%s\n", reg, num, reg); | |
2875 | } | |
2876 | else /* num < 0 && TARGET_V9 */ | |
2877 | { | |
2878 | /* Sethi does not sign extend, so we must use a little trickery | |
2879 | to use it for negative numbers. Invert the constant before | |
2880 | loading it in, then use xor immediate to invert the loaded bits | |
2881 | (along with the upper 32 bits) to the desired constant. This | |
2882 | works because the sethi and immediate fields overlap. */ | |
2883 | int asize = num; | |
2884 | int inv = ~asize; | |
2885 | int low = -0x400 + (asize & 0x3FF); | |
2886 | ||
2887 | fprintf (file, "\tsethi %%hi(%d),%s\n\txor %s,%d,%s\n", | |
2888 | inv, reg, reg, low, reg); | |
2889 | } | |
ab835497 RK |
2890 | } |
2891 | ||
915f619f JW |
2892 | /* Output code for the function prologue. */ |
2893 | ||
ab835497 RK |
2894 | void |
2895 | output_function_prologue (file, size, leaf_function) | |
2896 | FILE *file; | |
2897 | int size; | |
915f619f | 2898 | int leaf_function; |
ab835497 | 2899 | { |
915f619f JW |
2900 | /* Need to use actual_fsize, since we are also allocating |
2901 | space for our callee (and our own register save area). */ | |
ab835497 RK |
2902 | actual_fsize = compute_frame_size (size, leaf_function); |
2903 | ||
61a55e8b DE |
2904 | if (leaf_function) |
2905 | { | |
2906 | frame_base_name = "%sp"; | |
2907 | frame_base_offset = actual_fsize + SPARC_STACK_BIAS; | |
2908 | } | |
2909 | else | |
2910 | { | |
2911 | frame_base_name = "%fp"; | |
2912 | frame_base_offset = SPARC_STACK_BIAS; | |
2913 | } | |
2914 | ||
c6aa9ce1 | 2915 | /* This is only for the human reader. */ |
ab835497 | 2916 | fprintf (file, "\t!#PROLOGUE# 0\n"); |
c6aa9ce1 | 2917 | |
915f619f JW |
2918 | if (actual_fsize == 0) |
2919 | /* do nothing. */ ; | |
2920 | else if (actual_fsize <= 4096) | |
ab835497 RK |
2921 | { |
2922 | if (! leaf_function) | |
2923 | fprintf (file, "\tsave %%sp,-%d,%%sp\n", actual_fsize); | |
2924 | else | |
2925 | fprintf (file, "\tadd %%sp,-%d,%%sp\n", actual_fsize); | |
2926 | } | |
915f619f | 2927 | else if (actual_fsize <= 8192) |
ab835497 | 2928 | { |
915f619f JW |
2929 | /* For frames in the range 4097..8192, we can use just two insns. */ |
2930 | if (! leaf_function) | |
2931 | { | |
2932 | fprintf (file, "\tsave %%sp,-4096,%%sp\n"); | |
2933 | fprintf (file, "\tadd %%sp,-%d,%%sp\n", actual_fsize - 4096); | |
2934 | } | |
2935 | else | |
2936 | { | |
2937 | fprintf (file, "\tadd %%sp,-4096,%%sp\n"); | |
2938 | fprintf (file, "\tadd %%sp,-%d,%%sp\n", actual_fsize - 4096); | |
2939 | } | |
ab835497 RK |
2940 | } |
2941 | else | |
2942 | { | |
61a55e8b | 2943 | build_big_number (file, -actual_fsize, "%g1"); |
915f619f | 2944 | if (! leaf_function) |
61a55e8b | 2945 | fprintf (file, "\tsave %%sp,%%g1,%%sp\n"); |
915f619f | 2946 | else |
61a55e8b | 2947 | fprintf (file, "\tadd %%sp,%%g1,%%sp\n"); |
ab835497 RK |
2948 | } |
2949 | ||
2950 | /* If doing anything with PIC, do it now. */ | |
2951 | if (! flag_pic) | |
2952 | fprintf (file, "\t!#PROLOGUE# 1\n"); | |
2953 | ||
61a55e8b DE |
2954 | /* Call saved registers are saved just above the outgoing argument area. */ |
2955 | if (num_gfregs) | |
ab835497 | 2956 | { |
61a55e8b DE |
2957 | int offset, n_regs; |
2958 | char *base; | |
ab835497 | 2959 | |
61a55e8b DE |
2960 | offset = -apparent_fsize + frame_base_offset; |
2961 | if (offset < -4096 || offset + num_gfregs * 4 > 4096) | |
2962 | { | |
2963 | /* ??? This might be optimized a little as %g1 might already have a | |
2964 | value close enough that a single add insn will do. */ | |
2965 | /* ??? Although, all of this is probably only a temporary fix | |
2966 | because if %g1 can hold a function result, then | |
2967 | output_function_epilogue will lose (the result will get | |
2968 | clobbered). */ | |
2969 | build_big_number (file, offset, "%g1"); | |
2970 | fprintf (file, "\tadd %s,%%g1,%%g1\n", frame_base_name); | |
2971 | base = "%g1"; | |
2972 | offset = 0; | |
2973 | } | |
ab835497 | 2974 | else |
61a55e8b DE |
2975 | { |
2976 | base = frame_base_name; | |
2977 | } | |
ab835497 RK |
2978 | |
2979 | if (TARGET_EPILOGUE && ! leaf_function) | |
61a55e8b DE |
2980 | /* ??? Originally saved regs 0-15 here. */ |
2981 | n_regs = save_regs (file, 0, 8, base, offset, 0); | |
ab835497 | 2982 | else if (leaf_function) |
61a55e8b DE |
2983 | /* ??? Originally saved regs 0-31 here. */ |
2984 | n_regs = save_regs (file, 0, 8, base, offset, 0); | |
ab835497 | 2985 | if (TARGET_EPILOGUE) |
61a55e8b | 2986 | save_regs (file, 32, TARGET_V9 ? 96 : 64, base, offset, n_regs); |
ab835497 RK |
2987 | } |
2988 | ||
ab835497 RK |
2989 | leaf_label = 0; |
2990 | if (leaf_function && actual_fsize != 0) | |
2991 | { | |
2992 | /* warning ("leaf procedure with frame size %d", actual_fsize); */ | |
2993 | if (! TARGET_EPILOGUE) | |
2994 | leaf_label = gen_label_rtx (); | |
2995 | } | |
2996 | } | |
2997 | ||
915f619f JW |
2998 | /* Output code for the function epilogue. */ |
2999 | ||
ab835497 | 3000 | void |
ef8200df | 3001 | output_function_epilogue (file, size, leaf_function) |
ab835497 RK |
3002 | FILE *file; |
3003 | int size; | |
ef8200df | 3004 | int leaf_function; |
ab835497 | 3005 | { |
ab835497 RK |
3006 | char *ret; |
3007 | ||
3008 | if (leaf_label) | |
3009 | { | |
ab835497 RK |
3010 | emit_label_after (leaf_label, get_last_insn ()); |
3011 | final_scan_insn (get_last_insn (), file, 0, 0, 1); | |
3012 | } | |
3013 | ||
61a55e8b DE |
3014 | /* Restore any call saved registers. */ |
3015 | if (num_gfregs) | |
ab835497 | 3016 | { |
61a55e8b DE |
3017 | int offset, n_regs; |
3018 | char *base; | |
ab835497 | 3019 | |
61a55e8b DE |
3020 | offset = -apparent_fsize + frame_base_offset; |
3021 | if (offset < -4096 || offset + num_gfregs * 4 > 4096 - 8 /*double*/) | |
3022 | { | |
3023 | build_big_number (file, offset, "%g1"); | |
3024 | fprintf (file, "\tadd %s,%%g1,%%g1\n", frame_base_name); | |
3025 | base = "%g1"; | |
3026 | offset = 0; | |
3027 | } | |
ab835497 | 3028 | else |
61a55e8b DE |
3029 | { |
3030 | base = frame_base_name; | |
3031 | } | |
ab835497 RK |
3032 | |
3033 | if (TARGET_EPILOGUE && ! leaf_function) | |
61a55e8b DE |
3034 | /* ??? Originally saved regs 0-15 here. */ |
3035 | n_regs = restore_regs (file, 0, 8, base, offset, 0); | |
ab835497 | 3036 | else if (leaf_function) |
61a55e8b DE |
3037 | /* ??? Originally saved regs 0-31 here. */ |
3038 | n_regs = restore_regs (file, 0, 8, base, offset, 0); | |
ab835497 | 3039 | if (TARGET_EPILOGUE) |
61a55e8b | 3040 | restore_regs (file, 32, TARGET_V9 ? 96 : 64, base, offset, n_regs); |
ab835497 RK |
3041 | } |
3042 | ||
3043 | /* Work out how to skip the caller's unimp instruction if required. */ | |
3044 | if (leaf_function) | |
61a55e8b | 3045 | ret = (SKIP_CALLERS_UNIMP_P ? "jmp %o7+12" : "retl"); |
ab835497 | 3046 | else |
61a55e8b | 3047 | ret = (SKIP_CALLERS_UNIMP_P ? "jmp %i7+12" : "ret"); |
ab835497 | 3048 | |
ef8200df | 3049 | if (TARGET_EPILOGUE || leaf_label) |
ab835497 | 3050 | { |
ef8200df JW |
3051 | int old_target_epilogue = TARGET_EPILOGUE; |
3052 | target_flags &= ~old_target_epilogue; | |
ab835497 | 3053 | |
ef8200df JW |
3054 | if (! leaf_function) |
3055 | { | |
3056 | /* If we wound up with things in our delay slot, flush them here. */ | |
3057 | if (current_function_epilogue_delay_list) | |
ab835497 | 3058 | { |
ef8200df JW |
3059 | rtx insn = emit_jump_insn_after (gen_rtx (RETURN, VOIDmode), |
3060 | get_last_insn ()); | |
3061 | PATTERN (insn) = gen_rtx (PARALLEL, VOIDmode, | |
3062 | gen_rtvec (2, | |
3063 | PATTERN (XEXP (current_function_epilogue_delay_list, 0)), | |
3064 | PATTERN (insn))); | |
3065 | final_scan_insn (insn, file, 1, 0, 1); | |
ab835497 RK |
3066 | } |
3067 | else | |
ef8200df JW |
3068 | fprintf (file, "\t%s\n\trestore\n", ret); |
3069 | } | |
915f619f JW |
3070 | /* All of the following cases are for leaf functions. */ |
3071 | else if (current_function_epilogue_delay_list) | |
ef8200df | 3072 | { |
915f619f JW |
3073 | /* eligible_for_epilogue_delay_slot ensures that if this is a |
3074 | leaf function, then we will only have insn in the delay slot | |
3075 | if the frame size is zero, thus no adjust for the stack is | |
3076 | needed here. */ | |
3077 | if (actual_fsize != 0) | |
ef8200df | 3078 | abort (); |
915f619f JW |
3079 | fprintf (file, "\t%s\n", ret); |
3080 | final_scan_insn (XEXP (current_function_epilogue_delay_list, 0), | |
3081 | file, 1, 0, 1); | |
ab835497 | 3082 | } |
9bb7ffda JW |
3083 | /* Output 'nop' instead of 'sub %sp,-0,%sp' when no frame, so as to |
3084 | avoid generating confusing assembly language output. */ | |
3085 | else if (actual_fsize == 0) | |
3086 | fprintf (file, "\t%s\n\tnop\n", ret); | |
915f619f JW |
3087 | else if (actual_fsize <= 4096) |
3088 | fprintf (file, "\t%s\n\tsub %%sp,-%d,%%sp\n", ret, actual_fsize); | |
3089 | else if (actual_fsize <= 8192) | |
3090 | fprintf (file, "\tsub %%sp,-4096,%%sp\n\t%s\n\tsub %%sp,-%d,%%sp\n", | |
3091 | ret, actual_fsize - 4096); | |
3092 | else if ((actual_fsize & 0x3ff) == 0) | |
3093 | fprintf (file, "\tsethi %%hi(%d),%%g1\n\t%s\n\tadd %%sp,%%g1,%%sp\n", | |
3094 | actual_fsize, ret); | |
3095 | else | |
3096 | fprintf (file, "\tsethi %%hi(%d),%%g1\n\tor %%g1,%%lo(%d),%%g1\n\t%s\n\tadd %%sp,%%g1,%%sp\n", | |
3097 | actual_fsize, actual_fsize, ret); | |
ef8200df | 3098 | target_flags |= old_target_epilogue; |
ab835497 RK |
3099 | } |
3100 | } | |
3ea1fdd3 | 3101 | |
61a55e8b DE |
3102 | /* Do what is necessary for `va_start'. The argument is ignored. |
3103 | !v9: We look at the current function to determine if stdarg or varargs | |
3104 | is used and return the address of the first unnamed parameter. | |
3105 | v9: We save the argument integer and floating point regs in a buffer, and | |
3106 | return the address of this buffer. The rest is handled in va-sparc.h. */ | |
3107 | /* ??? This is currently conditioned on #ifdef SPARCV9 because | |
3108 | current_function_args_info is different in each compiler. */ | |
3109 | ||
3110 | #ifdef SPARCV9 | |
3111 | ||
3112 | rtx | |
3113 | sparc_builtin_saveregs (arglist) | |
3114 | tree arglist; | |
3115 | { | |
3116 | tree fntype = TREE_TYPE (current_function_decl); | |
3117 | /* First unnamed integer register. */ | |
a7acd911 | 3118 | int first_intreg = current_function_args_info.arg_count[(int) SPARC_ARG_INT]; |
61a55e8b DE |
3119 | /* Number of integer registers we need to save. */ |
3120 | int n_intregs = MAX (0, NPARM_REGS (SImode) - first_intreg); | |
3121 | /* First unnamed SFmode float reg (no, you can't pass SFmode floats as | |
a7acd911 DE |
3122 | unnamed arguments, we just number them that way). We must round up to |
3123 | the next double word float reg - that is the first one to save. */ | |
3124 | int first_floatreg = current_function_args_info.arg_count[(int) SPARC_ARG_FLOAT] + 1 & ~1; | |
61a55e8b DE |
3125 | /* Number of SFmode float regs to save. */ |
3126 | int n_floatregs = MAX (0, NPARM_REGS (SFmode) - first_floatreg); | |
3127 | int ptrsize = GET_MODE_SIZE (Pmode); | |
3128 | rtx valist, regbuf, fpregs; | |
a7acd911 | 3129 | int bufsize, adjust, regno; |
61a55e8b DE |
3130 | |
3131 | /* Allocate block of memory for the regs. | |
a7acd911 DE |
3132 | We only allocate as much as we need, but we must ensure quadword float |
3133 | regs are stored with the appropriate alignment. */ | |
61a55e8b DE |
3134 | /* ??? If n_intregs + n_floatregs == 0, should we allocate at least 1 byte? |
3135 | Or can assign_stack_local accept a 0 SIZE argument? */ | |
3136 | ||
a7acd911 DE |
3137 | bufsize = (n_intregs * UNITS_PER_WORD) + (n_floatregs * (UNITS_PER_WORD / 2)); |
3138 | /* Add space in front of the int regs to ensure proper alignment of quadword | |
3139 | fp regs. We must add the space in front because va_start assumes this. */ | |
3140 | if (n_floatregs >= 4) | |
3141 | adjust = ((n_intregs + first_floatreg / 2) % 2) * UNITS_PER_WORD; | |
3142 | else | |
3143 | adjust = 0; | |
3144 | ||
3145 | regbuf = assign_stack_local (BLKmode, bufsize + adjust, | |
3146 | GET_MODE_BITSIZE (TFmode)); | |
3147 | regbuf = gen_rtx (MEM, BLKmode, plus_constant (XEXP (regbuf, 0), adjust)); | |
61a55e8b DE |
3148 | MEM_IN_STRUCT_P (regbuf) = 1; |
3149 | ||
3150 | /* Save int args. | |
3151 | This is optimized to only save the regs that are necessary. Explicitly | |
3152 | named args need not be saved. */ | |
3153 | ||
3154 | if (n_intregs > 0) | |
3155 | move_block_from_reg (BASE_INCOMING_ARG_REG (SImode) + first_intreg, | |
3156 | regbuf, n_intregs, n_intregs * UNITS_PER_WORD); | |
3157 | ||
3158 | /* Save float args. | |
3159 | This is optimized to only save the regs that are necessary. Explicitly | |
3160 | named args need not be saved. | |
3161 | We explicitly build a pointer to the buffer because it halves the insn | |
3162 | count when not optimizing (otherwise the pointer is built for each reg | |
3163 | saved). */ | |
3164 | ||
3165 | fpregs = gen_reg_rtx (Pmode); | |
3166 | emit_move_insn (fpregs, plus_constant (XEXP (regbuf, 0), | |
3167 | n_intregs * UNITS_PER_WORD)); | |
3168 | for (regno = first_floatreg; regno < NPARM_REGS (SFmode); regno += 2) | |
3169 | emit_move_insn (gen_rtx (MEM, DFmode, | |
3170 | plus_constant (fpregs, | |
a7acd911 DE |
3171 | GET_MODE_SIZE (SFmode) |
3172 | * (regno - first_floatreg))), | |
3173 | gen_rtx (REG, DFmode, | |
3174 | BASE_INCOMING_ARG_REG (DFmode) + regno)); | |
61a55e8b DE |
3175 | |
3176 | /* Return the address of the regbuf. */ | |
3177 | ||
3178 | return XEXP (regbuf, 0); | |
3179 | } | |
3180 | ||
3181 | #else /* ! SPARCV9 */ | |
3ea1fdd3 JW |
3182 | |
3183 | rtx | |
3184 | sparc_builtin_saveregs (arglist) | |
3185 | tree arglist; | |
3186 | { | |
3187 | tree fntype = TREE_TYPE (current_function_decl); | |
3188 | int stdarg = (TYPE_ARG_TYPES (fntype) != 0 | |
3189 | && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype))) | |
3190 | != void_type_node)); | |
3191 | int first_reg = current_function_args_info; | |
3192 | rtx address; | |
3193 | int regno; | |
3194 | ||
227f7fd9 RS |
3195 | #if 0 /* This code seemed to have no effect except to make |
3196 | varargs not work right when va_list wasn't the first arg. */ | |
3ea1fdd3 JW |
3197 | if (! stdarg) |
3198 | first_reg = 0; | |
227f7fd9 | 3199 | #endif |
3ea1fdd3 | 3200 | |
61a55e8b | 3201 | for (regno = first_reg; regno < NPARM_REGS (SImode); regno++) |
3ea1fdd3 JW |
3202 | emit_move_insn (gen_rtx (MEM, word_mode, |
3203 | gen_rtx (PLUS, Pmode, | |
3204 | frame_pointer_rtx, | |
3205 | GEN_INT (STACK_POINTER_OFFSET | |
3206 | + UNITS_PER_WORD * regno))), | |
3207 | gen_rtx (REG, word_mode, BASE_INCOMING_ARG_REG (word_mode) | |
3208 | + regno)); | |
3209 | ||
3210 | address = gen_rtx (PLUS, Pmode, | |
3211 | frame_pointer_rtx, | |
3212 | GEN_INT (STACK_POINTER_OFFSET | |
3213 | + UNITS_PER_WORD * first_reg)); | |
3214 | ||
3215 | return address; | |
3216 | } | |
61a55e8b DE |
3217 | |
3218 | #endif /* ! SPARCV9 */ | |
ab835497 RK |
3219 | \f |
3220 | /* Return the string to output a conditional branch to LABEL, which is | |
3221 | the operand number of the label. OP is the conditional expression. The | |
3222 | mode of register 0 says what kind of comparison we made. | |
3223 | ||
61a55e8b DE |
3224 | FP_COND_REG indicates which fp condition code register to use if this is |
3225 | a floating point branch. | |
3226 | ||
ab835497 RK |
3227 | REVERSED is non-zero if we should reverse the sense of the comparison. |
3228 | ||
3229 | ANNUL is non-zero if we should generate an annulling branch. | |
3230 | ||
3231 | NOOP is non-zero if we have to follow this branch by a noop. */ | |
3232 | ||
3233 | char * | |
61a55e8b DE |
3234 | output_cbranch (op, fp_cond_reg, label, reversed, annul, noop) |
3235 | rtx op, fp_cond_reg; | |
ab835497 RK |
3236 | int label; |
3237 | int reversed, annul, noop; | |
3238 | { | |
3239 | static char string[20]; | |
3240 | enum rtx_code code = GET_CODE (op); | |
3241 | enum machine_mode mode = GET_MODE (XEXP (op, 0)); | |
61a55e8b DE |
3242 | static char v8_labelno[] = " %lX"; |
3243 | static char v9_icc_labelno[] = " %%icc,%lX"; | |
3244 | static char v9_xcc_labelno[] = " %%xcc,%lX"; | |
3245 | static char v9_fcc_labelno[] = " %%fccX,%lY"; | |
3246 | char *labelno; | |
3247 | int labeloff; | |
3248 | ||
3249 | /* ??? !v9: FP branches cannot be preceded by another floating point insn. | |
ab835497 RK |
3250 | Because there is currently no concept of pre-delay slots, we can fix |
3251 | this only by always emitting a nop before a floating point branch. */ | |
3252 | ||
61a55e8b | 3253 | if ((mode == CCFPmode || mode == CCFPEmode) && ! TARGET_V9) |
ab835497 | 3254 | strcpy (string, "nop\n\t"); |
61a55e8b DE |
3255 | else |
3256 | string[0] = '\0'; | |
ab835497 RK |
3257 | |
3258 | /* If not floating-point or if EQ or NE, we can just reverse the code. */ | |
4d449554 JW |
3259 | if (reversed |
3260 | && ((mode != CCFPmode && mode != CCFPEmode) || code == EQ || code == NE)) | |
ab835497 RK |
3261 | code = reverse_condition (code), reversed = 0; |
3262 | ||
3263 | /* Start by writing the branch condition. */ | |
3264 | switch (code) | |
3265 | { | |
3266 | case NE: | |
4d449554 | 3267 | if (mode == CCFPmode || mode == CCFPEmode) |
ab835497 RK |
3268 | strcat (string, "fbne"); |
3269 | else | |
3270 | strcpy (string, "bne"); | |
3271 | break; | |
3272 | ||
3273 | case EQ: | |
4d449554 | 3274 | if (mode == CCFPmode || mode == CCFPEmode) |
ab835497 RK |
3275 | strcat (string, "fbe"); |
3276 | else | |
3277 | strcpy (string, "be"); | |
3278 | break; | |
3279 | ||
3280 | case GE: | |
4d449554 | 3281 | if (mode == CCFPmode || mode == CCFPEmode) |
ab835497 RK |
3282 | { |
3283 | if (reversed) | |
3284 | strcat (string, "fbul"); | |
3285 | else | |
3286 | strcat (string, "fbge"); | |
3287 | } | |
3288 | else if (mode == CC_NOOVmode) | |
3289 | strcpy (string, "bpos"); | |
3290 | else | |
3291 | strcpy (string, "bge"); | |
3292 | break; | |
3293 | ||
3294 | case GT: | |
4d449554 | 3295 | if (mode == CCFPmode || mode == CCFPEmode) |
ab835497 RK |
3296 | { |
3297 | if (reversed) | |
3298 | strcat (string, "fbule"); | |
3299 | else | |
3300 | strcat (string, "fbg"); | |
3301 | } | |
3302 | else | |
3303 | strcpy (string, "bg"); | |
3304 | break; | |
3305 | ||
3306 | case LE: | |
4d449554 | 3307 | if (mode == CCFPmode || mode == CCFPEmode) |
ab835497 RK |
3308 | { |
3309 | if (reversed) | |
3310 | strcat (string, "fbug"); | |
3311 | else | |
3312 | strcat (string, "fble"); | |
3313 | } | |
3314 | else | |
3315 | strcpy (string, "ble"); | |
3316 | break; | |
3317 | ||
3318 | case LT: | |
4d449554 | 3319 | if (mode == CCFPmode || mode == CCFPEmode) |
ab835497 RK |
3320 | { |
3321 | if (reversed) | |
3322 | strcat (string, "fbuge"); | |
3323 | else | |
3324 | strcat (string, "fbl"); | |
3325 | } | |
3326 | else if (mode == CC_NOOVmode) | |
3327 | strcpy (string, "bneg"); | |
3328 | else | |
3329 | strcpy (string, "bl"); | |
3330 | break; | |
3331 | ||
3332 | case GEU: | |
3333 | strcpy (string, "bgeu"); | |
3334 | break; | |
3335 | ||
3336 | case GTU: | |
3337 | strcpy (string, "bgu"); | |
3338 | break; | |
3339 | ||
3340 | case LEU: | |
3341 | strcpy (string, "bleu"); | |
3342 | break; | |
3343 | ||
3344 | case LTU: | |
3345 | strcpy (string, "blu"); | |
3346 | break; | |
3347 | } | |
3348 | ||
3349 | /* Now add the annulling, the label, and a possible noop. */ | |
3350 | if (annul) | |
3351 | strcat (string, ",a"); | |
3352 | ||
61a55e8b DE |
3353 | /* ??? If v9, optional prediction bit ",pt" or ",pf" goes here. */ |
3354 | ||
3355 | if (! TARGET_V9) | |
3356 | { | |
3357 | labeloff = 3; | |
3358 | labelno = v8_labelno; | |
3359 | } | |
3360 | else | |
3361 | { | |
3362 | labeloff = 9; | |
3363 | if (mode == CCFPmode || mode == CCFPEmode) | |
3364 | { | |
3365 | labeloff = 10; | |
3366 | labelno = v9_fcc_labelno; | |
3367 | /* Set the char indicating the number of the fcc reg to use. */ | |
3368 | labelno[6] = REGNO (fp_cond_reg) - 96 + '0'; | |
3369 | } | |
3370 | else if (mode == CCXmode || mode == CCX_NOOVmode) | |
3371 | labelno = v9_xcc_labelno; | |
3372 | else | |
3373 | labelno = v9_icc_labelno; | |
3374 | } | |
3375 | /* Set the char indicating the number of the operand containing the | |
3376 | label_ref. */ | |
3377 | labelno[labeloff] = label + '0'; | |
3378 | strcat (string, labelno); | |
3379 | ||
3380 | if (noop) | |
3381 | strcat (string, "\n\tnop"); | |
3382 | ||
3383 | return string; | |
3384 | } | |
3385 | ||
3386 | /* Return the string to output a conditional branch to LABEL, testing | |
3387 | register REG. LABEL is the operand number of the label; REG is the | |
3388 | operand number of the reg. OP is the conditional expression. The mode | |
3389 | of REG says what kind of comparison we made. | |
3390 | ||
3391 | REVERSED is non-zero if we should reverse the sense of the comparison. | |
3392 | ||
3393 | ANNUL is non-zero if we should generate an annulling branch. | |
3394 | ||
3395 | NOOP is non-zero if we have to follow this branch by a noop. */ | |
3396 | ||
3397 | char * | |
3398 | output_v9branch (op, reg, label, reversed, annul, noop) | |
3399 | rtx op; | |
3400 | int reg, label; | |
3401 | int reversed, annul, noop; | |
3402 | { | |
3403 | static char string[20]; | |
3404 | enum rtx_code code = GET_CODE (op); | |
3405 | enum machine_mode mode = GET_MODE (XEXP (op, 0)); | |
3406 | static char labelno[] = " %X,%lX"; | |
3407 | ||
3408 | /* If not floating-point or if EQ or NE, we can just reverse the code. */ | |
3409 | if (reversed) | |
3410 | code = reverse_condition (code), reversed = 0; | |
3411 | ||
3412 | /* Only 64 bit versions of these instructions exist. */ | |
3413 | if (mode != DImode) | |
3414 | abort (); | |
3415 | ||
3416 | /* Start by writing the branch condition. */ | |
3417 | ||
3418 | switch (code) | |
3419 | { | |
3420 | case NE: | |
3421 | strcpy (string, "brnz"); | |
3422 | break; | |
3423 | ||
3424 | case EQ: | |
3425 | strcpy (string, "brz"); | |
3426 | break; | |
3427 | ||
3428 | case GE: | |
3429 | strcpy (string, "brgez"); | |
3430 | break; | |
3431 | ||
3432 | case LT: | |
3433 | strcpy (string, "brlz"); | |
3434 | break; | |
3435 | ||
3436 | case LE: | |
3437 | strcpy (string, "brlez"); | |
3438 | break; | |
3439 | ||
3440 | case GT: | |
3441 | strcpy (string, "brgz"); | |
3442 | break; | |
3443 | ||
3444 | default: | |
3445 | abort (); | |
3446 | } | |
3447 | ||
3448 | /* Now add the annulling, reg, label, and nop. */ | |
3449 | if (annul) | |
3450 | strcat (string, ",a"); | |
3451 | ||
3452 | /* ??? Optional prediction bit ",pt" or ",pf" goes here. */ | |
3453 | ||
3454 | labelno[2] = reg + '0'; | |
3455 | labelno[6] = label + '0'; | |
ab835497 RK |
3456 | strcat (string, labelno); |
3457 | ||
3458 | if (noop) | |
3459 | strcat (string, "\n\tnop"); | |
3460 | ||
3461 | return string; | |
3462 | } | |
3463 | ||
795068a4 JW |
3464 | /* Output assembler code to return from a function. */ |
3465 | ||
61a55e8b DE |
3466 | /* ??? v9: Update to use the new `return' instruction. Also, add patterns to |
3467 | md file for the `return' instruction. */ | |
3468 | ||
ab835497 RK |
3469 | char * |
3470 | output_return (operands) | |
3471 | rtx *operands; | |
3472 | { | |
3473 | if (leaf_label) | |
3474 | { | |
3475 | operands[0] = leaf_label; | |
3476 | return "b,a %l0"; | |
3477 | } | |
3478 | else if (leaf_function) | |
3479 | { | |
915f619f JW |
3480 | /* If we didn't allocate a frame pointer for the current function, |
3481 | the stack pointer might have been adjusted. Output code to | |
3482 | restore it now. */ | |
3483 | ||
ab835497 | 3484 | operands[0] = gen_rtx (CONST_INT, VOIDmode, actual_fsize); |
915f619f JW |
3485 | |
3486 | /* Use sub of negated value in first two cases instead of add to | |
3487 | allow actual_fsize == 4096. */ | |
3488 | ||
3489 | if (actual_fsize <= 4096) | |
ab835497 | 3490 | { |
61a55e8b | 3491 | if (SKIP_CALLERS_UNIMP_P) |
915f619f | 3492 | return "jmp %%o7+12\n\tsub %%sp,-%0,%%sp"; |
ab835497 | 3493 | else |
915f619f | 3494 | return "retl\n\tsub %%sp,-%0,%%sp"; |
ab835497 | 3495 | } |
915f619f | 3496 | else if (actual_fsize <= 8192) |
ab835497 | 3497 | { |
915f619f | 3498 | operands[0] = gen_rtx (CONST_INT, VOIDmode, actual_fsize - 4096); |
61a55e8b | 3499 | if (SKIP_CALLERS_UNIMP_P) |
915f619f JW |
3500 | return "sub %%sp,-4096,%%sp\n\tjmp %%o7+12\n\tsub %%sp,-%0,%%sp"; |
3501 | else | |
3502 | return "sub %%sp,-4096,%%sp\n\tretl\n\tsub %%sp,-%0,%%sp"; | |
3503 | } | |
61a55e8b | 3504 | else if (SKIP_CALLERS_UNIMP_P) |
915f619f JW |
3505 | { |
3506 | if ((actual_fsize & 0x3ff) != 0) | |
ab835497 RK |
3507 | return "sethi %%hi(%a0),%%g1\n\tor %%g1,%%lo(%a0),%%g1\n\tjmp %%o7+12\n\tadd %%sp,%%g1,%%sp"; |
3508 | else | |
915f619f JW |
3509 | return "sethi %%hi(%a0),%%g1\n\tjmp %%o7+12\n\tadd %%sp,%%g1,%%sp"; |
3510 | } | |
3511 | else | |
3512 | { | |
3513 | if ((actual_fsize & 0x3ff) != 0) | |
ab835497 | 3514 | return "sethi %%hi(%a0),%%g1\n\tor %%g1,%%lo(%a0),%%g1\n\tretl\n\tadd %%sp,%%g1,%%sp"; |
915f619f JW |
3515 | else |
3516 | return "sethi %%hi(%a0),%%g1\n\tretl\n\tadd %%sp,%%g1,%%sp"; | |
ab835497 RK |
3517 | } |
3518 | } | |
3519 | else | |
3520 | { | |
61a55e8b | 3521 | if (SKIP_CALLERS_UNIMP_P) |
ab835497 RK |
3522 | return "jmp %%i7+12\n\trestore"; |
3523 | else | |
3524 | return "ret\n\trestore"; | |
3525 | } | |
3526 | } | |
ab835497 RK |
3527 | \f |
3528 | /* Leaf functions and non-leaf functions have different needs. */ | |
3529 | ||
3530 | static int | |
3531 | reg_leaf_alloc_order[] = REG_LEAF_ALLOC_ORDER; | |
3532 | ||
3533 | static int | |
3534 | reg_nonleaf_alloc_order[] = REG_ALLOC_ORDER; | |
3535 | ||
3536 | static int *reg_alloc_orders[] = { | |
3537 | reg_leaf_alloc_order, | |
3538 | reg_nonleaf_alloc_order}; | |
3539 | ||
3540 | void | |
3541 | order_regs_for_local_alloc () | |
3542 | { | |
3543 | static int last_order_nonleaf = 1; | |
3544 | ||
3545 | if (regs_ever_live[15] != last_order_nonleaf) | |
3546 | { | |
3547 | last_order_nonleaf = !last_order_nonleaf; | |
d2889939 RK |
3548 | bcopy ((char *) reg_alloc_orders[last_order_nonleaf], |
3549 | (char *) reg_alloc_order, FIRST_PSEUDO_REGISTER * sizeof (int)); | |
ab835497 RK |
3550 | } |
3551 | } | |
3552 | \f | |
35016322 JW |
3553 | /* Return 1 if REGNO (reg1) is even and REGNO (reg1) == REGNO (reg2) - 1. |
3554 | This makes them candidates for using ldd and std insns. | |
3555 | ||
3556 | Note reg1 and reg2 *must* be hard registers. To be sure we will | |
3557 | abort if we are passed pseudo registers. */ | |
3558 | ||
3559 | int | |
7c56249d | 3560 | registers_ok_for_ldd_peep (reg1, reg2) |
35016322 JW |
3561 | rtx reg1, reg2; |
3562 | { | |
35016322 JW |
3563 | /* We might have been passed a SUBREG. */ |
3564 | if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG) | |
3565 | return 0; | |
3566 | ||
35016322 JW |
3567 | if (REGNO (reg1) % 2 != 0) |
3568 | return 0; | |
3569 | ||
3570 | return (REGNO (reg1) == REGNO (reg2) - 1); | |
35016322 JW |
3571 | } |
3572 | ||
3573 | /* Return 1 if addr1 and addr2 are suitable for use in an ldd or | |
3574 | std insn. | |
3575 | ||
3576 | This can only happen when addr1 and addr2 are consecutive memory | |
3577 | locations (addr1 + 4 == addr2). addr1 must also be aligned on a | |
3578 | 64 bit boundary (addr1 % 8 == 0). | |
3579 | ||
3580 | We know %sp and %fp are kept aligned on a 64 bit boundary. Other | |
3581 | registers are assumed to *never* be properly aligned and are | |
3582 | rejected. | |
3583 | ||
3584 | Knowing %sp and %fp are kept aligned on a 64 bit boundary, we | |
3585 | need only check that the offset for addr1 % 8 == 0. */ | |
3586 | ||
3587 | int | |
7c56249d | 3588 | addrs_ok_for_ldd_peep (addr1, addr2) |
35016322 JW |
3589 | rtx addr1, addr2; |
3590 | { | |
3591 | int reg1, offset1; | |
3592 | ||
3593 | /* Extract a register number and offset (if used) from the first addr. */ | |
3594 | if (GET_CODE (addr1) == PLUS) | |
3595 | { | |
3596 | /* If not a REG, return zero. */ | |
3597 | if (GET_CODE (XEXP (addr1, 0)) != REG) | |
3598 | return 0; | |
3599 | else | |
3600 | { | |
3601 | reg1 = REGNO (XEXP (addr1, 0)); | |
3602 | /* The offset must be constant! */ | |
3603 | if (GET_CODE (XEXP (addr1, 1)) != CONST_INT) | |
3604 | return 0; | |
3605 | offset1 = INTVAL (XEXP (addr1, 1)); | |
3606 | } | |
3607 | } | |
3608 | else if (GET_CODE (addr1) != REG) | |
3609 | return 0; | |
3610 | else | |
3611 | { | |
3612 | reg1 = REGNO (addr1); | |
3613 | /* This was a simple (mem (reg)) expression. Offset is 0. */ | |
3614 | offset1 = 0; | |
3615 | } | |
3616 | ||
3617 | /* Make sure the second address is a (mem (plus (reg) (const_int). */ | |
3618 | if (GET_CODE (addr2) != PLUS) | |
3619 | return 0; | |
3620 | ||
3621 | if (GET_CODE (XEXP (addr2, 0)) != REG | |
3622 | || GET_CODE (XEXP (addr2, 1)) != CONST_INT) | |
3623 | return 0; | |
3624 | ||
3625 | /* Only %fp and %sp are allowed. Additionally both addresses must | |
3626 | use the same register. */ | |
3627 | if (reg1 != FRAME_POINTER_REGNUM && reg1 != STACK_POINTER_REGNUM) | |
3628 | return 0; | |
3629 | ||
3630 | if (reg1 != REGNO (XEXP (addr2, 0))) | |
3631 | return 0; | |
3632 | ||
2296cba3 | 3633 | /* The first offset must be evenly divisible by 8 to ensure the |
35016322 JW |
3634 | address is 64 bit aligned. */ |
3635 | if (offset1 % 8 != 0) | |
3636 | return 0; | |
3637 | ||
3638 | /* The offset for the second addr must be 4 more than the first addr. */ | |
3639 | if (INTVAL (XEXP (addr2, 1)) != offset1 + 4) | |
3640 | return 0; | |
3641 | ||
3642 | /* All the tests passed. addr1 and addr2 are valid for ldd and std | |
3643 | instructions. */ | |
3644 | return 1; | |
3645 | } | |
7c56249d JL |
3646 | |
3647 | /* Return 1 if reg is a pseudo, or is the first register in | |
3648 | a hard register pair. This makes it a candidate for use in | |
3649 | ldd and std insns. */ | |
3650 | ||
3651 | int | |
3652 | register_ok_for_ldd (reg) | |
3653 | rtx reg; | |
3654 | { | |
7c56249d JL |
3655 | /* We might have been passed a SUBREG. */ |
3656 | if (GET_CODE (reg) != REG) | |
3657 | return 0; | |
3658 | ||
3659 | if (REGNO (reg) < FIRST_PSEUDO_REGISTER) | |
3660 | return (REGNO (reg) % 2 == 0); | |
3661 | else | |
3662 | return 1; | |
7c56249d | 3663 | } |
ab835497 | 3664 | \f |
ab835497 RK |
3665 | /* Print operand X (an rtx) in assembler syntax to file FILE. |
3666 | CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. | |
3667 | For `%' followed by punctuation, CODE is the punctuation and X is null. */ | |
3668 | ||
3669 | void | |
3670 | print_operand (file, x, code) | |
3671 | FILE *file; | |
3672 | rtx x; | |
3673 | int code; | |
3674 | { | |
3675 | switch (code) | |
3676 | { | |
3677 | case '#': | |
3678 | /* Output a 'nop' if there's nothing for the delay slot. */ | |
3679 | if (dbr_sequence_length () == 0) | |
3680 | fputs ("\n\tnop", file); | |
3681 | return; | |
3682 | case '*': | |
c6ce0969 JW |
3683 | /* Output an annul flag if there's nothing for the delay slot and we |
3684 | are optimizing. This is always used with '(' below. */ | |
3685 | /* Sun OS 4.1.1 dbx can't handle an annulled unconditional branch; | |
3686 | this is a dbx bug. So, we only do this when optimizing. */ | |
3687 | if (dbr_sequence_length () == 0 && optimize) | |
3688 | fputs (",a", file); | |
3689 | return; | |
3690 | case '(': | |
3691 | /* Output a 'nop' if there's nothing for the delay slot and we are | |
3692 | not optimizing. This is always used with '*' above. */ | |
3693 | if (dbr_sequence_length () == 0 && ! optimize) | |
3694 | fputs ("\n\tnop", file); | |
ab835497 | 3695 | return; |
61a55e8b DE |
3696 | case '_': |
3697 | /* Output the Medium/Anywhere code model base register. */ | |
3698 | fputs (MEDANY_BASE_REG, file); | |
3699 | return; | |
3700 | case '@': | |
3701 | /* Print out what we are using as the frame pointer. This might | |
3702 | be %fp, or might be %sp+offset. */ | |
3703 | /* ??? What if offset is too big? Perhaps the caller knows it isn't? */ | |
3704 | fprintf (file, "%s+%d", frame_base_name, frame_base_offset); | |
3705 | return; | |
ab835497 RK |
3706 | case 'Y': |
3707 | /* Adjust the operand to take into account a RESTORE operation. */ | |
3708 | if (GET_CODE (x) != REG) | |
b3b1e8bd JW |
3709 | output_operand_lossage ("Invalid %%Y operand"); |
3710 | else if (REGNO (x) < 8) | |
ab835497 RK |
3711 | fputs (reg_names[REGNO (x)], file); |
3712 | else if (REGNO (x) >= 24 && REGNO (x) < 32) | |
3713 | fputs (reg_names[REGNO (x)-16], file); | |
3714 | else | |
b3b1e8bd | 3715 | output_operand_lossage ("Invalid %%Y operand"); |
ab835497 | 3716 | return; |
ab835497 | 3717 | case 'R': |
795068a4 | 3718 | /* Print out the second register name of a register pair or quad. |
ab835497 RK |
3719 | I.e., R (%o0) => %o1. */ |
3720 | fputs (reg_names[REGNO (x)+1], file); | |
3721 | return; | |
795068a4 JW |
3722 | case 'S': |
3723 | /* Print out the third register name of a register quad. | |
3724 | I.e., S (%o0) => %o2. */ | |
3725 | fputs (reg_names[REGNO (x)+2], file); | |
3726 | return; | |
3727 | case 'T': | |
3728 | /* Print out the fourth register name of a register quad. | |
3729 | I.e., T (%o0) => %o3. */ | |
3730 | fputs (reg_names[REGNO (x)+3], file); | |
3731 | return; | |
ab835497 RK |
3732 | case 'm': |
3733 | /* Print the operand's address only. */ | |
3734 | output_address (XEXP (x, 0)); | |
3735 | return; | |
3736 | case 'r': | |
3737 | /* In this case we need a register. Use %g0 if the | |
77a02b01 | 3738 | operand is const0_rtx. */ |
76052e74 RS |
3739 | if (x == const0_rtx |
3740 | || (GET_MODE (x) != VOIDmode && x == CONST0_RTX (GET_MODE (x)))) | |
ab835497 RK |
3741 | { |
3742 | fputs ("%g0", file); | |
3743 | return; | |
3744 | } | |
3745 | else | |
3746 | break; | |
3747 | ||
61a55e8b | 3748 | case 'A': |
ab835497 RK |
3749 | switch (GET_CODE (x)) |
3750 | { | |
3751 | case IOR: fputs ("or", file); break; | |
3752 | case AND: fputs ("and", file); break; | |
3753 | case XOR: fputs ("xor", file); break; | |
b3b1e8bd | 3754 | default: output_operand_lossage ("Invalid %%A operand"); |
ab835497 RK |
3755 | } |
3756 | return; | |
3757 | ||
3758 | case 'B': | |
3759 | switch (GET_CODE (x)) | |
3760 | { | |
3761 | case IOR: fputs ("orn", file); break; | |
3762 | case AND: fputs ("andn", file); break; | |
3763 | case XOR: fputs ("xnor", file); break; | |
b3b1e8bd | 3764 | default: output_operand_lossage ("Invalid %%B operand"); |
ab835497 RK |
3765 | } |
3766 | return; | |
3767 | ||
61a55e8b DE |
3768 | /* This is used by the conditional move instructions. */ |
3769 | case 'C': | |
3770 | switch (GET_CODE (x)) | |
3771 | { | |
3772 | case NE: fputs ("ne", file); break; | |
3773 | case EQ: fputs ("e", file); break; | |
3774 | case GE: fputs ("ge", file); break; | |
3775 | case GT: fputs ("g", file); break; | |
3776 | case LE: fputs ("le", file); break; | |
3777 | case LT: fputs ("l", file); break; | |
3778 | case GEU: fputs ("geu", file); break; | |
3779 | case GTU: fputs ("gu", file); break; | |
3780 | case LEU: fputs ("leu", file); break; | |
3781 | case LTU: fputs ("lu", file); break; | |
3782 | default: output_operand_lossage ("Invalid %%C operand"); | |
3783 | } | |
3784 | return; | |
3785 | ||
3786 | /* This is used by the movr instruction pattern. */ | |
3787 | case 'D': | |
3788 | switch (GET_CODE (x)) | |
3789 | { | |
3790 | case NE: fputs ("ne", file); break; | |
3791 | case EQ: fputs ("e", file); break; | |
3792 | case GE: fputs ("gez", file); break; | |
3793 | case LT: fputs ("lz", file); break; | |
3794 | case LE: fputs ("lez", file); break; | |
3795 | case GT: fputs ("gz", file); break; | |
3796 | default: output_operand_lossage ("Invalid %%D operand"); | |
3797 | } | |
3798 | return; | |
3799 | ||
ab835497 RK |
3800 | case 'b': |
3801 | { | |
3802 | /* Print a sign-extended character. */ | |
3803 | int i = INTVAL (x) & 0xff; | |
3804 | if (i & 0x80) | |
3805 | i |= 0xffffff00; | |
3806 | fprintf (file, "%d", i); | |
3807 | return; | |
3808 | } | |
3809 | ||
d2889939 RK |
3810 | case 'f': |
3811 | /* Operand must be a MEM; write its address. */ | |
3812 | if (GET_CODE (x) != MEM) | |
3813 | output_operand_lossage ("Invalid %%f operand"); | |
3814 | output_address (XEXP (x, 0)); | |
3815 | return; | |
3816 | ||
ab835497 RK |
3817 | case 0: |
3818 | /* Do nothing special. */ | |
3819 | break; | |
3820 | ||
3821 | default: | |
3822 | /* Undocumented flag. */ | |
415f583e | 3823 | output_operand_lossage ("invalid operand output code"); |
ab835497 RK |
3824 | } |
3825 | ||
3826 | if (GET_CODE (x) == REG) | |
3827 | fputs (reg_names[REGNO (x)], file); | |
3828 | else if (GET_CODE (x) == MEM) | |
3829 | { | |
3830 | fputc ('[', file); | |
3831 | if (CONSTANT_P (XEXP (x, 0))) | |
3832 | /* Poor Sun assembler doesn't understand absolute addressing. */ | |
3833 | fputs ("%g0+", file); | |
3834 | output_address (XEXP (x, 0)); | |
3835 | fputc (']', file); | |
3836 | } | |
3837 | else if (GET_CODE (x) == HIGH) | |
3838 | { | |
3839 | fputs ("%hi(", file); | |
3840 | output_addr_const (file, XEXP (x, 0)); | |
3841 | fputc (')', file); | |
3842 | } | |
3843 | else if (GET_CODE (x) == LO_SUM) | |
3844 | { | |
3845 | print_operand (file, XEXP (x, 0), 0); | |
3846 | fputs ("+%lo(", file); | |
3847 | output_addr_const (file, XEXP (x, 1)); | |
3848 | fputc (')', file); | |
3849 | } | |
e601abce JW |
3850 | else if (GET_CODE (x) == CONST_DOUBLE |
3851 | && (GET_MODE (x) == VOIDmode | |
3852 | || GET_MODE_CLASS (GET_MODE (x)) == MODE_INT)) | |
ab835497 RK |
3853 | { |
3854 | if (CONST_DOUBLE_HIGH (x) == 0) | |
3855 | fprintf (file, "%u", CONST_DOUBLE_LOW (x)); | |
3856 | else if (CONST_DOUBLE_HIGH (x) == -1 | |
3857 | && CONST_DOUBLE_LOW (x) < 0) | |
3858 | fprintf (file, "%d", CONST_DOUBLE_LOW (x)); | |
3859 | else | |
e601abce | 3860 | output_operand_lossage ("long long constant not a valid immediate operand"); |
ab835497 | 3861 | } |
e601abce JW |
3862 | else if (GET_CODE (x) == CONST_DOUBLE) |
3863 | output_operand_lossage ("floating point constant not a valid immediate operand"); | |
ab835497 RK |
3864 | else { output_addr_const (file, x); } |
3865 | } | |
3866 | \f | |
3867 | /* This function outputs assembler code for VALUE to FILE, where VALUE is | |
3868 | a 64 bit (DImode) value. */ | |
3869 | ||
3870 | /* ??? If there is a 64 bit counterpart to .word that the assembler | |
3871 | understands, then using that would simply this code greatly. */ | |
61a55e8b DE |
3872 | /* ??? We only output .xword's for symbols and only then in environments |
3873 | where the assembler can handle them. */ | |
ab835497 RK |
3874 | |
3875 | void | |
3876 | output_double_int (file, value) | |
3877 | FILE *file; | |
3878 | rtx value; | |
3879 | { | |
3880 | if (GET_CODE (value) == CONST_INT) | |
3881 | { | |
3882 | if (INTVAL (value) < 0) | |
3883 | ASM_OUTPUT_INT (file, constm1_rtx); | |
3884 | else | |
3885 | ASM_OUTPUT_INT (file, const0_rtx); | |
3886 | ASM_OUTPUT_INT (file, value); | |
3887 | } | |
3888 | else if (GET_CODE (value) == CONST_DOUBLE) | |
3889 | { | |
3890 | ASM_OUTPUT_INT (file, gen_rtx (CONST_INT, VOIDmode, | |
3891 | CONST_DOUBLE_HIGH (value))); | |
3892 | ASM_OUTPUT_INT (file, gen_rtx (CONST_INT, VOIDmode, | |
3893 | CONST_DOUBLE_LOW (value))); | |
3894 | } | |
3895 | else if (GET_CODE (value) == SYMBOL_REF | |
3896 | || GET_CODE (value) == CONST | |
61a55e8b DE |
3897 | || GET_CODE (value) == PLUS |
3898 | || (TARGET_V9 && | |
3899 | (GET_CODE (value) == LABEL_REF | |
3900 | || GET_CODE (value) == MINUS))) | |
ab835497 | 3901 | { |
61a55e8b DE |
3902 | if (!TARGET_V9 || TARGET_ENV32) |
3903 | { | |
3904 | ASM_OUTPUT_INT (file, const0_rtx); | |
3905 | ASM_OUTPUT_INT (file, value); | |
3906 | } | |
3907 | else | |
3908 | { | |
3909 | fprintf (file, "\t%s\t", ASM_LONGLONG); | |
3910 | output_addr_const (file, value); | |
3911 | fprintf (file, "\n"); | |
3912 | } | |
ab835497 RK |
3913 | } |
3914 | else | |
3915 | abort (); | |
3916 | } | |
210aa14a | 3917 | \f |
b0468b84 RK |
3918 | /* Return the value of a code used in the .proc pseudo-op that says |
3919 | what kind of result this function returns. For non-C types, we pick | |
3920 | the closest C type. */ | |
3921 | ||
77a02b01 JW |
3922 | #ifndef CHAR_TYPE_SIZE |
3923 | #define CHAR_TYPE_SIZE BITS_PER_UNIT | |
3924 | #endif | |
3925 | ||
3926 | #ifndef SHORT_TYPE_SIZE | |
3927 | #define SHORT_TYPE_SIZE (BITS_PER_UNIT * 2) | |
3928 | #endif | |
3929 | ||
3930 | #ifndef INT_TYPE_SIZE | |
3931 | #define INT_TYPE_SIZE BITS_PER_WORD | |
3932 | #endif | |
3933 | ||
3934 | #ifndef LONG_TYPE_SIZE | |
3935 | #define LONG_TYPE_SIZE BITS_PER_WORD | |
3936 | #endif | |
3937 | ||
3938 | #ifndef LONG_LONG_TYPE_SIZE | |
3939 | #define LONG_LONG_TYPE_SIZE (BITS_PER_WORD * 2) | |
3940 | #endif | |
3941 | ||
3942 | #ifndef FLOAT_TYPE_SIZE | |
3943 | #define FLOAT_TYPE_SIZE BITS_PER_WORD | |
3944 | #endif | |
3945 | ||
3946 | #ifndef DOUBLE_TYPE_SIZE | |
3947 | #define DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2) | |
3948 | #endif | |
3949 | ||
3950 | #ifndef LONG_DOUBLE_TYPE_SIZE | |
3951 | #define LONG_DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2) | |
3952 | #endif | |
210aa14a RS |
3953 | |
3954 | unsigned long | |
3955 | sparc_type_code (type) | |
3956 | register tree type; | |
3957 | { | |
3958 | register unsigned long qualifiers = 0; | |
3959 | register unsigned shift = 6; | |
3960 | ||
aee2c3c5 JW |
3961 | /* Only the first 30 bits of the qualifer are valid. We must refrain from |
3962 | setting more, since some assemblers will give an error for this. Also, | |
3963 | we must be careful to avoid shifts of 32 bits or more to avoid getting | |
3964 | unpredictable results. */ | |
3965 | ||
210aa14a RS |
3966 | for (;;) |
3967 | { | |
3968 | switch (TREE_CODE (type)) | |
3969 | { | |
3970 | case ERROR_MARK: | |
3971 | return qualifiers; | |
3972 | ||
3973 | case ARRAY_TYPE: | |
aee2c3c5 JW |
3974 | if (shift < 30) |
3975 | qualifiers |= (3 << shift); | |
210aa14a RS |
3976 | shift += 2; |
3977 | type = TREE_TYPE (type); | |
3978 | break; | |
3979 | ||
3980 | case FUNCTION_TYPE: | |
3981 | case METHOD_TYPE: | |
aee2c3c5 JW |
3982 | if (shift < 30) |
3983 | qualifiers |= (2 << shift); | |
210aa14a RS |
3984 | shift += 2; |
3985 | type = TREE_TYPE (type); | |
3986 | break; | |
3987 | ||
3988 | case POINTER_TYPE: | |
3989 | case REFERENCE_TYPE: | |
3990 | case OFFSET_TYPE: | |
aee2c3c5 JW |
3991 | if (shift < 30) |
3992 | qualifiers |= (1 << shift); | |
210aa14a RS |
3993 | shift += 2; |
3994 | type = TREE_TYPE (type); | |
3995 | break; | |
ab835497 | 3996 | |
210aa14a RS |
3997 | case RECORD_TYPE: |
3998 | return (qualifiers | 8); | |
3999 | ||
4000 | case UNION_TYPE: | |
b0468b84 | 4001 | case QUAL_UNION_TYPE: |
210aa14a RS |
4002 | return (qualifiers | 9); |
4003 | ||
4004 | case ENUMERAL_TYPE: | |
4005 | return (qualifiers | 10); | |
4006 | ||
4007 | case VOID_TYPE: | |
4008 | return (qualifiers | 16); | |
4009 | ||
4010 | case INTEGER_TYPE: | |
654209e6 JW |
4011 | /* If this is a range type, consider it to be the underlying |
4012 | type. */ | |
4013 | if (TREE_TYPE (type) != 0) | |
4014 | { | |
4015 | type = TREE_TYPE (type); | |
4016 | break; | |
4017 | } | |
4018 | ||
77a02b01 | 4019 | /* Carefully distinguish all the standard types of C, |
b0468b84 RK |
4020 | without messing up if the language is not C. We do this by |
4021 | testing TYPE_PRECISION and TREE_UNSIGNED. The old code used to | |
4022 | look at both the names and the above fields, but that's redundant. | |
4023 | Any type whose size is between two C types will be considered | |
4024 | to be the wider of the two types. Also, we do not have a | |
4025 | special code to use for "long long", so anything wider than | |
4026 | long is treated the same. Note that we can't distinguish | |
4027 | between "int" and "long" in this code if they are the same | |
4028 | size, but that's fine, since neither can the assembler. */ | |
4029 | ||
4030 | if (TYPE_PRECISION (type) <= CHAR_TYPE_SIZE) | |
4031 | return (qualifiers | (TREE_UNSIGNED (type) ? 12 : 2)); | |
77a02b01 | 4032 | |
b0468b84 RK |
4033 | else if (TYPE_PRECISION (type) <= SHORT_TYPE_SIZE) |
4034 | return (qualifiers | (TREE_UNSIGNED (type) ? 13 : 3)); | |
77a02b01 | 4035 | |
b0468b84 | 4036 | else if (TYPE_PRECISION (type) <= INT_TYPE_SIZE) |
77a02b01 JW |
4037 | return (qualifiers | (TREE_UNSIGNED (type) ? 14 : 4)); |
4038 | ||
b0468b84 | 4039 | else |
77a02b01 JW |
4040 | return (qualifiers | (TREE_UNSIGNED (type) ? 15 : 5)); |
4041 | ||
210aa14a | 4042 | case REAL_TYPE: |
77a02b01 JW |
4043 | /* Carefully distinguish all the standard types of C, |
4044 | without messing up if the language is not C. */ | |
b0468b84 | 4045 | |
77a02b01 | 4046 | if (TYPE_PRECISION (type) == FLOAT_TYPE_SIZE) |
210aa14a | 4047 | return (qualifiers | 6); |
b0468b84 RK |
4048 | |
4049 | else | |
4050 | return (qualifiers | 7); | |
210aa14a RS |
4051 | |
4052 | case COMPLEX_TYPE: /* GNU Fortran COMPLEX type. */ | |
13d39dbc | 4053 | /* ??? We need to distinguish between double and float complex types, |
c82aa69a JW |
4054 | but I don't know how yet because I can't reach this code from |
4055 | existing front-ends. */ | |
4056 | return (qualifiers | 7); /* Who knows? */ | |
4057 | ||
210aa14a RS |
4058 | case CHAR_TYPE: /* GNU Pascal CHAR type. Not used in C. */ |
4059 | case BOOLEAN_TYPE: /* GNU Fortran BOOLEAN type. */ | |
4060 | case FILE_TYPE: /* GNU Pascal FILE type. */ | |
26902ae0 | 4061 | case SET_TYPE: /* GNU Pascal SET type. */ |
210aa14a | 4062 | case LANG_TYPE: /* ? */ |
26902ae0 | 4063 | return qualifiers; |
210aa14a RS |
4064 | |
4065 | default: | |
4066 | abort (); /* Not a type! */ | |
4067 | } | |
4068 | } | |
4069 | } | |
ead69aea | 4070 | \f |
61a55e8b DE |
4071 | /* Nested function support. */ |
4072 | ||
4073 | /* Emit RTL insns to initialize the variable parts of a trampoline. | |
4074 | FNADDR is an RTX for the address of the function's pure code. | |
4075 | CXT is an RTX for the static chain value for the function. | |
4076 | ||
4077 | This takes 16 insns: 2 shifts & 2 ands (to split up addresses), 4 sethi | |
4078 | (to load in opcodes), 4 iors (to merge address and opcodes), and 4 writes | |
4079 | (to store insns). This is a bit excessive. Perhaps a different | |
4080 | mechanism would be better here. | |
4081 | ||
ddd5a7c1 | 4082 | Emit 3 FLUSH instructions to synchronize the data and instruction caches. |
61a55e8b DE |
4083 | |
4084 | ??? v9: We assume the top 32 bits of function addresses are 0. */ | |
4085 | ||
4086 | void | |
4087 | sparc_initialize_trampoline (tramp, fnaddr, cxt) | |
4088 | rtx tramp, fnaddr, cxt; | |
4089 | { | |
4090 | rtx high_cxt = expand_shift (RSHIFT_EXPR, SImode, cxt, | |
4091 | size_int (10), 0, 1); | |
4092 | rtx high_fn = expand_shift (RSHIFT_EXPR, SImode, fnaddr, | |
4093 | size_int (10), 0, 1); | |
4094 | rtx low_cxt = expand_and (cxt, gen_rtx (CONST_INT, VOIDmode, 0x3ff), 0); | |
4095 | rtx low_fn = expand_and (fnaddr, gen_rtx (CONST_INT, VOIDmode, 0x3ff), 0); | |
4096 | rtx g1_sethi = gen_rtx (HIGH, SImode, | |
4097 | gen_rtx (CONST_INT, VOIDmode, 0x03000000)); | |
4098 | rtx g2_sethi = gen_rtx (HIGH, SImode, | |
4099 | gen_rtx (CONST_INT, VOIDmode, 0x05000000)); | |
4100 | rtx g1_ori = gen_rtx (HIGH, SImode, | |
4101 | gen_rtx (CONST_INT, VOIDmode, 0x82106000)); | |
4102 | rtx g2_ori = gen_rtx (HIGH, SImode, | |
4103 | gen_rtx (CONST_INT, VOIDmode, 0x8410A000)); | |
4104 | rtx tem = gen_reg_rtx (SImode); | |
4105 | emit_move_insn (tem, g1_sethi); | |
4106 | emit_insn (gen_iorsi3 (high_fn, high_fn, tem)); | |
4107 | emit_move_insn (gen_rtx (MEM, SImode, plus_constant (tramp, 0)), high_fn); | |
4108 | emit_move_insn (tem, g1_ori); | |
4109 | emit_insn (gen_iorsi3 (low_fn, low_fn, tem)); | |
4110 | emit_move_insn (gen_rtx (MEM, SImode, plus_constant (tramp, 4)), low_fn); | |
4111 | emit_move_insn (tem, g2_sethi); | |
4112 | emit_insn (gen_iorsi3 (high_cxt, high_cxt, tem)); | |
4113 | emit_move_insn (gen_rtx (MEM, SImode, plus_constant (tramp, 8)), high_cxt); | |
4114 | emit_move_insn (tem, g2_ori); | |
4115 | emit_insn (gen_iorsi3 (low_cxt, low_cxt, tem)); | |
4116 | emit_move_insn (gen_rtx (MEM, SImode, plus_constant (tramp, 16)), low_cxt); | |
d2889939 RK |
4117 | emit_insn (gen_flush (validize_mem (gen_rtx (MEM, SImode, tramp)))); |
4118 | emit_insn (gen_flush (validize_mem (gen_rtx (MEM, SImode, | |
4119 | plus_constant (tramp, 8))))); | |
4120 | emit_insn (gen_flush (validize_mem (gen_rtx (MEM, SImode, | |
4121 | plus_constant (tramp, 16))))); | |
61a55e8b DE |
4122 | } |
4123 | ||
4124 | void | |
4125 | sparc64_initialize_trampoline (tramp, fnaddr, cxt) | |
4126 | rtx tramp, fnaddr, cxt; | |
4127 | { | |
4128 | rtx fnaddrdi = gen_reg_rtx (Pmode); | |
4129 | rtx fnaddrsi = (emit_move_insn (fnaddrdi, fnaddr), | |
4130 | gen_rtx (SUBREG, SImode, fnaddrdi, 0)); | |
4131 | rtx cxtdi = gen_reg_rtx (Pmode); | |
4132 | rtx cxtsi = (emit_move_insn (cxtdi, cxt), | |
4133 | gen_rtx (SUBREG, SImode, cxtdi, 0)); | |
4134 | rtx high_cxt = expand_shift (RSHIFT_EXPR, SImode, cxtsi, | |
4135 | size_int (10), 0, 1); | |
4136 | rtx high_fn = expand_shift (RSHIFT_EXPR, SImode, fnaddrsi, | |
4137 | size_int (10), 0, 1); | |
4138 | rtx low_cxt = expand_and (cxtsi, gen_rtx (CONST_INT, VOIDmode, 0x3ff), 0); | |
4139 | rtx low_fn = expand_and (fnaddrsi, gen_rtx (CONST_INT, VOIDmode, 0x3ff), 0); | |
4140 | rtx g1_sethi = gen_rtx (HIGH, SImode, | |
4141 | gen_rtx (CONST_INT, VOIDmode, 0x03000000)); | |
4142 | rtx g2_sethi = gen_rtx (HIGH, SImode, | |
4143 | gen_rtx (CONST_INT, VOIDmode, 0x05000000)); | |
4144 | rtx g1_ori = gen_rtx (HIGH, SImode, | |
4145 | gen_rtx (CONST_INT, VOIDmode, 0x82106000)); | |
4146 | rtx g2_ori = gen_rtx (HIGH, SImode, | |
4147 | gen_rtx (CONST_INT, VOIDmode, 0x8410A000)); | |
4148 | rtx tem = gen_reg_rtx (SImode); | |
4149 | emit_move_insn (tem, g2_sethi); | |
4150 | emit_insn (gen_iorsi3 (high_fn, high_fn, tem)); | |
4151 | emit_move_insn (gen_rtx (MEM, SImode, plus_constant (tramp, 0)), high_fn); | |
4152 | emit_move_insn (tem, g2_ori); | |
4153 | emit_insn (gen_iorsi3 (low_fn, low_fn, tem)); | |
4154 | emit_move_insn (gen_rtx (MEM, SImode, plus_constant (tramp, 4)), low_fn); | |
4155 | emit_move_insn (tem, g1_sethi); | |
4156 | emit_insn (gen_iorsi3 (high_cxt, high_cxt, tem)); | |
4157 | emit_move_insn (gen_rtx (MEM, SImode, plus_constant (tramp, 8)), high_cxt); | |
4158 | emit_move_insn (tem, g1_ori); | |
4159 | emit_insn (gen_iorsi3 (low_cxt, low_cxt, tem)); | |
4160 | emit_move_insn (gen_rtx (MEM, SImode, plus_constant (tramp, 16)), low_cxt); | |
38489316 DE |
4161 | emit_insn (gen_flush (validize_mem (gen_rtx (MEM, DImode, tramp)))); |
4162 | emit_insn (gen_flush (validize_mem (gen_rtx (MEM, DImode, | |
4163 | plus_constant (tramp, 8))))); | |
4164 | emit_insn (gen_flush (validize_mem (gen_rtx (MEM, DImode, | |
4165 | plus_constant (tramp, 16))))); | |
61a55e8b DE |
4166 | } |
4167 | \f | |
c819be5b JW |
4168 | /* Subroutines to support a flat (single) register window calling |
4169 | convention. */ | |
4170 | ||
4171 | /* Single-register window sparc stack frames look like: | |
4172 | ||
4173 | Before call After call | |
4174 | +-----------------------+ +-----------------------+ | |
86735b02 DE |
4175 | high | | | | |
4176 | mem | caller's temps. | | caller's temps. | | |
c819be5b JW |
4177 | | | | | |
4178 | +-----------------------+ +-----------------------+ | |
4179 | | | | | | |
4180 | | arguments on stack. | | arguments on stack. | | |
86735b02 DE |
4181 | | | | | |
4182 | +-----------------------+FP+92->+-----------------------+ | |
c819be5b JW |
4183 | | 6 words to save | | 6 words to save | |
4184 | | arguments passed | | arguments passed | | |
4185 | | in registers, even | | in registers, even | | |
86735b02 DE |
4186 | | if not passed. | | if not passed. | |
4187 | SP+68->+-----------------------+FP+68->+-----------------------+ | |
4188 | | 1 word struct addr | | 1 word struct addr | | |
4189 | +-----------------------+FP+64->+-----------------------+ | |
4190 | | | | | | |
4191 | | 16 word reg save area | | 16 word reg save area | | |
4192 | | | | | | |
4193 | SP->+-----------------------+ FP->+-----------------------+ | |
4194 | | 4 word area for | | |
4195 | | fp/alu reg moves | | |
4196 | FP-16->+-----------------------+ | |
4197 | | | | |
4198 | | local variables | | |
4199 | | | | |
4200 | +-----------------------+ | |
4201 | | | | |
c819be5b | 4202 | | fp register save | |
86735b02 DE |
4203 | | | |
4204 | +-----------------------+ | |
4205 | | | | |
c819be5b JW |
4206 | | gp register save | |
4207 | | | | |
86735b02 DE |
4208 | +-----------------------+ |
4209 | | | | |
c819be5b | 4210 | | alloca allocations | |
86735b02 DE |
4211 | | | |
4212 | +-----------------------+ | |
4213 | | | | |
c819be5b | 4214 | | arguments on stack | |
86735b02 DE |
4215 | | | |
4216 | SP+92->+-----------------------+ | |
c819be5b | 4217 | | 6 words to save | |
86735b02 | 4218 | | arguments passed | |
c819be5b | 4219 | | in registers, even | |
86735b02 DE |
4220 | low | if not passed. | |
4221 | memory SP+68->+-----------------------+ | |
4222 | | 1 word struct addr | | |
4223 | SP+64->+-----------------------+ | |
4224 | | | | |
4225 | I 16 word reg save area | | |
4226 | | | | |
4227 | SP->+-----------------------+ */ | |
c819be5b | 4228 | |
c6aa9ce1 | 4229 | /* Structure to be filled in by sparc_flat_compute_frame_size with register |
c819be5b JW |
4230 | save masks, and offsets for the current function. */ |
4231 | ||
4232 | struct sparc_frame_info | |
4233 | { | |
4234 | unsigned long total_size; /* # bytes that the entire frame takes up. */ | |
4235 | unsigned long var_size; /* # bytes that variables take up. */ | |
4236 | unsigned long args_size; /* # bytes that outgoing arguments take up. */ | |
4237 | unsigned long extra_size; /* # bytes of extra gunk. */ | |
4238 | unsigned int gp_reg_size; /* # bytes needed to store gp regs. */ | |
4239 | unsigned int fp_reg_size; /* # bytes needed to store fp regs. */ | |
86735b02 | 4240 | unsigned long gmask; /* Mask of saved gp registers. */ |
c819be5b | 4241 | unsigned long fmask; /* Mask of saved fp registers. */ |
86735b02 | 4242 | unsigned long reg_offset; /* Offset from new sp to store regs. */ |
c819be5b JW |
4243 | int initialized; /* Nonzero if frame size already calculated. */ |
4244 | }; | |
4245 | ||
c6aa9ce1 | 4246 | /* Current frame information calculated by sparc_flat_compute_frame_size. */ |
c819be5b JW |
4247 | struct sparc_frame_info current_frame_info; |
4248 | ||
4249 | /* Zero structure to initialize current_frame_info. */ | |
4250 | struct sparc_frame_info zero_frame_info; | |
4251 | ||
4252 | /* Tell prologue and epilogue if register REGNO should be saved / restored. */ | |
4253 | ||
86735b02 DE |
4254 | #define RETURN_ADDR_REGNUM 15 |
4255 | #define FRAME_POINTER_MASK (1 << (FRAME_POINTER_REGNUM)) | |
4256 | #define RETURN_ADDR_MASK (1 << (RETURN_ADDR_REGNUM)) | |
4257 | ||
c819be5b JW |
4258 | #define MUST_SAVE_REGISTER(regno) \ |
4259 | ((regs_ever_live[regno] && !call_used_regs[regno]) \ | |
4260 | || (regno == FRAME_POINTER_REGNUM && frame_pointer_needed) \ | |
86735b02 | 4261 | || (regno == RETURN_ADDR_REGNUM && regs_ever_live[RETURN_ADDR_REGNUM])) |
c819be5b JW |
4262 | |
4263 | /* Return the bytes needed to compute the frame pointer from the current | |
4264 | stack pointer. */ | |
4265 | ||
4266 | unsigned long | |
c6aa9ce1 | 4267 | sparc_flat_compute_frame_size (size) |
c819be5b JW |
4268 | int size; /* # of var. bytes allocated. */ |
4269 | { | |
4270 | int regno; | |
4271 | unsigned long total_size; /* # bytes that the entire frame takes up. */ | |
4272 | unsigned long var_size; /* # bytes that variables take up. */ | |
4273 | unsigned long args_size; /* # bytes that outgoing arguments take up. */ | |
4274 | unsigned long extra_size; /* # extra bytes. */ | |
4275 | unsigned int gp_reg_size; /* # bytes needed to store gp regs. */ | |
4276 | unsigned int fp_reg_size; /* # bytes needed to store fp regs. */ | |
86735b02 | 4277 | unsigned long gmask; /* Mask of saved gp registers. */ |
c819be5b | 4278 | unsigned long fmask; /* Mask of saved fp registers. */ |
86735b02 DE |
4279 | unsigned long reg_offset; /* Offset to register save area. */ |
4280 | int need_aligned_p; /* 1 if need the save area 8 byte aligned. */ | |
c819be5b JW |
4281 | |
4282 | /* This is the size of the 16 word reg save area, 1 word struct addr | |
4283 | area, and 4 word fp/alu register copy area. */ | |
4284 | extra_size = -STARTING_FRAME_OFFSET + FIRST_PARM_OFFSET(0); | |
4285 | var_size = size; | |
4286 | /* Also include the size needed for the 6 parameter registers. */ | |
4287 | args_size = current_function_outgoing_args_size + 24; | |
4288 | total_size = var_size + args_size + extra_size; | |
4289 | gp_reg_size = 0; | |
4290 | fp_reg_size = 0; | |
86735b02 | 4291 | gmask = 0; |
c819be5b | 4292 | fmask = 0; |
86735b02 DE |
4293 | reg_offset = 0; |
4294 | need_aligned_p = 0; | |
c819be5b JW |
4295 | |
4296 | /* Calculate space needed for gp registers. */ | |
4297 | for (regno = 1; regno <= 31; regno++) | |
4298 | { | |
4299 | if (MUST_SAVE_REGISTER (regno)) | |
4300 | { | |
86735b02 DE |
4301 | /* If we need to save two regs in a row, ensure there's room to bump |
4302 | up the address to align it to a doubleword boundary. */ | |
c819be5b JW |
4303 | if ((regno & 0x1) == 0 && MUST_SAVE_REGISTER (regno+1)) |
4304 | { | |
4305 | if (gp_reg_size % 8 != 0) | |
86735b02 | 4306 | gp_reg_size += 4; |
c819be5b | 4307 | gp_reg_size += 2 * UNITS_PER_WORD; |
86735b02 | 4308 | gmask |= 3 << regno; |
c819be5b | 4309 | regno++; |
86735b02 | 4310 | need_aligned_p = 1; |
c819be5b JW |
4311 | } |
4312 | else | |
4313 | { | |
4314 | gp_reg_size += UNITS_PER_WORD; | |
86735b02 | 4315 | gmask |= 1 << regno; |
c819be5b JW |
4316 | } |
4317 | } | |
4318 | } | |
c819be5b JW |
4319 | |
4320 | /* Calculate space needed for fp registers. */ | |
4321 | for (regno = 32; regno <= 63; regno++) | |
4322 | { | |
4323 | if (regs_ever_live[regno] && !call_used_regs[regno]) | |
4324 | { | |
4325 | fp_reg_size += UNITS_PER_WORD; | |
4326 | fmask |= 1 << (regno - 32); | |
4327 | } | |
4328 | } | |
4329 | ||
86735b02 DE |
4330 | if (gmask || fmask) |
4331 | { | |
4332 | int n; | |
4333 | reg_offset = FIRST_PARM_OFFSET(0) + args_size; | |
4334 | /* Ensure save area is 8 byte aligned if we need it. */ | |
4335 | n = reg_offset % 8; | |
4336 | if (need_aligned_p && n != 0) | |
4337 | { | |
4338 | total_size += 8 - n; | |
4339 | reg_offset += 8 - n; | |
4340 | } | |
4341 | total_size += gp_reg_size + fp_reg_size; | |
4342 | } | |
c819be5b | 4343 | |
86735b02 | 4344 | /* ??? This looks a little suspicious. Clarify. */ |
c819be5b JW |
4345 | if (total_size == extra_size) |
4346 | total_size = extra_size = 0; | |
4347 | ||
4348 | total_size = SPARC_STACK_ALIGN (total_size); | |
4349 | ||
4350 | /* Save other computed information. */ | |
4351 | current_frame_info.total_size = total_size; | |
4352 | current_frame_info.var_size = var_size; | |
4353 | current_frame_info.args_size = args_size; | |
4354 | current_frame_info.extra_size = extra_size; | |
4355 | current_frame_info.gp_reg_size = gp_reg_size; | |
4356 | current_frame_info.fp_reg_size = fp_reg_size; | |
86735b02 | 4357 | current_frame_info.gmask = gmask; |
c819be5b | 4358 | current_frame_info.fmask = fmask; |
86735b02 | 4359 | current_frame_info.reg_offset = reg_offset; |
c819be5b JW |
4360 | current_frame_info.initialized = reload_completed; |
4361 | ||
c819be5b JW |
4362 | /* Ok, we're done. */ |
4363 | return total_size; | |
4364 | } | |
4365 | \f | |
86735b02 DE |
4366 | /* Save/restore registers in GMASK and FMASK at register BASE_REG plus offset |
4367 | OFFSET. | |
4368 | ||
4369 | BASE_REG must be 8 byte aligned. This allows us to test OFFSET for | |
4370 | appropriate alignment and use DOUBLEWORD_OP when we can. We assume | |
4371 | [BASE_REG+OFFSET] will always be a valid address. | |
4372 | ||
4373 | WORD_OP is either "st" for save, "ld" for restore. | |
4374 | DOUBLEWORD_OP is either "std" for save, "ldd" for restore. */ | |
c819be5b JW |
4375 | |
4376 | void | |
86735b02 DE |
4377 | sparc_flat_save_restore (file, base_reg, offset, gmask, fmask, word_op, doubleword_op) |
4378 | FILE *file; | |
4379 | char *base_reg; | |
4380 | unsigned int offset; | |
4381 | unsigned long gmask; | |
4382 | unsigned long fmask; | |
4383 | char *word_op; | |
4384 | char *doubleword_op; | |
c819be5b JW |
4385 | { |
4386 | int regno; | |
c819be5b | 4387 | |
86735b02 DE |
4388 | if (gmask == 0 && fmask == 0) |
4389 | return; | |
c819be5b | 4390 | |
86735b02 DE |
4391 | /* Save registers starting from high to low. We've already saved the |
4392 | previous frame pointer and previous return address for the debugger's | |
4393 | sake. The debugger allows us to not need a nop in the epilog if at least | |
4394 | one register is reloaded in addition to return address. */ | |
c819be5b | 4395 | |
86735b02 | 4396 | if (gmask) |
c819be5b JW |
4397 | { |
4398 | for (regno = 1; regno <= 31; regno++) | |
4399 | { | |
86735b02 | 4400 | if ((gmask & (1L << regno)) != 0) |
c819be5b | 4401 | { |
86735b02 | 4402 | if ((regno & 0x1) == 0 && ((gmask & (1L << (regno+1))) != 0)) |
c819be5b | 4403 | { |
86735b02 DE |
4404 | /* We can save two registers in a row. If we're not at a |
4405 | double word boundary, move to one. | |
4406 | sparc_flat_compute_frame_size ensures there's room to do | |
4407 | this. */ | |
4408 | if (offset % 8 != 0) | |
4409 | offset += UNITS_PER_WORD; | |
4410 | ||
c819be5b JW |
4411 | if (word_op[0] == 's') |
4412 | fprintf (file, "\t%s %s,[%s+%d]\n", | |
4413 | doubleword_op, reg_names[regno], | |
86735b02 | 4414 | base_reg, offset); |
c819be5b JW |
4415 | else |
4416 | fprintf (file, "\t%s [%s+%d],%s\n", | |
86735b02 | 4417 | doubleword_op, base_reg, offset, |
c819be5b JW |
4418 | reg_names[regno]); |
4419 | ||
86735b02 | 4420 | offset += 2 * UNITS_PER_WORD; |
c819be5b JW |
4421 | regno++; |
4422 | } | |
4423 | else | |
4424 | { | |
4425 | if (word_op[0] == 's') | |
4426 | fprintf (file, "\t%s %s,[%s+%d]\n", | |
4427 | word_op, reg_names[regno], | |
86735b02 | 4428 | base_reg, offset); |
c819be5b JW |
4429 | else |
4430 | fprintf (file, "\t%s [%s+%d],%s\n", | |
86735b02 | 4431 | word_op, base_reg, offset, reg_names[regno]); |
c819be5b | 4432 | |
86735b02 | 4433 | offset += UNITS_PER_WORD; |
c819be5b JW |
4434 | } |
4435 | } | |
4436 | } | |
4437 | } | |
4438 | ||
4439 | if (fmask) | |
4440 | { | |
4441 | for (regno = 32; regno <= 63; regno++) | |
4442 | { | |
4443 | if ((fmask & (1L << (regno - 32))) != 0) | |
4444 | { | |
4445 | if (word_op[0] == 's') | |
4446 | fprintf (file, "\t%s %s,[%s+%d]\n", | |
4447 | word_op, reg_names[regno], | |
86735b02 | 4448 | base_reg, offset); |
c819be5b JW |
4449 | else |
4450 | fprintf (file, "\t%s [%s+%d],%s\n", | |
86735b02 | 4451 | word_op, base_reg, offset, reg_names[regno]); |
c819be5b | 4452 | |
86735b02 | 4453 | offset += UNITS_PER_WORD; |
c819be5b JW |
4454 | } |
4455 | } | |
4456 | } | |
4457 | } | |
4458 | \f | |
4459 | /* Set up the stack and frame (if desired) for the function. */ | |
4460 | ||
4461 | void | |
c6aa9ce1 | 4462 | sparc_flat_output_function_prologue (file, size) |
c819be5b JW |
4463 | FILE *file; |
4464 | int size; | |
4465 | { | |
c819be5b | 4466 | char *sp_str = reg_names[STACK_POINTER_REGNUM]; |
86735b02 | 4467 | unsigned long gmask = current_frame_info.gmask; |
a07c1915 | 4468 | |
c6aa9ce1 | 4469 | /* This is only for the human reader. */ |
c819be5b | 4470 | fprintf (file, "\t!#PROLOGUE# 0\n"); |
86735b02 DE |
4471 | fprintf (file, "\t!# vars= %d, regs= %d/%d, args= %d, extra= %d\n", |
4472 | current_frame_info.var_size, | |
4473 | current_frame_info.gp_reg_size / 4, | |
9f8b85b8 | 4474 | current_frame_info.fp_reg_size / 4, |
86735b02 DE |
4475 | current_function_outgoing_args_size, |
4476 | current_frame_info.extra_size); | |
c819be5b JW |
4477 | |
4478 | size = SPARC_STACK_ALIGN (size); | |
86735b02 DE |
4479 | size = (! current_frame_info.initialized |
4480 | ? sparc_flat_compute_frame_size (size) | |
4481 | : current_frame_info.total_size); | |
c819be5b | 4482 | |
86735b02 DE |
4483 | /* These cases shouldn't happen. Catch them now. */ |
4484 | if (size == 0 && (gmask || current_frame_info.fmask)) | |
4485 | abort (); | |
c819be5b | 4486 | |
86735b02 DE |
4487 | /* Allocate our stack frame by decrementing %sp. |
4488 | At present, the only algorithm gdb can use to determine if this is a | |
4489 | flat frame is if we always set %i7 if we set %sp. This can be optimized | |
4490 | in the future by putting in some sort of debugging information that says | |
4491 | this is a `flat' function. However, there is still the case of debugging | |
4492 | code without such debugging information (including cases where most fns | |
4493 | have such info, but there is one that doesn't). So, always do this now | |
4494 | so we don't get a lot of code out there that gdb can't handle. | |
4495 | If the frame pointer isn't needn't then that's ok - gdb won't be able to | |
4496 | distinguish us from a non-flat function but there won't (and shouldn't) | |
4497 | be any differences anyway. The return pc is saved (if necessary) right | |
4498 | after %i7 so gdb won't have to look too far to find it. */ | |
4499 | if (size > 0) | |
c819be5b | 4500 | { |
86735b02 | 4501 | unsigned int reg_offset = current_frame_info.reg_offset; |
c6aa9ce1 | 4502 | char *fp_str = reg_names[FRAME_POINTER_REGNUM]; |
86735b02 DE |
4503 | char *t1_str = "%g1"; |
4504 | ||
4505 | /* Things get a little tricky if local variables take up more than ~4096 | |
4506 | bytes and outgoing arguments take up more than ~4096 bytes. When that | |
4507 | happens, the register save area can't be accessed from either end of | |
4508 | the frame. Handle this by decrementing %sp to the start of the gp | |
4509 | register save area, save the regs, update %i7, and then set %sp to its | |
4510 | final value. Given that we only have one scratch register to play | |
4511 | with it is the cheapest solution, and it helps gdb out as it won't | |
4512 | slow down recognition of flat functions. | |
4513 | Don't change the order of insns emitted here without checking with | |
4514 | the gdb folk first. */ | |
4515 | ||
ddd5a7c1 | 4516 | /* Is the entire register save area offsettable from %sp? */ |
86735b02 DE |
4517 | if (reg_offset < 4096 - 64 * UNITS_PER_WORD) |
4518 | { | |
4519 | if (size <= 4096) | |
4520 | { | |
4521 | fprintf (file, "\tadd %s,%d,%s\n", | |
4522 | sp_str, -size, sp_str); | |
4523 | if (gmask & FRAME_POINTER_MASK) | |
4524 | { | |
4525 | fprintf (file, "\tst %s,[%s+%d]\n", | |
4526 | fp_str, sp_str, reg_offset); | |
4527 | fprintf (file, "\tsub %s,%d,%s\t!# set up frame pointer\n", | |
4528 | sp_str, -size, fp_str); | |
4529 | reg_offset += 4; | |
4530 | } | |
4531 | } | |
4532 | else | |
4533 | { | |
4534 | fprintf (file, "\tset %d,%s\n\tsub %s,%s,%s\n", | |
4535 | size, t1_str, sp_str, t1_str, sp_str); | |
4536 | if (gmask & FRAME_POINTER_MASK) | |
4537 | { | |
4538 | fprintf (file, "\tst %s,[%s+%d]\n", | |
4539 | fp_str, sp_str, reg_offset); | |
4540 | fprintf (file, "\tadd %s,%s,%s\t!# set up frame pointer\n", | |
4541 | sp_str, t1_str, fp_str); | |
4542 | reg_offset += 4; | |
4543 | } | |
4544 | } | |
4545 | if (gmask & RETURN_ADDR_MASK) | |
4546 | { | |
4547 | fprintf (file, "\tst %s,[%s+%d]\n", | |
4548 | reg_names[RETURN_ADDR_REGNUM], sp_str, reg_offset); | |
4549 | reg_offset += 4; | |
4550 | } | |
4551 | sparc_flat_save_restore (file, sp_str, reg_offset, | |
4552 | gmask & ~(FRAME_POINTER_MASK | RETURN_ADDR_MASK), | |
4553 | current_frame_info.fmask, | |
4554 | "st", "std"); | |
4555 | } | |
c819be5b | 4556 | else |
86735b02 DE |
4557 | { |
4558 | /* Subtract %sp in two steps, but make sure there is always a | |
4559 | 64 byte register save area, and %sp is properly aligned. */ | |
4560 | /* Amount to decrement %sp by, the first time. */ | |
4561 | unsigned int size1 = ((size - reg_offset + 64) + 15) & -16; | |
4562 | /* Offset to register save area from %sp. */ | |
4563 | unsigned int offset = size1 - (size - reg_offset); | |
4564 | ||
4565 | if (size1 <= 4096) | |
4566 | { | |
4567 | fprintf (file, "\tadd %s,%d,%s\n", | |
4568 | sp_str, -size1, sp_str); | |
4569 | if (gmask & FRAME_POINTER_MASK) | |
4570 | { | |
4571 | fprintf (file, "\tst %s,[%s+%d]\n\tsub %s,%d,%s\t!# set up frame pointer\n", | |
4572 | fp_str, sp_str, offset, sp_str, -size1, fp_str); | |
4573 | offset += 4; | |
4574 | } | |
4575 | } | |
4576 | else | |
4577 | { | |
4578 | fprintf (file, "\tset %d,%s\n\tsub %s,%s,%s\n", | |
4579 | size1, t1_str, sp_str, t1_str, sp_str); | |
4580 | if (gmask & FRAME_POINTER_MASK) | |
4581 | { | |
4582 | fprintf (file, "\tst %s,[%s+%d]\n\tadd %s,%s,%s\t!# set up frame pointer\n", | |
4583 | fp_str, sp_str, offset, sp_str, t1_str, fp_str); | |
4584 | offset += 4; | |
4585 | } | |
4586 | } | |
4587 | if (gmask & RETURN_ADDR_MASK) | |
4588 | { | |
4589 | fprintf (file, "\tst %s,[%s+%d]\n", | |
4590 | reg_names[RETURN_ADDR_REGNUM], sp_str, offset); | |
4591 | offset += 4; | |
4592 | } | |
4593 | sparc_flat_save_restore (file, sp_str, offset, | |
4594 | gmask & ~(FRAME_POINTER_MASK | RETURN_ADDR_MASK), | |
4595 | current_frame_info.fmask, | |
4596 | "st", "std"); | |
4597 | fprintf (file, "\tset %d,%s\n\tsub %s,%s,%s\n", | |
4598 | size - size1, t1_str, sp_str, t1_str, sp_str); | |
4599 | } | |
c819be5b | 4600 | } |
c6aa9ce1 DE |
4601 | |
4602 | fprintf (file, "\t!#PROLOGUE# 1\n"); | |
c819be5b JW |
4603 | } |
4604 | \f | |
4605 | /* Do any necessary cleanup after a function to restore stack, frame, | |
4606 | and regs. */ | |
4607 | ||
4608 | void | |
c6aa9ce1 | 4609 | sparc_flat_output_function_epilogue (file, size) |
c819be5b JW |
4610 | FILE *file; |
4611 | int size; | |
4612 | { | |
c819be5b JW |
4613 | rtx epilogue_delay = current_function_epilogue_delay_list; |
4614 | int noepilogue = FALSE; | |
c819be5b | 4615 | |
c6aa9ce1 DE |
4616 | /* This is only for the human reader. */ |
4617 | fprintf (file, "\t!#EPILOGUE#\n"); | |
4618 | ||
c819be5b JW |
4619 | /* The epilogue does not depend on any registers, but the stack |
4620 | registers, so we assume that if we have 1 pending nop, it can be | |
4621 | ignored, and 2 it must be filled (2 nops occur for integer | |
4622 | multiply and divide). */ | |
4623 | ||
4624 | size = SPARC_STACK_ALIGN (size); | |
86735b02 | 4625 | size = (!current_frame_info.initialized |
c6aa9ce1 | 4626 | ? sparc_flat_compute_frame_size (size) |
c819be5b JW |
4627 | : current_frame_info.total_size); |
4628 | ||
86735b02 | 4629 | if (size == 0 && epilogue_delay == 0) |
c819be5b JW |
4630 | { |
4631 | rtx insn = get_last_insn (); | |
4632 | ||
4633 | /* If the last insn was a BARRIER, we don't have to write any code | |
4634 | because a jump (aka return) was put there. */ | |
4635 | if (GET_CODE (insn) == NOTE) | |
4636 | insn = prev_nonnote_insn (insn); | |
4637 | if (insn && GET_CODE (insn) == BARRIER) | |
4638 | noepilogue = TRUE; | |
4639 | } | |
4640 | ||
4641 | if (!noepilogue) | |
4642 | { | |
86735b02 DE |
4643 | unsigned int reg_offset = current_frame_info.reg_offset; |
4644 | unsigned int size1; | |
4645 | char *sp_str = reg_names[STACK_POINTER_REGNUM]; | |
4646 | char *fp_str = reg_names[FRAME_POINTER_REGNUM]; | |
4647 | char *t1_str = "%g1"; | |
4648 | ||
c819be5b JW |
4649 | /* In the reload sequence, we don't need to fill the load delay |
4650 | slots for most of the loads, also see if we can fill the final | |
4651 | delay slot if not otherwise filled by the reload sequence. */ | |
4652 | ||
86735b02 DE |
4653 | if (size > 4095) |
4654 | fprintf (file, "\tset %d,%s\n", size, t1_str); | |
c819be5b JW |
4655 | |
4656 | if (frame_pointer_needed) | |
4657 | { | |
86735b02 DE |
4658 | if (size > 4095) |
4659 | fprintf (file,"\tsub %s,%s,%s\t\t!# sp not trusted here\n", | |
c819be5b JW |
4660 | fp_str, t1_str, sp_str); |
4661 | else | |
86735b02 DE |
4662 | fprintf (file,"\tsub %s,%d,%s\t\t!# sp not trusted here\n", |
4663 | fp_str, size, sp_str); | |
c819be5b JW |
4664 | } |
4665 | ||
ddd5a7c1 | 4666 | /* Is the entire register save area offsettable from %sp? */ |
86735b02 DE |
4667 | if (reg_offset < 4096 - 64 * UNITS_PER_WORD) |
4668 | { | |
4669 | size1 = 0; | |
4670 | } | |
4671 | else | |
4672 | { | |
4673 | /* Restore %sp in two steps, but make sure there is always a | |
4674 | 64 byte register save area, and %sp is properly aligned. */ | |
4675 | /* Amount to increment %sp by, the first time. */ | |
4676 | size1 = ((reg_offset - 64 - 16) + 15) & -16; | |
4677 | /* Offset to register save area from %sp. */ | |
4678 | reg_offset = size1 - reg_offset; | |
4679 | ||
4680 | fprintf (file, "\tset %d,%s\n\tadd %s,%s,%s\n", | |
4681 | size1, t1_str, sp_str, t1_str, sp_str); | |
4682 | } | |
4683 | ||
4684 | /* We must restore the frame pointer and return address reg first | |
4685 | because they are treated specially by the prologue output code. */ | |
4686 | if (current_frame_info.gmask & FRAME_POINTER_MASK) | |
4687 | { | |
4688 | fprintf (file, "\tld [%s+%d],%s\n", | |
4689 | sp_str, reg_offset, fp_str); | |
4690 | reg_offset += 4; | |
4691 | } | |
4692 | if (current_frame_info.gmask & RETURN_ADDR_MASK) | |
4693 | { | |
4694 | fprintf (file, "\tld [%s+%d],%s\n", | |
4695 | sp_str, reg_offset, reg_names[RETURN_ADDR_REGNUM]); | |
4696 | reg_offset += 4; | |
4697 | } | |
4698 | ||
4699 | /* Restore any remaining saved registers. */ | |
4700 | sparc_flat_save_restore (file, sp_str, reg_offset, | |
4701 | current_frame_info.gmask & ~(FRAME_POINTER_MASK | RETURN_ADDR_MASK), | |
4702 | current_frame_info.fmask, | |
4703 | "ld", "ldd"); | |
4704 | ||
4705 | /* If we had to increment %sp in two steps, record it so the second | |
4706 | restoration in the epilogue finishes up. */ | |
4707 | if (size1 > 0) | |
4708 | { | |
4709 | size -= size1; | |
4710 | if (size > 4095) | |
4711 | fprintf (file, "\tset %d,%s\n", | |
4712 | size, t1_str); | |
4713 | } | |
c819be5b | 4714 | |
c819be5b JW |
4715 | if (current_function_returns_struct) |
4716 | fprintf (file, "\tjmp %%o7+12\n"); | |
4717 | else | |
4718 | fprintf (file, "\tretl\n"); | |
4719 | ||
4720 | /* If the only register saved is the return address, we need a | |
4721 | nop, unless we have an instruction to put into it. Otherwise | |
4722 | we don't since reloading multiple registers doesn't reference | |
4723 | the register being loaded. */ | |
4724 | ||
4725 | if (epilogue_delay) | |
4726 | { | |
86735b02 | 4727 | if (size) |
c819be5b JW |
4728 | abort (); |
4729 | final_scan_insn (XEXP (epilogue_delay, 0), file, 1, -2, 1); | |
4730 | } | |
4731 | ||
86735b02 | 4732 | else if (size > 4095) |
c819be5b JW |
4733 | fprintf (file, "\tadd %s,%s,%s\n", sp_str, t1_str, sp_str); |
4734 | ||
86735b02 DE |
4735 | else if (size > 0) |
4736 | fprintf (file, "\tadd %s,%d,%s\n", sp_str, size, sp_str); | |
c819be5b JW |
4737 | |
4738 | else | |
4739 | fprintf (file, "\tnop\n"); | |
4740 | } | |
4741 | ||
4742 | /* Reset state info for each function. */ | |
4743 | current_frame_info = zero_frame_info; | |
4744 | } | |
4745 | \f | |
4746 | /* Define the number of delay slots needed for the function epilogue. | |
4747 | ||
4748 | On the sparc, we need a slot if either no stack has been allocated, | |
4749 | or the only register saved is the return register. */ | |
4750 | ||
4751 | int | |
c6aa9ce1 | 4752 | sparc_flat_epilogue_delay_slots () |
c819be5b JW |
4753 | { |
4754 | if (!current_frame_info.initialized) | |
c6aa9ce1 | 4755 | (void) sparc_flat_compute_frame_size (get_frame_size ()); |
c819be5b JW |
4756 | |
4757 | if (current_frame_info.total_size == 0) | |
4758 | return 1; | |
4759 | ||
c819be5b JW |
4760 | return 0; |
4761 | } | |
4762 | ||
4763 | /* Return true is TRIAL is a valid insn for the epilogue delay slot. | |
4764 | Any single length instruction which doesn't reference the stack or frame | |
4765 | pointer is OK. */ | |
4766 | ||
4767 | int | |
c6aa9ce1 | 4768 | sparc_flat_eligible_for_epilogue_delay (trial, slot) |
c819be5b JW |
4769 | rtx trial; |
4770 | int slot; | |
4771 | { | |
4772 | if (get_attr_length (trial) == 1 | |
4773 | && ! reg_mentioned_p (stack_pointer_rtx, PATTERN (trial)) | |
4774 | && ! reg_mentioned_p (frame_pointer_rtx, PATTERN (trial))) | |
4775 | return 1; | |
4776 | return 0; | |
4777 | } | |
dbb54862 JW |
4778 | \f |
4779 | /* Adjust the cost of a scheduling dependency. Return the new cost of | |
4780 | a dependency LINK or INSN on DEP_INSN. COST is the current cost. */ | |
4781 | ||
4782 | int | |
4783 | supersparc_adjust_cost (insn, link, dep_insn, cost) | |
4784 | rtx insn; | |
4785 | rtx link; | |
4786 | rtx dep_insn; | |
4787 | int cost; | |
4788 | { | |
4789 | enum attr_type insn_type; | |
4790 | ||
4791 | if (! recog_memoized (insn)) | |
4792 | return 0; | |
4793 | ||
4794 | insn_type = get_attr_type (insn); | |
4795 | ||
4796 | if (REG_NOTE_KIND (link) == 0) | |
4797 | { | |
4798 | /* Data dependency; DEP_INSN writes a register that INSN reads some | |
4799 | cycles later. */ | |
4800 | ||
4801 | /* if a load, then the dependence must be on the memory address; | |
4802 | add an extra 'cycle'. Note that the cost could be two cycles | |
4803 | if the reg was written late in an instruction group; we can't tell | |
4804 | here. */ | |
4805 | if (insn_type == TYPE_LOAD || insn_type == TYPE_FPLOAD) | |
4806 | return cost + 3; | |
4807 | ||
4808 | /* Get the delay only if the address of the store is the dependence. */ | |
4809 | if (insn_type == TYPE_STORE || insn_type == TYPE_FPSTORE) | |
4810 | { | |
4811 | rtx pat = PATTERN(insn); | |
4812 | rtx dep_pat = PATTERN (dep_insn); | |
4813 | ||
4814 | if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET) | |
4815 | return cost; /* This shouldn't happen! */ | |
4816 | ||
4817 | /* The dependency between the two instructions was on the data that | |
4818 | is being stored. Assume that this implies that the address of the | |
4819 | store is not dependent. */ | |
4820 | if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat))) | |
4821 | return cost; | |
4822 | ||
4823 | return cost + 3; /* An approximation. */ | |
4824 | } | |
4825 | ||
4826 | /* A shift instruction cannot receive its data from an instruction | |
4827 | in the same cycle; add a one cycle penalty. */ | |
4828 | if (insn_type == TYPE_SHIFT) | |
4829 | return cost + 3; /* Split before cascade into shift. */ | |
4830 | } | |
4831 | else | |
4832 | { | |
4833 | /* Anti- or output- dependency; DEP_INSN reads/writes a register that | |
4834 | INSN writes some cycles later. */ | |
4835 | ||
4836 | /* These are only significant for the fpu unit; writing a fp reg before | |
4837 | the fpu has finished with it stalls the processor. */ | |
4838 | ||
4839 | /* Reusing an integer register causes no problems. */ | |
4840 | if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT) | |
4841 | return 0; | |
4842 | } | |
4843 | ||
4844 | return cost; | |
4845 | } |