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ab835497 | 1 | /* Subroutines for insn-output.c for Sun SPARC. |
b73bf65f | 2 | Copyright (C) 1987, 88, 89, 92-98, 1999 Free Software Foundation, Inc. |
ab835497 | 3 | Contributed by Michael Tiemann (tiemann@cygnus.com) |
61a55e8b DE |
4 | 64 bit SPARC V9 support by Michael Tiemann, Jim Wilson, and Doug Evans, |
5 | at Cygnus Support. | |
ab835497 RK |
6 | |
7 | This file is part of GNU CC. | |
8 | ||
9 | GNU CC is free software; you can redistribute it and/or modify | |
10 | it under the terms of the GNU General Public License as published by | |
11 | the Free Software Foundation; either version 2, or (at your option) | |
12 | any later version. | |
13 | ||
14 | GNU CC is distributed in the hope that it will be useful, | |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
18 | ||
19 | You should have received a copy of the GNU General Public License | |
20 | along with GNU CC; see the file COPYING. If not, write to | |
c15c9075 RK |
21 | the Free Software Foundation, 59 Temple Place - Suite 330, |
22 | Boston, MA 02111-1307, USA. */ | |
ab835497 | 23 | |
ab835497 | 24 | #include "config.h" |
284d86e9 | 25 | #include "system.h" |
210aa14a | 26 | #include "tree.h" |
ab835497 RK |
27 | #include "rtl.h" |
28 | #include "regs.h" | |
29 | #include "hard-reg-set.h" | |
30 | #include "real.h" | |
31 | #include "insn-config.h" | |
32 | #include "conditions.h" | |
33 | #include "insn-flags.h" | |
34 | #include "output.h" | |
35 | #include "insn-attr.h" | |
36 | #include "flags.h" | |
49ad7cfa | 37 | #include "function.h" |
ab835497 RK |
38 | #include "expr.h" |
39 | #include "recog.h" | |
487a6e06 | 40 | #include "toplev.h" |
d07d525a | 41 | #include "ggc.h" |
b1474bb7 | 42 | #include "tm_p.h" |
ab835497 | 43 | |
61a55e8b DE |
44 | /* 1 if the caller has placed an "unimp" insn immediately after the call. |
45 | This is used in v8 code when calling a function that returns a structure. | |
06b967f9 RK |
46 | v9 doesn't have this. Be careful to have this test be the same as that |
47 | used on the call. */ | |
48 | ||
49 | #define SKIP_CALLERS_UNIMP_P \ | |
50 | (!TARGET_ARCH64 && current_function_returns_struct \ | |
51 | && ! integer_zerop (DECL_SIZE (DECL_RESULT (current_function_decl))) \ | |
52 | && (TREE_CODE (DECL_SIZE (DECL_RESULT (current_function_decl))) \ | |
53 | == INTEGER_CST)) | |
61a55e8b | 54 | |
ab835497 RK |
55 | /* Global variables for machine-dependent things. */ |
56 | ||
61a55e8b DE |
57 | /* Size of frame. Need to know this to emit return insns from leaf procedures. |
58 | ACTUAL_FSIZE is set by compute_frame_size() which is called during the | |
59 | reload pass. This is important as the value is later used in insn | |
60 | scheduling (to see what can go in a delay slot). | |
61 | APPARENT_FSIZE is the size of the stack less the register save area and less | |
62 | the outgoing argument area. It is used when saving call preserved regs. */ | |
63 | static int apparent_fsize; | |
64 | static int actual_fsize; | |
65 | ||
e48addee JJ |
66 | /* Number of live general or floating point registers needed to be saved |
67 | (as 4-byte quantities). This is only done if TARGET_EPILOGUE. */ | |
68 | static int num_gfregs; | |
69 | ||
ab835497 RK |
70 | /* Save the operands last given to a compare for use when we |
71 | generate a scc or bcc insn. */ | |
72 | ||
73 | rtx sparc_compare_op0, sparc_compare_op1; | |
74 | ||
75 | /* We may need an epilogue if we spill too many registers. | |
76 | If this is non-zero, then we branch here for the epilogue. */ | |
77 | static rtx leaf_label; | |
78 | ||
79 | #ifdef LEAF_REGISTERS | |
80 | ||
81 | /* Vector to say how input registers are mapped to output | |
82 | registers. FRAME_POINTER_REGNUM cannot be remapped by | |
83 | this function to eliminate it. You must use -fomit-frame-pointer | |
84 | to get that. */ | |
85 | char leaf_reg_remap[] = | |
86 | { 0, 1, 2, 3, 4, 5, 6, 7, | |
87 | -1, -1, -1, -1, -1, -1, 14, -1, | |
88 | -1, -1, -1, -1, -1, -1, -1, -1, | |
89 | 8, 9, 10, 11, 12, 13, -1, 15, | |
90 | ||
91 | 32, 33, 34, 35, 36, 37, 38, 39, | |
92 | 40, 41, 42, 43, 44, 45, 46, 47, | |
93 | 48, 49, 50, 51, 52, 53, 54, 55, | |
61a55e8b DE |
94 | 56, 57, 58, 59, 60, 61, 62, 63, |
95 | 64, 65, 66, 67, 68, 69, 70, 71, | |
96 | 72, 73, 74, 75, 76, 77, 78, 79, | |
97 | 80, 81, 82, 83, 84, 85, 86, 87, | |
98 | 88, 89, 90, 91, 92, 93, 94, 95, | |
c4ce6853 | 99 | 96, 97, 98, 99, 100}; |
ab835497 | 100 | |
6a4bb1fa | 101 | #endif |
ab835497 | 102 | |
ab835497 RK |
103 | /* Name of where we pretend to think the frame pointer points. |
104 | Normally, this is "%fp", but if we are in a leaf procedure, | |
61a55e8b DE |
105 | this is "%sp+something". We record "something" separately as it may be |
106 | too big for reg+constant addressing. */ | |
107 | ||
3bb5de61 | 108 | static const char *frame_base_name; |
61a55e8b | 109 | static int frame_base_offset; |
ab835497 | 110 | |
c85f7c16 | 111 | static rtx pic_setup_code PROTO((void)); |
c85f7c16 | 112 | static void sparc_init_modes PROTO((void)); |
3bb5de61 | 113 | static int save_regs PROTO((FILE *, int, int, const char *, |
c85f7c16 | 114 | int, int, int)); |
3bb5de61 KG |
115 | static int restore_regs PROTO((FILE *, int, int, const char *, int, int)); |
116 | static void build_big_number PROTO((FILE *, int, const char *)); | |
5e9defae | 117 | static int function_arg_slotno PROTO((const CUMULATIVE_ARGS *, |
c85f7c16 JL |
118 | enum machine_mode, tree, int, int, |
119 | int *, int *)); | |
8947065c RH |
120 | |
121 | static int supersparc_adjust_cost PROTO((rtx, rtx, rtx, int)); | |
122 | static int hypersparc_adjust_cost PROTO((rtx, rtx, rtx, int)); | |
123 | static int ultrasparc_adjust_cost PROTO((rtx, rtx, rtx, int)); | |
124 | ||
e0d80184 DM |
125 | static void sparc_output_addr_vec PROTO((rtx)); |
126 | static void sparc_output_addr_diff_vec PROTO((rtx)); | |
127 | static void sparc_output_deferred_case_vectors PROTO((void)); | |
d07d525a MM |
128 | static void sparc_add_gc_roots PROTO ((void)); |
129 | static void mark_ultrasparc_pipeline_state PROTO ((void *)); | |
b1474bb7 | 130 | static int check_return_regs PROTO ((rtx)); |
e48addee | 131 | static int epilogue_renumber PROTO ((rtx *, int)); |
b1474bb7 KG |
132 | static int ultra_cmove_results_ready_p PROTO ((rtx)); |
133 | static int ultra_fpmode_conflict_exists PROTO ((enum machine_mode)); | |
134 | static rtx *ultra_find_type PROTO ((int, rtx *, int)); | |
135 | static void ultra_build_types_avail PROTO ((rtx *, int)); | |
136 | static void ultra_flush_pipeline PROTO ((void)); | |
137 | static void ultra_rescan_pipeline_state PROTO ((rtx *, int)); | |
138 | static int set_extends PROTO ((rtx, rtx)); | |
61a55e8b DE |
139 | \f |
140 | /* Option handling. */ | |
141 | ||
a0a301fc | 142 | /* Code model option as passed by user. */ |
3bb5de61 | 143 | const char *sparc_cmodel_string; |
a0a301fc DE |
144 | /* Parsed value. */ |
145 | enum cmodel sparc_cmodel; | |
146 | ||
1cb36a98 RH |
147 | char sparc_hard_reg_printed[8]; |
148 | ||
16956f6e DE |
149 | struct sparc_cpu_select sparc_select[] = |
150 | { | |
151 | /* switch name, tune arch */ | |
152 | { (char *)0, "default", 1, 1 }, | |
153 | { (char *)0, "-mcpu=", 1, 1 }, | |
154 | { (char *)0, "-mtune=", 1, 0 }, | |
db3d4438 | 155 | { 0, 0, 0, 0 } |
16956f6e | 156 | }; |
733f53f5 | 157 | |
16956f6e DE |
158 | /* CPU type. This is set from TARGET_CPU_DEFAULT and -m{cpu,tune}=xxx. */ |
159 | enum processor_type sparc_cpu; | |
733f53f5 | 160 | |
61a55e8b DE |
161 | /* Validate and override various options, and do some machine dependent |
162 | initialization. */ | |
163 | ||
164 | void | |
165 | sparc_override_options () | |
166 | { | |
a0a301fc | 167 | static struct code_model { |
3bb5de61 | 168 | const char *name; |
a0a301fc DE |
169 | int value; |
170 | } cmodels[] = { | |
171 | { "32", CM_32 }, | |
172 | { "medlow", CM_MEDLOW }, | |
173 | { "medmid", CM_MEDMID }, | |
174 | { "medany", CM_MEDANY }, | |
175 | { "embmedany", CM_EMBMEDANY }, | |
176 | { 0, 0 } | |
177 | }; | |
178 | struct code_model *cmodel; | |
16956f6e | 179 | /* Map TARGET_CPU_DEFAULT to value for -m{arch,tune}=. */ |
733f53f5 DE |
180 | static struct cpu_default { |
181 | int cpu; | |
3bb5de61 | 182 | const char *name; |
733f53f5 | 183 | } cpu_default[] = { |
a0a301fc | 184 | /* There must be one entry here for each TARGET_CPU value. */ |
16956f6e | 185 | { TARGET_CPU_sparc, "cypress" }, |
3592ea0d | 186 | { TARGET_CPU_sparclet, "tsc701" }, |
16956f6e | 187 | { TARGET_CPU_sparclite, "f930" }, |
a0a301fc | 188 | { TARGET_CPU_v8, "v8" }, |
8947065c RH |
189 | { TARGET_CPU_hypersparc, "hypersparc" }, |
190 | { TARGET_CPU_sparclite86x, "sparclite86x" }, | |
a0a301fc DE |
191 | { TARGET_CPU_supersparc, "supersparc" }, |
192 | { TARGET_CPU_v9, "v9" }, | |
ba542005 | 193 | { TARGET_CPU_ultrasparc, "ultrasparc" }, |
db3d4438 | 194 | { 0, 0 } |
733f53f5 | 195 | }; |
16956f6e DE |
196 | struct cpu_default *def; |
197 | /* Table of values for -m{cpu,tune}=. */ | |
733f53f5 | 198 | static struct cpu_table { |
3bb5de61 | 199 | const char *name; |
16956f6e | 200 | enum processor_type processor; |
733f53f5 DE |
201 | int disable; |
202 | int enable; | |
203 | } cpu_table[] = { | |
16956f6e DE |
204 | { "v7", PROCESSOR_V7, MASK_ISA, 0 }, |
205 | { "cypress", PROCESSOR_CYPRESS, MASK_ISA, 0 }, | |
206 | { "v8", PROCESSOR_V8, MASK_ISA, MASK_V8 }, | |
733f53f5 | 207 | /* TI TMS390Z55 supersparc */ |
16956f6e DE |
208 | { "supersparc", PROCESSOR_SUPERSPARC, MASK_ISA, MASK_V8 }, |
209 | { "sparclite", PROCESSOR_SPARCLITE, MASK_ISA, MASK_SPARCLITE }, | |
733f53f5 DE |
210 | /* The Fujitsu MB86930 is the original sparclite chip, with no fpu. |
211 | The Fujitsu MB86934 is the recent sparclite chip, with an fpu. */ | |
16956f6e DE |
212 | { "f930", PROCESSOR_F930, MASK_ISA|MASK_FPU, MASK_SPARCLITE }, |
213 | { "f934", PROCESSOR_F934, MASK_ISA, MASK_SPARCLITE|MASK_FPU }, | |
8947065c | 214 | { "hypersparc", PROCESSOR_HYPERSPARC, MASK_ISA, MASK_V8|MASK_FPU }, |
d3ec6b06 VM |
215 | { "sparclite86x", PROCESSOR_SPARCLITE86X, MASK_ISA|MASK_FPU, |
216 | MASK_SPARCLITE }, | |
16956f6e | 217 | { "sparclet", PROCESSOR_SPARCLET, MASK_ISA, MASK_SPARCLET }, |
733f53f5 | 218 | /* TEMIC sparclet */ |
3592ea0d | 219 | { "tsc701", PROCESSOR_TSC701, MASK_ISA, MASK_SPARCLET }, |
16956f6e | 220 | { "v9", PROCESSOR_V9, MASK_ISA, MASK_V9 }, |
5cb01b65 JJ |
221 | /* TI ultrasparc I, II, IIi */ |
222 | { "ultrasparc", PROCESSOR_ULTRASPARC, MASK_ISA, MASK_V9 | |
223 | /* Although insns using %y are deprecated, it is a clear win on current | |
224 | ultrasparcs. */ | |
225 | |MASK_DEPRECATED_V8_INSNS }, | |
db3d4438 | 226 | { 0, 0, 0, 0 } |
733f53f5 | 227 | }; |
16956f6e DE |
228 | struct cpu_table *cpu; |
229 | struct sparc_cpu_select *sel; | |
a0a301fc | 230 | int fpu; |
345a6161 | 231 | |
a0a301fc DE |
232 | #ifndef SPARC_BI_ARCH |
233 | /* Check for unsupported architecture size. */ | |
234 | if (! TARGET_64BIT != DEFAULT_ARCH32_P) | |
235 | { | |
236 | error ("%s is not supported by this configuration", | |
237 | DEFAULT_ARCH32_P ? "-m64" : "-m32"); | |
238 | } | |
239 | #endif | |
240 | ||
345a6161 DM |
241 | /* At the moment we don't allow different pointer size and architecture */ |
242 | if (! TARGET_64BIT != ! TARGET_PTR64) | |
243 | { | |
244 | error ("-mptr%d not allowed on -m%d", | |
245 | TARGET_PTR64 ? 64 : 32, TARGET_64BIT ? 64 : 32); | |
246 | if (TARGET_64BIT) | |
247 | target_flags |= MASK_PTR64; | |
248 | else | |
249 | target_flags &= ~MASK_PTR64; | |
250 | } | |
251 | ||
a0a301fc DE |
252 | /* Code model selection. */ |
253 | sparc_cmodel = SPARC_DEFAULT_CMODEL; | |
345a6161 DM |
254 | |
255 | #ifdef SPARC_BI_ARCH | |
256 | if (TARGET_ARCH32) | |
257 | sparc_cmodel = CM_32; | |
258 | #endif | |
259 | ||
a0a301fc DE |
260 | if (sparc_cmodel_string != NULL) |
261 | { | |
262 | if (TARGET_ARCH64) | |
263 | { | |
264 | for (cmodel = &cmodels[0]; cmodel->name; cmodel++) | |
265 | if (strcmp (sparc_cmodel_string, cmodel->name) == 0) | |
266 | break; | |
267 | if (cmodel->name == NULL) | |
268 | error ("bad value (%s) for -mcmodel= switch", sparc_cmodel_string); | |
269 | else | |
270 | sparc_cmodel = cmodel->value; | |
271 | } | |
272 | else | |
273 | error ("-mcmodel= is not supported on 32 bit systems"); | |
274 | } | |
16956f6e | 275 | |
a0a301fc | 276 | fpu = TARGET_FPU; /* save current -mfpu status */ |
1f1406b4 | 277 | |
a0a301fc | 278 | /* Set the default CPU. */ |
16956f6e DE |
279 | for (def = &cpu_default[0]; def->name; ++def) |
280 | if (def->cpu == TARGET_CPU_DEFAULT) | |
281 | break; | |
282 | if (! def->name) | |
283 | abort (); | |
284 | sparc_select[0].string = def->name; | |
285 | ||
286 | for (sel = &sparc_select[0]; sel->name; ++sel) | |
61a55e8b | 287 | { |
16956f6e | 288 | if (sel->string) |
733f53f5 | 289 | { |
16956f6e DE |
290 | for (cpu = &cpu_table[0]; cpu->name; ++cpu) |
291 | if (! strcmp (sel->string, cpu->name)) | |
292 | { | |
293 | if (sel->set_tune_p) | |
294 | sparc_cpu = cpu->processor; | |
295 | ||
296 | if (sel->set_arch_p) | |
297 | { | |
298 | target_flags &= ~cpu->disable; | |
299 | target_flags |= cpu->enable; | |
300 | } | |
301 | break; | |
302 | } | |
303 | ||
304 | if (! cpu->name) | |
305 | error ("bad value (%s) for %s switch", sel->string, sel->name); | |
733f53f5 | 306 | } |
61a55e8b | 307 | } |
97da85b7 | 308 | |
1f1406b4 | 309 | /* If -mfpu or -mno-fpu was explicitly used, don't override with |
46cc13b3 RO |
310 | the processor default. Clear MASK_FPU_SET to avoid confusing |
311 | the reverse mapping from switch values to names. */ | |
1f1406b4 | 312 | if (TARGET_FPU_SET) |
46cc13b3 RO |
313 | { |
314 | target_flags = (target_flags & ~MASK_FPU) | fpu; | |
315 | target_flags &= ~MASK_FPU_SET; | |
316 | } | |
1f1406b4 | 317 | |
16956f6e DE |
318 | /* Use the deprecated v8 insns for sparc64 in 32 bit mode. */ |
319 | if (TARGET_V9 && TARGET_ARCH32) | |
733f53f5 | 320 | target_flags |= MASK_DEPRECATED_V8_INSNS; |
61a55e8b | 321 | |
345a6161 DM |
322 | /* V8PLUS requires V9, makes no sense in 64 bit mode. */ |
323 | if (! TARGET_V9 || TARGET_ARCH64) | |
284d86e9 JC |
324 | target_flags &= ~MASK_V8PLUS; |
325 | ||
82d6b402 RH |
326 | /* Don't use stack biasing in 32 bit mode. */ |
327 | if (TARGET_ARCH32) | |
328 | target_flags &= ~MASK_STACK_BIAS; | |
f952a238 JJ |
329 | |
330 | /* Don't allow -mvis if FPU is disabled. */ | |
331 | if (! TARGET_FPU) | |
332 | target_flags &= ~MASK_VIS; | |
82d6b402 | 333 | |
efa3896a GK |
334 | /* Supply a default value for align_functions. */ |
335 | if (align_functions == 0 && sparc_cpu == PROCESSOR_ULTRASPARC) | |
336 | align_functions = 32; | |
bf62bbf1 | 337 | |
82d6b402 RH |
338 | /* Validate PCC_STRUCT_RETURN. */ |
339 | if (flag_pcc_struct_return == DEFAULT_PCC_STRUCT_RETURN) | |
340 | flag_pcc_struct_return = (TARGET_ARCH64 ? 0 : 1); | |
341 | ||
61a55e8b DE |
342 | /* Do various machine dependent initializations. */ |
343 | sparc_init_modes (); | |
2be15d0f RH |
344 | |
345 | if ((profile_flag || profile_block_flag) | |
346 | && sparc_cmodel != CM_MEDLOW) | |
347 | { | |
348 | error ("profiling does not support code models other than medlow"); | |
349 | } | |
d07d525a MM |
350 | |
351 | /* Register global variables with the garbage collector. */ | |
352 | sparc_add_gc_roots (); | |
61a55e8b DE |
353 | } |
354 | \f | |
cd5fb1ee DE |
355 | /* Miscellaneous utilities. */ |
356 | ||
357 | /* Nonzero if CODE, a comparison, is suitable for use in v9 conditional move | |
358 | or branch on register contents instructions. */ | |
359 | ||
360 | int | |
361 | v9_regcmp_p (code) | |
362 | enum rtx_code code; | |
363 | { | |
364 | return (code == EQ || code == NE || code == GE || code == LT | |
365 | || code == LE || code == GT); | |
366 | } | |
bfd6bc60 | 367 | |
cd5fb1ee DE |
368 | \f |
369 | /* Operand constraints. */ | |
370 | ||
ab835497 | 371 | /* Return non-zero only if OP is a register of mode MODE, |
c4ce6853 DE |
372 | or const0_rtx. Don't allow const0_rtx if TARGET_LIVE_G0 because |
373 | %g0 may contain anything. */ | |
374 | ||
ab835497 RK |
375 | int |
376 | reg_or_0_operand (op, mode) | |
377 | rtx op; | |
378 | enum machine_mode mode; | |
379 | { | |
c4ce6853 DE |
380 | if (register_operand (op, mode)) |
381 | return 1; | |
382 | if (TARGET_LIVE_G0) | |
383 | return 0; | |
384 | if (op == const0_rtx) | |
ab835497 | 385 | return 1; |
5b486ce0 | 386 | if (GET_MODE (op) == VOIDmode && GET_CODE (op) == CONST_DOUBLE |
ab835497 RK |
387 | && CONST_DOUBLE_HIGH (op) == 0 |
388 | && CONST_DOUBLE_LOW (op) == 0) | |
389 | return 1; | |
302484ff JW |
390 | if (GET_MODE_CLASS (GET_MODE (op)) == MODE_FLOAT |
391 | && GET_CODE (op) == CONST_DOUBLE | |
392 | && fp_zero_operand (op)) | |
393 | return 1; | |
ab835497 RK |
394 | return 0; |
395 | } | |
396 | ||
302484ff | 397 | /* Nonzero if OP is a floating point value with value 0.0. */ |
c4ce6853 | 398 | |
302484ff JW |
399 | int |
400 | fp_zero_operand (op) | |
401 | rtx op; | |
402 | { | |
403 | REAL_VALUE_TYPE r; | |
404 | ||
405 | REAL_VALUE_FROM_CONST_DOUBLE (r, op); | |
d61ba4f4 | 406 | return (REAL_VALUES_EQUAL (r, dconst0) && ! REAL_VALUE_MINUS_ZERO (r)); |
302484ff JW |
407 | } |
408 | ||
61a55e8b DE |
409 | /* Nonzero if OP is an integer register. */ |
410 | ||
411 | int | |
412 | intreg_operand (op, mode) | |
413 | rtx op; | |
487a6e06 | 414 | enum machine_mode mode ATTRIBUTE_UNUSED; |
61a55e8b DE |
415 | { |
416 | return (register_operand (op, SImode) | |
a9e27770 | 417 | || (TARGET_ARCH64 && register_operand (op, DImode))); |
61a55e8b DE |
418 | } |
419 | ||
420 | /* Nonzero if OP is a floating point condition code register. */ | |
421 | ||
422 | int | |
c4ce6853 | 423 | fcc_reg_operand (op, mode) |
61a55e8b DE |
424 | rtx op; |
425 | enum machine_mode mode; | |
426 | { | |
427 | /* This can happen when recog is called from combine. Op may be a MEM. | |
428 | Fail instead of calling abort in this case. */ | |
c4ce6853 | 429 | if (GET_CODE (op) != REG) |
61a55e8b | 430 | return 0; |
304b7a23 | 431 | |
c4ce6853 | 432 | if (mode != VOIDmode && mode != GET_MODE (op)) |
61a55e8b | 433 | return 0; |
304b7a23 DE |
434 | if (mode == VOIDmode |
435 | && (GET_MODE (op) != CCFPmode && GET_MODE (op) != CCFPEmode)) | |
436 | return 0; | |
61a55e8b | 437 | |
c4ce6853 | 438 | #if 0 /* ??? ==> 1 when %fcc0-3 are pseudos first. See gen_compare_reg(). */ |
61a55e8b DE |
439 | if (reg_renumber == 0) |
440 | return REGNO (op) >= FIRST_PSEUDO_REGISTER; | |
441 | return REGNO_OK_FOR_CCFP_P (REGNO (op)); | |
442 | #else | |
c4ce6853 | 443 | return (unsigned) REGNO (op) - SPARC_FIRST_V9_FCC_REG < 4; |
61a55e8b DE |
444 | #endif |
445 | } | |
446 | ||
c4ce6853 DE |
447 | /* Nonzero if OP is an integer or floating point condition code register. */ |
448 | ||
449 | int | |
450 | icc_or_fcc_reg_operand (op, mode) | |
451 | rtx op; | |
452 | enum machine_mode mode; | |
453 | { | |
454 | if (GET_CODE (op) == REG && REGNO (op) == SPARC_ICC_REG) | |
304b7a23 DE |
455 | { |
456 | if (mode != VOIDmode && mode != GET_MODE (op)) | |
457 | return 0; | |
458 | if (mode == VOIDmode | |
459 | && GET_MODE (op) != CCmode && GET_MODE (op) != CCXmode) | |
460 | return 0; | |
461 | return 1; | |
462 | } | |
463 | ||
c4ce6853 DE |
464 | return fcc_reg_operand (op, mode); |
465 | } | |
466 | ||
ab835497 RK |
467 | /* Nonzero if OP can appear as the dest of a RESTORE insn. */ |
468 | int | |
469 | restore_operand (op, mode) | |
470 | rtx op; | |
471 | enum machine_mode mode; | |
472 | { | |
473 | return (GET_CODE (op) == REG && GET_MODE (op) == mode | |
474 | && (REGNO (op) < 8 || (REGNO (op) >= 24 && REGNO (op) < 32))); | |
475 | } | |
476 | ||
401cec23 JW |
477 | /* Call insn on SPARC can take a PC-relative constant address, or any regular |
478 | memory address. */ | |
ab835497 RK |
479 | |
480 | int | |
481 | call_operand (op, mode) | |
482 | rtx op; | |
483 | enum machine_mode mode; | |
484 | { | |
485 | if (GET_CODE (op) != MEM) | |
486 | abort (); | |
487 | op = XEXP (op, 0); | |
2445f289 | 488 | return (symbolic_operand (op, mode) || memory_address_p (Pmode, op)); |
ab835497 RK |
489 | } |
490 | ||
491 | int | |
492 | call_operand_address (op, mode) | |
493 | rtx op; | |
494 | enum machine_mode mode; | |
495 | { | |
2445f289 | 496 | return (symbolic_operand (op, mode) || memory_address_p (Pmode, op)); |
ab835497 RK |
497 | } |
498 | ||
499 | /* Returns 1 if OP is either a symbol reference or a sum of a symbol | |
500 | reference and a constant. */ | |
501 | ||
502 | int | |
503 | symbolic_operand (op, mode) | |
504 | register rtx op; | |
505 | enum machine_mode mode; | |
506 | { | |
6871dd65 RH |
507 | enum machine_mode omode = GET_MODE (op); |
508 | ||
509 | if (omode != mode && omode != VOIDmode && mode != VOIDmode) | |
510 | return 0; | |
511 | ||
ab835497 RK |
512 | switch (GET_CODE (op)) |
513 | { | |
514 | case SYMBOL_REF: | |
515 | case LABEL_REF: | |
516 | return 1; | |
517 | ||
518 | case CONST: | |
519 | op = XEXP (op, 0); | |
520 | return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF | |
521 | || GET_CODE (XEXP (op, 0)) == LABEL_REF) | |
522 | && GET_CODE (XEXP (op, 1)) == CONST_INT); | |
523 | ||
ab835497 RK |
524 | default: |
525 | return 0; | |
526 | } | |
527 | } | |
528 | ||
529 | /* Return truth value of statement that OP is a symbolic memory | |
530 | operand of mode MODE. */ | |
531 | ||
532 | int | |
533 | symbolic_memory_operand (op, mode) | |
534 | rtx op; | |
487a6e06 | 535 | enum machine_mode mode ATTRIBUTE_UNUSED; |
ab835497 RK |
536 | { |
537 | if (GET_CODE (op) == SUBREG) | |
538 | op = SUBREG_REG (op); | |
539 | if (GET_CODE (op) != MEM) | |
540 | return 0; | |
541 | op = XEXP (op, 0); | |
542 | return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST | |
543 | || GET_CODE (op) == HIGH || GET_CODE (op) == LABEL_REF); | |
544 | } | |
545 | ||
5ab7138b DE |
546 | /* Return truth value of statement that OP is a LABEL_REF of mode MODE. */ |
547 | ||
548 | int | |
549 | label_ref_operand (op, mode) | |
550 | rtx op; | |
551 | enum machine_mode mode; | |
552 | { | |
553 | if (GET_CODE (op) != LABEL_REF) | |
554 | return 0; | |
555 | if (GET_MODE (op) != mode) | |
556 | return 0; | |
557 | return 1; | |
558 | } | |
559 | ||
95726648 DE |
560 | /* Return 1 if the operand is an argument used in generating pic references |
561 | in either the medium/low or medium/anywhere code models of sparc64. */ | |
562 | ||
563 | int | |
564 | sp64_medium_pic_operand (op, mode) | |
565 | rtx op; | |
487a6e06 | 566 | enum machine_mode mode ATTRIBUTE_UNUSED; |
95726648 DE |
567 | { |
568 | /* Check for (const (minus (symbol_ref:GOT) | |
569 | (const (minus (label) (pc))))). */ | |
570 | if (GET_CODE (op) != CONST) | |
571 | return 0; | |
572 | op = XEXP (op, 0); | |
573 | if (GET_CODE (op) != MINUS) | |
574 | return 0; | |
575 | if (GET_CODE (XEXP (op, 0)) != SYMBOL_REF) | |
576 | return 0; | |
577 | /* ??? Ensure symbol is GOT. */ | |
578 | if (GET_CODE (XEXP (op, 1)) != CONST) | |
579 | return 0; | |
580 | if (GET_CODE (XEXP (XEXP (op, 1), 0)) != MINUS) | |
581 | return 0; | |
582 | return 1; | |
583 | } | |
584 | ||
61a55e8b DE |
585 | /* Return 1 if the operand is a data segment reference. This includes |
586 | the readonly data segment, or in other words anything but the text segment. | |
587 | This is needed in the medium/anywhere code model on v9. These values | |
a0a301fc | 588 | are accessed with EMBMEDANY_BASE_REG. */ |
61a55e8b DE |
589 | |
590 | int | |
591 | data_segment_operand (op, mode) | |
592 | rtx op; | |
487a6e06 | 593 | enum machine_mode mode ATTRIBUTE_UNUSED; |
61a55e8b DE |
594 | { |
595 | switch (GET_CODE (op)) | |
596 | { | |
597 | case SYMBOL_REF : | |
598 | return ! SYMBOL_REF_FLAG (op); | |
599 | case PLUS : | |
95726648 DE |
600 | /* Assume canonical format of symbol + constant. |
601 | Fall through. */ | |
61a55e8b | 602 | case CONST : |
b1474bb7 | 603 | return data_segment_operand (XEXP (op, 0), VOIDmode); |
61a55e8b DE |
604 | default : |
605 | return 0; | |
606 | } | |
607 | } | |
608 | ||
609 | /* Return 1 if the operand is a text segment reference. | |
610 | This is needed in the medium/anywhere code model on v9. */ | |
611 | ||
612 | int | |
613 | text_segment_operand (op, mode) | |
614 | rtx op; | |
487a6e06 | 615 | enum machine_mode mode ATTRIBUTE_UNUSED; |
61a55e8b DE |
616 | { |
617 | switch (GET_CODE (op)) | |
618 | { | |
619 | case LABEL_REF : | |
620 | return 1; | |
621 | case SYMBOL_REF : | |
622 | return SYMBOL_REF_FLAG (op); | |
623 | case PLUS : | |
95726648 DE |
624 | /* Assume canonical format of symbol + constant. |
625 | Fall through. */ | |
61a55e8b | 626 | case CONST : |
b1474bb7 | 627 | return text_segment_operand (XEXP (op, 0), VOIDmode); |
61a55e8b DE |
628 | default : |
629 | return 0; | |
630 | } | |
631 | } | |
632 | ||
ab835497 RK |
633 | /* Return 1 if the operand is either a register or a memory operand that is |
634 | not symbolic. */ | |
635 | ||
636 | int | |
637 | reg_or_nonsymb_mem_operand (op, mode) | |
638 | register rtx op; | |
639 | enum machine_mode mode; | |
640 | { | |
641 | if (register_operand (op, mode)) | |
642 | return 1; | |
643 | ||
644 | if (memory_operand (op, mode) && ! symbolic_memory_operand (op, mode)) | |
645 | return 1; | |
646 | ||
647 | return 0; | |
648 | } | |
649 | ||
ab835497 | 650 | int |
6ac34277 | 651 | splittable_symbolic_memory_operand (op, mode) |
ab835497 | 652 | rtx op; |
487a6e06 | 653 | enum machine_mode mode ATTRIBUTE_UNUSED; |
ab835497 | 654 | { |
6ac34277 DE |
655 | if (GET_CODE (op) != MEM) |
656 | return 0; | |
657 | if (! symbolic_operand (XEXP (op, 0), Pmode)) | |
658 | return 0; | |
659 | return 1; | |
660 | } | |
661 | ||
662 | int | |
663 | splittable_immediate_memory_operand (op, mode) | |
664 | rtx op; | |
487a6e06 | 665 | enum machine_mode mode ATTRIBUTE_UNUSED; |
6ac34277 DE |
666 | { |
667 | if (GET_CODE (op) != MEM) | |
668 | return 0; | |
669 | if (! immediate_operand (XEXP (op, 0), Pmode)) | |
670 | return 0; | |
671 | return 1; | |
ab835497 RK |
672 | } |
673 | ||
674 | /* Return truth value of whether OP is EQ or NE. */ | |
675 | ||
676 | int | |
677 | eq_or_neq (op, mode) | |
678 | rtx op; | |
487a6e06 | 679 | enum machine_mode mode ATTRIBUTE_UNUSED; |
ab835497 RK |
680 | { |
681 | return (GET_CODE (op) == EQ || GET_CODE (op) == NE); | |
682 | } | |
683 | ||
684 | /* Return 1 if this is a comparison operator, but not an EQ, NE, GEU, | |
685 | or LTU for non-floating-point. We handle those specially. */ | |
686 | ||
687 | int | |
688 | normal_comp_operator (op, mode) | |
689 | rtx op; | |
487a6e06 | 690 | enum machine_mode mode ATTRIBUTE_UNUSED; |
ab835497 RK |
691 | { |
692 | enum rtx_code code = GET_CODE (op); | |
693 | ||
694 | if (GET_RTX_CLASS (code) != '<') | |
695 | return 0; | |
696 | ||
4d449554 JW |
697 | if (GET_MODE (XEXP (op, 0)) == CCFPmode |
698 | || GET_MODE (XEXP (op, 0)) == CCFPEmode) | |
ab835497 RK |
699 | return 1; |
700 | ||
701 | return (code != NE && code != EQ && code != GEU && code != LTU); | |
702 | } | |
703 | ||
704 | /* Return 1 if this is a comparison operator. This allows the use of | |
705 | MATCH_OPERATOR to recognize all the branch insns. */ | |
706 | ||
707 | int | |
708 | noov_compare_op (op, mode) | |
709 | register rtx op; | |
487a6e06 | 710 | enum machine_mode mode ATTRIBUTE_UNUSED; |
ab835497 RK |
711 | { |
712 | enum rtx_code code = GET_CODE (op); | |
713 | ||
714 | if (GET_RTX_CLASS (code) != '<') | |
715 | return 0; | |
716 | ||
717 | if (GET_MODE (XEXP (op, 0)) == CC_NOOVmode) | |
718 | /* These are the only branches which work with CC_NOOVmode. */ | |
719 | return (code == EQ || code == NE || code == GE || code == LT); | |
720 | return 1; | |
721 | } | |
722 | ||
61a55e8b DE |
723 | /* Nonzero if OP is a comparison operator suitable for use in v9 |
724 | conditional move or branch on register contents instructions. */ | |
725 | ||
726 | int | |
727 | v9_regcmp_op (op, mode) | |
728 | register rtx op; | |
487a6e06 | 729 | enum machine_mode mode ATTRIBUTE_UNUSED; |
61a55e8b DE |
730 | { |
731 | enum rtx_code code = GET_CODE (op); | |
732 | ||
733 | if (GET_RTX_CLASS (code) != '<') | |
734 | return 0; | |
735 | ||
cd5fb1ee | 736 | return v9_regcmp_p (code); |
61a55e8b DE |
737 | } |
738 | ||
ab835497 RK |
739 | /* Return 1 if this is a SIGN_EXTEND or ZERO_EXTEND operation. */ |
740 | ||
741 | int | |
742 | extend_op (op, mode) | |
743 | rtx op; | |
487a6e06 | 744 | enum machine_mode mode ATTRIBUTE_UNUSED; |
ab835497 RK |
745 | { |
746 | return GET_CODE (op) == SIGN_EXTEND || GET_CODE (op) == ZERO_EXTEND; | |
747 | } | |
748 | ||
749 | /* Return nonzero if OP is an operator of mode MODE which can set | |
750 | the condition codes explicitly. We do not include PLUS and MINUS | |
751 | because these require CC_NOOVmode, which we handle explicitly. */ | |
752 | ||
753 | int | |
754 | cc_arithop (op, mode) | |
755 | rtx op; | |
487a6e06 | 756 | enum machine_mode mode ATTRIBUTE_UNUSED; |
ab835497 RK |
757 | { |
758 | if (GET_CODE (op) == AND | |
759 | || GET_CODE (op) == IOR | |
760 | || GET_CODE (op) == XOR) | |
761 | return 1; | |
762 | ||
763 | return 0; | |
764 | } | |
765 | ||
766 | /* Return nonzero if OP is an operator of mode MODE which can bitwise | |
767 | complement its second operand and set the condition codes explicitly. */ | |
768 | ||
769 | int | |
770 | cc_arithopn (op, mode) | |
771 | rtx op; | |
487a6e06 | 772 | enum machine_mode mode ATTRIBUTE_UNUSED; |
ab835497 RK |
773 | { |
774 | /* XOR is not here because combine canonicalizes (xor (not ...) ...) | |
775 | and (xor ... (not ...)) to (not (xor ...)). */ | |
776 | return (GET_CODE (op) == AND | |
777 | || GET_CODE (op) == IOR); | |
778 | } | |
779 | \f | |
58cbf20e DE |
780 | /* Return true if OP is a register, or is a CONST_INT that can fit in a |
781 | signed 13 bit immediate field. This is an acceptable SImode operand for | |
782 | most 3 address instructions. */ | |
ab835497 RK |
783 | |
784 | int | |
785 | arith_operand (op, mode) | |
786 | rtx op; | |
787 | enum machine_mode mode; | |
788 | { | |
284d86e9 | 789 | int val; |
11301057 | 790 | if (register_operand (op, mode)) |
284d86e9 JC |
791 | return 1; |
792 | if (GET_CODE (op) != CONST_INT) | |
793 | return 0; | |
794 | val = INTVAL (op) & 0xffffffff; | |
795 | return SPARC_SIMM13_P (val); | |
ab835497 RK |
796 | } |
797 | ||
5d6d3339 JJ |
798 | /* Return true if OP is a constant 4096 */ |
799 | ||
800 | int | |
801 | arith_4096_operand (op, mode) | |
802 | rtx op; | |
ddf80874 | 803 | enum machine_mode mode ATTRIBUTE_UNUSED; |
5d6d3339 JJ |
804 | { |
805 | int val; | |
806 | if (GET_CODE (op) != CONST_INT) | |
807 | return 0; | |
808 | val = INTVAL (op) & 0xffffffff; | |
809 | return val == 4096; | |
810 | } | |
811 | ||
812 | /* Return true if OP is suitable as second operand for add/sub */ | |
813 | ||
814 | int | |
815 | arith_add_operand (op, mode) | |
816 | rtx op; | |
817 | enum machine_mode mode; | |
818 | { | |
819 | return arith_operand (op, mode) || arith_4096_operand (op, mode); | |
820 | } | |
821 | ||
89e65674 DM |
822 | /* Return true if OP is a CONST_INT or a CONST_DOUBLE which can fit in the |
823 | immediate field of OR and XOR instructions. Used for 64-bit | |
824 | constant formation patterns. */ | |
825 | int | |
826 | const64_operand (op, mode) | |
827 | rtx op; | |
ddf80874 | 828 | enum machine_mode mode ATTRIBUTE_UNUSED; |
89e65674 DM |
829 | { |
830 | return ((GET_CODE (op) == CONST_INT | |
831 | && SPARC_SIMM13_P (INTVAL (op))) | |
9208e4b2 | 832 | #if HOST_BITS_PER_WIDE_INT != 64 |
89e65674 | 833 | || (GET_CODE (op) == CONST_DOUBLE |
9208e4b2 DM |
834 | && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op)) |
835 | && (CONST_DOUBLE_HIGH (op) == | |
836 | ((CONST_DOUBLE_LOW (op) & 0x80000000) != 0 ? | |
ddf80874 | 837 | (HOST_WIDE_INT)0xffffffff : 0))) |
9208e4b2 | 838 | #endif |
11301057 | 839 | ); |
89e65674 DM |
840 | } |
841 | ||
9208e4b2 | 842 | /* The same, but only for sethi instructions. */ |
89e65674 DM |
843 | int |
844 | const64_high_operand (op, mode) | |
845 | rtx op; | |
ddf80874 | 846 | enum machine_mode mode ATTRIBUTE_UNUSED; |
89e65674 DM |
847 | { |
848 | return ((GET_CODE (op) == CONST_INT | |
9208e4b2 DM |
849 | && (INTVAL (op) & 0xfffffc00) != 0 |
850 | && SPARC_SETHI_P (INTVAL (op)) | |
851 | #if HOST_BITS_PER_WIDE_INT != 64 | |
852 | /* Must be positive on non-64bit host else the | |
853 | optimizer is fooled into thinking that sethi | |
854 | sign extends, even though it does not. */ | |
855 | && INTVAL (op) >= 0 | |
856 | #endif | |
857 | ) | |
89e65674 DM |
858 | || (GET_CODE (op) == CONST_DOUBLE |
859 | && CONST_DOUBLE_HIGH (op) == 0 | |
9208e4b2 | 860 | && (CONST_DOUBLE_LOW (op) & 0xfffffc00) != 0 |
11301057 | 861 | && SPARC_SETHI_P (CONST_DOUBLE_LOW (op)))); |
89e65674 DM |
862 | } |
863 | ||
58cbf20e DE |
864 | /* Return true if OP is a register, or is a CONST_INT that can fit in a |
865 | signed 11 bit immediate field. This is an acceptable SImode operand for | |
866 | the movcc instructions. */ | |
61a55e8b DE |
867 | |
868 | int | |
869 | arith11_operand (op, mode) | |
870 | rtx op; | |
871 | enum machine_mode mode; | |
872 | { | |
873 | return (register_operand (op, mode) | |
58cbf20e | 874 | || (GET_CODE (op) == CONST_INT && SPARC_SIMM11_P (INTVAL (op)))); |
61a55e8b DE |
875 | } |
876 | ||
58cbf20e DE |
877 | /* Return true if OP is a register, or is a CONST_INT that can fit in a |
878 | signed 10 bit immediate field. This is an acceptable SImode operand for | |
879 | the movrcc instructions. */ | |
61a55e8b DE |
880 | |
881 | int | |
882 | arith10_operand (op, mode) | |
883 | rtx op; | |
884 | enum machine_mode mode; | |
885 | { | |
886 | return (register_operand (op, mode) | |
58cbf20e | 887 | || (GET_CODE (op) == CONST_INT && SPARC_SIMM10_P (INTVAL (op)))); |
61a55e8b DE |
888 | } |
889 | ||
23b8a89f JW |
890 | /* Return true if OP is a register, is a CONST_INT that fits in a 13 bit |
891 | immediate field, or is a CONST_DOUBLE whose both parts fit in a 13 bit | |
61a55e8b DE |
892 | immediate field. |
893 | v9: Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that | |
894 | can fit in a 13 bit immediate field. This is an acceptable DImode operand | |
895 | for most 3 address instructions. */ | |
ab835497 RK |
896 | |
897 | int | |
898 | arith_double_operand (op, mode) | |
899 | rtx op; | |
900 | enum machine_mode mode; | |
901 | { | |
902 | return (register_operand (op, mode) | |
23b8a89f | 903 | || (GET_CODE (op) == CONST_INT && SMALL_INT (op)) |
a9e27770 | 904 | || (! TARGET_ARCH64 |
61a55e8b | 905 | && GET_CODE (op) == CONST_DOUBLE |
bf62bbf1 DE |
906 | && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x1000) < 0x2000 |
907 | && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_HIGH (op) + 0x1000) < 0x2000) | |
a9e27770 | 908 | || (TARGET_ARCH64 |
61a55e8b | 909 | && GET_CODE (op) == CONST_DOUBLE |
bf62bbf1 | 910 | && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x1000) < 0x2000 |
61a55e8b DE |
911 | && ((CONST_DOUBLE_HIGH (op) == -1 |
912 | && (CONST_DOUBLE_LOW (op) & 0x1000) == 0x1000) | |
913 | || (CONST_DOUBLE_HIGH (op) == 0 | |
914 | && (CONST_DOUBLE_LOW (op) & 0x1000) == 0)))); | |
915 | } | |
916 | ||
5d6d3339 JJ |
917 | /* Return true if OP is a constant 4096 for DImode on ARCH64 */ |
918 | ||
919 | int | |
920 | arith_double_4096_operand (op, mode) | |
921 | rtx op; | |
ddf80874 | 922 | enum machine_mode mode ATTRIBUTE_UNUSED; |
5d6d3339 JJ |
923 | { |
924 | return (TARGET_ARCH64 && | |
925 | ((GET_CODE (op) == CONST_INT && INTVAL (op) == 4096) || | |
926 | (GET_CODE (op) == CONST_DOUBLE && | |
927 | CONST_DOUBLE_LOW (op) == 4096 && | |
928 | CONST_DOUBLE_HIGH (op) == 0))); | |
929 | } | |
930 | ||
931 | /* Return true if OP is suitable as second operand for add/sub in DImode */ | |
932 | ||
933 | int | |
934 | arith_double_add_operand (op, mode) | |
935 | rtx op; | |
936 | enum machine_mode mode; | |
937 | { | |
938 | return arith_double_operand (op, mode) || arith_double_4096_operand (op, mode); | |
939 | } | |
940 | ||
61a55e8b DE |
941 | /* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that |
942 | can fit in an 11 bit immediate field. This is an acceptable DImode | |
943 | operand for the movcc instructions. */ | |
944 | /* ??? Replace with arith11_operand? */ | |
945 | ||
946 | int | |
947 | arith11_double_operand (op, mode) | |
948 | rtx op; | |
949 | enum machine_mode mode; | |
950 | { | |
951 | return (register_operand (op, mode) | |
952 | || (GET_CODE (op) == CONST_DOUBLE | |
953 | && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode) | |
bf62bbf1 | 954 | && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x400) < 0x800 |
61a55e8b DE |
955 | && ((CONST_DOUBLE_HIGH (op) == -1 |
956 | && (CONST_DOUBLE_LOW (op) & 0x400) == 0x400) | |
957 | || (CONST_DOUBLE_HIGH (op) == 0 | |
958 | && (CONST_DOUBLE_LOW (op) & 0x400) == 0))) | |
959 | || (GET_CODE (op) == CONST_INT | |
960 | && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode) | |
bf62bbf1 | 961 | && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x400) < 0x800)); |
61a55e8b DE |
962 | } |
963 | ||
964 | /* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that | |
965 | can fit in an 10 bit immediate field. This is an acceptable DImode | |
966 | operand for the movrcc instructions. */ | |
967 | /* ??? Replace with arith10_operand? */ | |
968 | ||
969 | int | |
970 | arith10_double_operand (op, mode) | |
971 | rtx op; | |
972 | enum machine_mode mode; | |
973 | { | |
974 | return (register_operand (op, mode) | |
975 | || (GET_CODE (op) == CONST_DOUBLE | |
976 | && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode) | |
977 | && (unsigned) (CONST_DOUBLE_LOW (op) + 0x200) < 0x400 | |
978 | && ((CONST_DOUBLE_HIGH (op) == -1 | |
979 | && (CONST_DOUBLE_LOW (op) & 0x200) == 0x200) | |
980 | || (CONST_DOUBLE_HIGH (op) == 0 | |
981 | && (CONST_DOUBLE_LOW (op) & 0x200) == 0))) | |
982 | || (GET_CODE (op) == CONST_INT | |
983 | && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode) | |
bf62bbf1 | 984 | && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x200) < 0x400)); |
ab835497 RK |
985 | } |
986 | ||
987 | /* Return truth value of whether OP is a integer which fits the | |
228b4037 JW |
988 | range constraining immediate operands in most three-address insns, |
989 | which have a 13 bit immediate field. */ | |
ab835497 RK |
990 | |
991 | int | |
992 | small_int (op, mode) | |
993 | rtx op; | |
487a6e06 | 994 | enum machine_mode mode ATTRIBUTE_UNUSED; |
ab835497 | 995 | { |
11301057 | 996 | return (GET_CODE (op) == CONST_INT && SMALL_INT (op)); |
ab835497 RK |
997 | } |
998 | ||
e0d80184 DM |
999 | int |
1000 | small_int_or_double (op, mode) | |
1001 | rtx op; | |
1002 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
1003 | { | |
1004 | return ((GET_CODE (op) == CONST_INT && SMALL_INT (op)) | |
1005 | || (GET_CODE (op) == CONST_DOUBLE | |
1006 | && CONST_DOUBLE_HIGH (op) == 0 | |
11301057 | 1007 | && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op)))); |
e0d80184 DM |
1008 | } |
1009 | ||
9b3fad96 JW |
1010 | /* Recognize operand values for the umul instruction. That instruction sign |
1011 | extends immediate values just like all other sparc instructions, but | |
1012 | interprets the extended result as an unsigned number. */ | |
1013 | ||
1014 | int | |
1015 | uns_small_int (op, mode) | |
1016 | rtx op; | |
487a6e06 | 1017 | enum machine_mode mode ATTRIBUTE_UNUSED; |
9b3fad96 JW |
1018 | { |
1019 | #if HOST_BITS_PER_WIDE_INT > 32 | |
1020 | /* All allowed constants will fit a CONST_INT. */ | |
11301057 RH |
1021 | return (GET_CODE (op) == CONST_INT |
1022 | && ((INTVAL (op) >= 0 && INTVAL (op) < 0x1000) | |
1023 | || (INTVAL (op) >= 0xFFFFF000 | |
1024 | && INTVAL (op) < 0x100000000))); | |
9b3fad96 | 1025 | #else |
11301057 RH |
1026 | return ((GET_CODE (op) == CONST_INT && (unsigned) INTVAL (op) < 0x1000) |
1027 | || (GET_CODE (op) == CONST_DOUBLE | |
1028 | && CONST_DOUBLE_HIGH (op) == 0 | |
1029 | && (unsigned) CONST_DOUBLE_LOW (op) - 0xFFFFF000 < 0x1000)); | |
9b3fad96 JW |
1030 | #endif |
1031 | } | |
1032 | ||
1033 | int | |
1034 | uns_arith_operand (op, mode) | |
1035 | rtx op; | |
1036 | enum machine_mode mode; | |
1037 | { | |
1038 | return register_operand (op, mode) || uns_small_int (op, mode); | |
1039 | } | |
1040 | ||
ab835497 RK |
1041 | /* Return truth value of statement that OP is a call-clobbered register. */ |
1042 | int | |
1043 | clobbered_register (op, mode) | |
1044 | rtx op; | |
487a6e06 | 1045 | enum machine_mode mode ATTRIBUTE_UNUSED; |
ab835497 RK |
1046 | { |
1047 | return (GET_CODE (op) == REG && call_used_regs[REGNO (op)]); | |
1048 | } | |
ab835497 | 1049 | |
e0d80184 DM |
1050 | /* Return 1 if OP is const0_rtx, used for TARGET_LIVE_G0 insns. */ |
1051 | ||
1052 | int | |
1053 | zero_operand (op, mode) | |
1054 | rtx op; | |
1055 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
ab835497 | 1056 | { |
11301057 | 1057 | return op == const0_rtx; |
e0d80184 | 1058 | } |
61a55e8b | 1059 | |
e0d80184 | 1060 | /* Return 1 if OP is a valid operand for the source of a move insn. */ |
61a55e8b | 1061 | |
e0d80184 DM |
1062 | int |
1063 | input_operand (op, mode) | |
1064 | rtx op; | |
1065 | enum machine_mode mode; | |
1066 | { | |
1067 | /* If both modes are non-void they must be the same. */ | |
1068 | if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op)) | |
1069 | return 0; | |
61a55e8b | 1070 | |
11301057 RH |
1071 | /* Only a tiny bit of handling for CONSTANT_P_RTX is necessary. */ |
1072 | if (GET_CODE (op) == CONST && GET_CODE (XEXP (op, 0)) == CONSTANT_P_RTX) | |
1073 | return 1; | |
1074 | ||
e0d80184 DM |
1075 | /* Allow any one instruction integer constant, and all CONST_INT |
1076 | variants when we are working in DImode and !arch64. */ | |
1077 | if (GET_MODE_CLASS (mode) == MODE_INT | |
9208e4b2 DM |
1078 | && ((GET_CODE (op) == CONST_INT |
1079 | && ((SPARC_SETHI_P (INTVAL (op)) | |
1080 | && (! TARGET_ARCH64 | |
1081 | || (INTVAL (op) >= 0) | |
1082 | || mode == SImode)) | |
1083 | || SPARC_SIMM13_P (INTVAL (op)) | |
1084 | || (mode == DImode | |
1085 | && ! TARGET_ARCH64))) | |
1086 | || (TARGET_ARCH64 | |
1087 | && GET_CODE (op) == CONST_DOUBLE | |
1088 | && ((CONST_DOUBLE_HIGH (op) == 0 | |
1089 | && SPARC_SETHI_P (CONST_DOUBLE_LOW (op))) | |
1090 | || | |
1091 | #if HOST_BITS_PER_WIDE_INT == 64 | |
1092 | (CONST_DOUBLE_HIGH (op) == 0 | |
1093 | && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op))) | |
1094 | #else | |
1095 | (SPARC_SIMM13_P (CONST_DOUBLE_LOW (op)) | |
1096 | && (((CONST_DOUBLE_LOW (op) & 0x80000000) == 0 | |
1097 | && CONST_DOUBLE_HIGH (op) == 0) | |
1098 | || (CONST_DOUBLE_HIGH (op) == -1))) | |
1099 | #endif | |
1100 | )))) | |
e0d80184 DM |
1101 | return 1; |
1102 | ||
e0d80184 DM |
1103 | /* If !arch64 and this is a DImode const, allow it so that |
1104 | the splits can be generated. */ | |
1105 | if (! TARGET_ARCH64 | |
1106 | && mode == DImode | |
1107 | && GET_CODE (op) == CONST_DOUBLE) | |
1108 | return 1; | |
1109 | ||
1110 | if (register_operand (op, mode)) | |
1111 | return 1; | |
1112 | ||
1113 | /* If this is a SUBREG, look inside so that we handle | |
1114 | paradoxical ones. */ | |
1115 | if (GET_CODE (op) == SUBREG) | |
1116 | op = SUBREG_REG (op); | |
1117 | ||
1118 | /* Check for valid MEM forms. */ | |
1119 | if (GET_CODE (op) == MEM) | |
61a55e8b | 1120 | { |
e0d80184 | 1121 | rtx inside = XEXP (op, 0); |
61a55e8b | 1122 | |
e0d80184 | 1123 | if (GET_CODE (inside) == LO_SUM) |
03ad6f4d DM |
1124 | { |
1125 | /* We can't allow these because all of the splits | |
1126 | (eventually as they trickle down into DFmode | |
1127 | splits) require offsettable memory references. */ | |
1128 | if (! TARGET_V9 | |
1129 | && GET_MODE (op) == TFmode) | |
1130 | return 0; | |
1131 | ||
1132 | return (register_operand (XEXP (inside, 0), Pmode) | |
1133 | && CONSTANT_P (XEXP (inside, 1))); | |
1134 | } | |
e0d80184 | 1135 | return memory_address_p (mode, inside); |
61a55e8b | 1136 | } |
ab835497 | 1137 | |
e0d80184 DM |
1138 | return 0; |
1139 | } | |
1140 | ||
1141 | \f | |
1142 | /* We know it can't be done in one insn when we get here, | |
1143 | the movsi expander guarentees this. */ | |
1144 | void | |
1145 | sparc_emit_set_const32 (op0, op1) | |
1146 | rtx op0; | |
1147 | rtx op1; | |
1148 | { | |
1149 | enum machine_mode mode = GET_MODE (op0); | |
1150 | rtx temp; | |
1151 | ||
1152 | if (GET_CODE (op1) == CONST_INT) | |
284d86e9 | 1153 | { |
2a01c939 | 1154 | HOST_WIDE_INT value = INTVAL (op1); |
e0d80184 DM |
1155 | |
1156 | if (SPARC_SETHI_P (value) | |
1157 | || SPARC_SIMM13_P (value)) | |
1158 | abort (); | |
284d86e9 | 1159 | } |
e0d80184 DM |
1160 | |
1161 | /* Full 2-insn decomposition is needed. */ | |
1162 | if (reload_in_progress || reload_completed) | |
1163 | temp = op0; | |
284d86e9 | 1164 | else |
e0d80184 DM |
1165 | temp = gen_reg_rtx (mode); |
1166 | ||
71648202 DM |
1167 | if (GET_CODE (op1) == CONST_INT) |
1168 | { | |
1169 | /* Emit them as real moves instead of a HIGH/LO_SUM, | |
1170 | this way CSE can see everything and reuse intermediate | |
1171 | values if it wants. */ | |
1172 | if (TARGET_ARCH64 | |
1173 | && HOST_BITS_PER_WIDE_INT != 64 | |
1174 | && (INTVAL (op1) & 0x80000000) != 0) | |
1175 | { | |
1176 | emit_insn (gen_rtx_SET (VOIDmode, | |
1177 | temp, | |
1178 | gen_rtx_CONST_DOUBLE (VOIDmode, const0_rtx, | |
1179 | INTVAL (op1) & 0xfffffc00, 0))); | |
1180 | } | |
1181 | else | |
1182 | { | |
1183 | emit_insn (gen_rtx_SET (VOIDmode, | |
1184 | temp, | |
1185 | GEN_INT (INTVAL (op1) & 0xfffffc00))); | |
1186 | } | |
1187 | emit_insn (gen_rtx_SET (VOIDmode, | |
1188 | op0, | |
1189 | gen_rtx_IOR (mode, | |
1190 | temp, | |
1191 | GEN_INT (INTVAL (op1) & 0x3ff)))); | |
1192 | } | |
1193 | else | |
1194 | { | |
1195 | /* A symbol, emit in the traditional way. */ | |
1196 | emit_insn (gen_rtx_SET (VOIDmode, | |
1197 | temp, | |
1198 | gen_rtx_HIGH (mode, | |
1199 | op1))); | |
1200 | emit_insn (gen_rtx_SET (VOIDmode, | |
1201 | op0, | |
1202 | gen_rtx_LO_SUM (mode, | |
1203 | temp, | |
1204 | op1))); | |
1205 | ||
1206 | } | |
e0d80184 DM |
1207 | } |
1208 | ||
1209 | \f | |
1210 | /* Sparc-v9 code-model support. */ | |
1211 | void | |
1212 | sparc_emit_set_symbolic_const64 (op0, op1, temp1) | |
1213 | rtx op0; | |
1214 | rtx op1; | |
1215 | rtx temp1; | |
1216 | { | |
1217 | switch (sparc_cmodel) | |
284d86e9 | 1218 | { |
e0d80184 DM |
1219 | case CM_MEDLOW: |
1220 | /* The range spanned by all instructions in the object is less | |
1221 | than 2^31 bytes (2GB) and the distance from any instruction | |
1222 | to the location of the label _GLOBAL_OFFSET_TABLE_ is less | |
1223 | than 2^31 bytes (2GB). | |
ab835497 | 1224 | |
e0d80184 DM |
1225 | The executable must be in the low 4TB of the virtual address |
1226 | space. | |
61a55e8b | 1227 | |
e0d80184 DM |
1228 | sethi %hi(symbol), %temp |
1229 | or %temp, %lo(symbol), %reg */ | |
9208e4b2 DM |
1230 | emit_insn (gen_rtx_SET (VOIDmode, temp1, gen_rtx_HIGH (DImode, op1))); |
1231 | emit_insn (gen_rtx_SET (VOIDmode, op0, gen_rtx_LO_SUM (DImode, temp1, op1))); | |
e0d80184 | 1232 | break; |
61a55e8b | 1233 | |
e0d80184 DM |
1234 | case CM_MEDMID: |
1235 | /* The range spanned by all instructions in the object is less | |
1236 | than 2^31 bytes (2GB) and the distance from any instruction | |
1237 | to the location of the label _GLOBAL_OFFSET_TABLE_ is less | |
1238 | than 2^31 bytes (2GB). | |
1239 | ||
1240 | The executable must be in the low 16TB of the virtual address | |
1241 | space. | |
1242 | ||
1243 | sethi %h44(symbol), %temp1 | |
1244 | or %temp1, %m44(symbol), %temp2 | |
1245 | sllx %temp2, 12, %temp3 | |
1246 | or %temp3, %l44(symbol), %reg */ | |
1247 | emit_insn (gen_seth44 (op0, op1)); | |
1248 | emit_insn (gen_setm44 (op0, op0, op1)); | |
9208e4b2 | 1249 | emit_insn (gen_rtx_SET (VOIDmode, temp1, |
e0d80184 DM |
1250 | gen_rtx_ASHIFT (DImode, op0, GEN_INT (12)))); |
1251 | emit_insn (gen_setl44 (op0, temp1, op1)); | |
1252 | break; | |
61a55e8b | 1253 | |
e0d80184 DM |
1254 | case CM_MEDANY: |
1255 | /* The range spanned by all instructions in the object is less | |
1256 | than 2^31 bytes (2GB) and the distance from any instruction | |
1257 | to the location of the label _GLOBAL_OFFSET_TABLE_ is less | |
1258 | than 2^31 bytes (2GB). | |
1259 | ||
1260 | The executable can be placed anywhere in the virtual address | |
1261 | space. | |
1262 | ||
1263 | sethi %hh(symbol), %temp1 | |
1264 | sethi %lm(symbol), %temp2 | |
1265 | or %temp1, %hm(symbol), %temp3 | |
1266 | or %temp2, %lo(symbol), %temp4 | |
1267 | sllx %temp3, 32, %temp5 | |
1268 | or %temp4, %temp5, %reg */ | |
1269 | ||
1270 | /* Getting this right wrt. reloading is really tricky. | |
5722d61c | 1271 | We _MUST_ have a separate temporary at this point, |
e0d80184 DM |
1272 | if we don't barf immediately instead of generating |
1273 | incorrect code. */ | |
1274 | if (temp1 == op0) | |
1275 | abort (); | |
61a55e8b | 1276 | |
e0d80184 DM |
1277 | emit_insn (gen_sethh (op0, op1)); |
1278 | emit_insn (gen_setlm (temp1, op1)); | |
1279 | emit_insn (gen_sethm (op0, op0, op1)); | |
9208e4b2 | 1280 | emit_insn (gen_rtx_SET (VOIDmode, op0, |
e0d80184 | 1281 | gen_rtx_ASHIFT (DImode, op0, GEN_INT (32)))); |
9208e4b2 | 1282 | emit_insn (gen_rtx_SET (VOIDmode, op0, |
e0d80184 DM |
1283 | gen_rtx_PLUS (DImode, op0, temp1))); |
1284 | emit_insn (gen_setlo (op0, op0, op1)); | |
1285 | break; | |
61a55e8b | 1286 | |
e0d80184 DM |
1287 | case CM_EMBMEDANY: |
1288 | /* Old old old backwards compatibility kruft here. | |
1289 | Essentially it is MEDLOW with a fixed 64-bit | |
1290 | virtual base added to all data segment addresses. | |
1291 | Text-segment stuff is computed like MEDANY, we can't | |
1292 | reuse the code above because the relocation knobs | |
1293 | look different. | |
1294 | ||
1295 | Data segment: sethi %hi(symbol), %temp1 | |
1296 | or %temp1, %lo(symbol), %temp2 | |
1297 | add %temp2, EMBMEDANY_BASE_REG, %reg | |
1298 | ||
1299 | Text segment: sethi %uhi(symbol), %temp1 | |
1300 | sethi %hi(symbol), %temp2 | |
1301 | or %temp1, %ulo(symbol), %temp3 | |
1302 | or %temp2, %lo(symbol), %temp4 | |
1303 | sllx %temp3, 32, %temp5 | |
1304 | or %temp4, %temp5, %reg */ | |
1305 | if (data_segment_operand (op1, GET_MODE (op1))) | |
1306 | { | |
1307 | emit_insn (gen_embmedany_sethi (temp1, op1)); | |
1308 | emit_insn (gen_embmedany_brsum (op0, temp1)); | |
1309 | emit_insn (gen_embmedany_losum (op0, op0, op1)); | |
1310 | } | |
1311 | else | |
1312 | { | |
1313 | /* Getting this right wrt. reloading is really tricky. | |
5722d61c | 1314 | We _MUST_ have a separate temporary at this point, |
f710f868 | 1315 | so we barf immediately instead of generating |
e0d80184 DM |
1316 | incorrect code. */ |
1317 | if (temp1 == op0) | |
1318 | abort (); | |
61a55e8b | 1319 | |
e0d80184 DM |
1320 | emit_insn (gen_embmedany_textuhi (op0, op1)); |
1321 | emit_insn (gen_embmedany_texthi (temp1, op1)); | |
1322 | emit_insn (gen_embmedany_textulo (op0, op0, op1)); | |
9208e4b2 | 1323 | emit_insn (gen_rtx_SET (VOIDmode, op0, |
e0d80184 | 1324 | gen_rtx_ASHIFT (DImode, op0, GEN_INT (32)))); |
9208e4b2 | 1325 | emit_insn (gen_rtx_SET (VOIDmode, op0, |
e0d80184 DM |
1326 | gen_rtx_PLUS (DImode, op0, temp1))); |
1327 | emit_insn (gen_embmedany_textlo (op0, op0, op1)); | |
1328 | } | |
1329 | break; | |
1330 | ||
1331 | default: | |
1332 | abort(); | |
1333 | } | |
1334 | } | |
1335 | ||
9208e4b2 DM |
1336 | /* These avoid problems when cross compiling. If we do not |
1337 | go through all this hair then the optimizer will see | |
1338 | invalid REG_EQUAL notes or in some cases none at all. */ | |
1339 | static void sparc_emit_set_safe_HIGH64 PROTO ((rtx, HOST_WIDE_INT)); | |
1340 | static rtx gen_safe_SET64 PROTO ((rtx, HOST_WIDE_INT)); | |
1341 | static rtx gen_safe_OR64 PROTO ((rtx, HOST_WIDE_INT)); | |
1342 | static rtx gen_safe_XOR64 PROTO ((rtx, HOST_WIDE_INT)); | |
1343 | ||
1344 | #if HOST_BITS_PER_WIDE_INT == 64 | |
1345 | #define GEN_HIGHINT64(__x) GEN_INT ((__x) & 0xfffffc00) | |
1346 | #define GEN_INT64(__x) GEN_INT (__x) | |
1347 | #else | |
1348 | #define GEN_HIGHINT64(__x) \ | |
1349 | gen_rtx_CONST_DOUBLE (VOIDmode, const0_rtx, \ | |
1350 | (__x) & 0xfffffc00, 0) | |
1351 | #define GEN_INT64(__x) \ | |
1352 | gen_rtx_CONST_DOUBLE (VOIDmode, const0_rtx, \ | |
1353 | (__x) & 0xffffffff, \ | |
1354 | ((__x) & 0x80000000 \ | |
1355 | ? 0xffffffff : 0)) | |
1356 | #endif | |
1357 | ||
1358 | /* The optimizer is not to assume anything about exactly | |
1359 | which bits are set for a HIGH, they are unspecified. | |
1360 | Unfortunately this leads to many missed optimizations | |
1361 | during CSE. We mask out the non-HIGH bits, and matches | |
1362 | a plain movdi, to alleviate this problem. */ | |
1363 | static void | |
1364 | sparc_emit_set_safe_HIGH64 (dest, val) | |
1365 | rtx dest; | |
1366 | HOST_WIDE_INT val; | |
1367 | { | |
1368 | emit_insn (gen_rtx_SET (VOIDmode, dest, GEN_HIGHINT64 (val))); | |
1369 | } | |
2a01c939 | 1370 | |
e0d80184 | 1371 | static rtx |
9208e4b2 DM |
1372 | gen_safe_SET64 (dest, val) |
1373 | rtx dest; | |
e0d80184 | 1374 | HOST_WIDE_INT val; |
61a55e8b | 1375 | { |
9208e4b2 DM |
1376 | return gen_rtx_SET (VOIDmode, dest, GEN_INT64 (val)); |
1377 | } | |
1378 | ||
1379 | static rtx | |
1380 | gen_safe_OR64 (src, val) | |
1381 | rtx src; | |
1382 | HOST_WIDE_INT val; | |
1383 | { | |
1384 | return gen_rtx_IOR (DImode, src, GEN_INT64 (val)); | |
1385 | } | |
1386 | ||
1387 | static rtx | |
1388 | gen_safe_XOR64 (src, val) | |
1389 | rtx src; | |
1390 | HOST_WIDE_INT val; | |
1391 | { | |
1392 | return gen_rtx_XOR (DImode, src, GEN_INT64 (val)); | |
e0d80184 | 1393 | } |
61a55e8b | 1394 | |
e0d80184 DM |
1395 | /* Worker routines for 64-bit constant formation on arch64. |
1396 | One of the key things to be doing in these emissions is | |
1397 | to create as many temp REGs as possible. This makes it | |
1398 | possible for half-built constants to be used later when | |
1399 | such values are similar to something required later on. | |
1400 | Without doing this, the optimizer cannot see such | |
1401 | opportunities. */ | |
2a01c939 DM |
1402 | |
1403 | static void sparc_emit_set_const64_quick1 | |
1404 | PROTO((rtx, rtx, unsigned HOST_WIDE_INT, int)); | |
1405 | ||
e0d80184 DM |
1406 | static void |
1407 | sparc_emit_set_const64_quick1 (op0, temp, low_bits, is_neg) | |
1408 | rtx op0; | |
1409 | rtx temp; | |
2a01c939 | 1410 | unsigned HOST_WIDE_INT low_bits; |
e0d80184 DM |
1411 | int is_neg; |
1412 | { | |
2a01c939 | 1413 | unsigned HOST_WIDE_INT high_bits; |
a9e27770 | 1414 | |
e0d80184 | 1415 | if (is_neg) |
2a01c939 | 1416 | high_bits = (~low_bits) & 0xffffffff; |
31bc9eba | 1417 | else |
e0d80184 | 1418 | high_bits = low_bits; |
31bc9eba | 1419 | |
9208e4b2 | 1420 | sparc_emit_set_safe_HIGH64 (temp, high_bits); |
e0d80184 | 1421 | if (!is_neg) |
5108f3e5 DM |
1422 | { |
1423 | emit_insn (gen_rtx_SET (VOIDmode, op0, | |
1424 | gen_safe_OR64 (temp, (high_bits & 0x3ff)))); | |
1425 | } | |
e0d80184 | 1426 | else |
5108f3e5 DM |
1427 | { |
1428 | /* If we are XOR'ing with -1, then we should emit a one's complement | |
1429 | instead. This way the combiner will notice logical operations | |
1430 | such as ANDN later on and substitute. */ | |
1431 | if ((low_bits & 0x3ff) == 0x3ff) | |
1432 | { | |
1433 | emit_insn (gen_rtx_SET (VOIDmode, op0, | |
1434 | gen_rtx_NOT (DImode, temp))); | |
1435 | } | |
1436 | else | |
1437 | { | |
1438 | emit_insn (gen_rtx_SET (VOIDmode, op0, | |
1439 | gen_safe_XOR64 (temp, | |
1440 | (-0x400 | (low_bits & 0x3ff))))); | |
1441 | } | |
1442 | } | |
e0d80184 | 1443 | } |
61a55e8b | 1444 | |
2a01c939 DM |
1445 | static void sparc_emit_set_const64_quick2 |
1446 | PROTO((rtx, rtx, unsigned HOST_WIDE_INT, | |
1447 | unsigned HOST_WIDE_INT, int)); | |
1448 | ||
e0d80184 DM |
1449 | static void |
1450 | sparc_emit_set_const64_quick2 (op0, temp, high_bits, low_immediate, shift_count) | |
1451 | rtx op0; | |
1452 | rtx temp; | |
2a01c939 DM |
1453 | unsigned HOST_WIDE_INT high_bits; |
1454 | unsigned HOST_WIDE_INT low_immediate; | |
e0d80184 DM |
1455 | int shift_count; |
1456 | { | |
1457 | rtx temp2 = op0; | |
61a55e8b | 1458 | |
e0d80184 DM |
1459 | if ((high_bits & 0xfffffc00) != 0) |
1460 | { | |
9208e4b2 | 1461 | sparc_emit_set_safe_HIGH64 (temp, high_bits); |
e0d80184 | 1462 | if ((high_bits & ~0xfffffc00) != 0) |
9208e4b2 DM |
1463 | emit_insn (gen_rtx_SET (VOIDmode, op0, |
1464 | gen_safe_OR64 (temp, (high_bits & 0x3ff)))); | |
61a55e8b | 1465 | else |
e0d80184 | 1466 | temp2 = temp; |
61a55e8b DE |
1467 | } |
1468 | else | |
1469 | { | |
f710f868 | 1470 | emit_insn (gen_safe_SET64 (temp, high_bits)); |
e0d80184 DM |
1471 | temp2 = temp; |
1472 | } | |
61a55e8b | 1473 | |
e0d80184 | 1474 | /* Now shift it up into place. */ |
9208e4b2 | 1475 | emit_insn (gen_rtx_SET (VOIDmode, op0, |
e0d80184 DM |
1476 | gen_rtx_ASHIFT (DImode, temp2, |
1477 | GEN_INT (shift_count)))); | |
61a55e8b | 1478 | |
e0d80184 DM |
1479 | /* If there is a low immediate part piece, finish up by |
1480 | putting that in as well. */ | |
1481 | if (low_immediate != 0) | |
9208e4b2 DM |
1482 | emit_insn (gen_rtx_SET (VOIDmode, op0, |
1483 | gen_safe_OR64 (op0, low_immediate))); | |
ab835497 RK |
1484 | } |
1485 | ||
2a01c939 DM |
1486 | static void sparc_emit_set_const64_longway |
1487 | PROTO((rtx, rtx, unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT)); | |
1488 | ||
e0d80184 DM |
1489 | /* Full 64-bit constant decomposition. Even though this is the |
1490 | 'worst' case, we still optimize a few things away. */ | |
1491 | static void | |
1492 | sparc_emit_set_const64_longway (op0, temp, high_bits, low_bits) | |
1493 | rtx op0; | |
1494 | rtx temp; | |
2a01c939 DM |
1495 | unsigned HOST_WIDE_INT high_bits; |
1496 | unsigned HOST_WIDE_INT low_bits; | |
ab835497 | 1497 | { |
e0d80184 | 1498 | rtx sub_temp; |
4bf7135b | 1499 | |
e0d80184 DM |
1500 | if (reload_in_progress || reload_completed) |
1501 | sub_temp = op0; | |
1502 | else | |
1503 | sub_temp = gen_reg_rtx (DImode); | |
1504 | ||
1505 | if ((high_bits & 0xfffffc00) != 0) | |
1506 | { | |
9208e4b2 | 1507 | sparc_emit_set_safe_HIGH64 (temp, high_bits); |
e0d80184 | 1508 | if ((high_bits & ~0xfffffc00) != 0) |
9208e4b2 | 1509 | emit_insn (gen_rtx_SET (VOIDmode, |
e0d80184 | 1510 | sub_temp, |
9208e4b2 | 1511 | gen_safe_OR64 (temp, (high_bits & 0x3ff)))); |
e0d80184 DM |
1512 | else |
1513 | sub_temp = temp; | |
1514 | } | |
1515 | else | |
ab835497 | 1516 | { |
f710f868 | 1517 | emit_insn (gen_safe_SET64 (temp, high_bits)); |
e0d80184 | 1518 | sub_temp = temp; |
ab835497 | 1519 | } |
4bf7135b | 1520 | |
e0d80184 | 1521 | if (!reload_in_progress && !reload_completed) |
284d86e9 | 1522 | { |
e0d80184 DM |
1523 | rtx temp2 = gen_reg_rtx (DImode); |
1524 | rtx temp3 = gen_reg_rtx (DImode); | |
1525 | rtx temp4 = gen_reg_rtx (DImode); | |
284d86e9 | 1526 | |
9208e4b2 | 1527 | emit_insn (gen_rtx_SET (VOIDmode, temp4, |
e0d80184 DM |
1528 | gen_rtx_ASHIFT (DImode, sub_temp, |
1529 | GEN_INT (32)))); | |
4bf7135b | 1530 | |
9208e4b2 | 1531 | sparc_emit_set_safe_HIGH64 (temp2, low_bits); |
e0d80184 | 1532 | if ((low_bits & ~0xfffffc00) != 0) |
f710f868 DM |
1533 | { |
1534 | emit_insn (gen_rtx_SET (VOIDmode, temp3, | |
1535 | gen_safe_OR64 (temp2, (low_bits & 0x3ff)))); | |
1536 | emit_insn (gen_rtx_SET (VOIDmode, op0, | |
1537 | gen_rtx_PLUS (DImode, temp4, temp3))); | |
1538 | } | |
1539 | else | |
1540 | { | |
1541 | emit_insn (gen_rtx_SET (VOIDmode, op0, | |
1542 | gen_rtx_PLUS (DImode, temp4, temp2))); | |
1543 | } | |
284d86e9 | 1544 | } |
e0d80184 DM |
1545 | else |
1546 | { | |
9208e4b2 DM |
1547 | rtx low1 = GEN_INT ((low_bits >> (32 - 12)) & 0xfff); |
1548 | rtx low2 = GEN_INT ((low_bits >> (32 - 12 - 12)) & 0xfff); | |
1549 | rtx low3 = GEN_INT ((low_bits >> (32 - 12 - 12 - 8)) & 0x0ff); | |
e0d80184 | 1550 | int to_shift = 12; |
284d86e9 | 1551 | |
e0d80184 DM |
1552 | /* We are in the middle of reload, so this is really |
1553 | painful. However we do still make an attempt to | |
5108f3e5 | 1554 | avoid emitting truly stupid code. */ |
e0d80184 DM |
1555 | if (low1 != const0_rtx) |
1556 | { | |
9208e4b2 | 1557 | emit_insn (gen_rtx_SET (VOIDmode, op0, |
e0d80184 | 1558 | gen_rtx_ASHIFT (DImode, sub_temp, |
2a01c939 | 1559 | GEN_INT (to_shift)))); |
9208e4b2 | 1560 | emit_insn (gen_rtx_SET (VOIDmode, op0, |
e0d80184 DM |
1561 | gen_rtx_IOR (DImode, op0, low1))); |
1562 | sub_temp = op0; | |
1563 | to_shift = 12; | |
1564 | } | |
1565 | else | |
1566 | { | |
1567 | to_shift += 12; | |
1568 | } | |
1569 | if (low2 != const0_rtx) | |
1570 | { | |
9208e4b2 | 1571 | emit_insn (gen_rtx_SET (VOIDmode, op0, |
e0d80184 DM |
1572 | gen_rtx_ASHIFT (DImode, sub_temp, |
1573 | GEN_INT (to_shift)))); | |
9208e4b2 | 1574 | emit_insn (gen_rtx_SET (VOIDmode, op0, |
e0d80184 DM |
1575 | gen_rtx_IOR (DImode, op0, low2))); |
1576 | sub_temp = op0; | |
1577 | to_shift = 8; | |
1578 | } | |
1579 | else | |
1580 | { | |
1581 | to_shift += 8; | |
1582 | } | |
9208e4b2 | 1583 | emit_insn (gen_rtx_SET (VOIDmode, op0, |
e0d80184 DM |
1584 | gen_rtx_ASHIFT (DImode, sub_temp, |
1585 | GEN_INT (to_shift)))); | |
1586 | if (low3 != const0_rtx) | |
9208e4b2 | 1587 | emit_insn (gen_rtx_SET (VOIDmode, op0, |
e0d80184 DM |
1588 | gen_rtx_IOR (DImode, op0, low3))); |
1589 | /* phew... */ | |
1590 | } | |
284d86e9 JC |
1591 | } |
1592 | ||
e0d80184 | 1593 | /* Analyze a 64-bit constant for certain properties. */ |
2a01c939 DM |
1594 | static void analyze_64bit_constant |
1595 | PROTO((unsigned HOST_WIDE_INT, | |
1596 | unsigned HOST_WIDE_INT, | |
1597 | int *, int *, int *)); | |
1598 | ||
e0d80184 DM |
1599 | static void |
1600 | analyze_64bit_constant (high_bits, low_bits, hbsp, lbsp, abbasp) | |
2a01c939 | 1601 | unsigned HOST_WIDE_INT high_bits, low_bits; |
e0d80184 | 1602 | int *hbsp, *lbsp, *abbasp; |
ab835497 | 1603 | { |
e0d80184 DM |
1604 | int lowest_bit_set, highest_bit_set, all_bits_between_are_set; |
1605 | int i; | |
ab835497 | 1606 | |
e0d80184 DM |
1607 | lowest_bit_set = highest_bit_set = -1; |
1608 | i = 0; | |
1609 | do | |
ab835497 | 1610 | { |
e0d80184 DM |
1611 | if ((lowest_bit_set == -1) |
1612 | && ((low_bits >> i) & 1)) | |
1613 | lowest_bit_set = i; | |
1614 | if ((highest_bit_set == -1) | |
1615 | && ((high_bits >> (32 - i - 1)) & 1)) | |
1616 | highest_bit_set = (64 - i - 1); | |
1617 | } | |
1618 | while (++i < 32 | |
1619 | && ((highest_bit_set == -1) | |
1620 | || (lowest_bit_set == -1))); | |
1621 | if (i == 32) | |
1622 | { | |
1623 | i = 0; | |
1624 | do | |
ab835497 | 1625 | { |
e0d80184 DM |
1626 | if ((lowest_bit_set == -1) |
1627 | && ((high_bits >> i) & 1)) | |
1628 | lowest_bit_set = i + 32; | |
1629 | if ((highest_bit_set == -1) | |
1630 | && ((low_bits >> (32 - i - 1)) & 1)) | |
1631 | highest_bit_set = 32 - i - 1; | |
ab835497 | 1632 | } |
e0d80184 DM |
1633 | while (++i < 32 |
1634 | && ((highest_bit_set == -1) | |
1635 | || (lowest_bit_set == -1))); | |
1636 | } | |
1637 | /* If there are no bits set this should have gone out | |
1638 | as one instruction! */ | |
1639 | if (lowest_bit_set == -1 | |
1640 | || highest_bit_set == -1) | |
9208e4b2 | 1641 | abort (); |
e0d80184 DM |
1642 | all_bits_between_are_set = 1; |
1643 | for (i = lowest_bit_set; i <= highest_bit_set; i++) | |
1644 | { | |
1645 | if (i < 32) | |
1646 | { | |
1647 | if ((low_bits & (1 << i)) != 0) | |
1648 | continue; | |
1649 | } | |
1650 | else | |
1651 | { | |
1652 | if ((high_bits & (1 << (i - 32))) != 0) | |
1653 | continue; | |
1654 | } | |
1655 | all_bits_between_are_set = 0; | |
1656 | break; | |
ab835497 | 1657 | } |
e0d80184 DM |
1658 | *hbsp = highest_bit_set; |
1659 | *lbsp = lowest_bit_set; | |
1660 | *abbasp = all_bits_between_are_set; | |
ab835497 | 1661 | } |
6a4bb1fa | 1662 | |
2a01c939 DM |
1663 | static int const64_is_2insns |
1664 | PROTO((unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT)); | |
1665 | ||
e0d80184 DM |
1666 | static int |
1667 | const64_is_2insns (high_bits, low_bits) | |
2a01c939 | 1668 | unsigned HOST_WIDE_INT high_bits, low_bits; |
e0d80184 DM |
1669 | { |
1670 | int highest_bit_set, lowest_bit_set, all_bits_between_are_set; | |
284d86e9 | 1671 | |
e0d80184 | 1672 | if (high_bits == 0 |
2a01c939 | 1673 | || high_bits == 0xffffffff) |
e0d80184 | 1674 | return 1; |
6a4bb1fa | 1675 | |
e0d80184 DM |
1676 | analyze_64bit_constant (high_bits, low_bits, |
1677 | &highest_bit_set, &lowest_bit_set, | |
1678 | &all_bits_between_are_set); | |
6a4bb1fa | 1679 | |
f710f868 DM |
1680 | if ((highest_bit_set == 63 |
1681 | || lowest_bit_set == 0) | |
e0d80184 DM |
1682 | && all_bits_between_are_set != 0) |
1683 | return 1; | |
6a4bb1fa | 1684 | |
9208e4b2 DM |
1685 | if ((highest_bit_set - lowest_bit_set) < 21) |
1686 | return 1; | |
1687 | ||
6a4bb1fa DE |
1688 | return 0; |
1689 | } | |
1690 | ||
2a01c939 DM |
1691 | static unsigned HOST_WIDE_INT create_simple_focus_bits |
1692 | PROTO((unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT, | |
ddf80874 | 1693 | int, int)); |
2a01c939 DM |
1694 | |
1695 | static unsigned HOST_WIDE_INT | |
ddf80874 | 1696 | create_simple_focus_bits (high_bits, low_bits, lowest_bit_set, shift) |
2a01c939 | 1697 | unsigned HOST_WIDE_INT high_bits, low_bits; |
ddf80874 | 1698 | int lowest_bit_set, shift; |
ab835497 | 1699 | { |
f710f868 | 1700 | HOST_WIDE_INT hi, lo; |
ab835497 | 1701 | |
e0d80184 DM |
1702 | if (lowest_bit_set < 32) |
1703 | { | |
1704 | lo = (low_bits >> lowest_bit_set) << shift; | |
1705 | hi = ((high_bits << (32 - lowest_bit_set)) << shift); | |
1706 | } | |
1707 | else | |
1708 | { | |
1709 | lo = 0; | |
1710 | hi = ((high_bits >> (lowest_bit_set - 32)) << shift); | |
1711 | } | |
1712 | if (hi & lo) | |
9208e4b2 | 1713 | abort (); |
e0d80184 DM |
1714 | return (hi | lo); |
1715 | } | |
ab835497 | 1716 | |
e0d80184 DM |
1717 | /* Here we are sure to be arch64 and this is an integer constant |
1718 | being loaded into a register. Emit the most efficient | |
1719 | insn sequence possible. Detection of all the 1-insn cases | |
1720 | has been done already. */ | |
1721 | void | |
1722 | sparc_emit_set_const64 (op0, op1) | |
1723 | rtx op0; | |
1724 | rtx op1; | |
1725 | { | |
2a01c939 | 1726 | unsigned HOST_WIDE_INT high_bits, low_bits; |
e0d80184 DM |
1727 | int lowest_bit_set, highest_bit_set; |
1728 | int all_bits_between_are_set; | |
e0d80184 | 1729 | rtx temp; |
ab835497 | 1730 | |
e0d80184 DM |
1731 | /* Sanity check that we know what we are working with. */ |
1732 | if (! TARGET_ARCH64 | |
1733 | || GET_CODE (op0) != REG | |
1734 | || (REGNO (op0) >= SPARC_FIRST_FP_REG | |
1735 | && REGNO (op0) <= SPARC_LAST_V9_FP_REG)) | |
9208e4b2 | 1736 | abort (); |
95726648 | 1737 | |
f710f868 DM |
1738 | if (reload_in_progress || reload_completed) |
1739 | temp = op0; | |
1740 | else | |
1741 | temp = gen_reg_rtx (DImode); | |
1742 | ||
e0d80184 DM |
1743 | if (GET_CODE (op1) != CONST_DOUBLE |
1744 | && GET_CODE (op1) != CONST_INT) | |
1745 | { | |
5f78aa30 JC |
1746 | sparc_emit_set_symbolic_const64 (op0, op1, temp); |
1747 | return; | |
e0d80184 | 1748 | } |
ab835497 | 1749 | |
e0d80184 DM |
1750 | if (GET_CODE (op1) == CONST_DOUBLE) |
1751 | { | |
1752 | #if HOST_BITS_PER_WIDE_INT == 64 | |
2a01c939 | 1753 | high_bits = (CONST_DOUBLE_LOW (op1) >> 32) & 0xffffffff; |
e0d80184 DM |
1754 | low_bits = CONST_DOUBLE_LOW (op1) & 0xffffffff; |
1755 | #else | |
1756 | high_bits = CONST_DOUBLE_HIGH (op1); | |
1757 | low_bits = CONST_DOUBLE_LOW (op1); | |
1758 | #endif | |
ab835497 | 1759 | } |
e0d80184 | 1760 | else |
ab835497 | 1761 | { |
e0d80184 | 1762 | #if HOST_BITS_PER_WIDE_INT == 64 |
2a01c939 | 1763 | high_bits = ((INTVAL (op1) >> 32) & 0xffffffff); |
e0d80184 DM |
1764 | low_bits = (INTVAL (op1) & 0xffffffff); |
1765 | #else | |
1766 | high_bits = ((INTVAL (op1) < 0) ? | |
1767 | 0xffffffff : | |
1768 | 0x00000000); | |
1769 | low_bits = INTVAL (op1); | |
1770 | #endif | |
1771 | } | |
ab835497 | 1772 | |
e0d80184 DM |
1773 | /* low_bits bits 0 --> 31 |
1774 | high_bits bits 32 --> 63 */ | |
ab835497 | 1775 | |
e0d80184 DM |
1776 | analyze_64bit_constant (high_bits, low_bits, |
1777 | &highest_bit_set, &lowest_bit_set, | |
1778 | &all_bits_between_are_set); | |
1779 | ||
1780 | /* First try for a 2-insn sequence. */ | |
1781 | ||
1782 | /* These situations are preferred because the optimizer can | |
1783 | * do more things with them: | |
1784 | * 1) mov -1, %reg | |
1785 | * sllx %reg, shift, %reg | |
1786 | * 2) mov -1, %reg | |
1787 | * srlx %reg, shift, %reg | |
1788 | * 3) mov some_small_const, %reg | |
1789 | * sllx %reg, shift, %reg | |
1790 | */ | |
1791 | if (((highest_bit_set == 63 | |
1792 | || lowest_bit_set == 0) | |
1793 | && all_bits_between_are_set != 0) | |
2a01c939 | 1794 | || ((highest_bit_set - lowest_bit_set) < 12)) |
e0d80184 | 1795 | { |
9208e4b2 | 1796 | HOST_WIDE_INT the_const = -1; |
e0d80184 DM |
1797 | int shift = lowest_bit_set; |
1798 | ||
f710f868 DM |
1799 | if ((highest_bit_set != 63 |
1800 | && lowest_bit_set != 0) | |
1801 | || all_bits_between_are_set == 0) | |
ab835497 | 1802 | { |
e0d80184 | 1803 | the_const = |
9208e4b2 | 1804 | create_simple_focus_bits (high_bits, low_bits, |
9208e4b2 | 1805 | lowest_bit_set, 0); |
ab835497 | 1806 | } |
e0d80184 | 1807 | else if (lowest_bit_set == 0) |
9208e4b2 | 1808 | shift = -(63 - highest_bit_set); |
e0d80184 | 1809 | |
f710f868 DM |
1810 | if (! SPARC_SIMM13_P (the_const)) |
1811 | abort (); | |
1812 | ||
9208e4b2 | 1813 | emit_insn (gen_safe_SET64 (temp, the_const)); |
e0d80184 | 1814 | if (shift > 0) |
9208e4b2 | 1815 | emit_insn (gen_rtx_SET (VOIDmode, |
e0d80184 DM |
1816 | op0, |
1817 | gen_rtx_ASHIFT (DImode, | |
1818 | temp, | |
1819 | GEN_INT (shift)))); | |
1820 | else if (shift < 0) | |
9208e4b2 | 1821 | emit_insn (gen_rtx_SET (VOIDmode, |
e0d80184 | 1822 | op0, |
9208e4b2 | 1823 | gen_rtx_LSHIFTRT (DImode, |
e0d80184 DM |
1824 | temp, |
1825 | GEN_INT (-shift)))); | |
ab835497 RK |
1826 | else |
1827 | abort (); | |
e0d80184 DM |
1828 | return; |
1829 | } | |
ab835497 | 1830 | |
e0d80184 DM |
1831 | /* Now a range of 22 or less bits set somewhere. |
1832 | * 1) sethi %hi(focus_bits), %reg | |
1833 | * sllx %reg, shift, %reg | |
1834 | * 2) sethi %hi(focus_bits), %reg | |
1835 | * srlx %reg, shift, %reg | |
1836 | */ | |
2a01c939 | 1837 | if ((highest_bit_set - lowest_bit_set) < 21) |
e0d80184 | 1838 | { |
2a01c939 | 1839 | unsigned HOST_WIDE_INT focus_bits = |
e0d80184 | 1840 | create_simple_focus_bits (high_bits, low_bits, |
ddf80874 | 1841 | lowest_bit_set, 10); |
f710f868 DM |
1842 | |
1843 | if (! SPARC_SETHI_P (focus_bits)) | |
1844 | abort (); | |
1845 | ||
9208e4b2 | 1846 | sparc_emit_set_safe_HIGH64 (temp, focus_bits); |
e0d80184 | 1847 | |
9208e4b2 | 1848 | /* If lowest_bit_set == 10 then a sethi alone could have done it. */ |
e0d80184 | 1849 | if (lowest_bit_set < 10) |
9208e4b2 | 1850 | emit_insn (gen_rtx_SET (VOIDmode, |
e0d80184 | 1851 | op0, |
9208e4b2 | 1852 | gen_rtx_LSHIFTRT (DImode, temp, |
e0d80184 | 1853 | GEN_INT (10 - lowest_bit_set)))); |
9208e4b2 DM |
1854 | else if (lowest_bit_set > 10) |
1855 | emit_insn (gen_rtx_SET (VOIDmode, | |
e0d80184 DM |
1856 | op0, |
1857 | gen_rtx_ASHIFT (DImode, temp, | |
1858 | GEN_INT (lowest_bit_set - 10)))); | |
1859 | else | |
9208e4b2 | 1860 | abort (); |
e0d80184 DM |
1861 | return; |
1862 | } | |
1863 | ||
1864 | /* 1) sethi %hi(low_bits), %reg | |
1865 | * or %reg, %lo(low_bits), %reg | |
1866 | * 2) sethi %hi(~low_bits), %reg | |
1867 | * xor %reg, %lo(-0x400 | (low_bits & 0x3ff)), %reg | |
1868 | */ | |
1869 | if (high_bits == 0 | |
2a01c939 | 1870 | || high_bits == 0xffffffff) |
5f78aa30 JC |
1871 | { |
1872 | sparc_emit_set_const64_quick1 (op0, temp, low_bits, | |
1873 | (high_bits == 0xffffffff)); | |
1874 | return; | |
1875 | } | |
e0d80184 | 1876 | |
f710f868 DM |
1877 | /* Now, try 3-insn sequences. */ |
1878 | ||
e0d80184 DM |
1879 | /* 1) sethi %hi(high_bits), %reg |
1880 | * or %reg, %lo(high_bits), %reg | |
1881 | * sllx %reg, 32, %reg | |
1882 | */ | |
f710f868 | 1883 | if (low_bits == 0) |
5f78aa30 | 1884 | { |
f710f868 | 1885 | sparc_emit_set_const64_quick2 (op0, temp, high_bits, 0, 32); |
5f78aa30 JC |
1886 | return; |
1887 | } | |
e0d80184 | 1888 | |
f710f868 DM |
1889 | /* We may be able to do something quick |
1890 | when the constant is negated, so try that. */ | |
e0d80184 DM |
1891 | if (const64_is_2insns ((~high_bits) & 0xffffffff, |
1892 | (~low_bits) & 0xfffffc00)) | |
1893 | { | |
5108f3e5 DM |
1894 | /* NOTE: The trailing bits get XOR'd so we need the |
1895 | non-negated bits, not the negated ones. */ | |
1896 | unsigned HOST_WIDE_INT trailing_bits = low_bits & 0x3ff; | |
e0d80184 DM |
1897 | |
1898 | if ((((~high_bits) & 0xffffffff) == 0 | |
1899 | && ((~low_bits) & 0x80000000) == 0) | |
1900 | || (((~high_bits) & 0xffffffff) == 0xffffffff | |
1901 | && ((~low_bits) & 0x80000000) != 0)) | |
ab835497 | 1902 | { |
5108f3e5 | 1903 | int fast_int = (~low_bits & 0xffffffff); |
e0d80184 | 1904 | |
5108f3e5 DM |
1905 | if ((SPARC_SETHI_P (fast_int) |
1906 | && (~high_bits & 0xffffffff) == 0) | |
1907 | || SPARC_SIMM13_P (fast_int)) | |
9208e4b2 | 1908 | emit_insn (gen_safe_SET64 (temp, fast_int)); |
ab835497 | 1909 | else |
9208e4b2 | 1910 | sparc_emit_set_const64 (temp, GEN_INT64 (fast_int)); |
ab835497 | 1911 | } |
e0d80184 DM |
1912 | else |
1913 | { | |
1914 | rtx negated_const; | |
1915 | #if HOST_BITS_PER_WIDE_INT == 64 | |
1916 | negated_const = GEN_INT (((~low_bits) & 0xfffffc00) | | |
1917 | (((HOST_WIDE_INT)((~high_bits) & 0xffffffff))<<32)); | |
1918 | #else | |
9208e4b2 | 1919 | negated_const = gen_rtx_CONST_DOUBLE (DImode, const0_rtx, |
e0d80184 DM |
1920 | (~low_bits) & 0xfffffc00, |
1921 | (~high_bits) & 0xffffffff); | |
1922 | #endif | |
1923 | sparc_emit_set_const64 (temp, negated_const); | |
1924 | } | |
5108f3e5 DM |
1925 | |
1926 | /* If we are XOR'ing with -1, then we should emit a one's complement | |
1927 | instead. This way the combiner will notice logical operations | |
1928 | such as ANDN later on and substitute. */ | |
1929 | if (trailing_bits == 0x3ff) | |
1930 | { | |
1931 | emit_insn (gen_rtx_SET (VOIDmode, op0, | |
1932 | gen_rtx_NOT (DImode, temp))); | |
1933 | } | |
1934 | else | |
1935 | { | |
1936 | emit_insn (gen_rtx_SET (VOIDmode, | |
1937 | op0, | |
1938 | gen_safe_XOR64 (temp, | |
1939 | (-0x400 | trailing_bits)))); | |
1940 | } | |
e0d80184 | 1941 | return; |
ab835497 | 1942 | } |
ab835497 | 1943 | |
e0d80184 DM |
1944 | /* 1) sethi %hi(xxx), %reg |
1945 | * or %reg, %lo(xxx), %reg | |
1946 | * sllx %reg, yyy, %reg | |
f710f868 DM |
1947 | * |
1948 | * ??? This is just a generalized version of the low_bits==0 | |
1949 | * thing above, FIXME... | |
e0d80184 DM |
1950 | */ |
1951 | if ((highest_bit_set - lowest_bit_set) < 32) | |
1952 | { | |
f710f868 DM |
1953 | unsigned HOST_WIDE_INT focus_bits = |
1954 | create_simple_focus_bits (high_bits, low_bits, | |
ddf80874 | 1955 | lowest_bit_set, 0); |
ab835497 | 1956 | |
e0d80184 DM |
1957 | /* We can't get here in this state. */ |
1958 | if (highest_bit_set < 32 | |
1959 | || lowest_bit_set >= 32) | |
9208e4b2 | 1960 | abort (); |
95726648 | 1961 | |
e0d80184 DM |
1962 | /* So what we know is that the set bits straddle the |
1963 | middle of the 64-bit word. */ | |
5f78aa30 JC |
1964 | sparc_emit_set_const64_quick2 (op0, temp, |
1965 | focus_bits, 0, | |
1966 | lowest_bit_set); | |
1967 | return; | |
e0d80184 | 1968 | } |
c85f7c16 | 1969 | |
f710f868 DM |
1970 | /* 1) sethi %hi(high_bits), %reg |
1971 | * or %reg, %lo(high_bits), %reg | |
1972 | * sllx %reg, 32, %reg | |
1973 | * or %reg, low_bits, %reg | |
1974 | */ | |
1975 | if (SPARC_SIMM13_P(low_bits) | |
1976 | && ((int)low_bits > 0)) | |
1977 | { | |
1978 | sparc_emit_set_const64_quick2 (op0, temp, high_bits, low_bits, 32); | |
1979 | return; | |
1980 | } | |
1981 | ||
e0d80184 DM |
1982 | /* The easiest way when all else fails, is full decomposition. */ |
1983 | #if 0 | |
1984 | printf ("sparc_emit_set_const64: Hard constant [%08lx%08lx] neg[%08lx%08lx]\n", | |
1985 | high_bits, low_bits, ~high_bits, ~low_bits); | |
1986 | #endif | |
1987 | sparc_emit_set_const64_longway (op0, temp, high_bits, low_bits); | |
c85f7c16 JL |
1988 | } |
1989 | ||
e0d80184 DM |
1990 | /* X and Y are two things to compare using CODE. Emit the compare insn and |
1991 | return the rtx for the cc reg in the proper mode. */ | |
c85f7c16 | 1992 | |
e0d80184 DM |
1993 | rtx |
1994 | gen_compare_reg (code, x, y) | |
1995 | enum rtx_code code; | |
1996 | rtx x, y; | |
c85f7c16 | 1997 | { |
e0d80184 DM |
1998 | enum machine_mode mode = SELECT_CC_MODE (code, x, y); |
1999 | rtx cc_reg; | |
c85f7c16 | 2000 | |
e0d80184 DM |
2001 | /* ??? We don't have movcc patterns so we cannot generate pseudo regs for the |
2002 | fcc regs (cse can't tell they're really call clobbered regs and will | |
2003 | remove a duplicate comparison even if there is an intervening function | |
2004 | call - it will then try to reload the cc reg via an int reg which is why | |
2005 | we need the movcc patterns). It is possible to provide the movcc | |
2006 | patterns by using the ldxfsr/stxfsr v9 insns. I tried it: you need two | |
2007 | registers (say %g1,%g5) and it takes about 6 insns. A better fix would be | |
2008 | to tell cse that CCFPE mode registers (even pseudos) are call | |
2009 | clobbered. */ | |
c85f7c16 | 2010 | |
e0d80184 DM |
2011 | /* ??? This is an experiment. Rather than making changes to cse which may |
2012 | or may not be easy/clean, we do our own cse. This is possible because | |
2013 | we will generate hard registers. Cse knows they're call clobbered (it | |
2014 | doesn't know the same thing about pseudos). If we guess wrong, no big | |
2015 | deal, but if we win, great! */ | |
c85f7c16 | 2016 | |
e0d80184 DM |
2017 | if (TARGET_V9 && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) |
2018 | #if 1 /* experiment */ | |
284d86e9 | 2019 | { |
e0d80184 DM |
2020 | int reg; |
2021 | /* We cycle through the registers to ensure they're all exercised. */ | |
2022 | static int next_fcc_reg = 0; | |
2023 | /* Previous x,y for each fcc reg. */ | |
2024 | static rtx prev_args[4][2]; | |
284d86e9 | 2025 | |
e0d80184 DM |
2026 | /* Scan prev_args for x,y. */ |
2027 | for (reg = 0; reg < 4; reg++) | |
2028 | if (prev_args[reg][0] == x && prev_args[reg][1] == y) | |
2029 | break; | |
2030 | if (reg == 4) | |
2031 | { | |
2032 | reg = next_fcc_reg; | |
2033 | prev_args[reg][0] = x; | |
2034 | prev_args[reg][1] = y; | |
2035 | next_fcc_reg = (next_fcc_reg + 1) & 3; | |
2036 | } | |
2037 | cc_reg = gen_rtx_REG (mode, reg + SPARC_FIRST_V9_FCC_REG); | |
284d86e9 | 2038 | } |
e0d80184 DM |
2039 | #else |
2040 | cc_reg = gen_reg_rtx (mode); | |
2041 | #endif /* ! experiment */ | |
2042 | else if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) | |
2043 | cc_reg = gen_rtx_REG (mode, SPARC_FCC_REG); | |
2044 | else | |
2045 | cc_reg = gen_rtx_REG (mode, SPARC_ICC_REG); | |
284d86e9 | 2046 | |
e0d80184 DM |
2047 | emit_insn (gen_rtx_SET (VOIDmode, cc_reg, |
2048 | gen_rtx_COMPARE (mode, x, y))); | |
c85f7c16 | 2049 | |
e0d80184 DM |
2050 | return cc_reg; |
2051 | } | |
c85f7c16 | 2052 | |
e0d80184 DM |
2053 | /* This function is used for v9 only. |
2054 | CODE is the code for an Scc's comparison. | |
2055 | OPERANDS[0] is the target of the Scc insn. | |
2056 | OPERANDS[1] is the value we compare against const0_rtx (which hasn't | |
2057 | been generated yet). | |
c85f7c16 | 2058 | |
e0d80184 | 2059 | This function is needed to turn |
ab835497 | 2060 | |
e0d80184 DM |
2061 | (set (reg:SI 110) |
2062 | (gt (reg:CCX 100 %icc) | |
2063 | (const_int 0))) | |
2064 | into | |
2065 | (set (reg:SI 110) | |
2066 | (gt:DI (reg:CCX 100 %icc) | |
2067 | (const_int 0))) | |
2068 | ||
2069 | IE: The instruction recognizer needs to see the mode of the comparison to | |
2070 | find the right instruction. We could use "gt:DI" right in the | |
2071 | define_expand, but leaving it out allows us to handle DI, SI, etc. | |
ab835497 | 2072 | |
e0d80184 DM |
2073 | We refer to the global sparc compare operands sparc_compare_op0 and |
2074 | sparc_compare_op1. */ | |
ab835497 RK |
2075 | |
2076 | int | |
e0d80184 DM |
2077 | gen_v9_scc (compare_code, operands) |
2078 | enum rtx_code compare_code; | |
2079 | register rtx *operands; | |
ab835497 | 2080 | { |
e0d80184 | 2081 | rtx temp, op0, op1; |
ab835497 | 2082 | |
e0d80184 DM |
2083 | if (! TARGET_ARCH64 |
2084 | && (GET_MODE (sparc_compare_op0) == DImode | |
2085 | || GET_MODE (operands[0]) == DImode)) | |
2086 | return 0; | |
7e2feebf | 2087 | |
e0d80184 DM |
2088 | /* Handle the case where operands[0] == sparc_compare_op0. |
2089 | We "early clobber" the result. */ | |
2090 | if (REGNO (operands[0]) == REGNO (sparc_compare_op0)) | |
ab835497 | 2091 | { |
e0d80184 DM |
2092 | op0 = gen_reg_rtx (GET_MODE (sparc_compare_op0)); |
2093 | emit_move_insn (op0, sparc_compare_op0); | |
ab835497 | 2094 | } |
e0d80184 DM |
2095 | else |
2096 | op0 = sparc_compare_op0; | |
2097 | /* For consistency in the following. */ | |
2098 | op1 = sparc_compare_op1; | |
2099 | ||
2100 | /* Try to use the movrCC insns. */ | |
2101 | if (TARGET_ARCH64 | |
2102 | && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT | |
2103 | && op1 == const0_rtx | |
2104 | && v9_regcmp_p (compare_code)) | |
ab835497 | 2105 | { |
e0d80184 DM |
2106 | /* Special case for op0 != 0. This can be done with one instruction if |
2107 | operands[0] == sparc_compare_op0. We don't assume they are equal | |
2108 | now though. */ | |
2109 | ||
2110 | if (compare_code == NE | |
2111 | && GET_MODE (operands[0]) == DImode | |
2112 | && GET_MODE (op0) == DImode) | |
ab835497 | 2113 | { |
e0d80184 DM |
2114 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], op0)); |
2115 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], | |
2116 | gen_rtx_IF_THEN_ELSE (DImode, | |
2117 | gen_rtx_fmt_ee (compare_code, DImode, | |
2118 | op0, const0_rtx), | |
2119 | const1_rtx, | |
2120 | operands[0]))); | |
ab835497 RK |
2121 | return 1; |
2122 | } | |
e0d80184 DM |
2123 | |
2124 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], const0_rtx)); | |
2125 | if (GET_MODE (op0) != DImode) | |
ab835497 | 2126 | { |
e0d80184 DM |
2127 | temp = gen_reg_rtx (DImode); |
2128 | convert_move (temp, op0, 0); | |
ab835497 | 2129 | } |
e0d80184 DM |
2130 | else |
2131 | temp = op0; | |
2132 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], | |
2133 | gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]), | |
2134 | gen_rtx_fmt_ee (compare_code, DImode, | |
2135 | temp, const0_rtx), | |
2136 | const1_rtx, | |
2137 | operands[0]))); | |
95726648 DE |
2138 | return 1; |
2139 | } | |
e0d80184 | 2140 | else |
ab835497 | 2141 | { |
e0d80184 | 2142 | operands[1] = gen_compare_reg (compare_code, op0, op1); |
ab835497 | 2143 | |
e0d80184 | 2144 | switch (GET_MODE (operands[1])) |
ab835497 | 2145 | { |
e0d80184 DM |
2146 | case CCmode : |
2147 | case CCXmode : | |
2148 | case CCFPEmode : | |
2149 | case CCFPmode : | |
2150 | break; | |
2151 | default : | |
2152 | abort (); | |
ab835497 | 2153 | } |
e0d80184 DM |
2154 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], const0_rtx)); |
2155 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], | |
2156 | gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]), | |
2157 | gen_rtx_fmt_ee (compare_code, | |
2158 | GET_MODE (operands[1]), | |
2159 | operands[1], const0_rtx), | |
2160 | const1_rtx, operands[0]))); | |
2161 | return 1; | |
ab835497 | 2162 | } |
ab835497 | 2163 | } |
4fb4e4b8 | 2164 | |
e0d80184 DM |
2165 | /* Emit a conditional jump insn for the v9 architecture using comparison code |
2166 | CODE and jump target LABEL. | |
2167 | This function exists to take advantage of the v9 brxx insns. */ | |
ab835497 | 2168 | |
e0d80184 DM |
2169 | void |
2170 | emit_v9_brxx_insn (code, op0, label) | |
2171 | enum rtx_code code; | |
2172 | rtx op0, label; | |
ab835497 | 2173 | { |
e0d80184 DM |
2174 | emit_jump_insn (gen_rtx_SET (VOIDmode, |
2175 | pc_rtx, | |
2176 | gen_rtx_IF_THEN_ELSE (VOIDmode, | |
2177 | gen_rtx_fmt_ee (code, GET_MODE (op0), | |
2178 | op0, const0_rtx), | |
2179 | gen_rtx_LABEL_REF (VOIDmode, label), | |
2180 | pc_rtx))); | |
2181 | } | |
2182 | \f | |
2183 | /* Return nonzero if a return peephole merging return with | |
2184 | setting of output register is ok. */ | |
2185 | int | |
2186 | leaf_return_peephole_ok () | |
2187 | { | |
2188 | return (actual_fsize == 0); | |
2189 | } | |
284d86e9 | 2190 | |
e0d80184 DM |
2191 | /* Return nonzero if TRIAL can go into the function epilogue's |
2192 | delay slot. SLOT is the slot we are trying to fill. */ | |
ab835497 | 2193 | |
e0d80184 DM |
2194 | int |
2195 | eligible_for_epilogue_delay (trial, slot) | |
2196 | rtx trial; | |
2197 | int slot; | |
2198 | { | |
2199 | rtx pat, src; | |
4fb4e4b8 | 2200 | |
e0d80184 DM |
2201 | if (slot >= 1) |
2202 | return 0; | |
4fb4e4b8 | 2203 | |
e0d80184 DM |
2204 | if (GET_CODE (trial) != INSN || GET_CODE (PATTERN (trial)) != SET) |
2205 | return 0; | |
4fb4e4b8 | 2206 | |
e0d80184 DM |
2207 | if (get_attr_length (trial) != 1) |
2208 | return 0; | |
4fb4e4b8 | 2209 | |
e0d80184 DM |
2210 | /* If %g0 is live, there are lots of things we can't handle. |
2211 | Rather than trying to find them all now, let's punt and only | |
2212 | optimize things as necessary. */ | |
2213 | if (TARGET_LIVE_G0) | |
2214 | return 0; | |
e48addee JJ |
2215 | |
2216 | /* If there are any call-saved registers, we should scan TRIAL if it | |
2217 | does not reference them. For now just make it easy. */ | |
2218 | if (num_gfregs) | |
2219 | return 0; | |
4fb4e4b8 | 2220 | |
e0d80184 DM |
2221 | /* In the case of a true leaf function, anything can go into the delay slot. |
2222 | A delay slot only exists however if the frame size is zero, otherwise | |
2223 | we will put an insn to adjust the stack after the return. */ | |
54ff41b7 | 2224 | if (current_function_uses_only_leaf_regs) |
4fb4e4b8 | 2225 | { |
e0d80184 DM |
2226 | if (leaf_return_peephole_ok ()) |
2227 | return ((get_attr_in_uncond_branch_delay (trial) | |
2228 | == IN_BRANCH_DELAY_TRUE)); | |
2229 | return 0; | |
4fb4e4b8 | 2230 | } |
4fb4e4b8 | 2231 | |
e0d80184 DM |
2232 | /* If only trivial `restore' insns work, nothing can go in the |
2233 | delay slot. */ | |
2234 | else if (TARGET_BROKEN_SAVERESTORE) | |
2235 | return 0; | |
795068a4 | 2236 | |
e0d80184 | 2237 | pat = PATTERN (trial); |
795068a4 | 2238 | |
e0d80184 | 2239 | /* Otherwise, only operations which can be done in tandem with |
e48addee | 2240 | a `restore' or `return' insn can go into the delay slot. */ |
e0d80184 DM |
2241 | if (GET_CODE (SET_DEST (pat)) != REG |
2242 | || REGNO (SET_DEST (pat)) >= 32 | |
2243 | || REGNO (SET_DEST (pat)) < 24) | |
2244 | return 0; | |
795068a4 | 2245 | |
e0d80184 DM |
2246 | /* The set of insns matched here must agree precisely with the set of |
2247 | patterns paired with a RETURN in sparc.md. */ | |
795068a4 | 2248 | |
e0d80184 | 2249 | src = SET_SRC (pat); |
795068a4 | 2250 | |
3c6088d2 | 2251 | /* This matches "*return_[qhs]i" or even "*return_di" on TARGET_ARCH64. */ |
e0d80184 | 2252 | if (arith_operand (src, GET_MODE (src))) |
3c6088d2 JJ |
2253 | { |
2254 | if (TARGET_ARCH64) | |
2255 | return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode); | |
2256 | else | |
2257 | return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (SImode); | |
2258 | } | |
e48addee | 2259 | |
e0d80184 DM |
2260 | /* This matches "*return_di". */ |
2261 | else if (arith_double_operand (src, GET_MODE (src))) | |
2262 | return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode); | |
795068a4 | 2263 | |
e0d80184 DM |
2264 | /* This matches "*return_sf_no_fpu". */ |
2265 | else if (! TARGET_FPU && restore_operand (SET_DEST (pat), SFmode) | |
2266 | && register_operand (src, SFmode)) | |
2267 | return 1; | |
f5da225e | 2268 | |
e48addee JJ |
2269 | /* If we have return instruction, anything that does not use |
2270 | local or output registers and can go into a delay slot wins. */ | |
2271 | else if (TARGET_V9 && ! epilogue_renumber (&pat, 1) | |
2272 | && (get_attr_in_uncond_branch_delay (trial) == IN_BRANCH_DELAY_TRUE)) | |
2273 | return 1; | |
2274 | ||
e0d80184 DM |
2275 | /* This matches "*return_addsi". */ |
2276 | else if (GET_CODE (src) == PLUS | |
2277 | && arith_operand (XEXP (src, 0), SImode) | |
2278 | && arith_operand (XEXP (src, 1), SImode) | |
2279 | && (register_operand (XEXP (src, 0), SImode) | |
2280 | || register_operand (XEXP (src, 1), SImode))) | |
2281 | return 1; | |
2282 | ||
2283 | /* This matches "*return_adddi". */ | |
2284 | else if (GET_CODE (src) == PLUS | |
2285 | && arith_double_operand (XEXP (src, 0), DImode) | |
2286 | && arith_double_operand (XEXP (src, 1), DImode) | |
2287 | && (register_operand (XEXP (src, 0), DImode) | |
2288 | || register_operand (XEXP (src, 1), DImode))) | |
795068a4 | 2289 | return 1; |
795068a4 | 2290 | |
e48addee JJ |
2291 | /* This can match "*return_losum_[sd]i". |
2292 | Catch only some cases, so that return_losum* don't have | |
2293 | to be too big. */ | |
2294 | else if (GET_CODE (src) == LO_SUM | |
2295 | && ! TARGET_CM_MEDMID | |
2296 | && ((register_operand (XEXP (src, 0), SImode) | |
2297 | && immediate_operand (XEXP (src, 1), SImode)) | |
2298 | || (TARGET_ARCH64 | |
2299 | && register_operand (XEXP (src, 0), DImode) | |
2300 | && immediate_operand (XEXP (src, 1), DImode)))) | |
2301 | return 1; | |
2302 | ||
2303 | /* sll{,x} reg,1,reg2 is add reg,reg,reg2 as well. */ | |
2304 | else if (GET_CODE (src) == ASHIFT | |
2305 | && (register_operand (XEXP (src, 0), SImode) | |
2306 | || register_operand (XEXP (src, 0), DImode)) | |
2307 | && XEXP (src, 1) == const1_rtx) | |
2308 | return 1; | |
2309 | ||
795068a4 JW |
2310 | return 0; |
2311 | } | |
2312 | ||
e0d80184 DM |
2313 | static int |
2314 | check_return_regs (x) | |
2315 | rtx x; | |
ab835497 | 2316 | { |
e0d80184 DM |
2317 | switch (GET_CODE (x)) |
2318 | { | |
2319 | case REG: | |
2320 | return IN_OR_GLOBAL_P (x); | |
ab835497 | 2321 | |
e0d80184 DM |
2322 | case CONST_INT: |
2323 | case CONST_DOUBLE: | |
2324 | case CONST: | |
2325 | case SYMBOL_REF: | |
2326 | case LABEL_REF: | |
2327 | return 1; | |
ab835497 | 2328 | |
e0d80184 DM |
2329 | case SET: |
2330 | case IOR: | |
2331 | case AND: | |
2332 | case XOR: | |
2333 | case PLUS: | |
2334 | case MINUS: | |
2335 | if (check_return_regs (XEXP (x, 1)) == 0) | |
2336 | return 0; | |
2337 | case NOT: | |
2338 | case NEG: | |
2339 | case MEM: | |
2340 | return check_return_regs (XEXP (x, 0)); | |
2341 | ||
2342 | default: | |
2343 | return 0; | |
2344 | } | |
ab835497 | 2345 | |
e0d80184 | 2346 | } |
ab835497 | 2347 | |
e0d80184 DM |
2348 | /* Return 1 if TRIAL references only in and global registers. */ |
2349 | int | |
2350 | eligible_for_return_delay (trial) | |
2351 | rtx trial; | |
2352 | { | |
2353 | if (GET_CODE (PATTERN (trial)) != SET) | |
2354 | return 0; | |
ab835497 | 2355 | |
e0d80184 DM |
2356 | return check_return_regs (PATTERN (trial)); |
2357 | } | |
ab835497 | 2358 | |
e0d80184 DM |
2359 | int |
2360 | short_branch (uid1, uid2) | |
2361 | int uid1, uid2; | |
2362 | { | |
2363 | unsigned int delta = insn_addresses[uid1] - insn_addresses[uid2]; | |
2364 | if (delta + 1024 < 2048) | |
2365 | return 1; | |
2366 | /* warning ("long branch, distance %d", delta); */ | |
2367 | return 0; | |
2368 | } | |
ab835497 | 2369 | |
e0d80184 DM |
2370 | /* Return non-zero if REG is not used after INSN. |
2371 | We assume REG is a reload reg, and therefore does | |
2372 | not live past labels or calls or jumps. */ | |
2373 | int | |
2374 | reg_unused_after (reg, insn) | |
2375 | rtx reg; | |
2376 | rtx insn; | |
2377 | { | |
2378 | enum rtx_code code, prev_code = UNKNOWN; | |
ab835497 | 2379 | |
e0d80184 | 2380 | while ((insn = NEXT_INSN (insn))) |
61a55e8b | 2381 | { |
e0d80184 DM |
2382 | if (prev_code == CALL_INSN && call_used_regs[REGNO (reg)]) |
2383 | return 1; | |
ab835497 | 2384 | |
e0d80184 DM |
2385 | code = GET_CODE (insn); |
2386 | if (GET_CODE (insn) == CODE_LABEL) | |
2387 | return 1; | |
bc961ed7 | 2388 | |
e0d80184 | 2389 | if (GET_RTX_CLASS (code) == 'i') |
61a55e8b | 2390 | { |
e0d80184 DM |
2391 | rtx set = single_set (insn); |
2392 | int in_src = set && reg_overlap_mentioned_p (reg, SET_SRC (set)); | |
2393 | if (set && in_src) | |
2394 | return 0; | |
2395 | if (set && reg_overlap_mentioned_p (reg, SET_DEST (set))) | |
2396 | return 1; | |
2397 | if (set == 0 && reg_overlap_mentioned_p (reg, PATTERN (insn))) | |
2398 | return 0; | |
61a55e8b | 2399 | } |
e0d80184 | 2400 | prev_code = code; |
61a55e8b | 2401 | } |
e0d80184 DM |
2402 | return 1; |
2403 | } | |
2404 | \f | |
2405 | /* The table we use to reference PIC data. */ | |
2406 | static rtx global_offset_table; | |
bc961ed7 | 2407 | |
e0d80184 DM |
2408 | /* The function we use to get at it. */ |
2409 | static rtx get_pc_symbol; | |
2410 | static char get_pc_symbol_name[256]; | |
ab835497 | 2411 | |
e0d80184 | 2412 | /* Ensure that we are not using patterns that are not OK with PIC. */ |
795068a4 | 2413 | |
e0d80184 DM |
2414 | int |
2415 | check_pic (i) | |
2416 | int i; | |
2417 | { | |
2418 | switch (flag_pic) | |
ab835497 | 2419 | { |
e0d80184 | 2420 | case 1: |
1ccbefce RH |
2421 | if (GET_CODE (recog_data.operand[i]) == SYMBOL_REF |
2422 | || (GET_CODE (recog_data.operand[i]) == CONST | |
2423 | && ! (GET_CODE (XEXP (recog_data.operand[i], 0)) == MINUS | |
2424 | && (XEXP (XEXP (recog_data.operand[i], 0), 0) | |
e0d80184 | 2425 | == global_offset_table) |
1ccbefce | 2426 | && (GET_CODE (XEXP (XEXP (recog_data.operand[i], 0), 1)) |
e0d80184 DM |
2427 | == CONST)))) |
2428 | abort (); | |
2429 | case 2: | |
2430 | default: | |
2431 | return 1; | |
ab835497 | 2432 | } |
ab835497 | 2433 | } |
795068a4 | 2434 | |
e0d80184 DM |
2435 | /* Return true if X is an address which needs a temporary register when |
2436 | reloaded while generating PIC code. */ | |
795068a4 | 2437 | |
e0d80184 DM |
2438 | int |
2439 | pic_address_needs_scratch (x) | |
2440 | rtx x; | |
795068a4 | 2441 | { |
e0d80184 DM |
2442 | /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */ |
2443 | if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS | |
2444 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF | |
2445 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT | |
2446 | && ! SMALL_INT (XEXP (XEXP (x, 0), 1))) | |
2447 | return 1; | |
795068a4 | 2448 | |
e0d80184 DM |
2449 | return 0; |
2450 | } | |
795068a4 | 2451 | |
e0d80184 DM |
2452 | /* Legitimize PIC addresses. If the address is already position-independent, |
2453 | we return ORIG. Newly generated position-independent addresses go into a | |
2454 | reg. This is REG if non zero, otherwise we allocate register(s) as | |
2455 | necessary. */ | |
795068a4 | 2456 | |
e0d80184 DM |
2457 | rtx |
2458 | legitimize_pic_address (orig, mode, reg) | |
2459 | rtx orig; | |
2460 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
2461 | rtx reg; | |
2462 | { | |
2463 | if (GET_CODE (orig) == SYMBOL_REF) | |
82d6b402 | 2464 | { |
e0d80184 DM |
2465 | rtx pic_ref, address; |
2466 | rtx insn; | |
82d6b402 | 2467 | |
e0d80184 | 2468 | if (reg == 0) |
82d6b402 | 2469 | { |
e0d80184 DM |
2470 | if (reload_in_progress || reload_completed) |
2471 | abort (); | |
2472 | else | |
2473 | reg = gen_reg_rtx (Pmode); | |
82d6b402 | 2474 | } |
795068a4 | 2475 | |
e0d80184 | 2476 | if (flag_pic == 2) |
4fb4e4b8 | 2477 | { |
e0d80184 DM |
2478 | /* If not during reload, allocate another temp reg here for loading |
2479 | in the address, so that these instructions can be optimized | |
2480 | properly. */ | |
2481 | rtx temp_reg = ((reload_in_progress || reload_completed) | |
2482 | ? reg : gen_reg_rtx (Pmode)); | |
2483 | ||
2484 | /* Must put the SYMBOL_REF inside an UNSPEC here so that cse | |
2485 | won't get confused into thinking that these two instructions | |
2486 | are loading in the true address of the symbol. If in the | |
2487 | future a PIC rtx exists, that should be used instead. */ | |
be3f1ff5 DM |
2488 | if (Pmode == SImode) |
2489 | { | |
2490 | emit_insn (gen_movsi_high_pic (temp_reg, orig)); | |
2491 | emit_insn (gen_movsi_lo_sum_pic (temp_reg, temp_reg, orig)); | |
2492 | } | |
2493 | else | |
2494 | { | |
2495 | emit_insn (gen_movdi_high_pic (temp_reg, orig)); | |
2496 | emit_insn (gen_movdi_lo_sum_pic (temp_reg, temp_reg, orig)); | |
2497 | } | |
e0d80184 | 2498 | address = temp_reg; |
4fb4e4b8 DE |
2499 | } |
2500 | else | |
e0d80184 DM |
2501 | address = orig; |
2502 | ||
2503 | pic_ref = gen_rtx_MEM (Pmode, | |
2504 | gen_rtx_PLUS (Pmode, | |
2505 | pic_offset_table_rtx, address)); | |
2506 | current_function_uses_pic_offset_table = 1; | |
2507 | RTX_UNCHANGING_P (pic_ref) = 1; | |
2508 | insn = emit_move_insn (reg, pic_ref); | |
2509 | /* Put a REG_EQUAL note on this insn, so that it can be optimized | |
2510 | by loop. */ | |
2511 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, orig, | |
2512 | REG_NOTES (insn)); | |
2513 | return reg; | |
795068a4 | 2514 | } |
e0d80184 | 2515 | else if (GET_CODE (orig) == CONST) |
795068a4 | 2516 | { |
e0d80184 | 2517 | rtx base, offset; |
795068a4 | 2518 | |
e0d80184 DM |
2519 | if (GET_CODE (XEXP (orig, 0)) == PLUS |
2520 | && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx) | |
2521 | return orig; | |
82d6b402 | 2522 | |
e0d80184 | 2523 | if (reg == 0) |
4fb4e4b8 | 2524 | { |
e0d80184 DM |
2525 | if (reload_in_progress || reload_completed) |
2526 | abort (); | |
2527 | else | |
2528 | reg = gen_reg_rtx (Pmode); | |
4fb4e4b8 | 2529 | } |
e0d80184 DM |
2530 | |
2531 | if (GET_CODE (XEXP (orig, 0)) == PLUS) | |
4fb4e4b8 | 2532 | { |
e0d80184 DM |
2533 | base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg); |
2534 | offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode, | |
2535 | base == reg ? 0 : reg); | |
4fb4e4b8 DE |
2536 | } |
2537 | else | |
61a66555 JW |
2538 | abort (); |
2539 | ||
e0d80184 DM |
2540 | if (GET_CODE (offset) == CONST_INT) |
2541 | { | |
2542 | if (SMALL_INT (offset)) | |
2543 | return plus_constant_for_output (base, INTVAL (offset)); | |
2544 | else if (! reload_in_progress && ! reload_completed) | |
2545 | offset = force_reg (Pmode, offset); | |
2546 | else | |
2547 | /* If we reach here, then something is seriously wrong. */ | |
2548 | abort (); | |
2549 | } | |
2550 | return gen_rtx_PLUS (Pmode, base, offset); | |
795068a4 | 2551 | } |
e0d80184 DM |
2552 | else if (GET_CODE (orig) == LABEL_REF) |
2553 | /* ??? Why do we do this? */ | |
2554 | /* Now movsi_pic_label_ref uses it, but we ought to be checking that | |
2555 | the register is live instead, in case it is eliminated. */ | |
2556 | current_function_uses_pic_offset_table = 1; | |
795068a4 | 2557 | |
e0d80184 DM |
2558 | return orig; |
2559 | } | |
795068a4 | 2560 | |
e0d80184 DM |
2561 | /* Return the RTX for insns to set the PIC register. */ |
2562 | ||
2563 | static rtx | |
2564 | pic_setup_code () | |
2565 | { | |
2566 | rtx seq; | |
2567 | ||
2568 | start_sequence (); | |
2569 | emit_insn (gen_get_pc (pic_offset_table_rtx, global_offset_table, | |
2570 | get_pc_symbol)); | |
2571 | seq = gen_sequence (); | |
2572 | end_sequence (); | |
82d6b402 | 2573 | |
e0d80184 DM |
2574 | return seq; |
2575 | } | |
795068a4 | 2576 | |
e0d80184 | 2577 | /* Emit special PIC prologues and epilogues. */ |
795068a4 | 2578 | |
e0d80184 DM |
2579 | void |
2580 | finalize_pic () | |
2581 | { | |
2582 | /* Labels to get the PC in the prologue of this function. */ | |
2583 | int orig_flag_pic = flag_pic; | |
2584 | rtx insn; | |
4fb4e4b8 | 2585 | |
e0d80184 DM |
2586 | if (current_function_uses_pic_offset_table == 0) |
2587 | return; | |
795068a4 | 2588 | |
e0d80184 DM |
2589 | if (! flag_pic) |
2590 | abort (); | |
2591 | ||
2592 | /* If we havn't emitted the special get_pc helper function, do so now. */ | |
2593 | if (get_pc_symbol_name[0] == 0) | |
4fb4e4b8 | 2594 | { |
d676da68 | 2595 | int align; |
82d6b402 | 2596 | |
d676da68 | 2597 | ASM_GENERATE_INTERNAL_LABEL (get_pc_symbol_name, "LGETPC", 0); |
e0d80184 | 2598 | text_section (); |
d676da68 DM |
2599 | |
2600 | align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT); | |
2601 | if (align > 0) | |
2602 | ASM_OUTPUT_ALIGN (asm_out_file, align); | |
e0d80184 DM |
2603 | ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "LGETPC", 0); |
2604 | fputs ("\tretl\n\tadd %o7,%l7,%l7\n", asm_out_file); | |
2605 | } | |
82d6b402 | 2606 | |
e0d80184 DM |
2607 | /* Initialize every time through, since we can't easily |
2608 | know this to be permanent. */ | |
2609 | global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_"); | |
2610 | get_pc_symbol = gen_rtx_SYMBOL_REF (Pmode, get_pc_symbol_name); | |
2611 | flag_pic = 0; | |
82d6b402 | 2612 | |
e0d80184 | 2613 | emit_insn_after (pic_setup_code (), get_insns ()); |
82d6b402 | 2614 | |
24a43d7b DM |
2615 | /* Insert the code in each nonlocal goto receiver. |
2616 | If you make changes here or to the nonlocal_goto_receiver | |
2617 | pattern, make sure the unspec_volatile numbers still | |
2618 | match. */ | |
e0d80184 DM |
2619 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) |
2620 | if (GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == UNSPEC_VOLATILE | |
24a43d7b | 2621 | && XINT (PATTERN (insn), 1) == 5) |
e0d80184 | 2622 | emit_insn_after (pic_setup_code (), insn); |
82d6b402 | 2623 | |
e0d80184 | 2624 | flag_pic = orig_flag_pic; |
82d6b402 | 2625 | |
e0d80184 DM |
2626 | /* Need to emit this whether or not we obey regdecls, |
2627 | since setjmp/longjmp can cause life info to screw up. | |
2628 | ??? In the case where we don't obey regdecls, this is not sufficient | |
2629 | since we may not fall out the bottom. */ | |
2630 | emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx)); | |
795068a4 | 2631 | } |
ab835497 | 2632 | \f |
e0d80184 DM |
2633 | /* Return 1 if RTX is a MEM which is known to be aligned to at |
2634 | least an 8 byte boundary. */ | |
a3ee5899 | 2635 | |
e0d80184 DM |
2636 | int |
2637 | mem_min_alignment (mem, desired) | |
2638 | rtx mem; | |
2639 | int desired; | |
ab835497 | 2640 | { |
e0d80184 DM |
2641 | rtx addr, base, offset; |
2642 | ||
2643 | /* If it's not a MEM we can't accept it. */ | |
2644 | if (GET_CODE (mem) != MEM) | |
2645 | return 0; | |
2646 | ||
2647 | addr = XEXP (mem, 0); | |
2648 | base = offset = NULL_RTX; | |
2649 | if (GET_CODE (addr) == PLUS) | |
ab835497 | 2650 | { |
e0d80184 | 2651 | if (GET_CODE (XEXP (addr, 0)) == REG) |
61a55e8b | 2652 | { |
e0d80184 DM |
2653 | base = XEXP (addr, 0); |
2654 | ||
2655 | /* What we are saying here is that if the base | |
2656 | REG is aligned properly, the compiler will make | |
2657 | sure any REG based index upon it will be so | |
2658 | as well. */ | |
2659 | if (GET_CODE (XEXP (addr, 1)) == CONST_INT) | |
2660 | offset = XEXP (addr, 1); | |
61a55e8b | 2661 | else |
e0d80184 | 2662 | offset = const0_rtx; |
61a55e8b | 2663 | } |
ab835497 | 2664 | } |
e0d80184 | 2665 | else if (GET_CODE (addr) == REG) |
ab835497 | 2666 | { |
e0d80184 DM |
2667 | base = addr; |
2668 | offset = const0_rtx; | |
ab835497 | 2669 | } |
82d6b402 | 2670 | |
e0d80184 | 2671 | if (base != NULL_RTX) |
795068a4 | 2672 | { |
e0d80184 DM |
2673 | int regno = REGNO (base); |
2674 | ||
2675 | if (regno != FRAME_POINTER_REGNUM | |
2676 | && regno != STACK_POINTER_REGNUM) | |
61a55e8b | 2677 | { |
e0d80184 DM |
2678 | /* Check if the compiler has recorded some information |
2679 | about the alignment of the base REG. If reload has | |
2680 | completed, we already matched with proper alignments. */ | |
49ad7cfa | 2681 | if (((current_function != 0 |
e0d80184 DM |
2682 | && REGNO_POINTER_ALIGN (regno) >= desired) |
2683 | || reload_completed) | |
2684 | && ((INTVAL (offset) & (desired - 1)) == 0)) | |
2685 | return 1; | |
61a55e8b | 2686 | } |
795068a4 | 2687 | else |
e0d80184 DM |
2688 | { |
2689 | if (((INTVAL (offset) - SPARC_STACK_BIAS) & (desired - 1)) == 0) | |
2690 | return 1; | |
2691 | } | |
795068a4 | 2692 | } |
e0d80184 DM |
2693 | else if (! TARGET_UNALIGNED_DOUBLES |
2694 | || CONSTANT_P (addr) | |
2695 | || GET_CODE (addr) == LO_SUM) | |
795068a4 | 2696 | { |
e0d80184 DM |
2697 | /* Anything else we know is properly aligned unless TARGET_UNALIGNED_DOUBLES |
2698 | is true, in which case we can only assume that an access is aligned if | |
2699 | it is to a constant address, or the address involves a LO_SUM. */ | |
2700 | return 1; | |
795068a4 | 2701 | } |
e0d80184 DM |
2702 | |
2703 | /* An obviously unaligned address. */ | |
2704 | return 0; | |
795068a4 | 2705 | } |
e0d80184 | 2706 | |
ab835497 | 2707 | \f |
61a55e8b DE |
2708 | /* Vectors to keep interesting information about registers where it can easily |
2709 | be got. We use to use the actual mode value as the bit number, but there | |
2710 | are more than 32 modes now. Instead we use two tables: one indexed by | |
2711 | hard register number, and one indexed by mode. */ | |
2712 | ||
2713 | /* The purpose of sparc_mode_class is to shrink the range of modes so that | |
2714 | they all fit (as bit numbers) in a 32 bit word (again). Each real mode is | |
2715 | mapped into one sparc_mode_class mode. */ | |
2716 | ||
2717 | enum sparc_mode_class { | |
61a55e8b | 2718 | S_MODE, D_MODE, T_MODE, O_MODE, |
c4ce6853 DE |
2719 | SF_MODE, DF_MODE, TF_MODE, OF_MODE, |
2720 | CC_MODE, CCFP_MODE | |
61a55e8b | 2721 | }; |
ab835497 | 2722 | |
61a55e8b DE |
2723 | /* Modes for single-word and smaller quantities. */ |
2724 | #define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE)) | |
2725 | ||
2726 | /* Modes for double-word and smaller quantities. */ | |
2727 | #define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE)) | |
2728 | ||
2729 | /* Modes for quad-word and smaller quantities. */ | |
2730 | #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE)) | |
ab835497 | 2731 | |
1e4eb8d1 JW |
2732 | /* Modes for single-float quantities. We must allow any single word or |
2733 | smaller quantity. This is because the fix/float conversion instructions | |
2734 | take integer inputs/outputs from the float registers. */ | |
2735 | #define SF_MODES (S_MODES) | |
ab835497 | 2736 | |
61a55e8b DE |
2737 | /* Modes for double-float and smaller quantities. */ |
2738 | #define DF_MODES (S_MODES | D_MODES) | |
2739 | ||
284d86e9 | 2740 | #define DF_MODES64 DF_MODES |
61a55e8b DE |
2741 | |
2742 | /* Modes for double-float only quantities. */ | |
284d86e9 | 2743 | #define DF_ONLY_MODES ((1 << (int) DF_MODE) | (1 << (int) D_MODE)) |
61a55e8b DE |
2744 | |
2745 | /* Modes for double-float and larger quantities. */ | |
2746 | #define DF_UP_MODES (DF_ONLY_MODES | TF_ONLY_MODES) | |
ab835497 | 2747 | |
61a55e8b DE |
2748 | /* Modes for quad-float only quantities. */ |
2749 | #define TF_ONLY_MODES (1 << (int) TF_MODE) | |
2750 | ||
2751 | /* Modes for quad-float and smaller quantities. */ | |
2752 | #define TF_MODES (DF_MODES | TF_ONLY_MODES) | |
2753 | ||
61a55e8b | 2754 | #define TF_MODES64 (DF_MODES64 | TF_ONLY_MODES) |
ab835497 | 2755 | |
c4ce6853 DE |
2756 | /* Modes for condition codes. */ |
2757 | #define CC_MODES (1 << (int) CC_MODE) | |
2758 | #define CCFP_MODES (1 << (int) CCFP_MODE) | |
2759 | ||
ab835497 RK |
2760 | /* Value is 1 if register/mode pair is acceptable on sparc. |
2761 | The funny mixture of D and T modes is because integer operations | |
2762 | do not specially operate on tetra quantities, so non-quad-aligned | |
2763 | registers can hold quadword quantities (except %o4 and %i4 because | |
c4ce6853 | 2764 | they cross fixed registers). */ |
ab835497 | 2765 | |
61a55e8b DE |
2766 | /* This points to either the 32 bit or the 64 bit version. */ |
2767 | int *hard_regno_mode_classes; | |
2768 | ||
2769 | static int hard_32bit_mode_classes[] = { | |
c4ce6853 | 2770 | S_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, |
ab835497 RK |
2771 | T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES, |
2772 | T_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, | |
2773 | T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES, | |
2774 | ||
2775 | TF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES, | |
2776 | TF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES, | |
2777 | TF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES, | |
61a55e8b | 2778 | TF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES, |
a9e27770 DE |
2779 | |
2780 | /* FP regs f32 to f63. Only the even numbered registers actually exist, | |
2781 | and none can hold SFmode/SImode values. */ | |
2782 | DF_UP_MODES, 0, DF_ONLY_MODES, 0, DF_UP_MODES, 0, DF_ONLY_MODES, 0, | |
2783 | DF_UP_MODES, 0, DF_ONLY_MODES, 0, DF_UP_MODES, 0, DF_ONLY_MODES, 0, | |
2784 | DF_UP_MODES, 0, DF_ONLY_MODES, 0, DF_UP_MODES, 0, DF_ONLY_MODES, 0, | |
2785 | DF_UP_MODES, 0, DF_ONLY_MODES, 0, DF_UP_MODES, 0, DF_ONLY_MODES, 0, | |
2786 | ||
2787 | /* %fcc[0123] */ | |
c4ce6853 DE |
2788 | CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES, |
2789 | ||
2790 | /* %icc */ | |
2791 | CC_MODES | |
61a55e8b DE |
2792 | }; |
2793 | ||
2794 | static int hard_64bit_mode_classes[] = { | |
c4ce6853 | 2795 | D_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, |
61a55e8b DE |
2796 | T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, |
2797 | T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, | |
2798 | T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, | |
2799 | ||
2800 | TF_MODES64, SF_MODES, DF_MODES64, SF_MODES, TF_MODES64, SF_MODES, DF_MODES64, SF_MODES, | |
2801 | TF_MODES64, SF_MODES, DF_MODES64, SF_MODES, TF_MODES64, SF_MODES, DF_MODES64, SF_MODES, | |
2802 | TF_MODES64, SF_MODES, DF_MODES64, SF_MODES, TF_MODES64, SF_MODES, DF_MODES64, SF_MODES, | |
2803 | TF_MODES64, SF_MODES, DF_MODES64, SF_MODES, TF_MODES64, SF_MODES, DF_MODES64, SF_MODES, | |
2804 | ||
a9e27770 | 2805 | /* FP regs f32 to f63. Only the even numbered registers actually exist, |
61a55e8b DE |
2806 | and none can hold SFmode/SImode values. */ |
2807 | DF_UP_MODES, 0, DF_ONLY_MODES, 0, DF_UP_MODES, 0, DF_ONLY_MODES, 0, | |
2808 | DF_UP_MODES, 0, DF_ONLY_MODES, 0, DF_UP_MODES, 0, DF_ONLY_MODES, 0, | |
2809 | DF_UP_MODES, 0, DF_ONLY_MODES, 0, DF_UP_MODES, 0, DF_ONLY_MODES, 0, | |
2810 | DF_UP_MODES, 0, DF_ONLY_MODES, 0, DF_UP_MODES, 0, DF_ONLY_MODES, 0, | |
2811 | ||
2812 | /* %fcc[0123] */ | |
c4ce6853 DE |
2813 | CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES, |
2814 | ||
2815 | /* %icc */ | |
2816 | CC_MODES | |
61a55e8b DE |
2817 | }; |
2818 | ||
2819 | int sparc_mode_class [NUM_MACHINE_MODES]; | |
2820 | ||
c4ce6853 DE |
2821 | enum reg_class sparc_regno_reg_class[FIRST_PSEUDO_REGISTER]; |
2822 | ||
61a55e8b DE |
2823 | static void |
2824 | sparc_init_modes () | |
2825 | { | |
2826 | int i; | |
2827 | ||
61a55e8b DE |
2828 | for (i = 0; i < NUM_MACHINE_MODES; i++) |
2829 | { | |
2830 | switch (GET_MODE_CLASS (i)) | |
2831 | { | |
2832 | case MODE_INT: | |
2833 | case MODE_PARTIAL_INT: | |
2834 | case MODE_COMPLEX_INT: | |
2835 | if (GET_MODE_SIZE (i) <= 4) | |
2836 | sparc_mode_class[i] = 1 << (int) S_MODE; | |
2837 | else if (GET_MODE_SIZE (i) == 8) | |
2838 | sparc_mode_class[i] = 1 << (int) D_MODE; | |
2839 | else if (GET_MODE_SIZE (i) == 16) | |
2840 | sparc_mode_class[i] = 1 << (int) T_MODE; | |
2841 | else if (GET_MODE_SIZE (i) == 32) | |
2842 | sparc_mode_class[i] = 1 << (int) O_MODE; | |
2843 | else | |
2844 | sparc_mode_class[i] = 0; | |
2845 | break; | |
2846 | case MODE_FLOAT: | |
2847 | case MODE_COMPLEX_FLOAT: | |
2848 | if (GET_MODE_SIZE (i) <= 4) | |
2849 | sparc_mode_class[i] = 1 << (int) SF_MODE; | |
2850 | else if (GET_MODE_SIZE (i) == 8) | |
2851 | sparc_mode_class[i] = 1 << (int) DF_MODE; | |
2852 | else if (GET_MODE_SIZE (i) == 16) | |
2853 | sparc_mode_class[i] = 1 << (int) TF_MODE; | |
2854 | else if (GET_MODE_SIZE (i) == 32) | |
2855 | sparc_mode_class[i] = 1 << (int) OF_MODE; | |
2856 | else | |
2857 | sparc_mode_class[i] = 0; | |
2858 | break; | |
2859 | case MODE_CC: | |
2860 | default: | |
2861 | /* mode_class hasn't been initialized yet for EXTRA_CC_MODES, so | |
2862 | we must explicitly check for them here. */ | |
2863 | if (i == (int) CCFPmode || i == (int) CCFPEmode) | |
2864 | sparc_mode_class[i] = 1 << (int) CCFP_MODE; | |
2865 | else if (i == (int) CCmode || i == (int) CC_NOOVmode | |
a9e27770 | 2866 | || i == (int) CCXmode || i == (int) CCX_NOOVmode) |
c4ce6853 | 2867 | sparc_mode_class[i] = 1 << (int) CC_MODE; |
61a55e8b DE |
2868 | else |
2869 | sparc_mode_class[i] = 0; | |
2870 | break; | |
2871 | } | |
2872 | } | |
2873 | ||
a9e27770 | 2874 | if (TARGET_ARCH64) |
61a55e8b DE |
2875 | hard_regno_mode_classes = hard_64bit_mode_classes; |
2876 | else | |
2877 | hard_regno_mode_classes = hard_32bit_mode_classes; | |
c4ce6853 DE |
2878 | |
2879 | /* Initialize the array used by REGNO_REG_CLASS. */ | |
2880 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
2881 | { | |
284d86e9 JC |
2882 | if (i < 16 && TARGET_V8PLUS) |
2883 | sparc_regno_reg_class[i] = I64_REGS; | |
2884 | else if (i < 32) | |
c4ce6853 DE |
2885 | sparc_regno_reg_class[i] = GENERAL_REGS; |
2886 | else if (i < 64) | |
2887 | sparc_regno_reg_class[i] = FP_REGS; | |
2888 | else if (i < 96) | |
2889 | sparc_regno_reg_class[i] = EXTRA_FP_REGS; | |
2890 | else if (i < 100) | |
2891 | sparc_regno_reg_class[i] = FPCC_REGS; | |
2892 | else | |
2893 | sparc_regno_reg_class[i] = NO_REGS; | |
2894 | } | |
61a55e8b | 2895 | } |
ab835497 | 2896 | \f |
61a55e8b DE |
2897 | /* Save non call used registers from LOW to HIGH at BASE+OFFSET. |
2898 | N_REGS is the number of 4-byte regs saved thus far. This applies even to | |
2899 | v9 int regs as it simplifies the code. */ | |
2900 | ||
ab835497 | 2901 | static int |
c53aa195 | 2902 | save_regs (file, low, high, base, offset, n_regs, real_offset) |
ab835497 RK |
2903 | FILE *file; |
2904 | int low, high; | |
3bb5de61 | 2905 | const char *base; |
ab835497 | 2906 | int offset; |
61a55e8b | 2907 | int n_regs; |
c53aa195 | 2908 | int real_offset; |
ab835497 RK |
2909 | { |
2910 | int i; | |
2911 | ||
a9e27770 | 2912 | if (TARGET_ARCH64 && high <= 32) |
ab835497 | 2913 | { |
61a55e8b DE |
2914 | for (i = low; i < high; i++) |
2915 | { | |
2916 | if (regs_ever_live[i] && ! call_used_regs[i]) | |
c53aa195 | 2917 | { |
e0d80184 | 2918 | fprintf (file, "\tstx\t%s, [%s+%d]\n", |
c53aa195 | 2919 | reg_names[i], base, offset + 4 * n_regs); |
0021b564 | 2920 | if (dwarf2out_do_frame ()) |
c53aa195 | 2921 | dwarf2out_reg_save ("", i, real_offset + 4 * n_regs); |
c53aa195 JM |
2922 | n_regs += 2; |
2923 | } | |
61a55e8b | 2924 | } |
ab835497 | 2925 | } |
61a55e8b DE |
2926 | else |
2927 | { | |
2928 | for (i = low; i < high; i += 2) | |
2929 | { | |
2930 | if (regs_ever_live[i] && ! call_used_regs[i]) | |
c53aa195 | 2931 | { |
5e9defae KG |
2932 | if (regs_ever_live[i+1] && ! call_used_regs[i+1]) |
2933 | { | |
e0d80184 | 2934 | fprintf (file, "\tstd\t%s, [%s+%d]\n", |
5e9defae KG |
2935 | reg_names[i], base, offset + 4 * n_regs); |
2936 | if (dwarf2out_do_frame ()) | |
2937 | { | |
2938 | char *l = dwarf2out_cfi_label (); | |
2939 | dwarf2out_reg_save (l, i, real_offset + 4 * n_regs); | |
2940 | dwarf2out_reg_save (l, i+1, real_offset + 4 * n_regs + 4); | |
2941 | } | |
2942 | n_regs += 2; | |
2943 | } | |
2944 | else | |
2945 | { | |
e0d80184 | 2946 | fprintf (file, "\tst\t%s, [%s+%d]\n", |
5e9defae KG |
2947 | reg_names[i], base, offset + 4 * n_regs); |
2948 | if (dwarf2out_do_frame ()) | |
2949 | dwarf2out_reg_save ("", i, real_offset + 4 * n_regs); | |
2950 | n_regs += 2; | |
2951 | } | |
2952 | } | |
2953 | else | |
2954 | { | |
2955 | if (regs_ever_live[i+1] && ! call_used_regs[i+1]) | |
2956 | { | |
e0d80184 | 2957 | fprintf (file, "\tst\t%s, [%s+%d]\n", |
5e9defae KG |
2958 | reg_names[i+1], base, offset + 4 * n_regs + 4); |
2959 | if (dwarf2out_do_frame ()) | |
2960 | dwarf2out_reg_save ("", i + 1, real_offset + 4 * n_regs + 4); | |
2961 | n_regs += 2; | |
2962 | } | |
c53aa195 | 2963 | } |
61a55e8b DE |
2964 | } |
2965 | } | |
2966 | return n_regs; | |
ab835497 RK |
2967 | } |
2968 | ||
61a55e8b DE |
2969 | /* Restore non call used registers from LOW to HIGH at BASE+OFFSET. |
2970 | ||
2971 | N_REGS is the number of 4-byte regs saved thus far. This applies even to | |
2972 | v9 int regs as it simplifies the code. */ | |
2973 | ||
ab835497 | 2974 | static int |
61a55e8b | 2975 | restore_regs (file, low, high, base, offset, n_regs) |
ab835497 RK |
2976 | FILE *file; |
2977 | int low, high; | |
3bb5de61 | 2978 | const char *base; |
ab835497 | 2979 | int offset; |
61a55e8b | 2980 | int n_regs; |
ab835497 RK |
2981 | { |
2982 | int i; | |
2983 | ||
a9e27770 | 2984 | if (TARGET_ARCH64 && high <= 32) |
61a55e8b DE |
2985 | { |
2986 | for (i = low; i < high; i++) | |
2987 | { | |
2988 | if (regs_ever_live[i] && ! call_used_regs[i]) | |
e0d80184 | 2989 | fprintf (file, "\tldx\t[%s+%d], %s\n", |
61a55e8b DE |
2990 | base, offset + 4 * n_regs, reg_names[i]), |
2991 | n_regs += 2; | |
2992 | } | |
2993 | } | |
2994 | else | |
ab835497 | 2995 | { |
61a55e8b DE |
2996 | for (i = low; i < high; i += 2) |
2997 | { | |
2998 | if (regs_ever_live[i] && ! call_used_regs[i]) | |
2999 | if (regs_ever_live[i+1] && ! call_used_regs[i+1]) | |
e0d80184 | 3000 | fprintf (file, "\tldd\t[%s+%d], %s\n", |
61a55e8b DE |
3001 | base, offset + 4 * n_regs, reg_names[i]), |
3002 | n_regs += 2; | |
3003 | else | |
e0d80184 | 3004 | fprintf (file, "\tld\t[%s+%d],%s\n", |
61a55e8b DE |
3005 | base, offset + 4 * n_regs, reg_names[i]), |
3006 | n_regs += 2; | |
3007 | else if (regs_ever_live[i+1] && ! call_used_regs[i+1]) | |
e0d80184 | 3008 | fprintf (file, "\tld\t[%s+%d],%s\n", |
61a55e8b DE |
3009 | base, offset + 4 * n_regs + 4, reg_names[i+1]), |
3010 | n_regs += 2; | |
3011 | } | |
ab835497 | 3012 | } |
61a55e8b | 3013 | return n_regs; |
ab835497 RK |
3014 | } |
3015 | ||
61a55e8b DE |
3016 | /* Compute the frame size required by the function. This function is called |
3017 | during the reload pass and also by output_function_prologue(). */ | |
ab835497 | 3018 | |
ab835497 RK |
3019 | int |
3020 | compute_frame_size (size, leaf_function) | |
3021 | int size; | |
3022 | int leaf_function; | |
3023 | { | |
61a55e8b | 3024 | int n_regs = 0, i; |
ab835497 | 3025 | int outgoing_args_size = (current_function_outgoing_args_size |
4fb4e4b8 | 3026 | + REG_PARM_STACK_SPACE (current_function_decl)); |
ab835497 | 3027 | |
61a55e8b | 3028 | if (TARGET_EPILOGUE) |
ab835497 | 3029 | { |
61a55e8b DE |
3030 | /* N_REGS is the number of 4-byte regs saved thus far. This applies |
3031 | even to v9 int regs to be consistent with save_regs/restore_regs. */ | |
3032 | ||
a9e27770 | 3033 | if (TARGET_ARCH64) |
61a55e8b DE |
3034 | { |
3035 | for (i = 0; i < 8; i++) | |
3036 | if (regs_ever_live[i] && ! call_used_regs[i]) | |
3037 | n_regs += 2; | |
3038 | } | |
3039 | else | |
3040 | { | |
3041 | for (i = 0; i < 8; i += 2) | |
3042 | if ((regs_ever_live[i] && ! call_used_regs[i]) | |
3043 | || (regs_ever_live[i+1] && ! call_used_regs[i+1])) | |
3044 | n_regs += 2; | |
3045 | } | |
3046 | ||
3047 | for (i = 32; i < (TARGET_V9 ? 96 : 64); i += 2) | |
ab835497 RK |
3048 | if ((regs_ever_live[i] && ! call_used_regs[i]) |
3049 | || (regs_ever_live[i+1] && ! call_used_regs[i+1])) | |
61a55e8b | 3050 | n_regs += 2; |
ab835497 RK |
3051 | } |
3052 | ||
3053 | /* Set up values for use in `function_epilogue'. */ | |
61a55e8b | 3054 | num_gfregs = n_regs; |
ab835497 | 3055 | |
61a55e8b DE |
3056 | if (leaf_function && n_regs == 0 |
3057 | && size == 0 && current_function_outgoing_args_size == 0) | |
3058 | { | |
3059 | actual_fsize = apparent_fsize = 0; | |
3060 | } | |
3061 | else | |
3062 | { | |
3063 | /* We subtract STARTING_FRAME_OFFSET, remember it's negative. | |
3064 | The stack bias (if any) is taken out to undo its effects. */ | |
3065 | apparent_fsize = (size - STARTING_FRAME_OFFSET + SPARC_STACK_BIAS + 7) & -8; | |
3066 | apparent_fsize += n_regs * 4; | |
3067 | actual_fsize = apparent_fsize + ((outgoing_args_size + 7) & -8); | |
3068 | } | |
ab835497 RK |
3069 | |
3070 | /* Make sure nothing can clobber our register windows. | |
3071 | If a SAVE must be done, or there is a stack-local variable, | |
61a55e8b | 3072 | the register window area must be allocated. |
4fb4e4b8 | 3073 | ??? For v8 we apparently need an additional 8 bytes of reserved space. */ |
ab835497 | 3074 | if (leaf_function == 0 || size > 0) |
4fb4e4b8 | 3075 | actual_fsize += (16 * UNITS_PER_WORD) + (TARGET_ARCH64 ? 0 : 8); |
ab835497 | 3076 | |
61a55e8b DE |
3077 | return SPARC_STACK_ALIGN (actual_fsize); |
3078 | } | |
3079 | ||
3080 | /* Build a (32 bit) big number in a register. */ | |
86735b02 | 3081 | /* ??? We may be able to use the set macro here too. */ |
61a55e8b DE |
3082 | |
3083 | static void | |
3084 | build_big_number (file, num, reg) | |
3085 | FILE *file; | |
3086 | int num; | |
3bb5de61 | 3087 | const char *reg; |
61a55e8b | 3088 | { |
a9e27770 | 3089 | if (num >= 0 || ! TARGET_ARCH64) |
61a55e8b | 3090 | { |
e0d80184 | 3091 | fprintf (file, "\tsethi\t%%hi(%d), %s\n", num, reg); |
61a55e8b | 3092 | if ((num & 0x3ff) != 0) |
e0d80184 | 3093 | fprintf (file, "\tor\t%s, %%lo(%d), %s\n", reg, num, reg); |
61a55e8b | 3094 | } |
a9e27770 | 3095 | else /* num < 0 && TARGET_ARCH64 */ |
61a55e8b DE |
3096 | { |
3097 | /* Sethi does not sign extend, so we must use a little trickery | |
3098 | to use it for negative numbers. Invert the constant before | |
3099 | loading it in, then use xor immediate to invert the loaded bits | |
3100 | (along with the upper 32 bits) to the desired constant. This | |
3101 | works because the sethi and immediate fields overlap. */ | |
3102 | int asize = num; | |
3103 | int inv = ~asize; | |
3104 | int low = -0x400 + (asize & 0x3FF); | |
3105 | ||
e0d80184 | 3106 | fprintf (file, "\tsethi\t%%hi(%d), %s\n\txor\t%s, %d, %s\n", |
61a55e8b DE |
3107 | inv, reg, reg, low, reg); |
3108 | } | |
ab835497 RK |
3109 | } |
3110 | ||
1cb36a98 RH |
3111 | /* Output any necessary .register pseudo-ops. */ |
3112 | void | |
3113 | sparc_output_scratch_registers (file) | |
3114 | FILE *file; | |
3115 | { | |
3116 | #ifdef HAVE_AS_REGISTER_PSEUDO_OP | |
3117 | int i; | |
3118 | ||
3119 | if (TARGET_ARCH32) | |
3120 | return; | |
3121 | ||
3122 | /* Check if %g[2367] were used without | |
3123 | .register being printed for them already. */ | |
3124 | for (i = 2; i < 8; i++) | |
3125 | { | |
3126 | if (regs_ever_live [i] | |
3127 | && ! sparc_hard_reg_printed [i]) | |
3128 | { | |
3129 | sparc_hard_reg_printed [i] = 1; | |
3130 | fprintf (file, "\t.register\t%%g%d, #scratch\n", i); | |
3131 | } | |
3132 | if (i == 3) i = 5; | |
3133 | } | |
3134 | #endif | |
3135 | } | |
3136 | ||
915f619f JW |
3137 | /* Output code for the function prologue. */ |
3138 | ||
ab835497 RK |
3139 | void |
3140 | output_function_prologue (file, size, leaf_function) | |
3141 | FILE *file; | |
3142 | int size; | |
915f619f | 3143 | int leaf_function; |
ab835497 | 3144 | { |
1cb36a98 RH |
3145 | sparc_output_scratch_registers (file); |
3146 | ||
915f619f JW |
3147 | /* Need to use actual_fsize, since we are also allocating |
3148 | space for our callee (and our own register save area). */ | |
ab835497 RK |
3149 | actual_fsize = compute_frame_size (size, leaf_function); |
3150 | ||
61a55e8b DE |
3151 | if (leaf_function) |
3152 | { | |
3153 | frame_base_name = "%sp"; | |
3154 | frame_base_offset = actual_fsize + SPARC_STACK_BIAS; | |
3155 | } | |
3156 | else | |
3157 | { | |
3158 | frame_base_name = "%fp"; | |
3159 | frame_base_offset = SPARC_STACK_BIAS; | |
3160 | } | |
3161 | ||
c6aa9ce1 | 3162 | /* This is only for the human reader. */ |
bf62bbf1 | 3163 | fprintf (file, "\t%s#PROLOGUE# 0\n", ASM_COMMENT_START); |
c6aa9ce1 | 3164 | |
915f619f JW |
3165 | if (actual_fsize == 0) |
3166 | /* do nothing. */ ; | |
3592ea0d | 3167 | else if (! leaf_function && ! TARGET_BROKEN_SAVERESTORE) |
ab835497 | 3168 | { |
3592ea0d | 3169 | if (actual_fsize <= 4096) |
e0d80184 | 3170 | fprintf (file, "\tsave\t%%sp, -%d, %%sp\n", actual_fsize); |
3592ea0d | 3171 | else if (actual_fsize <= 8192) |
915f619f | 3172 | { |
e0d80184 DM |
3173 | fprintf (file, "\tsave\t%%sp, -4096, %%sp\n"); |
3174 | fprintf (file, "\tadd\t%%sp, -%d, %%sp\n", actual_fsize - 4096); | |
915f619f JW |
3175 | } |
3176 | else | |
3177 | { | |
3592ea0d | 3178 | build_big_number (file, -actual_fsize, "%g1"); |
e0d80184 | 3179 | fprintf (file, "\tsave\t%%sp, %%g1, %%sp\n"); |
915f619f | 3180 | } |
ab835497 | 3181 | } |
5f4241d5 | 3182 | else if (! leaf_function && TARGET_BROKEN_SAVERESTORE) |
ab835497 | 3183 | { |
5f4241d5 | 3184 | /* We assume the environment will properly handle or otherwise avoid |
956d6950 JL |
3185 | trouble associated with an interrupt occurring after the `save' or |
3186 | trap occurring during it. */ | |
5f4241d5 | 3187 | fprintf (file, "\tsave\n"); |
3592ea0d | 3188 | |
5f4241d5 | 3189 | if (actual_fsize <= 4096) |
e0d80184 | 3190 | fprintf (file, "\tadd\t%%fp, -%d, %%sp\n", actual_fsize); |
5f4241d5 DE |
3191 | else if (actual_fsize <= 8192) |
3192 | { | |
e0d80184 DM |
3193 | fprintf (file, "\tadd\t%%fp, -4096, %%sp\n"); |
3194 | fprintf (file, "\tadd\t%%fp, -%d, %%sp\n", actual_fsize - 4096); | |
5f4241d5 DE |
3195 | } |
3196 | else | |
3197 | { | |
3198 | build_big_number (file, -actual_fsize, "%g1"); | |
e0d80184 | 3199 | fprintf (file, "\tadd\t%%fp, %%g1, %%sp\n"); |
5f4241d5 DE |
3200 | } |
3201 | } | |
3202 | else /* leaf function */ | |
3203 | { | |
3592ea0d | 3204 | if (actual_fsize <= 4096) |
e0d80184 | 3205 | fprintf (file, "\tadd\t%%sp, -%d, %%sp\n", actual_fsize); |
3592ea0d DE |
3206 | else if (actual_fsize <= 8192) |
3207 | { | |
e0d80184 DM |
3208 | fprintf (file, "\tadd\t%%sp, -4096, %%sp\n"); |
3209 | fprintf (file, "\tadd\t%%sp, -%d, %%sp\n", actual_fsize - 4096); | |
3592ea0d | 3210 | } |
915f619f | 3211 | else |
3592ea0d DE |
3212 | { |
3213 | build_big_number (file, -actual_fsize, "%g1"); | |
e0d80184 | 3214 | fprintf (file, "\tadd\t%%sp, %%g1, %%sp\n"); |
3592ea0d | 3215 | } |
ab835497 RK |
3216 | } |
3217 | ||
0021b564 | 3218 | if (dwarf2out_do_frame () && actual_fsize) |
c53aa195 | 3219 | { |
96987e96 | 3220 | char *label = dwarf2out_cfi_label (); |
c53aa195 JM |
3221 | |
3222 | /* The canonical frame address refers to the top of the frame. */ | |
3223 | dwarf2out_def_cfa (label, (leaf_function ? STACK_POINTER_REGNUM | |
3224 | : FRAME_POINTER_REGNUM), | |
3225 | frame_base_offset); | |
3226 | ||
3227 | if (! leaf_function) | |
3228 | { | |
3229 | /* Note the register window save. This tells the unwinder that | |
3230 | it needs to restore the window registers from the previous | |
3231 | frame's window save area at 0(cfa). */ | |
3232 | dwarf2out_window_save (label); | |
3233 | ||
3234 | /* The return address (-8) is now in %i7. */ | |
3235 | dwarf2out_return_reg (label, 31); | |
3236 | } | |
3237 | } | |
c53aa195 | 3238 | |
ab835497 RK |
3239 | /* If doing anything with PIC, do it now. */ |
3240 | if (! flag_pic) | |
bf62bbf1 | 3241 | fprintf (file, "\t%s#PROLOGUE# 1\n", ASM_COMMENT_START); |
ab835497 | 3242 | |
61a55e8b DE |
3243 | /* Call saved registers are saved just above the outgoing argument area. */ |
3244 | if (num_gfregs) | |
ab835497 | 3245 | { |
c53aa195 | 3246 | int offset, real_offset, n_regs; |
3bb5de61 | 3247 | const char *base; |
ab835497 | 3248 | |
84e884e9 JM |
3249 | real_offset = -apparent_fsize; |
3250 | offset = -apparent_fsize + frame_base_offset; | |
61a55e8b DE |
3251 | if (offset < -4096 || offset + num_gfregs * 4 > 4096) |
3252 | { | |
3253 | /* ??? This might be optimized a little as %g1 might already have a | |
3254 | value close enough that a single add insn will do. */ | |
3255 | /* ??? Although, all of this is probably only a temporary fix | |
3256 | because if %g1 can hold a function result, then | |
3257 | output_function_epilogue will lose (the result will get | |
3258 | clobbered). */ | |
3259 | build_big_number (file, offset, "%g1"); | |
e0d80184 | 3260 | fprintf (file, "\tadd\t%s, %%g1, %%g1\n", frame_base_name); |
61a55e8b DE |
3261 | base = "%g1"; |
3262 | offset = 0; | |
3263 | } | |
ab835497 | 3264 | else |
61a55e8b DE |
3265 | { |
3266 | base = frame_base_name; | |
3267 | } | |
ab835497 | 3268 | |
db3d4438 | 3269 | n_regs = 0; |
ab835497 | 3270 | if (TARGET_EPILOGUE && ! leaf_function) |
61a55e8b | 3271 | /* ??? Originally saved regs 0-15 here. */ |
c53aa195 | 3272 | n_regs = save_regs (file, 0, 8, base, offset, 0, real_offset); |
ab835497 | 3273 | else if (leaf_function) |
61a55e8b | 3274 | /* ??? Originally saved regs 0-31 here. */ |
c53aa195 | 3275 | n_regs = save_regs (file, 0, 8, base, offset, 0, real_offset); |
ab835497 | 3276 | if (TARGET_EPILOGUE) |
c53aa195 JM |
3277 | save_regs (file, 32, TARGET_V9 ? 96 : 64, base, offset, n_regs, |
3278 | real_offset); | |
ab835497 RK |
3279 | } |
3280 | ||
ab835497 RK |
3281 | leaf_label = 0; |
3282 | if (leaf_function && actual_fsize != 0) | |
3283 | { | |
3284 | /* warning ("leaf procedure with frame size %d", actual_fsize); */ | |
3285 | if (! TARGET_EPILOGUE) | |
3286 | leaf_label = gen_label_rtx (); | |
3287 | } | |
3288 | } | |
3289 | ||
915f619f JW |
3290 | /* Output code for the function epilogue. */ |
3291 | ||
ab835497 | 3292 | void |
ef8200df | 3293 | output_function_epilogue (file, size, leaf_function) |
ab835497 | 3294 | FILE *file; |
db3d4438 | 3295 | int size ATTRIBUTE_UNUSED; |
ef8200df | 3296 | int leaf_function; |
ab835497 | 3297 | { |
3bb5de61 | 3298 | const char *ret; |
ab835497 RK |
3299 | |
3300 | if (leaf_label) | |
3301 | { | |
ab835497 RK |
3302 | emit_label_after (leaf_label, get_last_insn ()); |
3303 | final_scan_insn (get_last_insn (), file, 0, 0, 1); | |
3304 | } | |
3305 | ||
b69649e4 RK |
3306 | #ifdef FUNCTION_BLOCK_PROFILER_EXIT |
3307 | else if (profile_block_flag == 2) | |
3308 | { | |
3309 | FUNCTION_BLOCK_PROFILER_EXIT(file); | |
3310 | } | |
3311 | #endif | |
3312 | ||
bfd6bc60 | 3313 | else if (current_function_epilogue_delay_list == 0) |
e48addee | 3314 | { |
e0d80184 DM |
3315 | /* If code does not drop into the epilogue, we need |
3316 | do nothing except output pending case vectors. */ | |
bfd6bc60 JC |
3317 | rtx insn = get_last_insn (); |
3318 | if (GET_CODE (insn) == NOTE) | |
3319 | insn = prev_nonnote_insn (insn); | |
3320 | if (insn && GET_CODE (insn) == BARRIER) | |
e0d80184 | 3321 | goto output_vectors; |
bfd6bc60 JC |
3322 | } |
3323 | ||
61a55e8b DE |
3324 | /* Restore any call saved registers. */ |
3325 | if (num_gfregs) | |
ab835497 | 3326 | { |
61a55e8b | 3327 | int offset, n_regs; |
3bb5de61 | 3328 | const char *base; |
ab835497 | 3329 | |
61a55e8b DE |
3330 | offset = -apparent_fsize + frame_base_offset; |
3331 | if (offset < -4096 || offset + num_gfregs * 4 > 4096 - 8 /*double*/) | |
3332 | { | |
3333 | build_big_number (file, offset, "%g1"); | |
e0d80184 | 3334 | fprintf (file, "\tadd\t%s, %%g1, %%g1\n", frame_base_name); |
61a55e8b DE |
3335 | base = "%g1"; |
3336 | offset = 0; | |
3337 | } | |
ab835497 | 3338 | else |
61a55e8b DE |
3339 | { |
3340 | base = frame_base_name; | |
3341 | } | |
ab835497 | 3342 | |
db3d4438 | 3343 | n_regs = 0; |
ab835497 | 3344 | if (TARGET_EPILOGUE && ! leaf_function) |
61a55e8b DE |
3345 | /* ??? Originally saved regs 0-15 here. */ |
3346 | n_regs = restore_regs (file, 0, 8, base, offset, 0); | |
ab835497 | 3347 | else if (leaf_function) |
61a55e8b DE |
3348 | /* ??? Originally saved regs 0-31 here. */ |
3349 | n_regs = restore_regs (file, 0, 8, base, offset, 0); | |
ab835497 | 3350 | if (TARGET_EPILOGUE) |
61a55e8b | 3351 | restore_regs (file, 32, TARGET_V9 ? 96 : 64, base, offset, n_regs); |
ab835497 RK |
3352 | } |
3353 | ||
3354 | /* Work out how to skip the caller's unimp instruction if required. */ | |
3355 | if (leaf_function) | |
e0d80184 | 3356 | ret = (SKIP_CALLERS_UNIMP_P ? "jmp\t%o7+12" : "retl"); |
ab835497 | 3357 | else |
e0d80184 | 3358 | ret = (SKIP_CALLERS_UNIMP_P ? "jmp\t%i7+12" : "ret"); |
ab835497 | 3359 | |
ef8200df | 3360 | if (TARGET_EPILOGUE || leaf_label) |
ab835497 | 3361 | { |
ef8200df JW |
3362 | int old_target_epilogue = TARGET_EPILOGUE; |
3363 | target_flags &= ~old_target_epilogue; | |
ab835497 | 3364 | |
ef8200df JW |
3365 | if (! leaf_function) |
3366 | { | |
3367 | /* If we wound up with things in our delay slot, flush them here. */ | |
3368 | if (current_function_epilogue_delay_list) | |
ab835497 | 3369 | { |
e48addee JJ |
3370 | rtx delay = PATTERN (XEXP (current_function_epilogue_delay_list, 0)); |
3371 | ||
3372 | if (TARGET_V9 && ! epilogue_renumber (&delay, 1)) | |
3373 | { | |
3374 | epilogue_renumber (&delay, 0); | |
3375 | fputs (SKIP_CALLERS_UNIMP_P | |
3376 | ? "\treturn\t%i7+12\n" | |
3377 | : "\treturn\t%i7+8\n", file); | |
3378 | final_scan_insn (XEXP (current_function_epilogue_delay_list, 0), file, 1, 0, 0); | |
3379 | } | |
3380 | else | |
3381 | { | |
3382 | rtx insn = emit_jump_insn_after (gen_rtx_RETURN (VOIDmode), | |
3383 | get_last_insn ()); | |
3384 | rtx src; | |
3385 | ||
3386 | if (GET_CODE (delay) != SET) | |
3387 | abort(); | |
3388 | ||
3389 | src = SET_SRC (delay); | |
3390 | if (GET_CODE (src) == ASHIFT) | |
3391 | { | |
3392 | if (XEXP (src, 1) != const1_rtx) | |
3393 | abort(); | |
3394 | SET_SRC (delay) = gen_rtx_PLUS (GET_MODE (src), XEXP (src, 0), | |
3395 | XEXP (src, 0)); | |
3396 | } | |
3397 | ||
3398 | PATTERN (insn) = gen_rtx_PARALLEL (VOIDmode, | |
3399 | gen_rtvec (2, delay, PATTERN (insn))); | |
3400 | final_scan_insn (insn, file, 1, 0, 1); | |
3401 | } | |
ab835497 | 3402 | } |
284d86e9 | 3403 | else if (TARGET_V9 && ! SKIP_CALLERS_UNIMP_P) |
e0d80184 | 3404 | fputs ("\treturn\t%i7+8\n\tnop\n", file); |
ab835497 | 3405 | else |
ef8200df JW |
3406 | fprintf (file, "\t%s\n\trestore\n", ret); |
3407 | } | |
915f619f JW |
3408 | /* All of the following cases are for leaf functions. */ |
3409 | else if (current_function_epilogue_delay_list) | |
ef8200df | 3410 | { |
915f619f JW |
3411 | /* eligible_for_epilogue_delay_slot ensures that if this is a |
3412 | leaf function, then we will only have insn in the delay slot | |
3413 | if the frame size is zero, thus no adjust for the stack is | |
3414 | needed here. */ | |
3415 | if (actual_fsize != 0) | |
ef8200df | 3416 | abort (); |
915f619f JW |
3417 | fprintf (file, "\t%s\n", ret); |
3418 | final_scan_insn (XEXP (current_function_epilogue_delay_list, 0), | |
3419 | file, 1, 0, 1); | |
ab835497 | 3420 | } |
9bb7ffda JW |
3421 | /* Output 'nop' instead of 'sub %sp,-0,%sp' when no frame, so as to |
3422 | avoid generating confusing assembly language output. */ | |
3423 | else if (actual_fsize == 0) | |
3424 | fprintf (file, "\t%s\n\tnop\n", ret); | |
915f619f | 3425 | else if (actual_fsize <= 4096) |
e0d80184 | 3426 | fprintf (file, "\t%s\n\tsub\t%%sp, -%d, %%sp\n", ret, actual_fsize); |
915f619f | 3427 | else if (actual_fsize <= 8192) |
e0d80184 | 3428 | fprintf (file, "\tsub\t%%sp, -4096, %%sp\n\t%s\n\tsub\t%%sp, -%d, %%sp\n", |
915f619f JW |
3429 | ret, actual_fsize - 4096); |
3430 | else if ((actual_fsize & 0x3ff) == 0) | |
e0d80184 | 3431 | fprintf (file, "\tsethi\t%%hi(%d), %%g1\n\t%s\n\tadd\t%%sp, %%g1, %%sp\n", |
915f619f JW |
3432 | actual_fsize, ret); |
3433 | else | |
e0d80184 | 3434 | fprintf (file, "\tsethi\t%%hi(%d), %%g1\n\tor\t%%g1, %%lo(%d), %%g1\n\t%s\n\tadd\t%%sp, %%g1, %%sp\n", |
915f619f | 3435 | actual_fsize, actual_fsize, ret); |
ef8200df | 3436 | target_flags |= old_target_epilogue; |
ab835497 | 3437 | } |
e0d80184 DM |
3438 | |
3439 | output_vectors: | |
3440 | sparc_output_deferred_case_vectors (); | |
ab835497 | 3441 | } |
4fb4e4b8 DE |
3442 | \f |
3443 | /* Functions for handling argument passing. | |
3444 | ||
3445 | For v8 the first six args are normally in registers and the rest are | |
3446 | pushed. Any arg that starts within the first 6 words is at least | |
3447 | partially passed in a register unless its data type forbids. | |
3448 | ||
3449 | For v9, the argument registers are laid out as an array of 16 elements | |
3450 | and arguments are added sequentially. The first 6 int args and up to the | |
3451 | first 16 fp args (depending on size) are passed in regs. | |
3452 | ||
3453 | Slot Stack Integral Float Float in structure Double Long Double | |
3454 | ---- ----- -------- ----- ------------------ ------ ----------- | |
3455 | 15 [SP+248] %f31 %f30,%f31 %d30 | |
3456 | 14 [SP+240] %f29 %f28,%f29 %d28 %q28 | |
3457 | 13 [SP+232] %f27 %f26,%f27 %d26 | |
3458 | 12 [SP+224] %f25 %f24,%f25 %d24 %q24 | |
3459 | 11 [SP+216] %f23 %f22,%f23 %d22 | |
3460 | 10 [SP+208] %f21 %f20,%f21 %d20 %q20 | |
3461 | 9 [SP+200] %f19 %f18,%f19 %d18 | |
3462 | 8 [SP+192] %f17 %f16,%f17 %d16 %q16 | |
3463 | 7 [SP+184] %f15 %f14,%f15 %d14 | |
3464 | 6 [SP+176] %f13 %f12,%f13 %d12 %q12 | |
3465 | 5 [SP+168] %o5 %f11 %f10,%f11 %d10 | |
3466 | 4 [SP+160] %o4 %f9 %f8,%f9 %d8 %q8 | |
3467 | 3 [SP+152] %o3 %f7 %f6,%f7 %d6 | |
3468 | 2 [SP+144] %o2 %f5 %f4,%f5 %d4 %q4 | |
3469 | 1 [SP+136] %o1 %f3 %f2,%f3 %d2 | |
3470 | 0 [SP+128] %o0 %f1 %f0,%f1 %d0 %q0 | |
3471 | ||
3472 | Here SP = %sp if -mno-stack-bias or %sp+stack_bias otherwise. | |
3473 | ||
3474 | Integral arguments are always passed as 64 bit quantities appropriately | |
3475 | extended. | |
3476 | ||
3477 | Passing of floating point values is handled as follows. | |
3478 | If a prototype is in scope: | |
3479 | If the value is in a named argument (i.e. not a stdarg function or a | |
3480 | value not part of the `...') then the value is passed in the appropriate | |
3481 | fp reg. | |
3482 | If the value is part of the `...' and is passed in one of the first 6 | |
3483 | slots then the value is passed in the appropriate int reg. | |
3484 | If the value is part of the `...' and is not passed in one of the first 6 | |
3485 | slots then the value is passed in memory. | |
3486 | If a prototype is not in scope: | |
3487 | If the value is one of the first 6 arguments the value is passed in the | |
3488 | appropriate integer reg and the appropriate fp reg. | |
3489 | If the value is not one of the first 6 arguments the value is passed in | |
3490 | the appropriate fp reg and in memory. | |
3491 | */ | |
3492 | ||
3493 | /* Maximum number of int regs for args. */ | |
3494 | #define SPARC_INT_ARG_MAX 6 | |
3495 | /* Maximum number of fp regs for args. */ | |
3496 | #define SPARC_FP_ARG_MAX 16 | |
3497 | ||
3498 | #define ROUND_ADVANCE(SIZE) (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) | |
3499 | ||
3500 | /* Handle the INIT_CUMULATIVE_ARGS macro. | |
3501 | Initialize a variable CUM of type CUMULATIVE_ARGS | |
3502 | for a call to a function whose data type is FNTYPE. | |
3503 | For a library call, FNTYPE is 0. */ | |
3ea1fdd3 | 3504 | |
4fb4e4b8 DE |
3505 | void |
3506 | init_cumulative_args (cum, fntype, libname, indirect) | |
3507 | CUMULATIVE_ARGS *cum; | |
db3d4438 | 3508 | tree fntype; |
88430453 | 3509 | rtx libname ATTRIBUTE_UNUSED; |
db3d4438 | 3510 | int indirect ATTRIBUTE_UNUSED; |
4fb4e4b8 DE |
3511 | { |
3512 | cum->words = 0; | |
3513 | cum->prototype_p = fntype && TYPE_ARG_TYPES (fntype); | |
3514 | cum->libcall_p = fntype == 0; | |
3515 | } | |
61a55e8b | 3516 | |
4fb4e4b8 DE |
3517 | /* Compute the slot number to pass an argument in. |
3518 | Returns the slot number or -1 if passing on the stack. | |
3519 | ||
3520 | CUM is a variable of type CUMULATIVE_ARGS which gives info about | |
3521 | the preceding args and about the function being called. | |
3522 | MODE is the argument's machine mode. | |
3523 | TYPE is the data type of the argument (as a tree). | |
3524 | This is null for libcalls where that information may | |
3525 | not be available. | |
3526 | NAMED is nonzero if this argument is a named parameter | |
3527 | (otherwise it is an extra parameter matching an ellipsis). | |
3528 | INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG. | |
3529 | *PREGNO records the register number to use if scalar type. | |
3530 | *PPADDING records the amount of padding needed in words. */ | |
3531 | ||
3532 | static int | |
3533 | function_arg_slotno (cum, mode, type, named, incoming_p, pregno, ppadding) | |
3534 | const CUMULATIVE_ARGS *cum; | |
3535 | enum machine_mode mode; | |
3536 | tree type; | |
3537 | int named; | |
3538 | int incoming_p; | |
3539 | int *pregno; | |
3540 | int *ppadding; | |
3541 | { | |
3542 | int regbase = (incoming_p | |
3543 | ? SPARC_INCOMING_INT_ARG_FIRST | |
3544 | : SPARC_OUTGOING_INT_ARG_FIRST); | |
3545 | int slotno = cum->words; | |
3546 | int regno; | |
3547 | ||
3548 | *ppadding = 0; | |
3549 | ||
3550 | if (type != 0 && TREE_ADDRESSABLE (type)) | |
3551 | return -1; | |
3552 | if (TARGET_ARCH32 | |
3553 | && type != 0 && mode == BLKmode | |
3554 | && TYPE_ALIGN (type) % PARM_BOUNDARY != 0) | |
3555 | return -1; | |
3556 | ||
3557 | switch (mode) | |
3558 | { | |
3559 | case VOIDmode : | |
3560 | /* MODE is VOIDmode when generating the actual call. | |
3561 | See emit_call_1. */ | |
3562 | return -1; | |
3563 | ||
3564 | case QImode : case CQImode : | |
3565 | case HImode : case CHImode : | |
3566 | case SImode : case CSImode : | |
3567 | case DImode : case CDImode : | |
3568 | if (slotno >= SPARC_INT_ARG_MAX) | |
3569 | return -1; | |
3570 | regno = regbase + slotno; | |
3571 | break; | |
3572 | ||
3573 | case SFmode : case SCmode : | |
3574 | case DFmode : case DCmode : | |
3575 | case TFmode : case TCmode : | |
3576 | if (TARGET_ARCH32) | |
3577 | { | |
3578 | if (slotno >= SPARC_INT_ARG_MAX) | |
3579 | return -1; | |
3580 | regno = regbase + slotno; | |
3581 | } | |
3582 | else | |
3583 | { | |
3584 | if ((mode == TFmode || mode == TCmode) | |
3585 | && (slotno & 1) != 0) | |
3586 | slotno++, *ppadding = 1; | |
3587 | if (TARGET_FPU && named) | |
3588 | { | |
3589 | if (slotno >= SPARC_FP_ARG_MAX) | |
82d6b402 | 3590 | return -1; |
4fb4e4b8 DE |
3591 | regno = SPARC_FP_ARG_FIRST + slotno * 2; |
3592 | if (mode == SFmode) | |
3593 | regno++; | |
3594 | } | |
3595 | else | |
3596 | { | |
3597 | if (slotno >= SPARC_INT_ARG_MAX) | |
3598 | return -1; | |
3599 | regno = regbase + slotno; | |
3600 | } | |
3601 | } | |
3602 | break; | |
3603 | ||
3604 | case BLKmode : | |
3605 | /* For sparc64, objects requiring 16 byte alignment get it. */ | |
3606 | if (TARGET_ARCH64) | |
3607 | { | |
3608 | if (type && TYPE_ALIGN (type) == 128 && (slotno & 1) != 0) | |
3609 | slotno++, *ppadding = 1; | |
3610 | } | |
3611 | ||
3612 | if (TARGET_ARCH32 | |
5e9defae | 3613 | || (type && TREE_CODE (type) == UNION_TYPE)) |
4fb4e4b8 DE |
3614 | { |
3615 | if (slotno >= SPARC_INT_ARG_MAX) | |
3616 | return -1; | |
3617 | regno = regbase + slotno; | |
3618 | } | |
3619 | else | |
3620 | { | |
3621 | tree field; | |
3622 | int intregs_p = 0, fpregs_p = 0; | |
3623 | /* The ABI obviously doesn't specify how packed | |
3624 | structures are passed. These are defined to be passed | |
3625 | in int regs if possible, otherwise memory. */ | |
3626 | int packed_p = 0; | |
3627 | ||
3628 | /* First see what kinds of registers we need. */ | |
3629 | for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field)) | |
3630 | { | |
3631 | if (TREE_CODE (field) == FIELD_DECL) | |
3632 | { | |
3633 | if (TREE_CODE (TREE_TYPE (field)) == REAL_TYPE | |
3634 | && TARGET_FPU) | |
3635 | fpregs_p = 1; | |
3636 | else | |
3637 | intregs_p = 1; | |
3638 | if (DECL_PACKED (field)) | |
3639 | packed_p = 1; | |
3640 | } | |
3641 | } | |
3642 | if (packed_p || !named) | |
3643 | fpregs_p = 0, intregs_p = 1; | |
3644 | ||
3645 | /* If all arg slots are filled, then must pass on stack. */ | |
3646 | if (fpregs_p && slotno >= SPARC_FP_ARG_MAX) | |
3647 | return -1; | |
3648 | /* If there are only int args and all int arg slots are filled, | |
3649 | then must pass on stack. */ | |
3650 | if (!fpregs_p && intregs_p && slotno >= SPARC_INT_ARG_MAX) | |
3651 | return -1; | |
3652 | /* Note that even if all int arg slots are filled, fp members may | |
3653 | still be passed in regs if such regs are available. | |
3654 | *PREGNO isn't set because there may be more than one, it's up | |
3655 | to the caller to compute them. */ | |
3656 | return slotno; | |
3657 | } | |
3658 | break; | |
3659 | ||
3660 | default : | |
3661 | abort (); | |
3662 | } | |
3663 | ||
3664 | *pregno = regno; | |
3665 | return slotno; | |
3666 | } | |
3667 | ||
82d6b402 RH |
3668 | /* Handle recursive register counting for structure field layout. */ |
3669 | ||
3670 | struct function_arg_record_value_parms | |
3671 | { | |
3672 | rtx ret; | |
3673 | int slotno, named, regbase; | |
3674 | int nregs, intoffset; | |
3675 | }; | |
3676 | ||
2a01c939 DM |
3677 | static void function_arg_record_value_3 |
3678 | PROTO((int, struct function_arg_record_value_parms *)); | |
3679 | static void function_arg_record_value_2 | |
3680 | PROTO((tree, int, struct function_arg_record_value_parms *)); | |
b1474bb7 KG |
3681 | static void function_arg_record_value_1 |
3682 | PROTO((tree, int, struct function_arg_record_value_parms *)); | |
2a01c939 DM |
3683 | static rtx function_arg_record_value |
3684 | PROTO((tree, enum machine_mode, int, int, int)); | |
3685 | ||
82d6b402 RH |
3686 | static void |
3687 | function_arg_record_value_1 (type, startbitpos, parms) | |
3688 | tree type; | |
3689 | int startbitpos; | |
3690 | struct function_arg_record_value_parms *parms; | |
3691 | { | |
3692 | tree field; | |
3693 | ||
3694 | /* The ABI obviously doesn't specify how packed structures are | |
3695 | passed. These are defined to be passed in int regs if possible, | |
3696 | otherwise memory. */ | |
3697 | int packed_p = 0; | |
3698 | ||
3699 | /* We need to compute how many registers are needed so we can | |
3700 | allocate the PARALLEL but before we can do that we need to know | |
3701 | whether there are any packed fields. If there are, int regs are | |
3702 | used regardless of whether there are fp values present. */ | |
3703 | for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field)) | |
3704 | { | |
3705 | if (TREE_CODE (field) == FIELD_DECL && DECL_PACKED (field)) | |
3706 | { | |
3707 | packed_p = 1; | |
3708 | break; | |
3709 | } | |
3710 | } | |
3711 | ||
3712 | /* Compute how many registers we need. */ | |
3713 | for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field)) | |
3714 | { | |
3715 | if (TREE_CODE (field) == FIELD_DECL) | |
3716 | { | |
3717 | int bitpos = startbitpos; | |
3718 | if (DECL_FIELD_BITPOS (field)) | |
3719 | bitpos += TREE_INT_CST_LOW (DECL_FIELD_BITPOS (field)); | |
3720 | /* ??? FIXME: else assume zero offset. */ | |
3721 | ||
3722 | if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE) | |
3723 | { | |
3724 | function_arg_record_value_1 (TREE_TYPE (field), bitpos, parms); | |
3725 | } | |
3726 | else if (TREE_CODE (TREE_TYPE (field)) == REAL_TYPE | |
3727 | && TARGET_FPU | |
3728 | && ! packed_p | |
3729 | && parms->named) | |
3730 | { | |
3731 | if (parms->intoffset != -1) | |
3732 | { | |
3733 | int intslots, this_slotno; | |
3734 | ||
3735 | intslots = (bitpos - parms->intoffset + BITS_PER_WORD - 1) | |
3736 | / BITS_PER_WORD; | |
3737 | this_slotno = parms->slotno + parms->intoffset | |
3738 | / BITS_PER_WORD; | |
3739 | ||
3740 | intslots = MIN (intslots, SPARC_INT_ARG_MAX - this_slotno); | |
3741 | intslots = MAX (intslots, 0); | |
3742 | parms->nregs += intslots; | |
3743 | parms->intoffset = -1; | |
3744 | } | |
3745 | ||
3746 | /* There's no need to check this_slotno < SPARC_FP_ARG MAX. | |
3747 | If it wasn't true we wouldn't be here. */ | |
3748 | parms->nregs += 1; | |
3749 | } | |
3750 | else | |
3751 | { | |
3752 | if (parms->intoffset == -1) | |
3753 | parms->intoffset = bitpos; | |
3754 | } | |
3755 | } | |
3756 | } | |
3757 | } | |
3758 | ||
3759 | /* Handle recursive structure field register assignment. */ | |
3760 | ||
3761 | static void | |
3762 | function_arg_record_value_3 (bitpos, parms) | |
3763 | int bitpos; | |
3764 | struct function_arg_record_value_parms *parms; | |
3765 | { | |
3766 | enum machine_mode mode; | |
3767 | int regno, this_slotno, intslots, intoffset; | |
3768 | rtx reg; | |
3769 | ||
3770 | if (parms->intoffset == -1) | |
3771 | return; | |
3772 | intoffset = parms->intoffset; | |
3773 | parms->intoffset = -1; | |
3774 | ||
3775 | intslots = (bitpos - intoffset + BITS_PER_WORD - 1) / BITS_PER_WORD; | |
3776 | this_slotno = parms->slotno + intoffset / BITS_PER_WORD; | |
3777 | ||
3778 | intslots = MIN (intslots, SPARC_INT_ARG_MAX - this_slotno); | |
3779 | if (intslots <= 0) | |
3780 | return; | |
3781 | ||
3782 | /* If this is the trailing part of a word, only load that much into | |
3783 | the register. Otherwise load the whole register. Note that in | |
3784 | the latter case we may pick up unwanted bits. It's not a problem | |
3785 | at the moment but may wish to revisit. */ | |
3786 | ||
3787 | if (intoffset % BITS_PER_WORD != 0) | |
3788 | { | |
3789 | mode = mode_for_size (BITS_PER_WORD - intoffset%BITS_PER_WORD, | |
3790 | MODE_INT, 0); | |
3791 | } | |
3792 | else | |
3793 | mode = word_mode; | |
3794 | ||
3795 | intoffset /= BITS_PER_UNIT; | |
3796 | do | |
3797 | { | |
3798 | regno = parms->regbase + this_slotno; | |
254110c2 | 3799 | reg = gen_rtx_REG (mode, regno); |
82d6b402 | 3800 | XVECEXP (parms->ret, 0, parms->nregs) |
254110c2 | 3801 | = gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset)); |
82d6b402 RH |
3802 | |
3803 | this_slotno += 1; | |
3804 | intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1; | |
3805 | parms->nregs += 1; | |
3806 | intslots -= 1; | |
3807 | } | |
3808 | while (intslots > 0); | |
3809 | } | |
3810 | ||
3811 | static void | |
3812 | function_arg_record_value_2 (type, startbitpos, parms) | |
3813 | tree type; | |
3814 | int startbitpos; | |
3815 | struct function_arg_record_value_parms *parms; | |
3816 | { | |
3817 | tree field; | |
3818 | int packed_p = 0; | |
3819 | ||
3820 | for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field)) | |
3821 | { | |
3822 | if (TREE_CODE (field) == FIELD_DECL && DECL_PACKED (field)) | |
3823 | { | |
3824 | packed_p = 1; | |
3825 | break; | |
3826 | } | |
3827 | } | |
3828 | ||
3829 | for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field)) | |
3830 | { | |
3831 | if (TREE_CODE (field) == FIELD_DECL) | |
3832 | { | |
3833 | int bitpos = startbitpos; | |
3834 | if (DECL_FIELD_BITPOS (field)) | |
3835 | bitpos += TREE_INT_CST_LOW (DECL_FIELD_BITPOS (field)); | |
3836 | /* ??? FIXME: else assume zero offset. */ | |
3837 | ||
3838 | if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE) | |
3839 | { | |
3840 | function_arg_record_value_2 (TREE_TYPE (field), bitpos, parms); | |
3841 | } | |
3842 | else if (TREE_CODE (TREE_TYPE (field)) == REAL_TYPE | |
3843 | && TARGET_FPU | |
3844 | && ! packed_p | |
3845 | && parms->named) | |
3846 | { | |
3847 | int this_slotno = parms->slotno + bitpos / BITS_PER_WORD; | |
3848 | rtx reg; | |
3849 | ||
3850 | function_arg_record_value_3 (bitpos, parms); | |
3851 | ||
254110c2 | 3852 | reg = gen_rtx_REG (DECL_MODE (field), |
82d6b402 RH |
3853 | (SPARC_FP_ARG_FIRST + this_slotno * 2 |
3854 | + (DECL_MODE (field) == SFmode | |
3855 | && (bitpos & 32) != 0))); | |
3856 | XVECEXP (parms->ret, 0, parms->nregs) | |
254110c2 | 3857 | = gen_rtx_EXPR_LIST (VOIDmode, reg, |
82d6b402 RH |
3858 | GEN_INT (bitpos / BITS_PER_UNIT)); |
3859 | parms->nregs += 1; | |
3860 | } | |
3861 | else | |
3862 | { | |
3863 | if (parms->intoffset == -1) | |
3864 | parms->intoffset = bitpos; | |
3865 | } | |
3866 | } | |
3867 | } | |
3868 | } | |
3869 | ||
3870 | static rtx | |
1eac9f59 | 3871 | function_arg_record_value (type, mode, slotno, named, regbase) |
82d6b402 | 3872 | tree type; |
1eac9f59 | 3873 | enum machine_mode mode; |
82d6b402 RH |
3874 | int slotno, named, regbase; |
3875 | { | |
3876 | HOST_WIDE_INT typesize = int_size_in_bytes (type); | |
3877 | struct function_arg_record_value_parms parms; | |
3878 | int nregs; | |
3879 | ||
3880 | parms.ret = NULL_RTX; | |
3881 | parms.slotno = slotno; | |
3882 | parms.named = named; | |
3883 | parms.regbase = regbase; | |
3884 | ||
3885 | /* Compute how many registers we need. */ | |
3886 | parms.nregs = 0; | |
3887 | parms.intoffset = 0; | |
3888 | function_arg_record_value_1 (type, 0, &parms); | |
3889 | ||
3890 | if (parms.intoffset != -1) | |
3891 | { | |
3892 | int intslots, this_slotno; | |
3893 | ||
3894 | intslots = (typesize*BITS_PER_UNIT - parms.intoffset + BITS_PER_WORD - 1) | |
3895 | / BITS_PER_WORD; | |
3896 | this_slotno = slotno + parms.intoffset / BITS_PER_WORD; | |
3897 | ||
3898 | intslots = MIN (intslots, SPARC_INT_ARG_MAX - this_slotno); | |
3899 | intslots = MAX (intslots, 0); | |
3900 | ||
3901 | parms.nregs += intslots; | |
3902 | } | |
3903 | nregs = parms.nregs; | |
3904 | ||
3905 | /* Allocate the vector and handle some annoying special cases. */ | |
3906 | if (nregs == 0) | |
3907 | { | |
3908 | /* ??? Empty structure has no value? Duh? */ | |
3909 | if (typesize <= 0) | |
3910 | { | |
3911 | /* Though there's nothing really to store, return a word register | |
3912 | anyway so the rest of gcc doesn't go nuts. Returning a PARALLEL | |
3913 | leads to breakage due to the fact that there are zero bytes to | |
3914 | load. */ | |
1eac9f59 | 3915 | return gen_rtx_REG (mode, regbase); |
82d6b402 RH |
3916 | } |
3917 | else | |
3918 | { | |
3919 | /* ??? C++ has structures with no fields, and yet a size. Give up | |
3920 | for now and pass everything back in integer registers. */ | |
3921 | nregs = (typesize + UNITS_PER_WORD - 1) / UNITS_PER_WORD; | |
3922 | } | |
3923 | if (nregs + slotno > SPARC_INT_ARG_MAX) | |
3924 | nregs = SPARC_INT_ARG_MAX - slotno; | |
3925 | } | |
3926 | if (nregs == 0) | |
9208e4b2 | 3927 | abort (); |
82d6b402 | 3928 | |
1eac9f59 | 3929 | parms.ret = gen_rtx_PARALLEL (mode, rtvec_alloc (nregs)); |
82d6b402 RH |
3930 | |
3931 | /* Fill in the entries. */ | |
3932 | parms.nregs = 0; | |
3933 | parms.intoffset = 0; | |
3934 | function_arg_record_value_2 (type, 0, &parms); | |
3935 | function_arg_record_value_3 (typesize * BITS_PER_UNIT, &parms); | |
3936 | ||
3937 | if (parms.nregs != nregs) | |
3938 | abort (); | |
3939 | ||
3940 | return parms.ret; | |
3941 | } | |
3942 | ||
4fb4e4b8 DE |
3943 | /* Handle the FUNCTION_ARG macro. |
3944 | Determine where to put an argument to a function. | |
3945 | Value is zero to push the argument on the stack, | |
3946 | or a hard register in which to store the argument. | |
3947 | ||
3948 | CUM is a variable of type CUMULATIVE_ARGS which gives info about | |
3949 | the preceding args and about the function being called. | |
3950 | MODE is the argument's machine mode. | |
3951 | TYPE is the data type of the argument (as a tree). | |
3952 | This is null for libcalls where that information may | |
3953 | not be available. | |
3954 | NAMED is nonzero if this argument is a named parameter | |
3955 | (otherwise it is an extra parameter matching an ellipsis). | |
3956 | INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG. */ | |
61a55e8b DE |
3957 | |
3958 | rtx | |
4fb4e4b8 DE |
3959 | function_arg (cum, mode, type, named, incoming_p) |
3960 | const CUMULATIVE_ARGS *cum; | |
3961 | enum machine_mode mode; | |
3962 | tree type; | |
3963 | int named; | |
3964 | int incoming_p; | |
61a55e8b | 3965 | { |
4fb4e4b8 DE |
3966 | int regbase = (incoming_p |
3967 | ? SPARC_INCOMING_INT_ARG_FIRST | |
3968 | : SPARC_OUTGOING_INT_ARG_FIRST); | |
3969 | int slotno, regno, padding; | |
3970 | rtx reg; | |
3971 | ||
3972 | slotno = function_arg_slotno (cum, mode, type, named, incoming_p, | |
3973 | ®no, &padding); | |
3974 | ||
3975 | if (slotno == -1) | |
3976 | return 0; | |
3977 | ||
3978 | if (TARGET_ARCH32) | |
3979 | { | |
254110c2 | 3980 | reg = gen_rtx_REG (mode, regno); |
4fb4e4b8 DE |
3981 | return reg; |
3982 | } | |
3983 | ||
3984 | /* v9 fp args in reg slots beyond the int reg slots get passed in regs | |
3985 | but also have the slot allocated for them. | |
3986 | If no prototype is in scope fp values in register slots get passed | |
3987 | in two places, either fp regs and int regs or fp regs and memory. */ | |
3988 | if ((GET_MODE_CLASS (mode) == MODE_FLOAT | |
3989 | || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT) | |
3990 | && SPARC_FP_REG_P (regno)) | |
3991 | { | |
254110c2 | 3992 | reg = gen_rtx_REG (mode, regno); |
4fb4e4b8 DE |
3993 | if (cum->prototype_p || cum->libcall_p) |
3994 | { | |
3995 | /* "* 2" because fp reg numbers are recorded in 4 byte | |
3996 | quantities. */ | |
82d6b402 | 3997 | #if 0 |
4fb4e4b8 DE |
3998 | /* ??? This will cause the value to be passed in the fp reg and |
3999 | in the stack. When a prototype exists we want to pass the | |
4000 | value in the reg but reserve space on the stack. That's an | |
956d6950 | 4001 | optimization, and is deferred [for a bit]. */ |
4fb4e4b8 | 4002 | if ((regno - SPARC_FP_ARG_FIRST) >= SPARC_INT_ARG_MAX * 2) |
254110c2 | 4003 | return gen_rtx_PARALLEL (mode, |
4fb4e4b8 | 4004 | gen_rtvec (2, |
254110c2 | 4005 | gen_rtx_EXPR_LIST (VOIDmode, |
4fb4e4b8 | 4006 | NULL_RTX, const0_rtx), |
254110c2 | 4007 | gen_rtx_EXPR_LIST (VOIDmode, |
4fb4e4b8 DE |
4008 | reg, const0_rtx))); |
4009 | else | |
82d6b402 RH |
4010 | #else |
4011 | /* ??? It seems that passing back a register even when past | |
4012 | the area declared by REG_PARM_STACK_SPACE will allocate | |
4013 | space appropriately, and will not copy the data onto the | |
4014 | stack, exactly as we desire. | |
4015 | ||
4016 | This is due to locate_and_pad_parm being called in | |
4017 | expand_call whenever reg_parm_stack_space > 0, which | |
4018 | while benefical to our example here, would seem to be | |
4019 | in error from what had been intended. Ho hum... -- r~ */ | |
4020 | #endif | |
4fb4e4b8 DE |
4021 | return reg; |
4022 | } | |
4023 | else | |
4024 | { | |
82d6b402 RH |
4025 | rtx v0, v1; |
4026 | ||
4fb4e4b8 DE |
4027 | if ((regno - SPARC_FP_ARG_FIRST) < SPARC_INT_ARG_MAX * 2) |
4028 | { | |
82d6b402 RH |
4029 | int intreg; |
4030 | ||
4031 | /* On incoming, we don't need to know that the value | |
4032 | is passed in %f0 and %i0, and it confuses other parts | |
4033 | causing needless spillage even on the simplest cases. */ | |
4034 | if (incoming_p) | |
4035 | return reg; | |
4036 | ||
4037 | intreg = (SPARC_OUTGOING_INT_ARG_FIRST | |
4038 | + (regno - SPARC_FP_ARG_FIRST) / 2); | |
4039 | ||
4040 | v0 = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx); | |
4041 | v1 = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_REG (mode, intreg), | |
4042 | const0_rtx); | |
4043 | return gen_rtx_PARALLEL (mode, gen_rtvec (2, v0, v1)); | |
4fb4e4b8 DE |
4044 | } |
4045 | else | |
82d6b402 RH |
4046 | { |
4047 | v0 = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx); | |
4048 | v1 = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx); | |
4049 | return gen_rtx_PARALLEL (mode, gen_rtvec (2, v0, v1)); | |
4050 | } | |
4fb4e4b8 DE |
4051 | } |
4052 | } | |
4053 | else if (type && TREE_CODE (type) == RECORD_TYPE) | |
4054 | { | |
4055 | /* Structures up to 16 bytes in size are passed in arg slots on the | |
4056 | stack and are promoted to registers where possible. */ | |
4fb4e4b8 DE |
4057 | |
4058 | if (int_size_in_bytes (type) > 16) | |
4059 | abort (); /* shouldn't get here */ | |
4060 | ||
1eac9f59 | 4061 | return function_arg_record_value (type, mode, slotno, named, regbase); |
4fb4e4b8 DE |
4062 | } |
4063 | else if (type && TREE_CODE (type) == UNION_TYPE) | |
4064 | { | |
4065 | enum machine_mode mode; | |
4066 | int bytes = int_size_in_bytes (type); | |
4067 | ||
4068 | if (bytes > 16) | |
4069 | abort (); | |
4070 | ||
4071 | mode = mode_for_size (bytes * BITS_PER_UNIT, MODE_INT, 0); | |
254110c2 | 4072 | reg = gen_rtx_REG (mode, regno); |
4fb4e4b8 | 4073 | } |
a7acd911 | 4074 | else |
4fb4e4b8 DE |
4075 | { |
4076 | /* Scalar or complex int. */ | |
254110c2 | 4077 | reg = gen_rtx_REG (mode, regno); |
4fb4e4b8 DE |
4078 | } |
4079 | ||
4080 | return reg; | |
4081 | } | |
a7acd911 | 4082 | |
4fb4e4b8 DE |
4083 | /* Handle the FUNCTION_ARG_PARTIAL_NREGS macro. |
4084 | For an arg passed partly in registers and partly in memory, | |
4085 | this is the number of registers used. | |
4086 | For args passed entirely in registers or entirely in memory, zero. | |
61a55e8b | 4087 | |
4fb4e4b8 DE |
4088 | Any arg that starts in the first 6 regs but won't entirely fit in them |
4089 | needs partial registers on v8. On v9, structures with integer | |
4090 | values in arg slots 5,6 will be passed in %o5 and SP+176, and complex fp | |
4091 | values that begin in the last fp reg [where "last fp reg" varies with the | |
4092 | mode] will be split between that reg and memory. */ | |
61a55e8b | 4093 | |
4fb4e4b8 DE |
4094 | int |
4095 | function_arg_partial_nregs (cum, mode, type, named) | |
4096 | const CUMULATIVE_ARGS *cum; | |
4097 | enum machine_mode mode; | |
4098 | tree type; | |
4099 | int named; | |
4100 | { | |
4101 | int slotno, regno, padding; | |
61a55e8b | 4102 | |
4fb4e4b8 DE |
4103 | /* We pass 0 for incoming_p here, it doesn't matter. */ |
4104 | slotno = function_arg_slotno (cum, mode, type, named, 0, ®no, &padding); | |
4105 | ||
4106 | if (slotno == -1) | |
4107 | return 0; | |
4108 | ||
4109 | if (TARGET_ARCH32) | |
bf62bbf1 | 4110 | { |
4fb4e4b8 DE |
4111 | if ((slotno + (mode == BLKmode |
4112 | ? ROUND_ADVANCE (int_size_in_bytes (type)) | |
4113 | : ROUND_ADVANCE (GET_MODE_SIZE (mode)))) | |
4114 | > NPARM_REGS (SImode)) | |
4115 | return NPARM_REGS (SImode) - slotno; | |
4116 | return 0; | |
4117 | } | |
4118 | else | |
4119 | { | |
4120 | if (type && AGGREGATE_TYPE_P (type)) | |
4121 | { | |
4122 | int size = int_size_in_bytes (type); | |
4123 | int align = TYPE_ALIGN (type); | |
bf62bbf1 | 4124 | |
4fb4e4b8 DE |
4125 | if (align == 16) |
4126 | slotno += slotno & 1; | |
4127 | if (size > 8 && size <= 16 | |
4128 | && slotno == SPARC_INT_ARG_MAX - 1) | |
4129 | return 1; | |
4130 | } | |
4131 | else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_INT | |
4132 | || (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT | |
4133 | && ! TARGET_FPU)) | |
4134 | { | |
4135 | if (GET_MODE_ALIGNMENT (mode) == 128) | |
4136 | { | |
4137 | slotno += slotno & 1; | |
4138 | if (slotno == SPARC_INT_ARG_MAX - 2) | |
4139 | return 1; | |
4140 | } | |
4141 | else | |
4142 | { | |
4143 | if (slotno == SPARC_INT_ARG_MAX - 1) | |
4144 | return 1; | |
4145 | } | |
4146 | } | |
4147 | else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT) | |
4148 | { | |
4149 | if (GET_MODE_ALIGNMENT (mode) == 128) | |
4150 | slotno += slotno & 1; | |
4151 | if ((slotno + GET_MODE_SIZE (mode) / UNITS_PER_WORD) | |
4152 | > SPARC_FP_ARG_MAX) | |
4153 | return 1; | |
4154 | } | |
4155 | return 0; | |
bf62bbf1 | 4156 | } |
4fb4e4b8 | 4157 | } |
61a55e8b | 4158 | |
4fb4e4b8 DE |
4159 | /* Handle the FUNCTION_ARG_PASS_BY_REFERENCE macro. |
4160 | !v9: The SPARC ABI stipulates passing struct arguments (of any size) and | |
4161 | quad-precision floats by invisible reference. | |
82d6b402 | 4162 | v9: Aggregates greater than 16 bytes are passed by reference. |
4fb4e4b8 DE |
4163 | For Pascal, also pass arrays by reference. */ |
4164 | ||
4165 | int | |
4166 | function_arg_pass_by_reference (cum, mode, type, named) | |
db3d4438 | 4167 | const CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED; |
4fb4e4b8 DE |
4168 | enum machine_mode mode; |
4169 | tree type; | |
db3d4438 | 4170 | int named ATTRIBUTE_UNUSED; |
4fb4e4b8 DE |
4171 | { |
4172 | if (TARGET_ARCH32) | |
eadceb59 | 4173 | { |
5e9defae | 4174 | return ((type && AGGREGATE_TYPE_P (type)) |
4fb4e4b8 DE |
4175 | || mode == TFmode || mode == TCmode); |
4176 | } | |
4177 | else | |
4178 | { | |
4179 | return ((type && TREE_CODE (type) == ARRAY_TYPE) | |
82d6b402 RH |
4180 | /* Consider complex values as aggregates, so care for TCmode. */ |
4181 | || GET_MODE_SIZE (mode) > 16 | |
4fb4e4b8 DE |
4182 | || (type && AGGREGATE_TYPE_P (type) |
4183 | && int_size_in_bytes (type) > 16)); | |
4184 | } | |
4185 | } | |
4186 | ||
4187 | /* Handle the FUNCTION_ARG_ADVANCE macro. | |
4188 | Update the data in CUM to advance over an argument | |
4189 | of mode MODE and data type TYPE. | |
4190 | TYPE is null for libcalls where that information may not be available. */ | |
4191 | ||
4192 | void | |
4193 | function_arg_advance (cum, mode, type, named) | |
4194 | CUMULATIVE_ARGS *cum; | |
4195 | enum machine_mode mode; | |
4196 | tree type; | |
4197 | int named; | |
4198 | { | |
4199 | int slotno, regno, padding; | |
4200 | ||
4201 | /* We pass 0 for incoming_p here, it doesn't matter. */ | |
4202 | slotno = function_arg_slotno (cum, mode, type, named, 0, ®no, &padding); | |
4203 | ||
4204 | /* If register required leading padding, add it. */ | |
4205 | if (slotno != -1) | |
4206 | cum->words += padding; | |
eadceb59 | 4207 | |
4fb4e4b8 DE |
4208 | if (TARGET_ARCH32) |
4209 | { | |
4210 | cum->words += (mode != BLKmode | |
4211 | ? ROUND_ADVANCE (GET_MODE_SIZE (mode)) | |
4212 | : ROUND_ADVANCE (int_size_in_bytes (type))); | |
4213 | } | |
4214 | else | |
4215 | { | |
4216 | if (type && AGGREGATE_TYPE_P (type)) | |
4217 | { | |
4218 | int size = int_size_in_bytes (type); | |
4219 | ||
4220 | if (size <= 8) | |
4221 | ++cum->words; | |
4222 | else if (size <= 16) | |
4223 | cum->words += 2; | |
4224 | else /* passed by reference */ | |
4225 | ++cum->words; | |
4226 | } | |
4227 | else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_INT) | |
4228 | { | |
4229 | cum->words += 2; | |
4230 | } | |
4231 | else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT) | |
4232 | { | |
4233 | cum->words += GET_MODE_SIZE (mode) / UNITS_PER_WORD; | |
4234 | } | |
4235 | else | |
4236 | { | |
4237 | cum->words += (mode != BLKmode | |
4238 | ? ROUND_ADVANCE (GET_MODE_SIZE (mode)) | |
4239 | : ROUND_ADVANCE (int_size_in_bytes (type))); | |
4240 | } | |
eadceb59 | 4241 | } |
4fb4e4b8 | 4242 | } |
eadceb59 | 4243 | |
4fb4e4b8 DE |
4244 | /* Handle the FUNCTION_ARG_PADDING macro. |
4245 | For the 64 bit ABI structs are always stored left shifted in their | |
4246 | argument slot. */ | |
4247 | ||
4248 | enum direction | |
4249 | function_arg_padding (mode, type) | |
4250 | enum machine_mode mode; | |
4251 | tree type; | |
4252 | { | |
c85f7c16 JL |
4253 | if (TARGET_ARCH64 && type != 0 && AGGREGATE_TYPE_P (type)) |
4254 | return upward; | |
61a55e8b | 4255 | |
4fb4e4b8 DE |
4256 | /* This is the default definition. */ |
4257 | return (! BYTES_BIG_ENDIAN | |
4258 | ? upward | |
4259 | : ((mode == BLKmode | |
4260 | ? (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST | |
4261 | && int_size_in_bytes (type) < (PARM_BOUNDARY / BITS_PER_UNIT)) | |
4262 | : GET_MODE_BITSIZE (mode) < PARM_BOUNDARY) | |
4263 | ? downward : upward)); | |
61a55e8b | 4264 | } |
82d6b402 RH |
4265 | |
4266 | /* Handle FUNCTION_VALUE, FUNCTION_OUTGOING_VALUE, and LIBCALL_VALUE macros. | |
4267 | For v9, function return values are subject to the same rules as arguments, | |
4268 | except that up to 32-bytes may be returned in registers. */ | |
4269 | ||
4270 | rtx | |
4271 | function_value (type, mode, incoming_p) | |
4272 | tree type; | |
4273 | enum machine_mode mode; | |
4274 | int incoming_p; | |
4275 | { | |
4276 | int regno; | |
4277 | int regbase = (incoming_p | |
4278 | ? SPARC_OUTGOING_INT_ARG_FIRST | |
4279 | : SPARC_INCOMING_INT_ARG_FIRST); | |
4280 | ||
4281 | if (TARGET_ARCH64 && type) | |
4282 | { | |
4283 | if (TREE_CODE (type) == RECORD_TYPE) | |
4284 | { | |
4285 | /* Structures up to 32 bytes in size are passed in registers, | |
4286 | promoted to fp registers where possible. */ | |
4287 | ||
4288 | if (int_size_in_bytes (type) > 32) | |
4289 | abort (); /* shouldn't get here */ | |
4290 | ||
1eac9f59 | 4291 | return function_arg_record_value (type, mode, 0, 1, regbase); |
82d6b402 RH |
4292 | } |
4293 | else if (TREE_CODE (type) == UNION_TYPE) | |
4294 | { | |
4295 | int bytes = int_size_in_bytes (type); | |
4296 | ||
4297 | if (bytes > 32) | |
4298 | abort (); | |
4299 | ||
4300 | mode = mode_for_size (bytes * BITS_PER_UNIT, MODE_INT, 0); | |
4301 | } | |
4302 | } | |
3c6088d2 JJ |
4303 | |
4304 | if (TARGET_ARCH64 | |
4305 | && GET_MODE_CLASS (mode) == MODE_INT | |
4306 | && GET_MODE_SIZE (mode) < UNITS_PER_WORD | |
4307 | && type && TREE_CODE (type) != UNION_TYPE) | |
4308 | mode = DImode; | |
82d6b402 RH |
4309 | |
4310 | if (incoming_p) | |
4311 | regno = BASE_RETURN_VALUE_REG (mode); | |
4312 | else | |
4313 | regno = BASE_OUTGOING_VALUE_REG (mode); | |
4314 | ||
254110c2 | 4315 | return gen_rtx_REG (mode, regno); |
82d6b402 RH |
4316 | } |
4317 | ||
648d2ffc RH |
4318 | /* Do what is necessary for `va_start'. We look at the current function |
4319 | to determine if stdarg or varargs is used and return the address of | |
4320 | the first unnamed parameter. */ | |
3ea1fdd3 JW |
4321 | |
4322 | rtx | |
648d2ffc | 4323 | sparc_builtin_saveregs () |
3ea1fdd3 | 4324 | { |
4fb4e4b8 | 4325 | int first_reg = current_function_args_info.words; |
3ea1fdd3 JW |
4326 | rtx address; |
4327 | int regno; | |
4328 | ||
4fb4e4b8 | 4329 | for (regno = first_reg; regno < NPARM_REGS (word_mode); regno++) |
254110c2 DM |
4330 | emit_move_insn (gen_rtx_MEM (word_mode, |
4331 | gen_rtx_PLUS (Pmode, | |
3ea1fdd3 JW |
4332 | frame_pointer_rtx, |
4333 | GEN_INT (STACK_POINTER_OFFSET | |
4334 | + UNITS_PER_WORD * regno))), | |
254110c2 | 4335 | gen_rtx_REG (word_mode, |
4fb4e4b8 | 4336 | BASE_INCOMING_ARG_REG (word_mode) + regno)); |
3ea1fdd3 | 4337 | |
254110c2 | 4338 | address = gen_rtx_PLUS (Pmode, |
3ea1fdd3 JW |
4339 | frame_pointer_rtx, |
4340 | GEN_INT (STACK_POINTER_OFFSET | |
4341 | + UNITS_PER_WORD * first_reg)); | |
4342 | ||
7d384cc0 | 4343 | if (current_function_check_memory_usage |
4fb4e4b8 | 4344 | && first_reg < NPARM_REGS (word_mode)) |
eadceb59 RK |
4345 | emit_library_call (chkr_set_right_libfunc, 1, VOIDmode, 3, |
4346 | address, ptr_mode, | |
4347 | GEN_INT (UNITS_PER_WORD | |
4fb4e4b8 | 4348 | * (NPARM_REGS (word_mode) - first_reg)), |
956d6950 JL |
4349 | TYPE_MODE (sizetype), GEN_INT (MEMORY_USE_RW), |
4350 | TYPE_MODE (integer_type_node)); | |
eadceb59 | 4351 | |
3ea1fdd3 JW |
4352 | return address; |
4353 | } | |
a8b2c8a1 RH |
4354 | |
4355 | /* Implement `va_start' for varargs and stdarg. */ | |
4356 | ||
4357 | void | |
4358 | sparc_va_start (stdarg_p, valist, nextarg) | |
4359 | int stdarg_p ATTRIBUTE_UNUSED; | |
4360 | tree valist; | |
4361 | rtx nextarg; | |
4362 | { | |
4363 | nextarg = expand_builtin_saveregs (); | |
4364 | std_expand_builtin_va_start (1, valist, nextarg); | |
4365 | } | |
4366 | ||
4367 | /* Implement `va_arg'. */ | |
4368 | ||
4369 | rtx | |
4370 | sparc_va_arg (valist, type) | |
4371 | tree valist, type; | |
4372 | { | |
4373 | HOST_WIDE_INT size, rsize, align; | |
da09e317 | 4374 | tree addr, incr; |
a8b2c8a1 RH |
4375 | rtx addr_rtx; |
4376 | int indirect = 0; | |
4377 | ||
4378 | /* Round up sizeof(type) to a word. */ | |
4379 | size = int_size_in_bytes (type); | |
4380 | rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD; | |
4381 | align = 0; | |
4382 | ||
4383 | if (TARGET_ARCH64) | |
4384 | { | |
4385 | if (TYPE_ALIGN (type) >= 2 * BITS_PER_WORD) | |
4386 | align = 2 * UNITS_PER_WORD; | |
4387 | ||
f34e52f7 | 4388 | if (AGGREGATE_TYPE_P (type)) |
a8b2c8a1 | 4389 | { |
f34e52f7 JJ |
4390 | if (size > 16) |
4391 | { | |
4392 | indirect = 1; | |
4393 | size = rsize = UNITS_PER_WORD; | |
4394 | } | |
4395 | else | |
4396 | size = rsize; | |
a8b2c8a1 RH |
4397 | } |
4398 | } | |
4399 | else | |
4400 | { | |
4401 | if (AGGREGATE_TYPE_P (type) | |
4402 | || TYPE_MODE (type) == TFmode | |
4403 | || TYPE_MODE (type) == TCmode) | |
4404 | { | |
4405 | indirect = 1; | |
4406 | size = rsize = UNITS_PER_WORD; | |
4407 | } | |
4408 | else | |
4409 | { | |
4410 | /* ??? The old va-sparc.h implementation, for 8 byte objects | |
4411 | copied stuff to a temporary -- I don't see that that | |
4412 | provides any more alignment than the stack slot did. */ | |
4413 | } | |
4414 | } | |
4415 | ||
4416 | incr = valist; | |
4417 | if (align) | |
4418 | { | |
4419 | incr = fold (build (PLUS_EXPR, ptr_type_node, incr, | |
4420 | build_int_2 (align - 1, 0))); | |
4421 | incr = fold (build (BIT_AND_EXPR, ptr_type_node, incr, | |
4422 | build_int_2 (-align, -1))); | |
4423 | } | |
4424 | ||
4425 | addr = incr = save_expr (incr); | |
4426 | if (BYTES_BIG_ENDIAN && size < rsize) | |
4427 | { | |
4428 | addr = fold (build (PLUS_EXPR, ptr_type_node, incr, | |
4429 | build_int_2 (rsize - size, 0))); | |
4430 | } | |
4431 | incr = fold (build (PLUS_EXPR, ptr_type_node, incr, | |
4432 | build_int_2 (rsize, 0))); | |
4433 | ||
4434 | incr = build (MODIFY_EXPR, ptr_type_node, valist, incr); | |
4435 | TREE_SIDE_EFFECTS (incr) = 1; | |
4436 | expand_expr (incr, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
4437 | ||
4438 | addr_rtx = expand_expr (addr, NULL, Pmode, EXPAND_NORMAL); | |
4439 | ||
4440 | if (indirect) | |
4441 | { | |
4442 | addr_rtx = force_reg (Pmode, addr_rtx); | |
4443 | addr_rtx = gen_rtx_MEM (Pmode, addr_rtx); | |
4444 | MEM_ALIAS_SET (addr_rtx) = get_varargs_alias_set (); | |
4445 | } | |
4446 | ||
4447 | return addr_rtx; | |
4448 | } | |
ab835497 RK |
4449 | \f |
4450 | /* Return the string to output a conditional branch to LABEL, which is | |
c4ce6853 DE |
4451 | the operand number of the label. OP is the conditional expression. |
4452 | XEXP (OP, 0) is assumed to be a condition code register (integer or | |
4453 | floating point) and its mode specifies what kind of comparison we made. | |
61a55e8b | 4454 | |
ab835497 RK |
4455 | REVERSED is non-zero if we should reverse the sense of the comparison. |
4456 | ||
4457 | ANNUL is non-zero if we should generate an annulling branch. | |
4458 | ||
c6b0465b JC |
4459 | NOOP is non-zero if we have to follow this branch by a noop. |
4460 | ||
4461 | INSN, if set, is the insn. */ | |
ab835497 RK |
4462 | |
4463 | char * | |
c6b0465b | 4464 | output_cbranch (op, label, reversed, annul, noop, insn) |
c4ce6853 | 4465 | rtx op; |
ab835497 RK |
4466 | int label; |
4467 | int reversed, annul, noop; | |
c6b0465b | 4468 | rtx insn; |
ab835497 | 4469 | { |
e0d80184 | 4470 | static char string[32]; |
ab835497 | 4471 | enum rtx_code code = GET_CODE (op); |
c4ce6853 DE |
4472 | rtx cc_reg = XEXP (op, 0); |
4473 | enum machine_mode mode = GET_MODE (cc_reg); | |
e0d80184 DM |
4474 | static char v8_labelno[] = "%lX"; |
4475 | static char v9_icc_labelno[] = "%%icc, %lX"; | |
4476 | static char v9_xcc_labelno[] = "%%xcc, %lX"; | |
4477 | static char v9_fcc_labelno[] = "%%fccX, %lY"; | |
61a55e8b | 4478 | char *labelno; |
e0d80184 | 4479 | int labeloff, spaces = 8; |
61a55e8b DE |
4480 | |
4481 | /* ??? !v9: FP branches cannot be preceded by another floating point insn. | |
ab835497 RK |
4482 | Because there is currently no concept of pre-delay slots, we can fix |
4483 | this only by always emitting a nop before a floating point branch. */ | |
4484 | ||
61a55e8b | 4485 | if ((mode == CCFPmode || mode == CCFPEmode) && ! TARGET_V9) |
ab835497 | 4486 | strcpy (string, "nop\n\t"); |
61a55e8b DE |
4487 | else |
4488 | string[0] = '\0'; | |
ab835497 RK |
4489 | |
4490 | /* If not floating-point or if EQ or NE, we can just reverse the code. */ | |
4d449554 JW |
4491 | if (reversed |
4492 | && ((mode != CCFPmode && mode != CCFPEmode) || code == EQ || code == NE)) | |
ab835497 RK |
4493 | code = reverse_condition (code), reversed = 0; |
4494 | ||
4495 | /* Start by writing the branch condition. */ | |
4496 | switch (code) | |
4497 | { | |
4498 | case NE: | |
4d449554 | 4499 | if (mode == CCFPmode || mode == CCFPEmode) |
e0d80184 DM |
4500 | { |
4501 | strcat (string, "fbne"); | |
4502 | spaces -= 4; | |
4503 | } | |
ab835497 | 4504 | else |
e0d80184 DM |
4505 | { |
4506 | strcpy (string, "bne"); | |
4507 | spaces -= 3; | |
4508 | } | |
ab835497 RK |
4509 | break; |
4510 | ||
4511 | case EQ: | |
4d449554 | 4512 | if (mode == CCFPmode || mode == CCFPEmode) |
e0d80184 DM |
4513 | { |
4514 | strcat (string, "fbe"); | |
4515 | spaces -= 3; | |
4516 | } | |
ab835497 | 4517 | else |
e0d80184 DM |
4518 | { |
4519 | strcpy (string, "be"); | |
4520 | spaces -= 2; | |
4521 | } | |
ab835497 RK |
4522 | break; |
4523 | ||
4524 | case GE: | |
4d449554 | 4525 | if (mode == CCFPmode || mode == CCFPEmode) |
ab835497 RK |
4526 | { |
4527 | if (reversed) | |
4528 | strcat (string, "fbul"); | |
4529 | else | |
4530 | strcat (string, "fbge"); | |
e0d80184 | 4531 | spaces -= 4; |
ab835497 RK |
4532 | } |
4533 | else if (mode == CC_NOOVmode) | |
e0d80184 DM |
4534 | { |
4535 | strcpy (string, "bpos"); | |
4536 | spaces -= 4; | |
4537 | } | |
ab835497 | 4538 | else |
e0d80184 DM |
4539 | { |
4540 | strcpy (string, "bge"); | |
4541 | spaces -= 3; | |
4542 | } | |
ab835497 RK |
4543 | break; |
4544 | ||
4545 | case GT: | |
4d449554 | 4546 | if (mode == CCFPmode || mode == CCFPEmode) |
ab835497 RK |
4547 | { |
4548 | if (reversed) | |
e0d80184 DM |
4549 | { |
4550 | strcat (string, "fbule"); | |
4551 | spaces -= 5; | |
4552 | } | |
ab835497 | 4553 | else |
e0d80184 DM |
4554 | { |
4555 | strcat (string, "fbg"); | |
4556 | spaces -= 3; | |
4557 | } | |
ab835497 RK |
4558 | } |
4559 | else | |
e0d80184 DM |
4560 | { |
4561 | strcpy (string, "bg"); | |
4562 | spaces -= 2; | |
4563 | } | |
ab835497 RK |
4564 | break; |
4565 | ||
4566 | case LE: | |
4d449554 | 4567 | if (mode == CCFPmode || mode == CCFPEmode) |
ab835497 RK |
4568 | { |
4569 | if (reversed) | |
4570 | strcat (string, "fbug"); | |
4571 | else | |
4572 | strcat (string, "fble"); | |
e0d80184 | 4573 | spaces -= 4; |
ab835497 RK |
4574 | } |
4575 | else | |
e0d80184 DM |
4576 | { |
4577 | strcpy (string, "ble"); | |
4578 | spaces -= 3; | |
4579 | } | |
ab835497 RK |
4580 | break; |
4581 | ||
4582 | case LT: | |
4d449554 | 4583 | if (mode == CCFPmode || mode == CCFPEmode) |
ab835497 RK |
4584 | { |
4585 | if (reversed) | |
e0d80184 DM |
4586 | { |
4587 | strcat (string, "fbuge"); | |
4588 | spaces -= 5; | |
4589 | } | |
ab835497 | 4590 | else |
e0d80184 DM |
4591 | { |
4592 | strcat (string, "fbl"); | |
4593 | spaces -= 3; | |
4594 | } | |
ab835497 RK |
4595 | } |
4596 | else if (mode == CC_NOOVmode) | |
e0d80184 DM |
4597 | { |
4598 | strcpy (string, "bneg"); | |
4599 | spaces -= 4; | |
4600 | } | |
ab835497 | 4601 | else |
e0d80184 DM |
4602 | { |
4603 | strcpy (string, "bl"); | |
4604 | spaces -= 2; | |
4605 | } | |
ab835497 RK |
4606 | break; |
4607 | ||
4608 | case GEU: | |
4609 | strcpy (string, "bgeu"); | |
e0d80184 | 4610 | spaces -= 4; |
ab835497 RK |
4611 | break; |
4612 | ||
4613 | case GTU: | |
4614 | strcpy (string, "bgu"); | |
e0d80184 | 4615 | spaces -= 3; |
ab835497 RK |
4616 | break; |
4617 | ||
4618 | case LEU: | |
4619 | strcpy (string, "bleu"); | |
e0d80184 | 4620 | spaces -= 4; |
ab835497 RK |
4621 | break; |
4622 | ||
4623 | case LTU: | |
4624 | strcpy (string, "blu"); | |
e0d80184 | 4625 | spaces -= 3; |
ab835497 | 4626 | break; |
91a51951 KG |
4627 | |
4628 | default: | |
e0d80184 | 4629 | abort (); |
ab835497 RK |
4630 | } |
4631 | ||
4632 | /* Now add the annulling, the label, and a possible noop. */ | |
4633 | if (annul) | |
e0d80184 DM |
4634 | { |
4635 | strcat (string, ",a"); | |
4636 | spaces -= 2; | |
4637 | } | |
ab835497 | 4638 | |
61a55e8b DE |
4639 | if (! TARGET_V9) |
4640 | { | |
e0d80184 | 4641 | labeloff = 2; |
61a55e8b DE |
4642 | labelno = v8_labelno; |
4643 | } | |
4644 | else | |
4645 | { | |
c6b0465b JC |
4646 | rtx note; |
4647 | ||
4648 | if (insn && (note = find_reg_note (insn, REG_BR_PRED, NULL_RTX))) | |
e0d80184 DM |
4649 | { |
4650 | strcat (string, | |
4651 | INTVAL (XEXP (note, 0)) & ATTR_FLAG_likely ? ",pt" : ",pn"); | |
4652 | spaces -= 3; | |
4653 | } | |
c6b0465b | 4654 | |
61a55e8b DE |
4655 | labeloff = 9; |
4656 | if (mode == CCFPmode || mode == CCFPEmode) | |
4657 | { | |
4658 | labeloff = 10; | |
4659 | labelno = v9_fcc_labelno; | |
4660 | /* Set the char indicating the number of the fcc reg to use. */ | |
e0d80184 | 4661 | labelno[5] = REGNO (cc_reg) - SPARC_FIRST_V9_FCC_REG + '0'; |
61a55e8b DE |
4662 | } |
4663 | else if (mode == CCXmode || mode == CCX_NOOVmode) | |
4664 | labelno = v9_xcc_labelno; | |
4665 | else | |
4666 | labelno = v9_icc_labelno; | |
4667 | } | |
4668 | /* Set the char indicating the number of the operand containing the | |
4669 | label_ref. */ | |
4670 | labelno[labeloff] = label + '0'; | |
e0d80184 DM |
4671 | if (spaces > 0) |
4672 | strcat (string, "\t"); | |
4673 | else | |
4674 | strcat (string, " "); | |
61a55e8b DE |
4675 | strcat (string, labelno); |
4676 | ||
4677 | if (noop) | |
4678 | strcat (string, "\n\tnop"); | |
4679 | ||
4680 | return string; | |
4681 | } | |
4682 | ||
4683 | /* Return the string to output a conditional branch to LABEL, testing | |
4684 | register REG. LABEL is the operand number of the label; REG is the | |
4685 | operand number of the reg. OP is the conditional expression. The mode | |
4686 | of REG says what kind of comparison we made. | |
4687 | ||
4688 | REVERSED is non-zero if we should reverse the sense of the comparison. | |
4689 | ||
4690 | ANNUL is non-zero if we should generate an annulling branch. | |
4691 | ||
4692 | NOOP is non-zero if we have to follow this branch by a noop. */ | |
4693 | ||
4694 | char * | |
e0d80184 | 4695 | output_v9branch (op, reg, label, reversed, annul, noop, insn) |
61a55e8b DE |
4696 | rtx op; |
4697 | int reg, label; | |
4698 | int reversed, annul, noop; | |
e0d80184 | 4699 | rtx insn; |
61a55e8b DE |
4700 | { |
4701 | static char string[20]; | |
4702 | enum rtx_code code = GET_CODE (op); | |
4703 | enum machine_mode mode = GET_MODE (XEXP (op, 0)); | |
e0d80184 DM |
4704 | static char labelno[] = "%X, %lX"; |
4705 | rtx note; | |
4706 | int spaces = 8; | |
61a55e8b DE |
4707 | |
4708 | /* If not floating-point or if EQ or NE, we can just reverse the code. */ | |
4709 | if (reversed) | |
4710 | code = reverse_condition (code), reversed = 0; | |
4711 | ||
4712 | /* Only 64 bit versions of these instructions exist. */ | |
4713 | if (mode != DImode) | |
4714 | abort (); | |
4715 | ||
4716 | /* Start by writing the branch condition. */ | |
4717 | ||
4718 | switch (code) | |
4719 | { | |
4720 | case NE: | |
4721 | strcpy (string, "brnz"); | |
e0d80184 | 4722 | spaces -= 4; |
61a55e8b DE |
4723 | break; |
4724 | ||
4725 | case EQ: | |
4726 | strcpy (string, "brz"); | |
e0d80184 | 4727 | spaces -= 3; |
61a55e8b DE |
4728 | break; |
4729 | ||
4730 | case GE: | |
4731 | strcpy (string, "brgez"); | |
e0d80184 | 4732 | spaces -= 5; |
61a55e8b DE |
4733 | break; |
4734 | ||
4735 | case LT: | |
4736 | strcpy (string, "brlz"); | |
e0d80184 | 4737 | spaces -= 4; |
61a55e8b DE |
4738 | break; |
4739 | ||
4740 | case LE: | |
4741 | strcpy (string, "brlez"); | |
e0d80184 | 4742 | spaces -= 5; |
61a55e8b DE |
4743 | break; |
4744 | ||
4745 | case GT: | |
4746 | strcpy (string, "brgz"); | |
e0d80184 | 4747 | spaces -= 4; |
61a55e8b DE |
4748 | break; |
4749 | ||
4750 | default: | |
4751 | abort (); | |
4752 | } | |
4753 | ||
4754 | /* Now add the annulling, reg, label, and nop. */ | |
4755 | if (annul) | |
e0d80184 DM |
4756 | { |
4757 | strcat (string, ",a"); | |
4758 | spaces -= 2; | |
4759 | } | |
61a55e8b | 4760 | |
e0d80184 DM |
4761 | if (insn && (note = find_reg_note (insn, REG_BR_PRED, NULL_RTX))) |
4762 | { | |
4763 | strcat (string, | |
4764 | INTVAL (XEXP (note, 0)) & ATTR_FLAG_likely ? ",pt" : ",pn"); | |
4765 | spaces -= 3; | |
4766 | } | |
61a55e8b | 4767 | |
e0d80184 | 4768 | labelno[1] = reg + '0'; |
61a55e8b | 4769 | labelno[6] = label + '0'; |
e0d80184 DM |
4770 | if (spaces > 0) |
4771 | strcat (string, "\t"); | |
4772 | else | |
4773 | strcat (string, " "); | |
ab835497 RK |
4774 | strcat (string, labelno); |
4775 | ||
4776 | if (noop) | |
4777 | strcat (string, "\n\tnop"); | |
4778 | ||
4779 | return string; | |
4780 | } | |
4781 | ||
e48addee JJ |
4782 | /* Return 1, if any of the registers of the instruction are %l[0-7] or %o[0-7]. |
4783 | Such instructions cannot be used in the delay slot of return insn on v9. | |
4784 | If TEST is 0, also rename all %i[0-7] registers to their %o[0-7] counterparts. | |
4785 | */ | |
284d86e9 | 4786 | |
e48addee JJ |
4787 | static int |
4788 | epilogue_renumber (where, test) | |
4789 | register rtx *where; | |
4790 | int test; | |
284d86e9 | 4791 | { |
e48addee JJ |
4792 | register const char *fmt; |
4793 | register int i; | |
4794 | register enum rtx_code code; | |
4795 | ||
4796 | if (*where == 0) | |
4797 | return 0; | |
4798 | ||
4799 | code = GET_CODE (*where); | |
284d86e9 JC |
4800 | |
4801 | switch (code) | |
4802 | { | |
284d86e9 | 4803 | case REG: |
e48addee JJ |
4804 | if (REGNO (*where) >= 8 && REGNO (*where) < 24) /* oX or lX */ |
4805 | return 1; | |
4806 | if (! test && REGNO (*where) >= 24 && REGNO (*where) < 32) | |
4807 | *where = gen_rtx (REG, GET_MODE (*where), OUTGOING_REGNO (REGNO(*where))); | |
4808 | case SCRATCH: | |
4809 | case CC0: | |
4810 | case PC: | |
284d86e9 JC |
4811 | case CONST_INT: |
4812 | case CONST_DOUBLE: | |
e48addee JJ |
4813 | return 0; |
4814 | } | |
284d86e9 | 4815 | |
e48addee | 4816 | fmt = GET_RTX_FORMAT (code); |
284d86e9 | 4817 | |
e48addee JJ |
4818 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) |
4819 | { | |
4820 | if (fmt[i] == 'E') | |
4821 | { | |
4822 | register int j; | |
4823 | for (j = XVECLEN (*where, i) - 1; j >= 0; j--) | |
4824 | if (epilogue_renumber (&(XVECEXP (*where, i, j)), test)) | |
4825 | return 1; | |
4826 | } | |
4827 | else if (fmt[i] == 'e' | |
4828 | && epilogue_renumber (&(XEXP (*where, i)), test)) | |
4829 | return 1; | |
284d86e9 | 4830 | } |
e48addee | 4831 | return 0; |
284d86e9 JC |
4832 | } |
4833 | ||
4834 | /* Output assembler code to return from a function. */ | |
61a55e8b | 4835 | |
3bb5de61 | 4836 | const char * |
ab835497 RK |
4837 | output_return (operands) |
4838 | rtx *operands; | |
4839 | { | |
284d86e9 JC |
4840 | rtx delay = final_sequence ? XVECEXP (final_sequence, 0, 1) : 0; |
4841 | ||
ab835497 RK |
4842 | if (leaf_label) |
4843 | { | |
4844 | operands[0] = leaf_label; | |
284d86e9 | 4845 | return "b%* %l0%("; |
ab835497 | 4846 | } |
54ff41b7 | 4847 | else if (current_function_uses_only_leaf_regs) |
ab835497 | 4848 | { |
284d86e9 JC |
4849 | /* No delay slot in a leaf function. */ |
4850 | if (delay) | |
4851 | abort (); | |
4852 | ||
915f619f JW |
4853 | /* If we didn't allocate a frame pointer for the current function, |
4854 | the stack pointer might have been adjusted. Output code to | |
4855 | restore it now. */ | |
4856 | ||
3a598fbe | 4857 | operands[0] = GEN_INT (actual_fsize); |
915f619f JW |
4858 | |
4859 | /* Use sub of negated value in first two cases instead of add to | |
4860 | allow actual_fsize == 4096. */ | |
4861 | ||
4862 | if (actual_fsize <= 4096) | |
ab835497 | 4863 | { |
61a55e8b | 4864 | if (SKIP_CALLERS_UNIMP_P) |
e0d80184 | 4865 | return "jmp\t%%o7+12\n\tsub\t%%sp, -%0, %%sp"; |
ab835497 | 4866 | else |
e0d80184 | 4867 | return "retl\n\tsub\t%%sp, -%0, %%sp"; |
ab835497 | 4868 | } |
915f619f | 4869 | else if (actual_fsize <= 8192) |
ab835497 | 4870 | { |
3a598fbe | 4871 | operands[0] = GEN_INT (actual_fsize - 4096); |
61a55e8b | 4872 | if (SKIP_CALLERS_UNIMP_P) |
e0d80184 | 4873 | return "sub\t%%sp, -4096, %%sp\n\tjmp\t%%o7+12\n\tsub\t%%sp, -%0, %%sp"; |
915f619f | 4874 | else |
e0d80184 | 4875 | return "sub\t%%sp, -4096, %%sp\n\tretl\n\tsub\t%%sp, -%0, %%sp"; |
915f619f | 4876 | } |
61a55e8b | 4877 | else if (SKIP_CALLERS_UNIMP_P) |
915f619f JW |
4878 | { |
4879 | if ((actual_fsize & 0x3ff) != 0) | |
e0d80184 | 4880 | return "sethi\t%%hi(%a0), %%g1\n\tor\t%%g1, %%lo(%a0), %%g1\n\tjmp\t%%o7+12\n\tadd\t%%sp, %%g1, %%sp"; |
ab835497 | 4881 | else |
e0d80184 | 4882 | return "sethi\t%%hi(%a0), %%g1\n\tjmp\t%%o7+12\n\tadd\t%%sp, %%g1, %%sp"; |
915f619f JW |
4883 | } |
4884 | else | |
4885 | { | |
4886 | if ((actual_fsize & 0x3ff) != 0) | |
ab835497 | 4887 | return "sethi %%hi(%a0),%%g1\n\tor %%g1,%%lo(%a0),%%g1\n\tretl\n\tadd %%sp,%%g1,%%sp"; |
915f619f JW |
4888 | else |
4889 | return "sethi %%hi(%a0),%%g1\n\tretl\n\tadd %%sp,%%g1,%%sp"; | |
ab835497 RK |
4890 | } |
4891 | } | |
284d86e9 JC |
4892 | else if (TARGET_V9) |
4893 | { | |
4894 | if (delay) | |
4895 | { | |
e48addee JJ |
4896 | epilogue_renumber (&SET_DEST (PATTERN (delay)), 0); |
4897 | epilogue_renumber (&SET_SRC (PATTERN (delay)), 0); | |
284d86e9 JC |
4898 | } |
4899 | if (SKIP_CALLERS_UNIMP_P) | |
e0d80184 | 4900 | return "return\t%%i7+12%#"; |
284d86e9 | 4901 | else |
e0d80184 | 4902 | return "return\t%%i7+8%#"; |
284d86e9 | 4903 | } |
ab835497 RK |
4904 | else |
4905 | { | |
284d86e9 JC |
4906 | if (delay) |
4907 | abort (); | |
61a55e8b | 4908 | if (SKIP_CALLERS_UNIMP_P) |
e0d80184 | 4909 | return "jmp\t%%i7+12\n\trestore"; |
ab835497 RK |
4910 | else |
4911 | return "ret\n\trestore"; | |
4912 | } | |
4913 | } | |
ab835497 RK |
4914 | \f |
4915 | /* Leaf functions and non-leaf functions have different needs. */ | |
4916 | ||
4917 | static int | |
4918 | reg_leaf_alloc_order[] = REG_LEAF_ALLOC_ORDER; | |
4919 | ||
4920 | static int | |
4921 | reg_nonleaf_alloc_order[] = REG_ALLOC_ORDER; | |
4922 | ||
4923 | static int *reg_alloc_orders[] = { | |
4924 | reg_leaf_alloc_order, | |
4925 | reg_nonleaf_alloc_order}; | |
4926 | ||
4927 | void | |
4928 | order_regs_for_local_alloc () | |
4929 | { | |
4930 | static int last_order_nonleaf = 1; | |
4931 | ||
4932 | if (regs_ever_live[15] != last_order_nonleaf) | |
4933 | { | |
4934 | last_order_nonleaf = !last_order_nonleaf; | |
d2889939 RK |
4935 | bcopy ((char *) reg_alloc_orders[last_order_nonleaf], |
4936 | (char *) reg_alloc_order, FIRST_PSEUDO_REGISTER * sizeof (int)); | |
ab835497 RK |
4937 | } |
4938 | } | |
4939 | \f | |
e0d80184 DM |
4940 | /* Return 1 if REG and MEM are legitimate enough to allow the various |
4941 | mem<-->reg splits to be run. */ | |
4942 | ||
4943 | int | |
e61c29e9 | 4944 | sparc_splitdi_legitimate (reg, mem) |
e0d80184 DM |
4945 | rtx reg; |
4946 | rtx mem; | |
4947 | { | |
e0d80184 DM |
4948 | /* Punt if we are here by mistake. */ |
4949 | if (! reload_completed) | |
9208e4b2 | 4950 | abort (); |
e0d80184 DM |
4951 | |
4952 | /* We must have an offsettable memory reference. */ | |
4953 | if (! offsettable_memref_p (mem)) | |
4954 | return 0; | |
4955 | ||
4956 | /* If we have legitimate args for ldd/std, we do not want | |
4957 | the split to happen. */ | |
4958 | if ((REGNO (reg) % 2) == 0 | |
4959 | && mem_min_alignment (mem, 8)) | |
4960 | return 0; | |
4961 | ||
4962 | /* Success. */ | |
4963 | return 1; | |
4964 | } | |
4965 | ||
e61c29e9 DM |
4966 | /* Return 1 if x and y are some kind of REG and they refer to |
4967 | different hard registers. This test is guarenteed to be | |
4968 | run after reload. */ | |
4969 | ||
4970 | int | |
4971 | sparc_absnegfloat_split_legitimate (x, y) | |
4972 | rtx x, y; | |
4973 | { | |
4974 | if (GET_CODE (x) == SUBREG) | |
4975 | x = alter_subreg (x); | |
4976 | if (GET_CODE (x) != REG) | |
4977 | return 0; | |
4978 | if (GET_CODE (y) == SUBREG) | |
4979 | y = alter_subreg (y); | |
4980 | if (GET_CODE (y) != REG) | |
4981 | return 0; | |
4982 | if (REGNO (x) == REGNO (y)) | |
4983 | return 0; | |
4984 | return 1; | |
4985 | } | |
4986 | ||
35016322 JW |
4987 | /* Return 1 if REGNO (reg1) is even and REGNO (reg1) == REGNO (reg2) - 1. |
4988 | This makes them candidates for using ldd and std insns. | |
4989 | ||
bfd6bc60 | 4990 | Note reg1 and reg2 *must* be hard registers. */ |
35016322 JW |
4991 | |
4992 | int | |
7c56249d | 4993 | registers_ok_for_ldd_peep (reg1, reg2) |
35016322 JW |
4994 | rtx reg1, reg2; |
4995 | { | |
35016322 JW |
4996 | /* We might have been passed a SUBREG. */ |
4997 | if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG) | |
4998 | return 0; | |
4999 | ||
35016322 JW |
5000 | if (REGNO (reg1) % 2 != 0) |
5001 | return 0; | |
5002 | ||
bfd6bc60 JC |
5003 | /* Integer ldd is deprecated in SPARC V9 */ |
5004 | if (TARGET_V9 && REGNO (reg1) < 32) | |
5005 | return 0; | |
5006 | ||
35016322 | 5007 | return (REGNO (reg1) == REGNO (reg2) - 1); |
35016322 JW |
5008 | } |
5009 | ||
5010 | /* Return 1 if addr1 and addr2 are suitable for use in an ldd or | |
5011 | std insn. | |
5012 | ||
5013 | This can only happen when addr1 and addr2 are consecutive memory | |
5014 | locations (addr1 + 4 == addr2). addr1 must also be aligned on a | |
5015 | 64 bit boundary (addr1 % 8 == 0). | |
5016 | ||
5017 | We know %sp and %fp are kept aligned on a 64 bit boundary. Other | |
5018 | registers are assumed to *never* be properly aligned and are | |
5019 | rejected. | |
5020 | ||
5021 | Knowing %sp and %fp are kept aligned on a 64 bit boundary, we | |
5022 | need only check that the offset for addr1 % 8 == 0. */ | |
5023 | ||
5024 | int | |
7c56249d | 5025 | addrs_ok_for_ldd_peep (addr1, addr2) |
35016322 JW |
5026 | rtx addr1, addr2; |
5027 | { | |
5028 | int reg1, offset1; | |
5029 | ||
5030 | /* Extract a register number and offset (if used) from the first addr. */ | |
5031 | if (GET_CODE (addr1) == PLUS) | |
5032 | { | |
5033 | /* If not a REG, return zero. */ | |
5034 | if (GET_CODE (XEXP (addr1, 0)) != REG) | |
5035 | return 0; | |
5036 | else | |
5037 | { | |
5038 | reg1 = REGNO (XEXP (addr1, 0)); | |
5039 | /* The offset must be constant! */ | |
5040 | if (GET_CODE (XEXP (addr1, 1)) != CONST_INT) | |
5041 | return 0; | |
5042 | offset1 = INTVAL (XEXP (addr1, 1)); | |
5043 | } | |
5044 | } | |
5045 | else if (GET_CODE (addr1) != REG) | |
5046 | return 0; | |
5047 | else | |
5048 | { | |
5049 | reg1 = REGNO (addr1); | |
5050 | /* This was a simple (mem (reg)) expression. Offset is 0. */ | |
5051 | offset1 = 0; | |
5052 | } | |
5053 | ||
5054 | /* Make sure the second address is a (mem (plus (reg) (const_int). */ | |
5055 | if (GET_CODE (addr2) != PLUS) | |
5056 | return 0; | |
5057 | ||
5058 | if (GET_CODE (XEXP (addr2, 0)) != REG | |
5059 | || GET_CODE (XEXP (addr2, 1)) != CONST_INT) | |
5060 | return 0; | |
5061 | ||
5062 | /* Only %fp and %sp are allowed. Additionally both addresses must | |
5063 | use the same register. */ | |
5064 | if (reg1 != FRAME_POINTER_REGNUM && reg1 != STACK_POINTER_REGNUM) | |
5065 | return 0; | |
5066 | ||
5067 | if (reg1 != REGNO (XEXP (addr2, 0))) | |
5068 | return 0; | |
5069 | ||
2296cba3 | 5070 | /* The first offset must be evenly divisible by 8 to ensure the |
35016322 JW |
5071 | address is 64 bit aligned. */ |
5072 | if (offset1 % 8 != 0) | |
5073 | return 0; | |
5074 | ||
5075 | /* The offset for the second addr must be 4 more than the first addr. */ | |
5076 | if (INTVAL (XEXP (addr2, 1)) != offset1 + 4) | |
5077 | return 0; | |
5078 | ||
5079 | /* All the tests passed. addr1 and addr2 are valid for ldd and std | |
5080 | instructions. */ | |
5081 | return 1; | |
5082 | } | |
7c56249d JL |
5083 | |
5084 | /* Return 1 if reg is a pseudo, or is the first register in | |
5085 | a hard register pair. This makes it a candidate for use in | |
5086 | ldd and std insns. */ | |
5087 | ||
5088 | int | |
5089 | register_ok_for_ldd (reg) | |
5090 | rtx reg; | |
5091 | { | |
7c56249d JL |
5092 | /* We might have been passed a SUBREG. */ |
5093 | if (GET_CODE (reg) != REG) | |
5094 | return 0; | |
5095 | ||
5096 | if (REGNO (reg) < FIRST_PSEUDO_REGISTER) | |
5097 | return (REGNO (reg) % 2 == 0); | |
5098 | else | |
5099 | return 1; | |
7c56249d | 5100 | } |
ab835497 | 5101 | \f |
ab835497 RK |
5102 | /* Print operand X (an rtx) in assembler syntax to file FILE. |
5103 | CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. | |
5104 | For `%' followed by punctuation, CODE is the punctuation and X is null. */ | |
5105 | ||
5106 | void | |
5107 | print_operand (file, x, code) | |
5108 | FILE *file; | |
5109 | rtx x; | |
5110 | int code; | |
5111 | { | |
5112 | switch (code) | |
5113 | { | |
5114 | case '#': | |
5115 | /* Output a 'nop' if there's nothing for the delay slot. */ | |
5116 | if (dbr_sequence_length () == 0) | |
e0d80184 | 5117 | fputs ("\n\t nop", file); |
ab835497 RK |
5118 | return; |
5119 | case '*': | |
c6ce0969 JW |
5120 | /* Output an annul flag if there's nothing for the delay slot and we |
5121 | are optimizing. This is always used with '(' below. */ | |
5122 | /* Sun OS 4.1.1 dbx can't handle an annulled unconditional branch; | |
5123 | this is a dbx bug. So, we only do this when optimizing. */ | |
bfd6bc60 JC |
5124 | /* On UltraSPARC, a branch in a delay slot causes a pipeline flush. |
5125 | Always emit a nop in case the next instruction is a branch. */ | |
5126 | if (dbr_sequence_length () == 0 | |
284d86e9 | 5127 | && (optimize && (int)sparc_cpu < PROCESSOR_V9)) |
c6ce0969 JW |
5128 | fputs (",a", file); |
5129 | return; | |
5130 | case '(': | |
5131 | /* Output a 'nop' if there's nothing for the delay slot and we are | |
5132 | not optimizing. This is always used with '*' above. */ | |
bfd6bc60 | 5133 | if (dbr_sequence_length () == 0 |
284d86e9 | 5134 | && ! (optimize && (int)sparc_cpu < PROCESSOR_V9)) |
e0d80184 | 5135 | fputs ("\n\t nop", file); |
ab835497 | 5136 | return; |
61a55e8b | 5137 | case '_': |
a0a301fc DE |
5138 | /* Output the Embedded Medium/Anywhere code model base register. */ |
5139 | fputs (EMBMEDANY_BASE_REG, file); | |
61a55e8b DE |
5140 | return; |
5141 | case '@': | |
5142 | /* Print out what we are using as the frame pointer. This might | |
5143 | be %fp, or might be %sp+offset. */ | |
5144 | /* ??? What if offset is too big? Perhaps the caller knows it isn't? */ | |
5145 | fprintf (file, "%s+%d", frame_base_name, frame_base_offset); | |
5146 | return; | |
ab835497 RK |
5147 | case 'Y': |
5148 | /* Adjust the operand to take into account a RESTORE operation. */ | |
bfd6bc60 JC |
5149 | if (GET_CODE (x) == CONST_INT) |
5150 | break; | |
5151 | else if (GET_CODE (x) != REG) | |
b3b1e8bd JW |
5152 | output_operand_lossage ("Invalid %%Y operand"); |
5153 | else if (REGNO (x) < 8) | |
ab835497 RK |
5154 | fputs (reg_names[REGNO (x)], file); |
5155 | else if (REGNO (x) >= 24 && REGNO (x) < 32) | |
5156 | fputs (reg_names[REGNO (x)-16], file); | |
5157 | else | |
b3b1e8bd | 5158 | output_operand_lossage ("Invalid %%Y operand"); |
ab835497 | 5159 | return; |
0f39a9aa DE |
5160 | case 'L': |
5161 | /* Print out the low order register name of a register pair. */ | |
5162 | if (WORDS_BIG_ENDIAN) | |
5163 | fputs (reg_names[REGNO (x)+1], file); | |
5164 | else | |
5165 | fputs (reg_names[REGNO (x)], file); | |
5166 | return; | |
5167 | case 'H': | |
5168 | /* Print out the high order register name of a register pair. */ | |
5169 | if (WORDS_BIG_ENDIAN) | |
5170 | fputs (reg_names[REGNO (x)], file); | |
5171 | else | |
5172 | fputs (reg_names[REGNO (x)+1], file); | |
5173 | return; | |
ab835497 | 5174 | case 'R': |
795068a4 | 5175 | /* Print out the second register name of a register pair or quad. |
ab835497 RK |
5176 | I.e., R (%o0) => %o1. */ |
5177 | fputs (reg_names[REGNO (x)+1], file); | |
5178 | return; | |
795068a4 JW |
5179 | case 'S': |
5180 | /* Print out the third register name of a register quad. | |
5181 | I.e., S (%o0) => %o2. */ | |
5182 | fputs (reg_names[REGNO (x)+2], file); | |
5183 | return; | |
5184 | case 'T': | |
5185 | /* Print out the fourth register name of a register quad. | |
5186 | I.e., T (%o0) => %o3. */ | |
5187 | fputs (reg_names[REGNO (x)+3], file); | |
5188 | return; | |
304b7a23 DE |
5189 | case 'x': |
5190 | /* Print a condition code register. */ | |
5191 | if (REGNO (x) == SPARC_ICC_REG) | |
5192 | { | |
5193 | /* We don't handle CC[X]_NOOVmode because they're not supposed | |
5194 | to occur here. */ | |
5195 | if (GET_MODE (x) == CCmode) | |
5196 | fputs ("%icc", file); | |
5197 | else if (GET_MODE (x) == CCXmode) | |
5198 | fputs ("%xcc", file); | |
5199 | else | |
5200 | abort (); | |
5201 | } | |
5202 | else | |
5203 | /* %fccN register */ | |
5204 | fputs (reg_names[REGNO (x)], file); | |
5205 | return; | |
ab835497 RK |
5206 | case 'm': |
5207 | /* Print the operand's address only. */ | |
5208 | output_address (XEXP (x, 0)); | |
5209 | return; | |
5210 | case 'r': | |
5211 | /* In this case we need a register. Use %g0 if the | |
77a02b01 | 5212 | operand is const0_rtx. */ |
76052e74 RS |
5213 | if (x == const0_rtx |
5214 | || (GET_MODE (x) != VOIDmode && x == CONST0_RTX (GET_MODE (x)))) | |
ab835497 RK |
5215 | { |
5216 | fputs ("%g0", file); | |
5217 | return; | |
5218 | } | |
5219 | else | |
5220 | break; | |
5221 | ||
61a55e8b | 5222 | case 'A': |
ab835497 RK |
5223 | switch (GET_CODE (x)) |
5224 | { | |
5225 | case IOR: fputs ("or", file); break; | |
5226 | case AND: fputs ("and", file); break; | |
5227 | case XOR: fputs ("xor", file); break; | |
b3b1e8bd | 5228 | default: output_operand_lossage ("Invalid %%A operand"); |
ab835497 RK |
5229 | } |
5230 | return; | |
5231 | ||
5232 | case 'B': | |
5233 | switch (GET_CODE (x)) | |
5234 | { | |
5235 | case IOR: fputs ("orn", file); break; | |
5236 | case AND: fputs ("andn", file); break; | |
5237 | case XOR: fputs ("xnor", file); break; | |
b3b1e8bd | 5238 | default: output_operand_lossage ("Invalid %%B operand"); |
ab835497 RK |
5239 | } |
5240 | return; | |
5241 | ||
304b7a23 DE |
5242 | /* These are used by the conditional move instructions. */ |
5243 | case 'c' : | |
61a55e8b | 5244 | case 'C': |
304b7a23 DE |
5245 | { |
5246 | enum rtx_code rc = (code == 'c' | |
5247 | ? reverse_condition (GET_CODE (x)) | |
5248 | : GET_CODE (x)); | |
5249 | switch (rc) | |
5250 | { | |
5251 | case NE: fputs ("ne", file); break; | |
5252 | case EQ: fputs ("e", file); break; | |
5253 | case GE: fputs ("ge", file); break; | |
5254 | case GT: fputs ("g", file); break; | |
5255 | case LE: fputs ("le", file); break; | |
5256 | case LT: fputs ("l", file); break; | |
5257 | case GEU: fputs ("geu", file); break; | |
5258 | case GTU: fputs ("gu", file); break; | |
5259 | case LEU: fputs ("leu", file); break; | |
5260 | case LTU: fputs ("lu", file); break; | |
5261 | default: output_operand_lossage (code == 'c' | |
5262 | ? "Invalid %%c operand" | |
5263 | : "Invalid %%C operand"); | |
5264 | } | |
5265 | return; | |
5266 | } | |
5267 | ||
5268 | /* These are used by the movr instruction pattern. */ | |
5269 | case 'd': | |
61a55e8b | 5270 | case 'D': |
304b7a23 DE |
5271 | { |
5272 | enum rtx_code rc = (code == 'd' | |
5273 | ? reverse_condition (GET_CODE (x)) | |
5274 | : GET_CODE (x)); | |
5275 | switch (rc) | |
5276 | { | |
5277 | case NE: fputs ("ne", file); break; | |
5278 | case EQ: fputs ("e", file); break; | |
5279 | case GE: fputs ("gez", file); break; | |
5280 | case LT: fputs ("lz", file); break; | |
5281 | case LE: fputs ("lez", file); break; | |
5282 | case GT: fputs ("gz", file); break; | |
5283 | default: output_operand_lossage (code == 'd' | |
5284 | ? "Invalid %%d operand" | |
5285 | : "Invalid %%D operand"); | |
5286 | } | |
5287 | return; | |
5288 | } | |
61a55e8b | 5289 | |
ab835497 RK |
5290 | case 'b': |
5291 | { | |
5292 | /* Print a sign-extended character. */ | |
5293 | int i = INTVAL (x) & 0xff; | |
5294 | if (i & 0x80) | |
5295 | i |= 0xffffff00; | |
5296 | fprintf (file, "%d", i); | |
5297 | return; | |
5298 | } | |
5299 | ||
d2889939 RK |
5300 | case 'f': |
5301 | /* Operand must be a MEM; write its address. */ | |
5302 | if (GET_CODE (x) != MEM) | |
5303 | output_operand_lossage ("Invalid %%f operand"); | |
5304 | output_address (XEXP (x, 0)); | |
5305 | return; | |
5306 | ||
ab835497 RK |
5307 | case 0: |
5308 | /* Do nothing special. */ | |
5309 | break; | |
5310 | ||
5311 | default: | |
5312 | /* Undocumented flag. */ | |
415f583e | 5313 | output_operand_lossage ("invalid operand output code"); |
ab835497 RK |
5314 | } |
5315 | ||
5316 | if (GET_CODE (x) == REG) | |
5317 | fputs (reg_names[REGNO (x)], file); | |
5318 | else if (GET_CODE (x) == MEM) | |
5319 | { | |
5320 | fputc ('[', file); | |
ab835497 | 5321 | /* Poor Sun assembler doesn't understand absolute addressing. */ |
c4ce6853 DE |
5322 | if (CONSTANT_P (XEXP (x, 0)) |
5323 | && ! TARGET_LIVE_G0) | |
ab835497 RK |
5324 | fputs ("%g0+", file); |
5325 | output_address (XEXP (x, 0)); | |
5326 | fputc (']', file); | |
5327 | } | |
5328 | else if (GET_CODE (x) == HIGH) | |
5329 | { | |
5330 | fputs ("%hi(", file); | |
5331 | output_addr_const (file, XEXP (x, 0)); | |
5332 | fputc (')', file); | |
5333 | } | |
5334 | else if (GET_CODE (x) == LO_SUM) | |
5335 | { | |
5336 | print_operand (file, XEXP (x, 0), 0); | |
e0d80184 DM |
5337 | if (TARGET_CM_MEDMID) |
5338 | fputs ("+%l44(", file); | |
5339 | else | |
5340 | fputs ("+%lo(", file); | |
ab835497 RK |
5341 | output_addr_const (file, XEXP (x, 1)); |
5342 | fputc (')', file); | |
5343 | } | |
e601abce JW |
5344 | else if (GET_CODE (x) == CONST_DOUBLE |
5345 | && (GET_MODE (x) == VOIDmode | |
5346 | || GET_MODE_CLASS (GET_MODE (x)) == MODE_INT)) | |
ab835497 RK |
5347 | { |
5348 | if (CONST_DOUBLE_HIGH (x) == 0) | |
5349 | fprintf (file, "%u", CONST_DOUBLE_LOW (x)); | |
5350 | else if (CONST_DOUBLE_HIGH (x) == -1 | |
5351 | && CONST_DOUBLE_LOW (x) < 0) | |
5352 | fprintf (file, "%d", CONST_DOUBLE_LOW (x)); | |
5353 | else | |
e601abce | 5354 | output_operand_lossage ("long long constant not a valid immediate operand"); |
ab835497 | 5355 | } |
e601abce JW |
5356 | else if (GET_CODE (x) == CONST_DOUBLE) |
5357 | output_operand_lossage ("floating point constant not a valid immediate operand"); | |
ab835497 RK |
5358 | else { output_addr_const (file, x); } |
5359 | } | |
5360 | \f | |
5361 | /* This function outputs assembler code for VALUE to FILE, where VALUE is | |
5362 | a 64 bit (DImode) value. */ | |
5363 | ||
5364 | /* ??? If there is a 64 bit counterpart to .word that the assembler | |
5365 | understands, then using that would simply this code greatly. */ | |
61a55e8b DE |
5366 | /* ??? We only output .xword's for symbols and only then in environments |
5367 | where the assembler can handle them. */ | |
ab835497 RK |
5368 | |
5369 | void | |
5370 | output_double_int (file, value) | |
5371 | FILE *file; | |
5372 | rtx value; | |
5373 | { | |
5374 | if (GET_CODE (value) == CONST_INT) | |
5375 | { | |
f4f8e370 DE |
5376 | /* ??? This has endianness issues. */ |
5377 | #if HOST_BITS_PER_WIDE_INT == 64 | |
5378 | HOST_WIDE_INT xword = INTVAL (value); | |
5379 | HOST_WIDE_INT high, low; | |
5380 | ||
5381 | high = (xword >> 32) & 0xffffffff; | |
5382 | low = xword & 0xffffffff; | |
3a598fbe JL |
5383 | ASM_OUTPUT_INT (file, GEN_INT (high)); |
5384 | ASM_OUTPUT_INT (file, GEN_INT (low)); | |
f4f8e370 | 5385 | #else |
ab835497 RK |
5386 | if (INTVAL (value) < 0) |
5387 | ASM_OUTPUT_INT (file, constm1_rtx); | |
5388 | else | |
5389 | ASM_OUTPUT_INT (file, const0_rtx); | |
5390 | ASM_OUTPUT_INT (file, value); | |
f4f8e370 | 5391 | #endif |
ab835497 RK |
5392 | } |
5393 | else if (GET_CODE (value) == CONST_DOUBLE) | |
5394 | { | |
3a598fbe JL |
5395 | ASM_OUTPUT_INT (file, GEN_INT (CONST_DOUBLE_HIGH (value))); |
5396 | ASM_OUTPUT_INT (file, GEN_INT (CONST_DOUBLE_LOW (value))); | |
ab835497 RK |
5397 | } |
5398 | else if (GET_CODE (value) == SYMBOL_REF | |
5399 | || GET_CODE (value) == CONST | |
61a55e8b | 5400 | || GET_CODE (value) == PLUS |
a9e27770 | 5401 | || (TARGET_ARCH64 && |
61a55e8b | 5402 | (GET_CODE (value) == LABEL_REF |
9fa9626b | 5403 | || GET_CODE (value) == CODE_LABEL |
61a55e8b | 5404 | || GET_CODE (value) == MINUS))) |
ab835497 | 5405 | { |
f3b8847b | 5406 | if (! TARGET_V9) |
61a55e8b DE |
5407 | { |
5408 | ASM_OUTPUT_INT (file, const0_rtx); | |
5409 | ASM_OUTPUT_INT (file, value); | |
5410 | } | |
5411 | else | |
5412 | { | |
5413 | fprintf (file, "\t%s\t", ASM_LONGLONG); | |
5414 | output_addr_const (file, value); | |
5415 | fprintf (file, "\n"); | |
5416 | } | |
ab835497 RK |
5417 | } |
5418 | else | |
5419 | abort (); | |
5420 | } | |
210aa14a | 5421 | \f |
b0468b84 RK |
5422 | /* Return the value of a code used in the .proc pseudo-op that says |
5423 | what kind of result this function returns. For non-C types, we pick | |
5424 | the closest C type. */ | |
5425 | ||
77a02b01 JW |
5426 | #ifndef CHAR_TYPE_SIZE |
5427 | #define CHAR_TYPE_SIZE BITS_PER_UNIT | |
5428 | #endif | |
5429 | ||
5430 | #ifndef SHORT_TYPE_SIZE | |
5431 | #define SHORT_TYPE_SIZE (BITS_PER_UNIT * 2) | |
5432 | #endif | |
5433 | ||
5434 | #ifndef INT_TYPE_SIZE | |
5435 | #define INT_TYPE_SIZE BITS_PER_WORD | |
5436 | #endif | |
5437 | ||
5438 | #ifndef LONG_TYPE_SIZE | |
5439 | #define LONG_TYPE_SIZE BITS_PER_WORD | |
5440 | #endif | |
5441 | ||
5442 | #ifndef LONG_LONG_TYPE_SIZE | |
5443 | #define LONG_LONG_TYPE_SIZE (BITS_PER_WORD * 2) | |
5444 | #endif | |
5445 | ||
5446 | #ifndef FLOAT_TYPE_SIZE | |
5447 | #define FLOAT_TYPE_SIZE BITS_PER_WORD | |
5448 | #endif | |
5449 | ||
5450 | #ifndef DOUBLE_TYPE_SIZE | |
5451 | #define DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2) | |
5452 | #endif | |
5453 | ||
5454 | #ifndef LONG_DOUBLE_TYPE_SIZE | |
5455 | #define LONG_DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2) | |
5456 | #endif | |
210aa14a RS |
5457 | |
5458 | unsigned long | |
5459 | sparc_type_code (type) | |
5460 | register tree type; | |
5461 | { | |
5462 | register unsigned long qualifiers = 0; | |
e5e809f4 | 5463 | register unsigned shift; |
210aa14a | 5464 | |
abc95ed3 | 5465 | /* Only the first 30 bits of the qualifier are valid. We must refrain from |
aee2c3c5 JW |
5466 | setting more, since some assemblers will give an error for this. Also, |
5467 | we must be careful to avoid shifts of 32 bits or more to avoid getting | |
5468 | unpredictable results. */ | |
5469 | ||
e5e809f4 | 5470 | for (shift = 6; shift < 30; shift += 2, type = TREE_TYPE (type)) |
210aa14a RS |
5471 | { |
5472 | switch (TREE_CODE (type)) | |
5473 | { | |
5474 | case ERROR_MARK: | |
5475 | return qualifiers; | |
5476 | ||
5477 | case ARRAY_TYPE: | |
e5e809f4 | 5478 | qualifiers |= (3 << shift); |
210aa14a RS |
5479 | break; |
5480 | ||
5481 | case FUNCTION_TYPE: | |
5482 | case METHOD_TYPE: | |
e5e809f4 | 5483 | qualifiers |= (2 << shift); |
210aa14a RS |
5484 | break; |
5485 | ||
5486 | case POINTER_TYPE: | |
5487 | case REFERENCE_TYPE: | |
5488 | case OFFSET_TYPE: | |
e5e809f4 | 5489 | qualifiers |= (1 << shift); |
210aa14a | 5490 | break; |
ab835497 | 5491 | |
210aa14a RS |
5492 | case RECORD_TYPE: |
5493 | return (qualifiers | 8); | |
5494 | ||
5495 | case UNION_TYPE: | |
b0468b84 | 5496 | case QUAL_UNION_TYPE: |
210aa14a RS |
5497 | return (qualifiers | 9); |
5498 | ||
5499 | case ENUMERAL_TYPE: | |
5500 | return (qualifiers | 10); | |
5501 | ||
5502 | case VOID_TYPE: | |
5503 | return (qualifiers | 16); | |
5504 | ||
5505 | case INTEGER_TYPE: | |
654209e6 JW |
5506 | /* If this is a range type, consider it to be the underlying |
5507 | type. */ | |
5508 | if (TREE_TYPE (type) != 0) | |
e5e809f4 | 5509 | break; |
654209e6 | 5510 | |
77a02b01 | 5511 | /* Carefully distinguish all the standard types of C, |
b0468b84 RK |
5512 | without messing up if the language is not C. We do this by |
5513 | testing TYPE_PRECISION and TREE_UNSIGNED. The old code used to | |
5514 | look at both the names and the above fields, but that's redundant. | |
5515 | Any type whose size is between two C types will be considered | |
5516 | to be the wider of the two types. Also, we do not have a | |
5517 | special code to use for "long long", so anything wider than | |
5518 | long is treated the same. Note that we can't distinguish | |
5519 | between "int" and "long" in this code if they are the same | |
5520 | size, but that's fine, since neither can the assembler. */ | |
5521 | ||
5522 | if (TYPE_PRECISION (type) <= CHAR_TYPE_SIZE) | |
5523 | return (qualifiers | (TREE_UNSIGNED (type) ? 12 : 2)); | |
77a02b01 | 5524 | |
b0468b84 RK |
5525 | else if (TYPE_PRECISION (type) <= SHORT_TYPE_SIZE) |
5526 | return (qualifiers | (TREE_UNSIGNED (type) ? 13 : 3)); | |
77a02b01 | 5527 | |
b0468b84 | 5528 | else if (TYPE_PRECISION (type) <= INT_TYPE_SIZE) |
77a02b01 JW |
5529 | return (qualifiers | (TREE_UNSIGNED (type) ? 14 : 4)); |
5530 | ||
b0468b84 | 5531 | else |
77a02b01 JW |
5532 | return (qualifiers | (TREE_UNSIGNED (type) ? 15 : 5)); |
5533 | ||
210aa14a | 5534 | case REAL_TYPE: |
e5e809f4 JL |
5535 | /* If this is a range type, consider it to be the underlying |
5536 | type. */ | |
5537 | if (TREE_TYPE (type) != 0) | |
5538 | break; | |
5539 | ||
77a02b01 JW |
5540 | /* Carefully distinguish all the standard types of C, |
5541 | without messing up if the language is not C. */ | |
b0468b84 | 5542 | |
77a02b01 | 5543 | if (TYPE_PRECISION (type) == FLOAT_TYPE_SIZE) |
210aa14a | 5544 | return (qualifiers | 6); |
b0468b84 RK |
5545 | |
5546 | else | |
5547 | return (qualifiers | 7); | |
210aa14a RS |
5548 | |
5549 | case COMPLEX_TYPE: /* GNU Fortran COMPLEX type. */ | |
13d39dbc | 5550 | /* ??? We need to distinguish between double and float complex types, |
c82aa69a JW |
5551 | but I don't know how yet because I can't reach this code from |
5552 | existing front-ends. */ | |
5553 | return (qualifiers | 7); /* Who knows? */ | |
5554 | ||
210aa14a RS |
5555 | case CHAR_TYPE: /* GNU Pascal CHAR type. Not used in C. */ |
5556 | case BOOLEAN_TYPE: /* GNU Fortran BOOLEAN type. */ | |
5557 | case FILE_TYPE: /* GNU Pascal FILE type. */ | |
26902ae0 | 5558 | case SET_TYPE: /* GNU Pascal SET type. */ |
210aa14a | 5559 | case LANG_TYPE: /* ? */ |
26902ae0 | 5560 | return qualifiers; |
210aa14a RS |
5561 | |
5562 | default: | |
5563 | abort (); /* Not a type! */ | |
5564 | } | |
5565 | } | |
e5e809f4 JL |
5566 | |
5567 | return qualifiers; | |
210aa14a | 5568 | } |
ead69aea | 5569 | \f |
61a55e8b DE |
5570 | /* Nested function support. */ |
5571 | ||
5572 | /* Emit RTL insns to initialize the variable parts of a trampoline. | |
5573 | FNADDR is an RTX for the address of the function's pure code. | |
5574 | CXT is an RTX for the static chain value for the function. | |
5575 | ||
5576 | This takes 16 insns: 2 shifts & 2 ands (to split up addresses), 4 sethi | |
5577 | (to load in opcodes), 4 iors (to merge address and opcodes), and 4 writes | |
5578 | (to store insns). This is a bit excessive. Perhaps a different | |
5579 | mechanism would be better here. | |
5580 | ||
849a528d | 5581 | Emit enough FLUSH insns to synchronize the data and instruction caches. */ |
61a55e8b DE |
5582 | |
5583 | void | |
5584 | sparc_initialize_trampoline (tramp, fnaddr, cxt) | |
5585 | rtx tramp, fnaddr, cxt; | |
5586 | { | |
c6b0465b JC |
5587 | /* SPARC 32 bit trampoline: |
5588 | ||
e0d80184 DM |
5589 | sethi %hi(fn), %g1 |
5590 | sethi %hi(static), %g2 | |
5591 | jmp %g1+%lo(fn) | |
5592 | or %g2, %lo(static), %g2 | |
c6b0465b JC |
5593 | |
5594 | SETHI i,r = 00rr rrr1 00ii iiii iiii iiii iiii iiii | |
5595 | JMPL r+i,d = 10dd ddd1 1100 0rrr rr1i iiii iiii iiii | |
5596 | */ | |
959eb758 DM |
5597 | #ifdef TRANSFER_FROM_TRAMPOLINE |
5598 | emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "__enable_execute_stack"), | |
5599 | 0, VOIDmode, 1, tramp, Pmode); | |
5600 | #endif | |
c6b0465b JC |
5601 | |
5602 | emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 0)), | |
5603 | expand_binop (SImode, ior_optab, | |
5604 | expand_shift (RSHIFT_EXPR, SImode, fnaddr, | |
5605 | size_int (10), 0, 1), | |
5606 | GEN_INT (0x03000000), | |
5607 | NULL_RTX, 1, OPTAB_DIRECT)); | |
5608 | ||
5609 | emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 4)), | |
5610 | expand_binop (SImode, ior_optab, | |
5611 | expand_shift (RSHIFT_EXPR, SImode, cxt, | |
5612 | size_int (10), 0, 1), | |
5613 | GEN_INT (0x05000000), | |
5614 | NULL_RTX, 1, OPTAB_DIRECT)); | |
5615 | ||
5616 | emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 8)), | |
5617 | expand_binop (SImode, ior_optab, | |
5618 | expand_and (fnaddr, GEN_INT (0x3ff), NULL_RTX), | |
5619 | GEN_INT (0x81c06000), | |
5620 | NULL_RTX, 1, OPTAB_DIRECT)); | |
5621 | ||
5622 | emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 12)), | |
5623 | expand_binop (SImode, ior_optab, | |
5624 | expand_and (cxt, GEN_INT (0x3ff), NULL_RTX), | |
5625 | GEN_INT (0x8410a000), | |
5626 | NULL_RTX, 1, OPTAB_DIRECT)); | |
5627 | ||
254110c2 | 5628 | emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode, tramp)))); |
c6b0465b JC |
5629 | /* On UltraSPARC a flush flushes an entire cache line. The trampoline is |
5630 | aligned on a 16 byte boundary so one flush clears it all. */ | |
5631 | if (sparc_cpu != PROCESSOR_ULTRASPARC) | |
5632 | emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode, | |
5633 | plus_constant (tramp, 8))))); | |
61a55e8b DE |
5634 | } |
5635 | ||
849a528d RK |
5636 | /* The 64 bit version is simpler because it makes more sense to load the |
5637 | values as "immediate" data out of the trampoline. It's also easier since | |
5638 | we can read the PC without clobbering a register. */ | |
5639 | ||
61a55e8b DE |
5640 | void |
5641 | sparc64_initialize_trampoline (tramp, fnaddr, cxt) | |
5642 | rtx tramp, fnaddr, cxt; | |
5643 | { | |
345a6161 DM |
5644 | #ifdef TRANSFER_FROM_TRAMPOLINE |
5645 | emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "__enable_execute_stack"), | |
5646 | 0, VOIDmode, 1, tramp, Pmode); | |
5647 | #endif | |
5648 | ||
c6b0465b | 5649 | /* |
e0d80184 DM |
5650 | rd %pc, %g1 |
5651 | ldx [%g1+24], %g5 | |
5652 | jmp %g5 | |
5653 | ldx [%g1+16], %g5 | |
c6b0465b JC |
5654 | +16 bytes data |
5655 | */ | |
5656 | ||
5657 | emit_move_insn (gen_rtx_MEM (SImode, tramp), | |
5658 | GEN_INT (0x83414000)); | |
5659 | emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 4)), | |
5660 | GEN_INT (0xca586018)); | |
5661 | emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 8)), | |
345a6161 | 5662 | GEN_INT (0x81c14000)); |
c6b0465b JC |
5663 | emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 12)), |
5664 | GEN_INT (0xca586010)); | |
5665 | emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 16)), cxt); | |
345a6161 | 5666 | emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 24)), fnaddr); |
254110c2 | 5667 | emit_insn (gen_flush (validize_mem (gen_rtx_MEM (DImode, tramp)))); |
345a6161 | 5668 | |
c6b0465b JC |
5669 | if (sparc_cpu != PROCESSOR_ULTRASPARC) |
5670 | emit_insn (gen_flush (validize_mem (gen_rtx_MEM (DImode, plus_constant (tramp, 8))))); | |
61a55e8b DE |
5671 | } |
5672 | \f | |
c819be5b JW |
5673 | /* Subroutines to support a flat (single) register window calling |
5674 | convention. */ | |
5675 | ||
5676 | /* Single-register window sparc stack frames look like: | |
5677 | ||
5678 | Before call After call | |
5679 | +-----------------------+ +-----------------------+ | |
86735b02 DE |
5680 | high | | | | |
5681 | mem | caller's temps. | | caller's temps. | | |
c819be5b JW |
5682 | | | | | |
5683 | +-----------------------+ +-----------------------+ | |
5684 | | | | | | |
5685 | | arguments on stack. | | arguments on stack. | | |
86735b02 DE |
5686 | | | | | |
5687 | +-----------------------+FP+92->+-----------------------+ | |
c819be5b JW |
5688 | | 6 words to save | | 6 words to save | |
5689 | | arguments passed | | arguments passed | | |
5690 | | in registers, even | | in registers, even | | |
86735b02 DE |
5691 | | if not passed. | | if not passed. | |
5692 | SP+68->+-----------------------+FP+68->+-----------------------+ | |
5693 | | 1 word struct addr | | 1 word struct addr | | |
5694 | +-----------------------+FP+64->+-----------------------+ | |
5695 | | | | | | |
5696 | | 16 word reg save area | | 16 word reg save area | | |
5697 | | | | | | |
5698 | SP->+-----------------------+ FP->+-----------------------+ | |
5699 | | 4 word area for | | |
5700 | | fp/alu reg moves | | |
5701 | FP-16->+-----------------------+ | |
5702 | | | | |
5703 | | local variables | | |
5704 | | | | |
5705 | +-----------------------+ | |
5706 | | | | |
c819be5b | 5707 | | fp register save | |
86735b02 DE |
5708 | | | |
5709 | +-----------------------+ | |
5710 | | | | |
c819be5b JW |
5711 | | gp register save | |
5712 | | | | |
86735b02 DE |
5713 | +-----------------------+ |
5714 | | | | |
c819be5b | 5715 | | alloca allocations | |
86735b02 DE |
5716 | | | |
5717 | +-----------------------+ | |
5718 | | | | |
c819be5b | 5719 | | arguments on stack | |
86735b02 DE |
5720 | | | |
5721 | SP+92->+-----------------------+ | |
c819be5b | 5722 | | 6 words to save | |
86735b02 | 5723 | | arguments passed | |
c819be5b | 5724 | | in registers, even | |
86735b02 DE |
5725 | low | if not passed. | |
5726 | memory SP+68->+-----------------------+ | |
5727 | | 1 word struct addr | | |
5728 | SP+64->+-----------------------+ | |
5729 | | | | |
5730 | I 16 word reg save area | | |
5731 | | | | |
5732 | SP->+-----------------------+ */ | |
c819be5b | 5733 | |
c6aa9ce1 | 5734 | /* Structure to be filled in by sparc_flat_compute_frame_size with register |
c819be5b JW |
5735 | save masks, and offsets for the current function. */ |
5736 | ||
5737 | struct sparc_frame_info | |
5738 | { | |
5739 | unsigned long total_size; /* # bytes that the entire frame takes up. */ | |
5740 | unsigned long var_size; /* # bytes that variables take up. */ | |
5741 | unsigned long args_size; /* # bytes that outgoing arguments take up. */ | |
5742 | unsigned long extra_size; /* # bytes of extra gunk. */ | |
5743 | unsigned int gp_reg_size; /* # bytes needed to store gp regs. */ | |
5744 | unsigned int fp_reg_size; /* # bytes needed to store fp regs. */ | |
86735b02 | 5745 | unsigned long gmask; /* Mask of saved gp registers. */ |
c819be5b | 5746 | unsigned long fmask; /* Mask of saved fp registers. */ |
86735b02 | 5747 | unsigned long reg_offset; /* Offset from new sp to store regs. */ |
c819be5b JW |
5748 | int initialized; /* Nonzero if frame size already calculated. */ |
5749 | }; | |
5750 | ||
c6aa9ce1 | 5751 | /* Current frame information calculated by sparc_flat_compute_frame_size. */ |
c819be5b JW |
5752 | struct sparc_frame_info current_frame_info; |
5753 | ||
5754 | /* Zero structure to initialize current_frame_info. */ | |
5755 | struct sparc_frame_info zero_frame_info; | |
5756 | ||
5757 | /* Tell prologue and epilogue if register REGNO should be saved / restored. */ | |
5758 | ||
86735b02 DE |
5759 | #define RETURN_ADDR_REGNUM 15 |
5760 | #define FRAME_POINTER_MASK (1 << (FRAME_POINTER_REGNUM)) | |
5761 | #define RETURN_ADDR_MASK (1 << (RETURN_ADDR_REGNUM)) | |
5762 | ||
c819be5b JW |
5763 | #define MUST_SAVE_REGISTER(regno) \ |
5764 | ((regs_ever_live[regno] && !call_used_regs[regno]) \ | |
5765 | || (regno == FRAME_POINTER_REGNUM && frame_pointer_needed) \ | |
86735b02 | 5766 | || (regno == RETURN_ADDR_REGNUM && regs_ever_live[RETURN_ADDR_REGNUM])) |
c819be5b JW |
5767 | |
5768 | /* Return the bytes needed to compute the frame pointer from the current | |
5769 | stack pointer. */ | |
5770 | ||
5771 | unsigned long | |
c6aa9ce1 | 5772 | sparc_flat_compute_frame_size (size) |
c819be5b JW |
5773 | int size; /* # of var. bytes allocated. */ |
5774 | { | |
5775 | int regno; | |
5776 | unsigned long total_size; /* # bytes that the entire frame takes up. */ | |
5777 | unsigned long var_size; /* # bytes that variables take up. */ | |
5778 | unsigned long args_size; /* # bytes that outgoing arguments take up. */ | |
5779 | unsigned long extra_size; /* # extra bytes. */ | |
5780 | unsigned int gp_reg_size; /* # bytes needed to store gp regs. */ | |
5781 | unsigned int fp_reg_size; /* # bytes needed to store fp regs. */ | |
86735b02 | 5782 | unsigned long gmask; /* Mask of saved gp registers. */ |
c819be5b | 5783 | unsigned long fmask; /* Mask of saved fp registers. */ |
86735b02 DE |
5784 | unsigned long reg_offset; /* Offset to register save area. */ |
5785 | int need_aligned_p; /* 1 if need the save area 8 byte aligned. */ | |
c819be5b JW |
5786 | |
5787 | /* This is the size of the 16 word reg save area, 1 word struct addr | |
5788 | area, and 4 word fp/alu register copy area. */ | |
8c64be75 SC |
5789 | extra_size = -STARTING_FRAME_OFFSET + FIRST_PARM_OFFSET(0); |
5790 | var_size = size; | |
5791 | gp_reg_size = 0; | |
5792 | fp_reg_size = 0; | |
5793 | gmask = 0; | |
5794 | fmask = 0; | |
5795 | reg_offset = 0; | |
86735b02 | 5796 | need_aligned_p = 0; |
c819be5b | 5797 | |
8c64be75 SC |
5798 | args_size = 0; |
5799 | if (!leaf_function_p ()) | |
5800 | { | |
5801 | /* Also include the size needed for the 6 parameter registers. */ | |
5802 | args_size = current_function_outgoing_args_size + 24; | |
5803 | } | |
5804 | total_size = var_size + args_size; | |
5805 | ||
c819be5b JW |
5806 | /* Calculate space needed for gp registers. */ |
5807 | for (regno = 1; regno <= 31; regno++) | |
5808 | { | |
5809 | if (MUST_SAVE_REGISTER (regno)) | |
5810 | { | |
86735b02 DE |
5811 | /* If we need to save two regs in a row, ensure there's room to bump |
5812 | up the address to align it to a doubleword boundary. */ | |
c819be5b JW |
5813 | if ((regno & 0x1) == 0 && MUST_SAVE_REGISTER (regno+1)) |
5814 | { | |
5815 | if (gp_reg_size % 8 != 0) | |
86735b02 | 5816 | gp_reg_size += 4; |
c819be5b | 5817 | gp_reg_size += 2 * UNITS_PER_WORD; |
86735b02 | 5818 | gmask |= 3 << regno; |
c819be5b | 5819 | regno++; |
86735b02 | 5820 | need_aligned_p = 1; |
c819be5b JW |
5821 | } |
5822 | else | |
5823 | { | |
5824 | gp_reg_size += UNITS_PER_WORD; | |
86735b02 | 5825 | gmask |= 1 << regno; |
c819be5b JW |
5826 | } |
5827 | } | |
5828 | } | |
c819be5b JW |
5829 | |
5830 | /* Calculate space needed for fp registers. */ | |
5831 | for (regno = 32; regno <= 63; regno++) | |
5832 | { | |
5833 | if (regs_ever_live[regno] && !call_used_regs[regno]) | |
5834 | { | |
5835 | fp_reg_size += UNITS_PER_WORD; | |
5836 | fmask |= 1 << (regno - 32); | |
5837 | } | |
5838 | } | |
5839 | ||
86735b02 DE |
5840 | if (gmask || fmask) |
5841 | { | |
5842 | int n; | |
5843 | reg_offset = FIRST_PARM_OFFSET(0) + args_size; | |
5844 | /* Ensure save area is 8 byte aligned if we need it. */ | |
5845 | n = reg_offset % 8; | |
5846 | if (need_aligned_p && n != 0) | |
5847 | { | |
5848 | total_size += 8 - n; | |
5849 | reg_offset += 8 - n; | |
5850 | } | |
5851 | total_size += gp_reg_size + fp_reg_size; | |
5852 | } | |
c819be5b | 5853 | |
8c64be75 SC |
5854 | /* If we must allocate a stack frame at all, we must also allocate |
5855 | room for register window spillage, so as to be binary compatible | |
5856 | with libraries and operating systems that do not use -mflat. */ | |
5857 | if (total_size > 0) | |
5858 | total_size += extra_size; | |
5859 | else | |
5860 | extra_size = 0; | |
c819be5b JW |
5861 | |
5862 | total_size = SPARC_STACK_ALIGN (total_size); | |
5863 | ||
5864 | /* Save other computed information. */ | |
5865 | current_frame_info.total_size = total_size; | |
5866 | current_frame_info.var_size = var_size; | |
5867 | current_frame_info.args_size = args_size; | |
5868 | current_frame_info.extra_size = extra_size; | |
5869 | current_frame_info.gp_reg_size = gp_reg_size; | |
5870 | current_frame_info.fp_reg_size = fp_reg_size; | |
86735b02 | 5871 | current_frame_info.gmask = gmask; |
c819be5b | 5872 | current_frame_info.fmask = fmask; |
86735b02 | 5873 | current_frame_info.reg_offset = reg_offset; |
c819be5b JW |
5874 | current_frame_info.initialized = reload_completed; |
5875 | ||
c819be5b JW |
5876 | /* Ok, we're done. */ |
5877 | return total_size; | |
5878 | } | |
5879 | \f | |
86735b02 DE |
5880 | /* Save/restore registers in GMASK and FMASK at register BASE_REG plus offset |
5881 | OFFSET. | |
5882 | ||
5883 | BASE_REG must be 8 byte aligned. This allows us to test OFFSET for | |
5884 | appropriate alignment and use DOUBLEWORD_OP when we can. We assume | |
5885 | [BASE_REG+OFFSET] will always be a valid address. | |
5886 | ||
5887 | WORD_OP is either "st" for save, "ld" for restore. | |
5888 | DOUBLEWORD_OP is either "std" for save, "ldd" for restore. */ | |
c819be5b JW |
5889 | |
5890 | void | |
96987e96 DE |
5891 | sparc_flat_save_restore (file, base_reg, offset, gmask, fmask, word_op, |
5892 | doubleword_op, base_offset) | |
86735b02 | 5893 | FILE *file; |
b1474bb7 | 5894 | const char *base_reg; |
86735b02 DE |
5895 | unsigned int offset; |
5896 | unsigned long gmask; | |
5897 | unsigned long fmask; | |
b1474bb7 KG |
5898 | const char *word_op; |
5899 | const char *doubleword_op; | |
c53aa195 | 5900 | unsigned long base_offset; |
c819be5b JW |
5901 | { |
5902 | int regno; | |
c819be5b | 5903 | |
86735b02 DE |
5904 | if (gmask == 0 && fmask == 0) |
5905 | return; | |
c819be5b | 5906 | |
86735b02 DE |
5907 | /* Save registers starting from high to low. We've already saved the |
5908 | previous frame pointer and previous return address for the debugger's | |
5909 | sake. The debugger allows us to not need a nop in the epilog if at least | |
5910 | one register is reloaded in addition to return address. */ | |
c819be5b | 5911 | |
86735b02 | 5912 | if (gmask) |
c819be5b JW |
5913 | { |
5914 | for (regno = 1; regno <= 31; regno++) | |
5915 | { | |
86735b02 | 5916 | if ((gmask & (1L << regno)) != 0) |
c819be5b | 5917 | { |
86735b02 | 5918 | if ((regno & 0x1) == 0 && ((gmask & (1L << (regno+1))) != 0)) |
c819be5b | 5919 | { |
86735b02 DE |
5920 | /* We can save two registers in a row. If we're not at a |
5921 | double word boundary, move to one. | |
5922 | sparc_flat_compute_frame_size ensures there's room to do | |
5923 | this. */ | |
5924 | if (offset % 8 != 0) | |
5925 | offset += UNITS_PER_WORD; | |
5926 | ||
c819be5b | 5927 | if (word_op[0] == 's') |
c53aa195 | 5928 | { |
e0d80184 | 5929 | fprintf (file, "\t%s\t%s, [%s+%d]\n", |
c53aa195 JM |
5930 | doubleword_op, reg_names[regno], |
5931 | base_reg, offset); | |
0021b564 | 5932 | if (dwarf2out_do_frame ()) |
c53aa195 | 5933 | { |
96987e96 | 5934 | char *l = dwarf2out_cfi_label (); |
c53aa195 JM |
5935 | dwarf2out_reg_save (l, regno, offset + base_offset); |
5936 | dwarf2out_reg_save | |
5937 | (l, regno+1, offset+base_offset + UNITS_PER_WORD); | |
5938 | } | |
c53aa195 | 5939 | } |
c819be5b | 5940 | else |
e0d80184 | 5941 | fprintf (file, "\t%s\t[%s+%d], %s\n", |
86735b02 | 5942 | doubleword_op, base_reg, offset, |
c819be5b JW |
5943 | reg_names[regno]); |
5944 | ||
86735b02 | 5945 | offset += 2 * UNITS_PER_WORD; |
c819be5b JW |
5946 | regno++; |
5947 | } | |
5948 | else | |
5949 | { | |
5950 | if (word_op[0] == 's') | |
c53aa195 | 5951 | { |
e0d80184 | 5952 | fprintf (file, "\t%s\t%s, [%s+%d]\n", |
c53aa195 JM |
5953 | word_op, reg_names[regno], |
5954 | base_reg, offset); | |
0021b564 | 5955 | if (dwarf2out_do_frame ()) |
c53aa195 | 5956 | dwarf2out_reg_save ("", regno, offset + base_offset); |
c53aa195 | 5957 | } |
c819be5b | 5958 | else |
e0d80184 | 5959 | fprintf (file, "\t%s\t[%s+%d], %s\n", |
86735b02 | 5960 | word_op, base_reg, offset, reg_names[regno]); |
c819be5b | 5961 | |
86735b02 | 5962 | offset += UNITS_PER_WORD; |
c819be5b JW |
5963 | } |
5964 | } | |
5965 | } | |
5966 | } | |
5967 | ||
5968 | if (fmask) | |
5969 | { | |
5970 | for (regno = 32; regno <= 63; regno++) | |
5971 | { | |
5972 | if ((fmask & (1L << (regno - 32))) != 0) | |
5973 | { | |
5974 | if (word_op[0] == 's') | |
c53aa195 | 5975 | { |
e0d80184 | 5976 | fprintf (file, "\t%s\t%s, [%s+%d]\n", |
c53aa195 JM |
5977 | word_op, reg_names[regno], |
5978 | base_reg, offset); | |
0021b564 | 5979 | if (dwarf2out_do_frame ()) |
c53aa195 | 5980 | dwarf2out_reg_save ("", regno, offset + base_offset); |
c53aa195 | 5981 | } |
c819be5b | 5982 | else |
e0d80184 | 5983 | fprintf (file, "\t%s\t[%s+%d], %s\n", |
86735b02 | 5984 | word_op, base_reg, offset, reg_names[regno]); |
c819be5b | 5985 | |
86735b02 | 5986 | offset += UNITS_PER_WORD; |
c819be5b JW |
5987 | } |
5988 | } | |
5989 | } | |
5990 | } | |
5991 | \f | |
5992 | /* Set up the stack and frame (if desired) for the function. */ | |
5993 | ||
5994 | void | |
c6aa9ce1 | 5995 | sparc_flat_output_function_prologue (file, size) |
c819be5b JW |
5996 | FILE *file; |
5997 | int size; | |
5998 | { | |
99f44eba | 5999 | const char *sp_str = reg_names[STACK_POINTER_REGNUM]; |
86735b02 | 6000 | unsigned long gmask = current_frame_info.gmask; |
a07c1915 | 6001 | |
1cb36a98 RH |
6002 | sparc_output_scratch_registers (file); |
6003 | ||
c6aa9ce1 | 6004 | /* This is only for the human reader. */ |
bf62bbf1 | 6005 | fprintf (file, "\t%s#PROLOGUE# 0\n", ASM_COMMENT_START); |
5e9defae | 6006 | fprintf (file, "\t%s# vars= %ld, regs= %d/%d, args= %d, extra= %ld\n", |
bf62bbf1 | 6007 | ASM_COMMENT_START, |
86735b02 DE |
6008 | current_frame_info.var_size, |
6009 | current_frame_info.gp_reg_size / 4, | |
9f8b85b8 | 6010 | current_frame_info.fp_reg_size / 4, |
86735b02 DE |
6011 | current_function_outgoing_args_size, |
6012 | current_frame_info.extra_size); | |
c819be5b JW |
6013 | |
6014 | size = SPARC_STACK_ALIGN (size); | |
86735b02 DE |
6015 | size = (! current_frame_info.initialized |
6016 | ? sparc_flat_compute_frame_size (size) | |
6017 | : current_frame_info.total_size); | |
c819be5b | 6018 | |
86735b02 DE |
6019 | /* These cases shouldn't happen. Catch them now. */ |
6020 | if (size == 0 && (gmask || current_frame_info.fmask)) | |
6021 | abort (); | |
c819be5b | 6022 | |
86735b02 DE |
6023 | /* Allocate our stack frame by decrementing %sp. |
6024 | At present, the only algorithm gdb can use to determine if this is a | |
6025 | flat frame is if we always set %i7 if we set %sp. This can be optimized | |
6026 | in the future by putting in some sort of debugging information that says | |
6027 | this is a `flat' function. However, there is still the case of debugging | |
6028 | code without such debugging information (including cases where most fns | |
6029 | have such info, but there is one that doesn't). So, always do this now | |
6030 | so we don't get a lot of code out there that gdb can't handle. | |
6031 | If the frame pointer isn't needn't then that's ok - gdb won't be able to | |
6032 | distinguish us from a non-flat function but there won't (and shouldn't) | |
6033 | be any differences anyway. The return pc is saved (if necessary) right | |
6034 | after %i7 so gdb won't have to look too far to find it. */ | |
6035 | if (size > 0) | |
c819be5b | 6036 | { |
86735b02 | 6037 | unsigned int reg_offset = current_frame_info.reg_offset; |
99f44eba | 6038 | const char *fp_str = reg_names[FRAME_POINTER_REGNUM]; |
3bb5de61 | 6039 | const char *t1_str = "%g1"; |
86735b02 DE |
6040 | |
6041 | /* Things get a little tricky if local variables take up more than ~4096 | |
6042 | bytes and outgoing arguments take up more than ~4096 bytes. When that | |
6043 | happens, the register save area can't be accessed from either end of | |
6044 | the frame. Handle this by decrementing %sp to the start of the gp | |
6045 | register save area, save the regs, update %i7, and then set %sp to its | |
6046 | final value. Given that we only have one scratch register to play | |
6047 | with it is the cheapest solution, and it helps gdb out as it won't | |
6048 | slow down recognition of flat functions. | |
6049 | Don't change the order of insns emitted here without checking with | |
6050 | the gdb folk first. */ | |
6051 | ||
ddd5a7c1 | 6052 | /* Is the entire register save area offsettable from %sp? */ |
86735b02 DE |
6053 | if (reg_offset < 4096 - 64 * UNITS_PER_WORD) |
6054 | { | |
6055 | if (size <= 4096) | |
6056 | { | |
e0d80184 | 6057 | fprintf (file, "\tadd\t%s, %d, %s\n", |
86735b02 DE |
6058 | sp_str, -size, sp_str); |
6059 | if (gmask & FRAME_POINTER_MASK) | |
6060 | { | |
e0d80184 | 6061 | fprintf (file, "\tst\t%s, [%s+%d]\n", |
86735b02 | 6062 | fp_str, sp_str, reg_offset); |
e0d80184 | 6063 | fprintf (file, "\tsub\t%s, %d, %s\t%s# set up frame pointer\n", |
bf62bbf1 | 6064 | sp_str, -size, fp_str, ASM_COMMENT_START); |
86735b02 DE |
6065 | reg_offset += 4; |
6066 | } | |
6067 | } | |
6068 | else | |
6069 | { | |
e0d80184 | 6070 | fprintf (file, "\tset\t%d, %s\n\tsub\t%s, %s, %s\n", |
86735b02 DE |
6071 | size, t1_str, sp_str, t1_str, sp_str); |
6072 | if (gmask & FRAME_POINTER_MASK) | |
6073 | { | |
e0d80184 | 6074 | fprintf (file, "\tst\t%s, [%s+%d]\n", |
86735b02 | 6075 | fp_str, sp_str, reg_offset); |
e0d80184 | 6076 | fprintf (file, "\tadd\t%s, %s, %s\t%s# set up frame pointer\n", |
bf62bbf1 | 6077 | sp_str, t1_str, fp_str, ASM_COMMENT_START); |
86735b02 DE |
6078 | reg_offset += 4; |
6079 | } | |
6080 | } | |
0021b564 | 6081 | if (dwarf2out_do_frame ()) |
c53aa195 | 6082 | { |
96987e96 | 6083 | char *l = dwarf2out_cfi_label (); |
c53aa195 JM |
6084 | if (gmask & FRAME_POINTER_MASK) |
6085 | { | |
6086 | dwarf2out_reg_save (l, FRAME_POINTER_REGNUM, | |
6087 | reg_offset - 4 - size); | |
6088 | dwarf2out_def_cfa (l, FRAME_POINTER_REGNUM, 0); | |
6089 | } | |
6090 | else | |
6091 | dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, size); | |
6092 | } | |
86735b02 DE |
6093 | if (gmask & RETURN_ADDR_MASK) |
6094 | { | |
e0d80184 | 6095 | fprintf (file, "\tst\t%s, [%s+%d]\n", |
86735b02 | 6096 | reg_names[RETURN_ADDR_REGNUM], sp_str, reg_offset); |
0021b564 | 6097 | if (dwarf2out_do_frame ()) |
c53aa195 | 6098 | dwarf2out_return_save ("", reg_offset - size); |
86735b02 DE |
6099 | reg_offset += 4; |
6100 | } | |
6101 | sparc_flat_save_restore (file, sp_str, reg_offset, | |
6102 | gmask & ~(FRAME_POINTER_MASK | RETURN_ADDR_MASK), | |
6103 | current_frame_info.fmask, | |
84e884e9 | 6104 | "st", "std", -size); |
86735b02 | 6105 | } |
c819be5b | 6106 | else |
86735b02 DE |
6107 | { |
6108 | /* Subtract %sp in two steps, but make sure there is always a | |
6109 | 64 byte register save area, and %sp is properly aligned. */ | |
6110 | /* Amount to decrement %sp by, the first time. */ | |
6111 | unsigned int size1 = ((size - reg_offset + 64) + 15) & -16; | |
6112 | /* Offset to register save area from %sp. */ | |
6113 | unsigned int offset = size1 - (size - reg_offset); | |
6114 | ||
6115 | if (size1 <= 4096) | |
6116 | { | |
e0d80184 | 6117 | fprintf (file, "\tadd\t%s, %d, %s\n", |
86735b02 DE |
6118 | sp_str, -size1, sp_str); |
6119 | if (gmask & FRAME_POINTER_MASK) | |
6120 | { | |
e0d80184 | 6121 | fprintf (file, "\tst\t%s, [%s+%d]\n\tsub\t%s, %d, %s\t%s# set up frame pointer\n", |
bf62bbf1 DE |
6122 | fp_str, sp_str, offset, sp_str, -size1, fp_str, |
6123 | ASM_COMMENT_START); | |
86735b02 DE |
6124 | offset += 4; |
6125 | } | |
6126 | } | |
6127 | else | |
6128 | { | |
e0d80184 | 6129 | fprintf (file, "\tset\t%d, %s\n\tsub\t%s, %s, %s\n", |
86735b02 DE |
6130 | size1, t1_str, sp_str, t1_str, sp_str); |
6131 | if (gmask & FRAME_POINTER_MASK) | |
6132 | { | |
e0d80184 | 6133 | fprintf (file, "\tst\t%s, [%s+%d]\n\tadd\t%s, %s, %s\t%s# set up frame pointer\n", |
bf62bbf1 DE |
6134 | fp_str, sp_str, offset, sp_str, t1_str, fp_str, |
6135 | ASM_COMMENT_START); | |
86735b02 DE |
6136 | offset += 4; |
6137 | } | |
6138 | } | |
0021b564 | 6139 | if (dwarf2out_do_frame ()) |
c53aa195 | 6140 | { |
96987e96 | 6141 | char *l = dwarf2out_cfi_label (); |
c53aa195 JM |
6142 | if (gmask & FRAME_POINTER_MASK) |
6143 | { | |
6144 | dwarf2out_reg_save (l, FRAME_POINTER_REGNUM, | |
6145 | offset - 4 - size1); | |
6146 | dwarf2out_def_cfa (l, FRAME_POINTER_REGNUM, 0); | |
6147 | } | |
6148 | else | |
6149 | dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, size1); | |
6150 | } | |
86735b02 DE |
6151 | if (gmask & RETURN_ADDR_MASK) |
6152 | { | |
e0d80184 | 6153 | fprintf (file, "\tst\t%s, [%s+%d]\n", |
86735b02 | 6154 | reg_names[RETURN_ADDR_REGNUM], sp_str, offset); |
0021b564 | 6155 | if (dwarf2out_do_frame ()) |
c53aa195 JM |
6156 | /* offset - size1 == reg_offset - size |
6157 | if reg_offset were updated above like offset. */ | |
6158 | dwarf2out_return_save ("", offset - size1); | |
86735b02 DE |
6159 | offset += 4; |
6160 | } | |
6161 | sparc_flat_save_restore (file, sp_str, offset, | |
6162 | gmask & ~(FRAME_POINTER_MASK | RETURN_ADDR_MASK), | |
6163 | current_frame_info.fmask, | |
84e884e9 | 6164 | "st", "std", -size1); |
e0d80184 | 6165 | fprintf (file, "\tset\t%d, %s\n\tsub\t%s, %s, %s\n", |
86735b02 | 6166 | size - size1, t1_str, sp_str, t1_str, sp_str); |
0021b564 | 6167 | if (dwarf2out_do_frame ()) |
c53aa195 JM |
6168 | if (! (gmask & FRAME_POINTER_MASK)) |
6169 | dwarf2out_def_cfa ("", STACK_POINTER_REGNUM, size); | |
86735b02 | 6170 | } |
c819be5b | 6171 | } |
c6aa9ce1 | 6172 | |
bf62bbf1 | 6173 | fprintf (file, "\t%s#PROLOGUE# 1\n", ASM_COMMENT_START); |
c819be5b JW |
6174 | } |
6175 | \f | |
6176 | /* Do any necessary cleanup after a function to restore stack, frame, | |
6177 | and regs. */ | |
6178 | ||
6179 | void | |
c6aa9ce1 | 6180 | sparc_flat_output_function_epilogue (file, size) |
c819be5b JW |
6181 | FILE *file; |
6182 | int size; | |
6183 | { | |
c819be5b JW |
6184 | rtx epilogue_delay = current_function_epilogue_delay_list; |
6185 | int noepilogue = FALSE; | |
c819be5b | 6186 | |
c6aa9ce1 | 6187 | /* This is only for the human reader. */ |
bf62bbf1 | 6188 | fprintf (file, "\t%s#EPILOGUE#\n", ASM_COMMENT_START); |
c6aa9ce1 | 6189 | |
c819be5b JW |
6190 | /* The epilogue does not depend on any registers, but the stack |
6191 | registers, so we assume that if we have 1 pending nop, it can be | |
6192 | ignored, and 2 it must be filled (2 nops occur for integer | |
6193 | multiply and divide). */ | |
6194 | ||
6195 | size = SPARC_STACK_ALIGN (size); | |
86735b02 | 6196 | size = (!current_frame_info.initialized |
c6aa9ce1 | 6197 | ? sparc_flat_compute_frame_size (size) |
c819be5b JW |
6198 | : current_frame_info.total_size); |
6199 | ||
86735b02 | 6200 | if (size == 0 && epilogue_delay == 0) |
c819be5b JW |
6201 | { |
6202 | rtx insn = get_last_insn (); | |
6203 | ||
6204 | /* If the last insn was a BARRIER, we don't have to write any code | |
6205 | because a jump (aka return) was put there. */ | |
6206 | if (GET_CODE (insn) == NOTE) | |
6207 | insn = prev_nonnote_insn (insn); | |
6208 | if (insn && GET_CODE (insn) == BARRIER) | |
6209 | noepilogue = TRUE; | |
6210 | } | |
6211 | ||
6212 | if (!noepilogue) | |
6213 | { | |
86735b02 DE |
6214 | unsigned int reg_offset = current_frame_info.reg_offset; |
6215 | unsigned int size1; | |
99f44eba KG |
6216 | const char *sp_str = reg_names[STACK_POINTER_REGNUM]; |
6217 | const char *fp_str = reg_names[FRAME_POINTER_REGNUM]; | |
3bb5de61 | 6218 | const char *t1_str = "%g1"; |
86735b02 | 6219 | |
c819be5b JW |
6220 | /* In the reload sequence, we don't need to fill the load delay |
6221 | slots for most of the loads, also see if we can fill the final | |
6222 | delay slot if not otherwise filled by the reload sequence. */ | |
6223 | ||
86735b02 | 6224 | if (size > 4095) |
e0d80184 | 6225 | fprintf (file, "\tset\t%d, %s\n", size, t1_str); |
c819be5b JW |
6226 | |
6227 | if (frame_pointer_needed) | |
6228 | { | |
86735b02 | 6229 | if (size > 4095) |
e0d80184 | 6230 | fprintf (file,"\tsub\t%s, %s, %s\t\t%s# sp not trusted here\n", |
bf62bbf1 | 6231 | fp_str, t1_str, sp_str, ASM_COMMENT_START); |
c819be5b | 6232 | else |
e0d80184 | 6233 | fprintf (file,"\tsub\t%s, %d, %s\t\t%s# sp not trusted here\n", |
bf62bbf1 | 6234 | fp_str, size, sp_str, ASM_COMMENT_START); |
c819be5b JW |
6235 | } |
6236 | ||
ddd5a7c1 | 6237 | /* Is the entire register save area offsettable from %sp? */ |
86735b02 DE |
6238 | if (reg_offset < 4096 - 64 * UNITS_PER_WORD) |
6239 | { | |
6240 | size1 = 0; | |
6241 | } | |
6242 | else | |
6243 | { | |
6244 | /* Restore %sp in two steps, but make sure there is always a | |
6245 | 64 byte register save area, and %sp is properly aligned. */ | |
6246 | /* Amount to increment %sp by, the first time. */ | |
6247 | size1 = ((reg_offset - 64 - 16) + 15) & -16; | |
6248 | /* Offset to register save area from %sp. */ | |
6249 | reg_offset = size1 - reg_offset; | |
6250 | ||
e0d80184 | 6251 | fprintf (file, "\tset\t%d, %s\n\tadd\t%s, %s, %s\n", |
86735b02 DE |
6252 | size1, t1_str, sp_str, t1_str, sp_str); |
6253 | } | |
6254 | ||
6255 | /* We must restore the frame pointer and return address reg first | |
6256 | because they are treated specially by the prologue output code. */ | |
6257 | if (current_frame_info.gmask & FRAME_POINTER_MASK) | |
6258 | { | |
e0d80184 | 6259 | fprintf (file, "\tld\t[%s+%d], %s\n", |
86735b02 DE |
6260 | sp_str, reg_offset, fp_str); |
6261 | reg_offset += 4; | |
6262 | } | |
6263 | if (current_frame_info.gmask & RETURN_ADDR_MASK) | |
6264 | { | |
e0d80184 | 6265 | fprintf (file, "\tld\t[%s+%d], %s\n", |
86735b02 DE |
6266 | sp_str, reg_offset, reg_names[RETURN_ADDR_REGNUM]); |
6267 | reg_offset += 4; | |
6268 | } | |
6269 | ||
6270 | /* Restore any remaining saved registers. */ | |
6271 | sparc_flat_save_restore (file, sp_str, reg_offset, | |
6272 | current_frame_info.gmask & ~(FRAME_POINTER_MASK | RETURN_ADDR_MASK), | |
6273 | current_frame_info.fmask, | |
c53aa195 | 6274 | "ld", "ldd", 0); |
86735b02 DE |
6275 | |
6276 | /* If we had to increment %sp in two steps, record it so the second | |
6277 | restoration in the epilogue finishes up. */ | |
6278 | if (size1 > 0) | |
6279 | { | |
6280 | size -= size1; | |
6281 | if (size > 4095) | |
e0d80184 | 6282 | fprintf (file, "\tset\t%d, %s\n", |
86735b02 DE |
6283 | size, t1_str); |
6284 | } | |
c819be5b | 6285 | |
c819be5b | 6286 | if (current_function_returns_struct) |
e0d80184 | 6287 | fprintf (file, "\tjmp\t%%o7+12\n"); |
c819be5b JW |
6288 | else |
6289 | fprintf (file, "\tretl\n"); | |
6290 | ||
6291 | /* If the only register saved is the return address, we need a | |
6292 | nop, unless we have an instruction to put into it. Otherwise | |
6293 | we don't since reloading multiple registers doesn't reference | |
6294 | the register being loaded. */ | |
6295 | ||
6296 | if (epilogue_delay) | |
6297 | { | |
86735b02 | 6298 | if (size) |
c819be5b JW |
6299 | abort (); |
6300 | final_scan_insn (XEXP (epilogue_delay, 0), file, 1, -2, 1); | |
6301 | } | |
6302 | ||
86735b02 | 6303 | else if (size > 4095) |
e0d80184 | 6304 | fprintf (file, "\tadd\t%s, %s, %s\n", sp_str, t1_str, sp_str); |
c819be5b | 6305 | |
86735b02 | 6306 | else if (size > 0) |
e0d80184 | 6307 | fprintf (file, "\tadd\t%s, %d, %s\n", sp_str, size, sp_str); |
c819be5b JW |
6308 | |
6309 | else | |
6310 | fprintf (file, "\tnop\n"); | |
6311 | } | |
6312 | ||
6313 | /* Reset state info for each function. */ | |
6314 | current_frame_info = zero_frame_info; | |
e0d80184 DM |
6315 | |
6316 | sparc_output_deferred_case_vectors (); | |
c819be5b JW |
6317 | } |
6318 | \f | |
6319 | /* Define the number of delay slots needed for the function epilogue. | |
6320 | ||
6321 | On the sparc, we need a slot if either no stack has been allocated, | |
6322 | or the only register saved is the return register. */ | |
6323 | ||
6324 | int | |
c6aa9ce1 | 6325 | sparc_flat_epilogue_delay_slots () |
c819be5b JW |
6326 | { |
6327 | if (!current_frame_info.initialized) | |
c6aa9ce1 | 6328 | (void) sparc_flat_compute_frame_size (get_frame_size ()); |
c819be5b JW |
6329 | |
6330 | if (current_frame_info.total_size == 0) | |
6331 | return 1; | |
6332 | ||
c819be5b JW |
6333 | return 0; |
6334 | } | |
6335 | ||
6336 | /* Return true is TRIAL is a valid insn for the epilogue delay slot. | |
6337 | Any single length instruction which doesn't reference the stack or frame | |
6338 | pointer is OK. */ | |
6339 | ||
6340 | int | |
c6aa9ce1 | 6341 | sparc_flat_eligible_for_epilogue_delay (trial, slot) |
c819be5b | 6342 | rtx trial; |
db3d4438 | 6343 | int slot ATTRIBUTE_UNUSED; |
c819be5b | 6344 | { |
c4ce6853 DE |
6345 | rtx pat = PATTERN (trial); |
6346 | ||
6347 | if (get_attr_length (trial) != 1) | |
6348 | return 0; | |
6349 | ||
6350 | /* If %g0 is live, there are lots of things we can't handle. | |
6351 | Rather than trying to find them all now, let's punt and only | |
6352 | optimize things as necessary. */ | |
6353 | if (TARGET_LIVE_G0) | |
6354 | return 0; | |
6355 | ||
6356 | if (! reg_mentioned_p (stack_pointer_rtx, pat) | |
6357 | && ! reg_mentioned_p (frame_pointer_rtx, pat)) | |
c819be5b | 6358 | return 1; |
c4ce6853 | 6359 | |
c819be5b JW |
6360 | return 0; |
6361 | } | |
dbb54862 JW |
6362 | \f |
6363 | /* Adjust the cost of a scheduling dependency. Return the new cost of | |
6364 | a dependency LINK or INSN on DEP_INSN. COST is the current cost. */ | |
6365 | ||
8947065c | 6366 | static int |
dbb54862 JW |
6367 | supersparc_adjust_cost (insn, link, dep_insn, cost) |
6368 | rtx insn; | |
6369 | rtx link; | |
6370 | rtx dep_insn; | |
6371 | int cost; | |
6372 | { | |
6373 | enum attr_type insn_type; | |
6374 | ||
6375 | if (! recog_memoized (insn)) | |
6376 | return 0; | |
6377 | ||
6378 | insn_type = get_attr_type (insn); | |
6379 | ||
6380 | if (REG_NOTE_KIND (link) == 0) | |
6381 | { | |
6382 | /* Data dependency; DEP_INSN writes a register that INSN reads some | |
6383 | cycles later. */ | |
6384 | ||
6385 | /* if a load, then the dependence must be on the memory address; | |
3bc8b61e DM |
6386 | add an extra "cycle". Note that the cost could be two cycles |
6387 | if the reg was written late in an instruction group; we ca not tell | |
dbb54862 JW |
6388 | here. */ |
6389 | if (insn_type == TYPE_LOAD || insn_type == TYPE_FPLOAD) | |
6390 | return cost + 3; | |
6391 | ||
6392 | /* Get the delay only if the address of the store is the dependence. */ | |
6393 | if (insn_type == TYPE_STORE || insn_type == TYPE_FPSTORE) | |
6394 | { | |
6395 | rtx pat = PATTERN(insn); | |
6396 | rtx dep_pat = PATTERN (dep_insn); | |
6397 | ||
6398 | if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET) | |
3bc8b61e | 6399 | return cost; /* This should not happen! */ |
dbb54862 JW |
6400 | |
6401 | /* The dependency between the two instructions was on the data that | |
6402 | is being stored. Assume that this implies that the address of the | |
6403 | store is not dependent. */ | |
6404 | if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat))) | |
6405 | return cost; | |
6406 | ||
6407 | return cost + 3; /* An approximation. */ | |
6408 | } | |
6409 | ||
6410 | /* A shift instruction cannot receive its data from an instruction | |
6411 | in the same cycle; add a one cycle penalty. */ | |
6412 | if (insn_type == TYPE_SHIFT) | |
6413 | return cost + 3; /* Split before cascade into shift. */ | |
6414 | } | |
6415 | else | |
6416 | { | |
6417 | /* Anti- or output- dependency; DEP_INSN reads/writes a register that | |
6418 | INSN writes some cycles later. */ | |
6419 | ||
6420 | /* These are only significant for the fpu unit; writing a fp reg before | |
6421 | the fpu has finished with it stalls the processor. */ | |
6422 | ||
6423 | /* Reusing an integer register causes no problems. */ | |
6424 | if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT) | |
6425 | return 0; | |
6426 | } | |
6427 | ||
6428 | return cost; | |
6429 | } | |
bfd6bc60 | 6430 | |
8947065c RH |
6431 | static int |
6432 | hypersparc_adjust_cost (insn, link, dep_insn, cost) | |
6433 | rtx insn; | |
6434 | rtx link; | |
6435 | rtx dep_insn; | |
6436 | int cost; | |
6437 | { | |
6438 | enum attr_type insn_type, dep_type; | |
6439 | rtx pat = PATTERN(insn); | |
6440 | rtx dep_pat = PATTERN (dep_insn); | |
6441 | ||
6442 | if (recog_memoized (insn) < 0 || recog_memoized (dep_insn) < 0) | |
6443 | return cost; | |
6444 | ||
6445 | insn_type = get_attr_type (insn); | |
6446 | dep_type = get_attr_type (dep_insn); | |
6447 | ||
6448 | switch (REG_NOTE_KIND (link)) | |
6449 | { | |
6450 | case 0: | |
6451 | /* Data dependency; DEP_INSN writes a register that INSN reads some | |
6452 | cycles later. */ | |
6453 | ||
6454 | switch (insn_type) | |
6455 | { | |
6456 | case TYPE_STORE: | |
6457 | case TYPE_FPSTORE: | |
6458 | /* Get the delay iff the address of the store is the dependence. */ | |
6459 | if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET) | |
6460 | return cost; | |
6461 | ||
6462 | if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat))) | |
6463 | return cost; | |
6464 | return cost + 3; | |
6465 | ||
6466 | case TYPE_LOAD: | |
6467 | case TYPE_SLOAD: | |
6468 | case TYPE_FPLOAD: | |
6469 | /* If a load, then the dependence must be on the memory address. If | |
6470 | the addresses aren't equal, then it might be a false dependency */ | |
6471 | if (dep_type == TYPE_STORE || dep_type == TYPE_FPSTORE) | |
6472 | { | |
6473 | if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET | |
6474 | || GET_CODE (SET_DEST (dep_pat)) != MEM | |
6475 | || GET_CODE (SET_SRC (pat)) != MEM | |
6476 | || ! rtx_equal_p (XEXP (SET_DEST (dep_pat), 0), | |
6477 | XEXP (SET_SRC (pat), 0))) | |
6478 | return cost + 2; | |
6479 | ||
6480 | return cost + 8; | |
6481 | } | |
6482 | break; | |
6483 | ||
6484 | case TYPE_BRANCH: | |
6485 | /* Compare to branch latency is 0. There is no benefit from | |
6486 | separating compare and branch. */ | |
6487 | if (dep_type == TYPE_COMPARE) | |
6488 | return 0; | |
6489 | /* Floating point compare to branch latency is less than | |
6490 | compare to conditional move. */ | |
6491 | if (dep_type == TYPE_FPCMP) | |
6492 | return cost - 1; | |
6493 | break; | |
3bb5de61 KG |
6494 | default: |
6495 | break; | |
8947065c RH |
6496 | } |
6497 | break; | |
6498 | ||
6499 | case REG_DEP_ANTI: | |
6500 | /* Anti-dependencies only penalize the fpu unit. */ | |
6501 | if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT) | |
6502 | return 0; | |
6503 | break; | |
6504 | ||
6505 | default: | |
6506 | break; | |
6507 | } | |
6508 | ||
6509 | return cost; | |
6510 | } | |
6511 | ||
6512 | static int | |
6513 | ultrasparc_adjust_cost (insn, link, dep_insn, cost) | |
6514 | rtx insn; | |
6515 | rtx link; | |
6516 | rtx dep_insn; | |
6517 | int cost; | |
6518 | { | |
6519 | enum attr_type insn_type, dep_type; | |
6520 | rtx pat = PATTERN(insn); | |
6521 | rtx dep_pat = PATTERN (dep_insn); | |
6522 | ||
6523 | if (recog_memoized (insn) < 0 || recog_memoized (dep_insn) < 0) | |
6524 | return cost; | |
6525 | ||
6526 | insn_type = get_attr_type (insn); | |
6527 | dep_type = get_attr_type (dep_insn); | |
6528 | ||
6529 | /* Nothing issues in parallel with integer multiplies, so | |
6530 | mark as zero cost since the scheduler can not do anything | |
6531 | about it. */ | |
6532 | if (insn_type == TYPE_IMUL) | |
6533 | return 0; | |
6534 | ||
6535 | #define SLOW_FP(dep_type) \ | |
c0ec7a75 DM |
6536 | (dep_type == TYPE_FPSQRTS || dep_type == TYPE_FPSQRTD || \ |
6537 | dep_type == TYPE_FPDIVS || dep_type == TYPE_FPDIVD) | |
8947065c RH |
6538 | |
6539 | switch (REG_NOTE_KIND (link)) | |
6540 | { | |
6541 | case 0: | |
6542 | /* Data dependency; DEP_INSN writes a register that INSN reads some | |
6543 | cycles later. */ | |
6544 | ||
6545 | if (dep_type == TYPE_CMOVE) | |
6546 | { | |
6547 | /* Instructions that read the result of conditional moves cannot | |
6548 | be in the same group or the following group. */ | |
6549 | return cost + 1; | |
6550 | } | |
6551 | ||
6552 | switch (insn_type) | |
6553 | { | |
6554 | /* UltraSPARC can dual issue a store and an instruction setting | |
6555 | the value stored, except for divide and square root. */ | |
6556 | case TYPE_FPSTORE: | |
6557 | if (! SLOW_FP (dep_type)) | |
6558 | return 0; | |
6559 | return cost; | |
6560 | ||
6561 | case TYPE_STORE: | |
6562 | if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET) | |
6563 | return cost; | |
6564 | ||
6565 | if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat))) | |
6566 | /* The dependency between the two instructions is on the data | |
6567 | that is being stored. Assume that the address of the store | |
6568 | is not also dependent. */ | |
6569 | return 0; | |
6570 | return cost; | |
6571 | ||
6572 | case TYPE_LOAD: | |
6573 | case TYPE_SLOAD: | |
6574 | case TYPE_FPLOAD: | |
6575 | /* A load does not return data until at least 11 cycles after | |
6576 | a store to the same location. 3 cycles are accounted for | |
6577 | in the load latency; add the other 8 here. */ | |
6578 | if (dep_type == TYPE_STORE || dep_type == TYPE_FPSTORE) | |
6579 | { | |
6580 | /* If the addresses are not equal this may be a false | |
6581 | dependency because pointer aliasing could not be | |
6582 | determined. Add only 2 cycles in that case. 2 is | |
6583 | an arbitrary compromise between 8, which would cause | |
6584 | the scheduler to generate worse code elsewhere to | |
6585 | compensate for a dependency which might not really | |
6586 | exist, and 0. */ | |
6587 | if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET | |
6588 | || GET_CODE (SET_SRC (pat)) != MEM | |
6589 | || GET_CODE (SET_DEST (dep_pat)) != MEM | |
6590 | || ! rtx_equal_p (XEXP (SET_SRC (pat), 0), | |
6591 | XEXP (SET_DEST (dep_pat), 0))) | |
6592 | return cost + 2; | |
6593 | ||
6594 | return cost + 8; | |
6595 | } | |
6596 | return cost; | |
6597 | ||
6598 | case TYPE_BRANCH: | |
6599 | /* Compare to branch latency is 0. There is no benefit from | |
6600 | separating compare and branch. */ | |
6601 | if (dep_type == TYPE_COMPARE) | |
6602 | return 0; | |
6603 | /* Floating point compare to branch latency is less than | |
6604 | compare to conditional move. */ | |
6605 | if (dep_type == TYPE_FPCMP) | |
6606 | return cost - 1; | |
6607 | return cost; | |
6608 | ||
6609 | case TYPE_FPCMOVE: | |
6610 | /* FMOVR class instructions can not issue in the same cycle | |
6611 | or the cycle after an instruction which writes any | |
6612 | integer register. Model this as cost 2 for dependent | |
6613 | instructions. */ | |
6614 | if ((dep_type == TYPE_IALU || dep_type == TYPE_UNARY | |
6615 | || dep_type == TYPE_BINARY) | |
6616 | && cost < 2) | |
6617 | return 2; | |
6618 | /* Otherwise check as for integer conditional moves. */ | |
6619 | ||
6620 | case TYPE_CMOVE: | |
6621 | /* Conditional moves involving integer registers wait until | |
6622 | 3 cycles after loads return data. The interlock applies | |
6623 | to all loads, not just dependent loads, but that is hard | |
6624 | to model. */ | |
6625 | if (dep_type == TYPE_LOAD || dep_type == TYPE_SLOAD) | |
6626 | return cost + 3; | |
6627 | return cost; | |
6628 | ||
6629 | default: | |
6630 | break; | |
6631 | } | |
6632 | break; | |
6633 | ||
6634 | case REG_DEP_ANTI: | |
6635 | /* Divide and square root lock destination registers for full latency. */ | |
6636 | if (! SLOW_FP (dep_type)) | |
6637 | return 0; | |
6638 | break; | |
6639 | ||
6640 | case REG_DEP_OUTPUT: | |
6641 | /* IEU and FPU instruction that have the same destination | |
6642 | register cannot be grouped together. */ | |
6643 | return cost + 1; | |
6644 | ||
6645 | default: | |
6646 | break; | |
6647 | } | |
6648 | ||
6649 | /* Other costs not accounted for: | |
6650 | - Single precision floating point loads lock the other half of | |
6651 | the even/odd register pair. | |
6652 | - Several hazards associated with ldd/std are ignored because these | |
6653 | instructions are rarely generated for V9. | |
6654 | - The floating point pipeline can not have both a single and double | |
6655 | precision operation active at the same time. Format conversions | |
6656 | and graphics instructions are given honorary double precision status. | |
6657 | - call and jmpl are always the first instruction in a group. */ | |
6658 | ||
6659 | return cost; | |
6660 | ||
6661 | #undef SLOW_FP | |
6662 | } | |
6663 | ||
6664 | int | |
6665 | sparc_adjust_cost(insn, link, dep, cost) | |
6666 | rtx insn; | |
6667 | rtx link; | |
6668 | rtx dep; | |
6669 | int cost; | |
6670 | { | |
6671 | switch (sparc_cpu) | |
6672 | { | |
6673 | case PROCESSOR_SUPERSPARC: | |
6674 | cost = supersparc_adjust_cost (insn, link, dep, cost); | |
6675 | break; | |
6676 | case PROCESSOR_HYPERSPARC: | |
6677 | case PROCESSOR_SPARCLITE86X: | |
6678 | cost = hypersparc_adjust_cost (insn, link, dep, cost); | |
6679 | break; | |
6680 | case PROCESSOR_ULTRASPARC: | |
6681 | cost = ultrasparc_adjust_cost (insn, link, dep, cost); | |
6682 | break; | |
6683 | default: | |
6684 | break; | |
6685 | } | |
6686 | return cost; | |
6687 | } | |
6688 | ||
3bc8b61e DM |
6689 | /* This describes the state of the UltraSPARC pipeline during |
6690 | instruction scheduling. */ | |
6691 | ||
b96a5ea5 KG |
6692 | #define TMASK(__x) ((unsigned)1 << ((int)(__x))) |
6693 | #define UMASK(__x) ((unsigned)1 << ((int)(__x))) | |
3bc8b61e DM |
6694 | |
6695 | enum ultra_code { NONE=0, /* no insn at all */ | |
6696 | IEU0, /* shifts and conditional moves */ | |
6697 | IEU1, /* condition code setting insns, calls+jumps */ | |
6698 | IEUN, /* all other single cycle ieu insns */ | |
6699 | LSU, /* loads and stores */ | |
6700 | CTI, /* branches */ | |
6701 | FPM, /* FPU pipeline 1, multiplies and divides */ | |
6702 | FPA, /* FPU pipeline 2, all other operations */ | |
6703 | SINGLE, /* single issue instructions */ | |
6704 | NUM_ULTRA_CODES }; | |
6705 | ||
b1474bb7 KG |
6706 | static enum ultra_code ultra_code_from_mask PROTO ((int)); |
6707 | static void ultra_schedule_insn PROTO ((rtx *, rtx *, int, enum ultra_code)); | |
6708 | ||
3bb5de61 | 6709 | static const char *ultra_code_names[NUM_ULTRA_CODES] = { |
3bc8b61e DM |
6710 | "NONE", "IEU0", "IEU1", "IEUN", "LSU", "CTI", |
6711 | "FPM", "FPA", "SINGLE" }; | |
6712 | ||
6713 | struct ultrasparc_pipeline_state { | |
6714 | /* The insns in this group. */ | |
6715 | rtx group[4]; | |
6716 | ||
6717 | /* The code for each insn. */ | |
6718 | enum ultra_code codes[4]; | |
6719 | ||
6720 | /* Which insns in this group have been committed by the | |
6721 | scheduler. This is how we determine how many more | |
6722 | can issue this cycle. */ | |
6723 | char commit[4]; | |
6724 | ||
6725 | /* How many insns in this group. */ | |
6726 | char group_size; | |
6727 | ||
6728 | /* Mask of free slots still in this group. */ | |
6729 | char free_slot_mask; | |
6730 | ||
6731 | /* The slotter uses the following to determine what other | |
6732 | insn types can still make their way into this group. */ | |
6733 | char contents [NUM_ULTRA_CODES]; | |
6734 | char num_ieu_insns; | |
6735 | }; | |
6736 | ||
6737 | #define ULTRA_NUM_HIST 8 | |
6738 | static struct ultrasparc_pipeline_state ultra_pipe_hist[ULTRA_NUM_HIST]; | |
6739 | static int ultra_cur_hist; | |
6740 | static int ultra_cycles_elapsed; | |
6741 | ||
6742 | #define ultra_pipe (ultra_pipe_hist[ultra_cur_hist]) | |
6743 | ||
6744 | /* Given TYPE_MASK compute the ultra_code it has. */ | |
6745 | static enum ultra_code | |
6746 | ultra_code_from_mask (type_mask) | |
6747 | int type_mask; | |
6748 | { | |
3bc8b61e DM |
6749 | if (type_mask & (TMASK (TYPE_SHIFT) | TMASK (TYPE_CMOVE))) |
6750 | return IEU0; | |
6751 | else if (type_mask & (TMASK (TYPE_COMPARE) | | |
6752 | TMASK (TYPE_CALL) | | |
6753 | TMASK (TYPE_UNCOND_BRANCH))) | |
6754 | return IEU1; | |
6755 | else if (type_mask & (TMASK (TYPE_IALU) | TMASK (TYPE_BINARY) | | |
6756 | TMASK (TYPE_MOVE) | TMASK (TYPE_UNARY))) | |
6757 | return IEUN; | |
6758 | else if (type_mask & (TMASK (TYPE_LOAD) | TMASK (TYPE_SLOAD) | | |
6759 | TMASK (TYPE_STORE) | TMASK (TYPE_FPLOAD) | | |
6760 | TMASK (TYPE_FPSTORE))) | |
6761 | return LSU; | |
6762 | else if (type_mask & (TMASK (TYPE_FPMUL) | TMASK (TYPE_FPDIVS) | | |
c0ec7a75 DM |
6763 | TMASK (TYPE_FPDIVD) | TMASK (TYPE_FPSQRTS) | |
6764 | TMASK (TYPE_FPSQRTD))) | |
3bc8b61e DM |
6765 | return FPM; |
6766 | else if (type_mask & (TMASK (TYPE_FPMOVE) | TMASK (TYPE_FPCMOVE) | | |
6767 | TMASK (TYPE_FP) | TMASK (TYPE_FPCMP))) | |
6768 | return FPA; | |
6769 | else if (type_mask & TMASK (TYPE_BRANCH)) | |
6770 | return CTI; | |
6771 | ||
6772 | return SINGLE; | |
6773 | } | |
6774 | ||
6775 | /* Check INSN (a conditional move) and make sure that it's | |
6776 | results are available at this cycle. Return 1 if the | |
6777 | results are in fact ready. */ | |
6778 | static int | |
6779 | ultra_cmove_results_ready_p (insn) | |
6780 | rtx insn; | |
6781 | { | |
6782 | struct ultrasparc_pipeline_state *up; | |
6783 | int entry, slot; | |
6784 | ||
6785 | /* If this got dispatched in the previous | |
6786 | group, the results are not ready. */ | |
ddf80874 | 6787 | entry = (ultra_cur_hist - 1) % (ULTRA_NUM_HIST - 1); |
3bc8b61e DM |
6788 | up = &ultra_pipe_hist[entry]; |
6789 | slot = 4; | |
6790 | while (--slot >= 0) | |
6791 | if (up->group[slot] == insn) | |
c305b1a7 | 6792 | return 0; |
3bc8b61e | 6793 | |
c305b1a7 | 6794 | return 1; |
3bc8b61e DM |
6795 | } |
6796 | ||
6797 | /* Walk backwards in pipeline history looking for FPU | |
6798 | operations which use a mode different than FPMODE and | |
6799 | will create a stall if an insn using FPMODE were to be | |
6800 | dispatched this cycle. */ | |
6801 | static int | |
6802 | ultra_fpmode_conflict_exists (fpmode) | |
6803 | enum machine_mode fpmode; | |
6804 | { | |
6805 | int hist_ent; | |
6806 | int hist_lim; | |
6807 | ||
ddf80874 | 6808 | hist_ent = (ultra_cur_hist - 1) % (ULTRA_NUM_HIST - 1); |
3bc8b61e DM |
6809 | if (ultra_cycles_elapsed < 4) |
6810 | hist_lim = ultra_cycles_elapsed; | |
6811 | else | |
6812 | hist_lim = 4; | |
6813 | while (hist_lim > 0) | |
6814 | { | |
6815 | struct ultrasparc_pipeline_state *up = &ultra_pipe_hist[hist_ent]; | |
6816 | int slot = 4; | |
6817 | ||
6818 | while (--slot >= 0) | |
6819 | { | |
6820 | rtx insn = up->group[slot]; | |
6821 | enum machine_mode this_mode; | |
3bc8b61e DM |
6822 | rtx pat; |
6823 | ||
6824 | if (! insn | |
6825 | || GET_CODE (insn) != INSN | |
6826 | || (pat = PATTERN (insn)) == 0 | |
6827 | || GET_CODE (pat) != SET) | |
6828 | continue; | |
6829 | ||
6830 | this_mode = GET_MODE (SET_DEST (pat)); | |
6831 | if ((this_mode != SFmode | |
6832 | && this_mode != DFmode) | |
6833 | || this_mode == fpmode) | |
6834 | continue; | |
6835 | ||
6836 | /* If it is not FMOV, FABS, FNEG, FDIV, or FSQRT then | |
ddf80874 DM |
6837 | we will get a stall. Loads and stores are independant |
6838 | of these rules. */ | |
3bc8b61e DM |
6839 | if (GET_CODE (SET_SRC (pat)) != ABS |
6840 | && GET_CODE (SET_SRC (pat)) != NEG | |
6841 | && ((TMASK (get_attr_type (insn)) & | |
6842 | (TMASK (TYPE_FPDIVS) | TMASK (TYPE_FPDIVD) | | |
c0ec7a75 DM |
6843 | TMASK (TYPE_FPMOVE) | TMASK (TYPE_FPSQRTS) | |
6844 | TMASK (TYPE_FPSQRTD) | | |
ddf80874 | 6845 | TMASK (TYPE_LOAD) | TMASK (TYPE_STORE))) == 0)) |
3bc8b61e DM |
6846 | return 1; |
6847 | } | |
6848 | hist_lim--; | |
ddf80874 | 6849 | hist_ent = (hist_ent - 1) % (ULTRA_NUM_HIST - 1); |
3bc8b61e DM |
6850 | } |
6851 | ||
6852 | /* No conflicts, safe to dispatch. */ | |
6853 | return 0; | |
6854 | } | |
6855 | ||
6856 | /* Find an instruction in LIST which has one of the | |
6857 | type attributes enumerated in TYPE_MASK. START | |
6858 | says where to begin the search. | |
6859 | ||
6860 | NOTE: This scheme depends upon the fact that we | |
6861 | have less than 32 distinct type attributes. */ | |
5a5325cb DM |
6862 | |
6863 | static int ultra_types_avail; | |
6864 | ||
3bc8b61e DM |
6865 | static rtx * |
6866 | ultra_find_type (type_mask, list, start) | |
6867 | int type_mask; | |
6868 | rtx *list; | |
6869 | int start; | |
6870 | { | |
6871 | int i; | |
6872 | ||
5a5325cb DM |
6873 | /* Short circuit if no such insn exists in the ready |
6874 | at the moment. */ | |
6875 | if ((type_mask & ultra_types_avail) == 0) | |
6876 | return 0; | |
6877 | ||
3bc8b61e DM |
6878 | for (i = start; i >= 0; i--) |
6879 | { | |
6880 | rtx insn = list[i]; | |
6881 | ||
6882 | if (recog_memoized (insn) >= 0 | |
6883 | && (TMASK(get_attr_type (insn)) & type_mask)) | |
6884 | { | |
ddf80874 | 6885 | enum machine_mode fpmode = SFmode; |
3bc8b61e DM |
6886 | rtx pat = 0; |
6887 | int slot; | |
6888 | int check_depend = 0; | |
6889 | int check_fpmode_conflict = 0; | |
6890 | ||
6891 | if (GET_CODE (insn) == INSN | |
6892 | && (pat = PATTERN(insn)) != 0 | |
6893 | && GET_CODE (pat) == SET | |
6894 | && !(type_mask & (TMASK (TYPE_STORE) | | |
6895 | TMASK (TYPE_FPSTORE)))) | |
6896 | { | |
6897 | check_depend = 1; | |
6898 | if (GET_MODE (SET_DEST (pat)) == SFmode | |
6899 | || GET_MODE (SET_DEST (pat)) == DFmode) | |
6900 | { | |
6901 | fpmode = GET_MODE (SET_DEST (pat)); | |
6902 | check_fpmode_conflict = 1; | |
6903 | } | |
6904 | } | |
6905 | ||
6906 | slot = 4; | |
6907 | while(--slot >= 0) | |
6908 | { | |
6909 | rtx slot_insn = ultra_pipe.group[slot]; | |
6910 | rtx slot_pat; | |
6911 | ||
6912 | /* Already issued, bad dependency, or FPU | |
6913 | mode conflict. */ | |
6914 | if (slot_insn != 0 | |
6915 | && (slot_pat = PATTERN (slot_insn)) != 0 | |
6916 | && ((insn == slot_insn) | |
6917 | || (check_depend == 1 | |
6918 | && GET_CODE (slot_insn) == INSN | |
6919 | && GET_CODE (slot_pat) == SET | |
5a5325cb DM |
6920 | && ((GET_CODE (SET_DEST (slot_pat)) == REG |
6921 | && GET_CODE (SET_SRC (pat)) == REG | |
6922 | && REGNO (SET_DEST (slot_pat)) == | |
6923 | REGNO (SET_SRC (pat))) | |
6924 | || (GET_CODE (SET_DEST (slot_pat)) == SUBREG | |
6925 | && GET_CODE (SET_SRC (pat)) == SUBREG | |
6926 | && REGNO (SUBREG_REG (SET_DEST (slot_pat))) == | |
6927 | REGNO (SUBREG_REG (SET_SRC (pat))) | |
6928 | && SUBREG_WORD (SET_DEST (slot_pat)) == | |
ddf80874 | 6929 | SUBREG_WORD (SET_SRC (pat))))) |
3bc8b61e DM |
6930 | || (check_fpmode_conflict == 1 |
6931 | && GET_CODE (slot_insn) == INSN | |
6932 | && GET_CODE (slot_pat) == SET | |
ddf80874 DM |
6933 | && (GET_MODE (SET_DEST (slot_pat)) == SFmode |
6934 | || GET_MODE (SET_DEST (slot_pat)) == DFmode) | |
6935 | && GET_MODE (SET_DEST (slot_pat)) != fpmode))) | |
3bc8b61e DM |
6936 | goto next; |
6937 | } | |
6938 | ||
6939 | /* Check for peculiar result availability and dispatch | |
6940 | interference situations. */ | |
6941 | if (pat != 0 | |
6942 | && ultra_cycles_elapsed > 0) | |
6943 | { | |
6944 | rtx link; | |
6945 | ||
6946 | for (link = LOG_LINKS (insn); link; link = XEXP (link, 1)) | |
6947 | { | |
6948 | rtx link_insn = XEXP (link, 0); | |
6949 | if (GET_CODE (link_insn) == INSN | |
6950 | && recog_memoized (link_insn) >= 0 | |
6951 | && (TMASK (get_attr_type (link_insn)) & | |
6952 | (TMASK (TYPE_CMOVE) | TMASK (TYPE_FPCMOVE))) | |
6953 | && ! ultra_cmove_results_ready_p (link_insn)) | |
6954 | goto next; | |
6955 | } | |
6956 | ||
6957 | if (check_fpmode_conflict | |
6958 | && ultra_fpmode_conflict_exists (fpmode)) | |
6959 | goto next; | |
6960 | } | |
6961 | ||
6962 | return &list[i]; | |
6963 | } | |
6964 | next: | |
5a5325cb | 6965 | ; |
3bc8b61e DM |
6966 | } |
6967 | return 0; | |
6968 | } | |
6969 | ||
5a5325cb DM |
6970 | static void |
6971 | ultra_build_types_avail (ready, n_ready) | |
6972 | rtx *ready; | |
6973 | int n_ready; | |
6974 | { | |
6975 | int i = n_ready - 1; | |
6976 | ||
6977 | ultra_types_avail = 0; | |
6978 | while(i >= 0) | |
6979 | { | |
6980 | rtx insn = ready[i]; | |
6981 | ||
6982 | if (recog_memoized (insn) >= 0) | |
6983 | ultra_types_avail |= TMASK (get_attr_type (insn)); | |
6984 | ||
6985 | i -= 1; | |
6986 | } | |
6987 | } | |
6988 | ||
3bc8b61e DM |
6989 | /* Place insn pointed to my IP into the pipeline. |
6990 | Make element THIS of READY be that insn if it | |
6991 | is not already. TYPE indicates the pipeline class | |
6992 | this insn falls into. */ | |
6993 | static void | |
6994 | ultra_schedule_insn (ip, ready, this, type) | |
6995 | rtx *ip; | |
6996 | rtx *ready; | |
6997 | int this; | |
6998 | enum ultra_code type; | |
6999 | { | |
7000 | int pipe_slot; | |
7001 | char mask = ultra_pipe.free_slot_mask; | |
c0ec7a75 | 7002 | rtx temp; |
3bc8b61e DM |
7003 | |
7004 | /* Obtain free slot. */ | |
7005 | for (pipe_slot = 0; pipe_slot < 4; pipe_slot++) | |
7006 | if ((mask & (1 << pipe_slot)) != 0) | |
7007 | break; | |
7008 | if (pipe_slot == 4) | |
7009 | abort (); | |
7010 | ||
7011 | /* In it goes, and it hasn't been committed yet. */ | |
7012 | ultra_pipe.group[pipe_slot] = *ip; | |
7013 | ultra_pipe.codes[pipe_slot] = type; | |
7014 | ultra_pipe.contents[type] = 1; | |
7015 | if (UMASK (type) & | |
7016 | (UMASK (IEUN) | UMASK (IEU0) | UMASK (IEU1))) | |
7017 | ultra_pipe.num_ieu_insns += 1; | |
7018 | ||
7019 | ultra_pipe.free_slot_mask = (mask & ~(1 << pipe_slot)); | |
7020 | ultra_pipe.group_size += 1; | |
7021 | ultra_pipe.commit[pipe_slot] = 0; | |
7022 | ||
7023 | /* Update ready list. */ | |
c0ec7a75 DM |
7024 | temp = *ip; |
7025 | while (ip != &ready[this]) | |
3bc8b61e | 7026 | { |
c0ec7a75 DM |
7027 | ip[0] = ip[1]; |
7028 | ++ip; | |
3bc8b61e | 7029 | } |
c0ec7a75 | 7030 | *ip = temp; |
3bc8b61e DM |
7031 | } |
7032 | ||
7033 | /* Advance to the next pipeline group. */ | |
7034 | static void | |
7035 | ultra_flush_pipeline () | |
7036 | { | |
ddf80874 | 7037 | ultra_cur_hist = (ultra_cur_hist + 1) % (ULTRA_NUM_HIST - 1); |
3bc8b61e DM |
7038 | ultra_cycles_elapsed += 1; |
7039 | bzero ((char *) &ultra_pipe, sizeof ultra_pipe); | |
7040 | ultra_pipe.free_slot_mask = 0xf; | |
7041 | } | |
7042 | ||
3bc8b61e DM |
7043 | /* Init our data structures for this current block. */ |
7044 | void | |
7045 | ultrasparc_sched_init (dump, sched_verbose) | |
ddf80874 DM |
7046 | FILE *dump ATTRIBUTE_UNUSED; |
7047 | int sched_verbose ATTRIBUTE_UNUSED; | |
3bc8b61e | 7048 | { |
b96a5ea5 | 7049 | bzero ((char *) ultra_pipe_hist, sizeof ultra_pipe_hist); |
3bc8b61e DM |
7050 | ultra_cur_hist = 0; |
7051 | ultra_cycles_elapsed = 0; | |
ddf80874 | 7052 | ultra_pipe.free_slot_mask = 0xf; |
3bc8b61e DM |
7053 | } |
7054 | ||
7055 | /* INSN has been scheduled, update pipeline commit state | |
7056 | and return how many instructions are still to be | |
7057 | scheduled in this group. */ | |
bfd6bc60 | 7058 | int |
3bc8b61e DM |
7059 | ultrasparc_variable_issue (insn) |
7060 | rtx insn; | |
7061 | { | |
7062 | struct ultrasparc_pipeline_state *up = &ultra_pipe; | |
7063 | int i, left_to_fire; | |
7064 | ||
7065 | left_to_fire = 0; | |
7066 | for (i = 0; i < 4; i++) | |
7067 | { | |
7068 | if (up->group[i] == 0) | |
7069 | continue; | |
7070 | ||
7071 | if (up->group[i] == insn) | |
7072 | { | |
7073 | up->commit[i] = 1; | |
7074 | } | |
7075 | else if (! up->commit[i]) | |
7076 | left_to_fire++; | |
7077 | } | |
7078 | ||
7079 | return left_to_fire; | |
7080 | } | |
7081 | ||
7082 | /* In actual_hazard_this_instance, we may have yanked some | |
7083 | instructions from the ready list due to conflict cost | |
7084 | adjustments. If so, and such an insn was in our pipeline | |
7085 | group, remove it and update state. */ | |
7086 | static void | |
7087 | ultra_rescan_pipeline_state (ready, n_ready) | |
7088 | rtx *ready; | |
7089 | int n_ready; | |
7090 | { | |
7091 | struct ultrasparc_pipeline_state *up = &ultra_pipe; | |
7092 | int i; | |
7093 | ||
7094 | for (i = 0; i < 4; i++) | |
7095 | { | |
7096 | rtx insn = up->group[i]; | |
3bc8b61e DM |
7097 | int j; |
7098 | ||
7099 | if (! insn) | |
7100 | continue; | |
7101 | ||
7102 | /* If it has been committed, then it was removed from | |
7103 | the ready list because it was actually scheduled, | |
7104 | and that is not the case we are searching for here. */ | |
7105 | if (up->commit[i] != 0) | |
7106 | continue; | |
7107 | ||
7108 | for (j = n_ready - 1; j >= 0; j--) | |
7109 | if (ready[j] == insn) | |
7110 | break; | |
7111 | ||
7112 | /* If we didn't find it, toss it. */ | |
7113 | if (j < 0) | |
7114 | { | |
7115 | enum ultra_code ucode = up->codes[i]; | |
7116 | ||
7117 | up->group[i] = 0; | |
7118 | up->codes[i] = NONE; | |
7119 | up->contents[ucode] = 0; | |
7120 | if (UMASK (ucode) & | |
7121 | (UMASK (IEUN) | UMASK (IEU0) | UMASK (IEU1))) | |
7122 | up->num_ieu_insns -= 1; | |
7123 | ||
7124 | up->free_slot_mask |= (1 << i); | |
7125 | up->group_size -= 1; | |
7126 | up->commit[i] = 0; | |
7127 | } | |
7128 | } | |
7129 | } | |
7130 | ||
7131 | void | |
7132 | ultrasparc_sched_reorder (dump, sched_verbose, ready, n_ready) | |
7133 | FILE *dump; | |
7134 | int sched_verbose; | |
7135 | rtx *ready; | |
7136 | int n_ready; | |
7137 | { | |
7138 | struct ultrasparc_pipeline_state *up = &ultra_pipe; | |
7139 | int i, this_insn; | |
7140 | ||
3bc8b61e DM |
7141 | if (sched_verbose) |
7142 | { | |
7143 | int n; | |
7144 | ||
7145 | fprintf (dump, "\n;;\tUltraSPARC Looking at ["); | |
7146 | for (n = n_ready - 1; n >= 0; n--) | |
7147 | { | |
7148 | rtx insn = ready[n]; | |
7149 | enum ultra_code ucode; | |
7150 | ||
7151 | if (recog_memoized (insn) < 0) | |
7152 | continue; | |
7153 | ucode = ultra_code_from_mask (TMASK (get_attr_type (insn))); | |
7154 | if (n != 0) | |
7155 | fprintf (dump, "%s(%d) ", | |
7156 | ultra_code_names[ucode], | |
7157 | INSN_UID (insn)); | |
7158 | else | |
7159 | fprintf (dump, "%s(%d)", | |
7160 | ultra_code_names[ucode], | |
7161 | INSN_UID (insn)); | |
7162 | } | |
7163 | fprintf (dump, "]\n"); | |
7164 | } | |
7165 | ||
7166 | this_insn = n_ready - 1; | |
7167 | ||
7168 | /* Skip over junk we don't understand. */ | |
7169 | while ((this_insn >= 0) | |
7170 | && recog_memoized (ready[this_insn]) < 0) | |
7171 | this_insn--; | |
7172 | ||
5a5325cb DM |
7173 | ultra_build_types_avail (ready, this_insn + 1); |
7174 | ||
3bc8b61e DM |
7175 | while (this_insn >= 0) { |
7176 | int old_group_size = up->group_size; | |
7177 | ||
7178 | if (up->group_size != 0) | |
7179 | { | |
7180 | int num_committed; | |
7181 | ||
7182 | num_committed = (up->commit[0] + up->commit[1] + | |
7183 | up->commit[2] + up->commit[3]); | |
7184 | /* If nothing has been commited from our group, or all of | |
7185 | them have. Clear out the (current cycle's) pipeline | |
7186 | state and start afresh. */ | |
7187 | if (num_committed == 0 | |
7188 | || num_committed == up->group_size) | |
7189 | { | |
ddf80874 DM |
7190 | ultra_flush_pipeline (); |
7191 | up = &ultra_pipe; | |
3bc8b61e DM |
7192 | old_group_size = 0; |
7193 | } | |
7194 | else | |
7195 | { | |
7196 | /* OK, some ready list insns got requeued and thus removed | |
7197 | from the ready list. Account for this fact. */ | |
7198 | ultra_rescan_pipeline_state (ready, n_ready); | |
7199 | ||
7200 | /* Something "changed", make this look like a newly | |
7201 | formed group so the code at the end of the loop | |
7202 | knows that progress was in fact made. */ | |
7203 | if (up->group_size != old_group_size) | |
ddf80874 | 7204 | old_group_size = 0; |
3bc8b61e DM |
7205 | } |
7206 | } | |
7207 | ||
7208 | if (up->group_size == 0) | |
7209 | { | |
7210 | /* If the pipeline is (still) empty and we have any single | |
7211 | group insns, get them out now as this is a good time. */ | |
7212 | rtx *ip = ultra_find_type ((TMASK (TYPE_RETURN) | TMASK (TYPE_ADDRESS) | | |
7213 | TMASK (TYPE_IMUL) | TMASK (TYPE_CMOVE) | | |
7214 | TMASK (TYPE_MULTI) | TMASK (TYPE_MISC)), | |
7215 | ready, this_insn); | |
7216 | if (ip) | |
7217 | { | |
7218 | ultra_schedule_insn (ip, ready, this_insn, SINGLE); | |
7219 | break; | |
7220 | } | |
7221 | ||
7222 | /* If we are not in the process of emptying out the pipe, try to | |
7223 | obtain an instruction which must be the first in it's group. */ | |
7224 | ip = ultra_find_type ((TMASK (TYPE_CALL) | | |
7225 | TMASK (TYPE_CALL_NO_DELAY_SLOT) | | |
7226 | TMASK (TYPE_UNCOND_BRANCH)), | |
7227 | ready, this_insn); | |
7228 | if (ip) | |
7229 | { | |
7230 | ultra_schedule_insn (ip, ready, this_insn, IEU1); | |
7231 | this_insn--; | |
7232 | } | |
7233 | else if ((ip = ultra_find_type ((TMASK (TYPE_FPDIVS) | | |
7234 | TMASK (TYPE_FPDIVD) | | |
c0ec7a75 DM |
7235 | TMASK (TYPE_FPSQRTS) | |
7236 | TMASK (TYPE_FPSQRTD)), | |
3bc8b61e DM |
7237 | ready, this_insn)) != 0) |
7238 | { | |
7239 | ultra_schedule_insn (ip, ready, this_insn, FPM); | |
7240 | this_insn--; | |
7241 | } | |
7242 | } | |
7243 | ||
7244 | /* Try to fill the integer pipeline. First, look for an IEU0 specific | |
7245 | operation. We can't do more IEU operations if the first 3 slots are | |
7246 | all full or we have dispatched two IEU insns already. */ | |
7247 | if ((up->free_slot_mask & 0x7) != 0 | |
7248 | && up->num_ieu_insns < 2 | |
7249 | && up->contents[IEU0] == 0 | |
7250 | && up->contents[IEUN] == 0) | |
7251 | { | |
7252 | rtx *ip = ultra_find_type (TMASK(TYPE_SHIFT), ready, this_insn); | |
7253 | if (ip) | |
7254 | { | |
7255 | ultra_schedule_insn (ip, ready, this_insn, IEU0); | |
7256 | this_insn--; | |
7257 | } | |
7258 | } | |
7259 | ||
7260 | /* If we can, try to find an IEU1 specific or an unnamed | |
7261 | IEU instruction. */ | |
7262 | if ((up->free_slot_mask & 0x7) != 0 | |
7263 | && up->num_ieu_insns < 2) | |
7264 | { | |
7265 | rtx *ip = ultra_find_type ((TMASK (TYPE_IALU) | TMASK (TYPE_BINARY) | | |
7266 | TMASK (TYPE_MOVE) | TMASK (TYPE_UNARY) | | |
7267 | (up->contents[IEU1] == 0 ? TMASK (TYPE_COMPARE) : 0)), | |
7268 | ready, this_insn); | |
7269 | if (ip) | |
7270 | { | |
7271 | rtx insn = *ip; | |
7272 | ||
7273 | ultra_schedule_insn (ip, ready, this_insn, | |
7274 | (!up->contents[IEU1] | |
7275 | && get_attr_type (insn) == TYPE_COMPARE) | |
7276 | ? IEU1 : IEUN); | |
7277 | this_insn--; | |
7278 | } | |
7279 | } | |
7280 | ||
7281 | /* If only one IEU insn has been found, try to find another unnamed | |
7282 | IEU operation or an IEU1 specific one. */ | |
7283 | if ((up->free_slot_mask & 0x7) != 0 | |
7284 | && up->num_ieu_insns < 2) | |
7285 | { | |
7286 | rtx *ip; | |
7287 | int tmask = (TMASK (TYPE_IALU) | TMASK (TYPE_BINARY) | | |
7288 | TMASK (TYPE_MOVE) | TMASK (TYPE_UNARY)); | |
7289 | ||
7290 | if (!up->contents[IEU1]) | |
7291 | tmask |= TMASK (TYPE_COMPARE); | |
7292 | ip = ultra_find_type (tmask, ready, this_insn); | |
7293 | if (ip) | |
7294 | { | |
7295 | rtx insn = *ip; | |
7296 | ||
7297 | ultra_schedule_insn (ip, ready, this_insn, | |
7298 | (!up->contents[IEU1] | |
7299 | && get_attr_type (insn) == TYPE_COMPARE) | |
7300 | ? IEU1 : IEUN); | |
7301 | this_insn--; | |
7302 | } | |
7303 | } | |
7304 | ||
7305 | /* Try for a load or store, but such an insn can only be issued | |
7306 | if it is within' one of the first 3 slots. */ | |
7307 | if ((up->free_slot_mask & 0x7) != 0 | |
7308 | && up->contents[LSU] == 0) | |
7309 | { | |
7310 | rtx *ip = ultra_find_type ((TMASK (TYPE_LOAD) | TMASK (TYPE_SLOAD) | | |
7311 | TMASK (TYPE_STORE) | TMASK (TYPE_FPLOAD) | | |
7312 | TMASK (TYPE_FPSTORE)), ready, this_insn); | |
7313 | if (ip) | |
7314 | { | |
7315 | ultra_schedule_insn (ip, ready, this_insn, LSU); | |
7316 | this_insn--; | |
7317 | } | |
7318 | } | |
7319 | ||
7320 | /* Now find FPU operations, first FPM class. But not divisions or | |
7321 | square-roots because those will break the group up. Unlike all | |
7322 | the previous types, these can go in any slot. */ | |
7323 | if (up->free_slot_mask != 0 | |
7324 | && up->contents[FPM] == 0) | |
7325 | { | |
7326 | rtx *ip = ultra_find_type (TMASK (TYPE_FPMUL), ready, this_insn); | |
7327 | if (ip) | |
7328 | { | |
7329 | ultra_schedule_insn (ip, ready, this_insn, FPM); | |
7330 | this_insn--; | |
7331 | } | |
7332 | } | |
7333 | ||
7334 | /* Continue on with FPA class if we have not filled the group already. */ | |
7335 | if (up->free_slot_mask != 0 | |
7336 | && up->contents[FPA] == 0) | |
7337 | { | |
7338 | rtx *ip = ultra_find_type ((TMASK (TYPE_FPMOVE) | TMASK (TYPE_FPCMOVE) | | |
7339 | TMASK (TYPE_FP) | TMASK (TYPE_FPCMP)), | |
7340 | ready, this_insn); | |
7341 | if (ip) | |
7342 | { | |
7343 | ultra_schedule_insn (ip, ready, this_insn, FPA); | |
7344 | this_insn--; | |
7345 | } | |
7346 | } | |
7347 | ||
7348 | /* Finally, maybe stick a branch in here. */ | |
7349 | if (up->free_slot_mask != 0 | |
7350 | && up->contents[CTI] == 0) | |
7351 | { | |
7352 | rtx *ip = ultra_find_type (TMASK (TYPE_BRANCH), ready, this_insn); | |
7353 | ||
7354 | /* Try to slip in a branch only if it is one of the | |
7355 | next 2 in the ready list. */ | |
7356 | if (ip && ((&ready[this_insn] - ip) < 2)) | |
7357 | { | |
7358 | ultra_schedule_insn (ip, ready, this_insn, CTI); | |
7359 | this_insn--; | |
7360 | } | |
7361 | } | |
7362 | ||
7363 | up->group_size = 0; | |
7364 | for (i = 0; i < 4; i++) | |
7365 | if ((up->free_slot_mask & (1 << i)) == 0) | |
7366 | up->group_size++; | |
7367 | ||
7368 | /* See if we made any progress... */ | |
7369 | if (old_group_size != up->group_size) | |
7370 | break; | |
7371 | ||
7372 | /* Clean out the (current cycle's) pipeline state | |
ddf80874 DM |
7373 | and try once more. If we placed no instructions |
7374 | into the pipeline at all, it means a real hard | |
7375 | conflict exists with some earlier issued instruction | |
7376 | so we must advance to the next cycle to clear it up. */ | |
7377 | if (up->group_size == 0) | |
7378 | { | |
7379 | ultra_flush_pipeline (); | |
7380 | up = &ultra_pipe; | |
7381 | } | |
7382 | else | |
7383 | { | |
7384 | bzero ((char *) &ultra_pipe, sizeof ultra_pipe); | |
7385 | ultra_pipe.free_slot_mask = 0xf; | |
7386 | } | |
3bc8b61e DM |
7387 | } |
7388 | ||
7389 | if (sched_verbose) | |
7390 | { | |
7391 | int n, gsize; | |
7392 | ||
7393 | fprintf (dump, ";;\tUltraSPARC Launched ["); | |
7394 | gsize = up->group_size; | |
7395 | for (n = 0; n < 4; n++) | |
7396 | { | |
7397 | rtx insn = up->group[n]; | |
7398 | ||
7399 | if (! insn) | |
7400 | continue; | |
7401 | ||
7402 | gsize -= 1; | |
7403 | if (gsize != 0) | |
7404 | fprintf (dump, "%s(%d) ", | |
7405 | ultra_code_names[up->codes[n]], | |
7406 | INSN_UID (insn)); | |
7407 | else | |
7408 | fprintf (dump, "%s(%d)", | |
7409 | ultra_code_names[up->codes[n]], | |
7410 | INSN_UID (insn)); | |
7411 | } | |
7412 | fprintf (dump, "]\n"); | |
7413 | } | |
7414 | } | |
7415 | ||
bfd6bc60 JC |
7416 | int |
7417 | sparc_issue_rate () | |
7418 | { | |
7419 | switch (sparc_cpu) | |
7420 | { | |
7421 | default: | |
7422 | return 1; | |
bfd6bc60 | 7423 | case PROCESSOR_V9: |
284d86e9 | 7424 | /* Assume V9 processors are capable of at least dual-issue. */ |
bfd6bc60 JC |
7425 | return 2; |
7426 | case PROCESSOR_SUPERSPARC: | |
7427 | return 3; | |
393049a9 RH |
7428 | case PROCESSOR_HYPERSPARC: |
7429 | case PROCESSOR_SPARCLITE86X: | |
7430 | return 2; | |
bfd6bc60 JC |
7431 | case PROCESSOR_ULTRASPARC: |
7432 | return 4; | |
7433 | } | |
7434 | } | |
284d86e9 JC |
7435 | |
7436 | static int | |
7437 | set_extends(x, insn) | |
7438 | rtx x, insn; | |
7439 | { | |
7440 | register rtx pat = PATTERN (insn); | |
7441 | ||
7442 | switch (GET_CODE (SET_SRC (pat))) | |
7443 | { | |
7444 | /* Load and some shift instructions zero extend. */ | |
7445 | case MEM: | |
7446 | case ZERO_EXTEND: | |
7447 | /* sethi clears the high bits */ | |
7448 | case HIGH: | |
7449 | /* LO_SUM is used with sethi. sethi cleared the high | |
7450 | bits and the values used with lo_sum are positive */ | |
7451 | case LO_SUM: | |
284d86e9 JC |
7452 | /* Store flag stores 0 or 1 */ |
7453 | case LT: case LTU: | |
7454 | case GT: case GTU: | |
7455 | case LE: case LEU: | |
7456 | case GE: case GEU: | |
7457 | case EQ: | |
7458 | case NE: | |
7459 | return 1; | |
7460 | case AND: | |
7461 | { | |
7462 | rtx op1 = XEXP (SET_SRC (pat), 1); | |
7463 | if (GET_CODE (op1) == CONST_INT) | |
7464 | return INTVAL (op1) >= 0; | |
7465 | if (GET_CODE (XEXP (SET_SRC (pat), 0)) == REG | |
7466 | && sparc_check_64 (XEXP (SET_SRC (pat), 0), insn) == 1) | |
7467 | return 1; | |
7468 | if (GET_CODE (op1) == REG | |
7469 | && sparc_check_64 ((op1), insn) == 1) | |
7470 | return 1; | |
7471 | } | |
7472 | case ASHIFT: | |
7473 | case LSHIFTRT: | |
7474 | return GET_MODE (SET_SRC (pat)) == SImode; | |
7475 | /* Positive integers leave the high bits zero. */ | |
7476 | case CONST_DOUBLE: | |
7477 | return ! (CONST_DOUBLE_LOW (x) & 0x80000000); | |
7478 | case CONST_INT: | |
7479 | return ! (INTVAL (x) & 0x80000000); | |
7480 | case ASHIFTRT: | |
7481 | case SIGN_EXTEND: | |
7482 | return - (GET_MODE (SET_SRC (pat)) == SImode); | |
7483 | default: | |
7484 | return 0; | |
7485 | } | |
7486 | } | |
7487 | ||
e0d80184 DM |
7488 | /* We _ought_ to have only one kind per function, but... */ |
7489 | static rtx sparc_addr_diff_list; | |
7490 | static rtx sparc_addr_list; | |
7491 | ||
7492 | void | |
7493 | sparc_defer_case_vector (lab, vec, diff) | |
7494 | rtx lab, vec; | |
7495 | int diff; | |
7496 | { | |
7497 | vec = gen_rtx_EXPR_LIST (VOIDmode, lab, vec); | |
7498 | if (diff) | |
7499 | sparc_addr_diff_list | |
7500 | = gen_rtx_EXPR_LIST (VOIDmode, vec, sparc_addr_diff_list); | |
7501 | else | |
7502 | sparc_addr_list = gen_rtx_EXPR_LIST (VOIDmode, vec, sparc_addr_list); | |
7503 | } | |
7504 | ||
7505 | static void | |
7506 | sparc_output_addr_vec (vec) | |
7507 | rtx vec; | |
7508 | { | |
7509 | rtx lab = XEXP (vec, 0), body = XEXP (vec, 1); | |
7510 | int idx, vlen = XVECLEN (body, 0); | |
7511 | ||
d1accaa3 JJ |
7512 | #ifdef ASM_OUTPUT_ADDR_VEC_START |
7513 | ASM_OUTPUT_ADDR_VEC_START (asm_out_file); | |
7514 | #endif | |
7515 | ||
e0d80184 DM |
7516 | #ifdef ASM_OUTPUT_CASE_LABEL |
7517 | ASM_OUTPUT_CASE_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab), | |
7518 | NEXT_INSN (lab)); | |
7519 | #else | |
7520 | ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab)); | |
7521 | #endif | |
7522 | ||
7523 | for (idx = 0; idx < vlen; idx++) | |
7524 | { | |
7525 | ASM_OUTPUT_ADDR_VEC_ELT | |
7526 | (asm_out_file, CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 0, idx), 0))); | |
7527 | } | |
d1accaa3 JJ |
7528 | |
7529 | #ifdef ASM_OUTPUT_ADDR_VEC_END | |
7530 | ASM_OUTPUT_ADDR_VEC_END (asm_out_file); | |
7531 | #endif | |
e0d80184 DM |
7532 | } |
7533 | ||
7534 | static void | |
7535 | sparc_output_addr_diff_vec (vec) | |
7536 | rtx vec; | |
7537 | { | |
7538 | rtx lab = XEXP (vec, 0), body = XEXP (vec, 1); | |
7539 | rtx base = XEXP (XEXP (body, 0), 0); | |
7540 | int idx, vlen = XVECLEN (body, 1); | |
7541 | ||
d1accaa3 JJ |
7542 | #ifdef ASM_OUTPUT_ADDR_VEC_START |
7543 | ASM_OUTPUT_ADDR_VEC_START (asm_out_file); | |
7544 | #endif | |
7545 | ||
e0d80184 DM |
7546 | #ifdef ASM_OUTPUT_CASE_LABEL |
7547 | ASM_OUTPUT_CASE_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab), | |
7548 | NEXT_INSN (lab)); | |
7549 | #else | |
7550 | ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab)); | |
7551 | #endif | |
7552 | ||
7553 | for (idx = 0; idx < vlen; idx++) | |
7554 | { | |
7555 | ASM_OUTPUT_ADDR_DIFF_ELT | |
7556 | (asm_out_file, | |
7557 | body, | |
7558 | CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 1, idx), 0)), | |
7559 | CODE_LABEL_NUMBER (base)); | |
7560 | } | |
d1accaa3 JJ |
7561 | |
7562 | #ifdef ASM_OUTPUT_ADDR_VEC_END | |
7563 | ASM_OUTPUT_ADDR_VEC_END (asm_out_file); | |
7564 | #endif | |
e0d80184 DM |
7565 | } |
7566 | ||
7567 | static void | |
7568 | sparc_output_deferred_case_vectors () | |
7569 | { | |
7570 | rtx t; | |
d676da68 | 7571 | int align; |
e0d80184 | 7572 | |
f3b8847b DM |
7573 | if (sparc_addr_list == NULL_RTX |
7574 | && sparc_addr_diff_list == NULL_RTX) | |
7575 | return; | |
7576 | ||
e0d80184 DM |
7577 | /* Align to cache line in the function's code section. */ |
7578 | function_section (current_function_decl); | |
d676da68 DM |
7579 | |
7580 | align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT); | |
7581 | if (align > 0) | |
f3b8847b | 7582 | ASM_OUTPUT_ALIGN (asm_out_file, align); |
e0d80184 DM |
7583 | |
7584 | for (t = sparc_addr_list; t ; t = XEXP (t, 1)) | |
7585 | sparc_output_addr_vec (XEXP (t, 0)); | |
7586 | for (t = sparc_addr_diff_list; t ; t = XEXP (t, 1)) | |
7587 | sparc_output_addr_diff_vec (XEXP (t, 0)); | |
7588 | ||
7589 | sparc_addr_list = sparc_addr_diff_list = NULL_RTX; | |
7590 | } | |
7591 | ||
284d86e9 JC |
7592 | /* Return 0 if the high 32 bits of X (the low word of X, if DImode) are |
7593 | unknown. Return 1 if the high bits are zero, -1 if the register is | |
7594 | sign extended. */ | |
7595 | int | |
7596 | sparc_check_64 (x, insn) | |
7597 | rtx x, insn; | |
7598 | { | |
7599 | /* If a register is set only once it is safe to ignore insns this | |
7600 | code does not know how to handle. The loop will either recognize | |
7601 | the single set and return the correct value or fail to recognize | |
7602 | it and return 0. */ | |
7603 | int set_once = 0; | |
7604 | ||
7605 | if (GET_CODE (x) == REG | |
7606 | && flag_expensive_optimizations | |
7607 | && REG_N_SETS (REGNO (x)) == 1) | |
7608 | set_once = 1; | |
7609 | ||
7610 | if (insn == 0) | |
d6f4ec51 KG |
7611 | { |
7612 | if (set_once) | |
7613 | insn = get_last_insn_anywhere (); | |
7614 | else | |
7615 | return 0; | |
7616 | } | |
284d86e9 | 7617 | |
d6f4ec51 | 7618 | while ((insn = PREV_INSN (insn))) |
284d86e9 JC |
7619 | { |
7620 | switch (GET_CODE (insn)) | |
7621 | { | |
7622 | case JUMP_INSN: | |
7623 | case NOTE: | |
7624 | break; | |
7625 | case CODE_LABEL: | |
7626 | case CALL_INSN: | |
7627 | default: | |
7628 | if (! set_once) | |
7629 | return 0; | |
7630 | break; | |
7631 | case INSN: | |
7632 | { | |
7633 | rtx pat = PATTERN (insn); | |
7634 | if (GET_CODE (pat) != SET) | |
7635 | return 0; | |
7636 | if (rtx_equal_p (x, SET_DEST (pat))) | |
7637 | return set_extends (x, insn); | |
7638 | if (reg_overlap_mentioned_p (SET_DEST (pat), x)) | |
7639 | return 0; | |
7640 | } | |
7641 | } | |
7642 | } | |
7643 | return 0; | |
7644 | } | |
7645 | ||
7646 | char * | |
7647 | sparc_v8plus_shift (operands, insn, opcode) | |
7648 | rtx *operands; | |
7649 | rtx insn; | |
b1474bb7 | 7650 | const char *opcode; |
284d86e9 JC |
7651 | { |
7652 | static char asm_code[60]; | |
7653 | ||
7654 | if (GET_CODE (operands[3]) == SCRATCH) | |
7655 | operands[3] = operands[0]; | |
c6b0465b JC |
7656 | if (GET_CODE (operands[1]) == CONST_INT) |
7657 | { | |
7658 | output_asm_insn ("mov %1,%3", operands); | |
7659 | } | |
7660 | else | |
7661 | { | |
7662 | output_asm_insn ("sllx %H1,32,%3", operands); | |
7663 | if (sparc_check_64 (operands[1], insn) <= 0) | |
7664 | output_asm_insn ("srl %L1,0,%L1", operands); | |
7665 | output_asm_insn ("or %L1,%3,%3", operands); | |
7666 | } | |
284d86e9 JC |
7667 | |
7668 | strcpy(asm_code, opcode); | |
7669 | if (which_alternative != 2) | |
7670 | return strcat (asm_code, " %0,%2,%L0\n\tsrlx %L0,32,%H0"); | |
7671 | else | |
7672 | return strcat (asm_code, " %3,%2,%3\n\tsrlx %3,32,%H0\n\tmov %3,%L0"); | |
7673 | } | |
7674 | ||
7675 | ||
7676 | /* Return 1 if DEST and SRC reference only global and in registers. */ | |
7677 | ||
7678 | int | |
7679 | sparc_return_peephole_ok (dest, src) | |
7680 | rtx dest, src; | |
7681 | { | |
7682 | if (! TARGET_V9) | |
7683 | return 0; | |
54ff41b7 | 7684 | if (current_function_uses_only_leaf_regs) |
284d86e9 JC |
7685 | return 0; |
7686 | if (GET_CODE (src) != CONST_INT | |
7687 | && (GET_CODE (src) != REG || ! IN_OR_GLOBAL_P (src))) | |
7688 | return 0; | |
7689 | return IN_OR_GLOBAL_P (dest); | |
7690 | } | |
2be15d0f RH |
7691 | \f |
7692 | /* Output assembler code to FILE to increment profiler label # LABELNO | |
7693 | for profiling a function entry. | |
7694 | ||
7695 | 32 bit sparc uses %g2 as the STATIC_CHAIN_REGNUM which gets clobbered | |
7696 | during profiling so we need to save/restore it around the call to mcount. | |
7697 | We're guaranteed that a save has just been done, and we use the space | |
7698 | allocated for intreg/fpreg value passing. */ | |
7699 | ||
7700 | void | |
7701 | sparc_function_profiler (file, labelno) | |
7702 | FILE *file; | |
7703 | int labelno; | |
7704 | { | |
7705 | char buf[32]; | |
7706 | ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno); | |
7707 | ||
7708 | if (! TARGET_ARCH64) | |
7709 | fputs ("\tst\t%g2,[%fp-4]\n", file); | |
7710 | ||
7711 | fputs ("\tsethi\t%hi(", file); | |
7712 | assemble_name (file, buf); | |
7713 | fputs ("),%o0\n", file); | |
7714 | ||
7715 | fputs ("\tcall\t", file); | |
7716 | assemble_name (file, MCOUNT_FUNCTION); | |
7717 | putc ('\n', file); | |
7718 | ||
7719 | fputs ("\t or\t%o0,%lo(", file); | |
7720 | assemble_name (file, buf); | |
7721 | fputs ("),%o0\n", file); | |
7722 | ||
7723 | if (! TARGET_ARCH64) | |
7724 | fputs ("\tld\t[%fp-4],%g2\n", file); | |
7725 | } | |
7726 | ||
7727 | ||
7728 | /* The following macro shall output assembler code to FILE | |
7729 | to initialize basic-block profiling. | |
7730 | ||
7731 | If profile_block_flag == 2 | |
7732 | ||
7733 | Output code to call the subroutine `__bb_init_trace_func' | |
7734 | and pass two parameters to it. The first parameter is | |
7735 | the address of a block allocated in the object module. | |
7736 | The second parameter is the number of the first basic block | |
7737 | of the function. | |
7738 | ||
7739 | The name of the block is a local symbol made with this statement: | |
7740 | ||
7741 | ASM_GENERATE_INTERNAL_LABEL (BUFFER, "LPBX", 0); | |
7742 | ||
7743 | Of course, since you are writing the definition of | |
7744 | `ASM_GENERATE_INTERNAL_LABEL' as well as that of this macro, you | |
7745 | can take a short cut in the definition of this macro and use the | |
7746 | name that you know will result. | |
7747 | ||
7748 | The number of the first basic block of the function is | |
7749 | passed to the macro in BLOCK_OR_LABEL. | |
7750 | ||
7751 | If described in a virtual assembler language the code to be | |
7752 | output looks like: | |
7753 | ||
7754 | parameter1 <- LPBX0 | |
7755 | parameter2 <- BLOCK_OR_LABEL | |
7756 | call __bb_init_trace_func | |
7757 | ||
7758 | else if profile_block_flag != 0 | |
7759 | ||
7760 | Output code to call the subroutine `__bb_init_func' | |
7761 | and pass one single parameter to it, which is the same | |
7762 | as the first parameter to `__bb_init_trace_func'. | |
7763 | ||
7764 | The first word of this parameter is a flag which will be nonzero if | |
7765 | the object module has already been initialized. So test this word | |
7766 | first, and do not call `__bb_init_func' if the flag is nonzero. | |
7767 | Note: When profile_block_flag == 2 the test need not be done | |
7768 | but `__bb_init_trace_func' *must* be called. | |
7769 | ||
7770 | BLOCK_OR_LABEL may be used to generate a label number as a | |
7771 | branch destination in case `__bb_init_func' will not be called. | |
7772 | ||
7773 | If described in a virtual assembler language the code to be | |
7774 | output looks like: | |
7775 | ||
7776 | cmp (LPBX0),0 | |
7777 | jne local_label | |
7778 | parameter1 <- LPBX0 | |
7779 | call __bb_init_func | |
7780 | local_label: | |
7781 | ||
7782 | */ | |
7783 | ||
7784 | void | |
7785 | sparc_function_block_profiler(file, block_or_label) | |
7786 | FILE *file; | |
7787 | int block_or_label; | |
7788 | { | |
7789 | char LPBX[32]; | |
7790 | ASM_GENERATE_INTERNAL_LABEL (LPBX, "LPBX", 0); | |
7791 | ||
7792 | if (profile_block_flag == 2) | |
7793 | { | |
7794 | fputs ("\tsethi\t%hi(", file); | |
7795 | assemble_name (file, LPBX); | |
7796 | fputs ("),%o0\n", file); | |
7797 | ||
7798 | fprintf (file, "\tsethi\t%%hi(%d),%%o1\n", block_or_label); | |
7799 | ||
7800 | fputs ("\tor\t%o0,%lo(", file); | |
7801 | assemble_name (file, LPBX); | |
7802 | fputs ("),%o0\n", file); | |
7803 | ||
7804 | fprintf (file, "\tcall\t%s__bb_init_trace_func\n", user_label_prefix); | |
7805 | ||
7806 | fprintf (file, "\t or\t%%o1,%%lo(%d),%%o1\n", block_or_label); | |
7807 | } | |
7808 | else if (profile_block_flag != 0) | |
7809 | { | |
7810 | char LPBY[32]; | |
7811 | ASM_GENERATE_INTERNAL_LABEL (LPBY, "LPBY", block_or_label); | |
7812 | ||
7813 | fputs ("\tsethi\t%hi(", file); | |
7814 | assemble_name (file, LPBX); | |
7815 | fputs ("),%o0\n", file); | |
7816 | ||
7817 | fputs ("\tld\t[%lo(", file); | |
7818 | assemble_name (file, LPBX); | |
7819 | fputs (")+%o0],%o1\n", file); | |
7820 | ||
7821 | fputs ("\ttst\t%o1\n", file); | |
7822 | ||
7823 | if (TARGET_V9) | |
7824 | { | |
7825 | fputs ("\tbne,pn\t%icc,", file); | |
7826 | assemble_name (file, LPBY); | |
7827 | putc ('\n', file); | |
7828 | } | |
7829 | else | |
7830 | { | |
7831 | fputs ("\tbne\t", file); | |
7832 | assemble_name (file, LPBY); | |
7833 | putc ('\n', file); | |
7834 | } | |
7835 | ||
7836 | fputs ("\t or\t%o0,%lo(", file); | |
7837 | assemble_name (file, LPBX); | |
7838 | fputs ("),%o0\n", file); | |
7839 | ||
7840 | fprintf (file, "\tcall\t%s__bb_init_func\n\t nop\n", user_label_prefix); | |
7841 | ||
7842 | ASM_OUTPUT_INTERNAL_LABEL (file, "LPBY", block_or_label); | |
7843 | } | |
7844 | } | |
7845 | ||
7846 | /* The following macro shall output assembler code to FILE | |
7847 | to increment a counter associated with basic block number BLOCKNO. | |
7848 | ||
7849 | If profile_block_flag == 2 | |
7850 | ||
7851 | Output code to initialize the global structure `__bb' and | |
7852 | call the function `__bb_trace_func' which will increment the | |
7853 | counter. | |
7854 | ||
7855 | `__bb' consists of two words. In the first word the number | |
7856 | of the basic block has to be stored. In the second word | |
7857 | the address of a block allocated in the object module | |
7858 | has to be stored. | |
7859 | ||
7860 | The basic block number is given by BLOCKNO. | |
7861 | ||
7862 | The address of the block is given by the label created with | |
7863 | ||
7864 | ASM_GENERATE_INTERNAL_LABEL (BUFFER, "LPBX", 0); | |
7865 | ||
7866 | by FUNCTION_BLOCK_PROFILER. | |
7867 | ||
7868 | Of course, since you are writing the definition of | |
7869 | `ASM_GENERATE_INTERNAL_LABEL' as well as that of this macro, you | |
7870 | can take a short cut in the definition of this macro and use the | |
7871 | name that you know will result. | |
7872 | ||
7873 | If described in a virtual assembler language the code to be | |
7874 | output looks like: | |
7875 | ||
7876 | move BLOCKNO -> (__bb) | |
7877 | move LPBX0 -> (__bb+4) | |
7878 | call __bb_trace_func | |
7879 | ||
7880 | Note that function `__bb_trace_func' must not change the | |
7881 | machine state, especially the flag register. To grant | |
7882 | this, you must output code to save and restore registers | |
7883 | either in this macro or in the macros MACHINE_STATE_SAVE | |
7884 | and MACHINE_STATE_RESTORE. The last two macros will be | |
7885 | used in the function `__bb_trace_func', so you must make | |
7886 | sure that the function prologue does not change any | |
7887 | register prior to saving it with MACHINE_STATE_SAVE. | |
7888 | ||
7889 | else if profile_block_flag != 0 | |
7890 | ||
7891 | Output code to increment the counter directly. | |
7892 | Basic blocks are numbered separately from zero within each | |
7893 | compiled object module. The count associated with block number | |
7894 | BLOCKNO is at index BLOCKNO in an array of words; the name of | |
7895 | this array is a local symbol made with this statement: | |
7896 | ||
7897 | ASM_GENERATE_INTERNAL_LABEL (BUFFER, "LPBX", 2); | |
7898 | ||
7899 | Of course, since you are writing the definition of | |
7900 | `ASM_GENERATE_INTERNAL_LABEL' as well as that of this macro, you | |
7901 | can take a short cut in the definition of this macro and use the | |
7902 | name that you know will result. | |
7903 | ||
7904 | If described in a virtual assembler language, the code to be | |
7905 | output looks like: | |
7906 | ||
7907 | inc (LPBX2+4*BLOCKNO) | |
7908 | ||
7909 | */ | |
7910 | ||
7911 | void | |
7912 | sparc_block_profiler(file, blockno) | |
7913 | FILE *file; | |
7914 | int blockno; | |
7915 | { | |
7916 | char LPBX[32]; | |
7917 | ||
7918 | if (profile_block_flag == 2) | |
7919 | { | |
7920 | ASM_GENERATE_INTERNAL_LABEL (LPBX, "LPBX", 0); | |
7921 | ||
7922 | fprintf (file, "\tsethi\t%%hi(%s__bb),%%g1\n", user_label_prefix); | |
7923 | fprintf (file, "\tsethi\t%%hi(%d),%%g2\n", blockno); | |
7924 | fprintf (file, "\tor\t%%g1,%%lo(%s__bb),%%g1\n", user_label_prefix); | |
7925 | fprintf (file, "\tor\t%%g2,%%lo(%d),%%g2\n", blockno); | |
7926 | ||
7927 | fputs ("\tst\t%g2,[%g1]\n", file); | |
7928 | ||
7929 | fputs ("\tsethi\t%hi(", file); | |
7930 | assemble_name (file, LPBX); | |
7931 | fputs ("),%g2\n", file); | |
7932 | ||
110b0302 | 7933 | fputs ("\tor\t%o2,%lo(", file); |
2be15d0f RH |
7934 | assemble_name (file, LPBX); |
7935 | fputs ("),%g2\n", file); | |
7936 | ||
7937 | fputs ("\tst\t%g2,[%g1+4]\n", file); | |
7938 | fputs ("\tmov\t%o7,%g2\n", file); | |
7939 | ||
7940 | fprintf (file, "\tcall\t%s__bb_trace_func\n\t nop\n", user_label_prefix); | |
7941 | ||
7942 | fputs ("\tmov\t%g2,%o7\n", file); | |
7943 | } | |
7944 | else if (profile_block_flag != 0) | |
7945 | { | |
7946 | ASM_GENERATE_INTERNAL_LABEL (LPBX, "LPBX", 2); | |
7947 | ||
7948 | fputs ("\tsethi\t%hi(", file); | |
7949 | assemble_name (file, LPBX); | |
7950 | fprintf (file, "+%d),%%g1\n", blockno*4); | |
7951 | ||
7952 | fputs ("\tld\t[%g1+%lo(", file); | |
7953 | assemble_name (file, LPBX); | |
7954 | fprintf (file, "+%d)],%%g2\n", blockno*4); | |
7955 | ||
7956 | fputs ("\tadd\t%g2,1,%g2\n", file); | |
7957 | ||
7958 | fputs ("\tst\t%g2,[%g1+%lo(", file); | |
7959 | assemble_name (file, LPBX); | |
7960 | fprintf (file, "+%d)]\n", blockno*4); | |
7961 | } | |
7962 | } | |
7963 | ||
7964 | /* The following macro shall output assembler code to FILE | |
7965 | to indicate a return from function during basic-block profiling. | |
7966 | ||
7967 | If profile_block_flag == 2: | |
7968 | ||
7969 | Output assembler code to call function `__bb_trace_ret'. | |
7970 | ||
7971 | Note that function `__bb_trace_ret' must not change the | |
7972 | machine state, especially the flag register. To grant | |
7973 | this, you must output code to save and restore registers | |
7974 | either in this macro or in the macros MACHINE_STATE_SAVE_RET | |
7975 | and MACHINE_STATE_RESTORE_RET. The last two macros will be | |
7976 | used in the function `__bb_trace_ret', so you must make | |
7977 | sure that the function prologue does not change any | |
7978 | register prior to saving it with MACHINE_STATE_SAVE_RET. | |
7979 | ||
7980 | else if profile_block_flag != 0: | |
7981 | ||
7982 | The macro will not be used, so it need not distinguish | |
7983 | these cases. | |
7984 | */ | |
7985 | ||
7986 | void | |
7987 | sparc_function_block_profiler_exit(file) | |
7988 | FILE *file; | |
7989 | { | |
7990 | if (profile_block_flag == 2) | |
7991 | fprintf (file, "\tcall\t%s__bb_trace_ret\n\t nop\n", user_label_prefix); | |
7992 | else | |
7993 | abort (); | |
7994 | } | |
d07d525a MM |
7995 | |
7996 | /* Mark ARG, which is really a struct ultrasparc_pipline_state *, for | |
7997 | GC. */ | |
7998 | ||
7999 | static void | |
8000 | mark_ultrasparc_pipeline_state (arg) | |
8001 | void *arg; | |
8002 | { | |
8003 | struct ultrasparc_pipeline_state *ups; | |
8004 | size_t i; | |
8005 | ||
8006 | ups = (struct ultrasparc_pipeline_state *) arg; | |
8007 | for (i = 0; i < sizeof (ups->group) / sizeof (rtx); ++i) | |
8008 | ggc_mark_rtx (ups->group[i]); | |
8009 | } | |
8010 | ||
8011 | /* Called to register all of our global variables with the garbage | |
8012 | collector. */ | |
8013 | ||
8014 | static void | |
8015 | sparc_add_gc_roots () | |
8016 | { | |
8017 | ggc_add_rtx_root (&sparc_compare_op0, 1); | |
8018 | ggc_add_rtx_root (&sparc_compare_op1, 1); | |
8019 | ggc_add_rtx_root (&leaf_label, 1); | |
8020 | ggc_add_rtx_root (&global_offset_table, 1); | |
8021 | ggc_add_rtx_root (&get_pc_symbol, 1); | |
8022 | ggc_add_rtx_root (&sparc_addr_diff_list, 1); | |
8023 | ggc_add_rtx_root (&sparc_addr_list, 1); | |
8024 | ggc_add_root (ultra_pipe_hist, | |
8025 | sizeof (ultra_pipe_hist) / sizeof (ultra_pipe_hist[0]), | |
8026 | sizeof (ultra_pipe_hist[0]), | |
8027 | &mark_ultrasparc_pipeline_state); | |
8028 | } |