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ab835497 | 1 | /* Subroutines for insn-output.c for Sun SPARC. |
27d8f9ea | 2 | Copyright (C) 1987, 88, 89, 92-97, 1998 Free Software Foundation, Inc. |
ab835497 | 3 | Contributed by Michael Tiemann (tiemann@cygnus.com) |
61a55e8b DE |
4 | 64 bit SPARC V9 support by Michael Tiemann, Jim Wilson, and Doug Evans, |
5 | at Cygnus Support. | |
ab835497 RK |
6 | |
7 | This file is part of GNU CC. | |
8 | ||
9 | GNU CC is free software; you can redistribute it and/or modify | |
10 | it under the terms of the GNU General Public License as published by | |
11 | the Free Software Foundation; either version 2, or (at your option) | |
12 | any later version. | |
13 | ||
14 | GNU CC is distributed in the hope that it will be useful, | |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
18 | ||
19 | You should have received a copy of the GNU General Public License | |
20 | along with GNU CC; see the file COPYING. If not, write to | |
c15c9075 RK |
21 | the Free Software Foundation, 59 Temple Place - Suite 330, |
22 | Boston, MA 02111-1307, USA. */ | |
ab835497 | 23 | |
ab835497 | 24 | #include "config.h" |
284d86e9 | 25 | #include "system.h" |
210aa14a | 26 | #include "tree.h" |
ab835497 RK |
27 | #include "rtl.h" |
28 | #include "regs.h" | |
29 | #include "hard-reg-set.h" | |
30 | #include "real.h" | |
31 | #include "insn-config.h" | |
32 | #include "conditions.h" | |
33 | #include "insn-flags.h" | |
34 | #include "output.h" | |
35 | #include "insn-attr.h" | |
36 | #include "flags.h" | |
37 | #include "expr.h" | |
38 | #include "recog.h" | |
487a6e06 | 39 | #include "toplev.h" |
ab835497 | 40 | |
61a55e8b DE |
41 | /* 1 if the caller has placed an "unimp" insn immediately after the call. |
42 | This is used in v8 code when calling a function that returns a structure. | |
06b967f9 RK |
43 | v9 doesn't have this. Be careful to have this test be the same as that |
44 | used on the call. */ | |
45 | ||
46 | #define SKIP_CALLERS_UNIMP_P \ | |
47 | (!TARGET_ARCH64 && current_function_returns_struct \ | |
48 | && ! integer_zerop (DECL_SIZE (DECL_RESULT (current_function_decl))) \ | |
49 | && (TREE_CODE (DECL_SIZE (DECL_RESULT (current_function_decl))) \ | |
50 | == INTEGER_CST)) | |
61a55e8b | 51 | |
ab835497 RK |
52 | /* Global variables for machine-dependent things. */ |
53 | ||
61a55e8b DE |
54 | /* Size of frame. Need to know this to emit return insns from leaf procedures. |
55 | ACTUAL_FSIZE is set by compute_frame_size() which is called during the | |
56 | reload pass. This is important as the value is later used in insn | |
57 | scheduling (to see what can go in a delay slot). | |
58 | APPARENT_FSIZE is the size of the stack less the register save area and less | |
59 | the outgoing argument area. It is used when saving call preserved regs. */ | |
60 | static int apparent_fsize; | |
61 | static int actual_fsize; | |
62 | ||
ab835497 RK |
63 | /* Save the operands last given to a compare for use when we |
64 | generate a scc or bcc insn. */ | |
65 | ||
66 | rtx sparc_compare_op0, sparc_compare_op1; | |
67 | ||
68 | /* We may need an epilogue if we spill too many registers. | |
69 | If this is non-zero, then we branch here for the epilogue. */ | |
70 | static rtx leaf_label; | |
71 | ||
72 | #ifdef LEAF_REGISTERS | |
73 | ||
74 | /* Vector to say how input registers are mapped to output | |
75 | registers. FRAME_POINTER_REGNUM cannot be remapped by | |
76 | this function to eliminate it. You must use -fomit-frame-pointer | |
77 | to get that. */ | |
78 | char leaf_reg_remap[] = | |
79 | { 0, 1, 2, 3, 4, 5, 6, 7, | |
80 | -1, -1, -1, -1, -1, -1, 14, -1, | |
81 | -1, -1, -1, -1, -1, -1, -1, -1, | |
82 | 8, 9, 10, 11, 12, 13, -1, 15, | |
83 | ||
84 | 32, 33, 34, 35, 36, 37, 38, 39, | |
85 | 40, 41, 42, 43, 44, 45, 46, 47, | |
86 | 48, 49, 50, 51, 52, 53, 54, 55, | |
61a55e8b DE |
87 | 56, 57, 58, 59, 60, 61, 62, 63, |
88 | 64, 65, 66, 67, 68, 69, 70, 71, | |
89 | 72, 73, 74, 75, 76, 77, 78, 79, | |
90 | 80, 81, 82, 83, 84, 85, 86, 87, | |
91 | 88, 89, 90, 91, 92, 93, 94, 95, | |
c4ce6853 | 92 | 96, 97, 98, 99, 100}; |
ab835497 | 93 | |
6a4bb1fa | 94 | #endif |
ab835497 | 95 | |
ab835497 RK |
96 | /* Name of where we pretend to think the frame pointer points. |
97 | Normally, this is "%fp", but if we are in a leaf procedure, | |
61a55e8b DE |
98 | this is "%sp+something". We record "something" separately as it may be |
99 | too big for reg+constant addressing. */ | |
100 | ||
101 | static char *frame_base_name; | |
102 | static int frame_base_offset; | |
ab835497 | 103 | |
c85f7c16 | 104 | static rtx pic_setup_code PROTO((void)); |
c85f7c16 JL |
105 | static void sparc_init_modes PROTO((void)); |
106 | static int save_regs PROTO((FILE *, int, int, char *, | |
107 | int, int, int)); | |
108 | static int restore_regs PROTO((FILE *, int, int, char *, int, int)); | |
109 | static void build_big_number PROTO((FILE *, int, char *)); | |
5e9defae | 110 | static int function_arg_slotno PROTO((const CUMULATIVE_ARGS *, |
c85f7c16 JL |
111 | enum machine_mode, tree, int, int, |
112 | int *, int *)); | |
e0d80184 DM |
113 | static void sparc_output_addr_vec PROTO((rtx)); |
114 | static void sparc_output_addr_diff_vec PROTO((rtx)); | |
115 | static void sparc_output_deferred_case_vectors PROTO((void)); | |
e9a25f70 | 116 | |
2a01c939 | 117 | |
e9a25f70 JL |
118 | #ifdef DWARF2_DEBUGGING_INFO |
119 | extern char *dwarf2out_cfi_label (); | |
120 | #endif | |
61a55e8b DE |
121 | \f |
122 | /* Option handling. */ | |
123 | ||
a0a301fc DE |
124 | /* Code model option as passed by user. */ |
125 | char *sparc_cmodel_string; | |
126 | /* Parsed value. */ | |
127 | enum cmodel sparc_cmodel; | |
128 | ||
129 | /* Record alignment options as passed by user. */ | |
bf62bbf1 DE |
130 | char *sparc_align_loops_string; |
131 | char *sparc_align_jumps_string; | |
132 | char *sparc_align_funcs_string; | |
133 | ||
134 | /* Parsed values, as a power of two. */ | |
135 | int sparc_align_loops; | |
136 | int sparc_align_jumps; | |
137 | int sparc_align_funcs; | |
138 | ||
16956f6e DE |
139 | struct sparc_cpu_select sparc_select[] = |
140 | { | |
141 | /* switch name, tune arch */ | |
142 | { (char *)0, "default", 1, 1 }, | |
143 | { (char *)0, "-mcpu=", 1, 1 }, | |
144 | { (char *)0, "-mtune=", 1, 0 }, | |
db3d4438 | 145 | { 0, 0, 0, 0 } |
16956f6e | 146 | }; |
733f53f5 | 147 | |
16956f6e DE |
148 | /* CPU type. This is set from TARGET_CPU_DEFAULT and -m{cpu,tune}=xxx. */ |
149 | enum processor_type sparc_cpu; | |
733f53f5 | 150 | |
61a55e8b DE |
151 | /* Validate and override various options, and do some machine dependent |
152 | initialization. */ | |
153 | ||
154 | void | |
155 | sparc_override_options () | |
156 | { | |
a0a301fc DE |
157 | static struct code_model { |
158 | char *name; | |
159 | int value; | |
160 | } cmodels[] = { | |
161 | { "32", CM_32 }, | |
162 | { "medlow", CM_MEDLOW }, | |
163 | { "medmid", CM_MEDMID }, | |
164 | { "medany", CM_MEDANY }, | |
165 | { "embmedany", CM_EMBMEDANY }, | |
166 | { 0, 0 } | |
167 | }; | |
168 | struct code_model *cmodel; | |
16956f6e | 169 | /* Map TARGET_CPU_DEFAULT to value for -m{arch,tune}=. */ |
733f53f5 DE |
170 | static struct cpu_default { |
171 | int cpu; | |
172 | char *name; | |
173 | } cpu_default[] = { | |
a0a301fc | 174 | /* There must be one entry here for each TARGET_CPU value. */ |
16956f6e | 175 | { TARGET_CPU_sparc, "cypress" }, |
3592ea0d | 176 | { TARGET_CPU_sparclet, "tsc701" }, |
16956f6e | 177 | { TARGET_CPU_sparclite, "f930" }, |
a0a301fc DE |
178 | { TARGET_CPU_v8, "v8" }, |
179 | { TARGET_CPU_supersparc, "supersparc" }, | |
180 | { TARGET_CPU_v9, "v9" }, | |
ba542005 | 181 | { TARGET_CPU_ultrasparc, "ultrasparc" }, |
db3d4438 | 182 | { 0, 0 } |
733f53f5 | 183 | }; |
16956f6e DE |
184 | struct cpu_default *def; |
185 | /* Table of values for -m{cpu,tune}=. */ | |
733f53f5 DE |
186 | static struct cpu_table { |
187 | char *name; | |
16956f6e | 188 | enum processor_type processor; |
733f53f5 DE |
189 | int disable; |
190 | int enable; | |
191 | } cpu_table[] = { | |
16956f6e DE |
192 | { "v7", PROCESSOR_V7, MASK_ISA, 0 }, |
193 | { "cypress", PROCESSOR_CYPRESS, MASK_ISA, 0 }, | |
194 | { "v8", PROCESSOR_V8, MASK_ISA, MASK_V8 }, | |
733f53f5 | 195 | /* TI TMS390Z55 supersparc */ |
16956f6e DE |
196 | { "supersparc", PROCESSOR_SUPERSPARC, MASK_ISA, MASK_V8 }, |
197 | { "sparclite", PROCESSOR_SPARCLITE, MASK_ISA, MASK_SPARCLITE }, | |
733f53f5 DE |
198 | /* The Fujitsu MB86930 is the original sparclite chip, with no fpu. |
199 | The Fujitsu MB86934 is the recent sparclite chip, with an fpu. */ | |
16956f6e DE |
200 | { "f930", PROCESSOR_F930, MASK_ISA|MASK_FPU, MASK_SPARCLITE }, |
201 | { "f934", PROCESSOR_F934, MASK_ISA, MASK_SPARCLITE|MASK_FPU }, | |
202 | { "sparclet", PROCESSOR_SPARCLET, MASK_ISA, MASK_SPARCLET }, | |
733f53f5 | 203 | /* TEMIC sparclet */ |
3592ea0d | 204 | { "tsc701", PROCESSOR_TSC701, MASK_ISA, MASK_SPARCLET }, |
16956f6e | 205 | { "v9", PROCESSOR_V9, MASK_ISA, MASK_V9 }, |
733f53f5 | 206 | /* TI ultrasparc */ |
284d86e9 | 207 | { "ultrasparc", PROCESSOR_ULTRASPARC, MASK_ISA, MASK_V9 }, |
db3d4438 | 208 | { 0, 0, 0, 0 } |
733f53f5 | 209 | }; |
16956f6e DE |
210 | struct cpu_table *cpu; |
211 | struct sparc_cpu_select *sel; | |
a0a301fc | 212 | int fpu; |
345a6161 | 213 | |
a0a301fc DE |
214 | #ifndef SPARC_BI_ARCH |
215 | /* Check for unsupported architecture size. */ | |
216 | if (! TARGET_64BIT != DEFAULT_ARCH32_P) | |
217 | { | |
218 | error ("%s is not supported by this configuration", | |
219 | DEFAULT_ARCH32_P ? "-m64" : "-m32"); | |
220 | } | |
221 | #endif | |
222 | ||
345a6161 DM |
223 | /* At the moment we don't allow different pointer size and architecture */ |
224 | if (! TARGET_64BIT != ! TARGET_PTR64) | |
225 | { | |
226 | error ("-mptr%d not allowed on -m%d", | |
227 | TARGET_PTR64 ? 64 : 32, TARGET_64BIT ? 64 : 32); | |
228 | if (TARGET_64BIT) | |
229 | target_flags |= MASK_PTR64; | |
230 | else | |
231 | target_flags &= ~MASK_PTR64; | |
232 | } | |
233 | ||
a0a301fc DE |
234 | /* Code model selection. */ |
235 | sparc_cmodel = SPARC_DEFAULT_CMODEL; | |
345a6161 DM |
236 | |
237 | #ifdef SPARC_BI_ARCH | |
238 | if (TARGET_ARCH32) | |
239 | sparc_cmodel = CM_32; | |
240 | #endif | |
241 | ||
a0a301fc DE |
242 | if (sparc_cmodel_string != NULL) |
243 | { | |
244 | if (TARGET_ARCH64) | |
245 | { | |
246 | for (cmodel = &cmodels[0]; cmodel->name; cmodel++) | |
247 | if (strcmp (sparc_cmodel_string, cmodel->name) == 0) | |
248 | break; | |
249 | if (cmodel->name == NULL) | |
250 | error ("bad value (%s) for -mcmodel= switch", sparc_cmodel_string); | |
251 | else | |
252 | sparc_cmodel = cmodel->value; | |
253 | } | |
254 | else | |
255 | error ("-mcmodel= is not supported on 32 bit systems"); | |
256 | } | |
16956f6e | 257 | |
a0a301fc | 258 | fpu = TARGET_FPU; /* save current -mfpu status */ |
1f1406b4 | 259 | |
a0a301fc | 260 | /* Set the default CPU. */ |
16956f6e DE |
261 | for (def = &cpu_default[0]; def->name; ++def) |
262 | if (def->cpu == TARGET_CPU_DEFAULT) | |
263 | break; | |
264 | if (! def->name) | |
265 | abort (); | |
266 | sparc_select[0].string = def->name; | |
267 | ||
268 | for (sel = &sparc_select[0]; sel->name; ++sel) | |
61a55e8b | 269 | { |
16956f6e | 270 | if (sel->string) |
733f53f5 | 271 | { |
16956f6e DE |
272 | for (cpu = &cpu_table[0]; cpu->name; ++cpu) |
273 | if (! strcmp (sel->string, cpu->name)) | |
274 | { | |
275 | if (sel->set_tune_p) | |
276 | sparc_cpu = cpu->processor; | |
277 | ||
278 | if (sel->set_arch_p) | |
279 | { | |
280 | target_flags &= ~cpu->disable; | |
281 | target_flags |= cpu->enable; | |
282 | } | |
283 | break; | |
284 | } | |
285 | ||
286 | if (! cpu->name) | |
287 | error ("bad value (%s) for %s switch", sel->string, sel->name); | |
733f53f5 | 288 | } |
61a55e8b | 289 | } |
97da85b7 | 290 | |
1f1406b4 DE |
291 | /* If -mfpu or -mno-fpu was explicitly used, don't override with |
292 | the processor default. */ | |
293 | if (TARGET_FPU_SET) | |
294 | target_flags = (target_flags & ~MASK_FPU) | fpu; | |
295 | ||
16956f6e DE |
296 | /* Use the deprecated v8 insns for sparc64 in 32 bit mode. */ |
297 | if (TARGET_V9 && TARGET_ARCH32) | |
733f53f5 | 298 | target_flags |= MASK_DEPRECATED_V8_INSNS; |
61a55e8b | 299 | |
345a6161 DM |
300 | /* V8PLUS requires V9, makes no sense in 64 bit mode. */ |
301 | if (! TARGET_V9 || TARGET_ARCH64) | |
284d86e9 JC |
302 | target_flags &= ~MASK_V8PLUS; |
303 | ||
82d6b402 RH |
304 | /* Don't use stack biasing in 32 bit mode. */ |
305 | if (TARGET_ARCH32) | |
306 | target_flags &= ~MASK_STACK_BIAS; | |
f952a238 JJ |
307 | |
308 | /* Don't allow -mvis if FPU is disabled. */ | |
309 | if (! TARGET_FPU) | |
310 | target_flags &= ~MASK_VIS; | |
82d6b402 | 311 | |
bf62bbf1 DE |
312 | /* Validate -malign-loops= value, or provide default. */ |
313 | if (sparc_align_loops_string) | |
314 | { | |
315 | sparc_align_loops = exact_log2 (atoi (sparc_align_loops_string)); | |
316 | if (sparc_align_loops < 2 || sparc_align_loops > 7) | |
317 | fatal ("-malign-loops=%s is not between 4 and 128 or is not a power of two", | |
318 | sparc_align_loops_string); | |
319 | } | |
320 | else | |
321 | { | |
322 | /* ??? This relies on ASM_OUTPUT_ALIGN to not emit the alignment if | |
323 | its 0. This sounds a bit kludgey. */ | |
324 | sparc_align_loops = 0; | |
325 | } | |
326 | ||
327 | /* Validate -malign-jumps= value, or provide default. */ | |
328 | if (sparc_align_jumps_string) | |
329 | { | |
330 | sparc_align_jumps = exact_log2 (atoi (sparc_align_jumps_string)); | |
331 | if (sparc_align_jumps < 2 || sparc_align_loops > 7) | |
332 | fatal ("-malign-jumps=%s is not between 4 and 128 or is not a power of two", | |
333 | sparc_align_jumps_string); | |
334 | } | |
335 | else | |
336 | { | |
337 | /* ??? This relies on ASM_OUTPUT_ALIGN to not emit the alignment if | |
338 | its 0. This sounds a bit kludgey. */ | |
339 | sparc_align_jumps = 0; | |
340 | } | |
341 | ||
342 | /* Validate -malign-functions= value, or provide default. */ | |
343 | if (sparc_align_funcs_string) | |
344 | { | |
345 | sparc_align_funcs = exact_log2 (atoi (sparc_align_funcs_string)); | |
346 | if (sparc_align_funcs < 2 || sparc_align_loops > 7) | |
347 | fatal ("-malign-functions=%s is not between 4 and 128 or is not a power of two", | |
348 | sparc_align_funcs_string); | |
349 | } | |
350 | else | |
351 | sparc_align_funcs = DEFAULT_SPARC_ALIGN_FUNCS; | |
352 | ||
82d6b402 RH |
353 | /* Validate PCC_STRUCT_RETURN. */ |
354 | if (flag_pcc_struct_return == DEFAULT_PCC_STRUCT_RETURN) | |
355 | flag_pcc_struct_return = (TARGET_ARCH64 ? 0 : 1); | |
356 | ||
61a55e8b DE |
357 | /* Do various machine dependent initializations. */ |
358 | sparc_init_modes (); | |
359 | } | |
360 | \f | |
cd5fb1ee DE |
361 | /* Miscellaneous utilities. */ |
362 | ||
363 | /* Nonzero if CODE, a comparison, is suitable for use in v9 conditional move | |
364 | or branch on register contents instructions. */ | |
365 | ||
366 | int | |
367 | v9_regcmp_p (code) | |
368 | enum rtx_code code; | |
369 | { | |
370 | return (code == EQ || code == NE || code == GE || code == LT | |
371 | || code == LE || code == GT); | |
372 | } | |
bfd6bc60 | 373 | |
cd5fb1ee DE |
374 | \f |
375 | /* Operand constraints. */ | |
376 | ||
ab835497 | 377 | /* Return non-zero only if OP is a register of mode MODE, |
c4ce6853 DE |
378 | or const0_rtx. Don't allow const0_rtx if TARGET_LIVE_G0 because |
379 | %g0 may contain anything. */ | |
380 | ||
ab835497 RK |
381 | int |
382 | reg_or_0_operand (op, mode) | |
383 | rtx op; | |
384 | enum machine_mode mode; | |
385 | { | |
c4ce6853 DE |
386 | if (register_operand (op, mode)) |
387 | return 1; | |
388 | if (TARGET_LIVE_G0) | |
389 | return 0; | |
390 | if (op == const0_rtx) | |
ab835497 | 391 | return 1; |
5b486ce0 | 392 | if (GET_MODE (op) == VOIDmode && GET_CODE (op) == CONST_DOUBLE |
ab835497 RK |
393 | && CONST_DOUBLE_HIGH (op) == 0 |
394 | && CONST_DOUBLE_LOW (op) == 0) | |
395 | return 1; | |
302484ff JW |
396 | if (GET_MODE_CLASS (GET_MODE (op)) == MODE_FLOAT |
397 | && GET_CODE (op) == CONST_DOUBLE | |
398 | && fp_zero_operand (op)) | |
399 | return 1; | |
ab835497 RK |
400 | return 0; |
401 | } | |
402 | ||
302484ff | 403 | /* Nonzero if OP is a floating point value with value 0.0. */ |
c4ce6853 | 404 | |
302484ff JW |
405 | int |
406 | fp_zero_operand (op) | |
407 | rtx op; | |
408 | { | |
409 | REAL_VALUE_TYPE r; | |
410 | ||
411 | REAL_VALUE_FROM_CONST_DOUBLE (r, op); | |
d61ba4f4 | 412 | return (REAL_VALUES_EQUAL (r, dconst0) && ! REAL_VALUE_MINUS_ZERO (r)); |
302484ff JW |
413 | } |
414 | ||
61a55e8b DE |
415 | /* Nonzero if OP is an integer register. */ |
416 | ||
417 | int | |
418 | intreg_operand (op, mode) | |
419 | rtx op; | |
487a6e06 | 420 | enum machine_mode mode ATTRIBUTE_UNUSED; |
61a55e8b DE |
421 | { |
422 | return (register_operand (op, SImode) | |
a9e27770 | 423 | || (TARGET_ARCH64 && register_operand (op, DImode))); |
61a55e8b DE |
424 | } |
425 | ||
426 | /* Nonzero if OP is a floating point condition code register. */ | |
427 | ||
428 | int | |
c4ce6853 | 429 | fcc_reg_operand (op, mode) |
61a55e8b DE |
430 | rtx op; |
431 | enum machine_mode mode; | |
432 | { | |
433 | /* This can happen when recog is called from combine. Op may be a MEM. | |
434 | Fail instead of calling abort in this case. */ | |
c4ce6853 | 435 | if (GET_CODE (op) != REG) |
61a55e8b | 436 | return 0; |
304b7a23 | 437 | |
c4ce6853 | 438 | if (mode != VOIDmode && mode != GET_MODE (op)) |
61a55e8b | 439 | return 0; |
304b7a23 DE |
440 | if (mode == VOIDmode |
441 | && (GET_MODE (op) != CCFPmode && GET_MODE (op) != CCFPEmode)) | |
442 | return 0; | |
61a55e8b | 443 | |
c4ce6853 | 444 | #if 0 /* ??? ==> 1 when %fcc0-3 are pseudos first. See gen_compare_reg(). */ |
61a55e8b DE |
445 | if (reg_renumber == 0) |
446 | return REGNO (op) >= FIRST_PSEUDO_REGISTER; | |
447 | return REGNO_OK_FOR_CCFP_P (REGNO (op)); | |
448 | #else | |
c4ce6853 | 449 | return (unsigned) REGNO (op) - SPARC_FIRST_V9_FCC_REG < 4; |
61a55e8b DE |
450 | #endif |
451 | } | |
452 | ||
c4ce6853 DE |
453 | /* Nonzero if OP is an integer or floating point condition code register. */ |
454 | ||
455 | int | |
456 | icc_or_fcc_reg_operand (op, mode) | |
457 | rtx op; | |
458 | enum machine_mode mode; | |
459 | { | |
460 | if (GET_CODE (op) == REG && REGNO (op) == SPARC_ICC_REG) | |
304b7a23 DE |
461 | { |
462 | if (mode != VOIDmode && mode != GET_MODE (op)) | |
463 | return 0; | |
464 | if (mode == VOIDmode | |
465 | && GET_MODE (op) != CCmode && GET_MODE (op) != CCXmode) | |
466 | return 0; | |
467 | return 1; | |
468 | } | |
469 | ||
c4ce6853 DE |
470 | return fcc_reg_operand (op, mode); |
471 | } | |
472 | ||
ab835497 RK |
473 | /* Nonzero if OP can appear as the dest of a RESTORE insn. */ |
474 | int | |
475 | restore_operand (op, mode) | |
476 | rtx op; | |
477 | enum machine_mode mode; | |
478 | { | |
479 | return (GET_CODE (op) == REG && GET_MODE (op) == mode | |
480 | && (REGNO (op) < 8 || (REGNO (op) >= 24 && REGNO (op) < 32))); | |
481 | } | |
482 | ||
401cec23 JW |
483 | /* Call insn on SPARC can take a PC-relative constant address, or any regular |
484 | memory address. */ | |
ab835497 RK |
485 | |
486 | int | |
487 | call_operand (op, mode) | |
488 | rtx op; | |
489 | enum machine_mode mode; | |
490 | { | |
491 | if (GET_CODE (op) != MEM) | |
492 | abort (); | |
493 | op = XEXP (op, 0); | |
2445f289 | 494 | return (symbolic_operand (op, mode) || memory_address_p (Pmode, op)); |
ab835497 RK |
495 | } |
496 | ||
497 | int | |
498 | call_operand_address (op, mode) | |
499 | rtx op; | |
500 | enum machine_mode mode; | |
501 | { | |
2445f289 | 502 | return (symbolic_operand (op, mode) || memory_address_p (Pmode, op)); |
ab835497 RK |
503 | } |
504 | ||
505 | /* Returns 1 if OP is either a symbol reference or a sum of a symbol | |
506 | reference and a constant. */ | |
507 | ||
508 | int | |
509 | symbolic_operand (op, mode) | |
510 | register rtx op; | |
511 | enum machine_mode mode; | |
512 | { | |
513 | switch (GET_CODE (op)) | |
514 | { | |
515 | case SYMBOL_REF: | |
516 | case LABEL_REF: | |
517 | return 1; | |
518 | ||
519 | case CONST: | |
520 | op = XEXP (op, 0); | |
521 | return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF | |
522 | || GET_CODE (XEXP (op, 0)) == LABEL_REF) | |
523 | && GET_CODE (XEXP (op, 1)) == CONST_INT); | |
524 | ||
228b4037 | 525 | /* ??? This clause seems to be irrelevant. */ |
ab835497 RK |
526 | case CONST_DOUBLE: |
527 | return GET_MODE (op) == mode; | |
528 | ||
529 | default: | |
530 | return 0; | |
531 | } | |
532 | } | |
533 | ||
534 | /* Return truth value of statement that OP is a symbolic memory | |
535 | operand of mode MODE. */ | |
536 | ||
537 | int | |
538 | symbolic_memory_operand (op, mode) | |
539 | rtx op; | |
487a6e06 | 540 | enum machine_mode mode ATTRIBUTE_UNUSED; |
ab835497 RK |
541 | { |
542 | if (GET_CODE (op) == SUBREG) | |
543 | op = SUBREG_REG (op); | |
544 | if (GET_CODE (op) != MEM) | |
545 | return 0; | |
546 | op = XEXP (op, 0); | |
547 | return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST | |
548 | || GET_CODE (op) == HIGH || GET_CODE (op) == LABEL_REF); | |
549 | } | |
550 | ||
5ab7138b DE |
551 | /* Return truth value of statement that OP is a LABEL_REF of mode MODE. */ |
552 | ||
553 | int | |
554 | label_ref_operand (op, mode) | |
555 | rtx op; | |
556 | enum machine_mode mode; | |
557 | { | |
558 | if (GET_CODE (op) != LABEL_REF) | |
559 | return 0; | |
560 | if (GET_MODE (op) != mode) | |
561 | return 0; | |
562 | return 1; | |
563 | } | |
564 | ||
95726648 DE |
565 | /* Return 1 if the operand is an argument used in generating pic references |
566 | in either the medium/low or medium/anywhere code models of sparc64. */ | |
567 | ||
568 | int | |
569 | sp64_medium_pic_operand (op, mode) | |
570 | rtx op; | |
487a6e06 | 571 | enum machine_mode mode ATTRIBUTE_UNUSED; |
95726648 DE |
572 | { |
573 | /* Check for (const (minus (symbol_ref:GOT) | |
574 | (const (minus (label) (pc))))). */ | |
575 | if (GET_CODE (op) != CONST) | |
576 | return 0; | |
577 | op = XEXP (op, 0); | |
578 | if (GET_CODE (op) != MINUS) | |
579 | return 0; | |
580 | if (GET_CODE (XEXP (op, 0)) != SYMBOL_REF) | |
581 | return 0; | |
582 | /* ??? Ensure symbol is GOT. */ | |
583 | if (GET_CODE (XEXP (op, 1)) != CONST) | |
584 | return 0; | |
585 | if (GET_CODE (XEXP (XEXP (op, 1), 0)) != MINUS) | |
586 | return 0; | |
587 | return 1; | |
588 | } | |
589 | ||
61a55e8b DE |
590 | /* Return 1 if the operand is a data segment reference. This includes |
591 | the readonly data segment, or in other words anything but the text segment. | |
592 | This is needed in the medium/anywhere code model on v9. These values | |
a0a301fc | 593 | are accessed with EMBMEDANY_BASE_REG. */ |
61a55e8b DE |
594 | |
595 | int | |
596 | data_segment_operand (op, mode) | |
597 | rtx op; | |
487a6e06 | 598 | enum machine_mode mode ATTRIBUTE_UNUSED; |
61a55e8b DE |
599 | { |
600 | switch (GET_CODE (op)) | |
601 | { | |
602 | case SYMBOL_REF : | |
603 | return ! SYMBOL_REF_FLAG (op); | |
604 | case PLUS : | |
95726648 DE |
605 | /* Assume canonical format of symbol + constant. |
606 | Fall through. */ | |
61a55e8b DE |
607 | case CONST : |
608 | return data_segment_operand (XEXP (op, 0)); | |
609 | default : | |
610 | return 0; | |
611 | } | |
612 | } | |
613 | ||
614 | /* Return 1 if the operand is a text segment reference. | |
615 | This is needed in the medium/anywhere code model on v9. */ | |
616 | ||
617 | int | |
618 | text_segment_operand (op, mode) | |
619 | rtx op; | |
487a6e06 | 620 | enum machine_mode mode ATTRIBUTE_UNUSED; |
61a55e8b DE |
621 | { |
622 | switch (GET_CODE (op)) | |
623 | { | |
624 | case LABEL_REF : | |
625 | return 1; | |
626 | case SYMBOL_REF : | |
627 | return SYMBOL_REF_FLAG (op); | |
628 | case PLUS : | |
95726648 DE |
629 | /* Assume canonical format of symbol + constant. |
630 | Fall through. */ | |
61a55e8b DE |
631 | case CONST : |
632 | return text_segment_operand (XEXP (op, 0)); | |
633 | default : | |
634 | return 0; | |
635 | } | |
636 | } | |
637 | ||
ab835497 RK |
638 | /* Return 1 if the operand is either a register or a memory operand that is |
639 | not symbolic. */ | |
640 | ||
641 | int | |
642 | reg_or_nonsymb_mem_operand (op, mode) | |
643 | register rtx op; | |
644 | enum machine_mode mode; | |
645 | { | |
646 | if (register_operand (op, mode)) | |
647 | return 1; | |
648 | ||
649 | if (memory_operand (op, mode) && ! symbolic_memory_operand (op, mode)) | |
650 | return 1; | |
651 | ||
652 | return 0; | |
653 | } | |
654 | ||
ab835497 | 655 | int |
6ac34277 | 656 | splittable_symbolic_memory_operand (op, mode) |
ab835497 | 657 | rtx op; |
487a6e06 | 658 | enum machine_mode mode ATTRIBUTE_UNUSED; |
ab835497 | 659 | { |
6ac34277 DE |
660 | if (GET_CODE (op) != MEM) |
661 | return 0; | |
662 | if (! symbolic_operand (XEXP (op, 0), Pmode)) | |
663 | return 0; | |
664 | return 1; | |
665 | } | |
666 | ||
667 | int | |
668 | splittable_immediate_memory_operand (op, mode) | |
669 | rtx op; | |
487a6e06 | 670 | enum machine_mode mode ATTRIBUTE_UNUSED; |
6ac34277 DE |
671 | { |
672 | if (GET_CODE (op) != MEM) | |
673 | return 0; | |
674 | if (! immediate_operand (XEXP (op, 0), Pmode)) | |
675 | return 0; | |
676 | return 1; | |
ab835497 RK |
677 | } |
678 | ||
679 | /* Return truth value of whether OP is EQ or NE. */ | |
680 | ||
681 | int | |
682 | eq_or_neq (op, mode) | |
683 | rtx op; | |
487a6e06 | 684 | enum machine_mode mode ATTRIBUTE_UNUSED; |
ab835497 RK |
685 | { |
686 | return (GET_CODE (op) == EQ || GET_CODE (op) == NE); | |
687 | } | |
688 | ||
689 | /* Return 1 if this is a comparison operator, but not an EQ, NE, GEU, | |
690 | or LTU for non-floating-point. We handle those specially. */ | |
691 | ||
692 | int | |
693 | normal_comp_operator (op, mode) | |
694 | rtx op; | |
487a6e06 | 695 | enum machine_mode mode ATTRIBUTE_UNUSED; |
ab835497 RK |
696 | { |
697 | enum rtx_code code = GET_CODE (op); | |
698 | ||
699 | if (GET_RTX_CLASS (code) != '<') | |
700 | return 0; | |
701 | ||
4d449554 JW |
702 | if (GET_MODE (XEXP (op, 0)) == CCFPmode |
703 | || GET_MODE (XEXP (op, 0)) == CCFPEmode) | |
ab835497 RK |
704 | return 1; |
705 | ||
706 | return (code != NE && code != EQ && code != GEU && code != LTU); | |
707 | } | |
708 | ||
709 | /* Return 1 if this is a comparison operator. This allows the use of | |
710 | MATCH_OPERATOR to recognize all the branch insns. */ | |
711 | ||
712 | int | |
713 | noov_compare_op (op, mode) | |
714 | register rtx op; | |
487a6e06 | 715 | enum machine_mode mode ATTRIBUTE_UNUSED; |
ab835497 RK |
716 | { |
717 | enum rtx_code code = GET_CODE (op); | |
718 | ||
719 | if (GET_RTX_CLASS (code) != '<') | |
720 | return 0; | |
721 | ||
722 | if (GET_MODE (XEXP (op, 0)) == CC_NOOVmode) | |
723 | /* These are the only branches which work with CC_NOOVmode. */ | |
724 | return (code == EQ || code == NE || code == GE || code == LT); | |
725 | return 1; | |
726 | } | |
727 | ||
61a55e8b DE |
728 | /* Nonzero if OP is a comparison operator suitable for use in v9 |
729 | conditional move or branch on register contents instructions. */ | |
730 | ||
731 | int | |
732 | v9_regcmp_op (op, mode) | |
733 | register rtx op; | |
487a6e06 | 734 | enum machine_mode mode ATTRIBUTE_UNUSED; |
61a55e8b DE |
735 | { |
736 | enum rtx_code code = GET_CODE (op); | |
737 | ||
738 | if (GET_RTX_CLASS (code) != '<') | |
739 | return 0; | |
740 | ||
cd5fb1ee | 741 | return v9_regcmp_p (code); |
61a55e8b DE |
742 | } |
743 | ||
ab835497 RK |
744 | /* Return 1 if this is a SIGN_EXTEND or ZERO_EXTEND operation. */ |
745 | ||
746 | int | |
747 | extend_op (op, mode) | |
748 | rtx op; | |
487a6e06 | 749 | enum machine_mode mode ATTRIBUTE_UNUSED; |
ab835497 RK |
750 | { |
751 | return GET_CODE (op) == SIGN_EXTEND || GET_CODE (op) == ZERO_EXTEND; | |
752 | } | |
753 | ||
754 | /* Return nonzero if OP is an operator of mode MODE which can set | |
755 | the condition codes explicitly. We do not include PLUS and MINUS | |
756 | because these require CC_NOOVmode, which we handle explicitly. */ | |
757 | ||
758 | int | |
759 | cc_arithop (op, mode) | |
760 | rtx op; | |
487a6e06 | 761 | enum machine_mode mode ATTRIBUTE_UNUSED; |
ab835497 RK |
762 | { |
763 | if (GET_CODE (op) == AND | |
764 | || GET_CODE (op) == IOR | |
765 | || GET_CODE (op) == XOR) | |
766 | return 1; | |
767 | ||
768 | return 0; | |
769 | } | |
770 | ||
771 | /* Return nonzero if OP is an operator of mode MODE which can bitwise | |
772 | complement its second operand and set the condition codes explicitly. */ | |
773 | ||
774 | int | |
775 | cc_arithopn (op, mode) | |
776 | rtx op; | |
487a6e06 | 777 | enum machine_mode mode ATTRIBUTE_UNUSED; |
ab835497 RK |
778 | { |
779 | /* XOR is not here because combine canonicalizes (xor (not ...) ...) | |
780 | and (xor ... (not ...)) to (not (xor ...)). */ | |
781 | return (GET_CODE (op) == AND | |
782 | || GET_CODE (op) == IOR); | |
783 | } | |
784 | \f | |
58cbf20e DE |
785 | /* Return true if OP is a register, or is a CONST_INT that can fit in a |
786 | signed 13 bit immediate field. This is an acceptable SImode operand for | |
787 | most 3 address instructions. */ | |
ab835497 RK |
788 | |
789 | int | |
790 | arith_operand (op, mode) | |
791 | rtx op; | |
792 | enum machine_mode mode; | |
793 | { | |
284d86e9 | 794 | int val; |
f7e0e539 DM |
795 | if (register_operand (op, mode) |
796 | || GET_CODE (op) == CONSTANT_P_RTX) | |
284d86e9 JC |
797 | return 1; |
798 | if (GET_CODE (op) != CONST_INT) | |
799 | return 0; | |
800 | val = INTVAL (op) & 0xffffffff; | |
801 | return SPARC_SIMM13_P (val); | |
ab835497 RK |
802 | } |
803 | ||
5d6d3339 JJ |
804 | /* Return true if OP is a constant 4096 */ |
805 | ||
806 | int | |
807 | arith_4096_operand (op, mode) | |
808 | rtx op; | |
ddf80874 | 809 | enum machine_mode mode ATTRIBUTE_UNUSED; |
5d6d3339 JJ |
810 | { |
811 | int val; | |
812 | if (GET_CODE (op) != CONST_INT) | |
813 | return 0; | |
814 | val = INTVAL (op) & 0xffffffff; | |
815 | return val == 4096; | |
816 | } | |
817 | ||
818 | /* Return true if OP is suitable as second operand for add/sub */ | |
819 | ||
820 | int | |
821 | arith_add_operand (op, mode) | |
822 | rtx op; | |
823 | enum machine_mode mode; | |
824 | { | |
825 | return arith_operand (op, mode) || arith_4096_operand (op, mode); | |
826 | } | |
827 | ||
89e65674 DM |
828 | /* Return true if OP is a CONST_INT or a CONST_DOUBLE which can fit in the |
829 | immediate field of OR and XOR instructions. Used for 64-bit | |
830 | constant formation patterns. */ | |
831 | int | |
832 | const64_operand (op, mode) | |
833 | rtx op; | |
ddf80874 | 834 | enum machine_mode mode ATTRIBUTE_UNUSED; |
89e65674 DM |
835 | { |
836 | return ((GET_CODE (op) == CONST_INT | |
837 | && SPARC_SIMM13_P (INTVAL (op))) | |
9208e4b2 | 838 | #if HOST_BITS_PER_WIDE_INT != 64 |
89e65674 | 839 | || (GET_CODE (op) == CONST_DOUBLE |
9208e4b2 DM |
840 | && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op)) |
841 | && (CONST_DOUBLE_HIGH (op) == | |
842 | ((CONST_DOUBLE_LOW (op) & 0x80000000) != 0 ? | |
ddf80874 | 843 | (HOST_WIDE_INT)0xffffffff : 0))) |
9208e4b2 | 844 | #endif |
89e65674 DM |
845 | || GET_CODE (op) == CONSTANT_P_RTX); |
846 | } | |
847 | ||
9208e4b2 | 848 | /* The same, but only for sethi instructions. */ |
89e65674 DM |
849 | int |
850 | const64_high_operand (op, mode) | |
851 | rtx op; | |
ddf80874 | 852 | enum machine_mode mode ATTRIBUTE_UNUSED; |
89e65674 DM |
853 | { |
854 | return ((GET_CODE (op) == CONST_INT | |
9208e4b2 DM |
855 | && (INTVAL (op) & 0xfffffc00) != 0 |
856 | && SPARC_SETHI_P (INTVAL (op)) | |
857 | #if HOST_BITS_PER_WIDE_INT != 64 | |
858 | /* Must be positive on non-64bit host else the | |
859 | optimizer is fooled into thinking that sethi | |
860 | sign extends, even though it does not. */ | |
861 | && INTVAL (op) >= 0 | |
862 | #endif | |
863 | ) | |
89e65674 DM |
864 | || (GET_CODE (op) == CONST_DOUBLE |
865 | && CONST_DOUBLE_HIGH (op) == 0 | |
9208e4b2 | 866 | && (CONST_DOUBLE_LOW (op) & 0xfffffc00) != 0 |
89e65674 DM |
867 | && SPARC_SETHI_P (CONST_DOUBLE_LOW (op))) |
868 | || GET_CODE (op) == CONSTANT_P_RTX); | |
869 | } | |
870 | ||
58cbf20e DE |
871 | /* Return true if OP is a register, or is a CONST_INT that can fit in a |
872 | signed 11 bit immediate field. This is an acceptable SImode operand for | |
873 | the movcc instructions. */ | |
61a55e8b DE |
874 | |
875 | int | |
876 | arith11_operand (op, mode) | |
877 | rtx op; | |
878 | enum machine_mode mode; | |
879 | { | |
880 | return (register_operand (op, mode) | |
f7e0e539 | 881 | || GET_CODE (op) == CONSTANT_P_RTX |
58cbf20e | 882 | || (GET_CODE (op) == CONST_INT && SPARC_SIMM11_P (INTVAL (op)))); |
61a55e8b DE |
883 | } |
884 | ||
58cbf20e DE |
885 | /* Return true if OP is a register, or is a CONST_INT that can fit in a |
886 | signed 10 bit immediate field. This is an acceptable SImode operand for | |
887 | the movrcc instructions. */ | |
61a55e8b DE |
888 | |
889 | int | |
890 | arith10_operand (op, mode) | |
891 | rtx op; | |
892 | enum machine_mode mode; | |
893 | { | |
894 | return (register_operand (op, mode) | |
f7e0e539 | 895 | || GET_CODE (op) == CONSTANT_P_RTX |
58cbf20e | 896 | || (GET_CODE (op) == CONST_INT && SPARC_SIMM10_P (INTVAL (op)))); |
61a55e8b DE |
897 | } |
898 | ||
23b8a89f JW |
899 | /* Return true if OP is a register, is a CONST_INT that fits in a 13 bit |
900 | immediate field, or is a CONST_DOUBLE whose both parts fit in a 13 bit | |
61a55e8b DE |
901 | immediate field. |
902 | v9: Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that | |
903 | can fit in a 13 bit immediate field. This is an acceptable DImode operand | |
904 | for most 3 address instructions. */ | |
ab835497 RK |
905 | |
906 | int | |
907 | arith_double_operand (op, mode) | |
908 | rtx op; | |
909 | enum machine_mode mode; | |
910 | { | |
911 | return (register_operand (op, mode) | |
f7e0e539 | 912 | || GET_CODE (op) == CONSTANT_P_RTX |
23b8a89f | 913 | || (GET_CODE (op) == CONST_INT && SMALL_INT (op)) |
a9e27770 | 914 | || (! TARGET_ARCH64 |
61a55e8b | 915 | && GET_CODE (op) == CONST_DOUBLE |
bf62bbf1 DE |
916 | && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x1000) < 0x2000 |
917 | && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_HIGH (op) + 0x1000) < 0x2000) | |
a9e27770 | 918 | || (TARGET_ARCH64 |
61a55e8b | 919 | && GET_CODE (op) == CONST_DOUBLE |
bf62bbf1 | 920 | && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x1000) < 0x2000 |
61a55e8b DE |
921 | && ((CONST_DOUBLE_HIGH (op) == -1 |
922 | && (CONST_DOUBLE_LOW (op) & 0x1000) == 0x1000) | |
923 | || (CONST_DOUBLE_HIGH (op) == 0 | |
924 | && (CONST_DOUBLE_LOW (op) & 0x1000) == 0)))); | |
925 | } | |
926 | ||
5d6d3339 JJ |
927 | /* Return true if OP is a constant 4096 for DImode on ARCH64 */ |
928 | ||
929 | int | |
930 | arith_double_4096_operand (op, mode) | |
931 | rtx op; | |
ddf80874 | 932 | enum machine_mode mode ATTRIBUTE_UNUSED; |
5d6d3339 JJ |
933 | { |
934 | return (TARGET_ARCH64 && | |
935 | ((GET_CODE (op) == CONST_INT && INTVAL (op) == 4096) || | |
936 | (GET_CODE (op) == CONST_DOUBLE && | |
937 | CONST_DOUBLE_LOW (op) == 4096 && | |
938 | CONST_DOUBLE_HIGH (op) == 0))); | |
939 | } | |
940 | ||
941 | /* Return true if OP is suitable as second operand for add/sub in DImode */ | |
942 | ||
943 | int | |
944 | arith_double_add_operand (op, mode) | |
945 | rtx op; | |
946 | enum machine_mode mode; | |
947 | { | |
948 | return arith_double_operand (op, mode) || arith_double_4096_operand (op, mode); | |
949 | } | |
950 | ||
61a55e8b DE |
951 | /* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that |
952 | can fit in an 11 bit immediate field. This is an acceptable DImode | |
953 | operand for the movcc instructions. */ | |
954 | /* ??? Replace with arith11_operand? */ | |
955 | ||
956 | int | |
957 | arith11_double_operand (op, mode) | |
958 | rtx op; | |
959 | enum machine_mode mode; | |
960 | { | |
961 | return (register_operand (op, mode) | |
f7e0e539 | 962 | || GET_CODE (op) == CONSTANT_P_RTX |
61a55e8b DE |
963 | || (GET_CODE (op) == CONST_DOUBLE |
964 | && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode) | |
bf62bbf1 | 965 | && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x400) < 0x800 |
61a55e8b DE |
966 | && ((CONST_DOUBLE_HIGH (op) == -1 |
967 | && (CONST_DOUBLE_LOW (op) & 0x400) == 0x400) | |
968 | || (CONST_DOUBLE_HIGH (op) == 0 | |
969 | && (CONST_DOUBLE_LOW (op) & 0x400) == 0))) | |
970 | || (GET_CODE (op) == CONST_INT | |
971 | && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode) | |
bf62bbf1 | 972 | && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x400) < 0x800)); |
61a55e8b DE |
973 | } |
974 | ||
975 | /* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that | |
976 | can fit in an 10 bit immediate field. This is an acceptable DImode | |
977 | operand for the movrcc instructions. */ | |
978 | /* ??? Replace with arith10_operand? */ | |
979 | ||
980 | int | |
981 | arith10_double_operand (op, mode) | |
982 | rtx op; | |
983 | enum machine_mode mode; | |
984 | { | |
985 | return (register_operand (op, mode) | |
f7e0e539 | 986 | || GET_CODE (op) == CONSTANT_P_RTX |
61a55e8b DE |
987 | || (GET_CODE (op) == CONST_DOUBLE |
988 | && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode) | |
989 | && (unsigned) (CONST_DOUBLE_LOW (op) + 0x200) < 0x400 | |
990 | && ((CONST_DOUBLE_HIGH (op) == -1 | |
991 | && (CONST_DOUBLE_LOW (op) & 0x200) == 0x200) | |
992 | || (CONST_DOUBLE_HIGH (op) == 0 | |
993 | && (CONST_DOUBLE_LOW (op) & 0x200) == 0))) | |
994 | || (GET_CODE (op) == CONST_INT | |
995 | && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode) | |
bf62bbf1 | 996 | && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x200) < 0x400)); |
ab835497 RK |
997 | } |
998 | ||
999 | /* Return truth value of whether OP is a integer which fits the | |
228b4037 JW |
1000 | range constraining immediate operands in most three-address insns, |
1001 | which have a 13 bit immediate field. */ | |
ab835497 RK |
1002 | |
1003 | int | |
1004 | small_int (op, mode) | |
1005 | rtx op; | |
487a6e06 | 1006 | enum machine_mode mode ATTRIBUTE_UNUSED; |
ab835497 | 1007 | { |
f7e0e539 DM |
1008 | return ((GET_CODE (op) == CONST_INT && SMALL_INT (op)) |
1009 | || GET_CODE (op) == CONSTANT_P_RTX); | |
ab835497 RK |
1010 | } |
1011 | ||
e0d80184 DM |
1012 | int |
1013 | small_int_or_double (op, mode) | |
1014 | rtx op; | |
1015 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
1016 | { | |
1017 | return ((GET_CODE (op) == CONST_INT && SMALL_INT (op)) | |
1018 | || (GET_CODE (op) == CONST_DOUBLE | |
1019 | && CONST_DOUBLE_HIGH (op) == 0 | |
1020 | && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op))) | |
1021 | || GET_CODE (op) == CONSTANT_P_RTX); | |
1022 | } | |
1023 | ||
9b3fad96 JW |
1024 | /* Recognize operand values for the umul instruction. That instruction sign |
1025 | extends immediate values just like all other sparc instructions, but | |
1026 | interprets the extended result as an unsigned number. */ | |
1027 | ||
1028 | int | |
1029 | uns_small_int (op, mode) | |
1030 | rtx op; | |
487a6e06 | 1031 | enum machine_mode mode ATTRIBUTE_UNUSED; |
9b3fad96 JW |
1032 | { |
1033 | #if HOST_BITS_PER_WIDE_INT > 32 | |
1034 | /* All allowed constants will fit a CONST_INT. */ | |
f7e0e539 DM |
1035 | return ((GET_CODE (op) == CONST_INT |
1036 | && ((INTVAL (op) >= 0 && INTVAL (op) < 0x1000) | |
e0d80184 DM |
1037 | || (INTVAL (op) >= 0xFFFFF000 |
1038 | && INTVAL (op) < 0x100000000))) | |
f7e0e539 | 1039 | || GET_CODE (op) == CONSTANT_P_RTX); |
9b3fad96 | 1040 | #else |
f7e0e539 DM |
1041 | return (((GET_CODE (op) == CONST_INT && (unsigned) INTVAL (op) < 0x1000) |
1042 | || (GET_CODE (op) == CONST_DOUBLE | |
1043 | && CONST_DOUBLE_HIGH (op) == 0 | |
1044 | && (unsigned) CONST_DOUBLE_LOW (op) - 0xFFFFF000 < 0x1000)) | |
1045 | || GET_CODE (op) == CONSTANT_P_RTX); | |
9b3fad96 JW |
1046 | #endif |
1047 | } | |
1048 | ||
1049 | int | |
1050 | uns_arith_operand (op, mode) | |
1051 | rtx op; | |
1052 | enum machine_mode mode; | |
1053 | { | |
1054 | return register_operand (op, mode) || uns_small_int (op, mode); | |
1055 | } | |
1056 | ||
ab835497 RK |
1057 | /* Return truth value of statement that OP is a call-clobbered register. */ |
1058 | int | |
1059 | clobbered_register (op, mode) | |
1060 | rtx op; | |
487a6e06 | 1061 | enum machine_mode mode ATTRIBUTE_UNUSED; |
ab835497 RK |
1062 | { |
1063 | return (GET_CODE (op) == REG && call_used_regs[REGNO (op)]); | |
1064 | } | |
ab835497 | 1065 | |
e0d80184 DM |
1066 | /* Return 1 if OP is const0_rtx, used for TARGET_LIVE_G0 insns. */ |
1067 | ||
1068 | int | |
1069 | zero_operand (op, mode) | |
1070 | rtx op; | |
1071 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
ab835497 | 1072 | { |
e0d80184 DM |
1073 | return (op == const0_rtx || GET_CODE (op) == CONSTANT_P_RTX); |
1074 | } | |
61a55e8b | 1075 | |
e0d80184 | 1076 | /* Return 1 if OP is a valid operand for the source of a move insn. */ |
61a55e8b | 1077 | |
e0d80184 DM |
1078 | int |
1079 | input_operand (op, mode) | |
1080 | rtx op; | |
1081 | enum machine_mode mode; | |
1082 | { | |
1083 | /* If both modes are non-void they must be the same. */ | |
1084 | if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op)) | |
1085 | return 0; | |
61a55e8b | 1086 | |
e0d80184 DM |
1087 | /* Allow any one instruction integer constant, and all CONST_INT |
1088 | variants when we are working in DImode and !arch64. */ | |
1089 | if (GET_MODE_CLASS (mode) == MODE_INT | |
9208e4b2 DM |
1090 | && ((GET_CODE (op) == CONST_INT |
1091 | && ((SPARC_SETHI_P (INTVAL (op)) | |
1092 | && (! TARGET_ARCH64 | |
1093 | || (INTVAL (op) >= 0) | |
1094 | || mode == SImode)) | |
1095 | || SPARC_SIMM13_P (INTVAL (op)) | |
1096 | || (mode == DImode | |
1097 | && ! TARGET_ARCH64))) | |
1098 | || (TARGET_ARCH64 | |
1099 | && GET_CODE (op) == CONST_DOUBLE | |
1100 | && ((CONST_DOUBLE_HIGH (op) == 0 | |
1101 | && SPARC_SETHI_P (CONST_DOUBLE_LOW (op))) | |
1102 | || | |
1103 | #if HOST_BITS_PER_WIDE_INT == 64 | |
1104 | (CONST_DOUBLE_HIGH (op) == 0 | |
1105 | && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op))) | |
1106 | #else | |
1107 | (SPARC_SIMM13_P (CONST_DOUBLE_LOW (op)) | |
1108 | && (((CONST_DOUBLE_LOW (op) & 0x80000000) == 0 | |
1109 | && CONST_DOUBLE_HIGH (op) == 0) | |
1110 | || (CONST_DOUBLE_HIGH (op) == -1))) | |
1111 | #endif | |
1112 | )))) | |
e0d80184 DM |
1113 | return 1; |
1114 | ||
1115 | /* Always match this. */ | |
1116 | if (GET_CODE (op) == CONSTANT_P_RTX) | |
1117 | return 1; | |
1118 | ||
1119 | /* If !arch64 and this is a DImode const, allow it so that | |
1120 | the splits can be generated. */ | |
1121 | if (! TARGET_ARCH64 | |
1122 | && mode == DImode | |
1123 | && GET_CODE (op) == CONST_DOUBLE) | |
1124 | return 1; | |
1125 | ||
1126 | if (register_operand (op, mode)) | |
1127 | return 1; | |
1128 | ||
1129 | /* If this is a SUBREG, look inside so that we handle | |
1130 | paradoxical ones. */ | |
1131 | if (GET_CODE (op) == SUBREG) | |
1132 | op = SUBREG_REG (op); | |
1133 | ||
1134 | /* Check for valid MEM forms. */ | |
1135 | if (GET_CODE (op) == MEM) | |
61a55e8b | 1136 | { |
e0d80184 | 1137 | rtx inside = XEXP (op, 0); |
61a55e8b | 1138 | |
e0d80184 | 1139 | if (GET_CODE (inside) == LO_SUM) |
03ad6f4d DM |
1140 | { |
1141 | /* We can't allow these because all of the splits | |
1142 | (eventually as they trickle down into DFmode | |
1143 | splits) require offsettable memory references. */ | |
1144 | if (! TARGET_V9 | |
1145 | && GET_MODE (op) == TFmode) | |
1146 | return 0; | |
1147 | ||
1148 | return (register_operand (XEXP (inside, 0), Pmode) | |
1149 | && CONSTANT_P (XEXP (inside, 1))); | |
1150 | } | |
e0d80184 | 1151 | return memory_address_p (mode, inside); |
61a55e8b | 1152 | } |
ab835497 | 1153 | |
e0d80184 DM |
1154 | return 0; |
1155 | } | |
1156 | ||
1157 | \f | |
1158 | /* We know it can't be done in one insn when we get here, | |
1159 | the movsi expander guarentees this. */ | |
1160 | void | |
1161 | sparc_emit_set_const32 (op0, op1) | |
1162 | rtx op0; | |
1163 | rtx op1; | |
1164 | { | |
1165 | enum machine_mode mode = GET_MODE (op0); | |
1166 | rtx temp; | |
1167 | ||
1168 | if (GET_CODE (op1) == CONST_INT) | |
284d86e9 | 1169 | { |
2a01c939 | 1170 | HOST_WIDE_INT value = INTVAL (op1); |
e0d80184 DM |
1171 | |
1172 | if (SPARC_SETHI_P (value) | |
1173 | || SPARC_SIMM13_P (value)) | |
1174 | abort (); | |
284d86e9 | 1175 | } |
e0d80184 DM |
1176 | |
1177 | /* Full 2-insn decomposition is needed. */ | |
1178 | if (reload_in_progress || reload_completed) | |
1179 | temp = op0; | |
284d86e9 | 1180 | else |
e0d80184 DM |
1181 | temp = gen_reg_rtx (mode); |
1182 | ||
71648202 DM |
1183 | if (GET_CODE (op1) == CONST_INT) |
1184 | { | |
1185 | /* Emit them as real moves instead of a HIGH/LO_SUM, | |
1186 | this way CSE can see everything and reuse intermediate | |
1187 | values if it wants. */ | |
1188 | if (TARGET_ARCH64 | |
1189 | && HOST_BITS_PER_WIDE_INT != 64 | |
1190 | && (INTVAL (op1) & 0x80000000) != 0) | |
1191 | { | |
1192 | emit_insn (gen_rtx_SET (VOIDmode, | |
1193 | temp, | |
1194 | gen_rtx_CONST_DOUBLE (VOIDmode, const0_rtx, | |
1195 | INTVAL (op1) & 0xfffffc00, 0))); | |
1196 | } | |
1197 | else | |
1198 | { | |
1199 | emit_insn (gen_rtx_SET (VOIDmode, | |
1200 | temp, | |
1201 | GEN_INT (INTVAL (op1) & 0xfffffc00))); | |
1202 | } | |
1203 | emit_insn (gen_rtx_SET (VOIDmode, | |
1204 | op0, | |
1205 | gen_rtx_IOR (mode, | |
1206 | temp, | |
1207 | GEN_INT (INTVAL (op1) & 0x3ff)))); | |
1208 | } | |
1209 | else | |
1210 | { | |
1211 | /* A symbol, emit in the traditional way. */ | |
1212 | emit_insn (gen_rtx_SET (VOIDmode, | |
1213 | temp, | |
1214 | gen_rtx_HIGH (mode, | |
1215 | op1))); | |
1216 | emit_insn (gen_rtx_SET (VOIDmode, | |
1217 | op0, | |
1218 | gen_rtx_LO_SUM (mode, | |
1219 | temp, | |
1220 | op1))); | |
1221 | ||
1222 | } | |
e0d80184 DM |
1223 | } |
1224 | ||
1225 | \f | |
1226 | /* Sparc-v9 code-model support. */ | |
1227 | void | |
1228 | sparc_emit_set_symbolic_const64 (op0, op1, temp1) | |
1229 | rtx op0; | |
1230 | rtx op1; | |
1231 | rtx temp1; | |
1232 | { | |
1233 | switch (sparc_cmodel) | |
284d86e9 | 1234 | { |
e0d80184 DM |
1235 | case CM_MEDLOW: |
1236 | /* The range spanned by all instructions in the object is less | |
1237 | than 2^31 bytes (2GB) and the distance from any instruction | |
1238 | to the location of the label _GLOBAL_OFFSET_TABLE_ is less | |
1239 | than 2^31 bytes (2GB). | |
ab835497 | 1240 | |
e0d80184 DM |
1241 | The executable must be in the low 4TB of the virtual address |
1242 | space. | |
61a55e8b | 1243 | |
e0d80184 DM |
1244 | sethi %hi(symbol), %temp |
1245 | or %temp, %lo(symbol), %reg */ | |
9208e4b2 DM |
1246 | emit_insn (gen_rtx_SET (VOIDmode, temp1, gen_rtx_HIGH (DImode, op1))); |
1247 | emit_insn (gen_rtx_SET (VOIDmode, op0, gen_rtx_LO_SUM (DImode, temp1, op1))); | |
e0d80184 | 1248 | break; |
61a55e8b | 1249 | |
e0d80184 DM |
1250 | case CM_MEDMID: |
1251 | /* The range spanned by all instructions in the object is less | |
1252 | than 2^31 bytes (2GB) and the distance from any instruction | |
1253 | to the location of the label _GLOBAL_OFFSET_TABLE_ is less | |
1254 | than 2^31 bytes (2GB). | |
1255 | ||
1256 | The executable must be in the low 16TB of the virtual address | |
1257 | space. | |
1258 | ||
1259 | sethi %h44(symbol), %temp1 | |
1260 | or %temp1, %m44(symbol), %temp2 | |
1261 | sllx %temp2, 12, %temp3 | |
1262 | or %temp3, %l44(symbol), %reg */ | |
1263 | emit_insn (gen_seth44 (op0, op1)); | |
1264 | emit_insn (gen_setm44 (op0, op0, op1)); | |
9208e4b2 | 1265 | emit_insn (gen_rtx_SET (VOIDmode, temp1, |
e0d80184 DM |
1266 | gen_rtx_ASHIFT (DImode, op0, GEN_INT (12)))); |
1267 | emit_insn (gen_setl44 (op0, temp1, op1)); | |
1268 | break; | |
61a55e8b | 1269 | |
e0d80184 DM |
1270 | case CM_MEDANY: |
1271 | /* The range spanned by all instructions in the object is less | |
1272 | than 2^31 bytes (2GB) and the distance from any instruction | |
1273 | to the location of the label _GLOBAL_OFFSET_TABLE_ is less | |
1274 | than 2^31 bytes (2GB). | |
1275 | ||
1276 | The executable can be placed anywhere in the virtual address | |
1277 | space. | |
1278 | ||
1279 | sethi %hh(symbol), %temp1 | |
1280 | sethi %lm(symbol), %temp2 | |
1281 | or %temp1, %hm(symbol), %temp3 | |
1282 | or %temp2, %lo(symbol), %temp4 | |
1283 | sllx %temp3, 32, %temp5 | |
1284 | or %temp4, %temp5, %reg */ | |
1285 | ||
1286 | /* Getting this right wrt. reloading is really tricky. | |
1287 | We _MUST_ have a seperate temporary at this point, | |
1288 | if we don't barf immediately instead of generating | |
1289 | incorrect code. */ | |
1290 | if (temp1 == op0) | |
1291 | abort (); | |
61a55e8b | 1292 | |
e0d80184 DM |
1293 | emit_insn (gen_sethh (op0, op1)); |
1294 | emit_insn (gen_setlm (temp1, op1)); | |
1295 | emit_insn (gen_sethm (op0, op0, op1)); | |
9208e4b2 | 1296 | emit_insn (gen_rtx_SET (VOIDmode, op0, |
e0d80184 | 1297 | gen_rtx_ASHIFT (DImode, op0, GEN_INT (32)))); |
9208e4b2 | 1298 | emit_insn (gen_rtx_SET (VOIDmode, op0, |
e0d80184 DM |
1299 | gen_rtx_PLUS (DImode, op0, temp1))); |
1300 | emit_insn (gen_setlo (op0, op0, op1)); | |
1301 | break; | |
61a55e8b | 1302 | |
e0d80184 DM |
1303 | case CM_EMBMEDANY: |
1304 | /* Old old old backwards compatibility kruft here. | |
1305 | Essentially it is MEDLOW with a fixed 64-bit | |
1306 | virtual base added to all data segment addresses. | |
1307 | Text-segment stuff is computed like MEDANY, we can't | |
1308 | reuse the code above because the relocation knobs | |
1309 | look different. | |
1310 | ||
1311 | Data segment: sethi %hi(symbol), %temp1 | |
1312 | or %temp1, %lo(symbol), %temp2 | |
1313 | add %temp2, EMBMEDANY_BASE_REG, %reg | |
1314 | ||
1315 | Text segment: sethi %uhi(symbol), %temp1 | |
1316 | sethi %hi(symbol), %temp2 | |
1317 | or %temp1, %ulo(symbol), %temp3 | |
1318 | or %temp2, %lo(symbol), %temp4 | |
1319 | sllx %temp3, 32, %temp5 | |
1320 | or %temp4, %temp5, %reg */ | |
1321 | if (data_segment_operand (op1, GET_MODE (op1))) | |
1322 | { | |
1323 | emit_insn (gen_embmedany_sethi (temp1, op1)); | |
1324 | emit_insn (gen_embmedany_brsum (op0, temp1)); | |
1325 | emit_insn (gen_embmedany_losum (op0, op0, op1)); | |
1326 | } | |
1327 | else | |
1328 | { | |
1329 | /* Getting this right wrt. reloading is really tricky. | |
1330 | We _MUST_ have a seperate temporary at this point, | |
f710f868 | 1331 | so we barf immediately instead of generating |
e0d80184 DM |
1332 | incorrect code. */ |
1333 | if (temp1 == op0) | |
1334 | abort (); | |
61a55e8b | 1335 | |
e0d80184 DM |
1336 | emit_insn (gen_embmedany_textuhi (op0, op1)); |
1337 | emit_insn (gen_embmedany_texthi (temp1, op1)); | |
1338 | emit_insn (gen_embmedany_textulo (op0, op0, op1)); | |
9208e4b2 | 1339 | emit_insn (gen_rtx_SET (VOIDmode, op0, |
e0d80184 | 1340 | gen_rtx_ASHIFT (DImode, op0, GEN_INT (32)))); |
9208e4b2 | 1341 | emit_insn (gen_rtx_SET (VOIDmode, op0, |
e0d80184 DM |
1342 | gen_rtx_PLUS (DImode, op0, temp1))); |
1343 | emit_insn (gen_embmedany_textlo (op0, op0, op1)); | |
1344 | } | |
1345 | break; | |
1346 | ||
1347 | default: | |
1348 | abort(); | |
1349 | } | |
1350 | } | |
1351 | ||
9208e4b2 DM |
1352 | /* These avoid problems when cross compiling. If we do not |
1353 | go through all this hair then the optimizer will see | |
1354 | invalid REG_EQUAL notes or in some cases none at all. */ | |
1355 | static void sparc_emit_set_safe_HIGH64 PROTO ((rtx, HOST_WIDE_INT)); | |
1356 | static rtx gen_safe_SET64 PROTO ((rtx, HOST_WIDE_INT)); | |
1357 | static rtx gen_safe_OR64 PROTO ((rtx, HOST_WIDE_INT)); | |
1358 | static rtx gen_safe_XOR64 PROTO ((rtx, HOST_WIDE_INT)); | |
1359 | ||
1360 | #if HOST_BITS_PER_WIDE_INT == 64 | |
1361 | #define GEN_HIGHINT64(__x) GEN_INT ((__x) & 0xfffffc00) | |
1362 | #define GEN_INT64(__x) GEN_INT (__x) | |
1363 | #else | |
1364 | #define GEN_HIGHINT64(__x) \ | |
1365 | gen_rtx_CONST_DOUBLE (VOIDmode, const0_rtx, \ | |
1366 | (__x) & 0xfffffc00, 0) | |
1367 | #define GEN_INT64(__x) \ | |
1368 | gen_rtx_CONST_DOUBLE (VOIDmode, const0_rtx, \ | |
1369 | (__x) & 0xffffffff, \ | |
1370 | ((__x) & 0x80000000 \ | |
1371 | ? 0xffffffff : 0)) | |
1372 | #endif | |
1373 | ||
1374 | /* The optimizer is not to assume anything about exactly | |
1375 | which bits are set for a HIGH, they are unspecified. | |
1376 | Unfortunately this leads to many missed optimizations | |
1377 | during CSE. We mask out the non-HIGH bits, and matches | |
1378 | a plain movdi, to alleviate this problem. */ | |
1379 | static void | |
1380 | sparc_emit_set_safe_HIGH64 (dest, val) | |
1381 | rtx dest; | |
1382 | HOST_WIDE_INT val; | |
1383 | { | |
1384 | emit_insn (gen_rtx_SET (VOIDmode, dest, GEN_HIGHINT64 (val))); | |
1385 | } | |
2a01c939 | 1386 | |
e0d80184 | 1387 | static rtx |
9208e4b2 DM |
1388 | gen_safe_SET64 (dest, val) |
1389 | rtx dest; | |
e0d80184 | 1390 | HOST_WIDE_INT val; |
61a55e8b | 1391 | { |
9208e4b2 DM |
1392 | return gen_rtx_SET (VOIDmode, dest, GEN_INT64 (val)); |
1393 | } | |
1394 | ||
1395 | static rtx | |
1396 | gen_safe_OR64 (src, val) | |
1397 | rtx src; | |
1398 | HOST_WIDE_INT val; | |
1399 | { | |
1400 | return gen_rtx_IOR (DImode, src, GEN_INT64 (val)); | |
1401 | } | |
1402 | ||
1403 | static rtx | |
1404 | gen_safe_XOR64 (src, val) | |
1405 | rtx src; | |
1406 | HOST_WIDE_INT val; | |
1407 | { | |
1408 | return gen_rtx_XOR (DImode, src, GEN_INT64 (val)); | |
e0d80184 | 1409 | } |
61a55e8b | 1410 | |
e0d80184 DM |
1411 | /* Worker routines for 64-bit constant formation on arch64. |
1412 | One of the key things to be doing in these emissions is | |
1413 | to create as many temp REGs as possible. This makes it | |
1414 | possible for half-built constants to be used later when | |
1415 | such values are similar to something required later on. | |
1416 | Without doing this, the optimizer cannot see such | |
1417 | opportunities. */ | |
2a01c939 DM |
1418 | |
1419 | static void sparc_emit_set_const64_quick1 | |
1420 | PROTO((rtx, rtx, unsigned HOST_WIDE_INT, int)); | |
1421 | ||
e0d80184 DM |
1422 | static void |
1423 | sparc_emit_set_const64_quick1 (op0, temp, low_bits, is_neg) | |
1424 | rtx op0; | |
1425 | rtx temp; | |
2a01c939 | 1426 | unsigned HOST_WIDE_INT low_bits; |
e0d80184 DM |
1427 | int is_neg; |
1428 | { | |
2a01c939 | 1429 | unsigned HOST_WIDE_INT high_bits; |
a9e27770 | 1430 | |
e0d80184 | 1431 | if (is_neg) |
2a01c939 | 1432 | high_bits = (~low_bits) & 0xffffffff; |
31bc9eba | 1433 | else |
e0d80184 | 1434 | high_bits = low_bits; |
31bc9eba | 1435 | |
9208e4b2 | 1436 | sparc_emit_set_safe_HIGH64 (temp, high_bits); |
e0d80184 | 1437 | if (!is_neg) |
5108f3e5 DM |
1438 | { |
1439 | emit_insn (gen_rtx_SET (VOIDmode, op0, | |
1440 | gen_safe_OR64 (temp, (high_bits & 0x3ff)))); | |
1441 | } | |
e0d80184 | 1442 | else |
5108f3e5 DM |
1443 | { |
1444 | /* If we are XOR'ing with -1, then we should emit a one's complement | |
1445 | instead. This way the combiner will notice logical operations | |
1446 | such as ANDN later on and substitute. */ | |
1447 | if ((low_bits & 0x3ff) == 0x3ff) | |
1448 | { | |
1449 | emit_insn (gen_rtx_SET (VOIDmode, op0, | |
1450 | gen_rtx_NOT (DImode, temp))); | |
1451 | } | |
1452 | else | |
1453 | { | |
1454 | emit_insn (gen_rtx_SET (VOIDmode, op0, | |
1455 | gen_safe_XOR64 (temp, | |
1456 | (-0x400 | (low_bits & 0x3ff))))); | |
1457 | } | |
1458 | } | |
e0d80184 | 1459 | } |
61a55e8b | 1460 | |
2a01c939 DM |
1461 | static void sparc_emit_set_const64_quick2 |
1462 | PROTO((rtx, rtx, unsigned HOST_WIDE_INT, | |
1463 | unsigned HOST_WIDE_INT, int)); | |
1464 | ||
e0d80184 DM |
1465 | static void |
1466 | sparc_emit_set_const64_quick2 (op0, temp, high_bits, low_immediate, shift_count) | |
1467 | rtx op0; | |
1468 | rtx temp; | |
2a01c939 DM |
1469 | unsigned HOST_WIDE_INT high_bits; |
1470 | unsigned HOST_WIDE_INT low_immediate; | |
e0d80184 DM |
1471 | int shift_count; |
1472 | { | |
1473 | rtx temp2 = op0; | |
61a55e8b | 1474 | |
e0d80184 DM |
1475 | if ((high_bits & 0xfffffc00) != 0) |
1476 | { | |
9208e4b2 | 1477 | sparc_emit_set_safe_HIGH64 (temp, high_bits); |
e0d80184 | 1478 | if ((high_bits & ~0xfffffc00) != 0) |
9208e4b2 DM |
1479 | emit_insn (gen_rtx_SET (VOIDmode, op0, |
1480 | gen_safe_OR64 (temp, (high_bits & 0x3ff)))); | |
61a55e8b | 1481 | else |
e0d80184 | 1482 | temp2 = temp; |
61a55e8b DE |
1483 | } |
1484 | else | |
1485 | { | |
f710f868 | 1486 | emit_insn (gen_safe_SET64 (temp, high_bits)); |
e0d80184 DM |
1487 | temp2 = temp; |
1488 | } | |
61a55e8b | 1489 | |
e0d80184 | 1490 | /* Now shift it up into place. */ |
9208e4b2 | 1491 | emit_insn (gen_rtx_SET (VOIDmode, op0, |
e0d80184 DM |
1492 | gen_rtx_ASHIFT (DImode, temp2, |
1493 | GEN_INT (shift_count)))); | |
61a55e8b | 1494 | |
e0d80184 DM |
1495 | /* If there is a low immediate part piece, finish up by |
1496 | putting that in as well. */ | |
1497 | if (low_immediate != 0) | |
9208e4b2 DM |
1498 | emit_insn (gen_rtx_SET (VOIDmode, op0, |
1499 | gen_safe_OR64 (op0, low_immediate))); | |
ab835497 RK |
1500 | } |
1501 | ||
2a01c939 DM |
1502 | static void sparc_emit_set_const64_longway |
1503 | PROTO((rtx, rtx, unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT)); | |
1504 | ||
e0d80184 DM |
1505 | /* Full 64-bit constant decomposition. Even though this is the |
1506 | 'worst' case, we still optimize a few things away. */ | |
1507 | static void | |
1508 | sparc_emit_set_const64_longway (op0, temp, high_bits, low_bits) | |
1509 | rtx op0; | |
1510 | rtx temp; | |
2a01c939 DM |
1511 | unsigned HOST_WIDE_INT high_bits; |
1512 | unsigned HOST_WIDE_INT low_bits; | |
ab835497 | 1513 | { |
e0d80184 | 1514 | rtx sub_temp; |
4bf7135b | 1515 | |
e0d80184 DM |
1516 | if (reload_in_progress || reload_completed) |
1517 | sub_temp = op0; | |
1518 | else | |
1519 | sub_temp = gen_reg_rtx (DImode); | |
1520 | ||
1521 | if ((high_bits & 0xfffffc00) != 0) | |
1522 | { | |
9208e4b2 | 1523 | sparc_emit_set_safe_HIGH64 (temp, high_bits); |
e0d80184 | 1524 | if ((high_bits & ~0xfffffc00) != 0) |
9208e4b2 | 1525 | emit_insn (gen_rtx_SET (VOIDmode, |
e0d80184 | 1526 | sub_temp, |
9208e4b2 | 1527 | gen_safe_OR64 (temp, (high_bits & 0x3ff)))); |
e0d80184 DM |
1528 | else |
1529 | sub_temp = temp; | |
1530 | } | |
1531 | else | |
ab835497 | 1532 | { |
f710f868 | 1533 | emit_insn (gen_safe_SET64 (temp, high_bits)); |
e0d80184 | 1534 | sub_temp = temp; |
ab835497 | 1535 | } |
4bf7135b | 1536 | |
e0d80184 | 1537 | if (!reload_in_progress && !reload_completed) |
284d86e9 | 1538 | { |
e0d80184 DM |
1539 | rtx temp2 = gen_reg_rtx (DImode); |
1540 | rtx temp3 = gen_reg_rtx (DImode); | |
1541 | rtx temp4 = gen_reg_rtx (DImode); | |
284d86e9 | 1542 | |
9208e4b2 | 1543 | emit_insn (gen_rtx_SET (VOIDmode, temp4, |
e0d80184 DM |
1544 | gen_rtx_ASHIFT (DImode, sub_temp, |
1545 | GEN_INT (32)))); | |
4bf7135b | 1546 | |
9208e4b2 | 1547 | sparc_emit_set_safe_HIGH64 (temp2, low_bits); |
e0d80184 | 1548 | if ((low_bits & ~0xfffffc00) != 0) |
f710f868 DM |
1549 | { |
1550 | emit_insn (gen_rtx_SET (VOIDmode, temp3, | |
1551 | gen_safe_OR64 (temp2, (low_bits & 0x3ff)))); | |
1552 | emit_insn (gen_rtx_SET (VOIDmode, op0, | |
1553 | gen_rtx_PLUS (DImode, temp4, temp3))); | |
1554 | } | |
1555 | else | |
1556 | { | |
1557 | emit_insn (gen_rtx_SET (VOIDmode, op0, | |
1558 | gen_rtx_PLUS (DImode, temp4, temp2))); | |
1559 | } | |
284d86e9 | 1560 | } |
e0d80184 DM |
1561 | else |
1562 | { | |
9208e4b2 DM |
1563 | rtx low1 = GEN_INT ((low_bits >> (32 - 12)) & 0xfff); |
1564 | rtx low2 = GEN_INT ((low_bits >> (32 - 12 - 12)) & 0xfff); | |
1565 | rtx low3 = GEN_INT ((low_bits >> (32 - 12 - 12 - 8)) & 0x0ff); | |
e0d80184 | 1566 | int to_shift = 12; |
284d86e9 | 1567 | |
e0d80184 DM |
1568 | /* We are in the middle of reload, so this is really |
1569 | painful. However we do still make an attempt to | |
5108f3e5 | 1570 | avoid emitting truly stupid code. */ |
e0d80184 DM |
1571 | if (low1 != const0_rtx) |
1572 | { | |
9208e4b2 | 1573 | emit_insn (gen_rtx_SET (VOIDmode, op0, |
e0d80184 | 1574 | gen_rtx_ASHIFT (DImode, sub_temp, |
2a01c939 | 1575 | GEN_INT (to_shift)))); |
9208e4b2 | 1576 | emit_insn (gen_rtx_SET (VOIDmode, op0, |
e0d80184 DM |
1577 | gen_rtx_IOR (DImode, op0, low1))); |
1578 | sub_temp = op0; | |
1579 | to_shift = 12; | |
1580 | } | |
1581 | else | |
1582 | { | |
1583 | to_shift += 12; | |
1584 | } | |
1585 | if (low2 != const0_rtx) | |
1586 | { | |
9208e4b2 | 1587 | emit_insn (gen_rtx_SET (VOIDmode, op0, |
e0d80184 DM |
1588 | gen_rtx_ASHIFT (DImode, sub_temp, |
1589 | GEN_INT (to_shift)))); | |
9208e4b2 | 1590 | emit_insn (gen_rtx_SET (VOIDmode, op0, |
e0d80184 DM |
1591 | gen_rtx_IOR (DImode, op0, low2))); |
1592 | sub_temp = op0; | |
1593 | to_shift = 8; | |
1594 | } | |
1595 | else | |
1596 | { | |
1597 | to_shift += 8; | |
1598 | } | |
9208e4b2 | 1599 | emit_insn (gen_rtx_SET (VOIDmode, op0, |
e0d80184 DM |
1600 | gen_rtx_ASHIFT (DImode, sub_temp, |
1601 | GEN_INT (to_shift)))); | |
1602 | if (low3 != const0_rtx) | |
9208e4b2 | 1603 | emit_insn (gen_rtx_SET (VOIDmode, op0, |
e0d80184 DM |
1604 | gen_rtx_IOR (DImode, op0, low3))); |
1605 | /* phew... */ | |
1606 | } | |
284d86e9 JC |
1607 | } |
1608 | ||
e0d80184 | 1609 | /* Analyze a 64-bit constant for certain properties. */ |
2a01c939 DM |
1610 | static void analyze_64bit_constant |
1611 | PROTO((unsigned HOST_WIDE_INT, | |
1612 | unsigned HOST_WIDE_INT, | |
1613 | int *, int *, int *)); | |
1614 | ||
e0d80184 DM |
1615 | static void |
1616 | analyze_64bit_constant (high_bits, low_bits, hbsp, lbsp, abbasp) | |
2a01c939 | 1617 | unsigned HOST_WIDE_INT high_bits, low_bits; |
e0d80184 | 1618 | int *hbsp, *lbsp, *abbasp; |
ab835497 | 1619 | { |
e0d80184 DM |
1620 | int lowest_bit_set, highest_bit_set, all_bits_between_are_set; |
1621 | int i; | |
ab835497 | 1622 | |
e0d80184 DM |
1623 | lowest_bit_set = highest_bit_set = -1; |
1624 | i = 0; | |
1625 | do | |
ab835497 | 1626 | { |
e0d80184 DM |
1627 | if ((lowest_bit_set == -1) |
1628 | && ((low_bits >> i) & 1)) | |
1629 | lowest_bit_set = i; | |
1630 | if ((highest_bit_set == -1) | |
1631 | && ((high_bits >> (32 - i - 1)) & 1)) | |
1632 | highest_bit_set = (64 - i - 1); | |
1633 | } | |
1634 | while (++i < 32 | |
1635 | && ((highest_bit_set == -1) | |
1636 | || (lowest_bit_set == -1))); | |
1637 | if (i == 32) | |
1638 | { | |
1639 | i = 0; | |
1640 | do | |
ab835497 | 1641 | { |
e0d80184 DM |
1642 | if ((lowest_bit_set == -1) |
1643 | && ((high_bits >> i) & 1)) | |
1644 | lowest_bit_set = i + 32; | |
1645 | if ((highest_bit_set == -1) | |
1646 | && ((low_bits >> (32 - i - 1)) & 1)) | |
1647 | highest_bit_set = 32 - i - 1; | |
ab835497 | 1648 | } |
e0d80184 DM |
1649 | while (++i < 32 |
1650 | && ((highest_bit_set == -1) | |
1651 | || (lowest_bit_set == -1))); | |
1652 | } | |
1653 | /* If there are no bits set this should have gone out | |
1654 | as one instruction! */ | |
1655 | if (lowest_bit_set == -1 | |
1656 | || highest_bit_set == -1) | |
9208e4b2 | 1657 | abort (); |
e0d80184 DM |
1658 | all_bits_between_are_set = 1; |
1659 | for (i = lowest_bit_set; i <= highest_bit_set; i++) | |
1660 | { | |
1661 | if (i < 32) | |
1662 | { | |
1663 | if ((low_bits & (1 << i)) != 0) | |
1664 | continue; | |
1665 | } | |
1666 | else | |
1667 | { | |
1668 | if ((high_bits & (1 << (i - 32))) != 0) | |
1669 | continue; | |
1670 | } | |
1671 | all_bits_between_are_set = 0; | |
1672 | break; | |
ab835497 | 1673 | } |
e0d80184 DM |
1674 | *hbsp = highest_bit_set; |
1675 | *lbsp = lowest_bit_set; | |
1676 | *abbasp = all_bits_between_are_set; | |
ab835497 | 1677 | } |
6a4bb1fa | 1678 | |
2a01c939 DM |
1679 | static int const64_is_2insns |
1680 | PROTO((unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT)); | |
1681 | ||
e0d80184 DM |
1682 | static int |
1683 | const64_is_2insns (high_bits, low_bits) | |
2a01c939 | 1684 | unsigned HOST_WIDE_INT high_bits, low_bits; |
e0d80184 DM |
1685 | { |
1686 | int highest_bit_set, lowest_bit_set, all_bits_between_are_set; | |
284d86e9 | 1687 | |
e0d80184 | 1688 | if (high_bits == 0 |
2a01c939 | 1689 | || high_bits == 0xffffffff) |
e0d80184 | 1690 | return 1; |
6a4bb1fa | 1691 | |
e0d80184 DM |
1692 | analyze_64bit_constant (high_bits, low_bits, |
1693 | &highest_bit_set, &lowest_bit_set, | |
1694 | &all_bits_between_are_set); | |
6a4bb1fa | 1695 | |
f710f868 DM |
1696 | if ((highest_bit_set == 63 |
1697 | || lowest_bit_set == 0) | |
e0d80184 DM |
1698 | && all_bits_between_are_set != 0) |
1699 | return 1; | |
6a4bb1fa | 1700 | |
9208e4b2 DM |
1701 | if ((highest_bit_set - lowest_bit_set) < 21) |
1702 | return 1; | |
1703 | ||
6a4bb1fa DE |
1704 | return 0; |
1705 | } | |
1706 | ||
2a01c939 DM |
1707 | static unsigned HOST_WIDE_INT create_simple_focus_bits |
1708 | PROTO((unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT, | |
ddf80874 | 1709 | int, int)); |
2a01c939 DM |
1710 | |
1711 | static unsigned HOST_WIDE_INT | |
ddf80874 | 1712 | create_simple_focus_bits (high_bits, low_bits, lowest_bit_set, shift) |
2a01c939 | 1713 | unsigned HOST_WIDE_INT high_bits, low_bits; |
ddf80874 | 1714 | int lowest_bit_set, shift; |
ab835497 | 1715 | { |
f710f868 | 1716 | HOST_WIDE_INT hi, lo; |
ab835497 | 1717 | |
e0d80184 DM |
1718 | if (lowest_bit_set < 32) |
1719 | { | |
1720 | lo = (low_bits >> lowest_bit_set) << shift; | |
1721 | hi = ((high_bits << (32 - lowest_bit_set)) << shift); | |
1722 | } | |
1723 | else | |
1724 | { | |
1725 | lo = 0; | |
1726 | hi = ((high_bits >> (lowest_bit_set - 32)) << shift); | |
1727 | } | |
1728 | if (hi & lo) | |
9208e4b2 | 1729 | abort (); |
e0d80184 DM |
1730 | return (hi | lo); |
1731 | } | |
ab835497 | 1732 | |
e0d80184 DM |
1733 | /* Here we are sure to be arch64 and this is an integer constant |
1734 | being loaded into a register. Emit the most efficient | |
1735 | insn sequence possible. Detection of all the 1-insn cases | |
1736 | has been done already. */ | |
1737 | void | |
1738 | sparc_emit_set_const64 (op0, op1) | |
1739 | rtx op0; | |
1740 | rtx op1; | |
1741 | { | |
2a01c939 | 1742 | unsigned HOST_WIDE_INT high_bits, low_bits; |
e0d80184 DM |
1743 | int lowest_bit_set, highest_bit_set; |
1744 | int all_bits_between_are_set; | |
e0d80184 | 1745 | rtx temp; |
ab835497 | 1746 | |
e0d80184 DM |
1747 | /* Sanity check that we know what we are working with. */ |
1748 | if (! TARGET_ARCH64 | |
1749 | || GET_CODE (op0) != REG | |
1750 | || (REGNO (op0) >= SPARC_FIRST_FP_REG | |
1751 | && REGNO (op0) <= SPARC_LAST_V9_FP_REG)) | |
9208e4b2 | 1752 | abort (); |
95726648 | 1753 | |
f710f868 DM |
1754 | if (reload_in_progress || reload_completed) |
1755 | temp = op0; | |
1756 | else | |
1757 | temp = gen_reg_rtx (DImode); | |
1758 | ||
e0d80184 DM |
1759 | if (GET_CODE (op1) != CONST_DOUBLE |
1760 | && GET_CODE (op1) != CONST_INT) | |
1761 | { | |
5f78aa30 JC |
1762 | sparc_emit_set_symbolic_const64 (op0, op1, temp); |
1763 | return; | |
e0d80184 | 1764 | } |
ab835497 | 1765 | |
e0d80184 DM |
1766 | if (GET_CODE (op1) == CONST_DOUBLE) |
1767 | { | |
1768 | #if HOST_BITS_PER_WIDE_INT == 64 | |
2a01c939 | 1769 | high_bits = (CONST_DOUBLE_LOW (op1) >> 32) & 0xffffffff; |
e0d80184 DM |
1770 | low_bits = CONST_DOUBLE_LOW (op1) & 0xffffffff; |
1771 | #else | |
1772 | high_bits = CONST_DOUBLE_HIGH (op1); | |
1773 | low_bits = CONST_DOUBLE_LOW (op1); | |
1774 | #endif | |
ab835497 | 1775 | } |
e0d80184 | 1776 | else |
ab835497 | 1777 | { |
e0d80184 | 1778 | #if HOST_BITS_PER_WIDE_INT == 64 |
2a01c939 | 1779 | high_bits = ((INTVAL (op1) >> 32) & 0xffffffff); |
e0d80184 DM |
1780 | low_bits = (INTVAL (op1) & 0xffffffff); |
1781 | #else | |
1782 | high_bits = ((INTVAL (op1) < 0) ? | |
1783 | 0xffffffff : | |
1784 | 0x00000000); | |
1785 | low_bits = INTVAL (op1); | |
1786 | #endif | |
1787 | } | |
ab835497 | 1788 | |
e0d80184 DM |
1789 | /* low_bits bits 0 --> 31 |
1790 | high_bits bits 32 --> 63 */ | |
ab835497 | 1791 | |
e0d80184 DM |
1792 | analyze_64bit_constant (high_bits, low_bits, |
1793 | &highest_bit_set, &lowest_bit_set, | |
1794 | &all_bits_between_are_set); | |
1795 | ||
1796 | /* First try for a 2-insn sequence. */ | |
1797 | ||
1798 | /* These situations are preferred because the optimizer can | |
1799 | * do more things with them: | |
1800 | * 1) mov -1, %reg | |
1801 | * sllx %reg, shift, %reg | |
1802 | * 2) mov -1, %reg | |
1803 | * srlx %reg, shift, %reg | |
1804 | * 3) mov some_small_const, %reg | |
1805 | * sllx %reg, shift, %reg | |
1806 | */ | |
1807 | if (((highest_bit_set == 63 | |
1808 | || lowest_bit_set == 0) | |
1809 | && all_bits_between_are_set != 0) | |
2a01c939 | 1810 | || ((highest_bit_set - lowest_bit_set) < 12)) |
e0d80184 | 1811 | { |
9208e4b2 | 1812 | HOST_WIDE_INT the_const = -1; |
e0d80184 DM |
1813 | int shift = lowest_bit_set; |
1814 | ||
f710f868 DM |
1815 | if ((highest_bit_set != 63 |
1816 | && lowest_bit_set != 0) | |
1817 | || all_bits_between_are_set == 0) | |
ab835497 | 1818 | { |
e0d80184 | 1819 | the_const = |
9208e4b2 | 1820 | create_simple_focus_bits (high_bits, low_bits, |
9208e4b2 | 1821 | lowest_bit_set, 0); |
ab835497 | 1822 | } |
e0d80184 | 1823 | else if (lowest_bit_set == 0) |
9208e4b2 | 1824 | shift = -(63 - highest_bit_set); |
e0d80184 | 1825 | |
f710f868 DM |
1826 | if (! SPARC_SIMM13_P (the_const)) |
1827 | abort (); | |
1828 | ||
9208e4b2 | 1829 | emit_insn (gen_safe_SET64 (temp, the_const)); |
e0d80184 | 1830 | if (shift > 0) |
9208e4b2 | 1831 | emit_insn (gen_rtx_SET (VOIDmode, |
e0d80184 DM |
1832 | op0, |
1833 | gen_rtx_ASHIFT (DImode, | |
1834 | temp, | |
1835 | GEN_INT (shift)))); | |
1836 | else if (shift < 0) | |
9208e4b2 | 1837 | emit_insn (gen_rtx_SET (VOIDmode, |
e0d80184 | 1838 | op0, |
9208e4b2 | 1839 | gen_rtx_LSHIFTRT (DImode, |
e0d80184 DM |
1840 | temp, |
1841 | GEN_INT (-shift)))); | |
ab835497 RK |
1842 | else |
1843 | abort (); | |
e0d80184 DM |
1844 | return; |
1845 | } | |
ab835497 | 1846 | |
e0d80184 DM |
1847 | /* Now a range of 22 or less bits set somewhere. |
1848 | * 1) sethi %hi(focus_bits), %reg | |
1849 | * sllx %reg, shift, %reg | |
1850 | * 2) sethi %hi(focus_bits), %reg | |
1851 | * srlx %reg, shift, %reg | |
1852 | */ | |
2a01c939 | 1853 | if ((highest_bit_set - lowest_bit_set) < 21) |
e0d80184 | 1854 | { |
2a01c939 | 1855 | unsigned HOST_WIDE_INT focus_bits = |
e0d80184 | 1856 | create_simple_focus_bits (high_bits, low_bits, |
ddf80874 | 1857 | lowest_bit_set, 10); |
f710f868 DM |
1858 | |
1859 | if (! SPARC_SETHI_P (focus_bits)) | |
1860 | abort (); | |
1861 | ||
9208e4b2 | 1862 | sparc_emit_set_safe_HIGH64 (temp, focus_bits); |
e0d80184 | 1863 | |
9208e4b2 | 1864 | /* If lowest_bit_set == 10 then a sethi alone could have done it. */ |
e0d80184 | 1865 | if (lowest_bit_set < 10) |
9208e4b2 | 1866 | emit_insn (gen_rtx_SET (VOIDmode, |
e0d80184 | 1867 | op0, |
9208e4b2 | 1868 | gen_rtx_LSHIFTRT (DImode, temp, |
e0d80184 | 1869 | GEN_INT (10 - lowest_bit_set)))); |
9208e4b2 DM |
1870 | else if (lowest_bit_set > 10) |
1871 | emit_insn (gen_rtx_SET (VOIDmode, | |
e0d80184 DM |
1872 | op0, |
1873 | gen_rtx_ASHIFT (DImode, temp, | |
1874 | GEN_INT (lowest_bit_set - 10)))); | |
1875 | else | |
9208e4b2 | 1876 | abort (); |
e0d80184 DM |
1877 | return; |
1878 | } | |
1879 | ||
1880 | /* 1) sethi %hi(low_bits), %reg | |
1881 | * or %reg, %lo(low_bits), %reg | |
1882 | * 2) sethi %hi(~low_bits), %reg | |
1883 | * xor %reg, %lo(-0x400 | (low_bits & 0x3ff)), %reg | |
1884 | */ | |
1885 | if (high_bits == 0 | |
2a01c939 | 1886 | || high_bits == 0xffffffff) |
5f78aa30 JC |
1887 | { |
1888 | sparc_emit_set_const64_quick1 (op0, temp, low_bits, | |
1889 | (high_bits == 0xffffffff)); | |
1890 | return; | |
1891 | } | |
e0d80184 | 1892 | |
f710f868 DM |
1893 | /* Now, try 3-insn sequences. */ |
1894 | ||
e0d80184 DM |
1895 | /* 1) sethi %hi(high_bits), %reg |
1896 | * or %reg, %lo(high_bits), %reg | |
1897 | * sllx %reg, 32, %reg | |
1898 | */ | |
f710f868 | 1899 | if (low_bits == 0) |
5f78aa30 | 1900 | { |
f710f868 | 1901 | sparc_emit_set_const64_quick2 (op0, temp, high_bits, 0, 32); |
5f78aa30 JC |
1902 | return; |
1903 | } | |
e0d80184 | 1904 | |
f710f868 DM |
1905 | /* We may be able to do something quick |
1906 | when the constant is negated, so try that. */ | |
e0d80184 DM |
1907 | if (const64_is_2insns ((~high_bits) & 0xffffffff, |
1908 | (~low_bits) & 0xfffffc00)) | |
1909 | { | |
5108f3e5 DM |
1910 | /* NOTE: The trailing bits get XOR'd so we need the |
1911 | non-negated bits, not the negated ones. */ | |
1912 | unsigned HOST_WIDE_INT trailing_bits = low_bits & 0x3ff; | |
e0d80184 DM |
1913 | |
1914 | if ((((~high_bits) & 0xffffffff) == 0 | |
1915 | && ((~low_bits) & 0x80000000) == 0) | |
1916 | || (((~high_bits) & 0xffffffff) == 0xffffffff | |
1917 | && ((~low_bits) & 0x80000000) != 0)) | |
ab835497 | 1918 | { |
5108f3e5 | 1919 | int fast_int = (~low_bits & 0xffffffff); |
e0d80184 | 1920 | |
5108f3e5 DM |
1921 | if ((SPARC_SETHI_P (fast_int) |
1922 | && (~high_bits & 0xffffffff) == 0) | |
1923 | || SPARC_SIMM13_P (fast_int)) | |
9208e4b2 | 1924 | emit_insn (gen_safe_SET64 (temp, fast_int)); |
ab835497 | 1925 | else |
9208e4b2 | 1926 | sparc_emit_set_const64 (temp, GEN_INT64 (fast_int)); |
ab835497 | 1927 | } |
e0d80184 DM |
1928 | else |
1929 | { | |
1930 | rtx negated_const; | |
1931 | #if HOST_BITS_PER_WIDE_INT == 64 | |
1932 | negated_const = GEN_INT (((~low_bits) & 0xfffffc00) | | |
1933 | (((HOST_WIDE_INT)((~high_bits) & 0xffffffff))<<32)); | |
1934 | #else | |
9208e4b2 | 1935 | negated_const = gen_rtx_CONST_DOUBLE (DImode, const0_rtx, |
e0d80184 DM |
1936 | (~low_bits) & 0xfffffc00, |
1937 | (~high_bits) & 0xffffffff); | |
1938 | #endif | |
1939 | sparc_emit_set_const64 (temp, negated_const); | |
1940 | } | |
5108f3e5 DM |
1941 | |
1942 | /* If we are XOR'ing with -1, then we should emit a one's complement | |
1943 | instead. This way the combiner will notice logical operations | |
1944 | such as ANDN later on and substitute. */ | |
1945 | if (trailing_bits == 0x3ff) | |
1946 | { | |
1947 | emit_insn (gen_rtx_SET (VOIDmode, op0, | |
1948 | gen_rtx_NOT (DImode, temp))); | |
1949 | } | |
1950 | else | |
1951 | { | |
1952 | emit_insn (gen_rtx_SET (VOIDmode, | |
1953 | op0, | |
1954 | gen_safe_XOR64 (temp, | |
1955 | (-0x400 | trailing_bits)))); | |
1956 | } | |
e0d80184 | 1957 | return; |
ab835497 | 1958 | } |
ab835497 | 1959 | |
e0d80184 DM |
1960 | /* 1) sethi %hi(xxx), %reg |
1961 | * or %reg, %lo(xxx), %reg | |
1962 | * sllx %reg, yyy, %reg | |
f710f868 DM |
1963 | * |
1964 | * ??? This is just a generalized version of the low_bits==0 | |
1965 | * thing above, FIXME... | |
e0d80184 DM |
1966 | */ |
1967 | if ((highest_bit_set - lowest_bit_set) < 32) | |
1968 | { | |
f710f868 DM |
1969 | unsigned HOST_WIDE_INT focus_bits = |
1970 | create_simple_focus_bits (high_bits, low_bits, | |
ddf80874 | 1971 | lowest_bit_set, 0); |
ab835497 | 1972 | |
e0d80184 DM |
1973 | /* We can't get here in this state. */ |
1974 | if (highest_bit_set < 32 | |
1975 | || lowest_bit_set >= 32) | |
9208e4b2 | 1976 | abort (); |
95726648 | 1977 | |
e0d80184 DM |
1978 | /* So what we know is that the set bits straddle the |
1979 | middle of the 64-bit word. */ | |
5f78aa30 JC |
1980 | sparc_emit_set_const64_quick2 (op0, temp, |
1981 | focus_bits, 0, | |
1982 | lowest_bit_set); | |
1983 | return; | |
e0d80184 | 1984 | } |
c85f7c16 | 1985 | |
f710f868 DM |
1986 | /* 1) sethi %hi(high_bits), %reg |
1987 | * or %reg, %lo(high_bits), %reg | |
1988 | * sllx %reg, 32, %reg | |
1989 | * or %reg, low_bits, %reg | |
1990 | */ | |
1991 | if (SPARC_SIMM13_P(low_bits) | |
1992 | && ((int)low_bits > 0)) | |
1993 | { | |
1994 | sparc_emit_set_const64_quick2 (op0, temp, high_bits, low_bits, 32); | |
1995 | return; | |
1996 | } | |
1997 | ||
e0d80184 DM |
1998 | /* The easiest way when all else fails, is full decomposition. */ |
1999 | #if 0 | |
2000 | printf ("sparc_emit_set_const64: Hard constant [%08lx%08lx] neg[%08lx%08lx]\n", | |
2001 | high_bits, low_bits, ~high_bits, ~low_bits); | |
2002 | #endif | |
2003 | sparc_emit_set_const64_longway (op0, temp, high_bits, low_bits); | |
c85f7c16 JL |
2004 | } |
2005 | ||
e0d80184 DM |
2006 | /* X and Y are two things to compare using CODE. Emit the compare insn and |
2007 | return the rtx for the cc reg in the proper mode. */ | |
c85f7c16 | 2008 | |
e0d80184 DM |
2009 | rtx |
2010 | gen_compare_reg (code, x, y) | |
2011 | enum rtx_code code; | |
2012 | rtx x, y; | |
c85f7c16 | 2013 | { |
e0d80184 DM |
2014 | enum machine_mode mode = SELECT_CC_MODE (code, x, y); |
2015 | rtx cc_reg; | |
c85f7c16 | 2016 | |
e0d80184 DM |
2017 | /* ??? We don't have movcc patterns so we cannot generate pseudo regs for the |
2018 | fcc regs (cse can't tell they're really call clobbered regs and will | |
2019 | remove a duplicate comparison even if there is an intervening function | |
2020 | call - it will then try to reload the cc reg via an int reg which is why | |
2021 | we need the movcc patterns). It is possible to provide the movcc | |
2022 | patterns by using the ldxfsr/stxfsr v9 insns. I tried it: you need two | |
2023 | registers (say %g1,%g5) and it takes about 6 insns. A better fix would be | |
2024 | to tell cse that CCFPE mode registers (even pseudos) are call | |
2025 | clobbered. */ | |
c85f7c16 | 2026 | |
e0d80184 DM |
2027 | /* ??? This is an experiment. Rather than making changes to cse which may |
2028 | or may not be easy/clean, we do our own cse. This is possible because | |
2029 | we will generate hard registers. Cse knows they're call clobbered (it | |
2030 | doesn't know the same thing about pseudos). If we guess wrong, no big | |
2031 | deal, but if we win, great! */ | |
c85f7c16 | 2032 | |
e0d80184 DM |
2033 | if (TARGET_V9 && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) |
2034 | #if 1 /* experiment */ | |
284d86e9 | 2035 | { |
e0d80184 DM |
2036 | int reg; |
2037 | /* We cycle through the registers to ensure they're all exercised. */ | |
2038 | static int next_fcc_reg = 0; | |
2039 | /* Previous x,y for each fcc reg. */ | |
2040 | static rtx prev_args[4][2]; | |
284d86e9 | 2041 | |
e0d80184 DM |
2042 | /* Scan prev_args for x,y. */ |
2043 | for (reg = 0; reg < 4; reg++) | |
2044 | if (prev_args[reg][0] == x && prev_args[reg][1] == y) | |
2045 | break; | |
2046 | if (reg == 4) | |
2047 | { | |
2048 | reg = next_fcc_reg; | |
2049 | prev_args[reg][0] = x; | |
2050 | prev_args[reg][1] = y; | |
2051 | next_fcc_reg = (next_fcc_reg + 1) & 3; | |
2052 | } | |
2053 | cc_reg = gen_rtx_REG (mode, reg + SPARC_FIRST_V9_FCC_REG); | |
284d86e9 | 2054 | } |
e0d80184 DM |
2055 | #else |
2056 | cc_reg = gen_reg_rtx (mode); | |
2057 | #endif /* ! experiment */ | |
2058 | else if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) | |
2059 | cc_reg = gen_rtx_REG (mode, SPARC_FCC_REG); | |
2060 | else | |
2061 | cc_reg = gen_rtx_REG (mode, SPARC_ICC_REG); | |
284d86e9 | 2062 | |
e0d80184 DM |
2063 | emit_insn (gen_rtx_SET (VOIDmode, cc_reg, |
2064 | gen_rtx_COMPARE (mode, x, y))); | |
c85f7c16 | 2065 | |
e0d80184 DM |
2066 | return cc_reg; |
2067 | } | |
c85f7c16 | 2068 | |
e0d80184 DM |
2069 | /* This function is used for v9 only. |
2070 | CODE is the code for an Scc's comparison. | |
2071 | OPERANDS[0] is the target of the Scc insn. | |
2072 | OPERANDS[1] is the value we compare against const0_rtx (which hasn't | |
2073 | been generated yet). | |
c85f7c16 | 2074 | |
e0d80184 | 2075 | This function is needed to turn |
ab835497 | 2076 | |
e0d80184 DM |
2077 | (set (reg:SI 110) |
2078 | (gt (reg:CCX 100 %icc) | |
2079 | (const_int 0))) | |
2080 | into | |
2081 | (set (reg:SI 110) | |
2082 | (gt:DI (reg:CCX 100 %icc) | |
2083 | (const_int 0))) | |
2084 | ||
2085 | IE: The instruction recognizer needs to see the mode of the comparison to | |
2086 | find the right instruction. We could use "gt:DI" right in the | |
2087 | define_expand, but leaving it out allows us to handle DI, SI, etc. | |
ab835497 | 2088 | |
e0d80184 DM |
2089 | We refer to the global sparc compare operands sparc_compare_op0 and |
2090 | sparc_compare_op1. */ | |
ab835497 RK |
2091 | |
2092 | int | |
e0d80184 DM |
2093 | gen_v9_scc (compare_code, operands) |
2094 | enum rtx_code compare_code; | |
2095 | register rtx *operands; | |
ab835497 | 2096 | { |
e0d80184 | 2097 | rtx temp, op0, op1; |
ab835497 | 2098 | |
e0d80184 DM |
2099 | if (! TARGET_ARCH64 |
2100 | && (GET_MODE (sparc_compare_op0) == DImode | |
2101 | || GET_MODE (operands[0]) == DImode)) | |
2102 | return 0; | |
7e2feebf | 2103 | |
e0d80184 DM |
2104 | /* Handle the case where operands[0] == sparc_compare_op0. |
2105 | We "early clobber" the result. */ | |
2106 | if (REGNO (operands[0]) == REGNO (sparc_compare_op0)) | |
ab835497 | 2107 | { |
e0d80184 DM |
2108 | op0 = gen_reg_rtx (GET_MODE (sparc_compare_op0)); |
2109 | emit_move_insn (op0, sparc_compare_op0); | |
ab835497 | 2110 | } |
e0d80184 DM |
2111 | else |
2112 | op0 = sparc_compare_op0; | |
2113 | /* For consistency in the following. */ | |
2114 | op1 = sparc_compare_op1; | |
2115 | ||
2116 | /* Try to use the movrCC insns. */ | |
2117 | if (TARGET_ARCH64 | |
2118 | && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT | |
2119 | && op1 == const0_rtx | |
2120 | && v9_regcmp_p (compare_code)) | |
ab835497 | 2121 | { |
e0d80184 DM |
2122 | /* Special case for op0 != 0. This can be done with one instruction if |
2123 | operands[0] == sparc_compare_op0. We don't assume they are equal | |
2124 | now though. */ | |
2125 | ||
2126 | if (compare_code == NE | |
2127 | && GET_MODE (operands[0]) == DImode | |
2128 | && GET_MODE (op0) == DImode) | |
ab835497 | 2129 | { |
e0d80184 DM |
2130 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], op0)); |
2131 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], | |
2132 | gen_rtx_IF_THEN_ELSE (DImode, | |
2133 | gen_rtx_fmt_ee (compare_code, DImode, | |
2134 | op0, const0_rtx), | |
2135 | const1_rtx, | |
2136 | operands[0]))); | |
ab835497 RK |
2137 | return 1; |
2138 | } | |
e0d80184 DM |
2139 | |
2140 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], const0_rtx)); | |
2141 | if (GET_MODE (op0) != DImode) | |
ab835497 | 2142 | { |
e0d80184 DM |
2143 | temp = gen_reg_rtx (DImode); |
2144 | convert_move (temp, op0, 0); | |
ab835497 | 2145 | } |
e0d80184 DM |
2146 | else |
2147 | temp = op0; | |
2148 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], | |
2149 | gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]), | |
2150 | gen_rtx_fmt_ee (compare_code, DImode, | |
2151 | temp, const0_rtx), | |
2152 | const1_rtx, | |
2153 | operands[0]))); | |
95726648 DE |
2154 | return 1; |
2155 | } | |
e0d80184 | 2156 | else |
ab835497 | 2157 | { |
e0d80184 | 2158 | operands[1] = gen_compare_reg (compare_code, op0, op1); |
ab835497 | 2159 | |
e0d80184 | 2160 | switch (GET_MODE (operands[1])) |
ab835497 | 2161 | { |
e0d80184 DM |
2162 | case CCmode : |
2163 | case CCXmode : | |
2164 | case CCFPEmode : | |
2165 | case CCFPmode : | |
2166 | break; | |
2167 | default : | |
2168 | abort (); | |
ab835497 | 2169 | } |
e0d80184 DM |
2170 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], const0_rtx)); |
2171 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], | |
2172 | gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]), | |
2173 | gen_rtx_fmt_ee (compare_code, | |
2174 | GET_MODE (operands[1]), | |
2175 | operands[1], const0_rtx), | |
2176 | const1_rtx, operands[0]))); | |
2177 | return 1; | |
ab835497 | 2178 | } |
ab835497 | 2179 | } |
4fb4e4b8 | 2180 | |
e0d80184 DM |
2181 | /* Emit a conditional jump insn for the v9 architecture using comparison code |
2182 | CODE and jump target LABEL. | |
2183 | This function exists to take advantage of the v9 brxx insns. */ | |
ab835497 | 2184 | |
e0d80184 DM |
2185 | void |
2186 | emit_v9_brxx_insn (code, op0, label) | |
2187 | enum rtx_code code; | |
2188 | rtx op0, label; | |
ab835497 | 2189 | { |
e0d80184 DM |
2190 | emit_jump_insn (gen_rtx_SET (VOIDmode, |
2191 | pc_rtx, | |
2192 | gen_rtx_IF_THEN_ELSE (VOIDmode, | |
2193 | gen_rtx_fmt_ee (code, GET_MODE (op0), | |
2194 | op0, const0_rtx), | |
2195 | gen_rtx_LABEL_REF (VOIDmode, label), | |
2196 | pc_rtx))); | |
2197 | } | |
2198 | \f | |
2199 | /* Return nonzero if a return peephole merging return with | |
2200 | setting of output register is ok. */ | |
2201 | int | |
2202 | leaf_return_peephole_ok () | |
2203 | { | |
2204 | return (actual_fsize == 0); | |
2205 | } | |
284d86e9 | 2206 | |
e0d80184 DM |
2207 | /* Return nonzero if TRIAL can go into the function epilogue's |
2208 | delay slot. SLOT is the slot we are trying to fill. */ | |
ab835497 | 2209 | |
e0d80184 DM |
2210 | int |
2211 | eligible_for_epilogue_delay (trial, slot) | |
2212 | rtx trial; | |
2213 | int slot; | |
2214 | { | |
2215 | rtx pat, src; | |
4fb4e4b8 | 2216 | |
e0d80184 DM |
2217 | if (slot >= 1) |
2218 | return 0; | |
4fb4e4b8 | 2219 | |
e0d80184 DM |
2220 | if (GET_CODE (trial) != INSN || GET_CODE (PATTERN (trial)) != SET) |
2221 | return 0; | |
4fb4e4b8 | 2222 | |
e0d80184 DM |
2223 | if (get_attr_length (trial) != 1) |
2224 | return 0; | |
4fb4e4b8 | 2225 | |
e0d80184 DM |
2226 | /* If %g0 is live, there are lots of things we can't handle. |
2227 | Rather than trying to find them all now, let's punt and only | |
2228 | optimize things as necessary. */ | |
2229 | if (TARGET_LIVE_G0) | |
2230 | return 0; | |
4fb4e4b8 | 2231 | |
e0d80184 DM |
2232 | /* In the case of a true leaf function, anything can go into the delay slot. |
2233 | A delay slot only exists however if the frame size is zero, otherwise | |
2234 | we will put an insn to adjust the stack after the return. */ | |
2235 | if (leaf_function) | |
4fb4e4b8 | 2236 | { |
e0d80184 DM |
2237 | if (leaf_return_peephole_ok ()) |
2238 | return ((get_attr_in_uncond_branch_delay (trial) | |
2239 | == IN_BRANCH_DELAY_TRUE)); | |
2240 | return 0; | |
4fb4e4b8 | 2241 | } |
4fb4e4b8 | 2242 | |
e0d80184 DM |
2243 | /* If only trivial `restore' insns work, nothing can go in the |
2244 | delay slot. */ | |
2245 | else if (TARGET_BROKEN_SAVERESTORE) | |
2246 | return 0; | |
795068a4 | 2247 | |
e0d80184 | 2248 | pat = PATTERN (trial); |
795068a4 | 2249 | |
e0d80184 DM |
2250 | /* Otherwise, only operations which can be done in tandem with |
2251 | a `restore' insn can go into the delay slot. */ | |
2252 | if (GET_CODE (SET_DEST (pat)) != REG | |
2253 | || REGNO (SET_DEST (pat)) >= 32 | |
2254 | || REGNO (SET_DEST (pat)) < 24) | |
2255 | return 0; | |
795068a4 | 2256 | |
e0d80184 DM |
2257 | /* The set of insns matched here must agree precisely with the set of |
2258 | patterns paired with a RETURN in sparc.md. */ | |
795068a4 | 2259 | |
e0d80184 | 2260 | src = SET_SRC (pat); |
795068a4 | 2261 | |
3c6088d2 | 2262 | /* This matches "*return_[qhs]i" or even "*return_di" on TARGET_ARCH64. */ |
e0d80184 | 2263 | if (arith_operand (src, GET_MODE (src))) |
3c6088d2 JJ |
2264 | { |
2265 | if (TARGET_ARCH64) | |
2266 | return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode); | |
2267 | else | |
2268 | return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (SImode); | |
2269 | } | |
e0d80184 DM |
2270 | |
2271 | /* This matches "*return_di". */ | |
2272 | else if (arith_double_operand (src, GET_MODE (src))) | |
2273 | return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode); | |
795068a4 | 2274 | |
e0d80184 DM |
2275 | /* This matches "*return_sf_no_fpu". */ |
2276 | else if (! TARGET_FPU && restore_operand (SET_DEST (pat), SFmode) | |
2277 | && register_operand (src, SFmode)) | |
2278 | return 1; | |
f5da225e | 2279 | |
e0d80184 DM |
2280 | /* This matches "*return_addsi". */ |
2281 | else if (GET_CODE (src) == PLUS | |
2282 | && arith_operand (XEXP (src, 0), SImode) | |
2283 | && arith_operand (XEXP (src, 1), SImode) | |
2284 | && (register_operand (XEXP (src, 0), SImode) | |
2285 | || register_operand (XEXP (src, 1), SImode))) | |
2286 | return 1; | |
2287 | ||
2288 | /* This matches "*return_adddi". */ | |
2289 | else if (GET_CODE (src) == PLUS | |
2290 | && arith_double_operand (XEXP (src, 0), DImode) | |
2291 | && arith_double_operand (XEXP (src, 1), DImode) | |
2292 | && (register_operand (XEXP (src, 0), DImode) | |
2293 | || register_operand (XEXP (src, 1), DImode))) | |
795068a4 | 2294 | return 1; |
795068a4 | 2295 | |
795068a4 JW |
2296 | return 0; |
2297 | } | |
2298 | ||
e0d80184 DM |
2299 | static int |
2300 | check_return_regs (x) | |
2301 | rtx x; | |
ab835497 | 2302 | { |
e0d80184 DM |
2303 | switch (GET_CODE (x)) |
2304 | { | |
2305 | case REG: | |
2306 | return IN_OR_GLOBAL_P (x); | |
ab835497 | 2307 | |
e0d80184 DM |
2308 | case CONST_INT: |
2309 | case CONST_DOUBLE: | |
2310 | case CONST: | |
2311 | case SYMBOL_REF: | |
2312 | case LABEL_REF: | |
2313 | return 1; | |
ab835497 | 2314 | |
e0d80184 DM |
2315 | case SET: |
2316 | case IOR: | |
2317 | case AND: | |
2318 | case XOR: | |
2319 | case PLUS: | |
2320 | case MINUS: | |
2321 | if (check_return_regs (XEXP (x, 1)) == 0) | |
2322 | return 0; | |
2323 | case NOT: | |
2324 | case NEG: | |
2325 | case MEM: | |
2326 | return check_return_regs (XEXP (x, 0)); | |
2327 | ||
2328 | default: | |
2329 | return 0; | |
2330 | } | |
ab835497 | 2331 | |
e0d80184 | 2332 | } |
ab835497 | 2333 | |
e0d80184 DM |
2334 | /* Return 1 if TRIAL references only in and global registers. */ |
2335 | int | |
2336 | eligible_for_return_delay (trial) | |
2337 | rtx trial; | |
2338 | { | |
2339 | if (GET_CODE (PATTERN (trial)) != SET) | |
2340 | return 0; | |
ab835497 | 2341 | |
e0d80184 DM |
2342 | return check_return_regs (PATTERN (trial)); |
2343 | } | |
ab835497 | 2344 | |
e0d80184 DM |
2345 | int |
2346 | short_branch (uid1, uid2) | |
2347 | int uid1, uid2; | |
2348 | { | |
2349 | unsigned int delta = insn_addresses[uid1] - insn_addresses[uid2]; | |
2350 | if (delta + 1024 < 2048) | |
2351 | return 1; | |
2352 | /* warning ("long branch, distance %d", delta); */ | |
2353 | return 0; | |
2354 | } | |
ab835497 | 2355 | |
e0d80184 DM |
2356 | /* Return non-zero if REG is not used after INSN. |
2357 | We assume REG is a reload reg, and therefore does | |
2358 | not live past labels or calls or jumps. */ | |
2359 | int | |
2360 | reg_unused_after (reg, insn) | |
2361 | rtx reg; | |
2362 | rtx insn; | |
2363 | { | |
2364 | enum rtx_code code, prev_code = UNKNOWN; | |
ab835497 | 2365 | |
e0d80184 | 2366 | while ((insn = NEXT_INSN (insn))) |
61a55e8b | 2367 | { |
e0d80184 DM |
2368 | if (prev_code == CALL_INSN && call_used_regs[REGNO (reg)]) |
2369 | return 1; | |
ab835497 | 2370 | |
e0d80184 DM |
2371 | code = GET_CODE (insn); |
2372 | if (GET_CODE (insn) == CODE_LABEL) | |
2373 | return 1; | |
bc961ed7 | 2374 | |
e0d80184 | 2375 | if (GET_RTX_CLASS (code) == 'i') |
61a55e8b | 2376 | { |
e0d80184 DM |
2377 | rtx set = single_set (insn); |
2378 | int in_src = set && reg_overlap_mentioned_p (reg, SET_SRC (set)); | |
2379 | if (set && in_src) | |
2380 | return 0; | |
2381 | if (set && reg_overlap_mentioned_p (reg, SET_DEST (set))) | |
2382 | return 1; | |
2383 | if (set == 0 && reg_overlap_mentioned_p (reg, PATTERN (insn))) | |
2384 | return 0; | |
61a55e8b | 2385 | } |
e0d80184 | 2386 | prev_code = code; |
61a55e8b | 2387 | } |
e0d80184 DM |
2388 | return 1; |
2389 | } | |
2390 | \f | |
2391 | /* The table we use to reference PIC data. */ | |
2392 | static rtx global_offset_table; | |
bc961ed7 | 2393 | |
e0d80184 DM |
2394 | /* The function we use to get at it. */ |
2395 | static rtx get_pc_symbol; | |
2396 | static char get_pc_symbol_name[256]; | |
ab835497 | 2397 | |
e0d80184 | 2398 | /* Ensure that we are not using patterns that are not OK with PIC. */ |
795068a4 | 2399 | |
e0d80184 DM |
2400 | int |
2401 | check_pic (i) | |
2402 | int i; | |
2403 | { | |
2404 | switch (flag_pic) | |
ab835497 | 2405 | { |
e0d80184 DM |
2406 | case 1: |
2407 | if (GET_CODE (recog_operand[i]) == SYMBOL_REF | |
2408 | || (GET_CODE (recog_operand[i]) == CONST | |
2409 | && ! (GET_CODE (XEXP (recog_operand[i], 0)) == MINUS | |
2410 | && (XEXP (XEXP (recog_operand[i], 0), 0) | |
2411 | == global_offset_table) | |
2412 | && (GET_CODE (XEXP (XEXP (recog_operand[i], 0), 1)) | |
2413 | == CONST)))) | |
2414 | abort (); | |
2415 | case 2: | |
2416 | default: | |
2417 | return 1; | |
ab835497 | 2418 | } |
ab835497 | 2419 | } |
795068a4 | 2420 | |
e0d80184 DM |
2421 | /* Return true if X is an address which needs a temporary register when |
2422 | reloaded while generating PIC code. */ | |
795068a4 | 2423 | |
e0d80184 DM |
2424 | int |
2425 | pic_address_needs_scratch (x) | |
2426 | rtx x; | |
795068a4 | 2427 | { |
e0d80184 DM |
2428 | /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */ |
2429 | if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS | |
2430 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF | |
2431 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT | |
2432 | && ! SMALL_INT (XEXP (XEXP (x, 0), 1))) | |
2433 | return 1; | |
795068a4 | 2434 | |
e0d80184 DM |
2435 | return 0; |
2436 | } | |
795068a4 | 2437 | |
e0d80184 DM |
2438 | /* Legitimize PIC addresses. If the address is already position-independent, |
2439 | we return ORIG. Newly generated position-independent addresses go into a | |
2440 | reg. This is REG if non zero, otherwise we allocate register(s) as | |
2441 | necessary. */ | |
795068a4 | 2442 | |
e0d80184 DM |
2443 | rtx |
2444 | legitimize_pic_address (orig, mode, reg) | |
2445 | rtx orig; | |
2446 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
2447 | rtx reg; | |
2448 | { | |
2449 | if (GET_CODE (orig) == SYMBOL_REF) | |
82d6b402 | 2450 | { |
e0d80184 DM |
2451 | rtx pic_ref, address; |
2452 | rtx insn; | |
82d6b402 | 2453 | |
e0d80184 | 2454 | if (reg == 0) |
82d6b402 | 2455 | { |
e0d80184 DM |
2456 | if (reload_in_progress || reload_completed) |
2457 | abort (); | |
2458 | else | |
2459 | reg = gen_reg_rtx (Pmode); | |
82d6b402 | 2460 | } |
795068a4 | 2461 | |
e0d80184 | 2462 | if (flag_pic == 2) |
4fb4e4b8 | 2463 | { |
e0d80184 DM |
2464 | /* If not during reload, allocate another temp reg here for loading |
2465 | in the address, so that these instructions can be optimized | |
2466 | properly. */ | |
2467 | rtx temp_reg = ((reload_in_progress || reload_completed) | |
2468 | ? reg : gen_reg_rtx (Pmode)); | |
2469 | ||
2470 | /* Must put the SYMBOL_REF inside an UNSPEC here so that cse | |
2471 | won't get confused into thinking that these two instructions | |
2472 | are loading in the true address of the symbol. If in the | |
2473 | future a PIC rtx exists, that should be used instead. */ | |
be3f1ff5 DM |
2474 | if (Pmode == SImode) |
2475 | { | |
2476 | emit_insn (gen_movsi_high_pic (temp_reg, orig)); | |
2477 | emit_insn (gen_movsi_lo_sum_pic (temp_reg, temp_reg, orig)); | |
2478 | } | |
2479 | else | |
2480 | { | |
2481 | emit_insn (gen_movdi_high_pic (temp_reg, orig)); | |
2482 | emit_insn (gen_movdi_lo_sum_pic (temp_reg, temp_reg, orig)); | |
2483 | } | |
e0d80184 | 2484 | address = temp_reg; |
4fb4e4b8 DE |
2485 | } |
2486 | else | |
e0d80184 DM |
2487 | address = orig; |
2488 | ||
2489 | pic_ref = gen_rtx_MEM (Pmode, | |
2490 | gen_rtx_PLUS (Pmode, | |
2491 | pic_offset_table_rtx, address)); | |
2492 | current_function_uses_pic_offset_table = 1; | |
2493 | RTX_UNCHANGING_P (pic_ref) = 1; | |
2494 | insn = emit_move_insn (reg, pic_ref); | |
2495 | /* Put a REG_EQUAL note on this insn, so that it can be optimized | |
2496 | by loop. */ | |
2497 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, orig, | |
2498 | REG_NOTES (insn)); | |
2499 | return reg; | |
795068a4 | 2500 | } |
e0d80184 | 2501 | else if (GET_CODE (orig) == CONST) |
795068a4 | 2502 | { |
e0d80184 | 2503 | rtx base, offset; |
795068a4 | 2504 | |
e0d80184 DM |
2505 | if (GET_CODE (XEXP (orig, 0)) == PLUS |
2506 | && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx) | |
2507 | return orig; | |
82d6b402 | 2508 | |
e0d80184 | 2509 | if (reg == 0) |
4fb4e4b8 | 2510 | { |
e0d80184 DM |
2511 | if (reload_in_progress || reload_completed) |
2512 | abort (); | |
2513 | else | |
2514 | reg = gen_reg_rtx (Pmode); | |
4fb4e4b8 | 2515 | } |
e0d80184 DM |
2516 | |
2517 | if (GET_CODE (XEXP (orig, 0)) == PLUS) | |
4fb4e4b8 | 2518 | { |
e0d80184 DM |
2519 | base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg); |
2520 | offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode, | |
2521 | base == reg ? 0 : reg); | |
4fb4e4b8 DE |
2522 | } |
2523 | else | |
61a66555 JW |
2524 | abort (); |
2525 | ||
e0d80184 DM |
2526 | if (GET_CODE (offset) == CONST_INT) |
2527 | { | |
2528 | if (SMALL_INT (offset)) | |
2529 | return plus_constant_for_output (base, INTVAL (offset)); | |
2530 | else if (! reload_in_progress && ! reload_completed) | |
2531 | offset = force_reg (Pmode, offset); | |
2532 | else | |
2533 | /* If we reach here, then something is seriously wrong. */ | |
2534 | abort (); | |
2535 | } | |
2536 | return gen_rtx_PLUS (Pmode, base, offset); | |
795068a4 | 2537 | } |
e0d80184 DM |
2538 | else if (GET_CODE (orig) == LABEL_REF) |
2539 | /* ??? Why do we do this? */ | |
2540 | /* Now movsi_pic_label_ref uses it, but we ought to be checking that | |
2541 | the register is live instead, in case it is eliminated. */ | |
2542 | current_function_uses_pic_offset_table = 1; | |
795068a4 | 2543 | |
e0d80184 DM |
2544 | return orig; |
2545 | } | |
795068a4 | 2546 | |
e0d80184 DM |
2547 | /* Return the RTX for insns to set the PIC register. */ |
2548 | ||
2549 | static rtx | |
2550 | pic_setup_code () | |
2551 | { | |
2552 | rtx seq; | |
2553 | ||
2554 | start_sequence (); | |
2555 | emit_insn (gen_get_pc (pic_offset_table_rtx, global_offset_table, | |
2556 | get_pc_symbol)); | |
2557 | seq = gen_sequence (); | |
2558 | end_sequence (); | |
82d6b402 | 2559 | |
e0d80184 DM |
2560 | return seq; |
2561 | } | |
795068a4 | 2562 | |
e0d80184 | 2563 | /* Emit special PIC prologues and epilogues. */ |
795068a4 | 2564 | |
e0d80184 DM |
2565 | void |
2566 | finalize_pic () | |
2567 | { | |
2568 | /* Labels to get the PC in the prologue of this function. */ | |
2569 | int orig_flag_pic = flag_pic; | |
2570 | rtx insn; | |
4fb4e4b8 | 2571 | |
e0d80184 DM |
2572 | if (current_function_uses_pic_offset_table == 0) |
2573 | return; | |
795068a4 | 2574 | |
e0d80184 DM |
2575 | if (! flag_pic) |
2576 | abort (); | |
2577 | ||
2578 | /* If we havn't emitted the special get_pc helper function, do so now. */ | |
2579 | if (get_pc_symbol_name[0] == 0) | |
4fb4e4b8 | 2580 | { |
d676da68 | 2581 | int align; |
82d6b402 | 2582 | |
d676da68 | 2583 | ASM_GENERATE_INTERNAL_LABEL (get_pc_symbol_name, "LGETPC", 0); |
e0d80184 | 2584 | text_section (); |
d676da68 DM |
2585 | |
2586 | align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT); | |
2587 | if (align > 0) | |
2588 | ASM_OUTPUT_ALIGN (asm_out_file, align); | |
e0d80184 DM |
2589 | ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "LGETPC", 0); |
2590 | fputs ("\tretl\n\tadd %o7,%l7,%l7\n", asm_out_file); | |
2591 | } | |
82d6b402 | 2592 | |
e0d80184 DM |
2593 | /* Initialize every time through, since we can't easily |
2594 | know this to be permanent. */ | |
2595 | global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_"); | |
2596 | get_pc_symbol = gen_rtx_SYMBOL_REF (Pmode, get_pc_symbol_name); | |
2597 | flag_pic = 0; | |
82d6b402 | 2598 | |
e0d80184 | 2599 | emit_insn_after (pic_setup_code (), get_insns ()); |
82d6b402 | 2600 | |
24a43d7b DM |
2601 | /* Insert the code in each nonlocal goto receiver. |
2602 | If you make changes here or to the nonlocal_goto_receiver | |
2603 | pattern, make sure the unspec_volatile numbers still | |
2604 | match. */ | |
e0d80184 DM |
2605 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) |
2606 | if (GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == UNSPEC_VOLATILE | |
24a43d7b | 2607 | && XINT (PATTERN (insn), 1) == 5) |
e0d80184 | 2608 | emit_insn_after (pic_setup_code (), insn); |
82d6b402 | 2609 | |
e0d80184 | 2610 | flag_pic = orig_flag_pic; |
82d6b402 | 2611 | |
e0d80184 DM |
2612 | /* Need to emit this whether or not we obey regdecls, |
2613 | since setjmp/longjmp can cause life info to screw up. | |
2614 | ??? In the case where we don't obey regdecls, this is not sufficient | |
2615 | since we may not fall out the bottom. */ | |
2616 | emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx)); | |
795068a4 | 2617 | } |
ab835497 | 2618 | \f |
e0d80184 DM |
2619 | /* Return 1 if RTX is a MEM which is known to be aligned to at |
2620 | least an 8 byte boundary. */ | |
a3ee5899 | 2621 | |
e0d80184 DM |
2622 | int |
2623 | mem_min_alignment (mem, desired) | |
2624 | rtx mem; | |
2625 | int desired; | |
ab835497 | 2626 | { |
e0d80184 DM |
2627 | rtx addr, base, offset; |
2628 | ||
2629 | /* If it's not a MEM we can't accept it. */ | |
2630 | if (GET_CODE (mem) != MEM) | |
2631 | return 0; | |
2632 | ||
2633 | addr = XEXP (mem, 0); | |
2634 | base = offset = NULL_RTX; | |
2635 | if (GET_CODE (addr) == PLUS) | |
ab835497 | 2636 | { |
e0d80184 | 2637 | if (GET_CODE (XEXP (addr, 0)) == REG) |
61a55e8b | 2638 | { |
e0d80184 DM |
2639 | base = XEXP (addr, 0); |
2640 | ||
2641 | /* What we are saying here is that if the base | |
2642 | REG is aligned properly, the compiler will make | |
2643 | sure any REG based index upon it will be so | |
2644 | as well. */ | |
2645 | if (GET_CODE (XEXP (addr, 1)) == CONST_INT) | |
2646 | offset = XEXP (addr, 1); | |
61a55e8b | 2647 | else |
e0d80184 | 2648 | offset = const0_rtx; |
61a55e8b | 2649 | } |
ab835497 | 2650 | } |
e0d80184 | 2651 | else if (GET_CODE (addr) == REG) |
ab835497 | 2652 | { |
e0d80184 DM |
2653 | base = addr; |
2654 | offset = const0_rtx; | |
ab835497 | 2655 | } |
82d6b402 | 2656 | |
e0d80184 | 2657 | if (base != NULL_RTX) |
795068a4 | 2658 | { |
e0d80184 DM |
2659 | int regno = REGNO (base); |
2660 | ||
2661 | if (regno != FRAME_POINTER_REGNUM | |
2662 | && regno != STACK_POINTER_REGNUM) | |
61a55e8b | 2663 | { |
e0d80184 DM |
2664 | /* Check if the compiler has recorded some information |
2665 | about the alignment of the base REG. If reload has | |
2666 | completed, we already matched with proper alignments. */ | |
2667 | if (((regno_pointer_align != NULL | |
2668 | && REGNO_POINTER_ALIGN (regno) >= desired) | |
2669 | || reload_completed) | |
2670 | && ((INTVAL (offset) & (desired - 1)) == 0)) | |
2671 | return 1; | |
61a55e8b | 2672 | } |
795068a4 | 2673 | else |
e0d80184 DM |
2674 | { |
2675 | if (((INTVAL (offset) - SPARC_STACK_BIAS) & (desired - 1)) == 0) | |
2676 | return 1; | |
2677 | } | |
795068a4 | 2678 | } |
e0d80184 DM |
2679 | else if (! TARGET_UNALIGNED_DOUBLES |
2680 | || CONSTANT_P (addr) | |
2681 | || GET_CODE (addr) == LO_SUM) | |
795068a4 | 2682 | { |
e0d80184 DM |
2683 | /* Anything else we know is properly aligned unless TARGET_UNALIGNED_DOUBLES |
2684 | is true, in which case we can only assume that an access is aligned if | |
2685 | it is to a constant address, or the address involves a LO_SUM. */ | |
2686 | return 1; | |
795068a4 | 2687 | } |
e0d80184 DM |
2688 | |
2689 | /* An obviously unaligned address. */ | |
2690 | return 0; | |
795068a4 | 2691 | } |
e0d80184 | 2692 | |
ab835497 | 2693 | \f |
61a55e8b DE |
2694 | /* Vectors to keep interesting information about registers where it can easily |
2695 | be got. We use to use the actual mode value as the bit number, but there | |
2696 | are more than 32 modes now. Instead we use two tables: one indexed by | |
2697 | hard register number, and one indexed by mode. */ | |
2698 | ||
2699 | /* The purpose of sparc_mode_class is to shrink the range of modes so that | |
2700 | they all fit (as bit numbers) in a 32 bit word (again). Each real mode is | |
2701 | mapped into one sparc_mode_class mode. */ | |
2702 | ||
2703 | enum sparc_mode_class { | |
61a55e8b | 2704 | S_MODE, D_MODE, T_MODE, O_MODE, |
c4ce6853 DE |
2705 | SF_MODE, DF_MODE, TF_MODE, OF_MODE, |
2706 | CC_MODE, CCFP_MODE | |
61a55e8b | 2707 | }; |
ab835497 | 2708 | |
61a55e8b DE |
2709 | /* Modes for single-word and smaller quantities. */ |
2710 | #define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE)) | |
2711 | ||
2712 | /* Modes for double-word and smaller quantities. */ | |
2713 | #define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE)) | |
2714 | ||
2715 | /* Modes for quad-word and smaller quantities. */ | |
2716 | #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE)) | |
ab835497 | 2717 | |
1e4eb8d1 JW |
2718 | /* Modes for single-float quantities. We must allow any single word or |
2719 | smaller quantity. This is because the fix/float conversion instructions | |
2720 | take integer inputs/outputs from the float registers. */ | |
2721 | #define SF_MODES (S_MODES) | |
ab835497 | 2722 | |
61a55e8b DE |
2723 | /* Modes for double-float and smaller quantities. */ |
2724 | #define DF_MODES (S_MODES | D_MODES) | |
2725 | ||
284d86e9 | 2726 | #define DF_MODES64 DF_MODES |
61a55e8b DE |
2727 | |
2728 | /* Modes for double-float only quantities. */ | |
284d86e9 | 2729 | #define DF_ONLY_MODES ((1 << (int) DF_MODE) | (1 << (int) D_MODE)) |
61a55e8b DE |
2730 | |
2731 | /* Modes for double-float and larger quantities. */ | |
2732 | #define DF_UP_MODES (DF_ONLY_MODES | TF_ONLY_MODES) | |
ab835497 | 2733 | |
61a55e8b DE |
2734 | /* Modes for quad-float only quantities. */ |
2735 | #define TF_ONLY_MODES (1 << (int) TF_MODE) | |
2736 | ||
2737 | /* Modes for quad-float and smaller quantities. */ | |
2738 | #define TF_MODES (DF_MODES | TF_ONLY_MODES) | |
2739 | ||
61a55e8b | 2740 | #define TF_MODES64 (DF_MODES64 | TF_ONLY_MODES) |
ab835497 | 2741 | |
c4ce6853 DE |
2742 | /* Modes for condition codes. */ |
2743 | #define CC_MODES (1 << (int) CC_MODE) | |
2744 | #define CCFP_MODES (1 << (int) CCFP_MODE) | |
2745 | ||
ab835497 RK |
2746 | /* Value is 1 if register/mode pair is acceptable on sparc. |
2747 | The funny mixture of D and T modes is because integer operations | |
2748 | do not specially operate on tetra quantities, so non-quad-aligned | |
2749 | registers can hold quadword quantities (except %o4 and %i4 because | |
c4ce6853 | 2750 | they cross fixed registers). */ |
ab835497 | 2751 | |
61a55e8b DE |
2752 | /* This points to either the 32 bit or the 64 bit version. */ |
2753 | int *hard_regno_mode_classes; | |
2754 | ||
2755 | static int hard_32bit_mode_classes[] = { | |
c4ce6853 | 2756 | S_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, |
ab835497 RK |
2757 | T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES, |
2758 | T_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, | |
2759 | T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES, | |
2760 | ||
2761 | TF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES, | |
2762 | TF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES, | |
2763 | TF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES, | |
61a55e8b | 2764 | TF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES, |
a9e27770 DE |
2765 | |
2766 | /* FP regs f32 to f63. Only the even numbered registers actually exist, | |
2767 | and none can hold SFmode/SImode values. */ | |
2768 | DF_UP_MODES, 0, DF_ONLY_MODES, 0, DF_UP_MODES, 0, DF_ONLY_MODES, 0, | |
2769 | DF_UP_MODES, 0, DF_ONLY_MODES, 0, DF_UP_MODES, 0, DF_ONLY_MODES, 0, | |
2770 | DF_UP_MODES, 0, DF_ONLY_MODES, 0, DF_UP_MODES, 0, DF_ONLY_MODES, 0, | |
2771 | DF_UP_MODES, 0, DF_ONLY_MODES, 0, DF_UP_MODES, 0, DF_ONLY_MODES, 0, | |
2772 | ||
2773 | /* %fcc[0123] */ | |
c4ce6853 DE |
2774 | CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES, |
2775 | ||
2776 | /* %icc */ | |
2777 | CC_MODES | |
61a55e8b DE |
2778 | }; |
2779 | ||
2780 | static int hard_64bit_mode_classes[] = { | |
c4ce6853 | 2781 | D_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, |
61a55e8b DE |
2782 | T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, |
2783 | T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, | |
2784 | T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, | |
2785 | ||
2786 | TF_MODES64, SF_MODES, DF_MODES64, SF_MODES, TF_MODES64, SF_MODES, DF_MODES64, SF_MODES, | |
2787 | TF_MODES64, SF_MODES, DF_MODES64, SF_MODES, TF_MODES64, SF_MODES, DF_MODES64, SF_MODES, | |
2788 | TF_MODES64, SF_MODES, DF_MODES64, SF_MODES, TF_MODES64, SF_MODES, DF_MODES64, SF_MODES, | |
2789 | TF_MODES64, SF_MODES, DF_MODES64, SF_MODES, TF_MODES64, SF_MODES, DF_MODES64, SF_MODES, | |
2790 | ||
a9e27770 | 2791 | /* FP regs f32 to f63. Only the even numbered registers actually exist, |
61a55e8b DE |
2792 | and none can hold SFmode/SImode values. */ |
2793 | DF_UP_MODES, 0, DF_ONLY_MODES, 0, DF_UP_MODES, 0, DF_ONLY_MODES, 0, | |
2794 | DF_UP_MODES, 0, DF_ONLY_MODES, 0, DF_UP_MODES, 0, DF_ONLY_MODES, 0, | |
2795 | DF_UP_MODES, 0, DF_ONLY_MODES, 0, DF_UP_MODES, 0, DF_ONLY_MODES, 0, | |
2796 | DF_UP_MODES, 0, DF_ONLY_MODES, 0, DF_UP_MODES, 0, DF_ONLY_MODES, 0, | |
2797 | ||
2798 | /* %fcc[0123] */ | |
c4ce6853 DE |
2799 | CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES, |
2800 | ||
2801 | /* %icc */ | |
2802 | CC_MODES | |
61a55e8b DE |
2803 | }; |
2804 | ||
2805 | int sparc_mode_class [NUM_MACHINE_MODES]; | |
2806 | ||
c4ce6853 DE |
2807 | enum reg_class sparc_regno_reg_class[FIRST_PSEUDO_REGISTER]; |
2808 | ||
61a55e8b DE |
2809 | static void |
2810 | sparc_init_modes () | |
2811 | { | |
2812 | int i; | |
2813 | ||
61a55e8b DE |
2814 | for (i = 0; i < NUM_MACHINE_MODES; i++) |
2815 | { | |
2816 | switch (GET_MODE_CLASS (i)) | |
2817 | { | |
2818 | case MODE_INT: | |
2819 | case MODE_PARTIAL_INT: | |
2820 | case MODE_COMPLEX_INT: | |
2821 | if (GET_MODE_SIZE (i) <= 4) | |
2822 | sparc_mode_class[i] = 1 << (int) S_MODE; | |
2823 | else if (GET_MODE_SIZE (i) == 8) | |
2824 | sparc_mode_class[i] = 1 << (int) D_MODE; | |
2825 | else if (GET_MODE_SIZE (i) == 16) | |
2826 | sparc_mode_class[i] = 1 << (int) T_MODE; | |
2827 | else if (GET_MODE_SIZE (i) == 32) | |
2828 | sparc_mode_class[i] = 1 << (int) O_MODE; | |
2829 | else | |
2830 | sparc_mode_class[i] = 0; | |
2831 | break; | |
2832 | case MODE_FLOAT: | |
2833 | case MODE_COMPLEX_FLOAT: | |
2834 | if (GET_MODE_SIZE (i) <= 4) | |
2835 | sparc_mode_class[i] = 1 << (int) SF_MODE; | |
2836 | else if (GET_MODE_SIZE (i) == 8) | |
2837 | sparc_mode_class[i] = 1 << (int) DF_MODE; | |
2838 | else if (GET_MODE_SIZE (i) == 16) | |
2839 | sparc_mode_class[i] = 1 << (int) TF_MODE; | |
2840 | else if (GET_MODE_SIZE (i) == 32) | |
2841 | sparc_mode_class[i] = 1 << (int) OF_MODE; | |
2842 | else | |
2843 | sparc_mode_class[i] = 0; | |
2844 | break; | |
2845 | case MODE_CC: | |
2846 | default: | |
2847 | /* mode_class hasn't been initialized yet for EXTRA_CC_MODES, so | |
2848 | we must explicitly check for them here. */ | |
2849 | if (i == (int) CCFPmode || i == (int) CCFPEmode) | |
2850 | sparc_mode_class[i] = 1 << (int) CCFP_MODE; | |
2851 | else if (i == (int) CCmode || i == (int) CC_NOOVmode | |
a9e27770 | 2852 | || i == (int) CCXmode || i == (int) CCX_NOOVmode) |
c4ce6853 | 2853 | sparc_mode_class[i] = 1 << (int) CC_MODE; |
61a55e8b DE |
2854 | else |
2855 | sparc_mode_class[i] = 0; | |
2856 | break; | |
2857 | } | |
2858 | } | |
2859 | ||
a9e27770 | 2860 | if (TARGET_ARCH64) |
61a55e8b DE |
2861 | hard_regno_mode_classes = hard_64bit_mode_classes; |
2862 | else | |
2863 | hard_regno_mode_classes = hard_32bit_mode_classes; | |
c4ce6853 DE |
2864 | |
2865 | /* Initialize the array used by REGNO_REG_CLASS. */ | |
2866 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
2867 | { | |
284d86e9 JC |
2868 | if (i < 16 && TARGET_V8PLUS) |
2869 | sparc_regno_reg_class[i] = I64_REGS; | |
2870 | else if (i < 32) | |
c4ce6853 DE |
2871 | sparc_regno_reg_class[i] = GENERAL_REGS; |
2872 | else if (i < 64) | |
2873 | sparc_regno_reg_class[i] = FP_REGS; | |
2874 | else if (i < 96) | |
2875 | sparc_regno_reg_class[i] = EXTRA_FP_REGS; | |
2876 | else if (i < 100) | |
2877 | sparc_regno_reg_class[i] = FPCC_REGS; | |
2878 | else | |
2879 | sparc_regno_reg_class[i] = NO_REGS; | |
2880 | } | |
61a55e8b | 2881 | } |
ab835497 | 2882 | \f |
61a55e8b DE |
2883 | /* Save non call used registers from LOW to HIGH at BASE+OFFSET. |
2884 | N_REGS is the number of 4-byte regs saved thus far. This applies even to | |
2885 | v9 int regs as it simplifies the code. */ | |
2886 | ||
ab835497 | 2887 | static int |
c53aa195 | 2888 | save_regs (file, low, high, base, offset, n_regs, real_offset) |
ab835497 RK |
2889 | FILE *file; |
2890 | int low, high; | |
2891 | char *base; | |
2892 | int offset; | |
61a55e8b | 2893 | int n_regs; |
c53aa195 | 2894 | int real_offset; |
ab835497 RK |
2895 | { |
2896 | int i; | |
2897 | ||
a9e27770 | 2898 | if (TARGET_ARCH64 && high <= 32) |
ab835497 | 2899 | { |
61a55e8b DE |
2900 | for (i = low; i < high; i++) |
2901 | { | |
2902 | if (regs_ever_live[i] && ! call_used_regs[i]) | |
c53aa195 | 2903 | { |
e0d80184 | 2904 | fprintf (file, "\tstx\t%s, [%s+%d]\n", |
c53aa195 | 2905 | reg_names[i], base, offset + 4 * n_regs); |
0021b564 | 2906 | if (dwarf2out_do_frame ()) |
c53aa195 | 2907 | dwarf2out_reg_save ("", i, real_offset + 4 * n_regs); |
c53aa195 JM |
2908 | n_regs += 2; |
2909 | } | |
61a55e8b | 2910 | } |
ab835497 | 2911 | } |
61a55e8b DE |
2912 | else |
2913 | { | |
2914 | for (i = low; i < high; i += 2) | |
2915 | { | |
2916 | if (regs_ever_live[i] && ! call_used_regs[i]) | |
c53aa195 | 2917 | { |
5e9defae KG |
2918 | if (regs_ever_live[i+1] && ! call_used_regs[i+1]) |
2919 | { | |
e0d80184 | 2920 | fprintf (file, "\tstd\t%s, [%s+%d]\n", |
5e9defae KG |
2921 | reg_names[i], base, offset + 4 * n_regs); |
2922 | if (dwarf2out_do_frame ()) | |
2923 | { | |
2924 | char *l = dwarf2out_cfi_label (); | |
2925 | dwarf2out_reg_save (l, i, real_offset + 4 * n_regs); | |
2926 | dwarf2out_reg_save (l, i+1, real_offset + 4 * n_regs + 4); | |
2927 | } | |
2928 | n_regs += 2; | |
2929 | } | |
2930 | else | |
2931 | { | |
e0d80184 | 2932 | fprintf (file, "\tst\t%s, [%s+%d]\n", |
5e9defae KG |
2933 | reg_names[i], base, offset + 4 * n_regs); |
2934 | if (dwarf2out_do_frame ()) | |
2935 | dwarf2out_reg_save ("", i, real_offset + 4 * n_regs); | |
2936 | n_regs += 2; | |
2937 | } | |
2938 | } | |
2939 | else | |
2940 | { | |
2941 | if (regs_ever_live[i+1] && ! call_used_regs[i+1]) | |
2942 | { | |
e0d80184 | 2943 | fprintf (file, "\tst\t%s, [%s+%d]\n", |
5e9defae KG |
2944 | reg_names[i+1], base, offset + 4 * n_regs + 4); |
2945 | if (dwarf2out_do_frame ()) | |
2946 | dwarf2out_reg_save ("", i + 1, real_offset + 4 * n_regs + 4); | |
2947 | n_regs += 2; | |
2948 | } | |
c53aa195 | 2949 | } |
61a55e8b DE |
2950 | } |
2951 | } | |
2952 | return n_regs; | |
ab835497 RK |
2953 | } |
2954 | ||
61a55e8b DE |
2955 | /* Restore non call used registers from LOW to HIGH at BASE+OFFSET. |
2956 | ||
2957 | N_REGS is the number of 4-byte regs saved thus far. This applies even to | |
2958 | v9 int regs as it simplifies the code. */ | |
2959 | ||
ab835497 | 2960 | static int |
61a55e8b | 2961 | restore_regs (file, low, high, base, offset, n_regs) |
ab835497 RK |
2962 | FILE *file; |
2963 | int low, high; | |
2964 | char *base; | |
2965 | int offset; | |
61a55e8b | 2966 | int n_regs; |
ab835497 RK |
2967 | { |
2968 | int i; | |
2969 | ||
a9e27770 | 2970 | if (TARGET_ARCH64 && high <= 32) |
61a55e8b DE |
2971 | { |
2972 | for (i = low; i < high; i++) | |
2973 | { | |
2974 | if (regs_ever_live[i] && ! call_used_regs[i]) | |
e0d80184 | 2975 | fprintf (file, "\tldx\t[%s+%d], %s\n", |
61a55e8b DE |
2976 | base, offset + 4 * n_regs, reg_names[i]), |
2977 | n_regs += 2; | |
2978 | } | |
2979 | } | |
2980 | else | |
ab835497 | 2981 | { |
61a55e8b DE |
2982 | for (i = low; i < high; i += 2) |
2983 | { | |
2984 | if (regs_ever_live[i] && ! call_used_regs[i]) | |
2985 | if (regs_ever_live[i+1] && ! call_used_regs[i+1]) | |
e0d80184 | 2986 | fprintf (file, "\tldd\t[%s+%d], %s\n", |
61a55e8b DE |
2987 | base, offset + 4 * n_regs, reg_names[i]), |
2988 | n_regs += 2; | |
2989 | else | |
e0d80184 | 2990 | fprintf (file, "\tld\t[%s+%d],%s\n", |
61a55e8b DE |
2991 | base, offset + 4 * n_regs, reg_names[i]), |
2992 | n_regs += 2; | |
2993 | else if (regs_ever_live[i+1] && ! call_used_regs[i+1]) | |
e0d80184 | 2994 | fprintf (file, "\tld\t[%s+%d],%s\n", |
61a55e8b DE |
2995 | base, offset + 4 * n_regs + 4, reg_names[i+1]), |
2996 | n_regs += 2; | |
2997 | } | |
ab835497 | 2998 | } |
61a55e8b | 2999 | return n_regs; |
ab835497 RK |
3000 | } |
3001 | ||
3002 | /* Static variables we want to share between prologue and epilogue. */ | |
3003 | ||
61a55e8b DE |
3004 | /* Number of live general or floating point registers needed to be saved |
3005 | (as 4-byte quantities). This is only done if TARGET_EPILOGUE. */ | |
3006 | static int num_gfregs; | |
3007 | ||
3008 | /* Compute the frame size required by the function. This function is called | |
3009 | during the reload pass and also by output_function_prologue(). */ | |
ab835497 | 3010 | |
ab835497 RK |
3011 | int |
3012 | compute_frame_size (size, leaf_function) | |
3013 | int size; | |
3014 | int leaf_function; | |
3015 | { | |
61a55e8b | 3016 | int n_regs = 0, i; |
ab835497 | 3017 | int outgoing_args_size = (current_function_outgoing_args_size |
4fb4e4b8 | 3018 | + REG_PARM_STACK_SPACE (current_function_decl)); |
ab835497 | 3019 | |
61a55e8b | 3020 | if (TARGET_EPILOGUE) |
ab835497 | 3021 | { |
61a55e8b DE |
3022 | /* N_REGS is the number of 4-byte regs saved thus far. This applies |
3023 | even to v9 int regs to be consistent with save_regs/restore_regs. */ | |
3024 | ||
a9e27770 | 3025 | if (TARGET_ARCH64) |
61a55e8b DE |
3026 | { |
3027 | for (i = 0; i < 8; i++) | |
3028 | if (regs_ever_live[i] && ! call_used_regs[i]) | |
3029 | n_regs += 2; | |
3030 | } | |
3031 | else | |
3032 | { | |
3033 | for (i = 0; i < 8; i += 2) | |
3034 | if ((regs_ever_live[i] && ! call_used_regs[i]) | |
3035 | || (regs_ever_live[i+1] && ! call_used_regs[i+1])) | |
3036 | n_regs += 2; | |
3037 | } | |
3038 | ||
3039 | for (i = 32; i < (TARGET_V9 ? 96 : 64); i += 2) | |
ab835497 RK |
3040 | if ((regs_ever_live[i] && ! call_used_regs[i]) |
3041 | || (regs_ever_live[i+1] && ! call_used_regs[i+1])) | |
61a55e8b | 3042 | n_regs += 2; |
ab835497 RK |
3043 | } |
3044 | ||
3045 | /* Set up values for use in `function_epilogue'. */ | |
61a55e8b | 3046 | num_gfregs = n_regs; |
ab835497 | 3047 | |
61a55e8b DE |
3048 | if (leaf_function && n_regs == 0 |
3049 | && size == 0 && current_function_outgoing_args_size == 0) | |
3050 | { | |
3051 | actual_fsize = apparent_fsize = 0; | |
3052 | } | |
3053 | else | |
3054 | { | |
3055 | /* We subtract STARTING_FRAME_OFFSET, remember it's negative. | |
3056 | The stack bias (if any) is taken out to undo its effects. */ | |
3057 | apparent_fsize = (size - STARTING_FRAME_OFFSET + SPARC_STACK_BIAS + 7) & -8; | |
3058 | apparent_fsize += n_regs * 4; | |
3059 | actual_fsize = apparent_fsize + ((outgoing_args_size + 7) & -8); | |
3060 | } | |
ab835497 RK |
3061 | |
3062 | /* Make sure nothing can clobber our register windows. | |
3063 | If a SAVE must be done, or there is a stack-local variable, | |
61a55e8b | 3064 | the register window area must be allocated. |
4fb4e4b8 | 3065 | ??? For v8 we apparently need an additional 8 bytes of reserved space. */ |
ab835497 | 3066 | if (leaf_function == 0 || size > 0) |
4fb4e4b8 | 3067 | actual_fsize += (16 * UNITS_PER_WORD) + (TARGET_ARCH64 ? 0 : 8); |
ab835497 | 3068 | |
61a55e8b DE |
3069 | return SPARC_STACK_ALIGN (actual_fsize); |
3070 | } | |
3071 | ||
3072 | /* Build a (32 bit) big number in a register. */ | |
86735b02 | 3073 | /* ??? We may be able to use the set macro here too. */ |
61a55e8b DE |
3074 | |
3075 | static void | |
3076 | build_big_number (file, num, reg) | |
3077 | FILE *file; | |
3078 | int num; | |
3079 | char *reg; | |
3080 | { | |
a9e27770 | 3081 | if (num >= 0 || ! TARGET_ARCH64) |
61a55e8b | 3082 | { |
e0d80184 | 3083 | fprintf (file, "\tsethi\t%%hi(%d), %s\n", num, reg); |
61a55e8b | 3084 | if ((num & 0x3ff) != 0) |
e0d80184 | 3085 | fprintf (file, "\tor\t%s, %%lo(%d), %s\n", reg, num, reg); |
61a55e8b | 3086 | } |
a9e27770 | 3087 | else /* num < 0 && TARGET_ARCH64 */ |
61a55e8b DE |
3088 | { |
3089 | /* Sethi does not sign extend, so we must use a little trickery | |
3090 | to use it for negative numbers. Invert the constant before | |
3091 | loading it in, then use xor immediate to invert the loaded bits | |
3092 | (along with the upper 32 bits) to the desired constant. This | |
3093 | works because the sethi and immediate fields overlap. */ | |
3094 | int asize = num; | |
3095 | int inv = ~asize; | |
3096 | int low = -0x400 + (asize & 0x3FF); | |
3097 | ||
e0d80184 | 3098 | fprintf (file, "\tsethi\t%%hi(%d), %s\n\txor\t%s, %d, %s\n", |
61a55e8b DE |
3099 | inv, reg, reg, low, reg); |
3100 | } | |
ab835497 RK |
3101 | } |
3102 | ||
915f619f JW |
3103 | /* Output code for the function prologue. */ |
3104 | ||
ab835497 RK |
3105 | void |
3106 | output_function_prologue (file, size, leaf_function) | |
3107 | FILE *file; | |
3108 | int size; | |
915f619f | 3109 | int leaf_function; |
ab835497 | 3110 | { |
915f619f JW |
3111 | /* Need to use actual_fsize, since we are also allocating |
3112 | space for our callee (and our own register save area). */ | |
ab835497 RK |
3113 | actual_fsize = compute_frame_size (size, leaf_function); |
3114 | ||
61a55e8b DE |
3115 | if (leaf_function) |
3116 | { | |
3117 | frame_base_name = "%sp"; | |
3118 | frame_base_offset = actual_fsize + SPARC_STACK_BIAS; | |
3119 | } | |
3120 | else | |
3121 | { | |
3122 | frame_base_name = "%fp"; | |
3123 | frame_base_offset = SPARC_STACK_BIAS; | |
3124 | } | |
3125 | ||
c6aa9ce1 | 3126 | /* This is only for the human reader. */ |
bf62bbf1 | 3127 | fprintf (file, "\t%s#PROLOGUE# 0\n", ASM_COMMENT_START); |
c6aa9ce1 | 3128 | |
915f619f JW |
3129 | if (actual_fsize == 0) |
3130 | /* do nothing. */ ; | |
3592ea0d | 3131 | else if (! leaf_function && ! TARGET_BROKEN_SAVERESTORE) |
ab835497 | 3132 | { |
3592ea0d | 3133 | if (actual_fsize <= 4096) |
e0d80184 | 3134 | fprintf (file, "\tsave\t%%sp, -%d, %%sp\n", actual_fsize); |
3592ea0d | 3135 | else if (actual_fsize <= 8192) |
915f619f | 3136 | { |
e0d80184 DM |
3137 | fprintf (file, "\tsave\t%%sp, -4096, %%sp\n"); |
3138 | fprintf (file, "\tadd\t%%sp, -%d, %%sp\n", actual_fsize - 4096); | |
915f619f JW |
3139 | } |
3140 | else | |
3141 | { | |
3592ea0d | 3142 | build_big_number (file, -actual_fsize, "%g1"); |
e0d80184 | 3143 | fprintf (file, "\tsave\t%%sp, %%g1, %%sp\n"); |
915f619f | 3144 | } |
ab835497 | 3145 | } |
5f4241d5 | 3146 | else if (! leaf_function && TARGET_BROKEN_SAVERESTORE) |
ab835497 | 3147 | { |
5f4241d5 | 3148 | /* We assume the environment will properly handle or otherwise avoid |
956d6950 JL |
3149 | trouble associated with an interrupt occurring after the `save' or |
3150 | trap occurring during it. */ | |
5f4241d5 | 3151 | fprintf (file, "\tsave\n"); |
3592ea0d | 3152 | |
5f4241d5 | 3153 | if (actual_fsize <= 4096) |
e0d80184 | 3154 | fprintf (file, "\tadd\t%%fp, -%d, %%sp\n", actual_fsize); |
5f4241d5 DE |
3155 | else if (actual_fsize <= 8192) |
3156 | { | |
e0d80184 DM |
3157 | fprintf (file, "\tadd\t%%fp, -4096, %%sp\n"); |
3158 | fprintf (file, "\tadd\t%%fp, -%d, %%sp\n", actual_fsize - 4096); | |
5f4241d5 DE |
3159 | } |
3160 | else | |
3161 | { | |
3162 | build_big_number (file, -actual_fsize, "%g1"); | |
e0d80184 | 3163 | fprintf (file, "\tadd\t%%fp, %%g1, %%sp\n"); |
5f4241d5 DE |
3164 | } |
3165 | } | |
3166 | else /* leaf function */ | |
3167 | { | |
3592ea0d | 3168 | if (actual_fsize <= 4096) |
e0d80184 | 3169 | fprintf (file, "\tadd\t%%sp, -%d, %%sp\n", actual_fsize); |
3592ea0d DE |
3170 | else if (actual_fsize <= 8192) |
3171 | { | |
e0d80184 DM |
3172 | fprintf (file, "\tadd\t%%sp, -4096, %%sp\n"); |
3173 | fprintf (file, "\tadd\t%%sp, -%d, %%sp\n", actual_fsize - 4096); | |
3592ea0d | 3174 | } |
915f619f | 3175 | else |
3592ea0d DE |
3176 | { |
3177 | build_big_number (file, -actual_fsize, "%g1"); | |
e0d80184 | 3178 | fprintf (file, "\tadd\t%%sp, %%g1, %%sp\n"); |
3592ea0d | 3179 | } |
ab835497 RK |
3180 | } |
3181 | ||
0021b564 | 3182 | if (dwarf2out_do_frame () && actual_fsize) |
c53aa195 | 3183 | { |
96987e96 | 3184 | char *label = dwarf2out_cfi_label (); |
c53aa195 JM |
3185 | |
3186 | /* The canonical frame address refers to the top of the frame. */ | |
3187 | dwarf2out_def_cfa (label, (leaf_function ? STACK_POINTER_REGNUM | |
3188 | : FRAME_POINTER_REGNUM), | |
3189 | frame_base_offset); | |
3190 | ||
3191 | if (! leaf_function) | |
3192 | { | |
3193 | /* Note the register window save. This tells the unwinder that | |
3194 | it needs to restore the window registers from the previous | |
3195 | frame's window save area at 0(cfa). */ | |
3196 | dwarf2out_window_save (label); | |
3197 | ||
3198 | /* The return address (-8) is now in %i7. */ | |
3199 | dwarf2out_return_reg (label, 31); | |
3200 | } | |
3201 | } | |
c53aa195 | 3202 | |
ab835497 RK |
3203 | /* If doing anything with PIC, do it now. */ |
3204 | if (! flag_pic) | |
bf62bbf1 | 3205 | fprintf (file, "\t%s#PROLOGUE# 1\n", ASM_COMMENT_START); |
ab835497 | 3206 | |
61a55e8b DE |
3207 | /* Call saved registers are saved just above the outgoing argument area. */ |
3208 | if (num_gfregs) | |
ab835497 | 3209 | { |
c53aa195 | 3210 | int offset, real_offset, n_regs; |
61a55e8b | 3211 | char *base; |
ab835497 | 3212 | |
84e884e9 JM |
3213 | real_offset = -apparent_fsize; |
3214 | offset = -apparent_fsize + frame_base_offset; | |
61a55e8b DE |
3215 | if (offset < -4096 || offset + num_gfregs * 4 > 4096) |
3216 | { | |
3217 | /* ??? This might be optimized a little as %g1 might already have a | |
3218 | value close enough that a single add insn will do. */ | |
3219 | /* ??? Although, all of this is probably only a temporary fix | |
3220 | because if %g1 can hold a function result, then | |
3221 | output_function_epilogue will lose (the result will get | |
3222 | clobbered). */ | |
3223 | build_big_number (file, offset, "%g1"); | |
e0d80184 | 3224 | fprintf (file, "\tadd\t%s, %%g1, %%g1\n", frame_base_name); |
61a55e8b DE |
3225 | base = "%g1"; |
3226 | offset = 0; | |
3227 | } | |
ab835497 | 3228 | else |
61a55e8b DE |
3229 | { |
3230 | base = frame_base_name; | |
3231 | } | |
ab835497 | 3232 | |
db3d4438 | 3233 | n_regs = 0; |
ab835497 | 3234 | if (TARGET_EPILOGUE && ! leaf_function) |
61a55e8b | 3235 | /* ??? Originally saved regs 0-15 here. */ |
c53aa195 | 3236 | n_regs = save_regs (file, 0, 8, base, offset, 0, real_offset); |
ab835497 | 3237 | else if (leaf_function) |
61a55e8b | 3238 | /* ??? Originally saved regs 0-31 here. */ |
c53aa195 | 3239 | n_regs = save_regs (file, 0, 8, base, offset, 0, real_offset); |
ab835497 | 3240 | if (TARGET_EPILOGUE) |
c53aa195 JM |
3241 | save_regs (file, 32, TARGET_V9 ? 96 : 64, base, offset, n_regs, |
3242 | real_offset); | |
ab835497 RK |
3243 | } |
3244 | ||
ab835497 RK |
3245 | leaf_label = 0; |
3246 | if (leaf_function && actual_fsize != 0) | |
3247 | { | |
3248 | /* warning ("leaf procedure with frame size %d", actual_fsize); */ | |
3249 | if (! TARGET_EPILOGUE) | |
3250 | leaf_label = gen_label_rtx (); | |
3251 | } | |
3252 | } | |
3253 | ||
915f619f JW |
3254 | /* Output code for the function epilogue. */ |
3255 | ||
ab835497 | 3256 | void |
ef8200df | 3257 | output_function_epilogue (file, size, leaf_function) |
ab835497 | 3258 | FILE *file; |
db3d4438 | 3259 | int size ATTRIBUTE_UNUSED; |
ef8200df | 3260 | int leaf_function; |
ab835497 | 3261 | { |
ab835497 RK |
3262 | char *ret; |
3263 | ||
3264 | if (leaf_label) | |
3265 | { | |
ab835497 RK |
3266 | emit_label_after (leaf_label, get_last_insn ()); |
3267 | final_scan_insn (get_last_insn (), file, 0, 0, 1); | |
3268 | } | |
3269 | ||
b69649e4 RK |
3270 | #ifdef FUNCTION_BLOCK_PROFILER_EXIT |
3271 | else if (profile_block_flag == 2) | |
3272 | { | |
3273 | FUNCTION_BLOCK_PROFILER_EXIT(file); | |
3274 | } | |
3275 | #endif | |
3276 | ||
bfd6bc60 JC |
3277 | else if (current_function_epilogue_delay_list == 0) |
3278 | { | |
e0d80184 DM |
3279 | /* If code does not drop into the epilogue, we need |
3280 | do nothing except output pending case vectors. */ | |
bfd6bc60 JC |
3281 | rtx insn = get_last_insn (); |
3282 | if (GET_CODE (insn) == NOTE) | |
3283 | insn = prev_nonnote_insn (insn); | |
3284 | if (insn && GET_CODE (insn) == BARRIER) | |
e0d80184 | 3285 | goto output_vectors; |
bfd6bc60 JC |
3286 | } |
3287 | ||
61a55e8b DE |
3288 | /* Restore any call saved registers. */ |
3289 | if (num_gfregs) | |
ab835497 | 3290 | { |
61a55e8b DE |
3291 | int offset, n_regs; |
3292 | char *base; | |
ab835497 | 3293 | |
61a55e8b DE |
3294 | offset = -apparent_fsize + frame_base_offset; |
3295 | if (offset < -4096 || offset + num_gfregs * 4 > 4096 - 8 /*double*/) | |
3296 | { | |
3297 | build_big_number (file, offset, "%g1"); | |
e0d80184 | 3298 | fprintf (file, "\tadd\t%s, %%g1, %%g1\n", frame_base_name); |
61a55e8b DE |
3299 | base = "%g1"; |
3300 | offset = 0; | |
3301 | } | |
ab835497 | 3302 | else |
61a55e8b DE |
3303 | { |
3304 | base = frame_base_name; | |
3305 | } | |
ab835497 | 3306 | |
db3d4438 | 3307 | n_regs = 0; |
ab835497 | 3308 | if (TARGET_EPILOGUE && ! leaf_function) |
61a55e8b DE |
3309 | /* ??? Originally saved regs 0-15 here. */ |
3310 | n_regs = restore_regs (file, 0, 8, base, offset, 0); | |
ab835497 | 3311 | else if (leaf_function) |
61a55e8b DE |
3312 | /* ??? Originally saved regs 0-31 here. */ |
3313 | n_regs = restore_regs (file, 0, 8, base, offset, 0); | |
ab835497 | 3314 | if (TARGET_EPILOGUE) |
61a55e8b | 3315 | restore_regs (file, 32, TARGET_V9 ? 96 : 64, base, offset, n_regs); |
ab835497 RK |
3316 | } |
3317 | ||
3318 | /* Work out how to skip the caller's unimp instruction if required. */ | |
3319 | if (leaf_function) | |
e0d80184 | 3320 | ret = (SKIP_CALLERS_UNIMP_P ? "jmp\t%o7+12" : "retl"); |
ab835497 | 3321 | else |
e0d80184 | 3322 | ret = (SKIP_CALLERS_UNIMP_P ? "jmp\t%i7+12" : "ret"); |
ab835497 | 3323 | |
ef8200df | 3324 | if (TARGET_EPILOGUE || leaf_label) |
ab835497 | 3325 | { |
ef8200df JW |
3326 | int old_target_epilogue = TARGET_EPILOGUE; |
3327 | target_flags &= ~old_target_epilogue; | |
ab835497 | 3328 | |
ef8200df JW |
3329 | if (! leaf_function) |
3330 | { | |
3331 | /* If we wound up with things in our delay slot, flush them here. */ | |
3332 | if (current_function_epilogue_delay_list) | |
ab835497 | 3333 | { |
254110c2 | 3334 | rtx insn = emit_jump_insn_after (gen_rtx_RETURN (VOIDmode), |
ef8200df | 3335 | get_last_insn ()); |
254110c2 | 3336 | PATTERN (insn) = gen_rtx_PARALLEL (VOIDmode, |
ef8200df JW |
3337 | gen_rtvec (2, |
3338 | PATTERN (XEXP (current_function_epilogue_delay_list, 0)), | |
3339 | PATTERN (insn))); | |
3340 | final_scan_insn (insn, file, 1, 0, 1); | |
ab835497 | 3341 | } |
284d86e9 | 3342 | else if (TARGET_V9 && ! SKIP_CALLERS_UNIMP_P) |
e0d80184 | 3343 | fputs ("\treturn\t%i7+8\n\tnop\n", file); |
ab835497 | 3344 | else |
ef8200df JW |
3345 | fprintf (file, "\t%s\n\trestore\n", ret); |
3346 | } | |
915f619f JW |
3347 | /* All of the following cases are for leaf functions. */ |
3348 | else if (current_function_epilogue_delay_list) | |
ef8200df | 3349 | { |
915f619f JW |
3350 | /* eligible_for_epilogue_delay_slot ensures that if this is a |
3351 | leaf function, then we will only have insn in the delay slot | |
3352 | if the frame size is zero, thus no adjust for the stack is | |
3353 | needed here. */ | |
3354 | if (actual_fsize != 0) | |
ef8200df | 3355 | abort (); |
915f619f JW |
3356 | fprintf (file, "\t%s\n", ret); |
3357 | final_scan_insn (XEXP (current_function_epilogue_delay_list, 0), | |
3358 | file, 1, 0, 1); | |
ab835497 | 3359 | } |
9bb7ffda JW |
3360 | /* Output 'nop' instead of 'sub %sp,-0,%sp' when no frame, so as to |
3361 | avoid generating confusing assembly language output. */ | |
3362 | else if (actual_fsize == 0) | |
3363 | fprintf (file, "\t%s\n\tnop\n", ret); | |
915f619f | 3364 | else if (actual_fsize <= 4096) |
e0d80184 | 3365 | fprintf (file, "\t%s\n\tsub\t%%sp, -%d, %%sp\n", ret, actual_fsize); |
915f619f | 3366 | else if (actual_fsize <= 8192) |
e0d80184 | 3367 | fprintf (file, "\tsub\t%%sp, -4096, %%sp\n\t%s\n\tsub\t%%sp, -%d, %%sp\n", |
915f619f JW |
3368 | ret, actual_fsize - 4096); |
3369 | else if ((actual_fsize & 0x3ff) == 0) | |
e0d80184 | 3370 | fprintf (file, "\tsethi\t%%hi(%d), %%g1\n\t%s\n\tadd\t%%sp, %%g1, %%sp\n", |
915f619f JW |
3371 | actual_fsize, ret); |
3372 | else | |
e0d80184 | 3373 | fprintf (file, "\tsethi\t%%hi(%d), %%g1\n\tor\t%%g1, %%lo(%d), %%g1\n\t%s\n\tadd\t%%sp, %%g1, %%sp\n", |
915f619f | 3374 | actual_fsize, actual_fsize, ret); |
ef8200df | 3375 | target_flags |= old_target_epilogue; |
ab835497 | 3376 | } |
e0d80184 DM |
3377 | |
3378 | output_vectors: | |
3379 | sparc_output_deferred_case_vectors (); | |
ab835497 | 3380 | } |
4fb4e4b8 DE |
3381 | \f |
3382 | /* Functions for handling argument passing. | |
3383 | ||
3384 | For v8 the first six args are normally in registers and the rest are | |
3385 | pushed. Any arg that starts within the first 6 words is at least | |
3386 | partially passed in a register unless its data type forbids. | |
3387 | ||
3388 | For v9, the argument registers are laid out as an array of 16 elements | |
3389 | and arguments are added sequentially. The first 6 int args and up to the | |
3390 | first 16 fp args (depending on size) are passed in regs. | |
3391 | ||
3392 | Slot Stack Integral Float Float in structure Double Long Double | |
3393 | ---- ----- -------- ----- ------------------ ------ ----------- | |
3394 | 15 [SP+248] %f31 %f30,%f31 %d30 | |
3395 | 14 [SP+240] %f29 %f28,%f29 %d28 %q28 | |
3396 | 13 [SP+232] %f27 %f26,%f27 %d26 | |
3397 | 12 [SP+224] %f25 %f24,%f25 %d24 %q24 | |
3398 | 11 [SP+216] %f23 %f22,%f23 %d22 | |
3399 | 10 [SP+208] %f21 %f20,%f21 %d20 %q20 | |
3400 | 9 [SP+200] %f19 %f18,%f19 %d18 | |
3401 | 8 [SP+192] %f17 %f16,%f17 %d16 %q16 | |
3402 | 7 [SP+184] %f15 %f14,%f15 %d14 | |
3403 | 6 [SP+176] %f13 %f12,%f13 %d12 %q12 | |
3404 | 5 [SP+168] %o5 %f11 %f10,%f11 %d10 | |
3405 | 4 [SP+160] %o4 %f9 %f8,%f9 %d8 %q8 | |
3406 | 3 [SP+152] %o3 %f7 %f6,%f7 %d6 | |
3407 | 2 [SP+144] %o2 %f5 %f4,%f5 %d4 %q4 | |
3408 | 1 [SP+136] %o1 %f3 %f2,%f3 %d2 | |
3409 | 0 [SP+128] %o0 %f1 %f0,%f1 %d0 %q0 | |
3410 | ||
3411 | Here SP = %sp if -mno-stack-bias or %sp+stack_bias otherwise. | |
3412 | ||
3413 | Integral arguments are always passed as 64 bit quantities appropriately | |
3414 | extended. | |
3415 | ||
3416 | Passing of floating point values is handled as follows. | |
3417 | If a prototype is in scope: | |
3418 | If the value is in a named argument (i.e. not a stdarg function or a | |
3419 | value not part of the `...') then the value is passed in the appropriate | |
3420 | fp reg. | |
3421 | If the value is part of the `...' and is passed in one of the first 6 | |
3422 | slots then the value is passed in the appropriate int reg. | |
3423 | If the value is part of the `...' and is not passed in one of the first 6 | |
3424 | slots then the value is passed in memory. | |
3425 | If a prototype is not in scope: | |
3426 | If the value is one of the first 6 arguments the value is passed in the | |
3427 | appropriate integer reg and the appropriate fp reg. | |
3428 | If the value is not one of the first 6 arguments the value is passed in | |
3429 | the appropriate fp reg and in memory. | |
3430 | */ | |
3431 | ||
3432 | /* Maximum number of int regs for args. */ | |
3433 | #define SPARC_INT_ARG_MAX 6 | |
3434 | /* Maximum number of fp regs for args. */ | |
3435 | #define SPARC_FP_ARG_MAX 16 | |
3436 | ||
3437 | #define ROUND_ADVANCE(SIZE) (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) | |
3438 | ||
3439 | /* Handle the INIT_CUMULATIVE_ARGS macro. | |
3440 | Initialize a variable CUM of type CUMULATIVE_ARGS | |
3441 | for a call to a function whose data type is FNTYPE. | |
3442 | For a library call, FNTYPE is 0. */ | |
3ea1fdd3 | 3443 | |
4fb4e4b8 DE |
3444 | void |
3445 | init_cumulative_args (cum, fntype, libname, indirect) | |
3446 | CUMULATIVE_ARGS *cum; | |
db3d4438 DM |
3447 | tree fntype; |
3448 | tree libname ATTRIBUTE_UNUSED; | |
3449 | int indirect ATTRIBUTE_UNUSED; | |
4fb4e4b8 DE |
3450 | { |
3451 | cum->words = 0; | |
3452 | cum->prototype_p = fntype && TYPE_ARG_TYPES (fntype); | |
3453 | cum->libcall_p = fntype == 0; | |
3454 | } | |
61a55e8b | 3455 | |
4fb4e4b8 DE |
3456 | /* Compute the slot number to pass an argument in. |
3457 | Returns the slot number or -1 if passing on the stack. | |
3458 | ||
3459 | CUM is a variable of type CUMULATIVE_ARGS which gives info about | |
3460 | the preceding args and about the function being called. | |
3461 | MODE is the argument's machine mode. | |
3462 | TYPE is the data type of the argument (as a tree). | |
3463 | This is null for libcalls where that information may | |
3464 | not be available. | |
3465 | NAMED is nonzero if this argument is a named parameter | |
3466 | (otherwise it is an extra parameter matching an ellipsis). | |
3467 | INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG. | |
3468 | *PREGNO records the register number to use if scalar type. | |
3469 | *PPADDING records the amount of padding needed in words. */ | |
3470 | ||
3471 | static int | |
3472 | function_arg_slotno (cum, mode, type, named, incoming_p, pregno, ppadding) | |
3473 | const CUMULATIVE_ARGS *cum; | |
3474 | enum machine_mode mode; | |
3475 | tree type; | |
3476 | int named; | |
3477 | int incoming_p; | |
3478 | int *pregno; | |
3479 | int *ppadding; | |
3480 | { | |
3481 | int regbase = (incoming_p | |
3482 | ? SPARC_INCOMING_INT_ARG_FIRST | |
3483 | : SPARC_OUTGOING_INT_ARG_FIRST); | |
3484 | int slotno = cum->words; | |
3485 | int regno; | |
3486 | ||
3487 | *ppadding = 0; | |
3488 | ||
3489 | if (type != 0 && TREE_ADDRESSABLE (type)) | |
3490 | return -1; | |
3491 | if (TARGET_ARCH32 | |
3492 | && type != 0 && mode == BLKmode | |
3493 | && TYPE_ALIGN (type) % PARM_BOUNDARY != 0) | |
3494 | return -1; | |
3495 | ||
3496 | switch (mode) | |
3497 | { | |
3498 | case VOIDmode : | |
3499 | /* MODE is VOIDmode when generating the actual call. | |
3500 | See emit_call_1. */ | |
3501 | return -1; | |
3502 | ||
3503 | case QImode : case CQImode : | |
3504 | case HImode : case CHImode : | |
3505 | case SImode : case CSImode : | |
3506 | case DImode : case CDImode : | |
3507 | if (slotno >= SPARC_INT_ARG_MAX) | |
3508 | return -1; | |
3509 | regno = regbase + slotno; | |
3510 | break; | |
3511 | ||
3512 | case SFmode : case SCmode : | |
3513 | case DFmode : case DCmode : | |
3514 | case TFmode : case TCmode : | |
3515 | if (TARGET_ARCH32) | |
3516 | { | |
3517 | if (slotno >= SPARC_INT_ARG_MAX) | |
3518 | return -1; | |
3519 | regno = regbase + slotno; | |
3520 | } | |
3521 | else | |
3522 | { | |
3523 | if ((mode == TFmode || mode == TCmode) | |
3524 | && (slotno & 1) != 0) | |
3525 | slotno++, *ppadding = 1; | |
3526 | if (TARGET_FPU && named) | |
3527 | { | |
3528 | if (slotno >= SPARC_FP_ARG_MAX) | |
82d6b402 | 3529 | return -1; |
4fb4e4b8 DE |
3530 | regno = SPARC_FP_ARG_FIRST + slotno * 2; |
3531 | if (mode == SFmode) | |
3532 | regno++; | |
3533 | } | |
3534 | else | |
3535 | { | |
3536 | if (slotno >= SPARC_INT_ARG_MAX) | |
3537 | return -1; | |
3538 | regno = regbase + slotno; | |
3539 | } | |
3540 | } | |
3541 | break; | |
3542 | ||
3543 | case BLKmode : | |
3544 | /* For sparc64, objects requiring 16 byte alignment get it. */ | |
3545 | if (TARGET_ARCH64) | |
3546 | { | |
3547 | if (type && TYPE_ALIGN (type) == 128 && (slotno & 1) != 0) | |
3548 | slotno++, *ppadding = 1; | |
3549 | } | |
3550 | ||
3551 | if (TARGET_ARCH32 | |
5e9defae | 3552 | || (type && TREE_CODE (type) == UNION_TYPE)) |
4fb4e4b8 DE |
3553 | { |
3554 | if (slotno >= SPARC_INT_ARG_MAX) | |
3555 | return -1; | |
3556 | regno = regbase + slotno; | |
3557 | } | |
3558 | else | |
3559 | { | |
3560 | tree field; | |
3561 | int intregs_p = 0, fpregs_p = 0; | |
3562 | /* The ABI obviously doesn't specify how packed | |
3563 | structures are passed. These are defined to be passed | |
3564 | in int regs if possible, otherwise memory. */ | |
3565 | int packed_p = 0; | |
3566 | ||
3567 | /* First see what kinds of registers we need. */ | |
3568 | for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field)) | |
3569 | { | |
3570 | if (TREE_CODE (field) == FIELD_DECL) | |
3571 | { | |
3572 | if (TREE_CODE (TREE_TYPE (field)) == REAL_TYPE | |
3573 | && TARGET_FPU) | |
3574 | fpregs_p = 1; | |
3575 | else | |
3576 | intregs_p = 1; | |
3577 | if (DECL_PACKED (field)) | |
3578 | packed_p = 1; | |
3579 | } | |
3580 | } | |
3581 | if (packed_p || !named) | |
3582 | fpregs_p = 0, intregs_p = 1; | |
3583 | ||
3584 | /* If all arg slots are filled, then must pass on stack. */ | |
3585 | if (fpregs_p && slotno >= SPARC_FP_ARG_MAX) | |
3586 | return -1; | |
3587 | /* If there are only int args and all int arg slots are filled, | |
3588 | then must pass on stack. */ | |
3589 | if (!fpregs_p && intregs_p && slotno >= SPARC_INT_ARG_MAX) | |
3590 | return -1; | |
3591 | /* Note that even if all int arg slots are filled, fp members may | |
3592 | still be passed in regs if such regs are available. | |
3593 | *PREGNO isn't set because there may be more than one, it's up | |
3594 | to the caller to compute them. */ | |
3595 | return slotno; | |
3596 | } | |
3597 | break; | |
3598 | ||
3599 | default : | |
3600 | abort (); | |
3601 | } | |
3602 | ||
3603 | *pregno = regno; | |
3604 | return slotno; | |
3605 | } | |
3606 | ||
82d6b402 RH |
3607 | /* Handle recursive register counting for structure field layout. */ |
3608 | ||
3609 | struct function_arg_record_value_parms | |
3610 | { | |
3611 | rtx ret; | |
3612 | int slotno, named, regbase; | |
3613 | int nregs, intoffset; | |
3614 | }; | |
3615 | ||
2a01c939 DM |
3616 | static void function_arg_record_value_3 |
3617 | PROTO((int, struct function_arg_record_value_parms *)); | |
3618 | static void function_arg_record_value_2 | |
3619 | PROTO((tree, int, struct function_arg_record_value_parms *)); | |
3620 | static rtx function_arg_record_value | |
3621 | PROTO((tree, enum machine_mode, int, int, int)); | |
3622 | ||
82d6b402 RH |
3623 | static void |
3624 | function_arg_record_value_1 (type, startbitpos, parms) | |
3625 | tree type; | |
3626 | int startbitpos; | |
3627 | struct function_arg_record_value_parms *parms; | |
3628 | { | |
3629 | tree field; | |
3630 | ||
3631 | /* The ABI obviously doesn't specify how packed structures are | |
3632 | passed. These are defined to be passed in int regs if possible, | |
3633 | otherwise memory. */ | |
3634 | int packed_p = 0; | |
3635 | ||
3636 | /* We need to compute how many registers are needed so we can | |
3637 | allocate the PARALLEL but before we can do that we need to know | |
3638 | whether there are any packed fields. If there are, int regs are | |
3639 | used regardless of whether there are fp values present. */ | |
3640 | for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field)) | |
3641 | { | |
3642 | if (TREE_CODE (field) == FIELD_DECL && DECL_PACKED (field)) | |
3643 | { | |
3644 | packed_p = 1; | |
3645 | break; | |
3646 | } | |
3647 | } | |
3648 | ||
3649 | /* Compute how many registers we need. */ | |
3650 | for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field)) | |
3651 | { | |
3652 | if (TREE_CODE (field) == FIELD_DECL) | |
3653 | { | |
3654 | int bitpos = startbitpos; | |
3655 | if (DECL_FIELD_BITPOS (field)) | |
3656 | bitpos += TREE_INT_CST_LOW (DECL_FIELD_BITPOS (field)); | |
3657 | /* ??? FIXME: else assume zero offset. */ | |
3658 | ||
3659 | if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE) | |
3660 | { | |
3661 | function_arg_record_value_1 (TREE_TYPE (field), bitpos, parms); | |
3662 | } | |
3663 | else if (TREE_CODE (TREE_TYPE (field)) == REAL_TYPE | |
3664 | && TARGET_FPU | |
3665 | && ! packed_p | |
3666 | && parms->named) | |
3667 | { | |
3668 | if (parms->intoffset != -1) | |
3669 | { | |
3670 | int intslots, this_slotno; | |
3671 | ||
3672 | intslots = (bitpos - parms->intoffset + BITS_PER_WORD - 1) | |
3673 | / BITS_PER_WORD; | |
3674 | this_slotno = parms->slotno + parms->intoffset | |
3675 | / BITS_PER_WORD; | |
3676 | ||
3677 | intslots = MIN (intslots, SPARC_INT_ARG_MAX - this_slotno); | |
3678 | intslots = MAX (intslots, 0); | |
3679 | parms->nregs += intslots; | |
3680 | parms->intoffset = -1; | |
3681 | } | |
3682 | ||
3683 | /* There's no need to check this_slotno < SPARC_FP_ARG MAX. | |
3684 | If it wasn't true we wouldn't be here. */ | |
3685 | parms->nregs += 1; | |
3686 | } | |
3687 | else | |
3688 | { | |
3689 | if (parms->intoffset == -1) | |
3690 | parms->intoffset = bitpos; | |
3691 | } | |
3692 | } | |
3693 | } | |
3694 | } | |
3695 | ||
3696 | /* Handle recursive structure field register assignment. */ | |
3697 | ||
3698 | static void | |
3699 | function_arg_record_value_3 (bitpos, parms) | |
3700 | int bitpos; | |
3701 | struct function_arg_record_value_parms *parms; | |
3702 | { | |
3703 | enum machine_mode mode; | |
3704 | int regno, this_slotno, intslots, intoffset; | |
3705 | rtx reg; | |
3706 | ||
3707 | if (parms->intoffset == -1) | |
3708 | return; | |
3709 | intoffset = parms->intoffset; | |
3710 | parms->intoffset = -1; | |
3711 | ||
3712 | intslots = (bitpos - intoffset + BITS_PER_WORD - 1) / BITS_PER_WORD; | |
3713 | this_slotno = parms->slotno + intoffset / BITS_PER_WORD; | |
3714 | ||
3715 | intslots = MIN (intslots, SPARC_INT_ARG_MAX - this_slotno); | |
3716 | if (intslots <= 0) | |
3717 | return; | |
3718 | ||
3719 | /* If this is the trailing part of a word, only load that much into | |
3720 | the register. Otherwise load the whole register. Note that in | |
3721 | the latter case we may pick up unwanted bits. It's not a problem | |
3722 | at the moment but may wish to revisit. */ | |
3723 | ||
3724 | if (intoffset % BITS_PER_WORD != 0) | |
3725 | { | |
3726 | mode = mode_for_size (BITS_PER_WORD - intoffset%BITS_PER_WORD, | |
3727 | MODE_INT, 0); | |
3728 | } | |
3729 | else | |
3730 | mode = word_mode; | |
3731 | ||
3732 | intoffset /= BITS_PER_UNIT; | |
3733 | do | |
3734 | { | |
3735 | regno = parms->regbase + this_slotno; | |
254110c2 | 3736 | reg = gen_rtx_REG (mode, regno); |
82d6b402 | 3737 | XVECEXP (parms->ret, 0, parms->nregs) |
254110c2 | 3738 | = gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset)); |
82d6b402 RH |
3739 | |
3740 | this_slotno += 1; | |
3741 | intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1; | |
3742 | parms->nregs += 1; | |
3743 | intslots -= 1; | |
3744 | } | |
3745 | while (intslots > 0); | |
3746 | } | |
3747 | ||
3748 | static void | |
3749 | function_arg_record_value_2 (type, startbitpos, parms) | |
3750 | tree type; | |
3751 | int startbitpos; | |
3752 | struct function_arg_record_value_parms *parms; | |
3753 | { | |
3754 | tree field; | |
3755 | int packed_p = 0; | |
3756 | ||
3757 | for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field)) | |
3758 | { | |
3759 | if (TREE_CODE (field) == FIELD_DECL && DECL_PACKED (field)) | |
3760 | { | |
3761 | packed_p = 1; | |
3762 | break; | |
3763 | } | |
3764 | } | |
3765 | ||
3766 | for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field)) | |
3767 | { | |
3768 | if (TREE_CODE (field) == FIELD_DECL) | |
3769 | { | |
3770 | int bitpos = startbitpos; | |
3771 | if (DECL_FIELD_BITPOS (field)) | |
3772 | bitpos += TREE_INT_CST_LOW (DECL_FIELD_BITPOS (field)); | |
3773 | /* ??? FIXME: else assume zero offset. */ | |
3774 | ||
3775 | if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE) | |
3776 | { | |
3777 | function_arg_record_value_2 (TREE_TYPE (field), bitpos, parms); | |
3778 | } | |
3779 | else if (TREE_CODE (TREE_TYPE (field)) == REAL_TYPE | |
3780 | && TARGET_FPU | |
3781 | && ! packed_p | |
3782 | && parms->named) | |
3783 | { | |
3784 | int this_slotno = parms->slotno + bitpos / BITS_PER_WORD; | |
3785 | rtx reg; | |
3786 | ||
3787 | function_arg_record_value_3 (bitpos, parms); | |
3788 | ||
254110c2 | 3789 | reg = gen_rtx_REG (DECL_MODE (field), |
82d6b402 RH |
3790 | (SPARC_FP_ARG_FIRST + this_slotno * 2 |
3791 | + (DECL_MODE (field) == SFmode | |
3792 | && (bitpos & 32) != 0))); | |
3793 | XVECEXP (parms->ret, 0, parms->nregs) | |
254110c2 | 3794 | = gen_rtx_EXPR_LIST (VOIDmode, reg, |
82d6b402 RH |
3795 | GEN_INT (bitpos / BITS_PER_UNIT)); |
3796 | parms->nregs += 1; | |
3797 | } | |
3798 | else | |
3799 | { | |
3800 | if (parms->intoffset == -1) | |
3801 | parms->intoffset = bitpos; | |
3802 | } | |
3803 | } | |
3804 | } | |
3805 | } | |
3806 | ||
3807 | static rtx | |
1eac9f59 | 3808 | function_arg_record_value (type, mode, slotno, named, regbase) |
82d6b402 | 3809 | tree type; |
1eac9f59 | 3810 | enum machine_mode mode; |
82d6b402 RH |
3811 | int slotno, named, regbase; |
3812 | { | |
3813 | HOST_WIDE_INT typesize = int_size_in_bytes (type); | |
3814 | struct function_arg_record_value_parms parms; | |
3815 | int nregs; | |
3816 | ||
3817 | parms.ret = NULL_RTX; | |
3818 | parms.slotno = slotno; | |
3819 | parms.named = named; | |
3820 | parms.regbase = regbase; | |
3821 | ||
3822 | /* Compute how many registers we need. */ | |
3823 | parms.nregs = 0; | |
3824 | parms.intoffset = 0; | |
3825 | function_arg_record_value_1 (type, 0, &parms); | |
3826 | ||
3827 | if (parms.intoffset != -1) | |
3828 | { | |
3829 | int intslots, this_slotno; | |
3830 | ||
3831 | intslots = (typesize*BITS_PER_UNIT - parms.intoffset + BITS_PER_WORD - 1) | |
3832 | / BITS_PER_WORD; | |
3833 | this_slotno = slotno + parms.intoffset / BITS_PER_WORD; | |
3834 | ||
3835 | intslots = MIN (intslots, SPARC_INT_ARG_MAX - this_slotno); | |
3836 | intslots = MAX (intslots, 0); | |
3837 | ||
3838 | parms.nregs += intslots; | |
3839 | } | |
3840 | nregs = parms.nregs; | |
3841 | ||
3842 | /* Allocate the vector and handle some annoying special cases. */ | |
3843 | if (nregs == 0) | |
3844 | { | |
3845 | /* ??? Empty structure has no value? Duh? */ | |
3846 | if (typesize <= 0) | |
3847 | { | |
3848 | /* Though there's nothing really to store, return a word register | |
3849 | anyway so the rest of gcc doesn't go nuts. Returning a PARALLEL | |
3850 | leads to breakage due to the fact that there are zero bytes to | |
3851 | load. */ | |
1eac9f59 | 3852 | return gen_rtx_REG (mode, regbase); |
82d6b402 RH |
3853 | } |
3854 | else | |
3855 | { | |
3856 | /* ??? C++ has structures with no fields, and yet a size. Give up | |
3857 | for now and pass everything back in integer registers. */ | |
3858 | nregs = (typesize + UNITS_PER_WORD - 1) / UNITS_PER_WORD; | |
3859 | } | |
3860 | if (nregs + slotno > SPARC_INT_ARG_MAX) | |
3861 | nregs = SPARC_INT_ARG_MAX - slotno; | |
3862 | } | |
3863 | if (nregs == 0) | |
9208e4b2 | 3864 | abort (); |
82d6b402 | 3865 | |
1eac9f59 | 3866 | parms.ret = gen_rtx_PARALLEL (mode, rtvec_alloc (nregs)); |
82d6b402 RH |
3867 | |
3868 | /* Fill in the entries. */ | |
3869 | parms.nregs = 0; | |
3870 | parms.intoffset = 0; | |
3871 | function_arg_record_value_2 (type, 0, &parms); | |
3872 | function_arg_record_value_3 (typesize * BITS_PER_UNIT, &parms); | |
3873 | ||
3874 | if (parms.nregs != nregs) | |
3875 | abort (); | |
3876 | ||
3877 | return parms.ret; | |
3878 | } | |
3879 | ||
4fb4e4b8 DE |
3880 | /* Handle the FUNCTION_ARG macro. |
3881 | Determine where to put an argument to a function. | |
3882 | Value is zero to push the argument on the stack, | |
3883 | or a hard register in which to store the argument. | |
3884 | ||
3885 | CUM is a variable of type CUMULATIVE_ARGS which gives info about | |
3886 | the preceding args and about the function being called. | |
3887 | MODE is the argument's machine mode. | |
3888 | TYPE is the data type of the argument (as a tree). | |
3889 | This is null for libcalls where that information may | |
3890 | not be available. | |
3891 | NAMED is nonzero if this argument is a named parameter | |
3892 | (otherwise it is an extra parameter matching an ellipsis). | |
3893 | INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG. */ | |
61a55e8b DE |
3894 | |
3895 | rtx | |
4fb4e4b8 DE |
3896 | function_arg (cum, mode, type, named, incoming_p) |
3897 | const CUMULATIVE_ARGS *cum; | |
3898 | enum machine_mode mode; | |
3899 | tree type; | |
3900 | int named; | |
3901 | int incoming_p; | |
61a55e8b | 3902 | { |
4fb4e4b8 DE |
3903 | int regbase = (incoming_p |
3904 | ? SPARC_INCOMING_INT_ARG_FIRST | |
3905 | : SPARC_OUTGOING_INT_ARG_FIRST); | |
3906 | int slotno, regno, padding; | |
3907 | rtx reg; | |
3908 | ||
3909 | slotno = function_arg_slotno (cum, mode, type, named, incoming_p, | |
3910 | ®no, &padding); | |
3911 | ||
3912 | if (slotno == -1) | |
3913 | return 0; | |
3914 | ||
3915 | if (TARGET_ARCH32) | |
3916 | { | |
254110c2 | 3917 | reg = gen_rtx_REG (mode, regno); |
4fb4e4b8 DE |
3918 | return reg; |
3919 | } | |
3920 | ||
3921 | /* v9 fp args in reg slots beyond the int reg slots get passed in regs | |
3922 | but also have the slot allocated for them. | |
3923 | If no prototype is in scope fp values in register slots get passed | |
3924 | in two places, either fp regs and int regs or fp regs and memory. */ | |
3925 | if ((GET_MODE_CLASS (mode) == MODE_FLOAT | |
3926 | || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT) | |
3927 | && SPARC_FP_REG_P (regno)) | |
3928 | { | |
254110c2 | 3929 | reg = gen_rtx_REG (mode, regno); |
4fb4e4b8 DE |
3930 | if (cum->prototype_p || cum->libcall_p) |
3931 | { | |
3932 | /* "* 2" because fp reg numbers are recorded in 4 byte | |
3933 | quantities. */ | |
82d6b402 | 3934 | #if 0 |
4fb4e4b8 DE |
3935 | /* ??? This will cause the value to be passed in the fp reg and |
3936 | in the stack. When a prototype exists we want to pass the | |
3937 | value in the reg but reserve space on the stack. That's an | |
956d6950 | 3938 | optimization, and is deferred [for a bit]. */ |
4fb4e4b8 | 3939 | if ((regno - SPARC_FP_ARG_FIRST) >= SPARC_INT_ARG_MAX * 2) |
254110c2 | 3940 | return gen_rtx_PARALLEL (mode, |
4fb4e4b8 | 3941 | gen_rtvec (2, |
254110c2 | 3942 | gen_rtx_EXPR_LIST (VOIDmode, |
4fb4e4b8 | 3943 | NULL_RTX, const0_rtx), |
254110c2 | 3944 | gen_rtx_EXPR_LIST (VOIDmode, |
4fb4e4b8 DE |
3945 | reg, const0_rtx))); |
3946 | else | |
82d6b402 RH |
3947 | #else |
3948 | /* ??? It seems that passing back a register even when past | |
3949 | the area declared by REG_PARM_STACK_SPACE will allocate | |
3950 | space appropriately, and will not copy the data onto the | |
3951 | stack, exactly as we desire. | |
3952 | ||
3953 | This is due to locate_and_pad_parm being called in | |
3954 | expand_call whenever reg_parm_stack_space > 0, which | |
3955 | while benefical to our example here, would seem to be | |
3956 | in error from what had been intended. Ho hum... -- r~ */ | |
3957 | #endif | |
4fb4e4b8 DE |
3958 | return reg; |
3959 | } | |
3960 | else | |
3961 | { | |
82d6b402 RH |
3962 | rtx v0, v1; |
3963 | ||
4fb4e4b8 DE |
3964 | if ((regno - SPARC_FP_ARG_FIRST) < SPARC_INT_ARG_MAX * 2) |
3965 | { | |
82d6b402 RH |
3966 | int intreg; |
3967 | ||
3968 | /* On incoming, we don't need to know that the value | |
3969 | is passed in %f0 and %i0, and it confuses other parts | |
3970 | causing needless spillage even on the simplest cases. */ | |
3971 | if (incoming_p) | |
3972 | return reg; | |
3973 | ||
3974 | intreg = (SPARC_OUTGOING_INT_ARG_FIRST | |
3975 | + (regno - SPARC_FP_ARG_FIRST) / 2); | |
3976 | ||
3977 | v0 = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx); | |
3978 | v1 = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_REG (mode, intreg), | |
3979 | const0_rtx); | |
3980 | return gen_rtx_PARALLEL (mode, gen_rtvec (2, v0, v1)); | |
4fb4e4b8 DE |
3981 | } |
3982 | else | |
82d6b402 RH |
3983 | { |
3984 | v0 = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx); | |
3985 | v1 = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx); | |
3986 | return gen_rtx_PARALLEL (mode, gen_rtvec (2, v0, v1)); | |
3987 | } | |
4fb4e4b8 DE |
3988 | } |
3989 | } | |
3990 | else if (type && TREE_CODE (type) == RECORD_TYPE) | |
3991 | { | |
3992 | /* Structures up to 16 bytes in size are passed in arg slots on the | |
3993 | stack and are promoted to registers where possible. */ | |
4fb4e4b8 DE |
3994 | |
3995 | if (int_size_in_bytes (type) > 16) | |
3996 | abort (); /* shouldn't get here */ | |
3997 | ||
1eac9f59 | 3998 | return function_arg_record_value (type, mode, slotno, named, regbase); |
4fb4e4b8 DE |
3999 | } |
4000 | else if (type && TREE_CODE (type) == UNION_TYPE) | |
4001 | { | |
4002 | enum machine_mode mode; | |
4003 | int bytes = int_size_in_bytes (type); | |
4004 | ||
4005 | if (bytes > 16) | |
4006 | abort (); | |
4007 | ||
4008 | mode = mode_for_size (bytes * BITS_PER_UNIT, MODE_INT, 0); | |
254110c2 | 4009 | reg = gen_rtx_REG (mode, regno); |
4fb4e4b8 | 4010 | } |
a7acd911 | 4011 | else |
4fb4e4b8 DE |
4012 | { |
4013 | /* Scalar or complex int. */ | |
254110c2 | 4014 | reg = gen_rtx_REG (mode, regno); |
4fb4e4b8 DE |
4015 | } |
4016 | ||
4017 | return reg; | |
4018 | } | |
a7acd911 | 4019 | |
4fb4e4b8 DE |
4020 | /* Handle the FUNCTION_ARG_PARTIAL_NREGS macro. |
4021 | For an arg passed partly in registers and partly in memory, | |
4022 | this is the number of registers used. | |
4023 | For args passed entirely in registers or entirely in memory, zero. | |
61a55e8b | 4024 | |
4fb4e4b8 DE |
4025 | Any arg that starts in the first 6 regs but won't entirely fit in them |
4026 | needs partial registers on v8. On v9, structures with integer | |
4027 | values in arg slots 5,6 will be passed in %o5 and SP+176, and complex fp | |
4028 | values that begin in the last fp reg [where "last fp reg" varies with the | |
4029 | mode] will be split between that reg and memory. */ | |
61a55e8b | 4030 | |
4fb4e4b8 DE |
4031 | int |
4032 | function_arg_partial_nregs (cum, mode, type, named) | |
4033 | const CUMULATIVE_ARGS *cum; | |
4034 | enum machine_mode mode; | |
4035 | tree type; | |
4036 | int named; | |
4037 | { | |
4038 | int slotno, regno, padding; | |
61a55e8b | 4039 | |
4fb4e4b8 DE |
4040 | /* We pass 0 for incoming_p here, it doesn't matter. */ |
4041 | slotno = function_arg_slotno (cum, mode, type, named, 0, ®no, &padding); | |
4042 | ||
4043 | if (slotno == -1) | |
4044 | return 0; | |
4045 | ||
4046 | if (TARGET_ARCH32) | |
bf62bbf1 | 4047 | { |
4fb4e4b8 DE |
4048 | if ((slotno + (mode == BLKmode |
4049 | ? ROUND_ADVANCE (int_size_in_bytes (type)) | |
4050 | : ROUND_ADVANCE (GET_MODE_SIZE (mode)))) | |
4051 | > NPARM_REGS (SImode)) | |
4052 | return NPARM_REGS (SImode) - slotno; | |
4053 | return 0; | |
4054 | } | |
4055 | else | |
4056 | { | |
4057 | if (type && AGGREGATE_TYPE_P (type)) | |
4058 | { | |
4059 | int size = int_size_in_bytes (type); | |
4060 | int align = TYPE_ALIGN (type); | |
bf62bbf1 | 4061 | |
4fb4e4b8 DE |
4062 | if (align == 16) |
4063 | slotno += slotno & 1; | |
4064 | if (size > 8 && size <= 16 | |
4065 | && slotno == SPARC_INT_ARG_MAX - 1) | |
4066 | return 1; | |
4067 | } | |
4068 | else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_INT | |
4069 | || (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT | |
4070 | && ! TARGET_FPU)) | |
4071 | { | |
4072 | if (GET_MODE_ALIGNMENT (mode) == 128) | |
4073 | { | |
4074 | slotno += slotno & 1; | |
4075 | if (slotno == SPARC_INT_ARG_MAX - 2) | |
4076 | return 1; | |
4077 | } | |
4078 | else | |
4079 | { | |
4080 | if (slotno == SPARC_INT_ARG_MAX - 1) | |
4081 | return 1; | |
4082 | } | |
4083 | } | |
4084 | else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT) | |
4085 | { | |
4086 | if (GET_MODE_ALIGNMENT (mode) == 128) | |
4087 | slotno += slotno & 1; | |
4088 | if ((slotno + GET_MODE_SIZE (mode) / UNITS_PER_WORD) | |
4089 | > SPARC_FP_ARG_MAX) | |
4090 | return 1; | |
4091 | } | |
4092 | return 0; | |
bf62bbf1 | 4093 | } |
4fb4e4b8 | 4094 | } |
61a55e8b | 4095 | |
4fb4e4b8 DE |
4096 | /* Handle the FUNCTION_ARG_PASS_BY_REFERENCE macro. |
4097 | !v9: The SPARC ABI stipulates passing struct arguments (of any size) and | |
4098 | quad-precision floats by invisible reference. | |
82d6b402 | 4099 | v9: Aggregates greater than 16 bytes are passed by reference. |
4fb4e4b8 DE |
4100 | For Pascal, also pass arrays by reference. */ |
4101 | ||
4102 | int | |
4103 | function_arg_pass_by_reference (cum, mode, type, named) | |
db3d4438 | 4104 | const CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED; |
4fb4e4b8 DE |
4105 | enum machine_mode mode; |
4106 | tree type; | |
db3d4438 | 4107 | int named ATTRIBUTE_UNUSED; |
4fb4e4b8 DE |
4108 | { |
4109 | if (TARGET_ARCH32) | |
eadceb59 | 4110 | { |
5e9defae | 4111 | return ((type && AGGREGATE_TYPE_P (type)) |
4fb4e4b8 DE |
4112 | || mode == TFmode || mode == TCmode); |
4113 | } | |
4114 | else | |
4115 | { | |
4116 | return ((type && TREE_CODE (type) == ARRAY_TYPE) | |
82d6b402 RH |
4117 | /* Consider complex values as aggregates, so care for TCmode. */ |
4118 | || GET_MODE_SIZE (mode) > 16 | |
4fb4e4b8 DE |
4119 | || (type && AGGREGATE_TYPE_P (type) |
4120 | && int_size_in_bytes (type) > 16)); | |
4121 | } | |
4122 | } | |
4123 | ||
4124 | /* Handle the FUNCTION_ARG_ADVANCE macro. | |
4125 | Update the data in CUM to advance over an argument | |
4126 | of mode MODE and data type TYPE. | |
4127 | TYPE is null for libcalls where that information may not be available. */ | |
4128 | ||
4129 | void | |
4130 | function_arg_advance (cum, mode, type, named) | |
4131 | CUMULATIVE_ARGS *cum; | |
4132 | enum machine_mode mode; | |
4133 | tree type; | |
4134 | int named; | |
4135 | { | |
4136 | int slotno, regno, padding; | |
4137 | ||
4138 | /* We pass 0 for incoming_p here, it doesn't matter. */ | |
4139 | slotno = function_arg_slotno (cum, mode, type, named, 0, ®no, &padding); | |
4140 | ||
4141 | /* If register required leading padding, add it. */ | |
4142 | if (slotno != -1) | |
4143 | cum->words += padding; | |
eadceb59 | 4144 | |
4fb4e4b8 DE |
4145 | if (TARGET_ARCH32) |
4146 | { | |
4147 | cum->words += (mode != BLKmode | |
4148 | ? ROUND_ADVANCE (GET_MODE_SIZE (mode)) | |
4149 | : ROUND_ADVANCE (int_size_in_bytes (type))); | |
4150 | } | |
4151 | else | |
4152 | { | |
4153 | if (type && AGGREGATE_TYPE_P (type)) | |
4154 | { | |
4155 | int size = int_size_in_bytes (type); | |
4156 | ||
4157 | if (size <= 8) | |
4158 | ++cum->words; | |
4159 | else if (size <= 16) | |
4160 | cum->words += 2; | |
4161 | else /* passed by reference */ | |
4162 | ++cum->words; | |
4163 | } | |
4164 | else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_INT) | |
4165 | { | |
4166 | cum->words += 2; | |
4167 | } | |
4168 | else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT) | |
4169 | { | |
4170 | cum->words += GET_MODE_SIZE (mode) / UNITS_PER_WORD; | |
4171 | } | |
4172 | else | |
4173 | { | |
4174 | cum->words += (mode != BLKmode | |
4175 | ? ROUND_ADVANCE (GET_MODE_SIZE (mode)) | |
4176 | : ROUND_ADVANCE (int_size_in_bytes (type))); | |
4177 | } | |
eadceb59 | 4178 | } |
4fb4e4b8 | 4179 | } |
eadceb59 | 4180 | |
4fb4e4b8 DE |
4181 | /* Handle the FUNCTION_ARG_PADDING macro. |
4182 | For the 64 bit ABI structs are always stored left shifted in their | |
4183 | argument slot. */ | |
4184 | ||
4185 | enum direction | |
4186 | function_arg_padding (mode, type) | |
4187 | enum machine_mode mode; | |
4188 | tree type; | |
4189 | { | |
c85f7c16 JL |
4190 | if (TARGET_ARCH64 && type != 0 && AGGREGATE_TYPE_P (type)) |
4191 | return upward; | |
61a55e8b | 4192 | |
4fb4e4b8 DE |
4193 | /* This is the default definition. */ |
4194 | return (! BYTES_BIG_ENDIAN | |
4195 | ? upward | |
4196 | : ((mode == BLKmode | |
4197 | ? (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST | |
4198 | && int_size_in_bytes (type) < (PARM_BOUNDARY / BITS_PER_UNIT)) | |
4199 | : GET_MODE_BITSIZE (mode) < PARM_BOUNDARY) | |
4200 | ? downward : upward)); | |
61a55e8b | 4201 | } |
82d6b402 RH |
4202 | |
4203 | /* Handle FUNCTION_VALUE, FUNCTION_OUTGOING_VALUE, and LIBCALL_VALUE macros. | |
4204 | For v9, function return values are subject to the same rules as arguments, | |
4205 | except that up to 32-bytes may be returned in registers. */ | |
4206 | ||
4207 | rtx | |
4208 | function_value (type, mode, incoming_p) | |
4209 | tree type; | |
4210 | enum machine_mode mode; | |
4211 | int incoming_p; | |
4212 | { | |
4213 | int regno; | |
4214 | int regbase = (incoming_p | |
4215 | ? SPARC_OUTGOING_INT_ARG_FIRST | |
4216 | : SPARC_INCOMING_INT_ARG_FIRST); | |
4217 | ||
4218 | if (TARGET_ARCH64 && type) | |
4219 | { | |
4220 | if (TREE_CODE (type) == RECORD_TYPE) | |
4221 | { | |
4222 | /* Structures up to 32 bytes in size are passed in registers, | |
4223 | promoted to fp registers where possible. */ | |
4224 | ||
4225 | if (int_size_in_bytes (type) > 32) | |
4226 | abort (); /* shouldn't get here */ | |
4227 | ||
1eac9f59 | 4228 | return function_arg_record_value (type, mode, 0, 1, regbase); |
82d6b402 RH |
4229 | } |
4230 | else if (TREE_CODE (type) == UNION_TYPE) | |
4231 | { | |
4232 | int bytes = int_size_in_bytes (type); | |
4233 | ||
4234 | if (bytes > 32) | |
4235 | abort (); | |
4236 | ||
4237 | mode = mode_for_size (bytes * BITS_PER_UNIT, MODE_INT, 0); | |
4238 | } | |
4239 | } | |
3c6088d2 JJ |
4240 | |
4241 | if (TARGET_ARCH64 | |
4242 | && GET_MODE_CLASS (mode) == MODE_INT | |
4243 | && GET_MODE_SIZE (mode) < UNITS_PER_WORD | |
4244 | && type && TREE_CODE (type) != UNION_TYPE) | |
4245 | mode = DImode; | |
82d6b402 RH |
4246 | |
4247 | if (incoming_p) | |
4248 | regno = BASE_RETURN_VALUE_REG (mode); | |
4249 | else | |
4250 | regno = BASE_OUTGOING_VALUE_REG (mode); | |
4251 | ||
254110c2 | 4252 | return gen_rtx_REG (mode, regno); |
82d6b402 RH |
4253 | } |
4254 | ||
4fb4e4b8 | 4255 | /* Do what is necessary for `va_start'. The argument is ignored. |
61a55e8b | 4256 | |
4fb4e4b8 DE |
4257 | We look at the current function to determine if stdarg or varargs |
4258 | is used and return the address of the first unnamed parameter. */ | |
3ea1fdd3 JW |
4259 | |
4260 | rtx | |
4261 | sparc_builtin_saveregs (arglist) | |
db3d4438 | 4262 | tree arglist ATTRIBUTE_UNUSED; |
3ea1fdd3 | 4263 | { |
4fb4e4b8 | 4264 | int first_reg = current_function_args_info.words; |
3ea1fdd3 JW |
4265 | rtx address; |
4266 | int regno; | |
4267 | ||
4fb4e4b8 | 4268 | for (regno = first_reg; regno < NPARM_REGS (word_mode); regno++) |
254110c2 DM |
4269 | emit_move_insn (gen_rtx_MEM (word_mode, |
4270 | gen_rtx_PLUS (Pmode, | |
3ea1fdd3 JW |
4271 | frame_pointer_rtx, |
4272 | GEN_INT (STACK_POINTER_OFFSET | |
4273 | + UNITS_PER_WORD * regno))), | |
254110c2 | 4274 | gen_rtx_REG (word_mode, |
4fb4e4b8 | 4275 | BASE_INCOMING_ARG_REG (word_mode) + regno)); |
3ea1fdd3 | 4276 | |
254110c2 | 4277 | address = gen_rtx_PLUS (Pmode, |
3ea1fdd3 JW |
4278 | frame_pointer_rtx, |
4279 | GEN_INT (STACK_POINTER_OFFSET | |
4280 | + UNITS_PER_WORD * first_reg)); | |
4281 | ||
7d384cc0 | 4282 | if (current_function_check_memory_usage |
4fb4e4b8 | 4283 | && first_reg < NPARM_REGS (word_mode)) |
eadceb59 RK |
4284 | emit_library_call (chkr_set_right_libfunc, 1, VOIDmode, 3, |
4285 | address, ptr_mode, | |
4286 | GEN_INT (UNITS_PER_WORD | |
4fb4e4b8 | 4287 | * (NPARM_REGS (word_mode) - first_reg)), |
956d6950 JL |
4288 | TYPE_MODE (sizetype), GEN_INT (MEMORY_USE_RW), |
4289 | TYPE_MODE (integer_type_node)); | |
eadceb59 | 4290 | |
3ea1fdd3 JW |
4291 | return address; |
4292 | } | |
ab835497 RK |
4293 | \f |
4294 | /* Return the string to output a conditional branch to LABEL, which is | |
c4ce6853 DE |
4295 | the operand number of the label. OP is the conditional expression. |
4296 | XEXP (OP, 0) is assumed to be a condition code register (integer or | |
4297 | floating point) and its mode specifies what kind of comparison we made. | |
61a55e8b | 4298 | |
ab835497 RK |
4299 | REVERSED is non-zero if we should reverse the sense of the comparison. |
4300 | ||
4301 | ANNUL is non-zero if we should generate an annulling branch. | |
4302 | ||
c6b0465b JC |
4303 | NOOP is non-zero if we have to follow this branch by a noop. |
4304 | ||
4305 | INSN, if set, is the insn. */ | |
ab835497 RK |
4306 | |
4307 | char * | |
c6b0465b | 4308 | output_cbranch (op, label, reversed, annul, noop, insn) |
c4ce6853 | 4309 | rtx op; |
ab835497 RK |
4310 | int label; |
4311 | int reversed, annul, noop; | |
c6b0465b | 4312 | rtx insn; |
ab835497 | 4313 | { |
e0d80184 | 4314 | static char string[32]; |
ab835497 | 4315 | enum rtx_code code = GET_CODE (op); |
c4ce6853 DE |
4316 | rtx cc_reg = XEXP (op, 0); |
4317 | enum machine_mode mode = GET_MODE (cc_reg); | |
e0d80184 DM |
4318 | static char v8_labelno[] = "%lX"; |
4319 | static char v9_icc_labelno[] = "%%icc, %lX"; | |
4320 | static char v9_xcc_labelno[] = "%%xcc, %lX"; | |
4321 | static char v9_fcc_labelno[] = "%%fccX, %lY"; | |
61a55e8b | 4322 | char *labelno; |
e0d80184 | 4323 | int labeloff, spaces = 8; |
61a55e8b DE |
4324 | |
4325 | /* ??? !v9: FP branches cannot be preceded by another floating point insn. | |
ab835497 RK |
4326 | Because there is currently no concept of pre-delay slots, we can fix |
4327 | this only by always emitting a nop before a floating point branch. */ | |
4328 | ||
61a55e8b | 4329 | if ((mode == CCFPmode || mode == CCFPEmode) && ! TARGET_V9) |
ab835497 | 4330 | strcpy (string, "nop\n\t"); |
61a55e8b DE |
4331 | else |
4332 | string[0] = '\0'; | |
ab835497 RK |
4333 | |
4334 | /* If not floating-point or if EQ or NE, we can just reverse the code. */ | |
4d449554 JW |
4335 | if (reversed |
4336 | && ((mode != CCFPmode && mode != CCFPEmode) || code == EQ || code == NE)) | |
ab835497 RK |
4337 | code = reverse_condition (code), reversed = 0; |
4338 | ||
4339 | /* Start by writing the branch condition. */ | |
4340 | switch (code) | |
4341 | { | |
4342 | case NE: | |
4d449554 | 4343 | if (mode == CCFPmode || mode == CCFPEmode) |
e0d80184 DM |
4344 | { |
4345 | strcat (string, "fbne"); | |
4346 | spaces -= 4; | |
4347 | } | |
ab835497 | 4348 | else |
e0d80184 DM |
4349 | { |
4350 | strcpy (string, "bne"); | |
4351 | spaces -= 3; | |
4352 | } | |
ab835497 RK |
4353 | break; |
4354 | ||
4355 | case EQ: | |
4d449554 | 4356 | if (mode == CCFPmode || mode == CCFPEmode) |
e0d80184 DM |
4357 | { |
4358 | strcat (string, "fbe"); | |
4359 | spaces -= 3; | |
4360 | } | |
ab835497 | 4361 | else |
e0d80184 DM |
4362 | { |
4363 | strcpy (string, "be"); | |
4364 | spaces -= 2; | |
4365 | } | |
ab835497 RK |
4366 | break; |
4367 | ||
4368 | case GE: | |
4d449554 | 4369 | if (mode == CCFPmode || mode == CCFPEmode) |
ab835497 RK |
4370 | { |
4371 | if (reversed) | |
4372 | strcat (string, "fbul"); | |
4373 | else | |
4374 | strcat (string, "fbge"); | |
e0d80184 | 4375 | spaces -= 4; |
ab835497 RK |
4376 | } |
4377 | else if (mode == CC_NOOVmode) | |
e0d80184 DM |
4378 | { |
4379 | strcpy (string, "bpos"); | |
4380 | spaces -= 4; | |
4381 | } | |
ab835497 | 4382 | else |
e0d80184 DM |
4383 | { |
4384 | strcpy (string, "bge"); | |
4385 | spaces -= 3; | |
4386 | } | |
ab835497 RK |
4387 | break; |
4388 | ||
4389 | case GT: | |
4d449554 | 4390 | if (mode == CCFPmode || mode == CCFPEmode) |
ab835497 RK |
4391 | { |
4392 | if (reversed) | |
e0d80184 DM |
4393 | { |
4394 | strcat (string, "fbule"); | |
4395 | spaces -= 5; | |
4396 | } | |
ab835497 | 4397 | else |
e0d80184 DM |
4398 | { |
4399 | strcat (string, "fbg"); | |
4400 | spaces -= 3; | |
4401 | } | |
ab835497 RK |
4402 | } |
4403 | else | |
e0d80184 DM |
4404 | { |
4405 | strcpy (string, "bg"); | |
4406 | spaces -= 2; | |
4407 | } | |
ab835497 RK |
4408 | break; |
4409 | ||
4410 | case LE: | |
4d449554 | 4411 | if (mode == CCFPmode || mode == CCFPEmode) |
ab835497 RK |
4412 | { |
4413 | if (reversed) | |
4414 | strcat (string, "fbug"); | |
4415 | else | |
4416 | strcat (string, "fble"); | |
e0d80184 | 4417 | spaces -= 4; |
ab835497 RK |
4418 | } |
4419 | else | |
e0d80184 DM |
4420 | { |
4421 | strcpy (string, "ble"); | |
4422 | spaces -= 3; | |
4423 | } | |
ab835497 RK |
4424 | break; |
4425 | ||
4426 | case LT: | |
4d449554 | 4427 | if (mode == CCFPmode || mode == CCFPEmode) |
ab835497 RK |
4428 | { |
4429 | if (reversed) | |
e0d80184 DM |
4430 | { |
4431 | strcat (string, "fbuge"); | |
4432 | spaces -= 5; | |
4433 | } | |
ab835497 | 4434 | else |
e0d80184 DM |
4435 | { |
4436 | strcat (string, "fbl"); | |
4437 | spaces -= 3; | |
4438 | } | |
ab835497 RK |
4439 | } |
4440 | else if (mode == CC_NOOVmode) | |
e0d80184 DM |
4441 | { |
4442 | strcpy (string, "bneg"); | |
4443 | spaces -= 4; | |
4444 | } | |
ab835497 | 4445 | else |
e0d80184 DM |
4446 | { |
4447 | strcpy (string, "bl"); | |
4448 | spaces -= 2; | |
4449 | } | |
ab835497 RK |
4450 | break; |
4451 | ||
4452 | case GEU: | |
4453 | strcpy (string, "bgeu"); | |
e0d80184 | 4454 | spaces -= 4; |
ab835497 RK |
4455 | break; |
4456 | ||
4457 | case GTU: | |
4458 | strcpy (string, "bgu"); | |
e0d80184 | 4459 | spaces -= 3; |
ab835497 RK |
4460 | break; |
4461 | ||
4462 | case LEU: | |
4463 | strcpy (string, "bleu"); | |
e0d80184 | 4464 | spaces -= 4; |
ab835497 RK |
4465 | break; |
4466 | ||
4467 | case LTU: | |
4468 | strcpy (string, "blu"); | |
e0d80184 | 4469 | spaces -= 3; |
ab835497 | 4470 | break; |
91a51951 KG |
4471 | |
4472 | default: | |
e0d80184 | 4473 | abort (); |
ab835497 RK |
4474 | } |
4475 | ||
4476 | /* Now add the annulling, the label, and a possible noop. */ | |
4477 | if (annul) | |
e0d80184 DM |
4478 | { |
4479 | strcat (string, ",a"); | |
4480 | spaces -= 2; | |
4481 | } | |
ab835497 | 4482 | |
61a55e8b DE |
4483 | if (! TARGET_V9) |
4484 | { | |
e0d80184 | 4485 | labeloff = 2; |
61a55e8b DE |
4486 | labelno = v8_labelno; |
4487 | } | |
4488 | else | |
4489 | { | |
c6b0465b JC |
4490 | rtx note; |
4491 | ||
4492 | if (insn && (note = find_reg_note (insn, REG_BR_PRED, NULL_RTX))) | |
e0d80184 DM |
4493 | { |
4494 | strcat (string, | |
4495 | INTVAL (XEXP (note, 0)) & ATTR_FLAG_likely ? ",pt" : ",pn"); | |
4496 | spaces -= 3; | |
4497 | } | |
c6b0465b | 4498 | |
61a55e8b DE |
4499 | labeloff = 9; |
4500 | if (mode == CCFPmode || mode == CCFPEmode) | |
4501 | { | |
4502 | labeloff = 10; | |
4503 | labelno = v9_fcc_labelno; | |
4504 | /* Set the char indicating the number of the fcc reg to use. */ | |
e0d80184 | 4505 | labelno[5] = REGNO (cc_reg) - SPARC_FIRST_V9_FCC_REG + '0'; |
61a55e8b DE |
4506 | } |
4507 | else if (mode == CCXmode || mode == CCX_NOOVmode) | |
4508 | labelno = v9_xcc_labelno; | |
4509 | else | |
4510 | labelno = v9_icc_labelno; | |
4511 | } | |
4512 | /* Set the char indicating the number of the operand containing the | |
4513 | label_ref. */ | |
4514 | labelno[labeloff] = label + '0'; | |
e0d80184 DM |
4515 | if (spaces > 0) |
4516 | strcat (string, "\t"); | |
4517 | else | |
4518 | strcat (string, " "); | |
61a55e8b DE |
4519 | strcat (string, labelno); |
4520 | ||
4521 | if (noop) | |
4522 | strcat (string, "\n\tnop"); | |
4523 | ||
4524 | return string; | |
4525 | } | |
4526 | ||
4527 | /* Return the string to output a conditional branch to LABEL, testing | |
4528 | register REG. LABEL is the operand number of the label; REG is the | |
4529 | operand number of the reg. OP is the conditional expression. The mode | |
4530 | of REG says what kind of comparison we made. | |
4531 | ||
4532 | REVERSED is non-zero if we should reverse the sense of the comparison. | |
4533 | ||
4534 | ANNUL is non-zero if we should generate an annulling branch. | |
4535 | ||
4536 | NOOP is non-zero if we have to follow this branch by a noop. */ | |
4537 | ||
4538 | char * | |
e0d80184 | 4539 | output_v9branch (op, reg, label, reversed, annul, noop, insn) |
61a55e8b DE |
4540 | rtx op; |
4541 | int reg, label; | |
4542 | int reversed, annul, noop; | |
e0d80184 | 4543 | rtx insn; |
61a55e8b DE |
4544 | { |
4545 | static char string[20]; | |
4546 | enum rtx_code code = GET_CODE (op); | |
4547 | enum machine_mode mode = GET_MODE (XEXP (op, 0)); | |
e0d80184 DM |
4548 | static char labelno[] = "%X, %lX"; |
4549 | rtx note; | |
4550 | int spaces = 8; | |
61a55e8b DE |
4551 | |
4552 | /* If not floating-point or if EQ or NE, we can just reverse the code. */ | |
4553 | if (reversed) | |
4554 | code = reverse_condition (code), reversed = 0; | |
4555 | ||
4556 | /* Only 64 bit versions of these instructions exist. */ | |
4557 | if (mode != DImode) | |
4558 | abort (); | |
4559 | ||
4560 | /* Start by writing the branch condition. */ | |
4561 | ||
4562 | switch (code) | |
4563 | { | |
4564 | case NE: | |
4565 | strcpy (string, "brnz"); | |
e0d80184 | 4566 | spaces -= 4; |
61a55e8b DE |
4567 | break; |
4568 | ||
4569 | case EQ: | |
4570 | strcpy (string, "brz"); | |
e0d80184 | 4571 | spaces -= 3; |
61a55e8b DE |
4572 | break; |
4573 | ||
4574 | case GE: | |
4575 | strcpy (string, "brgez"); | |
e0d80184 | 4576 | spaces -= 5; |
61a55e8b DE |
4577 | break; |
4578 | ||
4579 | case LT: | |
4580 | strcpy (string, "brlz"); | |
e0d80184 | 4581 | spaces -= 4; |
61a55e8b DE |
4582 | break; |
4583 | ||
4584 | case LE: | |
4585 | strcpy (string, "brlez"); | |
e0d80184 | 4586 | spaces -= 5; |
61a55e8b DE |
4587 | break; |
4588 | ||
4589 | case GT: | |
4590 | strcpy (string, "brgz"); | |
e0d80184 | 4591 | spaces -= 4; |
61a55e8b DE |
4592 | break; |
4593 | ||
4594 | default: | |
4595 | abort (); | |
4596 | } | |
4597 | ||
4598 | /* Now add the annulling, reg, label, and nop. */ | |
4599 | if (annul) | |
e0d80184 DM |
4600 | { |
4601 | strcat (string, ",a"); | |
4602 | spaces -= 2; | |
4603 | } | |
61a55e8b | 4604 | |
e0d80184 DM |
4605 | if (insn && (note = find_reg_note (insn, REG_BR_PRED, NULL_RTX))) |
4606 | { | |
4607 | strcat (string, | |
4608 | INTVAL (XEXP (note, 0)) & ATTR_FLAG_likely ? ",pt" : ",pn"); | |
4609 | spaces -= 3; | |
4610 | } | |
61a55e8b | 4611 | |
e0d80184 | 4612 | labelno[1] = reg + '0'; |
61a55e8b | 4613 | labelno[6] = label + '0'; |
e0d80184 DM |
4614 | if (spaces > 0) |
4615 | strcat (string, "\t"); | |
4616 | else | |
4617 | strcat (string, " "); | |
ab835497 RK |
4618 | strcat (string, labelno); |
4619 | ||
4620 | if (noop) | |
4621 | strcat (string, "\n\tnop"); | |
4622 | ||
4623 | return string; | |
4624 | } | |
4625 | ||
284d86e9 JC |
4626 | /* Renumber registers in delay slot. Replace registers instead of |
4627 | renumbering because they may be shared. | |
795068a4 | 4628 | |
284d86e9 JC |
4629 | This does not handle instructions other than move. */ |
4630 | ||
4631 | static void | |
4632 | epilogue_renumber (where) | |
4633 | rtx *where; | |
4634 | { | |
4635 | rtx x = *where; | |
4636 | enum rtx_code code = GET_CODE (x); | |
4637 | ||
4638 | switch (code) | |
4639 | { | |
4640 | case MEM: | |
4641 | *where = x = copy_rtx (x); | |
4642 | epilogue_renumber (&XEXP (x, 0)); | |
4643 | return; | |
4644 | ||
4645 | case REG: | |
4646 | { | |
4647 | int regno = REGNO (x); | |
4648 | if (regno > 8 && regno < 24) | |
4649 | abort (); | |
4650 | if (regno >= 24 && regno < 32) | |
4651 | *where = gen_rtx_REG (GET_MODE (x), regno - 16); | |
4652 | return; | |
4653 | } | |
4654 | case CONST_INT: | |
4655 | case CONST_DOUBLE: | |
4656 | case CONST: | |
4657 | case SYMBOL_REF: | |
4658 | case LABEL_REF: | |
4659 | return; | |
4660 | ||
4661 | case IOR: | |
4662 | case AND: | |
4663 | case XOR: | |
4664 | case PLUS: | |
4665 | case MINUS: | |
4666 | epilogue_renumber (&XEXP (x, 1)); | |
4667 | case NEG: | |
4668 | case NOT: | |
4669 | epilogue_renumber (&XEXP (x, 0)); | |
4670 | return; | |
4671 | ||
4672 | default: | |
4673 | debug_rtx (*where); | |
9208e4b2 | 4674 | abort (); |
284d86e9 JC |
4675 | } |
4676 | } | |
4677 | ||
4678 | /* Output assembler code to return from a function. */ | |
61a55e8b | 4679 | |
ab835497 RK |
4680 | char * |
4681 | output_return (operands) | |
4682 | rtx *operands; | |
4683 | { | |
284d86e9 JC |
4684 | rtx delay = final_sequence ? XVECEXP (final_sequence, 0, 1) : 0; |
4685 | ||
ab835497 RK |
4686 | if (leaf_label) |
4687 | { | |
4688 | operands[0] = leaf_label; | |
284d86e9 | 4689 | return "b%* %l0%("; |
ab835497 RK |
4690 | } |
4691 | else if (leaf_function) | |
4692 | { | |
284d86e9 JC |
4693 | /* No delay slot in a leaf function. */ |
4694 | if (delay) | |
4695 | abort (); | |
4696 | ||
915f619f JW |
4697 | /* If we didn't allocate a frame pointer for the current function, |
4698 | the stack pointer might have been adjusted. Output code to | |
4699 | restore it now. */ | |
4700 | ||
3a598fbe | 4701 | operands[0] = GEN_INT (actual_fsize); |
915f619f JW |
4702 | |
4703 | /* Use sub of negated value in first two cases instead of add to | |
4704 | allow actual_fsize == 4096. */ | |
4705 | ||
4706 | if (actual_fsize <= 4096) | |
ab835497 | 4707 | { |
61a55e8b | 4708 | if (SKIP_CALLERS_UNIMP_P) |
e0d80184 | 4709 | return "jmp\t%%o7+12\n\tsub\t%%sp, -%0, %%sp"; |
ab835497 | 4710 | else |
e0d80184 | 4711 | return "retl\n\tsub\t%%sp, -%0, %%sp"; |
ab835497 | 4712 | } |
915f619f | 4713 | else if (actual_fsize <= 8192) |
ab835497 | 4714 | { |
3a598fbe | 4715 | operands[0] = GEN_INT (actual_fsize - 4096); |
61a55e8b | 4716 | if (SKIP_CALLERS_UNIMP_P) |
e0d80184 | 4717 | return "sub\t%%sp, -4096, %%sp\n\tjmp\t%%o7+12\n\tsub\t%%sp, -%0, %%sp"; |
915f619f | 4718 | else |
e0d80184 | 4719 | return "sub\t%%sp, -4096, %%sp\n\tretl\n\tsub\t%%sp, -%0, %%sp"; |
915f619f | 4720 | } |
61a55e8b | 4721 | else if (SKIP_CALLERS_UNIMP_P) |
915f619f JW |
4722 | { |
4723 | if ((actual_fsize & 0x3ff) != 0) | |
e0d80184 | 4724 | return "sethi\t%%hi(%a0), %%g1\n\tor\t%%g1, %%lo(%a0), %%g1\n\tjmp\t%%o7+12\n\tadd\t%%sp, %%g1, %%sp"; |
ab835497 | 4725 | else |
e0d80184 | 4726 | return "sethi\t%%hi(%a0), %%g1\n\tjmp\t%%o7+12\n\tadd\t%%sp, %%g1, %%sp"; |
915f619f JW |
4727 | } |
4728 | else | |
4729 | { | |
4730 | if ((actual_fsize & 0x3ff) != 0) | |
ab835497 | 4731 | return "sethi %%hi(%a0),%%g1\n\tor %%g1,%%lo(%a0),%%g1\n\tretl\n\tadd %%sp,%%g1,%%sp"; |
915f619f JW |
4732 | else |
4733 | return "sethi %%hi(%a0),%%g1\n\tretl\n\tadd %%sp,%%g1,%%sp"; | |
ab835497 RK |
4734 | } |
4735 | } | |
284d86e9 JC |
4736 | else if (TARGET_V9) |
4737 | { | |
4738 | if (delay) | |
4739 | { | |
4740 | epilogue_renumber (&SET_DEST (PATTERN (delay))); | |
4741 | epilogue_renumber (&SET_SRC (PATTERN (delay))); | |
4742 | } | |
4743 | if (SKIP_CALLERS_UNIMP_P) | |
e0d80184 | 4744 | return "return\t%%i7+12%#"; |
284d86e9 | 4745 | else |
e0d80184 | 4746 | return "return\t%%i7+8%#"; |
284d86e9 | 4747 | } |
ab835497 RK |
4748 | else |
4749 | { | |
284d86e9 JC |
4750 | if (delay) |
4751 | abort (); | |
61a55e8b | 4752 | if (SKIP_CALLERS_UNIMP_P) |
e0d80184 | 4753 | return "jmp\t%%i7+12\n\trestore"; |
ab835497 RK |
4754 | else |
4755 | return "ret\n\trestore"; | |
4756 | } | |
4757 | } | |
ab835497 RK |
4758 | \f |
4759 | /* Leaf functions and non-leaf functions have different needs. */ | |
4760 | ||
4761 | static int | |
4762 | reg_leaf_alloc_order[] = REG_LEAF_ALLOC_ORDER; | |
4763 | ||
4764 | static int | |
4765 | reg_nonleaf_alloc_order[] = REG_ALLOC_ORDER; | |
4766 | ||
4767 | static int *reg_alloc_orders[] = { | |
4768 | reg_leaf_alloc_order, | |
4769 | reg_nonleaf_alloc_order}; | |
4770 | ||
4771 | void | |
4772 | order_regs_for_local_alloc () | |
4773 | { | |
4774 | static int last_order_nonleaf = 1; | |
4775 | ||
4776 | if (regs_ever_live[15] != last_order_nonleaf) | |
4777 | { | |
4778 | last_order_nonleaf = !last_order_nonleaf; | |
d2889939 RK |
4779 | bcopy ((char *) reg_alloc_orders[last_order_nonleaf], |
4780 | (char *) reg_alloc_order, FIRST_PSEUDO_REGISTER * sizeof (int)); | |
ab835497 RK |
4781 | } |
4782 | } | |
4783 | \f | |
e0d80184 DM |
4784 | /* Return 1 if REG and MEM are legitimate enough to allow the various |
4785 | mem<-->reg splits to be run. */ | |
4786 | ||
4787 | int | |
e61c29e9 | 4788 | sparc_splitdi_legitimate (reg, mem) |
e0d80184 DM |
4789 | rtx reg; |
4790 | rtx mem; | |
4791 | { | |
e0d80184 DM |
4792 | /* Punt if we are here by mistake. */ |
4793 | if (! reload_completed) | |
9208e4b2 | 4794 | abort (); |
e0d80184 DM |
4795 | |
4796 | /* We must have an offsettable memory reference. */ | |
4797 | if (! offsettable_memref_p (mem)) | |
4798 | return 0; | |
4799 | ||
4800 | /* If we have legitimate args for ldd/std, we do not want | |
4801 | the split to happen. */ | |
4802 | if ((REGNO (reg) % 2) == 0 | |
4803 | && mem_min_alignment (mem, 8)) | |
4804 | return 0; | |
4805 | ||
4806 | /* Success. */ | |
4807 | return 1; | |
4808 | } | |
4809 | ||
e61c29e9 DM |
4810 | /* Return 1 if x and y are some kind of REG and they refer to |
4811 | different hard registers. This test is guarenteed to be | |
4812 | run after reload. */ | |
4813 | ||
4814 | int | |
4815 | sparc_absnegfloat_split_legitimate (x, y) | |
4816 | rtx x, y; | |
4817 | { | |
4818 | if (GET_CODE (x) == SUBREG) | |
4819 | x = alter_subreg (x); | |
4820 | if (GET_CODE (x) != REG) | |
4821 | return 0; | |
4822 | if (GET_CODE (y) == SUBREG) | |
4823 | y = alter_subreg (y); | |
4824 | if (GET_CODE (y) != REG) | |
4825 | return 0; | |
4826 | if (REGNO (x) == REGNO (y)) | |
4827 | return 0; | |
4828 | return 1; | |
4829 | } | |
4830 | ||
35016322 JW |
4831 | /* Return 1 if REGNO (reg1) is even and REGNO (reg1) == REGNO (reg2) - 1. |
4832 | This makes them candidates for using ldd and std insns. | |
4833 | ||
bfd6bc60 | 4834 | Note reg1 and reg2 *must* be hard registers. */ |
35016322 JW |
4835 | |
4836 | int | |
7c56249d | 4837 | registers_ok_for_ldd_peep (reg1, reg2) |
35016322 JW |
4838 | rtx reg1, reg2; |
4839 | { | |
35016322 JW |
4840 | /* We might have been passed a SUBREG. */ |
4841 | if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG) | |
4842 | return 0; | |
4843 | ||
35016322 JW |
4844 | if (REGNO (reg1) % 2 != 0) |
4845 | return 0; | |
4846 | ||
bfd6bc60 JC |
4847 | /* Integer ldd is deprecated in SPARC V9 */ |
4848 | if (TARGET_V9 && REGNO (reg1) < 32) | |
4849 | return 0; | |
4850 | ||
35016322 | 4851 | return (REGNO (reg1) == REGNO (reg2) - 1); |
35016322 JW |
4852 | } |
4853 | ||
4854 | /* Return 1 if addr1 and addr2 are suitable for use in an ldd or | |
4855 | std insn. | |
4856 | ||
4857 | This can only happen when addr1 and addr2 are consecutive memory | |
4858 | locations (addr1 + 4 == addr2). addr1 must also be aligned on a | |
4859 | 64 bit boundary (addr1 % 8 == 0). | |
4860 | ||
4861 | We know %sp and %fp are kept aligned on a 64 bit boundary. Other | |
4862 | registers are assumed to *never* be properly aligned and are | |
4863 | rejected. | |
4864 | ||
4865 | Knowing %sp and %fp are kept aligned on a 64 bit boundary, we | |
4866 | need only check that the offset for addr1 % 8 == 0. */ | |
4867 | ||
4868 | int | |
7c56249d | 4869 | addrs_ok_for_ldd_peep (addr1, addr2) |
35016322 JW |
4870 | rtx addr1, addr2; |
4871 | { | |
4872 | int reg1, offset1; | |
4873 | ||
4874 | /* Extract a register number and offset (if used) from the first addr. */ | |
4875 | if (GET_CODE (addr1) == PLUS) | |
4876 | { | |
4877 | /* If not a REG, return zero. */ | |
4878 | if (GET_CODE (XEXP (addr1, 0)) != REG) | |
4879 | return 0; | |
4880 | else | |
4881 | { | |
4882 | reg1 = REGNO (XEXP (addr1, 0)); | |
4883 | /* The offset must be constant! */ | |
4884 | if (GET_CODE (XEXP (addr1, 1)) != CONST_INT) | |
4885 | return 0; | |
4886 | offset1 = INTVAL (XEXP (addr1, 1)); | |
4887 | } | |
4888 | } | |
4889 | else if (GET_CODE (addr1) != REG) | |
4890 | return 0; | |
4891 | else | |
4892 | { | |
4893 | reg1 = REGNO (addr1); | |
4894 | /* This was a simple (mem (reg)) expression. Offset is 0. */ | |
4895 | offset1 = 0; | |
4896 | } | |
4897 | ||
4898 | /* Make sure the second address is a (mem (plus (reg) (const_int). */ | |
4899 | if (GET_CODE (addr2) != PLUS) | |
4900 | return 0; | |
4901 | ||
4902 | if (GET_CODE (XEXP (addr2, 0)) != REG | |
4903 | || GET_CODE (XEXP (addr2, 1)) != CONST_INT) | |
4904 | return 0; | |
4905 | ||
4906 | /* Only %fp and %sp are allowed. Additionally both addresses must | |
4907 | use the same register. */ | |
4908 | if (reg1 != FRAME_POINTER_REGNUM && reg1 != STACK_POINTER_REGNUM) | |
4909 | return 0; | |
4910 | ||
4911 | if (reg1 != REGNO (XEXP (addr2, 0))) | |
4912 | return 0; | |
4913 | ||
2296cba3 | 4914 | /* The first offset must be evenly divisible by 8 to ensure the |
35016322 JW |
4915 | address is 64 bit aligned. */ |
4916 | if (offset1 % 8 != 0) | |
4917 | return 0; | |
4918 | ||
4919 | /* The offset for the second addr must be 4 more than the first addr. */ | |
4920 | if (INTVAL (XEXP (addr2, 1)) != offset1 + 4) | |
4921 | return 0; | |
4922 | ||
4923 | /* All the tests passed. addr1 and addr2 are valid for ldd and std | |
4924 | instructions. */ | |
4925 | return 1; | |
4926 | } | |
7c56249d JL |
4927 | |
4928 | /* Return 1 if reg is a pseudo, or is the first register in | |
4929 | a hard register pair. This makes it a candidate for use in | |
4930 | ldd and std insns. */ | |
4931 | ||
4932 | int | |
4933 | register_ok_for_ldd (reg) | |
4934 | rtx reg; | |
4935 | { | |
7c56249d JL |
4936 | /* We might have been passed a SUBREG. */ |
4937 | if (GET_CODE (reg) != REG) | |
4938 | return 0; | |
4939 | ||
4940 | if (REGNO (reg) < FIRST_PSEUDO_REGISTER) | |
4941 | return (REGNO (reg) % 2 == 0); | |
4942 | else | |
4943 | return 1; | |
7c56249d | 4944 | } |
ab835497 | 4945 | \f |
ab835497 RK |
4946 | /* Print operand X (an rtx) in assembler syntax to file FILE. |
4947 | CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. | |
4948 | For `%' followed by punctuation, CODE is the punctuation and X is null. */ | |
4949 | ||
4950 | void | |
4951 | print_operand (file, x, code) | |
4952 | FILE *file; | |
4953 | rtx x; | |
4954 | int code; | |
4955 | { | |
4956 | switch (code) | |
4957 | { | |
4958 | case '#': | |
4959 | /* Output a 'nop' if there's nothing for the delay slot. */ | |
4960 | if (dbr_sequence_length () == 0) | |
e0d80184 | 4961 | fputs ("\n\t nop", file); |
ab835497 RK |
4962 | return; |
4963 | case '*': | |
c6ce0969 JW |
4964 | /* Output an annul flag if there's nothing for the delay slot and we |
4965 | are optimizing. This is always used with '(' below. */ | |
4966 | /* Sun OS 4.1.1 dbx can't handle an annulled unconditional branch; | |
4967 | this is a dbx bug. So, we only do this when optimizing. */ | |
bfd6bc60 JC |
4968 | /* On UltraSPARC, a branch in a delay slot causes a pipeline flush. |
4969 | Always emit a nop in case the next instruction is a branch. */ | |
4970 | if (dbr_sequence_length () == 0 | |
284d86e9 | 4971 | && (optimize && (int)sparc_cpu < PROCESSOR_V9)) |
c6ce0969 JW |
4972 | fputs (",a", file); |
4973 | return; | |
4974 | case '(': | |
4975 | /* Output a 'nop' if there's nothing for the delay slot and we are | |
4976 | not optimizing. This is always used with '*' above. */ | |
bfd6bc60 | 4977 | if (dbr_sequence_length () == 0 |
284d86e9 | 4978 | && ! (optimize && (int)sparc_cpu < PROCESSOR_V9)) |
e0d80184 | 4979 | fputs ("\n\t nop", file); |
ab835497 | 4980 | return; |
61a55e8b | 4981 | case '_': |
a0a301fc DE |
4982 | /* Output the Embedded Medium/Anywhere code model base register. */ |
4983 | fputs (EMBMEDANY_BASE_REG, file); | |
61a55e8b DE |
4984 | return; |
4985 | case '@': | |
4986 | /* Print out what we are using as the frame pointer. This might | |
4987 | be %fp, or might be %sp+offset. */ | |
4988 | /* ??? What if offset is too big? Perhaps the caller knows it isn't? */ | |
4989 | fprintf (file, "%s+%d", frame_base_name, frame_base_offset); | |
4990 | return; | |
ab835497 RK |
4991 | case 'Y': |
4992 | /* Adjust the operand to take into account a RESTORE operation. */ | |
bfd6bc60 JC |
4993 | if (GET_CODE (x) == CONST_INT) |
4994 | break; | |
4995 | else if (GET_CODE (x) != REG) | |
b3b1e8bd JW |
4996 | output_operand_lossage ("Invalid %%Y operand"); |
4997 | else if (REGNO (x) < 8) | |
ab835497 RK |
4998 | fputs (reg_names[REGNO (x)], file); |
4999 | else if (REGNO (x) >= 24 && REGNO (x) < 32) | |
5000 | fputs (reg_names[REGNO (x)-16], file); | |
5001 | else | |
b3b1e8bd | 5002 | output_operand_lossage ("Invalid %%Y operand"); |
ab835497 | 5003 | return; |
0f39a9aa DE |
5004 | case 'L': |
5005 | /* Print out the low order register name of a register pair. */ | |
5006 | if (WORDS_BIG_ENDIAN) | |
5007 | fputs (reg_names[REGNO (x)+1], file); | |
5008 | else | |
5009 | fputs (reg_names[REGNO (x)], file); | |
5010 | return; | |
5011 | case 'H': | |
5012 | /* Print out the high order register name of a register pair. */ | |
5013 | if (WORDS_BIG_ENDIAN) | |
5014 | fputs (reg_names[REGNO (x)], file); | |
5015 | else | |
5016 | fputs (reg_names[REGNO (x)+1], file); | |
5017 | return; | |
ab835497 | 5018 | case 'R': |
795068a4 | 5019 | /* Print out the second register name of a register pair or quad. |
ab835497 RK |
5020 | I.e., R (%o0) => %o1. */ |
5021 | fputs (reg_names[REGNO (x)+1], file); | |
5022 | return; | |
795068a4 JW |
5023 | case 'S': |
5024 | /* Print out the third register name of a register quad. | |
5025 | I.e., S (%o0) => %o2. */ | |
5026 | fputs (reg_names[REGNO (x)+2], file); | |
5027 | return; | |
5028 | case 'T': | |
5029 | /* Print out the fourth register name of a register quad. | |
5030 | I.e., T (%o0) => %o3. */ | |
5031 | fputs (reg_names[REGNO (x)+3], file); | |
5032 | return; | |
304b7a23 DE |
5033 | case 'x': |
5034 | /* Print a condition code register. */ | |
5035 | if (REGNO (x) == SPARC_ICC_REG) | |
5036 | { | |
5037 | /* We don't handle CC[X]_NOOVmode because they're not supposed | |
5038 | to occur here. */ | |
5039 | if (GET_MODE (x) == CCmode) | |
5040 | fputs ("%icc", file); | |
5041 | else if (GET_MODE (x) == CCXmode) | |
5042 | fputs ("%xcc", file); | |
5043 | else | |
5044 | abort (); | |
5045 | } | |
5046 | else | |
5047 | /* %fccN register */ | |
5048 | fputs (reg_names[REGNO (x)], file); | |
5049 | return; | |
ab835497 RK |
5050 | case 'm': |
5051 | /* Print the operand's address only. */ | |
5052 | output_address (XEXP (x, 0)); | |
5053 | return; | |
5054 | case 'r': | |
5055 | /* In this case we need a register. Use %g0 if the | |
77a02b01 | 5056 | operand is const0_rtx. */ |
76052e74 RS |
5057 | if (x == const0_rtx |
5058 | || (GET_MODE (x) != VOIDmode && x == CONST0_RTX (GET_MODE (x)))) | |
ab835497 RK |
5059 | { |
5060 | fputs ("%g0", file); | |
5061 | return; | |
5062 | } | |
5063 | else | |
5064 | break; | |
5065 | ||
61a55e8b | 5066 | case 'A': |
ab835497 RK |
5067 | switch (GET_CODE (x)) |
5068 | { | |
5069 | case IOR: fputs ("or", file); break; | |
5070 | case AND: fputs ("and", file); break; | |
5071 | case XOR: fputs ("xor", file); break; | |
b3b1e8bd | 5072 | default: output_operand_lossage ("Invalid %%A operand"); |
ab835497 RK |
5073 | } |
5074 | return; | |
5075 | ||
5076 | case 'B': | |
5077 | switch (GET_CODE (x)) | |
5078 | { | |
5079 | case IOR: fputs ("orn", file); break; | |
5080 | case AND: fputs ("andn", file); break; | |
5081 | case XOR: fputs ("xnor", file); break; | |
b3b1e8bd | 5082 | default: output_operand_lossage ("Invalid %%B operand"); |
ab835497 RK |
5083 | } |
5084 | return; | |
5085 | ||
304b7a23 DE |
5086 | /* These are used by the conditional move instructions. */ |
5087 | case 'c' : | |
61a55e8b | 5088 | case 'C': |
304b7a23 DE |
5089 | { |
5090 | enum rtx_code rc = (code == 'c' | |
5091 | ? reverse_condition (GET_CODE (x)) | |
5092 | : GET_CODE (x)); | |
5093 | switch (rc) | |
5094 | { | |
5095 | case NE: fputs ("ne", file); break; | |
5096 | case EQ: fputs ("e", file); break; | |
5097 | case GE: fputs ("ge", file); break; | |
5098 | case GT: fputs ("g", file); break; | |
5099 | case LE: fputs ("le", file); break; | |
5100 | case LT: fputs ("l", file); break; | |
5101 | case GEU: fputs ("geu", file); break; | |
5102 | case GTU: fputs ("gu", file); break; | |
5103 | case LEU: fputs ("leu", file); break; | |
5104 | case LTU: fputs ("lu", file); break; | |
5105 | default: output_operand_lossage (code == 'c' | |
5106 | ? "Invalid %%c operand" | |
5107 | : "Invalid %%C operand"); | |
5108 | } | |
5109 | return; | |
5110 | } | |
5111 | ||
5112 | /* These are used by the movr instruction pattern. */ | |
5113 | case 'd': | |
61a55e8b | 5114 | case 'D': |
304b7a23 DE |
5115 | { |
5116 | enum rtx_code rc = (code == 'd' | |
5117 | ? reverse_condition (GET_CODE (x)) | |
5118 | : GET_CODE (x)); | |
5119 | switch (rc) | |
5120 | { | |
5121 | case NE: fputs ("ne", file); break; | |
5122 | case EQ: fputs ("e", file); break; | |
5123 | case GE: fputs ("gez", file); break; | |
5124 | case LT: fputs ("lz", file); break; | |
5125 | case LE: fputs ("lez", file); break; | |
5126 | case GT: fputs ("gz", file); break; | |
5127 | default: output_operand_lossage (code == 'd' | |
5128 | ? "Invalid %%d operand" | |
5129 | : "Invalid %%D operand"); | |
5130 | } | |
5131 | return; | |
5132 | } | |
61a55e8b | 5133 | |
ab835497 RK |
5134 | case 'b': |
5135 | { | |
5136 | /* Print a sign-extended character. */ | |
5137 | int i = INTVAL (x) & 0xff; | |
5138 | if (i & 0x80) | |
5139 | i |= 0xffffff00; | |
5140 | fprintf (file, "%d", i); | |
5141 | return; | |
5142 | } | |
5143 | ||
d2889939 RK |
5144 | case 'f': |
5145 | /* Operand must be a MEM; write its address. */ | |
5146 | if (GET_CODE (x) != MEM) | |
5147 | output_operand_lossage ("Invalid %%f operand"); | |
5148 | output_address (XEXP (x, 0)); | |
5149 | return; | |
5150 | ||
ab835497 RK |
5151 | case 0: |
5152 | /* Do nothing special. */ | |
5153 | break; | |
5154 | ||
5155 | default: | |
5156 | /* Undocumented flag. */ | |
415f583e | 5157 | output_operand_lossage ("invalid operand output code"); |
ab835497 RK |
5158 | } |
5159 | ||
5160 | if (GET_CODE (x) == REG) | |
5161 | fputs (reg_names[REGNO (x)], file); | |
5162 | else if (GET_CODE (x) == MEM) | |
5163 | { | |
5164 | fputc ('[', file); | |
ab835497 | 5165 | /* Poor Sun assembler doesn't understand absolute addressing. */ |
c4ce6853 DE |
5166 | if (CONSTANT_P (XEXP (x, 0)) |
5167 | && ! TARGET_LIVE_G0) | |
ab835497 RK |
5168 | fputs ("%g0+", file); |
5169 | output_address (XEXP (x, 0)); | |
5170 | fputc (']', file); | |
5171 | } | |
5172 | else if (GET_CODE (x) == HIGH) | |
5173 | { | |
5174 | fputs ("%hi(", file); | |
5175 | output_addr_const (file, XEXP (x, 0)); | |
5176 | fputc (')', file); | |
5177 | } | |
5178 | else if (GET_CODE (x) == LO_SUM) | |
5179 | { | |
5180 | print_operand (file, XEXP (x, 0), 0); | |
e0d80184 DM |
5181 | if (TARGET_CM_MEDMID) |
5182 | fputs ("+%l44(", file); | |
5183 | else | |
5184 | fputs ("+%lo(", file); | |
ab835497 RK |
5185 | output_addr_const (file, XEXP (x, 1)); |
5186 | fputc (')', file); | |
5187 | } | |
e601abce JW |
5188 | else if (GET_CODE (x) == CONST_DOUBLE |
5189 | && (GET_MODE (x) == VOIDmode | |
5190 | || GET_MODE_CLASS (GET_MODE (x)) == MODE_INT)) | |
ab835497 RK |
5191 | { |
5192 | if (CONST_DOUBLE_HIGH (x) == 0) | |
5193 | fprintf (file, "%u", CONST_DOUBLE_LOW (x)); | |
5194 | else if (CONST_DOUBLE_HIGH (x) == -1 | |
5195 | && CONST_DOUBLE_LOW (x) < 0) | |
5196 | fprintf (file, "%d", CONST_DOUBLE_LOW (x)); | |
5197 | else | |
e601abce | 5198 | output_operand_lossage ("long long constant not a valid immediate operand"); |
ab835497 | 5199 | } |
e601abce JW |
5200 | else if (GET_CODE (x) == CONST_DOUBLE) |
5201 | output_operand_lossage ("floating point constant not a valid immediate operand"); | |
ab835497 RK |
5202 | else { output_addr_const (file, x); } |
5203 | } | |
5204 | \f | |
5205 | /* This function outputs assembler code for VALUE to FILE, where VALUE is | |
5206 | a 64 bit (DImode) value. */ | |
5207 | ||
5208 | /* ??? If there is a 64 bit counterpart to .word that the assembler | |
5209 | understands, then using that would simply this code greatly. */ | |
61a55e8b DE |
5210 | /* ??? We only output .xword's for symbols and only then in environments |
5211 | where the assembler can handle them. */ | |
ab835497 RK |
5212 | |
5213 | void | |
5214 | output_double_int (file, value) | |
5215 | FILE *file; | |
5216 | rtx value; | |
5217 | { | |
5218 | if (GET_CODE (value) == CONST_INT) | |
5219 | { | |
f4f8e370 DE |
5220 | /* ??? This has endianness issues. */ |
5221 | #if HOST_BITS_PER_WIDE_INT == 64 | |
5222 | HOST_WIDE_INT xword = INTVAL (value); | |
5223 | HOST_WIDE_INT high, low; | |
5224 | ||
5225 | high = (xword >> 32) & 0xffffffff; | |
5226 | low = xword & 0xffffffff; | |
3a598fbe JL |
5227 | ASM_OUTPUT_INT (file, GEN_INT (high)); |
5228 | ASM_OUTPUT_INT (file, GEN_INT (low)); | |
f4f8e370 | 5229 | #else |
ab835497 RK |
5230 | if (INTVAL (value) < 0) |
5231 | ASM_OUTPUT_INT (file, constm1_rtx); | |
5232 | else | |
5233 | ASM_OUTPUT_INT (file, const0_rtx); | |
5234 | ASM_OUTPUT_INT (file, value); | |
f4f8e370 | 5235 | #endif |
ab835497 RK |
5236 | } |
5237 | else if (GET_CODE (value) == CONST_DOUBLE) | |
5238 | { | |
3a598fbe JL |
5239 | ASM_OUTPUT_INT (file, GEN_INT (CONST_DOUBLE_HIGH (value))); |
5240 | ASM_OUTPUT_INT (file, GEN_INT (CONST_DOUBLE_LOW (value))); | |
ab835497 RK |
5241 | } |
5242 | else if (GET_CODE (value) == SYMBOL_REF | |
5243 | || GET_CODE (value) == CONST | |
61a55e8b | 5244 | || GET_CODE (value) == PLUS |
a9e27770 | 5245 | || (TARGET_ARCH64 && |
61a55e8b | 5246 | (GET_CODE (value) == LABEL_REF |
9fa9626b | 5247 | || GET_CODE (value) == CODE_LABEL |
61a55e8b | 5248 | || GET_CODE (value) == MINUS))) |
ab835497 | 5249 | { |
f3b8847b | 5250 | if (! TARGET_V9) |
61a55e8b DE |
5251 | { |
5252 | ASM_OUTPUT_INT (file, const0_rtx); | |
5253 | ASM_OUTPUT_INT (file, value); | |
5254 | } | |
5255 | else | |
5256 | { | |
5257 | fprintf (file, "\t%s\t", ASM_LONGLONG); | |
5258 | output_addr_const (file, value); | |
5259 | fprintf (file, "\n"); | |
5260 | } | |
ab835497 RK |
5261 | } |
5262 | else | |
5263 | abort (); | |
5264 | } | |
210aa14a | 5265 | \f |
b0468b84 RK |
5266 | /* Return the value of a code used in the .proc pseudo-op that says |
5267 | what kind of result this function returns. For non-C types, we pick | |
5268 | the closest C type. */ | |
5269 | ||
77a02b01 JW |
5270 | #ifndef CHAR_TYPE_SIZE |
5271 | #define CHAR_TYPE_SIZE BITS_PER_UNIT | |
5272 | #endif | |
5273 | ||
5274 | #ifndef SHORT_TYPE_SIZE | |
5275 | #define SHORT_TYPE_SIZE (BITS_PER_UNIT * 2) | |
5276 | #endif | |
5277 | ||
5278 | #ifndef INT_TYPE_SIZE | |
5279 | #define INT_TYPE_SIZE BITS_PER_WORD | |
5280 | #endif | |
5281 | ||
5282 | #ifndef LONG_TYPE_SIZE | |
5283 | #define LONG_TYPE_SIZE BITS_PER_WORD | |
5284 | #endif | |
5285 | ||
5286 | #ifndef LONG_LONG_TYPE_SIZE | |
5287 | #define LONG_LONG_TYPE_SIZE (BITS_PER_WORD * 2) | |
5288 | #endif | |
5289 | ||
5290 | #ifndef FLOAT_TYPE_SIZE | |
5291 | #define FLOAT_TYPE_SIZE BITS_PER_WORD | |
5292 | #endif | |
5293 | ||
5294 | #ifndef DOUBLE_TYPE_SIZE | |
5295 | #define DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2) | |
5296 | #endif | |
5297 | ||
5298 | #ifndef LONG_DOUBLE_TYPE_SIZE | |
5299 | #define LONG_DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2) | |
5300 | #endif | |
210aa14a RS |
5301 | |
5302 | unsigned long | |
5303 | sparc_type_code (type) | |
5304 | register tree type; | |
5305 | { | |
5306 | register unsigned long qualifiers = 0; | |
e5e809f4 | 5307 | register unsigned shift; |
210aa14a | 5308 | |
abc95ed3 | 5309 | /* Only the first 30 bits of the qualifier are valid. We must refrain from |
aee2c3c5 JW |
5310 | setting more, since some assemblers will give an error for this. Also, |
5311 | we must be careful to avoid shifts of 32 bits or more to avoid getting | |
5312 | unpredictable results. */ | |
5313 | ||
e5e809f4 | 5314 | for (shift = 6; shift < 30; shift += 2, type = TREE_TYPE (type)) |
210aa14a RS |
5315 | { |
5316 | switch (TREE_CODE (type)) | |
5317 | { | |
5318 | case ERROR_MARK: | |
5319 | return qualifiers; | |
5320 | ||
5321 | case ARRAY_TYPE: | |
e5e809f4 | 5322 | qualifiers |= (3 << shift); |
210aa14a RS |
5323 | break; |
5324 | ||
5325 | case FUNCTION_TYPE: | |
5326 | case METHOD_TYPE: | |
e5e809f4 | 5327 | qualifiers |= (2 << shift); |
210aa14a RS |
5328 | break; |
5329 | ||
5330 | case POINTER_TYPE: | |
5331 | case REFERENCE_TYPE: | |
5332 | case OFFSET_TYPE: | |
e5e809f4 | 5333 | qualifiers |= (1 << shift); |
210aa14a | 5334 | break; |
ab835497 | 5335 | |
210aa14a RS |
5336 | case RECORD_TYPE: |
5337 | return (qualifiers | 8); | |
5338 | ||
5339 | case UNION_TYPE: | |
b0468b84 | 5340 | case QUAL_UNION_TYPE: |
210aa14a RS |
5341 | return (qualifiers | 9); |
5342 | ||
5343 | case ENUMERAL_TYPE: | |
5344 | return (qualifiers | 10); | |
5345 | ||
5346 | case VOID_TYPE: | |
5347 | return (qualifiers | 16); | |
5348 | ||
5349 | case INTEGER_TYPE: | |
654209e6 JW |
5350 | /* If this is a range type, consider it to be the underlying |
5351 | type. */ | |
5352 | if (TREE_TYPE (type) != 0) | |
e5e809f4 | 5353 | break; |
654209e6 | 5354 | |
77a02b01 | 5355 | /* Carefully distinguish all the standard types of C, |
b0468b84 RK |
5356 | without messing up if the language is not C. We do this by |
5357 | testing TYPE_PRECISION and TREE_UNSIGNED. The old code used to | |
5358 | look at both the names and the above fields, but that's redundant. | |
5359 | Any type whose size is between two C types will be considered | |
5360 | to be the wider of the two types. Also, we do not have a | |
5361 | special code to use for "long long", so anything wider than | |
5362 | long is treated the same. Note that we can't distinguish | |
5363 | between "int" and "long" in this code if they are the same | |
5364 | size, but that's fine, since neither can the assembler. */ | |
5365 | ||
5366 | if (TYPE_PRECISION (type) <= CHAR_TYPE_SIZE) | |
5367 | return (qualifiers | (TREE_UNSIGNED (type) ? 12 : 2)); | |
77a02b01 | 5368 | |
b0468b84 RK |
5369 | else if (TYPE_PRECISION (type) <= SHORT_TYPE_SIZE) |
5370 | return (qualifiers | (TREE_UNSIGNED (type) ? 13 : 3)); | |
77a02b01 | 5371 | |
b0468b84 | 5372 | else if (TYPE_PRECISION (type) <= INT_TYPE_SIZE) |
77a02b01 JW |
5373 | return (qualifiers | (TREE_UNSIGNED (type) ? 14 : 4)); |
5374 | ||
b0468b84 | 5375 | else |
77a02b01 JW |
5376 | return (qualifiers | (TREE_UNSIGNED (type) ? 15 : 5)); |
5377 | ||
210aa14a | 5378 | case REAL_TYPE: |
e5e809f4 JL |
5379 | /* If this is a range type, consider it to be the underlying |
5380 | type. */ | |
5381 | if (TREE_TYPE (type) != 0) | |
5382 | break; | |
5383 | ||
77a02b01 JW |
5384 | /* Carefully distinguish all the standard types of C, |
5385 | without messing up if the language is not C. */ | |
b0468b84 | 5386 | |
77a02b01 | 5387 | if (TYPE_PRECISION (type) == FLOAT_TYPE_SIZE) |
210aa14a | 5388 | return (qualifiers | 6); |
b0468b84 RK |
5389 | |
5390 | else | |
5391 | return (qualifiers | 7); | |
210aa14a RS |
5392 | |
5393 | case COMPLEX_TYPE: /* GNU Fortran COMPLEX type. */ | |
13d39dbc | 5394 | /* ??? We need to distinguish between double and float complex types, |
c82aa69a JW |
5395 | but I don't know how yet because I can't reach this code from |
5396 | existing front-ends. */ | |
5397 | return (qualifiers | 7); /* Who knows? */ | |
5398 | ||
210aa14a RS |
5399 | case CHAR_TYPE: /* GNU Pascal CHAR type. Not used in C. */ |
5400 | case BOOLEAN_TYPE: /* GNU Fortran BOOLEAN type. */ | |
5401 | case FILE_TYPE: /* GNU Pascal FILE type. */ | |
26902ae0 | 5402 | case SET_TYPE: /* GNU Pascal SET type. */ |
210aa14a | 5403 | case LANG_TYPE: /* ? */ |
26902ae0 | 5404 | return qualifiers; |
210aa14a RS |
5405 | |
5406 | default: | |
5407 | abort (); /* Not a type! */ | |
5408 | } | |
5409 | } | |
e5e809f4 JL |
5410 | |
5411 | return qualifiers; | |
210aa14a | 5412 | } |
ead69aea | 5413 | \f |
61a55e8b DE |
5414 | /* Nested function support. */ |
5415 | ||
5416 | /* Emit RTL insns to initialize the variable parts of a trampoline. | |
5417 | FNADDR is an RTX for the address of the function's pure code. | |
5418 | CXT is an RTX for the static chain value for the function. | |
5419 | ||
5420 | This takes 16 insns: 2 shifts & 2 ands (to split up addresses), 4 sethi | |
5421 | (to load in opcodes), 4 iors (to merge address and opcodes), and 4 writes | |
5422 | (to store insns). This is a bit excessive. Perhaps a different | |
5423 | mechanism would be better here. | |
5424 | ||
849a528d | 5425 | Emit enough FLUSH insns to synchronize the data and instruction caches. */ |
61a55e8b DE |
5426 | |
5427 | void | |
5428 | sparc_initialize_trampoline (tramp, fnaddr, cxt) | |
5429 | rtx tramp, fnaddr, cxt; | |
5430 | { | |
c6b0465b JC |
5431 | /* SPARC 32 bit trampoline: |
5432 | ||
e0d80184 DM |
5433 | sethi %hi(fn), %g1 |
5434 | sethi %hi(static), %g2 | |
5435 | jmp %g1+%lo(fn) | |
5436 | or %g2, %lo(static), %g2 | |
c6b0465b JC |
5437 | |
5438 | SETHI i,r = 00rr rrr1 00ii iiii iiii iiii iiii iiii | |
5439 | JMPL r+i,d = 10dd ddd1 1100 0rrr rr1i iiii iiii iiii | |
5440 | */ | |
959eb758 DM |
5441 | #ifdef TRANSFER_FROM_TRAMPOLINE |
5442 | emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "__enable_execute_stack"), | |
5443 | 0, VOIDmode, 1, tramp, Pmode); | |
5444 | #endif | |
c6b0465b JC |
5445 | |
5446 | emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 0)), | |
5447 | expand_binop (SImode, ior_optab, | |
5448 | expand_shift (RSHIFT_EXPR, SImode, fnaddr, | |
5449 | size_int (10), 0, 1), | |
5450 | GEN_INT (0x03000000), | |
5451 | NULL_RTX, 1, OPTAB_DIRECT)); | |
5452 | ||
5453 | emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 4)), | |
5454 | expand_binop (SImode, ior_optab, | |
5455 | expand_shift (RSHIFT_EXPR, SImode, cxt, | |
5456 | size_int (10), 0, 1), | |
5457 | GEN_INT (0x05000000), | |
5458 | NULL_RTX, 1, OPTAB_DIRECT)); | |
5459 | ||
5460 | emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 8)), | |
5461 | expand_binop (SImode, ior_optab, | |
5462 | expand_and (fnaddr, GEN_INT (0x3ff), NULL_RTX), | |
5463 | GEN_INT (0x81c06000), | |
5464 | NULL_RTX, 1, OPTAB_DIRECT)); | |
5465 | ||
5466 | emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 12)), | |
5467 | expand_binop (SImode, ior_optab, | |
5468 | expand_and (cxt, GEN_INT (0x3ff), NULL_RTX), | |
5469 | GEN_INT (0x8410a000), | |
5470 | NULL_RTX, 1, OPTAB_DIRECT)); | |
5471 | ||
254110c2 | 5472 | emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode, tramp)))); |
c6b0465b JC |
5473 | /* On UltraSPARC a flush flushes an entire cache line. The trampoline is |
5474 | aligned on a 16 byte boundary so one flush clears it all. */ | |
5475 | if (sparc_cpu != PROCESSOR_ULTRASPARC) | |
5476 | emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode, | |
5477 | plus_constant (tramp, 8))))); | |
61a55e8b DE |
5478 | } |
5479 | ||
849a528d RK |
5480 | /* The 64 bit version is simpler because it makes more sense to load the |
5481 | values as "immediate" data out of the trampoline. It's also easier since | |
5482 | we can read the PC without clobbering a register. */ | |
5483 | ||
61a55e8b DE |
5484 | void |
5485 | sparc64_initialize_trampoline (tramp, fnaddr, cxt) | |
5486 | rtx tramp, fnaddr, cxt; | |
5487 | { | |
345a6161 DM |
5488 | #ifdef TRANSFER_FROM_TRAMPOLINE |
5489 | emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "__enable_execute_stack"), | |
5490 | 0, VOIDmode, 1, tramp, Pmode); | |
5491 | #endif | |
5492 | ||
c6b0465b | 5493 | /* |
e0d80184 DM |
5494 | rd %pc, %g1 |
5495 | ldx [%g1+24], %g5 | |
5496 | jmp %g5 | |
5497 | ldx [%g1+16], %g5 | |
c6b0465b JC |
5498 | +16 bytes data |
5499 | */ | |
5500 | ||
5501 | emit_move_insn (gen_rtx_MEM (SImode, tramp), | |
5502 | GEN_INT (0x83414000)); | |
5503 | emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 4)), | |
5504 | GEN_INT (0xca586018)); | |
5505 | emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 8)), | |
345a6161 | 5506 | GEN_INT (0x81c14000)); |
c6b0465b JC |
5507 | emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 12)), |
5508 | GEN_INT (0xca586010)); | |
5509 | emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 16)), cxt); | |
345a6161 | 5510 | emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 24)), fnaddr); |
254110c2 | 5511 | emit_insn (gen_flush (validize_mem (gen_rtx_MEM (DImode, tramp)))); |
345a6161 | 5512 | |
c6b0465b JC |
5513 | if (sparc_cpu != PROCESSOR_ULTRASPARC) |
5514 | emit_insn (gen_flush (validize_mem (gen_rtx_MEM (DImode, plus_constant (tramp, 8))))); | |
61a55e8b DE |
5515 | } |
5516 | \f | |
c819be5b JW |
5517 | /* Subroutines to support a flat (single) register window calling |
5518 | convention. */ | |
5519 | ||
5520 | /* Single-register window sparc stack frames look like: | |
5521 | ||
5522 | Before call After call | |
5523 | +-----------------------+ +-----------------------+ | |
86735b02 DE |
5524 | high | | | | |
5525 | mem | caller's temps. | | caller's temps. | | |
c819be5b JW |
5526 | | | | | |
5527 | +-----------------------+ +-----------------------+ | |
5528 | | | | | | |
5529 | | arguments on stack. | | arguments on stack. | | |
86735b02 DE |
5530 | | | | | |
5531 | +-----------------------+FP+92->+-----------------------+ | |
c819be5b JW |
5532 | | 6 words to save | | 6 words to save | |
5533 | | arguments passed | | arguments passed | | |
5534 | | in registers, even | | in registers, even | | |
86735b02 DE |
5535 | | if not passed. | | if not passed. | |
5536 | SP+68->+-----------------------+FP+68->+-----------------------+ | |
5537 | | 1 word struct addr | | 1 word struct addr | | |
5538 | +-----------------------+FP+64->+-----------------------+ | |
5539 | | | | | | |
5540 | | 16 word reg save area | | 16 word reg save area | | |
5541 | | | | | | |
5542 | SP->+-----------------------+ FP->+-----------------------+ | |
5543 | | 4 word area for | | |
5544 | | fp/alu reg moves | | |
5545 | FP-16->+-----------------------+ | |
5546 | | | | |
5547 | | local variables | | |
5548 | | | | |
5549 | +-----------------------+ | |
5550 | | | | |
c819be5b | 5551 | | fp register save | |
86735b02 DE |
5552 | | | |
5553 | +-----------------------+ | |
5554 | | | | |
c819be5b JW |
5555 | | gp register save | |
5556 | | | | |
86735b02 DE |
5557 | +-----------------------+ |
5558 | | | | |
c819be5b | 5559 | | alloca allocations | |
86735b02 DE |
5560 | | | |
5561 | +-----------------------+ | |
5562 | | | | |
c819be5b | 5563 | | arguments on stack | |
86735b02 DE |
5564 | | | |
5565 | SP+92->+-----------------------+ | |
c819be5b | 5566 | | 6 words to save | |
86735b02 | 5567 | | arguments passed | |
c819be5b | 5568 | | in registers, even | |
86735b02 DE |
5569 | low | if not passed. | |
5570 | memory SP+68->+-----------------------+ | |
5571 | | 1 word struct addr | | |
5572 | SP+64->+-----------------------+ | |
5573 | | | | |
5574 | I 16 word reg save area | | |
5575 | | | | |
5576 | SP->+-----------------------+ */ | |
c819be5b | 5577 | |
c6aa9ce1 | 5578 | /* Structure to be filled in by sparc_flat_compute_frame_size with register |
c819be5b JW |
5579 | save masks, and offsets for the current function. */ |
5580 | ||
5581 | struct sparc_frame_info | |
5582 | { | |
5583 | unsigned long total_size; /* # bytes that the entire frame takes up. */ | |
5584 | unsigned long var_size; /* # bytes that variables take up. */ | |
5585 | unsigned long args_size; /* # bytes that outgoing arguments take up. */ | |
5586 | unsigned long extra_size; /* # bytes of extra gunk. */ | |
5587 | unsigned int gp_reg_size; /* # bytes needed to store gp regs. */ | |
5588 | unsigned int fp_reg_size; /* # bytes needed to store fp regs. */ | |
86735b02 | 5589 | unsigned long gmask; /* Mask of saved gp registers. */ |
c819be5b | 5590 | unsigned long fmask; /* Mask of saved fp registers. */ |
86735b02 | 5591 | unsigned long reg_offset; /* Offset from new sp to store regs. */ |
c819be5b JW |
5592 | int initialized; /* Nonzero if frame size already calculated. */ |
5593 | }; | |
5594 | ||
c6aa9ce1 | 5595 | /* Current frame information calculated by sparc_flat_compute_frame_size. */ |
c819be5b JW |
5596 | struct sparc_frame_info current_frame_info; |
5597 | ||
5598 | /* Zero structure to initialize current_frame_info. */ | |
5599 | struct sparc_frame_info zero_frame_info; | |
5600 | ||
5601 | /* Tell prologue and epilogue if register REGNO should be saved / restored. */ | |
5602 | ||
86735b02 DE |
5603 | #define RETURN_ADDR_REGNUM 15 |
5604 | #define FRAME_POINTER_MASK (1 << (FRAME_POINTER_REGNUM)) | |
5605 | #define RETURN_ADDR_MASK (1 << (RETURN_ADDR_REGNUM)) | |
5606 | ||
c819be5b JW |
5607 | #define MUST_SAVE_REGISTER(regno) \ |
5608 | ((regs_ever_live[regno] && !call_used_regs[regno]) \ | |
5609 | || (regno == FRAME_POINTER_REGNUM && frame_pointer_needed) \ | |
86735b02 | 5610 | || (regno == RETURN_ADDR_REGNUM && regs_ever_live[RETURN_ADDR_REGNUM])) |
c819be5b JW |
5611 | |
5612 | /* Return the bytes needed to compute the frame pointer from the current | |
5613 | stack pointer. */ | |
5614 | ||
5615 | unsigned long | |
c6aa9ce1 | 5616 | sparc_flat_compute_frame_size (size) |
c819be5b JW |
5617 | int size; /* # of var. bytes allocated. */ |
5618 | { | |
5619 | int regno; | |
5620 | unsigned long total_size; /* # bytes that the entire frame takes up. */ | |
5621 | unsigned long var_size; /* # bytes that variables take up. */ | |
5622 | unsigned long args_size; /* # bytes that outgoing arguments take up. */ | |
5623 | unsigned long extra_size; /* # extra bytes. */ | |
5624 | unsigned int gp_reg_size; /* # bytes needed to store gp regs. */ | |
5625 | unsigned int fp_reg_size; /* # bytes needed to store fp regs. */ | |
86735b02 | 5626 | unsigned long gmask; /* Mask of saved gp registers. */ |
c819be5b | 5627 | unsigned long fmask; /* Mask of saved fp registers. */ |
86735b02 DE |
5628 | unsigned long reg_offset; /* Offset to register save area. */ |
5629 | int need_aligned_p; /* 1 if need the save area 8 byte aligned. */ | |
c819be5b JW |
5630 | |
5631 | /* This is the size of the 16 word reg save area, 1 word struct addr | |
5632 | area, and 4 word fp/alu register copy area. */ | |
5633 | extra_size = -STARTING_FRAME_OFFSET + FIRST_PARM_OFFSET(0); | |
5634 | var_size = size; | |
5635 | /* Also include the size needed for the 6 parameter registers. */ | |
5636 | args_size = current_function_outgoing_args_size + 24; | |
5637 | total_size = var_size + args_size + extra_size; | |
5638 | gp_reg_size = 0; | |
5639 | fp_reg_size = 0; | |
86735b02 | 5640 | gmask = 0; |
c819be5b | 5641 | fmask = 0; |
86735b02 DE |
5642 | reg_offset = 0; |
5643 | need_aligned_p = 0; | |
c819be5b JW |
5644 | |
5645 | /* Calculate space needed for gp registers. */ | |
5646 | for (regno = 1; regno <= 31; regno++) | |
5647 | { | |
5648 | if (MUST_SAVE_REGISTER (regno)) | |
5649 | { | |
86735b02 DE |
5650 | /* If we need to save two regs in a row, ensure there's room to bump |
5651 | up the address to align it to a doubleword boundary. */ | |
c819be5b JW |
5652 | if ((regno & 0x1) == 0 && MUST_SAVE_REGISTER (regno+1)) |
5653 | { | |
5654 | if (gp_reg_size % 8 != 0) | |
86735b02 | 5655 | gp_reg_size += 4; |
c819be5b | 5656 | gp_reg_size += 2 * UNITS_PER_WORD; |
86735b02 | 5657 | gmask |= 3 << regno; |
c819be5b | 5658 | regno++; |
86735b02 | 5659 | need_aligned_p = 1; |
c819be5b JW |
5660 | } |
5661 | else | |
5662 | { | |
5663 | gp_reg_size += UNITS_PER_WORD; | |
86735b02 | 5664 | gmask |= 1 << regno; |
c819be5b JW |
5665 | } |
5666 | } | |
5667 | } | |
c819be5b JW |
5668 | |
5669 | /* Calculate space needed for fp registers. */ | |
5670 | for (regno = 32; regno <= 63; regno++) | |
5671 | { | |
5672 | if (regs_ever_live[regno] && !call_used_regs[regno]) | |
5673 | { | |
5674 | fp_reg_size += UNITS_PER_WORD; | |
5675 | fmask |= 1 << (regno - 32); | |
5676 | } | |
5677 | } | |
5678 | ||
86735b02 DE |
5679 | if (gmask || fmask) |
5680 | { | |
5681 | int n; | |
5682 | reg_offset = FIRST_PARM_OFFSET(0) + args_size; | |
5683 | /* Ensure save area is 8 byte aligned if we need it. */ | |
5684 | n = reg_offset % 8; | |
5685 | if (need_aligned_p && n != 0) | |
5686 | { | |
5687 | total_size += 8 - n; | |
5688 | reg_offset += 8 - n; | |
5689 | } | |
5690 | total_size += gp_reg_size + fp_reg_size; | |
5691 | } | |
c819be5b | 5692 | |
86735b02 | 5693 | /* ??? This looks a little suspicious. Clarify. */ |
c819be5b JW |
5694 | if (total_size == extra_size) |
5695 | total_size = extra_size = 0; | |
5696 | ||
5697 | total_size = SPARC_STACK_ALIGN (total_size); | |
5698 | ||
5699 | /* Save other computed information. */ | |
5700 | current_frame_info.total_size = total_size; | |
5701 | current_frame_info.var_size = var_size; | |
5702 | current_frame_info.args_size = args_size; | |
5703 | current_frame_info.extra_size = extra_size; | |
5704 | current_frame_info.gp_reg_size = gp_reg_size; | |
5705 | current_frame_info.fp_reg_size = fp_reg_size; | |
86735b02 | 5706 | current_frame_info.gmask = gmask; |
c819be5b | 5707 | current_frame_info.fmask = fmask; |
86735b02 | 5708 | current_frame_info.reg_offset = reg_offset; |
c819be5b JW |
5709 | current_frame_info.initialized = reload_completed; |
5710 | ||
c819be5b JW |
5711 | /* Ok, we're done. */ |
5712 | return total_size; | |
5713 | } | |
5714 | \f | |
86735b02 DE |
5715 | /* Save/restore registers in GMASK and FMASK at register BASE_REG plus offset |
5716 | OFFSET. | |
5717 | ||
5718 | BASE_REG must be 8 byte aligned. This allows us to test OFFSET for | |
5719 | appropriate alignment and use DOUBLEWORD_OP when we can. We assume | |
5720 | [BASE_REG+OFFSET] will always be a valid address. | |
5721 | ||
5722 | WORD_OP is either "st" for save, "ld" for restore. | |
5723 | DOUBLEWORD_OP is either "std" for save, "ldd" for restore. */ | |
c819be5b JW |
5724 | |
5725 | void | |
96987e96 DE |
5726 | sparc_flat_save_restore (file, base_reg, offset, gmask, fmask, word_op, |
5727 | doubleword_op, base_offset) | |
86735b02 DE |
5728 | FILE *file; |
5729 | char *base_reg; | |
5730 | unsigned int offset; | |
5731 | unsigned long gmask; | |
5732 | unsigned long fmask; | |
5733 | char *word_op; | |
5734 | char *doubleword_op; | |
c53aa195 | 5735 | unsigned long base_offset; |
c819be5b JW |
5736 | { |
5737 | int regno; | |
c819be5b | 5738 | |
86735b02 DE |
5739 | if (gmask == 0 && fmask == 0) |
5740 | return; | |
c819be5b | 5741 | |
86735b02 DE |
5742 | /* Save registers starting from high to low. We've already saved the |
5743 | previous frame pointer and previous return address for the debugger's | |
5744 | sake. The debugger allows us to not need a nop in the epilog if at least | |
5745 | one register is reloaded in addition to return address. */ | |
c819be5b | 5746 | |
86735b02 | 5747 | if (gmask) |
c819be5b JW |
5748 | { |
5749 | for (regno = 1; regno <= 31; regno++) | |
5750 | { | |
86735b02 | 5751 | if ((gmask & (1L << regno)) != 0) |
c819be5b | 5752 | { |
86735b02 | 5753 | if ((regno & 0x1) == 0 && ((gmask & (1L << (regno+1))) != 0)) |
c819be5b | 5754 | { |
86735b02 DE |
5755 | /* We can save two registers in a row. If we're not at a |
5756 | double word boundary, move to one. | |
5757 | sparc_flat_compute_frame_size ensures there's room to do | |
5758 | this. */ | |
5759 | if (offset % 8 != 0) | |
5760 | offset += UNITS_PER_WORD; | |
5761 | ||
c819be5b | 5762 | if (word_op[0] == 's') |
c53aa195 | 5763 | { |
e0d80184 | 5764 | fprintf (file, "\t%s\t%s, [%s+%d]\n", |
c53aa195 JM |
5765 | doubleword_op, reg_names[regno], |
5766 | base_reg, offset); | |
0021b564 | 5767 | if (dwarf2out_do_frame ()) |
c53aa195 | 5768 | { |
96987e96 | 5769 | char *l = dwarf2out_cfi_label (); |
c53aa195 JM |
5770 | dwarf2out_reg_save (l, regno, offset + base_offset); |
5771 | dwarf2out_reg_save | |
5772 | (l, regno+1, offset+base_offset + UNITS_PER_WORD); | |
5773 | } | |
c53aa195 | 5774 | } |
c819be5b | 5775 | else |
e0d80184 | 5776 | fprintf (file, "\t%s\t[%s+%d], %s\n", |
86735b02 | 5777 | doubleword_op, base_reg, offset, |
c819be5b JW |
5778 | reg_names[regno]); |
5779 | ||
86735b02 | 5780 | offset += 2 * UNITS_PER_WORD; |
c819be5b JW |
5781 | regno++; |
5782 | } | |
5783 | else | |
5784 | { | |
5785 | if (word_op[0] == 's') | |
c53aa195 | 5786 | { |
e0d80184 | 5787 | fprintf (file, "\t%s\t%s, [%s+%d]\n", |
c53aa195 JM |
5788 | word_op, reg_names[regno], |
5789 | base_reg, offset); | |
0021b564 | 5790 | if (dwarf2out_do_frame ()) |
c53aa195 | 5791 | dwarf2out_reg_save ("", regno, offset + base_offset); |
c53aa195 | 5792 | } |
c819be5b | 5793 | else |
e0d80184 | 5794 | fprintf (file, "\t%s\t[%s+%d], %s\n", |
86735b02 | 5795 | word_op, base_reg, offset, reg_names[regno]); |
c819be5b | 5796 | |
86735b02 | 5797 | offset += UNITS_PER_WORD; |
c819be5b JW |
5798 | } |
5799 | } | |
5800 | } | |
5801 | } | |
5802 | ||
5803 | if (fmask) | |
5804 | { | |
5805 | for (regno = 32; regno <= 63; regno++) | |
5806 | { | |
5807 | if ((fmask & (1L << (regno - 32))) != 0) | |
5808 | { | |
5809 | if (word_op[0] == 's') | |
c53aa195 | 5810 | { |
e0d80184 | 5811 | fprintf (file, "\t%s\t%s, [%s+%d]\n", |
c53aa195 JM |
5812 | word_op, reg_names[regno], |
5813 | base_reg, offset); | |
0021b564 | 5814 | if (dwarf2out_do_frame ()) |
c53aa195 | 5815 | dwarf2out_reg_save ("", regno, offset + base_offset); |
c53aa195 | 5816 | } |
c819be5b | 5817 | else |
e0d80184 | 5818 | fprintf (file, "\t%s\t[%s+%d], %s\n", |
86735b02 | 5819 | word_op, base_reg, offset, reg_names[regno]); |
c819be5b | 5820 | |
86735b02 | 5821 | offset += UNITS_PER_WORD; |
c819be5b JW |
5822 | } |
5823 | } | |
5824 | } | |
5825 | } | |
5826 | \f | |
5827 | /* Set up the stack and frame (if desired) for the function. */ | |
5828 | ||
5829 | void | |
c6aa9ce1 | 5830 | sparc_flat_output_function_prologue (file, size) |
c819be5b JW |
5831 | FILE *file; |
5832 | int size; | |
5833 | { | |
c819be5b | 5834 | char *sp_str = reg_names[STACK_POINTER_REGNUM]; |
86735b02 | 5835 | unsigned long gmask = current_frame_info.gmask; |
a07c1915 | 5836 | |
c6aa9ce1 | 5837 | /* This is only for the human reader. */ |
bf62bbf1 | 5838 | fprintf (file, "\t%s#PROLOGUE# 0\n", ASM_COMMENT_START); |
5e9defae | 5839 | fprintf (file, "\t%s# vars= %ld, regs= %d/%d, args= %d, extra= %ld\n", |
bf62bbf1 | 5840 | ASM_COMMENT_START, |
86735b02 DE |
5841 | current_frame_info.var_size, |
5842 | current_frame_info.gp_reg_size / 4, | |
9f8b85b8 | 5843 | current_frame_info.fp_reg_size / 4, |
86735b02 DE |
5844 | current_function_outgoing_args_size, |
5845 | current_frame_info.extra_size); | |
c819be5b JW |
5846 | |
5847 | size = SPARC_STACK_ALIGN (size); | |
86735b02 DE |
5848 | size = (! current_frame_info.initialized |
5849 | ? sparc_flat_compute_frame_size (size) | |
5850 | : current_frame_info.total_size); | |
c819be5b | 5851 | |
86735b02 DE |
5852 | /* These cases shouldn't happen. Catch them now. */ |
5853 | if (size == 0 && (gmask || current_frame_info.fmask)) | |
5854 | abort (); | |
c819be5b | 5855 | |
86735b02 DE |
5856 | /* Allocate our stack frame by decrementing %sp. |
5857 | At present, the only algorithm gdb can use to determine if this is a | |
5858 | flat frame is if we always set %i7 if we set %sp. This can be optimized | |
5859 | in the future by putting in some sort of debugging information that says | |
5860 | this is a `flat' function. However, there is still the case of debugging | |
5861 | code without such debugging information (including cases where most fns | |
5862 | have such info, but there is one that doesn't). So, always do this now | |
5863 | so we don't get a lot of code out there that gdb can't handle. | |
5864 | If the frame pointer isn't needn't then that's ok - gdb won't be able to | |
5865 | distinguish us from a non-flat function but there won't (and shouldn't) | |
5866 | be any differences anyway. The return pc is saved (if necessary) right | |
5867 | after %i7 so gdb won't have to look too far to find it. */ | |
5868 | if (size > 0) | |
c819be5b | 5869 | { |
86735b02 | 5870 | unsigned int reg_offset = current_frame_info.reg_offset; |
c6aa9ce1 | 5871 | char *fp_str = reg_names[FRAME_POINTER_REGNUM]; |
86735b02 DE |
5872 | char *t1_str = "%g1"; |
5873 | ||
5874 | /* Things get a little tricky if local variables take up more than ~4096 | |
5875 | bytes and outgoing arguments take up more than ~4096 bytes. When that | |
5876 | happens, the register save area can't be accessed from either end of | |
5877 | the frame. Handle this by decrementing %sp to the start of the gp | |
5878 | register save area, save the regs, update %i7, and then set %sp to its | |
5879 | final value. Given that we only have one scratch register to play | |
5880 | with it is the cheapest solution, and it helps gdb out as it won't | |
5881 | slow down recognition of flat functions. | |
5882 | Don't change the order of insns emitted here without checking with | |
5883 | the gdb folk first. */ | |
5884 | ||
ddd5a7c1 | 5885 | /* Is the entire register save area offsettable from %sp? */ |
86735b02 DE |
5886 | if (reg_offset < 4096 - 64 * UNITS_PER_WORD) |
5887 | { | |
5888 | if (size <= 4096) | |
5889 | { | |
e0d80184 | 5890 | fprintf (file, "\tadd\t%s, %d, %s\n", |
86735b02 DE |
5891 | sp_str, -size, sp_str); |
5892 | if (gmask & FRAME_POINTER_MASK) | |
5893 | { | |
e0d80184 | 5894 | fprintf (file, "\tst\t%s, [%s+%d]\n", |
86735b02 | 5895 | fp_str, sp_str, reg_offset); |
e0d80184 | 5896 | fprintf (file, "\tsub\t%s, %d, %s\t%s# set up frame pointer\n", |
bf62bbf1 | 5897 | sp_str, -size, fp_str, ASM_COMMENT_START); |
86735b02 DE |
5898 | reg_offset += 4; |
5899 | } | |
5900 | } | |
5901 | else | |
5902 | { | |
e0d80184 | 5903 | fprintf (file, "\tset\t%d, %s\n\tsub\t%s, %s, %s\n", |
86735b02 DE |
5904 | size, t1_str, sp_str, t1_str, sp_str); |
5905 | if (gmask & FRAME_POINTER_MASK) | |
5906 | { | |
e0d80184 | 5907 | fprintf (file, "\tst\t%s, [%s+%d]\n", |
86735b02 | 5908 | fp_str, sp_str, reg_offset); |
e0d80184 | 5909 | fprintf (file, "\tadd\t%s, %s, %s\t%s# set up frame pointer\n", |
bf62bbf1 | 5910 | sp_str, t1_str, fp_str, ASM_COMMENT_START); |
86735b02 DE |
5911 | reg_offset += 4; |
5912 | } | |
5913 | } | |
0021b564 | 5914 | if (dwarf2out_do_frame ()) |
c53aa195 | 5915 | { |
96987e96 | 5916 | char *l = dwarf2out_cfi_label (); |
c53aa195 JM |
5917 | if (gmask & FRAME_POINTER_MASK) |
5918 | { | |
5919 | dwarf2out_reg_save (l, FRAME_POINTER_REGNUM, | |
5920 | reg_offset - 4 - size); | |
5921 | dwarf2out_def_cfa (l, FRAME_POINTER_REGNUM, 0); | |
5922 | } | |
5923 | else | |
5924 | dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, size); | |
5925 | } | |
86735b02 DE |
5926 | if (gmask & RETURN_ADDR_MASK) |
5927 | { | |
e0d80184 | 5928 | fprintf (file, "\tst\t%s, [%s+%d]\n", |
86735b02 | 5929 | reg_names[RETURN_ADDR_REGNUM], sp_str, reg_offset); |
0021b564 | 5930 | if (dwarf2out_do_frame ()) |
c53aa195 | 5931 | dwarf2out_return_save ("", reg_offset - size); |
86735b02 DE |
5932 | reg_offset += 4; |
5933 | } | |
5934 | sparc_flat_save_restore (file, sp_str, reg_offset, | |
5935 | gmask & ~(FRAME_POINTER_MASK | RETURN_ADDR_MASK), | |
5936 | current_frame_info.fmask, | |
84e884e9 | 5937 | "st", "std", -size); |
86735b02 | 5938 | } |
c819be5b | 5939 | else |
86735b02 DE |
5940 | { |
5941 | /* Subtract %sp in two steps, but make sure there is always a | |
5942 | 64 byte register save area, and %sp is properly aligned. */ | |
5943 | /* Amount to decrement %sp by, the first time. */ | |
5944 | unsigned int size1 = ((size - reg_offset + 64) + 15) & -16; | |
5945 | /* Offset to register save area from %sp. */ | |
5946 | unsigned int offset = size1 - (size - reg_offset); | |
5947 | ||
5948 | if (size1 <= 4096) | |
5949 | { | |
e0d80184 | 5950 | fprintf (file, "\tadd\t%s, %d, %s\n", |
86735b02 DE |
5951 | sp_str, -size1, sp_str); |
5952 | if (gmask & FRAME_POINTER_MASK) | |
5953 | { | |
e0d80184 | 5954 | fprintf (file, "\tst\t%s, [%s+%d]\n\tsub\t%s, %d, %s\t%s# set up frame pointer\n", |
bf62bbf1 DE |
5955 | fp_str, sp_str, offset, sp_str, -size1, fp_str, |
5956 | ASM_COMMENT_START); | |
86735b02 DE |
5957 | offset += 4; |
5958 | } | |
5959 | } | |
5960 | else | |
5961 | { | |
e0d80184 | 5962 | fprintf (file, "\tset\t%d, %s\n\tsub\t%s, %s, %s\n", |
86735b02 DE |
5963 | size1, t1_str, sp_str, t1_str, sp_str); |
5964 | if (gmask & FRAME_POINTER_MASK) | |
5965 | { | |
e0d80184 | 5966 | fprintf (file, "\tst\t%s, [%s+%d]\n\tadd\t%s, %s, %s\t%s# set up frame pointer\n", |
bf62bbf1 DE |
5967 | fp_str, sp_str, offset, sp_str, t1_str, fp_str, |
5968 | ASM_COMMENT_START); | |
86735b02 DE |
5969 | offset += 4; |
5970 | } | |
5971 | } | |
0021b564 | 5972 | if (dwarf2out_do_frame ()) |
c53aa195 | 5973 | { |
96987e96 | 5974 | char *l = dwarf2out_cfi_label (); |
c53aa195 JM |
5975 | if (gmask & FRAME_POINTER_MASK) |
5976 | { | |
5977 | dwarf2out_reg_save (l, FRAME_POINTER_REGNUM, | |
5978 | offset - 4 - size1); | |
5979 | dwarf2out_def_cfa (l, FRAME_POINTER_REGNUM, 0); | |
5980 | } | |
5981 | else | |
5982 | dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, size1); | |
5983 | } | |
86735b02 DE |
5984 | if (gmask & RETURN_ADDR_MASK) |
5985 | { | |
e0d80184 | 5986 | fprintf (file, "\tst\t%s, [%s+%d]\n", |
86735b02 | 5987 | reg_names[RETURN_ADDR_REGNUM], sp_str, offset); |
0021b564 | 5988 | if (dwarf2out_do_frame ()) |
c53aa195 JM |
5989 | /* offset - size1 == reg_offset - size |
5990 | if reg_offset were updated above like offset. */ | |
5991 | dwarf2out_return_save ("", offset - size1); | |
86735b02 DE |
5992 | offset += 4; |
5993 | } | |
5994 | sparc_flat_save_restore (file, sp_str, offset, | |
5995 | gmask & ~(FRAME_POINTER_MASK | RETURN_ADDR_MASK), | |
5996 | current_frame_info.fmask, | |
84e884e9 | 5997 | "st", "std", -size1); |
e0d80184 | 5998 | fprintf (file, "\tset\t%d, %s\n\tsub\t%s, %s, %s\n", |
86735b02 | 5999 | size - size1, t1_str, sp_str, t1_str, sp_str); |
0021b564 | 6000 | if (dwarf2out_do_frame ()) |
c53aa195 JM |
6001 | if (! (gmask & FRAME_POINTER_MASK)) |
6002 | dwarf2out_def_cfa ("", STACK_POINTER_REGNUM, size); | |
86735b02 | 6003 | } |
c819be5b | 6004 | } |
c6aa9ce1 | 6005 | |
bf62bbf1 | 6006 | fprintf (file, "\t%s#PROLOGUE# 1\n", ASM_COMMENT_START); |
c819be5b JW |
6007 | } |
6008 | \f | |
6009 | /* Do any necessary cleanup after a function to restore stack, frame, | |
6010 | and regs. */ | |
6011 | ||
6012 | void | |
c6aa9ce1 | 6013 | sparc_flat_output_function_epilogue (file, size) |
c819be5b JW |
6014 | FILE *file; |
6015 | int size; | |
6016 | { | |
c819be5b JW |
6017 | rtx epilogue_delay = current_function_epilogue_delay_list; |
6018 | int noepilogue = FALSE; | |
c819be5b | 6019 | |
c6aa9ce1 | 6020 | /* This is only for the human reader. */ |
bf62bbf1 | 6021 | fprintf (file, "\t%s#EPILOGUE#\n", ASM_COMMENT_START); |
c6aa9ce1 | 6022 | |
c819be5b JW |
6023 | /* The epilogue does not depend on any registers, but the stack |
6024 | registers, so we assume that if we have 1 pending nop, it can be | |
6025 | ignored, and 2 it must be filled (2 nops occur for integer | |
6026 | multiply and divide). */ | |
6027 | ||
6028 | size = SPARC_STACK_ALIGN (size); | |
86735b02 | 6029 | size = (!current_frame_info.initialized |
c6aa9ce1 | 6030 | ? sparc_flat_compute_frame_size (size) |
c819be5b JW |
6031 | : current_frame_info.total_size); |
6032 | ||
86735b02 | 6033 | if (size == 0 && epilogue_delay == 0) |
c819be5b JW |
6034 | { |
6035 | rtx insn = get_last_insn (); | |
6036 | ||
6037 | /* If the last insn was a BARRIER, we don't have to write any code | |
6038 | because a jump (aka return) was put there. */ | |
6039 | if (GET_CODE (insn) == NOTE) | |
6040 | insn = prev_nonnote_insn (insn); | |
6041 | if (insn && GET_CODE (insn) == BARRIER) | |
6042 | noepilogue = TRUE; | |
6043 | } | |
6044 | ||
6045 | if (!noepilogue) | |
6046 | { | |
86735b02 DE |
6047 | unsigned int reg_offset = current_frame_info.reg_offset; |
6048 | unsigned int size1; | |
6049 | char *sp_str = reg_names[STACK_POINTER_REGNUM]; | |
6050 | char *fp_str = reg_names[FRAME_POINTER_REGNUM]; | |
6051 | char *t1_str = "%g1"; | |
6052 | ||
c819be5b JW |
6053 | /* In the reload sequence, we don't need to fill the load delay |
6054 | slots for most of the loads, also see if we can fill the final | |
6055 | delay slot if not otherwise filled by the reload sequence. */ | |
6056 | ||
86735b02 | 6057 | if (size > 4095) |
e0d80184 | 6058 | fprintf (file, "\tset\t%d, %s\n", size, t1_str); |
c819be5b JW |
6059 | |
6060 | if (frame_pointer_needed) | |
6061 | { | |
86735b02 | 6062 | if (size > 4095) |
e0d80184 | 6063 | fprintf (file,"\tsub\t%s, %s, %s\t\t%s# sp not trusted here\n", |
bf62bbf1 | 6064 | fp_str, t1_str, sp_str, ASM_COMMENT_START); |
c819be5b | 6065 | else |
e0d80184 | 6066 | fprintf (file,"\tsub\t%s, %d, %s\t\t%s# sp not trusted here\n", |
bf62bbf1 | 6067 | fp_str, size, sp_str, ASM_COMMENT_START); |
c819be5b JW |
6068 | } |
6069 | ||
ddd5a7c1 | 6070 | /* Is the entire register save area offsettable from %sp? */ |
86735b02 DE |
6071 | if (reg_offset < 4096 - 64 * UNITS_PER_WORD) |
6072 | { | |
6073 | size1 = 0; | |
6074 | } | |
6075 | else | |
6076 | { | |
6077 | /* Restore %sp in two steps, but make sure there is always a | |
6078 | 64 byte register save area, and %sp is properly aligned. */ | |
6079 | /* Amount to increment %sp by, the first time. */ | |
6080 | size1 = ((reg_offset - 64 - 16) + 15) & -16; | |
6081 | /* Offset to register save area from %sp. */ | |
6082 | reg_offset = size1 - reg_offset; | |
6083 | ||
e0d80184 | 6084 | fprintf (file, "\tset\t%d, %s\n\tadd\t%s, %s, %s\n", |
86735b02 DE |
6085 | size1, t1_str, sp_str, t1_str, sp_str); |
6086 | } | |
6087 | ||
6088 | /* We must restore the frame pointer and return address reg first | |
6089 | because they are treated specially by the prologue output code. */ | |
6090 | if (current_frame_info.gmask & FRAME_POINTER_MASK) | |
6091 | { | |
e0d80184 | 6092 | fprintf (file, "\tld\t[%s+%d], %s\n", |
86735b02 DE |
6093 | sp_str, reg_offset, fp_str); |
6094 | reg_offset += 4; | |
6095 | } | |
6096 | if (current_frame_info.gmask & RETURN_ADDR_MASK) | |
6097 | { | |
e0d80184 | 6098 | fprintf (file, "\tld\t[%s+%d], %s\n", |
86735b02 DE |
6099 | sp_str, reg_offset, reg_names[RETURN_ADDR_REGNUM]); |
6100 | reg_offset += 4; | |
6101 | } | |
6102 | ||
6103 | /* Restore any remaining saved registers. */ | |
6104 | sparc_flat_save_restore (file, sp_str, reg_offset, | |
6105 | current_frame_info.gmask & ~(FRAME_POINTER_MASK | RETURN_ADDR_MASK), | |
6106 | current_frame_info.fmask, | |
c53aa195 | 6107 | "ld", "ldd", 0); |
86735b02 DE |
6108 | |
6109 | /* If we had to increment %sp in two steps, record it so the second | |
6110 | restoration in the epilogue finishes up. */ | |
6111 | if (size1 > 0) | |
6112 | { | |
6113 | size -= size1; | |
6114 | if (size > 4095) | |
e0d80184 | 6115 | fprintf (file, "\tset\t%d, %s\n", |
86735b02 DE |
6116 | size, t1_str); |
6117 | } | |
c819be5b | 6118 | |
c819be5b | 6119 | if (current_function_returns_struct) |
e0d80184 | 6120 | fprintf (file, "\tjmp\t%%o7+12\n"); |
c819be5b JW |
6121 | else |
6122 | fprintf (file, "\tretl\n"); | |
6123 | ||
6124 | /* If the only register saved is the return address, we need a | |
6125 | nop, unless we have an instruction to put into it. Otherwise | |
6126 | we don't since reloading multiple registers doesn't reference | |
6127 | the register being loaded. */ | |
6128 | ||
6129 | if (epilogue_delay) | |
6130 | { | |
86735b02 | 6131 | if (size) |
c819be5b JW |
6132 | abort (); |
6133 | final_scan_insn (XEXP (epilogue_delay, 0), file, 1, -2, 1); | |
6134 | } | |
6135 | ||
86735b02 | 6136 | else if (size > 4095) |
e0d80184 | 6137 | fprintf (file, "\tadd\t%s, %s, %s\n", sp_str, t1_str, sp_str); |
c819be5b | 6138 | |
86735b02 | 6139 | else if (size > 0) |
e0d80184 | 6140 | fprintf (file, "\tadd\t%s, %d, %s\n", sp_str, size, sp_str); |
c819be5b JW |
6141 | |
6142 | else | |
6143 | fprintf (file, "\tnop\n"); | |
6144 | } | |
6145 | ||
6146 | /* Reset state info for each function. */ | |
6147 | current_frame_info = zero_frame_info; | |
e0d80184 DM |
6148 | |
6149 | sparc_output_deferred_case_vectors (); | |
c819be5b JW |
6150 | } |
6151 | \f | |
6152 | /* Define the number of delay slots needed for the function epilogue. | |
6153 | ||
6154 | On the sparc, we need a slot if either no stack has been allocated, | |
6155 | or the only register saved is the return register. */ | |
6156 | ||
6157 | int | |
c6aa9ce1 | 6158 | sparc_flat_epilogue_delay_slots () |
c819be5b JW |
6159 | { |
6160 | if (!current_frame_info.initialized) | |
c6aa9ce1 | 6161 | (void) sparc_flat_compute_frame_size (get_frame_size ()); |
c819be5b JW |
6162 | |
6163 | if (current_frame_info.total_size == 0) | |
6164 | return 1; | |
6165 | ||
c819be5b JW |
6166 | return 0; |
6167 | } | |
6168 | ||
6169 | /* Return true is TRIAL is a valid insn for the epilogue delay slot. | |
6170 | Any single length instruction which doesn't reference the stack or frame | |
6171 | pointer is OK. */ | |
6172 | ||
6173 | int | |
c6aa9ce1 | 6174 | sparc_flat_eligible_for_epilogue_delay (trial, slot) |
c819be5b | 6175 | rtx trial; |
db3d4438 | 6176 | int slot ATTRIBUTE_UNUSED; |
c819be5b | 6177 | { |
c4ce6853 DE |
6178 | rtx pat = PATTERN (trial); |
6179 | ||
6180 | if (get_attr_length (trial) != 1) | |
6181 | return 0; | |
6182 | ||
6183 | /* If %g0 is live, there are lots of things we can't handle. | |
6184 | Rather than trying to find them all now, let's punt and only | |
6185 | optimize things as necessary. */ | |
6186 | if (TARGET_LIVE_G0) | |
6187 | return 0; | |
6188 | ||
6189 | if (! reg_mentioned_p (stack_pointer_rtx, pat) | |
6190 | && ! reg_mentioned_p (frame_pointer_rtx, pat)) | |
c819be5b | 6191 | return 1; |
c4ce6853 | 6192 | |
c819be5b JW |
6193 | return 0; |
6194 | } | |
dbb54862 JW |
6195 | \f |
6196 | /* Adjust the cost of a scheduling dependency. Return the new cost of | |
6197 | a dependency LINK or INSN on DEP_INSN. COST is the current cost. */ | |
6198 | ||
6199 | int | |
6200 | supersparc_adjust_cost (insn, link, dep_insn, cost) | |
6201 | rtx insn; | |
6202 | rtx link; | |
6203 | rtx dep_insn; | |
6204 | int cost; | |
6205 | { | |
6206 | enum attr_type insn_type; | |
6207 | ||
6208 | if (! recog_memoized (insn)) | |
6209 | return 0; | |
6210 | ||
6211 | insn_type = get_attr_type (insn); | |
6212 | ||
6213 | if (REG_NOTE_KIND (link) == 0) | |
6214 | { | |
6215 | /* Data dependency; DEP_INSN writes a register that INSN reads some | |
6216 | cycles later. */ | |
6217 | ||
6218 | /* if a load, then the dependence must be on the memory address; | |
3bc8b61e DM |
6219 | add an extra "cycle". Note that the cost could be two cycles |
6220 | if the reg was written late in an instruction group; we ca not tell | |
dbb54862 JW |
6221 | here. */ |
6222 | if (insn_type == TYPE_LOAD || insn_type == TYPE_FPLOAD) | |
6223 | return cost + 3; | |
6224 | ||
6225 | /* Get the delay only if the address of the store is the dependence. */ | |
6226 | if (insn_type == TYPE_STORE || insn_type == TYPE_FPSTORE) | |
6227 | { | |
6228 | rtx pat = PATTERN(insn); | |
6229 | rtx dep_pat = PATTERN (dep_insn); | |
6230 | ||
6231 | if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET) | |
3bc8b61e | 6232 | return cost; /* This should not happen! */ |
dbb54862 JW |
6233 | |
6234 | /* The dependency between the two instructions was on the data that | |
6235 | is being stored. Assume that this implies that the address of the | |
6236 | store is not dependent. */ | |
6237 | if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat))) | |
6238 | return cost; | |
6239 | ||
6240 | return cost + 3; /* An approximation. */ | |
6241 | } | |
6242 | ||
6243 | /* A shift instruction cannot receive its data from an instruction | |
6244 | in the same cycle; add a one cycle penalty. */ | |
6245 | if (insn_type == TYPE_SHIFT) | |
6246 | return cost + 3; /* Split before cascade into shift. */ | |
6247 | } | |
6248 | else | |
6249 | { | |
6250 | /* Anti- or output- dependency; DEP_INSN reads/writes a register that | |
6251 | INSN writes some cycles later. */ | |
6252 | ||
6253 | /* These are only significant for the fpu unit; writing a fp reg before | |
6254 | the fpu has finished with it stalls the processor. */ | |
6255 | ||
6256 | /* Reusing an integer register causes no problems. */ | |
6257 | if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT) | |
6258 | return 0; | |
6259 | } | |
6260 | ||
6261 | return cost; | |
6262 | } | |
bfd6bc60 | 6263 | |
3bc8b61e DM |
6264 | /* This describes the state of the UltraSPARC pipeline during |
6265 | instruction scheduling. */ | |
6266 | ||
b96a5ea5 KG |
6267 | #define TMASK(__x) ((unsigned)1 << ((int)(__x))) |
6268 | #define UMASK(__x) ((unsigned)1 << ((int)(__x))) | |
3bc8b61e DM |
6269 | |
6270 | enum ultra_code { NONE=0, /* no insn at all */ | |
6271 | IEU0, /* shifts and conditional moves */ | |
6272 | IEU1, /* condition code setting insns, calls+jumps */ | |
6273 | IEUN, /* all other single cycle ieu insns */ | |
6274 | LSU, /* loads and stores */ | |
6275 | CTI, /* branches */ | |
6276 | FPM, /* FPU pipeline 1, multiplies and divides */ | |
6277 | FPA, /* FPU pipeline 2, all other operations */ | |
6278 | SINGLE, /* single issue instructions */ | |
6279 | NUM_ULTRA_CODES }; | |
6280 | ||
6281 | static char *ultra_code_names[NUM_ULTRA_CODES] = { | |
6282 | "NONE", "IEU0", "IEU1", "IEUN", "LSU", "CTI", | |
6283 | "FPM", "FPA", "SINGLE" }; | |
6284 | ||
6285 | struct ultrasparc_pipeline_state { | |
6286 | /* The insns in this group. */ | |
6287 | rtx group[4]; | |
6288 | ||
6289 | /* The code for each insn. */ | |
6290 | enum ultra_code codes[4]; | |
6291 | ||
6292 | /* Which insns in this group have been committed by the | |
6293 | scheduler. This is how we determine how many more | |
6294 | can issue this cycle. */ | |
6295 | char commit[4]; | |
6296 | ||
6297 | /* How many insns in this group. */ | |
6298 | char group_size; | |
6299 | ||
6300 | /* Mask of free slots still in this group. */ | |
6301 | char free_slot_mask; | |
6302 | ||
6303 | /* The slotter uses the following to determine what other | |
6304 | insn types can still make their way into this group. */ | |
6305 | char contents [NUM_ULTRA_CODES]; | |
6306 | char num_ieu_insns; | |
6307 | }; | |
6308 | ||
6309 | #define ULTRA_NUM_HIST 8 | |
6310 | static struct ultrasparc_pipeline_state ultra_pipe_hist[ULTRA_NUM_HIST]; | |
6311 | static int ultra_cur_hist; | |
6312 | static int ultra_cycles_elapsed; | |
6313 | ||
6314 | #define ultra_pipe (ultra_pipe_hist[ultra_cur_hist]) | |
6315 | ||
6316 | /* Given TYPE_MASK compute the ultra_code it has. */ | |
6317 | static enum ultra_code | |
6318 | ultra_code_from_mask (type_mask) | |
6319 | int type_mask; | |
6320 | { | |
3bc8b61e DM |
6321 | if (type_mask & (TMASK (TYPE_SHIFT) | TMASK (TYPE_CMOVE))) |
6322 | return IEU0; | |
6323 | else if (type_mask & (TMASK (TYPE_COMPARE) | | |
6324 | TMASK (TYPE_CALL) | | |
6325 | TMASK (TYPE_UNCOND_BRANCH))) | |
6326 | return IEU1; | |
6327 | else if (type_mask & (TMASK (TYPE_IALU) | TMASK (TYPE_BINARY) | | |
6328 | TMASK (TYPE_MOVE) | TMASK (TYPE_UNARY))) | |
6329 | return IEUN; | |
6330 | else if (type_mask & (TMASK (TYPE_LOAD) | TMASK (TYPE_SLOAD) | | |
6331 | TMASK (TYPE_STORE) | TMASK (TYPE_FPLOAD) | | |
6332 | TMASK (TYPE_FPSTORE))) | |
6333 | return LSU; | |
6334 | else if (type_mask & (TMASK (TYPE_FPMUL) | TMASK (TYPE_FPDIVS) | | |
6335 | TMASK (TYPE_FPDIVD) | TMASK (TYPE_FPSQRT))) | |
6336 | return FPM; | |
6337 | else if (type_mask & (TMASK (TYPE_FPMOVE) | TMASK (TYPE_FPCMOVE) | | |
6338 | TMASK (TYPE_FP) | TMASK (TYPE_FPCMP))) | |
6339 | return FPA; | |
6340 | else if (type_mask & TMASK (TYPE_BRANCH)) | |
6341 | return CTI; | |
6342 | ||
6343 | return SINGLE; | |
6344 | } | |
6345 | ||
6346 | /* Check INSN (a conditional move) and make sure that it's | |
6347 | results are available at this cycle. Return 1 if the | |
6348 | results are in fact ready. */ | |
6349 | static int | |
6350 | ultra_cmove_results_ready_p (insn) | |
6351 | rtx insn; | |
6352 | { | |
6353 | struct ultrasparc_pipeline_state *up; | |
6354 | int entry, slot; | |
6355 | ||
6356 | /* If this got dispatched in the previous | |
6357 | group, the results are not ready. */ | |
ddf80874 | 6358 | entry = (ultra_cur_hist - 1) % (ULTRA_NUM_HIST - 1); |
3bc8b61e DM |
6359 | up = &ultra_pipe_hist[entry]; |
6360 | slot = 4; | |
6361 | while (--slot >= 0) | |
6362 | if (up->group[slot] == insn) | |
c305b1a7 | 6363 | return 0; |
3bc8b61e | 6364 | |
c305b1a7 | 6365 | return 1; |
3bc8b61e DM |
6366 | } |
6367 | ||
6368 | /* Walk backwards in pipeline history looking for FPU | |
6369 | operations which use a mode different than FPMODE and | |
6370 | will create a stall if an insn using FPMODE were to be | |
6371 | dispatched this cycle. */ | |
6372 | static int | |
6373 | ultra_fpmode_conflict_exists (fpmode) | |
6374 | enum machine_mode fpmode; | |
6375 | { | |
6376 | int hist_ent; | |
6377 | int hist_lim; | |
6378 | ||
ddf80874 | 6379 | hist_ent = (ultra_cur_hist - 1) % (ULTRA_NUM_HIST - 1); |
3bc8b61e DM |
6380 | if (ultra_cycles_elapsed < 4) |
6381 | hist_lim = ultra_cycles_elapsed; | |
6382 | else | |
6383 | hist_lim = 4; | |
6384 | while (hist_lim > 0) | |
6385 | { | |
6386 | struct ultrasparc_pipeline_state *up = &ultra_pipe_hist[hist_ent]; | |
6387 | int slot = 4; | |
6388 | ||
6389 | while (--slot >= 0) | |
6390 | { | |
6391 | rtx insn = up->group[slot]; | |
6392 | enum machine_mode this_mode; | |
3bc8b61e DM |
6393 | rtx pat; |
6394 | ||
6395 | if (! insn | |
6396 | || GET_CODE (insn) != INSN | |
6397 | || (pat = PATTERN (insn)) == 0 | |
6398 | || GET_CODE (pat) != SET) | |
6399 | continue; | |
6400 | ||
6401 | this_mode = GET_MODE (SET_DEST (pat)); | |
6402 | if ((this_mode != SFmode | |
6403 | && this_mode != DFmode) | |
6404 | || this_mode == fpmode) | |
6405 | continue; | |
6406 | ||
6407 | /* If it is not FMOV, FABS, FNEG, FDIV, or FSQRT then | |
ddf80874 DM |
6408 | we will get a stall. Loads and stores are independant |
6409 | of these rules. */ | |
3bc8b61e DM |
6410 | if (GET_CODE (SET_SRC (pat)) != ABS |
6411 | && GET_CODE (SET_SRC (pat)) != NEG | |
6412 | && ((TMASK (get_attr_type (insn)) & | |
6413 | (TMASK (TYPE_FPDIVS) | TMASK (TYPE_FPDIVD) | | |
ddf80874 DM |
6414 | TMASK (TYPE_FPMOVE) | TMASK (TYPE_FPSQRT) | |
6415 | TMASK (TYPE_LOAD) | TMASK (TYPE_STORE))) == 0)) | |
3bc8b61e DM |
6416 | return 1; |
6417 | } | |
6418 | hist_lim--; | |
ddf80874 | 6419 | hist_ent = (hist_ent - 1) % (ULTRA_NUM_HIST - 1); |
3bc8b61e DM |
6420 | } |
6421 | ||
6422 | /* No conflicts, safe to dispatch. */ | |
6423 | return 0; | |
6424 | } | |
6425 | ||
6426 | /* Find an instruction in LIST which has one of the | |
6427 | type attributes enumerated in TYPE_MASK. START | |
6428 | says where to begin the search. | |
6429 | ||
6430 | NOTE: This scheme depends upon the fact that we | |
6431 | have less than 32 distinct type attributes. */ | |
5a5325cb DM |
6432 | |
6433 | static int ultra_types_avail; | |
6434 | ||
3bc8b61e DM |
6435 | static rtx * |
6436 | ultra_find_type (type_mask, list, start) | |
6437 | int type_mask; | |
6438 | rtx *list; | |
6439 | int start; | |
6440 | { | |
6441 | int i; | |
6442 | ||
5a5325cb DM |
6443 | /* Short circuit if no such insn exists in the ready |
6444 | at the moment. */ | |
6445 | if ((type_mask & ultra_types_avail) == 0) | |
6446 | return 0; | |
6447 | ||
3bc8b61e DM |
6448 | for (i = start; i >= 0; i--) |
6449 | { | |
6450 | rtx insn = list[i]; | |
6451 | ||
6452 | if (recog_memoized (insn) >= 0 | |
6453 | && (TMASK(get_attr_type (insn)) & type_mask)) | |
6454 | { | |
ddf80874 | 6455 | enum machine_mode fpmode = SFmode; |
3bc8b61e DM |
6456 | rtx pat = 0; |
6457 | int slot; | |
6458 | int check_depend = 0; | |
6459 | int check_fpmode_conflict = 0; | |
6460 | ||
6461 | if (GET_CODE (insn) == INSN | |
6462 | && (pat = PATTERN(insn)) != 0 | |
6463 | && GET_CODE (pat) == SET | |
6464 | && !(type_mask & (TMASK (TYPE_STORE) | | |
6465 | TMASK (TYPE_FPSTORE)))) | |
6466 | { | |
6467 | check_depend = 1; | |
6468 | if (GET_MODE (SET_DEST (pat)) == SFmode | |
6469 | || GET_MODE (SET_DEST (pat)) == DFmode) | |
6470 | { | |
6471 | fpmode = GET_MODE (SET_DEST (pat)); | |
6472 | check_fpmode_conflict = 1; | |
6473 | } | |
6474 | } | |
6475 | ||
6476 | slot = 4; | |
6477 | while(--slot >= 0) | |
6478 | { | |
6479 | rtx slot_insn = ultra_pipe.group[slot]; | |
6480 | rtx slot_pat; | |
6481 | ||
6482 | /* Already issued, bad dependency, or FPU | |
6483 | mode conflict. */ | |
6484 | if (slot_insn != 0 | |
6485 | && (slot_pat = PATTERN (slot_insn)) != 0 | |
6486 | && ((insn == slot_insn) | |
6487 | || (check_depend == 1 | |
6488 | && GET_CODE (slot_insn) == INSN | |
6489 | && GET_CODE (slot_pat) == SET | |
5a5325cb DM |
6490 | && ((GET_CODE (SET_DEST (slot_pat)) == REG |
6491 | && GET_CODE (SET_SRC (pat)) == REG | |
6492 | && REGNO (SET_DEST (slot_pat)) == | |
6493 | REGNO (SET_SRC (pat))) | |
6494 | || (GET_CODE (SET_DEST (slot_pat)) == SUBREG | |
6495 | && GET_CODE (SET_SRC (pat)) == SUBREG | |
6496 | && REGNO (SUBREG_REG (SET_DEST (slot_pat))) == | |
6497 | REGNO (SUBREG_REG (SET_SRC (pat))) | |
6498 | && SUBREG_WORD (SET_DEST (slot_pat)) == | |
ddf80874 | 6499 | SUBREG_WORD (SET_SRC (pat))))) |
3bc8b61e DM |
6500 | || (check_fpmode_conflict == 1 |
6501 | && GET_CODE (slot_insn) == INSN | |
6502 | && GET_CODE (slot_pat) == SET | |
ddf80874 DM |
6503 | && (GET_MODE (SET_DEST (slot_pat)) == SFmode |
6504 | || GET_MODE (SET_DEST (slot_pat)) == DFmode) | |
6505 | && GET_MODE (SET_DEST (slot_pat)) != fpmode))) | |
3bc8b61e DM |
6506 | goto next; |
6507 | } | |
6508 | ||
6509 | /* Check for peculiar result availability and dispatch | |
6510 | interference situations. */ | |
6511 | if (pat != 0 | |
6512 | && ultra_cycles_elapsed > 0) | |
6513 | { | |
6514 | rtx link; | |
6515 | ||
6516 | for (link = LOG_LINKS (insn); link; link = XEXP (link, 1)) | |
6517 | { | |
6518 | rtx link_insn = XEXP (link, 0); | |
6519 | if (GET_CODE (link_insn) == INSN | |
6520 | && recog_memoized (link_insn) >= 0 | |
6521 | && (TMASK (get_attr_type (link_insn)) & | |
6522 | (TMASK (TYPE_CMOVE) | TMASK (TYPE_FPCMOVE))) | |
6523 | && ! ultra_cmove_results_ready_p (link_insn)) | |
6524 | goto next; | |
6525 | } | |
6526 | ||
6527 | if (check_fpmode_conflict | |
6528 | && ultra_fpmode_conflict_exists (fpmode)) | |
6529 | goto next; | |
6530 | } | |
6531 | ||
6532 | return &list[i]; | |
6533 | } | |
6534 | next: | |
5a5325cb | 6535 | ; |
3bc8b61e DM |
6536 | } |
6537 | return 0; | |
6538 | } | |
6539 | ||
5a5325cb DM |
6540 | static void |
6541 | ultra_build_types_avail (ready, n_ready) | |
6542 | rtx *ready; | |
6543 | int n_ready; | |
6544 | { | |
6545 | int i = n_ready - 1; | |
6546 | ||
6547 | ultra_types_avail = 0; | |
6548 | while(i >= 0) | |
6549 | { | |
6550 | rtx insn = ready[i]; | |
6551 | ||
6552 | if (recog_memoized (insn) >= 0) | |
6553 | ultra_types_avail |= TMASK (get_attr_type (insn)); | |
6554 | ||
6555 | i -= 1; | |
6556 | } | |
6557 | } | |
6558 | ||
3bc8b61e DM |
6559 | /* Place insn pointed to my IP into the pipeline. |
6560 | Make element THIS of READY be that insn if it | |
6561 | is not already. TYPE indicates the pipeline class | |
6562 | this insn falls into. */ | |
6563 | static void | |
6564 | ultra_schedule_insn (ip, ready, this, type) | |
6565 | rtx *ip; | |
6566 | rtx *ready; | |
6567 | int this; | |
6568 | enum ultra_code type; | |
6569 | { | |
6570 | int pipe_slot; | |
6571 | char mask = ultra_pipe.free_slot_mask; | |
6572 | ||
6573 | /* Obtain free slot. */ | |
6574 | for (pipe_slot = 0; pipe_slot < 4; pipe_slot++) | |
6575 | if ((mask & (1 << pipe_slot)) != 0) | |
6576 | break; | |
6577 | if (pipe_slot == 4) | |
6578 | abort (); | |
6579 | ||
6580 | /* In it goes, and it hasn't been committed yet. */ | |
6581 | ultra_pipe.group[pipe_slot] = *ip; | |
6582 | ultra_pipe.codes[pipe_slot] = type; | |
6583 | ultra_pipe.contents[type] = 1; | |
6584 | if (UMASK (type) & | |
6585 | (UMASK (IEUN) | UMASK (IEU0) | UMASK (IEU1))) | |
6586 | ultra_pipe.num_ieu_insns += 1; | |
6587 | ||
6588 | ultra_pipe.free_slot_mask = (mask & ~(1 << pipe_slot)); | |
6589 | ultra_pipe.group_size += 1; | |
6590 | ultra_pipe.commit[pipe_slot] = 0; | |
6591 | ||
6592 | /* Update ready list. */ | |
6593 | if (ip != &ready[this]) | |
6594 | { | |
6595 | rtx temp = *ip; | |
6596 | ||
6597 | *ip = ready[this]; | |
6598 | ready[this] = temp; | |
6599 | } | |
6600 | } | |
6601 | ||
6602 | /* Advance to the next pipeline group. */ | |
6603 | static void | |
6604 | ultra_flush_pipeline () | |
6605 | { | |
ddf80874 | 6606 | ultra_cur_hist = (ultra_cur_hist + 1) % (ULTRA_NUM_HIST - 1); |
3bc8b61e DM |
6607 | ultra_cycles_elapsed += 1; |
6608 | bzero ((char *) &ultra_pipe, sizeof ultra_pipe); | |
6609 | ultra_pipe.free_slot_mask = 0xf; | |
6610 | } | |
6611 | ||
6612 | static int ultra_reorder_called_this_block; | |
6613 | ||
6614 | /* Init our data structures for this current block. */ | |
6615 | void | |
6616 | ultrasparc_sched_init (dump, sched_verbose) | |
ddf80874 DM |
6617 | FILE *dump ATTRIBUTE_UNUSED; |
6618 | int sched_verbose ATTRIBUTE_UNUSED; | |
3bc8b61e | 6619 | { |
b96a5ea5 | 6620 | bzero ((char *) ultra_pipe_hist, sizeof ultra_pipe_hist); |
3bc8b61e DM |
6621 | ultra_cur_hist = 0; |
6622 | ultra_cycles_elapsed = 0; | |
6623 | ultra_reorder_called_this_block = 0; | |
ddf80874 | 6624 | ultra_pipe.free_slot_mask = 0xf; |
3bc8b61e DM |
6625 | } |
6626 | ||
6627 | /* INSN has been scheduled, update pipeline commit state | |
6628 | and return how many instructions are still to be | |
6629 | scheduled in this group. */ | |
bfd6bc60 | 6630 | int |
3bc8b61e DM |
6631 | ultrasparc_variable_issue (insn) |
6632 | rtx insn; | |
6633 | { | |
6634 | struct ultrasparc_pipeline_state *up = &ultra_pipe; | |
6635 | int i, left_to_fire; | |
6636 | ||
6637 | left_to_fire = 0; | |
6638 | for (i = 0; i < 4; i++) | |
6639 | { | |
6640 | if (up->group[i] == 0) | |
6641 | continue; | |
6642 | ||
6643 | if (up->group[i] == insn) | |
6644 | { | |
6645 | up->commit[i] = 1; | |
6646 | } | |
6647 | else if (! up->commit[i]) | |
6648 | left_to_fire++; | |
6649 | } | |
6650 | ||
6651 | return left_to_fire; | |
6652 | } | |
6653 | ||
6654 | /* In actual_hazard_this_instance, we may have yanked some | |
6655 | instructions from the ready list due to conflict cost | |
6656 | adjustments. If so, and such an insn was in our pipeline | |
6657 | group, remove it and update state. */ | |
6658 | static void | |
6659 | ultra_rescan_pipeline_state (ready, n_ready) | |
6660 | rtx *ready; | |
6661 | int n_ready; | |
6662 | { | |
6663 | struct ultrasparc_pipeline_state *up = &ultra_pipe; | |
6664 | int i; | |
6665 | ||
6666 | for (i = 0; i < 4; i++) | |
6667 | { | |
6668 | rtx insn = up->group[i]; | |
3bc8b61e DM |
6669 | int j; |
6670 | ||
6671 | if (! insn) | |
6672 | continue; | |
6673 | ||
6674 | /* If it has been committed, then it was removed from | |
6675 | the ready list because it was actually scheduled, | |
6676 | and that is not the case we are searching for here. */ | |
6677 | if (up->commit[i] != 0) | |
6678 | continue; | |
6679 | ||
6680 | for (j = n_ready - 1; j >= 0; j--) | |
6681 | if (ready[j] == insn) | |
6682 | break; | |
6683 | ||
6684 | /* If we didn't find it, toss it. */ | |
6685 | if (j < 0) | |
6686 | { | |
6687 | enum ultra_code ucode = up->codes[i]; | |
6688 | ||
6689 | up->group[i] = 0; | |
6690 | up->codes[i] = NONE; | |
6691 | up->contents[ucode] = 0; | |
6692 | if (UMASK (ucode) & | |
6693 | (UMASK (IEUN) | UMASK (IEU0) | UMASK (IEU1))) | |
6694 | up->num_ieu_insns -= 1; | |
6695 | ||
6696 | up->free_slot_mask |= (1 << i); | |
6697 | up->group_size -= 1; | |
6698 | up->commit[i] = 0; | |
6699 | } | |
6700 | } | |
6701 | } | |
6702 | ||
6703 | void | |
6704 | ultrasparc_sched_reorder (dump, sched_verbose, ready, n_ready) | |
6705 | FILE *dump; | |
6706 | int sched_verbose; | |
6707 | rtx *ready; | |
6708 | int n_ready; | |
6709 | { | |
6710 | struct ultrasparc_pipeline_state *up = &ultra_pipe; | |
6711 | int i, this_insn; | |
6712 | ||
6713 | /* We get called once unnecessarily per block of insns | |
6714 | scheduled. */ | |
6715 | if (ultra_reorder_called_this_block == 0) | |
6716 | { | |
6717 | ultra_reorder_called_this_block = 1; | |
6718 | return; | |
6719 | } | |
6720 | ||
6721 | if (sched_verbose) | |
6722 | { | |
6723 | int n; | |
6724 | ||
6725 | fprintf (dump, "\n;;\tUltraSPARC Looking at ["); | |
6726 | for (n = n_ready - 1; n >= 0; n--) | |
6727 | { | |
6728 | rtx insn = ready[n]; | |
6729 | enum ultra_code ucode; | |
6730 | ||
6731 | if (recog_memoized (insn) < 0) | |
6732 | continue; | |
6733 | ucode = ultra_code_from_mask (TMASK (get_attr_type (insn))); | |
6734 | if (n != 0) | |
6735 | fprintf (dump, "%s(%d) ", | |
6736 | ultra_code_names[ucode], | |
6737 | INSN_UID (insn)); | |
6738 | else | |
6739 | fprintf (dump, "%s(%d)", | |
6740 | ultra_code_names[ucode], | |
6741 | INSN_UID (insn)); | |
6742 | } | |
6743 | fprintf (dump, "]\n"); | |
6744 | } | |
6745 | ||
6746 | this_insn = n_ready - 1; | |
6747 | ||
6748 | /* Skip over junk we don't understand. */ | |
6749 | while ((this_insn >= 0) | |
6750 | && recog_memoized (ready[this_insn]) < 0) | |
6751 | this_insn--; | |
6752 | ||
5a5325cb DM |
6753 | ultra_build_types_avail (ready, this_insn + 1); |
6754 | ||
3bc8b61e DM |
6755 | while (this_insn >= 0) { |
6756 | int old_group_size = up->group_size; | |
6757 | ||
6758 | if (up->group_size != 0) | |
6759 | { | |
6760 | int num_committed; | |
6761 | ||
6762 | num_committed = (up->commit[0] + up->commit[1] + | |
6763 | up->commit[2] + up->commit[3]); | |
6764 | /* If nothing has been commited from our group, or all of | |
6765 | them have. Clear out the (current cycle's) pipeline | |
6766 | state and start afresh. */ | |
6767 | if (num_committed == 0 | |
6768 | || num_committed == up->group_size) | |
6769 | { | |
ddf80874 DM |
6770 | ultra_flush_pipeline (); |
6771 | up = &ultra_pipe; | |
3bc8b61e DM |
6772 | old_group_size = 0; |
6773 | } | |
6774 | else | |
6775 | { | |
6776 | /* OK, some ready list insns got requeued and thus removed | |
6777 | from the ready list. Account for this fact. */ | |
6778 | ultra_rescan_pipeline_state (ready, n_ready); | |
6779 | ||
6780 | /* Something "changed", make this look like a newly | |
6781 | formed group so the code at the end of the loop | |
6782 | knows that progress was in fact made. */ | |
6783 | if (up->group_size != old_group_size) | |
ddf80874 | 6784 | old_group_size = 0; |
3bc8b61e DM |
6785 | } |
6786 | } | |
6787 | ||
6788 | if (up->group_size == 0) | |
6789 | { | |
6790 | /* If the pipeline is (still) empty and we have any single | |
6791 | group insns, get them out now as this is a good time. */ | |
6792 | rtx *ip = ultra_find_type ((TMASK (TYPE_RETURN) | TMASK (TYPE_ADDRESS) | | |
6793 | TMASK (TYPE_IMUL) | TMASK (TYPE_CMOVE) | | |
6794 | TMASK (TYPE_MULTI) | TMASK (TYPE_MISC)), | |
6795 | ready, this_insn); | |
6796 | if (ip) | |
6797 | { | |
6798 | ultra_schedule_insn (ip, ready, this_insn, SINGLE); | |
6799 | break; | |
6800 | } | |
6801 | ||
6802 | /* If we are not in the process of emptying out the pipe, try to | |
6803 | obtain an instruction which must be the first in it's group. */ | |
6804 | ip = ultra_find_type ((TMASK (TYPE_CALL) | | |
6805 | TMASK (TYPE_CALL_NO_DELAY_SLOT) | | |
6806 | TMASK (TYPE_UNCOND_BRANCH)), | |
6807 | ready, this_insn); | |
6808 | if (ip) | |
6809 | { | |
6810 | ultra_schedule_insn (ip, ready, this_insn, IEU1); | |
6811 | this_insn--; | |
6812 | } | |
6813 | else if ((ip = ultra_find_type ((TMASK (TYPE_FPDIVS) | | |
6814 | TMASK (TYPE_FPDIVD) | | |
6815 | TMASK (TYPE_FPSQRT)), | |
6816 | ready, this_insn)) != 0) | |
6817 | { | |
6818 | ultra_schedule_insn (ip, ready, this_insn, FPM); | |
6819 | this_insn--; | |
6820 | } | |
6821 | } | |
6822 | ||
6823 | /* Try to fill the integer pipeline. First, look for an IEU0 specific | |
6824 | operation. We can't do more IEU operations if the first 3 slots are | |
6825 | all full or we have dispatched two IEU insns already. */ | |
6826 | if ((up->free_slot_mask & 0x7) != 0 | |
6827 | && up->num_ieu_insns < 2 | |
6828 | && up->contents[IEU0] == 0 | |
6829 | && up->contents[IEUN] == 0) | |
6830 | { | |
6831 | rtx *ip = ultra_find_type (TMASK(TYPE_SHIFT), ready, this_insn); | |
6832 | if (ip) | |
6833 | { | |
6834 | ultra_schedule_insn (ip, ready, this_insn, IEU0); | |
6835 | this_insn--; | |
6836 | } | |
6837 | } | |
6838 | ||
6839 | /* If we can, try to find an IEU1 specific or an unnamed | |
6840 | IEU instruction. */ | |
6841 | if ((up->free_slot_mask & 0x7) != 0 | |
6842 | && up->num_ieu_insns < 2) | |
6843 | { | |
6844 | rtx *ip = ultra_find_type ((TMASK (TYPE_IALU) | TMASK (TYPE_BINARY) | | |
6845 | TMASK (TYPE_MOVE) | TMASK (TYPE_UNARY) | | |
6846 | (up->contents[IEU1] == 0 ? TMASK (TYPE_COMPARE) : 0)), | |
6847 | ready, this_insn); | |
6848 | if (ip) | |
6849 | { | |
6850 | rtx insn = *ip; | |
6851 | ||
6852 | ultra_schedule_insn (ip, ready, this_insn, | |
6853 | (!up->contents[IEU1] | |
6854 | && get_attr_type (insn) == TYPE_COMPARE) | |
6855 | ? IEU1 : IEUN); | |
6856 | this_insn--; | |
6857 | } | |
6858 | } | |
6859 | ||
6860 | /* If only one IEU insn has been found, try to find another unnamed | |
6861 | IEU operation or an IEU1 specific one. */ | |
6862 | if ((up->free_slot_mask & 0x7) != 0 | |
6863 | && up->num_ieu_insns < 2) | |
6864 | { | |
6865 | rtx *ip; | |
6866 | int tmask = (TMASK (TYPE_IALU) | TMASK (TYPE_BINARY) | | |
6867 | TMASK (TYPE_MOVE) | TMASK (TYPE_UNARY)); | |
6868 | ||
6869 | if (!up->contents[IEU1]) | |
6870 | tmask |= TMASK (TYPE_COMPARE); | |
6871 | ip = ultra_find_type (tmask, ready, this_insn); | |
6872 | if (ip) | |
6873 | { | |
6874 | rtx insn = *ip; | |
6875 | ||
6876 | ultra_schedule_insn (ip, ready, this_insn, | |
6877 | (!up->contents[IEU1] | |
6878 | && get_attr_type (insn) == TYPE_COMPARE) | |
6879 | ? IEU1 : IEUN); | |
6880 | this_insn--; | |
6881 | } | |
6882 | } | |
6883 | ||
6884 | /* Try for a load or store, but such an insn can only be issued | |
6885 | if it is within' one of the first 3 slots. */ | |
6886 | if ((up->free_slot_mask & 0x7) != 0 | |
6887 | && up->contents[LSU] == 0) | |
6888 | { | |
6889 | rtx *ip = ultra_find_type ((TMASK (TYPE_LOAD) | TMASK (TYPE_SLOAD) | | |
6890 | TMASK (TYPE_STORE) | TMASK (TYPE_FPLOAD) | | |
6891 | TMASK (TYPE_FPSTORE)), ready, this_insn); | |
6892 | if (ip) | |
6893 | { | |
6894 | ultra_schedule_insn (ip, ready, this_insn, LSU); | |
6895 | this_insn--; | |
6896 | } | |
6897 | } | |
6898 | ||
6899 | /* Now find FPU operations, first FPM class. But not divisions or | |
6900 | square-roots because those will break the group up. Unlike all | |
6901 | the previous types, these can go in any slot. */ | |
6902 | if (up->free_slot_mask != 0 | |
6903 | && up->contents[FPM] == 0) | |
6904 | { | |
6905 | rtx *ip = ultra_find_type (TMASK (TYPE_FPMUL), ready, this_insn); | |
6906 | if (ip) | |
6907 | { | |
6908 | ultra_schedule_insn (ip, ready, this_insn, FPM); | |
6909 | this_insn--; | |
6910 | } | |
6911 | } | |
6912 | ||
6913 | /* Continue on with FPA class if we have not filled the group already. */ | |
6914 | if (up->free_slot_mask != 0 | |
6915 | && up->contents[FPA] == 0) | |
6916 | { | |
6917 | rtx *ip = ultra_find_type ((TMASK (TYPE_FPMOVE) | TMASK (TYPE_FPCMOVE) | | |
6918 | TMASK (TYPE_FP) | TMASK (TYPE_FPCMP)), | |
6919 | ready, this_insn); | |
6920 | if (ip) | |
6921 | { | |
6922 | ultra_schedule_insn (ip, ready, this_insn, FPA); | |
6923 | this_insn--; | |
6924 | } | |
6925 | } | |
6926 | ||
6927 | /* Finally, maybe stick a branch in here. */ | |
6928 | if (up->free_slot_mask != 0 | |
6929 | && up->contents[CTI] == 0) | |
6930 | { | |
6931 | rtx *ip = ultra_find_type (TMASK (TYPE_BRANCH), ready, this_insn); | |
6932 | ||
6933 | /* Try to slip in a branch only if it is one of the | |
6934 | next 2 in the ready list. */ | |
6935 | if (ip && ((&ready[this_insn] - ip) < 2)) | |
6936 | { | |
6937 | ultra_schedule_insn (ip, ready, this_insn, CTI); | |
6938 | this_insn--; | |
6939 | } | |
6940 | } | |
6941 | ||
6942 | up->group_size = 0; | |
6943 | for (i = 0; i < 4; i++) | |
6944 | if ((up->free_slot_mask & (1 << i)) == 0) | |
6945 | up->group_size++; | |
6946 | ||
6947 | /* See if we made any progress... */ | |
6948 | if (old_group_size != up->group_size) | |
6949 | break; | |
6950 | ||
6951 | /* Clean out the (current cycle's) pipeline state | |
ddf80874 DM |
6952 | and try once more. If we placed no instructions |
6953 | into the pipeline at all, it means a real hard | |
6954 | conflict exists with some earlier issued instruction | |
6955 | so we must advance to the next cycle to clear it up. */ | |
6956 | if (up->group_size == 0) | |
6957 | { | |
6958 | ultra_flush_pipeline (); | |
6959 | up = &ultra_pipe; | |
6960 | } | |
6961 | else | |
6962 | { | |
6963 | bzero ((char *) &ultra_pipe, sizeof ultra_pipe); | |
6964 | ultra_pipe.free_slot_mask = 0xf; | |
6965 | } | |
3bc8b61e DM |
6966 | } |
6967 | ||
6968 | if (sched_verbose) | |
6969 | { | |
6970 | int n, gsize; | |
6971 | ||
6972 | fprintf (dump, ";;\tUltraSPARC Launched ["); | |
6973 | gsize = up->group_size; | |
6974 | for (n = 0; n < 4; n++) | |
6975 | { | |
6976 | rtx insn = up->group[n]; | |
6977 | ||
6978 | if (! insn) | |
6979 | continue; | |
6980 | ||
6981 | gsize -= 1; | |
6982 | if (gsize != 0) | |
6983 | fprintf (dump, "%s(%d) ", | |
6984 | ultra_code_names[up->codes[n]], | |
6985 | INSN_UID (insn)); | |
6986 | else | |
6987 | fprintf (dump, "%s(%d)", | |
6988 | ultra_code_names[up->codes[n]], | |
6989 | INSN_UID (insn)); | |
6990 | } | |
6991 | fprintf (dump, "]\n"); | |
6992 | } | |
6993 | } | |
6994 | ||
6995 | int | |
ddf80874 | 6996 | ultrasparc_adjust_cost (insn, link, dep_insn, cost) |
3bc8b61e DM |
6997 | rtx insn; |
6998 | rtx link; | |
6999 | rtx dep_insn; | |
3bc8b61e | 7000 | int cost; |
bfd6bc60 JC |
7001 | { |
7002 | enum attr_type insn_type, dep_type; | |
3bc8b61e DM |
7003 | rtx pat = PATTERN(insn); |
7004 | rtx dep_pat = PATTERN (dep_insn); | |
bfd6bc60 | 7005 | |
3bc8b61e DM |
7006 | if (recog_memoized (insn) < 0 || recog_memoized (dep_insn) < 0) |
7007 | return cost; | |
bfd6bc60 | 7008 | |
3bc8b61e DM |
7009 | insn_type = get_attr_type (insn); |
7010 | dep_type = get_attr_type (dep_insn); | |
7011 | ||
7012 | /* Nothing issues in parallel with integer multiplies, so | |
7013 | mark as zero cost since the scheduler can not do anything | |
7014 | about it. */ | |
7015 | if (insn_type == TYPE_IMUL) | |
7016 | return 0; | |
bfd6bc60 JC |
7017 | |
7018 | #define SLOW_FP(dep_type) \ | |
284d86e9 JC |
7019 | (dep_type == TYPE_FPSQRT || dep_type == TYPE_FPDIVS || dep_type == TYPE_FPDIVD) |
7020 | ||
bfd6bc60 | 7021 | switch (REG_NOTE_KIND (link)) |
3bc8b61e DM |
7022 | { |
7023 | case 0: | |
bfd6bc60 | 7024 | /* Data dependency; DEP_INSN writes a register that INSN reads some |
3bc8b61e DM |
7025 | cycles later. */ |
7026 | ||
7027 | if (dep_type == TYPE_CMOVE) | |
7028 | { | |
7029 | /* Instructions that read the result of conditional moves cannot | |
7030 | be in the same group or the following group. */ | |
7031 | return cost + 1; | |
7032 | } | |
bfd6bc60 JC |
7033 | |
7034 | switch (insn_type) | |
3bc8b61e DM |
7035 | { |
7036 | /* UltraSPARC can dual issue a store and an instruction setting | |
7037 | the value stored, except for divide and square root. */ | |
bfd6bc60 | 7038 | case TYPE_FPSTORE: |
3bc8b61e DM |
7039 | if (! SLOW_FP (dep_type)) |
7040 | return 0; | |
284d86e9 | 7041 | return cost; |
bfd6bc60 | 7042 | |
3bc8b61e | 7043 | case TYPE_STORE: |
bfd6bc60 | 7044 | if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET) |
3bc8b61e | 7045 | return cost; |
bfd6bc60 | 7046 | |
284d86e9 | 7047 | if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat))) |
3bc8b61e DM |
7048 | /* The dependency between the two instructions is on the data |
7049 | that is being stored. Assume that the address of the store | |
7050 | is not also dependent. */ | |
7051 | return 0; | |
7052 | return cost; | |
7053 | ||
7054 | case TYPE_LOAD: | |
7055 | case TYPE_SLOAD: | |
7056 | case TYPE_FPLOAD: | |
7057 | /* A load does not return data until at least 11 cycles after | |
bfd6bc60 JC |
7058 | a store to the same location. 3 cycles are accounted for |
7059 | in the load latency; add the other 8 here. */ | |
7060 | if (dep_type == TYPE_STORE || dep_type == TYPE_FPSTORE) | |
3bc8b61e | 7061 | { |
bfd6bc60 JC |
7062 | /* If the addresses are not equal this may be a false |
7063 | dependency because pointer aliasing could not be | |
7064 | determined. Add only 2 cycles in that case. 2 is | |
7065 | an arbitrary compromise between 8, which would cause | |
7066 | the scheduler to generate worse code elsewhere to | |
3bc8b61e DM |
7067 | compensate for a dependency which might not really |
7068 | exist, and 0. */ | |
bfd6bc60 | 7069 | if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET |
284d86e9 JC |
7070 | || GET_CODE (SET_SRC (pat)) != MEM |
7071 | || GET_CODE (SET_DEST (dep_pat)) != MEM | |
7072 | || ! rtx_equal_p (XEXP (SET_SRC (pat), 0), | |
7073 | XEXP (SET_DEST (dep_pat), 0))) | |
bfd6bc60 JC |
7074 | return cost + 2; |
7075 | ||
3bc8b61e DM |
7076 | return cost + 8; |
7077 | } | |
284d86e9 | 7078 | return cost; |
bfd6bc60 | 7079 | |
3bc8b61e | 7080 | case TYPE_BRANCH: |
bfd6bc60 JC |
7081 | /* Compare to branch latency is 0. There is no benefit from |
7082 | separating compare and branch. */ | |
3bc8b61e DM |
7083 | if (dep_type == TYPE_COMPARE) |
7084 | return 0; | |
7085 | /* Floating point compare to branch latency is less than | |
7086 | compare to conditional move. */ | |
7087 | if (dep_type == TYPE_FPCMP) | |
7088 | return cost - 1; | |
284d86e9 | 7089 | return cost; |
bfd6bc60 | 7090 | |
3bc8b61e | 7091 | case TYPE_FPCMOVE: |
bfd6bc60 JC |
7092 | /* FMOVR class instructions can not issue in the same cycle |
7093 | or the cycle after an instruction which writes any | |
7094 | integer register. Model this as cost 2 for dependent | |
3bc8b61e | 7095 | instructions. */ |
284d86e9 JC |
7096 | if ((dep_type == TYPE_IALU || dep_type == TYPE_UNARY |
7097 | || dep_type == TYPE_BINARY) | |
3bc8b61e | 7098 | && cost < 2) |
bfd6bc60 JC |
7099 | return 2; |
7100 | /* Otherwise check as for integer conditional moves. */ | |
7101 | ||
3bc8b61e | 7102 | case TYPE_CMOVE: |
bfd6bc60 JC |
7103 | /* Conditional moves involving integer registers wait until |
7104 | 3 cycles after loads return data. The interlock applies | |
7105 | to all loads, not just dependent loads, but that is hard | |
3bc8b61e DM |
7106 | to model. */ |
7107 | if (dep_type == TYPE_LOAD || dep_type == TYPE_SLOAD) | |
7108 | return cost + 3; | |
284d86e9 | 7109 | return cost; |
27d8f9ea KG |
7110 | |
7111 | default: | |
7112 | break; | |
bfd6bc60 | 7113 | } |
3bc8b61e | 7114 | break; |
bfd6bc60 | 7115 | |
3bc8b61e | 7116 | case REG_DEP_ANTI: |
bfd6bc60 | 7117 | /* Divide and square root lock destination registers for full latency. */ |
3bc8b61e DM |
7118 | if (! SLOW_FP (dep_type)) |
7119 | return 0; | |
7120 | break; | |
7121 | ||
7122 | case REG_DEP_OUTPUT: | |
7123 | /* IEU and FPU instruction that have the same destination | |
7124 | register cannot be grouped together. */ | |
7125 | return cost + 1; | |
27d8f9ea KG |
7126 | |
7127 | default: | |
7128 | break; | |
bfd6bc60 JC |
7129 | } |
7130 | ||
3bc8b61e DM |
7131 | /* Other costs not accounted for: |
7132 | - Single precision floating point loads lock the other half of | |
7133 | the even/odd register pair. | |
bfd6bc60 | 7134 | - Several hazards associated with ldd/std are ignored because these |
3bc8b61e | 7135 | instructions are rarely generated for V9. |
bfd6bc60 JC |
7136 | - The floating point pipeline can not have both a single and double |
7137 | precision operation active at the same time. Format conversions | |
7138 | and graphics instructions are given honorary double precision status. | |
7139 | - call and jmpl are always the first instruction in a group. */ | |
7140 | ||
3bc8b61e DM |
7141 | return cost; |
7142 | } | |
bfd6bc60 JC |
7143 | |
7144 | int | |
7145 | sparc_issue_rate () | |
7146 | { | |
7147 | switch (sparc_cpu) | |
7148 | { | |
7149 | default: | |
7150 | return 1; | |
bfd6bc60 | 7151 | case PROCESSOR_V9: |
284d86e9 | 7152 | /* Assume V9 processors are capable of at least dual-issue. */ |
bfd6bc60 JC |
7153 | return 2; |
7154 | case PROCESSOR_SUPERSPARC: | |
7155 | return 3; | |
7156 | case PROCESSOR_ULTRASPARC: | |
7157 | return 4; | |
7158 | } | |
7159 | } | |
284d86e9 JC |
7160 | |
7161 | static int | |
7162 | set_extends(x, insn) | |
7163 | rtx x, insn; | |
7164 | { | |
7165 | register rtx pat = PATTERN (insn); | |
7166 | ||
7167 | switch (GET_CODE (SET_SRC (pat))) | |
7168 | { | |
7169 | /* Load and some shift instructions zero extend. */ | |
7170 | case MEM: | |
7171 | case ZERO_EXTEND: | |
7172 | /* sethi clears the high bits */ | |
7173 | case HIGH: | |
7174 | /* LO_SUM is used with sethi. sethi cleared the high | |
7175 | bits and the values used with lo_sum are positive */ | |
7176 | case LO_SUM: | |
284d86e9 JC |
7177 | /* Store flag stores 0 or 1 */ |
7178 | case LT: case LTU: | |
7179 | case GT: case GTU: | |
7180 | case LE: case LEU: | |
7181 | case GE: case GEU: | |
7182 | case EQ: | |
7183 | case NE: | |
7184 | return 1; | |
7185 | case AND: | |
7186 | { | |
7187 | rtx op1 = XEXP (SET_SRC (pat), 1); | |
7188 | if (GET_CODE (op1) == CONST_INT) | |
7189 | return INTVAL (op1) >= 0; | |
7190 | if (GET_CODE (XEXP (SET_SRC (pat), 0)) == REG | |
7191 | && sparc_check_64 (XEXP (SET_SRC (pat), 0), insn) == 1) | |
7192 | return 1; | |
7193 | if (GET_CODE (op1) == REG | |
7194 | && sparc_check_64 ((op1), insn) == 1) | |
7195 | return 1; | |
7196 | } | |
7197 | case ASHIFT: | |
7198 | case LSHIFTRT: | |
7199 | return GET_MODE (SET_SRC (pat)) == SImode; | |
7200 | /* Positive integers leave the high bits zero. */ | |
7201 | case CONST_DOUBLE: | |
7202 | return ! (CONST_DOUBLE_LOW (x) & 0x80000000); | |
7203 | case CONST_INT: | |
7204 | return ! (INTVAL (x) & 0x80000000); | |
7205 | case ASHIFTRT: | |
7206 | case SIGN_EXTEND: | |
7207 | return - (GET_MODE (SET_SRC (pat)) == SImode); | |
7208 | default: | |
7209 | return 0; | |
7210 | } | |
7211 | } | |
7212 | ||
e0d80184 DM |
7213 | /* We _ought_ to have only one kind per function, but... */ |
7214 | static rtx sparc_addr_diff_list; | |
7215 | static rtx sparc_addr_list; | |
7216 | ||
7217 | void | |
7218 | sparc_defer_case_vector (lab, vec, diff) | |
7219 | rtx lab, vec; | |
7220 | int diff; | |
7221 | { | |
7222 | vec = gen_rtx_EXPR_LIST (VOIDmode, lab, vec); | |
7223 | if (diff) | |
7224 | sparc_addr_diff_list | |
7225 | = gen_rtx_EXPR_LIST (VOIDmode, vec, sparc_addr_diff_list); | |
7226 | else | |
7227 | sparc_addr_list = gen_rtx_EXPR_LIST (VOIDmode, vec, sparc_addr_list); | |
7228 | } | |
7229 | ||
7230 | static void | |
7231 | sparc_output_addr_vec (vec) | |
7232 | rtx vec; | |
7233 | { | |
7234 | rtx lab = XEXP (vec, 0), body = XEXP (vec, 1); | |
7235 | int idx, vlen = XVECLEN (body, 0); | |
7236 | ||
d1accaa3 JJ |
7237 | #ifdef ASM_OUTPUT_ADDR_VEC_START |
7238 | ASM_OUTPUT_ADDR_VEC_START (asm_out_file); | |
7239 | #endif | |
7240 | ||
e0d80184 DM |
7241 | #ifdef ASM_OUTPUT_CASE_LABEL |
7242 | ASM_OUTPUT_CASE_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab), | |
7243 | NEXT_INSN (lab)); | |
7244 | #else | |
7245 | ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab)); | |
7246 | #endif | |
7247 | ||
7248 | for (idx = 0; idx < vlen; idx++) | |
7249 | { | |
7250 | ASM_OUTPUT_ADDR_VEC_ELT | |
7251 | (asm_out_file, CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 0, idx), 0))); | |
7252 | } | |
d1accaa3 JJ |
7253 | |
7254 | #ifdef ASM_OUTPUT_ADDR_VEC_END | |
7255 | ASM_OUTPUT_ADDR_VEC_END (asm_out_file); | |
7256 | #endif | |
e0d80184 DM |
7257 | } |
7258 | ||
7259 | static void | |
7260 | sparc_output_addr_diff_vec (vec) | |
7261 | rtx vec; | |
7262 | { | |
7263 | rtx lab = XEXP (vec, 0), body = XEXP (vec, 1); | |
7264 | rtx base = XEXP (XEXP (body, 0), 0); | |
7265 | int idx, vlen = XVECLEN (body, 1); | |
7266 | ||
d1accaa3 JJ |
7267 | #ifdef ASM_OUTPUT_ADDR_VEC_START |
7268 | ASM_OUTPUT_ADDR_VEC_START (asm_out_file); | |
7269 | #endif | |
7270 | ||
e0d80184 DM |
7271 | #ifdef ASM_OUTPUT_CASE_LABEL |
7272 | ASM_OUTPUT_CASE_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab), | |
7273 | NEXT_INSN (lab)); | |
7274 | #else | |
7275 | ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab)); | |
7276 | #endif | |
7277 | ||
7278 | for (idx = 0; idx < vlen; idx++) | |
7279 | { | |
7280 | ASM_OUTPUT_ADDR_DIFF_ELT | |
7281 | (asm_out_file, | |
7282 | body, | |
7283 | CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 1, idx), 0)), | |
7284 | CODE_LABEL_NUMBER (base)); | |
7285 | } | |
d1accaa3 JJ |
7286 | |
7287 | #ifdef ASM_OUTPUT_ADDR_VEC_END | |
7288 | ASM_OUTPUT_ADDR_VEC_END (asm_out_file); | |
7289 | #endif | |
e0d80184 DM |
7290 | } |
7291 | ||
7292 | static void | |
7293 | sparc_output_deferred_case_vectors () | |
7294 | { | |
7295 | rtx t; | |
d676da68 | 7296 | int align; |
e0d80184 | 7297 | |
f3b8847b DM |
7298 | if (sparc_addr_list == NULL_RTX |
7299 | && sparc_addr_diff_list == NULL_RTX) | |
7300 | return; | |
7301 | ||
e0d80184 DM |
7302 | /* Align to cache line in the function's code section. */ |
7303 | function_section (current_function_decl); | |
d676da68 DM |
7304 | |
7305 | align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT); | |
7306 | if (align > 0) | |
f3b8847b | 7307 | ASM_OUTPUT_ALIGN (asm_out_file, align); |
e0d80184 DM |
7308 | |
7309 | for (t = sparc_addr_list; t ; t = XEXP (t, 1)) | |
7310 | sparc_output_addr_vec (XEXP (t, 0)); | |
7311 | for (t = sparc_addr_diff_list; t ; t = XEXP (t, 1)) | |
7312 | sparc_output_addr_diff_vec (XEXP (t, 0)); | |
7313 | ||
7314 | sparc_addr_list = sparc_addr_diff_list = NULL_RTX; | |
7315 | } | |
7316 | ||
284d86e9 JC |
7317 | /* Return 0 if the high 32 bits of X (the low word of X, if DImode) are |
7318 | unknown. Return 1 if the high bits are zero, -1 if the register is | |
7319 | sign extended. */ | |
7320 | int | |
7321 | sparc_check_64 (x, insn) | |
7322 | rtx x, insn; | |
7323 | { | |
7324 | /* If a register is set only once it is safe to ignore insns this | |
7325 | code does not know how to handle. The loop will either recognize | |
7326 | the single set and return the correct value or fail to recognize | |
7327 | it and return 0. */ | |
7328 | int set_once = 0; | |
7329 | ||
7330 | if (GET_CODE (x) == REG | |
7331 | && flag_expensive_optimizations | |
7332 | && REG_N_SETS (REGNO (x)) == 1) | |
7333 | set_once = 1; | |
7334 | ||
7335 | if (insn == 0) | |
d6f4ec51 KG |
7336 | { |
7337 | if (set_once) | |
7338 | insn = get_last_insn_anywhere (); | |
7339 | else | |
7340 | return 0; | |
7341 | } | |
284d86e9 | 7342 | |
d6f4ec51 | 7343 | while ((insn = PREV_INSN (insn))) |
284d86e9 JC |
7344 | { |
7345 | switch (GET_CODE (insn)) | |
7346 | { | |
7347 | case JUMP_INSN: | |
7348 | case NOTE: | |
7349 | break; | |
7350 | case CODE_LABEL: | |
7351 | case CALL_INSN: | |
7352 | default: | |
7353 | if (! set_once) | |
7354 | return 0; | |
7355 | break; | |
7356 | case INSN: | |
7357 | { | |
7358 | rtx pat = PATTERN (insn); | |
7359 | if (GET_CODE (pat) != SET) | |
7360 | return 0; | |
7361 | if (rtx_equal_p (x, SET_DEST (pat))) | |
7362 | return set_extends (x, insn); | |
7363 | if (reg_overlap_mentioned_p (SET_DEST (pat), x)) | |
7364 | return 0; | |
7365 | } | |
7366 | } | |
7367 | } | |
7368 | return 0; | |
7369 | } | |
7370 | ||
7371 | char * | |
7372 | sparc_v8plus_shift (operands, insn, opcode) | |
7373 | rtx *operands; | |
7374 | rtx insn; | |
7375 | char *opcode; | |
7376 | { | |
7377 | static char asm_code[60]; | |
7378 | ||
7379 | if (GET_CODE (operands[3]) == SCRATCH) | |
7380 | operands[3] = operands[0]; | |
c6b0465b JC |
7381 | if (GET_CODE (operands[1]) == CONST_INT) |
7382 | { | |
7383 | output_asm_insn ("mov %1,%3", operands); | |
7384 | } | |
7385 | else | |
7386 | { | |
7387 | output_asm_insn ("sllx %H1,32,%3", operands); | |
7388 | if (sparc_check_64 (operands[1], insn) <= 0) | |
7389 | output_asm_insn ("srl %L1,0,%L1", operands); | |
7390 | output_asm_insn ("or %L1,%3,%3", operands); | |
7391 | } | |
284d86e9 JC |
7392 | |
7393 | strcpy(asm_code, opcode); | |
7394 | if (which_alternative != 2) | |
7395 | return strcat (asm_code, " %0,%2,%L0\n\tsrlx %L0,32,%H0"); | |
7396 | else | |
7397 | return strcat (asm_code, " %3,%2,%3\n\tsrlx %3,32,%H0\n\tmov %3,%L0"); | |
7398 | } | |
7399 | ||
7400 | ||
7401 | /* Return 1 if DEST and SRC reference only global and in registers. */ | |
7402 | ||
7403 | int | |
7404 | sparc_return_peephole_ok (dest, src) | |
7405 | rtx dest, src; | |
7406 | { | |
7407 | if (! TARGET_V9) | |
7408 | return 0; | |
7409 | if (leaf_function) | |
7410 | return 0; | |
7411 | if (GET_CODE (src) != CONST_INT | |
7412 | && (GET_CODE (src) != REG || ! IN_OR_GLOBAL_P (src))) | |
7413 | return 0; | |
7414 | return IN_OR_GLOBAL_P (dest); | |
7415 | } |