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ab835497 | 1 | /* Subroutines for insn-output.c for Sun SPARC. |
f1fe6b07 | 2 | Copyright (C) 1987, 88, 89, 92-95, 1996 Free Software Foundation, Inc. |
ab835497 | 3 | Contributed by Michael Tiemann (tiemann@cygnus.com) |
61a55e8b DE |
4 | 64 bit SPARC V9 support by Michael Tiemann, Jim Wilson, and Doug Evans, |
5 | at Cygnus Support. | |
ab835497 RK |
6 | |
7 | This file is part of GNU CC. | |
8 | ||
9 | GNU CC is free software; you can redistribute it and/or modify | |
10 | it under the terms of the GNU General Public License as published by | |
11 | the Free Software Foundation; either version 2, or (at your option) | |
12 | any later version. | |
13 | ||
14 | GNU CC is distributed in the hope that it will be useful, | |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
18 | ||
19 | You should have received a copy of the GNU General Public License | |
20 | along with GNU CC; see the file COPYING. If not, write to | |
c15c9075 RK |
21 | the Free Software Foundation, 59 Temple Place - Suite 330, |
22 | Boston, MA 02111-1307, USA. */ | |
ab835497 RK |
23 | |
24 | #include <stdio.h> | |
25 | #include "config.h" | |
210aa14a | 26 | #include "tree.h" |
ab835497 RK |
27 | #include "rtl.h" |
28 | #include "regs.h" | |
29 | #include "hard-reg-set.h" | |
30 | #include "real.h" | |
31 | #include "insn-config.h" | |
32 | #include "conditions.h" | |
33 | #include "insn-flags.h" | |
34 | #include "output.h" | |
35 | #include "insn-attr.h" | |
36 | #include "flags.h" | |
37 | #include "expr.h" | |
38 | #include "recog.h" | |
39 | ||
61a55e8b DE |
40 | /* 1 if the caller has placed an "unimp" insn immediately after the call. |
41 | This is used in v8 code when calling a function that returns a structure. | |
06b967f9 RK |
42 | v9 doesn't have this. Be careful to have this test be the same as that |
43 | used on the call. */ | |
44 | ||
45 | #define SKIP_CALLERS_UNIMP_P \ | |
46 | (!TARGET_ARCH64 && current_function_returns_struct \ | |
47 | && ! integer_zerop (DECL_SIZE (DECL_RESULT (current_function_decl))) \ | |
48 | && (TREE_CODE (DECL_SIZE (DECL_RESULT (current_function_decl))) \ | |
49 | == INTEGER_CST)) | |
61a55e8b | 50 | |
ab835497 RK |
51 | /* Global variables for machine-dependent things. */ |
52 | ||
61a55e8b DE |
53 | /* Size of frame. Need to know this to emit return insns from leaf procedures. |
54 | ACTUAL_FSIZE is set by compute_frame_size() which is called during the | |
55 | reload pass. This is important as the value is later used in insn | |
56 | scheduling (to see what can go in a delay slot). | |
57 | APPARENT_FSIZE is the size of the stack less the register save area and less | |
58 | the outgoing argument area. It is used when saving call preserved regs. */ | |
59 | static int apparent_fsize; | |
60 | static int actual_fsize; | |
61 | ||
ab835497 RK |
62 | /* Save the operands last given to a compare for use when we |
63 | generate a scc or bcc insn. */ | |
64 | ||
65 | rtx sparc_compare_op0, sparc_compare_op1; | |
66 | ||
61a55e8b DE |
67 | /* Count of named arguments (v9 only). |
68 | ??? INIT_CUMULATIVE_ARGS initializes these, and FUNCTION_ARG_ADVANCE | |
69 | increments SPARC_ARG_COUNT. They are then used by | |
70 | FUNCTION_ARG_CALLEE_COPIES to determine if the argument is really a named | |
71 | argument or not. This hack is necessary because the NAMED argument to the | |
72 | FUNCTION_ARG_XXX macros is not what it says it is: it does not include the | |
73 | last named argument. */ | |
74 | ||
75 | int sparc_arg_count; | |
76 | int sparc_n_named_args; | |
77 | ||
ab835497 RK |
78 | /* We may need an epilogue if we spill too many registers. |
79 | If this is non-zero, then we branch here for the epilogue. */ | |
80 | static rtx leaf_label; | |
81 | ||
82 | #ifdef LEAF_REGISTERS | |
83 | ||
84 | /* Vector to say how input registers are mapped to output | |
85 | registers. FRAME_POINTER_REGNUM cannot be remapped by | |
86 | this function to eliminate it. You must use -fomit-frame-pointer | |
87 | to get that. */ | |
88 | char leaf_reg_remap[] = | |
89 | { 0, 1, 2, 3, 4, 5, 6, 7, | |
90 | -1, -1, -1, -1, -1, -1, 14, -1, | |
91 | -1, -1, -1, -1, -1, -1, -1, -1, | |
92 | 8, 9, 10, 11, 12, 13, -1, 15, | |
93 | ||
94 | 32, 33, 34, 35, 36, 37, 38, 39, | |
95 | 40, 41, 42, 43, 44, 45, 46, 47, | |
96 | 48, 49, 50, 51, 52, 53, 54, 55, | |
61a55e8b DE |
97 | 56, 57, 58, 59, 60, 61, 62, 63, |
98 | 64, 65, 66, 67, 68, 69, 70, 71, | |
99 | 72, 73, 74, 75, 76, 77, 78, 79, | |
100 | 80, 81, 82, 83, 84, 85, 86, 87, | |
101 | 88, 89, 90, 91, 92, 93, 94, 95, | |
c4ce6853 | 102 | 96, 97, 98, 99, 100}; |
ab835497 | 103 | |
6a4bb1fa | 104 | #endif |
ab835497 | 105 | |
ab835497 RK |
106 | /* Name of where we pretend to think the frame pointer points. |
107 | Normally, this is "%fp", but if we are in a leaf procedure, | |
61a55e8b DE |
108 | this is "%sp+something". We record "something" separately as it may be |
109 | too big for reg+constant addressing. */ | |
110 | ||
111 | static char *frame_base_name; | |
112 | static int frame_base_offset; | |
ab835497 RK |
113 | |
114 | static rtx find_addr_reg (); | |
61a55e8b DE |
115 | static void sparc_init_modes (); |
116 | \f | |
117 | /* Option handling. */ | |
118 | ||
16956f6e DE |
119 | struct sparc_cpu_select sparc_select[] = |
120 | { | |
121 | /* switch name, tune arch */ | |
122 | { (char *)0, "default", 1, 1 }, | |
123 | { (char *)0, "-mcpu=", 1, 1 }, | |
124 | { (char *)0, "-mtune=", 1, 0 }, | |
125 | { 0, 0 } | |
126 | }; | |
733f53f5 | 127 | |
16956f6e DE |
128 | /* CPU type. This is set from TARGET_CPU_DEFAULT and -m{cpu,tune}=xxx. */ |
129 | enum processor_type sparc_cpu; | |
733f53f5 | 130 | |
61a55e8b DE |
131 | /* Validate and override various options, and do some machine dependent |
132 | initialization. */ | |
133 | ||
134 | void | |
135 | sparc_override_options () | |
136 | { | |
16956f6e | 137 | /* Map TARGET_CPU_DEFAULT to value for -m{arch,tune}=. */ |
733f53f5 DE |
138 | static struct cpu_default { |
139 | int cpu; | |
140 | char *name; | |
141 | } cpu_default[] = { | |
16956f6e | 142 | { TARGET_CPU_sparc, "cypress" }, |
3592ea0d | 143 | { TARGET_CPU_sparclet, "tsc701" }, |
16956f6e DE |
144 | { TARGET_CPU_sparclite, "f930" }, |
145 | { TARGET_CPU_sparc64, "ultrasparc" }, | |
146 | { 0 } | |
733f53f5 | 147 | }; |
16956f6e DE |
148 | struct cpu_default *def; |
149 | /* Table of values for -m{cpu,tune}=. */ | |
733f53f5 DE |
150 | static struct cpu_table { |
151 | char *name; | |
16956f6e | 152 | enum processor_type processor; |
733f53f5 DE |
153 | int disable; |
154 | int enable; | |
155 | } cpu_table[] = { | |
16956f6e DE |
156 | { "v7", PROCESSOR_V7, MASK_ISA, 0 }, |
157 | { "cypress", PROCESSOR_CYPRESS, MASK_ISA, 0 }, | |
158 | { "v8", PROCESSOR_V8, MASK_ISA, MASK_V8 }, | |
733f53f5 | 159 | /* TI TMS390Z55 supersparc */ |
16956f6e DE |
160 | { "supersparc", PROCESSOR_SUPERSPARC, MASK_ISA, MASK_V8 }, |
161 | { "sparclite", PROCESSOR_SPARCLITE, MASK_ISA, MASK_SPARCLITE }, | |
733f53f5 DE |
162 | /* The Fujitsu MB86930 is the original sparclite chip, with no fpu. |
163 | The Fujitsu MB86934 is the recent sparclite chip, with an fpu. */ | |
16956f6e DE |
164 | { "f930", PROCESSOR_F930, MASK_ISA|MASK_FPU, MASK_SPARCLITE }, |
165 | { "f934", PROCESSOR_F934, MASK_ISA, MASK_SPARCLITE|MASK_FPU }, | |
166 | { "sparclet", PROCESSOR_SPARCLET, MASK_ISA, MASK_SPARCLET }, | |
733f53f5 | 167 | /* TEMIC sparclet */ |
3592ea0d | 168 | { "tsc701", PROCESSOR_TSC701, MASK_ISA, MASK_SPARCLET }, |
16956f6e DE |
169 | /* "v9" is used to specify a true 64 bit architecture. |
170 | "v8plus" is what Sun calls Solaris2 running on UltraSPARC's. */ | |
171 | { "v8plus", PROCESSOR_V8PLUS, MASK_ISA, MASK_V9 }, | |
172 | #if SPARC_ARCH64 | |
173 | { "v9", PROCESSOR_V9, MASK_ISA, MASK_V9 }, | |
174 | #endif | |
733f53f5 | 175 | /* TI ultrasparc */ |
16956f6e | 176 | { "ultrasparc", PROCESSOR_ULTRASPARC, MASK_ISA, MASK_V9 }, |
733f53f5 DE |
177 | { 0 } |
178 | }; | |
16956f6e DE |
179 | struct cpu_table *cpu; |
180 | struct sparc_cpu_select *sel; | |
181 | ||
182 | /* Set the default. */ | |
183 | for (def = &cpu_default[0]; def->name; ++def) | |
184 | if (def->cpu == TARGET_CPU_DEFAULT) | |
185 | break; | |
186 | if (! def->name) | |
187 | abort (); | |
188 | sparc_select[0].string = def->name; | |
189 | ||
190 | for (sel = &sparc_select[0]; sel->name; ++sel) | |
61a55e8b | 191 | { |
16956f6e | 192 | if (sel->string) |
733f53f5 | 193 | { |
16956f6e DE |
194 | for (cpu = &cpu_table[0]; cpu->name; ++cpu) |
195 | if (! strcmp (sel->string, cpu->name)) | |
196 | { | |
197 | if (sel->set_tune_p) | |
198 | sparc_cpu = cpu->processor; | |
199 | ||
200 | if (sel->set_arch_p) | |
201 | { | |
202 | target_flags &= ~cpu->disable; | |
203 | target_flags |= cpu->enable; | |
204 | } | |
205 | break; | |
206 | } | |
207 | ||
208 | if (! cpu->name) | |
209 | error ("bad value (%s) for %s switch", sel->string, sel->name); | |
733f53f5 | 210 | } |
61a55e8b | 211 | } |
97da85b7 | 212 | |
16956f6e DE |
213 | /* Use the deprecated v8 insns for sparc64 in 32 bit mode. */ |
214 | if (TARGET_V9 && TARGET_ARCH32) | |
733f53f5 | 215 | target_flags |= MASK_DEPRECATED_V8_INSNS; |
61a55e8b DE |
216 | |
217 | /* Do various machine dependent initializations. */ | |
218 | sparc_init_modes (); | |
219 | } | |
220 | \f | |
221 | /* Float conversions (v9 only). | |
222 | ||
223 | The floating point registers cannot hold DImode values because SUBREG's | |
224 | on them get the wrong register. "(subreg:SI (reg:DI M int-reg) 0)" is the | |
225 | same as "(subreg:SI (reg:DI N float-reg) 1)", but gcc doesn't know how to | |
226 | turn the "0" to a "1". Therefore, we must explicitly do the conversions | |
227 | to/from int/fp regs. `sparc64_fpconv_stack_slot' is the address of an | |
228 | 8 byte stack slot used during the transfer. | |
229 | ??? I could have used [%fp-16] but I didn't want to add yet another | |
230 | dependence on this. */ | |
231 | /* ??? Can we use assign_stack_temp here? */ | |
232 | ||
233 | static rtx fpconv_stack_temp; | |
234 | ||
235 | /* Called once for each function. */ | |
236 | ||
237 | void | |
238 | sparc64_init_expanders () | |
239 | { | |
240 | fpconv_stack_temp = NULL_RTX; | |
241 | } | |
242 | ||
243 | /* Assign a stack temp for fp/int DImode conversions. */ | |
ab835497 | 244 | |
61a55e8b DE |
245 | rtx |
246 | sparc64_fpconv_stack_temp () | |
247 | { | |
248 | if (fpconv_stack_temp == NULL_RTX) | |
249 | fpconv_stack_temp = | |
250 | assign_stack_local (DImode, GET_MODE_SIZE (DImode), 0); | |
251 | ||
252 | return fpconv_stack_temp; | |
253 | } | |
254 | \f | |
cd5fb1ee DE |
255 | /* Miscellaneous utilities. */ |
256 | ||
257 | /* Nonzero if CODE, a comparison, is suitable for use in v9 conditional move | |
258 | or branch on register contents instructions. */ | |
259 | ||
260 | int | |
261 | v9_regcmp_p (code) | |
262 | enum rtx_code code; | |
263 | { | |
264 | return (code == EQ || code == NE || code == GE || code == LT | |
265 | || code == LE || code == GT); | |
266 | } | |
267 | \f | |
268 | /* Operand constraints. */ | |
269 | ||
ab835497 | 270 | /* Return non-zero only if OP is a register of mode MODE, |
c4ce6853 DE |
271 | or const0_rtx. Don't allow const0_rtx if TARGET_LIVE_G0 because |
272 | %g0 may contain anything. */ | |
273 | ||
ab835497 RK |
274 | int |
275 | reg_or_0_operand (op, mode) | |
276 | rtx op; | |
277 | enum machine_mode mode; | |
278 | { | |
c4ce6853 DE |
279 | if (register_operand (op, mode)) |
280 | return 1; | |
281 | if (TARGET_LIVE_G0) | |
282 | return 0; | |
283 | if (op == const0_rtx) | |
ab835497 | 284 | return 1; |
5b486ce0 | 285 | if (GET_MODE (op) == VOIDmode && GET_CODE (op) == CONST_DOUBLE |
ab835497 RK |
286 | && CONST_DOUBLE_HIGH (op) == 0 |
287 | && CONST_DOUBLE_LOW (op) == 0) | |
288 | return 1; | |
302484ff JW |
289 | if (GET_MODE_CLASS (GET_MODE (op)) == MODE_FLOAT |
290 | && GET_CODE (op) == CONST_DOUBLE | |
291 | && fp_zero_operand (op)) | |
292 | return 1; | |
ab835497 RK |
293 | return 0; |
294 | } | |
295 | ||
302484ff | 296 | /* Nonzero if OP is a floating point value with value 0.0. */ |
c4ce6853 | 297 | |
302484ff JW |
298 | int |
299 | fp_zero_operand (op) | |
300 | rtx op; | |
301 | { | |
302 | REAL_VALUE_TYPE r; | |
303 | ||
304 | REAL_VALUE_FROM_CONST_DOUBLE (r, op); | |
d61ba4f4 | 305 | return (REAL_VALUES_EQUAL (r, dconst0) && ! REAL_VALUE_MINUS_ZERO (r)); |
302484ff JW |
306 | } |
307 | ||
61a55e8b DE |
308 | /* Nonzero if OP is an integer register. */ |
309 | ||
310 | int | |
311 | intreg_operand (op, mode) | |
312 | rtx op; | |
313 | enum machine_mode mode; | |
314 | { | |
315 | return (register_operand (op, SImode) | |
a9e27770 | 316 | || (TARGET_ARCH64 && register_operand (op, DImode))); |
61a55e8b DE |
317 | } |
318 | ||
319 | /* Nonzero if OP is a floating point condition code register. */ | |
320 | ||
321 | int | |
c4ce6853 | 322 | fcc_reg_operand (op, mode) |
61a55e8b DE |
323 | rtx op; |
324 | enum machine_mode mode; | |
325 | { | |
326 | /* This can happen when recog is called from combine. Op may be a MEM. | |
327 | Fail instead of calling abort in this case. */ | |
c4ce6853 | 328 | if (GET_CODE (op) != REG) |
61a55e8b | 329 | return 0; |
304b7a23 | 330 | |
c4ce6853 | 331 | if (mode != VOIDmode && mode != GET_MODE (op)) |
61a55e8b | 332 | return 0; |
304b7a23 DE |
333 | if (mode == VOIDmode |
334 | && (GET_MODE (op) != CCFPmode && GET_MODE (op) != CCFPEmode)) | |
335 | return 0; | |
61a55e8b | 336 | |
c4ce6853 | 337 | #if 0 /* ??? ==> 1 when %fcc0-3 are pseudos first. See gen_compare_reg(). */ |
61a55e8b DE |
338 | if (reg_renumber == 0) |
339 | return REGNO (op) >= FIRST_PSEUDO_REGISTER; | |
340 | return REGNO_OK_FOR_CCFP_P (REGNO (op)); | |
341 | #else | |
c4ce6853 | 342 | return (unsigned) REGNO (op) - SPARC_FIRST_V9_FCC_REG < 4; |
61a55e8b DE |
343 | #endif |
344 | } | |
345 | ||
c4ce6853 DE |
346 | /* Nonzero if OP is an integer or floating point condition code register. */ |
347 | ||
348 | int | |
349 | icc_or_fcc_reg_operand (op, mode) | |
350 | rtx op; | |
351 | enum machine_mode mode; | |
352 | { | |
353 | if (GET_CODE (op) == REG && REGNO (op) == SPARC_ICC_REG) | |
304b7a23 DE |
354 | { |
355 | if (mode != VOIDmode && mode != GET_MODE (op)) | |
356 | return 0; | |
357 | if (mode == VOIDmode | |
358 | && GET_MODE (op) != CCmode && GET_MODE (op) != CCXmode) | |
359 | return 0; | |
360 | return 1; | |
361 | } | |
362 | ||
c4ce6853 DE |
363 | return fcc_reg_operand (op, mode); |
364 | } | |
365 | ||
ab835497 RK |
366 | /* Nonzero if OP can appear as the dest of a RESTORE insn. */ |
367 | int | |
368 | restore_operand (op, mode) | |
369 | rtx op; | |
370 | enum machine_mode mode; | |
371 | { | |
372 | return (GET_CODE (op) == REG && GET_MODE (op) == mode | |
373 | && (REGNO (op) < 8 || (REGNO (op) >= 24 && REGNO (op) < 32))); | |
374 | } | |
375 | ||
401cec23 JW |
376 | /* Call insn on SPARC can take a PC-relative constant address, or any regular |
377 | memory address. */ | |
ab835497 RK |
378 | |
379 | int | |
380 | call_operand (op, mode) | |
381 | rtx op; | |
382 | enum machine_mode mode; | |
383 | { | |
384 | if (GET_CODE (op) != MEM) | |
385 | abort (); | |
386 | op = XEXP (op, 0); | |
2445f289 | 387 | return (symbolic_operand (op, mode) || memory_address_p (Pmode, op)); |
ab835497 RK |
388 | } |
389 | ||
390 | int | |
391 | call_operand_address (op, mode) | |
392 | rtx op; | |
393 | enum machine_mode mode; | |
394 | { | |
2445f289 | 395 | return (symbolic_operand (op, mode) || memory_address_p (Pmode, op)); |
ab835497 RK |
396 | } |
397 | ||
398 | /* Returns 1 if OP is either a symbol reference or a sum of a symbol | |
399 | reference and a constant. */ | |
400 | ||
401 | int | |
402 | symbolic_operand (op, mode) | |
403 | register rtx op; | |
404 | enum machine_mode mode; | |
405 | { | |
406 | switch (GET_CODE (op)) | |
407 | { | |
408 | case SYMBOL_REF: | |
409 | case LABEL_REF: | |
410 | return 1; | |
411 | ||
412 | case CONST: | |
413 | op = XEXP (op, 0); | |
414 | return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF | |
415 | || GET_CODE (XEXP (op, 0)) == LABEL_REF) | |
416 | && GET_CODE (XEXP (op, 1)) == CONST_INT); | |
417 | ||
228b4037 | 418 | /* ??? This clause seems to be irrelevant. */ |
ab835497 RK |
419 | case CONST_DOUBLE: |
420 | return GET_MODE (op) == mode; | |
421 | ||
422 | default: | |
423 | return 0; | |
424 | } | |
425 | } | |
426 | ||
427 | /* Return truth value of statement that OP is a symbolic memory | |
428 | operand of mode MODE. */ | |
429 | ||
430 | int | |
431 | symbolic_memory_operand (op, mode) | |
432 | rtx op; | |
433 | enum machine_mode mode; | |
434 | { | |
435 | if (GET_CODE (op) == SUBREG) | |
436 | op = SUBREG_REG (op); | |
437 | if (GET_CODE (op) != MEM) | |
438 | return 0; | |
439 | op = XEXP (op, 0); | |
440 | return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST | |
441 | || GET_CODE (op) == HIGH || GET_CODE (op) == LABEL_REF); | |
442 | } | |
443 | ||
5ab7138b DE |
444 | /* Return truth value of statement that OP is a LABEL_REF of mode MODE. */ |
445 | ||
446 | int | |
447 | label_ref_operand (op, mode) | |
448 | rtx op; | |
449 | enum machine_mode mode; | |
450 | { | |
451 | if (GET_CODE (op) != LABEL_REF) | |
452 | return 0; | |
453 | if (GET_MODE (op) != mode) | |
454 | return 0; | |
455 | return 1; | |
456 | } | |
457 | ||
95726648 DE |
458 | /* Return 1 if the operand is an argument used in generating pic references |
459 | in either the medium/low or medium/anywhere code models of sparc64. */ | |
460 | ||
461 | int | |
462 | sp64_medium_pic_operand (op, mode) | |
463 | rtx op; | |
464 | enum machine_mode mode; | |
465 | { | |
466 | /* Check for (const (minus (symbol_ref:GOT) | |
467 | (const (minus (label) (pc))))). */ | |
468 | if (GET_CODE (op) != CONST) | |
469 | return 0; | |
470 | op = XEXP (op, 0); | |
471 | if (GET_CODE (op) != MINUS) | |
472 | return 0; | |
473 | if (GET_CODE (XEXP (op, 0)) != SYMBOL_REF) | |
474 | return 0; | |
475 | /* ??? Ensure symbol is GOT. */ | |
476 | if (GET_CODE (XEXP (op, 1)) != CONST) | |
477 | return 0; | |
478 | if (GET_CODE (XEXP (XEXP (op, 1), 0)) != MINUS) | |
479 | return 0; | |
480 | return 1; | |
481 | } | |
482 | ||
61a55e8b DE |
483 | /* Return 1 if the operand is a data segment reference. This includes |
484 | the readonly data segment, or in other words anything but the text segment. | |
485 | This is needed in the medium/anywhere code model on v9. These values | |
486 | are accessed with MEDANY_BASE_REG. */ | |
487 | ||
488 | int | |
489 | data_segment_operand (op, mode) | |
490 | rtx op; | |
491 | enum machine_mode mode; | |
492 | { | |
493 | switch (GET_CODE (op)) | |
494 | { | |
495 | case SYMBOL_REF : | |
496 | return ! SYMBOL_REF_FLAG (op); | |
497 | case PLUS : | |
95726648 DE |
498 | /* Assume canonical format of symbol + constant. |
499 | Fall through. */ | |
61a55e8b DE |
500 | case CONST : |
501 | return data_segment_operand (XEXP (op, 0)); | |
502 | default : | |
503 | return 0; | |
504 | } | |
505 | } | |
506 | ||
507 | /* Return 1 if the operand is a text segment reference. | |
508 | This is needed in the medium/anywhere code model on v9. */ | |
509 | ||
510 | int | |
511 | text_segment_operand (op, mode) | |
512 | rtx op; | |
513 | enum machine_mode mode; | |
514 | { | |
515 | switch (GET_CODE (op)) | |
516 | { | |
517 | case LABEL_REF : | |
518 | return 1; | |
519 | case SYMBOL_REF : | |
520 | return SYMBOL_REF_FLAG (op); | |
521 | case PLUS : | |
95726648 DE |
522 | /* Assume canonical format of symbol + constant. |
523 | Fall through. */ | |
61a55e8b DE |
524 | case CONST : |
525 | return text_segment_operand (XEXP (op, 0)); | |
526 | default : | |
527 | return 0; | |
528 | } | |
529 | } | |
530 | ||
ab835497 RK |
531 | /* Return 1 if the operand is either a register or a memory operand that is |
532 | not symbolic. */ | |
533 | ||
534 | int | |
535 | reg_or_nonsymb_mem_operand (op, mode) | |
536 | register rtx op; | |
537 | enum machine_mode mode; | |
538 | { | |
539 | if (register_operand (op, mode)) | |
540 | return 1; | |
541 | ||
542 | if (memory_operand (op, mode) && ! symbolic_memory_operand (op, mode)) | |
543 | return 1; | |
544 | ||
545 | return 0; | |
546 | } | |
547 | ||
548 | int | |
549 | sparc_operand (op, mode) | |
550 | rtx op; | |
551 | enum machine_mode mode; | |
552 | { | |
553 | if (register_operand (op, mode)) | |
554 | return 1; | |
555 | if (GET_CODE (op) == CONST_INT) | |
556 | return SMALL_INT (op); | |
557 | if (GET_MODE (op) != mode) | |
558 | return 0; | |
559 | if (GET_CODE (op) == SUBREG) | |
560 | op = SUBREG_REG (op); | |
561 | if (GET_CODE (op) != MEM) | |
562 | return 0; | |
563 | ||
564 | op = XEXP (op, 0); | |
565 | if (GET_CODE (op) == LO_SUM) | |
566 | return (GET_CODE (XEXP (op, 0)) == REG | |
567 | && symbolic_operand (XEXP (op, 1), Pmode)); | |
568 | return memory_address_p (mode, op); | |
569 | } | |
570 | ||
571 | int | |
572 | move_operand (op, mode) | |
573 | rtx op; | |
574 | enum machine_mode mode; | |
575 | { | |
576 | if (mode == DImode && arith_double_operand (op, mode)) | |
577 | return 1; | |
578 | if (register_operand (op, mode)) | |
579 | return 1; | |
580 | if (GET_CODE (op) == CONST_INT) | |
581 | return (SMALL_INT (op) || (INTVAL (op) & 0x3ff) == 0); | |
582 | ||
583 | if (GET_MODE (op) != mode) | |
584 | return 0; | |
585 | if (GET_CODE (op) == SUBREG) | |
586 | op = SUBREG_REG (op); | |
587 | if (GET_CODE (op) != MEM) | |
588 | return 0; | |
589 | op = XEXP (op, 0); | |
590 | if (GET_CODE (op) == LO_SUM) | |
591 | return (register_operand (XEXP (op, 0), Pmode) | |
592 | && CONSTANT_P (XEXP (op, 1))); | |
593 | return memory_address_p (mode, op); | |
594 | } | |
595 | ||
ab835497 | 596 | int |
6ac34277 | 597 | splittable_symbolic_memory_operand (op, mode) |
ab835497 RK |
598 | rtx op; |
599 | enum machine_mode mode; | |
600 | { | |
6ac34277 DE |
601 | if (GET_CODE (op) != MEM) |
602 | return 0; | |
603 | if (! symbolic_operand (XEXP (op, 0), Pmode)) | |
604 | return 0; | |
605 | return 1; | |
606 | } | |
607 | ||
608 | int | |
609 | splittable_immediate_memory_operand (op, mode) | |
610 | rtx op; | |
611 | enum machine_mode mode; | |
612 | { | |
613 | if (GET_CODE (op) != MEM) | |
614 | return 0; | |
615 | if (! immediate_operand (XEXP (op, 0), Pmode)) | |
616 | return 0; | |
617 | return 1; | |
ab835497 RK |
618 | } |
619 | ||
620 | /* Return truth value of whether OP is EQ or NE. */ | |
621 | ||
622 | int | |
623 | eq_or_neq (op, mode) | |
624 | rtx op; | |
625 | enum machine_mode mode; | |
626 | { | |
627 | return (GET_CODE (op) == EQ || GET_CODE (op) == NE); | |
628 | } | |
629 | ||
630 | /* Return 1 if this is a comparison operator, but not an EQ, NE, GEU, | |
631 | or LTU for non-floating-point. We handle those specially. */ | |
632 | ||
633 | int | |
634 | normal_comp_operator (op, mode) | |
635 | rtx op; | |
636 | enum machine_mode mode; | |
637 | { | |
638 | enum rtx_code code = GET_CODE (op); | |
639 | ||
640 | if (GET_RTX_CLASS (code) != '<') | |
641 | return 0; | |
642 | ||
4d449554 JW |
643 | if (GET_MODE (XEXP (op, 0)) == CCFPmode |
644 | || GET_MODE (XEXP (op, 0)) == CCFPEmode) | |
ab835497 RK |
645 | return 1; |
646 | ||
647 | return (code != NE && code != EQ && code != GEU && code != LTU); | |
648 | } | |
649 | ||
650 | /* Return 1 if this is a comparison operator. This allows the use of | |
651 | MATCH_OPERATOR to recognize all the branch insns. */ | |
652 | ||
653 | int | |
654 | noov_compare_op (op, mode) | |
655 | register rtx op; | |
656 | enum machine_mode mode; | |
657 | { | |
658 | enum rtx_code code = GET_CODE (op); | |
659 | ||
660 | if (GET_RTX_CLASS (code) != '<') | |
661 | return 0; | |
662 | ||
663 | if (GET_MODE (XEXP (op, 0)) == CC_NOOVmode) | |
664 | /* These are the only branches which work with CC_NOOVmode. */ | |
665 | return (code == EQ || code == NE || code == GE || code == LT); | |
666 | return 1; | |
667 | } | |
668 | ||
61a55e8b DE |
669 | /* Nonzero if OP is a comparison operator suitable for use in v9 |
670 | conditional move or branch on register contents instructions. */ | |
671 | ||
672 | int | |
673 | v9_regcmp_op (op, mode) | |
674 | register rtx op; | |
675 | enum machine_mode mode; | |
676 | { | |
677 | enum rtx_code code = GET_CODE (op); | |
678 | ||
679 | if (GET_RTX_CLASS (code) != '<') | |
680 | return 0; | |
681 | ||
cd5fb1ee | 682 | return v9_regcmp_p (code); |
61a55e8b DE |
683 | } |
684 | ||
ab835497 RK |
685 | /* Return 1 if this is a SIGN_EXTEND or ZERO_EXTEND operation. */ |
686 | ||
687 | int | |
688 | extend_op (op, mode) | |
689 | rtx op; | |
690 | enum machine_mode mode; | |
691 | { | |
692 | return GET_CODE (op) == SIGN_EXTEND || GET_CODE (op) == ZERO_EXTEND; | |
693 | } | |
694 | ||
695 | /* Return nonzero if OP is an operator of mode MODE which can set | |
696 | the condition codes explicitly. We do not include PLUS and MINUS | |
697 | because these require CC_NOOVmode, which we handle explicitly. */ | |
698 | ||
699 | int | |
700 | cc_arithop (op, mode) | |
701 | rtx op; | |
702 | enum machine_mode mode; | |
703 | { | |
704 | if (GET_CODE (op) == AND | |
705 | || GET_CODE (op) == IOR | |
706 | || GET_CODE (op) == XOR) | |
707 | return 1; | |
708 | ||
709 | return 0; | |
710 | } | |
711 | ||
712 | /* Return nonzero if OP is an operator of mode MODE which can bitwise | |
713 | complement its second operand and set the condition codes explicitly. */ | |
714 | ||
715 | int | |
716 | cc_arithopn (op, mode) | |
717 | rtx op; | |
718 | enum machine_mode mode; | |
719 | { | |
720 | /* XOR is not here because combine canonicalizes (xor (not ...) ...) | |
721 | and (xor ... (not ...)) to (not (xor ...)). */ | |
722 | return (GET_CODE (op) == AND | |
723 | || GET_CODE (op) == IOR); | |
724 | } | |
725 | \f | |
58cbf20e DE |
726 | /* Return true if OP is a register, or is a CONST_INT that can fit in a |
727 | signed 13 bit immediate field. This is an acceptable SImode operand for | |
728 | most 3 address instructions. */ | |
ab835497 RK |
729 | |
730 | int | |
731 | arith_operand (op, mode) | |
732 | rtx op; | |
733 | enum machine_mode mode; | |
734 | { | |
735 | return (register_operand (op, mode) | |
736 | || (GET_CODE (op) == CONST_INT && SMALL_INT (op))); | |
737 | } | |
738 | ||
58cbf20e DE |
739 | /* Return true if OP is a register, or is a CONST_INT that can fit in a |
740 | signed 11 bit immediate field. This is an acceptable SImode operand for | |
741 | the movcc instructions. */ | |
61a55e8b DE |
742 | |
743 | int | |
744 | arith11_operand (op, mode) | |
745 | rtx op; | |
746 | enum machine_mode mode; | |
747 | { | |
748 | return (register_operand (op, mode) | |
58cbf20e | 749 | || (GET_CODE (op) == CONST_INT && SPARC_SIMM11_P (INTVAL (op)))); |
61a55e8b DE |
750 | } |
751 | ||
58cbf20e DE |
752 | /* Return true if OP is a register, or is a CONST_INT that can fit in a |
753 | signed 10 bit immediate field. This is an acceptable SImode operand for | |
754 | the movrcc instructions. */ | |
61a55e8b DE |
755 | |
756 | int | |
757 | arith10_operand (op, mode) | |
758 | rtx op; | |
759 | enum machine_mode mode; | |
760 | { | |
761 | return (register_operand (op, mode) | |
58cbf20e | 762 | || (GET_CODE (op) == CONST_INT && SPARC_SIMM10_P (INTVAL (op)))); |
61a55e8b DE |
763 | } |
764 | ||
23b8a89f JW |
765 | /* Return true if OP is a register, is a CONST_INT that fits in a 13 bit |
766 | immediate field, or is a CONST_DOUBLE whose both parts fit in a 13 bit | |
61a55e8b DE |
767 | immediate field. |
768 | v9: Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that | |
769 | can fit in a 13 bit immediate field. This is an acceptable DImode operand | |
770 | for most 3 address instructions. */ | |
ab835497 RK |
771 | |
772 | int | |
773 | arith_double_operand (op, mode) | |
774 | rtx op; | |
775 | enum machine_mode mode; | |
776 | { | |
777 | return (register_operand (op, mode) | |
23b8a89f | 778 | || (GET_CODE (op) == CONST_INT && SMALL_INT (op)) |
a9e27770 | 779 | || (! TARGET_ARCH64 |
61a55e8b | 780 | && GET_CODE (op) == CONST_DOUBLE |
ab835497 | 781 | && (unsigned) (CONST_DOUBLE_LOW (op) + 0x1000) < 0x2000 |
61a55e8b | 782 | && (unsigned) (CONST_DOUBLE_HIGH (op) + 0x1000) < 0x2000) |
a9e27770 | 783 | || (TARGET_ARCH64 |
61a55e8b DE |
784 | && GET_CODE (op) == CONST_DOUBLE |
785 | && (unsigned) (CONST_DOUBLE_LOW (op) + 0x1000) < 0x2000 | |
786 | && ((CONST_DOUBLE_HIGH (op) == -1 | |
787 | && (CONST_DOUBLE_LOW (op) & 0x1000) == 0x1000) | |
788 | || (CONST_DOUBLE_HIGH (op) == 0 | |
789 | && (CONST_DOUBLE_LOW (op) & 0x1000) == 0)))); | |
790 | } | |
791 | ||
792 | /* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that | |
793 | can fit in an 11 bit immediate field. This is an acceptable DImode | |
794 | operand for the movcc instructions. */ | |
795 | /* ??? Replace with arith11_operand? */ | |
796 | ||
797 | int | |
798 | arith11_double_operand (op, mode) | |
799 | rtx op; | |
800 | enum machine_mode mode; | |
801 | { | |
802 | return (register_operand (op, mode) | |
803 | || (GET_CODE (op) == CONST_DOUBLE | |
804 | && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode) | |
805 | && (unsigned) (CONST_DOUBLE_LOW (op) + 0x400) < 0x800 | |
806 | && ((CONST_DOUBLE_HIGH (op) == -1 | |
807 | && (CONST_DOUBLE_LOW (op) & 0x400) == 0x400) | |
808 | || (CONST_DOUBLE_HIGH (op) == 0 | |
809 | && (CONST_DOUBLE_LOW (op) & 0x400) == 0))) | |
810 | || (GET_CODE (op) == CONST_INT | |
811 | && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode) | |
812 | && (unsigned) (INTVAL (op) + 0x400) < 0x800)); | |
813 | } | |
814 | ||
815 | /* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that | |
816 | can fit in an 10 bit immediate field. This is an acceptable DImode | |
817 | operand for the movrcc instructions. */ | |
818 | /* ??? Replace with arith10_operand? */ | |
819 | ||
820 | int | |
821 | arith10_double_operand (op, mode) | |
822 | rtx op; | |
823 | enum machine_mode mode; | |
824 | { | |
825 | return (register_operand (op, mode) | |
826 | || (GET_CODE (op) == CONST_DOUBLE | |
827 | && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode) | |
828 | && (unsigned) (CONST_DOUBLE_LOW (op) + 0x200) < 0x400 | |
829 | && ((CONST_DOUBLE_HIGH (op) == -1 | |
830 | && (CONST_DOUBLE_LOW (op) & 0x200) == 0x200) | |
831 | || (CONST_DOUBLE_HIGH (op) == 0 | |
832 | && (CONST_DOUBLE_LOW (op) & 0x200) == 0))) | |
833 | || (GET_CODE (op) == CONST_INT | |
834 | && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode) | |
835 | && (unsigned) (INTVAL (op) + 0x200) < 0x400)); | |
ab835497 RK |
836 | } |
837 | ||
838 | /* Return truth value of whether OP is a integer which fits the | |
228b4037 JW |
839 | range constraining immediate operands in most three-address insns, |
840 | which have a 13 bit immediate field. */ | |
ab835497 RK |
841 | |
842 | int | |
843 | small_int (op, mode) | |
844 | rtx op; | |
845 | enum machine_mode mode; | |
846 | { | |
847 | return (GET_CODE (op) == CONST_INT && SMALL_INT (op)); | |
848 | } | |
849 | ||
9b3fad96 JW |
850 | /* Recognize operand values for the umul instruction. That instruction sign |
851 | extends immediate values just like all other sparc instructions, but | |
852 | interprets the extended result as an unsigned number. */ | |
853 | ||
854 | int | |
855 | uns_small_int (op, mode) | |
856 | rtx op; | |
857 | enum machine_mode mode; | |
858 | { | |
859 | #if HOST_BITS_PER_WIDE_INT > 32 | |
860 | /* All allowed constants will fit a CONST_INT. */ | |
861 | return (GET_CODE (op) == CONST_INT | |
862 | && ((INTVAL (op) >= 0 && INTVAL (op) < 0x1000) | |
863 | || (INTVAL (op) >= 0xFFFFF000 && INTVAL (op) < 0x100000000L))); | |
864 | #else | |
865 | return ((GET_CODE (op) == CONST_INT && (unsigned) INTVAL (op) < 0x1000) | |
866 | || (GET_CODE (op) == CONST_DOUBLE | |
867 | && CONST_DOUBLE_HIGH (op) == 0 | |
868 | && (unsigned) CONST_DOUBLE_LOW (op) - 0xFFFFF000 < 0x1000)); | |
869 | #endif | |
870 | } | |
871 | ||
872 | int | |
873 | uns_arith_operand (op, mode) | |
874 | rtx op; | |
875 | enum machine_mode mode; | |
876 | { | |
877 | return register_operand (op, mode) || uns_small_int (op, mode); | |
878 | } | |
879 | ||
ab835497 RK |
880 | /* Return truth value of statement that OP is a call-clobbered register. */ |
881 | int | |
882 | clobbered_register (op, mode) | |
883 | rtx op; | |
884 | enum machine_mode mode; | |
885 | { | |
886 | return (GET_CODE (op) == REG && call_used_regs[REGNO (op)]); | |
887 | } | |
888 | \f | |
889 | /* X and Y are two things to compare using CODE. Emit the compare insn and | |
61a55e8b | 890 | return the rtx for the cc reg in the proper mode. */ |
ab835497 RK |
891 | |
892 | rtx | |
893 | gen_compare_reg (code, x, y) | |
894 | enum rtx_code code; | |
895 | rtx x, y; | |
896 | { | |
679655e6 | 897 | enum machine_mode mode = SELECT_CC_MODE (code, x, y); |
61a55e8b DE |
898 | rtx cc_reg; |
899 | ||
900 | /* ??? We don't have movcc patterns so we cannot generate pseudo regs for the | |
c4ce6853 | 901 | fcc regs (cse can't tell they're really call clobbered regs and will |
61a55e8b DE |
902 | remove a duplicate comparison even if there is an intervening function |
903 | call - it will then try to reload the cc reg via an int reg which is why | |
904 | we need the movcc patterns). It is possible to provide the movcc | |
905 | patterns by using the ldxfsr/stxfsr v9 insns. I tried it: you need two | |
906 | registers (say %g1,%g5) and it takes about 6 insns. A better fix would be | |
ddd5a7c1 | 907 | to tell cse that CCFPE mode registers (even pseudos) are call |
61a55e8b DE |
908 | clobbered. */ |
909 | ||
910 | /* ??? This is an experiment. Rather than making changes to cse which may | |
911 | or may not be easy/clean, we do our own cse. This is possible because | |
912 | we will generate hard registers. Cse knows they're call clobbered (it | |
913 | doesn't know the same thing about pseudos). If we guess wrong, no big | |
914 | deal, but if we win, great! */ | |
915 | ||
916 | if (TARGET_V9 && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) | |
917 | #if 1 /* experiment */ | |
918 | { | |
919 | int reg; | |
920 | /* We cycle through the registers to ensure they're all exercised. */ | |
c4ce6853 DE |
921 | static int next_fcc_reg = 0; |
922 | /* Previous x,y for each fcc reg. */ | |
61a55e8b DE |
923 | static rtx prev_args[4][2]; |
924 | ||
925 | /* Scan prev_args for x,y. */ | |
926 | for (reg = 0; reg < 4; reg++) | |
927 | if (prev_args[reg][0] == x && prev_args[reg][1] == y) | |
928 | break; | |
929 | if (reg == 4) | |
930 | { | |
c4ce6853 | 931 | reg = next_fcc_reg; |
61a55e8b DE |
932 | prev_args[reg][0] = x; |
933 | prev_args[reg][1] = y; | |
c4ce6853 | 934 | next_fcc_reg = (next_fcc_reg + 1) & 3; |
61a55e8b | 935 | } |
c4ce6853 | 936 | cc_reg = gen_rtx (REG, mode, reg + SPARC_FIRST_V9_FCC_REG); |
61a55e8b DE |
937 | } |
938 | #else | |
939 | cc_reg = gen_reg_rtx (mode); | |
940 | #endif /* ! experiment */ | |
c4ce6853 DE |
941 | else if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) |
942 | cc_reg = gen_rtx (REG, mode, SPARC_FCC_REG); | |
61a55e8b | 943 | else |
c4ce6853 | 944 | cc_reg = gen_rtx (REG, mode, SPARC_ICC_REG); |
ab835497 RK |
945 | |
946 | emit_insn (gen_rtx (SET, VOIDmode, cc_reg, | |
947 | gen_rtx (COMPARE, mode, x, y))); | |
948 | ||
949 | return cc_reg; | |
950 | } | |
61a55e8b DE |
951 | |
952 | /* This function is used for v9 only. | |
953 | CODE is the code for an Scc's comparison. | |
954 | OPERANDS[0] is the target of the Scc insn. | |
955 | OPERANDS[1] is the value we compare against const0_rtx (which hasn't | |
956 | been generated yet). | |
957 | ||
958 | This function is needed to turn | |
959 | ||
960 | (set (reg:SI 110) | |
961 | (gt (reg:CCX 0 %g0) | |
962 | (const_int 0))) | |
963 | into | |
964 | (set (reg:SI 110) | |
965 | (gt:DI (reg:CCX 0 %g0) | |
966 | (const_int 0))) | |
967 | ||
968 | IE: The instruction recognizer needs to see the mode of the comparison to | |
969 | find the right instruction. We could use "gt:DI" right in the | |
970 | define_expand, but leaving it out allows us to handle DI, SI, etc. | |
971 | ||
972 | We refer to the global sparc compare operands sparc_compare_op0 and | |
973 | sparc_compare_op1. | |
974 | ||
975 | ??? Some of this is outdated as the scc insns set the mode of the | |
976 | comparison now. | |
977 | ||
978 | ??? We optimize for the case where op1 is 0 and the comparison allows us to | |
979 | use the "movrCC" insns. This reduces the generated code from three to two | |
980 | insns. This way seems too brute force though. Is there a more elegant way | |
981 | to achieve the same effect? | |
a9e27770 | 982 | */ |
61a55e8b DE |
983 | |
984 | int | |
985 | gen_v9_scc (compare_code, operands) | |
986 | enum rtx_code compare_code; | |
987 | register rtx *operands; | |
988 | { | |
989 | rtx temp; | |
990 | ||
a9e27770 DE |
991 | /* It might be that we'll never be called if this is true, |
992 | but keep this here for documentation at least. */ | |
993 | if (! TARGET_ARCH64 | |
994 | && (GET_MODE (sparc_compare_op0) == DImode | |
995 | || GET_MODE (operands[0]) == DImode)) | |
996 | return 0; | |
997 | ||
998 | /* Try to use the movrCC insns. */ | |
999 | if (TARGET_ARCH64 | |
1000 | && GET_MODE_CLASS (GET_MODE (sparc_compare_op0)) == MODE_INT | |
61a55e8b | 1001 | && sparc_compare_op1 == const0_rtx |
a9e27770 | 1002 | && v9_regcmp_p (compare_code)) |
61a55e8b DE |
1003 | { |
1004 | /* Special case for op0 != 0. This can be done with one instruction if | |
1005 | op0 can be clobbered. We store to a temp, and then clobber the temp, | |
1006 | but the combiner will remove the first insn. */ | |
1007 | ||
1008 | if (compare_code == NE | |
1009 | && GET_MODE (operands[0]) == DImode | |
1010 | && GET_MODE (sparc_compare_op0) == DImode) | |
1011 | { | |
1012 | emit_insn (gen_rtx (SET, VOIDmode, operands[0], sparc_compare_op0)); | |
1013 | emit_insn (gen_rtx (SET, VOIDmode, operands[0], | |
304b7a23 | 1014 | gen_rtx (IF_THEN_ELSE, DImode, |
61a55e8b DE |
1015 | gen_rtx (compare_code, DImode, |
1016 | sparc_compare_op0, const0_rtx), | |
1017 | const1_rtx, | |
1018 | operands[0]))); | |
1019 | return 1; | |
1020 | } | |
1021 | ||
1022 | emit_insn (gen_rtx (SET, VOIDmode, operands[0], const0_rtx)); | |
1023 | if (GET_MODE (sparc_compare_op0) != DImode) | |
1024 | { | |
1025 | temp = gen_reg_rtx (DImode); | |
1026 | convert_move (temp, sparc_compare_op0, 0); | |
1027 | } | |
1028 | else | |
1029 | { | |
1030 | temp = sparc_compare_op0; | |
1031 | } | |
1032 | emit_insn (gen_rtx (SET, VOIDmode, operands[0], | |
304b7a23 | 1033 | gen_rtx (IF_THEN_ELSE, GET_MODE (operands[0]), |
61a55e8b DE |
1034 | gen_rtx (compare_code, DImode, |
1035 | temp, const0_rtx), | |
1036 | const1_rtx, | |
1037 | operands[0]))); | |
1038 | return 1; | |
1039 | } | |
1040 | else | |
1041 | { | |
1042 | operands[1] = gen_compare_reg (compare_code, | |
1043 | sparc_compare_op0, sparc_compare_op1); | |
1044 | ||
1045 | switch (GET_MODE (operands[1])) | |
1046 | { | |
1047 | case CCmode : | |
1048 | case CCXmode : | |
1049 | case CCFPEmode : | |
1050 | case CCFPmode : | |
1051 | break; | |
1052 | default : | |
1053 | abort (); | |
1054 | } | |
304b7a23 DE |
1055 | emit_insn (gen_rtx (SET, VOIDmode, operands[0], const0_rtx)); |
1056 | emit_insn (gen_rtx (SET, VOIDmode, operands[0], | |
1057 | gen_rtx (IF_THEN_ELSE, GET_MODE (operands[0]), | |
1058 | gen_rtx (compare_code, | |
1059 | GET_MODE (operands[1]), | |
1060 | operands[1], const0_rtx), | |
1061 | const1_rtx, operands[0]))); | |
1062 | return 1; | |
61a55e8b DE |
1063 | } |
1064 | } | |
1065 | ||
1066 | /* Emit a conditional jump insn for the v9 architecture using comparison code | |
1067 | CODE and jump target LABEL. | |
1068 | This function exists to take advantage of the v9 brxx insns. */ | |
1069 | ||
1070 | void | |
1071 | emit_v9_brxx_insn (code, op0, label) | |
1072 | enum rtx_code code; | |
1073 | rtx op0, label; | |
1074 | { | |
1075 | emit_jump_insn (gen_rtx (SET, VOIDmode, | |
1076 | pc_rtx, | |
1077 | gen_rtx (IF_THEN_ELSE, VOIDmode, | |
1078 | gen_rtx (code, GET_MODE (op0), | |
1079 | op0, const0_rtx), | |
1080 | gen_rtx (LABEL_REF, VOIDmode, label), | |
1081 | pc_rtx))); | |
1082 | } | |
ab835497 RK |
1083 | \f |
1084 | /* Return nonzero if a return peephole merging return with | |
1085 | setting of output register is ok. */ | |
1086 | int | |
1087 | leaf_return_peephole_ok () | |
1088 | { | |
1089 | return (actual_fsize == 0); | |
1090 | } | |
1091 | ||
1092 | /* Return nonzero if TRIAL can go into the function epilogue's | |
1093 | delay slot. SLOT is the slot we are trying to fill. */ | |
1094 | ||
1095 | int | |
1096 | eligible_for_epilogue_delay (trial, slot) | |
1097 | rtx trial; | |
1098 | int slot; | |
1099 | { | |
ab835497 RK |
1100 | rtx pat, src; |
1101 | ||
1102 | if (slot >= 1) | |
1103 | return 0; | |
1104 | if (GET_CODE (trial) != INSN | |
1105 | || GET_CODE (PATTERN (trial)) != SET) | |
1106 | return 0; | |
1107 | if (get_attr_length (trial) != 1) | |
1108 | return 0; | |
1109 | ||
c4ce6853 DE |
1110 | /* If %g0 is live, there are lots of things we can't handle. |
1111 | Rather than trying to find them all now, let's punt and only | |
1112 | optimize things as necessary. */ | |
1113 | if (TARGET_LIVE_G0) | |
1114 | return 0; | |
1115 | ||
915f619f JW |
1116 | /* In the case of a true leaf function, anything can go into the delay slot. |
1117 | A delay slot only exists however if the frame size is zero, otherwise | |
1118 | we will put an insn to adjust the stack after the return. */ | |
ab835497 RK |
1119 | if (leaf_function) |
1120 | { | |
1121 | if (leaf_return_peephole_ok ()) | |
7c56249d | 1122 | return (get_attr_in_uncond_branch_delay (trial) == IN_BRANCH_DELAY_TRUE); |
ab835497 RK |
1123 | return 0; |
1124 | } | |
3592ea0d DE |
1125 | /* If only trivial `restore' insns work, nothing can go in the |
1126 | delay slot. */ | |
1127 | else if (TARGET_BROKEN_SAVERESTORE) | |
1128 | return 0; | |
ab835497 | 1129 | |
1ee4af95 DE |
1130 | pat = PATTERN (trial); |
1131 | ||
ab835497 RK |
1132 | /* Otherwise, only operations which can be done in tandem with |
1133 | a `restore' insn can go into the delay slot. */ | |
ab835497 | 1134 | if (GET_CODE (SET_DEST (pat)) != REG |
915f619f JW |
1135 | || REGNO (SET_DEST (pat)) >= 32 |
1136 | || REGNO (SET_DEST (pat)) < 24) | |
ab835497 | 1137 | return 0; |
915f619f | 1138 | |
ab835497 RK |
1139 | src = SET_SRC (pat); |
1140 | if (arith_operand (src, GET_MODE (src))) | |
1141 | return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (SImode); | |
1142 | if (arith_double_operand (src, GET_MODE (src))) | |
1143 | return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode); | |
1144 | if (GET_CODE (src) == PLUS) | |
1145 | { | |
1146 | if (register_operand (XEXP (src, 0), SImode) | |
1147 | && arith_operand (XEXP (src, 1), SImode)) | |
1148 | return 1; | |
1149 | if (register_operand (XEXP (src, 1), SImode) | |
1150 | && arith_operand (XEXP (src, 0), SImode)) | |
1151 | return 1; | |
1152 | if (register_operand (XEXP (src, 0), DImode) | |
1153 | && arith_double_operand (XEXP (src, 1), DImode)) | |
1154 | return 1; | |
1155 | if (register_operand (XEXP (src, 1), DImode) | |
1156 | && arith_double_operand (XEXP (src, 0), DImode)) | |
1157 | return 1; | |
1158 | } | |
1159 | if (GET_CODE (src) == MINUS | |
1160 | && register_operand (XEXP (src, 0), SImode) | |
1161 | && small_int (XEXP (src, 1), VOIDmode)) | |
1162 | return 1; | |
1163 | if (GET_CODE (src) == MINUS | |
1164 | && register_operand (XEXP (src, 0), DImode) | |
1165 | && !register_operand (XEXP (src, 1), DImode) | |
1166 | && arith_double_operand (XEXP (src, 1), DImode)) | |
1167 | return 1; | |
1168 | return 0; | |
1169 | } | |
1170 | ||
1171 | int | |
1172 | short_branch (uid1, uid2) | |
1173 | int uid1, uid2; | |
1174 | { | |
1175 | unsigned int delta = insn_addresses[uid1] - insn_addresses[uid2]; | |
1176 | if (delta + 1024 < 2048) | |
1177 | return 1; | |
1178 | /* warning ("long branch, distance %d", delta); */ | |
1179 | return 0; | |
1180 | } | |
1181 | ||
1182 | /* Return non-zero if REG is not used after INSN. | |
1183 | We assume REG is a reload reg, and therefore does | |
1184 | not live past labels or calls or jumps. */ | |
1185 | int | |
1186 | reg_unused_after (reg, insn) | |
1187 | rtx reg; | |
1188 | rtx insn; | |
1189 | { | |
1190 | enum rtx_code code, prev_code = UNKNOWN; | |
1191 | ||
1192 | while (insn = NEXT_INSN (insn)) | |
1193 | { | |
1194 | if (prev_code == CALL_INSN && call_used_regs[REGNO (reg)]) | |
1195 | return 1; | |
1196 | ||
1197 | code = GET_CODE (insn); | |
1198 | if (GET_CODE (insn) == CODE_LABEL) | |
1199 | return 1; | |
1200 | ||
1201 | if (GET_RTX_CLASS (code) == 'i') | |
1202 | { | |
1203 | rtx set = single_set (insn); | |
1204 | int in_src = set && reg_overlap_mentioned_p (reg, SET_SRC (set)); | |
1205 | if (set && in_src) | |
1206 | return 0; | |
1207 | if (set && reg_overlap_mentioned_p (reg, SET_DEST (set))) | |
1208 | return 1; | |
1209 | if (set == 0 && reg_overlap_mentioned_p (reg, PATTERN (insn))) | |
1210 | return 0; | |
1211 | } | |
1212 | prev_code = code; | |
1213 | } | |
1214 | return 1; | |
1215 | } | |
1216 | \f | |
6a4bb1fa DE |
1217 | /* The rtx for the global offset table which is a special form |
1218 | that *is* a position independent symbolic constant. */ | |
1219 | static rtx pic_pc_rtx; | |
1220 | ||
1221 | /* Ensure that we are not using patterns that are not OK with PIC. */ | |
1222 | ||
1223 | int | |
1224 | check_pic (i) | |
1225 | int i; | |
1226 | { | |
1227 | switch (flag_pic) | |
1228 | { | |
1229 | case 1: | |
1230 | if (GET_CODE (recog_operand[i]) == SYMBOL_REF | |
1231 | || (GET_CODE (recog_operand[i]) == CONST | |
1232 | && ! rtx_equal_p (pic_pc_rtx, recog_operand[i]))) | |
1233 | abort (); | |
1234 | case 2: | |
1235 | default: | |
1236 | return 1; | |
1237 | } | |
1238 | } | |
1239 | ||
1240 | /* Return true if X is an address which needs a temporary register when | |
1241 | reloaded while generating PIC code. */ | |
1242 | ||
1243 | int | |
1244 | pic_address_needs_scratch (x) | |
1245 | rtx x; | |
1246 | { | |
1247 | /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */ | |
1248 | if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS | |
1249 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF | |
1250 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT | |
1251 | && ! SMALL_INT (XEXP (XEXP (x, 0), 1))) | |
1252 | return 1; | |
1253 | ||
1254 | return 0; | |
1255 | } | |
1256 | ||
ab835497 RK |
1257 | /* Legitimize PIC addresses. If the address is already position-independent, |
1258 | we return ORIG. Newly generated position-independent addresses go into a | |
1259 | reg. This is REG if non zero, otherwise we allocate register(s) as | |
7e2feebf | 1260 | necessary. */ |
ab835497 RK |
1261 | |
1262 | rtx | |
7e2feebf | 1263 | legitimize_pic_address (orig, mode, reg) |
ab835497 RK |
1264 | rtx orig; |
1265 | enum machine_mode mode; | |
7e2feebf | 1266 | rtx reg; |
ab835497 RK |
1267 | { |
1268 | if (GET_CODE (orig) == SYMBOL_REF) | |
1269 | { | |
1270 | rtx pic_ref, address; | |
1271 | rtx insn; | |
1272 | ||
1273 | if (reg == 0) | |
1274 | { | |
01c0e9dc | 1275 | if (reload_in_progress || reload_completed) |
ab835497 RK |
1276 | abort (); |
1277 | else | |
1278 | reg = gen_reg_rtx (Pmode); | |
1279 | } | |
1280 | ||
1281 | if (flag_pic == 2) | |
1282 | { | |
1283 | /* If not during reload, allocate another temp reg here for loading | |
1284 | in the address, so that these instructions can be optimized | |
1285 | properly. */ | |
01c0e9dc JW |
1286 | rtx temp_reg = ((reload_in_progress || reload_completed) |
1287 | ? reg : gen_reg_rtx (Pmode)); | |
ab835497 | 1288 | |
b4ac57ab RS |
1289 | /* Must put the SYMBOL_REF inside an UNSPEC here so that cse |
1290 | won't get confused into thinking that these two instructions | |
1291 | are loading in the true address of the symbol. If in the | |
1292 | future a PIC rtx exists, that should be used instead. */ | |
95726648 DE |
1293 | emit_insn (gen_pic_sethi_si (temp_reg, orig)); |
1294 | emit_insn (gen_pic_lo_sum_si (temp_reg, temp_reg, orig)); | |
1295 | ||
ab835497 RK |
1296 | address = temp_reg; |
1297 | } | |
1298 | else | |
1299 | address = orig; | |
1300 | ||
1301 | pic_ref = gen_rtx (MEM, Pmode, | |
1302 | gen_rtx (PLUS, Pmode, | |
1303 | pic_offset_table_rtx, address)); | |
1304 | current_function_uses_pic_offset_table = 1; | |
1305 | RTX_UNCHANGING_P (pic_ref) = 1; | |
1306 | insn = emit_move_insn (reg, pic_ref); | |
1307 | /* Put a REG_EQUAL note on this insn, so that it can be optimized | |
1308 | by loop. */ | |
1309 | REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_EQUAL, orig, | |
1310 | REG_NOTES (insn)); | |
1311 | return reg; | |
1312 | } | |
1313 | else if (GET_CODE (orig) == CONST) | |
1314 | { | |
1315 | rtx base, offset; | |
1316 | ||
1317 | if (GET_CODE (XEXP (orig, 0)) == PLUS | |
1318 | && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx) | |
1319 | return orig; | |
1320 | ||
1321 | if (reg == 0) | |
1322 | { | |
01c0e9dc | 1323 | if (reload_in_progress || reload_completed) |
ab835497 RK |
1324 | abort (); |
1325 | else | |
1326 | reg = gen_reg_rtx (Pmode); | |
1327 | } | |
1328 | ||
1329 | if (GET_CODE (XEXP (orig, 0)) == PLUS) | |
1330 | { | |
7e2feebf | 1331 | base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg); |
ab835497 | 1332 | offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode, |
7e2feebf | 1333 | base == reg ? 0 : reg); |
ab835497 RK |
1334 | } |
1335 | else | |
1336 | abort (); | |
1337 | ||
1338 | if (GET_CODE (offset) == CONST_INT) | |
1339 | { | |
1340 | if (SMALL_INT (offset)) | |
1341 | return plus_constant_for_output (base, INTVAL (offset)); | |
01c0e9dc | 1342 | else if (! reload_in_progress && ! reload_completed) |
ab835497 | 1343 | offset = force_reg (Pmode, offset); |
ab835497 | 1344 | else |
7e2feebf | 1345 | /* If we reach here, then something is seriously wrong. */ |
ab835497 RK |
1346 | abort (); |
1347 | } | |
1348 | return gen_rtx (PLUS, Pmode, base, offset); | |
1349 | } | |
1350 | else if (GET_CODE (orig) == LABEL_REF) | |
95726648 | 1351 | /* ??? Why do we do this? */ |
ab835497 RK |
1352 | current_function_uses_pic_offset_table = 1; |
1353 | ||
1354 | return orig; | |
1355 | } | |
1356 | ||
1357 | /* Set up PIC-specific rtl. This should not cause any insns | |
1358 | to be emitted. */ | |
1359 | ||
1360 | void | |
1361 | initialize_pic () | |
1362 | { | |
1363 | } | |
1364 | ||
1365 | /* Emit special PIC prologues and epilogues. */ | |
1366 | ||
1367 | void | |
1368 | finalize_pic () | |
1369 | { | |
1370 | /* The table we use to reference PIC data. */ | |
1371 | rtx global_offset_table; | |
1372 | /* Labels to get the PC in the prologue of this function. */ | |
1373 | rtx l1, l2; | |
1374 | rtx seq; | |
1375 | int orig_flag_pic = flag_pic; | |
1376 | ||
1377 | if (current_function_uses_pic_offset_table == 0) | |
1378 | return; | |
1379 | ||
1380 | if (! flag_pic) | |
1381 | abort (); | |
1382 | ||
1383 | flag_pic = 0; | |
95726648 DE |
1384 | |
1385 | /* ??? sparc64 pic currently under construction. */ | |
ab835497 RK |
1386 | |
1387 | start_sequence (); | |
1388 | ||
95726648 | 1389 | l1 = gen_label_rtx (); |
ab835497 RK |
1390 | |
1391 | /* Initialize every time through, since we can't easily | |
1392 | know this to be permanent. */ | |
c4eb2bd7 | 1393 | global_offset_table = gen_rtx (SYMBOL_REF, Pmode, "_GLOBAL_OFFSET_TABLE_"); |
ab835497 RK |
1394 | pic_pc_rtx = gen_rtx (CONST, Pmode, |
1395 | gen_rtx (MINUS, Pmode, | |
1396 | global_offset_table, | |
1397 | gen_rtx (CONST, Pmode, | |
1398 | gen_rtx (MINUS, Pmode, | |
1399 | gen_rtx (LABEL_REF, VOIDmode, l1), | |
1400 | pc_rtx)))); | |
1401 | ||
95726648 DE |
1402 | if (! TARGET_ARCH64) |
1403 | { | |
1404 | l2 = gen_label_rtx (); | |
1405 | emit_label (l1); | |
1406 | /* Note that we pun calls and jumps here! */ | |
1407 | emit_jump_insn (gen_get_pc_sp32 (l2)); | |
1408 | emit_label (l2); | |
1409 | ||
1410 | emit_insn (gen_rtx (SET, VOIDmode, pic_offset_table_rtx, | |
1411 | gen_rtx (HIGH, Pmode, pic_pc_rtx))); | |
1412 | ||
1413 | emit_insn (gen_rtx (SET, VOIDmode, | |
1414 | pic_offset_table_rtx, | |
1415 | gen_rtx (LO_SUM, Pmode, | |
1416 | pic_offset_table_rtx, pic_pc_rtx))); | |
1417 | emit_insn (gen_rtx (SET, VOIDmode, | |
1418 | pic_offset_table_rtx, | |
1419 | gen_rtx (PLUS, Pmode, | |
1420 | pic_offset_table_rtx, | |
1421 | gen_rtx (REG, Pmode, 15)))); | |
1422 | ||
1423 | /* emit_insn (gen_rtx (ASM_INPUT, VOIDmode, "!#PROLOGUE# 1")); */ | |
1424 | LABEL_PRESERVE_P (l1) = 1; | |
1425 | LABEL_PRESERVE_P (l2) = 1; | |
1426 | } | |
61a55e8b | 1427 | else |
95726648 DE |
1428 | { |
1429 | /* ??? This definately isn't right for -mfullany. */ | |
1430 | /* ??? And it doesn't quite seem right for the others either. */ | |
1431 | emit_label (l1); | |
1432 | emit_insn (gen_get_pc_sp64 (gen_rtx (REG, Pmode, 1))); | |
1433 | ||
1434 | /* Don't let the scheduler separate the previous insn from `l1'. */ | |
1435 | emit_insn (gen_blockage ()); | |
1436 | ||
1437 | emit_insn (gen_rtx (SET, VOIDmode, pic_offset_table_rtx, | |
1438 | gen_rtx (HIGH, Pmode, pic_pc_rtx))); | |
1439 | ||
1440 | emit_insn (gen_rtx (SET, VOIDmode, | |
1441 | pic_offset_table_rtx, | |
1442 | gen_rtx (LO_SUM, Pmode, | |
1443 | pic_offset_table_rtx, pic_pc_rtx))); | |
1444 | emit_insn (gen_rtx (SET, VOIDmode, | |
1445 | pic_offset_table_rtx, | |
1446 | gen_rtx (PLUS, Pmode, | |
1447 | pic_offset_table_rtx, gen_rtx (REG, Pmode, 1)))); | |
1448 | ||
1449 | /* emit_insn (gen_rtx (ASM_INPUT, VOIDmode, "!#PROLOGUE# 1")); */ | |
1450 | LABEL_PRESERVE_P (l1) = 1; | |
1451 | } | |
1452 | ||
ab835497 RK |
1453 | flag_pic = orig_flag_pic; |
1454 | ||
1455 | seq = gen_sequence (); | |
1456 | end_sequence (); | |
1457 | emit_insn_after (seq, get_insns ()); | |
1458 | ||
1459 | /* Need to emit this whether or not we obey regdecls, | |
1460 | since setjmp/longjmp can cause life info to screw up. */ | |
1461 | emit_insn (gen_rtx (USE, VOIDmode, pic_offset_table_rtx)); | |
1462 | } | |
1463 | \f | |
ab835497 RK |
1464 | /* Emit insns to move operands[1] into operands[0]. |
1465 | ||
1466 | Return 1 if we have written out everything that needs to be done to | |
1467 | do the move. Otherwise, return 0 and the caller will emit the move | |
7e2feebf | 1468 | normally. */ |
ab835497 RK |
1469 | |
1470 | int | |
7e2feebf | 1471 | emit_move_sequence (operands, mode) |
ab835497 RK |
1472 | rtx *operands; |
1473 | enum machine_mode mode; | |
ab835497 RK |
1474 | { |
1475 | register rtx operand0 = operands[0]; | |
1476 | register rtx operand1 = operands[1]; | |
1477 | ||
7e2feebf JW |
1478 | if (CONSTANT_P (operand1) && flag_pic |
1479 | && pic_address_needs_scratch (operand1)) | |
1480 | operands[1] = operand1 = legitimize_pic_address (operand1, mode, 0); | |
1481 | ||
ab835497 RK |
1482 | /* Handle most common case first: storing into a register. */ |
1483 | if (register_operand (operand0, mode)) | |
1484 | { | |
1485 | if (register_operand (operand1, mode) | |
1486 | || (GET_CODE (operand1) == CONST_INT && SMALL_INT (operand1)) | |
1487 | || (GET_CODE (operand1) == CONST_DOUBLE | |
1488 | && arith_double_operand (operand1, DImode)) | |
1489 | || (GET_CODE (operand1) == HIGH && GET_MODE (operand1) != DImode) | |
1490 | /* Only `general_operands' can come here, so MEM is ok. */ | |
1491 | || GET_CODE (operand1) == MEM) | |
1492 | { | |
1493 | /* Run this case quickly. */ | |
1494 | emit_insn (gen_rtx (SET, VOIDmode, operand0, operand1)); | |
1495 | return 1; | |
1496 | } | |
1497 | } | |
1498 | else if (GET_CODE (operand0) == MEM) | |
1499 | { | |
c4ce6853 DE |
1500 | if (register_operand (operand1, mode) |
1501 | || (operand1 == const0_rtx && ! TARGET_LIVE_G0)) | |
ab835497 RK |
1502 | { |
1503 | /* Run this case quickly. */ | |
1504 | emit_insn (gen_rtx (SET, VOIDmode, operand0, operand1)); | |
1505 | return 1; | |
1506 | } | |
1507 | if (! reload_in_progress) | |
1508 | { | |
1509 | operands[0] = validize_mem (operand0); | |
1510 | operands[1] = operand1 = force_reg (mode, operand1); | |
1511 | } | |
1512 | } | |
1513 | ||
95726648 DE |
1514 | if (GET_CODE (operand1) == LABEL_REF |
1515 | && mode == SImode && flag_pic) | |
1516 | { | |
1517 | if (TARGET_ARCH64) | |
1518 | abort (); | |
5ab7138b DE |
1519 | /* ??? This might suffer from the same problem the DImode case did: |
1520 | flags in operand1 not being propagated. */ | |
95726648 DE |
1521 | emit_insn (gen_move_pic_label_si (operand0, XEXP (operand1, 0))); |
1522 | return 1; | |
1523 | } | |
1524 | /* Non-pic LABEL_REF's in sparc64 are expensive to do the normal way, | |
1525 | so always use special code. */ | |
1526 | else if (GET_CODE (operand1) == LABEL_REF | |
1527 | && mode == DImode) | |
1528 | { | |
1529 | if (! TARGET_ARCH64) | |
1530 | abort (); | |
5ab7138b | 1531 | emit_insn (gen_move_label_di (operand0, operand1)); |
95726648 DE |
1532 | return 1; |
1533 | } | |
1534 | /* DImode HIGH values in sparc64 need a clobber added. */ | |
1535 | else if (TARGET_ARCH64 | |
1536 | && GET_CODE (operand1) == HIGH && GET_MODE (operand1) == DImode) | |
1537 | { | |
1538 | emit_insn (gen_sethi_di_sp64 (operand0, XEXP (operand1, 0))); | |
1539 | return 1; | |
1540 | } | |
1541 | /* Simplify the source if we need to. */ | |
1542 | else if (GET_CODE (operand1) != HIGH && immediate_operand (operand1, mode)) | |
ab835497 RK |
1543 | { |
1544 | if (flag_pic && symbolic_operand (operand1, mode)) | |
1545 | { | |
1546 | rtx temp_reg = reload_in_progress ? operand0 : 0; | |
1547 | ||
7e2feebf | 1548 | operands[1] = legitimize_pic_address (operand1, mode, temp_reg); |
ab835497 RK |
1549 | } |
1550 | else if (GET_CODE (operand1) == CONST_INT | |
1551 | ? (! SMALL_INT (operand1) | |
1552 | && (INTVAL (operand1) & 0x3ff) != 0) | |
1553 | : (GET_CODE (operand1) == CONST_DOUBLE | |
1554 | ? ! arith_double_operand (operand1, DImode) | |
1555 | : 1)) | |
1556 | { | |
1557 | /* For DImode values, temp must be operand0 because of the way | |
1558 | HI and LO_SUM work. The LO_SUM operator only copies half of | |
1559 | the LSW from the dest of the HI operator. If the LO_SUM dest is | |
1560 | not the same as the HI dest, then the MSW of the LO_SUM dest will | |
1561 | never be set. | |
1562 | ||
1563 | ??? The real problem here is that the ...(HI:DImode pattern emits | |
1564 | multiple instructions, and the ...(LO_SUM:DImode pattern emits | |
1565 | one instruction. This fails, because the compiler assumes that | |
1566 | LO_SUM copies all bits of the first operand to its dest. Better | |
1567 | would be to have the HI pattern emit one instruction and the | |
1568 | LO_SUM pattern multiple instructions. Even better would be | |
1569 | to use four rtl insns. */ | |
1570 | rtx temp = ((reload_in_progress || mode == DImode) | |
1571 | ? operand0 : gen_reg_rtx (mode)); | |
1572 | ||
a9e27770 | 1573 | if (TARGET_ARCH64 && mode == DImode) |
95726648 | 1574 | emit_insn (gen_sethi_di_sp64 (temp, operand1)); |
61a55e8b DE |
1575 | else |
1576 | emit_insn (gen_rtx (SET, VOIDmode, temp, | |
1577 | gen_rtx (HIGH, mode, operand1))); | |
1578 | ||
ab835497 RK |
1579 | operands[1] = gen_rtx (LO_SUM, mode, temp, operand1); |
1580 | } | |
1581 | } | |
1582 | ||
ab835497 RK |
1583 | /* Now have insn-emit do whatever it normally does. */ |
1584 | return 0; | |
1585 | } | |
1586 | \f | |
1587 | /* Return the best assembler insn template | |
1588 | for moving operands[1] into operands[0] as a fullword. */ | |
1589 | ||
1590 | char * | |
1591 | singlemove_string (operands) | |
1592 | rtx *operands; | |
1593 | { | |
1594 | if (GET_CODE (operands[0]) == MEM) | |
1595 | { | |
1596 | if (GET_CODE (operands[1]) != MEM) | |
1597 | return "st %r1,%0"; | |
1598 | else | |
1599 | abort (); | |
1600 | } | |
2b9a9aea | 1601 | else if (GET_CODE (operands[1]) == MEM) |
ab835497 | 1602 | return "ld %1,%0"; |
2b9a9aea JW |
1603 | else if (GET_CODE (operands[1]) == CONST_DOUBLE) |
1604 | { | |
c90fb4e6 JW |
1605 | REAL_VALUE_TYPE r; |
1606 | long i; | |
2b9a9aea JW |
1607 | |
1608 | /* Must be SFmode, otherwise this doesn't make sense. */ | |
1609 | if (GET_MODE (operands[1]) != SFmode) | |
1610 | abort (); | |
1611 | ||
c90fb4e6 JW |
1612 | REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]); |
1613 | REAL_VALUE_TO_TARGET_SINGLE (r, i); | |
2b9a9aea JW |
1614 | operands[1] = gen_rtx (CONST_INT, VOIDmode, i); |
1615 | ||
1616 | if (CONST_OK_FOR_LETTER_P (i, 'I')) | |
1617 | return "mov %1,%0"; | |
1618 | else if ((i & 0x000003FF) != 0) | |
1619 | return "sethi %%hi(%a1),%0\n\tor %0,%%lo(%a1),%0"; | |
1620 | else | |
1621 | return "sethi %%hi(%a1),%0"; | |
1622 | } | |
1623 | else if (GET_CODE (operands[1]) == CONST_INT | |
1624 | && ! CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'I')) | |
ab835497 RK |
1625 | { |
1626 | int i = INTVAL (operands[1]); | |
1627 | ||
915f619f | 1628 | /* If all low order 10 bits are clear, then we only need a single |
ab835497 | 1629 | sethi insn to load the constant. */ |
915f619f | 1630 | if ((i & 0x000003FF) != 0) |
ab835497 RK |
1631 | return "sethi %%hi(%a1),%0\n\tor %0,%%lo(%a1),%0"; |
1632 | else | |
1633 | return "sethi %%hi(%a1),%0"; | |
1634 | } | |
2b9a9aea | 1635 | /* Operand 1 must be a register, or a 'I' type CONST_INT. */ |
ab835497 RK |
1636 | return "mov %1,%0"; |
1637 | } | |
1638 | \f | |
795068a4 JW |
1639 | /* Return non-zero if it is OK to assume that the given memory operand is |
1640 | aligned at least to a 8-byte boundary. This should only be called | |
1641 | for memory accesses whose size is 8 bytes or larger. */ | |
1642 | ||
7c56249d | 1643 | int |
795068a4 JW |
1644 | mem_aligned_8 (mem) |
1645 | register rtx mem; | |
1646 | { | |
1647 | register rtx addr; | |
1648 | register rtx base; | |
1649 | register rtx offset; | |
1650 | ||
1651 | if (GET_CODE (mem) != MEM) | |
7c56249d | 1652 | return 0; /* It's gotta be a MEM! */ |
795068a4 JW |
1653 | |
1654 | addr = XEXP (mem, 0); | |
1655 | ||
795068a4 | 1656 | /* Now that all misaligned double parms are copied on function entry, |
1934ceca JW |
1657 | we can assume any 64-bit object is 64-bit aligned except those which |
1658 | are at unaligned offsets from the stack or frame pointer. If the | |
1659 | TARGET_UNALIGNED_DOUBLES switch is given, we do not make this | |
1660 | assumption. */ | |
795068a4 JW |
1661 | |
1662 | /* See what register we use in the address. */ | |
1663 | base = 0; | |
1664 | if (GET_CODE (addr) == PLUS) | |
1665 | { | |
1666 | if (GET_CODE (XEXP (addr, 0)) == REG | |
1667 | && GET_CODE (XEXP (addr, 1)) == CONST_INT) | |
1668 | { | |
1669 | base = XEXP (addr, 0); | |
1670 | offset = XEXP (addr, 1); | |
1671 | } | |
1672 | } | |
1673 | else if (GET_CODE (addr) == REG) | |
1674 | { | |
1675 | base = addr; | |
1676 | offset = const0_rtx; | |
1677 | } | |
1678 | ||
1679 | /* If it's the stack or frame pointer, check offset alignment. | |
2296cba3 | 1680 | We can have improper alignment in the function entry code. */ |
795068a4 JW |
1681 | if (base |
1682 | && (REGNO (base) == FRAME_POINTER_REGNUM | |
1683 | || REGNO (base) == STACK_POINTER_REGNUM)) | |
1684 | { | |
61a55e8b | 1685 | if (((INTVAL (offset) - SPARC_STACK_BIAS) & 0x7) == 0) |
795068a4 JW |
1686 | return 1; |
1687 | } | |
1934ceca JW |
1688 | /* Anything else we know is properly aligned unless TARGET_UNALIGNED_DOUBLES |
1689 | is true, in which case we can only assume that an access is aligned if | |
f5da225e JW |
1690 | it is to a constant address, or the address involves a LO_SUM. |
1691 | ||
1692 | We used to assume an address was aligned if MEM_IN_STRUCT_P was true. | |
1693 | That assumption was deleted so that gcc generated code can be used with | |
1694 | memory allocators that only guarantee 4 byte alignment. */ | |
1695 | else if (! TARGET_UNALIGNED_DOUBLES || CONSTANT_P (addr) | |
1696 | || GET_CODE (addr) == LO_SUM) | |
795068a4 | 1697 | return 1; |
795068a4 JW |
1698 | |
1699 | /* An obviously unaligned address. */ | |
1700 | return 0; | |
1701 | } | |
1702 | ||
1703 | enum optype { REGOP, OFFSOP, MEMOP, PUSHOP, POPOP, CNSTOP, RNDOP }; | |
1704 | ||
ab835497 | 1705 | /* Output assembler code to perform a doubleword move insn |
795068a4 JW |
1706 | with operands OPERANDS. This is very similar to the following |
1707 | output_move_quad function. */ | |
ab835497 RK |
1708 | |
1709 | char * | |
1710 | output_move_double (operands) | |
1711 | rtx *operands; | |
1712 | { | |
795068a4 JW |
1713 | register rtx op0 = operands[0]; |
1714 | register rtx op1 = operands[1]; | |
1715 | register enum optype optype0; | |
1716 | register enum optype optype1; | |
ab835497 | 1717 | rtx latehalf[2]; |
795068a4 JW |
1718 | rtx addreg0 = 0; |
1719 | rtx addreg1 = 0; | |
3b76513a | 1720 | int highest_first = 0; |
f3a9d1e6 | 1721 | int no_addreg1_decrement = 0; |
ab835497 RK |
1722 | |
1723 | /* First classify both operands. */ | |
1724 | ||
795068a4 | 1725 | if (REG_P (op0)) |
ab835497 | 1726 | optype0 = REGOP; |
795068a4 | 1727 | else if (offsettable_memref_p (op0)) |
ab835497 | 1728 | optype0 = OFFSOP; |
795068a4 | 1729 | else if (GET_CODE (op0) == MEM) |
ab835497 RK |
1730 | optype0 = MEMOP; |
1731 | else | |
1732 | optype0 = RNDOP; | |
1733 | ||
795068a4 | 1734 | if (REG_P (op1)) |
ab835497 | 1735 | optype1 = REGOP; |
795068a4 | 1736 | else if (CONSTANT_P (op1)) |
ab835497 | 1737 | optype1 = CNSTOP; |
795068a4 | 1738 | else if (offsettable_memref_p (op1)) |
ab835497 | 1739 | optype1 = OFFSOP; |
795068a4 | 1740 | else if (GET_CODE (op1) == MEM) |
ab835497 RK |
1741 | optype1 = MEMOP; |
1742 | else | |
1743 | optype1 = RNDOP; | |
1744 | ||
1745 | /* Check for the cases that the operand constraints are not | |
1746 | supposed to allow to happen. Abort if we get one, | |
1747 | because generating code for these cases is painful. */ | |
1748 | ||
795068a4 JW |
1749 | if (optype0 == RNDOP || optype1 == RNDOP |
1750 | || (optype0 == MEM && optype1 == MEM)) | |
ab835497 RK |
1751 | abort (); |
1752 | ||
1753 | /* If an operand is an unoffsettable memory ref, find a register | |
1754 | we can increment temporarily to make it refer to the second word. */ | |
1755 | ||
1756 | if (optype0 == MEMOP) | |
795068a4 | 1757 | addreg0 = find_addr_reg (XEXP (op0, 0)); |
ab835497 RK |
1758 | |
1759 | if (optype1 == MEMOP) | |
795068a4 | 1760 | addreg1 = find_addr_reg (XEXP (op1, 0)); |
ab835497 RK |
1761 | |
1762 | /* Ok, we can do one word at a time. | |
795068a4 | 1763 | Set up in LATEHALF the operands to use for the |
ab835497 RK |
1764 | high-numbered (least significant) word and in some cases alter the |
1765 | operands in OPERANDS to be suitable for the low-numbered word. */ | |
1766 | ||
1767 | if (optype0 == REGOP) | |
795068a4 | 1768 | latehalf[0] = gen_rtx (REG, SImode, REGNO (op0) + 1); |
ab835497 | 1769 | else if (optype0 == OFFSOP) |
795068a4 | 1770 | latehalf[0] = adj_offsettable_operand (op0, 4); |
ab835497 | 1771 | else |
795068a4 | 1772 | latehalf[0] = op0; |
ab835497 RK |
1773 | |
1774 | if (optype1 == REGOP) | |
795068a4 | 1775 | latehalf[1] = gen_rtx (REG, SImode, REGNO (op1) + 1); |
ab835497 | 1776 | else if (optype1 == OFFSOP) |
795068a4 | 1777 | latehalf[1] = adj_offsettable_operand (op1, 4); |
ab835497 | 1778 | else if (optype1 == CNSTOP) |
61a55e8b | 1779 | { |
a9e27770 | 1780 | if (TARGET_ARCH64) |
61a55e8b DE |
1781 | { |
1782 | if (arith_double_operand (op1, DImode)) | |
1783 | { | |
1784 | operands[1] = gen_rtx (CONST_INT, VOIDmode, | |
1785 | CONST_DOUBLE_LOW (op1)); | |
1786 | return "mov %1,%0"; | |
1787 | } | |
1788 | else | |
1789 | { | |
1790 | /* The only way to handle CONST_DOUBLEs or other 64 bit | |
1791 | constants here is to use a temporary, such as is done | |
1792 | for the V9 DImode sethi insn pattern. This is not | |
1793 | a practical solution, so abort if we reach here. | |
1794 | The md file should always force such constants to | |
1795 | memory. */ | |
1796 | abort (); | |
1797 | } | |
1798 | } | |
1799 | else | |
1800 | split_double (op1, &operands[1], &latehalf[1]); | |
1801 | } | |
ab835497 | 1802 | else |
795068a4 | 1803 | latehalf[1] = op1; |
ab835497 | 1804 | |
795068a4 JW |
1805 | /* Easy case: try moving both words at once. Check for moving between |
1806 | an even/odd register pair and a memory location. */ | |
ab835497 | 1807 | if ((optype0 == REGOP && optype1 != REGOP && optype1 != CNSTOP |
a9e27770 | 1808 | && (TARGET_ARCH64 || (REGNO (op0) & 1) == 0)) |
ab835497 | 1809 | || (optype0 != REGOP && optype0 != CNSTOP && optype1 == REGOP |
a9e27770 | 1810 | && (TARGET_ARCH64 || (REGNO (op1) & 1) == 0))) |
ab835497 | 1811 | { |
61a55e8b | 1812 | register rtx mem,reg; |
bc961ed7 RS |
1813 | |
1814 | if (optype0 == REGOP) | |
61a55e8b | 1815 | mem = op1, reg = op0; |
bc961ed7 | 1816 | else |
61a55e8b DE |
1817 | mem = op0, reg = op1; |
1818 | ||
1819 | /* In v9, ldd can be used for word aligned addresses, so technically | |
1820 | some of this logic is unneeded. We still avoid ldd if the address | |
1821 | is obviously unaligned though. */ | |
1822 | ||
1823 | if (mem_aligned_8 (mem) | |
1824 | /* If this is a floating point register higher than %f31, | |
1825 | then we *must* use an aligned load, since `ld' will not accept | |
1826 | the register number. */ | |
1827 | || (TARGET_V9 && REGNO (reg) >= 64)) | |
1828 | { | |
a9e27770 | 1829 | if (FP_REG_P (reg) || ! TARGET_ARCH64) |
61a55e8b DE |
1830 | return (mem == op1 ? "ldd %1,%0" : "std %1,%0"); |
1831 | else | |
1832 | return (mem == op1 ? "ldx %1,%0" : "stx %1,%0"); | |
1833 | } | |
1834 | } | |
bc961ed7 | 1835 | |
a9e27770 | 1836 | if (TARGET_ARCH64) |
61a55e8b DE |
1837 | { |
1838 | if (optype0 == REGOP && optype1 == REGOP) | |
1839 | { | |
1840 | if (FP_REG_P (op0)) | |
1841 | return "fmovd %1,%0"; | |
1842 | else | |
1843 | return "mov %1,%0"; | |
1844 | } | |
ab835497 RK |
1845 | } |
1846 | ||
795068a4 JW |
1847 | /* If the first move would clobber the source of the second one, |
1848 | do them in the other order. */ | |
1849 | ||
1850 | /* Overlapping registers. */ | |
ab835497 | 1851 | if (optype0 == REGOP && optype1 == REGOP |
795068a4 | 1852 | && REGNO (op0) == REGNO (latehalf[1])) |
ab835497 | 1853 | { |
ab835497 RK |
1854 | /* Do that word. */ |
1855 | output_asm_insn (singlemove_string (latehalf), latehalf); | |
ab835497 RK |
1856 | /* Do low-numbered word. */ |
1857 | return singlemove_string (operands); | |
1858 | } | |
795068a4 | 1859 | /* Loading into a register which overlaps a register used in the address. */ |
ab835497 | 1860 | else if (optype0 == REGOP && optype1 != REGOP |
795068a4 | 1861 | && reg_overlap_mentioned_p (op0, op1)) |
ab835497 | 1862 | { |
f3a9d1e6 JW |
1863 | /* If both halves of dest are used in the src memory address, |
1864 | add the two regs and put them in the low reg (op0). | |
1865 | Then it works to load latehalf first. */ | |
bdec790c RS |
1866 | if (reg_mentioned_p (op0, XEXP (op1, 0)) |
1867 | && reg_mentioned_p (latehalf[0], XEXP (op1, 0))) | |
1868 | { | |
bdec790c RS |
1869 | rtx xops[2]; |
1870 | xops[0] = latehalf[0]; | |
1871 | xops[1] = op0; | |
1872 | output_asm_insn ("add %1,%0,%1", xops); | |
3b76513a | 1873 | operands[1] = gen_rtx (MEM, DImode, op0); |
bdec790c | 1874 | latehalf[1] = adj_offsettable_operand (operands[1], 4); |
3b76513a | 1875 | addreg1 = 0; |
f3a9d1e6 | 1876 | highest_first = 1; |
bdec790c | 1877 | } |
f3a9d1e6 JW |
1878 | /* Only one register in the dest is used in the src memory address, |
1879 | and this is the first register of the dest, so we want to do | |
1880 | the late half first here also. */ | |
1881 | else if (! reg_mentioned_p (latehalf[0], XEXP (op1, 0))) | |
1882 | highest_first = 1; | |
1883 | /* Only one register in the dest is used in the src memory address, | |
1884 | and this is the second register of the dest, so we want to do | |
1885 | the late half last. If addreg1 is set, and addreg1 is the same | |
1886 | register as latehalf, then we must suppress the trailing decrement, | |
1887 | because it would clobber the value just loaded. */ | |
1888 | else if (addreg1 && reg_mentioned_p (addreg1, latehalf[0])) | |
1889 | no_addreg1_decrement = 1; | |
ab835497 RK |
1890 | } |
1891 | ||
3b76513a RS |
1892 | /* Normal case: do the two words, low-numbered first. |
1893 | Overlap case (highest_first set): do high-numbered word first. */ | |
ab835497 | 1894 | |
3b76513a RS |
1895 | if (! highest_first) |
1896 | output_asm_insn (singlemove_string (operands), operands); | |
ab835497 RK |
1897 | |
1898 | /* Make any unoffsettable addresses point at high-numbered word. */ | |
1899 | if (addreg0) | |
1900 | output_asm_insn ("add %0,0x4,%0", &addreg0); | |
1901 | if (addreg1) | |
1902 | output_asm_insn ("add %0,0x4,%0", &addreg1); | |
1903 | ||
1904 | /* Do that word. */ | |
1905 | output_asm_insn (singlemove_string (latehalf), latehalf); | |
1906 | ||
1907 | /* Undo the adds we just did. */ | |
1908 | if (addreg0) | |
1909 | output_asm_insn ("add %0,-0x4,%0", &addreg0); | |
f3a9d1e6 | 1910 | if (addreg1 && ! no_addreg1_decrement) |
ab835497 RK |
1911 | output_asm_insn ("add %0,-0x4,%0", &addreg1); |
1912 | ||
3b76513a RS |
1913 | if (highest_first) |
1914 | output_asm_insn (singlemove_string (operands), operands); | |
1915 | ||
ab835497 RK |
1916 | return ""; |
1917 | } | |
795068a4 JW |
1918 | |
1919 | /* Output assembler code to perform a quadword move insn | |
2296cba3 | 1920 | with operands OPERANDS. This is very similar to the preceding |
795068a4 JW |
1921 | output_move_double function. */ |
1922 | ||
1923 | char * | |
1924 | output_move_quad (operands) | |
1925 | rtx *operands; | |
1926 | { | |
1927 | register rtx op0 = operands[0]; | |
1928 | register rtx op1 = operands[1]; | |
1929 | register enum optype optype0; | |
1930 | register enum optype optype1; | |
1931 | rtx wordpart[4][2]; | |
1932 | rtx addreg0 = 0; | |
1933 | rtx addreg1 = 0; | |
1934 | ||
1935 | /* First classify both operands. */ | |
1936 | ||
1937 | if (REG_P (op0)) | |
1938 | optype0 = REGOP; | |
1939 | else if (offsettable_memref_p (op0)) | |
1940 | optype0 = OFFSOP; | |
1941 | else if (GET_CODE (op0) == MEM) | |
1942 | optype0 = MEMOP; | |
1943 | else | |
1944 | optype0 = RNDOP; | |
1945 | ||
1946 | if (REG_P (op1)) | |
1947 | optype1 = REGOP; | |
1948 | else if (CONSTANT_P (op1)) | |
1949 | optype1 = CNSTOP; | |
1950 | else if (offsettable_memref_p (op1)) | |
1951 | optype1 = OFFSOP; | |
1952 | else if (GET_CODE (op1) == MEM) | |
1953 | optype1 = MEMOP; | |
1954 | else | |
1955 | optype1 = RNDOP; | |
1956 | ||
1957 | /* Check for the cases that the operand constraints are not | |
1958 | supposed to allow to happen. Abort if we get one, | |
1959 | because generating code for these cases is painful. */ | |
1960 | ||
1961 | if (optype0 == RNDOP || optype1 == RNDOP | |
1962 | || (optype0 == MEM && optype1 == MEM)) | |
1963 | abort (); | |
1964 | ||
1965 | /* If an operand is an unoffsettable memory ref, find a register | |
1966 | we can increment temporarily to make it refer to the later words. */ | |
1967 | ||
1968 | if (optype0 == MEMOP) | |
1969 | addreg0 = find_addr_reg (XEXP (op0, 0)); | |
1970 | ||
1971 | if (optype1 == MEMOP) | |
1972 | addreg1 = find_addr_reg (XEXP (op1, 0)); | |
1973 | ||
1974 | /* Ok, we can do one word at a time. | |
1975 | Set up in wordpart the operands to use for each word of the arguments. */ | |
1976 | ||
1977 | if (optype0 == REGOP) | |
1978 | { | |
1979 | wordpart[0][0] = gen_rtx (REG, SImode, REGNO (op0) + 0); | |
1980 | wordpart[1][0] = gen_rtx (REG, SImode, REGNO (op0) + 1); | |
1981 | wordpart[2][0] = gen_rtx (REG, SImode, REGNO (op0) + 2); | |
1982 | wordpart[3][0] = gen_rtx (REG, SImode, REGNO (op0) + 3); | |
1983 | } | |
1984 | else if (optype0 == OFFSOP) | |
1985 | { | |
1986 | wordpart[0][0] = adj_offsettable_operand (op0, 0); | |
1987 | wordpart[1][0] = adj_offsettable_operand (op0, 4); | |
1988 | wordpart[2][0] = adj_offsettable_operand (op0, 8); | |
1989 | wordpart[3][0] = adj_offsettable_operand (op0, 12); | |
1990 | } | |
1991 | else | |
1992 | { | |
1993 | wordpart[0][0] = op0; | |
1994 | wordpart[1][0] = op0; | |
1995 | wordpart[2][0] = op0; | |
1996 | wordpart[3][0] = op0; | |
1997 | } | |
1998 | ||
1999 | if (optype1 == REGOP) | |
2000 | { | |
2001 | wordpart[0][1] = gen_rtx (REG, SImode, REGNO (op1) + 0); | |
2002 | wordpart[1][1] = gen_rtx (REG, SImode, REGNO (op1) + 1); | |
2003 | wordpart[2][1] = gen_rtx (REG, SImode, REGNO (op1) + 2); | |
2004 | wordpart[3][1] = gen_rtx (REG, SImode, REGNO (op1) + 3); | |
2005 | } | |
2006 | else if (optype1 == OFFSOP) | |
2007 | { | |
2008 | wordpart[0][1] = adj_offsettable_operand (op1, 0); | |
2009 | wordpart[1][1] = adj_offsettable_operand (op1, 4); | |
2010 | wordpart[2][1] = adj_offsettable_operand (op1, 8); | |
2011 | wordpart[3][1] = adj_offsettable_operand (op1, 12); | |
2012 | } | |
2013 | else if (optype1 == CNSTOP) | |
2014 | { | |
61a66555 JW |
2015 | REAL_VALUE_TYPE r; |
2016 | long l[4]; | |
2017 | ||
2018 | /* This only works for TFmode floating point constants. */ | |
2019 | if (GET_CODE (op1) != CONST_DOUBLE || GET_MODE (op1) != TFmode) | |
2020 | abort (); | |
2021 | ||
2022 | REAL_VALUE_FROM_CONST_DOUBLE (r, op1); | |
2023 | REAL_VALUE_TO_TARGET_LONG_DOUBLE (r, l); | |
2024 | ||
2025 | wordpart[0][1] = GEN_INT (l[0]); | |
2026 | wordpart[1][1] = GEN_INT (l[1]); | |
2027 | wordpart[2][1] = GEN_INT (l[2]); | |
2028 | wordpart[3][1] = GEN_INT (l[3]); | |
795068a4 JW |
2029 | } |
2030 | else | |
2031 | { | |
2032 | wordpart[0][1] = op1; | |
2033 | wordpart[1][1] = op1; | |
2034 | wordpart[2][1] = op1; | |
2035 | wordpart[3][1] = op1; | |
2036 | } | |
2037 | ||
2038 | /* Easy case: try moving the quad as two pairs. Check for moving between | |
61a55e8b DE |
2039 | an even/odd register pair and a memory location. |
2040 | Also handle new v9 fp regs here. */ | |
795068a4 JW |
2041 | /* ??? Should also handle the case of non-offsettable addresses here. |
2042 | We can at least do the first pair as a ldd/std, and then do the third | |
2043 | and fourth words individually. */ | |
2044 | if ((optype0 == REGOP && optype1 == OFFSOP && (REGNO (op0) & 1) == 0) | |
2045 | || (optype0 == OFFSOP && optype1 == REGOP && (REGNO (op1) & 1) == 0)) | |
2046 | { | |
61a55e8b | 2047 | rtx mem, reg; |
795068a4 JW |
2048 | |
2049 | if (optype0 == REGOP) | |
61a55e8b | 2050 | mem = op1, reg = op0; |
795068a4 | 2051 | else |
61a55e8b | 2052 | mem = op0, reg = op1; |
795068a4 | 2053 | |
61a55e8b DE |
2054 | if (mem_aligned_8 (mem) |
2055 | /* If this is a floating point register higher than %f31, | |
2056 | then we *must* use an aligned load, since `ld' will not accept | |
2057 | the register number. */ | |
2058 | || (TARGET_V9 && REGNO (reg) >= 64)) | |
795068a4 | 2059 | { |
eb582c5d | 2060 | if (TARGET_V9 && FP_REG_P (reg) && TARGET_HARD_QUAD) |
61a55e8b DE |
2061 | { |
2062 | if ((REGNO (reg) & 3) != 0) | |
2063 | abort (); | |
2064 | return (mem == op1 ? "ldq %1,%0" : "stq %1,%0"); | |
2065 | } | |
795068a4 | 2066 | operands[2] = adj_offsettable_operand (mem, 8); |
eb582c5d | 2067 | /* ??? In arch64 case, shouldn't we use ldd/std for fp regs. */ |
795068a4 | 2068 | if (mem == op1) |
a9e27770 | 2069 | return TARGET_ARCH64 ? "ldx %1,%0;ldx %2,%R0" : "ldd %1,%0;ldd %2,%S0"; |
795068a4 | 2070 | else |
a9e27770 | 2071 | return TARGET_ARCH64 ? "stx %1,%0;stx %R1,%2" : "std %1,%0;std %S1,%2"; |
795068a4 JW |
2072 | } |
2073 | } | |
2074 | ||
2075 | /* If the first move would clobber the source of the second one, | |
2076 | do them in the other order. */ | |
2077 | ||
2078 | /* Overlapping registers. */ | |
2079 | if (optype0 == REGOP && optype1 == REGOP | |
2080 | && (REGNO (op0) == REGNO (wordpart[1][3]) | |
2081 | || REGNO (op0) == REGNO (wordpart[1][2]) | |
2082 | || REGNO (op0) == REGNO (wordpart[1][1]))) | |
2083 | { | |
2084 | /* Do fourth word. */ | |
2085 | output_asm_insn (singlemove_string (wordpart[3]), wordpart[3]); | |
2086 | /* Do the third word. */ | |
2087 | output_asm_insn (singlemove_string (wordpart[2]), wordpart[2]); | |
2088 | /* Do the second word. */ | |
2089 | output_asm_insn (singlemove_string (wordpart[1]), wordpart[1]); | |
2090 | /* Do lowest-numbered word. */ | |
2091 | return singlemove_string (wordpart[0]); | |
2092 | } | |
2093 | /* Loading into a register which overlaps a register used in the address. */ | |
2094 | if (optype0 == REGOP && optype1 != REGOP | |
2095 | && reg_overlap_mentioned_p (op0, op1)) | |
2096 | { | |
2097 | /* ??? Not implemented yet. This is a bit complicated, because we | |
2098 | must load which ever part overlaps the address last. If the address | |
2099 | is a double-reg address, then there are two parts which need to | |
2100 | be done last, which is impossible. We would need a scratch register | |
2101 | in that case. */ | |
2102 | abort (); | |
2103 | } | |
2104 | ||
ddd5a7c1 | 2105 | /* Normal case: move the four words in lowest to highest address order. */ |
795068a4 JW |
2106 | |
2107 | output_asm_insn (singlemove_string (wordpart[0]), wordpart[0]); | |
2108 | ||
2109 | /* Make any unoffsettable addresses point at the second word. */ | |
2110 | if (addreg0) | |
2111 | output_asm_insn ("add %0,0x4,%0", &addreg0); | |
2112 | if (addreg1) | |
2113 | output_asm_insn ("add %0,0x4,%0", &addreg1); | |
2114 | ||
2115 | /* Do the second word. */ | |
2116 | output_asm_insn (singlemove_string (wordpart[1]), wordpart[1]); | |
2117 | ||
2118 | /* Make any unoffsettable addresses point at the third word. */ | |
2119 | if (addreg0) | |
2120 | output_asm_insn ("add %0,0x4,%0", &addreg0); | |
2121 | if (addreg1) | |
2122 | output_asm_insn ("add %0,0x4,%0", &addreg1); | |
2123 | ||
2124 | /* Do the third word. */ | |
2125 | output_asm_insn (singlemove_string (wordpart[2]), wordpart[2]); | |
2126 | ||
2127 | /* Make any unoffsettable addresses point at the fourth word. */ | |
2128 | if (addreg0) | |
2129 | output_asm_insn ("add %0,0x4,%0", &addreg0); | |
2130 | if (addreg1) | |
2131 | output_asm_insn ("add %0,0x4,%0", &addreg1); | |
2132 | ||
2133 | /* Do the fourth word. */ | |
2134 | output_asm_insn (singlemove_string (wordpart[3]), wordpart[3]); | |
2135 | ||
2136 | /* Undo the adds we just did. */ | |
2137 | if (addreg0) | |
2138 | output_asm_insn ("add %0,-0xc,%0", &addreg0); | |
2139 | if (addreg1) | |
2140 | output_asm_insn ("add %0,-0xc,%0", &addreg1); | |
2141 | ||
2142 | return ""; | |
2143 | } | |
ab835497 | 2144 | \f |
795068a4 | 2145 | /* Output assembler code to perform a doubleword move insn with operands |
a3ee5899 JW |
2146 | OPERANDS, one of which must be a floating point register. */ |
2147 | ||
ab835497 RK |
2148 | char * |
2149 | output_fp_move_double (operands) | |
2150 | rtx *operands; | |
2151 | { | |
ab835497 RK |
2152 | if (FP_REG_P (operands[0])) |
2153 | { | |
2154 | if (FP_REG_P (operands[1])) | |
61a55e8b DE |
2155 | { |
2156 | if (TARGET_V9) | |
2157 | return "fmovd %1,%0"; | |
2158 | else | |
2159 | return "fmovs %1,%0\n\tfmovs %R1,%R0"; | |
2160 | } | |
a3ee5899 | 2161 | else if (GET_CODE (operands[1]) == REG) |
019c2b24 | 2162 | abort (); |
a3ee5899 JW |
2163 | else |
2164 | return output_move_double (operands); | |
ab835497 RK |
2165 | } |
2166 | else if (FP_REG_P (operands[1])) | |
2167 | { | |
2168 | if (GET_CODE (operands[0]) == REG) | |
019c2b24 | 2169 | abort (); |
a3ee5899 JW |
2170 | else |
2171 | return output_move_double (operands); | |
ab835497 RK |
2172 | } |
2173 | else abort (); | |
2174 | } | |
795068a4 JW |
2175 | |
2176 | /* Output assembler code to perform a quadword move insn with operands | |
2177 | OPERANDS, one of which must be a floating point register. */ | |
2178 | ||
2179 | char * | |
2180 | output_fp_move_quad (operands) | |
2181 | rtx *operands; | |
2182 | { | |
2183 | register rtx op0 = operands[0]; | |
2184 | register rtx op1 = operands[1]; | |
795068a4 JW |
2185 | |
2186 | if (FP_REG_P (op0)) | |
2187 | { | |
2188 | if (FP_REG_P (op1)) | |
61a55e8b DE |
2189 | { |
2190 | if (TARGET_V9) | |
2191 | return "fmovq %1,%0"; | |
2192 | else | |
2193 | return "fmovs %1,%0\n\tfmovs %R1,%R0\n\tfmovs %S1,%S0\n\tfmovs %T1,%T0"; | |
2194 | } | |
019c2b24 JW |
2195 | else if (GET_CODE (op1) == REG) |
2196 | abort (); | |
795068a4 JW |
2197 | else |
2198 | return output_move_quad (operands); | |
2199 | } | |
2200 | else if (FP_REG_P (op1)) | |
2201 | { | |
2202 | if (GET_CODE (op0) == REG) | |
019c2b24 | 2203 | abort (); |
795068a4 JW |
2204 | else |
2205 | return output_move_quad (operands); | |
2206 | } | |
2207 | else | |
2208 | abort (); | |
2209 | } | |
ab835497 RK |
2210 | \f |
2211 | /* Return a REG that occurs in ADDR with coefficient 1. | |
2212 | ADDR can be effectively incremented by incrementing REG. */ | |
2213 | ||
2214 | static rtx | |
2215 | find_addr_reg (addr) | |
2216 | rtx addr; | |
2217 | { | |
2218 | while (GET_CODE (addr) == PLUS) | |
2219 | { | |
2220 | /* We absolutely can not fudge the frame pointer here, because the | |
2221 | frame pointer must always be 8 byte aligned. It also confuses | |
2222 | debuggers. */ | |
2223 | if (GET_CODE (XEXP (addr, 0)) == REG | |
2224 | && REGNO (XEXP (addr, 0)) != FRAME_POINTER_REGNUM) | |
2225 | addr = XEXP (addr, 0); | |
2226 | else if (GET_CODE (XEXP (addr, 1)) == REG | |
2227 | && REGNO (XEXP (addr, 1)) != FRAME_POINTER_REGNUM) | |
2228 | addr = XEXP (addr, 1); | |
2229 | else if (CONSTANT_P (XEXP (addr, 0))) | |
2230 | addr = XEXP (addr, 1); | |
2231 | else if (CONSTANT_P (XEXP (addr, 1))) | |
2232 | addr = XEXP (addr, 0); | |
2233 | else | |
2234 | abort (); | |
2235 | } | |
2236 | if (GET_CODE (addr) == REG) | |
2237 | return addr; | |
2238 | abort (); | |
2239 | } | |
2240 | ||
6a4bb1fa DE |
2241 | #if 0 /* not currently used */ |
2242 | ||
ab835497 RK |
2243 | void |
2244 | output_sized_memop (opname, mode, signedp) | |
2245 | char *opname; | |
2246 | enum machine_mode mode; | |
2247 | int signedp; | |
2248 | { | |
2249 | static char *ld_size_suffix_u[] = { "ub", "uh", "", "?", "d" }; | |
2250 | static char *ld_size_suffix_s[] = { "sb", "sh", "", "?", "d" }; | |
2251 | static char *st_size_suffix[] = { "b", "h", "", "?", "d" }; | |
2252 | char **opnametab, *modename; | |
2253 | ||
2254 | if (opname[0] == 'l') | |
2255 | if (signedp) | |
2256 | opnametab = ld_size_suffix_s; | |
2257 | else | |
2258 | opnametab = ld_size_suffix_u; | |
2259 | else | |
2260 | opnametab = st_size_suffix; | |
2261 | modename = opnametab[GET_MODE_SIZE (mode) >> 1]; | |
2262 | ||
2263 | fprintf (asm_out_file, "\t%s%s", opname, modename); | |
2264 | } | |
2265 | \f | |
2266 | void | |
2267 | output_move_with_extension (operands) | |
2268 | rtx *operands; | |
2269 | { | |
2270 | if (GET_MODE (operands[2]) == HImode) | |
2271 | output_asm_insn ("sll %2,0x10,%0", operands); | |
2272 | else if (GET_MODE (operands[2]) == QImode) | |
2273 | output_asm_insn ("sll %2,0x18,%0", operands); | |
2274 | else | |
2275 | abort (); | |
2276 | } | |
6a4bb1fa | 2277 | #endif /* not currently used */ |
ab835497 | 2278 | \f |
09aa6559 JW |
2279 | #if 0 |
2280 | /* ??? These are only used by the movstrsi pattern, but we get better code | |
2281 | in general without that, because emit_block_move can do just as good a | |
2282 | job as this function does when alignment and size are known. When they | |
2283 | aren't known, a call to strcpy may be faster anyways, because it is | |
2284 | likely to be carefully crafted assembly language code, and below we just | |
2285 | do a byte-wise copy. | |
2286 | ||
2287 | Also, emit_block_move expands into multiple read/write RTL insns, which | |
2288 | can then be optimized, whereas our movstrsi pattern can not be optimized | |
2289 | at all. */ | |
2290 | ||
ab835497 RK |
2291 | /* Load the address specified by OPERANDS[3] into the register |
2292 | specified by OPERANDS[0]. | |
2293 | ||
2294 | OPERANDS[3] may be the result of a sum, hence it could either be: | |
2295 | ||
2296 | (1) CONST | |
2297 | (2) REG | |
2298 | (2) REG + CONST_INT | |
2299 | (3) REG + REG + CONST_INT | |
2300 | (4) REG + REG (special case of 3). | |
2301 | ||
2302 | Note that (3) is not a legitimate address. | |
2303 | All cases are handled here. */ | |
2304 | ||
2305 | void | |
2306 | output_load_address (operands) | |
2307 | rtx *operands; | |
2308 | { | |
2309 | rtx base, offset; | |
2310 | ||
2311 | if (CONSTANT_P (operands[3])) | |
2312 | { | |
2313 | output_asm_insn ("set %3,%0", operands); | |
2314 | return; | |
2315 | } | |
2316 | ||
2317 | if (REG_P (operands[3])) | |
2318 | { | |
2319 | if (REGNO (operands[0]) != REGNO (operands[3])) | |
2320 | output_asm_insn ("mov %3,%0", operands); | |
2321 | return; | |
2322 | } | |
2323 | ||
2324 | if (GET_CODE (operands[3]) != PLUS) | |
2325 | abort (); | |
2326 | ||
2327 | base = XEXP (operands[3], 0); | |
2328 | offset = XEXP (operands[3], 1); | |
2329 | ||
2330 | if (GET_CODE (base) == CONST_INT) | |
2331 | { | |
2332 | rtx tmp = base; | |
2333 | base = offset; | |
2334 | offset = tmp; | |
2335 | } | |
2336 | ||
2337 | if (GET_CODE (offset) != CONST_INT) | |
2338 | { | |
2339 | /* Operand is (PLUS (REG) (REG)). */ | |
2340 | base = operands[3]; | |
2341 | offset = const0_rtx; | |
2342 | } | |
2343 | ||
2344 | if (REG_P (base)) | |
2345 | { | |
2346 | operands[6] = base; | |
2347 | operands[7] = offset; | |
2348 | if (SMALL_INT (offset)) | |
2349 | output_asm_insn ("add %6,%7,%0", operands); | |
2350 | else | |
2351 | output_asm_insn ("set %7,%0\n\tadd %0,%6,%0", operands); | |
2352 | } | |
2353 | else if (GET_CODE (base) == PLUS) | |
2354 | { | |
2355 | operands[6] = XEXP (base, 0); | |
2356 | operands[7] = XEXP (base, 1); | |
2357 | operands[8] = offset; | |
2358 | ||
2359 | if (SMALL_INT (offset)) | |
2360 | output_asm_insn ("add %6,%7,%0\n\tadd %0,%8,%0", operands); | |
2361 | else | |
2362 | output_asm_insn ("set %8,%0\n\tadd %0,%6,%0\n\tadd %0,%7,%0", operands); | |
2363 | } | |
2364 | else | |
2365 | abort (); | |
2366 | } | |
2367 | ||
2368 | /* Output code to place a size count SIZE in register REG. | |
2369 | ALIGN is the size of the unit of transfer. | |
2370 | ||
2371 | Because block moves are pipelined, we don't include the | |
2372 | first element in the transfer of SIZE to REG. */ | |
2373 | ||
2374 | static void | |
2375 | output_size_for_block_move (size, reg, align) | |
2376 | rtx size, reg; | |
2377 | rtx align; | |
2378 | { | |
2379 | rtx xoperands[3]; | |
2380 | ||
2381 | xoperands[0] = reg; | |
2382 | xoperands[1] = size; | |
2383 | xoperands[2] = align; | |
2384 | if (GET_CODE (size) == REG) | |
2385 | output_asm_insn ("sub %1,%2,%0", xoperands); | |
2386 | else | |
2387 | { | |
2388 | xoperands[1] | |
2389 | = gen_rtx (CONST_INT, VOIDmode, INTVAL (size) - INTVAL (align)); | |
2390 | output_asm_insn ("set %1,%0", xoperands); | |
2391 | } | |
2392 | } | |
2393 | ||
2394 | /* Emit code to perform a block move. | |
2395 | ||
2396 | OPERANDS[0] is the destination. | |
2397 | OPERANDS[1] is the source. | |
2398 | OPERANDS[2] is the size. | |
2399 | OPERANDS[3] is the alignment safe to use. | |
2400 | OPERANDS[4] is a register we can safely clobber as a temp. */ | |
2401 | ||
2402 | char * | |
2403 | output_block_move (operands) | |
2404 | rtx *operands; | |
2405 | { | |
2406 | /* A vector for our computed operands. Note that load_output_address | |
2407 | makes use of (and can clobber) up to the 8th element of this vector. */ | |
2408 | rtx xoperands[10]; | |
2409 | rtx zoperands[10]; | |
2410 | static int movstrsi_label = 0; | |
2411 | int i; | |
2412 | rtx temp1 = operands[4]; | |
2413 | rtx sizertx = operands[2]; | |
2414 | rtx alignrtx = operands[3]; | |
2415 | int align = INTVAL (alignrtx); | |
210aa14a | 2416 | char label3[30], label5[30]; |
ab835497 RK |
2417 | |
2418 | xoperands[0] = operands[0]; | |
2419 | xoperands[1] = operands[1]; | |
2420 | xoperands[2] = temp1; | |
2421 | ||
391b99c9 RS |
2422 | /* We can't move more than this many bytes at a time because we have only |
2423 | one register, %g1, to move them through. */ | |
2424 | if (align > UNITS_PER_WORD) | |
ab835497 | 2425 | { |
391b99c9 RS |
2426 | align = UNITS_PER_WORD; |
2427 | alignrtx = gen_rtx (CONST_INT, VOIDmode, UNITS_PER_WORD); | |
ab835497 RK |
2428 | } |
2429 | ||
391b99c9 RS |
2430 | /* We consider 8 ld/st pairs, for a total of 16 inline insns to be |
2431 | reasonable here. (Actually will emit a maximum of 18 inline insns for | |
2432 | the case of size == 31 and align == 4). */ | |
2433 | ||
2434 | if (GET_CODE (sizertx) == CONST_INT && (INTVAL (sizertx) / align) <= 8 | |
2435 | && memory_address_p (QImode, plus_constant_for_output (xoperands[0], | |
2436 | INTVAL (sizertx))) | |
2437 | && memory_address_p (QImode, plus_constant_for_output (xoperands[1], | |
2438 | INTVAL (sizertx)))) | |
ab835497 RK |
2439 | { |
2440 | int size = INTVAL (sizertx); | |
391b99c9 | 2441 | int offset = 0; |
ab835497 | 2442 | |
391b99c9 RS |
2443 | /* We will store different integers into this particular RTX. */ |
2444 | xoperands[2] = rtx_alloc (CONST_INT); | |
2445 | PUT_MODE (xoperands[2], VOIDmode); | |
ab835497 | 2446 | |
391b99c9 RS |
2447 | /* This case is currently not handled. Abort instead of generating |
2448 | bad code. */ | |
61a55e8b | 2449 | if (align > UNITS_PER_WORD) |
391b99c9 | 2450 | abort (); |
ab835497 | 2451 | |
a9e27770 | 2452 | if (TARGET_ARCH64 && align >= 8) |
61a55e8b DE |
2453 | { |
2454 | for (i = (size >> 3) - 1; i >= 0; i--) | |
2455 | { | |
2456 | INTVAL (xoperands[2]) = (i << 3) + offset; | |
2457 | output_asm_insn ("ldx [%a1+%2],%%g1\n\tstx %%g1,[%a0+%2]", | |
2458 | xoperands); | |
2459 | } | |
2460 | offset += (size & ~0x7); | |
2461 | size = size & 0x7; | |
2462 | if (size == 0) | |
2463 | return ""; | |
2464 | } | |
2465 | ||
391b99c9 | 2466 | if (align >= 4) |
ab835497 | 2467 | { |
391b99c9 | 2468 | for (i = (size >> 2) - 1; i >= 0; i--) |
ab835497 | 2469 | { |
391b99c9 RS |
2470 | INTVAL (xoperands[2]) = (i << 2) + offset; |
2471 | output_asm_insn ("ld [%a1+%2],%%g1\n\tst %%g1,[%a0+%2]", | |
2472 | xoperands); | |
ab835497 | 2473 | } |
391b99c9 RS |
2474 | offset += (size & ~0x3); |
2475 | size = size & 0x3; | |
2476 | if (size == 0) | |
2477 | return ""; | |
ab835497 | 2478 | } |
391b99c9 RS |
2479 | |
2480 | if (align >= 2) | |
ab835497 | 2481 | { |
391b99c9 | 2482 | for (i = (size >> 1) - 1; i >= 0; i--) |
ab835497 | 2483 | { |
391b99c9 RS |
2484 | INTVAL (xoperands[2]) = (i << 1) + offset; |
2485 | output_asm_insn ("lduh [%a1+%2],%%g1\n\tsth %%g1,[%a0+%2]", | |
2486 | xoperands); | |
ab835497 | 2487 | } |
391b99c9 RS |
2488 | offset += (size & ~0x1); |
2489 | size = size & 0x1; | |
2490 | if (size == 0) | |
2491 | return ""; | |
ab835497 | 2492 | } |
391b99c9 RS |
2493 | |
2494 | if (align >= 1) | |
ab835497 | 2495 | { |
391b99c9 | 2496 | for (i = size - 1; i >= 0; i--) |
ab835497 | 2497 | { |
391b99c9 RS |
2498 | INTVAL (xoperands[2]) = i + offset; |
2499 | output_asm_insn ("ldub [%a1+%2],%%g1\n\tstb %%g1,[%a0+%2]", | |
2500 | xoperands); | |
ab835497 | 2501 | } |
391b99c9 | 2502 | return ""; |
ab835497 | 2503 | } |
391b99c9 RS |
2504 | |
2505 | /* We should never reach here. */ | |
2506 | abort (); | |
ab835497 RK |
2507 | } |
2508 | ||
391b99c9 RS |
2509 | /* If the size isn't known to be a multiple of the alignment, |
2510 | we have to do it in smaller pieces. If we could determine that | |
2511 | the size was a multiple of 2 (or whatever), we could be smarter | |
2512 | about this. */ | |
2513 | if (GET_CODE (sizertx) != CONST_INT) | |
2514 | align = 1; | |
2515 | else | |
2516 | { | |
2517 | int size = INTVAL (sizertx); | |
2518 | while (size % align) | |
2519 | align >>= 1; | |
2520 | } | |
2521 | ||
2522 | if (align != INTVAL (alignrtx)) | |
2523 | alignrtx = gen_rtx (CONST_INT, VOIDmode, align); | |
2524 | ||
ab835497 RK |
2525 | xoperands[3] = gen_rtx (CONST_INT, VOIDmode, movstrsi_label++); |
2526 | xoperands[4] = gen_rtx (CONST_INT, VOIDmode, align); | |
2527 | xoperands[5] = gen_rtx (CONST_INT, VOIDmode, movstrsi_label++); | |
2528 | ||
210aa14a RS |
2529 | ASM_GENERATE_INTERNAL_LABEL (label3, "Lm", INTVAL (xoperands[3])); |
2530 | ASM_GENERATE_INTERNAL_LABEL (label5, "Lm", INTVAL (xoperands[5])); | |
2531 | ||
391b99c9 RS |
2532 | /* This is the size of the transfer. Emit code to decrement the size |
2533 | value by ALIGN, and store the result in the temp1 register. */ | |
ab835497 RK |
2534 | output_size_for_block_move (sizertx, temp1, alignrtx); |
2535 | ||
2536 | /* Must handle the case when the size is zero or negative, so the first thing | |
2537 | we do is compare the size against zero, and only copy bytes if it is | |
2538 | zero or greater. Note that we have already subtracted off the alignment | |
2539 | once, so we must copy 1 alignment worth of bytes if the size is zero | |
2540 | here. | |
2541 | ||
2542 | The SUN assembler complains about labels in branch delay slots, so we | |
b4ac57ab | 2543 | do this before outputting the load address, so that there will always |
ab835497 RK |
2544 | be a harmless insn between the branch here and the next label emitted |
2545 | below. */ | |
2546 | ||
210aa14a RS |
2547 | { |
2548 | char pattern[100]; | |
2549 | ||
2550 | sprintf (pattern, "cmp %%2,0\n\tbl %s", &label5[1]); | |
2551 | output_asm_insn (pattern, xoperands); | |
2552 | } | |
ab835497 RK |
2553 | |
2554 | zoperands[0] = operands[0]; | |
2555 | zoperands[3] = plus_constant_for_output (operands[0], align); | |
2556 | output_load_address (zoperands); | |
2557 | ||
2558 | /* ??? This might be much faster if the loops below were preconditioned | |
2559 | and unrolled. | |
2560 | ||
2561 | That is, at run time, copy enough bytes one at a time to ensure that the | |
2562 | target and source addresses are aligned to the the largest possible | |
2563 | alignment. Then use a preconditioned unrolled loop to copy say 16 | |
2564 | bytes at a time. Then copy bytes one at a time until finish the rest. */ | |
2565 | ||
2566 | /* Output the first label separately, so that it is spaced properly. */ | |
2567 | ||
ab835497 | 2568 | ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "Lm", INTVAL (xoperands[3])); |
ab835497 | 2569 | |
210aa14a RS |
2570 | { |
2571 | char pattern[200]; | |
61a55e8b | 2572 | register char *ld_suffix = ((align == 1) ? "ub" : (align == 2) ? "uh" |
a9e27770 | 2573 | : (align == 8 && TARGET_ARCH64) ? "x" : ""); |
61a55e8b | 2574 | register char *st_suffix = ((align == 1) ? "b" : (align == 2) ? "h" |
a9e27770 | 2575 | : (align == 8 && TARGET_ARCH64) ? "x" : ""); |
210aa14a RS |
2576 | |
2577 | sprintf (pattern, "ld%s [%%1+%%2],%%%%g1\n\tsubcc %%2,%%4,%%2\n\tbge %s\n\tst%s %%%%g1,[%%0+%%2]\n%s:", ld_suffix, &label3[1], st_suffix, &label5[1]); | |
2578 | output_asm_insn (pattern, xoperands); | |
2579 | } | |
2580 | ||
ab835497 | 2581 | return ""; |
ab835497 | 2582 | } |
09aa6559 | 2583 | #endif |
ab835497 RK |
2584 | \f |
2585 | /* Output reasonable peephole for set-on-condition-code insns. | |
2586 | Note that these insns assume a particular way of defining | |
2587 | labels. Therefore, *both* sparc.h and this function must | |
2588 | be changed if a new syntax is needed. */ | |
2589 | ||
2590 | char * | |
2591 | output_scc_insn (operands, insn) | |
2592 | rtx operands[]; | |
2593 | rtx insn; | |
2594 | { | |
2595 | static char string[100]; | |
2596 | rtx label = 0, next = insn; | |
2597 | int need_label = 0; | |
2598 | ||
2599 | /* Try doing a jump optimization which jump.c can't do for us | |
2600 | because we did not expose that setcc works by using branches. | |
2601 | ||
2602 | If this scc insn is followed by an unconditional branch, then have | |
2603 | the jump insn emitted here jump to that location, instead of to | |
2604 | the end of the scc sequence as usual. */ | |
2605 | ||
2606 | do | |
2607 | { | |
2608 | if (GET_CODE (next) == CODE_LABEL) | |
2609 | label = next; | |
2610 | next = NEXT_INSN (next); | |
2611 | if (next == 0) | |
2612 | break; | |
2613 | } | |
2614 | while (GET_CODE (next) == NOTE || GET_CODE (next) == CODE_LABEL); | |
2615 | ||
2616 | /* If we are in a sequence, and the following insn is a sequence also, | |
2617 | then just following the current insn's next field will take us to the | |
2618 | first insn of the next sequence, which is the wrong place. We don't | |
2619 | want to optimize with a branch that has had its delay slot filled. | |
2620 | Avoid this by verifying that NEXT_INSN (PREV_INSN (next)) == next | |
2621 | which fails only if NEXT is such a branch. */ | |
2622 | ||
2623 | if (next && GET_CODE (next) == JUMP_INSN && simplejump_p (next) | |
2624 | && (! final_sequence || NEXT_INSN (PREV_INSN (next)) == next)) | |
2625 | label = JUMP_LABEL (next); | |
2626 | /* If not optimizing, jump label fields are not set. To be safe, always | |
2627 | check here to whether label is still zero. */ | |
2628 | if (label == 0) | |
2629 | { | |
2630 | label = gen_label_rtx (); | |
2631 | need_label = 1; | |
2632 | } | |
2633 | ||
2634 | LABEL_NUSES (label) += 1; | |
2635 | ||
c4ce6853 DE |
2636 | /* operands[3] is an unused slot. */ |
2637 | operands[3] = label; | |
ab835497 RK |
2638 | |
2639 | /* If we are in a delay slot, assume it is the delay slot of an fpcc | |
2640 | insn since our type isn't allowed anywhere else. */ | |
2641 | ||
2642 | /* ??? Fpcc instructions no longer have delay slots, so this code is | |
2643 | probably obsolete. */ | |
2644 | ||
2645 | /* The fastest way to emit code for this is an annulled branch followed | |
2646 | by two move insns. This will take two cycles if the branch is taken, | |
2647 | and three cycles if the branch is not taken. | |
2648 | ||
2649 | However, if we are in the delay slot of another branch, this won't work, | |
2650 | because we can't put a branch in the delay slot of another branch. | |
2651 | The above sequence would effectively take 3 or 4 cycles respectively | |
2652 | since a no op would have be inserted between the two branches. | |
2653 | In this case, we want to emit a move, annulled branch, and then the | |
2654 | second move. This sequence always takes 3 cycles, and hence is faster | |
2655 | when we are in a branch delay slot. */ | |
2656 | ||
2657 | if (final_sequence) | |
2658 | { | |
2659 | strcpy (string, "mov 0,%0\n\t"); | |
c4ce6853 | 2660 | strcat (string, output_cbranch (operands[2], 3, 0, 1, 0)); |
ab835497 RK |
2661 | strcat (string, "\n\tmov 1,%0"); |
2662 | } | |
2663 | else | |
2664 | { | |
c4ce6853 | 2665 | strcpy (string, output_cbranch (operands[2], 3, 0, 1, 0)); |
ab835497 RK |
2666 | strcat (string, "\n\tmov 1,%0\n\tmov 0,%0"); |
2667 | } | |
2668 | ||
2669 | if (need_label) | |
c4ce6853 | 2670 | strcat (string, "\n%l3:"); |
ab835497 RK |
2671 | |
2672 | return string; | |
2673 | } | |
2674 | \f | |
61a55e8b DE |
2675 | /* Vectors to keep interesting information about registers where it can easily |
2676 | be got. We use to use the actual mode value as the bit number, but there | |
2677 | are more than 32 modes now. Instead we use two tables: one indexed by | |
2678 | hard register number, and one indexed by mode. */ | |
2679 | ||
2680 | /* The purpose of sparc_mode_class is to shrink the range of modes so that | |
2681 | they all fit (as bit numbers) in a 32 bit word (again). Each real mode is | |
2682 | mapped into one sparc_mode_class mode. */ | |
2683 | ||
2684 | enum sparc_mode_class { | |
61a55e8b | 2685 | S_MODE, D_MODE, T_MODE, O_MODE, |
c4ce6853 DE |
2686 | SF_MODE, DF_MODE, TF_MODE, OF_MODE, |
2687 | CC_MODE, CCFP_MODE | |
61a55e8b | 2688 | }; |
ab835497 | 2689 | |
61a55e8b DE |
2690 | /* Modes for single-word and smaller quantities. */ |
2691 | #define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE)) | |
2692 | ||
2693 | /* Modes for double-word and smaller quantities. */ | |
2694 | #define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE)) | |
2695 | ||
2696 | /* Modes for quad-word and smaller quantities. */ | |
2697 | #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE)) | |
ab835497 | 2698 | |
1e4eb8d1 JW |
2699 | /* Modes for single-float quantities. We must allow any single word or |
2700 | smaller quantity. This is because the fix/float conversion instructions | |
2701 | take integer inputs/outputs from the float registers. */ | |
2702 | #define SF_MODES (S_MODES) | |
ab835497 | 2703 | |
61a55e8b DE |
2704 | /* Modes for double-float and smaller quantities. */ |
2705 | #define DF_MODES (S_MODES | D_MODES) | |
2706 | ||
2707 | /* ??? Sparc64 fp regs cannot hold DImode values. */ | |
2708 | #define DF_MODES64 (SF_MODES | DF_MODE /* | D_MODE*/) | |
2709 | ||
2710 | /* Modes for double-float only quantities. */ | |
c4ce6853 DE |
2711 | /* ??? Sparc64 fp regs cannot hold DImode values. |
2712 | See fix_truncsfdi2. */ | |
61a55e8b DE |
2713 | #define DF_ONLY_MODES ((1 << (int) DF_MODE) /*| (1 << (int) D_MODE)*/) |
2714 | ||
2715 | /* Modes for double-float and larger quantities. */ | |
2716 | #define DF_UP_MODES (DF_ONLY_MODES | TF_ONLY_MODES) | |
ab835497 | 2717 | |
61a55e8b DE |
2718 | /* Modes for quad-float only quantities. */ |
2719 | #define TF_ONLY_MODES (1 << (int) TF_MODE) | |
2720 | ||
2721 | /* Modes for quad-float and smaller quantities. */ | |
2722 | #define TF_MODES (DF_MODES | TF_ONLY_MODES) | |
2723 | ||
c4ce6853 DE |
2724 | /* ??? Sparc64 fp regs cannot hold DImode values. |
2725 | See fix_truncsfdi2. */ | |
61a55e8b | 2726 | #define TF_MODES64 (DF_MODES64 | TF_ONLY_MODES) |
ab835497 | 2727 | |
c4ce6853 DE |
2728 | /* Modes for condition codes. */ |
2729 | #define CC_MODES (1 << (int) CC_MODE) | |
2730 | #define CCFP_MODES (1 << (int) CCFP_MODE) | |
2731 | ||
ab835497 RK |
2732 | /* Value is 1 if register/mode pair is acceptable on sparc. |
2733 | The funny mixture of D and T modes is because integer operations | |
2734 | do not specially operate on tetra quantities, so non-quad-aligned | |
2735 | registers can hold quadword quantities (except %o4 and %i4 because | |
c4ce6853 | 2736 | they cross fixed registers). */ |
ab835497 | 2737 | |
61a55e8b DE |
2738 | /* This points to either the 32 bit or the 64 bit version. */ |
2739 | int *hard_regno_mode_classes; | |
2740 | ||
2741 | static int hard_32bit_mode_classes[] = { | |
c4ce6853 | 2742 | S_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, |
ab835497 RK |
2743 | T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES, |
2744 | T_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, | |
2745 | T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES, | |
2746 | ||
2747 | TF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES, | |
2748 | TF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES, | |
2749 | TF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES, | |
61a55e8b | 2750 | TF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES, |
a9e27770 DE |
2751 | |
2752 | /* FP regs f32 to f63. Only the even numbered registers actually exist, | |
2753 | and none can hold SFmode/SImode values. */ | |
2754 | DF_UP_MODES, 0, DF_ONLY_MODES, 0, DF_UP_MODES, 0, DF_ONLY_MODES, 0, | |
2755 | DF_UP_MODES, 0, DF_ONLY_MODES, 0, DF_UP_MODES, 0, DF_ONLY_MODES, 0, | |
2756 | DF_UP_MODES, 0, DF_ONLY_MODES, 0, DF_UP_MODES, 0, DF_ONLY_MODES, 0, | |
2757 | DF_UP_MODES, 0, DF_ONLY_MODES, 0, DF_UP_MODES, 0, DF_ONLY_MODES, 0, | |
2758 | ||
2759 | /* %fcc[0123] */ | |
c4ce6853 DE |
2760 | CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES, |
2761 | ||
2762 | /* %icc */ | |
2763 | CC_MODES | |
61a55e8b DE |
2764 | }; |
2765 | ||
2766 | static int hard_64bit_mode_classes[] = { | |
c4ce6853 | 2767 | D_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, |
61a55e8b DE |
2768 | T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, |
2769 | T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, | |
2770 | T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, | |
2771 | ||
2772 | TF_MODES64, SF_MODES, DF_MODES64, SF_MODES, TF_MODES64, SF_MODES, DF_MODES64, SF_MODES, | |
2773 | TF_MODES64, SF_MODES, DF_MODES64, SF_MODES, TF_MODES64, SF_MODES, DF_MODES64, SF_MODES, | |
2774 | TF_MODES64, SF_MODES, DF_MODES64, SF_MODES, TF_MODES64, SF_MODES, DF_MODES64, SF_MODES, | |
2775 | TF_MODES64, SF_MODES, DF_MODES64, SF_MODES, TF_MODES64, SF_MODES, DF_MODES64, SF_MODES, | |
2776 | ||
a9e27770 | 2777 | /* FP regs f32 to f63. Only the even numbered registers actually exist, |
61a55e8b DE |
2778 | and none can hold SFmode/SImode values. */ |
2779 | DF_UP_MODES, 0, DF_ONLY_MODES, 0, DF_UP_MODES, 0, DF_ONLY_MODES, 0, | |
2780 | DF_UP_MODES, 0, DF_ONLY_MODES, 0, DF_UP_MODES, 0, DF_ONLY_MODES, 0, | |
2781 | DF_UP_MODES, 0, DF_ONLY_MODES, 0, DF_UP_MODES, 0, DF_ONLY_MODES, 0, | |
2782 | DF_UP_MODES, 0, DF_ONLY_MODES, 0, DF_UP_MODES, 0, DF_ONLY_MODES, 0, | |
2783 | ||
2784 | /* %fcc[0123] */ | |
c4ce6853 DE |
2785 | CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES, |
2786 | ||
2787 | /* %icc */ | |
2788 | CC_MODES | |
61a55e8b DE |
2789 | }; |
2790 | ||
2791 | int sparc_mode_class [NUM_MACHINE_MODES]; | |
2792 | ||
c4ce6853 DE |
2793 | enum reg_class sparc_regno_reg_class[FIRST_PSEUDO_REGISTER]; |
2794 | ||
61a55e8b DE |
2795 | static void |
2796 | sparc_init_modes () | |
2797 | { | |
2798 | int i; | |
2799 | ||
61a55e8b DE |
2800 | for (i = 0; i < NUM_MACHINE_MODES; i++) |
2801 | { | |
2802 | switch (GET_MODE_CLASS (i)) | |
2803 | { | |
2804 | case MODE_INT: | |
2805 | case MODE_PARTIAL_INT: | |
2806 | case MODE_COMPLEX_INT: | |
2807 | if (GET_MODE_SIZE (i) <= 4) | |
2808 | sparc_mode_class[i] = 1 << (int) S_MODE; | |
2809 | else if (GET_MODE_SIZE (i) == 8) | |
2810 | sparc_mode_class[i] = 1 << (int) D_MODE; | |
2811 | else if (GET_MODE_SIZE (i) == 16) | |
2812 | sparc_mode_class[i] = 1 << (int) T_MODE; | |
2813 | else if (GET_MODE_SIZE (i) == 32) | |
2814 | sparc_mode_class[i] = 1 << (int) O_MODE; | |
2815 | else | |
2816 | sparc_mode_class[i] = 0; | |
2817 | break; | |
2818 | case MODE_FLOAT: | |
2819 | case MODE_COMPLEX_FLOAT: | |
2820 | if (GET_MODE_SIZE (i) <= 4) | |
2821 | sparc_mode_class[i] = 1 << (int) SF_MODE; | |
2822 | else if (GET_MODE_SIZE (i) == 8) | |
2823 | sparc_mode_class[i] = 1 << (int) DF_MODE; | |
2824 | else if (GET_MODE_SIZE (i) == 16) | |
2825 | sparc_mode_class[i] = 1 << (int) TF_MODE; | |
2826 | else if (GET_MODE_SIZE (i) == 32) | |
2827 | sparc_mode_class[i] = 1 << (int) OF_MODE; | |
2828 | else | |
2829 | sparc_mode_class[i] = 0; | |
2830 | break; | |
2831 | case MODE_CC: | |
2832 | default: | |
2833 | /* mode_class hasn't been initialized yet for EXTRA_CC_MODES, so | |
2834 | we must explicitly check for them here. */ | |
2835 | if (i == (int) CCFPmode || i == (int) CCFPEmode) | |
2836 | sparc_mode_class[i] = 1 << (int) CCFP_MODE; | |
2837 | else if (i == (int) CCmode || i == (int) CC_NOOVmode | |
a9e27770 | 2838 | || i == (int) CCXmode || i == (int) CCX_NOOVmode) |
c4ce6853 | 2839 | sparc_mode_class[i] = 1 << (int) CC_MODE; |
61a55e8b DE |
2840 | else |
2841 | sparc_mode_class[i] = 0; | |
2842 | break; | |
2843 | } | |
2844 | } | |
2845 | ||
a9e27770 | 2846 | if (TARGET_ARCH64) |
61a55e8b DE |
2847 | hard_regno_mode_classes = hard_64bit_mode_classes; |
2848 | else | |
2849 | hard_regno_mode_classes = hard_32bit_mode_classes; | |
c4ce6853 DE |
2850 | |
2851 | /* Initialize the array used by REGNO_REG_CLASS. */ | |
2852 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
2853 | { | |
2854 | if (i < 32) | |
2855 | sparc_regno_reg_class[i] = GENERAL_REGS; | |
2856 | else if (i < 64) | |
2857 | sparc_regno_reg_class[i] = FP_REGS; | |
2858 | else if (i < 96) | |
2859 | sparc_regno_reg_class[i] = EXTRA_FP_REGS; | |
2860 | else if (i < 100) | |
2861 | sparc_regno_reg_class[i] = FPCC_REGS; | |
2862 | else | |
2863 | sparc_regno_reg_class[i] = NO_REGS; | |
2864 | } | |
61a55e8b | 2865 | } |
ab835497 | 2866 | \f |
61a55e8b DE |
2867 | /* Save non call used registers from LOW to HIGH at BASE+OFFSET. |
2868 | N_REGS is the number of 4-byte regs saved thus far. This applies even to | |
2869 | v9 int regs as it simplifies the code. */ | |
2870 | ||
ab835497 | 2871 | #ifdef __GNUC__ |
99c7b2f6 | 2872 | __inline__ |
ab835497 RK |
2873 | #endif |
2874 | static int | |
61a55e8b | 2875 | save_regs (file, low, high, base, offset, n_regs) |
ab835497 RK |
2876 | FILE *file; |
2877 | int low, high; | |
2878 | char *base; | |
2879 | int offset; | |
61a55e8b | 2880 | int n_regs; |
ab835497 RK |
2881 | { |
2882 | int i; | |
2883 | ||
a9e27770 | 2884 | if (TARGET_ARCH64 && high <= 32) |
ab835497 | 2885 | { |
61a55e8b DE |
2886 | for (i = low; i < high; i++) |
2887 | { | |
2888 | if (regs_ever_live[i] && ! call_used_regs[i]) | |
2889 | fprintf (file, "\tstx %s,[%s+%d]\n", | |
2890 | reg_names[i], base, offset + 4 * n_regs), | |
2891 | n_regs += 2; | |
2892 | } | |
ab835497 | 2893 | } |
61a55e8b DE |
2894 | else |
2895 | { | |
2896 | for (i = low; i < high; i += 2) | |
2897 | { | |
2898 | if (regs_ever_live[i] && ! call_used_regs[i]) | |
2899 | if (regs_ever_live[i+1] && ! call_used_regs[i+1]) | |
2900 | fprintf (file, "\tstd %s,[%s+%d]\n", | |
2901 | reg_names[i], base, offset + 4 * n_regs), | |
2902 | n_regs += 2; | |
2903 | else | |
2904 | fprintf (file, "\tst %s,[%s+%d]\n", | |
2905 | reg_names[i], base, offset + 4 * n_regs), | |
2906 | n_regs += 2; | |
2907 | else if (regs_ever_live[i+1] && ! call_used_regs[i+1]) | |
2908 | fprintf (file, "\tst %s,[%s+%d]\n", | |
2909 | reg_names[i+1], base, offset + 4 * n_regs + 4), | |
2910 | n_regs += 2; | |
2911 | } | |
2912 | } | |
2913 | return n_regs; | |
ab835497 RK |
2914 | } |
2915 | ||
61a55e8b DE |
2916 | /* Restore non call used registers from LOW to HIGH at BASE+OFFSET. |
2917 | ||
2918 | N_REGS is the number of 4-byte regs saved thus far. This applies even to | |
2919 | v9 int regs as it simplifies the code. */ | |
2920 | ||
ab835497 | 2921 | #ifdef __GNUC__ |
99c7b2f6 | 2922 | __inline__ |
ab835497 RK |
2923 | #endif |
2924 | static int | |
61a55e8b | 2925 | restore_regs (file, low, high, base, offset, n_regs) |
ab835497 RK |
2926 | FILE *file; |
2927 | int low, high; | |
2928 | char *base; | |
2929 | int offset; | |
61a55e8b | 2930 | int n_regs; |
ab835497 RK |
2931 | { |
2932 | int i; | |
2933 | ||
a9e27770 | 2934 | if (TARGET_ARCH64 && high <= 32) |
61a55e8b DE |
2935 | { |
2936 | for (i = low; i < high; i++) | |
2937 | { | |
2938 | if (regs_ever_live[i] && ! call_used_regs[i]) | |
2939 | fprintf (file, "\tldx [%s+%d], %s\n", | |
2940 | base, offset + 4 * n_regs, reg_names[i]), | |
2941 | n_regs += 2; | |
2942 | } | |
2943 | } | |
2944 | else | |
ab835497 | 2945 | { |
61a55e8b DE |
2946 | for (i = low; i < high; i += 2) |
2947 | { | |
2948 | if (regs_ever_live[i] && ! call_used_regs[i]) | |
2949 | if (regs_ever_live[i+1] && ! call_used_regs[i+1]) | |
2950 | fprintf (file, "\tldd [%s+%d], %s\n", | |
2951 | base, offset + 4 * n_regs, reg_names[i]), | |
2952 | n_regs += 2; | |
2953 | else | |
2954 | fprintf (file, "\tld [%s+%d],%s\n", | |
2955 | base, offset + 4 * n_regs, reg_names[i]), | |
2956 | n_regs += 2; | |
2957 | else if (regs_ever_live[i+1] && ! call_used_regs[i+1]) | |
2958 | fprintf (file, "\tld [%s+%d],%s\n", | |
2959 | base, offset + 4 * n_regs + 4, reg_names[i+1]), | |
2960 | n_regs += 2; | |
2961 | } | |
ab835497 | 2962 | } |
61a55e8b | 2963 | return n_regs; |
ab835497 RK |
2964 | } |
2965 | ||
2966 | /* Static variables we want to share between prologue and epilogue. */ | |
2967 | ||
61a55e8b DE |
2968 | /* Number of live general or floating point registers needed to be saved |
2969 | (as 4-byte quantities). This is only done if TARGET_EPILOGUE. */ | |
2970 | static int num_gfregs; | |
2971 | ||
2972 | /* Compute the frame size required by the function. This function is called | |
2973 | during the reload pass and also by output_function_prologue(). */ | |
ab835497 | 2974 | |
ab835497 RK |
2975 | int |
2976 | compute_frame_size (size, leaf_function) | |
2977 | int size; | |
2978 | int leaf_function; | |
2979 | { | |
61a55e8b | 2980 | int n_regs = 0, i; |
ab835497 | 2981 | int outgoing_args_size = (current_function_outgoing_args_size |
a9e27770 | 2982 | #if ! SPARC_ARCH64 |
61a55e8b DE |
2983 | + REG_PARM_STACK_SPACE (current_function_decl) |
2984 | #endif | |
2985 | ); | |
ab835497 | 2986 | |
61a55e8b | 2987 | if (TARGET_EPILOGUE) |
ab835497 | 2988 | { |
61a55e8b DE |
2989 | /* N_REGS is the number of 4-byte regs saved thus far. This applies |
2990 | even to v9 int regs to be consistent with save_regs/restore_regs. */ | |
2991 | ||
a9e27770 | 2992 | if (TARGET_ARCH64) |
61a55e8b DE |
2993 | { |
2994 | for (i = 0; i < 8; i++) | |
2995 | if (regs_ever_live[i] && ! call_used_regs[i]) | |
2996 | n_regs += 2; | |
2997 | } | |
2998 | else | |
2999 | { | |
3000 | for (i = 0; i < 8; i += 2) | |
3001 | if ((regs_ever_live[i] && ! call_used_regs[i]) | |
3002 | || (regs_ever_live[i+1] && ! call_used_regs[i+1])) | |
3003 | n_regs += 2; | |
3004 | } | |
3005 | ||
3006 | for (i = 32; i < (TARGET_V9 ? 96 : 64); i += 2) | |
ab835497 RK |
3007 | if ((regs_ever_live[i] && ! call_used_regs[i]) |
3008 | || (regs_ever_live[i+1] && ! call_used_regs[i+1])) | |
61a55e8b | 3009 | n_regs += 2; |
ab835497 RK |
3010 | } |
3011 | ||
3012 | /* Set up values for use in `function_epilogue'. */ | |
61a55e8b | 3013 | num_gfregs = n_regs; |
ab835497 | 3014 | |
61a55e8b DE |
3015 | if (leaf_function && n_regs == 0 |
3016 | && size == 0 && current_function_outgoing_args_size == 0) | |
3017 | { | |
3018 | actual_fsize = apparent_fsize = 0; | |
3019 | } | |
3020 | else | |
3021 | { | |
3022 | /* We subtract STARTING_FRAME_OFFSET, remember it's negative. | |
3023 | The stack bias (if any) is taken out to undo its effects. */ | |
3024 | apparent_fsize = (size - STARTING_FRAME_OFFSET + SPARC_STACK_BIAS + 7) & -8; | |
3025 | apparent_fsize += n_regs * 4; | |
3026 | actual_fsize = apparent_fsize + ((outgoing_args_size + 7) & -8); | |
3027 | } | |
ab835497 RK |
3028 | |
3029 | /* Make sure nothing can clobber our register windows. | |
3030 | If a SAVE must be done, or there is a stack-local variable, | |
61a55e8b DE |
3031 | the register window area must be allocated. |
3032 | ??? For v9 we need an additional 8 bytes of reserved space, apparently | |
3033 | it's needed by v8 as well. */ | |
ab835497 | 3034 | if (leaf_function == 0 || size > 0) |
61a55e8b | 3035 | actual_fsize += (16 * UNITS_PER_WORD) + 8; |
ab835497 | 3036 | |
61a55e8b DE |
3037 | return SPARC_STACK_ALIGN (actual_fsize); |
3038 | } | |
3039 | ||
3040 | /* Build a (32 bit) big number in a register. */ | |
86735b02 | 3041 | /* ??? We may be able to use the set macro here too. */ |
61a55e8b DE |
3042 | |
3043 | static void | |
3044 | build_big_number (file, num, reg) | |
3045 | FILE *file; | |
3046 | int num; | |
3047 | char *reg; | |
3048 | { | |
a9e27770 | 3049 | if (num >= 0 || ! TARGET_ARCH64) |
61a55e8b DE |
3050 | { |
3051 | fprintf (file, "\tsethi %%hi(%d),%s\n", num, reg); | |
3052 | if ((num & 0x3ff) != 0) | |
3053 | fprintf (file, "\tor %s,%%lo(%d),%s\n", reg, num, reg); | |
3054 | } | |
a9e27770 | 3055 | else /* num < 0 && TARGET_ARCH64 */ |
61a55e8b DE |
3056 | { |
3057 | /* Sethi does not sign extend, so we must use a little trickery | |
3058 | to use it for negative numbers. Invert the constant before | |
3059 | loading it in, then use xor immediate to invert the loaded bits | |
3060 | (along with the upper 32 bits) to the desired constant. This | |
3061 | works because the sethi and immediate fields overlap. */ | |
3062 | int asize = num; | |
3063 | int inv = ~asize; | |
3064 | int low = -0x400 + (asize & 0x3FF); | |
3065 | ||
3066 | fprintf (file, "\tsethi %%hi(%d),%s\n\txor %s,%d,%s\n", | |
3067 | inv, reg, reg, low, reg); | |
3068 | } | |
ab835497 RK |
3069 | } |
3070 | ||
915f619f JW |
3071 | /* Output code for the function prologue. */ |
3072 | ||
ab835497 RK |
3073 | void |
3074 | output_function_prologue (file, size, leaf_function) | |
3075 | FILE *file; | |
3076 | int size; | |
915f619f | 3077 | int leaf_function; |
ab835497 | 3078 | { |
915f619f JW |
3079 | /* Need to use actual_fsize, since we are also allocating |
3080 | space for our callee (and our own register save area). */ | |
ab835497 RK |
3081 | actual_fsize = compute_frame_size (size, leaf_function); |
3082 | ||
61a55e8b DE |
3083 | if (leaf_function) |
3084 | { | |
3085 | frame_base_name = "%sp"; | |
3086 | frame_base_offset = actual_fsize + SPARC_STACK_BIAS; | |
3087 | } | |
3088 | else | |
3089 | { | |
3090 | frame_base_name = "%fp"; | |
3091 | frame_base_offset = SPARC_STACK_BIAS; | |
3092 | } | |
3093 | ||
c6aa9ce1 | 3094 | /* This is only for the human reader. */ |
ab835497 | 3095 | fprintf (file, "\t!#PROLOGUE# 0\n"); |
c6aa9ce1 | 3096 | |
915f619f JW |
3097 | if (actual_fsize == 0) |
3098 | /* do nothing. */ ; | |
3592ea0d | 3099 | else if (! leaf_function && ! TARGET_BROKEN_SAVERESTORE) |
ab835497 | 3100 | { |
3592ea0d | 3101 | if (actual_fsize <= 4096) |
ab835497 | 3102 | fprintf (file, "\tsave %%sp,-%d,%%sp\n", actual_fsize); |
3592ea0d | 3103 | else if (actual_fsize <= 8192) |
915f619f JW |
3104 | { |
3105 | fprintf (file, "\tsave %%sp,-4096,%%sp\n"); | |
3106 | fprintf (file, "\tadd %%sp,-%d,%%sp\n", actual_fsize - 4096); | |
3107 | } | |
3108 | else | |
3109 | { | |
3592ea0d DE |
3110 | build_big_number (file, -actual_fsize, "%g1"); |
3111 | fprintf (file, "\tsave %%sp,%%g1,%%sp\n"); | |
915f619f | 3112 | } |
ab835497 | 3113 | } |
5f4241d5 | 3114 | else if (! leaf_function && TARGET_BROKEN_SAVERESTORE) |
ab835497 | 3115 | { |
5f4241d5 | 3116 | /* We assume the environment will properly handle or otherwise avoid |
3592ea0d DE |
3117 | trouble associated with an interrupt occuring after the `save' or |
3118 | trap occuring during it. */ | |
5f4241d5 | 3119 | fprintf (file, "\tsave\n"); |
3592ea0d | 3120 | |
5f4241d5 DE |
3121 | if (actual_fsize <= 4096) |
3122 | fprintf (file, "\tadd %%fp,-%d,%%sp\n", actual_fsize); | |
3123 | else if (actual_fsize <= 8192) | |
3124 | { | |
3125 | fprintf (file, "\tadd %%fp,-4096,%%sp\n"); | |
3126 | fprintf (file, "\tadd %%fp,-%d,%%sp\n", actual_fsize - 4096); | |
3127 | } | |
3128 | else | |
3129 | { | |
3130 | build_big_number (file, -actual_fsize, "%g1"); | |
3131 | fprintf (file, "\tadd %%fp,%%g1,%%sp\n"); | |
3132 | } | |
3133 | } | |
3134 | else /* leaf function */ | |
3135 | { | |
3592ea0d DE |
3136 | if (actual_fsize <= 4096) |
3137 | fprintf (file, "\tadd %%sp,-%d,%%sp\n", actual_fsize); | |
3138 | else if (actual_fsize <= 8192) | |
3139 | { | |
3140 | fprintf (file, "\tadd %%sp,-4096,%%sp\n"); | |
3141 | fprintf (file, "\tadd %%sp,-%d,%%sp\n", actual_fsize - 4096); | |
3142 | } | |
915f619f | 3143 | else |
3592ea0d DE |
3144 | { |
3145 | build_big_number (file, -actual_fsize, "%g1"); | |
3146 | fprintf (file, "\tadd %%sp,%%g1,%%sp\n"); | |
3147 | } | |
ab835497 RK |
3148 | } |
3149 | ||
3150 | /* If doing anything with PIC, do it now. */ | |
3151 | if (! flag_pic) | |
3152 | fprintf (file, "\t!#PROLOGUE# 1\n"); | |
3153 | ||
61a55e8b DE |
3154 | /* Call saved registers are saved just above the outgoing argument area. */ |
3155 | if (num_gfregs) | |
ab835497 | 3156 | { |
61a55e8b DE |
3157 | int offset, n_regs; |
3158 | char *base; | |
ab835497 | 3159 | |
61a55e8b DE |
3160 | offset = -apparent_fsize + frame_base_offset; |
3161 | if (offset < -4096 || offset + num_gfregs * 4 > 4096) | |
3162 | { | |
3163 | /* ??? This might be optimized a little as %g1 might already have a | |
3164 | value close enough that a single add insn will do. */ | |
3165 | /* ??? Although, all of this is probably only a temporary fix | |
3166 | because if %g1 can hold a function result, then | |
3167 | output_function_epilogue will lose (the result will get | |
3168 | clobbered). */ | |
3169 | build_big_number (file, offset, "%g1"); | |
3170 | fprintf (file, "\tadd %s,%%g1,%%g1\n", frame_base_name); | |
3171 | base = "%g1"; | |
3172 | offset = 0; | |
3173 | } | |
ab835497 | 3174 | else |
61a55e8b DE |
3175 | { |
3176 | base = frame_base_name; | |
3177 | } | |
ab835497 RK |
3178 | |
3179 | if (TARGET_EPILOGUE && ! leaf_function) | |
61a55e8b DE |
3180 | /* ??? Originally saved regs 0-15 here. */ |
3181 | n_regs = save_regs (file, 0, 8, base, offset, 0); | |
ab835497 | 3182 | else if (leaf_function) |
61a55e8b DE |
3183 | /* ??? Originally saved regs 0-31 here. */ |
3184 | n_regs = save_regs (file, 0, 8, base, offset, 0); | |
ab835497 | 3185 | if (TARGET_EPILOGUE) |
61a55e8b | 3186 | save_regs (file, 32, TARGET_V9 ? 96 : 64, base, offset, n_regs); |
ab835497 RK |
3187 | } |
3188 | ||
ab835497 RK |
3189 | leaf_label = 0; |
3190 | if (leaf_function && actual_fsize != 0) | |
3191 | { | |
3192 | /* warning ("leaf procedure with frame size %d", actual_fsize); */ | |
3193 | if (! TARGET_EPILOGUE) | |
3194 | leaf_label = gen_label_rtx (); | |
3195 | } | |
3196 | } | |
3197 | ||
915f619f JW |
3198 | /* Output code for the function epilogue. */ |
3199 | ||
ab835497 | 3200 | void |
ef8200df | 3201 | output_function_epilogue (file, size, leaf_function) |
ab835497 RK |
3202 | FILE *file; |
3203 | int size; | |
ef8200df | 3204 | int leaf_function; |
ab835497 | 3205 | { |
ab835497 RK |
3206 | char *ret; |
3207 | ||
3208 | if (leaf_label) | |
3209 | { | |
ab835497 RK |
3210 | emit_label_after (leaf_label, get_last_insn ()); |
3211 | final_scan_insn (get_last_insn (), file, 0, 0, 1); | |
3212 | } | |
3213 | ||
b69649e4 RK |
3214 | #ifdef FUNCTION_BLOCK_PROFILER_EXIT |
3215 | else if (profile_block_flag == 2) | |
3216 | { | |
3217 | FUNCTION_BLOCK_PROFILER_EXIT(file); | |
3218 | } | |
3219 | #endif | |
3220 | ||
61a55e8b DE |
3221 | /* Restore any call saved registers. */ |
3222 | if (num_gfregs) | |
ab835497 | 3223 | { |
61a55e8b DE |
3224 | int offset, n_regs; |
3225 | char *base; | |
ab835497 | 3226 | |
61a55e8b DE |
3227 | offset = -apparent_fsize + frame_base_offset; |
3228 | if (offset < -4096 || offset + num_gfregs * 4 > 4096 - 8 /*double*/) | |
3229 | { | |
3230 | build_big_number (file, offset, "%g1"); | |
3231 | fprintf (file, "\tadd %s,%%g1,%%g1\n", frame_base_name); | |
3232 | base = "%g1"; | |
3233 | offset = 0; | |
3234 | } | |
ab835497 | 3235 | else |
61a55e8b DE |
3236 | { |
3237 | base = frame_base_name; | |
3238 | } | |
ab835497 RK |
3239 | |
3240 | if (TARGET_EPILOGUE && ! leaf_function) | |
61a55e8b DE |
3241 | /* ??? Originally saved regs 0-15 here. */ |
3242 | n_regs = restore_regs (file, 0, 8, base, offset, 0); | |
ab835497 | 3243 | else if (leaf_function) |
61a55e8b DE |
3244 | /* ??? Originally saved regs 0-31 here. */ |
3245 | n_regs = restore_regs (file, 0, 8, base, offset, 0); | |
ab835497 | 3246 | if (TARGET_EPILOGUE) |
61a55e8b | 3247 | restore_regs (file, 32, TARGET_V9 ? 96 : 64, base, offset, n_regs); |
ab835497 RK |
3248 | } |
3249 | ||
3250 | /* Work out how to skip the caller's unimp instruction if required. */ | |
3251 | if (leaf_function) | |
61a55e8b | 3252 | ret = (SKIP_CALLERS_UNIMP_P ? "jmp %o7+12" : "retl"); |
ab835497 | 3253 | else |
61a55e8b | 3254 | ret = (SKIP_CALLERS_UNIMP_P ? "jmp %i7+12" : "ret"); |
ab835497 | 3255 | |
ef8200df | 3256 | if (TARGET_EPILOGUE || leaf_label) |
ab835497 | 3257 | { |
ef8200df JW |
3258 | int old_target_epilogue = TARGET_EPILOGUE; |
3259 | target_flags &= ~old_target_epilogue; | |
ab835497 | 3260 | |
ef8200df JW |
3261 | if (! leaf_function) |
3262 | { | |
3263 | /* If we wound up with things in our delay slot, flush them here. */ | |
3264 | if (current_function_epilogue_delay_list) | |
ab835497 | 3265 | { |
ef8200df JW |
3266 | rtx insn = emit_jump_insn_after (gen_rtx (RETURN, VOIDmode), |
3267 | get_last_insn ()); | |
3268 | PATTERN (insn) = gen_rtx (PARALLEL, VOIDmode, | |
3269 | gen_rtvec (2, | |
3270 | PATTERN (XEXP (current_function_epilogue_delay_list, 0)), | |
3271 | PATTERN (insn))); | |
3272 | final_scan_insn (insn, file, 1, 0, 1); | |
ab835497 RK |
3273 | } |
3274 | else | |
ef8200df JW |
3275 | fprintf (file, "\t%s\n\trestore\n", ret); |
3276 | } | |
915f619f JW |
3277 | /* All of the following cases are for leaf functions. */ |
3278 | else if (current_function_epilogue_delay_list) | |
ef8200df | 3279 | { |
915f619f JW |
3280 | /* eligible_for_epilogue_delay_slot ensures that if this is a |
3281 | leaf function, then we will only have insn in the delay slot | |
3282 | if the frame size is zero, thus no adjust for the stack is | |
3283 | needed here. */ | |
3284 | if (actual_fsize != 0) | |
ef8200df | 3285 | abort (); |
915f619f JW |
3286 | fprintf (file, "\t%s\n", ret); |
3287 | final_scan_insn (XEXP (current_function_epilogue_delay_list, 0), | |
3288 | file, 1, 0, 1); | |
ab835497 | 3289 | } |
9bb7ffda JW |
3290 | /* Output 'nop' instead of 'sub %sp,-0,%sp' when no frame, so as to |
3291 | avoid generating confusing assembly language output. */ | |
3292 | else if (actual_fsize == 0) | |
3293 | fprintf (file, "\t%s\n\tnop\n", ret); | |
915f619f JW |
3294 | else if (actual_fsize <= 4096) |
3295 | fprintf (file, "\t%s\n\tsub %%sp,-%d,%%sp\n", ret, actual_fsize); | |
3296 | else if (actual_fsize <= 8192) | |
3297 | fprintf (file, "\tsub %%sp,-4096,%%sp\n\t%s\n\tsub %%sp,-%d,%%sp\n", | |
3298 | ret, actual_fsize - 4096); | |
3299 | else if ((actual_fsize & 0x3ff) == 0) | |
3300 | fprintf (file, "\tsethi %%hi(%d),%%g1\n\t%s\n\tadd %%sp,%%g1,%%sp\n", | |
3301 | actual_fsize, ret); | |
3302 | else | |
3303 | fprintf (file, "\tsethi %%hi(%d),%%g1\n\tor %%g1,%%lo(%d),%%g1\n\t%s\n\tadd %%sp,%%g1,%%sp\n", | |
3304 | actual_fsize, actual_fsize, ret); | |
ef8200df | 3305 | target_flags |= old_target_epilogue; |
ab835497 RK |
3306 | } |
3307 | } | |
3ea1fdd3 | 3308 | |
61a55e8b DE |
3309 | /* Do what is necessary for `va_start'. The argument is ignored. |
3310 | !v9: We look at the current function to determine if stdarg or varargs | |
3311 | is used and return the address of the first unnamed parameter. | |
3312 | v9: We save the argument integer and floating point regs in a buffer, and | |
3313 | return the address of this buffer. The rest is handled in va-sparc.h. */ | |
a9e27770 | 3314 | /* ??? This is currently conditioned on SPARC_ARCH64 because |
61a55e8b DE |
3315 | current_function_args_info is different in each compiler. */ |
3316 | ||
a9e27770 | 3317 | #if SPARC_ARCH64 |
61a55e8b DE |
3318 | |
3319 | rtx | |
3320 | sparc_builtin_saveregs (arglist) | |
3321 | tree arglist; | |
3322 | { | |
3323 | tree fntype = TREE_TYPE (current_function_decl); | |
3324 | /* First unnamed integer register. */ | |
a7acd911 | 3325 | int first_intreg = current_function_args_info.arg_count[(int) SPARC_ARG_INT]; |
61a55e8b DE |
3326 | /* Number of integer registers we need to save. */ |
3327 | int n_intregs = MAX (0, NPARM_REGS (SImode) - first_intreg); | |
3328 | /* First unnamed SFmode float reg (no, you can't pass SFmode floats as | |
a7acd911 DE |
3329 | unnamed arguments, we just number them that way). We must round up to |
3330 | the next double word float reg - that is the first one to save. */ | |
3331 | int first_floatreg = current_function_args_info.arg_count[(int) SPARC_ARG_FLOAT] + 1 & ~1; | |
61a55e8b DE |
3332 | /* Number of SFmode float regs to save. */ |
3333 | int n_floatregs = MAX (0, NPARM_REGS (SFmode) - first_floatreg); | |
3334 | int ptrsize = GET_MODE_SIZE (Pmode); | |
3335 | rtx valist, regbuf, fpregs; | |
a7acd911 | 3336 | int bufsize, adjust, regno; |
61a55e8b DE |
3337 | |
3338 | /* Allocate block of memory for the regs. | |
a7acd911 DE |
3339 | We only allocate as much as we need, but we must ensure quadword float |
3340 | regs are stored with the appropriate alignment. */ | |
61a55e8b DE |
3341 | /* ??? If n_intregs + n_floatregs == 0, should we allocate at least 1 byte? |
3342 | Or can assign_stack_local accept a 0 SIZE argument? */ | |
3343 | ||
a7acd911 DE |
3344 | bufsize = (n_intregs * UNITS_PER_WORD) + (n_floatregs * (UNITS_PER_WORD / 2)); |
3345 | /* Add space in front of the int regs to ensure proper alignment of quadword | |
3346 | fp regs. We must add the space in front because va_start assumes this. */ | |
3347 | if (n_floatregs >= 4) | |
3348 | adjust = ((n_intregs + first_floatreg / 2) % 2) * UNITS_PER_WORD; | |
3349 | else | |
3350 | adjust = 0; | |
3351 | ||
3352 | regbuf = assign_stack_local (BLKmode, bufsize + adjust, | |
3353 | GET_MODE_BITSIZE (TFmode)); | |
3354 | regbuf = gen_rtx (MEM, BLKmode, plus_constant (XEXP (regbuf, 0), adjust)); | |
61a55e8b DE |
3355 | MEM_IN_STRUCT_P (regbuf) = 1; |
3356 | ||
3357 | /* Save int args. | |
3358 | This is optimized to only save the regs that are necessary. Explicitly | |
3359 | named args need not be saved. */ | |
3360 | ||
3361 | if (n_intregs > 0) | |
3362 | move_block_from_reg (BASE_INCOMING_ARG_REG (SImode) + first_intreg, | |
3363 | regbuf, n_intregs, n_intregs * UNITS_PER_WORD); | |
3364 | ||
3365 | /* Save float args. | |
3366 | This is optimized to only save the regs that are necessary. Explicitly | |
3367 | named args need not be saved. | |
3368 | We explicitly build a pointer to the buffer because it halves the insn | |
3369 | count when not optimizing (otherwise the pointer is built for each reg | |
3370 | saved). */ | |
3371 | ||
3372 | fpregs = gen_reg_rtx (Pmode); | |
3373 | emit_move_insn (fpregs, plus_constant (XEXP (regbuf, 0), | |
3374 | n_intregs * UNITS_PER_WORD)); | |
3375 | for (regno = first_floatreg; regno < NPARM_REGS (SFmode); regno += 2) | |
3376 | emit_move_insn (gen_rtx (MEM, DFmode, | |
3377 | plus_constant (fpregs, | |
a7acd911 DE |
3378 | GET_MODE_SIZE (SFmode) |
3379 | * (regno - first_floatreg))), | |
3380 | gen_rtx (REG, DFmode, | |
3381 | BASE_INCOMING_ARG_REG (DFmode) + regno)); | |
61a55e8b DE |
3382 | |
3383 | /* Return the address of the regbuf. */ | |
3384 | ||
3385 | return XEXP (regbuf, 0); | |
3386 | } | |
3387 | ||
a9e27770 | 3388 | #else /* ! SPARC_ARCH64 */ |
3ea1fdd3 JW |
3389 | |
3390 | rtx | |
3391 | sparc_builtin_saveregs (arglist) | |
3392 | tree arglist; | |
3393 | { | |
3394 | tree fntype = TREE_TYPE (current_function_decl); | |
3395 | int stdarg = (TYPE_ARG_TYPES (fntype) != 0 | |
3396 | && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype))) | |
3397 | != void_type_node)); | |
3398 | int first_reg = current_function_args_info; | |
3399 | rtx address; | |
3400 | int regno; | |
3401 | ||
227f7fd9 RS |
3402 | #if 0 /* This code seemed to have no effect except to make |
3403 | varargs not work right when va_list wasn't the first arg. */ | |
3ea1fdd3 JW |
3404 | if (! stdarg) |
3405 | first_reg = 0; | |
227f7fd9 | 3406 | #endif |
3ea1fdd3 | 3407 | |
61a55e8b | 3408 | for (regno = first_reg; regno < NPARM_REGS (SImode); regno++) |
3ea1fdd3 JW |
3409 | emit_move_insn (gen_rtx (MEM, word_mode, |
3410 | gen_rtx (PLUS, Pmode, | |
3411 | frame_pointer_rtx, | |
3412 | GEN_INT (STACK_POINTER_OFFSET | |
3413 | + UNITS_PER_WORD * regno))), | |
3414 | gen_rtx (REG, word_mode, BASE_INCOMING_ARG_REG (word_mode) | |
3415 | + regno)); | |
3416 | ||
3417 | address = gen_rtx (PLUS, Pmode, | |
3418 | frame_pointer_rtx, | |
3419 | GEN_INT (STACK_POINTER_OFFSET | |
3420 | + UNITS_PER_WORD * first_reg)); | |
3421 | ||
3422 | return address; | |
3423 | } | |
61a55e8b | 3424 | |
a9e27770 | 3425 | #endif /* ! SPARC_ARCH64 */ |
ab835497 RK |
3426 | \f |
3427 | /* Return the string to output a conditional branch to LABEL, which is | |
c4ce6853 DE |
3428 | the operand number of the label. OP is the conditional expression. |
3429 | XEXP (OP, 0) is assumed to be a condition code register (integer or | |
3430 | floating point) and its mode specifies what kind of comparison we made. | |
61a55e8b | 3431 | |
ab835497 RK |
3432 | REVERSED is non-zero if we should reverse the sense of the comparison. |
3433 | ||
3434 | ANNUL is non-zero if we should generate an annulling branch. | |
3435 | ||
3436 | NOOP is non-zero if we have to follow this branch by a noop. */ | |
3437 | ||
3438 | char * | |
c4ce6853 DE |
3439 | output_cbranch (op, label, reversed, annul, noop) |
3440 | rtx op; | |
ab835497 RK |
3441 | int label; |
3442 | int reversed, annul, noop; | |
3443 | { | |
3444 | static char string[20]; | |
3445 | enum rtx_code code = GET_CODE (op); | |
c4ce6853 DE |
3446 | rtx cc_reg = XEXP (op, 0); |
3447 | enum machine_mode mode = GET_MODE (cc_reg); | |
61a55e8b DE |
3448 | static char v8_labelno[] = " %lX"; |
3449 | static char v9_icc_labelno[] = " %%icc,%lX"; | |
3450 | static char v9_xcc_labelno[] = " %%xcc,%lX"; | |
3451 | static char v9_fcc_labelno[] = " %%fccX,%lY"; | |
3452 | char *labelno; | |
3453 | int labeloff; | |
3454 | ||
3455 | /* ??? !v9: FP branches cannot be preceded by another floating point insn. | |
ab835497 RK |
3456 | Because there is currently no concept of pre-delay slots, we can fix |
3457 | this only by always emitting a nop before a floating point branch. */ | |
3458 | ||
61a55e8b | 3459 | if ((mode == CCFPmode || mode == CCFPEmode) && ! TARGET_V9) |
ab835497 | 3460 | strcpy (string, "nop\n\t"); |
61a55e8b DE |
3461 | else |
3462 | string[0] = '\0'; | |
ab835497 RK |
3463 | |
3464 | /* If not floating-point or if EQ or NE, we can just reverse the code. */ | |
4d449554 JW |
3465 | if (reversed |
3466 | && ((mode != CCFPmode && mode != CCFPEmode) || code == EQ || code == NE)) | |
ab835497 RK |
3467 | code = reverse_condition (code), reversed = 0; |
3468 | ||
3469 | /* Start by writing the branch condition. */ | |
3470 | switch (code) | |
3471 | { | |
3472 | case NE: | |
4d449554 | 3473 | if (mode == CCFPmode || mode == CCFPEmode) |
ab835497 RK |
3474 | strcat (string, "fbne"); |
3475 | else | |
3476 | strcpy (string, "bne"); | |
3477 | break; | |
3478 | ||
3479 | case EQ: | |
4d449554 | 3480 | if (mode == CCFPmode || mode == CCFPEmode) |
ab835497 RK |
3481 | strcat (string, "fbe"); |
3482 | else | |
3483 | strcpy (string, "be"); | |
3484 | break; | |
3485 | ||
3486 | case GE: | |
4d449554 | 3487 | if (mode == CCFPmode || mode == CCFPEmode) |
ab835497 RK |
3488 | { |
3489 | if (reversed) | |
3490 | strcat (string, "fbul"); | |
3491 | else | |
3492 | strcat (string, "fbge"); | |
3493 | } | |
3494 | else if (mode == CC_NOOVmode) | |
3495 | strcpy (string, "bpos"); | |
3496 | else | |
3497 | strcpy (string, "bge"); | |
3498 | break; | |
3499 | ||
3500 | case GT: | |
4d449554 | 3501 | if (mode == CCFPmode || mode == CCFPEmode) |
ab835497 RK |
3502 | { |
3503 | if (reversed) | |
3504 | strcat (string, "fbule"); | |
3505 | else | |
3506 | strcat (string, "fbg"); | |
3507 | } | |
3508 | else | |
3509 | strcpy (string, "bg"); | |
3510 | break; | |
3511 | ||
3512 | case LE: | |
4d449554 | 3513 | if (mode == CCFPmode || mode == CCFPEmode) |
ab835497 RK |
3514 | { |
3515 | if (reversed) | |
3516 | strcat (string, "fbug"); | |
3517 | else | |
3518 | strcat (string, "fble"); | |
3519 | } | |
3520 | else | |
3521 | strcpy (string, "ble"); | |
3522 | break; | |
3523 | ||
3524 | case LT: | |
4d449554 | 3525 | if (mode == CCFPmode || mode == CCFPEmode) |
ab835497 RK |
3526 | { |
3527 | if (reversed) | |
3528 | strcat (string, "fbuge"); | |
3529 | else | |
3530 | strcat (string, "fbl"); | |
3531 | } | |
3532 | else if (mode == CC_NOOVmode) | |
3533 | strcpy (string, "bneg"); | |
3534 | else | |
3535 | strcpy (string, "bl"); | |
3536 | break; | |
3537 | ||
3538 | case GEU: | |
3539 | strcpy (string, "bgeu"); | |
3540 | break; | |
3541 | ||
3542 | case GTU: | |
3543 | strcpy (string, "bgu"); | |
3544 | break; | |
3545 | ||
3546 | case LEU: | |
3547 | strcpy (string, "bleu"); | |
3548 | break; | |
3549 | ||
3550 | case LTU: | |
3551 | strcpy (string, "blu"); | |
3552 | break; | |
3553 | } | |
3554 | ||
3555 | /* Now add the annulling, the label, and a possible noop. */ | |
3556 | if (annul) | |
3557 | strcat (string, ",a"); | |
3558 | ||
61a55e8b DE |
3559 | /* ??? If v9, optional prediction bit ",pt" or ",pf" goes here. */ |
3560 | ||
3561 | if (! TARGET_V9) | |
3562 | { | |
3563 | labeloff = 3; | |
3564 | labelno = v8_labelno; | |
3565 | } | |
3566 | else | |
3567 | { | |
3568 | labeloff = 9; | |
3569 | if (mode == CCFPmode || mode == CCFPEmode) | |
3570 | { | |
3571 | labeloff = 10; | |
3572 | labelno = v9_fcc_labelno; | |
3573 | /* Set the char indicating the number of the fcc reg to use. */ | |
c4ce6853 | 3574 | labelno[6] = REGNO (cc_reg) - SPARC_FIRST_V9_FCC_REG + '0'; |
61a55e8b DE |
3575 | } |
3576 | else if (mode == CCXmode || mode == CCX_NOOVmode) | |
3577 | labelno = v9_xcc_labelno; | |
3578 | else | |
3579 | labelno = v9_icc_labelno; | |
3580 | } | |
3581 | /* Set the char indicating the number of the operand containing the | |
3582 | label_ref. */ | |
3583 | labelno[labeloff] = label + '0'; | |
3584 | strcat (string, labelno); | |
3585 | ||
3586 | if (noop) | |
3587 | strcat (string, "\n\tnop"); | |
3588 | ||
3589 | return string; | |
3590 | } | |
3591 | ||
3592 | /* Return the string to output a conditional branch to LABEL, testing | |
3593 | register REG. LABEL is the operand number of the label; REG is the | |
3594 | operand number of the reg. OP is the conditional expression. The mode | |
3595 | of REG says what kind of comparison we made. | |
3596 | ||
3597 | REVERSED is non-zero if we should reverse the sense of the comparison. | |
3598 | ||
3599 | ANNUL is non-zero if we should generate an annulling branch. | |
3600 | ||
3601 | NOOP is non-zero if we have to follow this branch by a noop. */ | |
3602 | ||
3603 | char * | |
3604 | output_v9branch (op, reg, label, reversed, annul, noop) | |
3605 | rtx op; | |
3606 | int reg, label; | |
3607 | int reversed, annul, noop; | |
3608 | { | |
3609 | static char string[20]; | |
3610 | enum rtx_code code = GET_CODE (op); | |
3611 | enum machine_mode mode = GET_MODE (XEXP (op, 0)); | |
3612 | static char labelno[] = " %X,%lX"; | |
3613 | ||
3614 | /* If not floating-point or if EQ or NE, we can just reverse the code. */ | |
3615 | if (reversed) | |
3616 | code = reverse_condition (code), reversed = 0; | |
3617 | ||
3618 | /* Only 64 bit versions of these instructions exist. */ | |
3619 | if (mode != DImode) | |
3620 | abort (); | |
3621 | ||
3622 | /* Start by writing the branch condition. */ | |
3623 | ||
3624 | switch (code) | |
3625 | { | |
3626 | case NE: | |
3627 | strcpy (string, "brnz"); | |
3628 | break; | |
3629 | ||
3630 | case EQ: | |
3631 | strcpy (string, "brz"); | |
3632 | break; | |
3633 | ||
3634 | case GE: | |
3635 | strcpy (string, "brgez"); | |
3636 | break; | |
3637 | ||
3638 | case LT: | |
3639 | strcpy (string, "brlz"); | |
3640 | break; | |
3641 | ||
3642 | case LE: | |
3643 | strcpy (string, "brlez"); | |
3644 | break; | |
3645 | ||
3646 | case GT: | |
3647 | strcpy (string, "brgz"); | |
3648 | break; | |
3649 | ||
3650 | default: | |
3651 | abort (); | |
3652 | } | |
3653 | ||
3654 | /* Now add the annulling, reg, label, and nop. */ | |
3655 | if (annul) | |
3656 | strcat (string, ",a"); | |
3657 | ||
3658 | /* ??? Optional prediction bit ",pt" or ",pf" goes here. */ | |
3659 | ||
3660 | labelno[2] = reg + '0'; | |
3661 | labelno[6] = label + '0'; | |
ab835497 RK |
3662 | strcat (string, labelno); |
3663 | ||
3664 | if (noop) | |
3665 | strcat (string, "\n\tnop"); | |
3666 | ||
3667 | return string; | |
3668 | } | |
3669 | ||
795068a4 JW |
3670 | /* Output assembler code to return from a function. */ |
3671 | ||
61a55e8b DE |
3672 | /* ??? v9: Update to use the new `return' instruction. Also, add patterns to |
3673 | md file for the `return' instruction. */ | |
3674 | ||
ab835497 RK |
3675 | char * |
3676 | output_return (operands) | |
3677 | rtx *operands; | |
3678 | { | |
3679 | if (leaf_label) | |
3680 | { | |
3681 | operands[0] = leaf_label; | |
3682 | return "b,a %l0"; | |
3683 | } | |
3684 | else if (leaf_function) | |
3685 | { | |
915f619f JW |
3686 | /* If we didn't allocate a frame pointer for the current function, |
3687 | the stack pointer might have been adjusted. Output code to | |
3688 | restore it now. */ | |
3689 | ||
ab835497 | 3690 | operands[0] = gen_rtx (CONST_INT, VOIDmode, actual_fsize); |
915f619f JW |
3691 | |
3692 | /* Use sub of negated value in first two cases instead of add to | |
3693 | allow actual_fsize == 4096. */ | |
3694 | ||
3695 | if (actual_fsize <= 4096) | |
ab835497 | 3696 | { |
61a55e8b | 3697 | if (SKIP_CALLERS_UNIMP_P) |
915f619f | 3698 | return "jmp %%o7+12\n\tsub %%sp,-%0,%%sp"; |
ab835497 | 3699 | else |
915f619f | 3700 | return "retl\n\tsub %%sp,-%0,%%sp"; |
ab835497 | 3701 | } |
915f619f | 3702 | else if (actual_fsize <= 8192) |
ab835497 | 3703 | { |
915f619f | 3704 | operands[0] = gen_rtx (CONST_INT, VOIDmode, actual_fsize - 4096); |
61a55e8b | 3705 | if (SKIP_CALLERS_UNIMP_P) |
915f619f JW |
3706 | return "sub %%sp,-4096,%%sp\n\tjmp %%o7+12\n\tsub %%sp,-%0,%%sp"; |
3707 | else | |
3708 | return "sub %%sp,-4096,%%sp\n\tretl\n\tsub %%sp,-%0,%%sp"; | |
3709 | } | |
61a55e8b | 3710 | else if (SKIP_CALLERS_UNIMP_P) |
915f619f JW |
3711 | { |
3712 | if ((actual_fsize & 0x3ff) != 0) | |
ab835497 RK |
3713 | return "sethi %%hi(%a0),%%g1\n\tor %%g1,%%lo(%a0),%%g1\n\tjmp %%o7+12\n\tadd %%sp,%%g1,%%sp"; |
3714 | else | |
915f619f JW |
3715 | return "sethi %%hi(%a0),%%g1\n\tjmp %%o7+12\n\tadd %%sp,%%g1,%%sp"; |
3716 | } | |
3717 | else | |
3718 | { | |
3719 | if ((actual_fsize & 0x3ff) != 0) | |
ab835497 | 3720 | return "sethi %%hi(%a0),%%g1\n\tor %%g1,%%lo(%a0),%%g1\n\tretl\n\tadd %%sp,%%g1,%%sp"; |
915f619f JW |
3721 | else |
3722 | return "sethi %%hi(%a0),%%g1\n\tretl\n\tadd %%sp,%%g1,%%sp"; | |
ab835497 RK |
3723 | } |
3724 | } | |
3725 | else | |
3726 | { | |
61a55e8b | 3727 | if (SKIP_CALLERS_UNIMP_P) |
ab835497 RK |
3728 | return "jmp %%i7+12\n\trestore"; |
3729 | else | |
3730 | return "ret\n\trestore"; | |
3731 | } | |
3732 | } | |
ab835497 RK |
3733 | \f |
3734 | /* Leaf functions and non-leaf functions have different needs. */ | |
3735 | ||
3736 | static int | |
3737 | reg_leaf_alloc_order[] = REG_LEAF_ALLOC_ORDER; | |
3738 | ||
3739 | static int | |
3740 | reg_nonleaf_alloc_order[] = REG_ALLOC_ORDER; | |
3741 | ||
3742 | static int *reg_alloc_orders[] = { | |
3743 | reg_leaf_alloc_order, | |
3744 | reg_nonleaf_alloc_order}; | |
3745 | ||
3746 | void | |
3747 | order_regs_for_local_alloc () | |
3748 | { | |
3749 | static int last_order_nonleaf = 1; | |
3750 | ||
3751 | if (regs_ever_live[15] != last_order_nonleaf) | |
3752 | { | |
3753 | last_order_nonleaf = !last_order_nonleaf; | |
d2889939 RK |
3754 | bcopy ((char *) reg_alloc_orders[last_order_nonleaf], |
3755 | (char *) reg_alloc_order, FIRST_PSEUDO_REGISTER * sizeof (int)); | |
ab835497 RK |
3756 | } |
3757 | } | |
3758 | \f | |
35016322 JW |
3759 | /* Return 1 if REGNO (reg1) is even and REGNO (reg1) == REGNO (reg2) - 1. |
3760 | This makes them candidates for using ldd and std insns. | |
3761 | ||
3762 | Note reg1 and reg2 *must* be hard registers. To be sure we will | |
3763 | abort if we are passed pseudo registers. */ | |
3764 | ||
3765 | int | |
7c56249d | 3766 | registers_ok_for_ldd_peep (reg1, reg2) |
35016322 JW |
3767 | rtx reg1, reg2; |
3768 | { | |
35016322 JW |
3769 | /* We might have been passed a SUBREG. */ |
3770 | if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG) | |
3771 | return 0; | |
3772 | ||
35016322 JW |
3773 | if (REGNO (reg1) % 2 != 0) |
3774 | return 0; | |
3775 | ||
3776 | return (REGNO (reg1) == REGNO (reg2) - 1); | |
35016322 JW |
3777 | } |
3778 | ||
3779 | /* Return 1 if addr1 and addr2 are suitable for use in an ldd or | |
3780 | std insn. | |
3781 | ||
3782 | This can only happen when addr1 and addr2 are consecutive memory | |
3783 | locations (addr1 + 4 == addr2). addr1 must also be aligned on a | |
3784 | 64 bit boundary (addr1 % 8 == 0). | |
3785 | ||
3786 | We know %sp and %fp are kept aligned on a 64 bit boundary. Other | |
3787 | registers are assumed to *never* be properly aligned and are | |
3788 | rejected. | |
3789 | ||
3790 | Knowing %sp and %fp are kept aligned on a 64 bit boundary, we | |
3791 | need only check that the offset for addr1 % 8 == 0. */ | |
3792 | ||
3793 | int | |
7c56249d | 3794 | addrs_ok_for_ldd_peep (addr1, addr2) |
35016322 JW |
3795 | rtx addr1, addr2; |
3796 | { | |
3797 | int reg1, offset1; | |
3798 | ||
3799 | /* Extract a register number and offset (if used) from the first addr. */ | |
3800 | if (GET_CODE (addr1) == PLUS) | |
3801 | { | |
3802 | /* If not a REG, return zero. */ | |
3803 | if (GET_CODE (XEXP (addr1, 0)) != REG) | |
3804 | return 0; | |
3805 | else | |
3806 | { | |
3807 | reg1 = REGNO (XEXP (addr1, 0)); | |
3808 | /* The offset must be constant! */ | |
3809 | if (GET_CODE (XEXP (addr1, 1)) != CONST_INT) | |
3810 | return 0; | |
3811 | offset1 = INTVAL (XEXP (addr1, 1)); | |
3812 | } | |
3813 | } | |
3814 | else if (GET_CODE (addr1) != REG) | |
3815 | return 0; | |
3816 | else | |
3817 | { | |
3818 | reg1 = REGNO (addr1); | |
3819 | /* This was a simple (mem (reg)) expression. Offset is 0. */ | |
3820 | offset1 = 0; | |
3821 | } | |
3822 | ||
3823 | /* Make sure the second address is a (mem (plus (reg) (const_int). */ | |
3824 | if (GET_CODE (addr2) != PLUS) | |
3825 | return 0; | |
3826 | ||
3827 | if (GET_CODE (XEXP (addr2, 0)) != REG | |
3828 | || GET_CODE (XEXP (addr2, 1)) != CONST_INT) | |
3829 | return 0; | |
3830 | ||
3831 | /* Only %fp and %sp are allowed. Additionally both addresses must | |
3832 | use the same register. */ | |
3833 | if (reg1 != FRAME_POINTER_REGNUM && reg1 != STACK_POINTER_REGNUM) | |
3834 | return 0; | |
3835 | ||
3836 | if (reg1 != REGNO (XEXP (addr2, 0))) | |
3837 | return 0; | |
3838 | ||
2296cba3 | 3839 | /* The first offset must be evenly divisible by 8 to ensure the |
35016322 JW |
3840 | address is 64 bit aligned. */ |
3841 | if (offset1 % 8 != 0) | |
3842 | return 0; | |
3843 | ||
3844 | /* The offset for the second addr must be 4 more than the first addr. */ | |
3845 | if (INTVAL (XEXP (addr2, 1)) != offset1 + 4) | |
3846 | return 0; | |
3847 | ||
3848 | /* All the tests passed. addr1 and addr2 are valid for ldd and std | |
3849 | instructions. */ | |
3850 | return 1; | |
3851 | } | |
7c56249d JL |
3852 | |
3853 | /* Return 1 if reg is a pseudo, or is the first register in | |
3854 | a hard register pair. This makes it a candidate for use in | |
3855 | ldd and std insns. */ | |
3856 | ||
3857 | int | |
3858 | register_ok_for_ldd (reg) | |
3859 | rtx reg; | |
3860 | { | |
7c56249d JL |
3861 | /* We might have been passed a SUBREG. */ |
3862 | if (GET_CODE (reg) != REG) | |
3863 | return 0; | |
3864 | ||
3865 | if (REGNO (reg) < FIRST_PSEUDO_REGISTER) | |
3866 | return (REGNO (reg) % 2 == 0); | |
3867 | else | |
3868 | return 1; | |
7c56249d | 3869 | } |
ab835497 | 3870 | \f |
ab835497 RK |
3871 | /* Print operand X (an rtx) in assembler syntax to file FILE. |
3872 | CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. | |
3873 | For `%' followed by punctuation, CODE is the punctuation and X is null. */ | |
3874 | ||
3875 | void | |
3876 | print_operand (file, x, code) | |
3877 | FILE *file; | |
3878 | rtx x; | |
3879 | int code; | |
3880 | { | |
3881 | switch (code) | |
3882 | { | |
3883 | case '#': | |
3884 | /* Output a 'nop' if there's nothing for the delay slot. */ | |
3885 | if (dbr_sequence_length () == 0) | |
3886 | fputs ("\n\tnop", file); | |
3887 | return; | |
3888 | case '*': | |
c6ce0969 JW |
3889 | /* Output an annul flag if there's nothing for the delay slot and we |
3890 | are optimizing. This is always used with '(' below. */ | |
3891 | /* Sun OS 4.1.1 dbx can't handle an annulled unconditional branch; | |
3892 | this is a dbx bug. So, we only do this when optimizing. */ | |
3893 | if (dbr_sequence_length () == 0 && optimize) | |
3894 | fputs (",a", file); | |
3895 | return; | |
3896 | case '(': | |
3897 | /* Output a 'nop' if there's nothing for the delay slot and we are | |
3898 | not optimizing. This is always used with '*' above. */ | |
3899 | if (dbr_sequence_length () == 0 && ! optimize) | |
3900 | fputs ("\n\tnop", file); | |
ab835497 | 3901 | return; |
61a55e8b DE |
3902 | case '_': |
3903 | /* Output the Medium/Anywhere code model base register. */ | |
3904 | fputs (MEDANY_BASE_REG, file); | |
3905 | return; | |
3906 | case '@': | |
3907 | /* Print out what we are using as the frame pointer. This might | |
3908 | be %fp, or might be %sp+offset. */ | |
3909 | /* ??? What if offset is too big? Perhaps the caller knows it isn't? */ | |
3910 | fprintf (file, "%s+%d", frame_base_name, frame_base_offset); | |
3911 | return; | |
ab835497 RK |
3912 | case 'Y': |
3913 | /* Adjust the operand to take into account a RESTORE operation. */ | |
3914 | if (GET_CODE (x) != REG) | |
b3b1e8bd JW |
3915 | output_operand_lossage ("Invalid %%Y operand"); |
3916 | else if (REGNO (x) < 8) | |
ab835497 RK |
3917 | fputs (reg_names[REGNO (x)], file); |
3918 | else if (REGNO (x) >= 24 && REGNO (x) < 32) | |
3919 | fputs (reg_names[REGNO (x)-16], file); | |
3920 | else | |
b3b1e8bd | 3921 | output_operand_lossage ("Invalid %%Y operand"); |
ab835497 | 3922 | return; |
ab835497 | 3923 | case 'R': |
795068a4 | 3924 | /* Print out the second register name of a register pair or quad. |
ab835497 RK |
3925 | I.e., R (%o0) => %o1. */ |
3926 | fputs (reg_names[REGNO (x)+1], file); | |
3927 | return; | |
795068a4 JW |
3928 | case 'S': |
3929 | /* Print out the third register name of a register quad. | |
3930 | I.e., S (%o0) => %o2. */ | |
3931 | fputs (reg_names[REGNO (x)+2], file); | |
3932 | return; | |
3933 | case 'T': | |
3934 | /* Print out the fourth register name of a register quad. | |
3935 | I.e., T (%o0) => %o3. */ | |
3936 | fputs (reg_names[REGNO (x)+3], file); | |
3937 | return; | |
304b7a23 DE |
3938 | case 'x': |
3939 | /* Print a condition code register. */ | |
3940 | if (REGNO (x) == SPARC_ICC_REG) | |
3941 | { | |
3942 | /* We don't handle CC[X]_NOOVmode because they're not supposed | |
3943 | to occur here. */ | |
3944 | if (GET_MODE (x) == CCmode) | |
3945 | fputs ("%icc", file); | |
3946 | else if (GET_MODE (x) == CCXmode) | |
3947 | fputs ("%xcc", file); | |
3948 | else | |
3949 | abort (); | |
3950 | } | |
3951 | else | |
3952 | /* %fccN register */ | |
3953 | fputs (reg_names[REGNO (x)], file); | |
3954 | return; | |
ab835497 RK |
3955 | case 'm': |
3956 | /* Print the operand's address only. */ | |
3957 | output_address (XEXP (x, 0)); | |
3958 | return; | |
3959 | case 'r': | |
3960 | /* In this case we need a register. Use %g0 if the | |
77a02b01 | 3961 | operand is const0_rtx. */ |
76052e74 RS |
3962 | if (x == const0_rtx |
3963 | || (GET_MODE (x) != VOIDmode && x == CONST0_RTX (GET_MODE (x)))) | |
ab835497 RK |
3964 | { |
3965 | fputs ("%g0", file); | |
3966 | return; | |
3967 | } | |
3968 | else | |
3969 | break; | |
3970 | ||
61a55e8b | 3971 | case 'A': |
ab835497 RK |
3972 | switch (GET_CODE (x)) |
3973 | { | |
3974 | case IOR: fputs ("or", file); break; | |
3975 | case AND: fputs ("and", file); break; | |
3976 | case XOR: fputs ("xor", file); break; | |
b3b1e8bd | 3977 | default: output_operand_lossage ("Invalid %%A operand"); |
ab835497 RK |
3978 | } |
3979 | return; | |
3980 | ||
3981 | case 'B': | |
3982 | switch (GET_CODE (x)) | |
3983 | { | |
3984 | case IOR: fputs ("orn", file); break; | |
3985 | case AND: fputs ("andn", file); break; | |
3986 | case XOR: fputs ("xnor", file); break; | |
b3b1e8bd | 3987 | default: output_operand_lossage ("Invalid %%B operand"); |
ab835497 RK |
3988 | } |
3989 | return; | |
3990 | ||
304b7a23 DE |
3991 | /* These are used by the conditional move instructions. */ |
3992 | case 'c' : | |
61a55e8b | 3993 | case 'C': |
304b7a23 DE |
3994 | { |
3995 | enum rtx_code rc = (code == 'c' | |
3996 | ? reverse_condition (GET_CODE (x)) | |
3997 | : GET_CODE (x)); | |
3998 | switch (rc) | |
3999 | { | |
4000 | case NE: fputs ("ne", file); break; | |
4001 | case EQ: fputs ("e", file); break; | |
4002 | case GE: fputs ("ge", file); break; | |
4003 | case GT: fputs ("g", file); break; | |
4004 | case LE: fputs ("le", file); break; | |
4005 | case LT: fputs ("l", file); break; | |
4006 | case GEU: fputs ("geu", file); break; | |
4007 | case GTU: fputs ("gu", file); break; | |
4008 | case LEU: fputs ("leu", file); break; | |
4009 | case LTU: fputs ("lu", file); break; | |
4010 | default: output_operand_lossage (code == 'c' | |
4011 | ? "Invalid %%c operand" | |
4012 | : "Invalid %%C operand"); | |
4013 | } | |
4014 | return; | |
4015 | } | |
4016 | ||
4017 | /* These are used by the movr instruction pattern. */ | |
4018 | case 'd': | |
61a55e8b | 4019 | case 'D': |
304b7a23 DE |
4020 | { |
4021 | enum rtx_code rc = (code == 'd' | |
4022 | ? reverse_condition (GET_CODE (x)) | |
4023 | : GET_CODE (x)); | |
4024 | switch (rc) | |
4025 | { | |
4026 | case NE: fputs ("ne", file); break; | |
4027 | case EQ: fputs ("e", file); break; | |
4028 | case GE: fputs ("gez", file); break; | |
4029 | case LT: fputs ("lz", file); break; | |
4030 | case LE: fputs ("lez", file); break; | |
4031 | case GT: fputs ("gz", file); break; | |
4032 | default: output_operand_lossage (code == 'd' | |
4033 | ? "Invalid %%d operand" | |
4034 | : "Invalid %%D operand"); | |
4035 | } | |
4036 | return; | |
4037 | } | |
61a55e8b | 4038 | |
ab835497 RK |
4039 | case 'b': |
4040 | { | |
4041 | /* Print a sign-extended character. */ | |
4042 | int i = INTVAL (x) & 0xff; | |
4043 | if (i & 0x80) | |
4044 | i |= 0xffffff00; | |
4045 | fprintf (file, "%d", i); | |
4046 | return; | |
4047 | } | |
4048 | ||
d2889939 RK |
4049 | case 'f': |
4050 | /* Operand must be a MEM; write its address. */ | |
4051 | if (GET_CODE (x) != MEM) | |
4052 | output_operand_lossage ("Invalid %%f operand"); | |
4053 | output_address (XEXP (x, 0)); | |
4054 | return; | |
4055 | ||
ab835497 RK |
4056 | case 0: |
4057 | /* Do nothing special. */ | |
4058 | break; | |
4059 | ||
4060 | default: | |
4061 | /* Undocumented flag. */ | |
415f583e | 4062 | output_operand_lossage ("invalid operand output code"); |
ab835497 RK |
4063 | } |
4064 | ||
4065 | if (GET_CODE (x) == REG) | |
4066 | fputs (reg_names[REGNO (x)], file); | |
4067 | else if (GET_CODE (x) == MEM) | |
4068 | { | |
4069 | fputc ('[', file); | |
ab835497 | 4070 | /* Poor Sun assembler doesn't understand absolute addressing. */ |
c4ce6853 DE |
4071 | if (CONSTANT_P (XEXP (x, 0)) |
4072 | && ! TARGET_LIVE_G0) | |
ab835497 RK |
4073 | fputs ("%g0+", file); |
4074 | output_address (XEXP (x, 0)); | |
4075 | fputc (']', file); | |
4076 | } | |
4077 | else if (GET_CODE (x) == HIGH) | |
4078 | { | |
4079 | fputs ("%hi(", file); | |
4080 | output_addr_const (file, XEXP (x, 0)); | |
4081 | fputc (')', file); | |
4082 | } | |
4083 | else if (GET_CODE (x) == LO_SUM) | |
4084 | { | |
4085 | print_operand (file, XEXP (x, 0), 0); | |
4086 | fputs ("+%lo(", file); | |
4087 | output_addr_const (file, XEXP (x, 1)); | |
4088 | fputc (')', file); | |
4089 | } | |
e601abce JW |
4090 | else if (GET_CODE (x) == CONST_DOUBLE |
4091 | && (GET_MODE (x) == VOIDmode | |
4092 | || GET_MODE_CLASS (GET_MODE (x)) == MODE_INT)) | |
ab835497 RK |
4093 | { |
4094 | if (CONST_DOUBLE_HIGH (x) == 0) | |
4095 | fprintf (file, "%u", CONST_DOUBLE_LOW (x)); | |
4096 | else if (CONST_DOUBLE_HIGH (x) == -1 | |
4097 | && CONST_DOUBLE_LOW (x) < 0) | |
4098 | fprintf (file, "%d", CONST_DOUBLE_LOW (x)); | |
4099 | else | |
e601abce | 4100 | output_operand_lossage ("long long constant not a valid immediate operand"); |
ab835497 | 4101 | } |
e601abce JW |
4102 | else if (GET_CODE (x) == CONST_DOUBLE) |
4103 | output_operand_lossage ("floating point constant not a valid immediate operand"); | |
ab835497 RK |
4104 | else { output_addr_const (file, x); } |
4105 | } | |
4106 | \f | |
4107 | /* This function outputs assembler code for VALUE to FILE, where VALUE is | |
4108 | a 64 bit (DImode) value. */ | |
4109 | ||
4110 | /* ??? If there is a 64 bit counterpart to .word that the assembler | |
4111 | understands, then using that would simply this code greatly. */ | |
61a55e8b DE |
4112 | /* ??? We only output .xword's for symbols and only then in environments |
4113 | where the assembler can handle them. */ | |
ab835497 RK |
4114 | |
4115 | void | |
4116 | output_double_int (file, value) | |
4117 | FILE *file; | |
4118 | rtx value; | |
4119 | { | |
4120 | if (GET_CODE (value) == CONST_INT) | |
4121 | { | |
4122 | if (INTVAL (value) < 0) | |
4123 | ASM_OUTPUT_INT (file, constm1_rtx); | |
4124 | else | |
4125 | ASM_OUTPUT_INT (file, const0_rtx); | |
4126 | ASM_OUTPUT_INT (file, value); | |
4127 | } | |
4128 | else if (GET_CODE (value) == CONST_DOUBLE) | |
4129 | { | |
4130 | ASM_OUTPUT_INT (file, gen_rtx (CONST_INT, VOIDmode, | |
4131 | CONST_DOUBLE_HIGH (value))); | |
4132 | ASM_OUTPUT_INT (file, gen_rtx (CONST_INT, VOIDmode, | |
4133 | CONST_DOUBLE_LOW (value))); | |
4134 | } | |
4135 | else if (GET_CODE (value) == SYMBOL_REF | |
4136 | || GET_CODE (value) == CONST | |
61a55e8b | 4137 | || GET_CODE (value) == PLUS |
a9e27770 | 4138 | || (TARGET_ARCH64 && |
61a55e8b | 4139 | (GET_CODE (value) == LABEL_REF |
9fa9626b | 4140 | || GET_CODE (value) == CODE_LABEL |
61a55e8b | 4141 | || GET_CODE (value) == MINUS))) |
ab835497 | 4142 | { |
a9e27770 | 4143 | if (!TARGET_V9 || TARGET_MEDLOW) |
61a55e8b DE |
4144 | { |
4145 | ASM_OUTPUT_INT (file, const0_rtx); | |
4146 | ASM_OUTPUT_INT (file, value); | |
4147 | } | |
4148 | else | |
4149 | { | |
4150 | fprintf (file, "\t%s\t", ASM_LONGLONG); | |
4151 | output_addr_const (file, value); | |
4152 | fprintf (file, "\n"); | |
4153 | } | |
ab835497 RK |
4154 | } |
4155 | else | |
4156 | abort (); | |
4157 | } | |
210aa14a | 4158 | \f |
b0468b84 RK |
4159 | /* Return the value of a code used in the .proc pseudo-op that says |
4160 | what kind of result this function returns. For non-C types, we pick | |
4161 | the closest C type. */ | |
4162 | ||
77a02b01 JW |
4163 | #ifndef CHAR_TYPE_SIZE |
4164 | #define CHAR_TYPE_SIZE BITS_PER_UNIT | |
4165 | #endif | |
4166 | ||
4167 | #ifndef SHORT_TYPE_SIZE | |
4168 | #define SHORT_TYPE_SIZE (BITS_PER_UNIT * 2) | |
4169 | #endif | |
4170 | ||
4171 | #ifndef INT_TYPE_SIZE | |
4172 | #define INT_TYPE_SIZE BITS_PER_WORD | |
4173 | #endif | |
4174 | ||
4175 | #ifndef LONG_TYPE_SIZE | |
4176 | #define LONG_TYPE_SIZE BITS_PER_WORD | |
4177 | #endif | |
4178 | ||
4179 | #ifndef LONG_LONG_TYPE_SIZE | |
4180 | #define LONG_LONG_TYPE_SIZE (BITS_PER_WORD * 2) | |
4181 | #endif | |
4182 | ||
4183 | #ifndef FLOAT_TYPE_SIZE | |
4184 | #define FLOAT_TYPE_SIZE BITS_PER_WORD | |
4185 | #endif | |
4186 | ||
4187 | #ifndef DOUBLE_TYPE_SIZE | |
4188 | #define DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2) | |
4189 | #endif | |
4190 | ||
4191 | #ifndef LONG_DOUBLE_TYPE_SIZE | |
4192 | #define LONG_DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2) | |
4193 | #endif | |
210aa14a RS |
4194 | |
4195 | unsigned long | |
4196 | sparc_type_code (type) | |
4197 | register tree type; | |
4198 | { | |
4199 | register unsigned long qualifiers = 0; | |
4200 | register unsigned shift = 6; | |
4201 | ||
abc95ed3 | 4202 | /* Only the first 30 bits of the qualifier are valid. We must refrain from |
aee2c3c5 JW |
4203 | setting more, since some assemblers will give an error for this. Also, |
4204 | we must be careful to avoid shifts of 32 bits or more to avoid getting | |
4205 | unpredictable results. */ | |
4206 | ||
210aa14a RS |
4207 | for (;;) |
4208 | { | |
4209 | switch (TREE_CODE (type)) | |
4210 | { | |
4211 | case ERROR_MARK: | |
4212 | return qualifiers; | |
4213 | ||
4214 | case ARRAY_TYPE: | |
aee2c3c5 JW |
4215 | if (shift < 30) |
4216 | qualifiers |= (3 << shift); | |
210aa14a RS |
4217 | shift += 2; |
4218 | type = TREE_TYPE (type); | |
4219 | break; | |
4220 | ||
4221 | case FUNCTION_TYPE: | |
4222 | case METHOD_TYPE: | |
aee2c3c5 JW |
4223 | if (shift < 30) |
4224 | qualifiers |= (2 << shift); | |
210aa14a RS |
4225 | shift += 2; |
4226 | type = TREE_TYPE (type); | |
4227 | break; | |
4228 | ||
4229 | case POINTER_TYPE: | |
4230 | case REFERENCE_TYPE: | |
4231 | case OFFSET_TYPE: | |
aee2c3c5 JW |
4232 | if (shift < 30) |
4233 | qualifiers |= (1 << shift); | |
210aa14a RS |
4234 | shift += 2; |
4235 | type = TREE_TYPE (type); | |
4236 | break; | |
ab835497 | 4237 | |
210aa14a RS |
4238 | case RECORD_TYPE: |
4239 | return (qualifiers | 8); | |
4240 | ||
4241 | case UNION_TYPE: | |
b0468b84 | 4242 | case QUAL_UNION_TYPE: |
210aa14a RS |
4243 | return (qualifiers | 9); |
4244 | ||
4245 | case ENUMERAL_TYPE: | |
4246 | return (qualifiers | 10); | |
4247 | ||
4248 | case VOID_TYPE: | |
4249 | return (qualifiers | 16); | |
4250 | ||
4251 | case INTEGER_TYPE: | |
654209e6 JW |
4252 | /* If this is a range type, consider it to be the underlying |
4253 | type. */ | |
4254 | if (TREE_TYPE (type) != 0) | |
4255 | { | |
4256 | type = TREE_TYPE (type); | |
4257 | break; | |
4258 | } | |
4259 | ||
77a02b01 | 4260 | /* Carefully distinguish all the standard types of C, |
b0468b84 RK |
4261 | without messing up if the language is not C. We do this by |
4262 | testing TYPE_PRECISION and TREE_UNSIGNED. The old code used to | |
4263 | look at both the names and the above fields, but that's redundant. | |
4264 | Any type whose size is between two C types will be considered | |
4265 | to be the wider of the two types. Also, we do not have a | |
4266 | special code to use for "long long", so anything wider than | |
4267 | long is treated the same. Note that we can't distinguish | |
4268 | between "int" and "long" in this code if they are the same | |
4269 | size, but that's fine, since neither can the assembler. */ | |
4270 | ||
4271 | if (TYPE_PRECISION (type) <= CHAR_TYPE_SIZE) | |
4272 | return (qualifiers | (TREE_UNSIGNED (type) ? 12 : 2)); | |
77a02b01 | 4273 | |
b0468b84 RK |
4274 | else if (TYPE_PRECISION (type) <= SHORT_TYPE_SIZE) |
4275 | return (qualifiers | (TREE_UNSIGNED (type) ? 13 : 3)); | |
77a02b01 | 4276 | |
b0468b84 | 4277 | else if (TYPE_PRECISION (type) <= INT_TYPE_SIZE) |
77a02b01 JW |
4278 | return (qualifiers | (TREE_UNSIGNED (type) ? 14 : 4)); |
4279 | ||
b0468b84 | 4280 | else |
77a02b01 JW |
4281 | return (qualifiers | (TREE_UNSIGNED (type) ? 15 : 5)); |
4282 | ||
210aa14a | 4283 | case REAL_TYPE: |
77a02b01 JW |
4284 | /* Carefully distinguish all the standard types of C, |
4285 | without messing up if the language is not C. */ | |
b0468b84 | 4286 | |
77a02b01 | 4287 | if (TYPE_PRECISION (type) == FLOAT_TYPE_SIZE) |
210aa14a | 4288 | return (qualifiers | 6); |
b0468b84 RK |
4289 | |
4290 | else | |
4291 | return (qualifiers | 7); | |
210aa14a RS |
4292 | |
4293 | case COMPLEX_TYPE: /* GNU Fortran COMPLEX type. */ | |
13d39dbc | 4294 | /* ??? We need to distinguish between double and float complex types, |
c82aa69a JW |
4295 | but I don't know how yet because I can't reach this code from |
4296 | existing front-ends. */ | |
4297 | return (qualifiers | 7); /* Who knows? */ | |
4298 | ||
210aa14a RS |
4299 | case CHAR_TYPE: /* GNU Pascal CHAR type. Not used in C. */ |
4300 | case BOOLEAN_TYPE: /* GNU Fortran BOOLEAN type. */ | |
4301 | case FILE_TYPE: /* GNU Pascal FILE type. */ | |
26902ae0 | 4302 | case SET_TYPE: /* GNU Pascal SET type. */ |
210aa14a | 4303 | case LANG_TYPE: /* ? */ |
26902ae0 | 4304 | return qualifiers; |
210aa14a RS |
4305 | |
4306 | default: | |
4307 | abort (); /* Not a type! */ | |
4308 | } | |
4309 | } | |
4310 | } | |
ead69aea | 4311 | \f |
61a55e8b DE |
4312 | /* Nested function support. */ |
4313 | ||
4314 | /* Emit RTL insns to initialize the variable parts of a trampoline. | |
4315 | FNADDR is an RTX for the address of the function's pure code. | |
4316 | CXT is an RTX for the static chain value for the function. | |
4317 | ||
4318 | This takes 16 insns: 2 shifts & 2 ands (to split up addresses), 4 sethi | |
4319 | (to load in opcodes), 4 iors (to merge address and opcodes), and 4 writes | |
4320 | (to store insns). This is a bit excessive. Perhaps a different | |
4321 | mechanism would be better here. | |
4322 | ||
849a528d | 4323 | Emit enough FLUSH insns to synchronize the data and instruction caches. */ |
61a55e8b DE |
4324 | |
4325 | void | |
4326 | sparc_initialize_trampoline (tramp, fnaddr, cxt) | |
4327 | rtx tramp, fnaddr, cxt; | |
4328 | { | |
4329 | rtx high_cxt = expand_shift (RSHIFT_EXPR, SImode, cxt, | |
4330 | size_int (10), 0, 1); | |
4331 | rtx high_fn = expand_shift (RSHIFT_EXPR, SImode, fnaddr, | |
4332 | size_int (10), 0, 1); | |
4333 | rtx low_cxt = expand_and (cxt, gen_rtx (CONST_INT, VOIDmode, 0x3ff), 0); | |
4334 | rtx low_fn = expand_and (fnaddr, gen_rtx (CONST_INT, VOIDmode, 0x3ff), 0); | |
4335 | rtx g1_sethi = gen_rtx (HIGH, SImode, | |
4336 | gen_rtx (CONST_INT, VOIDmode, 0x03000000)); | |
4337 | rtx g2_sethi = gen_rtx (HIGH, SImode, | |
4338 | gen_rtx (CONST_INT, VOIDmode, 0x05000000)); | |
4339 | rtx g1_ori = gen_rtx (HIGH, SImode, | |
4340 | gen_rtx (CONST_INT, VOIDmode, 0x82106000)); | |
4341 | rtx g2_ori = gen_rtx (HIGH, SImode, | |
4342 | gen_rtx (CONST_INT, VOIDmode, 0x8410A000)); | |
4343 | rtx tem = gen_reg_rtx (SImode); | |
4344 | emit_move_insn (tem, g1_sethi); | |
4345 | emit_insn (gen_iorsi3 (high_fn, high_fn, tem)); | |
4346 | emit_move_insn (gen_rtx (MEM, SImode, plus_constant (tramp, 0)), high_fn); | |
4347 | emit_move_insn (tem, g1_ori); | |
4348 | emit_insn (gen_iorsi3 (low_fn, low_fn, tem)); | |
4349 | emit_move_insn (gen_rtx (MEM, SImode, plus_constant (tramp, 4)), low_fn); | |
4350 | emit_move_insn (tem, g2_sethi); | |
4351 | emit_insn (gen_iorsi3 (high_cxt, high_cxt, tem)); | |
4352 | emit_move_insn (gen_rtx (MEM, SImode, plus_constant (tramp, 8)), high_cxt); | |
4353 | emit_move_insn (tem, g2_ori); | |
4354 | emit_insn (gen_iorsi3 (low_cxt, low_cxt, tem)); | |
4355 | emit_move_insn (gen_rtx (MEM, SImode, plus_constant (tramp, 16)), low_cxt); | |
d2889939 RK |
4356 | emit_insn (gen_flush (validize_mem (gen_rtx (MEM, SImode, tramp)))); |
4357 | emit_insn (gen_flush (validize_mem (gen_rtx (MEM, SImode, | |
4358 | plus_constant (tramp, 8))))); | |
4359 | emit_insn (gen_flush (validize_mem (gen_rtx (MEM, SImode, | |
4360 | plus_constant (tramp, 16))))); | |
61a55e8b DE |
4361 | } |
4362 | ||
849a528d RK |
4363 | /* The 64 bit version is simpler because it makes more sense to load the |
4364 | values as "immediate" data out of the trampoline. It's also easier since | |
4365 | we can read the PC without clobbering a register. */ | |
4366 | ||
61a55e8b DE |
4367 | void |
4368 | sparc64_initialize_trampoline (tramp, fnaddr, cxt) | |
4369 | rtx tramp, fnaddr, cxt; | |
4370 | { | |
849a528d RK |
4371 | emit_move_insn (gen_rtx (MEM, DImode, plus_constant (tramp, 24)), cxt); |
4372 | emit_move_insn (gen_rtx (MEM, DImode, plus_constant (tramp, 32)), fnaddr); | |
38489316 DE |
4373 | emit_insn (gen_flush (validize_mem (gen_rtx (MEM, DImode, tramp)))); |
4374 | emit_insn (gen_flush (validize_mem (gen_rtx (MEM, DImode, | |
4375 | plus_constant (tramp, 8))))); | |
4376 | emit_insn (gen_flush (validize_mem (gen_rtx (MEM, DImode, | |
4377 | plus_constant (tramp, 16))))); | |
849a528d RK |
4378 | emit_insn (gen_flush (validize_mem (gen_rtx (MEM, DImode, |
4379 | plus_constant (tramp, 24))))); | |
4380 | emit_insn (gen_flush (validize_mem (gen_rtx (MEM, DImode, | |
4381 | plus_constant (tramp, 32))))); | |
61a55e8b DE |
4382 | } |
4383 | \f | |
c819be5b JW |
4384 | /* Subroutines to support a flat (single) register window calling |
4385 | convention. */ | |
4386 | ||
4387 | /* Single-register window sparc stack frames look like: | |
4388 | ||
4389 | Before call After call | |
4390 | +-----------------------+ +-----------------------+ | |
86735b02 DE |
4391 | high | | | | |
4392 | mem | caller's temps. | | caller's temps. | | |
c819be5b JW |
4393 | | | | | |
4394 | +-----------------------+ +-----------------------+ | |
4395 | | | | | | |
4396 | | arguments on stack. | | arguments on stack. | | |
86735b02 DE |
4397 | | | | | |
4398 | +-----------------------+FP+92->+-----------------------+ | |
c819be5b JW |
4399 | | 6 words to save | | 6 words to save | |
4400 | | arguments passed | | arguments passed | | |
4401 | | in registers, even | | in registers, even | | |
86735b02 DE |
4402 | | if not passed. | | if not passed. | |
4403 | SP+68->+-----------------------+FP+68->+-----------------------+ | |
4404 | | 1 word struct addr | | 1 word struct addr | | |
4405 | +-----------------------+FP+64->+-----------------------+ | |
4406 | | | | | | |
4407 | | 16 word reg save area | | 16 word reg save area | | |
4408 | | | | | | |
4409 | SP->+-----------------------+ FP->+-----------------------+ | |
4410 | | 4 word area for | | |
4411 | | fp/alu reg moves | | |
4412 | FP-16->+-----------------------+ | |
4413 | | | | |
4414 | | local variables | | |
4415 | | | | |
4416 | +-----------------------+ | |
4417 | | | | |
c819be5b | 4418 | | fp register save | |
86735b02 DE |
4419 | | | |
4420 | +-----------------------+ | |
4421 | | | | |
c819be5b JW |
4422 | | gp register save | |
4423 | | | | |
86735b02 DE |
4424 | +-----------------------+ |
4425 | | | | |
c819be5b | 4426 | | alloca allocations | |
86735b02 DE |
4427 | | | |
4428 | +-----------------------+ | |
4429 | | | | |
c819be5b | 4430 | | arguments on stack | |
86735b02 DE |
4431 | | | |
4432 | SP+92->+-----------------------+ | |
c819be5b | 4433 | | 6 words to save | |
86735b02 | 4434 | | arguments passed | |
c819be5b | 4435 | | in registers, even | |
86735b02 DE |
4436 | low | if not passed. | |
4437 | memory SP+68->+-----------------------+ | |
4438 | | 1 word struct addr | | |
4439 | SP+64->+-----------------------+ | |
4440 | | | | |
4441 | I 16 word reg save area | | |
4442 | | | | |
4443 | SP->+-----------------------+ */ | |
c819be5b | 4444 | |
c6aa9ce1 | 4445 | /* Structure to be filled in by sparc_flat_compute_frame_size with register |
c819be5b JW |
4446 | save masks, and offsets for the current function. */ |
4447 | ||
4448 | struct sparc_frame_info | |
4449 | { | |
4450 | unsigned long total_size; /* # bytes that the entire frame takes up. */ | |
4451 | unsigned long var_size; /* # bytes that variables take up. */ | |
4452 | unsigned long args_size; /* # bytes that outgoing arguments take up. */ | |
4453 | unsigned long extra_size; /* # bytes of extra gunk. */ | |
4454 | unsigned int gp_reg_size; /* # bytes needed to store gp regs. */ | |
4455 | unsigned int fp_reg_size; /* # bytes needed to store fp regs. */ | |
86735b02 | 4456 | unsigned long gmask; /* Mask of saved gp registers. */ |
c819be5b | 4457 | unsigned long fmask; /* Mask of saved fp registers. */ |
86735b02 | 4458 | unsigned long reg_offset; /* Offset from new sp to store regs. */ |
c819be5b JW |
4459 | int initialized; /* Nonzero if frame size already calculated. */ |
4460 | }; | |
4461 | ||
c6aa9ce1 | 4462 | /* Current frame information calculated by sparc_flat_compute_frame_size. */ |
c819be5b JW |
4463 | struct sparc_frame_info current_frame_info; |
4464 | ||
4465 | /* Zero structure to initialize current_frame_info. */ | |
4466 | struct sparc_frame_info zero_frame_info; | |
4467 | ||
4468 | /* Tell prologue and epilogue if register REGNO should be saved / restored. */ | |
4469 | ||
86735b02 DE |
4470 | #define RETURN_ADDR_REGNUM 15 |
4471 | #define FRAME_POINTER_MASK (1 << (FRAME_POINTER_REGNUM)) | |
4472 | #define RETURN_ADDR_MASK (1 << (RETURN_ADDR_REGNUM)) | |
4473 | ||
c819be5b JW |
4474 | #define MUST_SAVE_REGISTER(regno) \ |
4475 | ((regs_ever_live[regno] && !call_used_regs[regno]) \ | |
4476 | || (regno == FRAME_POINTER_REGNUM && frame_pointer_needed) \ | |
86735b02 | 4477 | || (regno == RETURN_ADDR_REGNUM && regs_ever_live[RETURN_ADDR_REGNUM])) |
c819be5b JW |
4478 | |
4479 | /* Return the bytes needed to compute the frame pointer from the current | |
4480 | stack pointer. */ | |
4481 | ||
4482 | unsigned long | |
c6aa9ce1 | 4483 | sparc_flat_compute_frame_size (size) |
c819be5b JW |
4484 | int size; /* # of var. bytes allocated. */ |
4485 | { | |
4486 | int regno; | |
4487 | unsigned long total_size; /* # bytes that the entire frame takes up. */ | |
4488 | unsigned long var_size; /* # bytes that variables take up. */ | |
4489 | unsigned long args_size; /* # bytes that outgoing arguments take up. */ | |
4490 | unsigned long extra_size; /* # extra bytes. */ | |
4491 | unsigned int gp_reg_size; /* # bytes needed to store gp regs. */ | |
4492 | unsigned int fp_reg_size; /* # bytes needed to store fp regs. */ | |
86735b02 | 4493 | unsigned long gmask; /* Mask of saved gp registers. */ |
c819be5b | 4494 | unsigned long fmask; /* Mask of saved fp registers. */ |
86735b02 DE |
4495 | unsigned long reg_offset; /* Offset to register save area. */ |
4496 | int need_aligned_p; /* 1 if need the save area 8 byte aligned. */ | |
c819be5b JW |
4497 | |
4498 | /* This is the size of the 16 word reg save area, 1 word struct addr | |
4499 | area, and 4 word fp/alu register copy area. */ | |
4500 | extra_size = -STARTING_FRAME_OFFSET + FIRST_PARM_OFFSET(0); | |
4501 | var_size = size; | |
4502 | /* Also include the size needed for the 6 parameter registers. */ | |
4503 | args_size = current_function_outgoing_args_size + 24; | |
4504 | total_size = var_size + args_size + extra_size; | |
4505 | gp_reg_size = 0; | |
4506 | fp_reg_size = 0; | |
86735b02 | 4507 | gmask = 0; |
c819be5b | 4508 | fmask = 0; |
86735b02 DE |
4509 | reg_offset = 0; |
4510 | need_aligned_p = 0; | |
c819be5b JW |
4511 | |
4512 | /* Calculate space needed for gp registers. */ | |
4513 | for (regno = 1; regno <= 31; regno++) | |
4514 | { | |
4515 | if (MUST_SAVE_REGISTER (regno)) | |
4516 | { | |
86735b02 DE |
4517 | /* If we need to save two regs in a row, ensure there's room to bump |
4518 | up the address to align it to a doubleword boundary. */ | |
c819be5b JW |
4519 | if ((regno & 0x1) == 0 && MUST_SAVE_REGISTER (regno+1)) |
4520 | { | |
4521 | if (gp_reg_size % 8 != 0) | |
86735b02 | 4522 | gp_reg_size += 4; |
c819be5b | 4523 | gp_reg_size += 2 * UNITS_PER_WORD; |
86735b02 | 4524 | gmask |= 3 << regno; |
c819be5b | 4525 | regno++; |
86735b02 | 4526 | need_aligned_p = 1; |
c819be5b JW |
4527 | } |
4528 | else | |
4529 | { | |
4530 | gp_reg_size += UNITS_PER_WORD; | |
86735b02 | 4531 | gmask |= 1 << regno; |
c819be5b JW |
4532 | } |
4533 | } | |
4534 | } | |
c819be5b JW |
4535 | |
4536 | /* Calculate space needed for fp registers. */ | |
4537 | for (regno = 32; regno <= 63; regno++) | |
4538 | { | |
4539 | if (regs_ever_live[regno] && !call_used_regs[regno]) | |
4540 | { | |
4541 | fp_reg_size += UNITS_PER_WORD; | |
4542 | fmask |= 1 << (regno - 32); | |
4543 | } | |
4544 | } | |
4545 | ||
86735b02 DE |
4546 | if (gmask || fmask) |
4547 | { | |
4548 | int n; | |
4549 | reg_offset = FIRST_PARM_OFFSET(0) + args_size; | |
4550 | /* Ensure save area is 8 byte aligned if we need it. */ | |
4551 | n = reg_offset % 8; | |
4552 | if (need_aligned_p && n != 0) | |
4553 | { | |
4554 | total_size += 8 - n; | |
4555 | reg_offset += 8 - n; | |
4556 | } | |
4557 | total_size += gp_reg_size + fp_reg_size; | |
4558 | } | |
c819be5b | 4559 | |
86735b02 | 4560 | /* ??? This looks a little suspicious. Clarify. */ |
c819be5b JW |
4561 | if (total_size == extra_size) |
4562 | total_size = extra_size = 0; | |
4563 | ||
4564 | total_size = SPARC_STACK_ALIGN (total_size); | |
4565 | ||
4566 | /* Save other computed information. */ | |
4567 | current_frame_info.total_size = total_size; | |
4568 | current_frame_info.var_size = var_size; | |
4569 | current_frame_info.args_size = args_size; | |
4570 | current_frame_info.extra_size = extra_size; | |
4571 | current_frame_info.gp_reg_size = gp_reg_size; | |
4572 | current_frame_info.fp_reg_size = fp_reg_size; | |
86735b02 | 4573 | current_frame_info.gmask = gmask; |
c819be5b | 4574 | current_frame_info.fmask = fmask; |
86735b02 | 4575 | current_frame_info.reg_offset = reg_offset; |
c819be5b JW |
4576 | current_frame_info.initialized = reload_completed; |
4577 | ||
c819be5b JW |
4578 | /* Ok, we're done. */ |
4579 | return total_size; | |
4580 | } | |
4581 | \f | |
86735b02 DE |
4582 | /* Save/restore registers in GMASK and FMASK at register BASE_REG plus offset |
4583 | OFFSET. | |
4584 | ||
4585 | BASE_REG must be 8 byte aligned. This allows us to test OFFSET for | |
4586 | appropriate alignment and use DOUBLEWORD_OP when we can. We assume | |
4587 | [BASE_REG+OFFSET] will always be a valid address. | |
4588 | ||
4589 | WORD_OP is either "st" for save, "ld" for restore. | |
4590 | DOUBLEWORD_OP is either "std" for save, "ldd" for restore. */ | |
c819be5b JW |
4591 | |
4592 | void | |
86735b02 DE |
4593 | sparc_flat_save_restore (file, base_reg, offset, gmask, fmask, word_op, doubleword_op) |
4594 | FILE *file; | |
4595 | char *base_reg; | |
4596 | unsigned int offset; | |
4597 | unsigned long gmask; | |
4598 | unsigned long fmask; | |
4599 | char *word_op; | |
4600 | char *doubleword_op; | |
c819be5b JW |
4601 | { |
4602 | int regno; | |
c819be5b | 4603 | |
86735b02 DE |
4604 | if (gmask == 0 && fmask == 0) |
4605 | return; | |
c819be5b | 4606 | |
86735b02 DE |
4607 | /* Save registers starting from high to low. We've already saved the |
4608 | previous frame pointer and previous return address for the debugger's | |
4609 | sake. The debugger allows us to not need a nop in the epilog if at least | |
4610 | one register is reloaded in addition to return address. */ | |
c819be5b | 4611 | |
86735b02 | 4612 | if (gmask) |
c819be5b JW |
4613 | { |
4614 | for (regno = 1; regno <= 31; regno++) | |
4615 | { | |
86735b02 | 4616 | if ((gmask & (1L << regno)) != 0) |
c819be5b | 4617 | { |
86735b02 | 4618 | if ((regno & 0x1) == 0 && ((gmask & (1L << (regno+1))) != 0)) |
c819be5b | 4619 | { |
86735b02 DE |
4620 | /* We can save two registers in a row. If we're not at a |
4621 | double word boundary, move to one. | |
4622 | sparc_flat_compute_frame_size ensures there's room to do | |
4623 | this. */ | |
4624 | if (offset % 8 != 0) | |
4625 | offset += UNITS_PER_WORD; | |
4626 | ||
c819be5b JW |
4627 | if (word_op[0] == 's') |
4628 | fprintf (file, "\t%s %s,[%s+%d]\n", | |
4629 | doubleword_op, reg_names[regno], | |
86735b02 | 4630 | base_reg, offset); |
c819be5b JW |
4631 | else |
4632 | fprintf (file, "\t%s [%s+%d],%s\n", | |
86735b02 | 4633 | doubleword_op, base_reg, offset, |
c819be5b JW |
4634 | reg_names[regno]); |
4635 | ||
86735b02 | 4636 | offset += 2 * UNITS_PER_WORD; |
c819be5b JW |
4637 | regno++; |
4638 | } | |
4639 | else | |
4640 | { | |
4641 | if (word_op[0] == 's') | |
4642 | fprintf (file, "\t%s %s,[%s+%d]\n", | |
4643 | word_op, reg_names[regno], | |
86735b02 | 4644 | base_reg, offset); |
c819be5b JW |
4645 | else |
4646 | fprintf (file, "\t%s [%s+%d],%s\n", | |
86735b02 | 4647 | word_op, base_reg, offset, reg_names[regno]); |
c819be5b | 4648 | |
86735b02 | 4649 | offset += UNITS_PER_WORD; |
c819be5b JW |
4650 | } |
4651 | } | |
4652 | } | |
4653 | } | |
4654 | ||
4655 | if (fmask) | |
4656 | { | |
4657 | for (regno = 32; regno <= 63; regno++) | |
4658 | { | |
4659 | if ((fmask & (1L << (regno - 32))) != 0) | |
4660 | { | |
4661 | if (word_op[0] == 's') | |
4662 | fprintf (file, "\t%s %s,[%s+%d]\n", | |
4663 | word_op, reg_names[regno], | |
86735b02 | 4664 | base_reg, offset); |
c819be5b JW |
4665 | else |
4666 | fprintf (file, "\t%s [%s+%d],%s\n", | |
86735b02 | 4667 | word_op, base_reg, offset, reg_names[regno]); |
c819be5b | 4668 | |
86735b02 | 4669 | offset += UNITS_PER_WORD; |
c819be5b JW |
4670 | } |
4671 | } | |
4672 | } | |
4673 | } | |
4674 | \f | |
4675 | /* Set up the stack and frame (if desired) for the function. */ | |
4676 | ||
4677 | void | |
c6aa9ce1 | 4678 | sparc_flat_output_function_prologue (file, size) |
c819be5b JW |
4679 | FILE *file; |
4680 | int size; | |
4681 | { | |
c819be5b | 4682 | char *sp_str = reg_names[STACK_POINTER_REGNUM]; |
86735b02 | 4683 | unsigned long gmask = current_frame_info.gmask; |
a07c1915 | 4684 | |
c6aa9ce1 | 4685 | /* This is only for the human reader. */ |
c819be5b | 4686 | fprintf (file, "\t!#PROLOGUE# 0\n"); |
86735b02 DE |
4687 | fprintf (file, "\t!# vars= %d, regs= %d/%d, args= %d, extra= %d\n", |
4688 | current_frame_info.var_size, | |
4689 | current_frame_info.gp_reg_size / 4, | |
9f8b85b8 | 4690 | current_frame_info.fp_reg_size / 4, |
86735b02 DE |
4691 | current_function_outgoing_args_size, |
4692 | current_frame_info.extra_size); | |
c819be5b JW |
4693 | |
4694 | size = SPARC_STACK_ALIGN (size); | |
86735b02 DE |
4695 | size = (! current_frame_info.initialized |
4696 | ? sparc_flat_compute_frame_size (size) | |
4697 | : current_frame_info.total_size); | |
c819be5b | 4698 | |
86735b02 DE |
4699 | /* These cases shouldn't happen. Catch them now. */ |
4700 | if (size == 0 && (gmask || current_frame_info.fmask)) | |
4701 | abort (); | |
c819be5b | 4702 | |
86735b02 DE |
4703 | /* Allocate our stack frame by decrementing %sp. |
4704 | At present, the only algorithm gdb can use to determine if this is a | |
4705 | flat frame is if we always set %i7 if we set %sp. This can be optimized | |
4706 | in the future by putting in some sort of debugging information that says | |
4707 | this is a `flat' function. However, there is still the case of debugging | |
4708 | code without such debugging information (including cases where most fns | |
4709 | have such info, but there is one that doesn't). So, always do this now | |
4710 | so we don't get a lot of code out there that gdb can't handle. | |
4711 | If the frame pointer isn't needn't then that's ok - gdb won't be able to | |
4712 | distinguish us from a non-flat function but there won't (and shouldn't) | |
4713 | be any differences anyway. The return pc is saved (if necessary) right | |
4714 | after %i7 so gdb won't have to look too far to find it. */ | |
4715 | if (size > 0) | |
c819be5b | 4716 | { |
86735b02 | 4717 | unsigned int reg_offset = current_frame_info.reg_offset; |
c6aa9ce1 | 4718 | char *fp_str = reg_names[FRAME_POINTER_REGNUM]; |
86735b02 DE |
4719 | char *t1_str = "%g1"; |
4720 | ||
4721 | /* Things get a little tricky if local variables take up more than ~4096 | |
4722 | bytes and outgoing arguments take up more than ~4096 bytes. When that | |
4723 | happens, the register save area can't be accessed from either end of | |
4724 | the frame. Handle this by decrementing %sp to the start of the gp | |
4725 | register save area, save the regs, update %i7, and then set %sp to its | |
4726 | final value. Given that we only have one scratch register to play | |
4727 | with it is the cheapest solution, and it helps gdb out as it won't | |
4728 | slow down recognition of flat functions. | |
4729 | Don't change the order of insns emitted here without checking with | |
4730 | the gdb folk first. */ | |
4731 | ||
ddd5a7c1 | 4732 | /* Is the entire register save area offsettable from %sp? */ |
86735b02 DE |
4733 | if (reg_offset < 4096 - 64 * UNITS_PER_WORD) |
4734 | { | |
4735 | if (size <= 4096) | |
4736 | { | |
4737 | fprintf (file, "\tadd %s,%d,%s\n", | |
4738 | sp_str, -size, sp_str); | |
4739 | if (gmask & FRAME_POINTER_MASK) | |
4740 | { | |
4741 | fprintf (file, "\tst %s,[%s+%d]\n", | |
4742 | fp_str, sp_str, reg_offset); | |
4743 | fprintf (file, "\tsub %s,%d,%s\t!# set up frame pointer\n", | |
4744 | sp_str, -size, fp_str); | |
4745 | reg_offset += 4; | |
4746 | } | |
4747 | } | |
4748 | else | |
4749 | { | |
4750 | fprintf (file, "\tset %d,%s\n\tsub %s,%s,%s\n", | |
4751 | size, t1_str, sp_str, t1_str, sp_str); | |
4752 | if (gmask & FRAME_POINTER_MASK) | |
4753 | { | |
4754 | fprintf (file, "\tst %s,[%s+%d]\n", | |
4755 | fp_str, sp_str, reg_offset); | |
4756 | fprintf (file, "\tadd %s,%s,%s\t!# set up frame pointer\n", | |
4757 | sp_str, t1_str, fp_str); | |
4758 | reg_offset += 4; | |
4759 | } | |
4760 | } | |
4761 | if (gmask & RETURN_ADDR_MASK) | |
4762 | { | |
4763 | fprintf (file, "\tst %s,[%s+%d]\n", | |
4764 | reg_names[RETURN_ADDR_REGNUM], sp_str, reg_offset); | |
4765 | reg_offset += 4; | |
4766 | } | |
4767 | sparc_flat_save_restore (file, sp_str, reg_offset, | |
4768 | gmask & ~(FRAME_POINTER_MASK | RETURN_ADDR_MASK), | |
4769 | current_frame_info.fmask, | |
4770 | "st", "std"); | |
4771 | } | |
c819be5b | 4772 | else |
86735b02 DE |
4773 | { |
4774 | /* Subtract %sp in two steps, but make sure there is always a | |
4775 | 64 byte register save area, and %sp is properly aligned. */ | |
4776 | /* Amount to decrement %sp by, the first time. */ | |
4777 | unsigned int size1 = ((size - reg_offset + 64) + 15) & -16; | |
4778 | /* Offset to register save area from %sp. */ | |
4779 | unsigned int offset = size1 - (size - reg_offset); | |
4780 | ||
4781 | if (size1 <= 4096) | |
4782 | { | |
4783 | fprintf (file, "\tadd %s,%d,%s\n", | |
4784 | sp_str, -size1, sp_str); | |
4785 | if (gmask & FRAME_POINTER_MASK) | |
4786 | { | |
4787 | fprintf (file, "\tst %s,[%s+%d]\n\tsub %s,%d,%s\t!# set up frame pointer\n", | |
4788 | fp_str, sp_str, offset, sp_str, -size1, fp_str); | |
4789 | offset += 4; | |
4790 | } | |
4791 | } | |
4792 | else | |
4793 | { | |
4794 | fprintf (file, "\tset %d,%s\n\tsub %s,%s,%s\n", | |
4795 | size1, t1_str, sp_str, t1_str, sp_str); | |
4796 | if (gmask & FRAME_POINTER_MASK) | |
4797 | { | |
4798 | fprintf (file, "\tst %s,[%s+%d]\n\tadd %s,%s,%s\t!# set up frame pointer\n", | |
4799 | fp_str, sp_str, offset, sp_str, t1_str, fp_str); | |
4800 | offset += 4; | |
4801 | } | |
4802 | } | |
4803 | if (gmask & RETURN_ADDR_MASK) | |
4804 | { | |
4805 | fprintf (file, "\tst %s,[%s+%d]\n", | |
4806 | reg_names[RETURN_ADDR_REGNUM], sp_str, offset); | |
4807 | offset += 4; | |
4808 | } | |
4809 | sparc_flat_save_restore (file, sp_str, offset, | |
4810 | gmask & ~(FRAME_POINTER_MASK | RETURN_ADDR_MASK), | |
4811 | current_frame_info.fmask, | |
4812 | "st", "std"); | |
4813 | fprintf (file, "\tset %d,%s\n\tsub %s,%s,%s\n", | |
4814 | size - size1, t1_str, sp_str, t1_str, sp_str); | |
4815 | } | |
c819be5b | 4816 | } |
c6aa9ce1 DE |
4817 | |
4818 | fprintf (file, "\t!#PROLOGUE# 1\n"); | |
c819be5b JW |
4819 | } |
4820 | \f | |
4821 | /* Do any necessary cleanup after a function to restore stack, frame, | |
4822 | and regs. */ | |
4823 | ||
4824 | void | |
c6aa9ce1 | 4825 | sparc_flat_output_function_epilogue (file, size) |
c819be5b JW |
4826 | FILE *file; |
4827 | int size; | |
4828 | { | |
c819be5b JW |
4829 | rtx epilogue_delay = current_function_epilogue_delay_list; |
4830 | int noepilogue = FALSE; | |
c819be5b | 4831 | |
c6aa9ce1 DE |
4832 | /* This is only for the human reader. */ |
4833 | fprintf (file, "\t!#EPILOGUE#\n"); | |
4834 | ||
c819be5b JW |
4835 | /* The epilogue does not depend on any registers, but the stack |
4836 | registers, so we assume that if we have 1 pending nop, it can be | |
4837 | ignored, and 2 it must be filled (2 nops occur for integer | |
4838 | multiply and divide). */ | |
4839 | ||
4840 | size = SPARC_STACK_ALIGN (size); | |
86735b02 | 4841 | size = (!current_frame_info.initialized |
c6aa9ce1 | 4842 | ? sparc_flat_compute_frame_size (size) |
c819be5b JW |
4843 | : current_frame_info.total_size); |
4844 | ||
86735b02 | 4845 | if (size == 0 && epilogue_delay == 0) |
c819be5b JW |
4846 | { |
4847 | rtx insn = get_last_insn (); | |
4848 | ||
4849 | /* If the last insn was a BARRIER, we don't have to write any code | |
4850 | because a jump (aka return) was put there. */ | |
4851 | if (GET_CODE (insn) == NOTE) | |
4852 | insn = prev_nonnote_insn (insn); | |
4853 | if (insn && GET_CODE (insn) == BARRIER) | |
4854 | noepilogue = TRUE; | |
4855 | } | |
4856 | ||
4857 | if (!noepilogue) | |
4858 | { | |
86735b02 DE |
4859 | unsigned int reg_offset = current_frame_info.reg_offset; |
4860 | unsigned int size1; | |
4861 | char *sp_str = reg_names[STACK_POINTER_REGNUM]; | |
4862 | char *fp_str = reg_names[FRAME_POINTER_REGNUM]; | |
4863 | char *t1_str = "%g1"; | |
4864 | ||
c819be5b JW |
4865 | /* In the reload sequence, we don't need to fill the load delay |
4866 | slots for most of the loads, also see if we can fill the final | |
4867 | delay slot if not otherwise filled by the reload sequence. */ | |
4868 | ||
86735b02 DE |
4869 | if (size > 4095) |
4870 | fprintf (file, "\tset %d,%s\n", size, t1_str); | |
c819be5b JW |
4871 | |
4872 | if (frame_pointer_needed) | |
4873 | { | |
86735b02 DE |
4874 | if (size > 4095) |
4875 | fprintf (file,"\tsub %s,%s,%s\t\t!# sp not trusted here\n", | |
c819be5b JW |
4876 | fp_str, t1_str, sp_str); |
4877 | else | |
86735b02 DE |
4878 | fprintf (file,"\tsub %s,%d,%s\t\t!# sp not trusted here\n", |
4879 | fp_str, size, sp_str); | |
c819be5b JW |
4880 | } |
4881 | ||
ddd5a7c1 | 4882 | /* Is the entire register save area offsettable from %sp? */ |
86735b02 DE |
4883 | if (reg_offset < 4096 - 64 * UNITS_PER_WORD) |
4884 | { | |
4885 | size1 = 0; | |
4886 | } | |
4887 | else | |
4888 | { | |
4889 | /* Restore %sp in two steps, but make sure there is always a | |
4890 | 64 byte register save area, and %sp is properly aligned. */ | |
4891 | /* Amount to increment %sp by, the first time. */ | |
4892 | size1 = ((reg_offset - 64 - 16) + 15) & -16; | |
4893 | /* Offset to register save area from %sp. */ | |
4894 | reg_offset = size1 - reg_offset; | |
4895 | ||
4896 | fprintf (file, "\tset %d,%s\n\tadd %s,%s,%s\n", | |
4897 | size1, t1_str, sp_str, t1_str, sp_str); | |
4898 | } | |
4899 | ||
4900 | /* We must restore the frame pointer and return address reg first | |
4901 | because they are treated specially by the prologue output code. */ | |
4902 | if (current_frame_info.gmask & FRAME_POINTER_MASK) | |
4903 | { | |
4904 | fprintf (file, "\tld [%s+%d],%s\n", | |
4905 | sp_str, reg_offset, fp_str); | |
4906 | reg_offset += 4; | |
4907 | } | |
4908 | if (current_frame_info.gmask & RETURN_ADDR_MASK) | |
4909 | { | |
4910 | fprintf (file, "\tld [%s+%d],%s\n", | |
4911 | sp_str, reg_offset, reg_names[RETURN_ADDR_REGNUM]); | |
4912 | reg_offset += 4; | |
4913 | } | |
4914 | ||
4915 | /* Restore any remaining saved registers. */ | |
4916 | sparc_flat_save_restore (file, sp_str, reg_offset, | |
4917 | current_frame_info.gmask & ~(FRAME_POINTER_MASK | RETURN_ADDR_MASK), | |
4918 | current_frame_info.fmask, | |
4919 | "ld", "ldd"); | |
4920 | ||
4921 | /* If we had to increment %sp in two steps, record it so the second | |
4922 | restoration in the epilogue finishes up. */ | |
4923 | if (size1 > 0) | |
4924 | { | |
4925 | size -= size1; | |
4926 | if (size > 4095) | |
4927 | fprintf (file, "\tset %d,%s\n", | |
4928 | size, t1_str); | |
4929 | } | |
c819be5b | 4930 | |
c819be5b JW |
4931 | if (current_function_returns_struct) |
4932 | fprintf (file, "\tjmp %%o7+12\n"); | |
4933 | else | |
4934 | fprintf (file, "\tretl\n"); | |
4935 | ||
4936 | /* If the only register saved is the return address, we need a | |
4937 | nop, unless we have an instruction to put into it. Otherwise | |
4938 | we don't since reloading multiple registers doesn't reference | |
4939 | the register being loaded. */ | |
4940 | ||
4941 | if (epilogue_delay) | |
4942 | { | |
86735b02 | 4943 | if (size) |
c819be5b JW |
4944 | abort (); |
4945 | final_scan_insn (XEXP (epilogue_delay, 0), file, 1, -2, 1); | |
4946 | } | |
4947 | ||
86735b02 | 4948 | else if (size > 4095) |
c819be5b JW |
4949 | fprintf (file, "\tadd %s,%s,%s\n", sp_str, t1_str, sp_str); |
4950 | ||
86735b02 DE |
4951 | else if (size > 0) |
4952 | fprintf (file, "\tadd %s,%d,%s\n", sp_str, size, sp_str); | |
c819be5b JW |
4953 | |
4954 | else | |
4955 | fprintf (file, "\tnop\n"); | |
4956 | } | |
4957 | ||
4958 | /* Reset state info for each function. */ | |
4959 | current_frame_info = zero_frame_info; | |
4960 | } | |
4961 | \f | |
4962 | /* Define the number of delay slots needed for the function epilogue. | |
4963 | ||
4964 | On the sparc, we need a slot if either no stack has been allocated, | |
4965 | or the only register saved is the return register. */ | |
4966 | ||
4967 | int | |
c6aa9ce1 | 4968 | sparc_flat_epilogue_delay_slots () |
c819be5b JW |
4969 | { |
4970 | if (!current_frame_info.initialized) | |
c6aa9ce1 | 4971 | (void) sparc_flat_compute_frame_size (get_frame_size ()); |
c819be5b JW |
4972 | |
4973 | if (current_frame_info.total_size == 0) | |
4974 | return 1; | |
4975 | ||
c819be5b JW |
4976 | return 0; |
4977 | } | |
4978 | ||
4979 | /* Return true is TRIAL is a valid insn for the epilogue delay slot. | |
4980 | Any single length instruction which doesn't reference the stack or frame | |
4981 | pointer is OK. */ | |
4982 | ||
4983 | int | |
c6aa9ce1 | 4984 | sparc_flat_eligible_for_epilogue_delay (trial, slot) |
c819be5b JW |
4985 | rtx trial; |
4986 | int slot; | |
4987 | { | |
c4ce6853 DE |
4988 | rtx pat = PATTERN (trial); |
4989 | ||
4990 | if (get_attr_length (trial) != 1) | |
4991 | return 0; | |
4992 | ||
4993 | /* If %g0 is live, there are lots of things we can't handle. | |
4994 | Rather than trying to find them all now, let's punt and only | |
4995 | optimize things as necessary. */ | |
4996 | if (TARGET_LIVE_G0) | |
4997 | return 0; | |
4998 | ||
4999 | if (! reg_mentioned_p (stack_pointer_rtx, pat) | |
5000 | && ! reg_mentioned_p (frame_pointer_rtx, pat)) | |
c819be5b | 5001 | return 1; |
c4ce6853 | 5002 | |
c819be5b JW |
5003 | return 0; |
5004 | } | |
dbb54862 JW |
5005 | \f |
5006 | /* Adjust the cost of a scheduling dependency. Return the new cost of | |
5007 | a dependency LINK or INSN on DEP_INSN. COST is the current cost. */ | |
5008 | ||
5009 | int | |
5010 | supersparc_adjust_cost (insn, link, dep_insn, cost) | |
5011 | rtx insn; | |
5012 | rtx link; | |
5013 | rtx dep_insn; | |
5014 | int cost; | |
5015 | { | |
5016 | enum attr_type insn_type; | |
5017 | ||
5018 | if (! recog_memoized (insn)) | |
5019 | return 0; | |
5020 | ||
5021 | insn_type = get_attr_type (insn); | |
5022 | ||
5023 | if (REG_NOTE_KIND (link) == 0) | |
5024 | { | |
5025 | /* Data dependency; DEP_INSN writes a register that INSN reads some | |
5026 | cycles later. */ | |
5027 | ||
5028 | /* if a load, then the dependence must be on the memory address; | |
5029 | add an extra 'cycle'. Note that the cost could be two cycles | |
5030 | if the reg was written late in an instruction group; we can't tell | |
5031 | here. */ | |
5032 | if (insn_type == TYPE_LOAD || insn_type == TYPE_FPLOAD) | |
5033 | return cost + 3; | |
5034 | ||
5035 | /* Get the delay only if the address of the store is the dependence. */ | |
5036 | if (insn_type == TYPE_STORE || insn_type == TYPE_FPSTORE) | |
5037 | { | |
5038 | rtx pat = PATTERN(insn); | |
5039 | rtx dep_pat = PATTERN (dep_insn); | |
5040 | ||
5041 | if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET) | |
5042 | return cost; /* This shouldn't happen! */ | |
5043 | ||
5044 | /* The dependency between the two instructions was on the data that | |
5045 | is being stored. Assume that this implies that the address of the | |
5046 | store is not dependent. */ | |
5047 | if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat))) | |
5048 | return cost; | |
5049 | ||
5050 | return cost + 3; /* An approximation. */ | |
5051 | } | |
5052 | ||
5053 | /* A shift instruction cannot receive its data from an instruction | |
5054 | in the same cycle; add a one cycle penalty. */ | |
5055 | if (insn_type == TYPE_SHIFT) | |
5056 | return cost + 3; /* Split before cascade into shift. */ | |
5057 | } | |
5058 | else | |
5059 | { | |
5060 | /* Anti- or output- dependency; DEP_INSN reads/writes a register that | |
5061 | INSN writes some cycles later. */ | |
5062 | ||
5063 | /* These are only significant for the fpu unit; writing a fp reg before | |
5064 | the fpu has finished with it stalls the processor. */ | |
5065 | ||
5066 | /* Reusing an integer register causes no problems. */ | |
5067 | if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT) | |
5068 | return 0; | |
5069 | } | |
5070 | ||
5071 | return cost; | |
5072 | } |