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ab835497 RK |
1 | /* Subroutines for insn-output.c for Sun SPARC. |
2 | Copyright (C) 1987, 1988, 1989, 1992 Free Software Foundation, Inc. | |
3 | Contributed by Michael Tiemann (tiemann@cygnus.com) | |
4 | ||
5 | This file is part of GNU CC. | |
6 | ||
7 | GNU CC is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2, or (at your option) | |
10 | any later version. | |
11 | ||
12 | GNU CC is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GNU CC; see the file COPYING. If not, write to | |
19 | the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ | |
20 | ||
21 | #include <stdio.h> | |
22 | #include "config.h" | |
210aa14a | 23 | #include "tree.h" |
ab835497 RK |
24 | #include "rtl.h" |
25 | #include "regs.h" | |
26 | #include "hard-reg-set.h" | |
27 | #include "real.h" | |
28 | #include "insn-config.h" | |
29 | #include "conditions.h" | |
30 | #include "insn-flags.h" | |
31 | #include "output.h" | |
32 | #include "insn-attr.h" | |
33 | #include "flags.h" | |
34 | #include "expr.h" | |
35 | #include "recog.h" | |
36 | ||
37 | /* Global variables for machine-dependent things. */ | |
38 | ||
39 | /* Save the operands last given to a compare for use when we | |
40 | generate a scc or bcc insn. */ | |
41 | ||
42 | rtx sparc_compare_op0, sparc_compare_op1; | |
43 | ||
44 | /* We may need an epilogue if we spill too many registers. | |
45 | If this is non-zero, then we branch here for the epilogue. */ | |
46 | static rtx leaf_label; | |
47 | ||
48 | #ifdef LEAF_REGISTERS | |
49 | ||
50 | /* Vector to say how input registers are mapped to output | |
51 | registers. FRAME_POINTER_REGNUM cannot be remapped by | |
52 | this function to eliminate it. You must use -fomit-frame-pointer | |
53 | to get that. */ | |
54 | char leaf_reg_remap[] = | |
55 | { 0, 1, 2, 3, 4, 5, 6, 7, | |
56 | -1, -1, -1, -1, -1, -1, 14, -1, | |
57 | -1, -1, -1, -1, -1, -1, -1, -1, | |
58 | 8, 9, 10, 11, 12, 13, -1, 15, | |
59 | ||
60 | 32, 33, 34, 35, 36, 37, 38, 39, | |
61 | 40, 41, 42, 43, 44, 45, 46, 47, | |
62 | 48, 49, 50, 51, 52, 53, 54, 55, | |
63 | 56, 57, 58, 59, 60, 61, 62, 63}; | |
64 | ||
65 | char leaf_reg_backmap[] = | |
66 | { 0, 1, 2, 3, 4, 5, 6, 7, | |
67 | 24, 25, 26, 27, 28, 29, 14, 31, | |
68 | -1, -1, -1, -1, -1, -1, -1, -1, | |
69 | -1, -1, -1, -1, -1, -1, -1, -1, | |
70 | ||
71 | 32, 33, 34, 35, 36, 37, 38, 39, | |
72 | 40, 41, 42, 43, 44, 45, 46, 47, | |
73 | 48, 49, 50, 51, 52, 53, 54, 55, | |
74 | 56, 57, 58, 59, 60, 61, 62, 63}; | |
75 | #endif | |
76 | ||
77 | /* Global variables set by FUNCTION_PROLOGUE. */ | |
78 | /* Size of frame. Need to know this to emit return insns from | |
79 | leaf procedures. */ | |
80 | int apparent_fsize; | |
81 | int actual_fsize; | |
82 | ||
83 | /* Name of where we pretend to think the frame pointer points. | |
84 | Normally, this is "%fp", but if we are in a leaf procedure, | |
85 | this is "%sp+something". */ | |
86 | char *frame_base_name; | |
87 | ||
88 | static rtx find_addr_reg (); | |
89 | ||
90 | /* Return non-zero only if OP is a register of mode MODE, | |
91 | or const0_rtx. */ | |
92 | int | |
93 | reg_or_0_operand (op, mode) | |
94 | rtx op; | |
95 | enum machine_mode mode; | |
96 | { | |
97 | if (op == const0_rtx || register_operand (op, mode)) | |
98 | return 1; | |
99 | if (GET_CODE (op) == CONST_DOUBLE | |
100 | && CONST_DOUBLE_HIGH (op) == 0 | |
101 | && CONST_DOUBLE_LOW (op) == 0) | |
102 | return 1; | |
103 | return 0; | |
104 | } | |
105 | ||
106 | /* Nonzero if OP can appear as the dest of a RESTORE insn. */ | |
107 | int | |
108 | restore_operand (op, mode) | |
109 | rtx op; | |
110 | enum machine_mode mode; | |
111 | { | |
112 | return (GET_CODE (op) == REG && GET_MODE (op) == mode | |
113 | && (REGNO (op) < 8 || (REGNO (op) >= 24 && REGNO (op) < 32))); | |
114 | } | |
115 | ||
401cec23 JW |
116 | /* Call insn on SPARC can take a PC-relative constant address, or any regular |
117 | memory address. */ | |
ab835497 RK |
118 | |
119 | int | |
120 | call_operand (op, mode) | |
121 | rtx op; | |
122 | enum machine_mode mode; | |
123 | { | |
124 | if (GET_CODE (op) != MEM) | |
125 | abort (); | |
126 | op = XEXP (op, 0); | |
401cec23 | 127 | return (CONSTANT_P (op) || memory_address_p (Pmode, op)); |
ab835497 RK |
128 | } |
129 | ||
130 | int | |
131 | call_operand_address (op, mode) | |
132 | rtx op; | |
133 | enum machine_mode mode; | |
134 | { | |
401cec23 | 135 | return (CONSTANT_P (op) || memory_address_p (Pmode, op)); |
ab835497 RK |
136 | } |
137 | ||
138 | /* Returns 1 if OP is either a symbol reference or a sum of a symbol | |
139 | reference and a constant. */ | |
140 | ||
141 | int | |
142 | symbolic_operand (op, mode) | |
143 | register rtx op; | |
144 | enum machine_mode mode; | |
145 | { | |
146 | switch (GET_CODE (op)) | |
147 | { | |
148 | case SYMBOL_REF: | |
149 | case LABEL_REF: | |
150 | return 1; | |
151 | ||
152 | case CONST: | |
153 | op = XEXP (op, 0); | |
154 | return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF | |
155 | || GET_CODE (XEXP (op, 0)) == LABEL_REF) | |
156 | && GET_CODE (XEXP (op, 1)) == CONST_INT); | |
157 | ||
228b4037 | 158 | /* ??? This clause seems to be irrelevant. */ |
ab835497 RK |
159 | case CONST_DOUBLE: |
160 | return GET_MODE (op) == mode; | |
161 | ||
162 | default: | |
163 | return 0; | |
164 | } | |
165 | } | |
166 | ||
167 | /* Return truth value of statement that OP is a symbolic memory | |
168 | operand of mode MODE. */ | |
169 | ||
170 | int | |
171 | symbolic_memory_operand (op, mode) | |
172 | rtx op; | |
173 | enum machine_mode mode; | |
174 | { | |
175 | if (GET_CODE (op) == SUBREG) | |
176 | op = SUBREG_REG (op); | |
177 | if (GET_CODE (op) != MEM) | |
178 | return 0; | |
179 | op = XEXP (op, 0); | |
180 | return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST | |
181 | || GET_CODE (op) == HIGH || GET_CODE (op) == LABEL_REF); | |
182 | } | |
183 | ||
184 | /* Return 1 if the operand is either a register or a memory operand that is | |
185 | not symbolic. */ | |
186 | ||
187 | int | |
188 | reg_or_nonsymb_mem_operand (op, mode) | |
189 | register rtx op; | |
190 | enum machine_mode mode; | |
191 | { | |
192 | if (register_operand (op, mode)) | |
193 | return 1; | |
194 | ||
195 | if (memory_operand (op, mode) && ! symbolic_memory_operand (op, mode)) | |
196 | return 1; | |
197 | ||
198 | return 0; | |
199 | } | |
200 | ||
201 | int | |
202 | sparc_operand (op, mode) | |
203 | rtx op; | |
204 | enum machine_mode mode; | |
205 | { | |
206 | if (register_operand (op, mode)) | |
207 | return 1; | |
208 | if (GET_CODE (op) == CONST_INT) | |
209 | return SMALL_INT (op); | |
210 | if (GET_MODE (op) != mode) | |
211 | return 0; | |
212 | if (GET_CODE (op) == SUBREG) | |
213 | op = SUBREG_REG (op); | |
214 | if (GET_CODE (op) != MEM) | |
215 | return 0; | |
216 | ||
217 | op = XEXP (op, 0); | |
218 | if (GET_CODE (op) == LO_SUM) | |
219 | return (GET_CODE (XEXP (op, 0)) == REG | |
220 | && symbolic_operand (XEXP (op, 1), Pmode)); | |
221 | return memory_address_p (mode, op); | |
222 | } | |
223 | ||
224 | int | |
225 | move_operand (op, mode) | |
226 | rtx op; | |
227 | enum machine_mode mode; | |
228 | { | |
229 | if (mode == DImode && arith_double_operand (op, mode)) | |
230 | return 1; | |
231 | if (register_operand (op, mode)) | |
232 | return 1; | |
233 | if (GET_CODE (op) == CONST_INT) | |
234 | return (SMALL_INT (op) || (INTVAL (op) & 0x3ff) == 0); | |
235 | ||
236 | if (GET_MODE (op) != mode) | |
237 | return 0; | |
238 | if (GET_CODE (op) == SUBREG) | |
239 | op = SUBREG_REG (op); | |
240 | if (GET_CODE (op) != MEM) | |
241 | return 0; | |
242 | op = XEXP (op, 0); | |
243 | if (GET_CODE (op) == LO_SUM) | |
244 | return (register_operand (XEXP (op, 0), Pmode) | |
245 | && CONSTANT_P (XEXP (op, 1))); | |
246 | return memory_address_p (mode, op); | |
247 | } | |
248 | ||
249 | int | |
250 | move_pic_label (op, mode) | |
251 | rtx op; | |
252 | enum machine_mode mode; | |
253 | { | |
254 | /* Special case for PIC. */ | |
255 | if (flag_pic && GET_CODE (op) == LABEL_REF) | |
256 | return 1; | |
257 | return 0; | |
258 | } | |
259 | \f | |
260 | /* The rtx for the global offset table which is a special form | |
261 | that *is* a position independent symbolic constant. */ | |
262 | rtx pic_pc_rtx; | |
263 | ||
264 | /* Ensure that we are not using patterns that are not OK with PIC. */ | |
265 | ||
266 | int | |
267 | check_pic (i) | |
268 | int i; | |
269 | { | |
270 | switch (flag_pic) | |
271 | { | |
272 | case 1: | |
273 | if (GET_CODE (recog_operand[i]) == SYMBOL_REF | |
274 | || (GET_CODE (recog_operand[i]) == CONST | |
275 | && ! rtx_equal_p (pic_pc_rtx, recog_operand[i]))) | |
276 | abort (); | |
277 | case 2: | |
278 | default: | |
279 | return 1; | |
280 | } | |
281 | } | |
282 | ||
283 | /* Return true if X is an address which needs a temporary register when | |
284 | reloaded while generating PIC code. */ | |
285 | ||
286 | int | |
287 | pic_address_needs_scratch (x) | |
288 | rtx x; | |
289 | { | |
290 | /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */ | |
291 | if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS | |
292 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF | |
293 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT | |
294 | && ! SMALL_INT (XEXP (XEXP (x, 0), 1))) | |
295 | return 1; | |
296 | ||
297 | return 0; | |
298 | } | |
299 | ||
300 | int | |
301 | memop (op, mode) | |
302 | rtx op; | |
303 | enum machine_mode mode; | |
304 | { | |
305 | if (GET_CODE (op) == MEM) | |
306 | return (mode == VOIDmode || mode == GET_MODE (op)); | |
307 | return 0; | |
308 | } | |
309 | ||
310 | /* Return truth value of whether OP is EQ or NE. */ | |
311 | ||
312 | int | |
313 | eq_or_neq (op, mode) | |
314 | rtx op; | |
315 | enum machine_mode mode; | |
316 | { | |
317 | return (GET_CODE (op) == EQ || GET_CODE (op) == NE); | |
318 | } | |
319 | ||
320 | /* Return 1 if this is a comparison operator, but not an EQ, NE, GEU, | |
321 | or LTU for non-floating-point. We handle those specially. */ | |
322 | ||
323 | int | |
324 | normal_comp_operator (op, mode) | |
325 | rtx op; | |
326 | enum machine_mode mode; | |
327 | { | |
328 | enum rtx_code code = GET_CODE (op); | |
329 | ||
330 | if (GET_RTX_CLASS (code) != '<') | |
331 | return 0; | |
332 | ||
4d449554 JW |
333 | if (GET_MODE (XEXP (op, 0)) == CCFPmode |
334 | || GET_MODE (XEXP (op, 0)) == CCFPEmode) | |
ab835497 RK |
335 | return 1; |
336 | ||
337 | return (code != NE && code != EQ && code != GEU && code != LTU); | |
338 | } | |
339 | ||
340 | /* Return 1 if this is a comparison operator. This allows the use of | |
341 | MATCH_OPERATOR to recognize all the branch insns. */ | |
342 | ||
343 | int | |
344 | noov_compare_op (op, mode) | |
345 | register rtx op; | |
346 | enum machine_mode mode; | |
347 | { | |
348 | enum rtx_code code = GET_CODE (op); | |
349 | ||
350 | if (GET_RTX_CLASS (code) != '<') | |
351 | return 0; | |
352 | ||
353 | if (GET_MODE (XEXP (op, 0)) == CC_NOOVmode) | |
354 | /* These are the only branches which work with CC_NOOVmode. */ | |
355 | return (code == EQ || code == NE || code == GE || code == LT); | |
356 | return 1; | |
357 | } | |
358 | ||
359 | /* Return 1 if this is a SIGN_EXTEND or ZERO_EXTEND operation. */ | |
360 | ||
361 | int | |
362 | extend_op (op, mode) | |
363 | rtx op; | |
364 | enum machine_mode mode; | |
365 | { | |
366 | return GET_CODE (op) == SIGN_EXTEND || GET_CODE (op) == ZERO_EXTEND; | |
367 | } | |
368 | ||
369 | /* Return nonzero if OP is an operator of mode MODE which can set | |
370 | the condition codes explicitly. We do not include PLUS and MINUS | |
371 | because these require CC_NOOVmode, which we handle explicitly. */ | |
372 | ||
373 | int | |
374 | cc_arithop (op, mode) | |
375 | rtx op; | |
376 | enum machine_mode mode; | |
377 | { | |
378 | if (GET_CODE (op) == AND | |
379 | || GET_CODE (op) == IOR | |
380 | || GET_CODE (op) == XOR) | |
381 | return 1; | |
382 | ||
383 | return 0; | |
384 | } | |
385 | ||
386 | /* Return nonzero if OP is an operator of mode MODE which can bitwise | |
387 | complement its second operand and set the condition codes explicitly. */ | |
388 | ||
389 | int | |
390 | cc_arithopn (op, mode) | |
391 | rtx op; | |
392 | enum machine_mode mode; | |
393 | { | |
394 | /* XOR is not here because combine canonicalizes (xor (not ...) ...) | |
395 | and (xor ... (not ...)) to (not (xor ...)). */ | |
396 | return (GET_CODE (op) == AND | |
397 | || GET_CODE (op) == IOR); | |
398 | } | |
399 | \f | |
228b4037 JW |
400 | /* Return true if OP is a register, or is a CONST_INT that can fit in a 13 |
401 | bit immediate field. This is an acceptable SImode operand for most 3 | |
402 | address instructions. */ | |
ab835497 RK |
403 | |
404 | int | |
405 | arith_operand (op, mode) | |
406 | rtx op; | |
407 | enum machine_mode mode; | |
408 | { | |
409 | return (register_operand (op, mode) | |
410 | || (GET_CODE (op) == CONST_INT && SMALL_INT (op))); | |
411 | } | |
412 | ||
228b4037 JW |
413 | /* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that |
414 | can fit in a 13 bit immediate field. This is an acceptable DImode operand | |
415 | for most 3 address instructions. */ | |
ab835497 RK |
416 | |
417 | int | |
418 | arith_double_operand (op, mode) | |
419 | rtx op; | |
420 | enum machine_mode mode; | |
421 | { | |
422 | return (register_operand (op, mode) | |
423 | || (GET_CODE (op) == CONST_DOUBLE | |
424 | && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode) | |
425 | && (unsigned) (CONST_DOUBLE_LOW (op) + 0x1000) < 0x2000 | |
426 | && ((CONST_DOUBLE_HIGH (op) == -1 | |
427 | && (CONST_DOUBLE_LOW (op) & 0x1000) == 0x1000) | |
428 | || (CONST_DOUBLE_HIGH (op) == 0 | |
429 | && (CONST_DOUBLE_LOW (op) & 0x1000) == 0))) | |
430 | || (GET_CODE (op) == CONST_INT | |
431 | && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode) | |
432 | && (unsigned) (INTVAL (op) + 0x1000) < 0x2000)); | |
433 | } | |
434 | ||
435 | /* Return truth value of whether OP is a integer which fits the | |
228b4037 JW |
436 | range constraining immediate operands in most three-address insns, |
437 | which have a 13 bit immediate field. */ | |
ab835497 RK |
438 | |
439 | int | |
440 | small_int (op, mode) | |
441 | rtx op; | |
442 | enum machine_mode mode; | |
443 | { | |
444 | return (GET_CODE (op) == CONST_INT && SMALL_INT (op)); | |
445 | } | |
446 | ||
447 | /* Return truth value of statement that OP is a call-clobbered register. */ | |
448 | int | |
449 | clobbered_register (op, mode) | |
450 | rtx op; | |
451 | enum machine_mode mode; | |
452 | { | |
453 | return (GET_CODE (op) == REG && call_used_regs[REGNO (op)]); | |
454 | } | |
455 | \f | |
456 | /* X and Y are two things to compare using CODE. Emit the compare insn and | |
457 | return the rtx for register 0 in the proper mode. */ | |
458 | ||
459 | rtx | |
460 | gen_compare_reg (code, x, y) | |
461 | enum rtx_code code; | |
462 | rtx x, y; | |
463 | { | |
679655e6 | 464 | enum machine_mode mode = SELECT_CC_MODE (code, x, y); |
ab835497 RK |
465 | rtx cc_reg = gen_rtx (REG, mode, 0); |
466 | ||
467 | emit_insn (gen_rtx (SET, VOIDmode, cc_reg, | |
468 | gen_rtx (COMPARE, mode, x, y))); | |
469 | ||
470 | return cc_reg; | |
471 | } | |
472 | \f | |
473 | /* Return nonzero if a return peephole merging return with | |
474 | setting of output register is ok. */ | |
475 | int | |
476 | leaf_return_peephole_ok () | |
477 | { | |
478 | return (actual_fsize == 0); | |
479 | } | |
480 | ||
481 | /* Return nonzero if TRIAL can go into the function epilogue's | |
482 | delay slot. SLOT is the slot we are trying to fill. */ | |
483 | ||
484 | int | |
485 | eligible_for_epilogue_delay (trial, slot) | |
486 | rtx trial; | |
487 | int slot; | |
488 | { | |
ab835497 RK |
489 | rtx pat, src; |
490 | ||
491 | if (slot >= 1) | |
492 | return 0; | |
493 | if (GET_CODE (trial) != INSN | |
494 | || GET_CODE (PATTERN (trial)) != SET) | |
495 | return 0; | |
496 | if (get_attr_length (trial) != 1) | |
497 | return 0; | |
498 | ||
915f619f JW |
499 | /* In the case of a true leaf function, anything can go into the delay slot. |
500 | A delay slot only exists however if the frame size is zero, otherwise | |
501 | we will put an insn to adjust the stack after the return. */ | |
ab835497 RK |
502 | if (leaf_function) |
503 | { | |
504 | if (leaf_return_peephole_ok ()) | |
7c56249d | 505 | return (get_attr_in_uncond_branch_delay (trial) == IN_BRANCH_DELAY_TRUE); |
ab835497 RK |
506 | return 0; |
507 | } | |
508 | ||
509 | /* Otherwise, only operations which can be done in tandem with | |
510 | a `restore' insn can go into the delay slot. */ | |
511 | pat = PATTERN (trial); | |
512 | if (GET_CODE (SET_DEST (pat)) != REG | |
513 | || REGNO (SET_DEST (pat)) == 0 | |
915f619f JW |
514 | || REGNO (SET_DEST (pat)) >= 32 |
515 | || REGNO (SET_DEST (pat)) < 24) | |
ab835497 | 516 | return 0; |
915f619f | 517 | |
ab835497 RK |
518 | src = SET_SRC (pat); |
519 | if (arith_operand (src, GET_MODE (src))) | |
520 | return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (SImode); | |
521 | if (arith_double_operand (src, GET_MODE (src))) | |
522 | return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode); | |
523 | if (GET_CODE (src) == PLUS) | |
524 | { | |
525 | if (register_operand (XEXP (src, 0), SImode) | |
526 | && arith_operand (XEXP (src, 1), SImode)) | |
527 | return 1; | |
528 | if (register_operand (XEXP (src, 1), SImode) | |
529 | && arith_operand (XEXP (src, 0), SImode)) | |
530 | return 1; | |
531 | if (register_operand (XEXP (src, 0), DImode) | |
532 | && arith_double_operand (XEXP (src, 1), DImode)) | |
533 | return 1; | |
534 | if (register_operand (XEXP (src, 1), DImode) | |
535 | && arith_double_operand (XEXP (src, 0), DImode)) | |
536 | return 1; | |
537 | } | |
538 | if (GET_CODE (src) == MINUS | |
539 | && register_operand (XEXP (src, 0), SImode) | |
540 | && small_int (XEXP (src, 1), VOIDmode)) | |
541 | return 1; | |
542 | if (GET_CODE (src) == MINUS | |
543 | && register_operand (XEXP (src, 0), DImode) | |
544 | && !register_operand (XEXP (src, 1), DImode) | |
545 | && arith_double_operand (XEXP (src, 1), DImode)) | |
546 | return 1; | |
547 | return 0; | |
548 | } | |
549 | ||
550 | int | |
551 | short_branch (uid1, uid2) | |
552 | int uid1, uid2; | |
553 | { | |
554 | unsigned int delta = insn_addresses[uid1] - insn_addresses[uid2]; | |
555 | if (delta + 1024 < 2048) | |
556 | return 1; | |
557 | /* warning ("long branch, distance %d", delta); */ | |
558 | return 0; | |
559 | } | |
560 | ||
561 | /* Return non-zero if REG is not used after INSN. | |
562 | We assume REG is a reload reg, and therefore does | |
563 | not live past labels or calls or jumps. */ | |
564 | int | |
565 | reg_unused_after (reg, insn) | |
566 | rtx reg; | |
567 | rtx insn; | |
568 | { | |
569 | enum rtx_code code, prev_code = UNKNOWN; | |
570 | ||
571 | while (insn = NEXT_INSN (insn)) | |
572 | { | |
573 | if (prev_code == CALL_INSN && call_used_regs[REGNO (reg)]) | |
574 | return 1; | |
575 | ||
576 | code = GET_CODE (insn); | |
577 | if (GET_CODE (insn) == CODE_LABEL) | |
578 | return 1; | |
579 | ||
580 | if (GET_RTX_CLASS (code) == 'i') | |
581 | { | |
582 | rtx set = single_set (insn); | |
583 | int in_src = set && reg_overlap_mentioned_p (reg, SET_SRC (set)); | |
584 | if (set && in_src) | |
585 | return 0; | |
586 | if (set && reg_overlap_mentioned_p (reg, SET_DEST (set))) | |
587 | return 1; | |
588 | if (set == 0 && reg_overlap_mentioned_p (reg, PATTERN (insn))) | |
589 | return 0; | |
590 | } | |
591 | prev_code = code; | |
592 | } | |
593 | return 1; | |
594 | } | |
595 | \f | |
596 | /* Legitimize PIC addresses. If the address is already position-independent, | |
597 | we return ORIG. Newly generated position-independent addresses go into a | |
598 | reg. This is REG if non zero, otherwise we allocate register(s) as | |
599 | necessary. If this is called during reload, and we need a second temp | |
600 | register, then we use SCRATCH, which is provided via the | |
601 | SECONDARY_INPUT_RELOAD_CLASS mechanism. */ | |
602 | ||
603 | rtx | |
604 | legitimize_pic_address (orig, mode, reg, scratch) | |
605 | rtx orig; | |
606 | enum machine_mode mode; | |
607 | rtx reg, scratch; | |
608 | { | |
609 | if (GET_CODE (orig) == SYMBOL_REF) | |
610 | { | |
611 | rtx pic_ref, address; | |
612 | rtx insn; | |
613 | ||
614 | if (reg == 0) | |
615 | { | |
01c0e9dc | 616 | if (reload_in_progress || reload_completed) |
ab835497 RK |
617 | abort (); |
618 | else | |
619 | reg = gen_reg_rtx (Pmode); | |
620 | } | |
621 | ||
622 | if (flag_pic == 2) | |
623 | { | |
624 | /* If not during reload, allocate another temp reg here for loading | |
625 | in the address, so that these instructions can be optimized | |
626 | properly. */ | |
01c0e9dc JW |
627 | rtx temp_reg = ((reload_in_progress || reload_completed) |
628 | ? reg : gen_reg_rtx (Pmode)); | |
ab835497 | 629 | |
b4ac57ab RS |
630 | /* Must put the SYMBOL_REF inside an UNSPEC here so that cse |
631 | won't get confused into thinking that these two instructions | |
632 | are loading in the true address of the symbol. If in the | |
633 | future a PIC rtx exists, that should be used instead. */ | |
ab835497 | 634 | emit_insn (gen_rtx (SET, VOIDmode, temp_reg, |
b4ac57ab RS |
635 | gen_rtx (HIGH, Pmode, |
636 | gen_rtx (UNSPEC, Pmode, | |
637 | gen_rtvec (1, orig), | |
638 | 0)))); | |
ab835497 | 639 | emit_insn (gen_rtx (SET, VOIDmode, temp_reg, |
b4ac57ab RS |
640 | gen_rtx (LO_SUM, Pmode, temp_reg, |
641 | gen_rtx (UNSPEC, Pmode, | |
642 | gen_rtvec (1, orig), | |
643 | 0)))); | |
ab835497 RK |
644 | address = temp_reg; |
645 | } | |
646 | else | |
647 | address = orig; | |
648 | ||
649 | pic_ref = gen_rtx (MEM, Pmode, | |
650 | gen_rtx (PLUS, Pmode, | |
651 | pic_offset_table_rtx, address)); | |
652 | current_function_uses_pic_offset_table = 1; | |
653 | RTX_UNCHANGING_P (pic_ref) = 1; | |
654 | insn = emit_move_insn (reg, pic_ref); | |
655 | /* Put a REG_EQUAL note on this insn, so that it can be optimized | |
656 | by loop. */ | |
657 | REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_EQUAL, orig, | |
658 | REG_NOTES (insn)); | |
659 | return reg; | |
660 | } | |
661 | else if (GET_CODE (orig) == CONST) | |
662 | { | |
663 | rtx base, offset; | |
664 | ||
665 | if (GET_CODE (XEXP (orig, 0)) == PLUS | |
666 | && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx) | |
667 | return orig; | |
668 | ||
669 | if (reg == 0) | |
670 | { | |
01c0e9dc | 671 | if (reload_in_progress || reload_completed) |
ab835497 RK |
672 | abort (); |
673 | else | |
674 | reg = gen_reg_rtx (Pmode); | |
675 | } | |
676 | ||
677 | if (GET_CODE (XEXP (orig, 0)) == PLUS) | |
678 | { | |
679 | base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, | |
680 | reg, 0); | |
681 | offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode, | |
682 | base == reg ? 0 : reg, 0); | |
683 | } | |
684 | else | |
685 | abort (); | |
686 | ||
687 | if (GET_CODE (offset) == CONST_INT) | |
688 | { | |
689 | if (SMALL_INT (offset)) | |
690 | return plus_constant_for_output (base, INTVAL (offset)); | |
01c0e9dc | 691 | else if (! reload_in_progress && ! reload_completed) |
ab835497 RK |
692 | offset = force_reg (Pmode, offset); |
693 | /* We can't create any new registers during reload, so use the | |
694 | SCRATCH reg provided by the reload_insi pattern. */ | |
695 | else if (scratch) | |
696 | { | |
697 | emit_move_insn (scratch, offset); | |
698 | offset = scratch; | |
699 | } | |
700 | else | |
701 | /* If we reach here, then the SECONDARY_INPUT_RELOAD_CLASS | |
702 | macro needs to be adjusted so that a scratch reg is provided | |
703 | for this address. */ | |
704 | abort (); | |
705 | } | |
706 | return gen_rtx (PLUS, Pmode, base, offset); | |
707 | } | |
708 | else if (GET_CODE (orig) == LABEL_REF) | |
709 | current_function_uses_pic_offset_table = 1; | |
710 | ||
711 | return orig; | |
712 | } | |
713 | ||
714 | /* Set up PIC-specific rtl. This should not cause any insns | |
715 | to be emitted. */ | |
716 | ||
717 | void | |
718 | initialize_pic () | |
719 | { | |
720 | } | |
721 | ||
722 | /* Emit special PIC prologues and epilogues. */ | |
723 | ||
724 | void | |
725 | finalize_pic () | |
726 | { | |
727 | /* The table we use to reference PIC data. */ | |
728 | rtx global_offset_table; | |
729 | /* Labels to get the PC in the prologue of this function. */ | |
730 | rtx l1, l2; | |
731 | rtx seq; | |
732 | int orig_flag_pic = flag_pic; | |
733 | ||
734 | if (current_function_uses_pic_offset_table == 0) | |
735 | return; | |
736 | ||
737 | if (! flag_pic) | |
738 | abort (); | |
739 | ||
740 | flag_pic = 0; | |
741 | l1 = gen_label_rtx (); | |
742 | l2 = gen_label_rtx (); | |
743 | ||
744 | start_sequence (); | |
745 | ||
746 | emit_label (l1); | |
747 | /* Note that we pun calls and jumps here! */ | |
748 | emit_jump_insn (gen_rtx (PARALLEL, VOIDmode, | |
749 | gen_rtvec (2, | |
750 | gen_rtx (SET, VOIDmode, pc_rtx, gen_rtx (LABEL_REF, VOIDmode, l2)), | |
751 | gen_rtx (SET, VOIDmode, gen_rtx (REG, SImode, 15), gen_rtx (LABEL_REF, VOIDmode, l2))))); | |
752 | emit_label (l2); | |
753 | ||
754 | /* Initialize every time through, since we can't easily | |
755 | know this to be permanent. */ | |
c4eb2bd7 | 756 | global_offset_table = gen_rtx (SYMBOL_REF, Pmode, "_GLOBAL_OFFSET_TABLE_"); |
ab835497 RK |
757 | pic_pc_rtx = gen_rtx (CONST, Pmode, |
758 | gen_rtx (MINUS, Pmode, | |
759 | global_offset_table, | |
760 | gen_rtx (CONST, Pmode, | |
761 | gen_rtx (MINUS, Pmode, | |
762 | gen_rtx (LABEL_REF, VOIDmode, l1), | |
763 | pc_rtx)))); | |
764 | ||
765 | emit_insn (gen_rtx (SET, VOIDmode, pic_offset_table_rtx, | |
766 | gen_rtx (HIGH, Pmode, pic_pc_rtx))); | |
767 | emit_insn (gen_rtx (SET, VOIDmode, | |
768 | pic_offset_table_rtx, | |
769 | gen_rtx (LO_SUM, Pmode, | |
770 | pic_offset_table_rtx, pic_pc_rtx))); | |
771 | emit_insn (gen_rtx (SET, VOIDmode, | |
772 | pic_offset_table_rtx, | |
773 | gen_rtx (PLUS, Pmode, | |
774 | pic_offset_table_rtx, gen_rtx (REG, Pmode, 15)))); | |
775 | /* emit_insn (gen_rtx (ASM_INPUT, VOIDmode, "!#PROLOGUE# 1")); */ | |
776 | LABEL_PRESERVE_P (l1) = 1; | |
777 | LABEL_PRESERVE_P (l2) = 1; | |
778 | flag_pic = orig_flag_pic; | |
779 | ||
780 | seq = gen_sequence (); | |
781 | end_sequence (); | |
782 | emit_insn_after (seq, get_insns ()); | |
783 | ||
784 | /* Need to emit this whether or not we obey regdecls, | |
785 | since setjmp/longjmp can cause life info to screw up. */ | |
786 | emit_insn (gen_rtx (USE, VOIDmode, pic_offset_table_rtx)); | |
787 | } | |
788 | \f | |
789 | /* For the SPARC, REG and REG+CONST is cost 0, REG+REG is cost 1, | |
790 | and addresses involving symbolic constants are cost 2. | |
791 | ||
792 | We make REG+REG slightly more expensive because it might keep | |
793 | a register live for longer than we might like. | |
794 | ||
795 | PIC addresses are very expensive. | |
796 | ||
797 | It is no coincidence that this has the same structure | |
798 | as GO_IF_LEGITIMATE_ADDRESS. */ | |
799 | int | |
800 | sparc_address_cost (X) | |
801 | rtx X; | |
802 | { | |
803 | #if 0 | |
804 | /* Handled before calling here. */ | |
805 | if (GET_CODE (X) == REG) | |
806 | { return 1; } | |
807 | #endif | |
808 | if (GET_CODE (X) == PLUS) | |
809 | { | |
810 | if (GET_CODE (XEXP (X, 0)) == REG | |
811 | && GET_CODE (XEXP (X, 1)) == REG) | |
812 | return 2; | |
813 | return 1; | |
814 | } | |
815 | else if (GET_CODE (X) == LO_SUM) | |
816 | return 1; | |
817 | else if (GET_CODE (X) == HIGH) | |
818 | return 2; | |
819 | return 4; | |
820 | } | |
821 | \f | |
822 | /* Emit insns to move operands[1] into operands[0]. | |
823 | ||
824 | Return 1 if we have written out everything that needs to be done to | |
825 | do the move. Otherwise, return 0 and the caller will emit the move | |
826 | normally. | |
827 | ||
828 | SCRATCH_REG if non zero can be used as a scratch register for the move | |
829 | operation. It is provided by a SECONDARY_RELOAD_* macro if needed. */ | |
830 | ||
831 | int | |
832 | emit_move_sequence (operands, mode, scratch_reg) | |
833 | rtx *operands; | |
834 | enum machine_mode mode; | |
835 | rtx scratch_reg; | |
836 | { | |
837 | register rtx operand0 = operands[0]; | |
838 | register rtx operand1 = operands[1]; | |
839 | ||
840 | /* Handle most common case first: storing into a register. */ | |
841 | if (register_operand (operand0, mode)) | |
842 | { | |
843 | if (register_operand (operand1, mode) | |
844 | || (GET_CODE (operand1) == CONST_INT && SMALL_INT (operand1)) | |
845 | || (GET_CODE (operand1) == CONST_DOUBLE | |
846 | && arith_double_operand (operand1, DImode)) | |
847 | || (GET_CODE (operand1) == HIGH && GET_MODE (operand1) != DImode) | |
848 | /* Only `general_operands' can come here, so MEM is ok. */ | |
849 | || GET_CODE (operand1) == MEM) | |
850 | { | |
851 | /* Run this case quickly. */ | |
852 | emit_insn (gen_rtx (SET, VOIDmode, operand0, operand1)); | |
853 | return 1; | |
854 | } | |
855 | } | |
856 | else if (GET_CODE (operand0) == MEM) | |
857 | { | |
858 | if (register_operand (operand1, mode) || operand1 == const0_rtx) | |
859 | { | |
860 | /* Run this case quickly. */ | |
861 | emit_insn (gen_rtx (SET, VOIDmode, operand0, operand1)); | |
862 | return 1; | |
863 | } | |
864 | if (! reload_in_progress) | |
865 | { | |
866 | operands[0] = validize_mem (operand0); | |
867 | operands[1] = operand1 = force_reg (mode, operand1); | |
868 | } | |
869 | } | |
870 | ||
871 | /* Simplify the source if we need to. Must handle DImode HIGH operators | |
872 | here because such a move needs a clobber added. */ | |
873 | if ((GET_CODE (operand1) != HIGH && immediate_operand (operand1, mode)) | |
874 | || (GET_CODE (operand1) == HIGH && GET_MODE (operand1) == DImode)) | |
875 | { | |
876 | if (flag_pic && symbolic_operand (operand1, mode)) | |
877 | { | |
878 | rtx temp_reg = reload_in_progress ? operand0 : 0; | |
879 | ||
880 | operands[1] = legitimize_pic_address (operand1, mode, temp_reg, | |
881 | scratch_reg); | |
882 | } | |
883 | else if (GET_CODE (operand1) == CONST_INT | |
884 | ? (! SMALL_INT (operand1) | |
885 | && (INTVAL (operand1) & 0x3ff) != 0) | |
886 | : (GET_CODE (operand1) == CONST_DOUBLE | |
887 | ? ! arith_double_operand (operand1, DImode) | |
888 | : 1)) | |
889 | { | |
890 | /* For DImode values, temp must be operand0 because of the way | |
891 | HI and LO_SUM work. The LO_SUM operator only copies half of | |
892 | the LSW from the dest of the HI operator. If the LO_SUM dest is | |
893 | not the same as the HI dest, then the MSW of the LO_SUM dest will | |
894 | never be set. | |
895 | ||
896 | ??? The real problem here is that the ...(HI:DImode pattern emits | |
897 | multiple instructions, and the ...(LO_SUM:DImode pattern emits | |
898 | one instruction. This fails, because the compiler assumes that | |
899 | LO_SUM copies all bits of the first operand to its dest. Better | |
900 | would be to have the HI pattern emit one instruction and the | |
901 | LO_SUM pattern multiple instructions. Even better would be | |
902 | to use four rtl insns. */ | |
903 | rtx temp = ((reload_in_progress || mode == DImode) | |
904 | ? operand0 : gen_reg_rtx (mode)); | |
905 | ||
906 | emit_insn (gen_rtx (SET, VOIDmode, temp, | |
907 | gen_rtx (HIGH, mode, operand1))); | |
908 | operands[1] = gen_rtx (LO_SUM, mode, temp, operand1); | |
909 | } | |
910 | } | |
911 | ||
912 | if (GET_CODE (operand1) == LABEL_REF && flag_pic) | |
913 | { | |
914 | /* The procedure for doing this involves using a call instruction to | |
915 | get the pc into o7. We need to indicate this explicitly because | |
916 | the tablejump pattern assumes that it can use this value also. */ | |
917 | emit_insn (gen_rtx (PARALLEL, VOIDmode, | |
918 | gen_rtvec (2, | |
919 | gen_rtx (SET, VOIDmode, operand0, | |
920 | operand1), | |
921 | gen_rtx (SET, VOIDmode, | |
922 | gen_rtx (REG, mode, 15), | |
923 | pc_rtx)))); | |
924 | return 1; | |
925 | } | |
926 | ||
927 | /* Now have insn-emit do whatever it normally does. */ | |
928 | return 0; | |
929 | } | |
930 | \f | |
931 | /* Return the best assembler insn template | |
932 | for moving operands[1] into operands[0] as a fullword. */ | |
933 | ||
934 | char * | |
935 | singlemove_string (operands) | |
936 | rtx *operands; | |
937 | { | |
938 | if (GET_CODE (operands[0]) == MEM) | |
939 | { | |
940 | if (GET_CODE (operands[1]) != MEM) | |
941 | return "st %r1,%0"; | |
942 | else | |
943 | abort (); | |
944 | } | |
2b9a9aea | 945 | else if (GET_CODE (operands[1]) == MEM) |
ab835497 | 946 | return "ld %1,%0"; |
2b9a9aea JW |
947 | else if (GET_CODE (operands[1]) == CONST_DOUBLE) |
948 | { | |
949 | int i; | |
950 | union real_extract u; | |
951 | union float_extract { float f; int i; } v; | |
952 | ||
953 | /* Must be SFmode, otherwise this doesn't make sense. */ | |
954 | if (GET_MODE (operands[1]) != SFmode) | |
955 | abort (); | |
956 | ||
957 | bcopy (&CONST_DOUBLE_LOW (operands[1]), &u, sizeof u); | |
958 | v.f = REAL_VALUE_TRUNCATE (SFmode, u.d); | |
959 | i = v.i; | |
960 | ||
961 | operands[1] = gen_rtx (CONST_INT, VOIDmode, i); | |
962 | ||
963 | if (CONST_OK_FOR_LETTER_P (i, 'I')) | |
964 | return "mov %1,%0"; | |
965 | else if ((i & 0x000003FF) != 0) | |
966 | return "sethi %%hi(%a1),%0\n\tor %0,%%lo(%a1),%0"; | |
967 | else | |
968 | return "sethi %%hi(%a1),%0"; | |
969 | } | |
970 | else if (GET_CODE (operands[1]) == CONST_INT | |
971 | && ! CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'I')) | |
ab835497 RK |
972 | { |
973 | int i = INTVAL (operands[1]); | |
974 | ||
915f619f | 975 | /* If all low order 10 bits are clear, then we only need a single |
ab835497 | 976 | sethi insn to load the constant. */ |
915f619f | 977 | if ((i & 0x000003FF) != 0) |
ab835497 RK |
978 | return "sethi %%hi(%a1),%0\n\tor %0,%%lo(%a1),%0"; |
979 | else | |
980 | return "sethi %%hi(%a1),%0"; | |
981 | } | |
2b9a9aea | 982 | /* Operand 1 must be a register, or a 'I' type CONST_INT. */ |
ab835497 RK |
983 | return "mov %1,%0"; |
984 | } | |
985 | \f | |
795068a4 JW |
986 | /* Return non-zero if it is OK to assume that the given memory operand is |
987 | aligned at least to a 8-byte boundary. This should only be called | |
988 | for memory accesses whose size is 8 bytes or larger. */ | |
989 | ||
7c56249d | 990 | int |
795068a4 JW |
991 | mem_aligned_8 (mem) |
992 | register rtx mem; | |
993 | { | |
994 | register rtx addr; | |
995 | register rtx base; | |
996 | register rtx offset; | |
997 | ||
998 | if (GET_CODE (mem) != MEM) | |
7c56249d | 999 | return 0; /* It's gotta be a MEM! */ |
795068a4 JW |
1000 | |
1001 | addr = XEXP (mem, 0); | |
1002 | ||
795068a4 | 1003 | /* Now that all misaligned double parms are copied on function entry, |
1934ceca JW |
1004 | we can assume any 64-bit object is 64-bit aligned except those which |
1005 | are at unaligned offsets from the stack or frame pointer. If the | |
1006 | TARGET_UNALIGNED_DOUBLES switch is given, we do not make this | |
1007 | assumption. */ | |
795068a4 JW |
1008 | |
1009 | /* See what register we use in the address. */ | |
1010 | base = 0; | |
1011 | if (GET_CODE (addr) == PLUS) | |
1012 | { | |
1013 | if (GET_CODE (XEXP (addr, 0)) == REG | |
1014 | && GET_CODE (XEXP (addr, 1)) == CONST_INT) | |
1015 | { | |
1016 | base = XEXP (addr, 0); | |
1017 | offset = XEXP (addr, 1); | |
1018 | } | |
1019 | } | |
1020 | else if (GET_CODE (addr) == REG) | |
1021 | { | |
1022 | base = addr; | |
1023 | offset = const0_rtx; | |
1024 | } | |
1025 | ||
1026 | /* If it's the stack or frame pointer, check offset alignment. | |
2296cba3 | 1027 | We can have improper alignment in the function entry code. */ |
795068a4 JW |
1028 | if (base |
1029 | && (REGNO (base) == FRAME_POINTER_REGNUM | |
1030 | || REGNO (base) == STACK_POINTER_REGNUM)) | |
1031 | { | |
1032 | if ((INTVAL (offset) & 0x7) == 0) | |
1033 | return 1; | |
1034 | } | |
1934ceca JW |
1035 | /* Anything else we know is properly aligned unless TARGET_UNALIGNED_DOUBLES |
1036 | is true, in which case we can only assume that an access is aligned if | |
1037 | it is to an aggregate, it is to a constant address, or the address | |
1038 | involves a LO_SUM. */ | |
1039 | else if (! TARGET_UNALIGNED_DOUBLES || MEM_IN_STRUCT_P (mem) | |
1040 | || CONSTANT_P (addr) || GET_CODE (addr) == LO_SUM) | |
795068a4 | 1041 | return 1; |
795068a4 JW |
1042 | |
1043 | /* An obviously unaligned address. */ | |
1044 | return 0; | |
1045 | } | |
1046 | ||
1047 | enum optype { REGOP, OFFSOP, MEMOP, PUSHOP, POPOP, CNSTOP, RNDOP }; | |
1048 | ||
ab835497 | 1049 | /* Output assembler code to perform a doubleword move insn |
795068a4 JW |
1050 | with operands OPERANDS. This is very similar to the following |
1051 | output_move_quad function. */ | |
ab835497 RK |
1052 | |
1053 | char * | |
1054 | output_move_double (operands) | |
1055 | rtx *operands; | |
1056 | { | |
795068a4 JW |
1057 | register rtx op0 = operands[0]; |
1058 | register rtx op1 = operands[1]; | |
1059 | register enum optype optype0; | |
1060 | register enum optype optype1; | |
ab835497 | 1061 | rtx latehalf[2]; |
795068a4 JW |
1062 | rtx addreg0 = 0; |
1063 | rtx addreg1 = 0; | |
3b76513a | 1064 | int highest_first = 0; |
ab835497 RK |
1065 | |
1066 | /* First classify both operands. */ | |
1067 | ||
795068a4 | 1068 | if (REG_P (op0)) |
ab835497 | 1069 | optype0 = REGOP; |
795068a4 | 1070 | else if (offsettable_memref_p (op0)) |
ab835497 | 1071 | optype0 = OFFSOP; |
795068a4 | 1072 | else if (GET_CODE (op0) == MEM) |
ab835497 RK |
1073 | optype0 = MEMOP; |
1074 | else | |
1075 | optype0 = RNDOP; | |
1076 | ||
795068a4 | 1077 | if (REG_P (op1)) |
ab835497 | 1078 | optype1 = REGOP; |
795068a4 | 1079 | else if (CONSTANT_P (op1)) |
ab835497 | 1080 | optype1 = CNSTOP; |
795068a4 | 1081 | else if (offsettable_memref_p (op1)) |
ab835497 | 1082 | optype1 = OFFSOP; |
795068a4 | 1083 | else if (GET_CODE (op1) == MEM) |
ab835497 RK |
1084 | optype1 = MEMOP; |
1085 | else | |
1086 | optype1 = RNDOP; | |
1087 | ||
1088 | /* Check for the cases that the operand constraints are not | |
1089 | supposed to allow to happen. Abort if we get one, | |
1090 | because generating code for these cases is painful. */ | |
1091 | ||
795068a4 JW |
1092 | if (optype0 == RNDOP || optype1 == RNDOP |
1093 | || (optype0 == MEM && optype1 == MEM)) | |
ab835497 RK |
1094 | abort (); |
1095 | ||
1096 | /* If an operand is an unoffsettable memory ref, find a register | |
1097 | we can increment temporarily to make it refer to the second word. */ | |
1098 | ||
1099 | if (optype0 == MEMOP) | |
795068a4 | 1100 | addreg0 = find_addr_reg (XEXP (op0, 0)); |
ab835497 RK |
1101 | |
1102 | if (optype1 == MEMOP) | |
795068a4 | 1103 | addreg1 = find_addr_reg (XEXP (op1, 0)); |
ab835497 RK |
1104 | |
1105 | /* Ok, we can do one word at a time. | |
795068a4 | 1106 | Set up in LATEHALF the operands to use for the |
ab835497 RK |
1107 | high-numbered (least significant) word and in some cases alter the |
1108 | operands in OPERANDS to be suitable for the low-numbered word. */ | |
1109 | ||
1110 | if (optype0 == REGOP) | |
795068a4 | 1111 | latehalf[0] = gen_rtx (REG, SImode, REGNO (op0) + 1); |
ab835497 | 1112 | else if (optype0 == OFFSOP) |
795068a4 | 1113 | latehalf[0] = adj_offsettable_operand (op0, 4); |
ab835497 | 1114 | else |
795068a4 | 1115 | latehalf[0] = op0; |
ab835497 RK |
1116 | |
1117 | if (optype1 == REGOP) | |
795068a4 | 1118 | latehalf[1] = gen_rtx (REG, SImode, REGNO (op1) + 1); |
ab835497 | 1119 | else if (optype1 == OFFSOP) |
795068a4 | 1120 | latehalf[1] = adj_offsettable_operand (op1, 4); |
ab835497 | 1121 | else if (optype1 == CNSTOP) |
795068a4 | 1122 | split_double (op1, &operands[1], &latehalf[1]); |
ab835497 | 1123 | else |
795068a4 | 1124 | latehalf[1] = op1; |
ab835497 | 1125 | |
795068a4 JW |
1126 | /* Easy case: try moving both words at once. Check for moving between |
1127 | an even/odd register pair and a memory location. */ | |
ab835497 | 1128 | if ((optype0 == REGOP && optype1 != REGOP && optype1 != CNSTOP |
795068a4 | 1129 | && (REGNO (op0) & 1) == 0) |
ab835497 | 1130 | || (optype0 != REGOP && optype0 != CNSTOP && optype1 == REGOP |
795068a4 | 1131 | && (REGNO (op1) & 1) == 0)) |
ab835497 | 1132 | { |
795068a4 | 1133 | register rtx mem; |
bc961ed7 RS |
1134 | |
1135 | if (optype0 == REGOP) | |
795068a4 | 1136 | mem = op1; |
bc961ed7 | 1137 | else |
795068a4 | 1138 | mem = op0; |
bc961ed7 | 1139 | |
795068a4 JW |
1140 | if (mem_aligned_8 (mem)) |
1141 | return (mem == op1 ? "ldd %1,%0" : "std %1,%0"); | |
ab835497 RK |
1142 | } |
1143 | ||
795068a4 JW |
1144 | /* If the first move would clobber the source of the second one, |
1145 | do them in the other order. */ | |
1146 | ||
1147 | /* Overlapping registers. */ | |
ab835497 | 1148 | if (optype0 == REGOP && optype1 == REGOP |
795068a4 | 1149 | && REGNO (op0) == REGNO (latehalf[1])) |
ab835497 | 1150 | { |
ab835497 RK |
1151 | /* Do that word. */ |
1152 | output_asm_insn (singlemove_string (latehalf), latehalf); | |
ab835497 RK |
1153 | /* Do low-numbered word. */ |
1154 | return singlemove_string (operands); | |
1155 | } | |
795068a4 | 1156 | /* Loading into a register which overlaps a register used in the address. */ |
ab835497 | 1157 | else if (optype0 == REGOP && optype1 != REGOP |
795068a4 | 1158 | && reg_overlap_mentioned_p (op0, op1)) |
ab835497 | 1159 | { |
bdec790c RS |
1160 | if (reg_mentioned_p (op0, XEXP (op1, 0)) |
1161 | && reg_mentioned_p (latehalf[0], XEXP (op1, 0))) | |
1162 | { | |
1163 | /* If both halves of dest are used in the src memory address, | |
1164 | add the two regs and put them in the low reg (op0). | |
1165 | Then it works to load latehalf first. */ | |
1166 | rtx xops[2]; | |
1167 | xops[0] = latehalf[0]; | |
1168 | xops[1] = op0; | |
1169 | output_asm_insn ("add %1,%0,%1", xops); | |
3b76513a | 1170 | operands[1] = gen_rtx (MEM, DImode, op0); |
bdec790c | 1171 | latehalf[1] = adj_offsettable_operand (operands[1], 4); |
3b76513a | 1172 | addreg1 = 0; |
bdec790c | 1173 | } |
ab835497 | 1174 | /* Do the late half first. */ |
3b76513a | 1175 | highest_first = 1; |
ab835497 RK |
1176 | } |
1177 | ||
3b76513a RS |
1178 | /* Normal case: do the two words, low-numbered first. |
1179 | Overlap case (highest_first set): do high-numbered word first. */ | |
ab835497 | 1180 | |
3b76513a RS |
1181 | if (! highest_first) |
1182 | output_asm_insn (singlemove_string (operands), operands); | |
ab835497 RK |
1183 | |
1184 | /* Make any unoffsettable addresses point at high-numbered word. */ | |
1185 | if (addreg0) | |
1186 | output_asm_insn ("add %0,0x4,%0", &addreg0); | |
1187 | if (addreg1) | |
1188 | output_asm_insn ("add %0,0x4,%0", &addreg1); | |
1189 | ||
1190 | /* Do that word. */ | |
1191 | output_asm_insn (singlemove_string (latehalf), latehalf); | |
1192 | ||
1193 | /* Undo the adds we just did. */ | |
1194 | if (addreg0) | |
1195 | output_asm_insn ("add %0,-0x4,%0", &addreg0); | |
1196 | if (addreg1) | |
1197 | output_asm_insn ("add %0,-0x4,%0", &addreg1); | |
1198 | ||
3b76513a RS |
1199 | if (highest_first) |
1200 | output_asm_insn (singlemove_string (operands), operands); | |
1201 | ||
ab835497 RK |
1202 | return ""; |
1203 | } | |
795068a4 JW |
1204 | |
1205 | /* Output assembler code to perform a quadword move insn | |
2296cba3 | 1206 | with operands OPERANDS. This is very similar to the preceding |
795068a4 JW |
1207 | output_move_double function. */ |
1208 | ||
1209 | char * | |
1210 | output_move_quad (operands) | |
1211 | rtx *operands; | |
1212 | { | |
1213 | register rtx op0 = operands[0]; | |
1214 | register rtx op1 = operands[1]; | |
1215 | register enum optype optype0; | |
1216 | register enum optype optype1; | |
1217 | rtx wordpart[4][2]; | |
1218 | rtx addreg0 = 0; | |
1219 | rtx addreg1 = 0; | |
1220 | ||
1221 | /* First classify both operands. */ | |
1222 | ||
1223 | if (REG_P (op0)) | |
1224 | optype0 = REGOP; | |
1225 | else if (offsettable_memref_p (op0)) | |
1226 | optype0 = OFFSOP; | |
1227 | else if (GET_CODE (op0) == MEM) | |
1228 | optype0 = MEMOP; | |
1229 | else | |
1230 | optype0 = RNDOP; | |
1231 | ||
1232 | if (REG_P (op1)) | |
1233 | optype1 = REGOP; | |
1234 | else if (CONSTANT_P (op1)) | |
1235 | optype1 = CNSTOP; | |
1236 | else if (offsettable_memref_p (op1)) | |
1237 | optype1 = OFFSOP; | |
1238 | else if (GET_CODE (op1) == MEM) | |
1239 | optype1 = MEMOP; | |
1240 | else | |
1241 | optype1 = RNDOP; | |
1242 | ||
1243 | /* Check for the cases that the operand constraints are not | |
1244 | supposed to allow to happen. Abort if we get one, | |
1245 | because generating code for these cases is painful. */ | |
1246 | ||
1247 | if (optype0 == RNDOP || optype1 == RNDOP | |
1248 | || (optype0 == MEM && optype1 == MEM)) | |
1249 | abort (); | |
1250 | ||
1251 | /* If an operand is an unoffsettable memory ref, find a register | |
1252 | we can increment temporarily to make it refer to the later words. */ | |
1253 | ||
1254 | if (optype0 == MEMOP) | |
1255 | addreg0 = find_addr_reg (XEXP (op0, 0)); | |
1256 | ||
1257 | if (optype1 == MEMOP) | |
1258 | addreg1 = find_addr_reg (XEXP (op1, 0)); | |
1259 | ||
1260 | /* Ok, we can do one word at a time. | |
1261 | Set up in wordpart the operands to use for each word of the arguments. */ | |
1262 | ||
1263 | if (optype0 == REGOP) | |
1264 | { | |
1265 | wordpart[0][0] = gen_rtx (REG, SImode, REGNO (op0) + 0); | |
1266 | wordpart[1][0] = gen_rtx (REG, SImode, REGNO (op0) + 1); | |
1267 | wordpart[2][0] = gen_rtx (REG, SImode, REGNO (op0) + 2); | |
1268 | wordpart[3][0] = gen_rtx (REG, SImode, REGNO (op0) + 3); | |
1269 | } | |
1270 | else if (optype0 == OFFSOP) | |
1271 | { | |
1272 | wordpart[0][0] = adj_offsettable_operand (op0, 0); | |
1273 | wordpart[1][0] = adj_offsettable_operand (op0, 4); | |
1274 | wordpart[2][0] = adj_offsettable_operand (op0, 8); | |
1275 | wordpart[3][0] = adj_offsettable_operand (op0, 12); | |
1276 | } | |
1277 | else | |
1278 | { | |
1279 | wordpart[0][0] = op0; | |
1280 | wordpart[1][0] = op0; | |
1281 | wordpart[2][0] = op0; | |
1282 | wordpart[3][0] = op0; | |
1283 | } | |
1284 | ||
1285 | if (optype1 == REGOP) | |
1286 | { | |
1287 | wordpart[0][1] = gen_rtx (REG, SImode, REGNO (op1) + 0); | |
1288 | wordpart[1][1] = gen_rtx (REG, SImode, REGNO (op1) + 1); | |
1289 | wordpart[2][1] = gen_rtx (REG, SImode, REGNO (op1) + 2); | |
1290 | wordpart[3][1] = gen_rtx (REG, SImode, REGNO (op1) + 3); | |
1291 | } | |
1292 | else if (optype1 == OFFSOP) | |
1293 | { | |
1294 | wordpart[0][1] = adj_offsettable_operand (op1, 0); | |
1295 | wordpart[1][1] = adj_offsettable_operand (op1, 4); | |
1296 | wordpart[2][1] = adj_offsettable_operand (op1, 8); | |
1297 | wordpart[3][1] = adj_offsettable_operand (op1, 12); | |
1298 | } | |
1299 | else if (optype1 == CNSTOP) | |
1300 | { | |
61a66555 JW |
1301 | REAL_VALUE_TYPE r; |
1302 | long l[4]; | |
1303 | ||
1304 | /* This only works for TFmode floating point constants. */ | |
1305 | if (GET_CODE (op1) != CONST_DOUBLE || GET_MODE (op1) != TFmode) | |
1306 | abort (); | |
1307 | ||
1308 | REAL_VALUE_FROM_CONST_DOUBLE (r, op1); | |
1309 | REAL_VALUE_TO_TARGET_LONG_DOUBLE (r, l); | |
1310 | ||
1311 | wordpart[0][1] = GEN_INT (l[0]); | |
1312 | wordpart[1][1] = GEN_INT (l[1]); | |
1313 | wordpart[2][1] = GEN_INT (l[2]); | |
1314 | wordpart[3][1] = GEN_INT (l[3]); | |
795068a4 JW |
1315 | } |
1316 | else | |
1317 | { | |
1318 | wordpart[0][1] = op1; | |
1319 | wordpart[1][1] = op1; | |
1320 | wordpart[2][1] = op1; | |
1321 | wordpart[3][1] = op1; | |
1322 | } | |
1323 | ||
1324 | /* Easy case: try moving the quad as two pairs. Check for moving between | |
1325 | an even/odd register pair and a memory location. */ | |
1326 | /* ??? Should also handle the case of non-offsettable addresses here. | |
1327 | We can at least do the first pair as a ldd/std, and then do the third | |
1328 | and fourth words individually. */ | |
1329 | if ((optype0 == REGOP && optype1 == OFFSOP && (REGNO (op0) & 1) == 0) | |
1330 | || (optype0 == OFFSOP && optype1 == REGOP && (REGNO (op1) & 1) == 0)) | |
1331 | { | |
1332 | rtx mem; | |
1333 | ||
1334 | if (optype0 == REGOP) | |
1335 | mem = op1; | |
1336 | else | |
1337 | mem = op0; | |
1338 | ||
1339 | if (mem_aligned_8 (mem)) | |
1340 | { | |
1341 | operands[2] = adj_offsettable_operand (mem, 8); | |
1342 | if (mem == op1) | |
1343 | return "ldd %1,%0;ldd %2,%S0"; | |
1344 | else | |
1345 | return "std %1,%0;std %S1,%2"; | |
1346 | } | |
1347 | } | |
1348 | ||
1349 | /* If the first move would clobber the source of the second one, | |
1350 | do them in the other order. */ | |
1351 | ||
1352 | /* Overlapping registers. */ | |
1353 | if (optype0 == REGOP && optype1 == REGOP | |
1354 | && (REGNO (op0) == REGNO (wordpart[1][3]) | |
1355 | || REGNO (op0) == REGNO (wordpart[1][2]) | |
1356 | || REGNO (op0) == REGNO (wordpart[1][1]))) | |
1357 | { | |
1358 | /* Do fourth word. */ | |
1359 | output_asm_insn (singlemove_string (wordpart[3]), wordpart[3]); | |
1360 | /* Do the third word. */ | |
1361 | output_asm_insn (singlemove_string (wordpart[2]), wordpart[2]); | |
1362 | /* Do the second word. */ | |
1363 | output_asm_insn (singlemove_string (wordpart[1]), wordpart[1]); | |
1364 | /* Do lowest-numbered word. */ | |
1365 | return singlemove_string (wordpart[0]); | |
1366 | } | |
1367 | /* Loading into a register which overlaps a register used in the address. */ | |
1368 | if (optype0 == REGOP && optype1 != REGOP | |
1369 | && reg_overlap_mentioned_p (op0, op1)) | |
1370 | { | |
1371 | /* ??? Not implemented yet. This is a bit complicated, because we | |
1372 | must load which ever part overlaps the address last. If the address | |
1373 | is a double-reg address, then there are two parts which need to | |
1374 | be done last, which is impossible. We would need a scratch register | |
1375 | in that case. */ | |
1376 | abort (); | |
1377 | } | |
1378 | ||
1379 | /* Normal case: move the four words in lowest to higest address order. */ | |
1380 | ||
1381 | output_asm_insn (singlemove_string (wordpart[0]), wordpart[0]); | |
1382 | ||
1383 | /* Make any unoffsettable addresses point at the second word. */ | |
1384 | if (addreg0) | |
1385 | output_asm_insn ("add %0,0x4,%0", &addreg0); | |
1386 | if (addreg1) | |
1387 | output_asm_insn ("add %0,0x4,%0", &addreg1); | |
1388 | ||
1389 | /* Do the second word. */ | |
1390 | output_asm_insn (singlemove_string (wordpart[1]), wordpart[1]); | |
1391 | ||
1392 | /* Make any unoffsettable addresses point at the third word. */ | |
1393 | if (addreg0) | |
1394 | output_asm_insn ("add %0,0x4,%0", &addreg0); | |
1395 | if (addreg1) | |
1396 | output_asm_insn ("add %0,0x4,%0", &addreg1); | |
1397 | ||
1398 | /* Do the third word. */ | |
1399 | output_asm_insn (singlemove_string (wordpart[2]), wordpart[2]); | |
1400 | ||
1401 | /* Make any unoffsettable addresses point at the fourth word. */ | |
1402 | if (addreg0) | |
1403 | output_asm_insn ("add %0,0x4,%0", &addreg0); | |
1404 | if (addreg1) | |
1405 | output_asm_insn ("add %0,0x4,%0", &addreg1); | |
1406 | ||
1407 | /* Do the fourth word. */ | |
1408 | output_asm_insn (singlemove_string (wordpart[3]), wordpart[3]); | |
1409 | ||
1410 | /* Undo the adds we just did. */ | |
1411 | if (addreg0) | |
1412 | output_asm_insn ("add %0,-0xc,%0", &addreg0); | |
1413 | if (addreg1) | |
1414 | output_asm_insn ("add %0,-0xc,%0", &addreg1); | |
1415 | ||
1416 | return ""; | |
1417 | } | |
ab835497 | 1418 | \f |
795068a4 | 1419 | /* Output assembler code to perform a doubleword move insn with operands |
a3ee5899 JW |
1420 | OPERANDS, one of which must be a floating point register. */ |
1421 | ||
ab835497 RK |
1422 | char * |
1423 | output_fp_move_double (operands) | |
1424 | rtx *operands; | |
1425 | { | |
ab835497 RK |
1426 | if (FP_REG_P (operands[0])) |
1427 | { | |
1428 | if (FP_REG_P (operands[1])) | |
1429 | return "fmovs %1,%0\n\tfmovs %R1,%R0"; | |
a3ee5899 | 1430 | else if (GET_CODE (operands[1]) == REG) |
019c2b24 | 1431 | abort (); |
a3ee5899 JW |
1432 | else |
1433 | return output_move_double (operands); | |
ab835497 RK |
1434 | } |
1435 | else if (FP_REG_P (operands[1])) | |
1436 | { | |
1437 | if (GET_CODE (operands[0]) == REG) | |
019c2b24 | 1438 | abort (); |
a3ee5899 JW |
1439 | else |
1440 | return output_move_double (operands); | |
ab835497 RK |
1441 | } |
1442 | else abort (); | |
1443 | } | |
795068a4 JW |
1444 | |
1445 | /* Output assembler code to perform a quadword move insn with operands | |
1446 | OPERANDS, one of which must be a floating point register. */ | |
1447 | ||
1448 | char * | |
1449 | output_fp_move_quad (operands) | |
1450 | rtx *operands; | |
1451 | { | |
1452 | register rtx op0 = operands[0]; | |
1453 | register rtx op1 = operands[1]; | |
795068a4 JW |
1454 | |
1455 | if (FP_REG_P (op0)) | |
1456 | { | |
1457 | if (FP_REG_P (op1)) | |
1458 | return "fmovs %1,%0\n\tfmovs %R1,%R0\n\tfmovs %S1,%S0\n\tfmovs %T1,%T0"; | |
019c2b24 JW |
1459 | else if (GET_CODE (op1) == REG) |
1460 | abort (); | |
795068a4 JW |
1461 | else |
1462 | return output_move_quad (operands); | |
1463 | } | |
1464 | else if (FP_REG_P (op1)) | |
1465 | { | |
1466 | if (GET_CODE (op0) == REG) | |
019c2b24 | 1467 | abort (); |
795068a4 JW |
1468 | else |
1469 | return output_move_quad (operands); | |
1470 | } | |
1471 | else | |
1472 | abort (); | |
1473 | } | |
ab835497 RK |
1474 | \f |
1475 | /* Return a REG that occurs in ADDR with coefficient 1. | |
1476 | ADDR can be effectively incremented by incrementing REG. */ | |
1477 | ||
1478 | static rtx | |
1479 | find_addr_reg (addr) | |
1480 | rtx addr; | |
1481 | { | |
1482 | while (GET_CODE (addr) == PLUS) | |
1483 | { | |
1484 | /* We absolutely can not fudge the frame pointer here, because the | |
1485 | frame pointer must always be 8 byte aligned. It also confuses | |
1486 | debuggers. */ | |
1487 | if (GET_CODE (XEXP (addr, 0)) == REG | |
1488 | && REGNO (XEXP (addr, 0)) != FRAME_POINTER_REGNUM) | |
1489 | addr = XEXP (addr, 0); | |
1490 | else if (GET_CODE (XEXP (addr, 1)) == REG | |
1491 | && REGNO (XEXP (addr, 1)) != FRAME_POINTER_REGNUM) | |
1492 | addr = XEXP (addr, 1); | |
1493 | else if (CONSTANT_P (XEXP (addr, 0))) | |
1494 | addr = XEXP (addr, 1); | |
1495 | else if (CONSTANT_P (XEXP (addr, 1))) | |
1496 | addr = XEXP (addr, 0); | |
1497 | else | |
1498 | abort (); | |
1499 | } | |
1500 | if (GET_CODE (addr) == REG) | |
1501 | return addr; | |
1502 | abort (); | |
1503 | } | |
1504 | ||
1505 | void | |
1506 | output_sized_memop (opname, mode, signedp) | |
1507 | char *opname; | |
1508 | enum machine_mode mode; | |
1509 | int signedp; | |
1510 | { | |
1511 | static char *ld_size_suffix_u[] = { "ub", "uh", "", "?", "d" }; | |
1512 | static char *ld_size_suffix_s[] = { "sb", "sh", "", "?", "d" }; | |
1513 | static char *st_size_suffix[] = { "b", "h", "", "?", "d" }; | |
1514 | char **opnametab, *modename; | |
1515 | ||
1516 | if (opname[0] == 'l') | |
1517 | if (signedp) | |
1518 | opnametab = ld_size_suffix_s; | |
1519 | else | |
1520 | opnametab = ld_size_suffix_u; | |
1521 | else | |
1522 | opnametab = st_size_suffix; | |
1523 | modename = opnametab[GET_MODE_SIZE (mode) >> 1]; | |
1524 | ||
1525 | fprintf (asm_out_file, "\t%s%s", opname, modename); | |
1526 | } | |
1527 | \f | |
1528 | void | |
1529 | output_move_with_extension (operands) | |
1530 | rtx *operands; | |
1531 | { | |
1532 | if (GET_MODE (operands[2]) == HImode) | |
1533 | output_asm_insn ("sll %2,0x10,%0", operands); | |
1534 | else if (GET_MODE (operands[2]) == QImode) | |
1535 | output_asm_insn ("sll %2,0x18,%0", operands); | |
1536 | else | |
1537 | abort (); | |
1538 | } | |
1539 | \f | |
09aa6559 JW |
1540 | #if 0 |
1541 | /* ??? These are only used by the movstrsi pattern, but we get better code | |
1542 | in general without that, because emit_block_move can do just as good a | |
1543 | job as this function does when alignment and size are known. When they | |
1544 | aren't known, a call to strcpy may be faster anyways, because it is | |
1545 | likely to be carefully crafted assembly language code, and below we just | |
1546 | do a byte-wise copy. | |
1547 | ||
1548 | Also, emit_block_move expands into multiple read/write RTL insns, which | |
1549 | can then be optimized, whereas our movstrsi pattern can not be optimized | |
1550 | at all. */ | |
1551 | ||
ab835497 RK |
1552 | /* Load the address specified by OPERANDS[3] into the register |
1553 | specified by OPERANDS[0]. | |
1554 | ||
1555 | OPERANDS[3] may be the result of a sum, hence it could either be: | |
1556 | ||
1557 | (1) CONST | |
1558 | (2) REG | |
1559 | (2) REG + CONST_INT | |
1560 | (3) REG + REG + CONST_INT | |
1561 | (4) REG + REG (special case of 3). | |
1562 | ||
1563 | Note that (3) is not a legitimate address. | |
1564 | All cases are handled here. */ | |
1565 | ||
1566 | void | |
1567 | output_load_address (operands) | |
1568 | rtx *operands; | |
1569 | { | |
1570 | rtx base, offset; | |
1571 | ||
1572 | if (CONSTANT_P (operands[3])) | |
1573 | { | |
1574 | output_asm_insn ("set %3,%0", operands); | |
1575 | return; | |
1576 | } | |
1577 | ||
1578 | if (REG_P (operands[3])) | |
1579 | { | |
1580 | if (REGNO (operands[0]) != REGNO (operands[3])) | |
1581 | output_asm_insn ("mov %3,%0", operands); | |
1582 | return; | |
1583 | } | |
1584 | ||
1585 | if (GET_CODE (operands[3]) != PLUS) | |
1586 | abort (); | |
1587 | ||
1588 | base = XEXP (operands[3], 0); | |
1589 | offset = XEXP (operands[3], 1); | |
1590 | ||
1591 | if (GET_CODE (base) == CONST_INT) | |
1592 | { | |
1593 | rtx tmp = base; | |
1594 | base = offset; | |
1595 | offset = tmp; | |
1596 | } | |
1597 | ||
1598 | if (GET_CODE (offset) != CONST_INT) | |
1599 | { | |
1600 | /* Operand is (PLUS (REG) (REG)). */ | |
1601 | base = operands[3]; | |
1602 | offset = const0_rtx; | |
1603 | } | |
1604 | ||
1605 | if (REG_P (base)) | |
1606 | { | |
1607 | operands[6] = base; | |
1608 | operands[7] = offset; | |
1609 | if (SMALL_INT (offset)) | |
1610 | output_asm_insn ("add %6,%7,%0", operands); | |
1611 | else | |
1612 | output_asm_insn ("set %7,%0\n\tadd %0,%6,%0", operands); | |
1613 | } | |
1614 | else if (GET_CODE (base) == PLUS) | |
1615 | { | |
1616 | operands[6] = XEXP (base, 0); | |
1617 | operands[7] = XEXP (base, 1); | |
1618 | operands[8] = offset; | |
1619 | ||
1620 | if (SMALL_INT (offset)) | |
1621 | output_asm_insn ("add %6,%7,%0\n\tadd %0,%8,%0", operands); | |
1622 | else | |
1623 | output_asm_insn ("set %8,%0\n\tadd %0,%6,%0\n\tadd %0,%7,%0", operands); | |
1624 | } | |
1625 | else | |
1626 | abort (); | |
1627 | } | |
1628 | ||
1629 | /* Output code to place a size count SIZE in register REG. | |
1630 | ALIGN is the size of the unit of transfer. | |
1631 | ||
1632 | Because block moves are pipelined, we don't include the | |
1633 | first element in the transfer of SIZE to REG. */ | |
1634 | ||
1635 | static void | |
1636 | output_size_for_block_move (size, reg, align) | |
1637 | rtx size, reg; | |
1638 | rtx align; | |
1639 | { | |
1640 | rtx xoperands[3]; | |
1641 | ||
1642 | xoperands[0] = reg; | |
1643 | xoperands[1] = size; | |
1644 | xoperands[2] = align; | |
1645 | if (GET_CODE (size) == REG) | |
1646 | output_asm_insn ("sub %1,%2,%0", xoperands); | |
1647 | else | |
1648 | { | |
1649 | xoperands[1] | |
1650 | = gen_rtx (CONST_INT, VOIDmode, INTVAL (size) - INTVAL (align)); | |
1651 | output_asm_insn ("set %1,%0", xoperands); | |
1652 | } | |
1653 | } | |
1654 | ||
1655 | /* Emit code to perform a block move. | |
1656 | ||
1657 | OPERANDS[0] is the destination. | |
1658 | OPERANDS[1] is the source. | |
1659 | OPERANDS[2] is the size. | |
1660 | OPERANDS[3] is the alignment safe to use. | |
1661 | OPERANDS[4] is a register we can safely clobber as a temp. */ | |
1662 | ||
1663 | char * | |
1664 | output_block_move (operands) | |
1665 | rtx *operands; | |
1666 | { | |
1667 | /* A vector for our computed operands. Note that load_output_address | |
1668 | makes use of (and can clobber) up to the 8th element of this vector. */ | |
1669 | rtx xoperands[10]; | |
1670 | rtx zoperands[10]; | |
1671 | static int movstrsi_label = 0; | |
1672 | int i; | |
1673 | rtx temp1 = operands[4]; | |
1674 | rtx sizertx = operands[2]; | |
1675 | rtx alignrtx = operands[3]; | |
1676 | int align = INTVAL (alignrtx); | |
210aa14a | 1677 | char label3[30], label5[30]; |
ab835497 RK |
1678 | |
1679 | xoperands[0] = operands[0]; | |
1680 | xoperands[1] = operands[1]; | |
1681 | xoperands[2] = temp1; | |
1682 | ||
391b99c9 RS |
1683 | /* We can't move more than this many bytes at a time because we have only |
1684 | one register, %g1, to move them through. */ | |
1685 | if (align > UNITS_PER_WORD) | |
ab835497 | 1686 | { |
391b99c9 RS |
1687 | align = UNITS_PER_WORD; |
1688 | alignrtx = gen_rtx (CONST_INT, VOIDmode, UNITS_PER_WORD); | |
ab835497 RK |
1689 | } |
1690 | ||
391b99c9 RS |
1691 | /* We consider 8 ld/st pairs, for a total of 16 inline insns to be |
1692 | reasonable here. (Actually will emit a maximum of 18 inline insns for | |
1693 | the case of size == 31 and align == 4). */ | |
1694 | ||
1695 | if (GET_CODE (sizertx) == CONST_INT && (INTVAL (sizertx) / align) <= 8 | |
1696 | && memory_address_p (QImode, plus_constant_for_output (xoperands[0], | |
1697 | INTVAL (sizertx))) | |
1698 | && memory_address_p (QImode, plus_constant_for_output (xoperands[1], | |
1699 | INTVAL (sizertx)))) | |
ab835497 RK |
1700 | { |
1701 | int size = INTVAL (sizertx); | |
391b99c9 | 1702 | int offset = 0; |
ab835497 | 1703 | |
391b99c9 RS |
1704 | /* We will store different integers into this particular RTX. */ |
1705 | xoperands[2] = rtx_alloc (CONST_INT); | |
1706 | PUT_MODE (xoperands[2], VOIDmode); | |
ab835497 | 1707 | |
391b99c9 RS |
1708 | /* This case is currently not handled. Abort instead of generating |
1709 | bad code. */ | |
1710 | if (align > 4) | |
1711 | abort (); | |
ab835497 | 1712 | |
391b99c9 | 1713 | if (align >= 4) |
ab835497 | 1714 | { |
391b99c9 | 1715 | for (i = (size >> 2) - 1; i >= 0; i--) |
ab835497 | 1716 | { |
391b99c9 RS |
1717 | INTVAL (xoperands[2]) = (i << 2) + offset; |
1718 | output_asm_insn ("ld [%a1+%2],%%g1\n\tst %%g1,[%a0+%2]", | |
1719 | xoperands); | |
ab835497 | 1720 | } |
391b99c9 RS |
1721 | offset += (size & ~0x3); |
1722 | size = size & 0x3; | |
1723 | if (size == 0) | |
1724 | return ""; | |
ab835497 | 1725 | } |
391b99c9 RS |
1726 | |
1727 | if (align >= 2) | |
ab835497 | 1728 | { |
391b99c9 | 1729 | for (i = (size >> 1) - 1; i >= 0; i--) |
ab835497 | 1730 | { |
391b99c9 RS |
1731 | INTVAL (xoperands[2]) = (i << 1) + offset; |
1732 | output_asm_insn ("lduh [%a1+%2],%%g1\n\tsth %%g1,[%a0+%2]", | |
1733 | xoperands); | |
ab835497 | 1734 | } |
391b99c9 RS |
1735 | offset += (size & ~0x1); |
1736 | size = size & 0x1; | |
1737 | if (size == 0) | |
1738 | return ""; | |
ab835497 | 1739 | } |
391b99c9 RS |
1740 | |
1741 | if (align >= 1) | |
ab835497 | 1742 | { |
391b99c9 | 1743 | for (i = size - 1; i >= 0; i--) |
ab835497 | 1744 | { |
391b99c9 RS |
1745 | INTVAL (xoperands[2]) = i + offset; |
1746 | output_asm_insn ("ldub [%a1+%2],%%g1\n\tstb %%g1,[%a0+%2]", | |
1747 | xoperands); | |
ab835497 | 1748 | } |
391b99c9 | 1749 | return ""; |
ab835497 | 1750 | } |
391b99c9 RS |
1751 | |
1752 | /* We should never reach here. */ | |
1753 | abort (); | |
ab835497 RK |
1754 | } |
1755 | ||
391b99c9 RS |
1756 | /* If the size isn't known to be a multiple of the alignment, |
1757 | we have to do it in smaller pieces. If we could determine that | |
1758 | the size was a multiple of 2 (or whatever), we could be smarter | |
1759 | about this. */ | |
1760 | if (GET_CODE (sizertx) != CONST_INT) | |
1761 | align = 1; | |
1762 | else | |
1763 | { | |
1764 | int size = INTVAL (sizertx); | |
1765 | while (size % align) | |
1766 | align >>= 1; | |
1767 | } | |
1768 | ||
1769 | if (align != INTVAL (alignrtx)) | |
1770 | alignrtx = gen_rtx (CONST_INT, VOIDmode, align); | |
1771 | ||
ab835497 RK |
1772 | xoperands[3] = gen_rtx (CONST_INT, VOIDmode, movstrsi_label++); |
1773 | xoperands[4] = gen_rtx (CONST_INT, VOIDmode, align); | |
1774 | xoperands[5] = gen_rtx (CONST_INT, VOIDmode, movstrsi_label++); | |
1775 | ||
210aa14a RS |
1776 | ASM_GENERATE_INTERNAL_LABEL (label3, "Lm", INTVAL (xoperands[3])); |
1777 | ASM_GENERATE_INTERNAL_LABEL (label5, "Lm", INTVAL (xoperands[5])); | |
1778 | ||
391b99c9 RS |
1779 | /* This is the size of the transfer. Emit code to decrement the size |
1780 | value by ALIGN, and store the result in the temp1 register. */ | |
ab835497 RK |
1781 | output_size_for_block_move (sizertx, temp1, alignrtx); |
1782 | ||
1783 | /* Must handle the case when the size is zero or negative, so the first thing | |
1784 | we do is compare the size against zero, and only copy bytes if it is | |
1785 | zero or greater. Note that we have already subtracted off the alignment | |
1786 | once, so we must copy 1 alignment worth of bytes if the size is zero | |
1787 | here. | |
1788 | ||
1789 | The SUN assembler complains about labels in branch delay slots, so we | |
b4ac57ab | 1790 | do this before outputting the load address, so that there will always |
ab835497 RK |
1791 | be a harmless insn between the branch here and the next label emitted |
1792 | below. */ | |
1793 | ||
210aa14a RS |
1794 | { |
1795 | char pattern[100]; | |
1796 | ||
1797 | sprintf (pattern, "cmp %%2,0\n\tbl %s", &label5[1]); | |
1798 | output_asm_insn (pattern, xoperands); | |
1799 | } | |
ab835497 RK |
1800 | |
1801 | zoperands[0] = operands[0]; | |
1802 | zoperands[3] = plus_constant_for_output (operands[0], align); | |
1803 | output_load_address (zoperands); | |
1804 | ||
1805 | /* ??? This might be much faster if the loops below were preconditioned | |
1806 | and unrolled. | |
1807 | ||
1808 | That is, at run time, copy enough bytes one at a time to ensure that the | |
1809 | target and source addresses are aligned to the the largest possible | |
1810 | alignment. Then use a preconditioned unrolled loop to copy say 16 | |
1811 | bytes at a time. Then copy bytes one at a time until finish the rest. */ | |
1812 | ||
1813 | /* Output the first label separately, so that it is spaced properly. */ | |
1814 | ||
ab835497 | 1815 | ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "Lm", INTVAL (xoperands[3])); |
ab835497 | 1816 | |
210aa14a RS |
1817 | { |
1818 | char pattern[200]; | |
1819 | register char *ld_suffix = (align == 1) ? "ub" : (align == 2) ? "uh" : ""; | |
1820 | register char *st_suffix = (align == 1) ? "b" : (align == 2) ? "h" : ""; | |
1821 | ||
1822 | sprintf (pattern, "ld%s [%%1+%%2],%%%%g1\n\tsubcc %%2,%%4,%%2\n\tbge %s\n\tst%s %%%%g1,[%%0+%%2]\n%s:", ld_suffix, &label3[1], st_suffix, &label5[1]); | |
1823 | output_asm_insn (pattern, xoperands); | |
1824 | } | |
1825 | ||
ab835497 | 1826 | return ""; |
ab835497 | 1827 | } |
09aa6559 | 1828 | #endif |
ab835497 RK |
1829 | \f |
1830 | /* Output reasonable peephole for set-on-condition-code insns. | |
1831 | Note that these insns assume a particular way of defining | |
1832 | labels. Therefore, *both* sparc.h and this function must | |
1833 | be changed if a new syntax is needed. */ | |
1834 | ||
1835 | char * | |
1836 | output_scc_insn (operands, insn) | |
1837 | rtx operands[]; | |
1838 | rtx insn; | |
1839 | { | |
1840 | static char string[100]; | |
1841 | rtx label = 0, next = insn; | |
1842 | int need_label = 0; | |
1843 | ||
1844 | /* Try doing a jump optimization which jump.c can't do for us | |
1845 | because we did not expose that setcc works by using branches. | |
1846 | ||
1847 | If this scc insn is followed by an unconditional branch, then have | |
1848 | the jump insn emitted here jump to that location, instead of to | |
1849 | the end of the scc sequence as usual. */ | |
1850 | ||
1851 | do | |
1852 | { | |
1853 | if (GET_CODE (next) == CODE_LABEL) | |
1854 | label = next; | |
1855 | next = NEXT_INSN (next); | |
1856 | if (next == 0) | |
1857 | break; | |
1858 | } | |
1859 | while (GET_CODE (next) == NOTE || GET_CODE (next) == CODE_LABEL); | |
1860 | ||
1861 | /* If we are in a sequence, and the following insn is a sequence also, | |
1862 | then just following the current insn's next field will take us to the | |
1863 | first insn of the next sequence, which is the wrong place. We don't | |
1864 | want to optimize with a branch that has had its delay slot filled. | |
1865 | Avoid this by verifying that NEXT_INSN (PREV_INSN (next)) == next | |
1866 | which fails only if NEXT is such a branch. */ | |
1867 | ||
1868 | if (next && GET_CODE (next) == JUMP_INSN && simplejump_p (next) | |
1869 | && (! final_sequence || NEXT_INSN (PREV_INSN (next)) == next)) | |
1870 | label = JUMP_LABEL (next); | |
1871 | /* If not optimizing, jump label fields are not set. To be safe, always | |
1872 | check here to whether label is still zero. */ | |
1873 | if (label == 0) | |
1874 | { | |
1875 | label = gen_label_rtx (); | |
1876 | need_label = 1; | |
1877 | } | |
1878 | ||
1879 | LABEL_NUSES (label) += 1; | |
1880 | ||
1881 | operands[2] = label; | |
1882 | ||
1883 | /* If we are in a delay slot, assume it is the delay slot of an fpcc | |
1884 | insn since our type isn't allowed anywhere else. */ | |
1885 | ||
1886 | /* ??? Fpcc instructions no longer have delay slots, so this code is | |
1887 | probably obsolete. */ | |
1888 | ||
1889 | /* The fastest way to emit code for this is an annulled branch followed | |
1890 | by two move insns. This will take two cycles if the branch is taken, | |
1891 | and three cycles if the branch is not taken. | |
1892 | ||
1893 | However, if we are in the delay slot of another branch, this won't work, | |
1894 | because we can't put a branch in the delay slot of another branch. | |
1895 | The above sequence would effectively take 3 or 4 cycles respectively | |
1896 | since a no op would have be inserted between the two branches. | |
1897 | In this case, we want to emit a move, annulled branch, and then the | |
1898 | second move. This sequence always takes 3 cycles, and hence is faster | |
1899 | when we are in a branch delay slot. */ | |
1900 | ||
1901 | if (final_sequence) | |
1902 | { | |
1903 | strcpy (string, "mov 0,%0\n\t"); | |
1904 | strcat (string, output_cbranch (operands[1], 2, 0, 1, 0)); | |
1905 | strcat (string, "\n\tmov 1,%0"); | |
1906 | } | |
1907 | else | |
1908 | { | |
1909 | strcpy (string, output_cbranch (operands[1], 2, 0, 1, 0)); | |
1910 | strcat (string, "\n\tmov 1,%0\n\tmov 0,%0"); | |
1911 | } | |
1912 | ||
1913 | if (need_label) | |
1914 | strcat (string, "\n%l2:"); | |
1915 | ||
1916 | return string; | |
1917 | } | |
1918 | \f | |
1919 | /* Vectors to keep interesting information about registers where | |
1920 | it can easily be got. */ | |
1921 | ||
1922 | /* Modes for condition codes. */ | |
4d449554 JW |
1923 | #define C_MODES \ |
1924 | ((1 << (int) CCmode) | (1 << (int) CC_NOOVmode) \ | |
1925 | | (1 << (int) CCFPmode) | (1 << (int) CCFPEmode)) | |
ab835497 RK |
1926 | |
1927 | /* Modes for single-word (and smaller) quantities. */ | |
6ac2ba93 RS |
1928 | #define S_MODES \ |
1929 | ((1 << (int) QImode) | (1 << (int) HImode) | (1 << (int) SImode) \ | |
1930 | | (1 << (int) QFmode) | (1 << (int) HFmode) | (1 << (int) SFmode) \ | |
1931 | | (1 << (int) CQImode) | (1 << (int) CHImode)) | |
ab835497 RK |
1932 | |
1933 | /* Modes for double-word (and smaller) quantities. */ | |
6ac2ba93 RS |
1934 | #define D_MODES \ |
1935 | (S_MODES | (1 << (int) DImode) | (1 << (int) DFmode) \ | |
1936 | | (1 << (int) CSImode) | (1 << (int) SCmode)) | |
ab835497 RK |
1937 | |
1938 | /* Modes for quad-word quantities. */ | |
6ac2ba93 RS |
1939 | #define T_MODES \ |
1940 | (D_MODES | (1 << (int) TImode) | (1 << (int) TFmode) \ | |
1941 | | (1 << (int) DCmode) | (1 << (int) CDImode)) | |
ab835497 | 1942 | |
1e4eb8d1 JW |
1943 | /* Modes for single-float quantities. We must allow any single word or |
1944 | smaller quantity. This is because the fix/float conversion instructions | |
1945 | take integer inputs/outputs from the float registers. */ | |
1946 | #define SF_MODES (S_MODES) | |
ab835497 RK |
1947 | |
1948 | /* Modes for double-float quantities. */ | |
1949 | #define DF_MODES (SF_MODES | (1 << (int) DFmode) | (1 << (int) SCmode)) | |
1950 | ||
1951 | /* Modes for quad-float quantities. */ | |
1952 | #define TF_MODES (DF_MODES | (1 << (int) TFmode) | (1 << (int) DCmode)) | |
1953 | ||
1954 | /* Value is 1 if register/mode pair is acceptable on sparc. | |
1955 | The funny mixture of D and T modes is because integer operations | |
1956 | do not specially operate on tetra quantities, so non-quad-aligned | |
1957 | registers can hold quadword quantities (except %o4 and %i4 because | |
1958 | they cross fixed registers. */ | |
1959 | ||
1960 | int hard_regno_mode_ok[] = { | |
1961 | C_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, | |
1962 | T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES, | |
1963 | T_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, | |
1964 | T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES, | |
1965 | ||
1966 | TF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES, | |
1967 | TF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES, | |
1968 | TF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES, | |
1969 | TF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES}; | |
1970 | \f | |
1971 | #ifdef __GNUC__ | |
1972 | inline | |
1973 | #endif | |
1974 | static int | |
1975 | save_regs (file, low, high, base, offset, n_fregs) | |
1976 | FILE *file; | |
1977 | int low, high; | |
1978 | char *base; | |
1979 | int offset; | |
1980 | int n_fregs; | |
1981 | { | |
1982 | int i; | |
1983 | ||
1984 | for (i = low; i < high; i += 2) | |
1985 | { | |
1986 | if (regs_ever_live[i] && ! call_used_regs[i]) | |
1987 | if (regs_ever_live[i+1] && ! call_used_regs[i+1]) | |
1988 | fprintf (file, "\tstd %s,[%s+%d]\n", | |
1989 | reg_names[i], base, offset + 4 * n_fregs), | |
1990 | n_fregs += 2; | |
1991 | else | |
1992 | fprintf (file, "\tst %s,[%s+%d]\n", | |
1993 | reg_names[i], base, offset + 4 * n_fregs), | |
1994 | n_fregs += 2; | |
1995 | else if (regs_ever_live[i+1] && ! call_used_regs[i+1]) | |
1996 | fprintf (file, "\tst %s,[%s+%d]\n", | |
1997 | reg_names[i+1], base, offset + 4 * n_fregs), | |
1998 | n_fregs += 2; | |
1999 | } | |
2000 | return n_fregs; | |
2001 | } | |
2002 | ||
2003 | #ifdef __GNUC__ | |
2004 | inline | |
2005 | #endif | |
2006 | static int | |
2007 | restore_regs (file, low, high, base, offset, n_fregs) | |
2008 | FILE *file; | |
2009 | int low, high; | |
2010 | char *base; | |
2011 | int offset; | |
2012 | { | |
2013 | int i; | |
2014 | ||
2015 | for (i = low; i < high; i += 2) | |
2016 | { | |
2017 | if (regs_ever_live[i] && ! call_used_regs[i]) | |
2018 | if (regs_ever_live[i+1] && ! call_used_regs[i+1]) | |
2019 | fprintf (file, "\tldd [%s+%d], %s\n", | |
2020 | base, offset + 4 * n_fregs, reg_names[i]), | |
2021 | n_fregs += 2; | |
2022 | else | |
2023 | fprintf (file, "\tld [%s+%d],%s\n", | |
2024 | base, offset + 4 * n_fregs, reg_names[i]), | |
2025 | n_fregs += 2; | |
2026 | else if (regs_ever_live[i+1] && ! call_used_regs[i+1]) | |
2027 | fprintf (file, "\tld [%s+%d],%s\n", | |
2028 | base, offset + 4 * n_fregs, reg_names[i+1]), | |
2029 | n_fregs += 2; | |
2030 | } | |
2031 | return n_fregs; | |
2032 | } | |
2033 | ||
2034 | /* Static variables we want to share between prologue and epilogue. */ | |
2035 | ||
2036 | /* Number of live floating point registers needed to be saved. */ | |
2037 | static int num_fregs; | |
2038 | ||
ab835497 RK |
2039 | int |
2040 | compute_frame_size (size, leaf_function) | |
2041 | int size; | |
2042 | int leaf_function; | |
2043 | { | |
2044 | int fregs_ever_live = 0; | |
2045 | int n_fregs = 0, i; | |
2046 | int outgoing_args_size = (current_function_outgoing_args_size | |
2047 | + REG_PARM_STACK_SPACE (current_function_decl)); | |
2048 | ||
2049 | apparent_fsize = ((size) + 7 - STARTING_FRAME_OFFSET) & -8; | |
2050 | for (i = 32; i < FIRST_PSEUDO_REGISTER; i += 2) | |
2051 | fregs_ever_live |= regs_ever_live[i]|regs_ever_live[i+1]; | |
2052 | ||
2053 | if (TARGET_EPILOGUE && fregs_ever_live) | |
2054 | { | |
2055 | for (i = 32; i < FIRST_PSEUDO_REGISTER; i += 2) | |
2056 | if ((regs_ever_live[i] && ! call_used_regs[i]) | |
2057 | || (regs_ever_live[i+1] && ! call_used_regs[i+1])) | |
2058 | n_fregs += 2; | |
2059 | } | |
2060 | ||
2061 | /* Set up values for use in `function_epilogue'. */ | |
2062 | num_fregs = n_fregs; | |
2063 | ||
2064 | apparent_fsize += (outgoing_args_size+7) & -8; | |
2065 | if (leaf_function && n_fregs == 0 | |
2066 | && apparent_fsize == (REG_PARM_STACK_SPACE (current_function_decl) | |
2067 | - STARTING_FRAME_OFFSET)) | |
2068 | apparent_fsize = 0; | |
2069 | ||
2070 | actual_fsize = apparent_fsize + n_fregs*4; | |
2071 | ||
2072 | /* Make sure nothing can clobber our register windows. | |
2073 | If a SAVE must be done, or there is a stack-local variable, | |
2074 | the register window area must be allocated. */ | |
2075 | if (leaf_function == 0 || size > 0) | |
2076 | actual_fsize += (16 * UNITS_PER_WORD)+8; | |
2077 | ||
2078 | return actual_fsize; | |
2079 | } | |
2080 | ||
915f619f JW |
2081 | /* Output code for the function prologue. */ |
2082 | ||
ab835497 RK |
2083 | void |
2084 | output_function_prologue (file, size, leaf_function) | |
2085 | FILE *file; | |
2086 | int size; | |
915f619f | 2087 | int leaf_function; |
ab835497 | 2088 | { |
a07c1915 JW |
2089 | /* ??? This should be %sp+actual_fsize for a leaf function. I think it |
2090 | works only because it is never used. */ | |
ab835497 RK |
2091 | if (leaf_function) |
2092 | frame_base_name = "%sp+80"; | |
2093 | else | |
2094 | frame_base_name = "%fp"; | |
2095 | ||
915f619f JW |
2096 | /* Need to use actual_fsize, since we are also allocating |
2097 | space for our callee (and our own register save area). */ | |
ab835497 RK |
2098 | actual_fsize = compute_frame_size (size, leaf_function); |
2099 | ||
2100 | fprintf (file, "\t!#PROLOGUE# 0\n"); | |
915f619f JW |
2101 | if (actual_fsize == 0) |
2102 | /* do nothing. */ ; | |
2103 | else if (actual_fsize <= 4096) | |
ab835497 RK |
2104 | { |
2105 | if (! leaf_function) | |
2106 | fprintf (file, "\tsave %%sp,-%d,%%sp\n", actual_fsize); | |
2107 | else | |
2108 | fprintf (file, "\tadd %%sp,-%d,%%sp\n", actual_fsize); | |
2109 | } | |
915f619f | 2110 | else if (actual_fsize <= 8192) |
ab835497 | 2111 | { |
915f619f JW |
2112 | /* For frames in the range 4097..8192, we can use just two insns. */ |
2113 | if (! leaf_function) | |
2114 | { | |
2115 | fprintf (file, "\tsave %%sp,-4096,%%sp\n"); | |
2116 | fprintf (file, "\tadd %%sp,-%d,%%sp\n", actual_fsize - 4096); | |
2117 | } | |
2118 | else | |
2119 | { | |
2120 | fprintf (file, "\tadd %%sp,-4096,%%sp\n"); | |
2121 | fprintf (file, "\tadd %%sp,-%d,%%sp\n", actual_fsize - 4096); | |
2122 | } | |
ab835497 RK |
2123 | } |
2124 | else | |
2125 | { | |
915f619f JW |
2126 | if (! leaf_function) |
2127 | { | |
2128 | fprintf (file, "\tsethi %%hi(-%d),%%g1\n", actual_fsize); | |
2129 | if ((actual_fsize & 0x3ff) != 0) | |
2130 | fprintf (file, "\tor %%g1,%%lo(-%d),%%g1\n", actual_fsize); | |
2131 | fprintf (file, "\tsave %%sp,%%g1,%%sp\n"); | |
2132 | } | |
2133 | else | |
2134 | { | |
2135 | fprintf (file, "\tsethi %%hi(-%d),%%g1\n", actual_fsize); | |
2136 | if ((actual_fsize & 0x3ff) != 0) | |
2137 | fprintf (file, "\tor %%g1,%%lo(-%d),%%g1\n", actual_fsize); | |
2138 | fprintf (file, "\tadd %%sp,%%g1,%%sp\n"); | |
2139 | } | |
ab835497 RK |
2140 | } |
2141 | ||
2142 | /* If doing anything with PIC, do it now. */ | |
2143 | if (! flag_pic) | |
2144 | fprintf (file, "\t!#PROLOGUE# 1\n"); | |
2145 | ||
2146 | /* Figure out where to save any special registers. */ | |
2147 | if (num_fregs) | |
2148 | { | |
2149 | int offset, n_fregs = num_fregs; | |
2150 | ||
a07c1915 | 2151 | /* ??? This should always be -apparent_fsize. */ |
ab835497 RK |
2152 | if (! leaf_function) |
2153 | offset = -apparent_fsize; | |
2154 | else | |
2155 | offset = 0; | |
2156 | ||
2157 | if (TARGET_EPILOGUE && ! leaf_function) | |
2158 | n_fregs = save_regs (file, 0, 16, frame_base_name, offset, 0); | |
2159 | else if (leaf_function) | |
2160 | n_fregs = save_regs (file, 0, 32, frame_base_name, offset, 0); | |
2161 | if (TARGET_EPILOGUE) | |
2162 | save_regs (file, 32, FIRST_PSEUDO_REGISTER, | |
2163 | frame_base_name, offset, n_fregs); | |
2164 | } | |
2165 | ||
ab835497 RK |
2166 | leaf_label = 0; |
2167 | if (leaf_function && actual_fsize != 0) | |
2168 | { | |
2169 | /* warning ("leaf procedure with frame size %d", actual_fsize); */ | |
2170 | if (! TARGET_EPILOGUE) | |
2171 | leaf_label = gen_label_rtx (); | |
2172 | } | |
2173 | } | |
2174 | ||
915f619f JW |
2175 | /* Output code for the function epilogue. */ |
2176 | ||
ab835497 | 2177 | void |
ef8200df | 2178 | output_function_epilogue (file, size, leaf_function) |
ab835497 RK |
2179 | FILE *file; |
2180 | int size; | |
ef8200df | 2181 | int leaf_function; |
ab835497 | 2182 | { |
ab835497 RK |
2183 | char *ret; |
2184 | ||
2185 | if (leaf_label) | |
2186 | { | |
ab835497 RK |
2187 | emit_label_after (leaf_label, get_last_insn ()); |
2188 | final_scan_insn (get_last_insn (), file, 0, 0, 1); | |
2189 | } | |
2190 | ||
2191 | if (num_fregs) | |
2192 | { | |
2193 | int offset, n_fregs = num_fregs; | |
2194 | ||
a07c1915 | 2195 | /* ??? This should always be -apparent_fsize. */ |
ab835497 RK |
2196 | if (! leaf_function) |
2197 | offset = -apparent_fsize; | |
2198 | else | |
2199 | offset = 0; | |
2200 | ||
2201 | if (TARGET_EPILOGUE && ! leaf_function) | |
2202 | n_fregs = restore_regs (file, 0, 16, frame_base_name, offset, 0); | |
2203 | else if (leaf_function) | |
2204 | n_fregs = restore_regs (file, 0, 32, frame_base_name, offset, 0); | |
2205 | if (TARGET_EPILOGUE) | |
2206 | restore_regs (file, 32, FIRST_PSEUDO_REGISTER, | |
2207 | frame_base_name, offset, n_fregs); | |
2208 | } | |
2209 | ||
2210 | /* Work out how to skip the caller's unimp instruction if required. */ | |
2211 | if (leaf_function) | |
2212 | ret = (current_function_returns_struct ? "jmp %o7+12" : "retl"); | |
2213 | else | |
2214 | ret = (current_function_returns_struct ? "jmp %i7+12" : "ret"); | |
2215 | ||
ef8200df | 2216 | if (TARGET_EPILOGUE || leaf_label) |
ab835497 | 2217 | { |
ef8200df JW |
2218 | int old_target_epilogue = TARGET_EPILOGUE; |
2219 | target_flags &= ~old_target_epilogue; | |
ab835497 | 2220 | |
ef8200df JW |
2221 | if (! leaf_function) |
2222 | { | |
2223 | /* If we wound up with things in our delay slot, flush them here. */ | |
2224 | if (current_function_epilogue_delay_list) | |
ab835497 | 2225 | { |
ef8200df JW |
2226 | rtx insn = emit_jump_insn_after (gen_rtx (RETURN, VOIDmode), |
2227 | get_last_insn ()); | |
2228 | PATTERN (insn) = gen_rtx (PARALLEL, VOIDmode, | |
2229 | gen_rtvec (2, | |
2230 | PATTERN (XEXP (current_function_epilogue_delay_list, 0)), | |
2231 | PATTERN (insn))); | |
2232 | final_scan_insn (insn, file, 1, 0, 1); | |
ab835497 RK |
2233 | } |
2234 | else | |
ef8200df JW |
2235 | fprintf (file, "\t%s\n\trestore\n", ret); |
2236 | } | |
915f619f JW |
2237 | /* All of the following cases are for leaf functions. */ |
2238 | else if (current_function_epilogue_delay_list) | |
ef8200df | 2239 | { |
915f619f JW |
2240 | /* eligible_for_epilogue_delay_slot ensures that if this is a |
2241 | leaf function, then we will only have insn in the delay slot | |
2242 | if the frame size is zero, thus no adjust for the stack is | |
2243 | needed here. */ | |
2244 | if (actual_fsize != 0) | |
ef8200df | 2245 | abort (); |
915f619f JW |
2246 | fprintf (file, "\t%s\n", ret); |
2247 | final_scan_insn (XEXP (current_function_epilogue_delay_list, 0), | |
2248 | file, 1, 0, 1); | |
ab835497 | 2249 | } |
9bb7ffda JW |
2250 | /* Output 'nop' instead of 'sub %sp,-0,%sp' when no frame, so as to |
2251 | avoid generating confusing assembly language output. */ | |
2252 | else if (actual_fsize == 0) | |
2253 | fprintf (file, "\t%s\n\tnop\n", ret); | |
915f619f JW |
2254 | else if (actual_fsize <= 4096) |
2255 | fprintf (file, "\t%s\n\tsub %%sp,-%d,%%sp\n", ret, actual_fsize); | |
2256 | else if (actual_fsize <= 8192) | |
2257 | fprintf (file, "\tsub %%sp,-4096,%%sp\n\t%s\n\tsub %%sp,-%d,%%sp\n", | |
2258 | ret, actual_fsize - 4096); | |
2259 | else if ((actual_fsize & 0x3ff) == 0) | |
2260 | fprintf (file, "\tsethi %%hi(%d),%%g1\n\t%s\n\tadd %%sp,%%g1,%%sp\n", | |
2261 | actual_fsize, ret); | |
2262 | else | |
2263 | fprintf (file, "\tsethi %%hi(%d),%%g1\n\tor %%g1,%%lo(%d),%%g1\n\t%s\n\tadd %%sp,%%g1,%%sp\n", | |
2264 | actual_fsize, actual_fsize, ret); | |
ef8200df | 2265 | target_flags |= old_target_epilogue; |
ab835497 RK |
2266 | } |
2267 | } | |
3ea1fdd3 JW |
2268 | |
2269 | /* Do what is necessary for `va_start'. The argument is ignored; | |
2270 | We look at the current function to determine if stdarg or varargs | |
2271 | is used and return the address of the first unnamed parameter. */ | |
2272 | ||
2273 | rtx | |
2274 | sparc_builtin_saveregs (arglist) | |
2275 | tree arglist; | |
2276 | { | |
2277 | tree fntype = TREE_TYPE (current_function_decl); | |
2278 | int stdarg = (TYPE_ARG_TYPES (fntype) != 0 | |
2279 | && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype))) | |
2280 | != void_type_node)); | |
2281 | int first_reg = current_function_args_info; | |
2282 | rtx address; | |
2283 | int regno; | |
2284 | ||
227f7fd9 RS |
2285 | #if 0 /* This code seemed to have no effect except to make |
2286 | varargs not work right when va_list wasn't the first arg. */ | |
3ea1fdd3 JW |
2287 | if (! stdarg) |
2288 | first_reg = 0; | |
227f7fd9 | 2289 | #endif |
3ea1fdd3 JW |
2290 | |
2291 | for (regno = first_reg; regno < NPARM_REGS; regno++) | |
2292 | emit_move_insn (gen_rtx (MEM, word_mode, | |
2293 | gen_rtx (PLUS, Pmode, | |
2294 | frame_pointer_rtx, | |
2295 | GEN_INT (STACK_POINTER_OFFSET | |
2296 | + UNITS_PER_WORD * regno))), | |
2297 | gen_rtx (REG, word_mode, BASE_INCOMING_ARG_REG (word_mode) | |
2298 | + regno)); | |
2299 | ||
2300 | address = gen_rtx (PLUS, Pmode, | |
2301 | frame_pointer_rtx, | |
2302 | GEN_INT (STACK_POINTER_OFFSET | |
2303 | + UNITS_PER_WORD * first_reg)); | |
2304 | ||
2305 | return address; | |
2306 | } | |
ab835497 RK |
2307 | \f |
2308 | /* Return the string to output a conditional branch to LABEL, which is | |
2309 | the operand number of the label. OP is the conditional expression. The | |
2310 | mode of register 0 says what kind of comparison we made. | |
2311 | ||
2312 | REVERSED is non-zero if we should reverse the sense of the comparison. | |
2313 | ||
2314 | ANNUL is non-zero if we should generate an annulling branch. | |
2315 | ||
2316 | NOOP is non-zero if we have to follow this branch by a noop. */ | |
2317 | ||
2318 | char * | |
2319 | output_cbranch (op, label, reversed, annul, noop) | |
2320 | rtx op; | |
2321 | int label; | |
2322 | int reversed, annul, noop; | |
2323 | { | |
2324 | static char string[20]; | |
2325 | enum rtx_code code = GET_CODE (op); | |
2326 | enum machine_mode mode = GET_MODE (XEXP (op, 0)); | |
2327 | static char labelno[] = " %lX"; | |
2328 | ||
b4ac57ab | 2329 | /* ??? FP branches can not be preceded by another floating point insn. |
ab835497 RK |
2330 | Because there is currently no concept of pre-delay slots, we can fix |
2331 | this only by always emitting a nop before a floating point branch. */ | |
2332 | ||
4d449554 | 2333 | if (mode == CCFPmode || mode == CCFPEmode) |
ab835497 RK |
2334 | strcpy (string, "nop\n\t"); |
2335 | ||
2336 | /* If not floating-point or if EQ or NE, we can just reverse the code. */ | |
4d449554 JW |
2337 | if (reversed |
2338 | && ((mode != CCFPmode && mode != CCFPEmode) || code == EQ || code == NE)) | |
ab835497 RK |
2339 | code = reverse_condition (code), reversed = 0; |
2340 | ||
2341 | /* Start by writing the branch condition. */ | |
2342 | switch (code) | |
2343 | { | |
2344 | case NE: | |
4d449554 | 2345 | if (mode == CCFPmode || mode == CCFPEmode) |
ab835497 RK |
2346 | strcat (string, "fbne"); |
2347 | else | |
2348 | strcpy (string, "bne"); | |
2349 | break; | |
2350 | ||
2351 | case EQ: | |
4d449554 | 2352 | if (mode == CCFPmode || mode == CCFPEmode) |
ab835497 RK |
2353 | strcat (string, "fbe"); |
2354 | else | |
2355 | strcpy (string, "be"); | |
2356 | break; | |
2357 | ||
2358 | case GE: | |
4d449554 | 2359 | if (mode == CCFPmode || mode == CCFPEmode) |
ab835497 RK |
2360 | { |
2361 | if (reversed) | |
2362 | strcat (string, "fbul"); | |
2363 | else | |
2364 | strcat (string, "fbge"); | |
2365 | } | |
2366 | else if (mode == CC_NOOVmode) | |
2367 | strcpy (string, "bpos"); | |
2368 | else | |
2369 | strcpy (string, "bge"); | |
2370 | break; | |
2371 | ||
2372 | case GT: | |
4d449554 | 2373 | if (mode == CCFPmode || mode == CCFPEmode) |
ab835497 RK |
2374 | { |
2375 | if (reversed) | |
2376 | strcat (string, "fbule"); | |
2377 | else | |
2378 | strcat (string, "fbg"); | |
2379 | } | |
2380 | else | |
2381 | strcpy (string, "bg"); | |
2382 | break; | |
2383 | ||
2384 | case LE: | |
4d449554 | 2385 | if (mode == CCFPmode || mode == CCFPEmode) |
ab835497 RK |
2386 | { |
2387 | if (reversed) | |
2388 | strcat (string, "fbug"); | |
2389 | else | |
2390 | strcat (string, "fble"); | |
2391 | } | |
2392 | else | |
2393 | strcpy (string, "ble"); | |
2394 | break; | |
2395 | ||
2396 | case LT: | |
4d449554 | 2397 | if (mode == CCFPmode || mode == CCFPEmode) |
ab835497 RK |
2398 | { |
2399 | if (reversed) | |
2400 | strcat (string, "fbuge"); | |
2401 | else | |
2402 | strcat (string, "fbl"); | |
2403 | } | |
2404 | else if (mode == CC_NOOVmode) | |
2405 | strcpy (string, "bneg"); | |
2406 | else | |
2407 | strcpy (string, "bl"); | |
2408 | break; | |
2409 | ||
2410 | case GEU: | |
2411 | strcpy (string, "bgeu"); | |
2412 | break; | |
2413 | ||
2414 | case GTU: | |
2415 | strcpy (string, "bgu"); | |
2416 | break; | |
2417 | ||
2418 | case LEU: | |
2419 | strcpy (string, "bleu"); | |
2420 | break; | |
2421 | ||
2422 | case LTU: | |
2423 | strcpy (string, "blu"); | |
2424 | break; | |
2425 | } | |
2426 | ||
2427 | /* Now add the annulling, the label, and a possible noop. */ | |
2428 | if (annul) | |
2429 | strcat (string, ",a"); | |
2430 | ||
2431 | labelno[3] = label + '0'; | |
2432 | strcat (string, labelno); | |
2433 | ||
2434 | if (noop) | |
2435 | strcat (string, "\n\tnop"); | |
2436 | ||
2437 | return string; | |
2438 | } | |
2439 | ||
795068a4 JW |
2440 | /* Output assembler code to return from a function. */ |
2441 | ||
ab835497 RK |
2442 | char * |
2443 | output_return (operands) | |
2444 | rtx *operands; | |
2445 | { | |
2446 | if (leaf_label) | |
2447 | { | |
2448 | operands[0] = leaf_label; | |
2449 | return "b,a %l0"; | |
2450 | } | |
2451 | else if (leaf_function) | |
2452 | { | |
915f619f JW |
2453 | /* If we didn't allocate a frame pointer for the current function, |
2454 | the stack pointer might have been adjusted. Output code to | |
2455 | restore it now. */ | |
2456 | ||
ab835497 | 2457 | operands[0] = gen_rtx (CONST_INT, VOIDmode, actual_fsize); |
915f619f JW |
2458 | |
2459 | /* Use sub of negated value in first two cases instead of add to | |
2460 | allow actual_fsize == 4096. */ | |
2461 | ||
2462 | if (actual_fsize <= 4096) | |
ab835497 RK |
2463 | { |
2464 | if (current_function_returns_struct) | |
915f619f | 2465 | return "jmp %%o7+12\n\tsub %%sp,-%0,%%sp"; |
ab835497 | 2466 | else |
915f619f | 2467 | return "retl\n\tsub %%sp,-%0,%%sp"; |
ab835497 | 2468 | } |
915f619f | 2469 | else if (actual_fsize <= 8192) |
ab835497 | 2470 | { |
915f619f | 2471 | operands[0] = gen_rtx (CONST_INT, VOIDmode, actual_fsize - 4096); |
ab835497 | 2472 | if (current_function_returns_struct) |
915f619f JW |
2473 | return "sub %%sp,-4096,%%sp\n\tjmp %%o7+12\n\tsub %%sp,-%0,%%sp"; |
2474 | else | |
2475 | return "sub %%sp,-4096,%%sp\n\tretl\n\tsub %%sp,-%0,%%sp"; | |
2476 | } | |
2477 | else if (current_function_returns_struct) | |
2478 | { | |
2479 | if ((actual_fsize & 0x3ff) != 0) | |
ab835497 RK |
2480 | return "sethi %%hi(%a0),%%g1\n\tor %%g1,%%lo(%a0),%%g1\n\tjmp %%o7+12\n\tadd %%sp,%%g1,%%sp"; |
2481 | else | |
915f619f JW |
2482 | return "sethi %%hi(%a0),%%g1\n\tjmp %%o7+12\n\tadd %%sp,%%g1,%%sp"; |
2483 | } | |
2484 | else | |
2485 | { | |
2486 | if ((actual_fsize & 0x3ff) != 0) | |
ab835497 | 2487 | return "sethi %%hi(%a0),%%g1\n\tor %%g1,%%lo(%a0),%%g1\n\tretl\n\tadd %%sp,%%g1,%%sp"; |
915f619f JW |
2488 | else |
2489 | return "sethi %%hi(%a0),%%g1\n\tretl\n\tadd %%sp,%%g1,%%sp"; | |
ab835497 RK |
2490 | } |
2491 | } | |
2492 | else | |
2493 | { | |
2494 | if (current_function_returns_struct) | |
2495 | return "jmp %%i7+12\n\trestore"; | |
2496 | else | |
2497 | return "ret\n\trestore"; | |
2498 | } | |
2499 | } | |
ab835497 RK |
2500 | \f |
2501 | /* Leaf functions and non-leaf functions have different needs. */ | |
2502 | ||
2503 | static int | |
2504 | reg_leaf_alloc_order[] = REG_LEAF_ALLOC_ORDER; | |
2505 | ||
2506 | static int | |
2507 | reg_nonleaf_alloc_order[] = REG_ALLOC_ORDER; | |
2508 | ||
2509 | static int *reg_alloc_orders[] = { | |
2510 | reg_leaf_alloc_order, | |
2511 | reg_nonleaf_alloc_order}; | |
2512 | ||
2513 | void | |
2514 | order_regs_for_local_alloc () | |
2515 | { | |
2516 | static int last_order_nonleaf = 1; | |
2517 | ||
2518 | if (regs_ever_live[15] != last_order_nonleaf) | |
2519 | { | |
2520 | last_order_nonleaf = !last_order_nonleaf; | |
2521 | bcopy (reg_alloc_orders[last_order_nonleaf], reg_alloc_order, | |
2522 | FIRST_PSEUDO_REGISTER * sizeof (int)); | |
2523 | } | |
2524 | } | |
2525 | \f | |
35016322 JW |
2526 | /* Return 1 if REGNO (reg1) is even and REGNO (reg1) == REGNO (reg2) - 1. |
2527 | This makes them candidates for using ldd and std insns. | |
2528 | ||
2529 | Note reg1 and reg2 *must* be hard registers. To be sure we will | |
2530 | abort if we are passed pseudo registers. */ | |
2531 | ||
2532 | int | |
7c56249d | 2533 | registers_ok_for_ldd_peep (reg1, reg2) |
35016322 JW |
2534 | rtx reg1, reg2; |
2535 | { | |
2536 | ||
2537 | /* We might have been passed a SUBREG. */ | |
2538 | if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG) | |
2539 | return 0; | |
2540 | ||
35016322 JW |
2541 | if (REGNO (reg1) % 2 != 0) |
2542 | return 0; | |
2543 | ||
2544 | return (REGNO (reg1) == REGNO (reg2) - 1); | |
2545 | ||
2546 | } | |
2547 | ||
2548 | /* Return 1 if addr1 and addr2 are suitable for use in an ldd or | |
2549 | std insn. | |
2550 | ||
2551 | This can only happen when addr1 and addr2 are consecutive memory | |
2552 | locations (addr1 + 4 == addr2). addr1 must also be aligned on a | |
2553 | 64 bit boundary (addr1 % 8 == 0). | |
2554 | ||
2555 | We know %sp and %fp are kept aligned on a 64 bit boundary. Other | |
2556 | registers are assumed to *never* be properly aligned and are | |
2557 | rejected. | |
2558 | ||
2559 | Knowing %sp and %fp are kept aligned on a 64 bit boundary, we | |
2560 | need only check that the offset for addr1 % 8 == 0. */ | |
2561 | ||
2562 | int | |
7c56249d | 2563 | addrs_ok_for_ldd_peep (addr1, addr2) |
35016322 JW |
2564 | rtx addr1, addr2; |
2565 | { | |
2566 | int reg1, offset1; | |
2567 | ||
2568 | /* Extract a register number and offset (if used) from the first addr. */ | |
2569 | if (GET_CODE (addr1) == PLUS) | |
2570 | { | |
2571 | /* If not a REG, return zero. */ | |
2572 | if (GET_CODE (XEXP (addr1, 0)) != REG) | |
2573 | return 0; | |
2574 | else | |
2575 | { | |
2576 | reg1 = REGNO (XEXP (addr1, 0)); | |
2577 | /* The offset must be constant! */ | |
2578 | if (GET_CODE (XEXP (addr1, 1)) != CONST_INT) | |
2579 | return 0; | |
2580 | offset1 = INTVAL (XEXP (addr1, 1)); | |
2581 | } | |
2582 | } | |
2583 | else if (GET_CODE (addr1) != REG) | |
2584 | return 0; | |
2585 | else | |
2586 | { | |
2587 | reg1 = REGNO (addr1); | |
2588 | /* This was a simple (mem (reg)) expression. Offset is 0. */ | |
2589 | offset1 = 0; | |
2590 | } | |
2591 | ||
2592 | /* Make sure the second address is a (mem (plus (reg) (const_int). */ | |
2593 | if (GET_CODE (addr2) != PLUS) | |
2594 | return 0; | |
2595 | ||
2596 | if (GET_CODE (XEXP (addr2, 0)) != REG | |
2597 | || GET_CODE (XEXP (addr2, 1)) != CONST_INT) | |
2598 | return 0; | |
2599 | ||
2600 | /* Only %fp and %sp are allowed. Additionally both addresses must | |
2601 | use the same register. */ | |
2602 | if (reg1 != FRAME_POINTER_REGNUM && reg1 != STACK_POINTER_REGNUM) | |
2603 | return 0; | |
2604 | ||
2605 | if (reg1 != REGNO (XEXP (addr2, 0))) | |
2606 | return 0; | |
2607 | ||
2296cba3 | 2608 | /* The first offset must be evenly divisible by 8 to ensure the |
35016322 JW |
2609 | address is 64 bit aligned. */ |
2610 | if (offset1 % 8 != 0) | |
2611 | return 0; | |
2612 | ||
2613 | /* The offset for the second addr must be 4 more than the first addr. */ | |
2614 | if (INTVAL (XEXP (addr2, 1)) != offset1 + 4) | |
2615 | return 0; | |
2616 | ||
2617 | /* All the tests passed. addr1 and addr2 are valid for ldd and std | |
2618 | instructions. */ | |
2619 | return 1; | |
2620 | } | |
7c56249d JL |
2621 | |
2622 | /* Return 1 if reg is a pseudo, or is the first register in | |
2623 | a hard register pair. This makes it a candidate for use in | |
2624 | ldd and std insns. */ | |
2625 | ||
2626 | int | |
2627 | register_ok_for_ldd (reg) | |
2628 | rtx reg; | |
2629 | { | |
2630 | ||
2631 | /* We might have been passed a SUBREG. */ | |
2632 | if (GET_CODE (reg) != REG) | |
2633 | return 0; | |
2634 | ||
2635 | if (REGNO (reg) < FIRST_PSEUDO_REGISTER) | |
2636 | return (REGNO (reg) % 2 == 0); | |
2637 | else | |
2638 | return 1; | |
2639 | ||
2640 | } | |
ab835497 | 2641 | \f |
ab835497 RK |
2642 | /* Print operand X (an rtx) in assembler syntax to file FILE. |
2643 | CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. | |
2644 | For `%' followed by punctuation, CODE is the punctuation and X is null. */ | |
2645 | ||
2646 | void | |
2647 | print_operand (file, x, code) | |
2648 | FILE *file; | |
2649 | rtx x; | |
2650 | int code; | |
2651 | { | |
2652 | switch (code) | |
2653 | { | |
2654 | case '#': | |
2655 | /* Output a 'nop' if there's nothing for the delay slot. */ | |
2656 | if (dbr_sequence_length () == 0) | |
2657 | fputs ("\n\tnop", file); | |
2658 | return; | |
2659 | case '*': | |
c6ce0969 JW |
2660 | /* Output an annul flag if there's nothing for the delay slot and we |
2661 | are optimizing. This is always used with '(' below. */ | |
2662 | /* Sun OS 4.1.1 dbx can't handle an annulled unconditional branch; | |
2663 | this is a dbx bug. So, we only do this when optimizing. */ | |
2664 | if (dbr_sequence_length () == 0 && optimize) | |
2665 | fputs (",a", file); | |
2666 | return; | |
2667 | case '(': | |
2668 | /* Output a 'nop' if there's nothing for the delay slot and we are | |
2669 | not optimizing. This is always used with '*' above. */ | |
2670 | if (dbr_sequence_length () == 0 && ! optimize) | |
2671 | fputs ("\n\tnop", file); | |
ab835497 RK |
2672 | return; |
2673 | case 'Y': | |
2674 | /* Adjust the operand to take into account a RESTORE operation. */ | |
2675 | if (GET_CODE (x) != REG) | |
b3b1e8bd JW |
2676 | output_operand_lossage ("Invalid %%Y operand"); |
2677 | else if (REGNO (x) < 8) | |
ab835497 RK |
2678 | fputs (reg_names[REGNO (x)], file); |
2679 | else if (REGNO (x) >= 24 && REGNO (x) < 32) | |
2680 | fputs (reg_names[REGNO (x)-16], file); | |
2681 | else | |
b3b1e8bd | 2682 | output_operand_lossage ("Invalid %%Y operand"); |
ab835497 | 2683 | return; |
ab835497 | 2684 | case 'R': |
795068a4 | 2685 | /* Print out the second register name of a register pair or quad. |
ab835497 RK |
2686 | I.e., R (%o0) => %o1. */ |
2687 | fputs (reg_names[REGNO (x)+1], file); | |
2688 | return; | |
795068a4 JW |
2689 | case 'S': |
2690 | /* Print out the third register name of a register quad. | |
2691 | I.e., S (%o0) => %o2. */ | |
2692 | fputs (reg_names[REGNO (x)+2], file); | |
2693 | return; | |
2694 | case 'T': | |
2695 | /* Print out the fourth register name of a register quad. | |
2696 | I.e., T (%o0) => %o3. */ | |
2697 | fputs (reg_names[REGNO (x)+3], file); | |
2698 | return; | |
ab835497 RK |
2699 | case 'm': |
2700 | /* Print the operand's address only. */ | |
2701 | output_address (XEXP (x, 0)); | |
2702 | return; | |
2703 | case 'r': | |
2704 | /* In this case we need a register. Use %g0 if the | |
77a02b01 | 2705 | operand is const0_rtx. */ |
76052e74 RS |
2706 | if (x == const0_rtx |
2707 | || (GET_MODE (x) != VOIDmode && x == CONST0_RTX (GET_MODE (x)))) | |
ab835497 RK |
2708 | { |
2709 | fputs ("%g0", file); | |
2710 | return; | |
2711 | } | |
2712 | else | |
2713 | break; | |
2714 | ||
2715 | case 'A': | |
2716 | switch (GET_CODE (x)) | |
2717 | { | |
2718 | case IOR: fputs ("or", file); break; | |
2719 | case AND: fputs ("and", file); break; | |
2720 | case XOR: fputs ("xor", file); break; | |
b3b1e8bd | 2721 | default: output_operand_lossage ("Invalid %%A operand"); |
ab835497 RK |
2722 | } |
2723 | return; | |
2724 | ||
2725 | case 'B': | |
2726 | switch (GET_CODE (x)) | |
2727 | { | |
2728 | case IOR: fputs ("orn", file); break; | |
2729 | case AND: fputs ("andn", file); break; | |
2730 | case XOR: fputs ("xnor", file); break; | |
b3b1e8bd | 2731 | default: output_operand_lossage ("Invalid %%B operand"); |
ab835497 RK |
2732 | } |
2733 | return; | |
2734 | ||
2735 | case 'b': | |
2736 | { | |
2737 | /* Print a sign-extended character. */ | |
2738 | int i = INTVAL (x) & 0xff; | |
2739 | if (i & 0x80) | |
2740 | i |= 0xffffff00; | |
2741 | fprintf (file, "%d", i); | |
2742 | return; | |
2743 | } | |
2744 | ||
2745 | case 0: | |
2746 | /* Do nothing special. */ | |
2747 | break; | |
2748 | ||
2749 | default: | |
2750 | /* Undocumented flag. */ | |
415f583e | 2751 | output_operand_lossage ("invalid operand output code"); |
ab835497 RK |
2752 | } |
2753 | ||
2754 | if (GET_CODE (x) == REG) | |
2755 | fputs (reg_names[REGNO (x)], file); | |
2756 | else if (GET_CODE (x) == MEM) | |
2757 | { | |
2758 | fputc ('[', file); | |
2759 | if (CONSTANT_P (XEXP (x, 0))) | |
2760 | /* Poor Sun assembler doesn't understand absolute addressing. */ | |
2761 | fputs ("%g0+", file); | |
2762 | output_address (XEXP (x, 0)); | |
2763 | fputc (']', file); | |
2764 | } | |
2765 | else if (GET_CODE (x) == HIGH) | |
2766 | { | |
2767 | fputs ("%hi(", file); | |
2768 | output_addr_const (file, XEXP (x, 0)); | |
2769 | fputc (')', file); | |
2770 | } | |
2771 | else if (GET_CODE (x) == LO_SUM) | |
2772 | { | |
2773 | print_operand (file, XEXP (x, 0), 0); | |
2774 | fputs ("+%lo(", file); | |
2775 | output_addr_const (file, XEXP (x, 1)); | |
2776 | fputc (')', file); | |
2777 | } | |
e601abce JW |
2778 | else if (GET_CODE (x) == CONST_DOUBLE |
2779 | && (GET_MODE (x) == VOIDmode | |
2780 | || GET_MODE_CLASS (GET_MODE (x)) == MODE_INT)) | |
ab835497 RK |
2781 | { |
2782 | if (CONST_DOUBLE_HIGH (x) == 0) | |
2783 | fprintf (file, "%u", CONST_DOUBLE_LOW (x)); | |
2784 | else if (CONST_DOUBLE_HIGH (x) == -1 | |
2785 | && CONST_DOUBLE_LOW (x) < 0) | |
2786 | fprintf (file, "%d", CONST_DOUBLE_LOW (x)); | |
2787 | else | |
e601abce | 2788 | output_operand_lossage ("long long constant not a valid immediate operand"); |
ab835497 | 2789 | } |
e601abce JW |
2790 | else if (GET_CODE (x) == CONST_DOUBLE) |
2791 | output_operand_lossage ("floating point constant not a valid immediate operand"); | |
ab835497 RK |
2792 | else { output_addr_const (file, x); } |
2793 | } | |
2794 | \f | |
2795 | /* This function outputs assembler code for VALUE to FILE, where VALUE is | |
2796 | a 64 bit (DImode) value. */ | |
2797 | ||
2798 | /* ??? If there is a 64 bit counterpart to .word that the assembler | |
2799 | understands, then using that would simply this code greatly. */ | |
2800 | ||
2801 | void | |
2802 | output_double_int (file, value) | |
2803 | FILE *file; | |
2804 | rtx value; | |
2805 | { | |
2806 | if (GET_CODE (value) == CONST_INT) | |
2807 | { | |
2808 | if (INTVAL (value) < 0) | |
2809 | ASM_OUTPUT_INT (file, constm1_rtx); | |
2810 | else | |
2811 | ASM_OUTPUT_INT (file, const0_rtx); | |
2812 | ASM_OUTPUT_INT (file, value); | |
2813 | } | |
2814 | else if (GET_CODE (value) == CONST_DOUBLE) | |
2815 | { | |
2816 | ASM_OUTPUT_INT (file, gen_rtx (CONST_INT, VOIDmode, | |
2817 | CONST_DOUBLE_HIGH (value))); | |
2818 | ASM_OUTPUT_INT (file, gen_rtx (CONST_INT, VOIDmode, | |
2819 | CONST_DOUBLE_LOW (value))); | |
2820 | } | |
2821 | else if (GET_CODE (value) == SYMBOL_REF | |
2822 | || GET_CODE (value) == CONST | |
2823 | || GET_CODE (value) == PLUS) | |
2824 | { | |
2825 | /* Addresses are only 32 bits. */ | |
2826 | ASM_OUTPUT_INT (file, const0_rtx); | |
2827 | ASM_OUTPUT_INT (file, value); | |
2828 | } | |
2829 | else | |
2830 | abort (); | |
2831 | } | |
210aa14a | 2832 | \f |
77a02b01 JW |
2833 | #ifndef CHAR_TYPE_SIZE |
2834 | #define CHAR_TYPE_SIZE BITS_PER_UNIT | |
2835 | #endif | |
2836 | ||
2837 | #ifndef SHORT_TYPE_SIZE | |
2838 | #define SHORT_TYPE_SIZE (BITS_PER_UNIT * 2) | |
2839 | #endif | |
2840 | ||
2841 | #ifndef INT_TYPE_SIZE | |
2842 | #define INT_TYPE_SIZE BITS_PER_WORD | |
2843 | #endif | |
2844 | ||
2845 | #ifndef LONG_TYPE_SIZE | |
2846 | #define LONG_TYPE_SIZE BITS_PER_WORD | |
2847 | #endif | |
2848 | ||
2849 | #ifndef LONG_LONG_TYPE_SIZE | |
2850 | #define LONG_LONG_TYPE_SIZE (BITS_PER_WORD * 2) | |
2851 | #endif | |
2852 | ||
2853 | #ifndef FLOAT_TYPE_SIZE | |
2854 | #define FLOAT_TYPE_SIZE BITS_PER_WORD | |
2855 | #endif | |
2856 | ||
2857 | #ifndef DOUBLE_TYPE_SIZE | |
2858 | #define DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2) | |
2859 | #endif | |
2860 | ||
2861 | #ifndef LONG_DOUBLE_TYPE_SIZE | |
2862 | #define LONG_DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2) | |
2863 | #endif | |
210aa14a RS |
2864 | |
2865 | unsigned long | |
2866 | sparc_type_code (type) | |
2867 | register tree type; | |
2868 | { | |
2869 | register unsigned long qualifiers = 0; | |
2870 | register unsigned shift = 6; | |
2871 | ||
2872 | for (;;) | |
2873 | { | |
2874 | switch (TREE_CODE (type)) | |
2875 | { | |
2876 | case ERROR_MARK: | |
2877 | return qualifiers; | |
2878 | ||
2879 | case ARRAY_TYPE: | |
2880 | qualifiers |= (3 << shift); | |
2881 | shift += 2; | |
2882 | type = TREE_TYPE (type); | |
2883 | break; | |
2884 | ||
2885 | case FUNCTION_TYPE: | |
2886 | case METHOD_TYPE: | |
2887 | qualifiers |= (2 << shift); | |
2888 | shift += 2; | |
2889 | type = TREE_TYPE (type); | |
2890 | break; | |
2891 | ||
2892 | case POINTER_TYPE: | |
2893 | case REFERENCE_TYPE: | |
2894 | case OFFSET_TYPE: | |
2895 | qualifiers |= (1 << shift); | |
2896 | shift += 2; | |
2897 | type = TREE_TYPE (type); | |
2898 | break; | |
ab835497 | 2899 | |
210aa14a RS |
2900 | case RECORD_TYPE: |
2901 | return (qualifiers | 8); | |
2902 | ||
2903 | case UNION_TYPE: | |
2904 | return (qualifiers | 9); | |
2905 | ||
2906 | case ENUMERAL_TYPE: | |
2907 | return (qualifiers | 10); | |
2908 | ||
2909 | case VOID_TYPE: | |
2910 | return (qualifiers | 16); | |
2911 | ||
2912 | case INTEGER_TYPE: | |
77a02b01 JW |
2913 | /* Carefully distinguish all the standard types of C, |
2914 | without messing up if the language is not C. | |
2915 | Note that we check only for the names that contain spaces; | |
2916 | other names might occur by coincidence in other languages. */ | |
2917 | if (TYPE_NAME (type) != 0 | |
2918 | && TREE_CODE (TYPE_NAME (type)) == TYPE_DECL | |
2919 | && DECL_NAME (TYPE_NAME (type)) != 0 | |
2920 | && TREE_CODE (DECL_NAME (TYPE_NAME (type))) == IDENTIFIER_NODE) | |
2921 | { | |
2922 | char *name = IDENTIFIER_POINTER (DECL_NAME (TYPE_NAME (type))); | |
2923 | ||
2924 | if (!strcmp (name, "unsigned char")) | |
2925 | return (qualifiers | 12); | |
2926 | if (!strcmp (name, "signed char")) | |
2927 | return (qualifiers | 2); | |
2928 | if (!strcmp (name, "unsigned int")) | |
2929 | return (qualifiers | 14); | |
2930 | if (!strcmp (name, "short int")) | |
2931 | return (qualifiers | 3); | |
2932 | if (!strcmp (name, "short unsigned int")) | |
2933 | return (qualifiers | 13); | |
2934 | if (!strcmp (name, "long int")) | |
2935 | return (qualifiers | 5); | |
2936 | if (!strcmp (name, "long unsigned int")) | |
2937 | return (qualifiers | 15); | |
2938 | if (!strcmp (name, "long long int")) | |
2939 | return (qualifiers | 5); /* Who knows? */ | |
2940 | if (!strcmp (name, "long long unsigned int")) | |
2941 | return (qualifiers | 15); /* Who knows? */ | |
2942 | } | |
2943 | ||
2944 | /* Most integer types will be sorted out above, however, for the | |
2945 | sake of special `array index' integer types, the following code | |
2946 | is also provided. */ | |
2947 | ||
2948 | if (TYPE_PRECISION (type) == INT_TYPE_SIZE) | |
2949 | return (qualifiers | (TREE_UNSIGNED (type) ? 14 : 4)); | |
2950 | ||
2951 | if (TYPE_PRECISION (type) == LONG_TYPE_SIZE) | |
2952 | return (qualifiers | (TREE_UNSIGNED (type) ? 15 : 5)); | |
2953 | ||
2954 | if (TYPE_PRECISION (type) == LONG_LONG_TYPE_SIZE) | |
2955 | return (qualifiers | (TREE_UNSIGNED (type) ? 15 : 5)); | |
2956 | ||
2957 | if (TYPE_PRECISION (type) == SHORT_TYPE_SIZE) | |
2958 | return (qualifiers | (TREE_UNSIGNED (type) ? 13 : 3)); | |
2959 | ||
2960 | if (TYPE_PRECISION (type) == CHAR_TYPE_SIZE) | |
2961 | return (qualifiers | (TREE_UNSIGNED (type) ? 12 : 2)); | |
2962 | ||
2963 | abort (); | |
210aa14a RS |
2964 | |
2965 | case REAL_TYPE: | |
77a02b01 JW |
2966 | /* Carefully distinguish all the standard types of C, |
2967 | without messing up if the language is not C. */ | |
2968 | if (TYPE_NAME (type) != 0 | |
2969 | && TREE_CODE (TYPE_NAME (type)) == TYPE_DECL | |
2970 | && DECL_NAME (TYPE_NAME (type)) != 0 | |
2971 | && TREE_CODE (DECL_NAME (TYPE_NAME (type))) == IDENTIFIER_NODE) | |
2972 | { | |
2973 | char *name = IDENTIFIER_POINTER (DECL_NAME (TYPE_NAME (type))); | |
2974 | ||
2975 | if (!strcmp (name, "long double")) | |
2976 | return (qualifiers | 7); /* Who knows? */ | |
2977 | } | |
2978 | ||
2979 | if (TYPE_PRECISION (type) == DOUBLE_TYPE_SIZE) | |
2980 | return (qualifiers | 7); | |
2981 | if (TYPE_PRECISION (type) == FLOAT_TYPE_SIZE) | |
210aa14a | 2982 | return (qualifiers | 6); |
77a02b01 | 2983 | if (TYPE_PRECISION (type) == LONG_DOUBLE_TYPE_SIZE) |
210aa14a | 2984 | return (qualifiers | 7); /* Who knows? */ |
77a02b01 | 2985 | abort (); |
210aa14a RS |
2986 | |
2987 | case COMPLEX_TYPE: /* GNU Fortran COMPLEX type. */ | |
13d39dbc | 2988 | /* ??? We need to distinguish between double and float complex types, |
c82aa69a JW |
2989 | but I don't know how yet because I can't reach this code from |
2990 | existing front-ends. */ | |
2991 | return (qualifiers | 7); /* Who knows? */ | |
2992 | ||
210aa14a RS |
2993 | case CHAR_TYPE: /* GNU Pascal CHAR type. Not used in C. */ |
2994 | case BOOLEAN_TYPE: /* GNU Fortran BOOLEAN type. */ | |
2995 | case FILE_TYPE: /* GNU Pascal FILE type. */ | |
2996 | case STRING_TYPE: /* GNU Fortran STRING type. */ | |
2997 | case LANG_TYPE: /* ? */ | |
2998 | abort (); | |
2999 | ||
3000 | default: | |
3001 | abort (); /* Not a type! */ | |
3002 | } | |
3003 | } | |
3004 | } | |
ead69aea | 3005 | \f |
c819be5b JW |
3006 | /* Subroutines to support a flat (single) register window calling |
3007 | convention. */ | |
3008 | ||
3009 | /* Single-register window sparc stack frames look like: | |
3010 | ||
3011 | Before call After call | |
3012 | +-----------------------+ +-----------------------+ | |
3013 | high | | | | | |
3014 | mem. | | | | | |
3015 | | caller's temps. | | caller's temps. | | |
3016 | | | | | | |
3017 | +-----------------------+ +-----------------------+ | |
3018 | | | | | | |
3019 | | arguments on stack. | | arguments on stack. | | |
3020 | | |FP+92->| | | |
3021 | +-----------------------+ +-----------------------+ | |
3022 | | 6 words to save | | 6 words to save | | |
3023 | | arguments passed | | arguments passed | | |
3024 | | in registers, even | | in registers, even | | |
3025 | SP+68->| if not passed. |FP+68->| if not passed. | | |
3026 | +-----------------------+ +-----------------------+ | |
3027 | | 1 word struct addr |FP+64->| 1 word struct addr | | |
3028 | +-----------------------+ +-----------------------+ | |
3029 | | | | | | |
3030 | | 16 word reg save area | | 16 word reg save area | | |
3031 | SP->| | FP->| | | |
3032 | +-----------------------+ +-----------------------+ | |
3033 | | 4 word area for | | |
3034 | FP-16->| fp/alu reg moves | | |
3035 | +-----------------------+ | |
3036 | | | | |
3037 | | local variables | | |
3038 | | | | |
3039 | +-----------------------+ | |
3040 | | | | |
3041 | | fp register save | | |
3042 | | | | |
3043 | +-----------------------+ | |
3044 | | | | |
3045 | | gp register save | | |
3046 | | | | |
3047 | +-----------------------+ | |
3048 | | | | |
3049 | | alloca allocations | | |
3050 | | | | |
3051 | +-----------------------+ | |
3052 | | | | |
3053 | | arguments on stack | | |
3054 | SP+92->| | | |
3055 | +-----------------------+ | |
3056 | | 6 words to save | | |
3057 | | arguments passed | | |
3058 | | in registers, even | | |
3059 | low SP+68->| if not passed. | | |
3060 | memory +-----------------------+ | |
3061 | SP+64->| 1 word struct addr | | |
3062 | +-----------------------+ | |
3063 | | | | |
3064 | I 16 word reg save area | | |
3065 | SP->| | | |
3066 | +-----------------------+ */ | |
3067 | ||
3068 | /* Structure to be filled in by sparc_frw_compute_frame_size with register | |
3069 | save masks, and offsets for the current function. */ | |
3070 | ||
3071 | struct sparc_frame_info | |
3072 | { | |
3073 | unsigned long total_size; /* # bytes that the entire frame takes up. */ | |
3074 | unsigned long var_size; /* # bytes that variables take up. */ | |
3075 | unsigned long args_size; /* # bytes that outgoing arguments take up. */ | |
3076 | unsigned long extra_size; /* # bytes of extra gunk. */ | |
3077 | unsigned int gp_reg_size; /* # bytes needed to store gp regs. */ | |
3078 | unsigned int fp_reg_size; /* # bytes needed to store fp regs. */ | |
3079 | unsigned long mask; /* Mask of saved gp registers. */ | |
3080 | unsigned long fmask; /* Mask of saved fp registers. */ | |
3081 | unsigned long gp_sp_offset; /* Offset from new sp to store gp regs. */ | |
3082 | unsigned long fp_sp_offset; /* Offset from new sp to store fp regs. */ | |
3083 | int initialized; /* Nonzero if frame size already calculated. */ | |
3084 | }; | |
3085 | ||
3086 | /* Current frame information calculated by sparc_frw_compute_frame_size. */ | |
3087 | struct sparc_frame_info current_frame_info; | |
3088 | ||
3089 | /* Zero structure to initialize current_frame_info. */ | |
3090 | struct sparc_frame_info zero_frame_info; | |
3091 | ||
3092 | /* Tell prologue and epilogue if register REGNO should be saved / restored. */ | |
3093 | ||
3094 | #define MUST_SAVE_REGISTER(regno) \ | |
3095 | ((regs_ever_live[regno] && !call_used_regs[regno]) \ | |
3096 | || (regno == FRAME_POINTER_REGNUM && frame_pointer_needed) \ | |
3097 | || (regno == 15 && regs_ever_live[15])) | |
3098 | ||
3099 | /* Return the bytes needed to compute the frame pointer from the current | |
3100 | stack pointer. */ | |
3101 | ||
3102 | unsigned long | |
3103 | sparc_frw_compute_frame_size (size) | |
3104 | int size; /* # of var. bytes allocated. */ | |
3105 | { | |
3106 | int regno; | |
3107 | unsigned long total_size; /* # bytes that the entire frame takes up. */ | |
3108 | unsigned long var_size; /* # bytes that variables take up. */ | |
3109 | unsigned long args_size; /* # bytes that outgoing arguments take up. */ | |
3110 | unsigned long extra_size; /* # extra bytes. */ | |
3111 | unsigned int gp_reg_size; /* # bytes needed to store gp regs. */ | |
3112 | unsigned int fp_reg_size; /* # bytes needed to store fp regs. */ | |
3113 | unsigned long mask; /* Mask of saved gp registers. */ | |
3114 | unsigned long fmask; /* Mask of saved fp registers. */ | |
3115 | ||
3116 | /* This is the size of the 16 word reg save area, 1 word struct addr | |
3117 | area, and 4 word fp/alu register copy area. */ | |
3118 | extra_size = -STARTING_FRAME_OFFSET + FIRST_PARM_OFFSET(0); | |
3119 | var_size = size; | |
3120 | /* Also include the size needed for the 6 parameter registers. */ | |
3121 | args_size = current_function_outgoing_args_size + 24; | |
3122 | total_size = var_size + args_size + extra_size; | |
3123 | gp_reg_size = 0; | |
3124 | fp_reg_size = 0; | |
3125 | mask = 0; | |
3126 | fmask = 0; | |
3127 | ||
3128 | /* Calculate space needed for gp registers. */ | |
3129 | for (regno = 1; regno <= 31; regno++) | |
3130 | { | |
3131 | if (MUST_SAVE_REGISTER (regno)) | |
3132 | { | |
3133 | if ((regno & 0x1) == 0 && MUST_SAVE_REGISTER (regno+1)) | |
3134 | { | |
3135 | if (gp_reg_size % 8 != 0) | |
3136 | gp_reg_size += UNITS_PER_WORD; | |
3137 | gp_reg_size += 2 * UNITS_PER_WORD; | |
3138 | mask |= 3 << regno; | |
3139 | regno++; | |
3140 | } | |
3141 | else | |
3142 | { | |
3143 | gp_reg_size += UNITS_PER_WORD; | |
3144 | mask |= 1 << regno; | |
3145 | } | |
3146 | } | |
3147 | } | |
3148 | /* Add extra word in case we have to align the space to a double word | |
3149 | boundary. */ | |
3150 | if (gp_reg_size != 0) | |
3151 | gp_reg_size += UNITS_PER_WORD; | |
3152 | ||
3153 | /* Calculate space needed for fp registers. */ | |
3154 | for (regno = 32; regno <= 63; regno++) | |
3155 | { | |
3156 | if (regs_ever_live[regno] && !call_used_regs[regno]) | |
3157 | { | |
3158 | fp_reg_size += UNITS_PER_WORD; | |
3159 | fmask |= 1 << (regno - 32); | |
3160 | } | |
3161 | } | |
3162 | ||
3163 | total_size += gp_reg_size + fp_reg_size; | |
3164 | ||
3165 | if (total_size == extra_size) | |
3166 | total_size = extra_size = 0; | |
3167 | ||
3168 | total_size = SPARC_STACK_ALIGN (total_size); | |
3169 | ||
3170 | /* Save other computed information. */ | |
3171 | current_frame_info.total_size = total_size; | |
3172 | current_frame_info.var_size = var_size; | |
3173 | current_frame_info.args_size = args_size; | |
3174 | current_frame_info.extra_size = extra_size; | |
3175 | current_frame_info.gp_reg_size = gp_reg_size; | |
3176 | current_frame_info.fp_reg_size = fp_reg_size; | |
3177 | current_frame_info.mask = mask; | |
3178 | current_frame_info.fmask = fmask; | |
3179 | current_frame_info.initialized = reload_completed; | |
3180 | ||
3181 | if (mask) | |
3182 | { | |
3183 | unsigned long offset = args_size; | |
3184 | if (extra_size) | |
3185 | offset += FIRST_PARM_OFFSET(0); | |
3186 | current_frame_info.gp_sp_offset = offset; | |
3187 | } | |
3188 | ||
3189 | if (fmask) | |
3190 | { | |
3191 | unsigned long offset = args_size + gp_reg_size; | |
3192 | if (extra_size) | |
3193 | offset += FIRST_PARM_OFFSET(0); | |
3194 | current_frame_info.fp_sp_offset = offset; | |
3195 | } | |
3196 | ||
3197 | /* Ok, we're done. */ | |
3198 | return total_size; | |
3199 | } | |
3200 | \f | |
3201 | /* Common code to save/restore registers. */ | |
3202 | ||
3203 | void | |
3204 | sparc_frw_save_restore (file, word_op, doubleword_op) | |
3205 | FILE *file; /* Stream to write to. */ | |
3206 | char *word_op; /* Operation to do for one word. */ | |
3207 | char *doubleword_op; /* Operation to do for doubleword. */ | |
3208 | { | |
3209 | int regno; | |
3210 | unsigned long mask = current_frame_info.mask; | |
3211 | unsigned long fmask = current_frame_info.fmask; | |
3212 | unsigned long gp_offset; | |
3213 | unsigned long fp_offset; | |
3214 | unsigned long max_offset; | |
3215 | char *base_reg; | |
3216 | ||
3217 | if (mask == 0 && fmask == 0) | |
3218 | return; | |
3219 | ||
3220 | base_reg = reg_names[STACK_POINTER_REGNUM]; | |
3221 | gp_offset = current_frame_info.gp_sp_offset; | |
3222 | fp_offset = current_frame_info.fp_sp_offset; | |
3223 | max_offset = (gp_offset > fp_offset) ? gp_offset : fp_offset; | |
3224 | ||
3225 | /* Deal with calling functions with a large structure. */ | |
3226 | if (max_offset >= 4096) | |
3227 | { | |
3228 | char *temp = "%g2"; | |
3229 | fprintf (file, "\tset %ld,%s\n", max_offset, temp); | |
3230 | fprintf (file, "\tadd %s,%s,%s\n", temp, base_reg, temp); | |
3231 | base_reg = temp; | |
3232 | gp_offset = max_offset - gp_offset; | |
3233 | fp_offset = max_offset - fp_offset; | |
3234 | } | |
3235 | ||
3236 | /* Save registers starting from high to low. The debuggers prefer | |
3237 | at least the return register be stored at func+4, and also it | |
3238 | allows us not to need a nop in the epilog if at least one | |
3239 | register is reloaded in addition to return address. */ | |
3240 | ||
3241 | if (mask || frame_pointer_needed) | |
3242 | { | |
3243 | for (regno = 1; regno <= 31; regno++) | |
3244 | { | |
3245 | if ((mask & (1L << regno)) != 0 | |
3246 | || (regno == FRAME_POINTER_REGNUM && frame_pointer_needed)) | |
3247 | { | |
3248 | if ((regno & 0x1) == 0 && ((mask & (1L << regno+1)) != 0)) | |
3249 | { | |
3250 | if (gp_offset % 8 != 0) | |
3251 | gp_offset += UNITS_PER_WORD; | |
3252 | ||
3253 | if (word_op[0] == 's') | |
3254 | fprintf (file, "\t%s %s,[%s+%d]\n", | |
3255 | doubleword_op, reg_names[regno], | |
3256 | base_reg, gp_offset); | |
3257 | else | |
3258 | fprintf (file, "\t%s [%s+%d],%s\n", | |
3259 | doubleword_op, base_reg, gp_offset, | |
3260 | reg_names[regno]); | |
3261 | ||
3262 | gp_offset += 2 * UNITS_PER_WORD; | |
3263 | regno++; | |
3264 | } | |
3265 | else | |
3266 | { | |
3267 | if (word_op[0] == 's') | |
3268 | fprintf (file, "\t%s %s,[%s+%d]\n", | |
3269 | word_op, reg_names[regno], | |
3270 | base_reg, gp_offset); | |
3271 | else | |
3272 | fprintf (file, "\t%s [%s+%d],%s\n", | |
3273 | word_op, base_reg, gp_offset, reg_names[regno]); | |
3274 | ||
3275 | gp_offset += UNITS_PER_WORD; | |
3276 | } | |
3277 | } | |
3278 | } | |
3279 | } | |
3280 | ||
3281 | if (fmask) | |
3282 | { | |
3283 | for (regno = 32; regno <= 63; regno++) | |
3284 | { | |
3285 | if ((fmask & (1L << (regno - 32))) != 0) | |
3286 | { | |
3287 | if (word_op[0] == 's') | |
3288 | fprintf (file, "\t%s %s,[%s+%d]\n", | |
3289 | word_op, reg_names[regno], | |
3290 | base_reg, gp_offset); | |
3291 | else | |
3292 | fprintf (file, "\t%s [%s+%d],%s\n", | |
3293 | word_op, base_reg, gp_offset, reg_names[regno]); | |
3294 | ||
3295 | fp_offset += UNITS_PER_WORD; | |
3296 | } | |
3297 | } | |
3298 | } | |
3299 | } | |
3300 | \f | |
3301 | /* Set up the stack and frame (if desired) for the function. */ | |
3302 | ||
3303 | void | |
3304 | sparc_frw_output_function_prologue (file, size, ignored) | |
3305 | FILE *file; | |
3306 | int size; | |
3307 | { | |
3308 | extern char call_used_regs[]; | |
c819be5b JW |
3309 | int tsize; |
3310 | char *sp_str = reg_names[STACK_POINTER_REGNUM]; | |
a07c1915 JW |
3311 | |
3312 | /* ??? This should be %sp+actual_fsize for a leaf function. I think it | |
3313 | works only because it is never used. */ | |
c819be5b | 3314 | frame_base_name |
d4f55d3b | 3315 | = (!frame_pointer_needed) ? "%sp+80" : reg_names[FRAME_POINTER_REGNUM]; |
c819be5b JW |
3316 | |
3317 | fprintf (file, "\t!#PROLOGUE# 0\n"); | |
3318 | ||
3319 | size = SPARC_STACK_ALIGN (size); | |
3320 | tsize = (! current_frame_info.initialized | |
3321 | ? sparc_frw_compute_frame_size (size) | |
3322 | : current_frame_info.total_size); | |
3323 | ||
3324 | if (tsize > 0) | |
3325 | { | |
3326 | if (tsize <= 4095) | |
3327 | fprintf (file, | |
3328 | "\tsub %s,%d,%s\t\t!# vars= %d, regs= %d/%d, args = %d, extra= %d\n", | |
3329 | sp_str, tsize, sp_str, current_frame_info.var_size, | |
3330 | current_frame_info.gp_reg_size / 4, | |
3331 | current_frame_info.fp_reg_size / 8, | |
3332 | current_function_outgoing_args_size, | |
3333 | current_frame_info.extra_size); | |
3334 | else | |
3335 | fprintf (file, | |
3336 | "\tset %d,%s\n\tsub\t%s,%s,%s\t\t!# vars= %d, regs= %d/%d, args = %d, sfo= %d\n", | |
3337 | tsize, "%g1", sp_str, "%g1", | |
3338 | sp_str, current_frame_info.var_size, | |
3339 | current_frame_info.gp_reg_size / 4, | |
3340 | current_frame_info.fp_reg_size / 8, | |
3341 | current_function_outgoing_args_size, | |
3342 | current_frame_info.extra_size); | |
3343 | } | |
3344 | ||
3345 | sparc_frw_save_restore (file, "st", "std"); | |
3346 | ||
3347 | if (frame_pointer_needed) | |
3348 | { | |
3349 | if (tsize <= 4095) | |
3350 | fprintf (file, "\tadd %s,%d,%s\t!# set up frame pointer\n", sp_str, | |
3351 | tsize, frame_base_name); | |
3352 | else | |
3353 | fprintf (file, "\tadd %s,%s,%s\t!# set up frame pointer\n", sp_str, | |
3354 | "%g1", frame_base_name); | |
3355 | } | |
3356 | } | |
3357 | \f | |
3358 | /* Do any necessary cleanup after a function to restore stack, frame, | |
3359 | and regs. */ | |
3360 | ||
3361 | void | |
3362 | sparc_frw_output_function_epilogue (file, size, ignored1, ignored2) | |
3363 | FILE *file; | |
3364 | int size; | |
3365 | { | |
3366 | extern FILE *asm_out_data_file, *asm_out_file; | |
3367 | extern char call_used_regs[]; | |
3368 | extern int frame_pointer_needed; | |
3369 | int tsize; | |
3370 | char *sp_str = reg_names[STACK_POINTER_REGNUM]; | |
3371 | char *t1_str = "%g1"; | |
3372 | rtx epilogue_delay = current_function_epilogue_delay_list; | |
3373 | int noepilogue = FALSE; | |
c819be5b JW |
3374 | |
3375 | /* The epilogue does not depend on any registers, but the stack | |
3376 | registers, so we assume that if we have 1 pending nop, it can be | |
3377 | ignored, and 2 it must be filled (2 nops occur for integer | |
3378 | multiply and divide). */ | |
3379 | ||
3380 | size = SPARC_STACK_ALIGN (size); | |
3381 | tsize = (!current_frame_info.initialized | |
3382 | ? sparc_frw_compute_frame_size (size) | |
3383 | : current_frame_info.total_size); | |
3384 | ||
3385 | if (tsize == 0 && epilogue_delay == 0) | |
3386 | { | |
3387 | rtx insn = get_last_insn (); | |
3388 | ||
3389 | /* If the last insn was a BARRIER, we don't have to write any code | |
3390 | because a jump (aka return) was put there. */ | |
3391 | if (GET_CODE (insn) == NOTE) | |
3392 | insn = prev_nonnote_insn (insn); | |
3393 | if (insn && GET_CODE (insn) == BARRIER) | |
3394 | noepilogue = TRUE; | |
3395 | } | |
3396 | ||
3397 | if (!noepilogue) | |
3398 | { | |
3399 | /* In the reload sequence, we don't need to fill the load delay | |
3400 | slots for most of the loads, also see if we can fill the final | |
3401 | delay slot if not otherwise filled by the reload sequence. */ | |
3402 | ||
3403 | if (tsize > 4095) | |
3404 | fprintf (file, "\tset %d,%s\n", tsize, t1_str); | |
3405 | ||
3406 | if (frame_pointer_needed) | |
3407 | { | |
3408 | char *fp_str = reg_names[FRAME_POINTER_REGNUM]; | |
3409 | if (tsize > 4095) | |
3410 | fprintf (file,"\tsub %s,%s,%s\t\t!# sp not trusted here\n", | |
3411 | fp_str, t1_str, sp_str); | |
3412 | else | |
3413 | fprintf (file,"\tsub %s,%d,%s\t\t!# sp not trusted here\n", | |
3414 | fp_str, tsize, sp_str); | |
3415 | } | |
3416 | ||
3417 | sparc_frw_save_restore (file, "ld", "ldd"); | |
3418 | ||
c819be5b JW |
3419 | if (current_function_returns_struct) |
3420 | fprintf (file, "\tjmp %%o7+12\n"); | |
3421 | else | |
3422 | fprintf (file, "\tretl\n"); | |
3423 | ||
3424 | /* If the only register saved is the return address, we need a | |
3425 | nop, unless we have an instruction to put into it. Otherwise | |
3426 | we don't since reloading multiple registers doesn't reference | |
3427 | the register being loaded. */ | |
3428 | ||
3429 | if (epilogue_delay) | |
3430 | { | |
3431 | if (tsize) | |
3432 | abort (); | |
3433 | final_scan_insn (XEXP (epilogue_delay, 0), file, 1, -2, 1); | |
3434 | } | |
3435 | ||
3436 | else if (tsize > 4095) | |
3437 | fprintf (file, "\tadd %s,%s,%s\n", sp_str, t1_str, sp_str); | |
3438 | ||
3439 | else if (tsize > 0) | |
3440 | fprintf (file, "\tadd %s,%d,%s\n", sp_str, tsize, sp_str); | |
3441 | ||
3442 | else | |
3443 | fprintf (file, "\tnop\n"); | |
3444 | } | |
3445 | ||
3446 | /* Reset state info for each function. */ | |
3447 | current_frame_info = zero_frame_info; | |
3448 | } | |
3449 | \f | |
3450 | /* Define the number of delay slots needed for the function epilogue. | |
3451 | ||
3452 | On the sparc, we need a slot if either no stack has been allocated, | |
3453 | or the only register saved is the return register. */ | |
3454 | ||
3455 | int | |
3456 | sparc_frw_epilogue_delay_slots () | |
3457 | { | |
3458 | if (!current_frame_info.initialized) | |
3459 | (void) sparc_frw_compute_frame_size (get_frame_size ()); | |
3460 | ||
3461 | if (current_frame_info.total_size == 0) | |
3462 | return 1; | |
3463 | ||
c819be5b JW |
3464 | return 0; |
3465 | } | |
3466 | ||
3467 | /* Return true is TRIAL is a valid insn for the epilogue delay slot. | |
3468 | Any single length instruction which doesn't reference the stack or frame | |
3469 | pointer is OK. */ | |
3470 | ||
3471 | int | |
3472 | sparc_frw_eligible_for_epilogue_delay (trial, slot) | |
3473 | rtx trial; | |
3474 | int slot; | |
3475 | { | |
3476 | if (get_attr_length (trial) == 1 | |
3477 | && ! reg_mentioned_p (stack_pointer_rtx, PATTERN (trial)) | |
3478 | && ! reg_mentioned_p (frame_pointer_rtx, PATTERN (trial))) | |
3479 | return 1; | |
3480 | return 0; | |
3481 | } |