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ab835497 | 1 | /* Subroutines for insn-output.c for Sun SPARC. |
b0468b84 | 2 | Copyright (C) 1987, 88, 89, 92, 93, 1994 Free Software Foundation, Inc. |
ab835497 | 3 | Contributed by Michael Tiemann (tiemann@cygnus.com) |
61a55e8b DE |
4 | 64 bit SPARC V9 support by Michael Tiemann, Jim Wilson, and Doug Evans, |
5 | at Cygnus Support. | |
ab835497 RK |
6 | |
7 | This file is part of GNU CC. | |
8 | ||
9 | GNU CC is free software; you can redistribute it and/or modify | |
10 | it under the terms of the GNU General Public License as published by | |
11 | the Free Software Foundation; either version 2, or (at your option) | |
12 | any later version. | |
13 | ||
14 | GNU CC is distributed in the hope that it will be useful, | |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
18 | ||
19 | You should have received a copy of the GNU General Public License | |
20 | along with GNU CC; see the file COPYING. If not, write to | |
21 | the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ | |
22 | ||
23 | #include <stdio.h> | |
24 | #include "config.h" | |
210aa14a | 25 | #include "tree.h" |
ab835497 RK |
26 | #include "rtl.h" |
27 | #include "regs.h" | |
28 | #include "hard-reg-set.h" | |
29 | #include "real.h" | |
30 | #include "insn-config.h" | |
31 | #include "conditions.h" | |
32 | #include "insn-flags.h" | |
33 | #include "output.h" | |
34 | #include "insn-attr.h" | |
35 | #include "flags.h" | |
36 | #include "expr.h" | |
37 | #include "recog.h" | |
38 | ||
61a55e8b DE |
39 | /* 1 if the caller has placed an "unimp" insn immediately after the call. |
40 | This is used in v8 code when calling a function that returns a structure. | |
41 | v9 doesn't have this. */ | |
42 | ||
43 | #define SKIP_CALLERS_UNIMP_P (!TARGET_V9 && current_function_returns_struct) | |
44 | ||
ab835497 RK |
45 | /* Global variables for machine-dependent things. */ |
46 | ||
dbb54862 JW |
47 | /* Says what architecture we're compiling for. */ |
48 | enum arch_type sparc_arch_type; | |
61a55e8b DE |
49 | |
50 | /* Size of frame. Need to know this to emit return insns from leaf procedures. | |
51 | ACTUAL_FSIZE is set by compute_frame_size() which is called during the | |
52 | reload pass. This is important as the value is later used in insn | |
53 | scheduling (to see what can go in a delay slot). | |
54 | APPARENT_FSIZE is the size of the stack less the register save area and less | |
55 | the outgoing argument area. It is used when saving call preserved regs. */ | |
56 | static int apparent_fsize; | |
57 | static int actual_fsize; | |
58 | ||
ab835497 RK |
59 | /* Save the operands last given to a compare for use when we |
60 | generate a scc or bcc insn. */ | |
61 | ||
62 | rtx sparc_compare_op0, sparc_compare_op1; | |
63 | ||
61a55e8b DE |
64 | /* Count of named arguments (v9 only). |
65 | ??? INIT_CUMULATIVE_ARGS initializes these, and FUNCTION_ARG_ADVANCE | |
66 | increments SPARC_ARG_COUNT. They are then used by | |
67 | FUNCTION_ARG_CALLEE_COPIES to determine if the argument is really a named | |
68 | argument or not. This hack is necessary because the NAMED argument to the | |
69 | FUNCTION_ARG_XXX macros is not what it says it is: it does not include the | |
70 | last named argument. */ | |
71 | ||
72 | int sparc_arg_count; | |
73 | int sparc_n_named_args; | |
74 | ||
ab835497 RK |
75 | /* We may need an epilogue if we spill too many registers. |
76 | If this is non-zero, then we branch here for the epilogue. */ | |
77 | static rtx leaf_label; | |
78 | ||
79 | #ifdef LEAF_REGISTERS | |
80 | ||
81 | /* Vector to say how input registers are mapped to output | |
82 | registers. FRAME_POINTER_REGNUM cannot be remapped by | |
83 | this function to eliminate it. You must use -fomit-frame-pointer | |
84 | to get that. */ | |
85 | char leaf_reg_remap[] = | |
86 | { 0, 1, 2, 3, 4, 5, 6, 7, | |
87 | -1, -1, -1, -1, -1, -1, 14, -1, | |
88 | -1, -1, -1, -1, -1, -1, -1, -1, | |
89 | 8, 9, 10, 11, 12, 13, -1, 15, | |
90 | ||
91 | 32, 33, 34, 35, 36, 37, 38, 39, | |
92 | 40, 41, 42, 43, 44, 45, 46, 47, | |
93 | 48, 49, 50, 51, 52, 53, 54, 55, | |
61a55e8b DE |
94 | 56, 57, 58, 59, 60, 61, 62, 63, |
95 | 64, 65, 66, 67, 68, 69, 70, 71, | |
96 | 72, 73, 74, 75, 76, 77, 78, 79, | |
97 | 80, 81, 82, 83, 84, 85, 86, 87, | |
98 | 88, 89, 90, 91, 92, 93, 94, 95, | |
99 | 96, 97, 98, 99}; | |
ab835497 | 100 | |
6a4bb1fa | 101 | #endif |
ab835497 | 102 | |
ab835497 RK |
103 | /* Name of where we pretend to think the frame pointer points. |
104 | Normally, this is "%fp", but if we are in a leaf procedure, | |
61a55e8b DE |
105 | this is "%sp+something". We record "something" separately as it may be |
106 | too big for reg+constant addressing. */ | |
107 | ||
108 | static char *frame_base_name; | |
109 | static int frame_base_offset; | |
ab835497 RK |
110 | |
111 | static rtx find_addr_reg (); | |
61a55e8b DE |
112 | static void sparc_init_modes (); |
113 | \f | |
114 | /* Option handling. */ | |
115 | ||
61a55e8b DE |
116 | /* Validate and override various options, and do some machine dependent |
117 | initialization. */ | |
118 | ||
119 | void | |
120 | sparc_override_options () | |
121 | { | |
61a55e8b DE |
122 | /* Check for any conflicts in the choice of options. */ |
123 | /* ??? This stuff isn't really usable yet. */ | |
124 | ||
125 | if (! TARGET_V9) | |
126 | { | |
00dc0e0a JW |
127 | if (target_flags & MASK_CODE_MODEL) |
128 | error ("code model support is only available with -mv9"); | |
61a55e8b DE |
129 | if (TARGET_INT64) |
130 | error ("-mint64 is only available with -mv9"); | |
131 | if (TARGET_LONG64) | |
132 | error ("-mlong64 is only available with -mv9"); | |
133 | if (TARGET_PTR64) | |
134 | error ("-mptr64 is only available with -mv9"); | |
135 | if (TARGET_ENV32) | |
136 | error ("-menv32 is only available with -mv9"); | |
137 | if (TARGET_STACK_BIAS) | |
138 | error ("-mstack-bias is only available with -mv9"); | |
139 | } | |
140 | else | |
141 | { | |
142 | /* ??? Are there any options that aren't usable with v9. | |
143 | -munaligned-doubles? */ | |
144 | } | |
145 | ||
146 | /* Check for conflicts in cpu specification. | |
147 | If we use -mcpu=xxx, this can be removed. */ | |
148 | ||
149 | if ((TARGET_V8 != 0) + (TARGET_SPARCLITE != 0) + (TARGET_V9 != 0) > 1) | |
150 | error ("conflicting architectures defined"); | |
151 | ||
152 | /* Do various machine dependent initializations. */ | |
153 | sparc_init_modes (); | |
154 | } | |
155 | \f | |
156 | /* Float conversions (v9 only). | |
157 | ||
158 | The floating point registers cannot hold DImode values because SUBREG's | |
159 | on them get the wrong register. "(subreg:SI (reg:DI M int-reg) 0)" is the | |
160 | same as "(subreg:SI (reg:DI N float-reg) 1)", but gcc doesn't know how to | |
161 | turn the "0" to a "1". Therefore, we must explicitly do the conversions | |
162 | to/from int/fp regs. `sparc64_fpconv_stack_slot' is the address of an | |
163 | 8 byte stack slot used during the transfer. | |
164 | ??? I could have used [%fp-16] but I didn't want to add yet another | |
165 | dependence on this. */ | |
166 | /* ??? Can we use assign_stack_temp here? */ | |
167 | ||
168 | static rtx fpconv_stack_temp; | |
169 | ||
170 | /* Called once for each function. */ | |
171 | ||
172 | void | |
173 | sparc64_init_expanders () | |
174 | { | |
175 | fpconv_stack_temp = NULL_RTX; | |
176 | } | |
177 | ||
178 | /* Assign a stack temp for fp/int DImode conversions. */ | |
ab835497 | 179 | |
61a55e8b DE |
180 | rtx |
181 | sparc64_fpconv_stack_temp () | |
182 | { | |
183 | if (fpconv_stack_temp == NULL_RTX) | |
184 | fpconv_stack_temp = | |
185 | assign_stack_local (DImode, GET_MODE_SIZE (DImode), 0); | |
186 | ||
187 | return fpconv_stack_temp; | |
188 | } | |
189 | \f | |
ab835497 RK |
190 | /* Return non-zero only if OP is a register of mode MODE, |
191 | or const0_rtx. */ | |
192 | int | |
193 | reg_or_0_operand (op, mode) | |
194 | rtx op; | |
195 | enum machine_mode mode; | |
196 | { | |
197 | if (op == const0_rtx || register_operand (op, mode)) | |
198 | return 1; | |
5b486ce0 | 199 | if (GET_MODE (op) == VOIDmode && GET_CODE (op) == CONST_DOUBLE |
ab835497 RK |
200 | && CONST_DOUBLE_HIGH (op) == 0 |
201 | && CONST_DOUBLE_LOW (op) == 0) | |
202 | return 1; | |
302484ff JW |
203 | if (GET_MODE_CLASS (GET_MODE (op)) == MODE_FLOAT |
204 | && GET_CODE (op) == CONST_DOUBLE | |
205 | && fp_zero_operand (op)) | |
206 | return 1; | |
ab835497 RK |
207 | return 0; |
208 | } | |
209 | ||
302484ff JW |
210 | /* Nonzero if OP is a floating point value with value 0.0. */ |
211 | int | |
212 | fp_zero_operand (op) | |
213 | rtx op; | |
214 | { | |
215 | REAL_VALUE_TYPE r; | |
216 | ||
217 | REAL_VALUE_FROM_CONST_DOUBLE (r, op); | |
218 | return REAL_VALUES_EQUAL (r, dconst0); | |
219 | } | |
220 | ||
61a55e8b DE |
221 | /* Nonzero if OP is an integer register. */ |
222 | ||
223 | int | |
224 | intreg_operand (op, mode) | |
225 | rtx op; | |
226 | enum machine_mode mode; | |
227 | { | |
228 | return (register_operand (op, SImode) | |
229 | || (TARGET_V9 && register_operand (op, DImode))); | |
230 | } | |
231 | ||
232 | /* Nonzero if OP is a floating point condition code register. */ | |
233 | ||
234 | int | |
235 | ccfp_reg_operand (op, mode) | |
236 | rtx op; | |
237 | enum machine_mode mode; | |
238 | { | |
239 | /* This can happen when recog is called from combine. Op may be a MEM. | |
240 | Fail instead of calling abort in this case. */ | |
241 | if (GET_CODE (op) != REG || REGNO (op) == 0) | |
242 | return 0; | |
243 | if (GET_MODE (op) != mode) | |
244 | return 0; | |
245 | ||
246 | #if 0 /* ??? ==> 1 when %fcc1-3 are pseudos first. See gen_compare_reg(). */ | |
247 | if (reg_renumber == 0) | |
248 | return REGNO (op) >= FIRST_PSEUDO_REGISTER; | |
249 | return REGNO_OK_FOR_CCFP_P (REGNO (op)); | |
250 | #else | |
251 | return (unsigned) REGNO (op) - 96 < 4; | |
252 | #endif | |
253 | } | |
254 | ||
ab835497 RK |
255 | /* Nonzero if OP can appear as the dest of a RESTORE insn. */ |
256 | int | |
257 | restore_operand (op, mode) | |
258 | rtx op; | |
259 | enum machine_mode mode; | |
260 | { | |
261 | return (GET_CODE (op) == REG && GET_MODE (op) == mode | |
262 | && (REGNO (op) < 8 || (REGNO (op) >= 24 && REGNO (op) < 32))); | |
263 | } | |
264 | ||
401cec23 JW |
265 | /* Call insn on SPARC can take a PC-relative constant address, or any regular |
266 | memory address. */ | |
ab835497 RK |
267 | |
268 | int | |
269 | call_operand (op, mode) | |
270 | rtx op; | |
271 | enum machine_mode mode; | |
272 | { | |
273 | if (GET_CODE (op) != MEM) | |
274 | abort (); | |
275 | op = XEXP (op, 0); | |
2445f289 | 276 | return (symbolic_operand (op, mode) || memory_address_p (Pmode, op)); |
ab835497 RK |
277 | } |
278 | ||
279 | int | |
280 | call_operand_address (op, mode) | |
281 | rtx op; | |
282 | enum machine_mode mode; | |
283 | { | |
2445f289 | 284 | return (symbolic_operand (op, mode) || memory_address_p (Pmode, op)); |
ab835497 RK |
285 | } |
286 | ||
287 | /* Returns 1 if OP is either a symbol reference or a sum of a symbol | |
288 | reference and a constant. */ | |
289 | ||
290 | int | |
291 | symbolic_operand (op, mode) | |
292 | register rtx op; | |
293 | enum machine_mode mode; | |
294 | { | |
295 | switch (GET_CODE (op)) | |
296 | { | |
297 | case SYMBOL_REF: | |
298 | case LABEL_REF: | |
299 | return 1; | |
300 | ||
301 | case CONST: | |
302 | op = XEXP (op, 0); | |
303 | return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF | |
304 | || GET_CODE (XEXP (op, 0)) == LABEL_REF) | |
305 | && GET_CODE (XEXP (op, 1)) == CONST_INT); | |
306 | ||
228b4037 | 307 | /* ??? This clause seems to be irrelevant. */ |
ab835497 RK |
308 | case CONST_DOUBLE: |
309 | return GET_MODE (op) == mode; | |
310 | ||
311 | default: | |
312 | return 0; | |
313 | } | |
314 | } | |
315 | ||
316 | /* Return truth value of statement that OP is a symbolic memory | |
317 | operand of mode MODE. */ | |
318 | ||
319 | int | |
320 | symbolic_memory_operand (op, mode) | |
321 | rtx op; | |
322 | enum machine_mode mode; | |
323 | { | |
324 | if (GET_CODE (op) == SUBREG) | |
325 | op = SUBREG_REG (op); | |
326 | if (GET_CODE (op) != MEM) | |
327 | return 0; | |
328 | op = XEXP (op, 0); | |
329 | return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST | |
330 | || GET_CODE (op) == HIGH || GET_CODE (op) == LABEL_REF); | |
331 | } | |
332 | ||
61a55e8b DE |
333 | /* Return 1 if the operand is a data segment reference. This includes |
334 | the readonly data segment, or in other words anything but the text segment. | |
335 | This is needed in the medium/anywhere code model on v9. These values | |
336 | are accessed with MEDANY_BASE_REG. */ | |
337 | ||
338 | int | |
339 | data_segment_operand (op, mode) | |
340 | rtx op; | |
341 | enum machine_mode mode; | |
342 | { | |
343 | switch (GET_CODE (op)) | |
344 | { | |
345 | case SYMBOL_REF : | |
346 | return ! SYMBOL_REF_FLAG (op); | |
347 | case PLUS : | |
348 | /* Assume canonical format of symbol + constant. */ | |
349 | case CONST : | |
350 | return data_segment_operand (XEXP (op, 0)); | |
351 | default : | |
352 | return 0; | |
353 | } | |
354 | } | |
355 | ||
356 | /* Return 1 if the operand is a text segment reference. | |
357 | This is needed in the medium/anywhere code model on v9. */ | |
358 | ||
359 | int | |
360 | text_segment_operand (op, mode) | |
361 | rtx op; | |
362 | enum machine_mode mode; | |
363 | { | |
364 | switch (GET_CODE (op)) | |
365 | { | |
366 | case LABEL_REF : | |
367 | return 1; | |
368 | case SYMBOL_REF : | |
369 | return SYMBOL_REF_FLAG (op); | |
370 | case PLUS : | |
371 | /* Assume canonical format of symbol + constant. */ | |
372 | case CONST : | |
373 | return text_segment_operand (XEXP (op, 0)); | |
374 | default : | |
375 | return 0; | |
376 | } | |
377 | } | |
378 | ||
ab835497 RK |
379 | /* Return 1 if the operand is either a register or a memory operand that is |
380 | not symbolic. */ | |
381 | ||
382 | int | |
383 | reg_or_nonsymb_mem_operand (op, mode) | |
384 | register rtx op; | |
385 | enum machine_mode mode; | |
386 | { | |
387 | if (register_operand (op, mode)) | |
388 | return 1; | |
389 | ||
390 | if (memory_operand (op, mode) && ! symbolic_memory_operand (op, mode)) | |
391 | return 1; | |
392 | ||
393 | return 0; | |
394 | } | |
395 | ||
396 | int | |
397 | sparc_operand (op, mode) | |
398 | rtx op; | |
399 | enum machine_mode mode; | |
400 | { | |
401 | if (register_operand (op, mode)) | |
402 | return 1; | |
403 | if (GET_CODE (op) == CONST_INT) | |
404 | return SMALL_INT (op); | |
405 | if (GET_MODE (op) != mode) | |
406 | return 0; | |
407 | if (GET_CODE (op) == SUBREG) | |
408 | op = SUBREG_REG (op); | |
409 | if (GET_CODE (op) != MEM) | |
410 | return 0; | |
411 | ||
412 | op = XEXP (op, 0); | |
413 | if (GET_CODE (op) == LO_SUM) | |
414 | return (GET_CODE (XEXP (op, 0)) == REG | |
415 | && symbolic_operand (XEXP (op, 1), Pmode)); | |
416 | return memory_address_p (mode, op); | |
417 | } | |
418 | ||
419 | int | |
420 | move_operand (op, mode) | |
421 | rtx op; | |
422 | enum machine_mode mode; | |
423 | { | |
424 | if (mode == DImode && arith_double_operand (op, mode)) | |
425 | return 1; | |
426 | if (register_operand (op, mode)) | |
427 | return 1; | |
428 | if (GET_CODE (op) == CONST_INT) | |
429 | return (SMALL_INT (op) || (INTVAL (op) & 0x3ff) == 0); | |
430 | ||
431 | if (GET_MODE (op) != mode) | |
432 | return 0; | |
433 | if (GET_CODE (op) == SUBREG) | |
434 | op = SUBREG_REG (op); | |
435 | if (GET_CODE (op) != MEM) | |
436 | return 0; | |
437 | op = XEXP (op, 0); | |
438 | if (GET_CODE (op) == LO_SUM) | |
439 | return (register_operand (XEXP (op, 0), Pmode) | |
440 | && CONSTANT_P (XEXP (op, 1))); | |
441 | return memory_address_p (mode, op); | |
442 | } | |
443 | ||
444 | int | |
445 | move_pic_label (op, mode) | |
446 | rtx op; | |
447 | enum machine_mode mode; | |
448 | { | |
449 | /* Special case for PIC. */ | |
450 | if (flag_pic && GET_CODE (op) == LABEL_REF) | |
451 | return 1; | |
452 | return 0; | |
453 | } | |
ab835497 RK |
454 | |
455 | int | |
456 | memop (op, mode) | |
457 | rtx op; | |
458 | enum machine_mode mode; | |
459 | { | |
460 | if (GET_CODE (op) == MEM) | |
461 | return (mode == VOIDmode || mode == GET_MODE (op)); | |
462 | return 0; | |
463 | } | |
464 | ||
465 | /* Return truth value of whether OP is EQ or NE. */ | |
466 | ||
467 | int | |
468 | eq_or_neq (op, mode) | |
469 | rtx op; | |
470 | enum machine_mode mode; | |
471 | { | |
472 | return (GET_CODE (op) == EQ || GET_CODE (op) == NE); | |
473 | } | |
474 | ||
475 | /* Return 1 if this is a comparison operator, but not an EQ, NE, GEU, | |
476 | or LTU for non-floating-point. We handle those specially. */ | |
477 | ||
478 | int | |
479 | normal_comp_operator (op, mode) | |
480 | rtx op; | |
481 | enum machine_mode mode; | |
482 | { | |
483 | enum rtx_code code = GET_CODE (op); | |
484 | ||
485 | if (GET_RTX_CLASS (code) != '<') | |
486 | return 0; | |
487 | ||
4d449554 JW |
488 | if (GET_MODE (XEXP (op, 0)) == CCFPmode |
489 | || GET_MODE (XEXP (op, 0)) == CCFPEmode) | |
ab835497 RK |
490 | return 1; |
491 | ||
492 | return (code != NE && code != EQ && code != GEU && code != LTU); | |
493 | } | |
494 | ||
495 | /* Return 1 if this is a comparison operator. This allows the use of | |
496 | MATCH_OPERATOR to recognize all the branch insns. */ | |
497 | ||
498 | int | |
499 | noov_compare_op (op, mode) | |
500 | register rtx op; | |
501 | enum machine_mode mode; | |
502 | { | |
503 | enum rtx_code code = GET_CODE (op); | |
504 | ||
505 | if (GET_RTX_CLASS (code) != '<') | |
506 | return 0; | |
507 | ||
508 | if (GET_MODE (XEXP (op, 0)) == CC_NOOVmode) | |
509 | /* These are the only branches which work with CC_NOOVmode. */ | |
510 | return (code == EQ || code == NE || code == GE || code == LT); | |
511 | return 1; | |
512 | } | |
513 | ||
61a55e8b DE |
514 | /* Nonzero if OP is a comparison operator suitable for use in v9 |
515 | conditional move or branch on register contents instructions. */ | |
516 | ||
517 | int | |
518 | v9_regcmp_op (op, mode) | |
519 | register rtx op; | |
520 | enum machine_mode mode; | |
521 | { | |
522 | enum rtx_code code = GET_CODE (op); | |
523 | ||
524 | if (GET_RTX_CLASS (code) != '<') | |
525 | return 0; | |
526 | ||
527 | return (code == EQ || code == NE || code == GE || code == LT | |
528 | || code == LE || code == GT); | |
529 | } | |
530 | ||
ab835497 RK |
531 | /* Return 1 if this is a SIGN_EXTEND or ZERO_EXTEND operation. */ |
532 | ||
533 | int | |
534 | extend_op (op, mode) | |
535 | rtx op; | |
536 | enum machine_mode mode; | |
537 | { | |
538 | return GET_CODE (op) == SIGN_EXTEND || GET_CODE (op) == ZERO_EXTEND; | |
539 | } | |
540 | ||
541 | /* Return nonzero if OP is an operator of mode MODE which can set | |
542 | the condition codes explicitly. We do not include PLUS and MINUS | |
543 | because these require CC_NOOVmode, which we handle explicitly. */ | |
544 | ||
545 | int | |
546 | cc_arithop (op, mode) | |
547 | rtx op; | |
548 | enum machine_mode mode; | |
549 | { | |
550 | if (GET_CODE (op) == AND | |
551 | || GET_CODE (op) == IOR | |
552 | || GET_CODE (op) == XOR) | |
553 | return 1; | |
554 | ||
555 | return 0; | |
556 | } | |
557 | ||
558 | /* Return nonzero if OP is an operator of mode MODE which can bitwise | |
559 | complement its second operand and set the condition codes explicitly. */ | |
560 | ||
561 | int | |
562 | cc_arithopn (op, mode) | |
563 | rtx op; | |
564 | enum machine_mode mode; | |
565 | { | |
566 | /* XOR is not here because combine canonicalizes (xor (not ...) ...) | |
567 | and (xor ... (not ...)) to (not (xor ...)). */ | |
568 | return (GET_CODE (op) == AND | |
569 | || GET_CODE (op) == IOR); | |
570 | } | |
571 | \f | |
228b4037 JW |
572 | /* Return true if OP is a register, or is a CONST_INT that can fit in a 13 |
573 | bit immediate field. This is an acceptable SImode operand for most 3 | |
574 | address instructions. */ | |
ab835497 RK |
575 | |
576 | int | |
577 | arith_operand (op, mode) | |
578 | rtx op; | |
579 | enum machine_mode mode; | |
580 | { | |
581 | return (register_operand (op, mode) | |
582 | || (GET_CODE (op) == CONST_INT && SMALL_INT (op))); | |
583 | } | |
584 | ||
61a55e8b DE |
585 | /* Return true if OP is a register, or is a CONST_INT that can fit in an 11 |
586 | bit immediate field. This is an acceptable SImode operand for the movcc | |
587 | instructions. */ | |
588 | ||
589 | int | |
590 | arith11_operand (op, mode) | |
591 | rtx op; | |
592 | enum machine_mode mode; | |
593 | { | |
594 | return (register_operand (op, mode) | |
595 | || (GET_CODE (op) == CONST_INT | |
596 | && ((unsigned) (INTVAL (op) + 0x400) < 0x800))); | |
597 | } | |
598 | ||
599 | /* Return true if OP is a register, or is a CONST_INT that can fit in an 10 | |
600 | bit immediate field. This is an acceptable SImode operand for the movrcc | |
601 | instructions. */ | |
602 | ||
603 | int | |
604 | arith10_operand (op, mode) | |
605 | rtx op; | |
606 | enum machine_mode mode; | |
607 | { | |
608 | return (register_operand (op, mode) | |
609 | || (GET_CODE (op) == CONST_INT | |
610 | && ((unsigned) (INTVAL (op) + 0x200) < 0x400))); | |
611 | } | |
612 | ||
23b8a89f JW |
613 | /* Return true if OP is a register, is a CONST_INT that fits in a 13 bit |
614 | immediate field, or is a CONST_DOUBLE whose both parts fit in a 13 bit | |
61a55e8b DE |
615 | immediate field. |
616 | v9: Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that | |
617 | can fit in a 13 bit immediate field. This is an acceptable DImode operand | |
618 | for most 3 address instructions. */ | |
ab835497 RK |
619 | |
620 | int | |
621 | arith_double_operand (op, mode) | |
622 | rtx op; | |
623 | enum machine_mode mode; | |
624 | { | |
625 | return (register_operand (op, mode) | |
23b8a89f | 626 | || (GET_CODE (op) == CONST_INT && SMALL_INT (op)) |
61a55e8b DE |
627 | || (! TARGET_V9 |
628 | && GET_CODE (op) == CONST_DOUBLE | |
ab835497 | 629 | && (unsigned) (CONST_DOUBLE_LOW (op) + 0x1000) < 0x2000 |
61a55e8b DE |
630 | && (unsigned) (CONST_DOUBLE_HIGH (op) + 0x1000) < 0x2000) |
631 | || (TARGET_V9 | |
632 | && GET_CODE (op) == CONST_DOUBLE | |
633 | && (unsigned) (CONST_DOUBLE_LOW (op) + 0x1000) < 0x2000 | |
634 | && ((CONST_DOUBLE_HIGH (op) == -1 | |
635 | && (CONST_DOUBLE_LOW (op) & 0x1000) == 0x1000) | |
636 | || (CONST_DOUBLE_HIGH (op) == 0 | |
637 | && (CONST_DOUBLE_LOW (op) & 0x1000) == 0)))); | |
638 | } | |
639 | ||
640 | /* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that | |
641 | can fit in an 11 bit immediate field. This is an acceptable DImode | |
642 | operand for the movcc instructions. */ | |
643 | /* ??? Replace with arith11_operand? */ | |
644 | ||
645 | int | |
646 | arith11_double_operand (op, mode) | |
647 | rtx op; | |
648 | enum machine_mode mode; | |
649 | { | |
650 | return (register_operand (op, mode) | |
651 | || (GET_CODE (op) == CONST_DOUBLE | |
652 | && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode) | |
653 | && (unsigned) (CONST_DOUBLE_LOW (op) + 0x400) < 0x800 | |
654 | && ((CONST_DOUBLE_HIGH (op) == -1 | |
655 | && (CONST_DOUBLE_LOW (op) & 0x400) == 0x400) | |
656 | || (CONST_DOUBLE_HIGH (op) == 0 | |
657 | && (CONST_DOUBLE_LOW (op) & 0x400) == 0))) | |
658 | || (GET_CODE (op) == CONST_INT | |
659 | && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode) | |
660 | && (unsigned) (INTVAL (op) + 0x400) < 0x800)); | |
661 | } | |
662 | ||
663 | /* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that | |
664 | can fit in an 10 bit immediate field. This is an acceptable DImode | |
665 | operand for the movrcc instructions. */ | |
666 | /* ??? Replace with arith10_operand? */ | |
667 | ||
668 | int | |
669 | arith10_double_operand (op, mode) | |
670 | rtx op; | |
671 | enum machine_mode mode; | |
672 | { | |
673 | return (register_operand (op, mode) | |
674 | || (GET_CODE (op) == CONST_DOUBLE | |
675 | && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode) | |
676 | && (unsigned) (CONST_DOUBLE_LOW (op) + 0x200) < 0x400 | |
677 | && ((CONST_DOUBLE_HIGH (op) == -1 | |
678 | && (CONST_DOUBLE_LOW (op) & 0x200) == 0x200) | |
679 | || (CONST_DOUBLE_HIGH (op) == 0 | |
680 | && (CONST_DOUBLE_LOW (op) & 0x200) == 0))) | |
681 | || (GET_CODE (op) == CONST_INT | |
682 | && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode) | |
683 | && (unsigned) (INTVAL (op) + 0x200) < 0x400)); | |
ab835497 RK |
684 | } |
685 | ||
686 | /* Return truth value of whether OP is a integer which fits the | |
228b4037 JW |
687 | range constraining immediate operands in most three-address insns, |
688 | which have a 13 bit immediate field. */ | |
ab835497 RK |
689 | |
690 | int | |
691 | small_int (op, mode) | |
692 | rtx op; | |
693 | enum machine_mode mode; | |
694 | { | |
695 | return (GET_CODE (op) == CONST_INT && SMALL_INT (op)); | |
696 | } | |
697 | ||
9b3fad96 JW |
698 | /* Recognize operand values for the umul instruction. That instruction sign |
699 | extends immediate values just like all other sparc instructions, but | |
700 | interprets the extended result as an unsigned number. */ | |
701 | ||
702 | int | |
703 | uns_small_int (op, mode) | |
704 | rtx op; | |
705 | enum machine_mode mode; | |
706 | { | |
707 | #if HOST_BITS_PER_WIDE_INT > 32 | |
708 | /* All allowed constants will fit a CONST_INT. */ | |
709 | return (GET_CODE (op) == CONST_INT | |
710 | && ((INTVAL (op) >= 0 && INTVAL (op) < 0x1000) | |
711 | || (INTVAL (op) >= 0xFFFFF000 && INTVAL (op) < 0x100000000L))); | |
712 | #else | |
713 | return ((GET_CODE (op) == CONST_INT && (unsigned) INTVAL (op) < 0x1000) | |
714 | || (GET_CODE (op) == CONST_DOUBLE | |
715 | && CONST_DOUBLE_HIGH (op) == 0 | |
716 | && (unsigned) CONST_DOUBLE_LOW (op) - 0xFFFFF000 < 0x1000)); | |
717 | #endif | |
718 | } | |
719 | ||
720 | int | |
721 | uns_arith_operand (op, mode) | |
722 | rtx op; | |
723 | enum machine_mode mode; | |
724 | { | |
725 | return register_operand (op, mode) || uns_small_int (op, mode); | |
726 | } | |
727 | ||
ab835497 RK |
728 | /* Return truth value of statement that OP is a call-clobbered register. */ |
729 | int | |
730 | clobbered_register (op, mode) | |
731 | rtx op; | |
732 | enum machine_mode mode; | |
733 | { | |
734 | return (GET_CODE (op) == REG && call_used_regs[REGNO (op)]); | |
735 | } | |
736 | \f | |
737 | /* X and Y are two things to compare using CODE. Emit the compare insn and | |
61a55e8b | 738 | return the rtx for the cc reg in the proper mode. */ |
ab835497 RK |
739 | |
740 | rtx | |
741 | gen_compare_reg (code, x, y) | |
742 | enum rtx_code code; | |
743 | rtx x, y; | |
744 | { | |
679655e6 | 745 | enum machine_mode mode = SELECT_CC_MODE (code, x, y); |
61a55e8b DE |
746 | rtx cc_reg; |
747 | ||
748 | /* ??? We don't have movcc patterns so we cannot generate pseudo regs for the | |
749 | fpcc regs (cse can't tell they're really call clobbered regs and will | |
750 | remove a duplicate comparison even if there is an intervening function | |
751 | call - it will then try to reload the cc reg via an int reg which is why | |
752 | we need the movcc patterns). It is possible to provide the movcc | |
753 | patterns by using the ldxfsr/stxfsr v9 insns. I tried it: you need two | |
754 | registers (say %g1,%g5) and it takes about 6 insns. A better fix would be | |
755 | to tell cse that CCFPE mode registers (even pseudoes) are call | |
756 | clobbered. */ | |
757 | ||
758 | /* ??? This is an experiment. Rather than making changes to cse which may | |
759 | or may not be easy/clean, we do our own cse. This is possible because | |
760 | we will generate hard registers. Cse knows they're call clobbered (it | |
761 | doesn't know the same thing about pseudos). If we guess wrong, no big | |
762 | deal, but if we win, great! */ | |
763 | ||
764 | if (TARGET_V9 && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) | |
765 | #if 1 /* experiment */ | |
766 | { | |
767 | int reg; | |
768 | /* We cycle through the registers to ensure they're all exercised. */ | |
769 | static int next_fpcc_reg = 0; | |
770 | /* Previous x,y for each fpcc reg. */ | |
771 | static rtx prev_args[4][2]; | |
772 | ||
773 | /* Scan prev_args for x,y. */ | |
774 | for (reg = 0; reg < 4; reg++) | |
775 | if (prev_args[reg][0] == x && prev_args[reg][1] == y) | |
776 | break; | |
777 | if (reg == 4) | |
778 | { | |
779 | reg = next_fpcc_reg; | |
780 | prev_args[reg][0] = x; | |
781 | prev_args[reg][1] = y; | |
782 | next_fpcc_reg = (next_fpcc_reg + 1) & 3; | |
783 | } | |
784 | cc_reg = gen_rtx (REG, mode, reg + 96); | |
785 | } | |
786 | #else | |
787 | cc_reg = gen_reg_rtx (mode); | |
788 | #endif /* ! experiment */ | |
789 | else | |
790 | cc_reg = gen_rtx (REG, mode, 0); | |
ab835497 RK |
791 | |
792 | emit_insn (gen_rtx (SET, VOIDmode, cc_reg, | |
793 | gen_rtx (COMPARE, mode, x, y))); | |
794 | ||
795 | return cc_reg; | |
796 | } | |
61a55e8b DE |
797 | |
798 | /* This function is used for v9 only. | |
799 | CODE is the code for an Scc's comparison. | |
800 | OPERANDS[0] is the target of the Scc insn. | |
801 | OPERANDS[1] is the value we compare against const0_rtx (which hasn't | |
802 | been generated yet). | |
803 | ||
804 | This function is needed to turn | |
805 | ||
806 | (set (reg:SI 110) | |
807 | (gt (reg:CCX 0 %g0) | |
808 | (const_int 0))) | |
809 | into | |
810 | (set (reg:SI 110) | |
811 | (gt:DI (reg:CCX 0 %g0) | |
812 | (const_int 0))) | |
813 | ||
814 | IE: The instruction recognizer needs to see the mode of the comparison to | |
815 | find the right instruction. We could use "gt:DI" right in the | |
816 | define_expand, but leaving it out allows us to handle DI, SI, etc. | |
817 | ||
818 | We refer to the global sparc compare operands sparc_compare_op0 and | |
819 | sparc_compare_op1. | |
820 | ||
821 | ??? Some of this is outdated as the scc insns set the mode of the | |
822 | comparison now. | |
823 | ||
824 | ??? We optimize for the case where op1 is 0 and the comparison allows us to | |
825 | use the "movrCC" insns. This reduces the generated code from three to two | |
826 | insns. This way seems too brute force though. Is there a more elegant way | |
827 | to achieve the same effect? | |
828 | ||
829 | Currently, this function always returns 1. ??? Can it ever fail? */ | |
830 | ||
831 | int | |
832 | gen_v9_scc (compare_code, operands) | |
833 | enum rtx_code compare_code; | |
834 | register rtx *operands; | |
835 | { | |
836 | rtx temp; | |
837 | ||
838 | if (GET_MODE_CLASS (GET_MODE (sparc_compare_op0)) == MODE_INT | |
839 | && sparc_compare_op1 == const0_rtx | |
840 | && (compare_code == EQ || compare_code == NE | |
841 | || compare_code == LT || compare_code == LE | |
842 | || compare_code == GT || compare_code == GE)) | |
843 | { | |
844 | /* Special case for op0 != 0. This can be done with one instruction if | |
845 | op0 can be clobbered. We store to a temp, and then clobber the temp, | |
846 | but the combiner will remove the first insn. */ | |
847 | ||
848 | if (compare_code == NE | |
849 | && GET_MODE (operands[0]) == DImode | |
850 | && GET_MODE (sparc_compare_op0) == DImode) | |
851 | { | |
852 | emit_insn (gen_rtx (SET, VOIDmode, operands[0], sparc_compare_op0)); | |
853 | emit_insn (gen_rtx (SET, VOIDmode, operands[0], | |
854 | gen_rtx (IF_THEN_ELSE, VOIDmode, | |
855 | gen_rtx (compare_code, DImode, | |
856 | sparc_compare_op0, const0_rtx), | |
857 | const1_rtx, | |
858 | operands[0]))); | |
859 | return 1; | |
860 | } | |
861 | ||
862 | emit_insn (gen_rtx (SET, VOIDmode, operands[0], const0_rtx)); | |
863 | if (GET_MODE (sparc_compare_op0) != DImode) | |
864 | { | |
865 | temp = gen_reg_rtx (DImode); | |
866 | convert_move (temp, sparc_compare_op0, 0); | |
867 | } | |
868 | else | |
869 | { | |
870 | temp = sparc_compare_op0; | |
871 | } | |
872 | emit_insn (gen_rtx (SET, VOIDmode, operands[0], | |
873 | gen_rtx (IF_THEN_ELSE, VOIDmode, | |
874 | gen_rtx (compare_code, DImode, | |
875 | temp, const0_rtx), | |
876 | const1_rtx, | |
877 | operands[0]))); | |
878 | return 1; | |
879 | } | |
880 | else | |
881 | { | |
882 | operands[1] = gen_compare_reg (compare_code, | |
883 | sparc_compare_op0, sparc_compare_op1); | |
884 | ||
885 | switch (GET_MODE (operands[1])) | |
886 | { | |
887 | case CCmode : | |
888 | case CCXmode : | |
889 | case CCFPEmode : | |
890 | case CCFPmode : | |
891 | break; | |
892 | default : | |
893 | abort (); | |
894 | } | |
895 | emit_insn (gen_rtx (SET, VOIDmode, operands[0], const0_rtx)); | |
896 | emit_insn (gen_rtx (SET, VOIDmode, operands[0], | |
897 | gen_rtx (IF_THEN_ELSE, VOIDmode, | |
898 | gen_rtx (compare_code, | |
899 | GET_MODE (operands[1]), | |
900 | operands[1], const0_rtx), | |
901 | const1_rtx, operands[0]))); | |
902 | return 1; | |
903 | } | |
904 | } | |
905 | ||
906 | /* Emit a conditional jump insn for the v9 architecture using comparison code | |
907 | CODE and jump target LABEL. | |
908 | This function exists to take advantage of the v9 brxx insns. */ | |
909 | ||
910 | void | |
911 | emit_v9_brxx_insn (code, op0, label) | |
912 | enum rtx_code code; | |
913 | rtx op0, label; | |
914 | { | |
915 | emit_jump_insn (gen_rtx (SET, VOIDmode, | |
916 | pc_rtx, | |
917 | gen_rtx (IF_THEN_ELSE, VOIDmode, | |
918 | gen_rtx (code, GET_MODE (op0), | |
919 | op0, const0_rtx), | |
920 | gen_rtx (LABEL_REF, VOIDmode, label), | |
921 | pc_rtx))); | |
922 | } | |
ab835497 RK |
923 | \f |
924 | /* Return nonzero if a return peephole merging return with | |
925 | setting of output register is ok. */ | |
926 | int | |
927 | leaf_return_peephole_ok () | |
928 | { | |
929 | return (actual_fsize == 0); | |
930 | } | |
931 | ||
932 | /* Return nonzero if TRIAL can go into the function epilogue's | |
933 | delay slot. SLOT is the slot we are trying to fill. */ | |
934 | ||
935 | int | |
936 | eligible_for_epilogue_delay (trial, slot) | |
937 | rtx trial; | |
938 | int slot; | |
939 | { | |
ab835497 RK |
940 | rtx pat, src; |
941 | ||
942 | if (slot >= 1) | |
943 | return 0; | |
944 | if (GET_CODE (trial) != INSN | |
945 | || GET_CODE (PATTERN (trial)) != SET) | |
946 | return 0; | |
947 | if (get_attr_length (trial) != 1) | |
948 | return 0; | |
949 | ||
915f619f JW |
950 | /* In the case of a true leaf function, anything can go into the delay slot. |
951 | A delay slot only exists however if the frame size is zero, otherwise | |
952 | we will put an insn to adjust the stack after the return. */ | |
ab835497 RK |
953 | if (leaf_function) |
954 | { | |
955 | if (leaf_return_peephole_ok ()) | |
7c56249d | 956 | return (get_attr_in_uncond_branch_delay (trial) == IN_BRANCH_DELAY_TRUE); |
ab835497 RK |
957 | return 0; |
958 | } | |
959 | ||
960 | /* Otherwise, only operations which can be done in tandem with | |
961 | a `restore' insn can go into the delay slot. */ | |
962 | pat = PATTERN (trial); | |
963 | if (GET_CODE (SET_DEST (pat)) != REG | |
964 | || REGNO (SET_DEST (pat)) == 0 | |
915f619f JW |
965 | || REGNO (SET_DEST (pat)) >= 32 |
966 | || REGNO (SET_DEST (pat)) < 24) | |
ab835497 | 967 | return 0; |
915f619f | 968 | |
ab835497 RK |
969 | src = SET_SRC (pat); |
970 | if (arith_operand (src, GET_MODE (src))) | |
971 | return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (SImode); | |
972 | if (arith_double_operand (src, GET_MODE (src))) | |
973 | return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode); | |
974 | if (GET_CODE (src) == PLUS) | |
975 | { | |
976 | if (register_operand (XEXP (src, 0), SImode) | |
977 | && arith_operand (XEXP (src, 1), SImode)) | |
978 | return 1; | |
979 | if (register_operand (XEXP (src, 1), SImode) | |
980 | && arith_operand (XEXP (src, 0), SImode)) | |
981 | return 1; | |
982 | if (register_operand (XEXP (src, 0), DImode) | |
983 | && arith_double_operand (XEXP (src, 1), DImode)) | |
984 | return 1; | |
985 | if (register_operand (XEXP (src, 1), DImode) | |
986 | && arith_double_operand (XEXP (src, 0), DImode)) | |
987 | return 1; | |
988 | } | |
989 | if (GET_CODE (src) == MINUS | |
990 | && register_operand (XEXP (src, 0), SImode) | |
991 | && small_int (XEXP (src, 1), VOIDmode)) | |
992 | return 1; | |
993 | if (GET_CODE (src) == MINUS | |
994 | && register_operand (XEXP (src, 0), DImode) | |
995 | && !register_operand (XEXP (src, 1), DImode) | |
996 | && arith_double_operand (XEXP (src, 1), DImode)) | |
997 | return 1; | |
998 | return 0; | |
999 | } | |
1000 | ||
1001 | int | |
1002 | short_branch (uid1, uid2) | |
1003 | int uid1, uid2; | |
1004 | { | |
1005 | unsigned int delta = insn_addresses[uid1] - insn_addresses[uid2]; | |
1006 | if (delta + 1024 < 2048) | |
1007 | return 1; | |
1008 | /* warning ("long branch, distance %d", delta); */ | |
1009 | return 0; | |
1010 | } | |
1011 | ||
1012 | /* Return non-zero if REG is not used after INSN. | |
1013 | We assume REG is a reload reg, and therefore does | |
1014 | not live past labels or calls or jumps. */ | |
1015 | int | |
1016 | reg_unused_after (reg, insn) | |
1017 | rtx reg; | |
1018 | rtx insn; | |
1019 | { | |
1020 | enum rtx_code code, prev_code = UNKNOWN; | |
1021 | ||
1022 | while (insn = NEXT_INSN (insn)) | |
1023 | { | |
1024 | if (prev_code == CALL_INSN && call_used_regs[REGNO (reg)]) | |
1025 | return 1; | |
1026 | ||
1027 | code = GET_CODE (insn); | |
1028 | if (GET_CODE (insn) == CODE_LABEL) | |
1029 | return 1; | |
1030 | ||
1031 | if (GET_RTX_CLASS (code) == 'i') | |
1032 | { | |
1033 | rtx set = single_set (insn); | |
1034 | int in_src = set && reg_overlap_mentioned_p (reg, SET_SRC (set)); | |
1035 | if (set && in_src) | |
1036 | return 0; | |
1037 | if (set && reg_overlap_mentioned_p (reg, SET_DEST (set))) | |
1038 | return 1; | |
1039 | if (set == 0 && reg_overlap_mentioned_p (reg, PATTERN (insn))) | |
1040 | return 0; | |
1041 | } | |
1042 | prev_code = code; | |
1043 | } | |
1044 | return 1; | |
1045 | } | |
1046 | \f | |
6a4bb1fa DE |
1047 | /* The rtx for the global offset table which is a special form |
1048 | that *is* a position independent symbolic constant. */ | |
1049 | static rtx pic_pc_rtx; | |
1050 | ||
1051 | /* Ensure that we are not using patterns that are not OK with PIC. */ | |
1052 | ||
1053 | int | |
1054 | check_pic (i) | |
1055 | int i; | |
1056 | { | |
1057 | switch (flag_pic) | |
1058 | { | |
1059 | case 1: | |
1060 | if (GET_CODE (recog_operand[i]) == SYMBOL_REF | |
1061 | || (GET_CODE (recog_operand[i]) == CONST | |
1062 | && ! rtx_equal_p (pic_pc_rtx, recog_operand[i]))) | |
1063 | abort (); | |
1064 | case 2: | |
1065 | default: | |
1066 | return 1; | |
1067 | } | |
1068 | } | |
1069 | ||
1070 | /* Return true if X is an address which needs a temporary register when | |
1071 | reloaded while generating PIC code. */ | |
1072 | ||
1073 | int | |
1074 | pic_address_needs_scratch (x) | |
1075 | rtx x; | |
1076 | { | |
1077 | /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */ | |
1078 | if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS | |
1079 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF | |
1080 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT | |
1081 | && ! SMALL_INT (XEXP (XEXP (x, 0), 1))) | |
1082 | return 1; | |
1083 | ||
1084 | return 0; | |
1085 | } | |
1086 | ||
ab835497 RK |
1087 | /* Legitimize PIC addresses. If the address is already position-independent, |
1088 | we return ORIG. Newly generated position-independent addresses go into a | |
1089 | reg. This is REG if non zero, otherwise we allocate register(s) as | |
7e2feebf | 1090 | necessary. */ |
ab835497 RK |
1091 | |
1092 | rtx | |
7e2feebf | 1093 | legitimize_pic_address (orig, mode, reg) |
ab835497 RK |
1094 | rtx orig; |
1095 | enum machine_mode mode; | |
7e2feebf | 1096 | rtx reg; |
ab835497 RK |
1097 | { |
1098 | if (GET_CODE (orig) == SYMBOL_REF) | |
1099 | { | |
1100 | rtx pic_ref, address; | |
1101 | rtx insn; | |
1102 | ||
1103 | if (reg == 0) | |
1104 | { | |
01c0e9dc | 1105 | if (reload_in_progress || reload_completed) |
ab835497 RK |
1106 | abort (); |
1107 | else | |
1108 | reg = gen_reg_rtx (Pmode); | |
1109 | } | |
1110 | ||
1111 | if (flag_pic == 2) | |
1112 | { | |
1113 | /* If not during reload, allocate another temp reg here for loading | |
1114 | in the address, so that these instructions can be optimized | |
1115 | properly. */ | |
01c0e9dc JW |
1116 | rtx temp_reg = ((reload_in_progress || reload_completed) |
1117 | ? reg : gen_reg_rtx (Pmode)); | |
ab835497 | 1118 | |
b4ac57ab RS |
1119 | /* Must put the SYMBOL_REF inside an UNSPEC here so that cse |
1120 | won't get confused into thinking that these two instructions | |
1121 | are loading in the true address of the symbol. If in the | |
1122 | future a PIC rtx exists, that should be used instead. */ | |
ab835497 | 1123 | emit_insn (gen_rtx (SET, VOIDmode, temp_reg, |
b4ac57ab RS |
1124 | gen_rtx (HIGH, Pmode, |
1125 | gen_rtx (UNSPEC, Pmode, | |
1126 | gen_rtvec (1, orig), | |
1127 | 0)))); | |
ab835497 | 1128 | emit_insn (gen_rtx (SET, VOIDmode, temp_reg, |
b4ac57ab RS |
1129 | gen_rtx (LO_SUM, Pmode, temp_reg, |
1130 | gen_rtx (UNSPEC, Pmode, | |
1131 | gen_rtvec (1, orig), | |
1132 | 0)))); | |
ab835497 RK |
1133 | address = temp_reg; |
1134 | } | |
1135 | else | |
1136 | address = orig; | |
1137 | ||
1138 | pic_ref = gen_rtx (MEM, Pmode, | |
1139 | gen_rtx (PLUS, Pmode, | |
1140 | pic_offset_table_rtx, address)); | |
1141 | current_function_uses_pic_offset_table = 1; | |
1142 | RTX_UNCHANGING_P (pic_ref) = 1; | |
1143 | insn = emit_move_insn (reg, pic_ref); | |
1144 | /* Put a REG_EQUAL note on this insn, so that it can be optimized | |
1145 | by loop. */ | |
1146 | REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_EQUAL, orig, | |
1147 | REG_NOTES (insn)); | |
1148 | return reg; | |
1149 | } | |
1150 | else if (GET_CODE (orig) == CONST) | |
1151 | { | |
1152 | rtx base, offset; | |
1153 | ||
1154 | if (GET_CODE (XEXP (orig, 0)) == PLUS | |
1155 | && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx) | |
1156 | return orig; | |
1157 | ||
1158 | if (reg == 0) | |
1159 | { | |
01c0e9dc | 1160 | if (reload_in_progress || reload_completed) |
ab835497 RK |
1161 | abort (); |
1162 | else | |
1163 | reg = gen_reg_rtx (Pmode); | |
1164 | } | |
1165 | ||
1166 | if (GET_CODE (XEXP (orig, 0)) == PLUS) | |
1167 | { | |
7e2feebf | 1168 | base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg); |
ab835497 | 1169 | offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode, |
7e2feebf | 1170 | base == reg ? 0 : reg); |
ab835497 RK |
1171 | } |
1172 | else | |
1173 | abort (); | |
1174 | ||
1175 | if (GET_CODE (offset) == CONST_INT) | |
1176 | { | |
1177 | if (SMALL_INT (offset)) | |
1178 | return plus_constant_for_output (base, INTVAL (offset)); | |
01c0e9dc | 1179 | else if (! reload_in_progress && ! reload_completed) |
ab835497 | 1180 | offset = force_reg (Pmode, offset); |
ab835497 | 1181 | else |
7e2feebf | 1182 | /* If we reach here, then something is seriously wrong. */ |
ab835497 RK |
1183 | abort (); |
1184 | } | |
1185 | return gen_rtx (PLUS, Pmode, base, offset); | |
1186 | } | |
1187 | else if (GET_CODE (orig) == LABEL_REF) | |
1188 | current_function_uses_pic_offset_table = 1; | |
1189 | ||
1190 | return orig; | |
1191 | } | |
1192 | ||
1193 | /* Set up PIC-specific rtl. This should not cause any insns | |
1194 | to be emitted. */ | |
1195 | ||
1196 | void | |
1197 | initialize_pic () | |
1198 | { | |
1199 | } | |
1200 | ||
1201 | /* Emit special PIC prologues and epilogues. */ | |
1202 | ||
1203 | void | |
1204 | finalize_pic () | |
1205 | { | |
1206 | /* The table we use to reference PIC data. */ | |
1207 | rtx global_offset_table; | |
1208 | /* Labels to get the PC in the prologue of this function. */ | |
1209 | rtx l1, l2; | |
1210 | rtx seq; | |
1211 | int orig_flag_pic = flag_pic; | |
1212 | ||
1213 | if (current_function_uses_pic_offset_table == 0) | |
1214 | return; | |
1215 | ||
1216 | if (! flag_pic) | |
1217 | abort (); | |
1218 | ||
1219 | flag_pic = 0; | |
1220 | l1 = gen_label_rtx (); | |
1221 | l2 = gen_label_rtx (); | |
1222 | ||
1223 | start_sequence (); | |
1224 | ||
1225 | emit_label (l1); | |
1226 | /* Note that we pun calls and jumps here! */ | |
1227 | emit_jump_insn (gen_rtx (PARALLEL, VOIDmode, | |
1228 | gen_rtvec (2, | |
1229 | gen_rtx (SET, VOIDmode, pc_rtx, gen_rtx (LABEL_REF, VOIDmode, l2)), | |
1230 | gen_rtx (SET, VOIDmode, gen_rtx (REG, SImode, 15), gen_rtx (LABEL_REF, VOIDmode, l2))))); | |
1231 | emit_label (l2); | |
1232 | ||
1233 | /* Initialize every time through, since we can't easily | |
1234 | know this to be permanent. */ | |
c4eb2bd7 | 1235 | global_offset_table = gen_rtx (SYMBOL_REF, Pmode, "_GLOBAL_OFFSET_TABLE_"); |
ab835497 RK |
1236 | pic_pc_rtx = gen_rtx (CONST, Pmode, |
1237 | gen_rtx (MINUS, Pmode, | |
1238 | global_offset_table, | |
1239 | gen_rtx (CONST, Pmode, | |
1240 | gen_rtx (MINUS, Pmode, | |
1241 | gen_rtx (LABEL_REF, VOIDmode, l1), | |
1242 | pc_rtx)))); | |
1243 | ||
61a55e8b DE |
1244 | if (Pmode == DImode) |
1245 | emit_insn (gen_rtx (PARALLEL, VOIDmode, | |
1246 | gen_rtvec (2, | |
1247 | gen_rtx (SET, VOIDmode, pic_offset_table_rtx, | |
1248 | gen_rtx (HIGH, Pmode, pic_pc_rtx)), | |
1249 | gen_rtx (CLOBBER, VOIDmode, gen_rtx (REG, Pmode, 1))))); | |
1250 | else | |
1251 | emit_insn (gen_rtx (SET, VOIDmode, pic_offset_table_rtx, | |
1252 | gen_rtx (HIGH, Pmode, pic_pc_rtx))); | |
1253 | ||
ab835497 RK |
1254 | emit_insn (gen_rtx (SET, VOIDmode, |
1255 | pic_offset_table_rtx, | |
1256 | gen_rtx (LO_SUM, Pmode, | |
1257 | pic_offset_table_rtx, pic_pc_rtx))); | |
1258 | emit_insn (gen_rtx (SET, VOIDmode, | |
1259 | pic_offset_table_rtx, | |
1260 | gen_rtx (PLUS, Pmode, | |
1261 | pic_offset_table_rtx, gen_rtx (REG, Pmode, 15)))); | |
1262 | /* emit_insn (gen_rtx (ASM_INPUT, VOIDmode, "!#PROLOGUE# 1")); */ | |
1263 | LABEL_PRESERVE_P (l1) = 1; | |
1264 | LABEL_PRESERVE_P (l2) = 1; | |
1265 | flag_pic = orig_flag_pic; | |
1266 | ||
1267 | seq = gen_sequence (); | |
1268 | end_sequence (); | |
1269 | emit_insn_after (seq, get_insns ()); | |
1270 | ||
1271 | /* Need to emit this whether or not we obey regdecls, | |
1272 | since setjmp/longjmp can cause life info to screw up. */ | |
1273 | emit_insn (gen_rtx (USE, VOIDmode, pic_offset_table_rtx)); | |
1274 | } | |
1275 | \f | |
ab835497 RK |
1276 | /* Emit insns to move operands[1] into operands[0]. |
1277 | ||
1278 | Return 1 if we have written out everything that needs to be done to | |
1279 | do the move. Otherwise, return 0 and the caller will emit the move | |
7e2feebf | 1280 | normally. */ |
ab835497 RK |
1281 | |
1282 | int | |
7e2feebf | 1283 | emit_move_sequence (operands, mode) |
ab835497 RK |
1284 | rtx *operands; |
1285 | enum machine_mode mode; | |
ab835497 RK |
1286 | { |
1287 | register rtx operand0 = operands[0]; | |
1288 | register rtx operand1 = operands[1]; | |
1289 | ||
7e2feebf JW |
1290 | if (CONSTANT_P (operand1) && flag_pic |
1291 | && pic_address_needs_scratch (operand1)) | |
1292 | operands[1] = operand1 = legitimize_pic_address (operand1, mode, 0); | |
1293 | ||
ab835497 RK |
1294 | /* Handle most common case first: storing into a register. */ |
1295 | if (register_operand (operand0, mode)) | |
1296 | { | |
1297 | if (register_operand (operand1, mode) | |
1298 | || (GET_CODE (operand1) == CONST_INT && SMALL_INT (operand1)) | |
1299 | || (GET_CODE (operand1) == CONST_DOUBLE | |
1300 | && arith_double_operand (operand1, DImode)) | |
1301 | || (GET_CODE (operand1) == HIGH && GET_MODE (operand1) != DImode) | |
1302 | /* Only `general_operands' can come here, so MEM is ok. */ | |
1303 | || GET_CODE (operand1) == MEM) | |
1304 | { | |
1305 | /* Run this case quickly. */ | |
1306 | emit_insn (gen_rtx (SET, VOIDmode, operand0, operand1)); | |
1307 | return 1; | |
1308 | } | |
1309 | } | |
1310 | else if (GET_CODE (operand0) == MEM) | |
1311 | { | |
1312 | if (register_operand (operand1, mode) || operand1 == const0_rtx) | |
1313 | { | |
1314 | /* Run this case quickly. */ | |
1315 | emit_insn (gen_rtx (SET, VOIDmode, operand0, operand1)); | |
1316 | return 1; | |
1317 | } | |
1318 | if (! reload_in_progress) | |
1319 | { | |
1320 | operands[0] = validize_mem (operand0); | |
1321 | operands[1] = operand1 = force_reg (mode, operand1); | |
1322 | } | |
1323 | } | |
1324 | ||
1325 | /* Simplify the source if we need to. Must handle DImode HIGH operators | |
1326 | here because such a move needs a clobber added. */ | |
1327 | if ((GET_CODE (operand1) != HIGH && immediate_operand (operand1, mode)) | |
1328 | || (GET_CODE (operand1) == HIGH && GET_MODE (operand1) == DImode)) | |
1329 | { | |
1330 | if (flag_pic && symbolic_operand (operand1, mode)) | |
1331 | { | |
1332 | rtx temp_reg = reload_in_progress ? operand0 : 0; | |
1333 | ||
7e2feebf | 1334 | operands[1] = legitimize_pic_address (operand1, mode, temp_reg); |
ab835497 RK |
1335 | } |
1336 | else if (GET_CODE (operand1) == CONST_INT | |
1337 | ? (! SMALL_INT (operand1) | |
1338 | && (INTVAL (operand1) & 0x3ff) != 0) | |
1339 | : (GET_CODE (operand1) == CONST_DOUBLE | |
1340 | ? ! arith_double_operand (operand1, DImode) | |
1341 | : 1)) | |
1342 | { | |
1343 | /* For DImode values, temp must be operand0 because of the way | |
1344 | HI and LO_SUM work. The LO_SUM operator only copies half of | |
1345 | the LSW from the dest of the HI operator. If the LO_SUM dest is | |
1346 | not the same as the HI dest, then the MSW of the LO_SUM dest will | |
1347 | never be set. | |
1348 | ||
1349 | ??? The real problem here is that the ...(HI:DImode pattern emits | |
1350 | multiple instructions, and the ...(LO_SUM:DImode pattern emits | |
1351 | one instruction. This fails, because the compiler assumes that | |
1352 | LO_SUM copies all bits of the first operand to its dest. Better | |
1353 | would be to have the HI pattern emit one instruction and the | |
1354 | LO_SUM pattern multiple instructions. Even better would be | |
1355 | to use four rtl insns. */ | |
1356 | rtx temp = ((reload_in_progress || mode == DImode) | |
1357 | ? operand0 : gen_reg_rtx (mode)); | |
1358 | ||
61a55e8b DE |
1359 | if (TARGET_V9 && mode == DImode) |
1360 | { | |
1361 | int high_operand = 0; | |
1362 | ||
1363 | /* If the operand is already a HIGH, then remove the HIGH so | |
1364 | that we won't get duplicate HIGH operators in this insn. | |
1365 | Also, we must store the result into the original dest, | |
1366 | because that is where the following LO_SUM expects it. */ | |
1367 | if (GET_CODE (operand1) == HIGH) | |
1368 | { | |
1369 | operand1 = XEXP (operand1, 0); | |
1370 | high_operand = 1; | |
1371 | } | |
1372 | ||
1373 | emit_insn (gen_rtx (PARALLEL, VOIDmode, | |
1374 | gen_rtvec (2, | |
1375 | gen_rtx (SET, VOIDmode, temp, | |
1376 | gen_rtx (HIGH, mode, operand1)), | |
1377 | gen_rtx (CLOBBER, VOIDmode, gen_rtx (REG, DImode, 1))))); | |
1378 | ||
1379 | /* If this was a high operand, then we are now finished. */ | |
1380 | if (high_operand) | |
1381 | return 1; | |
1382 | } | |
1383 | else | |
1384 | emit_insn (gen_rtx (SET, VOIDmode, temp, | |
1385 | gen_rtx (HIGH, mode, operand1))); | |
1386 | ||
ab835497 RK |
1387 | operands[1] = gen_rtx (LO_SUM, mode, temp, operand1); |
1388 | } | |
1389 | } | |
1390 | ||
1391 | if (GET_CODE (operand1) == LABEL_REF && flag_pic) | |
1392 | { | |
1393 | /* The procedure for doing this involves using a call instruction to | |
1394 | get the pc into o7. We need to indicate this explicitly because | |
1395 | the tablejump pattern assumes that it can use this value also. */ | |
1396 | emit_insn (gen_rtx (PARALLEL, VOIDmode, | |
1397 | gen_rtvec (2, | |
1398 | gen_rtx (SET, VOIDmode, operand0, | |
1399 | operand1), | |
1400 | gen_rtx (SET, VOIDmode, | |
1401 | gen_rtx (REG, mode, 15), | |
1402 | pc_rtx)))); | |
1403 | return 1; | |
1404 | } | |
1405 | ||
1406 | /* Now have insn-emit do whatever it normally does. */ | |
1407 | return 0; | |
1408 | } | |
1409 | \f | |
1410 | /* Return the best assembler insn template | |
1411 | for moving operands[1] into operands[0] as a fullword. */ | |
1412 | ||
1413 | char * | |
1414 | singlemove_string (operands) | |
1415 | rtx *operands; | |
1416 | { | |
1417 | if (GET_CODE (operands[0]) == MEM) | |
1418 | { | |
1419 | if (GET_CODE (operands[1]) != MEM) | |
1420 | return "st %r1,%0"; | |
1421 | else | |
1422 | abort (); | |
1423 | } | |
2b9a9aea | 1424 | else if (GET_CODE (operands[1]) == MEM) |
ab835497 | 1425 | return "ld %1,%0"; |
2b9a9aea JW |
1426 | else if (GET_CODE (operands[1]) == CONST_DOUBLE) |
1427 | { | |
c90fb4e6 JW |
1428 | REAL_VALUE_TYPE r; |
1429 | long i; | |
2b9a9aea JW |
1430 | |
1431 | /* Must be SFmode, otherwise this doesn't make sense. */ | |
1432 | if (GET_MODE (operands[1]) != SFmode) | |
1433 | abort (); | |
1434 | ||
c90fb4e6 JW |
1435 | REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]); |
1436 | REAL_VALUE_TO_TARGET_SINGLE (r, i); | |
2b9a9aea JW |
1437 | operands[1] = gen_rtx (CONST_INT, VOIDmode, i); |
1438 | ||
1439 | if (CONST_OK_FOR_LETTER_P (i, 'I')) | |
1440 | return "mov %1,%0"; | |
1441 | else if ((i & 0x000003FF) != 0) | |
1442 | return "sethi %%hi(%a1),%0\n\tor %0,%%lo(%a1),%0"; | |
1443 | else | |
1444 | return "sethi %%hi(%a1),%0"; | |
1445 | } | |
1446 | else if (GET_CODE (operands[1]) == CONST_INT | |
1447 | && ! CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'I')) | |
ab835497 RK |
1448 | { |
1449 | int i = INTVAL (operands[1]); | |
1450 | ||
915f619f | 1451 | /* If all low order 10 bits are clear, then we only need a single |
ab835497 | 1452 | sethi insn to load the constant. */ |
915f619f | 1453 | if ((i & 0x000003FF) != 0) |
ab835497 RK |
1454 | return "sethi %%hi(%a1),%0\n\tor %0,%%lo(%a1),%0"; |
1455 | else | |
1456 | return "sethi %%hi(%a1),%0"; | |
1457 | } | |
2b9a9aea | 1458 | /* Operand 1 must be a register, or a 'I' type CONST_INT. */ |
ab835497 RK |
1459 | return "mov %1,%0"; |
1460 | } | |
1461 | \f | |
795068a4 JW |
1462 | /* Return non-zero if it is OK to assume that the given memory operand is |
1463 | aligned at least to a 8-byte boundary. This should only be called | |
1464 | for memory accesses whose size is 8 bytes or larger. */ | |
1465 | ||
7c56249d | 1466 | int |
795068a4 JW |
1467 | mem_aligned_8 (mem) |
1468 | register rtx mem; | |
1469 | { | |
1470 | register rtx addr; | |
1471 | register rtx base; | |
1472 | register rtx offset; | |
1473 | ||
1474 | if (GET_CODE (mem) != MEM) | |
7c56249d | 1475 | return 0; /* It's gotta be a MEM! */ |
795068a4 JW |
1476 | |
1477 | addr = XEXP (mem, 0); | |
1478 | ||
795068a4 | 1479 | /* Now that all misaligned double parms are copied on function entry, |
1934ceca JW |
1480 | we can assume any 64-bit object is 64-bit aligned except those which |
1481 | are at unaligned offsets from the stack or frame pointer. If the | |
1482 | TARGET_UNALIGNED_DOUBLES switch is given, we do not make this | |
1483 | assumption. */ | |
795068a4 JW |
1484 | |
1485 | /* See what register we use in the address. */ | |
1486 | base = 0; | |
1487 | if (GET_CODE (addr) == PLUS) | |
1488 | { | |
1489 | if (GET_CODE (XEXP (addr, 0)) == REG | |
1490 | && GET_CODE (XEXP (addr, 1)) == CONST_INT) | |
1491 | { | |
1492 | base = XEXP (addr, 0); | |
1493 | offset = XEXP (addr, 1); | |
1494 | } | |
1495 | } | |
1496 | else if (GET_CODE (addr) == REG) | |
1497 | { | |
1498 | base = addr; | |
1499 | offset = const0_rtx; | |
1500 | } | |
1501 | ||
1502 | /* If it's the stack or frame pointer, check offset alignment. | |
2296cba3 | 1503 | We can have improper alignment in the function entry code. */ |
795068a4 JW |
1504 | if (base |
1505 | && (REGNO (base) == FRAME_POINTER_REGNUM | |
1506 | || REGNO (base) == STACK_POINTER_REGNUM)) | |
1507 | { | |
61a55e8b | 1508 | if (((INTVAL (offset) - SPARC_STACK_BIAS) & 0x7) == 0) |
795068a4 JW |
1509 | return 1; |
1510 | } | |
1934ceca JW |
1511 | /* Anything else we know is properly aligned unless TARGET_UNALIGNED_DOUBLES |
1512 | is true, in which case we can only assume that an access is aligned if | |
f5da225e JW |
1513 | it is to a constant address, or the address involves a LO_SUM. |
1514 | ||
1515 | We used to assume an address was aligned if MEM_IN_STRUCT_P was true. | |
1516 | That assumption was deleted so that gcc generated code can be used with | |
1517 | memory allocators that only guarantee 4 byte alignment. */ | |
1518 | else if (! TARGET_UNALIGNED_DOUBLES || CONSTANT_P (addr) | |
1519 | || GET_CODE (addr) == LO_SUM) | |
795068a4 | 1520 | return 1; |
795068a4 JW |
1521 | |
1522 | /* An obviously unaligned address. */ | |
1523 | return 0; | |
1524 | } | |
1525 | ||
1526 | enum optype { REGOP, OFFSOP, MEMOP, PUSHOP, POPOP, CNSTOP, RNDOP }; | |
1527 | ||
ab835497 | 1528 | /* Output assembler code to perform a doubleword move insn |
795068a4 JW |
1529 | with operands OPERANDS. This is very similar to the following |
1530 | output_move_quad function. */ | |
ab835497 RK |
1531 | |
1532 | char * | |
1533 | output_move_double (operands) | |
1534 | rtx *operands; | |
1535 | { | |
795068a4 JW |
1536 | register rtx op0 = operands[0]; |
1537 | register rtx op1 = operands[1]; | |
1538 | register enum optype optype0; | |
1539 | register enum optype optype1; | |
ab835497 | 1540 | rtx latehalf[2]; |
795068a4 JW |
1541 | rtx addreg0 = 0; |
1542 | rtx addreg1 = 0; | |
3b76513a | 1543 | int highest_first = 0; |
f3a9d1e6 | 1544 | int no_addreg1_decrement = 0; |
ab835497 RK |
1545 | |
1546 | /* First classify both operands. */ | |
1547 | ||
795068a4 | 1548 | if (REG_P (op0)) |
ab835497 | 1549 | optype0 = REGOP; |
795068a4 | 1550 | else if (offsettable_memref_p (op0)) |
ab835497 | 1551 | optype0 = OFFSOP; |
795068a4 | 1552 | else if (GET_CODE (op0) == MEM) |
ab835497 RK |
1553 | optype0 = MEMOP; |
1554 | else | |
1555 | optype0 = RNDOP; | |
1556 | ||
795068a4 | 1557 | if (REG_P (op1)) |
ab835497 | 1558 | optype1 = REGOP; |
795068a4 | 1559 | else if (CONSTANT_P (op1)) |
ab835497 | 1560 | optype1 = CNSTOP; |
795068a4 | 1561 | else if (offsettable_memref_p (op1)) |
ab835497 | 1562 | optype1 = OFFSOP; |
795068a4 | 1563 | else if (GET_CODE (op1) == MEM) |
ab835497 RK |
1564 | optype1 = MEMOP; |
1565 | else | |
1566 | optype1 = RNDOP; | |
1567 | ||
1568 | /* Check for the cases that the operand constraints are not | |
1569 | supposed to allow to happen. Abort if we get one, | |
1570 | because generating code for these cases is painful. */ | |
1571 | ||
795068a4 JW |
1572 | if (optype0 == RNDOP || optype1 == RNDOP |
1573 | || (optype0 == MEM && optype1 == MEM)) | |
ab835497 RK |
1574 | abort (); |
1575 | ||
1576 | /* If an operand is an unoffsettable memory ref, find a register | |
1577 | we can increment temporarily to make it refer to the second word. */ | |
1578 | ||
1579 | if (optype0 == MEMOP) | |
795068a4 | 1580 | addreg0 = find_addr_reg (XEXP (op0, 0)); |
ab835497 RK |
1581 | |
1582 | if (optype1 == MEMOP) | |
795068a4 | 1583 | addreg1 = find_addr_reg (XEXP (op1, 0)); |
ab835497 RK |
1584 | |
1585 | /* Ok, we can do one word at a time. | |
795068a4 | 1586 | Set up in LATEHALF the operands to use for the |
ab835497 RK |
1587 | high-numbered (least significant) word and in some cases alter the |
1588 | operands in OPERANDS to be suitable for the low-numbered word. */ | |
1589 | ||
1590 | if (optype0 == REGOP) | |
795068a4 | 1591 | latehalf[0] = gen_rtx (REG, SImode, REGNO (op0) + 1); |
ab835497 | 1592 | else if (optype0 == OFFSOP) |
795068a4 | 1593 | latehalf[0] = adj_offsettable_operand (op0, 4); |
ab835497 | 1594 | else |
795068a4 | 1595 | latehalf[0] = op0; |
ab835497 RK |
1596 | |
1597 | if (optype1 == REGOP) | |
795068a4 | 1598 | latehalf[1] = gen_rtx (REG, SImode, REGNO (op1) + 1); |
ab835497 | 1599 | else if (optype1 == OFFSOP) |
795068a4 | 1600 | latehalf[1] = adj_offsettable_operand (op1, 4); |
ab835497 | 1601 | else if (optype1 == CNSTOP) |
61a55e8b DE |
1602 | { |
1603 | if (TARGET_V9) | |
1604 | { | |
1605 | if (arith_double_operand (op1, DImode)) | |
1606 | { | |
1607 | operands[1] = gen_rtx (CONST_INT, VOIDmode, | |
1608 | CONST_DOUBLE_LOW (op1)); | |
1609 | return "mov %1,%0"; | |
1610 | } | |
1611 | else | |
1612 | { | |
1613 | /* The only way to handle CONST_DOUBLEs or other 64 bit | |
1614 | constants here is to use a temporary, such as is done | |
1615 | for the V9 DImode sethi insn pattern. This is not | |
1616 | a practical solution, so abort if we reach here. | |
1617 | The md file should always force such constants to | |
1618 | memory. */ | |
1619 | abort (); | |
1620 | } | |
1621 | } | |
1622 | else | |
1623 | split_double (op1, &operands[1], &latehalf[1]); | |
1624 | } | |
ab835497 | 1625 | else |
795068a4 | 1626 | latehalf[1] = op1; |
ab835497 | 1627 | |
795068a4 JW |
1628 | /* Easy case: try moving both words at once. Check for moving between |
1629 | an even/odd register pair and a memory location. */ | |
ab835497 | 1630 | if ((optype0 == REGOP && optype1 != REGOP && optype1 != CNSTOP |
61a55e8b | 1631 | && (TARGET_V9 || (REGNO (op0) & 1) == 0)) |
ab835497 | 1632 | || (optype0 != REGOP && optype0 != CNSTOP && optype1 == REGOP |
61a55e8b | 1633 | && (TARGET_V9 || (REGNO (op1) & 1) == 0))) |
ab835497 | 1634 | { |
61a55e8b | 1635 | register rtx mem,reg; |
bc961ed7 RS |
1636 | |
1637 | if (optype0 == REGOP) | |
61a55e8b | 1638 | mem = op1, reg = op0; |
bc961ed7 | 1639 | else |
61a55e8b DE |
1640 | mem = op0, reg = op1; |
1641 | ||
1642 | /* In v9, ldd can be used for word aligned addresses, so technically | |
1643 | some of this logic is unneeded. We still avoid ldd if the address | |
1644 | is obviously unaligned though. */ | |
1645 | ||
1646 | if (mem_aligned_8 (mem) | |
1647 | /* If this is a floating point register higher than %f31, | |
1648 | then we *must* use an aligned load, since `ld' will not accept | |
1649 | the register number. */ | |
1650 | || (TARGET_V9 && REGNO (reg) >= 64)) | |
1651 | { | |
1652 | if (FP_REG_P (reg) || ! TARGET_V9) | |
1653 | return (mem == op1 ? "ldd %1,%0" : "std %1,%0"); | |
1654 | else | |
1655 | return (mem == op1 ? "ldx %1,%0" : "stx %1,%0"); | |
1656 | } | |
1657 | } | |
bc961ed7 | 1658 | |
61a55e8b DE |
1659 | if (TARGET_V9) |
1660 | { | |
1661 | if (optype0 == REGOP && optype1 == REGOP) | |
1662 | { | |
1663 | if (FP_REG_P (op0)) | |
1664 | return "fmovd %1,%0"; | |
1665 | else | |
1666 | return "mov %1,%0"; | |
1667 | } | |
ab835497 RK |
1668 | } |
1669 | ||
795068a4 JW |
1670 | /* If the first move would clobber the source of the second one, |
1671 | do them in the other order. */ | |
1672 | ||
1673 | /* Overlapping registers. */ | |
ab835497 | 1674 | if (optype0 == REGOP && optype1 == REGOP |
795068a4 | 1675 | && REGNO (op0) == REGNO (latehalf[1])) |
ab835497 | 1676 | { |
ab835497 RK |
1677 | /* Do that word. */ |
1678 | output_asm_insn (singlemove_string (latehalf), latehalf); | |
ab835497 RK |
1679 | /* Do low-numbered word. */ |
1680 | return singlemove_string (operands); | |
1681 | } | |
795068a4 | 1682 | /* Loading into a register which overlaps a register used in the address. */ |
ab835497 | 1683 | else if (optype0 == REGOP && optype1 != REGOP |
795068a4 | 1684 | && reg_overlap_mentioned_p (op0, op1)) |
ab835497 | 1685 | { |
f3a9d1e6 JW |
1686 | /* If both halves of dest are used in the src memory address, |
1687 | add the two regs and put them in the low reg (op0). | |
1688 | Then it works to load latehalf first. */ | |
bdec790c RS |
1689 | if (reg_mentioned_p (op0, XEXP (op1, 0)) |
1690 | && reg_mentioned_p (latehalf[0], XEXP (op1, 0))) | |
1691 | { | |
bdec790c RS |
1692 | rtx xops[2]; |
1693 | xops[0] = latehalf[0]; | |
1694 | xops[1] = op0; | |
1695 | output_asm_insn ("add %1,%0,%1", xops); | |
3b76513a | 1696 | operands[1] = gen_rtx (MEM, DImode, op0); |
bdec790c | 1697 | latehalf[1] = adj_offsettable_operand (operands[1], 4); |
3b76513a | 1698 | addreg1 = 0; |
f3a9d1e6 | 1699 | highest_first = 1; |
bdec790c | 1700 | } |
f3a9d1e6 JW |
1701 | /* Only one register in the dest is used in the src memory address, |
1702 | and this is the first register of the dest, so we want to do | |
1703 | the late half first here also. */ | |
1704 | else if (! reg_mentioned_p (latehalf[0], XEXP (op1, 0))) | |
1705 | highest_first = 1; | |
1706 | /* Only one register in the dest is used in the src memory address, | |
1707 | and this is the second register of the dest, so we want to do | |
1708 | the late half last. If addreg1 is set, and addreg1 is the same | |
1709 | register as latehalf, then we must suppress the trailing decrement, | |
1710 | because it would clobber the value just loaded. */ | |
1711 | else if (addreg1 && reg_mentioned_p (addreg1, latehalf[0])) | |
1712 | no_addreg1_decrement = 1; | |
ab835497 RK |
1713 | } |
1714 | ||
3b76513a RS |
1715 | /* Normal case: do the two words, low-numbered first. |
1716 | Overlap case (highest_first set): do high-numbered word first. */ | |
ab835497 | 1717 | |
3b76513a RS |
1718 | if (! highest_first) |
1719 | output_asm_insn (singlemove_string (operands), operands); | |
ab835497 RK |
1720 | |
1721 | /* Make any unoffsettable addresses point at high-numbered word. */ | |
1722 | if (addreg0) | |
1723 | output_asm_insn ("add %0,0x4,%0", &addreg0); | |
1724 | if (addreg1) | |
1725 | output_asm_insn ("add %0,0x4,%0", &addreg1); | |
1726 | ||
1727 | /* Do that word. */ | |
1728 | output_asm_insn (singlemove_string (latehalf), latehalf); | |
1729 | ||
1730 | /* Undo the adds we just did. */ | |
1731 | if (addreg0) | |
1732 | output_asm_insn ("add %0,-0x4,%0", &addreg0); | |
f3a9d1e6 | 1733 | if (addreg1 && ! no_addreg1_decrement) |
ab835497 RK |
1734 | output_asm_insn ("add %0,-0x4,%0", &addreg1); |
1735 | ||
3b76513a RS |
1736 | if (highest_first) |
1737 | output_asm_insn (singlemove_string (operands), operands); | |
1738 | ||
ab835497 RK |
1739 | return ""; |
1740 | } | |
795068a4 JW |
1741 | |
1742 | /* Output assembler code to perform a quadword move insn | |
2296cba3 | 1743 | with operands OPERANDS. This is very similar to the preceding |
795068a4 JW |
1744 | output_move_double function. */ |
1745 | ||
1746 | char * | |
1747 | output_move_quad (operands) | |
1748 | rtx *operands; | |
1749 | { | |
1750 | register rtx op0 = operands[0]; | |
1751 | register rtx op1 = operands[1]; | |
1752 | register enum optype optype0; | |
1753 | register enum optype optype1; | |
1754 | rtx wordpart[4][2]; | |
1755 | rtx addreg0 = 0; | |
1756 | rtx addreg1 = 0; | |
1757 | ||
1758 | /* First classify both operands. */ | |
1759 | ||
1760 | if (REG_P (op0)) | |
1761 | optype0 = REGOP; | |
1762 | else if (offsettable_memref_p (op0)) | |
1763 | optype0 = OFFSOP; | |
1764 | else if (GET_CODE (op0) == MEM) | |
1765 | optype0 = MEMOP; | |
1766 | else | |
1767 | optype0 = RNDOP; | |
1768 | ||
1769 | if (REG_P (op1)) | |
1770 | optype1 = REGOP; | |
1771 | else if (CONSTANT_P (op1)) | |
1772 | optype1 = CNSTOP; | |
1773 | else if (offsettable_memref_p (op1)) | |
1774 | optype1 = OFFSOP; | |
1775 | else if (GET_CODE (op1) == MEM) | |
1776 | optype1 = MEMOP; | |
1777 | else | |
1778 | optype1 = RNDOP; | |
1779 | ||
1780 | /* Check for the cases that the operand constraints are not | |
1781 | supposed to allow to happen. Abort if we get one, | |
1782 | because generating code for these cases is painful. */ | |
1783 | ||
1784 | if (optype0 == RNDOP || optype1 == RNDOP | |
1785 | || (optype0 == MEM && optype1 == MEM)) | |
1786 | abort (); | |
1787 | ||
1788 | /* If an operand is an unoffsettable memory ref, find a register | |
1789 | we can increment temporarily to make it refer to the later words. */ | |
1790 | ||
1791 | if (optype0 == MEMOP) | |
1792 | addreg0 = find_addr_reg (XEXP (op0, 0)); | |
1793 | ||
1794 | if (optype1 == MEMOP) | |
1795 | addreg1 = find_addr_reg (XEXP (op1, 0)); | |
1796 | ||
1797 | /* Ok, we can do one word at a time. | |
1798 | Set up in wordpart the operands to use for each word of the arguments. */ | |
1799 | ||
1800 | if (optype0 == REGOP) | |
1801 | { | |
1802 | wordpart[0][0] = gen_rtx (REG, SImode, REGNO (op0) + 0); | |
1803 | wordpart[1][0] = gen_rtx (REG, SImode, REGNO (op0) + 1); | |
1804 | wordpart[2][0] = gen_rtx (REG, SImode, REGNO (op0) + 2); | |
1805 | wordpart[3][0] = gen_rtx (REG, SImode, REGNO (op0) + 3); | |
1806 | } | |
1807 | else if (optype0 == OFFSOP) | |
1808 | { | |
1809 | wordpart[0][0] = adj_offsettable_operand (op0, 0); | |
1810 | wordpart[1][0] = adj_offsettable_operand (op0, 4); | |
1811 | wordpart[2][0] = adj_offsettable_operand (op0, 8); | |
1812 | wordpart[3][0] = adj_offsettable_operand (op0, 12); | |
1813 | } | |
1814 | else | |
1815 | { | |
1816 | wordpart[0][0] = op0; | |
1817 | wordpart[1][0] = op0; | |
1818 | wordpart[2][0] = op0; | |
1819 | wordpart[3][0] = op0; | |
1820 | } | |
1821 | ||
1822 | if (optype1 == REGOP) | |
1823 | { | |
1824 | wordpart[0][1] = gen_rtx (REG, SImode, REGNO (op1) + 0); | |
1825 | wordpart[1][1] = gen_rtx (REG, SImode, REGNO (op1) + 1); | |
1826 | wordpart[2][1] = gen_rtx (REG, SImode, REGNO (op1) + 2); | |
1827 | wordpart[3][1] = gen_rtx (REG, SImode, REGNO (op1) + 3); | |
1828 | } | |
1829 | else if (optype1 == OFFSOP) | |
1830 | { | |
1831 | wordpart[0][1] = adj_offsettable_operand (op1, 0); | |
1832 | wordpart[1][1] = adj_offsettable_operand (op1, 4); | |
1833 | wordpart[2][1] = adj_offsettable_operand (op1, 8); | |
1834 | wordpart[3][1] = adj_offsettable_operand (op1, 12); | |
1835 | } | |
1836 | else if (optype1 == CNSTOP) | |
1837 | { | |
61a66555 JW |
1838 | REAL_VALUE_TYPE r; |
1839 | long l[4]; | |
1840 | ||
1841 | /* This only works for TFmode floating point constants. */ | |
1842 | if (GET_CODE (op1) != CONST_DOUBLE || GET_MODE (op1) != TFmode) | |
1843 | abort (); | |
1844 | ||
1845 | REAL_VALUE_FROM_CONST_DOUBLE (r, op1); | |
1846 | REAL_VALUE_TO_TARGET_LONG_DOUBLE (r, l); | |
1847 | ||
1848 | wordpart[0][1] = GEN_INT (l[0]); | |
1849 | wordpart[1][1] = GEN_INT (l[1]); | |
1850 | wordpart[2][1] = GEN_INT (l[2]); | |
1851 | wordpart[3][1] = GEN_INT (l[3]); | |
795068a4 JW |
1852 | } |
1853 | else | |
1854 | { | |
1855 | wordpart[0][1] = op1; | |
1856 | wordpart[1][1] = op1; | |
1857 | wordpart[2][1] = op1; | |
1858 | wordpart[3][1] = op1; | |
1859 | } | |
1860 | ||
1861 | /* Easy case: try moving the quad as two pairs. Check for moving between | |
61a55e8b DE |
1862 | an even/odd register pair and a memory location. |
1863 | Also handle new v9 fp regs here. */ | |
795068a4 JW |
1864 | /* ??? Should also handle the case of non-offsettable addresses here. |
1865 | We can at least do the first pair as a ldd/std, and then do the third | |
1866 | and fourth words individually. */ | |
1867 | if ((optype0 == REGOP && optype1 == OFFSOP && (REGNO (op0) & 1) == 0) | |
1868 | || (optype0 == OFFSOP && optype1 == REGOP && (REGNO (op1) & 1) == 0)) | |
1869 | { | |
61a55e8b | 1870 | rtx mem, reg; |
795068a4 JW |
1871 | |
1872 | if (optype0 == REGOP) | |
61a55e8b | 1873 | mem = op1, reg = op0; |
795068a4 | 1874 | else |
61a55e8b | 1875 | mem = op0, reg = op1; |
795068a4 | 1876 | |
61a55e8b DE |
1877 | if (mem_aligned_8 (mem) |
1878 | /* If this is a floating point register higher than %f31, | |
1879 | then we *must* use an aligned load, since `ld' will not accept | |
1880 | the register number. */ | |
1881 | || (TARGET_V9 && REGNO (reg) >= 64)) | |
795068a4 | 1882 | { |
61a55e8b DE |
1883 | if (TARGET_V9 && FP_REG_P (reg)) |
1884 | { | |
1885 | if ((REGNO (reg) & 3) != 0) | |
1886 | abort (); | |
1887 | return (mem == op1 ? "ldq %1,%0" : "stq %1,%0"); | |
1888 | } | |
795068a4 JW |
1889 | operands[2] = adj_offsettable_operand (mem, 8); |
1890 | if (mem == op1) | |
61a55e8b | 1891 | return TARGET_V9 ? "ldx %1,%0;ldx %2,%R0" : "ldd %1,%0;ldd %2,%S0"; |
795068a4 | 1892 | else |
61a55e8b | 1893 | return TARGET_V9 ? "stx %1,%0;stx %R1,%2" : "std %1,%0;std %S1,%2"; |
795068a4 JW |
1894 | } |
1895 | } | |
1896 | ||
1897 | /* If the first move would clobber the source of the second one, | |
1898 | do them in the other order. */ | |
1899 | ||
1900 | /* Overlapping registers. */ | |
1901 | if (optype0 == REGOP && optype1 == REGOP | |
1902 | && (REGNO (op0) == REGNO (wordpart[1][3]) | |
1903 | || REGNO (op0) == REGNO (wordpart[1][2]) | |
1904 | || REGNO (op0) == REGNO (wordpart[1][1]))) | |
1905 | { | |
1906 | /* Do fourth word. */ | |
1907 | output_asm_insn (singlemove_string (wordpart[3]), wordpart[3]); | |
1908 | /* Do the third word. */ | |
1909 | output_asm_insn (singlemove_string (wordpart[2]), wordpart[2]); | |
1910 | /* Do the second word. */ | |
1911 | output_asm_insn (singlemove_string (wordpart[1]), wordpart[1]); | |
1912 | /* Do lowest-numbered word. */ | |
1913 | return singlemove_string (wordpart[0]); | |
1914 | } | |
1915 | /* Loading into a register which overlaps a register used in the address. */ | |
1916 | if (optype0 == REGOP && optype1 != REGOP | |
1917 | && reg_overlap_mentioned_p (op0, op1)) | |
1918 | { | |
1919 | /* ??? Not implemented yet. This is a bit complicated, because we | |
1920 | must load which ever part overlaps the address last. If the address | |
1921 | is a double-reg address, then there are two parts which need to | |
1922 | be done last, which is impossible. We would need a scratch register | |
1923 | in that case. */ | |
1924 | abort (); | |
1925 | } | |
1926 | ||
1927 | /* Normal case: move the four words in lowest to higest address order. */ | |
1928 | ||
1929 | output_asm_insn (singlemove_string (wordpart[0]), wordpart[0]); | |
1930 | ||
1931 | /* Make any unoffsettable addresses point at the second word. */ | |
1932 | if (addreg0) | |
1933 | output_asm_insn ("add %0,0x4,%0", &addreg0); | |
1934 | if (addreg1) | |
1935 | output_asm_insn ("add %0,0x4,%0", &addreg1); | |
1936 | ||
1937 | /* Do the second word. */ | |
1938 | output_asm_insn (singlemove_string (wordpart[1]), wordpart[1]); | |
1939 | ||
1940 | /* Make any unoffsettable addresses point at the third word. */ | |
1941 | if (addreg0) | |
1942 | output_asm_insn ("add %0,0x4,%0", &addreg0); | |
1943 | if (addreg1) | |
1944 | output_asm_insn ("add %0,0x4,%0", &addreg1); | |
1945 | ||
1946 | /* Do the third word. */ | |
1947 | output_asm_insn (singlemove_string (wordpart[2]), wordpart[2]); | |
1948 | ||
1949 | /* Make any unoffsettable addresses point at the fourth word. */ | |
1950 | if (addreg0) | |
1951 | output_asm_insn ("add %0,0x4,%0", &addreg0); | |
1952 | if (addreg1) | |
1953 | output_asm_insn ("add %0,0x4,%0", &addreg1); | |
1954 | ||
1955 | /* Do the fourth word. */ | |
1956 | output_asm_insn (singlemove_string (wordpart[3]), wordpart[3]); | |
1957 | ||
1958 | /* Undo the adds we just did. */ | |
1959 | if (addreg0) | |
1960 | output_asm_insn ("add %0,-0xc,%0", &addreg0); | |
1961 | if (addreg1) | |
1962 | output_asm_insn ("add %0,-0xc,%0", &addreg1); | |
1963 | ||
1964 | return ""; | |
1965 | } | |
ab835497 | 1966 | \f |
795068a4 | 1967 | /* Output assembler code to perform a doubleword move insn with operands |
a3ee5899 JW |
1968 | OPERANDS, one of which must be a floating point register. */ |
1969 | ||
ab835497 RK |
1970 | char * |
1971 | output_fp_move_double (operands) | |
1972 | rtx *operands; | |
1973 | { | |
ab835497 RK |
1974 | if (FP_REG_P (operands[0])) |
1975 | { | |
1976 | if (FP_REG_P (operands[1])) | |
61a55e8b DE |
1977 | { |
1978 | if (TARGET_V9) | |
1979 | return "fmovd %1,%0"; | |
1980 | else | |
1981 | return "fmovs %1,%0\n\tfmovs %R1,%R0"; | |
1982 | } | |
a3ee5899 | 1983 | else if (GET_CODE (operands[1]) == REG) |
019c2b24 | 1984 | abort (); |
a3ee5899 JW |
1985 | else |
1986 | return output_move_double (operands); | |
ab835497 RK |
1987 | } |
1988 | else if (FP_REG_P (operands[1])) | |
1989 | { | |
1990 | if (GET_CODE (operands[0]) == REG) | |
019c2b24 | 1991 | abort (); |
a3ee5899 JW |
1992 | else |
1993 | return output_move_double (operands); | |
ab835497 RK |
1994 | } |
1995 | else abort (); | |
1996 | } | |
795068a4 JW |
1997 | |
1998 | /* Output assembler code to perform a quadword move insn with operands | |
1999 | OPERANDS, one of which must be a floating point register. */ | |
2000 | ||
2001 | char * | |
2002 | output_fp_move_quad (operands) | |
2003 | rtx *operands; | |
2004 | { | |
2005 | register rtx op0 = operands[0]; | |
2006 | register rtx op1 = operands[1]; | |
795068a4 JW |
2007 | |
2008 | if (FP_REG_P (op0)) | |
2009 | { | |
2010 | if (FP_REG_P (op1)) | |
61a55e8b DE |
2011 | { |
2012 | if (TARGET_V9) | |
2013 | return "fmovq %1,%0"; | |
2014 | else | |
2015 | return "fmovs %1,%0\n\tfmovs %R1,%R0\n\tfmovs %S1,%S0\n\tfmovs %T1,%T0"; | |
2016 | } | |
019c2b24 JW |
2017 | else if (GET_CODE (op1) == REG) |
2018 | abort (); | |
795068a4 JW |
2019 | else |
2020 | return output_move_quad (operands); | |
2021 | } | |
2022 | else if (FP_REG_P (op1)) | |
2023 | { | |
2024 | if (GET_CODE (op0) == REG) | |
019c2b24 | 2025 | abort (); |
795068a4 JW |
2026 | else |
2027 | return output_move_quad (operands); | |
2028 | } | |
2029 | else | |
2030 | abort (); | |
2031 | } | |
ab835497 RK |
2032 | \f |
2033 | /* Return a REG that occurs in ADDR with coefficient 1. | |
2034 | ADDR can be effectively incremented by incrementing REG. */ | |
2035 | ||
2036 | static rtx | |
2037 | find_addr_reg (addr) | |
2038 | rtx addr; | |
2039 | { | |
2040 | while (GET_CODE (addr) == PLUS) | |
2041 | { | |
2042 | /* We absolutely can not fudge the frame pointer here, because the | |
2043 | frame pointer must always be 8 byte aligned. It also confuses | |
2044 | debuggers. */ | |
2045 | if (GET_CODE (XEXP (addr, 0)) == REG | |
2046 | && REGNO (XEXP (addr, 0)) != FRAME_POINTER_REGNUM) | |
2047 | addr = XEXP (addr, 0); | |
2048 | else if (GET_CODE (XEXP (addr, 1)) == REG | |
2049 | && REGNO (XEXP (addr, 1)) != FRAME_POINTER_REGNUM) | |
2050 | addr = XEXP (addr, 1); | |
2051 | else if (CONSTANT_P (XEXP (addr, 0))) | |
2052 | addr = XEXP (addr, 1); | |
2053 | else if (CONSTANT_P (XEXP (addr, 1))) | |
2054 | addr = XEXP (addr, 0); | |
2055 | else | |
2056 | abort (); | |
2057 | } | |
2058 | if (GET_CODE (addr) == REG) | |
2059 | return addr; | |
2060 | abort (); | |
2061 | } | |
2062 | ||
6a4bb1fa DE |
2063 | #if 0 /* not currently used */ |
2064 | ||
ab835497 RK |
2065 | void |
2066 | output_sized_memop (opname, mode, signedp) | |
2067 | char *opname; | |
2068 | enum machine_mode mode; | |
2069 | int signedp; | |
2070 | { | |
2071 | static char *ld_size_suffix_u[] = { "ub", "uh", "", "?", "d" }; | |
2072 | static char *ld_size_suffix_s[] = { "sb", "sh", "", "?", "d" }; | |
2073 | static char *st_size_suffix[] = { "b", "h", "", "?", "d" }; | |
2074 | char **opnametab, *modename; | |
2075 | ||
2076 | if (opname[0] == 'l') | |
2077 | if (signedp) | |
2078 | opnametab = ld_size_suffix_s; | |
2079 | else | |
2080 | opnametab = ld_size_suffix_u; | |
2081 | else | |
2082 | opnametab = st_size_suffix; | |
2083 | modename = opnametab[GET_MODE_SIZE (mode) >> 1]; | |
2084 | ||
2085 | fprintf (asm_out_file, "\t%s%s", opname, modename); | |
2086 | } | |
2087 | \f | |
2088 | void | |
2089 | output_move_with_extension (operands) | |
2090 | rtx *operands; | |
2091 | { | |
2092 | if (GET_MODE (operands[2]) == HImode) | |
2093 | output_asm_insn ("sll %2,0x10,%0", operands); | |
2094 | else if (GET_MODE (operands[2]) == QImode) | |
2095 | output_asm_insn ("sll %2,0x18,%0", operands); | |
2096 | else | |
2097 | abort (); | |
2098 | } | |
6a4bb1fa | 2099 | #endif /* not currently used */ |
ab835497 | 2100 | \f |
09aa6559 JW |
2101 | #if 0 |
2102 | /* ??? These are only used by the movstrsi pattern, but we get better code | |
2103 | in general without that, because emit_block_move can do just as good a | |
2104 | job as this function does when alignment and size are known. When they | |
2105 | aren't known, a call to strcpy may be faster anyways, because it is | |
2106 | likely to be carefully crafted assembly language code, and below we just | |
2107 | do a byte-wise copy. | |
2108 | ||
2109 | Also, emit_block_move expands into multiple read/write RTL insns, which | |
2110 | can then be optimized, whereas our movstrsi pattern can not be optimized | |
2111 | at all. */ | |
2112 | ||
ab835497 RK |
2113 | /* Load the address specified by OPERANDS[3] into the register |
2114 | specified by OPERANDS[0]. | |
2115 | ||
2116 | OPERANDS[3] may be the result of a sum, hence it could either be: | |
2117 | ||
2118 | (1) CONST | |
2119 | (2) REG | |
2120 | (2) REG + CONST_INT | |
2121 | (3) REG + REG + CONST_INT | |
2122 | (4) REG + REG (special case of 3). | |
2123 | ||
2124 | Note that (3) is not a legitimate address. | |
2125 | All cases are handled here. */ | |
2126 | ||
2127 | void | |
2128 | output_load_address (operands) | |
2129 | rtx *operands; | |
2130 | { | |
2131 | rtx base, offset; | |
2132 | ||
2133 | if (CONSTANT_P (operands[3])) | |
2134 | { | |
2135 | output_asm_insn ("set %3,%0", operands); | |
2136 | return; | |
2137 | } | |
2138 | ||
2139 | if (REG_P (operands[3])) | |
2140 | { | |
2141 | if (REGNO (operands[0]) != REGNO (operands[3])) | |
2142 | output_asm_insn ("mov %3,%0", operands); | |
2143 | return; | |
2144 | } | |
2145 | ||
2146 | if (GET_CODE (operands[3]) != PLUS) | |
2147 | abort (); | |
2148 | ||
2149 | base = XEXP (operands[3], 0); | |
2150 | offset = XEXP (operands[3], 1); | |
2151 | ||
2152 | if (GET_CODE (base) == CONST_INT) | |
2153 | { | |
2154 | rtx tmp = base; | |
2155 | base = offset; | |
2156 | offset = tmp; | |
2157 | } | |
2158 | ||
2159 | if (GET_CODE (offset) != CONST_INT) | |
2160 | { | |
2161 | /* Operand is (PLUS (REG) (REG)). */ | |
2162 | base = operands[3]; | |
2163 | offset = const0_rtx; | |
2164 | } | |
2165 | ||
2166 | if (REG_P (base)) | |
2167 | { | |
2168 | operands[6] = base; | |
2169 | operands[7] = offset; | |
2170 | if (SMALL_INT (offset)) | |
2171 | output_asm_insn ("add %6,%7,%0", operands); | |
2172 | else | |
2173 | output_asm_insn ("set %7,%0\n\tadd %0,%6,%0", operands); | |
2174 | } | |
2175 | else if (GET_CODE (base) == PLUS) | |
2176 | { | |
2177 | operands[6] = XEXP (base, 0); | |
2178 | operands[7] = XEXP (base, 1); | |
2179 | operands[8] = offset; | |
2180 | ||
2181 | if (SMALL_INT (offset)) | |
2182 | output_asm_insn ("add %6,%7,%0\n\tadd %0,%8,%0", operands); | |
2183 | else | |
2184 | output_asm_insn ("set %8,%0\n\tadd %0,%6,%0\n\tadd %0,%7,%0", operands); | |
2185 | } | |
2186 | else | |
2187 | abort (); | |
2188 | } | |
2189 | ||
2190 | /* Output code to place a size count SIZE in register REG. | |
2191 | ALIGN is the size of the unit of transfer. | |
2192 | ||
2193 | Because block moves are pipelined, we don't include the | |
2194 | first element in the transfer of SIZE to REG. */ | |
2195 | ||
2196 | static void | |
2197 | output_size_for_block_move (size, reg, align) | |
2198 | rtx size, reg; | |
2199 | rtx align; | |
2200 | { | |
2201 | rtx xoperands[3]; | |
2202 | ||
2203 | xoperands[0] = reg; | |
2204 | xoperands[1] = size; | |
2205 | xoperands[2] = align; | |
2206 | if (GET_CODE (size) == REG) | |
2207 | output_asm_insn ("sub %1,%2,%0", xoperands); | |
2208 | else | |
2209 | { | |
2210 | xoperands[1] | |
2211 | = gen_rtx (CONST_INT, VOIDmode, INTVAL (size) - INTVAL (align)); | |
2212 | output_asm_insn ("set %1,%0", xoperands); | |
2213 | } | |
2214 | } | |
2215 | ||
2216 | /* Emit code to perform a block move. | |
2217 | ||
2218 | OPERANDS[0] is the destination. | |
2219 | OPERANDS[1] is the source. | |
2220 | OPERANDS[2] is the size. | |
2221 | OPERANDS[3] is the alignment safe to use. | |
2222 | OPERANDS[4] is a register we can safely clobber as a temp. */ | |
2223 | ||
2224 | char * | |
2225 | output_block_move (operands) | |
2226 | rtx *operands; | |
2227 | { | |
2228 | /* A vector for our computed operands. Note that load_output_address | |
2229 | makes use of (and can clobber) up to the 8th element of this vector. */ | |
2230 | rtx xoperands[10]; | |
2231 | rtx zoperands[10]; | |
2232 | static int movstrsi_label = 0; | |
2233 | int i; | |
2234 | rtx temp1 = operands[4]; | |
2235 | rtx sizertx = operands[2]; | |
2236 | rtx alignrtx = operands[3]; | |
2237 | int align = INTVAL (alignrtx); | |
210aa14a | 2238 | char label3[30], label5[30]; |
ab835497 RK |
2239 | |
2240 | xoperands[0] = operands[0]; | |
2241 | xoperands[1] = operands[1]; | |
2242 | xoperands[2] = temp1; | |
2243 | ||
391b99c9 RS |
2244 | /* We can't move more than this many bytes at a time because we have only |
2245 | one register, %g1, to move them through. */ | |
2246 | if (align > UNITS_PER_WORD) | |
ab835497 | 2247 | { |
391b99c9 RS |
2248 | align = UNITS_PER_WORD; |
2249 | alignrtx = gen_rtx (CONST_INT, VOIDmode, UNITS_PER_WORD); | |
ab835497 RK |
2250 | } |
2251 | ||
391b99c9 RS |
2252 | /* We consider 8 ld/st pairs, for a total of 16 inline insns to be |
2253 | reasonable here. (Actually will emit a maximum of 18 inline insns for | |
2254 | the case of size == 31 and align == 4). */ | |
2255 | ||
2256 | if (GET_CODE (sizertx) == CONST_INT && (INTVAL (sizertx) / align) <= 8 | |
2257 | && memory_address_p (QImode, plus_constant_for_output (xoperands[0], | |
2258 | INTVAL (sizertx))) | |
2259 | && memory_address_p (QImode, plus_constant_for_output (xoperands[1], | |
2260 | INTVAL (sizertx)))) | |
ab835497 RK |
2261 | { |
2262 | int size = INTVAL (sizertx); | |
391b99c9 | 2263 | int offset = 0; |
ab835497 | 2264 | |
391b99c9 RS |
2265 | /* We will store different integers into this particular RTX. */ |
2266 | xoperands[2] = rtx_alloc (CONST_INT); | |
2267 | PUT_MODE (xoperands[2], VOIDmode); | |
ab835497 | 2268 | |
391b99c9 RS |
2269 | /* This case is currently not handled. Abort instead of generating |
2270 | bad code. */ | |
61a55e8b | 2271 | if (align > UNITS_PER_WORD) |
391b99c9 | 2272 | abort (); |
ab835497 | 2273 | |
61a55e8b DE |
2274 | if (TARGET_V9 && align >= 8) |
2275 | { | |
2276 | for (i = (size >> 3) - 1; i >= 0; i--) | |
2277 | { | |
2278 | INTVAL (xoperands[2]) = (i << 3) + offset; | |
2279 | output_asm_insn ("ldx [%a1+%2],%%g1\n\tstx %%g1,[%a0+%2]", | |
2280 | xoperands); | |
2281 | } | |
2282 | offset += (size & ~0x7); | |
2283 | size = size & 0x7; | |
2284 | if (size == 0) | |
2285 | return ""; | |
2286 | } | |
2287 | ||
391b99c9 | 2288 | if (align >= 4) |
ab835497 | 2289 | { |
391b99c9 | 2290 | for (i = (size >> 2) - 1; i >= 0; i--) |
ab835497 | 2291 | { |
391b99c9 RS |
2292 | INTVAL (xoperands[2]) = (i << 2) + offset; |
2293 | output_asm_insn ("ld [%a1+%2],%%g1\n\tst %%g1,[%a0+%2]", | |
2294 | xoperands); | |
ab835497 | 2295 | } |
391b99c9 RS |
2296 | offset += (size & ~0x3); |
2297 | size = size & 0x3; | |
2298 | if (size == 0) | |
2299 | return ""; | |
ab835497 | 2300 | } |
391b99c9 RS |
2301 | |
2302 | if (align >= 2) | |
ab835497 | 2303 | { |
391b99c9 | 2304 | for (i = (size >> 1) - 1; i >= 0; i--) |
ab835497 | 2305 | { |
391b99c9 RS |
2306 | INTVAL (xoperands[2]) = (i << 1) + offset; |
2307 | output_asm_insn ("lduh [%a1+%2],%%g1\n\tsth %%g1,[%a0+%2]", | |
2308 | xoperands); | |
ab835497 | 2309 | } |
391b99c9 RS |
2310 | offset += (size & ~0x1); |
2311 | size = size & 0x1; | |
2312 | if (size == 0) | |
2313 | return ""; | |
ab835497 | 2314 | } |
391b99c9 RS |
2315 | |
2316 | if (align >= 1) | |
ab835497 | 2317 | { |
391b99c9 | 2318 | for (i = size - 1; i >= 0; i--) |
ab835497 | 2319 | { |
391b99c9 RS |
2320 | INTVAL (xoperands[2]) = i + offset; |
2321 | output_asm_insn ("ldub [%a1+%2],%%g1\n\tstb %%g1,[%a0+%2]", | |
2322 | xoperands); | |
ab835497 | 2323 | } |
391b99c9 | 2324 | return ""; |
ab835497 | 2325 | } |
391b99c9 RS |
2326 | |
2327 | /* We should never reach here. */ | |
2328 | abort (); | |
ab835497 RK |
2329 | } |
2330 | ||
391b99c9 RS |
2331 | /* If the size isn't known to be a multiple of the alignment, |
2332 | we have to do it in smaller pieces. If we could determine that | |
2333 | the size was a multiple of 2 (or whatever), we could be smarter | |
2334 | about this. */ | |
2335 | if (GET_CODE (sizertx) != CONST_INT) | |
2336 | align = 1; | |
2337 | else | |
2338 | { | |
2339 | int size = INTVAL (sizertx); | |
2340 | while (size % align) | |
2341 | align >>= 1; | |
2342 | } | |
2343 | ||
2344 | if (align != INTVAL (alignrtx)) | |
2345 | alignrtx = gen_rtx (CONST_INT, VOIDmode, align); | |
2346 | ||
ab835497 RK |
2347 | xoperands[3] = gen_rtx (CONST_INT, VOIDmode, movstrsi_label++); |
2348 | xoperands[4] = gen_rtx (CONST_INT, VOIDmode, align); | |
2349 | xoperands[5] = gen_rtx (CONST_INT, VOIDmode, movstrsi_label++); | |
2350 | ||
210aa14a RS |
2351 | ASM_GENERATE_INTERNAL_LABEL (label3, "Lm", INTVAL (xoperands[3])); |
2352 | ASM_GENERATE_INTERNAL_LABEL (label5, "Lm", INTVAL (xoperands[5])); | |
2353 | ||
391b99c9 RS |
2354 | /* This is the size of the transfer. Emit code to decrement the size |
2355 | value by ALIGN, and store the result in the temp1 register. */ | |
ab835497 RK |
2356 | output_size_for_block_move (sizertx, temp1, alignrtx); |
2357 | ||
2358 | /* Must handle the case when the size is zero or negative, so the first thing | |
2359 | we do is compare the size against zero, and only copy bytes if it is | |
2360 | zero or greater. Note that we have already subtracted off the alignment | |
2361 | once, so we must copy 1 alignment worth of bytes if the size is zero | |
2362 | here. | |
2363 | ||
2364 | The SUN assembler complains about labels in branch delay slots, so we | |
b4ac57ab | 2365 | do this before outputting the load address, so that there will always |
ab835497 RK |
2366 | be a harmless insn between the branch here and the next label emitted |
2367 | below. */ | |
2368 | ||
210aa14a RS |
2369 | { |
2370 | char pattern[100]; | |
2371 | ||
2372 | sprintf (pattern, "cmp %%2,0\n\tbl %s", &label5[1]); | |
2373 | output_asm_insn (pattern, xoperands); | |
2374 | } | |
ab835497 RK |
2375 | |
2376 | zoperands[0] = operands[0]; | |
2377 | zoperands[3] = plus_constant_for_output (operands[0], align); | |
2378 | output_load_address (zoperands); | |
2379 | ||
2380 | /* ??? This might be much faster if the loops below were preconditioned | |
2381 | and unrolled. | |
2382 | ||
2383 | That is, at run time, copy enough bytes one at a time to ensure that the | |
2384 | target and source addresses are aligned to the the largest possible | |
2385 | alignment. Then use a preconditioned unrolled loop to copy say 16 | |
2386 | bytes at a time. Then copy bytes one at a time until finish the rest. */ | |
2387 | ||
2388 | /* Output the first label separately, so that it is spaced properly. */ | |
2389 | ||
ab835497 | 2390 | ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "Lm", INTVAL (xoperands[3])); |
ab835497 | 2391 | |
210aa14a RS |
2392 | { |
2393 | char pattern[200]; | |
61a55e8b DE |
2394 | register char *ld_suffix = ((align == 1) ? "ub" : (align == 2) ? "uh" |
2395 | : (align == 8 && TARGET_V9) ? "x" : ""); | |
2396 | register char *st_suffix = ((align == 1) ? "b" : (align == 2) ? "h" | |
2397 | : (align == 8 && TARGET_V9) ? "x" : ""); | |
210aa14a RS |
2398 | |
2399 | sprintf (pattern, "ld%s [%%1+%%2],%%%%g1\n\tsubcc %%2,%%4,%%2\n\tbge %s\n\tst%s %%%%g1,[%%0+%%2]\n%s:", ld_suffix, &label3[1], st_suffix, &label5[1]); | |
2400 | output_asm_insn (pattern, xoperands); | |
2401 | } | |
2402 | ||
ab835497 | 2403 | return ""; |
ab835497 | 2404 | } |
09aa6559 | 2405 | #endif |
ab835497 RK |
2406 | \f |
2407 | /* Output reasonable peephole for set-on-condition-code insns. | |
2408 | Note that these insns assume a particular way of defining | |
2409 | labels. Therefore, *both* sparc.h and this function must | |
2410 | be changed if a new syntax is needed. */ | |
2411 | ||
2412 | char * | |
2413 | output_scc_insn (operands, insn) | |
2414 | rtx operands[]; | |
2415 | rtx insn; | |
2416 | { | |
2417 | static char string[100]; | |
2418 | rtx label = 0, next = insn; | |
2419 | int need_label = 0; | |
2420 | ||
2421 | /* Try doing a jump optimization which jump.c can't do for us | |
2422 | because we did not expose that setcc works by using branches. | |
2423 | ||
2424 | If this scc insn is followed by an unconditional branch, then have | |
2425 | the jump insn emitted here jump to that location, instead of to | |
2426 | the end of the scc sequence as usual. */ | |
2427 | ||
2428 | do | |
2429 | { | |
2430 | if (GET_CODE (next) == CODE_LABEL) | |
2431 | label = next; | |
2432 | next = NEXT_INSN (next); | |
2433 | if (next == 0) | |
2434 | break; | |
2435 | } | |
2436 | while (GET_CODE (next) == NOTE || GET_CODE (next) == CODE_LABEL); | |
2437 | ||
2438 | /* If we are in a sequence, and the following insn is a sequence also, | |
2439 | then just following the current insn's next field will take us to the | |
2440 | first insn of the next sequence, which is the wrong place. We don't | |
2441 | want to optimize with a branch that has had its delay slot filled. | |
2442 | Avoid this by verifying that NEXT_INSN (PREV_INSN (next)) == next | |
2443 | which fails only if NEXT is such a branch. */ | |
2444 | ||
2445 | if (next && GET_CODE (next) == JUMP_INSN && simplejump_p (next) | |
2446 | && (! final_sequence || NEXT_INSN (PREV_INSN (next)) == next)) | |
2447 | label = JUMP_LABEL (next); | |
2448 | /* If not optimizing, jump label fields are not set. To be safe, always | |
2449 | check here to whether label is still zero. */ | |
2450 | if (label == 0) | |
2451 | { | |
2452 | label = gen_label_rtx (); | |
2453 | need_label = 1; | |
2454 | } | |
2455 | ||
2456 | LABEL_NUSES (label) += 1; | |
2457 | ||
2458 | operands[2] = label; | |
2459 | ||
2460 | /* If we are in a delay slot, assume it is the delay slot of an fpcc | |
2461 | insn since our type isn't allowed anywhere else. */ | |
2462 | ||
2463 | /* ??? Fpcc instructions no longer have delay slots, so this code is | |
2464 | probably obsolete. */ | |
2465 | ||
2466 | /* The fastest way to emit code for this is an annulled branch followed | |
2467 | by two move insns. This will take two cycles if the branch is taken, | |
2468 | and three cycles if the branch is not taken. | |
2469 | ||
2470 | However, if we are in the delay slot of another branch, this won't work, | |
2471 | because we can't put a branch in the delay slot of another branch. | |
2472 | The above sequence would effectively take 3 or 4 cycles respectively | |
2473 | since a no op would have be inserted between the two branches. | |
2474 | In this case, we want to emit a move, annulled branch, and then the | |
2475 | second move. This sequence always takes 3 cycles, and hence is faster | |
2476 | when we are in a branch delay slot. */ | |
2477 | ||
2478 | if (final_sequence) | |
2479 | { | |
2480 | strcpy (string, "mov 0,%0\n\t"); | |
61a55e8b | 2481 | strcat (string, output_cbranch (operands[1], 0, 2, 0, 1, 0)); |
ab835497 RK |
2482 | strcat (string, "\n\tmov 1,%0"); |
2483 | } | |
2484 | else | |
2485 | { | |
61a55e8b | 2486 | strcpy (string, output_cbranch (operands[1], 0, 2, 0, 1, 0)); |
ab835497 RK |
2487 | strcat (string, "\n\tmov 1,%0\n\tmov 0,%0"); |
2488 | } | |
2489 | ||
2490 | if (need_label) | |
2491 | strcat (string, "\n%l2:"); | |
2492 | ||
2493 | return string; | |
2494 | } | |
2495 | \f | |
61a55e8b DE |
2496 | /* Vectors to keep interesting information about registers where it can easily |
2497 | be got. We use to use the actual mode value as the bit number, but there | |
2498 | are more than 32 modes now. Instead we use two tables: one indexed by | |
2499 | hard register number, and one indexed by mode. */ | |
2500 | ||
2501 | /* The purpose of sparc_mode_class is to shrink the range of modes so that | |
2502 | they all fit (as bit numbers) in a 32 bit word (again). Each real mode is | |
2503 | mapped into one sparc_mode_class mode. */ | |
2504 | ||
2505 | enum sparc_mode_class { | |
2506 | C_MODE, CCFP_MODE, | |
2507 | S_MODE, D_MODE, T_MODE, O_MODE, | |
2508 | SF_MODE, DF_MODE, TF_MODE, OF_MODE | |
2509 | }; | |
ab835497 RK |
2510 | |
2511 | /* Modes for condition codes. */ | |
61a55e8b DE |
2512 | #define C_MODES ((1 << (int) C_MODE) | (1 << (int) CCFP_MODE)) |
2513 | #define CCFP_MODES (1 << (int) CCFP_MODE) | |
2514 | ||
2515 | /* Modes for single-word and smaller quantities. */ | |
2516 | #define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE)) | |
2517 | ||
2518 | /* Modes for double-word and smaller quantities. */ | |
2519 | #define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE)) | |
2520 | ||
2521 | /* Modes for quad-word and smaller quantities. */ | |
2522 | #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE)) | |
ab835497 | 2523 | |
1e4eb8d1 JW |
2524 | /* Modes for single-float quantities. We must allow any single word or |
2525 | smaller quantity. This is because the fix/float conversion instructions | |
2526 | take integer inputs/outputs from the float registers. */ | |
2527 | #define SF_MODES (S_MODES) | |
ab835497 | 2528 | |
61a55e8b DE |
2529 | /* Modes for double-float and smaller quantities. */ |
2530 | #define DF_MODES (S_MODES | D_MODES) | |
2531 | ||
2532 | /* ??? Sparc64 fp regs cannot hold DImode values. */ | |
2533 | #define DF_MODES64 (SF_MODES | DF_MODE /* | D_MODE*/) | |
2534 | ||
2535 | /* Modes for double-float only quantities. */ | |
2536 | /* ??? Sparc64 fp regs cannot hold DImode values. */ | |
2537 | #define DF_ONLY_MODES ((1 << (int) DF_MODE) /*| (1 << (int) D_MODE)*/) | |
2538 | ||
2539 | /* Modes for double-float and larger quantities. */ | |
2540 | #define DF_UP_MODES (DF_ONLY_MODES | TF_ONLY_MODES) | |
ab835497 | 2541 | |
61a55e8b DE |
2542 | /* Modes for quad-float only quantities. */ |
2543 | #define TF_ONLY_MODES (1 << (int) TF_MODE) | |
2544 | ||
2545 | /* Modes for quad-float and smaller quantities. */ | |
2546 | #define TF_MODES (DF_MODES | TF_ONLY_MODES) | |
2547 | ||
2548 | /* ??? Sparc64 fp regs cannot hold DImode values. */ | |
2549 | #define TF_MODES64 (DF_MODES64 | TF_ONLY_MODES) | |
ab835497 RK |
2550 | |
2551 | /* Value is 1 if register/mode pair is acceptable on sparc. | |
2552 | The funny mixture of D and T modes is because integer operations | |
2553 | do not specially operate on tetra quantities, so non-quad-aligned | |
2554 | registers can hold quadword quantities (except %o4 and %i4 because | |
2555 | they cross fixed registers. */ | |
2556 | ||
61a55e8b DE |
2557 | /* This points to either the 32 bit or the 64 bit version. */ |
2558 | int *hard_regno_mode_classes; | |
2559 | ||
2560 | static int hard_32bit_mode_classes[] = { | |
ab835497 RK |
2561 | C_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, |
2562 | T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES, | |
2563 | T_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, | |
2564 | T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES, | |
2565 | ||
2566 | TF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES, | |
2567 | TF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES, | |
2568 | TF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES, | |
61a55e8b DE |
2569 | TF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES, |
2570 | }; | |
2571 | ||
2572 | static int hard_64bit_mode_classes[] = { | |
2573 | C_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, | |
2574 | T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, | |
2575 | T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, | |
2576 | T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, | |
2577 | ||
2578 | TF_MODES64, SF_MODES, DF_MODES64, SF_MODES, TF_MODES64, SF_MODES, DF_MODES64, SF_MODES, | |
2579 | TF_MODES64, SF_MODES, DF_MODES64, SF_MODES, TF_MODES64, SF_MODES, DF_MODES64, SF_MODES, | |
2580 | TF_MODES64, SF_MODES, DF_MODES64, SF_MODES, TF_MODES64, SF_MODES, DF_MODES64, SF_MODES, | |
2581 | TF_MODES64, SF_MODES, DF_MODES64, SF_MODES, TF_MODES64, SF_MODES, DF_MODES64, SF_MODES, | |
2582 | ||
2583 | /* The remaining registers do not exist on a non-v9 sparc machine. | |
2584 | FP regs f32 to f63. Only the even numbered registers actually exist, | |
2585 | and none can hold SFmode/SImode values. */ | |
2586 | DF_UP_MODES, 0, DF_ONLY_MODES, 0, DF_UP_MODES, 0, DF_ONLY_MODES, 0, | |
2587 | DF_UP_MODES, 0, DF_ONLY_MODES, 0, DF_UP_MODES, 0, DF_ONLY_MODES, 0, | |
2588 | DF_UP_MODES, 0, DF_ONLY_MODES, 0, DF_UP_MODES, 0, DF_ONLY_MODES, 0, | |
2589 | DF_UP_MODES, 0, DF_ONLY_MODES, 0, DF_UP_MODES, 0, DF_ONLY_MODES, 0, | |
2590 | ||
2591 | /* %fcc[0123] */ | |
2592 | CCFP_MODE, CCFP_MODE, CCFP_MODE, CCFP_MODE | |
2593 | }; | |
2594 | ||
2595 | int sparc_mode_class [NUM_MACHINE_MODES]; | |
2596 | ||
2597 | static void | |
2598 | sparc_init_modes () | |
2599 | { | |
2600 | int i; | |
2601 | ||
dbb54862 | 2602 | sparc_arch_type = TARGET_V9 ? ARCH_64BIT : ARCH_32BIT; |
61a55e8b DE |
2603 | |
2604 | for (i = 0; i < NUM_MACHINE_MODES; i++) | |
2605 | { | |
2606 | switch (GET_MODE_CLASS (i)) | |
2607 | { | |
2608 | case MODE_INT: | |
2609 | case MODE_PARTIAL_INT: | |
2610 | case MODE_COMPLEX_INT: | |
2611 | if (GET_MODE_SIZE (i) <= 4) | |
2612 | sparc_mode_class[i] = 1 << (int) S_MODE; | |
2613 | else if (GET_MODE_SIZE (i) == 8) | |
2614 | sparc_mode_class[i] = 1 << (int) D_MODE; | |
2615 | else if (GET_MODE_SIZE (i) == 16) | |
2616 | sparc_mode_class[i] = 1 << (int) T_MODE; | |
2617 | else if (GET_MODE_SIZE (i) == 32) | |
2618 | sparc_mode_class[i] = 1 << (int) O_MODE; | |
2619 | else | |
2620 | sparc_mode_class[i] = 0; | |
2621 | break; | |
2622 | case MODE_FLOAT: | |
2623 | case MODE_COMPLEX_FLOAT: | |
2624 | if (GET_MODE_SIZE (i) <= 4) | |
2625 | sparc_mode_class[i] = 1 << (int) SF_MODE; | |
2626 | else if (GET_MODE_SIZE (i) == 8) | |
2627 | sparc_mode_class[i] = 1 << (int) DF_MODE; | |
2628 | else if (GET_MODE_SIZE (i) == 16) | |
2629 | sparc_mode_class[i] = 1 << (int) TF_MODE; | |
2630 | else if (GET_MODE_SIZE (i) == 32) | |
2631 | sparc_mode_class[i] = 1 << (int) OF_MODE; | |
2632 | else | |
2633 | sparc_mode_class[i] = 0; | |
2634 | break; | |
2635 | case MODE_CC: | |
2636 | default: | |
2637 | /* mode_class hasn't been initialized yet for EXTRA_CC_MODES, so | |
2638 | we must explicitly check for them here. */ | |
2639 | if (i == (int) CCFPmode || i == (int) CCFPEmode) | |
2640 | sparc_mode_class[i] = 1 << (int) CCFP_MODE; | |
2641 | else if (i == (int) CCmode || i == (int) CC_NOOVmode | |
2642 | #ifdef SPARCV9 | |
2643 | || i == (int) CCXmode | |
2644 | || i == (int) CCX_NOOVmode | |
2645 | #endif | |
2646 | ) | |
2647 | sparc_mode_class[i] = 1 << (int) C_MODE; | |
2648 | else | |
2649 | sparc_mode_class[i] = 0; | |
2650 | break; | |
2651 | } | |
2652 | } | |
2653 | ||
2654 | if (TARGET_V9) | |
2655 | hard_regno_mode_classes = hard_64bit_mode_classes; | |
2656 | else | |
2657 | hard_regno_mode_classes = hard_32bit_mode_classes; | |
2658 | } | |
ab835497 | 2659 | \f |
61a55e8b DE |
2660 | /* Save non call used registers from LOW to HIGH at BASE+OFFSET. |
2661 | N_REGS is the number of 4-byte regs saved thus far. This applies even to | |
2662 | v9 int regs as it simplifies the code. */ | |
2663 | ||
ab835497 | 2664 | #ifdef __GNUC__ |
99c7b2f6 | 2665 | __inline__ |
ab835497 RK |
2666 | #endif |
2667 | static int | |
61a55e8b | 2668 | save_regs (file, low, high, base, offset, n_regs) |
ab835497 RK |
2669 | FILE *file; |
2670 | int low, high; | |
2671 | char *base; | |
2672 | int offset; | |
61a55e8b | 2673 | int n_regs; |
ab835497 RK |
2674 | { |
2675 | int i; | |
2676 | ||
61a55e8b | 2677 | if (TARGET_V9 && high <= 32) |
ab835497 | 2678 | { |
61a55e8b DE |
2679 | for (i = low; i < high; i++) |
2680 | { | |
2681 | if (regs_ever_live[i] && ! call_used_regs[i]) | |
2682 | fprintf (file, "\tstx %s,[%s+%d]\n", | |
2683 | reg_names[i], base, offset + 4 * n_regs), | |
2684 | n_regs += 2; | |
2685 | } | |
ab835497 | 2686 | } |
61a55e8b DE |
2687 | else |
2688 | { | |
2689 | for (i = low; i < high; i += 2) | |
2690 | { | |
2691 | if (regs_ever_live[i] && ! call_used_regs[i]) | |
2692 | if (regs_ever_live[i+1] && ! call_used_regs[i+1]) | |
2693 | fprintf (file, "\tstd %s,[%s+%d]\n", | |
2694 | reg_names[i], base, offset + 4 * n_regs), | |
2695 | n_regs += 2; | |
2696 | else | |
2697 | fprintf (file, "\tst %s,[%s+%d]\n", | |
2698 | reg_names[i], base, offset + 4 * n_regs), | |
2699 | n_regs += 2; | |
2700 | else if (regs_ever_live[i+1] && ! call_used_regs[i+1]) | |
2701 | fprintf (file, "\tst %s,[%s+%d]\n", | |
2702 | reg_names[i+1], base, offset + 4 * n_regs + 4), | |
2703 | n_regs += 2; | |
2704 | } | |
2705 | } | |
2706 | return n_regs; | |
ab835497 RK |
2707 | } |
2708 | ||
61a55e8b DE |
2709 | /* Restore non call used registers from LOW to HIGH at BASE+OFFSET. |
2710 | ||
2711 | N_REGS is the number of 4-byte regs saved thus far. This applies even to | |
2712 | v9 int regs as it simplifies the code. */ | |
2713 | ||
ab835497 | 2714 | #ifdef __GNUC__ |
99c7b2f6 | 2715 | __inline__ |
ab835497 RK |
2716 | #endif |
2717 | static int | |
61a55e8b | 2718 | restore_regs (file, low, high, base, offset, n_regs) |
ab835497 RK |
2719 | FILE *file; |
2720 | int low, high; | |
2721 | char *base; | |
2722 | int offset; | |
61a55e8b | 2723 | int n_regs; |
ab835497 RK |
2724 | { |
2725 | int i; | |
2726 | ||
61a55e8b DE |
2727 | if (TARGET_V9 && high <= 32) |
2728 | { | |
2729 | for (i = low; i < high; i++) | |
2730 | { | |
2731 | if (regs_ever_live[i] && ! call_used_regs[i]) | |
2732 | fprintf (file, "\tldx [%s+%d], %s\n", | |
2733 | base, offset + 4 * n_regs, reg_names[i]), | |
2734 | n_regs += 2; | |
2735 | } | |
2736 | } | |
2737 | else | |
ab835497 | 2738 | { |
61a55e8b DE |
2739 | for (i = low; i < high; i += 2) |
2740 | { | |
2741 | if (regs_ever_live[i] && ! call_used_regs[i]) | |
2742 | if (regs_ever_live[i+1] && ! call_used_regs[i+1]) | |
2743 | fprintf (file, "\tldd [%s+%d], %s\n", | |
2744 | base, offset + 4 * n_regs, reg_names[i]), | |
2745 | n_regs += 2; | |
2746 | else | |
2747 | fprintf (file, "\tld [%s+%d],%s\n", | |
2748 | base, offset + 4 * n_regs, reg_names[i]), | |
2749 | n_regs += 2; | |
2750 | else if (regs_ever_live[i+1] && ! call_used_regs[i+1]) | |
2751 | fprintf (file, "\tld [%s+%d],%s\n", | |
2752 | base, offset + 4 * n_regs + 4, reg_names[i+1]), | |
2753 | n_regs += 2; | |
2754 | } | |
ab835497 | 2755 | } |
61a55e8b | 2756 | return n_regs; |
ab835497 RK |
2757 | } |
2758 | ||
2759 | /* Static variables we want to share between prologue and epilogue. */ | |
2760 | ||
61a55e8b DE |
2761 | /* Number of live general or floating point registers needed to be saved |
2762 | (as 4-byte quantities). This is only done if TARGET_EPILOGUE. */ | |
2763 | static int num_gfregs; | |
2764 | ||
2765 | /* Compute the frame size required by the function. This function is called | |
2766 | during the reload pass and also by output_function_prologue(). */ | |
ab835497 | 2767 | |
ab835497 RK |
2768 | int |
2769 | compute_frame_size (size, leaf_function) | |
2770 | int size; | |
2771 | int leaf_function; | |
2772 | { | |
61a55e8b | 2773 | int n_regs = 0, i; |
ab835497 | 2774 | int outgoing_args_size = (current_function_outgoing_args_size |
61a55e8b DE |
2775 | #ifndef SPARCV9 |
2776 | + REG_PARM_STACK_SPACE (current_function_decl) | |
2777 | #endif | |
2778 | ); | |
ab835497 | 2779 | |
61a55e8b | 2780 | if (TARGET_EPILOGUE) |
ab835497 | 2781 | { |
61a55e8b DE |
2782 | /* N_REGS is the number of 4-byte regs saved thus far. This applies |
2783 | even to v9 int regs to be consistent with save_regs/restore_regs. */ | |
2784 | ||
2785 | if (TARGET_V9) | |
2786 | { | |
2787 | for (i = 0; i < 8; i++) | |
2788 | if (regs_ever_live[i] && ! call_used_regs[i]) | |
2789 | n_regs += 2; | |
2790 | } | |
2791 | else | |
2792 | { | |
2793 | for (i = 0; i < 8; i += 2) | |
2794 | if ((regs_ever_live[i] && ! call_used_regs[i]) | |
2795 | || (regs_ever_live[i+1] && ! call_used_regs[i+1])) | |
2796 | n_regs += 2; | |
2797 | } | |
2798 | ||
2799 | for (i = 32; i < (TARGET_V9 ? 96 : 64); i += 2) | |
ab835497 RK |
2800 | if ((regs_ever_live[i] && ! call_used_regs[i]) |
2801 | || (regs_ever_live[i+1] && ! call_used_regs[i+1])) | |
61a55e8b | 2802 | n_regs += 2; |
ab835497 RK |
2803 | } |
2804 | ||
2805 | /* Set up values for use in `function_epilogue'. */ | |
61a55e8b | 2806 | num_gfregs = n_regs; |
ab835497 | 2807 | |
61a55e8b DE |
2808 | if (leaf_function && n_regs == 0 |
2809 | && size == 0 && current_function_outgoing_args_size == 0) | |
2810 | { | |
2811 | actual_fsize = apparent_fsize = 0; | |
2812 | } | |
2813 | else | |
2814 | { | |
2815 | /* We subtract STARTING_FRAME_OFFSET, remember it's negative. | |
2816 | The stack bias (if any) is taken out to undo its effects. */ | |
2817 | apparent_fsize = (size - STARTING_FRAME_OFFSET + SPARC_STACK_BIAS + 7) & -8; | |
2818 | apparent_fsize += n_regs * 4; | |
2819 | actual_fsize = apparent_fsize + ((outgoing_args_size + 7) & -8); | |
2820 | } | |
ab835497 RK |
2821 | |
2822 | /* Make sure nothing can clobber our register windows. | |
2823 | If a SAVE must be done, or there is a stack-local variable, | |
61a55e8b DE |
2824 | the register window area must be allocated. |
2825 | ??? For v9 we need an additional 8 bytes of reserved space, apparently | |
2826 | it's needed by v8 as well. */ | |
ab835497 | 2827 | if (leaf_function == 0 || size > 0) |
61a55e8b | 2828 | actual_fsize += (16 * UNITS_PER_WORD) + 8; |
ab835497 | 2829 | |
61a55e8b DE |
2830 | return SPARC_STACK_ALIGN (actual_fsize); |
2831 | } | |
2832 | ||
2833 | /* Build a (32 bit) big number in a register. */ | |
2834 | ||
2835 | static void | |
2836 | build_big_number (file, num, reg) | |
2837 | FILE *file; | |
2838 | int num; | |
2839 | char *reg; | |
2840 | { | |
2841 | if (num >= 0 || ! TARGET_V9) | |
2842 | { | |
2843 | fprintf (file, "\tsethi %%hi(%d),%s\n", num, reg); | |
2844 | if ((num & 0x3ff) != 0) | |
2845 | fprintf (file, "\tor %s,%%lo(%d),%s\n", reg, num, reg); | |
2846 | } | |
2847 | else /* num < 0 && TARGET_V9 */ | |
2848 | { | |
2849 | /* Sethi does not sign extend, so we must use a little trickery | |
2850 | to use it for negative numbers. Invert the constant before | |
2851 | loading it in, then use xor immediate to invert the loaded bits | |
2852 | (along with the upper 32 bits) to the desired constant. This | |
2853 | works because the sethi and immediate fields overlap. */ | |
2854 | int asize = num; | |
2855 | int inv = ~asize; | |
2856 | int low = -0x400 + (asize & 0x3FF); | |
2857 | ||
2858 | fprintf (file, "\tsethi %%hi(%d),%s\n\txor %s,%d,%s\n", | |
2859 | inv, reg, reg, low, reg); | |
2860 | } | |
ab835497 RK |
2861 | } |
2862 | ||
915f619f JW |
2863 | /* Output code for the function prologue. */ |
2864 | ||
ab835497 RK |
2865 | void |
2866 | output_function_prologue (file, size, leaf_function) | |
2867 | FILE *file; | |
2868 | int size; | |
915f619f | 2869 | int leaf_function; |
ab835497 | 2870 | { |
915f619f JW |
2871 | /* Need to use actual_fsize, since we are also allocating |
2872 | space for our callee (and our own register save area). */ | |
ab835497 RK |
2873 | actual_fsize = compute_frame_size (size, leaf_function); |
2874 | ||
61a55e8b DE |
2875 | if (leaf_function) |
2876 | { | |
2877 | frame_base_name = "%sp"; | |
2878 | frame_base_offset = actual_fsize + SPARC_STACK_BIAS; | |
2879 | } | |
2880 | else | |
2881 | { | |
2882 | frame_base_name = "%fp"; | |
2883 | frame_base_offset = SPARC_STACK_BIAS; | |
2884 | } | |
2885 | ||
c6aa9ce1 | 2886 | /* This is only for the human reader. */ |
ab835497 | 2887 | fprintf (file, "\t!#PROLOGUE# 0\n"); |
c6aa9ce1 | 2888 | |
915f619f JW |
2889 | if (actual_fsize == 0) |
2890 | /* do nothing. */ ; | |
2891 | else if (actual_fsize <= 4096) | |
ab835497 RK |
2892 | { |
2893 | if (! leaf_function) | |
2894 | fprintf (file, "\tsave %%sp,-%d,%%sp\n", actual_fsize); | |
2895 | else | |
2896 | fprintf (file, "\tadd %%sp,-%d,%%sp\n", actual_fsize); | |
2897 | } | |
915f619f | 2898 | else if (actual_fsize <= 8192) |
ab835497 | 2899 | { |
915f619f JW |
2900 | /* For frames in the range 4097..8192, we can use just two insns. */ |
2901 | if (! leaf_function) | |
2902 | { | |
2903 | fprintf (file, "\tsave %%sp,-4096,%%sp\n"); | |
2904 | fprintf (file, "\tadd %%sp,-%d,%%sp\n", actual_fsize - 4096); | |
2905 | } | |
2906 | else | |
2907 | { | |
2908 | fprintf (file, "\tadd %%sp,-4096,%%sp\n"); | |
2909 | fprintf (file, "\tadd %%sp,-%d,%%sp\n", actual_fsize - 4096); | |
2910 | } | |
ab835497 RK |
2911 | } |
2912 | else | |
2913 | { | |
61a55e8b | 2914 | build_big_number (file, -actual_fsize, "%g1"); |
915f619f | 2915 | if (! leaf_function) |
61a55e8b | 2916 | fprintf (file, "\tsave %%sp,%%g1,%%sp\n"); |
915f619f | 2917 | else |
61a55e8b | 2918 | fprintf (file, "\tadd %%sp,%%g1,%%sp\n"); |
ab835497 RK |
2919 | } |
2920 | ||
2921 | /* If doing anything with PIC, do it now. */ | |
2922 | if (! flag_pic) | |
2923 | fprintf (file, "\t!#PROLOGUE# 1\n"); | |
2924 | ||
61a55e8b DE |
2925 | /* Call saved registers are saved just above the outgoing argument area. */ |
2926 | if (num_gfregs) | |
ab835497 | 2927 | { |
61a55e8b DE |
2928 | int offset, n_regs; |
2929 | char *base; | |
ab835497 | 2930 | |
61a55e8b DE |
2931 | offset = -apparent_fsize + frame_base_offset; |
2932 | if (offset < -4096 || offset + num_gfregs * 4 > 4096) | |
2933 | { | |
2934 | /* ??? This might be optimized a little as %g1 might already have a | |
2935 | value close enough that a single add insn will do. */ | |
2936 | /* ??? Although, all of this is probably only a temporary fix | |
2937 | because if %g1 can hold a function result, then | |
2938 | output_function_epilogue will lose (the result will get | |
2939 | clobbered). */ | |
2940 | build_big_number (file, offset, "%g1"); | |
2941 | fprintf (file, "\tadd %s,%%g1,%%g1\n", frame_base_name); | |
2942 | base = "%g1"; | |
2943 | offset = 0; | |
2944 | } | |
ab835497 | 2945 | else |
61a55e8b DE |
2946 | { |
2947 | base = frame_base_name; | |
2948 | } | |
ab835497 RK |
2949 | |
2950 | if (TARGET_EPILOGUE && ! leaf_function) | |
61a55e8b DE |
2951 | /* ??? Originally saved regs 0-15 here. */ |
2952 | n_regs = save_regs (file, 0, 8, base, offset, 0); | |
ab835497 | 2953 | else if (leaf_function) |
61a55e8b DE |
2954 | /* ??? Originally saved regs 0-31 here. */ |
2955 | n_regs = save_regs (file, 0, 8, base, offset, 0); | |
ab835497 | 2956 | if (TARGET_EPILOGUE) |
61a55e8b | 2957 | save_regs (file, 32, TARGET_V9 ? 96 : 64, base, offset, n_regs); |
ab835497 RK |
2958 | } |
2959 | ||
ab835497 RK |
2960 | leaf_label = 0; |
2961 | if (leaf_function && actual_fsize != 0) | |
2962 | { | |
2963 | /* warning ("leaf procedure with frame size %d", actual_fsize); */ | |
2964 | if (! TARGET_EPILOGUE) | |
2965 | leaf_label = gen_label_rtx (); | |
2966 | } | |
2967 | } | |
2968 | ||
915f619f JW |
2969 | /* Output code for the function epilogue. */ |
2970 | ||
ab835497 | 2971 | void |
ef8200df | 2972 | output_function_epilogue (file, size, leaf_function) |
ab835497 RK |
2973 | FILE *file; |
2974 | int size; | |
ef8200df | 2975 | int leaf_function; |
ab835497 | 2976 | { |
ab835497 RK |
2977 | char *ret; |
2978 | ||
2979 | if (leaf_label) | |
2980 | { | |
ab835497 RK |
2981 | emit_label_after (leaf_label, get_last_insn ()); |
2982 | final_scan_insn (get_last_insn (), file, 0, 0, 1); | |
2983 | } | |
2984 | ||
61a55e8b DE |
2985 | /* Restore any call saved registers. */ |
2986 | if (num_gfregs) | |
ab835497 | 2987 | { |
61a55e8b DE |
2988 | int offset, n_regs; |
2989 | char *base; | |
ab835497 | 2990 | |
61a55e8b DE |
2991 | offset = -apparent_fsize + frame_base_offset; |
2992 | if (offset < -4096 || offset + num_gfregs * 4 > 4096 - 8 /*double*/) | |
2993 | { | |
2994 | build_big_number (file, offset, "%g1"); | |
2995 | fprintf (file, "\tadd %s,%%g1,%%g1\n", frame_base_name); | |
2996 | base = "%g1"; | |
2997 | offset = 0; | |
2998 | } | |
ab835497 | 2999 | else |
61a55e8b DE |
3000 | { |
3001 | base = frame_base_name; | |
3002 | } | |
ab835497 RK |
3003 | |
3004 | if (TARGET_EPILOGUE && ! leaf_function) | |
61a55e8b DE |
3005 | /* ??? Originally saved regs 0-15 here. */ |
3006 | n_regs = restore_regs (file, 0, 8, base, offset, 0); | |
ab835497 | 3007 | else if (leaf_function) |
61a55e8b DE |
3008 | /* ??? Originally saved regs 0-31 here. */ |
3009 | n_regs = restore_regs (file, 0, 8, base, offset, 0); | |
ab835497 | 3010 | if (TARGET_EPILOGUE) |
61a55e8b | 3011 | restore_regs (file, 32, TARGET_V9 ? 96 : 64, base, offset, n_regs); |
ab835497 RK |
3012 | } |
3013 | ||
3014 | /* Work out how to skip the caller's unimp instruction if required. */ | |
3015 | if (leaf_function) | |
61a55e8b | 3016 | ret = (SKIP_CALLERS_UNIMP_P ? "jmp %o7+12" : "retl"); |
ab835497 | 3017 | else |
61a55e8b | 3018 | ret = (SKIP_CALLERS_UNIMP_P ? "jmp %i7+12" : "ret"); |
ab835497 | 3019 | |
ef8200df | 3020 | if (TARGET_EPILOGUE || leaf_label) |
ab835497 | 3021 | { |
ef8200df JW |
3022 | int old_target_epilogue = TARGET_EPILOGUE; |
3023 | target_flags &= ~old_target_epilogue; | |
ab835497 | 3024 | |
ef8200df JW |
3025 | if (! leaf_function) |
3026 | { | |
3027 | /* If we wound up with things in our delay slot, flush them here. */ | |
3028 | if (current_function_epilogue_delay_list) | |
ab835497 | 3029 | { |
ef8200df JW |
3030 | rtx insn = emit_jump_insn_after (gen_rtx (RETURN, VOIDmode), |
3031 | get_last_insn ()); | |
3032 | PATTERN (insn) = gen_rtx (PARALLEL, VOIDmode, | |
3033 | gen_rtvec (2, | |
3034 | PATTERN (XEXP (current_function_epilogue_delay_list, 0)), | |
3035 | PATTERN (insn))); | |
3036 | final_scan_insn (insn, file, 1, 0, 1); | |
ab835497 RK |
3037 | } |
3038 | else | |
ef8200df JW |
3039 | fprintf (file, "\t%s\n\trestore\n", ret); |
3040 | } | |
915f619f JW |
3041 | /* All of the following cases are for leaf functions. */ |
3042 | else if (current_function_epilogue_delay_list) | |
ef8200df | 3043 | { |
915f619f JW |
3044 | /* eligible_for_epilogue_delay_slot ensures that if this is a |
3045 | leaf function, then we will only have insn in the delay slot | |
3046 | if the frame size is zero, thus no adjust for the stack is | |
3047 | needed here. */ | |
3048 | if (actual_fsize != 0) | |
ef8200df | 3049 | abort (); |
915f619f JW |
3050 | fprintf (file, "\t%s\n", ret); |
3051 | final_scan_insn (XEXP (current_function_epilogue_delay_list, 0), | |
3052 | file, 1, 0, 1); | |
ab835497 | 3053 | } |
9bb7ffda JW |
3054 | /* Output 'nop' instead of 'sub %sp,-0,%sp' when no frame, so as to |
3055 | avoid generating confusing assembly language output. */ | |
3056 | else if (actual_fsize == 0) | |
3057 | fprintf (file, "\t%s\n\tnop\n", ret); | |
915f619f JW |
3058 | else if (actual_fsize <= 4096) |
3059 | fprintf (file, "\t%s\n\tsub %%sp,-%d,%%sp\n", ret, actual_fsize); | |
3060 | else if (actual_fsize <= 8192) | |
3061 | fprintf (file, "\tsub %%sp,-4096,%%sp\n\t%s\n\tsub %%sp,-%d,%%sp\n", | |
3062 | ret, actual_fsize - 4096); | |
3063 | else if ((actual_fsize & 0x3ff) == 0) | |
3064 | fprintf (file, "\tsethi %%hi(%d),%%g1\n\t%s\n\tadd %%sp,%%g1,%%sp\n", | |
3065 | actual_fsize, ret); | |
3066 | else | |
3067 | fprintf (file, "\tsethi %%hi(%d),%%g1\n\tor %%g1,%%lo(%d),%%g1\n\t%s\n\tadd %%sp,%%g1,%%sp\n", | |
3068 | actual_fsize, actual_fsize, ret); | |
ef8200df | 3069 | target_flags |= old_target_epilogue; |
ab835497 RK |
3070 | } |
3071 | } | |
3ea1fdd3 | 3072 | |
61a55e8b DE |
3073 | /* Do what is necessary for `va_start'. The argument is ignored. |
3074 | !v9: We look at the current function to determine if stdarg or varargs | |
3075 | is used and return the address of the first unnamed parameter. | |
3076 | v9: We save the argument integer and floating point regs in a buffer, and | |
3077 | return the address of this buffer. The rest is handled in va-sparc.h. */ | |
3078 | /* ??? This is currently conditioned on #ifdef SPARCV9 because | |
3079 | current_function_args_info is different in each compiler. */ | |
3080 | ||
3081 | #ifdef SPARCV9 | |
3082 | ||
3083 | rtx | |
3084 | sparc_builtin_saveregs (arglist) | |
3085 | tree arglist; | |
3086 | { | |
3087 | tree fntype = TREE_TYPE (current_function_decl); | |
3088 | /* First unnamed integer register. */ | |
3089 | int first_intreg = current_function_args_info.arg_count[0]; | |
3090 | /* Number of integer registers we need to save. */ | |
3091 | int n_intregs = MAX (0, NPARM_REGS (SImode) - first_intreg); | |
3092 | /* First unnamed SFmode float reg (no, you can't pass SFmode floats as | |
3093 | unnamed arguments, we just number them that way). */ | |
3094 | int first_floatreg = current_function_args_info.arg_count[1] + 1 & ~1; | |
3095 | /* Number of SFmode float regs to save. */ | |
3096 | int n_floatregs = MAX (0, NPARM_REGS (SFmode) - first_floatreg); | |
3097 | int ptrsize = GET_MODE_SIZE (Pmode); | |
3098 | rtx valist, regbuf, fpregs; | |
3099 | int regno; | |
3100 | ||
3101 | /* Allocate block of memory for the regs. | |
3102 | We only allocate as much as we need. */ | |
3103 | /* ??? If n_intregs + n_floatregs == 0, should we allocate at least 1 byte? | |
3104 | Or can assign_stack_local accept a 0 SIZE argument? */ | |
3105 | ||
3106 | regbuf = assign_stack_local (BLKmode, | |
3107 | (n_intregs * UNITS_PER_WORD | |
3108 | + n_floatregs * FLOAT_TYPE_SIZE/BITS_PER_UNIT), | |
3109 | BITS_PER_WORD); | |
3110 | MEM_IN_STRUCT_P (regbuf) = 1; | |
3111 | ||
3112 | /* Save int args. | |
3113 | This is optimized to only save the regs that are necessary. Explicitly | |
3114 | named args need not be saved. */ | |
3115 | ||
3116 | if (n_intregs > 0) | |
3117 | move_block_from_reg (BASE_INCOMING_ARG_REG (SImode) + first_intreg, | |
3118 | regbuf, n_intregs, n_intregs * UNITS_PER_WORD); | |
3119 | ||
3120 | /* Save float args. | |
3121 | This is optimized to only save the regs that are necessary. Explicitly | |
3122 | named args need not be saved. | |
3123 | We explicitly build a pointer to the buffer because it halves the insn | |
3124 | count when not optimizing (otherwise the pointer is built for each reg | |
3125 | saved). */ | |
3126 | ||
3127 | fpregs = gen_reg_rtx (Pmode); | |
3128 | emit_move_insn (fpregs, plus_constant (XEXP (regbuf, 0), | |
3129 | n_intregs * UNITS_PER_WORD)); | |
3130 | for (regno = first_floatreg; regno < NPARM_REGS (SFmode); regno += 2) | |
3131 | emit_move_insn (gen_rtx (MEM, DFmode, | |
3132 | plus_constant (fpregs, | |
3133 | GET_MODE_SIZE (SFmode) * regno)), | |
3134 | gen_rtx (REG, DFmode, BASE_INCOMING_ARG_REG (DFmode) | |
3135 | + regno)); | |
3136 | ||
3137 | /* Return the address of the regbuf. */ | |
3138 | ||
3139 | return XEXP (regbuf, 0); | |
3140 | } | |
3141 | ||
3142 | #else /* ! SPARCV9 */ | |
3ea1fdd3 JW |
3143 | |
3144 | rtx | |
3145 | sparc_builtin_saveregs (arglist) | |
3146 | tree arglist; | |
3147 | { | |
3148 | tree fntype = TREE_TYPE (current_function_decl); | |
3149 | int stdarg = (TYPE_ARG_TYPES (fntype) != 0 | |
3150 | && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype))) | |
3151 | != void_type_node)); | |
3152 | int first_reg = current_function_args_info; | |
3153 | rtx address; | |
3154 | int regno; | |
3155 | ||
227f7fd9 RS |
3156 | #if 0 /* This code seemed to have no effect except to make |
3157 | varargs not work right when va_list wasn't the first arg. */ | |
3ea1fdd3 JW |
3158 | if (! stdarg) |
3159 | first_reg = 0; | |
227f7fd9 | 3160 | #endif |
3ea1fdd3 | 3161 | |
61a55e8b | 3162 | for (regno = first_reg; regno < NPARM_REGS (SImode); regno++) |
3ea1fdd3 JW |
3163 | emit_move_insn (gen_rtx (MEM, word_mode, |
3164 | gen_rtx (PLUS, Pmode, | |
3165 | frame_pointer_rtx, | |
3166 | GEN_INT (STACK_POINTER_OFFSET | |
3167 | + UNITS_PER_WORD * regno))), | |
3168 | gen_rtx (REG, word_mode, BASE_INCOMING_ARG_REG (word_mode) | |
3169 | + regno)); | |
3170 | ||
3171 | address = gen_rtx (PLUS, Pmode, | |
3172 | frame_pointer_rtx, | |
3173 | GEN_INT (STACK_POINTER_OFFSET | |
3174 | + UNITS_PER_WORD * first_reg)); | |
3175 | ||
3176 | return address; | |
3177 | } | |
61a55e8b DE |
3178 | |
3179 | #endif /* ! SPARCV9 */ | |
ab835497 RK |
3180 | \f |
3181 | /* Return the string to output a conditional branch to LABEL, which is | |
3182 | the operand number of the label. OP is the conditional expression. The | |
3183 | mode of register 0 says what kind of comparison we made. | |
3184 | ||
61a55e8b DE |
3185 | FP_COND_REG indicates which fp condition code register to use if this is |
3186 | a floating point branch. | |
3187 | ||
ab835497 RK |
3188 | REVERSED is non-zero if we should reverse the sense of the comparison. |
3189 | ||
3190 | ANNUL is non-zero if we should generate an annulling branch. | |
3191 | ||
3192 | NOOP is non-zero if we have to follow this branch by a noop. */ | |
3193 | ||
3194 | char * | |
61a55e8b DE |
3195 | output_cbranch (op, fp_cond_reg, label, reversed, annul, noop) |
3196 | rtx op, fp_cond_reg; | |
ab835497 RK |
3197 | int label; |
3198 | int reversed, annul, noop; | |
3199 | { | |
3200 | static char string[20]; | |
3201 | enum rtx_code code = GET_CODE (op); | |
3202 | enum machine_mode mode = GET_MODE (XEXP (op, 0)); | |
61a55e8b DE |
3203 | static char v8_labelno[] = " %lX"; |
3204 | static char v9_icc_labelno[] = " %%icc,%lX"; | |
3205 | static char v9_xcc_labelno[] = " %%xcc,%lX"; | |
3206 | static char v9_fcc_labelno[] = " %%fccX,%lY"; | |
3207 | char *labelno; | |
3208 | int labeloff; | |
3209 | ||
3210 | /* ??? !v9: FP branches cannot be preceded by another floating point insn. | |
ab835497 RK |
3211 | Because there is currently no concept of pre-delay slots, we can fix |
3212 | this only by always emitting a nop before a floating point branch. */ | |
3213 | ||
61a55e8b | 3214 | if ((mode == CCFPmode || mode == CCFPEmode) && ! TARGET_V9) |
ab835497 | 3215 | strcpy (string, "nop\n\t"); |
61a55e8b DE |
3216 | else |
3217 | string[0] = '\0'; | |
ab835497 RK |
3218 | |
3219 | /* If not floating-point or if EQ or NE, we can just reverse the code. */ | |
4d449554 JW |
3220 | if (reversed |
3221 | && ((mode != CCFPmode && mode != CCFPEmode) || code == EQ || code == NE)) | |
ab835497 RK |
3222 | code = reverse_condition (code), reversed = 0; |
3223 | ||
3224 | /* Start by writing the branch condition. */ | |
3225 | switch (code) | |
3226 | { | |
3227 | case NE: | |
4d449554 | 3228 | if (mode == CCFPmode || mode == CCFPEmode) |
ab835497 RK |
3229 | strcat (string, "fbne"); |
3230 | else | |
3231 | strcpy (string, "bne"); | |
3232 | break; | |
3233 | ||
3234 | case EQ: | |
4d449554 | 3235 | if (mode == CCFPmode || mode == CCFPEmode) |
ab835497 RK |
3236 | strcat (string, "fbe"); |
3237 | else | |
3238 | strcpy (string, "be"); | |
3239 | break; | |
3240 | ||
3241 | case GE: | |
4d449554 | 3242 | if (mode == CCFPmode || mode == CCFPEmode) |
ab835497 RK |
3243 | { |
3244 | if (reversed) | |
3245 | strcat (string, "fbul"); | |
3246 | else | |
3247 | strcat (string, "fbge"); | |
3248 | } | |
3249 | else if (mode == CC_NOOVmode) | |
3250 | strcpy (string, "bpos"); | |
3251 | else | |
3252 | strcpy (string, "bge"); | |
3253 | break; | |
3254 | ||
3255 | case GT: | |
4d449554 | 3256 | if (mode == CCFPmode || mode == CCFPEmode) |
ab835497 RK |
3257 | { |
3258 | if (reversed) | |
3259 | strcat (string, "fbule"); | |
3260 | else | |
3261 | strcat (string, "fbg"); | |
3262 | } | |
3263 | else | |
3264 | strcpy (string, "bg"); | |
3265 | break; | |
3266 | ||
3267 | case LE: | |
4d449554 | 3268 | if (mode == CCFPmode || mode == CCFPEmode) |
ab835497 RK |
3269 | { |
3270 | if (reversed) | |
3271 | strcat (string, "fbug"); | |
3272 | else | |
3273 | strcat (string, "fble"); | |
3274 | } | |
3275 | else | |
3276 | strcpy (string, "ble"); | |
3277 | break; | |
3278 | ||
3279 | case LT: | |
4d449554 | 3280 | if (mode == CCFPmode || mode == CCFPEmode) |
ab835497 RK |
3281 | { |
3282 | if (reversed) | |
3283 | strcat (string, "fbuge"); | |
3284 | else | |
3285 | strcat (string, "fbl"); | |
3286 | } | |
3287 | else if (mode == CC_NOOVmode) | |
3288 | strcpy (string, "bneg"); | |
3289 | else | |
3290 | strcpy (string, "bl"); | |
3291 | break; | |
3292 | ||
3293 | case GEU: | |
3294 | strcpy (string, "bgeu"); | |
3295 | break; | |
3296 | ||
3297 | case GTU: | |
3298 | strcpy (string, "bgu"); | |
3299 | break; | |
3300 | ||
3301 | case LEU: | |
3302 | strcpy (string, "bleu"); | |
3303 | break; | |
3304 | ||
3305 | case LTU: | |
3306 | strcpy (string, "blu"); | |
3307 | break; | |
3308 | } | |
3309 | ||
3310 | /* Now add the annulling, the label, and a possible noop. */ | |
3311 | if (annul) | |
3312 | strcat (string, ",a"); | |
3313 | ||
61a55e8b DE |
3314 | /* ??? If v9, optional prediction bit ",pt" or ",pf" goes here. */ |
3315 | ||
3316 | if (! TARGET_V9) | |
3317 | { | |
3318 | labeloff = 3; | |
3319 | labelno = v8_labelno; | |
3320 | } | |
3321 | else | |
3322 | { | |
3323 | labeloff = 9; | |
3324 | if (mode == CCFPmode || mode == CCFPEmode) | |
3325 | { | |
3326 | labeloff = 10; | |
3327 | labelno = v9_fcc_labelno; | |
3328 | /* Set the char indicating the number of the fcc reg to use. */ | |
3329 | labelno[6] = REGNO (fp_cond_reg) - 96 + '0'; | |
3330 | } | |
3331 | else if (mode == CCXmode || mode == CCX_NOOVmode) | |
3332 | labelno = v9_xcc_labelno; | |
3333 | else | |
3334 | labelno = v9_icc_labelno; | |
3335 | } | |
3336 | /* Set the char indicating the number of the operand containing the | |
3337 | label_ref. */ | |
3338 | labelno[labeloff] = label + '0'; | |
3339 | strcat (string, labelno); | |
3340 | ||
3341 | if (noop) | |
3342 | strcat (string, "\n\tnop"); | |
3343 | ||
3344 | return string; | |
3345 | } | |
3346 | ||
3347 | /* Return the string to output a conditional branch to LABEL, testing | |
3348 | register REG. LABEL is the operand number of the label; REG is the | |
3349 | operand number of the reg. OP is the conditional expression. The mode | |
3350 | of REG says what kind of comparison we made. | |
3351 | ||
3352 | REVERSED is non-zero if we should reverse the sense of the comparison. | |
3353 | ||
3354 | ANNUL is non-zero if we should generate an annulling branch. | |
3355 | ||
3356 | NOOP is non-zero if we have to follow this branch by a noop. */ | |
3357 | ||
3358 | char * | |
3359 | output_v9branch (op, reg, label, reversed, annul, noop) | |
3360 | rtx op; | |
3361 | int reg, label; | |
3362 | int reversed, annul, noop; | |
3363 | { | |
3364 | static char string[20]; | |
3365 | enum rtx_code code = GET_CODE (op); | |
3366 | enum machine_mode mode = GET_MODE (XEXP (op, 0)); | |
3367 | static char labelno[] = " %X,%lX"; | |
3368 | ||
3369 | /* If not floating-point or if EQ or NE, we can just reverse the code. */ | |
3370 | if (reversed) | |
3371 | code = reverse_condition (code), reversed = 0; | |
3372 | ||
3373 | /* Only 64 bit versions of these instructions exist. */ | |
3374 | if (mode != DImode) | |
3375 | abort (); | |
3376 | ||
3377 | /* Start by writing the branch condition. */ | |
3378 | ||
3379 | switch (code) | |
3380 | { | |
3381 | case NE: | |
3382 | strcpy (string, "brnz"); | |
3383 | break; | |
3384 | ||
3385 | case EQ: | |
3386 | strcpy (string, "brz"); | |
3387 | break; | |
3388 | ||
3389 | case GE: | |
3390 | strcpy (string, "brgez"); | |
3391 | break; | |
3392 | ||
3393 | case LT: | |
3394 | strcpy (string, "brlz"); | |
3395 | break; | |
3396 | ||
3397 | case LE: | |
3398 | strcpy (string, "brlez"); | |
3399 | break; | |
3400 | ||
3401 | case GT: | |
3402 | strcpy (string, "brgz"); | |
3403 | break; | |
3404 | ||
3405 | default: | |
3406 | abort (); | |
3407 | } | |
3408 | ||
3409 | /* Now add the annulling, reg, label, and nop. */ | |
3410 | if (annul) | |
3411 | strcat (string, ",a"); | |
3412 | ||
3413 | /* ??? Optional prediction bit ",pt" or ",pf" goes here. */ | |
3414 | ||
3415 | labelno[2] = reg + '0'; | |
3416 | labelno[6] = label + '0'; | |
ab835497 RK |
3417 | strcat (string, labelno); |
3418 | ||
3419 | if (noop) | |
3420 | strcat (string, "\n\tnop"); | |
3421 | ||
3422 | return string; | |
3423 | } | |
3424 | ||
795068a4 JW |
3425 | /* Output assembler code to return from a function. */ |
3426 | ||
61a55e8b DE |
3427 | /* ??? v9: Update to use the new `return' instruction. Also, add patterns to |
3428 | md file for the `return' instruction. */ | |
3429 | ||
ab835497 RK |
3430 | char * |
3431 | output_return (operands) | |
3432 | rtx *operands; | |
3433 | { | |
3434 | if (leaf_label) | |
3435 | { | |
3436 | operands[0] = leaf_label; | |
3437 | return "b,a %l0"; | |
3438 | } | |
3439 | else if (leaf_function) | |
3440 | { | |
915f619f JW |
3441 | /* If we didn't allocate a frame pointer for the current function, |
3442 | the stack pointer might have been adjusted. Output code to | |
3443 | restore it now. */ | |
3444 | ||
ab835497 | 3445 | operands[0] = gen_rtx (CONST_INT, VOIDmode, actual_fsize); |
915f619f JW |
3446 | |
3447 | /* Use sub of negated value in first two cases instead of add to | |
3448 | allow actual_fsize == 4096. */ | |
3449 | ||
3450 | if (actual_fsize <= 4096) | |
ab835497 | 3451 | { |
61a55e8b | 3452 | if (SKIP_CALLERS_UNIMP_P) |
915f619f | 3453 | return "jmp %%o7+12\n\tsub %%sp,-%0,%%sp"; |
ab835497 | 3454 | else |
915f619f | 3455 | return "retl\n\tsub %%sp,-%0,%%sp"; |
ab835497 | 3456 | } |
915f619f | 3457 | else if (actual_fsize <= 8192) |
ab835497 | 3458 | { |
915f619f | 3459 | operands[0] = gen_rtx (CONST_INT, VOIDmode, actual_fsize - 4096); |
61a55e8b | 3460 | if (SKIP_CALLERS_UNIMP_P) |
915f619f JW |
3461 | return "sub %%sp,-4096,%%sp\n\tjmp %%o7+12\n\tsub %%sp,-%0,%%sp"; |
3462 | else | |
3463 | return "sub %%sp,-4096,%%sp\n\tretl\n\tsub %%sp,-%0,%%sp"; | |
3464 | } | |
61a55e8b | 3465 | else if (SKIP_CALLERS_UNIMP_P) |
915f619f JW |
3466 | { |
3467 | if ((actual_fsize & 0x3ff) != 0) | |
ab835497 RK |
3468 | return "sethi %%hi(%a0),%%g1\n\tor %%g1,%%lo(%a0),%%g1\n\tjmp %%o7+12\n\tadd %%sp,%%g1,%%sp"; |
3469 | else | |
915f619f JW |
3470 | return "sethi %%hi(%a0),%%g1\n\tjmp %%o7+12\n\tadd %%sp,%%g1,%%sp"; |
3471 | } | |
3472 | else | |
3473 | { | |
3474 | if ((actual_fsize & 0x3ff) != 0) | |
ab835497 | 3475 | return "sethi %%hi(%a0),%%g1\n\tor %%g1,%%lo(%a0),%%g1\n\tretl\n\tadd %%sp,%%g1,%%sp"; |
915f619f JW |
3476 | else |
3477 | return "sethi %%hi(%a0),%%g1\n\tretl\n\tadd %%sp,%%g1,%%sp"; | |
ab835497 RK |
3478 | } |
3479 | } | |
3480 | else | |
3481 | { | |
61a55e8b | 3482 | if (SKIP_CALLERS_UNIMP_P) |
ab835497 RK |
3483 | return "jmp %%i7+12\n\trestore"; |
3484 | else | |
3485 | return "ret\n\trestore"; | |
3486 | } | |
3487 | } | |
ab835497 RK |
3488 | \f |
3489 | /* Leaf functions and non-leaf functions have different needs. */ | |
3490 | ||
3491 | static int | |
3492 | reg_leaf_alloc_order[] = REG_LEAF_ALLOC_ORDER; | |
3493 | ||
3494 | static int | |
3495 | reg_nonleaf_alloc_order[] = REG_ALLOC_ORDER; | |
3496 | ||
3497 | static int *reg_alloc_orders[] = { | |
3498 | reg_leaf_alloc_order, | |
3499 | reg_nonleaf_alloc_order}; | |
3500 | ||
3501 | void | |
3502 | order_regs_for_local_alloc () | |
3503 | { | |
3504 | static int last_order_nonleaf = 1; | |
3505 | ||
3506 | if (regs_ever_live[15] != last_order_nonleaf) | |
3507 | { | |
3508 | last_order_nonleaf = !last_order_nonleaf; | |
3509 | bcopy (reg_alloc_orders[last_order_nonleaf], reg_alloc_order, | |
3510 | FIRST_PSEUDO_REGISTER * sizeof (int)); | |
3511 | } | |
3512 | } | |
3513 | \f | |
35016322 JW |
3514 | /* Return 1 if REGNO (reg1) is even and REGNO (reg1) == REGNO (reg2) - 1. |
3515 | This makes them candidates for using ldd and std insns. | |
3516 | ||
3517 | Note reg1 and reg2 *must* be hard registers. To be sure we will | |
3518 | abort if we are passed pseudo registers. */ | |
3519 | ||
3520 | int | |
7c56249d | 3521 | registers_ok_for_ldd_peep (reg1, reg2) |
35016322 JW |
3522 | rtx reg1, reg2; |
3523 | { | |
35016322 JW |
3524 | /* We might have been passed a SUBREG. */ |
3525 | if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG) | |
3526 | return 0; | |
3527 | ||
35016322 JW |
3528 | if (REGNO (reg1) % 2 != 0) |
3529 | return 0; | |
3530 | ||
3531 | return (REGNO (reg1) == REGNO (reg2) - 1); | |
35016322 JW |
3532 | } |
3533 | ||
3534 | /* Return 1 if addr1 and addr2 are suitable for use in an ldd or | |
3535 | std insn. | |
3536 | ||
3537 | This can only happen when addr1 and addr2 are consecutive memory | |
3538 | locations (addr1 + 4 == addr2). addr1 must also be aligned on a | |
3539 | 64 bit boundary (addr1 % 8 == 0). | |
3540 | ||
3541 | We know %sp and %fp are kept aligned on a 64 bit boundary. Other | |
3542 | registers are assumed to *never* be properly aligned and are | |
3543 | rejected. | |
3544 | ||
3545 | Knowing %sp and %fp are kept aligned on a 64 bit boundary, we | |
3546 | need only check that the offset for addr1 % 8 == 0. */ | |
3547 | ||
3548 | int | |
7c56249d | 3549 | addrs_ok_for_ldd_peep (addr1, addr2) |
35016322 JW |
3550 | rtx addr1, addr2; |
3551 | { | |
3552 | int reg1, offset1; | |
3553 | ||
3554 | /* Extract a register number and offset (if used) from the first addr. */ | |
3555 | if (GET_CODE (addr1) == PLUS) | |
3556 | { | |
3557 | /* If not a REG, return zero. */ | |
3558 | if (GET_CODE (XEXP (addr1, 0)) != REG) | |
3559 | return 0; | |
3560 | else | |
3561 | { | |
3562 | reg1 = REGNO (XEXP (addr1, 0)); | |
3563 | /* The offset must be constant! */ | |
3564 | if (GET_CODE (XEXP (addr1, 1)) != CONST_INT) | |
3565 | return 0; | |
3566 | offset1 = INTVAL (XEXP (addr1, 1)); | |
3567 | } | |
3568 | } | |
3569 | else if (GET_CODE (addr1) != REG) | |
3570 | return 0; | |
3571 | else | |
3572 | { | |
3573 | reg1 = REGNO (addr1); | |
3574 | /* This was a simple (mem (reg)) expression. Offset is 0. */ | |
3575 | offset1 = 0; | |
3576 | } | |
3577 | ||
3578 | /* Make sure the second address is a (mem (plus (reg) (const_int). */ | |
3579 | if (GET_CODE (addr2) != PLUS) | |
3580 | return 0; | |
3581 | ||
3582 | if (GET_CODE (XEXP (addr2, 0)) != REG | |
3583 | || GET_CODE (XEXP (addr2, 1)) != CONST_INT) | |
3584 | return 0; | |
3585 | ||
3586 | /* Only %fp and %sp are allowed. Additionally both addresses must | |
3587 | use the same register. */ | |
3588 | if (reg1 != FRAME_POINTER_REGNUM && reg1 != STACK_POINTER_REGNUM) | |
3589 | return 0; | |
3590 | ||
3591 | if (reg1 != REGNO (XEXP (addr2, 0))) | |
3592 | return 0; | |
3593 | ||
2296cba3 | 3594 | /* The first offset must be evenly divisible by 8 to ensure the |
35016322 JW |
3595 | address is 64 bit aligned. */ |
3596 | if (offset1 % 8 != 0) | |
3597 | return 0; | |
3598 | ||
3599 | /* The offset for the second addr must be 4 more than the first addr. */ | |
3600 | if (INTVAL (XEXP (addr2, 1)) != offset1 + 4) | |
3601 | return 0; | |
3602 | ||
3603 | /* All the tests passed. addr1 and addr2 are valid for ldd and std | |
3604 | instructions. */ | |
3605 | return 1; | |
3606 | } | |
7c56249d JL |
3607 | |
3608 | /* Return 1 if reg is a pseudo, or is the first register in | |
3609 | a hard register pair. This makes it a candidate for use in | |
3610 | ldd and std insns. */ | |
3611 | ||
3612 | int | |
3613 | register_ok_for_ldd (reg) | |
3614 | rtx reg; | |
3615 | { | |
7c56249d JL |
3616 | /* We might have been passed a SUBREG. */ |
3617 | if (GET_CODE (reg) != REG) | |
3618 | return 0; | |
3619 | ||
3620 | if (REGNO (reg) < FIRST_PSEUDO_REGISTER) | |
3621 | return (REGNO (reg) % 2 == 0); | |
3622 | else | |
3623 | return 1; | |
7c56249d | 3624 | } |
ab835497 | 3625 | \f |
ab835497 RK |
3626 | /* Print operand X (an rtx) in assembler syntax to file FILE. |
3627 | CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. | |
3628 | For `%' followed by punctuation, CODE is the punctuation and X is null. */ | |
3629 | ||
3630 | void | |
3631 | print_operand (file, x, code) | |
3632 | FILE *file; | |
3633 | rtx x; | |
3634 | int code; | |
3635 | { | |
3636 | switch (code) | |
3637 | { | |
3638 | case '#': | |
3639 | /* Output a 'nop' if there's nothing for the delay slot. */ | |
3640 | if (dbr_sequence_length () == 0) | |
3641 | fputs ("\n\tnop", file); | |
3642 | return; | |
3643 | case '*': | |
c6ce0969 JW |
3644 | /* Output an annul flag if there's nothing for the delay slot and we |
3645 | are optimizing. This is always used with '(' below. */ | |
3646 | /* Sun OS 4.1.1 dbx can't handle an annulled unconditional branch; | |
3647 | this is a dbx bug. So, we only do this when optimizing. */ | |
3648 | if (dbr_sequence_length () == 0 && optimize) | |
3649 | fputs (",a", file); | |
3650 | return; | |
3651 | case '(': | |
3652 | /* Output a 'nop' if there's nothing for the delay slot and we are | |
3653 | not optimizing. This is always used with '*' above. */ | |
3654 | if (dbr_sequence_length () == 0 && ! optimize) | |
3655 | fputs ("\n\tnop", file); | |
ab835497 | 3656 | return; |
61a55e8b DE |
3657 | case '_': |
3658 | /* Output the Medium/Anywhere code model base register. */ | |
3659 | fputs (MEDANY_BASE_REG, file); | |
3660 | return; | |
3661 | case '@': | |
3662 | /* Print out what we are using as the frame pointer. This might | |
3663 | be %fp, or might be %sp+offset. */ | |
3664 | /* ??? What if offset is too big? Perhaps the caller knows it isn't? */ | |
3665 | fprintf (file, "%s+%d", frame_base_name, frame_base_offset); | |
3666 | return; | |
ab835497 RK |
3667 | case 'Y': |
3668 | /* Adjust the operand to take into account a RESTORE operation. */ | |
3669 | if (GET_CODE (x) != REG) | |
b3b1e8bd JW |
3670 | output_operand_lossage ("Invalid %%Y operand"); |
3671 | else if (REGNO (x) < 8) | |
ab835497 RK |
3672 | fputs (reg_names[REGNO (x)], file); |
3673 | else if (REGNO (x) >= 24 && REGNO (x) < 32) | |
3674 | fputs (reg_names[REGNO (x)-16], file); | |
3675 | else | |
b3b1e8bd | 3676 | output_operand_lossage ("Invalid %%Y operand"); |
ab835497 | 3677 | return; |
ab835497 | 3678 | case 'R': |
795068a4 | 3679 | /* Print out the second register name of a register pair or quad. |
ab835497 RK |
3680 | I.e., R (%o0) => %o1. */ |
3681 | fputs (reg_names[REGNO (x)+1], file); | |
3682 | return; | |
795068a4 JW |
3683 | case 'S': |
3684 | /* Print out the third register name of a register quad. | |
3685 | I.e., S (%o0) => %o2. */ | |
3686 | fputs (reg_names[REGNO (x)+2], file); | |
3687 | return; | |
3688 | case 'T': | |
3689 | /* Print out the fourth register name of a register quad. | |
3690 | I.e., T (%o0) => %o3. */ | |
3691 | fputs (reg_names[REGNO (x)+3], file); | |
3692 | return; | |
ab835497 RK |
3693 | case 'm': |
3694 | /* Print the operand's address only. */ | |
3695 | output_address (XEXP (x, 0)); | |
3696 | return; | |
3697 | case 'r': | |
3698 | /* In this case we need a register. Use %g0 if the | |
77a02b01 | 3699 | operand is const0_rtx. */ |
76052e74 RS |
3700 | if (x == const0_rtx |
3701 | || (GET_MODE (x) != VOIDmode && x == CONST0_RTX (GET_MODE (x)))) | |
ab835497 RK |
3702 | { |
3703 | fputs ("%g0", file); | |
3704 | return; | |
3705 | } | |
3706 | else | |
3707 | break; | |
3708 | ||
61a55e8b | 3709 | case 'A': |
ab835497 RK |
3710 | switch (GET_CODE (x)) |
3711 | { | |
3712 | case IOR: fputs ("or", file); break; | |
3713 | case AND: fputs ("and", file); break; | |
3714 | case XOR: fputs ("xor", file); break; | |
b3b1e8bd | 3715 | default: output_operand_lossage ("Invalid %%A operand"); |
ab835497 RK |
3716 | } |
3717 | return; | |
3718 | ||
3719 | case 'B': | |
3720 | switch (GET_CODE (x)) | |
3721 | { | |
3722 | case IOR: fputs ("orn", file); break; | |
3723 | case AND: fputs ("andn", file); break; | |
3724 | case XOR: fputs ("xnor", file); break; | |
b3b1e8bd | 3725 | default: output_operand_lossage ("Invalid %%B operand"); |
ab835497 RK |
3726 | } |
3727 | return; | |
3728 | ||
61a55e8b DE |
3729 | /* This is used by the conditional move instructions. */ |
3730 | case 'C': | |
3731 | switch (GET_CODE (x)) | |
3732 | { | |
3733 | case NE: fputs ("ne", file); break; | |
3734 | case EQ: fputs ("e", file); break; | |
3735 | case GE: fputs ("ge", file); break; | |
3736 | case GT: fputs ("g", file); break; | |
3737 | case LE: fputs ("le", file); break; | |
3738 | case LT: fputs ("l", file); break; | |
3739 | case GEU: fputs ("geu", file); break; | |
3740 | case GTU: fputs ("gu", file); break; | |
3741 | case LEU: fputs ("leu", file); break; | |
3742 | case LTU: fputs ("lu", file); break; | |
3743 | default: output_operand_lossage ("Invalid %%C operand"); | |
3744 | } | |
3745 | return; | |
3746 | ||
3747 | /* This is used by the movr instruction pattern. */ | |
3748 | case 'D': | |
3749 | switch (GET_CODE (x)) | |
3750 | { | |
3751 | case NE: fputs ("ne", file); break; | |
3752 | case EQ: fputs ("e", file); break; | |
3753 | case GE: fputs ("gez", file); break; | |
3754 | case LT: fputs ("lz", file); break; | |
3755 | case LE: fputs ("lez", file); break; | |
3756 | case GT: fputs ("gz", file); break; | |
3757 | default: output_operand_lossage ("Invalid %%D operand"); | |
3758 | } | |
3759 | return; | |
3760 | ||
ab835497 RK |
3761 | case 'b': |
3762 | { | |
3763 | /* Print a sign-extended character. */ | |
3764 | int i = INTVAL (x) & 0xff; | |
3765 | if (i & 0x80) | |
3766 | i |= 0xffffff00; | |
3767 | fprintf (file, "%d", i); | |
3768 | return; | |
3769 | } | |
3770 | ||
3771 | case 0: | |
3772 | /* Do nothing special. */ | |
3773 | break; | |
3774 | ||
3775 | default: | |
3776 | /* Undocumented flag. */ | |
415f583e | 3777 | output_operand_lossage ("invalid operand output code"); |
ab835497 RK |
3778 | } |
3779 | ||
3780 | if (GET_CODE (x) == REG) | |
3781 | fputs (reg_names[REGNO (x)], file); | |
3782 | else if (GET_CODE (x) == MEM) | |
3783 | { | |
3784 | fputc ('[', file); | |
3785 | if (CONSTANT_P (XEXP (x, 0))) | |
3786 | /* Poor Sun assembler doesn't understand absolute addressing. */ | |
3787 | fputs ("%g0+", file); | |
3788 | output_address (XEXP (x, 0)); | |
3789 | fputc (']', file); | |
3790 | } | |
3791 | else if (GET_CODE (x) == HIGH) | |
3792 | { | |
3793 | fputs ("%hi(", file); | |
3794 | output_addr_const (file, XEXP (x, 0)); | |
3795 | fputc (')', file); | |
3796 | } | |
3797 | else if (GET_CODE (x) == LO_SUM) | |
3798 | { | |
3799 | print_operand (file, XEXP (x, 0), 0); | |
3800 | fputs ("+%lo(", file); | |
3801 | output_addr_const (file, XEXP (x, 1)); | |
3802 | fputc (')', file); | |
3803 | } | |
e601abce JW |
3804 | else if (GET_CODE (x) == CONST_DOUBLE |
3805 | && (GET_MODE (x) == VOIDmode | |
3806 | || GET_MODE_CLASS (GET_MODE (x)) == MODE_INT)) | |
ab835497 RK |
3807 | { |
3808 | if (CONST_DOUBLE_HIGH (x) == 0) | |
3809 | fprintf (file, "%u", CONST_DOUBLE_LOW (x)); | |
3810 | else if (CONST_DOUBLE_HIGH (x) == -1 | |
3811 | && CONST_DOUBLE_LOW (x) < 0) | |
3812 | fprintf (file, "%d", CONST_DOUBLE_LOW (x)); | |
3813 | else | |
e601abce | 3814 | output_operand_lossage ("long long constant not a valid immediate operand"); |
ab835497 | 3815 | } |
e601abce JW |
3816 | else if (GET_CODE (x) == CONST_DOUBLE) |
3817 | output_operand_lossage ("floating point constant not a valid immediate operand"); | |
ab835497 RK |
3818 | else { output_addr_const (file, x); } |
3819 | } | |
3820 | \f | |
3821 | /* This function outputs assembler code for VALUE to FILE, where VALUE is | |
3822 | a 64 bit (DImode) value. */ | |
3823 | ||
3824 | /* ??? If there is a 64 bit counterpart to .word that the assembler | |
3825 | understands, then using that would simply this code greatly. */ | |
61a55e8b DE |
3826 | /* ??? We only output .xword's for symbols and only then in environments |
3827 | where the assembler can handle them. */ | |
ab835497 RK |
3828 | |
3829 | void | |
3830 | output_double_int (file, value) | |
3831 | FILE *file; | |
3832 | rtx value; | |
3833 | { | |
3834 | if (GET_CODE (value) == CONST_INT) | |
3835 | { | |
3836 | if (INTVAL (value) < 0) | |
3837 | ASM_OUTPUT_INT (file, constm1_rtx); | |
3838 | else | |
3839 | ASM_OUTPUT_INT (file, const0_rtx); | |
3840 | ASM_OUTPUT_INT (file, value); | |
3841 | } | |
3842 | else if (GET_CODE (value) == CONST_DOUBLE) | |
3843 | { | |
3844 | ASM_OUTPUT_INT (file, gen_rtx (CONST_INT, VOIDmode, | |
3845 | CONST_DOUBLE_HIGH (value))); | |
3846 | ASM_OUTPUT_INT (file, gen_rtx (CONST_INT, VOIDmode, | |
3847 | CONST_DOUBLE_LOW (value))); | |
3848 | } | |
3849 | else if (GET_CODE (value) == SYMBOL_REF | |
3850 | || GET_CODE (value) == CONST | |
61a55e8b DE |
3851 | || GET_CODE (value) == PLUS |
3852 | || (TARGET_V9 && | |
3853 | (GET_CODE (value) == LABEL_REF | |
3854 | || GET_CODE (value) == MINUS))) | |
ab835497 | 3855 | { |
61a55e8b DE |
3856 | if (!TARGET_V9 || TARGET_ENV32) |
3857 | { | |
3858 | ASM_OUTPUT_INT (file, const0_rtx); | |
3859 | ASM_OUTPUT_INT (file, value); | |
3860 | } | |
3861 | else | |
3862 | { | |
3863 | fprintf (file, "\t%s\t", ASM_LONGLONG); | |
3864 | output_addr_const (file, value); | |
3865 | fprintf (file, "\n"); | |
3866 | } | |
ab835497 RK |
3867 | } |
3868 | else | |
3869 | abort (); | |
3870 | } | |
210aa14a | 3871 | \f |
b0468b84 RK |
3872 | /* Return the value of a code used in the .proc pseudo-op that says |
3873 | what kind of result this function returns. For non-C types, we pick | |
3874 | the closest C type. */ | |
3875 | ||
77a02b01 JW |
3876 | #ifndef CHAR_TYPE_SIZE |
3877 | #define CHAR_TYPE_SIZE BITS_PER_UNIT | |
3878 | #endif | |
3879 | ||
3880 | #ifndef SHORT_TYPE_SIZE | |
3881 | #define SHORT_TYPE_SIZE (BITS_PER_UNIT * 2) | |
3882 | #endif | |
3883 | ||
3884 | #ifndef INT_TYPE_SIZE | |
3885 | #define INT_TYPE_SIZE BITS_PER_WORD | |
3886 | #endif | |
3887 | ||
3888 | #ifndef LONG_TYPE_SIZE | |
3889 | #define LONG_TYPE_SIZE BITS_PER_WORD | |
3890 | #endif | |
3891 | ||
3892 | #ifndef LONG_LONG_TYPE_SIZE | |
3893 | #define LONG_LONG_TYPE_SIZE (BITS_PER_WORD * 2) | |
3894 | #endif | |
3895 | ||
3896 | #ifndef FLOAT_TYPE_SIZE | |
3897 | #define FLOAT_TYPE_SIZE BITS_PER_WORD | |
3898 | #endif | |
3899 | ||
3900 | #ifndef DOUBLE_TYPE_SIZE | |
3901 | #define DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2) | |
3902 | #endif | |
3903 | ||
3904 | #ifndef LONG_DOUBLE_TYPE_SIZE | |
3905 | #define LONG_DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2) | |
3906 | #endif | |
210aa14a RS |
3907 | |
3908 | unsigned long | |
3909 | sparc_type_code (type) | |
3910 | register tree type; | |
3911 | { | |
3912 | register unsigned long qualifiers = 0; | |
3913 | register unsigned shift = 6; | |
3914 | ||
aee2c3c5 JW |
3915 | /* Only the first 30 bits of the qualifer are valid. We must refrain from |
3916 | setting more, since some assemblers will give an error for this. Also, | |
3917 | we must be careful to avoid shifts of 32 bits or more to avoid getting | |
3918 | unpredictable results. */ | |
3919 | ||
210aa14a RS |
3920 | for (;;) |
3921 | { | |
3922 | switch (TREE_CODE (type)) | |
3923 | { | |
3924 | case ERROR_MARK: | |
3925 | return qualifiers; | |
3926 | ||
3927 | case ARRAY_TYPE: | |
aee2c3c5 JW |
3928 | if (shift < 30) |
3929 | qualifiers |= (3 << shift); | |
210aa14a RS |
3930 | shift += 2; |
3931 | type = TREE_TYPE (type); | |
3932 | break; | |
3933 | ||
3934 | case FUNCTION_TYPE: | |
3935 | case METHOD_TYPE: | |
aee2c3c5 JW |
3936 | if (shift < 30) |
3937 | qualifiers |= (2 << shift); | |
210aa14a RS |
3938 | shift += 2; |
3939 | type = TREE_TYPE (type); | |
3940 | break; | |
3941 | ||
3942 | case POINTER_TYPE: | |
3943 | case REFERENCE_TYPE: | |
3944 | case OFFSET_TYPE: | |
aee2c3c5 JW |
3945 | if (shift < 30) |
3946 | qualifiers |= (1 << shift); | |
210aa14a RS |
3947 | shift += 2; |
3948 | type = TREE_TYPE (type); | |
3949 | break; | |
ab835497 | 3950 | |
210aa14a RS |
3951 | case RECORD_TYPE: |
3952 | return (qualifiers | 8); | |
3953 | ||
3954 | case UNION_TYPE: | |
b0468b84 | 3955 | case QUAL_UNION_TYPE: |
210aa14a RS |
3956 | return (qualifiers | 9); |
3957 | ||
3958 | case ENUMERAL_TYPE: | |
3959 | return (qualifiers | 10); | |
3960 | ||
3961 | case VOID_TYPE: | |
3962 | return (qualifiers | 16); | |
3963 | ||
3964 | case INTEGER_TYPE: | |
654209e6 JW |
3965 | /* If this is a range type, consider it to be the underlying |
3966 | type. */ | |
3967 | if (TREE_TYPE (type) != 0) | |
3968 | { | |
3969 | type = TREE_TYPE (type); | |
3970 | break; | |
3971 | } | |
3972 | ||
77a02b01 | 3973 | /* Carefully distinguish all the standard types of C, |
b0468b84 RK |
3974 | without messing up if the language is not C. We do this by |
3975 | testing TYPE_PRECISION and TREE_UNSIGNED. The old code used to | |
3976 | look at both the names and the above fields, but that's redundant. | |
3977 | Any type whose size is between two C types will be considered | |
3978 | to be the wider of the two types. Also, we do not have a | |
3979 | special code to use for "long long", so anything wider than | |
3980 | long is treated the same. Note that we can't distinguish | |
3981 | between "int" and "long" in this code if they are the same | |
3982 | size, but that's fine, since neither can the assembler. */ | |
3983 | ||
3984 | if (TYPE_PRECISION (type) <= CHAR_TYPE_SIZE) | |
3985 | return (qualifiers | (TREE_UNSIGNED (type) ? 12 : 2)); | |
77a02b01 | 3986 | |
b0468b84 RK |
3987 | else if (TYPE_PRECISION (type) <= SHORT_TYPE_SIZE) |
3988 | return (qualifiers | (TREE_UNSIGNED (type) ? 13 : 3)); | |
77a02b01 | 3989 | |
b0468b84 | 3990 | else if (TYPE_PRECISION (type) <= INT_TYPE_SIZE) |
77a02b01 JW |
3991 | return (qualifiers | (TREE_UNSIGNED (type) ? 14 : 4)); |
3992 | ||
b0468b84 | 3993 | else |
77a02b01 JW |
3994 | return (qualifiers | (TREE_UNSIGNED (type) ? 15 : 5)); |
3995 | ||
210aa14a | 3996 | case REAL_TYPE: |
77a02b01 JW |
3997 | /* Carefully distinguish all the standard types of C, |
3998 | without messing up if the language is not C. */ | |
b0468b84 | 3999 | |
77a02b01 | 4000 | if (TYPE_PRECISION (type) == FLOAT_TYPE_SIZE) |
210aa14a | 4001 | return (qualifiers | 6); |
b0468b84 RK |
4002 | |
4003 | else | |
4004 | return (qualifiers | 7); | |
210aa14a RS |
4005 | |
4006 | case COMPLEX_TYPE: /* GNU Fortran COMPLEX type. */ | |
13d39dbc | 4007 | /* ??? We need to distinguish between double and float complex types, |
c82aa69a JW |
4008 | but I don't know how yet because I can't reach this code from |
4009 | existing front-ends. */ | |
4010 | return (qualifiers | 7); /* Who knows? */ | |
4011 | ||
210aa14a RS |
4012 | case CHAR_TYPE: /* GNU Pascal CHAR type. Not used in C. */ |
4013 | case BOOLEAN_TYPE: /* GNU Fortran BOOLEAN type. */ | |
4014 | case FILE_TYPE: /* GNU Pascal FILE type. */ | |
26902ae0 | 4015 | case SET_TYPE: /* GNU Pascal SET type. */ |
210aa14a | 4016 | case LANG_TYPE: /* ? */ |
26902ae0 | 4017 | return qualifiers; |
210aa14a RS |
4018 | |
4019 | default: | |
4020 | abort (); /* Not a type! */ | |
4021 | } | |
4022 | } | |
4023 | } | |
ead69aea | 4024 | \f |
61a55e8b DE |
4025 | /* Nested function support. */ |
4026 | ||
4027 | /* Emit RTL insns to initialize the variable parts of a trampoline. | |
4028 | FNADDR is an RTX for the address of the function's pure code. | |
4029 | CXT is an RTX for the static chain value for the function. | |
4030 | ||
4031 | This takes 16 insns: 2 shifts & 2 ands (to split up addresses), 4 sethi | |
4032 | (to load in opcodes), 4 iors (to merge address and opcodes), and 4 writes | |
4033 | (to store insns). This is a bit excessive. Perhaps a different | |
4034 | mechanism would be better here. | |
4035 | ||
4036 | Emit 3 FLUSH instructions (UNSPEC_VOLATILE 2) to synchonize the data | |
4037 | and instruction caches. | |
4038 | ||
4039 | ??? v9: We assume the top 32 bits of function addresses are 0. */ | |
4040 | ||
4041 | void | |
4042 | sparc_initialize_trampoline (tramp, fnaddr, cxt) | |
4043 | rtx tramp, fnaddr, cxt; | |
4044 | { | |
4045 | rtx high_cxt = expand_shift (RSHIFT_EXPR, SImode, cxt, | |
4046 | size_int (10), 0, 1); | |
4047 | rtx high_fn = expand_shift (RSHIFT_EXPR, SImode, fnaddr, | |
4048 | size_int (10), 0, 1); | |
4049 | rtx low_cxt = expand_and (cxt, gen_rtx (CONST_INT, VOIDmode, 0x3ff), 0); | |
4050 | rtx low_fn = expand_and (fnaddr, gen_rtx (CONST_INT, VOIDmode, 0x3ff), 0); | |
4051 | rtx g1_sethi = gen_rtx (HIGH, SImode, | |
4052 | gen_rtx (CONST_INT, VOIDmode, 0x03000000)); | |
4053 | rtx g2_sethi = gen_rtx (HIGH, SImode, | |
4054 | gen_rtx (CONST_INT, VOIDmode, 0x05000000)); | |
4055 | rtx g1_ori = gen_rtx (HIGH, SImode, | |
4056 | gen_rtx (CONST_INT, VOIDmode, 0x82106000)); | |
4057 | rtx g2_ori = gen_rtx (HIGH, SImode, | |
4058 | gen_rtx (CONST_INT, VOIDmode, 0x8410A000)); | |
4059 | rtx tem = gen_reg_rtx (SImode); | |
4060 | emit_move_insn (tem, g1_sethi); | |
4061 | emit_insn (gen_iorsi3 (high_fn, high_fn, tem)); | |
4062 | emit_move_insn (gen_rtx (MEM, SImode, plus_constant (tramp, 0)), high_fn); | |
4063 | emit_move_insn (tem, g1_ori); | |
4064 | emit_insn (gen_iorsi3 (low_fn, low_fn, tem)); | |
4065 | emit_move_insn (gen_rtx (MEM, SImode, plus_constant (tramp, 4)), low_fn); | |
4066 | emit_move_insn (tem, g2_sethi); | |
4067 | emit_insn (gen_iorsi3 (high_cxt, high_cxt, tem)); | |
4068 | emit_move_insn (gen_rtx (MEM, SImode, plus_constant (tramp, 8)), high_cxt); | |
4069 | emit_move_insn (tem, g2_ori); | |
4070 | emit_insn (gen_iorsi3 (low_cxt, low_cxt, tem)); | |
4071 | emit_move_insn (gen_rtx (MEM, SImode, plus_constant (tramp, 16)), low_cxt); | |
4072 | emit_insn (gen_rtx (UNSPEC_VOLATILE, VOIDmode, | |
4073 | gen_rtvec (1, plus_constant (tramp, 0)), | |
4074 | 2)); | |
4075 | emit_insn (gen_rtx (UNSPEC_VOLATILE, VOIDmode, | |
4076 | gen_rtvec (1, plus_constant (tramp, 8)), | |
4077 | 2)); | |
4078 | emit_insn (gen_rtx (UNSPEC_VOLATILE, VOIDmode, | |
4079 | gen_rtvec (1, plus_constant (tramp, 16)), | |
4080 | 2)); | |
4081 | } | |
4082 | ||
4083 | void | |
4084 | sparc64_initialize_trampoline (tramp, fnaddr, cxt) | |
4085 | rtx tramp, fnaddr, cxt; | |
4086 | { | |
4087 | rtx fnaddrdi = gen_reg_rtx (Pmode); | |
4088 | rtx fnaddrsi = (emit_move_insn (fnaddrdi, fnaddr), | |
4089 | gen_rtx (SUBREG, SImode, fnaddrdi, 0)); | |
4090 | rtx cxtdi = gen_reg_rtx (Pmode); | |
4091 | rtx cxtsi = (emit_move_insn (cxtdi, cxt), | |
4092 | gen_rtx (SUBREG, SImode, cxtdi, 0)); | |
4093 | rtx high_cxt = expand_shift (RSHIFT_EXPR, SImode, cxtsi, | |
4094 | size_int (10), 0, 1); | |
4095 | rtx high_fn = expand_shift (RSHIFT_EXPR, SImode, fnaddrsi, | |
4096 | size_int (10), 0, 1); | |
4097 | rtx low_cxt = expand_and (cxtsi, gen_rtx (CONST_INT, VOIDmode, 0x3ff), 0); | |
4098 | rtx low_fn = expand_and (fnaddrsi, gen_rtx (CONST_INT, VOIDmode, 0x3ff), 0); | |
4099 | rtx g1_sethi = gen_rtx (HIGH, SImode, | |
4100 | gen_rtx (CONST_INT, VOIDmode, 0x03000000)); | |
4101 | rtx g2_sethi = gen_rtx (HIGH, SImode, | |
4102 | gen_rtx (CONST_INT, VOIDmode, 0x05000000)); | |
4103 | rtx g1_ori = gen_rtx (HIGH, SImode, | |
4104 | gen_rtx (CONST_INT, VOIDmode, 0x82106000)); | |
4105 | rtx g2_ori = gen_rtx (HIGH, SImode, | |
4106 | gen_rtx (CONST_INT, VOIDmode, 0x8410A000)); | |
4107 | rtx tem = gen_reg_rtx (SImode); | |
4108 | emit_move_insn (tem, g2_sethi); | |
4109 | emit_insn (gen_iorsi3 (high_fn, high_fn, tem)); | |
4110 | emit_move_insn (gen_rtx (MEM, SImode, plus_constant (tramp, 0)), high_fn); | |
4111 | emit_move_insn (tem, g2_ori); | |
4112 | emit_insn (gen_iorsi3 (low_fn, low_fn, tem)); | |
4113 | emit_move_insn (gen_rtx (MEM, SImode, plus_constant (tramp, 4)), low_fn); | |
4114 | emit_move_insn (tem, g1_sethi); | |
4115 | emit_insn (gen_iorsi3 (high_cxt, high_cxt, tem)); | |
4116 | emit_move_insn (gen_rtx (MEM, SImode, plus_constant (tramp, 8)), high_cxt); | |
4117 | emit_move_insn (tem, g1_ori); | |
4118 | emit_insn (gen_iorsi3 (low_cxt, low_cxt, tem)); | |
4119 | emit_move_insn (gen_rtx (MEM, SImode, plus_constant (tramp, 16)), low_cxt); | |
4120 | emit_insn (gen_rtx (UNSPEC_VOLATILE, VOIDmode, | |
4121 | gen_rtvec (1, plus_constant (tramp, 0)), | |
4122 | 2)); | |
4123 | emit_insn (gen_rtx (UNSPEC_VOLATILE, VOIDmode, | |
4124 | gen_rtvec (1, plus_constant (tramp, 8)), | |
4125 | 2)); | |
4126 | emit_insn (gen_rtx (UNSPEC_VOLATILE, VOIDmode, | |
4127 | gen_rtvec (1, plus_constant (tramp, 16)), | |
4128 | 2)); | |
4129 | } | |
4130 | \f | |
c819be5b JW |
4131 | /* Subroutines to support a flat (single) register window calling |
4132 | convention. */ | |
4133 | ||
4134 | /* Single-register window sparc stack frames look like: | |
4135 | ||
4136 | Before call After call | |
4137 | +-----------------------+ +-----------------------+ | |
4138 | high | | | | | |
4139 | mem. | | | | | |
4140 | | caller's temps. | | caller's temps. | | |
4141 | | | | | | |
4142 | +-----------------------+ +-----------------------+ | |
4143 | | | | | | |
4144 | | arguments on stack. | | arguments on stack. | | |
4145 | | |FP+92->| | | |
4146 | +-----------------------+ +-----------------------+ | |
4147 | | 6 words to save | | 6 words to save | | |
4148 | | arguments passed | | arguments passed | | |
4149 | | in registers, even | | in registers, even | | |
4150 | SP+68->| if not passed. |FP+68->| if not passed. | | |
4151 | +-----------------------+ +-----------------------+ | |
4152 | | 1 word struct addr |FP+64->| 1 word struct addr | | |
4153 | +-----------------------+ +-----------------------+ | |
4154 | | | | | | |
4155 | | 16 word reg save area | | 16 word reg save area | | |
4156 | SP->| | FP->| | | |
4157 | +-----------------------+ +-----------------------+ | |
4158 | | 4 word area for | | |
4159 | FP-16->| fp/alu reg moves | | |
4160 | +-----------------------+ | |
4161 | | | | |
4162 | | local variables | | |
4163 | | | | |
4164 | +-----------------------+ | |
4165 | | | | |
4166 | | fp register save | | |
4167 | | | | |
4168 | +-----------------------+ | |
4169 | | | | |
4170 | | gp register save | | |
4171 | | | | |
4172 | +-----------------------+ | |
4173 | | | | |
4174 | | alloca allocations | | |
4175 | | | | |
4176 | +-----------------------+ | |
4177 | | | | |
4178 | | arguments on stack | | |
4179 | SP+92->| | | |
4180 | +-----------------------+ | |
4181 | | 6 words to save | | |
4182 | | arguments passed | | |
4183 | | in registers, even | | |
4184 | low SP+68->| if not passed. | | |
4185 | memory +-----------------------+ | |
4186 | SP+64->| 1 word struct addr | | |
4187 | +-----------------------+ | |
4188 | | | | |
4189 | I 16 word reg save area | | |
4190 | SP->| | | |
4191 | +-----------------------+ */ | |
4192 | ||
c6aa9ce1 | 4193 | /* Structure to be filled in by sparc_flat_compute_frame_size with register |
c819be5b JW |
4194 | save masks, and offsets for the current function. */ |
4195 | ||
4196 | struct sparc_frame_info | |
4197 | { | |
4198 | unsigned long total_size; /* # bytes that the entire frame takes up. */ | |
4199 | unsigned long var_size; /* # bytes that variables take up. */ | |
4200 | unsigned long args_size; /* # bytes that outgoing arguments take up. */ | |
4201 | unsigned long extra_size; /* # bytes of extra gunk. */ | |
4202 | unsigned int gp_reg_size; /* # bytes needed to store gp regs. */ | |
4203 | unsigned int fp_reg_size; /* # bytes needed to store fp regs. */ | |
4204 | unsigned long mask; /* Mask of saved gp registers. */ | |
4205 | unsigned long fmask; /* Mask of saved fp registers. */ | |
4206 | unsigned long gp_sp_offset; /* Offset from new sp to store gp regs. */ | |
4207 | unsigned long fp_sp_offset; /* Offset from new sp to store fp regs. */ | |
4208 | int initialized; /* Nonzero if frame size already calculated. */ | |
4209 | }; | |
4210 | ||
c6aa9ce1 | 4211 | /* Current frame information calculated by sparc_flat_compute_frame_size. */ |
c819be5b JW |
4212 | struct sparc_frame_info current_frame_info; |
4213 | ||
4214 | /* Zero structure to initialize current_frame_info. */ | |
4215 | struct sparc_frame_info zero_frame_info; | |
4216 | ||
4217 | /* Tell prologue and epilogue if register REGNO should be saved / restored. */ | |
4218 | ||
4219 | #define MUST_SAVE_REGISTER(regno) \ | |
4220 | ((regs_ever_live[regno] && !call_used_regs[regno]) \ | |
4221 | || (regno == FRAME_POINTER_REGNUM && frame_pointer_needed) \ | |
4222 | || (regno == 15 && regs_ever_live[15])) | |
4223 | ||
4224 | /* Return the bytes needed to compute the frame pointer from the current | |
4225 | stack pointer. */ | |
4226 | ||
4227 | unsigned long | |
c6aa9ce1 | 4228 | sparc_flat_compute_frame_size (size) |
c819be5b JW |
4229 | int size; /* # of var. bytes allocated. */ |
4230 | { | |
4231 | int regno; | |
4232 | unsigned long total_size; /* # bytes that the entire frame takes up. */ | |
4233 | unsigned long var_size; /* # bytes that variables take up. */ | |
4234 | unsigned long args_size; /* # bytes that outgoing arguments take up. */ | |
4235 | unsigned long extra_size; /* # extra bytes. */ | |
4236 | unsigned int gp_reg_size; /* # bytes needed to store gp regs. */ | |
4237 | unsigned int fp_reg_size; /* # bytes needed to store fp regs. */ | |
4238 | unsigned long mask; /* Mask of saved gp registers. */ | |
4239 | unsigned long fmask; /* Mask of saved fp registers. */ | |
4240 | ||
4241 | /* This is the size of the 16 word reg save area, 1 word struct addr | |
4242 | area, and 4 word fp/alu register copy area. */ | |
61a55e8b | 4243 | /* ??? Is the stack bias taken into account here? */ |
c819be5b JW |
4244 | extra_size = -STARTING_FRAME_OFFSET + FIRST_PARM_OFFSET(0); |
4245 | var_size = size; | |
4246 | /* Also include the size needed for the 6 parameter registers. */ | |
4247 | args_size = current_function_outgoing_args_size + 24; | |
4248 | total_size = var_size + args_size + extra_size; | |
4249 | gp_reg_size = 0; | |
4250 | fp_reg_size = 0; | |
4251 | mask = 0; | |
4252 | fmask = 0; | |
4253 | ||
4254 | /* Calculate space needed for gp registers. */ | |
4255 | for (regno = 1; regno <= 31; regno++) | |
4256 | { | |
4257 | if (MUST_SAVE_REGISTER (regno)) | |
4258 | { | |
4259 | if ((regno & 0x1) == 0 && MUST_SAVE_REGISTER (regno+1)) | |
4260 | { | |
4261 | if (gp_reg_size % 8 != 0) | |
4262 | gp_reg_size += UNITS_PER_WORD; | |
4263 | gp_reg_size += 2 * UNITS_PER_WORD; | |
4264 | mask |= 3 << regno; | |
4265 | regno++; | |
4266 | } | |
4267 | else | |
4268 | { | |
4269 | gp_reg_size += UNITS_PER_WORD; | |
4270 | mask |= 1 << regno; | |
4271 | } | |
4272 | } | |
4273 | } | |
4274 | /* Add extra word in case we have to align the space to a double word | |
4275 | boundary. */ | |
4276 | if (gp_reg_size != 0) | |
4277 | gp_reg_size += UNITS_PER_WORD; | |
4278 | ||
4279 | /* Calculate space needed for fp registers. */ | |
4280 | for (regno = 32; regno <= 63; regno++) | |
4281 | { | |
4282 | if (regs_ever_live[regno] && !call_used_regs[regno]) | |
4283 | { | |
4284 | fp_reg_size += UNITS_PER_WORD; | |
4285 | fmask |= 1 << (regno - 32); | |
4286 | } | |
4287 | } | |
4288 | ||
4289 | total_size += gp_reg_size + fp_reg_size; | |
4290 | ||
4291 | if (total_size == extra_size) | |
4292 | total_size = extra_size = 0; | |
4293 | ||
4294 | total_size = SPARC_STACK_ALIGN (total_size); | |
4295 | ||
4296 | /* Save other computed information. */ | |
4297 | current_frame_info.total_size = total_size; | |
4298 | current_frame_info.var_size = var_size; | |
4299 | current_frame_info.args_size = args_size; | |
4300 | current_frame_info.extra_size = extra_size; | |
4301 | current_frame_info.gp_reg_size = gp_reg_size; | |
4302 | current_frame_info.fp_reg_size = fp_reg_size; | |
4303 | current_frame_info.mask = mask; | |
4304 | current_frame_info.fmask = fmask; | |
4305 | current_frame_info.initialized = reload_completed; | |
4306 | ||
4307 | if (mask) | |
4308 | { | |
4309 | unsigned long offset = args_size; | |
4310 | if (extra_size) | |
4311 | offset += FIRST_PARM_OFFSET(0); | |
4312 | current_frame_info.gp_sp_offset = offset; | |
4313 | } | |
4314 | ||
4315 | if (fmask) | |
4316 | { | |
4317 | unsigned long offset = args_size + gp_reg_size; | |
4318 | if (extra_size) | |
4319 | offset += FIRST_PARM_OFFSET(0); | |
4320 | current_frame_info.fp_sp_offset = offset; | |
4321 | } | |
4322 | ||
4323 | /* Ok, we're done. */ | |
4324 | return total_size; | |
4325 | } | |
4326 | \f | |
4327 | /* Common code to save/restore registers. */ | |
4328 | ||
4329 | void | |
c6aa9ce1 | 4330 | sparc_flat_save_restore (file, word_op, doubleword_op) |
c819be5b JW |
4331 | FILE *file; /* Stream to write to. */ |
4332 | char *word_op; /* Operation to do for one word. */ | |
4333 | char *doubleword_op; /* Operation to do for doubleword. */ | |
4334 | { | |
4335 | int regno; | |
4336 | unsigned long mask = current_frame_info.mask; | |
4337 | unsigned long fmask = current_frame_info.fmask; | |
4338 | unsigned long gp_offset; | |
4339 | unsigned long fp_offset; | |
4340 | unsigned long max_offset; | |
4341 | char *base_reg; | |
4342 | ||
4343 | if (mask == 0 && fmask == 0) | |
4344 | return; | |
4345 | ||
4346 | base_reg = reg_names[STACK_POINTER_REGNUM]; | |
4347 | gp_offset = current_frame_info.gp_sp_offset; | |
4348 | fp_offset = current_frame_info.fp_sp_offset; | |
4349 | max_offset = (gp_offset > fp_offset) ? gp_offset : fp_offset; | |
4350 | ||
4351 | /* Deal with calling functions with a large structure. */ | |
4352 | if (max_offset >= 4096) | |
4353 | { | |
4354 | char *temp = "%g2"; | |
4355 | fprintf (file, "\tset %ld,%s\n", max_offset, temp); | |
4356 | fprintf (file, "\tadd %s,%s,%s\n", temp, base_reg, temp); | |
4357 | base_reg = temp; | |
4358 | gp_offset = max_offset - gp_offset; | |
4359 | fp_offset = max_offset - fp_offset; | |
4360 | } | |
4361 | ||
4362 | /* Save registers starting from high to low. The debuggers prefer | |
4363 | at least the return register be stored at func+4, and also it | |
4364 | allows us not to need a nop in the epilog if at least one | |
4365 | register is reloaded in addition to return address. */ | |
4366 | ||
4367 | if (mask || frame_pointer_needed) | |
4368 | { | |
4369 | for (regno = 1; regno <= 31; regno++) | |
4370 | { | |
4371 | if ((mask & (1L << regno)) != 0 | |
4372 | || (regno == FRAME_POINTER_REGNUM && frame_pointer_needed)) | |
4373 | { | |
ea961c18 | 4374 | if ((regno & 0x1) == 0 && ((mask & (1L << (regno+1))) != 0)) |
c819be5b JW |
4375 | { |
4376 | if (gp_offset % 8 != 0) | |
4377 | gp_offset += UNITS_PER_WORD; | |
4378 | ||
4379 | if (word_op[0] == 's') | |
4380 | fprintf (file, "\t%s %s,[%s+%d]\n", | |
4381 | doubleword_op, reg_names[regno], | |
4382 | base_reg, gp_offset); | |
4383 | else | |
4384 | fprintf (file, "\t%s [%s+%d],%s\n", | |
4385 | doubleword_op, base_reg, gp_offset, | |
4386 | reg_names[regno]); | |
4387 | ||
4388 | gp_offset += 2 * UNITS_PER_WORD; | |
4389 | regno++; | |
4390 | } | |
4391 | else | |
4392 | { | |
4393 | if (word_op[0] == 's') | |
4394 | fprintf (file, "\t%s %s,[%s+%d]\n", | |
4395 | word_op, reg_names[regno], | |
4396 | base_reg, gp_offset); | |
4397 | else | |
4398 | fprintf (file, "\t%s [%s+%d],%s\n", | |
4399 | word_op, base_reg, gp_offset, reg_names[regno]); | |
4400 | ||
4401 | gp_offset += UNITS_PER_WORD; | |
4402 | } | |
4403 | } | |
4404 | } | |
4405 | } | |
4406 | ||
4407 | if (fmask) | |
4408 | { | |
4409 | for (regno = 32; regno <= 63; regno++) | |
4410 | { | |
4411 | if ((fmask & (1L << (regno - 32))) != 0) | |
4412 | { | |
4413 | if (word_op[0] == 's') | |
4414 | fprintf (file, "\t%s %s,[%s+%d]\n", | |
4415 | word_op, reg_names[regno], | |
4416 | base_reg, gp_offset); | |
4417 | else | |
4418 | fprintf (file, "\t%s [%s+%d],%s\n", | |
4419 | word_op, base_reg, gp_offset, reg_names[regno]); | |
4420 | ||
4421 | fp_offset += UNITS_PER_WORD; | |
4422 | } | |
4423 | } | |
4424 | } | |
4425 | } | |
4426 | \f | |
4427 | /* Set up the stack and frame (if desired) for the function. */ | |
4428 | ||
4429 | void | |
c6aa9ce1 | 4430 | sparc_flat_output_function_prologue (file, size) |
c819be5b JW |
4431 | FILE *file; |
4432 | int size; | |
4433 | { | |
c819be5b JW |
4434 | int tsize; |
4435 | char *sp_str = reg_names[STACK_POINTER_REGNUM]; | |
a07c1915 | 4436 | |
c6aa9ce1 | 4437 | /* This is only for the human reader. */ |
c819be5b JW |
4438 | fprintf (file, "\t!#PROLOGUE# 0\n"); |
4439 | ||
4440 | size = SPARC_STACK_ALIGN (size); | |
4441 | tsize = (! current_frame_info.initialized | |
c6aa9ce1 | 4442 | ? sparc_flat_compute_frame_size (size) |
c819be5b JW |
4443 | : current_frame_info.total_size); |
4444 | ||
4445 | if (tsize > 0) | |
4446 | { | |
4447 | if (tsize <= 4095) | |
4448 | fprintf (file, | |
4449 | "\tsub %s,%d,%s\t\t!# vars= %d, regs= %d/%d, args = %d, extra= %d\n", | |
4450 | sp_str, tsize, sp_str, current_frame_info.var_size, | |
4451 | current_frame_info.gp_reg_size / 4, | |
4452 | current_frame_info.fp_reg_size / 8, | |
4453 | current_function_outgoing_args_size, | |
4454 | current_frame_info.extra_size); | |
4455 | else | |
4456 | fprintf (file, | |
4457 | "\tset %d,%s\n\tsub\t%s,%s,%s\t\t!# vars= %d, regs= %d/%d, args = %d, sfo= %d\n", | |
4458 | tsize, "%g1", sp_str, "%g1", | |
4459 | sp_str, current_frame_info.var_size, | |
4460 | current_frame_info.gp_reg_size / 4, | |
4461 | current_frame_info.fp_reg_size / 8, | |
4462 | current_function_outgoing_args_size, | |
4463 | current_frame_info.extra_size); | |
4464 | } | |
4465 | ||
c6aa9ce1 | 4466 | sparc_flat_save_restore (file, "st", "std"); |
c819be5b JW |
4467 | |
4468 | if (frame_pointer_needed) | |
4469 | { | |
c6aa9ce1 DE |
4470 | char *fp_str = reg_names[FRAME_POINTER_REGNUM]; |
4471 | ||
c819be5b JW |
4472 | if (tsize <= 4095) |
4473 | fprintf (file, "\tadd %s,%d,%s\t!# set up frame pointer\n", sp_str, | |
c6aa9ce1 | 4474 | tsize, fp_str); |
c819be5b JW |
4475 | else |
4476 | fprintf (file, "\tadd %s,%s,%s\t!# set up frame pointer\n", sp_str, | |
c6aa9ce1 | 4477 | "%g1", fp_str); |
c819be5b | 4478 | } |
c6aa9ce1 DE |
4479 | |
4480 | fprintf (file, "\t!#PROLOGUE# 1\n"); | |
c819be5b JW |
4481 | } |
4482 | \f | |
4483 | /* Do any necessary cleanup after a function to restore stack, frame, | |
4484 | and regs. */ | |
4485 | ||
4486 | void | |
c6aa9ce1 | 4487 | sparc_flat_output_function_epilogue (file, size) |
c819be5b JW |
4488 | FILE *file; |
4489 | int size; | |
4490 | { | |
c819be5b JW |
4491 | int tsize; |
4492 | char *sp_str = reg_names[STACK_POINTER_REGNUM]; | |
4493 | char *t1_str = "%g1"; | |
4494 | rtx epilogue_delay = current_function_epilogue_delay_list; | |
4495 | int noepilogue = FALSE; | |
c819be5b | 4496 | |
c6aa9ce1 DE |
4497 | /* This is only for the human reader. */ |
4498 | fprintf (file, "\t!#EPILOGUE#\n"); | |
4499 | ||
c819be5b JW |
4500 | /* The epilogue does not depend on any registers, but the stack |
4501 | registers, so we assume that if we have 1 pending nop, it can be | |
4502 | ignored, and 2 it must be filled (2 nops occur for integer | |
4503 | multiply and divide). */ | |
4504 | ||
4505 | size = SPARC_STACK_ALIGN (size); | |
4506 | tsize = (!current_frame_info.initialized | |
c6aa9ce1 | 4507 | ? sparc_flat_compute_frame_size (size) |
c819be5b JW |
4508 | : current_frame_info.total_size); |
4509 | ||
4510 | if (tsize == 0 && epilogue_delay == 0) | |
4511 | { | |
4512 | rtx insn = get_last_insn (); | |
4513 | ||
4514 | /* If the last insn was a BARRIER, we don't have to write any code | |
4515 | because a jump (aka return) was put there. */ | |
4516 | if (GET_CODE (insn) == NOTE) | |
4517 | insn = prev_nonnote_insn (insn); | |
4518 | if (insn && GET_CODE (insn) == BARRIER) | |
4519 | noepilogue = TRUE; | |
4520 | } | |
4521 | ||
4522 | if (!noepilogue) | |
4523 | { | |
4524 | /* In the reload sequence, we don't need to fill the load delay | |
4525 | slots for most of the loads, also see if we can fill the final | |
4526 | delay slot if not otherwise filled by the reload sequence. */ | |
4527 | ||
4528 | if (tsize > 4095) | |
4529 | fprintf (file, "\tset %d,%s\n", tsize, t1_str); | |
4530 | ||
4531 | if (frame_pointer_needed) | |
4532 | { | |
4533 | char *fp_str = reg_names[FRAME_POINTER_REGNUM]; | |
4534 | if (tsize > 4095) | |
4535 | fprintf (file,"\tsub %s,%s,%s\t\t!# sp not trusted here\n", | |
4536 | fp_str, t1_str, sp_str); | |
4537 | else | |
4538 | fprintf (file,"\tsub %s,%d,%s\t\t!# sp not trusted here\n", | |
4539 | fp_str, tsize, sp_str); | |
4540 | } | |
4541 | ||
c6aa9ce1 | 4542 | sparc_flat_save_restore (file, "ld", "ldd"); |
c819be5b | 4543 | |
c819be5b JW |
4544 | if (current_function_returns_struct) |
4545 | fprintf (file, "\tjmp %%o7+12\n"); | |
4546 | else | |
4547 | fprintf (file, "\tretl\n"); | |
4548 | ||
4549 | /* If the only register saved is the return address, we need a | |
4550 | nop, unless we have an instruction to put into it. Otherwise | |
4551 | we don't since reloading multiple registers doesn't reference | |
4552 | the register being loaded. */ | |
4553 | ||
4554 | if (epilogue_delay) | |
4555 | { | |
4556 | if (tsize) | |
4557 | abort (); | |
4558 | final_scan_insn (XEXP (epilogue_delay, 0), file, 1, -2, 1); | |
4559 | } | |
4560 | ||
4561 | else if (tsize > 4095) | |
4562 | fprintf (file, "\tadd %s,%s,%s\n", sp_str, t1_str, sp_str); | |
4563 | ||
4564 | else if (tsize > 0) | |
4565 | fprintf (file, "\tadd %s,%d,%s\n", sp_str, tsize, sp_str); | |
4566 | ||
4567 | else | |
4568 | fprintf (file, "\tnop\n"); | |
4569 | } | |
4570 | ||
4571 | /* Reset state info for each function. */ | |
4572 | current_frame_info = zero_frame_info; | |
4573 | } | |
4574 | \f | |
4575 | /* Define the number of delay slots needed for the function epilogue. | |
4576 | ||
4577 | On the sparc, we need a slot if either no stack has been allocated, | |
4578 | or the only register saved is the return register. */ | |
4579 | ||
4580 | int | |
c6aa9ce1 | 4581 | sparc_flat_epilogue_delay_slots () |
c819be5b JW |
4582 | { |
4583 | if (!current_frame_info.initialized) | |
c6aa9ce1 | 4584 | (void) sparc_flat_compute_frame_size (get_frame_size ()); |
c819be5b JW |
4585 | |
4586 | if (current_frame_info.total_size == 0) | |
4587 | return 1; | |
4588 | ||
c819be5b JW |
4589 | return 0; |
4590 | } | |
4591 | ||
4592 | /* Return true is TRIAL is a valid insn for the epilogue delay slot. | |
4593 | Any single length instruction which doesn't reference the stack or frame | |
4594 | pointer is OK. */ | |
4595 | ||
4596 | int | |
c6aa9ce1 | 4597 | sparc_flat_eligible_for_epilogue_delay (trial, slot) |
c819be5b JW |
4598 | rtx trial; |
4599 | int slot; | |
4600 | { | |
4601 | if (get_attr_length (trial) == 1 | |
4602 | && ! reg_mentioned_p (stack_pointer_rtx, PATTERN (trial)) | |
4603 | && ! reg_mentioned_p (frame_pointer_rtx, PATTERN (trial))) | |
4604 | return 1; | |
4605 | return 0; | |
4606 | } | |
dbb54862 JW |
4607 | \f |
4608 | /* Adjust the cost of a scheduling dependency. Return the new cost of | |
4609 | a dependency LINK or INSN on DEP_INSN. COST is the current cost. */ | |
4610 | ||
4611 | int | |
4612 | supersparc_adjust_cost (insn, link, dep_insn, cost) | |
4613 | rtx insn; | |
4614 | rtx link; | |
4615 | rtx dep_insn; | |
4616 | int cost; | |
4617 | { | |
4618 | enum attr_type insn_type; | |
4619 | ||
4620 | if (! recog_memoized (insn)) | |
4621 | return 0; | |
4622 | ||
4623 | insn_type = get_attr_type (insn); | |
4624 | ||
4625 | if (REG_NOTE_KIND (link) == 0) | |
4626 | { | |
4627 | /* Data dependency; DEP_INSN writes a register that INSN reads some | |
4628 | cycles later. */ | |
4629 | ||
4630 | /* if a load, then the dependence must be on the memory address; | |
4631 | add an extra 'cycle'. Note that the cost could be two cycles | |
4632 | if the reg was written late in an instruction group; we can't tell | |
4633 | here. */ | |
4634 | if (insn_type == TYPE_LOAD || insn_type == TYPE_FPLOAD) | |
4635 | return cost + 3; | |
4636 | ||
4637 | /* Get the delay only if the address of the store is the dependence. */ | |
4638 | if (insn_type == TYPE_STORE || insn_type == TYPE_FPSTORE) | |
4639 | { | |
4640 | rtx pat = PATTERN(insn); | |
4641 | rtx dep_pat = PATTERN (dep_insn); | |
4642 | ||
4643 | if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET) | |
4644 | return cost; /* This shouldn't happen! */ | |
4645 | ||
4646 | /* The dependency between the two instructions was on the data that | |
4647 | is being stored. Assume that this implies that the address of the | |
4648 | store is not dependent. */ | |
4649 | if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat))) | |
4650 | return cost; | |
4651 | ||
4652 | return cost + 3; /* An approximation. */ | |
4653 | } | |
4654 | ||
4655 | /* A shift instruction cannot receive its data from an instruction | |
4656 | in the same cycle; add a one cycle penalty. */ | |
4657 | if (insn_type == TYPE_SHIFT) | |
4658 | return cost + 3; /* Split before cascade into shift. */ | |
4659 | } | |
4660 | else | |
4661 | { | |
4662 | /* Anti- or output- dependency; DEP_INSN reads/writes a register that | |
4663 | INSN writes some cycles later. */ | |
4664 | ||
4665 | /* These are only significant for the fpu unit; writing a fp reg before | |
4666 | the fpu has finished with it stalls the processor. */ | |
4667 | ||
4668 | /* Reusing an integer register causes no problems. */ | |
4669 | if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT) | |
4670 | return 0; | |
4671 | } | |
4672 | ||
4673 | return cost; | |
4674 | } |