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ab835497 | 1 | /* Subroutines for insn-output.c for Sun SPARC. |
4592bdcb JL |
2 | Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998, |
3 | 1999, 2000 Free Software Foundation, Inc. | |
ab835497 | 4 | Contributed by Michael Tiemann (tiemann@cygnus.com) |
61a55e8b DE |
5 | 64 bit SPARC V9 support by Michael Tiemann, Jim Wilson, and Doug Evans, |
6 | at Cygnus Support. | |
ab835497 RK |
7 | |
8 | This file is part of GNU CC. | |
9 | ||
10 | GNU CC is free software; you can redistribute it and/or modify | |
11 | it under the terms of the GNU General Public License as published by | |
12 | the Free Software Foundation; either version 2, or (at your option) | |
13 | any later version. | |
14 | ||
15 | GNU CC is distributed in the hope that it will be useful, | |
16 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | GNU General Public License for more details. | |
19 | ||
20 | You should have received a copy of the GNU General Public License | |
21 | along with GNU CC; see the file COPYING. If not, write to | |
c15c9075 RK |
22 | the Free Software Foundation, 59 Temple Place - Suite 330, |
23 | Boston, MA 02111-1307, USA. */ | |
ab835497 | 24 | |
ab835497 | 25 | #include "config.h" |
284d86e9 | 26 | #include "system.h" |
210aa14a | 27 | #include "tree.h" |
ab835497 RK |
28 | #include "rtl.h" |
29 | #include "regs.h" | |
30 | #include "hard-reg-set.h" | |
31 | #include "real.h" | |
32 | #include "insn-config.h" | |
33 | #include "conditions.h" | |
34 | #include "insn-flags.h" | |
35 | #include "output.h" | |
36 | #include "insn-attr.h" | |
37 | #include "flags.h" | |
49ad7cfa | 38 | #include "function.h" |
ab835497 RK |
39 | #include "expr.h" |
40 | #include "recog.h" | |
487a6e06 | 41 | #include "toplev.h" |
d07d525a | 42 | #include "ggc.h" |
b1474bb7 | 43 | #include "tm_p.h" |
ab835497 | 44 | |
61a55e8b DE |
45 | /* 1 if the caller has placed an "unimp" insn immediately after the call. |
46 | This is used in v8 code when calling a function that returns a structure. | |
06b967f9 RK |
47 | v9 doesn't have this. Be careful to have this test be the same as that |
48 | used on the call. */ | |
49 | ||
50 | #define SKIP_CALLERS_UNIMP_P \ | |
51 | (!TARGET_ARCH64 && current_function_returns_struct \ | |
52 | && ! integer_zerop (DECL_SIZE (DECL_RESULT (current_function_decl))) \ | |
53 | && (TREE_CODE (DECL_SIZE (DECL_RESULT (current_function_decl))) \ | |
54 | == INTEGER_CST)) | |
61a55e8b | 55 | |
ab835497 RK |
56 | /* Global variables for machine-dependent things. */ |
57 | ||
61a55e8b DE |
58 | /* Size of frame. Need to know this to emit return insns from leaf procedures. |
59 | ACTUAL_FSIZE is set by compute_frame_size() which is called during the | |
60 | reload pass. This is important as the value is later used in insn | |
61 | scheduling (to see what can go in a delay slot). | |
62 | APPARENT_FSIZE is the size of the stack less the register save area and less | |
63 | the outgoing argument area. It is used when saving call preserved regs. */ | |
64 | static int apparent_fsize; | |
65 | static int actual_fsize; | |
66 | ||
e48addee JJ |
67 | /* Number of live general or floating point registers needed to be saved |
68 | (as 4-byte quantities). This is only done if TARGET_EPILOGUE. */ | |
69 | static int num_gfregs; | |
70 | ||
ab835497 RK |
71 | /* Save the operands last given to a compare for use when we |
72 | generate a scc or bcc insn. */ | |
73 | ||
74 | rtx sparc_compare_op0, sparc_compare_op1; | |
75 | ||
76 | /* We may need an epilogue if we spill too many registers. | |
77 | If this is non-zero, then we branch here for the epilogue. */ | |
78 | static rtx leaf_label; | |
79 | ||
80 | #ifdef LEAF_REGISTERS | |
81 | ||
82 | /* Vector to say how input registers are mapped to output | |
83 | registers. FRAME_POINTER_REGNUM cannot be remapped by | |
84 | this function to eliminate it. You must use -fomit-frame-pointer | |
85 | to get that. */ | |
86 | char leaf_reg_remap[] = | |
87 | { 0, 1, 2, 3, 4, 5, 6, 7, | |
88 | -1, -1, -1, -1, -1, -1, 14, -1, | |
89 | -1, -1, -1, -1, -1, -1, -1, -1, | |
90 | 8, 9, 10, 11, 12, 13, -1, 15, | |
91 | ||
92 | 32, 33, 34, 35, 36, 37, 38, 39, | |
93 | 40, 41, 42, 43, 44, 45, 46, 47, | |
94 | 48, 49, 50, 51, 52, 53, 54, 55, | |
61a55e8b DE |
95 | 56, 57, 58, 59, 60, 61, 62, 63, |
96 | 64, 65, 66, 67, 68, 69, 70, 71, | |
97 | 72, 73, 74, 75, 76, 77, 78, 79, | |
98 | 80, 81, 82, 83, 84, 85, 86, 87, | |
99 | 88, 89, 90, 91, 92, 93, 94, 95, | |
c4ce6853 | 100 | 96, 97, 98, 99, 100}; |
ab835497 | 101 | |
7d167afd JJ |
102 | /* Vector, indexed by hard register number, which contains 1 |
103 | for a register that is allowable in a candidate for leaf | |
104 | function treatment. */ | |
105 | char sparc_leaf_regs[] = | |
106 | { 1, 1, 1, 1, 1, 1, 1, 1, | |
107 | 0, 0, 0, 0, 0, 0, 1, 0, | |
108 | 0, 0, 0, 0, 0, 0, 0, 0, | |
109 | 1, 1, 1, 1, 1, 1, 0, 1, | |
110 | 1, 1, 1, 1, 1, 1, 1, 1, | |
111 | 1, 1, 1, 1, 1, 1, 1, 1, | |
112 | 1, 1, 1, 1, 1, 1, 1, 1, | |
113 | 1, 1, 1, 1, 1, 1, 1, 1, | |
114 | 1, 1, 1, 1, 1, 1, 1, 1, | |
115 | 1, 1, 1, 1, 1, 1, 1, 1, | |
116 | 1, 1, 1, 1, 1, 1, 1, 1, | |
117 | 1, 1, 1, 1, 1, 1, 1, 1, | |
118 | 1, 1, 1, 1, 1}; | |
119 | ||
6a4bb1fa | 120 | #endif |
ab835497 | 121 | |
ab835497 RK |
122 | /* Name of where we pretend to think the frame pointer points. |
123 | Normally, this is "%fp", but if we are in a leaf procedure, | |
61a55e8b DE |
124 | this is "%sp+something". We record "something" separately as it may be |
125 | too big for reg+constant addressing. */ | |
126 | ||
3bb5de61 | 127 | static const char *frame_base_name; |
61a55e8b | 128 | static int frame_base_offset; |
ab835497 | 129 | |
f6da8bc3 KG |
130 | static rtx pic_setup_code PARAMS ((void)); |
131 | static void sparc_init_modes PARAMS ((void)); | |
132 | static int save_regs PARAMS ((FILE *, int, int, const char *, | |
c85f7c16 | 133 | int, int, int)); |
f6da8bc3 KG |
134 | static int restore_regs PARAMS ((FILE *, int, int, const char *, int, int)); |
135 | static void build_big_number PARAMS ((FILE *, int, const char *)); | |
136 | static int function_arg_slotno PARAMS ((const CUMULATIVE_ARGS *, | |
c85f7c16 JL |
137 | enum machine_mode, tree, int, int, |
138 | int *, int *)); | |
8947065c | 139 | |
f6da8bc3 KG |
140 | static int supersparc_adjust_cost PARAMS ((rtx, rtx, rtx, int)); |
141 | static int hypersparc_adjust_cost PARAMS ((rtx, rtx, rtx, int)); | |
142 | static int ultrasparc_adjust_cost PARAMS ((rtx, rtx, rtx, int)); | |
143 | ||
144 | static void sparc_output_addr_vec PARAMS ((rtx)); | |
145 | static void sparc_output_addr_diff_vec PARAMS ((rtx)); | |
146 | static void sparc_output_deferred_case_vectors PARAMS ((void)); | |
147 | static void sparc_add_gc_roots PARAMS ((void)); | |
148 | static void mark_ultrasparc_pipeline_state PARAMS ((void *)); | |
149 | static int check_return_regs PARAMS ((rtx)); | |
150 | static int epilogue_renumber PARAMS ((rtx *, int)); | |
151 | static int ultra_cmove_results_ready_p PARAMS ((rtx)); | |
152 | static int ultra_fpmode_conflict_exists PARAMS ((enum machine_mode)); | |
153 | static rtx *ultra_find_type PARAMS ((int, rtx *, int)); | |
154 | static void ultra_build_types_avail PARAMS ((rtx *, int)); | |
155 | static void ultra_flush_pipeline PARAMS ((void)); | |
156 | static void ultra_rescan_pipeline_state PARAMS ((rtx *, int)); | |
157 | static int set_extends PARAMS ((rtx, rtx)); | |
61a55e8b DE |
158 | \f |
159 | /* Option handling. */ | |
160 | ||
a0a301fc | 161 | /* Code model option as passed by user. */ |
3bb5de61 | 162 | const char *sparc_cmodel_string; |
a0a301fc DE |
163 | /* Parsed value. */ |
164 | enum cmodel sparc_cmodel; | |
165 | ||
1cb36a98 RH |
166 | char sparc_hard_reg_printed[8]; |
167 | ||
16956f6e DE |
168 | struct sparc_cpu_select sparc_select[] = |
169 | { | |
170 | /* switch name, tune arch */ | |
171 | { (char *)0, "default", 1, 1 }, | |
172 | { (char *)0, "-mcpu=", 1, 1 }, | |
173 | { (char *)0, "-mtune=", 1, 0 }, | |
db3d4438 | 174 | { 0, 0, 0, 0 } |
16956f6e | 175 | }; |
733f53f5 | 176 | |
16956f6e DE |
177 | /* CPU type. This is set from TARGET_CPU_DEFAULT and -m{cpu,tune}=xxx. */ |
178 | enum processor_type sparc_cpu; | |
733f53f5 | 179 | |
61a55e8b DE |
180 | /* Validate and override various options, and do some machine dependent |
181 | initialization. */ | |
182 | ||
183 | void | |
184 | sparc_override_options () | |
185 | { | |
a0a301fc | 186 | static struct code_model { |
3bb5de61 | 187 | const char *name; |
a0a301fc DE |
188 | int value; |
189 | } cmodels[] = { | |
190 | { "32", CM_32 }, | |
191 | { "medlow", CM_MEDLOW }, | |
192 | { "medmid", CM_MEDMID }, | |
193 | { "medany", CM_MEDANY }, | |
194 | { "embmedany", CM_EMBMEDANY }, | |
195 | { 0, 0 } | |
196 | }; | |
197 | struct code_model *cmodel; | |
16956f6e | 198 | /* Map TARGET_CPU_DEFAULT to value for -m{arch,tune}=. */ |
733f53f5 DE |
199 | static struct cpu_default { |
200 | int cpu; | |
3bb5de61 | 201 | const char *name; |
733f53f5 | 202 | } cpu_default[] = { |
a0a301fc | 203 | /* There must be one entry here for each TARGET_CPU value. */ |
16956f6e | 204 | { TARGET_CPU_sparc, "cypress" }, |
3592ea0d | 205 | { TARGET_CPU_sparclet, "tsc701" }, |
16956f6e | 206 | { TARGET_CPU_sparclite, "f930" }, |
a0a301fc | 207 | { TARGET_CPU_v8, "v8" }, |
8947065c RH |
208 | { TARGET_CPU_hypersparc, "hypersparc" }, |
209 | { TARGET_CPU_sparclite86x, "sparclite86x" }, | |
a0a301fc DE |
210 | { TARGET_CPU_supersparc, "supersparc" }, |
211 | { TARGET_CPU_v9, "v9" }, | |
ba542005 | 212 | { TARGET_CPU_ultrasparc, "ultrasparc" }, |
db3d4438 | 213 | { 0, 0 } |
733f53f5 | 214 | }; |
16956f6e DE |
215 | struct cpu_default *def; |
216 | /* Table of values for -m{cpu,tune}=. */ | |
733f53f5 | 217 | static struct cpu_table { |
3bb5de61 | 218 | const char *name; |
16956f6e | 219 | enum processor_type processor; |
733f53f5 DE |
220 | int disable; |
221 | int enable; | |
222 | } cpu_table[] = { | |
16956f6e DE |
223 | { "v7", PROCESSOR_V7, MASK_ISA, 0 }, |
224 | { "cypress", PROCESSOR_CYPRESS, MASK_ISA, 0 }, | |
225 | { "v8", PROCESSOR_V8, MASK_ISA, MASK_V8 }, | |
733f53f5 | 226 | /* TI TMS390Z55 supersparc */ |
16956f6e DE |
227 | { "supersparc", PROCESSOR_SUPERSPARC, MASK_ISA, MASK_V8 }, |
228 | { "sparclite", PROCESSOR_SPARCLITE, MASK_ISA, MASK_SPARCLITE }, | |
733f53f5 DE |
229 | /* The Fujitsu MB86930 is the original sparclite chip, with no fpu. |
230 | The Fujitsu MB86934 is the recent sparclite chip, with an fpu. */ | |
16956f6e DE |
231 | { "f930", PROCESSOR_F930, MASK_ISA|MASK_FPU, MASK_SPARCLITE }, |
232 | { "f934", PROCESSOR_F934, MASK_ISA, MASK_SPARCLITE|MASK_FPU }, | |
8947065c | 233 | { "hypersparc", PROCESSOR_HYPERSPARC, MASK_ISA, MASK_V8|MASK_FPU }, |
d3ec6b06 VM |
234 | { "sparclite86x", PROCESSOR_SPARCLITE86X, MASK_ISA|MASK_FPU, |
235 | MASK_SPARCLITE }, | |
16956f6e | 236 | { "sparclet", PROCESSOR_SPARCLET, MASK_ISA, MASK_SPARCLET }, |
733f53f5 | 237 | /* TEMIC sparclet */ |
3592ea0d | 238 | { "tsc701", PROCESSOR_TSC701, MASK_ISA, MASK_SPARCLET }, |
16956f6e | 239 | { "v9", PROCESSOR_V9, MASK_ISA, MASK_V9 }, |
5cb01b65 JJ |
240 | /* TI ultrasparc I, II, IIi */ |
241 | { "ultrasparc", PROCESSOR_ULTRASPARC, MASK_ISA, MASK_V9 | |
242 | /* Although insns using %y are deprecated, it is a clear win on current | |
243 | ultrasparcs. */ | |
244 | |MASK_DEPRECATED_V8_INSNS }, | |
db3d4438 | 245 | { 0, 0, 0, 0 } |
733f53f5 | 246 | }; |
16956f6e DE |
247 | struct cpu_table *cpu; |
248 | struct sparc_cpu_select *sel; | |
a0a301fc | 249 | int fpu; |
345a6161 | 250 | |
a0a301fc DE |
251 | #ifndef SPARC_BI_ARCH |
252 | /* Check for unsupported architecture size. */ | |
253 | if (! TARGET_64BIT != DEFAULT_ARCH32_P) | |
254 | { | |
255 | error ("%s is not supported by this configuration", | |
256 | DEFAULT_ARCH32_P ? "-m64" : "-m32"); | |
257 | } | |
258 | #endif | |
259 | ||
345a6161 DM |
260 | /* At the moment we don't allow different pointer size and architecture */ |
261 | if (! TARGET_64BIT != ! TARGET_PTR64) | |
262 | { | |
263 | error ("-mptr%d not allowed on -m%d", | |
264 | TARGET_PTR64 ? 64 : 32, TARGET_64BIT ? 64 : 32); | |
265 | if (TARGET_64BIT) | |
266 | target_flags |= MASK_PTR64; | |
267 | else | |
268 | target_flags &= ~MASK_PTR64; | |
269 | } | |
270 | ||
4710d3eb JJ |
271 | /* We force all 64bit archs to use 128 bit long double */ |
272 | if (TARGET_64BIT && ! TARGET_LONG_DOUBLE_128) | |
273 | { | |
274 | error ("-mlong-double-64 not allowed with -m64"); | |
275 | target_flags |= MASK_LONG_DOUBLE_128; | |
276 | } | |
277 | ||
a0a301fc DE |
278 | /* Code model selection. */ |
279 | sparc_cmodel = SPARC_DEFAULT_CMODEL; | |
345a6161 DM |
280 | |
281 | #ifdef SPARC_BI_ARCH | |
282 | if (TARGET_ARCH32) | |
283 | sparc_cmodel = CM_32; | |
284 | #endif | |
285 | ||
a0a301fc DE |
286 | if (sparc_cmodel_string != NULL) |
287 | { | |
288 | if (TARGET_ARCH64) | |
289 | { | |
290 | for (cmodel = &cmodels[0]; cmodel->name; cmodel++) | |
291 | if (strcmp (sparc_cmodel_string, cmodel->name) == 0) | |
292 | break; | |
293 | if (cmodel->name == NULL) | |
294 | error ("bad value (%s) for -mcmodel= switch", sparc_cmodel_string); | |
295 | else | |
296 | sparc_cmodel = cmodel->value; | |
297 | } | |
298 | else | |
299 | error ("-mcmodel= is not supported on 32 bit systems"); | |
300 | } | |
16956f6e | 301 | |
a0a301fc | 302 | fpu = TARGET_FPU; /* save current -mfpu status */ |
1f1406b4 | 303 | |
a0a301fc | 304 | /* Set the default CPU. */ |
16956f6e DE |
305 | for (def = &cpu_default[0]; def->name; ++def) |
306 | if (def->cpu == TARGET_CPU_DEFAULT) | |
307 | break; | |
308 | if (! def->name) | |
309 | abort (); | |
310 | sparc_select[0].string = def->name; | |
311 | ||
312 | for (sel = &sparc_select[0]; sel->name; ++sel) | |
61a55e8b | 313 | { |
16956f6e | 314 | if (sel->string) |
733f53f5 | 315 | { |
16956f6e DE |
316 | for (cpu = &cpu_table[0]; cpu->name; ++cpu) |
317 | if (! strcmp (sel->string, cpu->name)) | |
318 | { | |
319 | if (sel->set_tune_p) | |
320 | sparc_cpu = cpu->processor; | |
321 | ||
322 | if (sel->set_arch_p) | |
323 | { | |
324 | target_flags &= ~cpu->disable; | |
325 | target_flags |= cpu->enable; | |
326 | } | |
327 | break; | |
328 | } | |
329 | ||
330 | if (! cpu->name) | |
331 | error ("bad value (%s) for %s switch", sel->string, sel->name); | |
733f53f5 | 332 | } |
61a55e8b | 333 | } |
97da85b7 | 334 | |
1f1406b4 | 335 | /* If -mfpu or -mno-fpu was explicitly used, don't override with |
46cc13b3 RO |
336 | the processor default. Clear MASK_FPU_SET to avoid confusing |
337 | the reverse mapping from switch values to names. */ | |
1f1406b4 | 338 | if (TARGET_FPU_SET) |
46cc13b3 RO |
339 | { |
340 | target_flags = (target_flags & ~MASK_FPU) | fpu; | |
341 | target_flags &= ~MASK_FPU_SET; | |
342 | } | |
1f1406b4 | 343 | |
16956f6e DE |
344 | /* Use the deprecated v8 insns for sparc64 in 32 bit mode. */ |
345 | if (TARGET_V9 && TARGET_ARCH32) | |
733f53f5 | 346 | target_flags |= MASK_DEPRECATED_V8_INSNS; |
61a55e8b | 347 | |
345a6161 DM |
348 | /* V8PLUS requires V9, makes no sense in 64 bit mode. */ |
349 | if (! TARGET_V9 || TARGET_ARCH64) | |
284d86e9 JC |
350 | target_flags &= ~MASK_V8PLUS; |
351 | ||
82d6b402 RH |
352 | /* Don't use stack biasing in 32 bit mode. */ |
353 | if (TARGET_ARCH32) | |
354 | target_flags &= ~MASK_STACK_BIAS; | |
f952a238 JJ |
355 | |
356 | /* Don't allow -mvis if FPU is disabled. */ | |
357 | if (! TARGET_FPU) | |
358 | target_flags &= ~MASK_VIS; | |
82d6b402 | 359 | |
efa3896a GK |
360 | /* Supply a default value for align_functions. */ |
361 | if (align_functions == 0 && sparc_cpu == PROCESSOR_ULTRASPARC) | |
362 | align_functions = 32; | |
bf62bbf1 | 363 | |
82d6b402 RH |
364 | /* Validate PCC_STRUCT_RETURN. */ |
365 | if (flag_pcc_struct_return == DEFAULT_PCC_STRUCT_RETURN) | |
366 | flag_pcc_struct_return = (TARGET_ARCH64 ? 0 : 1); | |
367 | ||
61a55e8b DE |
368 | /* Do various machine dependent initializations. */ |
369 | sparc_init_modes (); | |
2be15d0f RH |
370 | |
371 | if ((profile_flag || profile_block_flag) | |
a330e73b | 372 | && sparc_cmodel != CM_32 && sparc_cmodel != CM_MEDLOW) |
2be15d0f RH |
373 | { |
374 | error ("profiling does not support code models other than medlow"); | |
375 | } | |
d07d525a MM |
376 | |
377 | /* Register global variables with the garbage collector. */ | |
378 | sparc_add_gc_roots (); | |
61a55e8b DE |
379 | } |
380 | \f | |
cd5fb1ee DE |
381 | /* Miscellaneous utilities. */ |
382 | ||
383 | /* Nonzero if CODE, a comparison, is suitable for use in v9 conditional move | |
384 | or branch on register contents instructions. */ | |
385 | ||
386 | int | |
387 | v9_regcmp_p (code) | |
388 | enum rtx_code code; | |
389 | { | |
390 | return (code == EQ || code == NE || code == GE || code == LT | |
391 | || code == LE || code == GT); | |
392 | } | |
bfd6bc60 | 393 | |
cd5fb1ee DE |
394 | \f |
395 | /* Operand constraints. */ | |
396 | ||
ab835497 | 397 | /* Return non-zero only if OP is a register of mode MODE, |
e6c1be7e | 398 | or const0_rtx. */ |
c4ce6853 | 399 | |
ab835497 RK |
400 | int |
401 | reg_or_0_operand (op, mode) | |
402 | rtx op; | |
403 | enum machine_mode mode; | |
404 | { | |
c4ce6853 DE |
405 | if (register_operand (op, mode)) |
406 | return 1; | |
c4ce6853 | 407 | if (op == const0_rtx) |
ab835497 | 408 | return 1; |
5b486ce0 | 409 | if (GET_MODE (op) == VOIDmode && GET_CODE (op) == CONST_DOUBLE |
ab835497 RK |
410 | && CONST_DOUBLE_HIGH (op) == 0 |
411 | && CONST_DOUBLE_LOW (op) == 0) | |
412 | return 1; | |
7ce86678 | 413 | if (fp_zero_operand (op, mode)) |
302484ff | 414 | return 1; |
ab835497 RK |
415 | return 0; |
416 | } | |
417 | ||
302484ff | 418 | /* Nonzero if OP is a floating point value with value 0.0. */ |
c4ce6853 | 419 | |
302484ff | 420 | int |
7ce86678 | 421 | fp_zero_operand (op, mode) |
302484ff | 422 | rtx op; |
7ce86678 | 423 | enum machine_mode mode; |
302484ff | 424 | { |
7ce86678 RH |
425 | if (GET_MODE_CLASS (GET_MODE (op)) != MODE_FLOAT) |
426 | return 0; | |
427 | return op == CONST0_RTX (mode); | |
302484ff JW |
428 | } |
429 | ||
62190128 DM |
430 | /* Nonzero if OP is a floating point constant which can |
431 | be loaded into an integer register using a single | |
432 | sethi instruction. */ | |
433 | ||
434 | int | |
435 | fp_sethi_p (op) | |
436 | rtx op; | |
437 | { | |
438 | if (GET_CODE (op) == CONST_DOUBLE) | |
439 | { | |
440 | REAL_VALUE_TYPE r; | |
441 | long i; | |
442 | ||
443 | REAL_VALUE_FROM_CONST_DOUBLE (r, op); | |
444 | if (REAL_VALUES_EQUAL (r, dconst0) && | |
445 | ! REAL_VALUE_MINUS_ZERO (r)) | |
446 | return 0; | |
447 | REAL_VALUE_TO_TARGET_SINGLE (r, i); | |
448 | if (SPARC_SETHI_P (i)) | |
449 | return 1; | |
450 | } | |
451 | ||
452 | return 0; | |
453 | } | |
454 | ||
455 | /* Nonzero if OP is a floating point constant which can | |
456 | be loaded into an integer register using a single | |
457 | mov instruction. */ | |
458 | ||
459 | int | |
460 | fp_mov_p (op) | |
461 | rtx op; | |
462 | { | |
463 | if (GET_CODE (op) == CONST_DOUBLE) | |
464 | { | |
465 | REAL_VALUE_TYPE r; | |
466 | long i; | |
467 | ||
468 | REAL_VALUE_FROM_CONST_DOUBLE (r, op); | |
469 | if (REAL_VALUES_EQUAL (r, dconst0) && | |
470 | ! REAL_VALUE_MINUS_ZERO (r)) | |
471 | return 0; | |
472 | REAL_VALUE_TO_TARGET_SINGLE (r, i); | |
473 | if (SPARC_SIMM13_P (i)) | |
474 | return 1; | |
475 | } | |
476 | ||
477 | return 0; | |
478 | } | |
479 | ||
480 | /* Nonzero if OP is a floating point constant which can | |
481 | be loaded into an integer register using a high/losum | |
482 | instruction sequence. */ | |
483 | ||
484 | int | |
485 | fp_high_losum_p (op) | |
486 | rtx op; | |
487 | { | |
488 | /* The constraints calling this should only be in | |
489 | SFmode move insns, so any constant which cannot | |
490 | be moved using a single insn will do. */ | |
491 | if (GET_CODE (op) == CONST_DOUBLE) | |
492 | { | |
493 | REAL_VALUE_TYPE r; | |
494 | long i; | |
495 | ||
496 | REAL_VALUE_FROM_CONST_DOUBLE (r, op); | |
497 | if (REAL_VALUES_EQUAL (r, dconst0) && | |
498 | ! REAL_VALUE_MINUS_ZERO (r)) | |
499 | return 0; | |
500 | REAL_VALUE_TO_TARGET_SINGLE (r, i); | |
501 | if (! SPARC_SETHI_P (i) | |
502 | && ! SPARC_SIMM13_P (i)) | |
503 | return 1; | |
504 | } | |
505 | ||
506 | return 0; | |
507 | } | |
508 | ||
61a55e8b DE |
509 | /* Nonzero if OP is an integer register. */ |
510 | ||
511 | int | |
512 | intreg_operand (op, mode) | |
513 | rtx op; | |
487a6e06 | 514 | enum machine_mode mode ATTRIBUTE_UNUSED; |
61a55e8b DE |
515 | { |
516 | return (register_operand (op, SImode) | |
a9e27770 | 517 | || (TARGET_ARCH64 && register_operand (op, DImode))); |
61a55e8b DE |
518 | } |
519 | ||
520 | /* Nonzero if OP is a floating point condition code register. */ | |
521 | ||
522 | int | |
c4ce6853 | 523 | fcc_reg_operand (op, mode) |
61a55e8b DE |
524 | rtx op; |
525 | enum machine_mode mode; | |
526 | { | |
527 | /* This can happen when recog is called from combine. Op may be a MEM. | |
528 | Fail instead of calling abort in this case. */ | |
c4ce6853 | 529 | if (GET_CODE (op) != REG) |
61a55e8b | 530 | return 0; |
304b7a23 | 531 | |
c4ce6853 | 532 | if (mode != VOIDmode && mode != GET_MODE (op)) |
61a55e8b | 533 | return 0; |
304b7a23 DE |
534 | if (mode == VOIDmode |
535 | && (GET_MODE (op) != CCFPmode && GET_MODE (op) != CCFPEmode)) | |
536 | return 0; | |
61a55e8b | 537 | |
c4ce6853 | 538 | #if 0 /* ??? ==> 1 when %fcc0-3 are pseudos first. See gen_compare_reg(). */ |
61a55e8b DE |
539 | if (reg_renumber == 0) |
540 | return REGNO (op) >= FIRST_PSEUDO_REGISTER; | |
541 | return REGNO_OK_FOR_CCFP_P (REGNO (op)); | |
542 | #else | |
c4ce6853 | 543 | return (unsigned) REGNO (op) - SPARC_FIRST_V9_FCC_REG < 4; |
61a55e8b DE |
544 | #endif |
545 | } | |
546 | ||
c4ce6853 DE |
547 | /* Nonzero if OP is an integer or floating point condition code register. */ |
548 | ||
549 | int | |
550 | icc_or_fcc_reg_operand (op, mode) | |
551 | rtx op; | |
552 | enum machine_mode mode; | |
553 | { | |
554 | if (GET_CODE (op) == REG && REGNO (op) == SPARC_ICC_REG) | |
304b7a23 DE |
555 | { |
556 | if (mode != VOIDmode && mode != GET_MODE (op)) | |
557 | return 0; | |
558 | if (mode == VOIDmode | |
559 | && GET_MODE (op) != CCmode && GET_MODE (op) != CCXmode) | |
560 | return 0; | |
561 | return 1; | |
562 | } | |
563 | ||
c4ce6853 DE |
564 | return fcc_reg_operand (op, mode); |
565 | } | |
566 | ||
ab835497 RK |
567 | /* Nonzero if OP can appear as the dest of a RESTORE insn. */ |
568 | int | |
569 | restore_operand (op, mode) | |
570 | rtx op; | |
571 | enum machine_mode mode; | |
572 | { | |
573 | return (GET_CODE (op) == REG && GET_MODE (op) == mode | |
574 | && (REGNO (op) < 8 || (REGNO (op) >= 24 && REGNO (op) < 32))); | |
575 | } | |
576 | ||
401cec23 JW |
577 | /* Call insn on SPARC can take a PC-relative constant address, or any regular |
578 | memory address. */ | |
ab835497 RK |
579 | |
580 | int | |
581 | call_operand (op, mode) | |
582 | rtx op; | |
583 | enum machine_mode mode; | |
584 | { | |
585 | if (GET_CODE (op) != MEM) | |
586 | abort (); | |
587 | op = XEXP (op, 0); | |
2445f289 | 588 | return (symbolic_operand (op, mode) || memory_address_p (Pmode, op)); |
ab835497 RK |
589 | } |
590 | ||
591 | int | |
592 | call_operand_address (op, mode) | |
593 | rtx op; | |
594 | enum machine_mode mode; | |
595 | { | |
2445f289 | 596 | return (symbolic_operand (op, mode) || memory_address_p (Pmode, op)); |
ab835497 RK |
597 | } |
598 | ||
599 | /* Returns 1 if OP is either a symbol reference or a sum of a symbol | |
600 | reference and a constant. */ | |
601 | ||
602 | int | |
603 | symbolic_operand (op, mode) | |
604 | register rtx op; | |
605 | enum machine_mode mode; | |
606 | { | |
6871dd65 RH |
607 | enum machine_mode omode = GET_MODE (op); |
608 | ||
609 | if (omode != mode && omode != VOIDmode && mode != VOIDmode) | |
610 | return 0; | |
611 | ||
ab835497 RK |
612 | switch (GET_CODE (op)) |
613 | { | |
614 | case SYMBOL_REF: | |
615 | case LABEL_REF: | |
616 | return 1; | |
617 | ||
618 | case CONST: | |
619 | op = XEXP (op, 0); | |
620 | return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF | |
621 | || GET_CODE (XEXP (op, 0)) == LABEL_REF) | |
622 | && GET_CODE (XEXP (op, 1)) == CONST_INT); | |
623 | ||
ab835497 RK |
624 | default: |
625 | return 0; | |
626 | } | |
627 | } | |
628 | ||
629 | /* Return truth value of statement that OP is a symbolic memory | |
630 | operand of mode MODE. */ | |
631 | ||
632 | int | |
633 | symbolic_memory_operand (op, mode) | |
634 | rtx op; | |
487a6e06 | 635 | enum machine_mode mode ATTRIBUTE_UNUSED; |
ab835497 RK |
636 | { |
637 | if (GET_CODE (op) == SUBREG) | |
638 | op = SUBREG_REG (op); | |
639 | if (GET_CODE (op) != MEM) | |
640 | return 0; | |
641 | op = XEXP (op, 0); | |
642 | return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST | |
643 | || GET_CODE (op) == HIGH || GET_CODE (op) == LABEL_REF); | |
644 | } | |
645 | ||
5ab7138b DE |
646 | /* Return truth value of statement that OP is a LABEL_REF of mode MODE. */ |
647 | ||
648 | int | |
649 | label_ref_operand (op, mode) | |
650 | rtx op; | |
651 | enum machine_mode mode; | |
652 | { | |
653 | if (GET_CODE (op) != LABEL_REF) | |
654 | return 0; | |
655 | if (GET_MODE (op) != mode) | |
656 | return 0; | |
657 | return 1; | |
658 | } | |
659 | ||
95726648 DE |
660 | /* Return 1 if the operand is an argument used in generating pic references |
661 | in either the medium/low or medium/anywhere code models of sparc64. */ | |
662 | ||
663 | int | |
664 | sp64_medium_pic_operand (op, mode) | |
665 | rtx op; | |
487a6e06 | 666 | enum machine_mode mode ATTRIBUTE_UNUSED; |
95726648 DE |
667 | { |
668 | /* Check for (const (minus (symbol_ref:GOT) | |
669 | (const (minus (label) (pc))))). */ | |
670 | if (GET_CODE (op) != CONST) | |
671 | return 0; | |
672 | op = XEXP (op, 0); | |
673 | if (GET_CODE (op) != MINUS) | |
674 | return 0; | |
675 | if (GET_CODE (XEXP (op, 0)) != SYMBOL_REF) | |
676 | return 0; | |
677 | /* ??? Ensure symbol is GOT. */ | |
678 | if (GET_CODE (XEXP (op, 1)) != CONST) | |
679 | return 0; | |
680 | if (GET_CODE (XEXP (XEXP (op, 1), 0)) != MINUS) | |
681 | return 0; | |
682 | return 1; | |
683 | } | |
684 | ||
61a55e8b DE |
685 | /* Return 1 if the operand is a data segment reference. This includes |
686 | the readonly data segment, or in other words anything but the text segment. | |
687 | This is needed in the medium/anywhere code model on v9. These values | |
a0a301fc | 688 | are accessed with EMBMEDANY_BASE_REG. */ |
61a55e8b DE |
689 | |
690 | int | |
691 | data_segment_operand (op, mode) | |
692 | rtx op; | |
487a6e06 | 693 | enum machine_mode mode ATTRIBUTE_UNUSED; |
61a55e8b DE |
694 | { |
695 | switch (GET_CODE (op)) | |
696 | { | |
697 | case SYMBOL_REF : | |
698 | return ! SYMBOL_REF_FLAG (op); | |
699 | case PLUS : | |
95726648 DE |
700 | /* Assume canonical format of symbol + constant. |
701 | Fall through. */ | |
61a55e8b | 702 | case CONST : |
b1474bb7 | 703 | return data_segment_operand (XEXP (op, 0), VOIDmode); |
61a55e8b DE |
704 | default : |
705 | return 0; | |
706 | } | |
707 | } | |
708 | ||
709 | /* Return 1 if the operand is a text segment reference. | |
710 | This is needed in the medium/anywhere code model on v9. */ | |
711 | ||
712 | int | |
713 | text_segment_operand (op, mode) | |
714 | rtx op; | |
487a6e06 | 715 | enum machine_mode mode ATTRIBUTE_UNUSED; |
61a55e8b DE |
716 | { |
717 | switch (GET_CODE (op)) | |
718 | { | |
719 | case LABEL_REF : | |
720 | return 1; | |
721 | case SYMBOL_REF : | |
722 | return SYMBOL_REF_FLAG (op); | |
723 | case PLUS : | |
95726648 DE |
724 | /* Assume canonical format of symbol + constant. |
725 | Fall through. */ | |
61a55e8b | 726 | case CONST : |
b1474bb7 | 727 | return text_segment_operand (XEXP (op, 0), VOIDmode); |
61a55e8b DE |
728 | default : |
729 | return 0; | |
730 | } | |
731 | } | |
732 | ||
ab835497 RK |
733 | /* Return 1 if the operand is either a register or a memory operand that is |
734 | not symbolic. */ | |
735 | ||
736 | int | |
737 | reg_or_nonsymb_mem_operand (op, mode) | |
738 | register rtx op; | |
739 | enum machine_mode mode; | |
740 | { | |
741 | if (register_operand (op, mode)) | |
742 | return 1; | |
743 | ||
744 | if (memory_operand (op, mode) && ! symbolic_memory_operand (op, mode)) | |
745 | return 1; | |
746 | ||
747 | return 0; | |
748 | } | |
749 | ||
ab835497 | 750 | int |
6ac34277 | 751 | splittable_symbolic_memory_operand (op, mode) |
ab835497 | 752 | rtx op; |
487a6e06 | 753 | enum machine_mode mode ATTRIBUTE_UNUSED; |
ab835497 | 754 | { |
6ac34277 DE |
755 | if (GET_CODE (op) != MEM) |
756 | return 0; | |
757 | if (! symbolic_operand (XEXP (op, 0), Pmode)) | |
758 | return 0; | |
759 | return 1; | |
760 | } | |
761 | ||
762 | int | |
763 | splittable_immediate_memory_operand (op, mode) | |
764 | rtx op; | |
487a6e06 | 765 | enum machine_mode mode ATTRIBUTE_UNUSED; |
6ac34277 DE |
766 | { |
767 | if (GET_CODE (op) != MEM) | |
768 | return 0; | |
769 | if (! immediate_operand (XEXP (op, 0), Pmode)) | |
770 | return 0; | |
771 | return 1; | |
ab835497 RK |
772 | } |
773 | ||
774 | /* Return truth value of whether OP is EQ or NE. */ | |
775 | ||
776 | int | |
777 | eq_or_neq (op, mode) | |
778 | rtx op; | |
487a6e06 | 779 | enum machine_mode mode ATTRIBUTE_UNUSED; |
ab835497 RK |
780 | { |
781 | return (GET_CODE (op) == EQ || GET_CODE (op) == NE); | |
782 | } | |
783 | ||
784 | /* Return 1 if this is a comparison operator, but not an EQ, NE, GEU, | |
785 | or LTU for non-floating-point. We handle those specially. */ | |
786 | ||
787 | int | |
788 | normal_comp_operator (op, mode) | |
789 | rtx op; | |
487a6e06 | 790 | enum machine_mode mode ATTRIBUTE_UNUSED; |
ab835497 RK |
791 | { |
792 | enum rtx_code code = GET_CODE (op); | |
793 | ||
794 | if (GET_RTX_CLASS (code) != '<') | |
795 | return 0; | |
796 | ||
4d449554 JW |
797 | if (GET_MODE (XEXP (op, 0)) == CCFPmode |
798 | || GET_MODE (XEXP (op, 0)) == CCFPEmode) | |
ab835497 RK |
799 | return 1; |
800 | ||
801 | return (code != NE && code != EQ && code != GEU && code != LTU); | |
802 | } | |
803 | ||
804 | /* Return 1 if this is a comparison operator. This allows the use of | |
805 | MATCH_OPERATOR to recognize all the branch insns. */ | |
806 | ||
807 | int | |
808 | noov_compare_op (op, mode) | |
809 | register rtx op; | |
487a6e06 | 810 | enum machine_mode mode ATTRIBUTE_UNUSED; |
ab835497 RK |
811 | { |
812 | enum rtx_code code = GET_CODE (op); | |
813 | ||
814 | if (GET_RTX_CLASS (code) != '<') | |
815 | return 0; | |
816 | ||
817 | if (GET_MODE (XEXP (op, 0)) == CC_NOOVmode) | |
818 | /* These are the only branches which work with CC_NOOVmode. */ | |
819 | return (code == EQ || code == NE || code == GE || code == LT); | |
820 | return 1; | |
821 | } | |
822 | ||
61a55e8b DE |
823 | /* Nonzero if OP is a comparison operator suitable for use in v9 |
824 | conditional move or branch on register contents instructions. */ | |
825 | ||
826 | int | |
827 | v9_regcmp_op (op, mode) | |
828 | register rtx op; | |
487a6e06 | 829 | enum machine_mode mode ATTRIBUTE_UNUSED; |
61a55e8b DE |
830 | { |
831 | enum rtx_code code = GET_CODE (op); | |
832 | ||
833 | if (GET_RTX_CLASS (code) != '<') | |
834 | return 0; | |
835 | ||
cd5fb1ee | 836 | return v9_regcmp_p (code); |
61a55e8b DE |
837 | } |
838 | ||
ab835497 RK |
839 | /* Return 1 if this is a SIGN_EXTEND or ZERO_EXTEND operation. */ |
840 | ||
841 | int | |
842 | extend_op (op, mode) | |
843 | rtx op; | |
487a6e06 | 844 | enum machine_mode mode ATTRIBUTE_UNUSED; |
ab835497 RK |
845 | { |
846 | return GET_CODE (op) == SIGN_EXTEND || GET_CODE (op) == ZERO_EXTEND; | |
847 | } | |
848 | ||
849 | /* Return nonzero if OP is an operator of mode MODE which can set | |
850 | the condition codes explicitly. We do not include PLUS and MINUS | |
851 | because these require CC_NOOVmode, which we handle explicitly. */ | |
852 | ||
853 | int | |
854 | cc_arithop (op, mode) | |
855 | rtx op; | |
487a6e06 | 856 | enum machine_mode mode ATTRIBUTE_UNUSED; |
ab835497 RK |
857 | { |
858 | if (GET_CODE (op) == AND | |
859 | || GET_CODE (op) == IOR | |
860 | || GET_CODE (op) == XOR) | |
861 | return 1; | |
862 | ||
863 | return 0; | |
864 | } | |
865 | ||
866 | /* Return nonzero if OP is an operator of mode MODE which can bitwise | |
867 | complement its second operand and set the condition codes explicitly. */ | |
868 | ||
869 | int | |
870 | cc_arithopn (op, mode) | |
871 | rtx op; | |
487a6e06 | 872 | enum machine_mode mode ATTRIBUTE_UNUSED; |
ab835497 RK |
873 | { |
874 | /* XOR is not here because combine canonicalizes (xor (not ...) ...) | |
875 | and (xor ... (not ...)) to (not (xor ...)). */ | |
876 | return (GET_CODE (op) == AND | |
877 | || GET_CODE (op) == IOR); | |
878 | } | |
879 | \f | |
58cbf20e DE |
880 | /* Return true if OP is a register, or is a CONST_INT that can fit in a |
881 | signed 13 bit immediate field. This is an acceptable SImode operand for | |
882 | most 3 address instructions. */ | |
ab835497 RK |
883 | |
884 | int | |
885 | arith_operand (op, mode) | |
886 | rtx op; | |
887 | enum machine_mode mode; | |
888 | { | |
284d86e9 | 889 | int val; |
11301057 | 890 | if (register_operand (op, mode)) |
284d86e9 JC |
891 | return 1; |
892 | if (GET_CODE (op) != CONST_INT) | |
893 | return 0; | |
894 | val = INTVAL (op) & 0xffffffff; | |
895 | return SPARC_SIMM13_P (val); | |
ab835497 RK |
896 | } |
897 | ||
5d6d3339 JJ |
898 | /* Return true if OP is a constant 4096 */ |
899 | ||
900 | int | |
901 | arith_4096_operand (op, mode) | |
902 | rtx op; | |
ddf80874 | 903 | enum machine_mode mode ATTRIBUTE_UNUSED; |
5d6d3339 JJ |
904 | { |
905 | int val; | |
906 | if (GET_CODE (op) != CONST_INT) | |
907 | return 0; | |
908 | val = INTVAL (op) & 0xffffffff; | |
909 | return val == 4096; | |
910 | } | |
911 | ||
912 | /* Return true if OP is suitable as second operand for add/sub */ | |
913 | ||
914 | int | |
915 | arith_add_operand (op, mode) | |
916 | rtx op; | |
917 | enum machine_mode mode; | |
918 | { | |
919 | return arith_operand (op, mode) || arith_4096_operand (op, mode); | |
920 | } | |
921 | ||
89e65674 DM |
922 | /* Return true if OP is a CONST_INT or a CONST_DOUBLE which can fit in the |
923 | immediate field of OR and XOR instructions. Used for 64-bit | |
924 | constant formation patterns. */ | |
925 | int | |
926 | const64_operand (op, mode) | |
927 | rtx op; | |
ddf80874 | 928 | enum machine_mode mode ATTRIBUTE_UNUSED; |
89e65674 DM |
929 | { |
930 | return ((GET_CODE (op) == CONST_INT | |
931 | && SPARC_SIMM13_P (INTVAL (op))) | |
9208e4b2 | 932 | #if HOST_BITS_PER_WIDE_INT != 64 |
89e65674 | 933 | || (GET_CODE (op) == CONST_DOUBLE |
9208e4b2 DM |
934 | && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op)) |
935 | && (CONST_DOUBLE_HIGH (op) == | |
936 | ((CONST_DOUBLE_LOW (op) & 0x80000000) != 0 ? | |
ddf80874 | 937 | (HOST_WIDE_INT)0xffffffff : 0))) |
9208e4b2 | 938 | #endif |
11301057 | 939 | ); |
89e65674 DM |
940 | } |
941 | ||
9208e4b2 | 942 | /* The same, but only for sethi instructions. */ |
89e65674 DM |
943 | int |
944 | const64_high_operand (op, mode) | |
945 | rtx op; | |
ddf80874 | 946 | enum machine_mode mode ATTRIBUTE_UNUSED; |
89e65674 DM |
947 | { |
948 | return ((GET_CODE (op) == CONST_INT | |
9208e4b2 DM |
949 | && (INTVAL (op) & 0xfffffc00) != 0 |
950 | && SPARC_SETHI_P (INTVAL (op)) | |
951 | #if HOST_BITS_PER_WIDE_INT != 64 | |
952 | /* Must be positive on non-64bit host else the | |
953 | optimizer is fooled into thinking that sethi | |
954 | sign extends, even though it does not. */ | |
955 | && INTVAL (op) >= 0 | |
956 | #endif | |
957 | ) | |
89e65674 DM |
958 | || (GET_CODE (op) == CONST_DOUBLE |
959 | && CONST_DOUBLE_HIGH (op) == 0 | |
9208e4b2 | 960 | && (CONST_DOUBLE_LOW (op) & 0xfffffc00) != 0 |
11301057 | 961 | && SPARC_SETHI_P (CONST_DOUBLE_LOW (op)))); |
89e65674 DM |
962 | } |
963 | ||
58cbf20e DE |
964 | /* Return true if OP is a register, or is a CONST_INT that can fit in a |
965 | signed 11 bit immediate field. This is an acceptable SImode operand for | |
966 | the movcc instructions. */ | |
61a55e8b DE |
967 | |
968 | int | |
969 | arith11_operand (op, mode) | |
970 | rtx op; | |
971 | enum machine_mode mode; | |
972 | { | |
973 | return (register_operand (op, mode) | |
58cbf20e | 974 | || (GET_CODE (op) == CONST_INT && SPARC_SIMM11_P (INTVAL (op)))); |
61a55e8b DE |
975 | } |
976 | ||
58cbf20e DE |
977 | /* Return true if OP is a register, or is a CONST_INT that can fit in a |
978 | signed 10 bit immediate field. This is an acceptable SImode operand for | |
979 | the movrcc instructions. */ | |
61a55e8b DE |
980 | |
981 | int | |
982 | arith10_operand (op, mode) | |
983 | rtx op; | |
984 | enum machine_mode mode; | |
985 | { | |
986 | return (register_operand (op, mode) | |
58cbf20e | 987 | || (GET_CODE (op) == CONST_INT && SPARC_SIMM10_P (INTVAL (op)))); |
61a55e8b DE |
988 | } |
989 | ||
23b8a89f JW |
990 | /* Return true if OP is a register, is a CONST_INT that fits in a 13 bit |
991 | immediate field, or is a CONST_DOUBLE whose both parts fit in a 13 bit | |
61a55e8b DE |
992 | immediate field. |
993 | v9: Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that | |
994 | can fit in a 13 bit immediate field. This is an acceptable DImode operand | |
995 | for most 3 address instructions. */ | |
ab835497 RK |
996 | |
997 | int | |
998 | arith_double_operand (op, mode) | |
999 | rtx op; | |
1000 | enum machine_mode mode; | |
1001 | { | |
1002 | return (register_operand (op, mode) | |
23b8a89f | 1003 | || (GET_CODE (op) == CONST_INT && SMALL_INT (op)) |
a9e27770 | 1004 | || (! TARGET_ARCH64 |
61a55e8b | 1005 | && GET_CODE (op) == CONST_DOUBLE |
bf62bbf1 DE |
1006 | && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x1000) < 0x2000 |
1007 | && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_HIGH (op) + 0x1000) < 0x2000) | |
a9e27770 | 1008 | || (TARGET_ARCH64 |
61a55e8b | 1009 | && GET_CODE (op) == CONST_DOUBLE |
bf62bbf1 | 1010 | && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x1000) < 0x2000 |
61a55e8b DE |
1011 | && ((CONST_DOUBLE_HIGH (op) == -1 |
1012 | && (CONST_DOUBLE_LOW (op) & 0x1000) == 0x1000) | |
1013 | || (CONST_DOUBLE_HIGH (op) == 0 | |
1014 | && (CONST_DOUBLE_LOW (op) & 0x1000) == 0)))); | |
1015 | } | |
1016 | ||
5d6d3339 JJ |
1017 | /* Return true if OP is a constant 4096 for DImode on ARCH64 */ |
1018 | ||
1019 | int | |
1020 | arith_double_4096_operand (op, mode) | |
1021 | rtx op; | |
ddf80874 | 1022 | enum machine_mode mode ATTRIBUTE_UNUSED; |
5d6d3339 JJ |
1023 | { |
1024 | return (TARGET_ARCH64 && | |
1025 | ((GET_CODE (op) == CONST_INT && INTVAL (op) == 4096) || | |
1026 | (GET_CODE (op) == CONST_DOUBLE && | |
1027 | CONST_DOUBLE_LOW (op) == 4096 && | |
1028 | CONST_DOUBLE_HIGH (op) == 0))); | |
1029 | } | |
1030 | ||
1031 | /* Return true if OP is suitable as second operand for add/sub in DImode */ | |
1032 | ||
1033 | int | |
1034 | arith_double_add_operand (op, mode) | |
1035 | rtx op; | |
1036 | enum machine_mode mode; | |
1037 | { | |
1038 | return arith_double_operand (op, mode) || arith_double_4096_operand (op, mode); | |
1039 | } | |
1040 | ||
61a55e8b DE |
1041 | /* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that |
1042 | can fit in an 11 bit immediate field. This is an acceptable DImode | |
1043 | operand for the movcc instructions. */ | |
1044 | /* ??? Replace with arith11_operand? */ | |
1045 | ||
1046 | int | |
1047 | arith11_double_operand (op, mode) | |
1048 | rtx op; | |
1049 | enum machine_mode mode; | |
1050 | { | |
1051 | return (register_operand (op, mode) | |
1052 | || (GET_CODE (op) == CONST_DOUBLE | |
1053 | && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode) | |
bf62bbf1 | 1054 | && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x400) < 0x800 |
61a55e8b DE |
1055 | && ((CONST_DOUBLE_HIGH (op) == -1 |
1056 | && (CONST_DOUBLE_LOW (op) & 0x400) == 0x400) | |
1057 | || (CONST_DOUBLE_HIGH (op) == 0 | |
1058 | && (CONST_DOUBLE_LOW (op) & 0x400) == 0))) | |
1059 | || (GET_CODE (op) == CONST_INT | |
1060 | && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode) | |
bf62bbf1 | 1061 | && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x400) < 0x800)); |
61a55e8b DE |
1062 | } |
1063 | ||
1064 | /* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that | |
1065 | can fit in an 10 bit immediate field. This is an acceptable DImode | |
1066 | operand for the movrcc instructions. */ | |
1067 | /* ??? Replace with arith10_operand? */ | |
1068 | ||
1069 | int | |
1070 | arith10_double_operand (op, mode) | |
1071 | rtx op; | |
1072 | enum machine_mode mode; | |
1073 | { | |
1074 | return (register_operand (op, mode) | |
1075 | || (GET_CODE (op) == CONST_DOUBLE | |
1076 | && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode) | |
1077 | && (unsigned) (CONST_DOUBLE_LOW (op) + 0x200) < 0x400 | |
1078 | && ((CONST_DOUBLE_HIGH (op) == -1 | |
1079 | && (CONST_DOUBLE_LOW (op) & 0x200) == 0x200) | |
1080 | || (CONST_DOUBLE_HIGH (op) == 0 | |
1081 | && (CONST_DOUBLE_LOW (op) & 0x200) == 0))) | |
1082 | || (GET_CODE (op) == CONST_INT | |
1083 | && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode) | |
bf62bbf1 | 1084 | && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x200) < 0x400)); |
ab835497 RK |
1085 | } |
1086 | ||
1087 | /* Return truth value of whether OP is a integer which fits the | |
228b4037 JW |
1088 | range constraining immediate operands in most three-address insns, |
1089 | which have a 13 bit immediate field. */ | |
ab835497 RK |
1090 | |
1091 | int | |
1092 | small_int (op, mode) | |
1093 | rtx op; | |
487a6e06 | 1094 | enum machine_mode mode ATTRIBUTE_UNUSED; |
ab835497 | 1095 | { |
11301057 | 1096 | return (GET_CODE (op) == CONST_INT && SMALL_INT (op)); |
ab835497 RK |
1097 | } |
1098 | ||
e0d80184 DM |
1099 | int |
1100 | small_int_or_double (op, mode) | |
1101 | rtx op; | |
1102 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
1103 | { | |
1104 | return ((GET_CODE (op) == CONST_INT && SMALL_INT (op)) | |
1105 | || (GET_CODE (op) == CONST_DOUBLE | |
1106 | && CONST_DOUBLE_HIGH (op) == 0 | |
11301057 | 1107 | && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op)))); |
e0d80184 DM |
1108 | } |
1109 | ||
9b3fad96 JW |
1110 | /* Recognize operand values for the umul instruction. That instruction sign |
1111 | extends immediate values just like all other sparc instructions, but | |
1112 | interprets the extended result as an unsigned number. */ | |
1113 | ||
1114 | int | |
1115 | uns_small_int (op, mode) | |
1116 | rtx op; | |
487a6e06 | 1117 | enum machine_mode mode ATTRIBUTE_UNUSED; |
9b3fad96 JW |
1118 | { |
1119 | #if HOST_BITS_PER_WIDE_INT > 32 | |
1120 | /* All allowed constants will fit a CONST_INT. */ | |
11301057 RH |
1121 | return (GET_CODE (op) == CONST_INT |
1122 | && ((INTVAL (op) >= 0 && INTVAL (op) < 0x1000) | |
1123 | || (INTVAL (op) >= 0xFFFFF000 | |
1124 | && INTVAL (op) < 0x100000000))); | |
9b3fad96 | 1125 | #else |
11301057 RH |
1126 | return ((GET_CODE (op) == CONST_INT && (unsigned) INTVAL (op) < 0x1000) |
1127 | || (GET_CODE (op) == CONST_DOUBLE | |
1128 | && CONST_DOUBLE_HIGH (op) == 0 | |
1129 | && (unsigned) CONST_DOUBLE_LOW (op) - 0xFFFFF000 < 0x1000)); | |
9b3fad96 JW |
1130 | #endif |
1131 | } | |
1132 | ||
1133 | int | |
1134 | uns_arith_operand (op, mode) | |
1135 | rtx op; | |
1136 | enum machine_mode mode; | |
1137 | { | |
1138 | return register_operand (op, mode) || uns_small_int (op, mode); | |
1139 | } | |
1140 | ||
ab835497 RK |
1141 | /* Return truth value of statement that OP is a call-clobbered register. */ |
1142 | int | |
1143 | clobbered_register (op, mode) | |
1144 | rtx op; | |
487a6e06 | 1145 | enum machine_mode mode ATTRIBUTE_UNUSED; |
ab835497 RK |
1146 | { |
1147 | return (GET_CODE (op) == REG && call_used_regs[REGNO (op)]); | |
1148 | } | |
ab835497 | 1149 | |
e0d80184 | 1150 | /* Return 1 if OP is a valid operand for the source of a move insn. */ |
61a55e8b | 1151 | |
e0d80184 DM |
1152 | int |
1153 | input_operand (op, mode) | |
1154 | rtx op; | |
1155 | enum machine_mode mode; | |
1156 | { | |
1157 | /* If both modes are non-void they must be the same. */ | |
1158 | if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op)) | |
1159 | return 0; | |
61a55e8b | 1160 | |
11301057 RH |
1161 | /* Only a tiny bit of handling for CONSTANT_P_RTX is necessary. */ |
1162 | if (GET_CODE (op) == CONST && GET_CODE (XEXP (op, 0)) == CONSTANT_P_RTX) | |
1163 | return 1; | |
1164 | ||
e0d80184 DM |
1165 | /* Allow any one instruction integer constant, and all CONST_INT |
1166 | variants when we are working in DImode and !arch64. */ | |
1167 | if (GET_MODE_CLASS (mode) == MODE_INT | |
9208e4b2 DM |
1168 | && ((GET_CODE (op) == CONST_INT |
1169 | && ((SPARC_SETHI_P (INTVAL (op)) | |
1170 | && (! TARGET_ARCH64 | |
1171 | || (INTVAL (op) >= 0) | |
dcee55a2 JJ |
1172 | || mode == SImode |
1173 | || mode == HImode | |
1174 | || mode == QImode)) | |
9208e4b2 DM |
1175 | || SPARC_SIMM13_P (INTVAL (op)) |
1176 | || (mode == DImode | |
1177 | && ! TARGET_ARCH64))) | |
1178 | || (TARGET_ARCH64 | |
1179 | && GET_CODE (op) == CONST_DOUBLE | |
1180 | && ((CONST_DOUBLE_HIGH (op) == 0 | |
1181 | && SPARC_SETHI_P (CONST_DOUBLE_LOW (op))) | |
1182 | || | |
1183 | #if HOST_BITS_PER_WIDE_INT == 64 | |
1184 | (CONST_DOUBLE_HIGH (op) == 0 | |
1185 | && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op))) | |
1186 | #else | |
1187 | (SPARC_SIMM13_P (CONST_DOUBLE_LOW (op)) | |
1188 | && (((CONST_DOUBLE_LOW (op) & 0x80000000) == 0 | |
1189 | && CONST_DOUBLE_HIGH (op) == 0) | |
1190 | || (CONST_DOUBLE_HIGH (op) == -1))) | |
1191 | #endif | |
1192 | )))) | |
e0d80184 DM |
1193 | return 1; |
1194 | ||
e0d80184 DM |
1195 | /* If !arch64 and this is a DImode const, allow it so that |
1196 | the splits can be generated. */ | |
1197 | if (! TARGET_ARCH64 | |
1198 | && mode == DImode | |
1199 | && GET_CODE (op) == CONST_DOUBLE) | |
1200 | return 1; | |
1201 | ||
1202 | if (register_operand (op, mode)) | |
1203 | return 1; | |
1204 | ||
62190128 DM |
1205 | if (GET_MODE_CLASS (mode) == MODE_FLOAT |
1206 | && GET_CODE (op) == CONST_DOUBLE) | |
1207 | return 1; | |
1208 | ||
e0d80184 DM |
1209 | /* If this is a SUBREG, look inside so that we handle |
1210 | paradoxical ones. */ | |
1211 | if (GET_CODE (op) == SUBREG) | |
1212 | op = SUBREG_REG (op); | |
1213 | ||
1214 | /* Check for valid MEM forms. */ | |
1215 | if (GET_CODE (op) == MEM) | |
61a55e8b | 1216 | { |
e0d80184 | 1217 | rtx inside = XEXP (op, 0); |
61a55e8b | 1218 | |
e0d80184 | 1219 | if (GET_CODE (inside) == LO_SUM) |
03ad6f4d DM |
1220 | { |
1221 | /* We can't allow these because all of the splits | |
1222 | (eventually as they trickle down into DFmode | |
1223 | splits) require offsettable memory references. */ | |
1224 | if (! TARGET_V9 | |
1225 | && GET_MODE (op) == TFmode) | |
1226 | return 0; | |
1227 | ||
1228 | return (register_operand (XEXP (inside, 0), Pmode) | |
1229 | && CONSTANT_P (XEXP (inside, 1))); | |
1230 | } | |
e0d80184 | 1231 | return memory_address_p (mode, inside); |
61a55e8b | 1232 | } |
ab835497 | 1233 | |
e0d80184 DM |
1234 | return 0; |
1235 | } | |
1236 | ||
1237 | \f | |
1238 | /* We know it can't be done in one insn when we get here, | |
1239 | the movsi expander guarentees this. */ | |
1240 | void | |
1241 | sparc_emit_set_const32 (op0, op1) | |
1242 | rtx op0; | |
1243 | rtx op1; | |
1244 | { | |
1245 | enum machine_mode mode = GET_MODE (op0); | |
1246 | rtx temp; | |
1247 | ||
1248 | if (GET_CODE (op1) == CONST_INT) | |
284d86e9 | 1249 | { |
2a01c939 | 1250 | HOST_WIDE_INT value = INTVAL (op1); |
e0d80184 DM |
1251 | |
1252 | if (SPARC_SETHI_P (value) | |
1253 | || SPARC_SIMM13_P (value)) | |
1254 | abort (); | |
284d86e9 | 1255 | } |
e0d80184 DM |
1256 | |
1257 | /* Full 2-insn decomposition is needed. */ | |
1258 | if (reload_in_progress || reload_completed) | |
1259 | temp = op0; | |
284d86e9 | 1260 | else |
e0d80184 DM |
1261 | temp = gen_reg_rtx (mode); |
1262 | ||
71648202 DM |
1263 | if (GET_CODE (op1) == CONST_INT) |
1264 | { | |
1265 | /* Emit them as real moves instead of a HIGH/LO_SUM, | |
1266 | this way CSE can see everything and reuse intermediate | |
1267 | values if it wants. */ | |
1268 | if (TARGET_ARCH64 | |
1269 | && HOST_BITS_PER_WIDE_INT != 64 | |
1270 | && (INTVAL (op1) & 0x80000000) != 0) | |
1271 | { | |
1272 | emit_insn (gen_rtx_SET (VOIDmode, | |
1273 | temp, | |
1274 | gen_rtx_CONST_DOUBLE (VOIDmode, const0_rtx, | |
1275 | INTVAL (op1) & 0xfffffc00, 0))); | |
1276 | } | |
1277 | else | |
1278 | { | |
1279 | emit_insn (gen_rtx_SET (VOIDmode, | |
1280 | temp, | |
1281 | GEN_INT (INTVAL (op1) & 0xfffffc00))); | |
1282 | } | |
1283 | emit_insn (gen_rtx_SET (VOIDmode, | |
1284 | op0, | |
1285 | gen_rtx_IOR (mode, | |
1286 | temp, | |
1287 | GEN_INT (INTVAL (op1) & 0x3ff)))); | |
1288 | } | |
1289 | else | |
1290 | { | |
1291 | /* A symbol, emit in the traditional way. */ | |
1292 | emit_insn (gen_rtx_SET (VOIDmode, | |
1293 | temp, | |
1294 | gen_rtx_HIGH (mode, | |
1295 | op1))); | |
1296 | emit_insn (gen_rtx_SET (VOIDmode, | |
1297 | op0, | |
1298 | gen_rtx_LO_SUM (mode, | |
1299 | temp, | |
1300 | op1))); | |
1301 | ||
1302 | } | |
e0d80184 DM |
1303 | } |
1304 | ||
1305 | \f | |
1306 | /* Sparc-v9 code-model support. */ | |
1307 | void | |
1308 | sparc_emit_set_symbolic_const64 (op0, op1, temp1) | |
1309 | rtx op0; | |
1310 | rtx op1; | |
1311 | rtx temp1; | |
1312 | { | |
1313 | switch (sparc_cmodel) | |
284d86e9 | 1314 | { |
e0d80184 DM |
1315 | case CM_MEDLOW: |
1316 | /* The range spanned by all instructions in the object is less | |
1317 | than 2^31 bytes (2GB) and the distance from any instruction | |
1318 | to the location of the label _GLOBAL_OFFSET_TABLE_ is less | |
1319 | than 2^31 bytes (2GB). | |
ab835497 | 1320 | |
e0d80184 DM |
1321 | The executable must be in the low 4TB of the virtual address |
1322 | space. | |
61a55e8b | 1323 | |
e0d80184 DM |
1324 | sethi %hi(symbol), %temp |
1325 | or %temp, %lo(symbol), %reg */ | |
9208e4b2 DM |
1326 | emit_insn (gen_rtx_SET (VOIDmode, temp1, gen_rtx_HIGH (DImode, op1))); |
1327 | emit_insn (gen_rtx_SET (VOIDmode, op0, gen_rtx_LO_SUM (DImode, temp1, op1))); | |
e0d80184 | 1328 | break; |
61a55e8b | 1329 | |
e0d80184 DM |
1330 | case CM_MEDMID: |
1331 | /* The range spanned by all instructions in the object is less | |
1332 | than 2^31 bytes (2GB) and the distance from any instruction | |
1333 | to the location of the label _GLOBAL_OFFSET_TABLE_ is less | |
1334 | than 2^31 bytes (2GB). | |
1335 | ||
1336 | The executable must be in the low 16TB of the virtual address | |
1337 | space. | |
1338 | ||
1339 | sethi %h44(symbol), %temp1 | |
1340 | or %temp1, %m44(symbol), %temp2 | |
1341 | sllx %temp2, 12, %temp3 | |
1342 | or %temp3, %l44(symbol), %reg */ | |
1343 | emit_insn (gen_seth44 (op0, op1)); | |
1344 | emit_insn (gen_setm44 (op0, op0, op1)); | |
9208e4b2 | 1345 | emit_insn (gen_rtx_SET (VOIDmode, temp1, |
e0d80184 DM |
1346 | gen_rtx_ASHIFT (DImode, op0, GEN_INT (12)))); |
1347 | emit_insn (gen_setl44 (op0, temp1, op1)); | |
1348 | break; | |
61a55e8b | 1349 | |
e0d80184 DM |
1350 | case CM_MEDANY: |
1351 | /* The range spanned by all instructions in the object is less | |
1352 | than 2^31 bytes (2GB) and the distance from any instruction | |
1353 | to the location of the label _GLOBAL_OFFSET_TABLE_ is less | |
1354 | than 2^31 bytes (2GB). | |
1355 | ||
1356 | The executable can be placed anywhere in the virtual address | |
1357 | space. | |
1358 | ||
1359 | sethi %hh(symbol), %temp1 | |
1360 | sethi %lm(symbol), %temp2 | |
1361 | or %temp1, %hm(symbol), %temp3 | |
1362 | or %temp2, %lo(symbol), %temp4 | |
1363 | sllx %temp3, 32, %temp5 | |
1364 | or %temp4, %temp5, %reg */ | |
1365 | ||
1366 | /* Getting this right wrt. reloading is really tricky. | |
5722d61c | 1367 | We _MUST_ have a separate temporary at this point, |
e0d80184 DM |
1368 | if we don't barf immediately instead of generating |
1369 | incorrect code. */ | |
1370 | if (temp1 == op0) | |
1371 | abort (); | |
61a55e8b | 1372 | |
e0d80184 DM |
1373 | emit_insn (gen_sethh (op0, op1)); |
1374 | emit_insn (gen_setlm (temp1, op1)); | |
1375 | emit_insn (gen_sethm (op0, op0, op1)); | |
9208e4b2 | 1376 | emit_insn (gen_rtx_SET (VOIDmode, op0, |
e0d80184 | 1377 | gen_rtx_ASHIFT (DImode, op0, GEN_INT (32)))); |
9208e4b2 | 1378 | emit_insn (gen_rtx_SET (VOIDmode, op0, |
e0d80184 DM |
1379 | gen_rtx_PLUS (DImode, op0, temp1))); |
1380 | emit_insn (gen_setlo (op0, op0, op1)); | |
1381 | break; | |
61a55e8b | 1382 | |
e0d80184 DM |
1383 | case CM_EMBMEDANY: |
1384 | /* Old old old backwards compatibility kruft here. | |
1385 | Essentially it is MEDLOW with a fixed 64-bit | |
1386 | virtual base added to all data segment addresses. | |
1387 | Text-segment stuff is computed like MEDANY, we can't | |
1388 | reuse the code above because the relocation knobs | |
1389 | look different. | |
1390 | ||
1391 | Data segment: sethi %hi(symbol), %temp1 | |
1392 | or %temp1, %lo(symbol), %temp2 | |
1393 | add %temp2, EMBMEDANY_BASE_REG, %reg | |
1394 | ||
1395 | Text segment: sethi %uhi(symbol), %temp1 | |
1396 | sethi %hi(symbol), %temp2 | |
1397 | or %temp1, %ulo(symbol), %temp3 | |
1398 | or %temp2, %lo(symbol), %temp4 | |
1399 | sllx %temp3, 32, %temp5 | |
1400 | or %temp4, %temp5, %reg */ | |
1401 | if (data_segment_operand (op1, GET_MODE (op1))) | |
1402 | { | |
1403 | emit_insn (gen_embmedany_sethi (temp1, op1)); | |
1404 | emit_insn (gen_embmedany_brsum (op0, temp1)); | |
1405 | emit_insn (gen_embmedany_losum (op0, op0, op1)); | |
1406 | } | |
1407 | else | |
1408 | { | |
1409 | /* Getting this right wrt. reloading is really tricky. | |
5722d61c | 1410 | We _MUST_ have a separate temporary at this point, |
f710f868 | 1411 | so we barf immediately instead of generating |
e0d80184 DM |
1412 | incorrect code. */ |
1413 | if (temp1 == op0) | |
1414 | abort (); | |
61a55e8b | 1415 | |
e0d80184 DM |
1416 | emit_insn (gen_embmedany_textuhi (op0, op1)); |
1417 | emit_insn (gen_embmedany_texthi (temp1, op1)); | |
1418 | emit_insn (gen_embmedany_textulo (op0, op0, op1)); | |
9208e4b2 | 1419 | emit_insn (gen_rtx_SET (VOIDmode, op0, |
e0d80184 | 1420 | gen_rtx_ASHIFT (DImode, op0, GEN_INT (32)))); |
9208e4b2 | 1421 | emit_insn (gen_rtx_SET (VOIDmode, op0, |
e0d80184 DM |
1422 | gen_rtx_PLUS (DImode, op0, temp1))); |
1423 | emit_insn (gen_embmedany_textlo (op0, op0, op1)); | |
1424 | } | |
1425 | break; | |
1426 | ||
1427 | default: | |
1428 | abort(); | |
1429 | } | |
1430 | } | |
1431 | ||
9208e4b2 DM |
1432 | /* These avoid problems when cross compiling. If we do not |
1433 | go through all this hair then the optimizer will see | |
1434 | invalid REG_EQUAL notes or in some cases none at all. */ | |
f6da8bc3 KG |
1435 | static void sparc_emit_set_safe_HIGH64 PARAMS ((rtx, HOST_WIDE_INT)); |
1436 | static rtx gen_safe_SET64 PARAMS ((rtx, HOST_WIDE_INT)); | |
1437 | static rtx gen_safe_OR64 PARAMS ((rtx, HOST_WIDE_INT)); | |
1438 | static rtx gen_safe_XOR64 PARAMS ((rtx, HOST_WIDE_INT)); | |
9208e4b2 DM |
1439 | |
1440 | #if HOST_BITS_PER_WIDE_INT == 64 | |
1441 | #define GEN_HIGHINT64(__x) GEN_INT ((__x) & 0xfffffc00) | |
1442 | #define GEN_INT64(__x) GEN_INT (__x) | |
1443 | #else | |
1444 | #define GEN_HIGHINT64(__x) \ | |
1445 | gen_rtx_CONST_DOUBLE (VOIDmode, const0_rtx, \ | |
1446 | (__x) & 0xfffffc00, 0) | |
1447 | #define GEN_INT64(__x) \ | |
1448 | gen_rtx_CONST_DOUBLE (VOIDmode, const0_rtx, \ | |
1449 | (__x) & 0xffffffff, \ | |
1450 | ((__x) & 0x80000000 \ | |
1451 | ? 0xffffffff : 0)) | |
1452 | #endif | |
1453 | ||
1454 | /* The optimizer is not to assume anything about exactly | |
1455 | which bits are set for a HIGH, they are unspecified. | |
1456 | Unfortunately this leads to many missed optimizations | |
1457 | during CSE. We mask out the non-HIGH bits, and matches | |
1458 | a plain movdi, to alleviate this problem. */ | |
1459 | static void | |
1460 | sparc_emit_set_safe_HIGH64 (dest, val) | |
1461 | rtx dest; | |
1462 | HOST_WIDE_INT val; | |
1463 | { | |
1464 | emit_insn (gen_rtx_SET (VOIDmode, dest, GEN_HIGHINT64 (val))); | |
1465 | } | |
2a01c939 | 1466 | |
e0d80184 | 1467 | static rtx |
9208e4b2 DM |
1468 | gen_safe_SET64 (dest, val) |
1469 | rtx dest; | |
e0d80184 | 1470 | HOST_WIDE_INT val; |
61a55e8b | 1471 | { |
9208e4b2 DM |
1472 | return gen_rtx_SET (VOIDmode, dest, GEN_INT64 (val)); |
1473 | } | |
1474 | ||
1475 | static rtx | |
1476 | gen_safe_OR64 (src, val) | |
1477 | rtx src; | |
1478 | HOST_WIDE_INT val; | |
1479 | { | |
1480 | return gen_rtx_IOR (DImode, src, GEN_INT64 (val)); | |
1481 | } | |
1482 | ||
1483 | static rtx | |
1484 | gen_safe_XOR64 (src, val) | |
1485 | rtx src; | |
1486 | HOST_WIDE_INT val; | |
1487 | { | |
1488 | return gen_rtx_XOR (DImode, src, GEN_INT64 (val)); | |
e0d80184 | 1489 | } |
61a55e8b | 1490 | |
e0d80184 DM |
1491 | /* Worker routines for 64-bit constant formation on arch64. |
1492 | One of the key things to be doing in these emissions is | |
1493 | to create as many temp REGs as possible. This makes it | |
1494 | possible for half-built constants to be used later when | |
1495 | such values are similar to something required later on. | |
1496 | Without doing this, the optimizer cannot see such | |
1497 | opportunities. */ | |
2a01c939 DM |
1498 | |
1499 | static void sparc_emit_set_const64_quick1 | |
f6da8bc3 | 1500 | PARAMS ((rtx, rtx, unsigned HOST_WIDE_INT, int)); |
2a01c939 | 1501 | |
e0d80184 DM |
1502 | static void |
1503 | sparc_emit_set_const64_quick1 (op0, temp, low_bits, is_neg) | |
1504 | rtx op0; | |
1505 | rtx temp; | |
2a01c939 | 1506 | unsigned HOST_WIDE_INT low_bits; |
e0d80184 DM |
1507 | int is_neg; |
1508 | { | |
2a01c939 | 1509 | unsigned HOST_WIDE_INT high_bits; |
a9e27770 | 1510 | |
e0d80184 | 1511 | if (is_neg) |
2a01c939 | 1512 | high_bits = (~low_bits) & 0xffffffff; |
31bc9eba | 1513 | else |
e0d80184 | 1514 | high_bits = low_bits; |
31bc9eba | 1515 | |
9208e4b2 | 1516 | sparc_emit_set_safe_HIGH64 (temp, high_bits); |
e0d80184 | 1517 | if (!is_neg) |
5108f3e5 DM |
1518 | { |
1519 | emit_insn (gen_rtx_SET (VOIDmode, op0, | |
1520 | gen_safe_OR64 (temp, (high_bits & 0x3ff)))); | |
1521 | } | |
e0d80184 | 1522 | else |
5108f3e5 DM |
1523 | { |
1524 | /* If we are XOR'ing with -1, then we should emit a one's complement | |
1525 | instead. This way the combiner will notice logical operations | |
1526 | such as ANDN later on and substitute. */ | |
1527 | if ((low_bits & 0x3ff) == 0x3ff) | |
1528 | { | |
1529 | emit_insn (gen_rtx_SET (VOIDmode, op0, | |
1530 | gen_rtx_NOT (DImode, temp))); | |
1531 | } | |
1532 | else | |
1533 | { | |
1534 | emit_insn (gen_rtx_SET (VOIDmode, op0, | |
1535 | gen_safe_XOR64 (temp, | |
1536 | (-0x400 | (low_bits & 0x3ff))))); | |
1537 | } | |
1538 | } | |
e0d80184 | 1539 | } |
61a55e8b | 1540 | |
2a01c939 | 1541 | static void sparc_emit_set_const64_quick2 |
f6da8bc3 | 1542 | PARAMS ((rtx, rtx, unsigned HOST_WIDE_INT, |
2a01c939 DM |
1543 | unsigned HOST_WIDE_INT, int)); |
1544 | ||
e0d80184 DM |
1545 | static void |
1546 | sparc_emit_set_const64_quick2 (op0, temp, high_bits, low_immediate, shift_count) | |
1547 | rtx op0; | |
1548 | rtx temp; | |
2a01c939 DM |
1549 | unsigned HOST_WIDE_INT high_bits; |
1550 | unsigned HOST_WIDE_INT low_immediate; | |
e0d80184 DM |
1551 | int shift_count; |
1552 | { | |
1553 | rtx temp2 = op0; | |
61a55e8b | 1554 | |
e0d80184 DM |
1555 | if ((high_bits & 0xfffffc00) != 0) |
1556 | { | |
9208e4b2 | 1557 | sparc_emit_set_safe_HIGH64 (temp, high_bits); |
e0d80184 | 1558 | if ((high_bits & ~0xfffffc00) != 0) |
9208e4b2 DM |
1559 | emit_insn (gen_rtx_SET (VOIDmode, op0, |
1560 | gen_safe_OR64 (temp, (high_bits & 0x3ff)))); | |
61a55e8b | 1561 | else |
e0d80184 | 1562 | temp2 = temp; |
61a55e8b DE |
1563 | } |
1564 | else | |
1565 | { | |
f710f868 | 1566 | emit_insn (gen_safe_SET64 (temp, high_bits)); |
e0d80184 DM |
1567 | temp2 = temp; |
1568 | } | |
61a55e8b | 1569 | |
e0d80184 | 1570 | /* Now shift it up into place. */ |
9208e4b2 | 1571 | emit_insn (gen_rtx_SET (VOIDmode, op0, |
e0d80184 DM |
1572 | gen_rtx_ASHIFT (DImode, temp2, |
1573 | GEN_INT (shift_count)))); | |
61a55e8b | 1574 | |
e0d80184 DM |
1575 | /* If there is a low immediate part piece, finish up by |
1576 | putting that in as well. */ | |
1577 | if (low_immediate != 0) | |
9208e4b2 DM |
1578 | emit_insn (gen_rtx_SET (VOIDmode, op0, |
1579 | gen_safe_OR64 (op0, low_immediate))); | |
ab835497 RK |
1580 | } |
1581 | ||
2a01c939 | 1582 | static void sparc_emit_set_const64_longway |
f6da8bc3 | 1583 | PARAMS ((rtx, rtx, unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT)); |
2a01c939 | 1584 | |
e0d80184 DM |
1585 | /* Full 64-bit constant decomposition. Even though this is the |
1586 | 'worst' case, we still optimize a few things away. */ | |
1587 | static void | |
1588 | sparc_emit_set_const64_longway (op0, temp, high_bits, low_bits) | |
1589 | rtx op0; | |
1590 | rtx temp; | |
2a01c939 DM |
1591 | unsigned HOST_WIDE_INT high_bits; |
1592 | unsigned HOST_WIDE_INT low_bits; | |
ab835497 | 1593 | { |
e0d80184 | 1594 | rtx sub_temp; |
4bf7135b | 1595 | |
e0d80184 DM |
1596 | if (reload_in_progress || reload_completed) |
1597 | sub_temp = op0; | |
1598 | else | |
1599 | sub_temp = gen_reg_rtx (DImode); | |
1600 | ||
1601 | if ((high_bits & 0xfffffc00) != 0) | |
1602 | { | |
9208e4b2 | 1603 | sparc_emit_set_safe_HIGH64 (temp, high_bits); |
e0d80184 | 1604 | if ((high_bits & ~0xfffffc00) != 0) |
9208e4b2 | 1605 | emit_insn (gen_rtx_SET (VOIDmode, |
e0d80184 | 1606 | sub_temp, |
9208e4b2 | 1607 | gen_safe_OR64 (temp, (high_bits & 0x3ff)))); |
e0d80184 DM |
1608 | else |
1609 | sub_temp = temp; | |
1610 | } | |
1611 | else | |
ab835497 | 1612 | { |
f710f868 | 1613 | emit_insn (gen_safe_SET64 (temp, high_bits)); |
e0d80184 | 1614 | sub_temp = temp; |
ab835497 | 1615 | } |
4bf7135b | 1616 | |
e0d80184 | 1617 | if (!reload_in_progress && !reload_completed) |
284d86e9 | 1618 | { |
e0d80184 DM |
1619 | rtx temp2 = gen_reg_rtx (DImode); |
1620 | rtx temp3 = gen_reg_rtx (DImode); | |
1621 | rtx temp4 = gen_reg_rtx (DImode); | |
284d86e9 | 1622 | |
9208e4b2 | 1623 | emit_insn (gen_rtx_SET (VOIDmode, temp4, |
e0d80184 DM |
1624 | gen_rtx_ASHIFT (DImode, sub_temp, |
1625 | GEN_INT (32)))); | |
4bf7135b | 1626 | |
9208e4b2 | 1627 | sparc_emit_set_safe_HIGH64 (temp2, low_bits); |
e0d80184 | 1628 | if ((low_bits & ~0xfffffc00) != 0) |
f710f868 DM |
1629 | { |
1630 | emit_insn (gen_rtx_SET (VOIDmode, temp3, | |
1631 | gen_safe_OR64 (temp2, (low_bits & 0x3ff)))); | |
1632 | emit_insn (gen_rtx_SET (VOIDmode, op0, | |
1633 | gen_rtx_PLUS (DImode, temp4, temp3))); | |
1634 | } | |
1635 | else | |
1636 | { | |
1637 | emit_insn (gen_rtx_SET (VOIDmode, op0, | |
1638 | gen_rtx_PLUS (DImode, temp4, temp2))); | |
1639 | } | |
284d86e9 | 1640 | } |
e0d80184 DM |
1641 | else |
1642 | { | |
9208e4b2 DM |
1643 | rtx low1 = GEN_INT ((low_bits >> (32 - 12)) & 0xfff); |
1644 | rtx low2 = GEN_INT ((low_bits >> (32 - 12 - 12)) & 0xfff); | |
1645 | rtx low3 = GEN_INT ((low_bits >> (32 - 12 - 12 - 8)) & 0x0ff); | |
e0d80184 | 1646 | int to_shift = 12; |
284d86e9 | 1647 | |
e0d80184 DM |
1648 | /* We are in the middle of reload, so this is really |
1649 | painful. However we do still make an attempt to | |
5108f3e5 | 1650 | avoid emitting truly stupid code. */ |
e0d80184 DM |
1651 | if (low1 != const0_rtx) |
1652 | { | |
9208e4b2 | 1653 | emit_insn (gen_rtx_SET (VOIDmode, op0, |
e0d80184 | 1654 | gen_rtx_ASHIFT (DImode, sub_temp, |
2a01c939 | 1655 | GEN_INT (to_shift)))); |
9208e4b2 | 1656 | emit_insn (gen_rtx_SET (VOIDmode, op0, |
e0d80184 DM |
1657 | gen_rtx_IOR (DImode, op0, low1))); |
1658 | sub_temp = op0; | |
1659 | to_shift = 12; | |
1660 | } | |
1661 | else | |
1662 | { | |
1663 | to_shift += 12; | |
1664 | } | |
1665 | if (low2 != const0_rtx) | |
1666 | { | |
9208e4b2 | 1667 | emit_insn (gen_rtx_SET (VOIDmode, op0, |
e0d80184 DM |
1668 | gen_rtx_ASHIFT (DImode, sub_temp, |
1669 | GEN_INT (to_shift)))); | |
9208e4b2 | 1670 | emit_insn (gen_rtx_SET (VOIDmode, op0, |
e0d80184 DM |
1671 | gen_rtx_IOR (DImode, op0, low2))); |
1672 | sub_temp = op0; | |
1673 | to_shift = 8; | |
1674 | } | |
1675 | else | |
1676 | { | |
1677 | to_shift += 8; | |
1678 | } | |
9208e4b2 | 1679 | emit_insn (gen_rtx_SET (VOIDmode, op0, |
e0d80184 DM |
1680 | gen_rtx_ASHIFT (DImode, sub_temp, |
1681 | GEN_INT (to_shift)))); | |
1682 | if (low3 != const0_rtx) | |
9208e4b2 | 1683 | emit_insn (gen_rtx_SET (VOIDmode, op0, |
e0d80184 DM |
1684 | gen_rtx_IOR (DImode, op0, low3))); |
1685 | /* phew... */ | |
1686 | } | |
284d86e9 JC |
1687 | } |
1688 | ||
e0d80184 | 1689 | /* Analyze a 64-bit constant for certain properties. */ |
2a01c939 | 1690 | static void analyze_64bit_constant |
f6da8bc3 | 1691 | PARAMS ((unsigned HOST_WIDE_INT, |
2a01c939 DM |
1692 | unsigned HOST_WIDE_INT, |
1693 | int *, int *, int *)); | |
1694 | ||
e0d80184 DM |
1695 | static void |
1696 | analyze_64bit_constant (high_bits, low_bits, hbsp, lbsp, abbasp) | |
2a01c939 | 1697 | unsigned HOST_WIDE_INT high_bits, low_bits; |
e0d80184 | 1698 | int *hbsp, *lbsp, *abbasp; |
ab835497 | 1699 | { |
e0d80184 DM |
1700 | int lowest_bit_set, highest_bit_set, all_bits_between_are_set; |
1701 | int i; | |
ab835497 | 1702 | |
e0d80184 DM |
1703 | lowest_bit_set = highest_bit_set = -1; |
1704 | i = 0; | |
1705 | do | |
ab835497 | 1706 | { |
e0d80184 DM |
1707 | if ((lowest_bit_set == -1) |
1708 | && ((low_bits >> i) & 1)) | |
1709 | lowest_bit_set = i; | |
1710 | if ((highest_bit_set == -1) | |
1711 | && ((high_bits >> (32 - i - 1)) & 1)) | |
1712 | highest_bit_set = (64 - i - 1); | |
1713 | } | |
1714 | while (++i < 32 | |
1715 | && ((highest_bit_set == -1) | |
1716 | || (lowest_bit_set == -1))); | |
1717 | if (i == 32) | |
1718 | { | |
1719 | i = 0; | |
1720 | do | |
ab835497 | 1721 | { |
e0d80184 DM |
1722 | if ((lowest_bit_set == -1) |
1723 | && ((high_bits >> i) & 1)) | |
1724 | lowest_bit_set = i + 32; | |
1725 | if ((highest_bit_set == -1) | |
1726 | && ((low_bits >> (32 - i - 1)) & 1)) | |
1727 | highest_bit_set = 32 - i - 1; | |
ab835497 | 1728 | } |
e0d80184 DM |
1729 | while (++i < 32 |
1730 | && ((highest_bit_set == -1) | |
1731 | || (lowest_bit_set == -1))); | |
1732 | } | |
1733 | /* If there are no bits set this should have gone out | |
1734 | as one instruction! */ | |
1735 | if (lowest_bit_set == -1 | |
1736 | || highest_bit_set == -1) | |
9208e4b2 | 1737 | abort (); |
e0d80184 DM |
1738 | all_bits_between_are_set = 1; |
1739 | for (i = lowest_bit_set; i <= highest_bit_set; i++) | |
1740 | { | |
1741 | if (i < 32) | |
1742 | { | |
1743 | if ((low_bits & (1 << i)) != 0) | |
1744 | continue; | |
1745 | } | |
1746 | else | |
1747 | { | |
1748 | if ((high_bits & (1 << (i - 32))) != 0) | |
1749 | continue; | |
1750 | } | |
1751 | all_bits_between_are_set = 0; | |
1752 | break; | |
ab835497 | 1753 | } |
e0d80184 DM |
1754 | *hbsp = highest_bit_set; |
1755 | *lbsp = lowest_bit_set; | |
1756 | *abbasp = all_bits_between_are_set; | |
ab835497 | 1757 | } |
6a4bb1fa | 1758 | |
2a01c939 | 1759 | static int const64_is_2insns |
f6da8bc3 | 1760 | PARAMS ((unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT)); |
2a01c939 | 1761 | |
e0d80184 DM |
1762 | static int |
1763 | const64_is_2insns (high_bits, low_bits) | |
2a01c939 | 1764 | unsigned HOST_WIDE_INT high_bits, low_bits; |
e0d80184 DM |
1765 | { |
1766 | int highest_bit_set, lowest_bit_set, all_bits_between_are_set; | |
284d86e9 | 1767 | |
e0d80184 | 1768 | if (high_bits == 0 |
2a01c939 | 1769 | || high_bits == 0xffffffff) |
e0d80184 | 1770 | return 1; |
6a4bb1fa | 1771 | |
e0d80184 DM |
1772 | analyze_64bit_constant (high_bits, low_bits, |
1773 | &highest_bit_set, &lowest_bit_set, | |
1774 | &all_bits_between_are_set); | |
6a4bb1fa | 1775 | |
f710f868 DM |
1776 | if ((highest_bit_set == 63 |
1777 | || lowest_bit_set == 0) | |
e0d80184 DM |
1778 | && all_bits_between_are_set != 0) |
1779 | return 1; | |
6a4bb1fa | 1780 | |
9208e4b2 DM |
1781 | if ((highest_bit_set - lowest_bit_set) < 21) |
1782 | return 1; | |
1783 | ||
6a4bb1fa DE |
1784 | return 0; |
1785 | } | |
1786 | ||
2a01c939 | 1787 | static unsigned HOST_WIDE_INT create_simple_focus_bits |
f6da8bc3 | 1788 | PARAMS ((unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT, |
ddf80874 | 1789 | int, int)); |
2a01c939 DM |
1790 | |
1791 | static unsigned HOST_WIDE_INT | |
ddf80874 | 1792 | create_simple_focus_bits (high_bits, low_bits, lowest_bit_set, shift) |
2a01c939 | 1793 | unsigned HOST_WIDE_INT high_bits, low_bits; |
ddf80874 | 1794 | int lowest_bit_set, shift; |
ab835497 | 1795 | { |
f710f868 | 1796 | HOST_WIDE_INT hi, lo; |
ab835497 | 1797 | |
e0d80184 DM |
1798 | if (lowest_bit_set < 32) |
1799 | { | |
1800 | lo = (low_bits >> lowest_bit_set) << shift; | |
1801 | hi = ((high_bits << (32 - lowest_bit_set)) << shift); | |
1802 | } | |
1803 | else | |
1804 | { | |
1805 | lo = 0; | |
1806 | hi = ((high_bits >> (lowest_bit_set - 32)) << shift); | |
1807 | } | |
1808 | if (hi & lo) | |
9208e4b2 | 1809 | abort (); |
e0d80184 DM |
1810 | return (hi | lo); |
1811 | } | |
ab835497 | 1812 | |
e0d80184 DM |
1813 | /* Here we are sure to be arch64 and this is an integer constant |
1814 | being loaded into a register. Emit the most efficient | |
1815 | insn sequence possible. Detection of all the 1-insn cases | |
1816 | has been done already. */ | |
1817 | void | |
1818 | sparc_emit_set_const64 (op0, op1) | |
1819 | rtx op0; | |
1820 | rtx op1; | |
1821 | { | |
2a01c939 | 1822 | unsigned HOST_WIDE_INT high_bits, low_bits; |
e0d80184 DM |
1823 | int lowest_bit_set, highest_bit_set; |
1824 | int all_bits_between_are_set; | |
e0d80184 | 1825 | rtx temp; |
ab835497 | 1826 | |
e0d80184 DM |
1827 | /* Sanity check that we know what we are working with. */ |
1828 | if (! TARGET_ARCH64 | |
1829 | || GET_CODE (op0) != REG | |
1830 | || (REGNO (op0) >= SPARC_FIRST_FP_REG | |
1831 | && REGNO (op0) <= SPARC_LAST_V9_FP_REG)) | |
9208e4b2 | 1832 | abort (); |
95726648 | 1833 | |
f710f868 DM |
1834 | if (reload_in_progress || reload_completed) |
1835 | temp = op0; | |
1836 | else | |
1837 | temp = gen_reg_rtx (DImode); | |
1838 | ||
e0d80184 DM |
1839 | if (GET_CODE (op1) != CONST_DOUBLE |
1840 | && GET_CODE (op1) != CONST_INT) | |
1841 | { | |
5f78aa30 JC |
1842 | sparc_emit_set_symbolic_const64 (op0, op1, temp); |
1843 | return; | |
e0d80184 | 1844 | } |
ab835497 | 1845 | |
e0d80184 DM |
1846 | if (GET_CODE (op1) == CONST_DOUBLE) |
1847 | { | |
1848 | #if HOST_BITS_PER_WIDE_INT == 64 | |
2a01c939 | 1849 | high_bits = (CONST_DOUBLE_LOW (op1) >> 32) & 0xffffffff; |
e0d80184 DM |
1850 | low_bits = CONST_DOUBLE_LOW (op1) & 0xffffffff; |
1851 | #else | |
1852 | high_bits = CONST_DOUBLE_HIGH (op1); | |
1853 | low_bits = CONST_DOUBLE_LOW (op1); | |
1854 | #endif | |
ab835497 | 1855 | } |
e0d80184 | 1856 | else |
ab835497 | 1857 | { |
e0d80184 | 1858 | #if HOST_BITS_PER_WIDE_INT == 64 |
2a01c939 | 1859 | high_bits = ((INTVAL (op1) >> 32) & 0xffffffff); |
e0d80184 DM |
1860 | low_bits = (INTVAL (op1) & 0xffffffff); |
1861 | #else | |
1862 | high_bits = ((INTVAL (op1) < 0) ? | |
1863 | 0xffffffff : | |
1864 | 0x00000000); | |
1865 | low_bits = INTVAL (op1); | |
1866 | #endif | |
1867 | } | |
ab835497 | 1868 | |
e0d80184 DM |
1869 | /* low_bits bits 0 --> 31 |
1870 | high_bits bits 32 --> 63 */ | |
ab835497 | 1871 | |
e0d80184 DM |
1872 | analyze_64bit_constant (high_bits, low_bits, |
1873 | &highest_bit_set, &lowest_bit_set, | |
1874 | &all_bits_between_are_set); | |
1875 | ||
1876 | /* First try for a 2-insn sequence. */ | |
1877 | ||
1878 | /* These situations are preferred because the optimizer can | |
1879 | * do more things with them: | |
1880 | * 1) mov -1, %reg | |
1881 | * sllx %reg, shift, %reg | |
1882 | * 2) mov -1, %reg | |
1883 | * srlx %reg, shift, %reg | |
1884 | * 3) mov some_small_const, %reg | |
1885 | * sllx %reg, shift, %reg | |
1886 | */ | |
1887 | if (((highest_bit_set == 63 | |
1888 | || lowest_bit_set == 0) | |
1889 | && all_bits_between_are_set != 0) | |
2a01c939 | 1890 | || ((highest_bit_set - lowest_bit_set) < 12)) |
e0d80184 | 1891 | { |
9208e4b2 | 1892 | HOST_WIDE_INT the_const = -1; |
e0d80184 DM |
1893 | int shift = lowest_bit_set; |
1894 | ||
f710f868 DM |
1895 | if ((highest_bit_set != 63 |
1896 | && lowest_bit_set != 0) | |
1897 | || all_bits_between_are_set == 0) | |
ab835497 | 1898 | { |
e0d80184 | 1899 | the_const = |
9208e4b2 | 1900 | create_simple_focus_bits (high_bits, low_bits, |
9208e4b2 | 1901 | lowest_bit_set, 0); |
ab835497 | 1902 | } |
e0d80184 | 1903 | else if (lowest_bit_set == 0) |
9208e4b2 | 1904 | shift = -(63 - highest_bit_set); |
e0d80184 | 1905 | |
f710f868 DM |
1906 | if (! SPARC_SIMM13_P (the_const)) |
1907 | abort (); | |
1908 | ||
9208e4b2 | 1909 | emit_insn (gen_safe_SET64 (temp, the_const)); |
e0d80184 | 1910 | if (shift > 0) |
9208e4b2 | 1911 | emit_insn (gen_rtx_SET (VOIDmode, |
e0d80184 DM |
1912 | op0, |
1913 | gen_rtx_ASHIFT (DImode, | |
1914 | temp, | |
1915 | GEN_INT (shift)))); | |
1916 | else if (shift < 0) | |
9208e4b2 | 1917 | emit_insn (gen_rtx_SET (VOIDmode, |
e0d80184 | 1918 | op0, |
9208e4b2 | 1919 | gen_rtx_LSHIFTRT (DImode, |
e0d80184 DM |
1920 | temp, |
1921 | GEN_INT (-shift)))); | |
ab835497 RK |
1922 | else |
1923 | abort (); | |
e0d80184 DM |
1924 | return; |
1925 | } | |
ab835497 | 1926 | |
e0d80184 DM |
1927 | /* Now a range of 22 or less bits set somewhere. |
1928 | * 1) sethi %hi(focus_bits), %reg | |
1929 | * sllx %reg, shift, %reg | |
1930 | * 2) sethi %hi(focus_bits), %reg | |
1931 | * srlx %reg, shift, %reg | |
1932 | */ | |
2a01c939 | 1933 | if ((highest_bit_set - lowest_bit_set) < 21) |
e0d80184 | 1934 | { |
2a01c939 | 1935 | unsigned HOST_WIDE_INT focus_bits = |
e0d80184 | 1936 | create_simple_focus_bits (high_bits, low_bits, |
ddf80874 | 1937 | lowest_bit_set, 10); |
f710f868 DM |
1938 | |
1939 | if (! SPARC_SETHI_P (focus_bits)) | |
1940 | abort (); | |
1941 | ||
9208e4b2 | 1942 | sparc_emit_set_safe_HIGH64 (temp, focus_bits); |
e0d80184 | 1943 | |
9208e4b2 | 1944 | /* If lowest_bit_set == 10 then a sethi alone could have done it. */ |
e0d80184 | 1945 | if (lowest_bit_set < 10) |
9208e4b2 | 1946 | emit_insn (gen_rtx_SET (VOIDmode, |
e0d80184 | 1947 | op0, |
9208e4b2 | 1948 | gen_rtx_LSHIFTRT (DImode, temp, |
e0d80184 | 1949 | GEN_INT (10 - lowest_bit_set)))); |
9208e4b2 DM |
1950 | else if (lowest_bit_set > 10) |
1951 | emit_insn (gen_rtx_SET (VOIDmode, | |
e0d80184 DM |
1952 | op0, |
1953 | gen_rtx_ASHIFT (DImode, temp, | |
1954 | GEN_INT (lowest_bit_set - 10)))); | |
1955 | else | |
9208e4b2 | 1956 | abort (); |
e0d80184 DM |
1957 | return; |
1958 | } | |
1959 | ||
1960 | /* 1) sethi %hi(low_bits), %reg | |
1961 | * or %reg, %lo(low_bits), %reg | |
1962 | * 2) sethi %hi(~low_bits), %reg | |
1963 | * xor %reg, %lo(-0x400 | (low_bits & 0x3ff)), %reg | |
1964 | */ | |
1965 | if (high_bits == 0 | |
2a01c939 | 1966 | || high_bits == 0xffffffff) |
5f78aa30 JC |
1967 | { |
1968 | sparc_emit_set_const64_quick1 (op0, temp, low_bits, | |
1969 | (high_bits == 0xffffffff)); | |
1970 | return; | |
1971 | } | |
e0d80184 | 1972 | |
f710f868 DM |
1973 | /* Now, try 3-insn sequences. */ |
1974 | ||
e0d80184 DM |
1975 | /* 1) sethi %hi(high_bits), %reg |
1976 | * or %reg, %lo(high_bits), %reg | |
1977 | * sllx %reg, 32, %reg | |
1978 | */ | |
f710f868 | 1979 | if (low_bits == 0) |
5f78aa30 | 1980 | { |
f710f868 | 1981 | sparc_emit_set_const64_quick2 (op0, temp, high_bits, 0, 32); |
5f78aa30 JC |
1982 | return; |
1983 | } | |
e0d80184 | 1984 | |
f710f868 DM |
1985 | /* We may be able to do something quick |
1986 | when the constant is negated, so try that. */ | |
e0d80184 DM |
1987 | if (const64_is_2insns ((~high_bits) & 0xffffffff, |
1988 | (~low_bits) & 0xfffffc00)) | |
1989 | { | |
5108f3e5 DM |
1990 | /* NOTE: The trailing bits get XOR'd so we need the |
1991 | non-negated bits, not the negated ones. */ | |
1992 | unsigned HOST_WIDE_INT trailing_bits = low_bits & 0x3ff; | |
e0d80184 DM |
1993 | |
1994 | if ((((~high_bits) & 0xffffffff) == 0 | |
1995 | && ((~low_bits) & 0x80000000) == 0) | |
1996 | || (((~high_bits) & 0xffffffff) == 0xffffffff | |
1997 | && ((~low_bits) & 0x80000000) != 0)) | |
ab835497 | 1998 | { |
5108f3e5 | 1999 | int fast_int = (~low_bits & 0xffffffff); |
e0d80184 | 2000 | |
5108f3e5 DM |
2001 | if ((SPARC_SETHI_P (fast_int) |
2002 | && (~high_bits & 0xffffffff) == 0) | |
2003 | || SPARC_SIMM13_P (fast_int)) | |
9208e4b2 | 2004 | emit_insn (gen_safe_SET64 (temp, fast_int)); |
ab835497 | 2005 | else |
9208e4b2 | 2006 | sparc_emit_set_const64 (temp, GEN_INT64 (fast_int)); |
ab835497 | 2007 | } |
e0d80184 DM |
2008 | else |
2009 | { | |
2010 | rtx negated_const; | |
2011 | #if HOST_BITS_PER_WIDE_INT == 64 | |
2012 | negated_const = GEN_INT (((~low_bits) & 0xfffffc00) | | |
2013 | (((HOST_WIDE_INT)((~high_bits) & 0xffffffff))<<32)); | |
2014 | #else | |
9208e4b2 | 2015 | negated_const = gen_rtx_CONST_DOUBLE (DImode, const0_rtx, |
e0d80184 DM |
2016 | (~low_bits) & 0xfffffc00, |
2017 | (~high_bits) & 0xffffffff); | |
2018 | #endif | |
2019 | sparc_emit_set_const64 (temp, negated_const); | |
2020 | } | |
5108f3e5 DM |
2021 | |
2022 | /* If we are XOR'ing with -1, then we should emit a one's complement | |
2023 | instead. This way the combiner will notice logical operations | |
2024 | such as ANDN later on and substitute. */ | |
2025 | if (trailing_bits == 0x3ff) | |
2026 | { | |
2027 | emit_insn (gen_rtx_SET (VOIDmode, op0, | |
2028 | gen_rtx_NOT (DImode, temp))); | |
2029 | } | |
2030 | else | |
2031 | { | |
2032 | emit_insn (gen_rtx_SET (VOIDmode, | |
2033 | op0, | |
2034 | gen_safe_XOR64 (temp, | |
2035 | (-0x400 | trailing_bits)))); | |
2036 | } | |
e0d80184 | 2037 | return; |
ab835497 | 2038 | } |
ab835497 | 2039 | |
e0d80184 DM |
2040 | /* 1) sethi %hi(xxx), %reg |
2041 | * or %reg, %lo(xxx), %reg | |
2042 | * sllx %reg, yyy, %reg | |
f710f868 DM |
2043 | * |
2044 | * ??? This is just a generalized version of the low_bits==0 | |
2045 | * thing above, FIXME... | |
e0d80184 DM |
2046 | */ |
2047 | if ((highest_bit_set - lowest_bit_set) < 32) | |
2048 | { | |
f710f868 DM |
2049 | unsigned HOST_WIDE_INT focus_bits = |
2050 | create_simple_focus_bits (high_bits, low_bits, | |
ddf80874 | 2051 | lowest_bit_set, 0); |
ab835497 | 2052 | |
e0d80184 DM |
2053 | /* We can't get here in this state. */ |
2054 | if (highest_bit_set < 32 | |
2055 | || lowest_bit_set >= 32) | |
9208e4b2 | 2056 | abort (); |
95726648 | 2057 | |
e0d80184 DM |
2058 | /* So what we know is that the set bits straddle the |
2059 | middle of the 64-bit word. */ | |
5f78aa30 JC |
2060 | sparc_emit_set_const64_quick2 (op0, temp, |
2061 | focus_bits, 0, | |
2062 | lowest_bit_set); | |
2063 | return; | |
e0d80184 | 2064 | } |
c85f7c16 | 2065 | |
f710f868 DM |
2066 | /* 1) sethi %hi(high_bits), %reg |
2067 | * or %reg, %lo(high_bits), %reg | |
2068 | * sllx %reg, 32, %reg | |
2069 | * or %reg, low_bits, %reg | |
2070 | */ | |
2071 | if (SPARC_SIMM13_P(low_bits) | |
2072 | && ((int)low_bits > 0)) | |
2073 | { | |
2074 | sparc_emit_set_const64_quick2 (op0, temp, high_bits, low_bits, 32); | |
2075 | return; | |
2076 | } | |
2077 | ||
e0d80184 DM |
2078 | /* The easiest way when all else fails, is full decomposition. */ |
2079 | #if 0 | |
2080 | printf ("sparc_emit_set_const64: Hard constant [%08lx%08lx] neg[%08lx%08lx]\n", | |
2081 | high_bits, low_bits, ~high_bits, ~low_bits); | |
2082 | #endif | |
2083 | sparc_emit_set_const64_longway (op0, temp, high_bits, low_bits); | |
c85f7c16 JL |
2084 | } |
2085 | ||
e267e177 RH |
2086 | /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, |
2087 | return the mode to be used for the comparison. For floating-point, | |
2088 | CCFP[E]mode is used. CC_NOOVmode should be used when the first operand | |
2089 | is a PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special | |
2090 | processing is needed. */ | |
2091 | ||
2092 | enum machine_mode | |
2093 | select_cc_mode (op, x, y) | |
2094 | enum rtx_code op; | |
2095 | rtx x; | |
2096 | rtx y ATTRIBUTE_UNUSED; | |
2097 | { | |
2098 | if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) | |
2099 | { | |
2100 | switch (op) | |
2101 | { | |
2102 | case EQ: | |
2103 | case NE: | |
2104 | case UNORDERED: | |
2105 | case ORDERED: | |
2106 | case UNLT: | |
2107 | case UNLE: | |
2108 | case UNGT: | |
2109 | case UNGE: | |
2110 | case UNEQ: | |
7913f3d0 | 2111 | case LTGT: |
e267e177 RH |
2112 | return CCFPmode; |
2113 | ||
2114 | case LT: | |
2115 | case LE: | |
2116 | case GT: | |
2117 | case GE: | |
2118 | return CCFPEmode; | |
2119 | ||
2120 | default: | |
2121 | abort (); | |
2122 | } | |
2123 | } | |
2124 | else if (GET_CODE (x) == PLUS || GET_CODE (x) == MINUS | |
2125 | || GET_CODE (x) == NEG || GET_CODE (x) == ASHIFT) | |
2126 | { | |
2127 | if (TARGET_ARCH64 && GET_MODE (x) == DImode) | |
2128 | return CCX_NOOVmode; | |
2129 | else | |
2130 | return CC_NOOVmode; | |
2131 | } | |
2132 | else | |
2133 | { | |
2134 | if (TARGET_ARCH64 && GET_MODE (x) == DImode) | |
2135 | return CCXmode; | |
2136 | else | |
2137 | return CCmode; | |
2138 | } | |
2139 | } | |
2140 | ||
e0d80184 DM |
2141 | /* X and Y are two things to compare using CODE. Emit the compare insn and |
2142 | return the rtx for the cc reg in the proper mode. */ | |
c85f7c16 | 2143 | |
e0d80184 DM |
2144 | rtx |
2145 | gen_compare_reg (code, x, y) | |
2146 | enum rtx_code code; | |
2147 | rtx x, y; | |
c85f7c16 | 2148 | { |
e0d80184 DM |
2149 | enum machine_mode mode = SELECT_CC_MODE (code, x, y); |
2150 | rtx cc_reg; | |
c85f7c16 | 2151 | |
e0d80184 DM |
2152 | /* ??? We don't have movcc patterns so we cannot generate pseudo regs for the |
2153 | fcc regs (cse can't tell they're really call clobbered regs and will | |
2154 | remove a duplicate comparison even if there is an intervening function | |
2155 | call - it will then try to reload the cc reg via an int reg which is why | |
2156 | we need the movcc patterns). It is possible to provide the movcc | |
2157 | patterns by using the ldxfsr/stxfsr v9 insns. I tried it: you need two | |
2158 | registers (say %g1,%g5) and it takes about 6 insns. A better fix would be | |
2159 | to tell cse that CCFPE mode registers (even pseudos) are call | |
2160 | clobbered. */ | |
c85f7c16 | 2161 | |
e0d80184 DM |
2162 | /* ??? This is an experiment. Rather than making changes to cse which may |
2163 | or may not be easy/clean, we do our own cse. This is possible because | |
2164 | we will generate hard registers. Cse knows they're call clobbered (it | |
2165 | doesn't know the same thing about pseudos). If we guess wrong, no big | |
2166 | deal, but if we win, great! */ | |
c85f7c16 | 2167 | |
e0d80184 DM |
2168 | if (TARGET_V9 && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) |
2169 | #if 1 /* experiment */ | |
284d86e9 | 2170 | { |
e0d80184 DM |
2171 | int reg; |
2172 | /* We cycle through the registers to ensure they're all exercised. */ | |
2173 | static int next_fcc_reg = 0; | |
2174 | /* Previous x,y for each fcc reg. */ | |
2175 | static rtx prev_args[4][2]; | |
284d86e9 | 2176 | |
e0d80184 DM |
2177 | /* Scan prev_args for x,y. */ |
2178 | for (reg = 0; reg < 4; reg++) | |
2179 | if (prev_args[reg][0] == x && prev_args[reg][1] == y) | |
2180 | break; | |
2181 | if (reg == 4) | |
2182 | { | |
2183 | reg = next_fcc_reg; | |
2184 | prev_args[reg][0] = x; | |
2185 | prev_args[reg][1] = y; | |
2186 | next_fcc_reg = (next_fcc_reg + 1) & 3; | |
2187 | } | |
2188 | cc_reg = gen_rtx_REG (mode, reg + SPARC_FIRST_V9_FCC_REG); | |
284d86e9 | 2189 | } |
e0d80184 DM |
2190 | #else |
2191 | cc_reg = gen_reg_rtx (mode); | |
2192 | #endif /* ! experiment */ | |
2193 | else if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) | |
2194 | cc_reg = gen_rtx_REG (mode, SPARC_FCC_REG); | |
2195 | else | |
2196 | cc_reg = gen_rtx_REG (mode, SPARC_ICC_REG); | |
284d86e9 | 2197 | |
e0d80184 DM |
2198 | emit_insn (gen_rtx_SET (VOIDmode, cc_reg, |
2199 | gen_rtx_COMPARE (mode, x, y))); | |
c85f7c16 | 2200 | |
e0d80184 DM |
2201 | return cc_reg; |
2202 | } | |
c85f7c16 | 2203 | |
e0d80184 DM |
2204 | /* This function is used for v9 only. |
2205 | CODE is the code for an Scc's comparison. | |
2206 | OPERANDS[0] is the target of the Scc insn. | |
2207 | OPERANDS[1] is the value we compare against const0_rtx (which hasn't | |
2208 | been generated yet). | |
c85f7c16 | 2209 | |
e0d80184 | 2210 | This function is needed to turn |
ab835497 | 2211 | |
e0d80184 DM |
2212 | (set (reg:SI 110) |
2213 | (gt (reg:CCX 100 %icc) | |
2214 | (const_int 0))) | |
2215 | into | |
2216 | (set (reg:SI 110) | |
2217 | (gt:DI (reg:CCX 100 %icc) | |
2218 | (const_int 0))) | |
2219 | ||
2220 | IE: The instruction recognizer needs to see the mode of the comparison to | |
2221 | find the right instruction. We could use "gt:DI" right in the | |
2222 | define_expand, but leaving it out allows us to handle DI, SI, etc. | |
ab835497 | 2223 | |
e0d80184 DM |
2224 | We refer to the global sparc compare operands sparc_compare_op0 and |
2225 | sparc_compare_op1. */ | |
ab835497 RK |
2226 | |
2227 | int | |
e0d80184 DM |
2228 | gen_v9_scc (compare_code, operands) |
2229 | enum rtx_code compare_code; | |
2230 | register rtx *operands; | |
ab835497 | 2231 | { |
e0d80184 | 2232 | rtx temp, op0, op1; |
ab835497 | 2233 | |
e0d80184 DM |
2234 | if (! TARGET_ARCH64 |
2235 | && (GET_MODE (sparc_compare_op0) == DImode | |
2236 | || GET_MODE (operands[0]) == DImode)) | |
2237 | return 0; | |
7e2feebf | 2238 | |
e0d80184 DM |
2239 | /* Handle the case where operands[0] == sparc_compare_op0. |
2240 | We "early clobber" the result. */ | |
2241 | if (REGNO (operands[0]) == REGNO (sparc_compare_op0)) | |
ab835497 | 2242 | { |
e0d80184 DM |
2243 | op0 = gen_reg_rtx (GET_MODE (sparc_compare_op0)); |
2244 | emit_move_insn (op0, sparc_compare_op0); | |
ab835497 | 2245 | } |
e0d80184 DM |
2246 | else |
2247 | op0 = sparc_compare_op0; | |
2248 | /* For consistency in the following. */ | |
2249 | op1 = sparc_compare_op1; | |
2250 | ||
2251 | /* Try to use the movrCC insns. */ | |
2252 | if (TARGET_ARCH64 | |
2253 | && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT | |
2254 | && op1 == const0_rtx | |
2255 | && v9_regcmp_p (compare_code)) | |
ab835497 | 2256 | { |
e0d80184 DM |
2257 | /* Special case for op0 != 0. This can be done with one instruction if |
2258 | operands[0] == sparc_compare_op0. We don't assume they are equal | |
2259 | now though. */ | |
2260 | ||
2261 | if (compare_code == NE | |
2262 | && GET_MODE (operands[0]) == DImode | |
2263 | && GET_MODE (op0) == DImode) | |
ab835497 | 2264 | { |
e0d80184 DM |
2265 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], op0)); |
2266 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], | |
2267 | gen_rtx_IF_THEN_ELSE (DImode, | |
2268 | gen_rtx_fmt_ee (compare_code, DImode, | |
2269 | op0, const0_rtx), | |
2270 | const1_rtx, | |
2271 | operands[0]))); | |
ab835497 RK |
2272 | return 1; |
2273 | } | |
e0d80184 DM |
2274 | |
2275 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], const0_rtx)); | |
2276 | if (GET_MODE (op0) != DImode) | |
ab835497 | 2277 | { |
e0d80184 DM |
2278 | temp = gen_reg_rtx (DImode); |
2279 | convert_move (temp, op0, 0); | |
ab835497 | 2280 | } |
e0d80184 DM |
2281 | else |
2282 | temp = op0; | |
2283 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], | |
2284 | gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]), | |
2285 | gen_rtx_fmt_ee (compare_code, DImode, | |
2286 | temp, const0_rtx), | |
2287 | const1_rtx, | |
2288 | operands[0]))); | |
95726648 DE |
2289 | return 1; |
2290 | } | |
e0d80184 | 2291 | else |
ab835497 | 2292 | { |
e0d80184 | 2293 | operands[1] = gen_compare_reg (compare_code, op0, op1); |
ab835497 | 2294 | |
e0d80184 | 2295 | switch (GET_MODE (operands[1])) |
ab835497 | 2296 | { |
e0d80184 DM |
2297 | case CCmode : |
2298 | case CCXmode : | |
2299 | case CCFPEmode : | |
2300 | case CCFPmode : | |
2301 | break; | |
2302 | default : | |
2303 | abort (); | |
ab835497 | 2304 | } |
e0d80184 DM |
2305 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], const0_rtx)); |
2306 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], | |
2307 | gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]), | |
2308 | gen_rtx_fmt_ee (compare_code, | |
2309 | GET_MODE (operands[1]), | |
2310 | operands[1], const0_rtx), | |
2311 | const1_rtx, operands[0]))); | |
2312 | return 1; | |
ab835497 | 2313 | } |
ab835497 | 2314 | } |
4fb4e4b8 | 2315 | |
e0d80184 DM |
2316 | /* Emit a conditional jump insn for the v9 architecture using comparison code |
2317 | CODE and jump target LABEL. | |
2318 | This function exists to take advantage of the v9 brxx insns. */ | |
ab835497 | 2319 | |
e0d80184 DM |
2320 | void |
2321 | emit_v9_brxx_insn (code, op0, label) | |
2322 | enum rtx_code code; | |
2323 | rtx op0, label; | |
ab835497 | 2324 | { |
e0d80184 DM |
2325 | emit_jump_insn (gen_rtx_SET (VOIDmode, |
2326 | pc_rtx, | |
2327 | gen_rtx_IF_THEN_ELSE (VOIDmode, | |
2328 | gen_rtx_fmt_ee (code, GET_MODE (op0), | |
2329 | op0, const0_rtx), | |
2330 | gen_rtx_LABEL_REF (VOIDmode, label), | |
2331 | pc_rtx))); | |
2332 | } | |
7b1ac798 JJ |
2333 | |
2334 | /* Generate a DFmode part of a hard TFmode register. | |
2335 | REG is the TFmode hard register, LOW is 1 for the | |
2336 | low 64bit of the register and 0 otherwise. | |
2337 | */ | |
2338 | rtx | |
2339 | gen_df_reg (reg, low) | |
2340 | rtx reg; | |
2341 | int low; | |
2342 | { | |
2343 | int regno = REGNO (reg); | |
2344 | ||
2345 | if ((WORDS_BIG_ENDIAN == 0) ^ (low != 0)) | |
2aac41d6 | 2346 | regno += (TARGET_ARCH64 && regno < 32) ? 1 : 2; |
7b1ac798 JJ |
2347 | return gen_rtx_REG (DFmode, regno); |
2348 | } | |
e0d80184 DM |
2349 | \f |
2350 | /* Return nonzero if a return peephole merging return with | |
2351 | setting of output register is ok. */ | |
2352 | int | |
2353 | leaf_return_peephole_ok () | |
2354 | { | |
2355 | return (actual_fsize == 0); | |
2356 | } | |
284d86e9 | 2357 | |
e0d80184 DM |
2358 | /* Return nonzero if TRIAL can go into the function epilogue's |
2359 | delay slot. SLOT is the slot we are trying to fill. */ | |
ab835497 | 2360 | |
e0d80184 DM |
2361 | int |
2362 | eligible_for_epilogue_delay (trial, slot) | |
2363 | rtx trial; | |
2364 | int slot; | |
2365 | { | |
2366 | rtx pat, src; | |
4fb4e4b8 | 2367 | |
e0d80184 DM |
2368 | if (slot >= 1) |
2369 | return 0; | |
4fb4e4b8 | 2370 | |
e0d80184 DM |
2371 | if (GET_CODE (trial) != INSN || GET_CODE (PATTERN (trial)) != SET) |
2372 | return 0; | |
4fb4e4b8 | 2373 | |
e0d80184 DM |
2374 | if (get_attr_length (trial) != 1) |
2375 | return 0; | |
4fb4e4b8 | 2376 | |
e48addee JJ |
2377 | /* If there are any call-saved registers, we should scan TRIAL if it |
2378 | does not reference them. For now just make it easy. */ | |
2379 | if (num_gfregs) | |
2380 | return 0; | |
4fb4e4b8 | 2381 | |
e0d80184 DM |
2382 | /* In the case of a true leaf function, anything can go into the delay slot. |
2383 | A delay slot only exists however if the frame size is zero, otherwise | |
2384 | we will put an insn to adjust the stack after the return. */ | |
54ff41b7 | 2385 | if (current_function_uses_only_leaf_regs) |
4fb4e4b8 | 2386 | { |
e0d80184 DM |
2387 | if (leaf_return_peephole_ok ()) |
2388 | return ((get_attr_in_uncond_branch_delay (trial) | |
2389 | == IN_BRANCH_DELAY_TRUE)); | |
2390 | return 0; | |
4fb4e4b8 | 2391 | } |
4fb4e4b8 | 2392 | |
e0d80184 | 2393 | pat = PATTERN (trial); |
795068a4 | 2394 | |
e0d80184 | 2395 | /* Otherwise, only operations which can be done in tandem with |
e48addee | 2396 | a `restore' or `return' insn can go into the delay slot. */ |
e0d80184 | 2397 | if (GET_CODE (SET_DEST (pat)) != REG |
e0d80184 DM |
2398 | || REGNO (SET_DEST (pat)) < 24) |
2399 | return 0; | |
795068a4 | 2400 | |
c137830f JJ |
2401 | /* If this instruction sets up floating point register and we have a return |
2402 | instruction, it can probably go in. But restore will not work | |
2403 | with FP_REGS. */ | |
2404 | if (REGNO (SET_DEST (pat)) >= 32) | |
2405 | { | |
2406 | if (TARGET_V9 && ! epilogue_renumber (&pat, 1) | |
2407 | && (get_attr_in_uncond_branch_delay (trial) == IN_BRANCH_DELAY_TRUE)) | |
2408 | return 1; | |
2409 | return 0; | |
2410 | } | |
2411 | ||
e0d80184 DM |
2412 | /* The set of insns matched here must agree precisely with the set of |
2413 | patterns paired with a RETURN in sparc.md. */ | |
795068a4 | 2414 | |
e0d80184 | 2415 | src = SET_SRC (pat); |
795068a4 | 2416 | |
3c6088d2 | 2417 | /* This matches "*return_[qhs]i" or even "*return_di" on TARGET_ARCH64. */ |
e0d80184 | 2418 | if (arith_operand (src, GET_MODE (src))) |
3c6088d2 JJ |
2419 | { |
2420 | if (TARGET_ARCH64) | |
2421 | return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode); | |
2422 | else | |
2423 | return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (SImode); | |
2424 | } | |
e48addee | 2425 | |
e0d80184 DM |
2426 | /* This matches "*return_di". */ |
2427 | else if (arith_double_operand (src, GET_MODE (src))) | |
2428 | return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode); | |
795068a4 | 2429 | |
e0d80184 DM |
2430 | /* This matches "*return_sf_no_fpu". */ |
2431 | else if (! TARGET_FPU && restore_operand (SET_DEST (pat), SFmode) | |
2432 | && register_operand (src, SFmode)) | |
2433 | return 1; | |
f5da225e | 2434 | |
e48addee JJ |
2435 | /* If we have return instruction, anything that does not use |
2436 | local or output registers and can go into a delay slot wins. */ | |
2437 | else if (TARGET_V9 && ! epilogue_renumber (&pat, 1) | |
2438 | && (get_attr_in_uncond_branch_delay (trial) == IN_BRANCH_DELAY_TRUE)) | |
2439 | return 1; | |
2440 | ||
e0d80184 DM |
2441 | /* This matches "*return_addsi". */ |
2442 | else if (GET_CODE (src) == PLUS | |
2443 | && arith_operand (XEXP (src, 0), SImode) | |
2444 | && arith_operand (XEXP (src, 1), SImode) | |
2445 | && (register_operand (XEXP (src, 0), SImode) | |
2446 | || register_operand (XEXP (src, 1), SImode))) | |
2447 | return 1; | |
2448 | ||
2449 | /* This matches "*return_adddi". */ | |
2450 | else if (GET_CODE (src) == PLUS | |
2451 | && arith_double_operand (XEXP (src, 0), DImode) | |
2452 | && arith_double_operand (XEXP (src, 1), DImode) | |
2453 | && (register_operand (XEXP (src, 0), DImode) | |
2454 | || register_operand (XEXP (src, 1), DImode))) | |
795068a4 | 2455 | return 1; |
795068a4 | 2456 | |
e48addee JJ |
2457 | /* This can match "*return_losum_[sd]i". |
2458 | Catch only some cases, so that return_losum* don't have | |
2459 | to be too big. */ | |
2460 | else if (GET_CODE (src) == LO_SUM | |
2461 | && ! TARGET_CM_MEDMID | |
2462 | && ((register_operand (XEXP (src, 0), SImode) | |
2463 | && immediate_operand (XEXP (src, 1), SImode)) | |
2464 | || (TARGET_ARCH64 | |
2465 | && register_operand (XEXP (src, 0), DImode) | |
2466 | && immediate_operand (XEXP (src, 1), DImode)))) | |
2467 | return 1; | |
2468 | ||
2469 | /* sll{,x} reg,1,reg2 is add reg,reg,reg2 as well. */ | |
2470 | else if (GET_CODE (src) == ASHIFT | |
2471 | && (register_operand (XEXP (src, 0), SImode) | |
2472 | || register_operand (XEXP (src, 0), DImode)) | |
2473 | && XEXP (src, 1) == const1_rtx) | |
2474 | return 1; | |
2475 | ||
795068a4 JW |
2476 | return 0; |
2477 | } | |
2478 | ||
7d167afd JJ |
2479 | /* Return nonzero if TRIAL can go into the sibling call |
2480 | delay slot. */ | |
2481 | ||
2482 | int | |
2483 | eligible_for_sibcall_delay (trial) | |
2484 | rtx trial; | |
2485 | { | |
2486 | rtx pat, src; | |
2487 | ||
2488 | if (GET_CODE (trial) != INSN || GET_CODE (PATTERN (trial)) != SET) | |
2489 | return 0; | |
2490 | ||
2491 | if (get_attr_length (trial) != 1 || profile_block_flag == 2) | |
2492 | return 0; | |
2493 | ||
2494 | pat = PATTERN (trial); | |
2495 | ||
2496 | if (current_function_uses_only_leaf_regs) | |
2497 | { | |
2498 | /* If the tail call is done using the call instruction, | |
2499 | we have to restore %o7 in the delay slot. */ | |
2500 | if (TARGET_ARCH64 && ! TARGET_CM_MEDLOW) | |
2501 | return 0; | |
2502 | ||
2503 | /* %g1 is used to build the function address */ | |
2504 | if (reg_mentioned_p (gen_rtx_REG (Pmode, 1), pat)) | |
2505 | return 0; | |
2506 | ||
2507 | return 1; | |
2508 | } | |
2509 | ||
2510 | /* Otherwise, only operations which can be done in tandem with | |
2511 | a `restore' insn can go into the delay slot. */ | |
2512 | if (GET_CODE (SET_DEST (pat)) != REG | |
2513 | || REGNO (SET_DEST (pat)) < 24 | |
2514 | || REGNO (SET_DEST (pat)) >= 32) | |
2515 | return 0; | |
2516 | ||
2517 | /* If it mentions %o7, it can't go in, because sibcall will clobber it | |
2518 | in most cases. */ | |
2519 | if (reg_mentioned_p (gen_rtx_REG (Pmode, 15), pat)) | |
2520 | return 0; | |
2521 | ||
2522 | src = SET_SRC (pat); | |
2523 | ||
2524 | if (arith_operand (src, GET_MODE (src))) | |
2525 | { | |
2526 | if (TARGET_ARCH64) | |
2527 | return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode); | |
2528 | else | |
2529 | return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (SImode); | |
2530 | } | |
2531 | ||
2532 | else if (arith_double_operand (src, GET_MODE (src))) | |
2533 | return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode); | |
2534 | ||
2535 | else if (! TARGET_FPU && restore_operand (SET_DEST (pat), SFmode) | |
2536 | && register_operand (src, SFmode)) | |
2537 | return 1; | |
2538 | ||
2539 | else if (GET_CODE (src) == PLUS | |
2540 | && arith_operand (XEXP (src, 0), SImode) | |
2541 | && arith_operand (XEXP (src, 1), SImode) | |
2542 | && (register_operand (XEXP (src, 0), SImode) | |
2543 | || register_operand (XEXP (src, 1), SImode))) | |
2544 | return 1; | |
2545 | ||
2546 | else if (GET_CODE (src) == PLUS | |
2547 | && arith_double_operand (XEXP (src, 0), DImode) | |
2548 | && arith_double_operand (XEXP (src, 1), DImode) | |
2549 | && (register_operand (XEXP (src, 0), DImode) | |
2550 | || register_operand (XEXP (src, 1), DImode))) | |
2551 | return 1; | |
2552 | ||
2553 | else if (GET_CODE (src) == LO_SUM | |
2554 | && ! TARGET_CM_MEDMID | |
2555 | && ((register_operand (XEXP (src, 0), SImode) | |
2556 | && immediate_operand (XEXP (src, 1), SImode)) | |
2557 | || (TARGET_ARCH64 | |
2558 | && register_operand (XEXP (src, 0), DImode) | |
2559 | && immediate_operand (XEXP (src, 1), DImode)))) | |
2560 | return 1; | |
2561 | ||
2562 | else if (GET_CODE (src) == ASHIFT | |
2563 | && (register_operand (XEXP (src, 0), SImode) | |
2564 | || register_operand (XEXP (src, 0), DImode)) | |
2565 | && XEXP (src, 1) == const1_rtx) | |
2566 | return 1; | |
2567 | ||
2568 | return 0; | |
2569 | } | |
2570 | ||
e0d80184 DM |
2571 | static int |
2572 | check_return_regs (x) | |
2573 | rtx x; | |
ab835497 | 2574 | { |
e0d80184 DM |
2575 | switch (GET_CODE (x)) |
2576 | { | |
2577 | case REG: | |
2578 | return IN_OR_GLOBAL_P (x); | |
ab835497 | 2579 | |
e0d80184 DM |
2580 | case CONST_INT: |
2581 | case CONST_DOUBLE: | |
2582 | case CONST: | |
2583 | case SYMBOL_REF: | |
2584 | case LABEL_REF: | |
2585 | return 1; | |
ab835497 | 2586 | |
e0d80184 DM |
2587 | case SET: |
2588 | case IOR: | |
2589 | case AND: | |
2590 | case XOR: | |
2591 | case PLUS: | |
2592 | case MINUS: | |
2593 | if (check_return_regs (XEXP (x, 1)) == 0) | |
2594 | return 0; | |
2595 | case NOT: | |
2596 | case NEG: | |
2597 | case MEM: | |
2598 | return check_return_regs (XEXP (x, 0)); | |
2599 | ||
2600 | default: | |
2601 | return 0; | |
2602 | } | |
ab835497 | 2603 | |
e0d80184 | 2604 | } |
ab835497 | 2605 | |
e0d80184 DM |
2606 | /* Return 1 if TRIAL references only in and global registers. */ |
2607 | int | |
2608 | eligible_for_return_delay (trial) | |
2609 | rtx trial; | |
2610 | { | |
2611 | if (GET_CODE (PATTERN (trial)) != SET) | |
2612 | return 0; | |
ab835497 | 2613 | |
e0d80184 DM |
2614 | return check_return_regs (PATTERN (trial)); |
2615 | } | |
ab835497 | 2616 | |
e0d80184 DM |
2617 | int |
2618 | short_branch (uid1, uid2) | |
2619 | int uid1, uid2; | |
2620 | { | |
2621 | unsigned int delta = insn_addresses[uid1] - insn_addresses[uid2]; | |
2622 | if (delta + 1024 < 2048) | |
2623 | return 1; | |
2624 | /* warning ("long branch, distance %d", delta); */ | |
2625 | return 0; | |
2626 | } | |
ab835497 | 2627 | |
e0d80184 DM |
2628 | /* Return non-zero if REG is not used after INSN. |
2629 | We assume REG is a reload reg, and therefore does | |
2630 | not live past labels or calls or jumps. */ | |
2631 | int | |
2632 | reg_unused_after (reg, insn) | |
2633 | rtx reg; | |
2634 | rtx insn; | |
2635 | { | |
2636 | enum rtx_code code, prev_code = UNKNOWN; | |
ab835497 | 2637 | |
e0d80184 | 2638 | while ((insn = NEXT_INSN (insn))) |
61a55e8b | 2639 | { |
e0d80184 DM |
2640 | if (prev_code == CALL_INSN && call_used_regs[REGNO (reg)]) |
2641 | return 1; | |
ab835497 | 2642 | |
e0d80184 DM |
2643 | code = GET_CODE (insn); |
2644 | if (GET_CODE (insn) == CODE_LABEL) | |
2645 | return 1; | |
bc961ed7 | 2646 | |
e0d80184 | 2647 | if (GET_RTX_CLASS (code) == 'i') |
61a55e8b | 2648 | { |
e0d80184 DM |
2649 | rtx set = single_set (insn); |
2650 | int in_src = set && reg_overlap_mentioned_p (reg, SET_SRC (set)); | |
2651 | if (set && in_src) | |
2652 | return 0; | |
2653 | if (set && reg_overlap_mentioned_p (reg, SET_DEST (set))) | |
2654 | return 1; | |
2655 | if (set == 0 && reg_overlap_mentioned_p (reg, PATTERN (insn))) | |
2656 | return 0; | |
61a55e8b | 2657 | } |
e0d80184 | 2658 | prev_code = code; |
61a55e8b | 2659 | } |
e0d80184 DM |
2660 | return 1; |
2661 | } | |
2662 | \f | |
2663 | /* The table we use to reference PIC data. */ | |
2664 | static rtx global_offset_table; | |
bc961ed7 | 2665 | |
e0d80184 DM |
2666 | /* The function we use to get at it. */ |
2667 | static rtx get_pc_symbol; | |
2668 | static char get_pc_symbol_name[256]; | |
ab835497 | 2669 | |
e0d80184 | 2670 | /* Ensure that we are not using patterns that are not OK with PIC. */ |
795068a4 | 2671 | |
e0d80184 DM |
2672 | int |
2673 | check_pic (i) | |
2674 | int i; | |
2675 | { | |
2676 | switch (flag_pic) | |
ab835497 | 2677 | { |
e0d80184 | 2678 | case 1: |
1ccbefce RH |
2679 | if (GET_CODE (recog_data.operand[i]) == SYMBOL_REF |
2680 | || (GET_CODE (recog_data.operand[i]) == CONST | |
2681 | && ! (GET_CODE (XEXP (recog_data.operand[i], 0)) == MINUS | |
2682 | && (XEXP (XEXP (recog_data.operand[i], 0), 0) | |
e0d80184 | 2683 | == global_offset_table) |
1ccbefce | 2684 | && (GET_CODE (XEXP (XEXP (recog_data.operand[i], 0), 1)) |
e0d80184 DM |
2685 | == CONST)))) |
2686 | abort (); | |
2687 | case 2: | |
2688 | default: | |
2689 | return 1; | |
ab835497 | 2690 | } |
ab835497 | 2691 | } |
795068a4 | 2692 | |
e0d80184 DM |
2693 | /* Return true if X is an address which needs a temporary register when |
2694 | reloaded while generating PIC code. */ | |
795068a4 | 2695 | |
e0d80184 DM |
2696 | int |
2697 | pic_address_needs_scratch (x) | |
2698 | rtx x; | |
795068a4 | 2699 | { |
e0d80184 DM |
2700 | /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */ |
2701 | if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS | |
2702 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF | |
2703 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT | |
2704 | && ! SMALL_INT (XEXP (XEXP (x, 0), 1))) | |
2705 | return 1; | |
795068a4 | 2706 | |
e0d80184 DM |
2707 | return 0; |
2708 | } | |
795068a4 | 2709 | |
e0d80184 DM |
2710 | /* Legitimize PIC addresses. If the address is already position-independent, |
2711 | we return ORIG. Newly generated position-independent addresses go into a | |
2712 | reg. This is REG if non zero, otherwise we allocate register(s) as | |
2713 | necessary. */ | |
795068a4 | 2714 | |
e0d80184 DM |
2715 | rtx |
2716 | legitimize_pic_address (orig, mode, reg) | |
2717 | rtx orig; | |
2718 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
2719 | rtx reg; | |
2720 | { | |
2721 | if (GET_CODE (orig) == SYMBOL_REF) | |
82d6b402 | 2722 | { |
e0d80184 DM |
2723 | rtx pic_ref, address; |
2724 | rtx insn; | |
82d6b402 | 2725 | |
e0d80184 | 2726 | if (reg == 0) |
82d6b402 | 2727 | { |
e0d80184 DM |
2728 | if (reload_in_progress || reload_completed) |
2729 | abort (); | |
2730 | else | |
2731 | reg = gen_reg_rtx (Pmode); | |
82d6b402 | 2732 | } |
795068a4 | 2733 | |
e0d80184 | 2734 | if (flag_pic == 2) |
4fb4e4b8 | 2735 | { |
e0d80184 DM |
2736 | /* If not during reload, allocate another temp reg here for loading |
2737 | in the address, so that these instructions can be optimized | |
2738 | properly. */ | |
2739 | rtx temp_reg = ((reload_in_progress || reload_completed) | |
2740 | ? reg : gen_reg_rtx (Pmode)); | |
2741 | ||
2742 | /* Must put the SYMBOL_REF inside an UNSPEC here so that cse | |
2743 | won't get confused into thinking that these two instructions | |
2744 | are loading in the true address of the symbol. If in the | |
2745 | future a PIC rtx exists, that should be used instead. */ | |
be3f1ff5 DM |
2746 | if (Pmode == SImode) |
2747 | { | |
2748 | emit_insn (gen_movsi_high_pic (temp_reg, orig)); | |
2749 | emit_insn (gen_movsi_lo_sum_pic (temp_reg, temp_reg, orig)); | |
2750 | } | |
2751 | else | |
2752 | { | |
2753 | emit_insn (gen_movdi_high_pic (temp_reg, orig)); | |
2754 | emit_insn (gen_movdi_lo_sum_pic (temp_reg, temp_reg, orig)); | |
2755 | } | |
e0d80184 | 2756 | address = temp_reg; |
4fb4e4b8 DE |
2757 | } |
2758 | else | |
e0d80184 DM |
2759 | address = orig; |
2760 | ||
2761 | pic_ref = gen_rtx_MEM (Pmode, | |
2762 | gen_rtx_PLUS (Pmode, | |
2763 | pic_offset_table_rtx, address)); | |
2764 | current_function_uses_pic_offset_table = 1; | |
2765 | RTX_UNCHANGING_P (pic_ref) = 1; | |
2766 | insn = emit_move_insn (reg, pic_ref); | |
2767 | /* Put a REG_EQUAL note on this insn, so that it can be optimized | |
2768 | by loop. */ | |
2769 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, orig, | |
2770 | REG_NOTES (insn)); | |
2771 | return reg; | |
795068a4 | 2772 | } |
e0d80184 | 2773 | else if (GET_CODE (orig) == CONST) |
795068a4 | 2774 | { |
e0d80184 | 2775 | rtx base, offset; |
795068a4 | 2776 | |
e0d80184 DM |
2777 | if (GET_CODE (XEXP (orig, 0)) == PLUS |
2778 | && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx) | |
2779 | return orig; | |
82d6b402 | 2780 | |
e0d80184 | 2781 | if (reg == 0) |
4fb4e4b8 | 2782 | { |
e0d80184 DM |
2783 | if (reload_in_progress || reload_completed) |
2784 | abort (); | |
2785 | else | |
2786 | reg = gen_reg_rtx (Pmode); | |
4fb4e4b8 | 2787 | } |
e0d80184 DM |
2788 | |
2789 | if (GET_CODE (XEXP (orig, 0)) == PLUS) | |
4fb4e4b8 | 2790 | { |
e0d80184 DM |
2791 | base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg); |
2792 | offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode, | |
2793 | base == reg ? 0 : reg); | |
4fb4e4b8 DE |
2794 | } |
2795 | else | |
61a66555 JW |
2796 | abort (); |
2797 | ||
e0d80184 DM |
2798 | if (GET_CODE (offset) == CONST_INT) |
2799 | { | |
2800 | if (SMALL_INT (offset)) | |
2801 | return plus_constant_for_output (base, INTVAL (offset)); | |
2802 | else if (! reload_in_progress && ! reload_completed) | |
2803 | offset = force_reg (Pmode, offset); | |
2804 | else | |
2805 | /* If we reach here, then something is seriously wrong. */ | |
2806 | abort (); | |
2807 | } | |
2808 | return gen_rtx_PLUS (Pmode, base, offset); | |
795068a4 | 2809 | } |
e0d80184 DM |
2810 | else if (GET_CODE (orig) == LABEL_REF) |
2811 | /* ??? Why do we do this? */ | |
2812 | /* Now movsi_pic_label_ref uses it, but we ought to be checking that | |
2813 | the register is live instead, in case it is eliminated. */ | |
2814 | current_function_uses_pic_offset_table = 1; | |
795068a4 | 2815 | |
e0d80184 DM |
2816 | return orig; |
2817 | } | |
795068a4 | 2818 | |
e0d80184 DM |
2819 | /* Return the RTX for insns to set the PIC register. */ |
2820 | ||
2821 | static rtx | |
2822 | pic_setup_code () | |
2823 | { | |
2824 | rtx seq; | |
2825 | ||
2826 | start_sequence (); | |
2827 | emit_insn (gen_get_pc (pic_offset_table_rtx, global_offset_table, | |
2828 | get_pc_symbol)); | |
2829 | seq = gen_sequence (); | |
2830 | end_sequence (); | |
82d6b402 | 2831 | |
e0d80184 DM |
2832 | return seq; |
2833 | } | |
795068a4 | 2834 | |
e0d80184 | 2835 | /* Emit special PIC prologues and epilogues. */ |
795068a4 | 2836 | |
e0d80184 DM |
2837 | void |
2838 | finalize_pic () | |
2839 | { | |
2840 | /* Labels to get the PC in the prologue of this function. */ | |
2841 | int orig_flag_pic = flag_pic; | |
2842 | rtx insn; | |
4fb4e4b8 | 2843 | |
e0d80184 DM |
2844 | if (current_function_uses_pic_offset_table == 0) |
2845 | return; | |
795068a4 | 2846 | |
e0d80184 DM |
2847 | if (! flag_pic) |
2848 | abort (); | |
2849 | ||
2850 | /* If we havn't emitted the special get_pc helper function, do so now. */ | |
2851 | if (get_pc_symbol_name[0] == 0) | |
4fb4e4b8 | 2852 | { |
d676da68 | 2853 | int align; |
82d6b402 | 2854 | |
d676da68 | 2855 | ASM_GENERATE_INTERNAL_LABEL (get_pc_symbol_name, "LGETPC", 0); |
e0d80184 | 2856 | text_section (); |
d676da68 DM |
2857 | |
2858 | align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT); | |
2859 | if (align > 0) | |
2860 | ASM_OUTPUT_ALIGN (asm_out_file, align); | |
e0d80184 DM |
2861 | ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "LGETPC", 0); |
2862 | fputs ("\tretl\n\tadd %o7,%l7,%l7\n", asm_out_file); | |
2863 | } | |
82d6b402 | 2864 | |
e0d80184 DM |
2865 | /* Initialize every time through, since we can't easily |
2866 | know this to be permanent. */ | |
2867 | global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_"); | |
2868 | get_pc_symbol = gen_rtx_SYMBOL_REF (Pmode, get_pc_symbol_name); | |
2869 | flag_pic = 0; | |
82d6b402 | 2870 | |
e0d80184 | 2871 | emit_insn_after (pic_setup_code (), get_insns ()); |
82d6b402 | 2872 | |
24a43d7b DM |
2873 | /* Insert the code in each nonlocal goto receiver. |
2874 | If you make changes here or to the nonlocal_goto_receiver | |
2875 | pattern, make sure the unspec_volatile numbers still | |
2876 | match. */ | |
e0d80184 DM |
2877 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) |
2878 | if (GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == UNSPEC_VOLATILE | |
24a43d7b | 2879 | && XINT (PATTERN (insn), 1) == 5) |
e0d80184 | 2880 | emit_insn_after (pic_setup_code (), insn); |
82d6b402 | 2881 | |
e0d80184 | 2882 | flag_pic = orig_flag_pic; |
82d6b402 | 2883 | |
e0d80184 DM |
2884 | /* Need to emit this whether or not we obey regdecls, |
2885 | since setjmp/longjmp can cause life info to screw up. | |
2886 | ??? In the case where we don't obey regdecls, this is not sufficient | |
2887 | since we may not fall out the bottom. */ | |
2888 | emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx)); | |
795068a4 | 2889 | } |
ab835497 | 2890 | \f |
e0d80184 DM |
2891 | /* Return 1 if RTX is a MEM which is known to be aligned to at |
2892 | least an 8 byte boundary. */ | |
a3ee5899 | 2893 | |
e0d80184 DM |
2894 | int |
2895 | mem_min_alignment (mem, desired) | |
2896 | rtx mem; | |
2897 | int desired; | |
ab835497 | 2898 | { |
e0d80184 DM |
2899 | rtx addr, base, offset; |
2900 | ||
2901 | /* If it's not a MEM we can't accept it. */ | |
2902 | if (GET_CODE (mem) != MEM) | |
2903 | return 0; | |
2904 | ||
2905 | addr = XEXP (mem, 0); | |
2906 | base = offset = NULL_RTX; | |
2907 | if (GET_CODE (addr) == PLUS) | |
ab835497 | 2908 | { |
e0d80184 | 2909 | if (GET_CODE (XEXP (addr, 0)) == REG) |
61a55e8b | 2910 | { |
e0d80184 DM |
2911 | base = XEXP (addr, 0); |
2912 | ||
2913 | /* What we are saying here is that if the base | |
2914 | REG is aligned properly, the compiler will make | |
2915 | sure any REG based index upon it will be so | |
2916 | as well. */ | |
2917 | if (GET_CODE (XEXP (addr, 1)) == CONST_INT) | |
2918 | offset = XEXP (addr, 1); | |
61a55e8b | 2919 | else |
e0d80184 | 2920 | offset = const0_rtx; |
61a55e8b | 2921 | } |
ab835497 | 2922 | } |
e0d80184 | 2923 | else if (GET_CODE (addr) == REG) |
ab835497 | 2924 | { |
e0d80184 DM |
2925 | base = addr; |
2926 | offset = const0_rtx; | |
ab835497 | 2927 | } |
82d6b402 | 2928 | |
e0d80184 | 2929 | if (base != NULL_RTX) |
795068a4 | 2930 | { |
e0d80184 DM |
2931 | int regno = REGNO (base); |
2932 | ||
2933 | if (regno != FRAME_POINTER_REGNUM | |
2934 | && regno != STACK_POINTER_REGNUM) | |
61a55e8b | 2935 | { |
e0d80184 DM |
2936 | /* Check if the compiler has recorded some information |
2937 | about the alignment of the base REG. If reload has | |
021e2ecc JJ |
2938 | completed, we already matched with proper alignments. |
2939 | If not running global_alloc, reload might give us | |
2940 | unaligned pointer to local stack though. */ | |
01d939e8 | 2941 | if (((cfun != 0 && REGNO_POINTER_ALIGN (regno) >= desired) |
021e2ecc | 2942 | || (optimize && reload_completed)) |
e0d80184 DM |
2943 | && ((INTVAL (offset) & (desired - 1)) == 0)) |
2944 | return 1; | |
61a55e8b | 2945 | } |
795068a4 | 2946 | else |
e0d80184 DM |
2947 | { |
2948 | if (((INTVAL (offset) - SPARC_STACK_BIAS) & (desired - 1)) == 0) | |
2949 | return 1; | |
2950 | } | |
795068a4 | 2951 | } |
e0d80184 DM |
2952 | else if (! TARGET_UNALIGNED_DOUBLES |
2953 | || CONSTANT_P (addr) | |
2954 | || GET_CODE (addr) == LO_SUM) | |
795068a4 | 2955 | { |
e0d80184 DM |
2956 | /* Anything else we know is properly aligned unless TARGET_UNALIGNED_DOUBLES |
2957 | is true, in which case we can only assume that an access is aligned if | |
2958 | it is to a constant address, or the address involves a LO_SUM. */ | |
2959 | return 1; | |
795068a4 | 2960 | } |
e0d80184 DM |
2961 | |
2962 | /* An obviously unaligned address. */ | |
2963 | return 0; | |
795068a4 | 2964 | } |
e0d80184 | 2965 | |
ab835497 | 2966 | \f |
61a55e8b DE |
2967 | /* Vectors to keep interesting information about registers where it can easily |
2968 | be got. We use to use the actual mode value as the bit number, but there | |
2969 | are more than 32 modes now. Instead we use two tables: one indexed by | |
2970 | hard register number, and one indexed by mode. */ | |
2971 | ||
2972 | /* The purpose of sparc_mode_class is to shrink the range of modes so that | |
2973 | they all fit (as bit numbers) in a 32 bit word (again). Each real mode is | |
2974 | mapped into one sparc_mode_class mode. */ | |
2975 | ||
2976 | enum sparc_mode_class { | |
61a55e8b | 2977 | S_MODE, D_MODE, T_MODE, O_MODE, |
c4ce6853 DE |
2978 | SF_MODE, DF_MODE, TF_MODE, OF_MODE, |
2979 | CC_MODE, CCFP_MODE | |
61a55e8b | 2980 | }; |
ab835497 | 2981 | |
61a55e8b DE |
2982 | /* Modes for single-word and smaller quantities. */ |
2983 | #define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE)) | |
2984 | ||
2985 | /* Modes for double-word and smaller quantities. */ | |
2986 | #define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE)) | |
2987 | ||
2988 | /* Modes for quad-word and smaller quantities. */ | |
2989 | #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE)) | |
ab835497 | 2990 | |
d0cee9ba JJ |
2991 | /* Modes for 8-word and smaller quantities. */ |
2992 | #define O_MODES (T_MODES | (1 << (int) O_MODE) | (1 << (int) OF_MODE)) | |
2993 | ||
1e4eb8d1 JW |
2994 | /* Modes for single-float quantities. We must allow any single word or |
2995 | smaller quantity. This is because the fix/float conversion instructions | |
2996 | take integer inputs/outputs from the float registers. */ | |
2997 | #define SF_MODES (S_MODES) | |
ab835497 | 2998 | |
61a55e8b DE |
2999 | /* Modes for double-float and smaller quantities. */ |
3000 | #define DF_MODES (S_MODES | D_MODES) | |
3001 | ||
61a55e8b | 3002 | /* Modes for double-float only quantities. */ |
d0cee9ba | 3003 | #define DF_MODES_NO_S (D_MODES) |
ab835497 | 3004 | |
61a55e8b DE |
3005 | /* Modes for quad-float only quantities. */ |
3006 | #define TF_ONLY_MODES (1 << (int) TF_MODE) | |
3007 | ||
3008 | /* Modes for quad-float and smaller quantities. */ | |
3009 | #define TF_MODES (DF_MODES | TF_ONLY_MODES) | |
3010 | ||
d0cee9ba JJ |
3011 | /* Modes for quad-float and double-float quantities. */ |
3012 | #define TF_MODES_NO_S (DF_MODES_NO_S | TF_ONLY_MODES) | |
3013 | ||
3014 | /* Modes for quad-float pair only quantities. */ | |
3015 | #define OF_ONLY_MODES (1 << (int) OF_MODE) | |
3016 | ||
3017 | /* Modes for quad-float pairs and smaller quantities. */ | |
3018 | #define OF_MODES (TF_MODES | OF_ONLY_MODES) | |
3019 | ||
3020 | #define OF_MODES_NO_S (TF_MODES_NO_S | OF_ONLY_MODES) | |
ab835497 | 3021 | |
c4ce6853 DE |
3022 | /* Modes for condition codes. */ |
3023 | #define CC_MODES (1 << (int) CC_MODE) | |
3024 | #define CCFP_MODES (1 << (int) CCFP_MODE) | |
3025 | ||
ab835497 RK |
3026 | /* Value is 1 if register/mode pair is acceptable on sparc. |
3027 | The funny mixture of D and T modes is because integer operations | |
3028 | do not specially operate on tetra quantities, so non-quad-aligned | |
3029 | registers can hold quadword quantities (except %o4 and %i4 because | |
c4ce6853 | 3030 | they cross fixed registers). */ |
ab835497 | 3031 | |
61a55e8b DE |
3032 | /* This points to either the 32 bit or the 64 bit version. */ |
3033 | int *hard_regno_mode_classes; | |
3034 | ||
3035 | static int hard_32bit_mode_classes[] = { | |
c4ce6853 | 3036 | S_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, |
ab835497 RK |
3037 | T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES, |
3038 | T_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, | |
3039 | T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES, | |
3040 | ||
d0cee9ba JJ |
3041 | OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES, |
3042 | OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES, | |
3043 | OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES, | |
3044 | OF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES, | |
a9e27770 DE |
3045 | |
3046 | /* FP regs f32 to f63. Only the even numbered registers actually exist, | |
3047 | and none can hold SFmode/SImode values. */ | |
d0cee9ba JJ |
3048 | OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, |
3049 | OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, | |
3050 | OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, | |
3051 | OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, TF_MODES_NO_S, 0, DF_MODES_NO_S, 0, | |
a9e27770 DE |
3052 | |
3053 | /* %fcc[0123] */ | |
c4ce6853 DE |
3054 | CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES, |
3055 | ||
3056 | /* %icc */ | |
3057 | CC_MODES | |
61a55e8b DE |
3058 | }; |
3059 | ||
3060 | static int hard_64bit_mode_classes[] = { | |
c4ce6853 | 3061 | D_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, |
d0cee9ba | 3062 | O_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, |
61a55e8b | 3063 | T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, |
d0cee9ba | 3064 | O_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, |
61a55e8b | 3065 | |
d0cee9ba JJ |
3066 | OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES, |
3067 | OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES, | |
3068 | OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES, | |
3069 | OF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES, | |
61a55e8b | 3070 | |
a9e27770 | 3071 | /* FP regs f32 to f63. Only the even numbered registers actually exist, |
61a55e8b | 3072 | and none can hold SFmode/SImode values. */ |
d0cee9ba JJ |
3073 | OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, |
3074 | OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, | |
3075 | OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, | |
3076 | OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, TF_MODES_NO_S, 0, DF_MODES_NO_S, 0, | |
61a55e8b DE |
3077 | |
3078 | /* %fcc[0123] */ | |
c4ce6853 DE |
3079 | CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES, |
3080 | ||
3081 | /* %icc */ | |
3082 | CC_MODES | |
61a55e8b DE |
3083 | }; |
3084 | ||
3085 | int sparc_mode_class [NUM_MACHINE_MODES]; | |
3086 | ||
c4ce6853 DE |
3087 | enum reg_class sparc_regno_reg_class[FIRST_PSEUDO_REGISTER]; |
3088 | ||
61a55e8b DE |
3089 | static void |
3090 | sparc_init_modes () | |
3091 | { | |
3092 | int i; | |
3093 | ||
61a55e8b DE |
3094 | for (i = 0; i < NUM_MACHINE_MODES; i++) |
3095 | { | |
3096 | switch (GET_MODE_CLASS (i)) | |
3097 | { | |
3098 | case MODE_INT: | |
3099 | case MODE_PARTIAL_INT: | |
3100 | case MODE_COMPLEX_INT: | |
3101 | if (GET_MODE_SIZE (i) <= 4) | |
3102 | sparc_mode_class[i] = 1 << (int) S_MODE; | |
3103 | else if (GET_MODE_SIZE (i) == 8) | |
3104 | sparc_mode_class[i] = 1 << (int) D_MODE; | |
3105 | else if (GET_MODE_SIZE (i) == 16) | |
3106 | sparc_mode_class[i] = 1 << (int) T_MODE; | |
3107 | else if (GET_MODE_SIZE (i) == 32) | |
3108 | sparc_mode_class[i] = 1 << (int) O_MODE; | |
3109 | else | |
3110 | sparc_mode_class[i] = 0; | |
3111 | break; | |
3112 | case MODE_FLOAT: | |
3113 | case MODE_COMPLEX_FLOAT: | |
3114 | if (GET_MODE_SIZE (i) <= 4) | |
3115 | sparc_mode_class[i] = 1 << (int) SF_MODE; | |
3116 | else if (GET_MODE_SIZE (i) == 8) | |
3117 | sparc_mode_class[i] = 1 << (int) DF_MODE; | |
3118 | else if (GET_MODE_SIZE (i) == 16) | |
3119 | sparc_mode_class[i] = 1 << (int) TF_MODE; | |
3120 | else if (GET_MODE_SIZE (i) == 32) | |
3121 | sparc_mode_class[i] = 1 << (int) OF_MODE; | |
3122 | else | |
3123 | sparc_mode_class[i] = 0; | |
3124 | break; | |
3125 | case MODE_CC: | |
3126 | default: | |
3127 | /* mode_class hasn't been initialized yet for EXTRA_CC_MODES, so | |
3128 | we must explicitly check for them here. */ | |
3129 | if (i == (int) CCFPmode || i == (int) CCFPEmode) | |
3130 | sparc_mode_class[i] = 1 << (int) CCFP_MODE; | |
3131 | else if (i == (int) CCmode || i == (int) CC_NOOVmode | |
a9e27770 | 3132 | || i == (int) CCXmode || i == (int) CCX_NOOVmode) |
c4ce6853 | 3133 | sparc_mode_class[i] = 1 << (int) CC_MODE; |
61a55e8b DE |
3134 | else |
3135 | sparc_mode_class[i] = 0; | |
3136 | break; | |
3137 | } | |
3138 | } | |
3139 | ||
a9e27770 | 3140 | if (TARGET_ARCH64) |
61a55e8b DE |
3141 | hard_regno_mode_classes = hard_64bit_mode_classes; |
3142 | else | |
3143 | hard_regno_mode_classes = hard_32bit_mode_classes; | |
c4ce6853 DE |
3144 | |
3145 | /* Initialize the array used by REGNO_REG_CLASS. */ | |
3146 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
3147 | { | |
284d86e9 JC |
3148 | if (i < 16 && TARGET_V8PLUS) |
3149 | sparc_regno_reg_class[i] = I64_REGS; | |
3150 | else if (i < 32) | |
c4ce6853 DE |
3151 | sparc_regno_reg_class[i] = GENERAL_REGS; |
3152 | else if (i < 64) | |
3153 | sparc_regno_reg_class[i] = FP_REGS; | |
3154 | else if (i < 96) | |
3155 | sparc_regno_reg_class[i] = EXTRA_FP_REGS; | |
3156 | else if (i < 100) | |
3157 | sparc_regno_reg_class[i] = FPCC_REGS; | |
3158 | else | |
3159 | sparc_regno_reg_class[i] = NO_REGS; | |
3160 | } | |
61a55e8b | 3161 | } |
ab835497 | 3162 | \f |
61a55e8b DE |
3163 | /* Save non call used registers from LOW to HIGH at BASE+OFFSET. |
3164 | N_REGS is the number of 4-byte regs saved thus far. This applies even to | |
3165 | v9 int regs as it simplifies the code. */ | |
3166 | ||
ab835497 | 3167 | static int |
c53aa195 | 3168 | save_regs (file, low, high, base, offset, n_regs, real_offset) |
ab835497 RK |
3169 | FILE *file; |
3170 | int low, high; | |
3bb5de61 | 3171 | const char *base; |
ab835497 | 3172 | int offset; |
61a55e8b | 3173 | int n_regs; |
c53aa195 | 3174 | int real_offset; |
ab835497 RK |
3175 | { |
3176 | int i; | |
3177 | ||
a9e27770 | 3178 | if (TARGET_ARCH64 && high <= 32) |
ab835497 | 3179 | { |
61a55e8b DE |
3180 | for (i = low; i < high; i++) |
3181 | { | |
3182 | if (regs_ever_live[i] && ! call_used_regs[i]) | |
c53aa195 | 3183 | { |
e0d80184 | 3184 | fprintf (file, "\tstx\t%s, [%s+%d]\n", |
c53aa195 | 3185 | reg_names[i], base, offset + 4 * n_regs); |
0021b564 | 3186 | if (dwarf2out_do_frame ()) |
c53aa195 | 3187 | dwarf2out_reg_save ("", i, real_offset + 4 * n_regs); |
c53aa195 JM |
3188 | n_regs += 2; |
3189 | } | |
61a55e8b | 3190 | } |
ab835497 | 3191 | } |
61a55e8b DE |
3192 | else |
3193 | { | |
3194 | for (i = low; i < high; i += 2) | |
3195 | { | |
3196 | if (regs_ever_live[i] && ! call_used_regs[i]) | |
c53aa195 | 3197 | { |
5e9defae KG |
3198 | if (regs_ever_live[i+1] && ! call_used_regs[i+1]) |
3199 | { | |
e0d80184 | 3200 | fprintf (file, "\tstd\t%s, [%s+%d]\n", |
5e9defae KG |
3201 | reg_names[i], base, offset + 4 * n_regs); |
3202 | if (dwarf2out_do_frame ()) | |
3203 | { | |
3204 | char *l = dwarf2out_cfi_label (); | |
3205 | dwarf2out_reg_save (l, i, real_offset + 4 * n_regs); | |
3206 | dwarf2out_reg_save (l, i+1, real_offset + 4 * n_regs + 4); | |
3207 | } | |
3208 | n_regs += 2; | |
3209 | } | |
3210 | else | |
3211 | { | |
e0d80184 | 3212 | fprintf (file, "\tst\t%s, [%s+%d]\n", |
5e9defae KG |
3213 | reg_names[i], base, offset + 4 * n_regs); |
3214 | if (dwarf2out_do_frame ()) | |
3215 | dwarf2out_reg_save ("", i, real_offset + 4 * n_regs); | |
3216 | n_regs += 2; | |
3217 | } | |
3218 | } | |
3219 | else | |
3220 | { | |
3221 | if (regs_ever_live[i+1] && ! call_used_regs[i+1]) | |
3222 | { | |
e0d80184 | 3223 | fprintf (file, "\tst\t%s, [%s+%d]\n", |
5e9defae KG |
3224 | reg_names[i+1], base, offset + 4 * n_regs + 4); |
3225 | if (dwarf2out_do_frame ()) | |
3226 | dwarf2out_reg_save ("", i + 1, real_offset + 4 * n_regs + 4); | |
3227 | n_regs += 2; | |
3228 | } | |
c53aa195 | 3229 | } |
61a55e8b DE |
3230 | } |
3231 | } | |
3232 | return n_regs; | |
ab835497 RK |
3233 | } |
3234 | ||
61a55e8b DE |
3235 | /* Restore non call used registers from LOW to HIGH at BASE+OFFSET. |
3236 | ||
3237 | N_REGS is the number of 4-byte regs saved thus far. This applies even to | |
3238 | v9 int regs as it simplifies the code. */ | |
3239 | ||
ab835497 | 3240 | static int |
61a55e8b | 3241 | restore_regs (file, low, high, base, offset, n_regs) |
ab835497 RK |
3242 | FILE *file; |
3243 | int low, high; | |
3bb5de61 | 3244 | const char *base; |
ab835497 | 3245 | int offset; |
61a55e8b | 3246 | int n_regs; |
ab835497 RK |
3247 | { |
3248 | int i; | |
3249 | ||
a9e27770 | 3250 | if (TARGET_ARCH64 && high <= 32) |
61a55e8b DE |
3251 | { |
3252 | for (i = low; i < high; i++) | |
3253 | { | |
3254 | if (regs_ever_live[i] && ! call_used_regs[i]) | |
e0d80184 | 3255 | fprintf (file, "\tldx\t[%s+%d], %s\n", |
61a55e8b DE |
3256 | base, offset + 4 * n_regs, reg_names[i]), |
3257 | n_regs += 2; | |
3258 | } | |
3259 | } | |
3260 | else | |
ab835497 | 3261 | { |
61a55e8b DE |
3262 | for (i = low; i < high; i += 2) |
3263 | { | |
3264 | if (regs_ever_live[i] && ! call_used_regs[i]) | |
3265 | if (regs_ever_live[i+1] && ! call_used_regs[i+1]) | |
e0d80184 | 3266 | fprintf (file, "\tldd\t[%s+%d], %s\n", |
61a55e8b DE |
3267 | base, offset + 4 * n_regs, reg_names[i]), |
3268 | n_regs += 2; | |
3269 | else | |
e0d80184 | 3270 | fprintf (file, "\tld\t[%s+%d],%s\n", |
61a55e8b DE |
3271 | base, offset + 4 * n_regs, reg_names[i]), |
3272 | n_regs += 2; | |
3273 | else if (regs_ever_live[i+1] && ! call_used_regs[i+1]) | |
e0d80184 | 3274 | fprintf (file, "\tld\t[%s+%d],%s\n", |
61a55e8b DE |
3275 | base, offset + 4 * n_regs + 4, reg_names[i+1]), |
3276 | n_regs += 2; | |
3277 | } | |
ab835497 | 3278 | } |
61a55e8b | 3279 | return n_regs; |
ab835497 RK |
3280 | } |
3281 | ||
61a55e8b DE |
3282 | /* Compute the frame size required by the function. This function is called |
3283 | during the reload pass and also by output_function_prologue(). */ | |
ab835497 | 3284 | |
ab835497 RK |
3285 | int |
3286 | compute_frame_size (size, leaf_function) | |
3287 | int size; | |
3288 | int leaf_function; | |
3289 | { | |
61a55e8b | 3290 | int n_regs = 0, i; |
ab835497 | 3291 | int outgoing_args_size = (current_function_outgoing_args_size |
4fb4e4b8 | 3292 | + REG_PARM_STACK_SPACE (current_function_decl)); |
ab835497 | 3293 | |
61a55e8b | 3294 | if (TARGET_EPILOGUE) |
ab835497 | 3295 | { |
61a55e8b DE |
3296 | /* N_REGS is the number of 4-byte regs saved thus far. This applies |
3297 | even to v9 int regs to be consistent with save_regs/restore_regs. */ | |
3298 | ||
a9e27770 | 3299 | if (TARGET_ARCH64) |
61a55e8b DE |
3300 | { |
3301 | for (i = 0; i < 8; i++) | |
3302 | if (regs_ever_live[i] && ! call_used_regs[i]) | |
3303 | n_regs += 2; | |
3304 | } | |
3305 | else | |
3306 | { | |
3307 | for (i = 0; i < 8; i += 2) | |
3308 | if ((regs_ever_live[i] && ! call_used_regs[i]) | |
3309 | || (regs_ever_live[i+1] && ! call_used_regs[i+1])) | |
3310 | n_regs += 2; | |
3311 | } | |
3312 | ||
3313 | for (i = 32; i < (TARGET_V9 ? 96 : 64); i += 2) | |
ab835497 RK |
3314 | if ((regs_ever_live[i] && ! call_used_regs[i]) |
3315 | || (regs_ever_live[i+1] && ! call_used_regs[i+1])) | |
61a55e8b | 3316 | n_regs += 2; |
ab835497 RK |
3317 | } |
3318 | ||
3319 | /* Set up values for use in `function_epilogue'. */ | |
61a55e8b | 3320 | num_gfregs = n_regs; |
ab835497 | 3321 | |
61a55e8b DE |
3322 | if (leaf_function && n_regs == 0 |
3323 | && size == 0 && current_function_outgoing_args_size == 0) | |
3324 | { | |
3325 | actual_fsize = apparent_fsize = 0; | |
3326 | } | |
3327 | else | |
3328 | { | |
3329 | /* We subtract STARTING_FRAME_OFFSET, remember it's negative. | |
3330 | The stack bias (if any) is taken out to undo its effects. */ | |
3331 | apparent_fsize = (size - STARTING_FRAME_OFFSET + SPARC_STACK_BIAS + 7) & -8; | |
3332 | apparent_fsize += n_regs * 4; | |
3333 | actual_fsize = apparent_fsize + ((outgoing_args_size + 7) & -8); | |
3334 | } | |
ab835497 RK |
3335 | |
3336 | /* Make sure nothing can clobber our register windows. | |
3337 | If a SAVE must be done, or there is a stack-local variable, | |
61a55e8b | 3338 | the register window area must be allocated. |
4fb4e4b8 | 3339 | ??? For v8 we apparently need an additional 8 bytes of reserved space. */ |
ab835497 | 3340 | if (leaf_function == 0 || size > 0) |
4fb4e4b8 | 3341 | actual_fsize += (16 * UNITS_PER_WORD) + (TARGET_ARCH64 ? 0 : 8); |
ab835497 | 3342 | |
61a55e8b DE |
3343 | return SPARC_STACK_ALIGN (actual_fsize); |
3344 | } | |
3345 | ||
3346 | /* Build a (32 bit) big number in a register. */ | |
86735b02 | 3347 | /* ??? We may be able to use the set macro here too. */ |
61a55e8b DE |
3348 | |
3349 | static void | |
3350 | build_big_number (file, num, reg) | |
3351 | FILE *file; | |
3352 | int num; | |
3bb5de61 | 3353 | const char *reg; |
61a55e8b | 3354 | { |
a9e27770 | 3355 | if (num >= 0 || ! TARGET_ARCH64) |
61a55e8b | 3356 | { |
e0d80184 | 3357 | fprintf (file, "\tsethi\t%%hi(%d), %s\n", num, reg); |
61a55e8b | 3358 | if ((num & 0x3ff) != 0) |
e0d80184 | 3359 | fprintf (file, "\tor\t%s, %%lo(%d), %s\n", reg, num, reg); |
61a55e8b | 3360 | } |
a9e27770 | 3361 | else /* num < 0 && TARGET_ARCH64 */ |
61a55e8b DE |
3362 | { |
3363 | /* Sethi does not sign extend, so we must use a little trickery | |
3364 | to use it for negative numbers. Invert the constant before | |
3365 | loading it in, then use xor immediate to invert the loaded bits | |
3366 | (along with the upper 32 bits) to the desired constant. This | |
3367 | works because the sethi and immediate fields overlap. */ | |
3368 | int asize = num; | |
3369 | int inv = ~asize; | |
3370 | int low = -0x400 + (asize & 0x3FF); | |
3371 | ||
e0d80184 | 3372 | fprintf (file, "\tsethi\t%%hi(%d), %s\n\txor\t%s, %d, %s\n", |
61a55e8b DE |
3373 | inv, reg, reg, low, reg); |
3374 | } | |
ab835497 RK |
3375 | } |
3376 | ||
1cb36a98 RH |
3377 | /* Output any necessary .register pseudo-ops. */ |
3378 | void | |
3379 | sparc_output_scratch_registers (file) | |
fbd039b2 | 3380 | FILE *file ATTRIBUTE_UNUSED; |
1cb36a98 RH |
3381 | { |
3382 | #ifdef HAVE_AS_REGISTER_PSEUDO_OP | |
3383 | int i; | |
3384 | ||
3385 | if (TARGET_ARCH32) | |
3386 | return; | |
3387 | ||
3388 | /* Check if %g[2367] were used without | |
3389 | .register being printed for them already. */ | |
3390 | for (i = 2; i < 8; i++) | |
3391 | { | |
3392 | if (regs_ever_live [i] | |
3393 | && ! sparc_hard_reg_printed [i]) | |
3394 | { | |
3395 | sparc_hard_reg_printed [i] = 1; | |
3396 | fprintf (file, "\t.register\t%%g%d, #scratch\n", i); | |
3397 | } | |
3398 | if (i == 3) i = 5; | |
3399 | } | |
3400 | #endif | |
3401 | } | |
3402 | ||
915f619f JW |
3403 | /* Output code for the function prologue. */ |
3404 | ||
ab835497 RK |
3405 | void |
3406 | output_function_prologue (file, size, leaf_function) | |
3407 | FILE *file; | |
3408 | int size; | |
915f619f | 3409 | int leaf_function; |
ab835497 | 3410 | { |
1cb36a98 RH |
3411 | sparc_output_scratch_registers (file); |
3412 | ||
915f619f JW |
3413 | /* Need to use actual_fsize, since we are also allocating |
3414 | space for our callee (and our own register save area). */ | |
ab835497 RK |
3415 | actual_fsize = compute_frame_size (size, leaf_function); |
3416 | ||
61a55e8b DE |
3417 | if (leaf_function) |
3418 | { | |
3419 | frame_base_name = "%sp"; | |
3420 | frame_base_offset = actual_fsize + SPARC_STACK_BIAS; | |
3421 | } | |
3422 | else | |
3423 | { | |
3424 | frame_base_name = "%fp"; | |
3425 | frame_base_offset = SPARC_STACK_BIAS; | |
3426 | } | |
3427 | ||
c6aa9ce1 | 3428 | /* This is only for the human reader. */ |
bf62bbf1 | 3429 | fprintf (file, "\t%s#PROLOGUE# 0\n", ASM_COMMENT_START); |
c6aa9ce1 | 3430 | |
915f619f JW |
3431 | if (actual_fsize == 0) |
3432 | /* do nothing. */ ; | |
e6c1be7e | 3433 | else if (! leaf_function) |
ab835497 | 3434 | { |
3592ea0d | 3435 | if (actual_fsize <= 4096) |
e0d80184 | 3436 | fprintf (file, "\tsave\t%%sp, -%d, %%sp\n", actual_fsize); |
3592ea0d | 3437 | else if (actual_fsize <= 8192) |
915f619f | 3438 | { |
e0d80184 DM |
3439 | fprintf (file, "\tsave\t%%sp, -4096, %%sp\n"); |
3440 | fprintf (file, "\tadd\t%%sp, -%d, %%sp\n", actual_fsize - 4096); | |
915f619f JW |
3441 | } |
3442 | else | |
3443 | { | |
3592ea0d | 3444 | build_big_number (file, -actual_fsize, "%g1"); |
e0d80184 | 3445 | fprintf (file, "\tsave\t%%sp, %%g1, %%sp\n"); |
915f619f | 3446 | } |
ab835497 | 3447 | } |
5f4241d5 DE |
3448 | else /* leaf function */ |
3449 | { | |
3592ea0d | 3450 | if (actual_fsize <= 4096) |
e0d80184 | 3451 | fprintf (file, "\tadd\t%%sp, -%d, %%sp\n", actual_fsize); |
3592ea0d DE |
3452 | else if (actual_fsize <= 8192) |
3453 | { | |
e0d80184 DM |
3454 | fprintf (file, "\tadd\t%%sp, -4096, %%sp\n"); |
3455 | fprintf (file, "\tadd\t%%sp, -%d, %%sp\n", actual_fsize - 4096); | |
3592ea0d | 3456 | } |
915f619f | 3457 | else |
3592ea0d DE |
3458 | { |
3459 | build_big_number (file, -actual_fsize, "%g1"); | |
e0d80184 | 3460 | fprintf (file, "\tadd\t%%sp, %%g1, %%sp\n"); |
3592ea0d | 3461 | } |
ab835497 RK |
3462 | } |
3463 | ||
0021b564 | 3464 | if (dwarf2out_do_frame () && actual_fsize) |
c53aa195 | 3465 | { |
96987e96 | 3466 | char *label = dwarf2out_cfi_label (); |
c53aa195 JM |
3467 | |
3468 | /* The canonical frame address refers to the top of the frame. */ | |
3469 | dwarf2out_def_cfa (label, (leaf_function ? STACK_POINTER_REGNUM | |
3470 | : FRAME_POINTER_REGNUM), | |
3471 | frame_base_offset); | |
3472 | ||
3473 | if (! leaf_function) | |
3474 | { | |
3475 | /* Note the register window save. This tells the unwinder that | |
3476 | it needs to restore the window registers from the previous | |
3477 | frame's window save area at 0(cfa). */ | |
3478 | dwarf2out_window_save (label); | |
3479 | ||
3480 | /* The return address (-8) is now in %i7. */ | |
3481 | dwarf2out_return_reg (label, 31); | |
3482 | } | |
3483 | } | |
c53aa195 | 3484 | |
ab835497 RK |
3485 | /* If doing anything with PIC, do it now. */ |
3486 | if (! flag_pic) | |
bf62bbf1 | 3487 | fprintf (file, "\t%s#PROLOGUE# 1\n", ASM_COMMENT_START); |
ab835497 | 3488 | |
61a55e8b DE |
3489 | /* Call saved registers are saved just above the outgoing argument area. */ |
3490 | if (num_gfregs) | |
ab835497 | 3491 | { |
c53aa195 | 3492 | int offset, real_offset, n_regs; |
3bb5de61 | 3493 | const char *base; |
ab835497 | 3494 | |
84e884e9 JM |
3495 | real_offset = -apparent_fsize; |
3496 | offset = -apparent_fsize + frame_base_offset; | |
61a55e8b DE |
3497 | if (offset < -4096 || offset + num_gfregs * 4 > 4096) |
3498 | { | |
3499 | /* ??? This might be optimized a little as %g1 might already have a | |
3500 | value close enough that a single add insn will do. */ | |
3501 | /* ??? Although, all of this is probably only a temporary fix | |
3502 | because if %g1 can hold a function result, then | |
3503 | output_function_epilogue will lose (the result will get | |
3504 | clobbered). */ | |
3505 | build_big_number (file, offset, "%g1"); | |
e0d80184 | 3506 | fprintf (file, "\tadd\t%s, %%g1, %%g1\n", frame_base_name); |
61a55e8b DE |
3507 | base = "%g1"; |
3508 | offset = 0; | |
3509 | } | |
ab835497 | 3510 | else |
61a55e8b DE |
3511 | { |
3512 | base = frame_base_name; | |
3513 | } | |
ab835497 | 3514 | |
db3d4438 | 3515 | n_regs = 0; |
ab835497 | 3516 | if (TARGET_EPILOGUE && ! leaf_function) |
61a55e8b | 3517 | /* ??? Originally saved regs 0-15 here. */ |
c53aa195 | 3518 | n_regs = save_regs (file, 0, 8, base, offset, 0, real_offset); |
ab835497 | 3519 | else if (leaf_function) |
61a55e8b | 3520 | /* ??? Originally saved regs 0-31 here. */ |
c53aa195 | 3521 | n_regs = save_regs (file, 0, 8, base, offset, 0, real_offset); |
ab835497 | 3522 | if (TARGET_EPILOGUE) |
c53aa195 JM |
3523 | save_regs (file, 32, TARGET_V9 ? 96 : 64, base, offset, n_regs, |
3524 | real_offset); | |
ab835497 RK |
3525 | } |
3526 | ||
ab835497 RK |
3527 | leaf_label = 0; |
3528 | if (leaf_function && actual_fsize != 0) | |
3529 | { | |
3530 | /* warning ("leaf procedure with frame size %d", actual_fsize); */ | |
3531 | if (! TARGET_EPILOGUE) | |
3532 | leaf_label = gen_label_rtx (); | |
3533 | } | |
3534 | } | |
3535 | ||
7d167afd JJ |
3536 | /* Output code to restore any call saved registers. */ |
3537 | ||
3538 | static void | |
3539 | output_restore_regs (file, leaf_function) | |
3540 | FILE *file; | |
3541 | int leaf_function; | |
3542 | { | |
3543 | int offset, n_regs; | |
3544 | const char *base; | |
3545 | ||
3546 | offset = -apparent_fsize + frame_base_offset; | |
3547 | if (offset < -4096 || offset + num_gfregs * 4 > 4096 - 8 /*double*/) | |
3548 | { | |
3549 | build_big_number (file, offset, "%g1"); | |
3550 | fprintf (file, "\tadd\t%s, %%g1, %%g1\n", frame_base_name); | |
3551 | base = "%g1"; | |
3552 | offset = 0; | |
3553 | } | |
3554 | else | |
3555 | { | |
3556 | base = frame_base_name; | |
3557 | } | |
3558 | ||
3559 | n_regs = 0; | |
3560 | if (TARGET_EPILOGUE && ! leaf_function) | |
3561 | /* ??? Originally saved regs 0-15 here. */ | |
3562 | n_regs = restore_regs (file, 0, 8, base, offset, 0); | |
3563 | else if (leaf_function) | |
3564 | /* ??? Originally saved regs 0-31 here. */ | |
3565 | n_regs = restore_regs (file, 0, 8, base, offset, 0); | |
3566 | if (TARGET_EPILOGUE) | |
3567 | restore_regs (file, 32, TARGET_V9 ? 96 : 64, base, offset, n_regs); | |
3568 | } | |
3569 | ||
915f619f JW |
3570 | /* Output code for the function epilogue. */ |
3571 | ||
ab835497 | 3572 | void |
ef8200df | 3573 | output_function_epilogue (file, size, leaf_function) |
ab835497 | 3574 | FILE *file; |
db3d4438 | 3575 | int size ATTRIBUTE_UNUSED; |
ef8200df | 3576 | int leaf_function; |
ab835497 | 3577 | { |
3bb5de61 | 3578 | const char *ret; |
ab835497 RK |
3579 | |
3580 | if (leaf_label) | |
3581 | { | |
ab835497 RK |
3582 | emit_label_after (leaf_label, get_last_insn ()); |
3583 | final_scan_insn (get_last_insn (), file, 0, 0, 1); | |
3584 | } | |
3585 | ||
b69649e4 RK |
3586 | #ifdef FUNCTION_BLOCK_PROFILER_EXIT |
3587 | else if (profile_block_flag == 2) | |
3588 | { | |
3589 | FUNCTION_BLOCK_PROFILER_EXIT(file); | |
3590 | } | |
3591 | #endif | |
3592 | ||
bfd6bc60 | 3593 | else if (current_function_epilogue_delay_list == 0) |
e48addee | 3594 | { |
e0d80184 DM |
3595 | /* If code does not drop into the epilogue, we need |
3596 | do nothing except output pending case vectors. */ | |
bfd6bc60 JC |
3597 | rtx insn = get_last_insn (); |
3598 | if (GET_CODE (insn) == NOTE) | |
3599 | insn = prev_nonnote_insn (insn); | |
3600 | if (insn && GET_CODE (insn) == BARRIER) | |
e0d80184 | 3601 | goto output_vectors; |
bfd6bc60 JC |
3602 | } |
3603 | ||
61a55e8b | 3604 | if (num_gfregs) |
7d167afd | 3605 | output_restore_regs (file, leaf_function); |
ab835497 RK |
3606 | |
3607 | /* Work out how to skip the caller's unimp instruction if required. */ | |
3608 | if (leaf_function) | |
e0d80184 | 3609 | ret = (SKIP_CALLERS_UNIMP_P ? "jmp\t%o7+12" : "retl"); |
ab835497 | 3610 | else |
e0d80184 | 3611 | ret = (SKIP_CALLERS_UNIMP_P ? "jmp\t%i7+12" : "ret"); |
ab835497 | 3612 | |
ef8200df | 3613 | if (TARGET_EPILOGUE || leaf_label) |
ab835497 | 3614 | { |
ef8200df JW |
3615 | int old_target_epilogue = TARGET_EPILOGUE; |
3616 | target_flags &= ~old_target_epilogue; | |
ab835497 | 3617 | |
ef8200df JW |
3618 | if (! leaf_function) |
3619 | { | |
3620 | /* If we wound up with things in our delay slot, flush them here. */ | |
3621 | if (current_function_epilogue_delay_list) | |
ab835497 | 3622 | { |
e48addee JJ |
3623 | rtx delay = PATTERN (XEXP (current_function_epilogue_delay_list, 0)); |
3624 | ||
3625 | if (TARGET_V9 && ! epilogue_renumber (&delay, 1)) | |
3626 | { | |
3627 | epilogue_renumber (&delay, 0); | |
3628 | fputs (SKIP_CALLERS_UNIMP_P | |
3629 | ? "\treturn\t%i7+12\n" | |
3630 | : "\treturn\t%i7+8\n", file); | |
3631 | final_scan_insn (XEXP (current_function_epilogue_delay_list, 0), file, 1, 0, 0); | |
3632 | } | |
3633 | else | |
3634 | { | |
3635 | rtx insn = emit_jump_insn_after (gen_rtx_RETURN (VOIDmode), | |
3636 | get_last_insn ()); | |
3637 | rtx src; | |
3638 | ||
3639 | if (GET_CODE (delay) != SET) | |
3640 | abort(); | |
3641 | ||
3642 | src = SET_SRC (delay); | |
3643 | if (GET_CODE (src) == ASHIFT) | |
3644 | { | |
3645 | if (XEXP (src, 1) != const1_rtx) | |
3646 | abort(); | |
3647 | SET_SRC (delay) = gen_rtx_PLUS (GET_MODE (src), XEXP (src, 0), | |
3648 | XEXP (src, 0)); | |
3649 | } | |
3650 | ||
3651 | PATTERN (insn) = gen_rtx_PARALLEL (VOIDmode, | |
3652 | gen_rtvec (2, delay, PATTERN (insn))); | |
3653 | final_scan_insn (insn, file, 1, 0, 1); | |
3654 | } | |
ab835497 | 3655 | } |
284d86e9 | 3656 | else if (TARGET_V9 && ! SKIP_CALLERS_UNIMP_P) |
e0d80184 | 3657 | fputs ("\treturn\t%i7+8\n\tnop\n", file); |
ab835497 | 3658 | else |
ef8200df JW |
3659 | fprintf (file, "\t%s\n\trestore\n", ret); |
3660 | } | |
915f619f JW |
3661 | /* All of the following cases are for leaf functions. */ |
3662 | else if (current_function_epilogue_delay_list) | |
ef8200df | 3663 | { |
915f619f JW |
3664 | /* eligible_for_epilogue_delay_slot ensures that if this is a |
3665 | leaf function, then we will only have insn in the delay slot | |
3666 | if the frame size is zero, thus no adjust for the stack is | |
3667 | needed here. */ | |
3668 | if (actual_fsize != 0) | |
ef8200df | 3669 | abort (); |
915f619f JW |
3670 | fprintf (file, "\t%s\n", ret); |
3671 | final_scan_insn (XEXP (current_function_epilogue_delay_list, 0), | |
3672 | file, 1, 0, 1); | |
ab835497 | 3673 | } |
9bb7ffda JW |
3674 | /* Output 'nop' instead of 'sub %sp,-0,%sp' when no frame, so as to |
3675 | avoid generating confusing assembly language output. */ | |
3676 | else if (actual_fsize == 0) | |
3677 | fprintf (file, "\t%s\n\tnop\n", ret); | |
915f619f | 3678 | else if (actual_fsize <= 4096) |
e0d80184 | 3679 | fprintf (file, "\t%s\n\tsub\t%%sp, -%d, %%sp\n", ret, actual_fsize); |
915f619f | 3680 | else if (actual_fsize <= 8192) |
e0d80184 | 3681 | fprintf (file, "\tsub\t%%sp, -4096, %%sp\n\t%s\n\tsub\t%%sp, -%d, %%sp\n", |
915f619f JW |
3682 | ret, actual_fsize - 4096); |
3683 | else if ((actual_fsize & 0x3ff) == 0) | |
e0d80184 | 3684 | fprintf (file, "\tsethi\t%%hi(%d), %%g1\n\t%s\n\tadd\t%%sp, %%g1, %%sp\n", |
915f619f JW |
3685 | actual_fsize, ret); |
3686 | else | |
e0d80184 | 3687 | fprintf (file, "\tsethi\t%%hi(%d), %%g1\n\tor\t%%g1, %%lo(%d), %%g1\n\t%s\n\tadd\t%%sp, %%g1, %%sp\n", |
915f619f | 3688 | actual_fsize, actual_fsize, ret); |
ef8200df | 3689 | target_flags |= old_target_epilogue; |
ab835497 | 3690 | } |
e0d80184 DM |
3691 | |
3692 | output_vectors: | |
3693 | sparc_output_deferred_case_vectors (); | |
ab835497 | 3694 | } |
7d167afd JJ |
3695 | |
3696 | /* Output a sibling call. */ | |
3697 | ||
3698 | const char * | |
3699 | output_sibcall (insn, call_operand) | |
3700 | rtx insn, call_operand; | |
3701 | { | |
3702 | int leaf_regs = current_function_uses_only_leaf_regs; | |
3703 | rtx operands[3]; | |
3704 | int delay_slot = dbr_sequence_length () > 0; | |
3705 | ||
3706 | if (num_gfregs) | |
3707 | { | |
3708 | /* Call to restore global regs might clobber | |
3709 | the delay slot. Instead of checking for this | |
3710 | output the delay slot now. */ | |
3711 | if (delay_slot) | |
3712 | { | |
3713 | rtx delay = NEXT_INSN (insn); | |
3714 | ||
3715 | if (! delay) | |
3716 | abort (); | |
3717 | ||
3718 | final_scan_insn (delay, asm_out_file, 1, 0, 1); | |
3719 | PATTERN (delay) = gen_blockage (); | |
3720 | INSN_CODE (delay) = -1; | |
3721 | delay_slot = 0; | |
3722 | } | |
3723 | output_restore_regs (asm_out_file, leaf_regs); | |
3724 | } | |
3725 | ||
3726 | operands[0] = call_operand; | |
3727 | ||
3728 | if (leaf_regs) | |
3729 | { | |
3730 | int spare_slot = (TARGET_ARCH32 || TARGET_CM_MEDLOW); | |
3731 | int size = 0; | |
3732 | ||
3733 | if ((actual_fsize || ! spare_slot) && delay_slot) | |
3734 | { | |
3735 | rtx delay = NEXT_INSN (insn); | |
3736 | ||
3737 | if (! delay) | |
3738 | abort (); | |
3739 | ||
3740 | final_scan_insn (delay, asm_out_file, 1, 0, 1); | |
3741 | PATTERN (delay) = gen_blockage (); | |
3742 | INSN_CODE (delay) = -1; | |
3743 | delay_slot = 0; | |
3744 | } | |
3745 | if (actual_fsize) | |
3746 | { | |
3747 | if (actual_fsize <= 4096) | |
3748 | size = actual_fsize; | |
3749 | else if (actual_fsize <= 8192) | |
3750 | { | |
3751 | fputs ("\tsub\t%sp, -4096, %sp\n", asm_out_file); | |
3752 | size = actual_fsize - 4096; | |
3753 | } | |
3754 | else if ((actual_fsize & 0x3ff) == 0) | |
3755 | fprintf (asm_out_file, | |
3756 | "\tsethi\t%%hi(%d), %%g1\n\tadd\t%%sp, %%g1, %%sp\n", | |
3757 | actual_fsize); | |
3758 | else | |
3759 | { | |
3760 | fprintf (asm_out_file, | |
3761 | "\tsethi\t%%hi(%d), %%g1\n\tor\t%%g1, %%lo(%d), %%g1\n", | |
3762 | actual_fsize, actual_fsize); | |
3763 | fputs ("\tadd\t%%sp, %%g1, %%sp\n", asm_out_file); | |
3764 | } | |
3765 | } | |
3766 | if (spare_slot) | |
3767 | { | |
3768 | output_asm_insn ("sethi\t%%hi(%a0), %%g1", operands); | |
3769 | output_asm_insn ("jmpl\t%%g1 + %%lo(%a0), %%g0", operands); | |
3770 | if (size) | |
3771 | fprintf (asm_out_file, "\t sub\t%%sp, -%d, %%sp\n", size); | |
3772 | else if (! delay_slot) | |
3773 | fputs ("\t nop\n", asm_out_file); | |
3774 | } | |
3775 | else | |
3776 | { | |
3777 | if (size) | |
3778 | fprintf (asm_out_file, "\tsub\t%%sp, -%d, %%sp\n", size); | |
3779 | output_asm_insn ("mov\t%%o7, %%g1", operands); | |
3780 | output_asm_insn ("call\t%a0, 0", operands); | |
3781 | output_asm_insn (" mov\t%%g1, %%o7", operands); | |
3782 | } | |
3783 | return ""; | |
3784 | } | |
3785 | ||
3786 | output_asm_insn ("call\t%a0, 0", operands); | |
3787 | if (delay_slot) | |
3788 | { | |
3789 | rtx delay = NEXT_INSN (insn), pat; | |
3790 | ||
3791 | if (! delay) | |
3792 | abort (); | |
3793 | ||
3794 | pat = PATTERN (delay); | |
3795 | if (GET_CODE (pat) != SET) | |
3796 | abort (); | |
3797 | ||
3798 | operands[0] = SET_DEST (pat); | |
3799 | pat = SET_SRC (pat); | |
3800 | switch (GET_CODE (pat)) | |
3801 | { | |
3802 | case PLUS: | |
3803 | operands[1] = XEXP (pat, 0); | |
3804 | operands[2] = XEXP (pat, 1); | |
3805 | output_asm_insn (" restore %r1, %2, %Y0", operands); | |
3806 | break; | |
3807 | case LO_SUM: | |
3808 | operands[1] = XEXP (pat, 0); | |
3809 | operands[2] = XEXP (pat, 1); | |
3810 | output_asm_insn (" restore %r1, %%lo(%a2), %Y0", operands); | |
3811 | break; | |
3812 | case ASHIFT: | |
3813 | operands[1] = XEXP (pat, 0); | |
3814 | output_asm_insn (" restore %r1, %r1, %Y0", operands); | |
3815 | break; | |
3816 | default: | |
3817 | operands[1] = pat; | |
3818 | output_asm_insn (" restore %%g0, %1, %Y0", operands); | |
3819 | break; | |
3820 | } | |
3821 | PATTERN (delay) = gen_blockage (); | |
3822 | INSN_CODE (delay) = -1; | |
3823 | } | |
3824 | else | |
3825 | fputs ("\t restore\n", asm_out_file); | |
3826 | return ""; | |
3827 | } | |
4fb4e4b8 DE |
3828 | \f |
3829 | /* Functions for handling argument passing. | |
3830 | ||
3831 | For v8 the first six args are normally in registers and the rest are | |
3832 | pushed. Any arg that starts within the first 6 words is at least | |
3833 | partially passed in a register unless its data type forbids. | |
3834 | ||
3835 | For v9, the argument registers are laid out as an array of 16 elements | |
3836 | and arguments are added sequentially. The first 6 int args and up to the | |
3837 | first 16 fp args (depending on size) are passed in regs. | |
3838 | ||
3839 | Slot Stack Integral Float Float in structure Double Long Double | |
3840 | ---- ----- -------- ----- ------------------ ------ ----------- | |
3841 | 15 [SP+248] %f31 %f30,%f31 %d30 | |
3842 | 14 [SP+240] %f29 %f28,%f29 %d28 %q28 | |
3843 | 13 [SP+232] %f27 %f26,%f27 %d26 | |
3844 | 12 [SP+224] %f25 %f24,%f25 %d24 %q24 | |
3845 | 11 [SP+216] %f23 %f22,%f23 %d22 | |
3846 | 10 [SP+208] %f21 %f20,%f21 %d20 %q20 | |
3847 | 9 [SP+200] %f19 %f18,%f19 %d18 | |
3848 | 8 [SP+192] %f17 %f16,%f17 %d16 %q16 | |
3849 | 7 [SP+184] %f15 %f14,%f15 %d14 | |
3850 | 6 [SP+176] %f13 %f12,%f13 %d12 %q12 | |
3851 | 5 [SP+168] %o5 %f11 %f10,%f11 %d10 | |
3852 | 4 [SP+160] %o4 %f9 %f8,%f9 %d8 %q8 | |
3853 | 3 [SP+152] %o3 %f7 %f6,%f7 %d6 | |
3854 | 2 [SP+144] %o2 %f5 %f4,%f5 %d4 %q4 | |
3855 | 1 [SP+136] %o1 %f3 %f2,%f3 %d2 | |
3856 | 0 [SP+128] %o0 %f1 %f0,%f1 %d0 %q0 | |
3857 | ||
3858 | Here SP = %sp if -mno-stack-bias or %sp+stack_bias otherwise. | |
3859 | ||
3860 | Integral arguments are always passed as 64 bit quantities appropriately | |
3861 | extended. | |
3862 | ||
3863 | Passing of floating point values is handled as follows. | |
3864 | If a prototype is in scope: | |
3865 | If the value is in a named argument (i.e. not a stdarg function or a | |
3866 | value not part of the `...') then the value is passed in the appropriate | |
3867 | fp reg. | |
3868 | If the value is part of the `...' and is passed in one of the first 6 | |
3869 | slots then the value is passed in the appropriate int reg. | |
3870 | If the value is part of the `...' and is not passed in one of the first 6 | |
3871 | slots then the value is passed in memory. | |
3872 | If a prototype is not in scope: | |
3873 | If the value is one of the first 6 arguments the value is passed in the | |
3874 | appropriate integer reg and the appropriate fp reg. | |
3875 | If the value is not one of the first 6 arguments the value is passed in | |
3876 | the appropriate fp reg and in memory. | |
3877 | */ | |
3878 | ||
3879 | /* Maximum number of int regs for args. */ | |
3880 | #define SPARC_INT_ARG_MAX 6 | |
3881 | /* Maximum number of fp regs for args. */ | |
3882 | #define SPARC_FP_ARG_MAX 16 | |
3883 | ||
3884 | #define ROUND_ADVANCE(SIZE) (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) | |
3885 | ||
3886 | /* Handle the INIT_CUMULATIVE_ARGS macro. | |
3887 | Initialize a variable CUM of type CUMULATIVE_ARGS | |
3888 | for a call to a function whose data type is FNTYPE. | |
3889 | For a library call, FNTYPE is 0. */ | |
3ea1fdd3 | 3890 | |
4fb4e4b8 DE |
3891 | void |
3892 | init_cumulative_args (cum, fntype, libname, indirect) | |
3893 | CUMULATIVE_ARGS *cum; | |
db3d4438 | 3894 | tree fntype; |
88430453 | 3895 | rtx libname ATTRIBUTE_UNUSED; |
db3d4438 | 3896 | int indirect ATTRIBUTE_UNUSED; |
4fb4e4b8 DE |
3897 | { |
3898 | cum->words = 0; | |
3899 | cum->prototype_p = fntype && TYPE_ARG_TYPES (fntype); | |
3900 | cum->libcall_p = fntype == 0; | |
3901 | } | |
61a55e8b | 3902 | |
4fb4e4b8 DE |
3903 | /* Compute the slot number to pass an argument in. |
3904 | Returns the slot number or -1 if passing on the stack. | |
3905 | ||
3906 | CUM is a variable of type CUMULATIVE_ARGS which gives info about | |
3907 | the preceding args and about the function being called. | |
3908 | MODE is the argument's machine mode. | |
3909 | TYPE is the data type of the argument (as a tree). | |
3910 | This is null for libcalls where that information may | |
3911 | not be available. | |
3912 | NAMED is nonzero if this argument is a named parameter | |
3913 | (otherwise it is an extra parameter matching an ellipsis). | |
3914 | INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG. | |
3915 | *PREGNO records the register number to use if scalar type. | |
3916 | *PPADDING records the amount of padding needed in words. */ | |
3917 | ||
3918 | static int | |
3919 | function_arg_slotno (cum, mode, type, named, incoming_p, pregno, ppadding) | |
3920 | const CUMULATIVE_ARGS *cum; | |
3921 | enum machine_mode mode; | |
3922 | tree type; | |
3923 | int named; | |
3924 | int incoming_p; | |
3925 | int *pregno; | |
3926 | int *ppadding; | |
3927 | { | |
3928 | int regbase = (incoming_p | |
3929 | ? SPARC_INCOMING_INT_ARG_FIRST | |
3930 | : SPARC_OUTGOING_INT_ARG_FIRST); | |
3931 | int slotno = cum->words; | |
3932 | int regno; | |
3933 | ||
3934 | *ppadding = 0; | |
3935 | ||
3936 | if (type != 0 && TREE_ADDRESSABLE (type)) | |
3937 | return -1; | |
3938 | if (TARGET_ARCH32 | |
3939 | && type != 0 && mode == BLKmode | |
3940 | && TYPE_ALIGN (type) % PARM_BOUNDARY != 0) | |
3941 | return -1; | |
3942 | ||
3943 | switch (mode) | |
3944 | { | |
3945 | case VOIDmode : | |
3946 | /* MODE is VOIDmode when generating the actual call. | |
3947 | See emit_call_1. */ | |
3948 | return -1; | |
3949 | ||
3950 | case QImode : case CQImode : | |
3951 | case HImode : case CHImode : | |
3952 | case SImode : case CSImode : | |
3953 | case DImode : case CDImode : | |
3954 | if (slotno >= SPARC_INT_ARG_MAX) | |
3955 | return -1; | |
3956 | regno = regbase + slotno; | |
3957 | break; | |
3958 | ||
3959 | case SFmode : case SCmode : | |
3960 | case DFmode : case DCmode : | |
3961 | case TFmode : case TCmode : | |
3962 | if (TARGET_ARCH32) | |
3963 | { | |
3964 | if (slotno >= SPARC_INT_ARG_MAX) | |
3965 | return -1; | |
3966 | regno = regbase + slotno; | |
3967 | } | |
3968 | else | |
3969 | { | |
3970 | if ((mode == TFmode || mode == TCmode) | |
3971 | && (slotno & 1) != 0) | |
3972 | slotno++, *ppadding = 1; | |
3973 | if (TARGET_FPU && named) | |
3974 | { | |
3975 | if (slotno >= SPARC_FP_ARG_MAX) | |
82d6b402 | 3976 | return -1; |
4fb4e4b8 DE |
3977 | regno = SPARC_FP_ARG_FIRST + slotno * 2; |
3978 | if (mode == SFmode) | |
3979 | regno++; | |
3980 | } | |
3981 | else | |
3982 | { | |
3983 | if (slotno >= SPARC_INT_ARG_MAX) | |
3984 | return -1; | |
3985 | regno = regbase + slotno; | |
3986 | } | |
3987 | } | |
3988 | break; | |
3989 | ||
3990 | case BLKmode : | |
3991 | /* For sparc64, objects requiring 16 byte alignment get it. */ | |
3992 | if (TARGET_ARCH64) | |
3993 | { | |
3994 | if (type && TYPE_ALIGN (type) == 128 && (slotno & 1) != 0) | |
3995 | slotno++, *ppadding = 1; | |
3996 | } | |
3997 | ||
3998 | if (TARGET_ARCH32 | |
5e9defae | 3999 | || (type && TREE_CODE (type) == UNION_TYPE)) |
4fb4e4b8 DE |
4000 | { |
4001 | if (slotno >= SPARC_INT_ARG_MAX) | |
4002 | return -1; | |
4003 | regno = regbase + slotno; | |
4004 | } | |
4005 | else | |
4006 | { | |
4007 | tree field; | |
4008 | int intregs_p = 0, fpregs_p = 0; | |
4009 | /* The ABI obviously doesn't specify how packed | |
4010 | structures are passed. These are defined to be passed | |
4011 | in int regs if possible, otherwise memory. */ | |
4012 | int packed_p = 0; | |
4013 | ||
4014 | /* First see what kinds of registers we need. */ | |
4015 | for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field)) | |
4016 | { | |
4017 | if (TREE_CODE (field) == FIELD_DECL) | |
4018 | { | |
4019 | if (TREE_CODE (TREE_TYPE (field)) == REAL_TYPE | |
4020 | && TARGET_FPU) | |
4021 | fpregs_p = 1; | |
4022 | else | |
4023 | intregs_p = 1; | |
4024 | if (DECL_PACKED (field)) | |
4025 | packed_p = 1; | |
4026 | } | |
4027 | } | |
4028 | if (packed_p || !named) | |
4029 | fpregs_p = 0, intregs_p = 1; | |
4030 | ||
4031 | /* If all arg slots are filled, then must pass on stack. */ | |
4032 | if (fpregs_p && slotno >= SPARC_FP_ARG_MAX) | |
4033 | return -1; | |
4034 | /* If there are only int args and all int arg slots are filled, | |
4035 | then must pass on stack. */ | |
4036 | if (!fpregs_p && intregs_p && slotno >= SPARC_INT_ARG_MAX) | |
4037 | return -1; | |
4038 | /* Note that even if all int arg slots are filled, fp members may | |
4039 | still be passed in regs if such regs are available. | |
4040 | *PREGNO isn't set because there may be more than one, it's up | |
4041 | to the caller to compute them. */ | |
4042 | return slotno; | |
4043 | } | |
4044 | break; | |
4045 | ||
4046 | default : | |
4047 | abort (); | |
4048 | } | |
4049 | ||
4050 | *pregno = regno; | |
4051 | return slotno; | |
4052 | } | |
4053 | ||
82d6b402 RH |
4054 | /* Handle recursive register counting for structure field layout. */ |
4055 | ||
4056 | struct function_arg_record_value_parms | |
4057 | { | |
4058 | rtx ret; | |
4059 | int slotno, named, regbase; | |
4060 | int nregs, intoffset; | |
4061 | }; | |
4062 | ||
2a01c939 | 4063 | static void function_arg_record_value_3 |
f6da8bc3 | 4064 | PARAMS ((int, struct function_arg_record_value_parms *)); |
2a01c939 | 4065 | static void function_arg_record_value_2 |
f6da8bc3 | 4066 | PARAMS ((tree, int, struct function_arg_record_value_parms *)); |
b1474bb7 | 4067 | static void function_arg_record_value_1 |
f6da8bc3 | 4068 | PARAMS ((tree, int, struct function_arg_record_value_parms *)); |
2a01c939 | 4069 | static rtx function_arg_record_value |
f6da8bc3 | 4070 | PARAMS ((tree, enum machine_mode, int, int, int)); |
2a01c939 | 4071 | |
82d6b402 RH |
4072 | static void |
4073 | function_arg_record_value_1 (type, startbitpos, parms) | |
4074 | tree type; | |
4075 | int startbitpos; | |
4076 | struct function_arg_record_value_parms *parms; | |
4077 | { | |
4078 | tree field; | |
4079 | ||
4080 | /* The ABI obviously doesn't specify how packed structures are | |
4081 | passed. These are defined to be passed in int regs if possible, | |
4082 | otherwise memory. */ | |
4083 | int packed_p = 0; | |
4084 | ||
4085 | /* We need to compute how many registers are needed so we can | |
4086 | allocate the PARALLEL but before we can do that we need to know | |
4087 | whether there are any packed fields. If there are, int regs are | |
4088 | used regardless of whether there are fp values present. */ | |
4089 | for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field)) | |
4090 | { | |
4091 | if (TREE_CODE (field) == FIELD_DECL && DECL_PACKED (field)) | |
4092 | { | |
4093 | packed_p = 1; | |
4094 | break; | |
4095 | } | |
4096 | } | |
4097 | ||
4098 | /* Compute how many registers we need. */ | |
4099 | for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field)) | |
4100 | { | |
4101 | if (TREE_CODE (field) == FIELD_DECL) | |
4102 | { | |
4103 | int bitpos = startbitpos; | |
4104 | if (DECL_FIELD_BITPOS (field)) | |
4105 | bitpos += TREE_INT_CST_LOW (DECL_FIELD_BITPOS (field)); | |
4106 | /* ??? FIXME: else assume zero offset. */ | |
4107 | ||
4108 | if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE) | |
4109 | { | |
4110 | function_arg_record_value_1 (TREE_TYPE (field), bitpos, parms); | |
4111 | } | |
4112 | else if (TREE_CODE (TREE_TYPE (field)) == REAL_TYPE | |
4113 | && TARGET_FPU | |
4114 | && ! packed_p | |
4115 | && parms->named) | |
4116 | { | |
4117 | if (parms->intoffset != -1) | |
4118 | { | |
4119 | int intslots, this_slotno; | |
4120 | ||
4121 | intslots = (bitpos - parms->intoffset + BITS_PER_WORD - 1) | |
4122 | / BITS_PER_WORD; | |
4123 | this_slotno = parms->slotno + parms->intoffset | |
4124 | / BITS_PER_WORD; | |
4125 | ||
4126 | intslots = MIN (intslots, SPARC_INT_ARG_MAX - this_slotno); | |
4127 | intslots = MAX (intslots, 0); | |
4128 | parms->nregs += intslots; | |
4129 | parms->intoffset = -1; | |
4130 | } | |
4131 | ||
4132 | /* There's no need to check this_slotno < SPARC_FP_ARG MAX. | |
4133 | If it wasn't true we wouldn't be here. */ | |
4134 | parms->nregs += 1; | |
4135 | } | |
4136 | else | |
4137 | { | |
4138 | if (parms->intoffset == -1) | |
4139 | parms->intoffset = bitpos; | |
4140 | } | |
4141 | } | |
4142 | } | |
4143 | } | |
4144 | ||
4145 | /* Handle recursive structure field register assignment. */ | |
4146 | ||
4147 | static void | |
4148 | function_arg_record_value_3 (bitpos, parms) | |
4149 | int bitpos; | |
4150 | struct function_arg_record_value_parms *parms; | |
4151 | { | |
4152 | enum machine_mode mode; | |
4153 | int regno, this_slotno, intslots, intoffset; | |
4154 | rtx reg; | |
4155 | ||
4156 | if (parms->intoffset == -1) | |
4157 | return; | |
4158 | intoffset = parms->intoffset; | |
4159 | parms->intoffset = -1; | |
4160 | ||
4161 | intslots = (bitpos - intoffset + BITS_PER_WORD - 1) / BITS_PER_WORD; | |
4162 | this_slotno = parms->slotno + intoffset / BITS_PER_WORD; | |
4163 | ||
4164 | intslots = MIN (intslots, SPARC_INT_ARG_MAX - this_slotno); | |
4165 | if (intslots <= 0) | |
4166 | return; | |
4167 | ||
4168 | /* If this is the trailing part of a word, only load that much into | |
4169 | the register. Otherwise load the whole register. Note that in | |
4170 | the latter case we may pick up unwanted bits. It's not a problem | |
4171 | at the moment but may wish to revisit. */ | |
4172 | ||
4173 | if (intoffset % BITS_PER_WORD != 0) | |
4174 | { | |
4175 | mode = mode_for_size (BITS_PER_WORD - intoffset%BITS_PER_WORD, | |
4176 | MODE_INT, 0); | |
4177 | } | |
4178 | else | |
4179 | mode = word_mode; | |
4180 | ||
4181 | intoffset /= BITS_PER_UNIT; | |
4182 | do | |
4183 | { | |
4184 | regno = parms->regbase + this_slotno; | |
254110c2 | 4185 | reg = gen_rtx_REG (mode, regno); |
82d6b402 | 4186 | XVECEXP (parms->ret, 0, parms->nregs) |
254110c2 | 4187 | = gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset)); |
82d6b402 RH |
4188 | |
4189 | this_slotno += 1; | |
4190 | intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1; | |
4191 | parms->nregs += 1; | |
4192 | intslots -= 1; | |
4193 | } | |
4194 | while (intslots > 0); | |
4195 | } | |
4196 | ||
4197 | static void | |
4198 | function_arg_record_value_2 (type, startbitpos, parms) | |
4199 | tree type; | |
4200 | int startbitpos; | |
4201 | struct function_arg_record_value_parms *parms; | |
4202 | { | |
4203 | tree field; | |
4204 | int packed_p = 0; | |
4205 | ||
4206 | for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field)) | |
4207 | { | |
4208 | if (TREE_CODE (field) == FIELD_DECL && DECL_PACKED (field)) | |
4209 | { | |
4210 | packed_p = 1; | |
4211 | break; | |
4212 | } | |
4213 | } | |
4214 | ||
4215 | for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field)) | |
4216 | { | |
4217 | if (TREE_CODE (field) == FIELD_DECL) | |
4218 | { | |
4219 | int bitpos = startbitpos; | |
4220 | if (DECL_FIELD_BITPOS (field)) | |
4221 | bitpos += TREE_INT_CST_LOW (DECL_FIELD_BITPOS (field)); | |
4222 | /* ??? FIXME: else assume zero offset. */ | |
4223 | ||
4224 | if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE) | |
4225 | { | |
4226 | function_arg_record_value_2 (TREE_TYPE (field), bitpos, parms); | |
4227 | } | |
4228 | else if (TREE_CODE (TREE_TYPE (field)) == REAL_TYPE | |
4229 | && TARGET_FPU | |
4230 | && ! packed_p | |
4231 | && parms->named) | |
4232 | { | |
4233 | int this_slotno = parms->slotno + bitpos / BITS_PER_WORD; | |
4234 | rtx reg; | |
4235 | ||
4236 | function_arg_record_value_3 (bitpos, parms); | |
4237 | ||
254110c2 | 4238 | reg = gen_rtx_REG (DECL_MODE (field), |
82d6b402 RH |
4239 | (SPARC_FP_ARG_FIRST + this_slotno * 2 |
4240 | + (DECL_MODE (field) == SFmode | |
4241 | && (bitpos & 32) != 0))); | |
4242 | XVECEXP (parms->ret, 0, parms->nregs) | |
254110c2 | 4243 | = gen_rtx_EXPR_LIST (VOIDmode, reg, |
82d6b402 RH |
4244 | GEN_INT (bitpos / BITS_PER_UNIT)); |
4245 | parms->nregs += 1; | |
4246 | } | |
4247 | else | |
4248 | { | |
4249 | if (parms->intoffset == -1) | |
4250 | parms->intoffset = bitpos; | |
4251 | } | |
4252 | } | |
4253 | } | |
4254 | } | |
4255 | ||
4256 | static rtx | |
1eac9f59 | 4257 | function_arg_record_value (type, mode, slotno, named, regbase) |
82d6b402 | 4258 | tree type; |
1eac9f59 | 4259 | enum machine_mode mode; |
82d6b402 RH |
4260 | int slotno, named, regbase; |
4261 | { | |
4262 | HOST_WIDE_INT typesize = int_size_in_bytes (type); | |
4263 | struct function_arg_record_value_parms parms; | |
4264 | int nregs; | |
4265 | ||
4266 | parms.ret = NULL_RTX; | |
4267 | parms.slotno = slotno; | |
4268 | parms.named = named; | |
4269 | parms.regbase = regbase; | |
4270 | ||
4271 | /* Compute how many registers we need. */ | |
4272 | parms.nregs = 0; | |
4273 | parms.intoffset = 0; | |
4274 | function_arg_record_value_1 (type, 0, &parms); | |
4275 | ||
4276 | if (parms.intoffset != -1) | |
4277 | { | |
4278 | int intslots, this_slotno; | |
4279 | ||
4280 | intslots = (typesize*BITS_PER_UNIT - parms.intoffset + BITS_PER_WORD - 1) | |
4281 | / BITS_PER_WORD; | |
4282 | this_slotno = slotno + parms.intoffset / BITS_PER_WORD; | |
4283 | ||
4284 | intslots = MIN (intslots, SPARC_INT_ARG_MAX - this_slotno); | |
4285 | intslots = MAX (intslots, 0); | |
4286 | ||
4287 | parms.nregs += intslots; | |
4288 | } | |
4289 | nregs = parms.nregs; | |
4290 | ||
4291 | /* Allocate the vector and handle some annoying special cases. */ | |
4292 | if (nregs == 0) | |
4293 | { | |
4294 | /* ??? Empty structure has no value? Duh? */ | |
4295 | if (typesize <= 0) | |
4296 | { | |
4297 | /* Though there's nothing really to store, return a word register | |
4298 | anyway so the rest of gcc doesn't go nuts. Returning a PARALLEL | |
4299 | leads to breakage due to the fact that there are zero bytes to | |
4300 | load. */ | |
1eac9f59 | 4301 | return gen_rtx_REG (mode, regbase); |
82d6b402 RH |
4302 | } |
4303 | else | |
4304 | { | |
4305 | /* ??? C++ has structures with no fields, and yet a size. Give up | |
4306 | for now and pass everything back in integer registers. */ | |
4307 | nregs = (typesize + UNITS_PER_WORD - 1) / UNITS_PER_WORD; | |
4308 | } | |
4309 | if (nregs + slotno > SPARC_INT_ARG_MAX) | |
4310 | nregs = SPARC_INT_ARG_MAX - slotno; | |
4311 | } | |
4312 | if (nregs == 0) | |
9208e4b2 | 4313 | abort (); |
82d6b402 | 4314 | |
1eac9f59 | 4315 | parms.ret = gen_rtx_PARALLEL (mode, rtvec_alloc (nregs)); |
82d6b402 RH |
4316 | |
4317 | /* Fill in the entries. */ | |
4318 | parms.nregs = 0; | |
4319 | parms.intoffset = 0; | |
4320 | function_arg_record_value_2 (type, 0, &parms); | |
4321 | function_arg_record_value_3 (typesize * BITS_PER_UNIT, &parms); | |
4322 | ||
4323 | if (parms.nregs != nregs) | |
4324 | abort (); | |
4325 | ||
4326 | return parms.ret; | |
4327 | } | |
4328 | ||
4fb4e4b8 DE |
4329 | /* Handle the FUNCTION_ARG macro. |
4330 | Determine where to put an argument to a function. | |
4331 | Value is zero to push the argument on the stack, | |
4332 | or a hard register in which to store the argument. | |
4333 | ||
4334 | CUM is a variable of type CUMULATIVE_ARGS which gives info about | |
4335 | the preceding args and about the function being called. | |
4336 | MODE is the argument's machine mode. | |
4337 | TYPE is the data type of the argument (as a tree). | |
4338 | This is null for libcalls where that information may | |
4339 | not be available. | |
4340 | NAMED is nonzero if this argument is a named parameter | |
4341 | (otherwise it is an extra parameter matching an ellipsis). | |
4342 | INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG. */ | |
61a55e8b DE |
4343 | |
4344 | rtx | |
4fb4e4b8 DE |
4345 | function_arg (cum, mode, type, named, incoming_p) |
4346 | const CUMULATIVE_ARGS *cum; | |
4347 | enum machine_mode mode; | |
4348 | tree type; | |
4349 | int named; | |
4350 | int incoming_p; | |
61a55e8b | 4351 | { |
4fb4e4b8 DE |
4352 | int regbase = (incoming_p |
4353 | ? SPARC_INCOMING_INT_ARG_FIRST | |
4354 | : SPARC_OUTGOING_INT_ARG_FIRST); | |
4355 | int slotno, regno, padding; | |
4356 | rtx reg; | |
4357 | ||
4358 | slotno = function_arg_slotno (cum, mode, type, named, incoming_p, | |
4359 | ®no, &padding); | |
4360 | ||
4361 | if (slotno == -1) | |
4362 | return 0; | |
4363 | ||
4364 | if (TARGET_ARCH32) | |
4365 | { | |
254110c2 | 4366 | reg = gen_rtx_REG (mode, regno); |
4fb4e4b8 DE |
4367 | return reg; |
4368 | } | |
4369 | ||
4370 | /* v9 fp args in reg slots beyond the int reg slots get passed in regs | |
4371 | but also have the slot allocated for them. | |
4372 | If no prototype is in scope fp values in register slots get passed | |
4373 | in two places, either fp regs and int regs or fp regs and memory. */ | |
4374 | if ((GET_MODE_CLASS (mode) == MODE_FLOAT | |
4375 | || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT) | |
4376 | && SPARC_FP_REG_P (regno)) | |
4377 | { | |
254110c2 | 4378 | reg = gen_rtx_REG (mode, regno); |
4fb4e4b8 DE |
4379 | if (cum->prototype_p || cum->libcall_p) |
4380 | { | |
4381 | /* "* 2" because fp reg numbers are recorded in 4 byte | |
4382 | quantities. */ | |
82d6b402 | 4383 | #if 0 |
4fb4e4b8 DE |
4384 | /* ??? This will cause the value to be passed in the fp reg and |
4385 | in the stack. When a prototype exists we want to pass the | |
4386 | value in the reg but reserve space on the stack. That's an | |
956d6950 | 4387 | optimization, and is deferred [for a bit]. */ |
4fb4e4b8 | 4388 | if ((regno - SPARC_FP_ARG_FIRST) >= SPARC_INT_ARG_MAX * 2) |
254110c2 | 4389 | return gen_rtx_PARALLEL (mode, |
4fb4e4b8 | 4390 | gen_rtvec (2, |
254110c2 | 4391 | gen_rtx_EXPR_LIST (VOIDmode, |
4fb4e4b8 | 4392 | NULL_RTX, const0_rtx), |
254110c2 | 4393 | gen_rtx_EXPR_LIST (VOIDmode, |
4fb4e4b8 DE |
4394 | reg, const0_rtx))); |
4395 | else | |
82d6b402 RH |
4396 | #else |
4397 | /* ??? It seems that passing back a register even when past | |
4398 | the area declared by REG_PARM_STACK_SPACE will allocate | |
4399 | space appropriately, and will not copy the data onto the | |
4400 | stack, exactly as we desire. | |
4401 | ||
4402 | This is due to locate_and_pad_parm being called in | |
4403 | expand_call whenever reg_parm_stack_space > 0, which | |
4404 | while benefical to our example here, would seem to be | |
4405 | in error from what had been intended. Ho hum... -- r~ */ | |
4406 | #endif | |
4fb4e4b8 DE |
4407 | return reg; |
4408 | } | |
4409 | else | |
4410 | { | |
82d6b402 RH |
4411 | rtx v0, v1; |
4412 | ||
4fb4e4b8 DE |
4413 | if ((regno - SPARC_FP_ARG_FIRST) < SPARC_INT_ARG_MAX * 2) |
4414 | { | |
82d6b402 RH |
4415 | int intreg; |
4416 | ||
4417 | /* On incoming, we don't need to know that the value | |
4418 | is passed in %f0 and %i0, and it confuses other parts | |
4419 | causing needless spillage even on the simplest cases. */ | |
4420 | if (incoming_p) | |
4421 | return reg; | |
4422 | ||
4423 | intreg = (SPARC_OUTGOING_INT_ARG_FIRST | |
4424 | + (regno - SPARC_FP_ARG_FIRST) / 2); | |
4425 | ||
4426 | v0 = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx); | |
4427 | v1 = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_REG (mode, intreg), | |
4428 | const0_rtx); | |
4429 | return gen_rtx_PARALLEL (mode, gen_rtvec (2, v0, v1)); | |
4fb4e4b8 DE |
4430 | } |
4431 | else | |
82d6b402 RH |
4432 | { |
4433 | v0 = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx); | |
4434 | v1 = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx); | |
4435 | return gen_rtx_PARALLEL (mode, gen_rtvec (2, v0, v1)); | |
4436 | } | |
4fb4e4b8 DE |
4437 | } |
4438 | } | |
4439 | else if (type && TREE_CODE (type) == RECORD_TYPE) | |
4440 | { | |
4441 | /* Structures up to 16 bytes in size are passed in arg slots on the | |
4442 | stack and are promoted to registers where possible. */ | |
4fb4e4b8 DE |
4443 | |
4444 | if (int_size_in_bytes (type) > 16) | |
4445 | abort (); /* shouldn't get here */ | |
4446 | ||
1eac9f59 | 4447 | return function_arg_record_value (type, mode, slotno, named, regbase); |
4fb4e4b8 DE |
4448 | } |
4449 | else if (type && TREE_CODE (type) == UNION_TYPE) | |
4450 | { | |
4451 | enum machine_mode mode; | |
4452 | int bytes = int_size_in_bytes (type); | |
4453 | ||
4454 | if (bytes > 16) | |
4455 | abort (); | |
4456 | ||
4457 | mode = mode_for_size (bytes * BITS_PER_UNIT, MODE_INT, 0); | |
254110c2 | 4458 | reg = gen_rtx_REG (mode, regno); |
4fb4e4b8 | 4459 | } |
a7acd911 | 4460 | else |
4fb4e4b8 DE |
4461 | { |
4462 | /* Scalar or complex int. */ | |
254110c2 | 4463 | reg = gen_rtx_REG (mode, regno); |
4fb4e4b8 DE |
4464 | } |
4465 | ||
4466 | return reg; | |
4467 | } | |
a7acd911 | 4468 | |
4fb4e4b8 DE |
4469 | /* Handle the FUNCTION_ARG_PARTIAL_NREGS macro. |
4470 | For an arg passed partly in registers and partly in memory, | |
4471 | this is the number of registers used. | |
4472 | For args passed entirely in registers or entirely in memory, zero. | |
61a55e8b | 4473 | |
4fb4e4b8 DE |
4474 | Any arg that starts in the first 6 regs but won't entirely fit in them |
4475 | needs partial registers on v8. On v9, structures with integer | |
4476 | values in arg slots 5,6 will be passed in %o5 and SP+176, and complex fp | |
4477 | values that begin in the last fp reg [where "last fp reg" varies with the | |
4478 | mode] will be split between that reg and memory. */ | |
61a55e8b | 4479 | |
4fb4e4b8 DE |
4480 | int |
4481 | function_arg_partial_nregs (cum, mode, type, named) | |
4482 | const CUMULATIVE_ARGS *cum; | |
4483 | enum machine_mode mode; | |
4484 | tree type; | |
4485 | int named; | |
4486 | { | |
4487 | int slotno, regno, padding; | |
61a55e8b | 4488 | |
4fb4e4b8 DE |
4489 | /* We pass 0 for incoming_p here, it doesn't matter. */ |
4490 | slotno = function_arg_slotno (cum, mode, type, named, 0, ®no, &padding); | |
4491 | ||
4492 | if (slotno == -1) | |
4493 | return 0; | |
4494 | ||
4495 | if (TARGET_ARCH32) | |
bf62bbf1 | 4496 | { |
4fb4e4b8 DE |
4497 | if ((slotno + (mode == BLKmode |
4498 | ? ROUND_ADVANCE (int_size_in_bytes (type)) | |
4499 | : ROUND_ADVANCE (GET_MODE_SIZE (mode)))) | |
4500 | > NPARM_REGS (SImode)) | |
4501 | return NPARM_REGS (SImode) - slotno; | |
4502 | return 0; | |
4503 | } | |
4504 | else | |
4505 | { | |
4506 | if (type && AGGREGATE_TYPE_P (type)) | |
4507 | { | |
4508 | int size = int_size_in_bytes (type); | |
4509 | int align = TYPE_ALIGN (type); | |
bf62bbf1 | 4510 | |
4fb4e4b8 DE |
4511 | if (align == 16) |
4512 | slotno += slotno & 1; | |
4513 | if (size > 8 && size <= 16 | |
4514 | && slotno == SPARC_INT_ARG_MAX - 1) | |
4515 | return 1; | |
4516 | } | |
4517 | else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_INT | |
4518 | || (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT | |
4519 | && ! TARGET_FPU)) | |
4520 | { | |
4521 | if (GET_MODE_ALIGNMENT (mode) == 128) | |
4522 | { | |
4523 | slotno += slotno & 1; | |
4524 | if (slotno == SPARC_INT_ARG_MAX - 2) | |
4525 | return 1; | |
4526 | } | |
4527 | else | |
4528 | { | |
4529 | if (slotno == SPARC_INT_ARG_MAX - 1) | |
4530 | return 1; | |
4531 | } | |
4532 | } | |
4533 | else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT) | |
4534 | { | |
4535 | if (GET_MODE_ALIGNMENT (mode) == 128) | |
4536 | slotno += slotno & 1; | |
4537 | if ((slotno + GET_MODE_SIZE (mode) / UNITS_PER_WORD) | |
4538 | > SPARC_FP_ARG_MAX) | |
4539 | return 1; | |
4540 | } | |
4541 | return 0; | |
bf62bbf1 | 4542 | } |
4fb4e4b8 | 4543 | } |
61a55e8b | 4544 | |
4fb4e4b8 DE |
4545 | /* Handle the FUNCTION_ARG_PASS_BY_REFERENCE macro. |
4546 | !v9: The SPARC ABI stipulates passing struct arguments (of any size) and | |
4547 | quad-precision floats by invisible reference. | |
82d6b402 | 4548 | v9: Aggregates greater than 16 bytes are passed by reference. |
4fb4e4b8 DE |
4549 | For Pascal, also pass arrays by reference. */ |
4550 | ||
4551 | int | |
4552 | function_arg_pass_by_reference (cum, mode, type, named) | |
db3d4438 | 4553 | const CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED; |
4fb4e4b8 DE |
4554 | enum machine_mode mode; |
4555 | tree type; | |
db3d4438 | 4556 | int named ATTRIBUTE_UNUSED; |
4fb4e4b8 DE |
4557 | { |
4558 | if (TARGET_ARCH32) | |
eadceb59 | 4559 | { |
5e9defae | 4560 | return ((type && AGGREGATE_TYPE_P (type)) |
4fb4e4b8 DE |
4561 | || mode == TFmode || mode == TCmode); |
4562 | } | |
4563 | else | |
4564 | { | |
4565 | return ((type && TREE_CODE (type) == ARRAY_TYPE) | |
82d6b402 RH |
4566 | /* Consider complex values as aggregates, so care for TCmode. */ |
4567 | || GET_MODE_SIZE (mode) > 16 | |
4fb4e4b8 DE |
4568 | || (type && AGGREGATE_TYPE_P (type) |
4569 | && int_size_in_bytes (type) > 16)); | |
4570 | } | |
4571 | } | |
4572 | ||
4573 | /* Handle the FUNCTION_ARG_ADVANCE macro. | |
4574 | Update the data in CUM to advance over an argument | |
4575 | of mode MODE and data type TYPE. | |
4576 | TYPE is null for libcalls where that information may not be available. */ | |
4577 | ||
4578 | void | |
4579 | function_arg_advance (cum, mode, type, named) | |
4580 | CUMULATIVE_ARGS *cum; | |
4581 | enum machine_mode mode; | |
4582 | tree type; | |
4583 | int named; | |
4584 | { | |
4585 | int slotno, regno, padding; | |
4586 | ||
4587 | /* We pass 0 for incoming_p here, it doesn't matter. */ | |
4588 | slotno = function_arg_slotno (cum, mode, type, named, 0, ®no, &padding); | |
4589 | ||
4590 | /* If register required leading padding, add it. */ | |
4591 | if (slotno != -1) | |
4592 | cum->words += padding; | |
eadceb59 | 4593 | |
4fb4e4b8 DE |
4594 | if (TARGET_ARCH32) |
4595 | { | |
4596 | cum->words += (mode != BLKmode | |
4597 | ? ROUND_ADVANCE (GET_MODE_SIZE (mode)) | |
4598 | : ROUND_ADVANCE (int_size_in_bytes (type))); | |
4599 | } | |
4600 | else | |
4601 | { | |
4602 | if (type && AGGREGATE_TYPE_P (type)) | |
4603 | { | |
4604 | int size = int_size_in_bytes (type); | |
4605 | ||
4606 | if (size <= 8) | |
4607 | ++cum->words; | |
4608 | else if (size <= 16) | |
4609 | cum->words += 2; | |
4610 | else /* passed by reference */ | |
4611 | ++cum->words; | |
4612 | } | |
4613 | else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_INT) | |
4614 | { | |
4615 | cum->words += 2; | |
4616 | } | |
4617 | else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT) | |
4618 | { | |
4619 | cum->words += GET_MODE_SIZE (mode) / UNITS_PER_WORD; | |
4620 | } | |
4621 | else | |
4622 | { | |
4623 | cum->words += (mode != BLKmode | |
4624 | ? ROUND_ADVANCE (GET_MODE_SIZE (mode)) | |
4625 | : ROUND_ADVANCE (int_size_in_bytes (type))); | |
4626 | } | |
eadceb59 | 4627 | } |
4fb4e4b8 | 4628 | } |
eadceb59 | 4629 | |
4fb4e4b8 DE |
4630 | /* Handle the FUNCTION_ARG_PADDING macro. |
4631 | For the 64 bit ABI structs are always stored left shifted in their | |
4632 | argument slot. */ | |
4633 | ||
4634 | enum direction | |
4635 | function_arg_padding (mode, type) | |
4636 | enum machine_mode mode; | |
4637 | tree type; | |
4638 | { | |
c85f7c16 JL |
4639 | if (TARGET_ARCH64 && type != 0 && AGGREGATE_TYPE_P (type)) |
4640 | return upward; | |
61a55e8b | 4641 | |
4fb4e4b8 DE |
4642 | /* This is the default definition. */ |
4643 | return (! BYTES_BIG_ENDIAN | |
4644 | ? upward | |
4645 | : ((mode == BLKmode | |
4646 | ? (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST | |
4647 | && int_size_in_bytes (type) < (PARM_BOUNDARY / BITS_PER_UNIT)) | |
4648 | : GET_MODE_BITSIZE (mode) < PARM_BOUNDARY) | |
4649 | ? downward : upward)); | |
61a55e8b | 4650 | } |
82d6b402 RH |
4651 | |
4652 | /* Handle FUNCTION_VALUE, FUNCTION_OUTGOING_VALUE, and LIBCALL_VALUE macros. | |
4653 | For v9, function return values are subject to the same rules as arguments, | |
4654 | except that up to 32-bytes may be returned in registers. */ | |
4655 | ||
4656 | rtx | |
4657 | function_value (type, mode, incoming_p) | |
4658 | tree type; | |
4659 | enum machine_mode mode; | |
4660 | int incoming_p; | |
4661 | { | |
4662 | int regno; | |
4663 | int regbase = (incoming_p | |
4664 | ? SPARC_OUTGOING_INT_ARG_FIRST | |
4665 | : SPARC_INCOMING_INT_ARG_FIRST); | |
4666 | ||
4667 | if (TARGET_ARCH64 && type) | |
4668 | { | |
4669 | if (TREE_CODE (type) == RECORD_TYPE) | |
4670 | { | |
4671 | /* Structures up to 32 bytes in size are passed in registers, | |
4672 | promoted to fp registers where possible. */ | |
4673 | ||
4674 | if (int_size_in_bytes (type) > 32) | |
4675 | abort (); /* shouldn't get here */ | |
4676 | ||
1eac9f59 | 4677 | return function_arg_record_value (type, mode, 0, 1, regbase); |
82d6b402 RH |
4678 | } |
4679 | else if (TREE_CODE (type) == UNION_TYPE) | |
4680 | { | |
4681 | int bytes = int_size_in_bytes (type); | |
4682 | ||
4683 | if (bytes > 32) | |
4684 | abort (); | |
4685 | ||
4686 | mode = mode_for_size (bytes * BITS_PER_UNIT, MODE_INT, 0); | |
4687 | } | |
4688 | } | |
3c6088d2 JJ |
4689 | |
4690 | if (TARGET_ARCH64 | |
4691 | && GET_MODE_CLASS (mode) == MODE_INT | |
4692 | && GET_MODE_SIZE (mode) < UNITS_PER_WORD | |
4693 | && type && TREE_CODE (type) != UNION_TYPE) | |
4694 | mode = DImode; | |
82d6b402 RH |
4695 | |
4696 | if (incoming_p) | |
4697 | regno = BASE_RETURN_VALUE_REG (mode); | |
4698 | else | |
4699 | regno = BASE_OUTGOING_VALUE_REG (mode); | |
4700 | ||
254110c2 | 4701 | return gen_rtx_REG (mode, regno); |
82d6b402 RH |
4702 | } |
4703 | ||
648d2ffc RH |
4704 | /* Do what is necessary for `va_start'. We look at the current function |
4705 | to determine if stdarg or varargs is used and return the address of | |
4706 | the first unnamed parameter. */ | |
3ea1fdd3 JW |
4707 | |
4708 | rtx | |
648d2ffc | 4709 | sparc_builtin_saveregs () |
3ea1fdd3 | 4710 | { |
4fb4e4b8 | 4711 | int first_reg = current_function_args_info.words; |
3ea1fdd3 JW |
4712 | rtx address; |
4713 | int regno; | |
4714 | ||
4fb4e4b8 | 4715 | for (regno = first_reg; regno < NPARM_REGS (word_mode); regno++) |
254110c2 DM |
4716 | emit_move_insn (gen_rtx_MEM (word_mode, |
4717 | gen_rtx_PLUS (Pmode, | |
3ea1fdd3 JW |
4718 | frame_pointer_rtx, |
4719 | GEN_INT (STACK_POINTER_OFFSET | |
4720 | + UNITS_PER_WORD * regno))), | |
254110c2 | 4721 | gen_rtx_REG (word_mode, |
4fb4e4b8 | 4722 | BASE_INCOMING_ARG_REG (word_mode) + regno)); |
3ea1fdd3 | 4723 | |
254110c2 | 4724 | address = gen_rtx_PLUS (Pmode, |
3ea1fdd3 JW |
4725 | frame_pointer_rtx, |
4726 | GEN_INT (STACK_POINTER_OFFSET | |
4727 | + UNITS_PER_WORD * first_reg)); | |
4728 | ||
7d384cc0 | 4729 | if (current_function_check_memory_usage |
4fb4e4b8 | 4730 | && first_reg < NPARM_REGS (word_mode)) |
eadceb59 RK |
4731 | emit_library_call (chkr_set_right_libfunc, 1, VOIDmode, 3, |
4732 | address, ptr_mode, | |
4733 | GEN_INT (UNITS_PER_WORD | |
4fb4e4b8 | 4734 | * (NPARM_REGS (word_mode) - first_reg)), |
956d6950 JL |
4735 | TYPE_MODE (sizetype), GEN_INT (MEMORY_USE_RW), |
4736 | TYPE_MODE (integer_type_node)); | |
eadceb59 | 4737 | |
3ea1fdd3 JW |
4738 | return address; |
4739 | } | |
a8b2c8a1 RH |
4740 | |
4741 | /* Implement `va_start' for varargs and stdarg. */ | |
4742 | ||
4743 | void | |
4744 | sparc_va_start (stdarg_p, valist, nextarg) | |
4745 | int stdarg_p ATTRIBUTE_UNUSED; | |
4746 | tree valist; | |
4747 | rtx nextarg; | |
4748 | { | |
4749 | nextarg = expand_builtin_saveregs (); | |
4750 | std_expand_builtin_va_start (1, valist, nextarg); | |
4751 | } | |
4752 | ||
4753 | /* Implement `va_arg'. */ | |
4754 | ||
4755 | rtx | |
4756 | sparc_va_arg (valist, type) | |
4757 | tree valist, type; | |
4758 | { | |
4759 | HOST_WIDE_INT size, rsize, align; | |
da09e317 | 4760 | tree addr, incr; |
a8b2c8a1 RH |
4761 | rtx addr_rtx; |
4762 | int indirect = 0; | |
4763 | ||
4764 | /* Round up sizeof(type) to a word. */ | |
4765 | size = int_size_in_bytes (type); | |
4766 | rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD; | |
4767 | align = 0; | |
4768 | ||
4769 | if (TARGET_ARCH64) | |
4770 | { | |
fbd039b2 | 4771 | if (TYPE_ALIGN (type) >= 2 * (unsigned) BITS_PER_WORD) |
a8b2c8a1 RH |
4772 | align = 2 * UNITS_PER_WORD; |
4773 | ||
f34e52f7 | 4774 | if (AGGREGATE_TYPE_P (type)) |
a8b2c8a1 | 4775 | { |
f34e52f7 JJ |
4776 | if (size > 16) |
4777 | { | |
4778 | indirect = 1; | |
4779 | size = rsize = UNITS_PER_WORD; | |
4780 | } | |
4781 | else | |
4782 | size = rsize; | |
a8b2c8a1 RH |
4783 | } |
4784 | } | |
4785 | else | |
4786 | { | |
4787 | if (AGGREGATE_TYPE_P (type) | |
4788 | || TYPE_MODE (type) == TFmode | |
4789 | || TYPE_MODE (type) == TCmode) | |
4790 | { | |
4791 | indirect = 1; | |
4792 | size = rsize = UNITS_PER_WORD; | |
4793 | } | |
4794 | else | |
4795 | { | |
4796 | /* ??? The old va-sparc.h implementation, for 8 byte objects | |
4797 | copied stuff to a temporary -- I don't see that that | |
4798 | provides any more alignment than the stack slot did. */ | |
4799 | } | |
4800 | } | |
4801 | ||
4802 | incr = valist; | |
4803 | if (align) | |
4804 | { | |
4805 | incr = fold (build (PLUS_EXPR, ptr_type_node, incr, | |
4806 | build_int_2 (align - 1, 0))); | |
4807 | incr = fold (build (BIT_AND_EXPR, ptr_type_node, incr, | |
4808 | build_int_2 (-align, -1))); | |
4809 | } | |
4810 | ||
4811 | addr = incr = save_expr (incr); | |
4812 | if (BYTES_BIG_ENDIAN && size < rsize) | |
4813 | { | |
4814 | addr = fold (build (PLUS_EXPR, ptr_type_node, incr, | |
4815 | build_int_2 (rsize - size, 0))); | |
4816 | } | |
4817 | incr = fold (build (PLUS_EXPR, ptr_type_node, incr, | |
4818 | build_int_2 (rsize, 0))); | |
4819 | ||
4820 | incr = build (MODIFY_EXPR, ptr_type_node, valist, incr); | |
4821 | TREE_SIDE_EFFECTS (incr) = 1; | |
4822 | expand_expr (incr, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
4823 | ||
4824 | addr_rtx = expand_expr (addr, NULL, Pmode, EXPAND_NORMAL); | |
4825 | ||
4826 | if (indirect) | |
4827 | { | |
4828 | addr_rtx = force_reg (Pmode, addr_rtx); | |
4829 | addr_rtx = gen_rtx_MEM (Pmode, addr_rtx); | |
4830 | MEM_ALIAS_SET (addr_rtx) = get_varargs_alias_set (); | |
4831 | } | |
4832 | ||
4833 | return addr_rtx; | |
4834 | } | |
ab835497 RK |
4835 | \f |
4836 | /* Return the string to output a conditional branch to LABEL, which is | |
c4ce6853 DE |
4837 | the operand number of the label. OP is the conditional expression. |
4838 | XEXP (OP, 0) is assumed to be a condition code register (integer or | |
4839 | floating point) and its mode specifies what kind of comparison we made. | |
61a55e8b | 4840 | |
ab835497 RK |
4841 | REVERSED is non-zero if we should reverse the sense of the comparison. |
4842 | ||
4843 | ANNUL is non-zero if we should generate an annulling branch. | |
4844 | ||
c6b0465b JC |
4845 | NOOP is non-zero if we have to follow this branch by a noop. |
4846 | ||
4847 | INSN, if set, is the insn. */ | |
ab835497 RK |
4848 | |
4849 | char * | |
c6b0465b | 4850 | output_cbranch (op, label, reversed, annul, noop, insn) |
c4ce6853 | 4851 | rtx op; |
ab835497 RK |
4852 | int label; |
4853 | int reversed, annul, noop; | |
c6b0465b | 4854 | rtx insn; |
ab835497 | 4855 | { |
e0d80184 | 4856 | static char string[32]; |
ab835497 | 4857 | enum rtx_code code = GET_CODE (op); |
c4ce6853 DE |
4858 | rtx cc_reg = XEXP (op, 0); |
4859 | enum machine_mode mode = GET_MODE (cc_reg); | |
e0d80184 DM |
4860 | static char v8_labelno[] = "%lX"; |
4861 | static char v9_icc_labelno[] = "%%icc, %lX"; | |
4862 | static char v9_xcc_labelno[] = "%%xcc, %lX"; | |
4863 | static char v9_fcc_labelno[] = "%%fccX, %lY"; | |
61a55e8b | 4864 | char *labelno; |
e267e177 | 4865 | const char *branch; |
e0d80184 | 4866 | int labeloff, spaces = 8; |
61a55e8b | 4867 | |
e267e177 | 4868 | if (reversed) |
ab835497 | 4869 | { |
e267e177 RH |
4870 | /* Reversal of FP compares takes care -- an ordered compare |
4871 | becomes an unordered compare and vice versa. */ | |
4d449554 | 4872 | if (mode == CCFPmode || mode == CCFPEmode) |
7913f3d0 | 4873 | code = reverse_condition_maybe_unordered (code); |
ab835497 | 4874 | else |
e267e177 | 4875 | code = reverse_condition (code); |
ab835497 RK |
4876 | } |
4877 | ||
e267e177 RH |
4878 | /* Start by writing the branch condition. */ |
4879 | if (mode == CCFPmode || mode == CCFPEmode) | |
5850dc00 RH |
4880 | { |
4881 | switch (code) | |
4882 | { | |
4883 | case NE: | |
4884 | branch = "fbne"; | |
4885 | break; | |
4886 | case EQ: | |
4887 | branch = "fbe"; | |
4888 | break; | |
4889 | case GE: | |
4890 | branch = "fbge"; | |
4891 | break; | |
4892 | case GT: | |
4893 | branch = "fbg"; | |
4894 | break; | |
4895 | case LE: | |
4896 | branch = "fble"; | |
4897 | break; | |
4898 | case LT: | |
4899 | branch = "fbl"; | |
4900 | break; | |
4901 | case UNORDERED: | |
4902 | branch = "fbu"; | |
4903 | break; | |
4904 | case ORDERED: | |
4905 | branch = "fbo"; | |
4906 | break; | |
4907 | case UNGT: | |
4908 | branch = "fbug"; | |
4909 | break; | |
4910 | case UNLT: | |
4911 | branch = "fbul"; | |
4912 | break; | |
4913 | case UNEQ: | |
4914 | branch = "fbue"; | |
4915 | break; | |
4916 | case UNGE: | |
4917 | branch = "fbuge"; | |
4918 | break; | |
4919 | case UNLE: | |
4920 | branch = "fbule"; | |
4921 | break; | |
4922 | case LTGT: | |
4923 | branch = "fblg"; | |
4924 | break; | |
4925 | ||
4926 | default: | |
4927 | abort (); | |
4928 | } | |
4929 | ||
4930 | /* ??? !v9: FP branches cannot be preceded by another floating point | |
4931 | insn. Because there is currently no concept of pre-delay slots, | |
4932 | we can fix this only by always emitting a nop before a floating | |
4933 | point branch. */ | |
4934 | ||
4935 | string[0] = '\0'; | |
4936 | if (! TARGET_V9) | |
4937 | strcpy (string, "nop\n\t"); | |
4938 | strcat (string, branch); | |
4939 | } | |
e267e177 | 4940 | else |
5850dc00 RH |
4941 | { |
4942 | switch (code) | |
4943 | { | |
4944 | case NE: | |
4945 | branch = "bne"; | |
4946 | break; | |
4947 | case EQ: | |
4948 | branch = "be"; | |
4949 | break; | |
4950 | case GE: | |
4951 | if (mode == CC_NOOVmode) | |
4952 | branch = "bpos"; | |
4953 | else | |
4954 | branch = "bge"; | |
4955 | break; | |
4956 | case GT: | |
4957 | branch = "bg"; | |
4958 | break; | |
4959 | case LE: | |
4960 | branch = "ble"; | |
4961 | break; | |
4962 | case LT: | |
4963 | if (mode == CC_NOOVmode) | |
4964 | branch = "bneg"; | |
4965 | else | |
4966 | branch = "bl"; | |
4967 | break; | |
4968 | case GEU: | |
4969 | branch = "bgeu"; | |
4970 | break; | |
4971 | case GTU: | |
4972 | branch = "bgu"; | |
4973 | break; | |
4974 | case LEU: | |
4975 | branch = "bleu"; | |
4976 | break; | |
4977 | case LTU: | |
4978 | branch = "blu"; | |
4979 | break; | |
4980 | ||
4981 | default: | |
4982 | abort (); | |
4983 | } | |
4984 | strcpy (string, branch); | |
4985 | } | |
e267e177 RH |
4986 | spaces -= strlen (branch); |
4987 | ||
ab835497 RK |
4988 | /* Now add the annulling, the label, and a possible noop. */ |
4989 | if (annul) | |
e0d80184 DM |
4990 | { |
4991 | strcat (string, ",a"); | |
4992 | spaces -= 2; | |
4993 | } | |
ab835497 | 4994 | |
61a55e8b DE |
4995 | if (! TARGET_V9) |
4996 | { | |
e0d80184 | 4997 | labeloff = 2; |
61a55e8b DE |
4998 | labelno = v8_labelno; |
4999 | } | |
5000 | else | |
5001 | { | |
c6b0465b JC |
5002 | rtx note; |
5003 | ||
5004 | if (insn && (note = find_reg_note (insn, REG_BR_PRED, NULL_RTX))) | |
e0d80184 DM |
5005 | { |
5006 | strcat (string, | |
5007 | INTVAL (XEXP (note, 0)) & ATTR_FLAG_likely ? ",pt" : ",pn"); | |
5008 | spaces -= 3; | |
5009 | } | |
c6b0465b | 5010 | |
61a55e8b DE |
5011 | labeloff = 9; |
5012 | if (mode == CCFPmode || mode == CCFPEmode) | |
5013 | { | |
5014 | labeloff = 10; | |
5015 | labelno = v9_fcc_labelno; | |
5016 | /* Set the char indicating the number of the fcc reg to use. */ | |
e0d80184 | 5017 | labelno[5] = REGNO (cc_reg) - SPARC_FIRST_V9_FCC_REG + '0'; |
61a55e8b DE |
5018 | } |
5019 | else if (mode == CCXmode || mode == CCX_NOOVmode) | |
5020 | labelno = v9_xcc_labelno; | |
5021 | else | |
5022 | labelno = v9_icc_labelno; | |
5023 | } | |
5024 | /* Set the char indicating the number of the operand containing the | |
5025 | label_ref. */ | |
5026 | labelno[labeloff] = label + '0'; | |
e0d80184 DM |
5027 | if (spaces > 0) |
5028 | strcat (string, "\t"); | |
5029 | else | |
5030 | strcat (string, " "); | |
61a55e8b DE |
5031 | strcat (string, labelno); |
5032 | ||
5033 | if (noop) | |
5034 | strcat (string, "\n\tnop"); | |
5035 | ||
5036 | return string; | |
5037 | } | |
5038 | ||
47ac041c JJ |
5039 | /* Emit a library call comparison between floating point X and Y. |
5040 | COMPARISON is the rtl operator to compare with (EQ, NE, GT, etc.). | |
5041 | TARGET_ARCH64 uses _Qp_* functions, which use pointers to TFmode | |
5042 | values as arguments instead of the TFmode registers themselves, | |
5043 | that's why we cannot call emit_float_lib_cmp. */ | |
5044 | void | |
5045 | sparc_emit_float_lib_cmp (x, y, comparison) | |
5046 | rtx x, y; | |
5047 | enum rtx_code comparison; | |
5048 | { | |
5c5c34a4 | 5049 | char *qpfunc; |
5c5c34a4 JJ |
5050 | rtx slot0, slot1, result, tem, tem2; |
5051 | enum machine_mode mode; | |
47ac041c JJ |
5052 | |
5053 | switch (comparison) | |
5054 | { | |
5055 | case EQ: | |
5c5c34a4 | 5056 | qpfunc = (TARGET_ARCH64) ? "_Qp_feq" : "_Q_feq"; |
47ac041c JJ |
5057 | break; |
5058 | ||
5059 | case NE: | |
5c5c34a4 | 5060 | qpfunc = (TARGET_ARCH64) ? "_Qp_fne" : "_Q_fne"; |
47ac041c JJ |
5061 | break; |
5062 | ||
5063 | case GT: | |
5c5c34a4 | 5064 | qpfunc = (TARGET_ARCH64) ? "_Qp_fgt" : "_Q_fgt"; |
47ac041c JJ |
5065 | break; |
5066 | ||
5067 | case GE: | |
5c5c34a4 | 5068 | qpfunc = (TARGET_ARCH64) ? "_Qp_fge" : "_Q_fge"; |
47ac041c JJ |
5069 | break; |
5070 | ||
5071 | case LT: | |
5c5c34a4 | 5072 | qpfunc = (TARGET_ARCH64) ? "_Qp_flt" : "_Q_flt"; |
47ac041c JJ |
5073 | break; |
5074 | ||
5075 | case LE: | |
5c5c34a4 JJ |
5076 | qpfunc = (TARGET_ARCH64) ? "_Qp_fle" : "_Q_fle"; |
5077 | break; | |
5078 | ||
5079 | case ORDERED: | |
5080 | case UNORDERED: | |
5081 | case UNGT: | |
5082 | case UNLT: | |
5083 | case UNEQ: | |
5084 | case UNGE: | |
5085 | case UNLE: | |
5086 | case LTGT: | |
5087 | qpfunc = (TARGET_ARCH64) ? "_Qp_cmp" : "_Q_cmp"; | |
47ac041c JJ |
5088 | break; |
5089 | ||
5090 | default: | |
5091 | abort(); | |
5092 | break; | |
5093 | } | |
5094 | ||
5c5c34a4 | 5095 | if (TARGET_ARCH64) |
47ac041c | 5096 | { |
5c5c34a4 JJ |
5097 | if (GET_CODE (x) != MEM) |
5098 | { | |
5099 | slot0 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0); | |
5100 | emit_insn (gen_rtx_SET (VOIDmode, slot0, x)); | |
5101 | } | |
5102 | else | |
5103 | slot0 = x; | |
5104 | ||
5105 | if (GET_CODE (y) != MEM) | |
5106 | { | |
5107 | slot1 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0); | |
5108 | emit_insn (gen_rtx_SET (VOIDmode, slot1, y)); | |
5109 | } | |
5110 | else | |
5111 | slot1 = y; | |
47ac041c | 5112 | |
5c5c34a4 JJ |
5113 | emit_library_call (gen_rtx_SYMBOL_REF (Pmode, qpfunc), 1, |
5114 | DImode, 2, | |
5115 | XEXP (slot0, 0), Pmode, | |
5116 | XEXP (slot1, 0), Pmode); | |
5117 | ||
5118 | mode = DImode; | |
5119 | } | |
5120 | else | |
47ac041c | 5121 | { |
5c5c34a4 JJ |
5122 | emit_library_call (gen_rtx_SYMBOL_REF (Pmode, qpfunc), 1, |
5123 | SImode, 2, | |
5124 | x, TFmode, y, TFmode); | |
5125 | ||
5126 | mode = SImode; | |
47ac041c JJ |
5127 | } |
5128 | ||
47ac041c JJ |
5129 | |
5130 | /* Immediately move the result of the libcall into a pseudo | |
5131 | register so reload doesn't clobber the value if it needs | |
5132 | the return register for a spill reg. */ | |
5c5c34a4 JJ |
5133 | result = gen_reg_rtx (mode); |
5134 | emit_move_insn (result, hard_libcall_value (mode)); | |
47ac041c | 5135 | |
5c5c34a4 JJ |
5136 | switch (comparison) |
5137 | { | |
5138 | default: | |
5139 | emit_cmp_insn (result, const0_rtx, NE, | |
5140 | NULL_RTX, mode, 0, 0); | |
5141 | break; | |
5142 | case ORDERED: | |
5143 | case UNORDERED: | |
5144 | emit_cmp_insn (result, GEN_INT(3), | |
5145 | (comparison == UNORDERED) ? EQ : NE, | |
5146 | NULL_RTX, mode, 0, 0); | |
5147 | break; | |
5148 | case UNGT: | |
5149 | case UNGE: | |
5150 | emit_cmp_insn (result, const1_rtx, | |
5151 | (comparison == UNGT) ? GT : NE, | |
5152 | NULL_RTX, mode, 0, 0); | |
5153 | break; | |
5154 | case UNLE: | |
5155 | emit_cmp_insn (result, const2_rtx, NE, | |
5156 | NULL_RTX, mode, 0, 0); | |
5157 | break; | |
5158 | case UNLT: | |
5159 | tem = gen_reg_rtx (mode); | |
5160 | if (TARGET_ARCH32) | |
5161 | emit_insn (gen_andsi3 (tem, result, const1_rtx)); | |
5162 | else | |
5163 | emit_insn (gen_anddi3 (tem, result, const1_rtx)); | |
5164 | emit_cmp_insn (tem, const0_rtx, NE, | |
5165 | NULL_RTX, mode, 0, 0); | |
5166 | break; | |
5167 | case UNEQ: | |
5168 | case LTGT: | |
5169 | tem = gen_reg_rtx (mode); | |
5170 | if (TARGET_ARCH32) | |
5171 | emit_insn (gen_addsi3 (tem, result, const1_rtx)); | |
5172 | else | |
5173 | emit_insn (gen_adddi3 (tem, result, const1_rtx)); | |
5174 | tem2 = gen_reg_rtx (mode); | |
5175 | if (TARGET_ARCH32) | |
5176 | emit_insn (gen_andsi3 (tem2, tem, const2_rtx)); | |
5177 | else | |
5178 | emit_insn (gen_anddi3 (tem2, tem, const2_rtx)); | |
5179 | emit_cmp_insn (tem2, const0_rtx, | |
5180 | (comparison == UNEQ) ? EQ : NE, | |
5181 | NULL_RTX, mode, 0, 0); | |
5182 | break; | |
5183 | } | |
47ac041c | 5184 | } |
5c5c34a4 | 5185 | |
61a55e8b DE |
5186 | /* Return the string to output a conditional branch to LABEL, testing |
5187 | register REG. LABEL is the operand number of the label; REG is the | |
5188 | operand number of the reg. OP is the conditional expression. The mode | |
5189 | of REG says what kind of comparison we made. | |
5190 | ||
5191 | REVERSED is non-zero if we should reverse the sense of the comparison. | |
5192 | ||
5193 | ANNUL is non-zero if we should generate an annulling branch. | |
5194 | ||
5195 | NOOP is non-zero if we have to follow this branch by a noop. */ | |
5196 | ||
5197 | char * | |
e0d80184 | 5198 | output_v9branch (op, reg, label, reversed, annul, noop, insn) |
61a55e8b DE |
5199 | rtx op; |
5200 | int reg, label; | |
5201 | int reversed, annul, noop; | |
e0d80184 | 5202 | rtx insn; |
61a55e8b DE |
5203 | { |
5204 | static char string[20]; | |
5205 | enum rtx_code code = GET_CODE (op); | |
5206 | enum machine_mode mode = GET_MODE (XEXP (op, 0)); | |
e0d80184 DM |
5207 | static char labelno[] = "%X, %lX"; |
5208 | rtx note; | |
5209 | int spaces = 8; | |
61a55e8b DE |
5210 | |
5211 | /* If not floating-point or if EQ or NE, we can just reverse the code. */ | |
5212 | if (reversed) | |
5213 | code = reverse_condition (code), reversed = 0; | |
5214 | ||
5215 | /* Only 64 bit versions of these instructions exist. */ | |
5216 | if (mode != DImode) | |
5217 | abort (); | |
5218 | ||
5219 | /* Start by writing the branch condition. */ | |
5220 | ||
5221 | switch (code) | |
5222 | { | |
5223 | case NE: | |
5224 | strcpy (string, "brnz"); | |
e0d80184 | 5225 | spaces -= 4; |
61a55e8b DE |
5226 | break; |
5227 | ||
5228 | case EQ: | |
5229 | strcpy (string, "brz"); | |
e0d80184 | 5230 | spaces -= 3; |
61a55e8b DE |
5231 | break; |
5232 | ||
5233 | case GE: | |
5234 | strcpy (string, "brgez"); | |
e0d80184 | 5235 | spaces -= 5; |
61a55e8b DE |
5236 | break; |
5237 | ||
5238 | case LT: | |
5239 | strcpy (string, "brlz"); | |
e0d80184 | 5240 | spaces -= 4; |
61a55e8b DE |
5241 | break; |
5242 | ||
5243 | case LE: | |
5244 | strcpy (string, "brlez"); | |
e0d80184 | 5245 | spaces -= 5; |
61a55e8b DE |
5246 | break; |
5247 | ||
5248 | case GT: | |
5249 | strcpy (string, "brgz"); | |
e0d80184 | 5250 | spaces -= 4; |
61a55e8b DE |
5251 | break; |
5252 | ||
5253 | default: | |
5254 | abort (); | |
5255 | } | |
5256 | ||
5257 | /* Now add the annulling, reg, label, and nop. */ | |
5258 | if (annul) | |
e0d80184 DM |
5259 | { |
5260 | strcat (string, ",a"); | |
5261 | spaces -= 2; | |
5262 | } | |
61a55e8b | 5263 | |
e0d80184 DM |
5264 | if (insn && (note = find_reg_note (insn, REG_BR_PRED, NULL_RTX))) |
5265 | { | |
5266 | strcat (string, | |
5267 | INTVAL (XEXP (note, 0)) & ATTR_FLAG_likely ? ",pt" : ",pn"); | |
5268 | spaces -= 3; | |
5269 | } | |
61a55e8b | 5270 | |
e0d80184 | 5271 | labelno[1] = reg + '0'; |
61a55e8b | 5272 | labelno[6] = label + '0'; |
e0d80184 DM |
5273 | if (spaces > 0) |
5274 | strcat (string, "\t"); | |
5275 | else | |
5276 | strcat (string, " "); | |
ab835497 RK |
5277 | strcat (string, labelno); |
5278 | ||
5279 | if (noop) | |
5280 | strcat (string, "\n\tnop"); | |
5281 | ||
5282 | return string; | |
5283 | } | |
5284 | ||
e48addee JJ |
5285 | /* Return 1, if any of the registers of the instruction are %l[0-7] or %o[0-7]. |
5286 | Such instructions cannot be used in the delay slot of return insn on v9. | |
5287 | If TEST is 0, also rename all %i[0-7] registers to their %o[0-7] counterparts. | |
5288 | */ | |
284d86e9 | 5289 | |
e48addee JJ |
5290 | static int |
5291 | epilogue_renumber (where, test) | |
5292 | register rtx *where; | |
5293 | int test; | |
284d86e9 | 5294 | { |
e48addee JJ |
5295 | register const char *fmt; |
5296 | register int i; | |
5297 | register enum rtx_code code; | |
5298 | ||
5299 | if (*where == 0) | |
5300 | return 0; | |
5301 | ||
5302 | code = GET_CODE (*where); | |
284d86e9 JC |
5303 | |
5304 | switch (code) | |
5305 | { | |
284d86e9 | 5306 | case REG: |
e48addee JJ |
5307 | if (REGNO (*where) >= 8 && REGNO (*where) < 24) /* oX or lX */ |
5308 | return 1; | |
5309 | if (! test && REGNO (*where) >= 24 && REGNO (*where) < 32) | |
5310 | *where = gen_rtx (REG, GET_MODE (*where), OUTGOING_REGNO (REGNO(*where))); | |
5311 | case SCRATCH: | |
5312 | case CC0: | |
5313 | case PC: | |
284d86e9 JC |
5314 | case CONST_INT: |
5315 | case CONST_DOUBLE: | |
e48addee | 5316 | return 0; |
76a7c776 DM |
5317 | |
5318 | default: | |
5319 | break; | |
e48addee | 5320 | } |
284d86e9 | 5321 | |
e48addee | 5322 | fmt = GET_RTX_FORMAT (code); |
284d86e9 | 5323 | |
e48addee JJ |
5324 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) |
5325 | { | |
5326 | if (fmt[i] == 'E') | |
5327 | { | |
5328 | register int j; | |
5329 | for (j = XVECLEN (*where, i) - 1; j >= 0; j--) | |
5330 | if (epilogue_renumber (&(XVECEXP (*where, i, j)), test)) | |
5331 | return 1; | |
5332 | } | |
5333 | else if (fmt[i] == 'e' | |
5334 | && epilogue_renumber (&(XEXP (*where, i)), test)) | |
5335 | return 1; | |
284d86e9 | 5336 | } |
e48addee | 5337 | return 0; |
284d86e9 JC |
5338 | } |
5339 | ||
5340 | /* Output assembler code to return from a function. */ | |
61a55e8b | 5341 | |
3bb5de61 | 5342 | const char * |
ab835497 RK |
5343 | output_return (operands) |
5344 | rtx *operands; | |
5345 | { | |
284d86e9 JC |
5346 | rtx delay = final_sequence ? XVECEXP (final_sequence, 0, 1) : 0; |
5347 | ||
ab835497 RK |
5348 | if (leaf_label) |
5349 | { | |
5350 | operands[0] = leaf_label; | |
284d86e9 | 5351 | return "b%* %l0%("; |
ab835497 | 5352 | } |
54ff41b7 | 5353 | else if (current_function_uses_only_leaf_regs) |
ab835497 | 5354 | { |
284d86e9 JC |
5355 | /* No delay slot in a leaf function. */ |
5356 | if (delay) | |
5357 | abort (); | |
5358 | ||
915f619f JW |
5359 | /* If we didn't allocate a frame pointer for the current function, |
5360 | the stack pointer might have been adjusted. Output code to | |
5361 | restore it now. */ | |
5362 | ||
3a598fbe | 5363 | operands[0] = GEN_INT (actual_fsize); |
915f619f JW |
5364 | |
5365 | /* Use sub of negated value in first two cases instead of add to | |
5366 | allow actual_fsize == 4096. */ | |
5367 | ||
5368 | if (actual_fsize <= 4096) | |
ab835497 | 5369 | { |
61a55e8b | 5370 | if (SKIP_CALLERS_UNIMP_P) |
e0d80184 | 5371 | return "jmp\t%%o7+12\n\tsub\t%%sp, -%0, %%sp"; |
ab835497 | 5372 | else |
e0d80184 | 5373 | return "retl\n\tsub\t%%sp, -%0, %%sp"; |
ab835497 | 5374 | } |
915f619f | 5375 | else if (actual_fsize <= 8192) |
ab835497 | 5376 | { |
3a598fbe | 5377 | operands[0] = GEN_INT (actual_fsize - 4096); |
61a55e8b | 5378 | if (SKIP_CALLERS_UNIMP_P) |
e0d80184 | 5379 | return "sub\t%%sp, -4096, %%sp\n\tjmp\t%%o7+12\n\tsub\t%%sp, -%0, %%sp"; |
915f619f | 5380 | else |
e0d80184 | 5381 | return "sub\t%%sp, -4096, %%sp\n\tretl\n\tsub\t%%sp, -%0, %%sp"; |
915f619f | 5382 | } |
61a55e8b | 5383 | else if (SKIP_CALLERS_UNIMP_P) |
915f619f JW |
5384 | { |
5385 | if ((actual_fsize & 0x3ff) != 0) | |
e0d80184 | 5386 | return "sethi\t%%hi(%a0), %%g1\n\tor\t%%g1, %%lo(%a0), %%g1\n\tjmp\t%%o7+12\n\tadd\t%%sp, %%g1, %%sp"; |
ab835497 | 5387 | else |
e0d80184 | 5388 | return "sethi\t%%hi(%a0), %%g1\n\tjmp\t%%o7+12\n\tadd\t%%sp, %%g1, %%sp"; |
915f619f JW |
5389 | } |
5390 | else | |
5391 | { | |
5392 | if ((actual_fsize & 0x3ff) != 0) | |
ab835497 | 5393 | return "sethi %%hi(%a0),%%g1\n\tor %%g1,%%lo(%a0),%%g1\n\tretl\n\tadd %%sp,%%g1,%%sp"; |
915f619f JW |
5394 | else |
5395 | return "sethi %%hi(%a0),%%g1\n\tretl\n\tadd %%sp,%%g1,%%sp"; | |
ab835497 RK |
5396 | } |
5397 | } | |
284d86e9 JC |
5398 | else if (TARGET_V9) |
5399 | { | |
5400 | if (delay) | |
5401 | { | |
e48addee JJ |
5402 | epilogue_renumber (&SET_DEST (PATTERN (delay)), 0); |
5403 | epilogue_renumber (&SET_SRC (PATTERN (delay)), 0); | |
284d86e9 JC |
5404 | } |
5405 | if (SKIP_CALLERS_UNIMP_P) | |
e0d80184 | 5406 | return "return\t%%i7+12%#"; |
284d86e9 | 5407 | else |
e0d80184 | 5408 | return "return\t%%i7+8%#"; |
284d86e9 | 5409 | } |
ab835497 RK |
5410 | else |
5411 | { | |
284d86e9 JC |
5412 | if (delay) |
5413 | abort (); | |
61a55e8b | 5414 | if (SKIP_CALLERS_UNIMP_P) |
e0d80184 | 5415 | return "jmp\t%%i7+12\n\trestore"; |
ab835497 RK |
5416 | else |
5417 | return "ret\n\trestore"; | |
5418 | } | |
5419 | } | |
ab835497 RK |
5420 | \f |
5421 | /* Leaf functions and non-leaf functions have different needs. */ | |
5422 | ||
5423 | static int | |
5424 | reg_leaf_alloc_order[] = REG_LEAF_ALLOC_ORDER; | |
5425 | ||
5426 | static int | |
5427 | reg_nonleaf_alloc_order[] = REG_ALLOC_ORDER; | |
5428 | ||
5429 | static int *reg_alloc_orders[] = { | |
5430 | reg_leaf_alloc_order, | |
5431 | reg_nonleaf_alloc_order}; | |
5432 | ||
5433 | void | |
5434 | order_regs_for_local_alloc () | |
5435 | { | |
5436 | static int last_order_nonleaf = 1; | |
5437 | ||
5438 | if (regs_ever_live[15] != last_order_nonleaf) | |
5439 | { | |
5440 | last_order_nonleaf = !last_order_nonleaf; | |
d2889939 RK |
5441 | bcopy ((char *) reg_alloc_orders[last_order_nonleaf], |
5442 | (char *) reg_alloc_order, FIRST_PSEUDO_REGISTER * sizeof (int)); | |
ab835497 RK |
5443 | } |
5444 | } | |
5445 | \f | |
e0d80184 DM |
5446 | /* Return 1 if REG and MEM are legitimate enough to allow the various |
5447 | mem<-->reg splits to be run. */ | |
5448 | ||
5449 | int | |
e61c29e9 | 5450 | sparc_splitdi_legitimate (reg, mem) |
e0d80184 DM |
5451 | rtx reg; |
5452 | rtx mem; | |
5453 | { | |
e0d80184 DM |
5454 | /* Punt if we are here by mistake. */ |
5455 | if (! reload_completed) | |
9208e4b2 | 5456 | abort (); |
e0d80184 DM |
5457 | |
5458 | /* We must have an offsettable memory reference. */ | |
5459 | if (! offsettable_memref_p (mem)) | |
5460 | return 0; | |
5461 | ||
5462 | /* If we have legitimate args for ldd/std, we do not want | |
5463 | the split to happen. */ | |
5464 | if ((REGNO (reg) % 2) == 0 | |
5465 | && mem_min_alignment (mem, 8)) | |
5466 | return 0; | |
5467 | ||
5468 | /* Success. */ | |
5469 | return 1; | |
5470 | } | |
5471 | ||
e61c29e9 DM |
5472 | /* Return 1 if x and y are some kind of REG and they refer to |
5473 | different hard registers. This test is guarenteed to be | |
5474 | run after reload. */ | |
5475 | ||
5476 | int | |
5477 | sparc_absnegfloat_split_legitimate (x, y) | |
5478 | rtx x, y; | |
5479 | { | |
5480 | if (GET_CODE (x) == SUBREG) | |
5481 | x = alter_subreg (x); | |
5482 | if (GET_CODE (x) != REG) | |
5483 | return 0; | |
5484 | if (GET_CODE (y) == SUBREG) | |
5485 | y = alter_subreg (y); | |
5486 | if (GET_CODE (y) != REG) | |
5487 | return 0; | |
5488 | if (REGNO (x) == REGNO (y)) | |
5489 | return 0; | |
5490 | return 1; | |
5491 | } | |
5492 | ||
35016322 JW |
5493 | /* Return 1 if REGNO (reg1) is even and REGNO (reg1) == REGNO (reg2) - 1. |
5494 | This makes them candidates for using ldd and std insns. | |
5495 | ||
bfd6bc60 | 5496 | Note reg1 and reg2 *must* be hard registers. */ |
35016322 JW |
5497 | |
5498 | int | |
7c56249d | 5499 | registers_ok_for_ldd_peep (reg1, reg2) |
35016322 JW |
5500 | rtx reg1, reg2; |
5501 | { | |
35016322 JW |
5502 | /* We might have been passed a SUBREG. */ |
5503 | if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG) | |
5504 | return 0; | |
5505 | ||
35016322 JW |
5506 | if (REGNO (reg1) % 2 != 0) |
5507 | return 0; | |
5508 | ||
bfd6bc60 JC |
5509 | /* Integer ldd is deprecated in SPARC V9 */ |
5510 | if (TARGET_V9 && REGNO (reg1) < 32) | |
5511 | return 0; | |
5512 | ||
35016322 | 5513 | return (REGNO (reg1) == REGNO (reg2) - 1); |
35016322 JW |
5514 | } |
5515 | ||
5516 | /* Return 1 if addr1 and addr2 are suitable for use in an ldd or | |
5517 | std insn. | |
5518 | ||
5519 | This can only happen when addr1 and addr2 are consecutive memory | |
5520 | locations (addr1 + 4 == addr2). addr1 must also be aligned on a | |
5521 | 64 bit boundary (addr1 % 8 == 0). | |
5522 | ||
5523 | We know %sp and %fp are kept aligned on a 64 bit boundary. Other | |
5524 | registers are assumed to *never* be properly aligned and are | |
5525 | rejected. | |
5526 | ||
5527 | Knowing %sp and %fp are kept aligned on a 64 bit boundary, we | |
5528 | need only check that the offset for addr1 % 8 == 0. */ | |
5529 | ||
5530 | int | |
7c56249d | 5531 | addrs_ok_for_ldd_peep (addr1, addr2) |
35016322 JW |
5532 | rtx addr1, addr2; |
5533 | { | |
5534 | int reg1, offset1; | |
5535 | ||
5536 | /* Extract a register number and offset (if used) from the first addr. */ | |
5537 | if (GET_CODE (addr1) == PLUS) | |
5538 | { | |
5539 | /* If not a REG, return zero. */ | |
5540 | if (GET_CODE (XEXP (addr1, 0)) != REG) | |
5541 | return 0; | |
5542 | else | |
5543 | { | |
5544 | reg1 = REGNO (XEXP (addr1, 0)); | |
5545 | /* The offset must be constant! */ | |
5546 | if (GET_CODE (XEXP (addr1, 1)) != CONST_INT) | |
5547 | return 0; | |
5548 | offset1 = INTVAL (XEXP (addr1, 1)); | |
5549 | } | |
5550 | } | |
5551 | else if (GET_CODE (addr1) != REG) | |
5552 | return 0; | |
5553 | else | |
5554 | { | |
5555 | reg1 = REGNO (addr1); | |
5556 | /* This was a simple (mem (reg)) expression. Offset is 0. */ | |
5557 | offset1 = 0; | |
5558 | } | |
5559 | ||
5560 | /* Make sure the second address is a (mem (plus (reg) (const_int). */ | |
5561 | if (GET_CODE (addr2) != PLUS) | |
5562 | return 0; | |
5563 | ||
5564 | if (GET_CODE (XEXP (addr2, 0)) != REG | |
5565 | || GET_CODE (XEXP (addr2, 1)) != CONST_INT) | |
5566 | return 0; | |
5567 | ||
5568 | /* Only %fp and %sp are allowed. Additionally both addresses must | |
5569 | use the same register. */ | |
5570 | if (reg1 != FRAME_POINTER_REGNUM && reg1 != STACK_POINTER_REGNUM) | |
5571 | return 0; | |
5572 | ||
5573 | if (reg1 != REGNO (XEXP (addr2, 0))) | |
5574 | return 0; | |
5575 | ||
2296cba3 | 5576 | /* The first offset must be evenly divisible by 8 to ensure the |
35016322 JW |
5577 | address is 64 bit aligned. */ |
5578 | if (offset1 % 8 != 0) | |
5579 | return 0; | |
5580 | ||
5581 | /* The offset for the second addr must be 4 more than the first addr. */ | |
5582 | if (INTVAL (XEXP (addr2, 1)) != offset1 + 4) | |
5583 | return 0; | |
5584 | ||
5585 | /* All the tests passed. addr1 and addr2 are valid for ldd and std | |
5586 | instructions. */ | |
5587 | return 1; | |
5588 | } | |
7c56249d JL |
5589 | |
5590 | /* Return 1 if reg is a pseudo, or is the first register in | |
5591 | a hard register pair. This makes it a candidate for use in | |
5592 | ldd and std insns. */ | |
5593 | ||
5594 | int | |
5595 | register_ok_for_ldd (reg) | |
5596 | rtx reg; | |
5597 | { | |
7c56249d JL |
5598 | /* We might have been passed a SUBREG. */ |
5599 | if (GET_CODE (reg) != REG) | |
5600 | return 0; | |
5601 | ||
5602 | if (REGNO (reg) < FIRST_PSEUDO_REGISTER) | |
5603 | return (REGNO (reg) % 2 == 0); | |
5604 | else | |
5605 | return 1; | |
7c56249d | 5606 | } |
ab835497 | 5607 | \f |
ab835497 RK |
5608 | /* Print operand X (an rtx) in assembler syntax to file FILE. |
5609 | CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. | |
5610 | For `%' followed by punctuation, CODE is the punctuation and X is null. */ | |
5611 | ||
5612 | void | |
5613 | print_operand (file, x, code) | |
5614 | FILE *file; | |
5615 | rtx x; | |
5616 | int code; | |
5617 | { | |
5618 | switch (code) | |
5619 | { | |
5620 | case '#': | |
5621 | /* Output a 'nop' if there's nothing for the delay slot. */ | |
5622 | if (dbr_sequence_length () == 0) | |
e0d80184 | 5623 | fputs ("\n\t nop", file); |
ab835497 RK |
5624 | return; |
5625 | case '*': | |
c6ce0969 JW |
5626 | /* Output an annul flag if there's nothing for the delay slot and we |
5627 | are optimizing. This is always used with '(' below. */ | |
5628 | /* Sun OS 4.1.1 dbx can't handle an annulled unconditional branch; | |
5629 | this is a dbx bug. So, we only do this when optimizing. */ | |
bfd6bc60 JC |
5630 | /* On UltraSPARC, a branch in a delay slot causes a pipeline flush. |
5631 | Always emit a nop in case the next instruction is a branch. */ | |
5632 | if (dbr_sequence_length () == 0 | |
284d86e9 | 5633 | && (optimize && (int)sparc_cpu < PROCESSOR_V9)) |
c6ce0969 JW |
5634 | fputs (",a", file); |
5635 | return; | |
5636 | case '(': | |
5637 | /* Output a 'nop' if there's nothing for the delay slot and we are | |
5638 | not optimizing. This is always used with '*' above. */ | |
bfd6bc60 | 5639 | if (dbr_sequence_length () == 0 |
284d86e9 | 5640 | && ! (optimize && (int)sparc_cpu < PROCESSOR_V9)) |
e0d80184 | 5641 | fputs ("\n\t nop", file); |
ab835497 | 5642 | return; |
61a55e8b | 5643 | case '_': |
a0a301fc DE |
5644 | /* Output the Embedded Medium/Anywhere code model base register. */ |
5645 | fputs (EMBMEDANY_BASE_REG, file); | |
61a55e8b DE |
5646 | return; |
5647 | case '@': | |
5648 | /* Print out what we are using as the frame pointer. This might | |
5649 | be %fp, or might be %sp+offset. */ | |
5650 | /* ??? What if offset is too big? Perhaps the caller knows it isn't? */ | |
5651 | fprintf (file, "%s+%d", frame_base_name, frame_base_offset); | |
5652 | return; | |
ab835497 RK |
5653 | case 'Y': |
5654 | /* Adjust the operand to take into account a RESTORE operation. */ | |
bfd6bc60 JC |
5655 | if (GET_CODE (x) == CONST_INT) |
5656 | break; | |
5657 | else if (GET_CODE (x) != REG) | |
b3b1e8bd JW |
5658 | output_operand_lossage ("Invalid %%Y operand"); |
5659 | else if (REGNO (x) < 8) | |
ab835497 RK |
5660 | fputs (reg_names[REGNO (x)], file); |
5661 | else if (REGNO (x) >= 24 && REGNO (x) < 32) | |
5662 | fputs (reg_names[REGNO (x)-16], file); | |
5663 | else | |
b3b1e8bd | 5664 | output_operand_lossage ("Invalid %%Y operand"); |
ab835497 | 5665 | return; |
0f39a9aa DE |
5666 | case 'L': |
5667 | /* Print out the low order register name of a register pair. */ | |
5668 | if (WORDS_BIG_ENDIAN) | |
5669 | fputs (reg_names[REGNO (x)+1], file); | |
5670 | else | |
5671 | fputs (reg_names[REGNO (x)], file); | |
5672 | return; | |
5673 | case 'H': | |
5674 | /* Print out the high order register name of a register pair. */ | |
5675 | if (WORDS_BIG_ENDIAN) | |
5676 | fputs (reg_names[REGNO (x)], file); | |
5677 | else | |
5678 | fputs (reg_names[REGNO (x)+1], file); | |
5679 | return; | |
ab835497 | 5680 | case 'R': |
795068a4 | 5681 | /* Print out the second register name of a register pair or quad. |
ab835497 RK |
5682 | I.e., R (%o0) => %o1. */ |
5683 | fputs (reg_names[REGNO (x)+1], file); | |
5684 | return; | |
795068a4 JW |
5685 | case 'S': |
5686 | /* Print out the third register name of a register quad. | |
5687 | I.e., S (%o0) => %o2. */ | |
5688 | fputs (reg_names[REGNO (x)+2], file); | |
5689 | return; | |
5690 | case 'T': | |
5691 | /* Print out the fourth register name of a register quad. | |
5692 | I.e., T (%o0) => %o3. */ | |
5693 | fputs (reg_names[REGNO (x)+3], file); | |
5694 | return; | |
304b7a23 DE |
5695 | case 'x': |
5696 | /* Print a condition code register. */ | |
5697 | if (REGNO (x) == SPARC_ICC_REG) | |
5698 | { | |
5699 | /* We don't handle CC[X]_NOOVmode because they're not supposed | |
5700 | to occur here. */ | |
5701 | if (GET_MODE (x) == CCmode) | |
5702 | fputs ("%icc", file); | |
5703 | else if (GET_MODE (x) == CCXmode) | |
5704 | fputs ("%xcc", file); | |
5705 | else | |
5706 | abort (); | |
5707 | } | |
5708 | else | |
5709 | /* %fccN register */ | |
5710 | fputs (reg_names[REGNO (x)], file); | |
5711 | return; | |
ab835497 RK |
5712 | case 'm': |
5713 | /* Print the operand's address only. */ | |
5714 | output_address (XEXP (x, 0)); | |
5715 | return; | |
5716 | case 'r': | |
5717 | /* In this case we need a register. Use %g0 if the | |
77a02b01 | 5718 | operand is const0_rtx. */ |
76052e74 RS |
5719 | if (x == const0_rtx |
5720 | || (GET_MODE (x) != VOIDmode && x == CONST0_RTX (GET_MODE (x)))) | |
ab835497 RK |
5721 | { |
5722 | fputs ("%g0", file); | |
5723 | return; | |
5724 | } | |
5725 | else | |
5726 | break; | |
5727 | ||
61a55e8b | 5728 | case 'A': |
ab835497 RK |
5729 | switch (GET_CODE (x)) |
5730 | { | |
5731 | case IOR: fputs ("or", file); break; | |
5732 | case AND: fputs ("and", file); break; | |
5733 | case XOR: fputs ("xor", file); break; | |
b3b1e8bd | 5734 | default: output_operand_lossage ("Invalid %%A operand"); |
ab835497 RK |
5735 | } |
5736 | return; | |
5737 | ||
5738 | case 'B': | |
5739 | switch (GET_CODE (x)) | |
5740 | { | |
5741 | case IOR: fputs ("orn", file); break; | |
5742 | case AND: fputs ("andn", file); break; | |
5743 | case XOR: fputs ("xnor", file); break; | |
b3b1e8bd | 5744 | default: output_operand_lossage ("Invalid %%B operand"); |
ab835497 RK |
5745 | } |
5746 | return; | |
5747 | ||
304b7a23 DE |
5748 | /* These are used by the conditional move instructions. */ |
5749 | case 'c' : | |
61a55e8b | 5750 | case 'C': |
304b7a23 | 5751 | { |
5c5c34a4 JJ |
5752 | enum rtx_code rc = GET_CODE (x); |
5753 | ||
5754 | if (code == 'c') | |
5755 | { | |
5756 | enum machine_mode mode = GET_MODE (XEXP (x, 0)); | |
5757 | if (mode == CCFPmode || mode == CCFPEmode) | |
5758 | rc = reverse_condition_maybe_unordered (GET_CODE (x)); | |
5759 | else | |
5760 | rc = reverse_condition (GET_CODE (x)); | |
5761 | } | |
304b7a23 DE |
5762 | switch (rc) |
5763 | { | |
5764 | case NE: fputs ("ne", file); break; | |
5765 | case EQ: fputs ("e", file); break; | |
5766 | case GE: fputs ("ge", file); break; | |
5767 | case GT: fputs ("g", file); break; | |
5768 | case LE: fputs ("le", file); break; | |
5769 | case LT: fputs ("l", file); break; | |
5770 | case GEU: fputs ("geu", file); break; | |
5771 | case GTU: fputs ("gu", file); break; | |
5772 | case LEU: fputs ("leu", file); break; | |
5773 | case LTU: fputs ("lu", file); break; | |
5c5c34a4 JJ |
5774 | case LTGT: fputs ("lg", file); break; |
5775 | case UNORDERED: fputs ("u", file); break; | |
5776 | case ORDERED: fputs ("o", file); break; | |
5777 | case UNLT: fputs ("ul", file); break; | |
5778 | case UNLE: fputs ("ule", file); break; | |
5779 | case UNGT: fputs ("ug", file); break; | |
5780 | case UNGE: fputs ("uge", file); break; | |
5781 | case UNEQ: fputs ("ue", file); break; | |
304b7a23 DE |
5782 | default: output_operand_lossage (code == 'c' |
5783 | ? "Invalid %%c operand" | |
5784 | : "Invalid %%C operand"); | |
5785 | } | |
5786 | return; | |
5787 | } | |
5788 | ||
5789 | /* These are used by the movr instruction pattern. */ | |
5790 | case 'd': | |
61a55e8b | 5791 | case 'D': |
304b7a23 DE |
5792 | { |
5793 | enum rtx_code rc = (code == 'd' | |
5794 | ? reverse_condition (GET_CODE (x)) | |
5795 | : GET_CODE (x)); | |
5796 | switch (rc) | |
5797 | { | |
5798 | case NE: fputs ("ne", file); break; | |
5799 | case EQ: fputs ("e", file); break; | |
5800 | case GE: fputs ("gez", file); break; | |
5801 | case LT: fputs ("lz", file); break; | |
5802 | case LE: fputs ("lez", file); break; | |
5803 | case GT: fputs ("gz", file); break; | |
5804 | default: output_operand_lossage (code == 'd' | |
5805 | ? "Invalid %%d operand" | |
5806 | : "Invalid %%D operand"); | |
5807 | } | |
5808 | return; | |
5809 | } | |
61a55e8b | 5810 | |
ab835497 RK |
5811 | case 'b': |
5812 | { | |
5813 | /* Print a sign-extended character. */ | |
5814 | int i = INTVAL (x) & 0xff; | |
5815 | if (i & 0x80) | |
5816 | i |= 0xffffff00; | |
5817 | fprintf (file, "%d", i); | |
5818 | return; | |
5819 | } | |
5820 | ||
d2889939 RK |
5821 | case 'f': |
5822 | /* Operand must be a MEM; write its address. */ | |
5823 | if (GET_CODE (x) != MEM) | |
5824 | output_operand_lossage ("Invalid %%f operand"); | |
5825 | output_address (XEXP (x, 0)); | |
5826 | return; | |
5827 | ||
ab835497 RK |
5828 | case 0: |
5829 | /* Do nothing special. */ | |
5830 | break; | |
5831 | ||
5832 | default: | |
5833 | /* Undocumented flag. */ | |
415f583e | 5834 | output_operand_lossage ("invalid operand output code"); |
ab835497 RK |
5835 | } |
5836 | ||
5837 | if (GET_CODE (x) == REG) | |
5838 | fputs (reg_names[REGNO (x)], file); | |
5839 | else if (GET_CODE (x) == MEM) | |
5840 | { | |
5841 | fputc ('[', file); | |
ab835497 | 5842 | /* Poor Sun assembler doesn't understand absolute addressing. */ |
e6c1be7e | 5843 | if (CONSTANT_P (XEXP (x, 0))) |
ab835497 RK |
5844 | fputs ("%g0+", file); |
5845 | output_address (XEXP (x, 0)); | |
5846 | fputc (']', file); | |
5847 | } | |
5848 | else if (GET_CODE (x) == HIGH) | |
5849 | { | |
5850 | fputs ("%hi(", file); | |
5851 | output_addr_const (file, XEXP (x, 0)); | |
5852 | fputc (')', file); | |
5853 | } | |
5854 | else if (GET_CODE (x) == LO_SUM) | |
5855 | { | |
5856 | print_operand (file, XEXP (x, 0), 0); | |
e0d80184 DM |
5857 | if (TARGET_CM_MEDMID) |
5858 | fputs ("+%l44(", file); | |
5859 | else | |
5860 | fputs ("+%lo(", file); | |
ab835497 RK |
5861 | output_addr_const (file, XEXP (x, 1)); |
5862 | fputc (')', file); | |
5863 | } | |
e601abce JW |
5864 | else if (GET_CODE (x) == CONST_DOUBLE |
5865 | && (GET_MODE (x) == VOIDmode | |
5866 | || GET_MODE_CLASS (GET_MODE (x)) == MODE_INT)) | |
ab835497 RK |
5867 | { |
5868 | if (CONST_DOUBLE_HIGH (x) == 0) | |
0d9484c5 | 5869 | fprintf (file, "%u", (unsigned int) CONST_DOUBLE_LOW (x)); |
ab835497 RK |
5870 | else if (CONST_DOUBLE_HIGH (x) == -1 |
5871 | && CONST_DOUBLE_LOW (x) < 0) | |
0d9484c5 | 5872 | fprintf (file, "%d", (int) CONST_DOUBLE_LOW (x)); |
ab835497 | 5873 | else |
e601abce | 5874 | output_operand_lossage ("long long constant not a valid immediate operand"); |
ab835497 | 5875 | } |
e601abce JW |
5876 | else if (GET_CODE (x) == CONST_DOUBLE) |
5877 | output_operand_lossage ("floating point constant not a valid immediate operand"); | |
ab835497 RK |
5878 | else { output_addr_const (file, x); } |
5879 | } | |
5880 | \f | |
5881 | /* This function outputs assembler code for VALUE to FILE, where VALUE is | |
5882 | a 64 bit (DImode) value. */ | |
5883 | ||
5884 | /* ??? If there is a 64 bit counterpart to .word that the assembler | |
5885 | understands, then using that would simply this code greatly. */ | |
61a55e8b DE |
5886 | /* ??? We only output .xword's for symbols and only then in environments |
5887 | where the assembler can handle them. */ | |
ab835497 RK |
5888 | |
5889 | void | |
5890 | output_double_int (file, value) | |
5891 | FILE *file; | |
5892 | rtx value; | |
5893 | { | |
5894 | if (GET_CODE (value) == CONST_INT) | |
5895 | { | |
f4f8e370 DE |
5896 | /* ??? This has endianness issues. */ |
5897 | #if HOST_BITS_PER_WIDE_INT == 64 | |
5898 | HOST_WIDE_INT xword = INTVAL (value); | |
5899 | HOST_WIDE_INT high, low; | |
5900 | ||
5901 | high = (xword >> 32) & 0xffffffff; | |
5902 | low = xword & 0xffffffff; | |
3a598fbe JL |
5903 | ASM_OUTPUT_INT (file, GEN_INT (high)); |
5904 | ASM_OUTPUT_INT (file, GEN_INT (low)); | |
f4f8e370 | 5905 | #else |
ab835497 RK |
5906 | if (INTVAL (value) < 0) |
5907 | ASM_OUTPUT_INT (file, constm1_rtx); | |
5908 | else | |
5909 | ASM_OUTPUT_INT (file, const0_rtx); | |
5910 | ASM_OUTPUT_INT (file, value); | |
f4f8e370 | 5911 | #endif |
ab835497 RK |
5912 | } |
5913 | else if (GET_CODE (value) == CONST_DOUBLE) | |
5914 | { | |
3a598fbe JL |
5915 | ASM_OUTPUT_INT (file, GEN_INT (CONST_DOUBLE_HIGH (value))); |
5916 | ASM_OUTPUT_INT (file, GEN_INT (CONST_DOUBLE_LOW (value))); | |
ab835497 RK |
5917 | } |
5918 | else if (GET_CODE (value) == SYMBOL_REF | |
5919 | || GET_CODE (value) == CONST | |
61a55e8b | 5920 | || GET_CODE (value) == PLUS |
a9e27770 | 5921 | || (TARGET_ARCH64 && |
61a55e8b | 5922 | (GET_CODE (value) == LABEL_REF |
9fa9626b | 5923 | || GET_CODE (value) == CODE_LABEL |
61a55e8b | 5924 | || GET_CODE (value) == MINUS))) |
ab835497 | 5925 | { |
f3b8847b | 5926 | if (! TARGET_V9) |
61a55e8b DE |
5927 | { |
5928 | ASM_OUTPUT_INT (file, const0_rtx); | |
5929 | ASM_OUTPUT_INT (file, value); | |
5930 | } | |
5931 | else | |
5932 | { | |
5933 | fprintf (file, "\t%s\t", ASM_LONGLONG); | |
5934 | output_addr_const (file, value); | |
5935 | fprintf (file, "\n"); | |
5936 | } | |
ab835497 RK |
5937 | } |
5938 | else | |
5939 | abort (); | |
5940 | } | |
210aa14a | 5941 | \f |
b0468b84 RK |
5942 | /* Return the value of a code used in the .proc pseudo-op that says |
5943 | what kind of result this function returns. For non-C types, we pick | |
5944 | the closest C type. */ | |
5945 | ||
77a02b01 JW |
5946 | #ifndef CHAR_TYPE_SIZE |
5947 | #define CHAR_TYPE_SIZE BITS_PER_UNIT | |
5948 | #endif | |
5949 | ||
5950 | #ifndef SHORT_TYPE_SIZE | |
5951 | #define SHORT_TYPE_SIZE (BITS_PER_UNIT * 2) | |
5952 | #endif | |
5953 | ||
5954 | #ifndef INT_TYPE_SIZE | |
5955 | #define INT_TYPE_SIZE BITS_PER_WORD | |
5956 | #endif | |
5957 | ||
5958 | #ifndef LONG_TYPE_SIZE | |
5959 | #define LONG_TYPE_SIZE BITS_PER_WORD | |
5960 | #endif | |
5961 | ||
5962 | #ifndef LONG_LONG_TYPE_SIZE | |
5963 | #define LONG_LONG_TYPE_SIZE (BITS_PER_WORD * 2) | |
5964 | #endif | |
5965 | ||
5966 | #ifndef FLOAT_TYPE_SIZE | |
5967 | #define FLOAT_TYPE_SIZE BITS_PER_WORD | |
5968 | #endif | |
5969 | ||
5970 | #ifndef DOUBLE_TYPE_SIZE | |
5971 | #define DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2) | |
5972 | #endif | |
5973 | ||
5974 | #ifndef LONG_DOUBLE_TYPE_SIZE | |
5975 | #define LONG_DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2) | |
5976 | #endif | |
210aa14a RS |
5977 | |
5978 | unsigned long | |
5979 | sparc_type_code (type) | |
5980 | register tree type; | |
5981 | { | |
5982 | register unsigned long qualifiers = 0; | |
e5e809f4 | 5983 | register unsigned shift; |
210aa14a | 5984 | |
abc95ed3 | 5985 | /* Only the first 30 bits of the qualifier are valid. We must refrain from |
aee2c3c5 JW |
5986 | setting more, since some assemblers will give an error for this. Also, |
5987 | we must be careful to avoid shifts of 32 bits or more to avoid getting | |
5988 | unpredictable results. */ | |
5989 | ||
e5e809f4 | 5990 | for (shift = 6; shift < 30; shift += 2, type = TREE_TYPE (type)) |
210aa14a RS |
5991 | { |
5992 | switch (TREE_CODE (type)) | |
5993 | { | |
5994 | case ERROR_MARK: | |
5995 | return qualifiers; | |
5996 | ||
5997 | case ARRAY_TYPE: | |
e5e809f4 | 5998 | qualifiers |= (3 << shift); |
210aa14a RS |
5999 | break; |
6000 | ||
6001 | case FUNCTION_TYPE: | |
6002 | case METHOD_TYPE: | |
e5e809f4 | 6003 | qualifiers |= (2 << shift); |
210aa14a RS |
6004 | break; |
6005 | ||
6006 | case POINTER_TYPE: | |
6007 | case REFERENCE_TYPE: | |
6008 | case OFFSET_TYPE: | |
e5e809f4 | 6009 | qualifiers |= (1 << shift); |
210aa14a | 6010 | break; |
ab835497 | 6011 | |
210aa14a RS |
6012 | case RECORD_TYPE: |
6013 | return (qualifiers | 8); | |
6014 | ||
6015 | case UNION_TYPE: | |
b0468b84 | 6016 | case QUAL_UNION_TYPE: |
210aa14a RS |
6017 | return (qualifiers | 9); |
6018 | ||
6019 | case ENUMERAL_TYPE: | |
6020 | return (qualifiers | 10); | |
6021 | ||
6022 | case VOID_TYPE: | |
6023 | return (qualifiers | 16); | |
6024 | ||
6025 | case INTEGER_TYPE: | |
654209e6 JW |
6026 | /* If this is a range type, consider it to be the underlying |
6027 | type. */ | |
6028 | if (TREE_TYPE (type) != 0) | |
e5e809f4 | 6029 | break; |
654209e6 | 6030 | |
77a02b01 | 6031 | /* Carefully distinguish all the standard types of C, |
b0468b84 RK |
6032 | without messing up if the language is not C. We do this by |
6033 | testing TYPE_PRECISION and TREE_UNSIGNED. The old code used to | |
6034 | look at both the names and the above fields, but that's redundant. | |
6035 | Any type whose size is between two C types will be considered | |
6036 | to be the wider of the two types. Also, we do not have a | |
6037 | special code to use for "long long", so anything wider than | |
6038 | long is treated the same. Note that we can't distinguish | |
6039 | between "int" and "long" in this code if they are the same | |
6040 | size, but that's fine, since neither can the assembler. */ | |
6041 | ||
6042 | if (TYPE_PRECISION (type) <= CHAR_TYPE_SIZE) | |
6043 | return (qualifiers | (TREE_UNSIGNED (type) ? 12 : 2)); | |
77a02b01 | 6044 | |
b0468b84 RK |
6045 | else if (TYPE_PRECISION (type) <= SHORT_TYPE_SIZE) |
6046 | return (qualifiers | (TREE_UNSIGNED (type) ? 13 : 3)); | |
77a02b01 | 6047 | |
b0468b84 | 6048 | else if (TYPE_PRECISION (type) <= INT_TYPE_SIZE) |
77a02b01 JW |
6049 | return (qualifiers | (TREE_UNSIGNED (type) ? 14 : 4)); |
6050 | ||
b0468b84 | 6051 | else |
77a02b01 JW |
6052 | return (qualifiers | (TREE_UNSIGNED (type) ? 15 : 5)); |
6053 | ||
210aa14a | 6054 | case REAL_TYPE: |
e5e809f4 JL |
6055 | /* If this is a range type, consider it to be the underlying |
6056 | type. */ | |
6057 | if (TREE_TYPE (type) != 0) | |
6058 | break; | |
6059 | ||
77a02b01 JW |
6060 | /* Carefully distinguish all the standard types of C, |
6061 | without messing up if the language is not C. */ | |
b0468b84 | 6062 | |
77a02b01 | 6063 | if (TYPE_PRECISION (type) == FLOAT_TYPE_SIZE) |
210aa14a | 6064 | return (qualifiers | 6); |
b0468b84 RK |
6065 | |
6066 | else | |
6067 | return (qualifiers | 7); | |
210aa14a RS |
6068 | |
6069 | case COMPLEX_TYPE: /* GNU Fortran COMPLEX type. */ | |
13d39dbc | 6070 | /* ??? We need to distinguish between double and float complex types, |
c82aa69a JW |
6071 | but I don't know how yet because I can't reach this code from |
6072 | existing front-ends. */ | |
6073 | return (qualifiers | 7); /* Who knows? */ | |
6074 | ||
210aa14a RS |
6075 | case CHAR_TYPE: /* GNU Pascal CHAR type. Not used in C. */ |
6076 | case BOOLEAN_TYPE: /* GNU Fortran BOOLEAN type. */ | |
6077 | case FILE_TYPE: /* GNU Pascal FILE type. */ | |
26902ae0 | 6078 | case SET_TYPE: /* GNU Pascal SET type. */ |
210aa14a | 6079 | case LANG_TYPE: /* ? */ |
26902ae0 | 6080 | return qualifiers; |
210aa14a RS |
6081 | |
6082 | default: | |
6083 | abort (); /* Not a type! */ | |
6084 | } | |
6085 | } | |
e5e809f4 JL |
6086 | |
6087 | return qualifiers; | |
210aa14a | 6088 | } |
ead69aea | 6089 | \f |
61a55e8b DE |
6090 | /* Nested function support. */ |
6091 | ||
6092 | /* Emit RTL insns to initialize the variable parts of a trampoline. | |
6093 | FNADDR is an RTX for the address of the function's pure code. | |
6094 | CXT is an RTX for the static chain value for the function. | |
6095 | ||
6096 | This takes 16 insns: 2 shifts & 2 ands (to split up addresses), 4 sethi | |
6097 | (to load in opcodes), 4 iors (to merge address and opcodes), and 4 writes | |
6098 | (to store insns). This is a bit excessive. Perhaps a different | |
6099 | mechanism would be better here. | |
6100 | ||
849a528d | 6101 | Emit enough FLUSH insns to synchronize the data and instruction caches. */ |
61a55e8b DE |
6102 | |
6103 | void | |
6104 | sparc_initialize_trampoline (tramp, fnaddr, cxt) | |
6105 | rtx tramp, fnaddr, cxt; | |
6106 | { | |
c6b0465b JC |
6107 | /* SPARC 32 bit trampoline: |
6108 | ||
e0d80184 DM |
6109 | sethi %hi(fn), %g1 |
6110 | sethi %hi(static), %g2 | |
6111 | jmp %g1+%lo(fn) | |
6112 | or %g2, %lo(static), %g2 | |
c6b0465b JC |
6113 | |
6114 | SETHI i,r = 00rr rrr1 00ii iiii iiii iiii iiii iiii | |
6115 | JMPL r+i,d = 10dd ddd1 1100 0rrr rr1i iiii iiii iiii | |
6116 | */ | |
959eb758 DM |
6117 | #ifdef TRANSFER_FROM_TRAMPOLINE |
6118 | emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "__enable_execute_stack"), | |
6119 | 0, VOIDmode, 1, tramp, Pmode); | |
6120 | #endif | |
c6b0465b JC |
6121 | |
6122 | emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 0)), | |
6123 | expand_binop (SImode, ior_optab, | |
6124 | expand_shift (RSHIFT_EXPR, SImode, fnaddr, | |
6125 | size_int (10), 0, 1), | |
6126 | GEN_INT (0x03000000), | |
6127 | NULL_RTX, 1, OPTAB_DIRECT)); | |
6128 | ||
6129 | emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 4)), | |
6130 | expand_binop (SImode, ior_optab, | |
6131 | expand_shift (RSHIFT_EXPR, SImode, cxt, | |
6132 | size_int (10), 0, 1), | |
6133 | GEN_INT (0x05000000), | |
6134 | NULL_RTX, 1, OPTAB_DIRECT)); | |
6135 | ||
6136 | emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 8)), | |
6137 | expand_binop (SImode, ior_optab, | |
6138 | expand_and (fnaddr, GEN_INT (0x3ff), NULL_RTX), | |
6139 | GEN_INT (0x81c06000), | |
6140 | NULL_RTX, 1, OPTAB_DIRECT)); | |
6141 | ||
6142 | emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 12)), | |
6143 | expand_binop (SImode, ior_optab, | |
6144 | expand_and (cxt, GEN_INT (0x3ff), NULL_RTX), | |
6145 | GEN_INT (0x8410a000), | |
6146 | NULL_RTX, 1, OPTAB_DIRECT)); | |
6147 | ||
254110c2 | 6148 | emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode, tramp)))); |
c6b0465b JC |
6149 | /* On UltraSPARC a flush flushes an entire cache line. The trampoline is |
6150 | aligned on a 16 byte boundary so one flush clears it all. */ | |
6151 | if (sparc_cpu != PROCESSOR_ULTRASPARC) | |
6152 | emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode, | |
6153 | plus_constant (tramp, 8))))); | |
61a55e8b DE |
6154 | } |
6155 | ||
849a528d RK |
6156 | /* The 64 bit version is simpler because it makes more sense to load the |
6157 | values as "immediate" data out of the trampoline. It's also easier since | |
6158 | we can read the PC without clobbering a register. */ | |
6159 | ||
61a55e8b DE |
6160 | void |
6161 | sparc64_initialize_trampoline (tramp, fnaddr, cxt) | |
6162 | rtx tramp, fnaddr, cxt; | |
6163 | { | |
345a6161 DM |
6164 | #ifdef TRANSFER_FROM_TRAMPOLINE |
6165 | emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "__enable_execute_stack"), | |
6166 | 0, VOIDmode, 1, tramp, Pmode); | |
6167 | #endif | |
6168 | ||
c6b0465b | 6169 | /* |
e0d80184 DM |
6170 | rd %pc, %g1 |
6171 | ldx [%g1+24], %g5 | |
6172 | jmp %g5 | |
6173 | ldx [%g1+16], %g5 | |
c6b0465b JC |
6174 | +16 bytes data |
6175 | */ | |
6176 | ||
6177 | emit_move_insn (gen_rtx_MEM (SImode, tramp), | |
6178 | GEN_INT (0x83414000)); | |
6179 | emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 4)), | |
6180 | GEN_INT (0xca586018)); | |
6181 | emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 8)), | |
345a6161 | 6182 | GEN_INT (0x81c14000)); |
c6b0465b JC |
6183 | emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 12)), |
6184 | GEN_INT (0xca586010)); | |
6185 | emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 16)), cxt); | |
345a6161 | 6186 | emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 24)), fnaddr); |
d4203cb4 | 6187 | emit_insn (gen_flushdi (validize_mem (gen_rtx_MEM (DImode, tramp)))); |
345a6161 | 6188 | |
c6b0465b | 6189 | if (sparc_cpu != PROCESSOR_ULTRASPARC) |
d4203cb4 | 6190 | emit_insn (gen_flushdi (validize_mem (gen_rtx_MEM (DImode, plus_constant (tramp, 8))))); |
61a55e8b DE |
6191 | } |
6192 | \f | |
c819be5b JW |
6193 | /* Subroutines to support a flat (single) register window calling |
6194 | convention. */ | |
6195 | ||
6196 | /* Single-register window sparc stack frames look like: | |
6197 | ||
6198 | Before call After call | |
6199 | +-----------------------+ +-----------------------+ | |
86735b02 DE |
6200 | high | | | | |
6201 | mem | caller's temps. | | caller's temps. | | |
c819be5b JW |
6202 | | | | | |
6203 | +-----------------------+ +-----------------------+ | |
6204 | | | | | | |
6205 | | arguments on stack. | | arguments on stack. | | |
86735b02 DE |
6206 | | | | | |
6207 | +-----------------------+FP+92->+-----------------------+ | |
c819be5b JW |
6208 | | 6 words to save | | 6 words to save | |
6209 | | arguments passed | | arguments passed | | |
6210 | | in registers, even | | in registers, even | | |
86735b02 DE |
6211 | | if not passed. | | if not passed. | |
6212 | SP+68->+-----------------------+FP+68->+-----------------------+ | |
6213 | | 1 word struct addr | | 1 word struct addr | | |
6214 | +-----------------------+FP+64->+-----------------------+ | |
6215 | | | | | | |
6216 | | 16 word reg save area | | 16 word reg save area | | |
6217 | | | | | | |
6218 | SP->+-----------------------+ FP->+-----------------------+ | |
6219 | | 4 word area for | | |
6220 | | fp/alu reg moves | | |
6221 | FP-16->+-----------------------+ | |
6222 | | | | |
6223 | | local variables | | |
6224 | | | | |
6225 | +-----------------------+ | |
6226 | | | | |
c819be5b | 6227 | | fp register save | |
86735b02 DE |
6228 | | | |
6229 | +-----------------------+ | |
6230 | | | | |
c819be5b JW |
6231 | | gp register save | |
6232 | | | | |
86735b02 DE |
6233 | +-----------------------+ |
6234 | | | | |
c819be5b | 6235 | | alloca allocations | |
86735b02 DE |
6236 | | | |
6237 | +-----------------------+ | |
6238 | | | | |
c819be5b | 6239 | | arguments on stack | |
86735b02 DE |
6240 | | | |
6241 | SP+92->+-----------------------+ | |
c819be5b | 6242 | | 6 words to save | |
86735b02 | 6243 | | arguments passed | |
c819be5b | 6244 | | in registers, even | |
86735b02 DE |
6245 | low | if not passed. | |
6246 | memory SP+68->+-----------------------+ | |
6247 | | 1 word struct addr | | |
6248 | SP+64->+-----------------------+ | |
6249 | | | | |
6250 | I 16 word reg save area | | |
6251 | | | | |
6252 | SP->+-----------------------+ */ | |
c819be5b | 6253 | |
c6aa9ce1 | 6254 | /* Structure to be filled in by sparc_flat_compute_frame_size with register |
c819be5b JW |
6255 | save masks, and offsets for the current function. */ |
6256 | ||
6257 | struct sparc_frame_info | |
6258 | { | |
6259 | unsigned long total_size; /* # bytes that the entire frame takes up. */ | |
6260 | unsigned long var_size; /* # bytes that variables take up. */ | |
6261 | unsigned long args_size; /* # bytes that outgoing arguments take up. */ | |
6262 | unsigned long extra_size; /* # bytes of extra gunk. */ | |
6263 | unsigned int gp_reg_size; /* # bytes needed to store gp regs. */ | |
6264 | unsigned int fp_reg_size; /* # bytes needed to store fp regs. */ | |
86735b02 | 6265 | unsigned long gmask; /* Mask of saved gp registers. */ |
c819be5b | 6266 | unsigned long fmask; /* Mask of saved fp registers. */ |
86735b02 | 6267 | unsigned long reg_offset; /* Offset from new sp to store regs. */ |
c819be5b JW |
6268 | int initialized; /* Nonzero if frame size already calculated. */ |
6269 | }; | |
6270 | ||
c6aa9ce1 | 6271 | /* Current frame information calculated by sparc_flat_compute_frame_size. */ |
c819be5b JW |
6272 | struct sparc_frame_info current_frame_info; |
6273 | ||
6274 | /* Zero structure to initialize current_frame_info. */ | |
6275 | struct sparc_frame_info zero_frame_info; | |
6276 | ||
6277 | /* Tell prologue and epilogue if register REGNO should be saved / restored. */ | |
6278 | ||
86735b02 DE |
6279 | #define RETURN_ADDR_REGNUM 15 |
6280 | #define FRAME_POINTER_MASK (1 << (FRAME_POINTER_REGNUM)) | |
6281 | #define RETURN_ADDR_MASK (1 << (RETURN_ADDR_REGNUM)) | |
6282 | ||
c819be5b JW |
6283 | #define MUST_SAVE_REGISTER(regno) \ |
6284 | ((regs_ever_live[regno] && !call_used_regs[regno]) \ | |
6285 | || (regno == FRAME_POINTER_REGNUM && frame_pointer_needed) \ | |
86735b02 | 6286 | || (regno == RETURN_ADDR_REGNUM && regs_ever_live[RETURN_ADDR_REGNUM])) |
c819be5b JW |
6287 | |
6288 | /* Return the bytes needed to compute the frame pointer from the current | |
6289 | stack pointer. */ | |
6290 | ||
6291 | unsigned long | |
c6aa9ce1 | 6292 | sparc_flat_compute_frame_size (size) |
c819be5b JW |
6293 | int size; /* # of var. bytes allocated. */ |
6294 | { | |
6295 | int regno; | |
6296 | unsigned long total_size; /* # bytes that the entire frame takes up. */ | |
6297 | unsigned long var_size; /* # bytes that variables take up. */ | |
6298 | unsigned long args_size; /* # bytes that outgoing arguments take up. */ | |
6299 | unsigned long extra_size; /* # extra bytes. */ | |
6300 | unsigned int gp_reg_size; /* # bytes needed to store gp regs. */ | |
6301 | unsigned int fp_reg_size; /* # bytes needed to store fp regs. */ | |
86735b02 | 6302 | unsigned long gmask; /* Mask of saved gp registers. */ |
c819be5b | 6303 | unsigned long fmask; /* Mask of saved fp registers. */ |
86735b02 DE |
6304 | unsigned long reg_offset; /* Offset to register save area. */ |
6305 | int need_aligned_p; /* 1 if need the save area 8 byte aligned. */ | |
c819be5b JW |
6306 | |
6307 | /* This is the size of the 16 word reg save area, 1 word struct addr | |
6308 | area, and 4 word fp/alu register copy area. */ | |
8c64be75 SC |
6309 | extra_size = -STARTING_FRAME_OFFSET + FIRST_PARM_OFFSET(0); |
6310 | var_size = size; | |
6311 | gp_reg_size = 0; | |
6312 | fp_reg_size = 0; | |
6313 | gmask = 0; | |
6314 | fmask = 0; | |
6315 | reg_offset = 0; | |
86735b02 | 6316 | need_aligned_p = 0; |
c819be5b | 6317 | |
8c64be75 SC |
6318 | args_size = 0; |
6319 | if (!leaf_function_p ()) | |
6320 | { | |
6321 | /* Also include the size needed for the 6 parameter registers. */ | |
6322 | args_size = current_function_outgoing_args_size + 24; | |
6323 | } | |
6324 | total_size = var_size + args_size; | |
6325 | ||
c819be5b JW |
6326 | /* Calculate space needed for gp registers. */ |
6327 | for (regno = 1; regno <= 31; regno++) | |
6328 | { | |
6329 | if (MUST_SAVE_REGISTER (regno)) | |
6330 | { | |
86735b02 DE |
6331 | /* If we need to save two regs in a row, ensure there's room to bump |
6332 | up the address to align it to a doubleword boundary. */ | |
c819be5b JW |
6333 | if ((regno & 0x1) == 0 && MUST_SAVE_REGISTER (regno+1)) |
6334 | { | |
6335 | if (gp_reg_size % 8 != 0) | |
86735b02 | 6336 | gp_reg_size += 4; |
c819be5b | 6337 | gp_reg_size += 2 * UNITS_PER_WORD; |
86735b02 | 6338 | gmask |= 3 << regno; |
c819be5b | 6339 | regno++; |
86735b02 | 6340 | need_aligned_p = 1; |
c819be5b JW |
6341 | } |
6342 | else | |
6343 | { | |
6344 | gp_reg_size += UNITS_PER_WORD; | |
86735b02 | 6345 | gmask |= 1 << regno; |
c819be5b JW |
6346 | } |
6347 | } | |
6348 | } | |
c819be5b JW |
6349 | |
6350 | /* Calculate space needed for fp registers. */ | |
6351 | for (regno = 32; regno <= 63; regno++) | |
6352 | { | |
6353 | if (regs_ever_live[regno] && !call_used_regs[regno]) | |
6354 | { | |
6355 | fp_reg_size += UNITS_PER_WORD; | |
6356 | fmask |= 1 << (regno - 32); | |
6357 | } | |
6358 | } | |
6359 | ||
86735b02 DE |
6360 | if (gmask || fmask) |
6361 | { | |
6362 | int n; | |
6363 | reg_offset = FIRST_PARM_OFFSET(0) + args_size; | |
6364 | /* Ensure save area is 8 byte aligned if we need it. */ | |
6365 | n = reg_offset % 8; | |
6366 | if (need_aligned_p && n != 0) | |
6367 | { | |
6368 | total_size += 8 - n; | |
6369 | reg_offset += 8 - n; | |
6370 | } | |
6371 | total_size += gp_reg_size + fp_reg_size; | |
6372 | } | |
c819be5b | 6373 | |
8c64be75 SC |
6374 | /* If we must allocate a stack frame at all, we must also allocate |
6375 | room for register window spillage, so as to be binary compatible | |
6376 | with libraries and operating systems that do not use -mflat. */ | |
6377 | if (total_size > 0) | |
6378 | total_size += extra_size; | |
6379 | else | |
6380 | extra_size = 0; | |
c819be5b JW |
6381 | |
6382 | total_size = SPARC_STACK_ALIGN (total_size); | |
6383 | ||
6384 | /* Save other computed information. */ | |
6385 | current_frame_info.total_size = total_size; | |
6386 | current_frame_info.var_size = var_size; | |
6387 | current_frame_info.args_size = args_size; | |
6388 | current_frame_info.extra_size = extra_size; | |
6389 | current_frame_info.gp_reg_size = gp_reg_size; | |
6390 | current_frame_info.fp_reg_size = fp_reg_size; | |
86735b02 | 6391 | current_frame_info.gmask = gmask; |
c819be5b | 6392 | current_frame_info.fmask = fmask; |
86735b02 | 6393 | current_frame_info.reg_offset = reg_offset; |
c819be5b JW |
6394 | current_frame_info.initialized = reload_completed; |
6395 | ||
c819be5b JW |
6396 | /* Ok, we're done. */ |
6397 | return total_size; | |
6398 | } | |
6399 | \f | |
86735b02 DE |
6400 | /* Save/restore registers in GMASK and FMASK at register BASE_REG plus offset |
6401 | OFFSET. | |
6402 | ||
6403 | BASE_REG must be 8 byte aligned. This allows us to test OFFSET for | |
6404 | appropriate alignment and use DOUBLEWORD_OP when we can. We assume | |
6405 | [BASE_REG+OFFSET] will always be a valid address. | |
6406 | ||
6407 | WORD_OP is either "st" for save, "ld" for restore. | |
6408 | DOUBLEWORD_OP is either "std" for save, "ldd" for restore. */ | |
c819be5b JW |
6409 | |
6410 | void | |
96987e96 DE |
6411 | sparc_flat_save_restore (file, base_reg, offset, gmask, fmask, word_op, |
6412 | doubleword_op, base_offset) | |
86735b02 | 6413 | FILE *file; |
b1474bb7 | 6414 | const char *base_reg; |
86735b02 DE |
6415 | unsigned int offset; |
6416 | unsigned long gmask; | |
6417 | unsigned long fmask; | |
b1474bb7 KG |
6418 | const char *word_op; |
6419 | const char *doubleword_op; | |
c53aa195 | 6420 | unsigned long base_offset; |
c819be5b JW |
6421 | { |
6422 | int regno; | |
c819be5b | 6423 | |
86735b02 DE |
6424 | if (gmask == 0 && fmask == 0) |
6425 | return; | |
c819be5b | 6426 | |
86735b02 DE |
6427 | /* Save registers starting from high to low. We've already saved the |
6428 | previous frame pointer and previous return address for the debugger's | |
6429 | sake. The debugger allows us to not need a nop in the epilog if at least | |
6430 | one register is reloaded in addition to return address. */ | |
c819be5b | 6431 | |
86735b02 | 6432 | if (gmask) |
c819be5b JW |
6433 | { |
6434 | for (regno = 1; regno <= 31; regno++) | |
6435 | { | |
86735b02 | 6436 | if ((gmask & (1L << regno)) != 0) |
c819be5b | 6437 | { |
86735b02 | 6438 | if ((regno & 0x1) == 0 && ((gmask & (1L << (regno+1))) != 0)) |
c819be5b | 6439 | { |
86735b02 DE |
6440 | /* We can save two registers in a row. If we're not at a |
6441 | double word boundary, move to one. | |
6442 | sparc_flat_compute_frame_size ensures there's room to do | |
6443 | this. */ | |
6444 | if (offset % 8 != 0) | |
6445 | offset += UNITS_PER_WORD; | |
6446 | ||
c819be5b | 6447 | if (word_op[0] == 's') |
c53aa195 | 6448 | { |
e0d80184 | 6449 | fprintf (file, "\t%s\t%s, [%s+%d]\n", |
c53aa195 JM |
6450 | doubleword_op, reg_names[regno], |
6451 | base_reg, offset); | |
0021b564 | 6452 | if (dwarf2out_do_frame ()) |
c53aa195 | 6453 | { |
96987e96 | 6454 | char *l = dwarf2out_cfi_label (); |
c53aa195 JM |
6455 | dwarf2out_reg_save (l, regno, offset + base_offset); |
6456 | dwarf2out_reg_save | |
6457 | (l, regno+1, offset+base_offset + UNITS_PER_WORD); | |
6458 | } | |
c53aa195 | 6459 | } |
c819be5b | 6460 | else |
e0d80184 | 6461 | fprintf (file, "\t%s\t[%s+%d], %s\n", |
86735b02 | 6462 | doubleword_op, base_reg, offset, |
c819be5b JW |
6463 | reg_names[regno]); |
6464 | ||
86735b02 | 6465 | offset += 2 * UNITS_PER_WORD; |
c819be5b JW |
6466 | regno++; |
6467 | } | |
6468 | else | |
6469 | { | |
6470 | if (word_op[0] == 's') | |
c53aa195 | 6471 | { |
e0d80184 | 6472 | fprintf (file, "\t%s\t%s, [%s+%d]\n", |
c53aa195 JM |
6473 | word_op, reg_names[regno], |
6474 | base_reg, offset); | |
0021b564 | 6475 | if (dwarf2out_do_frame ()) |
c53aa195 | 6476 | dwarf2out_reg_save ("", regno, offset + base_offset); |
c53aa195 | 6477 | } |
c819be5b | 6478 | else |
e0d80184 | 6479 | fprintf (file, "\t%s\t[%s+%d], %s\n", |
86735b02 | 6480 | word_op, base_reg, offset, reg_names[regno]); |
c819be5b | 6481 | |
86735b02 | 6482 | offset += UNITS_PER_WORD; |
c819be5b JW |
6483 | } |
6484 | } | |
6485 | } | |
6486 | } | |
6487 | ||
6488 | if (fmask) | |
6489 | { | |
6490 | for (regno = 32; regno <= 63; regno++) | |
6491 | { | |
6492 | if ((fmask & (1L << (regno - 32))) != 0) | |
6493 | { | |
6494 | if (word_op[0] == 's') | |
c53aa195 | 6495 | { |
e0d80184 | 6496 | fprintf (file, "\t%s\t%s, [%s+%d]\n", |
c53aa195 JM |
6497 | word_op, reg_names[regno], |
6498 | base_reg, offset); | |
0021b564 | 6499 | if (dwarf2out_do_frame ()) |
c53aa195 | 6500 | dwarf2out_reg_save ("", regno, offset + base_offset); |
c53aa195 | 6501 | } |
c819be5b | 6502 | else |
e0d80184 | 6503 | fprintf (file, "\t%s\t[%s+%d], %s\n", |
86735b02 | 6504 | word_op, base_reg, offset, reg_names[regno]); |
c819be5b | 6505 | |
86735b02 | 6506 | offset += UNITS_PER_WORD; |
c819be5b JW |
6507 | } |
6508 | } | |
6509 | } | |
6510 | } | |
6511 | \f | |
6512 | /* Set up the stack and frame (if desired) for the function. */ | |
6513 | ||
6514 | void | |
c6aa9ce1 | 6515 | sparc_flat_output_function_prologue (file, size) |
c819be5b JW |
6516 | FILE *file; |
6517 | int size; | |
6518 | { | |
99f44eba | 6519 | const char *sp_str = reg_names[STACK_POINTER_REGNUM]; |
86735b02 | 6520 | unsigned long gmask = current_frame_info.gmask; |
a07c1915 | 6521 | |
1cb36a98 RH |
6522 | sparc_output_scratch_registers (file); |
6523 | ||
c6aa9ce1 | 6524 | /* This is only for the human reader. */ |
bf62bbf1 | 6525 | fprintf (file, "\t%s#PROLOGUE# 0\n", ASM_COMMENT_START); |
5e9defae | 6526 | fprintf (file, "\t%s# vars= %ld, regs= %d/%d, args= %d, extra= %ld\n", |
bf62bbf1 | 6527 | ASM_COMMENT_START, |
86735b02 DE |
6528 | current_frame_info.var_size, |
6529 | current_frame_info.gp_reg_size / 4, | |
9f8b85b8 | 6530 | current_frame_info.fp_reg_size / 4, |
86735b02 DE |
6531 | current_function_outgoing_args_size, |
6532 | current_frame_info.extra_size); | |
c819be5b JW |
6533 | |
6534 | size = SPARC_STACK_ALIGN (size); | |
86735b02 DE |
6535 | size = (! current_frame_info.initialized |
6536 | ? sparc_flat_compute_frame_size (size) | |
6537 | : current_frame_info.total_size); | |
c819be5b | 6538 | |
86735b02 DE |
6539 | /* These cases shouldn't happen. Catch them now. */ |
6540 | if (size == 0 && (gmask || current_frame_info.fmask)) | |
6541 | abort (); | |
c819be5b | 6542 | |
86735b02 DE |
6543 | /* Allocate our stack frame by decrementing %sp. |
6544 | At present, the only algorithm gdb can use to determine if this is a | |
6545 | flat frame is if we always set %i7 if we set %sp. This can be optimized | |
6546 | in the future by putting in some sort of debugging information that says | |
6547 | this is a `flat' function. However, there is still the case of debugging | |
6548 | code without such debugging information (including cases where most fns | |
6549 | have such info, but there is one that doesn't). So, always do this now | |
6550 | so we don't get a lot of code out there that gdb can't handle. | |
6551 | If the frame pointer isn't needn't then that's ok - gdb won't be able to | |
6552 | distinguish us from a non-flat function but there won't (and shouldn't) | |
6553 | be any differences anyway. The return pc is saved (if necessary) right | |
6554 | after %i7 so gdb won't have to look too far to find it. */ | |
6555 | if (size > 0) | |
c819be5b | 6556 | { |
86735b02 | 6557 | unsigned int reg_offset = current_frame_info.reg_offset; |
99f44eba | 6558 | const char *fp_str = reg_names[FRAME_POINTER_REGNUM]; |
3bb5de61 | 6559 | const char *t1_str = "%g1"; |
86735b02 DE |
6560 | |
6561 | /* Things get a little tricky if local variables take up more than ~4096 | |
6562 | bytes and outgoing arguments take up more than ~4096 bytes. When that | |
6563 | happens, the register save area can't be accessed from either end of | |
6564 | the frame. Handle this by decrementing %sp to the start of the gp | |
6565 | register save area, save the regs, update %i7, and then set %sp to its | |
6566 | final value. Given that we only have one scratch register to play | |
6567 | with it is the cheapest solution, and it helps gdb out as it won't | |
6568 | slow down recognition of flat functions. | |
6569 | Don't change the order of insns emitted here without checking with | |
6570 | the gdb folk first. */ | |
6571 | ||
ddd5a7c1 | 6572 | /* Is the entire register save area offsettable from %sp? */ |
fbd039b2 | 6573 | if (reg_offset < 4096 - 64 * (unsigned) UNITS_PER_WORD) |
86735b02 DE |
6574 | { |
6575 | if (size <= 4096) | |
6576 | { | |
e0d80184 | 6577 | fprintf (file, "\tadd\t%s, %d, %s\n", |
86735b02 DE |
6578 | sp_str, -size, sp_str); |
6579 | if (gmask & FRAME_POINTER_MASK) | |
6580 | { | |
e0d80184 | 6581 | fprintf (file, "\tst\t%s, [%s+%d]\n", |
86735b02 | 6582 | fp_str, sp_str, reg_offset); |
e0d80184 | 6583 | fprintf (file, "\tsub\t%s, %d, %s\t%s# set up frame pointer\n", |
bf62bbf1 | 6584 | sp_str, -size, fp_str, ASM_COMMENT_START); |
86735b02 DE |
6585 | reg_offset += 4; |
6586 | } | |
6587 | } | |
6588 | else | |
6589 | { | |
e0d80184 | 6590 | fprintf (file, "\tset\t%d, %s\n\tsub\t%s, %s, %s\n", |
86735b02 DE |
6591 | size, t1_str, sp_str, t1_str, sp_str); |
6592 | if (gmask & FRAME_POINTER_MASK) | |
6593 | { | |
e0d80184 | 6594 | fprintf (file, "\tst\t%s, [%s+%d]\n", |
86735b02 | 6595 | fp_str, sp_str, reg_offset); |
e0d80184 | 6596 | fprintf (file, "\tadd\t%s, %s, %s\t%s# set up frame pointer\n", |
bf62bbf1 | 6597 | sp_str, t1_str, fp_str, ASM_COMMENT_START); |
86735b02 DE |
6598 | reg_offset += 4; |
6599 | } | |
6600 | } | |
0021b564 | 6601 | if (dwarf2out_do_frame ()) |
c53aa195 | 6602 | { |
96987e96 | 6603 | char *l = dwarf2out_cfi_label (); |
c53aa195 JM |
6604 | if (gmask & FRAME_POINTER_MASK) |
6605 | { | |
6606 | dwarf2out_reg_save (l, FRAME_POINTER_REGNUM, | |
6607 | reg_offset - 4 - size); | |
6608 | dwarf2out_def_cfa (l, FRAME_POINTER_REGNUM, 0); | |
6609 | } | |
6610 | else | |
6611 | dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, size); | |
6612 | } | |
86735b02 DE |
6613 | if (gmask & RETURN_ADDR_MASK) |
6614 | { | |
e0d80184 | 6615 | fprintf (file, "\tst\t%s, [%s+%d]\n", |
86735b02 | 6616 | reg_names[RETURN_ADDR_REGNUM], sp_str, reg_offset); |
0021b564 | 6617 | if (dwarf2out_do_frame ()) |
c53aa195 | 6618 | dwarf2out_return_save ("", reg_offset - size); |
86735b02 DE |
6619 | reg_offset += 4; |
6620 | } | |
6621 | sparc_flat_save_restore (file, sp_str, reg_offset, | |
6622 | gmask & ~(FRAME_POINTER_MASK | RETURN_ADDR_MASK), | |
6623 | current_frame_info.fmask, | |
84e884e9 | 6624 | "st", "std", -size); |
86735b02 | 6625 | } |
c819be5b | 6626 | else |
86735b02 DE |
6627 | { |
6628 | /* Subtract %sp in two steps, but make sure there is always a | |
6629 | 64 byte register save area, and %sp is properly aligned. */ | |
6630 | /* Amount to decrement %sp by, the first time. */ | |
6631 | unsigned int size1 = ((size - reg_offset + 64) + 15) & -16; | |
6632 | /* Offset to register save area from %sp. */ | |
6633 | unsigned int offset = size1 - (size - reg_offset); | |
6634 | ||
6635 | if (size1 <= 4096) | |
6636 | { | |
e0d80184 | 6637 | fprintf (file, "\tadd\t%s, %d, %s\n", |
86735b02 DE |
6638 | sp_str, -size1, sp_str); |
6639 | if (gmask & FRAME_POINTER_MASK) | |
6640 | { | |
e0d80184 | 6641 | fprintf (file, "\tst\t%s, [%s+%d]\n\tsub\t%s, %d, %s\t%s# set up frame pointer\n", |
bf62bbf1 DE |
6642 | fp_str, sp_str, offset, sp_str, -size1, fp_str, |
6643 | ASM_COMMENT_START); | |
86735b02 DE |
6644 | offset += 4; |
6645 | } | |
6646 | } | |
6647 | else | |
6648 | { | |
e0d80184 | 6649 | fprintf (file, "\tset\t%d, %s\n\tsub\t%s, %s, %s\n", |
86735b02 DE |
6650 | size1, t1_str, sp_str, t1_str, sp_str); |
6651 | if (gmask & FRAME_POINTER_MASK) | |
6652 | { | |
e0d80184 | 6653 | fprintf (file, "\tst\t%s, [%s+%d]\n\tadd\t%s, %s, %s\t%s# set up frame pointer\n", |
bf62bbf1 DE |
6654 | fp_str, sp_str, offset, sp_str, t1_str, fp_str, |
6655 | ASM_COMMENT_START); | |
86735b02 DE |
6656 | offset += 4; |
6657 | } | |
6658 | } | |
0021b564 | 6659 | if (dwarf2out_do_frame ()) |
c53aa195 | 6660 | { |
96987e96 | 6661 | char *l = dwarf2out_cfi_label (); |
c53aa195 JM |
6662 | if (gmask & FRAME_POINTER_MASK) |
6663 | { | |
6664 | dwarf2out_reg_save (l, FRAME_POINTER_REGNUM, | |
6665 | offset - 4 - size1); | |
6666 | dwarf2out_def_cfa (l, FRAME_POINTER_REGNUM, 0); | |
6667 | } | |
6668 | else | |
6669 | dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, size1); | |
6670 | } | |
86735b02 DE |
6671 | if (gmask & RETURN_ADDR_MASK) |
6672 | { | |
e0d80184 | 6673 | fprintf (file, "\tst\t%s, [%s+%d]\n", |
86735b02 | 6674 | reg_names[RETURN_ADDR_REGNUM], sp_str, offset); |
0021b564 | 6675 | if (dwarf2out_do_frame ()) |
c53aa195 JM |
6676 | /* offset - size1 == reg_offset - size |
6677 | if reg_offset were updated above like offset. */ | |
6678 | dwarf2out_return_save ("", offset - size1); | |
86735b02 DE |
6679 | offset += 4; |
6680 | } | |
6681 | sparc_flat_save_restore (file, sp_str, offset, | |
6682 | gmask & ~(FRAME_POINTER_MASK | RETURN_ADDR_MASK), | |
6683 | current_frame_info.fmask, | |
84e884e9 | 6684 | "st", "std", -size1); |
e0d80184 | 6685 | fprintf (file, "\tset\t%d, %s\n\tsub\t%s, %s, %s\n", |
86735b02 | 6686 | size - size1, t1_str, sp_str, t1_str, sp_str); |
0021b564 | 6687 | if (dwarf2out_do_frame ()) |
c53aa195 JM |
6688 | if (! (gmask & FRAME_POINTER_MASK)) |
6689 | dwarf2out_def_cfa ("", STACK_POINTER_REGNUM, size); | |
86735b02 | 6690 | } |
c819be5b | 6691 | } |
c6aa9ce1 | 6692 | |
bf62bbf1 | 6693 | fprintf (file, "\t%s#PROLOGUE# 1\n", ASM_COMMENT_START); |
c819be5b JW |
6694 | } |
6695 | \f | |
6696 | /* Do any necessary cleanup after a function to restore stack, frame, | |
6697 | and regs. */ | |
6698 | ||
6699 | void | |
c6aa9ce1 | 6700 | sparc_flat_output_function_epilogue (file, size) |
c819be5b JW |
6701 | FILE *file; |
6702 | int size; | |
6703 | { | |
c819be5b JW |
6704 | rtx epilogue_delay = current_function_epilogue_delay_list; |
6705 | int noepilogue = FALSE; | |
c819be5b | 6706 | |
c6aa9ce1 | 6707 | /* This is only for the human reader. */ |
bf62bbf1 | 6708 | fprintf (file, "\t%s#EPILOGUE#\n", ASM_COMMENT_START); |
c6aa9ce1 | 6709 | |
c819be5b JW |
6710 | /* The epilogue does not depend on any registers, but the stack |
6711 | registers, so we assume that if we have 1 pending nop, it can be | |
6712 | ignored, and 2 it must be filled (2 nops occur for integer | |
6713 | multiply and divide). */ | |
6714 | ||
6715 | size = SPARC_STACK_ALIGN (size); | |
86735b02 | 6716 | size = (!current_frame_info.initialized |
c6aa9ce1 | 6717 | ? sparc_flat_compute_frame_size (size) |
c819be5b JW |
6718 | : current_frame_info.total_size); |
6719 | ||
86735b02 | 6720 | if (size == 0 && epilogue_delay == 0) |
c819be5b JW |
6721 | { |
6722 | rtx insn = get_last_insn (); | |
6723 | ||
6724 | /* If the last insn was a BARRIER, we don't have to write any code | |
6725 | because a jump (aka return) was put there. */ | |
6726 | if (GET_CODE (insn) == NOTE) | |
6727 | insn = prev_nonnote_insn (insn); | |
6728 | if (insn && GET_CODE (insn) == BARRIER) | |
6729 | noepilogue = TRUE; | |
6730 | } | |
6731 | ||
6732 | if (!noepilogue) | |
6733 | { | |
86735b02 DE |
6734 | unsigned int reg_offset = current_frame_info.reg_offset; |
6735 | unsigned int size1; | |
99f44eba KG |
6736 | const char *sp_str = reg_names[STACK_POINTER_REGNUM]; |
6737 | const char *fp_str = reg_names[FRAME_POINTER_REGNUM]; | |
3bb5de61 | 6738 | const char *t1_str = "%g1"; |
86735b02 | 6739 | |
c819be5b JW |
6740 | /* In the reload sequence, we don't need to fill the load delay |
6741 | slots for most of the loads, also see if we can fill the final | |
6742 | delay slot if not otherwise filled by the reload sequence. */ | |
6743 | ||
86735b02 | 6744 | if (size > 4095) |
e0d80184 | 6745 | fprintf (file, "\tset\t%d, %s\n", size, t1_str); |
c819be5b JW |
6746 | |
6747 | if (frame_pointer_needed) | |
6748 | { | |
86735b02 | 6749 | if (size > 4095) |
e0d80184 | 6750 | fprintf (file,"\tsub\t%s, %s, %s\t\t%s# sp not trusted here\n", |
bf62bbf1 | 6751 | fp_str, t1_str, sp_str, ASM_COMMENT_START); |
c819be5b | 6752 | else |
e0d80184 | 6753 | fprintf (file,"\tsub\t%s, %d, %s\t\t%s# sp not trusted here\n", |
bf62bbf1 | 6754 | fp_str, size, sp_str, ASM_COMMENT_START); |
c819be5b JW |
6755 | } |
6756 | ||
ddd5a7c1 | 6757 | /* Is the entire register save area offsettable from %sp? */ |
fbd039b2 | 6758 | if (reg_offset < 4096 - 64 * (unsigned) UNITS_PER_WORD) |
86735b02 DE |
6759 | { |
6760 | size1 = 0; | |
6761 | } | |
6762 | else | |
6763 | { | |
6764 | /* Restore %sp in two steps, but make sure there is always a | |
6765 | 64 byte register save area, and %sp is properly aligned. */ | |
6766 | /* Amount to increment %sp by, the first time. */ | |
6767 | size1 = ((reg_offset - 64 - 16) + 15) & -16; | |
6768 | /* Offset to register save area from %sp. */ | |
6769 | reg_offset = size1 - reg_offset; | |
6770 | ||
e0d80184 | 6771 | fprintf (file, "\tset\t%d, %s\n\tadd\t%s, %s, %s\n", |
86735b02 DE |
6772 | size1, t1_str, sp_str, t1_str, sp_str); |
6773 | } | |
6774 | ||
6775 | /* We must restore the frame pointer and return address reg first | |
6776 | because they are treated specially by the prologue output code. */ | |
6777 | if (current_frame_info.gmask & FRAME_POINTER_MASK) | |
6778 | { | |
e0d80184 | 6779 | fprintf (file, "\tld\t[%s+%d], %s\n", |
86735b02 DE |
6780 | sp_str, reg_offset, fp_str); |
6781 | reg_offset += 4; | |
6782 | } | |
6783 | if (current_frame_info.gmask & RETURN_ADDR_MASK) | |
6784 | { | |
e0d80184 | 6785 | fprintf (file, "\tld\t[%s+%d], %s\n", |
86735b02 DE |
6786 | sp_str, reg_offset, reg_names[RETURN_ADDR_REGNUM]); |
6787 | reg_offset += 4; | |
6788 | } | |
6789 | ||
6790 | /* Restore any remaining saved registers. */ | |
6791 | sparc_flat_save_restore (file, sp_str, reg_offset, | |
6792 | current_frame_info.gmask & ~(FRAME_POINTER_MASK | RETURN_ADDR_MASK), | |
6793 | current_frame_info.fmask, | |
c53aa195 | 6794 | "ld", "ldd", 0); |
86735b02 DE |
6795 | |
6796 | /* If we had to increment %sp in two steps, record it so the second | |
6797 | restoration in the epilogue finishes up. */ | |
6798 | if (size1 > 0) | |
6799 | { | |
6800 | size -= size1; | |
6801 | if (size > 4095) | |
e0d80184 | 6802 | fprintf (file, "\tset\t%d, %s\n", |
86735b02 DE |
6803 | size, t1_str); |
6804 | } | |
c819be5b | 6805 | |
c819be5b | 6806 | if (current_function_returns_struct) |
e0d80184 | 6807 | fprintf (file, "\tjmp\t%%o7+12\n"); |
c819be5b JW |
6808 | else |
6809 | fprintf (file, "\tretl\n"); | |
6810 | ||
6811 | /* If the only register saved is the return address, we need a | |
6812 | nop, unless we have an instruction to put into it. Otherwise | |
6813 | we don't since reloading multiple registers doesn't reference | |
6814 | the register being loaded. */ | |
6815 | ||
6816 | if (epilogue_delay) | |
6817 | { | |
86735b02 | 6818 | if (size) |
c819be5b JW |
6819 | abort (); |
6820 | final_scan_insn (XEXP (epilogue_delay, 0), file, 1, -2, 1); | |
6821 | } | |
6822 | ||
86735b02 | 6823 | else if (size > 4095) |
e0d80184 | 6824 | fprintf (file, "\tadd\t%s, %s, %s\n", sp_str, t1_str, sp_str); |
c819be5b | 6825 | |
86735b02 | 6826 | else if (size > 0) |
e0d80184 | 6827 | fprintf (file, "\tadd\t%s, %d, %s\n", sp_str, size, sp_str); |
c819be5b JW |
6828 | |
6829 | else | |
6830 | fprintf (file, "\tnop\n"); | |
6831 | } | |
6832 | ||
6833 | /* Reset state info for each function. */ | |
6834 | current_frame_info = zero_frame_info; | |
e0d80184 DM |
6835 | |
6836 | sparc_output_deferred_case_vectors (); | |
c819be5b JW |
6837 | } |
6838 | \f | |
6839 | /* Define the number of delay slots needed for the function epilogue. | |
6840 | ||
6841 | On the sparc, we need a slot if either no stack has been allocated, | |
6842 | or the only register saved is the return register. */ | |
6843 | ||
6844 | int | |
c6aa9ce1 | 6845 | sparc_flat_epilogue_delay_slots () |
c819be5b JW |
6846 | { |
6847 | if (!current_frame_info.initialized) | |
c6aa9ce1 | 6848 | (void) sparc_flat_compute_frame_size (get_frame_size ()); |
c819be5b JW |
6849 | |
6850 | if (current_frame_info.total_size == 0) | |
6851 | return 1; | |
6852 | ||
c819be5b JW |
6853 | return 0; |
6854 | } | |
6855 | ||
6856 | /* Return true is TRIAL is a valid insn for the epilogue delay slot. | |
6857 | Any single length instruction which doesn't reference the stack or frame | |
6858 | pointer is OK. */ | |
6859 | ||
6860 | int | |
c6aa9ce1 | 6861 | sparc_flat_eligible_for_epilogue_delay (trial, slot) |
c819be5b | 6862 | rtx trial; |
db3d4438 | 6863 | int slot ATTRIBUTE_UNUSED; |
c819be5b | 6864 | { |
c4ce6853 DE |
6865 | rtx pat = PATTERN (trial); |
6866 | ||
6867 | if (get_attr_length (trial) != 1) | |
6868 | return 0; | |
6869 | ||
c4ce6853 DE |
6870 | if (! reg_mentioned_p (stack_pointer_rtx, pat) |
6871 | && ! reg_mentioned_p (frame_pointer_rtx, pat)) | |
c819be5b | 6872 | return 1; |
c4ce6853 | 6873 | |
c819be5b JW |
6874 | return 0; |
6875 | } | |
dbb54862 JW |
6876 | \f |
6877 | /* Adjust the cost of a scheduling dependency. Return the new cost of | |
6878 | a dependency LINK or INSN on DEP_INSN. COST is the current cost. */ | |
6879 | ||
8947065c | 6880 | static int |
dbb54862 JW |
6881 | supersparc_adjust_cost (insn, link, dep_insn, cost) |
6882 | rtx insn; | |
6883 | rtx link; | |
6884 | rtx dep_insn; | |
6885 | int cost; | |
6886 | { | |
6887 | enum attr_type insn_type; | |
6888 | ||
6889 | if (! recog_memoized (insn)) | |
6890 | return 0; | |
6891 | ||
6892 | insn_type = get_attr_type (insn); | |
6893 | ||
6894 | if (REG_NOTE_KIND (link) == 0) | |
6895 | { | |
6896 | /* Data dependency; DEP_INSN writes a register that INSN reads some | |
6897 | cycles later. */ | |
6898 | ||
6899 | /* if a load, then the dependence must be on the memory address; | |
3bc8b61e DM |
6900 | add an extra "cycle". Note that the cost could be two cycles |
6901 | if the reg was written late in an instruction group; we ca not tell | |
dbb54862 JW |
6902 | here. */ |
6903 | if (insn_type == TYPE_LOAD || insn_type == TYPE_FPLOAD) | |
6904 | return cost + 3; | |
6905 | ||
6906 | /* Get the delay only if the address of the store is the dependence. */ | |
6907 | if (insn_type == TYPE_STORE || insn_type == TYPE_FPSTORE) | |
6908 | { | |
6909 | rtx pat = PATTERN(insn); | |
6910 | rtx dep_pat = PATTERN (dep_insn); | |
6911 | ||
6912 | if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET) | |
3bc8b61e | 6913 | return cost; /* This should not happen! */ |
dbb54862 JW |
6914 | |
6915 | /* The dependency between the two instructions was on the data that | |
6916 | is being stored. Assume that this implies that the address of the | |
6917 | store is not dependent. */ | |
6918 | if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat))) | |
6919 | return cost; | |
6920 | ||
6921 | return cost + 3; /* An approximation. */ | |
6922 | } | |
6923 | ||
6924 | /* A shift instruction cannot receive its data from an instruction | |
6925 | in the same cycle; add a one cycle penalty. */ | |
6926 | if (insn_type == TYPE_SHIFT) | |
6927 | return cost + 3; /* Split before cascade into shift. */ | |
6928 | } | |
6929 | else | |
6930 | { | |
6931 | /* Anti- or output- dependency; DEP_INSN reads/writes a register that | |
6932 | INSN writes some cycles later. */ | |
6933 | ||
6934 | /* These are only significant for the fpu unit; writing a fp reg before | |
6935 | the fpu has finished with it stalls the processor. */ | |
6936 | ||
6937 | /* Reusing an integer register causes no problems. */ | |
6938 | if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT) | |
6939 | return 0; | |
6940 | } | |
6941 | ||
6942 | return cost; | |
6943 | } | |
bfd6bc60 | 6944 | |
8947065c RH |
6945 | static int |
6946 | hypersparc_adjust_cost (insn, link, dep_insn, cost) | |
6947 | rtx insn; | |
6948 | rtx link; | |
6949 | rtx dep_insn; | |
6950 | int cost; | |
6951 | { | |
6952 | enum attr_type insn_type, dep_type; | |
6953 | rtx pat = PATTERN(insn); | |
6954 | rtx dep_pat = PATTERN (dep_insn); | |
6955 | ||
6956 | if (recog_memoized (insn) < 0 || recog_memoized (dep_insn) < 0) | |
6957 | return cost; | |
6958 | ||
6959 | insn_type = get_attr_type (insn); | |
6960 | dep_type = get_attr_type (dep_insn); | |
6961 | ||
6962 | switch (REG_NOTE_KIND (link)) | |
6963 | { | |
6964 | case 0: | |
6965 | /* Data dependency; DEP_INSN writes a register that INSN reads some | |
6966 | cycles later. */ | |
6967 | ||
6968 | switch (insn_type) | |
6969 | { | |
6970 | case TYPE_STORE: | |
6971 | case TYPE_FPSTORE: | |
6972 | /* Get the delay iff the address of the store is the dependence. */ | |
6973 | if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET) | |
6974 | return cost; | |
6975 | ||
6976 | if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat))) | |
6977 | return cost; | |
6978 | return cost + 3; | |
6979 | ||
6980 | case TYPE_LOAD: | |
6981 | case TYPE_SLOAD: | |
6982 | case TYPE_FPLOAD: | |
6983 | /* If a load, then the dependence must be on the memory address. If | |
6984 | the addresses aren't equal, then it might be a false dependency */ | |
6985 | if (dep_type == TYPE_STORE || dep_type == TYPE_FPSTORE) | |
6986 | { | |
6987 | if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET | |
6988 | || GET_CODE (SET_DEST (dep_pat)) != MEM | |
6989 | || GET_CODE (SET_SRC (pat)) != MEM | |
6990 | || ! rtx_equal_p (XEXP (SET_DEST (dep_pat), 0), | |
6991 | XEXP (SET_SRC (pat), 0))) | |
6992 | return cost + 2; | |
6993 | ||
6994 | return cost + 8; | |
6995 | } | |
6996 | break; | |
6997 | ||
6998 | case TYPE_BRANCH: | |
6999 | /* Compare to branch latency is 0. There is no benefit from | |
7000 | separating compare and branch. */ | |
7001 | if (dep_type == TYPE_COMPARE) | |
7002 | return 0; | |
7003 | /* Floating point compare to branch latency is less than | |
7004 | compare to conditional move. */ | |
7005 | if (dep_type == TYPE_FPCMP) | |
7006 | return cost - 1; | |
7007 | break; | |
3bb5de61 KG |
7008 | default: |
7009 | break; | |
8947065c RH |
7010 | } |
7011 | break; | |
7012 | ||
7013 | case REG_DEP_ANTI: | |
7014 | /* Anti-dependencies only penalize the fpu unit. */ | |
7015 | if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT) | |
7016 | return 0; | |
7017 | break; | |
7018 | ||
7019 | default: | |
7020 | break; | |
7021 | } | |
7022 | ||
7023 | return cost; | |
7024 | } | |
7025 | ||
7026 | static int | |
7027 | ultrasparc_adjust_cost (insn, link, dep_insn, cost) | |
7028 | rtx insn; | |
7029 | rtx link; | |
7030 | rtx dep_insn; | |
7031 | int cost; | |
7032 | { | |
7033 | enum attr_type insn_type, dep_type; | |
7034 | rtx pat = PATTERN(insn); | |
7035 | rtx dep_pat = PATTERN (dep_insn); | |
7036 | ||
7037 | if (recog_memoized (insn) < 0 || recog_memoized (dep_insn) < 0) | |
7038 | return cost; | |
7039 | ||
7040 | insn_type = get_attr_type (insn); | |
7041 | dep_type = get_attr_type (dep_insn); | |
7042 | ||
7043 | /* Nothing issues in parallel with integer multiplies, so | |
7044 | mark as zero cost since the scheduler can not do anything | |
7045 | about it. */ | |
7046 | if (insn_type == TYPE_IMUL) | |
7047 | return 0; | |
7048 | ||
7049 | #define SLOW_FP(dep_type) \ | |
c0ec7a75 DM |
7050 | (dep_type == TYPE_FPSQRTS || dep_type == TYPE_FPSQRTD || \ |
7051 | dep_type == TYPE_FPDIVS || dep_type == TYPE_FPDIVD) | |
8947065c RH |
7052 | |
7053 | switch (REG_NOTE_KIND (link)) | |
7054 | { | |
7055 | case 0: | |
7056 | /* Data dependency; DEP_INSN writes a register that INSN reads some | |
7057 | cycles later. */ | |
7058 | ||
7059 | if (dep_type == TYPE_CMOVE) | |
7060 | { | |
7061 | /* Instructions that read the result of conditional moves cannot | |
7062 | be in the same group or the following group. */ | |
7063 | return cost + 1; | |
7064 | } | |
7065 | ||
7066 | switch (insn_type) | |
7067 | { | |
7068 | /* UltraSPARC can dual issue a store and an instruction setting | |
7069 | the value stored, except for divide and square root. */ | |
7070 | case TYPE_FPSTORE: | |
7071 | if (! SLOW_FP (dep_type)) | |
7072 | return 0; | |
7073 | return cost; | |
7074 | ||
7075 | case TYPE_STORE: | |
7076 | if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET) | |
7077 | return cost; | |
7078 | ||
7079 | if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat))) | |
7080 | /* The dependency between the two instructions is on the data | |
7081 | that is being stored. Assume that the address of the store | |
7082 | is not also dependent. */ | |
7083 | return 0; | |
7084 | return cost; | |
7085 | ||
7086 | case TYPE_LOAD: | |
7087 | case TYPE_SLOAD: | |
7088 | case TYPE_FPLOAD: | |
7089 | /* A load does not return data until at least 11 cycles after | |
7090 | a store to the same location. 3 cycles are accounted for | |
7091 | in the load latency; add the other 8 here. */ | |
7092 | if (dep_type == TYPE_STORE || dep_type == TYPE_FPSTORE) | |
7093 | { | |
7094 | /* If the addresses are not equal this may be a false | |
7095 | dependency because pointer aliasing could not be | |
7096 | determined. Add only 2 cycles in that case. 2 is | |
7097 | an arbitrary compromise between 8, which would cause | |
7098 | the scheduler to generate worse code elsewhere to | |
7099 | compensate for a dependency which might not really | |
7100 | exist, and 0. */ | |
7101 | if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET | |
7102 | || GET_CODE (SET_SRC (pat)) != MEM | |
7103 | || GET_CODE (SET_DEST (dep_pat)) != MEM | |
7104 | || ! rtx_equal_p (XEXP (SET_SRC (pat), 0), | |
7105 | XEXP (SET_DEST (dep_pat), 0))) | |
7106 | return cost + 2; | |
7107 | ||
7108 | return cost + 8; | |
7109 | } | |
7110 | return cost; | |
7111 | ||
7112 | case TYPE_BRANCH: | |
7113 | /* Compare to branch latency is 0. There is no benefit from | |
7114 | separating compare and branch. */ | |
7115 | if (dep_type == TYPE_COMPARE) | |
7116 | return 0; | |
7117 | /* Floating point compare to branch latency is less than | |
7118 | compare to conditional move. */ | |
7119 | if (dep_type == TYPE_FPCMP) | |
7120 | return cost - 1; | |
7121 | return cost; | |
7122 | ||
7123 | case TYPE_FPCMOVE: | |
7124 | /* FMOVR class instructions can not issue in the same cycle | |
7125 | or the cycle after an instruction which writes any | |
7126 | integer register. Model this as cost 2 for dependent | |
7127 | instructions. */ | |
7128 | if ((dep_type == TYPE_IALU || dep_type == TYPE_UNARY | |
7129 | || dep_type == TYPE_BINARY) | |
7130 | && cost < 2) | |
7131 | return 2; | |
7132 | /* Otherwise check as for integer conditional moves. */ | |
7133 | ||
7134 | case TYPE_CMOVE: | |
7135 | /* Conditional moves involving integer registers wait until | |
7136 | 3 cycles after loads return data. The interlock applies | |
7137 | to all loads, not just dependent loads, but that is hard | |
7138 | to model. */ | |
7139 | if (dep_type == TYPE_LOAD || dep_type == TYPE_SLOAD) | |
7140 | return cost + 3; | |
7141 | return cost; | |
7142 | ||
7143 | default: | |
7144 | break; | |
7145 | } | |
7146 | break; | |
7147 | ||
7148 | case REG_DEP_ANTI: | |
7149 | /* Divide and square root lock destination registers for full latency. */ | |
7150 | if (! SLOW_FP (dep_type)) | |
7151 | return 0; | |
7152 | break; | |
7153 | ||
7154 | case REG_DEP_OUTPUT: | |
7155 | /* IEU and FPU instruction that have the same destination | |
7156 | register cannot be grouped together. */ | |
7157 | return cost + 1; | |
7158 | ||
7159 | default: | |
7160 | break; | |
7161 | } | |
7162 | ||
7163 | /* Other costs not accounted for: | |
7164 | - Single precision floating point loads lock the other half of | |
7165 | the even/odd register pair. | |
7166 | - Several hazards associated with ldd/std are ignored because these | |
7167 | instructions are rarely generated for V9. | |
7168 | - The floating point pipeline can not have both a single and double | |
7169 | precision operation active at the same time. Format conversions | |
7170 | and graphics instructions are given honorary double precision status. | |
7171 | - call and jmpl are always the first instruction in a group. */ | |
7172 | ||
7173 | return cost; | |
7174 | ||
7175 | #undef SLOW_FP | |
7176 | } | |
7177 | ||
7178 | int | |
7179 | sparc_adjust_cost(insn, link, dep, cost) | |
7180 | rtx insn; | |
7181 | rtx link; | |
7182 | rtx dep; | |
7183 | int cost; | |
7184 | { | |
7185 | switch (sparc_cpu) | |
7186 | { | |
7187 | case PROCESSOR_SUPERSPARC: | |
7188 | cost = supersparc_adjust_cost (insn, link, dep, cost); | |
7189 | break; | |
7190 | case PROCESSOR_HYPERSPARC: | |
7191 | case PROCESSOR_SPARCLITE86X: | |
7192 | cost = hypersparc_adjust_cost (insn, link, dep, cost); | |
7193 | break; | |
7194 | case PROCESSOR_ULTRASPARC: | |
7195 | cost = ultrasparc_adjust_cost (insn, link, dep, cost); | |
7196 | break; | |
7197 | default: | |
7198 | break; | |
7199 | } | |
7200 | return cost; | |
7201 | } | |
7202 | ||
3bc8b61e DM |
7203 | /* This describes the state of the UltraSPARC pipeline during |
7204 | instruction scheduling. */ | |
7205 | ||
b96a5ea5 KG |
7206 | #define TMASK(__x) ((unsigned)1 << ((int)(__x))) |
7207 | #define UMASK(__x) ((unsigned)1 << ((int)(__x))) | |
3bc8b61e DM |
7208 | |
7209 | enum ultra_code { NONE=0, /* no insn at all */ | |
7210 | IEU0, /* shifts and conditional moves */ | |
7211 | IEU1, /* condition code setting insns, calls+jumps */ | |
7212 | IEUN, /* all other single cycle ieu insns */ | |
7213 | LSU, /* loads and stores */ | |
7214 | CTI, /* branches */ | |
7215 | FPM, /* FPU pipeline 1, multiplies and divides */ | |
7216 | FPA, /* FPU pipeline 2, all other operations */ | |
7217 | SINGLE, /* single issue instructions */ | |
7218 | NUM_ULTRA_CODES }; | |
7219 | ||
f6da8bc3 KG |
7220 | static enum ultra_code ultra_code_from_mask PARAMS ((int)); |
7221 | static void ultra_schedule_insn PARAMS ((rtx *, rtx *, int, enum ultra_code)); | |
b1474bb7 | 7222 | |
3bb5de61 | 7223 | static const char *ultra_code_names[NUM_ULTRA_CODES] = { |
3bc8b61e DM |
7224 | "NONE", "IEU0", "IEU1", "IEUN", "LSU", "CTI", |
7225 | "FPM", "FPA", "SINGLE" }; | |
7226 | ||
7227 | struct ultrasparc_pipeline_state { | |
7228 | /* The insns in this group. */ | |
7229 | rtx group[4]; | |
7230 | ||
7231 | /* The code for each insn. */ | |
7232 | enum ultra_code codes[4]; | |
7233 | ||
7234 | /* Which insns in this group have been committed by the | |
7235 | scheduler. This is how we determine how many more | |
7236 | can issue this cycle. */ | |
7237 | char commit[4]; | |
7238 | ||
7239 | /* How many insns in this group. */ | |
7240 | char group_size; | |
7241 | ||
7242 | /* Mask of free slots still in this group. */ | |
7243 | char free_slot_mask; | |
7244 | ||
7245 | /* The slotter uses the following to determine what other | |
7246 | insn types can still make their way into this group. */ | |
7247 | char contents [NUM_ULTRA_CODES]; | |
7248 | char num_ieu_insns; | |
7249 | }; | |
7250 | ||
7251 | #define ULTRA_NUM_HIST 8 | |
7252 | static struct ultrasparc_pipeline_state ultra_pipe_hist[ULTRA_NUM_HIST]; | |
7253 | static int ultra_cur_hist; | |
7254 | static int ultra_cycles_elapsed; | |
7255 | ||
7256 | #define ultra_pipe (ultra_pipe_hist[ultra_cur_hist]) | |
7257 | ||
7258 | /* Given TYPE_MASK compute the ultra_code it has. */ | |
7259 | static enum ultra_code | |
7260 | ultra_code_from_mask (type_mask) | |
7261 | int type_mask; | |
7262 | { | |
3bc8b61e DM |
7263 | if (type_mask & (TMASK (TYPE_SHIFT) | TMASK (TYPE_CMOVE))) |
7264 | return IEU0; | |
7265 | else if (type_mask & (TMASK (TYPE_COMPARE) | | |
7266 | TMASK (TYPE_CALL) | | |
7d167afd | 7267 | TMASK (TYPE_SIBCALL) | |
3bc8b61e DM |
7268 | TMASK (TYPE_UNCOND_BRANCH))) |
7269 | return IEU1; | |
7270 | else if (type_mask & (TMASK (TYPE_IALU) | TMASK (TYPE_BINARY) | | |
7271 | TMASK (TYPE_MOVE) | TMASK (TYPE_UNARY))) | |
7272 | return IEUN; | |
7273 | else if (type_mask & (TMASK (TYPE_LOAD) | TMASK (TYPE_SLOAD) | | |
7274 | TMASK (TYPE_STORE) | TMASK (TYPE_FPLOAD) | | |
7275 | TMASK (TYPE_FPSTORE))) | |
7276 | return LSU; | |
7277 | else if (type_mask & (TMASK (TYPE_FPMUL) | TMASK (TYPE_FPDIVS) | | |
c0ec7a75 DM |
7278 | TMASK (TYPE_FPDIVD) | TMASK (TYPE_FPSQRTS) | |
7279 | TMASK (TYPE_FPSQRTD))) | |
3bc8b61e DM |
7280 | return FPM; |
7281 | else if (type_mask & (TMASK (TYPE_FPMOVE) | TMASK (TYPE_FPCMOVE) | | |
7282 | TMASK (TYPE_FP) | TMASK (TYPE_FPCMP))) | |
7283 | return FPA; | |
7284 | else if (type_mask & TMASK (TYPE_BRANCH)) | |
7285 | return CTI; | |
7286 | ||
7287 | return SINGLE; | |
7288 | } | |
7289 | ||
7290 | /* Check INSN (a conditional move) and make sure that it's | |
7291 | results are available at this cycle. Return 1 if the | |
7292 | results are in fact ready. */ | |
7293 | static int | |
7294 | ultra_cmove_results_ready_p (insn) | |
7295 | rtx insn; | |
7296 | { | |
7297 | struct ultrasparc_pipeline_state *up; | |
7298 | int entry, slot; | |
7299 | ||
7300 | /* If this got dispatched in the previous | |
7301 | group, the results are not ready. */ | |
1f0e6e28 | 7302 | entry = (ultra_cur_hist - 1) & (ULTRA_NUM_HIST - 1); |
3bc8b61e DM |
7303 | up = &ultra_pipe_hist[entry]; |
7304 | slot = 4; | |
7305 | while (--slot >= 0) | |
7306 | if (up->group[slot] == insn) | |
c305b1a7 | 7307 | return 0; |
3bc8b61e | 7308 | |
c305b1a7 | 7309 | return 1; |
3bc8b61e DM |
7310 | } |
7311 | ||
7312 | /* Walk backwards in pipeline history looking for FPU | |
7313 | operations which use a mode different than FPMODE and | |
7314 | will create a stall if an insn using FPMODE were to be | |
7315 | dispatched this cycle. */ | |
7316 | static int | |
7317 | ultra_fpmode_conflict_exists (fpmode) | |
7318 | enum machine_mode fpmode; | |
7319 | { | |
7320 | int hist_ent; | |
7321 | int hist_lim; | |
7322 | ||
1f0e6e28 | 7323 | hist_ent = (ultra_cur_hist - 1) & (ULTRA_NUM_HIST - 1); |
3bc8b61e DM |
7324 | if (ultra_cycles_elapsed < 4) |
7325 | hist_lim = ultra_cycles_elapsed; | |
7326 | else | |
7327 | hist_lim = 4; | |
7328 | while (hist_lim > 0) | |
7329 | { | |
7330 | struct ultrasparc_pipeline_state *up = &ultra_pipe_hist[hist_ent]; | |
7331 | int slot = 4; | |
7332 | ||
7333 | while (--slot >= 0) | |
7334 | { | |
7335 | rtx insn = up->group[slot]; | |
7336 | enum machine_mode this_mode; | |
3bc8b61e DM |
7337 | rtx pat; |
7338 | ||
7339 | if (! insn | |
7340 | || GET_CODE (insn) != INSN | |
7341 | || (pat = PATTERN (insn)) == 0 | |
7342 | || GET_CODE (pat) != SET) | |
7343 | continue; | |
7344 | ||
7345 | this_mode = GET_MODE (SET_DEST (pat)); | |
7346 | if ((this_mode != SFmode | |
7347 | && this_mode != DFmode) | |
7348 | || this_mode == fpmode) | |
7349 | continue; | |
7350 | ||
7351 | /* If it is not FMOV, FABS, FNEG, FDIV, or FSQRT then | |
ddf80874 DM |
7352 | we will get a stall. Loads and stores are independant |
7353 | of these rules. */ | |
3bc8b61e DM |
7354 | if (GET_CODE (SET_SRC (pat)) != ABS |
7355 | && GET_CODE (SET_SRC (pat)) != NEG | |
7356 | && ((TMASK (get_attr_type (insn)) & | |
7357 | (TMASK (TYPE_FPDIVS) | TMASK (TYPE_FPDIVD) | | |
c0ec7a75 DM |
7358 | TMASK (TYPE_FPMOVE) | TMASK (TYPE_FPSQRTS) | |
7359 | TMASK (TYPE_FPSQRTD) | | |
ddf80874 | 7360 | TMASK (TYPE_LOAD) | TMASK (TYPE_STORE))) == 0)) |
3bc8b61e DM |
7361 | return 1; |
7362 | } | |
7363 | hist_lim--; | |
1f0e6e28 | 7364 | hist_ent = (hist_ent - 1) & (ULTRA_NUM_HIST - 1); |
3bc8b61e DM |
7365 | } |
7366 | ||
7367 | /* No conflicts, safe to dispatch. */ | |
7368 | return 0; | |
7369 | } | |
7370 | ||
7371 | /* Find an instruction in LIST which has one of the | |
7372 | type attributes enumerated in TYPE_MASK. START | |
7373 | says where to begin the search. | |
7374 | ||
7375 | NOTE: This scheme depends upon the fact that we | |
7376 | have less than 32 distinct type attributes. */ | |
5a5325cb DM |
7377 | |
7378 | static int ultra_types_avail; | |
7379 | ||
3bc8b61e DM |
7380 | static rtx * |
7381 | ultra_find_type (type_mask, list, start) | |
7382 | int type_mask; | |
7383 | rtx *list; | |
7384 | int start; | |
7385 | { | |
7386 | int i; | |
7387 | ||
5a5325cb DM |
7388 | /* Short circuit if no such insn exists in the ready |
7389 | at the moment. */ | |
7390 | if ((type_mask & ultra_types_avail) == 0) | |
7391 | return 0; | |
7392 | ||
3bc8b61e DM |
7393 | for (i = start; i >= 0; i--) |
7394 | { | |
7395 | rtx insn = list[i]; | |
7396 | ||
7397 | if (recog_memoized (insn) >= 0 | |
7398 | && (TMASK(get_attr_type (insn)) & type_mask)) | |
7399 | { | |
ddf80874 | 7400 | enum machine_mode fpmode = SFmode; |
3bc8b61e DM |
7401 | rtx pat = 0; |
7402 | int slot; | |
7403 | int check_depend = 0; | |
7404 | int check_fpmode_conflict = 0; | |
7405 | ||
7406 | if (GET_CODE (insn) == INSN | |
7407 | && (pat = PATTERN(insn)) != 0 | |
7408 | && GET_CODE (pat) == SET | |
7409 | && !(type_mask & (TMASK (TYPE_STORE) | | |
7410 | TMASK (TYPE_FPSTORE)))) | |
7411 | { | |
7412 | check_depend = 1; | |
7413 | if (GET_MODE (SET_DEST (pat)) == SFmode | |
7414 | || GET_MODE (SET_DEST (pat)) == DFmode) | |
7415 | { | |
7416 | fpmode = GET_MODE (SET_DEST (pat)); | |
7417 | check_fpmode_conflict = 1; | |
7418 | } | |
7419 | } | |
7420 | ||
7421 | slot = 4; | |
7422 | while(--slot >= 0) | |
7423 | { | |
7424 | rtx slot_insn = ultra_pipe.group[slot]; | |
7425 | rtx slot_pat; | |
7426 | ||
7427 | /* Already issued, bad dependency, or FPU | |
7428 | mode conflict. */ | |
7429 | if (slot_insn != 0 | |
7430 | && (slot_pat = PATTERN (slot_insn)) != 0 | |
7431 | && ((insn == slot_insn) | |
7432 | || (check_depend == 1 | |
7433 | && GET_CODE (slot_insn) == INSN | |
7434 | && GET_CODE (slot_pat) == SET | |
5a5325cb DM |
7435 | && ((GET_CODE (SET_DEST (slot_pat)) == REG |
7436 | && GET_CODE (SET_SRC (pat)) == REG | |
7437 | && REGNO (SET_DEST (slot_pat)) == | |
7438 | REGNO (SET_SRC (pat))) | |
7439 | || (GET_CODE (SET_DEST (slot_pat)) == SUBREG | |
7440 | && GET_CODE (SET_SRC (pat)) == SUBREG | |
7441 | && REGNO (SUBREG_REG (SET_DEST (slot_pat))) == | |
7442 | REGNO (SUBREG_REG (SET_SRC (pat))) | |
7443 | && SUBREG_WORD (SET_DEST (slot_pat)) == | |
ddf80874 | 7444 | SUBREG_WORD (SET_SRC (pat))))) |
3bc8b61e DM |
7445 | || (check_fpmode_conflict == 1 |
7446 | && GET_CODE (slot_insn) == INSN | |
7447 | && GET_CODE (slot_pat) == SET | |
ddf80874 DM |
7448 | && (GET_MODE (SET_DEST (slot_pat)) == SFmode |
7449 | || GET_MODE (SET_DEST (slot_pat)) == DFmode) | |
7450 | && GET_MODE (SET_DEST (slot_pat)) != fpmode))) | |
3bc8b61e DM |
7451 | goto next; |
7452 | } | |
7453 | ||
7454 | /* Check for peculiar result availability and dispatch | |
7455 | interference situations. */ | |
7456 | if (pat != 0 | |
7457 | && ultra_cycles_elapsed > 0) | |
7458 | { | |
7459 | rtx link; | |
7460 | ||
7461 | for (link = LOG_LINKS (insn); link; link = XEXP (link, 1)) | |
7462 | { | |
7463 | rtx link_insn = XEXP (link, 0); | |
7464 | if (GET_CODE (link_insn) == INSN | |
7465 | && recog_memoized (link_insn) >= 0 | |
7466 | && (TMASK (get_attr_type (link_insn)) & | |
7467 | (TMASK (TYPE_CMOVE) | TMASK (TYPE_FPCMOVE))) | |
7468 | && ! ultra_cmove_results_ready_p (link_insn)) | |
7469 | goto next; | |
7470 | } | |
7471 | ||
7472 | if (check_fpmode_conflict | |
7473 | && ultra_fpmode_conflict_exists (fpmode)) | |
7474 | goto next; | |
7475 | } | |
7476 | ||
7477 | return &list[i]; | |
7478 | } | |
7479 | next: | |
5a5325cb | 7480 | ; |
3bc8b61e DM |
7481 | } |
7482 | return 0; | |
7483 | } | |
7484 | ||
5a5325cb DM |
7485 | static void |
7486 | ultra_build_types_avail (ready, n_ready) | |
7487 | rtx *ready; | |
7488 | int n_ready; | |
7489 | { | |
7490 | int i = n_ready - 1; | |
7491 | ||
7492 | ultra_types_avail = 0; | |
7493 | while(i >= 0) | |
7494 | { | |
7495 | rtx insn = ready[i]; | |
7496 | ||
7497 | if (recog_memoized (insn) >= 0) | |
7498 | ultra_types_avail |= TMASK (get_attr_type (insn)); | |
7499 | ||
7500 | i -= 1; | |
7501 | } | |
7502 | } | |
7503 | ||
3bc8b61e DM |
7504 | /* Place insn pointed to my IP into the pipeline. |
7505 | Make element THIS of READY be that insn if it | |
7506 | is not already. TYPE indicates the pipeline class | |
7507 | this insn falls into. */ | |
7508 | static void | |
7509 | ultra_schedule_insn (ip, ready, this, type) | |
7510 | rtx *ip; | |
7511 | rtx *ready; | |
7512 | int this; | |
7513 | enum ultra_code type; | |
7514 | { | |
7515 | int pipe_slot; | |
7516 | char mask = ultra_pipe.free_slot_mask; | |
c0ec7a75 | 7517 | rtx temp; |
3bc8b61e DM |
7518 | |
7519 | /* Obtain free slot. */ | |
7520 | for (pipe_slot = 0; pipe_slot < 4; pipe_slot++) | |
7521 | if ((mask & (1 << pipe_slot)) != 0) | |
7522 | break; | |
7523 | if (pipe_slot == 4) | |
7524 | abort (); | |
7525 | ||
7526 | /* In it goes, and it hasn't been committed yet. */ | |
7527 | ultra_pipe.group[pipe_slot] = *ip; | |
7528 | ultra_pipe.codes[pipe_slot] = type; | |
7529 | ultra_pipe.contents[type] = 1; | |
7530 | if (UMASK (type) & | |
7531 | (UMASK (IEUN) | UMASK (IEU0) | UMASK (IEU1))) | |
7532 | ultra_pipe.num_ieu_insns += 1; | |
7533 | ||
7534 | ultra_pipe.free_slot_mask = (mask & ~(1 << pipe_slot)); | |
7535 | ultra_pipe.group_size += 1; | |
7536 | ultra_pipe.commit[pipe_slot] = 0; | |
7537 | ||
7538 | /* Update ready list. */ | |
c0ec7a75 DM |
7539 | temp = *ip; |
7540 | while (ip != &ready[this]) | |
3bc8b61e | 7541 | { |
c0ec7a75 DM |
7542 | ip[0] = ip[1]; |
7543 | ++ip; | |
3bc8b61e | 7544 | } |
c0ec7a75 | 7545 | *ip = temp; |
3bc8b61e DM |
7546 | } |
7547 | ||
7548 | /* Advance to the next pipeline group. */ | |
7549 | static void | |
7550 | ultra_flush_pipeline () | |
7551 | { | |
1f0e6e28 | 7552 | ultra_cur_hist = (ultra_cur_hist + 1) & (ULTRA_NUM_HIST - 1); |
3bc8b61e DM |
7553 | ultra_cycles_elapsed += 1; |
7554 | bzero ((char *) &ultra_pipe, sizeof ultra_pipe); | |
7555 | ultra_pipe.free_slot_mask = 0xf; | |
7556 | } | |
7557 | ||
3bc8b61e DM |
7558 | /* Init our data structures for this current block. */ |
7559 | void | |
7560 | ultrasparc_sched_init (dump, sched_verbose) | |
ddf80874 DM |
7561 | FILE *dump ATTRIBUTE_UNUSED; |
7562 | int sched_verbose ATTRIBUTE_UNUSED; | |
3bc8b61e | 7563 | { |
b96a5ea5 | 7564 | bzero ((char *) ultra_pipe_hist, sizeof ultra_pipe_hist); |
3bc8b61e DM |
7565 | ultra_cur_hist = 0; |
7566 | ultra_cycles_elapsed = 0; | |
ddf80874 | 7567 | ultra_pipe.free_slot_mask = 0xf; |
3bc8b61e DM |
7568 | } |
7569 | ||
7570 | /* INSN has been scheduled, update pipeline commit state | |
7571 | and return how many instructions are still to be | |
7572 | scheduled in this group. */ | |
bfd6bc60 | 7573 | int |
3bc8b61e DM |
7574 | ultrasparc_variable_issue (insn) |
7575 | rtx insn; | |
7576 | { | |
7577 | struct ultrasparc_pipeline_state *up = &ultra_pipe; | |
7578 | int i, left_to_fire; | |
7579 | ||
7580 | left_to_fire = 0; | |
7581 | for (i = 0; i < 4; i++) | |
7582 | { | |
7583 | if (up->group[i] == 0) | |
7584 | continue; | |
7585 | ||
7586 | if (up->group[i] == insn) | |
7587 | { | |
7588 | up->commit[i] = 1; | |
7589 | } | |
7590 | else if (! up->commit[i]) | |
7591 | left_to_fire++; | |
7592 | } | |
7593 | ||
7594 | return left_to_fire; | |
7595 | } | |
7596 | ||
7597 | /* In actual_hazard_this_instance, we may have yanked some | |
7598 | instructions from the ready list due to conflict cost | |
7599 | adjustments. If so, and such an insn was in our pipeline | |
7600 | group, remove it and update state. */ | |
7601 | static void | |
7602 | ultra_rescan_pipeline_state (ready, n_ready) | |
7603 | rtx *ready; | |
7604 | int n_ready; | |
7605 | { | |
7606 | struct ultrasparc_pipeline_state *up = &ultra_pipe; | |
7607 | int i; | |
7608 | ||
7609 | for (i = 0; i < 4; i++) | |
7610 | { | |
7611 | rtx insn = up->group[i]; | |
3bc8b61e DM |
7612 | int j; |
7613 | ||
7614 | if (! insn) | |
7615 | continue; | |
7616 | ||
7617 | /* If it has been committed, then it was removed from | |
7618 | the ready list because it was actually scheduled, | |
7619 | and that is not the case we are searching for here. */ | |
7620 | if (up->commit[i] != 0) | |
7621 | continue; | |
7622 | ||
7623 | for (j = n_ready - 1; j >= 0; j--) | |
7624 | if (ready[j] == insn) | |
7625 | break; | |
7626 | ||
7627 | /* If we didn't find it, toss it. */ | |
7628 | if (j < 0) | |
7629 | { | |
7630 | enum ultra_code ucode = up->codes[i]; | |
7631 | ||
7632 | up->group[i] = 0; | |
7633 | up->codes[i] = NONE; | |
7634 | up->contents[ucode] = 0; | |
7635 | if (UMASK (ucode) & | |
7636 | (UMASK (IEUN) | UMASK (IEU0) | UMASK (IEU1))) | |
7637 | up->num_ieu_insns -= 1; | |
7638 | ||
7639 | up->free_slot_mask |= (1 << i); | |
7640 | up->group_size -= 1; | |
7641 | up->commit[i] = 0; | |
7642 | } | |
7643 | } | |
7644 | } | |
7645 | ||
7646 | void | |
7647 | ultrasparc_sched_reorder (dump, sched_verbose, ready, n_ready) | |
7648 | FILE *dump; | |
7649 | int sched_verbose; | |
7650 | rtx *ready; | |
7651 | int n_ready; | |
7652 | { | |
7653 | struct ultrasparc_pipeline_state *up = &ultra_pipe; | |
7654 | int i, this_insn; | |
7655 | ||
3bc8b61e DM |
7656 | if (sched_verbose) |
7657 | { | |
7658 | int n; | |
7659 | ||
7660 | fprintf (dump, "\n;;\tUltraSPARC Looking at ["); | |
7661 | for (n = n_ready - 1; n >= 0; n--) | |
7662 | { | |
7663 | rtx insn = ready[n]; | |
7664 | enum ultra_code ucode; | |
7665 | ||
7666 | if (recog_memoized (insn) < 0) | |
7667 | continue; | |
7668 | ucode = ultra_code_from_mask (TMASK (get_attr_type (insn))); | |
7669 | if (n != 0) | |
7670 | fprintf (dump, "%s(%d) ", | |
7671 | ultra_code_names[ucode], | |
7672 | INSN_UID (insn)); | |
7673 | else | |
7674 | fprintf (dump, "%s(%d)", | |
7675 | ultra_code_names[ucode], | |
7676 | INSN_UID (insn)); | |
7677 | } | |
7678 | fprintf (dump, "]\n"); | |
7679 | } | |
7680 | ||
7681 | this_insn = n_ready - 1; | |
7682 | ||
7683 | /* Skip over junk we don't understand. */ | |
7684 | while ((this_insn >= 0) | |
7685 | && recog_memoized (ready[this_insn]) < 0) | |
7686 | this_insn--; | |
7687 | ||
5a5325cb DM |
7688 | ultra_build_types_avail (ready, this_insn + 1); |
7689 | ||
3bc8b61e DM |
7690 | while (this_insn >= 0) { |
7691 | int old_group_size = up->group_size; | |
7692 | ||
7693 | if (up->group_size != 0) | |
7694 | { | |
7695 | int num_committed; | |
7696 | ||
7697 | num_committed = (up->commit[0] + up->commit[1] + | |
7698 | up->commit[2] + up->commit[3]); | |
7699 | /* If nothing has been commited from our group, or all of | |
7700 | them have. Clear out the (current cycle's) pipeline | |
7701 | state and start afresh. */ | |
7702 | if (num_committed == 0 | |
7703 | || num_committed == up->group_size) | |
7704 | { | |
ddf80874 DM |
7705 | ultra_flush_pipeline (); |
7706 | up = &ultra_pipe; | |
3bc8b61e DM |
7707 | old_group_size = 0; |
7708 | } | |
7709 | else | |
7710 | { | |
7711 | /* OK, some ready list insns got requeued and thus removed | |
7712 | from the ready list. Account for this fact. */ | |
7713 | ultra_rescan_pipeline_state (ready, n_ready); | |
7714 | ||
7715 | /* Something "changed", make this look like a newly | |
7716 | formed group so the code at the end of the loop | |
7717 | knows that progress was in fact made. */ | |
7718 | if (up->group_size != old_group_size) | |
ddf80874 | 7719 | old_group_size = 0; |
3bc8b61e DM |
7720 | } |
7721 | } | |
7722 | ||
7723 | if (up->group_size == 0) | |
7724 | { | |
7725 | /* If the pipeline is (still) empty and we have any single | |
7726 | group insns, get them out now as this is a good time. */ | |
7727 | rtx *ip = ultra_find_type ((TMASK (TYPE_RETURN) | TMASK (TYPE_ADDRESS) | | |
7728 | TMASK (TYPE_IMUL) | TMASK (TYPE_CMOVE) | | |
7729 | TMASK (TYPE_MULTI) | TMASK (TYPE_MISC)), | |
7730 | ready, this_insn); | |
7731 | if (ip) | |
7732 | { | |
7733 | ultra_schedule_insn (ip, ready, this_insn, SINGLE); | |
7734 | break; | |
7735 | } | |
7736 | ||
7737 | /* If we are not in the process of emptying out the pipe, try to | |
7738 | obtain an instruction which must be the first in it's group. */ | |
7739 | ip = ultra_find_type ((TMASK (TYPE_CALL) | | |
7d167afd | 7740 | TMASK (TYPE_SIBCALL) | |
3bc8b61e DM |
7741 | TMASK (TYPE_CALL_NO_DELAY_SLOT) | |
7742 | TMASK (TYPE_UNCOND_BRANCH)), | |
7743 | ready, this_insn); | |
7744 | if (ip) | |
7745 | { | |
7746 | ultra_schedule_insn (ip, ready, this_insn, IEU1); | |
7747 | this_insn--; | |
7748 | } | |
7749 | else if ((ip = ultra_find_type ((TMASK (TYPE_FPDIVS) | | |
7750 | TMASK (TYPE_FPDIVD) | | |
c0ec7a75 DM |
7751 | TMASK (TYPE_FPSQRTS) | |
7752 | TMASK (TYPE_FPSQRTD)), | |
3bc8b61e DM |
7753 | ready, this_insn)) != 0) |
7754 | { | |
7755 | ultra_schedule_insn (ip, ready, this_insn, FPM); | |
7756 | this_insn--; | |
7757 | } | |
7758 | } | |
7759 | ||
7760 | /* Try to fill the integer pipeline. First, look for an IEU0 specific | |
7761 | operation. We can't do more IEU operations if the first 3 slots are | |
7762 | all full or we have dispatched two IEU insns already. */ | |
7763 | if ((up->free_slot_mask & 0x7) != 0 | |
7764 | && up->num_ieu_insns < 2 | |
7765 | && up->contents[IEU0] == 0 | |
7766 | && up->contents[IEUN] == 0) | |
7767 | { | |
7768 | rtx *ip = ultra_find_type (TMASK(TYPE_SHIFT), ready, this_insn); | |
7769 | if (ip) | |
7770 | { | |
7771 | ultra_schedule_insn (ip, ready, this_insn, IEU0); | |
7772 | this_insn--; | |
7773 | } | |
7774 | } | |
7775 | ||
7776 | /* If we can, try to find an IEU1 specific or an unnamed | |
7777 | IEU instruction. */ | |
7778 | if ((up->free_slot_mask & 0x7) != 0 | |
7779 | && up->num_ieu_insns < 2) | |
7780 | { | |
7781 | rtx *ip = ultra_find_type ((TMASK (TYPE_IALU) | TMASK (TYPE_BINARY) | | |
7782 | TMASK (TYPE_MOVE) | TMASK (TYPE_UNARY) | | |
7783 | (up->contents[IEU1] == 0 ? TMASK (TYPE_COMPARE) : 0)), | |
7784 | ready, this_insn); | |
7785 | if (ip) | |
7786 | { | |
7787 | rtx insn = *ip; | |
7788 | ||
7789 | ultra_schedule_insn (ip, ready, this_insn, | |
7790 | (!up->contents[IEU1] | |
7791 | && get_attr_type (insn) == TYPE_COMPARE) | |
7792 | ? IEU1 : IEUN); | |
7793 | this_insn--; | |
7794 | } | |
7795 | } | |
7796 | ||
7797 | /* If only one IEU insn has been found, try to find another unnamed | |
7798 | IEU operation or an IEU1 specific one. */ | |
7799 | if ((up->free_slot_mask & 0x7) != 0 | |
7800 | && up->num_ieu_insns < 2) | |
7801 | { | |
7802 | rtx *ip; | |
7803 | int tmask = (TMASK (TYPE_IALU) | TMASK (TYPE_BINARY) | | |
7804 | TMASK (TYPE_MOVE) | TMASK (TYPE_UNARY)); | |
7805 | ||
7806 | if (!up->contents[IEU1]) | |
7807 | tmask |= TMASK (TYPE_COMPARE); | |
7808 | ip = ultra_find_type (tmask, ready, this_insn); | |
7809 | if (ip) | |
7810 | { | |
7811 | rtx insn = *ip; | |
7812 | ||
7813 | ultra_schedule_insn (ip, ready, this_insn, | |
7814 | (!up->contents[IEU1] | |
7815 | && get_attr_type (insn) == TYPE_COMPARE) | |
7816 | ? IEU1 : IEUN); | |
7817 | this_insn--; | |
7818 | } | |
7819 | } | |
7820 | ||
7821 | /* Try for a load or store, but such an insn can only be issued | |
7822 | if it is within' one of the first 3 slots. */ | |
7823 | if ((up->free_slot_mask & 0x7) != 0 | |
7824 | && up->contents[LSU] == 0) | |
7825 | { | |
7826 | rtx *ip = ultra_find_type ((TMASK (TYPE_LOAD) | TMASK (TYPE_SLOAD) | | |
7827 | TMASK (TYPE_STORE) | TMASK (TYPE_FPLOAD) | | |
7828 | TMASK (TYPE_FPSTORE)), ready, this_insn); | |
7829 | if (ip) | |
7830 | { | |
7831 | ultra_schedule_insn (ip, ready, this_insn, LSU); | |
7832 | this_insn--; | |
7833 | } | |
7834 | } | |
7835 | ||
7836 | /* Now find FPU operations, first FPM class. But not divisions or | |
7837 | square-roots because those will break the group up. Unlike all | |
7838 | the previous types, these can go in any slot. */ | |
7839 | if (up->free_slot_mask != 0 | |
7840 | && up->contents[FPM] == 0) | |
7841 | { | |
7842 | rtx *ip = ultra_find_type (TMASK (TYPE_FPMUL), ready, this_insn); | |
7843 | if (ip) | |
7844 | { | |
7845 | ultra_schedule_insn (ip, ready, this_insn, FPM); | |
7846 | this_insn--; | |
7847 | } | |
7848 | } | |
7849 | ||
7850 | /* Continue on with FPA class if we have not filled the group already. */ | |
7851 | if (up->free_slot_mask != 0 | |
7852 | && up->contents[FPA] == 0) | |
7853 | { | |
7854 | rtx *ip = ultra_find_type ((TMASK (TYPE_FPMOVE) | TMASK (TYPE_FPCMOVE) | | |
7855 | TMASK (TYPE_FP) | TMASK (TYPE_FPCMP)), | |
7856 | ready, this_insn); | |
7857 | if (ip) | |
7858 | { | |
7859 | ultra_schedule_insn (ip, ready, this_insn, FPA); | |
7860 | this_insn--; | |
7861 | } | |
7862 | } | |
7863 | ||
7864 | /* Finally, maybe stick a branch in here. */ | |
7865 | if (up->free_slot_mask != 0 | |
7866 | && up->contents[CTI] == 0) | |
7867 | { | |
7868 | rtx *ip = ultra_find_type (TMASK (TYPE_BRANCH), ready, this_insn); | |
7869 | ||
7870 | /* Try to slip in a branch only if it is one of the | |
7871 | next 2 in the ready list. */ | |
7872 | if (ip && ((&ready[this_insn] - ip) < 2)) | |
7873 | { | |
7874 | ultra_schedule_insn (ip, ready, this_insn, CTI); | |
7875 | this_insn--; | |
7876 | } | |
7877 | } | |
7878 | ||
7879 | up->group_size = 0; | |
7880 | for (i = 0; i < 4; i++) | |
7881 | if ((up->free_slot_mask & (1 << i)) == 0) | |
7882 | up->group_size++; | |
7883 | ||
7884 | /* See if we made any progress... */ | |
7885 | if (old_group_size != up->group_size) | |
7886 | break; | |
7887 | ||
7888 | /* Clean out the (current cycle's) pipeline state | |
ddf80874 DM |
7889 | and try once more. If we placed no instructions |
7890 | into the pipeline at all, it means a real hard | |
7891 | conflict exists with some earlier issued instruction | |
7892 | so we must advance to the next cycle to clear it up. */ | |
7893 | if (up->group_size == 0) | |
7894 | { | |
7895 | ultra_flush_pipeline (); | |
7896 | up = &ultra_pipe; | |
7897 | } | |
7898 | else | |
7899 | { | |
7900 | bzero ((char *) &ultra_pipe, sizeof ultra_pipe); | |
7901 | ultra_pipe.free_slot_mask = 0xf; | |
7902 | } | |
3bc8b61e DM |
7903 | } |
7904 | ||
7905 | if (sched_verbose) | |
7906 | { | |
7907 | int n, gsize; | |
7908 | ||
7909 | fprintf (dump, ";;\tUltraSPARC Launched ["); | |
7910 | gsize = up->group_size; | |
7911 | for (n = 0; n < 4; n++) | |
7912 | { | |
7913 | rtx insn = up->group[n]; | |
7914 | ||
7915 | if (! insn) | |
7916 | continue; | |
7917 | ||
7918 | gsize -= 1; | |
7919 | if (gsize != 0) | |
7920 | fprintf (dump, "%s(%d) ", | |
7921 | ultra_code_names[up->codes[n]], | |
7922 | INSN_UID (insn)); | |
7923 | else | |
7924 | fprintf (dump, "%s(%d)", | |
7925 | ultra_code_names[up->codes[n]], | |
7926 | INSN_UID (insn)); | |
7927 | } | |
7928 | fprintf (dump, "]\n"); | |
7929 | } | |
7930 | } | |
7931 | ||
bfd6bc60 JC |
7932 | int |
7933 | sparc_issue_rate () | |
7934 | { | |
7935 | switch (sparc_cpu) | |
7936 | { | |
7937 | default: | |
7938 | return 1; | |
bfd6bc60 | 7939 | case PROCESSOR_V9: |
284d86e9 | 7940 | /* Assume V9 processors are capable of at least dual-issue. */ |
bfd6bc60 JC |
7941 | return 2; |
7942 | case PROCESSOR_SUPERSPARC: | |
7943 | return 3; | |
393049a9 RH |
7944 | case PROCESSOR_HYPERSPARC: |
7945 | case PROCESSOR_SPARCLITE86X: | |
7946 | return 2; | |
bfd6bc60 JC |
7947 | case PROCESSOR_ULTRASPARC: |
7948 | return 4; | |
7949 | } | |
7950 | } | |
284d86e9 JC |
7951 | |
7952 | static int | |
7953 | set_extends(x, insn) | |
7954 | rtx x, insn; | |
7955 | { | |
7956 | register rtx pat = PATTERN (insn); | |
7957 | ||
7958 | switch (GET_CODE (SET_SRC (pat))) | |
7959 | { | |
7960 | /* Load and some shift instructions zero extend. */ | |
7961 | case MEM: | |
7962 | case ZERO_EXTEND: | |
7963 | /* sethi clears the high bits */ | |
7964 | case HIGH: | |
7965 | /* LO_SUM is used with sethi. sethi cleared the high | |
7966 | bits and the values used with lo_sum are positive */ | |
7967 | case LO_SUM: | |
284d86e9 JC |
7968 | /* Store flag stores 0 or 1 */ |
7969 | case LT: case LTU: | |
7970 | case GT: case GTU: | |
7971 | case LE: case LEU: | |
7972 | case GE: case GEU: | |
7973 | case EQ: | |
7974 | case NE: | |
7975 | return 1; | |
7976 | case AND: | |
7977 | { | |
7978 | rtx op1 = XEXP (SET_SRC (pat), 1); | |
7979 | if (GET_CODE (op1) == CONST_INT) | |
7980 | return INTVAL (op1) >= 0; | |
7981 | if (GET_CODE (XEXP (SET_SRC (pat), 0)) == REG | |
7982 | && sparc_check_64 (XEXP (SET_SRC (pat), 0), insn) == 1) | |
7983 | return 1; | |
7984 | if (GET_CODE (op1) == REG | |
7985 | && sparc_check_64 ((op1), insn) == 1) | |
7986 | return 1; | |
7987 | } | |
7988 | case ASHIFT: | |
7989 | case LSHIFTRT: | |
7990 | return GET_MODE (SET_SRC (pat)) == SImode; | |
7991 | /* Positive integers leave the high bits zero. */ | |
7992 | case CONST_DOUBLE: | |
7993 | return ! (CONST_DOUBLE_LOW (x) & 0x80000000); | |
7994 | case CONST_INT: | |
7995 | return ! (INTVAL (x) & 0x80000000); | |
7996 | case ASHIFTRT: | |
7997 | case SIGN_EXTEND: | |
7998 | return - (GET_MODE (SET_SRC (pat)) == SImode); | |
7999 | default: | |
8000 | return 0; | |
8001 | } | |
8002 | } | |
8003 | ||
e0d80184 DM |
8004 | /* We _ought_ to have only one kind per function, but... */ |
8005 | static rtx sparc_addr_diff_list; | |
8006 | static rtx sparc_addr_list; | |
8007 | ||
8008 | void | |
8009 | sparc_defer_case_vector (lab, vec, diff) | |
8010 | rtx lab, vec; | |
8011 | int diff; | |
8012 | { | |
8013 | vec = gen_rtx_EXPR_LIST (VOIDmode, lab, vec); | |
8014 | if (diff) | |
8015 | sparc_addr_diff_list | |
8016 | = gen_rtx_EXPR_LIST (VOIDmode, vec, sparc_addr_diff_list); | |
8017 | else | |
8018 | sparc_addr_list = gen_rtx_EXPR_LIST (VOIDmode, vec, sparc_addr_list); | |
8019 | } | |
8020 | ||
8021 | static void | |
8022 | sparc_output_addr_vec (vec) | |
8023 | rtx vec; | |
8024 | { | |
8025 | rtx lab = XEXP (vec, 0), body = XEXP (vec, 1); | |
8026 | int idx, vlen = XVECLEN (body, 0); | |
8027 | ||
d1accaa3 JJ |
8028 | #ifdef ASM_OUTPUT_ADDR_VEC_START |
8029 | ASM_OUTPUT_ADDR_VEC_START (asm_out_file); | |
8030 | #endif | |
8031 | ||
e0d80184 DM |
8032 | #ifdef ASM_OUTPUT_CASE_LABEL |
8033 | ASM_OUTPUT_CASE_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab), | |
8034 | NEXT_INSN (lab)); | |
8035 | #else | |
8036 | ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab)); | |
8037 | #endif | |
8038 | ||
8039 | for (idx = 0; idx < vlen; idx++) | |
8040 | { | |
8041 | ASM_OUTPUT_ADDR_VEC_ELT | |
8042 | (asm_out_file, CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 0, idx), 0))); | |
8043 | } | |
d1accaa3 JJ |
8044 | |
8045 | #ifdef ASM_OUTPUT_ADDR_VEC_END | |
8046 | ASM_OUTPUT_ADDR_VEC_END (asm_out_file); | |
8047 | #endif | |
e0d80184 DM |
8048 | } |
8049 | ||
8050 | static void | |
8051 | sparc_output_addr_diff_vec (vec) | |
8052 | rtx vec; | |
8053 | { | |
8054 | rtx lab = XEXP (vec, 0), body = XEXP (vec, 1); | |
8055 | rtx base = XEXP (XEXP (body, 0), 0); | |
8056 | int idx, vlen = XVECLEN (body, 1); | |
8057 | ||
d1accaa3 JJ |
8058 | #ifdef ASM_OUTPUT_ADDR_VEC_START |
8059 | ASM_OUTPUT_ADDR_VEC_START (asm_out_file); | |
8060 | #endif | |
8061 | ||
e0d80184 DM |
8062 | #ifdef ASM_OUTPUT_CASE_LABEL |
8063 | ASM_OUTPUT_CASE_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab), | |
8064 | NEXT_INSN (lab)); | |
8065 | #else | |
8066 | ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab)); | |
8067 | #endif | |
8068 | ||
8069 | for (idx = 0; idx < vlen; idx++) | |
8070 | { | |
8071 | ASM_OUTPUT_ADDR_DIFF_ELT | |
8072 | (asm_out_file, | |
8073 | body, | |
8074 | CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 1, idx), 0)), | |
8075 | CODE_LABEL_NUMBER (base)); | |
8076 | } | |
d1accaa3 JJ |
8077 | |
8078 | #ifdef ASM_OUTPUT_ADDR_VEC_END | |
8079 | ASM_OUTPUT_ADDR_VEC_END (asm_out_file); | |
8080 | #endif | |
e0d80184 DM |
8081 | } |
8082 | ||
8083 | static void | |
8084 | sparc_output_deferred_case_vectors () | |
8085 | { | |
8086 | rtx t; | |
d676da68 | 8087 | int align; |
e0d80184 | 8088 | |
f3b8847b DM |
8089 | if (sparc_addr_list == NULL_RTX |
8090 | && sparc_addr_diff_list == NULL_RTX) | |
8091 | return; | |
8092 | ||
e0d80184 DM |
8093 | /* Align to cache line in the function's code section. */ |
8094 | function_section (current_function_decl); | |
d676da68 DM |
8095 | |
8096 | align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT); | |
8097 | if (align > 0) | |
f3b8847b | 8098 | ASM_OUTPUT_ALIGN (asm_out_file, align); |
e0d80184 DM |
8099 | |
8100 | for (t = sparc_addr_list; t ; t = XEXP (t, 1)) | |
8101 | sparc_output_addr_vec (XEXP (t, 0)); | |
8102 | for (t = sparc_addr_diff_list; t ; t = XEXP (t, 1)) | |
8103 | sparc_output_addr_diff_vec (XEXP (t, 0)); | |
8104 | ||
8105 | sparc_addr_list = sparc_addr_diff_list = NULL_RTX; | |
8106 | } | |
8107 | ||
284d86e9 JC |
8108 | /* Return 0 if the high 32 bits of X (the low word of X, if DImode) are |
8109 | unknown. Return 1 if the high bits are zero, -1 if the register is | |
8110 | sign extended. */ | |
8111 | int | |
8112 | sparc_check_64 (x, insn) | |
8113 | rtx x, insn; | |
8114 | { | |
8115 | /* If a register is set only once it is safe to ignore insns this | |
8116 | code does not know how to handle. The loop will either recognize | |
8117 | the single set and return the correct value or fail to recognize | |
8118 | it and return 0. */ | |
8119 | int set_once = 0; | |
8120 | ||
8121 | if (GET_CODE (x) == REG | |
8122 | && flag_expensive_optimizations | |
8123 | && REG_N_SETS (REGNO (x)) == 1) | |
8124 | set_once = 1; | |
8125 | ||
8126 | if (insn == 0) | |
d6f4ec51 KG |
8127 | { |
8128 | if (set_once) | |
8129 | insn = get_last_insn_anywhere (); | |
8130 | else | |
8131 | return 0; | |
8132 | } | |
284d86e9 | 8133 | |
d6f4ec51 | 8134 | while ((insn = PREV_INSN (insn))) |
284d86e9 JC |
8135 | { |
8136 | switch (GET_CODE (insn)) | |
8137 | { | |
8138 | case JUMP_INSN: | |
8139 | case NOTE: | |
8140 | break; | |
8141 | case CODE_LABEL: | |
8142 | case CALL_INSN: | |
8143 | default: | |
8144 | if (! set_once) | |
8145 | return 0; | |
8146 | break; | |
8147 | case INSN: | |
8148 | { | |
8149 | rtx pat = PATTERN (insn); | |
8150 | if (GET_CODE (pat) != SET) | |
8151 | return 0; | |
8152 | if (rtx_equal_p (x, SET_DEST (pat))) | |
8153 | return set_extends (x, insn); | |
8154 | if (reg_overlap_mentioned_p (SET_DEST (pat), x)) | |
8155 | return 0; | |
8156 | } | |
8157 | } | |
8158 | } | |
8159 | return 0; | |
8160 | } | |
8161 | ||
8162 | char * | |
8163 | sparc_v8plus_shift (operands, insn, opcode) | |
8164 | rtx *operands; | |
8165 | rtx insn; | |
b1474bb7 | 8166 | const char *opcode; |
284d86e9 JC |
8167 | { |
8168 | static char asm_code[60]; | |
8169 | ||
8170 | if (GET_CODE (operands[3]) == SCRATCH) | |
8171 | operands[3] = operands[0]; | |
c6b0465b JC |
8172 | if (GET_CODE (operands[1]) == CONST_INT) |
8173 | { | |
8174 | output_asm_insn ("mov %1,%3", operands); | |
8175 | } | |
8176 | else | |
8177 | { | |
8178 | output_asm_insn ("sllx %H1,32,%3", operands); | |
8179 | if (sparc_check_64 (operands[1], insn) <= 0) | |
8180 | output_asm_insn ("srl %L1,0,%L1", operands); | |
8181 | output_asm_insn ("or %L1,%3,%3", operands); | |
8182 | } | |
284d86e9 JC |
8183 | |
8184 | strcpy(asm_code, opcode); | |
8185 | if (which_alternative != 2) | |
8186 | return strcat (asm_code, " %0,%2,%L0\n\tsrlx %L0,32,%H0"); | |
8187 | else | |
8188 | return strcat (asm_code, " %3,%2,%3\n\tsrlx %3,32,%H0\n\tmov %3,%L0"); | |
8189 | } | |
8190 | ||
8191 | ||
8192 | /* Return 1 if DEST and SRC reference only global and in registers. */ | |
8193 | ||
8194 | int | |
8195 | sparc_return_peephole_ok (dest, src) | |
8196 | rtx dest, src; | |
8197 | { | |
8198 | if (! TARGET_V9) | |
8199 | return 0; | |
54ff41b7 | 8200 | if (current_function_uses_only_leaf_regs) |
284d86e9 JC |
8201 | return 0; |
8202 | if (GET_CODE (src) != CONST_INT | |
8203 | && (GET_CODE (src) != REG || ! IN_OR_GLOBAL_P (src))) | |
8204 | return 0; | |
8205 | return IN_OR_GLOBAL_P (dest); | |
8206 | } | |
2be15d0f RH |
8207 | \f |
8208 | /* Output assembler code to FILE to increment profiler label # LABELNO | |
8209 | for profiling a function entry. | |
8210 | ||
8211 | 32 bit sparc uses %g2 as the STATIC_CHAIN_REGNUM which gets clobbered | |
8212 | during profiling so we need to save/restore it around the call to mcount. | |
8213 | We're guaranteed that a save has just been done, and we use the space | |
8214 | allocated for intreg/fpreg value passing. */ | |
8215 | ||
8216 | void | |
8217 | sparc_function_profiler (file, labelno) | |
8218 | FILE *file; | |
8219 | int labelno; | |
8220 | { | |
8221 | char buf[32]; | |
8222 | ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno); | |
8223 | ||
8224 | if (! TARGET_ARCH64) | |
8225 | fputs ("\tst\t%g2,[%fp-4]\n", file); | |
8226 | ||
8227 | fputs ("\tsethi\t%hi(", file); | |
8228 | assemble_name (file, buf); | |
8229 | fputs ("),%o0\n", file); | |
8230 | ||
8231 | fputs ("\tcall\t", file); | |
8232 | assemble_name (file, MCOUNT_FUNCTION); | |
8233 | putc ('\n', file); | |
8234 | ||
8235 | fputs ("\t or\t%o0,%lo(", file); | |
8236 | assemble_name (file, buf); | |
8237 | fputs ("),%o0\n", file); | |
8238 | ||
8239 | if (! TARGET_ARCH64) | |
8240 | fputs ("\tld\t[%fp-4],%g2\n", file); | |
8241 | } | |
8242 | ||
8243 | ||
8244 | /* The following macro shall output assembler code to FILE | |
8245 | to initialize basic-block profiling. | |
8246 | ||
8247 | If profile_block_flag == 2 | |
8248 | ||
8249 | Output code to call the subroutine `__bb_init_trace_func' | |
8250 | and pass two parameters to it. The first parameter is | |
8251 | the address of a block allocated in the object module. | |
8252 | The second parameter is the number of the first basic block | |
8253 | of the function. | |
8254 | ||
8255 | The name of the block is a local symbol made with this statement: | |
8256 | ||
8257 | ASM_GENERATE_INTERNAL_LABEL (BUFFER, "LPBX", 0); | |
8258 | ||
8259 | Of course, since you are writing the definition of | |
8260 | `ASM_GENERATE_INTERNAL_LABEL' as well as that of this macro, you | |
8261 | can take a short cut in the definition of this macro and use the | |
8262 | name that you know will result. | |
8263 | ||
8264 | The number of the first basic block of the function is | |
8265 | passed to the macro in BLOCK_OR_LABEL. | |
8266 | ||
8267 | If described in a virtual assembler language the code to be | |
8268 | output looks like: | |
8269 | ||
8270 | parameter1 <- LPBX0 | |
8271 | parameter2 <- BLOCK_OR_LABEL | |
8272 | call __bb_init_trace_func | |
8273 | ||
8274 | else if profile_block_flag != 0 | |
8275 | ||
8276 | Output code to call the subroutine `__bb_init_func' | |
8277 | and pass one single parameter to it, which is the same | |
8278 | as the first parameter to `__bb_init_trace_func'. | |
8279 | ||
8280 | The first word of this parameter is a flag which will be nonzero if | |
8281 | the object module has already been initialized. So test this word | |
8282 | first, and do not call `__bb_init_func' if the flag is nonzero. | |
8283 | Note: When profile_block_flag == 2 the test need not be done | |
8284 | but `__bb_init_trace_func' *must* be called. | |
8285 | ||
8286 | BLOCK_OR_LABEL may be used to generate a label number as a | |
8287 | branch destination in case `__bb_init_func' will not be called. | |
8288 | ||
8289 | If described in a virtual assembler language the code to be | |
8290 | output looks like: | |
8291 | ||
8292 | cmp (LPBX0),0 | |
8293 | jne local_label | |
8294 | parameter1 <- LPBX0 | |
8295 | call __bb_init_func | |
8296 | local_label: | |
8297 | ||
8298 | */ | |
8299 | ||
8300 | void | |
8301 | sparc_function_block_profiler(file, block_or_label) | |
8302 | FILE *file; | |
8303 | int block_or_label; | |
8304 | { | |
8305 | char LPBX[32]; | |
8306 | ASM_GENERATE_INTERNAL_LABEL (LPBX, "LPBX", 0); | |
8307 | ||
8308 | if (profile_block_flag == 2) | |
8309 | { | |
8310 | fputs ("\tsethi\t%hi(", file); | |
8311 | assemble_name (file, LPBX); | |
8312 | fputs ("),%o0\n", file); | |
8313 | ||
8314 | fprintf (file, "\tsethi\t%%hi(%d),%%o1\n", block_or_label); | |
8315 | ||
8316 | fputs ("\tor\t%o0,%lo(", file); | |
8317 | assemble_name (file, LPBX); | |
8318 | fputs ("),%o0\n", file); | |
8319 | ||
8320 | fprintf (file, "\tcall\t%s__bb_init_trace_func\n", user_label_prefix); | |
8321 | ||
8322 | fprintf (file, "\t or\t%%o1,%%lo(%d),%%o1\n", block_or_label); | |
8323 | } | |
8324 | else if (profile_block_flag != 0) | |
8325 | { | |
8326 | char LPBY[32]; | |
8327 | ASM_GENERATE_INTERNAL_LABEL (LPBY, "LPBY", block_or_label); | |
8328 | ||
8329 | fputs ("\tsethi\t%hi(", file); | |
8330 | assemble_name (file, LPBX); | |
8331 | fputs ("),%o0\n", file); | |
8332 | ||
8333 | fputs ("\tld\t[%lo(", file); | |
8334 | assemble_name (file, LPBX); | |
8335 | fputs (")+%o0],%o1\n", file); | |
8336 | ||
8337 | fputs ("\ttst\t%o1\n", file); | |
8338 | ||
8339 | if (TARGET_V9) | |
8340 | { | |
8341 | fputs ("\tbne,pn\t%icc,", file); | |
8342 | assemble_name (file, LPBY); | |
8343 | putc ('\n', file); | |
8344 | } | |
8345 | else | |
8346 | { | |
8347 | fputs ("\tbne\t", file); | |
8348 | assemble_name (file, LPBY); | |
8349 | putc ('\n', file); | |
8350 | } | |
8351 | ||
8352 | fputs ("\t or\t%o0,%lo(", file); | |
8353 | assemble_name (file, LPBX); | |
8354 | fputs ("),%o0\n", file); | |
8355 | ||
8356 | fprintf (file, "\tcall\t%s__bb_init_func\n\t nop\n", user_label_prefix); | |
8357 | ||
8358 | ASM_OUTPUT_INTERNAL_LABEL (file, "LPBY", block_or_label); | |
8359 | } | |
8360 | } | |
8361 | ||
8362 | /* The following macro shall output assembler code to FILE | |
8363 | to increment a counter associated with basic block number BLOCKNO. | |
8364 | ||
8365 | If profile_block_flag == 2 | |
8366 | ||
8367 | Output code to initialize the global structure `__bb' and | |
8368 | call the function `__bb_trace_func' which will increment the | |
8369 | counter. | |
8370 | ||
8371 | `__bb' consists of two words. In the first word the number | |
8372 | of the basic block has to be stored. In the second word | |
8373 | the address of a block allocated in the object module | |
8374 | has to be stored. | |
8375 | ||
8376 | The basic block number is given by BLOCKNO. | |
8377 | ||
8378 | The address of the block is given by the label created with | |
8379 | ||
8380 | ASM_GENERATE_INTERNAL_LABEL (BUFFER, "LPBX", 0); | |
8381 | ||
8382 | by FUNCTION_BLOCK_PROFILER. | |
8383 | ||
8384 | Of course, since you are writing the definition of | |
8385 | `ASM_GENERATE_INTERNAL_LABEL' as well as that of this macro, you | |
8386 | can take a short cut in the definition of this macro and use the | |
8387 | name that you know will result. | |
8388 | ||
8389 | If described in a virtual assembler language the code to be | |
8390 | output looks like: | |
8391 | ||
8392 | move BLOCKNO -> (__bb) | |
8393 | move LPBX0 -> (__bb+4) | |
8394 | call __bb_trace_func | |
8395 | ||
8396 | Note that function `__bb_trace_func' must not change the | |
8397 | machine state, especially the flag register. To grant | |
8398 | this, you must output code to save and restore registers | |
8399 | either in this macro or in the macros MACHINE_STATE_SAVE | |
8400 | and MACHINE_STATE_RESTORE. The last two macros will be | |
8401 | used in the function `__bb_trace_func', so you must make | |
8402 | sure that the function prologue does not change any | |
8403 | register prior to saving it with MACHINE_STATE_SAVE. | |
8404 | ||
8405 | else if profile_block_flag != 0 | |
8406 | ||
8407 | Output code to increment the counter directly. | |
8408 | Basic blocks are numbered separately from zero within each | |
8409 | compiled object module. The count associated with block number | |
8410 | BLOCKNO is at index BLOCKNO in an array of words; the name of | |
8411 | this array is a local symbol made with this statement: | |
8412 | ||
8413 | ASM_GENERATE_INTERNAL_LABEL (BUFFER, "LPBX", 2); | |
8414 | ||
8415 | Of course, since you are writing the definition of | |
8416 | `ASM_GENERATE_INTERNAL_LABEL' as well as that of this macro, you | |
8417 | can take a short cut in the definition of this macro and use the | |
8418 | name that you know will result. | |
8419 | ||
8420 | If described in a virtual assembler language, the code to be | |
8421 | output looks like: | |
8422 | ||
8423 | inc (LPBX2+4*BLOCKNO) | |
8424 | ||
8425 | */ | |
8426 | ||
8427 | void | |
8428 | sparc_block_profiler(file, blockno) | |
8429 | FILE *file; | |
8430 | int blockno; | |
8431 | { | |
8432 | char LPBX[32]; | |
a330e73b | 8433 | int bbreg = TARGET_ARCH64 ? 4 : 2; |
2be15d0f RH |
8434 | |
8435 | if (profile_block_flag == 2) | |
8436 | { | |
8437 | ASM_GENERATE_INTERNAL_LABEL (LPBX, "LPBX", 0); | |
8438 | ||
8439 | fprintf (file, "\tsethi\t%%hi(%s__bb),%%g1\n", user_label_prefix); | |
a330e73b | 8440 | fprintf (file, "\tsethi\t%%hi(%d),%%g%d\n", blockno, bbreg); |
2be15d0f | 8441 | fprintf (file, "\tor\t%%g1,%%lo(%s__bb),%%g1\n", user_label_prefix); |
a330e73b | 8442 | fprintf (file, "\tor\t%%g%d,%%lo(%d),%%g%d\n", bbreg, blockno, bbreg); |
2be15d0f | 8443 | |
a330e73b | 8444 | fprintf (file, "\tst\t%%g%d,[%%g1]\n", bbreg); |
2be15d0f RH |
8445 | |
8446 | fputs ("\tsethi\t%hi(", file); | |
8447 | assemble_name (file, LPBX); | |
a330e73b | 8448 | fprintf (file, "),%%g%d\n", bbreg); |
2be15d0f | 8449 | |
110b0302 | 8450 | fputs ("\tor\t%o2,%lo(", file); |
2be15d0f | 8451 | assemble_name (file, LPBX); |
a330e73b | 8452 | fprintf (file, "),%%g%d\n", bbreg); |
2be15d0f | 8453 | |
a330e73b JJ |
8454 | fprintf (file, "\tst\t%%g%d,[%%g1+4]\n", bbreg); |
8455 | fprintf (file, "\tmov\t%%o7,%%g%d\n", bbreg); | |
2be15d0f RH |
8456 | |
8457 | fprintf (file, "\tcall\t%s__bb_trace_func\n\t nop\n", user_label_prefix); | |
8458 | ||
a330e73b | 8459 | fprintf (file, "\tmov\t%%g%d,%%o7\n", bbreg); |
2be15d0f RH |
8460 | } |
8461 | else if (profile_block_flag != 0) | |
8462 | { | |
8463 | ASM_GENERATE_INTERNAL_LABEL (LPBX, "LPBX", 2); | |
8464 | ||
8465 | fputs ("\tsethi\t%hi(", file); | |
8466 | assemble_name (file, LPBX); | |
8467 | fprintf (file, "+%d),%%g1\n", blockno*4); | |
8468 | ||
8469 | fputs ("\tld\t[%g1+%lo(", file); | |
8470 | assemble_name (file, LPBX); | |
a330e73b JJ |
8471 | if (TARGET_ARCH64 && USE_AS_OFFSETABLE_LO10) |
8472 | fprintf (file, ")+%d],%%g%d\n", blockno*4, bbreg); | |
8473 | else | |
8474 | fprintf (file, "+%d)],%%g%d\n", blockno*4, bbreg); | |
2be15d0f | 8475 | |
a330e73b | 8476 | fprintf (file, "\tadd\t%%g%d,1,%%g%d\n", bbreg, bbreg); |
2be15d0f | 8477 | |
a330e73b | 8478 | fprintf (file, "\tst\t%%g%d,[%%g1+%%lo(", bbreg); |
2be15d0f | 8479 | assemble_name (file, LPBX); |
a330e73b JJ |
8480 | if (TARGET_ARCH64 && USE_AS_OFFSETABLE_LO10) |
8481 | fprintf (file, ")+%d]\n", blockno*4); | |
8482 | else | |
8483 | fprintf (file, "+%d)]\n", blockno*4); | |
2be15d0f RH |
8484 | } |
8485 | } | |
8486 | ||
8487 | /* The following macro shall output assembler code to FILE | |
8488 | to indicate a return from function during basic-block profiling. | |
8489 | ||
8490 | If profile_block_flag == 2: | |
8491 | ||
8492 | Output assembler code to call function `__bb_trace_ret'. | |
8493 | ||
8494 | Note that function `__bb_trace_ret' must not change the | |
8495 | machine state, especially the flag register. To grant | |
8496 | this, you must output code to save and restore registers | |
8497 | either in this macro or in the macros MACHINE_STATE_SAVE_RET | |
8498 | and MACHINE_STATE_RESTORE_RET. The last two macros will be | |
8499 | used in the function `__bb_trace_ret', so you must make | |
8500 | sure that the function prologue does not change any | |
8501 | register prior to saving it with MACHINE_STATE_SAVE_RET. | |
8502 | ||
8503 | else if profile_block_flag != 0: | |
8504 | ||
8505 | The macro will not be used, so it need not distinguish | |
8506 | these cases. | |
8507 | */ | |
8508 | ||
8509 | void | |
8510 | sparc_function_block_profiler_exit(file) | |
8511 | FILE *file; | |
8512 | { | |
8513 | if (profile_block_flag == 2) | |
8514 | fprintf (file, "\tcall\t%s__bb_trace_ret\n\t nop\n", user_label_prefix); | |
8515 | else | |
8516 | abort (); | |
8517 | } | |
d07d525a MM |
8518 | |
8519 | /* Mark ARG, which is really a struct ultrasparc_pipline_state *, for | |
8520 | GC. */ | |
8521 | ||
8522 | static void | |
8523 | mark_ultrasparc_pipeline_state (arg) | |
8524 | void *arg; | |
8525 | { | |
8526 | struct ultrasparc_pipeline_state *ups; | |
8527 | size_t i; | |
8528 | ||
8529 | ups = (struct ultrasparc_pipeline_state *) arg; | |
8530 | for (i = 0; i < sizeof (ups->group) / sizeof (rtx); ++i) | |
8531 | ggc_mark_rtx (ups->group[i]); | |
8532 | } | |
8533 | ||
8534 | /* Called to register all of our global variables with the garbage | |
8535 | collector. */ | |
8536 | ||
8537 | static void | |
8538 | sparc_add_gc_roots () | |
8539 | { | |
8540 | ggc_add_rtx_root (&sparc_compare_op0, 1); | |
8541 | ggc_add_rtx_root (&sparc_compare_op1, 1); | |
8542 | ggc_add_rtx_root (&leaf_label, 1); | |
8543 | ggc_add_rtx_root (&global_offset_table, 1); | |
8544 | ggc_add_rtx_root (&get_pc_symbol, 1); | |
8545 | ggc_add_rtx_root (&sparc_addr_diff_list, 1); | |
8546 | ggc_add_rtx_root (&sparc_addr_list, 1); | |
8547 | ggc_add_root (ultra_pipe_hist, | |
8548 | sizeof (ultra_pipe_hist) / sizeof (ultra_pipe_hist[0]), | |
8549 | sizeof (ultra_pipe_hist[0]), | |
8550 | &mark_ultrasparc_pipeline_state); | |
8551 | } |