]> gcc.gnu.org Git - gcc.git/blame - gcc/config/sparc/sparc.c
git://gcc.gnu.org / gcc.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
decl2.c (import_export_vtable): Always make artificials comdat.
[gcc.git] / gcc / config / sparc / sparc.c
CommitLineData
ab835497 1/* Subroutines for insn-output.c for Sun SPARC.
27d8f9ea 2 Copyright (C) 1987, 88, 89, 92-97, 1998 Free Software Foundation, Inc.
ab835497 3 Contributed by Michael Tiemann (tiemann@cygnus.com)
61a55e8b
DE		 4 64 bit SPARC V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
5 at Cygnus Support.
ab835497
RK		 6
7This file is part of GNU CC.
8
9GNU CC is free software; you can redistribute it and/or modify
10it under the terms of the GNU General Public License as published by
11the Free Software Foundation; either version 2, or (at your option)
12any later version.
13
14GNU CC is distributed in the hope that it will be useful,
15but WITHOUT ANY WARRANTY; without even the implied warranty of
16MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17GNU General Public License for more details.
18
19You should have received a copy of the GNU General Public License
20along with GNU CC; see the file COPYING. If not, write to
c15c9075
RK		 21the Free Software Foundation, 59 Temple Place - Suite 330,
22Boston, MA 02111-1307, USA. */
ab835497 23
ab835497 24#include "config.h"
284d86e9 25#include "system.h"
210aa14a 26#include "tree.h"
ab835497
RK		 27#include "rtl.h"
28#include "regs.h"
29#include "hard-reg-set.h"
30#include "real.h"
31#include "insn-config.h"
32#include "conditions.h"
33#include "insn-flags.h"
34#include "output.h"
35#include "insn-attr.h"
36#include "flags.h"
37#include "expr.h"
38#include "recog.h"
487a6e06 39#include "toplev.h"
ab835497 40
61a55e8b
DE		 41/* 1 if the caller has placed an "unimp" insn immediately after the call.
42 This is used in v8 code when calling a function that returns a structure.
06b967f9
RK		 43 v9 doesn't have this. Be careful to have this test be the same as that
44 used on the call. */
45
46#define SKIP_CALLERS_UNIMP_P \
47(!TARGET_ARCH64 && current_function_returns_struct \
48 && ! integer_zerop (DECL_SIZE (DECL_RESULT (current_function_decl))) \
49 && (TREE_CODE (DECL_SIZE (DECL_RESULT (current_function_decl))) \
50 == INTEGER_CST))
61a55e8b 51
ab835497
RK		 52/* Global variables for machine-dependent things. */
53
61a55e8b
DE		 54/* Size of frame. Need to know this to emit return insns from leaf procedures.
55 ACTUAL_FSIZE is set by compute_frame_size() which is called during the
56 reload pass. This is important as the value is later used in insn
57 scheduling (to see what can go in a delay slot).
58 APPARENT_FSIZE is the size of the stack less the register save area and less
59 the outgoing argument area. It is used when saving call preserved regs. */
60static int apparent_fsize;
61static int actual_fsize;
62
ab835497
RK		 63/* Save the operands last given to a compare for use when we
64 generate a scc or bcc insn. */
65
66rtx sparc_compare_op0, sparc_compare_op1;
67
68/* We may need an epilogue if we spill too many registers.
69 If this is non-zero, then we branch here for the epilogue. */
70static rtx leaf_label;
71
72#ifdef LEAF_REGISTERS
73
74/* Vector to say how input registers are mapped to output
75 registers. FRAME_POINTER_REGNUM cannot be remapped by
76 this function to eliminate it. You must use -fomit-frame-pointer
77 to get that. */
78char leaf_reg_remap[] =
79{ 0, 1, 2, 3, 4, 5, 6, 7,
80 -1, -1, -1, -1, -1, -1, 14, -1,
81 -1, -1, -1, -1, -1, -1, -1, -1,
82 8, 9, 10, 11, 12, 13, -1, 15,
83
84 32, 33, 34, 35, 36, 37, 38, 39,
85 40, 41, 42, 43, 44, 45, 46, 47,
86 48, 49, 50, 51, 52, 53, 54, 55,
61a55e8b
DE		 87 56, 57, 58, 59, 60, 61, 62, 63,
88 64, 65, 66, 67, 68, 69, 70, 71,
89 72, 73, 74, 75, 76, 77, 78, 79,
90 80, 81, 82, 83, 84, 85, 86, 87,
91 88, 89, 90, 91, 92, 93, 94, 95,
c4ce6853 92 96, 97, 98, 99, 100};
ab835497 93
6a4bb1fa 94#endif
ab835497 95
ab835497
RK		 96/* Name of where we pretend to think the frame pointer points.
97 Normally, this is "%fp", but if we are in a leaf procedure,
61a55e8b
DE		 98 this is "%sp+something". We record "something" separately as it may be
99 too big for reg+constant addressing. */
100
101static char *frame_base_name;
102static int frame_base_offset;
ab835497 103
c85f7c16 104static rtx pic_setup_code PROTO((void));
c85f7c16
JL		 105static void sparc_init_modes PROTO((void));
106static int save_regs PROTO((FILE *, int, int, char *,
107 int, int, int));
108static int restore_regs PROTO((FILE *, int, int, char *, int, int));
109static void build_big_number PROTO((FILE *, int, char *));
5e9defae 110static int function_arg_slotno PROTO((const CUMULATIVE_ARGS *,
c85f7c16
JL		 111 enum machine_mode, tree, int, int,
112 int *, int *));
e0d80184
DM		 113static void sparc_output_addr_vec PROTO((rtx));
114static void sparc_output_addr_diff_vec PROTO((rtx));
115static void sparc_output_deferred_case_vectors PROTO((void));
e9a25f70 116
2a01c939 117
e9a25f70
JL		 118#ifdef DWARF2_DEBUGGING_INFO
119extern char *dwarf2out_cfi_label ();
120#endif
61a55e8b
DE		 121\f
122/* Option handling. */
123
a0a301fc
DE		 124/* Code model option as passed by user. */
125char *sparc_cmodel_string;
126/* Parsed value. */
127enum cmodel sparc_cmodel;
128
129/* Record alignment options as passed by user. */
bf62bbf1
DE		 130char *sparc_align_loops_string;
131char *sparc_align_jumps_string;
132char *sparc_align_funcs_string;
133
134/* Parsed values, as a power of two. */
135int sparc_align_loops;
136int sparc_align_jumps;
137int sparc_align_funcs;
138
16956f6e
DE		 139struct sparc_cpu_select sparc_select[] =
140{
141 /* switch name, tune arch */
142 { (char *)0, "default", 1, 1 },
143 { (char *)0, "-mcpu=", 1, 1 },
144 { (char *)0, "-mtune=", 1, 0 },
db3d4438 145 { 0, 0, 0, 0 }
16956f6e 146};
733f53f5 147
16956f6e
DE		 148/* CPU type. This is set from TARGET_CPU_DEFAULT and -m{cpu,tune}=xxx. */
149enum processor_type sparc_cpu;
733f53f5 150
61a55e8b
DE		 151/* Validate and override various options, and do some machine dependent
152 initialization. */
153
154void
155sparc_override_options ()
156{
a0a301fc
DE		 157 static struct code_model {
158 char *name;
159 int value;
160 } cmodels[] = {
161 { "32", CM_32 },
162 { "medlow", CM_MEDLOW },
163 { "medmid", CM_MEDMID },
164 { "medany", CM_MEDANY },
165 { "embmedany", CM_EMBMEDANY },
166 { 0, 0 }
167 };
168 struct code_model *cmodel;
16956f6e 169 /* Map TARGET_CPU_DEFAULT to value for -m{arch,tune}=. */
733f53f5
DE		 170 static struct cpu_default {
171 int cpu;
172 char *name;
173 } cpu_default[] = {
a0a301fc 174 /* There must be one entry here for each TARGET_CPU value. */
16956f6e 175 { TARGET_CPU_sparc, "cypress" },
3592ea0d 176 { TARGET_CPU_sparclet, "tsc701" },
16956f6e 177 { TARGET_CPU_sparclite, "f930" },
a0a301fc
DE		 178 { TARGET_CPU_v8, "v8" },
179 { TARGET_CPU_supersparc, "supersparc" },
180 { TARGET_CPU_v9, "v9" },
ba542005 181 { TARGET_CPU_ultrasparc, "ultrasparc" },
db3d4438 182 { 0, 0 }
733f53f5 183 };
16956f6e
DE		 184 struct cpu_default *def;
185 /* Table of values for -m{cpu,tune}=. */
733f53f5
DE		 186 static struct cpu_table {
187 char *name;
16956f6e 188 enum processor_type processor;
733f53f5
DE		 189 int disable;
190 int enable;
191 } cpu_table[] = {
16956f6e
DE		 192 { "v7", PROCESSOR_V7, MASK_ISA, 0 },
193 { "cypress", PROCESSOR_CYPRESS, MASK_ISA, 0 },
194 { "v8", PROCESSOR_V8, MASK_ISA, MASK_V8 },
733f53f5 195 /* TI TMS390Z55 supersparc */
16956f6e
DE		 196 { "supersparc", PROCESSOR_SUPERSPARC, MASK_ISA, MASK_V8 },
197 { "sparclite", PROCESSOR_SPARCLITE, MASK_ISA, MASK_SPARCLITE },
733f53f5
DE		 198 /* The Fujitsu MB86930 is the original sparclite chip, with no fpu.
199 The Fujitsu MB86934 is the recent sparclite chip, with an fpu. */
16956f6e
DE		 200 { "f930", PROCESSOR_F930, MASK_ISA|MASK_FPU, MASK_SPARCLITE },
201 { "f934", PROCESSOR_F934, MASK_ISA, MASK_SPARCLITE|MASK_FPU },
202 { "sparclet", PROCESSOR_SPARCLET, MASK_ISA, MASK_SPARCLET },
733f53f5 203 /* TEMIC sparclet */
3592ea0d 204 { "tsc701", PROCESSOR_TSC701, MASK_ISA, MASK_SPARCLET },
16956f6e 205 { "v9", PROCESSOR_V9, MASK_ISA, MASK_V9 },
733f53f5 206 /* TI ultrasparc */
284d86e9 207 { "ultrasparc", PROCESSOR_ULTRASPARC, MASK_ISA, MASK_V9 },
db3d4438 208 { 0, 0, 0, 0 }
733f53f5 209 };
16956f6e
DE		 210 struct cpu_table *cpu;
211 struct sparc_cpu_select *sel;
a0a301fc
DE		 212 int fpu;
213
214#ifndef SPARC_BI_ARCH
215 /* Check for unsupported architecture size. */
216 if (! TARGET_64BIT != DEFAULT_ARCH32_P)
217 {
218 error ("%s is not supported by this configuration",
219 DEFAULT_ARCH32_P ? "-m64" : "-m32");
220 }
221#endif
222
223 /* Code model selection. */
224 sparc_cmodel = SPARC_DEFAULT_CMODEL;
225 if (sparc_cmodel_string != NULL)
226 {
227 if (TARGET_ARCH64)
228 {
229 for (cmodel = &cmodels[0]; cmodel->name; cmodel++)
230 if (strcmp (sparc_cmodel_string, cmodel->name) == 0)
231 break;
232 if (cmodel->name == NULL)
233 error ("bad value (%s) for -mcmodel= switch", sparc_cmodel_string);
234 else
235 sparc_cmodel = cmodel->value;
236 }
237 else
238 error ("-mcmodel= is not supported on 32 bit systems");
239 }
16956f6e 240
a0a301fc 241 fpu = TARGET_FPU; /* save current -mfpu status */
1f1406b4 242
a0a301fc 243 /* Set the default CPU. */
16956f6e
DE		 244 for (def = &cpu_default[0]; def->name; ++def)
245 if (def->cpu == TARGET_CPU_DEFAULT)
246 break;
247 if (! def->name)
248 abort ();
249 sparc_select[0].string = def->name;
250
251 for (sel = &sparc_select[0]; sel->name; ++sel)
61a55e8b 252 {
16956f6e 253 if (sel->string)
733f53f5 254 {
16956f6e
DE		 255 for (cpu = &cpu_table[0]; cpu->name; ++cpu)
256 if (! strcmp (sel->string, cpu->name))
257 {
258 if (sel->set_tune_p)
259 sparc_cpu = cpu->processor;
260
261 if (sel->set_arch_p)
262 {
263 target_flags &= ~cpu->disable;
264 target_flags |= cpu->enable;
265 }
266 break;
267 }
268
269 if (! cpu->name)
270 error ("bad value (%s) for %s switch", sel->string, sel->name);
733f53f5 271 }
61a55e8b 272 }
97da85b7 273
1f1406b4
DE		 274 /* If -mfpu or -mno-fpu was explicitly used, don't override with
275 the processor default. */
276 if (TARGET_FPU_SET)
277 target_flags = (target_flags & ~MASK_FPU) | fpu;
278
16956f6e
DE		 279 /* Use the deprecated v8 insns for sparc64 in 32 bit mode. */
280 if (TARGET_V9 && TARGET_ARCH32)
733f53f5 281 target_flags |= MASK_DEPRECATED_V8_INSNS;
61a55e8b 282
284d86e9
JC		 283 /* V8PLUS requires V9 */
284 if (! TARGET_V9)
285 target_flags &= ~MASK_V8PLUS;
286
82d6b402
RH		 287 /* Don't use stack biasing in 32 bit mode. */
288 if (TARGET_ARCH32)
289 target_flags &= ~MASK_STACK_BIAS;
f952a238
JJ		 290
291 /* Don't allow -mvis if FPU is disabled. */
292 if (! TARGET_FPU)
293 target_flags &= ~MASK_VIS;
82d6b402 294
bf62bbf1
DE		 295 /* Validate -malign-loops= value, or provide default. */
296 if (sparc_align_loops_string)
297 {
298 sparc_align_loops = exact_log2 (atoi (sparc_align_loops_string));
299 if (sparc_align_loops < 2 || sparc_align_loops > 7)
300 fatal ("-malign-loops=%s is not between 4 and 128 or is not a power of two",
301 sparc_align_loops_string);
302 }
303 else
304 {
305 /* ??? This relies on ASM_OUTPUT_ALIGN to not emit the alignment if
306 its 0. This sounds a bit kludgey. */
307 sparc_align_loops = 0;
308 }
309
310 /* Validate -malign-jumps= value, or provide default. */
311 if (sparc_align_jumps_string)
312 {
313 sparc_align_jumps = exact_log2 (atoi (sparc_align_jumps_string));
314 if (sparc_align_jumps < 2 || sparc_align_loops > 7)
315 fatal ("-malign-jumps=%s is not between 4 and 128 or is not a power of two",
316 sparc_align_jumps_string);
317 }
318 else
319 {
320 /* ??? This relies on ASM_OUTPUT_ALIGN to not emit the alignment if
321 its 0. This sounds a bit kludgey. */
322 sparc_align_jumps = 0;
323 }
324
325 /* Validate -malign-functions= value, or provide default. */
326 if (sparc_align_funcs_string)
327 {
328 sparc_align_funcs = exact_log2 (atoi (sparc_align_funcs_string));
329 if (sparc_align_funcs < 2 || sparc_align_loops > 7)
330 fatal ("-malign-functions=%s is not between 4 and 128 or is not a power of two",
331 sparc_align_funcs_string);
332 }
333 else
334 sparc_align_funcs = DEFAULT_SPARC_ALIGN_FUNCS;
335
82d6b402
RH		 336 /* Validate PCC_STRUCT_RETURN. */
337 if (flag_pcc_struct_return == DEFAULT_PCC_STRUCT_RETURN)
338 flag_pcc_struct_return = (TARGET_ARCH64 ? 0 : 1);
339
61a55e8b
DE		 340 /* Do various machine dependent initializations. */
341 sparc_init_modes ();
342}
343\f
cd5fb1ee
DE		 344/* Miscellaneous utilities. */
345
346/* Nonzero if CODE, a comparison, is suitable for use in v9 conditional move
347 or branch on register contents instructions. */
348
349int
350v9_regcmp_p (code)
351 enum rtx_code code;
352{
353 return (code == EQ || code == NE || code == GE || code == LT
354 || code == LE || code == GT);
355}
bfd6bc60 356
cd5fb1ee
DE		 357\f
358/* Operand constraints. */
359
ab835497 360/* Return non-zero only if OP is a register of mode MODE,
c4ce6853
DE		 361 or const0_rtx. Don't allow const0_rtx if TARGET_LIVE_G0 because
362 %g0 may contain anything. */
363
ab835497
RK		 364int
365reg_or_0_operand (op, mode)
366 rtx op;
367 enum machine_mode mode;
368{
c4ce6853
DE		 369 if (register_operand (op, mode))
370 return 1;
371 if (TARGET_LIVE_G0)
372 return 0;
373 if (op == const0_rtx)
ab835497 374 return 1;
5b486ce0 375 if (GET_MODE (op) == VOIDmode && GET_CODE (op) == CONST_DOUBLE
ab835497
RK		 376 && CONST_DOUBLE_HIGH (op) == 0
377 && CONST_DOUBLE_LOW (op) == 0)
378 return 1;
302484ff
JW		 379 if (GET_MODE_CLASS (GET_MODE (op)) == MODE_FLOAT
380 && GET_CODE (op) == CONST_DOUBLE
381 && fp_zero_operand (op))
382 return 1;
ab835497
RK		 383 return 0;
384}
385
302484ff 386/* Nonzero if OP is a floating point value with value 0.0. */
c4ce6853 387
302484ff
JW		 388int
389fp_zero_operand (op)
390 rtx op;
391{
392 REAL_VALUE_TYPE r;
393
394 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
d61ba4f4 395 return (REAL_VALUES_EQUAL (r, dconst0) && ! REAL_VALUE_MINUS_ZERO (r));
302484ff
JW		 396}
397
61a55e8b
DE		 398/* Nonzero if OP is an integer register. */
399
400int
401intreg_operand (op, mode)
402 rtx op;
487a6e06 403 enum machine_mode mode ATTRIBUTE_UNUSED;
61a55e8b
DE		 404{
405 return (register_operand (op, SImode)
a9e27770 406 || (TARGET_ARCH64 && register_operand (op, DImode)));
61a55e8b
DE		 407}
408
409/* Nonzero if OP is a floating point condition code register. */
410
411int
c4ce6853 412fcc_reg_operand (op, mode)
61a55e8b
DE		 413 rtx op;
414 enum machine_mode mode;
415{
416 /* This can happen when recog is called from combine. Op may be a MEM.
417 Fail instead of calling abort in this case. */
c4ce6853 418 if (GET_CODE (op) != REG)
61a55e8b 419 return 0;
304b7a23 420
c4ce6853 421 if (mode != VOIDmode && mode != GET_MODE (op))
61a55e8b 422 return 0;
304b7a23
DE		 423 if (mode == VOIDmode
424 && (GET_MODE (op) != CCFPmode && GET_MODE (op) != CCFPEmode))
425 return 0;
61a55e8b 426
c4ce6853 427#if 0 /* ??? ==> 1 when %fcc0-3 are pseudos first. See gen_compare_reg(). */
61a55e8b
DE		 428 if (reg_renumber == 0)
429 return REGNO (op) >= FIRST_PSEUDO_REGISTER;
430 return REGNO_OK_FOR_CCFP_P (REGNO (op));
431#else
c4ce6853 432 return (unsigned) REGNO (op) - SPARC_FIRST_V9_FCC_REG < 4;
61a55e8b
DE		 433#endif
434}
435
c4ce6853
DE		 436/* Nonzero if OP is an integer or floating point condition code register. */
437
438int
439icc_or_fcc_reg_operand (op, mode)
440 rtx op;
441 enum machine_mode mode;
442{
443 if (GET_CODE (op) == REG && REGNO (op) == SPARC_ICC_REG)
304b7a23
DE		 444 {
445 if (mode != VOIDmode && mode != GET_MODE (op))
446 return 0;
447 if (mode == VOIDmode
448 && GET_MODE (op) != CCmode && GET_MODE (op) != CCXmode)
449 return 0;
450 return 1;
451 }
452
c4ce6853
DE		 453 return fcc_reg_operand (op, mode);
454}
455
ab835497
RK		 456/* Nonzero if OP can appear as the dest of a RESTORE insn. */
457int
458restore_operand (op, mode)
459 rtx op;
460 enum machine_mode mode;
461{
462 return (GET_CODE (op) == REG && GET_MODE (op) == mode
463 && (REGNO (op) < 8 || (REGNO (op) >= 24 && REGNO (op) < 32)));
464}
465
401cec23
JW		 466/* Call insn on SPARC can take a PC-relative constant address, or any regular
467 memory address. */
ab835497
RK		 468
469int
470call_operand (op, mode)
471 rtx op;
472 enum machine_mode mode;
473{
474 if (GET_CODE (op) != MEM)
475 abort ();
476 op = XEXP (op, 0);
2445f289 477 return (symbolic_operand (op, mode) || memory_address_p (Pmode, op));
ab835497
RK		 478}
479
480int
481call_operand_address (op, mode)
482 rtx op;
483 enum machine_mode mode;
484{
2445f289 485 return (symbolic_operand (op, mode) || memory_address_p (Pmode, op));
ab835497
RK		 486}
487
488/* Returns 1 if OP is either a symbol reference or a sum of a symbol
489 reference and a constant. */
490
491int
492symbolic_operand (op, mode)
493 register rtx op;
494 enum machine_mode mode;
495{
496 switch (GET_CODE (op))
497 {
498 case SYMBOL_REF:
499 case LABEL_REF:
500 return 1;
501
502 case CONST:
503 op = XEXP (op, 0);
504 return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
505 || GET_CODE (XEXP (op, 0)) == LABEL_REF)
506 && GET_CODE (XEXP (op, 1)) == CONST_INT);
507
228b4037 508 /* ??? This clause seems to be irrelevant. */
ab835497
RK		 509 case CONST_DOUBLE:
510 return GET_MODE (op) == mode;
511
512 default:
513 return 0;
514 }
515}
516
517/* Return truth value of statement that OP is a symbolic memory
518 operand of mode MODE. */
519
520int
521symbolic_memory_operand (op, mode)
522 rtx op;
487a6e06 523 enum machine_mode mode ATTRIBUTE_UNUSED;
ab835497
RK		 524{
525 if (GET_CODE (op) == SUBREG)
526 op = SUBREG_REG (op);
527 if (GET_CODE (op) != MEM)
528 return 0;
529 op = XEXP (op, 0);
530 return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST
531 || GET_CODE (op) == HIGH || GET_CODE (op) == LABEL_REF);
532}
533
5ab7138b
DE		 534/* Return truth value of statement that OP is a LABEL_REF of mode MODE. */
535
536int
537label_ref_operand (op, mode)
538 rtx op;
539 enum machine_mode mode;
540{
541 if (GET_CODE (op) != LABEL_REF)
542 return 0;
543 if (GET_MODE (op) != mode)
544 return 0;
545 return 1;
546}
547
95726648
DE		 548/* Return 1 if the operand is an argument used in generating pic references
549 in either the medium/low or medium/anywhere code models of sparc64. */
550
551int
552sp64_medium_pic_operand (op, mode)
553 rtx op;
487a6e06 554 enum machine_mode mode ATTRIBUTE_UNUSED;
95726648
DE		 555{
556 /* Check for (const (minus (symbol_ref:GOT)
557 (const (minus (label) (pc))))). */
558 if (GET_CODE (op) != CONST)
559 return 0;
560 op = XEXP (op, 0);
561 if (GET_CODE (op) != MINUS)
562 return 0;
563 if (GET_CODE (XEXP (op, 0)) != SYMBOL_REF)
564 return 0;
565 /* ??? Ensure symbol is GOT. */
566 if (GET_CODE (XEXP (op, 1)) != CONST)
567 return 0;
568 if (GET_CODE (XEXP (XEXP (op, 1), 0)) != MINUS)
569 return 0;
570 return 1;
571}
572
61a55e8b
DE		 573/* Return 1 if the operand is a data segment reference. This includes
574 the readonly data segment, or in other words anything but the text segment.
575 This is needed in the medium/anywhere code model on v9. These values
a0a301fc 576 are accessed with EMBMEDANY_BASE_REG. */
61a55e8b
DE		 577
578int
579data_segment_operand (op, mode)
580 rtx op;
487a6e06 581 enum machine_mode mode ATTRIBUTE_UNUSED;
61a55e8b
DE		 582{
583 switch (GET_CODE (op))
584 {
585 case SYMBOL_REF :
586 return ! SYMBOL_REF_FLAG (op);
587 case PLUS :
95726648
DE		 588 /* Assume canonical format of symbol + constant.
589 Fall through. */
61a55e8b
DE		 590 case CONST :
591 return data_segment_operand (XEXP (op, 0));
592 default :
593 return 0;
594 }
595}
596
597/* Return 1 if the operand is a text segment reference.
598 This is needed in the medium/anywhere code model on v9. */
599
600int
601text_segment_operand (op, mode)
602 rtx op;
487a6e06 603 enum machine_mode mode ATTRIBUTE_UNUSED;
61a55e8b
DE		 604{
605 switch (GET_CODE (op))
606 {
607 case LABEL_REF :
608 return 1;
609 case SYMBOL_REF :
610 return SYMBOL_REF_FLAG (op);
611 case PLUS :
95726648
DE		 612 /* Assume canonical format of symbol + constant.
613 Fall through. */
61a55e8b
DE		 614 case CONST :
615 return text_segment_operand (XEXP (op, 0));
616 default :
617 return 0;
618 }
619}
620
ab835497
RK		 621/* Return 1 if the operand is either a register or a memory operand that is
622 not symbolic. */
623
624int
625reg_or_nonsymb_mem_operand (op, mode)
626 register rtx op;
627 enum machine_mode mode;
628{
629 if (register_operand (op, mode))
630 return 1;
631
632 if (memory_operand (op, mode) && ! symbolic_memory_operand (op, mode))
633 return 1;
634
635 return 0;
636}
637
ab835497 638int
6ac34277 639splittable_symbolic_memory_operand (op, mode)
ab835497 640 rtx op;
487a6e06 641 enum machine_mode mode ATTRIBUTE_UNUSED;
ab835497 642{
6ac34277
DE		 643 if (GET_CODE (op) != MEM)
644 return 0;
645 if (! symbolic_operand (XEXP (op, 0), Pmode))
646 return 0;
647 return 1;
648}
649
650int
651splittable_immediate_memory_operand (op, mode)
652 rtx op;
487a6e06 653 enum machine_mode mode ATTRIBUTE_UNUSED;
6ac34277
DE		 654{
655 if (GET_CODE (op) != MEM)
656 return 0;
657 if (! immediate_operand (XEXP (op, 0), Pmode))
658 return 0;
659 return 1;
ab835497
RK		 660}
661
662/* Return truth value of whether OP is EQ or NE. */
663
664int
665eq_or_neq (op, mode)
666 rtx op;
487a6e06 667 enum machine_mode mode ATTRIBUTE_UNUSED;
ab835497
RK		 668{
669 return (GET_CODE (op) == EQ || GET_CODE (op) == NE);
670}
671
672/* Return 1 if this is a comparison operator, but not an EQ, NE, GEU,
673 or LTU for non-floating-point. We handle those specially. */
674
675int
676normal_comp_operator (op, mode)
677 rtx op;
487a6e06 678 enum machine_mode mode ATTRIBUTE_UNUSED;
ab835497
RK		 679{
680 enum rtx_code code = GET_CODE (op);
681
682 if (GET_RTX_CLASS (code) != '<')
683 return 0;
684
4d449554
JW		 685 if (GET_MODE (XEXP (op, 0)) == CCFPmode
686 || GET_MODE (XEXP (op, 0)) == CCFPEmode)
ab835497
RK		 687 return 1;
688
689 return (code != NE && code != EQ && code != GEU && code != LTU);
690}
691
692/* Return 1 if this is a comparison operator. This allows the use of
693 MATCH_OPERATOR to recognize all the branch insns. */
694
695int
696noov_compare_op (op, mode)
697 register rtx op;
487a6e06 698 enum machine_mode mode ATTRIBUTE_UNUSED;
ab835497
RK		 699{
700 enum rtx_code code = GET_CODE (op);
701
702 if (GET_RTX_CLASS (code) != '<')
703 return 0;
704
705 if (GET_MODE (XEXP (op, 0)) == CC_NOOVmode)
706 /* These are the only branches which work with CC_NOOVmode. */
707 return (code == EQ || code == NE || code == GE || code == LT);
708 return 1;
709}
710
61a55e8b
DE		 711/* Nonzero if OP is a comparison operator suitable for use in v9
712 conditional move or branch on register contents instructions. */
713
714int
715v9_regcmp_op (op, mode)
716 register rtx op;
487a6e06 717 enum machine_mode mode ATTRIBUTE_UNUSED;
61a55e8b
DE		 718{
719 enum rtx_code code = GET_CODE (op);
720
721 if (GET_RTX_CLASS (code) != '<')
722 return 0;
723
cd5fb1ee 724 return v9_regcmp_p (code);
61a55e8b
DE		 725}
726
ab835497
RK		 727/* Return 1 if this is a SIGN_EXTEND or ZERO_EXTEND operation. */
728
729int
730extend_op (op, mode)
731 rtx op;
487a6e06 732 enum machine_mode mode ATTRIBUTE_UNUSED;
ab835497
RK		 733{
734 return GET_CODE (op) == SIGN_EXTEND || GET_CODE (op) == ZERO_EXTEND;
735}
736
737/* Return nonzero if OP is an operator of mode MODE which can set
738 the condition codes explicitly. We do not include PLUS and MINUS
739 because these require CC_NOOVmode, which we handle explicitly. */
740
741int
742cc_arithop (op, mode)
743 rtx op;
487a6e06 744 enum machine_mode mode ATTRIBUTE_UNUSED;
ab835497
RK		 745{
746 if (GET_CODE (op) == AND
747 || GET_CODE (op) == IOR
748 || GET_CODE (op) == XOR)
749 return 1;
750
751 return 0;
752}
753
754/* Return nonzero if OP is an operator of mode MODE which can bitwise
755 complement its second operand and set the condition codes explicitly. */
756
757int
758cc_arithopn (op, mode)
759 rtx op;
487a6e06 760 enum machine_mode mode ATTRIBUTE_UNUSED;
ab835497
RK		 761{
762 /* XOR is not here because combine canonicalizes (xor (not ...) ...)
763 and (xor ... (not ...)) to (not (xor ...)). */
764 return (GET_CODE (op) == AND
765 || GET_CODE (op) == IOR);
766}
767\f
58cbf20e
DE		 768/* Return true if OP is a register, or is a CONST_INT that can fit in a
769 signed 13 bit immediate field. This is an acceptable SImode operand for
770 most 3 address instructions. */
ab835497
RK		 771
772int
773arith_operand (op, mode)
774 rtx op;
775 enum machine_mode mode;
776{
284d86e9 777 int val;
f7e0e539
DM		 778 if (register_operand (op, mode)
779 || GET_CODE (op) == CONSTANT_P_RTX)
284d86e9
JC		 780 return 1;
781 if (GET_CODE (op) != CONST_INT)
782 return 0;
783 val = INTVAL (op) & 0xffffffff;
784 return SPARC_SIMM13_P (val);
ab835497
RK		 785}
786
5d6d3339
JJ		 787/* Return true if OP is a constant 4096 */
788
789int
790arith_4096_operand (op, mode)
791 rtx op;
ddf80874 792 enum machine_mode mode ATTRIBUTE_UNUSED;
5d6d3339
JJ		 793{
794 int val;
795 if (GET_CODE (op) != CONST_INT)
796 return 0;
797 val = INTVAL (op) & 0xffffffff;
798 return val == 4096;
799}
800
801/* Return true if OP is suitable as second operand for add/sub */
802
803int
804arith_add_operand (op, mode)
805 rtx op;
806 enum machine_mode mode;
807{
808 return arith_operand (op, mode) || arith_4096_operand (op, mode);
809}
810
89e65674
DM		 811/* Return true if OP is a CONST_INT or a CONST_DOUBLE which can fit in the
812 immediate field of OR and XOR instructions. Used for 64-bit
813 constant formation patterns. */
814int
815const64_operand (op, mode)
816 rtx op;
ddf80874 817 enum machine_mode mode ATTRIBUTE_UNUSED;
89e65674
DM		 818{
819 return ((GET_CODE (op) == CONST_INT
820 && SPARC_SIMM13_P (INTVAL (op)))
9208e4b2 821#if HOST_BITS_PER_WIDE_INT != 64
89e65674 822 || (GET_CODE (op) == CONST_DOUBLE
9208e4b2
DM		 823 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op))
824 && (CONST_DOUBLE_HIGH (op) ==
825 ((CONST_DOUBLE_LOW (op) & 0x80000000) != 0 ?
ddf80874 826 (HOST_WIDE_INT)0xffffffff : 0)))
9208e4b2 827#endif
89e65674
DM		 828 || GET_CODE (op) == CONSTANT_P_RTX);
829}
830
9208e4b2 831/* The same, but only for sethi instructions. */
89e65674
DM		 832int
833const64_high_operand (op, mode)
834 rtx op;
ddf80874 835 enum machine_mode mode ATTRIBUTE_UNUSED;
89e65674
DM		 836{
837 return ((GET_CODE (op) == CONST_INT
9208e4b2
DM		 838 && (INTVAL (op) & 0xfffffc00) != 0
839 && SPARC_SETHI_P (INTVAL (op))
840#if HOST_BITS_PER_WIDE_INT != 64
841 /* Must be positive on non-64bit host else the
842 optimizer is fooled into thinking that sethi
843 sign extends, even though it does not. */
844 && INTVAL (op) >= 0
845#endif
846 )
89e65674
DM		 847 || (GET_CODE (op) == CONST_DOUBLE
848 && CONST_DOUBLE_HIGH (op) == 0
9208e4b2 849 && (CONST_DOUBLE_LOW (op) & 0xfffffc00) != 0
89e65674
DM		 850 && SPARC_SETHI_P (CONST_DOUBLE_LOW (op)))
851 || GET_CODE (op) == CONSTANT_P_RTX);
852}
853
58cbf20e
DE		 854/* Return true if OP is a register, or is a CONST_INT that can fit in a
855 signed 11 bit immediate field. This is an acceptable SImode operand for
856 the movcc instructions. */
61a55e8b
DE		 857
858int
859arith11_operand (op, mode)
860 rtx op;
861 enum machine_mode mode;
862{
863 return (register_operand (op, mode)
f7e0e539 864 || GET_CODE (op) == CONSTANT_P_RTX
58cbf20e 865 || (GET_CODE (op) == CONST_INT && SPARC_SIMM11_P (INTVAL (op))));
61a55e8b
DE		 866}
867
58cbf20e
DE		 868/* Return true if OP is a register, or is a CONST_INT that can fit in a
869 signed 10 bit immediate field. This is an acceptable SImode operand for
870 the movrcc instructions. */
61a55e8b
DE		 871
872int
873arith10_operand (op, mode)
874 rtx op;
875 enum machine_mode mode;
876{
877 return (register_operand (op, mode)
f7e0e539 878 || GET_CODE (op) == CONSTANT_P_RTX
58cbf20e 879 || (GET_CODE (op) == CONST_INT && SPARC_SIMM10_P (INTVAL (op))));
61a55e8b
DE		 880}
881
23b8a89f
JW		 882/* Return true if OP is a register, is a CONST_INT that fits in a 13 bit
883 immediate field, or is a CONST_DOUBLE whose both parts fit in a 13 bit
61a55e8b
DE		 884 immediate field.
885 v9: Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
886 can fit in a 13 bit immediate field. This is an acceptable DImode operand
887 for most 3 address instructions. */
ab835497
RK		 888
889int
890arith_double_operand (op, mode)
891 rtx op;
892 enum machine_mode mode;
893{
894 return (register_operand (op, mode)
f7e0e539 895 || GET_CODE (op) == CONSTANT_P_RTX
23b8a89f 896 || (GET_CODE (op) == CONST_INT && SMALL_INT (op))
a9e27770 897 || (! TARGET_ARCH64
61a55e8b 898 && GET_CODE (op) == CONST_DOUBLE
bf62bbf1
DE		 899 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x1000) < 0x2000
900 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_HIGH (op) + 0x1000) < 0x2000)
a9e27770 901 || (TARGET_ARCH64
61a55e8b 902 && GET_CODE (op) == CONST_DOUBLE
bf62bbf1 903 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x1000) < 0x2000
61a55e8b
DE		 904 && ((CONST_DOUBLE_HIGH (op) == -1
905 && (CONST_DOUBLE_LOW (op) & 0x1000) == 0x1000)
906 || (CONST_DOUBLE_HIGH (op) == 0
907 && (CONST_DOUBLE_LOW (op) & 0x1000) == 0))));
908}
909
5d6d3339
JJ		 910/* Return true if OP is a constant 4096 for DImode on ARCH64 */
911
912int
913arith_double_4096_operand (op, mode)
914 rtx op;
ddf80874 915 enum machine_mode mode ATTRIBUTE_UNUSED;
5d6d3339
JJ		 916{
917 return (TARGET_ARCH64 &&
918 ((GET_CODE (op) == CONST_INT && INTVAL (op) == 4096) ||
919 (GET_CODE (op) == CONST_DOUBLE &&
920 CONST_DOUBLE_LOW (op) == 4096 &&
921 CONST_DOUBLE_HIGH (op) == 0)));
922}
923
924/* Return true if OP is suitable as second operand for add/sub in DImode */
925
926int
927arith_double_add_operand (op, mode)
928 rtx op;
929 enum machine_mode mode;
930{
931 return arith_double_operand (op, mode) || arith_double_4096_operand (op, mode);
932}
933
61a55e8b
DE		 934/* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
935 can fit in an 11 bit immediate field. This is an acceptable DImode
936 operand for the movcc instructions. */
937/* ??? Replace with arith11_operand? */
938
939int
940arith11_double_operand (op, mode)
941 rtx op;
942 enum machine_mode mode;
943{
944 return (register_operand (op, mode)
f7e0e539 945 || GET_CODE (op) == CONSTANT_P_RTX
61a55e8b
DE		 946 || (GET_CODE (op) == CONST_DOUBLE
947 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
bf62bbf1 948 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x400) < 0x800
61a55e8b
DE		 949 && ((CONST_DOUBLE_HIGH (op) == -1
950 && (CONST_DOUBLE_LOW (op) & 0x400) == 0x400)
951 || (CONST_DOUBLE_HIGH (op) == 0
952 && (CONST_DOUBLE_LOW (op) & 0x400) == 0)))
953 || (GET_CODE (op) == CONST_INT
954 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
bf62bbf1 955 && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x400) < 0x800));
61a55e8b
DE		 956}
957
958/* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
959 can fit in an 10 bit immediate field. This is an acceptable DImode
960 operand for the movrcc instructions. */
961/* ??? Replace with arith10_operand? */
962
963int
964arith10_double_operand (op, mode)
965 rtx op;
966 enum machine_mode mode;
967{
968 return (register_operand (op, mode)
f7e0e539 969 || GET_CODE (op) == CONSTANT_P_RTX
61a55e8b
DE		 970 || (GET_CODE (op) == CONST_DOUBLE
971 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
972 && (unsigned) (CONST_DOUBLE_LOW (op) + 0x200) < 0x400
973 && ((CONST_DOUBLE_HIGH (op) == -1
974 && (CONST_DOUBLE_LOW (op) & 0x200) == 0x200)
975 || (CONST_DOUBLE_HIGH (op) == 0
976 && (CONST_DOUBLE_LOW (op) & 0x200) == 0)))
977 || (GET_CODE (op) == CONST_INT
978 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
bf62bbf1 979 && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x200) < 0x400));
ab835497
RK		 980}
981
982/* Return truth value of whether OP is a integer which fits the
228b4037
JW		 983 range constraining immediate operands in most three-address insns,
984 which have a 13 bit immediate field. */
ab835497
RK		 985
986int
987small_int (op, mode)
988 rtx op;
487a6e06 989 enum machine_mode mode ATTRIBUTE_UNUSED;
ab835497 990{
f7e0e539
DM		 991 return ((GET_CODE (op) == CONST_INT && SMALL_INT (op))
992 || GET_CODE (op) == CONSTANT_P_RTX);
ab835497
RK		 993}
994
e0d80184
DM		 995int
996small_int_or_double (op, mode)
997 rtx op;
998 enum machine_mode mode ATTRIBUTE_UNUSED;
999{
1000 return ((GET_CODE (op) == CONST_INT && SMALL_INT (op))
1001 || (GET_CODE (op) == CONST_DOUBLE
1002 && CONST_DOUBLE_HIGH (op) == 0
1003 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op)))
1004 || GET_CODE (op) == CONSTANT_P_RTX);
1005}
1006
9b3fad96
JW		 1007/* Recognize operand values for the umul instruction. That instruction sign
1008 extends immediate values just like all other sparc instructions, but
1009 interprets the extended result as an unsigned number. */
1010
1011int
1012uns_small_int (op, mode)
1013 rtx op;
487a6e06 1014 enum machine_mode mode ATTRIBUTE_UNUSED;
9b3fad96
JW		 1015{
1016#if HOST_BITS_PER_WIDE_INT > 32
1017 /* All allowed constants will fit a CONST_INT. */
f7e0e539
DM		 1018 return ((GET_CODE (op) == CONST_INT
1019 && ((INTVAL (op) >= 0 && INTVAL (op) < 0x1000)
e0d80184
DM		 1020 || (INTVAL (op) >= 0xFFFFF000
1021 && INTVAL (op) < 0x100000000)))
f7e0e539 1022 || GET_CODE (op) == CONSTANT_P_RTX);
9b3fad96 1023#else
f7e0e539
DM		 1024 return (((GET_CODE (op) == CONST_INT && (unsigned) INTVAL (op) < 0x1000)
1025 || (GET_CODE (op) == CONST_DOUBLE
1026 && CONST_DOUBLE_HIGH (op) == 0
1027 && (unsigned) CONST_DOUBLE_LOW (op) - 0xFFFFF000 < 0x1000))
1028 || GET_CODE (op) == CONSTANT_P_RTX);
9b3fad96
JW		 1029#endif
1030}
1031
1032int
1033uns_arith_operand (op, mode)
1034 rtx op;
1035 enum machine_mode mode;
1036{
1037 return register_operand (op, mode) || uns_small_int (op, mode);
1038}
1039
ab835497
RK		 1040/* Return truth value of statement that OP is a call-clobbered register. */
1041int
1042clobbered_register (op, mode)
1043 rtx op;
487a6e06 1044 enum machine_mode mode ATTRIBUTE_UNUSED;
ab835497
RK		 1045{
1046 return (GET_CODE (op) == REG && call_used_regs[REGNO (op)]);
1047}
ab835497 1048
e0d80184
DM		 1049/* Return 1 if OP is const0_rtx, used for TARGET_LIVE_G0 insns. */
1050
1051int
1052zero_operand (op, mode)
1053 rtx op;
1054 enum machine_mode mode ATTRIBUTE_UNUSED;
ab835497 1055{
e0d80184
DM		 1056 return (op == const0_rtx || GET_CODE (op) == CONSTANT_P_RTX);
1057}
61a55e8b 1058
e0d80184 1059/* Return 1 if OP is a valid operand for the source of a move insn. */
61a55e8b 1060
e0d80184
DM		 1061int
1062input_operand (op, mode)
1063 rtx op;
1064 enum machine_mode mode;
1065{
1066 /* If both modes are non-void they must be the same. */
1067 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op))
1068 return 0;
61a55e8b 1069
e0d80184
DM		 1070 /* Allow any one instruction integer constant, and all CONST_INT
1071 variants when we are working in DImode and !arch64. */
1072 if (GET_MODE_CLASS (mode) == MODE_INT
9208e4b2
DM		 1073 && ((GET_CODE (op) == CONST_INT
1074 && ((SPARC_SETHI_P (INTVAL (op))
1075 && (! TARGET_ARCH64
1076 || (INTVAL (op) >= 0)
1077 || mode == SImode))
1078 || SPARC_SIMM13_P (INTVAL (op))
1079 || (mode == DImode
1080 && ! TARGET_ARCH64)))
1081 || (TARGET_ARCH64
1082 && GET_CODE (op) == CONST_DOUBLE
1083 && ((CONST_DOUBLE_HIGH (op) == 0
1084 && SPARC_SETHI_P (CONST_DOUBLE_LOW (op)))
1085 ||
1086#if HOST_BITS_PER_WIDE_INT == 64
1087 (CONST_DOUBLE_HIGH (op) == 0
1088 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op)))
1089#else
1090 (SPARC_SIMM13_P (CONST_DOUBLE_LOW (op))
1091 && (((CONST_DOUBLE_LOW (op) & 0x80000000) == 0
1092 && CONST_DOUBLE_HIGH (op) == 0)
1093 || (CONST_DOUBLE_HIGH (op) == -1)))
1094#endif
1095 ))))
e0d80184
DM		 1096 return 1;
1097
1098 /* Always match this. */
1099 if (GET_CODE (op) == CONSTANT_P_RTX)
1100 return 1;
1101
1102 /* If !arch64 and this is a DImode const, allow it so that
1103 the splits can be generated. */
1104 if (! TARGET_ARCH64
1105 && mode == DImode
1106 && GET_CODE (op) == CONST_DOUBLE)
1107 return 1;
1108
1109 if (register_operand (op, mode))
1110 return 1;
1111
1112 /* If this is a SUBREG, look inside so that we handle
1113 paradoxical ones. */
1114 if (GET_CODE (op) == SUBREG)
1115 op = SUBREG_REG (op);
1116
1117 /* Check for valid MEM forms. */
1118 if (GET_CODE (op) == MEM)
61a55e8b 1119 {
e0d80184 1120 rtx inside = XEXP (op, 0);
61a55e8b 1121
e0d80184 1122 if (GET_CODE (inside) == LO_SUM)
03ad6f4d
DM		 1123 {
1124 /* We can't allow these because all of the splits
1125 (eventually as they trickle down into DFmode
1126 splits) require offsettable memory references. */
1127 if (! TARGET_V9
1128 && GET_MODE (op) == TFmode)
1129 return 0;
1130
1131 return (register_operand (XEXP (inside, 0), Pmode)
1132 && CONSTANT_P (XEXP (inside, 1)));
1133 }
e0d80184 1134 return memory_address_p (mode, inside);
61a55e8b 1135 }
ab835497 1136
e0d80184
DM		 1137 return 0;
1138}
1139
1140\f
1141/* We know it can't be done in one insn when we get here,
1142 the movsi expander guarentees this. */
1143void
1144sparc_emit_set_const32 (op0, op1)
1145 rtx op0;
1146 rtx op1;
1147{
1148 enum machine_mode mode = GET_MODE (op0);
1149 rtx temp;
1150
1151 if (GET_CODE (op1) == CONST_INT)
284d86e9 1152 {
2a01c939 1153 HOST_WIDE_INT value = INTVAL (op1);
e0d80184
DM		 1154
1155 if (SPARC_SETHI_P (value)
1156 || SPARC_SIMM13_P (value))
1157 abort ();
284d86e9 1158 }
e0d80184
DM		 1159
1160 /* Full 2-insn decomposition is needed. */
1161 if (reload_in_progress || reload_completed)
1162 temp = op0;
284d86e9 1163 else
e0d80184
DM		 1164 temp = gen_reg_rtx (mode);
1165
71648202
DM		 1166 if (GET_CODE (op1) == CONST_INT)
1167 {
1168 /* Emit them as real moves instead of a HIGH/LO_SUM,
1169 this way CSE can see everything and reuse intermediate
1170 values if it wants. */
1171 if (TARGET_ARCH64
1172 && HOST_BITS_PER_WIDE_INT != 64
1173 && (INTVAL (op1) & 0x80000000) != 0)
1174 {
1175 emit_insn (gen_rtx_SET (VOIDmode,
1176 temp,
1177 gen_rtx_CONST_DOUBLE (VOIDmode, const0_rtx,
1178 INTVAL (op1) & 0xfffffc00, 0)));
1179 }
1180 else
1181 {
1182 emit_insn (gen_rtx_SET (VOIDmode,
1183 temp,
1184 GEN_INT (INTVAL (op1) & 0xfffffc00)));
1185 }
1186 emit_insn (gen_rtx_SET (VOIDmode,
1187 op0,
1188 gen_rtx_IOR (mode,
1189 temp,
1190 GEN_INT (INTVAL (op1) & 0x3ff))));
1191 }
1192 else
1193 {
1194 /* A symbol, emit in the traditional way. */
1195 emit_insn (gen_rtx_SET (VOIDmode,
1196 temp,
1197 gen_rtx_HIGH (mode,
1198 op1)));
1199 emit_insn (gen_rtx_SET (VOIDmode,
1200 op0,
1201 gen_rtx_LO_SUM (mode,
1202 temp,
1203 op1)));
1204
1205 }
e0d80184
DM		 1206}
1207
1208\f
1209/* Sparc-v9 code-model support. */
1210void
1211sparc_emit_set_symbolic_const64 (op0, op1, temp1)
1212 rtx op0;
1213 rtx op1;
1214 rtx temp1;
1215{
1216 switch (sparc_cmodel)
284d86e9 1217 {
e0d80184
DM		 1218 case CM_MEDLOW:
1219 /* The range spanned by all instructions in the object is less
1220 than 2^31 bytes (2GB) and the distance from any instruction
1221 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1222 than 2^31 bytes (2GB).
ab835497 1223
e0d80184
DM		 1224 The executable must be in the low 4TB of the virtual address
1225 space.
61a55e8b 1226
e0d80184
DM		 1227 sethi %hi(symbol), %temp
1228 or %temp, %lo(symbol), %reg */
9208e4b2
DM		 1229 emit_insn (gen_rtx_SET (VOIDmode, temp1, gen_rtx_HIGH (DImode, op1)));
1230 emit_insn (gen_rtx_SET (VOIDmode, op0, gen_rtx_LO_SUM (DImode, temp1, op1)));
e0d80184 1231 break;
61a55e8b 1232
e0d80184
DM		 1233 case CM_MEDMID:
1234 /* The range spanned by all instructions in the object is less
1235 than 2^31 bytes (2GB) and the distance from any instruction
1236 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1237 than 2^31 bytes (2GB).
1238
1239 The executable must be in the low 16TB of the virtual address
1240 space.
1241
1242 sethi %h44(symbol), %temp1
1243 or %temp1, %m44(symbol), %temp2
1244 sllx %temp2, 12, %temp3
1245 or %temp3, %l44(symbol), %reg */
1246 emit_insn (gen_seth44 (op0, op1));
1247 emit_insn (gen_setm44 (op0, op0, op1));
9208e4b2 1248 emit_insn (gen_rtx_SET (VOIDmode, temp1,
e0d80184
DM		 1249 gen_rtx_ASHIFT (DImode, op0, GEN_INT (12))));
1250 emit_insn (gen_setl44 (op0, temp1, op1));
1251 break;
61a55e8b 1252
e0d80184
DM		 1253 case CM_MEDANY:
1254 /* The range spanned by all instructions in the object is less
1255 than 2^31 bytes (2GB) and the distance from any instruction
1256 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1257 than 2^31 bytes (2GB).
1258
1259 The executable can be placed anywhere in the virtual address
1260 space.
1261
1262 sethi %hh(symbol), %temp1
1263 sethi %lm(symbol), %temp2
1264 or %temp1, %hm(symbol), %temp3
1265 or %temp2, %lo(symbol), %temp4
1266 sllx %temp3, 32, %temp5
1267 or %temp4, %temp5, %reg */
1268
1269 /* Getting this right wrt. reloading is really tricky.
1270 We _MUST_ have a seperate temporary at this point,
1271 if we don't barf immediately instead of generating
1272 incorrect code. */
1273 if (temp1 == op0)
1274 abort ();
61a55e8b 1275
e0d80184
DM		 1276 emit_insn (gen_sethh (op0, op1));
1277 emit_insn (gen_setlm (temp1, op1));
1278 emit_insn (gen_sethm (op0, op0, op1));
9208e4b2 1279 emit_insn (gen_rtx_SET (VOIDmode, op0,
e0d80184 1280 gen_rtx_ASHIFT (DImode, op0, GEN_INT (32))));
9208e4b2 1281 emit_insn (gen_rtx_SET (VOIDmode, op0,
e0d80184
DM		 1282 gen_rtx_PLUS (DImode, op0, temp1)));
1283 emit_insn (gen_setlo (op0, op0, op1));
1284 break;
61a55e8b 1285
e0d80184
DM		 1286 case CM_EMBMEDANY:
1287 /* Old old old backwards compatibility kruft here.
1288 Essentially it is MEDLOW with a fixed 64-bit
1289 virtual base added to all data segment addresses.
1290 Text-segment stuff is computed like MEDANY, we can't
1291 reuse the code above because the relocation knobs
1292 look different.
1293
1294 Data segment: sethi %hi(symbol), %temp1
1295 or %temp1, %lo(symbol), %temp2
1296 add %temp2, EMBMEDANY_BASE_REG, %reg
1297
1298 Text segment: sethi %uhi(symbol), %temp1
1299 sethi %hi(symbol), %temp2
1300 or %temp1, %ulo(symbol), %temp3
1301 or %temp2, %lo(symbol), %temp4
1302 sllx %temp3, 32, %temp5
1303 or %temp4, %temp5, %reg */
1304 if (data_segment_operand (op1, GET_MODE (op1)))
1305 {
1306 emit_insn (gen_embmedany_sethi (temp1, op1));
1307 emit_insn (gen_embmedany_brsum (op0, temp1));
1308 emit_insn (gen_embmedany_losum (op0, op0, op1));
1309 }
1310 else
1311 {
1312 /* Getting this right wrt. reloading is really tricky.
1313 We _MUST_ have a seperate temporary at this point,
f710f868 1314 so we barf immediately instead of generating
e0d80184
DM		 1315 incorrect code. */
1316 if (temp1 == op0)
1317 abort ();
61a55e8b 1318
e0d80184
DM		 1319 emit_insn (gen_embmedany_textuhi (op0, op1));
1320 emit_insn (gen_embmedany_texthi (temp1, op1));
1321 emit_insn (gen_embmedany_textulo (op0, op0, op1));
9208e4b2 1322 emit_insn (gen_rtx_SET (VOIDmode, op0,
e0d80184 1323 gen_rtx_ASHIFT (DImode, op0, GEN_INT (32))));
9208e4b2 1324 emit_insn (gen_rtx_SET (VOIDmode, op0,
e0d80184
DM		 1325 gen_rtx_PLUS (DImode, op0, temp1)));
1326 emit_insn (gen_embmedany_textlo (op0, op0, op1));
1327 }
1328 break;
1329
1330 default:
1331 abort();
1332 }
1333}
1334
9208e4b2
DM		 1335/* These avoid problems when cross compiling. If we do not
1336 go through all this hair then the optimizer will see
1337 invalid REG_EQUAL notes or in some cases none at all. */
1338static void sparc_emit_set_safe_HIGH64 PROTO ((rtx, HOST_WIDE_INT));
1339static rtx gen_safe_SET64 PROTO ((rtx, HOST_WIDE_INT));
1340static rtx gen_safe_OR64 PROTO ((rtx, HOST_WIDE_INT));
1341static rtx gen_safe_XOR64 PROTO ((rtx, HOST_WIDE_INT));
1342
1343#if HOST_BITS_PER_WIDE_INT == 64
1344#define GEN_HIGHINT64(__x) GEN_INT ((__x) & 0xfffffc00)
1345#define GEN_INT64(__x) GEN_INT (__x)
1346#else
1347#define GEN_HIGHINT64(__x) \
1348 gen_rtx_CONST_DOUBLE (VOIDmode, const0_rtx, \
1349 (__x) & 0xfffffc00, 0)
1350#define GEN_INT64(__x) \
1351 gen_rtx_CONST_DOUBLE (VOIDmode, const0_rtx, \
1352 (__x) & 0xffffffff, \
1353 ((__x) & 0x80000000 \
1354 ? 0xffffffff : 0))
1355#endif
1356
1357/* The optimizer is not to assume anything about exactly
1358 which bits are set for a HIGH, they are unspecified.
1359 Unfortunately this leads to many missed optimizations
1360 during CSE. We mask out the non-HIGH bits, and matches
1361 a plain movdi, to alleviate this problem. */
1362static void
1363sparc_emit_set_safe_HIGH64 (dest, val)
1364 rtx dest;
1365 HOST_WIDE_INT val;
1366{
1367 emit_insn (gen_rtx_SET (VOIDmode, dest, GEN_HIGHINT64 (val)));
1368}
2a01c939 1369
e0d80184 1370static rtx
9208e4b2
DM		 1371gen_safe_SET64 (dest, val)
1372 rtx dest;
e0d80184 1373 HOST_WIDE_INT val;
61a55e8b 1374{
9208e4b2
DM		 1375 return gen_rtx_SET (VOIDmode, dest, GEN_INT64 (val));
1376}
1377
1378static rtx
1379gen_safe_OR64 (src, val)
1380 rtx src;
1381 HOST_WIDE_INT val;
1382{
1383 return gen_rtx_IOR (DImode, src, GEN_INT64 (val));
1384}
1385
1386static rtx
1387gen_safe_XOR64 (src, val)
1388 rtx src;
1389 HOST_WIDE_INT val;
1390{
1391 return gen_rtx_XOR (DImode, src, GEN_INT64 (val));
e0d80184 1392}
61a55e8b 1393
e0d80184
DM		 1394/* Worker routines for 64-bit constant formation on arch64.
1395 One of the key things to be doing in these emissions is
1396 to create as many temp REGs as possible. This makes it
1397 possible for half-built constants to be used later when
1398 such values are similar to something required later on.
1399 Without doing this, the optimizer cannot see such
1400 opportunities. */
2a01c939
DM		 1401
1402static void sparc_emit_set_const64_quick1
1403 PROTO((rtx, rtx, unsigned HOST_WIDE_INT, int));
1404
e0d80184
DM		 1405static void
1406sparc_emit_set_const64_quick1 (op0, temp, low_bits, is_neg)
1407 rtx op0;
1408 rtx temp;
2a01c939 1409 unsigned HOST_WIDE_INT low_bits;
e0d80184
DM		 1410 int is_neg;
1411{
2a01c939 1412 unsigned HOST_WIDE_INT high_bits;
a9e27770 1413
e0d80184 1414 if (is_neg)
2a01c939 1415 high_bits = (~low_bits) & 0xffffffff;
31bc9eba 1416 else
e0d80184 1417 high_bits = low_bits;
31bc9eba 1418
9208e4b2 1419 sparc_emit_set_safe_HIGH64 (temp, high_bits);
e0d80184 1420 if (!is_neg)
5108f3e5
DM		 1421 {
1422 emit_insn (gen_rtx_SET (VOIDmode, op0,
1423 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
1424 }
e0d80184 1425 else
5108f3e5
DM		 1426 {
1427 /* If we are XOR'ing with -1, then we should emit a one's complement
1428 instead. This way the combiner will notice logical operations
1429 such as ANDN later on and substitute. */
1430 if ((low_bits & 0x3ff) == 0x3ff)
1431 {
1432 emit_insn (gen_rtx_SET (VOIDmode, op0,
1433 gen_rtx_NOT (DImode, temp)));
1434 }
1435 else
1436 {
1437 emit_insn (gen_rtx_SET (VOIDmode, op0,
1438 gen_safe_XOR64 (temp,
1439 (-0x400 | (low_bits & 0x3ff)))));
1440 }
1441 }
e0d80184 1442}
61a55e8b 1443
2a01c939
DM		 1444static void sparc_emit_set_const64_quick2
1445 PROTO((rtx, rtx, unsigned HOST_WIDE_INT,
1446 unsigned HOST_WIDE_INT, int));
1447
e0d80184
DM		 1448static void
1449sparc_emit_set_const64_quick2 (op0, temp, high_bits, low_immediate, shift_count)
1450 rtx op0;
1451 rtx temp;
2a01c939
DM		 1452 unsigned HOST_WIDE_INT high_bits;
1453 unsigned HOST_WIDE_INT low_immediate;
e0d80184
DM		 1454 int shift_count;
1455{
1456 rtx temp2 = op0;
61a55e8b 1457
e0d80184
DM		 1458 if ((high_bits & 0xfffffc00) != 0)
1459 {
9208e4b2 1460 sparc_emit_set_safe_HIGH64 (temp, high_bits);
e0d80184 1461 if ((high_bits & ~0xfffffc00) != 0)
9208e4b2
DM		 1462 emit_insn (gen_rtx_SET (VOIDmode, op0,
1463 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
61a55e8b 1464 else
e0d80184 1465 temp2 = temp;
61a55e8b
DE		 1466 }
1467 else
1468 {
f710f868 1469 emit_insn (gen_safe_SET64 (temp, high_bits));
e0d80184
DM		 1470 temp2 = temp;
1471 }
61a55e8b 1472
e0d80184 1473 /* Now shift it up into place. */
9208e4b2 1474 emit_insn (gen_rtx_SET (VOIDmode, op0,
e0d80184
DM		 1475 gen_rtx_ASHIFT (DImode, temp2,
1476 GEN_INT (shift_count))));
61a55e8b 1477
e0d80184
DM		 1478 /* If there is a low immediate part piece, finish up by
1479 putting that in as well. */
1480 if (low_immediate != 0)
9208e4b2
DM		 1481 emit_insn (gen_rtx_SET (VOIDmode, op0,
1482 gen_safe_OR64 (op0, low_immediate)));
ab835497
RK		 1483}
1484
2a01c939
DM		 1485static void sparc_emit_set_const64_longway
1486 PROTO((rtx, rtx, unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT));
1487
e0d80184
DM		 1488/* Full 64-bit constant decomposition. Even though this is the
1489 'worst' case, we still optimize a few things away. */
1490static void
1491sparc_emit_set_const64_longway (op0, temp, high_bits, low_bits)
1492 rtx op0;
1493 rtx temp;
2a01c939
DM		 1494 unsigned HOST_WIDE_INT high_bits;
1495 unsigned HOST_WIDE_INT low_bits;
ab835497 1496{
e0d80184 1497 rtx sub_temp;
4bf7135b 1498
e0d80184
DM		 1499 if (reload_in_progress || reload_completed)
1500 sub_temp = op0;
1501 else
1502 sub_temp = gen_reg_rtx (DImode);
1503
1504 if ((high_bits & 0xfffffc00) != 0)
1505 {
9208e4b2 1506 sparc_emit_set_safe_HIGH64 (temp, high_bits);
e0d80184 1507 if ((high_bits & ~0xfffffc00) != 0)
9208e4b2 1508 emit_insn (gen_rtx_SET (VOIDmode,
e0d80184 1509 sub_temp,
9208e4b2 1510 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
e0d80184
DM		 1511 else
1512 sub_temp = temp;
1513 }
1514 else
ab835497 1515 {
f710f868 1516 emit_insn (gen_safe_SET64 (temp, high_bits));
e0d80184 1517 sub_temp = temp;
ab835497 1518 }
4bf7135b 1519
e0d80184 1520 if (!reload_in_progress && !reload_completed)
284d86e9 1521 {
e0d80184
DM		 1522 rtx temp2 = gen_reg_rtx (DImode);
1523 rtx temp3 = gen_reg_rtx (DImode);
1524 rtx temp4 = gen_reg_rtx (DImode);
284d86e9 1525
9208e4b2 1526 emit_insn (gen_rtx_SET (VOIDmode, temp4,
e0d80184
DM		 1527 gen_rtx_ASHIFT (DImode, sub_temp,
1528 GEN_INT (32))));
4bf7135b 1529
9208e4b2 1530 sparc_emit_set_safe_HIGH64 (temp2, low_bits);
e0d80184 1531 if ((low_bits & ~0xfffffc00) != 0)
f710f868
DM		 1532 {
1533 emit_insn (gen_rtx_SET (VOIDmode, temp3,
1534 gen_safe_OR64 (temp2, (low_bits & 0x3ff))));
1535 emit_insn (gen_rtx_SET (VOIDmode, op0,
1536 gen_rtx_PLUS (DImode, temp4, temp3)));
1537 }
1538 else
1539 {
1540 emit_insn (gen_rtx_SET (VOIDmode, op0,
1541 gen_rtx_PLUS (DImode, temp4, temp2)));
1542 }
284d86e9 1543 }
e0d80184
DM		 1544 else
1545 {
9208e4b2
DM		 1546 rtx low1 = GEN_INT ((low_bits >> (32 - 12)) & 0xfff);
1547 rtx low2 = GEN_INT ((low_bits >> (32 - 12 - 12)) & 0xfff);
1548 rtx low3 = GEN_INT ((low_bits >> (32 - 12 - 12 - 8)) & 0x0ff);
e0d80184 1549 int to_shift = 12;
284d86e9 1550
e0d80184
DM		 1551 /* We are in the middle of reload, so this is really
1552 painful. However we do still make an attempt to
5108f3e5 1553 avoid emitting truly stupid code. */
e0d80184
DM		 1554 if (low1 != const0_rtx)
1555 {
9208e4b2 1556 emit_insn (gen_rtx_SET (VOIDmode, op0,
e0d80184 1557 gen_rtx_ASHIFT (DImode, sub_temp,
2a01c939 1558 GEN_INT (to_shift))));
9208e4b2 1559 emit_insn (gen_rtx_SET (VOIDmode, op0,
e0d80184
DM		 1560 gen_rtx_IOR (DImode, op0, low1)));
1561 sub_temp = op0;
1562 to_shift = 12;
1563 }
1564 else
1565 {
1566 to_shift += 12;
1567 }
1568 if (low2 != const0_rtx)
1569 {
9208e4b2 1570 emit_insn (gen_rtx_SET (VOIDmode, op0,
e0d80184
DM		 1571 gen_rtx_ASHIFT (DImode, sub_temp,
1572 GEN_INT (to_shift))));
9208e4b2 1573 emit_insn (gen_rtx_SET (VOIDmode, op0,
e0d80184
DM		 1574 gen_rtx_IOR (DImode, op0, low2)));
1575 sub_temp = op0;
1576 to_shift = 8;
1577 }
1578 else
1579 {
1580 to_shift += 8;
1581 }
9208e4b2 1582 emit_insn (gen_rtx_SET (VOIDmode, op0,
e0d80184
DM		 1583 gen_rtx_ASHIFT (DImode, sub_temp,
1584 GEN_INT (to_shift))));
1585 if (low3 != const0_rtx)
9208e4b2 1586 emit_insn (gen_rtx_SET (VOIDmode, op0,
e0d80184
DM		 1587 gen_rtx_IOR (DImode, op0, low3)));
1588 /* phew... */
1589 }
284d86e9
JC		 1590}
1591
e0d80184 1592/* Analyze a 64-bit constant for certain properties. */
2a01c939
DM		 1593static void analyze_64bit_constant
1594 PROTO((unsigned HOST_WIDE_INT,
1595 unsigned HOST_WIDE_INT,
1596 int *, int *, int *));
1597
e0d80184
DM		 1598static void
1599analyze_64bit_constant (high_bits, low_bits, hbsp, lbsp, abbasp)
2a01c939 1600 unsigned HOST_WIDE_INT high_bits, low_bits;
e0d80184 1601 int *hbsp, *lbsp, *abbasp;
ab835497 1602{
e0d80184
DM		 1603 int lowest_bit_set, highest_bit_set, all_bits_between_are_set;
1604 int i;
ab835497 1605
e0d80184
DM		 1606 lowest_bit_set = highest_bit_set = -1;
1607 i = 0;
1608 do
ab835497 1609 {
e0d80184
DM		 1610 if ((lowest_bit_set == -1)
1611 && ((low_bits >> i) & 1))
1612 lowest_bit_set = i;
1613 if ((highest_bit_set == -1)
1614 && ((high_bits >> (32 - i - 1)) & 1))
1615 highest_bit_set = (64 - i - 1);
1616 }
1617 while (++i < 32
1618 && ((highest_bit_set == -1)
1619 || (lowest_bit_set == -1)));
1620 if (i == 32)
1621 {
1622 i = 0;
1623 do
ab835497 1624 {
e0d80184
DM		 1625 if ((lowest_bit_set == -1)
1626 && ((high_bits >> i) & 1))
1627 lowest_bit_set = i + 32;
1628 if ((highest_bit_set == -1)
1629 && ((low_bits >> (32 - i - 1)) & 1))
1630 highest_bit_set = 32 - i - 1;
ab835497 1631 }
e0d80184
DM		 1632 while (++i < 32
1633 && ((highest_bit_set == -1)
1634 || (lowest_bit_set == -1)));
1635 }
1636 /* If there are no bits set this should have gone out
1637 as one instruction! */
1638 if (lowest_bit_set == -1
1639 || highest_bit_set == -1)
9208e4b2 1640 abort ();
e0d80184
DM		 1641 all_bits_between_are_set = 1;
1642 for (i = lowest_bit_set; i <= highest_bit_set; i++)
1643 {
1644 if (i < 32)
1645 {
1646 if ((low_bits & (1 << i)) != 0)
1647 continue;
1648 }
1649 else
1650 {
1651 if ((high_bits & (1 << (i - 32))) != 0)
1652 continue;
1653 }
1654 all_bits_between_are_set = 0;
1655 break;
ab835497 1656 }
e0d80184
DM		 1657 *hbsp = highest_bit_set;
1658 *lbsp = lowest_bit_set;
1659 *abbasp = all_bits_between_are_set;
ab835497 1660}
6a4bb1fa 1661
2a01c939
DM		 1662static int const64_is_2insns
1663 PROTO((unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT));
1664
e0d80184
DM		 1665static int
1666const64_is_2insns (high_bits, low_bits)
2a01c939 1667 unsigned HOST_WIDE_INT high_bits, low_bits;
e0d80184
DM		 1668{
1669 int highest_bit_set, lowest_bit_set, all_bits_between_are_set;
284d86e9 1670
e0d80184 1671 if (high_bits == 0
2a01c939 1672 || high_bits == 0xffffffff)
e0d80184 1673 return 1;
6a4bb1fa 1674
e0d80184
DM		 1675 analyze_64bit_constant (high_bits, low_bits,
1676 &highest_bit_set, &lowest_bit_set,
1677 &all_bits_between_are_set);
6a4bb1fa 1678
f710f868
DM		 1679 if ((highest_bit_set == 63
1680 || lowest_bit_set == 0)
e0d80184
DM		 1681 && all_bits_between_are_set != 0)
1682 return 1;
6a4bb1fa 1683
9208e4b2
DM		 1684 if ((highest_bit_set - lowest_bit_set) < 21)
1685 return 1;
1686
6a4bb1fa
DE		 1687 return 0;
1688}
1689
2a01c939
DM		 1690static unsigned HOST_WIDE_INT create_simple_focus_bits
1691 PROTO((unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT,
ddf80874 1692 int, int));
2a01c939
DM		 1693
1694static unsigned HOST_WIDE_INT
ddf80874 1695create_simple_focus_bits (high_bits, low_bits, lowest_bit_set, shift)
2a01c939 1696 unsigned HOST_WIDE_INT high_bits, low_bits;
ddf80874 1697 int lowest_bit_set, shift;
ab835497 1698{
f710f868 1699 HOST_WIDE_INT hi, lo;
ab835497 1700
e0d80184
DM		 1701 if (lowest_bit_set < 32)
1702 {
1703 lo = (low_bits >> lowest_bit_set) << shift;
1704 hi = ((high_bits << (32 - lowest_bit_set)) << shift);
1705 }
1706 else
1707 {
1708 lo = 0;
1709 hi = ((high_bits >> (lowest_bit_set - 32)) << shift);
1710 }
1711 if (hi & lo)
9208e4b2 1712 abort ();
e0d80184
DM		 1713 return (hi | lo);
1714}
ab835497 1715
e0d80184
DM		 1716/* Here we are sure to be arch64 and this is an integer constant
1717 being loaded into a register. Emit the most efficient
1718 insn sequence possible. Detection of all the 1-insn cases
1719 has been done already. */
1720void
1721sparc_emit_set_const64 (op0, op1)
1722 rtx op0;
1723 rtx op1;
1724{
2a01c939 1725 unsigned HOST_WIDE_INT high_bits, low_bits;
e0d80184
DM		 1726 int lowest_bit_set, highest_bit_set;
1727 int all_bits_between_are_set;
e0d80184 1728 rtx temp;
ab835497 1729
e0d80184
DM		 1730 /* Sanity check that we know what we are working with. */
1731 if (! TARGET_ARCH64
1732 || GET_CODE (op0) != REG
1733 || (REGNO (op0) >= SPARC_FIRST_FP_REG
1734 && REGNO (op0) <= SPARC_LAST_V9_FP_REG))
9208e4b2 1735 abort ();
95726648 1736
f710f868
DM		 1737 if (reload_in_progress || reload_completed)
1738 temp = op0;
1739 else
1740 temp = gen_reg_rtx (DImode);
1741
e0d80184
DM		 1742 if (GET_CODE (op1) != CONST_DOUBLE
1743 && GET_CODE (op1) != CONST_INT)
1744 {
5f78aa30
JC		 1745 sparc_emit_set_symbolic_const64 (op0, op1, temp);
1746 return;
e0d80184 1747 }
ab835497 1748
e0d80184
DM		 1749 if (GET_CODE (op1) == CONST_DOUBLE)
1750 {
1751#if HOST_BITS_PER_WIDE_INT == 64
2a01c939 1752 high_bits = (CONST_DOUBLE_LOW (op1) >> 32) & 0xffffffff;
e0d80184
DM		 1753 low_bits = CONST_DOUBLE_LOW (op1) & 0xffffffff;
1754#else
1755 high_bits = CONST_DOUBLE_HIGH (op1);
1756 low_bits = CONST_DOUBLE_LOW (op1);
1757#endif
ab835497 1758 }
e0d80184 1759 else
ab835497 1760 {
e0d80184 1761#if HOST_BITS_PER_WIDE_INT == 64
2a01c939 1762 high_bits = ((INTVAL (op1) >> 32) & 0xffffffff);
e0d80184
DM		 1763 low_bits = (INTVAL (op1) & 0xffffffff);
1764#else
1765 high_bits = ((INTVAL (op1) < 0) ?
1766 0xffffffff :
1767 0x00000000);
1768 low_bits = INTVAL (op1);
1769#endif
1770 }
ab835497 1771
e0d80184
DM		 1772 /* low_bits bits 0 --> 31
1773 high_bits bits 32 --> 63 */
ab835497 1774
e0d80184
DM		 1775 analyze_64bit_constant (high_bits, low_bits,
1776 &highest_bit_set, &lowest_bit_set,
1777 &all_bits_between_are_set);
1778
1779 /* First try for a 2-insn sequence. */
1780
1781 /* These situations are preferred because the optimizer can
1782 * do more things with them:
1783 * 1) mov -1, %reg
1784 * sllx %reg, shift, %reg
1785 * 2) mov -1, %reg
1786 * srlx %reg, shift, %reg
1787 * 3) mov some_small_const, %reg
1788 * sllx %reg, shift, %reg
1789 */
1790 if (((highest_bit_set == 63
1791 || lowest_bit_set == 0)
1792 && all_bits_between_are_set != 0)
2a01c939 1793 || ((highest_bit_set - lowest_bit_set) < 12))
e0d80184 1794 {
9208e4b2 1795 HOST_WIDE_INT the_const = -1;
e0d80184
DM		 1796 int shift = lowest_bit_set;
1797
f710f868
DM		 1798 if ((highest_bit_set != 63
1799 && lowest_bit_set != 0)
1800 || all_bits_between_are_set == 0)
ab835497 1801 {
e0d80184 1802 the_const =
9208e4b2 1803 create_simple_focus_bits (high_bits, low_bits,
9208e4b2 1804 lowest_bit_set, 0);
ab835497 1805 }
e0d80184 1806 else if (lowest_bit_set == 0)
9208e4b2 1807 shift = -(63 - highest_bit_set);
e0d80184 1808
f710f868
DM		 1809 if (! SPARC_SIMM13_P (the_const))
1810 abort ();
1811
9208e4b2 1812 emit_insn (gen_safe_SET64 (temp, the_const));
e0d80184 1813 if (shift > 0)
9208e4b2 1814 emit_insn (gen_rtx_SET (VOIDmode,
e0d80184
DM		 1815 op0,
1816 gen_rtx_ASHIFT (DImode,
1817 temp,
1818 GEN_INT (shift))));
1819 else if (shift < 0)
9208e4b2 1820 emit_insn (gen_rtx_SET (VOIDmode,
e0d80184 1821 op0,
9208e4b2 1822 gen_rtx_LSHIFTRT (DImode,
e0d80184
DM		 1823 temp,
1824 GEN_INT (-shift))));
ab835497
RK		 1825 else
1826 abort ();
e0d80184
DM		 1827 return;
1828 }
ab835497 1829
e0d80184
DM		 1830 /* Now a range of 22 or less bits set somewhere.
1831 * 1) sethi %hi(focus_bits), %reg
1832 * sllx %reg, shift, %reg
1833 * 2) sethi %hi(focus_bits), %reg
1834 * srlx %reg, shift, %reg
1835 */
2a01c939 1836 if ((highest_bit_set - lowest_bit_set) < 21)
e0d80184 1837 {
2a01c939 1838 unsigned HOST_WIDE_INT focus_bits =
e0d80184 1839 create_simple_focus_bits (high_bits, low_bits,
ddf80874 1840 lowest_bit_set, 10);
f710f868
DM		 1841
1842 if (! SPARC_SETHI_P (focus_bits))
1843 abort ();
1844
9208e4b2 1845 sparc_emit_set_safe_HIGH64 (temp, focus_bits);
e0d80184 1846
9208e4b2 1847 /* If lowest_bit_set == 10 then a sethi alone could have done it. */
e0d80184 1848 if (lowest_bit_set < 10)
9208e4b2 1849 emit_insn (gen_rtx_SET (VOIDmode,
e0d80184 1850 op0,
9208e4b2 1851 gen_rtx_LSHIFTRT (DImode, temp,
e0d80184 1852 GEN_INT (10 - lowest_bit_set))));
9208e4b2
DM		 1853 else if (lowest_bit_set > 10)
1854 emit_insn (gen_rtx_SET (VOIDmode,
e0d80184
DM		 1855 op0,
1856 gen_rtx_ASHIFT (DImode, temp,
1857 GEN_INT (lowest_bit_set - 10))));
1858 else
9208e4b2 1859 abort ();
e0d80184
DM		 1860 return;
1861 }
1862
1863 /* 1) sethi %hi(low_bits), %reg
1864 * or %reg, %lo(low_bits), %reg
1865 * 2) sethi %hi(~low_bits), %reg
1866 * xor %reg, %lo(-0x400 | (low_bits & 0x3ff)), %reg
1867 */
1868 if (high_bits == 0
2a01c939 1869 || high_bits == 0xffffffff)
5f78aa30
JC		 1870 {
1871 sparc_emit_set_const64_quick1 (op0, temp, low_bits,
1872 (high_bits == 0xffffffff));
1873 return;
1874 }
e0d80184 1875
f710f868
DM		 1876 /* Now, try 3-insn sequences. */
1877
e0d80184
DM		 1878 /* 1) sethi %hi(high_bits), %reg
1879 * or %reg, %lo(high_bits), %reg
1880 * sllx %reg, 32, %reg
1881 */
f710f868 1882 if (low_bits == 0)
5f78aa30 1883 {
f710f868 1884 sparc_emit_set_const64_quick2 (op0, temp, high_bits, 0, 32);
5f78aa30
JC		 1885 return;
1886 }
e0d80184 1887
f710f868
DM		 1888 /* We may be able to do something quick
1889 when the constant is negated, so try that. */
e0d80184
DM		 1890 if (const64_is_2insns ((~high_bits) & 0xffffffff,
1891 (~low_bits) & 0xfffffc00))
1892 {
5108f3e5
DM		 1893 /* NOTE: The trailing bits get XOR'd so we need the
1894 non-negated bits, not the negated ones. */
1895 unsigned HOST_WIDE_INT trailing_bits = low_bits & 0x3ff;
e0d80184
DM		 1896
1897 if ((((~high_bits) & 0xffffffff) == 0
1898 && ((~low_bits) & 0x80000000) == 0)
1899 || (((~high_bits) & 0xffffffff) == 0xffffffff
1900 && ((~low_bits) & 0x80000000) != 0))
ab835497 1901 {
5108f3e5 1902 int fast_int = (~low_bits & 0xffffffff);
e0d80184 1903
5108f3e5
DM		 1904 if ((SPARC_SETHI_P (fast_int)
1905 && (~high_bits & 0xffffffff) == 0)
1906 || SPARC_SIMM13_P (fast_int))
9208e4b2 1907 emit_insn (gen_safe_SET64 (temp, fast_int));
ab835497 1908 else
9208e4b2 1909 sparc_emit_set_const64 (temp, GEN_INT64 (fast_int));
ab835497 1910 }
e0d80184
DM		 1911 else
1912 {
1913 rtx negated_const;
1914#if HOST_BITS_PER_WIDE_INT == 64
1915 negated_const = GEN_INT (((~low_bits) & 0xfffffc00) |
1916 (((HOST_WIDE_INT)((~high_bits) & 0xffffffff))<<32));
1917#else
9208e4b2 1918 negated_const = gen_rtx_CONST_DOUBLE (DImode, const0_rtx,
e0d80184
DM		 1919 (~low_bits) & 0xfffffc00,
1920 (~high_bits) & 0xffffffff);
1921#endif
1922 sparc_emit_set_const64 (temp, negated_const);
1923 }
5108f3e5
DM		 1924
1925 /* If we are XOR'ing with -1, then we should emit a one's complement
1926 instead. This way the combiner will notice logical operations
1927 such as ANDN later on and substitute. */
1928 if (trailing_bits == 0x3ff)
1929 {
1930 emit_insn (gen_rtx_SET (VOIDmode, op0,
1931 gen_rtx_NOT (DImode, temp)));
1932 }
1933 else
1934 {
1935 emit_insn (gen_rtx_SET (VOIDmode,
1936 op0,
1937 gen_safe_XOR64 (temp,
1938 (-0x400 | trailing_bits))));
1939 }
e0d80184 1940 return;
ab835497 1941 }
ab835497 1942
e0d80184
DM		 1943 /* 1) sethi %hi(xxx), %reg
1944 * or %reg, %lo(xxx), %reg
1945 * sllx %reg, yyy, %reg
f710f868
DM		 1946 *
1947 * ??? This is just a generalized version of the low_bits==0
1948 * thing above, FIXME...
e0d80184
DM		 1949 */
1950 if ((highest_bit_set - lowest_bit_set) < 32)
1951 {
f710f868
DM		 1952 unsigned HOST_WIDE_INT focus_bits =
1953 create_simple_focus_bits (high_bits, low_bits,
ddf80874 1954 lowest_bit_set, 0);
ab835497 1955
e0d80184
DM		 1956 /* We can't get here in this state. */
1957 if (highest_bit_set < 32
1958 || lowest_bit_set >= 32)
9208e4b2 1959 abort ();
95726648 1960
e0d80184
DM		 1961 /* So what we know is that the set bits straddle the
1962 middle of the 64-bit word. */
5f78aa30
JC		 1963 sparc_emit_set_const64_quick2 (op0, temp,
1964 focus_bits, 0,
1965 lowest_bit_set);
1966 return;
e0d80184 1967 }
c85f7c16 1968
f710f868
DM		 1969 /* 1) sethi %hi(high_bits), %reg
1970 * or %reg, %lo(high_bits), %reg
1971 * sllx %reg, 32, %reg
1972 * or %reg, low_bits, %reg
1973 */
1974 if (SPARC_SIMM13_P(low_bits)
1975 && ((int)low_bits > 0))
1976 {
1977 sparc_emit_set_const64_quick2 (op0, temp, high_bits, low_bits, 32);
1978 return;
1979 }
1980
e0d80184
DM		 1981 /* The easiest way when all else fails, is full decomposition. */
1982#if 0
1983 printf ("sparc_emit_set_const64: Hard constant [%08lx%08lx] neg[%08lx%08lx]\n",
1984 high_bits, low_bits, ~high_bits, ~low_bits);
1985#endif
1986 sparc_emit_set_const64_longway (op0, temp, high_bits, low_bits);
c85f7c16
JL		 1987}
1988
e0d80184
DM		 1989/* X and Y are two things to compare using CODE. Emit the compare insn and
1990 return the rtx for the cc reg in the proper mode. */
c85f7c16 1991
e0d80184
DM		 1992rtx
1993gen_compare_reg (code, x, y)
1994 enum rtx_code code;
1995 rtx x, y;
c85f7c16 1996{
e0d80184
DM		 1997 enum machine_mode mode = SELECT_CC_MODE (code, x, y);
1998 rtx cc_reg;
c85f7c16 1999
e0d80184
DM		 2000 /* ??? We don't have movcc patterns so we cannot generate pseudo regs for the
2001 fcc regs (cse can't tell they're really call clobbered regs and will
2002 remove a duplicate comparison even if there is an intervening function
2003 call - it will then try to reload the cc reg via an int reg which is why
2004 we need the movcc patterns). It is possible to provide the movcc
2005 patterns by using the ldxfsr/stxfsr v9 insns. I tried it: you need two
2006 registers (say %g1,%g5) and it takes about 6 insns. A better fix would be
2007 to tell cse that CCFPE mode registers (even pseudos) are call
2008 clobbered. */
c85f7c16 2009
e0d80184
DM		 2010 /* ??? This is an experiment. Rather than making changes to cse which may
2011 or may not be easy/clean, we do our own cse. This is possible because
2012 we will generate hard registers. Cse knows they're call clobbered (it
2013 doesn't know the same thing about pseudos). If we guess wrong, no big
2014 deal, but if we win, great! */
c85f7c16 2015
e0d80184
DM		 2016 if (TARGET_V9 && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2017#if 1 /* experiment */
284d86e9 2018 {
e0d80184
DM		 2019 int reg;
2020 /* We cycle through the registers to ensure they're all exercised. */
2021 static int next_fcc_reg = 0;
2022 /* Previous x,y for each fcc reg. */
2023 static rtx prev_args[4][2];
284d86e9 2024
e0d80184
DM		 2025 /* Scan prev_args for x,y. */
2026 for (reg = 0; reg < 4; reg++)
2027 if (prev_args[reg][0] == x && prev_args[reg][1] == y)
2028 break;
2029 if (reg == 4)
2030 {
2031 reg = next_fcc_reg;
2032 prev_args[reg][0] = x;
2033 prev_args[reg][1] = y;
2034 next_fcc_reg = (next_fcc_reg + 1) & 3;
2035 }
2036 cc_reg = gen_rtx_REG (mode, reg + SPARC_FIRST_V9_FCC_REG);
284d86e9 2037 }
e0d80184
DM		 2038#else
2039 cc_reg = gen_reg_rtx (mode);
2040#endif /* ! experiment */
2041 else if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2042 cc_reg = gen_rtx_REG (mode, SPARC_FCC_REG);
2043 else
2044 cc_reg = gen_rtx_REG (mode, SPARC_ICC_REG);
284d86e9 2045
e0d80184
DM		 2046 emit_insn (gen_rtx_SET (VOIDmode, cc_reg,
2047 gen_rtx_COMPARE (mode, x, y)));
c85f7c16 2048
e0d80184
DM		 2049 return cc_reg;
2050}
c85f7c16 2051
e0d80184
DM		 2052/* This function is used for v9 only.
2053 CODE is the code for an Scc's comparison.
2054 OPERANDS[0] is the target of the Scc insn.
2055 OPERANDS[1] is the value we compare against const0_rtx (which hasn't
2056 been generated yet).
c85f7c16 2057
e0d80184 2058 This function is needed to turn
ab835497 2059
e0d80184
DM		 2060 (set (reg:SI 110)
2061 (gt (reg:CCX 100 %icc)
2062 (const_int 0)))
2063 into
2064 (set (reg:SI 110)
2065 (gt:DI (reg:CCX 100 %icc)
2066 (const_int 0)))
2067
2068 IE: The instruction recognizer needs to see the mode of the comparison to
2069 find the right instruction. We could use "gt:DI" right in the
2070 define_expand, but leaving it out allows us to handle DI, SI, etc.
ab835497 2071
e0d80184
DM		 2072 We refer to the global sparc compare operands sparc_compare_op0 and
2073 sparc_compare_op1. */
ab835497
RK		 2074
2075int
e0d80184
DM		 2076gen_v9_scc (compare_code, operands)
2077 enum rtx_code compare_code;
2078 register rtx *operands;
ab835497 2079{
e0d80184 2080 rtx temp, op0, op1;
ab835497 2081
e0d80184
DM		 2082 if (! TARGET_ARCH64
2083 && (GET_MODE (sparc_compare_op0) == DImode
2084 || GET_MODE (operands[0]) == DImode))
2085 return 0;
7e2feebf 2086
e0d80184
DM		 2087 /* Handle the case where operands[0] == sparc_compare_op0.
2088 We "early clobber" the result. */
2089 if (REGNO (operands[0]) == REGNO (sparc_compare_op0))
ab835497 2090 {
e0d80184
DM		 2091 op0 = gen_reg_rtx (GET_MODE (sparc_compare_op0));
2092 emit_move_insn (op0, sparc_compare_op0);
ab835497 2093 }
e0d80184
DM		 2094 else
2095 op0 = sparc_compare_op0;
2096 /* For consistency in the following. */
2097 op1 = sparc_compare_op1;
2098
2099 /* Try to use the movrCC insns. */
2100 if (TARGET_ARCH64
2101 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
2102 && op1 == const0_rtx
2103 && v9_regcmp_p (compare_code))
ab835497 2104 {
e0d80184
DM		 2105 /* Special case for op0 != 0. This can be done with one instruction if
2106 operands[0] == sparc_compare_op0. We don't assume they are equal
2107 now though. */
2108
2109 if (compare_code == NE
2110 && GET_MODE (operands[0]) == DImode
2111 && GET_MODE (op0) == DImode)
ab835497 2112 {
e0d80184
DM		 2113 emit_insn (gen_rtx_SET (VOIDmode, operands[0], op0));
2114 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2115 gen_rtx_IF_THEN_ELSE (DImode,
2116 gen_rtx_fmt_ee (compare_code, DImode,
2117 op0, const0_rtx),
2118 const1_rtx,
2119 operands[0])));
ab835497
RK		 2120 return 1;
2121 }
e0d80184
DM		 2122
2123 emit_insn (gen_rtx_SET (VOIDmode, operands[0], const0_rtx));
2124 if (GET_MODE (op0) != DImode)
ab835497 2125 {
e0d80184
DM		 2126 temp = gen_reg_rtx (DImode);
2127 convert_move (temp, op0, 0);
ab835497 2128 }
e0d80184
DM		 2129 else
2130 temp = op0;
2131 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2132 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]),
2133 gen_rtx_fmt_ee (compare_code, DImode,
2134 temp, const0_rtx),
2135 const1_rtx,
2136 operands[0])));
95726648
DE		 2137 return 1;
2138 }
e0d80184 2139 else
ab835497 2140 {
e0d80184 2141 operands[1] = gen_compare_reg (compare_code, op0, op1);
ab835497 2142
e0d80184 2143 switch (GET_MODE (operands[1]))
ab835497 2144 {
e0d80184
DM		 2145 case CCmode :
2146 case CCXmode :
2147 case CCFPEmode :
2148 case CCFPmode :
2149 break;
2150 default :
2151 abort ();
ab835497 2152 }
e0d80184
DM		 2153 emit_insn (gen_rtx_SET (VOIDmode, operands[0], const0_rtx));
2154 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2155 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]),
2156 gen_rtx_fmt_ee (compare_code,
2157 GET_MODE (operands[1]),
2158 operands[1], const0_rtx),
2159 const1_rtx, operands[0])));
2160 return 1;
ab835497 2161 }
ab835497 2162}
4fb4e4b8 2163
e0d80184
DM		 2164/* Emit a conditional jump insn for the v9 architecture using comparison code
2165 CODE and jump target LABEL.
2166 This function exists to take advantage of the v9 brxx insns. */
ab835497 2167
e0d80184
DM		 2168void
2169emit_v9_brxx_insn (code, op0, label)
2170 enum rtx_code code;
2171 rtx op0, label;
ab835497 2172{
e0d80184
DM		 2173 emit_jump_insn (gen_rtx_SET (VOIDmode,
2174 pc_rtx,
2175 gen_rtx_IF_THEN_ELSE (VOIDmode,
2176 gen_rtx_fmt_ee (code, GET_MODE (op0),
2177 op0, const0_rtx),
2178 gen_rtx_LABEL_REF (VOIDmode, label),
2179 pc_rtx)));
2180}
2181\f
2182/* Return nonzero if a return peephole merging return with
2183 setting of output register is ok. */
2184int
2185leaf_return_peephole_ok ()
2186{
2187 return (actual_fsize == 0);
2188}
284d86e9 2189
e0d80184
DM		 2190/* Return nonzero if TRIAL can go into the function epilogue's
2191 delay slot. SLOT is the slot we are trying to fill. */
ab835497 2192
e0d80184
DM		 2193int
2194eligible_for_epilogue_delay (trial, slot)
2195 rtx trial;
2196 int slot;
2197{
2198 rtx pat, src;
4fb4e4b8 2199
e0d80184
DM		 2200 if (slot >= 1)
2201 return 0;
4fb4e4b8 2202
e0d80184
DM		 2203 if (GET_CODE (trial) != INSN || GET_CODE (PATTERN (trial)) != SET)
2204 return 0;
4fb4e4b8 2205
e0d80184
DM		 2206 if (get_attr_length (trial) != 1)
2207 return 0;
4fb4e4b8 2208
e0d80184
DM		 2209 /* If %g0 is live, there are lots of things we can't handle.
2210 Rather than trying to find them all now, let's punt and only
2211 optimize things as necessary. */
2212 if (TARGET_LIVE_G0)
2213 return 0;
4fb4e4b8 2214
e0d80184
DM		 2215 /* In the case of a true leaf function, anything can go into the delay slot.
2216 A delay slot only exists however if the frame size is zero, otherwise
2217 we will put an insn to adjust the stack after the return. */
2218 if (leaf_function)
4fb4e4b8 2219 {
e0d80184
DM		 2220 if (leaf_return_peephole_ok ())
2221 return ((get_attr_in_uncond_branch_delay (trial)
2222 == IN_BRANCH_DELAY_TRUE));
2223 return 0;
4fb4e4b8 2224 }
4fb4e4b8 2225
e0d80184
DM		 2226 /* If only trivial `restore' insns work, nothing can go in the
2227 delay slot. */
2228 else if (TARGET_BROKEN_SAVERESTORE)
2229 return 0;
795068a4 2230
e0d80184 2231 pat = PATTERN (trial);
795068a4 2232
e0d80184
DM		 2233 /* Otherwise, only operations which can be done in tandem with
2234 a `restore' insn can go into the delay slot. */
2235 if (GET_CODE (SET_DEST (pat)) != REG
2236 || REGNO (SET_DEST (pat)) >= 32
2237 || REGNO (SET_DEST (pat)) < 24)
2238 return 0;
795068a4 2239
e0d80184
DM		 2240 /* The set of insns matched here must agree precisely with the set of
2241 patterns paired with a RETURN in sparc.md. */
795068a4 2242
e0d80184 2243 src = SET_SRC (pat);
795068a4 2244
e0d80184
DM		 2245 /* This matches "*return_[qhs]i". */
2246 if (arith_operand (src, GET_MODE (src)))
2247 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (SImode);
2248
2249 /* This matches "*return_di". */
2250 else if (arith_double_operand (src, GET_MODE (src)))
2251 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
795068a4 2252
e0d80184
DM		 2253 /* This matches "*return_sf_no_fpu". */
2254 else if (! TARGET_FPU && restore_operand (SET_DEST (pat), SFmode)
2255 && register_operand (src, SFmode))
2256 return 1;
f5da225e 2257
e0d80184
DM		 2258 /* This matches "*return_addsi". */
2259 else if (GET_CODE (src) == PLUS
2260 && arith_operand (XEXP (src, 0), SImode)
2261 && arith_operand (XEXP (src, 1), SImode)
2262 && (register_operand (XEXP (src, 0), SImode)
2263 || register_operand (XEXP (src, 1), SImode)))
2264 return 1;
2265
2266 /* This matches "*return_adddi". */
2267 else if (GET_CODE (src) == PLUS
2268 && arith_double_operand (XEXP (src, 0), DImode)
2269 && arith_double_operand (XEXP (src, 1), DImode)
2270 && (register_operand (XEXP (src, 0), DImode)
2271 || register_operand (XEXP (src, 1), DImode)))
795068a4 2272 return 1;
795068a4 2273
795068a4
JW		 2274 return 0;
2275}
2276
e0d80184
DM		 2277static int
2278check_return_regs (x)
2279 rtx x;
ab835497 2280{
e0d80184
DM		 2281 switch (GET_CODE (x))
2282 {
2283 case REG:
2284 return IN_OR_GLOBAL_P (x);
ab835497 2285
e0d80184
DM		 2286 case CONST_INT:
2287 case CONST_DOUBLE:
2288 case CONST:
2289 case SYMBOL_REF:
2290 case LABEL_REF:
2291 return 1;
ab835497 2292
e0d80184
DM		 2293 case SET:
2294 case IOR:
2295 case AND:
2296 case XOR:
2297 case PLUS:
2298 case MINUS:
2299 if (check_return_regs (XEXP (x, 1)) == 0)
2300 return 0;
2301 case NOT:
2302 case NEG:
2303 case MEM:
2304 return check_return_regs (XEXP (x, 0));
2305
2306 default:
2307 return 0;
2308 }
ab835497 2309
e0d80184 2310}
ab835497 2311
e0d80184
DM		 2312/* Return 1 if TRIAL references only in and global registers. */
2313int
2314eligible_for_return_delay (trial)
2315 rtx trial;
2316{
2317 if (GET_CODE (PATTERN (trial)) != SET)
2318 return 0;
ab835497 2319
e0d80184
DM		 2320 return check_return_regs (PATTERN (trial));
2321}
ab835497 2322
e0d80184
DM		 2323int
2324short_branch (uid1, uid2)
2325 int uid1, uid2;
2326{
2327 unsigned int delta = insn_addresses[uid1] - insn_addresses[uid2];
2328 if (delta + 1024 < 2048)
2329 return 1;
2330 /* warning ("long branch, distance %d", delta); */
2331 return 0;
2332}
ab835497 2333
e0d80184
DM		 2334/* Return non-zero if REG is not used after INSN.
2335 We assume REG is a reload reg, and therefore does
2336 not live past labels or calls or jumps. */
2337int
2338reg_unused_after (reg, insn)
2339 rtx reg;
2340 rtx insn;
2341{
2342 enum rtx_code code, prev_code = UNKNOWN;
ab835497 2343
e0d80184 2344 while ((insn = NEXT_INSN (insn)))
61a55e8b 2345 {
e0d80184
DM		 2346 if (prev_code == CALL_INSN && call_used_regs[REGNO (reg)])
2347 return 1;
ab835497 2348
e0d80184
DM		 2349 code = GET_CODE (insn);
2350 if (GET_CODE (insn) == CODE_LABEL)
2351 return 1;
bc961ed7 2352
e0d80184 2353 if (GET_RTX_CLASS (code) == 'i')
61a55e8b 2354 {
e0d80184
DM		 2355 rtx set = single_set (insn);
2356 int in_src = set && reg_overlap_mentioned_p (reg, SET_SRC (set));
2357 if (set && in_src)
2358 return 0;
2359 if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
2360 return 1;
2361 if (set == 0 && reg_overlap_mentioned_p (reg, PATTERN (insn)))
2362 return 0;
61a55e8b 2363 }
e0d80184 2364 prev_code = code;
61a55e8b 2365 }
e0d80184
DM		 2366 return 1;
2367}
2368\f
2369/* The table we use to reference PIC data. */
2370static rtx global_offset_table;
bc961ed7 2371
e0d80184
DM		 2372/* The function we use to get at it. */
2373static rtx get_pc_symbol;
2374static char get_pc_symbol_name[256];
ab835497 2375
e0d80184 2376/* Ensure that we are not using patterns that are not OK with PIC. */
795068a4 2377
e0d80184
DM		 2378int
2379check_pic (i)
2380 int i;
2381{
2382 switch (flag_pic)
ab835497 2383 {
e0d80184
DM		 2384 case 1:
2385 if (GET_CODE (recog_operand[i]) == SYMBOL_REF
2386 || (GET_CODE (recog_operand[i]) == CONST
2387 && ! (GET_CODE (XEXP (recog_operand[i], 0)) == MINUS
2388 && (XEXP (XEXP (recog_operand[i], 0), 0)
2389 == global_offset_table)
2390 && (GET_CODE (XEXP (XEXP (recog_operand[i], 0), 1))
2391 == CONST))))
2392 abort ();
2393 case 2:
2394 default:
2395 return 1;
ab835497 2396 }
ab835497 2397}
795068a4 2398
e0d80184
DM		 2399/* Return true if X is an address which needs a temporary register when
2400 reloaded while generating PIC code. */
795068a4 2401
e0d80184
DM		 2402int
2403pic_address_needs_scratch (x)
2404 rtx x;
795068a4 2405{
e0d80184
DM		 2406 /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */
2407 if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS
2408 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
2409 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2410 && ! SMALL_INT (XEXP (XEXP (x, 0), 1)))
2411 return 1;
795068a4 2412
e0d80184
DM		 2413 return 0;
2414}
795068a4 2415
e0d80184
DM		 2416/* Legitimize PIC addresses. If the address is already position-independent,
2417 we return ORIG. Newly generated position-independent addresses go into a
2418 reg. This is REG if non zero, otherwise we allocate register(s) as
2419 necessary. */
795068a4 2420
e0d80184
DM		 2421rtx
2422legitimize_pic_address (orig, mode, reg)
2423 rtx orig;
2424 enum machine_mode mode ATTRIBUTE_UNUSED;
2425 rtx reg;
2426{
2427 if (GET_CODE (orig) == SYMBOL_REF)
82d6b402 2428 {
e0d80184
DM		 2429 rtx pic_ref, address;
2430 rtx insn;
82d6b402 2431
e0d80184 2432 if (reg == 0)
82d6b402 2433 {
e0d80184
DM		 2434 if (reload_in_progress || reload_completed)
2435 abort ();
2436 else
2437 reg = gen_reg_rtx (Pmode);
82d6b402 2438 }
795068a4 2439
e0d80184 2440 if (flag_pic == 2)
4fb4e4b8 2441 {
e0d80184
DM		 2442 /* If not during reload, allocate another temp reg here for loading
2443 in the address, so that these instructions can be optimized
2444 properly. */
2445 rtx temp_reg = ((reload_in_progress || reload_completed)
2446 ? reg : gen_reg_rtx (Pmode));
2447
2448 /* Must put the SYMBOL_REF inside an UNSPEC here so that cse
2449 won't get confused into thinking that these two instructions
2450 are loading in the true address of the symbol. If in the
2451 future a PIC rtx exists, that should be used instead. */
be3f1ff5
DM		 2452 if (Pmode == SImode)
2453 {
2454 emit_insn (gen_movsi_high_pic (temp_reg, orig));
2455 emit_insn (gen_movsi_lo_sum_pic (temp_reg, temp_reg, orig));
2456 }
2457 else
2458 {
2459 emit_insn (gen_movdi_high_pic (temp_reg, orig));
2460 emit_insn (gen_movdi_lo_sum_pic (temp_reg, temp_reg, orig));
2461 }
e0d80184 2462 address = temp_reg;
4fb4e4b8
DE		 2463 }
2464 else
e0d80184
DM		 2465 address = orig;
2466
2467 pic_ref = gen_rtx_MEM (Pmode,
2468 gen_rtx_PLUS (Pmode,
2469 pic_offset_table_rtx, address));
2470 current_function_uses_pic_offset_table = 1;
2471 RTX_UNCHANGING_P (pic_ref) = 1;
2472 insn = emit_move_insn (reg, pic_ref);
2473 /* Put a REG_EQUAL note on this insn, so that it can be optimized
2474 by loop. */
2475 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, orig,
2476 REG_NOTES (insn));
2477 return reg;
795068a4 2478 }
e0d80184 2479 else if (GET_CODE (orig) == CONST)
795068a4 2480 {
e0d80184 2481 rtx base, offset;
795068a4 2482
e0d80184
DM		 2483 if (GET_CODE (XEXP (orig, 0)) == PLUS
2484 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
2485 return orig;
82d6b402 2486
e0d80184 2487 if (reg == 0)
4fb4e4b8 2488 {
e0d80184
DM		 2489 if (reload_in_progress || reload_completed)
2490 abort ();
2491 else
2492 reg = gen_reg_rtx (Pmode);
4fb4e4b8 2493 }
e0d80184
DM		 2494
2495 if (GET_CODE (XEXP (orig, 0)) == PLUS)
4fb4e4b8 2496 {
e0d80184
DM		 2497 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
2498 offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
2499 base == reg ? 0 : reg);
4fb4e4b8
DE		 2500 }
2501 else
61a66555
JW		 2502 abort ();
2503
e0d80184
DM		 2504 if (GET_CODE (offset) == CONST_INT)
2505 {
2506 if (SMALL_INT (offset))
2507 return plus_constant_for_output (base, INTVAL (offset));
2508 else if (! reload_in_progress && ! reload_completed)
2509 offset = force_reg (Pmode, offset);
2510 else
2511 /* If we reach here, then something is seriously wrong. */
2512 abort ();
2513 }
2514 return gen_rtx_PLUS (Pmode, base, offset);
795068a4 2515 }
e0d80184
DM		 2516 else if (GET_CODE (orig) == LABEL_REF)
2517 /* ??? Why do we do this? */
2518 /* Now movsi_pic_label_ref uses it, but we ought to be checking that
2519 the register is live instead, in case it is eliminated. */
2520 current_function_uses_pic_offset_table = 1;
795068a4 2521
e0d80184
DM		 2522 return orig;
2523}
795068a4 2524
e0d80184
DM		 2525/* Return the RTX for insns to set the PIC register. */
2526
2527static rtx
2528pic_setup_code ()
2529{
2530 rtx seq;
2531
2532 start_sequence ();
2533 emit_insn (gen_get_pc (pic_offset_table_rtx, global_offset_table,
2534 get_pc_symbol));
2535 seq = gen_sequence ();
2536 end_sequence ();
82d6b402 2537
e0d80184
DM		 2538 return seq;
2539}
795068a4 2540
e0d80184 2541/* Emit special PIC prologues and epilogues. */
795068a4 2542
e0d80184
DM		 2543void
2544finalize_pic ()
2545{
2546 /* Labels to get the PC in the prologue of this function. */
2547 int orig_flag_pic = flag_pic;
2548 rtx insn;
4fb4e4b8 2549
e0d80184
DM		 2550 if (current_function_uses_pic_offset_table == 0)
2551 return;
795068a4 2552
e0d80184
DM		 2553 if (! flag_pic)
2554 abort ();
2555
2556 /* If we havn't emitted the special get_pc helper function, do so now. */
2557 if (get_pc_symbol_name[0] == 0)
4fb4e4b8 2558 {
d676da68 2559 int align;
82d6b402 2560
d676da68 2561 ASM_GENERATE_INTERNAL_LABEL (get_pc_symbol_name, "LGETPC", 0);
e0d80184 2562 text_section ();
d676da68
DM		 2563
2564 align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT);
2565 if (align > 0)
2566 ASM_OUTPUT_ALIGN (asm_out_file, align);
e0d80184
DM		 2567 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "LGETPC", 0);
2568 fputs ("\tretl\n\tadd %o7,%l7,%l7\n", asm_out_file);
2569 }
82d6b402 2570
e0d80184
DM		 2571 /* Initialize every time through, since we can't easily
2572 know this to be permanent. */
2573 global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
2574 get_pc_symbol = gen_rtx_SYMBOL_REF (Pmode, get_pc_symbol_name);
2575 flag_pic = 0;
82d6b402 2576
e0d80184 2577 emit_insn_after (pic_setup_code (), get_insns ());
82d6b402 2578
24a43d7b
DM		 2579 /* Insert the code in each nonlocal goto receiver.
2580 If you make changes here or to the nonlocal_goto_receiver
2581 pattern, make sure the unspec_volatile numbers still
2582 match. */
e0d80184
DM		 2583 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
2584 if (GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == UNSPEC_VOLATILE
24a43d7b 2585 && XINT (PATTERN (insn), 1) == 5)
e0d80184 2586 emit_insn_after (pic_setup_code (), insn);
82d6b402 2587
e0d80184 2588 flag_pic = orig_flag_pic;
82d6b402 2589
e0d80184
DM		 2590 /* Need to emit this whether or not we obey regdecls,
2591 since setjmp/longjmp can cause life info to screw up.
2592 ??? In the case where we don't obey regdecls, this is not sufficient
2593 since we may not fall out the bottom. */
2594 emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx));
795068a4 2595}
ab835497 2596\f
e0d80184
DM		 2597/* Return 1 if RTX is a MEM which is known to be aligned to at
2598 least an 8 byte boundary. */
a3ee5899 2599
e0d80184
DM		 2600int
2601mem_min_alignment (mem, desired)
2602 rtx mem;
2603 int desired;
ab835497 2604{
e0d80184
DM		 2605 rtx addr, base, offset;
2606
2607 /* If it's not a MEM we can't accept it. */
2608 if (GET_CODE (mem) != MEM)
2609 return 0;
2610
2611 addr = XEXP (mem, 0);
2612 base = offset = NULL_RTX;
2613 if (GET_CODE (addr) == PLUS)
ab835497 2614 {
e0d80184 2615 if (GET_CODE (XEXP (addr, 0)) == REG)
61a55e8b 2616 {
e0d80184
DM		 2617 base = XEXP (addr, 0);
2618
2619 /* What we are saying here is that if the base
2620 REG is aligned properly, the compiler will make
2621 sure any REG based index upon it will be so
2622 as well. */
2623 if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
2624 offset = XEXP (addr, 1);
61a55e8b 2625 else
e0d80184 2626 offset = const0_rtx;
61a55e8b 2627 }
ab835497 2628 }
e0d80184 2629 else if (GET_CODE (addr) == REG)
ab835497 2630 {
e0d80184
DM		 2631 base = addr;
2632 offset = const0_rtx;
ab835497 2633 }
82d6b402 2634
e0d80184 2635 if (base != NULL_RTX)
795068a4 2636 {
e0d80184
DM		 2637 int regno = REGNO (base);
2638
2639 if (regno != FRAME_POINTER_REGNUM
2640 && regno != STACK_POINTER_REGNUM)
61a55e8b 2641 {
e0d80184
DM		 2642 /* Check if the compiler has recorded some information
2643 about the alignment of the base REG. If reload has
2644 completed, we already matched with proper alignments. */
2645 if (((regno_pointer_align != NULL
2646 && REGNO_POINTER_ALIGN (regno) >= desired)
2647 || reload_completed)
2648 && ((INTVAL (offset) & (desired - 1)) == 0))
2649 return 1;
61a55e8b 2650 }
795068a4 2651 else
e0d80184
DM		 2652 {
2653 if (((INTVAL (offset) - SPARC_STACK_BIAS) & (desired - 1)) == 0)
2654 return 1;
2655 }
795068a4 2656 }
e0d80184
DM		 2657 else if (! TARGET_UNALIGNED_DOUBLES
2658 || CONSTANT_P (addr)
2659 || GET_CODE (addr) == LO_SUM)
795068a4 2660 {
e0d80184
DM		 2661 /* Anything else we know is properly aligned unless TARGET_UNALIGNED_DOUBLES
2662 is true, in which case we can only assume that an access is aligned if
2663 it is to a constant address, or the address involves a LO_SUM. */
2664 return 1;
795068a4 2665 }
e0d80184
DM		 2666
2667 /* An obviously unaligned address. */
2668 return 0;
795068a4 2669}
e0d80184 2670
ab835497 2671\f
61a55e8b
DE		 2672/* Vectors to keep interesting information about registers where it can easily
2673 be got. We use to use the actual mode value as the bit number, but there
2674 are more than 32 modes now. Instead we use two tables: one indexed by
2675 hard register number, and one indexed by mode. */
2676
2677/* The purpose of sparc_mode_class is to shrink the range of modes so that
2678 they all fit (as bit numbers) in a 32 bit word (again). Each real mode is
2679 mapped into one sparc_mode_class mode. */
2680
2681enum sparc_mode_class {
61a55e8b 2682 S_MODE, D_MODE, T_MODE, O_MODE,
c4ce6853
DE		 2683 SF_MODE, DF_MODE, TF_MODE, OF_MODE,
2684 CC_MODE, CCFP_MODE
61a55e8b 2685};
ab835497 2686
61a55e8b
DE		 2687/* Modes for single-word and smaller quantities. */
2688#define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE))
2689
2690/* Modes for double-word and smaller quantities. */
2691#define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
2692
2693/* Modes for quad-word and smaller quantities. */
2694#define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
ab835497 2695
1e4eb8d1
JW		 2696/* Modes for single-float quantities. We must allow any single word or
2697 smaller quantity. This is because the fix/float conversion instructions
2698 take integer inputs/outputs from the float registers. */
2699#define SF_MODES (S_MODES)
ab835497 2700
61a55e8b
DE		 2701/* Modes for double-float and smaller quantities. */
2702#define DF_MODES (S_MODES | D_MODES)
2703
284d86e9 2704#define DF_MODES64 DF_MODES
61a55e8b
DE		 2705
2706/* Modes for double-float only quantities. */
284d86e9 2707#define DF_ONLY_MODES ((1 << (int) DF_MODE) | (1 << (int) D_MODE))
61a55e8b
DE		 2708
2709/* Modes for double-float and larger quantities. */
2710#define DF_UP_MODES (DF_ONLY_MODES | TF_ONLY_MODES)
ab835497 2711
61a55e8b
DE		 2712/* Modes for quad-float only quantities. */
2713#define TF_ONLY_MODES (1 << (int) TF_MODE)
2714
2715/* Modes for quad-float and smaller quantities. */
2716#define TF_MODES (DF_MODES | TF_ONLY_MODES)
2717
61a55e8b 2718#define TF_MODES64 (DF_MODES64 | TF_ONLY_MODES)
ab835497 2719
c4ce6853
DE		 2720/* Modes for condition codes. */
2721#define CC_MODES (1 << (int) CC_MODE)
2722#define CCFP_MODES (1 << (int) CCFP_MODE)
2723
ab835497
RK		 2724/* Value is 1 if register/mode pair is acceptable on sparc.
2725 The funny mixture of D and T modes is because integer operations
2726 do not specially operate on tetra quantities, so non-quad-aligned
2727 registers can hold quadword quantities (except %o4 and %i4 because
c4ce6853 2728 they cross fixed registers). */
ab835497 2729
61a55e8b
DE		 2730/* This points to either the 32 bit or the 64 bit version. */
2731int *hard_regno_mode_classes;
2732
2733static int hard_32bit_mode_classes[] = {
c4ce6853 2734 S_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
ab835497
RK		 2735 T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES,
2736 T_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
2737 T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES,
2738
2739 TF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES,
2740 TF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES,
2741 TF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES,
61a55e8b 2742 TF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES,
a9e27770
DE		 2743
2744 /* FP regs f32 to f63. Only the even numbered registers actually exist,
2745 and none can hold SFmode/SImode values. */
2746 DF_UP_MODES, 0, DF_ONLY_MODES, 0, DF_UP_MODES, 0, DF_ONLY_MODES, 0,
2747 DF_UP_MODES, 0, DF_ONLY_MODES, 0, DF_UP_MODES, 0, DF_ONLY_MODES, 0,
2748 DF_UP_MODES, 0, DF_ONLY_MODES, 0, DF_UP_MODES, 0, DF_ONLY_MODES, 0,
2749 DF_UP_MODES, 0, DF_ONLY_MODES, 0, DF_UP_MODES, 0, DF_ONLY_MODES, 0,
2750
2751 /* %fcc[0123] */
c4ce6853
DE		 2752 CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES,
2753
2754 /* %icc */
2755 CC_MODES
61a55e8b
DE		 2756};
2757
2758static int hard_64bit_mode_classes[] = {
c4ce6853 2759 D_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
61a55e8b
DE		 2760 T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
2761 T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
2762 T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
2763
2764 TF_MODES64, SF_MODES, DF_MODES64, SF_MODES, TF_MODES64, SF_MODES, DF_MODES64, SF_MODES,
2765 TF_MODES64, SF_MODES, DF_MODES64, SF_MODES, TF_MODES64, SF_MODES, DF_MODES64, SF_MODES,
2766 TF_MODES64, SF_MODES, DF_MODES64, SF_MODES, TF_MODES64, SF_MODES, DF_MODES64, SF_MODES,
2767 TF_MODES64, SF_MODES, DF_MODES64, SF_MODES, TF_MODES64, SF_MODES, DF_MODES64, SF_MODES,
2768
a9e27770 2769 /* FP regs f32 to f63. Only the even numbered registers actually exist,
61a55e8b
DE		 2770 and none can hold SFmode/SImode values. */
2771 DF_UP_MODES, 0, DF_ONLY_MODES, 0, DF_UP_MODES, 0, DF_ONLY_MODES, 0,
2772 DF_UP_MODES, 0, DF_ONLY_MODES, 0, DF_UP_MODES, 0, DF_ONLY_MODES, 0,
2773 DF_UP_MODES, 0, DF_ONLY_MODES, 0, DF_UP_MODES, 0, DF_ONLY_MODES, 0,
2774 DF_UP_MODES, 0, DF_ONLY_MODES, 0, DF_UP_MODES, 0, DF_ONLY_MODES, 0,
2775
2776 /* %fcc[0123] */
c4ce6853
DE		 2777 CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES,
2778
2779 /* %icc */
2780 CC_MODES
61a55e8b
DE		 2781};
2782
2783int sparc_mode_class [NUM_MACHINE_MODES];
2784
c4ce6853
DE		 2785enum reg_class sparc_regno_reg_class[FIRST_PSEUDO_REGISTER];
2786
61a55e8b
DE		 2787static void
2788sparc_init_modes ()
2789{
2790 int i;
2791
61a55e8b
DE		 2792 for (i = 0; i < NUM_MACHINE_MODES; i++)
2793 {
2794 switch (GET_MODE_CLASS (i))
2795 {
2796 case MODE_INT:
2797 case MODE_PARTIAL_INT:
2798 case MODE_COMPLEX_INT:
2799 if (GET_MODE_SIZE (i) <= 4)
2800 sparc_mode_class[i] = 1 << (int) S_MODE;
2801 else if (GET_MODE_SIZE (i) == 8)
2802 sparc_mode_class[i] = 1 << (int) D_MODE;
2803 else if (GET_MODE_SIZE (i) == 16)
2804 sparc_mode_class[i] = 1 << (int) T_MODE;
2805 else if (GET_MODE_SIZE (i) == 32)
2806 sparc_mode_class[i] = 1 << (int) O_MODE;
2807 else
2808 sparc_mode_class[i] = 0;
2809 break;
2810 case MODE_FLOAT:
2811 case MODE_COMPLEX_FLOAT:
2812 if (GET_MODE_SIZE (i) <= 4)
2813 sparc_mode_class[i] = 1 << (int) SF_MODE;
2814 else if (GET_MODE_SIZE (i) == 8)
2815 sparc_mode_class[i] = 1 << (int) DF_MODE;
2816 else if (GET_MODE_SIZE (i) == 16)
2817 sparc_mode_class[i] = 1 << (int) TF_MODE;
2818 else if (GET_MODE_SIZE (i) == 32)
2819 sparc_mode_class[i] = 1 << (int) OF_MODE;
2820 else
2821 sparc_mode_class[i] = 0;
2822 break;
2823 case MODE_CC:
2824 default:
2825 /* mode_class hasn't been initialized yet for EXTRA_CC_MODES, so
2826 we must explicitly check for them here. */
2827 if (i == (int) CCFPmode || i == (int) CCFPEmode)
2828 sparc_mode_class[i] = 1 << (int) CCFP_MODE;
2829 else if (i == (int) CCmode || i == (int) CC_NOOVmode
a9e27770 2830 || i == (int) CCXmode || i == (int) CCX_NOOVmode)
c4ce6853 2831 sparc_mode_class[i] = 1 << (int) CC_MODE;
61a55e8b
DE		 2832 else
2833 sparc_mode_class[i] = 0;
2834 break;
2835 }
2836 }
2837
a9e27770 2838 if (TARGET_ARCH64)
61a55e8b
DE		 2839 hard_regno_mode_classes = hard_64bit_mode_classes;
2840 else
2841 hard_regno_mode_classes = hard_32bit_mode_classes;
c4ce6853
DE		 2842
2843 /* Initialize the array used by REGNO_REG_CLASS. */
2844 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
2845 {
284d86e9
JC		 2846 if (i < 16 && TARGET_V8PLUS)
2847 sparc_regno_reg_class[i] = I64_REGS;
2848 else if (i < 32)
c4ce6853
DE		 2849 sparc_regno_reg_class[i] = GENERAL_REGS;
2850 else if (i < 64)
2851 sparc_regno_reg_class[i] = FP_REGS;
2852 else if (i < 96)
2853 sparc_regno_reg_class[i] = EXTRA_FP_REGS;
2854 else if (i < 100)
2855 sparc_regno_reg_class[i] = FPCC_REGS;
2856 else
2857 sparc_regno_reg_class[i] = NO_REGS;
2858 }
61a55e8b 2859}
ab835497 2860\f
61a55e8b
DE		 2861/* Save non call used registers from LOW to HIGH at BASE+OFFSET.
2862 N_REGS is the number of 4-byte regs saved thus far. This applies even to
2863 v9 int regs as it simplifies the code. */
2864
ab835497 2865static int
c53aa195 2866save_regs (file, low, high, base, offset, n_regs, real_offset)
ab835497
RK		 2867 FILE *file;
2868 int low, high;
2869 char *base;
2870 int offset;
61a55e8b 2871 int n_regs;
c53aa195 2872 int real_offset;
ab835497
RK		 2873{
2874 int i;
2875
a9e27770 2876 if (TARGET_ARCH64 && high <= 32)
ab835497 2877 {
61a55e8b
DE		 2878 for (i = low; i < high; i++)
2879 {
2880 if (regs_ever_live[i] && ! call_used_regs[i])
c53aa195 2881 {
e0d80184 2882 fprintf (file, "\tstx\t%s, [%s+%d]\n",
c53aa195 2883 reg_names[i], base, offset + 4 * n_regs);
0021b564 2884 if (dwarf2out_do_frame ())
c53aa195 2885 dwarf2out_reg_save ("", i, real_offset + 4 * n_regs);
c53aa195
JM		 2886 n_regs += 2;
2887 }
61a55e8b 2888 }
ab835497 2889 }
61a55e8b
DE		 2890 else
2891 {
2892 for (i = low; i < high; i += 2)
2893 {
2894 if (regs_ever_live[i] && ! call_used_regs[i])
c53aa195 2895 {
5e9defae
KG		 2896 if (regs_ever_live[i+1] && ! call_used_regs[i+1])
2897 {
e0d80184 2898 fprintf (file, "\tstd\t%s, [%s+%d]\n",
5e9defae
KG		 2899 reg_names[i], base, offset + 4 * n_regs);
2900 if (dwarf2out_do_frame ())
2901 {
2902 char *l = dwarf2out_cfi_label ();
2903 dwarf2out_reg_save (l, i, real_offset + 4 * n_regs);
2904 dwarf2out_reg_save (l, i+1, real_offset + 4 * n_regs + 4);
2905 }
2906 n_regs += 2;
2907 }
2908 else
2909 {
e0d80184 2910 fprintf (file, "\tst\t%s, [%s+%d]\n",
5e9defae
KG		 2911 reg_names[i], base, offset + 4 * n_regs);
2912 if (dwarf2out_do_frame ())
2913 dwarf2out_reg_save ("", i, real_offset + 4 * n_regs);
2914 n_regs += 2;
2915 }
2916 }
2917 else
2918 {
2919 if (regs_ever_live[i+1] && ! call_used_regs[i+1])
2920 {
e0d80184 2921 fprintf (file, "\tst\t%s, [%s+%d]\n",
5e9defae
KG		 2922 reg_names[i+1], base, offset + 4 * n_regs + 4);
2923 if (dwarf2out_do_frame ())
2924 dwarf2out_reg_save ("", i + 1, real_offset + 4 * n_regs + 4);
2925 n_regs += 2;
2926 }
c53aa195 2927 }
61a55e8b
DE		 2928 }
2929 }
2930 return n_regs;
ab835497
RK		 2931}
2932
61a55e8b
DE		 2933/* Restore non call used registers from LOW to HIGH at BASE+OFFSET.
2934
2935 N_REGS is the number of 4-byte regs saved thus far. This applies even to
2936 v9 int regs as it simplifies the code. */
2937
ab835497 2938static int
61a55e8b 2939restore_regs (file, low, high, base, offset, n_regs)
ab835497
RK		 2940 FILE *file;
2941 int low, high;
2942 char *base;
2943 int offset;
61a55e8b 2944 int n_regs;
ab835497
RK		 2945{
2946 int i;
2947
a9e27770 2948 if (TARGET_ARCH64 && high <= 32)
61a55e8b
DE		 2949 {
2950 for (i = low; i < high; i++)
2951 {
2952 if (regs_ever_live[i] && ! call_used_regs[i])
e0d80184 2953 fprintf (file, "\tldx\t[%s+%d], %s\n",
61a55e8b
DE		 2954 base, offset + 4 * n_regs, reg_names[i]),
2955 n_regs += 2;
2956 }
2957 }
2958 else
ab835497 2959 {
61a55e8b
DE		 2960 for (i = low; i < high; i += 2)
2961 {
2962 if (regs_ever_live[i] && ! call_used_regs[i])
2963 if (regs_ever_live[i+1] && ! call_used_regs[i+1])
e0d80184 2964 fprintf (file, "\tldd\t[%s+%d], %s\n",
61a55e8b
DE		 2965 base, offset + 4 * n_regs, reg_names[i]),
2966 n_regs += 2;
2967 else
e0d80184 2968 fprintf (file, "\tld\t[%s+%d],%s\n",
61a55e8b
DE		 2969 base, offset + 4 * n_regs, reg_names[i]),
2970 n_regs += 2;
2971 else if (regs_ever_live[i+1] && ! call_used_regs[i+1])
e0d80184 2972 fprintf (file, "\tld\t[%s+%d],%s\n",
61a55e8b
DE		 2973 base, offset + 4 * n_regs + 4, reg_names[i+1]),
2974 n_regs += 2;
2975 }
ab835497 2976 }
61a55e8b 2977 return n_regs;
ab835497
RK		 2978}
2979
2980/* Static variables we want to share between prologue and epilogue. */
2981
61a55e8b
DE		 2982/* Number of live general or floating point registers needed to be saved
2983 (as 4-byte quantities). This is only done if TARGET_EPILOGUE. */
2984static int num_gfregs;
2985
2986/* Compute the frame size required by the function. This function is called
2987 during the reload pass and also by output_function_prologue(). */
ab835497 2988
ab835497
RK		 2989int
2990compute_frame_size (size, leaf_function)
2991 int size;
2992 int leaf_function;
2993{
61a55e8b 2994 int n_regs = 0, i;
ab835497 2995 int outgoing_args_size = (current_function_outgoing_args_size
4fb4e4b8 2996 + REG_PARM_STACK_SPACE (current_function_decl));
ab835497 2997
61a55e8b 2998 if (TARGET_EPILOGUE)
ab835497 2999 {
61a55e8b
DE		 3000 /* N_REGS is the number of 4-byte regs saved thus far. This applies
3001 even to v9 int regs to be consistent with save_regs/restore_regs. */
3002
a9e27770 3003 if (TARGET_ARCH64)
61a55e8b
DE		 3004 {
3005 for (i = 0; i < 8; i++)
3006 if (regs_ever_live[i] && ! call_used_regs[i])
3007 n_regs += 2;
3008 }
3009 else
3010 {
3011 for (i = 0; i < 8; i += 2)
3012 if ((regs_ever_live[i] && ! call_used_regs[i])
3013 || (regs_ever_live[i+1] && ! call_used_regs[i+1]))
3014 n_regs += 2;
3015 }
3016
3017 for (i = 32; i < (TARGET_V9 ? 96 : 64); i += 2)
ab835497
RK		 3018 if ((regs_ever_live[i] && ! call_used_regs[i])
3019 || (regs_ever_live[i+1] && ! call_used_regs[i+1]))
61a55e8b 3020 n_regs += 2;
ab835497
RK		 3021 }
3022
3023 /* Set up values for use in `function_epilogue'. */
61a55e8b 3024 num_gfregs = n_regs;
ab835497 3025
61a55e8b
DE		 3026 if (leaf_function && n_regs == 0
3027 && size == 0 && current_function_outgoing_args_size == 0)
3028 {
3029 actual_fsize = apparent_fsize = 0;
3030 }
3031 else
3032 {
3033 /* We subtract STARTING_FRAME_OFFSET, remember it's negative.
3034 The stack bias (if any) is taken out to undo its effects. */
3035 apparent_fsize = (size - STARTING_FRAME_OFFSET + SPARC_STACK_BIAS + 7) & -8;
3036 apparent_fsize += n_regs * 4;
3037 actual_fsize = apparent_fsize + ((outgoing_args_size + 7) & -8);
3038 }
ab835497
RK		 3039
3040 /* Make sure nothing can clobber our register windows.
3041 If a SAVE must be done, or there is a stack-local variable,
61a55e8b 3042 the register window area must be allocated.
4fb4e4b8 3043 ??? For v8 we apparently need an additional 8 bytes of reserved space. */
ab835497 3044 if (leaf_function == 0 || size > 0)
4fb4e4b8 3045 actual_fsize += (16 * UNITS_PER_WORD) + (TARGET_ARCH64 ? 0 : 8);
ab835497 3046
61a55e8b
DE		 3047 return SPARC_STACK_ALIGN (actual_fsize);
3048}
3049
3050/* Build a (32 bit) big number in a register. */
86735b02 3051/* ??? We may be able to use the set macro here too. */
61a55e8b
DE		 3052
3053static void
3054build_big_number (file, num, reg)
3055 FILE *file;
3056 int num;
3057 char *reg;
3058{
a9e27770 3059 if (num >= 0 || ! TARGET_ARCH64)
61a55e8b 3060 {
e0d80184 3061 fprintf (file, "\tsethi\t%%hi(%d), %s\n", num, reg);
61a55e8b 3062 if ((num & 0x3ff) != 0)
e0d80184 3063 fprintf (file, "\tor\t%s, %%lo(%d), %s\n", reg, num, reg);
61a55e8b 3064 }
a9e27770 3065 else /* num < 0 && TARGET_ARCH64 */
61a55e8b
DE		 3066 {
3067 /* Sethi does not sign extend, so we must use a little trickery
3068 to use it for negative numbers. Invert the constant before
3069 loading it in, then use xor immediate to invert the loaded bits
3070 (along with the upper 32 bits) to the desired constant. This
3071 works because the sethi and immediate fields overlap. */
3072 int asize = num;
3073 int inv = ~asize;
3074 int low = -0x400 + (asize & 0x3FF);
3075
e0d80184 3076 fprintf (file, "\tsethi\t%%hi(%d), %s\n\txor\t%s, %d, %s\n",
61a55e8b
DE		 3077 inv, reg, reg, low, reg);
3078 }
ab835497
RK		 3079}
3080
915f619f
JW		 3081/* Output code for the function prologue. */
3082
ab835497
RK		 3083void
3084output_function_prologue (file, size, leaf_function)
3085 FILE *file;
3086 int size;
915f619f 3087 int leaf_function;
ab835497 3088{
915f619f
JW		 3089 /* Need to use actual_fsize, since we are also allocating
3090 space for our callee (and our own register save area). */
ab835497
RK		 3091 actual_fsize = compute_frame_size (size, leaf_function);
3092
61a55e8b
DE		 3093 if (leaf_function)
3094 {
3095 frame_base_name = "%sp";
3096 frame_base_offset = actual_fsize + SPARC_STACK_BIAS;
3097 }
3098 else
3099 {
3100 frame_base_name = "%fp";
3101 frame_base_offset = SPARC_STACK_BIAS;
3102 }
3103
c6aa9ce1 3104 /* This is only for the human reader. */
bf62bbf1 3105 fprintf (file, "\t%s#PROLOGUE# 0\n", ASM_COMMENT_START);
c6aa9ce1 3106
915f619f
JW		 3107 if (actual_fsize == 0)
3108 /* do nothing. */ ;
3592ea0d 3109 else if (! leaf_function && ! TARGET_BROKEN_SAVERESTORE)
ab835497 3110 {
3592ea0d 3111 if (actual_fsize <= 4096)
e0d80184 3112 fprintf (file, "\tsave\t%%sp, -%d, %%sp\n", actual_fsize);
3592ea0d 3113 else if (actual_fsize <= 8192)
915f619f 3114 {
e0d80184
DM		 3115 fprintf (file, "\tsave\t%%sp, -4096, %%sp\n");
3116 fprintf (file, "\tadd\t%%sp, -%d, %%sp\n", actual_fsize - 4096);
915f619f
JW		 3117 }
3118 else
3119 {
3592ea0d 3120 build_big_number (file, -actual_fsize, "%g1");
e0d80184 3121 fprintf (file, "\tsave\t%%sp, %%g1, %%sp\n");
915f619f 3122 }
ab835497 3123 }
5f4241d5 3124 else if (! leaf_function && TARGET_BROKEN_SAVERESTORE)
ab835497 3125 {
5f4241d5 3126 /* We assume the environment will properly handle or otherwise avoid
956d6950
JL		 3127 trouble associated with an interrupt occurring after the `save' or
3128 trap occurring during it. */
5f4241d5 3129 fprintf (file, "\tsave\n");
3592ea0d 3130
5f4241d5 3131 if (actual_fsize <= 4096)
e0d80184 3132 fprintf (file, "\tadd\t%%fp, -%d, %%sp\n", actual_fsize);
5f4241d5
DE		 3133 else if (actual_fsize <= 8192)
3134 {
e0d80184
DM		 3135 fprintf (file, "\tadd\t%%fp, -4096, %%sp\n");
3136 fprintf (file, "\tadd\t%%fp, -%d, %%sp\n", actual_fsize - 4096);
5f4241d5
DE		 3137 }
3138 else
3139 {
3140 build_big_number (file, -actual_fsize, "%g1");
e0d80184 3141 fprintf (file, "\tadd\t%%fp, %%g1, %%sp\n");
5f4241d5
DE		 3142 }
3143 }
3144 else /* leaf function */
3145 {
3592ea0d 3146 if (actual_fsize <= 4096)
e0d80184 3147 fprintf (file, "\tadd\t%%sp, -%d, %%sp\n", actual_fsize);
3592ea0d
DE		 3148 else if (actual_fsize <= 8192)
3149 {
e0d80184
DM		 3150 fprintf (file, "\tadd\t%%sp, -4096, %%sp\n");
3151 fprintf (file, "\tadd\t%%sp, -%d, %%sp\n", actual_fsize - 4096);
3592ea0d 3152 }
915f619f 3153 else
3592ea0d
DE		 3154 {
3155 build_big_number (file, -actual_fsize, "%g1");
e0d80184 3156 fprintf (file, "\tadd\t%%sp, %%g1, %%sp\n");
3592ea0d 3157 }
ab835497
RK		 3158 }
3159
0021b564 3160 if (dwarf2out_do_frame () && actual_fsize)
c53aa195 3161 {
96987e96 3162 char *label = dwarf2out_cfi_label ();
c53aa195
JM		 3163
3164 /* The canonical frame address refers to the top of the frame. */
3165 dwarf2out_def_cfa (label, (leaf_function ? STACK_POINTER_REGNUM
3166 : FRAME_POINTER_REGNUM),
3167 frame_base_offset);
3168
3169 if (! leaf_function)
3170 {
3171 /* Note the register window save. This tells the unwinder that
3172 it needs to restore the window registers from the previous
3173 frame's window save area at 0(cfa). */
3174 dwarf2out_window_save (label);
3175
3176 /* The return address (-8) is now in %i7. */
3177 dwarf2out_return_reg (label, 31);
3178 }
3179 }
c53aa195 3180
ab835497
RK		 3181 /* If doing anything with PIC, do it now. */
3182 if (! flag_pic)
bf62bbf1 3183 fprintf (file, "\t%s#PROLOGUE# 1\n", ASM_COMMENT_START);
ab835497 3184
61a55e8b
DE		 3185 /* Call saved registers are saved just above the outgoing argument area. */
3186 if (num_gfregs)
ab835497 3187 {
c53aa195 3188 int offset, real_offset, n_regs;
61a55e8b 3189 char *base;
ab835497 3190
84e884e9
JM		 3191 real_offset = -apparent_fsize;
3192 offset = -apparent_fsize + frame_base_offset;
61a55e8b
DE		 3193 if (offset < -4096 || offset + num_gfregs * 4 > 4096)
3194 {
3195 /* ??? This might be optimized a little as %g1 might already have a
3196 value close enough that a single add insn will do. */
3197 /* ??? Although, all of this is probably only a temporary fix
3198 because if %g1 can hold a function result, then
3199 output_function_epilogue will lose (the result will get
3200 clobbered). */
3201 build_big_number (file, offset, "%g1");
e0d80184 3202 fprintf (file, "\tadd\t%s, %%g1, %%g1\n", frame_base_name);
61a55e8b
DE		 3203 base = "%g1";
3204 offset = 0;
3205 }
ab835497 3206 else
61a55e8b
DE		 3207 {
3208 base = frame_base_name;
3209 }
ab835497 3210
db3d4438 3211 n_regs = 0;
ab835497 3212 if (TARGET_EPILOGUE && ! leaf_function)
61a55e8b 3213 /* ??? Originally saved regs 0-15 here. */
c53aa195 3214 n_regs = save_regs (file, 0, 8, base, offset, 0, real_offset);
ab835497 3215 else if (leaf_function)
61a55e8b 3216 /* ??? Originally saved regs 0-31 here. */
c53aa195 3217 n_regs = save_regs (file, 0, 8, base, offset, 0, real_offset);
ab835497 3218 if (TARGET_EPILOGUE)
c53aa195
JM		 3219 save_regs (file, 32, TARGET_V9 ? 96 : 64, base, offset, n_regs,
3220 real_offset);
ab835497
RK		 3221 }
3222
ab835497
RK		 3223 leaf_label = 0;
3224 if (leaf_function && actual_fsize != 0)
3225 {
3226 /* warning ("leaf procedure with frame size %d", actual_fsize); */
3227 if (! TARGET_EPILOGUE)
3228 leaf_label = gen_label_rtx ();
3229 }
3230}
3231
915f619f
JW		 3232/* Output code for the function epilogue. */
3233
ab835497 3234void
ef8200df 3235output_function_epilogue (file, size, leaf_function)
ab835497 3236 FILE *file;
db3d4438 3237 int size ATTRIBUTE_UNUSED;
ef8200df 3238 int leaf_function;
ab835497 3239{
ab835497
RK		 3240 char *ret;
3241
3242 if (leaf_label)
3243 {
ab835497
RK		 3244 emit_label_after (leaf_label, get_last_insn ());
3245 final_scan_insn (get_last_insn (), file, 0, 0, 1);
3246 }
3247
b69649e4
RK		 3248#ifdef FUNCTION_BLOCK_PROFILER_EXIT
3249 else if (profile_block_flag == 2)
3250 {
3251 FUNCTION_BLOCK_PROFILER_EXIT(file);
3252 }
3253#endif
3254
bfd6bc60
JC		 3255 else if (current_function_epilogue_delay_list == 0)
3256 {
e0d80184
DM		 3257 /* If code does not drop into the epilogue, we need
3258 do nothing except output pending case vectors. */
bfd6bc60
JC		 3259 rtx insn = get_last_insn ();
3260 if (GET_CODE (insn) == NOTE)
3261 insn = prev_nonnote_insn (insn);
3262 if (insn && GET_CODE (insn) == BARRIER)
e0d80184 3263 goto output_vectors;
bfd6bc60
JC		 3264 }
3265
61a55e8b
DE		 3266 /* Restore any call saved registers. */
3267 if (num_gfregs)
ab835497 3268 {
61a55e8b
DE		 3269 int offset, n_regs;
3270 char *base;
ab835497 3271
61a55e8b
DE		 3272 offset = -apparent_fsize + frame_base_offset;
3273 if (offset < -4096 || offset + num_gfregs * 4 > 4096 - 8 /*double*/)
3274 {
3275 build_big_number (file, offset, "%g1");
e0d80184 3276 fprintf (file, "\tadd\t%s, %%g1, %%g1\n", frame_base_name);
61a55e8b
DE		 3277 base = "%g1";
3278 offset = 0;
3279 }
ab835497 3280 else
61a55e8b
DE		 3281 {
3282 base = frame_base_name;
3283 }
ab835497 3284
db3d4438 3285 n_regs = 0;
ab835497 3286 if (TARGET_EPILOGUE && ! leaf_function)
61a55e8b
DE		 3287 /* ??? Originally saved regs 0-15 here. */
3288 n_regs = restore_regs (file, 0, 8, base, offset, 0);
ab835497 3289 else if (leaf_function)
61a55e8b
DE		 3290 /* ??? Originally saved regs 0-31 here. */
3291 n_regs = restore_regs (file, 0, 8, base, offset, 0);
ab835497 3292 if (TARGET_EPILOGUE)
61a55e8b 3293 restore_regs (file, 32, TARGET_V9 ? 96 : 64, base, offset, n_regs);
ab835497
RK		 3294 }
3295
3296 /* Work out how to skip the caller's unimp instruction if required. */
3297 if (leaf_function)
e0d80184 3298 ret = (SKIP_CALLERS_UNIMP_P ? "jmp\t%o7+12" : "retl");
ab835497 3299 else
e0d80184 3300 ret = (SKIP_CALLERS_UNIMP_P ? "jmp\t%i7+12" : "ret");
ab835497 3301
ef8200df 3302 if (TARGET_EPILOGUE || leaf_label)
ab835497 3303 {
ef8200df
JW		 3304 int old_target_epilogue = TARGET_EPILOGUE;
3305 target_flags &= ~old_target_epilogue;
ab835497 3306
ef8200df
JW		 3307 if (! leaf_function)
3308 {
3309 /* If we wound up with things in our delay slot, flush them here. */
3310 if (current_function_epilogue_delay_list)
ab835497 3311 {
254110c2 3312 rtx insn = emit_jump_insn_after (gen_rtx_RETURN (VOIDmode),
ef8200df 3313 get_last_insn ());
254110c2 3314 PATTERN (insn) = gen_rtx_PARALLEL (VOIDmode,
ef8200df
JW		 3315 gen_rtvec (2,
3316 PATTERN (XEXP (current_function_epilogue_delay_list, 0)),
3317 PATTERN (insn)));
3318 final_scan_insn (insn, file, 1, 0, 1);
ab835497 3319 }
284d86e9 3320 else if (TARGET_V9 && ! SKIP_CALLERS_UNIMP_P)
e0d80184 3321 fputs ("\treturn\t%i7+8\n\tnop\n", file);
ab835497 3322 else
ef8200df
JW		 3323 fprintf (file, "\t%s\n\trestore\n", ret);
3324 }
915f619f
JW		 3325 /* All of the following cases are for leaf functions. */
3326 else if (current_function_epilogue_delay_list)
ef8200df 3327 {
915f619f
JW		 3328 /* eligible_for_epilogue_delay_slot ensures that if this is a
3329 leaf function, then we will only have insn in the delay slot
3330 if the frame size is zero, thus no adjust for the stack is
3331 needed here. */
3332 if (actual_fsize != 0)
ef8200df 3333 abort ();
915f619f
JW		 3334 fprintf (file, "\t%s\n", ret);
3335 final_scan_insn (XEXP (current_function_epilogue_delay_list, 0),
3336 file, 1, 0, 1);
ab835497 3337 }
9bb7ffda
JW		 3338 /* Output 'nop' instead of 'sub %sp,-0,%sp' when no frame, so as to
3339 avoid generating confusing assembly language output. */
3340 else if (actual_fsize == 0)
3341 fprintf (file, "\t%s\n\tnop\n", ret);
915f619f 3342 else if (actual_fsize <= 4096)
e0d80184 3343 fprintf (file, "\t%s\n\tsub\t%%sp, -%d, %%sp\n", ret, actual_fsize);
915f619f 3344 else if (actual_fsize <= 8192)
e0d80184 3345 fprintf (file, "\tsub\t%%sp, -4096, %%sp\n\t%s\n\tsub\t%%sp, -%d, %%sp\n",
915f619f
JW		 3346 ret, actual_fsize - 4096);
3347 else if ((actual_fsize & 0x3ff) == 0)
e0d80184 3348 fprintf (file, "\tsethi\t%%hi(%d), %%g1\n\t%s\n\tadd\t%%sp, %%g1, %%sp\n",
915f619f
JW		 3349 actual_fsize, ret);
3350 else
e0d80184 3351 fprintf (file, "\tsethi\t%%hi(%d), %%g1\n\tor\t%%g1, %%lo(%d), %%g1\n\t%s\n\tadd\t%%sp, %%g1, %%sp\n",
915f619f 3352 actual_fsize, actual_fsize, ret);
ef8200df 3353 target_flags |= old_target_epilogue;
ab835497 3354 }
e0d80184
DM		 3355
3356 output_vectors:
3357 sparc_output_deferred_case_vectors ();
ab835497 3358}
4fb4e4b8
DE		 3359\f
3360/* Functions for handling argument passing.
3361
3362 For v8 the first six args are normally in registers and the rest are
3363 pushed. Any arg that starts within the first 6 words is at least
3364 partially passed in a register unless its data type forbids.
3365
3366 For v9, the argument registers are laid out as an array of 16 elements
3367 and arguments are added sequentially. The first 6 int args and up to the
3368 first 16 fp args (depending on size) are passed in regs.
3369
3370 Slot Stack Integral Float Float in structure Double Long Double
3371 ---- ----- -------- ----- ------------------ ------ -----------
3372 15 [SP+248] %f31 %f30,%f31 %d30
3373 14 [SP+240] %f29 %f28,%f29 %d28 %q28
3374 13 [SP+232] %f27 %f26,%f27 %d26
3375 12 [SP+224] %f25 %f24,%f25 %d24 %q24
3376 11 [SP+216] %f23 %f22,%f23 %d22
3377 10 [SP+208] %f21 %f20,%f21 %d20 %q20
3378 9 [SP+200] %f19 %f18,%f19 %d18
3379 8 [SP+192] %f17 %f16,%f17 %d16 %q16
3380 7 [SP+184] %f15 %f14,%f15 %d14
3381 6 [SP+176] %f13 %f12,%f13 %d12 %q12
3382 5 [SP+168] %o5 %f11 %f10,%f11 %d10
3383 4 [SP+160] %o4 %f9 %f8,%f9 %d8 %q8
3384 3 [SP+152] %o3 %f7 %f6,%f7 %d6
3385 2 [SP+144] %o2 %f5 %f4,%f5 %d4 %q4
3386 1 [SP+136] %o1 %f3 %f2,%f3 %d2
3387 0 [SP+128] %o0 %f1 %f0,%f1 %d0 %q0
3388
3389 Here SP = %sp if -mno-stack-bias or %sp+stack_bias otherwise.
3390
3391 Integral arguments are always passed as 64 bit quantities appropriately
3392 extended.
3393
3394 Passing of floating point values is handled as follows.
3395 If a prototype is in scope:
3396 If the value is in a named argument (i.e. not a stdarg function or a
3397 value not part of the `...') then the value is passed in the appropriate
3398 fp reg.
3399 If the value is part of the `...' and is passed in one of the first 6
3400 slots then the value is passed in the appropriate int reg.
3401 If the value is part of the `...' and is not passed in one of the first 6
3402 slots then the value is passed in memory.
3403 If a prototype is not in scope:
3404 If the value is one of the first 6 arguments the value is passed in the
3405 appropriate integer reg and the appropriate fp reg.
3406 If the value is not one of the first 6 arguments the value is passed in
3407 the appropriate fp reg and in memory.
3408 */
3409
3410/* Maximum number of int regs for args. */
3411#define SPARC_INT_ARG_MAX 6
3412/* Maximum number of fp regs for args. */
3413#define SPARC_FP_ARG_MAX 16
3414
3415#define ROUND_ADVANCE(SIZE) (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
3416
3417/* Handle the INIT_CUMULATIVE_ARGS macro.
3418 Initialize a variable CUM of type CUMULATIVE_ARGS
3419 for a call to a function whose data type is FNTYPE.
3420 For a library call, FNTYPE is 0. */
3ea1fdd3 3421
4fb4e4b8
DE		 3422void
3423init_cumulative_args (cum, fntype, libname, indirect)
3424 CUMULATIVE_ARGS *cum;
db3d4438
DM		 3425 tree fntype;
3426 tree libname ATTRIBUTE_UNUSED;
3427 int indirect ATTRIBUTE_UNUSED;
4fb4e4b8
DE		 3428{
3429 cum->words = 0;
3430 cum->prototype_p = fntype && TYPE_ARG_TYPES (fntype);
3431 cum->libcall_p = fntype == 0;
3432}
61a55e8b 3433
4fb4e4b8
DE		 3434/* Compute the slot number to pass an argument in.
3435 Returns the slot number or -1 if passing on the stack.
3436
3437 CUM is a variable of type CUMULATIVE_ARGS which gives info about
3438 the preceding args and about the function being called.
3439 MODE is the argument's machine mode.
3440 TYPE is the data type of the argument (as a tree).
3441 This is null for libcalls where that information may
3442 not be available.
3443 NAMED is nonzero if this argument is a named parameter
3444 (otherwise it is an extra parameter matching an ellipsis).
3445 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG.
3446 *PREGNO records the register number to use if scalar type.
3447 *PPADDING records the amount of padding needed in words. */
3448
3449static int
3450function_arg_slotno (cum, mode, type, named, incoming_p, pregno, ppadding)
3451 const CUMULATIVE_ARGS *cum;
3452 enum machine_mode mode;
3453 tree type;
3454 int named;
3455 int incoming_p;
3456 int *pregno;
3457 int *ppadding;
3458{
3459 int regbase = (incoming_p
3460 ? SPARC_INCOMING_INT_ARG_FIRST
3461 : SPARC_OUTGOING_INT_ARG_FIRST);
3462 int slotno = cum->words;
3463 int regno;
3464
3465 *ppadding = 0;
3466
3467 if (type != 0 && TREE_ADDRESSABLE (type))
3468 return -1;
3469 if (TARGET_ARCH32
3470 && type != 0 && mode == BLKmode
3471 && TYPE_ALIGN (type) % PARM_BOUNDARY != 0)
3472 return -1;
3473
3474 switch (mode)
3475 {
3476 case VOIDmode :
3477 /* MODE is VOIDmode when generating the actual call.
3478 See emit_call_1. */
3479 return -1;
3480
3481 case QImode : case CQImode :
3482 case HImode : case CHImode :
3483 case SImode : case CSImode :
3484 case DImode : case CDImode :
3485 if (slotno >= SPARC_INT_ARG_MAX)
3486 return -1;
3487 regno = regbase + slotno;
3488 break;
3489
3490 case SFmode : case SCmode :
3491 case DFmode : case DCmode :
3492 case TFmode : case TCmode :
3493 if (TARGET_ARCH32)
3494 {
3495 if (slotno >= SPARC_INT_ARG_MAX)
3496 return -1;
3497 regno = regbase + slotno;
3498 }
3499 else
3500 {
3501 if ((mode == TFmode || mode == TCmode)
3502 && (slotno & 1) != 0)
3503 slotno++, *ppadding = 1;
3504 if (TARGET_FPU && named)
3505 {
3506 if (slotno >= SPARC_FP_ARG_MAX)
82d6b402 3507 return -1;
4fb4e4b8
DE		 3508 regno = SPARC_FP_ARG_FIRST + slotno * 2;
3509 if (mode == SFmode)
3510 regno++;
3511 }
3512 else
3513 {
3514 if (slotno >= SPARC_INT_ARG_MAX)
3515 return -1;
3516 regno = regbase + slotno;
3517 }
3518 }
3519 break;
3520
3521 case BLKmode :
3522 /* For sparc64, objects requiring 16 byte alignment get it. */
3523 if (TARGET_ARCH64)
3524 {
3525 if (type && TYPE_ALIGN (type) == 128 && (slotno & 1) != 0)
3526 slotno++, *ppadding = 1;
3527 }
3528
3529 if (TARGET_ARCH32
5e9defae 3530 || (type && TREE_CODE (type) == UNION_TYPE))
4fb4e4b8
DE		 3531 {
3532 if (slotno >= SPARC_INT_ARG_MAX)
3533 return -1;
3534 regno = regbase + slotno;
3535 }
3536 else
3537 {
3538 tree field;
3539 int intregs_p = 0, fpregs_p = 0;
3540 /* The ABI obviously doesn't specify how packed
3541 structures are passed. These are defined to be passed
3542 in int regs if possible, otherwise memory. */
3543 int packed_p = 0;
3544
3545 /* First see what kinds of registers we need. */
3546 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
3547 {
3548 if (TREE_CODE (field) == FIELD_DECL)
3549 {
3550 if (TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
3551 && TARGET_FPU)
3552 fpregs_p = 1;
3553 else
3554 intregs_p = 1;
3555 if (DECL_PACKED (field))
3556 packed_p = 1;
3557 }
3558 }
3559 if (packed_p || !named)
3560 fpregs_p = 0, intregs_p = 1;
3561
3562 /* If all arg slots are filled, then must pass on stack. */
3563 if (fpregs_p && slotno >= SPARC_FP_ARG_MAX)
3564 return -1;
3565 /* If there are only int args and all int arg slots are filled,
3566 then must pass on stack. */
3567 if (!fpregs_p && intregs_p && slotno >= SPARC_INT_ARG_MAX)
3568 return -1;
3569 /* Note that even if all int arg slots are filled, fp members may
3570 still be passed in regs if such regs are available.
3571 *PREGNO isn't set because there may be more than one, it's up
3572 to the caller to compute them. */
3573 return slotno;
3574 }
3575 break;
3576
3577 default :
3578 abort ();
3579 }
3580
3581 *pregno = regno;
3582 return slotno;
3583}
3584
82d6b402
RH		 3585/* Handle recursive register counting for structure field layout. */
3586
3587struct function_arg_record_value_parms
3588{
3589 rtx ret;
3590 int slotno, named, regbase;
3591 int nregs, intoffset;
3592};
3593
2a01c939
DM		 3594static void function_arg_record_value_3
3595 PROTO((int, struct function_arg_record_value_parms *));
3596static void function_arg_record_value_2
3597 PROTO((tree, int, struct function_arg_record_value_parms *));
3598static rtx function_arg_record_value
3599 PROTO((tree, enum machine_mode, int, int, int));
3600
82d6b402
RH		 3601static void
3602function_arg_record_value_1 (type, startbitpos, parms)
3603 tree type;
3604 int startbitpos;
3605 struct function_arg_record_value_parms *parms;
3606{
3607 tree field;
3608
3609 /* The ABI obviously doesn't specify how packed structures are
3610 passed. These are defined to be passed in int regs if possible,
3611 otherwise memory. */
3612 int packed_p = 0;
3613
3614 /* We need to compute how many registers are needed so we can
3615 allocate the PARALLEL but before we can do that we need to know
3616 whether there are any packed fields. If there are, int regs are
3617 used regardless of whether there are fp values present. */
3618 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
3619 {
3620 if (TREE_CODE (field) == FIELD_DECL && DECL_PACKED (field))
3621 {
3622 packed_p = 1;
3623 break;
3624 }
3625 }
3626
3627 /* Compute how many registers we need. */
3628 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
3629 {
3630 if (TREE_CODE (field) == FIELD_DECL)
3631 {
3632 int bitpos = startbitpos;
3633 if (DECL_FIELD_BITPOS (field))
3634 bitpos += TREE_INT_CST_LOW (DECL_FIELD_BITPOS (field));
3635 /* ??? FIXME: else assume zero offset. */
3636
3637 if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE)
3638 {
3639 function_arg_record_value_1 (TREE_TYPE (field), bitpos, parms);
3640 }
3641 else if (TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
3642 && TARGET_FPU
3643 && ! packed_p
3644 && parms->named)
3645 {
3646 if (parms->intoffset != -1)
3647 {
3648 int intslots, this_slotno;
3649
3650 intslots = (bitpos - parms->intoffset + BITS_PER_WORD - 1)
3651 / BITS_PER_WORD;
3652 this_slotno = parms->slotno + parms->intoffset
3653 / BITS_PER_WORD;
3654
3655 intslots = MIN (intslots, SPARC_INT_ARG_MAX - this_slotno);
3656 intslots = MAX (intslots, 0);
3657 parms->nregs += intslots;
3658 parms->intoffset = -1;
3659 }
3660
3661 /* There's no need to check this_slotno < SPARC_FP_ARG MAX.
3662 If it wasn't true we wouldn't be here. */
3663 parms->nregs += 1;
3664 }
3665 else
3666 {
3667 if (parms->intoffset == -1)
3668 parms->intoffset = bitpos;
3669 }
3670 }
3671 }
3672}
3673
3674/* Handle recursive structure field register assignment. */
3675
3676static void
3677function_arg_record_value_3 (bitpos, parms)
3678 int bitpos;
3679 struct function_arg_record_value_parms *parms;
3680{
3681 enum machine_mode mode;
3682 int regno, this_slotno, intslots, intoffset;
3683 rtx reg;
3684
3685 if (parms->intoffset == -1)
3686 return;
3687 intoffset = parms->intoffset;
3688 parms->intoffset = -1;
3689
3690 intslots = (bitpos - intoffset + BITS_PER_WORD - 1) / BITS_PER_WORD;
3691 this_slotno = parms->slotno + intoffset / BITS_PER_WORD;
3692
3693 intslots = MIN (intslots, SPARC_INT_ARG_MAX - this_slotno);
3694 if (intslots <= 0)
3695 return;
3696
3697 /* If this is the trailing part of a word, only load that much into
3698 the register. Otherwise load the whole register. Note that in
3699 the latter case we may pick up unwanted bits. It's not a problem
3700 at the moment but may wish to revisit. */
3701
3702 if (intoffset % BITS_PER_WORD != 0)
3703 {
3704 mode = mode_for_size (BITS_PER_WORD - intoffset%BITS_PER_WORD,
3705 MODE_INT, 0);
3706 }
3707 else
3708 mode = word_mode;
3709
3710 intoffset /= BITS_PER_UNIT;
3711 do
3712 {
3713 regno = parms->regbase + this_slotno;
254110c2 3714 reg = gen_rtx_REG (mode, regno);
82d6b402 3715 XVECEXP (parms->ret, 0, parms->nregs)
254110c2 3716 = gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset));
82d6b402
RH		 3717
3718 this_slotno += 1;
3719 intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1;
3720 parms->nregs += 1;
3721 intslots -= 1;
3722 }
3723 while (intslots > 0);
3724}
3725
3726static void
3727function_arg_record_value_2 (type, startbitpos, parms)
3728 tree type;
3729 int startbitpos;
3730 struct function_arg_record_value_parms *parms;
3731{
3732 tree field;
3733 int packed_p = 0;
3734
3735 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
3736 {
3737 if (TREE_CODE (field) == FIELD_DECL && DECL_PACKED (field))
3738 {
3739 packed_p = 1;
3740 break;
3741 }
3742 }
3743
3744 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
3745 {
3746 if (TREE_CODE (field) == FIELD_DECL)
3747 {
3748 int bitpos = startbitpos;
3749 if (DECL_FIELD_BITPOS (field))
3750 bitpos += TREE_INT_CST_LOW (DECL_FIELD_BITPOS (field));
3751 /* ??? FIXME: else assume zero offset. */
3752
3753 if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE)
3754 {
3755 function_arg_record_value_2 (TREE_TYPE (field), bitpos, parms);
3756 }
3757 else if (TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
3758 && TARGET_FPU
3759 && ! packed_p
3760 && parms->named)
3761 {
3762 int this_slotno = parms->slotno + bitpos / BITS_PER_WORD;
3763 rtx reg;
3764
3765 function_arg_record_value_3 (bitpos, parms);
3766
254110c2 3767 reg = gen_rtx_REG (DECL_MODE (field),
82d6b402
RH		 3768 (SPARC_FP_ARG_FIRST + this_slotno * 2
3769 + (DECL_MODE (field) == SFmode
3770 && (bitpos & 32) != 0)));
3771 XVECEXP (parms->ret, 0, parms->nregs)
254110c2 3772 = gen_rtx_EXPR_LIST (VOIDmode, reg,
82d6b402
RH		 3773 GEN_INT (bitpos / BITS_PER_UNIT));
3774 parms->nregs += 1;
3775 }
3776 else
3777 {
3778 if (parms->intoffset == -1)
3779 parms->intoffset = bitpos;
3780 }
3781 }
3782 }
3783}
3784
3785static rtx
1eac9f59 3786function_arg_record_value (type, mode, slotno, named, regbase)
82d6b402 3787 tree type;
1eac9f59 3788 enum machine_mode mode;
82d6b402
RH		 3789 int slotno, named, regbase;
3790{
3791 HOST_WIDE_INT typesize = int_size_in_bytes (type);
3792 struct function_arg_record_value_parms parms;
3793 int nregs;
3794
3795 parms.ret = NULL_RTX;
3796 parms.slotno = slotno;
3797 parms.named = named;
3798 parms.regbase = regbase;
3799
3800 /* Compute how many registers we need. */
3801 parms.nregs = 0;
3802 parms.intoffset = 0;
3803 function_arg_record_value_1 (type, 0, &parms);
3804
3805 if (parms.intoffset != -1)
3806 {
3807 int intslots, this_slotno;
3808
3809 intslots = (typesize*BITS_PER_UNIT - parms.intoffset + BITS_PER_WORD - 1)
3810 / BITS_PER_WORD;
3811 this_slotno = slotno + parms.intoffset / BITS_PER_WORD;
3812
3813 intslots = MIN (intslots, SPARC_INT_ARG_MAX - this_slotno);
3814 intslots = MAX (intslots, 0);
3815
3816 parms.nregs += intslots;
3817 }
3818 nregs = parms.nregs;
3819
3820 /* Allocate the vector and handle some annoying special cases. */
3821 if (nregs == 0)
3822 {
3823 /* ??? Empty structure has no value? Duh? */
3824 if (typesize <= 0)
3825 {
3826 /* Though there's nothing really to store, return a word register
3827 anyway so the rest of gcc doesn't go nuts. Returning a PARALLEL
3828 leads to breakage due to the fact that there are zero bytes to
3829 load. */
1eac9f59 3830 return gen_rtx_REG (mode, regbase);
82d6b402
RH		 3831 }
3832 else
3833 {
3834 /* ??? C++ has structures with no fields, and yet a size. Give up
3835 for now and pass everything back in integer registers. */
3836 nregs = (typesize + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3837 }
3838 if (nregs + slotno > SPARC_INT_ARG_MAX)
3839 nregs = SPARC_INT_ARG_MAX - slotno;
3840 }
3841 if (nregs == 0)
9208e4b2 3842 abort ();
82d6b402 3843
1eac9f59 3844 parms.ret = gen_rtx_PARALLEL (mode, rtvec_alloc (nregs));
82d6b402
RH		 3845
3846 /* Fill in the entries. */
3847 parms.nregs = 0;
3848 parms.intoffset = 0;
3849 function_arg_record_value_2 (type, 0, &parms);
3850 function_arg_record_value_3 (typesize * BITS_PER_UNIT, &parms);
3851
3852 if (parms.nregs != nregs)
3853 abort ();
3854
3855 return parms.ret;
3856}
3857
4fb4e4b8
DE		 3858/* Handle the FUNCTION_ARG macro.
3859 Determine where to put an argument to a function.
3860 Value is zero to push the argument on the stack,
3861 or a hard register in which to store the argument.
3862
3863 CUM is a variable of type CUMULATIVE_ARGS which gives info about
3864 the preceding args and about the function being called.
3865 MODE is the argument's machine mode.
3866 TYPE is the data type of the argument (as a tree).
3867 This is null for libcalls where that information may
3868 not be available.
3869 NAMED is nonzero if this argument is a named parameter
3870 (otherwise it is an extra parameter matching an ellipsis).
3871 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG. */
61a55e8b
DE		 3872
3873rtx
4fb4e4b8
DE		 3874function_arg (cum, mode, type, named, incoming_p)
3875 const CUMULATIVE_ARGS *cum;
3876 enum machine_mode mode;
3877 tree type;
3878 int named;
3879 int incoming_p;
61a55e8b 3880{
4fb4e4b8
DE		 3881 int regbase = (incoming_p
3882 ? SPARC_INCOMING_INT_ARG_FIRST
3883 : SPARC_OUTGOING_INT_ARG_FIRST);
3884 int slotno, regno, padding;
3885 rtx reg;
3886
3887 slotno = function_arg_slotno (cum, mode, type, named, incoming_p,
3888 &regno, &padding);
3889
3890 if (slotno == -1)
3891 return 0;
3892
3893 if (TARGET_ARCH32)
3894 {
254110c2 3895 reg = gen_rtx_REG (mode, regno);
4fb4e4b8
DE		 3896 return reg;
3897 }
3898
3899 /* v9 fp args in reg slots beyond the int reg slots get passed in regs
3900 but also have the slot allocated for them.
3901 If no prototype is in scope fp values in register slots get passed
3902 in two places, either fp regs and int regs or fp regs and memory. */
3903 if ((GET_MODE_CLASS (mode) == MODE_FLOAT
3904 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
3905 && SPARC_FP_REG_P (regno))
3906 {
254110c2 3907 reg = gen_rtx_REG (mode, regno);
4fb4e4b8
DE		 3908 if (cum->prototype_p || cum->libcall_p)
3909 {
3910 /* "* 2" because fp reg numbers are recorded in 4 byte
3911 quantities. */
82d6b402 3912#if 0
4fb4e4b8
DE		 3913 /* ??? This will cause the value to be passed in the fp reg and
3914 in the stack. When a prototype exists we want to pass the
3915 value in the reg but reserve space on the stack. That's an
956d6950 3916 optimization, and is deferred [for a bit]. */
4fb4e4b8 3917 if ((regno - SPARC_FP_ARG_FIRST) >= SPARC_INT_ARG_MAX * 2)
254110c2 3918 return gen_rtx_PARALLEL (mode,
4fb4e4b8 3919 gen_rtvec (2,
254110c2 3920 gen_rtx_EXPR_LIST (VOIDmode,
4fb4e4b8 3921 NULL_RTX, const0_rtx),
254110c2 3922 gen_rtx_EXPR_LIST (VOIDmode,
4fb4e4b8
DE		 3923 reg, const0_rtx)));
3924 else
82d6b402
RH		 3925#else
3926 /* ??? It seems that passing back a register even when past
3927 the area declared by REG_PARM_STACK_SPACE will allocate
3928 space appropriately, and will not copy the data onto the
3929 stack, exactly as we desire.
3930
3931 This is due to locate_and_pad_parm being called in
3932 expand_call whenever reg_parm_stack_space > 0, which
3933 while benefical to our example here, would seem to be
3934 in error from what had been intended. Ho hum... -- r~ */
3935#endif
4fb4e4b8
DE		 3936 return reg;
3937 }
3938 else
3939 {
82d6b402
RH		 3940 rtx v0, v1;
3941
4fb4e4b8
DE		 3942 if ((regno - SPARC_FP_ARG_FIRST) < SPARC_INT_ARG_MAX * 2)
3943 {
82d6b402
RH		 3944 int intreg;
3945
3946 /* On incoming, we don't need to know that the value
3947 is passed in %f0 and %i0, and it confuses other parts
3948 causing needless spillage even on the simplest cases. */
3949 if (incoming_p)
3950 return reg;
3951
3952 intreg = (SPARC_OUTGOING_INT_ARG_FIRST
3953 + (regno - SPARC_FP_ARG_FIRST) / 2);
3954
3955 v0 = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx);
3956 v1 = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_REG (mode, intreg),
3957 const0_rtx);
3958 return gen_rtx_PARALLEL (mode, gen_rtvec (2, v0, v1));
4fb4e4b8
DE		 3959 }
3960 else
82d6b402
RH		 3961 {
3962 v0 = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
3963 v1 = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx);
3964 return gen_rtx_PARALLEL (mode, gen_rtvec (2, v0, v1));
3965 }
4fb4e4b8
DE		 3966 }
3967 }
3968 else if (type && TREE_CODE (type) == RECORD_TYPE)
3969 {
3970 /* Structures up to 16 bytes in size are passed in arg slots on the
3971 stack and are promoted to registers where possible. */
4fb4e4b8
DE		 3972
3973 if (int_size_in_bytes (type) > 16)
3974 abort (); /* shouldn't get here */
3975
1eac9f59 3976 return function_arg_record_value (type, mode, slotno, named, regbase);
4fb4e4b8
DE		 3977 }
3978 else if (type && TREE_CODE (type) == UNION_TYPE)
3979 {
3980 enum machine_mode mode;
3981 int bytes = int_size_in_bytes (type);
3982
3983 if (bytes > 16)
3984 abort ();
3985
3986 mode = mode_for_size (bytes * BITS_PER_UNIT, MODE_INT, 0);
254110c2 3987 reg = gen_rtx_REG (mode, regno);
4fb4e4b8 3988 }
a7acd911 3989 else
4fb4e4b8
DE		 3990 {
3991 /* Scalar or complex int. */
254110c2 3992 reg = gen_rtx_REG (mode, regno);
4fb4e4b8
DE		 3993 }
3994
3995 return reg;
3996}
a7acd911 3997
4fb4e4b8
DE		 3998/* Handle the FUNCTION_ARG_PARTIAL_NREGS macro.
3999 For an arg passed partly in registers and partly in memory,
4000 this is the number of registers used.
4001 For args passed entirely in registers or entirely in memory, zero.
61a55e8b 4002
4fb4e4b8
DE		 4003 Any arg that starts in the first 6 regs but won't entirely fit in them
4004 needs partial registers on v8. On v9, structures with integer
4005 values in arg slots 5,6 will be passed in %o5 and SP+176, and complex fp
4006 values that begin in the last fp reg [where "last fp reg" varies with the
4007 mode] will be split between that reg and memory. */
61a55e8b 4008
4fb4e4b8
DE		 4009int
4010function_arg_partial_nregs (cum, mode, type, named)
4011 const CUMULATIVE_ARGS *cum;
4012 enum machine_mode mode;
4013 tree type;
4014 int named;
4015{
4016 int slotno, regno, padding;
61a55e8b 4017
4fb4e4b8
DE		 4018 /* We pass 0 for incoming_p here, it doesn't matter. */
4019 slotno = function_arg_slotno (cum, mode, type, named, 0, &regno, &padding);
4020
4021 if (slotno == -1)
4022 return 0;
4023
4024 if (TARGET_ARCH32)
bf62bbf1 4025 {
4fb4e4b8
DE		 4026 if ((slotno + (mode == BLKmode
4027 ? ROUND_ADVANCE (int_size_in_bytes (type))
4028 : ROUND_ADVANCE (GET_MODE_SIZE (mode))))
4029 > NPARM_REGS (SImode))
4030 return NPARM_REGS (SImode) - slotno;
4031 return 0;
4032 }
4033 else
4034 {
4035 if (type && AGGREGATE_TYPE_P (type))
4036 {
4037 int size = int_size_in_bytes (type);
4038 int align = TYPE_ALIGN (type);
bf62bbf1 4039
4fb4e4b8
DE		 4040 if (align == 16)
4041 slotno += slotno & 1;
4042 if (size > 8 && size <= 16
4043 && slotno == SPARC_INT_ARG_MAX - 1)
4044 return 1;
4045 }
4046 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_INT
4047 || (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
4048 && ! TARGET_FPU))
4049 {
4050 if (GET_MODE_ALIGNMENT (mode) == 128)
4051 {
4052 slotno += slotno & 1;
4053 if (slotno == SPARC_INT_ARG_MAX - 2)
4054 return 1;
4055 }
4056 else
4057 {
4058 if (slotno == SPARC_INT_ARG_MAX - 1)
4059 return 1;
4060 }
4061 }
4062 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
4063 {
4064 if (GET_MODE_ALIGNMENT (mode) == 128)
4065 slotno += slotno & 1;
4066 if ((slotno + GET_MODE_SIZE (mode) / UNITS_PER_WORD)
4067 > SPARC_FP_ARG_MAX)
4068 return 1;
4069 }
4070 return 0;
bf62bbf1 4071 }
4fb4e4b8 4072}
61a55e8b 4073
4fb4e4b8
DE		 4074/* Handle the FUNCTION_ARG_PASS_BY_REFERENCE macro.
4075 !v9: The SPARC ABI stipulates passing struct arguments (of any size) and
4076 quad-precision floats by invisible reference.
82d6b402 4077 v9: Aggregates greater than 16 bytes are passed by reference.
4fb4e4b8
DE		 4078 For Pascal, also pass arrays by reference. */
4079
4080int
4081function_arg_pass_by_reference (cum, mode, type, named)
db3d4438 4082 const CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED;
4fb4e4b8
DE		 4083 enum machine_mode mode;
4084 tree type;
db3d4438 4085 int named ATTRIBUTE_UNUSED;
4fb4e4b8
DE		 4086{
4087 if (TARGET_ARCH32)
eadceb59 4088 {
5e9defae 4089 return ((type && AGGREGATE_TYPE_P (type))
4fb4e4b8
DE		 4090 || mode == TFmode || mode == TCmode);
4091 }
4092 else
4093 {
4094 return ((type && TREE_CODE (type) == ARRAY_TYPE)
82d6b402
RH		 4095 /* Consider complex values as aggregates, so care for TCmode. */
4096 || GET_MODE_SIZE (mode) > 16
4fb4e4b8
DE		 4097 || (type && AGGREGATE_TYPE_P (type)
4098 && int_size_in_bytes (type) > 16));
4099 }
4100}
4101
4102/* Handle the FUNCTION_ARG_ADVANCE macro.
4103 Update the data in CUM to advance over an argument
4104 of mode MODE and data type TYPE.
4105 TYPE is null for libcalls where that information may not be available. */
4106
4107void
4108function_arg_advance (cum, mode, type, named)
4109 CUMULATIVE_ARGS *cum;
4110 enum machine_mode mode;
4111 tree type;
4112 int named;
4113{
4114 int slotno, regno, padding;
4115
4116 /* We pass 0 for incoming_p here, it doesn't matter. */
4117 slotno = function_arg_slotno (cum, mode, type, named, 0, &regno, &padding);
4118
4119 /* If register required leading padding, add it. */
4120 if (slotno != -1)
4121 cum->words += padding;
eadceb59 4122
4fb4e4b8
DE		 4123 if (TARGET_ARCH32)
4124 {
4125 cum->words += (mode != BLKmode
4126 ? ROUND_ADVANCE (GET_MODE_SIZE (mode))
4127 : ROUND_ADVANCE (int_size_in_bytes (type)));
4128 }
4129 else
4130 {
4131 if (type && AGGREGATE_TYPE_P (type))
4132 {
4133 int size = int_size_in_bytes (type);
4134
4135 if (size <= 8)
4136 ++cum->words;
4137 else if (size <= 16)
4138 cum->words += 2;
4139 else /* passed by reference */
4140 ++cum->words;
4141 }
4142 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_INT)
4143 {
4144 cum->words += 2;
4145 }
4146 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
4147 {
4148 cum->words += GET_MODE_SIZE (mode) / UNITS_PER_WORD;
4149 }
4150 else
4151 {
4152 cum->words += (mode != BLKmode
4153 ? ROUND_ADVANCE (GET_MODE_SIZE (mode))
4154 : ROUND_ADVANCE (int_size_in_bytes (type)));
4155 }
eadceb59 4156 }
4fb4e4b8 4157}
eadceb59 4158
4fb4e4b8
DE		 4159/* Handle the FUNCTION_ARG_PADDING macro.
4160 For the 64 bit ABI structs are always stored left shifted in their
4161 argument slot. */
4162
4163enum direction
4164function_arg_padding (mode, type)
4165 enum machine_mode mode;
4166 tree type;
4167{
c85f7c16
JL		 4168 if (TARGET_ARCH64 && type != 0 && AGGREGATE_TYPE_P (type))
4169 return upward;
61a55e8b 4170
4fb4e4b8
DE		 4171 /* This is the default definition. */
4172 return (! BYTES_BIG_ENDIAN
4173 ? upward
4174 : ((mode == BLKmode
4175 ? (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
4176 && int_size_in_bytes (type) < (PARM_BOUNDARY / BITS_PER_UNIT))
4177 : GET_MODE_BITSIZE (mode) < PARM_BOUNDARY)
4178 ? downward : upward));
61a55e8b 4179}
82d6b402
RH		 4180
4181/* Handle FUNCTION_VALUE, FUNCTION_OUTGOING_VALUE, and LIBCALL_VALUE macros.
4182 For v9, function return values are subject to the same rules as arguments,
4183 except that up to 32-bytes may be returned in registers. */
4184
4185rtx
4186function_value (type, mode, incoming_p)
4187 tree type;
4188 enum machine_mode mode;
4189 int incoming_p;
4190{
4191 int regno;
4192 int regbase = (incoming_p
4193 ? SPARC_OUTGOING_INT_ARG_FIRST
4194 : SPARC_INCOMING_INT_ARG_FIRST);
4195
4196 if (TARGET_ARCH64 && type)
4197 {
4198 if (TREE_CODE (type) == RECORD_TYPE)
4199 {
4200 /* Structures up to 32 bytes in size are passed in registers,
4201 promoted to fp registers where possible. */
4202
4203 if (int_size_in_bytes (type) > 32)
4204 abort (); /* shouldn't get here */
4205
1eac9f59 4206 return function_arg_record_value (type, mode, 0, 1, regbase);
82d6b402
RH		 4207 }
4208 else if (TREE_CODE (type) == UNION_TYPE)
4209 {
4210 int bytes = int_size_in_bytes (type);
4211
4212 if (bytes > 32)
4213 abort ();
4214
4215 mode = mode_for_size (bytes * BITS_PER_UNIT, MODE_INT, 0);
4216 }
4217 }
4218
4219 if (incoming_p)
4220 regno = BASE_RETURN_VALUE_REG (mode);
4221 else
4222 regno = BASE_OUTGOING_VALUE_REG (mode);
4223
254110c2 4224 return gen_rtx_REG (mode, regno);
82d6b402
RH		 4225}
4226
4fb4e4b8 4227/* Do what is necessary for `va_start'. The argument is ignored.
61a55e8b 4228
4fb4e4b8
DE		 4229 We look at the current function to determine if stdarg or varargs
4230 is used and return the address of the first unnamed parameter. */
3ea1fdd3
JW		 4231
4232rtx
4233sparc_builtin_saveregs (arglist)
db3d4438 4234 tree arglist ATTRIBUTE_UNUSED;
3ea1fdd3 4235{
4fb4e4b8 4236 int first_reg = current_function_args_info.words;
3ea1fdd3
JW		 4237 rtx address;
4238 int regno;
4239
4fb4e4b8 4240 for (regno = first_reg; regno < NPARM_REGS (word_mode); regno++)
254110c2
DM		 4241 emit_move_insn (gen_rtx_MEM (word_mode,
4242 gen_rtx_PLUS (Pmode,
3ea1fdd3
JW		 4243 frame_pointer_rtx,
4244 GEN_INT (STACK_POINTER_OFFSET
4245 + UNITS_PER_WORD * regno))),
254110c2 4246 gen_rtx_REG (word_mode,
4fb4e4b8 4247 BASE_INCOMING_ARG_REG (word_mode) + regno));
3ea1fdd3 4248
254110c2 4249 address = gen_rtx_PLUS (Pmode,
3ea1fdd3
JW		 4250 frame_pointer_rtx,
4251 GEN_INT (STACK_POINTER_OFFSET
4252 + UNITS_PER_WORD * first_reg));
4253
4fb4e4b8
DE		 4254 if (flag_check_memory_usage
4255 && first_reg < NPARM_REGS (word_mode))
eadceb59
RK		 4256 emit_library_call (chkr_set_right_libfunc, 1, VOIDmode, 3,
4257 address, ptr_mode,
4258 GEN_INT (UNITS_PER_WORD
4fb4e4b8 4259 * (NPARM_REGS (word_mode) - first_reg)),
956d6950
JL		 4260 TYPE_MODE (sizetype), GEN_INT (MEMORY_USE_RW),
4261 TYPE_MODE (integer_type_node));
eadceb59 4262
3ea1fdd3
JW		 4263 return address;
4264}
ab835497
RK		 4265\f
4266/* Return the string to output a conditional branch to LABEL, which is
c4ce6853
DE		 4267 the operand number of the label. OP is the conditional expression.
4268 XEXP (OP, 0) is assumed to be a condition code register (integer or
4269 floating point) and its mode specifies what kind of comparison we made.
61a55e8b 4270
ab835497
RK		 4271 REVERSED is non-zero if we should reverse the sense of the comparison.
4272
4273 ANNUL is non-zero if we should generate an annulling branch.
4274
c6b0465b
JC		 4275 NOOP is non-zero if we have to follow this branch by a noop.
4276
4277 INSN, if set, is the insn. */
ab835497
RK		 4278
4279char *
c6b0465b 4280output_cbranch (op, label, reversed, annul, noop, insn)
c4ce6853 4281 rtx op;
ab835497
RK		 4282 int label;
4283 int reversed, annul, noop;
c6b0465b 4284 rtx insn;
ab835497 4285{
e0d80184 4286 static char string[32];
ab835497 4287 enum rtx_code code = GET_CODE (op);
c4ce6853
DE		 4288 rtx cc_reg = XEXP (op, 0);
4289 enum machine_mode mode = GET_MODE (cc_reg);
e0d80184
DM		 4290 static char v8_labelno[] = "%lX";
4291 static char v9_icc_labelno[] = "%%icc, %lX";
4292 static char v9_xcc_labelno[] = "%%xcc, %lX";
4293 static char v9_fcc_labelno[] = "%%fccX, %lY";
61a55e8b 4294 char *labelno;
e0d80184 4295 int labeloff, spaces = 8;
61a55e8b
DE		 4296
4297 /* ??? !v9: FP branches cannot be preceded by another floating point insn.
ab835497
RK		 4298 Because there is currently no concept of pre-delay slots, we can fix
4299 this only by always emitting a nop before a floating point branch. */
4300
61a55e8b 4301 if ((mode == CCFPmode || mode == CCFPEmode) && ! TARGET_V9)
ab835497 4302 strcpy (string, "nop\n\t");
61a55e8b
DE		 4303 else
4304 string[0] = '\0';
ab835497
RK		 4305
4306 /* If not floating-point or if EQ or NE, we can just reverse the code. */
4d449554
JW		 4307 if (reversed
4308 && ((mode != CCFPmode && mode != CCFPEmode) || code == EQ || code == NE))
ab835497
RK		 4309 code = reverse_condition (code), reversed = 0;
4310
4311 /* Start by writing the branch condition. */
4312 switch (code)
4313 {
4314 case NE:
4d449554 4315 if (mode == CCFPmode || mode == CCFPEmode)
e0d80184
DM		 4316 {
4317 strcat (string, "fbne");
4318 spaces -= 4;
4319 }
ab835497 4320 else
e0d80184
DM		 4321 {
4322 strcpy (string, "bne");
4323 spaces -= 3;
4324 }
ab835497
RK		 4325 break;
4326
4327 case EQ:
4d449554 4328 if (mode == CCFPmode || mode == CCFPEmode)
e0d80184
DM		 4329 {
4330 strcat (string, "fbe");
4331 spaces -= 3;
4332 }
ab835497 4333 else
e0d80184
DM		 4334 {
4335 strcpy (string, "be");
4336 spaces -= 2;
4337 }
ab835497
RK		 4338 break;
4339
4340 case GE:
4d449554 4341 if (mode == CCFPmode || mode == CCFPEmode)
ab835497
RK		 4342 {
4343 if (reversed)
4344 strcat (string, "fbul");
4345 else
4346 strcat (string, "fbge");
e0d80184 4347 spaces -= 4;
ab835497
RK		 4348 }
4349 else if (mode == CC_NOOVmode)
e0d80184
DM		 4350 {
4351 strcpy (string, "bpos");
4352 spaces -= 4;
4353 }
ab835497 4354 else
e0d80184
DM		 4355 {
4356 strcpy (string, "bge");
4357 spaces -= 3;
4358 }
ab835497
RK		 4359 break;
4360
4361 case GT:
4d449554 4362 if (mode == CCFPmode || mode == CCFPEmode)
ab835497
RK		 4363 {
4364 if (reversed)
e0d80184
DM		 4365 {
4366 strcat (string, "fbule");
4367 spaces -= 5;
4368 }
ab835497 4369 else
e0d80184
DM		 4370 {
4371 strcat (string, "fbg");
4372 spaces -= 3;
4373 }
ab835497
RK		 4374 }
4375 else
e0d80184
DM		 4376 {
4377 strcpy (string, "bg");
4378 spaces -= 2;
4379 }
ab835497
RK		 4380 break;
4381
4382 case LE:
4d449554 4383 if (mode == CCFPmode || mode == CCFPEmode)
ab835497
RK		 4384 {
4385 if (reversed)
4386 strcat (string, "fbug");
4387 else
4388 strcat (string, "fble");
e0d80184 4389 spaces -= 4;
ab835497
RK		 4390 }
4391 else
e0d80184
DM		 4392 {
4393 strcpy (string, "ble");
4394 spaces -= 3;
4395 }
ab835497
RK		 4396 break;
4397
4398 case LT:
4d449554 4399 if (mode == CCFPmode || mode == CCFPEmode)
ab835497
RK		 4400 {
4401 if (reversed)
e0d80184
DM		 4402 {
4403 strcat (string, "fbuge");
4404 spaces -= 5;
4405 }
ab835497 4406 else
e0d80184
DM		 4407 {
4408 strcat (string, "fbl");
4409 spaces -= 3;
4410 }
ab835497
RK		 4411 }
4412 else if (mode == CC_NOOVmode)
e0d80184
DM		 4413 {
4414 strcpy (string, "bneg");
4415 spaces -= 4;
4416 }
ab835497 4417 else
e0d80184
DM		 4418 {
4419 strcpy (string, "bl");
4420 spaces -= 2;
4421 }
ab835497
RK		 4422 break;
4423
4424 case GEU:
4425 strcpy (string, "bgeu");
e0d80184 4426 spaces -= 4;
ab835497
RK		 4427 break;
4428
4429 case GTU:
4430 strcpy (string, "bgu");
e0d80184 4431 spaces -= 3;
ab835497
RK		 4432 break;
4433
4434 case LEU:
4435 strcpy (string, "bleu");
e0d80184 4436 spaces -= 4;
ab835497
RK		 4437 break;
4438
4439 case LTU:
4440 strcpy (string, "blu");
e0d80184 4441 spaces -= 3;
ab835497 4442 break;
91a51951
KG		 4443
4444 default:
e0d80184 4445 abort ();
ab835497
RK		 4446 }
4447
4448 /* Now add the annulling, the label, and a possible noop. */
4449 if (annul)
e0d80184
DM		 4450 {
4451 strcat (string, ",a");
4452 spaces -= 2;
4453 }
ab835497 4454
61a55e8b
DE		 4455 if (! TARGET_V9)
4456 {
e0d80184 4457 labeloff = 2;
61a55e8b
DE		 4458 labelno = v8_labelno;
4459 }
4460 else
4461 {
c6b0465b
JC		 4462 rtx note;
4463
4464 if (insn && (note = find_reg_note (insn, REG_BR_PRED, NULL_RTX)))
e0d80184
DM		 4465 {
4466 strcat (string,
4467 INTVAL (XEXP (note, 0)) & ATTR_FLAG_likely ? ",pt" : ",pn");
4468 spaces -= 3;
4469 }
c6b0465b 4470
61a55e8b
DE		 4471 labeloff = 9;
4472 if (mode == CCFPmode || mode == CCFPEmode)
4473 {
4474 labeloff = 10;
4475 labelno = v9_fcc_labelno;
4476 /* Set the char indicating the number of the fcc reg to use. */
e0d80184 4477 labelno[5] = REGNO (cc_reg) - SPARC_FIRST_V9_FCC_REG + '0';
61a55e8b
DE		 4478 }
4479 else if (mode == CCXmode || mode == CCX_NOOVmode)
4480 labelno = v9_xcc_labelno;
4481 else
4482 labelno = v9_icc_labelno;
4483 }
4484 /* Set the char indicating the number of the operand containing the
4485 label_ref. */
4486 labelno[labeloff] = label + '0';
e0d80184
DM		 4487 if (spaces > 0)
4488 strcat (string, "\t");
4489 else
4490 strcat (string, " ");
61a55e8b
DE		 4491 strcat (string, labelno);
4492
4493 if (noop)
4494 strcat (string, "\n\tnop");
4495
4496 return string;
4497}
4498
4499/* Return the string to output a conditional branch to LABEL, testing
4500 register REG. LABEL is the operand number of the label; REG is the
4501 operand number of the reg. OP is the conditional expression. The mode
4502 of REG says what kind of comparison we made.
4503
4504 REVERSED is non-zero if we should reverse the sense of the comparison.
4505
4506 ANNUL is non-zero if we should generate an annulling branch.
4507
4508 NOOP is non-zero if we have to follow this branch by a noop. */
4509
4510char *
e0d80184 4511output_v9branch (op, reg, label, reversed, annul, noop, insn)
61a55e8b
DE		 4512 rtx op;
4513 int reg, label;
4514 int reversed, annul, noop;
e0d80184 4515 rtx insn;
61a55e8b
DE		 4516{
4517 static char string[20];
4518 enum rtx_code code = GET_CODE (op);
4519 enum machine_mode mode = GET_MODE (XEXP (op, 0));
e0d80184
DM		 4520 static char labelno[] = "%X, %lX";
4521 rtx note;
4522 int spaces = 8;
61a55e8b
DE		 4523
4524 /* If not floating-point or if EQ or NE, we can just reverse the code. */
4525 if (reversed)
4526 code = reverse_condition (code), reversed = 0;
4527
4528 /* Only 64 bit versions of these instructions exist. */
4529 if (mode != DImode)
4530 abort ();
4531
4532 /* Start by writing the branch condition. */
4533
4534 switch (code)
4535 {
4536 case NE:
4537 strcpy (string, "brnz");
e0d80184 4538 spaces -= 4;
61a55e8b
DE		 4539 break;
4540
4541 case EQ:
4542 strcpy (string, "brz");
e0d80184 4543 spaces -= 3;
61a55e8b
DE		 4544 break;
4545
4546 case GE:
4547 strcpy (string, "brgez");
e0d80184 4548 spaces -= 5;
61a55e8b
DE		 4549 break;
4550
4551 case LT:
4552 strcpy (string, "brlz");
e0d80184 4553 spaces -= 4;
61a55e8b
DE		 4554 break;
4555
4556 case LE:
4557 strcpy (string, "brlez");
e0d80184 4558 spaces -= 5;
61a55e8b
DE		 4559 break;
4560
4561 case GT:
4562 strcpy (string, "brgz");
e0d80184 4563 spaces -= 4;
61a55e8b
DE		 4564 break;
4565
4566 default:
4567 abort ();
4568 }
4569
4570 /* Now add the annulling, reg, label, and nop. */
4571 if (annul)
e0d80184
DM		 4572 {
4573 strcat (string, ",a");
4574 spaces -= 2;
4575 }
61a55e8b 4576
e0d80184
DM		 4577 if (insn && (note = find_reg_note (insn, REG_BR_PRED, NULL_RTX)))
4578 {
4579 strcat (string,
4580 INTVAL (XEXP (note, 0)) & ATTR_FLAG_likely ? ",pt" : ",pn");
4581 spaces -= 3;
4582 }
61a55e8b 4583
e0d80184 4584 labelno[1] = reg + '0';
61a55e8b 4585 labelno[6] = label + '0';
e0d80184
DM		 4586 if (spaces > 0)
4587 strcat (string, "\t");
4588 else
4589 strcat (string, " ");
ab835497
RK		 4590 strcat (string, labelno);
4591
4592 if (noop)
4593 strcat (string, "\n\tnop");
4594
4595 return string;
4596}
4597
284d86e9
JC		 4598/* Renumber registers in delay slot. Replace registers instead of
4599 renumbering because they may be shared.
795068a4 4600
284d86e9
JC		 4601 This does not handle instructions other than move. */
4602
4603static void
4604epilogue_renumber (where)
4605 rtx *where;
4606{
4607 rtx x = *where;
4608 enum rtx_code code = GET_CODE (x);
4609
4610 switch (code)
4611 {
4612 case MEM:
4613 *where = x = copy_rtx (x);
4614 epilogue_renumber (&XEXP (x, 0));
4615 return;
4616
4617 case REG:
4618 {
4619 int regno = REGNO (x);
4620 if (regno > 8 && regno < 24)
4621 abort ();
4622 if (regno >= 24 && regno < 32)
4623 *where = gen_rtx_REG (GET_MODE (x), regno - 16);
4624 return;
4625 }
4626 case CONST_INT:
4627 case CONST_DOUBLE:
4628 case CONST:
4629 case SYMBOL_REF:
4630 case LABEL_REF:
4631 return;
4632
4633 case IOR:
4634 case AND:
4635 case XOR:
4636 case PLUS:
4637 case MINUS:
4638 epilogue_renumber (&XEXP (x, 1));
4639 case NEG:
4640 case NOT:
4641 epilogue_renumber (&XEXP (x, 0));
4642 return;
4643
4644 default:
4645 debug_rtx (*where);
9208e4b2 4646 abort ();
284d86e9
JC		 4647 }
4648}
4649
4650/* Output assembler code to return from a function. */
61a55e8b 4651
ab835497
RK		 4652char *
4653output_return (operands)
4654 rtx *operands;
4655{
284d86e9
JC		 4656 rtx delay = final_sequence ? XVECEXP (final_sequence, 0, 1) : 0;
4657
ab835497
RK		 4658 if (leaf_label)
4659 {
4660 operands[0] = leaf_label;
284d86e9 4661 return "b%* %l0%(";
ab835497
RK		 4662 }
4663 else if (leaf_function)
4664 {
284d86e9
JC		 4665 /* No delay slot in a leaf function. */
4666 if (delay)
4667 abort ();
4668
915f619f
JW		 4669 /* If we didn't allocate a frame pointer for the current function,
4670 the stack pointer might have been adjusted. Output code to
4671 restore it now. */
4672
3a598fbe 4673 operands[0] = GEN_INT (actual_fsize);
915f619f
JW		 4674
4675 /* Use sub of negated value in first two cases instead of add to
4676 allow actual_fsize == 4096. */
4677
4678 if (actual_fsize <= 4096)
ab835497 4679 {
61a55e8b 4680 if (SKIP_CALLERS_UNIMP_P)
e0d80184 4681 return "jmp\t%%o7+12\n\tsub\t%%sp, -%0, %%sp";
ab835497 4682 else
e0d80184 4683 return "retl\n\tsub\t%%sp, -%0, %%sp";
ab835497 4684 }
915f619f 4685 else if (actual_fsize <= 8192)
ab835497 4686 {
3a598fbe 4687 operands[0] = GEN_INT (actual_fsize - 4096);
61a55e8b 4688 if (SKIP_CALLERS_UNIMP_P)
e0d80184 4689 return "sub\t%%sp, -4096, %%sp\n\tjmp\t%%o7+12\n\tsub\t%%sp, -%0, %%sp";
915f619f 4690 else
e0d80184 4691 return "sub\t%%sp, -4096, %%sp\n\tretl\n\tsub\t%%sp, -%0, %%sp";
915f619f 4692 }
61a55e8b 4693 else if (SKIP_CALLERS_UNIMP_P)
915f619f
JW		 4694 {
4695 if ((actual_fsize & 0x3ff) != 0)
e0d80184 4696 return "sethi\t%%hi(%a0), %%g1\n\tor\t%%g1, %%lo(%a0), %%g1\n\tjmp\t%%o7+12\n\tadd\t%%sp, %%g1, %%sp";
ab835497 4697 else
e0d80184 4698 return "sethi\t%%hi(%a0), %%g1\n\tjmp\t%%o7+12\n\tadd\t%%sp, %%g1, %%sp";
915f619f
JW		 4699 }
4700 else
4701 {
4702 if ((actual_fsize & 0x3ff) != 0)
ab835497 4703 return "sethi %%hi(%a0),%%g1\n\tor %%g1,%%lo(%a0),%%g1\n\tretl\n\tadd %%sp,%%g1,%%sp";
915f619f
JW		 4704 else
4705 return "sethi %%hi(%a0),%%g1\n\tretl\n\tadd %%sp,%%g1,%%sp";
ab835497
RK		 4706 }
4707 }
284d86e9
JC		 4708 else if (TARGET_V9)
4709 {
4710 if (delay)
4711 {
4712 epilogue_renumber (&SET_DEST (PATTERN (delay)));
4713 epilogue_renumber (&SET_SRC (PATTERN (delay)));
4714 }
4715 if (SKIP_CALLERS_UNIMP_P)
e0d80184 4716 return "return\t%%i7+12%#";
284d86e9 4717 else
e0d80184 4718 return "return\t%%i7+8%#";
284d86e9 4719 }
ab835497
RK		 4720 else
4721 {
284d86e9
JC		 4722 if (delay)
4723 abort ();
61a55e8b 4724 if (SKIP_CALLERS_UNIMP_P)
e0d80184 4725 return "jmp\t%%i7+12\n\trestore";
ab835497
RK		 4726 else
4727 return "ret\n\trestore";
4728 }
4729}
ab835497
RK		 4730\f
4731/* Leaf functions and non-leaf functions have different needs. */
4732
4733static int
4734reg_leaf_alloc_order[] = REG_LEAF_ALLOC_ORDER;
4735
4736static int
4737reg_nonleaf_alloc_order[] = REG_ALLOC_ORDER;
4738
4739static int *reg_alloc_orders[] = {
4740 reg_leaf_alloc_order,
4741 reg_nonleaf_alloc_order};
4742
4743void
4744order_regs_for_local_alloc ()
4745{
4746 static int last_order_nonleaf = 1;
4747
4748 if (regs_ever_live[15] != last_order_nonleaf)
4749 {
4750 last_order_nonleaf = !last_order_nonleaf;
d2889939
RK		 4751 bcopy ((char *) reg_alloc_orders[last_order_nonleaf],
4752 (char *) reg_alloc_order, FIRST_PSEUDO_REGISTER * sizeof (int));
ab835497
RK		 4753 }
4754}
4755\f
e0d80184
DM		 4756/* Return 1 if REG and MEM are legitimate enough to allow the various
4757 mem<-->reg splits to be run. */
4758
4759int
e61c29e9 4760sparc_splitdi_legitimate (reg, mem)
e0d80184
DM		 4761 rtx reg;
4762 rtx mem;
4763{
e0d80184
DM		 4764 /* Punt if we are here by mistake. */
4765 if (! reload_completed)
9208e4b2 4766 abort ();
e0d80184
DM		 4767
4768 /* We must have an offsettable memory reference. */
4769 if (! offsettable_memref_p (mem))
4770 return 0;
4771
4772 /* If we have legitimate args for ldd/std, we do not want
4773 the split to happen. */
4774 if ((REGNO (reg) % 2) == 0
4775 && mem_min_alignment (mem, 8))
4776 return 0;
4777
4778 /* Success. */
4779 return 1;
4780}
4781
e61c29e9
DM		 4782/* Return 1 if x and y are some kind of REG and they refer to
4783 different hard registers. This test is guarenteed to be
4784 run after reload. */
4785
4786int
4787sparc_absnegfloat_split_legitimate (x, y)
4788 rtx x, y;
4789{
4790 if (GET_CODE (x) == SUBREG)
4791 x = alter_subreg (x);
4792 if (GET_CODE (x) != REG)
4793 return 0;
4794 if (GET_CODE (y) == SUBREG)
4795 y = alter_subreg (y);
4796 if (GET_CODE (y) != REG)
4797 return 0;
4798 if (REGNO (x) == REGNO (y))
4799 return 0;
4800 return 1;
4801}
4802
35016322
JW		 4803/* Return 1 if REGNO (reg1) is even and REGNO (reg1) == REGNO (reg2) - 1.
4804 This makes them candidates for using ldd and std insns.
4805
bfd6bc60 4806 Note reg1 and reg2 *must* be hard registers. */
35016322
JW		 4807
4808int
7c56249d 4809registers_ok_for_ldd_peep (reg1, reg2)
35016322
JW		 4810 rtx reg1, reg2;
4811{
35016322
JW		 4812 /* We might have been passed a SUBREG. */
4813 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
4814 return 0;
4815
35016322
JW		 4816 if (REGNO (reg1) % 2 != 0)
4817 return 0;
4818
bfd6bc60
JC		 4819 /* Integer ldd is deprecated in SPARC V9 */
4820 if (TARGET_V9 && REGNO (reg1) < 32)
4821 return 0;
4822
35016322 4823 return (REGNO (reg1) == REGNO (reg2) - 1);
35016322
JW		 4824}
4825
4826/* Return 1 if addr1 and addr2 are suitable for use in an ldd or
4827 std insn.
4828
4829 This can only happen when addr1 and addr2 are consecutive memory
4830 locations (addr1 + 4 == addr2). addr1 must also be aligned on a
4831 64 bit boundary (addr1 % 8 == 0).
4832
4833 We know %sp and %fp are kept aligned on a 64 bit boundary. Other
4834 registers are assumed to *never* be properly aligned and are
4835 rejected.
4836
4837 Knowing %sp and %fp are kept aligned on a 64 bit boundary, we
4838 need only check that the offset for addr1 % 8 == 0. */
4839
4840int
7c56249d 4841addrs_ok_for_ldd_peep (addr1, addr2)
35016322
JW		 4842 rtx addr1, addr2;
4843{
4844 int reg1, offset1;
4845
4846 /* Extract a register number and offset (if used) from the first addr. */
4847 if (GET_CODE (addr1) == PLUS)
4848 {
4849 /* If not a REG, return zero. */
4850 if (GET_CODE (XEXP (addr1, 0)) != REG)
4851 return 0;
4852 else
4853 {
4854 reg1 = REGNO (XEXP (addr1, 0));
4855 /* The offset must be constant! */
4856 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
4857 return 0;
4858 offset1 = INTVAL (XEXP (addr1, 1));
4859 }
4860 }
4861 else if (GET_CODE (addr1) != REG)
4862 return 0;
4863 else
4864 {
4865 reg1 = REGNO (addr1);
4866 /* This was a simple (mem (reg)) expression. Offset is 0. */
4867 offset1 = 0;
4868 }
4869
4870 /* Make sure the second address is a (mem (plus (reg) (const_int). */
4871 if (GET_CODE (addr2) != PLUS)
4872 return 0;
4873
4874 if (GET_CODE (XEXP (addr2, 0)) != REG
4875 || GET_CODE (XEXP (addr2, 1)) != CONST_INT)
4876 return 0;
4877
4878 /* Only %fp and %sp are allowed. Additionally both addresses must
4879 use the same register. */
4880 if (reg1 != FRAME_POINTER_REGNUM && reg1 != STACK_POINTER_REGNUM)
4881 return 0;
4882
4883 if (reg1 != REGNO (XEXP (addr2, 0)))
4884 return 0;
4885
2296cba3 4886 /* The first offset must be evenly divisible by 8 to ensure the
35016322
JW		 4887 address is 64 bit aligned. */
4888 if (offset1 % 8 != 0)
4889 return 0;
4890
4891 /* The offset for the second addr must be 4 more than the first addr. */
4892 if (INTVAL (XEXP (addr2, 1)) != offset1 + 4)
4893 return 0;
4894
4895 /* All the tests passed. addr1 and addr2 are valid for ldd and std
4896 instructions. */
4897 return 1;
4898}
7c56249d
JL		 4899
4900/* Return 1 if reg is a pseudo, or is the first register in
4901 a hard register pair. This makes it a candidate for use in
4902 ldd and std insns. */
4903
4904int
4905register_ok_for_ldd (reg)
4906 rtx reg;
4907{
7c56249d
JL		 4908 /* We might have been passed a SUBREG. */
4909 if (GET_CODE (reg) != REG)
4910 return 0;
4911
4912 if (REGNO (reg) < FIRST_PSEUDO_REGISTER)
4913 return (REGNO (reg) % 2 == 0);
4914 else
4915 return 1;
7c56249d 4916}
ab835497 4917\f
ab835497
RK		 4918/* Print operand X (an rtx) in assembler syntax to file FILE.
4919 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
4920 For `%' followed by punctuation, CODE is the punctuation and X is null. */
4921
4922void
4923print_operand (file, x, code)
4924 FILE *file;
4925 rtx x;
4926 int code;
4927{
4928 switch (code)
4929 {
4930 case '#':
4931 /* Output a 'nop' if there's nothing for the delay slot. */
4932 if (dbr_sequence_length () == 0)
e0d80184 4933 fputs ("\n\t nop", file);
ab835497
RK		 4934 return;
4935 case '*':
c6ce0969
JW		 4936 /* Output an annul flag if there's nothing for the delay slot and we
4937 are optimizing. This is always used with '(' below. */
4938 /* Sun OS 4.1.1 dbx can't handle an annulled unconditional branch;
4939 this is a dbx bug. So, we only do this when optimizing. */
bfd6bc60
JC		 4940 /* On UltraSPARC, a branch in a delay slot causes a pipeline flush.
4941 Always emit a nop in case the next instruction is a branch. */
4942 if (dbr_sequence_length () == 0
284d86e9 4943 && (optimize && (int)sparc_cpu < PROCESSOR_V9))
c6ce0969
JW		 4944 fputs (",a", file);
4945 return;
4946 case '(':
4947 /* Output a 'nop' if there's nothing for the delay slot and we are
4948 not optimizing. This is always used with '*' above. */
bfd6bc60 4949 if (dbr_sequence_length () == 0
284d86e9 4950 && ! (optimize && (int)sparc_cpu < PROCESSOR_V9))
e0d80184 4951 fputs ("\n\t nop", file);
ab835497 4952 return;
61a55e8b 4953 case '_':
a0a301fc
DE		 4954 /* Output the Embedded Medium/Anywhere code model base register. */
4955 fputs (EMBMEDANY_BASE_REG, file);
61a55e8b
DE		 4956 return;
4957 case '@':
4958 /* Print out what we are using as the frame pointer. This might
4959 be %fp, or might be %sp+offset. */
4960 /* ??? What if offset is too big? Perhaps the caller knows it isn't? */
4961 fprintf (file, "%s+%d", frame_base_name, frame_base_offset);
4962 return;
ab835497
RK		 4963 case 'Y':
4964 /* Adjust the operand to take into account a RESTORE operation. */
bfd6bc60
JC		 4965 if (GET_CODE (x) == CONST_INT)
4966 break;
4967 else if (GET_CODE (x) != REG)
b3b1e8bd
JW		 4968 output_operand_lossage ("Invalid %%Y operand");
4969 else if (REGNO (x) < 8)
ab835497
RK		 4970 fputs (reg_names[REGNO (x)], file);
4971 else if (REGNO (x) >= 24 && REGNO (x) < 32)
4972 fputs (reg_names[REGNO (x)-16], file);
4973 else
b3b1e8bd 4974 output_operand_lossage ("Invalid %%Y operand");
ab835497 4975 return;
0f39a9aa
DE		 4976 case 'L':
4977 /* Print out the low order register name of a register pair. */
4978 if (WORDS_BIG_ENDIAN)
4979 fputs (reg_names[REGNO (x)+1], file);
4980 else
4981 fputs (reg_names[REGNO (x)], file);
4982 return;
4983 case 'H':
4984 /* Print out the high order register name of a register pair. */
4985 if (WORDS_BIG_ENDIAN)
4986 fputs (reg_names[REGNO (x)], file);
4987 else
4988 fputs (reg_names[REGNO (x)+1], file);
4989 return;
ab835497 4990 case 'R':
795068a4 4991 /* Print out the second register name of a register pair or quad.
ab835497
RK		 4992 I.e., R (%o0) => %o1. */
4993 fputs (reg_names[REGNO (x)+1], file);
4994 return;
795068a4
JW		 4995 case 'S':
4996 /* Print out the third register name of a register quad.
4997 I.e., S (%o0) => %o2. */
4998 fputs (reg_names[REGNO (x)+2], file);
4999 return;
5000 case 'T':
5001 /* Print out the fourth register name of a register quad.
5002 I.e., T (%o0) => %o3. */
5003 fputs (reg_names[REGNO (x)+3], file);
5004 return;
304b7a23
DE		 5005 case 'x':
5006 /* Print a condition code register. */
5007 if (REGNO (x) == SPARC_ICC_REG)
5008 {
5009 /* We don't handle CC[X]_NOOVmode because they're not supposed
5010 to occur here. */
5011 if (GET_MODE (x) == CCmode)
5012 fputs ("%icc", file);
5013 else if (GET_MODE (x) == CCXmode)
5014 fputs ("%xcc", file);
5015 else
5016 abort ();
5017 }
5018 else
5019 /* %fccN register */
5020 fputs (reg_names[REGNO (x)], file);
5021 return;
ab835497
RK		 5022 case 'm':
5023 /* Print the operand's address only. */
5024 output_address (XEXP (x, 0));
5025 return;
5026 case 'r':
5027 /* In this case we need a register. Use %g0 if the
77a02b01 5028 operand is const0_rtx. */
76052e74
RS		 5029 if (x == const0_rtx
5030 || (GET_MODE (x) != VOIDmode && x == CONST0_RTX (GET_MODE (x))))
ab835497
RK		 5031 {
5032 fputs ("%g0", file);
5033 return;
5034 }
5035 else
5036 break;
5037
61a55e8b 5038 case 'A':
ab835497
RK		 5039 switch (GET_CODE (x))
5040 {
5041 case IOR: fputs ("or", file); break;
5042 case AND: fputs ("and", file); break;
5043 case XOR: fputs ("xor", file); break;
b3b1e8bd 5044 default: output_operand_lossage ("Invalid %%A operand");
ab835497
RK		 5045 }
5046 return;
5047
5048 case 'B':
5049 switch (GET_CODE (x))
5050 {
5051 case IOR: fputs ("orn", file); break;
5052 case AND: fputs ("andn", file); break;
5053 case XOR: fputs ("xnor", file); break;
b3b1e8bd 5054 default: output_operand_lossage ("Invalid %%B operand");
ab835497
RK		 5055 }
5056 return;
5057
304b7a23
DE		 5058 /* These are used by the conditional move instructions. */
5059 case 'c' :
61a55e8b 5060 case 'C':
304b7a23
DE		 5061 {
5062 enum rtx_code rc = (code == 'c'
5063 ? reverse_condition (GET_CODE (x))
5064 : GET_CODE (x));
5065 switch (rc)
5066 {
5067 case NE: fputs ("ne", file); break;
5068 case EQ: fputs ("e", file); break;
5069 case GE: fputs ("ge", file); break;
5070 case GT: fputs ("g", file); break;
5071 case LE: fputs ("le", file); break;
5072 case LT: fputs ("l", file); break;
5073 case GEU: fputs ("geu", file); break;
5074 case GTU: fputs ("gu", file); break;
5075 case LEU: fputs ("leu", file); break;
5076 case LTU: fputs ("lu", file); break;
5077 default: output_operand_lossage (code == 'c'
5078 ? "Invalid %%c operand"
5079 : "Invalid %%C operand");
5080 }
5081 return;
5082 }
5083
5084 /* These are used by the movr instruction pattern. */
5085 case 'd':
61a55e8b 5086 case 'D':
304b7a23
DE		 5087 {
5088 enum rtx_code rc = (code == 'd'
5089 ? reverse_condition (GET_CODE (x))
5090 : GET_CODE (x));
5091 switch (rc)
5092 {
5093 case NE: fputs ("ne", file); break;
5094 case EQ: fputs ("e", file); break;
5095 case GE: fputs ("gez", file); break;
5096 case LT: fputs ("lz", file); break;
5097 case LE: fputs ("lez", file); break;
5098 case GT: fputs ("gz", file); break;
5099 default: output_operand_lossage (code == 'd'
5100 ? "Invalid %%d operand"
5101 : "Invalid %%D operand");
5102 }
5103 return;
5104 }
61a55e8b 5105
ab835497
RK		 5106 case 'b':
5107 {
5108 /* Print a sign-extended character. */
5109 int i = INTVAL (x) & 0xff;
5110 if (i & 0x80)
5111 i |= 0xffffff00;
5112 fprintf (file, "%d", i);
5113 return;
5114 }
5115
d2889939
RK		 5116 case 'f':
5117 /* Operand must be a MEM; write its address. */
5118 if (GET_CODE (x) != MEM)
5119 output_operand_lossage ("Invalid %%f operand");
5120 output_address (XEXP (x, 0));
5121 return;
5122
ab835497
RK		 5123 case 0:
5124 /* Do nothing special. */
5125 break;
5126
5127 default:
5128 /* Undocumented flag. */
415f583e 5129 output_operand_lossage ("invalid operand output code");
ab835497
RK		 5130 }
5131
5132 if (GET_CODE (x) == REG)
5133 fputs (reg_names[REGNO (x)], file);
5134 else if (GET_CODE (x) == MEM)
5135 {
5136 fputc ('[', file);
ab835497 5137 /* Poor Sun assembler doesn't understand absolute addressing. */
c4ce6853
DE		 5138 if (CONSTANT_P (XEXP (x, 0))
5139 && ! TARGET_LIVE_G0)
ab835497
RK		 5140 fputs ("%g0+", file);
5141 output_address (XEXP (x, 0));
5142 fputc (']', file);
5143 }
5144 else if (GET_CODE (x) == HIGH)
5145 {
5146 fputs ("%hi(", file);
5147 output_addr_const (file, XEXP (x, 0));
5148 fputc (')', file);
5149 }
5150 else if (GET_CODE (x) == LO_SUM)
5151 {
5152 print_operand (file, XEXP (x, 0), 0);
e0d80184
DM		 5153 if (TARGET_CM_MEDMID)
5154 fputs ("+%l44(", file);
5155 else
5156 fputs ("+%lo(", file);
ab835497
RK		 5157 output_addr_const (file, XEXP (x, 1));
5158 fputc (')', file);
5159 }
e601abce
JW		 5160 else if (GET_CODE (x) == CONST_DOUBLE
5161 && (GET_MODE (x) == VOIDmode
5162 || GET_MODE_CLASS (GET_MODE (x)) == MODE_INT))
ab835497
RK		 5163 {
5164 if (CONST_DOUBLE_HIGH (x) == 0)
5165 fprintf (file, "%u", CONST_DOUBLE_LOW (x));
5166 else if (CONST_DOUBLE_HIGH (x) == -1
5167 && CONST_DOUBLE_LOW (x) < 0)
5168 fprintf (file, "%d", CONST_DOUBLE_LOW (x));
5169 else
e601abce 5170 output_operand_lossage ("long long constant not a valid immediate operand");
ab835497 5171 }
e601abce
JW		 5172 else if (GET_CODE (x) == CONST_DOUBLE)
5173 output_operand_lossage ("floating point constant not a valid immediate operand");
ab835497
RK		 5174 else { output_addr_const (file, x); }
5175}
5176\f
5177/* This function outputs assembler code for VALUE to FILE, where VALUE is
5178 a 64 bit (DImode) value. */
5179
5180/* ??? If there is a 64 bit counterpart to .word that the assembler
5181 understands, then using that would simply this code greatly. */
61a55e8b
DE		 5182/* ??? We only output .xword's for symbols and only then in environments
5183 where the assembler can handle them. */
ab835497
RK		 5184
5185void
5186output_double_int (file, value)
5187 FILE *file;
5188 rtx value;
5189{
5190 if (GET_CODE (value) == CONST_INT)
5191 {
f4f8e370
DE		 5192 /* ??? This has endianness issues. */
5193#if HOST_BITS_PER_WIDE_INT == 64
5194 HOST_WIDE_INT xword = INTVAL (value);
5195 HOST_WIDE_INT high, low;
5196
5197 high = (xword >> 32) & 0xffffffff;
5198 low = xword & 0xffffffff;
3a598fbe
JL		 5199 ASM_OUTPUT_INT (file, GEN_INT (high));
5200 ASM_OUTPUT_INT (file, GEN_INT (low));
f4f8e370 5201#else
ab835497
RK		 5202 if (INTVAL (value) < 0)
5203 ASM_OUTPUT_INT (file, constm1_rtx);
5204 else
5205 ASM_OUTPUT_INT (file, const0_rtx);
5206 ASM_OUTPUT_INT (file, value);
f4f8e370 5207#endif
ab835497
RK		 5208 }
5209 else if (GET_CODE (value) == CONST_DOUBLE)
5210 {
3a598fbe
JL		 5211 ASM_OUTPUT_INT (file, GEN_INT (CONST_DOUBLE_HIGH (value)));
5212 ASM_OUTPUT_INT (file, GEN_INT (CONST_DOUBLE_LOW (value)));
ab835497
RK		 5213 }
5214 else if (GET_CODE (value) == SYMBOL_REF
5215 || GET_CODE (value) == CONST
61a55e8b 5216 || GET_CODE (value) == PLUS
a9e27770 5217 || (TARGET_ARCH64 &&
61a55e8b 5218 (GET_CODE (value) == LABEL_REF
9fa9626b 5219 || GET_CODE (value) == CODE_LABEL
61a55e8b 5220 || GET_CODE (value) == MINUS)))
ab835497 5221 {
222a7e55
DM		 5222 if (! TARGET_V9
5223 || (TARGET_CM_MEDLOW
5224 && ! flag_pic))
61a55e8b
DE		 5225 {
5226 ASM_OUTPUT_INT (file, const0_rtx);
5227 ASM_OUTPUT_INT (file, value);
5228 }
5229 else
5230 {
5231 fprintf (file, "\t%s\t", ASM_LONGLONG);
5232 output_addr_const (file, value);
5233 fprintf (file, "\n");
5234 }
ab835497
RK		 5235 }
5236 else
5237 abort ();
5238}
210aa14a 5239\f
b0468b84
RK		 5240/* Return the value of a code used in the .proc pseudo-op that says
5241 what kind of result this function returns. For non-C types, we pick
5242 the closest C type. */
5243
77a02b01
JW		 5244#ifndef CHAR_TYPE_SIZE
5245#define CHAR_TYPE_SIZE BITS_PER_UNIT
5246#endif
5247
5248#ifndef SHORT_TYPE_SIZE
5249#define SHORT_TYPE_SIZE (BITS_PER_UNIT * 2)
5250#endif
5251
5252#ifndef INT_TYPE_SIZE
5253#define INT_TYPE_SIZE BITS_PER_WORD
5254#endif
5255
5256#ifndef LONG_TYPE_SIZE
5257#define LONG_TYPE_SIZE BITS_PER_WORD
5258#endif
5259
5260#ifndef LONG_LONG_TYPE_SIZE
5261#define LONG_LONG_TYPE_SIZE (BITS_PER_WORD * 2)
5262#endif
5263
5264#ifndef FLOAT_TYPE_SIZE
5265#define FLOAT_TYPE_SIZE BITS_PER_WORD
5266#endif
5267
5268#ifndef DOUBLE_TYPE_SIZE
5269#define DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
5270#endif
5271
5272#ifndef LONG_DOUBLE_TYPE_SIZE
5273#define LONG_DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
5274#endif
210aa14a
RS		 5275
5276unsigned long
5277sparc_type_code (type)
5278 register tree type;
5279{
5280 register unsigned long qualifiers = 0;
e5e809f4 5281 register unsigned shift;
210aa14a 5282
abc95ed3 5283 /* Only the first 30 bits of the qualifier are valid. We must refrain from
aee2c3c5
JW		 5284 setting more, since some assemblers will give an error for this. Also,
5285 we must be careful to avoid shifts of 32 bits or more to avoid getting
5286 unpredictable results. */
5287
e5e809f4 5288 for (shift = 6; shift < 30; shift += 2, type = TREE_TYPE (type))
210aa14a
RS		 5289 {
5290 switch (TREE_CODE (type))
5291 {
5292 case ERROR_MARK:
5293 return qualifiers;
5294
5295 case ARRAY_TYPE:
e5e809f4 5296 qualifiers |= (3 << shift);
210aa14a
RS		 5297 break;
5298
5299 case FUNCTION_TYPE:
5300 case METHOD_TYPE:
e5e809f4 5301 qualifiers |= (2 << shift);
210aa14a
RS		 5302 break;
5303
5304 case POINTER_TYPE:
5305 case REFERENCE_TYPE:
5306 case OFFSET_TYPE:
e5e809f4 5307 qualifiers |= (1 << shift);
210aa14a 5308 break;
ab835497 5309
210aa14a
RS		 5310 case RECORD_TYPE:
5311 return (qualifiers | 8);
5312
5313 case UNION_TYPE:
b0468b84 5314 case QUAL_UNION_TYPE:
210aa14a
RS		 5315 return (qualifiers | 9);
5316
5317 case ENUMERAL_TYPE:
5318 return (qualifiers | 10);
5319
5320 case VOID_TYPE:
5321 return (qualifiers | 16);
5322
5323 case INTEGER_TYPE:
654209e6
JW		 5324 /* If this is a range type, consider it to be the underlying
5325 type. */
5326 if (TREE_TYPE (type) != 0)
e5e809f4 5327 break;
654209e6 5328
77a02b01 5329 /* Carefully distinguish all the standard types of C,
b0468b84
RK		 5330 without messing up if the language is not C. We do this by
5331 testing TYPE_PRECISION and TREE_UNSIGNED. The old code used to
5332 look at both the names and the above fields, but that's redundant.
5333 Any type whose size is between two C types will be considered
5334 to be the wider of the two types. Also, we do not have a
5335 special code to use for "long long", so anything wider than
5336 long is treated the same. Note that we can't distinguish
5337 between "int" and "long" in this code if they are the same
5338 size, but that's fine, since neither can the assembler. */
5339
5340 if (TYPE_PRECISION (type) <= CHAR_TYPE_SIZE)
5341 return (qualifiers | (TREE_UNSIGNED (type) ? 12 : 2));
77a02b01 5342
b0468b84
RK		 5343 else if (TYPE_PRECISION (type) <= SHORT_TYPE_SIZE)
5344 return (qualifiers | (TREE_UNSIGNED (type) ? 13 : 3));
77a02b01 5345
b0468b84 5346 else if (TYPE_PRECISION (type) <= INT_TYPE_SIZE)
77a02b01
JW		 5347 return (qualifiers | (TREE_UNSIGNED (type) ? 14 : 4));
5348
b0468b84 5349 else
77a02b01
JW		 5350 return (qualifiers | (TREE_UNSIGNED (type) ? 15 : 5));
5351
210aa14a 5352 case REAL_TYPE:
e5e809f4
JL		 5353 /* If this is a range type, consider it to be the underlying
5354 type. */
5355 if (TREE_TYPE (type) != 0)
5356 break;
5357
77a02b01
JW		 5358 /* Carefully distinguish all the standard types of C,
5359 without messing up if the language is not C. */
b0468b84 5360
77a02b01 5361 if (TYPE_PRECISION (type) == FLOAT_TYPE_SIZE)
210aa14a 5362 return (qualifiers | 6);
b0468b84
RK		 5363
5364 else
5365 return (qualifiers | 7);
210aa14a
RS		 5366
5367 case COMPLEX_TYPE: /* GNU Fortran COMPLEX type. */
13d39dbc 5368 /* ??? We need to distinguish between double and float complex types,
c82aa69a
JW		 5369 but I don't know how yet because I can't reach this code from
5370 existing front-ends. */
5371 return (qualifiers | 7); /* Who knows? */
5372
210aa14a
RS		 5373 case CHAR_TYPE: /* GNU Pascal CHAR type. Not used in C. */
5374 case BOOLEAN_TYPE: /* GNU Fortran BOOLEAN type. */
5375 case FILE_TYPE: /* GNU Pascal FILE type. */
26902ae0 5376 case SET_TYPE: /* GNU Pascal SET type. */
210aa14a 5377 case LANG_TYPE: /* ? */
26902ae0 5378 return qualifiers;
210aa14a
RS		 5379
5380 default:
5381 abort (); /* Not a type! */
5382 }
5383 }
e5e809f4
JL		 5384
5385 return qualifiers;
210aa14a 5386}
ead69aea 5387\f
61a55e8b
DE		 5388/* Nested function support. */
5389
5390/* Emit RTL insns to initialize the variable parts of a trampoline.
5391 FNADDR is an RTX for the address of the function's pure code.
5392 CXT is an RTX for the static chain value for the function.
5393
5394 This takes 16 insns: 2 shifts & 2 ands (to split up addresses), 4 sethi
5395 (to load in opcodes), 4 iors (to merge address and opcodes), and 4 writes
5396 (to store insns). This is a bit excessive. Perhaps a different
5397 mechanism would be better here.
5398
849a528d 5399 Emit enough FLUSH insns to synchronize the data and instruction caches. */
61a55e8b
DE		 5400
5401void
5402sparc_initialize_trampoline (tramp, fnaddr, cxt)
5403 rtx tramp, fnaddr, cxt;
5404{
c6b0465b
JC		 5405 /* SPARC 32 bit trampoline:
5406
e0d80184
DM		 5407 sethi %hi(fn), %g1
5408 sethi %hi(static), %g2
5409 jmp %g1+%lo(fn)
5410 or %g2, %lo(static), %g2
c6b0465b
JC		 5411
5412 SETHI i,r = 00rr rrr1 00ii iiii iiii iiii iiii iiii
5413 JMPL r+i,d = 10dd ddd1 1100 0rrr rr1i iiii iiii iiii
5414 */
5415
5416 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 0)),
5417 expand_binop (SImode, ior_optab,
5418 expand_shift (RSHIFT_EXPR, SImode, fnaddr,
5419 size_int (10), 0, 1),
5420 GEN_INT (0x03000000),
5421 NULL_RTX, 1, OPTAB_DIRECT));
5422
5423 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 4)),
5424 expand_binop (SImode, ior_optab,
5425 expand_shift (RSHIFT_EXPR, SImode, cxt,
5426 size_int (10), 0, 1),
5427 GEN_INT (0x05000000),
5428 NULL_RTX, 1, OPTAB_DIRECT));
5429
5430 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 8)),
5431 expand_binop (SImode, ior_optab,
5432 expand_and (fnaddr, GEN_INT (0x3ff), NULL_RTX),
5433 GEN_INT (0x81c06000),
5434 NULL_RTX, 1, OPTAB_DIRECT));
5435
5436 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 12)),
5437 expand_binop (SImode, ior_optab,
5438 expand_and (cxt, GEN_INT (0x3ff), NULL_RTX),
5439 GEN_INT (0x8410a000),
5440 NULL_RTX, 1, OPTAB_DIRECT));
5441
254110c2 5442 emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode, tramp))));
c6b0465b
JC		 5443 /* On UltraSPARC a flush flushes an entire cache line. The trampoline is
5444 aligned on a 16 byte boundary so one flush clears it all. */
5445 if (sparc_cpu != PROCESSOR_ULTRASPARC)
5446 emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode,
5447 plus_constant (tramp, 8)))));
61a55e8b
DE		 5448}
5449
849a528d
RK		 5450/* The 64 bit version is simpler because it makes more sense to load the
5451 values as "immediate" data out of the trampoline. It's also easier since
5452 we can read the PC without clobbering a register. */
5453
61a55e8b
DE		 5454void
5455sparc64_initialize_trampoline (tramp, fnaddr, cxt)
5456 rtx tramp, fnaddr, cxt;
5457{
c6b0465b 5458 /*
e0d80184
DM		 5459 rd %pc, %g1
5460 ldx [%g1+24], %g5
5461 jmp %g5
5462 ldx [%g1+16], %g5
c6b0465b
JC		 5463 +16 bytes data
5464 */
5465
5466 emit_move_insn (gen_rtx_MEM (SImode, tramp),
5467 GEN_INT (0x83414000));
5468 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 4)),
5469 GEN_INT (0xca586018));
5470 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 8)),
5471 GEN_INT (0x81c04000));
5472 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 12)),
5473 GEN_INT (0xca586010));
5474 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 16)), cxt);
5475 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 20)), fnaddr);
254110c2 5476 emit_insn (gen_flush (validize_mem (gen_rtx_MEM (DImode, tramp))));
c6b0465b
JC		 5477 if (sparc_cpu != PROCESSOR_ULTRASPARC)
5478 emit_insn (gen_flush (validize_mem (gen_rtx_MEM (DImode, plus_constant (tramp, 8)))));
61a55e8b
DE		 5479}
5480\f
c819be5b
JW		 5481/* Subroutines to support a flat (single) register window calling
5482 convention. */
5483
5484/* Single-register window sparc stack frames look like:
5485
5486 Before call After call
5487 +-----------------------+ +-----------------------+
86735b02
DE		 5488 high | | | |
5489 mem | caller's temps. | | caller's temps. |
c819be5b
JW		 5490 | | | |
5491 +-----------------------+ +-----------------------+
5492 | | | |
5493 | arguments on stack. | | arguments on stack. |
86735b02
DE		 5494 | | | |
5495 +-----------------------+FP+92->+-----------------------+
c819be5b
JW		 5496 | 6 words to save | | 6 words to save |
5497 | arguments passed | | arguments passed |
5498 | in registers, even | | in registers, even |
86735b02
DE		 5499 | if not passed. | | if not passed. |
5500 SP+68->+-----------------------+FP+68->+-----------------------+
5501 | 1 word struct addr | | 1 word struct addr |
5502 +-----------------------+FP+64->+-----------------------+
5503 | | | |
5504 | 16 word reg save area | | 16 word reg save area |
5505 | | | |
5506 SP->+-----------------------+ FP->+-----------------------+
5507 | 4 word area for |
5508 | fp/alu reg moves |
5509 FP-16->+-----------------------+
5510 | |
5511 | local variables |
5512 | |
5513 +-----------------------+
5514 | |
c819be5b 5515 | fp register save |
86735b02
DE		 5516 | |
5517 +-----------------------+
5518 | |
c819be5b
JW		 5519 | gp register save |
5520 | |
86735b02
DE		 5521 +-----------------------+
5522 | |
c819be5b 5523 | alloca allocations |
86735b02
DE		 5524 | |
5525 +-----------------------+
5526 | |
c819be5b 5527 | arguments on stack |
86735b02
DE		 5528 | |
5529 SP+92->+-----------------------+
c819be5b 5530 | 6 words to save |
86735b02 5531 | arguments passed |
c819be5b 5532 | in registers, even |
86735b02
DE		 5533 low | if not passed. |
5534 memory SP+68->+-----------------------+
5535 | 1 word struct addr |
5536 SP+64->+-----------------------+
5537 | |
5538 I 16 word reg save area |
5539 | |
5540 SP->+-----------------------+ */
c819be5b 5541
c6aa9ce1 5542/* Structure to be filled in by sparc_flat_compute_frame_size with register
c819be5b
JW		 5543 save masks, and offsets for the current function. */
5544
5545struct sparc_frame_info
5546{
5547 unsigned long total_size; /* # bytes that the entire frame takes up. */
5548 unsigned long var_size; /* # bytes that variables take up. */
5549 unsigned long args_size; /* # bytes that outgoing arguments take up. */
5550 unsigned long extra_size; /* # bytes of extra gunk. */
5551 unsigned int gp_reg_size; /* # bytes needed to store gp regs. */
5552 unsigned int fp_reg_size; /* # bytes needed to store fp regs. */
86735b02 5553 unsigned long gmask; /* Mask of saved gp registers. */
c819be5b 5554 unsigned long fmask; /* Mask of saved fp registers. */
86735b02 5555 unsigned long reg_offset; /* Offset from new sp to store regs. */
c819be5b
JW		 5556 int initialized; /* Nonzero if frame size already calculated. */
5557};
5558
c6aa9ce1 5559/* Current frame information calculated by sparc_flat_compute_frame_size. */
c819be5b
JW		 5560struct sparc_frame_info current_frame_info;
5561
5562/* Zero structure to initialize current_frame_info. */
5563struct sparc_frame_info zero_frame_info;
5564
5565/* Tell prologue and epilogue if register REGNO should be saved / restored. */
5566
86735b02
DE		 5567#define RETURN_ADDR_REGNUM 15
5568#define FRAME_POINTER_MASK (1 << (FRAME_POINTER_REGNUM))
5569#define RETURN_ADDR_MASK (1 << (RETURN_ADDR_REGNUM))
5570
c819be5b
JW		 5571#define MUST_SAVE_REGISTER(regno) \
5572 ((regs_ever_live[regno] && !call_used_regs[regno]) \
5573 || (regno == FRAME_POINTER_REGNUM && frame_pointer_needed) \
86735b02 5574 || (regno == RETURN_ADDR_REGNUM && regs_ever_live[RETURN_ADDR_REGNUM]))
c819be5b
JW		 5575
5576/* Return the bytes needed to compute the frame pointer from the current
5577 stack pointer. */
5578
5579unsigned long
c6aa9ce1 5580sparc_flat_compute_frame_size (size)
c819be5b
JW		 5581 int size; /* # of var. bytes allocated. */
5582{
5583 int regno;
5584 unsigned long total_size; /* # bytes that the entire frame takes up. */
5585 unsigned long var_size; /* # bytes that variables take up. */
5586 unsigned long args_size; /* # bytes that outgoing arguments take up. */
5587 unsigned long extra_size; /* # extra bytes. */
5588 unsigned int gp_reg_size; /* # bytes needed to store gp regs. */
5589 unsigned int fp_reg_size; /* # bytes needed to store fp regs. */
86735b02 5590 unsigned long gmask; /* Mask of saved gp registers. */
c819be5b 5591 unsigned long fmask; /* Mask of saved fp registers. */
86735b02
DE		 5592 unsigned long reg_offset; /* Offset to register save area. */
5593 int need_aligned_p; /* 1 if need the save area 8 byte aligned. */
c819be5b
JW		 5594
5595 /* This is the size of the 16 word reg save area, 1 word struct addr
5596 area, and 4 word fp/alu register copy area. */
5597 extra_size = -STARTING_FRAME_OFFSET + FIRST_PARM_OFFSET(0);
5598 var_size = size;
5599 /* Also include the size needed for the 6 parameter registers. */
5600 args_size = current_function_outgoing_args_size + 24;
5601 total_size = var_size + args_size + extra_size;
5602 gp_reg_size = 0;
5603 fp_reg_size = 0;
86735b02 5604 gmask = 0;
c819be5b 5605 fmask = 0;
86735b02
DE		 5606 reg_offset = 0;
5607 need_aligned_p = 0;
c819be5b
JW		 5608
5609 /* Calculate space needed for gp registers. */
5610 for (regno = 1; regno <= 31; regno++)
5611 {
5612 if (MUST_SAVE_REGISTER (regno))
5613 {
86735b02
DE		 5614 /* If we need to save two regs in a row, ensure there's room to bump
5615 up the address to align it to a doubleword boundary. */
c819be5b
JW		 5616 if ((regno & 0x1) == 0 && MUST_SAVE_REGISTER (regno+1))
5617 {
5618 if (gp_reg_size % 8 != 0)
86735b02 5619 gp_reg_size += 4;
c819be5b 5620 gp_reg_size += 2 * UNITS_PER_WORD;
86735b02 5621 gmask |= 3 << regno;
c819be5b 5622 regno++;
86735b02 5623 need_aligned_p = 1;
c819be5b
JW		 5624 }
5625 else
5626 {
5627 gp_reg_size += UNITS_PER_WORD;
86735b02 5628 gmask |= 1 << regno;
c819be5b
JW		 5629 }
5630 }
5631 }
c819be5b
JW		 5632
5633 /* Calculate space needed for fp registers. */
5634 for (regno = 32; regno <= 63; regno++)
5635 {
5636 if (regs_ever_live[regno] && !call_used_regs[regno])
5637 {
5638 fp_reg_size += UNITS_PER_WORD;
5639 fmask |= 1 << (regno - 32);
5640 }
5641 }
5642
86735b02
DE		 5643 if (gmask || fmask)
5644 {
5645 int n;
5646 reg_offset = FIRST_PARM_OFFSET(0) + args_size;
5647 /* Ensure save area is 8 byte aligned if we need it. */
5648 n = reg_offset % 8;
5649 if (need_aligned_p && n != 0)
5650 {
5651 total_size += 8 - n;
5652 reg_offset += 8 - n;
5653 }
5654 total_size += gp_reg_size + fp_reg_size;
5655 }
c819be5b 5656
86735b02 5657 /* ??? This looks a little suspicious. Clarify. */
c819be5b
JW		 5658 if (total_size == extra_size)
5659 total_size = extra_size = 0;
5660
5661 total_size = SPARC_STACK_ALIGN (total_size);
5662
5663 /* Save other computed information. */
5664 current_frame_info.total_size = total_size;
5665 current_frame_info.var_size = var_size;
5666 current_frame_info.args_size = args_size;
5667 current_frame_info.extra_size = extra_size;
5668 current_frame_info.gp_reg_size = gp_reg_size;
5669 current_frame_info.fp_reg_size = fp_reg_size;
86735b02 5670 current_frame_info.gmask = gmask;
c819be5b 5671 current_frame_info.fmask = fmask;
86735b02 5672 current_frame_info.reg_offset = reg_offset;
c819be5b
JW		 5673 current_frame_info.initialized = reload_completed;
5674
c819be5b
JW		 5675 /* Ok, we're done. */
5676 return total_size;
5677}
5678\f
86735b02
DE		 5679/* Save/restore registers in GMASK and FMASK at register BASE_REG plus offset
5680 OFFSET.
5681
5682 BASE_REG must be 8 byte aligned. This allows us to test OFFSET for
5683 appropriate alignment and use DOUBLEWORD_OP when we can. We assume
5684 [BASE_REG+OFFSET] will always be a valid address.
5685
5686 WORD_OP is either "st" for save, "ld" for restore.
5687 DOUBLEWORD_OP is either "std" for save, "ldd" for restore. */
c819be5b
JW		 5688
5689void
96987e96
DE		 5690sparc_flat_save_restore (file, base_reg, offset, gmask, fmask, word_op,
5691 doubleword_op, base_offset)
86735b02
DE		 5692 FILE *file;
5693 char *base_reg;
5694 unsigned int offset;
5695 unsigned long gmask;
5696 unsigned long fmask;
5697 char *word_op;
5698 char *doubleword_op;
c53aa195 5699 unsigned long base_offset;
c819be5b
JW		 5700{
5701 int regno;
c819be5b 5702
86735b02
DE		 5703 if (gmask == 0 && fmask == 0)
5704 return;
c819be5b 5705
86735b02
DE		 5706 /* Save registers starting from high to low. We've already saved the
5707 previous frame pointer and previous return address for the debugger's
5708 sake. The debugger allows us to not need a nop in the epilog if at least
5709 one register is reloaded in addition to return address. */
c819be5b 5710
86735b02 5711 if (gmask)
c819be5b
JW		 5712 {
5713 for (regno = 1; regno <= 31; regno++)
5714 {
86735b02 5715 if ((gmask & (1L << regno)) != 0)
c819be5b 5716 {
86735b02 5717 if ((regno & 0x1) == 0 && ((gmask & (1L << (regno+1))) != 0))
c819be5b 5718 {
86735b02
DE		 5719 /* We can save two registers in a row. If we're not at a
5720 double word boundary, move to one.
5721 sparc_flat_compute_frame_size ensures there's room to do
5722 this. */
5723 if (offset % 8 != 0)
5724 offset += UNITS_PER_WORD;
5725
c819be5b 5726 if (word_op[0] == 's')
c53aa195 5727 {
e0d80184 5728 fprintf (file, "\t%s\t%s, [%s+%d]\n",
c53aa195
JM		 5729 doubleword_op, reg_names[regno],
5730 base_reg, offset);
0021b564 5731 if (dwarf2out_do_frame ())
c53aa195 5732 {
96987e96 5733 char *l = dwarf2out_cfi_label ();
c53aa195
JM		 5734 dwarf2out_reg_save (l, regno, offset + base_offset);
5735 dwarf2out_reg_save
5736 (l, regno+1, offset+base_offset + UNITS_PER_WORD);
5737 }
c53aa195 5738 }
c819be5b 5739 else
e0d80184 5740 fprintf (file, "\t%s\t[%s+%d], %s\n",
86735b02 5741 doubleword_op, base_reg, offset,
c819be5b
JW		 5742 reg_names[regno]);
5743
86735b02 5744 offset += 2 * UNITS_PER_WORD;
c819be5b
JW		 5745 regno++;
5746 }
5747 else
5748 {
5749 if (word_op[0] == 's')
c53aa195 5750 {
e0d80184 5751 fprintf (file, "\t%s\t%s, [%s+%d]\n",
c53aa195
JM		 5752 word_op, reg_names[regno],
5753 base_reg, offset);
0021b564 5754 if (dwarf2out_do_frame ())
c53aa195 5755 dwarf2out_reg_save ("", regno, offset + base_offset);
c53aa195 5756 }
c819be5b 5757 else
e0d80184 5758 fprintf (file, "\t%s\t[%s+%d], %s\n",
86735b02 5759 word_op, base_reg, offset, reg_names[regno]);
c819be5b 5760
86735b02 5761 offset += UNITS_PER_WORD;
c819be5b
JW		 5762 }
5763 }
5764 }
5765 }
5766
5767 if (fmask)
5768 {
5769 for (regno = 32; regno <= 63; regno++)
5770 {
5771 if ((fmask & (1L << (regno - 32))) != 0)
5772 {
5773 if (word_op[0] == 's')
c53aa195 5774 {
e0d80184 5775 fprintf (file, "\t%s\t%s, [%s+%d]\n",
c53aa195
JM		 5776 word_op, reg_names[regno],
5777 base_reg, offset);
0021b564 5778 if (dwarf2out_do_frame ())
c53aa195 5779 dwarf2out_reg_save ("", regno, offset + base_offset);
c53aa195 5780 }
c819be5b 5781 else
e0d80184 5782 fprintf (file, "\t%s\t[%s+%d], %s\n",
86735b02 5783 word_op, base_reg, offset, reg_names[regno]);
c819be5b 5784
86735b02 5785 offset += UNITS_PER_WORD;
c819be5b
JW		 5786 }
5787 }
5788 }
5789}
5790\f
5791/* Set up the stack and frame (if desired) for the function. */
5792
5793void
c6aa9ce1 5794sparc_flat_output_function_prologue (file, size)
c819be5b
JW		 5795 FILE *file;
5796 int size;
5797{
c819be5b 5798 char *sp_str = reg_names[STACK_POINTER_REGNUM];
86735b02 5799 unsigned long gmask = current_frame_info.gmask;
a07c1915 5800
c6aa9ce1 5801 /* This is only for the human reader. */
bf62bbf1 5802 fprintf (file, "\t%s#PROLOGUE# 0\n", ASM_COMMENT_START);
5e9defae 5803 fprintf (file, "\t%s# vars= %ld, regs= %d/%d, args= %d, extra= %ld\n",
bf62bbf1 5804 ASM_COMMENT_START,
86735b02
DE		 5805 current_frame_info.var_size,
5806 current_frame_info.gp_reg_size / 4,
9f8b85b8 5807 current_frame_info.fp_reg_size / 4,
86735b02
DE		 5808 current_function_outgoing_args_size,
5809 current_frame_info.extra_size);
c819be5b
JW		 5810
5811 size = SPARC_STACK_ALIGN (size);
86735b02
DE		 5812 size = (! current_frame_info.initialized
5813 ? sparc_flat_compute_frame_size (size)
5814 : current_frame_info.total_size);
c819be5b 5815
86735b02
DE		 5816 /* These cases shouldn't happen. Catch them now. */
5817 if (size == 0 && (gmask || current_frame_info.fmask))
5818 abort ();
c819be5b 5819
86735b02
DE		 5820 /* Allocate our stack frame by decrementing %sp.
5821 At present, the only algorithm gdb can use to determine if this is a
5822 flat frame is if we always set %i7 if we set %sp. This can be optimized
5823 in the future by putting in some sort of debugging information that says
5824 this is a `flat' function. However, there is still the case of debugging
5825 code without such debugging information (including cases where most fns
5826 have such info, but there is one that doesn't). So, always do this now
5827 so we don't get a lot of code out there that gdb can't handle.
5828 If the frame pointer isn't needn't then that's ok - gdb won't be able to
5829 distinguish us from a non-flat function but there won't (and shouldn't)
5830 be any differences anyway. The return pc is saved (if necessary) right
5831 after %i7 so gdb won't have to look too far to find it. */
5832 if (size > 0)
c819be5b 5833 {
86735b02 5834 unsigned int reg_offset = current_frame_info.reg_offset;
c6aa9ce1 5835 char *fp_str = reg_names[FRAME_POINTER_REGNUM];
86735b02
DE		 5836 char *t1_str = "%g1";
5837
5838 /* Things get a little tricky if local variables take up more than ~4096
5839 bytes and outgoing arguments take up more than ~4096 bytes. When that
5840 happens, the register save area can't be accessed from either end of
5841 the frame. Handle this by decrementing %sp to the start of the gp
5842 register save area, save the regs, update %i7, and then set %sp to its
5843 final value. Given that we only have one scratch register to play
5844 with it is the cheapest solution, and it helps gdb out as it won't
5845 slow down recognition of flat functions.
5846 Don't change the order of insns emitted here without checking with
5847 the gdb folk first. */
5848
ddd5a7c1 5849 /* Is the entire register save area offsettable from %sp? */
86735b02
DE		 5850 if (reg_offset < 4096 - 64 * UNITS_PER_WORD)
5851 {
5852 if (size <= 4096)
5853 {
e0d80184 5854 fprintf (file, "\tadd\t%s, %d, %s\n",
86735b02
DE		 5855 sp_str, -size, sp_str);
5856 if (gmask & FRAME_POINTER_MASK)
5857 {
e0d80184 5858 fprintf (file, "\tst\t%s, [%s+%d]\n",
86735b02 5859 fp_str, sp_str, reg_offset);
e0d80184 5860 fprintf (file, "\tsub\t%s, %d, %s\t%s# set up frame pointer\n",
bf62bbf1 5861 sp_str, -size, fp_str, ASM_COMMENT_START);
86735b02
DE		 5862 reg_offset += 4;
5863 }
5864 }
5865 else
5866 {
e0d80184 5867 fprintf (file, "\tset\t%d, %s\n\tsub\t%s, %s, %s\n",
86735b02
DE		 5868 size, t1_str, sp_str, t1_str, sp_str);
5869 if (gmask & FRAME_POINTER_MASK)
5870 {
e0d80184 5871 fprintf (file, "\tst\t%s, [%s+%d]\n",
86735b02 5872 fp_str, sp_str, reg_offset);
e0d80184 5873 fprintf (file, "\tadd\t%s, %s, %s\t%s# set up frame pointer\n",
bf62bbf1 5874 sp_str, t1_str, fp_str, ASM_COMMENT_START);
86735b02
DE		 5875 reg_offset += 4;
5876 }
5877 }
0021b564 5878 if (dwarf2out_do_frame ())
c53aa195 5879 {
96987e96 5880 char *l = dwarf2out_cfi_label ();
c53aa195
JM		 5881 if (gmask & FRAME_POINTER_MASK)
5882 {
5883 dwarf2out_reg_save (l, FRAME_POINTER_REGNUM,
5884 reg_offset - 4 - size);
5885 dwarf2out_def_cfa (l, FRAME_POINTER_REGNUM, 0);
5886 }
5887 else
5888 dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, size);
5889 }
86735b02
DE		 5890 if (gmask & RETURN_ADDR_MASK)
5891 {
e0d80184 5892 fprintf (file, "\tst\t%s, [%s+%d]\n",
86735b02 5893 reg_names[RETURN_ADDR_REGNUM], sp_str, reg_offset);
0021b564 5894 if (dwarf2out_do_frame ())
c53aa195 5895 dwarf2out_return_save ("", reg_offset - size);
86735b02
DE		 5896 reg_offset += 4;
5897 }
5898 sparc_flat_save_restore (file, sp_str, reg_offset,
5899 gmask & ~(FRAME_POINTER_MASK | RETURN_ADDR_MASK),
5900 current_frame_info.fmask,
84e884e9 5901 "st", "std", -size);
86735b02 5902 }
c819be5b 5903 else
86735b02
DE		 5904 {
5905 /* Subtract %sp in two steps, but make sure there is always a
5906 64 byte register save area, and %sp is properly aligned. */
5907 /* Amount to decrement %sp by, the first time. */
5908 unsigned int size1 = ((size - reg_offset + 64) + 15) & -16;
5909 /* Offset to register save area from %sp. */
5910 unsigned int offset = size1 - (size - reg_offset);
5911
5912 if (size1 <= 4096)
5913 {
e0d80184 5914 fprintf (file, "\tadd\t%s, %d, %s\n",
86735b02
DE		 5915 sp_str, -size1, sp_str);
5916 if (gmask & FRAME_POINTER_MASK)
5917 {
e0d80184 5918 fprintf (file, "\tst\t%s, [%s+%d]\n\tsub\t%s, %d, %s\t%s# set up frame pointer\n",
bf62bbf1
DE		 5919 fp_str, sp_str, offset, sp_str, -size1, fp_str,
5920 ASM_COMMENT_START);
86735b02
DE		 5921 offset += 4;
5922 }
5923 }
5924 else
5925 {
e0d80184 5926 fprintf (file, "\tset\t%d, %s\n\tsub\t%s, %s, %s\n",
86735b02
DE		 5927 size1, t1_str, sp_str, t1_str, sp_str);
5928 if (gmask & FRAME_POINTER_MASK)
5929 {
e0d80184 5930 fprintf (file, "\tst\t%s, [%s+%d]\n\tadd\t%s, %s, %s\t%s# set up frame pointer\n",
bf62bbf1
DE		 5931 fp_str, sp_str, offset, sp_str, t1_str, fp_str,
5932 ASM_COMMENT_START);
86735b02
DE		 5933 offset += 4;
5934 }
5935 }
0021b564 5936 if (dwarf2out_do_frame ())
c53aa195 5937 {
96987e96 5938 char *l = dwarf2out_cfi_label ();
c53aa195
JM		 5939 if (gmask & FRAME_POINTER_MASK)
5940 {
5941 dwarf2out_reg_save (l, FRAME_POINTER_REGNUM,
5942 offset - 4 - size1);
5943 dwarf2out_def_cfa (l, FRAME_POINTER_REGNUM, 0);
5944 }
5945 else
5946 dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, size1);
5947 }
86735b02
DE		 5948 if (gmask & RETURN_ADDR_MASK)
5949 {
e0d80184 5950 fprintf (file, "\tst\t%s, [%s+%d]\n",
86735b02 5951 reg_names[RETURN_ADDR_REGNUM], sp_str, offset);
0021b564 5952 if (dwarf2out_do_frame ())
c53aa195
JM		 5953 /* offset - size1 == reg_offset - size
5954 if reg_offset were updated above like offset. */
5955 dwarf2out_return_save ("", offset - size1);
86735b02
DE		 5956 offset += 4;
5957 }
5958 sparc_flat_save_restore (file, sp_str, offset,
5959 gmask & ~(FRAME_POINTER_MASK | RETURN_ADDR_MASK),
5960 current_frame_info.fmask,
84e884e9 5961 "st", "std", -size1);
e0d80184 5962 fprintf (file, "\tset\t%d, %s\n\tsub\t%s, %s, %s\n",
86735b02 5963 size - size1, t1_str, sp_str, t1_str, sp_str);
0021b564 5964 if (dwarf2out_do_frame ())
c53aa195
JM		 5965 if (! (gmask & FRAME_POINTER_MASK))
5966 dwarf2out_def_cfa ("", STACK_POINTER_REGNUM, size);
86735b02 5967 }
c819be5b 5968 }
c6aa9ce1 5969
bf62bbf1 5970 fprintf (file, "\t%s#PROLOGUE# 1\n", ASM_COMMENT_START);
c819be5b
JW		 5971}
5972\f
5973/* Do any necessary cleanup after a function to restore stack, frame,
5974 and regs. */
5975
5976void
c6aa9ce1 5977sparc_flat_output_function_epilogue (file, size)
c819be5b
JW		 5978 FILE *file;
5979 int size;
5980{
c819be5b
JW		 5981 rtx epilogue_delay = current_function_epilogue_delay_list;
5982 int noepilogue = FALSE;
c819be5b 5983
c6aa9ce1 5984 /* This is only for the human reader. */
bf62bbf1 5985 fprintf (file, "\t%s#EPILOGUE#\n", ASM_COMMENT_START);
c6aa9ce1 5986
c819be5b
JW		 5987 /* The epilogue does not depend on any registers, but the stack
5988 registers, so we assume that if we have 1 pending nop, it can be
5989 ignored, and 2 it must be filled (2 nops occur for integer
5990 multiply and divide). */
5991
5992 size = SPARC_STACK_ALIGN (size);
86735b02 5993 size = (!current_frame_info.initialized
c6aa9ce1 5994 ? sparc_flat_compute_frame_size (size)
c819be5b
JW		 5995 : current_frame_info.total_size);
5996
86735b02 5997 if (size == 0 && epilogue_delay == 0)
c819be5b
JW		 5998 {
5999 rtx insn = get_last_insn ();
6000
6001 /* If the last insn was a BARRIER, we don't have to write any code
6002 because a jump (aka return) was put there. */
6003 if (GET_CODE (insn) == NOTE)
6004 insn = prev_nonnote_insn (insn);
6005 if (insn && GET_CODE (insn) == BARRIER)
6006 noepilogue = TRUE;
6007 }
6008
6009 if (!noepilogue)
6010 {
86735b02
DE		 6011 unsigned int reg_offset = current_frame_info.reg_offset;
6012 unsigned int size1;
6013 char *sp_str = reg_names[STACK_POINTER_REGNUM];
6014 char *fp_str = reg_names[FRAME_POINTER_REGNUM];
6015 char *t1_str = "%g1";
6016
c819be5b
JW		 6017 /* In the reload sequence, we don't need to fill the load delay
6018 slots for most of the loads, also see if we can fill the final
6019 delay slot if not otherwise filled by the reload sequence. */
6020
86735b02 6021 if (size > 4095)
e0d80184 6022 fprintf (file, "\tset\t%d, %s\n", size, t1_str);
c819be5b
JW		 6023
6024 if (frame_pointer_needed)
6025 {
86735b02 6026 if (size > 4095)
e0d80184 6027 fprintf (file,"\tsub\t%s, %s, %s\t\t%s# sp not trusted here\n",
bf62bbf1 6028 fp_str, t1_str, sp_str, ASM_COMMENT_START);
c819be5b 6029 else
e0d80184 6030 fprintf (file,"\tsub\t%s, %d, %s\t\t%s# sp not trusted here\n",
bf62bbf1 6031 fp_str, size, sp_str, ASM_COMMENT_START);
c819be5b
JW		 6032 }
6033
ddd5a7c1 6034 /* Is the entire register save area offsettable from %sp? */
86735b02
DE		 6035 if (reg_offset < 4096 - 64 * UNITS_PER_WORD)
6036 {
6037 size1 = 0;
6038 }
6039 else
6040 {
6041 /* Restore %sp in two steps, but make sure there is always a
6042 64 byte register save area, and %sp is properly aligned. */
6043 /* Amount to increment %sp by, the first time. */
6044 size1 = ((reg_offset - 64 - 16) + 15) & -16;
6045 /* Offset to register save area from %sp. */
6046 reg_offset = size1 - reg_offset;
6047
e0d80184 6048 fprintf (file, "\tset\t%d, %s\n\tadd\t%s, %s, %s\n",
86735b02
DE		 6049 size1, t1_str, sp_str, t1_str, sp_str);
6050 }
6051
6052 /* We must restore the frame pointer and return address reg first
6053 because they are treated specially by the prologue output code. */
6054 if (current_frame_info.gmask & FRAME_POINTER_MASK)
6055 {
e0d80184 6056 fprintf (file, "\tld\t[%s+%d], %s\n",
86735b02
DE		 6057 sp_str, reg_offset, fp_str);
6058 reg_offset += 4;
6059 }
6060 if (current_frame_info.gmask & RETURN_ADDR_MASK)
6061 {
e0d80184 6062 fprintf (file, "\tld\t[%s+%d], %s\n",
86735b02
DE		 6063 sp_str, reg_offset, reg_names[RETURN_ADDR_REGNUM]);
6064 reg_offset += 4;
6065 }
6066
6067 /* Restore any remaining saved registers. */
6068 sparc_flat_save_restore (file, sp_str, reg_offset,
6069 current_frame_info.gmask & ~(FRAME_POINTER_MASK | RETURN_ADDR_MASK),
6070 current_frame_info.fmask,
c53aa195 6071 "ld", "ldd", 0);
86735b02
DE		 6072
6073 /* If we had to increment %sp in two steps, record it so the second
6074 restoration in the epilogue finishes up. */
6075 if (size1 > 0)
6076 {
6077 size -= size1;
6078 if (size > 4095)
e0d80184 6079 fprintf (file, "\tset\t%d, %s\n",
86735b02
DE		 6080 size, t1_str);
6081 }
c819be5b 6082
c819be5b 6083 if (current_function_returns_struct)
e0d80184 6084 fprintf (file, "\tjmp\t%%o7+12\n");
c819be5b
JW		 6085 else
6086 fprintf (file, "\tretl\n");
6087
6088 /* If the only register saved is the return address, we need a
6089 nop, unless we have an instruction to put into it. Otherwise
6090 we don't since reloading multiple registers doesn't reference
6091 the register being loaded. */
6092
6093 if (epilogue_delay)
6094 {
86735b02 6095 if (size)
c819be5b
JW		 6096 abort ();
6097 final_scan_insn (XEXP (epilogue_delay, 0), file, 1, -2, 1);
6098 }
6099
86735b02 6100 else if (size > 4095)
e0d80184 6101 fprintf (file, "\tadd\t%s, %s, %s\n", sp_str, t1_str, sp_str);
c819be5b 6102
86735b02 6103 else if (size > 0)
e0d80184 6104 fprintf (file, "\tadd\t%s, %d, %s\n", sp_str, size, sp_str);
c819be5b
JW		 6105
6106 else
6107 fprintf (file, "\tnop\n");
6108 }
6109
6110 /* Reset state info for each function. */
6111 current_frame_info = zero_frame_info;
e0d80184
DM		 6112
6113 sparc_output_deferred_case_vectors ();
c819be5b
JW		 6114}
6115\f
6116/* Define the number of delay slots needed for the function epilogue.
6117
6118 On the sparc, we need a slot if either no stack has been allocated,
6119 or the only register saved is the return register. */
6120
6121int
c6aa9ce1 6122sparc_flat_epilogue_delay_slots ()
c819be5b
JW		 6123{
6124 if (!current_frame_info.initialized)
c6aa9ce1 6125 (void) sparc_flat_compute_frame_size (get_frame_size ());
c819be5b
JW		 6126
6127 if (current_frame_info.total_size == 0)
6128 return 1;
6129
c819be5b
JW		 6130 return 0;
6131}
6132
6133/* Return true is TRIAL is a valid insn for the epilogue delay slot.
6134 Any single length instruction which doesn't reference the stack or frame
6135 pointer is OK. */
6136
6137int
c6aa9ce1 6138sparc_flat_eligible_for_epilogue_delay (trial, slot)
c819be5b 6139 rtx trial;
db3d4438 6140 int slot ATTRIBUTE_UNUSED;
c819be5b 6141{
c4ce6853
DE		 6142 rtx pat = PATTERN (trial);
6143
6144 if (get_attr_length (trial) != 1)
6145 return 0;
6146
6147 /* If %g0 is live, there are lots of things we can't handle.
6148 Rather than trying to find them all now, let's punt and only
6149 optimize things as necessary. */
6150 if (TARGET_LIVE_G0)
6151 return 0;
6152
6153 if (! reg_mentioned_p (stack_pointer_rtx, pat)
6154 && ! reg_mentioned_p (frame_pointer_rtx, pat))
c819be5b 6155 return 1;
c4ce6853 6156
c819be5b
JW		 6157 return 0;
6158}
dbb54862
JW		 6159\f
6160/* Adjust the cost of a scheduling dependency. Return the new cost of
6161 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
6162
6163int
6164supersparc_adjust_cost (insn, link, dep_insn, cost)
6165 rtx insn;
6166 rtx link;
6167 rtx dep_insn;
6168 int cost;
6169{
6170 enum attr_type insn_type;
6171
6172 if (! recog_memoized (insn))
6173 return 0;
6174
6175 insn_type = get_attr_type (insn);
6176
6177 if (REG_NOTE_KIND (link) == 0)
6178 {
6179 /* Data dependency; DEP_INSN writes a register that INSN reads some
6180 cycles later. */
6181
6182 /* if a load, then the dependence must be on the memory address;
3bc8b61e
DM		 6183 add an extra "cycle". Note that the cost could be two cycles
6184 if the reg was written late in an instruction group; we ca not tell
dbb54862
JW		 6185 here. */
6186 if (insn_type == TYPE_LOAD || insn_type == TYPE_FPLOAD)
6187 return cost + 3;
6188
6189 /* Get the delay only if the address of the store is the dependence. */
6190 if (insn_type == TYPE_STORE || insn_type == TYPE_FPSTORE)
6191 {
6192 rtx pat = PATTERN(insn);
6193 rtx dep_pat = PATTERN (dep_insn);
6194
6195 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
3bc8b61e 6196 return cost; /* This should not happen! */
dbb54862
JW		 6197
6198 /* The dependency between the two instructions was on the data that
6199 is being stored. Assume that this implies that the address of the
6200 store is not dependent. */
6201 if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat)))
6202 return cost;
6203
6204 return cost + 3; /* An approximation. */
6205 }
6206
6207 /* A shift instruction cannot receive its data from an instruction
6208 in the same cycle; add a one cycle penalty. */
6209 if (insn_type == TYPE_SHIFT)
6210 return cost + 3; /* Split before cascade into shift. */
6211 }
6212 else
6213 {
6214 /* Anti- or output- dependency; DEP_INSN reads/writes a register that
6215 INSN writes some cycles later. */
6216
6217 /* These are only significant for the fpu unit; writing a fp reg before
6218 the fpu has finished with it stalls the processor. */
6219
6220 /* Reusing an integer register causes no problems. */
6221 if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT)
6222 return 0;
6223 }
6224
6225 return cost;
6226}
bfd6bc60 6227
3bc8b61e
DM		 6228/* This describes the state of the UltraSPARC pipeline during
6229 instruction scheduling. */
6230
b96a5ea5
KG		 6231#define TMASK(__x) ((unsigned)1 << ((int)(__x)))
6232#define UMASK(__x) ((unsigned)1 << ((int)(__x)))
3bc8b61e
DM		 6233
6234enum ultra_code { NONE=0, /* no insn at all */
6235 IEU0, /* shifts and conditional moves */
6236 IEU1, /* condition code setting insns, calls+jumps */
6237 IEUN, /* all other single cycle ieu insns */
6238 LSU, /* loads and stores */
6239 CTI, /* branches */
6240 FPM, /* FPU pipeline 1, multiplies and divides */
6241 FPA, /* FPU pipeline 2, all other operations */
6242 SINGLE, /* single issue instructions */
6243 NUM_ULTRA_CODES };
6244
6245static char *ultra_code_names[NUM_ULTRA_CODES] = {
6246 "NONE", "IEU0", "IEU1", "IEUN", "LSU", "CTI",
6247 "FPM", "FPA", "SINGLE" };
6248
6249struct ultrasparc_pipeline_state {
6250 /* The insns in this group. */
6251 rtx group[4];
6252
6253 /* The code for each insn. */
6254 enum ultra_code codes[4];
6255
6256 /* Which insns in this group have been committed by the
6257 scheduler. This is how we determine how many more
6258 can issue this cycle. */
6259 char commit[4];
6260
6261 /* How many insns in this group. */
6262 char group_size;
6263
6264 /* Mask of free slots still in this group. */
6265 char free_slot_mask;
6266
6267 /* The slotter uses the following to determine what other
6268 insn types can still make their way into this group. */
6269 char contents [NUM_ULTRA_CODES];
6270 char num_ieu_insns;
6271};
6272
6273#define ULTRA_NUM_HIST 8
6274static struct ultrasparc_pipeline_state ultra_pipe_hist[ULTRA_NUM_HIST];
6275static int ultra_cur_hist;
6276static int ultra_cycles_elapsed;
6277
6278#define ultra_pipe (ultra_pipe_hist[ultra_cur_hist])
6279
6280/* Given TYPE_MASK compute the ultra_code it has. */
6281static enum ultra_code
6282ultra_code_from_mask (type_mask)
6283 int type_mask;
6284{
3bc8b61e
DM		 6285 if (type_mask & (TMASK (TYPE_SHIFT) | TMASK (TYPE_CMOVE)))
6286 return IEU0;
6287 else if (type_mask & (TMASK (TYPE_COMPARE) |
6288 TMASK (TYPE_CALL) |
6289 TMASK (TYPE_UNCOND_BRANCH)))
6290 return IEU1;
6291 else if (type_mask & (TMASK (TYPE_IALU) | TMASK (TYPE_BINARY) |
6292 TMASK (TYPE_MOVE) | TMASK (TYPE_UNARY)))
6293 return IEUN;
6294 else if (type_mask & (TMASK (TYPE_LOAD) | TMASK (TYPE_SLOAD) |
6295 TMASK (TYPE_STORE) | TMASK (TYPE_FPLOAD) |
6296 TMASK (TYPE_FPSTORE)))
6297 return LSU;
6298 else if (type_mask & (TMASK (TYPE_FPMUL) | TMASK (TYPE_FPDIVS) |
6299 TMASK (TYPE_FPDIVD) | TMASK (TYPE_FPSQRT)))
6300 return FPM;
6301 else if (type_mask & (TMASK (TYPE_FPMOVE) | TMASK (TYPE_FPCMOVE) |
6302 TMASK (TYPE_FP) | TMASK (TYPE_FPCMP)))
6303 return FPA;
6304 else if (type_mask & TMASK (TYPE_BRANCH))
6305 return CTI;
6306
6307 return SINGLE;
6308}
6309
6310/* Check INSN (a conditional move) and make sure that it's
6311 results are available at this cycle. Return 1 if the
6312 results are in fact ready. */
6313static int
6314ultra_cmove_results_ready_p (insn)
6315 rtx insn;
6316{
6317 struct ultrasparc_pipeline_state *up;
6318 int entry, slot;
6319
6320 /* If this got dispatched in the previous
6321 group, the results are not ready. */
ddf80874 6322 entry = (ultra_cur_hist - 1) % (ULTRA_NUM_HIST - 1);
3bc8b61e
DM		 6323 up = &ultra_pipe_hist[entry];
6324 slot = 4;
6325 while (--slot >= 0)
6326 if (up->group[slot] == insn)
c305b1a7 6327 return 0;
3bc8b61e 6328
c305b1a7 6329 return 1;
3bc8b61e
DM		 6330}
6331
6332/* Walk backwards in pipeline history looking for FPU
6333 operations which use a mode different than FPMODE and
6334 will create a stall if an insn using FPMODE were to be
6335 dispatched this cycle. */
6336static int
6337ultra_fpmode_conflict_exists (fpmode)
6338 enum machine_mode fpmode;
6339{
6340 int hist_ent;
6341 int hist_lim;
6342
ddf80874 6343 hist_ent = (ultra_cur_hist - 1) % (ULTRA_NUM_HIST - 1);
3bc8b61e
DM		 6344 if (ultra_cycles_elapsed < 4)
6345 hist_lim = ultra_cycles_elapsed;
6346 else
6347 hist_lim = 4;
6348 while (hist_lim > 0)
6349 {
6350 struct ultrasparc_pipeline_state *up = &ultra_pipe_hist[hist_ent];
6351 int slot = 4;
6352
6353 while (--slot >= 0)
6354 {
6355 rtx insn = up->group[slot];
6356 enum machine_mode this_mode;
3bc8b61e
DM		 6357 rtx pat;
6358
6359 if (! insn
6360 || GET_CODE (insn) != INSN
6361 || (pat = PATTERN (insn)) == 0
6362 || GET_CODE (pat) != SET)
6363 continue;
6364
6365 this_mode = GET_MODE (SET_DEST (pat));
6366 if ((this_mode != SFmode
6367 && this_mode != DFmode)
6368 || this_mode == fpmode)
6369 continue;
6370
6371 /* If it is not FMOV, FABS, FNEG, FDIV, or FSQRT then
ddf80874
DM		 6372 we will get a stall. Loads and stores are independant
6373 of these rules. */
3bc8b61e
DM		 6374 if (GET_CODE (SET_SRC (pat)) != ABS
6375 && GET_CODE (SET_SRC (pat)) != NEG
6376 && ((TMASK (get_attr_type (insn)) &
6377 (TMASK (TYPE_FPDIVS) | TMASK (TYPE_FPDIVD) |
ddf80874
DM		 6378 TMASK (TYPE_FPMOVE) | TMASK (TYPE_FPSQRT) |
6379 TMASK (TYPE_LOAD) | TMASK (TYPE_STORE))) == 0))
3bc8b61e
DM		 6380 return 1;
6381 }
6382 hist_lim--;
ddf80874 6383 hist_ent = (hist_ent - 1) % (ULTRA_NUM_HIST - 1);
3bc8b61e
DM		 6384 }
6385
6386 /* No conflicts, safe to dispatch. */
6387 return 0;
6388}
6389
6390/* Find an instruction in LIST which has one of the
6391 type attributes enumerated in TYPE_MASK. START
6392 says where to begin the search.
6393
6394 NOTE: This scheme depends upon the fact that we
6395 have less than 32 distinct type attributes. */
5a5325cb
DM		 6396
6397static int ultra_types_avail;
6398
3bc8b61e
DM		 6399static rtx *
6400ultra_find_type (type_mask, list, start)
6401 int type_mask;
6402 rtx *list;
6403 int start;
6404{
6405 int i;
6406
5a5325cb
DM		 6407 /* Short circuit if no such insn exists in the ready
6408 at the moment. */
6409 if ((type_mask & ultra_types_avail) == 0)
6410 return 0;
6411
3bc8b61e
DM		 6412 for (i = start; i >= 0; i--)
6413 {
6414 rtx insn = list[i];
6415
6416 if (recog_memoized (insn) >= 0
6417 && (TMASK(get_attr_type (insn)) & type_mask))
6418 {
ddf80874 6419 enum machine_mode fpmode = SFmode;
3bc8b61e
DM		 6420 rtx pat = 0;
6421 int slot;
6422 int check_depend = 0;
6423 int check_fpmode_conflict = 0;
6424
6425 if (GET_CODE (insn) == INSN
6426 && (pat = PATTERN(insn)) != 0
6427 && GET_CODE (pat) == SET
6428 && !(type_mask & (TMASK (TYPE_STORE) |
6429 TMASK (TYPE_FPSTORE))))
6430 {
6431 check_depend = 1;
6432 if (GET_MODE (SET_DEST (pat)) == SFmode
6433 || GET_MODE (SET_DEST (pat)) == DFmode)
6434 {
6435 fpmode = GET_MODE (SET_DEST (pat));
6436 check_fpmode_conflict = 1;
6437 }
6438 }
6439
6440 slot = 4;
6441 while(--slot >= 0)
6442 {
6443 rtx slot_insn = ultra_pipe.group[slot];
6444 rtx slot_pat;
6445
6446 /* Already issued, bad dependency, or FPU
6447 mode conflict. */
6448 if (slot_insn != 0
6449 && (slot_pat = PATTERN (slot_insn)) != 0
6450 && ((insn == slot_insn)
6451 || (check_depend == 1
6452 && GET_CODE (slot_insn) == INSN
6453 && GET_CODE (slot_pat) == SET
5a5325cb
DM		 6454 && ((GET_CODE (SET_DEST (slot_pat)) == REG
6455 && GET_CODE (SET_SRC (pat)) == REG
6456 && REGNO (SET_DEST (slot_pat)) ==
6457 REGNO (SET_SRC (pat)))
6458 || (GET_CODE (SET_DEST (slot_pat)) == SUBREG
6459 && GET_CODE (SET_SRC (pat)) == SUBREG
6460 && REGNO (SUBREG_REG (SET_DEST (slot_pat))) ==
6461 REGNO (SUBREG_REG (SET_SRC (pat)))
6462 && SUBREG_WORD (SET_DEST (slot_pat)) ==
ddf80874 6463 SUBREG_WORD (SET_SRC (pat)))))
3bc8b61e
DM		 6464 || (check_fpmode_conflict == 1
6465 && GET_CODE (slot_insn) == INSN
6466 && GET_CODE (slot_pat) == SET
ddf80874
DM		 6467 && (GET_MODE (SET_DEST (slot_pat)) == SFmode
6468 || GET_MODE (SET_DEST (slot_pat)) == DFmode)
6469 && GET_MODE (SET_DEST (slot_pat)) != fpmode)))
3bc8b61e
DM		 6470 goto next;
6471 }
6472
6473 /* Check for peculiar result availability and dispatch
6474 interference situations. */
6475 if (pat != 0
6476 && ultra_cycles_elapsed > 0)
6477 {
6478 rtx link;
6479
6480 for (link = LOG_LINKS (insn); link; link = XEXP (link, 1))
6481 {
6482 rtx link_insn = XEXP (link, 0);
6483 if (GET_CODE (link_insn) == INSN
6484 && recog_memoized (link_insn) >= 0
6485 && (TMASK (get_attr_type (link_insn)) &
6486 (TMASK (TYPE_CMOVE) | TMASK (TYPE_FPCMOVE)))
6487 && ! ultra_cmove_results_ready_p (link_insn))
6488 goto next;
6489 }
6490
6491 if (check_fpmode_conflict
6492 && ultra_fpmode_conflict_exists (fpmode))
6493 goto next;
6494 }
6495
6496 return &list[i];
6497 }
6498 next:
5a5325cb 6499 ;
3bc8b61e
DM		 6500 }
6501 return 0;
6502}
6503
5a5325cb
DM		 6504static void
6505ultra_build_types_avail (ready, n_ready)
6506 rtx *ready;
6507 int n_ready;
6508{
6509 int i = n_ready - 1;
6510
6511 ultra_types_avail = 0;
6512 while(i >= 0)
6513 {
6514 rtx insn = ready[i];
6515
6516 if (recog_memoized (insn) >= 0)
6517 ultra_types_avail |= TMASK (get_attr_type (insn));
6518
6519 i -= 1;
6520 }
6521}
6522
3bc8b61e
DM		 6523/* Place insn pointed to my IP into the pipeline.
6524 Make element THIS of READY be that insn if it
6525 is not already. TYPE indicates the pipeline class
6526 this insn falls into. */
6527static void
6528ultra_schedule_insn (ip, ready, this, type)
6529 rtx *ip;
6530 rtx *ready;
6531 int this;
6532 enum ultra_code type;
6533{
6534 int pipe_slot;
6535 char mask = ultra_pipe.free_slot_mask;
6536
6537 /* Obtain free slot. */
6538 for (pipe_slot = 0; pipe_slot < 4; pipe_slot++)
6539 if ((mask & (1 << pipe_slot)) != 0)
6540 break;
6541 if (pipe_slot == 4)
6542 abort ();
6543
6544 /* In it goes, and it hasn't been committed yet. */
6545 ultra_pipe.group[pipe_slot] = *ip;
6546 ultra_pipe.codes[pipe_slot] = type;
6547 ultra_pipe.contents[type] = 1;
6548 if (UMASK (type) &
6549 (UMASK (IEUN) | UMASK (IEU0) | UMASK (IEU1)))
6550 ultra_pipe.num_ieu_insns += 1;
6551
6552 ultra_pipe.free_slot_mask = (mask & ~(1 << pipe_slot));
6553 ultra_pipe.group_size += 1;
6554 ultra_pipe.commit[pipe_slot] = 0;
6555
6556 /* Update ready list. */
6557 if (ip != &ready[this])
6558 {
6559 rtx temp = *ip;
6560
6561 *ip = ready[this];
6562 ready[this] = temp;
6563 }
6564}
6565
6566/* Advance to the next pipeline group. */
6567static void
6568ultra_flush_pipeline ()
6569{
ddf80874 6570 ultra_cur_hist = (ultra_cur_hist + 1) % (ULTRA_NUM_HIST - 1);
3bc8b61e
DM		 6571 ultra_cycles_elapsed += 1;
6572 bzero ((char *) &ultra_pipe, sizeof ultra_pipe);
6573 ultra_pipe.free_slot_mask = 0xf;
6574}
6575
6576static int ultra_reorder_called_this_block;
6577
6578/* Init our data structures for this current block. */
6579void
6580ultrasparc_sched_init (dump, sched_verbose)
ddf80874
DM		 6581 FILE *dump ATTRIBUTE_UNUSED;
6582 int sched_verbose ATTRIBUTE_UNUSED;
3bc8b61e 6583{
b96a5ea5 6584 bzero ((char *) ultra_pipe_hist, sizeof ultra_pipe_hist);
3bc8b61e
DM		 6585 ultra_cur_hist = 0;
6586 ultra_cycles_elapsed = 0;
6587 ultra_reorder_called_this_block = 0;
ddf80874 6588 ultra_pipe.free_slot_mask = 0xf;
3bc8b61e
DM		 6589}
6590
6591/* INSN has been scheduled, update pipeline commit state
6592 and return how many instructions are still to be
6593 scheduled in this group. */
bfd6bc60 6594int
3bc8b61e
DM		 6595ultrasparc_variable_issue (insn)
6596 rtx insn;
6597{
6598 struct ultrasparc_pipeline_state *up = &ultra_pipe;
6599 int i, left_to_fire;
6600
6601 left_to_fire = 0;
6602 for (i = 0; i < 4; i++)
6603 {
6604 if (up->group[i] == 0)
6605 continue;
6606
6607 if (up->group[i] == insn)
6608 {
6609 up->commit[i] = 1;
6610 }
6611 else if (! up->commit[i])
6612 left_to_fire++;
6613 }
6614
6615 return left_to_fire;
6616}
6617
6618/* In actual_hazard_this_instance, we may have yanked some
6619 instructions from the ready list due to conflict cost
6620 adjustments. If so, and such an insn was in our pipeline
6621 group, remove it and update state. */
6622static void
6623ultra_rescan_pipeline_state (ready, n_ready)
6624 rtx *ready;
6625 int n_ready;
6626{
6627 struct ultrasparc_pipeline_state *up = &ultra_pipe;
6628 int i;
6629
6630 for (i = 0; i < 4; i++)
6631 {
6632 rtx insn = up->group[i];
3bc8b61e
DM		 6633 int j;
6634
6635 if (! insn)
6636 continue;
6637
6638 /* If it has been committed, then it was removed from
6639 the ready list because it was actually scheduled,
6640 and that is not the case we are searching for here. */
6641 if (up->commit[i] != 0)
6642 continue;
6643
6644 for (j = n_ready - 1; j >= 0; j--)
6645 if (ready[j] == insn)
6646 break;
6647
6648 /* If we didn't find it, toss it. */
6649 if (j < 0)
6650 {
6651 enum ultra_code ucode = up->codes[i];
6652
6653 up->group[i] = 0;
6654 up->codes[i] = NONE;
6655 up->contents[ucode] = 0;
6656 if (UMASK (ucode) &
6657 (UMASK (IEUN) | UMASK (IEU0) | UMASK (IEU1)))
6658 up->num_ieu_insns -= 1;
6659
6660 up->free_slot_mask |= (1 << i);
6661 up->group_size -= 1;
6662 up->commit[i] = 0;
6663 }
6664 }
6665}
6666
6667void
6668ultrasparc_sched_reorder (dump, sched_verbose, ready, n_ready)
6669 FILE *dump;
6670 int sched_verbose;
6671 rtx *ready;
6672 int n_ready;
6673{
6674 struct ultrasparc_pipeline_state *up = &ultra_pipe;
6675 int i, this_insn;
6676
6677 /* We get called once unnecessarily per block of insns
6678 scheduled. */
6679 if (ultra_reorder_called_this_block == 0)
6680 {
6681 ultra_reorder_called_this_block = 1;
6682 return;
6683 }
6684
6685 if (sched_verbose)
6686 {
6687 int n;
6688
6689 fprintf (dump, "\n;;\tUltraSPARC Looking at [");
6690 for (n = n_ready - 1; n >= 0; n--)
6691 {
6692 rtx insn = ready[n];
6693 enum ultra_code ucode;
6694
6695 if (recog_memoized (insn) < 0)
6696 continue;
6697 ucode = ultra_code_from_mask (TMASK (get_attr_type (insn)));
6698 if (n != 0)
6699 fprintf (dump, "%s(%d) ",
6700 ultra_code_names[ucode],
6701 INSN_UID (insn));
6702 else
6703 fprintf (dump, "%s(%d)",
6704 ultra_code_names[ucode],
6705 INSN_UID (insn));
6706 }
6707 fprintf (dump, "]\n");
6708 }
6709
6710 this_insn = n_ready - 1;
6711
6712 /* Skip over junk we don't understand. */
6713 while ((this_insn >= 0)
6714 && recog_memoized (ready[this_insn]) < 0)
6715 this_insn--;
6716
5a5325cb
DM		 6717 ultra_build_types_avail (ready, this_insn + 1);
6718
3bc8b61e
DM		 6719 while (this_insn >= 0) {
6720 int old_group_size = up->group_size;
6721
6722 if (up->group_size != 0)
6723 {
6724 int num_committed;
6725
6726 num_committed = (up->commit[0] + up->commit[1] +
6727 up->commit[2] + up->commit[3]);
6728 /* If nothing has been commited from our group, or all of
6729 them have. Clear out the (current cycle's) pipeline
6730 state and start afresh. */
6731 if (num_committed == 0
6732 || num_committed == up->group_size)
6733 {
ddf80874
DM		 6734 ultra_flush_pipeline ();
6735 up = &ultra_pipe;
3bc8b61e
DM		 6736 old_group_size = 0;
6737 }
6738 else
6739 {
6740 /* OK, some ready list insns got requeued and thus removed
6741 from the ready list. Account for this fact. */
6742 ultra_rescan_pipeline_state (ready, n_ready);
6743
6744 /* Something "changed", make this look like a newly
6745 formed group so the code at the end of the loop
6746 knows that progress was in fact made. */
6747 if (up->group_size != old_group_size)
ddf80874 6748 old_group_size = 0;
3bc8b61e
DM		 6749 }
6750 }
6751
6752 if (up->group_size == 0)
6753 {
6754 /* If the pipeline is (still) empty and we have any single
6755 group insns, get them out now as this is a good time. */
6756 rtx *ip = ultra_find_type ((TMASK (TYPE_RETURN) | TMASK (TYPE_ADDRESS) |
6757 TMASK (TYPE_IMUL) | TMASK (TYPE_CMOVE) |
6758 TMASK (TYPE_MULTI) | TMASK (TYPE_MISC)),
6759 ready, this_insn);
6760 if (ip)
6761 {
6762 ultra_schedule_insn (ip, ready, this_insn, SINGLE);
6763 break;
6764 }
6765
6766 /* If we are not in the process of emptying out the pipe, try to
6767 obtain an instruction which must be the first in it's group. */
6768 ip = ultra_find_type ((TMASK (TYPE_CALL) |
6769 TMASK (TYPE_CALL_NO_DELAY_SLOT) |
6770 TMASK (TYPE_UNCOND_BRANCH)),
6771 ready, this_insn);
6772 if (ip)
6773 {
6774 ultra_schedule_insn (ip, ready, this_insn, IEU1);
6775 this_insn--;
6776 }
6777 else if ((ip = ultra_find_type ((TMASK (TYPE_FPDIVS) |
6778 TMASK (TYPE_FPDIVD) |
6779 TMASK (TYPE_FPSQRT)),
6780 ready, this_insn)) != 0)
6781 {
6782 ultra_schedule_insn (ip, ready, this_insn, FPM);
6783 this_insn--;
6784 }
6785 }
6786
6787 /* Try to fill the integer pipeline. First, look for an IEU0 specific
6788 operation. We can't do more IEU operations if the first 3 slots are
6789 all full or we have dispatched two IEU insns already. */
6790 if ((up->free_slot_mask & 0x7) != 0
6791 && up->num_ieu_insns < 2
6792 && up->contents[IEU0] == 0
6793 && up->contents[IEUN] == 0)
6794 {
6795 rtx *ip = ultra_find_type (TMASK(TYPE_SHIFT), ready, this_insn);
6796 if (ip)
6797 {
6798 ultra_schedule_insn (ip, ready, this_insn, IEU0);
6799 this_insn--;
6800 }
6801 }
6802
6803 /* If we can, try to find an IEU1 specific or an unnamed
6804 IEU instruction. */
6805 if ((up->free_slot_mask & 0x7) != 0
6806 && up->num_ieu_insns < 2)
6807 {
6808 rtx *ip = ultra_find_type ((TMASK (TYPE_IALU) | TMASK (TYPE_BINARY) |
6809 TMASK (TYPE_MOVE) | TMASK (TYPE_UNARY) |
6810 (up->contents[IEU1] == 0 ? TMASK (TYPE_COMPARE) : 0)),
6811 ready, this_insn);
6812 if (ip)
6813 {
6814 rtx insn = *ip;
6815
6816 ultra_schedule_insn (ip, ready, this_insn,
6817 (!up->contents[IEU1]
6818 && get_attr_type (insn) == TYPE_COMPARE)
6819 ? IEU1 : IEUN);
6820 this_insn--;
6821 }
6822 }
6823
6824 /* If only one IEU insn has been found, try to find another unnamed
6825 IEU operation or an IEU1 specific one. */
6826 if ((up->free_slot_mask & 0x7) != 0
6827 && up->num_ieu_insns < 2)
6828 {
6829 rtx *ip;
6830 int tmask = (TMASK (TYPE_IALU) | TMASK (TYPE_BINARY) |
6831 TMASK (TYPE_MOVE) | TMASK (TYPE_UNARY));
6832
6833 if (!up->contents[IEU1])
6834 tmask |= TMASK (TYPE_COMPARE);
6835 ip = ultra_find_type (tmask, ready, this_insn);
6836 if (ip)
6837 {
6838 rtx insn = *ip;
6839
6840 ultra_schedule_insn (ip, ready, this_insn,
6841 (!up->contents[IEU1]
6842 && get_attr_type (insn) == TYPE_COMPARE)
6843 ? IEU1 : IEUN);
6844 this_insn--;
6845 }
6846 }
6847
6848 /* Try for a load or store, but such an insn can only be issued
6849 if it is within' one of the first 3 slots. */
6850 if ((up->free_slot_mask & 0x7) != 0
6851 && up->contents[LSU] == 0)
6852 {
6853 rtx *ip = ultra_find_type ((TMASK (TYPE_LOAD) | TMASK (TYPE_SLOAD) |
6854 TMASK (TYPE_STORE) | TMASK (TYPE_FPLOAD) |
6855 TMASK (TYPE_FPSTORE)), ready, this_insn);
6856 if (ip)
6857 {
6858 ultra_schedule_insn (ip, ready, this_insn, LSU);
6859 this_insn--;
6860 }
6861 }
6862
6863 /* Now find FPU operations, first FPM class. But not divisions or
6864 square-roots because those will break the group up. Unlike all
6865 the previous types, these can go in any slot. */
6866 if (up->free_slot_mask != 0
6867 && up->contents[FPM] == 0)
6868 {
6869 rtx *ip = ultra_find_type (TMASK (TYPE_FPMUL), ready, this_insn);
6870 if (ip)
6871 {
6872 ultra_schedule_insn (ip, ready, this_insn, FPM);
6873 this_insn--;
6874 }
6875 }
6876
6877 /* Continue on with FPA class if we have not filled the group already. */
6878 if (up->free_slot_mask != 0
6879 && up->contents[FPA] == 0)
6880 {
6881 rtx *ip = ultra_find_type ((TMASK (TYPE_FPMOVE) | TMASK (TYPE_FPCMOVE) |
6882 TMASK (TYPE_FP) | TMASK (TYPE_FPCMP)),
6883 ready, this_insn);
6884 if (ip)
6885 {
6886 ultra_schedule_insn (ip, ready, this_insn, FPA);
6887 this_insn--;
6888 }
6889 }
6890
6891 /* Finally, maybe stick a branch in here. */
6892 if (up->free_slot_mask != 0
6893 && up->contents[CTI] == 0)
6894 {
6895 rtx *ip = ultra_find_type (TMASK (TYPE_BRANCH), ready, this_insn);
6896
6897 /* Try to slip in a branch only if it is one of the
6898 next 2 in the ready list. */
6899 if (ip && ((&ready[this_insn] - ip) < 2))
6900 {
6901 ultra_schedule_insn (ip, ready, this_insn, CTI);
6902 this_insn--;
6903 }
6904 }
6905
6906 up->group_size = 0;
6907 for (i = 0; i < 4; i++)
6908 if ((up->free_slot_mask & (1 << i)) == 0)
6909 up->group_size++;
6910
6911 /* See if we made any progress... */
6912 if (old_group_size != up->group_size)
6913 break;
6914
6915 /* Clean out the (current cycle's) pipeline state
ddf80874
DM		 6916 and try once more. If we placed no instructions
6917 into the pipeline at all, it means a real hard
6918 conflict exists with some earlier issued instruction
6919 so we must advance to the next cycle to clear it up. */
6920 if (up->group_size == 0)
6921 {
6922 ultra_flush_pipeline ();
6923 up = &ultra_pipe;
6924 }
6925 else
6926 {
6927 bzero ((char *) &ultra_pipe, sizeof ultra_pipe);
6928 ultra_pipe.free_slot_mask = 0xf;
6929 }
3bc8b61e
DM		 6930 }
6931
6932 if (sched_verbose)
6933 {
6934 int n, gsize;
6935
6936 fprintf (dump, ";;\tUltraSPARC Launched [");
6937 gsize = up->group_size;
6938 for (n = 0; n < 4; n++)
6939 {
6940 rtx insn = up->group[n];
6941
6942 if (! insn)
6943 continue;
6944
6945 gsize -= 1;
6946 if (gsize != 0)
6947 fprintf (dump, "%s(%d) ",
6948 ultra_code_names[up->codes[n]],
6949 INSN_UID (insn));
6950 else
6951 fprintf (dump, "%s(%d)",
6952 ultra_code_names[up->codes[n]],
6953 INSN_UID (insn));
6954 }
6955 fprintf (dump, "]\n");
6956 }
6957}
6958
6959int
ddf80874 6960ultrasparc_adjust_cost (insn, link, dep_insn, cost)
3bc8b61e
DM		 6961 rtx insn;
6962 rtx link;
6963 rtx dep_insn;
3bc8b61e 6964 int cost;
bfd6bc60
JC		 6965{
6966 enum attr_type insn_type, dep_type;
3bc8b61e
DM		 6967 rtx pat = PATTERN(insn);
6968 rtx dep_pat = PATTERN (dep_insn);
bfd6bc60 6969
3bc8b61e
DM		 6970 if (recog_memoized (insn) < 0 || recog_memoized (dep_insn) < 0)
6971 return cost;
bfd6bc60 6972
3bc8b61e
DM		 6973 insn_type = get_attr_type (insn);
6974 dep_type = get_attr_type (dep_insn);
6975
6976 /* Nothing issues in parallel with integer multiplies, so
6977 mark as zero cost since the scheduler can not do anything
6978 about it. */
6979 if (insn_type == TYPE_IMUL)
6980 return 0;
bfd6bc60
JC		 6981
6982#define SLOW_FP(dep_type) \
284d86e9
JC		 6983(dep_type == TYPE_FPSQRT || dep_type == TYPE_FPDIVS || dep_type == TYPE_FPDIVD)
6984
bfd6bc60 6985 switch (REG_NOTE_KIND (link))
3bc8b61e
DM		 6986 {
6987 case 0:
bfd6bc60 6988 /* Data dependency; DEP_INSN writes a register that INSN reads some
3bc8b61e
DM		 6989 cycles later. */
6990
6991 if (dep_type == TYPE_CMOVE)
6992 {
6993 /* Instructions that read the result of conditional moves cannot
6994 be in the same group or the following group. */
6995 return cost + 1;
6996 }
bfd6bc60
JC		 6997
6998 switch (insn_type)
3bc8b61e
DM		 6999 {
7000 /* UltraSPARC can dual issue a store and an instruction setting
7001 the value stored, except for divide and square root. */
bfd6bc60 7002 case TYPE_FPSTORE:
3bc8b61e
DM		 7003 if (! SLOW_FP (dep_type))
7004 return 0;
284d86e9 7005 return cost;
bfd6bc60 7006
3bc8b61e 7007 case TYPE_STORE:
bfd6bc60 7008 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
3bc8b61e 7009 return cost;
bfd6bc60 7010
284d86e9 7011 if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat)))
3bc8b61e
DM		 7012 /* The dependency between the two instructions is on the data
7013 that is being stored. Assume that the address of the store
7014 is not also dependent. */
7015 return 0;
7016 return cost;
7017
7018 case TYPE_LOAD:
7019 case TYPE_SLOAD:
7020 case TYPE_FPLOAD:
7021 /* A load does not return data until at least 11 cycles after
bfd6bc60
JC		 7022 a store to the same location. 3 cycles are accounted for
7023 in the load latency; add the other 8 here. */
7024 if (dep_type == TYPE_STORE || dep_type == TYPE_FPSTORE)
3bc8b61e 7025 {
bfd6bc60
JC		 7026 /* If the addresses are not equal this may be a false
7027 dependency because pointer aliasing could not be
7028 determined. Add only 2 cycles in that case. 2 is
7029 an arbitrary compromise between 8, which would cause
7030 the scheduler to generate worse code elsewhere to
3bc8b61e
DM		 7031 compensate for a dependency which might not really
7032 exist, and 0. */
bfd6bc60 7033 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET
284d86e9
JC		 7034 || GET_CODE (SET_SRC (pat)) != MEM
7035 || GET_CODE (SET_DEST (dep_pat)) != MEM
7036 || ! rtx_equal_p (XEXP (SET_SRC (pat), 0),
7037 XEXP (SET_DEST (dep_pat), 0)))
bfd6bc60
JC		 7038 return cost + 2;
7039
3bc8b61e
DM		 7040 return cost + 8;
7041 }
284d86e9 7042 return cost;
bfd6bc60 7043
3bc8b61e 7044 case TYPE_BRANCH:
bfd6bc60
JC		 7045 /* Compare to branch latency is 0. There is no benefit from
7046 separating compare and branch. */
3bc8b61e
DM		 7047 if (dep_type == TYPE_COMPARE)
7048 return 0;
7049 /* Floating point compare to branch latency is less than
7050 compare to conditional move. */
7051 if (dep_type == TYPE_FPCMP)
7052 return cost - 1;
284d86e9 7053 return cost;
bfd6bc60 7054
3bc8b61e 7055 case TYPE_FPCMOVE:
bfd6bc60
JC		 7056 /* FMOVR class instructions can not issue in the same cycle
7057 or the cycle after an instruction which writes any
7058 integer register. Model this as cost 2 for dependent
3bc8b61e 7059 instructions. */
284d86e9
JC		 7060 if ((dep_type == TYPE_IALU || dep_type == TYPE_UNARY
7061 || dep_type == TYPE_BINARY)
3bc8b61e 7062 && cost < 2)
bfd6bc60
JC		 7063 return 2;
7064 /* Otherwise check as for integer conditional moves. */
7065
3bc8b61e 7066 case TYPE_CMOVE:
bfd6bc60
JC		 7067 /* Conditional moves involving integer registers wait until
7068 3 cycles after loads return data. The interlock applies
7069 to all loads, not just dependent loads, but that is hard
3bc8b61e
DM		 7070 to model. */
7071 if (dep_type == TYPE_LOAD || dep_type == TYPE_SLOAD)
7072 return cost + 3;
284d86e9 7073 return cost;
27d8f9ea
KG		 7074
7075 default:
7076 break;
bfd6bc60 7077 }
3bc8b61e 7078 break;
bfd6bc60 7079
3bc8b61e 7080 case REG_DEP_ANTI:
bfd6bc60 7081 /* Divide and square root lock destination registers for full latency. */
3bc8b61e
DM		 7082 if (! SLOW_FP (dep_type))
7083 return 0;
7084 break;
7085
7086 case REG_DEP_OUTPUT:
7087 /* IEU and FPU instruction that have the same destination
7088 register cannot be grouped together. */
7089 return cost + 1;
27d8f9ea
KG		 7090
7091 default:
7092 break;
bfd6bc60
JC		 7093 }
7094
3bc8b61e
DM		 7095 /* Other costs not accounted for:
7096 - Single precision floating point loads lock the other half of
7097 the even/odd register pair.
bfd6bc60 7098 - Several hazards associated with ldd/std are ignored because these
3bc8b61e 7099 instructions are rarely generated for V9.
bfd6bc60
JC		 7100 - The floating point pipeline can not have both a single and double
7101 precision operation active at the same time. Format conversions
7102 and graphics instructions are given honorary double precision status.
7103 - call and jmpl are always the first instruction in a group. */
7104
3bc8b61e
DM		 7105 return cost;
7106}
bfd6bc60
JC		 7107
7108int
7109sparc_issue_rate ()
7110{
7111 switch (sparc_cpu)
7112 {
7113 default:
7114 return 1;
bfd6bc60 7115 case PROCESSOR_V9:
284d86e9 7116 /* Assume V9 processors are capable of at least dual-issue. */
bfd6bc60
JC		 7117 return 2;
7118 case PROCESSOR_SUPERSPARC:
7119 return 3;
7120 case PROCESSOR_ULTRASPARC:
7121 return 4;
7122 }
7123}
284d86e9
JC		 7124
7125static int
7126set_extends(x, insn)
7127 rtx x, insn;
7128{
7129 register rtx pat = PATTERN (insn);
7130
7131 switch (GET_CODE (SET_SRC (pat)))
7132 {
7133 /* Load and some shift instructions zero extend. */
7134 case MEM:
7135 case ZERO_EXTEND:
7136 /* sethi clears the high bits */
7137 case HIGH:
7138 /* LO_SUM is used with sethi. sethi cleared the high
7139 bits and the values used with lo_sum are positive */
7140 case LO_SUM:
284d86e9
JC		 7141 /* Store flag stores 0 or 1 */
7142 case LT: case LTU:
7143 case GT: case GTU:
7144 case LE: case LEU:
7145 case GE: case GEU:
7146 case EQ:
7147 case NE:
7148 return 1;
7149 case AND:
7150 {
7151 rtx op1 = XEXP (SET_SRC (pat), 1);
7152 if (GET_CODE (op1) == CONST_INT)
7153 return INTVAL (op1) >= 0;
7154 if (GET_CODE (XEXP (SET_SRC (pat), 0)) == REG
7155 && sparc_check_64 (XEXP (SET_SRC (pat), 0), insn) == 1)
7156 return 1;
7157 if (GET_CODE (op1) == REG
7158 && sparc_check_64 ((op1), insn) == 1)
7159 return 1;
7160 }
7161 case ASHIFT:
7162 case LSHIFTRT:
7163 return GET_MODE (SET_SRC (pat)) == SImode;
7164 /* Positive integers leave the high bits zero. */
7165 case CONST_DOUBLE:
7166 return ! (CONST_DOUBLE_LOW (x) & 0x80000000);
7167 case CONST_INT:
7168 return ! (INTVAL (x) & 0x80000000);
7169 case ASHIFTRT:
7170 case SIGN_EXTEND:
7171 return - (GET_MODE (SET_SRC (pat)) == SImode);
7172 default:
7173 return 0;
7174 }
7175}
7176
e0d80184
DM		 7177/* We _ought_ to have only one kind per function, but... */
7178static rtx sparc_addr_diff_list;
7179static rtx sparc_addr_list;
7180
7181void
7182sparc_defer_case_vector (lab, vec, diff)
7183 rtx lab, vec;
7184 int diff;
7185{
7186 vec = gen_rtx_EXPR_LIST (VOIDmode, lab, vec);
7187 if (diff)
7188 sparc_addr_diff_list
7189 = gen_rtx_EXPR_LIST (VOIDmode, vec, sparc_addr_diff_list);
7190 else
7191 sparc_addr_list = gen_rtx_EXPR_LIST (VOIDmode, vec, sparc_addr_list);
7192}
7193
7194static void
7195sparc_output_addr_vec (vec)
7196 rtx vec;
7197{
7198 rtx lab = XEXP (vec, 0), body = XEXP (vec, 1);
7199 int idx, vlen = XVECLEN (body, 0);
7200
7201#ifdef ASM_OUTPUT_CASE_LABEL
7202 ASM_OUTPUT_CASE_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab),
7203 NEXT_INSN (lab));
7204#else
7205 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab));
7206#endif
7207
7208 for (idx = 0; idx < vlen; idx++)
7209 {
7210 ASM_OUTPUT_ADDR_VEC_ELT
7211 (asm_out_file, CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 0, idx), 0)));
7212 }
7213}
7214
7215static void
7216sparc_output_addr_diff_vec (vec)
7217 rtx vec;
7218{
7219 rtx lab = XEXP (vec, 0), body = XEXP (vec, 1);
7220 rtx base = XEXP (XEXP (body, 0), 0);
7221 int idx, vlen = XVECLEN (body, 1);
7222
7223#ifdef ASM_OUTPUT_CASE_LABEL
7224 ASM_OUTPUT_CASE_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab),
7225 NEXT_INSN (lab));
7226#else
7227 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab));
7228#endif
7229
7230 for (idx = 0; idx < vlen; idx++)
7231 {
7232 ASM_OUTPUT_ADDR_DIFF_ELT
7233 (asm_out_file,
7234 body,
7235 CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 1, idx), 0)),
7236 CODE_LABEL_NUMBER (base));
7237 }
7238}
7239
7240static void
7241sparc_output_deferred_case_vectors ()
7242{
7243 rtx t;
d676da68 7244 int align;
e0d80184
DM		 7245
7246 /* Align to cache line in the function's code section. */
7247 function_section (current_function_decl);
d676da68
DM		 7248
7249 align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT);
7250 if (align > 0)
7251 ASM_OUTPUT_ALIGN (asm_out_file, 5);
e0d80184
DM		 7252
7253 for (t = sparc_addr_list; t ; t = XEXP (t, 1))
7254 sparc_output_addr_vec (XEXP (t, 0));
7255 for (t = sparc_addr_diff_list; t ; t = XEXP (t, 1))
7256 sparc_output_addr_diff_vec (XEXP (t, 0));
7257
7258 sparc_addr_list = sparc_addr_diff_list = NULL_RTX;
7259}
7260
284d86e9
JC		 7261/* Return 0 if the high 32 bits of X (the low word of X, if DImode) are
7262 unknown. Return 1 if the high bits are zero, -1 if the register is
7263 sign extended. */
7264int
7265sparc_check_64 (x, insn)
7266 rtx x, insn;
7267{
7268 /* If a register is set only once it is safe to ignore insns this
7269 code does not know how to handle. The loop will either recognize
7270 the single set and return the correct value or fail to recognize
7271 it and return 0. */
7272 int set_once = 0;
7273
7274 if (GET_CODE (x) == REG
7275 && flag_expensive_optimizations
7276 && REG_N_SETS (REGNO (x)) == 1)
7277 set_once = 1;
7278
7279 if (insn == 0)
d6f4ec51
KG		 7280 {
7281 if (set_once)
7282 insn = get_last_insn_anywhere ();
7283 else
7284 return 0;
7285 }
284d86e9 7286
d6f4ec51 7287 while ((insn = PREV_INSN (insn)))
284d86e9
JC		 7288 {
7289 switch (GET_CODE (insn))
7290 {
7291 case JUMP_INSN:
7292 case NOTE:
7293 break;
7294 case CODE_LABEL:
7295 case CALL_INSN:
7296 default:
7297 if (! set_once)
7298 return 0;
7299 break;
7300 case INSN:
7301 {
7302 rtx pat = PATTERN (insn);
7303 if (GET_CODE (pat) != SET)
7304 return 0;
7305 if (rtx_equal_p (x, SET_DEST (pat)))
7306 return set_extends (x, insn);
7307 if (reg_overlap_mentioned_p (SET_DEST (pat), x))
7308 return 0;
7309 }
7310 }
7311 }
7312 return 0;
7313}
7314
7315char *
7316sparc_v8plus_shift (operands, insn, opcode)
7317 rtx *operands;
7318 rtx insn;
7319 char *opcode;
7320{
7321 static char asm_code[60];
7322
7323 if (GET_CODE (operands[3]) == SCRATCH)
7324 operands[3] = operands[0];
c6b0465b
JC		 7325 if (GET_CODE (operands[1]) == CONST_INT)
7326 {
7327 output_asm_insn ("mov %1,%3", operands);
7328 }
7329 else
7330 {
7331 output_asm_insn ("sllx %H1,32,%3", operands);
7332 if (sparc_check_64 (operands[1], insn) <= 0)
7333 output_asm_insn ("srl %L1,0,%L1", operands);
7334 output_asm_insn ("or %L1,%3,%3", operands);
7335 }
284d86e9
JC		 7336
7337 strcpy(asm_code, opcode);
7338 if (which_alternative != 2)
7339 return strcat (asm_code, " %0,%2,%L0\n\tsrlx %L0,32,%H0");
7340 else
7341 return strcat (asm_code, " %3,%2,%3\n\tsrlx %3,32,%H0\n\tmov %3,%L0");
7342}
7343
7344
7345/* Return 1 if DEST and SRC reference only global and in registers. */
7346
7347int
7348sparc_return_peephole_ok (dest, src)
7349 rtx dest, src;
7350{
7351 if (! TARGET_V9)
7352 return 0;
7353 if (leaf_function)
7354 return 0;
7355 if (GET_CODE (src) != CONST_INT
7356 && (GET_CODE (src) != REG || ! IN_OR_GLOBAL_P (src)))
7357 return 0;
7358 return IN_OR_GLOBAL_P (dest);
7359}
GNU Compiler Collection
This page took 1.425582 seconds and 5 git commands to generate.