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ab835497 | 1 | /* Subroutines for insn-output.c for Sun SPARC. |
4592bdcb | 2 | Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998, |
ae46c4e0 | 3 | 1999, 2000, 2001, 2002 Free Software Foundation, Inc. |
ab835497 | 4 | Contributed by Michael Tiemann (tiemann@cygnus.com) |
61a55e8b DE |
5 | 64 bit SPARC V9 support by Michael Tiemann, Jim Wilson, and Doug Evans, |
6 | at Cygnus Support. | |
ab835497 RK |
7 | |
8 | This file is part of GNU CC. | |
9 | ||
10 | GNU CC is free software; you can redistribute it and/or modify | |
11 | it under the terms of the GNU General Public License as published by | |
12 | the Free Software Foundation; either version 2, or (at your option) | |
13 | any later version. | |
14 | ||
15 | GNU CC is distributed in the hope that it will be useful, | |
16 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | GNU General Public License for more details. | |
19 | ||
20 | You should have received a copy of the GNU General Public License | |
21 | along with GNU CC; see the file COPYING. If not, write to | |
c15c9075 RK |
22 | the Free Software Foundation, 59 Temple Place - Suite 330, |
23 | Boston, MA 02111-1307, USA. */ | |
ab835497 | 24 | |
ab835497 | 25 | #include "config.h" |
284d86e9 | 26 | #include "system.h" |
4977bab6 ZW |
27 | #include "coretypes.h" |
28 | #include "tm.h" | |
210aa14a | 29 | #include "tree.h" |
ab835497 RK |
30 | #include "rtl.h" |
31 | #include "regs.h" | |
32 | #include "hard-reg-set.h" | |
33 | #include "real.h" | |
34 | #include "insn-config.h" | |
35 | #include "conditions.h" | |
ab835497 RK |
36 | #include "output.h" |
37 | #include "insn-attr.h" | |
38 | #include "flags.h" | |
49ad7cfa | 39 | #include "function.h" |
ab835497 | 40 | #include "expr.h" |
e78d8e51 ZW |
41 | #include "optabs.h" |
42 | #include "libfuncs.h" | |
ab835497 | 43 | #include "recog.h" |
487a6e06 | 44 | #include "toplev.h" |
d07d525a | 45 | #include "ggc.h" |
b1474bb7 | 46 | #include "tm_p.h" |
e78d8e51 | 47 | #include "debug.h" |
672a6f42 NB |
48 | #include "target.h" |
49 | #include "target-def.h" | |
117dca74 | 50 | #include "cfglayout.h" |
ab835497 | 51 | |
61a55e8b DE |
52 | /* 1 if the caller has placed an "unimp" insn immediately after the call. |
53 | This is used in v8 code when calling a function that returns a structure. | |
06b967f9 RK |
54 | v9 doesn't have this. Be careful to have this test be the same as that |
55 | used on the call. */ | |
56 | ||
57 | #define SKIP_CALLERS_UNIMP_P \ | |
58 | (!TARGET_ARCH64 && current_function_returns_struct \ | |
59 | && ! integer_zerop (DECL_SIZE (DECL_RESULT (current_function_decl))) \ | |
60 | && (TREE_CODE (DECL_SIZE (DECL_RESULT (current_function_decl))) \ | |
61 | == INTEGER_CST)) | |
61a55e8b | 62 | |
ab835497 RK |
63 | /* Global variables for machine-dependent things. */ |
64 | ||
61a55e8b DE |
65 | /* Size of frame. Need to know this to emit return insns from leaf procedures. |
66 | ACTUAL_FSIZE is set by compute_frame_size() which is called during the | |
67 | reload pass. This is important as the value is later used in insn | |
68 | scheduling (to see what can go in a delay slot). | |
69 | APPARENT_FSIZE is the size of the stack less the register save area and less | |
70 | the outgoing argument area. It is used when saving call preserved regs. */ | |
71 | static int apparent_fsize; | |
72 | static int actual_fsize; | |
73 | ||
33074e5f RH |
74 | /* Number of live general or floating point registers needed to be |
75 | saved (as 4-byte quantities). */ | |
e48addee JJ |
76 | static int num_gfregs; |
77 | ||
ab835497 RK |
78 | /* Save the operands last given to a compare for use when we |
79 | generate a scc or bcc insn. */ | |
ab835497 RK |
80 | rtx sparc_compare_op0, sparc_compare_op1; |
81 | ||
33074e5f RH |
82 | /* Coordinate with the md file wrt special insns created by |
83 | sparc_nonflat_function_epilogue. */ | |
84 | bool sparc_emitting_epilogue; | |
ab835497 | 85 | |
563c12b0 RH |
86 | /* Vector to say how input registers are mapped to output registers. |
87 | HARD_FRAME_POINTER_REGNUM cannot be remapped by this function to | |
88 | eliminate it. You must use -fomit-frame-pointer to get that. */ | |
d70e94ec | 89 | char leaf_reg_remap[] = |
ab835497 RK |
90 | { 0, 1, 2, 3, 4, 5, 6, 7, |
91 | -1, -1, -1, -1, -1, -1, 14, -1, | |
92 | -1, -1, -1, -1, -1, -1, -1, -1, | |
93 | 8, 9, 10, 11, 12, 13, -1, 15, | |
94 | ||
95 | 32, 33, 34, 35, 36, 37, 38, 39, | |
96 | 40, 41, 42, 43, 44, 45, 46, 47, | |
97 | 48, 49, 50, 51, 52, 53, 54, 55, | |
61a55e8b DE |
98 | 56, 57, 58, 59, 60, 61, 62, 63, |
99 | 64, 65, 66, 67, 68, 69, 70, 71, | |
100 | 72, 73, 74, 75, 76, 77, 78, 79, | |
101 | 80, 81, 82, 83, 84, 85, 86, 87, | |
102 | 88, 89, 90, 91, 92, 93, 94, 95, | |
c4ce6853 | 103 | 96, 97, 98, 99, 100}; |
ab835497 | 104 | |
7d167afd JJ |
105 | /* Vector, indexed by hard register number, which contains 1 |
106 | for a register that is allowable in a candidate for leaf | |
107 | function treatment. */ | |
108 | char sparc_leaf_regs[] = | |
109 | { 1, 1, 1, 1, 1, 1, 1, 1, | |
110 | 0, 0, 0, 0, 0, 0, 1, 0, | |
111 | 0, 0, 0, 0, 0, 0, 0, 0, | |
112 | 1, 1, 1, 1, 1, 1, 0, 1, | |
113 | 1, 1, 1, 1, 1, 1, 1, 1, | |
114 | 1, 1, 1, 1, 1, 1, 1, 1, | |
115 | 1, 1, 1, 1, 1, 1, 1, 1, | |
116 | 1, 1, 1, 1, 1, 1, 1, 1, | |
117 | 1, 1, 1, 1, 1, 1, 1, 1, | |
118 | 1, 1, 1, 1, 1, 1, 1, 1, | |
119 | 1, 1, 1, 1, 1, 1, 1, 1, | |
120 | 1, 1, 1, 1, 1, 1, 1, 1, | |
121 | 1, 1, 1, 1, 1}; | |
122 | ||
ab835497 RK |
123 | /* Name of where we pretend to think the frame pointer points. |
124 | Normally, this is "%fp", but if we are in a leaf procedure, | |
61a55e8b DE |
125 | this is "%sp+something". We record "something" separately as it may be |
126 | too big for reg+constant addressing. */ | |
127 | ||
3bb5de61 | 128 | static const char *frame_base_name; |
61a55e8b | 129 | static int frame_base_offset; |
ab835497 | 130 | |
f6da8bc3 KG |
131 | static void sparc_init_modes PARAMS ((void)); |
132 | static int save_regs PARAMS ((FILE *, int, int, const char *, | |
c85f7c16 | 133 | int, int, int)); |
f6da8bc3 KG |
134 | static int restore_regs PARAMS ((FILE *, int, int, const char *, int, int)); |
135 | static void build_big_number PARAMS ((FILE *, int, const char *)); | |
136 | static int function_arg_slotno PARAMS ((const CUMULATIVE_ARGS *, | |
c85f7c16 JL |
137 | enum machine_mode, tree, int, int, |
138 | int *, int *)); | |
8947065c | 139 | |
f6da8bc3 KG |
140 | static int supersparc_adjust_cost PARAMS ((rtx, rtx, rtx, int)); |
141 | static int hypersparc_adjust_cost PARAMS ((rtx, rtx, rtx, int)); | |
f6da8bc3 KG |
142 | |
143 | static void sparc_output_addr_vec PARAMS ((rtx)); | |
144 | static void sparc_output_addr_diff_vec PARAMS ((rtx)); | |
145 | static void sparc_output_deferred_case_vectors PARAMS ((void)); | |
f6da8bc3 KG |
146 | static int check_return_regs PARAMS ((rtx)); |
147 | static int epilogue_renumber PARAMS ((rtx *, int)); | |
301d03af | 148 | static bool sparc_assemble_integer PARAMS ((rtx, unsigned int, int)); |
4df1190a | 149 | static int set_extends PARAMS ((rtx)); |
e77d72cb | 150 | static void output_restore_regs PARAMS ((FILE *, int)); |
08c148a8 NB |
151 | static void sparc_output_function_prologue PARAMS ((FILE *, HOST_WIDE_INT)); |
152 | static void sparc_output_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT)); | |
153 | static void sparc_flat_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT)); | |
154 | static void sparc_flat_function_prologue PARAMS ((FILE *, HOST_WIDE_INT)); | |
155 | static void sparc_nonflat_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT, | |
156 | int)); | |
157 | static void sparc_nonflat_function_prologue PARAMS ((FILE *, HOST_WIDE_INT, | |
158 | int)); | |
ede75ee8 | 159 | #ifdef OBJECT_FORMAT_ELF |
715bdd29 | 160 | static void sparc_elf_asm_named_section PARAMS ((const char *, unsigned int)); |
ede75ee8 | 161 | #endif |
ae46c4e0 RH |
162 | static void sparc_aout_select_section PARAMS ((tree, int, |
163 | unsigned HOST_WIDE_INT)) | |
164 | ATTRIBUTE_UNUSED; | |
b64a1b53 RH |
165 | static void sparc_aout_select_rtx_section PARAMS ((enum machine_mode, rtx, |
166 | unsigned HOST_WIDE_INT)) | |
167 | ATTRIBUTE_UNUSED; | |
c237e94a ZW |
168 | |
169 | static int sparc_adjust_cost PARAMS ((rtx, rtx, rtx, int)); | |
170 | static int sparc_issue_rate PARAMS ((void)); | |
c237e94a | 171 | static void sparc_sched_init PARAMS ((FILE *, int, int)); |
fae15c93 VM |
172 | static int sparc_use_dfa_pipeline_interface PARAMS ((void)); |
173 | static int sparc_use_sched_lookahead PARAMS ((void)); | |
73985940 RH |
174 | |
175 | static void emit_soft_tfmode_libcall PARAMS ((const char *, int, rtx *)); | |
176 | static void emit_soft_tfmode_binop PARAMS ((enum rtx_code, rtx *)); | |
177 | static void emit_soft_tfmode_unop PARAMS ((enum rtx_code, rtx *)); | |
178 | static void emit_soft_tfmode_cvt PARAMS ((enum rtx_code, rtx *)); | |
179 | static void emit_hard_tfmode_operation PARAMS ((enum rtx_code, rtx *)); | |
fb49053f | 180 | |
4977bab6 | 181 | static bool sparc_function_ok_for_sibcall PARAMS ((tree, tree)); |
3961e8fe RH |
182 | static void sparc_output_mi_thunk PARAMS ((FILE *, tree, HOST_WIDE_INT, |
183 | HOST_WIDE_INT, tree)); | |
3c50106f | 184 | static bool sparc_rtx_costs PARAMS ((rtx, int, int, int *)); |
61a55e8b DE |
185 | \f |
186 | /* Option handling. */ | |
187 | ||
a0a301fc | 188 | /* Code model option as passed by user. */ |
3bb5de61 | 189 | const char *sparc_cmodel_string; |
a0a301fc DE |
190 | /* Parsed value. */ |
191 | enum cmodel sparc_cmodel; | |
192 | ||
1cb36a98 RH |
193 | char sparc_hard_reg_printed[8]; |
194 | ||
16956f6e DE |
195 | struct sparc_cpu_select sparc_select[] = |
196 | { | |
197 | /* switch name, tune arch */ | |
198 | { (char *)0, "default", 1, 1 }, | |
199 | { (char *)0, "-mcpu=", 1, 1 }, | |
200 | { (char *)0, "-mtune=", 1, 0 }, | |
db3d4438 | 201 | { 0, 0, 0, 0 } |
16956f6e | 202 | }; |
733f53f5 | 203 | |
16956f6e DE |
204 | /* CPU type. This is set from TARGET_CPU_DEFAULT and -m{cpu,tune}=xxx. */ |
205 | enum processor_type sparc_cpu; | |
672a6f42 NB |
206 | \f |
207 | /* Initialize the GCC target structure. */ | |
301d03af RS |
208 | |
209 | /* The sparc default is to use .half rather than .short for aligned | |
210 | HI objects. Use .word instead of .long on non-ELF systems. */ | |
211 | #undef TARGET_ASM_ALIGNED_HI_OP | |
212 | #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t" | |
213 | #ifndef OBJECT_FORMAT_ELF | |
214 | #undef TARGET_ASM_ALIGNED_SI_OP | |
215 | #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t" | |
216 | #endif | |
217 | ||
218 | #undef TARGET_ASM_UNALIGNED_HI_OP | |
219 | #define TARGET_ASM_UNALIGNED_HI_OP "\t.uahalf\t" | |
220 | #undef TARGET_ASM_UNALIGNED_SI_OP | |
221 | #define TARGET_ASM_UNALIGNED_SI_OP "\t.uaword\t" | |
222 | #undef TARGET_ASM_UNALIGNED_DI_OP | |
223 | #define TARGET_ASM_UNALIGNED_DI_OP "\t.uaxword\t" | |
224 | ||
225 | /* The target hook has to handle DI-mode values. */ | |
226 | #undef TARGET_ASM_INTEGER | |
227 | #define TARGET_ASM_INTEGER sparc_assemble_integer | |
228 | ||
08c148a8 NB |
229 | #undef TARGET_ASM_FUNCTION_PROLOGUE |
230 | #define TARGET_ASM_FUNCTION_PROLOGUE sparc_output_function_prologue | |
231 | #undef TARGET_ASM_FUNCTION_EPILOGUE | |
232 | #define TARGET_ASM_FUNCTION_EPILOGUE sparc_output_function_epilogue | |
733f53f5 | 233 | |
c237e94a ZW |
234 | #undef TARGET_SCHED_ADJUST_COST |
235 | #define TARGET_SCHED_ADJUST_COST sparc_adjust_cost | |
236 | #undef TARGET_SCHED_ISSUE_RATE | |
237 | #define TARGET_SCHED_ISSUE_RATE sparc_issue_rate | |
c237e94a ZW |
238 | #undef TARGET_SCHED_INIT |
239 | #define TARGET_SCHED_INIT sparc_sched_init | |
fae15c93 VM |
240 | #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE |
241 | #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE sparc_use_dfa_pipeline_interface | |
242 | #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD | |
243 | #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD sparc_use_sched_lookahead | |
c237e94a | 244 | |
4977bab6 ZW |
245 | #undef TARGET_FUNCTION_OK_FOR_SIBCALL |
246 | #define TARGET_FUNCTION_OK_FOR_SIBCALL sparc_function_ok_for_sibcall | |
247 | ||
c590b625 RH |
248 | #undef TARGET_ASM_OUTPUT_MI_THUNK |
249 | #define TARGET_ASM_OUTPUT_MI_THUNK sparc_output_mi_thunk | |
3961e8fe RH |
250 | #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK |
251 | #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall | |
c590b625 | 252 | |
3c50106f RH |
253 | #undef TARGET_RTX_COSTS |
254 | #define TARGET_RTX_COSTS sparc_rtx_costs | |
dcefdf67 RH |
255 | #undef TARGET_ADDRESS_COST |
256 | #define TARGET_ADDRESS_COST hook_int_rtx_0 | |
3c50106f | 257 | |
f6897b10 | 258 | struct gcc_target targetm = TARGET_INITIALIZER; |
672a6f42 | 259 | \f |
61a55e8b DE |
260 | /* Validate and override various options, and do some machine dependent |
261 | initialization. */ | |
262 | ||
263 | void | |
264 | sparc_override_options () | |
265 | { | |
a0a301fc | 266 | static struct code_model { |
8b60264b KG |
267 | const char *const name; |
268 | const int value; | |
269 | } const cmodels[] = { | |
a0a301fc DE |
270 | { "32", CM_32 }, |
271 | { "medlow", CM_MEDLOW }, | |
272 | { "medmid", CM_MEDMID }, | |
273 | { "medany", CM_MEDANY }, | |
274 | { "embmedany", CM_EMBMEDANY }, | |
275 | { 0, 0 } | |
276 | }; | |
8b60264b | 277 | const struct code_model *cmodel; |
16956f6e | 278 | /* Map TARGET_CPU_DEFAULT to value for -m{arch,tune}=. */ |
733f53f5 | 279 | static struct cpu_default { |
8b60264b KG |
280 | const int cpu; |
281 | const char *const name; | |
282 | } const cpu_default[] = { | |
a0a301fc | 283 | /* There must be one entry here for each TARGET_CPU value. */ |
16956f6e | 284 | { TARGET_CPU_sparc, "cypress" }, |
3592ea0d | 285 | { TARGET_CPU_sparclet, "tsc701" }, |
16956f6e | 286 | { TARGET_CPU_sparclite, "f930" }, |
a0a301fc | 287 | { TARGET_CPU_v8, "v8" }, |
8947065c RH |
288 | { TARGET_CPU_hypersparc, "hypersparc" }, |
289 | { TARGET_CPU_sparclite86x, "sparclite86x" }, | |
a0a301fc DE |
290 | { TARGET_CPU_supersparc, "supersparc" }, |
291 | { TARGET_CPU_v9, "v9" }, | |
ba542005 | 292 | { TARGET_CPU_ultrasparc, "ultrasparc" }, |
fae15c93 | 293 | { TARGET_CPU_ultrasparc3, "ultrasparc3" }, |
db3d4438 | 294 | { 0, 0 } |
733f53f5 | 295 | }; |
8b60264b | 296 | const struct cpu_default *def; |
16956f6e | 297 | /* Table of values for -m{cpu,tune}=. */ |
733f53f5 | 298 | static struct cpu_table { |
8b60264b KG |
299 | const char *const name; |
300 | const enum processor_type processor; | |
301 | const int disable; | |
302 | const int enable; | |
303 | } const cpu_table[] = { | |
16956f6e DE |
304 | { "v7", PROCESSOR_V7, MASK_ISA, 0 }, |
305 | { "cypress", PROCESSOR_CYPRESS, MASK_ISA, 0 }, | |
306 | { "v8", PROCESSOR_V8, MASK_ISA, MASK_V8 }, | |
733f53f5 | 307 | /* TI TMS390Z55 supersparc */ |
16956f6e DE |
308 | { "supersparc", PROCESSOR_SUPERSPARC, MASK_ISA, MASK_V8 }, |
309 | { "sparclite", PROCESSOR_SPARCLITE, MASK_ISA, MASK_SPARCLITE }, | |
733f53f5 DE |
310 | /* The Fujitsu MB86930 is the original sparclite chip, with no fpu. |
311 | The Fujitsu MB86934 is the recent sparclite chip, with an fpu. */ | |
16956f6e DE |
312 | { "f930", PROCESSOR_F930, MASK_ISA|MASK_FPU, MASK_SPARCLITE }, |
313 | { "f934", PROCESSOR_F934, MASK_ISA, MASK_SPARCLITE|MASK_FPU }, | |
8947065c | 314 | { "hypersparc", PROCESSOR_HYPERSPARC, MASK_ISA, MASK_V8|MASK_FPU }, |
d3ec6b06 VM |
315 | { "sparclite86x", PROCESSOR_SPARCLITE86X, MASK_ISA|MASK_FPU, |
316 | MASK_SPARCLITE }, | |
16956f6e | 317 | { "sparclet", PROCESSOR_SPARCLET, MASK_ISA, MASK_SPARCLET }, |
733f53f5 | 318 | /* TEMIC sparclet */ |
3592ea0d | 319 | { "tsc701", PROCESSOR_TSC701, MASK_ISA, MASK_SPARCLET }, |
16956f6e | 320 | { "v9", PROCESSOR_V9, MASK_ISA, MASK_V9 }, |
5cb01b65 JJ |
321 | /* TI ultrasparc I, II, IIi */ |
322 | { "ultrasparc", PROCESSOR_ULTRASPARC, MASK_ISA, MASK_V9 | |
323 | /* Although insns using %y are deprecated, it is a clear win on current | |
80ffc95e | 324 | ultrasparcs. */ |
3276910d | 325 | |MASK_DEPRECATED_V8_INSNS}, |
fae15c93 VM |
326 | /* TI ultrasparc III */ |
327 | /* ??? Check if %y issue still holds true in ultra3. */ | |
328 | { "ultrasparc3", PROCESSOR_ULTRASPARC3, MASK_ISA, MASK_V9|MASK_DEPRECATED_V8_INSNS}, | |
db3d4438 | 329 | { 0, 0, 0, 0 } |
733f53f5 | 330 | }; |
8b60264b KG |
331 | const struct cpu_table *cpu; |
332 | const struct sparc_cpu_select *sel; | |
a0a301fc | 333 | int fpu; |
345a6161 | 334 | |
a0a301fc DE |
335 | #ifndef SPARC_BI_ARCH |
336 | /* Check for unsupported architecture size. */ | |
337 | if (! TARGET_64BIT != DEFAULT_ARCH32_P) | |
3276910d RK |
338 | error ("%s is not supported by this configuration", |
339 | DEFAULT_ARCH32_P ? "-m64" : "-m32"); | |
a0a301fc DE |
340 | #endif |
341 | ||
4710d3eb JJ |
342 | /* We force all 64bit archs to use 128 bit long double */ |
343 | if (TARGET_64BIT && ! TARGET_LONG_DOUBLE_128) | |
344 | { | |
345 | error ("-mlong-double-64 not allowed with -m64"); | |
346 | target_flags |= MASK_LONG_DOUBLE_128; | |
347 | } | |
348 | ||
a0a301fc DE |
349 | /* Code model selection. */ |
350 | sparc_cmodel = SPARC_DEFAULT_CMODEL; | |
345a6161 DM |
351 | |
352 | #ifdef SPARC_BI_ARCH | |
353 | if (TARGET_ARCH32) | |
354 | sparc_cmodel = CM_32; | |
355 | #endif | |
356 | ||
a0a301fc DE |
357 | if (sparc_cmodel_string != NULL) |
358 | { | |
359 | if (TARGET_ARCH64) | |
360 | { | |
361 | for (cmodel = &cmodels[0]; cmodel->name; cmodel++) | |
362 | if (strcmp (sparc_cmodel_string, cmodel->name) == 0) | |
363 | break; | |
364 | if (cmodel->name == NULL) | |
365 | error ("bad value (%s) for -mcmodel= switch", sparc_cmodel_string); | |
366 | else | |
367 | sparc_cmodel = cmodel->value; | |
368 | } | |
369 | else | |
370 | error ("-mcmodel= is not supported on 32 bit systems"); | |
371 | } | |
16956f6e | 372 | |
a0a301fc | 373 | fpu = TARGET_FPU; /* save current -mfpu status */ |
1f1406b4 | 374 | |
a0a301fc | 375 | /* Set the default CPU. */ |
16956f6e DE |
376 | for (def = &cpu_default[0]; def->name; ++def) |
377 | if (def->cpu == TARGET_CPU_DEFAULT) | |
378 | break; | |
379 | if (! def->name) | |
380 | abort (); | |
381 | sparc_select[0].string = def->name; | |
382 | ||
383 | for (sel = &sparc_select[0]; sel->name; ++sel) | |
61a55e8b | 384 | { |
16956f6e | 385 | if (sel->string) |
733f53f5 | 386 | { |
16956f6e DE |
387 | for (cpu = &cpu_table[0]; cpu->name; ++cpu) |
388 | if (! strcmp (sel->string, cpu->name)) | |
389 | { | |
390 | if (sel->set_tune_p) | |
391 | sparc_cpu = cpu->processor; | |
392 | ||
393 | if (sel->set_arch_p) | |
394 | { | |
395 | target_flags &= ~cpu->disable; | |
396 | target_flags |= cpu->enable; | |
397 | } | |
398 | break; | |
399 | } | |
400 | ||
401 | if (! cpu->name) | |
402 | error ("bad value (%s) for %s switch", sel->string, sel->name); | |
733f53f5 | 403 | } |
61a55e8b | 404 | } |
97da85b7 | 405 | |
1f1406b4 | 406 | /* If -mfpu or -mno-fpu was explicitly used, don't override with |
46cc13b3 RO |
407 | the processor default. Clear MASK_FPU_SET to avoid confusing |
408 | the reverse mapping from switch values to names. */ | |
1f1406b4 | 409 | if (TARGET_FPU_SET) |
46cc13b3 RO |
410 | { |
411 | target_flags = (target_flags & ~MASK_FPU) | fpu; | |
412 | target_flags &= ~MASK_FPU_SET; | |
413 | } | |
1f1406b4 | 414 | |
a5774a7d JJ |
415 | /* Don't allow -mvis if FPU is disabled. */ |
416 | if (! TARGET_FPU) | |
417 | target_flags &= ~MASK_VIS; | |
418 | ||
419 | /* -mvis assumes UltraSPARC+, so we are sure v9 instructions | |
420 | are available. | |
421 | -m64 also implies v9. */ | |
422 | if (TARGET_VIS || TARGET_ARCH64) | |
c4031a04 JJ |
423 | { |
424 | target_flags |= MASK_V9; | |
425 | target_flags &= ~(MASK_V8 | MASK_SPARCLET | MASK_SPARCLITE); | |
426 | } | |
a5774a7d | 427 | |
16956f6e DE |
428 | /* Use the deprecated v8 insns for sparc64 in 32 bit mode. */ |
429 | if (TARGET_V9 && TARGET_ARCH32) | |
733f53f5 | 430 | target_flags |= MASK_DEPRECATED_V8_INSNS; |
61a55e8b | 431 | |
345a6161 DM |
432 | /* V8PLUS requires V9, makes no sense in 64 bit mode. */ |
433 | if (! TARGET_V9 || TARGET_ARCH64) | |
284d86e9 JC |
434 | target_flags &= ~MASK_V8PLUS; |
435 | ||
82d6b402 RH |
436 | /* Don't use stack biasing in 32 bit mode. */ |
437 | if (TARGET_ARCH32) | |
438 | target_flags &= ~MASK_STACK_BIAS; | |
f952a238 | 439 | |
efa3896a | 440 | /* Supply a default value for align_functions. */ |
fae15c93 VM |
441 | if (align_functions == 0 |
442 | && (sparc_cpu == PROCESSOR_ULTRASPARC | |
443 | || sparc_cpu == PROCESSOR_ULTRASPARC3)) | |
efa3896a | 444 | align_functions = 32; |
bf62bbf1 | 445 | |
82d6b402 RH |
446 | /* Validate PCC_STRUCT_RETURN. */ |
447 | if (flag_pcc_struct_return == DEFAULT_PCC_STRUCT_RETURN) | |
448 | flag_pcc_struct_return = (TARGET_ARCH64 ? 0 : 1); | |
449 | ||
301d03af RS |
450 | /* Only use .uaxword when compiling for a 64-bit target. */ |
451 | if (!TARGET_ARCH64) | |
452 | targetm.asm_out.unaligned_op.di = NULL; | |
453 | ||
61a55e8b DE |
454 | /* Do various machine dependent initializations. */ |
455 | sparc_init_modes (); | |
456 | } | |
457 | \f | |
cd5fb1ee DE |
458 | /* Miscellaneous utilities. */ |
459 | ||
460 | /* Nonzero if CODE, a comparison, is suitable for use in v9 conditional move | |
461 | or branch on register contents instructions. */ | |
462 | ||
463 | int | |
464 | v9_regcmp_p (code) | |
465 | enum rtx_code code; | |
466 | { | |
467 | return (code == EQ || code == NE || code == GE || code == LT | |
468 | || code == LE || code == GT); | |
469 | } | |
bfd6bc60 | 470 | |
cd5fb1ee DE |
471 | \f |
472 | /* Operand constraints. */ | |
473 | ||
5e7a8ee0 | 474 | /* Return nonzero only if OP is a register of mode MODE, |
e6c1be7e | 475 | or const0_rtx. */ |
c4ce6853 | 476 | |
ab835497 RK |
477 | int |
478 | reg_or_0_operand (op, mode) | |
479 | rtx op; | |
480 | enum machine_mode mode; | |
481 | { | |
c4ce6853 DE |
482 | if (register_operand (op, mode)) |
483 | return 1; | |
c4ce6853 | 484 | if (op == const0_rtx) |
ab835497 | 485 | return 1; |
5b486ce0 | 486 | if (GET_MODE (op) == VOIDmode && GET_CODE (op) == CONST_DOUBLE |
ab835497 RK |
487 | && CONST_DOUBLE_HIGH (op) == 0 |
488 | && CONST_DOUBLE_LOW (op) == 0) | |
489 | return 1; | |
7ce86678 | 490 | if (fp_zero_operand (op, mode)) |
302484ff | 491 | return 1; |
ab835497 RK |
492 | return 0; |
493 | } | |
494 | ||
5e7a8ee0 | 495 | /* Return nonzero only if OP is const1_rtx. */ |
84ea5bc1 JJ |
496 | |
497 | int | |
498 | const1_operand (op, mode) | |
499 | rtx op; | |
500 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
501 | { | |
502 | return op == const1_rtx; | |
503 | } | |
504 | ||
302484ff | 505 | /* Nonzero if OP is a floating point value with value 0.0. */ |
c4ce6853 | 506 | |
302484ff | 507 | int |
7ce86678 | 508 | fp_zero_operand (op, mode) |
302484ff | 509 | rtx op; |
7ce86678 | 510 | enum machine_mode mode; |
302484ff | 511 | { |
7ce86678 RH |
512 | if (GET_MODE_CLASS (GET_MODE (op)) != MODE_FLOAT) |
513 | return 0; | |
514 | return op == CONST0_RTX (mode); | |
302484ff JW |
515 | } |
516 | ||
2a732575 JJ |
517 | /* Nonzero if OP is a register operand in floating point register. */ |
518 | ||
519 | int | |
520 | fp_register_operand (op, mode) | |
521 | rtx op; | |
522 | enum machine_mode mode; | |
523 | { | |
524 | if (! register_operand (op, mode)) | |
525 | return 0; | |
526 | if (GET_CODE (op) == SUBREG) | |
527 | op = SUBREG_REG (op); | |
528 | return GET_CODE (op) == REG && SPARC_FP_REG_P (REGNO (op)); | |
529 | } | |
530 | ||
62190128 DM |
531 | /* Nonzero if OP is a floating point constant which can |
532 | be loaded into an integer register using a single | |
533 | sethi instruction. */ | |
534 | ||
535 | int | |
536 | fp_sethi_p (op) | |
537 | rtx op; | |
538 | { | |
539 | if (GET_CODE (op) == CONST_DOUBLE) | |
540 | { | |
541 | REAL_VALUE_TYPE r; | |
542 | long i; | |
543 | ||
544 | REAL_VALUE_FROM_CONST_DOUBLE (r, op); | |
545 | if (REAL_VALUES_EQUAL (r, dconst0) && | |
546 | ! REAL_VALUE_MINUS_ZERO (r)) | |
547 | return 0; | |
548 | REAL_VALUE_TO_TARGET_SINGLE (r, i); | |
549 | if (SPARC_SETHI_P (i)) | |
550 | return 1; | |
551 | } | |
552 | ||
553 | return 0; | |
554 | } | |
555 | ||
556 | /* Nonzero if OP is a floating point constant which can | |
557 | be loaded into an integer register using a single | |
558 | mov instruction. */ | |
559 | ||
560 | int | |
561 | fp_mov_p (op) | |
562 | rtx op; | |
563 | { | |
564 | if (GET_CODE (op) == CONST_DOUBLE) | |
565 | { | |
566 | REAL_VALUE_TYPE r; | |
567 | long i; | |
568 | ||
569 | REAL_VALUE_FROM_CONST_DOUBLE (r, op); | |
570 | if (REAL_VALUES_EQUAL (r, dconst0) && | |
571 | ! REAL_VALUE_MINUS_ZERO (r)) | |
572 | return 0; | |
573 | REAL_VALUE_TO_TARGET_SINGLE (r, i); | |
574 | if (SPARC_SIMM13_P (i)) | |
575 | return 1; | |
576 | } | |
577 | ||
578 | return 0; | |
579 | } | |
580 | ||
581 | /* Nonzero if OP is a floating point constant which can | |
582 | be loaded into an integer register using a high/losum | |
583 | instruction sequence. */ | |
584 | ||
585 | int | |
586 | fp_high_losum_p (op) | |
587 | rtx op; | |
588 | { | |
589 | /* The constraints calling this should only be in | |
590 | SFmode move insns, so any constant which cannot | |
591 | be moved using a single insn will do. */ | |
592 | if (GET_CODE (op) == CONST_DOUBLE) | |
593 | { | |
594 | REAL_VALUE_TYPE r; | |
595 | long i; | |
596 | ||
597 | REAL_VALUE_FROM_CONST_DOUBLE (r, op); | |
598 | if (REAL_VALUES_EQUAL (r, dconst0) && | |
599 | ! REAL_VALUE_MINUS_ZERO (r)) | |
600 | return 0; | |
601 | REAL_VALUE_TO_TARGET_SINGLE (r, i); | |
602 | if (! SPARC_SETHI_P (i) | |
603 | && ! SPARC_SIMM13_P (i)) | |
604 | return 1; | |
605 | } | |
606 | ||
607 | return 0; | |
608 | } | |
609 | ||
61a55e8b DE |
610 | /* Nonzero if OP is an integer register. */ |
611 | ||
612 | int | |
613 | intreg_operand (op, mode) | |
614 | rtx op; | |
487a6e06 | 615 | enum machine_mode mode ATTRIBUTE_UNUSED; |
61a55e8b DE |
616 | { |
617 | return (register_operand (op, SImode) | |
a9e27770 | 618 | || (TARGET_ARCH64 && register_operand (op, DImode))); |
61a55e8b DE |
619 | } |
620 | ||
621 | /* Nonzero if OP is a floating point condition code register. */ | |
622 | ||
623 | int | |
c4ce6853 | 624 | fcc_reg_operand (op, mode) |
61a55e8b DE |
625 | rtx op; |
626 | enum machine_mode mode; | |
627 | { | |
628 | /* This can happen when recog is called from combine. Op may be a MEM. | |
629 | Fail instead of calling abort in this case. */ | |
c4ce6853 | 630 | if (GET_CODE (op) != REG) |
61a55e8b | 631 | return 0; |
304b7a23 | 632 | |
c4ce6853 | 633 | if (mode != VOIDmode && mode != GET_MODE (op)) |
61a55e8b | 634 | return 0; |
304b7a23 DE |
635 | if (mode == VOIDmode |
636 | && (GET_MODE (op) != CCFPmode && GET_MODE (op) != CCFPEmode)) | |
637 | return 0; | |
61a55e8b | 638 | |
c4ce6853 | 639 | #if 0 /* ??? ==> 1 when %fcc0-3 are pseudos first. See gen_compare_reg(). */ |
61a55e8b DE |
640 | if (reg_renumber == 0) |
641 | return REGNO (op) >= FIRST_PSEUDO_REGISTER; | |
642 | return REGNO_OK_FOR_CCFP_P (REGNO (op)); | |
643 | #else | |
c4ce6853 | 644 | return (unsigned) REGNO (op) - SPARC_FIRST_V9_FCC_REG < 4; |
61a55e8b DE |
645 | #endif |
646 | } | |
647 | ||
0b82d204 JJ |
648 | /* Nonzero if OP is a floating point condition code fcc0 register. */ |
649 | ||
650 | int | |
651 | fcc0_reg_operand (op, mode) | |
652 | rtx op; | |
653 | enum machine_mode mode; | |
654 | { | |
655 | /* This can happen when recog is called from combine. Op may be a MEM. | |
656 | Fail instead of calling abort in this case. */ | |
657 | if (GET_CODE (op) != REG) | |
658 | return 0; | |
659 | ||
660 | if (mode != VOIDmode && mode != GET_MODE (op)) | |
661 | return 0; | |
662 | if (mode == VOIDmode | |
663 | && (GET_MODE (op) != CCFPmode && GET_MODE (op) != CCFPEmode)) | |
664 | return 0; | |
665 | ||
666 | return REGNO (op) == SPARC_FCC_REG; | |
667 | } | |
668 | ||
c4ce6853 DE |
669 | /* Nonzero if OP is an integer or floating point condition code register. */ |
670 | ||
671 | int | |
672 | icc_or_fcc_reg_operand (op, mode) | |
673 | rtx op; | |
674 | enum machine_mode mode; | |
675 | { | |
676 | if (GET_CODE (op) == REG && REGNO (op) == SPARC_ICC_REG) | |
304b7a23 DE |
677 | { |
678 | if (mode != VOIDmode && mode != GET_MODE (op)) | |
679 | return 0; | |
680 | if (mode == VOIDmode | |
681 | && GET_MODE (op) != CCmode && GET_MODE (op) != CCXmode) | |
682 | return 0; | |
683 | return 1; | |
684 | } | |
685 | ||
c4ce6853 DE |
686 | return fcc_reg_operand (op, mode); |
687 | } | |
688 | ||
ab835497 RK |
689 | /* Nonzero if OP can appear as the dest of a RESTORE insn. */ |
690 | int | |
691 | restore_operand (op, mode) | |
692 | rtx op; | |
693 | enum machine_mode mode; | |
694 | { | |
695 | return (GET_CODE (op) == REG && GET_MODE (op) == mode | |
696 | && (REGNO (op) < 8 || (REGNO (op) >= 24 && REGNO (op) < 32))); | |
697 | } | |
698 | ||
401cec23 JW |
699 | /* Call insn on SPARC can take a PC-relative constant address, or any regular |
700 | memory address. */ | |
ab835497 RK |
701 | |
702 | int | |
703 | call_operand (op, mode) | |
704 | rtx op; | |
705 | enum machine_mode mode; | |
706 | { | |
707 | if (GET_CODE (op) != MEM) | |
708 | abort (); | |
709 | op = XEXP (op, 0); | |
2445f289 | 710 | return (symbolic_operand (op, mode) || memory_address_p (Pmode, op)); |
ab835497 RK |
711 | } |
712 | ||
713 | int | |
714 | call_operand_address (op, mode) | |
715 | rtx op; | |
716 | enum machine_mode mode; | |
717 | { | |
2445f289 | 718 | return (symbolic_operand (op, mode) || memory_address_p (Pmode, op)); |
ab835497 RK |
719 | } |
720 | ||
721 | /* Returns 1 if OP is either a symbol reference or a sum of a symbol | |
722 | reference and a constant. */ | |
723 | ||
724 | int | |
725 | symbolic_operand (op, mode) | |
726 | register rtx op; | |
727 | enum machine_mode mode; | |
728 | { | |
6871dd65 RH |
729 | enum machine_mode omode = GET_MODE (op); |
730 | ||
731 | if (omode != mode && omode != VOIDmode && mode != VOIDmode) | |
732 | return 0; | |
733 | ||
ab835497 RK |
734 | switch (GET_CODE (op)) |
735 | { | |
736 | case SYMBOL_REF: | |
737 | case LABEL_REF: | |
738 | return 1; | |
739 | ||
740 | case CONST: | |
741 | op = XEXP (op, 0); | |
742 | return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF | |
743 | || GET_CODE (XEXP (op, 0)) == LABEL_REF) | |
744 | && GET_CODE (XEXP (op, 1)) == CONST_INT); | |
745 | ||
ab835497 RK |
746 | default: |
747 | return 0; | |
748 | } | |
749 | } | |
750 | ||
751 | /* Return truth value of statement that OP is a symbolic memory | |
752 | operand of mode MODE. */ | |
753 | ||
754 | int | |
755 | symbolic_memory_operand (op, mode) | |
756 | rtx op; | |
487a6e06 | 757 | enum machine_mode mode ATTRIBUTE_UNUSED; |
ab835497 RK |
758 | { |
759 | if (GET_CODE (op) == SUBREG) | |
760 | op = SUBREG_REG (op); | |
761 | if (GET_CODE (op) != MEM) | |
762 | return 0; | |
763 | op = XEXP (op, 0); | |
764 | return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST | |
765 | || GET_CODE (op) == HIGH || GET_CODE (op) == LABEL_REF); | |
766 | } | |
767 | ||
5ab7138b DE |
768 | /* Return truth value of statement that OP is a LABEL_REF of mode MODE. */ |
769 | ||
770 | int | |
771 | label_ref_operand (op, mode) | |
772 | rtx op; | |
773 | enum machine_mode mode; | |
774 | { | |
775 | if (GET_CODE (op) != LABEL_REF) | |
776 | return 0; | |
777 | if (GET_MODE (op) != mode) | |
778 | return 0; | |
779 | return 1; | |
780 | } | |
781 | ||
95726648 DE |
782 | /* Return 1 if the operand is an argument used in generating pic references |
783 | in either the medium/low or medium/anywhere code models of sparc64. */ | |
784 | ||
785 | int | |
786 | sp64_medium_pic_operand (op, mode) | |
787 | rtx op; | |
487a6e06 | 788 | enum machine_mode mode ATTRIBUTE_UNUSED; |
95726648 DE |
789 | { |
790 | /* Check for (const (minus (symbol_ref:GOT) | |
791 | (const (minus (label) (pc))))). */ | |
792 | if (GET_CODE (op) != CONST) | |
793 | return 0; | |
794 | op = XEXP (op, 0); | |
795 | if (GET_CODE (op) != MINUS) | |
796 | return 0; | |
797 | if (GET_CODE (XEXP (op, 0)) != SYMBOL_REF) | |
798 | return 0; | |
799 | /* ??? Ensure symbol is GOT. */ | |
800 | if (GET_CODE (XEXP (op, 1)) != CONST) | |
801 | return 0; | |
802 | if (GET_CODE (XEXP (XEXP (op, 1), 0)) != MINUS) | |
803 | return 0; | |
804 | return 1; | |
805 | } | |
806 | ||
61a55e8b DE |
807 | /* Return 1 if the operand is a data segment reference. This includes |
808 | the readonly data segment, or in other words anything but the text segment. | |
809 | This is needed in the medium/anywhere code model on v9. These values | |
a0a301fc | 810 | are accessed with EMBMEDANY_BASE_REG. */ |
61a55e8b DE |
811 | |
812 | int | |
813 | data_segment_operand (op, mode) | |
814 | rtx op; | |
487a6e06 | 815 | enum machine_mode mode ATTRIBUTE_UNUSED; |
61a55e8b DE |
816 | { |
817 | switch (GET_CODE (op)) | |
818 | { | |
819 | case SYMBOL_REF : | |
72628c61 | 820 | return ! SYMBOL_REF_FUNCTION_P (op); |
61a55e8b | 821 | case PLUS : |
95726648 DE |
822 | /* Assume canonical format of symbol + constant. |
823 | Fall through. */ | |
61a55e8b | 824 | case CONST : |
b1474bb7 | 825 | return data_segment_operand (XEXP (op, 0), VOIDmode); |
61a55e8b DE |
826 | default : |
827 | return 0; | |
828 | } | |
829 | } | |
830 | ||
831 | /* Return 1 if the operand is a text segment reference. | |
832 | This is needed in the medium/anywhere code model on v9. */ | |
833 | ||
834 | int | |
835 | text_segment_operand (op, mode) | |
836 | rtx op; | |
487a6e06 | 837 | enum machine_mode mode ATTRIBUTE_UNUSED; |
61a55e8b DE |
838 | { |
839 | switch (GET_CODE (op)) | |
840 | { | |
841 | case LABEL_REF : | |
842 | return 1; | |
843 | case SYMBOL_REF : | |
72628c61 | 844 | return SYMBOL_REF_FUNCTION_P (op); |
61a55e8b | 845 | case PLUS : |
95726648 DE |
846 | /* Assume canonical format of symbol + constant. |
847 | Fall through. */ | |
61a55e8b | 848 | case CONST : |
b1474bb7 | 849 | return text_segment_operand (XEXP (op, 0), VOIDmode); |
61a55e8b DE |
850 | default : |
851 | return 0; | |
852 | } | |
853 | } | |
854 | ||
ab835497 RK |
855 | /* Return 1 if the operand is either a register or a memory operand that is |
856 | not symbolic. */ | |
857 | ||
858 | int | |
859 | reg_or_nonsymb_mem_operand (op, mode) | |
860 | register rtx op; | |
861 | enum machine_mode mode; | |
862 | { | |
863 | if (register_operand (op, mode)) | |
864 | return 1; | |
865 | ||
866 | if (memory_operand (op, mode) && ! symbolic_memory_operand (op, mode)) | |
867 | return 1; | |
868 | ||
869 | return 0; | |
870 | } | |
871 | ||
ab835497 | 872 | int |
6ac34277 | 873 | splittable_symbolic_memory_operand (op, mode) |
ab835497 | 874 | rtx op; |
487a6e06 | 875 | enum machine_mode mode ATTRIBUTE_UNUSED; |
ab835497 | 876 | { |
6ac34277 DE |
877 | if (GET_CODE (op) != MEM) |
878 | return 0; | |
879 | if (! symbolic_operand (XEXP (op, 0), Pmode)) | |
880 | return 0; | |
881 | return 1; | |
882 | } | |
883 | ||
884 | int | |
885 | splittable_immediate_memory_operand (op, mode) | |
886 | rtx op; | |
487a6e06 | 887 | enum machine_mode mode ATTRIBUTE_UNUSED; |
6ac34277 DE |
888 | { |
889 | if (GET_CODE (op) != MEM) | |
890 | return 0; | |
891 | if (! immediate_operand (XEXP (op, 0), Pmode)) | |
892 | return 0; | |
893 | return 1; | |
ab835497 RK |
894 | } |
895 | ||
896 | /* Return truth value of whether OP is EQ or NE. */ | |
897 | ||
898 | int | |
899 | eq_or_neq (op, mode) | |
900 | rtx op; | |
487a6e06 | 901 | enum machine_mode mode ATTRIBUTE_UNUSED; |
ab835497 RK |
902 | { |
903 | return (GET_CODE (op) == EQ || GET_CODE (op) == NE); | |
904 | } | |
905 | ||
906 | /* Return 1 if this is a comparison operator, but not an EQ, NE, GEU, | |
907 | or LTU for non-floating-point. We handle those specially. */ | |
908 | ||
909 | int | |
910 | normal_comp_operator (op, mode) | |
911 | rtx op; | |
487a6e06 | 912 | enum machine_mode mode ATTRIBUTE_UNUSED; |
ab835497 RK |
913 | { |
914 | enum rtx_code code = GET_CODE (op); | |
915 | ||
916 | if (GET_RTX_CLASS (code) != '<') | |
917 | return 0; | |
918 | ||
4d449554 JW |
919 | if (GET_MODE (XEXP (op, 0)) == CCFPmode |
920 | || GET_MODE (XEXP (op, 0)) == CCFPEmode) | |
ab835497 RK |
921 | return 1; |
922 | ||
923 | return (code != NE && code != EQ && code != GEU && code != LTU); | |
924 | } | |
925 | ||
926 | /* Return 1 if this is a comparison operator. This allows the use of | |
927 | MATCH_OPERATOR to recognize all the branch insns. */ | |
928 | ||
929 | int | |
930 | noov_compare_op (op, mode) | |
931 | register rtx op; | |
487a6e06 | 932 | enum machine_mode mode ATTRIBUTE_UNUSED; |
ab835497 RK |
933 | { |
934 | enum rtx_code code = GET_CODE (op); | |
935 | ||
936 | if (GET_RTX_CLASS (code) != '<') | |
937 | return 0; | |
938 | ||
0b82d204 JJ |
939 | if (GET_MODE (XEXP (op, 0)) == CC_NOOVmode |
940 | || GET_MODE (XEXP (op, 0)) == CCX_NOOVmode) | |
ab835497 RK |
941 | /* These are the only branches which work with CC_NOOVmode. */ |
942 | return (code == EQ || code == NE || code == GE || code == LT); | |
943 | return 1; | |
944 | } | |
945 | ||
0b82d204 JJ |
946 | /* Return 1 if this is a 64-bit comparison operator. This allows the use of |
947 | MATCH_OPERATOR to recognize all the branch insns. */ | |
948 | ||
949 | int | |
950 | noov_compare64_op (op, mode) | |
951 | register rtx op; | |
952 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
953 | { | |
954 | enum rtx_code code = GET_CODE (op); | |
955 | ||
956 | if (! TARGET_V9) | |
957 | return 0; | |
958 | ||
959 | if (GET_RTX_CLASS (code) != '<') | |
960 | return 0; | |
961 | ||
962 | if (GET_MODE (XEXP (op, 0)) == CCX_NOOVmode) | |
963 | /* These are the only branches which work with CCX_NOOVmode. */ | |
964 | return (code == EQ || code == NE || code == GE || code == LT); | |
965 | return (GET_MODE (XEXP (op, 0)) == CCXmode); | |
966 | } | |
967 | ||
61a55e8b DE |
968 | /* Nonzero if OP is a comparison operator suitable for use in v9 |
969 | conditional move or branch on register contents instructions. */ | |
970 | ||
971 | int | |
972 | v9_regcmp_op (op, mode) | |
973 | register rtx op; | |
487a6e06 | 974 | enum machine_mode mode ATTRIBUTE_UNUSED; |
61a55e8b DE |
975 | { |
976 | enum rtx_code code = GET_CODE (op); | |
977 | ||
978 | if (GET_RTX_CLASS (code) != '<') | |
979 | return 0; | |
980 | ||
cd5fb1ee | 981 | return v9_regcmp_p (code); |
61a55e8b DE |
982 | } |
983 | ||
ab835497 RK |
984 | /* Return 1 if this is a SIGN_EXTEND or ZERO_EXTEND operation. */ |
985 | ||
986 | int | |
987 | extend_op (op, mode) | |
988 | rtx op; | |
487a6e06 | 989 | enum machine_mode mode ATTRIBUTE_UNUSED; |
ab835497 RK |
990 | { |
991 | return GET_CODE (op) == SIGN_EXTEND || GET_CODE (op) == ZERO_EXTEND; | |
992 | } | |
993 | ||
994 | /* Return nonzero if OP is an operator of mode MODE which can set | |
995 | the condition codes explicitly. We do not include PLUS and MINUS | |
996 | because these require CC_NOOVmode, which we handle explicitly. */ | |
997 | ||
998 | int | |
999 | cc_arithop (op, mode) | |
1000 | rtx op; | |
487a6e06 | 1001 | enum machine_mode mode ATTRIBUTE_UNUSED; |
ab835497 RK |
1002 | { |
1003 | if (GET_CODE (op) == AND | |
1004 | || GET_CODE (op) == IOR | |
1005 | || GET_CODE (op) == XOR) | |
1006 | return 1; | |
1007 | ||
1008 | return 0; | |
1009 | } | |
1010 | ||
1011 | /* Return nonzero if OP is an operator of mode MODE which can bitwise | |
1012 | complement its second operand and set the condition codes explicitly. */ | |
1013 | ||
1014 | int | |
1015 | cc_arithopn (op, mode) | |
1016 | rtx op; | |
487a6e06 | 1017 | enum machine_mode mode ATTRIBUTE_UNUSED; |
ab835497 RK |
1018 | { |
1019 | /* XOR is not here because combine canonicalizes (xor (not ...) ...) | |
80ffc95e | 1020 | and (xor ... (not ...)) to (not (xor ...)). */ |
ab835497 RK |
1021 | return (GET_CODE (op) == AND |
1022 | || GET_CODE (op) == IOR); | |
1023 | } | |
1024 | \f | |
58cbf20e DE |
1025 | /* Return true if OP is a register, or is a CONST_INT that can fit in a |
1026 | signed 13 bit immediate field. This is an acceptable SImode operand for | |
1027 | most 3 address instructions. */ | |
ab835497 RK |
1028 | |
1029 | int | |
1030 | arith_operand (op, mode) | |
1031 | rtx op; | |
1032 | enum machine_mode mode; | |
1033 | { | |
11301057 | 1034 | if (register_operand (op, mode)) |
284d86e9 JC |
1035 | return 1; |
1036 | if (GET_CODE (op) != CONST_INT) | |
1037 | return 0; | |
9e0625a3 | 1038 | return SMALL_INT32 (op); |
ab835497 RK |
1039 | } |
1040 | ||
5d6d3339 JJ |
1041 | /* Return true if OP is a constant 4096 */ |
1042 | ||
1043 | int | |
1044 | arith_4096_operand (op, mode) | |
1045 | rtx op; | |
ddf80874 | 1046 | enum machine_mode mode ATTRIBUTE_UNUSED; |
5d6d3339 | 1047 | { |
5d6d3339 JJ |
1048 | if (GET_CODE (op) != CONST_INT) |
1049 | return 0; | |
3070dd00 KG |
1050 | else |
1051 | return INTVAL (op) == 4096; | |
5d6d3339 JJ |
1052 | } |
1053 | ||
1054 | /* Return true if OP is suitable as second operand for add/sub */ | |
1055 | ||
1056 | int | |
1057 | arith_add_operand (op, mode) | |
1058 | rtx op; | |
1059 | enum machine_mode mode; | |
1060 | { | |
1061 | return arith_operand (op, mode) || arith_4096_operand (op, mode); | |
1062 | } | |
1063 | ||
89e65674 DM |
1064 | /* Return true if OP is a CONST_INT or a CONST_DOUBLE which can fit in the |
1065 | immediate field of OR and XOR instructions. Used for 64-bit | |
1066 | constant formation patterns. */ | |
1067 | int | |
1068 | const64_operand (op, mode) | |
1069 | rtx op; | |
ddf80874 | 1070 | enum machine_mode mode ATTRIBUTE_UNUSED; |
89e65674 DM |
1071 | { |
1072 | return ((GET_CODE (op) == CONST_INT | |
1073 | && SPARC_SIMM13_P (INTVAL (op))) | |
9208e4b2 | 1074 | #if HOST_BITS_PER_WIDE_INT != 64 |
89e65674 | 1075 | || (GET_CODE (op) == CONST_DOUBLE |
9208e4b2 DM |
1076 | && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op)) |
1077 | && (CONST_DOUBLE_HIGH (op) == | |
1078 | ((CONST_DOUBLE_LOW (op) & 0x80000000) != 0 ? | |
9e0625a3 | 1079 | (HOST_WIDE_INT)-1 : 0))) |
9208e4b2 | 1080 | #endif |
11301057 | 1081 | ); |
89e65674 DM |
1082 | } |
1083 | ||
9208e4b2 | 1084 | /* The same, but only for sethi instructions. */ |
89e65674 DM |
1085 | int |
1086 | const64_high_operand (op, mode) | |
1087 | rtx op; | |
7d6040e8 | 1088 | enum machine_mode mode; |
89e65674 DM |
1089 | { |
1090 | return ((GET_CODE (op) == CONST_INT | |
9e0625a3 | 1091 | && (INTVAL (op) & ~(HOST_WIDE_INT)0x3ff) != 0 |
7d6040e8 | 1092 | && SPARC_SETHI_P (INTVAL (op) & GET_MODE_MASK (mode)) |
9208e4b2 | 1093 | ) |
89e65674 DM |
1094 | || (GET_CODE (op) == CONST_DOUBLE |
1095 | && CONST_DOUBLE_HIGH (op) == 0 | |
9e0625a3 | 1096 | && (CONST_DOUBLE_LOW (op) & ~(HOST_WIDE_INT)0x3ff) != 0 |
11301057 | 1097 | && SPARC_SETHI_P (CONST_DOUBLE_LOW (op)))); |
89e65674 DM |
1098 | } |
1099 | ||
58cbf20e DE |
1100 | /* Return true if OP is a register, or is a CONST_INT that can fit in a |
1101 | signed 11 bit immediate field. This is an acceptable SImode operand for | |
1102 | the movcc instructions. */ | |
61a55e8b DE |
1103 | |
1104 | int | |
1105 | arith11_operand (op, mode) | |
1106 | rtx op; | |
1107 | enum machine_mode mode; | |
1108 | { | |
1109 | return (register_operand (op, mode) | |
58cbf20e | 1110 | || (GET_CODE (op) == CONST_INT && SPARC_SIMM11_P (INTVAL (op)))); |
61a55e8b DE |
1111 | } |
1112 | ||
58cbf20e DE |
1113 | /* Return true if OP is a register, or is a CONST_INT that can fit in a |
1114 | signed 10 bit immediate field. This is an acceptable SImode operand for | |
1115 | the movrcc instructions. */ | |
61a55e8b DE |
1116 | |
1117 | int | |
1118 | arith10_operand (op, mode) | |
1119 | rtx op; | |
1120 | enum machine_mode mode; | |
1121 | { | |
1122 | return (register_operand (op, mode) | |
58cbf20e | 1123 | || (GET_CODE (op) == CONST_INT && SPARC_SIMM10_P (INTVAL (op)))); |
61a55e8b DE |
1124 | } |
1125 | ||
23b8a89f JW |
1126 | /* Return true if OP is a register, is a CONST_INT that fits in a 13 bit |
1127 | immediate field, or is a CONST_DOUBLE whose both parts fit in a 13 bit | |
61a55e8b DE |
1128 | immediate field. |
1129 | v9: Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that | |
1130 | can fit in a 13 bit immediate field. This is an acceptable DImode operand | |
1131 | for most 3 address instructions. */ | |
ab835497 RK |
1132 | |
1133 | int | |
1134 | arith_double_operand (op, mode) | |
1135 | rtx op; | |
1136 | enum machine_mode mode; | |
1137 | { | |
1138 | return (register_operand (op, mode) | |
23b8a89f | 1139 | || (GET_CODE (op) == CONST_INT && SMALL_INT (op)) |
a9e27770 | 1140 | || (! TARGET_ARCH64 |
61a55e8b | 1141 | && GET_CODE (op) == CONST_DOUBLE |
bf62bbf1 DE |
1142 | && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x1000) < 0x2000 |
1143 | && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_HIGH (op) + 0x1000) < 0x2000) | |
a9e27770 | 1144 | || (TARGET_ARCH64 |
61a55e8b | 1145 | && GET_CODE (op) == CONST_DOUBLE |
bf62bbf1 | 1146 | && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x1000) < 0x2000 |
61a55e8b DE |
1147 | && ((CONST_DOUBLE_HIGH (op) == -1 |
1148 | && (CONST_DOUBLE_LOW (op) & 0x1000) == 0x1000) | |
1149 | || (CONST_DOUBLE_HIGH (op) == 0 | |
1150 | && (CONST_DOUBLE_LOW (op) & 0x1000) == 0)))); | |
1151 | } | |
1152 | ||
5d6d3339 JJ |
1153 | /* Return true if OP is a constant 4096 for DImode on ARCH64 */ |
1154 | ||
1155 | int | |
1156 | arith_double_4096_operand (op, mode) | |
1157 | rtx op; | |
ddf80874 | 1158 | enum machine_mode mode ATTRIBUTE_UNUSED; |
5d6d3339 JJ |
1159 | { |
1160 | return (TARGET_ARCH64 && | |
1161 | ((GET_CODE (op) == CONST_INT && INTVAL (op) == 4096) || | |
1162 | (GET_CODE (op) == CONST_DOUBLE && | |
1163 | CONST_DOUBLE_LOW (op) == 4096 && | |
1164 | CONST_DOUBLE_HIGH (op) == 0))); | |
1165 | } | |
1166 | ||
1167 | /* Return true if OP is suitable as second operand for add/sub in DImode */ | |
1168 | ||
1169 | int | |
1170 | arith_double_add_operand (op, mode) | |
1171 | rtx op; | |
1172 | enum machine_mode mode; | |
1173 | { | |
1174 | return arith_double_operand (op, mode) || arith_double_4096_operand (op, mode); | |
1175 | } | |
1176 | ||
61a55e8b DE |
1177 | /* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that |
1178 | can fit in an 11 bit immediate field. This is an acceptable DImode | |
1179 | operand for the movcc instructions. */ | |
1180 | /* ??? Replace with arith11_operand? */ | |
1181 | ||
1182 | int | |
1183 | arith11_double_operand (op, mode) | |
1184 | rtx op; | |
1185 | enum machine_mode mode; | |
1186 | { | |
1187 | return (register_operand (op, mode) | |
1188 | || (GET_CODE (op) == CONST_DOUBLE | |
1189 | && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode) | |
bf62bbf1 | 1190 | && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x400) < 0x800 |
61a55e8b DE |
1191 | && ((CONST_DOUBLE_HIGH (op) == -1 |
1192 | && (CONST_DOUBLE_LOW (op) & 0x400) == 0x400) | |
1193 | || (CONST_DOUBLE_HIGH (op) == 0 | |
1194 | && (CONST_DOUBLE_LOW (op) & 0x400) == 0))) | |
1195 | || (GET_CODE (op) == CONST_INT | |
1196 | && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode) | |
bf62bbf1 | 1197 | && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x400) < 0x800)); |
61a55e8b DE |
1198 | } |
1199 | ||
1200 | /* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that | |
1201 | can fit in an 10 bit immediate field. This is an acceptable DImode | |
1202 | operand for the movrcc instructions. */ | |
1203 | /* ??? Replace with arith10_operand? */ | |
1204 | ||
1205 | int | |
1206 | arith10_double_operand (op, mode) | |
1207 | rtx op; | |
1208 | enum machine_mode mode; | |
1209 | { | |
1210 | return (register_operand (op, mode) | |
1211 | || (GET_CODE (op) == CONST_DOUBLE | |
1212 | && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode) | |
1213 | && (unsigned) (CONST_DOUBLE_LOW (op) + 0x200) < 0x400 | |
1214 | && ((CONST_DOUBLE_HIGH (op) == -1 | |
1215 | && (CONST_DOUBLE_LOW (op) & 0x200) == 0x200) | |
1216 | || (CONST_DOUBLE_HIGH (op) == 0 | |
1217 | && (CONST_DOUBLE_LOW (op) & 0x200) == 0))) | |
1218 | || (GET_CODE (op) == CONST_INT | |
1219 | && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode) | |
bf62bbf1 | 1220 | && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x200) < 0x400)); |
ab835497 RK |
1221 | } |
1222 | ||
5519a4f9 | 1223 | /* Return truth value of whether OP is an integer which fits the |
228b4037 JW |
1224 | range constraining immediate operands in most three-address insns, |
1225 | which have a 13 bit immediate field. */ | |
ab835497 RK |
1226 | |
1227 | int | |
1228 | small_int (op, mode) | |
1229 | rtx op; | |
487a6e06 | 1230 | enum machine_mode mode ATTRIBUTE_UNUSED; |
ab835497 | 1231 | { |
11301057 | 1232 | return (GET_CODE (op) == CONST_INT && SMALL_INT (op)); |
ab835497 RK |
1233 | } |
1234 | ||
e0d80184 DM |
1235 | int |
1236 | small_int_or_double (op, mode) | |
1237 | rtx op; | |
1238 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
1239 | { | |
1240 | return ((GET_CODE (op) == CONST_INT && SMALL_INT (op)) | |
1241 | || (GET_CODE (op) == CONST_DOUBLE | |
1242 | && CONST_DOUBLE_HIGH (op) == 0 | |
11301057 | 1243 | && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op)))); |
e0d80184 DM |
1244 | } |
1245 | ||
9b3fad96 JW |
1246 | /* Recognize operand values for the umul instruction. That instruction sign |
1247 | extends immediate values just like all other sparc instructions, but | |
1248 | interprets the extended result as an unsigned number. */ | |
1249 | ||
1250 | int | |
1251 | uns_small_int (op, mode) | |
1252 | rtx op; | |
487a6e06 | 1253 | enum machine_mode mode ATTRIBUTE_UNUSED; |
9b3fad96 JW |
1254 | { |
1255 | #if HOST_BITS_PER_WIDE_INT > 32 | |
1256 | /* All allowed constants will fit a CONST_INT. */ | |
11301057 RH |
1257 | return (GET_CODE (op) == CONST_INT |
1258 | && ((INTVAL (op) >= 0 && INTVAL (op) < 0x1000) | |
1259 | || (INTVAL (op) >= 0xFFFFF000 | |
0d587737 | 1260 | && INTVAL (op) <= 0xFFFFFFFF))); |
9b3fad96 | 1261 | #else |
11301057 RH |
1262 | return ((GET_CODE (op) == CONST_INT && (unsigned) INTVAL (op) < 0x1000) |
1263 | || (GET_CODE (op) == CONST_DOUBLE | |
1264 | && CONST_DOUBLE_HIGH (op) == 0 | |
1265 | && (unsigned) CONST_DOUBLE_LOW (op) - 0xFFFFF000 < 0x1000)); | |
9b3fad96 JW |
1266 | #endif |
1267 | } | |
1268 | ||
1269 | int | |
1270 | uns_arith_operand (op, mode) | |
1271 | rtx op; | |
1272 | enum machine_mode mode; | |
1273 | { | |
1274 | return register_operand (op, mode) || uns_small_int (op, mode); | |
1275 | } | |
1276 | ||
ab835497 RK |
1277 | /* Return truth value of statement that OP is a call-clobbered register. */ |
1278 | int | |
1279 | clobbered_register (op, mode) | |
1280 | rtx op; | |
487a6e06 | 1281 | enum machine_mode mode ATTRIBUTE_UNUSED; |
ab835497 RK |
1282 | { |
1283 | return (GET_CODE (op) == REG && call_used_regs[REGNO (op)]); | |
1284 | } | |
ab835497 | 1285 | |
e0d80184 | 1286 | /* Return 1 if OP is a valid operand for the source of a move insn. */ |
61a55e8b | 1287 | |
e0d80184 DM |
1288 | int |
1289 | input_operand (op, mode) | |
1290 | rtx op; | |
1291 | enum machine_mode mode; | |
1292 | { | |
1293 | /* If both modes are non-void they must be the same. */ | |
1294 | if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op)) | |
1295 | return 0; | |
61a55e8b | 1296 | |
375ffbe6 EB |
1297 | /* Accept CONSTANT_P_RTX, since it will be gone by CSE1 and result in 0/1. */ |
1298 | if (GET_CODE (op) == CONSTANT_P_RTX) | |
11301057 RH |
1299 | return 1; |
1300 | ||
e0d80184 DM |
1301 | /* Allow any one instruction integer constant, and all CONST_INT |
1302 | variants when we are working in DImode and !arch64. */ | |
1303 | if (GET_MODE_CLASS (mode) == MODE_INT | |
9208e4b2 | 1304 | && ((GET_CODE (op) == CONST_INT |
7d6040e8 | 1305 | && (SPARC_SETHI_P (INTVAL (op) & GET_MODE_MASK (mode)) |
9208e4b2 DM |
1306 | || SPARC_SIMM13_P (INTVAL (op)) |
1307 | || (mode == DImode | |
1308 | && ! TARGET_ARCH64))) | |
1309 | || (TARGET_ARCH64 | |
1310 | && GET_CODE (op) == CONST_DOUBLE | |
1311 | && ((CONST_DOUBLE_HIGH (op) == 0 | |
1312 | && SPARC_SETHI_P (CONST_DOUBLE_LOW (op))) | |
1313 | || | |
1314 | #if HOST_BITS_PER_WIDE_INT == 64 | |
1315 | (CONST_DOUBLE_HIGH (op) == 0 | |
1316 | && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op))) | |
1317 | #else | |
1318 | (SPARC_SIMM13_P (CONST_DOUBLE_LOW (op)) | |
1319 | && (((CONST_DOUBLE_LOW (op) & 0x80000000) == 0 | |
1320 | && CONST_DOUBLE_HIGH (op) == 0) | |
4746e0fe RK |
1321 | || (CONST_DOUBLE_HIGH (op) == -1 |
1322 | && CONST_DOUBLE_LOW (op) & 0x80000000) != 0)) | |
9208e4b2 DM |
1323 | #endif |
1324 | )))) | |
e0d80184 DM |
1325 | return 1; |
1326 | ||
e0d80184 DM |
1327 | /* If !arch64 and this is a DImode const, allow it so that |
1328 | the splits can be generated. */ | |
1329 | if (! TARGET_ARCH64 | |
1330 | && mode == DImode | |
1331 | && GET_CODE (op) == CONST_DOUBLE) | |
1332 | return 1; | |
1333 | ||
1334 | if (register_operand (op, mode)) | |
1335 | return 1; | |
1336 | ||
62190128 DM |
1337 | if (GET_MODE_CLASS (mode) == MODE_FLOAT |
1338 | && GET_CODE (op) == CONST_DOUBLE) | |
1339 | return 1; | |
1340 | ||
e0d80184 DM |
1341 | /* If this is a SUBREG, look inside so that we handle |
1342 | paradoxical ones. */ | |
1343 | if (GET_CODE (op) == SUBREG) | |
1344 | op = SUBREG_REG (op); | |
1345 | ||
1346 | /* Check for valid MEM forms. */ | |
1347 | if (GET_CODE (op) == MEM) | |
61a55e8b | 1348 | { |
e0d80184 | 1349 | rtx inside = XEXP (op, 0); |
61a55e8b | 1350 | |
e0d80184 | 1351 | if (GET_CODE (inside) == LO_SUM) |
03ad6f4d DM |
1352 | { |
1353 | /* We can't allow these because all of the splits | |
1354 | (eventually as they trickle down into DFmode | |
1355 | splits) require offsettable memory references. */ | |
1356 | if (! TARGET_V9 | |
1357 | && GET_MODE (op) == TFmode) | |
1358 | return 0; | |
1359 | ||
1360 | return (register_operand (XEXP (inside, 0), Pmode) | |
1361 | && CONSTANT_P (XEXP (inside, 1))); | |
1362 | } | |
e0d80184 | 1363 | return memory_address_p (mode, inside); |
61a55e8b | 1364 | } |
ab835497 | 1365 | |
e0d80184 DM |
1366 | return 0; |
1367 | } | |
1368 | ||
1369 | \f | |
1370 | /* We know it can't be done in one insn when we get here, | |
1371 | the movsi expander guarentees this. */ | |
1372 | void | |
1373 | sparc_emit_set_const32 (op0, op1) | |
1374 | rtx op0; | |
1375 | rtx op1; | |
1376 | { | |
1377 | enum machine_mode mode = GET_MODE (op0); | |
1378 | rtx temp; | |
1379 | ||
1380 | if (GET_CODE (op1) == CONST_INT) | |
284d86e9 | 1381 | { |
2a01c939 | 1382 | HOST_WIDE_INT value = INTVAL (op1); |
e0d80184 | 1383 | |
7d6040e8 | 1384 | if (SPARC_SETHI_P (value & GET_MODE_MASK (mode)) |
e0d80184 DM |
1385 | || SPARC_SIMM13_P (value)) |
1386 | abort (); | |
284d86e9 | 1387 | } |
e0d80184 DM |
1388 | |
1389 | /* Full 2-insn decomposition is needed. */ | |
1390 | if (reload_in_progress || reload_completed) | |
1391 | temp = op0; | |
284d86e9 | 1392 | else |
e0d80184 DM |
1393 | temp = gen_reg_rtx (mode); |
1394 | ||
71648202 DM |
1395 | if (GET_CODE (op1) == CONST_INT) |
1396 | { | |
1397 | /* Emit them as real moves instead of a HIGH/LO_SUM, | |
1398 | this way CSE can see everything and reuse intermediate | |
1399 | values if it wants. */ | |
1400 | if (TARGET_ARCH64 | |
1401 | && HOST_BITS_PER_WIDE_INT != 64 | |
1402 | && (INTVAL (op1) & 0x80000000) != 0) | |
f2827474 RK |
1403 | emit_insn (gen_rtx_SET |
1404 | (VOIDmode, temp, | |
5692c7bc ZW |
1405 | immed_double_const (INTVAL (op1) & ~(HOST_WIDE_INT)0x3ff, |
1406 | 0, DImode))); | |
71648202 | 1407 | else |
f2827474 | 1408 | emit_insn (gen_rtx_SET (VOIDmode, temp, |
9e0625a3 AO |
1409 | GEN_INT (INTVAL (op1) |
1410 | & ~(HOST_WIDE_INT)0x3ff))); | |
f2827474 | 1411 | |
71648202 DM |
1412 | emit_insn (gen_rtx_SET (VOIDmode, |
1413 | op0, | |
f2827474 | 1414 | gen_rtx_IOR (mode, temp, |
71648202 DM |
1415 | GEN_INT (INTVAL (op1) & 0x3ff)))); |
1416 | } | |
1417 | else | |
1418 | { | |
1419 | /* A symbol, emit in the traditional way. */ | |
f2827474 RK |
1420 | emit_insn (gen_rtx_SET (VOIDmode, temp, |
1421 | gen_rtx_HIGH (mode, op1))); | |
71648202 | 1422 | emit_insn (gen_rtx_SET (VOIDmode, |
f2827474 | 1423 | op0, gen_rtx_LO_SUM (mode, temp, op1))); |
71648202 DM |
1424 | |
1425 | } | |
e0d80184 DM |
1426 | } |
1427 | ||
1428 | \f | |
56149abc | 1429 | /* SPARC-v9 code-model support. */ |
e0d80184 DM |
1430 | void |
1431 | sparc_emit_set_symbolic_const64 (op0, op1, temp1) | |
1432 | rtx op0; | |
1433 | rtx op1; | |
1434 | rtx temp1; | |
1435 | { | |
3968de80 DD |
1436 | rtx ti_temp1 = 0; |
1437 | ||
1438 | if (temp1 && GET_MODE (temp1) == TImode) | |
1439 | { | |
1440 | ti_temp1 = temp1; | |
1441 | temp1 = gen_rtx_REG (DImode, REGNO (temp1)); | |
1442 | } | |
1443 | ||
e0d80184 | 1444 | switch (sparc_cmodel) |
284d86e9 | 1445 | { |
e0d80184 DM |
1446 | case CM_MEDLOW: |
1447 | /* The range spanned by all instructions in the object is less | |
1448 | than 2^31 bytes (2GB) and the distance from any instruction | |
1449 | to the location of the label _GLOBAL_OFFSET_TABLE_ is less | |
1450 | than 2^31 bytes (2GB). | |
ab835497 | 1451 | |
e0d80184 DM |
1452 | The executable must be in the low 4TB of the virtual address |
1453 | space. | |
61a55e8b | 1454 | |
e0d80184 DM |
1455 | sethi %hi(symbol), %temp |
1456 | or %temp, %lo(symbol), %reg */ | |
9208e4b2 DM |
1457 | emit_insn (gen_rtx_SET (VOIDmode, temp1, gen_rtx_HIGH (DImode, op1))); |
1458 | emit_insn (gen_rtx_SET (VOIDmode, op0, gen_rtx_LO_SUM (DImode, temp1, op1))); | |
e0d80184 | 1459 | break; |
61a55e8b | 1460 | |
e0d80184 DM |
1461 | case CM_MEDMID: |
1462 | /* The range spanned by all instructions in the object is less | |
1463 | than 2^31 bytes (2GB) and the distance from any instruction | |
1464 | to the location of the label _GLOBAL_OFFSET_TABLE_ is less | |
1465 | than 2^31 bytes (2GB). | |
1466 | ||
1467 | The executable must be in the low 16TB of the virtual address | |
1468 | space. | |
1469 | ||
1470 | sethi %h44(symbol), %temp1 | |
1471 | or %temp1, %m44(symbol), %temp2 | |
1472 | sllx %temp2, 12, %temp3 | |
1473 | or %temp3, %l44(symbol), %reg */ | |
1474 | emit_insn (gen_seth44 (op0, op1)); | |
1475 | emit_insn (gen_setm44 (op0, op0, op1)); | |
9208e4b2 | 1476 | emit_insn (gen_rtx_SET (VOIDmode, temp1, |
e0d80184 DM |
1477 | gen_rtx_ASHIFT (DImode, op0, GEN_INT (12)))); |
1478 | emit_insn (gen_setl44 (op0, temp1, op1)); | |
1479 | break; | |
61a55e8b | 1480 | |
e0d80184 DM |
1481 | case CM_MEDANY: |
1482 | /* The range spanned by all instructions in the object is less | |
1483 | than 2^31 bytes (2GB) and the distance from any instruction | |
1484 | to the location of the label _GLOBAL_OFFSET_TABLE_ is less | |
1485 | than 2^31 bytes (2GB). | |
1486 | ||
1487 | The executable can be placed anywhere in the virtual address | |
1488 | space. | |
1489 | ||
1490 | sethi %hh(symbol), %temp1 | |
1491 | sethi %lm(symbol), %temp2 | |
1492 | or %temp1, %hm(symbol), %temp3 | |
1493 | or %temp2, %lo(symbol), %temp4 | |
1494 | sllx %temp3, 32, %temp5 | |
1495 | or %temp4, %temp5, %reg */ | |
1496 | ||
3968de80 DD |
1497 | /* It is possible that one of the registers we got for operands[2] |
1498 | might coincide with that of operands[0] (which is why we made | |
1499 | it TImode). Pick the other one to use as our scratch. */ | |
6cd444b4 | 1500 | if (rtx_equal_p (temp1, op0)) |
3968de80 DD |
1501 | { |
1502 | if (ti_temp1) | |
1503 | temp1 = gen_rtx_REG (DImode, REGNO (temp1) + 1); | |
1504 | else | |
1505 | abort(); | |
1506 | } | |
61a55e8b | 1507 | |
e0d80184 DM |
1508 | emit_insn (gen_sethh (op0, op1)); |
1509 | emit_insn (gen_setlm (temp1, op1)); | |
1510 | emit_insn (gen_sethm (op0, op0, op1)); | |
9208e4b2 | 1511 | emit_insn (gen_rtx_SET (VOIDmode, op0, |
e0d80184 | 1512 | gen_rtx_ASHIFT (DImode, op0, GEN_INT (32)))); |
9208e4b2 | 1513 | emit_insn (gen_rtx_SET (VOIDmode, op0, |
e0d80184 DM |
1514 | gen_rtx_PLUS (DImode, op0, temp1))); |
1515 | emit_insn (gen_setlo (op0, op0, op1)); | |
1516 | break; | |
61a55e8b | 1517 | |
e0d80184 DM |
1518 | case CM_EMBMEDANY: |
1519 | /* Old old old backwards compatibility kruft here. | |
1520 | Essentially it is MEDLOW with a fixed 64-bit | |
1521 | virtual base added to all data segment addresses. | |
1522 | Text-segment stuff is computed like MEDANY, we can't | |
1523 | reuse the code above because the relocation knobs | |
1524 | look different. | |
1525 | ||
1526 | Data segment: sethi %hi(symbol), %temp1 | |
1527 | or %temp1, %lo(symbol), %temp2 | |
1528 | add %temp2, EMBMEDANY_BASE_REG, %reg | |
1529 | ||
1530 | Text segment: sethi %uhi(symbol), %temp1 | |
1531 | sethi %hi(symbol), %temp2 | |
1532 | or %temp1, %ulo(symbol), %temp3 | |
1533 | or %temp2, %lo(symbol), %temp4 | |
1534 | sllx %temp3, 32, %temp5 | |
1535 | or %temp4, %temp5, %reg */ | |
1536 | if (data_segment_operand (op1, GET_MODE (op1))) | |
1537 | { | |
1538 | emit_insn (gen_embmedany_sethi (temp1, op1)); | |
1539 | emit_insn (gen_embmedany_brsum (op0, temp1)); | |
1540 | emit_insn (gen_embmedany_losum (op0, op0, op1)); | |
1541 | } | |
1542 | else | |
1543 | { | |
3968de80 DD |
1544 | /* It is possible that one of the registers we got for operands[2] |
1545 | might coincide with that of operands[0] (which is why we made | |
1546 | it TImode). Pick the other one to use as our scratch. */ | |
1547 | if (rtx_equal_p (temp1, op0)) | |
1548 | { | |
1549 | if (ti_temp1) | |
1550 | temp1 = gen_rtx_REG (DImode, REGNO (temp1) + 1); | |
1551 | else | |
1552 | abort(); | |
1553 | } | |
61a55e8b | 1554 | |
e0d80184 DM |
1555 | emit_insn (gen_embmedany_textuhi (op0, op1)); |
1556 | emit_insn (gen_embmedany_texthi (temp1, op1)); | |
1557 | emit_insn (gen_embmedany_textulo (op0, op0, op1)); | |
9208e4b2 | 1558 | emit_insn (gen_rtx_SET (VOIDmode, op0, |
e0d80184 | 1559 | gen_rtx_ASHIFT (DImode, op0, GEN_INT (32)))); |
9208e4b2 | 1560 | emit_insn (gen_rtx_SET (VOIDmode, op0, |
e0d80184 DM |
1561 | gen_rtx_PLUS (DImode, op0, temp1))); |
1562 | emit_insn (gen_embmedany_textlo (op0, op0, op1)); | |
1563 | } | |
1564 | break; | |
1565 | ||
1566 | default: | |
1567 | abort(); | |
1568 | } | |
1569 | } | |
1570 | ||
9208e4b2 DM |
1571 | /* These avoid problems when cross compiling. If we do not |
1572 | go through all this hair then the optimizer will see | |
1573 | invalid REG_EQUAL notes or in some cases none at all. */ | |
f6da8bc3 KG |
1574 | static void sparc_emit_set_safe_HIGH64 PARAMS ((rtx, HOST_WIDE_INT)); |
1575 | static rtx gen_safe_SET64 PARAMS ((rtx, HOST_WIDE_INT)); | |
1576 | static rtx gen_safe_OR64 PARAMS ((rtx, HOST_WIDE_INT)); | |
1577 | static rtx gen_safe_XOR64 PARAMS ((rtx, HOST_WIDE_INT)); | |
9208e4b2 DM |
1578 | |
1579 | #if HOST_BITS_PER_WIDE_INT == 64 | |
9e0625a3 | 1580 | #define GEN_HIGHINT64(__x) GEN_INT ((__x) & ~(HOST_WIDE_INT)0x3ff) |
9208e4b2 DM |
1581 | #define GEN_INT64(__x) GEN_INT (__x) |
1582 | #else | |
1583 | #define GEN_HIGHINT64(__x) \ | |
5692c7bc | 1584 | immed_double_const ((__x) & ~(HOST_WIDE_INT)0x3ff, 0, DImode) |
9208e4b2 | 1585 | #define GEN_INT64(__x) \ |
5692c7bc ZW |
1586 | immed_double_const ((__x) & 0xffffffff, \ |
1587 | ((__x) & 0x80000000 ? -1 : 0), DImode) | |
9208e4b2 DM |
1588 | #endif |
1589 | ||
1590 | /* The optimizer is not to assume anything about exactly | |
1591 | which bits are set for a HIGH, they are unspecified. | |
1592 | Unfortunately this leads to many missed optimizations | |
1593 | during CSE. We mask out the non-HIGH bits, and matches | |
1594 | a plain movdi, to alleviate this problem. */ | |
1595 | static void | |
1596 | sparc_emit_set_safe_HIGH64 (dest, val) | |
1597 | rtx dest; | |
1598 | HOST_WIDE_INT val; | |
1599 | { | |
1600 | emit_insn (gen_rtx_SET (VOIDmode, dest, GEN_HIGHINT64 (val))); | |
1601 | } | |
2a01c939 | 1602 | |
e0d80184 | 1603 | static rtx |
9208e4b2 DM |
1604 | gen_safe_SET64 (dest, val) |
1605 | rtx dest; | |
e0d80184 | 1606 | HOST_WIDE_INT val; |
61a55e8b | 1607 | { |
9208e4b2 DM |
1608 | return gen_rtx_SET (VOIDmode, dest, GEN_INT64 (val)); |
1609 | } | |
1610 | ||
1611 | static rtx | |
1612 | gen_safe_OR64 (src, val) | |
1613 | rtx src; | |
1614 | HOST_WIDE_INT val; | |
1615 | { | |
1616 | return gen_rtx_IOR (DImode, src, GEN_INT64 (val)); | |
1617 | } | |
1618 | ||
1619 | static rtx | |
1620 | gen_safe_XOR64 (src, val) | |
1621 | rtx src; | |
1622 | HOST_WIDE_INT val; | |
1623 | { | |
1624 | return gen_rtx_XOR (DImode, src, GEN_INT64 (val)); | |
e0d80184 | 1625 | } |
61a55e8b | 1626 | |
e0d80184 DM |
1627 | /* Worker routines for 64-bit constant formation on arch64. |
1628 | One of the key things to be doing in these emissions is | |
1629 | to create as many temp REGs as possible. This makes it | |
1630 | possible for half-built constants to be used later when | |
1631 | such values are similar to something required later on. | |
1632 | Without doing this, the optimizer cannot see such | |
1633 | opportunities. */ | |
2a01c939 DM |
1634 | |
1635 | static void sparc_emit_set_const64_quick1 | |
f6da8bc3 | 1636 | PARAMS ((rtx, rtx, unsigned HOST_WIDE_INT, int)); |
2a01c939 | 1637 | |
e0d80184 DM |
1638 | static void |
1639 | sparc_emit_set_const64_quick1 (op0, temp, low_bits, is_neg) | |
1640 | rtx op0; | |
1641 | rtx temp; | |
2a01c939 | 1642 | unsigned HOST_WIDE_INT low_bits; |
e0d80184 DM |
1643 | int is_neg; |
1644 | { | |
2a01c939 | 1645 | unsigned HOST_WIDE_INT high_bits; |
a9e27770 | 1646 | |
e0d80184 | 1647 | if (is_neg) |
2a01c939 | 1648 | high_bits = (~low_bits) & 0xffffffff; |
31bc9eba | 1649 | else |
e0d80184 | 1650 | high_bits = low_bits; |
31bc9eba | 1651 | |
9208e4b2 | 1652 | sparc_emit_set_safe_HIGH64 (temp, high_bits); |
e0d80184 | 1653 | if (!is_neg) |
5108f3e5 DM |
1654 | { |
1655 | emit_insn (gen_rtx_SET (VOIDmode, op0, | |
1656 | gen_safe_OR64 (temp, (high_bits & 0x3ff)))); | |
1657 | } | |
e0d80184 | 1658 | else |
5108f3e5 DM |
1659 | { |
1660 | /* If we are XOR'ing with -1, then we should emit a one's complement | |
1661 | instead. This way the combiner will notice logical operations | |
1662 | such as ANDN later on and substitute. */ | |
1663 | if ((low_bits & 0x3ff) == 0x3ff) | |
1664 | { | |
1665 | emit_insn (gen_rtx_SET (VOIDmode, op0, | |
1666 | gen_rtx_NOT (DImode, temp))); | |
1667 | } | |
1668 | else | |
1669 | { | |
1670 | emit_insn (gen_rtx_SET (VOIDmode, op0, | |
1671 | gen_safe_XOR64 (temp, | |
9e0625a3 AO |
1672 | (-(HOST_WIDE_INT)0x400 |
1673 | | (low_bits & 0x3ff))))); | |
5108f3e5 DM |
1674 | } |
1675 | } | |
e0d80184 | 1676 | } |
61a55e8b | 1677 | |
2a01c939 | 1678 | static void sparc_emit_set_const64_quick2 |
f6da8bc3 | 1679 | PARAMS ((rtx, rtx, unsigned HOST_WIDE_INT, |
2a01c939 DM |
1680 | unsigned HOST_WIDE_INT, int)); |
1681 | ||
e0d80184 DM |
1682 | static void |
1683 | sparc_emit_set_const64_quick2 (op0, temp, high_bits, low_immediate, shift_count) | |
1684 | rtx op0; | |
1685 | rtx temp; | |
2a01c939 DM |
1686 | unsigned HOST_WIDE_INT high_bits; |
1687 | unsigned HOST_WIDE_INT low_immediate; | |
e0d80184 DM |
1688 | int shift_count; |
1689 | { | |
1690 | rtx temp2 = op0; | |
61a55e8b | 1691 | |
e0d80184 DM |
1692 | if ((high_bits & 0xfffffc00) != 0) |
1693 | { | |
9208e4b2 | 1694 | sparc_emit_set_safe_HIGH64 (temp, high_bits); |
e0d80184 | 1695 | if ((high_bits & ~0xfffffc00) != 0) |
9208e4b2 DM |
1696 | emit_insn (gen_rtx_SET (VOIDmode, op0, |
1697 | gen_safe_OR64 (temp, (high_bits & 0x3ff)))); | |
61a55e8b | 1698 | else |
e0d80184 | 1699 | temp2 = temp; |
61a55e8b DE |
1700 | } |
1701 | else | |
1702 | { | |
f710f868 | 1703 | emit_insn (gen_safe_SET64 (temp, high_bits)); |
e0d80184 DM |
1704 | temp2 = temp; |
1705 | } | |
61a55e8b | 1706 | |
80ffc95e | 1707 | /* Now shift it up into place. */ |
9208e4b2 | 1708 | emit_insn (gen_rtx_SET (VOIDmode, op0, |
e0d80184 DM |
1709 | gen_rtx_ASHIFT (DImode, temp2, |
1710 | GEN_INT (shift_count)))); | |
61a55e8b | 1711 | |
e0d80184 DM |
1712 | /* If there is a low immediate part piece, finish up by |
1713 | putting that in as well. */ | |
1714 | if (low_immediate != 0) | |
9208e4b2 DM |
1715 | emit_insn (gen_rtx_SET (VOIDmode, op0, |
1716 | gen_safe_OR64 (op0, low_immediate))); | |
ab835497 RK |
1717 | } |
1718 | ||
2a01c939 | 1719 | static void sparc_emit_set_const64_longway |
f6da8bc3 | 1720 | PARAMS ((rtx, rtx, unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT)); |
2a01c939 | 1721 | |
e0d80184 DM |
1722 | /* Full 64-bit constant decomposition. Even though this is the |
1723 | 'worst' case, we still optimize a few things away. */ | |
1724 | static void | |
1725 | sparc_emit_set_const64_longway (op0, temp, high_bits, low_bits) | |
1726 | rtx op0; | |
1727 | rtx temp; | |
2a01c939 DM |
1728 | unsigned HOST_WIDE_INT high_bits; |
1729 | unsigned HOST_WIDE_INT low_bits; | |
ab835497 | 1730 | { |
e0d80184 | 1731 | rtx sub_temp; |
4bf7135b | 1732 | |
e0d80184 DM |
1733 | if (reload_in_progress || reload_completed) |
1734 | sub_temp = op0; | |
1735 | else | |
1736 | sub_temp = gen_reg_rtx (DImode); | |
1737 | ||
1738 | if ((high_bits & 0xfffffc00) != 0) | |
1739 | { | |
9208e4b2 | 1740 | sparc_emit_set_safe_HIGH64 (temp, high_bits); |
e0d80184 | 1741 | if ((high_bits & ~0xfffffc00) != 0) |
9208e4b2 | 1742 | emit_insn (gen_rtx_SET (VOIDmode, |
e0d80184 | 1743 | sub_temp, |
9208e4b2 | 1744 | gen_safe_OR64 (temp, (high_bits & 0x3ff)))); |
e0d80184 DM |
1745 | else |
1746 | sub_temp = temp; | |
1747 | } | |
1748 | else | |
ab835497 | 1749 | { |
f710f868 | 1750 | emit_insn (gen_safe_SET64 (temp, high_bits)); |
e0d80184 | 1751 | sub_temp = temp; |
ab835497 | 1752 | } |
4bf7135b | 1753 | |
e0d80184 | 1754 | if (!reload_in_progress && !reload_completed) |
284d86e9 | 1755 | { |
e0d80184 DM |
1756 | rtx temp2 = gen_reg_rtx (DImode); |
1757 | rtx temp3 = gen_reg_rtx (DImode); | |
1758 | rtx temp4 = gen_reg_rtx (DImode); | |
284d86e9 | 1759 | |
9208e4b2 | 1760 | emit_insn (gen_rtx_SET (VOIDmode, temp4, |
e0d80184 DM |
1761 | gen_rtx_ASHIFT (DImode, sub_temp, |
1762 | GEN_INT (32)))); | |
4bf7135b | 1763 | |
9208e4b2 | 1764 | sparc_emit_set_safe_HIGH64 (temp2, low_bits); |
e0d80184 | 1765 | if ((low_bits & ~0xfffffc00) != 0) |
f710f868 DM |
1766 | { |
1767 | emit_insn (gen_rtx_SET (VOIDmode, temp3, | |
1768 | gen_safe_OR64 (temp2, (low_bits & 0x3ff)))); | |
1769 | emit_insn (gen_rtx_SET (VOIDmode, op0, | |
1770 | gen_rtx_PLUS (DImode, temp4, temp3))); | |
1771 | } | |
1772 | else | |
1773 | { | |
1774 | emit_insn (gen_rtx_SET (VOIDmode, op0, | |
1775 | gen_rtx_PLUS (DImode, temp4, temp2))); | |
1776 | } | |
284d86e9 | 1777 | } |
e0d80184 DM |
1778 | else |
1779 | { | |
9208e4b2 DM |
1780 | rtx low1 = GEN_INT ((low_bits >> (32 - 12)) & 0xfff); |
1781 | rtx low2 = GEN_INT ((low_bits >> (32 - 12 - 12)) & 0xfff); | |
1782 | rtx low3 = GEN_INT ((low_bits >> (32 - 12 - 12 - 8)) & 0x0ff); | |
e0d80184 | 1783 | int to_shift = 12; |
284d86e9 | 1784 | |
e0d80184 DM |
1785 | /* We are in the middle of reload, so this is really |
1786 | painful. However we do still make an attempt to | |
5108f3e5 | 1787 | avoid emitting truly stupid code. */ |
e0d80184 DM |
1788 | if (low1 != const0_rtx) |
1789 | { | |
9208e4b2 | 1790 | emit_insn (gen_rtx_SET (VOIDmode, op0, |
e0d80184 | 1791 | gen_rtx_ASHIFT (DImode, sub_temp, |
2a01c939 | 1792 | GEN_INT (to_shift)))); |
9208e4b2 | 1793 | emit_insn (gen_rtx_SET (VOIDmode, op0, |
e0d80184 DM |
1794 | gen_rtx_IOR (DImode, op0, low1))); |
1795 | sub_temp = op0; | |
1796 | to_shift = 12; | |
1797 | } | |
1798 | else | |
1799 | { | |
1800 | to_shift += 12; | |
1801 | } | |
1802 | if (low2 != const0_rtx) | |
1803 | { | |
9208e4b2 | 1804 | emit_insn (gen_rtx_SET (VOIDmode, op0, |
e0d80184 DM |
1805 | gen_rtx_ASHIFT (DImode, sub_temp, |
1806 | GEN_INT (to_shift)))); | |
9208e4b2 | 1807 | emit_insn (gen_rtx_SET (VOIDmode, op0, |
e0d80184 DM |
1808 | gen_rtx_IOR (DImode, op0, low2))); |
1809 | sub_temp = op0; | |
1810 | to_shift = 8; | |
1811 | } | |
1812 | else | |
1813 | { | |
1814 | to_shift += 8; | |
1815 | } | |
9208e4b2 | 1816 | emit_insn (gen_rtx_SET (VOIDmode, op0, |
e0d80184 DM |
1817 | gen_rtx_ASHIFT (DImode, sub_temp, |
1818 | GEN_INT (to_shift)))); | |
1819 | if (low3 != const0_rtx) | |
9208e4b2 | 1820 | emit_insn (gen_rtx_SET (VOIDmode, op0, |
e0d80184 | 1821 | gen_rtx_IOR (DImode, op0, low3))); |
80ffc95e | 1822 | /* phew... */ |
e0d80184 | 1823 | } |
284d86e9 JC |
1824 | } |
1825 | ||
80ffc95e | 1826 | /* Analyze a 64-bit constant for certain properties. */ |
2a01c939 | 1827 | static void analyze_64bit_constant |
f6da8bc3 | 1828 | PARAMS ((unsigned HOST_WIDE_INT, |
2a01c939 DM |
1829 | unsigned HOST_WIDE_INT, |
1830 | int *, int *, int *)); | |
1831 | ||
e0d80184 DM |
1832 | static void |
1833 | analyze_64bit_constant (high_bits, low_bits, hbsp, lbsp, abbasp) | |
2a01c939 | 1834 | unsigned HOST_WIDE_INT high_bits, low_bits; |
e0d80184 | 1835 | int *hbsp, *lbsp, *abbasp; |
ab835497 | 1836 | { |
e0d80184 DM |
1837 | int lowest_bit_set, highest_bit_set, all_bits_between_are_set; |
1838 | int i; | |
ab835497 | 1839 | |
e0d80184 DM |
1840 | lowest_bit_set = highest_bit_set = -1; |
1841 | i = 0; | |
1842 | do | |
ab835497 | 1843 | { |
e0d80184 DM |
1844 | if ((lowest_bit_set == -1) |
1845 | && ((low_bits >> i) & 1)) | |
1846 | lowest_bit_set = i; | |
1847 | if ((highest_bit_set == -1) | |
1848 | && ((high_bits >> (32 - i - 1)) & 1)) | |
1849 | highest_bit_set = (64 - i - 1); | |
1850 | } | |
1851 | while (++i < 32 | |
1852 | && ((highest_bit_set == -1) | |
1853 | || (lowest_bit_set == -1))); | |
1854 | if (i == 32) | |
1855 | { | |
1856 | i = 0; | |
1857 | do | |
ab835497 | 1858 | { |
e0d80184 DM |
1859 | if ((lowest_bit_set == -1) |
1860 | && ((high_bits >> i) & 1)) | |
1861 | lowest_bit_set = i + 32; | |
1862 | if ((highest_bit_set == -1) | |
1863 | && ((low_bits >> (32 - i - 1)) & 1)) | |
1864 | highest_bit_set = 32 - i - 1; | |
ab835497 | 1865 | } |
e0d80184 DM |
1866 | while (++i < 32 |
1867 | && ((highest_bit_set == -1) | |
1868 | || (lowest_bit_set == -1))); | |
1869 | } | |
1870 | /* If there are no bits set this should have gone out | |
1871 | as one instruction! */ | |
1872 | if (lowest_bit_set == -1 | |
1873 | || highest_bit_set == -1) | |
9208e4b2 | 1874 | abort (); |
e0d80184 DM |
1875 | all_bits_between_are_set = 1; |
1876 | for (i = lowest_bit_set; i <= highest_bit_set; i++) | |
1877 | { | |
1878 | if (i < 32) | |
1879 | { | |
1880 | if ((low_bits & (1 << i)) != 0) | |
1881 | continue; | |
1882 | } | |
1883 | else | |
1884 | { | |
1885 | if ((high_bits & (1 << (i - 32))) != 0) | |
1886 | continue; | |
1887 | } | |
1888 | all_bits_between_are_set = 0; | |
1889 | break; | |
ab835497 | 1890 | } |
e0d80184 DM |
1891 | *hbsp = highest_bit_set; |
1892 | *lbsp = lowest_bit_set; | |
1893 | *abbasp = all_bits_between_are_set; | |
ab835497 | 1894 | } |
6a4bb1fa | 1895 | |
2a01c939 | 1896 | static int const64_is_2insns |
f6da8bc3 | 1897 | PARAMS ((unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT)); |
2a01c939 | 1898 | |
e0d80184 DM |
1899 | static int |
1900 | const64_is_2insns (high_bits, low_bits) | |
2a01c939 | 1901 | unsigned HOST_WIDE_INT high_bits, low_bits; |
e0d80184 DM |
1902 | { |
1903 | int highest_bit_set, lowest_bit_set, all_bits_between_are_set; | |
284d86e9 | 1904 | |
e0d80184 | 1905 | if (high_bits == 0 |
f451b552 | 1906 | || high_bits == 0xffffffff) |
e0d80184 | 1907 | return 1; |
6a4bb1fa | 1908 | |
e0d80184 DM |
1909 | analyze_64bit_constant (high_bits, low_bits, |
1910 | &highest_bit_set, &lowest_bit_set, | |
1911 | &all_bits_between_are_set); | |
6a4bb1fa | 1912 | |
f710f868 DM |
1913 | if ((highest_bit_set == 63 |
1914 | || lowest_bit_set == 0) | |
e0d80184 DM |
1915 | && all_bits_between_are_set != 0) |
1916 | return 1; | |
6a4bb1fa | 1917 | |
9208e4b2 DM |
1918 | if ((highest_bit_set - lowest_bit_set) < 21) |
1919 | return 1; | |
1920 | ||
6a4bb1fa DE |
1921 | return 0; |
1922 | } | |
1923 | ||
2a01c939 | 1924 | static unsigned HOST_WIDE_INT create_simple_focus_bits |
f6da8bc3 | 1925 | PARAMS ((unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT, |
ddf80874 | 1926 | int, int)); |
2a01c939 DM |
1927 | |
1928 | static unsigned HOST_WIDE_INT | |
ddf80874 | 1929 | create_simple_focus_bits (high_bits, low_bits, lowest_bit_set, shift) |
2a01c939 | 1930 | unsigned HOST_WIDE_INT high_bits, low_bits; |
ddf80874 | 1931 | int lowest_bit_set, shift; |
ab835497 | 1932 | { |
f710f868 | 1933 | HOST_WIDE_INT hi, lo; |
ab835497 | 1934 | |
e0d80184 DM |
1935 | if (lowest_bit_set < 32) |
1936 | { | |
1937 | lo = (low_bits >> lowest_bit_set) << shift; | |
1938 | hi = ((high_bits << (32 - lowest_bit_set)) << shift); | |
1939 | } | |
1940 | else | |
1941 | { | |
1942 | lo = 0; | |
1943 | hi = ((high_bits >> (lowest_bit_set - 32)) << shift); | |
1944 | } | |
1945 | if (hi & lo) | |
9208e4b2 | 1946 | abort (); |
e0d80184 DM |
1947 | return (hi | lo); |
1948 | } | |
ab835497 | 1949 | |
e0d80184 DM |
1950 | /* Here we are sure to be arch64 and this is an integer constant |
1951 | being loaded into a register. Emit the most efficient | |
1952 | insn sequence possible. Detection of all the 1-insn cases | |
1953 | has been done already. */ | |
1954 | void | |
1955 | sparc_emit_set_const64 (op0, op1) | |
1956 | rtx op0; | |
1957 | rtx op1; | |
1958 | { | |
2a01c939 | 1959 | unsigned HOST_WIDE_INT high_bits, low_bits; |
e0d80184 DM |
1960 | int lowest_bit_set, highest_bit_set; |
1961 | int all_bits_between_are_set; | |
e0d80184 | 1962 | rtx temp; |
ab835497 | 1963 | |
e0d80184 | 1964 | /* Sanity check that we know what we are working with. */ |
380f6ad3 | 1965 | if (! TARGET_ARCH64) |
9208e4b2 | 1966 | abort (); |
95726648 | 1967 | |
380f6ad3 JJ |
1968 | if (GET_CODE (op0) != SUBREG) |
1969 | { | |
1970 | if (GET_CODE (op0) != REG | |
1971 | || (REGNO (op0) >= SPARC_FIRST_FP_REG | |
1972 | && REGNO (op0) <= SPARC_LAST_V9_FP_REG)) | |
1973 | abort (); | |
1974 | } | |
1975 | ||
f710f868 DM |
1976 | if (reload_in_progress || reload_completed) |
1977 | temp = op0; | |
1978 | else | |
1979 | temp = gen_reg_rtx (DImode); | |
1980 | ||
e0d80184 DM |
1981 | if (GET_CODE (op1) != CONST_DOUBLE |
1982 | && GET_CODE (op1) != CONST_INT) | |
1983 | { | |
5f78aa30 JC |
1984 | sparc_emit_set_symbolic_const64 (op0, op1, temp); |
1985 | return; | |
e0d80184 | 1986 | } |
ab835497 | 1987 | |
e0d80184 DM |
1988 | if (GET_CODE (op1) == CONST_DOUBLE) |
1989 | { | |
1990 | #if HOST_BITS_PER_WIDE_INT == 64 | |
2a01c939 | 1991 | high_bits = (CONST_DOUBLE_LOW (op1) >> 32) & 0xffffffff; |
e0d80184 DM |
1992 | low_bits = CONST_DOUBLE_LOW (op1) & 0xffffffff; |
1993 | #else | |
1994 | high_bits = CONST_DOUBLE_HIGH (op1); | |
1995 | low_bits = CONST_DOUBLE_LOW (op1); | |
1996 | #endif | |
ab835497 | 1997 | } |
e0d80184 | 1998 | else |
ab835497 | 1999 | { |
e0d80184 | 2000 | #if HOST_BITS_PER_WIDE_INT == 64 |
2a01c939 | 2001 | high_bits = ((INTVAL (op1) >> 32) & 0xffffffff); |
e0d80184 DM |
2002 | low_bits = (INTVAL (op1) & 0xffffffff); |
2003 | #else | |
2004 | high_bits = ((INTVAL (op1) < 0) ? | |
2005 | 0xffffffff : | |
2006 | 0x00000000); | |
2007 | low_bits = INTVAL (op1); | |
2008 | #endif | |
2009 | } | |
ab835497 | 2010 | |
e0d80184 DM |
2011 | /* low_bits bits 0 --> 31 |
2012 | high_bits bits 32 --> 63 */ | |
ab835497 | 2013 | |
e0d80184 DM |
2014 | analyze_64bit_constant (high_bits, low_bits, |
2015 | &highest_bit_set, &lowest_bit_set, | |
2016 | &all_bits_between_are_set); | |
2017 | ||
2018 | /* First try for a 2-insn sequence. */ | |
2019 | ||
2020 | /* These situations are preferred because the optimizer can | |
2021 | * do more things with them: | |
2022 | * 1) mov -1, %reg | |
2023 | * sllx %reg, shift, %reg | |
2024 | * 2) mov -1, %reg | |
2025 | * srlx %reg, shift, %reg | |
2026 | * 3) mov some_small_const, %reg | |
2027 | * sllx %reg, shift, %reg | |
2028 | */ | |
2029 | if (((highest_bit_set == 63 | |
2030 | || lowest_bit_set == 0) | |
2031 | && all_bits_between_are_set != 0) | |
2a01c939 | 2032 | || ((highest_bit_set - lowest_bit_set) < 12)) |
e0d80184 | 2033 | { |
9208e4b2 | 2034 | HOST_WIDE_INT the_const = -1; |
e0d80184 DM |
2035 | int shift = lowest_bit_set; |
2036 | ||
f710f868 DM |
2037 | if ((highest_bit_set != 63 |
2038 | && lowest_bit_set != 0) | |
2039 | || all_bits_between_are_set == 0) | |
ab835497 | 2040 | { |
e0d80184 | 2041 | the_const = |
9208e4b2 | 2042 | create_simple_focus_bits (high_bits, low_bits, |
9208e4b2 | 2043 | lowest_bit_set, 0); |
ab835497 | 2044 | } |
e0d80184 | 2045 | else if (lowest_bit_set == 0) |
9208e4b2 | 2046 | shift = -(63 - highest_bit_set); |
e0d80184 | 2047 | |
f710f868 DM |
2048 | if (! SPARC_SIMM13_P (the_const)) |
2049 | abort (); | |
2050 | ||
9208e4b2 | 2051 | emit_insn (gen_safe_SET64 (temp, the_const)); |
e0d80184 | 2052 | if (shift > 0) |
9208e4b2 | 2053 | emit_insn (gen_rtx_SET (VOIDmode, |
e0d80184 DM |
2054 | op0, |
2055 | gen_rtx_ASHIFT (DImode, | |
2056 | temp, | |
2057 | GEN_INT (shift)))); | |
2058 | else if (shift < 0) | |
9208e4b2 | 2059 | emit_insn (gen_rtx_SET (VOIDmode, |
e0d80184 | 2060 | op0, |
9208e4b2 | 2061 | gen_rtx_LSHIFTRT (DImode, |
e0d80184 DM |
2062 | temp, |
2063 | GEN_INT (-shift)))); | |
ab835497 RK |
2064 | else |
2065 | abort (); | |
e0d80184 DM |
2066 | return; |
2067 | } | |
ab835497 | 2068 | |
e0d80184 DM |
2069 | /* Now a range of 22 or less bits set somewhere. |
2070 | * 1) sethi %hi(focus_bits), %reg | |
2071 | * sllx %reg, shift, %reg | |
2072 | * 2) sethi %hi(focus_bits), %reg | |
2073 | * srlx %reg, shift, %reg | |
2074 | */ | |
2a01c939 | 2075 | if ((highest_bit_set - lowest_bit_set) < 21) |
e0d80184 | 2076 | { |
2a01c939 | 2077 | unsigned HOST_WIDE_INT focus_bits = |
e0d80184 | 2078 | create_simple_focus_bits (high_bits, low_bits, |
ddf80874 | 2079 | lowest_bit_set, 10); |
f710f868 DM |
2080 | |
2081 | if (! SPARC_SETHI_P (focus_bits)) | |
2082 | abort (); | |
2083 | ||
9208e4b2 | 2084 | sparc_emit_set_safe_HIGH64 (temp, focus_bits); |
e0d80184 | 2085 | |
9208e4b2 | 2086 | /* If lowest_bit_set == 10 then a sethi alone could have done it. */ |
e0d80184 | 2087 | if (lowest_bit_set < 10) |
9208e4b2 | 2088 | emit_insn (gen_rtx_SET (VOIDmode, |
e0d80184 | 2089 | op0, |
9208e4b2 | 2090 | gen_rtx_LSHIFTRT (DImode, temp, |
e0d80184 | 2091 | GEN_INT (10 - lowest_bit_set)))); |
9208e4b2 DM |
2092 | else if (lowest_bit_set > 10) |
2093 | emit_insn (gen_rtx_SET (VOIDmode, | |
e0d80184 DM |
2094 | op0, |
2095 | gen_rtx_ASHIFT (DImode, temp, | |
2096 | GEN_INT (lowest_bit_set - 10)))); | |
2097 | else | |
9208e4b2 | 2098 | abort (); |
e0d80184 DM |
2099 | return; |
2100 | } | |
2101 | ||
2102 | /* 1) sethi %hi(low_bits), %reg | |
2103 | * or %reg, %lo(low_bits), %reg | |
2104 | * 2) sethi %hi(~low_bits), %reg | |
2105 | * xor %reg, %lo(-0x400 | (low_bits & 0x3ff)), %reg | |
2106 | */ | |
2107 | if (high_bits == 0 | |
2a01c939 | 2108 | || high_bits == 0xffffffff) |
5f78aa30 JC |
2109 | { |
2110 | sparc_emit_set_const64_quick1 (op0, temp, low_bits, | |
2111 | (high_bits == 0xffffffff)); | |
2112 | return; | |
2113 | } | |
e0d80184 | 2114 | |
f710f868 DM |
2115 | /* Now, try 3-insn sequences. */ |
2116 | ||
e0d80184 DM |
2117 | /* 1) sethi %hi(high_bits), %reg |
2118 | * or %reg, %lo(high_bits), %reg | |
2119 | * sllx %reg, 32, %reg | |
2120 | */ | |
f710f868 | 2121 | if (low_bits == 0) |
5f78aa30 | 2122 | { |
f710f868 | 2123 | sparc_emit_set_const64_quick2 (op0, temp, high_bits, 0, 32); |
5f78aa30 JC |
2124 | return; |
2125 | } | |
e0d80184 | 2126 | |
f710f868 DM |
2127 | /* We may be able to do something quick |
2128 | when the constant is negated, so try that. */ | |
e0d80184 DM |
2129 | if (const64_is_2insns ((~high_bits) & 0xffffffff, |
2130 | (~low_bits) & 0xfffffc00)) | |
2131 | { | |
5108f3e5 DM |
2132 | /* NOTE: The trailing bits get XOR'd so we need the |
2133 | non-negated bits, not the negated ones. */ | |
2134 | unsigned HOST_WIDE_INT trailing_bits = low_bits & 0x3ff; | |
e0d80184 DM |
2135 | |
2136 | if ((((~high_bits) & 0xffffffff) == 0 | |
2137 | && ((~low_bits) & 0x80000000) == 0) | |
2138 | || (((~high_bits) & 0xffffffff) == 0xffffffff | |
2139 | && ((~low_bits) & 0x80000000) != 0)) | |
ab835497 | 2140 | { |
5108f3e5 | 2141 | int fast_int = (~low_bits & 0xffffffff); |
e0d80184 | 2142 | |
5108f3e5 DM |
2143 | if ((SPARC_SETHI_P (fast_int) |
2144 | && (~high_bits & 0xffffffff) == 0) | |
2145 | || SPARC_SIMM13_P (fast_int)) | |
9208e4b2 | 2146 | emit_insn (gen_safe_SET64 (temp, fast_int)); |
ab835497 | 2147 | else |
9208e4b2 | 2148 | sparc_emit_set_const64 (temp, GEN_INT64 (fast_int)); |
ab835497 | 2149 | } |
e0d80184 DM |
2150 | else |
2151 | { | |
2152 | rtx negated_const; | |
2153 | #if HOST_BITS_PER_WIDE_INT == 64 | |
2154 | negated_const = GEN_INT (((~low_bits) & 0xfffffc00) | | |
2155 | (((HOST_WIDE_INT)((~high_bits) & 0xffffffff))<<32)); | |
2156 | #else | |
5692c7bc ZW |
2157 | negated_const = immed_double_const ((~low_bits) & 0xfffffc00, |
2158 | (~high_bits) & 0xffffffff, | |
2159 | DImode); | |
e0d80184 DM |
2160 | #endif |
2161 | sparc_emit_set_const64 (temp, negated_const); | |
2162 | } | |
5108f3e5 DM |
2163 | |
2164 | /* If we are XOR'ing with -1, then we should emit a one's complement | |
2165 | instead. This way the combiner will notice logical operations | |
2166 | such as ANDN later on and substitute. */ | |
2167 | if (trailing_bits == 0x3ff) | |
2168 | { | |
2169 | emit_insn (gen_rtx_SET (VOIDmode, op0, | |
2170 | gen_rtx_NOT (DImode, temp))); | |
2171 | } | |
2172 | else | |
2173 | { | |
2174 | emit_insn (gen_rtx_SET (VOIDmode, | |
2175 | op0, | |
2176 | gen_safe_XOR64 (temp, | |
2177 | (-0x400 | trailing_bits)))); | |
2178 | } | |
e0d80184 | 2179 | return; |
ab835497 | 2180 | } |
ab835497 | 2181 | |
e0d80184 DM |
2182 | /* 1) sethi %hi(xxx), %reg |
2183 | * or %reg, %lo(xxx), %reg | |
2184 | * sllx %reg, yyy, %reg | |
f710f868 DM |
2185 | * |
2186 | * ??? This is just a generalized version of the low_bits==0 | |
2187 | * thing above, FIXME... | |
e0d80184 DM |
2188 | */ |
2189 | if ((highest_bit_set - lowest_bit_set) < 32) | |
2190 | { | |
f710f868 DM |
2191 | unsigned HOST_WIDE_INT focus_bits = |
2192 | create_simple_focus_bits (high_bits, low_bits, | |
ddf80874 | 2193 | lowest_bit_set, 0); |
ab835497 | 2194 | |
e0d80184 DM |
2195 | /* We can't get here in this state. */ |
2196 | if (highest_bit_set < 32 | |
2197 | || lowest_bit_set >= 32) | |
9208e4b2 | 2198 | abort (); |
95726648 | 2199 | |
e0d80184 DM |
2200 | /* So what we know is that the set bits straddle the |
2201 | middle of the 64-bit word. */ | |
5f78aa30 JC |
2202 | sparc_emit_set_const64_quick2 (op0, temp, |
2203 | focus_bits, 0, | |
2204 | lowest_bit_set); | |
2205 | return; | |
e0d80184 | 2206 | } |
c85f7c16 | 2207 | |
f710f868 DM |
2208 | /* 1) sethi %hi(high_bits), %reg |
2209 | * or %reg, %lo(high_bits), %reg | |
2210 | * sllx %reg, 32, %reg | |
2211 | * or %reg, low_bits, %reg | |
2212 | */ | |
2213 | if (SPARC_SIMM13_P(low_bits) | |
2214 | && ((int)low_bits > 0)) | |
2215 | { | |
2216 | sparc_emit_set_const64_quick2 (op0, temp, high_bits, low_bits, 32); | |
2217 | return; | |
2218 | } | |
2219 | ||
80ffc95e | 2220 | /* The easiest way when all else fails, is full decomposition. */ |
e0d80184 DM |
2221 | #if 0 |
2222 | printf ("sparc_emit_set_const64: Hard constant [%08lx%08lx] neg[%08lx%08lx]\n", | |
2223 | high_bits, low_bits, ~high_bits, ~low_bits); | |
2224 | #endif | |
2225 | sparc_emit_set_const64_longway (op0, temp, high_bits, low_bits); | |
c85f7c16 JL |
2226 | } |
2227 | ||
e267e177 RH |
2228 | /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, |
2229 | return the mode to be used for the comparison. For floating-point, | |
2230 | CCFP[E]mode is used. CC_NOOVmode should be used when the first operand | |
2231 | is a PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special | |
2232 | processing is needed. */ | |
2233 | ||
2234 | enum machine_mode | |
2235 | select_cc_mode (op, x, y) | |
2236 | enum rtx_code op; | |
2237 | rtx x; | |
2238 | rtx y ATTRIBUTE_UNUSED; | |
2239 | { | |
2240 | if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) | |
2241 | { | |
2242 | switch (op) | |
2243 | { | |
2244 | case EQ: | |
2245 | case NE: | |
2246 | case UNORDERED: | |
2247 | case ORDERED: | |
2248 | case UNLT: | |
2249 | case UNLE: | |
2250 | case UNGT: | |
2251 | case UNGE: | |
2252 | case UNEQ: | |
7913f3d0 | 2253 | case LTGT: |
e267e177 RH |
2254 | return CCFPmode; |
2255 | ||
2256 | case LT: | |
2257 | case LE: | |
2258 | case GT: | |
2259 | case GE: | |
2260 | return CCFPEmode; | |
2261 | ||
2262 | default: | |
2263 | abort (); | |
2264 | } | |
2265 | } | |
2266 | else if (GET_CODE (x) == PLUS || GET_CODE (x) == MINUS | |
2267 | || GET_CODE (x) == NEG || GET_CODE (x) == ASHIFT) | |
2268 | { | |
2269 | if (TARGET_ARCH64 && GET_MODE (x) == DImode) | |
2270 | return CCX_NOOVmode; | |
2271 | else | |
2272 | return CC_NOOVmode; | |
2273 | } | |
2274 | else | |
2275 | { | |
2276 | if (TARGET_ARCH64 && GET_MODE (x) == DImode) | |
2277 | return CCXmode; | |
2278 | else | |
2279 | return CCmode; | |
2280 | } | |
2281 | } | |
2282 | ||
e0d80184 DM |
2283 | /* X and Y are two things to compare using CODE. Emit the compare insn and |
2284 | return the rtx for the cc reg in the proper mode. */ | |
c85f7c16 | 2285 | |
e0d80184 DM |
2286 | rtx |
2287 | gen_compare_reg (code, x, y) | |
2288 | enum rtx_code code; | |
2289 | rtx x, y; | |
c85f7c16 | 2290 | { |
e0d80184 DM |
2291 | enum machine_mode mode = SELECT_CC_MODE (code, x, y); |
2292 | rtx cc_reg; | |
c85f7c16 | 2293 | |
e0d80184 DM |
2294 | /* ??? We don't have movcc patterns so we cannot generate pseudo regs for the |
2295 | fcc regs (cse can't tell they're really call clobbered regs and will | |
2296 | remove a duplicate comparison even if there is an intervening function | |
2297 | call - it will then try to reload the cc reg via an int reg which is why | |
2298 | we need the movcc patterns). It is possible to provide the movcc | |
2299 | patterns by using the ldxfsr/stxfsr v9 insns. I tried it: you need two | |
2300 | registers (say %g1,%g5) and it takes about 6 insns. A better fix would be | |
2301 | to tell cse that CCFPE mode registers (even pseudos) are call | |
2302 | clobbered. */ | |
c85f7c16 | 2303 | |
e0d80184 DM |
2304 | /* ??? This is an experiment. Rather than making changes to cse which may |
2305 | or may not be easy/clean, we do our own cse. This is possible because | |
2306 | we will generate hard registers. Cse knows they're call clobbered (it | |
2307 | doesn't know the same thing about pseudos). If we guess wrong, no big | |
2308 | deal, but if we win, great! */ | |
c85f7c16 | 2309 | |
e0d80184 DM |
2310 | if (TARGET_V9 && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) |
2311 | #if 1 /* experiment */ | |
284d86e9 | 2312 | { |
e0d80184 DM |
2313 | int reg; |
2314 | /* We cycle through the registers to ensure they're all exercised. */ | |
2315 | static int next_fcc_reg = 0; | |
2316 | /* Previous x,y for each fcc reg. */ | |
2317 | static rtx prev_args[4][2]; | |
284d86e9 | 2318 | |
e0d80184 DM |
2319 | /* Scan prev_args for x,y. */ |
2320 | for (reg = 0; reg < 4; reg++) | |
2321 | if (prev_args[reg][0] == x && prev_args[reg][1] == y) | |
2322 | break; | |
2323 | if (reg == 4) | |
2324 | { | |
2325 | reg = next_fcc_reg; | |
2326 | prev_args[reg][0] = x; | |
2327 | prev_args[reg][1] = y; | |
2328 | next_fcc_reg = (next_fcc_reg + 1) & 3; | |
2329 | } | |
2330 | cc_reg = gen_rtx_REG (mode, reg + SPARC_FIRST_V9_FCC_REG); | |
284d86e9 | 2331 | } |
e0d80184 DM |
2332 | #else |
2333 | cc_reg = gen_reg_rtx (mode); | |
2334 | #endif /* ! experiment */ | |
2335 | else if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) | |
2336 | cc_reg = gen_rtx_REG (mode, SPARC_FCC_REG); | |
2337 | else | |
2338 | cc_reg = gen_rtx_REG (mode, SPARC_ICC_REG); | |
284d86e9 | 2339 | |
e0d80184 DM |
2340 | emit_insn (gen_rtx_SET (VOIDmode, cc_reg, |
2341 | gen_rtx_COMPARE (mode, x, y))); | |
c85f7c16 | 2342 | |
e0d80184 DM |
2343 | return cc_reg; |
2344 | } | |
c85f7c16 | 2345 | |
e0d80184 DM |
2346 | /* This function is used for v9 only. |
2347 | CODE is the code for an Scc's comparison. | |
2348 | OPERANDS[0] is the target of the Scc insn. | |
2349 | OPERANDS[1] is the value we compare against const0_rtx (which hasn't | |
2350 | been generated yet). | |
c85f7c16 | 2351 | |
e0d80184 | 2352 | This function is needed to turn |
ab835497 | 2353 | |
e0d80184 DM |
2354 | (set (reg:SI 110) |
2355 | (gt (reg:CCX 100 %icc) | |
2356 | (const_int 0))) | |
2357 | into | |
2358 | (set (reg:SI 110) | |
2359 | (gt:DI (reg:CCX 100 %icc) | |
2360 | (const_int 0))) | |
2361 | ||
2362 | IE: The instruction recognizer needs to see the mode of the comparison to | |
2363 | find the right instruction. We could use "gt:DI" right in the | |
2364 | define_expand, but leaving it out allows us to handle DI, SI, etc. | |
ab835497 | 2365 | |
e0d80184 DM |
2366 | We refer to the global sparc compare operands sparc_compare_op0 and |
2367 | sparc_compare_op1. */ | |
ab835497 RK |
2368 | |
2369 | int | |
e0d80184 DM |
2370 | gen_v9_scc (compare_code, operands) |
2371 | enum rtx_code compare_code; | |
2372 | register rtx *operands; | |
ab835497 | 2373 | { |
e0d80184 | 2374 | rtx temp, op0, op1; |
ab835497 | 2375 | |
e0d80184 DM |
2376 | if (! TARGET_ARCH64 |
2377 | && (GET_MODE (sparc_compare_op0) == DImode | |
2378 | || GET_MODE (operands[0]) == DImode)) | |
2379 | return 0; | |
7e2feebf | 2380 | |
a42519be | 2381 | op0 = sparc_compare_op0; |
e0d80184 DM |
2382 | op1 = sparc_compare_op1; |
2383 | ||
2384 | /* Try to use the movrCC insns. */ | |
2385 | if (TARGET_ARCH64 | |
2386 | && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT | |
2387 | && op1 == const0_rtx | |
2388 | && v9_regcmp_p (compare_code)) | |
ab835497 | 2389 | { |
e0d80184 | 2390 | /* Special case for op0 != 0. This can be done with one instruction if |
a42519be | 2391 | operands[0] == sparc_compare_op0. */ |
e0d80184 DM |
2392 | |
2393 | if (compare_code == NE | |
2394 | && GET_MODE (operands[0]) == DImode | |
a42519be | 2395 | && rtx_equal_p (op0, operands[0])) |
ab835497 | 2396 | { |
e0d80184 DM |
2397 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], |
2398 | gen_rtx_IF_THEN_ELSE (DImode, | |
2399 | gen_rtx_fmt_ee (compare_code, DImode, | |
2400 | op0, const0_rtx), | |
2401 | const1_rtx, | |
2402 | operands[0]))); | |
ab835497 RK |
2403 | return 1; |
2404 | } | |
e0d80184 | 2405 | |
a42519be JJ |
2406 | if (reg_overlap_mentioned_p (operands[0], op0)) |
2407 | { | |
2408 | /* Handle the case where operands[0] == sparc_compare_op0. | |
2409 | We "early clobber" the result. */ | |
2410 | op0 = gen_reg_rtx (GET_MODE (sparc_compare_op0)); | |
2411 | emit_move_insn (op0, sparc_compare_op0); | |
2412 | } | |
2413 | ||
e0d80184 DM |
2414 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], const0_rtx)); |
2415 | if (GET_MODE (op0) != DImode) | |
ab835497 | 2416 | { |
e0d80184 DM |
2417 | temp = gen_reg_rtx (DImode); |
2418 | convert_move (temp, op0, 0); | |
ab835497 | 2419 | } |
e0d80184 DM |
2420 | else |
2421 | temp = op0; | |
2422 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], | |
2423 | gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]), | |
2424 | gen_rtx_fmt_ee (compare_code, DImode, | |
2425 | temp, const0_rtx), | |
2426 | const1_rtx, | |
2427 | operands[0]))); | |
95726648 DE |
2428 | return 1; |
2429 | } | |
e0d80184 | 2430 | else |
ab835497 | 2431 | { |
e0d80184 | 2432 | operands[1] = gen_compare_reg (compare_code, op0, op1); |
ab835497 | 2433 | |
e0d80184 | 2434 | switch (GET_MODE (operands[1])) |
ab835497 | 2435 | { |
e0d80184 DM |
2436 | case CCmode : |
2437 | case CCXmode : | |
2438 | case CCFPEmode : | |
2439 | case CCFPmode : | |
2440 | break; | |
2441 | default : | |
2442 | abort (); | |
ab835497 | 2443 | } |
e0d80184 DM |
2444 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], const0_rtx)); |
2445 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], | |
2446 | gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]), | |
2447 | gen_rtx_fmt_ee (compare_code, | |
2448 | GET_MODE (operands[1]), | |
2449 | operands[1], const0_rtx), | |
2450 | const1_rtx, operands[0]))); | |
2451 | return 1; | |
ab835497 | 2452 | } |
ab835497 | 2453 | } |
4fb4e4b8 | 2454 | |
e0d80184 DM |
2455 | /* Emit a conditional jump insn for the v9 architecture using comparison code |
2456 | CODE and jump target LABEL. | |
2457 | This function exists to take advantage of the v9 brxx insns. */ | |
ab835497 | 2458 | |
e0d80184 DM |
2459 | void |
2460 | emit_v9_brxx_insn (code, op0, label) | |
2461 | enum rtx_code code; | |
2462 | rtx op0, label; | |
ab835497 | 2463 | { |
e0d80184 DM |
2464 | emit_jump_insn (gen_rtx_SET (VOIDmode, |
2465 | pc_rtx, | |
2466 | gen_rtx_IF_THEN_ELSE (VOIDmode, | |
2467 | gen_rtx_fmt_ee (code, GET_MODE (op0), | |
2468 | op0, const0_rtx), | |
2469 | gen_rtx_LABEL_REF (VOIDmode, label), | |
2470 | pc_rtx))); | |
2471 | } | |
7b1ac798 JJ |
2472 | |
2473 | /* Generate a DFmode part of a hard TFmode register. | |
2474 | REG is the TFmode hard register, LOW is 1 for the | |
2475 | low 64bit of the register and 0 otherwise. | |
2476 | */ | |
2477 | rtx | |
2478 | gen_df_reg (reg, low) | |
2479 | rtx reg; | |
2480 | int low; | |
2481 | { | |
2482 | int regno = REGNO (reg); | |
2483 | ||
2484 | if ((WORDS_BIG_ENDIAN == 0) ^ (low != 0)) | |
2aac41d6 | 2485 | regno += (TARGET_ARCH64 && regno < 32) ? 1 : 2; |
7b1ac798 JJ |
2486 | return gen_rtx_REG (DFmode, regno); |
2487 | } | |
e0d80184 | 2488 | \f |
73985940 RH |
2489 | /* Generate a call to FUNC with OPERANDS. Operand 0 is the return value. |
2490 | Unlike normal calls, TFmode operands are passed by reference. It is | |
2491 | assumed that no more than 3 operands are required. */ | |
2492 | ||
2493 | static void | |
2494 | emit_soft_tfmode_libcall (func_name, nargs, operands) | |
2495 | const char *func_name; | |
2496 | int nargs; | |
2497 | rtx *operands; | |
2498 | { | |
2499 | rtx ret_slot = NULL, arg[3], func_sym; | |
4e7d5d27 | 2500 | int i; |
73985940 RH |
2501 | |
2502 | /* We only expect to be called for conversions, unary, and binary ops. */ | |
2503 | if (nargs < 2 || nargs > 3) | |
2504 | abort (); | |
2505 | ||
2506 | for (i = 0; i < nargs; ++i) | |
2507 | { | |
2508 | rtx this_arg = operands[i]; | |
2509 | rtx this_slot; | |
2510 | ||
2511 | /* TFmode arguments and return values are passed by reference. */ | |
2512 | if (GET_MODE (this_arg) == TFmode) | |
2513 | { | |
4e7d5d27 DM |
2514 | int force_stack_temp; |
2515 | ||
2516 | force_stack_temp = 0; | |
2517 | if (TARGET_BUGGY_QP_LIB && i == 0) | |
2518 | force_stack_temp = 1; | |
2519 | ||
2520 | if (GET_CODE (this_arg) == MEM | |
2521 | && ! force_stack_temp) | |
2522 | this_arg = XEXP (this_arg, 0); | |
2523 | else if (CONSTANT_P (this_arg) | |
2524 | && ! force_stack_temp) | |
73985940 RH |
2525 | { |
2526 | this_slot = force_const_mem (TFmode, this_arg); | |
2527 | this_arg = XEXP (this_slot, 0); | |
2528 | } | |
2529 | else | |
2530 | { | |
2531 | this_slot = assign_stack_temp (TFmode, GET_MODE_SIZE (TFmode), 0); | |
2532 | ||
2533 | /* Operand 0 is the return value. We'll copy it out later. */ | |
2534 | if (i > 0) | |
2535 | emit_move_insn (this_slot, this_arg); | |
2536 | else | |
2537 | ret_slot = this_slot; | |
2538 | ||
2539 | this_arg = XEXP (this_slot, 0); | |
2540 | } | |
2541 | } | |
2542 | ||
2543 | arg[i] = this_arg; | |
2544 | } | |
2545 | ||
2546 | func_sym = gen_rtx_SYMBOL_REF (Pmode, func_name); | |
2547 | ||
2548 | if (GET_MODE (operands[0]) == TFmode) | |
2549 | { | |
2550 | if (nargs == 2) | |
2551 | emit_library_call (func_sym, LCT_NORMAL, VOIDmode, 2, | |
2552 | arg[0], GET_MODE (arg[0]), | |
2553 | arg[1], GET_MODE (arg[1])); | |
2554 | else | |
2555 | emit_library_call (func_sym, LCT_NORMAL, VOIDmode, 3, | |
2556 | arg[0], GET_MODE (arg[0]), | |
2557 | arg[1], GET_MODE (arg[1]), | |
2558 | arg[2], GET_MODE (arg[2])); | |
2559 | ||
2560 | if (ret_slot) | |
2561 | emit_move_insn (operands[0], ret_slot); | |
2562 | } | |
2563 | else | |
2564 | { | |
2565 | rtx ret; | |
2566 | ||
2567 | if (nargs != 2) | |
2568 | abort (); | |
2569 | ||
2570 | ret = emit_library_call_value (func_sym, operands[0], LCT_NORMAL, | |
2571 | GET_MODE (operands[0]), 1, | |
2572 | arg[1], GET_MODE (arg[1])); | |
2573 | ||
2574 | if (ret != operands[0]) | |
2575 | emit_move_insn (operands[0], ret); | |
2576 | } | |
2577 | } | |
2578 | ||
2579 | /* Expand soft-float TFmode calls to sparc abi routines. */ | |
2580 | ||
2581 | static void | |
2582 | emit_soft_tfmode_binop (code, operands) | |
2583 | enum rtx_code code; | |
2584 | rtx *operands; | |
2585 | { | |
2586 | const char *func; | |
2587 | ||
2588 | switch (code) | |
2589 | { | |
2590 | case PLUS: | |
2591 | func = "_Qp_add"; | |
2592 | break; | |
2593 | case MINUS: | |
2594 | func = "_Qp_sub"; | |
2595 | break; | |
2596 | case MULT: | |
2597 | func = "_Qp_mul"; | |
2598 | break; | |
2599 | case DIV: | |
2600 | func = "_Qp_div"; | |
2601 | break; | |
2602 | default: | |
2603 | abort (); | |
2604 | } | |
2605 | ||
2606 | emit_soft_tfmode_libcall (func, 3, operands); | |
2607 | } | |
2608 | ||
2609 | static void | |
2610 | emit_soft_tfmode_unop (code, operands) | |
2611 | enum rtx_code code; | |
2612 | rtx *operands; | |
2613 | { | |
2614 | const char *func; | |
2615 | ||
2616 | switch (code) | |
2617 | { | |
2618 | case SQRT: | |
2619 | func = "_Qp_sqrt"; | |
2620 | break; | |
2621 | default: | |
2622 | abort (); | |
2623 | } | |
2624 | ||
2625 | emit_soft_tfmode_libcall (func, 2, operands); | |
2626 | } | |
2627 | ||
2628 | static void | |
2629 | emit_soft_tfmode_cvt (code, operands) | |
2630 | enum rtx_code code; | |
2631 | rtx *operands; | |
2632 | { | |
2633 | const char *func; | |
2634 | ||
2635 | switch (code) | |
2636 | { | |
2637 | case FLOAT_EXTEND: | |
2638 | switch (GET_MODE (operands[1])) | |
2639 | { | |
2640 | case SFmode: | |
2641 | func = "_Qp_stoq"; | |
2642 | break; | |
2643 | case DFmode: | |
2644 | func = "_Qp_dtoq"; | |
2645 | break; | |
2646 | default: | |
2647 | abort (); | |
2648 | } | |
2649 | break; | |
2650 | ||
2651 | case FLOAT_TRUNCATE: | |
2652 | switch (GET_MODE (operands[0])) | |
2653 | { | |
2654 | case SFmode: | |
2655 | func = "_Qp_qtos"; | |
2656 | break; | |
2657 | case DFmode: | |
2658 | func = "_Qp_qtod"; | |
2659 | break; | |
2660 | default: | |
2661 | abort (); | |
2662 | } | |
2663 | break; | |
2664 | ||
2665 | case FLOAT: | |
2666 | switch (GET_MODE (operands[1])) | |
2667 | { | |
2668 | case SImode: | |
2669 | func = "_Qp_itoq"; | |
2670 | break; | |
2671 | case DImode: | |
2672 | func = "_Qp_xtoq"; | |
2673 | break; | |
2674 | default: | |
2675 | abort (); | |
2676 | } | |
2677 | break; | |
2678 | ||
2679 | case UNSIGNED_FLOAT: | |
2680 | switch (GET_MODE (operands[1])) | |
2681 | { | |
2682 | case SImode: | |
2683 | func = "_Qp_uitoq"; | |
2684 | break; | |
2685 | case DImode: | |
2686 | func = "_Qp_uxtoq"; | |
2687 | break; | |
2688 | default: | |
2689 | abort (); | |
2690 | } | |
2691 | break; | |
2692 | ||
2693 | case FIX: | |
2694 | switch (GET_MODE (operands[0])) | |
2695 | { | |
2696 | case SImode: | |
2697 | func = "_Qp_qtoi"; | |
2698 | break; | |
2699 | case DImode: | |
2700 | func = "_Qp_qtox"; | |
2701 | break; | |
2702 | default: | |
2703 | abort (); | |
2704 | } | |
2705 | break; | |
2706 | ||
2707 | case UNSIGNED_FIX: | |
2708 | switch (GET_MODE (operands[0])) | |
2709 | { | |
2710 | case SImode: | |
2711 | func = "_Qp_qtoui"; | |
2712 | break; | |
2713 | case DImode: | |
2714 | func = "_Qp_qtoux"; | |
2715 | break; | |
2716 | default: | |
2717 | abort (); | |
2718 | } | |
2719 | break; | |
2720 | ||
2721 | default: | |
2722 | abort (); | |
2723 | } | |
2724 | ||
2725 | emit_soft_tfmode_libcall (func, 2, operands); | |
2726 | } | |
2727 | ||
2728 | /* Expand a hard-float tfmode operation. All arguments must be in | |
2729 | registers. */ | |
2730 | ||
2731 | static void | |
2732 | emit_hard_tfmode_operation (code, operands) | |
2733 | enum rtx_code code; | |
2734 | rtx *operands; | |
2735 | { | |
2736 | rtx op, dest; | |
2737 | ||
2738 | if (GET_RTX_CLASS (code) == '1') | |
2739 | { | |
2740 | operands[1] = force_reg (GET_MODE (operands[1]), operands[1]); | |
2741 | op = gen_rtx_fmt_e (code, GET_MODE (operands[0]), operands[1]); | |
2742 | } | |
2743 | else | |
2744 | { | |
2745 | operands[1] = force_reg (GET_MODE (operands[1]), operands[1]); | |
2746 | operands[2] = force_reg (GET_MODE (operands[2]), operands[2]); | |
2747 | op = gen_rtx_fmt_ee (code, GET_MODE (operands[0]), | |
2748 | operands[1], operands[2]); | |
2749 | } | |
2750 | ||
2751 | if (register_operand (operands[0], VOIDmode)) | |
2752 | dest = operands[0]; | |
2753 | else | |
2754 | dest = gen_reg_rtx (GET_MODE (operands[0])); | |
2755 | ||
2756 | emit_insn (gen_rtx_SET (VOIDmode, dest, op)); | |
2757 | ||
2758 | if (dest != operands[0]) | |
2759 | emit_move_insn (operands[0], dest); | |
2760 | } | |
2761 | ||
2762 | void | |
2763 | emit_tfmode_binop (code, operands) | |
2764 | enum rtx_code code; | |
2765 | rtx *operands; | |
2766 | { | |
2767 | if (TARGET_HARD_QUAD) | |
2768 | emit_hard_tfmode_operation (code, operands); | |
2769 | else | |
2770 | emit_soft_tfmode_binop (code, operands); | |
2771 | } | |
2772 | ||
2773 | void | |
2774 | emit_tfmode_unop (code, operands) | |
2775 | enum rtx_code code; | |
2776 | rtx *operands; | |
2777 | { | |
2778 | if (TARGET_HARD_QUAD) | |
2779 | emit_hard_tfmode_operation (code, operands); | |
2780 | else | |
2781 | emit_soft_tfmode_unop (code, operands); | |
2782 | } | |
2783 | ||
2784 | void | |
2785 | emit_tfmode_cvt (code, operands) | |
2786 | enum rtx_code code; | |
2787 | rtx *operands; | |
2788 | { | |
2789 | if (TARGET_HARD_QUAD) | |
2790 | emit_hard_tfmode_operation (code, operands); | |
2791 | else | |
2792 | emit_soft_tfmode_cvt (code, operands); | |
2793 | } | |
2794 | \f | |
e0d80184 DM |
2795 | /* Return nonzero if a return peephole merging return with |
2796 | setting of output register is ok. */ | |
2797 | int | |
2798 | leaf_return_peephole_ok () | |
2799 | { | |
2800 | return (actual_fsize == 0); | |
2801 | } | |
284d86e9 | 2802 | |
f17f9332 JJ |
2803 | /* Return nonzero if a branch/jump/call instruction will be emitting |
2804 | nop into its delay slot. */ | |
2805 | ||
2806 | int | |
2807 | empty_delay_slot (insn) | |
2808 | rtx insn; | |
2809 | { | |
2810 | rtx seq; | |
2811 | ||
2812 | /* If no previous instruction (should not happen), return true. */ | |
2813 | if (PREV_INSN (insn) == NULL) | |
2814 | return 1; | |
2815 | ||
2816 | seq = NEXT_INSN (PREV_INSN (insn)); | |
2817 | if (GET_CODE (PATTERN (seq)) == SEQUENCE) | |
2818 | return 0; | |
2819 | ||
2820 | return 1; | |
2821 | } | |
2822 | ||
e0d80184 DM |
2823 | /* Return nonzero if TRIAL can go into the function epilogue's |
2824 | delay slot. SLOT is the slot we are trying to fill. */ | |
ab835497 | 2825 | |
e0d80184 DM |
2826 | int |
2827 | eligible_for_epilogue_delay (trial, slot) | |
2828 | rtx trial; | |
2829 | int slot; | |
2830 | { | |
2831 | rtx pat, src; | |
4fb4e4b8 | 2832 | |
e0d80184 DM |
2833 | if (slot >= 1) |
2834 | return 0; | |
4fb4e4b8 | 2835 | |
e0d80184 DM |
2836 | if (GET_CODE (trial) != INSN || GET_CODE (PATTERN (trial)) != SET) |
2837 | return 0; | |
4fb4e4b8 | 2838 | |
e0d80184 DM |
2839 | if (get_attr_length (trial) != 1) |
2840 | return 0; | |
4fb4e4b8 | 2841 | |
e48addee JJ |
2842 | /* If there are any call-saved registers, we should scan TRIAL if it |
2843 | does not reference them. For now just make it easy. */ | |
2844 | if (num_gfregs) | |
2845 | return 0; | |
4fb4e4b8 | 2846 | |
1150a841 RH |
2847 | /* If the function uses __builtin_eh_return, the eh_return machinery |
2848 | occupies the delay slot. */ | |
2849 | if (current_function_calls_eh_return) | |
2850 | return 0; | |
2851 | ||
e0d80184 DM |
2852 | /* In the case of a true leaf function, anything can go into the delay slot. |
2853 | A delay slot only exists however if the frame size is zero, otherwise | |
2854 | we will put an insn to adjust the stack after the return. */ | |
54ff41b7 | 2855 | if (current_function_uses_only_leaf_regs) |
4fb4e4b8 | 2856 | { |
e0d80184 DM |
2857 | if (leaf_return_peephole_ok ()) |
2858 | return ((get_attr_in_uncond_branch_delay (trial) | |
2859 | == IN_BRANCH_DELAY_TRUE)); | |
2860 | return 0; | |
4fb4e4b8 | 2861 | } |
4fb4e4b8 | 2862 | |
e0d80184 | 2863 | pat = PATTERN (trial); |
795068a4 | 2864 | |
e0d80184 | 2865 | /* Otherwise, only operations which can be done in tandem with |
e48addee | 2866 | a `restore' or `return' insn can go into the delay slot. */ |
e0d80184 | 2867 | if (GET_CODE (SET_DEST (pat)) != REG |
e0d80184 DM |
2868 | || REGNO (SET_DEST (pat)) < 24) |
2869 | return 0; | |
795068a4 | 2870 | |
c137830f JJ |
2871 | /* If this instruction sets up floating point register and we have a return |
2872 | instruction, it can probably go in. But restore will not work | |
2873 | with FP_REGS. */ | |
2874 | if (REGNO (SET_DEST (pat)) >= 32) | |
2875 | { | |
2876 | if (TARGET_V9 && ! epilogue_renumber (&pat, 1) | |
2877 | && (get_attr_in_uncond_branch_delay (trial) == IN_BRANCH_DELAY_TRUE)) | |
2878 | return 1; | |
2879 | return 0; | |
2880 | } | |
2881 | ||
e0d80184 DM |
2882 | /* The set of insns matched here must agree precisely with the set of |
2883 | patterns paired with a RETURN in sparc.md. */ | |
795068a4 | 2884 | |
e0d80184 | 2885 | src = SET_SRC (pat); |
795068a4 | 2886 | |
3c6088d2 | 2887 | /* This matches "*return_[qhs]i" or even "*return_di" on TARGET_ARCH64. */ |
3ec6f1a9 RK |
2888 | if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT |
2889 | && arith_operand (src, GET_MODE (src))) | |
3c6088d2 JJ |
2890 | { |
2891 | if (TARGET_ARCH64) | |
2892 | return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode); | |
2893 | else | |
2894 | return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (SImode); | |
2895 | } | |
e48addee | 2896 | |
e0d80184 | 2897 | /* This matches "*return_di". */ |
3ec6f1a9 RK |
2898 | else if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT |
2899 | && arith_double_operand (src, GET_MODE (src))) | |
e0d80184 | 2900 | return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode); |
795068a4 | 2901 | |
e0d80184 DM |
2902 | /* This matches "*return_sf_no_fpu". */ |
2903 | else if (! TARGET_FPU && restore_operand (SET_DEST (pat), SFmode) | |
2904 | && register_operand (src, SFmode)) | |
2905 | return 1; | |
f5da225e | 2906 | |
e48addee JJ |
2907 | /* If we have return instruction, anything that does not use |
2908 | local or output registers and can go into a delay slot wins. */ | |
2909 | else if (TARGET_V9 && ! epilogue_renumber (&pat, 1) | |
2910 | && (get_attr_in_uncond_branch_delay (trial) == IN_BRANCH_DELAY_TRUE)) | |
2911 | return 1; | |
2912 | ||
e0d80184 DM |
2913 | /* This matches "*return_addsi". */ |
2914 | else if (GET_CODE (src) == PLUS | |
2915 | && arith_operand (XEXP (src, 0), SImode) | |
2916 | && arith_operand (XEXP (src, 1), SImode) | |
2917 | && (register_operand (XEXP (src, 0), SImode) | |
2918 | || register_operand (XEXP (src, 1), SImode))) | |
2919 | return 1; | |
2920 | ||
2921 | /* This matches "*return_adddi". */ | |
2922 | else if (GET_CODE (src) == PLUS | |
2923 | && arith_double_operand (XEXP (src, 0), DImode) | |
2924 | && arith_double_operand (XEXP (src, 1), DImode) | |
2925 | && (register_operand (XEXP (src, 0), DImode) | |
2926 | || register_operand (XEXP (src, 1), DImode))) | |
795068a4 | 2927 | return 1; |
795068a4 | 2928 | |
e48addee JJ |
2929 | /* This can match "*return_losum_[sd]i". |
2930 | Catch only some cases, so that return_losum* don't have | |
2931 | to be too big. */ | |
2932 | else if (GET_CODE (src) == LO_SUM | |
2933 | && ! TARGET_CM_MEDMID | |
2934 | && ((register_operand (XEXP (src, 0), SImode) | |
2935 | && immediate_operand (XEXP (src, 1), SImode)) | |
2936 | || (TARGET_ARCH64 | |
2937 | && register_operand (XEXP (src, 0), DImode) | |
2938 | && immediate_operand (XEXP (src, 1), DImode)))) | |
2939 | return 1; | |
2940 | ||
2941 | /* sll{,x} reg,1,reg2 is add reg,reg,reg2 as well. */ | |
2942 | else if (GET_CODE (src) == ASHIFT | |
2943 | && (register_operand (XEXP (src, 0), SImode) | |
2944 | || register_operand (XEXP (src, 0), DImode)) | |
2945 | && XEXP (src, 1) == const1_rtx) | |
2946 | return 1; | |
2947 | ||
795068a4 JW |
2948 | return 0; |
2949 | } | |
2950 | ||
7d167afd JJ |
2951 | /* Return nonzero if TRIAL can go into the sibling call |
2952 | delay slot. */ | |
2953 | ||
2954 | int | |
2955 | eligible_for_sibcall_delay (trial) | |
2956 | rtx trial; | |
2957 | { | |
2958 | rtx pat, src; | |
2959 | ||
2960 | if (GET_CODE (trial) != INSN || GET_CODE (PATTERN (trial)) != SET) | |
2961 | return 0; | |
2962 | ||
8456b95a | 2963 | if (get_attr_length (trial) != 1) |
7d167afd JJ |
2964 | return 0; |
2965 | ||
2966 | pat = PATTERN (trial); | |
2967 | ||
2968 | if (current_function_uses_only_leaf_regs) | |
2969 | { | |
2970 | /* If the tail call is done using the call instruction, | |
2971 | we have to restore %o7 in the delay slot. */ | |
2be5e524 | 2972 | if ((TARGET_ARCH64 && ! TARGET_CM_MEDLOW) || flag_pic) |
7d167afd JJ |
2973 | return 0; |
2974 | ||
2975 | /* %g1 is used to build the function address */ | |
2976 | if (reg_mentioned_p (gen_rtx_REG (Pmode, 1), pat)) | |
2977 | return 0; | |
2978 | ||
2979 | return 1; | |
2980 | } | |
2981 | ||
2982 | /* Otherwise, only operations which can be done in tandem with | |
2983 | a `restore' insn can go into the delay slot. */ | |
2984 | if (GET_CODE (SET_DEST (pat)) != REG | |
2985 | || REGNO (SET_DEST (pat)) < 24 | |
2986 | || REGNO (SET_DEST (pat)) >= 32) | |
2987 | return 0; | |
2988 | ||
2989 | /* If it mentions %o7, it can't go in, because sibcall will clobber it | |
2990 | in most cases. */ | |
2991 | if (reg_mentioned_p (gen_rtx_REG (Pmode, 15), pat)) | |
2992 | return 0; | |
2993 | ||
2994 | src = SET_SRC (pat); | |
2995 | ||
3ec6f1a9 RK |
2996 | if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT |
2997 | && arith_operand (src, GET_MODE (src))) | |
7d167afd JJ |
2998 | { |
2999 | if (TARGET_ARCH64) | |
3000 | return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode); | |
3001 | else | |
3002 | return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (SImode); | |
3003 | } | |
3004 | ||
3ec6f1a9 RK |
3005 | else if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT |
3006 | && arith_double_operand (src, GET_MODE (src))) | |
7d167afd JJ |
3007 | return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode); |
3008 | ||
3009 | else if (! TARGET_FPU && restore_operand (SET_DEST (pat), SFmode) | |
3010 | && register_operand (src, SFmode)) | |
3011 | return 1; | |
3012 | ||
3013 | else if (GET_CODE (src) == PLUS | |
3014 | && arith_operand (XEXP (src, 0), SImode) | |
3015 | && arith_operand (XEXP (src, 1), SImode) | |
3016 | && (register_operand (XEXP (src, 0), SImode) | |
3017 | || register_operand (XEXP (src, 1), SImode))) | |
3018 | return 1; | |
3019 | ||
3020 | else if (GET_CODE (src) == PLUS | |
3021 | && arith_double_operand (XEXP (src, 0), DImode) | |
3022 | && arith_double_operand (XEXP (src, 1), DImode) | |
3023 | && (register_operand (XEXP (src, 0), DImode) | |
3024 | || register_operand (XEXP (src, 1), DImode))) | |
3025 | return 1; | |
3026 | ||
3027 | else if (GET_CODE (src) == LO_SUM | |
3028 | && ! TARGET_CM_MEDMID | |
3029 | && ((register_operand (XEXP (src, 0), SImode) | |
3030 | && immediate_operand (XEXP (src, 1), SImode)) | |
3031 | || (TARGET_ARCH64 | |
3032 | && register_operand (XEXP (src, 0), DImode) | |
3033 | && immediate_operand (XEXP (src, 1), DImode)))) | |
3034 | return 1; | |
3035 | ||
3036 | else if (GET_CODE (src) == ASHIFT | |
3037 | && (register_operand (XEXP (src, 0), SImode) | |
3038 | || register_operand (XEXP (src, 0), DImode)) | |
3039 | && XEXP (src, 1) == const1_rtx) | |
3040 | return 1; | |
3041 | ||
3042 | return 0; | |
3043 | } | |
3044 | ||
e0d80184 DM |
3045 | static int |
3046 | check_return_regs (x) | |
3047 | rtx x; | |
ab835497 | 3048 | { |
e0d80184 DM |
3049 | switch (GET_CODE (x)) |
3050 | { | |
3051 | case REG: | |
3052 | return IN_OR_GLOBAL_P (x); | |
ab835497 | 3053 | |
e0d80184 DM |
3054 | case CONST_INT: |
3055 | case CONST_DOUBLE: | |
3056 | case CONST: | |
3057 | case SYMBOL_REF: | |
3058 | case LABEL_REF: | |
3059 | return 1; | |
ab835497 | 3060 | |
e0d80184 DM |
3061 | case SET: |
3062 | case IOR: | |
3063 | case AND: | |
3064 | case XOR: | |
3065 | case PLUS: | |
3066 | case MINUS: | |
3067 | if (check_return_regs (XEXP (x, 1)) == 0) | |
3068 | return 0; | |
3069 | case NOT: | |
3070 | case NEG: | |
3071 | case MEM: | |
3072 | return check_return_regs (XEXP (x, 0)); | |
3073 | ||
3074 | default: | |
3075 | return 0; | |
3076 | } | |
ab835497 | 3077 | |
e0d80184 | 3078 | } |
ab835497 | 3079 | |
e0d80184 DM |
3080 | int |
3081 | short_branch (uid1, uid2) | |
3082 | int uid1, uid2; | |
3083 | { | |
9d98a694 | 3084 | int delta = INSN_ADDRESSES (uid1) - INSN_ADDRESSES (uid2); |
77b91512 RK |
3085 | |
3086 | /* Leave a few words of "slop". */ | |
3087 | if (delta >= -1023 && delta <= 1022) | |
e0d80184 | 3088 | return 1; |
77b91512 | 3089 | |
e0d80184 DM |
3090 | return 0; |
3091 | } | |
ab835497 | 3092 | |
5e7a8ee0 | 3093 | /* Return nonzero if REG is not used after INSN. |
e0d80184 DM |
3094 | We assume REG is a reload reg, and therefore does |
3095 | not live past labels or calls or jumps. */ | |
3096 | int | |
3097 | reg_unused_after (reg, insn) | |
3098 | rtx reg; | |
3099 | rtx insn; | |
3100 | { | |
3101 | enum rtx_code code, prev_code = UNKNOWN; | |
ab835497 | 3102 | |
e0d80184 | 3103 | while ((insn = NEXT_INSN (insn))) |
61a55e8b | 3104 | { |
e0d80184 DM |
3105 | if (prev_code == CALL_INSN && call_used_regs[REGNO (reg)]) |
3106 | return 1; | |
ab835497 | 3107 | |
e0d80184 DM |
3108 | code = GET_CODE (insn); |
3109 | if (GET_CODE (insn) == CODE_LABEL) | |
3110 | return 1; | |
bc961ed7 | 3111 | |
e0d80184 | 3112 | if (GET_RTX_CLASS (code) == 'i') |
61a55e8b | 3113 | { |
e0d80184 DM |
3114 | rtx set = single_set (insn); |
3115 | int in_src = set && reg_overlap_mentioned_p (reg, SET_SRC (set)); | |
3116 | if (set && in_src) | |
3117 | return 0; | |
3118 | if (set && reg_overlap_mentioned_p (reg, SET_DEST (set))) | |
3119 | return 1; | |
3120 | if (set == 0 && reg_overlap_mentioned_p (reg, PATTERN (insn))) | |
3121 | return 0; | |
61a55e8b | 3122 | } |
e0d80184 | 3123 | prev_code = code; |
61a55e8b | 3124 | } |
e0d80184 DM |
3125 | return 1; |
3126 | } | |
3127 | \f | |
3128 | /* The table we use to reference PIC data. */ | |
e2500fed | 3129 | static GTY(()) rtx global_offset_table; |
bc961ed7 | 3130 | |
e0d80184 | 3131 | /* The function we use to get at it. */ |
e2500fed | 3132 | static GTY(()) rtx get_pc_symbol; |
e0d80184 | 3133 | static char get_pc_symbol_name[256]; |
ab835497 | 3134 | |
e0d80184 | 3135 | /* Ensure that we are not using patterns that are not OK with PIC. */ |
795068a4 | 3136 | |
e0d80184 DM |
3137 | int |
3138 | check_pic (i) | |
3139 | int i; | |
3140 | { | |
3141 | switch (flag_pic) | |
ab835497 | 3142 | { |
e0d80184 | 3143 | case 1: |
1ccbefce RH |
3144 | if (GET_CODE (recog_data.operand[i]) == SYMBOL_REF |
3145 | || (GET_CODE (recog_data.operand[i]) == CONST | |
3146 | && ! (GET_CODE (XEXP (recog_data.operand[i], 0)) == MINUS | |
3147 | && (XEXP (XEXP (recog_data.operand[i], 0), 0) | |
e0d80184 | 3148 | == global_offset_table) |
1ccbefce | 3149 | && (GET_CODE (XEXP (XEXP (recog_data.operand[i], 0), 1)) |
e0d80184 DM |
3150 | == CONST)))) |
3151 | abort (); | |
3152 | case 2: | |
3153 | default: | |
3154 | return 1; | |
ab835497 | 3155 | } |
ab835497 | 3156 | } |
795068a4 | 3157 | |
e0d80184 DM |
3158 | /* Return true if X is an address which needs a temporary register when |
3159 | reloaded while generating PIC code. */ | |
795068a4 | 3160 | |
e0d80184 DM |
3161 | int |
3162 | pic_address_needs_scratch (x) | |
3163 | rtx x; | |
795068a4 | 3164 | { |
e0d80184 DM |
3165 | /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */ |
3166 | if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS | |
3167 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF | |
3168 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT | |
3169 | && ! SMALL_INT (XEXP (XEXP (x, 0), 1))) | |
3170 | return 1; | |
795068a4 | 3171 | |
e0d80184 DM |
3172 | return 0; |
3173 | } | |
795068a4 | 3174 | |
e0d80184 DM |
3175 | /* Legitimize PIC addresses. If the address is already position-independent, |
3176 | we return ORIG. Newly generated position-independent addresses go into a | |
88cad84b | 3177 | reg. This is REG if nonzero, otherwise we allocate register(s) as |
e0d80184 | 3178 | necessary. */ |
795068a4 | 3179 | |
e0d80184 DM |
3180 | rtx |
3181 | legitimize_pic_address (orig, mode, reg) | |
3182 | rtx orig; | |
3183 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
3184 | rtx reg; | |
3185 | { | |
3186 | if (GET_CODE (orig) == SYMBOL_REF) | |
82d6b402 | 3187 | { |
e0d80184 DM |
3188 | rtx pic_ref, address; |
3189 | rtx insn; | |
82d6b402 | 3190 | |
e0d80184 | 3191 | if (reg == 0) |
82d6b402 | 3192 | { |
e0d80184 DM |
3193 | if (reload_in_progress || reload_completed) |
3194 | abort (); | |
3195 | else | |
3196 | reg = gen_reg_rtx (Pmode); | |
82d6b402 | 3197 | } |
795068a4 | 3198 | |
e0d80184 | 3199 | if (flag_pic == 2) |
4fb4e4b8 | 3200 | { |
e0d80184 DM |
3201 | /* If not during reload, allocate another temp reg here for loading |
3202 | in the address, so that these instructions can be optimized | |
3203 | properly. */ | |
3204 | rtx temp_reg = ((reload_in_progress || reload_completed) | |
3205 | ? reg : gen_reg_rtx (Pmode)); | |
3206 | ||
3207 | /* Must put the SYMBOL_REF inside an UNSPEC here so that cse | |
3208 | won't get confused into thinking that these two instructions | |
3209 | are loading in the true address of the symbol. If in the | |
3210 | future a PIC rtx exists, that should be used instead. */ | |
be3f1ff5 DM |
3211 | if (Pmode == SImode) |
3212 | { | |
3213 | emit_insn (gen_movsi_high_pic (temp_reg, orig)); | |
3214 | emit_insn (gen_movsi_lo_sum_pic (temp_reg, temp_reg, orig)); | |
3215 | } | |
3216 | else | |
3217 | { | |
3218 | emit_insn (gen_movdi_high_pic (temp_reg, orig)); | |
3219 | emit_insn (gen_movdi_lo_sum_pic (temp_reg, temp_reg, orig)); | |
3220 | } | |
e0d80184 | 3221 | address = temp_reg; |
4fb4e4b8 DE |
3222 | } |
3223 | else | |
e0d80184 DM |
3224 | address = orig; |
3225 | ||
3226 | pic_ref = gen_rtx_MEM (Pmode, | |
8ac61af7 RK |
3227 | gen_rtx_PLUS (Pmode, |
3228 | pic_offset_table_rtx, address)); | |
e0d80184 DM |
3229 | current_function_uses_pic_offset_table = 1; |
3230 | RTX_UNCHANGING_P (pic_ref) = 1; | |
3231 | insn = emit_move_insn (reg, pic_ref); | |
3232 | /* Put a REG_EQUAL note on this insn, so that it can be optimized | |
3233 | by loop. */ | |
3234 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, orig, | |
3235 | REG_NOTES (insn)); | |
3236 | return reg; | |
795068a4 | 3237 | } |
e0d80184 | 3238 | else if (GET_CODE (orig) == CONST) |
795068a4 | 3239 | { |
e0d80184 | 3240 | rtx base, offset; |
795068a4 | 3241 | |
e0d80184 DM |
3242 | if (GET_CODE (XEXP (orig, 0)) == PLUS |
3243 | && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx) | |
3244 | return orig; | |
82d6b402 | 3245 | |
e0d80184 | 3246 | if (reg == 0) |
4fb4e4b8 | 3247 | { |
e0d80184 DM |
3248 | if (reload_in_progress || reload_completed) |
3249 | abort (); | |
3250 | else | |
3251 | reg = gen_reg_rtx (Pmode); | |
4fb4e4b8 | 3252 | } |
e0d80184 DM |
3253 | |
3254 | if (GET_CODE (XEXP (orig, 0)) == PLUS) | |
4fb4e4b8 | 3255 | { |
e0d80184 DM |
3256 | base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg); |
3257 | offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode, | |
3258 | base == reg ? 0 : reg); | |
4fb4e4b8 DE |
3259 | } |
3260 | else | |
61a66555 JW |
3261 | abort (); |
3262 | ||
e0d80184 DM |
3263 | if (GET_CODE (offset) == CONST_INT) |
3264 | { | |
3265 | if (SMALL_INT (offset)) | |
ed8908e7 | 3266 | return plus_constant (base, INTVAL (offset)); |
e0d80184 DM |
3267 | else if (! reload_in_progress && ! reload_completed) |
3268 | offset = force_reg (Pmode, offset); | |
3269 | else | |
3270 | /* If we reach here, then something is seriously wrong. */ | |
3271 | abort (); | |
3272 | } | |
3273 | return gen_rtx_PLUS (Pmode, base, offset); | |
795068a4 | 3274 | } |
e0d80184 DM |
3275 | else if (GET_CODE (orig) == LABEL_REF) |
3276 | /* ??? Why do we do this? */ | |
3277 | /* Now movsi_pic_label_ref uses it, but we ought to be checking that | |
3278 | the register is live instead, in case it is eliminated. */ | |
3279 | current_function_uses_pic_offset_table = 1; | |
795068a4 | 3280 | |
e0d80184 DM |
3281 | return orig; |
3282 | } | |
795068a4 | 3283 | |
fccf9848 | 3284 | /* Emit special PIC prologues. */ |
795068a4 | 3285 | |
e0d80184 | 3286 | void |
fccf9848 | 3287 | load_pic_register () |
e0d80184 DM |
3288 | { |
3289 | /* Labels to get the PC in the prologue of this function. */ | |
3290 | int orig_flag_pic = flag_pic; | |
4fb4e4b8 | 3291 | |
e0d80184 DM |
3292 | if (! flag_pic) |
3293 | abort (); | |
3294 | ||
d6a7951f | 3295 | /* If we haven't emitted the special get_pc helper function, do so now. */ |
e0d80184 | 3296 | if (get_pc_symbol_name[0] == 0) |
4fb4e4b8 | 3297 | { |
d676da68 | 3298 | int align; |
82d6b402 | 3299 | |
d676da68 | 3300 | ASM_GENERATE_INTERNAL_LABEL (get_pc_symbol_name, "LGETPC", 0); |
e0d80184 | 3301 | text_section (); |
d676da68 DM |
3302 | |
3303 | align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT); | |
3304 | if (align > 0) | |
3305 | ASM_OUTPUT_ALIGN (asm_out_file, align); | |
4977bab6 | 3306 | (*targetm.asm_out.internal_label) (asm_out_file, "LGETPC", 0); |
4df1190a | 3307 | fputs ("\tretl\n\tadd\t%o7, %l7, %l7\n", asm_out_file); |
e0d80184 | 3308 | } |
82d6b402 | 3309 | |
e0d80184 DM |
3310 | /* Initialize every time through, since we can't easily |
3311 | know this to be permanent. */ | |
3312 | global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_"); | |
3313 | get_pc_symbol = gen_rtx_SYMBOL_REF (Pmode, get_pc_symbol_name); | |
3314 | flag_pic = 0; | |
82d6b402 | 3315 | |
fccf9848 JJ |
3316 | emit_insn (gen_get_pc (pic_offset_table_rtx, global_offset_table, |
3317 | get_pc_symbol)); | |
82d6b402 | 3318 | |
e0d80184 | 3319 | flag_pic = orig_flag_pic; |
82d6b402 | 3320 | |
e0d80184 DM |
3321 | /* Need to emit this whether or not we obey regdecls, |
3322 | since setjmp/longjmp can cause life info to screw up. | |
3323 | ??? In the case where we don't obey regdecls, this is not sufficient | |
3324 | since we may not fall out the bottom. */ | |
3325 | emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx)); | |
795068a4 | 3326 | } |
ab835497 | 3327 | \f |
e0d80184 | 3328 | /* Return 1 if RTX is a MEM which is known to be aligned to at |
7a31a340 | 3329 | least a DESIRED byte boundary. */ |
a3ee5899 | 3330 | |
e0d80184 DM |
3331 | int |
3332 | mem_min_alignment (mem, desired) | |
3333 | rtx mem; | |
3334 | int desired; | |
ab835497 | 3335 | { |
e0d80184 DM |
3336 | rtx addr, base, offset; |
3337 | ||
3338 | /* If it's not a MEM we can't accept it. */ | |
3339 | if (GET_CODE (mem) != MEM) | |
3340 | return 0; | |
3341 | ||
3342 | addr = XEXP (mem, 0); | |
3343 | base = offset = NULL_RTX; | |
3344 | if (GET_CODE (addr) == PLUS) | |
ab835497 | 3345 | { |
e0d80184 | 3346 | if (GET_CODE (XEXP (addr, 0)) == REG) |
61a55e8b | 3347 | { |
e0d80184 DM |
3348 | base = XEXP (addr, 0); |
3349 | ||
3350 | /* What we are saying here is that if the base | |
3351 | REG is aligned properly, the compiler will make | |
3352 | sure any REG based index upon it will be so | |
3353 | as well. */ | |
3354 | if (GET_CODE (XEXP (addr, 1)) == CONST_INT) | |
3355 | offset = XEXP (addr, 1); | |
61a55e8b | 3356 | else |
e0d80184 | 3357 | offset = const0_rtx; |
61a55e8b | 3358 | } |
ab835497 | 3359 | } |
e0d80184 | 3360 | else if (GET_CODE (addr) == REG) |
ab835497 | 3361 | { |
e0d80184 DM |
3362 | base = addr; |
3363 | offset = const0_rtx; | |
ab835497 | 3364 | } |
82d6b402 | 3365 | |
e0d80184 | 3366 | if (base != NULL_RTX) |
795068a4 | 3367 | { |
e0d80184 DM |
3368 | int regno = REGNO (base); |
3369 | ||
563c12b0 | 3370 | if (regno != HARD_FRAME_POINTER_REGNUM && regno != STACK_POINTER_REGNUM) |
61a55e8b | 3371 | { |
e0d80184 DM |
3372 | /* Check if the compiler has recorded some information |
3373 | about the alignment of the base REG. If reload has | |
021e2ecc JJ |
3374 | completed, we already matched with proper alignments. |
3375 | If not running global_alloc, reload might give us | |
3376 | unaligned pointer to local stack though. */ | |
bdb429a5 RK |
3377 | if (((cfun != 0 |
3378 | && REGNO_POINTER_ALIGN (regno) >= desired * BITS_PER_UNIT) | |
021e2ecc | 3379 | || (optimize && reload_completed)) |
bdb429a5 | 3380 | && (INTVAL (offset) & (desired - 1)) == 0) |
e0d80184 | 3381 | return 1; |
61a55e8b | 3382 | } |
795068a4 | 3383 | else |
e0d80184 DM |
3384 | { |
3385 | if (((INTVAL (offset) - SPARC_STACK_BIAS) & (desired - 1)) == 0) | |
3386 | return 1; | |
3387 | } | |
795068a4 | 3388 | } |
e0d80184 DM |
3389 | else if (! TARGET_UNALIGNED_DOUBLES |
3390 | || CONSTANT_P (addr) | |
3391 | || GET_CODE (addr) == LO_SUM) | |
795068a4 | 3392 | { |
e0d80184 DM |
3393 | /* Anything else we know is properly aligned unless TARGET_UNALIGNED_DOUBLES |
3394 | is true, in which case we can only assume that an access is aligned if | |
3395 | it is to a constant address, or the address involves a LO_SUM. */ | |
3396 | return 1; | |
795068a4 | 3397 | } |
e0d80184 DM |
3398 | |
3399 | /* An obviously unaligned address. */ | |
3400 | return 0; | |
795068a4 | 3401 | } |
e0d80184 | 3402 | |
ab835497 | 3403 | \f |
61a55e8b | 3404 | /* Vectors to keep interesting information about registers where it can easily |
01d3224a | 3405 | be got. We used to use the actual mode value as the bit number, but there |
61a55e8b DE |
3406 | are more than 32 modes now. Instead we use two tables: one indexed by |
3407 | hard register number, and one indexed by mode. */ | |
3408 | ||
3409 | /* The purpose of sparc_mode_class is to shrink the range of modes so that | |
3410 | they all fit (as bit numbers) in a 32 bit word (again). Each real mode is | |
3411 | mapped into one sparc_mode_class mode. */ | |
3412 | ||
3413 | enum sparc_mode_class { | |
61a55e8b | 3414 | S_MODE, D_MODE, T_MODE, O_MODE, |
c4ce6853 DE |
3415 | SF_MODE, DF_MODE, TF_MODE, OF_MODE, |
3416 | CC_MODE, CCFP_MODE | |
61a55e8b | 3417 | }; |
ab835497 | 3418 | |
61a55e8b DE |
3419 | /* Modes for single-word and smaller quantities. */ |
3420 | #define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE)) | |
3421 | ||
3422 | /* Modes for double-word and smaller quantities. */ | |
3423 | #define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE)) | |
3424 | ||
3425 | /* Modes for quad-word and smaller quantities. */ | |
3426 | #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE)) | |
ab835497 | 3427 | |
d0cee9ba JJ |
3428 | /* Modes for 8-word and smaller quantities. */ |
3429 | #define O_MODES (T_MODES | (1 << (int) O_MODE) | (1 << (int) OF_MODE)) | |
3430 | ||
1e4eb8d1 JW |
3431 | /* Modes for single-float quantities. We must allow any single word or |
3432 | smaller quantity. This is because the fix/float conversion instructions | |
3433 | take integer inputs/outputs from the float registers. */ | |
3434 | #define SF_MODES (S_MODES) | |
ab835497 | 3435 | |
61a55e8b DE |
3436 | /* Modes for double-float and smaller quantities. */ |
3437 | #define DF_MODES (S_MODES | D_MODES) | |
3438 | ||
61a55e8b | 3439 | /* Modes for double-float only quantities. */ |
38875aba | 3440 | #define DF_MODES_NO_S ((1 << (int) D_MODE) | (1 << (int) DF_MODE)) |
ab835497 | 3441 | |
61a55e8b DE |
3442 | /* Modes for quad-float only quantities. */ |
3443 | #define TF_ONLY_MODES (1 << (int) TF_MODE) | |
3444 | ||
3445 | /* Modes for quad-float and smaller quantities. */ | |
3446 | #define TF_MODES (DF_MODES | TF_ONLY_MODES) | |
3447 | ||
d0cee9ba JJ |
3448 | /* Modes for quad-float and double-float quantities. */ |
3449 | #define TF_MODES_NO_S (DF_MODES_NO_S | TF_ONLY_MODES) | |
3450 | ||
3451 | /* Modes for quad-float pair only quantities. */ | |
3452 | #define OF_ONLY_MODES (1 << (int) OF_MODE) | |
3453 | ||
3454 | /* Modes for quad-float pairs and smaller quantities. */ | |
3455 | #define OF_MODES (TF_MODES | OF_ONLY_MODES) | |
3456 | ||
3457 | #define OF_MODES_NO_S (TF_MODES_NO_S | OF_ONLY_MODES) | |
ab835497 | 3458 | |
c4ce6853 DE |
3459 | /* Modes for condition codes. */ |
3460 | #define CC_MODES (1 << (int) CC_MODE) | |
3461 | #define CCFP_MODES (1 << (int) CCFP_MODE) | |
3462 | ||
ab835497 RK |
3463 | /* Value is 1 if register/mode pair is acceptable on sparc. |
3464 | The funny mixture of D and T modes is because integer operations | |
3465 | do not specially operate on tetra quantities, so non-quad-aligned | |
3466 | registers can hold quadword quantities (except %o4 and %i4 because | |
c4ce6853 | 3467 | they cross fixed registers). */ |
ab835497 | 3468 | |
61a55e8b | 3469 | /* This points to either the 32 bit or the 64 bit version. */ |
0b5826ac | 3470 | const int *hard_regno_mode_classes; |
61a55e8b | 3471 | |
0b5826ac | 3472 | static const int hard_32bit_mode_classes[] = { |
c4ce6853 | 3473 | S_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, |
ab835497 RK |
3474 | T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES, |
3475 | T_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, | |
3476 | T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES, | |
3477 | ||
d0cee9ba JJ |
3478 | OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES, |
3479 | OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES, | |
3480 | OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES, | |
3481 | OF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES, | |
a9e27770 DE |
3482 | |
3483 | /* FP regs f32 to f63. Only the even numbered registers actually exist, | |
3484 | and none can hold SFmode/SImode values. */ | |
d0cee9ba JJ |
3485 | OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, |
3486 | OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, | |
3487 | OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, | |
3488 | OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, TF_MODES_NO_S, 0, DF_MODES_NO_S, 0, | |
a9e27770 DE |
3489 | |
3490 | /* %fcc[0123] */ | |
c4ce6853 DE |
3491 | CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES, |
3492 | ||
3493 | /* %icc */ | |
3494 | CC_MODES | |
61a55e8b DE |
3495 | }; |
3496 | ||
0b5826ac | 3497 | static const int hard_64bit_mode_classes[] = { |
c4ce6853 | 3498 | D_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, |
d0cee9ba | 3499 | O_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, |
61a55e8b | 3500 | T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, |
d0cee9ba | 3501 | O_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, |
61a55e8b | 3502 | |
d0cee9ba JJ |
3503 | OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES, |
3504 | OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES, | |
3505 | OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES, | |
3506 | OF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES, | |
61a55e8b | 3507 | |
a9e27770 | 3508 | /* FP regs f32 to f63. Only the even numbered registers actually exist, |
61a55e8b | 3509 | and none can hold SFmode/SImode values. */ |
d0cee9ba JJ |
3510 | OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, |
3511 | OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, | |
3512 | OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, | |
3513 | OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, TF_MODES_NO_S, 0, DF_MODES_NO_S, 0, | |
61a55e8b DE |
3514 | |
3515 | /* %fcc[0123] */ | |
c4ce6853 DE |
3516 | CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES, |
3517 | ||
3518 | /* %icc */ | |
3519 | CC_MODES | |
61a55e8b DE |
3520 | }; |
3521 | ||
3522 | int sparc_mode_class [NUM_MACHINE_MODES]; | |
3523 | ||
c4ce6853 DE |
3524 | enum reg_class sparc_regno_reg_class[FIRST_PSEUDO_REGISTER]; |
3525 | ||
61a55e8b DE |
3526 | static void |
3527 | sparc_init_modes () | |
3528 | { | |
3529 | int i; | |
3530 | ||
61a55e8b DE |
3531 | for (i = 0; i < NUM_MACHINE_MODES; i++) |
3532 | { | |
3533 | switch (GET_MODE_CLASS (i)) | |
3534 | { | |
3535 | case MODE_INT: | |
3536 | case MODE_PARTIAL_INT: | |
3537 | case MODE_COMPLEX_INT: | |
3538 | if (GET_MODE_SIZE (i) <= 4) | |
3539 | sparc_mode_class[i] = 1 << (int) S_MODE; | |
3540 | else if (GET_MODE_SIZE (i) == 8) | |
3541 | sparc_mode_class[i] = 1 << (int) D_MODE; | |
3542 | else if (GET_MODE_SIZE (i) == 16) | |
3543 | sparc_mode_class[i] = 1 << (int) T_MODE; | |
3544 | else if (GET_MODE_SIZE (i) == 32) | |
3545 | sparc_mode_class[i] = 1 << (int) O_MODE; | |
3546 | else | |
3547 | sparc_mode_class[i] = 0; | |
3548 | break; | |
3549 | case MODE_FLOAT: | |
3550 | case MODE_COMPLEX_FLOAT: | |
3551 | if (GET_MODE_SIZE (i) <= 4) | |
3552 | sparc_mode_class[i] = 1 << (int) SF_MODE; | |
3553 | else if (GET_MODE_SIZE (i) == 8) | |
3554 | sparc_mode_class[i] = 1 << (int) DF_MODE; | |
3555 | else if (GET_MODE_SIZE (i) == 16) | |
3556 | sparc_mode_class[i] = 1 << (int) TF_MODE; | |
3557 | else if (GET_MODE_SIZE (i) == 32) | |
3558 | sparc_mode_class[i] = 1 << (int) OF_MODE; | |
3559 | else | |
3560 | sparc_mode_class[i] = 0; | |
3561 | break; | |
3562 | case MODE_CC: | |
3563 | default: | |
3564 | /* mode_class hasn't been initialized yet for EXTRA_CC_MODES, so | |
3565 | we must explicitly check for them here. */ | |
3566 | if (i == (int) CCFPmode || i == (int) CCFPEmode) | |
3567 | sparc_mode_class[i] = 1 << (int) CCFP_MODE; | |
3568 | else if (i == (int) CCmode || i == (int) CC_NOOVmode | |
a9e27770 | 3569 | || i == (int) CCXmode || i == (int) CCX_NOOVmode) |
c4ce6853 | 3570 | sparc_mode_class[i] = 1 << (int) CC_MODE; |
61a55e8b DE |
3571 | else |
3572 | sparc_mode_class[i] = 0; | |
3573 | break; | |
3574 | } | |
3575 | } | |
3576 | ||
a9e27770 | 3577 | if (TARGET_ARCH64) |
61a55e8b DE |
3578 | hard_regno_mode_classes = hard_64bit_mode_classes; |
3579 | else | |
3580 | hard_regno_mode_classes = hard_32bit_mode_classes; | |
c4ce6853 DE |
3581 | |
3582 | /* Initialize the array used by REGNO_REG_CLASS. */ | |
3583 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
3584 | { | |
284d86e9 JC |
3585 | if (i < 16 && TARGET_V8PLUS) |
3586 | sparc_regno_reg_class[i] = I64_REGS; | |
563c12b0 | 3587 | else if (i < 32 || i == FRAME_POINTER_REGNUM) |
c4ce6853 DE |
3588 | sparc_regno_reg_class[i] = GENERAL_REGS; |
3589 | else if (i < 64) | |
3590 | sparc_regno_reg_class[i] = FP_REGS; | |
3591 | else if (i < 96) | |
3592 | sparc_regno_reg_class[i] = EXTRA_FP_REGS; | |
3593 | else if (i < 100) | |
3594 | sparc_regno_reg_class[i] = FPCC_REGS; | |
3595 | else | |
3596 | sparc_regno_reg_class[i] = NO_REGS; | |
3597 | } | |
61a55e8b | 3598 | } |
ab835497 | 3599 | \f |
61a55e8b DE |
3600 | /* Save non call used registers from LOW to HIGH at BASE+OFFSET. |
3601 | N_REGS is the number of 4-byte regs saved thus far. This applies even to | |
3602 | v9 int regs as it simplifies the code. */ | |
3603 | ||
ab835497 | 3604 | static int |
c53aa195 | 3605 | save_regs (file, low, high, base, offset, n_regs, real_offset) |
ab835497 RK |
3606 | FILE *file; |
3607 | int low, high; | |
3bb5de61 | 3608 | const char *base; |
ab835497 | 3609 | int offset; |
61a55e8b | 3610 | int n_regs; |
c53aa195 | 3611 | int real_offset; |
ab835497 RK |
3612 | { |
3613 | int i; | |
3614 | ||
a9e27770 | 3615 | if (TARGET_ARCH64 && high <= 32) |
ab835497 | 3616 | { |
61a55e8b DE |
3617 | for (i = low; i < high; i++) |
3618 | { | |
3619 | if (regs_ever_live[i] && ! call_used_regs[i]) | |
c53aa195 | 3620 | { |
e0d80184 | 3621 | fprintf (file, "\tstx\t%s, [%s+%d]\n", |
c53aa195 | 3622 | reg_names[i], base, offset + 4 * n_regs); |
0021b564 | 3623 | if (dwarf2out_do_frame ()) |
c53aa195 | 3624 | dwarf2out_reg_save ("", i, real_offset + 4 * n_regs); |
c53aa195 JM |
3625 | n_regs += 2; |
3626 | } | |
61a55e8b | 3627 | } |
ab835497 | 3628 | } |
61a55e8b DE |
3629 | else |
3630 | { | |
3631 | for (i = low; i < high; i += 2) | |
3632 | { | |
3633 | if (regs_ever_live[i] && ! call_used_regs[i]) | |
c53aa195 | 3634 | { |
5e9defae KG |
3635 | if (regs_ever_live[i+1] && ! call_used_regs[i+1]) |
3636 | { | |
e0d80184 | 3637 | fprintf (file, "\tstd\t%s, [%s+%d]\n", |
5e9defae KG |
3638 | reg_names[i], base, offset + 4 * n_regs); |
3639 | if (dwarf2out_do_frame ()) | |
3640 | { | |
3641 | char *l = dwarf2out_cfi_label (); | |
3642 | dwarf2out_reg_save (l, i, real_offset + 4 * n_regs); | |
3643 | dwarf2out_reg_save (l, i+1, real_offset + 4 * n_regs + 4); | |
3644 | } | |
3645 | n_regs += 2; | |
3646 | } | |
3647 | else | |
3648 | { | |
e0d80184 | 3649 | fprintf (file, "\tst\t%s, [%s+%d]\n", |
5e9defae KG |
3650 | reg_names[i], base, offset + 4 * n_regs); |
3651 | if (dwarf2out_do_frame ()) | |
3652 | dwarf2out_reg_save ("", i, real_offset + 4 * n_regs); | |
3653 | n_regs += 2; | |
3654 | } | |
3655 | } | |
3656 | else | |
3657 | { | |
3658 | if (regs_ever_live[i+1] && ! call_used_regs[i+1]) | |
3659 | { | |
e0d80184 | 3660 | fprintf (file, "\tst\t%s, [%s+%d]\n", |
5e9defae KG |
3661 | reg_names[i+1], base, offset + 4 * n_regs + 4); |
3662 | if (dwarf2out_do_frame ()) | |
3663 | dwarf2out_reg_save ("", i + 1, real_offset + 4 * n_regs + 4); | |
3664 | n_regs += 2; | |
3665 | } | |
c53aa195 | 3666 | } |
61a55e8b DE |
3667 | } |
3668 | } | |
3669 | return n_regs; | |
ab835497 RK |
3670 | } |
3671 | ||
61a55e8b DE |
3672 | /* Restore non call used registers from LOW to HIGH at BASE+OFFSET. |
3673 | ||
3674 | N_REGS is the number of 4-byte regs saved thus far. This applies even to | |
3675 | v9 int regs as it simplifies the code. */ | |
3676 | ||
ab835497 | 3677 | static int |
61a55e8b | 3678 | restore_regs (file, low, high, base, offset, n_regs) |
ab835497 RK |
3679 | FILE *file; |
3680 | int low, high; | |
3bb5de61 | 3681 | const char *base; |
ab835497 | 3682 | int offset; |
61a55e8b | 3683 | int n_regs; |
ab835497 RK |
3684 | { |
3685 | int i; | |
3686 | ||
a9e27770 | 3687 | if (TARGET_ARCH64 && high <= 32) |
61a55e8b DE |
3688 | { |
3689 | for (i = low; i < high; i++) | |
3690 | { | |
3691 | if (regs_ever_live[i] && ! call_used_regs[i]) | |
e0d80184 | 3692 | fprintf (file, "\tldx\t[%s+%d], %s\n", |
61a55e8b DE |
3693 | base, offset + 4 * n_regs, reg_names[i]), |
3694 | n_regs += 2; | |
3695 | } | |
3696 | } | |
3697 | else | |
ab835497 | 3698 | { |
61a55e8b DE |
3699 | for (i = low; i < high; i += 2) |
3700 | { | |
3701 | if (regs_ever_live[i] && ! call_used_regs[i]) | |
3702 | if (regs_ever_live[i+1] && ! call_used_regs[i+1]) | |
e0d80184 | 3703 | fprintf (file, "\tldd\t[%s+%d], %s\n", |
61a55e8b DE |
3704 | base, offset + 4 * n_regs, reg_names[i]), |
3705 | n_regs += 2; | |
3706 | else | |
4df1190a | 3707 | fprintf (file, "\tld\t[%s+%d], %s\n", |
61a55e8b DE |
3708 | base, offset + 4 * n_regs, reg_names[i]), |
3709 | n_regs += 2; | |
3710 | else if (regs_ever_live[i+1] && ! call_used_regs[i+1]) | |
4df1190a | 3711 | fprintf (file, "\tld\t[%s+%d], %s\n", |
61a55e8b DE |
3712 | base, offset + 4 * n_regs + 4, reg_names[i+1]), |
3713 | n_regs += 2; | |
3714 | } | |
ab835497 | 3715 | } |
61a55e8b | 3716 | return n_regs; |
ab835497 RK |
3717 | } |
3718 | ||
61a55e8b DE |
3719 | /* Compute the frame size required by the function. This function is called |
3720 | during the reload pass and also by output_function_prologue(). */ | |
ab835497 | 3721 | |
ab835497 RK |
3722 | int |
3723 | compute_frame_size (size, leaf_function) | |
3724 | int size; | |
3725 | int leaf_function; | |
3726 | { | |
61a55e8b | 3727 | int n_regs = 0, i; |
ab835497 | 3728 | int outgoing_args_size = (current_function_outgoing_args_size |
4fb4e4b8 | 3729 | + REG_PARM_STACK_SPACE (current_function_decl)); |
ab835497 | 3730 | |
33074e5f RH |
3731 | /* N_REGS is the number of 4-byte regs saved thus far. This applies |
3732 | even to v9 int regs to be consistent with save_regs/restore_regs. */ | |
61a55e8b | 3733 | |
33074e5f RH |
3734 | if (TARGET_ARCH64) |
3735 | { | |
3736 | for (i = 0; i < 8; i++) | |
3737 | if (regs_ever_live[i] && ! call_used_regs[i]) | |
3738 | n_regs += 2; | |
3739 | } | |
3740 | else | |
3741 | { | |
3742 | for (i = 0; i < 8; i += 2) | |
ab835497 RK |
3743 | if ((regs_ever_live[i] && ! call_used_regs[i]) |
3744 | || (regs_ever_live[i+1] && ! call_used_regs[i+1])) | |
61a55e8b | 3745 | n_regs += 2; |
ab835497 RK |
3746 | } |
3747 | ||
33074e5f RH |
3748 | for (i = 32; i < (TARGET_V9 ? 96 : 64); i += 2) |
3749 | if ((regs_ever_live[i] && ! call_used_regs[i]) | |
3750 | || (regs_ever_live[i+1] && ! call_used_regs[i+1])) | |
3751 | n_regs += 2; | |
3752 | ||
ab835497 | 3753 | /* Set up values for use in `function_epilogue'. */ |
61a55e8b | 3754 | num_gfregs = n_regs; |
ab835497 | 3755 | |
61a55e8b DE |
3756 | if (leaf_function && n_regs == 0 |
3757 | && size == 0 && current_function_outgoing_args_size == 0) | |
3758 | { | |
3759 | actual_fsize = apparent_fsize = 0; | |
3760 | } | |
3761 | else | |
3762 | { | |
225909c3 JS |
3763 | /* We subtract STARTING_FRAME_OFFSET, remember it's negative. */ |
3764 | apparent_fsize = (size - STARTING_FRAME_OFFSET + 7) & -8; | |
61a55e8b DE |
3765 | apparent_fsize += n_regs * 4; |
3766 | actual_fsize = apparent_fsize + ((outgoing_args_size + 7) & -8); | |
3767 | } | |
ab835497 RK |
3768 | |
3769 | /* Make sure nothing can clobber our register windows. | |
3770 | If a SAVE must be done, or there is a stack-local variable, | |
61a55e8b | 3771 | the register window area must be allocated. |
4fb4e4b8 | 3772 | ??? For v8 we apparently need an additional 8 bytes of reserved space. */ |
ab835497 | 3773 | if (leaf_function == 0 || size > 0) |
4fb4e4b8 | 3774 | actual_fsize += (16 * UNITS_PER_WORD) + (TARGET_ARCH64 ? 0 : 8); |
ab835497 | 3775 | |
61a55e8b DE |
3776 | return SPARC_STACK_ALIGN (actual_fsize); |
3777 | } | |
3778 | ||
3779 | /* Build a (32 bit) big number in a register. */ | |
86735b02 | 3780 | /* ??? We may be able to use the set macro here too. */ |
61a55e8b DE |
3781 | |
3782 | static void | |
3783 | build_big_number (file, num, reg) | |
3784 | FILE *file; | |
3785 | int num; | |
3bb5de61 | 3786 | const char *reg; |
61a55e8b | 3787 | { |
a9e27770 | 3788 | if (num >= 0 || ! TARGET_ARCH64) |
61a55e8b | 3789 | { |
e0d80184 | 3790 | fprintf (file, "\tsethi\t%%hi(%d), %s\n", num, reg); |
61a55e8b | 3791 | if ((num & 0x3ff) != 0) |
e0d80184 | 3792 | fprintf (file, "\tor\t%s, %%lo(%d), %s\n", reg, num, reg); |
61a55e8b | 3793 | } |
a9e27770 | 3794 | else /* num < 0 && TARGET_ARCH64 */ |
61a55e8b DE |
3795 | { |
3796 | /* Sethi does not sign extend, so we must use a little trickery | |
3797 | to use it for negative numbers. Invert the constant before | |
3798 | loading it in, then use xor immediate to invert the loaded bits | |
3799 | (along with the upper 32 bits) to the desired constant. This | |
3800 | works because the sethi and immediate fields overlap. */ | |
3801 | int asize = num; | |
3802 | int inv = ~asize; | |
3803 | int low = -0x400 + (asize & 0x3FF); | |
3804 | ||
e0d80184 | 3805 | fprintf (file, "\tsethi\t%%hi(%d), %s\n\txor\t%s, %d, %s\n", |
61a55e8b DE |
3806 | inv, reg, reg, low, reg); |
3807 | } | |
ab835497 RK |
3808 | } |
3809 | ||
1cb36a98 RH |
3810 | /* Output any necessary .register pseudo-ops. */ |
3811 | void | |
3812 | sparc_output_scratch_registers (file) | |
fbd039b2 | 3813 | FILE *file ATTRIBUTE_UNUSED; |
1cb36a98 RH |
3814 | { |
3815 | #ifdef HAVE_AS_REGISTER_PSEUDO_OP | |
3816 | int i; | |
3817 | ||
3818 | if (TARGET_ARCH32) | |
3819 | return; | |
3820 | ||
3821 | /* Check if %g[2367] were used without | |
3822 | .register being printed for them already. */ | |
3823 | for (i = 2; i < 8; i++) | |
3824 | { | |
3825 | if (regs_ever_live [i] | |
3826 | && ! sparc_hard_reg_printed [i]) | |
3827 | { | |
3828 | sparc_hard_reg_printed [i] = 1; | |
3829 | fprintf (file, "\t.register\t%%g%d, #scratch\n", i); | |
3830 | } | |
3831 | if (i == 3) i = 5; | |
3832 | } | |
3833 | #endif | |
3834 | } | |
3835 | ||
08c148a8 NB |
3836 | /* This function generates the assembly code for function entry. |
3837 | FILE is a stdio stream to output the code to. | |
3838 | SIZE is an int: how many units of temporary storage to allocate. | |
3839 | Refer to the array `regs_ever_live' to determine which registers | |
3840 | to save; `regs_ever_live[I]' is nonzero if register number I | |
3841 | is ever used in the function. This macro is responsible for | |
3842 | knowing which registers should not be saved even if used. */ | |
3843 | ||
3844 | /* On SPARC, move-double insns between fpu and cpu need an 8-byte block | |
3845 | of memory. If any fpu reg is used in the function, we allocate | |
3846 | such a block here, at the bottom of the frame, just in case it's needed. | |
3847 | ||
3848 | If this function is a leaf procedure, then we may choose not | |
3849 | to do a "save" insn. The decision about whether or not | |
3850 | to do this is made in regclass.c. */ | |
3851 | ||
3852 | static void | |
3853 | sparc_output_function_prologue (file, size) | |
3854 | FILE *file; | |
3855 | HOST_WIDE_INT size; | |
3856 | { | |
3857 | if (TARGET_FLAT) | |
3858 | sparc_flat_function_prologue (file, size); | |
3859 | else | |
3860 | sparc_nonflat_function_prologue (file, size, | |
3861 | current_function_uses_only_leaf_regs); | |
3862 | } | |
3863 | ||
915f619f JW |
3864 | /* Output code for the function prologue. */ |
3865 | ||
08c148a8 NB |
3866 | static void |
3867 | sparc_nonflat_function_prologue (file, size, leaf_function) | |
ab835497 | 3868 | FILE *file; |
08c148a8 | 3869 | HOST_WIDE_INT size; |
915f619f | 3870 | int leaf_function; |
ab835497 | 3871 | { |
1cb36a98 RH |
3872 | sparc_output_scratch_registers (file); |
3873 | ||
915f619f JW |
3874 | /* Need to use actual_fsize, since we are also allocating |
3875 | space for our callee (and our own register save area). */ | |
ab835497 RK |
3876 | actual_fsize = compute_frame_size (size, leaf_function); |
3877 | ||
61a55e8b DE |
3878 | if (leaf_function) |
3879 | { | |
3880 | frame_base_name = "%sp"; | |
3881 | frame_base_offset = actual_fsize + SPARC_STACK_BIAS; | |
3882 | } | |
3883 | else | |
3884 | { | |
3885 | frame_base_name = "%fp"; | |
3886 | frame_base_offset = SPARC_STACK_BIAS; | |
3887 | } | |
3888 | ||
c6aa9ce1 | 3889 | /* This is only for the human reader. */ |
bf62bbf1 | 3890 | fprintf (file, "\t%s#PROLOGUE# 0\n", ASM_COMMENT_START); |
c6aa9ce1 | 3891 | |
915f619f JW |
3892 | if (actual_fsize == 0) |
3893 | /* do nothing. */ ; | |
e6c1be7e | 3894 | else if (! leaf_function) |
ab835497 | 3895 | { |
3592ea0d | 3896 | if (actual_fsize <= 4096) |
e0d80184 | 3897 | fprintf (file, "\tsave\t%%sp, -%d, %%sp\n", actual_fsize); |
3592ea0d | 3898 | else if (actual_fsize <= 8192) |
915f619f | 3899 | { |
e0d80184 DM |
3900 | fprintf (file, "\tsave\t%%sp, -4096, %%sp\n"); |
3901 | fprintf (file, "\tadd\t%%sp, -%d, %%sp\n", actual_fsize - 4096); | |
915f619f JW |
3902 | } |
3903 | else | |
3904 | { | |
3592ea0d | 3905 | build_big_number (file, -actual_fsize, "%g1"); |
e0d80184 | 3906 | fprintf (file, "\tsave\t%%sp, %%g1, %%sp\n"); |
915f619f | 3907 | } |
ab835497 | 3908 | } |
5f4241d5 DE |
3909 | else /* leaf function */ |
3910 | { | |
3592ea0d | 3911 | if (actual_fsize <= 4096) |
e0d80184 | 3912 | fprintf (file, "\tadd\t%%sp, -%d, %%sp\n", actual_fsize); |
3592ea0d DE |
3913 | else if (actual_fsize <= 8192) |
3914 | { | |
e0d80184 DM |
3915 | fprintf (file, "\tadd\t%%sp, -4096, %%sp\n"); |
3916 | fprintf (file, "\tadd\t%%sp, -%d, %%sp\n", actual_fsize - 4096); | |
3592ea0d | 3917 | } |
915f619f | 3918 | else |
3592ea0d DE |
3919 | { |
3920 | build_big_number (file, -actual_fsize, "%g1"); | |
e0d80184 | 3921 | fprintf (file, "\tadd\t%%sp, %%g1, %%sp\n"); |
3592ea0d | 3922 | } |
ab835497 RK |
3923 | } |
3924 | ||
0021b564 | 3925 | if (dwarf2out_do_frame () && actual_fsize) |
c53aa195 | 3926 | { |
96987e96 | 3927 | char *label = dwarf2out_cfi_label (); |
c53aa195 JM |
3928 | |
3929 | /* The canonical frame address refers to the top of the frame. */ | |
3930 | dwarf2out_def_cfa (label, (leaf_function ? STACK_POINTER_REGNUM | |
563c12b0 | 3931 | : HARD_FRAME_POINTER_REGNUM), |
c53aa195 JM |
3932 | frame_base_offset); |
3933 | ||
3934 | if (! leaf_function) | |
3935 | { | |
3936 | /* Note the register window save. This tells the unwinder that | |
3937 | it needs to restore the window registers from the previous | |
3938 | frame's window save area at 0(cfa). */ | |
3939 | dwarf2out_window_save (label); | |
3940 | ||
3941 | /* The return address (-8) is now in %i7. */ | |
3942 | dwarf2out_return_reg (label, 31); | |
3943 | } | |
3944 | } | |
c53aa195 | 3945 | |
ab835497 RK |
3946 | /* If doing anything with PIC, do it now. */ |
3947 | if (! flag_pic) | |
bf62bbf1 | 3948 | fprintf (file, "\t%s#PROLOGUE# 1\n", ASM_COMMENT_START); |
ab835497 | 3949 | |
61a55e8b DE |
3950 | /* Call saved registers are saved just above the outgoing argument area. */ |
3951 | if (num_gfregs) | |
ab835497 | 3952 | { |
c53aa195 | 3953 | int offset, real_offset, n_regs; |
3bb5de61 | 3954 | const char *base; |
ab835497 | 3955 | |
84e884e9 JM |
3956 | real_offset = -apparent_fsize; |
3957 | offset = -apparent_fsize + frame_base_offset; | |
61a55e8b DE |
3958 | if (offset < -4096 || offset + num_gfregs * 4 > 4096) |
3959 | { | |
3960 | /* ??? This might be optimized a little as %g1 might already have a | |
3961 | value close enough that a single add insn will do. */ | |
3962 | /* ??? Although, all of this is probably only a temporary fix | |
3963 | because if %g1 can hold a function result, then | |
3964 | output_function_epilogue will lose (the result will get | |
3965 | clobbered). */ | |
3966 | build_big_number (file, offset, "%g1"); | |
e0d80184 | 3967 | fprintf (file, "\tadd\t%s, %%g1, %%g1\n", frame_base_name); |
61a55e8b DE |
3968 | base = "%g1"; |
3969 | offset = 0; | |
3970 | } | |
ab835497 | 3971 | else |
61a55e8b DE |
3972 | { |
3973 | base = frame_base_name; | |
3974 | } | |
ab835497 | 3975 | |
33074e5f RH |
3976 | n_regs = save_regs (file, 0, 8, base, offset, 0, real_offset); |
3977 | save_regs (file, 32, TARGET_V9 ? 96 : 64, base, offset, n_regs, | |
3978 | real_offset); | |
ab835497 RK |
3979 | } |
3980 | } | |
3981 | ||
7d167afd JJ |
3982 | /* Output code to restore any call saved registers. */ |
3983 | ||
3984 | static void | |
3985 | output_restore_regs (file, leaf_function) | |
3986 | FILE *file; | |
f451b552 | 3987 | int leaf_function ATTRIBUTE_UNUSED; |
7d167afd JJ |
3988 | { |
3989 | int offset, n_regs; | |
3990 | const char *base; | |
3991 | ||
3992 | offset = -apparent_fsize + frame_base_offset; | |
3993 | if (offset < -4096 || offset + num_gfregs * 4 > 4096 - 8 /*double*/) | |
3994 | { | |
3995 | build_big_number (file, offset, "%g1"); | |
3996 | fprintf (file, "\tadd\t%s, %%g1, %%g1\n", frame_base_name); | |
3997 | base = "%g1"; | |
3998 | offset = 0; | |
3999 | } | |
4000 | else | |
4001 | { | |
4002 | base = frame_base_name; | |
4003 | } | |
4004 | ||
33074e5f RH |
4005 | n_regs = restore_regs (file, 0, 8, base, offset, 0); |
4006 | restore_regs (file, 32, TARGET_V9 ? 96 : 64, base, offset, n_regs); | |
7d167afd JJ |
4007 | } |
4008 | ||
08c148a8 NB |
4009 | /* This function generates the assembly code for function exit, |
4010 | on machines that need it. | |
4011 | ||
4012 | The function epilogue should not depend on the current stack pointer! | |
4013 | It should use the frame pointer only. This is mandatory because | |
4014 | of alloca; we also take advantage of it to omit stack adjustments | |
4015 | before returning. */ | |
4016 | ||
4017 | static void | |
4018 | sparc_output_function_epilogue (file, size) | |
4019 | FILE *file; | |
4020 | HOST_WIDE_INT size; | |
4021 | { | |
4022 | if (TARGET_FLAT) | |
4023 | sparc_flat_function_epilogue (file, size); | |
4024 | else | |
4025 | sparc_nonflat_function_epilogue (file, size, | |
4026 | current_function_uses_only_leaf_regs); | |
4027 | } | |
4028 | ||
915f619f JW |
4029 | /* Output code for the function epilogue. */ |
4030 | ||
08c148a8 NB |
4031 | static void |
4032 | sparc_nonflat_function_epilogue (file, size, leaf_function) | |
ab835497 | 4033 | FILE *file; |
08c148a8 | 4034 | HOST_WIDE_INT size ATTRIBUTE_UNUSED; |
ef8200df | 4035 | int leaf_function; |
ab835497 | 4036 | { |
3bb5de61 | 4037 | const char *ret; |
ab835497 | 4038 | |
8456b95a | 4039 | if (current_function_epilogue_delay_list == 0) |
e48addee | 4040 | { |
e0d80184 | 4041 | /* If code does not drop into the epilogue, we need |
7a31a340 DM |
4042 | do nothing except output pending case vectors. |
4043 | ||
4044 | We have to still output a dummy nop for the sake of | |
4045 | sane backtraces. Otherwise, if the last two instructions | |
4046 | of a function were call foo; dslot; this can make the return | |
4047 | PC of foo (ie. address of call instruction plus 8) point to | |
4048 | the first instruction in the next function. */ | |
4049 | rtx insn; | |
4050 | ||
4051 | fputs("\tnop\n", file); | |
4052 | ||
4053 | insn = get_last_insn (); | |
4054 | if (GET_CODE (insn) == NOTE) | |
4055 | insn = prev_nonnote_insn (insn); | |
4056 | if (insn && GET_CODE (insn) == BARRIER) | |
4057 | goto output_vectors; | |
bfd6bc60 JC |
4058 | } |
4059 | ||
61a55e8b | 4060 | if (num_gfregs) |
7d167afd | 4061 | output_restore_regs (file, leaf_function); |
ab835497 RK |
4062 | |
4063 | /* Work out how to skip the caller's unimp instruction if required. */ | |
4064 | if (leaf_function) | |
e0d80184 | 4065 | ret = (SKIP_CALLERS_UNIMP_P ? "jmp\t%o7+12" : "retl"); |
ab835497 | 4066 | else |
e0d80184 | 4067 | ret = (SKIP_CALLERS_UNIMP_P ? "jmp\t%i7+12" : "ret"); |
ab835497 | 4068 | |
33074e5f | 4069 | if (! leaf_function) |
ab835497 | 4070 | { |
33074e5f RH |
4071 | if (current_function_calls_eh_return) |
4072 | { | |
4073 | if (current_function_epilogue_delay_list) | |
4074 | abort (); | |
4075 | if (SKIP_CALLERS_UNIMP_P) | |
4076 | abort (); | |
ab835497 | 4077 | |
33074e5f RH |
4078 | fputs ("\trestore\n\tretl\n\tadd\t%sp, %g1, %sp\n", file); |
4079 | } | |
4080 | /* If we wound up with things in our delay slot, flush them here. */ | |
4081 | else if (current_function_epilogue_delay_list) | |
ef8200df | 4082 | { |
33074e5f | 4083 | rtx delay = PATTERN (XEXP (current_function_epilogue_delay_list, 0)); |
1150a841 | 4084 | |
33074e5f RH |
4085 | if (TARGET_V9 && ! epilogue_renumber (&delay, 1)) |
4086 | { | |
4087 | epilogue_renumber (&delay, 0); | |
4088 | fputs (SKIP_CALLERS_UNIMP_P | |
4089 | ? "\treturn\t%i7+12\n" | |
4090 | : "\treturn\t%i7+8\n", file); | |
4091 | final_scan_insn (XEXP (current_function_epilogue_delay_list, 0), | |
4092 | file, 1, 0, 0); | |
1150a841 | 4093 | } |
33074e5f | 4094 | else |
ab835497 | 4095 | { |
33074e5f | 4096 | rtx insn, src; |
e48addee | 4097 | |
33074e5f RH |
4098 | if (GET_CODE (delay) != SET) |
4099 | abort(); | |
e48addee | 4100 | |
33074e5f RH |
4101 | src = SET_SRC (delay); |
4102 | if (GET_CODE (src) == ASHIFT) | |
4103 | { | |
4104 | if (XEXP (src, 1) != const1_rtx) | |
e48addee | 4105 | abort(); |
33074e5f RH |
4106 | SET_SRC (delay) |
4107 | = gen_rtx_PLUS (GET_MODE (src), XEXP (src, 0), | |
4108 | XEXP (src, 0)); | |
4109 | } | |
e48addee | 4110 | |
33074e5f RH |
4111 | insn = gen_rtx_PARALLEL (VOIDmode, |
4112 | gen_rtvec (2, delay, | |
4113 | gen_rtx_RETURN (VOIDmode))); | |
4114 | insn = emit_jump_insn (insn); | |
e48addee | 4115 | |
33074e5f RH |
4116 | sparc_emitting_epilogue = true; |
4117 | final_scan_insn (insn, file, 1, 0, 1); | |
4118 | sparc_emitting_epilogue = false; | |
ab835497 | 4119 | } |
ef8200df | 4120 | } |
33074e5f RH |
4121 | else if (TARGET_V9 && ! SKIP_CALLERS_UNIMP_P) |
4122 | fputs ("\treturn\t%i7+8\n\tnop\n", file); | |
4123 | else | |
4124 | fprintf (file, "\t%s\n\trestore\n", ret); | |
4125 | } | |
4126 | /* All of the following cases are for leaf functions. */ | |
4127 | else if (current_function_calls_eh_return) | |
4128 | abort (); | |
4129 | else if (current_function_epilogue_delay_list) | |
4130 | { | |
4131 | /* eligible_for_epilogue_delay_slot ensures that if this is a | |
4132 | leaf function, then we will only have insn in the delay slot | |
4133 | if the frame size is zero, thus no adjust for the stack is | |
4134 | needed here. */ | |
4135 | if (actual_fsize != 0) | |
1150a841 | 4136 | abort (); |
33074e5f RH |
4137 | fprintf (file, "\t%s\n", ret); |
4138 | final_scan_insn (XEXP (current_function_epilogue_delay_list, 0), | |
4139 | file, 1, 0, 1); | |
ab835497 | 4140 | } |
33074e5f RH |
4141 | /* Output 'nop' instead of 'sub %sp,-0,%sp' when no frame, so as to |
4142 | avoid generating confusing assembly language output. */ | |
4143 | else if (actual_fsize == 0) | |
4144 | fprintf (file, "\t%s\n\tnop\n", ret); | |
4145 | else if (actual_fsize <= 4096) | |
4146 | fprintf (file, "\t%s\n\tsub\t%%sp, -%d, %%sp\n", ret, actual_fsize); | |
4147 | else if (actual_fsize <= 8192) | |
4148 | fprintf (file, "\tsub\t%%sp, -4096, %%sp\n\t%s\n\tsub\t%%sp, -%d, %%sp\n", | |
4149 | ret, actual_fsize - 4096); | |
4150 | else if ((actual_fsize & 0x3ff) == 0) | |
4151 | fprintf (file, "\tsethi\t%%hi(%d), %%g1\n\t%s\n\tadd\t%%sp, %%g1, %%sp\n", | |
4152 | actual_fsize, ret); | |
4153 | else | |
4154 | fprintf (file, "\tsethi\t%%hi(%d), %%g1\n\tor\t%%g1, %%lo(%d), %%g1\n\t%s\n\tadd\t%%sp, %%g1, %%sp\n", | |
4155 | actual_fsize, actual_fsize, ret); | |
e0d80184 DM |
4156 | |
4157 | output_vectors: | |
4158 | sparc_output_deferred_case_vectors (); | |
ab835497 | 4159 | } |
7d167afd JJ |
4160 | |
4161 | /* Output a sibling call. */ | |
4162 | ||
4163 | const char * | |
4164 | output_sibcall (insn, call_operand) | |
4165 | rtx insn, call_operand; | |
4166 | { | |
4167 | int leaf_regs = current_function_uses_only_leaf_regs; | |
4168 | rtx operands[3]; | |
4169 | int delay_slot = dbr_sequence_length () > 0; | |
4170 | ||
4171 | if (num_gfregs) | |
4172 | { | |
4173 | /* Call to restore global regs might clobber | |
4174 | the delay slot. Instead of checking for this | |
4175 | output the delay slot now. */ | |
4176 | if (delay_slot) | |
4177 | { | |
4178 | rtx delay = NEXT_INSN (insn); | |
4179 | ||
4180 | if (! delay) | |
4181 | abort (); | |
4182 | ||
4183 | final_scan_insn (delay, asm_out_file, 1, 0, 1); | |
4184 | PATTERN (delay) = gen_blockage (); | |
4185 | INSN_CODE (delay) = -1; | |
4186 | delay_slot = 0; | |
4187 | } | |
4188 | output_restore_regs (asm_out_file, leaf_regs); | |
4189 | } | |
4190 | ||
4191 | operands[0] = call_operand; | |
4192 | ||
4193 | if (leaf_regs) | |
4194 | { | |
e95b1e6a JJ |
4195 | #ifdef HAVE_AS_RELAX_OPTION |
4196 | /* If as and ld are relaxing tail call insns into branch always, | |
4197 | use or %o7,%g0,X; call Y; or X,%g0,%o7 always, so that it can | |
4198 | be optimized. With sethi/jmpl as nor ld has no easy way how to | |
4199 | find out if somebody does not branch between the sethi and jmpl. */ | |
4200 | int spare_slot = 0; | |
4201 | #else | |
2be5e524 | 4202 | int spare_slot = ((TARGET_ARCH32 || TARGET_CM_MEDLOW) && ! flag_pic); |
e95b1e6a | 4203 | #endif |
7d167afd JJ |
4204 | int size = 0; |
4205 | ||
4206 | if ((actual_fsize || ! spare_slot) && delay_slot) | |
4207 | { | |
4208 | rtx delay = NEXT_INSN (insn); | |
4209 | ||
4210 | if (! delay) | |
4211 | abort (); | |
4212 | ||
4213 | final_scan_insn (delay, asm_out_file, 1, 0, 1); | |
4214 | PATTERN (delay) = gen_blockage (); | |
4215 | INSN_CODE (delay) = -1; | |
4216 | delay_slot = 0; | |
4217 | } | |
4218 | if (actual_fsize) | |
4219 | { | |
4220 | if (actual_fsize <= 4096) | |
4221 | size = actual_fsize; | |
4222 | else if (actual_fsize <= 8192) | |
4223 | { | |
4224 | fputs ("\tsub\t%sp, -4096, %sp\n", asm_out_file); | |
4225 | size = actual_fsize - 4096; | |
4226 | } | |
4227 | else if ((actual_fsize & 0x3ff) == 0) | |
4228 | fprintf (asm_out_file, | |
4229 | "\tsethi\t%%hi(%d), %%g1\n\tadd\t%%sp, %%g1, %%sp\n", | |
4230 | actual_fsize); | |
4231 | else | |
4232 | { | |
4233 | fprintf (asm_out_file, | |
4234 | "\tsethi\t%%hi(%d), %%g1\n\tor\t%%g1, %%lo(%d), %%g1\n", | |
4235 | actual_fsize, actual_fsize); | |
4236 | fputs ("\tadd\t%%sp, %%g1, %%sp\n", asm_out_file); | |
4237 | } | |
4238 | } | |
4239 | if (spare_slot) | |
4240 | { | |
4241 | output_asm_insn ("sethi\t%%hi(%a0), %%g1", operands); | |
4242 | output_asm_insn ("jmpl\t%%g1 + %%lo(%a0), %%g0", operands); | |
4243 | if (size) | |
4244 | fprintf (asm_out_file, "\t sub\t%%sp, -%d, %%sp\n", size); | |
4245 | else if (! delay_slot) | |
4246 | fputs ("\t nop\n", asm_out_file); | |
4247 | } | |
4248 | else | |
4249 | { | |
4250 | if (size) | |
4251 | fprintf (asm_out_file, "\tsub\t%%sp, -%d, %%sp\n", size); | |
e95b1e6a JJ |
4252 | /* Use or with rs2 %%g0 instead of mov, so that as/ld can optimize |
4253 | it into branch if possible. */ | |
4254 | output_asm_insn ("or\t%%o7, %%g0, %%g1", operands); | |
7d167afd | 4255 | output_asm_insn ("call\t%a0, 0", operands); |
e95b1e6a | 4256 | output_asm_insn (" or\t%%g1, %%g0, %%o7", operands); |
7d167afd JJ |
4257 | } |
4258 | return ""; | |
4259 | } | |
4260 | ||
4261 | output_asm_insn ("call\t%a0, 0", operands); | |
4262 | if (delay_slot) | |
4263 | { | |
4264 | rtx delay = NEXT_INSN (insn), pat; | |
4265 | ||
4266 | if (! delay) | |
4267 | abort (); | |
4268 | ||
4269 | pat = PATTERN (delay); | |
4270 | if (GET_CODE (pat) != SET) | |
4271 | abort (); | |
4272 | ||
4273 | operands[0] = SET_DEST (pat); | |
4274 | pat = SET_SRC (pat); | |
4275 | switch (GET_CODE (pat)) | |
4276 | { | |
4277 | case PLUS: | |
4278 | operands[1] = XEXP (pat, 0); | |
4279 | operands[2] = XEXP (pat, 1); | |
4280 | output_asm_insn (" restore %r1, %2, %Y0", operands); | |
4281 | break; | |
4282 | case LO_SUM: | |
4283 | operands[1] = XEXP (pat, 0); | |
4284 | operands[2] = XEXP (pat, 1); | |
4285 | output_asm_insn (" restore %r1, %%lo(%a2), %Y0", operands); | |
4286 | break; | |
4287 | case ASHIFT: | |
4288 | operands[1] = XEXP (pat, 0); | |
4289 | output_asm_insn (" restore %r1, %r1, %Y0", operands); | |
4290 | break; | |
4291 | default: | |
4292 | operands[1] = pat; | |
4293 | output_asm_insn (" restore %%g0, %1, %Y0", operands); | |
4294 | break; | |
4295 | } | |
4296 | PATTERN (delay) = gen_blockage (); | |
4297 | INSN_CODE (delay) = -1; | |
4298 | } | |
4299 | else | |
4300 | fputs ("\t restore\n", asm_out_file); | |
4301 | return ""; | |
4302 | } | |
4fb4e4b8 DE |
4303 | \f |
4304 | /* Functions for handling argument passing. | |
4305 | ||
4306 | For v8 the first six args are normally in registers and the rest are | |
4307 | pushed. Any arg that starts within the first 6 words is at least | |
4308 | partially passed in a register unless its data type forbids. | |
4309 | ||
4310 | For v9, the argument registers are laid out as an array of 16 elements | |
4311 | and arguments are added sequentially. The first 6 int args and up to the | |
4312 | first 16 fp args (depending on size) are passed in regs. | |
4313 | ||
4314 | Slot Stack Integral Float Float in structure Double Long Double | |
4315 | ---- ----- -------- ----- ------------------ ------ ----------- | |
4316 | 15 [SP+248] %f31 %f30,%f31 %d30 | |
4317 | 14 [SP+240] %f29 %f28,%f29 %d28 %q28 | |
4318 | 13 [SP+232] %f27 %f26,%f27 %d26 | |
4319 | 12 [SP+224] %f25 %f24,%f25 %d24 %q24 | |
4320 | 11 [SP+216] %f23 %f22,%f23 %d22 | |
4321 | 10 [SP+208] %f21 %f20,%f21 %d20 %q20 | |
4322 | 9 [SP+200] %f19 %f18,%f19 %d18 | |
4323 | 8 [SP+192] %f17 %f16,%f17 %d16 %q16 | |
4324 | 7 [SP+184] %f15 %f14,%f15 %d14 | |
4325 | 6 [SP+176] %f13 %f12,%f13 %d12 %q12 | |
4326 | 5 [SP+168] %o5 %f11 %f10,%f11 %d10 | |
4327 | 4 [SP+160] %o4 %f9 %f8,%f9 %d8 %q8 | |
4328 | 3 [SP+152] %o3 %f7 %f6,%f7 %d6 | |
4329 | 2 [SP+144] %o2 %f5 %f4,%f5 %d4 %q4 | |
4330 | 1 [SP+136] %o1 %f3 %f2,%f3 %d2 | |
4331 | 0 [SP+128] %o0 %f1 %f0,%f1 %d0 %q0 | |
4332 | ||
4333 | Here SP = %sp if -mno-stack-bias or %sp+stack_bias otherwise. | |
4334 | ||
4335 | Integral arguments are always passed as 64 bit quantities appropriately | |
4336 | extended. | |
4337 | ||
4338 | Passing of floating point values is handled as follows. | |
4339 | If a prototype is in scope: | |
4340 | If the value is in a named argument (i.e. not a stdarg function or a | |
4341 | value not part of the `...') then the value is passed in the appropriate | |
4342 | fp reg. | |
4343 | If the value is part of the `...' and is passed in one of the first 6 | |
4344 | slots then the value is passed in the appropriate int reg. | |
4345 | If the value is part of the `...' and is not passed in one of the first 6 | |
4346 | slots then the value is passed in memory. | |
4347 | If a prototype is not in scope: | |
4348 | If the value is one of the first 6 arguments the value is passed in the | |
4349 | appropriate integer reg and the appropriate fp reg. | |
4350 | If the value is not one of the first 6 arguments the value is passed in | |
4351 | the appropriate fp reg and in memory. | |
4352 | */ | |
4353 | ||
4354 | /* Maximum number of int regs for args. */ | |
4355 | #define SPARC_INT_ARG_MAX 6 | |
4356 | /* Maximum number of fp regs for args. */ | |
4357 | #define SPARC_FP_ARG_MAX 16 | |
4358 | ||
4359 | #define ROUND_ADVANCE(SIZE) (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) | |
4360 | ||
4361 | /* Handle the INIT_CUMULATIVE_ARGS macro. | |
4362 | Initialize a variable CUM of type CUMULATIVE_ARGS | |
4363 | for a call to a function whose data type is FNTYPE. | |
4364 | For a library call, FNTYPE is 0. */ | |
3ea1fdd3 | 4365 | |
4fb4e4b8 | 4366 | void |
563a317a | 4367 | init_cumulative_args (cum, fntype, libname, fndecl) |
4fb4e4b8 | 4368 | CUMULATIVE_ARGS *cum; |
db3d4438 | 4369 | tree fntype; |
88430453 | 4370 | rtx libname ATTRIBUTE_UNUSED; |
563a317a | 4371 | tree fndecl ATTRIBUTE_UNUSED; |
4fb4e4b8 DE |
4372 | { |
4373 | cum->words = 0; | |
4374 | cum->prototype_p = fntype && TYPE_ARG_TYPES (fntype); | |
4375 | cum->libcall_p = fntype == 0; | |
4376 | } | |
61a55e8b | 4377 | |
4fb4e4b8 DE |
4378 | /* Compute the slot number to pass an argument in. |
4379 | Returns the slot number or -1 if passing on the stack. | |
4380 | ||
4381 | CUM is a variable of type CUMULATIVE_ARGS which gives info about | |
4382 | the preceding args and about the function being called. | |
4383 | MODE is the argument's machine mode. | |
4384 | TYPE is the data type of the argument (as a tree). | |
4385 | This is null for libcalls where that information may | |
4386 | not be available. | |
4387 | NAMED is nonzero if this argument is a named parameter | |
4388 | (otherwise it is an extra parameter matching an ellipsis). | |
4389 | INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG. | |
4390 | *PREGNO records the register number to use if scalar type. | |
4391 | *PPADDING records the amount of padding needed in words. */ | |
4392 | ||
4393 | static int | |
4394 | function_arg_slotno (cum, mode, type, named, incoming_p, pregno, ppadding) | |
4395 | const CUMULATIVE_ARGS *cum; | |
4396 | enum machine_mode mode; | |
4397 | tree type; | |
4398 | int named; | |
4399 | int incoming_p; | |
4400 | int *pregno; | |
4401 | int *ppadding; | |
4402 | { | |
4403 | int regbase = (incoming_p | |
4404 | ? SPARC_INCOMING_INT_ARG_FIRST | |
4405 | : SPARC_OUTGOING_INT_ARG_FIRST); | |
4406 | int slotno = cum->words; | |
4407 | int regno; | |
4408 | ||
4409 | *ppadding = 0; | |
4410 | ||
4411 | if (type != 0 && TREE_ADDRESSABLE (type)) | |
4412 | return -1; | |
4413 | if (TARGET_ARCH32 | |
4414 | && type != 0 && mode == BLKmode | |
4415 | && TYPE_ALIGN (type) % PARM_BOUNDARY != 0) | |
4416 | return -1; | |
4417 | ||
4418 | switch (mode) | |
4419 | { | |
4420 | case VOIDmode : | |
4421 | /* MODE is VOIDmode when generating the actual call. | |
4422 | See emit_call_1. */ | |
4423 | return -1; | |
4424 | ||
4425 | case QImode : case CQImode : | |
4426 | case HImode : case CHImode : | |
4427 | case SImode : case CSImode : | |
4428 | case DImode : case CDImode : | |
380f6ad3 | 4429 | case TImode : case CTImode : |
4fb4e4b8 DE |
4430 | if (slotno >= SPARC_INT_ARG_MAX) |
4431 | return -1; | |
4432 | regno = regbase + slotno; | |
4433 | break; | |
4434 | ||
4435 | case SFmode : case SCmode : | |
4436 | case DFmode : case DCmode : | |
4437 | case TFmode : case TCmode : | |
4438 | if (TARGET_ARCH32) | |
4439 | { | |
4440 | if (slotno >= SPARC_INT_ARG_MAX) | |
4441 | return -1; | |
4442 | regno = regbase + slotno; | |
4443 | } | |
4444 | else | |
4445 | { | |
4446 | if ((mode == TFmode || mode == TCmode) | |
4447 | && (slotno & 1) != 0) | |
4448 | slotno++, *ppadding = 1; | |
4449 | if (TARGET_FPU && named) | |
4450 | { | |
4451 | if (slotno >= SPARC_FP_ARG_MAX) | |
82d6b402 | 4452 | return -1; |
4fb4e4b8 DE |
4453 | regno = SPARC_FP_ARG_FIRST + slotno * 2; |
4454 | if (mode == SFmode) | |
4455 | regno++; | |
4456 | } | |
4457 | else | |
4458 | { | |
4459 | if (slotno >= SPARC_INT_ARG_MAX) | |
4460 | return -1; | |
4461 | regno = regbase + slotno; | |
4462 | } | |
4463 | } | |
4464 | break; | |
4465 | ||
4466 | case BLKmode : | |
4467 | /* For sparc64, objects requiring 16 byte alignment get it. */ | |
4468 | if (TARGET_ARCH64) | |
4469 | { | |
4470 | if (type && TYPE_ALIGN (type) == 128 && (slotno & 1) != 0) | |
4471 | slotno++, *ppadding = 1; | |
4472 | } | |
4473 | ||
4474 | if (TARGET_ARCH32 | |
5e9defae | 4475 | || (type && TREE_CODE (type) == UNION_TYPE)) |
4fb4e4b8 DE |
4476 | { |
4477 | if (slotno >= SPARC_INT_ARG_MAX) | |
4478 | return -1; | |
4479 | regno = regbase + slotno; | |
4480 | } | |
4481 | else | |
4482 | { | |
4483 | tree field; | |
4484 | int intregs_p = 0, fpregs_p = 0; | |
4485 | /* The ABI obviously doesn't specify how packed | |
4486 | structures are passed. These are defined to be passed | |
4487 | in int regs if possible, otherwise memory. */ | |
4488 | int packed_p = 0; | |
4489 | ||
4490 | /* First see what kinds of registers we need. */ | |
4491 | for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field)) | |
4492 | { | |
4493 | if (TREE_CODE (field) == FIELD_DECL) | |
4494 | { | |
4495 | if (TREE_CODE (TREE_TYPE (field)) == REAL_TYPE | |
4496 | && TARGET_FPU) | |
4497 | fpregs_p = 1; | |
4498 | else | |
4499 | intregs_p = 1; | |
4500 | if (DECL_PACKED (field)) | |
4501 | packed_p = 1; | |
4502 | } | |
4503 | } | |
4504 | if (packed_p || !named) | |
4505 | fpregs_p = 0, intregs_p = 1; | |
4506 | ||
4507 | /* If all arg slots are filled, then must pass on stack. */ | |
4508 | if (fpregs_p && slotno >= SPARC_FP_ARG_MAX) | |
4509 | return -1; | |
4510 | /* If there are only int args and all int arg slots are filled, | |
4511 | then must pass on stack. */ | |
4512 | if (!fpregs_p && intregs_p && slotno >= SPARC_INT_ARG_MAX) | |
4513 | return -1; | |
4514 | /* Note that even if all int arg slots are filled, fp members may | |
4515 | still be passed in regs if such regs are available. | |
4516 | *PREGNO isn't set because there may be more than one, it's up | |
4517 | to the caller to compute them. */ | |
4518 | return slotno; | |
4519 | } | |
4520 | break; | |
4521 | ||
4522 | default : | |
4523 | abort (); | |
4524 | } | |
4525 | ||
4526 | *pregno = regno; | |
4527 | return slotno; | |
4528 | } | |
4529 | ||
82d6b402 RH |
4530 | /* Handle recursive register counting for structure field layout. */ |
4531 | ||
4532 | struct function_arg_record_value_parms | |
4533 | { | |
48028e21 EB |
4534 | rtx ret; /* return expression being built. */ |
4535 | int slotno; /* slot number of the argument. */ | |
4536 | int named; /* whether the argument is named. */ | |
4537 | int regbase; /* regno of the base register. */ | |
4538 | int stack; /* 1 if part of the argument is on the stack. */ | |
4539 | int intoffset; /* offset of the pending integer field. */ | |
4540 | unsigned int nregs; /* number of words passed in registers. */ | |
82d6b402 RH |
4541 | }; |
4542 | ||
2a01c939 | 4543 | static void function_arg_record_value_3 |
75131237 | 4544 | PARAMS ((HOST_WIDE_INT, struct function_arg_record_value_parms *)); |
2a01c939 | 4545 | static void function_arg_record_value_2 |
75131237 RK |
4546 | PARAMS ((tree, HOST_WIDE_INT, |
4547 | struct function_arg_record_value_parms *)); | |
b1474bb7 | 4548 | static void function_arg_record_value_1 |
75131237 RK |
4549 | PARAMS ((tree, HOST_WIDE_INT, |
4550 | struct function_arg_record_value_parms *)); | |
2a01c939 | 4551 | static rtx function_arg_record_value |
f6da8bc3 | 4552 | PARAMS ((tree, enum machine_mode, int, int, int)); |
2a01c939 | 4553 | |
0020b823 RH |
4554 | /* A subroutine of function_arg_record_value. Traverse the structure |
4555 | recusively and determine how many registers will be required. */ | |
4556 | ||
82d6b402 RH |
4557 | static void |
4558 | function_arg_record_value_1 (type, startbitpos, parms) | |
4559 | tree type; | |
75131237 | 4560 | HOST_WIDE_INT startbitpos; |
82d6b402 RH |
4561 | struct function_arg_record_value_parms *parms; |
4562 | { | |
4563 | tree field; | |
4564 | ||
4565 | /* The ABI obviously doesn't specify how packed structures are | |
4566 | passed. These are defined to be passed in int regs if possible, | |
4567 | otherwise memory. */ | |
4568 | int packed_p = 0; | |
4569 | ||
4570 | /* We need to compute how many registers are needed so we can | |
4571 | allocate the PARALLEL but before we can do that we need to know | |
4572 | whether there are any packed fields. If there are, int regs are | |
4573 | used regardless of whether there are fp values present. */ | |
4574 | for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field)) | |
4575 | { | |
4576 | if (TREE_CODE (field) == FIELD_DECL && DECL_PACKED (field)) | |
4577 | { | |
4578 | packed_p = 1; | |
4579 | break; | |
4580 | } | |
4581 | } | |
4582 | ||
4583 | /* Compute how many registers we need. */ | |
4584 | for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field)) | |
4585 | { | |
4586 | if (TREE_CODE (field) == FIELD_DECL) | |
4587 | { | |
75131237 RK |
4588 | HOST_WIDE_INT bitpos = startbitpos; |
4589 | ||
4590 | if (DECL_SIZE (field) != 0 | |
4591 | && host_integerp (bit_position (field), 1)) | |
4592 | bitpos += int_bit_position (field); | |
4593 | ||
82d6b402 RH |
4594 | /* ??? FIXME: else assume zero offset. */ |
4595 | ||
4596 | if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE) | |
75131237 | 4597 | function_arg_record_value_1 (TREE_TYPE (field), bitpos, parms); |
105b2084 JJ |
4598 | else if ((TREE_CODE (TREE_TYPE (field)) == REAL_TYPE |
4599 | || (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE | |
4600 | && (TREE_CODE (TREE_TYPE (TREE_TYPE (field))) | |
4601 | == REAL_TYPE))) | |
82d6b402 RH |
4602 | && TARGET_FPU |
4603 | && ! packed_p | |
4604 | && parms->named) | |
4605 | { | |
4606 | if (parms->intoffset != -1) | |
4607 | { | |
4608 | int intslots, this_slotno; | |
4609 | ||
4610 | intslots = (bitpos - parms->intoffset + BITS_PER_WORD - 1) | |
4611 | / BITS_PER_WORD; | |
4612 | this_slotno = parms->slotno + parms->intoffset | |
4613 | / BITS_PER_WORD; | |
4614 | ||
48028e21 EB |
4615 | if (intslots > 0 && intslots > SPARC_INT_ARG_MAX - this_slotno) |
4616 | { | |
4617 | intslots = MAX (0, SPARC_INT_ARG_MAX - this_slotno); | |
4618 | /* We need to pass this field on the stack. */ | |
4619 | parms->stack = 1; | |
4620 | } | |
4621 | ||
82d6b402 RH |
4622 | parms->nregs += intslots; |
4623 | parms->intoffset = -1; | |
4624 | } | |
4625 | ||
4626 | /* There's no need to check this_slotno < SPARC_FP_ARG MAX. | |
4627 | If it wasn't true we wouldn't be here. */ | |
4628 | parms->nregs += 1; | |
105b2084 JJ |
4629 | if (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE) |
4630 | parms->nregs += 1; | |
82d6b402 RH |
4631 | } |
4632 | else | |
4633 | { | |
4634 | if (parms->intoffset == -1) | |
4635 | parms->intoffset = bitpos; | |
4636 | } | |
4637 | } | |
4638 | } | |
4639 | } | |
4640 | ||
0020b823 RH |
4641 | /* A subroutine of function_arg_record_value. Assign the bits of the |
4642 | structure between parms->intoffset and bitpos to integer registers. */ | |
82d6b402 RH |
4643 | |
4644 | static void | |
4645 | function_arg_record_value_3 (bitpos, parms) | |
75131237 | 4646 | HOST_WIDE_INT bitpos; |
82d6b402 RH |
4647 | struct function_arg_record_value_parms *parms; |
4648 | { | |
4649 | enum machine_mode mode; | |
75131237 | 4650 | unsigned int regno; |
0020b823 | 4651 | unsigned int startbit, endbit; |
75131237 | 4652 | int this_slotno, intslots, intoffset; |
82d6b402 RH |
4653 | rtx reg; |
4654 | ||
4655 | if (parms->intoffset == -1) | |
4656 | return; | |
75131237 | 4657 | |
82d6b402 RH |
4658 | intoffset = parms->intoffset; |
4659 | parms->intoffset = -1; | |
4660 | ||
0020b823 RH |
4661 | startbit = intoffset & -BITS_PER_WORD; |
4662 | endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD; | |
4663 | intslots = (endbit - startbit) / BITS_PER_WORD; | |
82d6b402 RH |
4664 | this_slotno = parms->slotno + intoffset / BITS_PER_WORD; |
4665 | ||
4666 | intslots = MIN (intslots, SPARC_INT_ARG_MAX - this_slotno); | |
4667 | if (intslots <= 0) | |
4668 | return; | |
4669 | ||
4670 | /* If this is the trailing part of a word, only load that much into | |
4671 | the register. Otherwise load the whole register. Note that in | |
4672 | the latter case we may pick up unwanted bits. It's not a problem | |
4673 | at the moment but may wish to revisit. */ | |
4674 | ||
4675 | if (intoffset % BITS_PER_WORD != 0) | |
75131237 RK |
4676 | mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD, |
4677 | MODE_INT, 0); | |
82d6b402 RH |
4678 | else |
4679 | mode = word_mode; | |
4680 | ||
4681 | intoffset /= BITS_PER_UNIT; | |
4682 | do | |
4683 | { | |
4684 | regno = parms->regbase + this_slotno; | |
254110c2 | 4685 | reg = gen_rtx_REG (mode, regno); |
48028e21 | 4686 | XVECEXP (parms->ret, 0, parms->stack + parms->nregs) |
254110c2 | 4687 | = gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset)); |
82d6b402 RH |
4688 | |
4689 | this_slotno += 1; | |
4690 | intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1; | |
4691 | parms->nregs += 1; | |
4692 | intslots -= 1; | |
4693 | } | |
4694 | while (intslots > 0); | |
4695 | } | |
4696 | ||
0020b823 RH |
4697 | /* A subroutine of function_arg_record_value. Traverse the structure |
4698 | recursively and assign bits to floating point registers. Track which | |
4699 | bits in between need integer registers; invoke function_arg_record_value_3 | |
4700 | to make that happen. */ | |
4701 | ||
82d6b402 RH |
4702 | static void |
4703 | function_arg_record_value_2 (type, startbitpos, parms) | |
4704 | tree type; | |
75131237 | 4705 | HOST_WIDE_INT startbitpos; |
82d6b402 RH |
4706 | struct function_arg_record_value_parms *parms; |
4707 | { | |
4708 | tree field; | |
4709 | int packed_p = 0; | |
4710 | ||
4711 | for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field)) | |
4712 | { | |
4713 | if (TREE_CODE (field) == FIELD_DECL && DECL_PACKED (field)) | |
4714 | { | |
4715 | packed_p = 1; | |
4716 | break; | |
4717 | } | |
4718 | } | |
4719 | ||
4720 | for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field)) | |
4721 | { | |
4722 | if (TREE_CODE (field) == FIELD_DECL) | |
4723 | { | |
75131237 RK |
4724 | HOST_WIDE_INT bitpos = startbitpos; |
4725 | ||
4726 | if (DECL_SIZE (field) != 0 | |
4727 | && host_integerp (bit_position (field), 1)) | |
4728 | bitpos += int_bit_position (field); | |
4729 | ||
82d6b402 RH |
4730 | /* ??? FIXME: else assume zero offset. */ |
4731 | ||
4732 | if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE) | |
75131237 | 4733 | function_arg_record_value_2 (TREE_TYPE (field), bitpos, parms); |
105b2084 JJ |
4734 | else if ((TREE_CODE (TREE_TYPE (field)) == REAL_TYPE |
4735 | || (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE | |
4736 | && (TREE_CODE (TREE_TYPE (TREE_TYPE (field))) | |
4737 | == REAL_TYPE))) | |
82d6b402 RH |
4738 | && TARGET_FPU |
4739 | && ! packed_p | |
4740 | && parms->named) | |
4741 | { | |
4742 | int this_slotno = parms->slotno + bitpos / BITS_PER_WORD; | |
105b2084 JJ |
4743 | int regno; |
4744 | enum machine_mode mode = DECL_MODE (field); | |
82d6b402 RH |
4745 | rtx reg; |
4746 | ||
4747 | function_arg_record_value_3 (bitpos, parms); | |
105b2084 JJ |
4748 | regno = SPARC_FP_ARG_FIRST + this_slotno * 2 |
4749 | + ((mode == SFmode || mode == SCmode) | |
4750 | && (bitpos & 32) != 0); | |
4751 | switch (mode) | |
4752 | { | |
4753 | case SCmode: mode = SFmode; break; | |
4754 | case DCmode: mode = DFmode; break; | |
4755 | case TCmode: mode = TFmode; break; | |
4756 | default: break; | |
4757 | } | |
4758 | reg = gen_rtx_REG (mode, regno); | |
48028e21 | 4759 | XVECEXP (parms->ret, 0, parms->stack + parms->nregs) |
254110c2 | 4760 | = gen_rtx_EXPR_LIST (VOIDmode, reg, |
82d6b402 RH |
4761 | GEN_INT (bitpos / BITS_PER_UNIT)); |
4762 | parms->nregs += 1; | |
105b2084 JJ |
4763 | if (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE) |
4764 | { | |
4765 | regno += GET_MODE_SIZE (mode) / 4; | |
4766 | reg = gen_rtx_REG (mode, regno); | |
48028e21 | 4767 | XVECEXP (parms->ret, 0, parms->stack + parms->nregs) |
105b2084 JJ |
4768 | = gen_rtx_EXPR_LIST (VOIDmode, reg, |
4769 | GEN_INT ((bitpos + GET_MODE_BITSIZE (mode)) | |
4770 | / BITS_PER_UNIT)); | |
4771 | parms->nregs += 1; | |
4772 | } | |
82d6b402 RH |
4773 | } |
4774 | else | |
4775 | { | |
4776 | if (parms->intoffset == -1) | |
4777 | parms->intoffset = bitpos; | |
4778 | } | |
4779 | } | |
4780 | } | |
4781 | } | |
4782 | ||
0020b823 | 4783 | /* Used by function_arg and function_value to implement the complex |
48028e21 EB |
4784 | conventions of the 64-bit ABI for passing and returning structures. |
4785 | Return an expression valid as a return value for the two macros | |
4786 | FUNCTION_ARG and FUNCTION_VALUE. | |
0020b823 | 4787 | |
48028e21 EB |
4788 | TYPE is the data type of the argument (as a tree). |
4789 | This is null for libcalls where that information may | |
4790 | not be available. | |
4791 | MODE is the argument's machine mode. | |
4792 | SLOTNO is the index number of the argument's slot in the parameter array. | |
4793 | NAMED is nonzero if this argument is a named parameter | |
4794 | (otherwise it is an extra parameter matching an ellipsis). | |
4795 | REGBASE is the regno of the base register for the parameter array. */ | |
4796 | ||
82d6b402 | 4797 | static rtx |
1eac9f59 | 4798 | function_arg_record_value (type, mode, slotno, named, regbase) |
82d6b402 | 4799 | tree type; |
1eac9f59 | 4800 | enum machine_mode mode; |
82d6b402 RH |
4801 | int slotno, named, regbase; |
4802 | { | |
4803 | HOST_WIDE_INT typesize = int_size_in_bytes (type); | |
4804 | struct function_arg_record_value_parms parms; | |
75131237 | 4805 | unsigned int nregs; |
82d6b402 RH |
4806 | |
4807 | parms.ret = NULL_RTX; | |
4808 | parms.slotno = slotno; | |
4809 | parms.named = named; | |
4810 | parms.regbase = regbase; | |
48028e21 | 4811 | parms.stack = 0; |
82d6b402 RH |
4812 | |
4813 | /* Compute how many registers we need. */ | |
4814 | parms.nregs = 0; | |
4815 | parms.intoffset = 0; | |
4816 | function_arg_record_value_1 (type, 0, &parms); | |
4817 | ||
4818 | if (parms.intoffset != -1) | |
4819 | { | |
0020b823 | 4820 | unsigned int startbit, endbit; |
82d6b402 RH |
4821 | int intslots, this_slotno; |
4822 | ||
0020b823 RH |
4823 | startbit = parms.intoffset & -BITS_PER_WORD; |
4824 | endbit = (typesize*BITS_PER_UNIT + BITS_PER_WORD - 1) & -BITS_PER_WORD; | |
4825 | intslots = (endbit - startbit) / BITS_PER_WORD; | |
82d6b402 RH |
4826 | this_slotno = slotno + parms.intoffset / BITS_PER_WORD; |
4827 | ||
48028e21 EB |
4828 | if (intslots > 0 && intslots > SPARC_INT_ARG_MAX - this_slotno) |
4829 | { | |
4830 | intslots = MAX (0, SPARC_INT_ARG_MAX - this_slotno); | |
4831 | /* We need to pass this field on the stack. */ | |
4832 | parms.stack = 1; | |
4833 | } | |
82d6b402 RH |
4834 | |
4835 | parms.nregs += intslots; | |
4836 | } | |
4837 | nregs = parms.nregs; | |
4838 | ||
4839 | /* Allocate the vector and handle some annoying special cases. */ | |
4840 | if (nregs == 0) | |
4841 | { | |
4842 | /* ??? Empty structure has no value? Duh? */ | |
4843 | if (typesize <= 0) | |
4844 | { | |
4845 | /* Though there's nothing really to store, return a word register | |
4846 | anyway so the rest of gcc doesn't go nuts. Returning a PARALLEL | |
4847 | leads to breakage due to the fact that there are zero bytes to | |
4848 | load. */ | |
1eac9f59 | 4849 | return gen_rtx_REG (mode, regbase); |
82d6b402 RH |
4850 | } |
4851 | else | |
4852 | { | |
4853 | /* ??? C++ has structures with no fields, and yet a size. Give up | |
4854 | for now and pass everything back in integer registers. */ | |
4855 | nregs = (typesize + UNITS_PER_WORD - 1) / UNITS_PER_WORD; | |
4856 | } | |
4857 | if (nregs + slotno > SPARC_INT_ARG_MAX) | |
4858 | nregs = SPARC_INT_ARG_MAX - slotno; | |
4859 | } | |
4860 | if (nregs == 0) | |
9208e4b2 | 4861 | abort (); |
82d6b402 | 4862 | |
48028e21 EB |
4863 | parms.ret = gen_rtx_PARALLEL (mode, rtvec_alloc (parms.stack + nregs)); |
4864 | ||
4865 | /* If at least one field must be passed on the stack, generate | |
4866 | (parallel [(expr_list (nil) ...) ...]) so that all fields will | |
4867 | also be passed on the stack. We can't do much better because the | |
4868 | semantics of FUNCTION_ARG_PARTIAL_NREGS doesn't handle the case | |
4869 | of structures for which the fields passed exclusively in registers | |
4870 | are not at the beginning of the structure. */ | |
4871 | if (parms.stack) | |
4872 | XVECEXP (parms.ret, 0, 0) | |
4873 | = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx); | |
82d6b402 RH |
4874 | |
4875 | /* Fill in the entries. */ | |
4876 | parms.nregs = 0; | |
4877 | parms.intoffset = 0; | |
4878 | function_arg_record_value_2 (type, 0, &parms); | |
4879 | function_arg_record_value_3 (typesize * BITS_PER_UNIT, &parms); | |
4880 | ||
4881 | if (parms.nregs != nregs) | |
4882 | abort (); | |
4883 | ||
4884 | return parms.ret; | |
4885 | } | |
4886 | ||
4fb4e4b8 DE |
4887 | /* Handle the FUNCTION_ARG macro. |
4888 | Determine where to put an argument to a function. | |
4889 | Value is zero to push the argument on the stack, | |
4890 | or a hard register in which to store the argument. | |
4891 | ||
4892 | CUM is a variable of type CUMULATIVE_ARGS which gives info about | |
4893 | the preceding args and about the function being called. | |
4894 | MODE is the argument's machine mode. | |
4895 | TYPE is the data type of the argument (as a tree). | |
4896 | This is null for libcalls where that information may | |
4897 | not be available. | |
4898 | NAMED is nonzero if this argument is a named parameter | |
4899 | (otherwise it is an extra parameter matching an ellipsis). | |
4900 | INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG. */ | |
61a55e8b DE |
4901 | |
4902 | rtx | |
4fb4e4b8 DE |
4903 | function_arg (cum, mode, type, named, incoming_p) |
4904 | const CUMULATIVE_ARGS *cum; | |
4905 | enum machine_mode mode; | |
4906 | tree type; | |
4907 | int named; | |
4908 | int incoming_p; | |
61a55e8b | 4909 | { |
4fb4e4b8 DE |
4910 | int regbase = (incoming_p |
4911 | ? SPARC_INCOMING_INT_ARG_FIRST | |
4912 | : SPARC_OUTGOING_INT_ARG_FIRST); | |
4913 | int slotno, regno, padding; | |
4914 | rtx reg; | |
4915 | ||
4916 | slotno = function_arg_slotno (cum, mode, type, named, incoming_p, | |
4917 | ®no, &padding); | |
4918 | ||
4919 | if (slotno == -1) | |
4920 | return 0; | |
4921 | ||
4922 | if (TARGET_ARCH32) | |
4923 | { | |
254110c2 | 4924 | reg = gen_rtx_REG (mode, regno); |
4fb4e4b8 DE |
4925 | return reg; |
4926 | } | |
4927 | ||
4928 | /* v9 fp args in reg slots beyond the int reg slots get passed in regs | |
4929 | but also have the slot allocated for them. | |
4930 | If no prototype is in scope fp values in register slots get passed | |
4931 | in two places, either fp regs and int regs or fp regs and memory. */ | |
4932 | if ((GET_MODE_CLASS (mode) == MODE_FLOAT | |
4933 | || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT) | |
4934 | && SPARC_FP_REG_P (regno)) | |
4935 | { | |
254110c2 | 4936 | reg = gen_rtx_REG (mode, regno); |
4fb4e4b8 DE |
4937 | if (cum->prototype_p || cum->libcall_p) |
4938 | { | |
4939 | /* "* 2" because fp reg numbers are recorded in 4 byte | |
4940 | quantities. */ | |
82d6b402 | 4941 | #if 0 |
4fb4e4b8 DE |
4942 | /* ??? This will cause the value to be passed in the fp reg and |
4943 | in the stack. When a prototype exists we want to pass the | |
4944 | value in the reg but reserve space on the stack. That's an | |
956d6950 | 4945 | optimization, and is deferred [for a bit]. */ |
4fb4e4b8 | 4946 | if ((regno - SPARC_FP_ARG_FIRST) >= SPARC_INT_ARG_MAX * 2) |
254110c2 | 4947 | return gen_rtx_PARALLEL (mode, |
4fb4e4b8 | 4948 | gen_rtvec (2, |
254110c2 | 4949 | gen_rtx_EXPR_LIST (VOIDmode, |
4fb4e4b8 | 4950 | NULL_RTX, const0_rtx), |
254110c2 | 4951 | gen_rtx_EXPR_LIST (VOIDmode, |
4fb4e4b8 DE |
4952 | reg, const0_rtx))); |
4953 | else | |
82d6b402 RH |
4954 | #else |
4955 | /* ??? It seems that passing back a register even when past | |
4956 | the area declared by REG_PARM_STACK_SPACE will allocate | |
4957 | space appropriately, and will not copy the data onto the | |
4958 | stack, exactly as we desire. | |
4959 | ||
4960 | This is due to locate_and_pad_parm being called in | |
4961 | expand_call whenever reg_parm_stack_space > 0, which | |
4962 | while benefical to our example here, would seem to be | |
4963 | in error from what had been intended. Ho hum... -- r~ */ | |
4964 | #endif | |
4fb4e4b8 DE |
4965 | return reg; |
4966 | } | |
4967 | else | |
4968 | { | |
82d6b402 RH |
4969 | rtx v0, v1; |
4970 | ||
4fb4e4b8 DE |
4971 | if ((regno - SPARC_FP_ARG_FIRST) < SPARC_INT_ARG_MAX * 2) |
4972 | { | |
82d6b402 RH |
4973 | int intreg; |
4974 | ||
4975 | /* On incoming, we don't need to know that the value | |
4976 | is passed in %f0 and %i0, and it confuses other parts | |
4977 | causing needless spillage even on the simplest cases. */ | |
4978 | if (incoming_p) | |
4979 | return reg; | |
4980 | ||
4981 | intreg = (SPARC_OUTGOING_INT_ARG_FIRST | |
4982 | + (regno - SPARC_FP_ARG_FIRST) / 2); | |
4983 | ||
4984 | v0 = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx); | |
4985 | v1 = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_REG (mode, intreg), | |
4986 | const0_rtx); | |
4987 | return gen_rtx_PARALLEL (mode, gen_rtvec (2, v0, v1)); | |
4fb4e4b8 DE |
4988 | } |
4989 | else | |
82d6b402 RH |
4990 | { |
4991 | v0 = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx); | |
4992 | v1 = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx); | |
4993 | return gen_rtx_PARALLEL (mode, gen_rtvec (2, v0, v1)); | |
4994 | } | |
4fb4e4b8 DE |
4995 | } |
4996 | } | |
4997 | else if (type && TREE_CODE (type) == RECORD_TYPE) | |
4998 | { | |
4999 | /* Structures up to 16 bytes in size are passed in arg slots on the | |
5000 | stack and are promoted to registers where possible. */ | |
4fb4e4b8 DE |
5001 | |
5002 | if (int_size_in_bytes (type) > 16) | |
5003 | abort (); /* shouldn't get here */ | |
5004 | ||
1eac9f59 | 5005 | return function_arg_record_value (type, mode, slotno, named, regbase); |
4fb4e4b8 DE |
5006 | } |
5007 | else if (type && TREE_CODE (type) == UNION_TYPE) | |
5008 | { | |
5009 | enum machine_mode mode; | |
5010 | int bytes = int_size_in_bytes (type); | |
5011 | ||
5012 | if (bytes > 16) | |
5013 | abort (); | |
5014 | ||
5015 | mode = mode_for_size (bytes * BITS_PER_UNIT, MODE_INT, 0); | |
254110c2 | 5016 | reg = gen_rtx_REG (mode, regno); |
4fb4e4b8 | 5017 | } |
a7acd911 | 5018 | else |
4fb4e4b8 DE |
5019 | { |
5020 | /* Scalar or complex int. */ | |
254110c2 | 5021 | reg = gen_rtx_REG (mode, regno); |
4fb4e4b8 DE |
5022 | } |
5023 | ||
5024 | return reg; | |
5025 | } | |
a7acd911 | 5026 | |
4fb4e4b8 DE |
5027 | /* Handle the FUNCTION_ARG_PARTIAL_NREGS macro. |
5028 | For an arg passed partly in registers and partly in memory, | |
5029 | this is the number of registers used. | |
5030 | For args passed entirely in registers or entirely in memory, zero. | |
61a55e8b | 5031 | |
4fb4e4b8 DE |
5032 | Any arg that starts in the first 6 regs but won't entirely fit in them |
5033 | needs partial registers on v8. On v9, structures with integer | |
5034 | values in arg slots 5,6 will be passed in %o5 and SP+176, and complex fp | |
5035 | values that begin in the last fp reg [where "last fp reg" varies with the | |
5036 | mode] will be split between that reg and memory. */ | |
61a55e8b | 5037 | |
4fb4e4b8 DE |
5038 | int |
5039 | function_arg_partial_nregs (cum, mode, type, named) | |
5040 | const CUMULATIVE_ARGS *cum; | |
5041 | enum machine_mode mode; | |
5042 | tree type; | |
5043 | int named; | |
5044 | { | |
5045 | int slotno, regno, padding; | |
61a55e8b | 5046 | |
4fb4e4b8 DE |
5047 | /* We pass 0 for incoming_p here, it doesn't matter. */ |
5048 | slotno = function_arg_slotno (cum, mode, type, named, 0, ®no, &padding); | |
5049 | ||
5050 | if (slotno == -1) | |
5051 | return 0; | |
5052 | ||
5053 | if (TARGET_ARCH32) | |
bf62bbf1 | 5054 | { |
4fb4e4b8 DE |
5055 | if ((slotno + (mode == BLKmode |
5056 | ? ROUND_ADVANCE (int_size_in_bytes (type)) | |
5057 | : ROUND_ADVANCE (GET_MODE_SIZE (mode)))) | |
5058 | > NPARM_REGS (SImode)) | |
5059 | return NPARM_REGS (SImode) - slotno; | |
5060 | return 0; | |
5061 | } | |
5062 | else | |
5063 | { | |
5064 | if (type && AGGREGATE_TYPE_P (type)) | |
5065 | { | |
5066 | int size = int_size_in_bytes (type); | |
5067 | int align = TYPE_ALIGN (type); | |
bf62bbf1 | 5068 | |
4fb4e4b8 DE |
5069 | if (align == 16) |
5070 | slotno += slotno & 1; | |
5071 | if (size > 8 && size <= 16 | |
5072 | && slotno == SPARC_INT_ARG_MAX - 1) | |
5073 | return 1; | |
5074 | } | |
5075 | else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_INT | |
5076 | || (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT | |
5077 | && ! TARGET_FPU)) | |
5078 | { | |
5079 | if (GET_MODE_ALIGNMENT (mode) == 128) | |
5080 | { | |
5081 | slotno += slotno & 1; | |
5082 | if (slotno == SPARC_INT_ARG_MAX - 2) | |
5083 | return 1; | |
5084 | } | |
5085 | else | |
5086 | { | |
5087 | if (slotno == SPARC_INT_ARG_MAX - 1) | |
5088 | return 1; | |
5089 | } | |
5090 | } | |
5091 | else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT) | |
5092 | { | |
5093 | if (GET_MODE_ALIGNMENT (mode) == 128) | |
5094 | slotno += slotno & 1; | |
5095 | if ((slotno + GET_MODE_SIZE (mode) / UNITS_PER_WORD) | |
5096 | > SPARC_FP_ARG_MAX) | |
5097 | return 1; | |
5098 | } | |
5099 | return 0; | |
bf62bbf1 | 5100 | } |
4fb4e4b8 | 5101 | } |
61a55e8b | 5102 | |
4fb4e4b8 DE |
5103 | /* Handle the FUNCTION_ARG_PASS_BY_REFERENCE macro. |
5104 | !v9: The SPARC ABI stipulates passing struct arguments (of any size) and | |
5105 | quad-precision floats by invisible reference. | |
82d6b402 | 5106 | v9: Aggregates greater than 16 bytes are passed by reference. |
4fb4e4b8 DE |
5107 | For Pascal, also pass arrays by reference. */ |
5108 | ||
5109 | int | |
5110 | function_arg_pass_by_reference (cum, mode, type, named) | |
db3d4438 | 5111 | const CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED; |
4fb4e4b8 DE |
5112 | enum machine_mode mode; |
5113 | tree type; | |
db3d4438 | 5114 | int named ATTRIBUTE_UNUSED; |
4fb4e4b8 DE |
5115 | { |
5116 | if (TARGET_ARCH32) | |
eadceb59 | 5117 | { |
5e9defae | 5118 | return ((type && AGGREGATE_TYPE_P (type)) |
4fb4e4b8 DE |
5119 | || mode == TFmode || mode == TCmode); |
5120 | } | |
5121 | else | |
5122 | { | |
5123 | return ((type && TREE_CODE (type) == ARRAY_TYPE) | |
80ffc95e | 5124 | /* Consider complex values as aggregates, so care for TCmode. */ |
82d6b402 | 5125 | || GET_MODE_SIZE (mode) > 16 |
f36dea3c RH |
5126 | || (type |
5127 | && AGGREGATE_TYPE_P (type) | |
5128 | && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 16)); | |
4fb4e4b8 DE |
5129 | } |
5130 | } | |
5131 | ||
5132 | /* Handle the FUNCTION_ARG_ADVANCE macro. | |
5133 | Update the data in CUM to advance over an argument | |
5134 | of mode MODE and data type TYPE. | |
5135 | TYPE is null for libcalls where that information may not be available. */ | |
5136 | ||
5137 | void | |
5138 | function_arg_advance (cum, mode, type, named) | |
5139 | CUMULATIVE_ARGS *cum; | |
5140 | enum machine_mode mode; | |
5141 | tree type; | |
5142 | int named; | |
5143 | { | |
5144 | int slotno, regno, padding; | |
5145 | ||
5146 | /* We pass 0 for incoming_p here, it doesn't matter. */ | |
5147 | slotno = function_arg_slotno (cum, mode, type, named, 0, ®no, &padding); | |
5148 | ||
5149 | /* If register required leading padding, add it. */ | |
5150 | if (slotno != -1) | |
5151 | cum->words += padding; | |
eadceb59 | 5152 | |
4fb4e4b8 DE |
5153 | if (TARGET_ARCH32) |
5154 | { | |
5155 | cum->words += (mode != BLKmode | |
5156 | ? ROUND_ADVANCE (GET_MODE_SIZE (mode)) | |
5157 | : ROUND_ADVANCE (int_size_in_bytes (type))); | |
5158 | } | |
5159 | else | |
5160 | { | |
5161 | if (type && AGGREGATE_TYPE_P (type)) | |
5162 | { | |
5163 | int size = int_size_in_bytes (type); | |
5164 | ||
5165 | if (size <= 8) | |
5166 | ++cum->words; | |
5167 | else if (size <= 16) | |
5168 | cum->words += 2; | |
5169 | else /* passed by reference */ | |
5170 | ++cum->words; | |
5171 | } | |
5172 | else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_INT) | |
5173 | { | |
5174 | cum->words += 2; | |
5175 | } | |
5176 | else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT) | |
5177 | { | |
5178 | cum->words += GET_MODE_SIZE (mode) / UNITS_PER_WORD; | |
5179 | } | |
5180 | else | |
5181 | { | |
5182 | cum->words += (mode != BLKmode | |
5183 | ? ROUND_ADVANCE (GET_MODE_SIZE (mode)) | |
5184 | : ROUND_ADVANCE (int_size_in_bytes (type))); | |
5185 | } | |
eadceb59 | 5186 | } |
4fb4e4b8 | 5187 | } |
eadceb59 | 5188 | |
4fb4e4b8 DE |
5189 | /* Handle the FUNCTION_ARG_PADDING macro. |
5190 | For the 64 bit ABI structs are always stored left shifted in their | |
5191 | argument slot. */ | |
5192 | ||
5193 | enum direction | |
5194 | function_arg_padding (mode, type) | |
5195 | enum machine_mode mode; | |
5196 | tree type; | |
5197 | { | |
c85f7c16 JL |
5198 | if (TARGET_ARCH64 && type != 0 && AGGREGATE_TYPE_P (type)) |
5199 | return upward; | |
61a55e8b | 5200 | |
4fb4e4b8 DE |
5201 | /* This is the default definition. */ |
5202 | return (! BYTES_BIG_ENDIAN | |
5203 | ? upward | |
5204 | : ((mode == BLKmode | |
5205 | ? (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST | |
5206 | && int_size_in_bytes (type) < (PARM_BOUNDARY / BITS_PER_UNIT)) | |
5207 | : GET_MODE_BITSIZE (mode) < PARM_BOUNDARY) | |
5208 | ? downward : upward)); | |
61a55e8b | 5209 | } |
82d6b402 RH |
5210 | |
5211 | /* Handle FUNCTION_VALUE, FUNCTION_OUTGOING_VALUE, and LIBCALL_VALUE macros. | |
5212 | For v9, function return values are subject to the same rules as arguments, | |
5213 | except that up to 32-bytes may be returned in registers. */ | |
5214 | ||
5215 | rtx | |
5216 | function_value (type, mode, incoming_p) | |
5217 | tree type; | |
5218 | enum machine_mode mode; | |
5219 | int incoming_p; | |
5220 | { | |
5221 | int regno; | |
5222 | int regbase = (incoming_p | |
5223 | ? SPARC_OUTGOING_INT_ARG_FIRST | |
5224 | : SPARC_INCOMING_INT_ARG_FIRST); | |
5225 | ||
5226 | if (TARGET_ARCH64 && type) | |
5227 | { | |
5228 | if (TREE_CODE (type) == RECORD_TYPE) | |
5229 | { | |
5230 | /* Structures up to 32 bytes in size are passed in registers, | |
5231 | promoted to fp registers where possible. */ | |
5232 | ||
5233 | if (int_size_in_bytes (type) > 32) | |
5234 | abort (); /* shouldn't get here */ | |
5235 | ||
1eac9f59 | 5236 | return function_arg_record_value (type, mode, 0, 1, regbase); |
82d6b402 | 5237 | } |
8a7199ad | 5238 | else if (AGGREGATE_TYPE_P (type)) |
82d6b402 | 5239 | { |
8a7199ad RK |
5240 | /* All other aggregate types are passed in an integer register |
5241 | in a mode corresponding to the size of the type. */ | |
5242 | HOST_WIDE_INT bytes = int_size_in_bytes (type); | |
82d6b402 RH |
5243 | |
5244 | if (bytes > 32) | |
5245 | abort (); | |
5246 | ||
5247 | mode = mode_for_size (bytes * BITS_PER_UNIT, MODE_INT, 0); | |
5248 | } | |
5249 | } | |
3c6088d2 JJ |
5250 | |
5251 | if (TARGET_ARCH64 | |
5252 | && GET_MODE_CLASS (mode) == MODE_INT | |
5253 | && GET_MODE_SIZE (mode) < UNITS_PER_WORD | |
8a7199ad | 5254 | && type && ! AGGREGATE_TYPE_P (type)) |
3c6088d2 | 5255 | mode = DImode; |
82d6b402 RH |
5256 | |
5257 | if (incoming_p) | |
5258 | regno = BASE_RETURN_VALUE_REG (mode); | |
5259 | else | |
5260 | regno = BASE_OUTGOING_VALUE_REG (mode); | |
5261 | ||
254110c2 | 5262 | return gen_rtx_REG (mode, regno); |
82d6b402 RH |
5263 | } |
5264 | ||
648d2ffc RH |
5265 | /* Do what is necessary for `va_start'. We look at the current function |
5266 | to determine if stdarg or varargs is used and return the address of | |
5267 | the first unnamed parameter. */ | |
3ea1fdd3 JW |
5268 | |
5269 | rtx | |
648d2ffc | 5270 | sparc_builtin_saveregs () |
3ea1fdd3 | 5271 | { |
4fb4e4b8 | 5272 | int first_reg = current_function_args_info.words; |
3ea1fdd3 JW |
5273 | rtx address; |
5274 | int regno; | |
5275 | ||
4fb4e4b8 | 5276 | for (regno = first_reg; regno < NPARM_REGS (word_mode); regno++) |
254110c2 | 5277 | emit_move_insn (gen_rtx_MEM (word_mode, |
8ac61af7 RK |
5278 | gen_rtx_PLUS (Pmode, |
5279 | frame_pointer_rtx, | |
563c12b0 | 5280 | GEN_INT (FIRST_PARM_OFFSET (0) |
8ac61af7 RK |
5281 | + (UNITS_PER_WORD |
5282 | * regno)))), | |
254110c2 | 5283 | gen_rtx_REG (word_mode, |
8ac61af7 | 5284 | BASE_INCOMING_ARG_REG (word_mode) + regno)); |
3ea1fdd3 | 5285 | |
254110c2 | 5286 | address = gen_rtx_PLUS (Pmode, |
8ac61af7 | 5287 | frame_pointer_rtx, |
563c12b0 | 5288 | GEN_INT (FIRST_PARM_OFFSET (0) |
8ac61af7 | 5289 | + UNITS_PER_WORD * first_reg)); |
3ea1fdd3 JW |
5290 | |
5291 | return address; | |
5292 | } | |
a8b2c8a1 RH |
5293 | |
5294 | /* Implement `va_start' for varargs and stdarg. */ | |
5295 | ||
5296 | void | |
e5faf155 | 5297 | sparc_va_start (valist, nextarg) |
a8b2c8a1 RH |
5298 | tree valist; |
5299 | rtx nextarg; | |
5300 | { | |
5301 | nextarg = expand_builtin_saveregs (); | |
e5faf155 | 5302 | std_expand_builtin_va_start (valist, nextarg); |
a8b2c8a1 RH |
5303 | } |
5304 | ||
5305 | /* Implement `va_arg'. */ | |
5306 | ||
5307 | rtx | |
5308 | sparc_va_arg (valist, type) | |
5309 | tree valist, type; | |
5310 | { | |
5311 | HOST_WIDE_INT size, rsize, align; | |
da09e317 | 5312 | tree addr, incr; |
a8b2c8a1 RH |
5313 | rtx addr_rtx; |
5314 | int indirect = 0; | |
5315 | ||
5316 | /* Round up sizeof(type) to a word. */ | |
5317 | size = int_size_in_bytes (type); | |
5318 | rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD; | |
5319 | align = 0; | |
5320 | ||
5321 | if (TARGET_ARCH64) | |
5322 | { | |
fbd039b2 | 5323 | if (TYPE_ALIGN (type) >= 2 * (unsigned) BITS_PER_WORD) |
a8b2c8a1 RH |
5324 | align = 2 * UNITS_PER_WORD; |
5325 | ||
f34e52f7 | 5326 | if (AGGREGATE_TYPE_P (type)) |
a8b2c8a1 | 5327 | { |
f36dea3c | 5328 | if ((unsigned HOST_WIDE_INT) size > 16) |
f34e52f7 JJ |
5329 | { |
5330 | indirect = 1; | |
5331 | size = rsize = UNITS_PER_WORD; | |
5332 | } | |
014c0998 JJ |
5333 | /* SPARC v9 ABI states that structures up to 8 bytes in size are |
5334 | given one 8 byte slot. */ | |
5335 | else if (size == 0) | |
5336 | size = rsize = UNITS_PER_WORD; | |
f34e52f7 JJ |
5337 | else |
5338 | size = rsize; | |
a8b2c8a1 RH |
5339 | } |
5340 | } | |
5341 | else | |
5342 | { | |
5343 | if (AGGREGATE_TYPE_P (type) | |
5344 | || TYPE_MODE (type) == TFmode | |
5345 | || TYPE_MODE (type) == TCmode) | |
5346 | { | |
5347 | indirect = 1; | |
5348 | size = rsize = UNITS_PER_WORD; | |
5349 | } | |
a8b2c8a1 RH |
5350 | } |
5351 | ||
5352 | incr = valist; | |
5353 | if (align) | |
5354 | { | |
5355 | incr = fold (build (PLUS_EXPR, ptr_type_node, incr, | |
5356 | build_int_2 (align - 1, 0))); | |
5357 | incr = fold (build (BIT_AND_EXPR, ptr_type_node, incr, | |
5358 | build_int_2 (-align, -1))); | |
5359 | } | |
5360 | ||
5361 | addr = incr = save_expr (incr); | |
5362 | if (BYTES_BIG_ENDIAN && size < rsize) | |
5363 | { | |
5364 | addr = fold (build (PLUS_EXPR, ptr_type_node, incr, | |
5365 | build_int_2 (rsize - size, 0))); | |
5366 | } | |
5367 | incr = fold (build (PLUS_EXPR, ptr_type_node, incr, | |
5368 | build_int_2 (rsize, 0))); | |
5369 | ||
5370 | incr = build (MODIFY_EXPR, ptr_type_node, valist, incr); | |
5371 | TREE_SIDE_EFFECTS (incr) = 1; | |
5372 | expand_expr (incr, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
5373 | ||
5374 | addr_rtx = expand_expr (addr, NULL, Pmode, EXPAND_NORMAL); | |
5375 | ||
9a0662b4 GK |
5376 | /* If the address isn't aligned properly for the type, |
5377 | we may need to copy to a temporary. | |
5378 | FIXME: This is inefficient. Usually we can do this | |
5379 | in registers. */ | |
5380 | if (align == 0 | |
5381 | && TYPE_ALIGN (type) > BITS_PER_WORD | |
5382 | && !indirect) | |
5383 | { | |
5384 | /* FIXME: We really need to specify that the temporary is live | |
5385 | for the whole function because expand_builtin_va_arg wants | |
5386 | the alias set to be get_varargs_alias_set (), but in this | |
5387 | case the alias set is that for TYPE and if the memory gets | |
5388 | reused it will be reused with alias set TYPE. */ | |
5389 | rtx tmp = assign_temp (type, 0, 1, 0); | |
5390 | rtx dest_addr; | |
5391 | ||
5392 | addr_rtx = force_reg (Pmode, addr_rtx); | |
5393 | addr_rtx = gen_rtx_MEM (BLKmode, addr_rtx); | |
ba4828e0 | 5394 | set_mem_alias_set (addr_rtx, get_varargs_alias_set ()); |
8ac61af7 | 5395 | set_mem_align (addr_rtx, BITS_PER_WORD); |
9a0662b4 GK |
5396 | tmp = shallow_copy_rtx (tmp); |
5397 | PUT_MODE (tmp, BLKmode); | |
ba4828e0 | 5398 | set_mem_alias_set (tmp, 0); |
9a0662b4 | 5399 | |
44bb111a RH |
5400 | dest_addr = emit_block_move (tmp, addr_rtx, GEN_INT (rsize), |
5401 | BLOCK_OP_NORMAL); | |
9a0662b4 GK |
5402 | if (dest_addr != NULL_RTX) |
5403 | addr_rtx = dest_addr; | |
5404 | else | |
5405 | addr_rtx = XCEXP (tmp, 0, MEM); | |
5406 | } | |
5407 | ||
a8b2c8a1 RH |
5408 | if (indirect) |
5409 | { | |
5410 | addr_rtx = force_reg (Pmode, addr_rtx); | |
5411 | addr_rtx = gen_rtx_MEM (Pmode, addr_rtx); | |
ba4828e0 | 5412 | set_mem_alias_set (addr_rtx, get_varargs_alias_set ()); |
a8b2c8a1 RH |
5413 | } |
5414 | ||
5415 | return addr_rtx; | |
5416 | } | |
ab835497 RK |
5417 | \f |
5418 | /* Return the string to output a conditional branch to LABEL, which is | |
c4ce6853 DE |
5419 | the operand number of the label. OP is the conditional expression. |
5420 | XEXP (OP, 0) is assumed to be a condition code register (integer or | |
5421 | floating point) and its mode specifies what kind of comparison we made. | |
61a55e8b | 5422 | |
5e7a8ee0 | 5423 | REVERSED is nonzero if we should reverse the sense of the comparison. |
ab835497 | 5424 | |
5e7a8ee0 | 5425 | ANNUL is nonzero if we should generate an annulling branch. |
ab835497 | 5426 | |
5e7a8ee0 | 5427 | NOOP is nonzero if we have to follow this branch by a noop. |
c6b0465b JC |
5428 | |
5429 | INSN, if set, is the insn. */ | |
ab835497 RK |
5430 | |
5431 | char * | |
0b82d204 JJ |
5432 | output_cbranch (op, dest, label, reversed, annul, noop, insn) |
5433 | rtx op, dest; | |
ab835497 RK |
5434 | int label; |
5435 | int reversed, annul, noop; | |
c6b0465b | 5436 | rtx insn; |
ab835497 | 5437 | { |
0b82d204 | 5438 | static char string[50]; |
ab835497 | 5439 | enum rtx_code code = GET_CODE (op); |
c4ce6853 DE |
5440 | rtx cc_reg = XEXP (op, 0); |
5441 | enum machine_mode mode = GET_MODE (cc_reg); | |
0b82d204 JJ |
5442 | const char *labelno, *branch; |
5443 | int spaces = 8, far; | |
5444 | char *p; | |
5445 | ||
5446 | /* v9 branches are limited to +-1MB. If it is too far away, | |
5447 | change | |
5448 | ||
5449 | bne,pt %xcc, .LC30 | |
5450 | ||
5451 | to | |
5452 | ||
5453 | be,pn %xcc, .+12 | |
5454 | nop | |
5455 | ba .LC30 | |
5456 | ||
5457 | and | |
5458 | ||
5459 | fbne,a,pn %fcc2, .LC29 | |
61a55e8b | 5460 | |
0b82d204 JJ |
5461 | to |
5462 | ||
5463 | fbe,pt %fcc2, .+16 | |
5464 | nop | |
5465 | ba .LC29 */ | |
5466 | ||
5467 | far = get_attr_length (insn) >= 3; | |
5468 | if (reversed ^ far) | |
ab835497 | 5469 | { |
e267e177 RH |
5470 | /* Reversal of FP compares takes care -- an ordered compare |
5471 | becomes an unordered compare and vice versa. */ | |
4d449554 | 5472 | if (mode == CCFPmode || mode == CCFPEmode) |
7913f3d0 | 5473 | code = reverse_condition_maybe_unordered (code); |
ab835497 | 5474 | else |
e267e177 | 5475 | code = reverse_condition (code); |
ab835497 RK |
5476 | } |
5477 | ||
e267e177 RH |
5478 | /* Start by writing the branch condition. */ |
5479 | if (mode == CCFPmode || mode == CCFPEmode) | |
5850dc00 RH |
5480 | { |
5481 | switch (code) | |
5482 | { | |
5483 | case NE: | |
5484 | branch = "fbne"; | |
5485 | break; | |
5486 | case EQ: | |
5487 | branch = "fbe"; | |
5488 | break; | |
5489 | case GE: | |
5490 | branch = "fbge"; | |
5491 | break; | |
5492 | case GT: | |
5493 | branch = "fbg"; | |
5494 | break; | |
5495 | case LE: | |
5496 | branch = "fble"; | |
5497 | break; | |
5498 | case LT: | |
5499 | branch = "fbl"; | |
5500 | break; | |
5501 | case UNORDERED: | |
5502 | branch = "fbu"; | |
5503 | break; | |
5504 | case ORDERED: | |
5505 | branch = "fbo"; | |
5506 | break; | |
5507 | case UNGT: | |
5508 | branch = "fbug"; | |
5509 | break; | |
5510 | case UNLT: | |
5511 | branch = "fbul"; | |
5512 | break; | |
5513 | case UNEQ: | |
5514 | branch = "fbue"; | |
5515 | break; | |
5516 | case UNGE: | |
5517 | branch = "fbuge"; | |
5518 | break; | |
5519 | case UNLE: | |
5520 | branch = "fbule"; | |
5521 | break; | |
5522 | case LTGT: | |
5523 | branch = "fblg"; | |
5524 | break; | |
5525 | ||
5526 | default: | |
5527 | abort (); | |
5528 | } | |
5529 | ||
5530 | /* ??? !v9: FP branches cannot be preceded by another floating point | |
5531 | insn. Because there is currently no concept of pre-delay slots, | |
5532 | we can fix this only by always emitting a nop before a floating | |
5533 | point branch. */ | |
5534 | ||
5535 | string[0] = '\0'; | |
5536 | if (! TARGET_V9) | |
5537 | strcpy (string, "nop\n\t"); | |
5538 | strcat (string, branch); | |
5539 | } | |
e267e177 | 5540 | else |
5850dc00 RH |
5541 | { |
5542 | switch (code) | |
5543 | { | |
5544 | case NE: | |
5545 | branch = "bne"; | |
5546 | break; | |
5547 | case EQ: | |
5548 | branch = "be"; | |
5549 | break; | |
5550 | case GE: | |
0b82d204 | 5551 | if (mode == CC_NOOVmode || mode == CCX_NOOVmode) |
5850dc00 RH |
5552 | branch = "bpos"; |
5553 | else | |
5554 | branch = "bge"; | |
5555 | break; | |
5556 | case GT: | |
5557 | branch = "bg"; | |
5558 | break; | |
5559 | case LE: | |
5560 | branch = "ble"; | |
5561 | break; | |
5562 | case LT: | |
0b82d204 | 5563 | if (mode == CC_NOOVmode || mode == CCX_NOOVmode) |
5850dc00 RH |
5564 | branch = "bneg"; |
5565 | else | |
5566 | branch = "bl"; | |
5567 | break; | |
5568 | case GEU: | |
5569 | branch = "bgeu"; | |
5570 | break; | |
5571 | case GTU: | |
5572 | branch = "bgu"; | |
5573 | break; | |
5574 | case LEU: | |
5575 | branch = "bleu"; | |
5576 | break; | |
5577 | case LTU: | |
5578 | branch = "blu"; | |
5579 | break; | |
5580 | ||
5581 | default: | |
5582 | abort (); | |
5583 | } | |
5584 | strcpy (string, branch); | |
5585 | } | |
e267e177 | 5586 | spaces -= strlen (branch); |
0b82d204 | 5587 | p = strchr (string, '\0'); |
e267e177 | 5588 | |
ab835497 | 5589 | /* Now add the annulling, the label, and a possible noop. */ |
0b82d204 | 5590 | if (annul && ! far) |
e0d80184 | 5591 | { |
0b82d204 JJ |
5592 | strcpy (p, ",a"); |
5593 | p += 2; | |
e0d80184 DM |
5594 | spaces -= 2; |
5595 | } | |
ab835497 | 5596 | |
61a55e8b | 5597 | if (! TARGET_V9) |
0b82d204 | 5598 | labelno = ""; |
61a55e8b DE |
5599 | else |
5600 | { | |
c6b0465b | 5601 | rtx note; |
0b82d204 | 5602 | int v8 = 0; |
c6b0465b | 5603 | |
0b82d204 | 5604 | if (! far && insn && INSN_ADDRESSES_SET_P ()) |
e0d80184 | 5605 | { |
0b82d204 JJ |
5606 | int delta = (INSN_ADDRESSES (INSN_UID (dest)) |
5607 | - INSN_ADDRESSES (INSN_UID (insn))); | |
5608 | /* Leave some instructions for "slop". */ | |
5609 | if (delta < -260000 || delta >= 260000) | |
5610 | v8 = 1; | |
e0d80184 | 5611 | } |
c6b0465b | 5612 | |
61a55e8b DE |
5613 | if (mode == CCFPmode || mode == CCFPEmode) |
5614 | { | |
0b82d204 | 5615 | static char v9_fcc_labelno[] = "%%fccX, "; |
61a55e8b | 5616 | /* Set the char indicating the number of the fcc reg to use. */ |
0b82d204 JJ |
5617 | v9_fcc_labelno[5] = REGNO (cc_reg) - SPARC_FIRST_V9_FCC_REG + '0'; |
5618 | labelno = v9_fcc_labelno; | |
5619 | if (v8) | |
5620 | { | |
5621 | if (REGNO (cc_reg) == SPARC_FCC_REG) | |
5622 | labelno = ""; | |
5623 | else | |
5624 | abort (); | |
5625 | } | |
61a55e8b DE |
5626 | } |
5627 | else if (mode == CCXmode || mode == CCX_NOOVmode) | |
0b82d204 JJ |
5628 | { |
5629 | labelno = "%%xcc, "; | |
5630 | if (v8) | |
5631 | abort (); | |
5632 | } | |
61a55e8b | 5633 | else |
0b82d204 JJ |
5634 | { |
5635 | labelno = "%%icc, "; | |
5636 | if (v8) | |
5637 | labelno = ""; | |
5638 | } | |
5639 | ||
4f31cce8 | 5640 | if (*labelno && insn && (note = find_reg_note (insn, REG_BR_PROB, NULL_RTX))) |
0b82d204 JJ |
5641 | { |
5642 | strcpy (p, | |
4f31cce8 | 5643 | ((INTVAL (XEXP (note, 0)) >= REG_BR_PROB_BASE / 2) ^ far) |
0b82d204 JJ |
5644 | ? ",pt" : ",pn"); |
5645 | p += 3; | |
5646 | spaces -= 3; | |
5647 | } | |
61a55e8b | 5648 | } |
e0d80184 | 5649 | if (spaces > 0) |
0b82d204 | 5650 | *p++ = '\t'; |
e0d80184 | 5651 | else |
0b82d204 JJ |
5652 | *p++ = ' '; |
5653 | strcpy (p, labelno); | |
5654 | p = strchr (p, '\0'); | |
5655 | if (far) | |
5656 | { | |
5657 | strcpy (p, ".+12\n\tnop\n\tb\t"); | |
5658 | if (annul || noop) | |
5659 | p[3] = '6'; | |
5660 | p += 13; | |
5661 | } | |
5662 | *p++ = '%'; | |
5663 | *p++ = 'l'; | |
5664 | /* Set the char indicating the number of the operand containing the | |
5665 | label_ref. */ | |
5666 | *p++ = label + '0'; | |
5667 | *p = '\0'; | |
61a55e8b | 5668 | if (noop) |
0b82d204 | 5669 | strcpy (p, "\n\tnop"); |
61a55e8b DE |
5670 | |
5671 | return string; | |
5672 | } | |
5673 | ||
47ac041c JJ |
5674 | /* Emit a library call comparison between floating point X and Y. |
5675 | COMPARISON is the rtl operator to compare with (EQ, NE, GT, etc.). | |
5676 | TARGET_ARCH64 uses _Qp_* functions, which use pointers to TFmode | |
5677 | values as arguments instead of the TFmode registers themselves, | |
5678 | that's why we cannot call emit_float_lib_cmp. */ | |
5679 | void | |
5680 | sparc_emit_float_lib_cmp (x, y, comparison) | |
5681 | rtx x, y; | |
5682 | enum rtx_code comparison; | |
5683 | { | |
e77d72cb | 5684 | const char *qpfunc; |
5c5c34a4 JJ |
5685 | rtx slot0, slot1, result, tem, tem2; |
5686 | enum machine_mode mode; | |
47ac041c JJ |
5687 | |
5688 | switch (comparison) | |
5689 | { | |
5690 | case EQ: | |
5c5c34a4 | 5691 | qpfunc = (TARGET_ARCH64) ? "_Qp_feq" : "_Q_feq"; |
47ac041c JJ |
5692 | break; |
5693 | ||
5694 | case NE: | |
5c5c34a4 | 5695 | qpfunc = (TARGET_ARCH64) ? "_Qp_fne" : "_Q_fne"; |
47ac041c JJ |
5696 | break; |
5697 | ||
5698 | case GT: | |
5c5c34a4 | 5699 | qpfunc = (TARGET_ARCH64) ? "_Qp_fgt" : "_Q_fgt"; |
47ac041c JJ |
5700 | break; |
5701 | ||
5702 | case GE: | |
5c5c34a4 | 5703 | qpfunc = (TARGET_ARCH64) ? "_Qp_fge" : "_Q_fge"; |
47ac041c JJ |
5704 | break; |
5705 | ||
5706 | case LT: | |
5c5c34a4 | 5707 | qpfunc = (TARGET_ARCH64) ? "_Qp_flt" : "_Q_flt"; |
47ac041c JJ |
5708 | break; |
5709 | ||
5710 | case LE: | |
5c5c34a4 JJ |
5711 | qpfunc = (TARGET_ARCH64) ? "_Qp_fle" : "_Q_fle"; |
5712 | break; | |
5713 | ||
5714 | case ORDERED: | |
5715 | case UNORDERED: | |
5716 | case UNGT: | |
5717 | case UNLT: | |
5718 | case UNEQ: | |
5719 | case UNGE: | |
5720 | case UNLE: | |
5721 | case LTGT: | |
5722 | qpfunc = (TARGET_ARCH64) ? "_Qp_cmp" : "_Q_cmp"; | |
47ac041c JJ |
5723 | break; |
5724 | ||
5725 | default: | |
5726 | abort(); | |
5727 | break; | |
5728 | } | |
5729 | ||
5c5c34a4 | 5730 | if (TARGET_ARCH64) |
47ac041c | 5731 | { |
5c5c34a4 JJ |
5732 | if (GET_CODE (x) != MEM) |
5733 | { | |
5734 | slot0 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0); | |
5735 | emit_insn (gen_rtx_SET (VOIDmode, slot0, x)); | |
5736 | } | |
5737 | else | |
5738 | slot0 = x; | |
5739 | ||
5740 | if (GET_CODE (y) != MEM) | |
5741 | { | |
5742 | slot1 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0); | |
5743 | emit_insn (gen_rtx_SET (VOIDmode, slot1, y)); | |
5744 | } | |
5745 | else | |
5746 | slot1 = y; | |
47ac041c | 5747 | |
eb29ddb6 | 5748 | emit_library_call (gen_rtx_SYMBOL_REF (Pmode, qpfunc), LCT_NORMAL, |
5c5c34a4 JJ |
5749 | DImode, 2, |
5750 | XEXP (slot0, 0), Pmode, | |
5751 | XEXP (slot1, 0), Pmode); | |
5752 | ||
5753 | mode = DImode; | |
5754 | } | |
5755 | else | |
47ac041c | 5756 | { |
eb29ddb6 | 5757 | emit_library_call (gen_rtx_SYMBOL_REF (Pmode, qpfunc), LCT_NORMAL, |
5c5c34a4 JJ |
5758 | SImode, 2, |
5759 | x, TFmode, y, TFmode); | |
5760 | ||
5761 | mode = SImode; | |
47ac041c JJ |
5762 | } |
5763 | ||
47ac041c JJ |
5764 | |
5765 | /* Immediately move the result of the libcall into a pseudo | |
5766 | register so reload doesn't clobber the value if it needs | |
5767 | the return register for a spill reg. */ | |
5c5c34a4 JJ |
5768 | result = gen_reg_rtx (mode); |
5769 | emit_move_insn (result, hard_libcall_value (mode)); | |
47ac041c | 5770 | |
5c5c34a4 JJ |
5771 | switch (comparison) |
5772 | { | |
5773 | default: | |
3b2d1507 | 5774 | emit_cmp_insn (result, const0_rtx, NE, NULL_RTX, mode, 0); |
5c5c34a4 JJ |
5775 | break; |
5776 | case ORDERED: | |
5777 | case UNORDERED: | |
3b2d1507 AT |
5778 | emit_cmp_insn (result, GEN_INT(3), comparison == UNORDERED ? EQ : NE, |
5779 | NULL_RTX, mode, 0); | |
5c5c34a4 JJ |
5780 | break; |
5781 | case UNGT: | |
5782 | case UNGE: | |
5783 | emit_cmp_insn (result, const1_rtx, | |
3b2d1507 | 5784 | comparison == UNGT ? GT : NE, NULL_RTX, mode, 0); |
5c5c34a4 JJ |
5785 | break; |
5786 | case UNLE: | |
3b2d1507 | 5787 | emit_cmp_insn (result, const2_rtx, NE, NULL_RTX, mode, 0); |
5c5c34a4 JJ |
5788 | break; |
5789 | case UNLT: | |
5790 | tem = gen_reg_rtx (mode); | |
5791 | if (TARGET_ARCH32) | |
5792 | emit_insn (gen_andsi3 (tem, result, const1_rtx)); | |
5793 | else | |
5794 | emit_insn (gen_anddi3 (tem, result, const1_rtx)); | |
3b2d1507 | 5795 | emit_cmp_insn (tem, const0_rtx, NE, NULL_RTX, mode, 0); |
5c5c34a4 JJ |
5796 | break; |
5797 | case UNEQ: | |
5798 | case LTGT: | |
5799 | tem = gen_reg_rtx (mode); | |
5800 | if (TARGET_ARCH32) | |
5801 | emit_insn (gen_addsi3 (tem, result, const1_rtx)); | |
5802 | else | |
5803 | emit_insn (gen_adddi3 (tem, result, const1_rtx)); | |
5804 | tem2 = gen_reg_rtx (mode); | |
5805 | if (TARGET_ARCH32) | |
5806 | emit_insn (gen_andsi3 (tem2, tem, const2_rtx)); | |
5807 | else | |
5808 | emit_insn (gen_anddi3 (tem2, tem, const2_rtx)); | |
3b2d1507 AT |
5809 | emit_cmp_insn (tem2, const0_rtx, comparison == UNEQ ? EQ : NE, |
5810 | NULL_RTX, mode, 0); | |
5c5c34a4 JJ |
5811 | break; |
5812 | } | |
47ac041c | 5813 | } |
5c5c34a4 | 5814 | |
d88e57d1 RH |
5815 | /* Generate an unsigned DImode to FP conversion. This is the same code |
5816 | optabs would emit if we didn't have TFmode patterns. */ | |
5817 | ||
5818 | void | |
5819 | sparc_emit_floatunsdi (operands) | |
5820 | rtx operands[2]; | |
5821 | { | |
5822 | rtx neglab, donelab, i0, i1, f0, in, out; | |
5823 | enum machine_mode mode; | |
5824 | ||
5825 | out = operands[0]; | |
5826 | in = force_reg (DImode, operands[1]); | |
5827 | mode = GET_MODE (out); | |
5828 | neglab = gen_label_rtx (); | |
5829 | donelab = gen_label_rtx (); | |
5830 | i0 = gen_reg_rtx (DImode); | |
5831 | i1 = gen_reg_rtx (DImode); | |
5832 | f0 = gen_reg_rtx (mode); | |
5833 | ||
5834 | emit_cmp_and_jump_insns (in, const0_rtx, LT, const0_rtx, DImode, 0, neglab); | |
5835 | ||
5836 | emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_FLOAT (mode, in))); | |
5837 | emit_jump_insn (gen_jump (donelab)); | |
5838 | emit_barrier (); | |
5839 | ||
5840 | emit_label (neglab); | |
5841 | ||
5842 | emit_insn (gen_lshrdi3 (i0, in, const1_rtx)); | |
5843 | emit_insn (gen_anddi3 (i1, in, const1_rtx)); | |
5844 | emit_insn (gen_iordi3 (i0, i0, i1)); | |
5845 | emit_insn (gen_rtx_SET (VOIDmode, f0, gen_rtx_FLOAT (mode, i0))); | |
5846 | emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_PLUS (mode, f0, f0))); | |
5847 | ||
5848 | emit_label (donelab); | |
5849 | } | |
5850 | ||
61a55e8b DE |
5851 | /* Return the string to output a conditional branch to LABEL, testing |
5852 | register REG. LABEL is the operand number of the label; REG is the | |
5853 | operand number of the reg. OP is the conditional expression. The mode | |
5854 | of REG says what kind of comparison we made. | |
5855 | ||
5e7a8ee0 | 5856 | REVERSED is nonzero if we should reverse the sense of the comparison. |
61a55e8b | 5857 | |
5e7a8ee0 | 5858 | ANNUL is nonzero if we should generate an annulling branch. |
61a55e8b | 5859 | |
5e7a8ee0 | 5860 | NOOP is nonzero if we have to follow this branch by a noop. */ |
61a55e8b DE |
5861 | |
5862 | char * | |
0b82d204 JJ |
5863 | output_v9branch (op, dest, reg, label, reversed, annul, noop, insn) |
5864 | rtx op, dest; | |
61a55e8b DE |
5865 | int reg, label; |
5866 | int reversed, annul, noop; | |
e0d80184 | 5867 | rtx insn; |
61a55e8b | 5868 | { |
0b82d204 | 5869 | static char string[50]; |
61a55e8b DE |
5870 | enum rtx_code code = GET_CODE (op); |
5871 | enum machine_mode mode = GET_MODE (XEXP (op, 0)); | |
e0d80184 | 5872 | rtx note; |
0b82d204 JJ |
5873 | int far; |
5874 | char *p; | |
5875 | ||
5876 | /* branch on register are limited to +-128KB. If it is too far away, | |
5877 | change | |
5878 | ||
5879 | brnz,pt %g1, .LC30 | |
5880 | ||
5881 | to | |
5882 | ||
5883 | brz,pn %g1, .+12 | |
5884 | nop | |
5885 | ba,pt %xcc, .LC30 | |
5886 | ||
5887 | and | |
5888 | ||
5889 | brgez,a,pn %o1, .LC29 | |
5890 | ||
5891 | to | |
5892 | ||
5893 | brlz,pt %o1, .+16 | |
5894 | nop | |
5895 | ba,pt %xcc, .LC29 */ | |
5896 | ||
5897 | far = get_attr_length (insn) >= 3; | |
61a55e8b DE |
5898 | |
5899 | /* If not floating-point or if EQ or NE, we can just reverse the code. */ | |
0b82d204 JJ |
5900 | if (reversed ^ far) |
5901 | code = reverse_condition (code); | |
61a55e8b DE |
5902 | |
5903 | /* Only 64 bit versions of these instructions exist. */ | |
5904 | if (mode != DImode) | |
5905 | abort (); | |
5906 | ||
5907 | /* Start by writing the branch condition. */ | |
5908 | ||
5909 | switch (code) | |
5910 | { | |
5911 | case NE: | |
5912 | strcpy (string, "brnz"); | |
5913 | break; | |
5914 | ||
5915 | case EQ: | |
5916 | strcpy (string, "brz"); | |
5917 | break; | |
5918 | ||
5919 | case GE: | |
5920 | strcpy (string, "brgez"); | |
5921 | break; | |
5922 | ||
5923 | case LT: | |
5924 | strcpy (string, "brlz"); | |
5925 | break; | |
5926 | ||
5927 | case LE: | |
5928 | strcpy (string, "brlez"); | |
5929 | break; | |
5930 | ||
5931 | case GT: | |
5932 | strcpy (string, "brgz"); | |
5933 | break; | |
5934 | ||
5935 | default: | |
5936 | abort (); | |
5937 | } | |
5938 | ||
0b82d204 JJ |
5939 | p = strchr (string, '\0'); |
5940 | ||
61a55e8b | 5941 | /* Now add the annulling, reg, label, and nop. */ |
0b82d204 | 5942 | if (annul && ! far) |
e0d80184 | 5943 | { |
0b82d204 JJ |
5944 | strcpy (p, ",a"); |
5945 | p += 2; | |
e0d80184 | 5946 | } |
61a55e8b | 5947 | |
4f31cce8 | 5948 | if (insn && (note = find_reg_note (insn, REG_BR_PROB, NULL_RTX))) |
e0d80184 | 5949 | { |
0b82d204 | 5950 | strcpy (p, |
4f31cce8 | 5951 | ((INTVAL (XEXP (note, 0)) >= REG_BR_PROB_BASE / 2) ^ far) |
0b82d204 JJ |
5952 | ? ",pt" : ",pn"); |
5953 | p += 3; | |
e0d80184 | 5954 | } |
61a55e8b | 5955 | |
0b82d204 JJ |
5956 | *p = p < string + 8 ? '\t' : ' '; |
5957 | p++; | |
5958 | *p++ = '%'; | |
5959 | *p++ = '0' + reg; | |
5960 | *p++ = ','; | |
5961 | *p++ = ' '; | |
5962 | if (far) | |
5963 | { | |
5964 | int veryfar = 1, delta; | |
5965 | ||
5966 | if (INSN_ADDRESSES_SET_P ()) | |
5967 | { | |
5968 | delta = (INSN_ADDRESSES (INSN_UID (dest)) | |
5969 | - INSN_ADDRESSES (INSN_UID (insn))); | |
5970 | /* Leave some instructions for "slop". */ | |
5971 | if (delta >= -260000 && delta < 260000) | |
5972 | veryfar = 0; | |
5973 | } | |
5974 | ||
5975 | strcpy (p, ".+12\n\tnop\n\t"); | |
5976 | if (annul || noop) | |
5977 | p[3] = '6'; | |
5978 | p += 11; | |
5979 | if (veryfar) | |
5980 | { | |
5981 | strcpy (p, "b\t"); | |
5982 | p += 2; | |
5983 | } | |
5984 | else | |
5985 | { | |
5986 | strcpy (p, "ba,pt\t%%xcc, "); | |
5987 | p += 13; | |
5988 | } | |
5989 | } | |
5990 | *p++ = '%'; | |
5991 | *p++ = 'l'; | |
5992 | *p++ = '0' + label; | |
5993 | *p = '\0'; | |
ab835497 RK |
5994 | |
5995 | if (noop) | |
0b82d204 | 5996 | strcpy (p, "\n\tnop"); |
ab835497 RK |
5997 | |
5998 | return string; | |
5999 | } | |
6000 | ||
e48addee JJ |
6001 | /* Return 1, if any of the registers of the instruction are %l[0-7] or %o[0-7]. |
6002 | Such instructions cannot be used in the delay slot of return insn on v9. | |
6003 | If TEST is 0, also rename all %i[0-7] registers to their %o[0-7] counterparts. | |
6004 | */ | |
284d86e9 | 6005 | |
e48addee JJ |
6006 | static int |
6007 | epilogue_renumber (where, test) | |
6008 | register rtx *where; | |
6009 | int test; | |
284d86e9 | 6010 | { |
e48addee JJ |
6011 | register const char *fmt; |
6012 | register int i; | |
6013 | register enum rtx_code code; | |
6014 | ||
6015 | if (*where == 0) | |
6016 | return 0; | |
6017 | ||
6018 | code = GET_CODE (*where); | |
284d86e9 JC |
6019 | |
6020 | switch (code) | |
6021 | { | |
284d86e9 | 6022 | case REG: |
e48addee JJ |
6023 | if (REGNO (*where) >= 8 && REGNO (*where) < 24) /* oX or lX */ |
6024 | return 1; | |
6025 | if (! test && REGNO (*where) >= 24 && REGNO (*where) < 32) | |
6026 | *where = gen_rtx (REG, GET_MODE (*where), OUTGOING_REGNO (REGNO(*where))); | |
6027 | case SCRATCH: | |
6028 | case CC0: | |
6029 | case PC: | |
284d86e9 JC |
6030 | case CONST_INT: |
6031 | case CONST_DOUBLE: | |
e48addee | 6032 | return 0; |
76a7c776 | 6033 | |
09ebda1b SC |
6034 | /* Do not replace the frame pointer with the stack pointer because |
6035 | it can cause the delayed instruction to load below the stack. | |
6036 | This occurs when instructions like: | |
6037 | ||
6038 | (set (reg/i:SI 24 %i0) | |
6039 | (mem/f:SI (plus:SI (reg/f:SI 30 %fp) | |
6040 | (const_int -20 [0xffffffec])) 0)) | |
6041 | ||
6042 | are in the return delayed slot. */ | |
6043 | case PLUS: | |
6044 | if (GET_CODE (XEXP (*where, 0)) == REG | |
563c12b0 | 6045 | && REGNO (XEXP (*where, 0)) == HARD_FRAME_POINTER_REGNUM |
09ebda1b SC |
6046 | && (GET_CODE (XEXP (*where, 1)) != CONST_INT |
6047 | || INTVAL (XEXP (*where, 1)) < SPARC_STACK_BIAS)) | |
6048 | return 1; | |
6049 | break; | |
6050 | ||
6051 | case MEM: | |
6052 | if (SPARC_STACK_BIAS | |
6053 | && GET_CODE (XEXP (*where, 0)) == REG | |
563c12b0 | 6054 | && REGNO (XEXP (*where, 0)) == HARD_FRAME_POINTER_REGNUM) |
09ebda1b SC |
6055 | return 1; |
6056 | break; | |
6057 | ||
76a7c776 DM |
6058 | default: |
6059 | break; | |
e48addee | 6060 | } |
284d86e9 | 6061 | |
e48addee | 6062 | fmt = GET_RTX_FORMAT (code); |
284d86e9 | 6063 | |
e48addee JJ |
6064 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) |
6065 | { | |
6066 | if (fmt[i] == 'E') | |
6067 | { | |
6068 | register int j; | |
6069 | for (j = XVECLEN (*where, i) - 1; j >= 0; j--) | |
6070 | if (epilogue_renumber (&(XVECEXP (*where, i, j)), test)) | |
6071 | return 1; | |
6072 | } | |
6073 | else if (fmt[i] == 'e' | |
6074 | && epilogue_renumber (&(XEXP (*where, i)), test)) | |
6075 | return 1; | |
284d86e9 | 6076 | } |
e48addee | 6077 | return 0; |
284d86e9 | 6078 | } |
ab835497 RK |
6079 | \f |
6080 | /* Leaf functions and non-leaf functions have different needs. */ | |
6081 | ||
8b60264b | 6082 | static const int |
ab835497 RK |
6083 | reg_leaf_alloc_order[] = REG_LEAF_ALLOC_ORDER; |
6084 | ||
8b60264b | 6085 | static const int |
ab835497 RK |
6086 | reg_nonleaf_alloc_order[] = REG_ALLOC_ORDER; |
6087 | ||
8b60264b | 6088 | static const int *const reg_alloc_orders[] = { |
ab835497 RK |
6089 | reg_leaf_alloc_order, |
6090 | reg_nonleaf_alloc_order}; | |
6091 | ||
6092 | void | |
6093 | order_regs_for_local_alloc () | |
6094 | { | |
6095 | static int last_order_nonleaf = 1; | |
6096 | ||
6097 | if (regs_ever_live[15] != last_order_nonleaf) | |
6098 | { | |
6099 | last_order_nonleaf = !last_order_nonleaf; | |
2e09e75a | 6100 | memcpy ((char *) reg_alloc_order, |
8b60264b | 6101 | (const char *) reg_alloc_orders[last_order_nonleaf], |
2e09e75a | 6102 | FIRST_PSEUDO_REGISTER * sizeof (int)); |
ab835497 RK |
6103 | } |
6104 | } | |
6105 | \f | |
e0d80184 DM |
6106 | /* Return 1 if REG and MEM are legitimate enough to allow the various |
6107 | mem<-->reg splits to be run. */ | |
6108 | ||
6109 | int | |
e61c29e9 | 6110 | sparc_splitdi_legitimate (reg, mem) |
e0d80184 DM |
6111 | rtx reg; |
6112 | rtx mem; | |
6113 | { | |
e0d80184 DM |
6114 | /* Punt if we are here by mistake. */ |
6115 | if (! reload_completed) | |
9208e4b2 | 6116 | abort (); |
e0d80184 DM |
6117 | |
6118 | /* We must have an offsettable memory reference. */ | |
6119 | if (! offsettable_memref_p (mem)) | |
6120 | return 0; | |
6121 | ||
6122 | /* If we have legitimate args for ldd/std, we do not want | |
6123 | the split to happen. */ | |
6124 | if ((REGNO (reg) % 2) == 0 | |
6125 | && mem_min_alignment (mem, 8)) | |
6126 | return 0; | |
6127 | ||
6128 | /* Success. */ | |
6129 | return 1; | |
6130 | } | |
6131 | ||
e61c29e9 DM |
6132 | /* Return 1 if x and y are some kind of REG and they refer to |
6133 | different hard registers. This test is guarenteed to be | |
6134 | run after reload. */ | |
6135 | ||
6136 | int | |
6137 | sparc_absnegfloat_split_legitimate (x, y) | |
6138 | rtx x, y; | |
6139 | { | |
e61c29e9 DM |
6140 | if (GET_CODE (x) != REG) |
6141 | return 0; | |
e61c29e9 DM |
6142 | if (GET_CODE (y) != REG) |
6143 | return 0; | |
6144 | if (REGNO (x) == REGNO (y)) | |
6145 | return 0; | |
6146 | return 1; | |
6147 | } | |
6148 | ||
35016322 JW |
6149 | /* Return 1 if REGNO (reg1) is even and REGNO (reg1) == REGNO (reg2) - 1. |
6150 | This makes them candidates for using ldd and std insns. | |
6151 | ||
bfd6bc60 | 6152 | Note reg1 and reg2 *must* be hard registers. */ |
35016322 JW |
6153 | |
6154 | int | |
7c56249d | 6155 | registers_ok_for_ldd_peep (reg1, reg2) |
35016322 JW |
6156 | rtx reg1, reg2; |
6157 | { | |
35016322 JW |
6158 | /* We might have been passed a SUBREG. */ |
6159 | if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG) | |
6160 | return 0; | |
6161 | ||
35016322 JW |
6162 | if (REGNO (reg1) % 2 != 0) |
6163 | return 0; | |
6164 | ||
bfd6bc60 JC |
6165 | /* Integer ldd is deprecated in SPARC V9 */ |
6166 | if (TARGET_V9 && REGNO (reg1) < 32) | |
6167 | return 0; | |
6168 | ||
35016322 | 6169 | return (REGNO (reg1) == REGNO (reg2) - 1); |
35016322 JW |
6170 | } |
6171 | ||
2aad5d68 | 6172 | /* Return 1 if the addresses in mem1 and mem2 are suitable for use in |
303f8933 DN |
6173 | an ldd or std insn. |
6174 | ||
2aad5d68 DN |
6175 | This can only happen when addr1 and addr2, the addresses in mem1 |
6176 | and mem2, are consecutive memory locations (addr1 + 4 == addr2). | |
303f8933 DN |
6177 | addr1 must also be aligned on a 64-bit boundary. |
6178 | ||
6179 | Also iff dependent_reg_rtx is not null it should not be used to | |
6180 | compute the address for mem1, i.e. we cannot optimize a sequence | |
6181 | like: | |
6182 | ld [%o0], %o0 | |
6183 | ld [%o0 + 4], %o1 | |
6184 | to | |
bcdd764b | 6185 | ldd [%o0], %o0 |
0acf409f DM |
6186 | nor: |
6187 | ld [%g3 + 4], %g3 | |
6188 | ld [%g3], %g2 | |
6189 | to | |
6190 | ldd [%g3], %g2 | |
6191 | ||
6192 | But, note that the transformation from: | |
6193 | ld [%g2 + 4], %g3 | |
6194 | ld [%g2], %g2 | |
6195 | to | |
6196 | ldd [%g2], %g2 | |
6197 | is perfectly fine. Thus, the peephole2 patterns always pass us | |
6198 | the destination register of the first load, never the second one. | |
6199 | ||
303f8933 DN |
6200 | For stores we don't have a similar problem, so dependent_reg_rtx is |
6201 | NULL_RTX. */ | |
35016322 JW |
6202 | |
6203 | int | |
303f8933 DN |
6204 | mems_ok_for_ldd_peep (mem1, mem2, dependent_reg_rtx) |
6205 | rtx mem1, mem2, dependent_reg_rtx; | |
35016322 | 6206 | { |
2aad5d68 | 6207 | rtx addr1, addr2; |
0d587737 KG |
6208 | unsigned int reg1; |
6209 | int offset1; | |
35016322 | 6210 | |
303f8933 DN |
6211 | /* The mems cannot be volatile. */ |
6212 | if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2)) | |
6213 | return 0; | |
2aad5d68 | 6214 | |
303f8933 | 6215 | /* MEM1 should be aligned on a 64-bit boundary. */ |
2aad5d68 DN |
6216 | if (MEM_ALIGN (mem1) < 64) |
6217 | return 0; | |
6218 | ||
303f8933 DN |
6219 | addr1 = XEXP (mem1, 0); |
6220 | addr2 = XEXP (mem2, 0); | |
6221 | ||
35016322 JW |
6222 | /* Extract a register number and offset (if used) from the first addr. */ |
6223 | if (GET_CODE (addr1) == PLUS) | |
6224 | { | |
6225 | /* If not a REG, return zero. */ | |
6226 | if (GET_CODE (XEXP (addr1, 0)) != REG) | |
6227 | return 0; | |
6228 | else | |
6229 | { | |
6230 | reg1 = REGNO (XEXP (addr1, 0)); | |
6231 | /* The offset must be constant! */ | |
6232 | if (GET_CODE (XEXP (addr1, 1)) != CONST_INT) | |
6233 | return 0; | |
6234 | offset1 = INTVAL (XEXP (addr1, 1)); | |
6235 | } | |
6236 | } | |
6237 | else if (GET_CODE (addr1) != REG) | |
6238 | return 0; | |
6239 | else | |
6240 | { | |
6241 | reg1 = REGNO (addr1); | |
6242 | /* This was a simple (mem (reg)) expression. Offset is 0. */ | |
6243 | offset1 = 0; | |
6244 | } | |
6245 | ||
6246 | /* Make sure the second address is a (mem (plus (reg) (const_int). */ | |
6247 | if (GET_CODE (addr2) != PLUS) | |
6248 | return 0; | |
6249 | ||
6250 | if (GET_CODE (XEXP (addr2, 0)) != REG | |
6251 | || GET_CODE (XEXP (addr2, 1)) != CONST_INT) | |
6252 | return 0; | |
6253 | ||
35016322 JW |
6254 | if (reg1 != REGNO (XEXP (addr2, 0))) |
6255 | return 0; | |
6256 | ||
303f8933 DN |
6257 | if (dependent_reg_rtx != NULL_RTX && reg1 == REGNO (dependent_reg_rtx)) |
6258 | return 0; | |
6259 | ||
2296cba3 | 6260 | /* The first offset must be evenly divisible by 8 to ensure the |
35016322 JW |
6261 | address is 64 bit aligned. */ |
6262 | if (offset1 % 8 != 0) | |
6263 | return 0; | |
6264 | ||
6265 | /* The offset for the second addr must be 4 more than the first addr. */ | |
6266 | if (INTVAL (XEXP (addr2, 1)) != offset1 + 4) | |
6267 | return 0; | |
6268 | ||
6269 | /* All the tests passed. addr1 and addr2 are valid for ldd and std | |
6270 | instructions. */ | |
6271 | return 1; | |
6272 | } | |
7c56249d JL |
6273 | |
6274 | /* Return 1 if reg is a pseudo, or is the first register in | |
6275 | a hard register pair. This makes it a candidate for use in | |
6276 | ldd and std insns. */ | |
6277 | ||
6278 | int | |
6279 | register_ok_for_ldd (reg) | |
6280 | rtx reg; | |
6281 | { | |
7c56249d JL |
6282 | /* We might have been passed a SUBREG. */ |
6283 | if (GET_CODE (reg) != REG) | |
6284 | return 0; | |
6285 | ||
6286 | if (REGNO (reg) < FIRST_PSEUDO_REGISTER) | |
6287 | return (REGNO (reg) % 2 == 0); | |
6288 | else | |
6289 | return 1; | |
7c56249d | 6290 | } |
ab835497 | 6291 | \f |
ab835497 RK |
6292 | /* Print operand X (an rtx) in assembler syntax to file FILE. |
6293 | CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. | |
6294 | For `%' followed by punctuation, CODE is the punctuation and X is null. */ | |
6295 | ||
6296 | void | |
6297 | print_operand (file, x, code) | |
6298 | FILE *file; | |
6299 | rtx x; | |
6300 | int code; | |
6301 | { | |
6302 | switch (code) | |
6303 | { | |
6304 | case '#': | |
6305 | /* Output a 'nop' if there's nothing for the delay slot. */ | |
6306 | if (dbr_sequence_length () == 0) | |
e0d80184 | 6307 | fputs ("\n\t nop", file); |
ab835497 RK |
6308 | return; |
6309 | case '*': | |
c6ce0969 JW |
6310 | /* Output an annul flag if there's nothing for the delay slot and we |
6311 | are optimizing. This is always used with '(' below. */ | |
6312 | /* Sun OS 4.1.1 dbx can't handle an annulled unconditional branch; | |
6313 | this is a dbx bug. So, we only do this when optimizing. */ | |
bfd6bc60 JC |
6314 | /* On UltraSPARC, a branch in a delay slot causes a pipeline flush. |
6315 | Always emit a nop in case the next instruction is a branch. */ | |
6316 | if (dbr_sequence_length () == 0 | |
284d86e9 | 6317 | && (optimize && (int)sparc_cpu < PROCESSOR_V9)) |
c6ce0969 JW |
6318 | fputs (",a", file); |
6319 | return; | |
6320 | case '(': | |
6321 | /* Output a 'nop' if there's nothing for the delay slot and we are | |
6322 | not optimizing. This is always used with '*' above. */ | |
bfd6bc60 | 6323 | if (dbr_sequence_length () == 0 |
284d86e9 | 6324 | && ! (optimize && (int)sparc_cpu < PROCESSOR_V9)) |
e0d80184 | 6325 | fputs ("\n\t nop", file); |
ab835497 | 6326 | return; |
61a55e8b | 6327 | case '_': |
a0a301fc DE |
6328 | /* Output the Embedded Medium/Anywhere code model base register. */ |
6329 | fputs (EMBMEDANY_BASE_REG, file); | |
61a55e8b DE |
6330 | return; |
6331 | case '@': | |
6332 | /* Print out what we are using as the frame pointer. This might | |
6333 | be %fp, or might be %sp+offset. */ | |
6334 | /* ??? What if offset is too big? Perhaps the caller knows it isn't? */ | |
6335 | fprintf (file, "%s+%d", frame_base_name, frame_base_offset); | |
6336 | return; | |
ab835497 RK |
6337 | case 'Y': |
6338 | /* Adjust the operand to take into account a RESTORE operation. */ | |
bfd6bc60 JC |
6339 | if (GET_CODE (x) == CONST_INT) |
6340 | break; | |
6341 | else if (GET_CODE (x) != REG) | |
c725bd79 | 6342 | output_operand_lossage ("invalid %%Y operand"); |
b3b1e8bd | 6343 | else if (REGNO (x) < 8) |
ab835497 RK |
6344 | fputs (reg_names[REGNO (x)], file); |
6345 | else if (REGNO (x) >= 24 && REGNO (x) < 32) | |
6346 | fputs (reg_names[REGNO (x)-16], file); | |
6347 | else | |
c725bd79 | 6348 | output_operand_lossage ("invalid %%Y operand"); |
ab835497 | 6349 | return; |
0f39a9aa DE |
6350 | case 'L': |
6351 | /* Print out the low order register name of a register pair. */ | |
6352 | if (WORDS_BIG_ENDIAN) | |
6353 | fputs (reg_names[REGNO (x)+1], file); | |
6354 | else | |
6355 | fputs (reg_names[REGNO (x)], file); | |
6356 | return; | |
6357 | case 'H': | |
6358 | /* Print out the high order register name of a register pair. */ | |
6359 | if (WORDS_BIG_ENDIAN) | |
6360 | fputs (reg_names[REGNO (x)], file); | |
6361 | else | |
6362 | fputs (reg_names[REGNO (x)+1], file); | |
6363 | return; | |
ab835497 | 6364 | case 'R': |
795068a4 | 6365 | /* Print out the second register name of a register pair or quad. |
ab835497 RK |
6366 | I.e., R (%o0) => %o1. */ |
6367 | fputs (reg_names[REGNO (x)+1], file); | |
6368 | return; | |
795068a4 JW |
6369 | case 'S': |
6370 | /* Print out the third register name of a register quad. | |
6371 | I.e., S (%o0) => %o2. */ | |
6372 | fputs (reg_names[REGNO (x)+2], file); | |
6373 | return; | |
6374 | case 'T': | |
6375 | /* Print out the fourth register name of a register quad. | |
6376 | I.e., T (%o0) => %o3. */ | |
6377 | fputs (reg_names[REGNO (x)+3], file); | |
6378 | return; | |
304b7a23 DE |
6379 | case 'x': |
6380 | /* Print a condition code register. */ | |
6381 | if (REGNO (x) == SPARC_ICC_REG) | |
6382 | { | |
6383 | /* We don't handle CC[X]_NOOVmode because they're not supposed | |
6384 | to occur here. */ | |
6385 | if (GET_MODE (x) == CCmode) | |
6386 | fputs ("%icc", file); | |
6387 | else if (GET_MODE (x) == CCXmode) | |
6388 | fputs ("%xcc", file); | |
6389 | else | |
6390 | abort (); | |
6391 | } | |
6392 | else | |
6393 | /* %fccN register */ | |
6394 | fputs (reg_names[REGNO (x)], file); | |
6395 | return; | |
ab835497 RK |
6396 | case 'm': |
6397 | /* Print the operand's address only. */ | |
6398 | output_address (XEXP (x, 0)); | |
6399 | return; | |
6400 | case 'r': | |
6401 | /* In this case we need a register. Use %g0 if the | |
77a02b01 | 6402 | operand is const0_rtx. */ |
76052e74 RS |
6403 | if (x == const0_rtx |
6404 | || (GET_MODE (x) != VOIDmode && x == CONST0_RTX (GET_MODE (x)))) | |
ab835497 RK |
6405 | { |
6406 | fputs ("%g0", file); | |
6407 | return; | |
6408 | } | |
6409 | else | |
6410 | break; | |
6411 | ||
61a55e8b | 6412 | case 'A': |
ab835497 RK |
6413 | switch (GET_CODE (x)) |
6414 | { | |
6415 | case IOR: fputs ("or", file); break; | |
6416 | case AND: fputs ("and", file); break; | |
6417 | case XOR: fputs ("xor", file); break; | |
c725bd79 | 6418 | default: output_operand_lossage ("invalid %%A operand"); |
ab835497 RK |
6419 | } |
6420 | return; | |
6421 | ||
6422 | case 'B': | |
6423 | switch (GET_CODE (x)) | |
6424 | { | |
6425 | case IOR: fputs ("orn", file); break; | |
6426 | case AND: fputs ("andn", file); break; | |
6427 | case XOR: fputs ("xnor", file); break; | |
c725bd79 | 6428 | default: output_operand_lossage ("invalid %%B operand"); |
ab835497 RK |
6429 | } |
6430 | return; | |
6431 | ||
304b7a23 DE |
6432 | /* These are used by the conditional move instructions. */ |
6433 | case 'c' : | |
61a55e8b | 6434 | case 'C': |
304b7a23 | 6435 | { |
5c5c34a4 JJ |
6436 | enum rtx_code rc = GET_CODE (x); |
6437 | ||
6438 | if (code == 'c') | |
6439 | { | |
6440 | enum machine_mode mode = GET_MODE (XEXP (x, 0)); | |
6441 | if (mode == CCFPmode || mode == CCFPEmode) | |
6442 | rc = reverse_condition_maybe_unordered (GET_CODE (x)); | |
6443 | else | |
6444 | rc = reverse_condition (GET_CODE (x)); | |
6445 | } | |
304b7a23 DE |
6446 | switch (rc) |
6447 | { | |
6448 | case NE: fputs ("ne", file); break; | |
6449 | case EQ: fputs ("e", file); break; | |
6450 | case GE: fputs ("ge", file); break; | |
6451 | case GT: fputs ("g", file); break; | |
6452 | case LE: fputs ("le", file); break; | |
6453 | case LT: fputs ("l", file); break; | |
6454 | case GEU: fputs ("geu", file); break; | |
6455 | case GTU: fputs ("gu", file); break; | |
6456 | case LEU: fputs ("leu", file); break; | |
6457 | case LTU: fputs ("lu", file); break; | |
5c5c34a4 JJ |
6458 | case LTGT: fputs ("lg", file); break; |
6459 | case UNORDERED: fputs ("u", file); break; | |
6460 | case ORDERED: fputs ("o", file); break; | |
6461 | case UNLT: fputs ("ul", file); break; | |
6462 | case UNLE: fputs ("ule", file); break; | |
6463 | case UNGT: fputs ("ug", file); break; | |
6464 | case UNGE: fputs ("uge", file); break; | |
6465 | case UNEQ: fputs ("ue", file); break; | |
304b7a23 | 6466 | default: output_operand_lossage (code == 'c' |
c725bd79 NB |
6467 | ? "invalid %%c operand" |
6468 | : "invalid %%C operand"); | |
304b7a23 DE |
6469 | } |
6470 | return; | |
6471 | } | |
6472 | ||
6473 | /* These are used by the movr instruction pattern. */ | |
6474 | case 'd': | |
61a55e8b | 6475 | case 'D': |
304b7a23 DE |
6476 | { |
6477 | enum rtx_code rc = (code == 'd' | |
6478 | ? reverse_condition (GET_CODE (x)) | |
6479 | : GET_CODE (x)); | |
6480 | switch (rc) | |
6481 | { | |
6482 | case NE: fputs ("ne", file); break; | |
6483 | case EQ: fputs ("e", file); break; | |
6484 | case GE: fputs ("gez", file); break; | |
6485 | case LT: fputs ("lz", file); break; | |
6486 | case LE: fputs ("lez", file); break; | |
6487 | case GT: fputs ("gz", file); break; | |
6488 | default: output_operand_lossage (code == 'd' | |
c725bd79 NB |
6489 | ? "invalid %%d operand" |
6490 | : "invalid %%D operand"); | |
304b7a23 DE |
6491 | } |
6492 | return; | |
6493 | } | |
61a55e8b | 6494 | |
ab835497 RK |
6495 | case 'b': |
6496 | { | |
6497 | /* Print a sign-extended character. */ | |
9e0625a3 | 6498 | int i = trunc_int_for_mode (INTVAL (x), QImode); |
ab835497 RK |
6499 | fprintf (file, "%d", i); |
6500 | return; | |
6501 | } | |
6502 | ||
d2889939 RK |
6503 | case 'f': |
6504 | /* Operand must be a MEM; write its address. */ | |
6505 | if (GET_CODE (x) != MEM) | |
c725bd79 | 6506 | output_operand_lossage ("invalid %%f operand"); |
d2889939 RK |
6507 | output_address (XEXP (x, 0)); |
6508 | return; | |
6509 | ||
8707fe93 RH |
6510 | case 's': |
6511 | { | |
6512 | /* Print a sign-extended 32-bit value. */ | |
6513 | HOST_WIDE_INT i; | |
6514 | if (GET_CODE(x) == CONST_INT) | |
6515 | i = INTVAL (x); | |
6516 | else if (GET_CODE(x) == CONST_DOUBLE) | |
6517 | i = CONST_DOUBLE_LOW (x); | |
6518 | else | |
ffa916ba KG |
6519 | { |
6520 | output_operand_lossage ("invalid %%s operand"); | |
6521 | return; | |
6522 | } | |
8707fe93 RH |
6523 | i = trunc_int_for_mode (i, SImode); |
6524 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, i); | |
6525 | return; | |
6526 | } | |
6527 | ||
ab835497 RK |
6528 | case 0: |
6529 | /* Do nothing special. */ | |
6530 | break; | |
6531 | ||
6532 | default: | |
6533 | /* Undocumented flag. */ | |
415f583e | 6534 | output_operand_lossage ("invalid operand output code"); |
ab835497 RK |
6535 | } |
6536 | ||
6537 | if (GET_CODE (x) == REG) | |
6538 | fputs (reg_names[REGNO (x)], file); | |
6539 | else if (GET_CODE (x) == MEM) | |
6540 | { | |
6541 | fputc ('[', file); | |
ab835497 | 6542 | /* Poor Sun assembler doesn't understand absolute addressing. */ |
e6c1be7e | 6543 | if (CONSTANT_P (XEXP (x, 0))) |
ab835497 RK |
6544 | fputs ("%g0+", file); |
6545 | output_address (XEXP (x, 0)); | |
6546 | fputc (']', file); | |
6547 | } | |
6548 | else if (GET_CODE (x) == HIGH) | |
6549 | { | |
6550 | fputs ("%hi(", file); | |
6551 | output_addr_const (file, XEXP (x, 0)); | |
6552 | fputc (')', file); | |
6553 | } | |
6554 | else if (GET_CODE (x) == LO_SUM) | |
6555 | { | |
6556 | print_operand (file, XEXP (x, 0), 0); | |
e0d80184 DM |
6557 | if (TARGET_CM_MEDMID) |
6558 | fputs ("+%l44(", file); | |
6559 | else | |
6560 | fputs ("+%lo(", file); | |
ab835497 RK |
6561 | output_addr_const (file, XEXP (x, 1)); |
6562 | fputc (')', file); | |
6563 | } | |
e601abce JW |
6564 | else if (GET_CODE (x) == CONST_DOUBLE |
6565 | && (GET_MODE (x) == VOIDmode | |
6566 | || GET_MODE_CLASS (GET_MODE (x)) == MODE_INT)) | |
ab835497 RK |
6567 | { |
6568 | if (CONST_DOUBLE_HIGH (x) == 0) | |
0d9484c5 | 6569 | fprintf (file, "%u", (unsigned int) CONST_DOUBLE_LOW (x)); |
ab835497 RK |
6570 | else if (CONST_DOUBLE_HIGH (x) == -1 |
6571 | && CONST_DOUBLE_LOW (x) < 0) | |
0d9484c5 | 6572 | fprintf (file, "%d", (int) CONST_DOUBLE_LOW (x)); |
ab835497 | 6573 | else |
e601abce | 6574 | output_operand_lossage ("long long constant not a valid immediate operand"); |
ab835497 | 6575 | } |
e601abce JW |
6576 | else if (GET_CODE (x) == CONST_DOUBLE) |
6577 | output_operand_lossage ("floating point constant not a valid immediate operand"); | |
ab835497 RK |
6578 | else { output_addr_const (file, x); } |
6579 | } | |
6580 | \f | |
301d03af RS |
6581 | /* Target hook for assembling integer objects. The sparc version has |
6582 | special handling for aligned DI-mode objects. */ | |
ab835497 | 6583 | |
301d03af RS |
6584 | static bool |
6585 | sparc_assemble_integer (x, size, aligned_p) | |
6586 | rtx x; | |
6587 | unsigned int size; | |
6588 | int aligned_p; | |
ab835497 | 6589 | { |
301d03af RS |
6590 | /* ??? We only output .xword's for symbols and only then in environments |
6591 | where the assembler can handle them. */ | |
6592 | if (aligned_p && size == 8 | |
6593 | && (GET_CODE (x) != CONST_INT && GET_CODE (x) != CONST_DOUBLE)) | |
ab835497 | 6594 | { |
301d03af | 6595 | if (TARGET_V9) |
61a55e8b | 6596 | { |
301d03af RS |
6597 | assemble_integer_with_op ("\t.xword\t", x); |
6598 | return true; | |
61a55e8b DE |
6599 | } |
6600 | else | |
6601 | { | |
301d03af RS |
6602 | assemble_aligned_integer (4, const0_rtx); |
6603 | assemble_aligned_integer (4, x); | |
6604 | return true; | |
61a55e8b | 6605 | } |
ab835497 | 6606 | } |
301d03af | 6607 | return default_assemble_integer (x, size, aligned_p); |
ab835497 | 6608 | } |
210aa14a | 6609 | \f |
b0468b84 RK |
6610 | /* Return the value of a code used in the .proc pseudo-op that says |
6611 | what kind of result this function returns. For non-C types, we pick | |
6612 | the closest C type. */ | |
6613 | ||
77a02b01 JW |
6614 | #ifndef SHORT_TYPE_SIZE |
6615 | #define SHORT_TYPE_SIZE (BITS_PER_UNIT * 2) | |
6616 | #endif | |
6617 | ||
6618 | #ifndef INT_TYPE_SIZE | |
6619 | #define INT_TYPE_SIZE BITS_PER_WORD | |
6620 | #endif | |
6621 | ||
6622 | #ifndef LONG_TYPE_SIZE | |
6623 | #define LONG_TYPE_SIZE BITS_PER_WORD | |
6624 | #endif | |
6625 | ||
6626 | #ifndef LONG_LONG_TYPE_SIZE | |
6627 | #define LONG_LONG_TYPE_SIZE (BITS_PER_WORD * 2) | |
6628 | #endif | |
6629 | ||
6630 | #ifndef FLOAT_TYPE_SIZE | |
6631 | #define FLOAT_TYPE_SIZE BITS_PER_WORD | |
6632 | #endif | |
6633 | ||
6634 | #ifndef DOUBLE_TYPE_SIZE | |
6635 | #define DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2) | |
6636 | #endif | |
6637 | ||
6638 | #ifndef LONG_DOUBLE_TYPE_SIZE | |
6639 | #define LONG_DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2) | |
6640 | #endif | |
210aa14a RS |
6641 | |
6642 | unsigned long | |
6643 | sparc_type_code (type) | |
6644 | register tree type; | |
6645 | { | |
6646 | register unsigned long qualifiers = 0; | |
e5e809f4 | 6647 | register unsigned shift; |
210aa14a | 6648 | |
abc95ed3 | 6649 | /* Only the first 30 bits of the qualifier are valid. We must refrain from |
aee2c3c5 JW |
6650 | setting more, since some assemblers will give an error for this. Also, |
6651 | we must be careful to avoid shifts of 32 bits or more to avoid getting | |
6652 | unpredictable results. */ | |
6653 | ||
e5e809f4 | 6654 | for (shift = 6; shift < 30; shift += 2, type = TREE_TYPE (type)) |
210aa14a RS |
6655 | { |
6656 | switch (TREE_CODE (type)) | |
6657 | { | |
6658 | case ERROR_MARK: | |
6659 | return qualifiers; | |
6660 | ||
6661 | case ARRAY_TYPE: | |
e5e809f4 | 6662 | qualifiers |= (3 << shift); |
210aa14a RS |
6663 | break; |
6664 | ||
6665 | case FUNCTION_TYPE: | |
6666 | case METHOD_TYPE: | |
e5e809f4 | 6667 | qualifiers |= (2 << shift); |
210aa14a RS |
6668 | break; |
6669 | ||
6670 | case POINTER_TYPE: | |
6671 | case REFERENCE_TYPE: | |
6672 | case OFFSET_TYPE: | |
e5e809f4 | 6673 | qualifiers |= (1 << shift); |
210aa14a | 6674 | break; |
ab835497 | 6675 | |
210aa14a RS |
6676 | case RECORD_TYPE: |
6677 | return (qualifiers | 8); | |
6678 | ||
6679 | case UNION_TYPE: | |
b0468b84 | 6680 | case QUAL_UNION_TYPE: |
210aa14a RS |
6681 | return (qualifiers | 9); |
6682 | ||
6683 | case ENUMERAL_TYPE: | |
6684 | return (qualifiers | 10); | |
6685 | ||
6686 | case VOID_TYPE: | |
6687 | return (qualifiers | 16); | |
6688 | ||
6689 | case INTEGER_TYPE: | |
654209e6 JW |
6690 | /* If this is a range type, consider it to be the underlying |
6691 | type. */ | |
6692 | if (TREE_TYPE (type) != 0) | |
e5e809f4 | 6693 | break; |
654209e6 | 6694 | |
77a02b01 | 6695 | /* Carefully distinguish all the standard types of C, |
b0468b84 RK |
6696 | without messing up if the language is not C. We do this by |
6697 | testing TYPE_PRECISION and TREE_UNSIGNED. The old code used to | |
6698 | look at both the names and the above fields, but that's redundant. | |
6699 | Any type whose size is between two C types will be considered | |
6700 | to be the wider of the two types. Also, we do not have a | |
6701 | special code to use for "long long", so anything wider than | |
6702 | long is treated the same. Note that we can't distinguish | |
6703 | between "int" and "long" in this code if they are the same | |
6704 | size, but that's fine, since neither can the assembler. */ | |
6705 | ||
6706 | if (TYPE_PRECISION (type) <= CHAR_TYPE_SIZE) | |
6707 | return (qualifiers | (TREE_UNSIGNED (type) ? 12 : 2)); | |
77a02b01 | 6708 | |
b0468b84 RK |
6709 | else if (TYPE_PRECISION (type) <= SHORT_TYPE_SIZE) |
6710 | return (qualifiers | (TREE_UNSIGNED (type) ? 13 : 3)); | |
77a02b01 | 6711 | |
b0468b84 | 6712 | else if (TYPE_PRECISION (type) <= INT_TYPE_SIZE) |
77a02b01 JW |
6713 | return (qualifiers | (TREE_UNSIGNED (type) ? 14 : 4)); |
6714 | ||
b0468b84 | 6715 | else |
77a02b01 JW |
6716 | return (qualifiers | (TREE_UNSIGNED (type) ? 15 : 5)); |
6717 | ||
210aa14a | 6718 | case REAL_TYPE: |
e5e809f4 JL |
6719 | /* If this is a range type, consider it to be the underlying |
6720 | type. */ | |
6721 | if (TREE_TYPE (type) != 0) | |
6722 | break; | |
6723 | ||
77a02b01 JW |
6724 | /* Carefully distinguish all the standard types of C, |
6725 | without messing up if the language is not C. */ | |
b0468b84 | 6726 | |
77a02b01 | 6727 | if (TYPE_PRECISION (type) == FLOAT_TYPE_SIZE) |
210aa14a | 6728 | return (qualifiers | 6); |
b0468b84 RK |
6729 | |
6730 | else | |
6731 | return (qualifiers | 7); | |
210aa14a RS |
6732 | |
6733 | case COMPLEX_TYPE: /* GNU Fortran COMPLEX type. */ | |
13d39dbc | 6734 | /* ??? We need to distinguish between double and float complex types, |
c82aa69a JW |
6735 | but I don't know how yet because I can't reach this code from |
6736 | existing front-ends. */ | |
6737 | return (qualifiers | 7); /* Who knows? */ | |
6738 | ||
210aa14a RS |
6739 | case CHAR_TYPE: /* GNU Pascal CHAR type. Not used in C. */ |
6740 | case BOOLEAN_TYPE: /* GNU Fortran BOOLEAN type. */ | |
6741 | case FILE_TYPE: /* GNU Pascal FILE type. */ | |
26902ae0 | 6742 | case SET_TYPE: /* GNU Pascal SET type. */ |
210aa14a | 6743 | case LANG_TYPE: /* ? */ |
26902ae0 | 6744 | return qualifiers; |
210aa14a RS |
6745 | |
6746 | default: | |
6747 | abort (); /* Not a type! */ | |
6748 | } | |
6749 | } | |
e5e809f4 JL |
6750 | |
6751 | return qualifiers; | |
210aa14a | 6752 | } |
ead69aea | 6753 | \f |
61a55e8b DE |
6754 | /* Nested function support. */ |
6755 | ||
6756 | /* Emit RTL insns to initialize the variable parts of a trampoline. | |
6757 | FNADDR is an RTX for the address of the function's pure code. | |
6758 | CXT is an RTX for the static chain value for the function. | |
6759 | ||
6760 | This takes 16 insns: 2 shifts & 2 ands (to split up addresses), 4 sethi | |
6761 | (to load in opcodes), 4 iors (to merge address and opcodes), and 4 writes | |
6762 | (to store insns). This is a bit excessive. Perhaps a different | |
6763 | mechanism would be better here. | |
6764 | ||
849a528d | 6765 | Emit enough FLUSH insns to synchronize the data and instruction caches. */ |
61a55e8b DE |
6766 | |
6767 | void | |
6768 | sparc_initialize_trampoline (tramp, fnaddr, cxt) | |
6769 | rtx tramp, fnaddr, cxt; | |
6770 | { | |
c6b0465b JC |
6771 | /* SPARC 32 bit trampoline: |
6772 | ||
e0d80184 DM |
6773 | sethi %hi(fn), %g1 |
6774 | sethi %hi(static), %g2 | |
6775 | jmp %g1+%lo(fn) | |
6776 | or %g2, %lo(static), %g2 | |
c6b0465b JC |
6777 | |
6778 | SETHI i,r = 00rr rrr1 00ii iiii iiii iiii iiii iiii | |
6779 | JMPL r+i,d = 10dd ddd1 1100 0rrr rr1i iiii iiii iiii | |
6780 | */ | |
959eb758 DM |
6781 | #ifdef TRANSFER_FROM_TRAMPOLINE |
6782 | emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "__enable_execute_stack"), | |
eb29ddb6 | 6783 | LCT_NORMAL, VOIDmode, 1, tramp, Pmode); |
959eb758 | 6784 | #endif |
c6b0465b | 6785 | |
35aa3c1c RK |
6786 | emit_move_insn |
6787 | (gen_rtx_MEM (SImode, plus_constant (tramp, 0)), | |
6788 | expand_binop (SImode, ior_optab, | |
6789 | expand_shift (RSHIFT_EXPR, SImode, fnaddr, | |
6790 | size_int (10), 0, 1), | |
6791 | GEN_INT (trunc_int_for_mode (0x03000000, SImode)), | |
6792 | NULL_RTX, 1, OPTAB_DIRECT)); | |
6793 | ||
6794 | emit_move_insn | |
6795 | (gen_rtx_MEM (SImode, plus_constant (tramp, 4)), | |
6796 | expand_binop (SImode, ior_optab, | |
6797 | expand_shift (RSHIFT_EXPR, SImode, cxt, | |
6798 | size_int (10), 0, 1), | |
6799 | GEN_INT (trunc_int_for_mode (0x05000000, SImode)), | |
6800 | NULL_RTX, 1, OPTAB_DIRECT)); | |
6801 | ||
6802 | emit_move_insn | |
6803 | (gen_rtx_MEM (SImode, plus_constant (tramp, 8)), | |
6804 | expand_binop (SImode, ior_optab, | |
6805 | expand_and (SImode, fnaddr, GEN_INT (0x3ff), NULL_RTX), | |
6806 | GEN_INT (trunc_int_for_mode (0x81c06000, SImode)), | |
6807 | NULL_RTX, 1, OPTAB_DIRECT)); | |
6808 | ||
6809 | emit_move_insn | |
6810 | (gen_rtx_MEM (SImode, plus_constant (tramp, 12)), | |
6811 | expand_binop (SImode, ior_optab, | |
6812 | expand_and (SImode, cxt, GEN_INT (0x3ff), NULL_RTX), | |
6813 | GEN_INT (trunc_int_for_mode (0x8410a000, SImode)), | |
6814 | NULL_RTX, 1, OPTAB_DIRECT)); | |
c6b0465b | 6815 | |
c6b0465b JC |
6816 | /* On UltraSPARC a flush flushes an entire cache line. The trampoline is |
6817 | aligned on a 16 byte boundary so one flush clears it all. */ | |
35aa3c1c | 6818 | emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode, tramp)))); |
84643cbf DM |
6819 | if (sparc_cpu != PROCESSOR_ULTRASPARC |
6820 | && sparc_cpu != PROCESSOR_ULTRASPARC3) | |
c6b0465b JC |
6821 | emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode, |
6822 | plus_constant (tramp, 8))))); | |
61a55e8b DE |
6823 | } |
6824 | ||
849a528d RK |
6825 | /* The 64 bit version is simpler because it makes more sense to load the |
6826 | values as "immediate" data out of the trampoline. It's also easier since | |
6827 | we can read the PC without clobbering a register. */ | |
6828 | ||
61a55e8b DE |
6829 | void |
6830 | sparc64_initialize_trampoline (tramp, fnaddr, cxt) | |
6831 | rtx tramp, fnaddr, cxt; | |
6832 | { | |
345a6161 DM |
6833 | #ifdef TRANSFER_FROM_TRAMPOLINE |
6834 | emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "__enable_execute_stack"), | |
eb29ddb6 | 6835 | LCT_NORMAL, VOIDmode, 1, tramp, Pmode); |
345a6161 DM |
6836 | #endif |
6837 | ||
c6b0465b | 6838 | /* |
e0d80184 DM |
6839 | rd %pc, %g1 |
6840 | ldx [%g1+24], %g5 | |
6841 | jmp %g5 | |
6842 | ldx [%g1+16], %g5 | |
c6b0465b JC |
6843 | +16 bytes data |
6844 | */ | |
6845 | ||
6846 | emit_move_insn (gen_rtx_MEM (SImode, tramp), | |
e3aaacf4 | 6847 | GEN_INT (trunc_int_for_mode (0x83414000, SImode))); |
c6b0465b | 6848 | emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 4)), |
e3aaacf4 | 6849 | GEN_INT (trunc_int_for_mode (0xca586018, SImode))); |
c6b0465b | 6850 | emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 8)), |
e3aaacf4 | 6851 | GEN_INT (trunc_int_for_mode (0x81c14000, SImode))); |
c6b0465b | 6852 | emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 12)), |
e3aaacf4 | 6853 | GEN_INT (trunc_int_for_mode (0xca586010, SImode))); |
c6b0465b | 6854 | emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 16)), cxt); |
345a6161 | 6855 | emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 24)), fnaddr); |
d4203cb4 | 6856 | emit_insn (gen_flushdi (validize_mem (gen_rtx_MEM (DImode, tramp)))); |
345a6161 | 6857 | |
fae15c93 VM |
6858 | if (sparc_cpu != PROCESSOR_ULTRASPARC |
6859 | && sparc_cpu != PROCESSOR_ULTRASPARC3) | |
d4203cb4 | 6860 | emit_insn (gen_flushdi (validize_mem (gen_rtx_MEM (DImode, plus_constant (tramp, 8))))); |
61a55e8b DE |
6861 | } |
6862 | \f | |
c819be5b JW |
6863 | /* Subroutines to support a flat (single) register window calling |
6864 | convention. */ | |
6865 | ||
6866 | /* Single-register window sparc stack frames look like: | |
6867 | ||
6868 | Before call After call | |
6869 | +-----------------------+ +-----------------------+ | |
86735b02 DE |
6870 | high | | | | |
6871 | mem | caller's temps. | | caller's temps. | | |
c819be5b JW |
6872 | | | | | |
6873 | +-----------------------+ +-----------------------+ | |
6874 | | | | | | |
6875 | | arguments on stack. | | arguments on stack. | | |
86735b02 DE |
6876 | | | | | |
6877 | +-----------------------+FP+92->+-----------------------+ | |
c819be5b JW |
6878 | | 6 words to save | | 6 words to save | |
6879 | | arguments passed | | arguments passed | | |
6880 | | in registers, even | | in registers, even | | |
86735b02 DE |
6881 | | if not passed. | | if not passed. | |
6882 | SP+68->+-----------------------+FP+68->+-----------------------+ | |
6883 | | 1 word struct addr | | 1 word struct addr | | |
6884 | +-----------------------+FP+64->+-----------------------+ | |
6885 | | | | | | |
6886 | | 16 word reg save area | | 16 word reg save area | | |
6887 | | | | | | |
6888 | SP->+-----------------------+ FP->+-----------------------+ | |
6889 | | 4 word area for | | |
6890 | | fp/alu reg moves | | |
6891 | FP-16->+-----------------------+ | |
6892 | | | | |
6893 | | local variables | | |
6894 | | | | |
6895 | +-----------------------+ | |
6896 | | | | |
c819be5b | 6897 | | fp register save | |
86735b02 DE |
6898 | | | |
6899 | +-----------------------+ | |
6900 | | | | |
c819be5b JW |
6901 | | gp register save | |
6902 | | | | |
86735b02 DE |
6903 | +-----------------------+ |
6904 | | | | |
c819be5b | 6905 | | alloca allocations | |
86735b02 DE |
6906 | | | |
6907 | +-----------------------+ | |
6908 | | | | |
c819be5b | 6909 | | arguments on stack | |
86735b02 DE |
6910 | | | |
6911 | SP+92->+-----------------------+ | |
c819be5b | 6912 | | 6 words to save | |
86735b02 | 6913 | | arguments passed | |
c819be5b | 6914 | | in registers, even | |
86735b02 DE |
6915 | low | if not passed. | |
6916 | memory SP+68->+-----------------------+ | |
6917 | | 1 word struct addr | | |
6918 | SP+64->+-----------------------+ | |
6919 | | | | |
6920 | I 16 word reg save area | | |
6921 | | | | |
6922 | SP->+-----------------------+ */ | |
c819be5b | 6923 | |
c6aa9ce1 | 6924 | /* Structure to be filled in by sparc_flat_compute_frame_size with register |
c819be5b JW |
6925 | save masks, and offsets for the current function. */ |
6926 | ||
6927 | struct sparc_frame_info | |
6928 | { | |
6929 | unsigned long total_size; /* # bytes that the entire frame takes up. */ | |
6930 | unsigned long var_size; /* # bytes that variables take up. */ | |
6931 | unsigned long args_size; /* # bytes that outgoing arguments take up. */ | |
6932 | unsigned long extra_size; /* # bytes of extra gunk. */ | |
6933 | unsigned int gp_reg_size; /* # bytes needed to store gp regs. */ | |
6934 | unsigned int fp_reg_size; /* # bytes needed to store fp regs. */ | |
86735b02 | 6935 | unsigned long gmask; /* Mask of saved gp registers. */ |
c819be5b | 6936 | unsigned long fmask; /* Mask of saved fp registers. */ |
86735b02 | 6937 | unsigned long reg_offset; /* Offset from new sp to store regs. */ |
c819be5b JW |
6938 | int initialized; /* Nonzero if frame size already calculated. */ |
6939 | }; | |
6940 | ||
c6aa9ce1 | 6941 | /* Current frame information calculated by sparc_flat_compute_frame_size. */ |
c819be5b JW |
6942 | struct sparc_frame_info current_frame_info; |
6943 | ||
6944 | /* Zero structure to initialize current_frame_info. */ | |
6945 | struct sparc_frame_info zero_frame_info; | |
6946 | ||
6947 | /* Tell prologue and epilogue if register REGNO should be saved / restored. */ | |
6948 | ||
86735b02 | 6949 | #define RETURN_ADDR_REGNUM 15 |
563c12b0 | 6950 | #define HARD_FRAME_POINTER_MASK (1 << (HARD_FRAME_POINTER_REGNUM)) |
86735b02 DE |
6951 | #define RETURN_ADDR_MASK (1 << (RETURN_ADDR_REGNUM)) |
6952 | ||
c819be5b | 6953 | #define MUST_SAVE_REGISTER(regno) \ |
563c12b0 RH |
6954 | ((regs_ever_live[regno] && !call_used_regs[regno]) \ |
6955 | || (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed) \ | |
86735b02 | 6956 | || (regno == RETURN_ADDR_REGNUM && regs_ever_live[RETURN_ADDR_REGNUM])) |
c819be5b JW |
6957 | |
6958 | /* Return the bytes needed to compute the frame pointer from the current | |
6959 | stack pointer. */ | |
6960 | ||
6961 | unsigned long | |
c6aa9ce1 | 6962 | sparc_flat_compute_frame_size (size) |
c819be5b JW |
6963 | int size; /* # of var. bytes allocated. */ |
6964 | { | |
6965 | int regno; | |
6966 | unsigned long total_size; /* # bytes that the entire frame takes up. */ | |
6967 | unsigned long var_size; /* # bytes that variables take up. */ | |
6968 | unsigned long args_size; /* # bytes that outgoing arguments take up. */ | |
6969 | unsigned long extra_size; /* # extra bytes. */ | |
6970 | unsigned int gp_reg_size; /* # bytes needed to store gp regs. */ | |
6971 | unsigned int fp_reg_size; /* # bytes needed to store fp regs. */ | |
86735b02 | 6972 | unsigned long gmask; /* Mask of saved gp registers. */ |
c819be5b | 6973 | unsigned long fmask; /* Mask of saved fp registers. */ |
86735b02 DE |
6974 | unsigned long reg_offset; /* Offset to register save area. */ |
6975 | int need_aligned_p; /* 1 if need the save area 8 byte aligned. */ | |
c819be5b JW |
6976 | |
6977 | /* This is the size of the 16 word reg save area, 1 word struct addr | |
6978 | area, and 4 word fp/alu register copy area. */ | |
8c64be75 SC |
6979 | extra_size = -STARTING_FRAME_OFFSET + FIRST_PARM_OFFSET(0); |
6980 | var_size = size; | |
6981 | gp_reg_size = 0; | |
6982 | fp_reg_size = 0; | |
6983 | gmask = 0; | |
6984 | fmask = 0; | |
6985 | reg_offset = 0; | |
86735b02 | 6986 | need_aligned_p = 0; |
c819be5b | 6987 | |
8c64be75 SC |
6988 | args_size = 0; |
6989 | if (!leaf_function_p ()) | |
6990 | { | |
6991 | /* Also include the size needed for the 6 parameter registers. */ | |
6992 | args_size = current_function_outgoing_args_size + 24; | |
6993 | } | |
6994 | total_size = var_size + args_size; | |
6995 | ||
c819be5b JW |
6996 | /* Calculate space needed for gp registers. */ |
6997 | for (regno = 1; regno <= 31; regno++) | |
6998 | { | |
6999 | if (MUST_SAVE_REGISTER (regno)) | |
7000 | { | |
86735b02 DE |
7001 | /* If we need to save two regs in a row, ensure there's room to bump |
7002 | up the address to align it to a doubleword boundary. */ | |
c819be5b JW |
7003 | if ((regno & 0x1) == 0 && MUST_SAVE_REGISTER (regno+1)) |
7004 | { | |
7005 | if (gp_reg_size % 8 != 0) | |
86735b02 | 7006 | gp_reg_size += 4; |
c819be5b | 7007 | gp_reg_size += 2 * UNITS_PER_WORD; |
86735b02 | 7008 | gmask |= 3 << regno; |
c819be5b | 7009 | regno++; |
86735b02 | 7010 | need_aligned_p = 1; |
c819be5b JW |
7011 | } |
7012 | else | |
7013 | { | |
7014 | gp_reg_size += UNITS_PER_WORD; | |
86735b02 | 7015 | gmask |= 1 << regno; |
c819be5b JW |
7016 | } |
7017 | } | |
7018 | } | |
c819be5b JW |
7019 | |
7020 | /* Calculate space needed for fp registers. */ | |
7021 | for (regno = 32; regno <= 63; regno++) | |
7022 | { | |
7023 | if (regs_ever_live[regno] && !call_used_regs[regno]) | |
7024 | { | |
7025 | fp_reg_size += UNITS_PER_WORD; | |
7026 | fmask |= 1 << (regno - 32); | |
7027 | } | |
7028 | } | |
7029 | ||
86735b02 DE |
7030 | if (gmask || fmask) |
7031 | { | |
7032 | int n; | |
7033 | reg_offset = FIRST_PARM_OFFSET(0) + args_size; | |
7034 | /* Ensure save area is 8 byte aligned if we need it. */ | |
7035 | n = reg_offset % 8; | |
7036 | if (need_aligned_p && n != 0) | |
7037 | { | |
7038 | total_size += 8 - n; | |
7039 | reg_offset += 8 - n; | |
7040 | } | |
7041 | total_size += gp_reg_size + fp_reg_size; | |
7042 | } | |
c819be5b | 7043 | |
8c64be75 SC |
7044 | /* If we must allocate a stack frame at all, we must also allocate |
7045 | room for register window spillage, so as to be binary compatible | |
7046 | with libraries and operating systems that do not use -mflat. */ | |
7047 | if (total_size > 0) | |
7048 | total_size += extra_size; | |
7049 | else | |
7050 | extra_size = 0; | |
c819be5b JW |
7051 | |
7052 | total_size = SPARC_STACK_ALIGN (total_size); | |
7053 | ||
7054 | /* Save other computed information. */ | |
7055 | current_frame_info.total_size = total_size; | |
7056 | current_frame_info.var_size = var_size; | |
7057 | current_frame_info.args_size = args_size; | |
7058 | current_frame_info.extra_size = extra_size; | |
7059 | current_frame_info.gp_reg_size = gp_reg_size; | |
7060 | current_frame_info.fp_reg_size = fp_reg_size; | |
86735b02 | 7061 | current_frame_info.gmask = gmask; |
c819be5b | 7062 | current_frame_info.fmask = fmask; |
86735b02 | 7063 | current_frame_info.reg_offset = reg_offset; |
c819be5b JW |
7064 | current_frame_info.initialized = reload_completed; |
7065 | ||
c819be5b JW |
7066 | /* Ok, we're done. */ |
7067 | return total_size; | |
7068 | } | |
7069 | \f | |
86735b02 DE |
7070 | /* Save/restore registers in GMASK and FMASK at register BASE_REG plus offset |
7071 | OFFSET. | |
7072 | ||
7073 | BASE_REG must be 8 byte aligned. This allows us to test OFFSET for | |
7074 | appropriate alignment and use DOUBLEWORD_OP when we can. We assume | |
7075 | [BASE_REG+OFFSET] will always be a valid address. | |
7076 | ||
7077 | WORD_OP is either "st" for save, "ld" for restore. | |
7078 | DOUBLEWORD_OP is either "std" for save, "ldd" for restore. */ | |
c819be5b JW |
7079 | |
7080 | void | |
96987e96 DE |
7081 | sparc_flat_save_restore (file, base_reg, offset, gmask, fmask, word_op, |
7082 | doubleword_op, base_offset) | |
86735b02 | 7083 | FILE *file; |
b1474bb7 | 7084 | const char *base_reg; |
86735b02 DE |
7085 | unsigned int offset; |
7086 | unsigned long gmask; | |
7087 | unsigned long fmask; | |
b1474bb7 KG |
7088 | const char *word_op; |
7089 | const char *doubleword_op; | |
c53aa195 | 7090 | unsigned long base_offset; |
c819be5b JW |
7091 | { |
7092 | int regno; | |
c819be5b | 7093 | |
86735b02 DE |
7094 | if (gmask == 0 && fmask == 0) |
7095 | return; | |
c819be5b | 7096 | |
86735b02 DE |
7097 | /* Save registers starting from high to low. We've already saved the |
7098 | previous frame pointer and previous return address for the debugger's | |
7099 | sake. The debugger allows us to not need a nop in the epilog if at least | |
7100 | one register is reloaded in addition to return address. */ | |
c819be5b | 7101 | |
86735b02 | 7102 | if (gmask) |
c819be5b JW |
7103 | { |
7104 | for (regno = 1; regno <= 31; regno++) | |
7105 | { | |
86735b02 | 7106 | if ((gmask & (1L << regno)) != 0) |
c819be5b | 7107 | { |
86735b02 | 7108 | if ((regno & 0x1) == 0 && ((gmask & (1L << (regno+1))) != 0)) |
c819be5b | 7109 | { |
86735b02 DE |
7110 | /* We can save two registers in a row. If we're not at a |
7111 | double word boundary, move to one. | |
7112 | sparc_flat_compute_frame_size ensures there's room to do | |
7113 | this. */ | |
7114 | if (offset % 8 != 0) | |
7115 | offset += UNITS_PER_WORD; | |
7116 | ||
c819be5b | 7117 | if (word_op[0] == 's') |
c53aa195 | 7118 | { |
e0d80184 | 7119 | fprintf (file, "\t%s\t%s, [%s+%d]\n", |
c53aa195 JM |
7120 | doubleword_op, reg_names[regno], |
7121 | base_reg, offset); | |
0021b564 | 7122 | if (dwarf2out_do_frame ()) |
c53aa195 | 7123 | { |
96987e96 | 7124 | char *l = dwarf2out_cfi_label (); |
c53aa195 JM |
7125 | dwarf2out_reg_save (l, regno, offset + base_offset); |
7126 | dwarf2out_reg_save | |
7127 | (l, regno+1, offset+base_offset + UNITS_PER_WORD); | |
7128 | } | |
c53aa195 | 7129 | } |
c819be5b | 7130 | else |
e0d80184 | 7131 | fprintf (file, "\t%s\t[%s+%d], %s\n", |
86735b02 | 7132 | doubleword_op, base_reg, offset, |
c819be5b JW |
7133 | reg_names[regno]); |
7134 | ||
86735b02 | 7135 | offset += 2 * UNITS_PER_WORD; |
c819be5b JW |
7136 | regno++; |
7137 | } | |
7138 | else | |
7139 | { | |
7140 | if (word_op[0] == 's') | |
c53aa195 | 7141 | { |
e0d80184 | 7142 | fprintf (file, "\t%s\t%s, [%s+%d]\n", |
c53aa195 JM |
7143 | word_op, reg_names[regno], |
7144 | base_reg, offset); | |
0021b564 | 7145 | if (dwarf2out_do_frame ()) |
c53aa195 | 7146 | dwarf2out_reg_save ("", regno, offset + base_offset); |
c53aa195 | 7147 | } |
c819be5b | 7148 | else |
e0d80184 | 7149 | fprintf (file, "\t%s\t[%s+%d], %s\n", |
86735b02 | 7150 | word_op, base_reg, offset, reg_names[regno]); |
c819be5b | 7151 | |
86735b02 | 7152 | offset += UNITS_PER_WORD; |
c819be5b JW |
7153 | } |
7154 | } | |
7155 | } | |
7156 | } | |
7157 | ||
7158 | if (fmask) | |
7159 | { | |
7160 | for (regno = 32; regno <= 63; regno++) | |
7161 | { | |
7162 | if ((fmask & (1L << (regno - 32))) != 0) | |
7163 | { | |
7164 | if (word_op[0] == 's') | |
c53aa195 | 7165 | { |
e0d80184 | 7166 | fprintf (file, "\t%s\t%s, [%s+%d]\n", |
c53aa195 JM |
7167 | word_op, reg_names[regno], |
7168 | base_reg, offset); | |
0021b564 | 7169 | if (dwarf2out_do_frame ()) |
c53aa195 | 7170 | dwarf2out_reg_save ("", regno, offset + base_offset); |
c53aa195 | 7171 | } |
c819be5b | 7172 | else |
e0d80184 | 7173 | fprintf (file, "\t%s\t[%s+%d], %s\n", |
86735b02 | 7174 | word_op, base_reg, offset, reg_names[regno]); |
c819be5b | 7175 | |
86735b02 | 7176 | offset += UNITS_PER_WORD; |
c819be5b JW |
7177 | } |
7178 | } | |
7179 | } | |
7180 | } | |
7181 | \f | |
7182 | /* Set up the stack and frame (if desired) for the function. */ | |
7183 | ||
08c148a8 NB |
7184 | static void |
7185 | sparc_flat_function_prologue (file, size) | |
c819be5b | 7186 | FILE *file; |
08c148a8 | 7187 | HOST_WIDE_INT size; |
c819be5b | 7188 | { |
99f44eba | 7189 | const char *sp_str = reg_names[STACK_POINTER_REGNUM]; |
86735b02 | 7190 | unsigned long gmask = current_frame_info.gmask; |
a07c1915 | 7191 | |
1cb36a98 RH |
7192 | sparc_output_scratch_registers (file); |
7193 | ||
c6aa9ce1 | 7194 | /* This is only for the human reader. */ |
bf62bbf1 | 7195 | fprintf (file, "\t%s#PROLOGUE# 0\n", ASM_COMMENT_START); |
5e9defae | 7196 | fprintf (file, "\t%s# vars= %ld, regs= %d/%d, args= %d, extra= %ld\n", |
bf62bbf1 | 7197 | ASM_COMMENT_START, |
86735b02 DE |
7198 | current_frame_info.var_size, |
7199 | current_frame_info.gp_reg_size / 4, | |
9f8b85b8 | 7200 | current_frame_info.fp_reg_size / 4, |
86735b02 DE |
7201 | current_function_outgoing_args_size, |
7202 | current_frame_info.extra_size); | |
c819be5b JW |
7203 | |
7204 | size = SPARC_STACK_ALIGN (size); | |
86735b02 DE |
7205 | size = (! current_frame_info.initialized |
7206 | ? sparc_flat_compute_frame_size (size) | |
7207 | : current_frame_info.total_size); | |
c819be5b | 7208 | |
86735b02 DE |
7209 | /* These cases shouldn't happen. Catch them now. */ |
7210 | if (size == 0 && (gmask || current_frame_info.fmask)) | |
7211 | abort (); | |
c819be5b | 7212 | |
86735b02 DE |
7213 | /* Allocate our stack frame by decrementing %sp. |
7214 | At present, the only algorithm gdb can use to determine if this is a | |
7215 | flat frame is if we always set %i7 if we set %sp. This can be optimized | |
7216 | in the future by putting in some sort of debugging information that says | |
7217 | this is a `flat' function. However, there is still the case of debugging | |
7218 | code without such debugging information (including cases where most fns | |
7219 | have such info, but there is one that doesn't). So, always do this now | |
7220 | so we don't get a lot of code out there that gdb can't handle. | |
7221 | If the frame pointer isn't needn't then that's ok - gdb won't be able to | |
7222 | distinguish us from a non-flat function but there won't (and shouldn't) | |
7223 | be any differences anyway. The return pc is saved (if necessary) right | |
7224 | after %i7 so gdb won't have to look too far to find it. */ | |
7225 | if (size > 0) | |
c819be5b | 7226 | { |
86735b02 | 7227 | unsigned int reg_offset = current_frame_info.reg_offset; |
563c12b0 | 7228 | const char *const fp_str = reg_names[HARD_FRAME_POINTER_REGNUM]; |
83182544 | 7229 | static const char *const t1_str = "%g1"; |
86735b02 DE |
7230 | |
7231 | /* Things get a little tricky if local variables take up more than ~4096 | |
7232 | bytes and outgoing arguments take up more than ~4096 bytes. When that | |
7233 | happens, the register save area can't be accessed from either end of | |
7234 | the frame. Handle this by decrementing %sp to the start of the gp | |
7235 | register save area, save the regs, update %i7, and then set %sp to its | |
7236 | final value. Given that we only have one scratch register to play | |
7237 | with it is the cheapest solution, and it helps gdb out as it won't | |
7238 | slow down recognition of flat functions. | |
7239 | Don't change the order of insns emitted here without checking with | |
7240 | the gdb folk first. */ | |
7241 | ||
ddd5a7c1 | 7242 | /* Is the entire register save area offsettable from %sp? */ |
fbd039b2 | 7243 | if (reg_offset < 4096 - 64 * (unsigned) UNITS_PER_WORD) |
86735b02 DE |
7244 | { |
7245 | if (size <= 4096) | |
7246 | { | |
e0d80184 | 7247 | fprintf (file, "\tadd\t%s, %d, %s\n", |
0d587737 | 7248 | sp_str, (int) -size, sp_str); |
563c12b0 | 7249 | if (gmask & HARD_FRAME_POINTER_MASK) |
86735b02 | 7250 | { |
e0d80184 | 7251 | fprintf (file, "\tst\t%s, [%s+%d]\n", |
86735b02 | 7252 | fp_str, sp_str, reg_offset); |
e0d80184 | 7253 | fprintf (file, "\tsub\t%s, %d, %s\t%s# set up frame pointer\n", |
0d587737 | 7254 | sp_str, (int) -size, fp_str, ASM_COMMENT_START); |
86735b02 DE |
7255 | reg_offset += 4; |
7256 | } | |
7257 | } | |
7258 | else | |
7259 | { | |
4a0a75dd KG |
7260 | fprintf (file, "\tset\t" HOST_WIDE_INT_PRINT_DEC |
7261 | ", %s\n\tsub\t%s, %s, %s\n", | |
7262 | size, t1_str, sp_str, t1_str, sp_str); | |
563c12b0 | 7263 | if (gmask & HARD_FRAME_POINTER_MASK) |
86735b02 | 7264 | { |
e0d80184 | 7265 | fprintf (file, "\tst\t%s, [%s+%d]\n", |
86735b02 | 7266 | fp_str, sp_str, reg_offset); |
e0d80184 | 7267 | fprintf (file, "\tadd\t%s, %s, %s\t%s# set up frame pointer\n", |
bf62bbf1 | 7268 | sp_str, t1_str, fp_str, ASM_COMMENT_START); |
86735b02 DE |
7269 | reg_offset += 4; |
7270 | } | |
7271 | } | |
0021b564 | 7272 | if (dwarf2out_do_frame ()) |
c53aa195 | 7273 | { |
96987e96 | 7274 | char *l = dwarf2out_cfi_label (); |
563c12b0 | 7275 | if (gmask & HARD_FRAME_POINTER_MASK) |
c53aa195 | 7276 | { |
563c12b0 | 7277 | dwarf2out_reg_save (l, HARD_FRAME_POINTER_REGNUM, |
c53aa195 | 7278 | reg_offset - 4 - size); |
563c12b0 | 7279 | dwarf2out_def_cfa (l, HARD_FRAME_POINTER_REGNUM, 0); |
c53aa195 JM |
7280 | } |
7281 | else | |
7282 | dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, size); | |
7283 | } | |
86735b02 DE |
7284 | if (gmask & RETURN_ADDR_MASK) |
7285 | { | |
e0d80184 | 7286 | fprintf (file, "\tst\t%s, [%s+%d]\n", |
86735b02 | 7287 | reg_names[RETURN_ADDR_REGNUM], sp_str, reg_offset); |
0021b564 | 7288 | if (dwarf2out_do_frame ()) |
c53aa195 | 7289 | dwarf2out_return_save ("", reg_offset - size); |
86735b02 DE |
7290 | reg_offset += 4; |
7291 | } | |
7292 | sparc_flat_save_restore (file, sp_str, reg_offset, | |
563c12b0 | 7293 | gmask & ~(HARD_FRAME_POINTER_MASK | RETURN_ADDR_MASK), |
86735b02 | 7294 | current_frame_info.fmask, |
84e884e9 | 7295 | "st", "std", -size); |
86735b02 | 7296 | } |
c819be5b | 7297 | else |
86735b02 DE |
7298 | { |
7299 | /* Subtract %sp in two steps, but make sure there is always a | |
7300 | 64 byte register save area, and %sp is properly aligned. */ | |
7301 | /* Amount to decrement %sp by, the first time. */ | |
08c148a8 | 7302 | unsigned HOST_WIDE_INT size1 = ((size - reg_offset + 64) + 15) & -16; |
86735b02 | 7303 | /* Offset to register save area from %sp. */ |
08c148a8 | 7304 | unsigned HOST_WIDE_INT offset = size1 - (size - reg_offset); |
86735b02 DE |
7305 | |
7306 | if (size1 <= 4096) | |
7307 | { | |
e0d80184 | 7308 | fprintf (file, "\tadd\t%s, %d, %s\n", |
0d587737 | 7309 | sp_str, (int) -size1, sp_str); |
563c12b0 | 7310 | if (gmask & HARD_FRAME_POINTER_MASK) |
86735b02 | 7311 | { |
e0d80184 | 7312 | fprintf (file, "\tst\t%s, [%s+%d]\n\tsub\t%s, %d, %s\t%s# set up frame pointer\n", |
0d587737 KG |
7313 | fp_str, sp_str, (int) offset, sp_str, (int) -size1, |
7314 | fp_str, ASM_COMMENT_START); | |
86735b02 DE |
7315 | offset += 4; |
7316 | } | |
7317 | } | |
7318 | else | |
7319 | { | |
4a0a75dd KG |
7320 | fprintf (file, "\tset\t" HOST_WIDE_INT_PRINT_DEC |
7321 | ", %s\n\tsub\t%s, %s, %s\n", | |
7322 | size1, t1_str, sp_str, t1_str, sp_str); | |
563c12b0 | 7323 | if (gmask & HARD_FRAME_POINTER_MASK) |
86735b02 | 7324 | { |
e0d80184 | 7325 | fprintf (file, "\tst\t%s, [%s+%d]\n\tadd\t%s, %s, %s\t%s# set up frame pointer\n", |
0d587737 KG |
7326 | fp_str, sp_str, (int) offset, sp_str, t1_str, |
7327 | fp_str, ASM_COMMENT_START); | |
86735b02 DE |
7328 | offset += 4; |
7329 | } | |
7330 | } | |
0021b564 | 7331 | if (dwarf2out_do_frame ()) |
c53aa195 | 7332 | { |
96987e96 | 7333 | char *l = dwarf2out_cfi_label (); |
563c12b0 | 7334 | if (gmask & HARD_FRAME_POINTER_MASK) |
c53aa195 | 7335 | { |
563c12b0 | 7336 | dwarf2out_reg_save (l, HARD_FRAME_POINTER_REGNUM, |
c53aa195 | 7337 | offset - 4 - size1); |
563c12b0 | 7338 | dwarf2out_def_cfa (l, HARD_FRAME_POINTER_REGNUM, 0); |
c53aa195 JM |
7339 | } |
7340 | else | |
7341 | dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, size1); | |
7342 | } | |
86735b02 DE |
7343 | if (gmask & RETURN_ADDR_MASK) |
7344 | { | |
e0d80184 | 7345 | fprintf (file, "\tst\t%s, [%s+%d]\n", |
0d587737 | 7346 | reg_names[RETURN_ADDR_REGNUM], sp_str, (int) offset); |
0021b564 | 7347 | if (dwarf2out_do_frame ()) |
c53aa195 JM |
7348 | /* offset - size1 == reg_offset - size |
7349 | if reg_offset were updated above like offset. */ | |
7350 | dwarf2out_return_save ("", offset - size1); | |
86735b02 DE |
7351 | offset += 4; |
7352 | } | |
7353 | sparc_flat_save_restore (file, sp_str, offset, | |
563c12b0 | 7354 | gmask & ~(HARD_FRAME_POINTER_MASK | RETURN_ADDR_MASK), |
86735b02 | 7355 | current_frame_info.fmask, |
84e884e9 | 7356 | "st", "std", -size1); |
4a0a75dd KG |
7357 | fprintf (file, "\tset\t" HOST_WIDE_INT_PRINT_DEC |
7358 | ", %s\n\tsub\t%s, %s, %s\n", | |
7359 | size - size1, t1_str, sp_str, t1_str, sp_str); | |
0021b564 | 7360 | if (dwarf2out_do_frame ()) |
563c12b0 | 7361 | if (! (gmask & HARD_FRAME_POINTER_MASK)) |
c53aa195 | 7362 | dwarf2out_def_cfa ("", STACK_POINTER_REGNUM, size); |
86735b02 | 7363 | } |
c819be5b | 7364 | } |
c6aa9ce1 | 7365 | |
bf62bbf1 | 7366 | fprintf (file, "\t%s#PROLOGUE# 1\n", ASM_COMMENT_START); |
c819be5b JW |
7367 | } |
7368 | \f | |
7369 | /* Do any necessary cleanup after a function to restore stack, frame, | |
80ffc95e | 7370 | and regs. */ |
c819be5b | 7371 | |
08c148a8 NB |
7372 | static void |
7373 | sparc_flat_function_epilogue (file, size) | |
c819be5b | 7374 | FILE *file; |
08c148a8 | 7375 | HOST_WIDE_INT size; |
c819be5b | 7376 | { |
c819be5b JW |
7377 | rtx epilogue_delay = current_function_epilogue_delay_list; |
7378 | int noepilogue = FALSE; | |
c819be5b | 7379 | |
c6aa9ce1 | 7380 | /* This is only for the human reader. */ |
bf62bbf1 | 7381 | fprintf (file, "\t%s#EPILOGUE#\n", ASM_COMMENT_START); |
c6aa9ce1 | 7382 | |
c819be5b JW |
7383 | /* The epilogue does not depend on any registers, but the stack |
7384 | registers, so we assume that if we have 1 pending nop, it can be | |
7385 | ignored, and 2 it must be filled (2 nops occur for integer | |
7386 | multiply and divide). */ | |
7387 | ||
7388 | size = SPARC_STACK_ALIGN (size); | |
86735b02 | 7389 | size = (!current_frame_info.initialized |
c6aa9ce1 | 7390 | ? sparc_flat_compute_frame_size (size) |
c819be5b JW |
7391 | : current_frame_info.total_size); |
7392 | ||
86735b02 | 7393 | if (size == 0 && epilogue_delay == 0) |
c819be5b JW |
7394 | { |
7395 | rtx insn = get_last_insn (); | |
7396 | ||
7397 | /* If the last insn was a BARRIER, we don't have to write any code | |
7398 | because a jump (aka return) was put there. */ | |
7399 | if (GET_CODE (insn) == NOTE) | |
7400 | insn = prev_nonnote_insn (insn); | |
7401 | if (insn && GET_CODE (insn) == BARRIER) | |
7402 | noepilogue = TRUE; | |
7403 | } | |
7404 | ||
7405 | if (!noepilogue) | |
7406 | { | |
08c148a8 NB |
7407 | unsigned HOST_WIDE_INT reg_offset = current_frame_info.reg_offset; |
7408 | unsigned HOST_WIDE_INT size1; | |
27c38fbe | 7409 | const char *const sp_str = reg_names[STACK_POINTER_REGNUM]; |
563c12b0 | 7410 | const char *const fp_str = reg_names[HARD_FRAME_POINTER_REGNUM]; |
83182544 | 7411 | static const char *const t1_str = "%g1"; |
86735b02 | 7412 | |
c819be5b JW |
7413 | /* In the reload sequence, we don't need to fill the load delay |
7414 | slots for most of the loads, also see if we can fill the final | |
7415 | delay slot if not otherwise filled by the reload sequence. */ | |
7416 | ||
86735b02 | 7417 | if (size > 4095) |
4a0a75dd KG |
7418 | fprintf (file, "\tset\t" HOST_WIDE_INT_PRINT_DEC ", %s\n", |
7419 | size, t1_str); | |
c819be5b JW |
7420 | |
7421 | if (frame_pointer_needed) | |
7422 | { | |
86735b02 | 7423 | if (size > 4095) |
e0d80184 | 7424 | fprintf (file,"\tsub\t%s, %s, %s\t\t%s# sp not trusted here\n", |
bf62bbf1 | 7425 | fp_str, t1_str, sp_str, ASM_COMMENT_START); |
c819be5b | 7426 | else |
e0d80184 | 7427 | fprintf (file,"\tsub\t%s, %d, %s\t\t%s# sp not trusted here\n", |
0d587737 | 7428 | fp_str, (int) size, sp_str, ASM_COMMENT_START); |
c819be5b JW |
7429 | } |
7430 | ||
ddd5a7c1 | 7431 | /* Is the entire register save area offsettable from %sp? */ |
fbd039b2 | 7432 | if (reg_offset < 4096 - 64 * (unsigned) UNITS_PER_WORD) |
86735b02 DE |
7433 | { |
7434 | size1 = 0; | |
7435 | } | |
7436 | else | |
7437 | { | |
7438 | /* Restore %sp in two steps, but make sure there is always a | |
7439 | 64 byte register save area, and %sp is properly aligned. */ | |
7440 | /* Amount to increment %sp by, the first time. */ | |
7441 | size1 = ((reg_offset - 64 - 16) + 15) & -16; | |
7442 | /* Offset to register save area from %sp. */ | |
7443 | reg_offset = size1 - reg_offset; | |
7444 | ||
4a0a75dd KG |
7445 | fprintf (file, "\tset\t" HOST_WIDE_INT_PRINT_DEC |
7446 | ", %s\n\tadd\t%s, %s, %s\n", | |
7447 | size1, t1_str, sp_str, t1_str, sp_str); | |
86735b02 DE |
7448 | } |
7449 | ||
7450 | /* We must restore the frame pointer and return address reg first | |
7451 | because they are treated specially by the prologue output code. */ | |
563c12b0 | 7452 | if (current_frame_info.gmask & HARD_FRAME_POINTER_MASK) |
86735b02 | 7453 | { |
e0d80184 | 7454 | fprintf (file, "\tld\t[%s+%d], %s\n", |
0d587737 | 7455 | sp_str, (int) reg_offset, fp_str); |
86735b02 DE |
7456 | reg_offset += 4; |
7457 | } | |
7458 | if (current_frame_info.gmask & RETURN_ADDR_MASK) | |
7459 | { | |
e0d80184 | 7460 | fprintf (file, "\tld\t[%s+%d], %s\n", |
0d587737 | 7461 | sp_str, (int) reg_offset, reg_names[RETURN_ADDR_REGNUM]); |
86735b02 DE |
7462 | reg_offset += 4; |
7463 | } | |
7464 | ||
7465 | /* Restore any remaining saved registers. */ | |
7466 | sparc_flat_save_restore (file, sp_str, reg_offset, | |
563c12b0 | 7467 | current_frame_info.gmask & ~(HARD_FRAME_POINTER_MASK | RETURN_ADDR_MASK), |
86735b02 | 7468 | current_frame_info.fmask, |
c53aa195 | 7469 | "ld", "ldd", 0); |
86735b02 DE |
7470 | |
7471 | /* If we had to increment %sp in two steps, record it so the second | |
7472 | restoration in the epilogue finishes up. */ | |
7473 | if (size1 > 0) | |
7474 | { | |
7475 | size -= size1; | |
7476 | if (size > 4095) | |
4a0a75dd KG |
7477 | fprintf (file, "\tset\t" HOST_WIDE_INT_PRINT_DEC ", %s\n", |
7478 | size, t1_str); | |
86735b02 | 7479 | } |
c819be5b | 7480 | |
c819be5b | 7481 | if (current_function_returns_struct) |
e0d80184 | 7482 | fprintf (file, "\tjmp\t%%o7+12\n"); |
c819be5b JW |
7483 | else |
7484 | fprintf (file, "\tretl\n"); | |
7485 | ||
7486 | /* If the only register saved is the return address, we need a | |
7487 | nop, unless we have an instruction to put into it. Otherwise | |
7488 | we don't since reloading multiple registers doesn't reference | |
7489 | the register being loaded. */ | |
7490 | ||
7491 | if (epilogue_delay) | |
7492 | { | |
86735b02 | 7493 | if (size) |
c819be5b JW |
7494 | abort (); |
7495 | final_scan_insn (XEXP (epilogue_delay, 0), file, 1, -2, 1); | |
7496 | } | |
7497 | ||
86735b02 | 7498 | else if (size > 4095) |
e0d80184 | 7499 | fprintf (file, "\tadd\t%s, %s, %s\n", sp_str, t1_str, sp_str); |
c819be5b | 7500 | |
86735b02 | 7501 | else if (size > 0) |
0d587737 | 7502 | fprintf (file, "\tadd\t%s, %d, %s\n", sp_str, (int) size, sp_str); |
c819be5b JW |
7503 | |
7504 | else | |
7505 | fprintf (file, "\tnop\n"); | |
7506 | } | |
7507 | ||
7508 | /* Reset state info for each function. */ | |
7509 | current_frame_info = zero_frame_info; | |
e0d80184 DM |
7510 | |
7511 | sparc_output_deferred_case_vectors (); | |
c819be5b JW |
7512 | } |
7513 | \f | |
7514 | /* Define the number of delay slots needed for the function epilogue. | |
7515 | ||
7516 | On the sparc, we need a slot if either no stack has been allocated, | |
7517 | or the only register saved is the return register. */ | |
7518 | ||
7519 | int | |
c6aa9ce1 | 7520 | sparc_flat_epilogue_delay_slots () |
c819be5b JW |
7521 | { |
7522 | if (!current_frame_info.initialized) | |
c6aa9ce1 | 7523 | (void) sparc_flat_compute_frame_size (get_frame_size ()); |
c819be5b JW |
7524 | |
7525 | if (current_frame_info.total_size == 0) | |
7526 | return 1; | |
7527 | ||
c819be5b JW |
7528 | return 0; |
7529 | } | |
7530 | ||
51f26c45 | 7531 | /* Return true if TRIAL is a valid insn for the epilogue delay slot. |
c819be5b JW |
7532 | Any single length instruction which doesn't reference the stack or frame |
7533 | pointer is OK. */ | |
7534 | ||
7535 | int | |
c6aa9ce1 | 7536 | sparc_flat_eligible_for_epilogue_delay (trial, slot) |
c819be5b | 7537 | rtx trial; |
db3d4438 | 7538 | int slot ATTRIBUTE_UNUSED; |
c819be5b | 7539 | { |
c4ce6853 DE |
7540 | rtx pat = PATTERN (trial); |
7541 | ||
7542 | if (get_attr_length (trial) != 1) | |
7543 | return 0; | |
7544 | ||
c4ce6853 DE |
7545 | if (! reg_mentioned_p (stack_pointer_rtx, pat) |
7546 | && ! reg_mentioned_p (frame_pointer_rtx, pat)) | |
c819be5b | 7547 | return 1; |
c4ce6853 | 7548 | |
c819be5b JW |
7549 | return 0; |
7550 | } | |
dbb54862 JW |
7551 | \f |
7552 | /* Adjust the cost of a scheduling dependency. Return the new cost of | |
7553 | a dependency LINK or INSN on DEP_INSN. COST is the current cost. */ | |
7554 | ||
8947065c | 7555 | static int |
dbb54862 JW |
7556 | supersparc_adjust_cost (insn, link, dep_insn, cost) |
7557 | rtx insn; | |
7558 | rtx link; | |
7559 | rtx dep_insn; | |
7560 | int cost; | |
7561 | { | |
7562 | enum attr_type insn_type; | |
7563 | ||
7564 | if (! recog_memoized (insn)) | |
7565 | return 0; | |
7566 | ||
7567 | insn_type = get_attr_type (insn); | |
7568 | ||
7569 | if (REG_NOTE_KIND (link) == 0) | |
7570 | { | |
7571 | /* Data dependency; DEP_INSN writes a register that INSN reads some | |
7572 | cycles later. */ | |
7573 | ||
7574 | /* if a load, then the dependence must be on the memory address; | |
3bc8b61e DM |
7575 | add an extra "cycle". Note that the cost could be two cycles |
7576 | if the reg was written late in an instruction group; we ca not tell | |
dbb54862 JW |
7577 | here. */ |
7578 | if (insn_type == TYPE_LOAD || insn_type == TYPE_FPLOAD) | |
7579 | return cost + 3; | |
7580 | ||
7581 | /* Get the delay only if the address of the store is the dependence. */ | |
7582 | if (insn_type == TYPE_STORE || insn_type == TYPE_FPSTORE) | |
7583 | { | |
7584 | rtx pat = PATTERN(insn); | |
7585 | rtx dep_pat = PATTERN (dep_insn); | |
7586 | ||
7587 | if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET) | |
3bc8b61e | 7588 | return cost; /* This should not happen! */ |
dbb54862 JW |
7589 | |
7590 | /* The dependency between the two instructions was on the data that | |
7591 | is being stored. Assume that this implies that the address of the | |
7592 | store is not dependent. */ | |
7593 | if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat))) | |
7594 | return cost; | |
7595 | ||
7596 | return cost + 3; /* An approximation. */ | |
7597 | } | |
7598 | ||
7599 | /* A shift instruction cannot receive its data from an instruction | |
7600 | in the same cycle; add a one cycle penalty. */ | |
7601 | if (insn_type == TYPE_SHIFT) | |
7602 | return cost + 3; /* Split before cascade into shift. */ | |
7603 | } | |
7604 | else | |
7605 | { | |
7606 | /* Anti- or output- dependency; DEP_INSN reads/writes a register that | |
7607 | INSN writes some cycles later. */ | |
7608 | ||
7609 | /* These are only significant for the fpu unit; writing a fp reg before | |
7610 | the fpu has finished with it stalls the processor. */ | |
7611 | ||
7612 | /* Reusing an integer register causes no problems. */ | |
7613 | if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT) | |
7614 | return 0; | |
7615 | } | |
7616 | ||
7617 | return cost; | |
7618 | } | |
bfd6bc60 | 7619 | |
8947065c RH |
7620 | static int |
7621 | hypersparc_adjust_cost (insn, link, dep_insn, cost) | |
7622 | rtx insn; | |
7623 | rtx link; | |
7624 | rtx dep_insn; | |
7625 | int cost; | |
7626 | { | |
7627 | enum attr_type insn_type, dep_type; | |
7628 | rtx pat = PATTERN(insn); | |
7629 | rtx dep_pat = PATTERN (dep_insn); | |
7630 | ||
7631 | if (recog_memoized (insn) < 0 || recog_memoized (dep_insn) < 0) | |
7632 | return cost; | |
7633 | ||
7634 | insn_type = get_attr_type (insn); | |
7635 | dep_type = get_attr_type (dep_insn); | |
7636 | ||
7637 | switch (REG_NOTE_KIND (link)) | |
7638 | { | |
7639 | case 0: | |
7640 | /* Data dependency; DEP_INSN writes a register that INSN reads some | |
7641 | cycles later. */ | |
7642 | ||
7643 | switch (insn_type) | |
7644 | { | |
7645 | case TYPE_STORE: | |
7646 | case TYPE_FPSTORE: | |
80ffc95e | 7647 | /* Get the delay iff the address of the store is the dependence. */ |
8947065c RH |
7648 | if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET) |
7649 | return cost; | |
7650 | ||
7651 | if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat))) | |
7652 | return cost; | |
7653 | return cost + 3; | |
7654 | ||
7655 | case TYPE_LOAD: | |
7656 | case TYPE_SLOAD: | |
7657 | case TYPE_FPLOAD: | |
7658 | /* If a load, then the dependence must be on the memory address. If | |
7659 | the addresses aren't equal, then it might be a false dependency */ | |
7660 | if (dep_type == TYPE_STORE || dep_type == TYPE_FPSTORE) | |
7661 | { | |
7662 | if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET | |
7663 | || GET_CODE (SET_DEST (dep_pat)) != MEM | |
7664 | || GET_CODE (SET_SRC (pat)) != MEM | |
7665 | || ! rtx_equal_p (XEXP (SET_DEST (dep_pat), 0), | |
7666 | XEXP (SET_SRC (pat), 0))) | |
7667 | return cost + 2; | |
7668 | ||
7669 | return cost + 8; | |
7670 | } | |
7671 | break; | |
7672 | ||
7673 | case TYPE_BRANCH: | |
7674 | /* Compare to branch latency is 0. There is no benefit from | |
7675 | separating compare and branch. */ | |
7676 | if (dep_type == TYPE_COMPARE) | |
7677 | return 0; | |
7678 | /* Floating point compare to branch latency is less than | |
7679 | compare to conditional move. */ | |
7680 | if (dep_type == TYPE_FPCMP) | |
7681 | return cost - 1; | |
7682 | break; | |
3bb5de61 KG |
7683 | default: |
7684 | break; | |
8947065c RH |
7685 | } |
7686 | break; | |
7687 | ||
7688 | case REG_DEP_ANTI: | |
80ffc95e | 7689 | /* Anti-dependencies only penalize the fpu unit. */ |
8947065c RH |
7690 | if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT) |
7691 | return 0; | |
7692 | break; | |
7693 | ||
7694 | default: | |
7695 | break; | |
7696 | } | |
7697 | ||
7698 | return cost; | |
7699 | } | |
7700 | ||
c237e94a | 7701 | static int |
8947065c RH |
7702 | sparc_adjust_cost(insn, link, dep, cost) |
7703 | rtx insn; | |
7704 | rtx link; | |
7705 | rtx dep; | |
7706 | int cost; | |
7707 | { | |
7708 | switch (sparc_cpu) | |
7709 | { | |
7710 | case PROCESSOR_SUPERSPARC: | |
7711 | cost = supersparc_adjust_cost (insn, link, dep, cost); | |
7712 | break; | |
7713 | case PROCESSOR_HYPERSPARC: | |
7714 | case PROCESSOR_SPARCLITE86X: | |
7715 | cost = hypersparc_adjust_cost (insn, link, dep, cost); | |
7716 | break; | |
8947065c RH |
7717 | default: |
7718 | break; | |
7719 | } | |
7720 | return cost; | |
7721 | } | |
7722 | ||
fae15c93 VM |
7723 | static void |
7724 | sparc_sched_init (dump, sched_verbose, max_ready) | |
7725 | FILE *dump ATTRIBUTE_UNUSED; | |
7726 | int sched_verbose ATTRIBUTE_UNUSED; | |
7727 | int max_ready ATTRIBUTE_UNUSED; | |
3bc8b61e | 7728 | { |
3bc8b61e | 7729 | } |
fae15c93 | 7730 | |
3bc8b61e | 7731 | static int |
fae15c93 | 7732 | sparc_use_dfa_pipeline_interface () |
3bc8b61e | 7733 | { |
fae15c93 VM |
7734 | if ((1 << sparc_cpu) & |
7735 | ((1 << PROCESSOR_ULTRASPARC) | (1 << PROCESSOR_CYPRESS) | | |
7736 | (1 << PROCESSOR_SUPERSPARC) | (1 << PROCESSOR_HYPERSPARC) | | |
7737 | (1 << PROCESSOR_SPARCLITE86X) | (1 << PROCESSOR_TSC701) | | |
7738 | (1 << PROCESSOR_ULTRASPARC3))) | |
7739 | return 1; | |
3bc8b61e DM |
7740 | return 0; |
7741 | } | |
7742 | ||
fae15c93 VM |
7743 | static int |
7744 | sparc_use_sched_lookahead () | |
7745 | { | |
7746 | if (sparc_cpu == PROCESSOR_ULTRASPARC | |
7747 | || sparc_cpu == PROCESSOR_ULTRASPARC3) | |
7748 | return 4; | |
7749 | if ((1 << sparc_cpu) & | |
7750 | ((1 << PROCESSOR_SUPERSPARC) | (1 << PROCESSOR_HYPERSPARC) | | |
7751 | (1 << PROCESSOR_SPARCLITE86X))) | |
7752 | return 3; | |
3bc8b61e DM |
7753 | return 0; |
7754 | } | |
7755 | ||
fae15c93 | 7756 | static int |
bfd6bc60 JC |
7757 | sparc_issue_rate () |
7758 | { | |
7759 | switch (sparc_cpu) | |
7760 | { | |
fae15c93 VM |
7761 | default: |
7762 | return 1; | |
7763 | case PROCESSOR_V9: | |
284d86e9 | 7764 | /* Assume V9 processors are capable of at least dual-issue. */ |
bfd6bc60 | 7765 | return 2; |
fae15c93 VM |
7766 | case PROCESSOR_SUPERSPARC: |
7767 | return 3; | |
393049a9 RH |
7768 | case PROCESSOR_HYPERSPARC: |
7769 | case PROCESSOR_SPARCLITE86X: | |
7770 | return 2; | |
fae15c93 VM |
7771 | case PROCESSOR_ULTRASPARC: |
7772 | case PROCESSOR_ULTRASPARC3: | |
7773 | return 4; | |
bfd6bc60 JC |
7774 | } |
7775 | } | |
284d86e9 JC |
7776 | |
7777 | static int | |
4df1190a JJ |
7778 | set_extends (insn) |
7779 | rtx insn; | |
284d86e9 JC |
7780 | { |
7781 | register rtx pat = PATTERN (insn); | |
7782 | ||
7783 | switch (GET_CODE (SET_SRC (pat))) | |
7784 | { | |
80ffc95e | 7785 | /* Load and some shift instructions zero extend. */ |
284d86e9 JC |
7786 | case MEM: |
7787 | case ZERO_EXTEND: | |
7788 | /* sethi clears the high bits */ | |
7789 | case HIGH: | |
7790 | /* LO_SUM is used with sethi. sethi cleared the high | |
7791 | bits and the values used with lo_sum are positive */ | |
7792 | case LO_SUM: | |
284d86e9 JC |
7793 | /* Store flag stores 0 or 1 */ |
7794 | case LT: case LTU: | |
7795 | case GT: case GTU: | |
7796 | case LE: case LEU: | |
7797 | case GE: case GEU: | |
7798 | case EQ: | |
7799 | case NE: | |
7800 | return 1; | |
7801 | case AND: | |
7802 | { | |
4df1190a | 7803 | rtx op0 = XEXP (SET_SRC (pat), 0); |
284d86e9 JC |
7804 | rtx op1 = XEXP (SET_SRC (pat), 1); |
7805 | if (GET_CODE (op1) == CONST_INT) | |
7806 | return INTVAL (op1) >= 0; | |
4df1190a JJ |
7807 | if (GET_CODE (op0) != REG) |
7808 | return 0; | |
7809 | if (sparc_check_64 (op0, insn) == 1) | |
284d86e9 | 7810 | return 1; |
4df1190a JJ |
7811 | return (GET_CODE (op1) == REG && sparc_check_64 (op1, insn) == 1); |
7812 | } | |
7813 | case IOR: | |
7814 | case XOR: | |
7815 | { | |
7816 | rtx op0 = XEXP (SET_SRC (pat), 0); | |
7817 | rtx op1 = XEXP (SET_SRC (pat), 1); | |
7818 | if (GET_CODE (op0) != REG || sparc_check_64 (op0, insn) <= 0) | |
7819 | return 0; | |
7820 | if (GET_CODE (op1) == CONST_INT) | |
7821 | return INTVAL (op1) >= 0; | |
7822 | return (GET_CODE (op1) == REG && sparc_check_64 (op1, insn) == 1); | |
284d86e9 | 7823 | } |
284d86e9 JC |
7824 | case LSHIFTRT: |
7825 | return GET_MODE (SET_SRC (pat)) == SImode; | |
80ffc95e | 7826 | /* Positive integers leave the high bits zero. */ |
284d86e9 | 7827 | case CONST_DOUBLE: |
4df1190a | 7828 | return ! (CONST_DOUBLE_LOW (SET_SRC (pat)) & 0x80000000); |
284d86e9 | 7829 | case CONST_INT: |
4df1190a | 7830 | return ! (INTVAL (SET_SRC (pat)) & 0x80000000); |
284d86e9 JC |
7831 | case ASHIFTRT: |
7832 | case SIGN_EXTEND: | |
7833 | return - (GET_MODE (SET_SRC (pat)) == SImode); | |
4df1190a JJ |
7834 | case REG: |
7835 | return sparc_check_64 (SET_SRC (pat), insn); | |
284d86e9 JC |
7836 | default: |
7837 | return 0; | |
7838 | } | |
7839 | } | |
7840 | ||
80ffc95e | 7841 | /* We _ought_ to have only one kind per function, but... */ |
e2500fed GK |
7842 | static GTY(()) rtx sparc_addr_diff_list; |
7843 | static GTY(()) rtx sparc_addr_list; | |
e0d80184 DM |
7844 | |
7845 | void | |
7846 | sparc_defer_case_vector (lab, vec, diff) | |
7847 | rtx lab, vec; | |
7848 | int diff; | |
7849 | { | |
7850 | vec = gen_rtx_EXPR_LIST (VOIDmode, lab, vec); | |
7851 | if (diff) | |
7852 | sparc_addr_diff_list | |
7853 | = gen_rtx_EXPR_LIST (VOIDmode, vec, sparc_addr_diff_list); | |
7854 | else | |
7855 | sparc_addr_list = gen_rtx_EXPR_LIST (VOIDmode, vec, sparc_addr_list); | |
7856 | } | |
7857 | ||
7858 | static void | |
7859 | sparc_output_addr_vec (vec) | |
7860 | rtx vec; | |
7861 | { | |
7862 | rtx lab = XEXP (vec, 0), body = XEXP (vec, 1); | |
7863 | int idx, vlen = XVECLEN (body, 0); | |
7864 | ||
d1accaa3 JJ |
7865 | #ifdef ASM_OUTPUT_ADDR_VEC_START |
7866 | ASM_OUTPUT_ADDR_VEC_START (asm_out_file); | |
7867 | #endif | |
7868 | ||
e0d80184 DM |
7869 | #ifdef ASM_OUTPUT_CASE_LABEL |
7870 | ASM_OUTPUT_CASE_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab), | |
7871 | NEXT_INSN (lab)); | |
7872 | #else | |
4977bab6 | 7873 | (*targetm.asm_out.internal_label) (asm_out_file, "L", CODE_LABEL_NUMBER (lab)); |
e0d80184 DM |
7874 | #endif |
7875 | ||
7876 | for (idx = 0; idx < vlen; idx++) | |
7877 | { | |
7878 | ASM_OUTPUT_ADDR_VEC_ELT | |
7879 | (asm_out_file, CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 0, idx), 0))); | |
7880 | } | |
d1accaa3 JJ |
7881 | |
7882 | #ifdef ASM_OUTPUT_ADDR_VEC_END | |
7883 | ASM_OUTPUT_ADDR_VEC_END (asm_out_file); | |
7884 | #endif | |
e0d80184 DM |
7885 | } |
7886 | ||
7887 | static void | |
7888 | sparc_output_addr_diff_vec (vec) | |
7889 | rtx vec; | |
7890 | { | |
7891 | rtx lab = XEXP (vec, 0), body = XEXP (vec, 1); | |
7892 | rtx base = XEXP (XEXP (body, 0), 0); | |
7893 | int idx, vlen = XVECLEN (body, 1); | |
7894 | ||
d1accaa3 JJ |
7895 | #ifdef ASM_OUTPUT_ADDR_VEC_START |
7896 | ASM_OUTPUT_ADDR_VEC_START (asm_out_file); | |
7897 | #endif | |
7898 | ||
e0d80184 DM |
7899 | #ifdef ASM_OUTPUT_CASE_LABEL |
7900 | ASM_OUTPUT_CASE_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab), | |
7901 | NEXT_INSN (lab)); | |
7902 | #else | |
4977bab6 | 7903 | (*targetm.asm_out.internal_label) (asm_out_file, "L", CODE_LABEL_NUMBER (lab)); |
e0d80184 DM |
7904 | #endif |
7905 | ||
7906 | for (idx = 0; idx < vlen; idx++) | |
7907 | { | |
7908 | ASM_OUTPUT_ADDR_DIFF_ELT | |
7909 | (asm_out_file, | |
7910 | body, | |
7911 | CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 1, idx), 0)), | |
7912 | CODE_LABEL_NUMBER (base)); | |
7913 | } | |
d1accaa3 JJ |
7914 | |
7915 | #ifdef ASM_OUTPUT_ADDR_VEC_END | |
7916 | ASM_OUTPUT_ADDR_VEC_END (asm_out_file); | |
7917 | #endif | |
e0d80184 DM |
7918 | } |
7919 | ||
7920 | static void | |
7921 | sparc_output_deferred_case_vectors () | |
7922 | { | |
7923 | rtx t; | |
d676da68 | 7924 | int align; |
e0d80184 | 7925 | |
f3b8847b DM |
7926 | if (sparc_addr_list == NULL_RTX |
7927 | && sparc_addr_diff_list == NULL_RTX) | |
7928 | return; | |
7929 | ||
e0d80184 DM |
7930 | /* Align to cache line in the function's code section. */ |
7931 | function_section (current_function_decl); | |
d676da68 DM |
7932 | |
7933 | align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT); | |
7934 | if (align > 0) | |
f3b8847b | 7935 | ASM_OUTPUT_ALIGN (asm_out_file, align); |
e0d80184 DM |
7936 | |
7937 | for (t = sparc_addr_list; t ; t = XEXP (t, 1)) | |
7938 | sparc_output_addr_vec (XEXP (t, 0)); | |
7939 | for (t = sparc_addr_diff_list; t ; t = XEXP (t, 1)) | |
7940 | sparc_output_addr_diff_vec (XEXP (t, 0)); | |
7941 | ||
7942 | sparc_addr_list = sparc_addr_diff_list = NULL_RTX; | |
7943 | } | |
7944 | ||
284d86e9 JC |
7945 | /* Return 0 if the high 32 bits of X (the low word of X, if DImode) are |
7946 | unknown. Return 1 if the high bits are zero, -1 if the register is | |
7947 | sign extended. */ | |
7948 | int | |
7949 | sparc_check_64 (x, insn) | |
7950 | rtx x, insn; | |
7951 | { | |
7952 | /* If a register is set only once it is safe to ignore insns this | |
7953 | code does not know how to handle. The loop will either recognize | |
7954 | the single set and return the correct value or fail to recognize | |
7955 | it and return 0. */ | |
7956 | int set_once = 0; | |
4df1190a JJ |
7957 | rtx y = x; |
7958 | ||
7959 | if (GET_CODE (x) != REG) | |
7960 | abort (); | |
7961 | ||
7962 | if (GET_MODE (x) == DImode) | |
7963 | y = gen_rtx_REG (SImode, REGNO (x) + WORDS_BIG_ENDIAN); | |
284d86e9 | 7964 | |
4df1190a JJ |
7965 | if (flag_expensive_optimizations |
7966 | && REG_N_SETS (REGNO (y)) == 1) | |
284d86e9 JC |
7967 | set_once = 1; |
7968 | ||
7969 | if (insn == 0) | |
d6f4ec51 KG |
7970 | { |
7971 | if (set_once) | |
7972 | insn = get_last_insn_anywhere (); | |
7973 | else | |
7974 | return 0; | |
7975 | } | |
284d86e9 | 7976 | |
d6f4ec51 | 7977 | while ((insn = PREV_INSN (insn))) |
284d86e9 JC |
7978 | { |
7979 | switch (GET_CODE (insn)) | |
7980 | { | |
7981 | case JUMP_INSN: | |
7982 | case NOTE: | |
7983 | break; | |
7984 | case CODE_LABEL: | |
7985 | case CALL_INSN: | |
7986 | default: | |
7987 | if (! set_once) | |
7988 | return 0; | |
7989 | break; | |
7990 | case INSN: | |
7991 | { | |
7992 | rtx pat = PATTERN (insn); | |
7993 | if (GET_CODE (pat) != SET) | |
7994 | return 0; | |
7995 | if (rtx_equal_p (x, SET_DEST (pat))) | |
4df1190a JJ |
7996 | return set_extends (insn); |
7997 | if (y && rtx_equal_p (y, SET_DEST (pat))) | |
7998 | return set_extends (insn); | |
7999 | if (reg_overlap_mentioned_p (SET_DEST (pat), y)) | |
284d86e9 JC |
8000 | return 0; |
8001 | } | |
8002 | } | |
8003 | } | |
8004 | return 0; | |
8005 | } | |
8006 | ||
01d3224a EB |
8007 | /* Returns assembly code to perform a DImode shift using |
8008 | a 64-bit global or out register on SPARC-V8+. */ | |
284d86e9 JC |
8009 | char * |
8010 | sparc_v8plus_shift (operands, insn, opcode) | |
8011 | rtx *operands; | |
8012 | rtx insn; | |
b1474bb7 | 8013 | const char *opcode; |
284d86e9 JC |
8014 | { |
8015 | static char asm_code[60]; | |
8016 | ||
01d3224a EB |
8017 | /* The scratch register is only required when the destination |
8018 | register is not a 64-bit global or out register. */ | |
8019 | if (which_alternative != 2) | |
284d86e9 | 8020 | operands[3] = operands[0]; |
01d3224a | 8021 | |
c6b0465b JC |
8022 | if (GET_CODE (operands[1]) == CONST_INT) |
8023 | { | |
4df1190a | 8024 | output_asm_insn ("mov\t%1, %3", operands); |
c6b0465b JC |
8025 | } |
8026 | else | |
8027 | { | |
4df1190a | 8028 | output_asm_insn ("sllx\t%H1, 32, %3", operands); |
c6b0465b | 8029 | if (sparc_check_64 (operands[1], insn) <= 0) |
4df1190a JJ |
8030 | output_asm_insn ("srl\t%L1, 0, %L1", operands); |
8031 | output_asm_insn ("or\t%L1, %3, %3", operands); | |
c6b0465b | 8032 | } |
284d86e9 JC |
8033 | |
8034 | strcpy(asm_code, opcode); | |
01d3224a | 8035 | |
284d86e9 | 8036 | if (which_alternative != 2) |
4df1190a | 8037 | return strcat (asm_code, "\t%0, %2, %L0\n\tsrlx\t%L0, 32, %H0"); |
284d86e9 | 8038 | else |
4df1190a | 8039 | return strcat (asm_code, "\t%3, %2, %3\n\tsrlx\t%3, 32, %H0\n\tmov\t%3, %L0"); |
284d86e9 | 8040 | } |
2be15d0f | 8041 | \f |
89a8b315 RH |
8042 | /* Output rtl to increment the profiler label LABELNO |
8043 | for profiling a function entry. */ | |
2be15d0f RH |
8044 | |
8045 | void | |
89a8b315 | 8046 | sparc_profile_hook (labelno) |
2be15d0f RH |
8047 | int labelno; |
8048 | { | |
8049 | char buf[32]; | |
89a8b315 | 8050 | rtx lab, fun; |
2be15d0f | 8051 | |
89a8b315 RH |
8052 | ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno); |
8053 | lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); | |
8054 | fun = gen_rtx_SYMBOL_REF (Pmode, MCOUNT_FUNCTION); | |
2be15d0f | 8055 | |
eb29ddb6 | 8056 | emit_library_call (fun, LCT_NORMAL, VOIDmode, 1, lab, Pmode); |
2be15d0f | 8057 | } |
89a8b315 | 8058 | \f |
ede75ee8 | 8059 | #ifdef OBJECT_FORMAT_ELF |
7c262518 | 8060 | static void |
715bdd29 | 8061 | sparc_elf_asm_named_section (name, flags) |
7c262518 RH |
8062 | const char *name; |
8063 | unsigned int flags; | |
7c262518 | 8064 | { |
201556f0 JJ |
8065 | if (flags & SECTION_MERGE) |
8066 | { | |
8067 | /* entsize cannot be expressed in this section attributes | |
8068 | encoding style. */ | |
8069 | default_elf_asm_named_section (name, flags); | |
8070 | return; | |
8071 | } | |
8072 | ||
7c262518 RH |
8073 | fprintf (asm_out_file, "\t.section\t\"%s\"", name); |
8074 | ||
8075 | if (!(flags & SECTION_DEBUG)) | |
8076 | fputs (",#alloc", asm_out_file); | |
8077 | if (flags & SECTION_WRITE) | |
8078 | fputs (",#write", asm_out_file); | |
8079 | if (flags & SECTION_CODE) | |
8080 | fputs (",#execinstr", asm_out_file); | |
8081 | ||
8082 | /* ??? Handle SECTION_BSS. */ | |
8083 | ||
8084 | fputc ('\n', asm_out_file); | |
8085 | } | |
ede75ee8 | 8086 | #endif /* OBJECT_FORMAT_ELF */ |
f451b552 | 8087 | |
4977bab6 ZW |
8088 | /* We do not allow sibling calls if -mflat, nor |
8089 | we do not allow indirect calls to be optimized into sibling calls. | |
8090 | ||
8091 | Also, on sparc 32-bit we cannot emit a sibling call when the | |
8092 | current function returns a structure. This is because the "unimp | |
8093 | after call" convention would cause the callee to return to the | |
8094 | wrong place. The generic code already disallows cases where the | |
8095 | function being called returns a structure. | |
8096 | ||
8097 | It may seem strange how this last case could occur. Usually there | |
8098 | is code after the call which jumps to epilogue code which dumps the | |
8099 | return value into the struct return area. That ought to invalidate | |
8100 | the sibling call right? Well, in the c++ case we can end up passing | |
8101 | the pointer to the struct return area to a constructor (which returns | |
8102 | void) and then nothing else happens. Such a sibling call would look | |
8103 | valid without the added check here. */ | |
8104 | static bool | |
8105 | sparc_function_ok_for_sibcall (decl, exp) | |
8106 | tree decl; | |
8107 | tree exp ATTRIBUTE_UNUSED; | |
8108 | { | |
8109 | return (decl | |
8110 | && ! TARGET_FLAT | |
8111 | && (TARGET_ARCH64 || ! current_function_returns_struct)); | |
8112 | } | |
8113 | ||
ae46c4e0 RH |
8114 | /* ??? Similar to the standard section selection, but force reloc-y-ness |
8115 | if SUNOS4_SHARED_LIBRARIES. Unclear why this helps (as opposed to | |
8116 | pretending PIC always on), but that's what the old code did. */ | |
8117 | ||
8118 | static void | |
8119 | sparc_aout_select_section (t, reloc, align) | |
8120 | tree t; | |
8121 | int reloc; | |
8122 | unsigned HOST_WIDE_INT align; | |
8123 | { | |
508bc172 | 8124 | default_select_section (t, reloc | SUNOS4_SHARED_LIBRARIES, align); |
ae46c4e0 RH |
8125 | } |
8126 | ||
b64a1b53 RH |
8127 | /* Use text section for a constant unless we need more alignment than |
8128 | that offers. */ | |
8129 | ||
8130 | static void | |
8131 | sparc_aout_select_rtx_section (mode, x, align) | |
8132 | enum machine_mode mode; | |
8133 | rtx x; | |
8134 | unsigned HOST_WIDE_INT align; | |
8135 | { | |
8136 | if (align <= MAX_TEXT_ALIGN | |
8137 | && ! (flag_pic && (symbolic_operand (x, mode) | |
8138 | || SUNOS4_SHARED_LIBRARIES))) | |
8139 | readonly_data_section (); | |
8140 | else | |
8141 | data_section (); | |
8142 | } | |
8143 | ||
f451b552 DM |
8144 | int |
8145 | sparc_extra_constraint_check (op, c, strict) | |
8146 | rtx op; | |
eb29ddb6 | 8147 | int c; |
f451b552 DM |
8148 | int strict; |
8149 | { | |
8150 | int reload_ok_mem; | |
8151 | ||
8152 | if (TARGET_ARCH64 | |
8153 | && (c == 'T' || c == 'U')) | |
8154 | return 0; | |
8155 | ||
8156 | switch (c) | |
8157 | { | |
8158 | case 'Q': | |
8159 | return fp_sethi_p (op); | |
8160 | ||
8161 | case 'R': | |
8162 | return fp_mov_p (op); | |
8163 | ||
8164 | case 'S': | |
8165 | return fp_high_losum_p (op); | |
8166 | ||
8167 | case 'U': | |
8168 | if (! strict | |
8169 | || (GET_CODE (op) == REG | |
8170 | && (REGNO (op) < FIRST_PSEUDO_REGISTER | |
8171 | || reg_renumber[REGNO (op)] >= 0))) | |
8172 | return register_ok_for_ldd (op); | |
8173 | ||
8174 | return 0; | |
8175 | ||
8176 | case 'W': | |
8177 | case 'T': | |
8178 | break; | |
8179 | ||
8180 | default: | |
8181 | return 0; | |
8182 | } | |
8183 | ||
8184 | /* Our memory extra constraints have to emulate the | |
8185 | behavior of 'm' and 'o' in order for reload to work | |
8186 | correctly. */ | |
8187 | if (GET_CODE (op) == MEM) | |
8188 | { | |
8189 | reload_ok_mem = 0; | |
8190 | if ((TARGET_ARCH64 || mem_min_alignment (op, 8)) | |
8191 | && (! strict | |
8192 | || strict_memory_address_p (Pmode, XEXP (op, 0)))) | |
8193 | reload_ok_mem = 1; | |
8194 | } | |
8195 | else | |
8196 | { | |
8197 | reload_ok_mem = (reload_in_progress | |
8198 | && GET_CODE (op) == REG | |
8199 | && REGNO (op) >= FIRST_PSEUDO_REGISTER | |
8200 | && reg_renumber [REGNO (op)] < 0); | |
8201 | } | |
8202 | ||
8203 | return reload_ok_mem; | |
8204 | } | |
2ce04b6b | 8205 | |
214c6394 DM |
8206 | /* ??? This duplicates information provided to the compiler by the |
8207 | ??? scheduler description. Some day, teach genautomata to output | |
8208 | ??? the latencies and then CSE will just use that. */ | |
8209 | ||
3c50106f RH |
8210 | static bool |
8211 | sparc_rtx_costs (x, code, outer_code, total) | |
2ce04b6b | 8212 | rtx x; |
3c50106f | 8213 | int code, outer_code, *total; |
2ce04b6b DM |
8214 | { |
8215 | switch (code) | |
8216 | { | |
214c6394 DM |
8217 | case PLUS: case MINUS: case ABS: case NEG: |
8218 | case FLOAT: case UNSIGNED_FLOAT: | |
8219 | case FIX: case UNSIGNED_FIX: | |
8220 | case FLOAT_EXTEND: case FLOAT_TRUNCATE: | |
8221 | if (FLOAT_MODE_P (GET_MODE (x))) | |
8222 | { | |
8223 | switch (sparc_cpu) | |
8224 | { | |
8225 | case PROCESSOR_ULTRASPARC: | |
8226 | case PROCESSOR_ULTRASPARC3: | |
3c50106f RH |
8227 | *total = COSTS_N_INSNS (4); |
8228 | return true; | |
214c6394 DM |
8229 | |
8230 | case PROCESSOR_SUPERSPARC: | |
3c50106f RH |
8231 | *total = COSTS_N_INSNS (3); |
8232 | return true; | |
214c6394 DM |
8233 | |
8234 | case PROCESSOR_CYPRESS: | |
3c50106f RH |
8235 | *total = COSTS_N_INSNS (5); |
8236 | return true; | |
214c6394 DM |
8237 | |
8238 | case PROCESSOR_HYPERSPARC: | |
8239 | case PROCESSOR_SPARCLITE86X: | |
8240 | default: | |
3c50106f RH |
8241 | *total = COSTS_N_INSNS (1); |
8242 | return true; | |
214c6394 DM |
8243 | } |
8244 | } | |
8245 | ||
3c50106f RH |
8246 | *total = COSTS_N_INSNS (1); |
8247 | return true; | |
214c6394 DM |
8248 | |
8249 | case SQRT: | |
8250 | switch (sparc_cpu) | |
8251 | { | |
8252 | case PROCESSOR_ULTRASPARC: | |
8253 | if (GET_MODE (x) == SFmode) | |
3c50106f | 8254 | *total = COSTS_N_INSNS (13); |
214c6394 | 8255 | else |
3c50106f RH |
8256 | *total = COSTS_N_INSNS (23); |
8257 | return true; | |
214c6394 DM |
8258 | |
8259 | case PROCESSOR_ULTRASPARC3: | |
8260 | if (GET_MODE (x) == SFmode) | |
3c50106f | 8261 | *total = COSTS_N_INSNS (20); |
214c6394 | 8262 | else |
3c50106f RH |
8263 | *total = COSTS_N_INSNS (29); |
8264 | return true; | |
214c6394 DM |
8265 | |
8266 | case PROCESSOR_SUPERSPARC: | |
3c50106f RH |
8267 | *total = COSTS_N_INSNS (12); |
8268 | return true; | |
214c6394 DM |
8269 | |
8270 | case PROCESSOR_CYPRESS: | |
3c50106f RH |
8271 | *total = COSTS_N_INSNS (63); |
8272 | return true; | |
214c6394 DM |
8273 | |
8274 | case PROCESSOR_HYPERSPARC: | |
8275 | case PROCESSOR_SPARCLITE86X: | |
3c50106f RH |
8276 | *total = COSTS_N_INSNS (17); |
8277 | return true; | |
214c6394 DM |
8278 | |
8279 | default: | |
3c50106f RH |
8280 | *total = COSTS_N_INSNS (30); |
8281 | return true; | |
214c6394 DM |
8282 | } |
8283 | ||
8284 | case COMPARE: | |
8285 | if (FLOAT_MODE_P (GET_MODE (x))) | |
8286 | { | |
8287 | switch (sparc_cpu) | |
8288 | { | |
8289 | case PROCESSOR_ULTRASPARC: | |
8290 | case PROCESSOR_ULTRASPARC3: | |
3c50106f RH |
8291 | *total = COSTS_N_INSNS (1); |
8292 | return true; | |
214c6394 DM |
8293 | |
8294 | case PROCESSOR_SUPERSPARC: | |
3c50106f RH |
8295 | *total = COSTS_N_INSNS (3); |
8296 | return true; | |
214c6394 DM |
8297 | |
8298 | case PROCESSOR_CYPRESS: | |
3c50106f RH |
8299 | *total = COSTS_N_INSNS (5); |
8300 | return true; | |
214c6394 DM |
8301 | |
8302 | case PROCESSOR_HYPERSPARC: | |
8303 | case PROCESSOR_SPARCLITE86X: | |
8304 | default: | |
3c50106f RH |
8305 | *total = COSTS_N_INSNS (1); |
8306 | return true; | |
214c6394 DM |
8307 | } |
8308 | } | |
8309 | ||
8310 | /* ??? Maybe mark integer compares as zero cost on | |
8311 | ??? all UltraSPARC processors because the result | |
8312 | ??? can be bypassed to a branch in the same group. */ | |
8313 | ||
3c50106f RH |
8314 | *total = COSTS_N_INSNS (1); |
8315 | return true; | |
214c6394 | 8316 | |
2ce04b6b | 8317 | case MULT: |
214c6394 DM |
8318 | if (FLOAT_MODE_P (GET_MODE (x))) |
8319 | { | |
8320 | switch (sparc_cpu) | |
8321 | { | |
8322 | case PROCESSOR_ULTRASPARC: | |
8323 | case PROCESSOR_ULTRASPARC3: | |
3c50106f RH |
8324 | *total = COSTS_N_INSNS (4); |
8325 | return true; | |
214c6394 DM |
8326 | |
8327 | case PROCESSOR_SUPERSPARC: | |
3c50106f RH |
8328 | *total = COSTS_N_INSNS (3); |
8329 | return true; | |
214c6394 DM |
8330 | |
8331 | case PROCESSOR_CYPRESS: | |
3c50106f RH |
8332 | *total = COSTS_N_INSNS (7); |
8333 | return true; | |
214c6394 DM |
8334 | |
8335 | case PROCESSOR_HYPERSPARC: | |
8336 | case PROCESSOR_SPARCLITE86X: | |
3c50106f RH |
8337 | *total = COSTS_N_INSNS (1); |
8338 | return true; | |
214c6394 DM |
8339 | |
8340 | default: | |
3c50106f RH |
8341 | *total = COSTS_N_INSNS (5); |
8342 | return true; | |
214c6394 DM |
8343 | } |
8344 | } | |
8345 | ||
8346 | /* The latency is actually variable for Ultra-I/II | |
8347 | And if one of the inputs have a known constant | |
8348 | value, we could calculate this precisely. | |
8349 | ||
8350 | However, for that to be useful we would need to | |
8351 | add some machine description changes which would | |
8352 | make sure small constants ended up in rs1 of the | |
8353 | multiply instruction. This is because the multiply | |
8354 | latency is determined by the number of clear (or | |
8355 | set if the value is negative) bits starting from | |
8356 | the most significant bit of the first input. | |
8357 | ||
8358 | The algorithm for computing num_cycles of a multiply | |
8359 | on Ultra-I/II is: | |
8360 | ||
8361 | if (rs1 < 0) | |
8362 | highest_bit = highest_clear_bit(rs1); | |
8363 | else | |
8364 | highest_bit = highest_set_bit(rs1); | |
8365 | if (num_bits < 3) | |
8366 | highest_bit = 3; | |
8367 | num_cycles = 4 + ((highest_bit - 3) / 2); | |
8368 | ||
8369 | If we did that we would have to also consider register | |
8370 | allocation issues that would result from forcing such | |
8371 | a value into a register. | |
8372 | ||
8373 | There are other similar tricks we could play if we | |
8374 | knew, for example, that one input was an array index. | |
8375 | ||
8376 | Since we do not play any such tricks currently the | |
8377 | safest thing to do is report the worst case latency. */ | |
2ce04b6b | 8378 | if (sparc_cpu == PROCESSOR_ULTRASPARC) |
3c50106f RH |
8379 | { |
8380 | *total = (GET_MODE (x) == DImode | |
8381 | ? COSTS_N_INSNS (34) : COSTS_N_INSNS (19)); | |
8382 | return true; | |
8383 | } | |
2ce04b6b | 8384 | |
214c6394 | 8385 | /* Multiply latency on Ultra-III, fortunately, is constant. */ |
2ce04b6b | 8386 | if (sparc_cpu == PROCESSOR_ULTRASPARC3) |
3c50106f RH |
8387 | { |
8388 | *total = COSTS_N_INSNS (6); | |
8389 | return true; | |
8390 | } | |
2ce04b6b | 8391 | |
214c6394 DM |
8392 | if (sparc_cpu == PROCESSOR_HYPERSPARC |
8393 | || sparc_cpu == PROCESSOR_SPARCLITE86X) | |
3c50106f RH |
8394 | { |
8395 | *total = COSTS_N_INSNS (17); | |
8396 | return true; | |
8397 | } | |
214c6394 | 8398 | |
3c50106f RH |
8399 | *total = (TARGET_HARD_MUL ? COSTS_N_INSNS (5) : COSTS_N_INSNS (25)); |
8400 | return true; | |
2ce04b6b DM |
8401 | |
8402 | case DIV: | |
8403 | case UDIV: | |
8404 | case MOD: | |
8405 | case UMOD: | |
214c6394 DM |
8406 | if (FLOAT_MODE_P (GET_MODE (x))) |
8407 | { | |
8408 | switch (sparc_cpu) | |
8409 | { | |
8410 | case PROCESSOR_ULTRASPARC: | |
8411 | if (GET_MODE (x) == SFmode) | |
3c50106f | 8412 | *total = COSTS_N_INSNS (13); |
214c6394 | 8413 | else |
3c50106f RH |
8414 | *total = COSTS_N_INSNS (23); |
8415 | return true; | |
214c6394 DM |
8416 | |
8417 | case PROCESSOR_ULTRASPARC3: | |
8418 | if (GET_MODE (x) == SFmode) | |
3c50106f | 8419 | *total = COSTS_N_INSNS (17); |
214c6394 | 8420 | else |
3c50106f RH |
8421 | *total = COSTS_N_INSNS (20); |
8422 | return true; | |
214c6394 DM |
8423 | |
8424 | case PROCESSOR_SUPERSPARC: | |
8425 | if (GET_MODE (x) == SFmode) | |
3c50106f | 8426 | *total = COSTS_N_INSNS (6); |
214c6394 | 8427 | else |
3c50106f RH |
8428 | *total = COSTS_N_INSNS (9); |
8429 | return true; | |
214c6394 DM |
8430 | |
8431 | case PROCESSOR_HYPERSPARC: | |
8432 | case PROCESSOR_SPARCLITE86X: | |
8433 | if (GET_MODE (x) == SFmode) | |
3c50106f | 8434 | *total = COSTS_N_INSNS (8); |
214c6394 | 8435 | else |
3c50106f RH |
8436 | *total = COSTS_N_INSNS (12); |
8437 | return true; | |
214c6394 DM |
8438 | |
8439 | default: | |
3c50106f RH |
8440 | *total = COSTS_N_INSNS (7); |
8441 | return true; | |
214c6394 DM |
8442 | } |
8443 | } | |
8444 | ||
2ce04b6b | 8445 | if (sparc_cpu == PROCESSOR_ULTRASPARC) |
3c50106f RH |
8446 | *total = (GET_MODE (x) == DImode |
8447 | ? COSTS_N_INSNS (68) : COSTS_N_INSNS (37)); | |
8448 | else if (sparc_cpu == PROCESSOR_ULTRASPARC3) | |
8449 | *total = (GET_MODE (x) == DImode | |
8450 | ? COSTS_N_INSNS (71) : COSTS_N_INSNS (40)); | |
8451 | else | |
8452 | *total = COSTS_N_INSNS (25); | |
8453 | return true; | |
2ce04b6b | 8454 | |
214c6394 DM |
8455 | case IF_THEN_ELSE: |
8456 | /* Conditional moves. */ | |
8457 | switch (sparc_cpu) | |
8458 | { | |
8459 | case PROCESSOR_ULTRASPARC: | |
3c50106f RH |
8460 | *total = COSTS_N_INSNS (2); |
8461 | return true; | |
214c6394 DM |
8462 | |
8463 | case PROCESSOR_ULTRASPARC3: | |
8464 | if (FLOAT_MODE_P (GET_MODE (x))) | |
3c50106f | 8465 | *total = COSTS_N_INSNS (3); |
214c6394 | 8466 | else |
3c50106f RH |
8467 | *total = COSTS_N_INSNS (2); |
8468 | return true; | |
214c6394 DM |
8469 | |
8470 | default: | |
3c50106f RH |
8471 | *total = COSTS_N_INSNS (1); |
8472 | return true; | |
214c6394 DM |
8473 | } |
8474 | ||
8475 | case MEM: | |
8476 | /* If outer-code is SIGN/ZERO extension we have to subtract | |
8477 | out COSTS_N_INSNS (1) from whatever we return in determining | |
8478 | the cost. */ | |
8479 | switch (sparc_cpu) | |
8480 | { | |
8481 | case PROCESSOR_ULTRASPARC: | |
8482 | if (outer_code == ZERO_EXTEND) | |
3c50106f | 8483 | *total = COSTS_N_INSNS (1); |
214c6394 | 8484 | else |
3c50106f RH |
8485 | *total = COSTS_N_INSNS (2); |
8486 | return true; | |
214c6394 DM |
8487 | |
8488 | case PROCESSOR_ULTRASPARC3: | |
8489 | if (outer_code == ZERO_EXTEND) | |
8490 | { | |
8491 | if (GET_MODE (x) == QImode | |
8492 | || GET_MODE (x) == HImode | |
8493 | || outer_code == SIGN_EXTEND) | |
3c50106f | 8494 | *total = COSTS_N_INSNS (2); |
214c6394 | 8495 | else |
3c50106f | 8496 | *total = COSTS_N_INSNS (1); |
214c6394 DM |
8497 | } |
8498 | else | |
8499 | { | |
8500 | /* This handles sign extension (3 cycles) | |
8501 | and everything else (2 cycles). */ | |
3c50106f | 8502 | *total = COSTS_N_INSNS (2); |
214c6394 | 8503 | } |
3c50106f | 8504 | return true; |
214c6394 DM |
8505 | |
8506 | case PROCESSOR_SUPERSPARC: | |
8507 | if (FLOAT_MODE_P (GET_MODE (x)) | |
8508 | || outer_code == ZERO_EXTEND | |
8509 | || outer_code == SIGN_EXTEND) | |
3c50106f | 8510 | *total = COSTS_N_INSNS (0); |
214c6394 | 8511 | else |
3c50106f RH |
8512 | *total = COSTS_N_INSNS (1); |
8513 | return true; | |
214c6394 DM |
8514 | |
8515 | case PROCESSOR_TSC701: | |
8516 | if (outer_code == ZERO_EXTEND | |
8517 | || outer_code == SIGN_EXTEND) | |
3c50106f | 8518 | *total = COSTS_N_INSNS (2); |
214c6394 | 8519 | else |
3c50106f RH |
8520 | *total = COSTS_N_INSNS (3); |
8521 | return true; | |
214c6394 DM |
8522 | |
8523 | case PROCESSOR_CYPRESS: | |
8524 | if (outer_code == ZERO_EXTEND | |
8525 | || outer_code == SIGN_EXTEND) | |
3c50106f | 8526 | *total = COSTS_N_INSNS (1); |
214c6394 | 8527 | else |
3c50106f RH |
8528 | *total = COSTS_N_INSNS (2); |
8529 | return true; | |
214c6394 DM |
8530 | |
8531 | case PROCESSOR_HYPERSPARC: | |
8532 | case PROCESSOR_SPARCLITE86X: | |
8533 | default: | |
8534 | if (outer_code == ZERO_EXTEND | |
8535 | || outer_code == SIGN_EXTEND) | |
3c50106f | 8536 | *total = COSTS_N_INSNS (0); |
214c6394 | 8537 | else |
3c50106f RH |
8538 | *total = COSTS_N_INSNS (1); |
8539 | return true; | |
214c6394 | 8540 | } |
2ce04b6b DM |
8541 | |
8542 | case CONST_INT: | |
8543 | if (INTVAL (x) < 0x1000 && INTVAL (x) >= -0x1000) | |
3c50106f RH |
8544 | { |
8545 | *total = 0; | |
8546 | return true; | |
8547 | } | |
8548 | /* FALLTHRU */ | |
2ce04b6b | 8549 | |
2ce04b6b | 8550 | case HIGH: |
3c50106f RH |
8551 | *total = 2; |
8552 | return true; | |
2ce04b6b DM |
8553 | |
8554 | case CONST: | |
8555 | case LABEL_REF: | |
8556 | case SYMBOL_REF: | |
3c50106f RH |
8557 | *total = 4; |
8558 | return true; | |
2ce04b6b DM |
8559 | |
8560 | case CONST_DOUBLE: | |
3c50106f RH |
8561 | if (GET_MODE (x) == DImode |
8562 | && ((XINT (x, 3) == 0 | |
8563 | && (unsigned HOST_WIDE_INT) XINT (x, 2) < 0x1000) | |
8564 | || (XINT (x, 3) == -1 | |
8565 | && XINT (x, 2) < 0 | |
8566 | && XINT (x, 2) >= -0x1000))) | |
8567 | *total = 0; | |
8568 | else | |
8569 | *total = 8; | |
8570 | return true; | |
2ce04b6b DM |
8571 | |
8572 | default: | |
3c50106f RH |
8573 | return false; |
8574 | } | |
2ce04b6b | 8575 | } |
fb49053f | 8576 | |
e133041b RH |
8577 | /* Output code to add DELTA to the first argument, and then jump to FUNCTION. |
8578 | Used for C++ multiple inheritance. */ | |
8579 | ||
c590b625 | 8580 | static void |
3961e8fe | 8581 | sparc_output_mi_thunk (file, thunk_fndecl, delta, vcall_offset, function) |
e133041b RH |
8582 | FILE *file; |
8583 | tree thunk_fndecl ATTRIBUTE_UNUSED; | |
8584 | HOST_WIDE_INT delta; | |
3961e8fe | 8585 | HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED; |
e133041b RH |
8586 | tree function; |
8587 | { | |
8588 | rtx this, insn, funexp, delta_rtx, tmp; | |
8589 | ||
8590 | reload_completed = 1; | |
8591 | no_new_pseudos = 1; | |
8592 | current_function_uses_only_leaf_regs = 1; | |
8593 | ||
8594 | emit_note (NULL, NOTE_INSN_PROLOGUE_END); | |
8595 | ||
8596 | /* Find the "this" pointer. Normally in %o0, but in ARCH64 if the function | |
8597 | returns a structure, the structure return pointer is there instead. */ | |
8598 | if (TARGET_ARCH64 && aggregate_value_p (TREE_TYPE (TREE_TYPE (function)))) | |
8599 | this = gen_rtx_REG (Pmode, SPARC_INCOMING_INT_ARG_FIRST + 1); | |
8600 | else | |
8601 | this = gen_rtx_REG (Pmode, SPARC_INCOMING_INT_ARG_FIRST); | |
8602 | ||
8603 | /* Add DELTA. When possible use a plain add, otherwise load it into | |
8604 | a register first. */ | |
8605 | delta_rtx = GEN_INT (delta); | |
8606 | if (!SPARC_SIMM13_P (delta)) | |
8607 | { | |
8608 | rtx scratch = gen_rtx_REG (Pmode, 1); | |
8609 | if (TARGET_ARCH64) | |
8610 | sparc_emit_set_const64 (scratch, delta_rtx); | |
8611 | else | |
8612 | sparc_emit_set_const32 (scratch, delta_rtx); | |
8613 | delta_rtx = scratch; | |
8614 | } | |
8615 | ||
8616 | tmp = gen_rtx_PLUS (Pmode, this, delta_rtx); | |
8617 | emit_insn (gen_rtx_SET (VOIDmode, this, tmp)); | |
8618 | ||
8619 | /* Generate a tail call to the target function. */ | |
8620 | if (! TREE_USED (function)) | |
8621 | { | |
8622 | assemble_external (function); | |
8623 | TREE_USED (function) = 1; | |
8624 | } | |
8625 | funexp = XEXP (DECL_RTL (function), 0); | |
8626 | funexp = gen_rtx_MEM (FUNCTION_MODE, funexp); | |
8627 | insn = emit_call_insn (gen_sibcall (funexp)); | |
8628 | SIBLING_CALL_P (insn) = 1; | |
8629 | emit_barrier (); | |
8630 | ||
8631 | /* Run just enough of rest_of_compilation to get the insns emitted. | |
8632 | There's not really enough bulk here to make other passes such as | |
8633 | instruction scheduling worth while. Note that use_thunk calls | |
8634 | assemble_start_function and assemble_end_function. */ | |
8635 | insn = get_insns (); | |
a2855205 | 8636 | insn_locators_initialize (); |
e133041b RH |
8637 | shorten_branches (insn); |
8638 | final_start_function (insn, file, 1); | |
8639 | final (insn, file, 1, 0); | |
8640 | final_end_function (); | |
8641 | ||
8642 | reload_completed = 0; | |
8643 | no_new_pseudos = 0; | |
8644 | } | |
e2500fed GK |
8645 | |
8646 | #include "gt-sparc.h" |