]>
Commit | Line | Data |
---|---|---|
8b109b37 RK |
1 | /* Definitions of target machine for GNU compiler for Hitachi Super-H. |
2 | Copyright (C) 1993, 1994, 1995 Free Software Foundation, Inc. | |
058f9bb5 JW |
3 | Contributed by Steve Chamberlain (sac@cygnus.com). |
4 | Improved by Jim Wilson (wilson@cygnus.com). | |
bc45ade3 SC |
5 | |
6 | This file is part of GNU CC. | |
7 | ||
8 | GNU CC is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 2, or (at your option) | |
11 | any later version. | |
12 | ||
13 | GNU CC is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with GNU CC; see the file COPYING. If not, write to | |
20 | the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ | |
21 | ||
8b109b37 | 22 | |
c5d67833 | 23 | #define TARGET_VERSION \ |
bc45ade3 SC |
24 | fputs (" (Hitachi SH)", stderr); |
25 | ||
26 | /* Generate SDB debugging information. */ | |
27 | ||
c5d67833 | 28 | #define SDB_DEBUGGING_INFO |
bc45ade3 | 29 | |
60033bb7 DE |
30 | /* Output DBX (stabs) debugging information if doing -gstabs. */ |
31 | ||
32 | #define DBX_DEBUGGING_INFO | |
33 | ||
994295f2 | 34 | /* Generate SDB debugging information by default. */ |
60033bb7 DE |
35 | |
36 | #define PREFERRED_DEBUGGING_TYPE SDB_DEBUG | |
37 | ||
bc45ade3 SC |
38 | #define SDB_DELIM ";" |
39 | ||
00f8ff66 SC |
40 | #define CPP_SPEC "%{ml:-D__LITTLE_ENDIAN__}" |
41 | ||
65c42379 | 42 | #define CPP_PREDEFINES "-D__sh__ -Acpu(sh) -Amachine(sh)" |
bc45ade3 | 43 | |
00f8ff66 SC |
44 | #define ASM_SPEC "%{ml:-little}" |
45 | ||
46 | #define LINK_SPEC "%{ml:-m shl}" | |
47 | ||
4f074454 RK |
48 | /* Show we can debug even without a frame pointer. */ |
49 | #define CAN_DEBUG_WITHOUT_FP | |
0d7e008e | 50 | |
0d7e008e | 51 | #define CONDITIONAL_REGISTER_USAGE \ |
994295f2 | 52 | /* Hitachi saves and restores mac registers on call. */ \ |
0d7e008e SC |
53 | if (TARGET_HITACHI) \ |
54 | { \ | |
55 | call_used_regs[MACH_REG] = 0; \ | |
56 | call_used_regs[MACL_REG] = 0; \ | |
994295f2 | 57 | } |
bc45ade3 | 58 | \f |
994295f2 | 59 | /* Run-time compilation parameters selecting different hardware subsets. */ |
bc45ade3 SC |
60 | |
61 | extern int target_flags; | |
0d7e008e | 62 | #define ISIZE_BIT (1<<1) |
0d7e008e SC |
63 | #define DALIGN_BIT (1<<6) |
64 | #define SH0_BIT (1<<7) | |
65 | #define SH1_BIT (1<<8) | |
66 | #define SH2_BIT (1<<9) | |
67 | #define SH3_BIT (1<<10) | |
0d7e008e SC |
68 | #define SPACE_BIT (1<<13) |
69 | #define BIGTABLE_BIT (1<<14) | |
0d7e008e | 70 | #define HITACHI_BIT (1<<22) |
9791111f | 71 | #define PADSTRUCT_BIT (1<<28) |
00f8ff66 | 72 | #define LITTLE_ENDIAN_BIT (1<<29) |
b9654711 | 73 | |
c5d67833 JW |
74 | /* Nonzero if we should dump out instruction size info. */ |
75 | #define TARGET_DUMPISIZE (target_flags & ISIZE_BIT) | |
76 | ||
77 | /* Nonzero to align doubles on 64 bit boundaries. */ | |
78 | #define TARGET_ALIGN_DOUBLE (target_flags & DALIGN_BIT) | |
79 | ||
994295f2 | 80 | /* Nonzero if we should generate code using type 0 insns. */ |
c5d67833 JW |
81 | /* ??? Is there such a thing as SH0? If not, we should delete all |
82 | references to it. */ | |
b9654711 SC |
83 | #define TARGET_SH0 (target_flags & SH0_BIT) |
84 | ||
994295f2 | 85 | /* Nonzero if we should generate code using type 1 insns. */ |
b9654711 SC |
86 | #define TARGET_SH1 (target_flags & SH1_BIT) |
87 | ||
994295f2 | 88 | /* Nonzero if we should generate code using type 2 insns. */ |
b9654711 | 89 | #define TARGET_SH2 (target_flags & SH2_BIT) |
bc45ade3 | 90 | |
994295f2 | 91 | /* Nonzero if we should generate code using type 3 insns. */ |
b9654711 | 92 | #define TARGET_SH3 (target_flags & SH3_BIT) |
bc45ade3 | 93 | |
994295f2 | 94 | /* Nonzero if we should generate smaller code rather than faster code. */ |
b9654711 SC |
95 | #define TARGET_SMALLCODE (target_flags & SPACE_BIT) |
96 | ||
994295f2 | 97 | /* Nonzero to use long jump tables. */ |
0d7e008e | 98 | #define TARGET_BIGTABLE (target_flags & BIGTABLE_BIT) |
b9654711 | 99 | |
994295f2 | 100 | /* Nonzero if using Hitachi's calling convention. */ |
d3ae8277 | 101 | #define TARGET_HITACHI (target_flags & HITACHI_BIT) |
8e87e161 | 102 | |
9791111f JW |
103 | /* Nonzero if padding structures to a multiple of 4 bytes. This is |
104 | incompatible with Hitachi's compiler, and gives unusual structure layouts | |
105 | which confuse programmers. | |
106 | ??? This option is not useful, but is retained in case there are people | |
107 | who are still relying on it. It may be deleted in the future. */ | |
108 | #define TARGET_PADSTRUCT (target_flags & PADSTRUCT_BIT) | |
00f8ff66 | 109 | |
c5d67833 | 110 | /* Nonzero if generating code for a little endian SH. */ |
00f8ff66 SC |
111 | #define TARGET_LITTLE_ENDIAN (target_flags & LITTLE_ENDIAN_BIT) |
112 | ||
113 | #define TARGET_SWITCHES \ | |
c5d67833 JW |
114 | { {"0", SH0_BIT}, \ |
115 | {"1", SH1_BIT}, \ | |
116 | {"2", SH2_BIT}, \ | |
117 | {"3", SH3_BIT|SH2_BIT}, \ | |
118 | {"3l", SH3_BIT|SH2_BIT|LITTLE_ENDIAN_BIT}, \ | |
119 | {"b", -LITTLE_ENDIAN_BIT}, \ | |
120 | {"bigtable", BIGTABLE_BIT}, \ | |
121 | {"dalign", DALIGN_BIT}, \ | |
122 | {"hitachi", HITACHI_BIT}, \ | |
123 | {"isize", ISIZE_BIT}, \ | |
124 | {"l", LITTLE_ENDIAN_BIT}, \ | |
125 | {"padstruct", PADSTRUCT_BIT}, \ | |
126 | {"space", SPACE_BIT}, \ | |
00f8ff66 | 127 | {"", TARGET_DEFAULT} \ |
bc45ade3 SC |
128 | } |
129 | ||
058f9bb5 | 130 | #define TARGET_DEFAULT (0) |
00f8ff66 | 131 | |
0d7e008e SC |
132 | #define OVERRIDE_OPTIONS \ |
133 | do { \ | |
134 | sh_cpu = CPU_SH0; \ | |
135 | if (TARGET_SH1) \ | |
136 | sh_cpu = CPU_SH1; \ | |
137 | if (TARGET_SH2) \ | |
138 | sh_cpu = CPU_SH2; \ | |
7c596205 JW |
139 | if (TARGET_SH3) \ |
140 | sh_cpu = CPU_SH3; \ | |
0d7e008e | 141 | \ |
c5d67833 JW |
142 | /* We *MUST* always define optimize since we *HAVE* to run \ |
143 | shorten branches to get correct code. */ \ | |
144 | /* ??? This is obsolete, since now shorten branches is no \ | |
145 | longer required by the SH, and is always run once even \ | |
146 | when not optimizing. Changing this now might be \ | |
147 | confusing though. */ \ | |
148 | optimize = 1; \ | |
0d7e008e | 149 | flag_delayed_branch = 1; \ |
c5d67833 JW |
150 | \ |
151 | /* But never run scheduling before reload, since that can \ | |
152 | break global alloc, and generates slower code anyway due \ | |
153 | to the pressure on R0. */ \ | |
154 | flag_schedule_insns = 0; \ | |
0d7e008e | 155 | } while (0) |
bc45ade3 | 156 | \f |
c5d67833 | 157 | /* Target machine storage layout. */ |
bc45ade3 | 158 | |
b9654711 | 159 | /* Define to use software floating point emulator for REAL_ARITHMETIC and |
994295f2 | 160 | decimal <-> binary conversion. */ |
b9654711 SC |
161 | #define REAL_ARITHMETIC |
162 | ||
bc45ade3 SC |
163 | /* Define this if most significant bit is lowest numbered |
164 | in instructions that operate on numbered bit-fields. */ | |
00f8ff66 | 165 | |
bc45ade3 SC |
166 | #define BITS_BIG_ENDIAN 0 |
167 | ||
168 | /* Define this if most significant byte of a word is the lowest numbered. */ | |
00f8ff66 | 169 | #define BYTES_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0) |
bc45ade3 SC |
170 | |
171 | /* Define this if most significant word of a multiword number is the lowest | |
172 | numbered. */ | |
00f8ff66 SC |
173 | #define WORDS_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0) |
174 | ||
00f8ff66 SC |
175 | /* Define this to set the endianness to use in libgcc2.c, which can |
176 | not depend on target_flags. */ | |
177 | #if defined(__LITTLE_ENDIAN__) | |
178 | #define LIBGCC2_WORDS_BIG_ENDIAN 0 | |
179 | #else | |
180 | #define LIBGCC2_WORDS_BIG_ENDIAN 1 | |
181 | #endif | |
bc45ade3 | 182 | |
994295f2 | 183 | /* Number of bits in an addressable storage unit. */ |
bc45ade3 SC |
184 | #define BITS_PER_UNIT 8 |
185 | ||
186 | /* Width in bits of a "word", which is the contents of a machine register. | |
187 | Note that this is not necessarily the width of data type `int'; | |
188 | if using 16-bit ints on a 68000, this would still be 32. | |
189 | But on a machine with 16-bit registers, this would be 16. */ | |
190 | #define BITS_PER_WORD 32 | |
191 | #define MAX_BITS_PER_WORD 32 | |
192 | ||
193 | /* Width of a word, in units (bytes). */ | |
194 | #define UNITS_PER_WORD 4 | |
195 | ||
196 | /* Width in bits of a pointer. | |
197 | See also the macro `Pmode' defined below. */ | |
198 | #define POINTER_SIZE 32 | |
199 | ||
200 | /* Allocation boundary (in *bits*) for storing arguments in argument list. */ | |
201 | #define PARM_BOUNDARY 32 | |
202 | ||
203 | /* Boundary (in *bits*) on which stack pointer should be aligned. */ | |
204 | #define STACK_BOUNDARY 32 | |
205 | ||
97b65a3e JW |
206 | /* Allocation boundary (in *bits*) for the code of a function. |
207 | 32 bit alignment is faster, because instructions are always fetched as a | |
208 | pair from a longword boundary. */ | |
209 | #define FUNCTION_BOUNDARY (TARGET_SMALLCODE ? 16 : 32) | |
bc45ade3 SC |
210 | |
211 | /* Alignment of field after `int : 0' in a structure. */ | |
212 | #define EMPTY_FIELD_BOUNDARY 32 | |
213 | ||
214 | /* No data type wants to be aligned rounder than this. */ | |
215 | #define BIGGEST_ALIGNMENT (TARGET_ALIGN_DOUBLE ? 64 : 32) | |
216 | ||
217 | /* The best alignment to use in cases where we have a choice. */ | |
218 | #define FASTEST_ALIGNMENT 32 | |
219 | ||
bc45ade3 | 220 | /* Make strings word-aligned so strcpy from constants will be faster. */ |
c5d67833 | 221 | #define CONSTANT_ALIGNMENT(EXP, ALIGN) \ |
bc45ade3 SC |
222 | ((TREE_CODE (EXP) == STRING_CST \ |
223 | && (ALIGN) < FASTEST_ALIGNMENT) \ | |
0d7e008e | 224 | ? FASTEST_ALIGNMENT : (ALIGN)) |
bc45ade3 SC |
225 | |
226 | /* Make arrays of chars word-aligned for the same reasons. */ | |
227 | #define DATA_ALIGNMENT(TYPE, ALIGN) \ | |
228 | (TREE_CODE (TYPE) == ARRAY_TYPE \ | |
229 | && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \ | |
230 | && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN)) | |
231 | ||
8e87e161 SC |
232 | /* Number of bits which any structure or union's size must be a |
233 | multiple of. Each structure or union's size is rounded up to a | |
994295f2 | 234 | multiple of this. */ |
9791111f | 235 | #define STRUCTURE_SIZE_BOUNDARY (TARGET_PADSTRUCT ? 32 : 8) |
8e87e161 | 236 | |
bc45ade3 SC |
237 | /* Set this nonzero if move instructions will actually fail to work |
238 | when given unaligned data. */ | |
239 | #define STRICT_ALIGNMENT 1 | |
bc45ade3 SC |
240 | \f |
241 | /* Standard register usage. */ | |
242 | ||
0d7e008e | 243 | /* Register allocation for the Hitachi calling convention: |
bc45ade3 | 244 | |
0d7e008e SC |
245 | r0 arg return |
246 | r1..r3 scratch | |
c5d67833 | 247 | r4..r7 args in |
0d7e008e SC |
248 | r8..r13 call saved |
249 | r14 frame pointer/call saved | |
bc45ade3 SC |
250 | r15 stack pointer |
251 | ap arg pointer (doesn't really exist, always eliminated) | |
252 | pr subroutine return address | |
253 | t t bit | |
994295f2 JW |
254 | mach multiply/accumulate result, high part |
255 | macl multiply/accumulate result, low part. */ | |
bc45ade3 SC |
256 | |
257 | /* Number of actual hardware registers. | |
258 | The hardware registers are assigned numbers for the compiler | |
259 | from 0 to just below FIRST_PSEUDO_REGISTER. | |
260 | All registers that the compiler knows about must be given numbers, | |
994295f2 | 261 | even those that are not normally considered general registers. */ |
bc45ade3 | 262 | |
994295f2 | 263 | #define AP_REG 16 |
bc45ade3 SC |
264 | #define PR_REG 17 |
265 | #define T_REG 18 | |
266 | #define GBR_REG 19 | |
267 | #define MACH_REG 20 | |
268 | #define MACL_REG 21 | |
058f9bb5 | 269 | #define SPECIAL_REG(REGNO) ((REGNO) >= 18 && (REGNO) <= 21) |
bc45ade3 | 270 | |
0d7e008e | 271 | #define FIRST_PSEUDO_REGISTER 22 |
bc45ade3 SC |
272 | |
273 | /* 1 for registers that have pervasive standard uses | |
994295f2 | 274 | and are not available for the register allocator. |
d3ae8277 | 275 | |
97b65a3e JW |
276 | Mach register is fixed 'cause it's only 10 bits wide for SH1. |
277 | It is 32 bits wide for SH2. */ | |
d3ae8277 | 278 | |
0d7e008e SC |
279 | #define FIXED_REGISTERS \ |
280 | { 0, 0, 0, 0, \ | |
281 | 0, 0, 0, 0, \ | |
282 | 0, 0, 0, 0, \ | |
283 | 0, 0, 0, 1, \ | |
284 | 1, 1, 1, 1, \ | |
285 | 1, 1} | |
bc45ade3 SC |
286 | |
287 | /* 1 for registers not available across function calls. | |
288 | These must include the FIXED_REGISTERS and also any | |
289 | registers that can be used without being saved. | |
290 | The latter must include the registers where values are returned | |
291 | and the register where structure-value addresses are passed. | |
292 | Aside from that, you can include as many other registers as you like. */ | |
293 | ||
0d7e008e SC |
294 | #define CALL_USED_REGISTERS \ |
295 | { 1, 1, 1, 1, \ | |
296 | 1, 1, 1, 1, \ | |
297 | 0, 0, 0, 0, \ | |
298 | 0, 0, 0, 1, \ | |
299 | 1, 0, 1, 1, \ | |
994295f2 | 300 | 1, 1} |
bc45ade3 SC |
301 | |
302 | /* Return number of consecutive hard regs needed starting at reg REGNO | |
303 | to hold something of mode MODE. | |
304 | This is ordinarily the length in words of a value of mode MODE | |
305 | but can be less for certain modes in special long registers. | |
306 | ||
994295f2 | 307 | On the SH regs are UNITS_PER_WORD bits wide. */ |
0d7e008e | 308 | |
c5d67833 | 309 | #define HARD_REGNO_NREGS(REGNO, MODE) \ |
bc45ade3 SC |
310 | (((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) |
311 | ||
312 | /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. | |
058f9bb5 JW |
313 | We can allow any mode in any general register. The special registers |
314 | only allow SImode. Don't allow any mode in the PR. */ | |
bc45ade3 | 315 | |
c5d67833 | 316 | #define HARD_REGNO_MODE_OK(REGNO, MODE) \ |
058f9bb5 JW |
317 | (SPECIAL_REG (REGNO) ? (MODE) == SImode \ |
318 | : (REGNO) == PR_REG ? 0 \ | |
319 | : 1) | |
bc45ade3 SC |
320 | |
321 | /* Value is 1 if it is a good idea to tie two pseudo registers | |
322 | when one has mode MODE1 and one has mode MODE2. | |
323 | If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, | |
324 | for any hard reg, then this must be 0 for correct output. */ | |
325 | ||
326 | #define MODES_TIEABLE_P(MODE1, MODE2) \ | |
327 | ((MODE1) == (MODE2) || GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2)) | |
328 | ||
329 | /* Specify the registers used for certain standard purposes. | |
330 | The values of these macros are register numbers. */ | |
331 | ||
332 | /* Define this if the program counter is overloaded on a register. */ | |
333 | /* #define PC_REGNUM 15*/ | |
334 | ||
335 | /* Register to use for pushing function arguments. */ | |
336 | #define STACK_POINTER_REGNUM 15 | |
337 | ||
338 | /* Base register for access to local variables of the function. */ | |
339 | #define FRAME_POINTER_REGNUM 14 | |
340 | ||
341 | /* Value should be nonzero if functions must have frame pointers. | |
342 | Zero means the frame pointer need not be set up (and parms may be accessed | |
343 | via the stack pointer) in functions that seem suitable. */ | |
b9654711 | 344 | |
0d7e008e | 345 | #define FRAME_POINTER_REQUIRED 0 |
bc45ade3 SC |
346 | |
347 | /* Definitions for register eliminations. | |
348 | ||
97b65a3e | 349 | We have two registers that can be eliminated on the SH. First, the |
bc45ade3 SC |
350 | frame pointer register can often be eliminated in favor of the stack |
351 | pointer register. Secondly, the argument pointer register can always be | |
352 | eliminated; it is replaced with either the stack or frame pointer. */ | |
353 | ||
354 | /* This is an array of structures. Each structure initializes one pair | |
355 | of eliminable registers. The "from" register number is given first, | |
356 | followed by "to". Eliminations of the same "from" register are listed | |
357 | in order of preference. */ | |
358 | ||
359 | #define ELIMINABLE_REGS \ | |
360 | {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
361 | { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
362 | { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM},} | |
363 | ||
364 | /* Given FROM and TO register numbers, say whether this elimination | |
365 | is allowed. */ | |
366 | #define CAN_ELIMINATE(FROM, TO) \ | |
367 | (!((FROM) == FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)) | |
368 | ||
369 | /* Define the offset between two registers, one to be eliminated, and the other | |
370 | its replacement, at the start of a routine. */ | |
371 | ||
372 | #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ | |
373 | OFFSET = initial_elimination_offset (FROM, TO) | |
374 | ||
375 | /* Base register for access to arguments of the function. */ | |
376 | #define ARG_POINTER_REGNUM 16 | |
377 | ||
378 | /* Register in which the static-chain is passed to a function. */ | |
379 | #define STATIC_CHAIN_REGNUM 13 | |
380 | ||
994295f2 | 381 | /* The register in which a struct value address is passed. */ |
b9654711 | 382 | |
0d7e008e SC |
383 | #define STRUCT_VALUE_REGNUM 2 |
384 | ||
385 | /* If the structure value address is not passed in a register, define | |
386 | `STRUCT_VALUE' as an expression returning an RTX for the place | |
387 | where the address is passed. If it returns 0, the address is | |
388 | passed as an "invisible" first argument. */ | |
389 | ||
390 | /*#define STRUCT_VALUE ((rtx)0)*/ | |
bc45ade3 | 391 | |
0d7e008e SC |
392 | /* Don't default to pcc-struct-return, because we have already specified |
393 | exactly how to return structures in the RETURN_IN_MEMORY macro. */ | |
394 | ||
395 | #define DEFAULT_PCC_STRUCT_RETURN 0 | |
bc45ade3 SC |
396 | \f |
397 | /* Define the classes of registers for register constraints in the | |
398 | machine description. Also define ranges of constants. | |
399 | ||
400 | One of the classes must always be named ALL_REGS and include all hard regs. | |
401 | If there is more than one class, another class must be named NO_REGS | |
402 | and contain no registers. | |
403 | ||
404 | The name GENERAL_REGS must be the name of a class (or an alias for | |
405 | another name such as ALL_REGS). This is the class of registers | |
406 | that is allowed by "g" or "r" in a register constraint. | |
407 | Also, registers outside this class are allocated only when | |
408 | instructions express preferences for them. | |
409 | ||
410 | The classes must be numbered in nondecreasing order; that is, | |
411 | a larger-numbered class must never be contained completely | |
412 | in a smaller-numbered class. | |
413 | ||
414 | For any two classes, it is very desirable that there be another | |
415 | class that represents their union. */ | |
416 | ||
994295f2 | 417 | /* The SH has two sorts of general registers, R0 and the rest. R0 can |
bc45ade3 SC |
418 | be used as the destination of some of the arithmetic ops. There are |
419 | also some special purpose registers; the T bit register, the | |
ddd5a7c1 | 420 | Procedure Return Register and the Multiply Accumulate Registers. */ |
bc45ade3 SC |
421 | |
422 | enum reg_class | |
423 | { | |
424 | NO_REGS, | |
425 | R0_REGS, | |
bc45ade3 SC |
426 | PR_REGS, |
427 | T_REGS, | |
428 | MAC_REGS, | |
0d7e008e | 429 | GENERAL_REGS, |
bc45ade3 SC |
430 | ALL_REGS, |
431 | LIM_REG_CLASSES | |
432 | }; | |
433 | ||
434 | #define N_REG_CLASSES (int) LIM_REG_CLASSES | |
435 | ||
994295f2 | 436 | /* Give names of register classes as strings for dump file. */ |
c5d67833 | 437 | #define REG_CLASS_NAMES \ |
bc45ade3 SC |
438 | { \ |
439 | "NO_REGS", \ | |
440 | "R0_REGS", \ | |
bc45ade3 SC |
441 | "PR_REGS", \ |
442 | "T_REGS", \ | |
443 | "MAC_REGS", \ | |
0d7e008e | 444 | "GENERAL_REGS", \ |
bc45ade3 SC |
445 | "ALL_REGS", \ |
446 | } | |
447 | ||
448 | /* Define which registers fit in which classes. | |
449 | This is an initializer for a vector of HARD_REG_SET | |
450 | of length N_REG_CLASSES. */ | |
451 | ||
c5d67833 | 452 | #define REG_CLASS_CONTENTS \ |
bc45ade3 SC |
453 | { \ |
454 | 0x000000, /* NO_REGS */ \ | |
455 | 0x000001, /* R0_REGS */ \ | |
bc45ade3 SC |
456 | 0x020000, /* PR_REGS */ \ |
457 | 0x040000, /* T_REGS */ \ | |
458 | 0x300000, /* MAC_REGS */ \ | |
0d7e008e | 459 | 0x01FFFF, /* GENERAL_REGS */ \ |
bc45ade3 SC |
460 | 0x37FFFF /* ALL_REGS */ \ |
461 | } | |
462 | ||
463 | /* The same information, inverted: | |
464 | Return the class number of the smallest class containing | |
465 | reg number REGNO. This could be a conditional expression | |
466 | or could index an array. */ | |
467 | ||
468 | extern int regno_reg_class[]; | |
469 | #define REGNO_REG_CLASS(REGNO) regno_reg_class[REGNO] | |
470 | ||
0d7e008e SC |
471 | /* When defined, the compiler allows registers explicitly used in the |
472 | rtl to be used as spill registers but prevents the compiler from | |
994295f2 | 473 | extending the lifetime of these registers. */ |
0d7e008e SC |
474 | |
475 | #define SMALL_REGISTER_CLASSES | |
476 | ||
bc45ade3 | 477 | /* The order in which register should be allocated. */ |
c5d67833 | 478 | #define REG_ALLOC_ORDER \ |
0d7e008e | 479 | { 1,2,3,7,6,5,4,0,8,9,10,11,12,13,14,15,16,17,18,19,20,21 } |
bc45ade3 SC |
480 | |
481 | /* The class value for index registers, and the one for base regs. */ | |
482 | #define INDEX_REG_CLASS R0_REGS | |
483 | #define BASE_REG_CLASS GENERAL_REGS | |
484 | ||
994295f2 JW |
485 | /* Get reg_class from a letter such as appears in the machine |
486 | description. */ | |
bc45ade3 SC |
487 | extern enum reg_class reg_class_from_letter[]; |
488 | ||
489 | #define REG_CLASS_FROM_LETTER(C) \ | |
490 | ( (C) >= 'a' && (C) <= 'z' ? reg_class_from_letter[(C)-'a'] : NO_REGS ) | |
c5d67833 | 491 | \f |
bc45ade3 SC |
492 | /* The letters I, J, K, L and M in a register constraint string |
493 | can be used to stand for particular ranges of immediate operands. | |
494 | This macro defines what the ranges are. | |
495 | C is the letter, and VALUE is a constant value. | |
496 | Return 1 if VALUE is in the range specified by C. | |
497 | I: arithmetic operand -127..128, as used in add, sub, etc | |
b52cd365 | 498 | K: shift operand 1,2,8 or 16 |
b9654711 | 499 | L: logical operand 0..255, as used in and, or, etc. |
bc45ade3 | 500 | M: constant 1 |
b52cd365 | 501 | N: constant 0 */ |
bc45ade3 | 502 | |
b9654711 | 503 | #define CONST_OK_FOR_I(VALUE) (((int)(VALUE))>= -128 && ((int)(VALUE)) <= 127) |
b52cd365 | 504 | #define CONST_OK_FOR_K(VALUE) ((VALUE)==1||(VALUE)==2||(VALUE)==8||(VALUE)==16) |
b9654711 | 505 | #define CONST_OK_FOR_L(VALUE) (((int)(VALUE))>= 0 && ((int)(VALUE)) <= 255) |
bc45ade3 | 506 | #define CONST_OK_FOR_M(VALUE) ((VALUE)==1) |
0d7e008e | 507 | #define CONST_OK_FOR_N(VALUE) ((VALUE)==0) |
c5d67833 JW |
508 | #define CONST_OK_FOR_LETTER_P(VALUE, C) \ |
509 | ((C) == 'I' ? CONST_OK_FOR_I (VALUE) \ | |
510 | : (C) == 'K' ? CONST_OK_FOR_K (VALUE) \ | |
511 | : (C) == 'L' ? CONST_OK_FOR_L (VALUE) \ | |
512 | : (C) == 'M' ? CONST_OK_FOR_M (VALUE) \ | |
513 | : (C) == 'N' ? CONST_OK_FOR_N (VALUE) \ | |
bc45ade3 SC |
514 | : 0) |
515 | ||
516 | /* Similar, but for floating constants, and defining letters G and H. | |
517 | Here VALUE is the CONST_DOUBLE rtx itself. */ | |
518 | ||
c5d67833 | 519 | #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) 0 |
bc45ade3 SC |
520 | |
521 | /* Given an rtx X being reloaded into a reg required to be | |
522 | in class CLASS, return the class of reg to actually use. | |
523 | In general this is just CLASS; but on some machines | |
524 | in some cases it is preferable to use a more restrictive class. */ | |
525 | ||
0d7e008e | 526 | #define PREFERRED_RELOAD_CLASS(X, CLASS) CLASS |
bc45ade3 | 527 | |
bc45ade3 | 528 | /* Return the maximum number of consecutive registers |
994295f2 | 529 | needed to represent mode MODE in a register of class CLASS. |
bc45ade3 | 530 | |
994295f2 | 531 | On SH this is the size of MODE in words. */ |
c5d67833 | 532 | #define CLASS_MAX_NREGS(CLASS, MODE) \ |
bc45ade3 | 533 | ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) |
bc45ade3 SC |
534 | \f |
535 | /* Stack layout; function entry, exit and calling. */ | |
536 | ||
c5d67833 JW |
537 | /* Define the number of registers that can hold parameters. |
538 | These three macros are used only in other macro definitions below. */ | |
bc45ade3 SC |
539 | #define NPARM_REGS 4 |
540 | #define FIRST_PARM_REG 4 | |
97b65a3e | 541 | #define FIRST_RET_REG 0 |
bc45ade3 SC |
542 | |
543 | /* Define this if pushing a word on the stack | |
544 | makes the stack pointer a smaller address. */ | |
994295f2 | 545 | #define STACK_GROWS_DOWNWARD |
bc45ade3 | 546 | |
0d7e008e SC |
547 | /* Define this macro if the addresses of local variable slots are at |
548 | negative offsets from the frame pointer. | |
bc45ade3 | 549 | |
994295f2 | 550 | The SH only has positive indexes, so grow the frame up. */ |
0d7e008e SC |
551 | /* #define FRAME_GROWS_DOWNWARD */ |
552 | ||
553 | /* Offset from the frame pointer to the first local variable slot to | |
994295f2 | 554 | be allocated. */ |
bc45ade3 SC |
555 | #define STARTING_FRAME_OFFSET 0 |
556 | ||
557 | /* If we generate an insn to push BYTES bytes, | |
558 | this says how many the stack pointer really advances by. */ | |
559 | #define PUSH_ROUNDING(NPUSHED) (((NPUSHED) + 3) & ~3) | |
560 | ||
561 | /* Offset of first parameter from the argument pointer register value. */ | |
562 | #define FIRST_PARM_OFFSET(FNDECL) 0 | |
563 | ||
564 | /* Value is the number of byte of arguments automatically | |
565 | popped when returning from a subroutine call. | |
8b109b37 | 566 | FUNDECL is the declaration node of the function (as a tree), |
bc45ade3 SC |
567 | FUNTYPE is the data type of the function (as a tree), |
568 | or for a library call it is an identifier node for the subroutine name. | |
569 | SIZE is the number of bytes of arguments passed on the stack. | |
570 | ||
571 | On the SH, the caller does not pop any of its arguments that were passed | |
572 | on the stack. */ | |
8b109b37 | 573 | #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0 |
bc45ade3 SC |
574 | |
575 | /* Define how to find the value returned by a function. | |
576 | VALTYPE is the data type of the value (as a tree). | |
577 | If the precise function being called is known, FUNC is its FUNCTION_DECL; | |
578 | otherwise, FUNC is 0. */ | |
0d7e008e SC |
579 | |
580 | #define FUNCTION_VALUE(VALTYPE, FUNC) \ | |
c5d67833 | 581 | gen_rtx (REG, TYPE_MODE (VALTYPE), FIRST_RET_REG) |
bc45ade3 SC |
582 | |
583 | /* Define how to find the value returned by a library function | |
584 | assuming the value has mode MODE. */ | |
c5d67833 | 585 | #define LIBCALL_VALUE(MODE) gen_rtx (REG, MODE, FIRST_RET_REG) |
bc45ade3 SC |
586 | |
587 | /* 1 if N is a possible register number for a function value. | |
0d7e008e | 588 | On the SH, only r0 can return results. */ |
c5d67833 | 589 | #define FUNCTION_VALUE_REGNO_P(REGNO) ((REGNO) == FIRST_RET_REG) |
bc45ade3 | 590 | |
994295f2 | 591 | /* 1 if N is a possible register number for function argument passing. */ |
bc45ade3 | 592 | |
c5d67833 | 593 | #define FUNCTION_ARG_REGNO_P(REGNO) \ |
bc45ade3 | 594 | ((REGNO) >= FIRST_PARM_REG && (REGNO) < (NPARM_REGS + FIRST_PARM_REG)) |
bc45ade3 SC |
595 | \f |
596 | /* Define a data type for recording info about an argument list | |
597 | during the scan of that argument list. This data type should | |
598 | hold all necessary information about the function itself | |
599 | and about the args processed so far, enough to enable macros | |
600 | such as FUNCTION_ARG to determine where the next arg should go. | |
601 | ||
602 | On SH, this is a single integer, which is a number of words | |
603 | of arguments scanned so far (including the invisible argument, | |
604 | if any, which holds the structure-value-address). | |
605 | Thus NARGREGS or more means all following args should go on the stack. */ | |
606 | ||
607 | #define CUMULATIVE_ARGS int | |
608 | ||
c5d67833 | 609 | #define ROUND_ADVANCE(SIZE) \ |
bc45ade3 SC |
610 | ((SIZE + UNITS_PER_WORD - 1) / UNITS_PER_WORD) |
611 | ||
994295f2 JW |
612 | /* Round a register number up to a proper boundary for an arg of mode |
613 | MODE. | |
614 | ||
d3ae8277 | 615 | The SH doesn't care about double alignment, so we only |
994295f2 | 616 | round doubles to even regs when asked to explicitly. */ |
bc45ade3 SC |
617 | |
618 | #define ROUND_REG(X, MODE) \ | |
619 | ((TARGET_ALIGN_DOUBLE \ | |
620 | && GET_MODE_UNIT_SIZE ((MODE)) > UNITS_PER_WORD) \ | |
621 | ? ((X) + ((X) & 1)) : (X)) | |
622 | ||
bc45ade3 SC |
623 | /* Initialize a variable CUM of type CUMULATIVE_ARGS |
624 | for a call to a function whose data type is FNTYPE. | |
625 | For a library call, FNTYPE is 0. | |
626 | ||
627 | On SH, the offset always starts at 0: the first parm reg is always | |
628 | the same reg. */ | |
629 | ||
c5d67833 | 630 | #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME) \ |
bc45ade3 SC |
631 | ((CUM) = 0) |
632 | ||
633 | /* Update the data in CUM to advance over an argument | |
634 | of mode MODE and data type TYPE. | |
635 | (TYPE is null for libcalls where that information may not be | |
636 | available.) */ | |
637 | ||
638 | #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ | |
639 | ((CUM) = (ROUND_REG ((CUM), (MODE)) \ | |
640 | + ((MODE) != BLKmode \ | |
641 | ? ROUND_ADVANCE (GET_MODE_SIZE (MODE)) \ | |
642 | : ROUND_ADVANCE (int_size_in_bytes (TYPE))))) | |
643 | ||
644 | /* Define where to put the arguments to a function. | |
645 | Value is zero to push the argument on the stack, | |
646 | or a hard register in which to store the argument. | |
647 | ||
648 | MODE is the argument's machine mode. | |
649 | TYPE is the data type of the argument (as a tree). | |
650 | This is null for libcalls where that information may | |
651 | not be available. | |
652 | CUM is a variable of type CUMULATIVE_ARGS which gives info about | |
653 | the preceding args and about the function being called. | |
654 | NAMED is nonzero if this argument is a named parameter | |
655 | (otherwise it is an extra parameter matching an ellipsis). | |
656 | ||
657 | On SH the first args are normally in registers | |
658 | and the rest are pushed. Any arg that starts within the first | |
659 | NPARM_REGS words is at least partially passed in a register unless | |
660 | its data type forbids. */ | |
661 | ||
d3ae8277 | 662 | #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ |
c5d67833 | 663 | sh_function_arg (CUM, MODE, TYPE, NAMED) |
d3ae8277 SC |
664 | |
665 | extern struct rtx_def *sh_function_arg(); | |
bc45ade3 SC |
666 | |
667 | /* For an arg passed partly in registers and partly in memory, | |
668 | this is the number of registers used. | |
669 | For args passed entirely in registers or entirely in memory, zero. | |
994295f2 JW |
670 | |
671 | We sometimes split args. */ | |
0d7e008e | 672 | |
d3ae8277 SC |
673 | #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \ |
674 | sh_function_arg_partial_nregs (CUM, MODE, TYPE, NAMED) | |
bc45ade3 SC |
675 | |
676 | extern int current_function_anonymous_args; | |
677 | ||
678 | /* Perform any needed actions needed for a function that is receiving a | |
994295f2 | 679 | variable number of arguments. */ |
bc45ade3 SC |
680 | |
681 | #define SETUP_INCOMING_VARARGS(ASF, MODE, TYPE, PAS, ST) \ | |
682 | current_function_anonymous_args = 1; | |
683 | ||
994295f2 | 684 | /* Call the function profiler with a given profile label. */ |
bc45ade3 | 685 | |
b9654711 SC |
686 | #define FUNCTION_PROFILER(STREAM,LABELNO) \ |
687 | { \ | |
688 | fprintf(STREAM, " trapa #5\n"); \ | |
689 | fprintf(STREAM, " .align 2\n"); \ | |
690 | fprintf(STREAM, " .long LP%d\n", (LABELNO)); \ | |
bc45ade3 SC |
691 | } |
692 | ||
bc45ade3 SC |
693 | /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, |
694 | the stack pointer does not matter. The value is tested only in | |
695 | functions that have frame pointers. | |
696 | No definition is equivalent to always zero. */ | |
697 | ||
4fdd1f85 | 698 | #define EXIT_IGNORE_STACK 1 |
bc45ade3 | 699 | |
994295f2 JW |
700 | /* Generate the assembly code for function exit |
701 | Just dump out any accumulated constant table. */ | |
bc45ade3 | 702 | |
0d7e008e SC |
703 | #define FUNCTION_EPILOGUE(STREAM, SIZE) function_epilogue (STREAM, SIZE) |
704 | ||
bc45ade3 SC |
705 | /* Output assembler code for a block containing the constant parts |
706 | of a trampoline, leaving space for the variable parts. | |
707 | ||
ddd5a7c1 | 708 | On the SH, the trampoline looks like |
bc45ade3 SC |
709 | 1 0000 D301 mov.l l1,r3 |
710 | 2 0002 DD02 mov.l l2,r13 | |
711 | 3 0004 4D2B jmp @r13 | |
712 | 4 0006 200B or r0,r0 | |
713 | 5 0008 00000000 l1: .long function | |
994295f2 | 714 | 6 000c 00000000 l2: .long area */ |
bc45ade3 SC |
715 | #define TRAMPOLINE_TEMPLATE(FILE) \ |
716 | { \ | |
717 | fprintf ((FILE), " .word 0xd301\n"); \ | |
718 | fprintf ((FILE), " .word 0xdd02\n"); \ | |
c5d67833 | 719 | fprintf ((FILE), " .word 0x4d2b\n"); \ |
bc45ade3 SC |
720 | fprintf ((FILE), " .word 0x200b\n"); \ |
721 | fprintf ((FILE), " .long 0\n"); \ | |
722 | fprintf ((FILE), " .long 0\n"); \ | |
723 | } | |
724 | ||
725 | /* Length in units of the trampoline for entering a nested function. */ | |
726 | #define TRAMPOLINE_SIZE 16 | |
727 | ||
728 | /* Alignment required for a trampoline in units. */ | |
729 | #define TRAMPOLINE_ALIGN 4 | |
730 | ||
731 | /* Emit RTL insns to initialize the variable parts of a trampoline. | |
732 | FNADDR is an RTX for the address of the function's pure code. | |
733 | CXT is an RTX for the static chain value for the function. */ | |
734 | ||
c5d67833 | 735 | #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ |
bc45ade3 SC |
736 | { \ |
737 | emit_move_insn (gen_rtx (MEM, SImode, plus_constant ((TRAMP), 8)), \ | |
738 | (CXT)); \ | |
739 | emit_move_insn (gen_rtx (MEM, SImode, plus_constant ((TRAMP), 12)), \ | |
740 | (FNADDR)); \ | |
741 | } | |
bc45ade3 SC |
742 | \f |
743 | /* Addressing modes, and classification of registers for them. */ | |
d3ae8277 | 744 | #define HAVE_POST_INCREMENT 1 |
bc45ade3 SC |
745 | /*#define HAVE_PRE_INCREMENT 1*/ |
746 | /*#define HAVE_POST_DECREMENT 1*/ | |
d3ae8277 | 747 | #define HAVE_PRE_DECREMENT 1 |
bc45ade3 SC |
748 | |
749 | /* Macros to check register numbers against specific register classes. */ | |
750 | ||
751 | /* These assume that REGNO is a hard or pseudo reg number. | |
752 | They give nonzero only if REGNO is a hard reg of the suitable class | |
753 | or a pseudo reg currently allocated to a suitable hard reg. | |
754 | Since they use reg_renumber, they are safe only once reg_renumber | |
994295f2 | 755 | has been allocated, which happens in local-alloc.c. */ |
0d7e008e | 756 | |
c5d67833 | 757 | #define REGNO_OK_FOR_BASE_P(REGNO) \ |
bc45ade3 | 758 | ((REGNO) < PR_REG || (unsigned) reg_renumber[(REGNO)] < PR_REG) |
c5d67833 | 759 | #define REGNO_OK_FOR_INDEX_P(REGNO) \ |
0d7e008e | 760 | ((REGNO) == 0 || (unsigned) reg_renumber[(REGNO)] == 0) |
bc45ade3 | 761 | |
994295f2 JW |
762 | /* Maximum number of registers that can appear in a valid memory |
763 | address. */ | |
bc45ade3 | 764 | |
0d7e008e | 765 | #define MAX_REGS_PER_ADDRESS 2 |
bc45ade3 SC |
766 | |
767 | /* Recognize any constant value that is a valid address. */ | |
768 | ||
c5d67833 | 769 | #define CONSTANT_ADDRESS_P(X) (GET_CODE (X) == LABEL_REF) |
bc45ade3 | 770 | |
994295f2 | 771 | /* Nonzero if the constant value X is a legitimate general operand. */ |
bc45ade3 | 772 | |
058f9bb5 JW |
773 | /* ??? Should modify this to accept CONST_DOUBLE, and then modify the |
774 | constant pool table code to fix loads of CONST_DOUBLEs. If that doesn't | |
c5d67833 JW |
775 | work well, then we can at least handle simple CONST_DOUBLEs here |
776 | such as 0.0. */ | |
777 | #define LEGITIMATE_CONSTANT_P(X) (GET_CODE(X) != CONST_DOUBLE) | |
bc45ade3 | 778 | |
bc45ade3 SC |
779 | /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx |
780 | and check its validity for a certain class. | |
781 | We have two alternate definitions for each of them. | |
782 | The usual definition accepts all pseudo regs; the other rejects | |
783 | them unless they have been allocated suitable hard regs. | |
784 | The symbol REG_OK_STRICT causes the latter definition to be used. */ | |
785 | ||
8e87e161 SC |
786 | #define MODE_DISP_OK_4(X,MODE) ((GET_MODE_SIZE(MODE)==4) && ((unsigned)INTVAL(X)<64) && (!(INTVAL(X) &3))) |
787 | #define MODE_DISP_OK_8(X,MODE) ((GET_MODE_SIZE(MODE)==8) && ((unsigned)INTVAL(X)<60) && (!(INTVAL(X) &3))) | |
0d7e008e | 788 | |
bc45ade3 | 789 | #ifndef REG_OK_STRICT |
b9654711 | 790 | |
bc45ade3 SC |
791 | /* Nonzero if X is a hard reg that can be used as a base reg |
792 | or if it is a pseudo reg. */ | |
793 | #define REG_OK_FOR_BASE_P(X) \ | |
0d7e008e | 794 | (REGNO (X) <= 16 || REGNO(X) >= FIRST_PSEUDO_REGISTER) |
c5d67833 | 795 | |
bc45ade3 SC |
796 | /* Nonzero if X is a hard reg that can be used as an index |
797 | or if it is a pseudo reg. */ | |
798 | #define REG_OK_FOR_INDEX_P(X) \ | |
0d7e008e | 799 | (REGNO (X) == 0 || REGNO(X) >= FIRST_PSEUDO_REGISTER) |
b9654711 | 800 | |
bc45ade3 | 801 | #else |
c5d67833 | 802 | |
bc45ade3 | 803 | /* Nonzero if X is a hard reg that can be used as a base reg. */ |
c5d67833 | 804 | #define REG_OK_FOR_BASE_P(X) \ |
b9654711 SC |
805 | REGNO_OK_FOR_BASE_P (REGNO (X)) |
806 | ||
bc45ade3 | 807 | /* Nonzero if X is a hard reg that can be used as an index. */ |
c5d67833 | 808 | #define REG_OK_FOR_INDEX_P(X) \ |
b9654711 SC |
809 | REGNO_OK_FOR_INDEX_P (REGNO (X)) |
810 | ||
bc45ade3 | 811 | #endif |
0d7e008e | 812 | |
c5d67833 | 813 | /* The 'Q' constraint is a pc relative load operand. */ |
06c386ea SC |
814 | #define EXTRA_CONSTRAINT_Q(OP) \ |
815 | (GET_CODE (OP) == MEM && \ | |
816 | ((GET_CODE (XEXP (OP, 0)) == LABEL_REF) \ | |
817 | || (GET_CODE (XEXP (OP, 0)) == CONST \ | |
818 | && GET_CODE (XEXP (XEXP (OP, 0), 0)) == PLUS \ | |
819 | && GET_CODE (XEXP (XEXP (XEXP (OP, 0), 0), 0)) == LABEL_REF \ | |
820 | && GET_CODE (XEXP (XEXP (XEXP (OP, 0), 0), 1)) == CONST_INT))) | |
0d7e008e | 821 | |
c5d67833 JW |
822 | #define EXTRA_CONSTRAINT(OP, C) \ |
823 | ((C) == 'Q' ? EXTRA_CONSTRAINT_Q (OP) \ | |
824 | : 0) | |
bc45ade3 SC |
825 | \f |
826 | /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression | |
827 | that is a valid memory address for an instruction. | |
828 | The MODE argument is the machine mode for the MEM expression | |
829 | that wants to use this address. | |
830 | ||
831 | The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS. */ | |
b9654711 | 832 | |
c5d67833 JW |
833 | #define BASE_REGISTER_RTX_P(X) \ |
834 | ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \ | |
835 | || (GET_CODE (X) == SUBREG \ | |
836 | && GET_CODE (SUBREG_REG (X)) == REG \ | |
837 | && REG_OK_FOR_BASE_P (SUBREG_REG (X)))) | |
bc45ade3 | 838 | |
c5d67833 JW |
839 | #define INDEX_REGISTER_RTX_P(X) \ |
840 | ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \ | |
841 | || (GET_CODE (X) == SUBREG \ | |
842 | && GET_CODE (SUBREG_REG (X)) == REG \ | |
843 | && REG_OK_FOR_INDEX_P (SUBREG_REG (X)))) | |
bc45ade3 SC |
844 | |
845 | /* Jump to LABEL if X is a valid address RTX. This must also take | |
846 | REG_OK_STRICT into account when deciding about valid registers, but it uses | |
994295f2 JW |
847 | the above macros so we are in luck. |
848 | ||
bc45ade3 SC |
849 | Allow REG |
850 | REG+disp | |
851 | REG+r0 | |
852 | REG++ | |
994295f2 | 853 | --REG */ |
bc45ade3 | 854 | |
994295f2 | 855 | /* The SH allows a displacement in a QI or HI amode, but only when the |
b9654711 SC |
856 | other operand is R0. GCC doesn't handle this very well, so we forgo |
857 | all of that. | |
858 | ||
c5d67833 JW |
859 | A legitimate index for a QI or HI is 0, SI can be any number 0..63, |
860 | DI can be any number 0..60. */ | |
bc45ade3 | 861 | |
c5d67833 | 862 | #define GO_IF_LEGITIMATE_INDEX(MODE, OP, LABEL) \ |
0d7e008e SC |
863 | do { \ |
864 | if (GET_CODE (OP) == CONST_INT) \ | |
865 | { \ | |
866 | if (MODE_DISP_OK_4 (OP, MODE)) goto LABEL; \ | |
d3ae8277 | 867 | if (MODE_DISP_OK_8 (OP, MODE)) goto LABEL; \ |
0d7e008e | 868 | } \ |
bc45ade3 SC |
869 | } while(0) |
870 | ||
c5d67833 JW |
871 | #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \ |
872 | { \ | |
873 | if (BASE_REGISTER_RTX_P (X)) \ | |
874 | goto LABEL; \ | |
875 | else if ((GET_CODE (X) == POST_INC || GET_CODE (X) == PRE_DEC) \ | |
876 | && BASE_REGISTER_RTX_P (XEXP (X, 0))) \ | |
877 | goto LABEL; \ | |
878 | else if (GET_CODE (X) == PLUS) \ | |
879 | { \ | |
880 | rtx xop0 = XEXP (X, 0); \ | |
881 | rtx xop1 = XEXP (X, 1); \ | |
882 | if (GET_MODE_SIZE (MODE) <= 8 && BASE_REGISTER_RTX_P (xop0)) \ | |
883 | GO_IF_LEGITIMATE_INDEX (MODE, xop1, LABEL); \ | |
884 | if (GET_MODE_SIZE (MODE) <= 4) \ | |
885 | { \ | |
886 | if (BASE_REGISTER_RTX_P (xop1) && INDEX_REGISTER_RTX_P (xop0))\ | |
887 | goto LABEL; \ | |
888 | if (INDEX_REGISTER_RTX_P (xop1) && BASE_REGISTER_RTX_P (xop0))\ | |
889 | goto LABEL; \ | |
890 | } \ | |
891 | } \ | |
994295f2 JW |
892 | } |
893 | \f | |
894 | /* Try machine-dependent ways of modifying an illegitimate address | |
bc45ade3 SC |
895 | to be legitimate. If we find one, return the new, valid address. |
896 | This macro is used in only one place: `memory_address' in explow.c. | |
897 | ||
898 | OLDX is the address as it was before break_out_memory_refs was called. | |
899 | In some cases it is useful to look at this to decide what needs to be done. | |
900 | ||
901 | MODE and WIN are passed so that this macro can use | |
902 | GO_IF_LEGITIMATE_ADDRESS. | |
903 | ||
904 | It is always safe for this macro to do nothing. It exists to recognize | |
994295f2 | 905 | opportunities to optimize the output. */ |
bc45ade3 | 906 | |
d3ae8277 | 907 | #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) ; |
bc45ade3 SC |
908 | |
909 | /* Go to LABEL if ADDR (a legitimate address expression) | |
910 | has an effect that depends on the machine mode it is used for. */ | |
c5d67833 | 911 | #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \ |
bc45ade3 | 912 | { \ |
c5d67833 | 913 | if (GET_CODE(ADDR) == PRE_DEC || GET_CODE(ADDR) == POST_INC) \ |
bc45ade3 SC |
914 | goto LABEL; \ |
915 | } | |
916 | \f | |
917 | /* Specify the machine mode that this machine uses | |
918 | for the index in the tablejump instruction. */ | |
0d7e008e | 919 | #define CASE_VECTOR_MODE (TARGET_BIGTABLE ? SImode : HImode) |
bc45ade3 SC |
920 | |
921 | /* Define this if the tablejump instruction expects the table | |
922 | to contain offsets from the address of the table. | |
923 | Do not define this if the table should contain absolute addresses. */ | |
994295f2 | 924 | #define CASE_VECTOR_PC_RELATIVE |
bc45ade3 SC |
925 | |
926 | /* Specify the tree operation to be used to convert reals to integers. */ | |
927 | #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR | |
928 | ||
929 | /* This is the kind of divide that is easiest to do in the general case. */ | |
930 | #define EASY_DIV_EXPR TRUNC_DIV_EXPR | |
931 | ||
994295f2 | 932 | /* 'char' is signed by default. */ |
bc45ade3 SC |
933 | #define DEFAULT_SIGNED_CHAR 1 |
934 | ||
935 | /* The type of size_t unsigned int. */ | |
936 | #define SIZE_TYPE "unsigned int" | |
937 | ||
8e87e161 SC |
938 | #define WCHAR_TYPE "short unsigned int" |
939 | #define WCHAR_TYPE_SIZE 16 | |
940 | ||
bc45ade3 | 941 | /* Don't cse the address of the function being compiled. */ |
0d7e008e | 942 | /*#define NO_RECURSIVE_FUNCTION_CSE 1*/ |
bc45ade3 SC |
943 | |
944 | /* Max number of bytes we can move from memory to memory | |
945 | in one reasonably fast instruction. */ | |
946 | #define MOVE_MAX 4 | |
947 | ||
9a63901f RK |
948 | /* Define if operations between registers always perform the operation |
949 | on the full register even if a narrower mode is specified. */ | |
950 | #define WORD_REGISTER_OPERATIONS | |
951 | ||
952 | /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD | |
953 | will either zero-extend or sign-extend. The value of this macro should | |
954 | be the code that says which one of the two operations is implicitly | |
955 | done, NIL if none. */ | |
956 | #define LOAD_EXTEND_OP(MODE) SIGN_EXTEND | |
bc45ade3 SC |
957 | |
958 | /* Define this if zero-extension is slow (more than one real instruction). | |
994295f2 | 959 | On the SH, it's only one instruction. */ |
bc45ade3 SC |
960 | /* #define SLOW_ZERO_EXTEND */ |
961 | ||
962 | /* Nonzero if access to memory by bytes is slow and undesirable. */ | |
963 | #define SLOW_BYTE_ACCESS 0 | |
964 | ||
965 | /* We assume that the store-condition-codes instructions store 0 for false | |
966 | and some other value for true. This is the value stored for true. */ | |
967 | ||
968 | #define STORE_FLAG_VALUE 1 | |
969 | ||
970 | /* Immediate shift counts are truncated by the output routines (or was it | |
97b65a3e | 971 | the assembler?). Shift counts in a register are truncated by SH. Note |
bc45ade3 | 972 | that the native compiler puts too large (> 32) immediate shift counts |
97b65a3e | 973 | into a register and shifts by the register, letting the SH decide what |
bc45ade3 SC |
974 | to do instead of doing that itself. */ |
975 | #define SHIFT_COUNT_TRUNCATED 1 | |
976 | ||
bc45ade3 SC |
977 | /* All integers have the same format so truncation is easy. */ |
978 | #define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) 1 | |
979 | ||
980 | /* Define this if addresses of constant functions | |
981 | shouldn't be put through pseudo regs where they can be cse'd. | |
982 | Desirable on machines where ordinary constants are expensive | |
983 | but a CALL with constant address is cheap. */ | |
984 | /*#define NO_FUNCTION_CSE 1*/ | |
985 | ||
986 | /* Chars and shorts should be passed as ints. */ | |
987 | #define PROMOTE_PROTOTYPES 1 | |
988 | ||
994295f2 | 989 | /* The machine modes of pointers and functions. */ |
bc45ade3 SC |
990 | #define Pmode SImode |
991 | #define FUNCTION_MODE Pmode | |
992 | ||
bc45ade3 SC |
993 | /* The relative costs of various types of constants. Note that cse.c defines |
994 | REG = 1, SUBREG = 2, any node = (2 + sum of subnodes). */ | |
995 | ||
c5d67833 | 996 | #define CONST_COSTS(RTX, CODE, OUTER_CODE) \ |
bc45ade3 | 997 | case CONST_INT: \ |
97b65a3e JW |
998 | if (INTVAL (RTX) == 0) \ |
999 | return 0; \ | |
1000 | else if (CONST_OK_FOR_I (INTVAL (RTX))) \ | |
1001 | return 1; \ | |
1002 | else if ((OUTER_CODE == AND || OUTER_CODE == IOR || OUTER_CODE == XOR) \ | |
1003 | && CONST_OK_FOR_L (INTVAL (RTX))) \ | |
bc45ade3 SC |
1004 | return 1; \ |
1005 | else \ | |
b9654711 | 1006 | return 8; \ |
bc45ade3 SC |
1007 | case CONST: \ |
1008 | case LABEL_REF: \ | |
1009 | case SYMBOL_REF: \ | |
b9654711 | 1010 | return 5; \ |
bc45ade3 SC |
1011 | case CONST_DOUBLE: \ |
1012 | return 10; | |
1013 | ||
1014 | #define RTX_COSTS(X, CODE, OUTER_CODE) \ | |
0d7e008e | 1015 | case AND: \ |
c5d67833 | 1016 | return COSTS_N_INSNS (andcosts (X)); \ |
bc45ade3 | 1017 | case MULT: \ |
b9654711 SC |
1018 | return COSTS_N_INSNS (multcosts (X)); \ |
1019 | case ASHIFT: \ | |
1020 | case ASHIFTRT: \ | |
994295f2 | 1021 | case LSHIFTRT: \ |
b9654711 | 1022 | return COSTS_N_INSNS (shiftcosts (X)) ; \ |
bc45ade3 SC |
1023 | case DIV: \ |
1024 | case UDIV: \ | |
1025 | case MOD: \ | |
1026 | case UMOD: \ | |
00f8ff66 | 1027 | return COSTS_N_INSNS (20); \ |
bc45ade3 SC |
1028 | case FLOAT: \ |
1029 | case FIX: \ | |
1030 | return 100; | |
1031 | ||
97b65a3e JW |
1032 | /* The multiply insn on the SH1 and the divide insns on the SH1 and SH2 |
1033 | are actually function calls with some special constraints on arguments | |
1034 | and register usage. | |
0d7e008e | 1035 | |
994295f2 JW |
1036 | These macros tell reorg that the references to arguments and |
1037 | register clobbers for insns of type sfunc do not appear to happen | |
0d7e008e SC |
1038 | until after the millicode call. This allows reorg to put insns |
1039 | which set the argument registers into the delay slot of the millicode | |
1040 | call -- thus they act more like traditional CALL_INSNs. | |
1041 | ||
1042 | get_attr_type will try to recognize the given insn, so make sure to | |
1043 | filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns | |
1044 | in particular. */ | |
1045 | ||
1046 | #define INSN_SETS_ARE_DELAYED(X) \ | |
1047 | ((GET_CODE (X) == INSN \ | |
1048 | && GET_CODE (PATTERN (X)) != SEQUENCE \ | |
1049 | && GET_CODE (PATTERN (X)) != USE \ | |
1050 | && GET_CODE (PATTERN (X)) != CLOBBER \ | |
1051 | && get_attr_type (X) == TYPE_SFUNC)) | |
1052 | ||
1053 | #define INSN_REFERENCES_ARE_DELAYED(X) \ | |
1054 | ((GET_CODE (X) == INSN \ | |
1055 | && GET_CODE (PATTERN (X)) != SEQUENCE \ | |
1056 | && GET_CODE (PATTERN (X)) != USE \ | |
1057 | && GET_CODE (PATTERN (X)) != CLOBBER \ | |
994295f2 | 1058 | && get_attr_type (X) == TYPE_SFUNC)) |
0d7e008e | 1059 | |
bc45ade3 | 1060 | /* Compute extra cost of moving data between one register class |
994295f2 | 1061 | and another. |
bc45ade3 SC |
1062 | |
1063 | On the SH it is hard to move into the T reg, but simple to load | |
994295f2 | 1064 | from it. */ |
bc45ade3 | 1065 | |
c5d67833 | 1066 | #define REGISTER_MOVE_COST(SRCCLASS, DSTCLASS) \ |
0d7e008e | 1067 | (((DSTCLASS == T_REGS) || (DSTCLASS == PR_REG)) ? 10 : 1) |
bc45ade3 | 1068 | \f |
994295f2 | 1069 | /* Assembler output control. */ |
bc45ade3 | 1070 | |
994295f2 JW |
1071 | /* The text to go at the start of the assembler file. */ |
1072 | #define ASM_FILE_START(STREAM) \ | |
1073 | output_file_start (STREAM, f_options, \ | |
1074 | sizeof f_options / sizeof f_options[0], \ | |
1075 | W_options, sizeof W_options / sizeof W_options[0]); | |
bc45ade3 | 1076 | |
994295f2 | 1077 | #define ASM_FILE_END(STREAM) |
bc45ade3 | 1078 | |
0d7e008e SC |
1079 | #define ASM_APP_ON "" |
1080 | #define ASM_APP_OFF "" | |
1081 | #define FILE_ASM_OP "\t.file\n" | |
1082 | #define IDENT_ASM_OP "\t.ident\n" | |
bc45ade3 | 1083 | |
994295f2 | 1084 | /* How to change between sections. */ |
bc45ade3 | 1085 | |
8e87e161 SC |
1086 | #define TEXT_SECTION_ASM_OP "\t.text" |
1087 | #define DATA_SECTION_ASM_OP "\t.data" | |
8e87e161 SC |
1088 | #define CTORS_SECTION_ASM_OP "\t.section\t.ctors\n" |
1089 | #define DTORS_SECTION_ASM_OP "\t.section\t.dtors\n" | |
1090 | #define INIT_SECTION_ASM_OP "\t.section\t.init\n" | |
06c386ea | 1091 | #define EXTRA_SECTIONS in_ctors, in_dtors |
c5d67833 JW |
1092 | #define EXTRA_SECTION_FUNCTIONS \ |
1093 | void \ | |
1094 | ctors_section() \ | |
1095 | { \ | |
1096 | if (in_section != in_ctors) \ | |
1097 | { \ | |
1098 | fprintf (asm_out_file, "%s\n", CTORS_SECTION_ASM_OP); \ | |
1099 | in_section = in_ctors; \ | |
1100 | } \ | |
1101 | } \ | |
1102 | void \ | |
1103 | dtors_section() \ | |
1104 | { \ | |
1105 | if (in_section != in_dtors) \ | |
1106 | { \ | |
1107 | fprintf (asm_out_file, "%s\n", DTORS_SECTION_ASM_OP); \ | |
1108 | in_section = in_dtors; \ | |
1109 | } \ | |
994295f2 | 1110 | } |
b9654711 | 1111 | |
7e7be9c3 DE |
1112 | /* A C statement to output something to the assembler file to switch to section |
1113 | NAME for object DECL which is either a FUNCTION_DECL, a VAR_DECL or | |
1114 | NULL_TREE. Some target formats do not support arbitrary sections. Do not | |
1115 | define this macro in such cases. */ | |
d3ae8277 | 1116 | |
7e7be9c3 | 1117 | #define ASM_OUTPUT_SECTION_NAME(FILE, DECL, NAME) \ |
d3ae8277 SC |
1118 | do { fprintf (FILE, ".section\t%s\n", NAME); } while (0) |
1119 | ||
c5d67833 | 1120 | #define ASM_OUTPUT_CONSTRUCTOR(FILE,NAME) \ |
b9654711 SC |
1121 | do { ctors_section(); fprintf(FILE,"\t.long\t_%s\n", NAME); } while (0) |
1122 | ||
c5d67833 | 1123 | #define ASM_OUTPUT_DESTRUCTOR(FILE,NAME) \ |
b9654711 SC |
1124 | do { dtors_section(); fprintf(FILE,"\t.long\t_%s\n", NAME); } while (0) |
1125 | ||
994295f2 | 1126 | #undef DO_GLOBAL_CTORS_BODY |
0d7e008e | 1127 | |
b9654711 SC |
1128 | #define DO_GLOBAL_CTORS_BODY \ |
1129 | { \ | |
1130 | typedef (*pfunc)(); \ | |
1131 | extern pfunc __ctors[]; \ | |
1132 | extern pfunc __ctors_end[]; \ | |
1133 | pfunc *p; \ | |
c1fe41cb | 1134 | for (p = __ctors_end; p > __ctors; ) \ |
b9654711 | 1135 | { \ |
c1fe41cb | 1136 | (*--p)(); \ |
b9654711 | 1137 | } \ |
994295f2 | 1138 | } |
b9654711 | 1139 | |
994295f2 | 1140 | #undef DO_GLOBAL_DTORS_BODY |
c5d67833 | 1141 | #define DO_GLOBAL_DTORS_BODY \ |
b9654711 SC |
1142 | { \ |
1143 | typedef (*pfunc)(); \ | |
1144 | extern pfunc __dtors[]; \ | |
1145 | extern pfunc __dtors_end[]; \ | |
1146 | pfunc *p; \ | |
1147 | for (p = __dtors; p < __dtors_end; p++) \ | |
1148 | { \ | |
1149 | (*p)(); \ | |
1150 | } \ | |
994295f2 | 1151 | } |
b9654711 | 1152 | |
b9654711 SC |
1153 | #define ASM_OUTPUT_REG_PUSH(file, v) \ |
1154 | fprintf (file, "\tmov.l r%s,-@r15\n", v); | |
bc45ade3 | 1155 | |
b9654711 SC |
1156 | #define ASM_OUTPUT_REG_POP(file, v) \ |
1157 | fprintf (file, "\tmov.l @r15+,r%s\n", v); | |
1158 | ||
bc45ade3 SC |
1159 | /* The assembler's names for the registers. RFP need not always be used as |
1160 | the Real framepointer; it can also be used as a normal general register. | |
1161 | Note that the name `fp' is horribly misleading since `fp' is in fact only | |
1162 | the argument-and-return-context pointer. */ | |
1163 | #define REGISTER_NAMES \ | |
1164 | { \ | |
1165 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \ | |
1166 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \ | |
1167 | "ap", "pr", "t", "gbr", "mach","macl" \ | |
1168 | } | |
1169 | ||
994295f2 | 1170 | /* DBX register number for a given compiler register number. */ |
bc45ade3 SC |
1171 | #define DBX_REGISTER_NUMBER(REGNO) (REGNO) |
1172 | ||
1173 | /* Output a label definition. */ | |
c5d67833 | 1174 | #define ASM_OUTPUT_LABEL(FILE,NAME) \ |
bc45ade3 SC |
1175 | do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0) |
1176 | ||
bc45ade3 SC |
1177 | /* This is how to output an assembler line |
1178 | that says to advance the location counter | |
1179 | to a multiple of 2**LOG bytes. */ | |
1180 | ||
1181 | #define ASM_OUTPUT_ALIGN(FILE,LOG) \ | |
1182 | if ((LOG) != 0) \ | |
1183 | fprintf (FILE, "\t.align %d\n", LOG) | |
1184 | ||
1185 | /* Output a function label definition. */ | |
1186 | #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL) \ | |
1187 | ASM_OUTPUT_LABEL(STREAM, NAME) | |
1188 | ||
1189 | /* Output a globalising directive for a label. */ | |
c5d67833 JW |
1190 | #define ASM_GLOBALIZE_LABEL(STREAM,NAME) \ |
1191 | (fprintf (STREAM, "\t.global\t"), \ | |
1192 | assemble_name (STREAM, NAME), \ | |
1193 | fputc ('\n',STREAM)) | |
bc45ade3 SC |
1194 | |
1195 | /* Output a reference to a label. */ | |
c5d67833 | 1196 | #define ASM_OUTPUT_LABELREF(STREAM,NAME) \ |
bc45ade3 SC |
1197 | fprintf (STREAM, "_%s", NAME) |
1198 | ||
1199 | /* Make an internal label into a string. */ | |
c5d67833 | 1200 | #define ASM_GENERATE_INTERNAL_LABEL(STRING, PREFIX, NUM) \ |
bc45ade3 SC |
1201 | sprintf (STRING, "*%s%d", PREFIX, NUM) |
1202 | ||
1203 | /* Output an internal label definition. */ | |
c5d67833 | 1204 | #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \ |
bc45ade3 SC |
1205 | fprintf (FILE, "%s%d:\n", PREFIX, NUM) |
1206 | ||
bc45ade3 SC |
1207 | /* #define ASM_OUTPUT_CASE_END(STREAM,NUM,TABLE) */ |
1208 | ||
1209 | /* Construct a private name. */ | |
c5d67833 JW |
1210 | #define ASM_FORMAT_PRIVATE_NAME(OUTVAR,NAME,NUMBER) \ |
1211 | ((OUTVAR) = (char *) alloca (strlen (NAME) + 10), \ | |
bc45ade3 SC |
1212 | sprintf ((OUTVAR), "%s.%d", (NAME), (NUMBER))) |
1213 | ||
994295f2 | 1214 | /* Jump tables must be 32 bit aligned, no matter the size of the element. */ |
bc1ebe63 | 1215 | #define ASM_OUTPUT_CASE_LABEL(STREAM,PREFIX,NUM,TABLE) \ |
c5d67833 | 1216 | fprintf (STREAM, "\t.align 2\n%s%d:\n", PREFIX, NUM); |
0d7e008e | 1217 | |
994295f2 | 1218 | /* Output a relative address table. */ |
bc1ebe63 | 1219 | |
0d7e008e SC |
1220 | #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM,VALUE,REL) \ |
1221 | if (TARGET_BIGTABLE) \ | |
c5d67833 | 1222 | fprintf (STREAM, "\t.long L%d-L%d\n", VALUE,REL); \ |
0d7e008e | 1223 | else \ |
c5d67833 | 1224 | fprintf (STREAM, "\t.word L%d-L%d\n", VALUE,REL); \ |
bc45ade3 | 1225 | |
994295f2 | 1226 | /* Output an absolute table element. */ |
0d7e008e SC |
1227 | |
1228 | #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM,VALUE) \ | |
1229 | if (TARGET_BIGTABLE) \ | |
c5d67833 | 1230 | fprintf (STREAM, "\t.long L%d\n", VALUE); \ |
0d7e008e | 1231 | else \ |
c5d67833 | 1232 | fprintf (STREAM, "\t.word L%d\n", VALUE); \ |
bc45ade3 SC |
1233 | |
1234 | /* Output various types of constants. */ | |
1235 | ||
994295f2 | 1236 | /* This is how to output an assembler line defining a `double'. */ |
bc45ade3 | 1237 | |
b9654711 SC |
1238 | #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \ |
1239 | do { char dstr[30]; \ | |
1240 | REAL_VALUE_TO_DECIMAL ((VALUE), "%.20e", dstr); \ | |
1241 | fprintf (FILE, "\t.double %s\n", dstr); \ | |
1242 | } while (0) | |
1243 | ||
bc45ade3 | 1244 | /* This is how to output an assembler line defining a `float' constant. */ |
c5d67833 | 1245 | #define ASM_OUTPUT_FLOAT(FILE,VALUE) \ |
b9654711 SC |
1246 | do { char dstr[30]; \ |
1247 | REAL_VALUE_TO_DECIMAL ((VALUE), "%.20e", dstr); \ | |
1248 | fprintf (FILE, "\t.float %s\n", dstr); \ | |
1249 | } while (0) | |
bc45ade3 | 1250 | |
bc45ade3 SC |
1251 | #define ASM_OUTPUT_INT(STREAM, EXP) \ |
1252 | (fprintf (STREAM, "\t.long\t"), \ | |
1253 | output_addr_const (STREAM, (EXP)), \ | |
994295f2 | 1254 | fputc ('\n', STREAM)) |
bc45ade3 | 1255 | |
c5d67833 JW |
1256 | #define ASM_OUTPUT_SHORT(STREAM, EXP) \ |
1257 | (fprintf (STREAM, "\t.short\t"), \ | |
1258 | output_addr_const (STREAM, (EXP)), \ | |
994295f2 | 1259 | fputc ('\n', STREAM)) |
bc45ade3 SC |
1260 | |
1261 | #define ASM_OUTPUT_CHAR(STREAM, EXP) \ | |
1262 | (fprintf (STREAM, "\t.byte\t"), \ | |
1263 | output_addr_const (STREAM, (EXP)), \ | |
1264 | fputc ('\n', STREAM)) | |
1265 | ||
1266 | #define ASM_OUTPUT_BYTE(STREAM, VALUE) \ | |
1267 | fprintf (STREAM, "\t.byte\t%d\n", VALUE) \ | |
1268 | ||
1269 | /* This is how to output an assembler line | |
1270 | that says to advance the location counter by SIZE bytes. */ | |
1271 | ||
c5d67833 | 1272 | #define ASM_OUTPUT_SKIP(FILE,SIZE) \ |
bc45ade3 SC |
1273 | fprintf (FILE, "\t.space %d\n", (SIZE)) |
1274 | ||
1275 | /* This says how to output an assembler line | |
1276 | to define a global common symbol. */ | |
1277 | ||
c5d67833 | 1278 | #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \ |
bc45ade3 SC |
1279 | ( fputs ("\t.comm ", (FILE)), \ |
1280 | assemble_name ((FILE), (NAME)), \ | |
1281 | fprintf ((FILE), ",%d\n", (SIZE))) | |
1282 | ||
1283 | /* This says how to output an assembler line | |
1284 | to define a local common symbol. */ | |
1285 | ||
1286 | #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE,ROUNDED) \ | |
1287 | ( fputs ("\t.lcomm ", (FILE)), \ | |
1288 | assemble_name ((FILE), (NAME)), \ | |
1289 | fprintf ((FILE), ",%d\n", (SIZE))) | |
1290 | ||
bc45ade3 SC |
1291 | /* The assembler's parentheses characters. */ |
1292 | #define ASM_OPEN_PAREN "(" | |
1293 | #define ASM_CLOSE_PAREN ")" | |
1294 | ||
1295 | /* Target characters. */ | |
1296 | #define TARGET_BELL 007 | |
1297 | #define TARGET_BS 010 | |
1298 | #define TARGET_TAB 011 | |
1299 | #define TARGET_NEWLINE 012 | |
1300 | #define TARGET_VT 013 | |
1301 | #define TARGET_FF 014 | |
1302 | #define TARGET_CR 015 | |
1303 | \f | |
bc45ade3 | 1304 | /* Only perform branch elimination (by making instructions conditional) if |
c5d67833 JW |
1305 | we're optimizing. Otherwise it's of no use anyway. */ |
1306 | #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \ | |
1307 | final_prescan_insn (INSN, OPVEC, NOPERANDS) | |
bc45ade3 SC |
1308 | |
1309 | /* Print operand X (an rtx) in assembler syntax to file FILE. | |
1310 | CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. | |
1311 | For `%' followed by punctuation, CODE is the punctuation and X is null. */ | |
1312 | ||
1313 | #define PRINT_OPERAND(STREAM, X, CODE) print_operand (STREAM, X, CODE) | |
1314 | ||
1315 | /* Print a memory address as an operand to reference that memory location. */ | |
1316 | ||
1317 | #define PRINT_OPERAND_ADDRESS(STREAM,X) print_operand_address (STREAM, X) | |
1318 | ||
1319 | #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \ | |
97b65a3e | 1320 | ((CHAR)=='.' || (CHAR) == '#' || (CHAR)=='@') |
bc45ade3 | 1321 | \f |
bc45ade3 SC |
1322 | extern struct rtx_def *sh_compare_op0; |
1323 | extern struct rtx_def *sh_compare_op1; | |
1324 | extern struct rtx_def *prepare_scc_operands(); | |
1325 | ||
994295f2 JW |
1326 | /* Which processor to schedule for. The elements of the enumeration must |
1327 | match exactly the cpu attribute in the sh.md file. */ | |
bc45ade3 | 1328 | |
994295f2 JW |
1329 | enum processor_type { |
1330 | PROCESSOR_SH0, | |
1331 | PROCESSOR_SH1, | |
1332 | PROCESSOR_SH2, | |
1333 | PROCESSOR_SH3 | |
1334 | }; | |
1335 | ||
1336 | #define sh_cpu_attr ((enum attr_cpu)sh_cpu) | |
1337 | extern enum processor_type sh_cpu; | |
1338 | ||
1339 | /* Declare functions defined in sh.c and used in templates. */ | |
bc45ade3 SC |
1340 | |
1341 | extern char *output_branch(); | |
1342 | extern char *output_shift(); | |
1343 | extern char *output_movedouble(); | |
1344 | extern char *output_movepcrel(); | |
0d7e008e SC |
1345 | extern char *output_jump_label_table(); |
1346 | extern char *output_far_jump(); | |
1347 | ||
0d7e008e | 1348 | #define MACHINE_DEPENDENT_REORG(X) machine_dependent_reorg(X) |
bc45ade3 | 1349 | |
0d7e008e | 1350 | /* Generate calls to memcpy, memcmp and memset. */ |
b9654711 | 1351 | |
0d7e008e | 1352 | #define TARGET_MEM_FUNCTIONS |
b9654711 | 1353 | |
8e87e161 | 1354 | #define HANDLE_PRAGMA(finput) return handle_pragma (finput) |
b9654711 | 1355 | |
994295f2 | 1356 | /* Set when processing a function with pragma interrupt turned on. */ |
b9654711 | 1357 | |
0d7e008e | 1358 | extern int pragma_interrupt; |
b9654711 | 1359 | |
058f9bb5 | 1360 | #define MOVE_RATIO (TARGET_SMALLCODE ? 2 : 16) |
b52cd365 JW |
1361 | \f |
1362 | /* Instructions with unfilled delay slots take up an extra two bytes for | |
1363 | the nop in the delay slot. */ | |
1364 | ||
1365 | #define ADJUST_INSN_LENGTH(X, LENGTH) \ | |
1366 | if (((GET_CODE (X) == INSN \ | |
1367 | && GET_CODE (PATTERN (X)) != SEQUENCE \ | |
1368 | && GET_CODE (PATTERN (X)) != USE \ | |
1369 | && GET_CODE (PATTERN (X)) != CLOBBER) \ | |
1370 | || GET_CODE (X) == CALL_INSN \ | |
1371 | || (GET_CODE (X) == JUMP_INSN \ | |
1372 | && GET_CODE (PATTERN (X)) != ADDR_DIFF_VEC \ | |
1373 | && GET_CODE (PATTERN (X)) != ADDR_VEC)) \ | |
1374 | && get_attr_needs_delay_slot (X) == NEEDS_DELAY_SLOT_YES) \ | |
1375 | LENGTH += 2; | |
1376 | ||
1377 | /* Enable a bug fix for the shorten_branches pass. */ | |
1378 | #define SHORTEN_WITH_ADJUST_INSN_LENGTH | |
c5d67833 JW |
1379 | \f |
1380 | /* Define the codes that are matched by predicates in sh.c. */ | |
1381 | #define PREDICATE_CODES \ | |
1382 | {"arith_reg_operand", {SUBREG, REG}}, \ | |
1383 | {"arith_operand", {SUBREG, REG, CONST_INT}}, \ | |
1384 | {"arith_reg_or_0_operand", {SUBREG, REG, CONST_INT}}, \ | |
1385 | {"logical_operand", {SUBREG, REG, CONST_INT}}, \ | |
1386 | {"general_movsrc_operand", {SUBREG, REG, CONST_INT, MEM}}, \ | |
1387 | {"general_movdst_operand", {SUBREG, REG, CONST_INT, MEM}}, | |
1388 | ||
1389 | /* Define this macro if it is advisable to hold scalars in registers | |
1390 | in a wider mode than that declared by the program. In such cases, | |
1391 | the value is constrained to be within the bounds of the declared | |
1392 | type, but kept valid in the wider mode. The signedness of the | |
1393 | extension may differ from that of the type. | |
1394 | ||
1395 | Leaving the unsignedp unchanged gives better code than always setting it | |
1396 | to 0. This is despite the fact that we have only signed char and short | |
1397 | load instructions. */ | |
1398 | #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ | |
1399 | if (GET_MODE_CLASS (MODE) == MODE_INT \ | |
1400 | && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \ | |
1401 | MODE = SImode; | |
1402 | ||
1403 | /* PROMOTE_FUNCTION_ARGS and PROMOTE_FUNCTION_RETURN appear to have no | |
1404 | effect, because all unprototyped char/shorts are already promoted to | |
1405 | int, and because PROMOTE_PROTOTYPES causes all prototypes char/shorts | |
1406 | to be promoted to it. */ | |
1407 | ||
1408 | /* ??? Define ACCUMULATE_OUTGOING_ARGS? This is more efficient than pushing | |
1409 | and poping arguments. However, we do have push/pop instructions, and | |
1410 | rather limited offsets (4 bits) in load/store instructions, so it isn't | |
1411 | clear if this would give better code. If implemented, should check for | |
1412 | compatibility problems. */ | |
1413 | ||
1414 | /* ??? Define ADJUST_COSTS? */ |