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c8f0269d 1/* Definitions of target machine for GNU compiler for Renesas / SuperH SH.
c58b209a 2 Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
283334f0 3 2003, 2004 Free Software Foundation, Inc.
058f9bb5
JW		 4 Contributed by Steve Chamberlain (sac@cygnus.com).
5 Improved by Jim Wilson (wilson@cygnus.com).
bc45ade3 6
7ec022b2 7This file is part of GCC.
bc45ade3 8
7ec022b2 9GCC is free software; you can redistribute it and/or modify
bc45ade3
SC		 10it under the terms of the GNU General Public License as published by
11the Free Software Foundation; either version 2, or (at your option)
12any later version.
13
7ec022b2 14GCC is distributed in the hope that it will be useful,
bc45ade3
SC		 15but WITHOUT ANY WARRANTY; without even the implied warranty of
16MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17GNU General Public License for more details.
18
19You should have received a copy of the GNU General Public License
7ec022b2 20along with GCC; see the file COPYING. If not, write to
c15c9075
RK		 21the Free Software Foundation, 59 Temple Place - Suite 330,
22Boston, MA 02111-1307, USA. */
bc45ade3 23
8b97c5f8
ZW		 24#ifndef GCC_SH_H
25#define GCC_SH_H
8b109b37 26
c5d67833 27#define TARGET_VERSION \
bc45ade3
SC		 28 fputs (" (Hitachi SH)", stderr);
29
e9a25f70 30/* Unfortunately, insn-attrtab.c doesn't include insn-codes.h. We can't
4977bab6 31 include it here, because bconfig.h is also included by gencodes.c . */
5e7f4a4a 32/* ??? No longer true. */
e9a25f70
JL		 33extern int code_for_indirect_jump_scratch;
34
f1a58d92
R		 35#define TARGET_CPU_CPP_BUILTINS() \
36do { \
37 builtin_define ("__sh__"); \
38 builtin_assert ("cpu=sh"); \
39 builtin_assert ("machine=sh"); \
40 switch ((int) sh_cpu) \
41 { \
42 case PROCESSOR_SH1: \
43 builtin_define ("__sh1__"); \
44 break; \
45 case PROCESSOR_SH2: \
46 builtin_define ("__sh2__"); \
47 break; \
3a8699c7
AO		 48 case PROCESSOR_SH2E: \
49 builtin_define ("__SH2E__"); \
50 break; \
f1a58d92
R		 51 case PROCESSOR_SH3: \
52 builtin_define ("__sh3__"); \
53 builtin_define ("__SH3__"); \
54 if (TARGET_HARD_SH4) \
55 builtin_define ("__SH4_NOFPU__"); \
56 break; \
57 case PROCESSOR_SH3E: \
58 builtin_define (TARGET_HARD_SH4 ? "__SH4_SINGLE_ONLY__" : "__SH3E__"); \
59 break; \
60 case PROCESSOR_SH4: \
61 builtin_define (TARGET_FPU_SINGLE ? "__SH4_SINGLE__" : "__SH4__"); \
62 break; \
63 case PROCESSOR_SH5: \
64 { \
65 builtin_define_with_value ("__SH5__", \
66 TARGET_SHMEDIA64 ? "64" : "32", 0); \
67 builtin_define_with_value ("__SHMEDIA__", \
68 TARGET_SHMEDIA ? "1" : "0", 0); \
69 if (! TARGET_FPU_DOUBLE) \
70 builtin_define ("__SH4_NOFPU__"); \
f1a58d92
R		 71 } \
72 } \
73 if (TARGET_HITACHI) \
74 builtin_define ("__HITACHI__"); \
75 builtin_define (TARGET_LITTLE_ENDIAN \
76 ? "__LITTLE_ENDIAN__" : "__BIG_ENDIAN__"); \
77 if (flag_pic) \
78 { \
79 builtin_define ("__pic__"); \
80 builtin_define ("__PIC__"); \
81 } \
f1a58d92 82} while (0)
00f8ff66 83
d8ace44f
RK		 84/* We can not debug without a frame pointer. */
85/* #define CAN_DEBUG_WITHOUT_FP */
0d7e008e 86
cb51ecd2
AO		 87#define CONDITIONAL_REGISTER_USAGE do \
88{ \
89 int regno; \
fa5322fa
AO		 90 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno ++) \
91 if (! VALID_REGISTER_P (regno)) \
92 fixed_regs[regno] = call_used_regs[regno] = 1; \
93 /* R8 and R9 are call-clobbered on SH5, but not on earlier SH ABIs. */ \
94 if (TARGET_SH5) \
95 call_used_regs[FIRST_GENERAL_REG + 8] \
96 = call_used_regs[FIRST_GENERAL_REG + 9] = 1; \
97 if (TARGET_SHMEDIA) \
225e4f43 98 { \
fa5322fa
AO		 99 regno_reg_class[FIRST_GENERAL_REG] = GENERAL_REGS; \
100 CLEAR_HARD_REG_SET (reg_class_contents[FP0_REGS]); \
101 regno_reg_class[FIRST_FP_REG] = FP_REGS; \
225e4f43 102 } \
1a66cd67 103 if (flag_pic) \
6915629f 104 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
c8f0269d 105 /* Renesas saves and restores mac registers on call. */ \
aff2c066 106 if (TARGET_HITACHI && ! TARGET_NOMACSAVE) \
225e4f43
R		 107 { \
108 call_used_regs[MACH_REG] = 0; \
109 call_used_regs[MACL_REG] = 0; \
cb51ecd2 110 } \
0ac78517
R		 111 for (regno = FIRST_FP_REG + (TARGET_LITTLE_ENDIAN != 0); \
112 regno <= LAST_FP_REG; regno += 2) \
113 SET_HARD_REG_BIT (reg_class_contents[DF_HI_REGS], regno); \
fa5322fa
AO		 114 if (TARGET_SHMEDIA) \
115 { \
116 for (regno = FIRST_TARGET_REG; regno <= LAST_TARGET_REG; regno ++)\
117 if (! fixed_regs[regno] && call_used_regs[regno]) \
118 SET_HARD_REG_BIT (reg_class_contents[SIBCALL_REGS], regno); \
119 } \
120 else \
121 for (regno = FIRST_GENERAL_REG; regno <= LAST_GENERAL_REG; regno++) \
122 if (! fixed_regs[regno] && call_used_regs[regno]) \
123 SET_HARD_REG_BIT (reg_class_contents[SIBCALL_REGS], regno); \
cb51ecd2 124} while (0)
bc45ade3 125\f
85256f8a
JW		 126/* ??? Need to write documentation for all SH options and add it to the
127 invoke.texi file. */
128
994295f2 129/* Run-time compilation parameters selecting different hardware subsets. */
bc45ade3
SC		 130
131extern int target_flags;
0d7e008e 132#define ISIZE_BIT (1<<1)
0d7e008e 133#define DALIGN_BIT (1<<6)
0d7e008e
SC		 134#define SH1_BIT (1<<8)
135#define SH2_BIT (1<<9)
136#define SH3_BIT (1<<10)
3a8699c7 137#define SH_E_BIT (1<<11)
225e4f43
R		 138#define HARD_SH4_BIT (1<<5)
139#define FPU_SINGLE_BIT (1<<7)
140#define SH4_BIT (1<<12)
141#define FMOVD_BIT (1<<4)
fa5322fa 142#define SH5_BIT (1<<0)
0d7e008e
SC		 143#define SPACE_BIT (1<<13)
144#define BIGTABLE_BIT (1<<14)
8b32b684 145#define RELAX_BIT (1<<15)
93ca1662 146#define USERMODE_BIT (1<<16)
0d7e008e 147#define HITACHI_BIT (1<<22)
aff2c066 148#define NOMACSAVE_BIT (1<<23)
1a66cd67 149#define PREFERGOT_BIT (1<<24)
9791111f 150#define PADSTRUCT_BIT (1<<28)
00f8ff66 151#define LITTLE_ENDIAN_BIT (1<<29)
e9a25f70 152#define IEEE_BIT (1<<30)
fe3ad572 153#define SAVE_ALL_TR_BIT (1<<2)
b9654711 154
1bc7c5b6
ZW		 155/* Nonzero if this is an ELF target - compile time only */
156#define TARGET_ELF 0
157
c5d67833
JW		 158/* Nonzero if we should dump out instruction size info. */
159#define TARGET_DUMPISIZE (target_flags & ISIZE_BIT)
160
161/* Nonzero to align doubles on 64 bit boundaries. */
162#define TARGET_ALIGN_DOUBLE (target_flags & DALIGN_BIT)
163
994295f2 164/* Nonzero if we should generate code using type 1 insns. */
b9654711
SC		 165#define TARGET_SH1 (target_flags & SH1_BIT)
166
994295f2 167/* Nonzero if we should generate code using type 2 insns. */
b9654711 168#define TARGET_SH2 (target_flags & SH2_BIT)
bc45ade3 169
3a8699c7
AO		 170/* Nonzero if we should generate code using type 2E insns. */
171#define TARGET_SH2E ((target_flags & SH_E_BIT) && TARGET_SH2)
172
994295f2 173/* Nonzero if we should generate code using type 3 insns. */
b9654711 174#define TARGET_SH3 (target_flags & SH3_BIT)
bc45ade3 175
5c3ea805 176/* Nonzero if we should generate code using type 3E insns. */
3a8699c7 177#define TARGET_SH3E ((target_flags & SH_E_BIT) && TARGET_SH3)
5c3ea805 178
6f317ef3 179/* Nonzero if the cache line size is 32. */
fa5322fa 180#define TARGET_CACHE32 (target_flags & HARD_SH4_BIT || TARGET_SH5)
225e4f43 181
6f317ef3 182/* Nonzero if we schedule for a superscalar implementation. */
225e4f43
R		 183#define TARGET_SUPERSCALAR (target_flags & HARD_SH4_BIT)
184
185/* Nonzero if the target has separate instruction and data caches. */
0aa54da2 186#define TARGET_HARVARD (target_flags & HARD_SH4_BIT)
225e4f43
R		 187
188/* Nonzero if compiling for SH4 hardware (to be used for insn costs etc.) */
189#define TARGET_HARD_SH4 (target_flags & HARD_SH4_BIT)
190
191/* Nonzero if the default precision of th FPU is single */
192#define TARGET_FPU_SINGLE (target_flags & FPU_SINGLE_BIT)
193
fa5322fa
AO		 194/* Nonzero if a double-precision FPU is available. */
195#define TARGET_FPU_DOUBLE (target_flags & SH4_BIT)
196
197/* Nonzero if an FPU is available. */
3a8699c7 198#define TARGET_FPU_ANY (TARGET_SH2E || TARGET_FPU_DOUBLE)
fa5322fa 199
225e4f43 200/* Nonzero if we should generate code using type 4 insns. */
fa5322fa
AO		 201#define TARGET_SH4 ((target_flags & SH4_BIT) && (target_flags & SH1_BIT))
202
203/* Nonzero if we should generate code for a SH5 CPU (either ISA). */
204#define TARGET_SH5 (target_flags & SH5_BIT)
205
206/* Nonzero if we should generate code using the SHcompact instruction
207 set and 32-bit ABI. */
208#define TARGET_SHCOMPACT (TARGET_SH5 && TARGET_SH1)
209
210/* Nonzero if we should generate code using the SHmedia instruction
211 set and ABI. */
212#define TARGET_SHMEDIA (TARGET_SH5 && ! TARGET_SH1)
225e4f43 213
fa5322fa
AO		 214/* Nonzero if we should generate code using the SHmedia ISA and 32-bit
215 ABI. */
216#define TARGET_SHMEDIA32 (TARGET_SH5 && ! TARGET_SH1 \
3a8699c7 217 && (target_flags & SH_E_BIT))
fa5322fa
AO		 218
219/* Nonzero if we should generate code using the SHmedia ISA and 64-bit
220 ABI. */
221#define TARGET_SHMEDIA64 (TARGET_SH5 && ! TARGET_SH1 \
3a8699c7 222 && ! (target_flags & SH_E_BIT))
fa5322fa
AO		 223
224/* Nonzero if we should generate code using SHmedia FPU instructions. */
225#define TARGET_SHMEDIA_FPU (TARGET_SHMEDIA && TARGET_FPU_DOUBLE)
225e4f43
R		 226/* Nonzero if we should generate fmovd. */
227#define TARGET_FMOVD (target_flags & FMOVD_BIT)
228
e9a25f70
JL		 229/* Nonzero if we respect NANs. */
230#define TARGET_IEEE (target_flags & IEEE_BIT)
231
994295f2 232/* Nonzero if we should generate smaller code rather than faster code. */
b9654711
SC		 233#define TARGET_SMALLCODE (target_flags & SPACE_BIT)
234
994295f2 235/* Nonzero to use long jump tables. */
0d7e008e 236#define TARGET_BIGTABLE (target_flags & BIGTABLE_BIT)
b9654711 237
8b32b684
JW		 238/* Nonzero to generate pseudo-ops needed by the assembler and linker
239 to do function call relaxing. */
240#define TARGET_RELAX (target_flags & RELAX_BIT)
241
c8f0269d 242/* Nonzero if using Renesas's calling convention. */
d3ae8277 243#define TARGET_HITACHI (target_flags & HITACHI_BIT)
8e87e161 244
aff2c066
R		 245/* Nonzero if not saving macl/mach when using -mhitachi */
246#define TARGET_NOMACSAVE (target_flags & NOMACSAVE_BIT)
247
9791111f 248/* Nonzero if padding structures to a multiple of 4 bytes. This is
c8f0269d 249 incompatible with Renesas's compiler, and gives unusual structure layouts
9791111f
JW		 250 which confuse programmers.
251 ??? This option is not useful, but is retained in case there are people
252 who are still relying on it. It may be deleted in the future. */
253#define TARGET_PADSTRUCT (target_flags & PADSTRUCT_BIT)
00f8ff66 254
c5d67833 255/* Nonzero if generating code for a little endian SH. */
00f8ff66
SC		 256#define TARGET_LITTLE_ENDIAN (target_flags & LITTLE_ENDIAN_BIT)
257
93ca1662
NY		 258/* Nonzero if we should do everything in userland. */
259#define TARGET_USERMODE (target_flags & USERMODE_BIT)
260
1a66cd67
AO		 261/* Nonzero if we should prefer @GOT calls when generating PIC. */
262#define TARGET_PREFERGOT (target_flags & PREFERGOT_BIT)
263
fe3ad572
SC		 264#define TARGET_SAVE_ALL_TARGET_REGS (target_flags & SAVE_ALL_TR_BIT)
265
49616835
JR		 266/* This is not used by the SH2E calling convention */
267#define TARGET_VARARGS_PRETEND_ARGS(FUN_DECL) \
268 (TARGET_SH1 && ! TARGET_SH2E && ! TARGET_SH5 \
269 && ! (TARGET_HITACHI || sh_attr_renesas_p (FUN_DECL)))
270
da28a3b9
JR		 271#ifndef TARGET_CPU_DEFAULT
272#define TARGET_CPU_DEFAULT SELECT_SH1
273#define SUPPORT_SH1
274#define SUPPORT_SH2E
275#define SUPPORT_SH4
276#define SUPPORT_SH4_SINGLE
277#endif
278
3a8699c7
AO		 279#define SELECT_SH1 (SH1_BIT)
280#define SELECT_SH2 (SH2_BIT | SELECT_SH1)
281#define SELECT_SH2E (SH_E_BIT | SH2_BIT | SH1_BIT | FPU_SINGLE_BIT)
282#define SELECT_SH3 (SH3_BIT | SELECT_SH2)
283#define SELECT_SH3E (SH_E_BIT | FPU_SINGLE_BIT | SELECT_SH3)
284#define SELECT_SH4_NOFPU (HARD_SH4_BIT | SELECT_SH3)
285#define SELECT_SH4_SINGLE_ONLY (HARD_SH4_BIT | SELECT_SH3E)
286#define SELECT_SH4 (SH4_BIT | SH_E_BIT | HARD_SH4_BIT | SELECT_SH3)
287#define SELECT_SH4_SINGLE (FPU_SINGLE_BIT | SELECT_SH4)
da28a3b9
JR		 288#define SELECT_SH5_64MEDIA (SH5_BIT | SH4_BIT)
289#define SELECT_SH5_64MEDIA_NOFPU (SH5_BIT)
290#define SELECT_SH5_32MEDIA (SH5_BIT | SH4_BIT | SH_E_BIT)
291#define SELECT_SH5_32MEDIA_NOFPU (SH5_BIT | SH_E_BIT)
3a8699c7 292#define SELECT_SH5_COMPACT (SH5_BIT | SH4_BIT | SELECT_SH3E)
8bc6e101
R		 293#define SELECT_SH5_COMPACT_NOFPU (SH5_BIT | SELECT_SH3)
294
da28a3b9
JR		 295/* Disable processor switches for which we have no suitable multilibs. */
296#ifndef SUPPORT_SH1
297#define TARGET_SWITCH_SH1
298#ifndef SUPPORT_SH2
299#define TARGET_SWITCH_SH2
300#ifndef SUPPORT_SH3
301#define TARGET_SWITCH_SH3
302#ifndef SUPPORT_SH4_NOFPU
303#define TARGET_SWITCH_SH4_NOFPU
304#endif
305#endif
306#endif
307#endif
308
309#ifndef SUPPORT_SH2E
310#define TARGET_SWITCH_SH2E
311#ifndef SUPPORT_SH3E
312#define TARGET_SWITCH_SH3E
313#ifndef SUPPORT_SH4_SINGLE_ONLY
314#define TARGET_SWITCH_SH4_SINGLE_ONLY
315#endif
316#endif
317#endif
318
319#ifndef SUPPORT_SH4
320#define TARGET_SWITCH_SH4
321#endif
322
323#ifndef SUPPORT_SH4_SINGLE
324#define TARGET_SWITCH_SH4_SINGLE
325#endif
326
327#ifndef SUPPORT_SH5_64MEDIA
328#define TARGET_SWITCH_SH5_64MEDIA
329#endif
330
331#ifndef SUPPORT_SH5_64MEDIA_NOFPU
332#define TARGET_SWITCH_SH5_64MEDIA_NOFPU
333#endif
334
335#if !defined(SUPPORT_SH5_32MEDIA) && !defined (SUPPORT_SH5_COMPACT)
336#define TARGET_SWITCHES_SH5_32MEDIA
337#endif
338
339#if !defined(SUPPORT_SH5_32MEDIA_NOFPU) && !defined (SUPPORT_SH5_COMPACT_NOFPU)
340#define TARGET_SWITCHES_SH5_32MEDIA_NOFPU
341#endif
342
ae010e43 343/* Reset all target-selection flags. */
3a8699c7 344#define TARGET_NONE -(SH1_BIT | SH2_BIT | SH3_BIT | SH_E_BIT | SH4_BIT \
fa5322fa 345 | HARD_SH4_BIT | FPU_SINGLE_BIT | SH5_BIT)
ae010e43 346
da28a3b9
JR		 347#ifndef TARGET_SWITCH_SH1
348#define TARGET_SWITCH_SH1 \
349 {"1", TARGET_NONE, "" }, \
350 {"1", SELECT_SH1, "Generate SH1 code" },
351#endif
352#ifndef TARGET_SWITCH_SH2
353#define TARGET_SWITCH_SH2 \
354 {"2", TARGET_NONE, "" }, \
355 {"2", SELECT_SH2, "Generate SH2 code" },
356#endif
357#ifndef TARGET_SWITCH_SH2E
358#define TARGET_SWITCH_SH2E \
359 {"2e", TARGET_NONE, "" }, \
360 {"2e", SELECT_SH2E, "Generate SH2e code" },
361#endif
362#ifndef TARGET_SWITCH_SH3
363#define TARGET_SWITCH_SH3 \
364 {"3", TARGET_NONE, "" }, \
365 {"3", SELECT_SH3, "Generate SH3 code" },
366#endif
367#ifndef TARGET_SWITCH_SH3E
368#define TARGET_SWITCH_SH3E \
369 {"3e", TARGET_NONE, "" }, \
370 {"3e", SELECT_SH3E, "Generate SH3e code" },
371#endif
372#ifndef TARGET_SWITCH_SH4_SINGLE_ONLY
373#define TARGET_SWITCH_SH4_SINGLE_ONLY \
374 {"4-single-only", TARGET_NONE, "" }, \
375 {"4-single-only", SELECT_SH4_SINGLE_ONLY, "Generate only single-precision SH4 code" },
376#endif
377#ifndef TARGET_SWITCH_SH4_SINGLE
378#define TARGET_SWITCH_SH4_SINGLE \
379 {"4-single", TARGET_NONE, "" }, \
380 {"4-single", SELECT_SH4_SINGLE, "Generate default single-precision SH4 code" },
381#endif
382#ifndef TARGET_SWITCH_SH4_NOFPU
383#define TARGET_SWITCH_SH4_NOFPU \
384 {"4-nofpu", TARGET_NONE, "" }, \
385 {"4-nofpu", SELECT_SH4_NOFPU, "Generate SH4 FPU-less code" },
386#endif
387#ifndef TARGET_SWITCH_SH4
388#define TARGET_SWITCH_SH4 \
389 {"4", TARGET_NONE, "" }, \
390 {"4", SELECT_SH4, "Generate SH4 code" },
391#endif
392#ifndef TARGET_SWITCH_SH5_64MEDIA
393#define TARGET_SWITCH_SH5_64MEDIA \
fa5322fa 394 {"5-64media", TARGET_NONE, "" }, \
da28a3b9
JR		 395 {"5-64media", SELECT_SH5_64MEDIA, "Generate 64-bit SHmedia code" },
396#endif
397#ifndef TARGET_SWITCH_SH5_64MEDIA_NOFPU
398#define TARGET_SWITCH_SH5_64MEDIA_NOFPU \
fa5322fa 399 {"5-64media-nofpu", TARGET_NONE, "" }, \
da28a3b9
JR		 400 {"5-64media-nofpu", SELECT_SH5_64MEDIA_NOFPU, "Generate 64-bit FPU-less SHmedia code" },
401#endif
402#ifndef TARGET_SWITCHES_SH5_32MEDIA
403#define TARGET_SWITCHES_SH5_32MEDIA \
fa5322fa 404 {"5-32media", TARGET_NONE, "" }, \
da28a3b9 405 {"5-32media", SELECT_SH5_32MEDIA, "Generate 32-bit SHmedia code" }, \
fa5322fa 406 {"5-compact", TARGET_NONE, "" }, \
da28a3b9
JR		 407 {"5-compact", SELECT_SH5_COMPACT, "Generate SHcompact code" },
408#endif
409#ifndef TARGET_SWITCHES_SH5_32MEDIA_NOFPU
410#define TARGET_SWITCHES_SH5_32MEDIA_NOFPU \
411 {"5-32media-nofpu", TARGET_NONE, "" }, \
412 {"5-32media-nofpu", SELECT_SH5_32MEDIA_NOFPU, "Generate 32-bit FPU-less SHmedia code" }, \
fa5322fa 413 {"5-compact-nofpu", TARGET_NONE, "" }, \
da28a3b9
JR		 414 {"5-compact-nofpu", SELECT_SH5_COMPACT_NOFPU, "Generate FPU-less SHcompact code" },
415#endif
416
417#define TARGET_SWITCHES \
418{ TARGET_SWITCH_SH1 \
419 TARGET_SWITCH_SH2 \
420 TARGET_SWITCH_SH2E \
421 TARGET_SWITCH_SH3 \
422 TARGET_SWITCH_SH3E \
423 TARGET_SWITCH_SH4_SINGLE_ONLY \
424 TARGET_SWITCH_SH4_SINGLE \
425 TARGET_SWITCH_SH4_NOFPU \
426 TARGET_SWITCH_SH4 \
427 TARGET_SWITCH_SH5_64MEDIA \
428 TARGET_SWITCH_SH5_64MEDIA_NOFPU \
429 TARGET_SWITCHES_SH5_32MEDIA \
430 TARGET_SWITCHES_SH5_32MEDIA_NOFPU \
04213688
RB		 431 {"b", -LITTLE_ENDIAN_BIT, "Generate code in big endian mode" }, \
432 {"bigtable", BIGTABLE_BIT, "Generate 32-bit offsets in switch tables" }, \
433 {"dalign", DALIGN_BIT, "Aligns doubles at 64-bit boundaries" }, \
ae010e43 434 {"fmovd", FMOVD_BIT, "" }, \
04213688 435 {"hitachi", HITACHI_BIT, "Follow Renesas (formerly Hitachi) / SuperH calling conventions" }, \
61f71b34 436 {"renesas", HITACHI_BIT, "Follow Renesas (formerly Hitachi) / SuperH calling conventions" }, \
04213688
RB		 437 {"nomacsave", NOMACSAVE_BIT, "Mark MAC register as call-clobbered" }, \
438 {"ieee", IEEE_BIT, "Increase the IEEE compliance for floating-point code" }, \
ae010e43 439 {"isize", ISIZE_BIT, "" }, \
04213688 440 {"l", LITTLE_ENDIAN_BIT, "Generate code in little endian mode" }, \
ae010e43
AO		 441 {"no-ieee", -IEEE_BIT, "" }, \
442 {"padstruct", PADSTRUCT_BIT, "" }, \
04213688
RB		 443 {"prefergot", PREFERGOT_BIT, "Emit function-calls using global offset table when generating PIC" }, \
444 {"relax", RELAX_BIT, "Shorten address references during linking" }, \
445 {"space", SPACE_BIT, "Deprecated. Use -Os instead" }, \
446 {"usermode", USERMODE_BIT, "Generate library function call to invalidate instruction cache entries after fixing trampoline" }, \
5d84b57e 447 SUBTARGET_SWITCHES \
ae010e43 448 {"", TARGET_DEFAULT, "" } \
bc45ade3
SC		 449}
450
5d84b57e
JS		 451/* This are meant to be redefined in the host dependent files */
452#define SUBTARGET_SWITCHES
453
f1a58d92
R		 454/* This defaults us to big-endian. */
455#ifndef TARGET_ENDIAN_DEFAULT
456#define TARGET_ENDIAN_DEFAULT 0
457#endif
458
da28a3b9
JR		 459#define TARGET_DEFAULT (TARGET_CPU_DEFAULT|TARGET_ENDIAN_DEFAULT)
460
461#ifndef SH_MULTILIB_CPU_DEFAULT
462#define SH_MULTILIB_CPU_DEFAULT "m1"
8bc6e101
R		 463#endif
464
da28a3b9
JR		 465#if TARGET_ENDIAN_DEFAULT
466#define MULTILIB_DEFAULTS { "ml", SH_MULTILIB_CPU_DEFAULT }
467#else
468#define MULTILIB_DEFAULTS { "mb", SH_MULTILIB_CPU_DEFAULT }
469#endif
f1a58d92
R		 470
471#define CPP_SPEC " %(subtarget_cpp_spec) "
472
473#ifndef SUBTARGET_CPP_SPEC
474#define SUBTARGET_CPP_SPEC ""
475#endif
476
6a79bb0a
JT		 477#ifndef SUBTARGET_EXTRA_SPECS
478#define SUBTARGET_EXTRA_SPECS
479#endif
480
f1a58d92
R		 481#define EXTRA_SPECS \
482 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
483 { "link_emul_prefix", LINK_EMUL_PREFIX }, \
484 { "link_default_cpu_emul", LINK_DEFAULT_CPU_EMUL }, \
485 { "subtarget_link_emul_suffix", SUBTARGET_LINK_EMUL_SUFFIX }, \
486 { "subtarget_link_spec", SUBTARGET_LINK_SPEC }, \
6a79bb0a 487 { "subtarget_asm_endian_spec", SUBTARGET_ASM_ENDIAN_SPEC }, \
d44cc404
R		 488 { "subtarget_asm_relax_spec", SUBTARGET_ASM_RELAX_SPEC }, \
489 { "subtarget_asm_isa_spec", SUBTARGET_ASM_ISA_SPEC }, \
6a79bb0a 490 SUBTARGET_EXTRA_SPECS
f1a58d92 491
d44cc404 492#if TARGET_CPU_DEFAULT & HARD_SH4_BIT
04953ac9 493#define SUBTARGET_ASM_RELAX_SPEC "%{!m1:%{!m2:%{!m3*:%{!m5*:-isa=sh4}}}}"
d44cc404
R		 494#else
495#define SUBTARGET_ASM_RELAX_SPEC "%{m4*:-isa=sh4}"
496#endif
497
498#define SH_ASM_SPEC \
499 "%(subtarget_asm_endian_spec) %{mrelax:-relax %(subtarget_asm_relax_spec)}\
500%(subtarget_asm_isa_spec)"
501
502#define ASM_SPEC SH_ASM_SPEC
f1a58d92
R		 503
504#ifndef SUBTARGET_ASM_ENDIAN_SPEC
505#if TARGET_ENDIAN_DEFAULT == LITTLE_ENDIAN_BIT
506#define SUBTARGET_ASM_ENDIAN_SPEC "%{mb:-big} %{!mb:-little}"
507#else
508#define SUBTARGET_ASM_ENDIAN_SPEC "%{ml:-little} %{!ml:-big}"
509#endif
510#endif
511
d44cc404
R		 512#define SUBTARGET_ASM_ISA_SPEC ""
513
f1a58d92 514#define LINK_EMUL_PREFIX "sh%{ml:l}"
8bc6e101
R		 515
516#if TARGET_CPU_DEFAULT & SH5_BIT
3a8699c7 517#if TARGET_CPU_DEFAULT & SH_E_BIT
8bc6e101 518#define LINK_DEFAULT_CPU_EMUL "32"
da28a3b9
JR		 519#if TARGET_CPU_DEFAULT & SH1_BIT
520#define ASM_ISA_SPEC_DEFAULT "--isa=SHcompact"
8bc6e101 521#else
da28a3b9
JR		 522#define ASM_ISA_SPEC_DEFAULT "--isa=SHmedia --abi=32"
523#endif /* SH1_BIT */
524#else /* !SH_E_BIT */
8bc6e101 525#define LINK_DEFAULT_CPU_EMUL "64"
da28a3b9 526#define ASM_ISA_SPEC_DEFAULT "--isa=SHmedia --abi=64"
3a8699c7 527#endif /* SH_E_BIT */
da28a3b9
JR		 528#define ASM_ISA_DEFAULT_SPEC \
529" %{!m1:%{!m2*:%{!m3*:%{!m4*:%{!m5*:" ASM_ISA_SPEC_DEFAULT "}}}}}"
530#else /* !SH5_BIT */
f1a58d92 531#define LINK_DEFAULT_CPU_EMUL ""
da28a3b9 532#define ASM_ISA_DEFAULT_SPEC ""
8bc6e101
R		 533#endif /* SH5_BIT */
534
f1a58d92
R		 535#define SUBTARGET_LINK_EMUL_SUFFIX ""
536#define SUBTARGET_LINK_SPEC ""
537
538/* svr4.h redefines LINK_SPEC inappropriately, so go via SH_LINK_SPEC,
539 so that we can undo the damage without code replication. */
540#define LINK_SPEC SH_LINK_SPEC
541
542#define SH_LINK_SPEC "\
543-m %(link_emul_prefix)\
544%{m5-compact*|m5-32media*:32}\
545%{m5-64media*:64}\
546%{!m1:%{!m2:%{!m3*:%{!m4*:%{!m5*:%(link_default_cpu_emul)}}}}}\
547%(subtarget_link_emul_suffix) \
548%{mrelax:-relax} %(subtarget_link_spec)"
00f8ff66 549
04d02ece
R		 550#define OPTIMIZATION_OPTIONS(LEVEL,SIZE) \
551do { \
225e4f43
R		 552 if (LEVEL) \
553 flag_omit_frame_pointer = -1; \
04d02ece
R		 554 if (SIZE) \
555 target_flags |= SPACE_BIT; \
fe3ad572
SC		 556 if (TARGET_SHMEDIA && LEVEL > 1) \
557 { \
558 flag_branch_target_load_optimize = 1; \
559 if (! (SIZE)) \
560 target_flags |= SAVE_ALL_TR_BIT; \
561 } \
04d02ece
R		 562} while (0)
563
225e4f43
R		 564#define ASSEMBLER_DIALECT assembler_dialect
565
566extern int assembler_dialect;
567
568#define OVERRIDE_OPTIONS \
569do { \
fa5322fa
AO		 570 int regno; \
571 \
225e4f43
R		 572 sh_cpu = CPU_SH1; \
573 assembler_dialect = 0; \
574 if (TARGET_SH2) \
575 sh_cpu = CPU_SH2; \
3a8699c7
AO		 576 if (TARGET_SH2E) \
577 sh_cpu = CPU_SH2E; \
225e4f43
R		 578 if (TARGET_SH3) \
579 sh_cpu = CPU_SH3; \
580 if (TARGET_SH3E) \
581 sh_cpu = CPU_SH3E; \
582 if (TARGET_SH4) \
583 { \
584 assembler_dialect = 1; \
585 sh_cpu = CPU_SH4; \
586 } \
fa5322fa
AO		 587 if (TARGET_SH5) \
588 { \
589 sh_cpu = CPU_SH5; \
590 target_flags |= DALIGN_BIT; \
701e3726
R		 591 if (TARGET_FPU_ANY \
592 && ! (TARGET_SHCOMPACT && TARGET_LITTLE_ENDIAN)) \
fa5322fa
AO		 593 target_flags |= FMOVD_BIT; \
594 if (TARGET_SHMEDIA) \
595 { \
596 /* There are no delay slots on SHmedia. */ \
597 flag_delayed_branch = 0; \
598 /* Relaxation isn't yet supported for SHmedia */ \
599 target_flags &= ~RELAX_BIT; \
600 } \
90534361
R		 601 /* -fprofile-arcs needs a working libgcov . In unified tree \
602 configurations with newlib, this requires to configure with \
603 --with-newlib --with-headers. But there is no way to check \
604 here we have a working libgcov, so just assume that we have. */\
605 if (profile_flag) \
fa5322fa
AO		 606 { \
607 warning ("Profiling is not supported on this target."); \
608 profile_flag = profile_arc_flag = 0; \
609 } \
610 } \
611 else \
225e4f43 612 { \
fa5322fa
AO		 613 /* Only the sh64-elf assembler fully supports .quad properly. */\
614 targetm.asm_out.aligned_op.di = NULL; \
615 targetm.asm_out.unaligned_op.di = NULL; \
225e4f43 616 } \
ec555f32 617 if (TARGET_FMOVD) \
a93d1ba2 618 reg_class_from_letter['e' - 'a'] = NO_REGS; \
fa5322fa
AO		 619 \
620 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) \
621 if (! VALID_REGISTER_P (regno)) \
622 sh_register_names[regno][0] = '\0'; \
623 \
624 for (regno = 0; regno < ADDREGNAMES_SIZE; regno++) \
625 if (! VALID_REGISTER_P (ADDREGNAMES_REGNO (regno))) \
626 sh_additional_register_names[regno][0] = '\0'; \
627 \
225e4f43 628 if (flag_omit_frame_pointer < 0) \
cfe1cd40
AH		 629 { \
630 /* The debugging information is sufficient, \
631 but gdb doesn't implement this yet */ \
632 if (0) \
633 flag_omit_frame_pointer \
634 = (PREFERRED_DEBUGGING_TYPE == DWARF_DEBUG \
635 || PREFERRED_DEBUGGING_TYPE == DWARF2_DEBUG); \
636 else \
637 flag_omit_frame_pointer = 0; \
638 } \
225e4f43 639 \
4979c2a9 640 if (flag_pic && ! TARGET_PREFERGOT) \
1a66cd67
AO		 641 flag_no_function_cse = 1; \
642 \
e2c734c1
R		 643 if (SMALL_REGISTER_CLASSES) \
644 { \
645 /* Never run scheduling before reload, since that can \
646 break global alloc, and generates slower code anyway due \
647 to the pressure on R0. */ \
58565a33
SKG		 648 /* Enable sched1 for SH4; ready queue will be reordered by \
649 the target hooks when pressure is high. We can not do this for \
650 SH3 and lower as they give spill failures for R0. */ \
651 if (!TARGET_HARD_SH4) \
652 flag_schedule_insns = 0; \
e2c734c1 653 } \
58ab7171 654 \
10f4f635
R		 655 if (align_loops == 0) \
656 align_loops = 1 << (TARGET_SH5 ? 3 : 2); \
657 if (align_jumps == 0) \
658 align_jumps = 1 << CACHE_LOG; \
bb182d23
R		 659 else if (align_jumps < (TARGET_SHMEDIA ? 4 : 2)) \
660 align_jumps = TARGET_SHMEDIA ? 4 : 2; \
10f4f635 661 \
0b0ad147 662 /* Allocation boundary (in *bytes*) for the code of a function. \
58ab7171
R		 663 SH1: 32 bit alignment is faster, because instructions are always \
664 fetched as a pair from a longword boundary. \
665 SH2 .. SH5 : align to cache line start. */ \
666 if (align_functions == 0) \
667 align_functions \
0b0ad147 668 = TARGET_SMALLCODE ? FUNCTION_BOUNDARY/8 : (1 << CACHE_LOG); \
10f4f635
R		 669 /* The linker relaxation code breaks when a function contains \
670 alignments that are larger than that at the start of a \
671 compilation unit. */ \
672 if (TARGET_RELAX) \
673 { \
674 int min_align \
675 = align_loops > align_jumps ? align_loops : align_jumps; \
676 \
677 /* Also take possible .long constants / mova tables int account. */\
678 if (min_align < 4) \
679 min_align = 4; \
680 if (align_functions < min_align) \
681 align_functions = min_align; \
682 } \
0d7e008e 683} while (0)
bc45ade3 684\f
c5d67833 685/* Target machine storage layout. */
bc45ade3
SC		 686
687/* Define this if most significant bit is lowest numbered
688 in instructions that operate on numbered bit-fields. */
00f8ff66 689
bc45ade3
SC		 690#define BITS_BIG_ENDIAN 0
691
692/* Define this if most significant byte of a word is the lowest numbered. */
00f8ff66 693#define BYTES_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
bc45ade3
SC		 694
695/* Define this if most significant word of a multiword number is the lowest
696 numbered. */
00f8ff66
SC		 697#define WORDS_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
698
00f8ff66
SC		 699/* Define this to set the endianness to use in libgcc2.c, which can
700 not depend on target_flags. */
701#if defined(__LITTLE_ENDIAN__)
702#define LIBGCC2_WORDS_BIG_ENDIAN 0
703#else
704#define LIBGCC2_WORDS_BIG_ENDIAN 1
705#endif
bc45ade3 706
fa5322fa
AO		 707#define MAX_BITS_PER_WORD 64
708
fa5322fa 709/* Width in bits of an `int'. We want just 32-bits, even if words are
24746a42 710 longer. */
fa5322fa
AO		 711#define INT_TYPE_SIZE 32
712
713/* Width in bits of a `long'. */
714#define LONG_TYPE_SIZE (TARGET_SHMEDIA64 ? 64 : 32)
715
716/* Width in bits of a `long long'. */
717#define LONG_LONG_TYPE_SIZE 64
718
719/* Width in bits of a `long double'. */
720#define LONG_DOUBLE_TYPE_SIZE 64
bc45ade3
SC		 721
722/* Width of a word, in units (bytes). */
fa5322fa
AO		 723#define UNITS_PER_WORD (TARGET_SHMEDIA ? 8 : 4)
724#define MIN_UNITS_PER_WORD 4
bc45ade3 725
fada1961
R		 726/* Scaling factor for Dwarf data offsets for CFI information.
727 The dwarf2out.c default would use -UNITS_PER_WORD, which is -8 for
728 SHmedia; however, since we do partial register saves for the registers
729 visible to SHcompact, and for target registers for SHMEDIA32, we have
730 to allow saves that are only 4-byte aligned. */
731#define DWARF_CIE_DATA_ALIGNMENT -4
732
bc45ade3
SC		 733/* Width in bits of a pointer.
734 See also the macro `Pmode' defined below. */
fa5322fa 735#define POINTER_SIZE (TARGET_SHMEDIA64 ? 64 : 32)
bc45ade3
SC		 736
737/* Allocation boundary (in *bits*) for storing arguments in argument list. */
fa5322fa 738#define PARM_BOUNDARY (TARGET_SH5 ? 64 : 32)
bc45ade3
SC		 739
740/* Boundary (in *bits*) on which stack pointer should be aligned. */
3d5a0820 741#define STACK_BOUNDARY BIGGEST_ALIGNMENT
bc45ade3 742
e9a25f70 743/* The log (base 2) of the cache line size, in bytes. Processors prior to
b4d34be1
R		 744 SH2 have no actual cache, but they fetch code in chunks of 4 bytes.
745 The SH2/3 have 16 byte cache lines, and the SH4 has a 32 byte cache line */
746#define CACHE_LOG (TARGET_CACHE32 ? 5 : TARGET_SH2 ? 4 : 2)
e9a25f70 747
58ab7171
R		 748/* ABI given & required minimum allocation boundary (in *bits*) for the
749 code of a function. */
750#define FUNCTION_BOUNDARY (16 << TARGET_SHMEDIA)
fa5322fa
AO		 751
752/* On SH5, the lowest bit is used to indicate SHmedia functions, so
753 the vbit must go into the delta field of
754 pointers-to-member-functions. */
755#define TARGET_PTRMEMFUNC_VBIT_LOCATION \
756 (TARGET_SH5 ? ptrmemfunc_vbit_in_delta : ptrmemfunc_vbit_in_pfn)
bc45ade3
SC		 757
758/* Alignment of field after `int : 0' in a structure. */
759#define EMPTY_FIELD_BOUNDARY 32
760
761/* No data type wants to be aligned rounder than this. */
762#define BIGGEST_ALIGNMENT (TARGET_ALIGN_DOUBLE ? 64 : 32)
763
764/* The best alignment to use in cases where we have a choice. */
fa5322fa 765#define FASTEST_ALIGNMENT (TARGET_SH5 ? 64 : 32)
bc45ade3 766
bc45ade3 767/* Make strings word-aligned so strcpy from constants will be faster. */
c5d67833 768#define CONSTANT_ALIGNMENT(EXP, ALIGN) \
bc45ade3
SC		 769 ((TREE_CODE (EXP) == STRING_CST \
770 && (ALIGN) < FASTEST_ALIGNMENT) \
0d7e008e 771 ? FASTEST_ALIGNMENT : (ALIGN))
bc45ade3 772
1bf93c14
R		 773/* get_mode_alignment assumes complex values are always held in multiple
774 registers, but that is not the case on the SH; CQImode and CHImode are
775 held in a single integer register. SH5 also holds CSImode and SCmode
fae778eb 776 values in integer registers. This is relevant for argument passing on
9218882a 777 SHcompact as we use a stack temp in order to pass CSImode by reference. */
1bf93c14
R		 778#define LOCAL_ALIGNMENT(TYPE, ALIGN) \
779 ((GET_MODE_CLASS (TYPE_MODE (TYPE)) == MODE_COMPLEX_INT \
780 || GET_MODE_CLASS (TYPE_MODE (TYPE)) == MODE_COMPLEX_FLOAT) \
fada1961
R		 781 ? (unsigned) MIN (BIGGEST_ALIGNMENT, GET_MODE_BITSIZE (TYPE_MODE (TYPE))) \
782 : (unsigned) ALIGN)
1bf93c14 783
bc45ade3
SC		 784/* Make arrays of chars word-aligned for the same reasons. */
785#define DATA_ALIGNMENT(TYPE, ALIGN) \
786 (TREE_CODE (TYPE) == ARRAY_TYPE \
787 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
788 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
789
8e87e161
SC		 790/* Number of bits which any structure or union's size must be a
791 multiple of. Each structure or union's size is rounded up to a
994295f2 792 multiple of this. */
9791111f 793#define STRUCTURE_SIZE_BOUNDARY (TARGET_PADSTRUCT ? 32 : 8)
8e87e161 794
bc45ade3
SC		 795/* Set this nonzero if move instructions will actually fail to work
796 when given unaligned data. */
797#define STRICT_ALIGNMENT 1
33f7f353
JR		 798
799/* If LABEL_AFTER_BARRIER demands an alignment, return its base 2 logarithm. */
800#define LABEL_ALIGN_AFTER_BARRIER(LABEL_AFTER_BARRIER) \
801 barrier_align (LABEL_AFTER_BARRIER)
802
77008a44 803#define LOOP_ALIGN(A_LABEL) \
2148624a
R		 804 ((! optimize || TARGET_HARVARD || TARGET_SMALLCODE) \
805 ? 0 : sh_loop_align (A_LABEL))
33f7f353
JR		 806
807#define LABEL_ALIGN(A_LABEL) \
808( \
809 (PREV_INSN (A_LABEL) \
810 && GET_CODE (PREV_INSN (A_LABEL)) == INSN \
811 && GET_CODE (PATTERN (PREV_INSN (A_LABEL))) == UNSPEC_VOLATILE \
f6f1dc95 812 && XINT (PATTERN (PREV_INSN (A_LABEL)), 1) == UNSPECV_ALIGN) \
6f317ef3 813 /* explicit alignment insn in constant tables. */ \
33f7f353
JR		 814 ? INTVAL (XVECEXP (PATTERN (PREV_INSN (A_LABEL)), 0, 0)) \
815 : 0)
816
817/* Jump tables must be 32 bit aligned, no matter the size of the element. */
818#define ADDR_VEC_ALIGN(ADDR_VEC) 2
819
820/* The base two logarithm of the known minimum alignment of an insn length. */
821#define INSN_LENGTH_ALIGNMENT(A_INSN) \
822 (GET_CODE (A_INSN) == INSN \
fa5322fa 823 ? 1 << TARGET_SHMEDIA \
33f7f353 824 : GET_CODE (A_INSN) == JUMP_INSN || GET_CODE (A_INSN) == CALL_INSN \
fa5322fa 825 ? 1 << TARGET_SHMEDIA \
33f7f353 826 : CACHE_LOG)
bc45ade3
SC		 827\f
828/* Standard register usage. */
829
c8f0269d 830/* Register allocation for the Renesas calling convention:
bc45ade3 831
0d7e008e
SC		 832 r0 arg return
833 r1..r3 scratch
c5d67833 834 r4..r7 args in
0d7e008e
SC		 835 r8..r13 call saved
836 r14 frame pointer/call saved
bc45ade3
SC		 837 r15 stack pointer
838 ap arg pointer (doesn't really exist, always eliminated)
839 pr subroutine return address
840 t t bit
994295f2 841 mach multiply/accumulate result, high part
5c3ea805
JW		 842 macl multiply/accumulate result, low part.
843 fpul fp/int communication register
d1405d89 844 rap return address pointer register
5c3ea805
JW		 845 fr0 fp arg return
846 fr1..fr3 scratch floating point registers
847 fr4..fr11 fp args in
848 fr12..fr15 call saved floating point registers */
bc45ade3 849
fa5322fa
AO		 850#define MAX_REGISTER_NAME_LENGTH 5
851extern char sh_register_names[][MAX_REGISTER_NAME_LENGTH + 1];
852
853#define SH_REGISTER_NAMES_INITIALIZER \
854{ \
855 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
856 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
857 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", \
858 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", \
859 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39", \
860 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47", \
861 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55", \
862 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63", \
863 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", \
864 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", \
865 "fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", "fr23", \
866 "fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31", \
867 "fr32", "fr33", "fr34", "fr35", "fr36", "fr37", "fr38", "fr39", \
868 "fr40", "fr41", "fr42", "fr43", "fr44", "fr45", "fr46", "fr47", \
869 "fr48", "fr49", "fr50", "fr51", "fr52", "fr53", "fr54", "fr55", \
870 "fr56", "fr57", "fr58", "fr59", "fr60", "fr61", "fr62", "fr63", \
871 "tr0", "tr1", "tr2", "tr3", "tr4", "tr5", "tr6", "tr7", \
872 "xd0", "xd2", "xd4", "xd6", "xd8", "xd10", "xd12", "xd14", \
873 "gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", \
874 "rap" \
875}
876
fa5322fa
AO		 877#define REGNAMES_ARR_INDEX_1(index) \
878 (sh_register_names[index])
879#define REGNAMES_ARR_INDEX_2(index) \
880 REGNAMES_ARR_INDEX_1 ((index)), REGNAMES_ARR_INDEX_1 ((index)+1)
881#define REGNAMES_ARR_INDEX_4(index) \
882 REGNAMES_ARR_INDEX_2 ((index)), REGNAMES_ARR_INDEX_2 ((index)+2)
883#define REGNAMES_ARR_INDEX_8(index) \
884 REGNAMES_ARR_INDEX_4 ((index)), REGNAMES_ARR_INDEX_4 ((index)+4)
885#define REGNAMES_ARR_INDEX_16(index) \
886 REGNAMES_ARR_INDEX_8 ((index)), REGNAMES_ARR_INDEX_8 ((index)+8)
887#define REGNAMES_ARR_INDEX_32(index) \
888 REGNAMES_ARR_INDEX_16 ((index)), REGNAMES_ARR_INDEX_16 ((index)+16)
889#define REGNAMES_ARR_INDEX_64(index) \
890 REGNAMES_ARR_INDEX_32 ((index)), REGNAMES_ARR_INDEX_32 ((index)+32)
891
892#define REGISTER_NAMES \
893{ \
894 REGNAMES_ARR_INDEX_64 (0), \
895 REGNAMES_ARR_INDEX_64 (64), \
896 REGNAMES_ARR_INDEX_8 (128), \
897 REGNAMES_ARR_INDEX_8 (136), \
898 REGNAMES_ARR_INDEX_8 (144), \
899 REGNAMES_ARR_INDEX_1 (152) \
900}
901
902#define ADDREGNAMES_SIZE 32
903#define MAX_ADDITIONAL_REGISTER_NAME_LENGTH 4
904extern char sh_additional_register_names[ADDREGNAMES_SIZE] \
905 [MAX_ADDITIONAL_REGISTER_NAME_LENGTH + 1];
906
907#define SH_ADDITIONAL_REGISTER_NAMES_INITIALIZER \
908{ \
909 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14", \
910 "dr16", "dr18", "dr20", "dr22", "dr24", "dr26", "dr28", "dr30", \
911 "dr32", "dr34", "dr36", "dr38", "dr40", "dr42", "dr44", "dr46", \
912 "dr48", "dr50", "dr52", "dr54", "dr56", "dr58", "dr60", "dr62" \
913}
914
915#define ADDREGNAMES_REGNO(index) \
916 ((index < 32) ? (FIRST_FP_REG + (index) * 2) \
917 : (-1))
918
919#define ADDREGNAMES_ARR_INDEX_1(index) \
920 { (sh_additional_register_names[index]), ADDREGNAMES_REGNO (index) }
921#define ADDREGNAMES_ARR_INDEX_2(index) \
922 ADDREGNAMES_ARR_INDEX_1 ((index)), ADDREGNAMES_ARR_INDEX_1 ((index)+1)
923#define ADDREGNAMES_ARR_INDEX_4(index) \
924 ADDREGNAMES_ARR_INDEX_2 ((index)), ADDREGNAMES_ARR_INDEX_2 ((index)+2)
925#define ADDREGNAMES_ARR_INDEX_8(index) \
926 ADDREGNAMES_ARR_INDEX_4 ((index)), ADDREGNAMES_ARR_INDEX_4 ((index)+4)
927#define ADDREGNAMES_ARR_INDEX_16(index) \
928 ADDREGNAMES_ARR_INDEX_8 ((index)), ADDREGNAMES_ARR_INDEX_8 ((index)+8)
929#define ADDREGNAMES_ARR_INDEX_32(index) \
930 ADDREGNAMES_ARR_INDEX_16 ((index)), ADDREGNAMES_ARR_INDEX_16 ((index)+16)
931
932#define ADDITIONAL_REGISTER_NAMES \
933{ \
934 ADDREGNAMES_ARR_INDEX_32 (0) \
935}
936
bc45ade3
SC		 937/* Number of actual hardware registers.
938 The hardware registers are assigned numbers for the compiler
939 from 0 to just below FIRST_PSEUDO_REGISTER.
940 All registers that the compiler knows about must be given numbers,
994295f2 941 even those that are not normally considered general registers. */
bc45ade3 942
4773afa4
AO		 943/* There are many other relevant definitions in sh.md's md_constants. */
944
945#define FIRST_GENERAL_REG R0_REG
fa5322fa 946#define LAST_GENERAL_REG (FIRST_GENERAL_REG + (TARGET_SHMEDIA ? 63 : 15))
4773afa4 947#define FIRST_FP_REG DR0_REG
fa5322fa 948#define LAST_FP_REG (FIRST_FP_REG + \
3a8699c7 949 (TARGET_SHMEDIA_FPU ? 63 : TARGET_SH2E ? 15 : -1))
4773afa4 950#define FIRST_XD_REG XD0_REG
fa5322fa
AO		 951#define LAST_XD_REG (FIRST_XD_REG + ((TARGET_SH4 && TARGET_FMOVD) ? 7 : -1))
952#define FIRST_TARGET_REG TR0_REG
953#define LAST_TARGET_REG (FIRST_TARGET_REG + (TARGET_SHMEDIA ? 7 : -1))
4773afa4 954
104ee20b 955#define GENERAL_REGISTER_P(REGNO) \
fada1961
R		 956 IN_RANGE ((REGNO), \
957 (unsigned HOST_WIDE_INT) FIRST_GENERAL_REG, \
958 (unsigned HOST_WIDE_INT) LAST_GENERAL_REG)
104ee20b
AO		 959
960#define GENERAL_OR_AP_REGISTER_P(REGNO) \
961 (GENERAL_REGISTER_P (REGNO) || ((REGNO) == AP_REG))
962
963#define FP_REGISTER_P(REGNO) \
fada1961 964 ((int) (REGNO) >= FIRST_FP_REG && (int) (REGNO) <= LAST_FP_REG)
104ee20b
AO		 965
966#define XD_REGISTER_P(REGNO) \
fada1961 967 ((int) (REGNO) >= FIRST_XD_REG && (int) (REGNO) <= LAST_XD_REG)
104ee20b
AO		 968
969#define FP_OR_XD_REGISTER_P(REGNO) \
970 (FP_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO))
971
972#define FP_ANY_REGISTER_P(REGNO) \
973 (FP_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO) || (REGNO) == FPUL_REG)
974
975#define SPECIAL_REGISTER_P(REGNO) \
4773afa4
AO		 976 ((REGNO) == GBR_REG || (REGNO) == T_REG \
977 || (REGNO) == MACH_REG || (REGNO) == MACL_REG)
bc45ade3 978
fa5322fa 979#define TARGET_REGISTER_P(REGNO) \
fada1961 980 ((int) (REGNO) >= FIRST_TARGET_REG && (int) (REGNO) <= LAST_TARGET_REG)
fa5322fa
AO		 981
982#define SHMEDIA_REGISTER_P(REGNO) \
983 (GENERAL_REGISTER_P (REGNO) || FP_REGISTER_P (REGNO) \
984 || TARGET_REGISTER_P (REGNO))
985
986/* This is to be used in CONDITIONAL_REGISTER_USAGE, to mark registers
987 that should be fixed. */
988#define VALID_REGISTER_P(REGNO) \
989 (SHMEDIA_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO) \
990 || (REGNO) == AP_REG || (REGNO) == RAP_REG \
991 || (TARGET_SH1 && (SPECIAL_REGISTER_P (REGNO) || (REGNO) == PR_REG)) \
3a8699c7 992 || (TARGET_SH2E && (REGNO) == FPUL_REG))
fa5322fa
AO		 993
994/* The mode that should be generally used to store a register by
995 itself in the stack, or to load it back. */
996#define REGISTER_NATURAL_MODE(REGNO) \
997 (FP_REGISTER_P (REGNO) ? SFmode \
998 : XD_REGISTER_P (REGNO) ? DFmode \
a138247b
AO		 999 : TARGET_SHMEDIA && ! HARD_REGNO_CALL_PART_CLOBBERED ((REGNO), DImode) \
1000 ? DImode \
1001 : SImode)
fa5322fa
AO		 1002
1003#define FIRST_PSEUDO_REGISTER 153
bc45ade3
SC		 1004
1005/* 1 for registers that have pervasive standard uses
994295f2 1006 and are not available for the register allocator.
d3ae8277 1007
97b65a3e
JW		 1008 Mach register is fixed 'cause it's only 10 bits wide for SH1.
1009 It is 32 bits wide for SH2. */
d3ae8277 1010
fa5322fa
AO		 1011#define FIXED_REGISTERS \
1012{ \
1013/* Regular registers. */ \
1014 0, 0, 0, 0, 0, 0, 0, 0, \
1015 0, 0, 0, 0, 0, 0, 0, 1, \
1016 /* r16 is reserved, r18 is the former pr. */ \
1017 1, 0, 0, 0, 0, 0, 0, 0, \
1018 /* r24 is reserved for the OS; r25, for the assembler or linker. */ \
1019 /* r26 is a global variable data pointer; r27 is for constants. */ \
1020 1, 1, 1, 1, 0, 0, 0, 0, \
1021 0, 0, 0, 0, 0, 0, 0, 0, \
1022 0, 0, 0, 0, 0, 0, 0, 0, \
1023 0, 0, 0, 0, 0, 0, 0, 0, \
1024 0, 0, 0, 0, 0, 0, 0, 1, \
1025/* FP registers. */ \
1026 0, 0, 0, 0, 0, 0, 0, 0, \
1027 0, 0, 0, 0, 0, 0, 0, 0, \
1028 0, 0, 0, 0, 0, 0, 0, 0, \
1029 0, 0, 0, 0, 0, 0, 0, 0, \
1030 0, 0, 0, 0, 0, 0, 0, 0, \
1031 0, 0, 0, 0, 0, 0, 0, 0, \
1032 0, 0, 0, 0, 0, 0, 0, 0, \
1033 0, 0, 0, 0, 0, 0, 0, 0, \
1034/* Branch target registers. */ \
1035 0, 0, 0, 0, 0, 0, 0, 0, \
1036/* XD registers. */ \
1037 0, 0, 0, 0, 0, 0, 0, 0, \
1038/*"gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", */ \
1039 1, 1, 1, 1, 1, 1, 0, 1, \
1040/*"rap" */ \
1041 1, \
5c3ea805 1042}
bc45ade3
SC		 1043
1044/* 1 for registers not available across function calls.
1045 These must include the FIXED_REGISTERS and also any
1046 registers that can be used without being saved.
1047 The latter must include the registers where values are returned
1048 and the register where structure-value addresses are passed.
1049 Aside from that, you can include as many other registers as you like. */
1050
fa5322fa
AO		 1051#define CALL_USED_REGISTERS \
1052{ \
1053/* Regular registers. */ \
1054 1, 1, 1, 1, 1, 1, 1, 1, \
1055 /* R8 and R9 are call-clobbered on SH5, but not on earlier SH ABIs. \
1056 Only the lower 32bits of R10-R14 are guaranteed to be preserved \
1057 across SH5 function calls. */ \
1058 0, 0, 0, 0, 0, 0, 0, 1, \
97b3d0f0 1059 1, 1, 1, 1, 1, 1, 1, 1, \
fa5322fa
AO		 1060 1, 1, 1, 1, 0, 0, 0, 0, \
1061 0, 0, 0, 0, 1, 1, 1, 1, \
1062 1, 1, 1, 1, 0, 0, 0, 0, \
1063 0, 0, 0, 0, 0, 0, 0, 0, \
1064 0, 0, 0, 0, 1, 1, 1, 1, \
1065/* FP registers. */ \
1066 1, 1, 1, 1, 1, 1, 1, 1, \
1067 1, 1, 1, 1, 0, 0, 0, 0, \
1068 1, 1, 1, 1, 1, 1, 1, 1, \
1069 1, 1, 1, 1, 1, 1, 1, 1, \
1070 1, 1, 1, 1, 0, 0, 0, 0, \
1071 0, 0, 0, 0, 0, 0, 0, 0, \
1072 0, 0, 0, 0, 0, 0, 0, 0, \
1073 0, 0, 0, 0, 0, 0, 0, 0, \
1074/* Branch target registers. */ \
1075 1, 1, 1, 1, 1, 0, 0, 0, \
1076/* XD registers. */ \
1077 1, 1, 1, 1, 1, 1, 0, 0, \
1078/*"gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", */ \
97b3d0f0 1079 1, 1, 1, 1, 1, 1, 1, 1, \
fa5322fa
AO		 1080/*"rap" */ \
1081 1, \
5c3ea805 1082}
bc45ade3 1083
fa5322fa
AO		 1084/* Only the lower 32-bits of R10-R14 are guaranteed to be preserved
1085 across SHcompact function calls. We can't tell whether a called
1086 function is SHmedia or SHcompact, so we assume it may be when
1087 compiling SHmedia code with the 32-bit ABI, since that's the only
1088 ABI that can be linked with SHcompact code. */
1089#define HARD_REGNO_CALL_PART_CLOBBERED(REGNO,MODE) \
1090 (TARGET_SHMEDIA32 \
1091 && GET_MODE_SIZE (MODE) > 4 \
a138247b 1092 && (((REGNO) >= FIRST_GENERAL_REG + 10 \
fada1961
R		 1093 && (REGNO) <= FIRST_GENERAL_REG + 15) \
1094 || TARGET_REGISTER_P (REGNO) \
a138247b 1095 || (REGNO) == PR_MEDIA_REG))
fa5322fa 1096
bc45ade3
SC		 1097/* Return number of consecutive hard regs needed starting at reg REGNO
1098 to hold something of mode MODE.
1099 This is ordinarily the length in words of a value of mode MODE
1100 but can be less for certain modes in special long registers.
1101
225e4f43 1102 On the SH all but the XD regs are UNITS_PER_WORD bits wide. */
0d7e008e 1103
c5d67833 1104#define HARD_REGNO_NREGS(REGNO, MODE) \
104ee20b 1105 (XD_REGISTER_P (REGNO) \
9bcd9715 1106 ? ((GET_MODE_SIZE (MODE) + (2*UNITS_PER_WORD - 1)) / (2*UNITS_PER_WORD)) \
fa5322fa
AO		 1107 : (TARGET_SHMEDIA && FP_REGISTER_P (REGNO)) \
1108 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD/2 - 1) / (UNITS_PER_WORD/2)) \
9bcd9715 1109 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
bc45ade3
SC		 1110
1111/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
058f9bb5
JW		 1112 We can allow any mode in any general register. The special registers
1113 only allow SImode. Don't allow any mode in the PR. */
bc45ade3 1114
225e4f43
R		 1115/* We cannot hold DCmode values in the XD registers because alter_reg
1116 handles subregs of them incorrectly. We could work around this by
1117 spacing the XD registers like the DR registers, but this would require
1118 additional memory in every compilation to hold larger register vectors.
1119 We could hold SFmode / SCmode values in XD registers, but that
1120 would require a tertiary reload when reloading from / to memory,
1121 and a secondary reload to reload from / to general regs; that
1122 seems to be a loosing proposition. */
0ac78517
R		 1123/* We want to allow TImode FP regs so that when V4SFmode is loaded as TImode,
1124 it won't be ferried through GP registers first. */
c5d67833 1125#define HARD_REGNO_MODE_OK(REGNO, MODE) \
104ee20b 1126 (SPECIAL_REGISTER_P (REGNO) ? (MODE) == SImode \
5c3ea805 1127 : (REGNO) == FPUL_REG ? (MODE) == SImode || (MODE) == SFmode \
104ee20b 1128 : FP_REGISTER_P (REGNO) && (MODE) == SFmode \
225e4f43 1129 ? 1 \
fa5322fa 1130 : (MODE) == V2SFmode \
0ac78517 1131 ? ((FP_REGISTER_P (REGNO) && ((REGNO) - FIRST_FP_REG) % 2 == 0) \
ec555f32 1132 || GENERAL_REGISTER_P (REGNO)) \
fa5322fa 1133 : (MODE) == V4SFmode \
ec555f32
R		 1134 ? ((FP_REGISTER_P (REGNO) && ((REGNO) - FIRST_FP_REG) % 4 == 0) \
1135 || (! TARGET_SHMEDIA && GENERAL_REGISTER_P (REGNO))) \
fa5322fa
AO		 1136 : (MODE) == V16SFmode \
1137 ? (TARGET_SHMEDIA \
1138 ? (FP_REGISTER_P (REGNO) && ((REGNO) - FIRST_FP_REG) % 16 == 0) \
1139 : (REGNO) == FIRST_XD_REG) \
104ee20b 1140 : FP_REGISTER_P (REGNO) \
ec555f32 1141 ? ((MODE) == SFmode || (MODE) == SImode \
3a8699c7 1142 || ((TARGET_SH2E || TARGET_SHMEDIA) && (MODE) == SCmode) \
fa5322fa
AO		 1143 || (((TARGET_SH4 && (MODE) == DFmode) || (MODE) == DCmode \
1144 || (TARGET_SHMEDIA && ((MODE) == DFmode || (MODE) == DImode \
0ac78517 1145 || (MODE) == V2SFmode || (MODE) == TImode))) \
225e4f43 1146 && (((REGNO) - FIRST_FP_REG) & 1) == 0)) \
104ee20b 1147 : XD_REGISTER_P (REGNO) \
225e4f43 1148 ? (MODE) == DFmode \
fa5322fa
AO		 1149 : TARGET_REGISTER_P (REGNO) \
1150 ? ((MODE) == DImode || (MODE) == SImode) \
b869f904 1151 : (REGNO) == PR_REG ? (MODE) == SImode \
225e4f43 1152 : (REGNO) == FPSCR_REG ? (MODE) == PSImode \
058f9bb5 1153 : 1)
bc45ade3 1154
fa5322fa
AO		 1155/* Value is 1 if MODE is a supported vector mode. */
1156#define VECTOR_MODE_SUPPORTED_P(MODE) \
c1b92d09
R		 1157 ((TARGET_FPU_ANY \
1158 && ((MODE) == V2SFmode || (MODE) == V4SFmode || (MODE) == V16SFmode)) \
1159 || (TARGET_SHMEDIA \
1160 && ((MODE) == V8QImode || (MODE) == V2HImode || (MODE) == V4HImode \
1161 || (MODE) == V2SImode)))
fa5322fa 1162
bc45ade3
SC		 1163/* Value is 1 if it is a good idea to tie two pseudo registers
1164 when one has mode MODE1 and one has mode MODE2.
1165 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
93a77848
AO		 1166 for any hard reg, then this must be 0 for correct output.
1167 That's the case for xd registers: we don't hold SFmode values in
1168 them, so we can't tie an SFmode pseudos with one in another
1169 floating-point mode. */
bc45ade3
SC		 1170
1171#define MODES_TIEABLE_P(MODE1, MODE2) \
93a77848
AO		 1172 ((MODE1) == (MODE2) \
1173 || (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2) \
fa5322fa
AO		 1174 && (TARGET_SHMEDIA ? ((GET_MODE_SIZE (MODE1) <= 4) \
1175 && (GET_MODE_SIZE (MODE2) <= 4)) \
1176 : ((MODE1) != SFmode && (MODE2) != SFmode))))
bc45ade3 1177
03b8ec29
DD		 1178/* A C expression that is nonzero if hard register NEW_REG can be
1179 considered for use as a rename register for OLD_REG register */
1180
1181#define HARD_REGNO_RENAME_OK(OLD_REG, NEW_REG) \
1182 sh_hard_regno_rename_ok (OLD_REG, NEW_REG)
1183
bc45ade3
SC		 1184/* Specify the registers used for certain standard purposes.
1185 The values of these macros are register numbers. */
1186
1187/* Define this if the program counter is overloaded on a register. */
1188/* #define PC_REGNUM 15*/
1189
1190/* Register to use for pushing function arguments. */
4773afa4 1191#define STACK_POINTER_REGNUM SP_REG
bc45ade3
SC		 1192
1193/* Base register for access to local variables of the function. */
4773afa4 1194#define FRAME_POINTER_REGNUM FP_REG
bc45ade3 1195
d1405d89
JW		 1196/* Fake register that holds the address on the stack of the
1197 current function's return address. */
4773afa4 1198#define RETURN_ADDRESS_POINTER_REGNUM RAP_REG
d1405d89 1199
1a66cd67
AO		 1200/* Register to hold the addressing base for position independent
1201 code access to data items. */
309d8365 1202#define PIC_OFFSET_TABLE_REGNUM (flag_pic ? PIC_REG : INVALID_REGNUM)
1a66cd67
AO		 1203
1204#define GOT_SYMBOL_NAME "*_GLOBAL_OFFSET_TABLE_"
1205
bc45ade3
SC		 1206/* Value should be nonzero if functions must have frame pointers.
1207 Zero means the frame pointer need not be set up (and parms may be accessed
1208 via the stack pointer) in functions that seem suitable. */
b9654711 1209
0d7e008e 1210#define FRAME_POINTER_REQUIRED 0
bc45ade3
SC		 1211
1212/* Definitions for register eliminations.
1213
cc27ef74 1214 We have three registers that can be eliminated on the SH. First, the
bc45ade3
SC		 1215 frame pointer register can often be eliminated in favor of the stack
1216 pointer register. Secondly, the argument pointer register can always be
cc27ef74 1217 eliminated; it is replaced with either the stack or frame pointer.
956d6950 1218 Third, there is the return address pointer, which can also be replaced
cc27ef74 1219 with either the stack or the frame pointer. */
bc45ade3
SC		 1220
1221/* This is an array of structures. Each structure initializes one pair
1222 of eliminable registers. The "from" register number is given first,
1223 followed by "to". Eliminations of the same "from" register are listed
1224 in order of preference. */
1225
cc27ef74
JR		 1226/* If you add any registers here that are not actually hard registers,
1227 and that have any alternative of elimination that doesn't always
1228 apply, you need to amend calc_live_regs to exclude it, because
1229 reload spills all eliminable registers where it sees an
1230 can_eliminate == 0 entry, thus making them 'live' .
1231 If you add any hard registers that can be eliminated in different
1232 ways, you have to patch reload to spill them only when all alternatives
1233 of elimination fail. */
1234
d1405d89
JW		 1235#define ELIMINABLE_REGS \
1236{{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1237 { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1238 { RETURN_ADDRESS_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
1239 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1240 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM},}
bc45ade3
SC		 1241
1242/* Given FROM and TO register numbers, say whether this elimination
1243 is allowed. */
1244#define CAN_ELIMINATE(FROM, TO) \
1245 (!((FROM) == FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED))
1246
1247/* Define the offset between two registers, one to be eliminated, and the other
1248 its replacement, at the start of a routine. */
1249
1250#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
e9a25f70 1251 OFFSET = initial_elimination_offset ((FROM), (TO))
bc45ade3
SC		 1252
1253/* Base register for access to arguments of the function. */
f00018dd 1254#define ARG_POINTER_REGNUM AP_REG
bc45ade3
SC		 1255
1256/* Register in which the static-chain is passed to a function. */
fa5322fa 1257#define STATIC_CHAIN_REGNUM (TARGET_SH5 ? 1 : 3)
bc45ade3 1258
0d7e008e 1259/* Don't default to pcc-struct-return, because we have already specified
bd5bd7ac
KH		 1260 exactly how to return structures in the TARGET_RETURN_IN_MEMORY
1261 target hook. */
0d7e008e
SC		 1262
1263#define DEFAULT_PCC_STRUCT_RETURN 0
fa5322fa
AO		 1264
1265#define SHMEDIA_REGS_STACK_ADJUST() \
1266 (TARGET_SHCOMPACT && current_function_has_nonlocal_label \
1267 ? (8 * (/* r28-r35 */ 8 + /* r44-r59 */ 16 + /* tr5-tr7 */ 3) \
1268 + (TARGET_FPU_ANY ? 4 * (/* fr36 - fr63 */ 28) : 0)) \
1269 : 0)
1270
bc45ade3
SC		 1271\f
1272/* Define the classes of registers for register constraints in the
1273 machine description. Also define ranges of constants.
1274
1275 One of the classes must always be named ALL_REGS and include all hard regs.
1276 If there is more than one class, another class must be named NO_REGS
1277 and contain no registers.
1278
1279 The name GENERAL_REGS must be the name of a class (or an alias for
1280 another name such as ALL_REGS). This is the class of registers
1281 that is allowed by "g" or "r" in a register constraint.
1282 Also, registers outside this class are allocated only when
1283 instructions express preferences for them.
1284
1285 The classes must be numbered in nondecreasing order; that is,
1286 a larger-numbered class must never be contained completely
1287 in a smaller-numbered class.
1288
1289 For any two classes, it is very desirable that there be another
1290 class that represents their union. */
1291
994295f2 1292/* The SH has two sorts of general registers, R0 and the rest. R0 can
bc45ade3
SC		 1293 be used as the destination of some of the arithmetic ops. There are
1294 also some special purpose registers; the T bit register, the
ddd5a7c1 1295 Procedure Return Register and the Multiply Accumulate Registers. */
e9a25f70
JL		 1296/* Place GENERAL_REGS after FPUL_REGS so that it will be preferred by
1297 reg_class_subunion. We don't want to have an actual union class
1298 of these, because it would only be used when both classes are calculated
1299 to give the same cost, but there is only one FPUL register.
1300 Besides, regclass fails to notice the different REGISTER_MOVE_COSTS
1301 applying to the actual instruction alternative considered. E.g., the
1302 y/r alternative of movsi_ie is considered to have no more cost that
1303 the r/r alternative, which is patently untrue. */
bc45ade3
SC		 1304
1305enum reg_class
1306{
1307 NO_REGS,
1308 R0_REGS,
bc45ade3
SC		 1309 PR_REGS,
1310 T_REGS,
1311 MAC_REGS,
5c3ea805 1312 FPUL_REGS,
cb51ecd2 1313 SIBCALL_REGS,
e9a25f70 1314 GENERAL_REGS,
5c3ea805
JW		 1315 FP0_REGS,
1316 FP_REGS,
0ac78517 1317 DF_HI_REGS,
225e4f43
R		 1318 DF_REGS,
1319 FPSCR_REGS,
5c5eb4ef 1320 GENERAL_FP_REGS,
fa5322fa 1321 TARGET_REGS,
bc45ade3
SC		 1322 ALL_REGS,
1323 LIM_REG_CLASSES
1324};
1325
1326#define N_REG_CLASSES (int) LIM_REG_CLASSES
1327
994295f2 1328/* Give names of register classes as strings for dump file. */
c5d67833 1329#define REG_CLASS_NAMES \
bc45ade3
SC		 1330{ \
1331 "NO_REGS", \
1332 "R0_REGS", \
bc45ade3
SC		 1333 "PR_REGS", \
1334 "T_REGS", \
1335 "MAC_REGS", \
5c3ea805 1336 "FPUL_REGS", \
cb51ecd2 1337 "SIBCALL_REGS", \
e9a25f70 1338 "GENERAL_REGS", \
5c3ea805
JW		 1339 "FP0_REGS", \
1340 "FP_REGS", \
0ac78517 1341 "DF_HI_REGS", \
225e4f43
R		 1342 "DF_REGS", \
1343 "FPSCR_REGS", \
5c5eb4ef 1344 "GENERAL_FP_REGS", \
fa5322fa 1345 "TARGET_REGS", \
bc45ade3
SC		 1346 "ALL_REGS", \
1347}
1348
1349/* Define which registers fit in which classes.
1350 This is an initializer for a vector of HARD_REG_SET
1351 of length N_REG_CLASSES. */
1352
fa5322fa
AO		 1353#define REG_CLASS_CONTENTS \
1354{ \
1355/* NO_REGS: */ \
1356 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1357/* R0_REGS: */ \
1358 { 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1359/* PR_REGS: */ \
1360 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00040000 }, \
1361/* T_REGS: */ \
1362 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00080000 }, \
1363/* MAC_REGS: */ \
1364 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00300000 }, \
1365/* FPUL_REGS: */ \
1366 { 0x00000000, 0x00000000, 0x00000000, 0x00000001, 0x00400000 }, \
1367/* SIBCALL_REGS: Initialized in CONDITIONAL_REGISTER_USAGE. */ \
1368 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1369/* GENERAL_REGS: */ \
1370 { 0xffffffff, 0xffffffff, 0x00000000, 0x00000000, 0x01020000 }, \
1371/* FP0_REGS: */ \
1372 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000 }, \
1373/* FP_REGS: */ \
1374 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x00000000 }, \
0ac78517
R		 1375/* DF_HI_REGS: Initialized in CONDITIONAL_REGISTER_USAGE. */ \
1376 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x0000ff00 }, \
fa5322fa
AO		 1377/* DF_REGS: */ \
1378 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x0000ff00 }, \
1379/* FPSCR_REGS: */ \
1380 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00800000 }, \
1381/* GENERAL_FP_REGS: */ \
1382 { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x0102ff00 }, \
1383/* TARGET_REGS: */ \
1384 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000000ff }, \
1385/* ALL_REGS: */ \
1386 { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x01ffffff }, \
73774972 1387}
bc45ade3
SC		 1388
1389/* The same information, inverted:
1390 Return the class number of the smallest class containing
1391 reg number REGNO. This could be a conditional expression
1392 or could index an array. */
1393
fada1961 1394extern enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER];
e9a25f70 1395#define REGNO_REG_CLASS(REGNO) regno_reg_class[(REGNO)]
bc45ade3 1396
0d7e008e
SC		 1397/* When defined, the compiler allows registers explicitly used in the
1398 rtl to be used as spill registers but prevents the compiler from
994295f2 1399 extending the lifetime of these registers. */
0d7e008e 1400
fa5322fa 1401#define SMALL_REGISTER_CLASSES (! TARGET_SHMEDIA)
0d7e008e 1402
bc45ade3 1403/* The order in which register should be allocated. */
e9a25f70
JL		 1404/* Sometimes FP0_REGS becomes the preferred class of a floating point pseudo,
1405 and GENERAL_FP_REGS the alternate class. Since FP0 is likely to be
1406 spilled or used otherwise, we better have the FP_REGS allocated first. */
c5d67833 1407#define REG_ALLOC_ORDER \
1bf93c14
R		 1408 {/* Caller-saved FPRs */ \
1409 65, 66, 67, 68, 69, 70, 71, 64, \
1410 72, 73, 74, 75, 80, 81, 82, 83, \
1411 84, 85, 86, 87, 88, 89, 90, 91, \
1412 92, 93, 94, 95, 96, 97, 98, 99, \
1413 /* Callee-saved FPRs */ \
1414 76, 77, 78, 79,100,101,102,103, \
fa5322fa
AO		 1415 104,105,106,107,108,109,110,111, \
1416 112,113,114,115,116,117,118,119, \
1417 120,121,122,123,124,125,126,127, \
1bf93c14
R		 1418 136,137,138,139,140,141,142,143, \
1419 /* FPSCR */ 151, \
1420 /* Caller-saved GPRs (except 8/9 on SH1-4) */ \
1421 1, 2, 3, 7, 6, 5, 4, 0, \
1422 8, 9, 17, 19, 20, 21, 22, 23, \
1423 36, 37, 38, 39, 40, 41, 42, 43, \
1424 60, 61, 62, \
1425 /* SH1-4 callee-saved saved GPRs / SH5 partially-saved GPRs */ \
1426 10, 11, 12, 13, 14, 18, \
1427 /* SH5 callee-saved GPRs */ \
1428 28, 29, 30, 31, 32, 33, 34, 35, \
1429 44, 45, 46, 47, 48, 49, 50, 51, \
1430 52, 53, 54, 55, 56, 57, 58, 59, \
1431 /* FPUL */ 150, \
1432 /* SH5 branch target registers */ \
fa5322fa 1433 128,129,130,131,132,133,134,135, \
1bf93c14
R		 1434 /* Fixed registers */ \
1435 15, 16, 24, 25, 26, 27, 63,144, \
1436 145,146,147,148,149,152 }
bc45ade3
SC		 1437
1438/* The class value for index registers, and the one for base regs. */
fa5322fa 1439#define INDEX_REG_CLASS (TARGET_SHMEDIA ? GENERAL_REGS : R0_REGS)
bc45ade3
SC		 1440#define BASE_REG_CLASS GENERAL_REGS
1441
994295f2
JW		 1442/* Get reg_class from a letter such as appears in the machine
1443 description. */
ec555f32 1444extern enum reg_class reg_class_from_letter[];
bc45ade3 1445
735cb76e
R		 1446/* We might use 'Rxx' constraints in the future for exotic reg classes.*/
1447#define REG_CLASS_FROM_CONSTRAINT(C, STR) \
1448 (ISLOWER (C) ? reg_class_from_letter[(C)-'a'] : NO_REGS )
c5d67833 1449\f
735cb76e
R		 1450/* Overview of uppercase letter constraints:
1451 A: Addresses (constraint len == 3)
1452 Ac4: sh4 cache operations
1453 Ac5: sh5 cache operations
1454 Bxx: miscellaneous constraints
1455 Bsc: SCRATCH - for the scratch register in movsi_ie in the
1456 fldi0 / fldi0 cases
1457 C: Constants other than only CONST_INT (constraint len == 3)
1458 C16: 16 bit constant, literal or symbolic
1459 Csy: label or symbol
1460 Cpg: non-explicit constants that can be directly loaded into a general
1461 purpose register in PIC code. like 's' except we don't allow
1462 PIC_DIRECT_ADDR_P
1463 IJKLMNOP: CONT_INT constants
1464 Ixx: signed xx bit
1465 J16: 0xffffffff00000000 | 0x00000000ffffffff
1466 Kxx: unsigned xx bit
1467 M: 1
1468 N: 0
1469 P27: 1 | 2 | 8 | 16
1470 Q: pc relative load operand
1471 Rxx: reserved for exotic register classes.
1472 S: extra memory (storage) constraints (constraint len == 3)
1473 Sua: unaligned memory operations
1474 W: vector
1475 Z: zero in any mode
1476
1477 unused CONST_INT constraint letters: LO
1478 unused EXTRA_CONSTRAINT letters: D T U Y */
1479
fae778eb 1480#if 1 /* check that the transition went well. */
735cb76e
R		 1481#define CONSTRAINT_LEN(C,STR) \
1482 (((C) == 'L' || (C) == 'O' || (C) == 'D' || (C) == 'T' || (C) == 'U' \
1483 || (C) == 'Y' \
fada1961
R		 1484 || ((C) == 'I' \
1485 && (((STR)[1] != '0' && (STR)[1] != '1') \
1486 || (STR)[2] < '0' || (STR)[2] > '9')) \
735cb76e
R		 1487 || ((C) == 'B' && ((STR)[1] != 's' || (STR)[2] != 'c')) \
1488 || ((C) == 'J' && ((STR)[1] != '1' || (STR)[2] != '6')) \
1489 || ((C) == 'K' && ((STR)[1] != '0' || (STR)[2] != '8')) \
1490 || ((C) == 'P' && ((STR)[1] != '2' || (STR)[2] != '7'))) \
1491 ? -1 \
1492 : ((C) == 'A' || (C) == 'B' || (C) == 'C' \
1493 || (C) == 'I' || (C) == 'J' || (C) == 'K' || (C) == 'P' \
1494 || (C) == 'R' || (C) == 'S') \
1495 ? 3 \
1496 : DEFAULT_CONSTRAINT_LEN ((C), (STR)))
1497#else
1498#define CONSTRAINT_LEN(C,STR) \
1499 (((C) == 'A' || (C) == 'B' || (C) == 'C' \
1500 || (C) == 'I' || (C) == 'J' || (C) == 'K' || (C) == 'P' \
1501 || (C) == 'R' || (C) == 'S') \
1502 ? 3 : DEFAULT_CONSTRAINT_LEN ((C), (STR)))
1503#endif
1504
bc45ade3
SC		 1505/* The letters I, J, K, L and M in a register constraint string
1506 can be used to stand for particular ranges of immediate operands.
1507 This macro defines what the ranges are.
1508 C is the letter, and VALUE is a constant value.
1509 Return 1 if VALUE is in the range specified by C.
735cb76e
R		 1510 I08: arithmetic operand -127..128, as used in add, sub, etc
1511 I16: arithmetic operand -32768..32767, as used in SHmedia movi and shori
1512 P27: shift operand 1,2,8 or 16
1513 K08: logical operand 0..255, as used in and, or, etc.
bc45ade3 1514 M: constant 1
fa5322fa 1515 N: constant 0
735cb76e
R		 1516 I06: arithmetic operand -32..31, as used in SHmedia beqi, bnei and xori
1517 I10: arithmetic operand -512..511, as used in SHmedia andi, ori
fa5322fa 1518*/
bc45ade3 1519
735cb76e
R		 1520#define CONST_OK_FOR_I06(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -32 \
1521 && ((HOST_WIDE_INT)(VALUE)) <= 31)
1522#define CONST_OK_FOR_I08(VALUE) (((HOST_WIDE_INT)(VALUE))>= -128 \
1523 && ((HOST_WIDE_INT)(VALUE)) <= 127)
1524#define CONST_OK_FOR_I10(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -512 \
1525 && ((HOST_WIDE_INT)(VALUE)) <= 511)
1526#define CONST_OK_FOR_I16(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -32768 \
1527 && ((HOST_WIDE_INT)(VALUE)) <= 32767)
1528#define CONST_OK_FOR_I(VALUE, STR) \
1529 ((STR)[1] == '0' && (STR)[2] == 6 ? CONST_OK_FOR_I06 (VALUE) \
1530 : (STR)[1] == '0' && (STR)[2] == '8' ? CONST_OK_FOR_I08 (VALUE) \
1531 : (STR)[1] == '1' && (STR)[2] == '0' ? CONST_OK_FOR_I10 (VALUE) \
1532 : (STR)[1] == '1' && (STR)[2] == '6' ? CONST_OK_FOR_I16 (VALUE) \
1533 : 0)
1534
1535#define CONST_OK_FOR_J16(VALUE) \
fdc88a4d 1536 (HOST_BITS_PER_WIDE_INT >= 64 && (VALUE) == (HOST_WIDE_INT) 0xffffffff \
735cb76e
R		 1537 || (HOST_BITS_PER_WIDE_INT >= 64 && (VALUE) == (HOST_WIDE_INT) -1 << 32))
1538#define CONST_OK_FOR_J(VALUE, STR) \
1539 ((STR)[1] == '1' && (STR)[2] == '6' ? CONST_OK_FOR_J16 (VALUE) \
1540 : 0)
1541
1542#define CONST_OK_FOR_K08(VALUE) (((HOST_WIDE_INT)(VALUE))>= 0 \
1543 && ((HOST_WIDE_INT)(VALUE)) <= 255)
1544#define CONST_OK_FOR_K(VALUE, STR) \
1545 ((STR)[1] == '0' && (STR)[2] == '8' ? CONST_OK_FOR_K08 (VALUE) \
1546 : 0)
1547#define CONST_OK_FOR_P27(VALUE) \
1548 ((VALUE)==1||(VALUE)==2||(VALUE)==8||(VALUE)==16)
1549#define CONST_OK_FOR_P(VALUE, STR) \
1550 ((STR)[1] == '2' && (STR)[2] == '7' ? CONST_OK_FOR_P27 (VALUE) \
1551 : 0)
bc45ade3 1552#define CONST_OK_FOR_M(VALUE) ((VALUE)==1)
0d7e008e 1553#define CONST_OK_FOR_N(VALUE) ((VALUE)==0)
735cb76e
R		 1554#define CONST_OK_FOR_CONSTRAINT_P(VALUE, C, STR) \
1555 ((C) == 'I' ? CONST_OK_FOR_I ((VALUE), (STR)) \
1556 : (C) == 'J' ? CONST_OK_FOR_J ((VALUE), (STR)) \
1557 : (C) == 'K' ? CONST_OK_FOR_K ((VALUE), (STR)) \
1558 : (C) == 'M' ? CONST_OK_FOR_M (VALUE) \
1559 : (C) == 'N' ? CONST_OK_FOR_N (VALUE) \
1560 : (C) == 'P' ? CONST_OK_FOR_P ((VALUE), (STR)) \
bc45ade3
SC		 1561 : 0)
1562
1563/* Similar, but for floating constants, and defining letters G and H.
1564 Here VALUE is the CONST_DOUBLE rtx itself. */
1565
9f09b1f2
R		 1566#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
1567((C) == 'G' ? (fp_zero_operand (VALUE) && fldi_ok ()) \
1568 : (C) == 'H' ? (fp_one_operand (VALUE) && fldi_ok ()) \
b1bbe732 1569 : (C) == 'F')
5c3ea805 1570
bc45ade3
SC		 1571/* Given an rtx X being reloaded into a reg required to be
1572 in class CLASS, return the class of reg to actually use.
1573 In general this is just CLASS; but on some machines
1574 in some cases it is preferable to use a more restrictive class. */
1575
fa5322fa
AO		 1576#define PREFERRED_RELOAD_CLASS(X, CLASS) \
1577 ((CLASS) == NO_REGS && TARGET_SHMEDIA \
1578 && (GET_CODE (X) == CONST_DOUBLE \
1579 || GET_CODE (X) == SYMBOL_REF) \
1580 ? GENERAL_REGS \
1581 : (CLASS)) \
bc45ade3 1582
0f68f06b 1583#define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,X) \
ec555f32
R		 1584 ((((REGCLASS_HAS_FP_REG (CLASS) \
1585 && (GET_CODE (X) == REG \
1586 && (GENERAL_OR_AP_REGISTER_P (REGNO (X)) \
1587 || (FP_REGISTER_P (REGNO (X)) && (MODE) == SImode \
1588 && TARGET_FMOVD)))) \
1589 || (REGCLASS_HAS_GENERAL_REG (CLASS) \
e9a25f70 1590 && GET_CODE (X) == REG \
104ee20b 1591 && FP_REGISTER_P (REGNO (X)))) \
fa5322fa 1592 && ! TARGET_SHMEDIA \
ec555f32 1593 && ((MODE) == SFmode || (MODE) == SImode)) \
e9a25f70 1594 ? FPUL_REGS \
ec555f32
R		 1595 : (((CLASS) == FPUL_REGS \
1596 || (REGCLASS_HAS_FP_REG (CLASS) \
1597 && ! TARGET_SHMEDIA && MODE == SImode)) \
e9a25f70 1598 && (GET_CODE (X) == MEM \
fc39d371
AH		 1599 || (GET_CODE (X) == REG \
1600 && (REGNO (X) >= FIRST_PSEUDO_REGISTER \
0c4c9b16 1601 || REGNO (X) == T_REG \
fc39d371 1602 || system_reg_operand (X, VOIDmode))))) \
e9a25f70 1603 ? GENERAL_REGS \
fa5322fa
AO		 1604 : ((CLASS) == TARGET_REGS \
1605 || (TARGET_SHMEDIA && (CLASS) == SIBCALL_REGS)) \
1606 ? ((target_operand ((X), (MODE)) \
1607 && ! target_reg_operand ((X), (MODE))) \
1608 ? NO_REGS : GENERAL_REGS) \
e9a25f70 1609 : (((CLASS) == MAC_REGS || (CLASS) == PR_REGS) \
104ee20b 1610 && GET_CODE (X) == REG && ! GENERAL_REGISTER_P (REGNO (X)) \
e9a25f70 1611 && (CLASS) != REGNO_REG_CLASS (REGNO (X))) \
0ac78517
R		 1612 ? GENERAL_REGS \
1613 : ((CLASS) != GENERAL_REGS && GET_CODE (X) == REG \
1614 && TARGET_REGISTER_P (REGNO (X))) \
e9a25f70 1615 ? GENERAL_REGS : NO_REGS)
0f68f06b
JR		 1616
1617#define SECONDARY_INPUT_RELOAD_CLASS(CLASS,MODE,X) \
ec555f32 1618 ((REGCLASS_HAS_FP_REG (CLASS) \
fa5322fa 1619 && ! TARGET_SHMEDIA \
e9a25f70 1620 && immediate_operand ((X), (MODE)) \
9f09b1f2
R		 1621 && ! ((fp_zero_operand (X) || fp_one_operand (X)) \
1622 && (MODE) == SFmode && fldi_ok ())) \
225e4f43 1623 ? R0_REGS \
0c4c9b16
BS		 1624 : (CLASS == FPUL_REGS \
1625 && ((GET_CODE (X) == REG \
bb182d23
R		 1626 && (REGNO (X) == MACL_REG || REGNO (X) == MACH_REG \
1627 || REGNO (X) == T_REG)) \
1628 || GET_CODE (X) == PLUS)) \
0c4c9b16 1629 ? GENERAL_REGS \
225e4f43 1630 : CLASS == FPUL_REGS && immediate_operand ((X), (MODE)) \
735cb76e 1631 ? (GET_CODE (X) == CONST_INT && CONST_OK_FOR_I08 (INTVAL (X)) \
225e4f43
R		 1632 ? GENERAL_REGS \
1633 : R0_REGS) \
1634 : (CLASS == FPSCR_REGS \
1635 && ((GET_CODE (X) == REG && REGNO (X) >= FIRST_PSEUDO_REGISTER) \
318881c0 1636 || (GET_CODE (X) == MEM && GET_CODE (XEXP ((X), 0)) == PLUS)))\
225e4f43 1637 ? GENERAL_REGS \
ec555f32 1638 : (REGCLASS_HAS_FP_REG (CLASS) \
0ac78517
R		 1639 && TARGET_SHMEDIA \
1640 && immediate_operand ((X), (MODE)) \
1641 && (X) != CONST0_RTX (GET_MODE (X)) \
1642 && GET_MODE (X) != V4SFmode) \
1643 ? GENERAL_REGS \
225e4f43 1644 : SECONDARY_OUTPUT_RELOAD_CLASS((CLASS),(MODE),(X)))
0f68f06b 1645
bc45ade3 1646/* Return the maximum number of consecutive registers
994295f2 1647 needed to represent mode MODE in a register of class CLASS.
bc45ade3 1648
3620944c
RS		 1649 If TARGET_SHMEDIA, we need two FP registers per word.
1650 Otherwise we will need at most one register per word. */
c5d67833 1651#define CLASS_MAX_NREGS(CLASS, MODE) \
3620944c
RS		 1652 (TARGET_SHMEDIA \
1653 && TEST_HARD_REG_BIT (reg_class_contents[CLASS], FIRST_FP_REG) \
1654 ? (GET_MODE_SIZE (MODE) + UNITS_PER_WORD/2 - 1) / (UNITS_PER_WORD/2) \
1655 : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
225e4f43
R		 1656
1657/* If defined, gives a class of registers that cannot be used as the
02188693 1658 operand of a SUBREG that changes the mode of the object illegally. */
0ac78517
R		 1659/* ??? We need to renumber the internal numbers for the frnn registers
1660 when in little endian in order to allow mode size changes. */
225e4f43 1661
b0c42aed
JH		 1662#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1663 sh_cannot_change_mode_class (FROM, TO, CLASS)
bc45ade3
SC		 1664\f
1665/* Stack layout; function entry, exit and calling. */
1666
c5d67833 1667/* Define the number of registers that can hold parameters.
5c3ea805
JW		 1668 These macros are used only in other macro definitions below. */
1669
1670#define NPARM_REGS(MODE) \
fa5322fa
AO		 1671 (TARGET_FPU_ANY && (MODE) == SFmode \
1672 ? (TARGET_SH5 ? 12 : 8) \
225e4f43
R		 1673 : TARGET_SH4 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1674 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
fa5322fa
AO		 1675 ? (TARGET_SH5 ? 12 : 8) \
1676 : (TARGET_SH5 ? 8 : 4))
5c3ea805 1677
fa5322fa
AO		 1678#define FIRST_PARM_REG (FIRST_GENERAL_REG + (TARGET_SH5 ? 2 : 4))
1679#define FIRST_RET_REG (FIRST_GENERAL_REG + (TARGET_SH5 ? 2 : 0))
bc45ade3 1680
fa5322fa 1681#define FIRST_FP_PARM_REG (FIRST_FP_REG + (TARGET_SH5 ? 0 : 4))
5c3ea805
JW		 1682#define FIRST_FP_RET_REG FIRST_FP_REG
1683
bc45ade3
SC		 1684/* Define this if pushing a word on the stack
1685 makes the stack pointer a smaller address. */
994295f2 1686#define STACK_GROWS_DOWNWARD
bc45ade3 1687
0d7e008e
SC		 1688/* Define this macro if the addresses of local variable slots are at
1689 negative offsets from the frame pointer.
bc45ade3 1690
994295f2 1691 The SH only has positive indexes, so grow the frame up. */
0d7e008e
SC		 1692/* #define FRAME_GROWS_DOWNWARD */
1693
1694/* Offset from the frame pointer to the first local variable slot to
994295f2 1695 be allocated. */
bc45ade3
SC		 1696#define STARTING_FRAME_OFFSET 0
1697
1698/* If we generate an insn to push BYTES bytes,
1699 this says how many the stack pointer really advances by. */
e9a25f70
JL		 1700/* Don't define PUSH_ROUNDING, since the hardware doesn't do this.
1701 When PUSH_ROUNDING is not defined, PARM_BOUNDARY will cause gcc to
1702 do correct alignment. */
1703#if 0
bc45ade3 1704#define PUSH_ROUNDING(NPUSHED) (((NPUSHED) + 3) & ~3)
e9a25f70 1705#endif
bc45ade3
SC		 1706
1707/* Offset of first parameter from the argument pointer register value. */
1708#define FIRST_PARM_OFFSET(FNDECL) 0
1709
1710/* Value is the number of byte of arguments automatically
1711 popped when returning from a subroutine call.
8b109b37 1712 FUNDECL is the declaration node of the function (as a tree),
bc45ade3
SC		 1713 FUNTYPE is the data type of the function (as a tree),
1714 or for a library call it is an identifier node for the subroutine name.
1715 SIZE is the number of bytes of arguments passed on the stack.
1716
1717 On the SH, the caller does not pop any of its arguments that were passed
1718 on the stack. */
8b109b37 1719#define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
bc45ade3 1720
fa5322fa
AO		 1721/* Value is the number of bytes of arguments automatically popped when
1722 calling a subroutine.
1723 CUM is the accumulated argument list.
1724
1725 On SHcompact, the call trampoline pops arguments off the stack. */
1726#define CALL_POPS_ARGS(CUM) (TARGET_SHCOMPACT ? (CUM).stack_regs * 8 : 0)
1727
97e3c422
R		 1728/* Nonzero if we do not know how to pass TYPE solely in registers.
1729 Values that come in registers with inconvenient padding are stored
1730 to memory at the function start. */
1731
1732#define MUST_PASS_IN_STACK(MODE,TYPE) \
1733 ((TYPE) != 0 \
1734 && (TREE_CODE (TYPE_SIZE (TYPE)) != INTEGER_CST \
1735 || TREE_ADDRESSABLE (TYPE)))
6f317ef3 1736/* Some subroutine macros specific to this machine. */
5c3ea805
JW		 1737
1738#define BASE_RETURN_VALUE_REG(MODE) \
fa5322fa 1739 ((TARGET_FPU_ANY && ((MODE) == SFmode)) \
5c3ea805 1740 ? FIRST_FP_RET_REG \
fa5322fa 1741 : TARGET_FPU_ANY && (MODE) == SCmode \
225e4f43 1742 ? FIRST_FP_RET_REG \
fa5322fa 1743 : (TARGET_FPU_DOUBLE \
225e4f43
R		 1744 && ((MODE) == DFmode || (MODE) == SFmode \
1745 || (MODE) == DCmode || (MODE) == SCmode )) \
1746 ? FIRST_FP_RET_REG \
5c3ea805
JW		 1747 : FIRST_RET_REG)
1748
1749#define BASE_ARG_REG(MODE) \
3a8699c7 1750 ((TARGET_SH2E && ((MODE) == SFmode)) \
5c3ea805 1751 ? FIRST_FP_PARM_REG \
225e4f43
R		 1752 : TARGET_SH4 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1753 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT)\
1754 ? FIRST_FP_PARM_REG \
5c3ea805
JW		 1755 : FIRST_PARM_REG)
1756
bc45ade3
SC		 1757/* Define how to find the value returned by a function.
1758 VALTYPE is the data type of the value (as a tree).
1759 If the precise function being called is known, FUNC is its FUNCTION_DECL;
225e4f43
R		 1760 otherwise, FUNC is 0.
1761 For the SH, this is like LIBCALL_VALUE, except that we must change the
1762 mode like PROMOTE_MODE does.
1763 ??? PROMOTE_MODE is ignored for non-scalar types. The set of types
1764 tested here has to be kept in sync with the one in explow.c:promote_mode. */
1765
1766#define FUNCTION_VALUE(VALTYPE, FUNC) \
c0d4e710 1767 gen_rtx_REG ( \
225e4f43
R		 1768 ((GET_MODE_CLASS (TYPE_MODE (VALTYPE)) == MODE_INT \
1769 && GET_MODE_SIZE (TYPE_MODE (VALTYPE)) < UNITS_PER_WORD \
1770 && (TREE_CODE (VALTYPE) == INTEGER_TYPE \
1771 || TREE_CODE (VALTYPE) == ENUMERAL_TYPE \
1772 || TREE_CODE (VALTYPE) == BOOLEAN_TYPE \
1773 || TREE_CODE (VALTYPE) == CHAR_TYPE \
1774 || TREE_CODE (VALTYPE) == REAL_TYPE \
1775 || TREE_CODE (VALTYPE) == OFFSET_TYPE)) \
150e407a 1776 && sh_promote_prototypes (VALTYPE) \
fa5322fa 1777 ? (TARGET_SHMEDIA ? DImode : SImode) : TYPE_MODE (VALTYPE)), \
225e4f43 1778 BASE_RETURN_VALUE_REG (TYPE_MODE (VALTYPE)))
73774972 1779
bc45ade3
SC		 1780/* Define how to find the value returned by a library function
1781 assuming the value has mode MODE. */
5c3ea805 1782#define LIBCALL_VALUE(MODE) \
c5c76735 1783 gen_rtx_REG ((MODE), BASE_RETURN_VALUE_REG (MODE));
bc45ade3 1784
6f317ef3 1785/* 1 if N is a possible register number for a function value. */
5c3ea805 1786#define FUNCTION_VALUE_REGNO_P(REGNO) \
3a8699c7 1787 ((REGNO) == FIRST_RET_REG || (TARGET_SH2E && (REGNO) == FIRST_FP_RET_REG) \
fa5322fa 1788 || (TARGET_SHMEDIA_FPU && (REGNO) == FIRST_FP_RET_REG))
bc45ade3 1789
994295f2 1790/* 1 if N is a possible register number for function argument passing. */
fada1961
R		 1791/* ??? There are some callers that pass REGNO as int, and others that pass
1792 it as unsigned. We get warnings unless we do casts everywhere. */
c5d67833 1793#define FUNCTION_ARG_REGNO_P(REGNO) \
fada1961
R		 1794 (((unsigned) (REGNO) >= (unsigned) FIRST_PARM_REG \
1795 && (unsigned) (REGNO) < (unsigned) (FIRST_PARM_REG + NPARM_REGS (SImode)))\
fa5322fa 1796 || (TARGET_FPU_ANY \
fada1961
R		 1797 && (unsigned) (REGNO) >= (unsigned) FIRST_FP_PARM_REG \
1798 && (unsigned) (REGNO) < (unsigned) (FIRST_FP_PARM_REG \
1799 + NPARM_REGS (SFmode))))
bc45ade3
SC		 1800\f
1801/* Define a data type for recording info about an argument list
1802 during the scan of that argument list. This data type should
1803 hold all necessary information about the function itself
1804 and about the args processed so far, enough to enable macros
1805 such as FUNCTION_ARG to determine where the next arg should go.
1806
1807 On SH, this is a single integer, which is a number of words
1808 of arguments scanned so far (including the invisible argument,
1809 if any, which holds the structure-value-address).
1810 Thus NARGREGS or more means all following args should go on the stack. */
1811
5c3ea805
JW		 1812enum sh_arg_class { SH_ARG_INT = 0, SH_ARG_FLOAT = 1 };
1813struct sh_args {
1814 int arg_count[2];
07385c49 1815 int force_mem;
5e7a8ee0 1816 /* Nonzero if a prototype is available for the function. */
fa5322fa
AO		 1817 int prototype_p;
1818 /* The number of an odd floating-point register, that should be used
1819 for the next argument of type float. */
1820 int free_single_fp_reg;
1821 /* Whether we're processing an outgoing function call. */
1822 int outgoing;
1823 /* The number of general-purpose registers that should have been
1824 used to pass partial arguments, that are passed totally on the
1825 stack. On SHcompact, a call trampoline will pop them off the
1826 stack before calling the actual function, and, if the called
1827 function is implemented in SHcompact mode, the incoming arguments
1828 decoder will push such arguments back onto the stack. For
1829 incoming arguments, STACK_REGS also takes into account other
1830 arguments passed by reference, that the decoder will also push
1831 onto the stack. */
1832 int stack_regs;
1833 /* The number of general-purpose registers that should have been
1834 used to pass arguments, if the arguments didn't have to be passed
1835 by reference. */
1836 int byref_regs;
1837 /* Set by SHCOMPACT_BYREF if the current argument is to be passed by
1838 reference. */
1839 int byref;
1840
1841 /* call_cookie is a bitmask used by call expanders, as well as
1842 function prologue and epilogues, to allow SHcompact to comply
1843 with the SH5 32-bit ABI, that requires 64-bit registers to be
1844 used even though only the lower 32-bit half is visible in
1845 SHcompact mode. The strategy is to call SHmedia trampolines.
1846
1847 The alternatives for each of the argument-passing registers are
1848 (a) leave it unchanged; (b) pop it off the stack; (c) load its
1849 contents from the address in it; (d) add 8 to it, storing the
1850 result in the next register, then (c); (e) copy it from some
1851 floating-point register,
1852
1853 Regarding copies from floating-point registers, r2 may only be
1854 copied from dr0. r3 may be copied from dr0 or dr2. r4 maybe
1855 copied from dr0, dr2 or dr4. r5 maybe copied from dr0, dr2,
1856 dr4 or dr6. r6 may be copied from dr0, dr2, dr4, dr6 or dr8.
1857 r7 through to r9 may be copied from dr0, dr2, dr4, dr8, dr8 or
1858 dr10.
1859
1860 The bit mask is structured as follows:
1861
1862 - 1 bit to tell whether to set up a return trampoline.
1863
1864 - 3 bits to count the number consecutive registers to pop off the
1865 stack.
1866
1867 - 4 bits for each of r9, r8, r7 and r6.
1868
1869 - 3 bits for each of r5, r4, r3 and r2.
1870
1871 - 3 bits set to 0 (the most significant ones)
1872
1873 3 2 1 0
1874 1098 7654 3210 9876 5432 1098 7654 3210
1875 FLPF LPFL PFLP FFLP FFLP FFLP FFLP SSST
1876 2223 3344 4555 6666 7777 8888 9999 SSS-
1877
1878 - If F is set, the register must be copied from an FP register,
1879 whose number is encoded in the remaining bits.
1880
1881 - Else, if L is set, the register must be loaded from the address
1882 contained in it. If the P bit is *not* set, the address of the
1883 following dword should be computed first, and stored in the
1884 following register.
1885
1886 - Else, if P is set, the register alone should be popped off the
1887 stack.
1888
1889 - After all this processing, the number of registers represented
1890 in SSS will be popped off the stack. This is an optimization
1891 for pushing/popping consecutive registers, typically used for
1892 varargs and large arguments partially passed in registers.
1893
1894 - If T is set, a return trampoline will be set up for 64-bit
1895 return values to be split into 2 32-bit registers. */
1896#define CALL_COOKIE_RET_TRAMP_SHIFT 0
1897#define CALL_COOKIE_RET_TRAMP(VAL) ((VAL) << CALL_COOKIE_RET_TRAMP_SHIFT)
1898#define CALL_COOKIE_STACKSEQ_SHIFT 1
1899#define CALL_COOKIE_STACKSEQ(VAL) ((VAL) << CALL_COOKIE_STACKSEQ_SHIFT)
1900#define CALL_COOKIE_STACKSEQ_GET(COOKIE) \
1901 (((COOKIE) >> CALL_COOKIE_STACKSEQ_SHIFT) & 7)
1902#define CALL_COOKIE_INT_REG_SHIFT(REG) \
1903 (4 * (7 - (REG)) + (((REG) <= 2) ? ((REG) - 2) : 1) + 3)
1904#define CALL_COOKIE_INT_REG(REG, VAL) \
1905 ((VAL) << CALL_COOKIE_INT_REG_SHIFT (REG))
1906#define CALL_COOKIE_INT_REG_GET(COOKIE, REG) \
1907 (((COOKIE) >> CALL_COOKIE_INT_REG_SHIFT (REG)) & ((REG) < 4 ? 7 : 15))
1908 long call_cookie;
61f71b34 1909
e86ac6af 1910 /* This is set to nonzero when the call in question must use the Renesas ABI,
61f71b34
DD		 1911 even without the -mrenesas option. */
1912 int renesas_abi;
5c3ea805
JW		 1913};
1914
1915#define CUMULATIVE_ARGS struct sh_args
1916
1917#define GET_SH_ARG_CLASS(MODE) \
fa5322fa 1918 ((TARGET_FPU_ANY && (MODE) == SFmode) \
225e4f43 1919 ? SH_ARG_FLOAT \
fa5322fa
AO		 1920 /* There's no mention of complex float types in the SH5 ABI, so we
1921 should presumably handle them as aggregate types. */ \
1922 : TARGET_SH5 && GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT \
1923 ? SH_ARG_INT \
1924 : TARGET_FPU_DOUBLE && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1925 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
225e4f43 1926 ? SH_ARG_FLOAT : SH_ARG_INT)
bc45ade3 1927
c5d67833 1928#define ROUND_ADVANCE(SIZE) \
e9a25f70 1929 (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
bc45ade3 1930
994295f2
JW		 1931/* Round a register number up to a proper boundary for an arg of mode
1932 MODE.
1933
d3ae8277 1934 The SH doesn't care about double alignment, so we only
994295f2 1935 round doubles to even regs when asked to explicitly. */
bc45ade3 1936
5c3ea805 1937#define ROUND_REG(CUM, MODE) \
225e4f43
R		 1938 (((TARGET_ALIGN_DOUBLE \
1939 || (TARGET_SH4 && ((MODE) == DFmode || (MODE) == DCmode) \
1940 && (CUM).arg_count[(int) SH_ARG_FLOAT] < NPARM_REGS (MODE)))\
5c3ea805
JW		 1941 && GET_MODE_UNIT_SIZE ((MODE)) > UNITS_PER_WORD) \
1942 ? ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] \
1943 + ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] & 1)) \
1944 : (CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)])
bc45ade3 1945
bc45ade3
SC		 1946/* Initialize a variable CUM of type CUMULATIVE_ARGS
1947 for a call to a function whose data type is FNTYPE.
1948 For a library call, FNTYPE is 0.
1949
1950 On SH, the offset always starts at 0: the first parm reg is always
07385c49
R		 1951 the same reg for a given argument class.
1952
1953 For TARGET_HITACHI, the structure value pointer is passed in memory. */
bc45ade3 1954
0f6937fe 1955#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
5c3ea805
JW		 1956 do { \
1957 (CUM).arg_count[(int) SH_ARG_INT] = 0; \
1958 (CUM).arg_count[(int) SH_ARG_FLOAT] = 0; \
61f71b34 1959 (CUM).renesas_abi = sh_attr_renesas_p (FNTYPE) ? 1 : 0; \
07385c49 1960 (CUM).force_mem \
61f71b34
DD		 1961 = ((TARGET_HITACHI || (CUM).renesas_abi) && (FNTYPE) \
1962 && aggregate_value_p (TREE_TYPE (FNTYPE), (FNDECL))); \
fa5322fa
AO		 1963 (CUM).prototype_p = (FNTYPE) && TYPE_ARG_TYPES (FNTYPE); \
1964 (CUM).arg_count[(int) SH_ARG_INT] \
1965 = (TARGET_SH5 && (FNTYPE) \
61f71b34 1966 && aggregate_value_p (TREE_TYPE (FNTYPE), (FNDECL))); \
fa5322fa
AO		 1967 (CUM).free_single_fp_reg = 0; \
1968 (CUM).outgoing = 1; \
1969 (CUM).stack_regs = 0; \
1970 (CUM).byref_regs = 0; \
1971 (CUM).byref = 0; \
1972 (CUM).call_cookie \
1973 = (CALL_COOKIE_RET_TRAMP \
1974 (TARGET_SHCOMPACT && (FNTYPE) \
1975 && (CUM).arg_count[(int) SH_ARG_INT] == 0 \
1976 && (TYPE_MODE (TREE_TYPE (FNTYPE)) == BLKmode \
1977 ? int_size_in_bytes (TREE_TYPE (FNTYPE)) \
1978 : GET_MODE_SIZE (TYPE_MODE (TREE_TYPE (FNTYPE)))) > 4 \
1979 && (BASE_RETURN_VALUE_REG (TYPE_MODE (TREE_TYPE \
1980 (FNTYPE))) \
1981 == FIRST_RET_REG))); \
1982 } while (0)
1983
1984#define INIT_CUMULATIVE_LIBCALL_ARGS(CUM, MODE, LIBNAME) \
1985 do { \
0f6937fe 1986 INIT_CUMULATIVE_ARGS ((CUM), NULL_TREE, (LIBNAME), 0, 0); \
fa5322fa
AO		 1987 (CUM).call_cookie \
1988 = (CALL_COOKIE_RET_TRAMP \
1989 (TARGET_SHCOMPACT && GET_MODE_SIZE (MODE) > 4 \
1990 && BASE_RETURN_VALUE_REG (MODE) == FIRST_RET_REG)); \
1991 } while (0)
1992
1993#define INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME) \
1994 do { \
0f6937fe 1995 INIT_CUMULATIVE_ARGS ((CUM), (FNTYPE), (LIBNAME), 0, 0); \
fa5322fa 1996 (CUM).outgoing = 0; \
5c3ea805 1997 } while (0)
bc45ade3
SC		 1998
1999#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
61f71b34
DD		 2000 sh_function_arg_advance (&(CUM), (MODE), (TYPE), (NAMED))
2001#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
2002 sh_function_arg (&(CUM), (MODE), (TYPE), (NAMED))
bc45ade3 2003
5c3ea805 2004/* Return boolean indicating arg of mode MODE will be passed in a reg.
6f317ef3 2005 This macro is only used in this file. */
5c3ea805
JW		 2006
2007#define PASS_IN_REG_P(CUM, MODE, TYPE) \
9ab70a9b 2008 (((TYPE) == 0 \
229f17cf 2009 || (! TREE_ADDRESSABLE ((tree)(TYPE)) \
61f71b34
DD		 2010 && (! (TARGET_HITACHI || (CUM).renesas_abi) \
2011 || ! (AGGREGATE_TYPE_P (TYPE) \
2012 || (!TARGET_FPU_ANY \
2013 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
2014 && GET_MODE_SIZE (MODE) > GET_MODE_SIZE (SFmode))))))) \
07385c49 2015 && ! (CUM).force_mem \
3a8699c7 2016 && (TARGET_SH2E \
1245df60
R		 2017 ? ((MODE) == BLKmode \
2018 ? (((CUM).arg_count[(int) SH_ARG_INT] * UNITS_PER_WORD \
2019 + int_size_in_bytes (TYPE)) \
2020 <= NPARM_REGS (SImode) * UNITS_PER_WORD) \
2021 : ((ROUND_REG((CUM), (MODE)) \
2022 + HARD_REGNO_NREGS (BASE_ARG_REG (MODE), (MODE))) \
2023 <= NPARM_REGS (MODE))) \
2024 : ROUND_REG ((CUM), (MODE)) < NPARM_REGS (MODE)))
5c3ea805 2025
6d1cb95f
R		 2026/* By accident we got stuck with passing SCmode on SH4 little endian
2027 in two registers that are nominally successive - which is different from
2028 two single SFmode values, where we take endianness translation into
2029 account. That does not work at all if an odd number of registers is
2030 already in use, so that got fixed, but library functions are still more
2031 likely to use complex numbers without mixing them with SFmode arguments
2032 (which in C would have to be structures), so for the sake of ABI
2033 compatibility the way SCmode values are passed when an even number of
2034 FP registers is in use remains different from a pair of SFmode values for
2035 now.
2036 I.e.:
2037 foo (double); a: fr5,fr4
2038 foo (float a, float b); a: fr5 b: fr4
2039 foo (__complex float a); a.real fr4 a.imag: fr5 - for consistency,
2040 this should be the other way round...
2041 foo (float a, __complex float b); a: fr5 b.real: fr4 b.imag: fr7 */
2042#define FUNCTION_ARG_SCmode_WART 1
2043
fa5322fa
AO		 2044/* Whether an argument must be passed by reference. On SHcompact, we
2045 pretend arguments wider than 32-bits that would have been passed in
2046 registers are passed by reference, so that an SHmedia trampoline
2047 loads them into the full 64-bits registers. */
2048#define FUNCTION_ARG_PASS_BY_REFERENCE(CUM,MODE,TYPE,NAMED) \
2049 (MUST_PASS_IN_STACK ((MODE), (TYPE)) \
6d1cb95f 2050 || SHCOMPACT_BYREF ((CUM), (MODE), (TYPE), (NAMED)))
fa5322fa
AO		 2051
2052#define SHCOMPACT_BYREF(CUM, MODE, TYPE, NAMED) \
2053 ((CUM).byref \
2054 = (TARGET_SHCOMPACT \
2055 && (CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
2056 && (! (NAMED) || GET_SH_ARG_CLASS (MODE) == SH_ARG_INT \
2057 || (GET_SH_ARG_CLASS (MODE) == SH_ARG_FLOAT \
2058 && ((CUM).arg_count[(int) SH_ARG_FLOAT] \
2059 >= NPARM_REGS (SFmode)))) \
2060 && ((MODE) == BLKmode ? int_size_in_bytes (TYPE) \
2061 : GET_MODE_SIZE (MODE)) > 4 \
2062 && ! SHCOMPACT_FORCE_ON_STACK ((MODE), (TYPE)) \
2063 && ! SH5_WOULD_BE_PARTIAL_NREGS ((CUM), (MODE), \
2064 (TYPE), (NAMED))) \
2065 ? ((MODE) == BLKmode ? int_size_in_bytes (TYPE) \
2066 : GET_MODE_SIZE (MODE)) \
2067 : 0)
2068
2069/* If an argument of size 5, 6 or 7 bytes is to be passed in a 64-bit
2070 register in SHcompact mode, it must be padded in the most
2071 significant end. This means that passing it by reference wouldn't
2072 pad properly on a big-endian machine. In this particular case, we
2073 pass this argument on the stack, in a way that the call trampoline
2074 will load its value into the appropriate register. */
2075#define SHCOMPACT_FORCE_ON_STACK(MODE,TYPE) \
2076 ((MODE) == BLKmode \
2077 && TARGET_SHCOMPACT \
2078 && ! TARGET_LITTLE_ENDIAN \
2079 && int_size_in_bytes (TYPE) > 4 \
2080 && int_size_in_bytes (TYPE) < 8)
2081
2082/* Minimum alignment for an argument to be passed by callee-copy
2083 reference. We need such arguments to be aligned to 8 byte
2084 boundaries, because they'll be loaded using quad loads. */
2085#define SH_MIN_ALIGN_FOR_CALLEE_COPY (8 * BITS_PER_UNIT)
2086
2087#define FUNCTION_ARG_CALLEE_COPIES(CUM,MODE,TYPE,NAMED) \
2088 ((CUM).outgoing \
2089 && (((MODE) == BLKmode ? TYPE_ALIGN (TYPE) \
2090 : GET_MODE_ALIGNMENT (MODE)) \
2091 % SH_MIN_ALIGN_FOR_CALLEE_COPY == 0))
2092
2093/* The SH5 ABI requires floating-point arguments to be passed to
2094 functions without a prototype in both an FP register and a regular
2095 register or the stack. When passing the argument in both FP and
2096 general-purpose registers, list the FP register first. */
2097#define SH5_PROTOTYPELESS_FLOAT_ARG(CUM,MODE) \
2098 (gen_rtx_PARALLEL \
2099 ((MODE), \
2100 gen_rtvec (2, \
2101 gen_rtx_EXPR_LIST \
2102 (VOIDmode, \
2103 ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
2104 ? gen_rtx_REG ((MODE), FIRST_FP_PARM_REG \
2105 + (CUM).arg_count[(int) SH_ARG_FLOAT]) \
2106 : NULL_RTX), \
2107 const0_rtx), \
2108 gen_rtx_EXPR_LIST \
2109 (VOIDmode, \
2110 ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
2111 ? gen_rtx_REG ((MODE), FIRST_PARM_REG \
2112 + (CUM).arg_count[(int) SH_ARG_INT]) \
2113 : gen_rtx_REG ((MODE), FIRST_FP_PARM_REG \
2114 + (CUM).arg_count[(int) SH_ARG_FLOAT])), \
2115 const0_rtx))))
2116
2117/* The SH5 ABI requires regular registers or stack slots to be
2118 reserved for floating-point arguments. Registers are taken care of
2119 in FUNCTION_ARG_ADVANCE, but stack slots must be reserved here.
2120 Unfortunately, there's no way to just reserve a stack slot, so
2121 we'll end up needlessly storing a copy of the argument in the
2122 stack. For incoming arguments, however, the PARALLEL will be
2123 optimized to the register-only form, and the value in the stack
2124 slot won't be used at all. */
2125#define SH5_PROTOTYPED_FLOAT_ARG(CUM,MODE,REG) \
2126 ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
2127 ? gen_rtx_REG ((MODE), (REG)) \
2128 : gen_rtx_PARALLEL ((MODE), \
2129 gen_rtvec (2, \
2130 gen_rtx_EXPR_LIST \
2131 (VOIDmode, NULL_RTX, \
2132 const0_rtx), \
2133 gen_rtx_EXPR_LIST \
2134 (VOIDmode, gen_rtx_REG ((MODE), \
2135 (REG)), \
2136 const0_rtx))))
2137
bc45ade3
SC		 2138/* For an arg passed partly in registers and partly in memory,
2139 this is the number of registers used.
2140 For args passed entirely in registers or entirely in memory, zero.
994295f2
JW		 2141
2142 We sometimes split args. */
0d7e008e 2143
d3ae8277 2144#define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
fa5322fa
AO		 2145 ((! TARGET_SH5 \
2146 && PASS_IN_REG_P ((CUM), (MODE), (TYPE)) \
225e4f43 2147 && ! TARGET_SH4 \
5c3ea805 2148 && (ROUND_REG ((CUM), (MODE)) \
225e4f43 2149 + ((MODE) != BLKmode \
5c3ea805
JW		 2150 ? ROUND_ADVANCE (GET_MODE_SIZE (MODE)) \
2151 : ROUND_ADVANCE (int_size_in_bytes (TYPE))) \
007baa49 2152 > NPARM_REGS (MODE))) \
5c3ea805 2153 ? NPARM_REGS (MODE) - ROUND_REG ((CUM), (MODE)) \
fa5322fa
AO		 2154 : (SH5_WOULD_BE_PARTIAL_NREGS ((CUM), (MODE), (TYPE), (NAMED)) \
2155 && ! TARGET_SHCOMPACT) \
2156 ? NPARM_REGS (SImode) - (CUM).arg_count[(int) SH_ARG_INT] \
5c3ea805 2157 : 0)
bc45ade3 2158
fa5322fa 2159#define SH5_WOULD_BE_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
1bf93c14
R		 2160 (TARGET_SH5 \
2161 && ((MODE) == BLKmode || (MODE) == TImode || (MODE) == CDImode \
2162 || (MODE) == DCmode) \
fa5322fa
AO		 2163 && ((CUM).arg_count[(int) SH_ARG_INT] \
2164 + (int_size_in_bytes (TYPE) + 7) / 8) > NPARM_REGS (SImode))
2165
bc45ade3 2166/* Perform any needed actions needed for a function that is receiving a
994295f2 2167 variable number of arguments. */
bc45ade3 2168
514066a1 2169/* Implement `va_start' for varargs and stdarg. */
e5faf155
ZW		 2170#define EXPAND_BUILTIN_VA_START(valist, nextarg) \
2171 sh_va_start (valist, nextarg)
514066a1
RH		 2172
2173/* Implement `va_arg'. */
2174#define EXPAND_BUILTIN_VA_ARG(valist, type) \
2175 sh_va_arg (valist, type)
2176
1bad666c
JW		 2177/* Call the function profiler with a given profile label.
2178 We use two .aligns, so as to make sure that both the .long is aligned
2179 on a 4 byte boundary, and that the .long is a fixed distance (2 bytes)
2180 from the trapa instruction. */
bc45ade3 2181
b9654711
SC		 2182#define FUNCTION_PROFILER(STREAM,LABELNO) \
2183{ \
e9a25f70
JL		 2184 fprintf((STREAM), "\t.align\t2\n"); \
2185 fprintf((STREAM), "\ttrapa\t#33\n"); \
2186 fprintf((STREAM), "\t.align\t2\n"); \
2187 asm_fprintf((STREAM), "\t.long\t%LLP%d\n", (LABELNO)); \
bc45ade3
SC		 2188}
2189
d59c4c8e
JW		 2190/* Define this macro if the code for function profiling should come
2191 before the function prologue. Normally, the profiling code comes
2192 after. */
2193
2194#define PROFILE_BEFORE_PROLOGUE
2195
bc45ade3
SC		 2196/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2197 the stack pointer does not matter. The value is tested only in
2198 functions that have frame pointers.
2199 No definition is equivalent to always zero. */
2200
4fdd1f85 2201#define EXIT_IGNORE_STACK 1
bc45ade3 2202
73774972 2203/*
ddd5a7c1 2204 On the SH, the trampoline looks like
ec4ad0f9 2205 2 0002 D202 mov.l l2,r2
e9a25f70 2206 1 0000 D301 mov.l l1,r3
ec4ad0f9 2207 3 0004 422B jmp @r2
e9a25f70 2208 4 0006 0009 nop
ec4ad0f9
AO		 2209 5 0008 00000000 l1: .long area
2210 6 000c 00000000 l2: .long function */
bc45ade3
SC		 2211
2212/* Length in units of the trampoline for entering a nested function. */
ca903bba 2213#define TRAMPOLINE_SIZE (TARGET_SHMEDIA64 ? 40 : TARGET_SH5 ? 24 : 16)
bc45ade3 2214
e9a25f70
JL		 2215/* Alignment required for a trampoline in bits . */
2216#define TRAMPOLINE_ALIGNMENT \
ca903bba
R		 2217 ((CACHE_LOG < 3 || (TARGET_SMALLCODE && ! TARGET_HARVARD)) ? 32 \
2218 : TARGET_SHMEDIA ? 256 : 64)
bc45ade3
SC		 2219
2220/* Emit RTL insns to initialize the variable parts of a trampoline.
2221 FNADDR is an RTX for the address of the function's pure code.
2222 CXT is an RTX for the static chain value for the function. */
2223
ca903bba
R		 2224#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
2225 sh_initialize_trampoline ((TRAMP), (FNADDR), (CXT))
d1405d89 2226
fa5322fa
AO		 2227/* On SH5, trampolines are SHmedia code, so add 1 to the address. */
2228
2229#define TRAMPOLINE_ADJUST_ADDRESS(TRAMP) do \
2230{ \
ca903bba 2231 if (TARGET_SHMEDIA) \
a556fd39 2232 (TRAMP) = expand_simple_binop (Pmode, PLUS, (TRAMP), const1_rtx, \
fa5322fa
AO		 2233 gen_reg_rtx (Pmode), 0, \
2234 OPTAB_LIB_WIDEN); \
2235} while (0)
2236
d1405d89
JW		 2237/* A C expression whose value is RTL representing the value of the return
2238 address for the frame COUNT steps up from the current frame.
2239 FRAMEADDR is already the frame pointer of the COUNT frame, so we
2240 can ignore COUNT. */
2241
2242#define RETURN_ADDR_RTX(COUNT, FRAME) \
fada1961 2243 (((COUNT) == 0) ? sh_get_pr_initial_val () : (rtx) 0)
2754d3c5
R		 2244
2245/* A C expression whose value is RTL representing the location of the
2246 incoming return address at the beginning of any function, before the
2247 prologue. This RTL is either a REG, indicating that the return
2248 value is saved in REG, or a MEM representing a location in
2249 the stack. */
2250#define INCOMING_RETURN_ADDR_RTX \
2251 gen_rtx_REG (Pmode, TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG)
bc45ade3
SC		 2252\f
2253/* Addressing modes, and classification of registers for them. */
fa5322fa 2254#define HAVE_POST_INCREMENT TARGET_SH1
fa5322fa 2255#define HAVE_PRE_DECREMENT TARGET_SH1
bc45ade3 2256
fbe1758d 2257#define USE_LOAD_POST_INCREMENT(mode) ((mode == SImode || mode == DImode) \
fa5322fa 2258 ? 0 : TARGET_SH1)
fbe1758d
AM		 2259#define USE_LOAD_PRE_DECREMENT(mode) 0
2260#define USE_STORE_POST_INCREMENT(mode) 0
2261#define USE_STORE_PRE_DECREMENT(mode) ((mode == SImode || mode == DImode) \
fa5322fa 2262 ? 0 : TARGET_SH1)
fbe1758d
AM		 2263
2264#define MOVE_BY_PIECES_P(SIZE, ALIGN) (move_by_pieces_ninsns (SIZE, ALIGN) \
2265 < (TARGET_SMALLCODE ? 2 : \
19caa751 2266 ((ALIGN >= 32) ? 16 : 2)))
fbe1758d 2267
bc45ade3
SC		 2268/* Macros to check register numbers against specific register classes. */
2269
2270/* These assume that REGNO is a hard or pseudo reg number.
2271 They give nonzero only if REGNO is a hard reg of the suitable class
2272 or a pseudo reg currently allocated to a suitable hard reg.
2273 Since they use reg_renumber, they are safe only once reg_renumber
994295f2 2274 has been allocated, which happens in local-alloc.c. */
0d7e008e 2275
c5d67833 2276#define REGNO_OK_FOR_BASE_P(REGNO) \
104ee20b
AO		 2277 (GENERAL_OR_AP_REGISTER_P (REGNO) \
2278 || GENERAL_OR_AP_REGISTER_P (reg_renumber[(REGNO)]))
c5d67833 2279#define REGNO_OK_FOR_INDEX_P(REGNO) \
fa5322fa
AO		 2280 (TARGET_SHMEDIA \
2281 ? (GENERAL_REGISTER_P (REGNO) \
2282 || GENERAL_REGISTER_P ((unsigned) reg_renumber[(REGNO)])) \
2283 : (REGNO) == R0_REG || (unsigned) reg_renumber[(REGNO)] == R0_REG)
bc45ade3 2284
994295f2
JW		 2285/* Maximum number of registers that can appear in a valid memory
2286 address. */
bc45ade3 2287
0d7e008e 2288#define MAX_REGS_PER_ADDRESS 2
bc45ade3
SC		 2289
2290/* Recognize any constant value that is a valid address. */
2291
c5d67833 2292#define CONSTANT_ADDRESS_P(X) (GET_CODE (X) == LABEL_REF)
bc45ade3 2293
994295f2 2294/* Nonzero if the constant value X is a legitimate general operand. */
bc45ade3 2295
5c3ea805 2296#define LEGITIMATE_CONSTANT_P(X) \
fa5322fa 2297 (TARGET_SHMEDIA \
0ac78517
R		 2298 ? ((GET_MODE (X) != DFmode \
2299 && GET_MODE_CLASS (GET_MODE (X)) != MODE_VECTOR_FLOAT) \
fa5322fa
AO		 2300 || (X) == CONST0_RTX (GET_MODE (X)) \
2301 || ! TARGET_SHMEDIA_FPU \
2302 || TARGET_SHMEDIA64) \
2303 : (GET_CODE (X) != CONST_DOUBLE \
2304 || GET_MODE (X) == DFmode || GET_MODE (X) == SFmode \
3a8699c7 2305 || (TARGET_SH2E && (fp_zero_operand (X) || fp_one_operand (X)))))
bc45ade3 2306
bc45ade3
SC		 2307/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2308 and check its validity for a certain class.
2309 We have two alternate definitions for each of them.
2310 The usual definition accepts all pseudo regs; the other rejects
2311 them unless they have been allocated suitable hard regs.
2312 The symbol REG_OK_STRICT causes the latter definition to be used. */
2313
2314#ifndef REG_OK_STRICT
b9654711 2315
bc45ade3
SC		 2316/* Nonzero if X is a hard reg that can be used as a base reg
2317 or if it is a pseudo reg. */
2318#define REG_OK_FOR_BASE_P(X) \
104ee20b 2319 (GENERAL_OR_AP_REGISTER_P (REGNO (X)) || REGNO (X) >= FIRST_PSEUDO_REGISTER)
c5d67833 2320
bc45ade3
SC		 2321/* Nonzero if X is a hard reg that can be used as an index
2322 or if it is a pseudo reg. */
2323#define REG_OK_FOR_INDEX_P(X) \
fa5322fa
AO		 2324 ((TARGET_SHMEDIA ? GENERAL_REGISTER_P (REGNO (X)) \
2325 : REGNO (X) == R0_REG) || REGNO (X) >= FIRST_PSEUDO_REGISTER)
53c8870f
RK		 2326
2327/* Nonzero if X/OFFSET is a hard reg that can be used as an index
2328 or if X is a pseudo reg. */
2329#define SUBREG_OK_FOR_INDEX_P(X, OFFSET) \
fa5322fa
AO		 2330 ((TARGET_SHMEDIA ? GENERAL_REGISTER_P (REGNO (X)) \
2331 : REGNO (X) == R0_REG && OFFSET == 0) || REGNO (X) >= FIRST_PSEUDO_REGISTER)
b9654711 2332
bc45ade3 2333#else
c5d67833 2334
bc45ade3 2335/* Nonzero if X is a hard reg that can be used as a base reg. */
c5d67833 2336#define REG_OK_FOR_BASE_P(X) \
53c8870f 2337 REGNO_OK_FOR_BASE_P (REGNO (X))
b9654711 2338
bc45ade3 2339/* Nonzero if X is a hard reg that can be used as an index. */
c5d67833 2340#define REG_OK_FOR_INDEX_P(X) \
53c8870f
RK		 2341 REGNO_OK_FOR_INDEX_P (REGNO (X))
2342
2343/* Nonzero if X/OFFSET is a hard reg that can be used as an index. */
2344#define SUBREG_OK_FOR_INDEX_P(X, OFFSET) \
e9a25f70 2345 (REGNO_OK_FOR_INDEX_P (REGNO (X)) && (OFFSET) == 0)
b9654711 2346
bc45ade3 2347#endif
0d7e008e 2348
c5d67833 2349/* The 'Q' constraint is a pc relative load operand. */
06c386ea 2350#define EXTRA_CONSTRAINT_Q(OP) \
a6f463a0
AO		 2351 (GET_CODE (OP) == MEM \
2352 && ((GET_CODE (XEXP ((OP), 0)) == LABEL_REF) \
2353 || (GET_CODE (XEXP ((OP), 0)) == CONST \
2354 && GET_CODE (XEXP (XEXP ((OP), 0), 0)) == PLUS \
2355 && GET_CODE (XEXP (XEXP (XEXP ((OP), 0), 0), 0)) == LABEL_REF \
2356 && GET_CODE (XEXP (XEXP (XEXP ((OP), 0), 0), 1)) == CONST_INT)))
0d7e008e 2357
735cb76e
R		 2358/* Extra address constraints. */
2359#define EXTRA_CONSTRAINT_A(OP, STR) 0
2360
2361/* Constraint for selecting FLDI0 or FLDI1 instruction. If the clobber
2362 operand is not SCRATCH (i.e. REG) then R0 is probably being
2363 used, hence mova is being used, hence do not select this pattern */
2364#define EXTRA_CONSTRAINT_Bsc(OP) (GET_CODE(OP) == SCRATCH)
2365#define EXTRA_CONSTRAINT_B(OP, STR) \
2366 ((STR)[1] == 's' && (STR)[2] == 'c' ? EXTRA_CONSTRAINT_Bsc (OP) \
2367 : 0)
2368
2369/* The `C16' constraint is a 16-bit constant, literal or symbolic. */
2370#define EXTRA_CONSTRAINT_C16(OP) \
fa5322fa
AO		 2371 (GET_CODE (OP) == CONST \
2372 && GET_CODE (XEXP ((OP), 0)) == SIGN_EXTEND \
2373 && GET_MODE (XEXP ((OP), 0)) == DImode \
2374 && GET_CODE (XEXP (XEXP ((OP), 0), 0)) == TRUNCATE \
2375 && GET_MODE (XEXP (XEXP ((OP), 0), 0)) == HImode \
2376 && (MOVI_SHORI_BASE_OPERAND_P (XEXP (XEXP (XEXP ((OP), 0), 0), 0)) \
2377 || (GET_CODE (XEXP (XEXP (XEXP ((OP), 0), 0), 0)) == ASHIFTRT \
2378 && (MOVI_SHORI_BASE_OPERAND_P \
2379 (XEXP (XEXP (XEXP (XEXP ((OP), 0), 0), 0), 0))) \
2380 && GET_CODE (XEXP (XEXP (XEXP (XEXP ((OP), 0), 0), 0), \
2381 1)) == CONST_INT)))
2382
2383/* Check whether OP is a datalabel unspec. */
2384#define DATALABEL_REF_NO_CONST_P(OP) \
2385 (GET_CODE (OP) == UNSPEC \
2386 && XINT ((OP), 1) == UNSPEC_DATALABEL \
2387 && XVECLEN ((OP), 0) == 1 \
2388 && (GET_CODE (XVECEXP ((OP), 0, 0)) == SYMBOL_REF \
2389 || GET_CODE (XVECEXP ((OP), 0, 0)) == LABEL_REF))
2390
2391/* Check whether OP is a datalabel unspec, possibly enclosed within a
2392 CONST. */
2393#define DATALABEL_REF_P(OP) \
2394 ((GET_CODE (OP) == CONST && DATALABEL_REF_NO_CONST_P (XEXP ((OP), 0))) \
2395 || DATALABEL_REF_NO_CONST_P (OP))
2396
2397#define GOT_ENTRY_P(OP) \
2398 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
2399 && XINT (XEXP ((OP), 0), 1) == UNSPEC_GOT)
2400
2401#define GOTPLT_ENTRY_P(OP) \
2402 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
2403 && XINT (XEXP ((OP), 0), 1) == UNSPEC_GOTPLT)
2404
fff08fd8
SC		 2405#define UNSPEC_GOTOFF_P(OP) \
2406 (GET_CODE (OP) == UNSPEC && XINT ((OP), 1) == UNSPEC_GOTOFF)
2407
fa5322fa 2408#define GOTOFF_P(OP) \
fff08fd8
SC		 2409 (GET_CODE (OP) == CONST \
2410 && (UNSPEC_GOTOFF_P (XEXP ((OP), 0)) \
2411 || (GET_CODE (XEXP ((OP), 0)) == PLUS \
2412 && UNSPEC_GOTOFF_P (XEXP (XEXP ((OP), 0), 0)) \
2413 && GET_CODE (XEXP (XEXP ((OP), 0), 1)) == CONST_INT)))
fa5322fa
AO		 2414
2415#define PIC_ADDR_P(OP) \
2416 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
2417 && XINT (XEXP ((OP), 0), 1) == UNSPEC_PIC)
2418
735cb76e
R		 2419#define PIC_OFFSET_P(OP) \
2420 (PIC_ADDR_P (OP) \
2421 && GET_CODE (XVECEXP (XEXP ((OP), 0), 0, 0)) == MINUS \
2422 && reg_mentioned_p (pc_rtx, XEXP (XVECEXP (XEXP ((OP), 0), 0, 0), 1)))
2423
2424#define PIC_DIRECT_ADDR_P(OP) \
2425 (PIC_ADDR_P (OP) && GET_CODE (XVECEXP (XEXP ((OP), 0), 0, 0)) != MINUS)
2426
fa5322fa
AO		 2427#define NON_PIC_REFERENCE_P(OP) \
2428 (GET_CODE (OP) == LABEL_REF || GET_CODE (OP) == SYMBOL_REF \
2429 || DATALABEL_REF_P (OP) \
2430 || (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == PLUS \
2431 && (GET_CODE (XEXP (XEXP ((OP), 0), 0)) == SYMBOL_REF \
2432 || DATALABEL_REF_P (XEXP (XEXP ((OP), 0), 0))) \
2433 && GET_CODE (XEXP (XEXP ((OP), 0), 1)) == CONST_INT))
2434
2435#define PIC_REFERENCE_P(OP) \
2436 (GOT_ENTRY_P (OP) || GOTPLT_ENTRY_P (OP) \
2437 || GOTOFF_P (OP) || PIC_ADDR_P (OP))
2438
2439#define MOVI_SHORI_BASE_OPERAND_P(OP) \
735cb76e
R		 2440 (flag_pic \
2441 ? (GOT_ENTRY_P (OP) || GOTPLT_ENTRY_P (OP) || GOTOFF_P (OP) \
2442 || PIC_OFFSET_P (OP)) \
2443 : NON_PIC_REFERENCE_P (OP))
fa5322fa 2444
735cb76e
R		 2445/* The `Csy' constraint is a label or a symbol. */
2446#define EXTRA_CONSTRAINT_Csy(OP) \
1bf93c14 2447 (NON_PIC_REFERENCE_P (OP) || PIC_DIRECT_ADDR_P (OP))
fa5322fa 2448
c1b92d09 2449/* A zero in any shape or form. */
735cb76e 2450#define EXTRA_CONSTRAINT_Z(OP) \
0ac78517 2451 ((OP) == CONST0_RTX (GET_MODE (OP)))
c1b92d09
R		 2452
2453/* Any vector constant we can handle. */
2454#define EXTRA_CONSTRAINT_W(OP) \
2455 (GET_CODE (OP) == CONST_VECTOR \
2456 && (sh_rep_vec ((OP), VOIDmode) \
2457 || (HOST_BITS_PER_WIDE_INT >= 64 \
2458 ? sh_const_vec ((OP), VOIDmode) \
2459 : sh_1el_vec ((OP), VOIDmode))))
2460
735cb76e
R		 2461/* A non-explicit constant that can be loaded directly into a general purpose
2462 register. This is like 's' except we don't allow PIC_DIRECT_ADDR_P. */
2463#define EXTRA_CONSTRAINT_Cpg(OP) \
2464 (CONSTANT_P (OP) \
2465 && GET_CODE (OP) != CONST_INT \
2466 && GET_CODE (OP) != CONST_DOUBLE \
2467 && (!flag_pic \
2468 || (LEGITIMATE_PIC_OPERAND_P (OP) \
2469 && (! PIC_ADDR_P (OP) || PIC_OFFSET_P (OP)) \
2470 && GET_CODE (OP) != LABEL_REF)))
2471#define EXTRA_CONSTRAINT_C(OP, STR) \
2472 ((STR)[1] == '1' && (STR)[2] == '6' ? EXTRA_CONSTRAINT_C16 (OP) \
2473 : (STR)[1] == 's' && (STR)[2] == 'y' ? EXTRA_CONSTRAINT_Csy (OP) \
2474 : (STR)[1] == 'p' && (STR)[2] == 'g' ? EXTRA_CONSTRAINT_Cpg (OP) \
2475 : 0)
2476
2477#define EXTRA_MEMORY_CONSTRAINT(C,STR) ((C) == 'S')
2478#define EXTRA_CONSTRAINT_Sr0(OP) \
2479 (memory_operand((OP), GET_MODE (OP)) \
2480 && ! refers_to_regno_p (R0_REG, R0_REG + 1, OP, (rtx *)0))
2481#define EXTRA_CONSTRAINT_S(OP, STR) \
2482 ((STR)[1] == 'r' && (STR)[2] == '0' ? EXTRA_CONSTRAINT_Sr0 (OP) \
2483 : 0)
b51dc045 2484
735cb76e 2485#define EXTRA_CONSTRAINT_STR(OP, C, STR) \
c5d67833 2486 ((C) == 'Q' ? EXTRA_CONSTRAINT_Q (OP) \
735cb76e
R		 2487 : (C) == 'A' ? EXTRA_CONSTRAINT_A ((OP), (STR)) \
2488 : (C) == 'B' ? EXTRA_CONSTRAINT_B ((OP), (STR)) \
2489 : (C) == 'C' ? EXTRA_CONSTRAINT_C ((OP), (STR)) \
2490 : (C) == 'S' ? EXTRA_CONSTRAINT_S ((OP), (STR)) \
c1b92d09 2491 : (C) == 'W' ? EXTRA_CONSTRAINT_W (OP) \
26d83879 2492 : (C) == 'Z' ? EXTRA_CONSTRAINT_Z (OP) \
c5d67833 2493 : 0)
bc45ade3
SC		 2494\f
2495/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
2496 that is a valid memory address for an instruction.
2497 The MODE argument is the machine mode for the MEM expression
f295bdb5 2498 that wants to use this address. */
b9654711 2499
5c3ea805
JW		 2500#define MODE_DISP_OK_4(X,MODE) \
2501(GET_MODE_SIZE (MODE) == 4 && (unsigned) INTVAL (X) < 64 \
3a8699c7 2502 && ! (INTVAL (X) & 3) && ! (TARGET_SH2E && (MODE) == SFmode))
225e4f43
R		 2503
2504#define MODE_DISP_OK_8(X,MODE) \
2505((GET_MODE_SIZE(MODE)==8) && ((unsigned)INTVAL(X)<60) \
2506 && ! (INTVAL(X) & 3) && ! (TARGET_SH4 && (MODE) == DFmode))
5a463884 2507
c5d67833
JW		 2508#define BASE_REGISTER_RTX_P(X) \
2509 ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \
2510 || (GET_CODE (X) == SUBREG \
2511 && GET_CODE (SUBREG_REG (X)) == REG \
2512 && REG_OK_FOR_BASE_P (SUBREG_REG (X))))
bc45ade3 2513
53c8870f
RK		 2514/* Since this must be r0, which is a single register class, we must check
2515 SUBREGs more carefully, to be sure that we don't accept one that extends
2516 outside the class. */
c5d67833
JW		 2517#define INDEX_REGISTER_RTX_P(X) \
2518 ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \
2519 || (GET_CODE (X) == SUBREG \
2520 && GET_CODE (SUBREG_REG (X)) == REG \
ddef6bc7 2521 && SUBREG_OK_FOR_INDEX_P (SUBREG_REG (X), SUBREG_BYTE (X))))
bc45ade3
SC		 2522
2523/* Jump to LABEL if X is a valid address RTX. This must also take
2524 REG_OK_STRICT into account when deciding about valid registers, but it uses
994295f2
JW		 2525 the above macros so we are in luck.
2526
bc45ade3
SC		 2527 Allow REG
2528 REG+disp
2529 REG+r0
2530 REG++
994295f2 2531 --REG */
bc45ade3 2532
3a8699c7 2533/* ??? The SH2e does not have the REG+disp addressing mode when loading values
5c3ea805
JW		 2534 into the FRx registers. We implement this by setting the maximum offset
2535 to zero when the value is SFmode. This also restricts loading of SFmode
2536 values into the integer registers, but that can't be helped. */
2537
994295f2 2538/* The SH allows a displacement in a QI or HI amode, but only when the
b9654711
SC		 2539 other operand is R0. GCC doesn't handle this very well, so we forgo
2540 all of that.
2541
c5d67833
JW		 2542 A legitimate index for a QI or HI is 0, SI can be any number 0..63,
2543 DI can be any number 0..60. */
bc45ade3 2544
c5d67833 2545#define GO_IF_LEGITIMATE_INDEX(MODE, OP, LABEL) \
0d7e008e
SC		 2546 do { \
2547 if (GET_CODE (OP) == CONST_INT) \
2548 { \
fa5322fa
AO		 2549 if (TARGET_SHMEDIA) \
2550 { \
2551 int MODE_SIZE = GET_MODE_SIZE (MODE); \
2552 if (! (INTVAL (OP) & (MODE_SIZE - 1)) \
2553 && INTVAL (OP) >= -512 * MODE_SIZE \
2554 && INTVAL (OP) < 512 * MODE_SIZE) \
2555 goto LABEL; \
2556 else \
2557 break; \
2558 } \
e9a25f70
JL		 2559 if (MODE_DISP_OK_4 ((OP), (MODE))) goto LABEL; \
2560 if (MODE_DISP_OK_8 ((OP), (MODE))) goto LABEL; \
0d7e008e 2561 } \
bc45ade3
SC		 2562 } while(0)
2563
c5d67833
JW		 2564#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \
2565{ \
2566 if (BASE_REGISTER_RTX_P (X)) \
2567 goto LABEL; \
2568 else if ((GET_CODE (X) == POST_INC || GET_CODE (X) == PRE_DEC) \
fa5322fa 2569 && ! TARGET_SHMEDIA \
e9a25f70 2570 && BASE_REGISTER_RTX_P (XEXP ((X), 0))) \
c5d67833 2571 goto LABEL; \
225e4f43
R		 2572 else if (GET_CODE (X) == PLUS \
2573 && ((MODE) != PSImode || reload_completed)) \
c5d67833 2574 { \
e9a25f70
JL		 2575 rtx xop0 = XEXP ((X), 0); \
2576 rtx xop1 = XEXP ((X), 1); \
c5d67833 2577 if (GET_MODE_SIZE (MODE) <= 8 && BASE_REGISTER_RTX_P (xop0)) \
e9a25f70 2578 GO_IF_LEGITIMATE_INDEX ((MODE), xop1, LABEL); \
225e4f43 2579 if (GET_MODE_SIZE (MODE) <= 4 \
fa5322fa 2580 || (TARGET_SHMEDIA && GET_MODE_SIZE (MODE) <= 8) \
229f17cf 2581 || (TARGET_SH4 && TARGET_FMOVD && MODE == DFmode)) \
c5d67833
JW		 2582 { \
2583 if (BASE_REGISTER_RTX_P (xop1) && INDEX_REGISTER_RTX_P (xop0))\
2584 goto LABEL; \
2585 if (INDEX_REGISTER_RTX_P (xop1) && BASE_REGISTER_RTX_P (xop0))\
2586 goto LABEL; \
2587 } \
2588 } \
994295f2
JW		 2589}
2590\f
2591/* Try machine-dependent ways of modifying an illegitimate address
bc45ade3
SC		 2592 to be legitimate. If we find one, return the new, valid address.
2593 This macro is used in only one place: `memory_address' in explow.c.
2594
2595 OLDX is the address as it was before break_out_memory_refs was called.
2596 In some cases it is useful to look at this to decide what needs to be done.
2597
2598 MODE and WIN are passed so that this macro can use
2599 GO_IF_LEGITIMATE_ADDRESS.
2600
2601 It is always safe for this macro to do nothing. It exists to recognize
a73a5114 2602 opportunities to optimize the output.
bc45ade3 2603
a73a5114
JW		 2604 For the SH, if X is almost suitable for indexing, but the offset is
2605 out of range, convert it into a normal form so that cse has a chance
2606 of reducing the number of address registers used. */
2607
2608#define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
2609{ \
1a66cd67
AO		 2610 if (flag_pic) \
2611 (X) = legitimize_pic_address (OLDX, MODE, NULL_RTX); \
55ebdce3 2612 if (GET_CODE (X) == PLUS \
a73a5114
JW		 2613 && (GET_MODE_SIZE (MODE) == 4 \
2614 || GET_MODE_SIZE (MODE) == 8) \
e9a25f70
JL		 2615 && GET_CODE (XEXP ((X), 1)) == CONST_INT \
2616 && BASE_REGISTER_RTX_P (XEXP ((X), 0)) \
fa5322fa 2617 && ! TARGET_SHMEDIA \
225e4f43 2618 && ! (TARGET_SH4 && (MODE) == DFmode) \
3a8699c7 2619 && ! (TARGET_SH2E && (MODE) == SFmode)) \
a73a5114 2620 { \
e9a25f70 2621 rtx index_rtx = XEXP ((X), 1); \
a73a5114
JW		 2622 HOST_WIDE_INT offset = INTVAL (index_rtx), offset_base; \
2623 rtx sum; \
2624 \
e9a25f70 2625 GO_IF_LEGITIMATE_INDEX ((MODE), index_rtx, WIN); \
24f72d76 2626 /* On rare occasions, we might get an unaligned pointer \
a73a5114
JW		 2627 that is indexed in a way to give an aligned address. \
2628 Therefore, keep the lower two bits in offset_base. */ \
2629 /* Instead of offset_base 128..131 use 124..127, so that \
2630 simple add suffices. */ \
2631 if (offset > 127) \
2632 { \
2633 offset_base = ((offset + 4) & ~60) - 4; \
2634 } \
2635 else \
2636 offset_base = offset & ~60; \
2637 /* Sometimes the normal form does not suit DImode. We \
2638 could avoid that by using smaller ranges, but that \
55ebdce3 2639 would give less optimized code when SImode is \
a73a5114
JW		 2640 prevalent. */ \
2641 if (GET_MODE_SIZE (MODE) + offset - offset_base <= 64) \
2642 { \
e9a25f70 2643 sum = expand_binop (Pmode, add_optab, XEXP ((X), 0), \
a73a5114
JW		 2644 GEN_INT (offset_base), NULL_RTX, 0, \
2645 OPTAB_LIB_WIDEN); \
2646 \
c5c76735 2647 (X) = gen_rtx_PLUS (Pmode, sum, GEN_INT (offset - offset_base)); \
a73a5114
JW		 2648 goto WIN; \
2649 } \
2650 } \
2651}
bc45ade3 2652
ef41dabb
R		 2653/* A C compound statement that attempts to replace X, which is an address
2654 that needs reloading, with a valid memory address for an operand of
2655 mode MODE. WIN is a C statement label elsewhere in the code.
2656
2657 Like for LEGITIMIZE_ADDRESS, for the SH we try to get a normal form
2658 of the address. That will allow inheritance of the address reloads. */
2659
2660#define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
2661{ \
2662 if (GET_CODE (X) == PLUS \
2663 && (GET_MODE_SIZE (MODE) == 4 || GET_MODE_SIZE (MODE) == 8) \
2664 && GET_CODE (XEXP (X, 1)) == CONST_INT \
2665 && BASE_REGISTER_RTX_P (XEXP (X, 0)) \
fa5322fa 2666 && ! TARGET_SHMEDIA \
225e4f43
R		 2667 && ! (TARGET_SH4 && (MODE) == DFmode) \
2668 && ! ((MODE) == PSImode && (TYPE) == RELOAD_FOR_INPUT_ADDRESS)) \
ef41dabb
R		 2669 { \
2670 rtx index_rtx = XEXP (X, 1); \
2671 HOST_WIDE_INT offset = INTVAL (index_rtx), offset_base; \
2672 rtx sum; \
2673 \
3a8699c7 2674 if (TARGET_SH2E && MODE == SFmode) \
225e4f43
R		 2675 { \
2676 X = copy_rtx (X); \
df4ae160 2677 push_reload (index_rtx, NULL_RTX, &XEXP (X, 1), NULL, \
225e4f43
R		 2678 INDEX_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), \
2679 (TYPE)); \
2680 goto WIN; \
2681 } \
ef41dabb
R		 2682 /* Instead of offset_base 128..131 use 124..127, so that \
2683 simple add suffices. */ \
2684 if (offset > 127) \
2685 { \
2686 offset_base = ((offset + 4) & ~60) - 4; \
2687 } \
2688 else \
2689 offset_base = offset & ~60; \
2690 /* Sometimes the normal form does not suit DImode. We \
2691 could avoid that by using smaller ranges, but that \
2692 would give less optimized code when SImode is \
2693 prevalent. */ \
2694 if (GET_MODE_SIZE (MODE) + offset - offset_base <= 64) \
2695 { \
c0d4e710 2696 sum = gen_rtx_PLUS (Pmode, XEXP (X, 0), \
ef41dabb 2697 GEN_INT (offset_base)); \
c0d4e710 2698 X = gen_rtx_PLUS (Pmode, sum, GEN_INT (offset - offset_base));\
df4ae160 2699 push_reload (sum, NULL_RTX, &XEXP (X, 0), NULL, \
ef41dabb
R		 2700 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), \
2701 (TYPE)); \
2702 goto WIN; \
2703 } \
2704 } \
2705 /* We must re-recognize what we created before. */ \
2706 else if (GET_CODE (X) == PLUS \
2707 && (GET_MODE_SIZE (MODE) == 4 || GET_MODE_SIZE (MODE) == 8) \
2708 && GET_CODE (XEXP (X, 0)) == PLUS \
2709 && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT \
2710 && BASE_REGISTER_RTX_P (XEXP (XEXP (X, 0), 0)) \
2711 && GET_CODE (XEXP (X, 1)) == CONST_INT \
fa5322fa 2712 && ! TARGET_SHMEDIA \
3a8699c7 2713 && ! (TARGET_SH2E && MODE == SFmode)) \
ef41dabb
R		 2714 { \
2715 /* Because this address is so complex, we know it must have \
2716 been created by LEGITIMIZE_RELOAD_ADDRESS before; thus, \
2717 it is already unshared, and needs no further unsharing. */ \
df4ae160 2718 push_reload (XEXP ((X), 0), NULL_RTX, &XEXP ((X), 0), NULL, \
ef41dabb
R		 2719 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), (TYPE));\
2720 goto WIN; \
2721 } \
2722}
2723
bc45ade3 2724/* Go to LABEL if ADDR (a legitimate address expression)
e9a25f70
JL		 2725 has an effect that depends on the machine mode it is used for.
2726
2727 ??? Strictly speaking, we should also include all indexed addressing,
2728 because the index scale factor is the length of the operand.
2729 However, the impact of GO_IF_MODE_DEPENDENT_ADDRESS would be to
2730 high if we did that. So we rely on reload to fix things up. */
2731
c5d67833 2732#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
bc45ade3 2733{ \
c5d67833 2734 if (GET_CODE(ADDR) == PRE_DEC || GET_CODE(ADDR) == POST_INC) \
bc45ade3
SC		 2735 goto LABEL; \
2736}
2737\f
2738/* Specify the machine mode that this machine uses
2739 for the index in the tablejump instruction. */
8b26829f 2740#define CASE_VECTOR_MODE ((! optimize || TARGET_BIGTABLE) ? SImode : HImode)
bc45ade3 2741
33f7f353
JR		 2742#define CASE_VECTOR_SHORTEN_MODE(MIN_OFFSET, MAX_OFFSET, BODY) \
2743((MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 127 \
33f7f353 2744 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 0, QImode) \
64ad9df2
R		 2745 : (MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 255 \
2746 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 1, QImode) \
33f7f353
JR		 2747 : (MIN_OFFSET) >= -32768 && (MAX_OFFSET) <= 32767 ? HImode \
2748 : SImode)
2749
18543a22
ILT		 2750/* Define as C expression which evaluates to nonzero if the tablejump
2751 instruction expects the table to contain offsets from the address of the
2752 table.
6f317ef3 2753 Do not define this if the table should contain absolute addresses. */
18543a22 2754#define CASE_VECTOR_PC_RELATIVE 1
bc45ade3 2755
fa5322fa
AO		 2756/* Define it here, so that it doesn't get bumped to 64-bits on SHmedia. */
2757#define FLOAT_TYPE_SIZE 32
2758
3a8699c7 2759/* Since the SH2e has only `float' support, it is desirable to make all
5c3ea805 2760 floating point types equivalent to `float'. */
3a8699c7 2761#define DOUBLE_TYPE_SIZE ((TARGET_SH2E && ! TARGET_SH4) ? 32 : 64)
5c3ea805 2762
994295f2 2763/* 'char' is signed by default. */
bc45ade3
SC		 2764#define DEFAULT_SIGNED_CHAR 1
2765
2766/* The type of size_t unsigned int. */
fa5322fa
AO		 2767#define SIZE_TYPE (TARGET_SH5 ? "long unsigned int" : "unsigned int")
2768
fa5322fa
AO		 2769#undef PTRDIFF_TYPE
2770#define PTRDIFF_TYPE (TARGET_SH5 ? "long int" : "int")
bc45ade3 2771
8e87e161
SC		 2772#define WCHAR_TYPE "short unsigned int"
2773#define WCHAR_TYPE_SIZE 16
1951818c
R		 2774
2775#define SH_ELF_WCHAR_TYPE "long int"
8e87e161 2776
bc45ade3
SC		 2777/* Max number of bytes we can move from memory to memory
2778 in one reasonably fast instruction. */
fa5322fa
AO		 2779#define MOVE_MAX (TARGET_SHMEDIA ? 8 : 4)
2780
2781/* Maximum value possibly taken by MOVE_MAX. Must be defined whenever
2782 MOVE_MAX is not a compile-time constant. */
2783#define MAX_MOVE_MAX 8
bc45ade3 2784
fbe1758d
AM		 2785/* Max number of bytes we want move_by_pieces to be able to copy
2786 efficiently. */
fa5322fa 2787#define MOVE_MAX_PIECES (TARGET_SH4 || TARGET_SHMEDIA ? 8 : 4)
fbe1758d 2788
9a63901f
RK		 2789/* Define if operations between registers always perform the operation
2790 on the full register even if a narrower mode is specified. */
2791#define WORD_REGISTER_OPERATIONS
2792
2793/* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2794 will either zero-extend or sign-extend. The value of this macro should
2795 be the code that says which one of the two operations is implicitly
2796 done, NIL if none. */
59324685 2797/* For SHmedia, we can truncate to QImode easier using zero extension. */
0ac78517
R		 2798/* FP registers can load SImode values, but don't implicitly sign-extend
2799 them to DImode. */
59324685
R		 2800#define LOAD_EXTEND_OP(MODE) \
2801 (((MODE) == QImode && TARGET_SHMEDIA) ? ZERO_EXTEND \
2802 : (MODE) != SImode ? SIGN_EXTEND : NIL)
bc45ade3 2803
211a0f85
JW		 2804/* Define if loading short immediate values into registers sign extends. */
2805#define SHORT_IMMEDIATES_SIGN_EXTEND
2806
9a5bb317
R		 2807/* Nonzero if access to memory by bytes is no faster than for words. */
2808#define SLOW_BYTE_ACCESS 1
2809
bc45ade3 2810/* Immediate shift counts are truncated by the output routines (or was it
97b65a3e 2811 the assembler?). Shift counts in a register are truncated by SH. Note
bc45ade3 2812 that the native compiler puts too large (> 32) immediate shift counts
97b65a3e 2813 into a register and shifts by the register, letting the SH decide what
bc45ade3 2814 to do instead of doing that itself. */
e9a25f70
JL		 2815/* ??? The library routines in lib1funcs.asm truncate the shift count.
2816 However, the SH3 has hardware shifts that do not truncate exactly as gcc
2817 expects - the sign bit is significant - so it appears that we need to
2818 leave this zero for correct SH3 code. */
2819#define SHIFT_COUNT_TRUNCATED (! TARGET_SH3)
bc45ade3 2820
bc45ade3
SC		 2821/* All integers have the same format so truncation is easy. */
2822#define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) 1
2823
2824/* Define this if addresses of constant functions
2825 shouldn't be put through pseudo regs where they can be cse'd.
2826 Desirable on machines where ordinary constants are expensive
2827 but a CALL with constant address is cheap. */
2828/*#define NO_FUNCTION_CSE 1*/
2829
994295f2 2830/* The machine modes of pointers and functions. */
fa5322fa 2831#define Pmode (TARGET_SHMEDIA64 ? DImode : SImode)
bc45ade3
SC		 2832#define FUNCTION_MODE Pmode
2833
97b65a3e
JW		 2834/* The multiply insn on the SH1 and the divide insns on the SH1 and SH2
2835 are actually function calls with some special constraints on arguments
2836 and register usage.
0d7e008e 2837
994295f2
JW		 2838 These macros tell reorg that the references to arguments and
2839 register clobbers for insns of type sfunc do not appear to happen
0d7e008e
SC		 2840 until after the millicode call. This allows reorg to put insns
2841 which set the argument registers into the delay slot of the millicode
2842 call -- thus they act more like traditional CALL_INSNs.
2843
0603a39d 2844 get_attr_is_sfunc will try to recognize the given insn, so make sure to
0d7e008e
SC		 2845 filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns
2846 in particular. */
2847
2848#define INSN_SETS_ARE_DELAYED(X) \
2849 ((GET_CODE (X) == INSN \
2850 && GET_CODE (PATTERN (X)) != SEQUENCE \
2851 && GET_CODE (PATTERN (X)) != USE \
2852 && GET_CODE (PATTERN (X)) != CLOBBER \
0603a39d 2853 && get_attr_is_sfunc (X)))
0d7e008e
SC		 2854
2855#define INSN_REFERENCES_ARE_DELAYED(X) \
2856 ((GET_CODE (X) == INSN \
2857 && GET_CODE (PATTERN (X)) != SEQUENCE \
2858 && GET_CODE (PATTERN (X)) != USE \
2859 && GET_CODE (PATTERN (X)) != CLOBBER \
0603a39d 2860 && get_attr_is_sfunc (X)))
0d7e008e 2861
1a66cd67
AO		 2862\f
2863/* Position Independent Code. */
1a66cd67 2864
2cef831c
KK		 2865/* We can't directly access anything that contains a symbol,
2866 nor can we indirect via the constant pool. */
2867#define LEGITIMATE_PIC_OPERAND_P(X) \
1bf93c14
R		 2868 ((! nonpic_symbol_mentioned_p (X) \
2869 && (GET_CODE (X) != SYMBOL_REF \
2870 || ! CONSTANT_POOL_ADDRESS_P (X) \
2871 || ! nonpic_symbol_mentioned_p (get_pool_constant (X)))) \
2872 || (TARGET_SHMEDIA && GET_CODE (X) == LABEL_REF))
2cef831c 2873
1a66cd67
AO		 2874#define SYMBOLIC_CONST_P(X) \
2875((GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == LABEL_REF) \
2876 && nonpic_symbol_mentioned_p (X))
2877\f
bc45ade3 2878/* Compute extra cost of moving data between one register class
e9a25f70 2879 and another. */
bc45ade3 2880
ec555f32
R		 2881/* If SECONDARY*_RELOAD_CLASS says something about the src/dst pair, regclass
2882 uses this information. Hence, the general register <-> floating point
225e4f43 2883 register information here is not used for SFmode. */
70a72ca4 2884
9a4816af
R		 2885#define REGCLASS_HAS_GENERAL_REG(CLASS) \
2886 ((CLASS) == GENERAL_REGS || (CLASS) == R0_REGS \
2887 || (! TARGET_SHMEDIA && (CLASS) == SIBCALL_REGS))
70a72ca4 2888
9a4816af
R		 2889#define REGCLASS_HAS_FP_REG(CLASS) \
2890 ((CLASS) == FP0_REGS || (CLASS) == FP_REGS \
2891 || (CLASS) == DF_REGS || (CLASS) == DF_HI_REGS)
2892
cf011243 2893#define REGISTER_MOVE_COST(MODE, SRCCLASS, DSTCLASS) \
9a4816af 2894 sh_register_move_cost ((MODE), (SRCCLASS), (DSTCLASS))
85256f8a
JW		 2895
2896/* ??? Perhaps make MEMORY_MOVE_COST depend on compiler option? This
ec4c28e5 2897 would be so that people with slow memory systems could generate
85256f8a 2898 different code that does fewer memory accesses. */
ec4c28e5
R		 2899
2900/* A C expression for the cost of a branch instruction. A value of 1
2901 is the default; other values are interpreted relative to that.
2902 The SH1 does not have delay slots, hence we get a pipeline stall
2903 at every branch. The SH4 is superscalar, so the single delay slot
7df87939 2904 is not sufficient to keep both pipelines filled. */
fa5322fa 2905#define BRANCH_COST (TARGET_SH5 ? 1 : ! TARGET_SH2 || TARGET_HARD_SH4 ? 2 : 1)
bc45ade3 2906\f
994295f2 2907/* Assembler output control. */
bc45ade3 2908
17b65371
DE		 2909/* A C string constant describing how to begin a comment in the target
2910 assembler language. The compiler assumes that the comment will end at
2911 the end of the line. */
2912#define ASM_COMMENT_START "!"
2913
0d7e008e
SC		 2914#define ASM_APP_ON ""
2915#define ASM_APP_OFF ""
2916#define FILE_ASM_OP "\t.file\n"
471b6f1b 2917#define SET_ASM_OP "\t.set\t"
bc45ade3 2918
994295f2 2919/* How to change between sections. */
bc45ade3 2920
fa5322fa 2921#define TEXT_SECTION_ASM_OP (TARGET_SHMEDIA32 ? "\t.section\t.text..SHmedia32,\"ax\"" : "\t.text")
8e87e161 2922#define DATA_SECTION_ASM_OP "\t.data"
b9654711 2923
fa5322fa
AO		 2924#if defined CRT_BEGIN || defined CRT_END
2925/* Arrange for TEXT_SECTION_ASM_OP to be a compile-time constant. */
2926# undef TEXT_SECTION_ASM_OP
2927# if __SHMEDIA__ == 1 && __SH5__ == 32
2928# define TEXT_SECTION_ASM_OP "\t.section\t.text..SHmedia32,\"ax\""
2929# else
2930# define TEXT_SECTION_ASM_OP "\t.text"
2931# endif
2932#endif
2933
2934
48b1580e
VM		 2935/* If defined, a C expression whose value is a string containing the
2936 assembler operation to identify the following data as
2937 uninitialized global data. If not defined, and neither
2938 `ASM_OUTPUT_BSS' nor `ASM_OUTPUT_ALIGNED_BSS' are defined,
2939 uninitialized global data will be output in the data section if
2940 `-fno-common' is passed, otherwise `ASM_OUTPUT_COMMON' will be
2941 used. */
2942#ifndef BSS_SECTION_ASM_OP
471b6f1b 2943#define BSS_SECTION_ASM_OP "\t.section\t.bss"
48b1580e
VM		 2944#endif
2945
2946/* Like `ASM_OUTPUT_BSS' except takes the required alignment as a
2947 separate, explicit argument. If you define this macro, it is used
2948 in place of `ASM_OUTPUT_BSS', and gives you more flexibility in
2949 handling the required alignment of the variable. The alignment is
2950 specified as the number of bits.
2951
2952 Try to use function `asm_output_aligned_bss' defined in file
6f317ef3 2953 `varasm.c' when defining this macro. */
48b1580e
VM		 2954#ifndef ASM_OUTPUT_ALIGNED_BSS
2955#define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
2956 asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN)
2957#endif
2958
e115e436
JW		 2959/* Define this so that jump tables go in same section as the current function,
2960 which could be text or it could be a user defined section. */
75197b37 2961#define JUMP_TABLES_IN_TEXT_SECTION 1
e115e436 2962
994295f2 2963#undef DO_GLOBAL_CTORS_BODY
b9654711
SC		 2964#define DO_GLOBAL_CTORS_BODY \
2965{ \
2966 typedef (*pfunc)(); \
2967 extern pfunc __ctors[]; \
2968 extern pfunc __ctors_end[]; \
2969 pfunc *p; \
c1fe41cb 2970 for (p = __ctors_end; p > __ctors; ) \
b9654711 2971 { \
c1fe41cb 2972 (*--p)(); \
b9654711 2973 } \
994295f2 2974}
b9654711 2975
994295f2 2976#undef DO_GLOBAL_DTORS_BODY
c5d67833 2977#define DO_GLOBAL_DTORS_BODY \
b9654711
SC		 2978{ \
2979 typedef (*pfunc)(); \
2980 extern pfunc __dtors[]; \
2981 extern pfunc __dtors_end[]; \
2982 pfunc *p; \
2983 for (p = __dtors; p < __dtors_end; p++) \
2984 { \
2985 (*p)(); \
2986 } \
994295f2 2987}
b9654711 2988
b9654711 2989#define ASM_OUTPUT_REG_PUSH(file, v) \
2e71ae82 2990 fprintf ((file), "\tmov.l\tr%d,@-r15\n", (v));
bc45ade3 2991
b9654711 2992#define ASM_OUTPUT_REG_POP(file, v) \
318881c0 2993 fprintf ((file), "\tmov.l\t@r15+,r%d\n", (v));
b9654711 2994
994295f2 2995/* DBX register number for a given compiler register number. */
5c3ea805
JW		 2996/* GDB has FPUL at 23 and FP0 at 25, so we must add one to all FP registers
2997 to match gdb. */
1951818c
R		 2998/* svr4.h undefines this macro, yet we really want to use the same numbers
2999 for coff as for elf, so we go via another macro: SH_DBX_REGISTER_NUMBER. */
4977bab6
ZW		 3000/* expand_builtin_init_dwarf_reg_sizes uses this to test if a
3001 register exists, so we should return -1 for invalid register numbers. */
1951818c
R		 3002#define DBX_REGISTER_NUMBER(REGNO) SH_DBX_REGISTER_NUMBER (REGNO)
3003
b869f904
R		 3004/* SHcompact PR_REG used to use the encoding 241, and SHcompact FP registers
3005 used to use the encodings 245..260, but that doesn't make sense:
3006 PR_REG and PR_MEDIA_REG are actually the same register, and likewise
3007 the FP registers stay the same when switching between compact and media
839a4992 3008 mode. Hence, we also need to use the same dwarf frame columns.
b869f904
R		 3009 Likewise, we need to support unwind information for SHmedia registers
3010 even in compact code. */
1951818c 3011#define SH_DBX_REGISTER_NUMBER(REGNO) \
b869f904
R		 3012 (IN_RANGE ((REGNO), \
3013 (unsigned HOST_WIDE_INT) FIRST_GENERAL_REG, \
3014 FIRST_GENERAL_REG + (TARGET_SH5 ? 63U :15U)) \
fada1961 3015 ? ((unsigned) (REGNO) - FIRST_GENERAL_REG) \
b869f904
R		 3016 : ((int) (REGNO) >= FIRST_FP_REG \
3017 && ((int) (REGNO) \
3018 <= (FIRST_FP_REG + \
3019 ((TARGET_SH5 && TARGET_FPU_ANY) ? 63 : TARGET_SH2E ? 15 : -1)))) \
fada1961 3020 ? ((unsigned) (REGNO) - FIRST_FP_REG \
b869f904 3021 + (TARGET_SH5 ? 77 : 25)) \
fa5322fa 3022 : XD_REGISTER_P (REGNO) \
fada1961 3023 ? ((unsigned) (REGNO) - FIRST_XD_REG + (TARGET_SH5 ? 289 : 87)) \
fa5322fa 3024 : TARGET_REGISTER_P (REGNO) \
fada1961 3025 ? ((unsigned) (REGNO) - FIRST_TARGET_REG + 68) \
fa5322fa 3026 : (REGNO) == PR_REG \
b869f904 3027 ? (TARGET_SH5 ? 18 : 17) \
8d6b008d 3028 : (REGNO) == PR_MEDIA_REG \
fada1961 3029 ? (TARGET_SH5 ? 18 : (unsigned) -1) \
fa5322fa
AO		 3030 : (REGNO) == T_REG \
3031 ? (TARGET_SH5 ? 242 : 18) \
3032 : (REGNO) == GBR_REG \
3033 ? (TARGET_SH5 ? 238 : 19) \
3034 : (REGNO) == MACH_REG \
3035 ? (TARGET_SH5 ? 239 : 20) \
3036 : (REGNO) == MACL_REG \
3037 ? (TARGET_SH5 ? 240 : 21) \
3038 : (REGNO) == FPUL_REG \
3039 ? (TARGET_SH5 ? 244 : 23) \
fada1961 3040 : (unsigned) -1)
fa5322fa 3041
fa5322fa
AO		 3042/* This is how to output a reference to a symbol_ref. On SH5,
3043 references to non-code symbols must be preceded by `datalabel'. */
3044#define ASM_OUTPUT_SYMBOL_REF(FILE,SYM) \
3045 do \
3046 { \
675ff4c7 3047 if (TARGET_SH5 && !SYMBOL_REF_FUNCTION_P (SYM)) \
fa5322fa
AO		 3048 fputs ("datalabel ", (FILE)); \
3049 assemble_name ((FILE), XSTR ((SYM), 0)); \
3050 } \
3051 while (0)
bc45ade3 3052
bc45ade3
SC		 3053/* This is how to output an assembler line
3054 that says to advance the location counter
3055 to a multiple of 2**LOG bytes. */
3056
3057#define ASM_OUTPUT_ALIGN(FILE,LOG) \
3058 if ((LOG) != 0) \
e9a25f70 3059 fprintf ((FILE), "\t.align %d\n", (LOG))
bc45ade3 3060
506a61b1
KG		 3061/* Globalizing directive for a label. */
3062#define GLOBAL_ASM_OP "\t.global\t"
bc45ade3 3063
bc45ade3
SC		 3064/* #define ASM_OUTPUT_CASE_END(STREAM,NUM,TABLE) */
3065
994295f2 3066/* Output a relative address table. */
bc1ebe63 3067
33f7f353
JR		 3068#define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM,BODY,VALUE,REL) \
3069 switch (GET_MODE (BODY)) \
e9a25f70
JL		 3070 { \
3071 case SImode: \
fa5322fa
AO		 3072 if (TARGET_SH5) \
3073 { \
3074 asm_fprintf ((STREAM), "\t.long\t%LL%d-datalabel %LL%d\n", \
3075 (VALUE), (REL)); \
3076 break; \
3077 } \
e9a25f70
JL		 3078 asm_fprintf ((STREAM), "\t.long\t%LL%d-%LL%d\n", (VALUE),(REL)); \
3079 break; \
3080 case HImode: \
fa5322fa
AO		 3081 if (TARGET_SH5) \
3082 { \
3083 asm_fprintf ((STREAM), "\t.word\t%LL%d-datalabel %LL%d\n", \
3084 (VALUE), (REL)); \
3085 break; \
3086 } \
e9a25f70
JL		 3087 asm_fprintf ((STREAM), "\t.word\t%LL%d-%LL%d\n", (VALUE),(REL)); \
3088 break; \
3089 case QImode: \
fa5322fa
AO		 3090 if (TARGET_SH5) \
3091 { \
3092 asm_fprintf ((STREAM), "\t.byte\t%LL%d-datalabel %LL%d\n", \
3093 (VALUE), (REL)); \
3094 break; \
3095 } \
e9a25f70
JL		 3096 asm_fprintf ((STREAM), "\t.byte\t%LL%d-%LL%d\n", (VALUE),(REL)); \
3097 break; \
318881c0
KG		 3098 default: \
3099 break; \
e9a25f70 3100 }
bc45ade3 3101
994295f2 3102/* Output an absolute table element. */
0d7e008e
SC		 3103
3104#define ASM_OUTPUT_ADDR_VEC_ELT(STREAM,VALUE) \
8b26829f 3105 if (! optimize || TARGET_BIGTABLE) \
f1a58d92 3106 asm_fprintf ((STREAM), "\t.long\t%LL%d\n", (VALUE)); \
0d7e008e 3107 else \
f1a58d92 3108 asm_fprintf ((STREAM), "\t.word\t%LL%d\n", (VALUE));
bc45ade3 3109
bc45ade3 3110\f
e9a25f70
JL		 3111/* A C statement to be executed just prior to the output of
3112 assembler code for INSN, to modify the extracted operands so
3113 they will be output differently.
3114
3115 Here the argument OPVEC is the vector containing the operands
3116 extracted from INSN, and NOPERANDS is the number of elements of
3117 the vector which contain meaningful data for this insn.
3118 The contents of this vector are what will be used to convert the insn
3119 template into assembler code, so you can change the assembler output
3120 by changing the contents of the vector. */
3121
c5d67833 3122#define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
e9a25f70 3123 final_prescan_insn ((INSN), (OPVEC), (NOPERANDS))
bc45ade3
SC		 3124
3125/* Print operand X (an rtx) in assembler syntax to file FILE.
3126 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
3127 For `%' followed by punctuation, CODE is the punctuation and X is null. */
3128
e9a25f70 3129#define PRINT_OPERAND(STREAM, X, CODE) print_operand ((STREAM), (X), (CODE))
bc45ade3
SC		 3130
3131/* Print a memory address as an operand to reference that memory location. */
3132
e9a25f70 3133#define PRINT_OPERAND_ADDRESS(STREAM,X) print_operand_address ((STREAM), (X))
bc45ade3
SC		 3134
3135#define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
e9a25f70 3136 ((CHAR) == '.' || (CHAR) == '#' || (CHAR) == '@' || (CHAR) == ',' \
c8cc4417 3137 || (CHAR) == '$'|| (CHAR) == '\'')
422be3c3
AO		 3138
3139/* Recognize machine-specific patterns that may appear within
3140 constants. Used for PIC-specific UNSPECs. */
3141#define OUTPUT_ADDR_CONST_EXTRA(STREAM, X, FAIL) \
3142 do \
fa5322fa 3143 if (GET_CODE (X) == UNSPEC && XVECLEN ((X), 0) == 1) \
422be3c3
AO		 3144 { \
3145 switch (XINT ((X), 1)) \
3146 { \
fa5322fa
AO		 3147 case UNSPEC_DATALABEL: \
3148 fputs ("datalabel ", (STREAM)); \
3149 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3150 break; \
422be3c3
AO		 3151 case UNSPEC_PIC: \
3152 /* GLOBAL_OFFSET_TABLE or local symbols, no suffix. */ \
3153 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3154 break; \
3155 case UNSPEC_GOT: \
3156 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3157 fputs ("@GOT", (STREAM)); \
3158 break; \
3159 case UNSPEC_GOTOFF: \
3160 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3161 fputs ("@GOTOFF", (STREAM)); \
3162 break; \
3163 case UNSPEC_PLT: \
3164 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3165 fputs ("@PLT", (STREAM)); \
3166 break; \
fa5322fa
AO		 3167 case UNSPEC_GOTPLT: \
3168 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3169 fputs ("@GOTPLT", (STREAM)); \
3170 break; \
463f02cd
KK		 3171 case UNSPEC_DTPOFF: \
3172 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3173 fputs ("@DTPOFF", (STREAM)); \
3174 break; \
3175 case UNSPEC_GOTTPOFF: \
3176 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3177 fputs ("@GOTTPOFF", (STREAM)); \
3178 break; \
3179 case UNSPEC_TPOFF: \
3180 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3181 fputs ("@TPOFF", (STREAM)); \
3182 break; \
2d01e445
AO		 3183 case UNSPEC_CALLER: \
3184 { \
3185 char name[32]; \
3186 /* LPCS stands for Label for PIC Call Site. */ \
3187 ASM_GENERATE_INTERNAL_LABEL \
f00018dd 3188 (name, "LPCS", INTVAL (XVECEXP ((X), 0, 0))); \
2d01e445
AO		 3189 assemble_name ((STREAM), name); \
3190 } \
3191 break; \
422be3c3
AO		 3192 default: \
3193 goto FAIL; \
3194 } \
3195 break; \
3196 } \
3197 else \
3198 goto FAIL; \
3199 while (0)
3200
bc45ade3 3201\f
bc45ade3
SC		 3202extern struct rtx_def *sh_compare_op0;
3203extern struct rtx_def *sh_compare_op1;
bc45ade3 3204
994295f2
JW		 3205/* Which processor to schedule for. The elements of the enumeration must
3206 match exactly the cpu attribute in the sh.md file. */
bc45ade3 3207
994295f2 3208enum processor_type {
994295f2
JW		 3209 PROCESSOR_SH1,
3210 PROCESSOR_SH2,
3a8699c7 3211 PROCESSOR_SH2E,
5c3ea805 3212 PROCESSOR_SH3,
225e4f43 3213 PROCESSOR_SH3E,
fa5322fa
AO		 3214 PROCESSOR_SH4,
3215 PROCESSOR_SH5
994295f2
JW		 3216};
3217
3218#define sh_cpu_attr ((enum attr_cpu)sh_cpu)
3219extern enum processor_type sh_cpu;
3220
33f7f353
JR		 3221extern int optimize; /* needed for gen_casesi. */
3222
e9a25f70
JL		 3223enum mdep_reorg_phase_e
3224{
3225 SH_BEFORE_MDEP_REORG,
3226 SH_INSERT_USES_LABELS,
3227 SH_SHORTEN_BRANCHES0,
3228 SH_FIXUP_PCLOAD,
3229 SH_SHORTEN_BRANCHES1,
3230 SH_AFTER_MDEP_REORG
3231};
3232
33f7f353
JR		 3233extern enum mdep_reorg_phase_e mdep_reorg_phase;
3234
c8f0269d 3235/* Handle Renesas compiler's pragmas. */
c58b209a
NB		 3236#define REGISTER_TARGET_PRAGMAS() do { \
3237 c_register_pragma (0, "interrupt", sh_pr_interrupt); \
3238 c_register_pragma (0, "trapa", sh_pr_trapa); \
3239 c_register_pragma (0, "nosave_low_regs", sh_pr_nosave_low_regs); \
8b97c5f8 3240} while (0)
b9654711 3241
994295f2 3242/* Set when processing a function with pragma interrupt turned on. */
b9654711 3243
0d7e008e 3244extern int pragma_interrupt;
b9654711 3245
552ecbd9
AH		 3246/* Set when processing a function with interrupt attribute. */
3247
3248extern int current_function_interrupt;
3249
4408efce
JL		 3250/* Set to an RTX containing the address of the stack to switch to
3251 for interrupt functions. */
3252extern struct rtx_def *sp_switch;
3253
225e4f43 3254extern int rtx_equal_function_value_matters;
225e4f43 3255
b52cd365 3256\f
9342c0c4
R		 3257/* Instructions with unfilled delay slots take up an
3258 extra two bytes for the nop in the delay slot.
3259 sh-dsp parallel processing insns are four bytes long. */
b52cd365
JW		 3260
3261#define ADJUST_INSN_LENGTH(X, LENGTH) \
9342c0c4 3262 (LENGTH) += sh_insn_length_adjustment (X);
c5d67833
JW		 3263\f
3264/* Define the codes that are matched by predicates in sh.c. */
3265#define PREDICATE_CODES \
c1b92d09 3266 {"and_operand", {SUBREG, REG, CONST_INT}}, \
e69d1422 3267 {"any_register_operand", {SUBREG, REG}}, \
c5d67833 3268 {"arith_operand", {SUBREG, REG, CONST_INT}}, \
c1b92d09 3269 {"arith_reg_dest", {SUBREG, REG}}, \
e9a25f70 3270 {"arith_reg_operand", {SUBREG, REG}}, \
52702ae1 3271 {"arith_reg_or_0_operand", {SUBREG, REG, CONST_INT, CONST_VECTOR}}, \
0ac78517 3272 {"binary_float_operator", {PLUS, MINUS, MULT, DIV}}, \
ff881d52 3273 {"binary_logical_operator", {AND, IOR, XOR}}, \
3db1b434 3274 {"cmpsi_operand", {SUBREG, REG, CONST_INT}}, \
225e4f43 3275 {"commutative_float_operator", {PLUS, MULT}}, \
c8cc4417 3276 {"equality_comparison_operator", {EQ,NE}}, \
c1b92d09
R		 3277 {"extend_reg_operand", {SUBREG, REG, TRUNCATE}}, \
3278 {"extend_reg_or_0_operand", {SUBREG, REG, TRUNCATE, CONST_INT}}, \
225e4f43 3279 {"fp_arith_reg_operand", {SUBREG, REG}}, \
225e4f43 3280 {"fpscr_operand", {REG}}, \
4b9580a5 3281 {"fpul_operand", {REG}}, \
b6d33983 3282 {"general_extend_operand", {SUBREG, REG, MEM, TRUNCATE}}, \
ae0a1c23
AO		 3283 {"general_movsrc_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE, MEM}}, \
3284 {"general_movdst_operand", {SUBREG, REG, MEM}}, \
c8cc4417 3285 {"greater_comparison_operator", {GT,GE,GTU,GEU}}, \
e69d1422 3286 {"int_gpr_dest", {SUBREG, REG}}, \
b6d33983 3287 {"inqhi_operand", {TRUNCATE}}, \
c8cc4417 3288 {"less_comparison_operator", {LT,LE,LTU,LEU}}, \
e9a25f70 3289 {"logical_operand", {SUBREG, REG, CONST_INT}}, \
c1b92d09 3290 {"mextr_bit_offset", {CONST_INT}}, \
225e4f43 3291 {"noncommutative_float_operator", {MINUS, DIV}}, \
fa5322fa 3292 {"shmedia_6bit_operand", {SUBREG, REG, CONST_INT}}, \
d9da94a1 3293 {"sh_register_operand", {REG, SUBREG, CONST_INT}}, \
fa5322fa 3294 {"target_reg_operand", {SUBREG, REG}}, \
c1b92d09 3295 {"target_operand", {SUBREG, REG, LABEL_REF, SYMBOL_REF, CONST, UNSPEC}},\
e69d1422 3296 {"trunc_hi_operand", {SUBREG, REG, TRUNCATE}}, \
2d01e445 3297 {"register_operand", {SUBREG, REG}}, \
c1b92d09
R		 3298 {"sh_const_vec", {CONST_VECTOR}}, \
3299 {"sh_1el_vec", {CONST_VECTOR, PARALLEL}}, \
3300 {"sh_rep_vec", {CONST_VECTOR, PARALLEL}}, \
3301 {"symbol_ref_operand", {SYMBOL_REF}}, \
0ac78517 3302 {"unary_float_operator", {ABS, NEG, SQRT}}, \
c5d67833 3303
e69d1422
R		 3304#define SPECIAL_MODE_PREDICATES \
3305 "any_register_operand", \
3306 "int_gpr_dest", \
3307 "trunc_hi_operand", \
3308 /* This line intentionally left blank. */
3309
3310#define any_register_operand register_operand
3311
c5d67833 3312/* Define this macro if it is advisable to hold scalars in registers
73774972 3313 in a wider mode than that declared by the program. In such cases,
c5d67833
JW		 3314 the value is constrained to be within the bounds of the declared
3315 type, but kept valid in the wider mode. The signedness of the
3316 extension may differ from that of the type.
3317
3318 Leaving the unsignedp unchanged gives better code than always setting it
3319 to 0. This is despite the fact that we have only signed char and short
3320 load instructions. */
3321#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
3322 if (GET_MODE_CLASS (MODE) == MODE_INT \
3323 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
fa5322fa
AO		 3324 (UNSIGNEDP) = ((MODE) == SImode ? 0 : (UNSIGNEDP)), \
3325 (MODE) = (TARGET_SH1 ? SImode : DImode);
c5d67833 3326
dcb44500
R		 3327#define MAX_FIXED_MODE_SIZE (TARGET_SH5 ? 128 : 64)
3328
c5d67833 3329/* ??? Define ACCUMULATE_OUTGOING_ARGS? This is more efficient than pushing
2067c116 3330 and popping arguments. However, we do have push/pop instructions, and
c5d67833
JW		 3331 rather limited offsets (4 bits) in load/store instructions, so it isn't
3332 clear if this would give better code. If implemented, should check for
3333 compatibility problems. */
3334
225e4f43
R		 3335#define SH_DYNAMIC_SHIFT_COST \
3336 (TARGET_HARD_SH4 ? 1 : TARGET_SH3 ? (TARGET_SMALLCODE ? 1 : 2) : 20)
9f09b1f2
R		 3337
3338
3339#define NUM_MODES_FOR_MODE_SWITCHING { FP_MODE_NONE }
3340
3341#define OPTIMIZE_MODE_SWITCHING(ENTITY) TARGET_SH4
3342
5d806217
R		 3343#define ACTUAL_NORMAL_MODE(ENTITY) \
3344 (TARGET_FPU_SINGLE ? FP_MODE_SINGLE : FP_MODE_DOUBLE)
3345
1270c255 3346#define NORMAL_MODE(ENTITY) \
ac55736a
R		 3347 (sh_cfun_interrupt_handler_p () \
3348 ? (TARGET_FMOVD ? FP_MODE_DOUBLE : FP_MODE_NONE) \
5d806217 3349 : ACTUAL_NORMAL_MODE (ENTITY))
1270c255 3350
73774972
EC		 3351#define MODE_ENTRY(ENTITY) NORMAL_MODE (ENTITY)
3352
3353#define MODE_EXIT(ENTITY) \
3354 (sh_cfun_attr_renesas_p () ? FP_MODE_NONE : NORMAL_MODE (ENTITY))
3355
3a8699c7 3356#define EPILOGUE_USES(REGNO) ((TARGET_SH2E || TARGET_SH4) \
616af7ee 3357 && (REGNO) == FPSCR_REG)
9f09b1f2
R		 3358
3359#define MODE_NEEDED(ENTITY, INSN) \
3360 (recog_memoized (INSN) >= 0 \
3361 ? get_attr_fp_mode (INSN) \
9f09b1f2
R		 3362 : FP_MODE_NONE)
3363
73774972 3364#define MODE_AFTER(MODE, INSN) \
bcc8cc82
R		 3365 (TARGET_HITACHI \
3366 && recog_memoized (INSN) >= 0 \
73774972
EC		 3367 && get_attr_fp_set (INSN) != FP_SET_NONE \
3368 ? get_attr_fp_set (INSN) \
3369 : (MODE))
3370
9f09b1f2
R		 3371#define MODE_PRIORITY_TO_MODE(ENTITY, N) \
3372 ((TARGET_FPU_SINGLE != 0) ^ (N) ? FP_MODE_SINGLE : FP_MODE_DOUBLE)
3373
3374#define EMIT_MODE_SET(ENTITY, MODE, HARD_REGS_LIVE) \
3375 fpscr_set_from_mem ((MODE), (HARD_REGS_LIVE))
86f49b02 3376
6e7b03e1
AH		 3377#define MD_CAN_REDIRECT_BRANCH(INSN, SEQ) \
3378 sh_can_redirect_branch ((INSN), (SEQ))
3379
e284643a
R		 3380#define DWARF_FRAME_RETURN_COLUMN \
3381 (TARGET_SH5 ? DWARF_FRAME_REGNUM (PR_MEDIA_REG) : DWARF_FRAME_REGNUM (PR_REG))
2754d3c5 3382
4977bab6 3383#define EH_RETURN_DATA_REGNO(N) \
fada1961 3384 ((N) < 4 ? (N) + (TARGET_SH5 ? 2U : 4U) : INVALID_REGNUM)
4977bab6 3385
fada1961
R		 3386#define EH_RETURN_STACKADJ_REGNO STATIC_CHAIN_REGNUM
3387#define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, EH_RETURN_STACKADJ_REGNO)
4977bab6 3388
b869f904
R		 3389/* We have to distinguish between code and data, so that we apply
3390 datalabel where and only where appropriate. Use textrel for code. */
3391#define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
3392 ((flag_pic && (GLOBAL) ? DW_EH_PE_indirect : 0) \
3393 | ((CODE) ? DW_EH_PE_textrel : flag_pic ? DW_EH_PE_pcrel : DW_EH_PE_absptr))
3394
3395/* Handle special EH pointer encodings. Absolute, pc-relative, and
3396 indirect are handled automatically. */
3397#define ASM_MAYBE_OUTPUT_ENCODED_ADDR_RTX(FILE, ENCODING, SIZE, ADDR, DONE) \
3398 do { \
3399 if (((ENCODING) & 0x70) == DW_EH_PE_textrel) \
3400 { \
3401 encoding &= ~DW_EH_PE_textrel; \
3402 encoding |= flag_pic ? DW_EH_PE_pcrel : DW_EH_PE_absptr; \
3403 if (GET_CODE (ADDR) != SYMBOL_REF) \
3404 abort (); \
3405 SYMBOL_REF_FLAGS (ADDR) |= SYMBOL_FLAG_FUNCTION; \
3406 if (0) goto DONE; \
3407 } \
3408 } while (0)
3409
fa5322fa 3410#if (defined CRT_BEGIN || defined CRT_END) && ! __SHMEDIA__
1a66cd67
AO		 3411/* SH constant pool breaks the devices in crtstuff.c to control section
3412 in where code resides. We have to write it as asm code. */
cea3bd3e
RH		 3413#define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
3414 asm (SECTION_OP "\n\
3415 mov.l 1f,r1\n\
1a66cd67
AO		 3416 mova 2f,r0\n\
3417 braf r1\n\
3418 lds r0,pr\n\
34190: .p2align 2\n\
cea3bd3e
RH		 34201: .long " USER_LABEL_PREFIX #FUNC " - 0b\n\
34212:\n" TEXT_SECTION_ASM_OP);
fa5322fa 3422#endif /* (defined CRT_BEGIN || defined CRT_END) && ! __SHMEDIA__ */
8b97c5f8 3423
3007d592 3424#define ALLOCATE_INITIAL_VALUE(hard_reg) \
b869f904
R		 3425 (REGNO (hard_reg) == (TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG) \
3426 ? (current_function_is_leaf \
3427 && ! sh_pr_n_sets () \
3428 && ! (TARGET_SHCOMPACT \
3429 && ((current_function_args_info.call_cookie \
3430 & ~ CALL_COOKIE_RET_TRAMP (1)) \
3431 || current_function_has_nonlocal_label)) \
3007d592 3432 ? (hard_reg) \
e6ff425c 3433 : gen_rtx_MEM (Pmode, return_address_pointer_rtx)) \
3007d592
R		 3434 : NULL_RTX)
3435
88657302 3436#endif /* ! GCC_SH_H */
GNU Compiler Collection
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