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9db1d521 | 1 | /* Subroutines used for code generation on IBM S/390 and zSeries |
5624e564 | 2 | Copyright (C) 1999-2015 Free Software Foundation, Inc. |
9db1d521 | 3 | Contributed by Hartmut Penner (hpenner@de.ibm.com) and |
963fc8d0 AK |
4 | Ulrich Weigand (uweigand@de.ibm.com) and |
5 | Andreas Krebbel (Andreas.Krebbel@de.ibm.com). | |
9db1d521 | 6 | |
58add37a | 7 | This file is part of GCC. |
9db1d521 | 8 | |
58add37a UW |
9 | GCC is free software; you can redistribute it and/or modify it under |
10 | the terms of the GNU General Public License as published by the Free | |
2f83c7d6 | 11 | Software Foundation; either version 3, or (at your option) any later |
58add37a | 12 | version. |
9db1d521 | 13 | |
58add37a UW |
14 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY |
15 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
16 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
17 | for more details. | |
9db1d521 HP |
18 | |
19 | You should have received a copy of the GNU General Public License | |
2f83c7d6 NC |
20 | along with GCC; see the file COPYING3. If not see |
21 | <http://www.gnu.org/licenses/>. */ | |
9db1d521 HP |
22 | |
23 | #include "config.h" | |
9db1d521 | 24 | #include "system.h" |
4977bab6 ZW |
25 | #include "coretypes.h" |
26 | #include "tm.h" | |
9db1d521 | 27 | #include "rtl.h" |
40e23961 MC |
28 | #include "hash-set.h" |
29 | #include "machmode.h" | |
30 | #include "vec.h" | |
31 | #include "double-int.h" | |
32 | #include "input.h" | |
33 | #include "alias.h" | |
34 | #include "symtab.h" | |
35 | #include "wide-int.h" | |
36 | #include "inchash.h" | |
9db1d521 | 37 | #include "tree.h" |
40e23961 | 38 | #include "fold-const.h" |
d8a2d370 DN |
39 | #include "print-tree.h" |
40 | #include "stringpool.h" | |
41 | #include "stor-layout.h" | |
42 | #include "varasm.h" | |
43 | #include "calls.h" | |
9db1d521 HP |
44 | #include "tm_p.h" |
45 | #include "regs.h" | |
46 | #include "hard-reg-set.h" | |
9db1d521 HP |
47 | #include "insn-config.h" |
48 | #include "conditions.h" | |
49 | #include "output.h" | |
50 | #include "insn-attr.h" | |
51 | #include "flags.h" | |
52 | #include "except.h" | |
53 | #include "function.h" | |
54 | #include "recog.h" | |
36566b39 PK |
55 | #include "hashtab.h" |
56 | #include "statistics.h" | |
57 | #include "real.h" | |
58 | #include "fixed-value.h" | |
59 | #include "expmed.h" | |
60 | #include "dojump.h" | |
61 | #include "explow.h" | |
62 | #include "emit-rtl.h" | |
63 | #include "stmt.h" | |
9db1d521 | 64 | #include "expr.h" |
7c82a1ed | 65 | #include "reload.h" |
718f9c0f | 66 | #include "diagnostic-core.h" |
60393bbc AM |
67 | #include "predict.h" |
68 | #include "dominance.h" | |
69 | #include "cfg.h" | |
70 | #include "cfgrtl.h" | |
71 | #include "cfganal.h" | |
72 | #include "lcm.h" | |
73 | #include "cfgbuild.h" | |
74 | #include "cfgcleanup.h" | |
9db1d521 HP |
75 | #include "basic-block.h" |
76 | #include "ggc.h" | |
77 | #include "target.h" | |
78 | #include "target-def.h" | |
0d3c08b6 | 79 | #include "debug.h" |
f1e639b1 | 80 | #include "langhooks.h" |
b0710fe1 | 81 | #include "insn-codes.h" |
a41c6c53 | 82 | #include "optabs.h" |
2fb9a547 | 83 | #include "hash-table.h" |
2fb9a547 AM |
84 | #include "tree-ssa-alias.h" |
85 | #include "internal-fn.h" | |
86 | #include "gimple-fold.h" | |
87 | #include "tree-eh.h" | |
88 | #include "gimple-expr.h" | |
89 | #include "is-a.h" | |
18f429e2 | 90 | #include "gimple.h" |
45b0be94 | 91 | #include "gimplify.h" |
6fb5fa3c | 92 | #include "df.h" |
ff5b964d | 93 | #include "params.h" |
40ac4f73 | 94 | #include "cfgloop.h" |
96e45421 | 95 | #include "opts.h" |
4099494d RS |
96 | #include "tree-pass.h" |
97 | #include "context.h" | |
9b2b7279 | 98 | #include "builtins.h" |
9dc7a9da | 99 | #include "rtl-iter.h" |
085261c8 AK |
100 | #include "intl.h" |
101 | #include "plugin-api.h" | |
102 | #include "ipa-ref.h" | |
103 | #include "cgraph.h" | |
9db1d521 | 104 | |
017e0eb9 MD |
105 | /* Define the specific costs for a given cpu. */ |
106 | ||
f4aa3848 | 107 | struct processor_costs |
017e0eb9 | 108 | { |
98fd0d70 | 109 | /* multiplication */ |
017e0eb9 MD |
110 | const int m; /* cost of an M instruction. */ |
111 | const int mghi; /* cost of an MGHI instruction. */ | |
112 | const int mh; /* cost of an MH instruction. */ | |
113 | const int mhi; /* cost of an MHI instruction. */ | |
2742a1ed | 114 | const int ml; /* cost of an ML instruction. */ |
017e0eb9 MD |
115 | const int mr; /* cost of an MR instruction. */ |
116 | const int ms; /* cost of an MS instruction. */ | |
117 | const int msg; /* cost of an MSG instruction. */ | |
118 | const int msgf; /* cost of an MSGF instruction. */ | |
119 | const int msgfr; /* cost of an MSGFR instruction. */ | |
120 | const int msgr; /* cost of an MSGR instruction. */ | |
121 | const int msr; /* cost of an MSR instruction. */ | |
122 | const int mult_df; /* cost of multiplication in DFmode. */ | |
f61a2c7d | 123 | const int mxbr; |
98fd0d70 | 124 | /* square root */ |
f61a2c7d | 125 | const int sqxbr; /* cost of square root in TFmode. */ |
2742a1ed MD |
126 | const int sqdbr; /* cost of square root in DFmode. */ |
127 | const int sqebr; /* cost of square root in SFmode. */ | |
98fd0d70 | 128 | /* multiply and add */ |
b75d6bab MD |
129 | const int madbr; /* cost of multiply and add in DFmode. */ |
130 | const int maebr; /* cost of multiply and add in SFmode. */ | |
98fd0d70 | 131 | /* division */ |
f61a2c7d | 132 | const int dxbr; |
98fd0d70 | 133 | const int ddbr; |
98fd0d70 | 134 | const int debr; |
6fa5b390 MD |
135 | const int dlgr; |
136 | const int dlr; | |
137 | const int dr; | |
138 | const int dsgfr; | |
139 | const int dsgr; | |
017e0eb9 MD |
140 | }; |
141 | ||
142 | const struct processor_costs *s390_cost; | |
143 | ||
144 | static const | |
f4aa3848 | 145 | struct processor_costs z900_cost = |
017e0eb9 MD |
146 | { |
147 | COSTS_N_INSNS (5), /* M */ | |
148 | COSTS_N_INSNS (10), /* MGHI */ | |
149 | COSTS_N_INSNS (5), /* MH */ | |
150 | COSTS_N_INSNS (4), /* MHI */ | |
2742a1ed | 151 | COSTS_N_INSNS (5), /* ML */ |
017e0eb9 MD |
152 | COSTS_N_INSNS (5), /* MR */ |
153 | COSTS_N_INSNS (4), /* MS */ | |
154 | COSTS_N_INSNS (15), /* MSG */ | |
155 | COSTS_N_INSNS (7), /* MSGF */ | |
156 | COSTS_N_INSNS (7), /* MSGFR */ | |
157 | COSTS_N_INSNS (10), /* MSGR */ | |
158 | COSTS_N_INSNS (4), /* MSR */ | |
159 | COSTS_N_INSNS (7), /* multiplication in DFmode */ | |
f61a2c7d AK |
160 | COSTS_N_INSNS (13), /* MXBR */ |
161 | COSTS_N_INSNS (136), /* SQXBR */ | |
2742a1ed MD |
162 | COSTS_N_INSNS (44), /* SQDBR */ |
163 | COSTS_N_INSNS (35), /* SQEBR */ | |
b75d6bab MD |
164 | COSTS_N_INSNS (18), /* MADBR */ |
165 | COSTS_N_INSNS (13), /* MAEBR */ | |
f61a2c7d | 166 | COSTS_N_INSNS (134), /* DXBR */ |
98fd0d70 | 167 | COSTS_N_INSNS (30), /* DDBR */ |
98fd0d70 | 168 | COSTS_N_INSNS (27), /* DEBR */ |
6fa5b390 MD |
169 | COSTS_N_INSNS (220), /* DLGR */ |
170 | COSTS_N_INSNS (34), /* DLR */ | |
171 | COSTS_N_INSNS (34), /* DR */ | |
172 | COSTS_N_INSNS (32), /* DSGFR */ | |
173 | COSTS_N_INSNS (32), /* DSGR */ | |
017e0eb9 MD |
174 | }; |
175 | ||
176 | static const | |
f4aa3848 | 177 | struct processor_costs z990_cost = |
017e0eb9 MD |
178 | { |
179 | COSTS_N_INSNS (4), /* M */ | |
180 | COSTS_N_INSNS (2), /* MGHI */ | |
181 | COSTS_N_INSNS (2), /* MH */ | |
182 | COSTS_N_INSNS (2), /* MHI */ | |
2742a1ed | 183 | COSTS_N_INSNS (4), /* ML */ |
017e0eb9 MD |
184 | COSTS_N_INSNS (4), /* MR */ |
185 | COSTS_N_INSNS (5), /* MS */ | |
186 | COSTS_N_INSNS (6), /* MSG */ | |
187 | COSTS_N_INSNS (4), /* MSGF */ | |
188 | COSTS_N_INSNS (4), /* MSGFR */ | |
189 | COSTS_N_INSNS (4), /* MSGR */ | |
190 | COSTS_N_INSNS (4), /* MSR */ | |
191 | COSTS_N_INSNS (1), /* multiplication in DFmode */ | |
f61a2c7d AK |
192 | COSTS_N_INSNS (28), /* MXBR */ |
193 | COSTS_N_INSNS (130), /* SQXBR */ | |
2742a1ed MD |
194 | COSTS_N_INSNS (66), /* SQDBR */ |
195 | COSTS_N_INSNS (38), /* SQEBR */ | |
b75d6bab MD |
196 | COSTS_N_INSNS (1), /* MADBR */ |
197 | COSTS_N_INSNS (1), /* MAEBR */ | |
f61a2c7d | 198 | COSTS_N_INSNS (60), /* DXBR */ |
98fd0d70 | 199 | COSTS_N_INSNS (40), /* DDBR */ |
142cd70f | 200 | COSTS_N_INSNS (26), /* DEBR */ |
6fa5b390 MD |
201 | COSTS_N_INSNS (176), /* DLGR */ |
202 | COSTS_N_INSNS (31), /* DLR */ | |
203 | COSTS_N_INSNS (31), /* DR */ | |
204 | COSTS_N_INSNS (31), /* DSGFR */ | |
205 | COSTS_N_INSNS (31), /* DSGR */ | |
017e0eb9 MD |
206 | }; |
207 | ||
ec24698e | 208 | static const |
f4aa3848 | 209 | struct processor_costs z9_109_cost = |
ec24698e UW |
210 | { |
211 | COSTS_N_INSNS (4), /* M */ | |
212 | COSTS_N_INSNS (2), /* MGHI */ | |
213 | COSTS_N_INSNS (2), /* MH */ | |
214 | COSTS_N_INSNS (2), /* MHI */ | |
215 | COSTS_N_INSNS (4), /* ML */ | |
216 | COSTS_N_INSNS (4), /* MR */ | |
217 | COSTS_N_INSNS (5), /* MS */ | |
218 | COSTS_N_INSNS (6), /* MSG */ | |
219 | COSTS_N_INSNS (4), /* MSGF */ | |
220 | COSTS_N_INSNS (4), /* MSGFR */ | |
221 | COSTS_N_INSNS (4), /* MSGR */ | |
222 | COSTS_N_INSNS (4), /* MSR */ | |
223 | COSTS_N_INSNS (1), /* multiplication in DFmode */ | |
f61a2c7d AK |
224 | COSTS_N_INSNS (28), /* MXBR */ |
225 | COSTS_N_INSNS (130), /* SQXBR */ | |
ec24698e UW |
226 | COSTS_N_INSNS (66), /* SQDBR */ |
227 | COSTS_N_INSNS (38), /* SQEBR */ | |
228 | COSTS_N_INSNS (1), /* MADBR */ | |
229 | COSTS_N_INSNS (1), /* MAEBR */ | |
f61a2c7d | 230 | COSTS_N_INSNS (60), /* DXBR */ |
ec24698e | 231 | COSTS_N_INSNS (40), /* DDBR */ |
142cd70f | 232 | COSTS_N_INSNS (26), /* DEBR */ |
ec24698e UW |
233 | COSTS_N_INSNS (30), /* DLGR */ |
234 | COSTS_N_INSNS (23), /* DLR */ | |
235 | COSTS_N_INSNS (23), /* DR */ | |
236 | COSTS_N_INSNS (24), /* DSGFR */ | |
237 | COSTS_N_INSNS (24), /* DSGR */ | |
238 | }; | |
017e0eb9 | 239 | |
93538e8e AK |
240 | static const |
241 | struct processor_costs z10_cost = | |
242 | { | |
9381e3f1 WG |
243 | COSTS_N_INSNS (10), /* M */ |
244 | COSTS_N_INSNS (10), /* MGHI */ | |
245 | COSTS_N_INSNS (10), /* MH */ | |
246 | COSTS_N_INSNS (10), /* MHI */ | |
247 | COSTS_N_INSNS (10), /* ML */ | |
248 | COSTS_N_INSNS (10), /* MR */ | |
249 | COSTS_N_INSNS (10), /* MS */ | |
250 | COSTS_N_INSNS (10), /* MSG */ | |
251 | COSTS_N_INSNS (10), /* MSGF */ | |
252 | COSTS_N_INSNS (10), /* MSGFR */ | |
253 | COSTS_N_INSNS (10), /* MSGR */ | |
254 | COSTS_N_INSNS (10), /* MSR */ | |
2cdece44 | 255 | COSTS_N_INSNS (1) , /* multiplication in DFmode */ |
9381e3f1 WG |
256 | COSTS_N_INSNS (50), /* MXBR */ |
257 | COSTS_N_INSNS (120), /* SQXBR */ | |
258 | COSTS_N_INSNS (52), /* SQDBR */ | |
93538e8e | 259 | COSTS_N_INSNS (38), /* SQEBR */ |
2cdece44 WG |
260 | COSTS_N_INSNS (1), /* MADBR */ |
261 | COSTS_N_INSNS (1), /* MAEBR */ | |
9381e3f1 WG |
262 | COSTS_N_INSNS (111), /* DXBR */ |
263 | COSTS_N_INSNS (39), /* DDBR */ | |
264 | COSTS_N_INSNS (32), /* DEBR */ | |
265 | COSTS_N_INSNS (160), /* DLGR */ | |
266 | COSTS_N_INSNS (71), /* DLR */ | |
267 | COSTS_N_INSNS (71), /* DR */ | |
268 | COSTS_N_INSNS (71), /* DSGFR */ | |
269 | COSTS_N_INSNS (71), /* DSGR */ | |
93538e8e AK |
270 | }; |
271 | ||
65b1d8ea AK |
272 | static const |
273 | struct processor_costs z196_cost = | |
274 | { | |
275 | COSTS_N_INSNS (7), /* M */ | |
276 | COSTS_N_INSNS (5), /* MGHI */ | |
277 | COSTS_N_INSNS (5), /* MH */ | |
278 | COSTS_N_INSNS (5), /* MHI */ | |
279 | COSTS_N_INSNS (7), /* ML */ | |
280 | COSTS_N_INSNS (7), /* MR */ | |
281 | COSTS_N_INSNS (6), /* MS */ | |
282 | COSTS_N_INSNS (8), /* MSG */ | |
283 | COSTS_N_INSNS (6), /* MSGF */ | |
284 | COSTS_N_INSNS (6), /* MSGFR */ | |
285 | COSTS_N_INSNS (8), /* MSGR */ | |
286 | COSTS_N_INSNS (6), /* MSR */ | |
287 | COSTS_N_INSNS (1) , /* multiplication in DFmode */ | |
288 | COSTS_N_INSNS (40), /* MXBR B+40 */ | |
289 | COSTS_N_INSNS (100), /* SQXBR B+100 */ | |
290 | COSTS_N_INSNS (42), /* SQDBR B+42 */ | |
291 | COSTS_N_INSNS (28), /* SQEBR B+28 */ | |
292 | COSTS_N_INSNS (1), /* MADBR B */ | |
293 | COSTS_N_INSNS (1), /* MAEBR B */ | |
294 | COSTS_N_INSNS (101), /* DXBR B+101 */ | |
295 | COSTS_N_INSNS (29), /* DDBR */ | |
296 | COSTS_N_INSNS (22), /* DEBR */ | |
297 | COSTS_N_INSNS (160), /* DLGR cracked */ | |
298 | COSTS_N_INSNS (160), /* DLR cracked */ | |
299 | COSTS_N_INSNS (160), /* DR expanded */ | |
300 | COSTS_N_INSNS (160), /* DSGFR cracked */ | |
301 | COSTS_N_INSNS (160), /* DSGR cracked */ | |
302 | }; | |
303 | ||
22ac2c2f AK |
304 | static const |
305 | struct processor_costs zEC12_cost = | |
306 | { | |
307 | COSTS_N_INSNS (7), /* M */ | |
308 | COSTS_N_INSNS (5), /* MGHI */ | |
309 | COSTS_N_INSNS (5), /* MH */ | |
310 | COSTS_N_INSNS (5), /* MHI */ | |
311 | COSTS_N_INSNS (7), /* ML */ | |
312 | COSTS_N_INSNS (7), /* MR */ | |
313 | COSTS_N_INSNS (6), /* MS */ | |
314 | COSTS_N_INSNS (8), /* MSG */ | |
315 | COSTS_N_INSNS (6), /* MSGF */ | |
316 | COSTS_N_INSNS (6), /* MSGFR */ | |
317 | COSTS_N_INSNS (8), /* MSGR */ | |
318 | COSTS_N_INSNS (6), /* MSR */ | |
319 | COSTS_N_INSNS (1) , /* multiplication in DFmode */ | |
320 | COSTS_N_INSNS (40), /* MXBR B+40 */ | |
321 | COSTS_N_INSNS (100), /* SQXBR B+100 */ | |
322 | COSTS_N_INSNS (42), /* SQDBR B+42 */ | |
323 | COSTS_N_INSNS (28), /* SQEBR B+28 */ | |
324 | COSTS_N_INSNS (1), /* MADBR B */ | |
325 | COSTS_N_INSNS (1), /* MAEBR B */ | |
326 | COSTS_N_INSNS (131), /* DXBR B+131 */ | |
327 | COSTS_N_INSNS (29), /* DDBR */ | |
328 | COSTS_N_INSNS (22), /* DEBR */ | |
329 | COSTS_N_INSNS (160), /* DLGR cracked */ | |
330 | COSTS_N_INSNS (160), /* DLR cracked */ | |
331 | COSTS_N_INSNS (160), /* DR expanded */ | |
332 | COSTS_N_INSNS (160), /* DSGFR cracked */ | |
333 | COSTS_N_INSNS (160), /* DSGR cracked */ | |
334 | }; | |
335 | ||
9db1d521 HP |
336 | extern int reload_completed; |
337 | ||
3a892e44 | 338 | /* Kept up to date using the SCHED_VARIABLE_ISSUE hook. */ |
775c43d3 | 339 | static rtx_insn *last_scheduled_insn; |
3a892e44 | 340 | |
994fe660 UW |
341 | /* Structure used to hold the components of a S/390 memory |
342 | address. A legitimate address on S/390 is of the general | |
343 | form | |
344 | base + index + displacement | |
345 | where any of the components is optional. | |
346 | ||
347 | base and index are registers of the class ADDR_REGS, | |
348 | displacement is an unsigned 12-bit immediate constant. */ | |
9db1d521 HP |
349 | |
350 | struct s390_address | |
351 | { | |
352 | rtx base; | |
353 | rtx indx; | |
354 | rtx disp; | |
3ed99cc9 | 355 | bool pointer; |
f01cf809 | 356 | bool literal_pool; |
9db1d521 HP |
357 | }; |
358 | ||
f4aa3848 | 359 | /* The following structure is embedded in the machine |
adf39f8f AK |
360 | specific part of struct function. */ |
361 | ||
d1b38208 | 362 | struct GTY (()) s390_frame_layout |
adf39f8f AK |
363 | { |
364 | /* Offset within stack frame. */ | |
365 | HOST_WIDE_INT gprs_offset; | |
366 | HOST_WIDE_INT f0_offset; | |
367 | HOST_WIDE_INT f4_offset; | |
368 | HOST_WIDE_INT f8_offset; | |
369 | HOST_WIDE_INT backchain_offset; | |
fb3712f6 AK |
370 | |
371 | /* Number of first and last gpr where slots in the register | |
372 | save area are reserved for. */ | |
373 | int first_save_gpr_slot; | |
374 | int last_save_gpr_slot; | |
375 | ||
6455a49e AK |
376 | /* Location (FP register number) where GPRs (r0-r15) should |
377 | be saved to. | |
378 | 0 - does not need to be saved at all | |
379 | -1 - stack slot */ | |
380 | signed char gpr_save_slots[16]; | |
381 | ||
29742ba4 | 382 | /* Number of first and last gpr to be saved, restored. */ |
4023fb28 UW |
383 | int first_save_gpr; |
384 | int first_restore_gpr; | |
385 | int last_save_gpr; | |
b767fc11 | 386 | int last_restore_gpr; |
4023fb28 | 387 | |
f4aa3848 AK |
388 | /* Bits standing for floating point registers. Set, if the |
389 | respective register has to be saved. Starting with reg 16 (f0) | |
adf39f8f | 390 | at the rightmost bit. |
2cf4c39e AK |
391 | Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
392 | fpr 15 13 11 9 14 12 10 8 7 5 3 1 6 4 2 0 | |
393 | reg 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 */ | |
adf39f8f AK |
394 | unsigned int fpr_bitmap; |
395 | ||
396 | /* Number of floating point registers f8-f15 which must be saved. */ | |
397 | int high_fprs; | |
398 | ||
dc4477f5 AK |
399 | /* Set if return address needs to be saved. |
400 | This flag is set by s390_return_addr_rtx if it could not use | |
401 | the initial value of r14 and therefore depends on r14 saved | |
402 | to the stack. */ | |
adf39f8f AK |
403 | bool save_return_addr_p; |
404 | ||
29742ba4 | 405 | /* Size of stack frame. */ |
4023fb28 | 406 | HOST_WIDE_INT frame_size; |
adf39f8f AK |
407 | }; |
408 | ||
409 | /* Define the structure for the machine field in struct function. */ | |
410 | ||
d1b38208 | 411 | struct GTY(()) machine_function |
adf39f8f AK |
412 | { |
413 | struct s390_frame_layout frame_layout; | |
fd3cd001 | 414 | |
585539a1 UW |
415 | /* Literal pool base register. */ |
416 | rtx base_reg; | |
417 | ||
91086990 UW |
418 | /* True if we may need to perform branch splitting. */ |
419 | bool split_branches_pending_p; | |
420 | ||
7bcebb25 | 421 | bool has_landing_pad_p; |
5a3fe9b6 AK |
422 | |
423 | /* True if the current function may contain a tbegin clobbering | |
424 | FPRs. */ | |
425 | bool tbegin_p; | |
4023fb28 UW |
426 | }; |
427 | ||
adf39f8f AK |
428 | /* Few accessor macros for struct cfun->machine->s390_frame_layout. */ |
429 | ||
430 | #define cfun_frame_layout (cfun->machine->frame_layout) | |
431 | #define cfun_save_high_fprs_p (!!cfun_frame_layout.high_fprs) | |
6455a49e AK |
432 | #define cfun_save_arg_fprs_p (!!(TARGET_64BIT \ |
433 | ? cfun_frame_layout.fpr_bitmap & 0x0f \ | |
434 | : cfun_frame_layout.fpr_bitmap & 0x03)) | |
435 | #define cfun_gprs_save_area_size ((cfun_frame_layout.last_save_gpr_slot - \ | |
9602b6a1 | 436 | cfun_frame_layout.first_save_gpr_slot + 1) * UNITS_PER_LONG) |
b89b22fc | 437 | #define cfun_set_fpr_save(REGNO) (cfun->machine->frame_layout.fpr_bitmap |= \ |
2cf4c39e | 438 | (1 << (REGNO - FPR0_REGNUM))) |
b89b22fc | 439 | #define cfun_fpr_save_p(REGNO) (!!(cfun->machine->frame_layout.fpr_bitmap & \ |
2cf4c39e | 440 | (1 << (REGNO - FPR0_REGNUM)))) |
6455a49e AK |
441 | #define cfun_gpr_save_slot(REGNO) \ |
442 | cfun->machine->frame_layout.gpr_save_slots[REGNO] | |
adf39f8f | 443 | |
29a79fcf UW |
444 | /* Number of GPRs and FPRs used for argument passing. */ |
445 | #define GP_ARG_NUM_REG 5 | |
446 | #define FP_ARG_NUM_REG (TARGET_64BIT? 4 : 2) | |
085261c8 | 447 | #define VEC_ARG_NUM_REG 8 |
29a79fcf | 448 | |
b5c67a49 AK |
449 | /* A couple of shortcuts. */ |
450 | #define CONST_OK_FOR_J(x) \ | |
451 | CONST_OK_FOR_CONSTRAINT_P((x), 'J', "J") | |
452 | #define CONST_OK_FOR_K(x) \ | |
453 | CONST_OK_FOR_CONSTRAINT_P((x), 'K', "K") | |
ec24698e UW |
454 | #define CONST_OK_FOR_Os(x) \ |
455 | CONST_OK_FOR_CONSTRAINT_P((x), 'O', "Os") | |
456 | #define CONST_OK_FOR_Op(x) \ | |
457 | CONST_OK_FOR_CONSTRAINT_P((x), 'O', "Op") | |
458 | #define CONST_OK_FOR_On(x) \ | |
459 | CONST_OK_FOR_CONSTRAINT_P((x), 'O', "On") | |
b5c67a49 | 460 | |
74aa8b4b AK |
461 | #define REGNO_PAIR_OK(REGNO, MODE) \ |
462 | (HARD_REGNO_NREGS ((REGNO), (MODE)) == 1 || !((REGNO) & 1)) | |
463 | ||
b0f86a7e | 464 | /* That's the read ahead of the dynamic branch prediction unit in |
65b1d8ea AK |
465 | bytes on a z10 (or higher) CPU. */ |
466 | #define PREDICT_DISTANCE (TARGET_Z10 ? 384 : 2048) | |
b0f86a7e | 467 | |
94091f43 DV |
468 | static const int s390_hotpatch_hw_max = 1000000; |
469 | static int s390_hotpatch_hw_before_label = 0; | |
470 | static int s390_hotpatch_hw_after_label = 0; | |
d0de9e13 DV |
471 | |
472 | /* Check whether the hotpatch attribute is applied to a function and, if it has | |
473 | an argument, the argument is valid. */ | |
474 | ||
475 | static tree | |
476 | s390_handle_hotpatch_attribute (tree *node, tree name, tree args, | |
477 | int flags ATTRIBUTE_UNUSED, bool *no_add_attrs) | |
478 | { | |
94091f43 DV |
479 | tree expr; |
480 | tree expr2; | |
481 | int err; | |
482 | ||
d0de9e13 DV |
483 | if (TREE_CODE (*node) != FUNCTION_DECL) |
484 | { | |
485 | warning (OPT_Wattributes, "%qE attribute only applies to functions", | |
486 | name); | |
487 | *no_add_attrs = true; | |
488 | } | |
94091f43 DV |
489 | if (args != NULL && TREE_CHAIN (args) != NULL) |
490 | { | |
491 | expr = TREE_VALUE (args); | |
492 | expr2 = TREE_VALUE (TREE_CHAIN (args)); | |
493 | } | |
494 | if (args == NULL || TREE_CHAIN (args) == NULL) | |
495 | err = 1; | |
496 | else if (TREE_CODE (expr) != INTEGER_CST | |
497 | || !INTEGRAL_TYPE_P (TREE_TYPE (expr)) | |
498 | || wi::gtu_p (expr, s390_hotpatch_hw_max)) | |
499 | err = 1; | |
500 | else if (TREE_CODE (expr2) != INTEGER_CST | |
501 | || !INTEGRAL_TYPE_P (TREE_TYPE (expr2)) | |
502 | || wi::gtu_p (expr2, s390_hotpatch_hw_max)) | |
503 | err = 1; | |
504 | else | |
505 | err = 0; | |
506 | if (err) | |
d0de9e13 | 507 | { |
94091f43 DV |
508 | error ("requested %qE attribute is not a comma separated pair of" |
509 | " non-negative integer constants or too large (max. %d)", name, | |
510 | s390_hotpatch_hw_max); | |
511 | *no_add_attrs = true; | |
d0de9e13 DV |
512 | } |
513 | ||
514 | return NULL_TREE; | |
515 | } | |
516 | ||
517 | static const struct attribute_spec s390_attribute_table[] = { | |
94091f43 | 518 | { "hotpatch", 2, 2, true, false, false, s390_handle_hotpatch_attribute, false |
d0de9e13 DV |
519 | }, |
520 | /* End element. */ | |
521 | { NULL, 0, 0, false, false, false, NULL, false } | |
522 | }; | |
523 | ||
5d304e47 AK |
524 | /* Return the alignment for LABEL. We default to the -falign-labels |
525 | value except for the literal pool base label. */ | |
526 | int | |
527 | s390_label_align (rtx label) | |
528 | { | |
e8a54173 DM |
529 | rtx_insn *prev_insn = prev_active_insn (label); |
530 | rtx set, src; | |
5d304e47 AK |
531 | |
532 | if (prev_insn == NULL_RTX) | |
533 | goto old; | |
534 | ||
e8a54173 | 535 | set = single_set (prev_insn); |
5d304e47 | 536 | |
e8a54173 | 537 | if (set == NULL_RTX) |
5d304e47 AK |
538 | goto old; |
539 | ||
e8a54173 | 540 | src = SET_SRC (set); |
5d304e47 AK |
541 | |
542 | /* Don't align literal pool base labels. */ | |
e8a54173 DM |
543 | if (GET_CODE (src) == UNSPEC |
544 | && XINT (src, 1) == UNSPEC_MAIN_BASE) | |
5d304e47 AK |
545 | return 0; |
546 | ||
547 | old: | |
548 | return align_labels_log; | |
549 | } | |
550 | ||
ef4bddc2 | 551 | static machine_mode |
c7ff6e7a AK |
552 | s390_libgcc_cmp_return_mode (void) |
553 | { | |
554 | return TARGET_64BIT ? DImode : SImode; | |
555 | } | |
556 | ||
ef4bddc2 | 557 | static machine_mode |
c7ff6e7a AK |
558 | s390_libgcc_shift_count_mode (void) |
559 | { | |
560 | return TARGET_64BIT ? DImode : SImode; | |
561 | } | |
562 | ||
ef4bddc2 | 563 | static machine_mode |
9602b6a1 AK |
564 | s390_unwind_word_mode (void) |
565 | { | |
566 | return TARGET_64BIT ? DImode : SImode; | |
567 | } | |
568 | ||
4dc19cc0 AK |
569 | /* Return true if the back end supports mode MODE. */ |
570 | static bool | |
ef4bddc2 | 571 | s390_scalar_mode_supported_p (machine_mode mode) |
4dc19cc0 | 572 | { |
9602b6a1 AK |
573 | /* In contrast to the default implementation reject TImode constants on 31bit |
574 | TARGET_ZARCH for ABI compliance. */ | |
575 | if (!TARGET_64BIT && TARGET_ZARCH && mode == TImode) | |
576 | return false; | |
577 | ||
4dc19cc0 | 578 | if (DECIMAL_FLOAT_MODE_P (mode)) |
a9ab39d3 | 579 | return default_decimal_float_supported_p (); |
9602b6a1 AK |
580 | |
581 | return default_scalar_mode_supported_p (mode); | |
4dc19cc0 AK |
582 | } |
583 | ||
085261c8 AK |
584 | /* Return true if the back end supports vector mode MODE. */ |
585 | static bool | |
586 | s390_vector_mode_supported_p (machine_mode mode) | |
587 | { | |
588 | machine_mode inner; | |
589 | ||
590 | if (!VECTOR_MODE_P (mode) | |
591 | || !TARGET_VX | |
592 | || GET_MODE_SIZE (mode) > 16) | |
593 | return false; | |
594 | ||
595 | inner = GET_MODE_INNER (mode); | |
596 | ||
597 | switch (inner) | |
598 | { | |
599 | case QImode: | |
600 | case HImode: | |
601 | case SImode: | |
602 | case DImode: | |
603 | case TImode: | |
604 | case SFmode: | |
605 | case DFmode: | |
606 | case TFmode: | |
607 | return true; | |
608 | default: | |
609 | return false; | |
610 | } | |
611 | } | |
612 | ||
7bcebb25 AK |
613 | /* Set the has_landing_pad_p flag in struct machine_function to VALUE. */ |
614 | ||
615 | void | |
616 | s390_set_has_landing_pad_p (bool value) | |
617 | { | |
618 | cfun->machine->has_landing_pad_p = value; | |
619 | } | |
29a79fcf | 620 | |
69950452 AS |
621 | /* If two condition code modes are compatible, return a condition code |
622 | mode which is compatible with both. Otherwise, return | |
623 | VOIDmode. */ | |
624 | ||
ef4bddc2 RS |
625 | static machine_mode |
626 | s390_cc_modes_compatible (machine_mode m1, machine_mode m2) | |
69950452 AS |
627 | { |
628 | if (m1 == m2) | |
629 | return m1; | |
630 | ||
631 | switch (m1) | |
632 | { | |
633 | case CCZmode: | |
634 | if (m2 == CCUmode || m2 == CCTmode || m2 == CCZ1mode | |
635 | || m2 == CCSmode || m2 == CCSRmode || m2 == CCURmode) | |
636 | return m2; | |
637 | return VOIDmode; | |
638 | ||
639 | case CCSmode: | |
640 | case CCUmode: | |
641 | case CCTmode: | |
642 | case CCSRmode: | |
643 | case CCURmode: | |
644 | case CCZ1mode: | |
645 | if (m2 == CCZmode) | |
646 | return m1; | |
f4aa3848 | 647 | |
69950452 AS |
648 | return VOIDmode; |
649 | ||
650 | default: | |
651 | return VOIDmode; | |
652 | } | |
653 | return VOIDmode; | |
654 | } | |
655 | ||
994fe660 | 656 | /* Return true if SET either doesn't set the CC register, or else |
c7453384 | 657 | the source and destination have matching CC modes and that |
994fe660 | 658 | CC mode is at least as constrained as REQ_MODE. */ |
c7453384 | 659 | |
3ed99cc9 | 660 | static bool |
ef4bddc2 | 661 | s390_match_ccmode_set (rtx set, machine_mode req_mode) |
9db1d521 | 662 | { |
ef4bddc2 | 663 | machine_mode set_mode; |
9db1d521 | 664 | |
8d933e31 | 665 | gcc_assert (GET_CODE (set) == SET); |
9db1d521 HP |
666 | |
667 | if (GET_CODE (SET_DEST (set)) != REG || !CC_REGNO_P (REGNO (SET_DEST (set)))) | |
668 | return 1; | |
669 | ||
670 | set_mode = GET_MODE (SET_DEST (set)); | |
671 | switch (set_mode) | |
672 | { | |
9db1d521 | 673 | case CCSmode: |
07893d4f | 674 | case CCSRmode: |
9db1d521 | 675 | case CCUmode: |
07893d4f | 676 | case CCURmode: |
ba956982 | 677 | case CCLmode: |
07893d4f UW |
678 | case CCL1mode: |
679 | case CCL2mode: | |
5d880bd2 | 680 | case CCL3mode: |
07893d4f UW |
681 | case CCT1mode: |
682 | case CCT2mode: | |
683 | case CCT3mode: | |
684 | if (req_mode != set_mode) | |
ba956982 UW |
685 | return 0; |
686 | break; | |
07893d4f | 687 | |
9db1d521 | 688 | case CCZmode: |
07893d4f UW |
689 | if (req_mode != CCSmode && req_mode != CCUmode && req_mode != CCTmode |
690 | && req_mode != CCSRmode && req_mode != CCURmode) | |
9db1d521 HP |
691 | return 0; |
692 | break; | |
0a3bdf9d UW |
693 | |
694 | case CCAPmode: | |
695 | case CCANmode: | |
696 | if (req_mode != CCAmode) | |
697 | return 0; | |
698 | break; | |
c7453384 | 699 | |
9db1d521 | 700 | default: |
8d933e31 | 701 | gcc_unreachable (); |
9db1d521 | 702 | } |
c7453384 | 703 | |
9db1d521 HP |
704 | return (GET_MODE (SET_SRC (set)) == set_mode); |
705 | } | |
706 | ||
c7453384 EC |
707 | /* Return true if every SET in INSN that sets the CC register |
708 | has source and destination with matching CC modes and that | |
709 | CC mode is at least as constrained as REQ_MODE. | |
07893d4f | 710 | If REQ_MODE is VOIDmode, always return false. */ |
c7453384 | 711 | |
3ed99cc9 | 712 | bool |
ef4bddc2 | 713 | s390_match_ccmode (rtx_insn *insn, machine_mode req_mode) |
9db1d521 HP |
714 | { |
715 | int i; | |
716 | ||
07893d4f UW |
717 | /* s390_tm_ccmode returns VOIDmode to indicate failure. */ |
718 | if (req_mode == VOIDmode) | |
3ed99cc9 | 719 | return false; |
07893d4f | 720 | |
9db1d521 HP |
721 | if (GET_CODE (PATTERN (insn)) == SET) |
722 | return s390_match_ccmode_set (PATTERN (insn), req_mode); | |
723 | ||
724 | if (GET_CODE (PATTERN (insn)) == PARALLEL) | |
725 | for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++) | |
726 | { | |
727 | rtx set = XVECEXP (PATTERN (insn), 0, i); | |
728 | if (GET_CODE (set) == SET) | |
729 | if (!s390_match_ccmode_set (set, req_mode)) | |
3ed99cc9 | 730 | return false; |
9db1d521 HP |
731 | } |
732 | ||
3ed99cc9 | 733 | return true; |
9db1d521 HP |
734 | } |
735 | ||
c7453384 | 736 | /* If a test-under-mask instruction can be used to implement |
07893d4f | 737 | (compare (and ... OP1) OP2), return the CC mode required |
c7453384 | 738 | to do that. Otherwise, return VOIDmode. |
07893d4f UW |
739 | MIXED is true if the instruction can distinguish between |
740 | CC1 and CC2 for mixed selected bits (TMxx), it is false | |
741 | if the instruction cannot (TM). */ | |
742 | ||
ef4bddc2 | 743 | machine_mode |
3ed99cc9 | 744 | s390_tm_ccmode (rtx op1, rtx op2, bool mixed) |
07893d4f UW |
745 | { |
746 | int bit0, bit1; | |
747 | ||
748 | /* ??? Fixme: should work on CONST_DOUBLE as well. */ | |
749 | if (GET_CODE (op1) != CONST_INT || GET_CODE (op2) != CONST_INT) | |
750 | return VOIDmode; | |
751 | ||
00bda920 AK |
752 | /* Selected bits all zero: CC0. |
753 | e.g.: int a; if ((a & (16 + 128)) == 0) */ | |
07893d4f UW |
754 | if (INTVAL (op2) == 0) |
755 | return CCTmode; | |
756 | ||
f4aa3848 | 757 | /* Selected bits all one: CC3. |
00bda920 | 758 | e.g.: int a; if ((a & (16 + 128)) == 16 + 128) */ |
07893d4f UW |
759 | if (INTVAL (op2) == INTVAL (op1)) |
760 | return CCT3mode; | |
761 | ||
00bda920 AK |
762 | /* Exactly two bits selected, mixed zeroes and ones: CC1 or CC2. e.g.: |
763 | int a; | |
764 | if ((a & (16 + 128)) == 16) -> CCT1 | |
765 | if ((a & (16 + 128)) == 128) -> CCT2 */ | |
07893d4f UW |
766 | if (mixed) |
767 | { | |
768 | bit1 = exact_log2 (INTVAL (op2)); | |
769 | bit0 = exact_log2 (INTVAL (op1) ^ INTVAL (op2)); | |
770 | if (bit0 != -1 && bit1 != -1) | |
771 | return bit0 > bit1 ? CCT1mode : CCT2mode; | |
772 | } | |
773 | ||
774 | return VOIDmode; | |
775 | } | |
776 | ||
c7453384 EC |
777 | /* Given a comparison code OP (EQ, NE, etc.) and the operands |
778 | OP0 and OP1 of a COMPARE, return the mode to be used for the | |
ba956982 UW |
779 | comparison. */ |
780 | ||
ef4bddc2 | 781 | machine_mode |
9c808aad | 782 | s390_select_ccmode (enum rtx_code code, rtx op0, rtx op1) |
ba956982 UW |
783 | { |
784 | switch (code) | |
785 | { | |
786 | case EQ: | |
787 | case NE: | |
26a89301 UW |
788 | if ((GET_CODE (op0) == NEG || GET_CODE (op0) == ABS) |
789 | && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT) | |
790 | return CCAPmode; | |
0a3bdf9d | 791 | if (GET_CODE (op0) == PLUS && GET_CODE (XEXP (op0, 1)) == CONST_INT |
b5c67a49 | 792 | && CONST_OK_FOR_K (INTVAL (XEXP (op0, 1)))) |
0a3bdf9d | 793 | return CCAPmode; |
3ef093a8 AK |
794 | if ((GET_CODE (op0) == PLUS || GET_CODE (op0) == MINUS |
795 | || GET_CODE (op1) == NEG) | |
796 | && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT) | |
ba956982 UW |
797 | return CCLmode; |
798 | ||
07893d4f UW |
799 | if (GET_CODE (op0) == AND) |
800 | { | |
801 | /* Check whether we can potentially do it via TM. */ | |
ef4bddc2 | 802 | machine_mode ccmode; |
07893d4f UW |
803 | ccmode = s390_tm_ccmode (XEXP (op0, 1), op1, 1); |
804 | if (ccmode != VOIDmode) | |
805 | { | |
806 | /* Relax CCTmode to CCZmode to allow fall-back to AND | |
807 | if that turns out to be beneficial. */ | |
808 | return ccmode == CCTmode ? CCZmode : ccmode; | |
809 | } | |
810 | } | |
811 | ||
c7453384 | 812 | if (register_operand (op0, HImode) |
07893d4f UW |
813 | && GET_CODE (op1) == CONST_INT |
814 | && (INTVAL (op1) == -1 || INTVAL (op1) == 65535)) | |
815 | return CCT3mode; | |
c7453384 | 816 | if (register_operand (op0, QImode) |
07893d4f UW |
817 | && GET_CODE (op1) == CONST_INT |
818 | && (INTVAL (op1) == -1 || INTVAL (op1) == 255)) | |
819 | return CCT3mode; | |
820 | ||
ba956982 UW |
821 | return CCZmode; |
822 | ||
823 | case LE: | |
824 | case LT: | |
825 | case GE: | |
826 | case GT: | |
00bda920 AK |
827 | /* The only overflow condition of NEG and ABS happens when |
828 | -INT_MAX is used as parameter, which stays negative. So | |
f4aa3848 | 829 | we have an overflow from a positive value to a negative. |
00bda920 | 830 | Using CCAP mode the resulting cc can be used for comparisons. */ |
26a89301 UW |
831 | if ((GET_CODE (op0) == NEG || GET_CODE (op0) == ABS) |
832 | && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT) | |
833 | return CCAPmode; | |
00bda920 AK |
834 | |
835 | /* If constants are involved in an add instruction it is possible to use | |
836 | the resulting cc for comparisons with zero. Knowing the sign of the | |
35fd3193 | 837 | constant the overflow behavior gets predictable. e.g.: |
f4aa3848 | 838 | int a, b; if ((b = a + c) > 0) |
00bda920 | 839 | with c as a constant value: c < 0 -> CCAN and c >= 0 -> CCAP */ |
26a89301 | 840 | if (GET_CODE (op0) == PLUS && GET_CODE (XEXP (op0, 1)) == CONST_INT |
71ce1a34 AK |
841 | && (CONST_OK_FOR_K (INTVAL (XEXP (op0, 1))) |
842 | || (CONST_OK_FOR_CONSTRAINT_P (INTVAL (XEXP (op0, 1)), 'O', "Os") | |
843 | /* Avoid INT32_MIN on 32 bit. */ | |
844 | && (!TARGET_ZARCH || INTVAL (XEXP (op0, 1)) != -0x7fffffff - 1)))) | |
26a89301 UW |
845 | { |
846 | if (INTVAL (XEXP((op0), 1)) < 0) | |
847 | return CCANmode; | |
848 | else | |
849 | return CCAPmode; | |
850 | } | |
851 | /* Fall through. */ | |
ba956982 UW |
852 | case UNORDERED: |
853 | case ORDERED: | |
854 | case UNEQ: | |
855 | case UNLE: | |
856 | case UNLT: | |
857 | case UNGE: | |
858 | case UNGT: | |
859 | case LTGT: | |
07893d4f UW |
860 | if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND) |
861 | && GET_CODE (op1) != CONST_INT) | |
862 | return CCSRmode; | |
ba956982 UW |
863 | return CCSmode; |
864 | ||
ba956982 UW |
865 | case LTU: |
866 | case GEU: | |
3ef093a8 AK |
867 | if (GET_CODE (op0) == PLUS |
868 | && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT) | |
07893d4f UW |
869 | return CCL1mode; |
870 | ||
871 | if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND) | |
872 | && GET_CODE (op1) != CONST_INT) | |
873 | return CCURmode; | |
874 | return CCUmode; | |
875 | ||
876 | case LEU: | |
ba956982 | 877 | case GTU: |
3ef093a8 AK |
878 | if (GET_CODE (op0) == MINUS |
879 | && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT) | |
07893d4f UW |
880 | return CCL2mode; |
881 | ||
882 | if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND) | |
883 | && GET_CODE (op1) != CONST_INT) | |
884 | return CCURmode; | |
ba956982 UW |
885 | return CCUmode; |
886 | ||
887 | default: | |
8d933e31 | 888 | gcc_unreachable (); |
ba956982 UW |
889 | } |
890 | } | |
891 | ||
68f9c5e2 UW |
892 | /* Replace the comparison OP0 CODE OP1 by a semantically equivalent one |
893 | that we can implement more efficiently. */ | |
894 | ||
c354951b AK |
895 | static void |
896 | s390_canonicalize_comparison (int *code, rtx *op0, rtx *op1, | |
897 | bool op0_preserve_value) | |
68f9c5e2 | 898 | { |
c354951b AK |
899 | if (op0_preserve_value) |
900 | return; | |
901 | ||
68f9c5e2 UW |
902 | /* Convert ZERO_EXTRACT back to AND to enable TM patterns. */ |
903 | if ((*code == EQ || *code == NE) | |
904 | && *op1 == const0_rtx | |
905 | && GET_CODE (*op0) == ZERO_EXTRACT | |
906 | && GET_CODE (XEXP (*op0, 1)) == CONST_INT | |
907 | && GET_CODE (XEXP (*op0, 2)) == CONST_INT | |
908 | && SCALAR_INT_MODE_P (GET_MODE (XEXP (*op0, 0)))) | |
909 | { | |
910 | rtx inner = XEXP (*op0, 0); | |
911 | HOST_WIDE_INT modesize = GET_MODE_BITSIZE (GET_MODE (inner)); | |
912 | HOST_WIDE_INT len = INTVAL (XEXP (*op0, 1)); | |
913 | HOST_WIDE_INT pos = INTVAL (XEXP (*op0, 2)); | |
914 | ||
915 | if (len > 0 && len < modesize | |
916 | && pos >= 0 && pos + len <= modesize | |
917 | && modesize <= HOST_BITS_PER_WIDE_INT) | |
918 | { | |
919 | unsigned HOST_WIDE_INT block; | |
920 | block = ((unsigned HOST_WIDE_INT) 1 << len) - 1; | |
921 | block <<= modesize - pos - len; | |
922 | ||
923 | *op0 = gen_rtx_AND (GET_MODE (inner), inner, | |
924 | gen_int_mode (block, GET_MODE (inner))); | |
925 | } | |
926 | } | |
927 | ||
928 | /* Narrow AND of memory against immediate to enable TM. */ | |
929 | if ((*code == EQ || *code == NE) | |
930 | && *op1 == const0_rtx | |
931 | && GET_CODE (*op0) == AND | |
932 | && GET_CODE (XEXP (*op0, 1)) == CONST_INT | |
933 | && SCALAR_INT_MODE_P (GET_MODE (XEXP (*op0, 0)))) | |
934 | { | |
935 | rtx inner = XEXP (*op0, 0); | |
936 | rtx mask = XEXP (*op0, 1); | |
937 | ||
938 | /* Ignore paradoxical SUBREGs if all extra bits are masked out. */ | |
939 | if (GET_CODE (inner) == SUBREG | |
940 | && SCALAR_INT_MODE_P (GET_MODE (SUBREG_REG (inner))) | |
941 | && (GET_MODE_SIZE (GET_MODE (inner)) | |
942 | >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner)))) | |
943 | && ((INTVAL (mask) | |
944 | & GET_MODE_MASK (GET_MODE (inner)) | |
945 | & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (inner)))) | |
946 | == 0)) | |
947 | inner = SUBREG_REG (inner); | |
948 | ||
949 | /* Do not change volatile MEMs. */ | |
950 | if (MEM_P (inner) && !MEM_VOLATILE_P (inner)) | |
951 | { | |
952 | int part = s390_single_part (XEXP (*op0, 1), | |
953 | GET_MODE (inner), QImode, 0); | |
954 | if (part >= 0) | |
955 | { | |
956 | mask = gen_int_mode (s390_extract_part (mask, QImode, 0), QImode); | |
957 | inner = adjust_address_nv (inner, QImode, part); | |
958 | *op0 = gen_rtx_AND (QImode, inner, mask); | |
959 | } | |
960 | } | |
961 | } | |
962 | ||
963 | /* Narrow comparisons against 0xffff to HImode if possible. */ | |
68f9c5e2 UW |
964 | if ((*code == EQ || *code == NE) |
965 | && GET_CODE (*op1) == CONST_INT | |
966 | && INTVAL (*op1) == 0xffff | |
967 | && SCALAR_INT_MODE_P (GET_MODE (*op0)) | |
f4aa3848 | 968 | && (nonzero_bits (*op0, GET_MODE (*op0)) |
68f9c5e2 UW |
969 | & ~(unsigned HOST_WIDE_INT) 0xffff) == 0) |
970 | { | |
971 | *op0 = gen_lowpart (HImode, *op0); | |
972 | *op1 = constm1_rtx; | |
973 | } | |
5b022de5 | 974 | |
5a3fe9b6 | 975 | /* Remove redundant UNSPEC_STRCMPCC_TO_INT conversions if possible. */ |
5b022de5 | 976 | if (GET_CODE (*op0) == UNSPEC |
5a3fe9b6 | 977 | && XINT (*op0, 1) == UNSPEC_STRCMPCC_TO_INT |
5b022de5 UW |
978 | && XVECLEN (*op0, 0) == 1 |
979 | && GET_MODE (XVECEXP (*op0, 0, 0)) == CCUmode | |
980 | && GET_CODE (XVECEXP (*op0, 0, 0)) == REG | |
981 | && REGNO (XVECEXP (*op0, 0, 0)) == CC_REGNUM | |
982 | && *op1 == const0_rtx) | |
983 | { | |
984 | enum rtx_code new_code = UNKNOWN; | |
985 | switch (*code) | |
986 | { | |
987 | case EQ: new_code = EQ; break; | |
988 | case NE: new_code = NE; break; | |
02887425 UW |
989 | case LT: new_code = GTU; break; |
990 | case GT: new_code = LTU; break; | |
991 | case LE: new_code = GEU; break; | |
992 | case GE: new_code = LEU; break; | |
5b022de5 UW |
993 | default: break; |
994 | } | |
995 | ||
996 | if (new_code != UNKNOWN) | |
997 | { | |
998 | *op0 = XVECEXP (*op0, 0, 0); | |
999 | *code = new_code; | |
1000 | } | |
1001 | } | |
69950452 | 1002 | |
5a3fe9b6 | 1003 | /* Remove redundant UNSPEC_CC_TO_INT conversions if possible. */ |
638e37c2 | 1004 | if (GET_CODE (*op0) == UNSPEC |
5a3fe9b6 | 1005 | && XINT (*op0, 1) == UNSPEC_CC_TO_INT |
638e37c2 | 1006 | && XVECLEN (*op0, 0) == 1 |
638e37c2 WG |
1007 | && GET_CODE (XVECEXP (*op0, 0, 0)) == REG |
1008 | && REGNO (XVECEXP (*op0, 0, 0)) == CC_REGNUM | |
5a3fe9b6 | 1009 | && CONST_INT_P (*op1)) |
638e37c2 WG |
1010 | { |
1011 | enum rtx_code new_code = UNKNOWN; | |
5a3fe9b6 | 1012 | switch (GET_MODE (XVECEXP (*op0, 0, 0))) |
638e37c2 | 1013 | { |
5a3fe9b6 AK |
1014 | case CCZmode: |
1015 | case CCRAWmode: | |
1016 | switch (*code) | |
1017 | { | |
1018 | case EQ: new_code = EQ; break; | |
1019 | case NE: new_code = NE; break; | |
1020 | default: break; | |
1021 | } | |
1022 | break; | |
1023 | default: break; | |
638e37c2 WG |
1024 | } |
1025 | ||
1026 | if (new_code != UNKNOWN) | |
1027 | { | |
5a3fe9b6 AK |
1028 | /* For CCRAWmode put the required cc mask into the second |
1029 | operand. */ | |
2561451d AK |
1030 | if (GET_MODE (XVECEXP (*op0, 0, 0)) == CCRAWmode |
1031 | && INTVAL (*op1) >= 0 && INTVAL (*op1) <= 3) | |
5a3fe9b6 | 1032 | *op1 = gen_rtx_CONST_INT (VOIDmode, 1 << (3 - INTVAL (*op1))); |
638e37c2 WG |
1033 | *op0 = XVECEXP (*op0, 0, 0); |
1034 | *code = new_code; | |
1035 | } | |
1036 | } | |
1037 | ||
69950452 AS |
1038 | /* Simplify cascaded EQ, NE with const0_rtx. */ |
1039 | if ((*code == NE || *code == EQ) | |
1040 | && (GET_CODE (*op0) == EQ || GET_CODE (*op0) == NE) | |
1041 | && GET_MODE (*op0) == SImode | |
1042 | && GET_MODE (XEXP (*op0, 0)) == CCZ1mode | |
1043 | && REG_P (XEXP (*op0, 0)) | |
1044 | && XEXP (*op0, 1) == const0_rtx | |
1045 | && *op1 == const0_rtx) | |
1046 | { | |
1047 | if ((*code == EQ && GET_CODE (*op0) == NE) | |
1048 | || (*code == NE && GET_CODE (*op0) == EQ)) | |
1049 | *code = EQ; | |
1050 | else | |
1051 | *code = NE; | |
1052 | *op0 = XEXP (*op0, 0); | |
1053 | } | |
c5b2a111 UW |
1054 | |
1055 | /* Prefer register over memory as first operand. */ | |
1056 | if (MEM_P (*op0) && REG_P (*op1)) | |
1057 | { | |
1058 | rtx tem = *op0; *op0 = *op1; *op1 = tem; | |
c354951b | 1059 | *code = (int)swap_condition ((enum rtx_code)*code); |
c5b2a111 | 1060 | } |
68f9c5e2 UW |
1061 | } |
1062 | ||
6590e19a UW |
1063 | /* Emit a compare instruction suitable to implement the comparison |
1064 | OP0 CODE OP1. Return the correct condition RTL to be placed in | |
1065 | the IF_THEN_ELSE of the conditional branch testing the result. */ | |
1066 | ||
1067 | rtx | |
1068 | s390_emit_compare (enum rtx_code code, rtx op0, rtx op1) | |
1069 | { | |
ef4bddc2 | 1070 | machine_mode mode = s390_select_ccmode (code, op0, op1); |
4a77c72b | 1071 | rtx cc; |
6590e19a | 1072 | |
e0374221 | 1073 | /* Do not output a redundant compare instruction if a compare_and_swap |
69950452 | 1074 | pattern already computed the result and the machine modes are compatible. */ |
4a77c72b PB |
1075 | if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC) |
1076 | { | |
1077 | gcc_assert (s390_cc_modes_compatible (GET_MODE (op0), mode) | |
1078 | == GET_MODE (op0)); | |
1079 | cc = op0; | |
1080 | } | |
e0374221 AS |
1081 | else |
1082 | { | |
4a77c72b | 1083 | cc = gen_rtx_REG (mode, CC_REGNUM); |
f7df4a84 | 1084 | emit_insn (gen_rtx_SET (cc, gen_rtx_COMPARE (mode, op0, op1))); |
e0374221 | 1085 | } |
4a77c72b | 1086 | |
f4aa3848 | 1087 | return gen_rtx_fmt_ee (code, VOIDmode, cc, const0_rtx); |
6590e19a UW |
1088 | } |
1089 | ||
0a2aaacc | 1090 | /* Emit a SImode compare and swap instruction setting MEM to NEW_RTX if OLD |
8bb501bb AK |
1091 | matches CMP. |
1092 | Return the correct condition RTL to be placed in the IF_THEN_ELSE of the | |
1093 | conditional branch testing the result. */ | |
1094 | ||
1095 | static rtx | |
78ce265b RH |
1096 | s390_emit_compare_and_swap (enum rtx_code code, rtx old, rtx mem, |
1097 | rtx cmp, rtx new_rtx) | |
8bb501bb | 1098 | { |
78ce265b RH |
1099 | emit_insn (gen_atomic_compare_and_swapsi_internal (old, mem, cmp, new_rtx)); |
1100 | return s390_emit_compare (code, gen_rtx_REG (CCZ1mode, CC_REGNUM), | |
1101 | const0_rtx); | |
8bb501bb AK |
1102 | } |
1103 | ||
5a3fe9b6 AK |
1104 | /* Emit a jump instruction to TARGET and return it. If COND is |
1105 | NULL_RTX, emit an unconditional jump, else a conditional jump under | |
1106 | condition COND. */ | |
6590e19a | 1107 | |
775c43d3 | 1108 | rtx_insn * |
6590e19a UW |
1109 | s390_emit_jump (rtx target, rtx cond) |
1110 | { | |
1111 | rtx insn; | |
1112 | ||
1113 | target = gen_rtx_LABEL_REF (VOIDmode, target); | |
1114 | if (cond) | |
1115 | target = gen_rtx_IF_THEN_ELSE (VOIDmode, cond, target, pc_rtx); | |
1116 | ||
f7df4a84 | 1117 | insn = gen_rtx_SET (pc_rtx, target); |
5a3fe9b6 | 1118 | return emit_jump_insn (insn); |
6590e19a UW |
1119 | } |
1120 | ||
c7453384 | 1121 | /* Return branch condition mask to implement a branch |
5b022de5 | 1122 | specified by CODE. Return -1 for invalid comparisons. */ |
ba956982 | 1123 | |
0bfc3f69 | 1124 | int |
9c808aad | 1125 | s390_branch_condition_mask (rtx code) |
c7453384 | 1126 | { |
ba956982 UW |
1127 | const int CC0 = 1 << 3; |
1128 | const int CC1 = 1 << 2; | |
1129 | const int CC2 = 1 << 1; | |
1130 | const int CC3 = 1 << 0; | |
1131 | ||
8d933e31 AS |
1132 | gcc_assert (GET_CODE (XEXP (code, 0)) == REG); |
1133 | gcc_assert (REGNO (XEXP (code, 0)) == CC_REGNUM); | |
5a3fe9b6 AK |
1134 | gcc_assert (XEXP (code, 1) == const0_rtx |
1135 | || (GET_MODE (XEXP (code, 0)) == CCRAWmode | |
1136 | && CONST_INT_P (XEXP (code, 1)))); | |
1137 | ||
ba956982 UW |
1138 | |
1139 | switch (GET_MODE (XEXP (code, 0))) | |
1140 | { | |
1141 | case CCZmode: | |
69950452 | 1142 | case CCZ1mode: |
ba956982 UW |
1143 | switch (GET_CODE (code)) |
1144 | { | |
1145 | case EQ: return CC0; | |
1146 | case NE: return CC1 | CC2 | CC3; | |
5b022de5 | 1147 | default: return -1; |
ba956982 UW |
1148 | } |
1149 | break; | |
1150 | ||
07893d4f UW |
1151 | case CCT1mode: |
1152 | switch (GET_CODE (code)) | |
1153 | { | |
1154 | case EQ: return CC1; | |
1155 | case NE: return CC0 | CC2 | CC3; | |
5b022de5 | 1156 | default: return -1; |
07893d4f UW |
1157 | } |
1158 | break; | |
1159 | ||
1160 | case CCT2mode: | |
1161 | switch (GET_CODE (code)) | |
1162 | { | |
1163 | case EQ: return CC2; | |
1164 | case NE: return CC0 | CC1 | CC3; | |
5b022de5 | 1165 | default: return -1; |
07893d4f UW |
1166 | } |
1167 | break; | |
1168 | ||
1169 | case CCT3mode: | |
1170 | switch (GET_CODE (code)) | |
1171 | { | |
1172 | case EQ: return CC3; | |
1173 | case NE: return CC0 | CC1 | CC2; | |
5b022de5 | 1174 | default: return -1; |
07893d4f UW |
1175 | } |
1176 | break; | |
1177 | ||
ba956982 UW |
1178 | case CCLmode: |
1179 | switch (GET_CODE (code)) | |
1180 | { | |
1181 | case EQ: return CC0 | CC2; | |
1182 | case NE: return CC1 | CC3; | |
5b022de5 | 1183 | default: return -1; |
07893d4f UW |
1184 | } |
1185 | break; | |
1186 | ||
1187 | case CCL1mode: | |
1188 | switch (GET_CODE (code)) | |
1189 | { | |
1190 | case LTU: return CC2 | CC3; /* carry */ | |
1191 | case GEU: return CC0 | CC1; /* no carry */ | |
5b022de5 | 1192 | default: return -1; |
07893d4f UW |
1193 | } |
1194 | break; | |
1195 | ||
1196 | case CCL2mode: | |
1197 | switch (GET_CODE (code)) | |
1198 | { | |
1199 | case GTU: return CC0 | CC1; /* borrow */ | |
1200 | case LEU: return CC2 | CC3; /* no borrow */ | |
5b022de5 | 1201 | default: return -1; |
ba956982 UW |
1202 | } |
1203 | break; | |
1204 | ||
5d880bd2 UW |
1205 | case CCL3mode: |
1206 | switch (GET_CODE (code)) | |
1207 | { | |
1208 | case EQ: return CC0 | CC2; | |
1209 | case NE: return CC1 | CC3; | |
1210 | case LTU: return CC1; | |
1211 | case GTU: return CC3; | |
1212 | case LEU: return CC1 | CC2; | |
1213 | case GEU: return CC2 | CC3; | |
5b022de5 | 1214 | default: return -1; |
5d880bd2 UW |
1215 | } |
1216 | ||
ba956982 UW |
1217 | case CCUmode: |
1218 | switch (GET_CODE (code)) | |
1219 | { | |
1220 | case EQ: return CC0; | |
1221 | case NE: return CC1 | CC2 | CC3; | |
1222 | case LTU: return CC1; | |
1223 | case GTU: return CC2; | |
1224 | case LEU: return CC0 | CC1; | |
1225 | case GEU: return CC0 | CC2; | |
5b022de5 | 1226 | default: return -1; |
ba956982 UW |
1227 | } |
1228 | break; | |
1229 | ||
07893d4f UW |
1230 | case CCURmode: |
1231 | switch (GET_CODE (code)) | |
1232 | { | |
1233 | case EQ: return CC0; | |
1234 | case NE: return CC2 | CC1 | CC3; | |
1235 | case LTU: return CC2; | |
1236 | case GTU: return CC1; | |
1237 | case LEU: return CC0 | CC2; | |
1238 | case GEU: return CC0 | CC1; | |
5b022de5 | 1239 | default: return -1; |
07893d4f UW |
1240 | } |
1241 | break; | |
1242 | ||
0a3bdf9d UW |
1243 | case CCAPmode: |
1244 | switch (GET_CODE (code)) | |
1245 | { | |
1246 | case EQ: return CC0; | |
1247 | case NE: return CC1 | CC2 | CC3; | |
1248 | case LT: return CC1 | CC3; | |
1249 | case GT: return CC2; | |
1250 | case LE: return CC0 | CC1 | CC3; | |
1251 | case GE: return CC0 | CC2; | |
5b022de5 | 1252 | default: return -1; |
0a3bdf9d UW |
1253 | } |
1254 | break; | |
1255 | ||
1256 | case CCANmode: | |
1257 | switch (GET_CODE (code)) | |
1258 | { | |
1259 | case EQ: return CC0; | |
1260 | case NE: return CC1 | CC2 | CC3; | |
1261 | case LT: return CC1; | |
1262 | case GT: return CC2 | CC3; | |
1263 | case LE: return CC0 | CC1; | |
1264 | case GE: return CC0 | CC2 | CC3; | |
5b022de5 | 1265 | default: return -1; |
0a3bdf9d UW |
1266 | } |
1267 | break; | |
1268 | ||
ba956982 UW |
1269 | case CCSmode: |
1270 | switch (GET_CODE (code)) | |
1271 | { | |
1272 | case EQ: return CC0; | |
1273 | case NE: return CC1 | CC2 | CC3; | |
1274 | case LT: return CC1; | |
1275 | case GT: return CC2; | |
1276 | case LE: return CC0 | CC1; | |
1277 | case GE: return CC0 | CC2; | |
1278 | case UNORDERED: return CC3; | |
1279 | case ORDERED: return CC0 | CC1 | CC2; | |
1280 | case UNEQ: return CC0 | CC3; | |
1281 | case UNLT: return CC1 | CC3; | |
1282 | case UNGT: return CC2 | CC3; | |
1283 | case UNLE: return CC0 | CC1 | CC3; | |
1284 | case UNGE: return CC0 | CC2 | CC3; | |
1285 | case LTGT: return CC1 | CC2; | |
5b022de5 | 1286 | default: return -1; |
ba956982 | 1287 | } |
07893d4f UW |
1288 | break; |
1289 | ||
1290 | case CCSRmode: | |
1291 | switch (GET_CODE (code)) | |
1292 | { | |
1293 | case EQ: return CC0; | |
1294 | case NE: return CC2 | CC1 | CC3; | |
1295 | case LT: return CC2; | |
1296 | case GT: return CC1; | |
1297 | case LE: return CC0 | CC2; | |
1298 | case GE: return CC0 | CC1; | |
1299 | case UNORDERED: return CC3; | |
1300 | case ORDERED: return CC0 | CC2 | CC1; | |
1301 | case UNEQ: return CC0 | CC3; | |
1302 | case UNLT: return CC2 | CC3; | |
1303 | case UNGT: return CC1 | CC3; | |
1304 | case UNLE: return CC0 | CC2 | CC3; | |
1305 | case UNGE: return CC0 | CC1 | CC3; | |
1306 | case LTGT: return CC2 | CC1; | |
5b022de5 | 1307 | default: return -1; |
07893d4f UW |
1308 | } |
1309 | break; | |
ba956982 | 1310 | |
5a3fe9b6 AK |
1311 | case CCRAWmode: |
1312 | switch (GET_CODE (code)) | |
1313 | { | |
1314 | case EQ: | |
1315 | return INTVAL (XEXP (code, 1)); | |
1316 | case NE: | |
1317 | return (INTVAL (XEXP (code, 1))) ^ 0xf; | |
1318 | default: | |
1319 | gcc_unreachable (); | |
1320 | } | |
1321 | ||
ba956982 | 1322 | default: |
5b022de5 | 1323 | return -1; |
ba956982 UW |
1324 | } |
1325 | } | |
1326 | ||
963fc8d0 AK |
1327 | |
1328 | /* Return branch condition mask to implement a compare and branch | |
1329 | specified by CODE. Return -1 for invalid comparisons. */ | |
1330 | ||
1331 | int | |
1332 | s390_compare_and_branch_condition_mask (rtx code) | |
1333 | { | |
1334 | const int CC0 = 1 << 3; | |
1335 | const int CC1 = 1 << 2; | |
1336 | const int CC2 = 1 << 1; | |
1337 | ||
1338 | switch (GET_CODE (code)) | |
1339 | { | |
1340 | case EQ: | |
1341 | return CC0; | |
1342 | case NE: | |
1343 | return CC1 | CC2; | |
1344 | case LT: | |
1345 | case LTU: | |
1346 | return CC1; | |
1347 | case GT: | |
1348 | case GTU: | |
1349 | return CC2; | |
1350 | case LE: | |
1351 | case LEU: | |
1352 | return CC0 | CC1; | |
1353 | case GE: | |
1354 | case GEU: | |
1355 | return CC0 | CC2; | |
1356 | default: | |
1357 | gcc_unreachable (); | |
1358 | } | |
1359 | return -1; | |
1360 | } | |
1361 | ||
c7453384 EC |
1362 | /* If INV is false, return assembler mnemonic string to implement |
1363 | a branch specified by CODE. If INV is true, return mnemonic | |
ba956982 UW |
1364 | for the corresponding inverted branch. */ |
1365 | ||
1366 | static const char * | |
9c808aad | 1367 | s390_branch_condition_mnemonic (rtx code, int inv) |
ba956982 | 1368 | { |
963fc8d0 AK |
1369 | int mask; |
1370 | ||
0139adca | 1371 | static const char *const mnemonic[16] = |
ba956982 UW |
1372 | { |
1373 | NULL, "o", "h", "nle", | |
1374 | "l", "nhe", "lh", "ne", | |
1375 | "e", "nlh", "he", "nl", | |
1376 | "le", "nh", "no", NULL | |
1377 | }; | |
1378 | ||
963fc8d0 AK |
1379 | if (GET_CODE (XEXP (code, 0)) == REG |
1380 | && REGNO (XEXP (code, 0)) == CC_REGNUM | |
5a3fe9b6 AK |
1381 | && (XEXP (code, 1) == const0_rtx |
1382 | || (GET_MODE (XEXP (code, 0)) == CCRAWmode | |
1383 | && CONST_INT_P (XEXP (code, 1))))) | |
963fc8d0 AK |
1384 | mask = s390_branch_condition_mask (code); |
1385 | else | |
1386 | mask = s390_compare_and_branch_condition_mask (code); | |
1387 | ||
5b022de5 | 1388 | gcc_assert (mask >= 0); |
ba956982 UW |
1389 | |
1390 | if (inv) | |
1391 | mask ^= 15; | |
1392 | ||
8d933e31 | 1393 | gcc_assert (mask >= 1 && mask <= 14); |
ba956982 UW |
1394 | |
1395 | return mnemonic[mask]; | |
1396 | } | |
1397 | ||
f19a9af7 AK |
1398 | /* Return the part of op which has a value different from def. |
1399 | The size of the part is determined by mode. | |
38899e29 | 1400 | Use this function only if you already know that op really |
f19a9af7 | 1401 | contains such a part. */ |
4023fb28 | 1402 | |
f19a9af7 | 1403 | unsigned HOST_WIDE_INT |
ef4bddc2 | 1404 | s390_extract_part (rtx op, machine_mode mode, int def) |
4023fb28 | 1405 | { |
f19a9af7 AK |
1406 | unsigned HOST_WIDE_INT value = 0; |
1407 | int max_parts = HOST_BITS_PER_WIDE_INT / GET_MODE_BITSIZE (mode); | |
1408 | int part_bits = GET_MODE_BITSIZE (mode); | |
c4d50129 AK |
1409 | unsigned HOST_WIDE_INT part_mask |
1410 | = ((unsigned HOST_WIDE_INT)1 << part_bits) - 1; | |
f19a9af7 | 1411 | int i; |
38899e29 | 1412 | |
f19a9af7 | 1413 | for (i = 0; i < max_parts; i++) |
4023fb28 | 1414 | { |
f19a9af7 AK |
1415 | if (i == 0) |
1416 | value = (unsigned HOST_WIDE_INT) INTVAL (op); | |
4023fb28 | 1417 | else |
f19a9af7 | 1418 | value >>= part_bits; |
38899e29 | 1419 | |
f19a9af7 AK |
1420 | if ((value & part_mask) != (def & part_mask)) |
1421 | return value & part_mask; | |
4023fb28 | 1422 | } |
38899e29 | 1423 | |
8d933e31 | 1424 | gcc_unreachable (); |
4023fb28 UW |
1425 | } |
1426 | ||
1427 | /* If OP is an integer constant of mode MODE with exactly one | |
f19a9af7 AK |
1428 | part of mode PART_MODE unequal to DEF, return the number of that |
1429 | part. Otherwise, return -1. */ | |
4023fb28 UW |
1430 | |
1431 | int | |
38899e29 | 1432 | s390_single_part (rtx op, |
ef4bddc2 RS |
1433 | machine_mode mode, |
1434 | machine_mode part_mode, | |
f19a9af7 AK |
1435 | int def) |
1436 | { | |
1437 | unsigned HOST_WIDE_INT value = 0; | |
1438 | int n_parts = GET_MODE_SIZE (mode) / GET_MODE_SIZE (part_mode); | |
c4d50129 AK |
1439 | unsigned HOST_WIDE_INT part_mask |
1440 | = ((unsigned HOST_WIDE_INT)1 << GET_MODE_BITSIZE (part_mode)) - 1; | |
f19a9af7 AK |
1441 | int i, part = -1; |
1442 | ||
1443 | if (GET_CODE (op) != CONST_INT) | |
1444 | return -1; | |
38899e29 | 1445 | |
f19a9af7 AK |
1446 | for (i = 0; i < n_parts; i++) |
1447 | { | |
1448 | if (i == 0) | |
1449 | value = (unsigned HOST_WIDE_INT) INTVAL (op); | |
4023fb28 | 1450 | else |
f19a9af7 | 1451 | value >>= GET_MODE_BITSIZE (part_mode); |
38899e29 | 1452 | |
f19a9af7 AK |
1453 | if ((value & part_mask) != (def & part_mask)) |
1454 | { | |
1455 | if (part != -1) | |
1456 | return -1; | |
1457 | else | |
1458 | part = i; | |
1459 | } | |
4023fb28 | 1460 | } |
f19a9af7 | 1461 | return part == -1 ? -1 : n_parts - 1 - part; |
4023fb28 UW |
1462 | } |
1463 | ||
963fc8d0 AK |
1464 | /* Return true if IN contains a contiguous bitfield in the lower SIZE |
1465 | bits and no other bits are set in IN. POS and LENGTH can be used | |
1466 | to obtain the start position and the length of the bitfield. | |
1467 | ||
1468 | POS gives the position of the first bit of the bitfield counting | |
1469 | from the lowest order bit starting with zero. In order to use this | |
1470 | value for S/390 instructions this has to be converted to "bits big | |
1471 | endian" style. */ | |
1472 | ||
1473 | bool | |
1474 | s390_contiguous_bitmask_p (unsigned HOST_WIDE_INT in, int size, | |
1475 | int *pos, int *length) | |
1476 | { | |
1477 | int tmp_pos = 0; | |
1478 | int tmp_length = 0; | |
1479 | int i; | |
1480 | unsigned HOST_WIDE_INT mask = 1ULL; | |
1481 | bool contiguous = false; | |
1482 | ||
1483 | for (i = 0; i < size; mask <<= 1, i++) | |
1484 | { | |
1485 | if (contiguous) | |
1486 | { | |
1487 | if (mask & in) | |
1488 | tmp_length++; | |
1489 | else | |
1490 | break; | |
1491 | } | |
1492 | else | |
1493 | { | |
1494 | if (mask & in) | |
1495 | { | |
1496 | contiguous = true; | |
1497 | tmp_length++; | |
1498 | } | |
1499 | else | |
1500 | tmp_pos++; | |
1501 | } | |
1502 | } | |
1503 | ||
1504 | if (!tmp_length) | |
1505 | return false; | |
1506 | ||
1507 | /* Calculate a mask for all bits beyond the contiguous bits. */ | |
1508 | mask = (-1LL & ~(((1ULL << (tmp_length + tmp_pos - 1)) << 1) - 1)); | |
1509 | ||
085261c8 AK |
1510 | if ((unsigned)size < sizeof (HOST_WIDE_INT) * BITS_PER_UNIT) |
1511 | mask &= (HOST_WIDE_INT_1U << size) - 1; | |
1512 | ||
963fc8d0 AK |
1513 | if (mask & in) |
1514 | return false; | |
1515 | ||
1516 | if (tmp_length + tmp_pos - 1 > size) | |
1517 | return false; | |
1518 | ||
1519 | if (length) | |
1520 | *length = tmp_length; | |
1521 | ||
1522 | if (pos) | |
1523 | *pos = tmp_pos; | |
1524 | ||
1525 | return true; | |
1526 | } | |
1527 | ||
085261c8 AK |
1528 | /* Return true if OP contains the same contiguous bitfield in *all* |
1529 | its elements. START and END can be used to obtain the start and | |
1530 | end position of the bitfield. | |
1531 | ||
1532 | START/STOP give the position of the first/last bit of the bitfield | |
1533 | counting from the lowest order bit starting with zero. In order to | |
1534 | use these values for S/390 instructions this has to be converted to | |
1535 | "bits big endian" style. */ | |
1536 | ||
1537 | bool | |
1538 | s390_contiguous_bitmask_vector_p (rtx op, int *start, int *end) | |
1539 | { | |
1540 | unsigned HOST_WIDE_INT mask; | |
1541 | int length, size; | |
1542 | ||
1543 | if (!VECTOR_MODE_P (GET_MODE (op)) | |
1544 | || GET_CODE (op) != CONST_VECTOR | |
1545 | || !CONST_INT_P (XVECEXP (op, 0, 0))) | |
1546 | return false; | |
1547 | ||
1548 | if (GET_MODE_NUNITS (GET_MODE (op)) > 1) | |
1549 | { | |
1550 | int i; | |
1551 | ||
1552 | for (i = 1; i < GET_MODE_NUNITS (GET_MODE (op)); ++i) | |
1553 | if (!rtx_equal_p (XVECEXP (op, 0, i), XVECEXP (op, 0, 0))) | |
1554 | return false; | |
1555 | } | |
1556 | ||
1557 | size = GET_MODE_UNIT_BITSIZE (GET_MODE (op)); | |
1558 | mask = UINTVAL (XVECEXP (op, 0, 0)); | |
1559 | if (s390_contiguous_bitmask_p (mask, size, start, | |
1560 | end != NULL ? &length : NULL)) | |
1561 | { | |
1562 | if (end != NULL) | |
1563 | *end = *start + length - 1; | |
1564 | return true; | |
1565 | } | |
1566 | /* 0xff00000f style immediates can be covered by swapping start and | |
1567 | end indices in vgm. */ | |
1568 | if (s390_contiguous_bitmask_p (~mask, size, start, | |
1569 | end != NULL ? &length : NULL)) | |
1570 | { | |
1571 | if (end != NULL) | |
1572 | *end = *start - 1; | |
1573 | if (start != NULL) | |
1574 | *start = *start + length; | |
1575 | return true; | |
1576 | } | |
1577 | return false; | |
1578 | } | |
1579 | ||
1580 | /* Return true if C consists only of byte chunks being either 0 or | |
1581 | 0xff. If MASK is !=NULL a byte mask is generated which is | |
1582 | appropriate for the vector generate byte mask instruction. */ | |
1583 | ||
1584 | bool | |
1585 | s390_bytemask_vector_p (rtx op, unsigned *mask) | |
1586 | { | |
1587 | int i; | |
1588 | unsigned tmp_mask = 0; | |
1589 | int nunit, unit_size; | |
1590 | ||
1591 | if (!VECTOR_MODE_P (GET_MODE (op)) | |
1592 | || GET_CODE (op) != CONST_VECTOR | |
1593 | || !CONST_INT_P (XVECEXP (op, 0, 0))) | |
1594 | return false; | |
1595 | ||
1596 | nunit = GET_MODE_NUNITS (GET_MODE (op)); | |
1597 | unit_size = GET_MODE_UNIT_SIZE (GET_MODE (op)); | |
1598 | ||
1599 | for (i = 0; i < nunit; i++) | |
1600 | { | |
1601 | unsigned HOST_WIDE_INT c; | |
1602 | int j; | |
1603 | ||
1604 | if (!CONST_INT_P (XVECEXP (op, 0, i))) | |
1605 | return false; | |
1606 | ||
1607 | c = UINTVAL (XVECEXP (op, 0, i)); | |
1608 | for (j = 0; j < unit_size; j++) | |
1609 | { | |
1610 | if ((c & 0xff) != 0 && (c & 0xff) != 0xff) | |
1611 | return false; | |
1612 | tmp_mask |= (c & 1) << ((nunit - 1 - i) * unit_size + j); | |
1613 | c = c >> BITS_PER_UNIT; | |
1614 | } | |
1615 | } | |
1616 | ||
1617 | if (mask != NULL) | |
1618 | *mask = tmp_mask; | |
1619 | ||
1620 | return true; | |
1621 | } | |
1622 | ||
1a2e356e RH |
1623 | /* Check whether a rotate of ROTL followed by an AND of CONTIG is |
1624 | equivalent to a shift followed by the AND. In particular, CONTIG | |
1625 | should not overlap the (rotated) bit 0/bit 63 gap. Negative values | |
1626 | for ROTL indicate a rotate to the right. */ | |
1627 | ||
1628 | bool | |
1629 | s390_extzv_shift_ok (int bitsize, int rotl, unsigned HOST_WIDE_INT contig) | |
1630 | { | |
1631 | int pos, len; | |
1632 | bool ok; | |
1633 | ||
1634 | ok = s390_contiguous_bitmask_p (contig, bitsize, &pos, &len); | |
1635 | gcc_assert (ok); | |
1636 | ||
1637 | return ((rotl >= 0 && rotl <= pos) | |
1638 | || (rotl < 0 && -rotl <= bitsize - len - pos)); | |
1639 | } | |
1640 | ||
c7453384 EC |
1641 | /* Check whether we can (and want to) split a double-word |
1642 | move in mode MODE from SRC to DST into two single-word | |
dc65c307 UW |
1643 | moves, moving the subword FIRST_SUBWORD first. */ |
1644 | ||
1645 | bool | |
ef4bddc2 | 1646 | s390_split_ok_p (rtx dst, rtx src, machine_mode mode, int first_subword) |
dc65c307 | 1647 | { |
085261c8 AK |
1648 | /* Floating point and vector registers cannot be split. */ |
1649 | if (FP_REG_P (src) || FP_REG_P (dst) || VECTOR_REG_P (src) || VECTOR_REG_P (dst)) | |
dc65c307 UW |
1650 | return false; |
1651 | ||
fae778eb | 1652 | /* We don't need to split if operands are directly accessible. */ |
dc65c307 UW |
1653 | if (s_operand (src, mode) || s_operand (dst, mode)) |
1654 | return false; | |
1655 | ||
1656 | /* Non-offsettable memory references cannot be split. */ | |
1657 | if ((GET_CODE (src) == MEM && !offsettable_memref_p (src)) | |
1658 | || (GET_CODE (dst) == MEM && !offsettable_memref_p (dst))) | |
1659 | return false; | |
1660 | ||
1661 | /* Moving the first subword must not clobber a register | |
1662 | needed to move the second subword. */ | |
1663 | if (register_operand (dst, mode)) | |
1664 | { | |
1665 | rtx subreg = operand_subword (dst, first_subword, 0, mode); | |
1666 | if (reg_overlap_mentioned_p (subreg, src)) | |
1667 | return false; | |
1668 | } | |
1669 | ||
1670 | return true; | |
1671 | } | |
1672 | ||
bcf8c1cc AK |
1673 | /* Return true if it can be proven that [MEM1, MEM1 + SIZE] |
1674 | and [MEM2, MEM2 + SIZE] do overlap and false | |
1675 | otherwise. */ | |
1676 | ||
1677 | bool | |
1678 | s390_overlap_p (rtx mem1, rtx mem2, HOST_WIDE_INT size) | |
1679 | { | |
1680 | rtx addr1, addr2, addr_delta; | |
1681 | HOST_WIDE_INT delta; | |
1682 | ||
1683 | if (GET_CODE (mem1) != MEM || GET_CODE (mem2) != MEM) | |
1684 | return true; | |
1685 | ||
1686 | if (size == 0) | |
1687 | return false; | |
1688 | ||
1689 | addr1 = XEXP (mem1, 0); | |
1690 | addr2 = XEXP (mem2, 0); | |
1691 | ||
1692 | addr_delta = simplify_binary_operation (MINUS, Pmode, addr2, addr1); | |
1693 | ||
1694 | /* This overlapping check is used by peepholes merging memory block operations. | |
1695 | Overlapping operations would otherwise be recognized by the S/390 hardware | |
f4aa3848 | 1696 | and would fall back to a slower implementation. Allowing overlapping |
bcf8c1cc | 1697 | operations would lead to slow code but not to wrong code. Therefore we are |
f4aa3848 | 1698 | somewhat optimistic if we cannot prove that the memory blocks are |
bcf8c1cc AK |
1699 | overlapping. |
1700 | That's why we return false here although this may accept operations on | |
1701 | overlapping memory areas. */ | |
1702 | if (!addr_delta || GET_CODE (addr_delta) != CONST_INT) | |
1703 | return false; | |
1704 | ||
1705 | delta = INTVAL (addr_delta); | |
1706 | ||
1707 | if (delta == 0 | |
1708 | || (delta > 0 && delta < size) | |
1709 | || (delta < 0 && -delta < size)) | |
1710 | return true; | |
1711 | ||
1712 | return false; | |
1713 | } | |
1714 | ||
19b63d8e UW |
1715 | /* Check whether the address of memory reference MEM2 equals exactly |
1716 | the address of memory reference MEM1 plus DELTA. Return true if | |
1717 | we can prove this to be the case, false otherwise. */ | |
1718 | ||
1719 | bool | |
1720 | s390_offset_p (rtx mem1, rtx mem2, rtx delta) | |
1721 | { | |
1722 | rtx addr1, addr2, addr_delta; | |
1723 | ||
1724 | if (GET_CODE (mem1) != MEM || GET_CODE (mem2) != MEM) | |
1725 | return false; | |
1726 | ||
1727 | addr1 = XEXP (mem1, 0); | |
1728 | addr2 = XEXP (mem2, 0); | |
1729 | ||
1730 | addr_delta = simplify_binary_operation (MINUS, Pmode, addr2, addr1); | |
1731 | if (!addr_delta || !rtx_equal_p (addr_delta, delta)) | |
1732 | return false; | |
1733 | ||
1734 | return true; | |
1735 | } | |
1736 | ||
8cb66696 UW |
1737 | /* Expand logical operator CODE in mode MODE with operands OPERANDS. */ |
1738 | ||
1739 | void | |
ef4bddc2 | 1740 | s390_expand_logical_operator (enum rtx_code code, machine_mode mode, |
8cb66696 UW |
1741 | rtx *operands) |
1742 | { | |
ef4bddc2 | 1743 | machine_mode wmode = mode; |
8cb66696 UW |
1744 | rtx dst = operands[0]; |
1745 | rtx src1 = operands[1]; | |
1746 | rtx src2 = operands[2]; | |
1747 | rtx op, clob, tem; | |
1748 | ||
1749 | /* If we cannot handle the operation directly, use a temp register. */ | |
1750 | if (!s390_logical_operator_ok_p (operands)) | |
1751 | dst = gen_reg_rtx (mode); | |
1752 | ||
1753 | /* QImode and HImode patterns make sense only if we have a destination | |
1754 | in memory. Otherwise perform the operation in SImode. */ | |
1755 | if ((mode == QImode || mode == HImode) && GET_CODE (dst) != MEM) | |
1756 | wmode = SImode; | |
1757 | ||
1758 | /* Widen operands if required. */ | |
1759 | if (mode != wmode) | |
1760 | { | |
1761 | if (GET_CODE (dst) == SUBREG | |
1762 | && (tem = simplify_subreg (wmode, dst, mode, 0)) != 0) | |
1763 | dst = tem; | |
1764 | else if (REG_P (dst)) | |
1765 | dst = gen_rtx_SUBREG (wmode, dst, 0); | |
1766 | else | |
1767 | dst = gen_reg_rtx (wmode); | |
1768 | ||
1769 | if (GET_CODE (src1) == SUBREG | |
1770 | && (tem = simplify_subreg (wmode, src1, mode, 0)) != 0) | |
1771 | src1 = tem; | |
1772 | else if (GET_MODE (src1) != VOIDmode) | |
1773 | src1 = gen_rtx_SUBREG (wmode, force_reg (mode, src1), 0); | |
1774 | ||
1775 | if (GET_CODE (src2) == SUBREG | |
1776 | && (tem = simplify_subreg (wmode, src2, mode, 0)) != 0) | |
1777 | src2 = tem; | |
1778 | else if (GET_MODE (src2) != VOIDmode) | |
1779 | src2 = gen_rtx_SUBREG (wmode, force_reg (mode, src2), 0); | |
1780 | } | |
1781 | ||
1782 | /* Emit the instruction. */ | |
f7df4a84 | 1783 | op = gen_rtx_SET (dst, gen_rtx_fmt_ee (code, wmode, src1, src2)); |
8cb66696 UW |
1784 | clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM)); |
1785 | emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clob))); | |
1786 | ||
1787 | /* Fix up the destination if needed. */ | |
1788 | if (dst != operands[0]) | |
1789 | emit_move_insn (operands[0], gen_lowpart (mode, dst)); | |
1790 | } | |
1791 | ||
1792 | /* Check whether OPERANDS are OK for a logical operation (AND, IOR, XOR). */ | |
1793 | ||
1794 | bool | |
1795 | s390_logical_operator_ok_p (rtx *operands) | |
1796 | { | |
1797 | /* If the destination operand is in memory, it needs to coincide | |
1798 | with one of the source operands. After reload, it has to be | |
1799 | the first source operand. */ | |
1800 | if (GET_CODE (operands[0]) == MEM) | |
1801 | return rtx_equal_p (operands[0], operands[1]) | |
1802 | || (!reload_completed && rtx_equal_p (operands[0], operands[2])); | |
1803 | ||
1804 | return true; | |
1805 | } | |
1806 | ||
0dfa6c5e UW |
1807 | /* Narrow logical operation CODE of memory operand MEMOP with immediate |
1808 | operand IMMOP to switch from SS to SI type instructions. */ | |
1809 | ||
1810 | void | |
1811 | s390_narrow_logical_operator (enum rtx_code code, rtx *memop, rtx *immop) | |
1812 | { | |
1813 | int def = code == AND ? -1 : 0; | |
1814 | HOST_WIDE_INT mask; | |
1815 | int part; | |
1816 | ||
1817 | gcc_assert (GET_CODE (*memop) == MEM); | |
1818 | gcc_assert (!MEM_VOLATILE_P (*memop)); | |
1819 | ||
1820 | mask = s390_extract_part (*immop, QImode, def); | |
1821 | part = s390_single_part (*immop, GET_MODE (*memop), QImode, def); | |
1822 | gcc_assert (part >= 0); | |
1823 | ||
1824 | *memop = adjust_address (*memop, QImode, part); | |
1825 | *immop = gen_int_mode (mask, QImode); | |
1826 | } | |
1827 | ||
ba956982 | 1828 | |
ab96de7e AS |
1829 | /* How to allocate a 'struct machine_function'. */ |
1830 | ||
1831 | static struct machine_function * | |
1832 | s390_init_machine_status (void) | |
1833 | { | |
766090c2 | 1834 | return ggc_cleared_alloc<machine_function> (); |
ab96de7e AS |
1835 | } |
1836 | ||
9db1d521 HP |
1837 | /* Map for smallest class containing reg regno. */ |
1838 | ||
0139adca | 1839 | const enum reg_class regclass_map[FIRST_PSEUDO_REGISTER] = |
085261c8 AK |
1840 | { GENERAL_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS, /* 0 */ |
1841 | ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS, /* 4 */ | |
1842 | ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS, /* 8 */ | |
1843 | ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS, /* 12 */ | |
1844 | FP_REGS, FP_REGS, FP_REGS, FP_REGS, /* 16 */ | |
1845 | FP_REGS, FP_REGS, FP_REGS, FP_REGS, /* 20 */ | |
1846 | FP_REGS, FP_REGS, FP_REGS, FP_REGS, /* 24 */ | |
1847 | FP_REGS, FP_REGS, FP_REGS, FP_REGS, /* 28 */ | |
1848 | ADDR_REGS, CC_REGS, ADDR_REGS, ADDR_REGS, /* 32 */ | |
1849 | ACCESS_REGS, ACCESS_REGS, VEC_REGS, VEC_REGS, /* 36 */ | |
1850 | VEC_REGS, VEC_REGS, VEC_REGS, VEC_REGS, /* 40 */ | |
1851 | VEC_REGS, VEC_REGS, VEC_REGS, VEC_REGS, /* 44 */ | |
1852 | VEC_REGS, VEC_REGS, VEC_REGS, VEC_REGS, /* 48 */ | |
1853 | VEC_REGS, VEC_REGS /* 52 */ | |
9db1d521 HP |
1854 | }; |
1855 | ||
077dab3b HP |
1856 | /* Return attribute type of insn. */ |
1857 | ||
1858 | static enum attr_type | |
647d790d | 1859 | s390_safe_attr_type (rtx_insn *insn) |
077dab3b HP |
1860 | { |
1861 | if (recog_memoized (insn) >= 0) | |
1862 | return get_attr_type (insn); | |
1863 | else | |
1864 | return TYPE_NONE; | |
1865 | } | |
9db1d521 | 1866 | |
d3632d41 UW |
1867 | /* Return true if DISP is a valid short displacement. */ |
1868 | ||
3ed99cc9 | 1869 | static bool |
9c808aad | 1870 | s390_short_displacement (rtx disp) |
d3632d41 UW |
1871 | { |
1872 | /* No displacement is OK. */ | |
1873 | if (!disp) | |
3ed99cc9 | 1874 | return true; |
d3632d41 | 1875 | |
4fe6dea8 AK |
1876 | /* Without the long displacement facility we don't need to |
1877 | distingiush between long and short displacement. */ | |
1878 | if (!TARGET_LONG_DISPLACEMENT) | |
1879 | return true; | |
1880 | ||
d3632d41 UW |
1881 | /* Integer displacement in range. */ |
1882 | if (GET_CODE (disp) == CONST_INT) | |
1883 | return INTVAL (disp) >= 0 && INTVAL (disp) < 4096; | |
1884 | ||
1885 | /* GOT offset is not OK, the GOT can be large. */ | |
1886 | if (GET_CODE (disp) == CONST | |
1887 | && GET_CODE (XEXP (disp, 0)) == UNSPEC | |
227a39fa UW |
1888 | && (XINT (XEXP (disp, 0), 1) == UNSPEC_GOT |
1889 | || XINT (XEXP (disp, 0), 1) == UNSPEC_GOTNTPOFF)) | |
3ed99cc9 | 1890 | return false; |
d3632d41 UW |
1891 | |
1892 | /* All other symbolic constants are literal pool references, | |
1893 | which are OK as the literal pool must be small. */ | |
1894 | if (GET_CODE (disp) == CONST) | |
3ed99cc9 | 1895 | return true; |
d3632d41 | 1896 | |
3ed99cc9 | 1897 | return false; |
d3632d41 UW |
1898 | } |
1899 | ||
ab96de7e AS |
1900 | /* Decompose a RTL expression ADDR for a memory address into |
1901 | its components, returned in OUT. | |
ccfc6cc8 | 1902 | |
3ed99cc9 | 1903 | Returns false if ADDR is not a valid memory address, true |
ab96de7e AS |
1904 | otherwise. If OUT is NULL, don't return the components, |
1905 | but check for validity only. | |
ccfc6cc8 | 1906 | |
ab96de7e AS |
1907 | Note: Only addresses in canonical form are recognized. |
1908 | LEGITIMIZE_ADDRESS should convert non-canonical forms to the | |
1909 | canonical form so that they will be recognized. */ | |
f19a9af7 | 1910 | |
ab96de7e | 1911 | static int |
5d81b82b | 1912 | s390_decompose_address (rtx addr, struct s390_address *out) |
ab96de7e AS |
1913 | { |
1914 | HOST_WIDE_INT offset = 0; | |
1915 | rtx base = NULL_RTX; | |
1916 | rtx indx = NULL_RTX; | |
1917 | rtx disp = NULL_RTX; | |
1918 | rtx orig_disp; | |
3ed99cc9 AS |
1919 | bool pointer = false; |
1920 | bool base_ptr = false; | |
1921 | bool indx_ptr = false; | |
f01cf809 UW |
1922 | bool literal_pool = false; |
1923 | ||
1924 | /* We may need to substitute the literal pool base register into the address | |
1925 | below. However, at this point we do not know which register is going to | |
1926 | be used as base, so we substitute the arg pointer register. This is going | |
1927 | to be treated as holding a pointer below -- it shouldn't be used for any | |
1928 | other purpose. */ | |
1929 | rtx fake_pool_base = gen_rtx_REG (Pmode, ARG_POINTER_REGNUM); | |
0dfa6c5e | 1930 | |
ab96de7e | 1931 | /* Decompose address into base + index + displacement. */ |
0dfa6c5e | 1932 | |
ab96de7e AS |
1933 | if (GET_CODE (addr) == REG || GET_CODE (addr) == UNSPEC) |
1934 | base = addr; | |
0dfa6c5e | 1935 | |
ab96de7e | 1936 | else if (GET_CODE (addr) == PLUS) |
e221ef54 | 1937 | { |
ab96de7e AS |
1938 | rtx op0 = XEXP (addr, 0); |
1939 | rtx op1 = XEXP (addr, 1); | |
1940 | enum rtx_code code0 = GET_CODE (op0); | |
1941 | enum rtx_code code1 = GET_CODE (op1); | |
e221ef54 | 1942 | |
ab96de7e AS |
1943 | if (code0 == REG || code0 == UNSPEC) |
1944 | { | |
1945 | if (code1 == REG || code1 == UNSPEC) | |
1946 | { | |
1947 | indx = op0; /* index + base */ | |
1948 | base = op1; | |
1949 | } | |
e221ef54 | 1950 | |
ab96de7e AS |
1951 | else |
1952 | { | |
1953 | base = op0; /* base + displacement */ | |
1954 | disp = op1; | |
1955 | } | |
1956 | } | |
ccfc6cc8 | 1957 | |
ab96de7e | 1958 | else if (code0 == PLUS) |
d3632d41 | 1959 | { |
ab96de7e AS |
1960 | indx = XEXP (op0, 0); /* index + base + disp */ |
1961 | base = XEXP (op0, 1); | |
1962 | disp = op1; | |
d3632d41 | 1963 | } |
d3632d41 | 1964 | |
ab96de7e | 1965 | else |
d3632d41 | 1966 | { |
3ed99cc9 | 1967 | return false; |
d3632d41 | 1968 | } |
ab96de7e | 1969 | } |
d3632d41 | 1970 | |
ab96de7e AS |
1971 | else |
1972 | disp = addr; /* displacement */ | |
d3632d41 | 1973 | |
ab96de7e AS |
1974 | /* Extract integer part of displacement. */ |
1975 | orig_disp = disp; | |
1976 | if (disp) | |
1977 | { | |
1978 | if (GET_CODE (disp) == CONST_INT) | |
d3632d41 | 1979 | { |
ab96de7e AS |
1980 | offset = INTVAL (disp); |
1981 | disp = NULL_RTX; | |
d3632d41 | 1982 | } |
ab96de7e AS |
1983 | else if (GET_CODE (disp) == CONST |
1984 | && GET_CODE (XEXP (disp, 0)) == PLUS | |
1985 | && GET_CODE (XEXP (XEXP (disp, 0), 1)) == CONST_INT) | |
1986 | { | |
1987 | offset = INTVAL (XEXP (XEXP (disp, 0), 1)); | |
1988 | disp = XEXP (XEXP (disp, 0), 0); | |
1989 | } | |
1990 | } | |
d3632d41 | 1991 | |
ab96de7e AS |
1992 | /* Strip off CONST here to avoid special case tests later. */ |
1993 | if (disp && GET_CODE (disp) == CONST) | |
1994 | disp = XEXP (disp, 0); | |
ac32b25e | 1995 | |
ab96de7e AS |
1996 | /* We can convert literal pool addresses to |
1997 | displacements by basing them off the base register. */ | |
1998 | if (disp && GET_CODE (disp) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (disp)) | |
1999 | { | |
2000 | /* Either base or index must be free to hold the base register. */ | |
2001 | if (!base) | |
f01cf809 | 2002 | base = fake_pool_base, literal_pool = true; |
ab96de7e | 2003 | else if (!indx) |
f01cf809 | 2004 | indx = fake_pool_base, literal_pool = true; |
ab96de7e | 2005 | else |
3ed99cc9 | 2006 | return false; |
ab96de7e AS |
2007 | |
2008 | /* Mark up the displacement. */ | |
2009 | disp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, disp), | |
2010 | UNSPEC_LTREL_OFFSET); | |
d3632d41 | 2011 | } |
ccfc6cc8 | 2012 | |
ab96de7e AS |
2013 | /* Validate base register. */ |
2014 | if (base) | |
2015 | { | |
2016 | if (GET_CODE (base) == UNSPEC) | |
2017 | switch (XINT (base, 1)) | |
2018 | { | |
2019 | case UNSPEC_LTREF: | |
2020 | if (!disp) | |
f4aa3848 | 2021 | disp = gen_rtx_UNSPEC (Pmode, |
ab96de7e AS |
2022 | gen_rtvec (1, XVECEXP (base, 0, 0)), |
2023 | UNSPEC_LTREL_OFFSET); | |
2024 | else | |
3ed99cc9 | 2025 | return false; |
ccfc6cc8 | 2026 | |
f01cf809 | 2027 | base = XVECEXP (base, 0, 1); |
ab96de7e | 2028 | break; |
f19a9af7 | 2029 | |
ab96de7e | 2030 | case UNSPEC_LTREL_BASE: |
f01cf809 UW |
2031 | if (XVECLEN (base, 0) == 1) |
2032 | base = fake_pool_base, literal_pool = true; | |
2033 | else | |
2034 | base = XVECEXP (base, 0, 1); | |
ab96de7e | 2035 | break; |
f19a9af7 | 2036 | |
ab96de7e | 2037 | default: |
3ed99cc9 | 2038 | return false; |
ab96de7e | 2039 | } |
f19a9af7 | 2040 | |
f4aa3848 AK |
2041 | if (!REG_P (base) |
2042 | || (GET_MODE (base) != SImode | |
93fa8428 | 2043 | && GET_MODE (base) != Pmode)) |
3ed99cc9 | 2044 | return false; |
ab96de7e | 2045 | |
f01cf809 | 2046 | if (REGNO (base) == STACK_POINTER_REGNUM |
ab96de7e AS |
2047 | || REGNO (base) == FRAME_POINTER_REGNUM |
2048 | || ((reload_completed || reload_in_progress) | |
2049 | && frame_pointer_needed | |
2050 | && REGNO (base) == HARD_FRAME_POINTER_REGNUM) | |
2051 | || REGNO (base) == ARG_POINTER_REGNUM | |
2052 | || (flag_pic | |
2053 | && REGNO (base) == PIC_OFFSET_TABLE_REGNUM)) | |
3ed99cc9 | 2054 | pointer = base_ptr = true; |
f01cf809 UW |
2055 | |
2056 | if ((reload_completed || reload_in_progress) | |
2057 | && base == cfun->machine->base_reg) | |
2058 | pointer = base_ptr = literal_pool = true; | |
ab96de7e AS |
2059 | } |
2060 | ||
2061 | /* Validate index register. */ | |
2062 | if (indx) | |
f19a9af7 | 2063 | { |
ab96de7e AS |
2064 | if (GET_CODE (indx) == UNSPEC) |
2065 | switch (XINT (indx, 1)) | |
2066 | { | |
2067 | case UNSPEC_LTREF: | |
2068 | if (!disp) | |
f4aa3848 | 2069 | disp = gen_rtx_UNSPEC (Pmode, |
ab96de7e AS |
2070 | gen_rtvec (1, XVECEXP (indx, 0, 0)), |
2071 | UNSPEC_LTREL_OFFSET); | |
2072 | else | |
3ed99cc9 | 2073 | return false; |
f19a9af7 | 2074 | |
f01cf809 | 2075 | indx = XVECEXP (indx, 0, 1); |
ab96de7e | 2076 | break; |
f19a9af7 | 2077 | |
ab96de7e | 2078 | case UNSPEC_LTREL_BASE: |
f01cf809 UW |
2079 | if (XVECLEN (indx, 0) == 1) |
2080 | indx = fake_pool_base, literal_pool = true; | |
2081 | else | |
2082 | indx = XVECEXP (indx, 0, 1); | |
ab96de7e | 2083 | break; |
f19a9af7 | 2084 | |
ab96de7e | 2085 | default: |
3ed99cc9 | 2086 | return false; |
ab96de7e | 2087 | } |
f19a9af7 | 2088 | |
f4aa3848 | 2089 | if (!REG_P (indx) |
93fa8428 AK |
2090 | || (GET_MODE (indx) != SImode |
2091 | && GET_MODE (indx) != Pmode)) | |
3ed99cc9 | 2092 | return false; |
f19a9af7 | 2093 | |
f01cf809 | 2094 | if (REGNO (indx) == STACK_POINTER_REGNUM |
ab96de7e AS |
2095 | || REGNO (indx) == FRAME_POINTER_REGNUM |
2096 | || ((reload_completed || reload_in_progress) | |
2097 | && frame_pointer_needed | |
2098 | && REGNO (indx) == HARD_FRAME_POINTER_REGNUM) | |
2099 | || REGNO (indx) == ARG_POINTER_REGNUM | |
2100 | || (flag_pic | |
2101 | && REGNO (indx) == PIC_OFFSET_TABLE_REGNUM)) | |
3ed99cc9 | 2102 | pointer = indx_ptr = true; |
f01cf809 UW |
2103 | |
2104 | if ((reload_completed || reload_in_progress) | |
2105 | && indx == cfun->machine->base_reg) | |
2106 | pointer = indx_ptr = literal_pool = true; | |
ab96de7e | 2107 | } |
38899e29 | 2108 | |
ab96de7e AS |
2109 | /* Prefer to use pointer as base, not index. */ |
2110 | if (base && indx && !base_ptr | |
2111 | && (indx_ptr || (!REG_POINTER (base) && REG_POINTER (indx)))) | |
2112 | { | |
2113 | rtx tmp = base; | |
2114 | base = indx; | |
2115 | indx = tmp; | |
2116 | } | |
f19a9af7 | 2117 | |
ab96de7e AS |
2118 | /* Validate displacement. */ |
2119 | if (!disp) | |
2120 | { | |
f4aa3848 AK |
2121 | /* If virtual registers are involved, the displacement will change later |
2122 | anyway as the virtual registers get eliminated. This could make a | |
2123 | valid displacement invalid, but it is more likely to make an invalid | |
2124 | displacement valid, because we sometimes access the register save area | |
63296cb1 | 2125 | via negative offsets to one of those registers. |
ab96de7e AS |
2126 | Thus we don't check the displacement for validity here. If after |
2127 | elimination the displacement turns out to be invalid after all, | |
2128 | this is fixed up by reload in any case. */ | |
3597e113 VM |
2129 | /* LRA maintains always displacements up to date and we need to |
2130 | know the displacement is right during all LRA not only at the | |
2131 | final elimination. */ | |
2132 | if (lra_in_progress | |
2133 | || (base != arg_pointer_rtx | |
2134 | && indx != arg_pointer_rtx | |
2135 | && base != return_address_pointer_rtx | |
2136 | && indx != return_address_pointer_rtx | |
2137 | && base != frame_pointer_rtx | |
2138 | && indx != frame_pointer_rtx | |
2139 | && base != virtual_stack_vars_rtx | |
2140 | && indx != virtual_stack_vars_rtx)) | |
ab96de7e | 2141 | if (!DISP_IN_RANGE (offset)) |
3ed99cc9 | 2142 | return false; |
ab96de7e AS |
2143 | } |
2144 | else | |
2145 | { | |
2146 | /* All the special cases are pointers. */ | |
3ed99cc9 | 2147 | pointer = true; |
f19a9af7 | 2148 | |
ab96de7e AS |
2149 | /* In the small-PIC case, the linker converts @GOT |
2150 | and @GOTNTPOFF offsets to possible displacements. */ | |
2151 | if (GET_CODE (disp) == UNSPEC | |
2152 | && (XINT (disp, 1) == UNSPEC_GOT | |
2153 | || XINT (disp, 1) == UNSPEC_GOTNTPOFF) | |
ab96de7e AS |
2154 | && flag_pic == 1) |
2155 | { | |
2156 | ; | |
2157 | } | |
f19a9af7 | 2158 | |
dc66391d RS |
2159 | /* Accept pool label offsets. */ |
2160 | else if (GET_CODE (disp) == UNSPEC | |
2161 | && XINT (disp, 1) == UNSPEC_POOL_OFFSET) | |
2162 | ; | |
f19a9af7 | 2163 | |
ab96de7e AS |
2164 | /* Accept literal pool references. */ |
2165 | else if (GET_CODE (disp) == UNSPEC | |
2166 | && XINT (disp, 1) == UNSPEC_LTREL_OFFSET) | |
2167 | { | |
bc6ce334 AK |
2168 | /* In case CSE pulled a non literal pool reference out of |
2169 | the pool we have to reject the address. This is | |
2170 | especially important when loading the GOT pointer on non | |
2171 | zarch CPUs. In this case the literal pool contains an lt | |
2172 | relative offset to the _GLOBAL_OFFSET_TABLE_ label which | |
2173 | will most likely exceed the displacement. */ | |
2174 | if (GET_CODE (XVECEXP (disp, 0, 0)) != SYMBOL_REF | |
2175 | || !CONSTANT_POOL_ADDRESS_P (XVECEXP (disp, 0, 0))) | |
2176 | return false; | |
2177 | ||
ab96de7e AS |
2178 | orig_disp = gen_rtx_CONST (Pmode, disp); |
2179 | if (offset) | |
2180 | { | |
2181 | /* If we have an offset, make sure it does not | |
2182 | exceed the size of the constant pool entry. */ | |
2183 | rtx sym = XVECEXP (disp, 0, 0); | |
2184 | if (offset >= GET_MODE_SIZE (get_pool_mode (sym))) | |
3ed99cc9 | 2185 | return false; |
f19a9af7 | 2186 | |
0a81f074 | 2187 | orig_disp = plus_constant (Pmode, orig_disp, offset); |
ab96de7e AS |
2188 | } |
2189 | } | |
2190 | ||
2191 | else | |
3ed99cc9 | 2192 | return false; |
f19a9af7 AK |
2193 | } |
2194 | ||
ab96de7e | 2195 | if (!base && !indx) |
3ed99cc9 | 2196 | pointer = true; |
ab96de7e AS |
2197 | |
2198 | if (out) | |
2199 | { | |
2200 | out->base = base; | |
2201 | out->indx = indx; | |
2202 | out->disp = orig_disp; | |
2203 | out->pointer = pointer; | |
f01cf809 | 2204 | out->literal_pool = literal_pool; |
ab96de7e AS |
2205 | } |
2206 | ||
3ed99cc9 | 2207 | return true; |
f19a9af7 AK |
2208 | } |
2209 | ||
d98ad410 UW |
2210 | /* Decompose a RTL expression OP for a shift count into its components, |
2211 | and return the base register in BASE and the offset in OFFSET. | |
2212 | ||
d98ad410 UW |
2213 | Return true if OP is a valid shift count, false if not. */ |
2214 | ||
2215 | bool | |
4989e88a | 2216 | s390_decompose_shift_count (rtx op, rtx *base, HOST_WIDE_INT *offset) |
d98ad410 UW |
2217 | { |
2218 | HOST_WIDE_INT off = 0; | |
2219 | ||
d98ad410 UW |
2220 | /* We can have an integer constant, an address register, |
2221 | or a sum of the two. */ | |
2222 | if (GET_CODE (op) == CONST_INT) | |
2223 | { | |
2224 | off = INTVAL (op); | |
2225 | op = NULL_RTX; | |
2226 | } | |
2227 | if (op && GET_CODE (op) == PLUS && GET_CODE (XEXP (op, 1)) == CONST_INT) | |
2228 | { | |
2229 | off = INTVAL (XEXP (op, 1)); | |
2230 | op = XEXP (op, 0); | |
2231 | } | |
2232 | while (op && GET_CODE (op) == SUBREG) | |
2233 | op = SUBREG_REG (op); | |
2234 | ||
2235 | if (op && GET_CODE (op) != REG) | |
2236 | return false; | |
2237 | ||
2238 | if (offset) | |
2239 | *offset = off; | |
2240 | if (base) | |
2241 | *base = op; | |
2242 | ||
2243 | return true; | |
2244 | } | |
2245 | ||
2246 | ||
ab96de7e | 2247 | /* Return true if CODE is a valid address without index. */ |
3c50106f | 2248 | |
ab96de7e AS |
2249 | bool |
2250 | s390_legitimate_address_without_index_p (rtx op) | |
2251 | { | |
2252 | struct s390_address addr; | |
2253 | ||
2254 | if (!s390_decompose_address (XEXP (op, 0), &addr)) | |
2255 | return false; | |
2256 | if (addr.indx) | |
2257 | return false; | |
2258 | ||
2259 | return true; | |
2260 | } | |
2261 | ||
cd8dc1f9 | 2262 | |
0ff4390d AK |
2263 | /* Return TRUE if ADDR is an operand valid for a load/store relative |
2264 | instruction. Be aware that the alignment of the operand needs to | |
2265 | be checked separately. | |
2266 | Valid addresses are single references or a sum of a reference and a | |
2267 | constant integer. Return these parts in SYMREF and ADDEND. You can | |
2268 | pass NULL in REF and/or ADDEND if you are not interested in these | |
2269 | values. Literal pool references are *not* considered symbol | |
2270 | references. */ | |
ab96de7e | 2271 | |
4fe6dea8 | 2272 | static bool |
0ff4390d | 2273 | s390_loadrelative_operand_p (rtx addr, rtx *symref, HOST_WIDE_INT *addend) |
ab96de7e | 2274 | { |
4fe6dea8 | 2275 | HOST_WIDE_INT tmpaddend = 0; |
ab96de7e | 2276 | |
4fe6dea8 AK |
2277 | if (GET_CODE (addr) == CONST) |
2278 | addr = XEXP (addr, 0); | |
2279 | ||
2280 | if (GET_CODE (addr) == PLUS) | |
ab96de7e | 2281 | { |
0ff4390d | 2282 | if (!CONST_INT_P (XEXP (addr, 1))) |
4fe6dea8 | 2283 | return false; |
ab96de7e | 2284 | |
0ff4390d AK |
2285 | tmpaddend = INTVAL (XEXP (addr, 1)); |
2286 | addr = XEXP (addr, 0); | |
2287 | } | |
98412b77 | 2288 | |
0ff4390d AK |
2289 | if ((GET_CODE (addr) == SYMBOL_REF && !CONSTANT_POOL_ADDRESS_P (addr)) |
2290 | || (GET_CODE (addr) == UNSPEC | |
2291 | && (XINT (addr, 1) == UNSPEC_GOTENT | |
2292 | || (TARGET_CPU_ZARCH && XINT (addr, 1) == UNSPEC_PLT)))) | |
2293 | { | |
2294 | if (symref) | |
2295 | *symref = addr; | |
2296 | if (addend) | |
2297 | *addend = tmpaddend; | |
98412b77 | 2298 | |
0ff4390d AK |
2299 | return true; |
2300 | } | |
2301 | return false; | |
98412b77 | 2302 | } |
4fe6dea8 AK |
2303 | |
2304 | /* Return true if the address in OP is valid for constraint letter C | |
2305 | if wrapped in a MEM rtx. Set LIT_POOL_OK to true if it literal | |
2306 | pool MEMs should be accepted. Only the Q, R, S, T constraint | |
2307 | letters are allowed for C. */ | |
ab96de7e | 2308 | |
4fe6dea8 AK |
2309 | static int |
2310 | s390_check_qrst_address (char c, rtx op, bool lit_pool_ok) | |
2311 | { | |
2312 | struct s390_address addr; | |
2313 | bool decomposed = false; | |
2314 | ||
2315 | /* This check makes sure that no symbolic address (except literal | |
2316 | pool references) are accepted by the R or T constraints. */ | |
0ff4390d | 2317 | if (s390_loadrelative_operand_p (op, NULL, NULL)) |
98635b04 UW |
2318 | return 0; |
2319 | ||
2320 | /* Ensure literal pool references are only accepted if LIT_POOL_OK. */ | |
2321 | if (!lit_pool_ok) | |
ab96de7e | 2322 | { |
4fe6dea8 | 2323 | if (!s390_decompose_address (op, &addr)) |
ab96de7e | 2324 | return 0; |
98635b04 | 2325 | if (addr.literal_pool) |
ab96de7e | 2326 | return 0; |
4fe6dea8 | 2327 | decomposed = true; |
ab96de7e AS |
2328 | } |
2329 | ||
2330 | switch (c) | |
2331 | { | |
4fe6dea8 AK |
2332 | case 'Q': /* no index short displacement */ |
2333 | if (!decomposed && !s390_decompose_address (op, &addr)) | |
ab96de7e AS |
2334 | return 0; |
2335 | if (addr.indx) | |
2336 | return 0; | |
4fe6dea8 | 2337 | if (!s390_short_displacement (addr.disp)) |
ab96de7e | 2338 | return 0; |
4fe6dea8 | 2339 | break; |
ab96de7e | 2340 | |
4fe6dea8 | 2341 | case 'R': /* with index short displacement */ |
ab96de7e AS |
2342 | if (TARGET_LONG_DISPLACEMENT) |
2343 | { | |
4fe6dea8 | 2344 | if (!decomposed && !s390_decompose_address (op, &addr)) |
ab96de7e AS |
2345 | return 0; |
2346 | if (!s390_short_displacement (addr.disp)) | |
2347 | return 0; | |
2348 | } | |
4fe6dea8 AK |
2349 | /* Any invalid address here will be fixed up by reload, |
2350 | so accept it for the most generic constraint. */ | |
ab96de7e AS |
2351 | break; |
2352 | ||
4fe6dea8 | 2353 | case 'S': /* no index long displacement */ |
ab96de7e AS |
2354 | if (!TARGET_LONG_DISPLACEMENT) |
2355 | return 0; | |
4fe6dea8 | 2356 | if (!decomposed && !s390_decompose_address (op, &addr)) |
ab96de7e AS |
2357 | return 0; |
2358 | if (addr.indx) | |
2359 | return 0; | |
2360 | if (s390_short_displacement (addr.disp)) | |
2361 | return 0; | |
2362 | break; | |
2363 | ||
4fe6dea8 | 2364 | case 'T': /* with index long displacement */ |
ab96de7e AS |
2365 | if (!TARGET_LONG_DISPLACEMENT) |
2366 | return 0; | |
4fe6dea8 AK |
2367 | /* Any invalid address here will be fixed up by reload, |
2368 | so accept it for the most generic constraint. */ | |
2369 | if ((decomposed || s390_decompose_address (op, &addr)) | |
2370 | && s390_short_displacement (addr.disp)) | |
ab96de7e AS |
2371 | return 0; |
2372 | break; | |
4fe6dea8 AK |
2373 | default: |
2374 | return 0; | |
2375 | } | |
2376 | return 1; | |
2377 | } | |
ab96de7e | 2378 | |
ab96de7e | 2379 | |
4fe6dea8 AK |
2380 | /* Evaluates constraint strings described by the regular expression |
2381 | ([A|B|Z](Q|R|S|T))|U|W|Y and returns 1 if OP is a valid operand for | |
2382 | the constraint given in STR, or 0 else. */ | |
2383 | ||
2384 | int | |
2385 | s390_mem_constraint (const char *str, rtx op) | |
2386 | { | |
2387 | char c = str[0]; | |
2388 | ||
2389 | switch (c) | |
2390 | { | |
2391 | case 'A': | |
2392 | /* Check for offsettable variants of memory constraints. */ | |
2393 | if (!MEM_P (op) || MEM_VOLATILE_P (op)) | |
ab96de7e | 2394 | return 0; |
4fe6dea8 AK |
2395 | if ((reload_completed || reload_in_progress) |
2396 | ? !offsettable_memref_p (op) : !offsettable_nonstrict_memref_p (op)) | |
963fc8d0 | 2397 | return 0; |
4fe6dea8 AK |
2398 | return s390_check_qrst_address (str[1], XEXP (op, 0), true); |
2399 | case 'B': | |
2400 | /* Check for non-literal-pool variants of memory constraints. */ | |
2401 | if (!MEM_P (op)) | |
ab96de7e | 2402 | return 0; |
4fe6dea8 AK |
2403 | return s390_check_qrst_address (str[1], XEXP (op, 0), false); |
2404 | case 'Q': | |
2405 | case 'R': | |
2406 | case 'S': | |
2407 | case 'T': | |
2408 | if (GET_CODE (op) != MEM) | |
2409 | return 0; | |
2410 | return s390_check_qrst_address (c, XEXP (op, 0), true); | |
2411 | case 'U': | |
2412 | return (s390_check_qrst_address ('Q', op, true) | |
2413 | || s390_check_qrst_address ('R', op, true)); | |
2414 | case 'W': | |
2415 | return (s390_check_qrst_address ('S', op, true) | |
2416 | || s390_check_qrst_address ('T', op, true)); | |
ab96de7e | 2417 | case 'Y': |
d98ad410 UW |
2418 | /* Simply check for the basic form of a shift count. Reload will |
2419 | take care of making sure we have a proper base register. */ | |
4989e88a | 2420 | if (!s390_decompose_shift_count (op, NULL, NULL)) |
d98ad410 UW |
2421 | return 0; |
2422 | break; | |
4fe6dea8 AK |
2423 | case 'Z': |
2424 | return s390_check_qrst_address (str[1], op, true); | |
ab96de7e AS |
2425 | default: |
2426 | return 0; | |
2427 | } | |
ab96de7e AS |
2428 | return 1; |
2429 | } | |
2430 | ||
cd8dc1f9 | 2431 | |
cd8dc1f9 WG |
2432 | /* Evaluates constraint strings starting with letter O. Input |
2433 | parameter C is the second letter following the "O" in the constraint | |
2434 | string. Returns 1 if VALUE meets the respective constraint and 0 | |
2435 | otherwise. */ | |
ab96de7e | 2436 | |
d096725d | 2437 | int |
cd8dc1f9 | 2438 | s390_O_constraint_str (const char c, HOST_WIDE_INT value) |
d096725d | 2439 | { |
cd8dc1f9 WG |
2440 | if (!TARGET_EXTIMM) |
2441 | return 0; | |
d096725d | 2442 | |
cd8dc1f9 | 2443 | switch (c) |
d096725d | 2444 | { |
cd8dc1f9 WG |
2445 | case 's': |
2446 | return trunc_int_for_mode (value, SImode) == value; | |
2447 | ||
2448 | case 'p': | |
2449 | return value == 0 | |
2450 | || s390_single_part (GEN_INT (value), DImode, SImode, 0) == 1; | |
2451 | ||
2452 | case 'n': | |
ee3f3449 | 2453 | return s390_single_part (GEN_INT (value - 1), DImode, SImode, -1) == 1; |
cd8dc1f9 | 2454 | |
d096725d | 2455 | default: |
cd8dc1f9 | 2456 | gcc_unreachable (); |
d096725d AS |
2457 | } |
2458 | } | |
2459 | ||
cd8dc1f9 WG |
2460 | |
2461 | /* Evaluates constraint strings starting with letter N. Parameter STR | |
2462 | contains the letters following letter "N" in the constraint string. | |
2463 | Returns true if VALUE matches the constraint. */ | |
d096725d | 2464 | |
ab96de7e | 2465 | int |
cd8dc1f9 | 2466 | s390_N_constraint_str (const char *str, HOST_WIDE_INT value) |
ab96de7e | 2467 | { |
ef4bddc2 | 2468 | machine_mode mode, part_mode; |
ab96de7e AS |
2469 | int def; |
2470 | int part, part_goal; | |
2471 | ||
ab96de7e | 2472 | |
cd8dc1f9 WG |
2473 | if (str[0] == 'x') |
2474 | part_goal = -1; | |
2475 | else | |
2476 | part_goal = str[0] - '0'; | |
ab96de7e | 2477 | |
cd8dc1f9 WG |
2478 | switch (str[1]) |
2479 | { | |
2480 | case 'Q': | |
2481 | part_mode = QImode; | |
ab96de7e | 2482 | break; |
cd8dc1f9 WG |
2483 | case 'H': |
2484 | part_mode = HImode; | |
ec24698e | 2485 | break; |
cd8dc1f9 WG |
2486 | case 'S': |
2487 | part_mode = SImode; | |
2488 | break; | |
2489 | default: | |
2490 | return 0; | |
2491 | } | |
ec24698e | 2492 | |
cd8dc1f9 WG |
2493 | switch (str[2]) |
2494 | { | |
2495 | case 'H': | |
2496 | mode = HImode; | |
2497 | break; | |
2498 | case 'S': | |
2499 | mode = SImode; | |
2500 | break; | |
2501 | case 'D': | |
2502 | mode = DImode; | |
2503 | break; | |
2504 | default: | |
2505 | return 0; | |
2506 | } | |
11598938 | 2507 | |
cd8dc1f9 WG |
2508 | switch (str[3]) |
2509 | { | |
2510 | case '0': | |
2511 | def = 0; | |
2512 | break; | |
2513 | case 'F': | |
2514 | def = -1; | |
2515 | break; | |
ab96de7e AS |
2516 | default: |
2517 | return 0; | |
2518 | } | |
2519 | ||
cd8dc1f9 WG |
2520 | if (GET_MODE_SIZE (mode) <= GET_MODE_SIZE (part_mode)) |
2521 | return 0; | |
2522 | ||
2523 | part = s390_single_part (GEN_INT (value), mode, part_mode, def); | |
2524 | if (part < 0) | |
2525 | return 0; | |
2526 | if (part_goal != -1 && part_goal != part) | |
2527 | return 0; | |
2528 | ||
ab96de7e AS |
2529 | return 1; |
2530 | } | |
2531 | ||
cd8dc1f9 WG |
2532 | |
2533 | /* Returns true if the input parameter VALUE is a float zero. */ | |
2534 | ||
2535 | int | |
2536 | s390_float_const_zero_p (rtx value) | |
2537 | { | |
2538 | return (GET_MODE_CLASS (GET_MODE (value)) == MODE_FLOAT | |
2539 | && value == CONST0_RTX (GET_MODE (value))); | |
2540 | } | |
2541 | ||
ccaed3ba AS |
2542 | /* Implement TARGET_REGISTER_MOVE_COST. */ |
2543 | ||
2544 | static int | |
f954fb25 | 2545 | s390_register_move_cost (machine_mode mode, |
ccaed3ba AS |
2546 | reg_class_t from, reg_class_t to) |
2547 | { | |
f954fb25 AK |
2548 | /* On s390, copy between fprs and gprs is expensive. */ |
2549 | ||
2550 | /* It becomes somewhat faster having ldgr/lgdr. */ | |
2551 | if (TARGET_Z10 && GET_MODE_SIZE (mode) == 8) | |
2552 | { | |
2553 | /* ldgr is single cycle. */ | |
2554 | if (reg_classes_intersect_p (from, GENERAL_REGS) | |
2555 | && reg_classes_intersect_p (to, FP_REGS)) | |
2556 | return 1; | |
2557 | /* lgdr needs 3 cycles. */ | |
2558 | if (reg_classes_intersect_p (to, GENERAL_REGS) | |
2559 | && reg_classes_intersect_p (from, FP_REGS)) | |
2560 | return 3; | |
2561 | } | |
2562 | ||
2563 | /* Otherwise copying is done via memory. */ | |
2564 | if ((reg_classes_intersect_p (from, GENERAL_REGS) | |
2565 | && reg_classes_intersect_p (to, FP_REGS)) | |
2566 | || (reg_classes_intersect_p (from, FP_REGS) | |
2567 | && reg_classes_intersect_p (to, GENERAL_REGS))) | |
ccaed3ba AS |
2568 | return 10; |
2569 | ||
2570 | return 1; | |
2571 | } | |
2572 | ||
2573 | /* Implement TARGET_MEMORY_MOVE_COST. */ | |
2574 | ||
2575 | static int | |
ef4bddc2 | 2576 | s390_memory_move_cost (machine_mode mode ATTRIBUTE_UNUSED, |
ccaed3ba AS |
2577 | reg_class_t rclass ATTRIBUTE_UNUSED, |
2578 | bool in ATTRIBUTE_UNUSED) | |
2579 | { | |
fb1a3f8f | 2580 | return 2; |
ccaed3ba | 2581 | } |
cd8dc1f9 | 2582 | |
ab96de7e AS |
2583 | /* Compute a (partial) cost for rtx X. Return true if the complete |
2584 | cost has been computed, and false if subexpressions should be | |
f4aa3848 AK |
2585 | scanned. In either case, *TOTAL contains the cost result. |
2586 | CODE contains GET_CODE (x), OUTER_CODE contains the code | |
ab96de7e AS |
2587 | of the superexpression of x. */ |
2588 | ||
2589 | static bool | |
68f932c4 RS |
2590 | s390_rtx_costs (rtx x, int code, int outer_code, int opno ATTRIBUTE_UNUSED, |
2591 | int *total, bool speed ATTRIBUTE_UNUSED) | |
3c50106f RH |
2592 | { |
2593 | switch (code) | |
2594 | { | |
2595 | case CONST: | |
3c50106f | 2596 | case CONST_INT: |
3c50106f RH |
2597 | case LABEL_REF: |
2598 | case SYMBOL_REF: | |
2599 | case CONST_DOUBLE: | |
6fa5b390 | 2600 | case MEM: |
3c50106f RH |
2601 | *total = 0; |
2602 | return true; | |
2603 | ||
2604 | case ASHIFT: | |
2605 | case ASHIFTRT: | |
2606 | case LSHIFTRT: | |
017e0eb9 MD |
2607 | case ROTATE: |
2608 | case ROTATERT: | |
3c50106f RH |
2609 | case AND: |
2610 | case IOR: | |
2611 | case XOR: | |
3c50106f RH |
2612 | case NEG: |
2613 | case NOT: | |
2614 | *total = COSTS_N_INSNS (1); | |
017e0eb9 | 2615 | return false; |
3c50106f | 2616 | |
2742a1ed MD |
2617 | case PLUS: |
2618 | case MINUS: | |
2742a1ed MD |
2619 | *total = COSTS_N_INSNS (1); |
2620 | return false; | |
2621 | ||
f4aa3848 | 2622 | case MULT: |
017e0eb9 MD |
2623 | switch (GET_MODE (x)) |
2624 | { | |
2625 | case SImode: | |
2742a1ed | 2626 | { |
017e0eb9 MD |
2627 | rtx left = XEXP (x, 0); |
2628 | rtx right = XEXP (x, 1); | |
2629 | if (GET_CODE (right) == CONST_INT | |
b5c67a49 | 2630 | && CONST_OK_FOR_K (INTVAL (right))) |
017e0eb9 MD |
2631 | *total = s390_cost->mhi; |
2632 | else if (GET_CODE (left) == SIGN_EXTEND) | |
2633 | *total = s390_cost->mh; | |
2634 | else | |
2635 | *total = s390_cost->ms; /* msr, ms, msy */ | |
2636 | break; | |
2637 | } | |
2638 | case DImode: | |
2639 | { | |
2640 | rtx left = XEXP (x, 0); | |
2641 | rtx right = XEXP (x, 1); | |
9602b6a1 | 2642 | if (TARGET_ZARCH) |
017e0eb9 MD |
2643 | { |
2644 | if (GET_CODE (right) == CONST_INT | |
b5c67a49 | 2645 | && CONST_OK_FOR_K (INTVAL (right))) |
017e0eb9 MD |
2646 | *total = s390_cost->mghi; |
2647 | else if (GET_CODE (left) == SIGN_EXTEND) | |
2648 | *total = s390_cost->msgf; | |
2649 | else | |
2650 | *total = s390_cost->msg; /* msgr, msg */ | |
2651 | } | |
2652 | else /* TARGET_31BIT */ | |
2653 | { | |
2654 | if (GET_CODE (left) == SIGN_EXTEND | |
2655 | && GET_CODE (right) == SIGN_EXTEND) | |
2656 | /* mulsidi case: mr, m */ | |
2657 | *total = s390_cost->m; | |
2742a1ed MD |
2658 | else if (GET_CODE (left) == ZERO_EXTEND |
2659 | && GET_CODE (right) == ZERO_EXTEND | |
2660 | && TARGET_CPU_ZARCH) | |
2661 | /* umulsidi case: ml, mlr */ | |
2662 | *total = s390_cost->ml; | |
017e0eb9 MD |
2663 | else |
2664 | /* Complex calculation is required. */ | |
2665 | *total = COSTS_N_INSNS (40); | |
2666 | } | |
2667 | break; | |
2668 | } | |
2669 | case SFmode: | |
2670 | case DFmode: | |
2671 | *total = s390_cost->mult_df; | |
2672 | break; | |
f61a2c7d AK |
2673 | case TFmode: |
2674 | *total = s390_cost->mxbr; | |
2675 | break; | |
017e0eb9 MD |
2676 | default: |
2677 | return false; | |
2678 | } | |
2679 | return false; | |
3c50106f | 2680 | |
d7ecb504 RH |
2681 | case FMA: |
2682 | switch (GET_MODE (x)) | |
2683 | { | |
2684 | case DFmode: | |
2685 | *total = s390_cost->madbr; | |
2686 | break; | |
2687 | case SFmode: | |
2688 | *total = s390_cost->maebr; | |
2689 | break; | |
2690 | default: | |
2691 | return false; | |
2692 | } | |
2693 | /* Negate in the third argument is free: FMSUB. */ | |
2694 | if (GET_CODE (XEXP (x, 2)) == NEG) | |
2695 | { | |
68f932c4 RS |
2696 | *total += (rtx_cost (XEXP (x, 0), FMA, 0, speed) |
2697 | + rtx_cost (XEXP (x, 1), FMA, 1, speed) | |
2698 | + rtx_cost (XEXP (XEXP (x, 2), 0), FMA, 2, speed)); | |
d7ecb504 RH |
2699 | return true; |
2700 | } | |
2701 | return false; | |
2702 | ||
6fa5b390 MD |
2703 | case UDIV: |
2704 | case UMOD: | |
2705 | if (GET_MODE (x) == TImode) /* 128 bit division */ | |
2706 | *total = s390_cost->dlgr; | |
2707 | else if (GET_MODE (x) == DImode) | |
2708 | { | |
2709 | rtx right = XEXP (x, 1); | |
2710 | if (GET_CODE (right) == ZERO_EXTEND) /* 64 by 32 bit division */ | |
2711 | *total = s390_cost->dlr; | |
2712 | else /* 64 by 64 bit division */ | |
2713 | *total = s390_cost->dlgr; | |
2714 | } | |
2715 | else if (GET_MODE (x) == SImode) /* 32 bit division */ | |
2716 | *total = s390_cost->dlr; | |
2717 | return false; | |
2718 | ||
3c50106f | 2719 | case DIV: |
6fa5b390 MD |
2720 | case MOD: |
2721 | if (GET_MODE (x) == DImode) | |
2722 | { | |
2723 | rtx right = XEXP (x, 1); | |
2724 | if (GET_CODE (right) == ZERO_EXTEND) /* 64 by 32 bit division */ | |
9602b6a1 | 2725 | if (TARGET_ZARCH) |
6fa5b390 MD |
2726 | *total = s390_cost->dsgfr; |
2727 | else | |
2728 | *total = s390_cost->dr; | |
2729 | else /* 64 by 64 bit division */ | |
2730 | *total = s390_cost->dsgr; | |
2731 | } | |
2732 | else if (GET_MODE (x) == SImode) /* 32 bit division */ | |
2733 | *total = s390_cost->dlr; | |
2734 | else if (GET_MODE (x) == SFmode) | |
98fd0d70 | 2735 | { |
142cd70f | 2736 | *total = s390_cost->debr; |
98fd0d70 MD |
2737 | } |
2738 | else if (GET_MODE (x) == DFmode) | |
2739 | { | |
142cd70f | 2740 | *total = s390_cost->ddbr; |
98fd0d70 | 2741 | } |
f61a2c7d AK |
2742 | else if (GET_MODE (x) == TFmode) |
2743 | { | |
142cd70f | 2744 | *total = s390_cost->dxbr; |
f61a2c7d | 2745 | } |
017e0eb9 MD |
2746 | return false; |
2747 | ||
2742a1ed MD |
2748 | case SQRT: |
2749 | if (GET_MODE (x) == SFmode) | |
2750 | *total = s390_cost->sqebr; | |
f61a2c7d | 2751 | else if (GET_MODE (x) == DFmode) |
2742a1ed | 2752 | *total = s390_cost->sqdbr; |
f61a2c7d AK |
2753 | else /* TFmode */ |
2754 | *total = s390_cost->sqxbr; | |
2742a1ed MD |
2755 | return false; |
2756 | ||
017e0eb9 | 2757 | case SIGN_EXTEND: |
2742a1ed | 2758 | case ZERO_EXTEND: |
6fa5b390 MD |
2759 | if (outer_code == MULT || outer_code == DIV || outer_code == MOD |
2760 | || outer_code == PLUS || outer_code == MINUS | |
2761 | || outer_code == COMPARE) | |
017e0eb9 MD |
2762 | *total = 0; |
2763 | return false; | |
3c50106f | 2764 | |
6fa5b390 MD |
2765 | case COMPARE: |
2766 | *total = COSTS_N_INSNS (1); | |
2767 | if (GET_CODE (XEXP (x, 0)) == AND | |
2768 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
2769 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT) | |
2770 | { | |
2771 | rtx op0 = XEXP (XEXP (x, 0), 0); | |
2772 | rtx op1 = XEXP (XEXP (x, 0), 1); | |
2773 | rtx op2 = XEXP (x, 1); | |
2774 | ||
2775 | if (memory_operand (op0, GET_MODE (op0)) | |
2776 | && s390_tm_ccmode (op1, op2, 0) != VOIDmode) | |
2777 | return true; | |
2778 | if (register_operand (op0, GET_MODE (op0)) | |
2779 | && s390_tm_ccmode (op1, op2, 1) != VOIDmode) | |
2780 | return true; | |
2781 | } | |
2782 | return false; | |
2783 | ||
3c50106f RH |
2784 | default: |
2785 | return false; | |
2786 | } | |
2787 | } | |
2788 | ||
dea09b1b UW |
2789 | /* Return the cost of an address rtx ADDR. */ |
2790 | ||
dcefdf67 | 2791 | static int |
ef4bddc2 | 2792 | s390_address_cost (rtx addr, machine_mode mode ATTRIBUTE_UNUSED, |
b413068c OE |
2793 | addr_space_t as ATTRIBUTE_UNUSED, |
2794 | bool speed ATTRIBUTE_UNUSED) | |
dea09b1b UW |
2795 | { |
2796 | struct s390_address ad; | |
2797 | if (!s390_decompose_address (addr, &ad)) | |
2798 | return 1000; | |
2799 | ||
2800 | return ad.indx? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (1); | |
2801 | } | |
2802 | ||
fd3cd001 UW |
2803 | /* If OP is a SYMBOL_REF of a thread-local symbol, return its TLS mode, |
2804 | otherwise return 0. */ | |
2805 | ||
2806 | int | |
5d81b82b | 2807 | tls_symbolic_operand (rtx op) |
fd3cd001 | 2808 | { |
fd3cd001 UW |
2809 | if (GET_CODE (op) != SYMBOL_REF) |
2810 | return 0; | |
114278e7 | 2811 | return SYMBOL_REF_TLS_MODEL (op); |
fd3cd001 | 2812 | } |
9db1d521 | 2813 | \f |
c5aa1d12 UW |
2814 | /* Split DImode access register reference REG (on 64-bit) into its constituent |
2815 | low and high parts, and store them into LO and HI. Note that gen_lowpart/ | |
2816 | gen_highpart cannot be used as they assume all registers are word-sized, | |
2817 | while our access registers have only half that size. */ | |
2818 | ||
2819 | void | |
2820 | s390_split_access_reg (rtx reg, rtx *lo, rtx *hi) | |
2821 | { | |
2822 | gcc_assert (TARGET_64BIT); | |
2823 | gcc_assert (ACCESS_REG_P (reg)); | |
2824 | gcc_assert (GET_MODE (reg) == DImode); | |
2825 | gcc_assert (!(REGNO (reg) & 1)); | |
2826 | ||
2827 | *lo = gen_rtx_REG (SImode, REGNO (reg) + 1); | |
2828 | *hi = gen_rtx_REG (SImode, REGNO (reg)); | |
2829 | } | |
9db1d521 | 2830 | |
994fe660 | 2831 | /* Return true if OP contains a symbol reference */ |
9db1d521 | 2832 | |
3ed99cc9 | 2833 | bool |
9c808aad | 2834 | symbolic_reference_mentioned_p (rtx op) |
9db1d521 | 2835 | { |
5d81b82b AS |
2836 | const char *fmt; |
2837 | int i; | |
9db1d521 HP |
2838 | |
2839 | if (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF) | |
2840 | return 1; | |
2841 | ||
2842 | fmt = GET_RTX_FORMAT (GET_CODE (op)); | |
2843 | for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--) | |
2844 | { | |
2845 | if (fmt[i] == 'E') | |
2846 | { | |
5d81b82b | 2847 | int j; |
9db1d521 HP |
2848 | |
2849 | for (j = XVECLEN (op, i) - 1; j >= 0; j--) | |
2850 | if (symbolic_reference_mentioned_p (XVECEXP (op, i, j))) | |
2851 | return 1; | |
2852 | } | |
2853 | ||
2854 | else if (fmt[i] == 'e' && symbolic_reference_mentioned_p (XEXP (op, i))) | |
2855 | return 1; | |
2856 | } | |
2857 | ||
2858 | return 0; | |
2859 | } | |
2860 | ||
fd3cd001 UW |
2861 | /* Return true if OP contains a reference to a thread-local symbol. */ |
2862 | ||
3ed99cc9 | 2863 | bool |
9c808aad | 2864 | tls_symbolic_reference_mentioned_p (rtx op) |
fd3cd001 | 2865 | { |
5d81b82b AS |
2866 | const char *fmt; |
2867 | int i; | |
fd3cd001 UW |
2868 | |
2869 | if (GET_CODE (op) == SYMBOL_REF) | |
2870 | return tls_symbolic_operand (op); | |
2871 | ||
2872 | fmt = GET_RTX_FORMAT (GET_CODE (op)); | |
2873 | for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--) | |
2874 | { | |
2875 | if (fmt[i] == 'E') | |
2876 | { | |
5d81b82b | 2877 | int j; |
fd3cd001 UW |
2878 | |
2879 | for (j = XVECLEN (op, i) - 1; j >= 0; j--) | |
2880 | if (tls_symbolic_reference_mentioned_p (XVECEXP (op, i, j))) | |
3ed99cc9 | 2881 | return true; |
fd3cd001 UW |
2882 | } |
2883 | ||
2884 | else if (fmt[i] == 'e' && tls_symbolic_reference_mentioned_p (XEXP (op, i))) | |
3ed99cc9 | 2885 | return true; |
fd3cd001 UW |
2886 | } |
2887 | ||
3ed99cc9 | 2888 | return false; |
fd3cd001 UW |
2889 | } |
2890 | ||
9db1d521 | 2891 | |
c7453384 EC |
2892 | /* Return true if OP is a legitimate general operand when |
2893 | generating PIC code. It is given that flag_pic is on | |
994fe660 UW |
2894 | and that OP satisfies CONSTANT_P or is a CONST_DOUBLE. */ |
2895 | ||
9db1d521 | 2896 | int |
5d81b82b | 2897 | legitimate_pic_operand_p (rtx op) |
9db1d521 | 2898 | { |
4023fb28 | 2899 | /* Accept all non-symbolic constants. */ |
9db1d521 HP |
2900 | if (!SYMBOLIC_CONST (op)) |
2901 | return 1; | |
2902 | ||
c7453384 | 2903 | /* Reject everything else; must be handled |
fd3cd001 | 2904 | via emit_symbolic_move. */ |
9db1d521 HP |
2905 | return 0; |
2906 | } | |
2907 | ||
994fe660 UW |
2908 | /* Returns true if the constant value OP is a legitimate general operand. |
2909 | It is given that OP satisfies CONSTANT_P or is a CONST_DOUBLE. */ | |
2910 | ||
1a627b35 | 2911 | static bool |
ef4bddc2 | 2912 | s390_legitimate_constant_p (machine_mode mode, rtx op) |
9db1d521 | 2913 | { |
085261c8 AK |
2914 | if (VECTOR_MODE_P (mode) && GET_CODE (op) == CONST_VECTOR) |
2915 | { | |
2916 | if (GET_MODE_SIZE (mode) != 16) | |
2917 | return 0; | |
2918 | ||
2919 | if (!const0_operand (op, mode) | |
2920 | && !s390_contiguous_bitmask_vector_p (op, NULL, NULL) | |
2921 | && !s390_bytemask_vector_p (op, NULL)) | |
2922 | return 0; | |
2923 | } | |
2924 | ||
4023fb28 | 2925 | /* Accept all non-symbolic constants. */ |
9db1d521 HP |
2926 | if (!SYMBOLIC_CONST (op)) |
2927 | return 1; | |
2928 | ||
fd3cd001 | 2929 | /* Accept immediate LARL operands. */ |
1a627b35 | 2930 | if (TARGET_CPU_ZARCH && larl_operand (op, mode)) |
fd3cd001 UW |
2931 | return 1; |
2932 | ||
2933 | /* Thread-local symbols are never legal constants. This is | |
2934 | so that emit_call knows that computing such addresses | |
2935 | might require a function call. */ | |
2936 | if (TLS_SYMBOLIC_CONST (op)) | |
2937 | return 0; | |
2938 | ||
9db1d521 HP |
2939 | /* In the PIC case, symbolic constants must *not* be |
2940 | forced into the literal pool. We accept them here, | |
fd3cd001 | 2941 | so that they will be handled by emit_symbolic_move. */ |
9db1d521 HP |
2942 | if (flag_pic) |
2943 | return 1; | |
2944 | ||
9db1d521 HP |
2945 | /* All remaining non-PIC symbolic constants are |
2946 | forced into the literal pool. */ | |
2947 | return 0; | |
2948 | } | |
2949 | ||
fd3cd001 UW |
2950 | /* Determine if it's legal to put X into the constant pool. This |
2951 | is not possible if X contains the address of a symbol that is | |
2952 | not constant (TLS) or not known at final link time (PIC). */ | |
2953 | ||
2954 | static bool | |
ef4bddc2 | 2955 | s390_cannot_force_const_mem (machine_mode mode, rtx x) |
fd3cd001 UW |
2956 | { |
2957 | switch (GET_CODE (x)) | |
2958 | { | |
2959 | case CONST_INT: | |
2960 | case CONST_DOUBLE: | |
085261c8 | 2961 | case CONST_VECTOR: |
fd3cd001 UW |
2962 | /* Accept all non-symbolic constants. */ |
2963 | return false; | |
2964 | ||
2965 | case LABEL_REF: | |
2966 | /* Labels are OK iff we are non-PIC. */ | |
2967 | return flag_pic != 0; | |
2968 | ||
2969 | case SYMBOL_REF: | |
2970 | /* 'Naked' TLS symbol references are never OK, | |
2971 | non-TLS symbols are OK iff we are non-PIC. */ | |
2972 | if (tls_symbolic_operand (x)) | |
2973 | return true; | |
2974 | else | |
2975 | return flag_pic != 0; | |
2976 | ||
2977 | case CONST: | |
fbbf66e7 | 2978 | return s390_cannot_force_const_mem (mode, XEXP (x, 0)); |
fd3cd001 UW |
2979 | case PLUS: |
2980 | case MINUS: | |
fbbf66e7 RS |
2981 | return s390_cannot_force_const_mem (mode, XEXP (x, 0)) |
2982 | || s390_cannot_force_const_mem (mode, XEXP (x, 1)); | |
fd3cd001 UW |
2983 | |
2984 | case UNSPEC: | |
2985 | switch (XINT (x, 1)) | |
2986 | { | |
2987 | /* Only lt-relative or GOT-relative UNSPECs are OK. */ | |
fd7643fb UW |
2988 | case UNSPEC_LTREL_OFFSET: |
2989 | case UNSPEC_GOT: | |
2990 | case UNSPEC_GOTOFF: | |
2991 | case UNSPEC_PLTOFF: | |
fd3cd001 UW |
2992 | case UNSPEC_TLSGD: |
2993 | case UNSPEC_TLSLDM: | |
2994 | case UNSPEC_NTPOFF: | |
2995 | case UNSPEC_DTPOFF: | |
2996 | case UNSPEC_GOTNTPOFF: | |
2997 | case UNSPEC_INDNTPOFF: | |
2998 | return false; | |
2999 | ||
9bb86f41 UW |
3000 | /* If the literal pool shares the code section, be put |
3001 | execute template placeholders into the pool as well. */ | |
3002 | case UNSPEC_INSN: | |
3003 | return TARGET_CPU_ZARCH; | |
3004 | ||
fd3cd001 UW |
3005 | default: |
3006 | return true; | |
3007 | } | |
3008 | break; | |
3009 | ||
3010 | default: | |
8d933e31 | 3011 | gcc_unreachable (); |
fd3cd001 UW |
3012 | } |
3013 | } | |
3014 | ||
4023fb28 | 3015 | /* Returns true if the constant value OP is a legitimate general |
c7453384 | 3016 | operand during and after reload. The difference to |
4023fb28 UW |
3017 | legitimate_constant_p is that this function will not accept |
3018 | a constant that would need to be forced to the literal pool | |
65b1d8ea AK |
3019 | before it can be used as operand. |
3020 | This function accepts all constants which can be loaded directly | |
3021 | into a GPR. */ | |
4023fb28 | 3022 | |
3ed99cc9 | 3023 | bool |
5d81b82b | 3024 | legitimate_reload_constant_p (rtx op) |
4023fb28 | 3025 | { |
d3632d41 | 3026 | /* Accept la(y) operands. */ |
c7453384 | 3027 | if (GET_CODE (op) == CONST_INT |
d3632d41 | 3028 | && DISP_IN_RANGE (INTVAL (op))) |
3ed99cc9 | 3029 | return true; |
d3632d41 | 3030 | |
ec24698e | 3031 | /* Accept l(g)hi/l(g)fi operands. */ |
4023fb28 | 3032 | if (GET_CODE (op) == CONST_INT |
ec24698e | 3033 | && (CONST_OK_FOR_K (INTVAL (op)) || CONST_OK_FOR_Os (INTVAL (op)))) |
3ed99cc9 | 3034 | return true; |
4023fb28 UW |
3035 | |
3036 | /* Accept lliXX operands. */ | |
9e8327e3 | 3037 | if (TARGET_ZARCH |
11598938 UW |
3038 | && GET_CODE (op) == CONST_INT |
3039 | && trunc_int_for_mode (INTVAL (op), word_mode) == INTVAL (op) | |
3040 | && s390_single_part (op, word_mode, HImode, 0) >= 0) | |
3ed99cc9 | 3041 | return true; |
4023fb28 | 3042 | |
ec24698e UW |
3043 | if (TARGET_EXTIMM |
3044 | && GET_CODE (op) == CONST_INT | |
3045 | && trunc_int_for_mode (INTVAL (op), word_mode) == INTVAL (op) | |
3046 | && s390_single_part (op, word_mode, SImode, 0) >= 0) | |
3047 | return true; | |
3048 | ||
4023fb28 | 3049 | /* Accept larl operands. */ |
9e8327e3 | 3050 | if (TARGET_CPU_ZARCH |
4023fb28 | 3051 | && larl_operand (op, VOIDmode)) |
3ed99cc9 | 3052 | return true; |
4023fb28 | 3053 | |
45e5214c UW |
3054 | /* Accept floating-point zero operands that fit into a single GPR. */ |
3055 | if (GET_CODE (op) == CONST_DOUBLE | |
3056 | && s390_float_const_zero_p (op) | |
3057 | && GET_MODE_SIZE (GET_MODE (op)) <= UNITS_PER_WORD) | |
3058 | return true; | |
3059 | ||
11598938 UW |
3060 | /* Accept double-word operands that can be split. */ |
3061 | if (GET_CODE (op) == CONST_INT | |
3062 | && trunc_int_for_mode (INTVAL (op), word_mode) != INTVAL (op)) | |
3063 | { | |
ef4bddc2 | 3064 | machine_mode dword_mode = word_mode == SImode ? DImode : TImode; |
11598938 UW |
3065 | rtx hi = operand_subword (op, 0, 0, dword_mode); |
3066 | rtx lo = operand_subword (op, 1, 0, dword_mode); | |
3067 | return legitimate_reload_constant_p (hi) | |
3068 | && legitimate_reload_constant_p (lo); | |
3069 | } | |
3070 | ||
4023fb28 | 3071 | /* Everything else cannot be handled without reload. */ |
3ed99cc9 | 3072 | return false; |
4023fb28 UW |
3073 | } |
3074 | ||
65b1d8ea AK |
3075 | /* Returns true if the constant value OP is a legitimate fp operand |
3076 | during and after reload. | |
3077 | This function accepts all constants which can be loaded directly | |
3078 | into an FPR. */ | |
3079 | ||
3080 | static bool | |
3081 | legitimate_reload_fp_constant_p (rtx op) | |
3082 | { | |
3083 | /* Accept floating-point zero operands if the load zero instruction | |
22ac2c2f AK |
3084 | can be used. Prior to z196 the load fp zero instruction caused a |
3085 | performance penalty if the result is used as BFP number. */ | |
65b1d8ea AK |
3086 | if (TARGET_Z196 |
3087 | && GET_CODE (op) == CONST_DOUBLE | |
3088 | && s390_float_const_zero_p (op)) | |
3089 | return true; | |
3090 | ||
3091 | return false; | |
3092 | } | |
3093 | ||
085261c8 AK |
3094 | /* Returns true if the constant value OP is a legitimate vector operand |
3095 | during and after reload. | |
3096 | This function accepts all constants which can be loaded directly | |
3097 | into an VR. */ | |
3098 | ||
3099 | static bool | |
3100 | legitimate_reload_vector_constant_p (rtx op) | |
3101 | { | |
3102 | /* FIXME: Support constant vectors with all the same 16 bit unsigned | |
3103 | operands. These can be loaded with vrepi. */ | |
3104 | ||
3105 | if (TARGET_VX && GET_MODE_SIZE (GET_MODE (op)) == 16 | |
3106 | && (const0_operand (op, GET_MODE (op)) | |
3107 | || constm1_operand (op, GET_MODE (op)) | |
3108 | || s390_contiguous_bitmask_vector_p (op, NULL, NULL) | |
3109 | || s390_bytemask_vector_p (op, NULL))) | |
3110 | return true; | |
3111 | ||
3112 | return false; | |
3113 | } | |
3114 | ||
0a2aaacc | 3115 | /* Given an rtx OP being reloaded into a reg required to be in class RCLASS, |
4023fb28 UW |
3116 | return the class of reg to actually use. */ |
3117 | ||
5df97412 AS |
3118 | static reg_class_t |
3119 | s390_preferred_reload_class (rtx op, reg_class_t rclass) | |
4023fb28 | 3120 | { |
4023fb28 UW |
3121 | switch (GET_CODE (op)) |
3122 | { | |
45e5214c UW |
3123 | /* Constants we cannot reload into general registers |
3124 | must be forced into the literal pool. */ | |
085261c8 | 3125 | case CONST_VECTOR: |
4023fb28 UW |
3126 | case CONST_DOUBLE: |
3127 | case CONST_INT: | |
45e5214c UW |
3128 | if (reg_class_subset_p (GENERAL_REGS, rclass) |
3129 | && legitimate_reload_constant_p (op)) | |
3130 | return GENERAL_REGS; | |
3131 | else if (reg_class_subset_p (ADDR_REGS, rclass) | |
3132 | && legitimate_reload_constant_p (op)) | |
3133 | return ADDR_REGS; | |
65b1d8ea AK |
3134 | else if (reg_class_subset_p (FP_REGS, rclass) |
3135 | && legitimate_reload_fp_constant_p (op)) | |
3136 | return FP_REGS; | |
085261c8 AK |
3137 | else if (reg_class_subset_p (VEC_REGS, rclass) |
3138 | && legitimate_reload_vector_constant_p (op)) | |
3139 | return VEC_REGS; | |
3140 | ||
65b1d8ea | 3141 | return NO_REGS; |
4023fb28 UW |
3142 | |
3143 | /* If a symbolic constant or a PLUS is reloaded, | |
14b3e8ef UW |
3144 | it is most likely being used as an address, so |
3145 | prefer ADDR_REGS. If 'class' is not a superset | |
3146 | of ADDR_REGS, e.g. FP_REGS, reject this reload. */ | |
1abcd5eb | 3147 | case CONST: |
cb4b6d17 AK |
3148 | /* Symrefs cannot be pushed into the literal pool with -fPIC |
3149 | so we *MUST NOT* return NO_REGS for these cases | |
3150 | (s390_cannot_force_const_mem will return true). | |
3151 | ||
3152 | On the other hand we MUST return NO_REGS for symrefs with | |
3153 | invalid addend which might have been pushed to the literal | |
3154 | pool (no -fPIC). Usually we would expect them to be | |
3155 | handled via secondary reload but this does not happen if | |
3156 | they are used as literal pool slot replacement in reload | |
3157 | inheritance (see emit_input_reload_insns). */ | |
1abcd5eb AK |
3158 | if (TARGET_CPU_ZARCH |
3159 | && GET_CODE (XEXP (op, 0)) == PLUS | |
3160 | && GET_CODE (XEXP (XEXP(op, 0), 0)) == SYMBOL_REF | |
3161 | && GET_CODE (XEXP (XEXP(op, 0), 1)) == CONST_INT) | |
3162 | { | |
cb4b6d17 | 3163 | if (flag_pic && reg_class_subset_p (ADDR_REGS, rclass)) |
1abcd5eb AK |
3164 | return ADDR_REGS; |
3165 | else | |
3166 | return NO_REGS; | |
3167 | } | |
3168 | /* fallthrough */ | |
4023fb28 UW |
3169 | case LABEL_REF: |
3170 | case SYMBOL_REF: | |
212aa74f AK |
3171 | if (!legitimate_reload_constant_p (op)) |
3172 | return NO_REGS; | |
3173 | /* fallthrough */ | |
3174 | case PLUS: | |
3175 | /* load address will be used. */ | |
0a2aaacc | 3176 | if (reg_class_subset_p (ADDR_REGS, rclass)) |
212aa74f | 3177 | return ADDR_REGS; |
14b3e8ef UW |
3178 | else |
3179 | return NO_REGS; | |
4023fb28 UW |
3180 | |
3181 | default: | |
3182 | break; | |
3183 | } | |
3184 | ||
0a2aaacc | 3185 | return rclass; |
4023fb28 | 3186 | } |
9db1d521 | 3187 | |
963fc8d0 AK |
3188 | /* Return true if ADDR is SYMBOL_REF + addend with addend being a |
3189 | multiple of ALIGNMENT and the SYMBOL_REF being naturally | |
3190 | aligned. */ | |
3191 | ||
3192 | bool | |
3193 | s390_check_symref_alignment (rtx addr, HOST_WIDE_INT alignment) | |
3194 | { | |
3195 | HOST_WIDE_INT addend; | |
3196 | rtx symref; | |
3197 | ||
0ff4390d AK |
3198 | if (!s390_loadrelative_operand_p (addr, &symref, &addend)) |
3199 | return false; | |
98412b77 | 3200 | |
0ff4390d | 3201 | if (addend & (alignment - 1)) |
963fc8d0 AK |
3202 | return false; |
3203 | ||
0ff4390d AK |
3204 | if (GET_CODE (symref) == SYMBOL_REF |
3205 | && !SYMBOL_REF_NOT_NATURALLY_ALIGNED_P (symref)) | |
3206 | return true; | |
3207 | ||
3208 | if (GET_CODE (symref) == UNSPEC | |
3209 | && alignment <= UNITS_PER_LONG) | |
3210 | return true; | |
3211 | ||
3212 | return false; | |
963fc8d0 AK |
3213 | } |
3214 | ||
3215 | /* ADDR is moved into REG using larl. If ADDR isn't a valid larl | |
3216 | operand SCRATCH is used to reload the even part of the address and | |
3217 | adding one. */ | |
3218 | ||
3219 | void | |
3220 | s390_reload_larl_operand (rtx reg, rtx addr, rtx scratch) | |
3221 | { | |
3222 | HOST_WIDE_INT addend; | |
3223 | rtx symref; | |
3224 | ||
0ff4390d | 3225 | if (!s390_loadrelative_operand_p (addr, &symref, &addend)) |
963fc8d0 AK |
3226 | gcc_unreachable (); |
3227 | ||
3228 | if (!(addend & 1)) | |
3229 | /* Easy case. The addend is even so larl will do fine. */ | |
3230 | emit_move_insn (reg, addr); | |
3231 | else | |
3232 | { | |
3233 | /* We can leave the scratch register untouched if the target | |
3234 | register is a valid base register. */ | |
3235 | if (REGNO (reg) < FIRST_PSEUDO_REGISTER | |
3236 | && REGNO_REG_CLASS (REGNO (reg)) == ADDR_REGS) | |
3237 | scratch = reg; | |
3238 | ||
3239 | gcc_assert (REGNO (scratch) < FIRST_PSEUDO_REGISTER); | |
3240 | gcc_assert (REGNO_REG_CLASS (REGNO (scratch)) == ADDR_REGS); | |
3241 | ||
3242 | if (addend != 1) | |
3243 | emit_move_insn (scratch, | |
3244 | gen_rtx_CONST (Pmode, | |
3245 | gen_rtx_PLUS (Pmode, symref, | |
3246 | GEN_INT (addend - 1)))); | |
3247 | else | |
3248 | emit_move_insn (scratch, symref); | |
3249 | ||
3250 | /* Increment the address using la in order to avoid clobbering cc. */ | |
1abcd5eb | 3251 | s390_load_address (reg, gen_rtx_PLUS (Pmode, scratch, const1_rtx)); |
963fc8d0 AK |
3252 | } |
3253 | } | |
3254 | ||
3255 | /* Generate what is necessary to move between REG and MEM using | |
3256 | SCRATCH. The direction is given by TOMEM. */ | |
3257 | ||
3258 | void | |
3259 | s390_reload_symref_address (rtx reg, rtx mem, rtx scratch, bool tomem) | |
3260 | { | |
3261 | /* Reload might have pulled a constant out of the literal pool. | |
3262 | Force it back in. */ | |
3263 | if (CONST_INT_P (mem) || GET_CODE (mem) == CONST_DOUBLE | |
085261c8 | 3264 | || GET_CODE (mem) == CONST_VECTOR |
963fc8d0 AK |
3265 | || GET_CODE (mem) == CONST) |
3266 | mem = force_const_mem (GET_MODE (reg), mem); | |
3267 | ||
3268 | gcc_assert (MEM_P (mem)); | |
3269 | ||
3270 | /* For a load from memory we can leave the scratch register | |
3271 | untouched if the target register is a valid base register. */ | |
3272 | if (!tomem | |
3273 | && REGNO (reg) < FIRST_PSEUDO_REGISTER | |
3274 | && REGNO_REG_CLASS (REGNO (reg)) == ADDR_REGS | |
3275 | && GET_MODE (reg) == GET_MODE (scratch)) | |
3276 | scratch = reg; | |
3277 | ||
3278 | /* Load address into scratch register. Since we can't have a | |
3279 | secondary reload for a secondary reload we have to cover the case | |
3280 | where larl would need a secondary reload here as well. */ | |
3281 | s390_reload_larl_operand (scratch, XEXP (mem, 0), scratch); | |
3282 | ||
3283 | /* Now we can use a standard load/store to do the move. */ | |
3284 | if (tomem) | |
3285 | emit_move_insn (replace_equiv_address (mem, scratch), reg); | |
3286 | else | |
3287 | emit_move_insn (reg, replace_equiv_address (mem, scratch)); | |
3288 | } | |
3289 | ||
833cd70a | 3290 | /* Inform reload about cases where moving X with a mode MODE to a register in |
0a2aaacc | 3291 | RCLASS requires an extra scratch or immediate register. Return the class |
833cd70a | 3292 | needed for the immediate register. */ |
f61a2c7d | 3293 | |
a87cf97e JR |
3294 | static reg_class_t |
3295 | s390_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i, | |
ef4bddc2 | 3296 | machine_mode mode, secondary_reload_info *sri) |
833cd70a | 3297 | { |
a87cf97e JR |
3298 | enum reg_class rclass = (enum reg_class) rclass_i; |
3299 | ||
833cd70a | 3300 | /* Intermediate register needed. */ |
0a2aaacc | 3301 | if (reg_classes_intersect_p (CC_REGS, rclass)) |
9dc62c00 AK |
3302 | return GENERAL_REGS; |
3303 | ||
085261c8 AK |
3304 | if (TARGET_VX) |
3305 | { | |
3306 | /* The vst/vl vector move instructions allow only for short | |
3307 | displacements. */ | |
3308 | if (MEM_P (x) | |
3309 | && GET_CODE (XEXP (x, 0)) == PLUS | |
3310 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT | |
3311 | && !SHORT_DISP_IN_RANGE(INTVAL (XEXP (XEXP (x, 0), 1))) | |
3312 | && reg_class_subset_p (rclass, VEC_REGS) | |
3313 | && (!reg_class_subset_p (rclass, FP_REGS) | |
3314 | || (GET_MODE_SIZE (mode) > 8 | |
3315 | && s390_class_max_nregs (FP_REGS, mode) == 1))) | |
3316 | { | |
3317 | if (in_p) | |
3318 | sri->icode = (TARGET_64BIT ? | |
3319 | CODE_FOR_reloaddi_la_in : | |
3320 | CODE_FOR_reloadsi_la_in); | |
3321 | else | |
3322 | sri->icode = (TARGET_64BIT ? | |
3323 | CODE_FOR_reloaddi_la_out : | |
3324 | CODE_FOR_reloadsi_la_out); | |
3325 | } | |
3326 | } | |
3327 | ||
963fc8d0 AK |
3328 | if (TARGET_Z10) |
3329 | { | |
212aa74f AK |
3330 | HOST_WIDE_INT offset; |
3331 | rtx symref; | |
3332 | ||
963fc8d0 AK |
3333 | /* On z10 several optimizer steps may generate larl operands with |
3334 | an odd addend. */ | |
3335 | if (in_p | |
0ff4390d | 3336 | && s390_loadrelative_operand_p (x, &symref, &offset) |
963fc8d0 | 3337 | && mode == Pmode |
212aa74f AK |
3338 | && !SYMBOL_REF_ALIGN1_P (symref) |
3339 | && (offset & 1) == 1) | |
963fc8d0 AK |
3340 | sri->icode = ((mode == DImode) ? CODE_FOR_reloaddi_larl_odd_addend_z10 |
3341 | : CODE_FOR_reloadsi_larl_odd_addend_z10); | |
3342 | ||
05702110 AK |
3343 | /* Handle all the (mem (symref)) accesses we cannot use the z10 |
3344 | instructions for. */ | |
963fc8d0 | 3345 | if (MEM_P (x) |
0ff4390d | 3346 | && s390_loadrelative_operand_p (XEXP (x, 0), NULL, NULL) |
05702110 AK |
3347 | && (mode == QImode |
3348 | || !reg_classes_intersect_p (GENERAL_REGS, rclass) | |
3349 | || GET_MODE_SIZE (mode) > UNITS_PER_WORD | |
3350 | || !s390_check_symref_alignment (XEXP (x, 0), | |
3351 | GET_MODE_SIZE (mode)))) | |
963fc8d0 AK |
3352 | { |
3353 | #define __SECONDARY_RELOAD_CASE(M,m) \ | |
3354 | case M##mode: \ | |
3355 | if (TARGET_64BIT) \ | |
3356 | sri->icode = in_p ? CODE_FOR_reload##m##di_toreg_z10 : \ | |
3357 | CODE_FOR_reload##m##di_tomem_z10; \ | |
3358 | else \ | |
3359 | sri->icode = in_p ? CODE_FOR_reload##m##si_toreg_z10 : \ | |
3360 | CODE_FOR_reload##m##si_tomem_z10; \ | |
3361 | break; | |
3362 | ||
3363 | switch (GET_MODE (x)) | |
3364 | { | |
3365 | __SECONDARY_RELOAD_CASE (QI, qi); | |
3366 | __SECONDARY_RELOAD_CASE (HI, hi); | |
3367 | __SECONDARY_RELOAD_CASE (SI, si); | |
3368 | __SECONDARY_RELOAD_CASE (DI, di); | |
3369 | __SECONDARY_RELOAD_CASE (TI, ti); | |
3370 | __SECONDARY_RELOAD_CASE (SF, sf); | |
3371 | __SECONDARY_RELOAD_CASE (DF, df); | |
3372 | __SECONDARY_RELOAD_CASE (TF, tf); | |
3373 | __SECONDARY_RELOAD_CASE (SD, sd); | |
3374 | __SECONDARY_RELOAD_CASE (DD, dd); | |
3375 | __SECONDARY_RELOAD_CASE (TD, td); | |
085261c8 AK |
3376 | __SECONDARY_RELOAD_CASE (V1QI, v1qi); |
3377 | __SECONDARY_RELOAD_CASE (V2QI, v2qi); | |
3378 | __SECONDARY_RELOAD_CASE (V4QI, v4qi); | |
3379 | __SECONDARY_RELOAD_CASE (V8QI, v8qi); | |
3380 | __SECONDARY_RELOAD_CASE (V16QI, v16qi); | |
3381 | __SECONDARY_RELOAD_CASE (V1HI, v1hi); | |
3382 | __SECONDARY_RELOAD_CASE (V2HI, v2hi); | |
3383 | __SECONDARY_RELOAD_CASE (V4HI, v4hi); | |
3384 | __SECONDARY_RELOAD_CASE (V8HI, v8hi); | |
3385 | __SECONDARY_RELOAD_CASE (V1SI, v1si); | |
3386 | __SECONDARY_RELOAD_CASE (V2SI, v2si); | |
3387 | __SECONDARY_RELOAD_CASE (V4SI, v4si); | |
3388 | __SECONDARY_RELOAD_CASE (V1DI, v1di); | |
3389 | __SECONDARY_RELOAD_CASE (V2DI, v2di); | |
3390 | __SECONDARY_RELOAD_CASE (V1TI, v1ti); | |
3391 | __SECONDARY_RELOAD_CASE (V1SF, v1sf); | |
3392 | __SECONDARY_RELOAD_CASE (V2SF, v2sf); | |
3393 | __SECONDARY_RELOAD_CASE (V4SF, v4sf); | |
3394 | __SECONDARY_RELOAD_CASE (V1DF, v1df); | |
3395 | __SECONDARY_RELOAD_CASE (V2DF, v2df); | |
3396 | __SECONDARY_RELOAD_CASE (V1TF, v1tf); | |
963fc8d0 AK |
3397 | default: |
3398 | gcc_unreachable (); | |
3399 | } | |
3400 | #undef __SECONDARY_RELOAD_CASE | |
3401 | } | |
3402 | } | |
3403 | ||
833cd70a AK |
3404 | /* We need a scratch register when loading a PLUS expression which |
3405 | is not a legitimate operand of the LOAD ADDRESS instruction. */ | |
3597e113 VM |
3406 | /* LRA can deal with transformation of plus op very well -- so we |
3407 | don't need to prompt LRA in this case. */ | |
3408 | if (! lra_in_progress && in_p && s390_plus_operand (x, mode)) | |
833cd70a AK |
3409 | sri->icode = (TARGET_64BIT ? |
3410 | CODE_FOR_reloaddi_plus : CODE_FOR_reloadsi_plus); | |
3411 | ||
7fa7289d | 3412 | /* Performing a multiword move from or to memory we have to make sure the |
833cd70a AK |
3413 | second chunk in memory is addressable without causing a displacement |
3414 | overflow. If that would be the case we calculate the address in | |
3415 | a scratch register. */ | |
3416 | if (MEM_P (x) | |
3417 | && GET_CODE (XEXP (x, 0)) == PLUS | |
3418 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT | |
3419 | && !DISP_IN_RANGE (INTVAL (XEXP (XEXP (x, 0), 1)) | |
0ca89db7 | 3420 | + GET_MODE_SIZE (mode) - 1)) |
833cd70a | 3421 | { |
7fa7289d | 3422 | /* For GENERAL_REGS a displacement overflow is no problem if occurring |
833cd70a AK |
3423 | in a s_operand address since we may fallback to lm/stm. So we only |
3424 | have to care about overflows in the b+i+d case. */ | |
0a2aaacc | 3425 | if ((reg_classes_intersect_p (GENERAL_REGS, rclass) |
833cd70a AK |
3426 | && s390_class_max_nregs (GENERAL_REGS, mode) > 1 |
3427 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS) | |
3428 | /* For FP_REGS no lm/stm is available so this check is triggered | |
3429 | for displacement overflows in b+i+d and b+d like addresses. */ | |
0a2aaacc | 3430 | || (reg_classes_intersect_p (FP_REGS, rclass) |
833cd70a AK |
3431 | && s390_class_max_nregs (FP_REGS, mode) > 1)) |
3432 | { | |
3433 | if (in_p) | |
3434 | sri->icode = (TARGET_64BIT ? | |
085261c8 AK |
3435 | CODE_FOR_reloaddi_la_in : |
3436 | CODE_FOR_reloadsi_la_in); | |
833cd70a AK |
3437 | else |
3438 | sri->icode = (TARGET_64BIT ? | |
085261c8 AK |
3439 | CODE_FOR_reloaddi_la_out : |
3440 | CODE_FOR_reloadsi_la_out); | |
833cd70a AK |
3441 | } |
3442 | } | |
9dc62c00 | 3443 | |
1f9e1fc6 AK |
3444 | /* A scratch address register is needed when a symbolic constant is |
3445 | copied to r0 compiling with -fPIC. In other cases the target | |
3446 | register might be used as temporary (see legitimize_pic_address). */ | |
0a2aaacc | 3447 | if (in_p && SYMBOLIC_CONST (x) && flag_pic == 2 && rclass != ADDR_REGS) |
1f9e1fc6 AK |
3448 | sri->icode = (TARGET_64BIT ? |
3449 | CODE_FOR_reloaddi_PIC_addr : | |
3450 | CODE_FOR_reloadsi_PIC_addr); | |
3451 | ||
833cd70a | 3452 | /* Either scratch or no register needed. */ |
dc65c307 UW |
3453 | return NO_REGS; |
3454 | } | |
3455 | ||
f3e9edff UW |
3456 | /* Generate code to load SRC, which is PLUS that is not a |
3457 | legitimate operand for the LA instruction, into TARGET. | |
3458 | SCRATCH may be used as scratch register. */ | |
3459 | ||
3460 | void | |
5d81b82b AS |
3461 | s390_expand_plus_operand (rtx target, rtx src, |
3462 | rtx scratch) | |
f3e9edff | 3463 | { |
7974fe63 | 3464 | rtx sum1, sum2; |
b808c04c | 3465 | struct s390_address ad; |
6a4e49c1 | 3466 | |
6a4e49c1 | 3467 | /* src must be a PLUS; get its two operands. */ |
8d933e31 AS |
3468 | gcc_assert (GET_CODE (src) == PLUS); |
3469 | gcc_assert (GET_MODE (src) == Pmode); | |
f3e9edff | 3470 | |
7c82a1ed UW |
3471 | /* Check if any of the two operands is already scheduled |
3472 | for replacement by reload. This can happen e.g. when | |
3473 | float registers occur in an address. */ | |
3474 | sum1 = find_replacement (&XEXP (src, 0)); | |
3475 | sum2 = find_replacement (&XEXP (src, 1)); | |
ccfc6cc8 | 3476 | src = gen_rtx_PLUS (Pmode, sum1, sum2); |
ccfc6cc8 | 3477 | |
7974fe63 UW |
3478 | /* If the address is already strictly valid, there's nothing to do. */ |
3479 | if (!s390_decompose_address (src, &ad) | |
93fa8428 AK |
3480 | || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base))) |
3481 | || (ad.indx && !REGNO_OK_FOR_INDEX_P (REGNO (ad.indx)))) | |
f3e9edff | 3482 | { |
7974fe63 UW |
3483 | /* Otherwise, one of the operands cannot be an address register; |
3484 | we reload its value into the scratch register. */ | |
3485 | if (true_regnum (sum1) < 1 || true_regnum (sum1) > 15) | |
3486 | { | |
3487 | emit_move_insn (scratch, sum1); | |
3488 | sum1 = scratch; | |
3489 | } | |
3490 | if (true_regnum (sum2) < 1 || true_regnum (sum2) > 15) | |
3491 | { | |
3492 | emit_move_insn (scratch, sum2); | |
3493 | sum2 = scratch; | |
3494 | } | |
f3e9edff | 3495 | |
7974fe63 UW |
3496 | /* According to the way these invalid addresses are generated |
3497 | in reload.c, it should never happen (at least on s390) that | |
3498 | *neither* of the PLUS components, after find_replacements | |
3499 | was applied, is an address register. */ | |
3500 | if (sum1 == scratch && sum2 == scratch) | |
3501 | { | |
3502 | debug_rtx (src); | |
8d933e31 | 3503 | gcc_unreachable (); |
7974fe63 | 3504 | } |
f3e9edff | 3505 | |
7974fe63 | 3506 | src = gen_rtx_PLUS (Pmode, sum1, sum2); |
f3e9edff UW |
3507 | } |
3508 | ||
3509 | /* Emit the LOAD ADDRESS pattern. Note that reload of PLUS | |
3510 | is only ever performed on addresses, so we can mark the | |
3511 | sum as legitimate for LA in any case. */ | |
a41c6c53 | 3512 | s390_load_address (target, src); |
f3e9edff UW |
3513 | } |
3514 | ||
3515 | ||
3ed99cc9 | 3516 | /* Return true if ADDR is a valid memory address. |
ab96de7e | 3517 | STRICT specifies whether strict register checking applies. */ |
9db1d521 | 3518 | |
c6c3dba9 | 3519 | static bool |
ef4bddc2 | 3520 | s390_legitimate_address_p (machine_mode mode, rtx addr, bool strict) |
9db1d521 | 3521 | { |
ab96de7e | 3522 | struct s390_address ad; |
963fc8d0 AK |
3523 | |
3524 | if (TARGET_Z10 | |
3525 | && larl_operand (addr, VOIDmode) | |
3526 | && (mode == VOIDmode | |
3527 | || s390_check_symref_alignment (addr, GET_MODE_SIZE (mode)))) | |
3528 | return true; | |
3529 | ||
ab96de7e | 3530 | if (!s390_decompose_address (addr, &ad)) |
3ed99cc9 | 3531 | return false; |
b808c04c UW |
3532 | |
3533 | if (strict) | |
3534 | { | |
93fa8428 | 3535 | if (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base))) |
3ed99cc9 | 3536 | return false; |
93fa8428 AK |
3537 | |
3538 | if (ad.indx && !REGNO_OK_FOR_INDEX_P (REGNO (ad.indx))) | |
3ed99cc9 | 3539 | return false; |
b808c04c UW |
3540 | } |
3541 | else | |
3542 | { | |
f4aa3848 | 3543 | if (ad.base |
93fa8428 AK |
3544 | && !(REGNO (ad.base) >= FIRST_PSEUDO_REGISTER |
3545 | || REGNO_REG_CLASS (REGNO (ad.base)) == ADDR_REGS)) | |
3ed99cc9 | 3546 | return false; |
f4aa3848 | 3547 | |
93fa8428 AK |
3548 | if (ad.indx |
3549 | && !(REGNO (ad.indx) >= FIRST_PSEUDO_REGISTER | |
3550 | || REGNO_REG_CLASS (REGNO (ad.indx)) == ADDR_REGS)) | |
3551 | return false; | |
b808c04c | 3552 | } |
3ed99cc9 | 3553 | return true; |
9db1d521 HP |
3554 | } |
3555 | ||
3ed99cc9 | 3556 | /* Return true if OP is a valid operand for the LA instruction. |
ba956982 UW |
3557 | In 31-bit, we need to prove that the result is used as an |
3558 | address, as LA performs only a 31-bit addition. */ | |
3559 | ||
3ed99cc9 | 3560 | bool |
5d81b82b | 3561 | legitimate_la_operand_p (rtx op) |
ba956982 UW |
3562 | { |
3563 | struct s390_address addr; | |
b808c04c | 3564 | if (!s390_decompose_address (op, &addr)) |
3ed99cc9 | 3565 | return false; |
ba956982 | 3566 | |
3ed99cc9 | 3567 | return (TARGET_64BIT || addr.pointer); |
f3e9edff | 3568 | } |
ba956982 | 3569 | |
3ed99cc9 | 3570 | /* Return true if it is valid *and* preferable to use LA to |
e1d5ee28 | 3571 | compute the sum of OP1 and OP2. */ |
c7453384 | 3572 | |
3ed99cc9 | 3573 | bool |
e1d5ee28 | 3574 | preferred_la_operand_p (rtx op1, rtx op2) |
100c7420 UW |
3575 | { |
3576 | struct s390_address addr; | |
e1d5ee28 UW |
3577 | |
3578 | if (op2 != const0_rtx) | |
3579 | op1 = gen_rtx_PLUS (Pmode, op1, op2); | |
3580 | ||
3581 | if (!s390_decompose_address (op1, &addr)) | |
3ed99cc9 | 3582 | return false; |
93fa8428 | 3583 | if (addr.base && !REGNO_OK_FOR_BASE_P (REGNO (addr.base))) |
3ed99cc9 | 3584 | return false; |
93fa8428 | 3585 | if (addr.indx && !REGNO_OK_FOR_INDEX_P (REGNO (addr.indx))) |
3ed99cc9 | 3586 | return false; |
100c7420 | 3587 | |
65b1d8ea | 3588 | /* Avoid LA instructions with index register on z196; it is |
22ac2c2f AK |
3589 | preferable to use regular add instructions when possible. |
3590 | Starting with zEC12 the la with index register is "uncracked" | |
3591 | again. */ | |
65b1d8ea AK |
3592 | if (addr.indx && s390_tune == PROCESSOR_2817_Z196) |
3593 | return false; | |
3594 | ||
100c7420 | 3595 | if (!TARGET_64BIT && !addr.pointer) |
3ed99cc9 | 3596 | return false; |
100c7420 UW |
3597 | |
3598 | if (addr.pointer) | |
3ed99cc9 | 3599 | return true; |
100c7420 | 3600 | |
4888ec5d UW |
3601 | if ((addr.base && REG_P (addr.base) && REG_POINTER (addr.base)) |
3602 | || (addr.indx && REG_P (addr.indx) && REG_POINTER (addr.indx))) | |
3ed99cc9 | 3603 | return true; |
100c7420 | 3604 | |
3ed99cc9 | 3605 | return false; |
100c7420 UW |
3606 | } |
3607 | ||
a41c6c53 UW |
3608 | /* Emit a forced load-address operation to load SRC into DST. |
3609 | This will use the LOAD ADDRESS instruction even in situations | |
3610 | where legitimate_la_operand_p (SRC) returns false. */ | |
ba956982 | 3611 | |
a41c6c53 | 3612 | void |
9c808aad | 3613 | s390_load_address (rtx dst, rtx src) |
f3e9edff | 3614 | { |
a41c6c53 UW |
3615 | if (TARGET_64BIT) |
3616 | emit_move_insn (dst, src); | |
3617 | else | |
3618 | emit_insn (gen_force_la_31 (dst, src)); | |
ba956982 UW |
3619 | } |
3620 | ||
9db1d521 HP |
3621 | /* Return a legitimate reference for ORIG (an address) using the |
3622 | register REG. If REG is 0, a new pseudo is generated. | |
3623 | ||
3624 | There are two types of references that must be handled: | |
3625 | ||
3626 | 1. Global data references must load the address from the GOT, via | |
3627 | the PIC reg. An insn is emitted to do this load, and the reg is | |
3628 | returned. | |
3629 | ||
3630 | 2. Static data references, constant pool addresses, and code labels | |
3631 | compute the address as an offset from the GOT, whose base is in | |
114278e7 | 3632 | the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to |
9db1d521 HP |
3633 | differentiate them from global data objects. The returned |
3634 | address is the PIC reg + an unspec constant. | |
3635 | ||
331d9186 | 3636 | TARGET_LEGITIMIZE_ADDRESS_P rejects symbolic references unless the PIC |
9db1d521 HP |
3637 | reg also appears in the address. */ |
3638 | ||
3639 | rtx | |
9c808aad | 3640 | legitimize_pic_address (rtx orig, rtx reg) |
9db1d521 HP |
3641 | { |
3642 | rtx addr = orig; | |
0ff4390d | 3643 | rtx addend = const0_rtx; |
0a2aaacc | 3644 | rtx new_rtx = orig; |
9db1d521 | 3645 | |
cf9d7618 ANM |
3646 | gcc_assert (!TLS_SYMBOLIC_CONST (addr)); |
3647 | ||
0ff4390d AK |
3648 | if (GET_CODE (addr) == CONST) |
3649 | addr = XEXP (addr, 0); | |
3650 | ||
3651 | if (GET_CODE (addr) == PLUS) | |
9db1d521 | 3652 | { |
0ff4390d AK |
3653 | addend = XEXP (addr, 1); |
3654 | addr = XEXP (addr, 0); | |
3655 | } | |
3656 | ||
3657 | if ((GET_CODE (addr) == LABEL_REF | |
3658 | || (GET_CODE (addr) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (addr)) | |
3659 | || (GET_CODE (addr) == UNSPEC && | |
3660 | (XINT (addr, 1) == UNSPEC_GOTENT | |
3661 | || (TARGET_CPU_ZARCH && XINT (addr, 1) == UNSPEC_PLT)))) | |
3662 | && GET_CODE (addend) == CONST_INT) | |
3663 | { | |
3664 | /* This can be locally addressed. */ | |
3665 | ||
3666 | /* larl_operand requires UNSPECs to be wrapped in a const rtx. */ | |
3667 | rtx const_addr = (GET_CODE (addr) == UNSPEC ? | |
3668 | gen_rtx_CONST (Pmode, addr) : addr); | |
3669 | ||
3670 | if (TARGET_CPU_ZARCH | |
3671 | && larl_operand (const_addr, VOIDmode) | |
3672 | && INTVAL (addend) < (HOST_WIDE_INT)1 << 31 | |
3673 | && INTVAL (addend) >= -((HOST_WIDE_INT)1 << 31)) | |
3674 | { | |
3675 | if (INTVAL (addend) & 1) | |
3676 | { | |
3677 | /* LARL can't handle odd offsets, so emit a pair of LARL | |
3678 | and LA. */ | |
3679 | rtx temp = reg? reg : gen_reg_rtx (Pmode); | |
3680 | ||
3681 | if (!DISP_IN_RANGE (INTVAL (addend))) | |
3682 | { | |
3683 | HOST_WIDE_INT even = INTVAL (addend) - 1; | |
3684 | addr = gen_rtx_PLUS (Pmode, addr, GEN_INT (even)); | |
3685 | addr = gen_rtx_CONST (Pmode, addr); | |
3686 | addend = const1_rtx; | |
3687 | } | |
3688 | ||
3689 | emit_move_insn (temp, addr); | |
3690 | new_rtx = gen_rtx_PLUS (Pmode, temp, addend); | |
3691 | ||
3692 | if (reg != 0) | |
3693 | { | |
3694 | s390_load_address (reg, new_rtx); | |
3695 | new_rtx = reg; | |
3696 | } | |
3697 | } | |
3698 | else | |
3699 | { | |
3700 | /* If the offset is even, we can just use LARL. This | |
3701 | will happen automatically. */ | |
3702 | } | |
3703 | } | |
9db1d521 | 3704 | else |
0ff4390d AK |
3705 | { |
3706 | /* No larl - Access local symbols relative to the GOT. */ | |
9db1d521 | 3707 | |
0ff4390d | 3708 | rtx temp = reg? reg : gen_reg_rtx (Pmode); |
9db1d521 | 3709 | |
fd7643fb | 3710 | if (reload_in_progress || reload_completed) |
6fb5fa3c | 3711 | df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true); |
fd7643fb | 3712 | |
0ff4390d AK |
3713 | addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTOFF); |
3714 | if (addend != const0_rtx) | |
3715 | addr = gen_rtx_PLUS (Pmode, addr, addend); | |
3716 | addr = gen_rtx_CONST (Pmode, addr); | |
3717 | addr = force_const_mem (Pmode, addr); | |
9db1d521 HP |
3718 | emit_move_insn (temp, addr); |
3719 | ||
0ff4390d AK |
3720 | new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp); |
3721 | if (reg != 0) | |
3722 | { | |
3723 | s390_load_address (reg, new_rtx); | |
3724 | new_rtx = reg; | |
3725 | } | |
3726 | } | |
9db1d521 | 3727 | } |
0ff4390d | 3728 | else if (GET_CODE (addr) == SYMBOL_REF && addend == const0_rtx) |
9db1d521 | 3729 | { |
0ff4390d AK |
3730 | /* A non-local symbol reference without addend. |
3731 | ||
3732 | The symbol ref is wrapped into an UNSPEC to make sure the | |
3733 | proper operand modifier (@GOT or @GOTENT) will be emitted. | |
3734 | This will tell the linker to put the symbol into the GOT. | |
3735 | ||
3736 | Additionally the code dereferencing the GOT slot is emitted here. | |
3737 | ||
3738 | An addend to the symref needs to be added afterwards. | |
3739 | legitimize_pic_address calls itself recursively to handle | |
3740 | that case. So no need to do it here. */ | |
3741 | ||
9db1d521 HP |
3742 | if (reg == 0) |
3743 | reg = gen_reg_rtx (Pmode); | |
3744 | ||
0ff4390d AK |
3745 | if (TARGET_Z10) |
3746 | { | |
3747 | /* Use load relative if possible. | |
3748 | lgrl <target>, sym@GOTENT */ | |
3749 | new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTENT); | |
3750 | new_rtx = gen_rtx_CONST (Pmode, new_rtx); | |
3751 | new_rtx = gen_const_mem (GET_MODE (reg), new_rtx); | |
3752 | ||
3753 | emit_move_insn (reg, new_rtx); | |
3754 | new_rtx = reg; | |
3755 | } | |
3756 | else if (flag_pic == 1) | |
9db1d521 | 3757 | { |
0ff4390d AK |
3758 | /* Assume GOT offset is a valid displacement operand (< 4k |
3759 | or < 512k with z990). This is handled the same way in | |
3760 | both 31- and 64-bit code (@GOT). | |
3761 | lg <target>, sym@GOT(r12) */ | |
9db1d521 | 3762 | |
c3cc6b78 | 3763 | if (reload_in_progress || reload_completed) |
6fb5fa3c | 3764 | df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true); |
9db1d521 | 3765 | |
0a2aaacc KG |
3766 | new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOT); |
3767 | new_rtx = gen_rtx_CONST (Pmode, new_rtx); | |
3768 | new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx); | |
3769 | new_rtx = gen_const_mem (Pmode, new_rtx); | |
3770 | emit_move_insn (reg, new_rtx); | |
3771 | new_rtx = reg; | |
9db1d521 | 3772 | } |
9e8327e3 | 3773 | else if (TARGET_CPU_ZARCH) |
9db1d521 HP |
3774 | { |
3775 | /* If the GOT offset might be >= 4k, we determine the position | |
0ff4390d AK |
3776 | of the GOT entry via a PC-relative LARL (@GOTENT). |
3777 | larl temp, sym@GOTENT | |
3778 | lg <target>, 0(temp) */ | |
9db1d521 | 3779 | |
1f9e1fc6 AK |
3780 | rtx temp = reg ? reg : gen_reg_rtx (Pmode); |
3781 | ||
3782 | gcc_assert (REGNO (temp) >= FIRST_PSEUDO_REGISTER | |
3783 | || REGNO_REG_CLASS (REGNO (temp)) == ADDR_REGS); | |
9db1d521 | 3784 | |
0a2aaacc KG |
3785 | new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTENT); |
3786 | new_rtx = gen_rtx_CONST (Pmode, new_rtx); | |
0ff4390d | 3787 | emit_move_insn (temp, new_rtx); |
9db1d521 | 3788 | |
0ff4390d | 3789 | new_rtx = gen_const_mem (Pmode, temp); |
0a2aaacc | 3790 | emit_move_insn (reg, new_rtx); |
0ff4390d | 3791 | |
0a2aaacc | 3792 | new_rtx = reg; |
9db1d521 HP |
3793 | } |
3794 | else | |
3795 | { | |
c7453384 | 3796 | /* If the GOT offset might be >= 4k, we have to load it |
0ff4390d AK |
3797 | from the literal pool (@GOT). |
3798 | ||
3799 | lg temp, lit-litbase(r13) | |
3800 | lg <target>, 0(temp) | |
3801 | lit: .long sym@GOT */ | |
9db1d521 | 3802 | |
1f9e1fc6 AK |
3803 | rtx temp = reg ? reg : gen_reg_rtx (Pmode); |
3804 | ||
3805 | gcc_assert (REGNO (temp) >= FIRST_PSEUDO_REGISTER | |
3806 | || REGNO_REG_CLASS (REGNO (temp)) == ADDR_REGS); | |
9db1d521 | 3807 | |
c3cc6b78 | 3808 | if (reload_in_progress || reload_completed) |
6fb5fa3c | 3809 | df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true); |
9db1d521 | 3810 | |
fd7643fb | 3811 | addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOT); |
e23795ea UW |
3812 | addr = gen_rtx_CONST (Pmode, addr); |
3813 | addr = force_const_mem (Pmode, addr); | |
9db1d521 HP |
3814 | emit_move_insn (temp, addr); |
3815 | ||
0a2aaacc KG |
3816 | new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp); |
3817 | new_rtx = gen_const_mem (Pmode, new_rtx); | |
3818 | emit_move_insn (reg, new_rtx); | |
3819 | new_rtx = reg; | |
9db1d521 | 3820 | } |
c7453384 | 3821 | } |
0ff4390d | 3822 | else if (GET_CODE (addr) == UNSPEC && GET_CODE (addend) == CONST_INT) |
9db1d521 | 3823 | { |
0ff4390d AK |
3824 | gcc_assert (XVECLEN (addr, 0) == 1); |
3825 | switch (XINT (addr, 1)) | |
9db1d521 | 3826 | { |
0ff4390d AK |
3827 | /* These address symbols (or PLT slots) relative to the GOT |
3828 | (not GOT slots!). In general this will exceed the | |
3829 | displacement range so these value belong into the literal | |
3830 | pool. */ | |
3831 | case UNSPEC_GOTOFF: | |
3832 | case UNSPEC_PLTOFF: | |
3833 | new_rtx = force_const_mem (Pmode, orig); | |
3834 | break; | |
9db1d521 | 3835 | |
0ff4390d AK |
3836 | /* For -fPIC the GOT size might exceed the displacement |
3837 | range so make sure the value is in the literal pool. */ | |
3838 | case UNSPEC_GOT: | |
3839 | if (flag_pic == 2) | |
3840 | new_rtx = force_const_mem (Pmode, orig); | |
3841 | break; | |
9db1d521 | 3842 | |
0ff4390d AK |
3843 | /* For @GOTENT larl is used. This is handled like local |
3844 | symbol refs. */ | |
3845 | case UNSPEC_GOTENT: | |
3846 | gcc_unreachable (); | |
3847 | break; | |
9db1d521 | 3848 | |
0ff4390d AK |
3849 | /* @PLT is OK as is on 64-bit, must be converted to |
3850 | GOT-relative @PLTOFF on 31-bit. */ | |
3851 | case UNSPEC_PLT: | |
3852 | if (!TARGET_CPU_ZARCH) | |
9db1d521 | 3853 | { |
0ff4390d AK |
3854 | rtx temp = reg? reg : gen_reg_rtx (Pmode); |
3855 | ||
3856 | if (reload_in_progress || reload_completed) | |
3857 | df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true); | |
3858 | ||
3859 | addr = XVECEXP (addr, 0, 0); | |
3860 | addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), | |
3861 | UNSPEC_PLTOFF); | |
3862 | if (addend != const0_rtx) | |
3863 | addr = gen_rtx_PLUS (Pmode, addr, addend); | |
3864 | addr = gen_rtx_CONST (Pmode, addr); | |
3865 | addr = force_const_mem (Pmode, addr); | |
3866 | emit_move_insn (temp, addr); | |
3867 | ||
3868 | new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp); | |
3869 | if (reg != 0) | |
9db1d521 | 3870 | { |
0ff4390d AK |
3871 | s390_load_address (reg, new_rtx); |
3872 | new_rtx = reg; | |
9db1d521 | 3873 | } |
0ff4390d AK |
3874 | } |
3875 | else | |
3876 | /* On 64 bit larl can be used. This case is handled like | |
3877 | local symbol refs. */ | |
3878 | gcc_unreachable (); | |
3879 | break; | |
3880 | ||
3881 | /* Everything else cannot happen. */ | |
3882 | default: | |
3883 | gcc_unreachable (); | |
3884 | } | |
3885 | } | |
3886 | else if (addend != const0_rtx) | |
3887 | { | |
3888 | /* Otherwise, compute the sum. */ | |
9db1d521 | 3889 | |
0ff4390d AK |
3890 | rtx base = legitimize_pic_address (addr, reg); |
3891 | new_rtx = legitimize_pic_address (addend, | |
3892 | base == reg ? NULL_RTX : reg); | |
3893 | if (GET_CODE (new_rtx) == CONST_INT) | |
3894 | new_rtx = plus_constant (Pmode, base, INTVAL (new_rtx)); | |
3895 | else | |
3896 | { | |
3897 | if (GET_CODE (new_rtx) == PLUS && CONSTANT_P (XEXP (new_rtx, 1))) | |
3898 | { | |
3899 | base = gen_rtx_PLUS (Pmode, base, XEXP (new_rtx, 0)); | |
3900 | new_rtx = XEXP (new_rtx, 1); | |
9db1d521 | 3901 | } |
0ff4390d | 3902 | new_rtx = gen_rtx_PLUS (Pmode, base, new_rtx); |
9db1d521 | 3903 | } |
0ff4390d AK |
3904 | |
3905 | if (GET_CODE (new_rtx) == CONST) | |
3906 | new_rtx = XEXP (new_rtx, 0); | |
3907 | new_rtx = force_operand (new_rtx, 0); | |
9db1d521 | 3908 | } |
0ff4390d | 3909 | |
0a2aaacc | 3910 | return new_rtx; |
9db1d521 HP |
3911 | } |
3912 | ||
fd3cd001 UW |
3913 | /* Load the thread pointer into a register. */ |
3914 | ||
7b8acc34 AK |
3915 | rtx |
3916 | s390_get_thread_pointer (void) | |
fd3cd001 | 3917 | { |
c5aa1d12 | 3918 | rtx tp = gen_reg_rtx (Pmode); |
fd3cd001 | 3919 | |
c5aa1d12 | 3920 | emit_move_insn (tp, gen_rtx_REG (Pmode, TP_REGNUM)); |
fd3cd001 UW |
3921 | mark_reg_pointer (tp, BITS_PER_WORD); |
3922 | ||
3923 | return tp; | |
3924 | } | |
3925 | ||
ed9676cf AK |
3926 | /* Emit a tls call insn. The call target is the SYMBOL_REF stored |
3927 | in s390_tls_symbol which always refers to __tls_get_offset. | |
3928 | The returned offset is written to RESULT_REG and an USE rtx is | |
3929 | generated for TLS_CALL. */ | |
fd3cd001 UW |
3930 | |
3931 | static GTY(()) rtx s390_tls_symbol; | |
ed9676cf AK |
3932 | |
3933 | static void | |
3934 | s390_emit_tls_call_insn (rtx result_reg, rtx tls_call) | |
fd3cd001 | 3935 | { |
ed9676cf | 3936 | rtx insn; |
38899e29 | 3937 | |
68c0ef75 AK |
3938 | if (!flag_pic) |
3939 | emit_insn (s390_load_got ()); | |
ed9676cf | 3940 | |
fd3cd001 UW |
3941 | if (!s390_tls_symbol) |
3942 | s390_tls_symbol = gen_rtx_SYMBOL_REF (Pmode, "__tls_get_offset"); | |
3943 | ||
38899e29 EC |
3944 | insn = s390_emit_call (s390_tls_symbol, tls_call, result_reg, |
3945 | gen_rtx_REG (Pmode, RETURN_REGNUM)); | |
ed9676cf AK |
3946 | |
3947 | use_reg (&CALL_INSN_FUNCTION_USAGE (insn), result_reg); | |
becfd6e5 | 3948 | RTL_CONST_CALL_P (insn) = 1; |
fd3cd001 UW |
3949 | } |
3950 | ||
3951 | /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute | |
3952 | this (thread-local) address. REG may be used as temporary. */ | |
3953 | ||
3954 | static rtx | |
9c808aad | 3955 | legitimize_tls_address (rtx addr, rtx reg) |
fd3cd001 | 3956 | { |
0a2aaacc | 3957 | rtx new_rtx, tls_call, temp, base, r2, insn; |
fd3cd001 UW |
3958 | |
3959 | if (GET_CODE (addr) == SYMBOL_REF) | |
3960 | switch (tls_symbolic_operand (addr)) | |
3961 | { | |
3962 | case TLS_MODEL_GLOBAL_DYNAMIC: | |
3963 | start_sequence (); | |
3964 | r2 = gen_rtx_REG (Pmode, 2); | |
3965 | tls_call = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_TLSGD); | |
0a2aaacc KG |
3966 | new_rtx = gen_rtx_CONST (Pmode, tls_call); |
3967 | new_rtx = force_const_mem (Pmode, new_rtx); | |
3968 | emit_move_insn (r2, new_rtx); | |
ed9676cf | 3969 | s390_emit_tls_call_insn (r2, tls_call); |
fd3cd001 UW |
3970 | insn = get_insns (); |
3971 | end_sequence (); | |
3972 | ||
0a2aaacc | 3973 | new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_NTPOFF); |
fd3cd001 | 3974 | temp = gen_reg_rtx (Pmode); |
0a2aaacc | 3975 | emit_libcall_block (insn, temp, r2, new_rtx); |
fd3cd001 | 3976 | |
0a2aaacc | 3977 | new_rtx = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp); |
fd3cd001 UW |
3978 | if (reg != 0) |
3979 | { | |
0a2aaacc KG |
3980 | s390_load_address (reg, new_rtx); |
3981 | new_rtx = reg; | |
fd3cd001 UW |
3982 | } |
3983 | break; | |
3984 | ||
3985 | case TLS_MODEL_LOCAL_DYNAMIC: | |
3986 | start_sequence (); | |
3987 | r2 = gen_rtx_REG (Pmode, 2); | |
3988 | tls_call = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_TLSLDM); | |
0a2aaacc KG |
3989 | new_rtx = gen_rtx_CONST (Pmode, tls_call); |
3990 | new_rtx = force_const_mem (Pmode, new_rtx); | |
3991 | emit_move_insn (r2, new_rtx); | |
ed9676cf | 3992 | s390_emit_tls_call_insn (r2, tls_call); |
fd3cd001 UW |
3993 | insn = get_insns (); |
3994 | end_sequence (); | |
3995 | ||
0a2aaacc | 3996 | new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_TLSLDM_NTPOFF); |
fd3cd001 | 3997 | temp = gen_reg_rtx (Pmode); |
0a2aaacc | 3998 | emit_libcall_block (insn, temp, r2, new_rtx); |
fd3cd001 | 3999 | |
0a2aaacc | 4000 | new_rtx = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp); |
fd3cd001 | 4001 | base = gen_reg_rtx (Pmode); |
0a2aaacc | 4002 | s390_load_address (base, new_rtx); |
fd3cd001 | 4003 | |
0a2aaacc KG |
4004 | new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_DTPOFF); |
4005 | new_rtx = gen_rtx_CONST (Pmode, new_rtx); | |
4006 | new_rtx = force_const_mem (Pmode, new_rtx); | |
fd3cd001 | 4007 | temp = gen_reg_rtx (Pmode); |
0a2aaacc | 4008 | emit_move_insn (temp, new_rtx); |
fd3cd001 | 4009 | |
0a2aaacc | 4010 | new_rtx = gen_rtx_PLUS (Pmode, base, temp); |
fd3cd001 UW |
4011 | if (reg != 0) |
4012 | { | |
0a2aaacc KG |
4013 | s390_load_address (reg, new_rtx); |
4014 | new_rtx = reg; | |
fd3cd001 UW |
4015 | } |
4016 | break; | |
4017 | ||
4018 | case TLS_MODEL_INITIAL_EXEC: | |
4019 | if (flag_pic == 1) | |
4020 | { | |
4021 | /* Assume GOT offset < 4k. This is handled the same way | |
4022 | in both 31- and 64-bit code. */ | |
4023 | ||
4024 | if (reload_in_progress || reload_completed) | |
6fb5fa3c | 4025 | df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true); |
fd3cd001 | 4026 | |
0a2aaacc KG |
4027 | new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTNTPOFF); |
4028 | new_rtx = gen_rtx_CONST (Pmode, new_rtx); | |
4029 | new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx); | |
4030 | new_rtx = gen_const_mem (Pmode, new_rtx); | |
fd3cd001 | 4031 | temp = gen_reg_rtx (Pmode); |
0a2aaacc | 4032 | emit_move_insn (temp, new_rtx); |
fd3cd001 | 4033 | } |
9e8327e3 | 4034 | else if (TARGET_CPU_ZARCH) |
fd3cd001 UW |
4035 | { |
4036 | /* If the GOT offset might be >= 4k, we determine the position | |
4037 | of the GOT entry via a PC-relative LARL. */ | |
4038 | ||
0a2aaacc KG |
4039 | new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_INDNTPOFF); |
4040 | new_rtx = gen_rtx_CONST (Pmode, new_rtx); | |
fd3cd001 | 4041 | temp = gen_reg_rtx (Pmode); |
0a2aaacc | 4042 | emit_move_insn (temp, new_rtx); |
fd3cd001 | 4043 | |
0a2aaacc | 4044 | new_rtx = gen_const_mem (Pmode, temp); |
fd3cd001 | 4045 | temp = gen_reg_rtx (Pmode); |
0a2aaacc | 4046 | emit_move_insn (temp, new_rtx); |
fd3cd001 UW |
4047 | } |
4048 | else if (flag_pic) | |
4049 | { | |
c7453384 | 4050 | /* If the GOT offset might be >= 4k, we have to load it |
fd3cd001 UW |
4051 | from the literal pool. */ |
4052 | ||
4053 | if (reload_in_progress || reload_completed) | |
6fb5fa3c | 4054 | df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true); |
fd3cd001 | 4055 | |
0a2aaacc KG |
4056 | new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTNTPOFF); |
4057 | new_rtx = gen_rtx_CONST (Pmode, new_rtx); | |
4058 | new_rtx = force_const_mem (Pmode, new_rtx); | |
fd3cd001 | 4059 | temp = gen_reg_rtx (Pmode); |
0a2aaacc | 4060 | emit_move_insn (temp, new_rtx); |
fd3cd001 | 4061 | |
0a2aaacc KG |
4062 | new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp); |
4063 | new_rtx = gen_const_mem (Pmode, new_rtx); | |
fd3cd001 | 4064 | |
0a2aaacc | 4065 | new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, new_rtx, addr), UNSPEC_TLS_LOAD); |
fd3cd001 | 4066 | temp = gen_reg_rtx (Pmode); |
f7df4a84 | 4067 | emit_insn (gen_rtx_SET (temp, new_rtx)); |
fd3cd001 UW |
4068 | } |
4069 | else | |
4070 | { | |
4071 | /* In position-dependent code, load the absolute address of | |
4072 | the GOT entry from the literal pool. */ | |
4073 | ||
0a2aaacc KG |
4074 | new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_INDNTPOFF); |
4075 | new_rtx = gen_rtx_CONST (Pmode, new_rtx); | |
4076 | new_rtx = force_const_mem (Pmode, new_rtx); | |
fd3cd001 | 4077 | temp = gen_reg_rtx (Pmode); |
0a2aaacc | 4078 | emit_move_insn (temp, new_rtx); |
fd3cd001 | 4079 | |
0a2aaacc KG |
4080 | new_rtx = temp; |
4081 | new_rtx = gen_const_mem (Pmode, new_rtx); | |
4082 | new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, new_rtx, addr), UNSPEC_TLS_LOAD); | |
fd3cd001 | 4083 | temp = gen_reg_rtx (Pmode); |
f7df4a84 | 4084 | emit_insn (gen_rtx_SET (temp, new_rtx)); |
fd3cd001 UW |
4085 | } |
4086 | ||
0a2aaacc | 4087 | new_rtx = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp); |
fd3cd001 UW |
4088 | if (reg != 0) |
4089 | { | |
0a2aaacc KG |
4090 | s390_load_address (reg, new_rtx); |
4091 | new_rtx = reg; | |
fd3cd001 UW |
4092 | } |
4093 | break; | |
4094 | ||
4095 | case TLS_MODEL_LOCAL_EXEC: | |
0a2aaacc KG |
4096 | new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_NTPOFF); |
4097 | new_rtx = gen_rtx_CONST (Pmode, new_rtx); | |
4098 | new_rtx = force_const_mem (Pmode, new_rtx); | |
fd3cd001 | 4099 | temp = gen_reg_rtx (Pmode); |
0a2aaacc | 4100 | emit_move_insn (temp, new_rtx); |
fd3cd001 | 4101 | |
0a2aaacc | 4102 | new_rtx = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp); |
fd3cd001 UW |
4103 | if (reg != 0) |
4104 | { | |
0a2aaacc KG |
4105 | s390_load_address (reg, new_rtx); |
4106 | new_rtx = reg; | |
fd3cd001 UW |
4107 | } |
4108 | break; | |
4109 | ||
4110 | default: | |
8d933e31 | 4111 | gcc_unreachable (); |
fd3cd001 UW |
4112 | } |
4113 | ||
4114 | else if (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == UNSPEC) | |
4115 | { | |
4116 | switch (XINT (XEXP (addr, 0), 1)) | |
4117 | { | |
4118 | case UNSPEC_INDNTPOFF: | |
8d933e31 | 4119 | gcc_assert (TARGET_CPU_ZARCH); |
0a2aaacc | 4120 | new_rtx = addr; |
fd3cd001 UW |
4121 | break; |
4122 | ||
4123 | default: | |
8d933e31 | 4124 | gcc_unreachable (); |
fd3cd001 UW |
4125 | } |
4126 | } | |
4127 | ||
578d1468 UW |
4128 | else if (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == PLUS |
4129 | && GET_CODE (XEXP (XEXP (addr, 0), 1)) == CONST_INT) | |
4130 | { | |
0a2aaacc KG |
4131 | new_rtx = XEXP (XEXP (addr, 0), 0); |
4132 | if (GET_CODE (new_rtx) != SYMBOL_REF) | |
4133 | new_rtx = gen_rtx_CONST (Pmode, new_rtx); | |
578d1468 | 4134 | |
0a2aaacc | 4135 | new_rtx = legitimize_tls_address (new_rtx, reg); |
0a81f074 RS |
4136 | new_rtx = plus_constant (Pmode, new_rtx, |
4137 | INTVAL (XEXP (XEXP (addr, 0), 1))); | |
0a2aaacc | 4138 | new_rtx = force_operand (new_rtx, 0); |
578d1468 UW |
4139 | } |
4140 | ||
fd3cd001 | 4141 | else |
8d933e31 | 4142 | gcc_unreachable (); /* for now ... */ |
fd3cd001 | 4143 | |
0a2aaacc | 4144 | return new_rtx; |
fd3cd001 UW |
4145 | } |
4146 | ||
1f9e1fc6 AK |
4147 | /* Emit insns making the address in operands[1] valid for a standard |
4148 | move to operands[0]. operands[1] is replaced by an address which | |
4149 | should be used instead of the former RTX to emit the move | |
4150 | pattern. */ | |
9db1d521 HP |
4151 | |
4152 | void | |
9c808aad | 4153 | emit_symbolic_move (rtx *operands) |
9db1d521 | 4154 | { |
b3a13419 | 4155 | rtx temp = !can_create_pseudo_p () ? operands[0] : gen_reg_rtx (Pmode); |
9db1d521 | 4156 | |
fd3cd001 | 4157 | if (GET_CODE (operands[0]) == MEM) |
9db1d521 | 4158 | operands[1] = force_reg (Pmode, operands[1]); |
fd3cd001 UW |
4159 | else if (TLS_SYMBOLIC_CONST (operands[1])) |
4160 | operands[1] = legitimize_tls_address (operands[1], temp); | |
4161 | else if (flag_pic) | |
9db1d521 HP |
4162 | operands[1] = legitimize_pic_address (operands[1], temp); |
4163 | } | |
4164 | ||
994fe660 | 4165 | /* Try machine-dependent ways of modifying an illegitimate address X |
9db1d521 | 4166 | to be legitimate. If we find one, return the new, valid address. |
9db1d521 HP |
4167 | |
4168 | OLDX is the address as it was before break_out_memory_refs was called. | |
4169 | In some cases it is useful to look at this to decide what needs to be done. | |
4170 | ||
994fe660 | 4171 | MODE is the mode of the operand pointed to by X. |
9db1d521 HP |
4172 | |
4173 | When -fpic is used, special handling is needed for symbolic references. | |
4174 | See comments by legitimize_pic_address for details. */ | |
4175 | ||
506d7b68 PB |
4176 | static rtx |
4177 | s390_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, | |
ef4bddc2 | 4178 | machine_mode mode ATTRIBUTE_UNUSED) |
9db1d521 | 4179 | { |
ba956982 | 4180 | rtx constant_term = const0_rtx; |
9db1d521 | 4181 | |
fd3cd001 UW |
4182 | if (TLS_SYMBOLIC_CONST (x)) |
4183 | { | |
4184 | x = legitimize_tls_address (x, 0); | |
4185 | ||
c6c3dba9 | 4186 | if (s390_legitimate_address_p (mode, x, FALSE)) |
fd3cd001 UW |
4187 | return x; |
4188 | } | |
cf9d7618 | 4189 | else if (GET_CODE (x) == PLUS |
f4aa3848 | 4190 | && (TLS_SYMBOLIC_CONST (XEXP (x, 0)) |
cf9d7618 ANM |
4191 | || TLS_SYMBOLIC_CONST (XEXP (x, 1)))) |
4192 | { | |
4193 | return x; | |
4194 | } | |
fd3cd001 | 4195 | else if (flag_pic) |
9db1d521 | 4196 | { |
ba956982 | 4197 | if (SYMBOLIC_CONST (x) |
c7453384 EC |
4198 | || (GET_CODE (x) == PLUS |
4199 | && (SYMBOLIC_CONST (XEXP (x, 0)) | |
ba956982 UW |
4200 | || SYMBOLIC_CONST (XEXP (x, 1))))) |
4201 | x = legitimize_pic_address (x, 0); | |
4202 | ||
c6c3dba9 | 4203 | if (s390_legitimate_address_p (mode, x, FALSE)) |
ba956982 | 4204 | return x; |
9db1d521 | 4205 | } |
9db1d521 | 4206 | |
ba956982 | 4207 | x = eliminate_constant_term (x, &constant_term); |
994fe660 | 4208 | |
61f02ff5 UW |
4209 | /* Optimize loading of large displacements by splitting them |
4210 | into the multiple of 4K and the rest; this allows the | |
c7453384 | 4211 | former to be CSE'd if possible. |
61f02ff5 UW |
4212 | |
4213 | Don't do this if the displacement is added to a register | |
4214 | pointing into the stack frame, as the offsets will | |
4215 | change later anyway. */ | |
4216 | ||
4217 | if (GET_CODE (constant_term) == CONST_INT | |
d3632d41 UW |
4218 | && !TARGET_LONG_DISPLACEMENT |
4219 | && !DISP_IN_RANGE (INTVAL (constant_term)) | |
61f02ff5 UW |
4220 | && !(REG_P (x) && REGNO_PTR_FRAME_P (REGNO (x)))) |
4221 | { | |
4222 | HOST_WIDE_INT lower = INTVAL (constant_term) & 0xfff; | |
4223 | HOST_WIDE_INT upper = INTVAL (constant_term) ^ lower; | |
4224 | ||
4225 | rtx temp = gen_reg_rtx (Pmode); | |
4226 | rtx val = force_operand (GEN_INT (upper), temp); | |
4227 | if (val != temp) | |
4228 | emit_move_insn (temp, val); | |
4229 | ||
4230 | x = gen_rtx_PLUS (Pmode, x, temp); | |
4231 | constant_term = GEN_INT (lower); | |
4232 | } | |
4233 | ||
ba956982 | 4234 | if (GET_CODE (x) == PLUS) |
9db1d521 | 4235 | { |
ba956982 UW |
4236 | if (GET_CODE (XEXP (x, 0)) == REG) |
4237 | { | |
5d81b82b AS |
4238 | rtx temp = gen_reg_rtx (Pmode); |
4239 | rtx val = force_operand (XEXP (x, 1), temp); | |
ba956982 UW |
4240 | if (val != temp) |
4241 | emit_move_insn (temp, val); | |
4242 | ||
4243 | x = gen_rtx_PLUS (Pmode, XEXP (x, 0), temp); | |
4244 | } | |
4245 | ||
4246 | else if (GET_CODE (XEXP (x, 1)) == REG) | |
4247 | { | |
5d81b82b AS |
4248 | rtx temp = gen_reg_rtx (Pmode); |
4249 | rtx val = force_operand (XEXP (x, 0), temp); | |
ba956982 UW |
4250 | if (val != temp) |
4251 | emit_move_insn (temp, val); | |
4252 | ||
4253 | x = gen_rtx_PLUS (Pmode, temp, XEXP (x, 1)); | |
4254 | } | |
9db1d521 | 4255 | } |
ba956982 UW |
4256 | |
4257 | if (constant_term != const0_rtx) | |
4258 | x = gen_rtx_PLUS (Pmode, x, constant_term); | |
4259 | ||
4260 | return x; | |
9db1d521 HP |
4261 | } |
4262 | ||
0b540f12 | 4263 | /* Try a machine-dependent way of reloading an illegitimate address AD |
dd5a833e | 4264 | operand. If we find one, push the reload and return the new address. |
0b540f12 UW |
4265 | |
4266 | MODE is the mode of the enclosing MEM. OPNUM is the operand number | |
4267 | and TYPE is the reload type of the current reload. */ | |
4268 | ||
f4aa3848 | 4269 | rtx |
ef4bddc2 | 4270 | legitimize_reload_address (rtx ad, machine_mode mode ATTRIBUTE_UNUSED, |
0b540f12 UW |
4271 | int opnum, int type) |
4272 | { | |
4273 | if (!optimize || TARGET_LONG_DISPLACEMENT) | |
4274 | return NULL_RTX; | |
4275 | ||
4276 | if (GET_CODE (ad) == PLUS) | |
4277 | { | |
4278 | rtx tem = simplify_binary_operation (PLUS, Pmode, | |
4279 | XEXP (ad, 0), XEXP (ad, 1)); | |
4280 | if (tem) | |
4281 | ad = tem; | |
4282 | } | |
4283 | ||
4284 | if (GET_CODE (ad) == PLUS | |
4285 | && GET_CODE (XEXP (ad, 0)) == REG | |
4286 | && GET_CODE (XEXP (ad, 1)) == CONST_INT | |
4287 | && !DISP_IN_RANGE (INTVAL (XEXP (ad, 1)))) | |
4288 | { | |
4289 | HOST_WIDE_INT lower = INTVAL (XEXP (ad, 1)) & 0xfff; | |
4290 | HOST_WIDE_INT upper = INTVAL (XEXP (ad, 1)) ^ lower; | |
0a2aaacc | 4291 | rtx cst, tem, new_rtx; |
0b540f12 UW |
4292 | |
4293 | cst = GEN_INT (upper); | |
4294 | if (!legitimate_reload_constant_p (cst)) | |
4295 | cst = force_const_mem (Pmode, cst); | |
4296 | ||
4297 | tem = gen_rtx_PLUS (Pmode, XEXP (ad, 0), cst); | |
0a2aaacc | 4298 | new_rtx = gen_rtx_PLUS (Pmode, tem, GEN_INT (lower)); |
0b540f12 UW |
4299 | |
4300 | push_reload (XEXP (tem, 1), 0, &XEXP (tem, 1), 0, | |
f4aa3848 | 4301 | BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, |
0b540f12 | 4302 | opnum, (enum reload_type) type); |
0a2aaacc | 4303 | return new_rtx; |
0b540f12 UW |
4304 | } |
4305 | ||
4306 | return NULL_RTX; | |
4307 | } | |
4308 | ||
a41c6c53 UW |
4309 | /* Emit code to move LEN bytes from DST to SRC. */ |
4310 | ||
367d32f3 | 4311 | bool |
70128ad9 | 4312 | s390_expand_movmem (rtx dst, rtx src, rtx len) |
a41c6c53 | 4313 | { |
367d32f3 AK |
4314 | /* When tuning for z10 or higher we rely on the Glibc functions to |
4315 | do the right thing. Only for constant lengths below 64k we will | |
4316 | generate inline code. */ | |
4317 | if (s390_tune >= PROCESSOR_2097_Z10 | |
4318 | && (GET_CODE (len) != CONST_INT || INTVAL (len) > (1<<16))) | |
4319 | return false; | |
4320 | ||
a41c6c53 UW |
4321 | if (GET_CODE (len) == CONST_INT && INTVAL (len) >= 0 && INTVAL (len) <= 256) |
4322 | { | |
4323 | if (INTVAL (len) > 0) | |
70128ad9 | 4324 | emit_insn (gen_movmem_short (dst, src, GEN_INT (INTVAL (len) - 1))); |
a41c6c53 UW |
4325 | } |
4326 | ||
4327 | else if (TARGET_MVCLE) | |
4328 | { | |
70128ad9 | 4329 | emit_insn (gen_movmem_long (dst, src, convert_to_mode (Pmode, len, 1))); |
a41c6c53 UW |
4330 | } |
4331 | ||
4332 | else | |
4333 | { | |
4334 | rtx dst_addr, src_addr, count, blocks, temp; | |
19f8b229 TS |
4335 | rtx_code_label *loop_start_label = gen_label_rtx (); |
4336 | rtx_code_label *loop_end_label = gen_label_rtx (); | |
4337 | rtx_code_label *end_label = gen_label_rtx (); | |
ef4bddc2 | 4338 | machine_mode mode; |
a41c6c53 UW |
4339 | |
4340 | mode = GET_MODE (len); | |
4341 | if (mode == VOIDmode) | |
b9404c99 | 4342 | mode = Pmode; |
a41c6c53 | 4343 | |
a41c6c53 UW |
4344 | dst_addr = gen_reg_rtx (Pmode); |
4345 | src_addr = gen_reg_rtx (Pmode); | |
4346 | count = gen_reg_rtx (mode); | |
4347 | blocks = gen_reg_rtx (mode); | |
4348 | ||
4349 | convert_move (count, len, 1); | |
c7453384 | 4350 | emit_cmp_and_jump_insns (count, const0_rtx, |
a41c6c53 UW |
4351 | EQ, NULL_RTX, mode, 1, end_label); |
4352 | ||
4353 | emit_move_insn (dst_addr, force_operand (XEXP (dst, 0), NULL_RTX)); | |
4354 | emit_move_insn (src_addr, force_operand (XEXP (src, 0), NULL_RTX)); | |
4355 | dst = change_address (dst, VOIDmode, dst_addr); | |
4356 | src = change_address (src, VOIDmode, src_addr); | |
c7453384 | 4357 | |
bbbbb16a ILT |
4358 | temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1, |
4359 | OPTAB_DIRECT); | |
a41c6c53 UW |
4360 | if (temp != count) |
4361 | emit_move_insn (count, temp); | |
4362 | ||
bbbbb16a ILT |
4363 | temp = expand_binop (mode, lshr_optab, count, GEN_INT (8), blocks, 1, |
4364 | OPTAB_DIRECT); | |
a41c6c53 UW |
4365 | if (temp != blocks) |
4366 | emit_move_insn (blocks, temp); | |
4367 | ||
6de9cd9a DN |
4368 | emit_cmp_and_jump_insns (blocks, const0_rtx, |
4369 | EQ, NULL_RTX, mode, 1, loop_end_label); | |
70315fcd SB |
4370 | |
4371 | emit_label (loop_start_label); | |
a41c6c53 | 4372 | |
adfa3cd3 AK |
4373 | if (TARGET_Z10 |
4374 | && (GET_CODE (len) != CONST_INT || INTVAL (len) > 768)) | |
4375 | { | |
4376 | rtx prefetch; | |
4377 | ||
4378 | /* Issue a read prefetch for the +3 cache line. */ | |
4379 | prefetch = gen_prefetch (gen_rtx_PLUS (Pmode, src_addr, GEN_INT (768)), | |
4380 | const0_rtx, const0_rtx); | |
4381 | PREFETCH_SCHEDULE_BARRIER_P (prefetch) = true; | |
4382 | emit_insn (prefetch); | |
4383 | ||
4384 | /* Issue a write prefetch for the +3 cache line. */ | |
4385 | prefetch = gen_prefetch (gen_rtx_PLUS (Pmode, dst_addr, GEN_INT (768)), | |
4386 | const1_rtx, const0_rtx); | |
4387 | PREFETCH_SCHEDULE_BARRIER_P (prefetch) = true; | |
4388 | emit_insn (prefetch); | |
4389 | } | |
4390 | ||
70128ad9 | 4391 | emit_insn (gen_movmem_short (dst, src, GEN_INT (255))); |
c7453384 | 4392 | s390_load_address (dst_addr, |
a41c6c53 | 4393 | gen_rtx_PLUS (Pmode, dst_addr, GEN_INT (256))); |
c7453384 | 4394 | s390_load_address (src_addr, |
a41c6c53 | 4395 | gen_rtx_PLUS (Pmode, src_addr, GEN_INT (256))); |
c7453384 | 4396 | |
bbbbb16a ILT |
4397 | temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1, |
4398 | OPTAB_DIRECT); | |
a41c6c53 UW |
4399 | if (temp != blocks) |
4400 | emit_move_insn (blocks, temp); | |
4401 | ||
6de9cd9a DN |
4402 | emit_cmp_and_jump_insns (blocks, const0_rtx, |
4403 | EQ, NULL_RTX, mode, 1, loop_end_label); | |
70315fcd SB |
4404 | |
4405 | emit_jump (loop_start_label); | |
6de9cd9a | 4406 | emit_label (loop_end_label); |
a41c6c53 | 4407 | |
70128ad9 | 4408 | emit_insn (gen_movmem_short (dst, src, |
b9404c99 | 4409 | convert_to_mode (Pmode, count, 1))); |
a41c6c53 UW |
4410 | emit_label (end_label); |
4411 | } | |
367d32f3 | 4412 | return true; |
a41c6c53 UW |
4413 | } |
4414 | ||
6d057022 AS |
4415 | /* Emit code to set LEN bytes at DST to VAL. |
4416 | Make use of clrmem if VAL is zero. */ | |
a41c6c53 UW |
4417 | |
4418 | void | |
6d057022 | 4419 | s390_expand_setmem (rtx dst, rtx len, rtx val) |
a41c6c53 | 4420 | { |
c9f59991 AK |
4421 | if (GET_CODE (len) == CONST_INT && INTVAL (len) == 0) |
4422 | return; | |
4423 | ||
6d057022 | 4424 | gcc_assert (GET_CODE (val) == CONST_INT || GET_MODE (val) == QImode); |
f4aa3848 | 4425 | |
c9f59991 | 4426 | if (GET_CODE (len) == CONST_INT && INTVAL (len) > 0 && INTVAL (len) <= 257) |
a41c6c53 | 4427 | { |
6d057022 | 4428 | if (val == const0_rtx && INTVAL (len) <= 256) |
70128ad9 | 4429 | emit_insn (gen_clrmem_short (dst, GEN_INT (INTVAL (len) - 1))); |
6d057022 AS |
4430 | else |
4431 | { | |
4432 | /* Initialize memory by storing the first byte. */ | |
4433 | emit_move_insn (adjust_address (dst, QImode, 0), val); | |
f4aa3848 | 4434 | |
6d057022 AS |
4435 | if (INTVAL (len) > 1) |
4436 | { | |
4437 | /* Initiate 1 byte overlap move. | |
4438 | The first byte of DST is propagated through DSTP1. | |
4439 | Prepare a movmem for: DST+1 = DST (length = LEN - 1). | |
4440 | DST is set to size 1 so the rest of the memory location | |
4441 | does not count as source operand. */ | |
4442 | rtx dstp1 = adjust_address (dst, VOIDmode, 1); | |
f5541398 | 4443 | set_mem_size (dst, 1); |
6d057022 | 4444 | |
f4aa3848 | 4445 | emit_insn (gen_movmem_short (dstp1, dst, |
6d057022 AS |
4446 | GEN_INT (INTVAL (len) - 2))); |
4447 | } | |
4448 | } | |
a41c6c53 UW |
4449 | } |
4450 | ||
4451 | else if (TARGET_MVCLE) | |
4452 | { | |
6d057022 AS |
4453 | val = force_not_mem (convert_modes (Pmode, QImode, val, 1)); |
4454 | emit_insn (gen_setmem_long (dst, convert_to_mode (Pmode, len, 1), val)); | |
a41c6c53 UW |
4455 | } |
4456 | ||
4457 | else | |
4458 | { | |
9602b6a1 | 4459 | rtx dst_addr, count, blocks, temp, dstp1 = NULL_RTX; |
19f8b229 TS |
4460 | rtx_code_label *loop_start_label = gen_label_rtx (); |
4461 | rtx_code_label *loop_end_label = gen_label_rtx (); | |
4462 | rtx_code_label *end_label = gen_label_rtx (); | |
ef4bddc2 | 4463 | machine_mode mode; |
a41c6c53 UW |
4464 | |
4465 | mode = GET_MODE (len); | |
4466 | if (mode == VOIDmode) | |
b9404c99 | 4467 | mode = Pmode; |
a41c6c53 | 4468 | |
a41c6c53 | 4469 | dst_addr = gen_reg_rtx (Pmode); |
a41c6c53 UW |
4470 | count = gen_reg_rtx (mode); |
4471 | blocks = gen_reg_rtx (mode); | |
4472 | ||
4473 | convert_move (count, len, 1); | |
c7453384 | 4474 | emit_cmp_and_jump_insns (count, const0_rtx, |
a41c6c53 UW |
4475 | EQ, NULL_RTX, mode, 1, end_label); |
4476 | ||
4477 | emit_move_insn (dst_addr, force_operand (XEXP (dst, 0), NULL_RTX)); | |
4478 | dst = change_address (dst, VOIDmode, dst_addr); | |
c7453384 | 4479 | |
6d057022 | 4480 | if (val == const0_rtx) |
bbbbb16a ILT |
4481 | temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1, |
4482 | OPTAB_DIRECT); | |
6d057022 AS |
4483 | else |
4484 | { | |
4485 | dstp1 = adjust_address (dst, VOIDmode, 1); | |
f5541398 | 4486 | set_mem_size (dst, 1); |
6d057022 AS |
4487 | |
4488 | /* Initialize memory by storing the first byte. */ | |
4489 | emit_move_insn (adjust_address (dst, QImode, 0), val); | |
f4aa3848 | 4490 | |
6d057022 AS |
4491 | /* If count is 1 we are done. */ |
4492 | emit_cmp_and_jump_insns (count, const1_rtx, | |
4493 | EQ, NULL_RTX, mode, 1, end_label); | |
4494 | ||
bbbbb16a ILT |
4495 | temp = expand_binop (mode, add_optab, count, GEN_INT (-2), count, 1, |
4496 | OPTAB_DIRECT); | |
6d057022 | 4497 | } |
a41c6c53 UW |
4498 | if (temp != count) |
4499 | emit_move_insn (count, temp); | |
4500 | ||
bbbbb16a ILT |
4501 | temp = expand_binop (mode, lshr_optab, count, GEN_INT (8), blocks, 1, |
4502 | OPTAB_DIRECT); | |
a41c6c53 UW |
4503 | if (temp != blocks) |
4504 | emit_move_insn (blocks, temp); | |
4505 | ||
6de9cd9a DN |
4506 | emit_cmp_and_jump_insns (blocks, const0_rtx, |
4507 | EQ, NULL_RTX, mode, 1, loop_end_label); | |
70315fcd SB |
4508 | |
4509 | emit_label (loop_start_label); | |
a41c6c53 | 4510 | |
adfa3cd3 AK |
4511 | if (TARGET_Z10 |
4512 | && (GET_CODE (len) != CONST_INT || INTVAL (len) > 1024)) | |
4513 | { | |
4514 | /* Issue a write prefetch for the +4 cache line. */ | |
4515 | rtx prefetch = gen_prefetch (gen_rtx_PLUS (Pmode, dst_addr, | |
4516 | GEN_INT (1024)), | |
4517 | const1_rtx, const0_rtx); | |
4518 | emit_insn (prefetch); | |
4519 | PREFETCH_SCHEDULE_BARRIER_P (prefetch) = true; | |
4520 | } | |
4521 | ||
6d057022 AS |
4522 | if (val == const0_rtx) |
4523 | emit_insn (gen_clrmem_short (dst, GEN_INT (255))); | |
4524 | else | |
4525 | emit_insn (gen_movmem_short (dstp1, dst, GEN_INT (255))); | |
c7453384 | 4526 | s390_load_address (dst_addr, |
a41c6c53 | 4527 | gen_rtx_PLUS (Pmode, dst_addr, GEN_INT (256))); |
c7453384 | 4528 | |
bbbbb16a ILT |
4529 | temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1, |
4530 | OPTAB_DIRECT); | |
a41c6c53 UW |
4531 | if (temp != blocks) |
4532 | emit_move_insn (blocks, temp); | |
4533 | ||
6de9cd9a DN |
4534 | emit_cmp_and_jump_insns (blocks, const0_rtx, |
4535 | EQ, NULL_RTX, mode, 1, loop_end_label); | |
70315fcd SB |
4536 | |
4537 | emit_jump (loop_start_label); | |
6de9cd9a | 4538 | emit_label (loop_end_label); |
a41c6c53 | 4539 | |
6d057022 AS |
4540 | if (val == const0_rtx) |
4541 | emit_insn (gen_clrmem_short (dst, convert_to_mode (Pmode, count, 1))); | |
4542 | else | |
4543 | emit_insn (gen_movmem_short (dstp1, dst, convert_to_mode (Pmode, count, 1))); | |
a41c6c53 UW |
4544 | emit_label (end_label); |
4545 | } | |
4546 | } | |
4547 | ||
4548 | /* Emit code to compare LEN bytes at OP0 with those at OP1, | |
4549 | and return the result in TARGET. */ | |
4550 | ||
367d32f3 | 4551 | bool |
9c808aad | 4552 | s390_expand_cmpmem (rtx target, rtx op0, rtx op1, rtx len) |
a41c6c53 | 4553 | { |
5b022de5 | 4554 | rtx ccreg = gen_rtx_REG (CCUmode, CC_REGNUM); |
02887425 UW |
4555 | rtx tmp; |
4556 | ||
367d32f3 AK |
4557 | /* When tuning for z10 or higher we rely on the Glibc functions to |
4558 | do the right thing. Only for constant lengths below 64k we will | |
4559 | generate inline code. */ | |
4560 | if (s390_tune >= PROCESSOR_2097_Z10 | |
4561 | && (GET_CODE (len) != CONST_INT || INTVAL (len) > (1<<16))) | |
4562 | return false; | |
4563 | ||
02887425 UW |
4564 | /* As the result of CMPINT is inverted compared to what we need, |
4565 | we have to swap the operands. */ | |
4566 | tmp = op0; op0 = op1; op1 = tmp; | |
a41c6c53 | 4567 | |
a41c6c53 UW |
4568 | if (GET_CODE (len) == CONST_INT && INTVAL (len) >= 0 && INTVAL (len) <= 256) |
4569 | { | |
4570 | if (INTVAL (len) > 0) | |
4571 | { | |
b9404c99 | 4572 | emit_insn (gen_cmpmem_short (op0, op1, GEN_INT (INTVAL (len) - 1))); |
02887425 | 4573 | emit_insn (gen_cmpint (target, ccreg)); |
a41c6c53 UW |
4574 | } |
4575 | else | |
4576 | emit_move_insn (target, const0_rtx); | |
4577 | } | |
9dc62c00 | 4578 | else if (TARGET_MVCLE) |
a41c6c53 | 4579 | { |
b9404c99 | 4580 | emit_insn (gen_cmpmem_long (op0, op1, convert_to_mode (Pmode, len, 1))); |
02887425 | 4581 | emit_insn (gen_cmpint (target, ccreg)); |
a41c6c53 | 4582 | } |
a41c6c53 UW |
4583 | else |
4584 | { | |
4585 | rtx addr0, addr1, count, blocks, temp; | |
19f8b229 TS |
4586 | rtx_code_label *loop_start_label = gen_label_rtx (); |
4587 | rtx_code_label *loop_end_label = gen_label_rtx (); | |
4588 | rtx_code_label *end_label = gen_label_rtx (); | |
ef4bddc2 | 4589 | machine_mode mode; |
a41c6c53 UW |
4590 | |
4591 | mode = GET_MODE (len); | |
4592 | if (mode == VOIDmode) | |
b9404c99 | 4593 | mode = Pmode; |
a41c6c53 | 4594 | |
a41c6c53 UW |
4595 | addr0 = gen_reg_rtx (Pmode); |
4596 | addr1 = gen_reg_rtx (Pmode); | |
4597 | count = gen_reg_rtx (mode); | |
4598 | blocks = gen_reg_rtx (mode); | |
4599 | ||
4600 | convert_move (count, len, 1); | |
c7453384 | 4601 | emit_cmp_and_jump_insns (count, const0_rtx, |
a41c6c53 UW |
4602 | EQ, NULL_RTX, mode, 1, end_label); |
4603 | ||
4604 | emit_move_insn (addr0, force_operand (XEXP (op0, 0), NULL_RTX)); | |
4605 | emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX)); | |
4606 | op0 = change_address (op0, VOIDmode, addr0); | |
4607 | op1 = change_address (op1, VOIDmode, addr1); | |
c7453384 | 4608 | |
bbbbb16a ILT |
4609 | temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1, |
4610 | OPTAB_DIRECT); | |
a41c6c53 UW |
4611 | if (temp != count) |
4612 | emit_move_insn (count, temp); | |
4613 | ||
bbbbb16a ILT |
4614 | temp = expand_binop (mode, lshr_optab, count, GEN_INT (8), blocks, 1, |
4615 | OPTAB_DIRECT); | |
a41c6c53 UW |
4616 | if (temp != blocks) |
4617 | emit_move_insn (blocks, temp); | |
4618 | ||
6de9cd9a DN |
4619 | emit_cmp_and_jump_insns (blocks, const0_rtx, |
4620 | EQ, NULL_RTX, mode, 1, loop_end_label); | |
70315fcd SB |
4621 | |
4622 | emit_label (loop_start_label); | |
a41c6c53 | 4623 | |
adfa3cd3 AK |
4624 | if (TARGET_Z10 |
4625 | && (GET_CODE (len) != CONST_INT || INTVAL (len) > 512)) | |
4626 | { | |
4627 | rtx prefetch; | |
4628 | ||
4629 | /* Issue a read prefetch for the +2 cache line of operand 1. */ | |
4630 | prefetch = gen_prefetch (gen_rtx_PLUS (Pmode, addr0, GEN_INT (512)), | |
4631 | const0_rtx, const0_rtx); | |
4632 | emit_insn (prefetch); | |
4633 | PREFETCH_SCHEDULE_BARRIER_P (prefetch) = true; | |
4634 | ||
4635 | /* Issue a read prefetch for the +2 cache line of operand 2. */ | |
4636 | prefetch = gen_prefetch (gen_rtx_PLUS (Pmode, addr1, GEN_INT (512)), | |
4637 | const0_rtx, const0_rtx); | |
4638 | emit_insn (prefetch); | |
4639 | PREFETCH_SCHEDULE_BARRIER_P (prefetch) = true; | |
4640 | } | |
4641 | ||
b9404c99 | 4642 | emit_insn (gen_cmpmem_short (op0, op1, GEN_INT (255))); |
5b022de5 | 4643 | temp = gen_rtx_NE (VOIDmode, ccreg, const0_rtx); |
c7453384 | 4644 | temp = gen_rtx_IF_THEN_ELSE (VOIDmode, temp, |
a41c6c53 | 4645 | gen_rtx_LABEL_REF (VOIDmode, end_label), pc_rtx); |
f7df4a84 | 4646 | temp = gen_rtx_SET (pc_rtx, temp); |
a41c6c53 UW |
4647 | emit_jump_insn (temp); |
4648 | ||
c7453384 | 4649 | s390_load_address (addr0, |
a41c6c53 | 4650 | gen_rtx_PLUS (Pmode, addr0, GEN_INT (256))); |
c7453384 | 4651 | s390_load_address (addr1, |
a41c6c53 | 4652 | gen_rtx_PLUS (Pmode, addr1, GEN_INT (256))); |
c7453384 | 4653 | |
bbbbb16a ILT |
4654 | temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1, |
4655 | OPTAB_DIRECT); | |
a41c6c53 UW |
4656 | if (temp != blocks) |
4657 | emit_move_insn (blocks, temp); | |
4658 | ||
6de9cd9a DN |
4659 | emit_cmp_and_jump_insns (blocks, const0_rtx, |
4660 | EQ, NULL_RTX, mode, 1, loop_end_label); | |
70315fcd SB |
4661 | |
4662 | emit_jump (loop_start_label); | |
6de9cd9a | 4663 | emit_label (loop_end_label); |
a41c6c53 | 4664 | |
38899e29 | 4665 | emit_insn (gen_cmpmem_short (op0, op1, |
b9404c99 | 4666 | convert_to_mode (Pmode, count, 1))); |
a41c6c53 UW |
4667 | emit_label (end_label); |
4668 | ||
02887425 | 4669 | emit_insn (gen_cmpint (target, ccreg)); |
a41c6c53 | 4670 | } |
367d32f3 | 4671 | return true; |
a41c6c53 UW |
4672 | } |
4673 | ||
085261c8 AK |
4674 | /* Emit a conditional jump to LABEL for condition code mask MASK using |
4675 | comparsion operator COMPARISON. Return the emitted jump insn. */ | |
4676 | ||
4677 | static rtx | |
4678 | s390_emit_ccraw_jump (HOST_WIDE_INT mask, enum rtx_code comparison, rtx label) | |
4679 | { | |
4680 | rtx temp; | |
4681 | ||
4682 | gcc_assert (comparison == EQ || comparison == NE); | |
4683 | gcc_assert (mask > 0 && mask < 15); | |
4684 | ||
4685 | temp = gen_rtx_fmt_ee (comparison, VOIDmode, | |
4686 | gen_rtx_REG (CCRAWmode, CC_REGNUM), GEN_INT (mask)); | |
4687 | temp = gen_rtx_IF_THEN_ELSE (VOIDmode, temp, | |
4688 | gen_rtx_LABEL_REF (VOIDmode, label), pc_rtx); | |
4689 | temp = gen_rtx_SET (pc_rtx, temp); | |
4690 | return emit_jump_insn (temp); | |
4691 | } | |
4692 | ||
4693 | /* Emit the instructions to implement strlen of STRING and store the | |
4694 | result in TARGET. The string has the known ALIGNMENT. This | |
4695 | version uses vector instructions and is therefore not appropriate | |
4696 | for targets prior to z13. */ | |
4697 | ||
4698 | void | |
4699 | s390_expand_vec_strlen (rtx target, rtx string, rtx alignment) | |
4700 | { | |
4701 | int very_unlikely = REG_BR_PROB_BASE / 100 - 1; | |
4702 | int very_likely = REG_BR_PROB_BASE - 1; | |
4703 | rtx highest_index_to_load_reg = gen_reg_rtx (Pmode); | |
4704 | rtx str_reg = gen_reg_rtx (V16QImode); | |
4705 | rtx str_addr_base_reg = gen_reg_rtx (Pmode); | |
4706 | rtx str_idx_reg = gen_reg_rtx (Pmode); | |
4707 | rtx result_reg = gen_reg_rtx (V16QImode); | |
4708 | rtx is_aligned_label = gen_label_rtx (); | |
4709 | rtx into_loop_label = NULL_RTX; | |
4710 | rtx loop_start_label = gen_label_rtx (); | |
4711 | rtx temp; | |
4712 | rtx len = gen_reg_rtx (QImode); | |
4713 | rtx cond; | |
4714 | ||
4715 | s390_load_address (str_addr_base_reg, XEXP (string, 0)); | |
4716 | emit_move_insn (str_idx_reg, const0_rtx); | |
4717 | ||
4718 | if (INTVAL (alignment) < 16) | |
4719 | { | |
4720 | /* Check whether the address happens to be aligned properly so | |
4721 | jump directly to the aligned loop. */ | |
4722 | emit_cmp_and_jump_insns (gen_rtx_AND (Pmode, | |
4723 | str_addr_base_reg, GEN_INT (15)), | |
4724 | const0_rtx, EQ, NULL_RTX, | |
4725 | Pmode, 1, is_aligned_label); | |
4726 | ||
4727 | temp = gen_reg_rtx (Pmode); | |
4728 | temp = expand_binop (Pmode, and_optab, str_addr_base_reg, | |
4729 | GEN_INT (15), temp, 1, OPTAB_DIRECT); | |
4730 | gcc_assert (REG_P (temp)); | |
4731 | highest_index_to_load_reg = | |
4732 | expand_binop (Pmode, sub_optab, GEN_INT (15), temp, | |
4733 | highest_index_to_load_reg, 1, OPTAB_DIRECT); | |
4734 | gcc_assert (REG_P (highest_index_to_load_reg)); | |
4735 | emit_insn (gen_vllv16qi (str_reg, | |
4736 | convert_to_mode (SImode, highest_index_to_load_reg, 1), | |
4737 | gen_rtx_MEM (BLKmode, str_addr_base_reg))); | |
4738 | ||
4739 | into_loop_label = gen_label_rtx (); | |
4740 | s390_emit_jump (into_loop_label, NULL_RTX); | |
4741 | emit_barrier (); | |
4742 | } | |
4743 | ||
4744 | emit_label (is_aligned_label); | |
4745 | LABEL_NUSES (is_aligned_label) = INTVAL (alignment) < 16 ? 2 : 1; | |
4746 | ||
4747 | /* Reaching this point we are only performing 16 bytes aligned | |
4748 | loads. */ | |
4749 | emit_move_insn (highest_index_to_load_reg, GEN_INT (15)); | |
4750 | ||
4751 | emit_label (loop_start_label); | |
4752 | LABEL_NUSES (loop_start_label) = 1; | |
4753 | ||
4754 | /* Load 16 bytes of the string into VR. */ | |
4755 | emit_move_insn (str_reg, | |
4756 | gen_rtx_MEM (V16QImode, | |
4757 | gen_rtx_PLUS (Pmode, str_idx_reg, | |
4758 | str_addr_base_reg))); | |
4759 | if (into_loop_label != NULL_RTX) | |
4760 | { | |
4761 | emit_label (into_loop_label); | |
4762 | LABEL_NUSES (into_loop_label) = 1; | |
4763 | } | |
4764 | ||
4765 | /* Increment string index by 16 bytes. */ | |
4766 | expand_binop (Pmode, add_optab, str_idx_reg, GEN_INT (16), | |
4767 | str_idx_reg, 1, OPTAB_DIRECT); | |
4768 | ||
4769 | emit_insn (gen_vec_vfenesv16qi (result_reg, str_reg, str_reg, | |
4770 | GEN_INT (VSTRING_FLAG_ZS | VSTRING_FLAG_CS))); | |
4771 | ||
4772 | add_int_reg_note (s390_emit_ccraw_jump (8, NE, loop_start_label), | |
4773 | REG_BR_PROB, very_likely); | |
4774 | emit_insn (gen_vec_extractv16qi (len, result_reg, GEN_INT (7))); | |
4775 | ||
4776 | /* If the string pointer wasn't aligned we have loaded less then 16 | |
4777 | bytes and the remaining bytes got filled with zeros (by vll). | |
4778 | Now we have to check whether the resulting index lies within the | |
4779 | bytes actually part of the string. */ | |
4780 | ||
4781 | cond = s390_emit_compare (GT, convert_to_mode (Pmode, len, 1), | |
4782 | highest_index_to_load_reg); | |
4783 | s390_load_address (highest_index_to_load_reg, | |
4784 | gen_rtx_PLUS (Pmode, highest_index_to_load_reg, | |
4785 | const1_rtx)); | |
4786 | if (TARGET_64BIT) | |
4787 | emit_insn (gen_movdicc (str_idx_reg, cond, | |
4788 | highest_index_to_load_reg, str_idx_reg)); | |
4789 | else | |
4790 | emit_insn (gen_movsicc (str_idx_reg, cond, | |
4791 | highest_index_to_load_reg, str_idx_reg)); | |
4792 | ||
4793 | add_int_reg_note (s390_emit_jump (is_aligned_label, cond), REG_BR_PROB, | |
4794 | very_unlikely); | |
4795 | ||
4796 | expand_binop (Pmode, add_optab, str_idx_reg, | |
4797 | GEN_INT (-16), str_idx_reg, 1, OPTAB_DIRECT); | |
4798 | /* FIXME: len is already zero extended - so avoid the llgcr emitted | |
4799 | here. */ | |
4800 | temp = expand_binop (Pmode, add_optab, str_idx_reg, | |
4801 | convert_to_mode (Pmode, len, 1), | |
4802 | target, 1, OPTAB_DIRECT); | |
4803 | if (temp != target) | |
4804 | emit_move_insn (target, temp); | |
4805 | } | |
5d880bd2 UW |
4806 | |
4807 | /* Expand conditional increment or decrement using alc/slb instructions. | |
4808 | Should generate code setting DST to either SRC or SRC + INCREMENT, | |
4809 | depending on the result of the comparison CMP_OP0 CMP_CODE CMP_OP1. | |
00bda920 AK |
4810 | Returns true if successful, false otherwise. |
4811 | ||
4812 | That makes it possible to implement some if-constructs without jumps e.g.: | |
4813 | (borrow = CC0 | CC1 and carry = CC2 | CC3) | |
4814 | unsigned int a, b, c; | |
4815 | if (a < b) c++; -> CCU b > a -> CC2; c += carry; | |
4816 | if (a < b) c--; -> CCL3 a - b -> borrow; c -= borrow; | |
4817 | if (a <= b) c++; -> CCL3 b - a -> borrow; c += carry; | |
4818 | if (a <= b) c--; -> CCU a <= b -> borrow; c -= borrow; | |
4819 | ||
4820 | Checks for EQ and NE with a nonzero value need an additional xor e.g.: | |
4821 | if (a == b) c++; -> CCL3 a ^= b; 0 - a -> borrow; c += carry; | |
4822 | if (a == b) c--; -> CCU a ^= b; a <= 0 -> CC0 | CC1; c -= borrow; | |
4823 | if (a != b) c++; -> CCU a ^= b; a > 0 -> CC2; c += carry; | |
4824 | if (a != b) c--; -> CCL3 a ^= b; 0 - a -> borrow; c -= borrow; */ | |
5d880bd2 UW |
4825 | |
4826 | bool | |
4827 | s390_expand_addcc (enum rtx_code cmp_code, rtx cmp_op0, rtx cmp_op1, | |
4828 | rtx dst, rtx src, rtx increment) | |
4829 | { | |
ef4bddc2 RS |
4830 | machine_mode cmp_mode; |
4831 | machine_mode cc_mode; | |
5d880bd2 UW |
4832 | rtx op_res; |
4833 | rtx insn; | |
4834 | rtvec p; | |
8d933e31 | 4835 | int ret; |
5d880bd2 UW |
4836 | |
4837 | if ((GET_MODE (cmp_op0) == SImode || GET_MODE (cmp_op0) == VOIDmode) | |
4838 | && (GET_MODE (cmp_op1) == SImode || GET_MODE (cmp_op1) == VOIDmode)) | |
4839 | cmp_mode = SImode; | |
4840 | else if ((GET_MODE (cmp_op0) == DImode || GET_MODE (cmp_op0) == VOIDmode) | |
4841 | && (GET_MODE (cmp_op1) == DImode || GET_MODE (cmp_op1) == VOIDmode)) | |
4842 | cmp_mode = DImode; | |
4843 | else | |
4844 | return false; | |
4845 | ||
4846 | /* Try ADD LOGICAL WITH CARRY. */ | |
4847 | if (increment == const1_rtx) | |
4848 | { | |
4849 | /* Determine CC mode to use. */ | |
4850 | if (cmp_code == EQ || cmp_code == NE) | |
4851 | { | |
4852 | if (cmp_op1 != const0_rtx) | |
4853 | { | |
4854 | cmp_op0 = expand_simple_binop (cmp_mode, XOR, cmp_op0, cmp_op1, | |
4855 | NULL_RTX, 0, OPTAB_WIDEN); | |
4856 | cmp_op1 = const0_rtx; | |
4857 | } | |
4858 | ||
4859 | cmp_code = cmp_code == EQ ? LEU : GTU; | |
4860 | } | |
4861 | ||
4862 | if (cmp_code == LTU || cmp_code == LEU) | |
4863 | { | |
4864 | rtx tem = cmp_op0; | |
4865 | cmp_op0 = cmp_op1; | |
4866 | cmp_op1 = tem; | |
4867 | cmp_code = swap_condition (cmp_code); | |
4868 | } | |
4869 | ||
4870 | switch (cmp_code) | |
4871 | { | |
4872 | case GTU: | |
4873 | cc_mode = CCUmode; | |
4874 | break; | |
4875 | ||
4876 | case GEU: | |
4877 | cc_mode = CCL3mode; | |
4878 | break; | |
4879 | ||
4880 | default: | |
4881 | return false; | |
4882 | } | |
4883 | ||
4884 | /* Emit comparison instruction pattern. */ | |
4885 | if (!register_operand (cmp_op0, cmp_mode)) | |
4886 | cmp_op0 = force_reg (cmp_mode, cmp_op0); | |
4887 | ||
f7df4a84 | 4888 | insn = gen_rtx_SET (gen_rtx_REG (cc_mode, CC_REGNUM), |
5d880bd2 UW |
4889 | gen_rtx_COMPARE (cc_mode, cmp_op0, cmp_op1)); |
4890 | /* We use insn_invalid_p here to add clobbers if required. */ | |
57ac4c34 | 4891 | ret = insn_invalid_p (emit_insn (insn), false); |
8d933e31 | 4892 | gcc_assert (!ret); |
5d880bd2 UW |
4893 | |
4894 | /* Emit ALC instruction pattern. */ | |
4895 | op_res = gen_rtx_fmt_ee (cmp_code, GET_MODE (dst), | |
4896 | gen_rtx_REG (cc_mode, CC_REGNUM), | |
4897 | const0_rtx); | |
4898 | ||
4899 | if (src != const0_rtx) | |
4900 | { | |
4901 | if (!register_operand (src, GET_MODE (dst))) | |
4902 | src = force_reg (GET_MODE (dst), src); | |
4903 | ||
a94a76a7 UW |
4904 | op_res = gen_rtx_PLUS (GET_MODE (dst), op_res, src); |
4905 | op_res = gen_rtx_PLUS (GET_MODE (dst), op_res, const0_rtx); | |
5d880bd2 UW |
4906 | } |
4907 | ||
4908 | p = rtvec_alloc (2); | |
f4aa3848 | 4909 | RTVEC_ELT (p, 0) = |
f7df4a84 | 4910 | gen_rtx_SET (dst, op_res); |
f4aa3848 | 4911 | RTVEC_ELT (p, 1) = |
5d880bd2 UW |
4912 | gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM)); |
4913 | emit_insn (gen_rtx_PARALLEL (VOIDmode, p)); | |
4914 | ||
4915 | return true; | |
4916 | } | |
4917 | ||
4918 | /* Try SUBTRACT LOGICAL WITH BORROW. */ | |
4919 | if (increment == constm1_rtx) | |
4920 | { | |
4921 | /* Determine CC mode to use. */ | |
4922 | if (cmp_code == EQ || cmp_code == NE) | |
4923 | { | |
4924 | if (cmp_op1 != const0_rtx) | |
4925 | { | |
4926 | cmp_op0 = expand_simple_binop (cmp_mode, XOR, cmp_op0, cmp_op1, | |
4927 | NULL_RTX, 0, OPTAB_WIDEN); | |
4928 | cmp_op1 = const0_rtx; | |
4929 | } | |
4930 | ||
4931 | cmp_code = cmp_code == EQ ? LEU : GTU; | |
4932 | } | |
4933 | ||
4934 | if (cmp_code == GTU || cmp_code == GEU) | |
4935 | { | |
4936 | rtx tem = cmp_op0; | |
4937 | cmp_op0 = cmp_op1; | |
4938 | cmp_op1 = tem; | |
4939 | cmp_code = swap_condition (cmp_code); | |
4940 | } | |
4941 | ||
4942 | switch (cmp_code) | |
4943 | { | |
4944 | case LEU: | |
4945 | cc_mode = CCUmode; | |
4946 | break; | |
4947 | ||
4948 | case LTU: | |
4949 | cc_mode = CCL3mode; | |
4950 | break; | |
4951 | ||
4952 | default: | |
4953 | return false; | |
4954 | } | |
4955 | ||
4956 | /* Emit comparison instruction pattern. */ | |
4957 | if (!register_operand (cmp_op0, cmp_mode)) | |
4958 | cmp_op0 = force_reg (cmp_mode, cmp_op0); | |
4959 | ||
f7df4a84 | 4960 | insn = gen_rtx_SET (gen_rtx_REG (cc_mode, CC_REGNUM), |
5d880bd2 UW |
4961 | gen_rtx_COMPARE (cc_mode, cmp_op0, cmp_op1)); |
4962 | /* We use insn_invalid_p here to add clobbers if required. */ | |
57ac4c34 | 4963 | ret = insn_invalid_p (emit_insn (insn), false); |
8d933e31 | 4964 | gcc_assert (!ret); |
5d880bd2 UW |
4965 | |
4966 | /* Emit SLB instruction pattern. */ | |
4967 | if (!register_operand (src, GET_MODE (dst))) | |
4968 | src = force_reg (GET_MODE (dst), src); | |
4969 | ||
f4aa3848 AK |
4970 | op_res = gen_rtx_MINUS (GET_MODE (dst), |
4971 | gen_rtx_MINUS (GET_MODE (dst), src, const0_rtx), | |
4972 | gen_rtx_fmt_ee (cmp_code, GET_MODE (dst), | |
4973 | gen_rtx_REG (cc_mode, CC_REGNUM), | |
5d880bd2 UW |
4974 | const0_rtx)); |
4975 | p = rtvec_alloc (2); | |
f4aa3848 | 4976 | RTVEC_ELT (p, 0) = |
f7df4a84 | 4977 | gen_rtx_SET (dst, op_res); |
f4aa3848 | 4978 | RTVEC_ELT (p, 1) = |
5d880bd2 UW |
4979 | gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM)); |
4980 | emit_insn (gen_rtx_PARALLEL (VOIDmode, p)); | |
4981 | ||
4982 | return true; | |
4983 | } | |
4984 | ||
4985 | return false; | |
4986 | } | |
4987 | ||
963fc8d0 | 4988 | /* Expand code for the insv template. Return true if successful. */ |
6fa05db6 | 4989 | |
963fc8d0 | 4990 | bool |
6fa05db6 AS |
4991 | s390_expand_insv (rtx dest, rtx op1, rtx op2, rtx src) |
4992 | { | |
4993 | int bitsize = INTVAL (op1); | |
4994 | int bitpos = INTVAL (op2); | |
ef4bddc2 RS |
4995 | machine_mode mode = GET_MODE (dest); |
4996 | machine_mode smode; | |
78ce265b RH |
4997 | int smode_bsize, mode_bsize; |
4998 | rtx op, clobber; | |
6fa05db6 | 4999 | |
a9d46e32 | 5000 | if (bitsize + bitpos > GET_MODE_BITSIZE (mode)) |
03ed99a8 AK |
5001 | return false; |
5002 | ||
78ce265b RH |
5003 | /* Generate INSERT IMMEDIATE (IILL et al). */ |
5004 | /* (set (ze (reg)) (const_int)). */ | |
5005 | if (TARGET_ZARCH | |
5006 | && register_operand (dest, word_mode) | |
5007 | && (bitpos % 16) == 0 | |
5008 | && (bitsize % 16) == 0 | |
5009 | && const_int_operand (src, VOIDmode)) | |
963fc8d0 | 5010 | { |
78ce265b RH |
5011 | HOST_WIDE_INT val = INTVAL (src); |
5012 | int regpos = bitpos + bitsize; | |
963fc8d0 | 5013 | |
78ce265b RH |
5014 | while (regpos > bitpos) |
5015 | { | |
ef4bddc2 | 5016 | machine_mode putmode; |
78ce265b RH |
5017 | int putsize; |
5018 | ||
5019 | if (TARGET_EXTIMM && (regpos % 32 == 0) && (regpos >= bitpos + 32)) | |
5020 | putmode = SImode; | |
5021 | else | |
5022 | putmode = HImode; | |
963fc8d0 | 5023 | |
78ce265b RH |
5024 | putsize = GET_MODE_BITSIZE (putmode); |
5025 | regpos -= putsize; | |
5026 | emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode, dest, | |
5027 | GEN_INT (putsize), | |
5028 | GEN_INT (regpos)), | |
5029 | gen_int_mode (val, putmode)); | |
5030 | val >>= putsize; | |
5031 | } | |
5032 | gcc_assert (regpos == bitpos); | |
963fc8d0 AK |
5033 | return true; |
5034 | } | |
5035 | ||
78ce265b RH |
5036 | smode = smallest_mode_for_size (bitsize, MODE_INT); |
5037 | smode_bsize = GET_MODE_BITSIZE (smode); | |
5038 | mode_bsize = GET_MODE_BITSIZE (mode); | |
6fa05db6 | 5039 | |
78ce265b | 5040 | /* Generate STORE CHARACTERS UNDER MASK (STCM et al). */ |
6fa05db6 | 5041 | if (bitpos == 0 |
78ce265b RH |
5042 | && (bitsize % BITS_PER_UNIT) == 0 |
5043 | && MEM_P (dest) | |
6fa05db6 AS |
5044 | && (register_operand (src, word_mode) |
5045 | || const_int_operand (src, VOIDmode))) | |
5046 | { | |
5047 | /* Emit standard pattern if possible. */ | |
78ce265b RH |
5048 | if (smode_bsize == bitsize) |
5049 | { | |
5050 | emit_move_insn (adjust_address (dest, smode, 0), | |
5051 | gen_lowpart (smode, src)); | |
5052 | return true; | |
5053 | } | |
6fa05db6 AS |
5054 | |
5055 | /* (set (ze (mem)) (const_int)). */ | |
5056 | else if (const_int_operand (src, VOIDmode)) | |
5057 | { | |
5058 | int size = bitsize / BITS_PER_UNIT; | |
78ce265b RH |
5059 | rtx src_mem = adjust_address (force_const_mem (word_mode, src), |
5060 | BLKmode, | |
5061 | UNITS_PER_WORD - size); | |
6fa05db6 AS |
5062 | |
5063 | dest = adjust_address (dest, BLKmode, 0); | |
f5541398 | 5064 | set_mem_size (dest, size); |
6fa05db6 | 5065 | s390_expand_movmem (dest, src_mem, GEN_INT (size)); |
78ce265b | 5066 | return true; |
6fa05db6 | 5067 | } |
f4aa3848 | 5068 | |
6fa05db6 AS |
5069 | /* (set (ze (mem)) (reg)). */ |
5070 | else if (register_operand (src, word_mode)) | |
5071 | { | |
78ce265b | 5072 | if (bitsize <= 32) |
6fa05db6 AS |
5073 | emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode, dest, op1, |
5074 | const0_rtx), src); | |
5075 | else | |
5076 | { | |
5077 | /* Emit st,stcmh sequence. */ | |
78ce265b | 5078 | int stcmh_width = bitsize - 32; |
6fa05db6 AS |
5079 | int size = stcmh_width / BITS_PER_UNIT; |
5080 | ||
f4aa3848 | 5081 | emit_move_insn (adjust_address (dest, SImode, size), |
6fa05db6 | 5082 | gen_lowpart (SImode, src)); |
f5541398 | 5083 | set_mem_size (dest, size); |
78ce265b RH |
5084 | emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode, dest, |
5085 | GEN_INT (stcmh_width), | |
5086 | const0_rtx), | |
5087 | gen_rtx_LSHIFTRT (word_mode, src, GEN_INT (32))); | |
6fa05db6 | 5088 | } |
78ce265b | 5089 | return true; |
6fa05db6 | 5090 | } |
78ce265b | 5091 | } |
6fa05db6 | 5092 | |
78ce265b RH |
5093 | /* Generate INSERT CHARACTERS UNDER MASK (IC, ICM et al). */ |
5094 | if ((bitpos % BITS_PER_UNIT) == 0 | |
5095 | && (bitsize % BITS_PER_UNIT) == 0 | |
5096 | && (bitpos & 32) == ((bitpos + bitsize - 1) & 32) | |
5097 | && MEM_P (src) | |
5098 | && (mode == DImode || mode == SImode) | |
5099 | && register_operand (dest, mode)) | |
5100 | { | |
5101 | /* Emit a strict_low_part pattern if possible. */ | |
5102 | if (smode_bsize == bitsize && bitpos == mode_bsize - smode_bsize) | |
5103 | { | |
5104 | op = gen_rtx_STRICT_LOW_PART (VOIDmode, gen_lowpart (smode, dest)); | |
f7df4a84 | 5105 | op = gen_rtx_SET (op, gen_lowpart (smode, src)); |
78ce265b RH |
5106 | clobber = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM)); |
5107 | emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clobber))); | |
5108 | return true; | |
5109 | } | |
5110 | ||
5111 | /* ??? There are more powerful versions of ICM that are not | |
5112 | completely represented in the md file. */ | |
6fa05db6 AS |
5113 | } |
5114 | ||
78ce265b RH |
5115 | /* For z10, generate ROTATE THEN INSERT SELECTED BITS (RISBG et al). */ |
5116 | if (TARGET_Z10 && (mode == DImode || mode == SImode)) | |
6fa05db6 | 5117 | { |
ef4bddc2 | 5118 | machine_mode mode_s = GET_MODE (src); |
6fa05db6 | 5119 | |
78ce265b | 5120 | if (mode_s == VOIDmode) |
6fa05db6 | 5121 | { |
78ce265b RH |
5122 | /* Assume const_int etc already in the proper mode. */ |
5123 | src = force_reg (mode, src); | |
5124 | } | |
5125 | else if (mode_s != mode) | |
5126 | { | |
5127 | gcc_assert (GET_MODE_BITSIZE (mode_s) >= bitsize); | |
5128 | src = force_reg (mode_s, src); | |
5129 | src = gen_lowpart (mode, src); | |
5130 | } | |
6fa05db6 | 5131 | |
0d8e4dac | 5132 | op = gen_rtx_ZERO_EXTRACT (mode, dest, op1, op2), |
f7df4a84 | 5133 | op = gen_rtx_SET (op, src); |
22ac2c2f AK |
5134 | |
5135 | if (!TARGET_ZEC12) | |
5136 | { | |
5137 | clobber = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM)); | |
5138 | op = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clobber)); | |
5139 | } | |
5140 | emit_insn (op); | |
6fa05db6 | 5141 | |
6fa05db6 AS |
5142 | return true; |
5143 | } | |
5144 | ||
5145 | return false; | |
5146 | } | |
5d880bd2 | 5147 | |
45d18331 AS |
5148 | /* A subroutine of s390_expand_cs_hqi and s390_expand_atomic which returns a |
5149 | register that holds VAL of mode MODE shifted by COUNT bits. */ | |
3093f076 AS |
5150 | |
5151 | static inline rtx | |
ef4bddc2 | 5152 | s390_expand_mask_and_shift (rtx val, machine_mode mode, rtx count) |
3093f076 AS |
5153 | { |
5154 | val = expand_simple_binop (SImode, AND, val, GEN_INT (GET_MODE_MASK (mode)), | |
5155 | NULL_RTX, 1, OPTAB_DIRECT); | |
f4aa3848 | 5156 | return expand_simple_binop (SImode, ASHIFT, val, count, |
3093f076 AS |
5157 | NULL_RTX, 1, OPTAB_DIRECT); |
5158 | } | |
5159 | ||
085261c8 AK |
5160 | /* Generate a vector comparison COND of CMP_OP1 and CMP_OP2 and store |
5161 | the result in TARGET. */ | |
5162 | ||
5163 | void | |
5164 | s390_expand_vec_compare (rtx target, enum rtx_code cond, | |
5165 | rtx cmp_op1, rtx cmp_op2) | |
5166 | { | |
5167 | machine_mode mode = GET_MODE (target); | |
5168 | bool neg_p = false, swap_p = false; | |
5169 | rtx tmp; | |
5170 | ||
5171 | if (GET_MODE (cmp_op1) == V2DFmode) | |
5172 | { | |
5173 | switch (cond) | |
5174 | { | |
5175 | /* NE a != b -> !(a == b) */ | |
5176 | case NE: cond = EQ; neg_p = true; break; | |
5177 | /* UNGT a u> b -> !(b >= a) */ | |
5178 | case UNGT: cond = GE; neg_p = true; swap_p = true; break; | |
5179 | /* UNGE a u>= b -> !(b > a) */ | |
5180 | case UNGE: cond = GT; neg_p = true; swap_p = true; break; | |
5181 | /* LE: a <= b -> b >= a */ | |
5182 | case LE: cond = GE; swap_p = true; break; | |
5183 | /* UNLE: a u<= b -> !(a > b) */ | |
5184 | case UNLE: cond = GT; neg_p = true; break; | |
5185 | /* LT: a < b -> b > a */ | |
5186 | case LT: cond = GT; swap_p = true; break; | |
5187 | /* UNLT: a u< b -> !(a >= b) */ | |
5188 | case UNLT: cond = GE; neg_p = true; break; | |
5189 | case UNEQ: | |
5190 | emit_insn (gen_vec_cmpuneqv2df (target, cmp_op1, cmp_op2)); | |
5191 | return; | |
5192 | case LTGT: | |
5193 | emit_insn (gen_vec_cmpltgtv2df (target, cmp_op1, cmp_op2)); | |
5194 | return; | |
5195 | case ORDERED: | |
5196 | emit_insn (gen_vec_orderedv2df (target, cmp_op1, cmp_op2)); | |
5197 | return; | |
5198 | case UNORDERED: | |
5199 | emit_insn (gen_vec_unorderedv2df (target, cmp_op1, cmp_op2)); | |
5200 | return; | |
5201 | default: break; | |
5202 | } | |
5203 | } | |
5204 | else | |
5205 | { | |
5206 | switch (cond) | |
5207 | { | |
5208 | /* NE: a != b -> !(a == b) */ | |
5209 | case NE: cond = EQ; neg_p = true; break; | |
5210 | /* GE: a >= b -> !(b > a) */ | |
5211 | case GE: cond = GT; neg_p = true; swap_p = true; break; | |
5212 | /* GEU: a >= b -> !(b > a) */ | |
5213 | case GEU: cond = GTU; neg_p = true; swap_p = true; break; | |
5214 | /* LE: a <= b -> !(a > b) */ | |
5215 | case LE: cond = GT; neg_p = true; break; | |
5216 | /* LEU: a <= b -> !(a > b) */ | |
5217 | case LEU: cond = GTU; neg_p = true; break; | |
5218 | /* LT: a < b -> b > a */ | |
5219 | case LT: cond = GT; swap_p = true; break; | |
5220 | /* LTU: a < b -> b > a */ | |
5221 | case LTU: cond = GTU; swap_p = true; break; | |
5222 | default: break; | |
5223 | } | |
5224 | } | |
5225 | ||
5226 | if (swap_p) | |
5227 | { | |
5228 | tmp = cmp_op1; cmp_op1 = cmp_op2; cmp_op2 = tmp; | |
5229 | } | |
5230 | ||
5231 | emit_insn (gen_rtx_SET (target, gen_rtx_fmt_ee (cond, | |
5232 | mode, | |
5233 | cmp_op1, cmp_op2))); | |
5234 | if (neg_p) | |
5235 | emit_insn (gen_rtx_SET (target, gen_rtx_NOT (mode, target))); | |
5236 | } | |
5237 | ||
5238 | /* Generate a vector comparison expression loading either elements of | |
5239 | THEN or ELS into TARGET depending on the comparison COND of CMP_OP1 | |
5240 | and CMP_OP2. */ | |
5241 | ||
5242 | void | |
5243 | s390_expand_vcond (rtx target, rtx then, rtx els, | |
5244 | enum rtx_code cond, rtx cmp_op1, rtx cmp_op2) | |
5245 | { | |
5246 | rtx tmp; | |
5247 | machine_mode result_mode; | |
5248 | rtx result_target; | |
5249 | ||
5250 | /* We always use an integral type vector to hold the comparison | |
5251 | result. */ | |
5252 | result_mode = GET_MODE (cmp_op1) == V2DFmode ? V2DImode : GET_MODE (cmp_op1); | |
5253 | result_target = gen_reg_rtx (result_mode); | |
5254 | ||
5255 | /* Alternatively this could be done by reload by lowering the cmp* | |
5256 | predicates. But it appears to be better for scheduling etc. to | |
5257 | have that in early. */ | |
5258 | if (!REG_P (cmp_op1)) | |
5259 | cmp_op1 = force_reg (GET_MODE (target), cmp_op1); | |
5260 | ||
5261 | if (!REG_P (cmp_op2)) | |
5262 | cmp_op2 = force_reg (GET_MODE (target), cmp_op2); | |
5263 | ||
5264 | s390_expand_vec_compare (result_target, cond, | |
5265 | cmp_op1, cmp_op2); | |
5266 | ||
5267 | /* If the results are supposed to be either -1 or 0 we are done | |
5268 | since this is what our compare instructions generate anyway. */ | |
5269 | if (constm1_operand (then, GET_MODE (then)) | |
5270 | && const0_operand (els, GET_MODE (els))) | |
5271 | { | |
5272 | emit_move_insn (target, gen_rtx_SUBREG (GET_MODE (target), | |
5273 | result_target, 0)); | |
5274 | return; | |
5275 | } | |
5276 | ||
5277 | /* Otherwise we will do a vsel afterwards. */ | |
5278 | /* This gets triggered e.g. | |
5279 | with gcc.c-torture/compile/pr53410-1.c */ | |
5280 | if (!REG_P (then)) | |
5281 | then = force_reg (GET_MODE (target), then); | |
5282 | ||
5283 | if (!REG_P (els)) | |
5284 | els = force_reg (GET_MODE (target), els); | |
5285 | ||
5286 | tmp = gen_rtx_fmt_ee (EQ, VOIDmode, | |
5287 | result_target, | |
5288 | CONST0_RTX (result_mode)); | |
5289 | ||
5290 | /* We compared the result against zero above so we have to swap then | |
5291 | and els here. */ | |
5292 | tmp = gen_rtx_IF_THEN_ELSE (GET_MODE (target), tmp, els, then); | |
5293 | ||
5294 | gcc_assert (GET_MODE (target) == GET_MODE (then)); | |
5295 | emit_insn (gen_rtx_SET (target, tmp)); | |
5296 | } | |
5297 | ||
5298 | /* Emit the RTX necessary to initialize the vector TARGET with values | |
5299 | in VALS. */ | |
5300 | void | |
5301 | s390_expand_vec_init (rtx target, rtx vals) | |
5302 | { | |
5303 | machine_mode mode = GET_MODE (target); | |
5304 | machine_mode inner_mode = GET_MODE_INNER (mode); | |
5305 | int n_elts = GET_MODE_NUNITS (mode); | |
5306 | bool all_same = true, all_regs = true, all_const_int = true; | |
5307 | rtx x; | |
5308 | int i; | |
5309 | ||
5310 | for (i = 0; i < n_elts; ++i) | |
5311 | { | |
5312 | x = XVECEXP (vals, 0, i); | |
5313 | ||
5314 | if (!CONST_INT_P (x)) | |
5315 | all_const_int = false; | |
5316 | ||
5317 | if (i > 0 && !rtx_equal_p (x, XVECEXP (vals, 0, 0))) | |
5318 | all_same = false; | |
5319 | ||
5320 | if (!REG_P (x)) | |
5321 | all_regs = false; | |
5322 | } | |
5323 | ||
5324 | /* Use vector gen mask or vector gen byte mask if possible. */ | |
5325 | if (all_same && all_const_int | |
5326 | && (XVECEXP (vals, 0, 0) == const0_rtx | |
5327 | || s390_contiguous_bitmask_vector_p (XVECEXP (vals, 0, 0), | |
5328 | NULL, NULL) | |
5329 | || s390_bytemask_vector_p (XVECEXP (vals, 0, 0), NULL))) | |
5330 | { | |
5331 | emit_insn (gen_rtx_SET (target, | |
5332 | gen_rtx_CONST_VECTOR (mode, XVEC (vals, 0)))); | |
5333 | return; | |
5334 | } | |
5335 | ||
5336 | if (all_same) | |
5337 | { | |
5338 | emit_insn (gen_rtx_SET (target, | |
5339 | gen_rtx_VEC_DUPLICATE (mode, | |
5340 | XVECEXP (vals, 0, 0)))); | |
5341 | return; | |
5342 | } | |
5343 | ||
5344 | if (all_regs && REG_P (target) && n_elts == 2 && inner_mode == DImode) | |
5345 | { | |
5346 | /* Use vector load pair. */ | |
5347 | emit_insn (gen_rtx_SET (target, | |
5348 | gen_rtx_VEC_CONCAT (mode, | |
5349 | XVECEXP (vals, 0, 0), | |
5350 | XVECEXP (vals, 0, 1)))); | |
5351 | return; | |
5352 | } | |
5353 | ||
5354 | /* We are about to set the vector elements one by one. Zero out the | |
5355 | full register first in order to help the data flow framework to | |
5356 | detect it as full VR set. */ | |
5357 | emit_insn (gen_rtx_SET (target, CONST0_RTX (mode))); | |
5358 | ||
5359 | /* Unfortunately the vec_init expander is not allowed to fail. So | |
5360 | we have to implement the fallback ourselves. */ | |
5361 | for (i = 0; i < n_elts; i++) | |
5362 | emit_insn (gen_rtx_SET (target, | |
5363 | gen_rtx_UNSPEC (mode, | |
5364 | gen_rtvec (3, XVECEXP (vals, 0, i), | |
5365 | GEN_INT (i), target), | |
5366 | UNSPEC_VEC_SET))); | |
5367 | } | |
5368 | ||
3093f076 | 5369 | /* Structure to hold the initial parameters for a compare_and_swap operation |
f4aa3848 | 5370 | in HImode and QImode. */ |
3093f076 AS |
5371 | |
5372 | struct alignment_context | |
5373 | { | |
f4aa3848 | 5374 | rtx memsi; /* SI aligned memory location. */ |
3093f076 AS |
5375 | rtx shift; /* Bit offset with regard to lsb. */ |
5376 | rtx modemask; /* Mask of the HQImode shifted by SHIFT bits. */ | |
5377 | rtx modemaski; /* ~modemask */ | |
6416ae7f | 5378 | bool aligned; /* True if memory is aligned, false else. */ |
3093f076 AS |
5379 | }; |
5380 | ||
45d18331 AS |
5381 | /* A subroutine of s390_expand_cs_hqi and s390_expand_atomic to initialize |
5382 | structure AC for transparent simplifying, if the memory alignment is known | |
5383 | to be at least 32bit. MEM is the memory location for the actual operation | |
5384 | and MODE its mode. */ | |
3093f076 AS |
5385 | |
5386 | static void | |
5387 | init_alignment_context (struct alignment_context *ac, rtx mem, | |
ef4bddc2 | 5388 | machine_mode mode) |
3093f076 AS |
5389 | { |
5390 | ac->shift = GEN_INT (GET_MODE_SIZE (SImode) - GET_MODE_SIZE (mode)); | |
5391 | ac->aligned = (MEM_ALIGN (mem) >= GET_MODE_BITSIZE (SImode)); | |
5392 | ||
5393 | if (ac->aligned) | |
5394 | ac->memsi = adjust_address (mem, SImode, 0); /* Memory is aligned. */ | |
5395 | else | |
5396 | { | |
5397 | /* Alignment is unknown. */ | |
5398 | rtx byteoffset, addr, align; | |
5399 | ||
5400 | /* Force the address into a register. */ | |
5401 | addr = force_reg (Pmode, XEXP (mem, 0)); | |
5402 | ||
5403 | /* Align it to SImode. */ | |
5404 | align = expand_simple_binop (Pmode, AND, addr, | |
5405 | GEN_INT (-GET_MODE_SIZE (SImode)), | |
5406 | NULL_RTX, 1, OPTAB_DIRECT); | |
5407 | /* Generate MEM. */ | |
5408 | ac->memsi = gen_rtx_MEM (SImode, align); | |
5409 | MEM_VOLATILE_P (ac->memsi) = MEM_VOLATILE_P (mem); | |
44d64274 | 5410 | set_mem_alias_set (ac->memsi, ALIAS_SET_MEMORY_BARRIER); |
3093f076 AS |
5411 | set_mem_align (ac->memsi, GET_MODE_BITSIZE (SImode)); |
5412 | ||
5413 | /* Calculate shiftcount. */ | |
5414 | byteoffset = expand_simple_binop (Pmode, AND, addr, | |
5415 | GEN_INT (GET_MODE_SIZE (SImode) - 1), | |
5416 | NULL_RTX, 1, OPTAB_DIRECT); | |
5417 | /* As we already have some offset, evaluate the remaining distance. */ | |
5418 | ac->shift = expand_simple_binop (SImode, MINUS, ac->shift, byteoffset, | |
5419 | NULL_RTX, 1, OPTAB_DIRECT); | |
3093f076 | 5420 | } |
78ce265b | 5421 | |
3093f076 | 5422 | /* Shift is the byte count, but we need the bitcount. */ |
78ce265b RH |
5423 | ac->shift = expand_simple_binop (SImode, ASHIFT, ac->shift, GEN_INT (3), |
5424 | NULL_RTX, 1, OPTAB_DIRECT); | |
5425 | ||
3093f076 | 5426 | /* Calculate masks. */ |
f4aa3848 | 5427 | ac->modemask = expand_simple_binop (SImode, ASHIFT, |
78ce265b RH |
5428 | GEN_INT (GET_MODE_MASK (mode)), |
5429 | ac->shift, NULL_RTX, 1, OPTAB_DIRECT); | |
5430 | ac->modemaski = expand_simple_unop (SImode, NOT, ac->modemask, | |
5431 | NULL_RTX, 1); | |
5432 | } | |
5433 | ||
5434 | /* A subroutine of s390_expand_cs_hqi. Insert INS into VAL. If possible, | |
5435 | use a single insv insn into SEQ2. Otherwise, put prep insns in SEQ1 and | |
5436 | perform the merge in SEQ2. */ | |
5437 | ||
5438 | static rtx | |
5439 | s390_two_part_insv (struct alignment_context *ac, rtx *seq1, rtx *seq2, | |
ef4bddc2 | 5440 | machine_mode mode, rtx val, rtx ins) |
78ce265b RH |
5441 | { |
5442 | rtx tmp; | |
5443 | ||
5444 | if (ac->aligned) | |
5445 | { | |
5446 | start_sequence (); | |
5447 | tmp = copy_to_mode_reg (SImode, val); | |
5448 | if (s390_expand_insv (tmp, GEN_INT (GET_MODE_BITSIZE (mode)), | |
5449 | const0_rtx, ins)) | |
5450 | { | |
5451 | *seq1 = NULL; | |
5452 | *seq2 = get_insns (); | |
5453 | end_sequence (); | |
5454 | return tmp; | |
5455 | } | |
5456 | end_sequence (); | |
5457 | } | |
5458 | ||
5459 | /* Failed to use insv. Generate a two part shift and mask. */ | |
5460 | start_sequence (); | |
5461 | tmp = s390_expand_mask_and_shift (ins, mode, ac->shift); | |
5462 | *seq1 = get_insns (); | |
5463 | end_sequence (); | |
5464 | ||
5465 | start_sequence (); | |
5466 | tmp = expand_simple_binop (SImode, IOR, tmp, val, NULL_RTX, 1, OPTAB_DIRECT); | |
5467 | *seq2 = get_insns (); | |
5468 | end_sequence (); | |
5469 | ||
5470 | return tmp; | |
3093f076 AS |
5471 | } |
5472 | ||
5473 | /* Expand an atomic compare and swap operation for HImode and QImode. MEM is | |
78ce265b RH |
5474 | the memory location, CMP the old value to compare MEM with and NEW_RTX the |
5475 | value to set if CMP == MEM. */ | |
3093f076 AS |
5476 | |
5477 | void | |
ef4bddc2 | 5478 | s390_expand_cs_hqi (machine_mode mode, rtx btarget, rtx vtarget, rtx mem, |
78ce265b | 5479 | rtx cmp, rtx new_rtx, bool is_weak) |
3093f076 AS |
5480 | { |
5481 | struct alignment_context ac; | |
4e1ffb63 | 5482 | rtx cmpv, newv, val, cc, seq0, seq1, seq2, seq3; |
3093f076 | 5483 | rtx res = gen_reg_rtx (SImode); |
19f8b229 | 5484 | rtx_code_label *csloop = NULL, *csend = NULL; |
3093f076 | 5485 | |
3093f076 AS |
5486 | gcc_assert (MEM_P (mem)); |
5487 | ||
5488 | init_alignment_context (&ac, mem, mode); | |
5489 | ||
3093f076 AS |
5490 | /* Load full word. Subsequent loads are performed by CS. */ |
5491 | val = expand_simple_binop (SImode, AND, ac.memsi, ac.modemaski, | |
5492 | NULL_RTX, 1, OPTAB_DIRECT); | |
5493 | ||
78ce265b RH |
5494 | /* Prepare insertions of cmp and new_rtx into the loaded value. When |
5495 | possible, we try to use insv to make this happen efficiently. If | |
5496 | that fails we'll generate code both inside and outside the loop. */ | |
5497 | cmpv = s390_two_part_insv (&ac, &seq0, &seq2, mode, val, cmp); | |
5498 | newv = s390_two_part_insv (&ac, &seq1, &seq3, mode, val, new_rtx); | |
5499 | ||
5500 | if (seq0) | |
5501 | emit_insn (seq0); | |
5502 | if (seq1) | |
5503 | emit_insn (seq1); | |
5504 | ||
3093f076 | 5505 | /* Start CS loop. */ |
78ce265b RH |
5506 | if (!is_weak) |
5507 | { | |
5508 | /* Begin assuming success. */ | |
5509 | emit_move_insn (btarget, const1_rtx); | |
5510 | ||
5511 | csloop = gen_label_rtx (); | |
5512 | csend = gen_label_rtx (); | |
5513 | emit_label (csloop); | |
5514 | } | |
5515 | ||
f4aa3848 | 5516 | /* val = "<mem>00..0<mem>" |
3093f076 | 5517 | * cmp = "00..0<cmp>00..0" |
f4aa3848 | 5518 | * new = "00..0<new>00..0" |
3093f076 AS |
5519 | */ |
5520 | ||
78ce265b RH |
5521 | emit_insn (seq2); |
5522 | emit_insn (seq3); | |
5523 | ||
5524 | cc = s390_emit_compare_and_swap (EQ, res, ac.memsi, cmpv, newv); | |
5525 | if (is_weak) | |
5526 | emit_insn (gen_cstorecc4 (btarget, cc, XEXP (cc, 0), XEXP (cc, 1))); | |
3093f076 | 5527 | else |
3093f076 | 5528 | { |
4e1ffb63 RH |
5529 | rtx tmp; |
5530 | ||
78ce265b RH |
5531 | /* Jump to end if we're done (likely?). */ |
5532 | s390_emit_jump (csend, cc); | |
5533 | ||
4e1ffb63 RH |
5534 | /* Check for changes outside mode, and loop internal if so. |
5535 | Arrange the moves so that the compare is adjacent to the | |
5536 | branch so that we can generate CRJ. */ | |
5537 | tmp = copy_to_reg (val); | |
5538 | force_expand_binop (SImode, and_optab, res, ac.modemaski, val, | |
5539 | 1, OPTAB_DIRECT); | |
5540 | cc = s390_emit_compare (NE, val, tmp); | |
78ce265b RH |
5541 | s390_emit_jump (csloop, cc); |
5542 | ||
5543 | /* Failed. */ | |
5544 | emit_move_insn (btarget, const0_rtx); | |
5545 | emit_label (csend); | |
3093f076 | 5546 | } |
f4aa3848 | 5547 | |
3093f076 | 5548 | /* Return the correct part of the bitfield. */ |
78ce265b RH |
5549 | convert_move (vtarget, expand_simple_binop (SImode, LSHIFTRT, res, ac.shift, |
5550 | NULL_RTX, 1, OPTAB_DIRECT), 1); | |
3093f076 AS |
5551 | } |
5552 | ||
45d18331 | 5553 | /* Expand an atomic operation CODE of mode MODE. MEM is the memory location |
ea2c620c | 5554 | and VAL the value to play with. If AFTER is true then store the value |
45d18331 AS |
5555 | MEM holds after the operation, if AFTER is false then store the value MEM |
5556 | holds before the operation. If TARGET is zero then discard that value, else | |
5557 | store it to TARGET. */ | |
5558 | ||
5559 | void | |
ef4bddc2 | 5560 | s390_expand_atomic (machine_mode mode, enum rtx_code code, |
45d18331 AS |
5561 | rtx target, rtx mem, rtx val, bool after) |
5562 | { | |
5563 | struct alignment_context ac; | |
5564 | rtx cmp; | |
0a2aaacc | 5565 | rtx new_rtx = gen_reg_rtx (SImode); |
45d18331 | 5566 | rtx orig = gen_reg_rtx (SImode); |
19f8b229 | 5567 | rtx_code_label *csloop = gen_label_rtx (); |
45d18331 AS |
5568 | |
5569 | gcc_assert (!target || register_operand (target, VOIDmode)); | |
5570 | gcc_assert (MEM_P (mem)); | |
5571 | ||
5572 | init_alignment_context (&ac, mem, mode); | |
5573 | ||
5574 | /* Shift val to the correct bit positions. | |
5575 | Preserve "icm", but prevent "ex icm". */ | |
5576 | if (!(ac.aligned && code == SET && MEM_P (val))) | |
5577 | val = s390_expand_mask_and_shift (val, mode, ac.shift); | |
5578 | ||
5579 | /* Further preparation insns. */ | |
5580 | if (code == PLUS || code == MINUS) | |
5581 | emit_move_insn (orig, val); | |
5582 | else if (code == MULT || code == AND) /* val = "11..1<val>11..1" */ | |
5583 | val = expand_simple_binop (SImode, XOR, val, ac.modemaski, | |
5584 | NULL_RTX, 1, OPTAB_DIRECT); | |
5585 | ||
5586 | /* Load full word. Subsequent loads are performed by CS. */ | |
5587 | cmp = force_reg (SImode, ac.memsi); | |
5588 | ||
5589 | /* Start CS loop. */ | |
5590 | emit_label (csloop); | |
0a2aaacc | 5591 | emit_move_insn (new_rtx, cmp); |
45d18331 AS |
5592 | |
5593 | /* Patch new with val at correct position. */ | |
5594 | switch (code) | |
5595 | { | |
5596 | case PLUS: | |
5597 | case MINUS: | |
0a2aaacc | 5598 | val = expand_simple_binop (SImode, code, new_rtx, orig, |
45d18331 AS |
5599 | NULL_RTX, 1, OPTAB_DIRECT); |
5600 | val = expand_simple_binop (SImode, AND, val, ac.modemask, | |
5601 | NULL_RTX, 1, OPTAB_DIRECT); | |
5602 | /* FALLTHRU */ | |
f4aa3848 | 5603 | case SET: |
45d18331 | 5604 | if (ac.aligned && MEM_P (val)) |
44e95206 AH |
5605 | store_bit_field (new_rtx, GET_MODE_BITSIZE (mode), 0, |
5606 | 0, 0, SImode, val); | |
45d18331 AS |
5607 | else |
5608 | { | |
0a2aaacc | 5609 | new_rtx = expand_simple_binop (SImode, AND, new_rtx, ac.modemaski, |
45d18331 | 5610 | NULL_RTX, 1, OPTAB_DIRECT); |
0a2aaacc | 5611 | new_rtx = expand_simple_binop (SImode, IOR, new_rtx, val, |
45d18331 AS |
5612 | NULL_RTX, 1, OPTAB_DIRECT); |
5613 | } | |
5614 | break; | |
5615 | case AND: | |
5616 | case IOR: | |
5617 | case XOR: | |
0a2aaacc | 5618 | new_rtx = expand_simple_binop (SImode, code, new_rtx, val, |
45d18331 AS |
5619 | NULL_RTX, 1, OPTAB_DIRECT); |
5620 | break; | |
5621 | case MULT: /* NAND */ | |
0a2aaacc | 5622 | new_rtx = expand_simple_binop (SImode, AND, new_rtx, val, |
45d18331 | 5623 | NULL_RTX, 1, OPTAB_DIRECT); |
6a238c58 AK |
5624 | new_rtx = expand_simple_binop (SImode, XOR, new_rtx, ac.modemask, |
5625 | NULL_RTX, 1, OPTAB_DIRECT); | |
45d18331 AS |
5626 | break; |
5627 | default: | |
5628 | gcc_unreachable (); | |
5629 | } | |
45d18331 | 5630 | |
8bb501bb | 5631 | s390_emit_jump (csloop, s390_emit_compare_and_swap (NE, cmp, |
0a2aaacc | 5632 | ac.memsi, cmp, new_rtx)); |
45d18331 AS |
5633 | |
5634 | /* Return the correct part of the bitfield. */ | |
5635 | if (target) | |
5636 | convert_move (target, expand_simple_binop (SImode, LSHIFTRT, | |
0a2aaacc | 5637 | after ? new_rtx : cmp, ac.shift, |
45d18331 AS |
5638 | NULL_RTX, 1, OPTAB_DIRECT), 1); |
5639 | } | |
5640 | ||
fdbe66f2 | 5641 | /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL. |
6b2300b3 JJ |
5642 | We need to emit DTP-relative relocations. */ |
5643 | ||
fdbe66f2 EB |
5644 | static void s390_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED; |
5645 | ||
5646 | static void | |
9c808aad | 5647 | s390_output_dwarf_dtprel (FILE *file, int size, rtx x) |
6b2300b3 JJ |
5648 | { |
5649 | switch (size) | |
5650 | { | |
5651 | case 4: | |
5652 | fputs ("\t.long\t", file); | |
5653 | break; | |
5654 | case 8: | |
5655 | fputs ("\t.quad\t", file); | |
5656 | break; | |
5657 | default: | |
8d933e31 | 5658 | gcc_unreachable (); |
6b2300b3 JJ |
5659 | } |
5660 | output_addr_const (file, x); | |
5661 | fputs ("@DTPOFF", file); | |
5662 | } | |
5663 | ||
085261c8 AK |
5664 | /* Return the proper mode for REGNO being represented in the dwarf |
5665 | unwind table. */ | |
5666 | machine_mode | |
5667 | s390_dwarf_frame_reg_mode (int regno) | |
5668 | { | |
5669 | machine_mode save_mode = default_dwarf_frame_reg_mode (regno); | |
5670 | ||
5671 | /* The rightmost 64 bits of vector registers are call-clobbered. */ | |
5672 | if (GET_MODE_SIZE (save_mode) > 8) | |
5673 | save_mode = DImode; | |
5674 | ||
5675 | return save_mode; | |
5676 | } | |
5677 | ||
7269aee7 | 5678 | #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING |
608063c3 | 5679 | /* Implement TARGET_MANGLE_TYPE. */ |
7269aee7 AH |
5680 | |
5681 | static const char * | |
3101faab | 5682 | s390_mangle_type (const_tree type) |
7269aee7 AH |
5683 | { |
5684 | if (TYPE_MAIN_VARIANT (type) == long_double_type_node | |
5685 | && TARGET_LONG_DOUBLE_128) | |
5686 | return "g"; | |
5687 | ||
5688 | /* For all other types, use normal C++ mangling. */ | |
5689 | return NULL; | |
5690 | } | |
5691 | #endif | |
5692 | ||
4c8c0dec | 5693 | /* In the name of slightly smaller debug output, and to cater to |
aabcd309 | 5694 | general assembler lossage, recognize various UNSPEC sequences |
4c8c0dec JJ |
5695 | and turn them back into a direct symbol reference. */ |
5696 | ||
69bd9368 | 5697 | static rtx |
9c808aad | 5698 | s390_delegitimize_address (rtx orig_x) |
4c8c0dec | 5699 | { |
e8d8f497 | 5700 | rtx x, y; |
4c8c0dec | 5701 | |
e8d8f497 JJ |
5702 | orig_x = delegitimize_mem_from_attrs (orig_x); |
5703 | x = orig_x; | |
e101e12e AK |
5704 | |
5705 | /* Extract the symbol ref from: | |
5706 | (plus:SI (reg:SI 12 %r12) | |
5707 | (const:SI (unspec:SI [(symbol_ref/f:SI ("*.LC0"))] | |
01841ac0 AK |
5708 | UNSPEC_GOTOFF/PLTOFF))) |
5709 | and | |
5710 | (plus:SI (reg:SI 12 %r12) | |
5711 | (const:SI (plus:SI (unspec:SI [(symbol_ref:SI ("L"))] | |
5712 | UNSPEC_GOTOFF/PLTOFF) | |
5713 | (const_int 4 [0x4])))) */ | |
e101e12e AK |
5714 | if (GET_CODE (x) == PLUS |
5715 | && REG_P (XEXP (x, 0)) | |
5716 | && REGNO (XEXP (x, 0)) == PIC_OFFSET_TABLE_REGNUM | |
5717 | && GET_CODE (XEXP (x, 1)) == CONST) | |
5718 | { | |
ab081dd6 AK |
5719 | HOST_WIDE_INT offset = 0; |
5720 | ||
e101e12e AK |
5721 | /* The const operand. */ |
5722 | y = XEXP (XEXP (x, 1), 0); | |
01841ac0 AK |
5723 | |
5724 | if (GET_CODE (y) == PLUS | |
5725 | && GET_CODE (XEXP (y, 1)) == CONST_INT) | |
ab081dd6 AK |
5726 | { |
5727 | offset = INTVAL (XEXP (y, 1)); | |
5728 | y = XEXP (y, 0); | |
5729 | } | |
01841ac0 | 5730 | |
e101e12e | 5731 | if (GET_CODE (y) == UNSPEC |
01841ac0 AK |
5732 | && (XINT (y, 1) == UNSPEC_GOTOFF |
5733 | || XINT (y, 1) == UNSPEC_PLTOFF)) | |
0a81f074 | 5734 | return plus_constant (Pmode, XVECEXP (y, 0, 0), offset); |
e101e12e AK |
5735 | } |
5736 | ||
4c8c0dec JJ |
5737 | if (GET_CODE (x) != MEM) |
5738 | return orig_x; | |
5739 | ||
5740 | x = XEXP (x, 0); | |
5741 | if (GET_CODE (x) == PLUS | |
5742 | && GET_CODE (XEXP (x, 1)) == CONST | |
5743 | && GET_CODE (XEXP (x, 0)) == REG | |
5744 | && REGNO (XEXP (x, 0)) == PIC_OFFSET_TABLE_REGNUM) | |
5745 | { | |
5746 | y = XEXP (XEXP (x, 1), 0); | |
5747 | if (GET_CODE (y) == UNSPEC | |
fd7643fb | 5748 | && XINT (y, 1) == UNSPEC_GOT) |
67a2f76d JJ |
5749 | y = XVECEXP (y, 0, 0); |
5750 | else | |
5751 | return orig_x; | |
4c8c0dec | 5752 | } |
67a2f76d | 5753 | else if (GET_CODE (x) == CONST) |
4c8c0dec | 5754 | { |
01841ac0 AK |
5755 | /* Extract the symbol ref from: |
5756 | (mem:QI (const:DI (unspec:DI [(symbol_ref:DI ("foo"))] | |
5757 | UNSPEC_PLT/GOTENT))) */ | |
5758 | ||
4c8c0dec JJ |
5759 | y = XEXP (x, 0); |
5760 | if (GET_CODE (y) == UNSPEC | |
01841ac0 AK |
5761 | && (XINT (y, 1) == UNSPEC_GOTENT |
5762 | || XINT (y, 1) == UNSPEC_PLT)) | |
67a2f76d JJ |
5763 | y = XVECEXP (y, 0, 0); |
5764 | else | |
5765 | return orig_x; | |
4c8c0dec | 5766 | } |
67a2f76d JJ |
5767 | else |
5768 | return orig_x; | |
4c8c0dec | 5769 | |
67a2f76d JJ |
5770 | if (GET_MODE (orig_x) != Pmode) |
5771 | { | |
2f36e14b JJ |
5772 | if (GET_MODE (orig_x) == BLKmode) |
5773 | return orig_x; | |
67a2f76d JJ |
5774 | y = lowpart_subreg (GET_MODE (orig_x), y, Pmode); |
5775 | if (y == NULL_RTX) | |
5776 | return orig_x; | |
5777 | } | |
5778 | return y; | |
4c8c0dec | 5779 | } |
ba956982 | 5780 | |
6d057022 AS |
5781 | /* Output operand OP to stdio stream FILE. |
5782 | OP is an address (register + offset) which is not used to address data; | |
5783 | instead the rightmost bits are interpreted as the value. */ | |
ac32b25e UW |
5784 | |
5785 | static void | |
5786 | print_shift_count_operand (FILE *file, rtx op) | |
5787 | { | |
d98ad410 UW |
5788 | HOST_WIDE_INT offset; |
5789 | rtx base; | |
f83a336d | 5790 | |
d98ad410 | 5791 | /* Extract base register and offset. */ |
4989e88a | 5792 | if (!s390_decompose_shift_count (op, &base, &offset)) |
d98ad410 | 5793 | gcc_unreachable (); |
ac32b25e UW |
5794 | |
5795 | /* Sanity check. */ | |
d98ad410 | 5796 | if (base) |
8d933e31 | 5797 | { |
d98ad410 UW |
5798 | gcc_assert (GET_CODE (base) == REG); |
5799 | gcc_assert (REGNO (base) < FIRST_PSEUDO_REGISTER); | |
5800 | gcc_assert (REGNO_REG_CLASS (REGNO (base)) == ADDR_REGS); | |
8d933e31 | 5801 | } |
ac32b25e | 5802 | |
6d057022 AS |
5803 | /* Offsets are constricted to twelve bits. */ |
5804 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, offset & ((1 << 12) - 1)); | |
d98ad410 UW |
5805 | if (base) |
5806 | fprintf (file, "(%s)", reg_names[REGNO (base)]); | |
ac32b25e UW |
5807 | } |
5808 | ||
2d38d809 DV |
5809 | /* Assigns the number of NOP halfwords to be emitted before and after the |
5810 | function label to *HW_BEFORE and *HW_AFTER. Both pointers must not be NULL. | |
5811 | If hotpatching is disabled for the function, the values are set to zero. | |
5812 | */ | |
d0de9e13 | 5813 | |
2d38d809 | 5814 | static void |
94091f43 DV |
5815 | s390_function_num_hotpatch_hw (tree decl, |
5816 | int *hw_before, | |
5817 | int *hw_after) | |
d0de9e13 DV |
5818 | { |
5819 | tree attr; | |
5820 | ||
94091f43 DV |
5821 | attr = lookup_attribute ("hotpatch", DECL_ATTRIBUTES (decl)); |
5822 | ||
5823 | /* Handle the arguments of the hotpatch attribute. The values | |
5824 | specified via attribute might override the cmdline argument | |
5825 | values. */ | |
5826 | if (attr) | |
d0de9e13 | 5827 | { |
94091f43 DV |
5828 | tree args = TREE_VALUE (attr); |
5829 | ||
5830 | *hw_before = TREE_INT_CST_LOW (TREE_VALUE (args)); | |
5831 | *hw_after = TREE_INT_CST_LOW (TREE_VALUE (TREE_CHAIN (args))); | |
d0de9e13 | 5832 | } |
94091f43 | 5833 | else |
d0de9e13 | 5834 | { |
94091f43 DV |
5835 | /* Use the values specified by the cmdline arguments. */ |
5836 | *hw_before = s390_hotpatch_hw_before_label; | |
5837 | *hw_after = s390_hotpatch_hw_after_label; | |
d0de9e13 | 5838 | } |
d0de9e13 DV |
5839 | } |
5840 | ||
5841 | /* Write the extra assembler code needed to declare a function properly. */ | |
5842 | ||
5843 | void | |
5844 | s390_asm_output_function_label (FILE *asm_out_file, const char *fname, | |
5845 | tree decl) | |
5846 | { | |
94091f43 | 5847 | int hw_before, hw_after; |
d0de9e13 | 5848 | |
2d38d809 DV |
5849 | s390_function_num_hotpatch_hw (decl, &hw_before, &hw_after); |
5850 | if (hw_before > 0) | |
d0de9e13 | 5851 | { |
f8af0e30 | 5852 | unsigned int function_alignment; |
d0de9e13 DV |
5853 | int i; |
5854 | ||
5855 | /* Add a trampoline code area before the function label and initialize it | |
5856 | with two-byte nop instructions. This area can be overwritten with code | |
5857 | that jumps to a patched version of the function. */ | |
2d38d809 DV |
5858 | asm_fprintf (asm_out_file, "\tnopr\t%%r7" |
5859 | "\t# pre-label NOPs for hotpatch (%d halfwords)\n", | |
5860 | hw_before); | |
5861 | for (i = 1; i < hw_before; i++) | |
5862 | fputs ("\tnopr\t%r7\n", asm_out_file); | |
5863 | ||
d0de9e13 DV |
5864 | /* Note: The function label must be aligned so that (a) the bytes of the |
5865 | following nop do not cross a cacheline boundary, and (b) a jump address | |
5866 | (eight bytes for 64 bit targets, 4 bytes for 32 bit targets) can be | |
5867 | stored directly before the label without crossing a cacheline | |
5868 | boundary. All this is necessary to make sure the trampoline code can | |
2d38d809 DV |
5869 | be changed atomically. |
5870 | This alignment is done automatically using the FOUNCTION_BOUNDARY, but | |
5871 | if there are NOPs before the function label, the alignment is placed | |
5872 | before them. So it is necessary to duplicate the alignment after the | |
5873 | NOPs. */ | |
f8af0e30 DV |
5874 | function_alignment = MAX (8, DECL_ALIGN (decl) / BITS_PER_UNIT); |
5875 | if (! DECL_USER_ALIGN (decl)) | |
5876 | function_alignment = MAX (function_alignment, | |
5877 | (unsigned int) align_functions); | |
2d38d809 | 5878 | fputs ("\t# alignment for hotpatch\n", asm_out_file); |
f8af0e30 | 5879 | ASM_OUTPUT_ALIGN (asm_out_file, floor_log2 (function_alignment)); |
d0de9e13 DV |
5880 | } |
5881 | ||
5882 | ASM_OUTPUT_LABEL (asm_out_file, fname); | |
2d38d809 DV |
5883 | if (hw_after > 0) |
5884 | asm_fprintf (asm_out_file, | |
5885 | "\t# post-label NOPs for hotpatch (%d halfwords)\n", | |
5886 | hw_after); | |
d0de9e13 DV |
5887 | } |
5888 | ||
38899e29 | 5889 | /* Output machine-dependent UNSPECs occurring in address constant X |
faeb9bb6 UW |
5890 | in assembler syntax to stdio stream FILE. Returns true if the |
5891 | constant X could be recognized, false otherwise. */ | |
9db1d521 | 5892 | |
0f8ab434 | 5893 | static bool |
faeb9bb6 | 5894 | s390_output_addr_const_extra (FILE *file, rtx x) |
9db1d521 | 5895 | { |
faeb9bb6 UW |
5896 | if (GET_CODE (x) == UNSPEC && XVECLEN (x, 0) == 1) |
5897 | switch (XINT (x, 1)) | |
5898 | { | |
5899 | case UNSPEC_GOTENT: | |
5900 | output_addr_const (file, XVECEXP (x, 0, 0)); | |
5901 | fprintf (file, "@GOTENT"); | |
5902 | return true; | |
5903 | case UNSPEC_GOT: | |
5904 | output_addr_const (file, XVECEXP (x, 0, 0)); | |
5905 | fprintf (file, "@GOT"); | |
5906 | return true; | |
5907 | case UNSPEC_GOTOFF: | |
5908 | output_addr_const (file, XVECEXP (x, 0, 0)); | |
5909 | fprintf (file, "@GOTOFF"); | |
5910 | return true; | |
5911 | case UNSPEC_PLT: | |
5912 | output_addr_const (file, XVECEXP (x, 0, 0)); | |
5913 | fprintf (file, "@PLT"); | |
5914 | return true; | |
5915 | case UNSPEC_PLTOFF: | |
5916 | output_addr_const (file, XVECEXP (x, 0, 0)); | |
5917 | fprintf (file, "@PLTOFF"); | |
5918 | return true; | |
5919 | case UNSPEC_TLSGD: | |
5920 | output_addr_const (file, XVECEXP (x, 0, 0)); | |
5921 | fprintf (file, "@TLSGD"); | |
5922 | return true; | |
5923 | case UNSPEC_TLSLDM: | |
5924 | assemble_name (file, get_some_local_dynamic_name ()); | |
5925 | fprintf (file, "@TLSLDM"); | |
5926 | return true; | |
5927 | case UNSPEC_DTPOFF: | |
5928 | output_addr_const (file, XVECEXP (x, 0, 0)); | |
5929 | fprintf (file, "@DTPOFF"); | |
5930 | return true; | |
5931 | case UNSPEC_NTPOFF: | |
5932 | output_addr_const (file, XVECEXP (x, 0, 0)); | |
5933 | fprintf (file, "@NTPOFF"); | |
5934 | return true; | |
5935 | case UNSPEC_GOTNTPOFF: | |
5936 | output_addr_const (file, XVECEXP (x, 0, 0)); | |
5937 | fprintf (file, "@GOTNTPOFF"); | |
5938 | return true; | |
5939 | case UNSPEC_INDNTPOFF: | |
5940 | output_addr_const (file, XVECEXP (x, 0, 0)); | |
5941 | fprintf (file, "@INDNTPOFF"); | |
5942 | return true; | |
5943 | } | |
9db1d521 | 5944 | |
dc66391d RS |
5945 | if (GET_CODE (x) == UNSPEC && XVECLEN (x, 0) == 2) |
5946 | switch (XINT (x, 1)) | |
5947 | { | |
5948 | case UNSPEC_POOL_OFFSET: | |
5949 | x = gen_rtx_MINUS (GET_MODE (x), XVECEXP (x, 0, 0), XVECEXP (x, 0, 1)); | |
5950 | output_addr_const (file, x); | |
5951 | return true; | |
5952 | } | |
faeb9bb6 | 5953 | return false; |
9db1d521 HP |
5954 | } |
5955 | ||
c7453384 | 5956 | /* Output address operand ADDR in assembler syntax to |
994fe660 | 5957 | stdio stream FILE. */ |
9db1d521 HP |
5958 | |
5959 | void | |
9c808aad | 5960 | print_operand_address (FILE *file, rtx addr) |
9db1d521 HP |
5961 | { |
5962 | struct s390_address ad; | |
5963 | ||
0ff4390d | 5964 | if (s390_loadrelative_operand_p (addr, NULL, NULL)) |
963fc8d0 | 5965 | { |
8395b41e AK |
5966 | if (!TARGET_Z10) |
5967 | { | |
3f3c098d AK |
5968 | output_operand_lossage ("symbolic memory references are " |
5969 | "only supported on z10 or later"); | |
8395b41e AK |
5970 | return; |
5971 | } | |
963fc8d0 AK |
5972 | output_addr_const (file, addr); |
5973 | return; | |
5974 | } | |
5975 | ||
b808c04c | 5976 | if (!s390_decompose_address (addr, &ad) |
93fa8428 AK |
5977 | || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base))) |
5978 | || (ad.indx && !REGNO_OK_FOR_INDEX_P (REGNO (ad.indx)))) | |
c85ce869 | 5979 | output_operand_lossage ("cannot decompose address"); |
c7453384 | 5980 | |
9db1d521 | 5981 | if (ad.disp) |
faeb9bb6 | 5982 | output_addr_const (file, ad.disp); |
9db1d521 HP |
5983 | else |
5984 | fprintf (file, "0"); | |
5985 | ||
5986 | if (ad.base && ad.indx) | |
5987 | fprintf (file, "(%s,%s)", reg_names[REGNO (ad.indx)], | |
5988 | reg_names[REGNO (ad.base)]); | |
5989 | else if (ad.base) | |
5990 | fprintf (file, "(%s)", reg_names[REGNO (ad.base)]); | |
5991 | } | |
5992 | ||
c7453384 EC |
5993 | /* Output operand X in assembler syntax to stdio stream FILE. |
5994 | CODE specified the format flag. The following format flags | |
994fe660 UW |
5995 | are recognized: |
5996 | ||
5997 | 'C': print opcode suffix for branch condition. | |
5998 | 'D': print opcode suffix for inverse branch condition. | |
f1149235 | 5999 | 'E': print opcode suffix for branch on index instruction. |
7b8acc34 | 6000 | 'G': print the size of the operand in bytes. |
75ca1b39 RH |
6001 | 'J': print tls_load/tls_gdcall/tls_ldcall suffix |
6002 | 'M': print the second word of a TImode operand. | |
6003 | 'N': print the second word of a DImode operand. | |
085261c8 AK |
6004 | 'O': print only the displacement of a memory reference or address. |
6005 | 'R': print only the base register of a memory reference or address. | |
fc0ea003 | 6006 | 'S': print S-type memory reference (base+displacement). |
ac32b25e | 6007 | 'Y': print shift count operand. |
994fe660 | 6008 | |
5519a4f9 | 6009 | 'b': print integer X as if it's an unsigned byte. |
963fc8d0 | 6010 | 'c': print integer X as if it's an signed byte. |
085261c8 AK |
6011 | 'e': "end" contiguous bitmask X in either DImode or vector inner mode. |
6012 | 'f': "end" contiguous bitmask X in SImode. | |
da48f5ec | 6013 | 'h': print integer X as if it's a signed halfword. |
f19a9af7 | 6014 | 'i': print the first nonzero HImode part of X. |
da48f5ec AK |
6015 | 'j': print the first HImode part unequal to -1 of X. |
6016 | 'k': print the first nonzero SImode part of X. | |
6017 | 'm': print the first SImode part unequal to -1 of X. | |
75ca1b39 | 6018 | 'o': print integer X as if it's an unsigned 32bit word. |
085261c8 AK |
6019 | 's': "start" of contiguous bitmask X in either DImode or vector inner mode. |
6020 | 't': CONST_INT: "start" of contiguous bitmask X in SImode. | |
6021 | CONST_VECTOR: Generate a bitmask for vgbm instruction. | |
75ca1b39 | 6022 | 'x': print integer X as if it's an unsigned halfword. |
085261c8 | 6023 | 'v': print register number as vector register (v1 instead of f1). |
75ca1b39 | 6024 | */ |
9db1d521 HP |
6025 | |
6026 | void | |
9c808aad | 6027 | print_operand (FILE *file, rtx x, int code) |
9db1d521 | 6028 | { |
75ca1b39 RH |
6029 | HOST_WIDE_INT ival; |
6030 | ||
9db1d521 HP |
6031 | switch (code) |
6032 | { | |
6033 | case 'C': | |
ba956982 | 6034 | fprintf (file, s390_branch_condition_mnemonic (x, FALSE)); |
9db1d521 HP |
6035 | return; |
6036 | ||
6037 | case 'D': | |
ba956982 | 6038 | fprintf (file, s390_branch_condition_mnemonic (x, TRUE)); |
9db1d521 HP |
6039 | return; |
6040 | ||
f1149235 AK |
6041 | case 'E': |
6042 | if (GET_CODE (x) == LE) | |
6043 | fprintf (file, "l"); | |
6044 | else if (GET_CODE (x) == GT) | |
6045 | fprintf (file, "h"); | |
6046 | else | |
3f3c098d AK |
6047 | output_operand_lossage ("invalid comparison operator " |
6048 | "for 'E' output modifier"); | |
f1149235 AK |
6049 | return; |
6050 | ||
fd3cd001 UW |
6051 | case 'J': |
6052 | if (GET_CODE (x) == SYMBOL_REF) | |
6053 | { | |
6054 | fprintf (file, "%s", ":tls_load:"); | |
6055 | output_addr_const (file, x); | |
6056 | } | |
6057 | else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLSGD) | |
6058 | { | |
6059 | fprintf (file, "%s", ":tls_gdcall:"); | |
6060 | output_addr_const (file, XVECEXP (x, 0, 0)); | |
6061 | } | |
6062 | else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLSLDM) | |
6063 | { | |
6064 | fprintf (file, "%s", ":tls_ldcall:"); | |
4fbca4ba RS |
6065 | const char *name = get_some_local_dynamic_name (); |
6066 | gcc_assert (name); | |
6067 | assemble_name (file, name); | |
fd3cd001 UW |
6068 | } |
6069 | else | |
3f3c098d | 6070 | output_operand_lossage ("invalid reference for 'J' output modifier"); |
fd3cd001 UW |
6071 | return; |
6072 | ||
7b8acc34 AK |
6073 | case 'G': |
6074 | fprintf (file, "%u", GET_MODE_SIZE (GET_MODE (x))); | |
6075 | return; | |
6076 | ||
9db1d521 HP |
6077 | case 'O': |
6078 | { | |
6079 | struct s390_address ad; | |
8d933e31 | 6080 | int ret; |
9db1d521 | 6081 | |
085261c8 | 6082 | ret = s390_decompose_address (MEM_P (x) ? XEXP (x, 0) : x, &ad); |
8395b41e AK |
6083 | |
6084 | if (!ret | |
6085 | || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base))) | |
6086 | || ad.indx) | |
6087 | { | |
3f3c098d | 6088 | output_operand_lossage ("invalid address for 'O' output modifier"); |
8395b41e AK |
6089 | return; |
6090 | } | |
9db1d521 HP |
6091 | |
6092 | if (ad.disp) | |
faeb9bb6 | 6093 | output_addr_const (file, ad.disp); |
9db1d521 HP |
6094 | else |
6095 | fprintf (file, "0"); | |
6096 | } | |
6097 | return; | |
6098 | ||
6099 | case 'R': | |
6100 | { | |
6101 | struct s390_address ad; | |
8d933e31 | 6102 | int ret; |
9db1d521 | 6103 | |
085261c8 | 6104 | ret = s390_decompose_address (MEM_P (x) ? XEXP (x, 0) : x, &ad); |
8395b41e AK |
6105 | |
6106 | if (!ret | |
6107 | || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base))) | |
6108 | || ad.indx) | |
6109 | { | |
3f3c098d | 6110 | output_operand_lossage ("invalid address for 'R' output modifier"); |
8395b41e AK |
6111 | return; |
6112 | } | |
9db1d521 HP |
6113 | |
6114 | if (ad.base) | |
6115 | fprintf (file, "%s", reg_names[REGNO (ad.base)]); | |
6116 | else | |
6117 | fprintf (file, "0"); | |
6118 | } | |
6119 | return; | |
6120 | ||
fc0ea003 UW |
6121 | case 'S': |
6122 | { | |
6123 | struct s390_address ad; | |
8d933e31 | 6124 | int ret; |
fc0ea003 | 6125 | |
8395b41e AK |
6126 | if (!MEM_P (x)) |
6127 | { | |
3f3c098d AK |
6128 | output_operand_lossage ("memory reference expected for " |
6129 | "'S' output modifier"); | |
8395b41e AK |
6130 | return; |
6131 | } | |
8d933e31 | 6132 | ret = s390_decompose_address (XEXP (x, 0), &ad); |
8395b41e AK |
6133 | |
6134 | if (!ret | |
6135 | || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base))) | |
6136 | || ad.indx) | |
6137 | { | |
3f3c098d | 6138 | output_operand_lossage ("invalid address for 'S' output modifier"); |
8395b41e AK |
6139 | return; |
6140 | } | |
fc0ea003 UW |
6141 | |
6142 | if (ad.disp) | |
6143 | output_addr_const (file, ad.disp); | |
6144 | else | |
6145 | fprintf (file, "0"); | |
6146 | ||
6147 | if (ad.base) | |
6148 | fprintf (file, "(%s)", reg_names[REGNO (ad.base)]); | |
6149 | } | |
6150 | return; | |
6151 | ||
9db1d521 HP |
6152 | case 'N': |
6153 | if (GET_CODE (x) == REG) | |
6154 | x = gen_rtx_REG (GET_MODE (x), REGNO (x) + 1); | |
6155 | else if (GET_CODE (x) == MEM) | |
0a81f074 RS |
6156 | x = change_address (x, VOIDmode, |
6157 | plus_constant (Pmode, XEXP (x, 0), 4)); | |
9db1d521 | 6158 | else |
3f3c098d AK |
6159 | output_operand_lossage ("register or memory expression expected " |
6160 | "for 'N' output modifier"); | |
9db1d521 HP |
6161 | break; |
6162 | ||
6163 | case 'M': | |
6164 | if (GET_CODE (x) == REG) | |
6165 | x = gen_rtx_REG (GET_MODE (x), REGNO (x) + 1); | |
6166 | else if (GET_CODE (x) == MEM) | |
0a81f074 RS |
6167 | x = change_address (x, VOIDmode, |
6168 | plus_constant (Pmode, XEXP (x, 0), 8)); | |
9db1d521 | 6169 | else |
3f3c098d AK |
6170 | output_operand_lossage ("register or memory expression expected " |
6171 | "for 'M' output modifier"); | |
9db1d521 | 6172 | break; |
ac32b25e UW |
6173 | |
6174 | case 'Y': | |
6175 | print_shift_count_operand (file, x); | |
6176 | return; | |
9db1d521 HP |
6177 | } |
6178 | ||
6179 | switch (GET_CODE (x)) | |
6180 | { | |
6181 | case REG: | |
085261c8 AK |
6182 | /* Print FP regs as fx instead of vx when they are accessed |
6183 | through non-vector mode. */ | |
6184 | if (code == 'v' | |
6185 | || VECTOR_NOFP_REG_P (x) | |
6186 | || (FP_REG_P (x) && VECTOR_MODE_P (GET_MODE (x))) | |
6187 | || (VECTOR_REG_P (x) | |
6188 | && (GET_MODE_SIZE (GET_MODE (x)) / | |
6189 | s390_class_max_nregs (FP_REGS, GET_MODE (x))) > 8)) | |
6190 | fprintf (file, "%%v%s", reg_names[REGNO (x)] + 2); | |
6191 | else | |
6192 | fprintf (file, "%s", reg_names[REGNO (x)]); | |
9db1d521 HP |
6193 | break; |
6194 | ||
6195 | case MEM: | |
6196 | output_address (XEXP (x, 0)); | |
6197 | break; | |
6198 | ||
6199 | case CONST: | |
6200 | case CODE_LABEL: | |
6201 | case LABEL_REF: | |
6202 | case SYMBOL_REF: | |
faeb9bb6 | 6203 | output_addr_const (file, x); |
9db1d521 HP |
6204 | break; |
6205 | ||
6206 | case CONST_INT: | |
75ca1b39 RH |
6207 | ival = INTVAL (x); |
6208 | switch (code) | |
6209 | { | |
6210 | case 0: | |
6211 | break; | |
6212 | case 'b': | |
6213 | ival &= 0xff; | |
6214 | break; | |
6215 | case 'c': | |
6216 | ival = ((ival & 0xff) ^ 0x80) - 0x80; | |
6217 | break; | |
6218 | case 'x': | |
6219 | ival &= 0xffff; | |
6220 | break; | |
6221 | case 'h': | |
6222 | ival = ((ival & 0xffff) ^ 0x8000) - 0x8000; | |
6223 | break; | |
6224 | case 'i': | |
6225 | ival = s390_extract_part (x, HImode, 0); | |
6226 | break; | |
6227 | case 'j': | |
6228 | ival = s390_extract_part (x, HImode, -1); | |
6229 | break; | |
6230 | case 'k': | |
6231 | ival = s390_extract_part (x, SImode, 0); | |
6232 | break; | |
6233 | case 'm': | |
6234 | ival = s390_extract_part (x, SImode, -1); | |
6235 | break; | |
6236 | case 'o': | |
6237 | ival &= 0xffffffff; | |
6238 | break; | |
6239 | case 'e': case 'f': | |
6240 | case 's': case 't': | |
6241 | { | |
6242 | int pos, len; | |
6243 | bool ok; | |
6244 | ||
6245 | len = (code == 's' || code == 'e' ? 64 : 32); | |
6246 | ok = s390_contiguous_bitmask_p (ival, len, &pos, &len); | |
6247 | gcc_assert (ok); | |
6248 | if (code == 's' || code == 't') | |
6249 | ival = 64 - pos - len; | |
6250 | else | |
6251 | ival = 64 - 1 - pos; | |
6252 | } | |
6253 | break; | |
6254 | default: | |
6255 | output_operand_lossage ("invalid constant for output modifier '%c'", code); | |
6256 | } | |
6257 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, ival); | |
4023fb28 UW |
6258 | break; |
6259 | ||
6260 | case CONST_DOUBLE: | |
8d933e31 | 6261 | gcc_assert (GET_MODE (x) == VOIDmode); |
4023fb28 UW |
6262 | if (code == 'b') |
6263 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x) & 0xff); | |
9db1d521 | 6264 | else if (code == 'x') |
4023fb28 | 6265 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x) & 0xffff); |
9db1d521 | 6266 | else if (code == 'h') |
3f3c098d AK |
6267 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, |
6268 | ((CONST_DOUBLE_LOW (x) & 0xffff) ^ 0x8000) - 0x8000); | |
9db1d521 | 6269 | else |
8395b41e AK |
6270 | { |
6271 | if (code == 0) | |
3f3c098d AK |
6272 | output_operand_lossage ("invalid constant - try using " |
6273 | "an output modifier"); | |
8395b41e | 6274 | else |
3f3c098d AK |
6275 | output_operand_lossage ("invalid constant for output modifier '%c'", |
6276 | code); | |
8395b41e | 6277 | } |
9db1d521 | 6278 | break; |
085261c8 AK |
6279 | case CONST_VECTOR: |
6280 | switch (code) | |
6281 | { | |
6282 | case 'e': | |
6283 | case 's': | |
6284 | { | |
6285 | int start, stop, inner_len; | |
6286 | bool ok; | |
6287 | ||
6288 | inner_len = GET_MODE_UNIT_BITSIZE (GET_MODE (x)); | |
6289 | ok = s390_contiguous_bitmask_vector_p (x, &start, &stop); | |
6290 | gcc_assert (ok); | |
6291 | if (code == 's' || code == 't') | |
6292 | ival = inner_len - stop - 1; | |
6293 | else | |
6294 | ival = inner_len - start - 1; | |
6295 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, ival); | |
6296 | } | |
6297 | break; | |
6298 | case 't': | |
6299 | { | |
6300 | unsigned mask; | |
6301 | bool ok = s390_bytemask_vector_p (x, &mask); | |
6302 | gcc_assert (ok); | |
6303 | fprintf (file, "%u", mask); | |
6304 | } | |
6305 | break; | |
6306 | ||
6307 | default: | |
6308 | output_operand_lossage ("invalid constant vector for output " | |
6309 | "modifier '%c'", code); | |
6310 | } | |
6311 | break; | |
9db1d521 HP |
6312 | |
6313 | default: | |
8395b41e | 6314 | if (code == 0) |
3f3c098d AK |
6315 | output_operand_lossage ("invalid expression - try using " |
6316 | "an output modifier"); | |
8395b41e | 6317 | else |
3f3c098d AK |
6318 | output_operand_lossage ("invalid expression for output " |
6319 | "modifier '%c'", code); | |
9db1d521 HP |
6320 | break; |
6321 | } | |
6322 | } | |
6323 | ||
301d03af RS |
6324 | /* Target hook for assembling integer objects. We need to define it |
6325 | here to work a round a bug in some versions of GAS, which couldn't | |
6326 | handle values smaller than INT_MIN when printed in decimal. */ | |
6327 | ||
6328 | static bool | |
9c808aad | 6329 | s390_assemble_integer (rtx x, unsigned int size, int aligned_p) |
301d03af RS |
6330 | { |
6331 | if (size == 8 && aligned_p | |
6332 | && GET_CODE (x) == CONST_INT && INTVAL (x) < INT_MIN) | |
6333 | { | |
4a0a75dd KG |
6334 | fprintf (asm_out_file, "\t.quad\t" HOST_WIDE_INT_PRINT_HEX "\n", |
6335 | INTVAL (x)); | |
301d03af RS |
6336 | return true; |
6337 | } | |
6338 | return default_assemble_integer (x, size, aligned_p); | |
6339 | } | |
6340 | ||
c7453384 | 6341 | /* Returns true if register REGNO is used for forming |
994fe660 | 6342 | a memory address in expression X. */ |
9db1d521 | 6343 | |
3ed99cc9 | 6344 | static bool |
9c808aad | 6345 | reg_used_in_mem_p (int regno, rtx x) |
9db1d521 HP |
6346 | { |
6347 | enum rtx_code code = GET_CODE (x); | |
6348 | int i, j; | |
6349 | const char *fmt; | |
c7453384 | 6350 | |
9db1d521 HP |
6351 | if (code == MEM) |
6352 | { | |
c9bd6bcd | 6353 | if (refers_to_regno_p (regno, XEXP (x, 0))) |
3ed99cc9 | 6354 | return true; |
9db1d521 | 6355 | } |
c7453384 | 6356 | else if (code == SET |
4023fb28 UW |
6357 | && GET_CODE (SET_DEST (x)) == PC) |
6358 | { | |
c9bd6bcd | 6359 | if (refers_to_regno_p (regno, SET_SRC (x))) |
3ed99cc9 | 6360 | return true; |
4023fb28 | 6361 | } |
9db1d521 HP |
6362 | |
6363 | fmt = GET_RTX_FORMAT (code); | |
6364 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
6365 | { | |
6366 | if (fmt[i] == 'e' | |
6367 | && reg_used_in_mem_p (regno, XEXP (x, i))) | |
3ed99cc9 | 6368 | return true; |
c7453384 | 6369 | |
9db1d521 HP |
6370 | else if (fmt[i] == 'E') |
6371 | for (j = 0; j < XVECLEN (x, i); j++) | |
6372 | if (reg_used_in_mem_p (regno, XVECEXP (x, i, j))) | |
3ed99cc9 | 6373 | return true; |
9db1d521 | 6374 | } |
3ed99cc9 | 6375 | return false; |
9db1d521 HP |
6376 | } |
6377 | ||
d65f7478 | 6378 | /* Returns true if expression DEP_RTX sets an address register |
994fe660 | 6379 | used by instruction INSN to address memory. */ |
9db1d521 | 6380 | |
3ed99cc9 | 6381 | static bool |
647d790d | 6382 | addr_generation_dependency_p (rtx dep_rtx, rtx_insn *insn) |
9db1d521 | 6383 | { |
4023fb28 | 6384 | rtx target, pat; |
9db1d521 | 6385 | |
b64925dc | 6386 | if (NONJUMP_INSN_P (dep_rtx)) |
34f0d87a | 6387 | dep_rtx = PATTERN (dep_rtx); |
077dab3b | 6388 | |
9db1d521 HP |
6389 | if (GET_CODE (dep_rtx) == SET) |
6390 | { | |
6391 | target = SET_DEST (dep_rtx); | |
cc7ab9b7 UW |
6392 | if (GET_CODE (target) == STRICT_LOW_PART) |
6393 | target = XEXP (target, 0); | |
6394 | while (GET_CODE (target) == SUBREG) | |
6395 | target = SUBREG_REG (target); | |
6396 | ||
9db1d521 HP |
6397 | if (GET_CODE (target) == REG) |
6398 | { | |
6399 | int regno = REGNO (target); | |
6400 | ||
077dab3b | 6401 | if (s390_safe_attr_type (insn) == TYPE_LA) |
4023fb28 UW |
6402 | { |
6403 | pat = PATTERN (insn); | |
6404 | if (GET_CODE (pat) == PARALLEL) | |
6405 | { | |
8d933e31 | 6406 | gcc_assert (XVECLEN (pat, 0) == 2); |
4023fb28 UW |
6407 | pat = XVECEXP (pat, 0, 0); |
6408 | } | |
8d933e31 | 6409 | gcc_assert (GET_CODE (pat) == SET); |
c9bd6bcd | 6410 | return refers_to_regno_p (regno, SET_SRC (pat)); |
4023fb28 | 6411 | } |
077dab3b | 6412 | else if (get_attr_atype (insn) == ATYPE_AGEN) |
4023fb28 UW |
6413 | return reg_used_in_mem_p (regno, PATTERN (insn)); |
6414 | } | |
9db1d521 | 6415 | } |
3ed99cc9 | 6416 | return false; |
9db1d521 HP |
6417 | } |
6418 | ||
077dab3b HP |
6419 | /* Return 1, if dep_insn sets register used in insn in the agen unit. */ |
6420 | ||
c7453384 | 6421 | int |
647d790d | 6422 | s390_agen_dep_p (rtx_insn *dep_insn, rtx_insn *insn) |
c7453384 | 6423 | { |
077dab3b HP |
6424 | rtx dep_rtx = PATTERN (dep_insn); |
6425 | int i; | |
c7453384 EC |
6426 | |
6427 | if (GET_CODE (dep_rtx) == SET | |
077dab3b HP |
6428 | && addr_generation_dependency_p (dep_rtx, insn)) |
6429 | return 1; | |
6430 | else if (GET_CODE (dep_rtx) == PARALLEL) | |
6431 | { | |
6432 | for (i = 0; i < XVECLEN (dep_rtx, 0); i++) | |
6433 | { | |
6434 | if (addr_generation_dependency_p (XVECEXP (dep_rtx, 0, i), insn)) | |
6435 | return 1; | |
6436 | } | |
6437 | } | |
6438 | return 0; | |
6439 | } | |
6440 | ||
9381e3f1 | 6441 | |
52609473 HP |
6442 | /* A C statement (sans semicolon) to update the integer scheduling priority |
6443 | INSN_PRIORITY (INSN). Increase the priority to execute the INSN earlier, | |
6444 | reduce the priority to execute INSN later. Do not define this macro if | |
c7453384 | 6445 | you do not need to adjust the scheduling priorities of insns. |
52609473 | 6446 | |
c7453384 | 6447 | A STD instruction should be scheduled earlier, |
52609473 | 6448 | in order to use the bypass. */ |
52609473 | 6449 | static int |
ac44248e | 6450 | s390_adjust_priority (rtx_insn *insn, int priority) |
52609473 HP |
6451 | { |
6452 | if (! INSN_P (insn)) | |
6453 | return priority; | |
6454 | ||
ec24698e | 6455 | if (s390_tune != PROCESSOR_2084_Z990 |
2cdece44 | 6456 | && s390_tune != PROCESSOR_2094_Z9_109 |
65b1d8ea | 6457 | && s390_tune != PROCESSOR_2097_Z10 |
22ac2c2f | 6458 | && s390_tune != PROCESSOR_2817_Z196 |
55ac540c AK |
6459 | && s390_tune != PROCESSOR_2827_ZEC12 |
6460 | && s390_tune != PROCESSOR_2964_Z13) | |
52609473 HP |
6461 | return priority; |
6462 | ||
6463 | switch (s390_safe_attr_type (insn)) | |
6464 | { | |
cfdb984b AS |
6465 | case TYPE_FSTOREDF: |
6466 | case TYPE_FSTORESF: | |
52609473 HP |
6467 | priority = priority << 3; |
6468 | break; | |
6469 | case TYPE_STORE: | |
ea77e738 | 6470 | case TYPE_STM: |
52609473 HP |
6471 | priority = priority << 1; |
6472 | break; | |
6473 | default: | |
6474 | break; | |
6475 | } | |
6476 | return priority; | |
6477 | } | |
f2d3c02a | 6478 | |
2cdece44 | 6479 | |
077dab3b | 6480 | /* The number of instructions that can be issued per cycle. */ |
f2d3c02a | 6481 | |
077dab3b | 6482 | static int |
9c808aad | 6483 | s390_issue_rate (void) |
077dab3b | 6484 | { |
93538e8e AK |
6485 | switch (s390_tune) |
6486 | { | |
6487 | case PROCESSOR_2084_Z990: | |
6488 | case PROCESSOR_2094_Z9_109: | |
65b1d8ea | 6489 | case PROCESSOR_2817_Z196: |
93538e8e AK |
6490 | return 3; |
6491 | case PROCESSOR_2097_Z10: | |
6492 | return 2; | |
ff39d72a AK |
6493 | /* Starting with EC12 we use the sched_reorder hook to take care |
6494 | of instruction dispatch constraints. The algorithm only | |
6495 | picks the best instruction and assumes only a single | |
6496 | instruction gets issued per cycle. */ | |
6497 | case PROCESSOR_2827_ZEC12: | |
93538e8e AK |
6498 | default: |
6499 | return 1; | |
6500 | } | |
077dab3b | 6501 | } |
f2d3c02a | 6502 | |
52609473 | 6503 | static int |
9c808aad | 6504 | s390_first_cycle_multipass_dfa_lookahead (void) |
52609473 | 6505 | { |
64e1e4c4 | 6506 | return 4; |
52609473 HP |
6507 | } |
6508 | ||
585539a1 UW |
6509 | /* Annotate every literal pool reference in X by an UNSPEC_LTREF expression. |
6510 | Fix up MEMs as required. */ | |
6511 | ||
6512 | static void | |
6513 | annotate_constant_pool_refs (rtx *x) | |
6514 | { | |
6515 | int i, j; | |
6516 | const char *fmt; | |
6517 | ||
8d933e31 AS |
6518 | gcc_assert (GET_CODE (*x) != SYMBOL_REF |
6519 | || !CONSTANT_POOL_ADDRESS_P (*x)); | |
585539a1 UW |
6520 | |
6521 | /* Literal pool references can only occur inside a MEM ... */ | |
6522 | if (GET_CODE (*x) == MEM) | |
6523 | { | |
6524 | rtx memref = XEXP (*x, 0); | |
6525 | ||
6526 | if (GET_CODE (memref) == SYMBOL_REF | |
6527 | && CONSTANT_POOL_ADDRESS_P (memref)) | |
6528 | { | |
6529 | rtx base = cfun->machine->base_reg; | |
6530 | rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, memref, base), | |
6531 | UNSPEC_LTREF); | |
6532 | ||
6533 | *x = replace_equiv_address (*x, addr); | |
6534 | return; | |
6535 | } | |
6536 | ||
6537 | if (GET_CODE (memref) == CONST | |
6538 | && GET_CODE (XEXP (memref, 0)) == PLUS | |
6539 | && GET_CODE (XEXP (XEXP (memref, 0), 1)) == CONST_INT | |
6540 | && GET_CODE (XEXP (XEXP (memref, 0), 0)) == SYMBOL_REF | |
6541 | && CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (memref, 0), 0))) | |
6542 | { | |
6543 | HOST_WIDE_INT off = INTVAL (XEXP (XEXP (memref, 0), 1)); | |
6544 | rtx sym = XEXP (XEXP (memref, 0), 0); | |
6545 | rtx base = cfun->machine->base_reg; | |
6546 | rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, sym, base), | |
6547 | UNSPEC_LTREF); | |
6548 | ||
0a81f074 | 6549 | *x = replace_equiv_address (*x, plus_constant (Pmode, addr, off)); |
585539a1 UW |
6550 | return; |
6551 | } | |
6552 | } | |
6553 | ||
6554 | /* ... or a load-address type pattern. */ | |
6555 | if (GET_CODE (*x) == SET) | |
6556 | { | |
6557 | rtx addrref = SET_SRC (*x); | |
6558 | ||
6559 | if (GET_CODE (addrref) == SYMBOL_REF | |
6560 | && CONSTANT_POOL_ADDRESS_P (addrref)) | |
6561 | { | |
6562 | rtx base = cfun->machine->base_reg; | |
6563 | rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, addrref, base), | |
6564 | UNSPEC_LTREF); | |
6565 | ||
6566 | SET_SRC (*x) = addr; | |
6567 | return; | |
6568 | } | |
6569 | ||
6570 | if (GET_CODE (addrref) == CONST | |
6571 | && GET_CODE (XEXP (addrref, 0)) == PLUS | |
6572 | && GET_CODE (XEXP (XEXP (addrref, 0), 1)) == CONST_INT | |
6573 | && GET_CODE (XEXP (XEXP (addrref, 0), 0)) == SYMBOL_REF | |
6574 | && CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (addrref, 0), 0))) | |
6575 | { | |
6576 | HOST_WIDE_INT off = INTVAL (XEXP (XEXP (addrref, 0), 1)); | |
6577 | rtx sym = XEXP (XEXP (addrref, 0), 0); | |
6578 | rtx base = cfun->machine->base_reg; | |
6579 | rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, sym, base), | |
6580 | UNSPEC_LTREF); | |
6581 | ||
0a81f074 | 6582 | SET_SRC (*x) = plus_constant (Pmode, addr, off); |
585539a1 UW |
6583 | return; |
6584 | } | |
6585 | } | |
6586 | ||
6587 | /* Annotate LTREL_BASE as well. */ | |
6588 | if (GET_CODE (*x) == UNSPEC | |
6589 | && XINT (*x, 1) == UNSPEC_LTREL_BASE) | |
6590 | { | |
6591 | rtx base = cfun->machine->base_reg; | |
6592 | *x = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, XVECEXP (*x, 0, 0), base), | |
6593 | UNSPEC_LTREL_BASE); | |
6594 | return; | |
6595 | } | |
6596 | ||
6597 | fmt = GET_RTX_FORMAT (GET_CODE (*x)); | |
6598 | for (i = GET_RTX_LENGTH (GET_CODE (*x)) - 1; i >= 0; i--) | |
6599 | { | |
6600 | if (fmt[i] == 'e') | |
6601 | { | |
6602 | annotate_constant_pool_refs (&XEXP (*x, i)); | |
6603 | } | |
6604 | else if (fmt[i] == 'E') | |
6605 | { | |
6606 | for (j = 0; j < XVECLEN (*x, i); j++) | |
6607 | annotate_constant_pool_refs (&XVECEXP (*x, i, j)); | |
6608 | } | |
6609 | } | |
6610 | } | |
6611 | ||
ab96de7e AS |
6612 | /* Split all branches that exceed the maximum distance. |
6613 | Returns true if this created a new literal pool entry. */ | |
6614 | ||
6615 | static int | |
6616 | s390_split_branches (void) | |
6617 | { | |
6618 | rtx temp_reg = gen_rtx_REG (Pmode, RETURN_REGNUM); | |
8d933e31 | 6619 | int new_literal = 0, ret; |
775c43d3 | 6620 | rtx_insn *insn; |
17f385d8 | 6621 | rtx pat, target; |
ab96de7e AS |
6622 | rtx *label; |
6623 | ||
6624 | /* We need correct insn addresses. */ | |
6625 | ||
6626 | shorten_branches (get_insns ()); | |
6627 | ||
6628 | /* Find all branches that exceed 64KB, and split them. */ | |
6629 | ||
6630 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) | |
6631 | { | |
966f97ac | 6632 | if (! JUMP_P (insn) || tablejump_p (insn, NULL, NULL)) |
ab96de7e AS |
6633 | continue; |
6634 | ||
6635 | pat = PATTERN (insn); | |
966f97ac | 6636 | if (GET_CODE (pat) == PARALLEL) |
ab96de7e AS |
6637 | pat = XVECEXP (pat, 0, 0); |
6638 | if (GET_CODE (pat) != SET || SET_DEST (pat) != pc_rtx) | |
6639 | continue; | |
6640 | ||
6641 | if (GET_CODE (SET_SRC (pat)) == LABEL_REF) | |
6642 | { | |
6643 | label = &SET_SRC (pat); | |
6644 | } | |
6645 | else if (GET_CODE (SET_SRC (pat)) == IF_THEN_ELSE) | |
6646 | { | |
6647 | if (GET_CODE (XEXP (SET_SRC (pat), 1)) == LABEL_REF) | |
6648 | label = &XEXP (SET_SRC (pat), 1); | |
6649 | else if (GET_CODE (XEXP (SET_SRC (pat), 2)) == LABEL_REF) | |
6650 | label = &XEXP (SET_SRC (pat), 2); | |
6651 | else | |
6652 | continue; | |
6653 | } | |
6654 | else | |
6655 | continue; | |
6656 | ||
6657 | if (get_attr_length (insn) <= 4) | |
6658 | continue; | |
6659 | ||
e2df5c1d UW |
6660 | /* We are going to use the return register as scratch register, |
6661 | make sure it will be saved/restored by the prologue/epilogue. */ | |
6662 | cfun_frame_layout.save_return_addr_p = 1; | |
6663 | ||
ab96de7e AS |
6664 | if (!flag_pic) |
6665 | { | |
6666 | new_literal = 1; | |
17f385d8 | 6667 | rtx mem = force_const_mem (Pmode, *label); |
f7df4a84 RS |
6668 | rtx_insn *set_insn = emit_insn_before (gen_rtx_SET (temp_reg, mem), |
6669 | insn); | |
17f385d8 DM |
6670 | INSN_ADDRESSES_NEW (set_insn, -1); |
6671 | annotate_constant_pool_refs (&PATTERN (set_insn)); | |
ab96de7e AS |
6672 | |
6673 | target = temp_reg; | |
6674 | } | |
6675 | else | |
6676 | { | |
6677 | new_literal = 1; | |
6678 | target = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, *label), | |
6679 | UNSPEC_LTREL_OFFSET); | |
6680 | target = gen_rtx_CONST (Pmode, target); | |
6681 | target = force_const_mem (Pmode, target); | |
f7df4a84 RS |
6682 | rtx_insn *set_insn = emit_insn_before (gen_rtx_SET (temp_reg, target), |
6683 | insn); | |
17f385d8 DM |
6684 | INSN_ADDRESSES_NEW (set_insn, -1); |
6685 | annotate_constant_pool_refs (&PATTERN (set_insn)); | |
ab96de7e AS |
6686 | |
6687 | target = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, XEXP (target, 0), | |
6688 | cfun->machine->base_reg), | |
6689 | UNSPEC_LTREL_BASE); | |
6690 | target = gen_rtx_PLUS (Pmode, temp_reg, target); | |
6691 | } | |
6692 | ||
8d933e31 AS |
6693 | ret = validate_change (insn, label, target, 0); |
6694 | gcc_assert (ret); | |
ab96de7e AS |
6695 | } |
6696 | ||
6697 | return new_literal; | |
6698 | } | |
6699 | ||
b2ccb744 | 6700 | |
f4aa3848 AK |
6701 | /* Find an annotated literal pool symbol referenced in RTX X, |
6702 | and store it at REF. Will abort if X contains references to | |
585539a1 UW |
6703 | more than one such pool symbol; multiple references to the same |
6704 | symbol are allowed, however. | |
b2ccb744 | 6705 | |
c7453384 | 6706 | The rtx pointed to by REF must be initialized to NULL_RTX |
b2ccb744 UW |
6707 | by the caller before calling this routine. */ |
6708 | ||
6709 | static void | |
9c808aad | 6710 | find_constant_pool_ref (rtx x, rtx *ref) |
b2ccb744 UW |
6711 | { |
6712 | int i, j; | |
6713 | const char *fmt; | |
6714 | ||
fd7643fb UW |
6715 | /* Ignore LTREL_BASE references. */ |
6716 | if (GET_CODE (x) == UNSPEC | |
6717 | && XINT (x, 1) == UNSPEC_LTREL_BASE) | |
6718 | return; | |
5af2f3d3 UW |
6719 | /* Likewise POOL_ENTRY insns. */ |
6720 | if (GET_CODE (x) == UNSPEC_VOLATILE | |
6721 | && XINT (x, 1) == UNSPECV_POOL_ENTRY) | |
6722 | return; | |
fd7643fb | 6723 | |
8d933e31 AS |
6724 | gcc_assert (GET_CODE (x) != SYMBOL_REF |
6725 | || !CONSTANT_POOL_ADDRESS_P (x)); | |
585539a1 UW |
6726 | |
6727 | if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_LTREF) | |
b2ccb744 | 6728 | { |
585539a1 | 6729 | rtx sym = XVECEXP (x, 0, 0); |
8d933e31 AS |
6730 | gcc_assert (GET_CODE (sym) == SYMBOL_REF |
6731 | && CONSTANT_POOL_ADDRESS_P (sym)); | |
585539a1 | 6732 | |
b2ccb744 | 6733 | if (*ref == NULL_RTX) |
585539a1 | 6734 | *ref = sym; |
f4aa3848 | 6735 | else |
8d933e31 | 6736 | gcc_assert (*ref == sym); |
585539a1 UW |
6737 | |
6738 | return; | |
b2ccb744 UW |
6739 | } |
6740 | ||
6741 | fmt = GET_RTX_FORMAT (GET_CODE (x)); | |
6742 | for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--) | |
6743 | { | |
6744 | if (fmt[i] == 'e') | |
6745 | { | |
6746 | find_constant_pool_ref (XEXP (x, i), ref); | |
6747 | } | |
6748 | else if (fmt[i] == 'E') | |
6749 | { | |
6750 | for (j = 0; j < XVECLEN (x, i); j++) | |
6751 | find_constant_pool_ref (XVECEXP (x, i, j), ref); | |
6752 | } | |
6753 | } | |
6754 | } | |
6755 | ||
f4aa3848 | 6756 | /* Replace every reference to the annotated literal pool |
585539a1 | 6757 | symbol REF in X by its base plus OFFSET. */ |
b2ccb744 UW |
6758 | |
6759 | static void | |
585539a1 | 6760 | replace_constant_pool_ref (rtx *x, rtx ref, rtx offset) |
b2ccb744 UW |
6761 | { |
6762 | int i, j; | |
6763 | const char *fmt; | |
6764 | ||
8d933e31 | 6765 | gcc_assert (*x != ref); |
b2ccb744 | 6766 | |
585539a1 UW |
6767 | if (GET_CODE (*x) == UNSPEC |
6768 | && XINT (*x, 1) == UNSPEC_LTREF | |
6769 | && XVECEXP (*x, 0, 0) == ref) | |
b2ccb744 | 6770 | { |
585539a1 UW |
6771 | *x = gen_rtx_PLUS (Pmode, XVECEXP (*x, 0, 1), offset); |
6772 | return; | |
b2ccb744 UW |
6773 | } |
6774 | ||
585539a1 UW |
6775 | if (GET_CODE (*x) == PLUS |
6776 | && GET_CODE (XEXP (*x, 1)) == CONST_INT | |
6777 | && GET_CODE (XEXP (*x, 0)) == UNSPEC | |
6778 | && XINT (XEXP (*x, 0), 1) == UNSPEC_LTREF | |
6779 | && XVECEXP (XEXP (*x, 0), 0, 0) == ref) | |
b2ccb744 | 6780 | { |
585539a1 | 6781 | rtx addr = gen_rtx_PLUS (Pmode, XVECEXP (XEXP (*x, 0), 0, 1), offset); |
0a81f074 | 6782 | *x = plus_constant (Pmode, addr, INTVAL (XEXP (*x, 1))); |
585539a1 | 6783 | return; |
b2ccb744 UW |
6784 | } |
6785 | ||
6786 | fmt = GET_RTX_FORMAT (GET_CODE (*x)); | |
6787 | for (i = GET_RTX_LENGTH (GET_CODE (*x)) - 1; i >= 0; i--) | |
6788 | { | |
6789 | if (fmt[i] == 'e') | |
6790 | { | |
585539a1 | 6791 | replace_constant_pool_ref (&XEXP (*x, i), ref, offset); |
b2ccb744 UW |
6792 | } |
6793 | else if (fmt[i] == 'E') | |
6794 | { | |
6795 | for (j = 0; j < XVECLEN (*x, i); j++) | |
585539a1 | 6796 | replace_constant_pool_ref (&XVECEXP (*x, i, j), ref, offset); |
b2ccb744 UW |
6797 | } |
6798 | } | |
6799 | } | |
6800 | ||
c7453384 | 6801 | /* Check whether X contains an UNSPEC_LTREL_BASE. |
fd7643fb | 6802 | Return its constant pool symbol if found, NULL_RTX otherwise. */ |
aee4e0db | 6803 | |
fd7643fb | 6804 | static rtx |
9c808aad | 6805 | find_ltrel_base (rtx x) |
aee4e0db | 6806 | { |
aee4e0db UW |
6807 | int i, j; |
6808 | const char *fmt; | |
6809 | ||
fd7643fb UW |
6810 | if (GET_CODE (x) == UNSPEC |
6811 | && XINT (x, 1) == UNSPEC_LTREL_BASE) | |
6812 | return XVECEXP (x, 0, 0); | |
aee4e0db UW |
6813 | |
6814 | fmt = GET_RTX_FORMAT (GET_CODE (x)); | |
6815 | for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--) | |
6816 | { | |
6817 | if (fmt[i] == 'e') | |
6818 | { | |
fd7643fb UW |
6819 | rtx fnd = find_ltrel_base (XEXP (x, i)); |
6820 | if (fnd) | |
6821 | return fnd; | |
aee4e0db UW |
6822 | } |
6823 | else if (fmt[i] == 'E') | |
6824 | { | |
6825 | for (j = 0; j < XVECLEN (x, i); j++) | |
fd7643fb UW |
6826 | { |
6827 | rtx fnd = find_ltrel_base (XVECEXP (x, i, j)); | |
6828 | if (fnd) | |
6829 | return fnd; | |
6830 | } | |
aee4e0db UW |
6831 | } |
6832 | } | |
6833 | ||
fd7643fb | 6834 | return NULL_RTX; |
aee4e0db UW |
6835 | } |
6836 | ||
585539a1 | 6837 | /* Replace any occurrence of UNSPEC_LTREL_BASE in X with its base. */ |
aee4e0db UW |
6838 | |
6839 | static void | |
585539a1 | 6840 | replace_ltrel_base (rtx *x) |
aee4e0db | 6841 | { |
fd7643fb | 6842 | int i, j; |
aee4e0db UW |
6843 | const char *fmt; |
6844 | ||
fd7643fb UW |
6845 | if (GET_CODE (*x) == UNSPEC |
6846 | && XINT (*x, 1) == UNSPEC_LTREL_BASE) | |
aee4e0db | 6847 | { |
585539a1 | 6848 | *x = XVECEXP (*x, 0, 1); |
fd7643fb | 6849 | return; |
aee4e0db UW |
6850 | } |
6851 | ||
6852 | fmt = GET_RTX_FORMAT (GET_CODE (*x)); | |
6853 | for (i = GET_RTX_LENGTH (GET_CODE (*x)) - 1; i >= 0; i--) | |
6854 | { | |
6855 | if (fmt[i] == 'e') | |
6856 | { | |
585539a1 | 6857 | replace_ltrel_base (&XEXP (*x, i)); |
aee4e0db UW |
6858 | } |
6859 | else if (fmt[i] == 'E') | |
6860 | { | |
6861 | for (j = 0; j < XVECLEN (*x, i); j++) | |
585539a1 | 6862 | replace_ltrel_base (&XVECEXP (*x, i, j)); |
aee4e0db UW |
6863 | } |
6864 | } | |
6865 | } | |
6866 | ||
6867 | ||
fd7643fb | 6868 | /* We keep a list of constants which we have to add to internal |
b2ccb744 UW |
6869 | constant tables in the middle of large functions. */ |
6870 | ||
085261c8 | 6871 | #define NR_C_MODES 31 |
ef4bddc2 | 6872 | machine_mode constant_modes[NR_C_MODES] = |
b2ccb744 | 6873 | { |
4dc19cc0 | 6874 | TFmode, TImode, TDmode, |
085261c8 | 6875 | V16QImode, V8HImode, V4SImode, V2DImode, V4SFmode, V2DFmode, V1TFmode, |
4dc19cc0 | 6876 | DFmode, DImode, DDmode, |
085261c8 | 6877 | V8QImode, V4HImode, V2SImode, V1DImode, V2SFmode, V1DFmode, |
4dc19cc0 | 6878 | SFmode, SImode, SDmode, |
085261c8 | 6879 | V4QImode, V2HImode, V1SImode, V1SFmode, |
b2ccb744 | 6880 | HImode, |
085261c8 AK |
6881 | V2QImode, V1HImode, |
6882 | QImode, | |
6883 | V1QImode | |
b2ccb744 UW |
6884 | }; |
6885 | ||
b2ccb744 UW |
6886 | struct constant |
6887 | { | |
6888 | struct constant *next; | |
6889 | rtx value; | |
775c43d3 | 6890 | rtx_code_label *label; |
b2ccb744 UW |
6891 | }; |
6892 | ||
6893 | struct constant_pool | |
6894 | { | |
6895 | struct constant_pool *next; | |
775c43d3 DM |
6896 | rtx_insn *first_insn; |
6897 | rtx_insn *pool_insn; | |
aee4e0db | 6898 | bitmap insns; |
775c43d3 | 6899 | rtx_insn *emit_pool_after; |
b2ccb744 UW |
6900 | |
6901 | struct constant *constants[NR_C_MODES]; | |
9bb86f41 | 6902 | struct constant *execute; |
775c43d3 | 6903 | rtx_code_label *label; |
b2ccb744 UW |
6904 | int size; |
6905 | }; | |
6906 | ||
ab96de7e AS |
6907 | /* Allocate new constant_pool structure. */ |
6908 | ||
6909 | static struct constant_pool * | |
6910 | s390_alloc_pool (void) | |
6911 | { | |
6912 | struct constant_pool *pool; | |
6913 | int i; | |
6914 | ||
6915 | pool = (struct constant_pool *) xmalloc (sizeof *pool); | |
6916 | pool->next = NULL; | |
6917 | for (i = 0; i < NR_C_MODES; i++) | |
6918 | pool->constants[i] = NULL; | |
6919 | ||
6920 | pool->execute = NULL; | |
6921 | pool->label = gen_label_rtx (); | |
775c43d3 DM |
6922 | pool->first_insn = NULL; |
6923 | pool->pool_insn = NULL; | |
ab96de7e AS |
6924 | pool->insns = BITMAP_ALLOC (NULL); |
6925 | pool->size = 0; | |
775c43d3 | 6926 | pool->emit_pool_after = NULL; |
ab96de7e AS |
6927 | |
6928 | return pool; | |
6929 | } | |
b2ccb744 UW |
6930 | |
6931 | /* Create new constant pool covering instructions starting at INSN | |
6932 | and chain it to the end of POOL_LIST. */ | |
6933 | ||
6934 | static struct constant_pool * | |
775c43d3 | 6935 | s390_start_pool (struct constant_pool **pool_list, rtx_insn *insn) |
b2ccb744 UW |
6936 | { |
6937 | struct constant_pool *pool, **prev; | |
b2ccb744 | 6938 | |
5af2f3d3 | 6939 | pool = s390_alloc_pool (); |
b2ccb744 | 6940 | pool->first_insn = insn; |
aee4e0db | 6941 | |
b2ccb744 UW |
6942 | for (prev = pool_list; *prev; prev = &(*prev)->next) |
6943 | ; | |
6944 | *prev = pool; | |
6945 | ||
6946 | return pool; | |
6947 | } | |
6948 | ||
aee4e0db UW |
6949 | /* End range of instructions covered by POOL at INSN and emit |
6950 | placeholder insn representing the pool. */ | |
b2ccb744 UW |
6951 | |
6952 | static void | |
775c43d3 | 6953 | s390_end_pool (struct constant_pool *pool, rtx_insn *insn) |
b2ccb744 | 6954 | { |
aee4e0db UW |
6955 | rtx pool_size = GEN_INT (pool->size + 8 /* alignment slop */); |
6956 | ||
6957 | if (!insn) | |
6958 | insn = get_last_insn (); | |
6959 | ||
6960 | pool->pool_insn = emit_insn_after (gen_pool (pool_size), insn); | |
6961 | INSN_ADDRESSES_NEW (pool->pool_insn, -1); | |
6962 | } | |
6963 | ||
6964 | /* Add INSN to the list of insns covered by POOL. */ | |
6965 | ||
6966 | static void | |
9c808aad | 6967 | s390_add_pool_insn (struct constant_pool *pool, rtx insn) |
aee4e0db UW |
6968 | { |
6969 | bitmap_set_bit (pool->insns, INSN_UID (insn)); | |
b2ccb744 UW |
6970 | } |
6971 | ||
6972 | /* Return pool out of POOL_LIST that covers INSN. */ | |
6973 | ||
6974 | static struct constant_pool * | |
9c808aad | 6975 | s390_find_pool (struct constant_pool *pool_list, rtx insn) |
b2ccb744 | 6976 | { |
b2ccb744 UW |
6977 | struct constant_pool *pool; |
6978 | ||
b2ccb744 | 6979 | for (pool = pool_list; pool; pool = pool->next) |
aee4e0db | 6980 | if (bitmap_bit_p (pool->insns, INSN_UID (insn))) |
b2ccb744 UW |
6981 | break; |
6982 | ||
6983 | return pool; | |
6984 | } | |
6985 | ||
aee4e0db | 6986 | /* Add constant VAL of mode MODE to the constant pool POOL. */ |
b2ccb744 | 6987 | |
aee4e0db | 6988 | static void |
ef4bddc2 | 6989 | s390_add_constant (struct constant_pool *pool, rtx val, machine_mode mode) |
b2ccb744 UW |
6990 | { |
6991 | struct constant *c; | |
b2ccb744 UW |
6992 | int i; |
6993 | ||
6994 | for (i = 0; i < NR_C_MODES; i++) | |
6995 | if (constant_modes[i] == mode) | |
6996 | break; | |
8d933e31 | 6997 | gcc_assert (i != NR_C_MODES); |
b2ccb744 UW |
6998 | |
6999 | for (c = pool->constants[i]; c != NULL; c = c->next) | |
7000 | if (rtx_equal_p (val, c->value)) | |
7001 | break; | |
7002 | ||
7003 | if (c == NULL) | |
7004 | { | |
7005 | c = (struct constant *) xmalloc (sizeof *c); | |
7006 | c->value = val; | |
7007 | c->label = gen_label_rtx (); | |
7008 | c->next = pool->constants[i]; | |
7009 | pool->constants[i] = c; | |
7010 | pool->size += GET_MODE_SIZE (mode); | |
7011 | } | |
aee4e0db | 7012 | } |
b2ccb744 | 7013 | |
dc66391d RS |
7014 | /* Return an rtx that represents the offset of X from the start of |
7015 | pool POOL. */ | |
7016 | ||
7017 | static rtx | |
7018 | s390_pool_offset (struct constant_pool *pool, rtx x) | |
7019 | { | |
7020 | rtx label; | |
7021 | ||
7022 | label = gen_rtx_LABEL_REF (GET_MODE (x), pool->label); | |
7023 | x = gen_rtx_UNSPEC (GET_MODE (x), gen_rtvec (2, x, label), | |
7024 | UNSPEC_POOL_OFFSET); | |
7025 | return gen_rtx_CONST (GET_MODE (x), x); | |
7026 | } | |
7027 | ||
aee4e0db UW |
7028 | /* Find constant VAL of mode MODE in the constant pool POOL. |
7029 | Return an RTX describing the distance from the start of | |
7030 | the pool to the location of the new constant. */ | |
c7453384 | 7031 | |
aee4e0db | 7032 | static rtx |
9c808aad | 7033 | s390_find_constant (struct constant_pool *pool, rtx val, |
ef4bddc2 | 7034 | machine_mode mode) |
aee4e0db UW |
7035 | { |
7036 | struct constant *c; | |
aee4e0db | 7037 | int i; |
c7453384 | 7038 | |
aee4e0db UW |
7039 | for (i = 0; i < NR_C_MODES; i++) |
7040 | if (constant_modes[i] == mode) | |
7041 | break; | |
8d933e31 | 7042 | gcc_assert (i != NR_C_MODES); |
c7453384 | 7043 | |
aee4e0db UW |
7044 | for (c = pool->constants[i]; c != NULL; c = c->next) |
7045 | if (rtx_equal_p (val, c->value)) | |
7046 | break; | |
c7453384 | 7047 | |
8d933e31 | 7048 | gcc_assert (c); |
c7453384 | 7049 | |
dc66391d | 7050 | return s390_pool_offset (pool, gen_rtx_LABEL_REF (Pmode, c->label)); |
b2ccb744 UW |
7051 | } |
7052 | ||
ab96de7e AS |
7053 | /* Check whether INSN is an execute. Return the label_ref to its |
7054 | execute target template if so, NULL_RTX otherwise. */ | |
7055 | ||
7056 | static rtx | |
7057 | s390_execute_label (rtx insn) | |
7058 | { | |
b64925dc | 7059 | if (NONJUMP_INSN_P (insn) |
ab96de7e AS |
7060 | && GET_CODE (PATTERN (insn)) == PARALLEL |
7061 | && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == UNSPEC | |
7062 | && XINT (XVECEXP (PATTERN (insn), 0, 0), 1) == UNSPEC_EXECUTE) | |
7063 | return XVECEXP (XVECEXP (PATTERN (insn), 0, 0), 0, 2); | |
7064 | ||
7065 | return NULL_RTX; | |
7066 | } | |
7067 | ||
9bb86f41 UW |
7068 | /* Add execute target for INSN to the constant pool POOL. */ |
7069 | ||
7070 | static void | |
7071 | s390_add_execute (struct constant_pool *pool, rtx insn) | |
7072 | { | |
7073 | struct constant *c; | |
7074 | ||
7075 | for (c = pool->execute; c != NULL; c = c->next) | |
7076 | if (INSN_UID (insn) == INSN_UID (c->value)) | |
7077 | break; | |
7078 | ||
7079 | if (c == NULL) | |
7080 | { | |
9bb86f41 UW |
7081 | c = (struct constant *) xmalloc (sizeof *c); |
7082 | c->value = insn; | |
d24959df | 7083 | c->label = gen_label_rtx (); |
9bb86f41 UW |
7084 | c->next = pool->execute; |
7085 | pool->execute = c; | |
d24959df | 7086 | pool->size += 6; |
9bb86f41 UW |
7087 | } |
7088 | } | |
7089 | ||
7090 | /* Find execute target for INSN in the constant pool POOL. | |
7091 | Return an RTX describing the distance from the start of | |
7092 | the pool to the location of the execute target. */ | |
7093 | ||
7094 | static rtx | |
7095 | s390_find_execute (struct constant_pool *pool, rtx insn) | |
7096 | { | |
7097 | struct constant *c; | |
9bb86f41 UW |
7098 | |
7099 | for (c = pool->execute; c != NULL; c = c->next) | |
7100 | if (INSN_UID (insn) == INSN_UID (c->value)) | |
7101 | break; | |
7102 | ||
8d933e31 | 7103 | gcc_assert (c); |
9bb86f41 | 7104 | |
dc66391d | 7105 | return s390_pool_offset (pool, gen_rtx_LABEL_REF (Pmode, c->label)); |
9bb86f41 UW |
7106 | } |
7107 | ||
ab96de7e | 7108 | /* For an execute INSN, extract the execute target template. */ |
9bb86f41 UW |
7109 | |
7110 | static rtx | |
ab96de7e | 7111 | s390_execute_target (rtx insn) |
9bb86f41 | 7112 | { |
ab96de7e AS |
7113 | rtx pattern = PATTERN (insn); |
7114 | gcc_assert (s390_execute_label (insn)); | |
9bb86f41 UW |
7115 | |
7116 | if (XVECLEN (pattern, 0) == 2) | |
7117 | { | |
7118 | pattern = copy_rtx (XVECEXP (pattern, 0, 1)); | |
7119 | } | |
7120 | else | |
7121 | { | |
7122 | rtvec vec = rtvec_alloc (XVECLEN (pattern, 0) - 1); | |
7123 | int i; | |
7124 | ||
7125 | for (i = 0; i < XVECLEN (pattern, 0) - 1; i++) | |
7126 | RTVEC_ELT (vec, i) = copy_rtx (XVECEXP (pattern, 0, i + 1)); | |
7127 | ||
7128 | pattern = gen_rtx_PARALLEL (VOIDmode, vec); | |
7129 | } | |
7130 | ||
7131 | return pattern; | |
7132 | } | |
7133 | ||
7134 | /* Indicate that INSN cannot be duplicated. This is the case for | |
7135 | execute insns that carry a unique label. */ | |
7136 | ||
7137 | static bool | |
ac44248e | 7138 | s390_cannot_copy_insn_p (rtx_insn *insn) |
9bb86f41 UW |
7139 | { |
7140 | rtx label = s390_execute_label (insn); | |
7141 | return label && label != const0_rtx; | |
7142 | } | |
7143 | ||
5af2f3d3 UW |
7144 | /* Dump out the constants in POOL. If REMOTE_LABEL is true, |
7145 | do not emit the pool base label. */ | |
b2ccb744 | 7146 | |
9bb86f41 | 7147 | static void |
5af2f3d3 | 7148 | s390_dump_pool (struct constant_pool *pool, bool remote_label) |
b2ccb744 UW |
7149 | { |
7150 | struct constant *c; | |
775c43d3 | 7151 | rtx_insn *insn = pool->pool_insn; |
b2ccb744 UW |
7152 | int i; |
7153 | ||
9bb86f41 UW |
7154 | /* Switch to rodata section. */ |
7155 | if (TARGET_CPU_ZARCH) | |
7156 | { | |
7157 | insn = emit_insn_after (gen_pool_section_start (), insn); | |
7158 | INSN_ADDRESSES_NEW (insn, -1); | |
7159 | } | |
7160 | ||
7161 | /* Ensure minimum pool alignment. */ | |
9e8327e3 | 7162 | if (TARGET_CPU_ZARCH) |
9bb86f41 | 7163 | insn = emit_insn_after (gen_pool_align (GEN_INT (8)), insn); |
b2ccb744 | 7164 | else |
9bb86f41 | 7165 | insn = emit_insn_after (gen_pool_align (GEN_INT (4)), insn); |
b2ccb744 UW |
7166 | INSN_ADDRESSES_NEW (insn, -1); |
7167 | ||
9bb86f41 | 7168 | /* Emit pool base label. */ |
5af2f3d3 UW |
7169 | if (!remote_label) |
7170 | { | |
7171 | insn = emit_label_after (pool->label, insn); | |
7172 | INSN_ADDRESSES_NEW (insn, -1); | |
7173 | } | |
b2ccb744 UW |
7174 | |
7175 | /* Dump constants in descending alignment requirement order, | |
7176 | ensuring proper alignment for every constant. */ | |
7177 | for (i = 0; i < NR_C_MODES; i++) | |
7178 | for (c = pool->constants[i]; c; c = c->next) | |
7179 | { | |
fd7643fb | 7180 | /* Convert UNSPEC_LTREL_OFFSET unspecs to pool-relative references. */ |
77340500 | 7181 | rtx value = copy_rtx (c->value); |
aee4e0db UW |
7182 | if (GET_CODE (value) == CONST |
7183 | && GET_CODE (XEXP (value, 0)) == UNSPEC | |
fd7643fb | 7184 | && XINT (XEXP (value, 0), 1) == UNSPEC_LTREL_OFFSET |
aee4e0db | 7185 | && XVECLEN (XEXP (value, 0), 0) == 1) |
dc66391d | 7186 | value = s390_pool_offset (pool, XVECEXP (XEXP (value, 0), 0, 0)); |
aee4e0db | 7187 | |
b2ccb744 UW |
7188 | insn = emit_label_after (c->label, insn); |
7189 | INSN_ADDRESSES_NEW (insn, -1); | |
416cf582 | 7190 | |
38899e29 | 7191 | value = gen_rtx_UNSPEC_VOLATILE (constant_modes[i], |
416cf582 UW |
7192 | gen_rtvec (1, value), |
7193 | UNSPECV_POOL_ENTRY); | |
7194 | insn = emit_insn_after (value, insn); | |
b2ccb744 UW |
7195 | INSN_ADDRESSES_NEW (insn, -1); |
7196 | } | |
7197 | ||
9bb86f41 UW |
7198 | /* Ensure minimum alignment for instructions. */ |
7199 | insn = emit_insn_after (gen_pool_align (GEN_INT (2)), insn); | |
b2ccb744 UW |
7200 | INSN_ADDRESSES_NEW (insn, -1); |
7201 | ||
9bb86f41 UW |
7202 | /* Output in-pool execute template insns. */ |
7203 | for (c = pool->execute; c; c = c->next) | |
7204 | { | |
9bb86f41 UW |
7205 | insn = emit_label_after (c->label, insn); |
7206 | INSN_ADDRESSES_NEW (insn, -1); | |
7207 | ||
7208 | insn = emit_insn_after (s390_execute_target (c->value), insn); | |
7209 | INSN_ADDRESSES_NEW (insn, -1); | |
7210 | } | |
7211 | ||
7212 | /* Switch back to previous section. */ | |
7213 | if (TARGET_CPU_ZARCH) | |
7214 | { | |
7215 | insn = emit_insn_after (gen_pool_section_end (), insn); | |
7216 | INSN_ADDRESSES_NEW (insn, -1); | |
7217 | } | |
7218 | ||
b2ccb744 UW |
7219 | insn = emit_barrier_after (insn); |
7220 | INSN_ADDRESSES_NEW (insn, -1); | |
7221 | ||
aee4e0db UW |
7222 | /* Remove placeholder insn. */ |
7223 | remove_insn (pool->pool_insn); | |
9bb86f41 UW |
7224 | } |
7225 | ||
b2ccb744 UW |
7226 | /* Free all memory used by POOL. */ |
7227 | ||
7228 | static void | |
9c808aad | 7229 | s390_free_pool (struct constant_pool *pool) |
b2ccb744 | 7230 | { |
9bb86f41 | 7231 | struct constant *c, *next; |
b2ccb744 UW |
7232 | int i; |
7233 | ||
7234 | for (i = 0; i < NR_C_MODES; i++) | |
9bb86f41 UW |
7235 | for (c = pool->constants[i]; c; c = next) |
7236 | { | |
7237 | next = c->next; | |
7238 | free (c); | |
7239 | } | |
7240 | ||
7241 | for (c = pool->execute; c; c = next) | |
b2ccb744 | 7242 | { |
9bb86f41 UW |
7243 | next = c->next; |
7244 | free (c); | |
b2ccb744 UW |
7245 | } |
7246 | ||
7b210806 | 7247 | BITMAP_FREE (pool->insns); |
b2ccb744 | 7248 | free (pool); |
c7453384 | 7249 | } |
b2ccb744 | 7250 | |
b2ccb744 | 7251 | |
5af2f3d3 UW |
7252 | /* Collect main literal pool. Return NULL on overflow. */ |
7253 | ||
7254 | static struct constant_pool * | |
7255 | s390_mainpool_start (void) | |
7256 | { | |
7257 | struct constant_pool *pool; | |
775c43d3 | 7258 | rtx_insn *insn; |
5af2f3d3 UW |
7259 | |
7260 | pool = s390_alloc_pool (); | |
7261 | ||
7262 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) | |
7263 | { | |
b64925dc | 7264 | if (NONJUMP_INSN_P (insn) |
585539a1 UW |
7265 | && GET_CODE (PATTERN (insn)) == SET |
7266 | && GET_CODE (SET_SRC (PATTERN (insn))) == UNSPEC_VOLATILE | |
7267 | && XINT (SET_SRC (PATTERN (insn)), 1) == UNSPECV_MAIN_POOL) | |
5af2f3d3 | 7268 | { |
177bc204 RS |
7269 | /* There might be two main_pool instructions if base_reg |
7270 | is call-clobbered; one for shrink-wrapped code and one | |
7271 | for the rest. We want to keep the first. */ | |
7272 | if (pool->pool_insn) | |
7273 | { | |
7274 | insn = PREV_INSN (insn); | |
7275 | delete_insn (NEXT_INSN (insn)); | |
7276 | continue; | |
7277 | } | |
5af2f3d3 UW |
7278 | pool->pool_insn = insn; |
7279 | } | |
7280 | ||
d24959df | 7281 | if (!TARGET_CPU_ZARCH && s390_execute_label (insn)) |
9bb86f41 UW |
7282 | { |
7283 | s390_add_execute (pool, insn); | |
7284 | } | |
b64925dc | 7285 | else if (NONJUMP_INSN_P (insn) || CALL_P (insn)) |
5af2f3d3 UW |
7286 | { |
7287 | rtx pool_ref = NULL_RTX; | |
7288 | find_constant_pool_ref (PATTERN (insn), &pool_ref); | |
7289 | if (pool_ref) | |
7290 | { | |
7291 | rtx constant = get_pool_constant (pool_ref); | |
ef4bddc2 | 7292 | machine_mode mode = get_pool_mode (pool_ref); |
5af2f3d3 UW |
7293 | s390_add_constant (pool, constant, mode); |
7294 | } | |
7295 | } | |
03870a04 AK |
7296 | |
7297 | /* If hot/cold partitioning is enabled we have to make sure that | |
7298 | the literal pool is emitted in the same section where the | |
7299 | initialization of the literal pool base pointer takes place. | |
7300 | emit_pool_after is only used in the non-overflow case on non | |
7301 | Z cpus where we can emit the literal pool at the end of the | |
7302 | function body within the text section. */ | |
7303 | if (NOTE_P (insn) | |
b49326f1 AK |
7304 | && NOTE_KIND (insn) == NOTE_INSN_SWITCH_TEXT_SECTIONS |
7305 | && !pool->emit_pool_after) | |
7306 | pool->emit_pool_after = PREV_INSN (insn); | |
5af2f3d3 UW |
7307 | } |
7308 | ||
8d933e31 | 7309 | gcc_assert (pool->pool_insn || pool->size == 0); |
5af2f3d3 UW |
7310 | |
7311 | if (pool->size >= 4096) | |
7312 | { | |
d76e8439 UW |
7313 | /* We're going to chunkify the pool, so remove the main |
7314 | pool placeholder insn. */ | |
7315 | remove_insn (pool->pool_insn); | |
7316 | ||
5af2f3d3 UW |
7317 | s390_free_pool (pool); |
7318 | pool = NULL; | |
7319 | } | |
7320 | ||
03870a04 AK |
7321 | /* If the functions ends with the section where the literal pool |
7322 | should be emitted set the marker to its end. */ | |
b49326f1 | 7323 | if (pool && !pool->emit_pool_after) |
03870a04 AK |
7324 | pool->emit_pool_after = get_last_insn (); |
7325 | ||
5af2f3d3 UW |
7326 | return pool; |
7327 | } | |
7328 | ||
7329 | /* POOL holds the main literal pool as collected by s390_mainpool_start. | |
7330 | Modify the current function to output the pool constants as well as | |
585539a1 | 7331 | the pool register setup instruction. */ |
5af2f3d3 UW |
7332 | |
7333 | static void | |
585539a1 | 7334 | s390_mainpool_finish (struct constant_pool *pool) |
5af2f3d3 | 7335 | { |
91086990 | 7336 | rtx base_reg = cfun->machine->base_reg; |
5af2f3d3 UW |
7337 | |
7338 | /* If the pool is empty, we're done. */ | |
7339 | if (pool->size == 0) | |
7340 | { | |
91086990 UW |
7341 | /* We don't actually need a base register after all. */ |
7342 | cfun->machine->base_reg = NULL_RTX; | |
7343 | ||
7344 | if (pool->pool_insn) | |
7345 | remove_insn (pool->pool_insn); | |
5af2f3d3 UW |
7346 | s390_free_pool (pool); |
7347 | return; | |
7348 | } | |
7349 | ||
7350 | /* We need correct insn addresses. */ | |
7351 | shorten_branches (get_insns ()); | |
7352 | ||
9e8327e3 | 7353 | /* On zSeries, we use a LARL to load the pool register. The pool is |
5af2f3d3 | 7354 | located in the .rodata section, so we emit it after the function. */ |
9e8327e3 | 7355 | if (TARGET_CPU_ZARCH) |
5af2f3d3 | 7356 | { |
17f385d8 DM |
7357 | rtx set = gen_main_base_64 (base_reg, pool->label); |
7358 | rtx_insn *insn = emit_insn_after (set, pool->pool_insn); | |
5af2f3d3 UW |
7359 | INSN_ADDRESSES_NEW (insn, -1); |
7360 | remove_insn (pool->pool_insn); | |
38899e29 EC |
7361 | |
7362 | insn = get_last_insn (); | |
5af2f3d3 UW |
7363 | pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn); |
7364 | INSN_ADDRESSES_NEW (pool->pool_insn, -1); | |
7365 | ||
7366 | s390_dump_pool (pool, 0); | |
7367 | } | |
7368 | ||
9e8327e3 | 7369 | /* On S/390, if the total size of the function's code plus literal pool |
5af2f3d3 UW |
7370 | does not exceed 4096 bytes, we use BASR to set up a function base |
7371 | pointer, and emit the literal pool at the end of the function. */ | |
03870a04 | 7372 | else if (INSN_ADDRESSES (INSN_UID (pool->emit_pool_after)) |
5af2f3d3 UW |
7373 | + pool->size + 8 /* alignment slop */ < 4096) |
7374 | { | |
17f385d8 DM |
7375 | rtx set = gen_main_base_31_small (base_reg, pool->label); |
7376 | rtx_insn *insn = emit_insn_after (set, pool->pool_insn); | |
5af2f3d3 UW |
7377 | INSN_ADDRESSES_NEW (insn, -1); |
7378 | remove_insn (pool->pool_insn); | |
7379 | ||
7380 | insn = emit_label_after (pool->label, insn); | |
7381 | INSN_ADDRESSES_NEW (insn, -1); | |
7382 | ||
03870a04 AK |
7383 | /* emit_pool_after will be set by s390_mainpool_start to the |
7384 | last insn of the section where the literal pool should be | |
7385 | emitted. */ | |
7386 | insn = pool->emit_pool_after; | |
7387 | ||
5af2f3d3 UW |
7388 | pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn); |
7389 | INSN_ADDRESSES_NEW (pool->pool_insn, -1); | |
7390 | ||
7391 | s390_dump_pool (pool, 1); | |
7392 | } | |
7393 | ||
7394 | /* Otherwise, we emit an inline literal pool and use BASR to branch | |
7395 | over it, setting up the pool register at the same time. */ | |
7396 | else | |
7397 | { | |
17f385d8 | 7398 | rtx_code_label *pool_end = gen_label_rtx (); |
5af2f3d3 | 7399 | |
17f385d8 DM |
7400 | rtx pat = gen_main_base_31_large (base_reg, pool->label, pool_end); |
7401 | rtx_insn *insn = emit_jump_insn_after (pat, pool->pool_insn); | |
b0a1ac21 | 7402 | JUMP_LABEL (insn) = pool_end; |
5af2f3d3 UW |
7403 | INSN_ADDRESSES_NEW (insn, -1); |
7404 | remove_insn (pool->pool_insn); | |
7405 | ||
7406 | insn = emit_label_after (pool->label, insn); | |
7407 | INSN_ADDRESSES_NEW (insn, -1); | |
7408 | ||
7409 | pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn); | |
7410 | INSN_ADDRESSES_NEW (pool->pool_insn, -1); | |
7411 | ||
7412 | insn = emit_label_after (pool_end, pool->pool_insn); | |
7413 | INSN_ADDRESSES_NEW (insn, -1); | |
7414 | ||
7415 | s390_dump_pool (pool, 1); | |
7416 | } | |
7417 | ||
7418 | ||
7419 | /* Replace all literal pool references. */ | |
7420 | ||
b32d5189 | 7421 | for (rtx_insn *insn = get_insns (); insn; insn = NEXT_INSN (insn)) |
5af2f3d3 UW |
7422 | { |
7423 | if (INSN_P (insn)) | |
585539a1 | 7424 | replace_ltrel_base (&PATTERN (insn)); |
5af2f3d3 | 7425 | |
b64925dc | 7426 | if (NONJUMP_INSN_P (insn) || CALL_P (insn)) |
5af2f3d3 UW |
7427 | { |
7428 | rtx addr, pool_ref = NULL_RTX; | |
7429 | find_constant_pool_ref (PATTERN (insn), &pool_ref); | |
7430 | if (pool_ref) | |
7431 | { | |
9bb86f41 UW |
7432 | if (s390_execute_label (insn)) |
7433 | addr = s390_find_execute (pool, insn); | |
7434 | else | |
7435 | addr = s390_find_constant (pool, get_pool_constant (pool_ref), | |
7436 | get_pool_mode (pool_ref)); | |
7437 | ||
5af2f3d3 UW |
7438 | replace_constant_pool_ref (&PATTERN (insn), pool_ref, addr); |
7439 | INSN_CODE (insn) = -1; | |
7440 | } | |
7441 | } | |
7442 | } | |
7443 | ||
7444 | ||
7445 | /* Free the pool. */ | |
7446 | s390_free_pool (pool); | |
7447 | } | |
7448 | ||
7449 | /* POOL holds the main literal pool as collected by s390_mainpool_start. | |
7450 | We have decided we cannot use this pool, so revert all changes | |
7451 | to the current function that were done by s390_mainpool_start. */ | |
7452 | static void | |
7453 | s390_mainpool_cancel (struct constant_pool *pool) | |
7454 | { | |
7455 | /* We didn't actually change the instruction stream, so simply | |
7456 | free the pool memory. */ | |
7457 | s390_free_pool (pool); | |
7458 | } | |
7459 | ||
7460 | ||
585539a1 | 7461 | /* Chunkify the literal pool. */ |
9db1d521 | 7462 | |
b2ccb744 UW |
7463 | #define S390_POOL_CHUNK_MIN 0xc00 |
7464 | #define S390_POOL_CHUNK_MAX 0xe00 | |
7465 | ||
c7453384 | 7466 | static struct constant_pool * |
585539a1 | 7467 | s390_chunkify_start (void) |
9db1d521 | 7468 | { |
b2ccb744 UW |
7469 | struct constant_pool *curr_pool = NULL, *pool_list = NULL; |
7470 | int extra_size = 0; | |
7471 | bitmap far_labels; | |
fd7643fb | 7472 | rtx pending_ltrel = NULL_RTX; |
775c43d3 | 7473 | rtx_insn *insn; |
9db1d521 | 7474 | |
9c808aad | 7475 | rtx (*gen_reload_base) (rtx, rtx) = |
9e8327e3 | 7476 | TARGET_CPU_ZARCH? gen_reload_base_64 : gen_reload_base_31; |
aee4e0db UW |
7477 | |
7478 | ||
c3cc6b78 UW |
7479 | /* We need correct insn addresses. */ |
7480 | ||
7481 | shorten_branches (get_insns ()); | |
7482 | ||
fd7643fb | 7483 | /* Scan all insns and move literals to pool chunks. */ |
13e58269 | 7484 | |
13e58269 | 7485 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) |
9db1d521 | 7486 | { |
03870a04 AK |
7487 | bool section_switch_p = false; |
7488 | ||
fd7643fb UW |
7489 | /* Check for pending LTREL_BASE. */ |
7490 | if (INSN_P (insn)) | |
7491 | { | |
7492 | rtx ltrel_base = find_ltrel_base (PATTERN (insn)); | |
7493 | if (ltrel_base) | |
7494 | { | |
8d933e31 AS |
7495 | gcc_assert (ltrel_base == pending_ltrel); |
7496 | pending_ltrel = NULL_RTX; | |
fd7643fb UW |
7497 | } |
7498 | } | |
7499 | ||
d24959df | 7500 | if (!TARGET_CPU_ZARCH && s390_execute_label (insn)) |
9bb86f41 UW |
7501 | { |
7502 | if (!curr_pool) | |
7503 | curr_pool = s390_start_pool (&pool_list, insn); | |
7504 | ||
7505 | s390_add_execute (curr_pool, insn); | |
7506 | s390_add_pool_insn (curr_pool, insn); | |
7507 | } | |
b64925dc | 7508 | else if (NONJUMP_INSN_P (insn) || CALL_P (insn)) |
b2ccb744 | 7509 | { |
aee4e0db | 7510 | rtx pool_ref = NULL_RTX; |
b2ccb744 UW |
7511 | find_constant_pool_ref (PATTERN (insn), &pool_ref); |
7512 | if (pool_ref) | |
7513 | { | |
fd7643fb | 7514 | rtx constant = get_pool_constant (pool_ref); |
ef4bddc2 | 7515 | machine_mode mode = get_pool_mode (pool_ref); |
fd7643fb | 7516 | |
b2ccb744 UW |
7517 | if (!curr_pool) |
7518 | curr_pool = s390_start_pool (&pool_list, insn); | |
7519 | ||
fd7643fb | 7520 | s390_add_constant (curr_pool, constant, mode); |
aee4e0db | 7521 | s390_add_pool_insn (curr_pool, insn); |
aee4e0db | 7522 | |
fd7643fb UW |
7523 | /* Don't split the pool chunk between a LTREL_OFFSET load |
7524 | and the corresponding LTREL_BASE. */ | |
7525 | if (GET_CODE (constant) == CONST | |
7526 | && GET_CODE (XEXP (constant, 0)) == UNSPEC | |
7527 | && XINT (XEXP (constant, 0), 1) == UNSPEC_LTREL_OFFSET) | |
7528 | { | |
8d933e31 | 7529 | gcc_assert (!pending_ltrel); |
fd7643fb UW |
7530 | pending_ltrel = pool_ref; |
7531 | } | |
b2ccb744 UW |
7532 | } |
7533 | } | |
7534 | ||
39718607 | 7535 | if (JUMP_P (insn) || JUMP_TABLE_DATA_P (insn) || LABEL_P (insn)) |
fd7643fb UW |
7536 | { |
7537 | if (curr_pool) | |
7538 | s390_add_pool_insn (curr_pool, insn); | |
7539 | /* An LTREL_BASE must follow within the same basic block. */ | |
8d933e31 | 7540 | gcc_assert (!pending_ltrel); |
fd7643fb | 7541 | } |
aee4e0db | 7542 | |
00fbd5c8 JJ |
7543 | if (NOTE_P (insn)) |
7544 | switch (NOTE_KIND (insn)) | |
7545 | { | |
7546 | case NOTE_INSN_SWITCH_TEXT_SECTIONS: | |
7547 | section_switch_p = true; | |
7548 | break; | |
7549 | case NOTE_INSN_VAR_LOCATION: | |
7550 | case NOTE_INSN_CALL_ARG_LOCATION: | |
7551 | continue; | |
7552 | default: | |
7553 | break; | |
7554 | } | |
03870a04 | 7555 | |
c7453384 | 7556 | if (!curr_pool |
b2ccb744 UW |
7557 | || INSN_ADDRESSES_SIZE () <= (size_t) INSN_UID (insn) |
7558 | || INSN_ADDRESSES (INSN_UID (insn)) == -1) | |
9db1d521 | 7559 | continue; |
13e58269 | 7560 | |
9e8327e3 | 7561 | if (TARGET_CPU_ZARCH) |
9db1d521 | 7562 | { |
b2ccb744 UW |
7563 | if (curr_pool->size < S390_POOL_CHUNK_MAX) |
7564 | continue; | |
13e58269 | 7565 | |
775c43d3 | 7566 | s390_end_pool (curr_pool, NULL); |
b2ccb744 UW |
7567 | curr_pool = NULL; |
7568 | } | |
7569 | else | |
9db1d521 | 7570 | { |
b2ccb744 | 7571 | int chunk_size = INSN_ADDRESSES (INSN_UID (insn)) |
9c808aad | 7572 | - INSN_ADDRESSES (INSN_UID (curr_pool->first_insn)) |
b2ccb744 UW |
7573 | + extra_size; |
7574 | ||
7575 | /* We will later have to insert base register reload insns. | |
7576 | Those will have an effect on code size, which we need to | |
7577 | consider here. This calculation makes rather pessimistic | |
7578 | worst-case assumptions. */ | |
b64925dc | 7579 | if (LABEL_P (insn)) |
b2ccb744 | 7580 | extra_size += 6; |
b2ccb744 UW |
7581 | |
7582 | if (chunk_size < S390_POOL_CHUNK_MIN | |
03870a04 AK |
7583 | && curr_pool->size < S390_POOL_CHUNK_MIN |
7584 | && !section_switch_p) | |
b2ccb744 UW |
7585 | continue; |
7586 | ||
7587 | /* Pool chunks can only be inserted after BARRIERs ... */ | |
b64925dc | 7588 | if (BARRIER_P (insn)) |
b2ccb744 UW |
7589 | { |
7590 | s390_end_pool (curr_pool, insn); | |
7591 | curr_pool = NULL; | |
7592 | extra_size = 0; | |
7593 | } | |
7594 | ||
7595 | /* ... so if we don't find one in time, create one. */ | |
03870a04 AK |
7596 | else if (chunk_size > S390_POOL_CHUNK_MAX |
7597 | || curr_pool->size > S390_POOL_CHUNK_MAX | |
7598 | || section_switch_p) | |
b2ccb744 | 7599 | { |
775c43d3 | 7600 | rtx_insn *label, *jump, *barrier, *next, *prev; |
b2ccb744 | 7601 | |
03870a04 AK |
7602 | if (!section_switch_p) |
7603 | { | |
7604 | /* We can insert the barrier only after a 'real' insn. */ | |
b64925dc | 7605 | if (! NONJUMP_INSN_P (insn) && ! CALL_P (insn)) |
03870a04 AK |
7606 | continue; |
7607 | if (get_attr_length (insn) == 0) | |
7608 | continue; | |
7609 | /* Don't separate LTREL_BASE from the corresponding | |
00fbd5c8 | 7610 | LTREL_OFFSET load. */ |
03870a04 AK |
7611 | if (pending_ltrel) |
7612 | continue; | |
00fbd5c8 JJ |
7613 | next = insn; |
7614 | do | |
7615 | { | |
7616 | insn = next; | |
7617 | next = NEXT_INSN (insn); | |
7618 | } | |
7619 | while (next | |
7620 | && NOTE_P (next) | |
7621 | && (NOTE_KIND (next) == NOTE_INSN_VAR_LOCATION | |
7622 | || NOTE_KIND (next) == NOTE_INSN_CALL_ARG_LOCATION)); | |
03870a04 AK |
7623 | } |
7624 | else | |
7625 | { | |
7626 | gcc_assert (!pending_ltrel); | |
7627 | ||
7628 | /* The old pool has to end before the section switch | |
7629 | note in order to make it part of the current | |
7630 | section. */ | |
7631 | insn = PREV_INSN (insn); | |
7632 | } | |
aee4e0db | 7633 | |
9c808aad | 7634 | label = gen_label_rtx (); |
00fbd5c8 JJ |
7635 | prev = insn; |
7636 | if (prev && NOTE_P (prev)) | |
7637 | prev = prev_nonnote_insn (prev); | |
7638 | if (prev) | |
7639 | jump = emit_jump_insn_after_setloc (gen_jump (label), insn, | |
9d12bc68 | 7640 | INSN_LOCATION (prev)); |
00fbd5c8 JJ |
7641 | else |
7642 | jump = emit_jump_insn_after_noloc (gen_jump (label), insn); | |
b2ccb744 UW |
7643 | barrier = emit_barrier_after (jump); |
7644 | insn = emit_label_after (label, barrier); | |
7645 | JUMP_LABEL (jump) = label; | |
7646 | LABEL_NUSES (label) = 1; | |
7647 | ||
aee4e0db UW |
7648 | INSN_ADDRESSES_NEW (jump, -1); |
7649 | INSN_ADDRESSES_NEW (barrier, -1); | |
b2ccb744 UW |
7650 | INSN_ADDRESSES_NEW (insn, -1); |
7651 | ||
7652 | s390_end_pool (curr_pool, barrier); | |
7653 | curr_pool = NULL; | |
7654 | extra_size = 0; | |
7655 | } | |
13e58269 | 7656 | } |
9db1d521 | 7657 | } |
ce50cae8 | 7658 | |
aee4e0db | 7659 | if (curr_pool) |
775c43d3 | 7660 | s390_end_pool (curr_pool, NULL); |
8d933e31 | 7661 | gcc_assert (!pending_ltrel); |
b2ccb744 | 7662 | |
c7453384 | 7663 | /* Find all labels that are branched into |
13e58269 | 7664 | from an insn belonging to a different chunk. */ |
ce50cae8 | 7665 | |
7b210806 | 7666 | far_labels = BITMAP_ALLOC (NULL); |
6bc627b3 | 7667 | |
13e58269 | 7668 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) |
9db1d521 | 7669 | { |
8942ee0f | 7670 | rtx_jump_table_data *table; |
966f97ac | 7671 | |
b2ccb744 UW |
7672 | /* Labels marked with LABEL_PRESERVE_P can be target |
7673 | of non-local jumps, so we have to mark them. | |
7674 | The same holds for named labels. | |
7675 | ||
7676 | Don't do that, however, if it is the label before | |
7677 | a jump table. */ | |
7678 | ||
b64925dc | 7679 | if (LABEL_P (insn) |
b2ccb744 UW |
7680 | && (LABEL_PRESERVE_P (insn) || LABEL_NAME (insn))) |
7681 | { | |
775c43d3 | 7682 | rtx_insn *vec_insn = NEXT_INSN (insn); |
34f0d87a | 7683 | if (! vec_insn || ! JUMP_TABLE_DATA_P (vec_insn)) |
b2ccb744 UW |
7684 | bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (insn)); |
7685 | } | |
966f97ac JJ |
7686 | /* Check potential targets in a table jump (casesi_jump). */ |
7687 | else if (tablejump_p (insn, NULL, &table)) | |
7688 | { | |
7689 | rtx vec_pat = PATTERN (table); | |
7690 | int i, diff_p = GET_CODE (vec_pat) == ADDR_DIFF_VEC; | |
7691 | ||
7692 | for (i = 0; i < XVECLEN (vec_pat, diff_p); i++) | |
7693 | { | |
7694 | rtx label = XEXP (XVECEXP (vec_pat, diff_p, i), 0); | |
b2ccb744 | 7695 | |
966f97ac JJ |
7696 | if (s390_find_pool (pool_list, label) |
7697 | != s390_find_pool (pool_list, insn)) | |
7698 | bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (label)); | |
7699 | } | |
7700 | } | |
7701 | /* If we have a direct jump (conditional or unconditional), | |
7702 | check all potential targets. */ | |
b64925dc | 7703 | else if (JUMP_P (insn)) |
13e58269 | 7704 | { |
966f97ac | 7705 | rtx pat = PATTERN (insn); |
5fdc1e5d | 7706 | |
966f97ac | 7707 | if (GET_CODE (pat) == PARALLEL) |
0a3bdf9d UW |
7708 | pat = XVECEXP (pat, 0, 0); |
7709 | ||
966f97ac JJ |
7710 | if (GET_CODE (pat) == SET) |
7711 | { | |
aee4e0db | 7712 | rtx label = JUMP_LABEL (insn); |
177bc204 | 7713 | if (label && !ANY_RETURN_P (label)) |
13e58269 | 7714 | { |
966f97ac | 7715 | if (s390_find_pool (pool_list, label) |
b2ccb744 UW |
7716 | != s390_find_pool (pool_list, insn)) |
7717 | bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (label)); | |
13e58269 | 7718 | } |
b2ccb744 | 7719 | } |
966f97ac | 7720 | } |
9db1d521 | 7721 | } |
ce50cae8 | 7722 | |
b2ccb744 UW |
7723 | /* Insert base register reload insns before every pool. */ |
7724 | ||
7725 | for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next) | |
aee4e0db | 7726 | { |
f4aa3848 | 7727 | rtx new_insn = gen_reload_base (cfun->machine->base_reg, |
585539a1 | 7728 | curr_pool->label); |
775c43d3 | 7729 | rtx_insn *insn = curr_pool->first_insn; |
aee4e0db UW |
7730 | INSN_ADDRESSES_NEW (emit_insn_before (new_insn, insn), -1); |
7731 | } | |
b2ccb744 UW |
7732 | |
7733 | /* Insert base register reload insns at every far label. */ | |
13e58269 | 7734 | |
13e58269 | 7735 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) |
b64925dc | 7736 | if (LABEL_P (insn) |
b2ccb744 UW |
7737 | && bitmap_bit_p (far_labels, CODE_LABEL_NUMBER (insn))) |
7738 | { | |
7739 | struct constant_pool *pool = s390_find_pool (pool_list, insn); | |
7740 | if (pool) | |
7741 | { | |
f4aa3848 | 7742 | rtx new_insn = gen_reload_base (cfun->machine->base_reg, |
585539a1 | 7743 | pool->label); |
aee4e0db | 7744 | INSN_ADDRESSES_NEW (emit_insn_after (new_insn, insn), -1); |
b2ccb744 UW |
7745 | } |
7746 | } | |
7747 | ||
aee4e0db | 7748 | |
7b210806 | 7749 | BITMAP_FREE (far_labels); |
13e58269 | 7750 | |
13e58269 UW |
7751 | |
7752 | /* Recompute insn addresses. */ | |
7753 | ||
7754 | init_insn_lengths (); | |
7755 | shorten_branches (get_insns ()); | |
9db1d521 | 7756 | |
aee4e0db UW |
7757 | return pool_list; |
7758 | } | |
9db1d521 | 7759 | |
aee4e0db | 7760 | /* POOL_LIST is a chunk list as prepared by s390_chunkify_start. |
c7453384 | 7761 | After we have decided to use this list, finish implementing |
585539a1 | 7762 | all changes to the current function as required. */ |
c7453384 | 7763 | |
aee4e0db | 7764 | static void |
585539a1 | 7765 | s390_chunkify_finish (struct constant_pool *pool_list) |
aee4e0db | 7766 | { |
aee4e0db | 7767 | struct constant_pool *curr_pool = NULL; |
775c43d3 | 7768 | rtx_insn *insn; |
c7453384 EC |
7769 | |
7770 | ||
aee4e0db UW |
7771 | /* Replace all literal pool references. */ |
7772 | ||
c7453384 | 7773 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) |
aee4e0db | 7774 | { |
fd7643fb | 7775 | if (INSN_P (insn)) |
585539a1 | 7776 | replace_ltrel_base (&PATTERN (insn)); |
fd7643fb | 7777 | |
aee4e0db UW |
7778 | curr_pool = s390_find_pool (pool_list, insn); |
7779 | if (!curr_pool) | |
7780 | continue; | |
7781 | ||
b64925dc | 7782 | if (NONJUMP_INSN_P (insn) || CALL_P (insn)) |
aee4e0db UW |
7783 | { |
7784 | rtx addr, pool_ref = NULL_RTX; | |
7785 | find_constant_pool_ref (PATTERN (insn), &pool_ref); | |
7786 | if (pool_ref) | |
7787 | { | |
9bb86f41 UW |
7788 | if (s390_execute_label (insn)) |
7789 | addr = s390_find_execute (curr_pool, insn); | |
7790 | else | |
7791 | addr = s390_find_constant (curr_pool, | |
7792 | get_pool_constant (pool_ref), | |
7793 | get_pool_mode (pool_ref)); | |
7794 | ||
aee4e0db UW |
7795 | replace_constant_pool_ref (&PATTERN (insn), pool_ref, addr); |
7796 | INSN_CODE (insn) = -1; | |
7797 | } | |
aee4e0db UW |
7798 | } |
7799 | } | |
7800 | ||
7801 | /* Dump out all literal pools. */ | |
c7453384 | 7802 | |
aee4e0db | 7803 | for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next) |
5af2f3d3 | 7804 | s390_dump_pool (curr_pool, 0); |
c7453384 | 7805 | |
aee4e0db UW |
7806 | /* Free pool list. */ |
7807 | ||
7808 | while (pool_list) | |
7809 | { | |
7810 | struct constant_pool *next = pool_list->next; | |
7811 | s390_free_pool (pool_list); | |
7812 | pool_list = next; | |
7813 | } | |
7814 | } | |
7815 | ||
7816 | /* POOL_LIST is a chunk list as prepared by s390_chunkify_start. | |
7817 | We have decided we cannot use this list, so revert all changes | |
7818 | to the current function that were done by s390_chunkify_start. */ | |
c7453384 | 7819 | |
aee4e0db | 7820 | static void |
9c808aad | 7821 | s390_chunkify_cancel (struct constant_pool *pool_list) |
aee4e0db UW |
7822 | { |
7823 | struct constant_pool *curr_pool = NULL; | |
775c43d3 | 7824 | rtx_insn *insn; |
aee4e0db UW |
7825 | |
7826 | /* Remove all pool placeholder insns. */ | |
7827 | ||
7828 | for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next) | |
7829 | { | |
7830 | /* Did we insert an extra barrier? Remove it. */ | |
775c43d3 DM |
7831 | rtx_insn *barrier = PREV_INSN (curr_pool->pool_insn); |
7832 | rtx_insn *jump = barrier? PREV_INSN (barrier) : NULL; | |
7833 | rtx_insn *label = NEXT_INSN (curr_pool->pool_insn); | |
aee4e0db | 7834 | |
b64925dc SB |
7835 | if (jump && JUMP_P (jump) |
7836 | && barrier && BARRIER_P (barrier) | |
7837 | && label && LABEL_P (label) | |
aee4e0db UW |
7838 | && GET_CODE (PATTERN (jump)) == SET |
7839 | && SET_DEST (PATTERN (jump)) == pc_rtx | |
7840 | && GET_CODE (SET_SRC (PATTERN (jump))) == LABEL_REF | |
7841 | && XEXP (SET_SRC (PATTERN (jump)), 0) == label) | |
7842 | { | |
7843 | remove_insn (jump); | |
7844 | remove_insn (barrier); | |
7845 | remove_insn (label); | |
b2ccb744 | 7846 | } |
9db1d521 | 7847 | |
aee4e0db UW |
7848 | remove_insn (curr_pool->pool_insn); |
7849 | } | |
7850 | ||
fd7643fb | 7851 | /* Remove all base register reload insns. */ |
aee4e0db UW |
7852 | |
7853 | for (insn = get_insns (); insn; ) | |
7854 | { | |
775c43d3 | 7855 | rtx_insn *next_insn = NEXT_INSN (insn); |
aee4e0db | 7856 | |
b64925dc | 7857 | if (NONJUMP_INSN_P (insn) |
aee4e0db UW |
7858 | && GET_CODE (PATTERN (insn)) == SET |
7859 | && GET_CODE (SET_SRC (PATTERN (insn))) == UNSPEC | |
fd7643fb | 7860 | && XINT (SET_SRC (PATTERN (insn)), 1) == UNSPEC_RELOAD_BASE) |
aee4e0db | 7861 | remove_insn (insn); |
9db1d521 | 7862 | |
aee4e0db UW |
7863 | insn = next_insn; |
7864 | } | |
7865 | ||
7866 | /* Free pool list. */ | |
9db1d521 | 7867 | |
b2ccb744 | 7868 | while (pool_list) |
9db1d521 | 7869 | { |
b2ccb744 UW |
7870 | struct constant_pool *next = pool_list->next; |
7871 | s390_free_pool (pool_list); | |
7872 | pool_list = next; | |
9db1d521 | 7873 | } |
9db1d521 HP |
7874 | } |
7875 | ||
faeb9bb6 | 7876 | /* Output the constant pool entry EXP in mode MODE with alignment ALIGN. */ |
416cf582 UW |
7877 | |
7878 | void | |
ef4bddc2 | 7879 | s390_output_pool_entry (rtx exp, machine_mode mode, unsigned int align) |
416cf582 UW |
7880 | { |
7881 | REAL_VALUE_TYPE r; | |
7882 | ||
7883 | switch (GET_MODE_CLASS (mode)) | |
7884 | { | |
7885 | case MODE_FLOAT: | |
4dc19cc0 | 7886 | case MODE_DECIMAL_FLOAT: |
8d933e31 | 7887 | gcc_assert (GET_CODE (exp) == CONST_DOUBLE); |
416cf582 UW |
7888 | |
7889 | REAL_VALUE_FROM_CONST_DOUBLE (r, exp); | |
7890 | assemble_real (r, mode, align); | |
7891 | break; | |
7892 | ||
7893 | case MODE_INT: | |
faeb9bb6 | 7894 | assemble_integer (exp, GET_MODE_SIZE (mode), align, 1); |
a7fe25b8 | 7895 | mark_symbol_refs_as_used (exp); |
416cf582 UW |
7896 | break; |
7897 | ||
085261c8 AK |
7898 | case MODE_VECTOR_INT: |
7899 | case MODE_VECTOR_FLOAT: | |
7900 | { | |
7901 | int i; | |
7902 | machine_mode inner_mode; | |
7903 | gcc_assert (GET_CODE (exp) == CONST_VECTOR); | |
7904 | ||
7905 | inner_mode = GET_MODE_INNER (GET_MODE (exp)); | |
7906 | for (i = 0; i < XVECLEN (exp, 0); i++) | |
7907 | s390_output_pool_entry (XVECEXP (exp, 0, i), | |
7908 | inner_mode, | |
7909 | i == 0 | |
7910 | ? align | |
7911 | : GET_MODE_BITSIZE (inner_mode)); | |
7912 | } | |
7913 | break; | |
7914 | ||
416cf582 | 7915 | default: |
8d933e31 | 7916 | gcc_unreachable (); |
416cf582 UW |
7917 | } |
7918 | } | |
7919 | ||
7920 | ||
ab96de7e AS |
7921 | /* Return an RTL expression representing the value of the return address |
7922 | for the frame COUNT steps up from the current frame. FRAME is the | |
7923 | frame pointer of that frame. */ | |
b2ccb744 | 7924 | |
ab96de7e AS |
7925 | rtx |
7926 | s390_return_addr_rtx (int count, rtx frame ATTRIBUTE_UNUSED) | |
b2ccb744 | 7927 | { |
ab96de7e AS |
7928 | int offset; |
7929 | rtx addr; | |
aee4e0db | 7930 | |
ab96de7e | 7931 | /* Without backchain, we fail for all but the current frame. */ |
c3cc6b78 | 7932 | |
ab96de7e AS |
7933 | if (!TARGET_BACKCHAIN && count > 0) |
7934 | return NULL_RTX; | |
c3cc6b78 | 7935 | |
ab96de7e AS |
7936 | /* For the current frame, we need to make sure the initial |
7937 | value of RETURN_REGNUM is actually saved. */ | |
c3cc6b78 | 7938 | |
ab96de7e | 7939 | if (count == 0) |
c3cc6b78 | 7940 | { |
7bcebb25 AK |
7941 | /* On non-z architectures branch splitting could overwrite r14. */ |
7942 | if (TARGET_CPU_ZARCH) | |
7943 | return get_hard_reg_initial_val (Pmode, RETURN_REGNUM); | |
7944 | else | |
7945 | { | |
7946 | cfun_frame_layout.save_return_addr_p = true; | |
7947 | return gen_rtx_MEM (Pmode, return_address_pointer_rtx); | |
7948 | } | |
ab96de7e | 7949 | } |
c3cc6b78 | 7950 | |
ab96de7e | 7951 | if (TARGET_PACKED_STACK) |
9602b6a1 | 7952 | offset = -2 * UNITS_PER_LONG; |
ab96de7e | 7953 | else |
9602b6a1 | 7954 | offset = RETURN_REGNUM * UNITS_PER_LONG; |
c3cc6b78 | 7955 | |
0a81f074 | 7956 | addr = plus_constant (Pmode, frame, offset); |
ab96de7e AS |
7957 | addr = memory_address (Pmode, addr); |
7958 | return gen_rtx_MEM (Pmode, addr); | |
7959 | } | |
c3cc6b78 | 7960 | |
ab96de7e AS |
7961 | /* Return an RTL expression representing the back chain stored in |
7962 | the current stack frame. */ | |
545d16ff | 7963 | |
ab96de7e AS |
7964 | rtx |
7965 | s390_back_chain_rtx (void) | |
7966 | { | |
7967 | rtx chain; | |
545d16ff | 7968 | |
ab96de7e | 7969 | gcc_assert (TARGET_BACKCHAIN); |
545d16ff | 7970 | |
ab96de7e | 7971 | if (TARGET_PACKED_STACK) |
0a81f074 | 7972 | chain = plus_constant (Pmode, stack_pointer_rtx, |
9602b6a1 | 7973 | STACK_POINTER_OFFSET - UNITS_PER_LONG); |
ab96de7e AS |
7974 | else |
7975 | chain = stack_pointer_rtx; | |
545d16ff | 7976 | |
ab96de7e AS |
7977 | chain = gen_rtx_MEM (Pmode, chain); |
7978 | return chain; | |
7979 | } | |
c3cc6b78 | 7980 | |
ab96de7e AS |
7981 | /* Find first call clobbered register unused in a function. |
7982 | This could be used as base register in a leaf function | |
7983 | or for holding the return address before epilogue. */ | |
c3cc6b78 | 7984 | |
ab96de7e AS |
7985 | static int |
7986 | find_unused_clobbered_reg (void) | |
7987 | { | |
7988 | int i; | |
7989 | for (i = 0; i < 6; i++) | |
6fb5fa3c | 7990 | if (!df_regs_ever_live_p (i)) |
ab96de7e AS |
7991 | return i; |
7992 | return 0; | |
7993 | } | |
c3cc6b78 | 7994 | |
7bcebb25 | 7995 | |
f4aa3848 | 7996 | /* Helper function for s390_regs_ever_clobbered. Sets the fields in DATA for all |
7bcebb25 AK |
7997 | clobbered hard regs in SETREG. */ |
7998 | ||
7999 | static void | |
7bc980e1 | 8000 | s390_reg_clobbered_rtx (rtx setreg, const_rtx set_insn ATTRIBUTE_UNUSED, void *data) |
7bcebb25 | 8001 | { |
6455a49e | 8002 | char *regs_ever_clobbered = (char *)data; |
7bcebb25 | 8003 | unsigned int i, regno; |
ef4bddc2 | 8004 | machine_mode mode = GET_MODE (setreg); |
7bcebb25 AK |
8005 | |
8006 | if (GET_CODE (setreg) == SUBREG) | |
8007 | { | |
8008 | rtx inner = SUBREG_REG (setreg); | |
5a3fe9b6 | 8009 | if (!GENERAL_REG_P (inner) && !FP_REG_P (inner)) |
7bcebb25 AK |
8010 | return; |
8011 | regno = subreg_regno (setreg); | |
8012 | } | |
5a3fe9b6 | 8013 | else if (GENERAL_REG_P (setreg) || FP_REG_P (setreg)) |
7bcebb25 AK |
8014 | regno = REGNO (setreg); |
8015 | else | |
8016 | return; | |
8017 | ||
8018 | for (i = regno; | |
8019 | i < regno + HARD_REGNO_NREGS (regno, mode); | |
8020 | i++) | |
8021 | regs_ever_clobbered[i] = 1; | |
8022 | } | |
8023 | ||
8024 | /* Walks through all basic blocks of the current function looking | |
8025 | for clobbered hard regs using s390_reg_clobbered_rtx. The fields | |
8026 | of the passed integer array REGS_EVER_CLOBBERED are set to one for | |
8027 | each of those regs. */ | |
8028 | ||
8029 | static void | |
6455a49e | 8030 | s390_regs_ever_clobbered (char regs_ever_clobbered[]) |
7bcebb25 AK |
8031 | { |
8032 | basic_block cur_bb; | |
775c43d3 | 8033 | rtx_insn *cur_insn; |
7bcebb25 AK |
8034 | unsigned int i; |
8035 | ||
6455a49e | 8036 | memset (regs_ever_clobbered, 0, 32); |
7bcebb25 AK |
8037 | |
8038 | /* For non-leaf functions we have to consider all call clobbered regs to be | |
8039 | clobbered. */ | |
416ff32e | 8040 | if (!crtl->is_leaf) |
7bcebb25 | 8041 | { |
5a3fe9b6 | 8042 | for (i = 0; i < 32; i++) |
7bcebb25 AK |
8043 | regs_ever_clobbered[i] = call_really_used_regs[i]; |
8044 | } | |
8045 | ||
8046 | /* Make the "magic" eh_return registers live if necessary. For regs_ever_live | |
8047 | this work is done by liveness analysis (mark_regs_live_at_end). | |
8048 | Special care is needed for functions containing landing pads. Landing pads | |
8049 | may use the eh registers, but the code which sets these registers is not | |
8050 | contained in that function. Hence s390_regs_ever_clobbered is not able to | |
8051 | deal with this automatically. */ | |
e3b5732b | 8052 | if (crtl->calls_eh_return || cfun->machine->has_landing_pad_p) |
7bcebb25 | 8053 | for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM ; i++) |
f4aa3848 AK |
8054 | if (crtl->calls_eh_return |
8055 | || (cfun->machine->has_landing_pad_p | |
6fb5fa3c | 8056 | && df_regs_ever_live_p (EH_RETURN_DATA_REGNO (i)))) |
297a777d | 8057 | regs_ever_clobbered[EH_RETURN_DATA_REGNO (i)] = 1; |
7bcebb25 AK |
8058 | |
8059 | /* For nonlocal gotos all call-saved registers have to be saved. | |
8060 | This flag is also set for the unwinding code in libgcc. | |
8061 | See expand_builtin_unwind_init. For regs_ever_live this is done by | |
8062 | reload. */ | |
6455a49e | 8063 | if (crtl->saves_all_registers) |
5a3fe9b6 | 8064 | for (i = 0; i < 32; i++) |
7bcebb25 AK |
8065 | if (!call_really_used_regs[i]) |
8066 | regs_ever_clobbered[i] = 1; | |
8067 | ||
11cd3bed | 8068 | FOR_EACH_BB_FN (cur_bb, cfun) |
7bcebb25 AK |
8069 | { |
8070 | FOR_BB_INSNS (cur_bb, cur_insn) | |
8071 | { | |
6455a49e AK |
8072 | rtx pat; |
8073 | ||
8074 | if (!INSN_P (cur_insn)) | |
8075 | continue; | |
8076 | ||
8077 | pat = PATTERN (cur_insn); | |
8078 | ||
8079 | /* Ignore GPR restore insns. */ | |
8080 | if (epilogue_completed && RTX_FRAME_RELATED_P (cur_insn)) | |
8081 | { | |
8082 | if (GET_CODE (pat) == SET | |
8083 | && GENERAL_REG_P (SET_DEST (pat))) | |
8084 | { | |
8085 | /* lgdr */ | |
8086 | if (GET_MODE (SET_SRC (pat)) == DImode | |
8087 | && FP_REG_P (SET_SRC (pat))) | |
8088 | continue; | |
8089 | ||
8090 | /* l / lg */ | |
8091 | if (GET_CODE (SET_SRC (pat)) == MEM) | |
8092 | continue; | |
8093 | } | |
8094 | ||
8095 | /* lm / lmg */ | |
8096 | if (GET_CODE (pat) == PARALLEL | |
8097 | && load_multiple_operation (pat, VOIDmode)) | |
8098 | continue; | |
8099 | } | |
8100 | ||
8101 | note_stores (pat, | |
8102 | s390_reg_clobbered_rtx, | |
8103 | regs_ever_clobbered); | |
7bcebb25 AK |
8104 | } |
8105 | } | |
8106 | } | |
8107 | ||
f4aa3848 AK |
8108 | /* Determine the frame area which actually has to be accessed |
8109 | in the function epilogue. The values are stored at the | |
ab96de7e | 8110 | given pointers AREA_BOTTOM (address of the lowest used stack |
f4aa3848 | 8111 | address) and AREA_TOP (address of the first item which does |
ab96de7e | 8112 | not belong to the stack frame). */ |
545d16ff | 8113 | |
ab96de7e AS |
8114 | static void |
8115 | s390_frame_area (int *area_bottom, int *area_top) | |
8116 | { | |
8117 | int b, t; | |
545d16ff | 8118 | |
ab96de7e AS |
8119 | b = INT_MAX; |
8120 | t = INT_MIN; | |
adf39f8f AK |
8121 | |
8122 | if (cfun_frame_layout.first_restore_gpr != -1) | |
8123 | { | |
8124 | b = (cfun_frame_layout.gprs_offset | |
9602b6a1 | 8125 | + cfun_frame_layout.first_restore_gpr * UNITS_PER_LONG); |
adf39f8f | 8126 | t = b + (cfun_frame_layout.last_restore_gpr |
9602b6a1 | 8127 | - cfun_frame_layout.first_restore_gpr + 1) * UNITS_PER_LONG; |
adf39f8f AK |
8128 | } |
8129 | ||
8130 | if (TARGET_64BIT && cfun_save_high_fprs_p) | |
8131 | { | |
8132 | b = MIN (b, cfun_frame_layout.f8_offset); | |
8133 | t = MAX (t, (cfun_frame_layout.f8_offset | |
8134 | + cfun_frame_layout.high_fprs * 8)); | |
8135 | } | |
8136 | ||
8137 | if (!TARGET_64BIT) | |
b89b22fc | 8138 | { |
2cf4c39e | 8139 | if (cfun_fpr_save_p (FPR4_REGNUM)) |
adf39f8f | 8140 | { |
b89b22fc AK |
8141 | b = MIN (b, cfun_frame_layout.f4_offset); |
8142 | t = MAX (t, cfun_frame_layout.f4_offset + 8); | |
adf39f8f | 8143 | } |
2cf4c39e | 8144 | if (cfun_fpr_save_p (FPR6_REGNUM)) |
b89b22fc AK |
8145 | { |
8146 | b = MIN (b, cfun_frame_layout.f4_offset + 8); | |
8147 | t = MAX (t, cfun_frame_layout.f4_offset + 16); | |
8148 | } | |
8149 | } | |
adf39f8f AK |
8150 | *area_bottom = b; |
8151 | *area_top = t; | |
8152 | } | |
6455a49e AK |
8153 | /* Update gpr_save_slots in the frame layout trying to make use of |
8154 | FPRs as GPR save slots. | |
8155 | This is a helper routine of s390_register_info. */ | |
4023fb28 UW |
8156 | |
8157 | static void | |
6455a49e | 8158 | s390_register_info_gprtofpr () |
4023fb28 | 8159 | { |
6455a49e | 8160 | int save_reg_slot = FPR0_REGNUM; |
4023fb28 | 8161 | int i, j; |
4023fb28 | 8162 | |
6455a49e AK |
8163 | if (!TARGET_Z10 || !TARGET_HARD_FLOAT || !crtl->is_leaf) |
8164 | return; | |
7bcebb25 | 8165 | |
6455a49e | 8166 | for (i = 15; i >= 6; i--) |
5a3fe9b6 | 8167 | { |
6455a49e AK |
8168 | if (cfun_gpr_save_slot (i) == 0) |
8169 | continue; | |
36c0bd4f | 8170 | |
6455a49e AK |
8171 | /* Advance to the next FP register which can be used as a |
8172 | GPR save slot. */ | |
8173 | while ((!call_really_used_regs[save_reg_slot] | |
8174 | || df_regs_ever_live_p (save_reg_slot) | |
8175 | || cfun_fpr_save_p (save_reg_slot)) | |
8176 | && FP_REGNO_P (save_reg_slot)) | |
8177 | save_reg_slot++; | |
8178 | if (!FP_REGNO_P (save_reg_slot)) | |
8179 | { | |
8180 | /* We only want to use ldgr/lgdr if we can get rid of | |
8181 | stm/lm entirely. So undo the gpr slot allocation in | |
8182 | case we ran out of FPR save slots. */ | |
8183 | for (j = 6; j <= 15; j++) | |
8184 | if (FP_REGNO_P (cfun_gpr_save_slot (j))) | |
8185 | cfun_gpr_save_slot (j) = -1; | |
8186 | break; | |
36c0bd4f | 8187 | } |
6455a49e | 8188 | cfun_gpr_save_slot (i) = save_reg_slot++; |
5a3fe9b6 | 8189 | } |
6455a49e | 8190 | } |
5a3fe9b6 | 8191 | |
6455a49e AK |
8192 | /* Set the bits in fpr_bitmap for FPRs which need to be saved due to |
8193 | stdarg. | |
8194 | This is a helper routine for s390_register_info. */ | |
7bcebb25 | 8195 | |
6455a49e AK |
8196 | static void |
8197 | s390_register_info_stdarg_fpr () | |
8198 | { | |
8199 | int i; | |
8200 | int min_fpr; | |
8201 | int max_fpr; | |
8202 | ||
8203 | /* Save the FP argument regs for stdarg. f0, f2 for 31 bit and | |
8204 | f0-f4 for 64 bit. */ | |
8205 | if (!cfun->stdarg | |
8206 | || !TARGET_HARD_FLOAT | |
8207 | || !cfun->va_list_fpr_size | |
8208 | || crtl->args.info.fprs >= FP_ARG_NUM_REG) | |
8209 | return; | |
8210 | ||
8211 | min_fpr = crtl->args.info.fprs; | |
8212 | max_fpr = min_fpr + cfun->va_list_fpr_size; | |
8213 | if (max_fpr > FP_ARG_NUM_REG) | |
8214 | max_fpr = FP_ARG_NUM_REG; | |
8215 | ||
6455a49e AK |
8216 | for (i = min_fpr; i < max_fpr; i++) |
8217 | cfun_set_fpr_save (i + FPR0_REGNUM); | |
8218 | } | |
8219 | ||
8220 | /* Reserve the GPR save slots for GPRs which need to be saved due to | |
8221 | stdarg. | |
8222 | This is a helper routine for s390_register_info. */ | |
8223 | ||
8224 | static void | |
8225 | s390_register_info_stdarg_gpr () | |
8226 | { | |
8227 | int i; | |
8228 | int min_gpr; | |
8229 | int max_gpr; | |
8230 | ||
8231 | if (!cfun->stdarg | |
8232 | || !cfun->va_list_gpr_size | |
8233 | || crtl->args.info.gprs >= GP_ARG_NUM_REG) | |
8234 | return; | |
8235 | ||
8236 | min_gpr = crtl->args.info.gprs; | |
8237 | max_gpr = min_gpr + cfun->va_list_gpr_size; | |
8238 | if (max_gpr > GP_ARG_NUM_REG) | |
8239 | max_gpr = GP_ARG_NUM_REG; | |
8240 | ||
8241 | for (i = min_gpr; i < max_gpr; i++) | |
8242 | cfun_gpr_save_slot (2 + i) = -1; | |
8243 | } | |
8244 | ||
8245 | /* The GPR and FPR save slots in cfun->machine->frame_layout are set | |
8246 | for registers which need to be saved in function prologue. | |
8247 | This function can be used until the insns emitted for save/restore | |
8248 | of the regs are visible in the RTL stream. */ | |
8249 | ||
8250 | static void | |
8251 | s390_register_info () | |
8252 | { | |
8253 | int i, j; | |
8254 | char clobbered_regs[32]; | |
8255 | ||
8256 | gcc_assert (!epilogue_completed); | |
8257 | ||
8258 | if (reload_completed) | |
8259 | /* After reload we rely on our own routine to determine which | |
8260 | registers need saving. */ | |
8261 | s390_regs_ever_clobbered (clobbered_regs); | |
8262 | else | |
8263 | /* During reload we use regs_ever_live as a base since reload | |
8264 | does changes in there which we otherwise would not be aware | |
8265 | of. */ | |
8266 | for (i = 0; i < 32; i++) | |
8267 | clobbered_regs[i] = df_regs_ever_live_p (i); | |
8268 | ||
8269 | for (i = 0; i < 32; i++) | |
8270 | clobbered_regs[i] = clobbered_regs[i] && !global_regs[i]; | |
8271 | ||
8272 | /* Mark the call-saved FPRs which need to be saved. | |
8273 | This needs to be done before checking the special GPRs since the | |
8274 | stack pointer usage depends on whether high FPRs have to be saved | |
8275 | or not. */ | |
8276 | cfun_frame_layout.fpr_bitmap = 0; | |
8277 | cfun_frame_layout.high_fprs = 0; | |
8278 | for (i = FPR0_REGNUM; i <= FPR15_REGNUM; i++) | |
8279 | if (clobbered_regs[i] && !call_really_used_regs[i]) | |
8280 | { | |
8281 | cfun_set_fpr_save (i); | |
8282 | if (i >= FPR8_REGNUM) | |
8283 | cfun_frame_layout.high_fprs++; | |
8284 | } | |
c3cc6b78 | 8285 | |
b767fc11 | 8286 | if (flag_pic) |
f4aa3848 | 8287 | clobbered_regs[PIC_OFFSET_TABLE_REGNUM] |
6455a49e | 8288 | |= !!df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM); |
91086990 | 8289 | |
f4aa3848 | 8290 | clobbered_regs[BASE_REGNUM] |
e2df5c1d | 8291 | |= (cfun->machine->base_reg |
6455a49e | 8292 | && REGNO (cfun->machine->base_reg) == BASE_REGNUM); |
91086990 | 8293 | |
6455a49e AK |
8294 | clobbered_regs[HARD_FRAME_POINTER_REGNUM] |
8295 | |= !!frame_pointer_needed; | |
8296 | ||
8297 | /* On pre z900 machines this might take until machine dependent | |
8298 | reorg to decide. | |
8299 | save_return_addr_p will only be set on non-zarch machines so | |
8300 | there is no risk that r14 goes into an FPR instead of a stack | |
8301 | slot. */ | |
7bcebb25 | 8302 | clobbered_regs[RETURN_REGNUM] |
416ff32e | 8303 | |= (!crtl->is_leaf |
dc4477f5 | 8304 | || TARGET_TPF_PROFILING |
e2df5c1d UW |
8305 | || cfun->machine->split_branches_pending_p |
8306 | || cfun_frame_layout.save_return_addr_p | |
6455a49e | 8307 | || crtl->calls_eh_return); |
91086990 | 8308 | |
7bcebb25 | 8309 | clobbered_regs[STACK_POINTER_REGNUM] |
416ff32e | 8310 | |= (!crtl->is_leaf |
e2df5c1d UW |
8311 | || TARGET_TPF_PROFILING |
8312 | || cfun_save_high_fprs_p | |
8313 | || get_frame_size () > 0 | |
36c0bd4f | 8314 | || (reload_completed && cfun_frame_layout.frame_size > 0) |
6455a49e AK |
8315 | || cfun->calls_alloca); |
8316 | ||
8317 | memset (cfun_frame_layout.gpr_save_slots, 0, 16); | |
7bcebb25 | 8318 | |
b767fc11 | 8319 | for (i = 6; i < 16; i++) |
6455a49e AK |
8320 | if (clobbered_regs[i]) |
8321 | cfun_gpr_save_slot (i) = -1; | |
c3cc6b78 | 8322 | |
6455a49e AK |
8323 | s390_register_info_stdarg_fpr (); |
8324 | s390_register_info_gprtofpr (); | |
fb3712f6 | 8325 | |
6455a49e AK |
8326 | /* First find the range of GPRs to be restored. Vararg regs don't |
8327 | need to be restored so we do it before assigning slots to the | |
8328 | vararg GPRs. */ | |
8329 | for (i = 0; i < 16 && cfun_gpr_save_slot (i) != -1; i++); | |
8330 | for (j = 15; j > i && cfun_gpr_save_slot (j) != -1; j--); | |
8331 | cfun_frame_layout.first_restore_gpr = (i == 16) ? -1 : i; | |
8332 | cfun_frame_layout.last_restore_gpr = (i == 16) ? -1 : j; | |
fb3712f6 | 8333 | |
6455a49e AK |
8334 | /* stdarg functions might need to save GPRs 2 to 6. This might |
8335 | override the GPR->FPR save decision made above for r6 since | |
8336 | vararg regs must go to the stack. */ | |
8337 | s390_register_info_stdarg_gpr (); | |
f4aa3848 | 8338 | |
6455a49e AK |
8339 | /* Now the range of GPRs which need saving. */ |
8340 | for (i = 0; i < 16 && cfun_gpr_save_slot (i) != -1; i++); | |
8341 | for (j = 15; j > i && cfun_gpr_save_slot (j) != -1; j--); | |
8342 | cfun_frame_layout.first_save_gpr = (i == 16) ? -1 : i; | |
8343 | cfun_frame_layout.last_save_gpr = (i == 16) ? -1 : j; | |
8344 | } | |
c3cc6b78 | 8345 | |
6455a49e AK |
8346 | /* This function is called by s390_optimize_prologue in order to get |
8347 | rid of unnecessary GPR save/restore instructions. The register info | |
8348 | for the GPRs is re-computed and the ranges are re-calculated. */ | |
29a79fcf | 8349 | |
6455a49e AK |
8350 | static void |
8351 | s390_optimize_register_info () | |
8352 | { | |
8353 | char clobbered_regs[32]; | |
8354 | int i, j; | |
29a79fcf | 8355 | |
6455a49e AK |
8356 | gcc_assert (epilogue_completed); |
8357 | gcc_assert (!cfun->machine->split_branches_pending_p); | |
b767fc11 | 8358 | |
6455a49e | 8359 | s390_regs_ever_clobbered (clobbered_regs); |
29a79fcf | 8360 | |
6455a49e AK |
8361 | for (i = 0; i < 32; i++) |
8362 | clobbered_regs[i] = clobbered_regs[i] && !global_regs[i]; | |
29a79fcf | 8363 | |
6455a49e AK |
8364 | /* There is still special treatment needed for cases invisible to |
8365 | s390_regs_ever_clobbered. */ | |
8366 | clobbered_regs[RETURN_REGNUM] | |
8367 | |= (TARGET_TPF_PROFILING | |
8368 | /* When expanding builtin_return_addr in ESA mode we do not | |
8369 | know whether r14 will later be needed as scratch reg when | |
8370 | doing branch splitting. So the builtin always accesses the | |
8371 | r14 save slot and we need to stick to the save/restore | |
8372 | decision for r14 even if it turns out that it didn't get | |
8373 | clobbered. */ | |
8374 | || cfun_frame_layout.save_return_addr_p | |
8375 | || crtl->calls_eh_return); | |
8376 | ||
8377 | memset (cfun_frame_layout.gpr_save_slots, 0, 6); | |
8378 | ||
8379 | for (i = 6; i < 16; i++) | |
8380 | if (!clobbered_regs[i]) | |
8381 | cfun_gpr_save_slot (i) = 0; | |
8382 | ||
8383 | for (i = 0; i < 16 && cfun_gpr_save_slot (i) != -1; i++); | |
8384 | for (j = 15; j > i && cfun_gpr_save_slot (j) != -1; j--); | |
8385 | cfun_frame_layout.first_restore_gpr = (i == 16) ? -1 : i; | |
8386 | cfun_frame_layout.last_restore_gpr = (i == 16) ? -1 : j; | |
8387 | ||
8388 | s390_register_info_stdarg_gpr (); | |
8389 | ||
8390 | for (i = 0; i < 16 && cfun_gpr_save_slot (i) != -1; i++); | |
8391 | for (j = 15; j > i && cfun_gpr_save_slot (j) != -1; j--); | |
8392 | cfun_frame_layout.first_save_gpr = (i == 16) ? -1 : i; | |
8393 | cfun_frame_layout.last_save_gpr = (i == 16) ? -1 : j; | |
adf39f8f AK |
8394 | } |
8395 | ||
91086990 | 8396 | /* Fill cfun->machine with info about frame of current function. */ |
adf39f8f AK |
8397 | |
8398 | static void | |
91086990 | 8399 | s390_frame_info (void) |
adf39f8f | 8400 | { |
74129172 | 8401 | HOST_WIDE_INT lowest_offset; |
adf39f8f | 8402 | |
6455a49e AK |
8403 | cfun_frame_layout.first_save_gpr_slot = cfun_frame_layout.first_save_gpr; |
8404 | cfun_frame_layout.last_save_gpr_slot = cfun_frame_layout.last_save_gpr; | |
8405 | ||
8406 | /* The va_arg builtin uses a constant distance of 16 * | |
8407 | UNITS_PER_LONG (r0-r15) to reach the FPRs from the reg_save_area | |
8408 | pointer. So even if we are going to save the stack pointer in an | |
8409 | FPR we need the stack space in order to keep the offsets | |
8410 | correct. */ | |
8411 | if (cfun->stdarg && cfun_save_arg_fprs_p) | |
8412 | { | |
8413 | cfun_frame_layout.last_save_gpr_slot = STACK_POINTER_REGNUM; | |
8414 | ||
8415 | if (cfun_frame_layout.first_save_gpr_slot == -1) | |
8416 | cfun_frame_layout.first_save_gpr_slot = STACK_POINTER_REGNUM; | |
8417 | } | |
8418 | ||
adf39f8f | 8419 | cfun_frame_layout.frame_size = get_frame_size (); |
adf39f8f | 8420 | if (!TARGET_64BIT && cfun_frame_layout.frame_size > 0x7fff0000) |
40fecdd6 JM |
8421 | fatal_error (input_location, |
8422 | "total size of local variables exceeds architecture limit"); | |
f4aa3848 | 8423 | |
b3d31392 | 8424 | if (!TARGET_PACKED_STACK) |
adf39f8f | 8425 | { |
74129172 | 8426 | /* Fixed stack layout. */ |
adf39f8f | 8427 | cfun_frame_layout.backchain_offset = 0; |
9602b6a1 | 8428 | cfun_frame_layout.f0_offset = 16 * UNITS_PER_LONG; |
adf39f8f AK |
8429 | cfun_frame_layout.f4_offset = cfun_frame_layout.f0_offset + 2 * 8; |
8430 | cfun_frame_layout.f8_offset = -cfun_frame_layout.high_fprs * 8; | |
fb3712f6 | 8431 | cfun_frame_layout.gprs_offset = (cfun_frame_layout.first_save_gpr_slot |
9602b6a1 | 8432 | * UNITS_PER_LONG); |
adf39f8f | 8433 | } |
74129172 | 8434 | else if (TARGET_BACKCHAIN) |
adf39f8f | 8435 | { |
74129172 AK |
8436 | /* Kernel stack layout - packed stack, backchain, no float */ |
8437 | gcc_assert (TARGET_SOFT_FLOAT); | |
adf39f8f | 8438 | cfun_frame_layout.backchain_offset = (STACK_POINTER_OFFSET |
9602b6a1 | 8439 | - UNITS_PER_LONG); |
74129172 AK |
8440 | |
8441 | /* The distance between the backchain and the return address | |
8442 | save slot must not change. So we always need a slot for the | |
8443 | stack pointer which resides in between. */ | |
8444 | cfun_frame_layout.last_save_gpr_slot = STACK_POINTER_REGNUM; | |
8445 | ||
f4aa3848 | 8446 | cfun_frame_layout.gprs_offset |
74129172 | 8447 | = cfun_frame_layout.backchain_offset - cfun_gprs_save_area_size; |
f4aa3848 | 8448 | |
74129172 AK |
8449 | /* FPRs will not be saved. Nevertheless pick sane values to |
8450 | keep area calculations valid. */ | |
8451 | cfun_frame_layout.f0_offset = | |
8452 | cfun_frame_layout.f4_offset = | |
8453 | cfun_frame_layout.f8_offset = cfun_frame_layout.gprs_offset; | |
adf39f8f | 8454 | } |
74129172 | 8455 | else |
adf39f8f | 8456 | { |
e179df83 AK |
8457 | int num_fprs; |
8458 | ||
74129172 | 8459 | /* Packed stack layout without backchain. */ |
f4aa3848 | 8460 | |
e179df83 AK |
8461 | /* With stdarg FPRs need their dedicated slots. */ |
8462 | num_fprs = (TARGET_64BIT && cfun->stdarg ? 2 | |
8463 | : (cfun_fpr_save_p (FPR4_REGNUM) + | |
8464 | cfun_fpr_save_p (FPR6_REGNUM))); | |
8465 | cfun_frame_layout.f4_offset = STACK_POINTER_OFFSET - 8 * num_fprs; | |
8466 | ||
8467 | num_fprs = (cfun->stdarg ? 2 | |
8468 | : (cfun_fpr_save_p (FPR0_REGNUM) | |
8469 | + cfun_fpr_save_p (FPR2_REGNUM))); | |
8470 | cfun_frame_layout.f0_offset = cfun_frame_layout.f4_offset - 8 * num_fprs; | |
f4aa3848 AK |
8471 | |
8472 | cfun_frame_layout.gprs_offset | |
adf39f8f | 8473 | = cfun_frame_layout.f0_offset - cfun_gprs_save_area_size; |
74129172 AK |
8474 | |
8475 | cfun_frame_layout.f8_offset = (cfun_frame_layout.gprs_offset | |
8476 | - cfun_frame_layout.high_fprs * 8); | |
adf39f8f AK |
8477 | } |
8478 | ||
74129172 AK |
8479 | if (cfun_save_high_fprs_p) |
8480 | cfun_frame_layout.frame_size += cfun_frame_layout.high_fprs * 8; | |
8481 | ||
8482 | if (!crtl->is_leaf) | |
8483 | cfun_frame_layout.frame_size += crtl->outgoing_args_size; | |
8484 | ||
8485 | /* In the following cases we have to allocate a STACK_POINTER_OFFSET | |
8486 | sized area at the bottom of the stack. This is required also for | |
8487 | leaf functions. When GCC generates a local stack reference it | |
8488 | will always add STACK_POINTER_OFFSET to all these references. */ | |
416ff32e | 8489 | if (crtl->is_leaf |
adf39f8f AK |
8490 | && !TARGET_TPF_PROFILING |
8491 | && cfun_frame_layout.frame_size == 0 | |
6455a49e | 8492 | && !cfun->calls_alloca) |
adf39f8f AK |
8493 | return; |
8494 | ||
74129172 AK |
8495 | /* Calculate the number of bytes we have used in our own register |
8496 | save area. With the packed stack layout we can re-use the | |
8497 | remaining bytes for normal stack elements. */ | |
adf39f8f | 8498 | |
74129172 AK |
8499 | if (TARGET_PACKED_STACK) |
8500 | lowest_offset = MIN (MIN (cfun_frame_layout.f0_offset, | |
8501 | cfun_frame_layout.f4_offset), | |
8502 | cfun_frame_layout.gprs_offset); | |
8503 | else | |
8504 | lowest_offset = 0; | |
f4aa3848 | 8505 | |
74129172 AK |
8506 | if (TARGET_BACKCHAIN) |
8507 | lowest_offset = MIN (lowest_offset, cfun_frame_layout.backchain_offset); | |
f4aa3848 | 8508 | |
74129172 | 8509 | cfun_frame_layout.frame_size += STACK_POINTER_OFFSET - lowest_offset; |
adf39f8f | 8510 | |
74129172 AK |
8511 | /* If under 31 bit an odd number of gprs has to be saved we have to |
8512 | adjust the frame size to sustain 8 byte alignment of stack | |
8513 | frames. */ | |
8514 | cfun_frame_layout.frame_size = ((cfun_frame_layout.frame_size + | |
8515 | STACK_BOUNDARY / BITS_PER_UNIT - 1) | |
8516 | & ~(STACK_BOUNDARY / BITS_PER_UNIT - 1)); | |
4023fb28 UW |
8517 | } |
8518 | ||
91086990 UW |
8519 | /* Generate frame layout. Fills in register and frame data for the current |
8520 | function in cfun->machine. This routine can be called multiple times; | |
8521 | it will re-do the complete frame layout every time. */ | |
4023fb28 | 8522 | |
91086990 UW |
8523 | static void |
8524 | s390_init_frame_layout (void) | |
9db1d521 | 8525 | { |
91086990 UW |
8526 | HOST_WIDE_INT frame_size; |
8527 | int base_used; | |
6455a49e AK |
8528 | |
8529 | gcc_assert (!reload_completed); | |
b767fc11 | 8530 | |
91086990 UW |
8531 | /* On S/390 machines, we may need to perform branch splitting, which |
8532 | will require both base and return address register. We have no | |
8533 | choice but to assume we're going to need them until right at the | |
8534 | end of the machine dependent reorg phase. */ | |
8535 | if (!TARGET_CPU_ZARCH) | |
8536 | cfun->machine->split_branches_pending_p = true; | |
8537 | ||
8538 | do | |
8539 | { | |
8540 | frame_size = cfun_frame_layout.frame_size; | |
8541 | ||
8542 | /* Try to predict whether we'll need the base register. */ | |
8543 | base_used = cfun->machine->split_branches_pending_p | |
e3b5732b | 8544 | || crtl->uses_const_pool |
20f04e65 AK |
8545 | || (!DISP_IN_RANGE (frame_size) |
8546 | && !CONST_OK_FOR_K (frame_size)); | |
91086990 UW |
8547 | |
8548 | /* Decide which register to use as literal pool base. In small | |
8549 | leaf functions, try to use an unused call-clobbered register | |
8550 | as base register to avoid save/restore overhead. */ | |
8551 | if (!base_used) | |
8552 | cfun->machine->base_reg = NULL_RTX; | |
416ff32e | 8553 | else if (crtl->is_leaf && !df_regs_ever_live_p (5)) |
91086990 UW |
8554 | cfun->machine->base_reg = gen_rtx_REG (Pmode, 5); |
8555 | else | |
8556 | cfun->machine->base_reg = gen_rtx_REG (Pmode, BASE_REGNUM); | |
adf39f8f | 8557 | |
6455a49e | 8558 | s390_register_info (); |
91086990 UW |
8559 | s390_frame_info (); |
8560 | } | |
8561 | while (frame_size != cfun_frame_layout.frame_size); | |
9db1d521 HP |
8562 | } |
8563 | ||
5a3fe9b6 AK |
8564 | /* Remove the FPR clobbers from a tbegin insn if it can be proven that |
8565 | the TX is nonescaping. A transaction is considered escaping if | |
8566 | there is at least one path from tbegin returning CC0 to the | |
8567 | function exit block without an tend. | |
8568 | ||
8569 | The check so far has some limitations: | |
8570 | - only single tbegin/tend BBs are supported | |
8571 | - the first cond jump after tbegin must separate the CC0 path from ~CC0 | |
8572 | - when CC is copied to a GPR and the CC0 check is done with the GPR | |
8573 | this is not supported | |
8574 | */ | |
8575 | ||
8576 | static void | |
8577 | s390_optimize_nonescaping_tx (void) | |
8578 | { | |
8579 | const unsigned int CC0 = 1 << 3; | |
8580 | basic_block tbegin_bb = NULL; | |
8581 | basic_block tend_bb = NULL; | |
8582 | basic_block bb; | |
775c43d3 | 8583 | rtx_insn *insn; |
5a3fe9b6 AK |
8584 | bool result = true; |
8585 | int bb_index; | |
775c43d3 | 8586 | rtx_insn *tbegin_insn = NULL; |
5a3fe9b6 AK |
8587 | |
8588 | if (!cfun->machine->tbegin_p) | |
8589 | return; | |
8590 | ||
0cae8d31 | 8591 | for (bb_index = 0; bb_index < n_basic_blocks_for_fn (cfun); bb_index++) |
5a3fe9b6 | 8592 | { |
06e28de2 | 8593 | bb = BASIC_BLOCK_FOR_FN (cfun, bb_index); |
5a3fe9b6 | 8594 | |
2561451d AK |
8595 | if (!bb) |
8596 | continue; | |
8597 | ||
5a3fe9b6 AK |
8598 | FOR_BB_INSNS (bb, insn) |
8599 | { | |
8600 | rtx ite, cc, pat, target; | |
8601 | unsigned HOST_WIDE_INT mask; | |
8602 | ||
8603 | if (!INSN_P (insn) || INSN_CODE (insn) <= 0) | |
8604 | continue; | |
8605 | ||
8606 | pat = PATTERN (insn); | |
8607 | ||
8608 | if (GET_CODE (pat) == PARALLEL) | |
8609 | pat = XVECEXP (pat, 0, 0); | |
8610 | ||
8611 | if (GET_CODE (pat) != SET | |
8612 | || GET_CODE (SET_SRC (pat)) != UNSPEC_VOLATILE) | |
8613 | continue; | |
8614 | ||
8615 | if (XINT (SET_SRC (pat), 1) == UNSPECV_TBEGIN) | |
8616 | { | |
b32d5189 | 8617 | rtx_insn *tmp; |
5a3fe9b6 AK |
8618 | |
8619 | tbegin_insn = insn; | |
8620 | ||
8621 | /* Just return if the tbegin doesn't have clobbers. */ | |
8622 | if (GET_CODE (PATTERN (insn)) != PARALLEL) | |
8623 | return; | |
8624 | ||
8625 | if (tbegin_bb != NULL) | |
8626 | return; | |
8627 | ||
8628 | /* Find the next conditional jump. */ | |
8629 | for (tmp = NEXT_INSN (insn); | |
8630 | tmp != NULL_RTX; | |
8631 | tmp = NEXT_INSN (tmp)) | |
8632 | { | |
8633 | if (reg_set_p (gen_rtx_REG (CCmode, CC_REGNUM), tmp)) | |
8634 | return; | |
8635 | if (!JUMP_P (tmp)) | |
8636 | continue; | |
8637 | ||
8638 | ite = SET_SRC (PATTERN (tmp)); | |
8639 | if (GET_CODE (ite) != IF_THEN_ELSE) | |
8640 | continue; | |
8641 | ||
8642 | cc = XEXP (XEXP (ite, 0), 0); | |
8643 | if (!REG_P (cc) || !CC_REGNO_P (REGNO (cc)) | |
8644 | || GET_MODE (cc) != CCRAWmode | |
8645 | || GET_CODE (XEXP (XEXP (ite, 0), 1)) != CONST_INT) | |
8646 | return; | |
8647 | ||
8648 | if (bb->succs->length () != 2) | |
8649 | return; | |
8650 | ||
8651 | mask = INTVAL (XEXP (XEXP (ite, 0), 1)); | |
8652 | if (GET_CODE (XEXP (ite, 0)) == NE) | |
8653 | mask ^= 0xf; | |
8654 | ||
8655 | if (mask == CC0) | |
8656 | target = XEXP (ite, 1); | |
8657 | else if (mask == (CC0 ^ 0xf)) | |
8658 | target = XEXP (ite, 2); | |
8659 | else | |
8660 | return; | |
8661 | ||
8662 | { | |
8663 | edge_iterator ei; | |
8664 | edge e1, e2; | |
8665 | ||
8666 | ei = ei_start (bb->succs); | |
8667 | e1 = ei_safe_edge (ei); | |
8668 | ei_next (&ei); | |
8669 | e2 = ei_safe_edge (ei); | |
8670 | ||
8671 | if (e2->flags & EDGE_FALLTHRU) | |
8672 | { | |
8673 | e2 = e1; | |
8674 | e1 = ei_safe_edge (ei); | |
8675 | } | |
8676 | ||
8677 | if (!(e1->flags & EDGE_FALLTHRU)) | |
8678 | return; | |
8679 | ||
8680 | tbegin_bb = (target == pc_rtx) ? e1->dest : e2->dest; | |
8681 | } | |
8682 | if (tmp == BB_END (bb)) | |
8683 | break; | |
8684 | } | |
8685 | } | |
8686 | ||
8687 | if (XINT (SET_SRC (pat), 1) == UNSPECV_TEND) | |
8688 | { | |
8689 | if (tend_bb != NULL) | |
8690 | return; | |
8691 | tend_bb = bb; | |
8692 | } | |
8693 | } | |
8694 | } | |
8695 | ||
8696 | /* Either we successfully remove the FPR clobbers here or we are not | |
8697 | able to do anything for this TX. Both cases don't qualify for | |
8698 | another look. */ | |
8699 | cfun->machine->tbegin_p = false; | |
8700 | ||
8701 | if (tbegin_bb == NULL || tend_bb == NULL) | |
8702 | return; | |
8703 | ||
8704 | calculate_dominance_info (CDI_POST_DOMINATORS); | |
8705 | result = dominated_by_p (CDI_POST_DOMINATORS, tbegin_bb, tend_bb); | |
8706 | free_dominance_info (CDI_POST_DOMINATORS); | |
8707 | ||
8708 | if (!result) | |
8709 | return; | |
8710 | ||
2561451d AK |
8711 | PATTERN (tbegin_insn) = gen_rtx_PARALLEL (VOIDmode, |
8712 | gen_rtvec (2, | |
8713 | XVECEXP (PATTERN (tbegin_insn), 0, 0), | |
8714 | XVECEXP (PATTERN (tbegin_insn), 0, 1))); | |
5a3fe9b6 AK |
8715 | INSN_CODE (tbegin_insn) = -1; |
8716 | df_insn_rescan (tbegin_insn); | |
8717 | ||
8718 | return; | |
8719 | } | |
8720 | ||
74aa8b4b AK |
8721 | /* Return true if it is legal to put a value with MODE into REGNO. */ |
8722 | ||
8723 | bool | |
ef4bddc2 | 8724 | s390_hard_regno_mode_ok (unsigned int regno, machine_mode mode) |
74aa8b4b | 8725 | { |
085261c8 AK |
8726 | if (!TARGET_VX && VECTOR_NOFP_REGNO_P (regno)) |
8727 | return false; | |
8728 | ||
74aa8b4b AK |
8729 | switch (REGNO_REG_CLASS (regno)) |
8730 | { | |
085261c8 AK |
8731 | case VEC_REGS: |
8732 | return ((GET_MODE_CLASS (mode) == MODE_INT | |
8733 | && s390_class_max_nregs (VEC_REGS, mode) == 1) | |
8734 | || mode == DFmode | |
8735 | || s390_vector_mode_supported_p (mode)); | |
8736 | break; | |
74aa8b4b | 8737 | case FP_REGS: |
085261c8 AK |
8738 | if (TARGET_VX |
8739 | && ((GET_MODE_CLASS (mode) == MODE_INT | |
8740 | && s390_class_max_nregs (FP_REGS, mode) == 1) | |
8741 | || mode == DFmode | |
8742 | || s390_vector_mode_supported_p (mode))) | |
8743 | return true; | |
8744 | ||
74aa8b4b AK |
8745 | if (REGNO_PAIR_OK (regno, mode)) |
8746 | { | |
8747 | if (mode == SImode || mode == DImode) | |
8748 | return true; | |
8749 | ||
8750 | if (FLOAT_MODE_P (mode) && GET_MODE_CLASS (mode) != MODE_VECTOR_FLOAT) | |
8751 | return true; | |
8752 | } | |
8753 | break; | |
8754 | case ADDR_REGS: | |
8755 | if (FRAME_REGNO_P (regno) && mode == Pmode) | |
8756 | return true; | |
8757 | ||
8758 | /* fallthrough */ | |
8759 | case GENERAL_REGS: | |
8760 | if (REGNO_PAIR_OK (regno, mode)) | |
8761 | { | |
9602b6a1 | 8762 | if (TARGET_ZARCH |
4dc19cc0 | 8763 | || (mode != TFmode && mode != TCmode && mode != TDmode)) |
74aa8b4b | 8764 | return true; |
f4aa3848 | 8765 | } |
74aa8b4b AK |
8766 | break; |
8767 | case CC_REGS: | |
8768 | if (GET_MODE_CLASS (mode) == MODE_CC) | |
8769 | return true; | |
8770 | break; | |
8771 | case ACCESS_REGS: | |
8772 | if (REGNO_PAIR_OK (regno, mode)) | |
8773 | { | |
8774 | if (mode == SImode || mode == Pmode) | |
8775 | return true; | |
8776 | } | |
8777 | break; | |
8778 | default: | |
8779 | return false; | |
8780 | } | |
f4aa3848 | 8781 | |
74aa8b4b AK |
8782 | return false; |
8783 | } | |
8784 | ||
7633f08e UW |
8785 | /* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */ |
8786 | ||
8787 | bool | |
8788 | s390_hard_regno_rename_ok (unsigned int old_reg, unsigned int new_reg) | |
8789 | { | |
8790 | /* Once we've decided upon a register to use as base register, it must | |
8791 | no longer be used for any other purpose. */ | |
8792 | if (cfun->machine->base_reg) | |
8793 | if (REGNO (cfun->machine->base_reg) == old_reg | |
8794 | || REGNO (cfun->machine->base_reg) == new_reg) | |
8795 | return false; | |
8796 | ||
6455a49e AK |
8797 | /* Prevent regrename from using call-saved regs which haven't |
8798 | actually been saved. This is necessary since regrename assumes | |
8799 | the backend save/restore decisions are based on | |
8800 | df_regs_ever_live. Since we have our own routine we have to tell | |
8801 | regrename manually about it. */ | |
8802 | if (GENERAL_REGNO_P (new_reg) | |
8803 | && !call_really_used_regs[new_reg] | |
8804 | && cfun_gpr_save_slot (new_reg) == 0) | |
8805 | return false; | |
8806 | ||
8807 | return true; | |
8808 | } | |
8809 | ||
8810 | /* Return nonzero if register REGNO can be used as a scratch register | |
8811 | in peephole2. */ | |
8812 | ||
8813 | static bool | |
8814 | s390_hard_regno_scratch_ok (unsigned int regno) | |
8815 | { | |
8816 | /* See s390_hard_regno_rename_ok. */ | |
8817 | if (GENERAL_REGNO_P (regno) | |
8818 | && !call_really_used_regs[regno] | |
8819 | && cfun_gpr_save_slot (regno) == 0) | |
8820 | return false; | |
8821 | ||
7633f08e UW |
8822 | return true; |
8823 | } | |
8824 | ||
74aa8b4b | 8825 | /* Maximum number of registers to represent a value of mode MODE |
0a2aaacc | 8826 | in a register of class RCLASS. */ |
74aa8b4b | 8827 | |
c4100a35 | 8828 | int |
ef4bddc2 | 8829 | s390_class_max_nregs (enum reg_class rclass, machine_mode mode) |
74aa8b4b | 8830 | { |
085261c8 AK |
8831 | int reg_size; |
8832 | bool reg_pair_required_p = false; | |
8833 | ||
0a2aaacc | 8834 | switch (rclass) |
74aa8b4b AK |
8835 | { |
8836 | case FP_REGS: | |
085261c8 AK |
8837 | case VEC_REGS: |
8838 | reg_size = TARGET_VX ? 16 : 8; | |
8839 | ||
8840 | /* TF and TD modes would fit into a VR but we put them into a | |
8841 | register pair since we do not have 128bit FP instructions on | |
8842 | full VRs. */ | |
8843 | if (TARGET_VX | |
8844 | && SCALAR_FLOAT_MODE_P (mode) | |
8845 | && GET_MODE_SIZE (mode) >= 16) | |
8846 | reg_pair_required_p = true; | |
8847 | ||
8848 | /* Even if complex types would fit into a single FPR/VR we force | |
8849 | them into a register pair to deal with the parts more easily. | |
8850 | (FIXME: What about complex ints?) */ | |
74aa8b4b | 8851 | if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT) |
085261c8 AK |
8852 | reg_pair_required_p = true; |
8853 | break; | |
74aa8b4b | 8854 | case ACCESS_REGS: |
085261c8 AK |
8855 | reg_size = 4; |
8856 | break; | |
74aa8b4b | 8857 | default: |
085261c8 | 8858 | reg_size = UNITS_PER_WORD; |
74aa8b4b AK |
8859 | break; |
8860 | } | |
085261c8 AK |
8861 | |
8862 | if (reg_pair_required_p) | |
8863 | return 2 * ((GET_MODE_SIZE (mode) / 2 + reg_size - 1) / reg_size); | |
8864 | ||
8865 | return (GET_MODE_SIZE (mode) + reg_size - 1) / reg_size; | |
8866 | } | |
8867 | ||
8868 | /* Return TRUE if changing mode from FROM to TO should not be allowed | |
8869 | for register class CLASS. */ | |
8870 | ||
8871 | int | |
8872 | s390_cannot_change_mode_class (machine_mode from_mode, | |
8873 | machine_mode to_mode, | |
8874 | enum reg_class rclass) | |
8875 | { | |
8876 | machine_mode small_mode; | |
8877 | machine_mode big_mode; | |
8878 | ||
8879 | if (GET_MODE_SIZE (from_mode) == GET_MODE_SIZE (to_mode)) | |
8880 | return 0; | |
8881 | ||
8882 | if (GET_MODE_SIZE (from_mode) < GET_MODE_SIZE (to_mode)) | |
8883 | { | |
8884 | small_mode = from_mode; | |
8885 | big_mode = to_mode; | |
8886 | } | |
8887 | else | |
8888 | { | |
8889 | small_mode = to_mode; | |
8890 | big_mode = from_mode; | |
8891 | } | |
8892 | ||
8893 | /* Values residing in VRs are little-endian style. All modes are | |
8894 | placed left-aligned in an VR. This means that we cannot allow | |
8895 | switching between modes with differing sizes. Also if the vector | |
8896 | facility is available we still place TFmode values in VR register | |
8897 | pairs, since the only instructions we have operating on TFmodes | |
8898 | only deal with register pairs. Therefore we have to allow DFmode | |
8899 | subregs of TFmodes to enable the TFmode splitters. */ | |
8900 | if (reg_classes_intersect_p (VEC_REGS, rclass) | |
8901 | && (GET_MODE_SIZE (small_mode) < 8 | |
8902 | || s390_class_max_nregs (VEC_REGS, big_mode) == 1)) | |
8903 | return 1; | |
8904 | ||
8905 | /* Likewise for access registers, since they have only half the | |
8906 | word size on 64-bit. */ | |
8907 | if (reg_classes_intersect_p (ACCESS_REGS, rclass)) | |
8908 | return 1; | |
8909 | ||
8910 | return 0; | |
74aa8b4b AK |
8911 | } |
8912 | ||
3597e113 VM |
8913 | /* Return true if we use LRA instead of reload pass. */ |
8914 | static bool | |
8915 | s390_lra_p (void) | |
8916 | { | |
8917 | return s390_lra_flag; | |
8918 | } | |
8919 | ||
91086990 UW |
8920 | /* Return true if register FROM can be eliminated via register TO. */ |
8921 | ||
7b5cbb57 AS |
8922 | static bool |
8923 | s390_can_eliminate (const int from, const int to) | |
91086990 | 8924 | { |
7633f08e UW |
8925 | /* On zSeries machines, we have not marked the base register as fixed. |
8926 | Instead, we have an elimination rule BASE_REGNUM -> BASE_REGNUM. | |
8927 | If a function requires the base register, we say here that this | |
8928 | elimination cannot be performed. This will cause reload to free | |
8929 | up the base register (as if it were fixed). On the other hand, | |
8930 | if the current function does *not* require the base register, we | |
8931 | say here the elimination succeeds, which in turn allows reload | |
8932 | to allocate the base register for any other purpose. */ | |
8933 | if (from == BASE_REGNUM && to == BASE_REGNUM) | |
8934 | { | |
8935 | if (TARGET_CPU_ZARCH) | |
8936 | { | |
8937 | s390_init_frame_layout (); | |
8938 | return cfun->machine->base_reg == NULL_RTX; | |
8939 | } | |
8940 | ||
8941 | return false; | |
8942 | } | |
8943 | ||
8944 | /* Everything else must point into the stack frame. */ | |
91086990 UW |
8945 | gcc_assert (to == STACK_POINTER_REGNUM |
8946 | || to == HARD_FRAME_POINTER_REGNUM); | |
8947 | ||
8948 | gcc_assert (from == FRAME_POINTER_REGNUM | |
8949 | || from == ARG_POINTER_REGNUM | |
8950 | || from == RETURN_ADDRESS_POINTER_REGNUM); | |
8951 | ||
8952 | /* Make sure we actually saved the return address. */ | |
8953 | if (from == RETURN_ADDRESS_POINTER_REGNUM) | |
e3b5732b JH |
8954 | if (!crtl->calls_eh_return |
8955 | && !cfun->stdarg | |
91086990 UW |
8956 | && !cfun_frame_layout.save_return_addr_p) |
8957 | return false; | |
8958 | ||
8959 | return true; | |
8960 | } | |
8961 | ||
8962 | /* Return offset between register FROM and TO initially after prolog. */ | |
a38e09bc AK |
8963 | |
8964 | HOST_WIDE_INT | |
91086990 | 8965 | s390_initial_elimination_offset (int from, int to) |
a38e09bc | 8966 | { |
91086990 | 8967 | HOST_WIDE_INT offset; |
a38e09bc | 8968 | |
91086990 UW |
8969 | /* ??? Why are we called for non-eliminable pairs? */ |
8970 | if (!s390_can_eliminate (from, to)) | |
8971 | return 0; | |
8972 | ||
8973 | switch (from) | |
8974 | { | |
8975 | case FRAME_POINTER_REGNUM: | |
f4aa3848 | 8976 | offset = (get_frame_size() |
63296cb1 | 8977 | + STACK_POINTER_OFFSET |
38173d38 | 8978 | + crtl->outgoing_args_size); |
91086990 | 8979 | break; |
adf39f8f | 8980 | |
91086990 UW |
8981 | case ARG_POINTER_REGNUM: |
8982 | s390_init_frame_layout (); | |
8983 | offset = cfun_frame_layout.frame_size + STACK_POINTER_OFFSET; | |
8984 | break; | |
8985 | ||
8986 | case RETURN_ADDRESS_POINTER_REGNUM: | |
8987 | s390_init_frame_layout (); | |
6455a49e AK |
8988 | |
8989 | if (cfun_frame_layout.first_save_gpr_slot == -1) | |
8990 | { | |
8991 | /* If it turns out that for stdarg nothing went into the reg | |
8992 | save area we also do not need the return address | |
8993 | pointer. */ | |
8994 | if (cfun->stdarg && !cfun_save_arg_fprs_p) | |
8995 | return 0; | |
8996 | ||
8997 | gcc_unreachable (); | |
8998 | } | |
8999 | ||
9000 | /* In order to make the following work it is not necessary for | |
9001 | r14 to have a save slot. It is sufficient if one other GPR | |
9002 | got one. Since the GPRs are always stored without gaps we | |
9003 | are able to calculate where the r14 save slot would | |
9004 | reside. */ | |
9005 | offset = (cfun_frame_layout.frame_size + cfun_frame_layout.gprs_offset + | |
9006 | (RETURN_REGNUM - cfun_frame_layout.first_save_gpr_slot) * | |
9007 | UNITS_PER_LONG); | |
91086990 UW |
9008 | break; |
9009 | ||
7633f08e UW |
9010 | case BASE_REGNUM: |
9011 | offset = 0; | |
9012 | break; | |
9013 | ||
91086990 UW |
9014 | default: |
9015 | gcc_unreachable (); | |
9016 | } | |
9017 | ||
9018 | return offset; | |
a38e09bc AK |
9019 | } |
9020 | ||
4023fb28 | 9021 | /* Emit insn to save fpr REGNUM at offset OFFSET relative |
c7453384 | 9022 | to register BASE. Return generated insn. */ |
994fe660 | 9023 | |
9db1d521 | 9024 | static rtx |
9c808aad | 9025 | save_fpr (rtx base, int offset, int regnum) |
9db1d521 | 9026 | { |
4023fb28 | 9027 | rtx addr; |
0a81f074 | 9028 | addr = gen_rtx_MEM (DFmode, plus_constant (Pmode, base, offset)); |
dcc9eb26 AK |
9029 | |
9030 | if (regnum >= 16 && regnum <= (16 + FP_ARG_NUM_REG)) | |
9031 | set_mem_alias_set (addr, get_varargs_alias_set ()); | |
9032 | else | |
9033 | set_mem_alias_set (addr, get_frame_alias_set ()); | |
9db1d521 | 9034 | |
4023fb28 UW |
9035 | return emit_move_insn (addr, gen_rtx_REG (DFmode, regnum)); |
9036 | } | |
9db1d521 | 9037 | |
4023fb28 | 9038 | /* Emit insn to restore fpr REGNUM from offset OFFSET relative |
c7453384 | 9039 | to register BASE. Return generated insn. */ |
9db1d521 | 9040 | |
4023fb28 | 9041 | static rtx |
9c808aad | 9042 | restore_fpr (rtx base, int offset, int regnum) |
4023fb28 UW |
9043 | { |
9044 | rtx addr; | |
0a81f074 | 9045 | addr = gen_rtx_MEM (DFmode, plus_constant (Pmode, base, offset)); |
dcc9eb26 | 9046 | set_mem_alias_set (addr, get_frame_alias_set ()); |
9db1d521 | 9047 | |
4023fb28 | 9048 | return emit_move_insn (gen_rtx_REG (DFmode, regnum), addr); |
9db1d521 HP |
9049 | } |
9050 | ||
75707b28 JJ |
9051 | /* Return true if REGNO is a global register, but not one |
9052 | of the special ones that need to be saved/restored in anyway. */ | |
9053 | ||
9054 | static inline bool | |
9055 | global_not_special_regno_p (int regno) | |
9056 | { | |
9057 | return (global_regs[regno] | |
9058 | /* These registers are special and need to be | |
9059 | restored in any case. */ | |
9060 | && !(regno == STACK_POINTER_REGNUM | |
9061 | || regno == RETURN_REGNUM | |
9062 | || regno == BASE_REGNUM | |
9063 | || (flag_pic && regno == (int)PIC_OFFSET_TABLE_REGNUM))); | |
9064 | } | |
9065 | ||
c3cc6b78 | 9066 | /* Generate insn to save registers FIRST to LAST into |
c7453384 | 9067 | the register save area located at offset OFFSET |
c3cc6b78 | 9068 | relative to register BASE. */ |
9db1d521 | 9069 | |
c3cc6b78 | 9070 | static rtx |
9c808aad | 9071 | save_gprs (rtx base, int offset, int first, int last) |
9db1d521 | 9072 | { |
c3cc6b78 UW |
9073 | rtx addr, insn, note; |
9074 | int i; | |
9075 | ||
0a81f074 | 9076 | addr = plus_constant (Pmode, base, offset); |
c3cc6b78 | 9077 | addr = gen_rtx_MEM (Pmode, addr); |
dcc9eb26 AK |
9078 | |
9079 | set_mem_alias_set (addr, get_frame_alias_set ()); | |
c3cc6b78 UW |
9080 | |
9081 | /* Special-case single register. */ | |
9082 | if (first == last) | |
9083 | { | |
9084 | if (TARGET_64BIT) | |
9085 | insn = gen_movdi (addr, gen_rtx_REG (Pmode, first)); | |
9086 | else | |
9087 | insn = gen_movsi (addr, gen_rtx_REG (Pmode, first)); | |
9088 | ||
75707b28 JJ |
9089 | if (!global_not_special_regno_p (first)) |
9090 | RTX_FRAME_RELATED_P (insn) = 1; | |
c3cc6b78 UW |
9091 | return insn; |
9092 | } | |
9093 | ||
9094 | ||
9095 | insn = gen_store_multiple (addr, | |
9096 | gen_rtx_REG (Pmode, first), | |
9097 | GEN_INT (last - first + 1)); | |
9098 | ||
e3b5732b | 9099 | if (first <= 6 && cfun->stdarg) |
dcc9eb26 AK |
9100 | for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++) |
9101 | { | |
9102 | rtx mem = XEXP (XVECEXP (PATTERN (insn), 0, i), 0); | |
f4aa3848 | 9103 | |
dcc9eb26 AK |
9104 | if (first + i <= 6) |
9105 | set_mem_alias_set (mem, get_varargs_alias_set ()); | |
9106 | } | |
c3cc6b78 UW |
9107 | |
9108 | /* We need to set the FRAME_RELATED flag on all SETs | |
9109 | inside the store-multiple pattern. | |
9110 | ||
9111 | However, we must not emit DWARF records for registers 2..5 | |
c7453384 | 9112 | if they are stored for use by variable arguments ... |
c3cc6b78 | 9113 | |
a4d05547 | 9114 | ??? Unfortunately, it is not enough to simply not the |
c3cc6b78 UW |
9115 | FRAME_RELATED flags for those SETs, because the first SET |
9116 | of the PARALLEL is always treated as if it had the flag | |
9117 | set, even if it does not. Therefore we emit a new pattern | |
9118 | without those registers as REG_FRAME_RELATED_EXPR note. */ | |
9119 | ||
75707b28 | 9120 | if (first >= 6 && !global_not_special_regno_p (first)) |
c3cc6b78 UW |
9121 | { |
9122 | rtx pat = PATTERN (insn); | |
9123 | ||
9124 | for (i = 0; i < XVECLEN (pat, 0); i++) | |
75707b28 JJ |
9125 | if (GET_CODE (XVECEXP (pat, 0, i)) == SET |
9126 | && !global_not_special_regno_p (REGNO (SET_SRC (XVECEXP (pat, | |
9127 | 0, i))))) | |
c3cc6b78 UW |
9128 | RTX_FRAME_RELATED_P (XVECEXP (pat, 0, i)) = 1; |
9129 | ||
9130 | RTX_FRAME_RELATED_P (insn) = 1; | |
9131 | } | |
9132 | else if (last >= 6) | |
9133 | { | |
75707b28 JJ |
9134 | int start; |
9135 | ||
9136 | for (start = first >= 6 ? first : 6; start <= last; start++) | |
9137 | if (!global_not_special_regno_p (start)) | |
9138 | break; | |
9139 | ||
9140 | if (start > last) | |
9141 | return insn; | |
9142 | ||
0a81f074 RS |
9143 | addr = plus_constant (Pmode, base, |
9144 | offset + (start - first) * UNITS_PER_LONG); | |
6455a49e AK |
9145 | |
9146 | if (start == last) | |
9147 | { | |
9148 | if (TARGET_64BIT) | |
9149 | note = gen_movdi (gen_rtx_MEM (Pmode, addr), | |
9150 | gen_rtx_REG (Pmode, start)); | |
9151 | else | |
9152 | note = gen_movsi (gen_rtx_MEM (Pmode, addr), | |
9153 | gen_rtx_REG (Pmode, start)); | |
9154 | note = PATTERN (note); | |
9155 | ||
9156 | add_reg_note (insn, REG_FRAME_RELATED_EXPR, note); | |
9157 | RTX_FRAME_RELATED_P (insn) = 1; | |
9158 | ||
9159 | return insn; | |
9160 | } | |
9161 | ||
c7453384 | 9162 | note = gen_store_multiple (gen_rtx_MEM (Pmode, addr), |
75707b28 JJ |
9163 | gen_rtx_REG (Pmode, start), |
9164 | GEN_INT (last - start + 1)); | |
c3cc6b78 UW |
9165 | note = PATTERN (note); |
9166 | ||
bbbbb16a | 9167 | add_reg_note (insn, REG_FRAME_RELATED_EXPR, note); |
c3cc6b78 UW |
9168 | |
9169 | for (i = 0; i < XVECLEN (note, 0); i++) | |
75707b28 JJ |
9170 | if (GET_CODE (XVECEXP (note, 0, i)) == SET |
9171 | && !global_not_special_regno_p (REGNO (SET_SRC (XVECEXP (note, | |
9172 | 0, i))))) | |
c3cc6b78 UW |
9173 | RTX_FRAME_RELATED_P (XVECEXP (note, 0, i)) = 1; |
9174 | ||
9175 | RTX_FRAME_RELATED_P (insn) = 1; | |
9176 | } | |
9177 | ||
9178 | return insn; | |
4023fb28 | 9179 | } |
9db1d521 | 9180 | |
c3cc6b78 | 9181 | /* Generate insn to restore registers FIRST to LAST from |
c7453384 | 9182 | the register save area located at offset OFFSET |
c3cc6b78 | 9183 | relative to register BASE. */ |
9db1d521 | 9184 | |
c3cc6b78 | 9185 | static rtx |
9c808aad | 9186 | restore_gprs (rtx base, int offset, int first, int last) |
4023fb28 | 9187 | { |
c3cc6b78 UW |
9188 | rtx addr, insn; |
9189 | ||
0a81f074 | 9190 | addr = plus_constant (Pmode, base, offset); |
c3cc6b78 | 9191 | addr = gen_rtx_MEM (Pmode, addr); |
dcc9eb26 | 9192 | set_mem_alias_set (addr, get_frame_alias_set ()); |
c3cc6b78 UW |
9193 | |
9194 | /* Special-case single register. */ | |
9195 | if (first == last) | |
9196 | { | |
9197 | if (TARGET_64BIT) | |
9198 | insn = gen_movdi (gen_rtx_REG (Pmode, first), addr); | |
9199 | else | |
9200 | insn = gen_movsi (gen_rtx_REG (Pmode, first), addr); | |
9201 | ||
6455a49e | 9202 | RTX_FRAME_RELATED_P (insn) = 1; |
c3cc6b78 UW |
9203 | return insn; |
9204 | } | |
9205 | ||
9206 | insn = gen_load_multiple (gen_rtx_REG (Pmode, first), | |
9207 | addr, | |
9208 | GEN_INT (last - first + 1)); | |
6455a49e | 9209 | RTX_FRAME_RELATED_P (insn) = 1; |
c3cc6b78 | 9210 | return insn; |
4023fb28 | 9211 | } |
9db1d521 | 9212 | |
585539a1 | 9213 | /* Return insn sequence to load the GOT register. */ |
fd7643fb UW |
9214 | |
9215 | static GTY(()) rtx got_symbol; | |
775c43d3 | 9216 | rtx_insn * |
585539a1 | 9217 | s390_load_got (void) |
fd7643fb | 9218 | { |
775c43d3 | 9219 | rtx_insn *insns; |
585539a1 | 9220 | |
68c0ef75 AK |
9221 | /* We cannot use pic_offset_table_rtx here since we use this |
9222 | function also for non-pic if __tls_get_offset is called and in | |
9223 | that case PIC_OFFSET_TABLE_REGNUM as well as pic_offset_table_rtx | |
9224 | aren't usable. */ | |
9225 | rtx got_rtx = gen_rtx_REG (Pmode, 12); | |
9226 | ||
fd7643fb UW |
9227 | if (!got_symbol) |
9228 | { | |
9229 | got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_"); | |
9230 | SYMBOL_REF_FLAGS (got_symbol) = SYMBOL_FLAG_LOCAL; | |
9231 | } | |
9232 | ||
585539a1 UW |
9233 | start_sequence (); |
9234 | ||
9e8327e3 | 9235 | if (TARGET_CPU_ZARCH) |
fd7643fb | 9236 | { |
68c0ef75 | 9237 | emit_move_insn (got_rtx, got_symbol); |
fd7643fb UW |
9238 | } |
9239 | else | |
9240 | { | |
585539a1 | 9241 | rtx offset; |
fd7643fb | 9242 | |
c7453384 | 9243 | offset = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, got_symbol), |
fd7643fb UW |
9244 | UNSPEC_LTREL_OFFSET); |
9245 | offset = gen_rtx_CONST (Pmode, offset); | |
9246 | offset = force_const_mem (Pmode, offset); | |
9247 | ||
68c0ef75 | 9248 | emit_move_insn (got_rtx, offset); |
fd7643fb | 9249 | |
c7453384 | 9250 | offset = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, XEXP (offset, 0)), |
fd7643fb | 9251 | UNSPEC_LTREL_BASE); |
68c0ef75 | 9252 | offset = gen_rtx_PLUS (Pmode, got_rtx, offset); |
fd7643fb | 9253 | |
68c0ef75 | 9254 | emit_move_insn (got_rtx, offset); |
fd7643fb | 9255 | } |
585539a1 UW |
9256 | |
9257 | insns = get_insns (); | |
9258 | end_sequence (); | |
9259 | return insns; | |
fd7643fb UW |
9260 | } |
9261 | ||
12959abe AK |
9262 | /* This ties together stack memory (MEM with an alias set of frame_alias_set) |
9263 | and the change to the stack pointer. */ | |
9264 | ||
9265 | static void | |
9266 | s390_emit_stack_tie (void) | |
9267 | { | |
9268 | rtx mem = gen_frame_mem (BLKmode, | |
9269 | gen_rtx_REG (Pmode, STACK_POINTER_REGNUM)); | |
9270 | ||
9271 | emit_insn (gen_stack_tie (mem)); | |
9272 | } | |
9273 | ||
6455a49e AK |
9274 | /* Copy GPRS into FPR save slots. */ |
9275 | ||
9276 | static void | |
9277 | s390_save_gprs_to_fprs (void) | |
9278 | { | |
9279 | int i; | |
9280 | ||
9281 | if (!TARGET_Z10 || !TARGET_HARD_FLOAT || !crtl->is_leaf) | |
9282 | return; | |
9283 | ||
9284 | for (i = 6; i < 16; i++) | |
9285 | { | |
9286 | if (FP_REGNO_P (cfun_gpr_save_slot (i))) | |
9287 | { | |
775c43d3 | 9288 | rtx_insn *insn = |
6455a49e AK |
9289 | emit_move_insn (gen_rtx_REG (DImode, cfun_gpr_save_slot (i)), |
9290 | gen_rtx_REG (DImode, i)); | |
9291 | RTX_FRAME_RELATED_P (insn) = 1; | |
9292 | } | |
9293 | } | |
9294 | } | |
9295 | ||
9296 | /* Restore GPRs from FPR save slots. */ | |
9297 | ||
9298 | static void | |
9299 | s390_restore_gprs_from_fprs (void) | |
9300 | { | |
9301 | int i; | |
9302 | ||
9303 | if (!TARGET_Z10 || !TARGET_HARD_FLOAT || !crtl->is_leaf) | |
9304 | return; | |
9305 | ||
9306 | for (i = 6; i < 16; i++) | |
9307 | { | |
9308 | if (FP_REGNO_P (cfun_gpr_save_slot (i))) | |
9309 | { | |
775c43d3 | 9310 | rtx_insn *insn = |
6455a49e AK |
9311 | emit_move_insn (gen_rtx_REG (DImode, i), |
9312 | gen_rtx_REG (DImode, cfun_gpr_save_slot (i))); | |
9313 | df_set_regs_ever_live (i, true); | |
0621cf3c RS |
9314 | add_reg_note (insn, REG_CFA_RESTORE, gen_rtx_REG (DImode, i)); |
9315 | if (i == STACK_POINTER_REGNUM) | |
9316 | add_reg_note (insn, REG_CFA_DEF_CFA, | |
9317 | plus_constant (Pmode, stack_pointer_rtx, | |
9318 | STACK_POINTER_OFFSET)); | |
6455a49e AK |
9319 | RTX_FRAME_RELATED_P (insn) = 1; |
9320 | } | |
9321 | } | |
9322 | } | |
9323 | ||
9db1d521 | 9324 | |
4099494d RS |
9325 | /* A pass run immediately before shrink-wrapping and prologue and epilogue |
9326 | generation. */ | |
9327 | ||
4099494d RS |
9328 | namespace { |
9329 | ||
9330 | const pass_data pass_data_s390_early_mach = | |
9331 | { | |
9332 | RTL_PASS, /* type */ | |
9333 | "early_mach", /* name */ | |
9334 | OPTGROUP_NONE, /* optinfo_flags */ | |
4099494d RS |
9335 | TV_MACH_DEP, /* tv_id */ |
9336 | 0, /* properties_required */ | |
9337 | 0, /* properties_provided */ | |
9338 | 0, /* properties_destroyed */ | |
9339 | 0, /* todo_flags_start */ | |
3bea341f | 9340 | ( TODO_df_verify | TODO_df_finish ), /* todo_flags_finish */ |
4099494d | 9341 | }; |
585539a1 | 9342 | |
4099494d RS |
9343 | class pass_s390_early_mach : public rtl_opt_pass |
9344 | { | |
9345 | public: | |
9346 | pass_s390_early_mach (gcc::context *ctxt) | |
9347 | : rtl_opt_pass (pass_data_s390_early_mach, ctxt) | |
9348 | {} | |
9349 | ||
9350 | /* opt_pass methods: */ | |
be55bfe6 | 9351 | virtual unsigned int execute (function *); |
4099494d RS |
9352 | |
9353 | }; // class pass_s390_early_mach | |
9354 | ||
be55bfe6 TS |
9355 | unsigned int |
9356 | pass_s390_early_mach::execute (function *fun) | |
9357 | { | |
775c43d3 | 9358 | rtx_insn *insn; |
be55bfe6 TS |
9359 | |
9360 | /* Try to get rid of the FPR clobbers. */ | |
9361 | s390_optimize_nonescaping_tx (); | |
9362 | ||
9363 | /* Re-compute register info. */ | |
9364 | s390_register_info (); | |
9365 | ||
9366 | /* If we're using a base register, ensure that it is always valid for | |
9367 | the first non-prologue instruction. */ | |
9368 | if (fun->machine->base_reg) | |
9369 | emit_insn_at_entry (gen_main_pool (fun->machine->base_reg)); | |
9370 | ||
9371 | /* Annotate all constant pool references to let the scheduler know | |
9372 | they implicitly use the base register. */ | |
9373 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) | |
9374 | if (INSN_P (insn)) | |
9375 | { | |
9376 | annotate_constant_pool_refs (&PATTERN (insn)); | |
9377 | df_insn_rescan (insn); | |
9378 | } | |
9379 | return 0; | |
9380 | } | |
9381 | ||
4099494d RS |
9382 | } // anon namespace |
9383 | ||
9384 | /* Expand the prologue into a bunch of separate insns. */ | |
9385 | ||
9386 | void | |
9387 | s390_emit_prologue (void) | |
9388 | { | |
9389 | rtx insn, addr; | |
9390 | rtx temp_reg; | |
9391 | int i; | |
9392 | int offset; | |
9393 | int next_fpr = 0; | |
585539a1 | 9394 | |
c7453384 EC |
9395 | /* Choose best register to use for temp use within prologue. |
9396 | See below for why TPF must use the register 1. */ | |
9397 | ||
f4aa3848 | 9398 | if (!has_hard_reg_initial_val (Pmode, RETURN_REGNUM) |
416ff32e | 9399 | && !crtl->is_leaf |
7bcebb25 | 9400 | && !TARGET_TPF_PROFILING) |
4023fb28 | 9401 | temp_reg = gen_rtx_REG (Pmode, RETURN_REGNUM); |
9db1d521 | 9402 | else |
4023fb28 | 9403 | temp_reg = gen_rtx_REG (Pmode, 1); |
9db1d521 | 9404 | |
6455a49e AK |
9405 | s390_save_gprs_to_fprs (); |
9406 | ||
4023fb28 | 9407 | /* Save call saved gprs. */ |
adf39f8f | 9408 | if (cfun_frame_layout.first_save_gpr != -1) |
2790879f | 9409 | { |
f4aa3848 AK |
9410 | insn = save_gprs (stack_pointer_rtx, |
9411 | cfun_frame_layout.gprs_offset + | |
9602b6a1 | 9412 | UNITS_PER_LONG * (cfun_frame_layout.first_save_gpr |
fb3712f6 | 9413 | - cfun_frame_layout.first_save_gpr_slot), |
f4aa3848 | 9414 | cfun_frame_layout.first_save_gpr, |
2790879f AK |
9415 | cfun_frame_layout.last_save_gpr); |
9416 | emit_insn (insn); | |
9417 | } | |
4023fb28 | 9418 | |
5af2f3d3 | 9419 | /* Dummy insn to mark literal pool slot. */ |
c7453384 | 9420 | |
91086990 UW |
9421 | if (cfun->machine->base_reg) |
9422 | emit_insn (gen_main_pool (cfun->machine->base_reg)); | |
c7453384 | 9423 | |
adf39f8f | 9424 | offset = cfun_frame_layout.f0_offset; |
4023fb28 | 9425 | |
adf39f8f | 9426 | /* Save f0 and f2. */ |
2cf4c39e | 9427 | for (i = FPR0_REGNUM; i <= FPR0_REGNUM + 1; i++) |
adf39f8f | 9428 | { |
b89b22fc | 9429 | if (cfun_fpr_save_p (i)) |
adf39f8f | 9430 | { |
b89b22fc | 9431 | save_fpr (stack_pointer_rtx, offset, i); |
adf39f8f AK |
9432 | offset += 8; |
9433 | } | |
e179df83 AK |
9434 | else if (!TARGET_PACKED_STACK || cfun->stdarg) |
9435 | offset += 8; | |
adf39f8f | 9436 | } |
9db1d521 | 9437 | |
adf39f8f AK |
9438 | /* Save f4 and f6. */ |
9439 | offset = cfun_frame_layout.f4_offset; | |
2cf4c39e | 9440 | for (i = FPR4_REGNUM; i <= FPR4_REGNUM + 1; i++) |
adf39f8f | 9441 | { |
b89b22fc | 9442 | if (cfun_fpr_save_p (i)) |
4023fb28 | 9443 | { |
b89b22fc | 9444 | insn = save_fpr (stack_pointer_rtx, offset, i); |
adf39f8f AK |
9445 | offset += 8; |
9446 | ||
e179df83 AK |
9447 | /* If f4 and f6 are call clobbered they are saved due to |
9448 | stdargs and therefore are not frame related. */ | |
b89b22fc | 9449 | if (!call_really_used_regs[i]) |
adf39f8f | 9450 | RTX_FRAME_RELATED_P (insn) = 1; |
4023fb28 | 9451 | } |
e179df83 | 9452 | else if (!TARGET_PACKED_STACK || call_really_used_regs[i]) |
adf39f8f AK |
9453 | offset += 8; |
9454 | } | |
9455 | ||
b3d31392 | 9456 | if (TARGET_PACKED_STACK |
adf39f8f AK |
9457 | && cfun_save_high_fprs_p |
9458 | && cfun_frame_layout.f8_offset + cfun_frame_layout.high_fprs * 8 > 0) | |
9459 | { | |
9460 | offset = (cfun_frame_layout.f8_offset | |
9461 | + (cfun_frame_layout.high_fprs - 1) * 8); | |
9462 | ||
2cf4c39e | 9463 | for (i = FPR15_REGNUM; i >= FPR8_REGNUM && offset >= 0; i--) |
b89b22fc | 9464 | if (cfun_fpr_save_p (i)) |
adf39f8f | 9465 | { |
b89b22fc | 9466 | insn = save_fpr (stack_pointer_rtx, offset, i); |
f4aa3848 | 9467 | |
adf39f8f AK |
9468 | RTX_FRAME_RELATED_P (insn) = 1; |
9469 | offset -= 8; | |
9470 | } | |
9471 | if (offset >= cfun_frame_layout.f8_offset) | |
b89b22fc | 9472 | next_fpr = i; |
adf39f8f | 9473 | } |
f4aa3848 | 9474 | |
b3d31392 | 9475 | if (!TARGET_PACKED_STACK) |
2cf4c39e | 9476 | next_fpr = cfun_save_high_fprs_p ? FPR15_REGNUM : 0; |
9db1d521 | 9477 | |
a11e0df4 | 9478 | if (flag_stack_usage_info) |
5c779305 AK |
9479 | current_function_static_stack_size = cfun_frame_layout.frame_size; |
9480 | ||
4023fb28 | 9481 | /* Decrement stack pointer. */ |
9db1d521 | 9482 | |
adf39f8f | 9483 | if (cfun_frame_layout.frame_size > 0) |
4023fb28 | 9484 | { |
adf39f8f | 9485 | rtx frame_off = GEN_INT (-cfun_frame_layout.frame_size); |
bbbbb16a | 9486 | rtx real_frame_off; |
9db1d521 | 9487 | |
d75f90f1 AK |
9488 | if (s390_stack_size) |
9489 | { | |
690e7b63 | 9490 | HOST_WIDE_INT stack_guard; |
d75f90f1 | 9491 | |
690e7b63 AK |
9492 | if (s390_stack_guard) |
9493 | stack_guard = s390_stack_guard; | |
d75f90f1 | 9494 | else |
690e7b63 AK |
9495 | { |
9496 | /* If no value for stack guard is provided the smallest power of 2 | |
9497 | larger than the current frame size is chosen. */ | |
9498 | stack_guard = 1; | |
9499 | while (stack_guard < cfun_frame_layout.frame_size) | |
9500 | stack_guard <<= 1; | |
9501 | } | |
d75f90f1 | 9502 | |
690e7b63 AK |
9503 | if (cfun_frame_layout.frame_size >= s390_stack_size) |
9504 | { | |
cabbe12a | 9505 | warning (0, "frame size of function %qs is %wd" |
690e7b63 | 9506 | " bytes exceeding user provided stack limit of " |
cabbe12a | 9507 | "%d bytes. " |
690e7b63 AK |
9508 | "An unconditional trap is added.", |
9509 | current_function_name(), cfun_frame_layout.frame_size, | |
9510 | s390_stack_size); | |
9511 | emit_insn (gen_trap ()); | |
9512 | } | |
9513 | else | |
9514 | { | |
a3e7e012 AK |
9515 | /* stack_guard has to be smaller than s390_stack_size. |
9516 | Otherwise we would emit an AND with zero which would | |
9517 | not match the test under mask pattern. */ | |
9518 | if (stack_guard >= s390_stack_size) | |
9519 | { | |
f137aa63 | 9520 | warning (0, "frame size of function %qs is %wd" |
a3e7e012 AK |
9521 | " bytes which is more than half the stack size. " |
9522 | "The dynamic check would not be reliable. " | |
9523 | "No check emitted for this function.", | |
9524 | current_function_name(), | |
9525 | cfun_frame_layout.frame_size); | |
9526 | } | |
690e7b63 | 9527 | else |
a3e7e012 AK |
9528 | { |
9529 | HOST_WIDE_INT stack_check_mask = ((s390_stack_size - 1) | |
9530 | & ~(stack_guard - 1)); | |
9531 | ||
9532 | rtx t = gen_rtx_AND (Pmode, stack_pointer_rtx, | |
9533 | GEN_INT (stack_check_mask)); | |
9534 | if (TARGET_64BIT) | |
9535 | emit_insn (gen_ctrapdi4 (gen_rtx_EQ (VOIDmode, | |
9536 | t, const0_rtx), | |
9537 | t, const0_rtx, const0_rtx)); | |
9538 | else | |
9539 | emit_insn (gen_ctrapsi4 (gen_rtx_EQ (VOIDmode, | |
9540 | t, const0_rtx), | |
9541 | t, const0_rtx, const0_rtx)); | |
9542 | } | |
690e7b63 | 9543 | } |
d75f90f1 AK |
9544 | } |
9545 | ||
f4aa3848 | 9546 | if (s390_warn_framesize > 0 |
d75f90f1 | 9547 | && cfun_frame_layout.frame_size >= s390_warn_framesize) |
f137aa63 | 9548 | warning (0, "frame size of %qs is %wd bytes", |
d75f90f1 AK |
9549 | current_function_name (), cfun_frame_layout.frame_size); |
9550 | ||
9551 | if (s390_warn_dynamicstack_p && cfun->calls_alloca) | |
d4ee4d25 | 9552 | warning (0, "%qs uses dynamic stack allocation", current_function_name ()); |
d75f90f1 | 9553 | |
4023fb28 | 9554 | /* Save incoming stack pointer into temp reg. */ |
66480e91 | 9555 | if (TARGET_BACKCHAIN || next_fpr) |
adf39f8f | 9556 | insn = emit_insn (gen_move_insn (temp_reg, stack_pointer_rtx)); |
c7453384 | 9557 | |
fae778eb | 9558 | /* Subtract frame size from stack pointer. */ |
4023fb28 | 9559 | |
d3632d41 UW |
9560 | if (DISP_IN_RANGE (INTVAL (frame_off))) |
9561 | { | |
f7df4a84 | 9562 | insn = gen_rtx_SET (stack_pointer_rtx, |
f4aa3848 | 9563 | gen_rtx_PLUS (Pmode, stack_pointer_rtx, |
9c808aad | 9564 | frame_off)); |
d3632d41 UW |
9565 | insn = emit_insn (insn); |
9566 | } | |
9567 | else | |
9568 | { | |
b5c67a49 | 9569 | if (!CONST_OK_FOR_K (INTVAL (frame_off))) |
d3632d41 UW |
9570 | frame_off = force_const_mem (Pmode, frame_off); |
9571 | ||
9572 | insn = emit_insn (gen_add2_insn (stack_pointer_rtx, frame_off)); | |
585539a1 | 9573 | annotate_constant_pool_refs (&PATTERN (insn)); |
d3632d41 | 9574 | } |
4023fb28 | 9575 | |
4023fb28 | 9576 | RTX_FRAME_RELATED_P (insn) = 1; |
bbbbb16a ILT |
9577 | real_frame_off = GEN_INT (-cfun_frame_layout.frame_size); |
9578 | add_reg_note (insn, REG_FRAME_RELATED_EXPR, | |
f7df4a84 | 9579 | gen_rtx_SET (stack_pointer_rtx, |
bbbbb16a ILT |
9580 | gen_rtx_PLUS (Pmode, stack_pointer_rtx, |
9581 | real_frame_off))); | |
4023fb28 UW |
9582 | |
9583 | /* Set backchain. */ | |
c7453384 | 9584 | |
66480e91 | 9585 | if (TARGET_BACKCHAIN) |
9db1d521 | 9586 | { |
adf39f8f | 9587 | if (cfun_frame_layout.backchain_offset) |
f4aa3848 | 9588 | addr = gen_rtx_MEM (Pmode, |
0a81f074 | 9589 | plus_constant (Pmode, stack_pointer_rtx, |
adf39f8f AK |
9590 | cfun_frame_layout.backchain_offset)); |
9591 | else | |
f4aa3848 | 9592 | addr = gen_rtx_MEM (Pmode, stack_pointer_rtx); |
dcc9eb26 | 9593 | set_mem_alias_set (addr, get_frame_alias_set ()); |
4023fb28 | 9594 | insn = emit_insn (gen_move_insn (addr, temp_reg)); |
9db1d521 | 9595 | } |
7d798969 | 9596 | |
8f4f502f | 9597 | /* If we support non-call exceptions (e.g. for Java), |
7d798969 UW |
9598 | we need to make sure the backchain pointer is set up |
9599 | before any possibly trapping memory access. */ | |
8f4f502f | 9600 | if (TARGET_BACKCHAIN && cfun->can_throw_non_call_exceptions) |
7d798969 UW |
9601 | { |
9602 | addr = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (VOIDmode)); | |
c41c1387 | 9603 | emit_clobber (addr); |
7d798969 | 9604 | } |
4023fb28 | 9605 | } |
9db1d521 | 9606 | |
4023fb28 | 9607 | /* Save fprs 8 - 15 (64 bit ABI). */ |
c7453384 | 9608 | |
adf39f8f | 9609 | if (cfun_save_high_fprs_p && next_fpr) |
4023fb28 | 9610 | { |
12959abe AK |
9611 | /* If the stack might be accessed through a different register |
9612 | we have to make sure that the stack pointer decrement is not | |
9613 | moved below the use of the stack slots. */ | |
9614 | s390_emit_stack_tie (); | |
9615 | ||
f4aa3848 | 9616 | insn = emit_insn (gen_add2_insn (temp_reg, |
adf39f8f AK |
9617 | GEN_INT (cfun_frame_layout.f8_offset))); |
9618 | ||
9619 | offset = 0; | |
9db1d521 | 9620 | |
2cf4c39e | 9621 | for (i = FPR8_REGNUM; i <= next_fpr; i++) |
b89b22fc | 9622 | if (cfun_fpr_save_p (i)) |
4023fb28 | 9623 | { |
0a81f074 | 9624 | rtx addr = plus_constant (Pmode, stack_pointer_rtx, |
adf39f8f AK |
9625 | cfun_frame_layout.frame_size |
9626 | + cfun_frame_layout.f8_offset | |
9627 | + offset); | |
f4aa3848 | 9628 | |
adf39f8f AK |
9629 | insn = save_fpr (temp_reg, offset, i); |
9630 | offset += 8; | |
4023fb28 | 9631 | RTX_FRAME_RELATED_P (insn) = 1; |
bbbbb16a | 9632 | add_reg_note (insn, REG_FRAME_RELATED_EXPR, |
f7df4a84 | 9633 | gen_rtx_SET (gen_rtx_MEM (DFmode, addr), |
bbbbb16a | 9634 | gen_rtx_REG (DFmode, i))); |
4023fb28 UW |
9635 | } |
9636 | } | |
c7453384 | 9637 | |
4023fb28 | 9638 | /* Set frame pointer, if needed. */ |
c7453384 | 9639 | |
29742ba4 | 9640 | if (frame_pointer_needed) |
4023fb28 UW |
9641 | { |
9642 | insn = emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx); | |
9643 | RTX_FRAME_RELATED_P (insn) = 1; | |
9644 | } | |
9db1d521 | 9645 | |
4023fb28 | 9646 | /* Set up got pointer, if needed. */ |
c7453384 | 9647 | |
6fb5fa3c | 9648 | if (flag_pic && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM)) |
585539a1 | 9649 | { |
775c43d3 | 9650 | rtx_insn *insns = s390_load_got (); |
585539a1 | 9651 | |
b32d5189 | 9652 | for (rtx_insn *insn = insns; insn; insn = NEXT_INSN (insn)) |
6fb5fa3c | 9653 | annotate_constant_pool_refs (&PATTERN (insn)); |
585539a1 UW |
9654 | |
9655 | emit_insn (insns); | |
9656 | } | |
c7453384 | 9657 | |
3839e36a | 9658 | if (TARGET_TPF_PROFILING) |
c7453384 EC |
9659 | { |
9660 | /* Generate a BAS instruction to serve as a function | |
9661 | entry intercept to facilitate the use of tracing | |
2f7e5a0d EC |
9662 | algorithms located at the branch target. */ |
9663 | emit_insn (gen_prologue_tpf ()); | |
c7453384 EC |
9664 | |
9665 | /* Emit a blockage here so that all code | |
9666 | lies between the profiling mechanisms. */ | |
9667 | emit_insn (gen_blockage ()); | |
9668 | } | |
4023fb28 | 9669 | } |
9db1d521 | 9670 | |
b1c9bc51 | 9671 | /* Expand the epilogue into a bunch of separate insns. */ |
9db1d521 | 9672 | |
4023fb28 | 9673 | void |
ed9676cf | 9674 | s390_emit_epilogue (bool sibcall) |
4023fb28 | 9675 | { |
75707b28 | 9676 | rtx frame_pointer, return_reg, cfa_restores = NULL_RTX; |
5d4d885c | 9677 | int area_bottom, area_top, offset = 0; |
adf39f8f | 9678 | int next_offset; |
4023fb28 | 9679 | rtvec p; |
7333171f | 9680 | int i; |
9db1d521 | 9681 | |
3839e36a | 9682 | if (TARGET_TPF_PROFILING) |
c7453384 EC |
9683 | { |
9684 | ||
9685 | /* Generate a BAS instruction to serve as a function | |
9686 | entry intercept to facilitate the use of tracing | |
2f7e5a0d | 9687 | algorithms located at the branch target. */ |
c7453384 | 9688 | |
c7453384 EC |
9689 | /* Emit a blockage here so that all code |
9690 | lies between the profiling mechanisms. */ | |
9691 | emit_insn (gen_blockage ()); | |
9692 | ||
2f7e5a0d | 9693 | emit_insn (gen_epilogue_tpf ()); |
c7453384 EC |
9694 | } |
9695 | ||
4023fb28 | 9696 | /* Check whether to use frame or stack pointer for restore. */ |
9db1d521 | 9697 | |
f4aa3848 | 9698 | frame_pointer = (frame_pointer_needed |
adf39f8f | 9699 | ? hard_frame_pointer_rtx : stack_pointer_rtx); |
9db1d521 | 9700 | |
adf39f8f | 9701 | s390_frame_area (&area_bottom, &area_top); |
9db1d521 | 9702 | |
c7453384 | 9703 | /* Check whether we can access the register save area. |
4023fb28 | 9704 | If not, increment the frame pointer as required. */ |
9db1d521 | 9705 | |
4023fb28 UW |
9706 | if (area_top <= area_bottom) |
9707 | { | |
9708 | /* Nothing to restore. */ | |
9709 | } | |
adf39f8f AK |
9710 | else if (DISP_IN_RANGE (cfun_frame_layout.frame_size + area_bottom) |
9711 | && DISP_IN_RANGE (cfun_frame_layout.frame_size + area_top - 1)) | |
4023fb28 UW |
9712 | { |
9713 | /* Area is in range. */ | |
adf39f8f | 9714 | offset = cfun_frame_layout.frame_size; |
4023fb28 UW |
9715 | } |
9716 | else | |
9717 | { | |
75707b28 | 9718 | rtx insn, frame_off, cfa; |
9db1d521 | 9719 | |
c7453384 | 9720 | offset = area_bottom < 0 ? -area_bottom : 0; |
adf39f8f | 9721 | frame_off = GEN_INT (cfun_frame_layout.frame_size - offset); |
9db1d521 | 9722 | |
f7df4a84 | 9723 | cfa = gen_rtx_SET (frame_pointer, |
75707b28 | 9724 | gen_rtx_PLUS (Pmode, frame_pointer, frame_off)); |
d3632d41 UW |
9725 | if (DISP_IN_RANGE (INTVAL (frame_off))) |
9726 | { | |
f7df4a84 | 9727 | insn = gen_rtx_SET (frame_pointer, |
d3632d41 UW |
9728 | gen_rtx_PLUS (Pmode, frame_pointer, frame_off)); |
9729 | insn = emit_insn (insn); | |
9730 | } | |
9731 | else | |
9732 | { | |
b5c67a49 | 9733 | if (!CONST_OK_FOR_K (INTVAL (frame_off))) |
d3632d41 | 9734 | frame_off = force_const_mem (Pmode, frame_off); |
9db1d521 | 9735 | |
d3632d41 | 9736 | insn = emit_insn (gen_add2_insn (frame_pointer, frame_off)); |
585539a1 | 9737 | annotate_constant_pool_refs (&PATTERN (insn)); |
d3632d41 | 9738 | } |
75707b28 JJ |
9739 | add_reg_note (insn, REG_CFA_ADJUST_CFA, cfa); |
9740 | RTX_FRAME_RELATED_P (insn) = 1; | |
4023fb28 | 9741 | } |
9db1d521 | 9742 | |
4023fb28 UW |
9743 | /* Restore call saved fprs. */ |
9744 | ||
9745 | if (TARGET_64BIT) | |
9db1d521 | 9746 | { |
adf39f8f AK |
9747 | if (cfun_save_high_fprs_p) |
9748 | { | |
9749 | next_offset = cfun_frame_layout.f8_offset; | |
2cf4c39e | 9750 | for (i = FPR8_REGNUM; i <= FPR15_REGNUM; i++) |
adf39f8f | 9751 | { |
b89b22fc | 9752 | if (cfun_fpr_save_p (i)) |
adf39f8f AK |
9753 | { |
9754 | restore_fpr (frame_pointer, | |
9755 | offset + next_offset, i); | |
75707b28 JJ |
9756 | cfa_restores |
9757 | = alloc_reg_note (REG_CFA_RESTORE, | |
9758 | gen_rtx_REG (DFmode, i), cfa_restores); | |
adf39f8f AK |
9759 | next_offset += 8; |
9760 | } | |
9761 | } | |
9762 | } | |
f4aa3848 | 9763 | |
9db1d521 HP |
9764 | } |
9765 | else | |
9766 | { | |
adf39f8f | 9767 | next_offset = cfun_frame_layout.f4_offset; |
b89b22fc | 9768 | /* f4, f6 */ |
2cf4c39e | 9769 | for (i = FPR4_REGNUM; i <= FPR4_REGNUM + 1; i++) |
adf39f8f | 9770 | { |
b89b22fc | 9771 | if (cfun_fpr_save_p (i)) |
adf39f8f AK |
9772 | { |
9773 | restore_fpr (frame_pointer, | |
9774 | offset + next_offset, i); | |
75707b28 JJ |
9775 | cfa_restores |
9776 | = alloc_reg_note (REG_CFA_RESTORE, | |
9777 | gen_rtx_REG (DFmode, i), cfa_restores); | |
adf39f8f AK |
9778 | next_offset += 8; |
9779 | } | |
b3d31392 | 9780 | else if (!TARGET_PACKED_STACK) |
adf39f8f AK |
9781 | next_offset += 8; |
9782 | } | |
f4aa3848 | 9783 | |
4023fb28 | 9784 | } |
9db1d521 | 9785 | |
4023fb28 UW |
9786 | /* Return register. */ |
9787 | ||
c7453384 | 9788 | return_reg = gen_rtx_REG (Pmode, RETURN_REGNUM); |
4023fb28 UW |
9789 | |
9790 | /* Restore call saved gprs. */ | |
9791 | ||
adf39f8f | 9792 | if (cfun_frame_layout.first_restore_gpr != -1) |
4023fb28 | 9793 | { |
c3cc6b78 | 9794 | rtx insn, addr; |
1447dc69 HP |
9795 | int i; |
9796 | ||
c7453384 | 9797 | /* Check for global register and save them |
1447dc69 HP |
9798 | to stack location from where they get restored. */ |
9799 | ||
adf39f8f AK |
9800 | for (i = cfun_frame_layout.first_restore_gpr; |
9801 | i <= cfun_frame_layout.last_restore_gpr; | |
1447dc69 HP |
9802 | i++) |
9803 | { | |
75707b28 | 9804 | if (global_not_special_regno_p (i)) |
1447dc69 | 9805 | { |
0a81f074 | 9806 | addr = plus_constant (Pmode, frame_pointer, |
f4aa3848 | 9807 | offset + cfun_frame_layout.gprs_offset |
fb3712f6 | 9808 | + (i - cfun_frame_layout.first_save_gpr_slot) |
9602b6a1 | 9809 | * UNITS_PER_LONG); |
1447dc69 | 9810 | addr = gen_rtx_MEM (Pmode, addr); |
dcc9eb26 | 9811 | set_mem_alias_set (addr, get_frame_alias_set ()); |
1447dc69 | 9812 | emit_move_insn (addr, gen_rtx_REG (Pmode, i)); |
c7453384 | 9813 | } |
75707b28 JJ |
9814 | else |
9815 | cfa_restores | |
9816 | = alloc_reg_note (REG_CFA_RESTORE, | |
9817 | gen_rtx_REG (Pmode, i), cfa_restores); | |
1447dc69 | 9818 | } |
4023fb28 | 9819 | |
ed9676cf | 9820 | if (! sibcall) |
9db1d521 | 9821 | { |
ed9676cf | 9822 | /* Fetch return address from stack before load multiple, |
db716bde AK |
9823 | this will do good for scheduling. |
9824 | ||
9825 | Only do this if we already decided that r14 needs to be | |
9826 | saved to a stack slot. (And not just because r14 happens to | |
9827 | be in between two GPRs which need saving.) Otherwise it | |
9828 | would be difficult to take that decision back in | |
9829 | s390_optimize_prologue. */ | |
9830 | if (cfun_gpr_save_slot (RETURN_REGNUM) == -1) | |
ed9676cf AK |
9831 | { |
9832 | int return_regnum = find_unused_clobbered_reg(); | |
9833 | if (!return_regnum) | |
9834 | return_regnum = 4; | |
9835 | return_reg = gen_rtx_REG (Pmode, return_regnum); | |
38899e29 | 9836 | |
0a81f074 | 9837 | addr = plus_constant (Pmode, frame_pointer, |
adf39f8f | 9838 | offset + cfun_frame_layout.gprs_offset |
f4aa3848 | 9839 | + (RETURN_REGNUM |
fb3712f6 | 9840 | - cfun_frame_layout.first_save_gpr_slot) |
9602b6a1 | 9841 | * UNITS_PER_LONG); |
ed9676cf | 9842 | addr = gen_rtx_MEM (Pmode, addr); |
dcc9eb26 | 9843 | set_mem_alias_set (addr, get_frame_alias_set ()); |
ed9676cf | 9844 | emit_move_insn (return_reg, addr); |
db716bde AK |
9845 | |
9846 | /* Once we did that optimization we have to make sure | |
9847 | s390_optimize_prologue does not try to remove the | |
9848 | store of r14 since we will not be able to find the | |
9849 | load issued here. */ | |
9850 | cfun_frame_layout.save_return_addr_p = true; | |
ed9676cf | 9851 | } |
9db1d521 | 9852 | } |
4023fb28 | 9853 | |
adf39f8f AK |
9854 | insn = restore_gprs (frame_pointer, |
9855 | offset + cfun_frame_layout.gprs_offset | |
f4aa3848 | 9856 | + (cfun_frame_layout.first_restore_gpr |
fb3712f6 | 9857 | - cfun_frame_layout.first_save_gpr_slot) |
9602b6a1 | 9858 | * UNITS_PER_LONG, |
adf39f8f AK |
9859 | cfun_frame_layout.first_restore_gpr, |
9860 | cfun_frame_layout.last_restore_gpr); | |
75707b28 JJ |
9861 | insn = emit_insn (insn); |
9862 | REG_NOTES (insn) = cfa_restores; | |
9863 | add_reg_note (insn, REG_CFA_DEF_CFA, | |
0a81f074 RS |
9864 | plus_constant (Pmode, stack_pointer_rtx, |
9865 | STACK_POINTER_OFFSET)); | |
75707b28 | 9866 | RTX_FRAME_RELATED_P (insn) = 1; |
4023fb28 | 9867 | } |
9db1d521 | 9868 | |
6455a49e AK |
9869 | s390_restore_gprs_from_fprs (); |
9870 | ||
ed9676cf AK |
9871 | if (! sibcall) |
9872 | { | |
c7453384 | 9873 | |
ed9676cf | 9874 | /* Return to caller. */ |
38899e29 | 9875 | |
ed9676cf | 9876 | p = rtvec_alloc (2); |
38899e29 | 9877 | |
3810076b | 9878 | RTVEC_ELT (p, 0) = ret_rtx; |
ed9676cf AK |
9879 | RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode, return_reg); |
9880 | emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p)); | |
9881 | } | |
9db1d521 HP |
9882 | } |
9883 | ||
177bc204 RS |
9884 | /* Implement TARGET_SET_UP_BY_PROLOGUE. */ |
9885 | ||
9886 | static void | |
9887 | s300_set_up_by_prologue (hard_reg_set_container *regs) | |
9888 | { | |
9889 | if (cfun->machine->base_reg | |
9890 | && !call_really_used_regs[REGNO (cfun->machine->base_reg)]) | |
9891 | SET_HARD_REG_BIT (regs->set, REGNO (cfun->machine->base_reg)); | |
9892 | } | |
9893 | ||
9894 | /* Return true if the function can use simple_return to return outside | |
9895 | of a shrink-wrapped region. At present shrink-wrapping is supported | |
9896 | in all cases. */ | |
9897 | ||
9898 | bool | |
9899 | s390_can_use_simple_return_insn (void) | |
9900 | { | |
9901 | return true; | |
9902 | } | |
9903 | ||
9904 | /* Return true if the epilogue is guaranteed to contain only a return | |
9905 | instruction and if a direct return can therefore be used instead. | |
9906 | One of the main advantages of using direct return instructions | |
9907 | is that we can then use conditional returns. */ | |
9908 | ||
9909 | bool | |
9910 | s390_can_use_return_insn (void) | |
9911 | { | |
9912 | int i; | |
9913 | ||
9914 | if (!reload_completed) | |
9915 | return false; | |
9916 | ||
9917 | if (crtl->profile) | |
9918 | return false; | |
9919 | ||
9920 | if (TARGET_TPF_PROFILING) | |
9921 | return false; | |
9922 | ||
9923 | for (i = 0; i < 16; i++) | |
9924 | if (cfun_gpr_save_slot (i)) | |
9925 | return false; | |
9926 | ||
6e77facf AK |
9927 | /* For 31 bit this is not covered by the frame_size check below |
9928 | since f4, f6 are saved in the register save area without needing | |
9929 | additional stack space. */ | |
9930 | if (!TARGET_64BIT | |
9931 | && (cfun_fpr_save_p (FPR4_REGNUM) || cfun_fpr_save_p (FPR6_REGNUM))) | |
9932 | return false; | |
9933 | ||
177bc204 RS |
9934 | if (cfun->machine->base_reg |
9935 | && !call_really_used_regs[REGNO (cfun->machine->base_reg)]) | |
9936 | return false; | |
9937 | ||
9938 | return cfun_frame_layout.frame_size == 0; | |
9939 | } | |
9db1d521 | 9940 | |
085261c8 AK |
9941 | /* The VX ABI differs for vararg functions. Therefore we need the |
9942 | prototype of the callee to be available when passing vector type | |
9943 | values. */ | |
9944 | static const char * | |
9945 | s390_invalid_arg_for_unprototyped_fn (const_tree typelist, const_tree funcdecl, const_tree val) | |
9946 | { | |
9947 | return ((TARGET_VX_ABI | |
9948 | && typelist == 0 | |
9949 | && VECTOR_TYPE_P (TREE_TYPE (val)) | |
9950 | && (funcdecl == NULL_TREE | |
9951 | || (TREE_CODE (funcdecl) == FUNCTION_DECL | |
9952 | && DECL_BUILT_IN_CLASS (funcdecl) != BUILT_IN_MD))) | |
9953 | ? N_("Vector argument passed to unprototyped function") | |
9954 | : NULL); | |
9955 | } | |
9956 | ||
9957 | ||
c7453384 | 9958 | /* Return the size in bytes of a function argument of |
994fe660 UW |
9959 | type TYPE and/or mode MODE. At least one of TYPE or |
9960 | MODE must be specified. */ | |
9db1d521 HP |
9961 | |
9962 | static int | |
ef4bddc2 | 9963 | s390_function_arg_size (machine_mode mode, const_tree type) |
9db1d521 HP |
9964 | { |
9965 | if (type) | |
9966 | return int_size_in_bytes (type); | |
9967 | ||
d65f7478 | 9968 | /* No type info available for some library calls ... */ |
9db1d521 HP |
9969 | if (mode != BLKmode) |
9970 | return GET_MODE_SIZE (mode); | |
9971 | ||
9972 | /* If we have neither type nor mode, abort */ | |
8d933e31 | 9973 | gcc_unreachable (); |
9db1d521 HP |
9974 | } |
9975 | ||
085261c8 AK |
9976 | /* Return true if a function argument of type TYPE and mode MODE |
9977 | is to be passed in a vector register, if available. */ | |
9978 | ||
9979 | bool | |
9980 | s390_function_arg_vector (machine_mode mode, const_tree type) | |
9981 | { | |
9982 | if (!TARGET_VX_ABI) | |
9983 | return false; | |
9984 | ||
9985 | if (s390_function_arg_size (mode, type) > 16) | |
9986 | return false; | |
9987 | ||
9988 | /* No type info available for some library calls ... */ | |
9989 | if (!type) | |
9990 | return VECTOR_MODE_P (mode); | |
9991 | ||
9992 | /* The ABI says that record types with a single member are treated | |
9993 | just like that member would be. */ | |
9994 | while (TREE_CODE (type) == RECORD_TYPE) | |
9995 | { | |
9996 | tree field, single = NULL_TREE; | |
9997 | ||
9998 | for (field = TYPE_FIELDS (type); field; field = DECL_CHAIN (field)) | |
9999 | { | |
10000 | if (TREE_CODE (field) != FIELD_DECL) | |
10001 | continue; | |
10002 | ||
10003 | if (single == NULL_TREE) | |
10004 | single = TREE_TYPE (field); | |
10005 | else | |
10006 | return false; | |
10007 | } | |
10008 | ||
10009 | if (single == NULL_TREE) | |
10010 | return false; | |
10011 | else | |
10012 | { | |
10013 | /* If the field declaration adds extra byte due to | |
10014 | e.g. padding this is not accepted as vector type. */ | |
10015 | if (int_size_in_bytes (single) <= 0 | |
10016 | || int_size_in_bytes (single) != int_size_in_bytes (type)) | |
10017 | return false; | |
10018 | type = single; | |
10019 | } | |
10020 | } | |
10021 | ||
10022 | return VECTOR_TYPE_P (type); | |
10023 | } | |
10024 | ||
82b1c974 UW |
10025 | /* Return true if a function argument of type TYPE and mode MODE |
10026 | is to be passed in a floating-point register, if available. */ | |
10027 | ||
10028 | static bool | |
ef4bddc2 | 10029 | s390_function_arg_float (machine_mode mode, const_tree type) |
82b1c974 | 10030 | { |
085261c8 | 10031 | if (s390_function_arg_size (mode, type) > 8) |
8c17530e UW |
10032 | return false; |
10033 | ||
82b1c974 UW |
10034 | /* Soft-float changes the ABI: no floating-point registers are used. */ |
10035 | if (TARGET_SOFT_FLOAT) | |
10036 | return false; | |
10037 | ||
10038 | /* No type info available for some library calls ... */ | |
10039 | if (!type) | |
4dc19cc0 | 10040 | return mode == SFmode || mode == DFmode || mode == SDmode || mode == DDmode; |
82b1c974 UW |
10041 | |
10042 | /* The ABI says that record types with a single member are treated | |
10043 | just like that member would be. */ | |
10044 | while (TREE_CODE (type) == RECORD_TYPE) | |
10045 | { | |
10046 | tree field, single = NULL_TREE; | |
10047 | ||
910ad8de | 10048 | for (field = TYPE_FIELDS (type); field; field = DECL_CHAIN (field)) |
82b1c974 UW |
10049 | { |
10050 | if (TREE_CODE (field) != FIELD_DECL) | |
10051 | continue; | |
10052 | ||
10053 | if (single == NULL_TREE) | |
10054 | single = TREE_TYPE (field); | |
10055 | else | |
10056 | return false; | |
10057 | } | |
10058 | ||
10059 | if (single == NULL_TREE) | |
10060 | return false; | |
10061 | else | |
10062 | type = single; | |
10063 | } | |
10064 | ||
10065 | return TREE_CODE (type) == REAL_TYPE; | |
10066 | } | |
10067 | ||
8c17530e UW |
10068 | /* Return true if a function argument of type TYPE and mode MODE |
10069 | is to be passed in an integer register, or a pair of integer | |
10070 | registers, if available. */ | |
10071 | ||
10072 | static bool | |
ef4bddc2 | 10073 | s390_function_arg_integer (machine_mode mode, const_tree type) |
8c17530e UW |
10074 | { |
10075 | int size = s390_function_arg_size (mode, type); | |
10076 | if (size > 8) | |
10077 | return false; | |
10078 | ||
10079 | /* No type info available for some library calls ... */ | |
10080 | if (!type) | |
10081 | return GET_MODE_CLASS (mode) == MODE_INT | |
4dc19cc0 | 10082 | || (TARGET_SOFT_FLOAT && SCALAR_FLOAT_MODE_P (mode)); |
8c17530e UW |
10083 | |
10084 | /* We accept small integral (and similar) types. */ | |
10085 | if (INTEGRAL_TYPE_P (type) | |
38899e29 | 10086 | || POINTER_TYPE_P (type) |
0d697034 | 10087 | || TREE_CODE (type) == NULLPTR_TYPE |
8c17530e UW |
10088 | || TREE_CODE (type) == OFFSET_TYPE |
10089 | || (TARGET_SOFT_FLOAT && TREE_CODE (type) == REAL_TYPE)) | |
10090 | return true; | |
10091 | ||
10092 | /* We also accept structs of size 1, 2, 4, 8 that are not | |
38899e29 | 10093 | passed in floating-point registers. */ |
8c17530e UW |
10094 | if (AGGREGATE_TYPE_P (type) |
10095 | && exact_log2 (size) >= 0 | |
10096 | && !s390_function_arg_float (mode, type)) | |
10097 | return true; | |
10098 | ||
10099 | return false; | |
10100 | } | |
10101 | ||
994fe660 UW |
10102 | /* Return 1 if a function argument of type TYPE and mode MODE |
10103 | is to be passed by reference. The ABI specifies that only | |
10104 | structures of size 1, 2, 4, or 8 bytes are passed by value, | |
10105 | all other structures (and complex numbers) are passed by | |
10106 | reference. */ | |
10107 | ||
8cd5a4e0 | 10108 | static bool |
d5cc9181 | 10109 | s390_pass_by_reference (cumulative_args_t ca ATTRIBUTE_UNUSED, |
ef4bddc2 | 10110 | machine_mode mode, const_tree type, |
8cd5a4e0 | 10111 | bool named ATTRIBUTE_UNUSED) |
9db1d521 HP |
10112 | { |
10113 | int size = s390_function_arg_size (mode, type); | |
085261c8 AK |
10114 | |
10115 | if (s390_function_arg_vector (mode, type)) | |
10116 | return false; | |
10117 | ||
8c17530e UW |
10118 | if (size > 8) |
10119 | return true; | |
9db1d521 HP |
10120 | |
10121 | if (type) | |
10122 | { | |
8c17530e | 10123 | if (AGGREGATE_TYPE_P (type) && exact_log2 (size) < 0) |
085261c8 | 10124 | return true; |
9db1d521 | 10125 | |
8c17530e UW |
10126 | if (TREE_CODE (type) == COMPLEX_TYPE |
10127 | || TREE_CODE (type) == VECTOR_TYPE) | |
085261c8 | 10128 | return true; |
9db1d521 | 10129 | } |
c7453384 | 10130 | |
085261c8 | 10131 | return false; |
9db1d521 HP |
10132 | } |
10133 | ||
10134 | /* Update the data in CUM to advance over an argument of mode MODE and | |
10135 | data type TYPE. (TYPE is null for libcalls where that information | |
994fe660 UW |
10136 | may not be available.). The boolean NAMED specifies whether the |
10137 | argument is a named argument (as opposed to an unnamed argument | |
10138 | matching an ellipsis). */ | |
9db1d521 | 10139 | |
3cb1da52 | 10140 | static void |
ef4bddc2 | 10141 | s390_function_arg_advance (cumulative_args_t cum_v, machine_mode mode, |
085261c8 | 10142 | const_tree type, bool named) |
9db1d521 | 10143 | { |
d5cc9181 JR |
10144 | CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v); |
10145 | ||
085261c8 AK |
10146 | if (s390_function_arg_vector (mode, type)) |
10147 | { | |
10148 | /* We are called for unnamed vector stdarg arguments which are | |
10149 | passed on the stack. In this case this hook does not have to | |
10150 | do anything since stack arguments are tracked by common | |
10151 | code. */ | |
10152 | if (!named) | |
10153 | return; | |
10154 | cum->vrs += 1; | |
10155 | } | |
10156 | else if (s390_function_arg_float (mode, type)) | |
9db1d521 | 10157 | { |
82b1c974 | 10158 | cum->fprs += 1; |
9db1d521 | 10159 | } |
8c17530e | 10160 | else if (s390_function_arg_integer (mode, type)) |
9db1d521 HP |
10161 | { |
10162 | int size = s390_function_arg_size (mode, type); | |
9602b6a1 | 10163 | cum->gprs += ((size + UNITS_PER_LONG - 1) / UNITS_PER_LONG); |
9db1d521 | 10164 | } |
8c17530e | 10165 | else |
8d933e31 | 10166 | gcc_unreachable (); |
9db1d521 HP |
10167 | } |
10168 | ||
994fe660 UW |
10169 | /* Define where to put the arguments to a function. |
10170 | Value is zero to push the argument on the stack, | |
10171 | or a hard register in which to store the argument. | |
10172 | ||
10173 | MODE is the argument's machine mode. | |
10174 | TYPE is the data type of the argument (as a tree). | |
10175 | This is null for libcalls where that information may | |
10176 | not be available. | |
10177 | CUM is a variable of type CUMULATIVE_ARGS which gives info about | |
10178 | the preceding args and about the function being called. | |
10179 | NAMED is nonzero if this argument is a named parameter | |
c7453384 | 10180 | (otherwise it is an extra parameter matching an ellipsis). |
994fe660 UW |
10181 | |
10182 | On S/390, we use general purpose registers 2 through 6 to | |
10183 | pass integer, pointer, and certain structure arguments, and | |
10184 | floating point registers 0 and 2 (0, 2, 4, and 6 on 64-bit) | |
10185 | to pass floating point arguments. All remaining arguments | |
10186 | are pushed to the stack. */ | |
9db1d521 | 10187 | |
3cb1da52 | 10188 | static rtx |
ef4bddc2 | 10189 | s390_function_arg (cumulative_args_t cum_v, machine_mode mode, |
085261c8 | 10190 | const_tree type, bool named) |
9db1d521 | 10191 | { |
d5cc9181 JR |
10192 | CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v); |
10193 | ||
085261c8 AK |
10194 | |
10195 | if (s390_function_arg_vector (mode, type)) | |
10196 | { | |
10197 | /* Vector arguments being part of the ellipsis are passed on the | |
10198 | stack. */ | |
10199 | if (!named || (cum->vrs + 1 > VEC_ARG_NUM_REG)) | |
10200 | return NULL_RTX; | |
10201 | ||
10202 | return gen_rtx_REG (mode, cum->vrs + FIRST_VEC_ARG_REGNO); | |
10203 | } | |
10204 | else if (s390_function_arg_float (mode, type)) | |
9db1d521 | 10205 | { |
29a79fcf | 10206 | if (cum->fprs + 1 > FP_ARG_NUM_REG) |
085261c8 | 10207 | return NULL_RTX; |
9db1d521 | 10208 | else |
f1c25d3b | 10209 | return gen_rtx_REG (mode, cum->fprs + 16); |
9db1d521 | 10210 | } |
8c17530e | 10211 | else if (s390_function_arg_integer (mode, type)) |
9db1d521 HP |
10212 | { |
10213 | int size = s390_function_arg_size (mode, type); | |
9602b6a1 | 10214 | int n_gprs = (size + UNITS_PER_LONG - 1) / UNITS_PER_LONG; |
9db1d521 | 10215 | |
29a79fcf | 10216 | if (cum->gprs + n_gprs > GP_ARG_NUM_REG) |
085261c8 | 10217 | return NULL_RTX; |
9602b6a1 | 10218 | else if (n_gprs == 1 || UNITS_PER_WORD == UNITS_PER_LONG) |
f1c25d3b | 10219 | return gen_rtx_REG (mode, cum->gprs + 2); |
9602b6a1 AK |
10220 | else if (n_gprs == 2) |
10221 | { | |
10222 | rtvec p = rtvec_alloc (2); | |
10223 | ||
10224 | RTVEC_ELT (p, 0) | |
10225 | = gen_rtx_EXPR_LIST (SImode, gen_rtx_REG (SImode, cum->gprs + 2), | |
10226 | const0_rtx); | |
10227 | RTVEC_ELT (p, 1) | |
10228 | = gen_rtx_EXPR_LIST (SImode, gen_rtx_REG (SImode, cum->gprs + 3), | |
10229 | GEN_INT (4)); | |
10230 | ||
10231 | return gen_rtx_PARALLEL (mode, p); | |
10232 | } | |
9db1d521 | 10233 | } |
8c17530e UW |
10234 | |
10235 | /* After the real arguments, expand_call calls us once again | |
10236 | with a void_type_node type. Whatever we return here is | |
10237 | passed as operand 2 to the call expanders. | |
10238 | ||
10239 | We don't need this feature ... */ | |
10240 | else if (type == void_type_node) | |
10241 | return const0_rtx; | |
10242 | ||
8d933e31 | 10243 | gcc_unreachable (); |
8c17530e UW |
10244 | } |
10245 | ||
10246 | /* Return true if return values of type TYPE should be returned | |
10247 | in a memory buffer whose address is passed by the caller as | |
10248 | hidden first argument. */ | |
10249 | ||
10250 | static bool | |
586de218 | 10251 | s390_return_in_memory (const_tree type, const_tree fundecl ATTRIBUTE_UNUSED) |
8c17530e UW |
10252 | { |
10253 | /* We accept small integral (and similar) types. */ | |
10254 | if (INTEGRAL_TYPE_P (type) | |
38899e29 | 10255 | || POINTER_TYPE_P (type) |
8c17530e UW |
10256 | || TREE_CODE (type) == OFFSET_TYPE |
10257 | || TREE_CODE (type) == REAL_TYPE) | |
10258 | return int_size_in_bytes (type) > 8; | |
10259 | ||
085261c8 AK |
10260 | /* vector types which fit into a VR. */ |
10261 | if (TARGET_VX_ABI | |
10262 | && VECTOR_TYPE_P (type) | |
10263 | && int_size_in_bytes (type) <= 16) | |
10264 | return false; | |
10265 | ||
8c17530e UW |
10266 | /* Aggregates and similar constructs are always returned |
10267 | in memory. */ | |
10268 | if (AGGREGATE_TYPE_P (type) | |
10269 | || TREE_CODE (type) == COMPLEX_TYPE | |
085261c8 | 10270 | || VECTOR_TYPE_P (type)) |
8c17530e UW |
10271 | return true; |
10272 | ||
10273 | /* ??? We get called on all sorts of random stuff from | |
10274 | aggregate_value_p. We can't abort, but it's not clear | |
10275 | what's safe to return. Pretend it's a struct I guess. */ | |
10276 | return true; | |
10277 | } | |
10278 | ||
cde0f3fd PB |
10279 | /* Function arguments and return values are promoted to word size. */ |
10280 | ||
ef4bddc2 RS |
10281 | static machine_mode |
10282 | s390_promote_function_mode (const_tree type, machine_mode mode, | |
cde0f3fd PB |
10283 | int *punsignedp, |
10284 | const_tree fntype ATTRIBUTE_UNUSED, | |
10285 | int for_return ATTRIBUTE_UNUSED) | |
10286 | { | |
10287 | if (INTEGRAL_MODE_P (mode) | |
9602b6a1 | 10288 | && GET_MODE_SIZE (mode) < UNITS_PER_LONG) |
cde0f3fd | 10289 | { |
5e617be8 | 10290 | if (type != NULL_TREE && POINTER_TYPE_P (type)) |
cde0f3fd PB |
10291 | *punsignedp = POINTERS_EXTEND_UNSIGNED; |
10292 | return Pmode; | |
10293 | } | |
10294 | ||
10295 | return mode; | |
10296 | } | |
10297 | ||
b46616fd AK |
10298 | /* Define where to return a (scalar) value of type RET_TYPE. |
10299 | If RET_TYPE is null, define where to return a (scalar) | |
8c17530e UW |
10300 | value of mode MODE from a libcall. */ |
10301 | ||
b46616fd | 10302 | static rtx |
ef4bddc2 | 10303 | s390_function_and_libcall_value (machine_mode mode, |
b46616fd AK |
10304 | const_tree ret_type, |
10305 | const_tree fntype_or_decl, | |
10306 | bool outgoing ATTRIBUTE_UNUSED) | |
8c17530e | 10307 | { |
085261c8 AK |
10308 | /* For vector return types it is important to use the RET_TYPE |
10309 | argument whenever available since the middle-end might have | |
10310 | changed the mode to a scalar mode. */ | |
10311 | bool vector_ret_type_p = ((ret_type && VECTOR_TYPE_P (ret_type)) | |
10312 | || (!ret_type && VECTOR_MODE_P (mode))); | |
10313 | ||
b46616fd AK |
10314 | /* For normal functions perform the promotion as |
10315 | promote_function_mode would do. */ | |
10316 | if (ret_type) | |
8c17530e | 10317 | { |
b46616fd AK |
10318 | int unsignedp = TYPE_UNSIGNED (ret_type); |
10319 | mode = promote_function_mode (ret_type, mode, &unsignedp, | |
10320 | fntype_or_decl, 1); | |
8c17530e UW |
10321 | } |
10322 | ||
085261c8 AK |
10323 | gcc_assert (GET_MODE_CLASS (mode) == MODE_INT |
10324 | || SCALAR_FLOAT_MODE_P (mode) | |
10325 | || (TARGET_VX_ABI && vector_ret_type_p)); | |
10326 | gcc_assert (GET_MODE_SIZE (mode) <= (TARGET_VX_ABI ? 16 : 8)); | |
8c17530e | 10327 | |
085261c8 AK |
10328 | if (TARGET_VX_ABI && vector_ret_type_p) |
10329 | return gen_rtx_REG (mode, FIRST_VEC_ARG_REGNO); | |
10330 | else if (TARGET_HARD_FLOAT && SCALAR_FLOAT_MODE_P (mode)) | |
8c17530e | 10331 | return gen_rtx_REG (mode, 16); |
9602b6a1 AK |
10332 | else if (GET_MODE_SIZE (mode) <= UNITS_PER_LONG |
10333 | || UNITS_PER_LONG == UNITS_PER_WORD) | |
8c17530e | 10334 | return gen_rtx_REG (mode, 2); |
9602b6a1 AK |
10335 | else if (GET_MODE_SIZE (mode) == 2 * UNITS_PER_LONG) |
10336 | { | |
b46616fd AK |
10337 | /* This case is triggered when returning a 64 bit value with |
10338 | -m31 -mzarch. Although the value would fit into a single | |
10339 | register it has to be forced into a 32 bit register pair in | |
10340 | order to match the ABI. */ | |
9602b6a1 AK |
10341 | rtvec p = rtvec_alloc (2); |
10342 | ||
10343 | RTVEC_ELT (p, 0) | |
10344 | = gen_rtx_EXPR_LIST (SImode, gen_rtx_REG (SImode, 2), const0_rtx); | |
10345 | RTVEC_ELT (p, 1) | |
10346 | = gen_rtx_EXPR_LIST (SImode, gen_rtx_REG (SImode, 3), GEN_INT (4)); | |
10347 | ||
10348 | return gen_rtx_PARALLEL (mode, p); | |
10349 | } | |
10350 | ||
10351 | gcc_unreachable (); | |
9db1d521 HP |
10352 | } |
10353 | ||
b46616fd AK |
10354 | /* Define where to return a scalar return value of type RET_TYPE. */ |
10355 | ||
10356 | static rtx | |
10357 | s390_function_value (const_tree ret_type, const_tree fn_decl_or_type, | |
10358 | bool outgoing) | |
10359 | { | |
10360 | return s390_function_and_libcall_value (TYPE_MODE (ret_type), ret_type, | |
10361 | fn_decl_or_type, outgoing); | |
10362 | } | |
10363 | ||
10364 | /* Define where to return a scalar libcall return value of mode | |
10365 | MODE. */ | |
10366 | ||
10367 | static rtx | |
ef4bddc2 | 10368 | s390_libcall_value (machine_mode mode, const_rtx fun ATTRIBUTE_UNUSED) |
b46616fd AK |
10369 | { |
10370 | return s390_function_and_libcall_value (mode, NULL_TREE, | |
10371 | NULL_TREE, true); | |
10372 | } | |
10373 | ||
9db1d521 | 10374 | |
994fe660 UW |
10375 | /* Create and return the va_list datatype. |
10376 | ||
10377 | On S/390, va_list is an array type equivalent to | |
10378 | ||
10379 | typedef struct __va_list_tag | |
10380 | { | |
10381 | long __gpr; | |
10382 | long __fpr; | |
10383 | void *__overflow_arg_area; | |
10384 | void *__reg_save_area; | |
994fe660 UW |
10385 | } va_list[1]; |
10386 | ||
10387 | where __gpr and __fpr hold the number of general purpose | |
10388 | or floating point arguments used up to now, respectively, | |
c7453384 | 10389 | __overflow_arg_area points to the stack location of the |
994fe660 UW |
10390 | next argument passed on the stack, and __reg_save_area |
10391 | always points to the start of the register area in the | |
10392 | call frame of the current function. The function prologue | |
10393 | saves all registers used for argument passing into this | |
10394 | area if the function uses variable arguments. */ | |
9db1d521 | 10395 | |
c35d187f RH |
10396 | static tree |
10397 | s390_build_builtin_va_list (void) | |
9db1d521 HP |
10398 | { |
10399 | tree f_gpr, f_fpr, f_ovf, f_sav, record, type_decl; | |
10400 | ||
47798692 | 10401 | record = lang_hooks.types.make_type (RECORD_TYPE); |
9db1d521 HP |
10402 | |
10403 | type_decl = | |
4c4bde29 AH |
10404 | build_decl (BUILTINS_LOCATION, |
10405 | TYPE_DECL, get_identifier ("__va_list_tag"), record); | |
9db1d521 | 10406 | |
4c4bde29 AH |
10407 | f_gpr = build_decl (BUILTINS_LOCATION, |
10408 | FIELD_DECL, get_identifier ("__gpr"), | |
9db1d521 | 10409 | long_integer_type_node); |
4c4bde29 AH |
10410 | f_fpr = build_decl (BUILTINS_LOCATION, |
10411 | FIELD_DECL, get_identifier ("__fpr"), | |
9db1d521 | 10412 | long_integer_type_node); |
4c4bde29 AH |
10413 | f_ovf = build_decl (BUILTINS_LOCATION, |
10414 | FIELD_DECL, get_identifier ("__overflow_arg_area"), | |
9db1d521 | 10415 | ptr_type_node); |
4c4bde29 AH |
10416 | f_sav = build_decl (BUILTINS_LOCATION, |
10417 | FIELD_DECL, get_identifier ("__reg_save_area"), | |
9db1d521 HP |
10418 | ptr_type_node); |
10419 | ||
29a79fcf UW |
10420 | va_list_gpr_counter_field = f_gpr; |
10421 | va_list_fpr_counter_field = f_fpr; | |
10422 | ||
9db1d521 HP |
10423 | DECL_FIELD_CONTEXT (f_gpr) = record; |
10424 | DECL_FIELD_CONTEXT (f_fpr) = record; | |
10425 | DECL_FIELD_CONTEXT (f_ovf) = record; | |
10426 | DECL_FIELD_CONTEXT (f_sav) = record; | |
10427 | ||
0fd2eac2 | 10428 | TYPE_STUB_DECL (record) = type_decl; |
9db1d521 HP |
10429 | TYPE_NAME (record) = type_decl; |
10430 | TYPE_FIELDS (record) = f_gpr; | |
910ad8de NF |
10431 | DECL_CHAIN (f_gpr) = f_fpr; |
10432 | DECL_CHAIN (f_fpr) = f_ovf; | |
10433 | DECL_CHAIN (f_ovf) = f_sav; | |
9db1d521 HP |
10434 | |
10435 | layout_type (record); | |
10436 | ||
10437 | /* The correct type is an array type of one element. */ | |
10438 | return build_array_type (record, build_index_type (size_zero_node)); | |
10439 | } | |
10440 | ||
994fe660 | 10441 | /* Implement va_start by filling the va_list structure VALIST. |
6c535c69 ZW |
10442 | STDARG_P is always true, and ignored. |
10443 | NEXTARG points to the first anonymous stack argument. | |
994fe660 | 10444 | |
f710504c | 10445 | The following global variables are used to initialize |
994fe660 UW |
10446 | the va_list structure: |
10447 | ||
38173d38 | 10448 | crtl->args.info: |
994fe660 | 10449 | holds number of gprs and fprs used for named arguments. |
38173d38 | 10450 | crtl->args.arg_offset_rtx: |
994fe660 UW |
10451 | holds the offset of the first anonymous stack argument |
10452 | (relative to the virtual arg pointer). */ | |
9db1d521 | 10453 | |
d7bd8aeb | 10454 | static void |
9c808aad | 10455 | s390_va_start (tree valist, rtx nextarg ATTRIBUTE_UNUSED) |
9db1d521 HP |
10456 | { |
10457 | HOST_WIDE_INT n_gpr, n_fpr; | |
10458 | int off; | |
10459 | tree f_gpr, f_fpr, f_ovf, f_sav; | |
10460 | tree gpr, fpr, ovf, sav, t; | |
10461 | ||
10462 | f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node)); | |
910ad8de NF |
10463 | f_fpr = DECL_CHAIN (f_gpr); |
10464 | f_ovf = DECL_CHAIN (f_fpr); | |
10465 | f_sav = DECL_CHAIN (f_ovf); | |
9db1d521 | 10466 | |
86710a8b | 10467 | valist = build_simple_mem_ref (valist); |
47a25a46 RG |
10468 | gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE); |
10469 | fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE); | |
10470 | ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE); | |
10471 | sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE); | |
9db1d521 HP |
10472 | |
10473 | /* Count number of gp and fp argument registers used. */ | |
10474 | ||
38173d38 JH |
10475 | n_gpr = crtl->args.info.gprs; |
10476 | n_fpr = crtl->args.info.fprs; | |
9db1d521 | 10477 | |
29a79fcf UW |
10478 | if (cfun->va_list_gpr_size) |
10479 | { | |
726a989a RB |
10480 | t = build2 (MODIFY_EXPR, TREE_TYPE (gpr), gpr, |
10481 | build_int_cst (NULL_TREE, n_gpr)); | |
29a79fcf UW |
10482 | TREE_SIDE_EFFECTS (t) = 1; |
10483 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
10484 | } | |
9db1d521 | 10485 | |
29a79fcf UW |
10486 | if (cfun->va_list_fpr_size) |
10487 | { | |
726a989a | 10488 | t = build2 (MODIFY_EXPR, TREE_TYPE (fpr), fpr, |
47a25a46 | 10489 | build_int_cst (NULL_TREE, n_fpr)); |
29a79fcf UW |
10490 | TREE_SIDE_EFFECTS (t) = 1; |
10491 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
10492 | } | |
9db1d521 | 10493 | |
085261c8 AK |
10494 | /* Find the overflow area. |
10495 | FIXME: This currently is too pessimistic when the vector ABI is | |
10496 | enabled. In that case we *always* set up the overflow area | |
10497 | pointer. */ | |
29a79fcf | 10498 | if (n_gpr + cfun->va_list_gpr_size > GP_ARG_NUM_REG |
085261c8 AK |
10499 | || n_fpr + cfun->va_list_fpr_size > FP_ARG_NUM_REG |
10500 | || TARGET_VX_ABI) | |
29a79fcf UW |
10501 | { |
10502 | t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx); | |
9db1d521 | 10503 | |
38173d38 | 10504 | off = INTVAL (crtl->args.arg_offset_rtx); |
29a79fcf UW |
10505 | off = off < 0 ? 0 : off; |
10506 | if (TARGET_DEBUG_ARG) | |
10507 | fprintf (stderr, "va_start: n_gpr = %d, n_fpr = %d off %d\n", | |
10508 | (int)n_gpr, (int)n_fpr, off); | |
9db1d521 | 10509 | |
5d49b6a7 | 10510 | t = fold_build_pointer_plus_hwi (t, off); |
9db1d521 | 10511 | |
726a989a | 10512 | t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t); |
29a79fcf UW |
10513 | TREE_SIDE_EFFECTS (t) = 1; |
10514 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
10515 | } | |
9db1d521 HP |
10516 | |
10517 | /* Find the register save area. */ | |
29a79fcf UW |
10518 | if ((cfun->va_list_gpr_size && n_gpr < GP_ARG_NUM_REG) |
10519 | || (cfun->va_list_fpr_size && n_fpr < FP_ARG_NUM_REG)) | |
10520 | { | |
10521 | t = make_tree (TREE_TYPE (sav), return_address_pointer_rtx); | |
5d49b6a7 | 10522 | t = fold_build_pointer_plus_hwi (t, -RETURN_REGNUM * UNITS_PER_LONG); |
f4aa3848 | 10523 | |
726a989a | 10524 | t = build2 (MODIFY_EXPR, TREE_TYPE (sav), sav, t); |
29a79fcf UW |
10525 | TREE_SIDE_EFFECTS (t) = 1; |
10526 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
10527 | } | |
9db1d521 HP |
10528 | } |
10529 | ||
c7453384 | 10530 | /* Implement va_arg by updating the va_list structure |
994fe660 | 10531 | VALIST as required to retrieve an argument of type |
c7453384 EC |
10532 | TYPE, and returning that argument. |
10533 | ||
994fe660 | 10534 | Generates code equivalent to: |
c7453384 | 10535 | |
9db1d521 HP |
10536 | if (integral value) { |
10537 | if (size <= 4 && args.gpr < 5 || | |
c7453384 | 10538 | size > 4 && args.gpr < 4 ) |
9db1d521 HP |
10539 | ret = args.reg_save_area[args.gpr+8] |
10540 | else | |
10541 | ret = *args.overflow_arg_area++; | |
085261c8 AK |
10542 | } else if (vector value) { |
10543 | ret = *args.overflow_arg_area; | |
10544 | args.overflow_arg_area += size / 8; | |
9db1d521 HP |
10545 | } else if (float value) { |
10546 | if (args.fgpr < 2) | |
10547 | ret = args.reg_save_area[args.fpr+64] | |
10548 | else | |
10549 | ret = *args.overflow_arg_area++; | |
10550 | } else if (aggregate value) { | |
10551 | if (args.gpr < 5) | |
10552 | ret = *args.reg_save_area[args.gpr] | |
10553 | else | |
10554 | ret = **args.overflow_arg_area++; | |
10555 | } */ | |
10556 | ||
ab96de7e | 10557 | static tree |
f4aa3848 | 10558 | s390_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p, |
726a989a | 10559 | gimple_seq *post_p ATTRIBUTE_UNUSED) |
9db1d521 HP |
10560 | { |
10561 | tree f_gpr, f_fpr, f_ovf, f_sav; | |
10562 | tree gpr, fpr, ovf, sav, reg, t, u; | |
10563 | int indirect_p, size, n_reg, sav_ofs, sav_scale, max_reg; | |
085261c8 AK |
10564 | tree lab_false, lab_over; |
10565 | tree addr = create_tmp_var (ptr_type_node, "addr"); | |
10566 | bool left_align_p; /* How a value < UNITS_PER_LONG is aligned within | |
10567 | a stack slot. */ | |
9db1d521 HP |
10568 | |
10569 | f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node)); | |
910ad8de NF |
10570 | f_fpr = DECL_CHAIN (f_gpr); |
10571 | f_ovf = DECL_CHAIN (f_fpr); | |
10572 | f_sav = DECL_CHAIN (f_ovf); | |
9db1d521 | 10573 | |
47a25a46 RG |
10574 | gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE); |
10575 | fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE); | |
47a25a46 | 10576 | sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE); |
9db1d521 | 10577 | |
726a989a RB |
10578 | /* The tree for args* cannot be shared between gpr/fpr and ovf since |
10579 | both appear on a lhs. */ | |
10580 | valist = unshare_expr (valist); | |
10581 | ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE); | |
10582 | ||
9db1d521 HP |
10583 | size = int_size_in_bytes (type); |
10584 | ||
8cd5a4e0 | 10585 | if (pass_by_reference (NULL, TYPE_MODE (type), type, false)) |
9db1d521 HP |
10586 | { |
10587 | if (TARGET_DEBUG_ARG) | |
10588 | { | |
10589 | fprintf (stderr, "va_arg: aggregate type"); | |
10590 | debug_tree (type); | |
10591 | } | |
10592 | ||
10593 | /* Aggregates are passed by reference. */ | |
10594 | indirect_p = 1; | |
10595 | reg = gpr; | |
10596 | n_reg = 1; | |
ea506297 | 10597 | |
b3d31392 | 10598 | /* kernel stack layout on 31 bit: It is assumed here that no padding |
ea506297 AK |
10599 | will be added by s390_frame_info because for va_args always an even |
10600 | number of gprs has to be saved r15-r2 = 14 regs. */ | |
9602b6a1 AK |
10601 | sav_ofs = 2 * UNITS_PER_LONG; |
10602 | sav_scale = UNITS_PER_LONG; | |
10603 | size = UNITS_PER_LONG; | |
29a79fcf | 10604 | max_reg = GP_ARG_NUM_REG - n_reg; |
085261c8 AK |
10605 | left_align_p = false; |
10606 | } | |
10607 | else if (s390_function_arg_vector (TYPE_MODE (type), type)) | |
10608 | { | |
10609 | if (TARGET_DEBUG_ARG) | |
10610 | { | |
10611 | fprintf (stderr, "va_arg: vector type"); | |
10612 | debug_tree (type); | |
10613 | } | |
10614 | ||
10615 | indirect_p = 0; | |
10616 | reg = NULL_TREE; | |
10617 | n_reg = 0; | |
10618 | sav_ofs = 0; | |
10619 | sav_scale = 8; | |
10620 | max_reg = 0; | |
10621 | left_align_p = true; | |
9db1d521 | 10622 | } |
82b1c974 | 10623 | else if (s390_function_arg_float (TYPE_MODE (type), type)) |
9db1d521 HP |
10624 | { |
10625 | if (TARGET_DEBUG_ARG) | |
10626 | { | |
10627 | fprintf (stderr, "va_arg: float type"); | |
10628 | debug_tree (type); | |
10629 | } | |
10630 | ||
10631 | /* FP args go in FP registers, if present. */ | |
10632 | indirect_p = 0; | |
10633 | reg = fpr; | |
10634 | n_reg = 1; | |
9602b6a1 | 10635 | sav_ofs = 16 * UNITS_PER_LONG; |
9db1d521 | 10636 | sav_scale = 8; |
29a79fcf | 10637 | max_reg = FP_ARG_NUM_REG - n_reg; |
085261c8 | 10638 | left_align_p = false; |
9db1d521 HP |
10639 | } |
10640 | else | |
10641 | { | |
10642 | if (TARGET_DEBUG_ARG) | |
10643 | { | |
10644 | fprintf (stderr, "va_arg: other type"); | |
10645 | debug_tree (type); | |
10646 | } | |
10647 | ||
10648 | /* Otherwise into GP registers. */ | |
10649 | indirect_p = 0; | |
10650 | reg = gpr; | |
9602b6a1 | 10651 | n_reg = (size + UNITS_PER_LONG - 1) / UNITS_PER_LONG; |
ea506297 | 10652 | |
b3d31392 AK |
10653 | /* kernel stack layout on 31 bit: It is assumed here that no padding |
10654 | will be added by s390_frame_info because for va_args always an even | |
10655 | number of gprs has to be saved r15-r2 = 14 regs. */ | |
9602b6a1 | 10656 | sav_ofs = 2 * UNITS_PER_LONG; |
c7453384 | 10657 | |
9602b6a1 AK |
10658 | if (size < UNITS_PER_LONG) |
10659 | sav_ofs += UNITS_PER_LONG - size; | |
9db1d521 | 10660 | |
9602b6a1 | 10661 | sav_scale = UNITS_PER_LONG; |
29a79fcf | 10662 | max_reg = GP_ARG_NUM_REG - n_reg; |
085261c8 | 10663 | left_align_p = false; |
9db1d521 HP |
10664 | } |
10665 | ||
10666 | /* Pull the value out of the saved registers ... */ | |
10667 | ||
085261c8 AK |
10668 | if (reg != NULL_TREE) |
10669 | { | |
10670 | /* | |
10671 | if (reg > ((typeof (reg))max_reg)) | |
10672 | goto lab_false; | |
9db1d521 | 10673 | |
085261c8 | 10674 | addr = sav + sav_ofs + reg * save_scale; |
9db1d521 | 10675 | |
085261c8 | 10676 | goto lab_over; |
9db1d521 | 10677 | |
085261c8 AK |
10678 | lab_false: |
10679 | */ | |
10680 | ||
10681 | lab_false = create_artificial_label (UNKNOWN_LOCATION); | |
10682 | lab_over = create_artificial_label (UNKNOWN_LOCATION); | |
10683 | ||
10684 | t = fold_convert (TREE_TYPE (reg), size_int (max_reg)); | |
10685 | t = build2 (GT_EXPR, boolean_type_node, reg, t); | |
10686 | u = build1 (GOTO_EXPR, void_type_node, lab_false); | |
10687 | t = build3 (COND_EXPR, void_type_node, t, u, NULL_TREE); | |
10688 | gimplify_and_add (t, pre_p); | |
9db1d521 | 10689 | |
085261c8 AK |
10690 | t = fold_build_pointer_plus_hwi (sav, sav_ofs); |
10691 | u = build2 (MULT_EXPR, TREE_TYPE (reg), reg, | |
10692 | fold_convert (TREE_TYPE (reg), size_int (sav_scale))); | |
10693 | t = fold_build_pointer_plus (t, u); | |
9db1d521 | 10694 | |
085261c8 | 10695 | gimplify_assign (addr, t, pre_p); |
9db1d521 | 10696 | |
085261c8 AK |
10697 | gimple_seq_add_stmt (pre_p, gimple_build_goto (lab_over)); |
10698 | ||
10699 | gimple_seq_add_stmt (pre_p, gimple_build_label (lab_false)); | |
10700 | } | |
9db1d521 HP |
10701 | |
10702 | /* ... Otherwise out of the overflow area. */ | |
10703 | ||
ab96de7e | 10704 | t = ovf; |
085261c8 | 10705 | if (size < UNITS_PER_LONG && !left_align_p) |
5d49b6a7 | 10706 | t = fold_build_pointer_plus_hwi (t, UNITS_PER_LONG - size); |
ab96de7e AS |
10707 | |
10708 | gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue); | |
10709 | ||
726a989a | 10710 | gimplify_assign (addr, t, pre_p); |
ab96de7e | 10711 | |
085261c8 AK |
10712 | if (size < UNITS_PER_LONG && left_align_p) |
10713 | t = fold_build_pointer_plus_hwi (t, UNITS_PER_LONG); | |
10714 | else | |
10715 | t = fold_build_pointer_plus_hwi (t, size); | |
10716 | ||
726a989a | 10717 | gimplify_assign (ovf, t, pre_p); |
ab96de7e | 10718 | |
085261c8 AK |
10719 | if (reg != NULL_TREE) |
10720 | gimple_seq_add_stmt (pre_p, gimple_build_label (lab_over)); | |
ab96de7e AS |
10721 | |
10722 | ||
10723 | /* Increment register save count. */ | |
10724 | ||
085261c8 AK |
10725 | if (n_reg > 0) |
10726 | { | |
10727 | u = build2 (PREINCREMENT_EXPR, TREE_TYPE (reg), reg, | |
10728 | fold_convert (TREE_TYPE (reg), size_int (n_reg))); | |
10729 | gimplify_and_add (u, pre_p); | |
10730 | } | |
ab96de7e AS |
10731 | |
10732 | if (indirect_p) | |
10733 | { | |
5b21f0f3 RG |
10734 | t = build_pointer_type_for_mode (build_pointer_type (type), |
10735 | ptr_mode, true); | |
ab96de7e AS |
10736 | addr = fold_convert (t, addr); |
10737 | addr = build_va_arg_indirect_ref (addr); | |
10738 | } | |
10739 | else | |
10740 | { | |
5b21f0f3 | 10741 | t = build_pointer_type_for_mode (type, ptr_mode, true); |
ab96de7e AS |
10742 | addr = fold_convert (t, addr); |
10743 | } | |
10744 | ||
10745 | return build_va_arg_indirect_ref (addr); | |
10746 | } | |
10747 | ||
5a3fe9b6 AK |
10748 | /* Emit rtl for the tbegin or tbegin_retry (RETRY != NULL_RTX) |
10749 | expanders. | |
10750 | DEST - Register location where CC will be stored. | |
10751 | TDB - Pointer to a 256 byte area where to store the transaction. | |
10752 | diagnostic block. NULL if TDB is not needed. | |
10753 | RETRY - Retry count value. If non-NULL a retry loop for CC2 | |
10754 | is emitted | |
10755 | CLOBBER_FPRS_P - If true clobbers for all FPRs are emitted as part | |
10756 | of the tbegin instruction pattern. */ | |
10757 | ||
10758 | void | |
10759 | s390_expand_tbegin (rtx dest, rtx tdb, rtx retry, bool clobber_fprs_p) | |
10760 | { | |
2561451d | 10761 | rtx retry_plus_two = gen_reg_rtx (SImode); |
5a3fe9b6 | 10762 | rtx retry_reg = gen_reg_rtx (SImode); |
19f8b229 | 10763 | rtx_code_label *retry_label = NULL; |
5a3fe9b6 AK |
10764 | |
10765 | if (retry != NULL_RTX) | |
10766 | { | |
10767 | emit_move_insn (retry_reg, retry); | |
2561451d AK |
10768 | emit_insn (gen_addsi3 (retry_plus_two, retry_reg, const2_rtx)); |
10769 | emit_insn (gen_addsi3 (retry_reg, retry_reg, const1_rtx)); | |
5a3fe9b6 AK |
10770 | retry_label = gen_label_rtx (); |
10771 | emit_label (retry_label); | |
10772 | } | |
10773 | ||
10774 | if (clobber_fprs_p) | |
2561451d | 10775 | emit_insn (gen_tbegin_1 (gen_rtx_CONST_INT (VOIDmode, TBEGIN_MASK), tdb)); |
5a3fe9b6 | 10776 | else |
2561451d AK |
10777 | emit_insn (gen_tbegin_nofloat_1 (gen_rtx_CONST_INT (VOIDmode, TBEGIN_MASK), |
10778 | tdb)); | |
5a3fe9b6 | 10779 | |
2561451d AK |
10780 | emit_move_insn (dest, gen_rtx_UNSPEC (SImode, |
10781 | gen_rtvec (1, gen_rtx_REG (CCRAWmode, | |
10782 | CC_REGNUM)), | |
10783 | UNSPEC_CC_TO_INT)); | |
5a3fe9b6 AK |
10784 | if (retry != NULL_RTX) |
10785 | { | |
86464cbd AK |
10786 | const int CC0 = 1 << 3; |
10787 | const int CC1 = 1 << 2; | |
10788 | const int CC3 = 1 << 0; | |
10789 | rtx jump; | |
5a3fe9b6 | 10790 | rtx count = gen_reg_rtx (SImode); |
775c43d3 | 10791 | rtx_code_label *leave_label = gen_label_rtx (); |
86464cbd AK |
10792 | |
10793 | /* Exit for success and permanent failures. */ | |
5a3fe9b6 AK |
10794 | jump = s390_emit_jump (leave_label, |
10795 | gen_rtx_EQ (VOIDmode, | |
10796 | gen_rtx_REG (CCRAWmode, CC_REGNUM), | |
86464cbd AK |
10797 | gen_rtx_CONST_INT (VOIDmode, CC0 | CC1 | CC3))); |
10798 | LABEL_NUSES (leave_label) = 1; | |
5a3fe9b6 AK |
10799 | |
10800 | /* CC2 - transient failure. Perform retry with ppa. */ | |
2561451d | 10801 | emit_move_insn (count, retry_plus_two); |
5a3fe9b6 AK |
10802 | emit_insn (gen_subsi3 (count, count, retry_reg)); |
10803 | emit_insn (gen_tx_assist (count)); | |
10804 | jump = emit_jump_insn (gen_doloop_si64 (retry_label, | |
10805 | retry_reg, | |
10806 | retry_reg)); | |
10807 | JUMP_LABEL (jump) = retry_label; | |
10808 | LABEL_NUSES (retry_label) = 1; | |
86464cbd | 10809 | emit_label (leave_label); |
5a3fe9b6 | 10810 | } |
5a3fe9b6 AK |
10811 | } |
10812 | ||
10813 | /* Builtins. */ | |
10814 | ||
10815 | enum s390_builtin | |
10816 | { | |
10817 | S390_BUILTIN_TBEGIN, | |
10818 | S390_BUILTIN_TBEGIN_NOFLOAT, | |
10819 | S390_BUILTIN_TBEGIN_RETRY, | |
10820 | S390_BUILTIN_TBEGIN_RETRY_NOFLOAT, | |
10821 | S390_BUILTIN_TBEGINC, | |
10822 | S390_BUILTIN_TEND, | |
10823 | S390_BUILTIN_TABORT, | |
10824 | S390_BUILTIN_NON_TX_STORE, | |
10825 | S390_BUILTIN_TX_NESTING_DEPTH, | |
10826 | S390_BUILTIN_TX_ASSIST, | |
10827 | ||
004f64e1 AK |
10828 | S390_BUILTIN_S390_SFPC, |
10829 | S390_BUILTIN_S390_EFPC, | |
10830 | ||
9b80b7bc | 10831 | S390_BUILTIN_MAX |
5a3fe9b6 AK |
10832 | }; |
10833 | ||
9b80b7bc AK |
10834 | tree s390_builtin_decls[S390_BUILTIN_MAX]; |
10835 | ||
10836 | static enum insn_code const code_for_builtin[S390_BUILTIN_MAX] = { | |
5a3fe9b6 AK |
10837 | CODE_FOR_tbegin, |
10838 | CODE_FOR_tbegin_nofloat, | |
10839 | CODE_FOR_tbegin_retry, | |
10840 | CODE_FOR_tbegin_retry_nofloat, | |
10841 | CODE_FOR_tbeginc, | |
10842 | CODE_FOR_tend, | |
10843 | CODE_FOR_tabort, | |
10844 | CODE_FOR_ntstg, | |
10845 | CODE_FOR_etnd, | |
004f64e1 AK |
10846 | CODE_FOR_tx_assist, |
10847 | ||
10848 | CODE_FOR_s390_sfpc, | |
10849 | CODE_FOR_s390_efpc | |
5a3fe9b6 AK |
10850 | }; |
10851 | ||
10852 | static void | |
10853 | s390_init_builtins (void) | |
10854 | { | |
10855 | tree ftype, uint64_type; | |
2561451d AK |
10856 | tree returns_twice_attr = tree_cons (get_identifier ("returns_twice"), |
10857 | NULL, NULL); | |
10858 | tree noreturn_attr = tree_cons (get_identifier ("noreturn"), NULL, NULL); | |
5a3fe9b6 AK |
10859 | |
10860 | /* void foo (void) */ | |
10861 | ftype = build_function_type_list (void_type_node, NULL_TREE); | |
9b80b7bc AK |
10862 | s390_builtin_decls[S390_BUILTIN_TBEGINC] = |
10863 | add_builtin_function ("__builtin_tbeginc", ftype, S390_BUILTIN_TBEGINC, | |
10864 | BUILT_IN_MD, NULL, NULL_TREE); | |
5a3fe9b6 AK |
10865 | |
10866 | /* void foo (int) */ | |
10867 | ftype = build_function_type_list (void_type_node, integer_type_node, | |
10868 | NULL_TREE); | |
9b80b7bc AK |
10869 | s390_builtin_decls[S390_BUILTIN_TABORT] = |
10870 | add_builtin_function ("__builtin_tabort", ftype, | |
10871 | S390_BUILTIN_TABORT, BUILT_IN_MD, NULL, | |
10872 | noreturn_attr); | |
10873 | s390_builtin_decls[S390_BUILTIN_TX_ASSIST] = | |
10874 | add_builtin_function ("__builtin_tx_assist", ftype, | |
10875 | S390_BUILTIN_TX_ASSIST, BUILT_IN_MD, NULL, NULL_TREE); | |
10876 | ||
004f64e1 AK |
10877 | /* void foo (unsigned) */ |
10878 | ftype = build_function_type_list (void_type_node, unsigned_type_node, | |
10879 | NULL_TREE); | |
10880 | s390_builtin_decls[S390_BUILTIN_S390_SFPC] = | |
10881 | add_builtin_function ("__builtin_s390_sfpc", ftype, | |
10882 | S390_BUILTIN_S390_SFPC, BUILT_IN_MD, NULL, NULL_TREE); | |
5a3fe9b6 AK |
10883 | |
10884 | /* int foo (void *) */ | |
9b80b7bc AK |
10885 | ftype = build_function_type_list (integer_type_node, ptr_type_node, |
10886 | NULL_TREE); | |
10887 | s390_builtin_decls[S390_BUILTIN_TBEGIN] = | |
10888 | add_builtin_function ("__builtin_tbegin", ftype, S390_BUILTIN_TBEGIN, | |
10889 | BUILT_IN_MD, NULL, returns_twice_attr); | |
10890 | s390_builtin_decls[S390_BUILTIN_TBEGIN_NOFLOAT] = | |
10891 | add_builtin_function ("__builtin_tbegin_nofloat", ftype, | |
10892 | S390_BUILTIN_TBEGIN_NOFLOAT, | |
10893 | BUILT_IN_MD, NULL, returns_twice_attr); | |
5a3fe9b6 AK |
10894 | |
10895 | /* int foo (void *, int) */ | |
10896 | ftype = build_function_type_list (integer_type_node, ptr_type_node, | |
10897 | integer_type_node, NULL_TREE); | |
9b80b7bc AK |
10898 | s390_builtin_decls[S390_BUILTIN_TBEGIN_RETRY] = |
10899 | add_builtin_function ("__builtin_tbegin_retry", ftype, | |
10900 | S390_BUILTIN_TBEGIN_RETRY, | |
10901 | BUILT_IN_MD, | |
10902 | NULL, returns_twice_attr); | |
10903 | s390_builtin_decls[S390_BUILTIN_TBEGIN_RETRY_NOFLOAT] = | |
10904 | add_builtin_function ("__builtin_tbegin_retry_nofloat", ftype, | |
10905 | S390_BUILTIN_TBEGIN_RETRY_NOFLOAT, | |
10906 | BUILT_IN_MD, | |
10907 | NULL, returns_twice_attr); | |
5a3fe9b6 AK |
10908 | |
10909 | /* int foo (void) */ | |
10910 | ftype = build_function_type_list (integer_type_node, NULL_TREE); | |
9b80b7bc AK |
10911 | s390_builtin_decls[S390_BUILTIN_TX_NESTING_DEPTH] = |
10912 | add_builtin_function ("__builtin_tx_nesting_depth", ftype, | |
10913 | S390_BUILTIN_TX_NESTING_DEPTH, | |
10914 | BUILT_IN_MD, NULL, NULL_TREE); | |
10915 | s390_builtin_decls[S390_BUILTIN_TEND] = | |
10916 | add_builtin_function ("__builtin_tend", ftype, | |
10917 | S390_BUILTIN_TEND, BUILT_IN_MD, NULL, NULL_TREE); | |
10918 | ||
004f64e1 AK |
10919 | /* unsigned foo (void) */ |
10920 | ftype = build_function_type_list (unsigned_type_node, NULL_TREE); | |
10921 | s390_builtin_decls[S390_BUILTIN_S390_EFPC] = | |
10922 | add_builtin_function ("__builtin_s390_efpc", ftype, | |
10923 | S390_BUILTIN_S390_EFPC, BUILT_IN_MD, NULL, NULL_TREE); | |
5a3fe9b6 AK |
10924 | |
10925 | /* void foo (uint64_t *, uint64_t) */ | |
10926 | if (TARGET_64BIT) | |
10927 | uint64_type = long_unsigned_type_node; | |
10928 | else | |
10929 | uint64_type = long_long_unsigned_type_node; | |
10930 | ||
9b80b7bc | 10931 | ftype = build_function_type_list (void_type_node, |
5a3fe9b6 AK |
10932 | build_pointer_type (uint64_type), |
10933 | uint64_type, NULL_TREE); | |
9b80b7bc AK |
10934 | s390_builtin_decls[S390_BUILTIN_NON_TX_STORE] = |
10935 | add_builtin_function ("__builtin_non_tx_store", ftype, | |
10936 | S390_BUILTIN_NON_TX_STORE, | |
10937 | BUILT_IN_MD, NULL, NULL_TREE); | |
5a3fe9b6 AK |
10938 | } |
10939 | ||
10940 | /* Expand an expression EXP that calls a built-in function, | |
10941 | with result going to TARGET if that's convenient | |
10942 | (and in mode MODE if that's convenient). | |
10943 | SUBTARGET may be used as the target for computing one of EXP's operands. | |
10944 | IGNORE is nonzero if the value is to be ignored. */ | |
10945 | ||
10946 | static rtx | |
10947 | s390_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED, | |
ef4bddc2 | 10948 | machine_mode mode ATTRIBUTE_UNUSED, |
5a3fe9b6 AK |
10949 | int ignore ATTRIBUTE_UNUSED) |
10950 | { | |
10951 | #define MAX_ARGS 2 | |
10952 | ||
10953 | tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0); | |
10954 | unsigned int fcode = DECL_FUNCTION_CODE (fndecl); | |
10955 | enum insn_code icode; | |
10956 | rtx op[MAX_ARGS], pat; | |
10957 | int arity; | |
10958 | bool nonvoid; | |
10959 | tree arg; | |
10960 | call_expr_arg_iterator iter; | |
10961 | ||
9b80b7bc | 10962 | if (fcode >= S390_BUILTIN_MAX) |
5a3fe9b6 AK |
10963 | internal_error ("bad builtin fcode"); |
10964 | icode = code_for_builtin[fcode]; | |
10965 | if (icode == 0) | |
10966 | internal_error ("bad builtin fcode"); | |
10967 | ||
4b9f07eb | 10968 | if (!TARGET_HTM && fcode <= S390_BUILTIN_TX_ASSIST) |
167f68ed | 10969 | error ("Transactional execution builtins not enabled (-mhtm)\n"); |
5a3fe9b6 AK |
10970 | |
10971 | /* Set a flag in the machine specific cfun part in order to support | |
10972 | saving/restoring of FPRs. */ | |
10973 | if (fcode == S390_BUILTIN_TBEGIN || fcode == S390_BUILTIN_TBEGIN_RETRY) | |
10974 | cfun->machine->tbegin_p = true; | |
10975 | ||
10976 | nonvoid = TREE_TYPE (TREE_TYPE (fndecl)) != void_type_node; | |
10977 | ||
10978 | arity = 0; | |
10979 | FOR_EACH_CALL_EXPR_ARG (arg, iter, exp) | |
10980 | { | |
10981 | const struct insn_operand_data *insn_op; | |
10982 | ||
10983 | if (arg == error_mark_node) | |
10984 | return NULL_RTX; | |
10985 | if (arity >= MAX_ARGS) | |
10986 | return NULL_RTX; | |
10987 | ||
10988 | insn_op = &insn_data[icode].operand[arity + nonvoid]; | |
10989 | ||
10990 | op[arity] = expand_expr (arg, NULL_RTX, insn_op->mode, EXPAND_NORMAL); | |
10991 | ||
10992 | if (!(*insn_op->predicate) (op[arity], insn_op->mode)) | |
10993 | { | |
10994 | if (insn_op->predicate == memory_operand) | |
10995 | { | |
10996 | /* Don't move a NULL pointer into a register. Otherwise | |
10997 | we have to rely on combine being able to move it back | |
10998 | in order to get an immediate 0 in the instruction. */ | |
10999 | if (op[arity] != const0_rtx) | |
11000 | op[arity] = copy_to_mode_reg (Pmode, op[arity]); | |
11001 | op[arity] = gen_rtx_MEM (insn_op->mode, op[arity]); | |
11002 | } | |
11003 | else | |
11004 | op[arity] = copy_to_mode_reg (insn_op->mode, op[arity]); | |
11005 | } | |
11006 | ||
11007 | arity++; | |
11008 | } | |
11009 | ||
11010 | if (nonvoid) | |
11011 | { | |
ef4bddc2 | 11012 | machine_mode tmode = insn_data[icode].operand[0].mode; |
5a3fe9b6 AK |
11013 | if (!target |
11014 | || GET_MODE (target) != tmode | |
11015 | || !(*insn_data[icode].operand[0].predicate) (target, tmode)) | |
11016 | target = gen_reg_rtx (tmode); | |
11017 | } | |
11018 | ||
11019 | switch (arity) | |
11020 | { | |
11021 | case 0: | |
11022 | pat = GEN_FCN (icode) (target); | |
11023 | break; | |
11024 | case 1: | |
11025 | if (nonvoid) | |
11026 | pat = GEN_FCN (icode) (target, op[0]); | |
11027 | else | |
11028 | pat = GEN_FCN (icode) (op[0]); | |
11029 | break; | |
11030 | case 2: | |
11031 | if (nonvoid) | |
11032 | pat = GEN_FCN (icode) (target, op[0], op[1]); | |
11033 | else | |
11034 | pat = GEN_FCN (icode) (op[0], op[1]); | |
11035 | break; | |
11036 | default: | |
11037 | gcc_unreachable (); | |
11038 | } | |
11039 | if (!pat) | |
11040 | return NULL_RTX; | |
11041 | emit_insn (pat); | |
11042 | ||
11043 | if (nonvoid) | |
11044 | return target; | |
11045 | else | |
11046 | return const0_rtx; | |
11047 | } | |
11048 | ||
9b80b7bc AK |
11049 | /* Return the decl for the target specific builtin with the function |
11050 | code FCODE. */ | |
11051 | ||
11052 | static tree | |
11053 | s390_builtin_decl (unsigned fcode, bool initialized_p ATTRIBUTE_UNUSED) | |
11054 | { | |
11055 | if (fcode >= S390_BUILTIN_MAX) | |
11056 | return error_mark_node; | |
11057 | ||
11058 | return s390_builtin_decls[fcode]; | |
11059 | } | |
11060 | ||
d56a43a0 AK |
11061 | /* We call mcount before the function prologue. So a profiled leaf |
11062 | function should stay a leaf function. */ | |
11063 | ||
11064 | static bool | |
11065 | s390_keep_leaf_when_profiled () | |
11066 | { | |
11067 | return true; | |
11068 | } | |
5a3fe9b6 | 11069 | |
ab96de7e AS |
11070 | /* Output assembly code for the trampoline template to |
11071 | stdio stream FILE. | |
11072 | ||
11073 | On S/390, we use gpr 1 internally in the trampoline code; | |
11074 | gpr 0 is used to hold the static chain. */ | |
11075 | ||
b81ecf6f RH |
11076 | static void |
11077 | s390_asm_trampoline_template (FILE *file) | |
ab96de7e AS |
11078 | { |
11079 | rtx op[2]; | |
11080 | op[0] = gen_rtx_REG (Pmode, 0); | |
11081 | op[1] = gen_rtx_REG (Pmode, 1); | |
11082 | ||
11083 | if (TARGET_64BIT) | |
11084 | { | |
cab78b15 AK |
11085 | output_asm_insn ("basr\t%1,0", op); /* 2 byte */ |
11086 | output_asm_insn ("lmg\t%0,%1,14(%1)", op); /* 6 byte */ | |
11087 | output_asm_insn ("br\t%1", op); /* 2 byte */ | |
ab96de7e AS |
11088 | ASM_OUTPUT_SKIP (file, (HOST_WIDE_INT)(TRAMPOLINE_SIZE - 10)); |
11089 | } | |
11090 | else | |
11091 | { | |
cab78b15 AK |
11092 | output_asm_insn ("basr\t%1,0", op); /* 2 byte */ |
11093 | output_asm_insn ("lm\t%0,%1,6(%1)", op); /* 4 byte */ | |
11094 | output_asm_insn ("br\t%1", op); /* 2 byte */ | |
ab96de7e AS |
11095 | ASM_OUTPUT_SKIP (file, (HOST_WIDE_INT)(TRAMPOLINE_SIZE - 8)); |
11096 | } | |
11097 | } | |
11098 | ||
11099 | /* Emit RTL insns to initialize the variable parts of a trampoline. | |
11100 | FNADDR is an RTX for the address of the function's pure code. | |
11101 | CXT is an RTX for the static chain value for the function. */ | |
11102 | ||
b81ecf6f RH |
11103 | static void |
11104 | s390_trampoline_init (rtx m_tramp, tree fndecl, rtx cxt) | |
ab96de7e | 11105 | { |
b81ecf6f RH |
11106 | rtx fnaddr = XEXP (DECL_RTL (fndecl), 0); |
11107 | rtx mem; | |
3a892e44 | 11108 | |
b81ecf6f | 11109 | emit_block_move (m_tramp, assemble_trampoline_template (), |
cab78b15 | 11110 | GEN_INT (2 * UNITS_PER_LONG), BLOCK_OP_NORMAL); |
b81ecf6f | 11111 | |
cab78b15 | 11112 | mem = adjust_address (m_tramp, Pmode, 2 * UNITS_PER_LONG); |
b81ecf6f | 11113 | emit_move_insn (mem, cxt); |
cab78b15 | 11114 | mem = adjust_address (m_tramp, Pmode, 3 * UNITS_PER_LONG); |
b81ecf6f | 11115 | emit_move_insn (mem, fnaddr); |
ab96de7e AS |
11116 | } |
11117 | ||
ab96de7e AS |
11118 | /* Output assembler code to FILE to increment profiler label # LABELNO |
11119 | for profiling a function entry. */ | |
11120 | ||
11121 | void | |
11122 | s390_function_profiler (FILE *file, int labelno) | |
11123 | { | |
11124 | rtx op[7]; | |
11125 | ||
11126 | char label[128]; | |
11127 | ASM_GENERATE_INTERNAL_LABEL (label, "LP", labelno); | |
11128 | ||
11129 | fprintf (file, "# function profiler \n"); | |
11130 | ||
11131 | op[0] = gen_rtx_REG (Pmode, RETURN_REGNUM); | |
11132 | op[1] = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM); | |
0a81f074 | 11133 | op[1] = gen_rtx_MEM (Pmode, plus_constant (Pmode, op[1], UNITS_PER_LONG)); |
ab96de7e AS |
11134 | |
11135 | op[2] = gen_rtx_REG (Pmode, 1); | |
11136 | op[3] = gen_rtx_SYMBOL_REF (Pmode, label); | |
11137 | SYMBOL_REF_FLAGS (op[3]) = SYMBOL_FLAG_LOCAL; | |
11138 | ||
11139 | op[4] = gen_rtx_SYMBOL_REF (Pmode, "_mcount"); | |
11140 | if (flag_pic) | |
11141 | { | |
11142 | op[4] = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op[4]), UNSPEC_PLT); | |
11143 | op[4] = gen_rtx_CONST (Pmode, op[4]); | |
11144 | } | |
11145 | ||
11146 | if (TARGET_64BIT) | |
11147 | { | |
11148 | output_asm_insn ("stg\t%0,%1", op); | |
11149 | output_asm_insn ("larl\t%2,%3", op); | |
11150 | output_asm_insn ("brasl\t%0,%4", op); | |
11151 | output_asm_insn ("lg\t%0,%1", op); | |
11152 | } | |
11153 | else if (!flag_pic) | |
11154 | { | |
11155 | op[6] = gen_label_rtx (); | |
11156 | ||
11157 | output_asm_insn ("st\t%0,%1", op); | |
11158 | output_asm_insn ("bras\t%2,%l6", op); | |
11159 | output_asm_insn (".long\t%4", op); | |
11160 | output_asm_insn (".long\t%3", op); | |
11161 | targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[6])); | |
11162 | output_asm_insn ("l\t%0,0(%2)", op); | |
11163 | output_asm_insn ("l\t%2,4(%2)", op); | |
11164 | output_asm_insn ("basr\t%0,%0", op); | |
11165 | output_asm_insn ("l\t%0,%1", op); | |
11166 | } | |
11167 | else | |
11168 | { | |
11169 | op[5] = gen_label_rtx (); | |
11170 | op[6] = gen_label_rtx (); | |
11171 | ||
11172 | output_asm_insn ("st\t%0,%1", op); | |
11173 | output_asm_insn ("bras\t%2,%l6", op); | |
11174 | targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[5])); | |
11175 | output_asm_insn (".long\t%4-%l5", op); | |
11176 | output_asm_insn (".long\t%3-%l5", op); | |
11177 | targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[6])); | |
11178 | output_asm_insn ("lr\t%0,%2", op); | |
11179 | output_asm_insn ("a\t%0,0(%2)", op); | |
11180 | output_asm_insn ("a\t%2,4(%2)", op); | |
11181 | output_asm_insn ("basr\t%0,%0", op); | |
11182 | output_asm_insn ("l\t%0,%1", op); | |
11183 | } | |
11184 | } | |
11185 | ||
11186 | /* Encode symbol attributes (local vs. global, tls model) of a SYMBOL_REF | |
11187 | into its SYMBOL_REF_FLAGS. */ | |
11188 | ||
11189 | static void | |
11190 | s390_encode_section_info (tree decl, rtx rtl, int first) | |
11191 | { | |
11192 | default_encode_section_info (decl, rtl, first); | |
11193 | ||
963fc8d0 AK |
11194 | if (TREE_CODE (decl) == VAR_DECL) |
11195 | { | |
11196 | /* If a variable has a forced alignment to < 2 bytes, mark it | |
11197 | with SYMBOL_FLAG_ALIGN1 to prevent it from being used as LARL | |
11198 | operand. */ | |
11199 | if (DECL_USER_ALIGN (decl) && DECL_ALIGN (decl) < 16) | |
11200 | SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_ALIGN1; | |
11201 | if (!DECL_SIZE (decl) | |
11202 | || !DECL_ALIGN (decl) | |
9541ffee | 11203 | || !tree_fits_shwi_p (DECL_SIZE (decl)) |
963fc8d0 | 11204 | || (DECL_ALIGN (decl) <= 64 |
9439e9a1 | 11205 | && DECL_ALIGN (decl) != tree_to_shwi (DECL_SIZE (decl)))) |
963fc8d0 AK |
11206 | SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_NOT_NATURALLY_ALIGNED; |
11207 | } | |
11208 | ||
11209 | /* Literal pool references don't have a decl so they are handled | |
11210 | differently here. We rely on the information in the MEM_ALIGN | |
11211 | entry to decide upon natural alignment. */ | |
11212 | if (MEM_P (rtl) | |
11213 | && GET_CODE (XEXP (rtl, 0)) == SYMBOL_REF | |
11214 | && TREE_CONSTANT_POOL_ADDRESS_P (XEXP (rtl, 0)) | |
11215 | && (MEM_ALIGN (rtl) == 0 | |
35fcb6ba | 11216 | || GET_MODE_BITSIZE (GET_MODE (rtl)) == 0 |
963fc8d0 AK |
11217 | || MEM_ALIGN (rtl) < GET_MODE_BITSIZE (GET_MODE (rtl)))) |
11218 | SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_NOT_NATURALLY_ALIGNED; | |
ab96de7e AS |
11219 | } |
11220 | ||
11221 | /* Output thunk to FILE that implements a C++ virtual function call (with | |
11222 | multiple inheritance) to FUNCTION. The thunk adjusts the this pointer | |
11223 | by DELTA, and unless VCALL_OFFSET is zero, applies an additional adjustment | |
11224 | stored at VCALL_OFFSET in the vtable whose address is located at offset 0 | |
11225 | relative to the resulting this pointer. */ | |
11226 | ||
11227 | static void | |
11228 | s390_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED, | |
11229 | HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset, | |
11230 | tree function) | |
11231 | { | |
11232 | rtx op[10]; | |
11233 | int nonlocal = 0; | |
11234 | ||
81ef7e24 JJ |
11235 | /* Make sure unwind info is emitted for the thunk if needed. */ |
11236 | final_start_function (emit_barrier (), file, 1); | |
11237 | ||
ab96de7e AS |
11238 | /* Operand 0 is the target function. */ |
11239 | op[0] = XEXP (DECL_RTL (function), 0); | |
11240 | if (flag_pic && !SYMBOL_REF_LOCAL_P (op[0])) | |
11241 | { | |
11242 | nonlocal = 1; | |
11243 | op[0] = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op[0]), | |
11244 | TARGET_64BIT ? UNSPEC_PLT : UNSPEC_GOT); | |
11245 | op[0] = gen_rtx_CONST (Pmode, op[0]); | |
11246 | } | |
11247 | ||
11248 | /* Operand 1 is the 'this' pointer. */ | |
11249 | if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function)) | |
11250 | op[1] = gen_rtx_REG (Pmode, 3); | |
11251 | else | |
11252 | op[1] = gen_rtx_REG (Pmode, 2); | |
11253 | ||
11254 | /* Operand 2 is the delta. */ | |
11255 | op[2] = GEN_INT (delta); | |
11256 | ||
11257 | /* Operand 3 is the vcall_offset. */ | |
11258 | op[3] = GEN_INT (vcall_offset); | |
11259 | ||
11260 | /* Operand 4 is the temporary register. */ | |
11261 | op[4] = gen_rtx_REG (Pmode, 1); | |
11262 | ||
11263 | /* Operands 5 to 8 can be used as labels. */ | |
11264 | op[5] = NULL_RTX; | |
11265 | op[6] = NULL_RTX; | |
11266 | op[7] = NULL_RTX; | |
11267 | op[8] = NULL_RTX; | |
11268 | ||
11269 | /* Operand 9 can be used for temporary register. */ | |
11270 | op[9] = NULL_RTX; | |
11271 | ||
11272 | /* Generate code. */ | |
11273 | if (TARGET_64BIT) | |
11274 | { | |
11275 | /* Setup literal pool pointer if required. */ | |
11276 | if ((!DISP_IN_RANGE (delta) | |
ec24698e UW |
11277 | && !CONST_OK_FOR_K (delta) |
11278 | && !CONST_OK_FOR_Os (delta)) | |
ab96de7e | 11279 | || (!DISP_IN_RANGE (vcall_offset) |
ec24698e UW |
11280 | && !CONST_OK_FOR_K (vcall_offset) |
11281 | && !CONST_OK_FOR_Os (vcall_offset))) | |
ab96de7e AS |
11282 | { |
11283 | op[5] = gen_label_rtx (); | |
11284 | output_asm_insn ("larl\t%4,%5", op); | |
11285 | } | |
11286 | ||
11287 | /* Add DELTA to this pointer. */ | |
11288 | if (delta) | |
11289 | { | |
b5c67a49 | 11290 | if (CONST_OK_FOR_J (delta)) |
ab96de7e AS |
11291 | output_asm_insn ("la\t%1,%2(%1)", op); |
11292 | else if (DISP_IN_RANGE (delta)) | |
11293 | output_asm_insn ("lay\t%1,%2(%1)", op); | |
b5c67a49 | 11294 | else if (CONST_OK_FOR_K (delta)) |
ab96de7e | 11295 | output_asm_insn ("aghi\t%1,%2", op); |
ec24698e UW |
11296 | else if (CONST_OK_FOR_Os (delta)) |
11297 | output_asm_insn ("agfi\t%1,%2", op); | |
ab96de7e AS |
11298 | else |
11299 | { | |
11300 | op[6] = gen_label_rtx (); | |
11301 | output_asm_insn ("agf\t%1,%6-%5(%4)", op); | |
11302 | } | |
11303 | } | |
11304 | ||
11305 | /* Perform vcall adjustment. */ | |
11306 | if (vcall_offset) | |
11307 | { | |
11308 | if (DISP_IN_RANGE (vcall_offset)) | |
11309 | { | |
11310 | output_asm_insn ("lg\t%4,0(%1)", op); | |
11311 | output_asm_insn ("ag\t%1,%3(%4)", op); | |
11312 | } | |
b5c67a49 | 11313 | else if (CONST_OK_FOR_K (vcall_offset)) |
ab96de7e AS |
11314 | { |
11315 | output_asm_insn ("lghi\t%4,%3", op); | |
11316 | output_asm_insn ("ag\t%4,0(%1)", op); | |
11317 | output_asm_insn ("ag\t%1,0(%4)", op); | |
11318 | } | |
ec24698e UW |
11319 | else if (CONST_OK_FOR_Os (vcall_offset)) |
11320 | { | |
11321 | output_asm_insn ("lgfi\t%4,%3", op); | |
11322 | output_asm_insn ("ag\t%4,0(%1)", op); | |
11323 | output_asm_insn ("ag\t%1,0(%4)", op); | |
11324 | } | |
ab96de7e AS |
11325 | else |
11326 | { | |
11327 | op[7] = gen_label_rtx (); | |
11328 | output_asm_insn ("llgf\t%4,%7-%5(%4)", op); | |
11329 | output_asm_insn ("ag\t%4,0(%1)", op); | |
11330 | output_asm_insn ("ag\t%1,0(%4)", op); | |
11331 | } | |
11332 | } | |
11333 | ||
11334 | /* Jump to target. */ | |
11335 | output_asm_insn ("jg\t%0", op); | |
11336 | ||
11337 | /* Output literal pool if required. */ | |
11338 | if (op[5]) | |
11339 | { | |
11340 | output_asm_insn (".align\t4", op); | |
11341 | targetm.asm_out.internal_label (file, "L", | |
11342 | CODE_LABEL_NUMBER (op[5])); | |
11343 | } | |
11344 | if (op[6]) | |
11345 | { | |
11346 | targetm.asm_out.internal_label (file, "L", | |
11347 | CODE_LABEL_NUMBER (op[6])); | |
11348 | output_asm_insn (".long\t%2", op); | |
11349 | } | |
11350 | if (op[7]) | |
11351 | { | |
11352 | targetm.asm_out.internal_label (file, "L", | |
11353 | CODE_LABEL_NUMBER (op[7])); | |
11354 | output_asm_insn (".long\t%3", op); | |
11355 | } | |
11356 | } | |
11357 | else | |
11358 | { | |
11359 | /* Setup base pointer if required. */ | |
11360 | if (!vcall_offset | |
11361 | || (!DISP_IN_RANGE (delta) | |
ec24698e UW |
11362 | && !CONST_OK_FOR_K (delta) |
11363 | && !CONST_OK_FOR_Os (delta)) | |
ab96de7e | 11364 | || (!DISP_IN_RANGE (delta) |
ec24698e UW |
11365 | && !CONST_OK_FOR_K (vcall_offset) |
11366 | && !CONST_OK_FOR_Os (vcall_offset))) | |
ab96de7e AS |
11367 | { |
11368 | op[5] = gen_label_rtx (); | |
11369 | output_asm_insn ("basr\t%4,0", op); | |
11370 | targetm.asm_out.internal_label (file, "L", | |
11371 | CODE_LABEL_NUMBER (op[5])); | |
11372 | } | |
11373 | ||
11374 | /* Add DELTA to this pointer. */ | |
11375 | if (delta) | |
11376 | { | |
b5c67a49 | 11377 | if (CONST_OK_FOR_J (delta)) |
ab96de7e AS |
11378 | output_asm_insn ("la\t%1,%2(%1)", op); |
11379 | else if (DISP_IN_RANGE (delta)) | |
11380 | output_asm_insn ("lay\t%1,%2(%1)", op); | |
b5c67a49 | 11381 | else if (CONST_OK_FOR_K (delta)) |
ab96de7e | 11382 | output_asm_insn ("ahi\t%1,%2", op); |
ec24698e UW |
11383 | else if (CONST_OK_FOR_Os (delta)) |
11384 | output_asm_insn ("afi\t%1,%2", op); | |
ab96de7e AS |
11385 | else |
11386 | { | |
11387 | op[6] = gen_label_rtx (); | |
11388 | output_asm_insn ("a\t%1,%6-%5(%4)", op); | |
11389 | } | |
11390 | } | |
11391 | ||
11392 | /* Perform vcall adjustment. */ | |
11393 | if (vcall_offset) | |
11394 | { | |
b5c67a49 | 11395 | if (CONST_OK_FOR_J (vcall_offset)) |
ab96de7e | 11396 | { |
c4d50129 | 11397 | output_asm_insn ("l\t%4,0(%1)", op); |
ab96de7e AS |
11398 | output_asm_insn ("a\t%1,%3(%4)", op); |
11399 | } | |
11400 | else if (DISP_IN_RANGE (vcall_offset)) | |
11401 | { | |
c4d50129 | 11402 | output_asm_insn ("l\t%4,0(%1)", op); |
ab96de7e AS |
11403 | output_asm_insn ("ay\t%1,%3(%4)", op); |
11404 | } | |
b5c67a49 | 11405 | else if (CONST_OK_FOR_K (vcall_offset)) |
ab96de7e AS |
11406 | { |
11407 | output_asm_insn ("lhi\t%4,%3", op); | |
11408 | output_asm_insn ("a\t%4,0(%1)", op); | |
11409 | output_asm_insn ("a\t%1,0(%4)", op); | |
11410 | } | |
ec24698e UW |
11411 | else if (CONST_OK_FOR_Os (vcall_offset)) |
11412 | { | |
11413 | output_asm_insn ("iilf\t%4,%3", op); | |
11414 | output_asm_insn ("a\t%4,0(%1)", op); | |
11415 | output_asm_insn ("a\t%1,0(%4)", op); | |
11416 | } | |
ab96de7e AS |
11417 | else |
11418 | { | |
11419 | op[7] = gen_label_rtx (); | |
11420 | output_asm_insn ("l\t%4,%7-%5(%4)", op); | |
11421 | output_asm_insn ("a\t%4,0(%1)", op); | |
11422 | output_asm_insn ("a\t%1,0(%4)", op); | |
11423 | } | |
9db1d521 | 11424 | |
ab96de7e AS |
11425 | /* We had to clobber the base pointer register. |
11426 | Re-setup the base pointer (with a different base). */ | |
11427 | op[5] = gen_label_rtx (); | |
11428 | output_asm_insn ("basr\t%4,0", op); | |
11429 | targetm.asm_out.internal_label (file, "L", | |
11430 | CODE_LABEL_NUMBER (op[5])); | |
11431 | } | |
9db1d521 | 11432 | |
ab96de7e AS |
11433 | /* Jump to target. */ |
11434 | op[8] = gen_label_rtx (); | |
9db1d521 | 11435 | |
ab96de7e AS |
11436 | if (!flag_pic) |
11437 | output_asm_insn ("l\t%4,%8-%5(%4)", op); | |
11438 | else if (!nonlocal) | |
11439 | output_asm_insn ("a\t%4,%8-%5(%4)", op); | |
11440 | /* We cannot call through .plt, since .plt requires %r12 loaded. */ | |
11441 | else if (flag_pic == 1) | |
11442 | { | |
11443 | output_asm_insn ("a\t%4,%8-%5(%4)", op); | |
11444 | output_asm_insn ("l\t%4,%0(%4)", op); | |
11445 | } | |
11446 | else if (flag_pic == 2) | |
11447 | { | |
11448 | op[9] = gen_rtx_REG (Pmode, 0); | |
11449 | output_asm_insn ("l\t%9,%8-4-%5(%4)", op); | |
11450 | output_asm_insn ("a\t%4,%8-%5(%4)", op); | |
11451 | output_asm_insn ("ar\t%4,%9", op); | |
11452 | output_asm_insn ("l\t%4,0(%4)", op); | |
11453 | } | |
9db1d521 | 11454 | |
ab96de7e | 11455 | output_asm_insn ("br\t%4", op); |
9db1d521 | 11456 | |
ab96de7e AS |
11457 | /* Output literal pool. */ |
11458 | output_asm_insn (".align\t4", op); | |
9db1d521 | 11459 | |
ab96de7e AS |
11460 | if (nonlocal && flag_pic == 2) |
11461 | output_asm_insn (".long\t%0", op); | |
11462 | if (nonlocal) | |
11463 | { | |
11464 | op[0] = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_"); | |
11465 | SYMBOL_REF_FLAGS (op[0]) = SYMBOL_FLAG_LOCAL; | |
11466 | } | |
63694b5e | 11467 | |
ab96de7e AS |
11468 | targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[8])); |
11469 | if (!flag_pic) | |
11470 | output_asm_insn (".long\t%0", op); | |
11471 | else | |
11472 | output_asm_insn (".long\t%0-%5", op); | |
9db1d521 | 11473 | |
ab96de7e AS |
11474 | if (op[6]) |
11475 | { | |
11476 | targetm.asm_out.internal_label (file, "L", | |
11477 | CODE_LABEL_NUMBER (op[6])); | |
11478 | output_asm_insn (".long\t%2", op); | |
11479 | } | |
11480 | if (op[7]) | |
11481 | { | |
11482 | targetm.asm_out.internal_label (file, "L", | |
11483 | CODE_LABEL_NUMBER (op[7])); | |
11484 | output_asm_insn (".long\t%3", op); | |
11485 | } | |
9db1d521 | 11486 | } |
81ef7e24 | 11487 | final_end_function (); |
9db1d521 HP |
11488 | } |
11489 | ||
ab96de7e | 11490 | static bool |
ef4bddc2 | 11491 | s390_valid_pointer_mode (machine_mode mode) |
ab96de7e AS |
11492 | { |
11493 | return (mode == SImode || (TARGET_64BIT && mode == DImode)); | |
11494 | } | |
994fe660 | 11495 | |
9a6f71b4 | 11496 | /* Checks whether the given CALL_EXPR would use a caller |
ab96de7e AS |
11497 | saved register. This is used to decide whether sibling call |
11498 | optimization could be performed on the respective function | |
11499 | call. */ | |
fd3cd001 | 11500 | |
ab96de7e | 11501 | static bool |
9a6f71b4 | 11502 | s390_call_saved_register_used (tree call_expr) |
fd3cd001 | 11503 | { |
d5cc9181 JR |
11504 | CUMULATIVE_ARGS cum_v; |
11505 | cumulative_args_t cum; | |
ab96de7e | 11506 | tree parameter; |
ef4bddc2 | 11507 | machine_mode mode; |
ab96de7e AS |
11508 | tree type; |
11509 | rtx parm_rtx; | |
9a6f71b4 | 11510 | int reg, i; |
fd3cd001 | 11511 | |
d5cc9181 JR |
11512 | INIT_CUMULATIVE_ARGS (cum_v, NULL, NULL, 0, 0); |
11513 | cum = pack_cumulative_args (&cum_v); | |
fd3cd001 | 11514 | |
9a6f71b4 | 11515 | for (i = 0; i < call_expr_nargs (call_expr); i++) |
ab96de7e | 11516 | { |
9a6f71b4 | 11517 | parameter = CALL_EXPR_ARG (call_expr, i); |
8d933e31 | 11518 | gcc_assert (parameter); |
fd3cd001 | 11519 | |
ab96de7e AS |
11520 | /* For an undeclared variable passed as parameter we will get |
11521 | an ERROR_MARK node here. */ | |
11522 | if (TREE_CODE (parameter) == ERROR_MARK) | |
11523 | return true; | |
fd3cd001 | 11524 | |
8d933e31 AS |
11525 | type = TREE_TYPE (parameter); |
11526 | gcc_assert (type); | |
fd3cd001 | 11527 | |
8d933e31 AS |
11528 | mode = TYPE_MODE (type); |
11529 | gcc_assert (mode); | |
fd3cd001 | 11530 | |
085261c8 AK |
11531 | /* We assume that in the target function all parameters are |
11532 | named. This only has an impact on vector argument register | |
11533 | usage none of which is call-saved. */ | |
d5cc9181 | 11534 | if (pass_by_reference (&cum_v, mode, type, true)) |
ab96de7e AS |
11535 | { |
11536 | mode = Pmode; | |
11537 | type = build_pointer_type (type); | |
11538 | } | |
fd3cd001 | 11539 | |
085261c8 | 11540 | parm_rtx = s390_function_arg (cum, mode, type, true); |
fd3cd001 | 11541 | |
085261c8 | 11542 | s390_function_arg_advance (cum, mode, type, true); |
fd3cd001 | 11543 | |
9602b6a1 AK |
11544 | if (!parm_rtx) |
11545 | continue; | |
11546 | ||
11547 | if (REG_P (parm_rtx)) | |
11548 | { | |
e8de8fea AK |
11549 | for (reg = 0; |
11550 | reg < HARD_REGNO_NREGS (REGNO (parm_rtx), GET_MODE (parm_rtx)); | |
11551 | reg++) | |
9602b6a1 AK |
11552 | if (!call_used_regs[reg + REGNO (parm_rtx)]) |
11553 | return true; | |
11554 | } | |
11555 | ||
11556 | if (GET_CODE (parm_rtx) == PARALLEL) | |
ab96de7e | 11557 | { |
9602b6a1 | 11558 | int i; |
e8de8fea | 11559 | |
9602b6a1 AK |
11560 | for (i = 0; i < XVECLEN (parm_rtx, 0); i++) |
11561 | { | |
11562 | rtx r = XEXP (XVECEXP (parm_rtx, 0, i), 0); | |
9602b6a1 AK |
11563 | |
11564 | gcc_assert (REG_P (r)); | |
11565 | ||
e8de8fea AK |
11566 | for (reg = 0; |
11567 | reg < HARD_REGNO_NREGS (REGNO (r), GET_MODE (r)); | |
11568 | reg++) | |
9602b6a1 AK |
11569 | if (!call_used_regs[reg + REGNO (r)]) |
11570 | return true; | |
11571 | } | |
ab96de7e | 11572 | } |
9602b6a1 | 11573 | |
ab96de7e AS |
11574 | } |
11575 | return false; | |
11576 | } | |
fd3cd001 | 11577 | |
ab96de7e AS |
11578 | /* Return true if the given call expression can be |
11579 | turned into a sibling call. | |
11580 | DECL holds the declaration of the function to be called whereas | |
11581 | EXP is the call expression itself. */ | |
fd3cd001 | 11582 | |
ab96de7e AS |
11583 | static bool |
11584 | s390_function_ok_for_sibcall (tree decl, tree exp) | |
11585 | { | |
11586 | /* The TPF epilogue uses register 1. */ | |
11587 | if (TARGET_TPF_PROFILING) | |
11588 | return false; | |
fd3cd001 | 11589 | |
ab96de7e AS |
11590 | /* The 31 bit PLT code uses register 12 (GOT pointer - caller saved) |
11591 | which would have to be restored before the sibcall. */ | |
7691ec4e | 11592 | if (!TARGET_64BIT && flag_pic && decl && !targetm.binds_local_p (decl)) |
ab96de7e | 11593 | return false; |
fd3cd001 | 11594 | |
ab96de7e AS |
11595 | /* Register 6 on s390 is available as an argument register but unfortunately |
11596 | "caller saved". This makes functions needing this register for arguments | |
11597 | not suitable for sibcalls. */ | |
9a6f71b4 | 11598 | return !s390_call_saved_register_used (exp); |
ab96de7e | 11599 | } |
fd3cd001 | 11600 | |
ab96de7e | 11601 | /* Return the fixed registers used for condition codes. */ |
fd3cd001 | 11602 | |
ab96de7e AS |
11603 | static bool |
11604 | s390_fixed_condition_code_regs (unsigned int *p1, unsigned int *p2) | |
11605 | { | |
11606 | *p1 = CC_REGNUM; | |
11607 | *p2 = INVALID_REGNUM; | |
f4aa3848 | 11608 | |
ab96de7e AS |
11609 | return true; |
11610 | } | |
fd3cd001 | 11611 | |
ab96de7e AS |
11612 | /* This function is used by the call expanders of the machine description. |
11613 | It emits the call insn itself together with the necessary operations | |
11614 | to adjust the target address and returns the emitted insn. | |
11615 | ADDR_LOCATION is the target address rtx | |
11616 | TLS_CALL the location of the thread-local symbol | |
11617 | RESULT_REG the register where the result of the call should be stored | |
11618 | RETADDR_REG the register where the return address should be stored | |
11619 | If this parameter is NULL_RTX the call is considered | |
11620 | to be a sibling call. */ | |
fd3cd001 | 11621 | |
775c43d3 | 11622 | rtx_insn * |
ab96de7e AS |
11623 | s390_emit_call (rtx addr_location, rtx tls_call, rtx result_reg, |
11624 | rtx retaddr_reg) | |
9db1d521 | 11625 | { |
ab96de7e | 11626 | bool plt_call = false; |
775c43d3 | 11627 | rtx_insn *insn; |
ab96de7e AS |
11628 | rtx call; |
11629 | rtx clobber; | |
11630 | rtvec vec; | |
cadc42db | 11631 | |
ab96de7e AS |
11632 | /* Direct function calls need special treatment. */ |
11633 | if (GET_CODE (addr_location) == SYMBOL_REF) | |
9db1d521 | 11634 | { |
ab96de7e AS |
11635 | /* When calling a global routine in PIC mode, we must |
11636 | replace the symbol itself with the PLT stub. */ | |
11637 | if (flag_pic && !SYMBOL_REF_LOCAL_P (addr_location)) | |
11638 | { | |
72e2cf16 AK |
11639 | if (retaddr_reg != NULL_RTX) |
11640 | { | |
11641 | addr_location = gen_rtx_UNSPEC (Pmode, | |
11642 | gen_rtvec (1, addr_location), | |
11643 | UNSPEC_PLT); | |
11644 | addr_location = gen_rtx_CONST (Pmode, addr_location); | |
11645 | plt_call = true; | |
11646 | } | |
11647 | else | |
11648 | /* For -fpic code the PLT entries might use r12 which is | |
11649 | call-saved. Therefore we cannot do a sibcall when | |
11650 | calling directly using a symbol ref. When reaching | |
11651 | this point we decided (in s390_function_ok_for_sibcall) | |
11652 | to do a sibcall for a function pointer but one of the | |
11653 | optimizers was able to get rid of the function pointer | |
11654 | by propagating the symbol ref into the call. This | |
11655 | optimization is illegal for S/390 so we turn the direct | |
11656 | call into a indirect call again. */ | |
11657 | addr_location = force_reg (Pmode, addr_location); | |
ab96de7e AS |
11658 | } |
11659 | ||
11660 | /* Unless we can use the bras(l) insn, force the | |
11661 | routine address into a register. */ | |
11662 | if (!TARGET_SMALL_EXEC && !TARGET_CPU_ZARCH) | |
11663 | { | |
11664 | if (flag_pic) | |
11665 | addr_location = legitimize_pic_address (addr_location, 0); | |
11666 | else | |
11667 | addr_location = force_reg (Pmode, addr_location); | |
11668 | } | |
9db1d521 | 11669 | } |
ab96de7e AS |
11670 | |
11671 | /* If it is already an indirect call or the code above moved the | |
11672 | SYMBOL_REF to somewhere else make sure the address can be found in | |
11673 | register 1. */ | |
11674 | if (retaddr_reg == NULL_RTX | |
11675 | && GET_CODE (addr_location) != SYMBOL_REF | |
11676 | && !plt_call) | |
9db1d521 | 11677 | { |
ab96de7e AS |
11678 | emit_move_insn (gen_rtx_REG (Pmode, SIBCALL_REGNUM), addr_location); |
11679 | addr_location = gen_rtx_REG (Pmode, SIBCALL_REGNUM); | |
9db1d521 | 11680 | } |
9db1d521 | 11681 | |
ab96de7e AS |
11682 | addr_location = gen_rtx_MEM (QImode, addr_location); |
11683 | call = gen_rtx_CALL (VOIDmode, addr_location, const0_rtx); | |
4023fb28 | 11684 | |
ab96de7e | 11685 | if (result_reg != NULL_RTX) |
f7df4a84 | 11686 | call = gen_rtx_SET (result_reg, call); |
4023fb28 | 11687 | |
ab96de7e AS |
11688 | if (retaddr_reg != NULL_RTX) |
11689 | { | |
11690 | clobber = gen_rtx_CLOBBER (VOIDmode, retaddr_reg); | |
c7453384 | 11691 | |
ab96de7e AS |
11692 | if (tls_call != NULL_RTX) |
11693 | vec = gen_rtvec (3, call, clobber, | |
11694 | gen_rtx_USE (VOIDmode, tls_call)); | |
11695 | else | |
11696 | vec = gen_rtvec (2, call, clobber); | |
4023fb28 | 11697 | |
ab96de7e AS |
11698 | call = gen_rtx_PARALLEL (VOIDmode, vec); |
11699 | } | |
4023fb28 | 11700 | |
ab96de7e | 11701 | insn = emit_call_insn (call); |
4023fb28 | 11702 | |
ab96de7e AS |
11703 | /* 31-bit PLT stubs and tls calls use the GOT register implicitly. */ |
11704 | if ((!TARGET_64BIT && plt_call) || tls_call != NULL_RTX) | |
11705 | { | |
11706 | /* s390_function_ok_for_sibcall should | |
11707 | have denied sibcalls in this case. */ | |
8d933e31 | 11708 | gcc_assert (retaddr_reg != NULL_RTX); |
68c0ef75 | 11709 | use_reg (&CALL_INSN_FUNCTION_USAGE (insn), gen_rtx_REG (Pmode, 12)); |
ab96de7e AS |
11710 | } |
11711 | return insn; | |
11712 | } | |
4023fb28 | 11713 | |
5efd84c5 | 11714 | /* Implement TARGET_CONDITIONAL_REGISTER_USAGE. */ |
4023fb28 | 11715 | |
5efd84c5 | 11716 | static void |
ab96de7e AS |
11717 | s390_conditional_register_usage (void) |
11718 | { | |
11719 | int i; | |
4023fb28 | 11720 | |
4023fb28 UW |
11721 | if (flag_pic) |
11722 | { | |
ab96de7e AS |
11723 | fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; |
11724 | call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; | |
4023fb28 | 11725 | } |
ab96de7e | 11726 | if (TARGET_CPU_ZARCH) |
4023fb28 | 11727 | { |
7633f08e UW |
11728 | fixed_regs[BASE_REGNUM] = 0; |
11729 | call_used_regs[BASE_REGNUM] = 0; | |
ab96de7e AS |
11730 | fixed_regs[RETURN_REGNUM] = 0; |
11731 | call_used_regs[RETURN_REGNUM] = 0; | |
4023fb28 | 11732 | } |
ab96de7e | 11733 | if (TARGET_64BIT) |
4023fb28 | 11734 | { |
2cf4c39e | 11735 | for (i = FPR8_REGNUM; i <= FPR15_REGNUM; i++) |
ab96de7e | 11736 | call_used_regs[i] = call_really_used_regs[i] = 0; |
4023fb28 UW |
11737 | } |
11738 | else | |
11739 | { | |
2cf4c39e AK |
11740 | call_used_regs[FPR4_REGNUM] = call_really_used_regs[FPR4_REGNUM] = 0; |
11741 | call_used_regs[FPR6_REGNUM] = call_really_used_regs[FPR6_REGNUM] = 0; | |
ab96de7e | 11742 | } |
4023fb28 | 11743 | |
ab96de7e AS |
11744 | if (TARGET_SOFT_FLOAT) |
11745 | { | |
2cf4c39e | 11746 | for (i = FPR0_REGNUM; i <= FPR15_REGNUM; i++) |
ab96de7e | 11747 | call_used_regs[i] = fixed_regs[i] = 1; |
4023fb28 | 11748 | } |
085261c8 AK |
11749 | |
11750 | /* Disable v16 - v31 for non-vector target. */ | |
11751 | if (!TARGET_VX) | |
11752 | { | |
11753 | for (i = VR16_REGNUM; i <= VR31_REGNUM; i++) | |
11754 | fixed_regs[i] = call_used_regs[i] = call_really_used_regs[i] = 1; | |
11755 | } | |
4023fb28 UW |
11756 | } |
11757 | ||
ab96de7e | 11758 | /* Corresponding function to eh_return expander. */ |
fb49053f | 11759 | |
ab96de7e AS |
11760 | static GTY(()) rtx s390_tpf_eh_return_symbol; |
11761 | void | |
11762 | s390_emit_tpf_eh_return (rtx target) | |
fb49053f | 11763 | { |
775c43d3 DM |
11764 | rtx_insn *insn; |
11765 | rtx reg, orig_ra; | |
e23795ea | 11766 | |
ab96de7e AS |
11767 | if (!s390_tpf_eh_return_symbol) |
11768 | s390_tpf_eh_return_symbol = gen_rtx_SYMBOL_REF (Pmode, "__tpf_eh_return"); | |
11769 | ||
11770 | reg = gen_rtx_REG (Pmode, 2); | |
87cb0c0c | 11771 | orig_ra = gen_rtx_REG (Pmode, 3); |
ab96de7e AS |
11772 | |
11773 | emit_move_insn (reg, target); | |
87cb0c0c | 11774 | emit_move_insn (orig_ra, get_hard_reg_initial_val (Pmode, RETURN_REGNUM)); |
ab96de7e AS |
11775 | insn = s390_emit_call (s390_tpf_eh_return_symbol, NULL_RTX, reg, |
11776 | gen_rtx_REG (Pmode, RETURN_REGNUM)); | |
11777 | use_reg (&CALL_INSN_FUNCTION_USAGE (insn), reg); | |
87cb0c0c | 11778 | use_reg (&CALL_INSN_FUNCTION_USAGE (insn), orig_ra); |
ab96de7e AS |
11779 | |
11780 | emit_move_insn (EH_RETURN_HANDLER_RTX, reg); | |
fd3cd001 UW |
11781 | } |
11782 | ||
ab96de7e AS |
11783 | /* Rework the prologue/epilogue to avoid saving/restoring |
11784 | registers unnecessarily. */ | |
3062825f | 11785 | |
c590b625 | 11786 | static void |
ab96de7e | 11787 | s390_optimize_prologue (void) |
483ab821 | 11788 | { |
775c43d3 | 11789 | rtx_insn *insn, *new_insn, *next_insn; |
3062825f | 11790 | |
ab96de7e | 11791 | /* Do a final recompute of the frame-related data. */ |
6455a49e | 11792 | s390_optimize_register_info (); |
3062825f | 11793 | |
ab96de7e AS |
11794 | /* If all special registers are in fact used, there's nothing we |
11795 | can do, so no point in walking the insn list. */ | |
3062825f | 11796 | |
f4aa3848 | 11797 | if (cfun_frame_layout.first_save_gpr <= BASE_REGNUM |
ab96de7e | 11798 | && cfun_frame_layout.last_save_gpr >= BASE_REGNUM |
f4aa3848 AK |
11799 | && (TARGET_CPU_ZARCH |
11800 | || (cfun_frame_layout.first_save_gpr <= RETURN_REGNUM | |
ab96de7e AS |
11801 | && cfun_frame_layout.last_save_gpr >= RETURN_REGNUM))) |
11802 | return; | |
3062825f | 11803 | |
ab96de7e | 11804 | /* Search for prologue/epilogue insns and replace them. */ |
3062825f | 11805 | |
ab96de7e AS |
11806 | for (insn = get_insns (); insn; insn = next_insn) |
11807 | { | |
11808 | int first, last, off; | |
11809 | rtx set, base, offset; | |
6455a49e | 11810 | rtx pat; |
3062825f | 11811 | |
ab96de7e | 11812 | next_insn = NEXT_INSN (insn); |
89ce1c8f | 11813 | |
6455a49e | 11814 | if (! NONJUMP_INSN_P (insn) || ! RTX_FRAME_RELATED_P (insn)) |
ab96de7e | 11815 | continue; |
3062825f | 11816 | |
6455a49e AK |
11817 | pat = PATTERN (insn); |
11818 | ||
11819 | /* Remove ldgr/lgdr instructions used for saving and restore | |
11820 | GPRs if possible. */ | |
11821 | if (TARGET_Z10 | |
11822 | && GET_CODE (pat) == SET | |
11823 | && GET_MODE (SET_SRC (pat)) == DImode | |
11824 | && REG_P (SET_SRC (pat)) | |
11825 | && REG_P (SET_DEST (pat))) | |
11826 | { | |
11827 | int src_regno = REGNO (SET_SRC (pat)); | |
11828 | int dest_regno = REGNO (SET_DEST (pat)); | |
11829 | int gpr_regno; | |
11830 | int fpr_regno; | |
11831 | ||
11832 | if (!((GENERAL_REGNO_P (src_regno) && FP_REGNO_P (dest_regno)) | |
11833 | || (FP_REGNO_P (src_regno) && GENERAL_REGNO_P (dest_regno)))) | |
11834 | continue; | |
11835 | ||
11836 | gpr_regno = GENERAL_REGNO_P (src_regno) ? src_regno : dest_regno; | |
11837 | fpr_regno = FP_REGNO_P (src_regno) ? src_regno : dest_regno; | |
11838 | ||
11839 | /* GPR must be call-saved, FPR must be call-clobbered. */ | |
11840 | if (!call_really_used_regs[fpr_regno] | |
11841 | || call_really_used_regs[gpr_regno]) | |
11842 | continue; | |
11843 | ||
6455a49e AK |
11844 | /* It must not happen that what we once saved in an FPR now |
11845 | needs a stack slot. */ | |
11846 | gcc_assert (cfun_gpr_save_slot (gpr_regno) != -1); | |
11847 | ||
11848 | if (cfun_gpr_save_slot (gpr_regno) == 0) | |
11849 | { | |
11850 | remove_insn (insn); | |
11851 | continue; | |
11852 | } | |
11853 | } | |
11854 | ||
11855 | if (GET_CODE (pat) == PARALLEL | |
11856 | && store_multiple_operation (pat, VOIDmode)) | |
3062825f | 11857 | { |
6455a49e | 11858 | set = XVECEXP (pat, 0, 0); |
ab96de7e | 11859 | first = REGNO (SET_SRC (set)); |
6455a49e | 11860 | last = first + XVECLEN (pat, 0) - 1; |
ab96de7e AS |
11861 | offset = const0_rtx; |
11862 | base = eliminate_constant_term (XEXP (SET_DEST (set), 0), &offset); | |
11863 | off = INTVAL (offset); | |
3062825f | 11864 | |
ab96de7e AS |
11865 | if (GET_CODE (base) != REG || off < 0) |
11866 | continue; | |
22a707a4 AK |
11867 | if (cfun_frame_layout.first_save_gpr != -1 |
11868 | && (cfun_frame_layout.first_save_gpr < first | |
11869 | || cfun_frame_layout.last_save_gpr > last)) | |
11870 | continue; | |
ab96de7e AS |
11871 | if (REGNO (base) != STACK_POINTER_REGNUM |
11872 | && REGNO (base) != HARD_FRAME_POINTER_REGNUM) | |
11873 | continue; | |
11874 | if (first > BASE_REGNUM || last < BASE_REGNUM) | |
11875 | continue; | |
11876 | ||
11877 | if (cfun_frame_layout.first_save_gpr != -1) | |
3062825f | 11878 | { |
775c43d3 | 11879 | rtx s_pat = save_gprs (base, |
ab96de7e | 11880 | off + (cfun_frame_layout.first_save_gpr |
9602b6a1 | 11881 | - first) * UNITS_PER_LONG, |
ab96de7e AS |
11882 | cfun_frame_layout.first_save_gpr, |
11883 | cfun_frame_layout.last_save_gpr); | |
775c43d3 | 11884 | new_insn = emit_insn_before (s_pat, insn); |
ab96de7e | 11885 | INSN_ADDRESSES_NEW (new_insn, -1); |
3062825f | 11886 | } |
3062825f | 11887 | |
ab96de7e AS |
11888 | remove_insn (insn); |
11889 | continue; | |
3062825f UW |
11890 | } |
11891 | ||
22a707a4 | 11892 | if (cfun_frame_layout.first_save_gpr == -1 |
6455a49e AK |
11893 | && GET_CODE (pat) == SET |
11894 | && GENERAL_REG_P (SET_SRC (pat)) | |
11895 | && GET_CODE (SET_DEST (pat)) == MEM) | |
3062825f | 11896 | { |
6455a49e | 11897 | set = pat; |
ab96de7e AS |
11898 | first = REGNO (SET_SRC (set)); |
11899 | offset = const0_rtx; | |
11900 | base = eliminate_constant_term (XEXP (SET_DEST (set), 0), &offset); | |
11901 | off = INTVAL (offset); | |
3062825f | 11902 | |
ab96de7e AS |
11903 | if (GET_CODE (base) != REG || off < 0) |
11904 | continue; | |
11905 | if (REGNO (base) != STACK_POINTER_REGNUM | |
11906 | && REGNO (base) != HARD_FRAME_POINTER_REGNUM) | |
11907 | continue; | |
3062825f | 11908 | |
ab96de7e AS |
11909 | remove_insn (insn); |
11910 | continue; | |
3062825f UW |
11911 | } |
11912 | ||
6455a49e AK |
11913 | if (GET_CODE (pat) == PARALLEL |
11914 | && load_multiple_operation (pat, VOIDmode)) | |
89ce1c8f | 11915 | { |
6455a49e | 11916 | set = XVECEXP (pat, 0, 0); |
ab96de7e | 11917 | first = REGNO (SET_DEST (set)); |
6455a49e | 11918 | last = first + XVECLEN (pat, 0) - 1; |
ab96de7e AS |
11919 | offset = const0_rtx; |
11920 | base = eliminate_constant_term (XEXP (SET_SRC (set), 0), &offset); | |
11921 | off = INTVAL (offset); | |
89ce1c8f | 11922 | |
ab96de7e AS |
11923 | if (GET_CODE (base) != REG || off < 0) |
11924 | continue; | |
6455a49e | 11925 | |
22a707a4 AK |
11926 | if (cfun_frame_layout.first_restore_gpr != -1 |
11927 | && (cfun_frame_layout.first_restore_gpr < first | |
11928 | || cfun_frame_layout.last_restore_gpr > last)) | |
11929 | continue; | |
ab96de7e AS |
11930 | if (REGNO (base) != STACK_POINTER_REGNUM |
11931 | && REGNO (base) != HARD_FRAME_POINTER_REGNUM) | |
11932 | continue; | |
11933 | if (first > BASE_REGNUM || last < BASE_REGNUM) | |
11934 | continue; | |
3062825f | 11935 | |
ab96de7e AS |
11936 | if (cfun_frame_layout.first_restore_gpr != -1) |
11937 | { | |
775c43d3 | 11938 | rtx rpat = restore_gprs (base, |
ab96de7e | 11939 | off + (cfun_frame_layout.first_restore_gpr |
9602b6a1 | 11940 | - first) * UNITS_PER_LONG, |
ab96de7e AS |
11941 | cfun_frame_layout.first_restore_gpr, |
11942 | cfun_frame_layout.last_restore_gpr); | |
0621cf3c RS |
11943 | |
11944 | /* Remove REG_CFA_RESTOREs for registers that we no | |
11945 | longer need to save. */ | |
775c43d3 DM |
11946 | REG_NOTES (rpat) = REG_NOTES (insn); |
11947 | for (rtx *ptr = ®_NOTES (rpat); *ptr; ) | |
0621cf3c RS |
11948 | if (REG_NOTE_KIND (*ptr) == REG_CFA_RESTORE |
11949 | && ((int) REGNO (XEXP (*ptr, 0)) | |
11950 | < cfun_frame_layout.first_restore_gpr)) | |
11951 | *ptr = XEXP (*ptr, 1); | |
11952 | else | |
11953 | ptr = &XEXP (*ptr, 1); | |
775c43d3 | 11954 | new_insn = emit_insn_before (rpat, insn); |
0621cf3c | 11955 | RTX_FRAME_RELATED_P (new_insn) = 1; |
ab96de7e AS |
11956 | INSN_ADDRESSES_NEW (new_insn, -1); |
11957 | } | |
89ce1c8f | 11958 | |
ab96de7e AS |
11959 | remove_insn (insn); |
11960 | continue; | |
89ce1c8f JJ |
11961 | } |
11962 | ||
22a707a4 | 11963 | if (cfun_frame_layout.first_restore_gpr == -1 |
6455a49e AK |
11964 | && GET_CODE (pat) == SET |
11965 | && GENERAL_REG_P (SET_DEST (pat)) | |
11966 | && GET_CODE (SET_SRC (pat)) == MEM) | |
3062825f | 11967 | { |
6455a49e | 11968 | set = pat; |
ab96de7e AS |
11969 | first = REGNO (SET_DEST (set)); |
11970 | offset = const0_rtx; | |
11971 | base = eliminate_constant_term (XEXP (SET_SRC (set), 0), &offset); | |
11972 | off = INTVAL (offset); | |
c7453384 | 11973 | |
ab96de7e AS |
11974 | if (GET_CODE (base) != REG || off < 0) |
11975 | continue; | |
6455a49e | 11976 | |
ab96de7e AS |
11977 | if (REGNO (base) != STACK_POINTER_REGNUM |
11978 | && REGNO (base) != HARD_FRAME_POINTER_REGNUM) | |
11979 | continue; | |
29742ba4 | 11980 | |
ab96de7e AS |
11981 | remove_insn (insn); |
11982 | continue; | |
11983 | } | |
11984 | } | |
29742ba4 HP |
11985 | } |
11986 | ||
65b1d8ea AK |
11987 | /* On z10 and later the dynamic branch prediction must see the |
11988 | backward jump within a certain windows. If not it falls back to | |
11989 | the static prediction. This function rearranges the loop backward | |
11990 | branch in a way which makes the static prediction always correct. | |
11991 | The function returns true if it added an instruction. */ | |
b0f86a7e | 11992 | static bool |
775c43d3 | 11993 | s390_fix_long_loop_prediction (rtx_insn *insn) |
b0f86a7e AK |
11994 | { |
11995 | rtx set = single_set (insn); | |
11996 | rtx code_label, label_ref, new_label; | |
e60365d3 | 11997 | rtx_insn *uncond_jump; |
775c43d3 | 11998 | rtx_insn *cur_insn; |
b0f86a7e AK |
11999 | rtx tmp; |
12000 | int distance; | |
12001 | ||
12002 | /* This will exclude branch on count and branch on index patterns | |
12003 | since these are correctly statically predicted. */ | |
12004 | if (!set | |
12005 | || SET_DEST (set) != pc_rtx | |
12006 | || GET_CODE (SET_SRC(set)) != IF_THEN_ELSE) | |
12007 | return false; | |
12008 | ||
177bc204 RS |
12009 | /* Skip conditional returns. */ |
12010 | if (ANY_RETURN_P (XEXP (SET_SRC (set), 1)) | |
12011 | && XEXP (SET_SRC (set), 2) == pc_rtx) | |
12012 | return false; | |
12013 | ||
b0f86a7e AK |
12014 | label_ref = (GET_CODE (XEXP (SET_SRC (set), 1)) == LABEL_REF ? |
12015 | XEXP (SET_SRC (set), 1) : XEXP (SET_SRC (set), 2)); | |
12016 | ||
12017 | gcc_assert (GET_CODE (label_ref) == LABEL_REF); | |
12018 | ||
12019 | code_label = XEXP (label_ref, 0); | |
12020 | ||
12021 | if (INSN_ADDRESSES (INSN_UID (code_label)) == -1 | |
12022 | || INSN_ADDRESSES (INSN_UID (insn)) == -1 | |
12023 | || (INSN_ADDRESSES (INSN_UID (insn)) | |
65b1d8ea | 12024 | - INSN_ADDRESSES (INSN_UID (code_label)) < PREDICT_DISTANCE)) |
b0f86a7e AK |
12025 | return false; |
12026 | ||
12027 | for (distance = 0, cur_insn = PREV_INSN (insn); | |
65b1d8ea | 12028 | distance < PREDICT_DISTANCE - 6; |
b0f86a7e AK |
12029 | distance += get_attr_length (cur_insn), cur_insn = PREV_INSN (cur_insn)) |
12030 | if (!cur_insn || JUMP_P (cur_insn) || LABEL_P (cur_insn)) | |
12031 | return false; | |
12032 | ||
12033 | new_label = gen_label_rtx (); | |
12034 | uncond_jump = emit_jump_insn_after ( | |
f7df4a84 | 12035 | gen_rtx_SET (pc_rtx, |
b0f86a7e AK |
12036 | gen_rtx_LABEL_REF (VOIDmode, code_label)), |
12037 | insn); | |
12038 | emit_label_after (new_label, uncond_jump); | |
12039 | ||
12040 | tmp = XEXP (SET_SRC (set), 1); | |
12041 | XEXP (SET_SRC (set), 1) = XEXP (SET_SRC (set), 2); | |
12042 | XEXP (SET_SRC (set), 2) = tmp; | |
12043 | INSN_CODE (insn) = -1; | |
12044 | ||
12045 | XEXP (label_ref, 0) = new_label; | |
12046 | JUMP_LABEL (insn) = new_label; | |
12047 | JUMP_LABEL (uncond_jump) = code_label; | |
12048 | ||
12049 | return true; | |
12050 | } | |
12051 | ||
d277db6b WG |
12052 | /* Returns 1 if INSN reads the value of REG for purposes not related |
12053 | to addressing of memory, and 0 otherwise. */ | |
12054 | static int | |
775c43d3 | 12055 | s390_non_addr_reg_read_p (rtx reg, rtx_insn *insn) |
d277db6b WG |
12056 | { |
12057 | return reg_referenced_p (reg, PATTERN (insn)) | |
12058 | && !reg_used_in_mem_p (REGNO (reg), PATTERN (insn)); | |
12059 | } | |
12060 | ||
e3cba5e5 AK |
12061 | /* Starting from INSN find_cond_jump looks downwards in the insn |
12062 | stream for a single jump insn which is the last user of the | |
12063 | condition code set in INSN. */ | |
775c43d3 DM |
12064 | static rtx_insn * |
12065 | find_cond_jump (rtx_insn *insn) | |
e3cba5e5 AK |
12066 | { |
12067 | for (; insn; insn = NEXT_INSN (insn)) | |
12068 | { | |
12069 | rtx ite, cc; | |
12070 | ||
12071 | if (LABEL_P (insn)) | |
12072 | break; | |
12073 | ||
12074 | if (!JUMP_P (insn)) | |
12075 | { | |
12076 | if (reg_mentioned_p (gen_rtx_REG (CCmode, CC_REGNUM), insn)) | |
12077 | break; | |
12078 | continue; | |
12079 | } | |
12080 | ||
12081 | /* This will be triggered by a return. */ | |
12082 | if (GET_CODE (PATTERN (insn)) != SET) | |
12083 | break; | |
12084 | ||
12085 | gcc_assert (SET_DEST (PATTERN (insn)) == pc_rtx); | |
12086 | ite = SET_SRC (PATTERN (insn)); | |
12087 | ||
12088 | if (GET_CODE (ite) != IF_THEN_ELSE) | |
12089 | break; | |
12090 | ||
12091 | cc = XEXP (XEXP (ite, 0), 0); | |
12092 | if (!REG_P (cc) || !CC_REGNO_P (REGNO (cc))) | |
12093 | break; | |
12094 | ||
12095 | if (find_reg_note (insn, REG_DEAD, cc)) | |
12096 | return insn; | |
12097 | break; | |
12098 | } | |
12099 | ||
775c43d3 | 12100 | return NULL; |
e3cba5e5 AK |
12101 | } |
12102 | ||
12103 | /* Swap the condition in COND and the operands in OP0 and OP1 so that | |
12104 | the semantics does not change. If NULL_RTX is passed as COND the | |
12105 | function tries to find the conditional jump starting with INSN. */ | |
12106 | static void | |
775c43d3 | 12107 | s390_swap_cmp (rtx cond, rtx *op0, rtx *op1, rtx_insn *insn) |
e3cba5e5 AK |
12108 | { |
12109 | rtx tmp = *op0; | |
12110 | ||
12111 | if (cond == NULL_RTX) | |
12112 | { | |
e8a54173 DM |
12113 | rtx_insn *jump = find_cond_jump (NEXT_INSN (insn)); |
12114 | rtx set = jump ? single_set (jump) : NULL_RTX; | |
e3cba5e5 | 12115 | |
e8a54173 | 12116 | if (set == NULL_RTX) |
e3cba5e5 AK |
12117 | return; |
12118 | ||
e8a54173 | 12119 | cond = XEXP (SET_SRC (set), 0); |
e3cba5e5 AK |
12120 | } |
12121 | ||
12122 | *op0 = *op1; | |
12123 | *op1 = tmp; | |
12124 | PUT_CODE (cond, swap_condition (GET_CODE (cond))); | |
12125 | } | |
d277db6b WG |
12126 | |
12127 | /* On z10, instructions of the compare-and-branch family have the | |
12128 | property to access the register occurring as second operand with | |
12129 | its bits complemented. If such a compare is grouped with a second | |
12130 | instruction that accesses the same register non-complemented, and | |
12131 | if that register's value is delivered via a bypass, then the | |
12132 | pipeline recycles, thereby causing significant performance decline. | |
12133 | This function locates such situations and exchanges the two | |
b0f86a7e AK |
12134 | operands of the compare. The function return true whenever it |
12135 | added an insn. */ | |
12136 | static bool | |
775c43d3 | 12137 | s390_z10_optimize_cmp (rtx_insn *insn) |
d277db6b | 12138 | { |
775c43d3 | 12139 | rtx_insn *prev_insn, *next_insn; |
b0f86a7e AK |
12140 | bool insn_added_p = false; |
12141 | rtx cond, *op0, *op1; | |
d277db6b | 12142 | |
b0f86a7e | 12143 | if (GET_CODE (PATTERN (insn)) == PARALLEL) |
d277db6b | 12144 | { |
b0f86a7e AK |
12145 | /* Handle compare and branch and branch on count |
12146 | instructions. */ | |
12147 | rtx pattern = single_set (insn); | |
e3cba5e5 | 12148 | |
b0f86a7e AK |
12149 | if (!pattern |
12150 | || SET_DEST (pattern) != pc_rtx | |
12151 | || GET_CODE (SET_SRC (pattern)) != IF_THEN_ELSE) | |
12152 | return false; | |
d277db6b | 12153 | |
b0f86a7e AK |
12154 | cond = XEXP (SET_SRC (pattern), 0); |
12155 | op0 = &XEXP (cond, 0); | |
12156 | op1 = &XEXP (cond, 1); | |
12157 | } | |
12158 | else if (GET_CODE (PATTERN (insn)) == SET) | |
12159 | { | |
12160 | rtx src, dest; | |
d277db6b | 12161 | |
b0f86a7e AK |
12162 | /* Handle normal compare instructions. */ |
12163 | src = SET_SRC (PATTERN (insn)); | |
12164 | dest = SET_DEST (PATTERN (insn)); | |
e3cba5e5 | 12165 | |
b0f86a7e AK |
12166 | if (!REG_P (dest) |
12167 | || !CC_REGNO_P (REGNO (dest)) | |
12168 | || GET_CODE (src) != COMPARE) | |
12169 | return false; | |
e3cba5e5 | 12170 | |
b0f86a7e AK |
12171 | /* s390_swap_cmp will try to find the conditional |
12172 | jump when passing NULL_RTX as condition. */ | |
12173 | cond = NULL_RTX; | |
12174 | op0 = &XEXP (src, 0); | |
12175 | op1 = &XEXP (src, 1); | |
12176 | } | |
12177 | else | |
12178 | return false; | |
e3cba5e5 | 12179 | |
b0f86a7e AK |
12180 | if (!REG_P (*op0) || !REG_P (*op1)) |
12181 | return false; | |
e3cba5e5 | 12182 | |
2dfdbf2b AK |
12183 | if (GET_MODE_CLASS (GET_MODE (*op0)) != MODE_INT) |
12184 | return false; | |
12185 | ||
b0f86a7e AK |
12186 | /* Swap the COMPARE arguments and its mask if there is a |
12187 | conflicting access in the previous insn. */ | |
33ab2bd4 | 12188 | prev_insn = prev_active_insn (insn); |
b0f86a7e AK |
12189 | if (prev_insn != NULL_RTX && INSN_P (prev_insn) |
12190 | && reg_referenced_p (*op1, PATTERN (prev_insn))) | |
12191 | s390_swap_cmp (cond, op0, op1, insn); | |
12192 | ||
12193 | /* Check if there is a conflict with the next insn. If there | |
12194 | was no conflict with the previous insn, then swap the | |
12195 | COMPARE arguments and its mask. If we already swapped | |
12196 | the operands, or if swapping them would cause a conflict | |
12197 | with the previous insn, issue a NOP after the COMPARE in | |
12198 | order to separate the two instuctions. */ | |
33ab2bd4 | 12199 | next_insn = next_active_insn (insn); |
b0f86a7e AK |
12200 | if (next_insn != NULL_RTX && INSN_P (next_insn) |
12201 | && s390_non_addr_reg_read_p (*op1, next_insn)) | |
12202 | { | |
e3cba5e5 | 12203 | if (prev_insn != NULL_RTX && INSN_P (prev_insn) |
b0f86a7e | 12204 | && s390_non_addr_reg_read_p (*op0, prev_insn)) |
e3cba5e5 | 12205 | { |
b0f86a7e AK |
12206 | if (REGNO (*op1) == 0) |
12207 | emit_insn_after (gen_nop1 (), insn); | |
e3cba5e5 | 12208 | else |
b0f86a7e AK |
12209 | emit_insn_after (gen_nop (), insn); |
12210 | insn_added_p = true; | |
d277db6b | 12211 | } |
b0f86a7e AK |
12212 | else |
12213 | s390_swap_cmp (cond, op0, op1, insn); | |
d277db6b | 12214 | } |
b0f86a7e | 12215 | return insn_added_p; |
d277db6b WG |
12216 | } |
12217 | ||
ab96de7e | 12218 | /* Perform machine-dependent processing. */ |
ed9676cf | 12219 | |
ab96de7e AS |
12220 | static void |
12221 | s390_reorg (void) | |
ed9676cf | 12222 | { |
ab96de7e | 12223 | bool pool_overflow = false; |
f8af0e30 | 12224 | int hw_before, hw_after; |
ed9676cf | 12225 | |
ab96de7e AS |
12226 | /* Make sure all splits have been performed; splits after |
12227 | machine_dependent_reorg might confuse insn length counts. */ | |
12228 | split_all_insns_noflow (); | |
38899e29 | 12229 | |
ab96de7e AS |
12230 | /* Install the main literal pool and the associated base |
12231 | register load insns. | |
38899e29 | 12232 | |
ab96de7e AS |
12233 | In addition, there are two problematic situations we need |
12234 | to correct: | |
ed9676cf | 12235 | |
ab96de7e AS |
12236 | - the literal pool might be > 4096 bytes in size, so that |
12237 | some of its elements cannot be directly accessed | |
ed9676cf | 12238 | |
ab96de7e AS |
12239 | - a branch target might be > 64K away from the branch, so that |
12240 | it is not possible to use a PC-relative instruction. | |
ed9676cf | 12241 | |
ab96de7e AS |
12242 | To fix those, we split the single literal pool into multiple |
12243 | pool chunks, reloading the pool base register at various | |
12244 | points throughout the function to ensure it always points to | |
12245 | the pool chunk the following code expects, and / or replace | |
12246 | PC-relative branches by absolute branches. | |
ed9676cf | 12247 | |
ab96de7e AS |
12248 | However, the two problems are interdependent: splitting the |
12249 | literal pool can move a branch further away from its target, | |
12250 | causing the 64K limit to overflow, and on the other hand, | |
12251 | replacing a PC-relative branch by an absolute branch means | |
12252 | we need to put the branch target address into the literal | |
12253 | pool, possibly causing it to overflow. | |
ffdda752 | 12254 | |
ab96de7e AS |
12255 | So, we loop trying to fix up both problems until we manage |
12256 | to satisfy both conditions at the same time. Note that the | |
12257 | loop is guaranteed to terminate as every pass of the loop | |
12258 | strictly decreases the total number of PC-relative branches | |
12259 | in the function. (This is not completely true as there | |
12260 | might be branch-over-pool insns introduced by chunkify_start. | |
12261 | Those never need to be split however.) */ | |
ffdda752 | 12262 | |
ab96de7e AS |
12263 | for (;;) |
12264 | { | |
12265 | struct constant_pool *pool = NULL; | |
a628ab6d | 12266 | |
ab96de7e AS |
12267 | /* Collect the literal pool. */ |
12268 | if (!pool_overflow) | |
12269 | { | |
12270 | pool = s390_mainpool_start (); | |
12271 | if (!pool) | |
12272 | pool_overflow = true; | |
12273 | } | |
a628ab6d | 12274 | |
ab96de7e AS |
12275 | /* If literal pool overflowed, start to chunkify it. */ |
12276 | if (pool_overflow) | |
12277 | pool = s390_chunkify_start (); | |
a628ab6d | 12278 | |
ab96de7e AS |
12279 | /* Split out-of-range branches. If this has created new |
12280 | literal pool entries, cancel current chunk list and | |
12281 | recompute it. zSeries machines have large branch | |
12282 | instructions, so we never need to split a branch. */ | |
12283 | if (!TARGET_CPU_ZARCH && s390_split_branches ()) | |
12284 | { | |
12285 | if (pool_overflow) | |
12286 | s390_chunkify_cancel (pool); | |
12287 | else | |
12288 | s390_mainpool_cancel (pool); | |
a628ab6d | 12289 | |
ab96de7e AS |
12290 | continue; |
12291 | } | |
12292 | ||
12293 | /* If we made it up to here, both conditions are satisfied. | |
12294 | Finish up literal pool related changes. */ | |
12295 | if (pool_overflow) | |
12296 | s390_chunkify_finish (pool); | |
12297 | else | |
12298 | s390_mainpool_finish (pool); | |
12299 | ||
12300 | /* We're done splitting branches. */ | |
12301 | cfun->machine->split_branches_pending_p = false; | |
12302 | break; | |
a628ab6d | 12303 | } |
a628ab6d | 12304 | |
d24959df UW |
12305 | /* Generate out-of-pool execute target insns. */ |
12306 | if (TARGET_CPU_ZARCH) | |
12307 | { | |
775c43d3 DM |
12308 | rtx_insn *insn, *target; |
12309 | rtx label; | |
d24959df UW |
12310 | |
12311 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) | |
12312 | { | |
12313 | label = s390_execute_label (insn); | |
12314 | if (!label) | |
12315 | continue; | |
12316 | ||
12317 | gcc_assert (label != const0_rtx); | |
12318 | ||
12319 | target = emit_label (XEXP (label, 0)); | |
12320 | INSN_ADDRESSES_NEW (target, -1); | |
12321 | ||
12322 | target = emit_insn (s390_execute_target (insn)); | |
12323 | INSN_ADDRESSES_NEW (target, -1); | |
12324 | } | |
12325 | } | |
12326 | ||
12327 | /* Try to optimize prologue and epilogue further. */ | |
ab96de7e | 12328 | s390_optimize_prologue (); |
d277db6b | 12329 | |
65b1d8ea AK |
12330 | /* Walk over the insns and do some >=z10 specific changes. */ |
12331 | if (s390_tune == PROCESSOR_2097_Z10 | |
22ac2c2f | 12332 | || s390_tune == PROCESSOR_2817_Z196 |
55ac540c AK |
12333 | || s390_tune == PROCESSOR_2827_ZEC12 |
12334 | || s390_tune == PROCESSOR_2964_Z13) | |
b0f86a7e | 12335 | { |
775c43d3 | 12336 | rtx_insn *insn; |
b0f86a7e AK |
12337 | bool insn_added_p = false; |
12338 | ||
12339 | /* The insn lengths and addresses have to be up to date for the | |
12340 | following manipulations. */ | |
12341 | shorten_branches (get_insns ()); | |
12342 | ||
12343 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) | |
12344 | { | |
12345 | if (!INSN_P (insn) || INSN_CODE (insn) <= 0) | |
12346 | continue; | |
12347 | ||
12348 | if (JUMP_P (insn)) | |
65b1d8ea | 12349 | insn_added_p |= s390_fix_long_loop_prediction (insn); |
b0f86a7e | 12350 | |
65b1d8ea AK |
12351 | if ((GET_CODE (PATTERN (insn)) == PARALLEL |
12352 | || GET_CODE (PATTERN (insn)) == SET) | |
12353 | && s390_tune == PROCESSOR_2097_Z10) | |
b0f86a7e AK |
12354 | insn_added_p |= s390_z10_optimize_cmp (insn); |
12355 | } | |
12356 | ||
12357 | /* Adjust branches if we added new instructions. */ | |
12358 | if (insn_added_p) | |
12359 | shorten_branches (get_insns ()); | |
12360 | } | |
f8af0e30 DV |
12361 | |
12362 | s390_function_num_hotpatch_hw (current_function_decl, &hw_before, &hw_after); | |
12363 | if (hw_after > 0) | |
12364 | { | |
12365 | rtx_insn *insn; | |
12366 | ||
2d38d809 | 12367 | /* Insert NOPs for hotpatching. */ |
f8af0e30 DV |
12368 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) |
12369 | { | |
12370 | if (NOTE_P (insn) && NOTE_KIND (insn) == NOTE_INSN_FUNCTION_BEG) | |
12371 | break; | |
12372 | } | |
12373 | gcc_assert (insn); | |
12374 | /* Output a series of NOPs after the NOTE_INSN_FUNCTION_BEG. */ | |
12375 | while (hw_after > 0) | |
12376 | { | |
12377 | if (hw_after >= 3 && TARGET_CPU_ZARCH) | |
12378 | { | |
12379 | insn = emit_insn_after (gen_nop_6_byte (), insn); | |
12380 | hw_after -= 3; | |
12381 | } | |
12382 | else if (hw_after >= 2) | |
12383 | { | |
12384 | insn = emit_insn_after (gen_nop_4_byte (), insn); | |
12385 | hw_after -= 2; | |
12386 | } | |
12387 | else | |
12388 | { | |
12389 | insn = emit_insn_after (gen_nop_2_byte (), insn); | |
12390 | hw_after -= 1; | |
12391 | } | |
12392 | } | |
12393 | gcc_assert (hw_after == 0); | |
12394 | } | |
ab96de7e | 12395 | } |
ed9676cf | 12396 | |
3a892e44 AK |
12397 | /* Return true if INSN is a fp load insn writing register REGNO. */ |
12398 | static inline bool | |
647d790d | 12399 | s390_fpload_toreg (rtx_insn *insn, unsigned int regno) |
3a892e44 AK |
12400 | { |
12401 | rtx set; | |
12402 | enum attr_type flag = s390_safe_attr_type (insn); | |
12403 | ||
12404 | if (flag != TYPE_FLOADSF && flag != TYPE_FLOADDF) | |
12405 | return false; | |
12406 | ||
12407 | set = single_set (insn); | |
12408 | ||
12409 | if (set == NULL_RTX) | |
12410 | return false; | |
12411 | ||
12412 | if (!REG_P (SET_DEST (set)) || !MEM_P (SET_SRC (set))) | |
12413 | return false; | |
12414 | ||
12415 | if (REGNO (SET_DEST (set)) != regno) | |
12416 | return false; | |
12417 | ||
12418 | return true; | |
12419 | } | |
12420 | ||
12421 | /* This value describes the distance to be avoided between an | |
12422 | aritmetic fp instruction and an fp load writing the same register. | |
12423 | Z10_EARLYLOAD_DISTANCE - 1 as well as Z10_EARLYLOAD_DISTANCE + 1 is | |
12424 | fine but the exact value has to be avoided. Otherwise the FP | |
12425 | pipeline will throw an exception causing a major penalty. */ | |
12426 | #define Z10_EARLYLOAD_DISTANCE 7 | |
12427 | ||
12428 | /* Rearrange the ready list in order to avoid the situation described | |
12429 | for Z10_EARLYLOAD_DISTANCE. A problematic load instruction is | |
12430 | moved to the very end of the ready list. */ | |
12431 | static void | |
ce1ce33a | 12432 | s390_z10_prevent_earlyload_conflicts (rtx_insn **ready, int *nready_p) |
3a892e44 AK |
12433 | { |
12434 | unsigned int regno; | |
12435 | int nready = *nready_p; | |
ce1ce33a | 12436 | rtx_insn *tmp; |
3a892e44 | 12437 | int i; |
775c43d3 | 12438 | rtx_insn *insn; |
3a892e44 AK |
12439 | rtx set; |
12440 | enum attr_type flag; | |
12441 | int distance; | |
12442 | ||
12443 | /* Skip DISTANCE - 1 active insns. */ | |
12444 | for (insn = last_scheduled_insn, distance = Z10_EARLYLOAD_DISTANCE - 1; | |
12445 | distance > 0 && insn != NULL_RTX; | |
12446 | distance--, insn = prev_active_insn (insn)) | |
12447 | if (CALL_P (insn) || JUMP_P (insn)) | |
12448 | return; | |
12449 | ||
12450 | if (insn == NULL_RTX) | |
12451 | return; | |
12452 | ||
12453 | set = single_set (insn); | |
12454 | ||
12455 | if (set == NULL_RTX || !REG_P (SET_DEST (set)) | |
12456 | || GET_MODE_CLASS (GET_MODE (SET_DEST (set))) != MODE_FLOAT) | |
12457 | return; | |
12458 | ||
12459 | flag = s390_safe_attr_type (insn); | |
12460 | ||
12461 | if (flag == TYPE_FLOADSF || flag == TYPE_FLOADDF) | |
12462 | return; | |
12463 | ||
12464 | regno = REGNO (SET_DEST (set)); | |
12465 | i = nready - 1; | |
12466 | ||
12467 | while (!s390_fpload_toreg (ready[i], regno) && i > 0) | |
12468 | i--; | |
12469 | ||
12470 | if (!i) | |
12471 | return; | |
12472 | ||
12473 | tmp = ready[i]; | |
ce1ce33a | 12474 | memmove (&ready[1], &ready[0], sizeof (rtx_insn *) * i); |
3a892e44 AK |
12475 | ready[0] = tmp; |
12476 | } | |
12477 | ||
22ac2c2f AK |
12478 | |
12479 | /* The s390_sched_state variable tracks the state of the current or | |
12480 | the last instruction group. | |
12481 | ||
12482 | 0,1,2 number of instructions scheduled in the current group | |
12483 | 3 the last group is complete - normal insns | |
12484 | 4 the last group was a cracked/expanded insn */ | |
12485 | ||
12486 | static int s390_sched_state; | |
12487 | ||
12488 | #define S390_OOO_SCHED_STATE_NORMAL 3 | |
12489 | #define S390_OOO_SCHED_STATE_CRACKED 4 | |
12490 | ||
12491 | #define S390_OOO_SCHED_ATTR_MASK_CRACKED 0x1 | |
12492 | #define S390_OOO_SCHED_ATTR_MASK_EXPANDED 0x2 | |
12493 | #define S390_OOO_SCHED_ATTR_MASK_ENDGROUP 0x4 | |
12494 | #define S390_OOO_SCHED_ATTR_MASK_GROUPALONE 0x8 | |
12495 | ||
12496 | static unsigned int | |
84034c69 | 12497 | s390_get_sched_attrmask (rtx_insn *insn) |
22ac2c2f AK |
12498 | { |
12499 | unsigned int mask = 0; | |
12500 | ||
12501 | if (get_attr_ooo_cracked (insn)) | |
12502 | mask |= S390_OOO_SCHED_ATTR_MASK_CRACKED; | |
12503 | if (get_attr_ooo_expanded (insn)) | |
12504 | mask |= S390_OOO_SCHED_ATTR_MASK_EXPANDED; | |
12505 | if (get_attr_ooo_endgroup (insn)) | |
12506 | mask |= S390_OOO_SCHED_ATTR_MASK_ENDGROUP; | |
12507 | if (get_attr_ooo_groupalone (insn)) | |
12508 | mask |= S390_OOO_SCHED_ATTR_MASK_GROUPALONE; | |
12509 | return mask; | |
12510 | } | |
12511 | ||
12512 | /* Return the scheduling score for INSN. The higher the score the | |
12513 | better. The score is calculated from the OOO scheduling attributes | |
12514 | of INSN and the scheduling state s390_sched_state. */ | |
12515 | static int | |
84034c69 | 12516 | s390_sched_score (rtx_insn *insn) |
22ac2c2f AK |
12517 | { |
12518 | unsigned int mask = s390_get_sched_attrmask (insn); | |
12519 | int score = 0; | |
12520 | ||
12521 | switch (s390_sched_state) | |
12522 | { | |
12523 | case 0: | |
12524 | /* Try to put insns into the first slot which would otherwise | |
12525 | break a group. */ | |
12526 | if ((mask & S390_OOO_SCHED_ATTR_MASK_CRACKED) != 0 | |
12527 | || (mask & S390_OOO_SCHED_ATTR_MASK_EXPANDED) != 0) | |
12528 | score += 5; | |
12529 | if ((mask & S390_OOO_SCHED_ATTR_MASK_GROUPALONE) != 0) | |
12530 | score += 10; | |
12531 | case 1: | |
12532 | /* Prefer not cracked insns while trying to put together a | |
12533 | group. */ | |
12534 | if ((mask & S390_OOO_SCHED_ATTR_MASK_CRACKED) == 0 | |
12535 | && (mask & S390_OOO_SCHED_ATTR_MASK_EXPANDED) == 0 | |
12536 | && (mask & S390_OOO_SCHED_ATTR_MASK_GROUPALONE) == 0) | |
12537 | score += 10; | |
12538 | if ((mask & S390_OOO_SCHED_ATTR_MASK_ENDGROUP) == 0) | |
12539 | score += 5; | |
12540 | break; | |
12541 | case 2: | |
12542 | /* Prefer not cracked insns while trying to put together a | |
12543 | group. */ | |
12544 | if ((mask & S390_OOO_SCHED_ATTR_MASK_CRACKED) == 0 | |
12545 | && (mask & S390_OOO_SCHED_ATTR_MASK_EXPANDED) == 0 | |
12546 | && (mask & S390_OOO_SCHED_ATTR_MASK_GROUPALONE) == 0) | |
12547 | score += 10; | |
12548 | /* Prefer endgroup insns in the last slot. */ | |
12549 | if ((mask & S390_OOO_SCHED_ATTR_MASK_ENDGROUP) != 0) | |
12550 | score += 10; | |
12551 | break; | |
12552 | case S390_OOO_SCHED_STATE_NORMAL: | |
12553 | /* Prefer not cracked insns if the last was not cracked. */ | |
12554 | if ((mask & S390_OOO_SCHED_ATTR_MASK_CRACKED) == 0 | |
12555 | && (mask & S390_OOO_SCHED_ATTR_MASK_EXPANDED) == 0) | |
12556 | score += 5; | |
12557 | if ((mask & S390_OOO_SCHED_ATTR_MASK_GROUPALONE) != 0) | |
12558 | score += 10; | |
12559 | break; | |
12560 | case S390_OOO_SCHED_STATE_CRACKED: | |
12561 | /* Try to keep cracked insns together to prevent them from | |
12562 | interrupting groups. */ | |
12563 | if ((mask & S390_OOO_SCHED_ATTR_MASK_CRACKED) != 0 | |
12564 | || (mask & S390_OOO_SCHED_ATTR_MASK_EXPANDED) != 0) | |
12565 | score += 5; | |
12566 | break; | |
12567 | } | |
12568 | return score; | |
12569 | } | |
12570 | ||
3a892e44 | 12571 | /* This function is called via hook TARGET_SCHED_REORDER before |
631b20a7 | 12572 | issuing one insn from list READY which contains *NREADYP entries. |
3a892e44 AK |
12573 | For target z10 it reorders load instructions to avoid early load |
12574 | conflicts in the floating point pipeline */ | |
12575 | static int | |
22ac2c2f | 12576 | s390_sched_reorder (FILE *file, int verbose, |
ce1ce33a | 12577 | rtx_insn **ready, int *nreadyp, int clock ATTRIBUTE_UNUSED) |
3a892e44 AK |
12578 | { |
12579 | if (s390_tune == PROCESSOR_2097_Z10) | |
12580 | if (reload_completed && *nreadyp > 1) | |
12581 | s390_z10_prevent_earlyload_conflicts (ready, nreadyp); | |
12582 | ||
55ac540c AK |
12583 | if ((s390_tune == PROCESSOR_2827_ZEC12 |
12584 | || s390_tune == PROCESSOR_2964_Z13) | |
22ac2c2f AK |
12585 | && reload_completed |
12586 | && *nreadyp > 1) | |
12587 | { | |
12588 | int i; | |
12589 | int last_index = *nreadyp - 1; | |
12590 | int max_index = -1; | |
12591 | int max_score = -1; | |
ce1ce33a | 12592 | rtx_insn *tmp; |
22ac2c2f AK |
12593 | |
12594 | /* Just move the insn with the highest score to the top (the | |
12595 | end) of the list. A full sort is not needed since a conflict | |
12596 | in the hazard recognition cannot happen. So the top insn in | |
12597 | the ready list will always be taken. */ | |
12598 | for (i = last_index; i >= 0; i--) | |
12599 | { | |
12600 | int score; | |
12601 | ||
12602 | if (recog_memoized (ready[i]) < 0) | |
12603 | continue; | |
12604 | ||
12605 | score = s390_sched_score (ready[i]); | |
12606 | if (score > max_score) | |
12607 | { | |
12608 | max_score = score; | |
12609 | max_index = i; | |
12610 | } | |
12611 | } | |
12612 | ||
12613 | if (max_index != -1) | |
12614 | { | |
12615 | if (max_index != last_index) | |
12616 | { | |
12617 | tmp = ready[max_index]; | |
12618 | ready[max_index] = ready[last_index]; | |
12619 | ready[last_index] = tmp; | |
12620 | ||
12621 | if (verbose > 5) | |
12622 | fprintf (file, | |
12623 | "move insn %d to the top of list\n", | |
12624 | INSN_UID (ready[last_index])); | |
12625 | } | |
12626 | else if (verbose > 5) | |
12627 | fprintf (file, | |
12628 | "best insn %d already on top\n", | |
12629 | INSN_UID (ready[last_index])); | |
12630 | } | |
12631 | ||
12632 | if (verbose > 5) | |
12633 | { | |
12634 | fprintf (file, "ready list ooo attributes - sched state: %d\n", | |
12635 | s390_sched_state); | |
12636 | ||
12637 | for (i = last_index; i >= 0; i--) | |
12638 | { | |
12639 | if (recog_memoized (ready[i]) < 0) | |
12640 | continue; | |
12641 | fprintf (file, "insn %d score: %d: ", INSN_UID (ready[i]), | |
12642 | s390_sched_score (ready[i])); | |
12643 | #define PRINT_OOO_ATTR(ATTR) fprintf (file, "%s ", get_attr_##ATTR (ready[i]) ? #ATTR : "!" #ATTR); | |
12644 | PRINT_OOO_ATTR (ooo_cracked); | |
12645 | PRINT_OOO_ATTR (ooo_expanded); | |
12646 | PRINT_OOO_ATTR (ooo_endgroup); | |
12647 | PRINT_OOO_ATTR (ooo_groupalone); | |
12648 | #undef PRINT_OOO_ATTR | |
12649 | fprintf (file, "\n"); | |
12650 | } | |
12651 | } | |
12652 | } | |
12653 | ||
3a892e44 AK |
12654 | return s390_issue_rate (); |
12655 | } | |
12656 | ||
22ac2c2f | 12657 | |
3a892e44 AK |
12658 | /* This function is called via hook TARGET_SCHED_VARIABLE_ISSUE after |
12659 | the scheduler has issued INSN. It stores the last issued insn into | |
12660 | last_scheduled_insn in order to make it available for | |
12661 | s390_sched_reorder. */ | |
12662 | static int | |
ac44248e | 12663 | s390_sched_variable_issue (FILE *file, int verbose, rtx_insn *insn, int more) |
3a892e44 AK |
12664 | { |
12665 | last_scheduled_insn = insn; | |
12666 | ||
55ac540c AK |
12667 | if ((s390_tune == PROCESSOR_2827_ZEC12 |
12668 | || s390_tune == PROCESSOR_2964_Z13) | |
22ac2c2f AK |
12669 | && reload_completed |
12670 | && recog_memoized (insn) >= 0) | |
12671 | { | |
12672 | unsigned int mask = s390_get_sched_attrmask (insn); | |
12673 | ||
12674 | if ((mask & S390_OOO_SCHED_ATTR_MASK_CRACKED) != 0 | |
12675 | || (mask & S390_OOO_SCHED_ATTR_MASK_EXPANDED) != 0) | |
12676 | s390_sched_state = S390_OOO_SCHED_STATE_CRACKED; | |
12677 | else if ((mask & S390_OOO_SCHED_ATTR_MASK_ENDGROUP) != 0 | |
12678 | || (mask & S390_OOO_SCHED_ATTR_MASK_GROUPALONE) != 0) | |
12679 | s390_sched_state = S390_OOO_SCHED_STATE_NORMAL; | |
12680 | else | |
12681 | { | |
12682 | /* Only normal insns are left (mask == 0). */ | |
12683 | switch (s390_sched_state) | |
12684 | { | |
12685 | case 0: | |
12686 | case 1: | |
12687 | case 2: | |
12688 | case S390_OOO_SCHED_STATE_NORMAL: | |
12689 | if (s390_sched_state == S390_OOO_SCHED_STATE_NORMAL) | |
12690 | s390_sched_state = 1; | |
12691 | else | |
12692 | s390_sched_state++; | |
12693 | ||
12694 | break; | |
12695 | case S390_OOO_SCHED_STATE_CRACKED: | |
12696 | s390_sched_state = S390_OOO_SCHED_STATE_NORMAL; | |
12697 | break; | |
12698 | } | |
12699 | } | |
12700 | if (verbose > 5) | |
12701 | { | |
12702 | fprintf (file, "insn %d: ", INSN_UID (insn)); | |
12703 | #define PRINT_OOO_ATTR(ATTR) \ | |
12704 | fprintf (file, "%s ", get_attr_##ATTR (insn) ? #ATTR : ""); | |
12705 | PRINT_OOO_ATTR (ooo_cracked); | |
12706 | PRINT_OOO_ATTR (ooo_expanded); | |
12707 | PRINT_OOO_ATTR (ooo_endgroup); | |
12708 | PRINT_OOO_ATTR (ooo_groupalone); | |
12709 | #undef PRINT_OOO_ATTR | |
12710 | fprintf (file, "\n"); | |
12711 | fprintf (file, "sched state: %d\n", s390_sched_state); | |
12712 | } | |
12713 | } | |
12714 | ||
3a892e44 AK |
12715 | if (GET_CODE (PATTERN (insn)) != USE |
12716 | && GET_CODE (PATTERN (insn)) != CLOBBER) | |
12717 | return more - 1; | |
12718 | else | |
12719 | return more; | |
12720 | } | |
ed9676cf | 12721 | |
244e6c5c AK |
12722 | static void |
12723 | s390_sched_init (FILE *file ATTRIBUTE_UNUSED, | |
12724 | int verbose ATTRIBUTE_UNUSED, | |
12725 | int max_ready ATTRIBUTE_UNUSED) | |
12726 | { | |
775c43d3 | 12727 | last_scheduled_insn = NULL; |
22ac2c2f | 12728 | s390_sched_state = 0; |
244e6c5c AK |
12729 | } |
12730 | ||
40ac4f73 | 12731 | /* This target hook implementation for TARGET_LOOP_UNROLL_ADJUST calculates |
65b1d8ea AK |
12732 | a new number struct loop *loop should be unrolled if tuned for cpus with |
12733 | a built-in stride prefetcher. | |
12734 | The loop is analyzed for memory accesses by calling check_dpu for | |
40ac4f73 CB |
12735 | each rtx of the loop. Depending on the loop_depth and the amount of |
12736 | memory accesses a new number <=nunroll is returned to improve the | |
12737 | behaviour of the hardware prefetch unit. */ | |
12738 | static unsigned | |
12739 | s390_loop_unroll_adjust (unsigned nunroll, struct loop *loop) | |
12740 | { | |
12741 | basic_block *bbs; | |
775c43d3 | 12742 | rtx_insn *insn; |
40ac4f73 CB |
12743 | unsigned i; |
12744 | unsigned mem_count = 0; | |
12745 | ||
22ac2c2f AK |
12746 | if (s390_tune != PROCESSOR_2097_Z10 |
12747 | && s390_tune != PROCESSOR_2817_Z196 | |
55ac540c AK |
12748 | && s390_tune != PROCESSOR_2827_ZEC12 |
12749 | && s390_tune != PROCESSOR_2964_Z13) | |
40ac4f73 CB |
12750 | return nunroll; |
12751 | ||
12752 | /* Count the number of memory references within the loop body. */ | |
12753 | bbs = get_loop_body (loop); | |
9dc7a9da | 12754 | subrtx_iterator::array_type array; |
40ac4f73 | 12755 | for (i = 0; i < loop->num_nodes; i++) |
9dc7a9da RS |
12756 | FOR_BB_INSNS (bbs[i], insn) |
12757 | if (INSN_P (insn) && INSN_CODE (insn) != -1) | |
12758 | FOR_EACH_SUBRTX (iter, array, PATTERN (insn), NONCONST) | |
12759 | if (MEM_P (*iter)) | |
12760 | mem_count += 1; | |
40ac4f73 CB |
12761 | free (bbs); |
12762 | ||
12763 | /* Prevent division by zero, and we do not need to adjust nunroll in this case. */ | |
12764 | if (mem_count == 0) | |
12765 | return nunroll; | |
12766 | ||
12767 | switch (loop_depth(loop)) | |
12768 | { | |
12769 | case 1: | |
12770 | return MIN (nunroll, 28 / mem_count); | |
12771 | case 2: | |
12772 | return MIN (nunroll, 22 / mem_count); | |
12773 | default: | |
12774 | return MIN (nunroll, 16 / mem_count); | |
12775 | } | |
12776 | } | |
12777 | ||
4099494d RS |
12778 | static void |
12779 | s390_option_override (void) | |
12780 | { | |
12781 | unsigned int i; | |
12782 | cl_deferred_option *opt; | |
12783 | vec<cl_deferred_option> *v = | |
12784 | (vec<cl_deferred_option> *) s390_deferred_options; | |
12785 | ||
12786 | if (v) | |
12787 | FOR_EACH_VEC_ELT (*v, i, opt) | |
12788 | { | |
12789 | switch (opt->opt_index) | |
12790 | { | |
4099494d RS |
12791 | case OPT_mhotpatch_: |
12792 | { | |
94091f43 DV |
12793 | int val1; |
12794 | int val2; | |
12795 | char s[256]; | |
12796 | char *t; | |
12797 | ||
12798 | strncpy (s, opt->arg, 256); | |
12799 | s[255] = 0; | |
12800 | t = strchr (s, ','); | |
12801 | if (t != NULL) | |
12802 | { | |
12803 | *t = 0; | |
12804 | t++; | |
12805 | val1 = integral_argument (s); | |
12806 | val2 = integral_argument (t); | |
12807 | } | |
12808 | else | |
12809 | { | |
12810 | val1 = -1; | |
12811 | val2 = -1; | |
12812 | } | |
12813 | if (val1 == -1 || val2 == -1) | |
4099494d RS |
12814 | { |
12815 | /* argument is not a plain number */ | |
94091f43 DV |
12816 | error ("arguments to %qs should be non-negative integers", |
12817 | "-mhotpatch=n,m"); | |
4099494d RS |
12818 | break; |
12819 | } | |
94091f43 DV |
12820 | else if (val1 > s390_hotpatch_hw_max |
12821 | || val2 > s390_hotpatch_hw_max) | |
4099494d RS |
12822 | { |
12823 | error ("argument to %qs is too large (max. %d)", | |
94091f43 | 12824 | "-mhotpatch=n,m", s390_hotpatch_hw_max); |
4099494d RS |
12825 | break; |
12826 | } | |
94091f43 DV |
12827 | s390_hotpatch_hw_before_label = val1; |
12828 | s390_hotpatch_hw_after_label = val2; | |
4099494d RS |
12829 | break; |
12830 | } | |
12831 | default: | |
12832 | gcc_unreachable (); | |
12833 | } | |
12834 | } | |
12835 | ||
12836 | /* Set up function hooks. */ | |
12837 | init_machine_status = s390_init_machine_status; | |
12838 | ||
12839 | /* Architecture mode defaults according to ABI. */ | |
12840 | if (!(target_flags_explicit & MASK_ZARCH)) | |
12841 | { | |
12842 | if (TARGET_64BIT) | |
12843 | target_flags |= MASK_ZARCH; | |
12844 | else | |
12845 | target_flags &= ~MASK_ZARCH; | |
12846 | } | |
12847 | ||
12848 | /* Set the march default in case it hasn't been specified on | |
12849 | cmdline. */ | |
12850 | if (s390_arch == PROCESSOR_max) | |
12851 | { | |
12852 | s390_arch_string = TARGET_ZARCH? "z900" : "g5"; | |
12853 | s390_arch = TARGET_ZARCH ? PROCESSOR_2064_Z900 : PROCESSOR_9672_G5; | |
12854 | s390_arch_flags = processor_flags_table[(int)s390_arch]; | |
12855 | } | |
12856 | ||
12857 | /* Determine processor to tune for. */ | |
12858 | if (s390_tune == PROCESSOR_max) | |
12859 | { | |
12860 | s390_tune = s390_arch; | |
12861 | s390_tune_flags = s390_arch_flags; | |
12862 | } | |
12863 | ||
12864 | /* Sanity checks. */ | |
12865 | if (TARGET_ZARCH && !TARGET_CPU_ZARCH) | |
12866 | error ("z/Architecture mode not supported on %s", s390_arch_string); | |
12867 | if (TARGET_64BIT && !TARGET_ZARCH) | |
12868 | error ("64-bit ABI not supported in ESA/390 mode"); | |
12869 | ||
12870 | /* Use hardware DFP if available and not explicitly disabled by | |
12871 | user. E.g. with -m31 -march=z10 -mzarch */ | |
12872 | if (!(target_flags_explicit & MASK_HARD_DFP) && TARGET_DFP) | |
12873 | target_flags |= MASK_HARD_DFP; | |
12874 | ||
12875 | /* Enable hardware transactions if available and not explicitly | |
12876 | disabled by user. E.g. with -m31 -march=zEC12 -mzarch */ | |
12877 | if (!(target_flags_explicit & MASK_OPT_HTM) && TARGET_CPU_HTM && TARGET_ZARCH) | |
12878 | target_flags |= MASK_OPT_HTM; | |
12879 | ||
55ac540c AK |
12880 | if (target_flags_explicit & MASK_OPT_VX) |
12881 | { | |
12882 | if (TARGET_OPT_VX) | |
12883 | { | |
12884 | if (!TARGET_CPU_VX) | |
12885 | error ("hardware vector support not available on %s", | |
12886 | s390_arch_string); | |
12887 | if (TARGET_SOFT_FLOAT) | |
12888 | error ("hardware vector support not available with -msoft-float"); | |
12889 | } | |
12890 | } | |
12891 | else if (TARGET_CPU_VX) | |
12892 | /* Enable vector support if available and not explicitly disabled | |
12893 | by user. E.g. with -m31 -march=z13 -mzarch */ | |
12894 | target_flags |= MASK_OPT_VX; | |
12895 | ||
4099494d RS |
12896 | if (TARGET_HARD_DFP && !TARGET_DFP) |
12897 | { | |
12898 | if (target_flags_explicit & MASK_HARD_DFP) | |
12899 | { | |
12900 | if (!TARGET_CPU_DFP) | |
12901 | error ("hardware decimal floating point instructions" | |
12902 | " not available on %s", s390_arch_string); | |
12903 | if (!TARGET_ZARCH) | |
12904 | error ("hardware decimal floating point instructions" | |
12905 | " not available in ESA/390 mode"); | |
12906 | } | |
12907 | else | |
12908 | target_flags &= ~MASK_HARD_DFP; | |
12909 | } | |
12910 | ||
12911 | if ((target_flags_explicit & MASK_SOFT_FLOAT) && TARGET_SOFT_FLOAT) | |
12912 | { | |
12913 | if ((target_flags_explicit & MASK_HARD_DFP) && TARGET_HARD_DFP) | |
12914 | error ("-mhard-dfp can%'t be used in conjunction with -msoft-float"); | |
12915 | ||
12916 | target_flags &= ~MASK_HARD_DFP; | |
12917 | } | |
12918 | ||
12919 | /* Set processor cost function. */ | |
12920 | switch (s390_tune) | |
12921 | { | |
12922 | case PROCESSOR_2084_Z990: | |
12923 | s390_cost = &z990_cost; | |
12924 | break; | |
12925 | case PROCESSOR_2094_Z9_109: | |
12926 | s390_cost = &z9_109_cost; | |
12927 | break; | |
12928 | case PROCESSOR_2097_Z10: | |
12929 | s390_cost = &z10_cost; | |
12930 | break; | |
12931 | case PROCESSOR_2817_Z196: | |
12932 | s390_cost = &z196_cost; | |
12933 | break; | |
12934 | case PROCESSOR_2827_ZEC12: | |
55ac540c | 12935 | case PROCESSOR_2964_Z13: |
4099494d RS |
12936 | s390_cost = &zEC12_cost; |
12937 | break; | |
12938 | default: | |
12939 | s390_cost = &z900_cost; | |
12940 | } | |
12941 | ||
12942 | if (TARGET_BACKCHAIN && TARGET_PACKED_STACK && TARGET_HARD_FLOAT) | |
12943 | error ("-mbackchain -mpacked-stack -mhard-float are not supported " | |
12944 | "in combination"); | |
12945 | ||
12946 | if (s390_stack_size) | |
12947 | { | |
12948 | if (s390_stack_guard >= s390_stack_size) | |
12949 | error ("stack size must be greater than the stack guard value"); | |
12950 | else if (s390_stack_size > 1 << 16) | |
12951 | error ("stack size must not be greater than 64k"); | |
12952 | } | |
12953 | else if (s390_stack_guard) | |
12954 | error ("-mstack-guard implies use of -mstack-size"); | |
12955 | ||
12956 | #ifdef TARGET_DEFAULT_LONG_DOUBLE_128 | |
12957 | if (!(target_flags_explicit & MASK_LONG_DOUBLE_128)) | |
12958 | target_flags |= MASK_LONG_DOUBLE_128; | |
12959 | #endif | |
12960 | ||
12961 | if (s390_tune == PROCESSOR_2097_Z10 | |
12962 | || s390_tune == PROCESSOR_2817_Z196 | |
55ac540c AK |
12963 | || s390_tune == PROCESSOR_2827_ZEC12 |
12964 | || s390_tune == PROCESSOR_2964_Z13) | |
4099494d RS |
12965 | { |
12966 | maybe_set_param_value (PARAM_MAX_UNROLLED_INSNS, 100, | |
12967 | global_options.x_param_values, | |
12968 | global_options_set.x_param_values); | |
12969 | maybe_set_param_value (PARAM_MAX_UNROLL_TIMES, 32, | |
12970 | global_options.x_param_values, | |
12971 | global_options_set.x_param_values); | |
12972 | maybe_set_param_value (PARAM_MAX_COMPLETELY_PEELED_INSNS, 2000, | |
12973 | global_options.x_param_values, | |
12974 | global_options_set.x_param_values); | |
12975 | maybe_set_param_value (PARAM_MAX_COMPLETELY_PEEL_TIMES, 64, | |
12976 | global_options.x_param_values, | |
12977 | global_options_set.x_param_values); | |
12978 | } | |
12979 | ||
12980 | maybe_set_param_value (PARAM_MAX_PENDING_LIST_LENGTH, 256, | |
12981 | global_options.x_param_values, | |
12982 | global_options_set.x_param_values); | |
12983 | /* values for loop prefetching */ | |
12984 | maybe_set_param_value (PARAM_L1_CACHE_LINE_SIZE, 256, | |
12985 | global_options.x_param_values, | |
12986 | global_options_set.x_param_values); | |
12987 | maybe_set_param_value (PARAM_L1_CACHE_SIZE, 128, | |
12988 | global_options.x_param_values, | |
12989 | global_options_set.x_param_values); | |
12990 | /* s390 has more than 2 levels and the size is much larger. Since | |
12991 | we are always running virtualized assume that we only get a small | |
12992 | part of the caches above l1. */ | |
12993 | maybe_set_param_value (PARAM_L2_CACHE_SIZE, 1500, | |
12994 | global_options.x_param_values, | |
12995 | global_options_set.x_param_values); | |
12996 | maybe_set_param_value (PARAM_PREFETCH_MIN_INSN_TO_MEM_RATIO, 2, | |
12997 | global_options.x_param_values, | |
12998 | global_options_set.x_param_values); | |
12999 | maybe_set_param_value (PARAM_SIMULTANEOUS_PREFETCHES, 6, | |
13000 | global_options.x_param_values, | |
13001 | global_options_set.x_param_values); | |
13002 | ||
13003 | /* This cannot reside in s390_option_optimization_table since HAVE_prefetch | |
13004 | requires the arch flags to be evaluated already. Since prefetching | |
13005 | is beneficial on s390, we enable it if available. */ | |
13006 | if (flag_prefetch_loop_arrays < 0 && HAVE_prefetch && optimize >= 3) | |
13007 | flag_prefetch_loop_arrays = 1; | |
13008 | ||
13009 | /* Use the alternative scheduling-pressure algorithm by default. */ | |
13010 | maybe_set_param_value (PARAM_SCHED_PRESSURE_ALGORITHM, 2, | |
13011 | global_options.x_param_values, | |
13012 | global_options_set.x_param_values); | |
13013 | ||
13014 | if (TARGET_TPF) | |
13015 | { | |
13016 | /* Don't emit DWARF3/4 unless specifically selected. The TPF | |
13017 | debuggers do not yet support DWARF 3/4. */ | |
13018 | if (!global_options_set.x_dwarf_strict) | |
13019 | dwarf_strict = 1; | |
13020 | if (!global_options_set.x_dwarf_version) | |
13021 | dwarf_version = 2; | |
13022 | } | |
13023 | ||
13024 | /* Register a target-specific optimization-and-lowering pass | |
13025 | to run immediately before prologue and epilogue generation. | |
13026 | ||
13027 | Registering the pass must be done at start up. It's | |
13028 | convenient to do it here. */ | |
13029 | opt_pass *new_pass = new pass_s390_early_mach (g); | |
13030 | struct register_pass_info insert_pass_s390_early_mach = | |
13031 | { | |
13032 | new_pass, /* pass */ | |
13033 | "pro_and_epilogue", /* reference_pass_name */ | |
13034 | 1, /* ref_pass_instance_number */ | |
13035 | PASS_POS_INSERT_BEFORE /* po_op */ | |
13036 | }; | |
13037 | register_pass (&insert_pass_s390_early_mach); | |
13038 | } | |
13039 | ||
b5e3200c JG |
13040 | /* Implement TARGET_USE_BY_PIECES_INFRASTRUCTURE_P. */ |
13041 | ||
13042 | static bool | |
445d7826 | 13043 | s390_use_by_pieces_infrastructure_p (unsigned HOST_WIDE_INT size, |
b5e3200c JG |
13044 | unsigned int align ATTRIBUTE_UNUSED, |
13045 | enum by_pieces_operation op ATTRIBUTE_UNUSED, | |
13046 | bool speed_p ATTRIBUTE_UNUSED) | |
13047 | { | |
13048 | return (size == 1 || size == 2 | |
13049 | || size == 4 || (TARGET_ZARCH && size == 8)); | |
13050 | } | |
13051 | ||
35bc11c3 AK |
13052 | /* Implement TARGET_ATOMIC_ASSIGN_EXPAND_FENV hook. */ |
13053 | ||
13054 | static void | |
13055 | s390_atomic_assign_expand_fenv (tree *hold, tree *clear, tree *update) | |
13056 | { | |
13057 | tree sfpc = s390_builtin_decls[S390_BUILTIN_S390_SFPC]; | |
13058 | tree efpc = s390_builtin_decls[S390_BUILTIN_S390_EFPC]; | |
13059 | tree call_efpc = build_call_expr (efpc, 0); | |
13060 | tree fenv_var = create_tmp_var (unsigned_type_node); | |
13061 | ||
13062 | #define FPC_EXCEPTION_MASK HOST_WIDE_INT_UC (0xf8000000) | |
13063 | #define FPC_FLAGS_MASK HOST_WIDE_INT_UC (0x00f80000) | |
13064 | #define FPC_DXC_MASK HOST_WIDE_INT_UC (0x0000ff00) | |
13065 | #define FPC_EXCEPTION_MASK_SHIFT HOST_WIDE_INT_UC (24) | |
13066 | #define FPC_FLAGS_SHIFT HOST_WIDE_INT_UC (16) | |
13067 | #define FPC_DXC_SHIFT HOST_WIDE_INT_UC (8) | |
13068 | ||
13069 | /* Generates the equivalent of feholdexcept (&fenv_var) | |
13070 | ||
13071 | fenv_var = __builtin_s390_efpc (); | |
13072 | __builtin_s390_sfpc (fenv_var & mask) */ | |
13073 | tree old_fpc = build2 (MODIFY_EXPR, unsigned_type_node, fenv_var, call_efpc); | |
13074 | tree new_fpc = | |
13075 | build2 (BIT_AND_EXPR, unsigned_type_node, fenv_var, | |
13076 | build_int_cst (unsigned_type_node, | |
13077 | ~(FPC_DXC_MASK | FPC_FLAGS_MASK | | |
13078 | FPC_EXCEPTION_MASK))); | |
13079 | tree set_new_fpc = build_call_expr (sfpc, 1, new_fpc); | |
13080 | *hold = build2 (COMPOUND_EXPR, void_type_node, old_fpc, set_new_fpc); | |
13081 | ||
13082 | /* Generates the equivalent of feclearexcept (FE_ALL_EXCEPT) | |
13083 | ||
13084 | __builtin_s390_sfpc (__builtin_s390_efpc () & mask) */ | |
13085 | new_fpc = build2 (BIT_AND_EXPR, unsigned_type_node, call_efpc, | |
13086 | build_int_cst (unsigned_type_node, | |
13087 | ~(FPC_DXC_MASK | FPC_FLAGS_MASK))); | |
13088 | *clear = build_call_expr (sfpc, 1, new_fpc); | |
13089 | ||
13090 | /* Generates the equivalent of feupdateenv (fenv_var) | |
13091 | ||
13092 | old_fpc = __builtin_s390_efpc (); | |
13093 | __builtin_s390_sfpc (fenv_var); | |
13094 | __atomic_feraiseexcept ((old_fpc & FPC_FLAGS_MASK) >> FPC_FLAGS_SHIFT); */ | |
13095 | ||
13096 | old_fpc = create_tmp_var (unsigned_type_node); | |
13097 | tree store_old_fpc = build2 (MODIFY_EXPR, void_type_node, | |
13098 | old_fpc, call_efpc); | |
13099 | ||
13100 | set_new_fpc = build_call_expr (sfpc, 1, fenv_var); | |
13101 | ||
13102 | tree raise_old_except = build2 (BIT_AND_EXPR, unsigned_type_node, old_fpc, | |
13103 | build_int_cst (unsigned_type_node, | |
13104 | FPC_FLAGS_MASK)); | |
13105 | raise_old_except = build2 (RSHIFT_EXPR, unsigned_type_node, raise_old_except, | |
13106 | build_int_cst (unsigned_type_node, | |
13107 | FPC_FLAGS_SHIFT)); | |
13108 | tree atomic_feraiseexcept | |
13109 | = builtin_decl_implicit (BUILT_IN_ATOMIC_FERAISEEXCEPT); | |
13110 | raise_old_except = build_call_expr (atomic_feraiseexcept, | |
13111 | 1, raise_old_except); | |
13112 | ||
13113 | *update = build2 (COMPOUND_EXPR, void_type_node, | |
13114 | build2 (COMPOUND_EXPR, void_type_node, | |
13115 | store_old_fpc, set_new_fpc), | |
13116 | raise_old_except); | |
13117 | ||
13118 | #undef FPC_EXCEPTION_MASK | |
13119 | #undef FPC_FLAGS_MASK | |
13120 | #undef FPC_DXC_MASK | |
13121 | #undef FPC_EXCEPTION_MASK_SHIFT | |
13122 | #undef FPC_FLAGS_SHIFT | |
13123 | #undef FPC_DXC_SHIFT | |
13124 | } | |
13125 | ||
085261c8 AK |
13126 | /* Return the vector mode to be used for inner mode MODE when doing |
13127 | vectorization. */ | |
13128 | static machine_mode | |
13129 | s390_preferred_simd_mode (machine_mode mode) | |
13130 | { | |
13131 | if (TARGET_VX) | |
13132 | switch (mode) | |
13133 | { | |
13134 | case DFmode: | |
13135 | return V2DFmode; | |
13136 | case DImode: | |
13137 | return V2DImode; | |
13138 | case SImode: | |
13139 | return V4SImode; | |
13140 | case HImode: | |
13141 | return V8HImode; | |
13142 | case QImode: | |
13143 | return V16QImode; | |
13144 | default:; | |
13145 | } | |
13146 | return word_mode; | |
13147 | } | |
13148 | ||
13149 | /* Our hardware does not require vectors to be strictly aligned. */ | |
13150 | static bool | |
13151 | s390_support_vector_misalignment (machine_mode mode ATTRIBUTE_UNUSED, | |
13152 | const_tree type ATTRIBUTE_UNUSED, | |
13153 | int misalignment ATTRIBUTE_UNUSED, | |
13154 | bool is_packed ATTRIBUTE_UNUSED) | |
13155 | { | |
13156 | return true; | |
13157 | } | |
13158 | ||
13159 | /* The vector ABI requires vector types to be aligned on an 8 byte | |
13160 | boundary (our stack alignment). However, we allow this to be | |
13161 | overriden by the user, while this definitely breaks the ABI. */ | |
13162 | static HOST_WIDE_INT | |
13163 | s390_vector_alignment (const_tree type) | |
13164 | { | |
13165 | if (!TARGET_VX_ABI) | |
13166 | return default_vector_alignment (type); | |
13167 | ||
13168 | if (TYPE_USER_ALIGN (type)) | |
13169 | return TYPE_ALIGN (type); | |
13170 | ||
13171 | return MIN (64, tree_to_shwi (TYPE_SIZE (type))); | |
13172 | } | |
13173 | ||
13174 | ||
ab96de7e | 13175 | /* Initialize GCC target structure. */ |
38899e29 | 13176 | |
ab96de7e AS |
13177 | #undef TARGET_ASM_ALIGNED_HI_OP |
13178 | #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t" | |
13179 | #undef TARGET_ASM_ALIGNED_DI_OP | |
13180 | #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t" | |
13181 | #undef TARGET_ASM_INTEGER | |
13182 | #define TARGET_ASM_INTEGER s390_assemble_integer | |
ed9676cf | 13183 | |
ab96de7e AS |
13184 | #undef TARGET_ASM_OPEN_PAREN |
13185 | #define TARGET_ASM_OPEN_PAREN "" | |
38899e29 | 13186 | |
ab96de7e AS |
13187 | #undef TARGET_ASM_CLOSE_PAREN |
13188 | #define TARGET_ASM_CLOSE_PAREN "" | |
ed9676cf | 13189 | |
c5387660 JM |
13190 | #undef TARGET_OPTION_OVERRIDE |
13191 | #define TARGET_OPTION_OVERRIDE s390_option_override | |
13192 | ||
ab96de7e AS |
13193 | #undef TARGET_ENCODE_SECTION_INFO |
13194 | #define TARGET_ENCODE_SECTION_INFO s390_encode_section_info | |
ed9676cf | 13195 | |
9602b6a1 AK |
13196 | #undef TARGET_SCALAR_MODE_SUPPORTED_P |
13197 | #define TARGET_SCALAR_MODE_SUPPORTED_P s390_scalar_mode_supported_p | |
13198 | ||
ab96de7e AS |
13199 | #ifdef HAVE_AS_TLS |
13200 | #undef TARGET_HAVE_TLS | |
13201 | #define TARGET_HAVE_TLS true | |
13202 | #endif | |
13203 | #undef TARGET_CANNOT_FORCE_CONST_MEM | |
13204 | #define TARGET_CANNOT_FORCE_CONST_MEM s390_cannot_force_const_mem | |
ed9676cf | 13205 | |
ab96de7e AS |
13206 | #undef TARGET_DELEGITIMIZE_ADDRESS |
13207 | #define TARGET_DELEGITIMIZE_ADDRESS s390_delegitimize_address | |
ed9676cf | 13208 | |
506d7b68 PB |
13209 | #undef TARGET_LEGITIMIZE_ADDRESS |
13210 | #define TARGET_LEGITIMIZE_ADDRESS s390_legitimize_address | |
13211 | ||
ab96de7e AS |
13212 | #undef TARGET_RETURN_IN_MEMORY |
13213 | #define TARGET_RETURN_IN_MEMORY s390_return_in_memory | |
38899e29 | 13214 | |
5a3fe9b6 AK |
13215 | #undef TARGET_INIT_BUILTINS |
13216 | #define TARGET_INIT_BUILTINS s390_init_builtins | |
13217 | #undef TARGET_EXPAND_BUILTIN | |
13218 | #define TARGET_EXPAND_BUILTIN s390_expand_builtin | |
9b80b7bc AK |
13219 | #undef TARGET_BUILTIN_DECL |
13220 | #define TARGET_BUILTIN_DECL s390_builtin_decl | |
5a3fe9b6 | 13221 | |
0f8ab434 AS |
13222 | #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA |
13223 | #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA s390_output_addr_const_extra | |
13224 | ||
ab96de7e AS |
13225 | #undef TARGET_ASM_OUTPUT_MI_THUNK |
13226 | #define TARGET_ASM_OUTPUT_MI_THUNK s390_output_mi_thunk | |
13227 | #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK | |
3101faab | 13228 | #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true |
ed9676cf | 13229 | |
ab96de7e AS |
13230 | #undef TARGET_SCHED_ADJUST_PRIORITY |
13231 | #define TARGET_SCHED_ADJUST_PRIORITY s390_adjust_priority | |
13232 | #undef TARGET_SCHED_ISSUE_RATE | |
13233 | #define TARGET_SCHED_ISSUE_RATE s390_issue_rate | |
13234 | #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD | |
13235 | #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD s390_first_cycle_multipass_dfa_lookahead | |
38899e29 | 13236 | |
3a892e44 AK |
13237 | #undef TARGET_SCHED_VARIABLE_ISSUE |
13238 | #define TARGET_SCHED_VARIABLE_ISSUE s390_sched_variable_issue | |
13239 | #undef TARGET_SCHED_REORDER | |
13240 | #define TARGET_SCHED_REORDER s390_sched_reorder | |
244e6c5c AK |
13241 | #undef TARGET_SCHED_INIT |
13242 | #define TARGET_SCHED_INIT s390_sched_init | |
3a892e44 | 13243 | |
ab96de7e AS |
13244 | #undef TARGET_CANNOT_COPY_INSN_P |
13245 | #define TARGET_CANNOT_COPY_INSN_P s390_cannot_copy_insn_p | |
13246 | #undef TARGET_RTX_COSTS | |
13247 | #define TARGET_RTX_COSTS s390_rtx_costs | |
13248 | #undef TARGET_ADDRESS_COST | |
13249 | #define TARGET_ADDRESS_COST s390_address_cost | |
ccaed3ba AS |
13250 | #undef TARGET_REGISTER_MOVE_COST |
13251 | #define TARGET_REGISTER_MOVE_COST s390_register_move_cost | |
13252 | #undef TARGET_MEMORY_MOVE_COST | |
13253 | #define TARGET_MEMORY_MOVE_COST s390_memory_move_cost | |
38899e29 | 13254 | |
ab96de7e AS |
13255 | #undef TARGET_MACHINE_DEPENDENT_REORG |
13256 | #define TARGET_MACHINE_DEPENDENT_REORG s390_reorg | |
8a512b77 | 13257 | |
ab96de7e AS |
13258 | #undef TARGET_VALID_POINTER_MODE |
13259 | #define TARGET_VALID_POINTER_MODE s390_valid_pointer_mode | |
38899e29 | 13260 | |
ab96de7e AS |
13261 | #undef TARGET_BUILD_BUILTIN_VA_LIST |
13262 | #define TARGET_BUILD_BUILTIN_VA_LIST s390_build_builtin_va_list | |
d7bd8aeb JJ |
13263 | #undef TARGET_EXPAND_BUILTIN_VA_START |
13264 | #define TARGET_EXPAND_BUILTIN_VA_START s390_va_start | |
ab96de7e AS |
13265 | #undef TARGET_GIMPLIFY_VA_ARG_EXPR |
13266 | #define TARGET_GIMPLIFY_VA_ARG_EXPR s390_gimplify_va_arg | |
4798630c | 13267 | |
cde0f3fd PB |
13268 | #undef TARGET_PROMOTE_FUNCTION_MODE |
13269 | #define TARGET_PROMOTE_FUNCTION_MODE s390_promote_function_mode | |
ab96de7e AS |
13270 | #undef TARGET_PASS_BY_REFERENCE |
13271 | #define TARGET_PASS_BY_REFERENCE s390_pass_by_reference | |
4798630c | 13272 | |
ab96de7e AS |
13273 | #undef TARGET_FUNCTION_OK_FOR_SIBCALL |
13274 | #define TARGET_FUNCTION_OK_FOR_SIBCALL s390_function_ok_for_sibcall | |
3cb1da52 NF |
13275 | #undef TARGET_FUNCTION_ARG |
13276 | #define TARGET_FUNCTION_ARG s390_function_arg | |
13277 | #undef TARGET_FUNCTION_ARG_ADVANCE | |
13278 | #define TARGET_FUNCTION_ARG_ADVANCE s390_function_arg_advance | |
b46616fd AK |
13279 | #undef TARGET_FUNCTION_VALUE |
13280 | #define TARGET_FUNCTION_VALUE s390_function_value | |
13281 | #undef TARGET_LIBCALL_VALUE | |
13282 | #define TARGET_LIBCALL_VALUE s390_libcall_value | |
085261c8 AK |
13283 | #undef TARGET_STRICT_ARGUMENT_NAMING |
13284 | #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true | |
4798630c | 13285 | |
d56a43a0 AK |
13286 | #undef TARGET_KEEP_LEAF_WHEN_PROFILED |
13287 | #define TARGET_KEEP_LEAF_WHEN_PROFILED s390_keep_leaf_when_profiled | |
13288 | ||
ab96de7e AS |
13289 | #undef TARGET_FIXED_CONDITION_CODE_REGS |
13290 | #define TARGET_FIXED_CONDITION_CODE_REGS s390_fixed_condition_code_regs | |
4798630c | 13291 | |
ab96de7e AS |
13292 | #undef TARGET_CC_MODES_COMPATIBLE |
13293 | #define TARGET_CC_MODES_COMPATIBLE s390_cc_modes_compatible | |
4798630c | 13294 | |
e7e64a25 | 13295 | #undef TARGET_INVALID_WITHIN_DOLOOP |
ac44248e | 13296 | #define TARGET_INVALID_WITHIN_DOLOOP hook_constcharptr_const_rtx_insn_null |
c08b81aa | 13297 | |
fdbe66f2 EB |
13298 | #ifdef HAVE_AS_TLS |
13299 | #undef TARGET_ASM_OUTPUT_DWARF_DTPREL | |
13300 | #define TARGET_ASM_OUTPUT_DWARF_DTPREL s390_output_dwarf_dtprel | |
13301 | #endif | |
13302 | ||
085261c8 AK |
13303 | #undef TARGET_DWARF_FRAME_REG_MODE |
13304 | #define TARGET_DWARF_FRAME_REG_MODE s390_dwarf_frame_reg_mode | |
13305 | ||
7269aee7 | 13306 | #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING |
608063c3 JB |
13307 | #undef TARGET_MANGLE_TYPE |
13308 | #define TARGET_MANGLE_TYPE s390_mangle_type | |
7269aee7 AH |
13309 | #endif |
13310 | ||
4dc19cc0 AK |
13311 | #undef TARGET_SCALAR_MODE_SUPPORTED_P |
13312 | #define TARGET_SCALAR_MODE_SUPPORTED_P s390_scalar_mode_supported_p | |
13313 | ||
085261c8 AK |
13314 | #undef TARGET_VECTOR_MODE_SUPPORTED_P |
13315 | #define TARGET_VECTOR_MODE_SUPPORTED_P s390_vector_mode_supported_p | |
13316 | ||
5df97412 AS |
13317 | #undef TARGET_PREFERRED_RELOAD_CLASS |
13318 | #define TARGET_PREFERRED_RELOAD_CLASS s390_preferred_reload_class | |
13319 | ||
833cd70a AK |
13320 | #undef TARGET_SECONDARY_RELOAD |
13321 | #define TARGET_SECONDARY_RELOAD s390_secondary_reload | |
13322 | ||
c7ff6e7a AK |
13323 | #undef TARGET_LIBGCC_CMP_RETURN_MODE |
13324 | #define TARGET_LIBGCC_CMP_RETURN_MODE s390_libgcc_cmp_return_mode | |
13325 | ||
13326 | #undef TARGET_LIBGCC_SHIFT_COUNT_MODE | |
13327 | #define TARGET_LIBGCC_SHIFT_COUNT_MODE s390_libgcc_shift_count_mode | |
13328 | ||
c6c3dba9 PB |
13329 | #undef TARGET_LEGITIMATE_ADDRESS_P |
13330 | #define TARGET_LEGITIMATE_ADDRESS_P s390_legitimate_address_p | |
13331 | ||
1a627b35 RS |
13332 | #undef TARGET_LEGITIMATE_CONSTANT_P |
13333 | #define TARGET_LEGITIMATE_CONSTANT_P s390_legitimate_constant_p | |
13334 | ||
3597e113 VM |
13335 | #undef TARGET_LRA_P |
13336 | #define TARGET_LRA_P s390_lra_p | |
13337 | ||
7b5cbb57 AS |
13338 | #undef TARGET_CAN_ELIMINATE |
13339 | #define TARGET_CAN_ELIMINATE s390_can_eliminate | |
13340 | ||
5efd84c5 NF |
13341 | #undef TARGET_CONDITIONAL_REGISTER_USAGE |
13342 | #define TARGET_CONDITIONAL_REGISTER_USAGE s390_conditional_register_usage | |
13343 | ||
40ac4f73 CB |
13344 | #undef TARGET_LOOP_UNROLL_ADJUST |
13345 | #define TARGET_LOOP_UNROLL_ADJUST s390_loop_unroll_adjust | |
13346 | ||
b81ecf6f RH |
13347 | #undef TARGET_ASM_TRAMPOLINE_TEMPLATE |
13348 | #define TARGET_ASM_TRAMPOLINE_TEMPLATE s390_asm_trampoline_template | |
13349 | #undef TARGET_TRAMPOLINE_INIT | |
13350 | #define TARGET_TRAMPOLINE_INIT s390_trampoline_init | |
13351 | ||
9602b6a1 AK |
13352 | #undef TARGET_UNWIND_WORD_MODE |
13353 | #define TARGET_UNWIND_WORD_MODE s390_unwind_word_mode | |
13354 | ||
c354951b AK |
13355 | #undef TARGET_CANONICALIZE_COMPARISON |
13356 | #define TARGET_CANONICALIZE_COMPARISON s390_canonicalize_comparison | |
13357 | ||
6455a49e AK |
13358 | #undef TARGET_HARD_REGNO_SCRATCH_OK |
13359 | #define TARGET_HARD_REGNO_SCRATCH_OK s390_hard_regno_scratch_ok | |
13360 | ||
d0de9e13 DV |
13361 | #undef TARGET_ATTRIBUTE_TABLE |
13362 | #define TARGET_ATTRIBUTE_TABLE s390_attribute_table | |
13363 | ||
94091f43 DV |
13364 | #undef TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P |
13365 | #define TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P hook_bool_const_tree_true | |
d0de9e13 | 13366 | |
177bc204 RS |
13367 | #undef TARGET_SET_UP_BY_PROLOGUE |
13368 | #define TARGET_SET_UP_BY_PROLOGUE s300_set_up_by_prologue | |
13369 | ||
b5e3200c JG |
13370 | #undef TARGET_USE_BY_PIECES_INFRASTRUCTURE_P |
13371 | #define TARGET_USE_BY_PIECES_INFRASTRUCTURE_P \ | |
13372 | s390_use_by_pieces_infrastructure_p | |
13373 | ||
35bc11c3 AK |
13374 | #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV |
13375 | #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV s390_atomic_assign_expand_fenv | |
13376 | ||
085261c8 AK |
13377 | #undef TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN |
13378 | #define TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN s390_invalid_arg_for_unprototyped_fn | |
13379 | ||
13380 | #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE | |
13381 | #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE s390_preferred_simd_mode | |
13382 | ||
13383 | #undef TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT | |
13384 | #define TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT s390_support_vector_misalignment | |
13385 | ||
13386 | #undef TARGET_VECTOR_ALIGNMENT | |
13387 | #define TARGET_VECTOR_ALIGNMENT s390_vector_alignment | |
13388 | ||
ab96de7e | 13389 | struct gcc_target targetm = TARGET_INITIALIZER; |
38899e29 | 13390 | |
29742ba4 | 13391 | #include "gt-s390.h" |