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1fd4e8c1
RK		 1;;- Machine description for IBM RISC System 6000 (POWER) for GNU C compiler
2;; Copyright (C) 1990, 1991 Free Software Foundation, Inc.
3;; Contributed by Richard Kenner (kenner@nyu.edu)
4
5;; This file is part of GNU CC.
6
7;; GNU CC is free software; you can redistribute it and/or modify
8;; it under the terms of the GNU General Public License as published by
9;; the Free Software Foundation; either version 2, or (at your option)
10;; any later version.
11
12;; GNU CC is distributed in the hope that it will be useful,
13;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15;; GNU General Public License for more details.
16
17;; You should have received a copy of the GNU General Public License
18;; along with GNU CC; see the file COPYING. If not, write to
19;; the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
20
21;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
22\f
23;; Define an insn type attribute. This is used in function unit delay
24;; computations.
5c23c401 25(define_attr "type" "load,integer,fp,compare,delayed_compare,fpcompare,mtlr"
1fd4e8c1
RK		 26 (const_string "integer"))
27
28;; Memory delivers its result in two cycles.
29(define_function_unit "memory" 1 0 (eq_attr "type" "load") 2 0)
30
31;; We consider floating-point insns to deliver their result in two cycles
32;; to try to intersperse integer and FP operations.
33(define_function_unit "fp" 1 0 (eq_attr "type" "fp,fpcompare") 2 0)
34
35;; Most integer comparisons are ready in four cycles (a stall of three).
36(define_function_unit "compare" 1 0 (eq_attr "type" "compare") 4 0)
37
38;; Some integer comparisons aren't ready for five cycles (a stall of four).
39(define_function_unit "compare" 1 0 (eq_attr "type" "delayed_compare") 5 0)
40
41;; Floating-point comparisons take eight cycles.
42(define_function_unit "compare" 1 0 (eq_attr "type" "fpcompare") 8 0)
5c23c401
RK		 43
44;; Branches on LR cannot be done until five cycles after LR is set.
45(define_function_unit "branch" 1 0 (eq_attr "type" "mtlr") 5 0)
1fd4e8c1
RK		 46\f
47;; Start with fixed-point load and store insns. Here we put only the more
48;; complex forms. Basic data transfer is done later.
49
50(define_expand "zero_extendqisi2"
51 [(set (match_operand:SI 0 "gen_reg_operand" "")
52 (zero_extend:SI (match_operand:QI 1 "gen_reg_operand" "")))]
53 ""
54 "")
55
56(define_insn ""
57 [(set (match_operand:SI 0 "gen_reg_operand" "=r,r")
58 (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
59 ""
60 "@
61 lbz%U1%X1 %0,%1
62 rlinm %0,%1,0,24,31"
63 [(set_attr "type" "load,*")])
64
65(define_insn ""
66 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
67 (compare:CC (zero_extend:SI (match_operand:QI 1 "gen_reg_operand" "r"))
68 (const_int 0)))
69 (clobber (match_scratch:SI 2 "=r"))]
70 ""
71 "andil. %2,%1,255"
72 [(set_attr "type" "compare")])
73
74(define_insn ""
75 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
76 (compare:CC (zero_extend:SI (match_operand:QI 1 "gen_reg_operand" "r"))
77 (const_int 0)))
78 (set (match_operand:SI 0 "gen_reg_operand" "=r")
79 (zero_extend:SI (match_dup 1)))]
80 ""
81 "andil. %0,%1,255"
82 [(set_attr "type" "compare")])
83
84(define_expand "zero_extendqihi2"
85 [(set (match_operand:HI 0 "gen_reg_operand" "")
86 (zero_extend:HI (match_operand:QI 1 "gen_reg_operand" "")))]
87 ""
88 "")
89
90(define_insn ""
91 [(set (match_operand:HI 0 "gen_reg_operand" "=r,r")
92 (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
93 ""
94 "@
95 lbz%U1%X1 %0,%1
96 rlinm %0,%1,0,24,31"
97 [(set_attr "type" "load,*")])
98
99(define_expand "zero_extendhisi2"
100 [(set (match_operand:SI 0 "gen_reg_operand" "r")
101 (zero_extend:SI (match_operand:HI 1 "gen_reg_operand" "")))]
102 ""
103 "")
104
105(define_insn ""
106 [(set (match_operand:SI 0 "gen_reg_operand" "=r,r")
107 (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
108 ""
109 "@
110 lhz%U1%X1 %0,%1
111 rlinm %0,%1,0,16,31"
112 [(set_attr "type" "load,*")])
113
114(define_insn ""
115 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
116 (compare:CC (zero_extend:SI (match_operand:HI 1 "gen_reg_operand" "r"))
117 (const_int 0)))
118 (clobber (match_scratch:SI 2 "=r"))]
119 ""
120 "andil. %2,%1,65535"
121 [(set_attr "type" "compare")])
122
123(define_insn ""
124 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
125 (compare:CC (zero_extend:SI (match_operand:HI 1 "gen_reg_operand" "r"))
126 (const_int 0)))
127 (set (match_operand:SI 0 "gen_reg_operand" "=r")
128 (zero_extend:SI (match_dup 1)))]
129 ""
130 "andil. %0,%1,65535"
131 [(set_attr "type" "compare")])
132
133(define_expand "extendhisi2"
134 [(set (match_operand:SI 0 "gen_reg_operand" "")
135 (sign_extend:SI (match_operand:HI 1 "gen_reg_operand" "")))]
136 ""
137 "")
138
139(define_insn ""
140 [(set (match_operand:SI 0 "gen_reg_operand" "=r,r")
141 (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
142 ""
143 "@
144 lha%U1%X1 %0,%1
145 exts %0,%1"
146 [(set_attr "type" "load,*")])
147
148(define_insn ""
149 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
150 (compare:CC (sign_extend:SI (match_operand:HI 1 "gen_reg_operand" "r"))
151 (const_int 0)))
152 (clobber (match_scratch:SI 2 "=r"))]
153 ""
154 "exts. %2,%1"
155 [(set_attr "type" "compare")])
156
157(define_insn ""
158 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
159 (compare:CC (sign_extend:SI (match_operand:HI 1 "gen_reg_operand" "r"))
160 (const_int 0)))
161 (set (match_operand:SI 0 "gen_reg_operand" "=r")
162 (sign_extend:SI (match_dup 1)))]
163 ""
164 "exts. %0,%1"
165 [(set_attr "type" "compare")])
166\f
167;; Fixed-point arithmetic insns.
f357808b 168(define_insn "addsi3"
1fd4e8c1
RK		 169 [(set (match_operand:SI 0 "gen_reg_operand" "=r,r")
170 (plus:SI (match_operand:SI 1 "gen_reg_operand" "%r,b")
171 (match_operand:SI 2 "add_operand" "rI,J")))]
172 ""
173 "@
174 a%I2 %0,%1,%2
175 cau %0,%1,%u2")
176
177(define_insn ""
178 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
179 (compare:CC (plus:SI (match_operand:SI 1 "gen_reg_operand" "r")
180 (match_operand:SI 2 "reg_or_short_operand" "rI"))
181 (const_int 0)))
182 (clobber (match_scratch:SI 3 "=r"))]
183 ""
184 "a%I2. %3,%1,%2"
185 [(set_attr "type" "compare")])
186
187(define_insn ""
188 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
189 (compare:CC (plus:SI (match_operand:SI 1 "gen_reg_operand" "r")
190 (match_operand:SI 2 "reg_or_short_operand" "rI"))
191 (const_int 0)))
192 (set (match_operand:SI 0 "gen_reg_operand" "=r")
193 (plus:SI (match_dup 1) (match_dup 2)))]
194 ""
195 "a%I2. %0,%1,%2"
196 [(set_attr "type" "compare")])
197
f357808b
RK		 198;; Split an add that we can't do in one insn into two insns, each of which
199;; does one 16-bit part. This is used by combine. Note that the low-order
200;; add should be last in case the result gets used in an address.
201
202(define_split
1fd4e8c1
RK		 203 [(set (match_operand:SI 0 "gen_reg_operand" "")
204 (plus:SI (match_operand:SI 1 "gen_reg_operand" "")
f357808b 205 (match_operand:SI 2 "non_add_cint_operand" "")))]
1fd4e8c1 206 ""
f357808b
RK		 207 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))
208 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
209"
1fd4e8c1 210{
f357808b
RK		 211 int low = INTVAL (operands[2]) & 0xffff;
212 int high = (unsigned) INTVAL (operands[2]) >> 16;
1fd4e8c1 213
f357808b
RK		 214 if (low & 0x8000)
215 high++, low |= 0xffff0000;
1fd4e8c1 216
f357808b
RK		 217 operands[3] = gen_rtx (CONST_INT, VOIDmode, high << 16);
218 operands[4] = gen_rtx (CONST_INT, VOIDmode, low);
1fd4e8c1
RK		 219}")
220
221(define_insn "one_cmplsi2"
222 [(set (match_operand:SI 0 "gen_reg_operand" "=r")
223 (not:SI (match_operand:SI 1 "gen_reg_operand" "r")))]
224 ""
225 "sfi %0,%1,-1")
226
227(define_insn ""
228 [(set (match_operand:SI 0 "gen_reg_operand" "=r,r")
229 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "r,I")
230 (match_operand:SI 2 "gen_reg_operand" "r,r")))]
231 ""
232 "@
233 sf %0,%2,%1
234 sfi %0,%2,%1")
235
236(define_insn ""
237 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
238 (compare:CC (minus:SI (match_operand:SI 1 "gen_reg_operand" "r")
239 (match_operand:SI 2 "gen_reg_operand" "r"))
240 (const_int 0)))
241 (clobber (match_scratch:SI 3 "=r"))]
242 ""
243 "sf. %3,%2,%1"
244 [(set_attr "type" "compare")])
245
246(define_insn ""
247 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
248 (compare:CC (minus:SI (match_operand:SI 1 "gen_reg_operand" "r")
249 (match_operand:SI 2 "gen_reg_operand" "r"))
250 (const_int 0)))
251 (set (match_operand:SI 0 "gen_reg_operand" "=r")
252 (minus:SI (match_dup 1) (match_dup 2)))]
253 ""
254 "sf. %0,%2,%1"
255 [(set_attr "type" "compare")])
256
257(define_expand "subsi3"
258 [(set (match_operand:SI 0 "gen_reg_operand" "")
259 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "")
260 (match_operand:SI 2 "reg_or_cint_operand" "")))]
261 ""
262 "
263{
264 if (GET_CODE (operands[2]) == CONST_INT)
265 {
266 emit_insn (gen_addsi3 (operands[0], operands[1],
267 negate_rtx (SImode, operands[2])));
268 DONE;
269 }
1fd4e8c1
RK		 270}")
271
272;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i]
273;; instruction and some auxiliary computations. Then we just have a single
274;; DEFINE_INSN for doz[i].
275
276(define_expand "sminsi3"
277 [(set (match_dup 3)
278 (if_then_else:SI (gt:SI (match_operand:SI 1 "gen_reg_operand" "")
279 (match_operand:SI 2 "reg_or_short_operand" ""))
280 (const_int 0)
281 (minus:SI (match_dup 2) (match_dup 1))))
282 (set (match_operand:SI 0 "gen_reg_operand" "")
283 (minus:SI (match_dup 2) (match_dup 3)))]
284 ""
285 "
286{ operands[3] = gen_reg_rtx (SImode); }")
287
288(define_expand "smaxsi3"
289 [(set (match_dup 3)
290 (if_then_else:SI (gt:SI (match_operand:SI 1 "gen_reg_operand" "")
291 (match_operand:SI 2 "reg_or_short_operand" ""))
292 (const_int 0)
293 (minus:SI (match_dup 2) (match_dup 1))))
294 (set (match_operand:SI 0 "gen_reg_operand" "")
295 (plus:SI (match_dup 3) (match_dup 1)))]
296 ""
297 "
298{ operands[3] = gen_reg_rtx (SImode); }")
299
300(define_expand "uminsi3"
301 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gen_reg_operand" "")
302 (const_int -2147483648)))
303 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gen_reg_operand" "")
304 (const_int -2147483648)))
305 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
306 (const_int 0)
307 (minus:SI (match_dup 4) (match_dup 3))))
308 (set (match_operand:SI 0 "gen_reg_operand" "")
309 (minus:SI (match_dup 2) (match_dup 3)))]
310 ""
311 "
312{ operands[3] = gen_reg_rtx (SImode); operands[4] = gen_reg_rtx (SImode); }")
313
314(define_expand "umaxsi3"
315 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gen_reg_operand" "")
316 (const_int -2147483648)))
317 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gen_reg_operand" "")
318 (const_int -2147483648)))
319 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
320 (const_int 0)
321 (minus:SI (match_dup 4) (match_dup 3))))
322 (set (match_operand:SI 0 "gen_reg_operand" "")
323 (plus:SI (match_dup 3) (match_dup 1)))]
324 ""
325 "
326{ operands[3] = gen_reg_rtx (SImode); operands[4] = gen_reg_rtx (SImode); }")
327
328(define_insn ""
329 [(set (match_operand:SI 0 "gen_reg_operand" "=r")
330 (if_then_else:SI (gt (match_operand:SI 1 "gen_reg_operand" "r")
5c23c401 331 (match_operand:SI 2 "reg_or_short_operand" "rI"))
1fd4e8c1
RK		 332 (const_int 0)
333 (minus:SI (match_dup 2) (match_dup 1))))]
334 ""
335 "doz%I2 %0,%1,%2")
336
337(define_insn ""
338 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
339 (compare:CC
340 (if_then_else:SI (gt (match_operand:SI 1 "gen_reg_operand" "r")
5c23c401 341 (match_operand:SI 2 "reg_or_short_operand" "rI"))
1fd4e8c1
RK		 342 (const_int 0)
343 (minus:SI (match_dup 2) (match_dup 1)))
344 (const_int 0)))
345 (clobber (match_scratch:SI 3 "=r"))]
346 ""
347 "doz%I2. %3,%1,%2"
348 [(set_attr "type" "delayed_compare")])
349
350(define_insn ""
351 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
352 (compare:CC
353 (if_then_else:SI (gt (match_operand:SI 1 "gen_reg_operand" "r")
5c23c401 354 (match_operand:SI 2 "reg_or_short_operand" "rI"))
1fd4e8c1
RK		 355 (const_int 0)
356 (minus:SI (match_dup 2) (match_dup 1)))
357 (const_int 0)))
358 (set (match_operand:SI 0 "gen_reg_operand" "=r")
359 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
360 (const_int 0)
361 (minus:SI (match_dup 2) (match_dup 1))))]
362 ""
363 "doz%I2. %0,%1,%2"
364 [(set_attr "type" "delayed_compare")])
365
366;; We don't need abs with condition code because such comparisons should
367;; never be done.
368(define_insn "abssi2"
369 [(set (match_operand:SI 0 "gen_reg_operand" "=r")
370 (abs:SI (match_operand:SI 1 "gen_reg_operand" "r")))]
371 ""
372 "abs %0,%1")
373
374(define_insn ""
375 [(set (match_operand:SI 0 "gen_reg_operand" "=r")
376 (neg:SI (abs:SI (match_operand:SI 1 "gen_reg_operand" "r"))))]
377 ""
378 "nabs %0,%1")
379
380(define_insn "negsi2"
381 [(set (match_operand:SI 0 "gen_reg_operand" "=r")
382 (neg:SI (match_operand:SI 1 "gen_reg_operand" "r")))]
383 ""
384 "neg %0,%1")
385
386(define_insn ""
387 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
388 (compare:CC (neg:SI (match_operand:SI 1 "gen_reg_operand" "r"))
389 (const_int 0)))
390 (clobber (match_scratch:SI 2 "=r"))]
391 ""
392 "neg. %2,%1"
393 [(set_attr "type" "compare")])
394
395(define_insn ""
396 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
397 (compare:CC (neg:SI (match_operand:SI 1 "gen_reg_operand" "r"))
398 (const_int 0)))
399 (set (match_operand:SI 0 "gen_reg_operand" "=r")
400 (neg:SI (match_dup 1)))]
401 ""
402 "neg. %0,%1"
403 [(set_attr "type" "compare")])
404
405(define_insn "ffssi2"
406 [(set (match_operand:SI 0 "register_operand" "=&r")
407 (ffs:SI (match_operand:SI 1 "register_operand" "r")))]
408 ""
409 "neg %0,%1\;and %0,%0,%1\;cntlz %0,%0\;sfi %0,%0,32")
410
411;; There is no need for (set (condition) (compare (ffs) 0)) because that
412;; can be simplified to an ordinary comparison. A parallel set and compare
413;; might be used, so include it.
414
415(define_insn ""
416 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
417 (compare:CC (ffs:SI (match_operand:SI 1 "register_operand" "r"))
418 (const_int 0)))
419 (set (match_operand:SI 0 "register_operand" "=&r")
420 (ffs:SI (match_dup 1)))]
421 ""
422 "neg %0,%1\;and %0,%0,%1\;cntlz %0,%0\;sfi. %0,%0,32"
423 [(set_attr "type" "compare")])
424
425(define_insn "mulsi3"
426 [(set (match_operand:SI 0 "gen_reg_operand" "=r,r")
427 (mult:SI (match_operand:SI 1 "gen_reg_operand" "%r,r")
428 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
429 (clobber (match_scratch:SI 3 "=q,q"))]
430 ""
431 "@
432 muls %0,%1,%2
433 muli %0,%1,%2")
434
435(define_insn ""
436 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
437 (compare:CC (mult:SI (match_operand:SI 1 "gen_reg_operand" "r")
438 (match_operand:SI 2 "gen_reg_operand" "r"))
439 (const_int 0)))
440 (clobber (match_scratch:SI 3 "=r"))
441 (clobber (match_scratch:SI 4 "=q"))]
442 ""
443 "muls. %3,%1,%2"
444 [(set_attr "type" "delayed_compare")])
445
446(define_insn ""
447 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
448 (compare:CC (mult:SI (match_operand:SI 1 "gen_reg_operand" "r")
449 (match_operand:SI 2 "gen_reg_operand" "r"))
450 (const_int 0)))
451 (set (match_operand:SI 0 "gen_reg_operand" "=r")
452 (mult:SI (match_dup 1) (match_dup 2)))
453 (clobber (match_scratch:SI 4 "=q"))]
454 ""
455 "muls. %0,%1,%2"
456 [(set_attr "type" "delayed_compare")])
457
458;; Operand 1 is divided by operand 2; quotient goes to operand
459;; 0 and remainder to operand 3.
460;; ??? At some point, see what, if anything, we can do about if (x % y == 0).
461
462(define_insn "divmodsi4"
463 [(set (match_operand:SI 0 "gen_reg_operand" "=r")
464 (div:SI (match_operand:SI 1 "gen_reg_operand" "r")
465 (match_operand:SI 2 "gen_reg_operand" "r")))
466 (set (match_operand:SI 3 "gen_reg_operand" "=q")
467 (mod:SI (match_dup 1) (match_dup 2)))]
468 ""
469 "divs %0,%1,%2")
470
471;; For powers of two we can do srai/aze for divide and then adjust for
472;; modulus. If it isn't a power of two, FAIL so divmodsi4 will be used.
473(define_expand "divsi3"
474 [(set (match_operand:SI 0 "gen_reg_operand" "")
475 (div:SI (match_operand:SI 1 "gen_reg_operand" "")
476 (match_operand:SI 2 "reg_or_cint_operand" "")))]
477 ""
478 "
479{
480 if (GET_CODE (operands[2]) != CONST_INT
481 || exact_log2 (INTVAL (operands[2])) < 0)
482 FAIL;
483}")
484
485(define_expand "modsi3"
486 [(set (match_dup 3)
487 (div:SI (match_operand:SI 1 "gen_reg_operand" "")
488 (match_operand:SI 2 "reg_or_cint_operand" "")))
489 (parallel [(set (match_dup 4) (ashift:SI (match_dup 3) (match_dup 5)))
490 (clobber (scratch:SI))])
491 (set (match_operand:SI 0 "gen_reg_operand" "")
492 (minus:SI (match_dup 1) (match_dup 4)))]
493 ""
494 "
495{
496 int i = exact_log2 (INTVAL (operands[2]));
497
498 if (GET_CODE (operands[2]) != CONST_INT || i < 0)
499 FAIL;
500
501 operands[3] = gen_reg_rtx (SImode);
502 operands[4] = gen_reg_rtx (SImode);
503 operands[5] = gen_rtx (CONST_INT, VOIDmode, i);
504}")
505
506(define_insn ""
507 [(set (match_operand:SI 0 "gen_reg_operand" "=r")
508 (div:SI (match_operand:SI 1 "gen_reg_operand" "r")
509 (match_operand:SI 2 "const_int_operand" "N")))]
510 "exact_log2 (INTVAL (operands[2])) >= 0"
511 "srai %0,%1,%p2\;aze %0,%0")
512
513(define_insn ""
514 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
515 (div:SI (match_operand:SI 1 "gen_reg_operand" "r")
516 (match_operand:SI 2 "const_int_operand" "N")))
517 (clobber (match_scratch:SI 3 "=r"))]
518 "exact_log2 (INTVAL (operands[2])) >= 0"
519 "srai %3,%1,%p2\;aze. %3,%3"
520 [(set_attr "type" "compare")])
521
522(define_insn ""
523 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
524 (div:SI (match_operand:SI 1 "gen_reg_operand" "r")
525 (match_operand:SI 2 "const_int_operand" "N")))
526 (set (match_operand:SI 0 "gen_reg_operand" "=r")
527 (div:SI (match_dup 1) (match_dup 2)))]
528 "exact_log2 (INTVAL (operands[2])) >= 0"
529 "srai %0,%1,%p2\;aze. %0,%0"
530 [(set_attr "type" "compare")])
531
532(define_insn ""
533 [(set (match_operand:SI 0 "gen_reg_operand" "=r")
534 (udiv:SI
535 (plus:DI (lshift:DI
536 (zero_extend:DI (match_operand:SI 1 "gen_reg_operand" "r"))
537 (const_int 32))
538 (zero_extend:DI (match_operand:SI 2 "register_operand" "*q")))
539 (match_operand:SI 3 "gen_reg_operand" "r")))
540 (set (match_operand:SI 4 "register_operand" "=*q")
541 (umod:SI
542 (plus:DI (lshift:DI
543 (zero_extend:DI (match_dup 1)) (const_int 32))
544 (zero_extend:DI (match_dup 2)))
545 (match_dup 3)))]
546
547 ""
548 "div %0,%1,%3")
549
550;; To do unsigned divide we handle the cases of the divisor looking like a
551;; negative number. If it is a constant that is less than 2**31, we don't
552;; have to worry about the branches. So make a few subroutines here.
553;;
554;; First comes the normal case.
555(define_expand "udivmodsi4_normal"
556 [(set (match_dup 4) (const_int 0))
557 (parallel [(set (match_operand:SI 0 "" "")
558 (udiv:SI (plus:DI (lshift:DI (zero_extend:DI (match_dup 4))
559 (const_int 32))
560 (zero_extend:DI (match_operand:SI 1 "" "")))
561 (match_operand:SI 2 "" "")))
562 (set (match_operand:SI 3 "" "")
563 (umod:SI (plus:DI (lshift:DI (zero_extend:DI (match_dup 4))
564 (const_int 32))
565 (zero_extend:DI (match_dup 1)))
566 (match_dup 2)))])]
567 ""
568 "
569{ operands[4] = gen_reg_rtx (SImode); }")
570
571;; This handles the branches.
572(define_expand "udivmodsi4_tests"
573 [(set (match_operand:SI 0 "" "") (const_int 0))
574 (set (match_operand:SI 3 "" "") (match_operand:SI 1 "" ""))
575 (set (match_dup 5) (compare:CCUNS (match_dup 1) (match_operand:SI 2 "" "")))
576 (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0))
577 (label_ref (match_operand:SI 4 "" "")) (pc)))
578 (set (match_dup 0) (const_int 1))
579 (set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2)))
580 (set (match_dup 6) (compare:CC (match_dup 2) (const_int 0)))
581 (set (pc) (if_then_else (lt (match_dup 6) (const_int 0))
582 (label_ref (match_dup 4)) (pc)))]
583 ""
584 "
585{ operands[5] = gen_reg_rtx (CCUNSmode);
586 operands[6] = gen_reg_rtx (CCmode);
587}")
588
589(define_expand "udivmodsi4"
590 [(parallel [(set (match_operand:SI 0 "gen_reg_operand" "")
591 (udiv:SI (match_operand:SI 1 "gen_reg_operand" "")
592 (match_operand:SI 2 "reg_or_cint_operand" "")))
593 (set (match_operand:SI 3 "gen_reg_operand" "")
594 (umod:SI (match_dup 1) (match_dup 2)))])]
595 ""
596 "
597{
598 rtx label = 0;
599
600 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) < 0)
601 {
602 operands[2] = force_reg (SImode, operands[2]);
603 label = gen_label_rtx ();
604 emit (gen_udivmodsi4_tests (operands[0], operands[1], operands[2],
605 operands[3], label));
606 }
607 else
608 operands[2] = force_reg (SImode, operands[2]);
609
610 emit (gen_udivmodsi4_normal (operands[0], operands[1], operands[2],
611 operands[3]));
612 if (label)
613 emit_label (label);
614
615 DONE;
616}")
617
618(define_insn "andsi3"
619 [(set (match_operand:SI 0 "gen_reg_operand" "=r,r,r,r")
620 (and:SI (match_operand:SI 1 "gen_reg_operand" "%r,r,r,r")
621 (match_operand:SI 2 "and_operand" "?r,L,K,J")))
622 (clobber (match_scratch:CC 3 "=X,X,x,x"))]
623 ""
624 "@
625 and %0,%1,%2
626 rlinm %0,%1,0,%m2,%M2
627 andil. %0,%1,%b2
628 andiu. %0,%1,%u2")
629
630(define_insn ""
631 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x")
632 (compare:CC (and:SI (match_operand:SI 1 "gen_reg_operand" "%r,r,r,r")
633 (match_operand:SI 2 "and_operand" "r,K,J,L"))
634 (const_int 0)))
635 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
636 ""
637 "@
638 and. %3,%1,%2
639 andil. %3,%1,%b2
640 andiu. %3,%1,%u2
641 rlinm. %3,%1,0,%m2,%M2"
642 [(set_attr "type" "compare,compare,compare,delayed_compare")])
643
644(define_insn ""
645 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x")
646 (compare:CC (and:SI (match_operand:SI 1 "gen_reg_operand" "%r,r,r,r")
647 (match_operand:SI 2 "and_operand" "r,K,J,L"))
648 (const_int 0)))
649 (set (match_operand:SI 0 "gen_reg_operand" "=r,r,r,r")
650 (and:SI (match_dup 1) (match_dup 2)))]
651 ""
652 "@
653 and. %0,%1,%2
654 andil. %0,%1,%b2
655 andiu. %0,%1,%u2
656 rlinm. %0,%1,0,%m2,%M2"
657 [(set_attr "type" "compare,compare,compare,delayed_compare")])
658
f357808b
RK		 659;; Take a AND with a constant that cannot be done in a single insn and try to
660;; split it into two insns. This does not verify that the insns are valid
661;; since this need not be done as combine will do it.
662
663(define_split
664 [(set (match_operand:SI 0 "gen_reg_operand" "")
665 (and:SI (match_operand:SI 1 "gen_reg_operand" "")
666 (match_operand:SI 2 "non_and_cint_operand" "")))]
667 ""
668 [(set (match_dup 0) (and:SI (match_dup 1) (match_dup 3)))
669 (set (match_dup 0) (and:SI (match_dup 0) (match_dup 4)))]
670 "
671{
672 int maskval = INTVAL (operands[2]);
673 int i, transitions, last_bit_value;
674 int orig = maskval, first_c = maskval, second_c;
675
676 /* We know that MASKVAL must have more than 2 bit-transitions. Start at
677 the low-order bit and count for the third transition. When we get there,
678 make a first mask that has everything to the left of that position
679 a one. Then make the second mask to turn off whatever else is needed. */
680
681 for (i = 1, transitions = 0, last_bit_value = maskval & 1; i < 32; i++)
682 {
683 if (((maskval >>= 1) & 1) != last_bit_value)
684 last_bit_value ^= 1, transitions++;
685
686 if (transitions > 2)
687 {
688 first_c |= (~0) << i;
689 break;
690 }
691 }
692
693 second_c = orig | ~ first_c;
694
695 operands[3] = gen_rtx (CONST_INT, VOIDmode, first_c);
696 operands[4] = gen_rtx (CONST_INT, VOIDmode, second_c);
697}")
698
699(define_insn "iorsi3"
1fd4e8c1
RK		 700 [(set (match_operand:SI 0 "gen_reg_operand" "=r,r,r")
701 (ior:SI (match_operand:SI 1 "gen_reg_operand" "%r,r,r")
702 (match_operand:SI 2 "logical_operand" "r,K,J")))]
703 ""
704 "@
705 or %0,%1,%2
706 oril %0,%1,%b2
707 oriu %0,%1,%u2")
708
709(define_insn ""
710 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
711 (compare:CC (ior:SI (match_operand:SI 1 "gen_reg_operand" "r")
712 (match_operand:SI 2 "gen_reg_operand" "r"))
713 (const_int 0)))
714 (clobber (match_scratch:SI 3 "=r"))]
715 ""
716 "or. %3,%1,%2"
717 [(set_attr "type" "compare")])
718
719(define_insn ""
720 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
721 (compare:CC (ior:SI (match_operand:SI 1 "gen_reg_operand" "r")
722 (match_operand:SI 2 "gen_reg_operand" "r"))
723 (const_int 0)))
724 (set (match_operand:SI 0 "gen_reg_operand" "=r")
725 (ior:SI (match_dup 1) (match_dup 2)))]
726 ""
727 "or. %0,%1,%2"
728 [(set_attr "type" "compare")])
729
f357808b
RK		 730;; Split an IOR that we can't do in one insn into two insns, each of which
731;; does one 16-bit part. This is used by combine.
732
733(define_split
1fd4e8c1
RK		 734 [(set (match_operand:SI 0 "gen_reg_operand" "")
735 (ior:SI (match_operand:SI 1 "gen_reg_operand" "")
f357808b 736 (match_operand:SI 2 "non_logical_cint_operand" "")))]
1fd4e8c1 737 ""
f357808b
RK		 738 [(set (match_dup 0) (ior:SI (match_dup 1) (match_dup 3)))
739 (set (match_dup 0) (ior:SI (match_dup 0) (match_dup 4)))]
740"
1fd4e8c1 741{
f357808b
RK		 742 operands[3] = gen_rtx (CONST_INT, VOIDmode,
743 INTVAL (operands[2]) & 0xffff0000);
744 operands[4] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) & 0xffff);
1fd4e8c1
RK		 745}")
746
f357808b 747(define_insn "xorsi3"
1fd4e8c1
RK		 748 [(set (match_operand:SI 0 "gen_reg_operand" "=r,r,r")
749 (xor:SI (match_operand:SI 1 "gen_reg_operand" "%r,r,r")
750 (match_operand:SI 2 "logical_operand" "r,K,J")))]
751 ""
752 "@
753 xor %0,%1,%2
754 xoril %0,%1,%b2
755 xoriu %0,%1,%u2")
756
757(define_insn ""
758 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
759 (compare:CC (xor:SI (match_operand:SI 1 "gen_reg_operand" "r")
760 (match_operand:SI 2 "gen_reg_operand" "r"))
761 (const_int 0)))
762 (clobber (match_scratch:SI 3 "=r"))]
763 ""
764 "xor. %3,%1,%2"
765 [(set_attr "type" "compare")])
766
767(define_insn ""
768 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
769 (compare:CC (xor:SI (match_operand:SI 1 "gen_reg_operand" "r")
770 (match_operand:SI 2 "gen_reg_operand" "r"))
771 (const_int 0)))
772 (set (match_operand:SI 0 "gen_reg_operand" "=r")
773 (xor:SI (match_dup 1) (match_dup 2)))]
774 ""
775 "xor. %0,%1,%2"
776 [(set_attr "type" "compare")])
777
f357808b
RK		 778;; Split an XOR that we can't do in one insn into two insns, each of which
779;; does one 16-bit part. This is used by combine.
780
781(define_split
1fd4e8c1
RK		 782 [(set (match_operand:SI 0 "gen_reg_operand" "")
783 (xor:SI (match_operand:SI 1 "gen_reg_operand" "")
f357808b 784 (match_operand:SI 2 "non_logical_cint_operand" "")))]
1fd4e8c1 785 ""
f357808b
RK		 786 [(set (match_dup 0) (xor:SI (match_dup 1) (match_dup 3)))
787 (set (match_dup 0) (xor:SI (match_dup 0) (match_dup 4)))]
788"
1fd4e8c1 789{
f357808b
RK		 790 operands[3] = gen_rtx (CONST_INT, VOIDmode,
791 INTVAL (operands[2]) & 0xffff0000);
792 operands[4] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) & 0xffff);
1fd4e8c1
RK		 793}")
794
795(define_insn ""
796 [(set (match_operand:SI 0 "gen_reg_operand" "=r")
797 (not:SI (xor:SI (match_operand:SI 1 "gen_reg_operand" "%r")
798 (match_operand:SI 2 "gen_reg_operand" "r"))))]
799 ""
800 "eqv %0,%1,%2")
801
802(define_insn ""
803 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
804 (compare:CC (not:SI (xor:SI (match_operand:SI 1 "gen_reg_operand" "%r")
805 (match_operand:SI 2 "gen_reg_operand" "r")))
806 (const_int 0)))
807 (clobber (match_scratch:SI 3 "=r"))]
808 ""
809 "eqv. %3,%1,%2"
810 [(set_attr "type" "compare")])
811
812(define_insn ""
813 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
814 (compare:CC (not:SI (xor:SI (match_operand:SI 1 "gen_reg_operand" "%r")
815 (match_operand:SI 2 "gen_reg_operand" "r")))
816 (const_int 0)))
817 (set (match_operand:SI 0 "gen_reg_operand" "=r")
818 (not:SI (xor:SI (match_dup 1) (match_dup 2))))]
819 ""
820 "eqv. %0,%1,%2"
821 [(set_attr "type" "compare")])
822
823(define_insn ""
824 [(set (match_operand:SI 0 "gen_reg_operand" "=r")
825 (and:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
826 (match_operand:SI 2 "gen_reg_operand" "r")))]
827 ""
828 "andc %0,%2,%1")
829
830(define_insn ""
831 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
832 (compare:CC (and:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
833 (match_operand:SI 2 "gen_reg_operand" "r"))
834 (const_int 0)))
835 (clobber (match_scratch:SI 3 "=r"))]
836 ""
837 "andc. %3,%2,%1"
838 [(set_attr "type" "compare")])
839
840(define_insn ""
841 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
842 (compare:CC (and:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
843 (match_operand:SI 2 "gen_reg_operand" "r"))
844 (const_int 0)))
845 (set (match_operand:SI 0 "gen_reg_operand" "=r")
846 (and:SI (not:SI (match_dup 1)) (match_dup 2)))]
847 ""
848 "andc. %0,%2,%1"
849 [(set_attr "type" "compare")])
850
851(define_insn ""
852 [(set (match_operand:SI 0 "gen_reg_operand" "=r")
853 (ior:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
854 (match_operand:SI 2 "gen_reg_operand" "r")))]
855 ""
856 "orc %0,%2,%1")
857
858(define_insn ""
859 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
860 (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
861 (match_operand:SI 2 "gen_reg_operand" "r"))
862 (const_int 0)))
863 (clobber (match_scratch:SI 3 "=r"))]
864 ""
865 "orc. %3,%2,%1"
866 [(set_attr "type" "compare")])
867
868(define_insn ""
869 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
870 (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
871 (match_operand:SI 2 "gen_reg_operand" "r"))
872 (const_int 0)))
873 (set (match_operand:SI 0 "gen_reg_operand" "=r")
874 (ior:SI (not:SI (match_dup 1)) (match_dup 2)))]
875 ""
876 "orc. %0,%2,%1"
877 [(set_attr "type" "compare")])
878
879(define_insn ""
880 [(set (match_operand:SI 0 "gen_reg_operand" "=r")
881 (ior:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
882 (not:SI (match_operand:SI 2 "gen_reg_operand" "r"))))]
883 ""
884 "nand %0,%1,%2")
885
886(define_insn ""
887 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
888 (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
889 (not:SI (match_operand:SI 2 "gen_reg_operand" "r")))
890 (const_int 0)))
891 (clobber (match_scratch:SI 3 "=r"))]
892 ""
893 "nand. %3,%1,%2"
894 [(set_attr "type" "compare")])
895
896(define_insn ""
897 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
898 (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
899 (not:SI (match_operand:SI 2 "gen_reg_operand" "r")))
900 (const_int 0)))
901 (set (match_operand:SI 0 "gen_reg_operand" "=r")
902 (ior:SI (not:SI (match_dup 1)) (not:SI (match_dup 2))))]
903 ""
904 "nand. %0,%1,%2"
905 [(set_attr "type" "compare")])
906
907(define_insn ""
908 [(set (match_operand:SI 0 "gen_reg_operand" "=r")
909 (and:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
910 (not:SI (match_operand:SI 2 "gen_reg_operand" "r"))))]
911 ""
912 "nor %0,%1,%2")
913
914(define_insn ""
915 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
916 (compare:CC (and:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
917 (not:SI (match_operand:SI 2 "gen_reg_operand" "r")))
918 (const_int 0)))
919 (clobber (match_scratch:SI 3 "=r"))]
920 ""
921 "nor. %3,%1,%2"
922 [(set_attr "type" "compare")])
923
924(define_insn ""
925 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
926 (compare:CC (and:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
927 (not:SI (match_operand:SI 2 "gen_reg_operand" "r")))
928 (const_int 0)))
929 (set (match_operand:SI 0 "gen_reg_operand" "=r")
930 (and:SI (not:SI (match_dup 1)) (not:SI (match_dup 2))))]
931 ""
932 "nor. %0,%1,%2"
933 [(set_attr "type" "compare")])
934
935;; maskir insn. We need four forms because things might be in arbitrary
936;; orders. Don't define forms that only set CR fields because these
937;; would modify an input register.
938
939(define_insn ""
940 [(set (match_operand:SI 0 "gen_reg_operand" "=r")
941 (ior:SI (and:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
942 (match_operand:SI 2 "gen_reg_operand" "0"))
943 (and:SI (match_dup 1)
944 (match_operand:SI 3 "gen_reg_operand" "r"))))]
945 ""
946 "maskir %0,%3,%1")
947
948(define_insn ""
949 [(set (match_operand:SI 0 "register_operand" "=r")
950 (ior:SI (and:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
951 (match_operand:SI 2 "gen_reg_operand" "0"))
952 (and:SI (match_operand:SI 3 "gen_reg_operand" "r")
953 (match_dup 1))))]
954 ""
955 "maskir %0,%3,%1")
956
957(define_insn ""
958 [(set (match_operand:SI 0 "gen_reg_operand" "=r")
959 (ior:SI (and:SI (match_dup 1)
960 (match_operand:SI 3 "gen_reg_operand" "r"))
961 (and:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
962 (match_operand:SI 2 "gen_reg_operand" "0"))))]
963 ""
964 "maskir %0,%3,%1")
965
966(define_insn ""
967 [(set (match_operand:SI 0 "gen_reg_operand" "=r")
968 (ior:SI (and:SI (match_operand:SI 3 "gen_reg_operand" "r")
969 (match_dup 1))
970 (and:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
971 (match_operand:SI 2 "gen_reg_operand" "0"))))]
972 ""
973 "maskir %0,%3,%1")
974
975(define_insn ""
976 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
977 (compare:CC
978 (ior:SI (and:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
979 (match_operand:SI 2 "gen_reg_operand" "0"))
980 (and:SI (match_dup 1)
981 (match_operand:SI 3 "gen_reg_operand" "r")))
982 (const_int 0)))
983 (set (match_operand:SI 0 "gen_reg_operand" "=r")
984 (ior:SI (and:SI (not:SI (match_dup 1)) (match_dup 2))
985 (and:SI (match_dup 1) (match_dup 3))))]
986 ""
987 "maskir. %0,%3,%1"
988 [(set_attr "type" "compare")])
989
990(define_insn ""
991 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
992 (compare:CC
993 (ior:SI (and:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
994 (match_operand:SI 2 "gen_reg_operand" "0"))
995 (and:SI (match_operand:SI 3 "gen_reg_operand" "r")
996 (match_dup 1)))
997 (const_int 0)))
998 (set (match_operand:SI 0 "register_operand" "=r")
999 (ior:SI (and:SI (not:SI (match_dup 1)) (match_dup 2))
1000 (and:SI (match_dup 3) (match_dup 1))))]
1001 ""
1002 "maskir. %0,%3,%1"
1003 [(set_attr "type" "compare")])
1004
1005(define_insn ""
1006 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
1007 (compare:CC
1008 (ior:SI (and:SI (match_dup 1)
1009 (match_operand:SI 3 "gen_reg_operand" "r"))
1010 (and:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
1011 (match_operand:SI 2 "gen_reg_operand" "0")))
1012 (const_int 0)))
1013 (set (match_operand:SI 0 "gen_reg_operand" "=r")
1014 (ior:SI (and:SI (match_dup 1) (match_dup 3))
1015 (and:SI (not:SI (match_dup 1)) (match_dup 2))))]
1016 ""
1017 "maskir. %0,%3,%1"
1018 [(set_attr "type" "compare")])
1019
1020(define_insn ""
1021 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
1022 (compare:CC
1023 (ior:SI (and:SI (match_operand:SI 3 "gen_reg_operand" "r")
1024 (match_dup 1))
1025 (and:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
1026 (match_operand:SI 2 "gen_reg_operand" "0")))
1027 (const_int 0)))
1028 (set (match_operand:SI 0 "gen_reg_operand" "=r")
1029 (ior:SI (and:SI (match_dup 3) (match_dup 1))
1030 (and:SI (not:SI (match_dup 1)) (match_dup 2))))]
1031 ""
1032 "maskir. %0,%3,%1"
1033 [(set_attr "type" "compare")])
1034\f
1035;; Rotate and shift insns, in all their variants. These support shifts,
1036;; field inserts and extracts, and various combinations thereof.
1037(define_insn "insv"
1038 [(set (zero_extract:SI (match_operand:SI 0 "gen_reg_operand" "+r")
1039 (match_operand:SI 1 "const_int_operand" "i")
1040 (match_operand:SI 2 "const_int_operand" "i"))
1041 (match_operand:SI 3 "gen_reg_operand" "r"))]
1042 ""
1043 "*
1044{
1045 int start = INTVAL (operands[2]) & 31;
1046 int size = INTVAL (operands[1]) & 31;
1047
1048 operands[4] = gen_rtx (CONST_INT, VOIDmode, 32 - start - size);
1049 operands[1] = gen_rtx (CONST_INT, VOIDmode, start + size - 1);
1050 return \"rlimi %0,%3,%4,%h2,%h1\";
1051}")
1052
1053(define_insn "extzv"
1054 [(set (match_operand:SI 0 "gen_reg_operand" "=r")
1055 (zero_extract:SI (match_operand:SI 1 "gen_reg_operand" "r")
1056 (match_operand:SI 2 "const_int_operand" "i")
1057 (match_operand:SI 3 "const_int_operand" "i")))]
1058 ""
1059 "*
1060{
1061 int start = INTVAL (operands[3]) & 31;
1062 int size = INTVAL (operands[2]) & 31;
1063
1064 if (start + size >= 32)
1065 operands[3] = const0_rtx;
1066 else
1067 operands[3] = gen_rtx (CONST_INT, VOIDmode, start + size);
1068 return \"rlinm %0,%1,%3,%s2,31\";
1069}")
1070
1071(define_insn ""
1072 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1073 (compare:CC (zero_extract:SI (match_operand:SI 1 "gen_reg_operand" "r")
1074 (match_operand:SI 2 "const_int_operand" "i")
1075 (match_operand:SI 3 "const_int_operand" "i"))
1076 (const_int 0)))
1077 (clobber (match_scratch:SI 4 "=r"))]
1078 ""
1079 "*
1080{
1081 int start = INTVAL (operands[3]) & 31;
1082 int size = INTVAL (operands[2]) & 31;
1083
df031c43
RK		 1084 if ((start < 16 && start + size <= 16) || start >= 16)
1085 {
1086 operands[3] = gen_rtx (CONST_INT, VOIDmode,
1087 ((1 << (16 - (start & 15)))
1088 - (1 << (16 - (start & 15) - size))));
1089 if (start < 16)
1090 return \"andiu. %4,%1,%3\";
1091 else
1092 return \"andil. %4,%1,%3\";
1093 }
1094
1fd4e8c1
RK		 1095 if (start + size >= 32)
1096 operands[3] = const0_rtx;
1097 else
1098 operands[3] = gen_rtx (CONST_INT, VOIDmode, start + size);
1099 return \"rlinm. %4,%1,%3,%s2,31\";
1100}"
1101 [(set_attr "type" "compare")])
1102
1103(define_insn ""
1104 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
1105 (compare:CC (zero_extract:SI (match_operand:SI 1 "gen_reg_operand" "r")
1106 (match_operand:SI 2 "const_int_operand" "i")
1107 (match_operand:SI 3 "const_int_operand" "i"))
1108 (const_int 0)))
1109 (set (match_operand:SI 0 "gen_reg_operand" "=r")
1110 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
1111 ""
1112 "*
1113{
1114 int start = INTVAL (operands[3]) & 31;
1115 int size = INTVAL (operands[2]) & 31;
1116
df031c43
RK		 1117 if ((start < 16 && start + size <= 16) || start >= 16)
1118 {
1119 operands[3] = gen_rtx (CONST_INT, VOIDmode,
1120 ((1 << (16 - (start & 15)))
1121 - (1 << (16 - (start & 15) - size))));
1122 if (start < 16)
1123 return \"andiu. %0,%1,%3\";
1124 else
1125 return \"andil. %0,%1,%3\";
1126 }
1127
1fd4e8c1
RK		 1128 if (start + size >= 32)
1129 operands[3] = const0_rtx;
1130 else
1131 operands[3] = gen_rtx (CONST_INT, VOIDmode, start + size);
1132 return \"rlinm. %0,%1,%3,%s2,31\";
1133}"
1134 [(set_attr "type" "delayed_compare")])
1135
1136(define_insn "rotlsi3"
1137 [(set (match_operand:SI 0 "gen_reg_operand" "=r")
1138 (rotate:SI (match_operand:SI 1 "gen_reg_operand" "r")
1139 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
1140 ""
1141 "rl%I2nm %0,%1,%h2,0,31")
1142
1143(define_insn ""
1144 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1145 (compare:CC (rotate:SI (match_operand:SI 1 "gen_reg_operand" "r")
1146 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
1147 (const_int 0)))
1148 (clobber (match_scratch:SI 3 "=r"))]
1149 ""
1150 "rl%I2nm. %3,%1,%h2,0,31"
1151 [(set_attr "type" "delayed_compare")])
1152
1153(define_insn ""
1154 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1155 (compare:CC (rotate:SI (match_operand:SI 1 "gen_reg_operand" "r")
1156 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
1157 (const_int 0)))
1158 (set (match_operand:SI 0 "gen_reg_operand" "=r")
1159 (rotate:SI (match_dup 1) (match_dup 2)))]
1160 ""
1161 "rl%I2nm. %0,%1,%h2,0,31"
1162 [(set_attr "type" "delayed_compare")])
1163
1164(define_insn ""
1165 [(set (match_operand:SI 0 "gen_reg_operand" "=r")
1166 (and:SI (rotate:SI (match_operand:SI 1 "gen_reg_operand" "r")
1167 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
1168 (match_operand:SI 3 "mask_operand" "L")))]
1169 ""
1170 "rl%I2nm %0,%1,%h2,%m3,%M3")
1171
1172(define_insn ""
1173 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1174 (compare:CC (and:SI
1175 (rotate:SI (match_operand:SI 1 "gen_reg_operand" "r")
1176 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
1177 (match_operand:SI 3 "mask_operand" "L"))
1178 (const_int 0)))
1179 (clobber (match_scratch:SI 4 "=r"))]
1180 ""
1181 "rl%I2nm. %4,%1,%h2,%m3,%M3"
1182 [(set_attr "type" "delayed_compare")])
1183
1184(define_insn ""
1185 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
1186 (compare:CC (and:SI
1187 (rotate:SI (match_operand:SI 1 "gen_reg_operand" "r")
1188 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
1189 (match_operand:SI 3 "mask_operand" "L"))
1190 (const_int 0)))
1191 (set (match_operand:SI 0 "gen_reg_operand" "=r")
1192 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
1193 ""
1194 "rl%I2nm. %0,%1,%h2,%m3,%M3"
1195 [(set_attr "type" "delayed_compare")])
1196
1197(define_insn ""
1198 [(set (match_operand:SI 0 "gen_reg_operand" "=r")
1199 (zero_extend:SI
1200 (subreg:QI
1201 (rotate:SI (match_operand:SI 1 "gen_reg_operand" "r")
1202 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
1203 ""
1204 "rl%I2nm %0,%1,%h2,24,31")
1205
1206(define_insn ""
1207 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1208 (compare:CC (zero_extend:SI
1209 (subreg:QI
1210 (rotate:SI (match_operand:SI 1 "gen_reg_operand" "r")
1211 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0))
1212 (const_int 0)))
1213 (clobber (match_scratch:SI 3 "=r"))]
1214 ""
1215 "rl%I2nm. %3,%1,%h2,24,31"
1216 [(set_attr "type" "delayed_compare")])
1217
1218(define_insn ""
1219 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1220 (compare:CC (zero_extend:SI
1221 (subreg:QI
1222 (rotate:SI (match_operand:SI 1 "gen_reg_operand" "r")
1223 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0))
1224 (const_int 0)))
1225 (set (match_operand:SI 0 "gen_reg_operand" "=r")
1226 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
1227 ""
1228 "rl%I2nm. %0,%1,%h2,24,31"
1229 [(set_attr "type" "delayed_compare")])
1230
1231(define_insn ""
1232 [(set (match_operand:SI 0 "gen_reg_operand" "=r")
1233 (zero_extend:SI
1234 (subreg:HI
1235 (rotate:SI (match_operand:SI 1 "gen_reg_operand" "r")
1236 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
1237 ""
1238 "rl%I2nm %0,%1,%h2,16,31")
1239
1240(define_insn ""
1241 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1242 (compare:CC (zero_extend:SI
1243 (subreg:HI
1244 (rotate:SI (match_operand:SI 1 "gen_reg_operand" "r")
1245 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0))
1246 (const_int 0)))
1247 (clobber (match_scratch:SI 3 "=r"))]
1248 ""
1249 "rl%I2nm. %3,%1,%h2,16,31"
1250 [(set_attr "type" "delayed_compare")])
1251
1252(define_insn ""
1253 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1254 (compare:CC (zero_extend:SI
1255 (subreg:HI
1256 (rotate:SI (match_operand:SI 1 "gen_reg_operand" "r")
1257 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0))
1258 (const_int 0)))
1259 (set (match_operand:SI 0 "gen_reg_operand" "=r")
1260 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
1261 ""
1262 "rl%I2nm. %0,%1,%h2,16,31"
1263 [(set_attr "type" "delayed_compare")])
1264
1265;; Note that we use "sle." instead of "sl." so that we can set
1266;; SHIFT_COUNT_TRUNCATED.
1267
1268(define_insn "ashlsi3"
1269 [(set (match_operand:SI 0 "gen_reg_operand" "=r,r")
1270 (ashift:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
1271 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
1272 (clobber (match_scratch:SI 3 "=q,X"))]
1273 ""
1274 "@
1275 sle %0,%1,%2
1276 sli %0,%1,%h2")
1277
1278(define_insn ""
1279 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
1280 (compare:CC (ashift:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
1281 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
1282 (const_int 0)))
1283 (clobber (match_scratch:SI 3 "=r,r"))
1284 (clobber (match_scratch:SI 4 "=q,X"))]
1285 ""
1286 "@
1287 sle. %3,%1,%2
1288 sli. %3,%1,%h2"
1289 [(set_attr "type" "delayed_compare")])
1290
1291(define_insn ""
1292 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x")
1293 (compare:CC (ashift:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
1294 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
1295 (const_int 0)))
1296 (set (match_operand:SI 0 "gen_reg_operand" "=r,r")
1297 (ashift:SI (match_dup 1) (match_dup 2)))
1298 (clobber (match_scratch:SI 4 "=q,X"))]
1299 ""
1300 "@
1301 sle. %0,%1,%2
1302 sli. %0,%1,%h2"
1303 [(set_attr "type" "delayed_compare")])
1304
1305(define_insn ""
1306 [(set (match_operand:SI 0 "gen_reg_operand" "=r")
1307 (and:SI (ashift:SI (match_operand:SI 1 "gen_reg_operand" "r")
1308 (match_operand:SI 2 "const_int_operand" "i"))
1309 (match_operand:SI 3 "mask_operand" "L")))]
1310 "includes_lshift_p (operands[2], operands[3])"
1311 "rlinm %0,%h1,%h2,%m3,%M3")
1312
1313(define_insn ""
1314 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1315 (compare:CC
1316 (and:SI (ashift:SI (match_operand:SI 1 "gen_reg_operand" "r")
1317 (match_operand:SI 2 "const_int_operand" "i"))
1318 (match_operand:SI 3 "mask_operand" "L"))
1319 (const_int 0)))
1320 (clobber (match_scratch:SI 4 "=r"))]
1321 "includes_lshift_p (operands[2], operands[3])"
1322 "rlinm. %4,%h1,%h2,%m3,%M3"
1323 [(set_attr "type" "delayed_compare")])
1324
1325(define_insn ""
1326 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
1327 (compare:CC
1328 (and:SI (ashift:SI (match_operand:SI 1 "gen_reg_operand" "r")
1329 (match_operand:SI 2 "const_int_operand" "i"))
1330 (match_operand:SI 3 "mask_operand" "L"))
1331 (const_int 0)))
1332 (set (match_operand:SI 0 "gen_reg_operand" "=r")
1333 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
1334 "includes_lshift_p (operands[2], operands[3])"
1335 "rlinm. %0,%h1,%h2,%m3,%M3"
1336 [(set_attr "type" "delayed_compare")])
1337
5c23c401
RK		 1338;; The RS/6000 assembler mis-handles "sri x,x,0", so write that case as
1339;; "sli x,x,0".
1fd4e8c1
RK		 1340(define_insn "lshrsi3"
1341 [(set (match_operand:SI 0 "gen_reg_operand" "=r,r")
1342 (lshiftrt:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
1343 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
1344 (clobber (match_scratch:SI 3 "=q,X"))]
1345 ""
1346 "@
1347 sre %0,%1,%2
5c23c401 1348 s%A2i %0,%1,%h2")
1fd4e8c1
RK		 1349
1350(define_insn ""
1351 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
1352 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
1353 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
1354 (const_int 0)))
1355 (clobber (match_scratch:SI 3 "=r,r"))
1356 (clobber (match_scratch:SI 4 "=q,X"))]
1357 ""
1358 "@
1359 sre. %3,%1,%2
5c23c401 1360 s%A2i. %3,%1,%h2"
1fd4e8c1
RK		 1361 [(set_attr "type" "delayed_compare")])
1362
1363(define_insn ""
1364 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x")
1365 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
1366 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
1367 (const_int 0)))
1368 (set (match_operand:SI 0 "gen_reg_operand" "=r,r")
1369 (lshiftrt:SI (match_dup 1) (match_dup 2)))
1370 (clobber (match_scratch:SI 4 "=q,X"))]
1371 ""
1372 "@
1373 sre. %0,%1,%2
5c23c401 1374 s%A2i. %0,%1,%h2"
1fd4e8c1
RK		 1375 [(set_attr "type" "delayed_compare")])
1376
1377(define_insn ""
1378 [(set (match_operand:SI 0 "gen_reg_operand" "=r")
1379 (and:SI (lshiftrt:SI (match_operand:SI 1 "gen_reg_operand" "r")
1380 (match_operand:SI 2 "const_int_operand" "i"))
1381 (match_operand:SI 3 "mask_operand" "L")))]
1382 "includes_rshift_p (operands[2], operands[3])"
1383 "rlinm %0,%1,%s2,%m3,%M3")
1384
1385(define_insn ""
1386 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1387 (compare:CC
1388 (and:SI (lshiftrt:SI (match_operand:SI 1 "gen_reg_operand" "r")
1389 (match_operand:SI 2 "const_int_operand" "i"))
1390 (match_operand:SI 3 "mask_operand" "L"))
1391 (const_int 0)))
1392 (clobber (match_scratch:SI 4 "=r"))]
1393 "includes_rshift_p (operands[2], operands[3])"
1394 "rlinm. %4,%1,%s2,%m3,%M3"
1395 [(set_attr "type" "delayed_compare")])
1396
1397(define_insn ""
1398 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
1399 (compare:CC
1400 (and:SI (lshiftrt:SI (match_operand:SI 1 "gen_reg_operand" "r")
1401 (match_operand:SI 2 "const_int_operand" "i"))
1402 (match_operand:SI 3 "mask_operand" "L"))
1403 (const_int 0)))
1404 (set (match_operand:SI 0 "gen_reg_operand" "=r")
1405 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
1406 "includes_rshift_p (operands[2], operands[3])"
1407 "rlinm. %0,%1,%s2,%m3,%M3"
1408 [(set_attr "type" "delayed_compare")])
1409
1410(define_insn ""
1411 [(set (match_operand:SI 0 "gen_reg_operand" "=r")
1412 (zero_extend:SI
1413 (subreg:QI
1414 (lshiftrt:SI (match_operand:SI 1 "gen_reg_operand" "r")
1415 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
1416 "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 255))"
1417 "rlinm %0,%1,%s2,24,31")
1418
1419(define_insn ""
1420 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1421 (compare:CC
1422 (zero_extend:SI
1423 (subreg:QI
1424 (lshiftrt:SI (match_operand:SI 1 "gen_reg_operand" "r")
1425 (match_operand:SI 2 "const_int_operand" "i")) 0))
1426 (const_int 0)))
1427 (clobber (match_scratch:SI 3 "=r"))]
1428 "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 255))"
1429 "rlinm. %3,%1,%s2,24,31"
1430 [(set_attr "type" "delayed_compare")])
1431
1432(define_insn ""
1433 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1434 (compare:CC
1435 (zero_extend:SI
1436 (subreg:QI
1437 (lshiftrt:SI (match_operand:SI 1 "gen_reg_operand" "r")
1438 (match_operand:SI 2 "const_int_operand" "i")) 0))
1439 (const_int 0)))
1440 (set (match_operand:SI 0 "gen_reg_operand" "=r")
1441 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
1442 "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 255))"
1443 "rlinm. %0,%1,%s2,24,31"
1444 [(set_attr "type" "delayed_compare")])
1445
1446(define_insn ""
1447 [(set (match_operand:SI 0 "gen_reg_operand" "=r")
1448 (zero_extend:SI
1449 (subreg:HI
1450 (lshiftrt:SI (match_operand:SI 1 "gen_reg_operand" "r")
1451 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
1452 "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 65535))"
1453 "rlinm %0,%1,%s2,16,31")
1454
1455(define_insn ""
1456 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1457 (compare:CC
1458 (zero_extend:SI
1459 (subreg:HI
1460 (lshiftrt:SI (match_operand:SI 1 "gen_reg_operand" "r")
1461 (match_operand:SI 2 "const_int_operand" "i")) 0))
1462 (const_int 0)))
1463 (clobber (match_scratch:SI 3 "=r"))]
1464 "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 65535))"
1465 "rlinm. %3,%1,%s2,16,31"
1466 [(set_attr "type" "delayed_compare")])
1467
1468(define_insn ""
1469 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1470 (compare:CC
1471 (zero_extend:SI
1472 (subreg:HI
1473 (lshiftrt:SI (match_operand:SI 1 "gen_reg_operand" "r")
1474 (match_operand:SI 2 "const_int_operand" "i")) 0))
1475 (const_int 0)))
1476 (set (match_operand:SI 0 "gen_reg_operand" "=r")
1477 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
1478 "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 65535))"
1479 "rlinm. %0,%1,%s2,16,31"
1480 [(set_attr "type" "delayed_compare")])
1481
1482(define_insn ""
1483 [(set (zero_extract:SI (match_operand:SI 0 "gen_reg_operand" "+r")
1484 (const_int 1)
1485 (match_operand:SI 1 "gen_reg_operand" "r"))
1486 (ashiftrt:SI (match_operand:SI 2 "gen_reg_operand" "r")
1487 (const_int 31)))]
1488 ""
1489 "rrib %0,%1,%2")
1490
1491(define_insn ""
1492 [(set (zero_extract:SI (match_operand:SI 0 "gen_reg_operand" "+r")
1493 (const_int 1)
1494 (match_operand:SI 1 "gen_reg_operand" "r"))
1495 (lshiftrt:SI (match_operand:SI 2 "gen_reg_operand" "r")
1496 (const_int 31)))]
1497 ""
1498 "rrib %0,%1,%2")
1499
1500(define_insn ""
1501 [(set (zero_extract:SI (match_operand:SI 0 "gen_reg_operand" "+r")
1502 (const_int 1)
1503 (match_operand:SI 1 "gen_reg_operand" "r"))
1504 (zero_extract:SI (match_operand:SI 2 "gen_reg_operand" "r")
1505 (const_int 1)
1506 (const_int 0)))]
1507 ""
1508 "rrib %0,%1,%2")
1509
1510(define_insn "ashrsi3"
1511 [(set (match_operand:SI 0 "gen_reg_operand" "=r,r")
1512 (ashiftrt:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
1513 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
1514 (clobber (match_scratch:SI 3 "=q,X"))]
1515 ""
1516 "@
1517 srea %0,%1,%2
1518 srai %0,%1,%h2")
1519
1520(define_insn ""
1521 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
1522 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
1523 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
1524 (const_int 0)))
1525 (clobber (match_scratch:SI 3 "=r,r"))
1526 (clobber (match_scratch:SI 4 "=q,X"))]
1527 ""
1528 "@
1529 srea. %3,%1,%2
1530 srai. %3,%1,%h2"
1531 [(set_attr "type" "delayed_compare")])
1532
1533(define_insn ""
1534 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x")
1535 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
1536 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
1537 (const_int 0)))
1538 (set (match_operand:SI 0 "gen_reg_operand" "=r,r")
1539 (ashiftrt:SI (match_dup 1) (match_dup 2)))
1540 (clobber (match_scratch:SI 4 "=q,X"))]
1541 ""
1542 "@
1543 srea. %0,%1,%2
1544 srai. %0,%1,%h2"
1545 [(set_attr "type" "delayed_compare")])
1546
1547(define_expand "extendqisi2"
1548 [(parallel [(set (match_dup 2)
1549 (ashift:SI (match_operand:QI 1 "gen_reg_operand" "")
1550 (const_int 24)))
1551 (clobber (scratch:SI))])
1552 (parallel [(set (match_operand:SI 0 "gen_reg_operand" "")
1553 (ashiftrt:SI (match_dup 2)
1554 (const_int 24)))
1555 (clobber (scratch:SI))])]
1556 ""
1557 "
1558{ operands[1] = gen_lowpart (SImode, operands[1]);
1559 operands[2] = gen_reg_rtx (SImode); }")
1560
1561(define_expand "extendqihi2"
1562 [(parallel [(set (match_dup 2)
1563 (ashift:SI (match_operand:QI 1 "gen_reg_operand" "")
1564 (const_int 24)))
1565 (clobber (scratch:SI))])
1566 (parallel [(set (match_operand:HI 0 "gen_reg_operand" "")
1567 (ashiftrt:SI (match_dup 2)
1568 (const_int 24)))
1569 (clobber (scratch:SI))])]
1570 ""
1571 "
1572{ operands[0] = gen_lowpart (SImode, operands[0]);
1573 operands[1] = gen_lowpart (SImode, operands[1]);
1574 operands[2] = gen_reg_rtx (SImode); }")
1575\f
1576;; Floating-point insns, excluding normal data motion.
1577;;
1578;; We pretend that we have both SFmode and DFmode insns, while, in fact,
1579;; all fp insns are actually done in double. The only conversions we will
1580;; do will be when storing to memory. In that case, we will use the "frsp"
1581;; instruction before storing.
1582;;
1583;; Note that when we store into a single-precision memory location, we need to
1584;; use the frsp insn first. If the register being stored isn't dead, we
1585;; need a scratch register for the frsp. But this is difficult when the store
1586;; is done by reload. It is not incorrect to do the frsp on the register in
1587;; this case, we just lose precision that we would have otherwise gotten but
1588;; is not guaranteed. Perhaps this should be tightened up at some point.
1589
1590(define_insn "extendsfdf2"
1591 [(set (match_operand:DF 0 "gen_reg_operand" "=f")
1592 (float_extend:DF (match_operand:SF 1 "gen_reg_operand" "f")))]
1593 ""
1594 "*
1595{
1596 if (REGNO (operands[0]) == REGNO (operands[1]))
1597 return \"\";
1598 else
1599 return \"fmr %0,%1\";
1600}"
1601 [(set_attr "type" "fp")])
1602
1603(define_insn "truncdfsf2"
1604 [(set (match_operand:SF 0 "gen_reg_operand" "=f")
1605 (float_truncate:SF (match_operand:DF 1 "gen_reg_operand" "f")))]
1606 ""
1607 "*
1608{
1609 if (REGNO (operands[0]) == REGNO (operands[1]))
1610 return \"\";
1611 else
1612 return \"fmr %0,%1\";
1613}"
1614 [(set_attr "type" "fp")])
1615
1616(define_insn "negsf2"
1617 [(set (match_operand:SF 0 "gen_reg_operand" "=f")
1618 (neg:SF (match_operand:SF 1 "gen_reg_operand" "f")))]
1619 ""
1620 "fneg %0,%1"
1621 [(set_attr "type" "fp")])
1622
1623(define_insn "abssf2"
1624 [(set (match_operand:SF 0 "gen_reg_operand" "=f")
1625 (abs:SF (match_operand:SF 1 "gen_reg_operand" "f")))]
1626 ""
1627 "fabs %0,%1"
1628 [(set_attr "type" "fp")])
1629
1630(define_insn ""
1631 [(set (match_operand:SF 0 "gen_reg_operand" "=f")
1632 (neg:SF (abs:SF (match_operand:SF 1 "gen_reg_operand" "f"))))]
1633 ""
1634 "fnabs %0,%1"
1635 [(set_attr "type" "fp")])
1636
1637(define_insn "addsf3"
1638 [(set (match_operand:SF 0 "gen_reg_operand" "=f")
1639 (plus:SF (match_operand:SF 1 "gen_reg_operand" "%f")
1640 (match_operand:SF 2 "gen_reg_operand" "f")))]
1641 ""
1642 "fa %0,%1,%2"
1643 [(set_attr "type" "fp")])
1644
1645(define_insn "subsf3"
1646 [(set (match_operand:SF 0 "gen_reg_operand" "=f")
1647 (minus:SF (match_operand:SF 1 "gen_reg_operand" "f")
1648 (match_operand:SF 2 "gen_reg_operand" "f")))]
1649 ""
1650 "fs %0,%1,%2"
1651 [(set_attr "type" "fp")])
1652
1653(define_insn "mulsf3"
1654 [(set (match_operand:SF 0 "gen_reg_operand" "=f")
1655 (mult:SF (match_operand:SF 1 "gen_reg_operand" "%f")
1656 (match_operand:SF 2 "gen_reg_operand" "f")))]
1657 ""
1658 "fm %0,%1,%2"
1659 [(set_attr "type" "fp")])
1660
1661(define_insn "divsf3"
1662 [(set (match_operand:SF 0 "gen_reg_operand" "=f")
1663 (div:SF (match_operand:SF 1 "gen_reg_operand" "f")
1664 (match_operand:SF 2 "gen_reg_operand" "f")))]
1665 ""
1666 "fd %0,%1,%2"
1667 [(set_attr "type" "fp")])
1668
1669(define_insn ""
1670 [(set (match_operand:SF 0 "gen_reg_operand" "=f")
1671 (plus:SF (mult:SF (match_operand:SF 1 "gen_reg_operand" "%f")
1672 (match_operand:SF 2 "gen_reg_operand" "f"))
1673 (match_operand:SF 3 "gen_reg_operand" "f")))]
1674 ""
1675 "fma %0,%1,%2,%3"
1676 [(set_attr "type" "fp")])
1677
1678(define_insn ""
1679 [(set (match_operand:SF 0 "gen_reg_operand" "=f")
1680 (minus:SF (mult:SF (match_operand:SF 1 "gen_reg_operand" "%f")
1681 (match_operand:SF 2 "gen_reg_operand" "f"))
1682 (match_operand:SF 3 "gen_reg_operand" "f")))]
1683 ""
1684 "fms %0,%1,%2,%3"
1685 [(set_attr "type" "fp")])
1686
1687(define_insn ""
1688 [(set (match_operand:SF 0 "gen_reg_operand" "=f")
1689 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gen_reg_operand" "%f")
1690 (match_operand:SF 2 "gen_reg_operand" "f"))
1691 (match_operand:SF 3 "gen_reg_operand" "f"))))]
1692 ""
1693 "fnma %0,%1,%2,%3"
1694 [(set_attr "type" "fp")])
1695
1696(define_insn ""
1697 [(set (match_operand:SF 0 "gen_reg_operand" "=f")
1698 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gen_reg_operand" "%f")
1699 (match_operand:SF 2 "gen_reg_operand" "f"))
1700 (match_operand:SF 3 "gen_reg_operand" "f"))))]
1701 ""
1702 "fnms %0,%1,%2,%3"
1703 [(set_attr "type" "fp")])
1704
1705(define_insn "negdf2"
1706 [(set (match_operand:DF 0 "gen_reg_operand" "=f")
1707 (neg:DF (match_operand:DF 1 "gen_reg_operand" "f")))]
1708 ""
1709 "fneg %0,%1"
1710 [(set_attr "type" "fp")])
1711
1712(define_insn "absdf2"
1713 [(set (match_operand:DF 0 "gen_reg_operand" "=f")
1714 (abs:DF (match_operand:DF 1 "gen_reg_operand" "f")))]
1715 ""
1716 "fabs %0,%1"
1717 [(set_attr "type" "fp")])
1718
1719(define_insn ""
1720 [(set (match_operand:DF 0 "gen_reg_operand" "=f")
1721 (neg:DF (abs:DF (match_operand:DF 1 "gen_reg_operand" "f"))))]
1722 ""
1723 "fnabs %0,%1"
1724 [(set_attr "type" "fp")])
1725
1726(define_insn "adddf3"
1727 [(set (match_operand:DF 0 "gen_reg_operand" "=f")
1728 (plus:DF (match_operand:DF 1 "gen_reg_operand" "%f")
1729 (match_operand:DF 2 "gen_reg_operand" "f")))]
1730 ""
1731 "fa %0,%1,%2"
1732 [(set_attr "type" "fp")])
1733
1734(define_insn "subdf3"
1735 [(set (match_operand:DF 0 "gen_reg_operand" "=f")
1736 (minus:DF (match_operand:DF 1 "gen_reg_operand" "f")
1737 (match_operand:DF 2 "gen_reg_operand" "f")))]
1738 ""
1739 "fs %0,%1,%2"
1740 [(set_attr "type" "fp")])
1741
1742(define_insn "muldf3"
1743 [(set (match_operand:DF 0 "gen_reg_operand" "=f")
1744 (mult:DF (match_operand:DF 1 "gen_reg_operand" "%f")
1745 (match_operand:DF 2 "gen_reg_operand" "f")))]
1746 ""
1747 "fm %0,%1,%2"
1748 [(set_attr "type" "fp")])
1749
1750(define_insn "divdf3"
1751 [(set (match_operand:DF 0 "gen_reg_operand" "=f")
1752 (div:DF (match_operand:DF 1 "gen_reg_operand" "f")
1753 (match_operand:DF 2 "gen_reg_operand" "f")))]
1754 ""
1755 "fd %0,%1,%2"
1756 [(set_attr "type" "fp")])
1757
1758(define_insn ""
1759 [(set (match_operand:DF 0 "gen_reg_operand" "=f")
1760 (plus:DF (mult:DF (match_operand:DF 1 "gen_reg_operand" "%f")
1761 (match_operand:DF 2 "gen_reg_operand" "f"))
1762 (match_operand:DF 3 "gen_reg_operand" "f")))]
1763 ""
1764 "fma %0,%1,%2,%3"
1765 [(set_attr "type" "fp")])
1766
1767(define_insn ""
1768 [(set (match_operand:DF 0 "gen_reg_operand" "=f")
1769 (minus:DF (mult:DF (match_operand:DF 1 "gen_reg_operand" "%f")
1770 (match_operand:DF 2 "gen_reg_operand" "f"))
1771 (match_operand:DF 3 "gen_reg_operand" "f")))]
1772 ""
1773 "fms %0,%1,%2,%3"
1774 [(set_attr "type" "fp")])
1775
1776(define_insn ""
1777 [(set (match_operand:DF 0 "gen_reg_operand" "=f")
1778 (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gen_reg_operand" "%f")
1779 (match_operand:DF 2 "gen_reg_operand" "f"))
1780 (match_operand:DF 3 "gen_reg_operand" "f"))))]
1781 ""
1782 "fnma %0,%1,%2,%3"
1783 [(set_attr "type" "fp")])
1784
1785(define_insn ""
1786 [(set (match_operand:DF 0 "gen_reg_operand" "=f")
1787 (neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gen_reg_operand" "%f")
1788 (match_operand:DF 2 "gen_reg_operand" "f"))
1789 (match_operand:DF 3 "gen_reg_operand" "f"))))]
1790 ""
1791 "fnms %0,%1,%2,%3"
1792 [(set_attr "type" "fp")])
1793\f
1794;; Conversions to and from floating-point.
1795(define_expand "floatsidf2"
1796 [(set (match_dup 2)
1797 (plus:DI (zero_extend:DI
1798 (xor:SI (match_operand:SI 1 "gen_reg_operand" "")
1799 (match_dup 3)))
1800 (match_dup 4)))
1801 (set (match_operand:DF 0 "gen_reg_operand" "")
1802 (minus:DF (subreg:DF (match_dup 2) 0)
1803 (match_dup 5)))]
1804 ""
1805 "
1806{
1807#if HOST_BITS_PER_INT != BITS_PER_WORD
1808 /* Maybe someone can figure out how to do this in that case. I don't
1809 want to right now. */
1810 abort ();
1811#endif
1812
1813 operands[2] = gen_reg_rtx (DImode);
1814 operands[3] = gen_rtx (CONST_INT, VOIDmode, 0x80000000);
1815 operands[4] = immed_double_const (0, 0x43300000, DImode);
1816 operands[5] = force_reg (DFmode, immed_double_const (0x43300000,
1817 0x80000000, DFmode));
1818}")
1819
1820(define_expand "floatunssidf2"
1821 [(set (match_dup 2)
1822 (plus:DI (zero_extend:DI (match_operand:SI 1 "gen_reg_operand" ""))
1823 (match_dup 3)))
1824 (set (match_operand:DF 0 "gen_reg_operand" "")
1825 (minus:DF (subreg:DF (match_dup 2) 0)
1826 (match_dup 4)))]
1827 ""
1828 "
1829{
1830#if HOST_BITS_PER_INT != BITS_PER_WORD
1831 /* Maybe someone can figure out how to do this in that case. I don't
1832 want to right now. */
1833 abort ();
1834#endif
1835
1836 operands[2] = gen_reg_rtx (DImode);
1837 operands[3] = immed_double_const (0, 0x43300000, DImode);
1838 operands[4] = force_reg (DFmode, immed_double_const (0x43300000, 0, DFmode));
1839}")
1840
1841;; For the above two cases, we always split.
1842(define_split
1843 [(set (match_operand:DI 0 "gen_reg_operand" "")
1844 (plus:DI (zero_extend:DI
1845 (xor:SI (match_operand:SI 1 "gen_reg_operand" "")
1846 (match_operand:SI 2 "logical_operand" "")))
1847 (match_operand:DI 3 "immediate_operand" "")))]
1848 "reload_completed && HOST_BITS_PER_INT == BITS_PER_WORD
1849 && GET_CODE (operands[3]) == CONST_DOUBLE
1850 && CONST_DOUBLE_LOW (operands[3]) == 0"
1851 [(set (match_dup 6) (xor:SI (match_dup 1) (match_dup 2)))
1852 (set (match_dup 4) (match_dup 5))]
1853 "
1854{ operands[4] = operand_subword (operands[0], 0, 0, DImode);
1855 operands[5] = operand_subword (operands[3], 0, 0, DImode);
1856 operands[6] = operand_subword (operands[0], 1, 0, DImode);
1857}")
1858
1859(define_insn ""
1860 [(set (match_operand:DI 0 "gen_reg_operand" "=r")
1861 (plus:DI (zero_extend:DI
1862 (xor:SI (match_operand:SI 1 "gen_reg_operand" "%r")
1863 (match_operand:SI 2 "logical_operand" "rKJ")))
1864 (match_operand:DI 3 "immediate_operand" "n")))]
1865 "HOST_BITS_PER_INT == BITS_PER_WORD
1866 && GET_CODE (operands[3]) == CONST_DOUBLE
1867 && CONST_DOUBLE_LOW (operands[3]) == 0"
1868 "#")
1869
1870(define_split
1871 [(set (match_operand:DI 0 "gen_reg_operand" "=")
1872 (plus:DI (zero_extend:DI (match_operand:SI 1 "gen_reg_operand" ""))
1873 (match_operand:DI 2 "immediate_operand" "")))]
1874 "reload_completed && HOST_BITS_PER_INT == BITS_PER_WORD
1875 && GET_CODE (operands[2]) == CONST_DOUBLE
1876 && CONST_DOUBLE_LOW (operands[2]) == 0"
1877 [(set (match_dup 3) (match_dup 4))
1878 (set (match_dup 5) (match_dup 1))]
1879 "
1880{ operands[3] = operand_subword (operands[0], 0, 0, DImode);
1881 operands[4] = operand_subword (operands[2], 0, 0, DImode);
1882 operands[5] = operand_subword (operands[0], 1, 0, DImode);
1883
1884 if (rtx_equal_p (operands[1], operands[5]))
1885 {
1886 emit_move_insn (operands[3], operands[4]);
1887 DONE;
1888 }
1889}")
1890
1891(define_insn ""
1892 [(set (match_operand:DI 0 "gen_reg_operand" "=r")
1893 (plus:DI (zero_extend:DI (match_operand:SI 1 "gen_reg_operand" "r"))
1894 (match_operand:DI 2 "immediate_operand" "n")))]
1895 "HOST_BITS_PER_INT == BITS_PER_WORD
1896 && GET_CODE (operands[2]) == CONST_DOUBLE
1897 && CONST_DOUBLE_LOW (operands[2]) == 0"
1898 "#")
1899
1900(define_expand "fix_truncdfsi2"
1901 [(set (match_operand:SI 0 "gen_reg_operand" "")
1902 (fix:DF (match_operand:DF 1 "gen_reg_operand" "")))]
1903 ""
1904 "
1905{
1906 emit_insn (gen_trunc_call (operands[0], operands[1],
1907 gen_rtx (SYMBOL_REF, Pmode, \"itrunc\")));
1908 DONE;
1909}")
1910
1911(define_expand "fixuns_truncdfsi2"
1912 [(set (match_operand:SI 0 "gen_reg_operand" "")
1913 (unsigned_fix:DF (match_operand:DF 1 "gen_reg_operand" "")))]
1914 ""
1915 "
1916{
1917 emit_insn (gen_trunc_call (operands[0], operands[1],
1918 gen_rtx (SYMBOL_REF, Pmode, \"uitrunc\")));
1919 DONE;
1920}")
1921
1922
1923(define_expand "trunc_call"
1924 [(parallel [(set (match_operand:SI 0 "" "")
1925 (fix:DF (match_operand:DF 1 "" "")))
1926 (use (match_operand:SI 2 "" ""))])]
1927 ""
1928 "
1929{
1930 rtx insns = gen_trunc_call_rtl (operands[0], operands[1], operands[2]);
1931 rtx first = XVECEXP (insns, 0, 0);
1932 rtx last = XVECEXP (insns, 0, XVECLEN (insns, 0) - 1);
1933
1934 REG_NOTES (first) = gen_rtx (INSN_LIST, REG_LIBCALL, last,
1935 REG_NOTES (first));
1936 REG_NOTES (last) = gen_rtx (INSN_LIST, REG_RETVAL, first, REG_NOTES (last));
1937
1938 emit_insn (insns);
1939 DONE;
1940}")
1941
1942(define_expand "trunc_call_rtl"
1943 [(set (reg:DF 33) (match_operand:DF 1 "gen_reg_operand" ""))
1944 (use (reg:DF 33))
1945 (parallel [(set (reg:SI 3)
1946 (call (mem:SI (match_operand 2 "" "")) (const_int 0)))
1947 (clobber (scratch:SI))])
1948 (set (match_operand:SI 0 "gen_reg_operand" "")
1949 (reg:SI 3))]
1950 ""
1951 "
1952{
1953 rs6000_trunc_used = 1;
1954}")
1955\f
1956;; Define the DImode operations that can be done in a small number
1957;; of instructions.
1958(define_insn "adddi3"
1959 [(set (match_operand:DI 0 "gen_reg_operand" "=r")
1960 (plus:DI (match_operand:DI 1 "gen_reg_operand" "%r")
1961 (match_operand:DI 2 "gen_reg_operand" "r")))]
1962 ""
1963 "a %L0,%L1,%L2\;ae %0,%1,%2")
1964
1965(define_insn "subdi3"
1966 [(set (match_operand:DI 0 "gen_reg_operand" "=r")
1967 (minus:DI (match_operand:DI 1 "gen_reg_operand" "r")
1968 (match_operand:DI 2 "gen_reg_operand" "r")))]
1969 ""
1970 "sf %L0,%L2,%L1\;sfe %0,%2,%1")
1971
1972(define_insn "negdi3"
1973 [(set (match_operand:DI 0 "gen_reg_operand" "=r")
1974 (neg:DI (match_operand:DI 1 "gen_reg_operand" "r")))]
1975 ""
1976 "sfi %L0,%L1,0\;sfze %0,%1")
1977
1978(define_insn "mulsidi3"
1979 [(set (match_operand:DI 0 "gen_reg_operand" "=r")
1980 (mult:DI (sign_extend:DI (match_operand:SI 1 "gen_reg_operand" "r"))
1981 (sign_extend:DI (match_operand:SI 2 "gen_reg_operand" "r"))))
1982 (clobber (match_scratch:SI 3 "=q"))]
1983 ""
1984 "mul %0,%1,%2\;mfmq %L0")
1985
1986;; If operands 0 and 2 are in the same register, we have a problem. But
1987;; operands 0 and 1 (the usual case) can be in the same register. That's
1988;; why we have the strange constraints below.
1989(define_insn "ashldi3"
1990 [(set (match_operand:DI 0 "gen_reg_operand" "=r,r,r,&r")
1991 (ashift:DI (match_operand:DI 1 "gen_reg_operand" "r,r,0,r")
1992 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
1993 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
1994 ""
1995 "@
1996 sli %0,%L1,%h2\;cal %L0,0(0)
1997 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
1998 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
5c23c401 1999 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2")
1fd4e8c1
RK		 2000
2001(define_insn "lshrdi3"
5c23c401 2002 [(set (match_operand:DI 0 "gen_reg_operand" "=&r,r,r,&r")
1fd4e8c1
RK		 2003 (lshiftrt:DI (match_operand:DI 1 "gen_reg_operand" "r,r,0,r")
2004 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
2005 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
2006 ""
2007 "@
5c23c401 2008 cal %0,0(0)\;s%A2i %L0,%1,%h2
46a48c7f
RK		 2009 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
2010 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
2011 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2")
1fd4e8c1
RK		 2012
2013;; Shift by a variable amount is too complex to be worth open-coding. We
2014;; just handle shifts by constants.
2015
2016(define_expand "ashrdi3"
2017 [(parallel [(set (match_operand:DI 0 "gen_reg_operand" "=")
2018 (ashiftrt:DI (match_operand:DI 1 "gen_reg_operand" "")
2019 (match_operand:SI 2 "general_operand" "")))
2020 (clobber (match_scratch:SI 3 ""))])]
2021 ""
2022 "
2023{ if (GET_CODE (operands[2]) != CONST_INT)
2024 FAIL;
2025}")
2026
2027(define_insn ""
2028 [(set (match_operand:DI 0 "gen_reg_operand" "=r,r")
2029 (ashiftrt:DI (match_operand:DI 1 "gen_reg_operand" "r,r")
2030 (match_operand:SI 2 "const_int_operand" "M,i")))
2031 (clobber (match_scratch:SI 3 "=X,q"))]
2032 ""
2033 "@
2034 srai %0,%1,31\;srai %L0,%1,%h2
46a48c7f 2035 sraiq %0,%1,%h2\;srliq %L0,%L1,%h2")
1fd4e8c1
RK		 2036\f
2037;; Now define ways of moving data around.
2038;;
2039;; For SI, we special-case integers that can't be loaded in one insn. We
2040;; do the load 16-bits at a time. We could do this by loading from memory,
2041;; and this is even supposed to be faster, but it is simpler not to get
2042;; integers in the TOC.
2043(define_expand "movsi"
2044 [(set (match_operand:SI 0 "general_operand" "")
2045 (match_operand:SI 1 "any_operand" ""))]
2046 ""
2047 "
2048{
2049 if (GET_CODE (operands[0]) != REG)
2050 operands[1] = force_reg (SImode, operands[1]);
2051
2052 if (CONSTANT_P (operands[1]) && GET_CODE (operands[1]) != CONST_INT)
2053 operands[1] = force_const_mem (SImode, operands[1]);
2054
2055 if (GET_CODE (operands[1]) == CONST_INT
2056 && (unsigned) (INTVAL (operands[1]) + 0x8000) >= 0x10000
2057 && (INTVAL (operands[1]) & 0xffff) != 0)
2058 {
2059 emit_move_insn (operands[0],
2060 gen_rtx (CONST_INT, VOIDmode,
2061 INTVAL (operands[1]) & 0xffff0000));
2062 emit_insn (gen_iorsi3 (operands[0], operands[0],
2063 gen_rtx (CONST_INT, VOIDmode,
2064 INTVAL (operands[1]) & 0xffff)));
2065 DONE;
2066 }
2067}")
2068
2069(define_insn ""
5c23c401
RK		 2070 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,m,r,r,r,*c*q,*l")
2071 (match_operand:SI 1 "input_operand" "r,m,r,I,J,*h,r,r"))]
1fd4e8c1
RK		 2072 "gen_reg_operand (operands[0], SImode)
2073 || gen_reg_operand (operands[1], SImode)"
2074 "@
2075 ai %0,%1,0
2076 l%U1%X1 %0,%1
2077 st%U0%X0 %1,%0
2078 cal %0,%1(0)
2079 cau %0,0,%u1
2080 mf%1 %0
5c23c401 2081 mt%0 %1
1fd4e8c1 2082 mt%0 %1"
5c23c401 2083 [(set_attr "type" "*,load,*,*,*,*,*,mtlr")])
1fd4e8c1
RK		 2084
2085(define_insn ""
2086 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
2087 (compare:CC (match_operand:SI 1 "gen_reg_operand" "r")
2088 (const_int 0)))
2089 (set (match_operand:SI 0 "gen_reg_operand" "=r") (match_dup 1))]
2090 ""
2091 "ai. %0,%1,0"
2092 [(set_attr "type" "compare")])
2093\f
2094(define_expand "movhi"
2095 [(set (match_operand:HI 0 "general_operand" "")
2096 (match_operand:HI 1 "any_operand" ""))]
2097 ""
2098 "
2099{
2100 if (GET_CODE (operands[0]) != REG)
2101 operands[1] = force_reg (HImode, operands[1]);
2102
2103 if (CONSTANT_P (operands[1]) && GET_CODE (operands[1]) != CONST_INT)
2104 operands[1] = force_const_mem (HImode, operands[1]);
2105}")
2106
2107(define_insn ""
2108 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*h")
2109 (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r"))]
2110 "gen_reg_operand (operands[0], HImode)
2111 || gen_reg_operand (operands[1], HImode)"
2112 "@
2113 oril %0,%1,0
2114 lhz%U1%X1 %0,%1
2115 sth%U0%X0 %1,%0
2116 cal %0,%w1(0)
2117 mf%1 %0
2118 mt%0 %1"
2119 [(set_attr "type" "*,load,*,*,*,*")])
2120
2121(define_expand "movqi"
2122 [(set (match_operand:QI 0 "general_operand" "")
2123 (match_operand:QI 1 "any_operand" ""))]
2124 ""
2125 "
2126{
2127 if (GET_CODE (operands[0]) != REG)
2128 operands[1] = force_reg (QImode, operands[1]);
2129
2130 if (CONSTANT_P (operands[1]) && GET_CODE (operands[1]) != CONST_INT)
2131 operands[1] = force_const_mem (QImode, operands[1]);
2132}")
2133
2134(define_insn ""
2135 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*h")
2136 (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r"))]
2137 "gen_reg_operand (operands[0], QImode)
2138 || gen_reg_operand (operands[1], QImode)"
2139 "@
2140 oril %0,%1,0
2141 lbz%U1%X1 %0,%1
2142 stb%U0%X0 %1,%0
2143 cal %0,%1(0)
2144 mf%1 %0
2145 mt%0 %1"
2146 [(set_attr "type" "*,load,*,*,*,*")])
2147\f
2148;; Here is how to move condition codes around. When we store CC data in
2149;; an integer register or memory, we store just the high-order 4 bits.
2150;; This lets us not shift in the most common case of CR0.
2151(define_expand "movcc"
2152 [(set (match_operand:CC 0 "nonimmediate_operand" "")
2153 (match_operand:CC 1 "nonimmediate_operand" ""))]
2154 ""
2155 "")
2156
2157(define_insn ""
2158 [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,y,r,r,r,r,m")
2159 (match_operand:CC 1 "nonimmediate_operand" "y,r,r,x,y,r,m,r"))]
2160 "register_operand (operands[0], CCmode)
2161 || register_operand (operands[1], CCmode)"
2162 "@
2163 mcrf %0,%1
2164 mtcrf 128,%1
2165 rlinm %1,%1,%F0,0,31\;mtcrf %R0,%1\;rlinm %1,%1,%f0,0,31
2166 mfcr %0
2167 mfcr %0\;rlinm %0,%0,%f1,0,3
2168 ai %0,%1,0
2169 l%U1%X1 %0,%1
2170 st%U0%U1 %1,%0"
2171 [(set_attr "type" "*,*,*,compare,*,*,load,*")])
2172\f
2173;; For floating-point, we normally deal with the floating-point registers.
2174;; The sole exception is that parameter passing can produce floating-point
2175;; values in fixed-point registers. Unless the value is a simple constant
2176;; or already in memory, we deal with this by allocating memory and copying
2177;; the value explicitly via that memory location.
2178(define_expand "movsf"
2179 [(set (match_operand:SF 0 "nonimmediate_operand" "")
2180 (match_operand:SF 1 "any_operand" ""))]
2181 ""
2182 "
2183{
2184 /* If we are called from reload, we might be getting a SUBREG of a hard
2185 reg. So expand it. */
2186 if (GET_CODE (operands[0]) == SUBREG
2187 && GET_CODE (SUBREG_REG (operands[0])) == REG
2188 && REGNO (SUBREG_REG (operands[0])) < FIRST_PSEUDO_REGISTER)
2189 operands[0] = alter_subreg (operands[0]);
2190 if (GET_CODE (operands[1]) == SUBREG
2191 && GET_CODE (SUBREG_REG (operands[1])) == REG
2192 && REGNO (SUBREG_REG (operands[1])) < FIRST_PSEUDO_REGISTER)
2193 operands[1] = alter_subreg (operands[1]);
2194
2195 /* If we are being called from reload, it is possible that operands[1]
2196 is a hard non-fp register. So handle those cases. */
2197 if (reload_in_progress && GET_CODE (operands[1]) == REG
2198 && REGNO (operands[1]) < 32)
2199 {
2200 rtx stack_slot;
2201
2202 /* Remember that we only see a pseudo here if it didn't get a hard
2203 register, so it is memory. */
2204 if (GET_CODE (operands[0]) == MEM
2205 || (GET_CODE (operands[0]) == REG
2206 && (REGNO (operands[0]) < 32
2207 || REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER))
2208 || (GET_CODE (operands[0]) == REG && REGNO (operands[0]) < 32))
2209 {
2210 emit_move_insn (operand_subword (operands[0], 0, 0, SFmode),
2211 operand_subword (operands[1], 0, 0, SFmode));
2212 DONE;
2213 }
2214
2215 stack_slot = gen_rtx (MEM, SFmode, plus_constant (stack_pointer_rtx, 4));
2216 emit_move_insn (stack_slot, operands[1]);
2217 emit_move_insn (operands[0], stack_slot);
2218 DONE;
2219 }
2220
2221 if (GET_CODE (operands[0]) == MEM)
2222 operands[1] = force_reg (SFmode, operands[1]);
2223
2224 if (GET_CODE (operands[0]) == REG && REGNO (operands[0]) < 32)
2225 {
2226 rtx stack_slot;
2227
2228 if (GET_CODE (operands[1]) == MEM
2229#if HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT && ! defined(REAL_IS_NOT_DOUBLE)
2230 || GET_CODE (operands[1]) == CONST_DOUBLE
2231#endif
2232 || (GET_CODE (operands[1]) == REG && REGNO (operands[1]) < 32)
2233 || (reload_in_progress && GET_CODE (operands[1]) == REG
2234 && REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER))
2235 {
2236 emit_move_insn (operand_subword (operands[0], 0, 0, SFmode),
2237 operand_subword (operands[1], 0, 0, SFmode));
2238 DONE;
2239 }
2240
2241 if (reload_in_progress)
2242 stack_slot = gen_rtx (MEM, SFmode,
2243 plus_constant (stack_pointer_rtx, 4));
2244 else
2245 stack_slot = assign_stack_temp (SFmode, 4, 0);
2246 emit_move_insn (stack_slot, operands[1]);
2247 emit_move_insn (operands[0], stack_slot);
2248 DONE;
2249 }
2250
2251 if (CONSTANT_P (operands[1]))
2252 {
2253 operands[1] = force_const_mem (SFmode, operands[1]);
2254 if (! memory_address_p (SFmode, XEXP (operands[1], 0))
2255 && ! reload_in_progress)
2256 operands[1] = change_address (operands[1], SFmode,
2257 XEXP (operands[1], 0));
2258 }
2259}")
2260
2261(define_insn ""
2262 [(set (match_operand:SF 0 "gen_reg_operand" "=r,r")
2263 (match_operand:SF 1 "mem_or_easy_const_operand" "G,m"))]
2264 "REGNO (operands[0]) <= 31"
2265 "@
2266 #
2267 l%U1%X1 %0,%1"
2268 [(set_attr "type" "*,load")])
2269
2270(define_split
2271 [(set (match_operand:SF 0 "gen_reg_operand" "")
2272 (match_operand:SF 1 "easy_fp_constant" ""))]
2273 "reload_completed && REGNO (operands[0]) <= 31"
2274 [(set (match_dup 2) (match_dup 3))]
2275 "
2276{ operands[2] = operand_subword (operands[0], 0, 0, SFmode);
2277 operands[3] = operand_subword (operands[1], 0, 0, SFmode); }")
2278
2279(define_insn ""
2280 [(set (match_operand:SF 0 "fp_reg_or_mem_operand" "=f,f,m")
2281 (match_operand:SF 1 "input_operand" "f,m,f"))]
2282 "gen_reg_operand (operands[0], SFmode)
2283 || gen_reg_operand (operands[1], SFmode)"
2284 "@
2285 fmr %0,%1
2286 lfs%U1%X1 %0,%1
2287 frsp %1,%1\;stfs%U0%X0 %1,%0"
2288 [(set_attr "type" "fp,load,*")])
2289\f
2290(define_expand "movdf"
2291 [(set (match_operand:DF 0 "nonimmediate_operand" "")
2292 (match_operand:DF 1 "any_operand" ""))]
2293 ""
2294 "
2295{
2296 /* If we are called from reload, we might be getting a SUBREG of a hard
2297 reg. So expand it. */
2298 if (GET_CODE (operands[0]) == SUBREG
2299 && GET_CODE (SUBREG_REG (operands[0])) == REG
2300 && REGNO (SUBREG_REG (operands[0])) < FIRST_PSEUDO_REGISTER)
2301 operands[0] = alter_subreg (operands[0]);
2302 if (GET_CODE (operands[1]) == SUBREG
2303 && GET_CODE (SUBREG_REG (operands[1])) == REG
2304 && REGNO (SUBREG_REG (operands[1])) < FIRST_PSEUDO_REGISTER)
2305 operands[1] = alter_subreg (operands[1]);
2306
2307 /* If we are being called from reload, it is possible that operands[1]
2308 is a hard non-fp register. So handle those cases. */
2309 if (reload_in_progress && GET_CODE (operands[1]) == REG
2310 && REGNO (operands[1]) < 32)
2311 {
2312 rtx stack_slot;
2313
2314 /* Remember that we only see a pseudo here if it didn't get a hard
2315 register, so it is memory. */
2316 if (GET_CODE (operands[0]) == MEM
2317 || (GET_CODE (operands[0]) == REG
2318 && (REGNO (operands[0]) < 32
2319 || REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER)))
2320 {
2321 emit_move_insn (operand_subword (operands[0], 0, 0, DFmode),
2322 operand_subword (operands[1], 0, 0, DFmode));
2323 emit_move_insn (operand_subword (operands[0], 1, 0, DFmode),
2324 operand_subword (operands[1], 1, 0, DFmode));
2325 DONE;
2326 }
2327
2328 stack_slot = gen_rtx (MEM, DFmode, plus_constant (stack_pointer_rtx, 8));
2329 emit_move_insn (stack_slot, operands[1]);
2330 emit_move_insn (operands[0], stack_slot);
2331 DONE;
2332 }
2333
2334 if (GET_CODE (operands[0]) == MEM)
2335 {
2336 if (GET_CODE (operands[1]) == MEM)
2337 {
2338 emit_move_insn (operand_subword (operands[0], 0, 0, DFmode),
2339 operand_subword (operands[1], 0, 0, DFmode));
2340 emit_move_insn (operand_subword (operands[0], 1, 0, DFmode),
2341 operand_subword (operands[1], 1, 0, DFmode));
2342 DONE;
2343 }
2344
2345 operands[1] = force_reg (DFmode, operands[1]);
2346 }
2347
2348 if (GET_CODE (operands[0]) == REG && REGNO (operands[0]) < 32)
2349 {
2350 rtx stack_slot;
2351
2352 if (GET_CODE (operands[1]) == MEM
2353#if HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT && ! defined(REAL_IS_NOT_DOUBLE)
2354 || GET_CODE (operands[1]) == CONST_DOUBLE
2355#endif
2356 || (GET_CODE (operands[1]) == REG && REGNO (operands[1]) < 32)
2357 || (reload_in_progress && GET_CODE (operands[1]) == REG
2358 && REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER))
2359 {
2360 emit_move_insn (operand_subword (operands[0], 0, 0, DFmode),
2361 operand_subword (operands[1], 0, 0, DFmode));
2362 emit_move_insn (operand_subword (operands[0], 1, 0, DFmode),
2363 operand_subword (operands[1], 1, 0, DFmode));
2364 DONE;
2365 }
2366
2367 if (reload_in_progress)
2368 stack_slot = gen_rtx (MEM, DFmode,
2369 plus_constant (stack_pointer_rtx, 8));
2370 else
2371 stack_slot = assign_stack_temp (DFmode, 8, 0);
2372 emit_move_insn (stack_slot, operands[1]);
2373 emit_move_insn (operands[0], stack_slot);
2374 DONE;
2375 }
2376
2377 if (CONSTANT_P (operands[1]))
2378 {
2379 operands[1] = force_const_mem (DFmode, operands[1]);
2380 if (! memory_address_p (DFmode, XEXP (operands[1], 0))
2381 && ! reload_in_progress)
2382 operands[1] = change_address (operands[1], DFmode,
2383 XEXP (operands[1], 0));
2384 }
2385}")
2386
2387(define_insn ""
2388 [(set (match_operand:DF 0 "gen_reg_operand" "=r,r")
2389 (match_operand:DF 1 "mem_or_easy_const_operand" "G,m"))]
2390 "REGNO (operands[0]) <= 31"
2391 "@
2392 #
2393 l %0,%1\;l %L0,%L1"
2394 [(set_attr "type" "*,load")])
2395
2396(define_split
2397 [(set (match_operand:DF 0 "gen_reg_operand" "")
2398 (match_operand:DF 1 "easy_fp_constant" ""))]
2399 "reload_completed && REGNO (operands[0]) <= 31"
2400 [(set (match_dup 2) (match_dup 3))
2401 (set (match_dup 4) (match_dup 5))]
2402 "
2403{ operands[2] = operand_subword (operands[0], 0, 0, DFmode);
2404 operands[3] = operand_subword (operands[1], 0, 0, DFmode);
2405 operands[4] = operand_subword (operands[0], 1, 0, DFmode);
2406 operands[5] = operand_subword (operands[1], 1, 0, DFmode); }")
2407
2408(define_insn ""
2409 [(set (match_operand:DF 0 "fp_reg_or_mem_operand" "=f,f,m")
2410 (match_operand:DF 1 "fp_reg_or_mem_operand" "f,m,f"))]
2411 "gen_reg_operand (operands[0], DFmode)
2412 || gen_reg_operand (operands[1], DFmode)"
2413 "@
2414 fmr %0,%1
2415 lfd%U1%X1 %0,%1
2416 stfd%U0%X0 %1,%0"
2417 [(set_attr "type" "fp,load,*")])
2418\f
2419;; Next come the multi-word integer load and store and the load and store
2420;; multiple insns.
2421(define_expand "movdi"
2422 [(set (match_operand:DI 0 "general_operand" "")
2423 (match_operand:DI 1 "general_operand" ""))]
2424 ""
2425 "
2426{
2427 if (GET_CODE (operands[0]) == MEM)
2428 operands[1] = force_reg (DImode, operands[1]);
2429
2430 else if (GET_CODE (operands[1]) == CONST_DOUBLE
2431 || GET_CODE (operands[1]) == CONST_INT)
2432 {
2433 emit_move_insn (operand_subword (operands[0], 0, 0, DImode),
2434 operand_subword (operands[1], 0, 0, DImode));
2435 emit_move_insn (operand_subword (operands[0], 1, 0, DImode),
2436 operand_subword (operands[1], 1, 0, DImode));
2437 DONE;
2438 }
2439}")
2440
2441(define_insn ""
2442 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m")
2443 (match_operand:DI 1 "input_operand" "r,m,r"))]
2444 "gen_reg_operand (operands[0], DImode)
2445 || gen_reg_operand (operands[1], DImode)"
2446 "*
2447{
2448 switch (which_alternative)
2449 {
2450 case 0:
2451 /* We normally copy the low-numbered register first. However, if
2452 the first register operand 0 is the same as the second register of
2453 operand 1, we must copy in the opposite order. */
2454 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
2455 return \"oril %L0,%L1,0\;oril %0,%1,0\";
2456 else
2457 return \"oril %0,%1,0\;oril %L0,%L1,0\";
2458 case 1:
2459 /* If the low-address word is used in the address, we must load it
2460 last. Otherwise, load it first. Note that we cannot have
2461 auto-increment in that case since the address register is known to be
2462 dead. */
2463 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
2464 operands [1], 0))
2465 return \"l %L0,%L1\;l %0,%1\";
2466 else
2467 return \"l%U1 %0,%1\;l %L0,%L1\";
2468 case 2:
2469 return \"st%U0 %1,%0\;st %L1,%L0\";
2470 }
2471}"
2472 [(set_attr "type" "*,load,*")])
2473\f
2474;; TImode is similar, except that we usually want to compute the address into
2475;; a register and use lsi/stsi (the exception is during reload). MQ is also
2476;; clobbered in stsi, so we need a SCRATCH for it.
2477(define_expand "movti"
2478 [(parallel [(set (match_operand:TI 0 "general_operand" "")
2479 (match_operand:TI 1 "general_operand" ""))
2480 (clobber (scratch:SI))])]
2481 ""
2482 "
2483{
2484 if (GET_CODE (operands[0]) == MEM)
2485 operands[1] = force_reg (TImode, operands[1]);
2486
2487 if (GET_CODE (operands[0]) == MEM
2488 && GET_CODE (XEXP (operands[0], 0)) != REG
2489 && ! reload_in_progress)
2490 operands[0] = change_address (operands[0], TImode,
2491 copy_addr_to_reg (XEXP (operands[0], 0)));
2492
2493 if (GET_CODE (operands[1]) == MEM
2494 && GET_CODE (XEXP (operands[1], 0)) != REG
2495 && ! reload_in_progress)
2496 operands[1] = change_address (operands[1], TImode,
2497 copy_addr_to_reg (XEXP (operands[1], 0)));
2498}")
2499
2500;; We say that MQ is clobbered in the last alternative because the first
2501;; alternative would never get used otherwise since it would need a reload
2502;; while the 2nd alternative would not. We put memory cases first so they
2503;; are preferred. Otherwise, we'd try to reload the output instead of
2504;; giving the SCRATCH mq.
2505(define_insn ""
2506 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,r,r,r")
2507 (match_operand:TI 1 "reg_or_mem_operand" "r,r,r,Q,m"))
2508 (clobber (match_scratch:SI 2 "=q,q#X,X,X,X"))]
2509 "gen_reg_operand (operands[0], TImode)
2510 || gen_reg_operand (operands[1], TImode)"
2511 "*
2512{
2513 switch (which_alternative)
2514 {
2515 case 0:
2516 return \"stsi %1,%P0,16\";
2517
2518 case 1:
2519 return \"st%U0 %1,%0\;st %L1,%L0\;st %Y1,%Y0\;st %Z1,%Z0\";
2520
2521 case 2:
2522 /* Normally copy registers with lowest numbered register copied first.
2523 But copy in the other order if the first register of the output
2524 is the second, third, or fourth register in the input. */
2525 if (REGNO (operands[0]) >= REGNO (operands[1]) + 1
2526 && REGNO (operands[0]) <= REGNO (operands[1]) + 3)
2527 return \"oril %Z0,%Z1,0\;oril %Y0,%Y1,0\;oril %L0,%L1,0\;oril %0,%1,0\";
2528 else
2529 return \"oril %0,%1,0\;oril %L0,%L1,0\;oril %Y0,%Y1,0\;oril %Z0,%Z1,0\";
2530 case 3:
2531 /* If the address is not used in the output, we can use lsi. Otherwise,
2532 fall through to generating four loads. */
2533 if (! reg_overlap_mentioned_p (operands[0], operands[1]))
2534 return \"lsi %0,%P1,16\";
2535 /* ... fall through ... */
2536 case 4:
2537 /* If the address register is the same as the register for the lowest-
2538 addressed word, load it last. Similarly for the next two words.
2539 Otherwise load lowest address to highest. */
2540 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
2541 operands[1], 0))
2542 return \"l %L0,%L1\;l %Y0,%Y1\;l %Z0,%Z1\;l %0,%1\";
2543 else if (refers_to_regno_p (REGNO (operands[0]) + 1,
2544 REGNO (operands[0]) + 2, operands[1], 0))
2545 return \"l %0,%1\;l %Y0,%Y1\;l %Z0,%Z1\;l %L0,%L1\";
2546 else if (refers_to_regno_p (REGNO (operands[0]) + 2,
2547 REGNO (operands[0]) + 3, operands[1], 0))
2548 return \"l %0,%1\;l %L0,%L1\;l %Z0,%Z1\;l %Y0,%Y1\";
2549 else
2550 return \"l%U1 %0,%1\;l %L0,%L1\;l %Y0,%Y1\;l %Z0,%Z1\";
2551 }
2552}"
2553 [(set_attr "type" "*,load,load,*,*")])
2554\f
2555(define_expand "load_multiple"
2556 [(match_parallel 3 "" [(set (match_operand:SI 0 "" "")
2557 (match_operand:SI 1 "" ""))
2558 (use (match_operand:SI 2 "" ""))])]
2559 ""
2560 "
2561{
2562 int regno;
2563 int count;
2564 rtx from;
2565 int i;
2566
2567 /* Support only loading a constant number of fixed-point registers from
2568 memory and only bother with this if more than two; the machine
2569 doesn't support more than eight. */
2570 if (GET_CODE (operands[2]) != CONST_INT
2571 || INTVAL (operands[2]) <= 2
2572 || INTVAL (operands[2]) > 8
2573 || GET_CODE (operands[1]) != MEM
2574 || GET_CODE (operands[0]) != REG
2575 || REGNO (operands[0]) >= 32)
2576 FAIL;
2577
2578 count = INTVAL (operands[2]);
2579 regno = REGNO (operands[0]);
2580
2581 operands[3] = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (count));
2582 from = force_reg (SImode, XEXP (operands[1], 0));
2583
2584 for (i = 0; i < count; i++)
2585 XVECEXP (operands[3], 0, i)
2586 = gen_rtx (SET, VOIDmode, gen_rtx (REG, SImode, regno + i),
2587 gen_rtx (MEM, SImode, plus_constant (from, i * 4)));
2588}")
2589
2590(define_insn ""
2591 [(match_parallel 0 "load_multiple_operation"
2592 [(set (match_operand:SI 1 "gen_reg_operand" "=r")
2593 (match_operand:SI 2 "indirect_operand" "Q"))])]
2594 ""
2595 "*
2596{
2597 /* We have to handle the case where the pseudo used to contain the address
2598 is assigned to one of the output registers. In that case, do the
2599 lsi, but then load the correct value. This is a bit of a mess, but is
2600 the best we can do. */
2601 static char result[100];
2602 char newload[40];
2603 int i;
2604
2605 strcpy (result, \"lsi %1,%P2,%N0\");
2606 for (i = 0; i < XVECLEN (operands[0], 0); i++)
2607 if (refers_to_regno_p (REGNO (operands[1]) + i,
2608 REGNO (operands[1]) + i + 1, operands[2], 0))
2609 {
2610 sprintf (newload, \"\;l %d,%d(%d)\",
2611 REGNO (operands[1]) + i,
2612 i * 4, REGNO (XEXP (operands[2], 0)));
2613 strcat (result, newload);
2614 }
2615
2616 return result;
2617}"
2618 [(set_attr "type" "load")])
2619\f
2620(define_expand "store_multiple"
2621 [(match_parallel 3 "" [(set (match_operand:SI 0 "" "")
2622 (match_operand:SI 1 "" ""))
2623 (clobber (scratch:SI))
2624 (use (match_operand:SI 2 "" ""))])]
2625 ""
2626 "
2627{
2628 int regno;
2629 int count;
2630 rtx to;
2631 int i;
2632
2633 /* Support only storing a constant number of fixed-point registers to
2634 memory and only bother with this if more than two; the machine
2635 doesn't support more than eight. */
2636 if (GET_CODE (operands[2]) != CONST_INT
2637 || INTVAL (operands[2]) <= 2
2638 || INTVAL (operands[2]) > 8
2639 || GET_CODE (operands[0]) != MEM
2640 || GET_CODE (operands[1]) != REG
2641 || REGNO (operands[1]) >= 32)
2642 FAIL;
2643
2644 count = INTVAL (operands[2]);
2645 regno = REGNO (operands[1]);
2646
2647 operands[3] = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (count + 1));
2648 to = force_reg (SImode, XEXP (operands[0], 0));
2649
2650 XVECEXP (operands[3], 0, 0)
2651 = gen_rtx (SET, VOIDmode, gen_rtx (MEM, SImode, to), operands[1]);
2652 XVECEXP (operands[3], 0, 1) = gen_rtx (CLOBBER, VOIDmode,
2653 gen_rtx (SCRATCH, SImode));
2654
2655 for (i = 1; i < count; i++)
2656 XVECEXP (operands[3], 0, i + 1)
2657 = gen_rtx (SET, VOIDmode,
2658 gen_rtx (MEM, SImode, plus_constant (to, i * 4)),
2659 gen_rtx (REG, SImode, regno + i));
2660}")
2661
2662(define_insn ""
2663 [(match_parallel 0 "store_multiple_operation"
2664 [(set (match_operand:SI 1 "indirect_operand" "=Q")
2665 (match_operand:SI 2 "gen_reg_operand" "r"))
2666 (clobber (match_scratch:SI 3 "=q"))])]
2667 ""
2668 "stsi %2,%P1,%O0")
2669\f
2670;; Define insns that do load or store with update. Some of these we can
2671;; get by using pre-decrement or pre-increment, but the hardware can also
2672;; do cases where the increment is not the size of the object.
2673;;
2674;; In all these cases, we use operands 0 and 1 for the register being
2675;; incremented because those are the operands that local-alloc will
2676;; tie and these are the pair most likely to be tieable (and the ones
2677;; that will benefit the most).
2678
2679(define_insn ""
2680 [(set (match_operand:SI 3 "gen_reg_operand" "=r,r")
2681 (mem:SI (plus:SI (match_operand:SI 1 "gen_reg_operand" "0,0")
2682 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
2683 (set (match_operand:SI 0 "gen_reg_operand" "=b,b")
2684 (plus:SI (match_dup 1) (match_dup 2)))]
2685 ""
2686 "@
2687 lux %3,%1,%2
2688 lu %3,%2(%1)"
2689 [(set_attr "type" "load,load")])
2690
2691(define_insn ""
2692 [(set (mem:SI (plus:SI (match_operand:SI 1 "gen_reg_operand" "0,0")
2693 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
2694 (match_operand:SI 3 "gen_reg_operand" "r,r"))
2695 (set (match_operand:SI 0 "gen_reg_operand" "=b,b")
2696 (plus:SI (match_dup 1) (match_dup 2)))]
2697 ""
2698 "@
2699 stux %3,%1,%2
2700 stu %3,%2(%1)")
2701
2702(define_insn ""
2703 [(set (match_operand:HI 3 "gen_reg_operand" "=r,r")
2704 (mem:HI (plus:SI (match_operand:SI 1 "gen_reg_operand" "0,0")
2705 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
2706 (set (match_operand:SI 0 "gen_reg_operand" "=b,b")
2707 (plus:SI (match_dup 1) (match_dup 2)))]
2708 ""
2709 "@
2710 lhzux %3,%1,%2
2711 lhzu %3,%2(%1)"
2712 [(set_attr "type" "load,load")])
2713
2714(define_insn ""
2715 [(set (match_operand:SI 3 "gen_reg_operand" "=r,r")
2716 (zero_extend:SI
2717 (mem:HI (plus:SI (match_operand:SI 1 "gen_reg_operand" "0,0")
2718 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
2719 (set (match_operand:SI 0 "gen_reg_operand" "=b,b")
2720 (plus:SI (match_dup 1) (match_dup 2)))]
2721 ""
2722 "@
2723 lhzux %3,%1,%2
2724 lhzu %3,%2(%1)"
2725 [(set_attr "type" "load,load")])
2726
2727(define_insn ""
2728 [(set (match_operand:SI 3 "gen_reg_operand" "=r,r")
2729 (sign_extend:SI
2730 (mem:HI (plus:SI (match_operand:SI 1 "gen_reg_operand" "0,0")
2731 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
2732 (set (match_operand:SI 0 "gen_reg_operand" "=b,b")
2733 (plus:SI (match_dup 1) (match_dup 2)))]
2734 ""
2735 "@
2736 lhaux %3,%1,%2
2737 lhau %3,%2(%1)"
2738 [(set_attr "type" "load,load")])
2739
2740(define_insn ""
2741 [(set (mem:HI (plus:SI (match_operand:SI 1 "gen_reg_operand" "0,0")
2742 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
2743 (match_operand:HI 3 "gen_reg_operand" "r,r"))
2744 (set (match_operand:SI 0 "gen_reg_operand" "=b,b")
2745 (plus:SI (match_dup 1) (match_dup 2)))]
2746 ""
2747 "@
2748 sthux %3,%1,%2
2749 sthu %3,%2(%1)"
2750 [(set_attr "type" "load,load")])
2751
2752(define_insn ""
2753 [(set (match_operand:QI 3 "gen_reg_operand" "=r,r")
2754 (mem:QI (plus:SI (match_operand:SI 1 "gen_reg_operand" "0,0")
2755 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
2756 (set (match_operand:SI 0 "gen_reg_operand" "=b,b")
2757 (plus:SI (match_dup 1) (match_dup 2)))]
2758 ""
2759 "@
2760 lbzux %3,%1,%2
2761 lbzu %3,%2(%1)"
2762 [(set_attr "type" "load,load")])
2763
2764(define_insn ""
2765 [(set (match_operand:SI 3 "gen_reg_operand" "=r,r")
2766 (zero_extend:SI
2767 (mem:QI (plus:SI (match_operand:SI 1 "gen_reg_operand" "0,0")
2768 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
2769 (set (match_operand:SI 0 "gen_reg_operand" "=b,b")
2770 (plus:SI (match_dup 1) (match_dup 2)))]
2771 ""
2772 "@
2773 lbzux %3,%1,%2
2774 lbzu %3,%2(%1)"
2775 [(set_attr "type" "load,load")])
2776
2777(define_insn ""
2778 [(set (mem:QI (plus:SI (match_operand:SI 1 "gen_reg_operand" "0,0")
2779 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
2780 (match_operand:QI 3 "gen_reg_operand" "r,r"))
2781 (set (match_operand:SI 0 "gen_reg_operand" "=b,b")
2782 (plus:SI (match_dup 1) (match_dup 2)))]
2783 ""
2784 "@
2785 stbux %3,%1,%2
2786 stbu %3,%2(%1)")
2787
2788(define_insn ""
2789 [(set (match_operand:SF 3 "gen_reg_operand" "=f,f")
2790 (mem:SI (plus:SI (match_operand:SI 1 "gen_reg_operand" "0,0")
2791 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
2792 (set (match_operand:SI 0 "gen_reg_operand" "=b,b")
2793 (plus:SI (match_dup 1) (match_dup 2)))]
2794 ""
2795 "@
2796 lfsux %3,%1,%2
2797 lfsu %3,%2(%1)"
2798 [(set_attr "type" "load,load")])
2799
2800(define_insn ""
2801 [(set (mem:SF (plus:SI (match_operand:SI 1 "gen_reg_operand" "0,0")
2802 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
2803 (match_operand:SF 3 "gen_reg_operand" "f,f"))
2804 (set (match_operand:SI 0 "gen_reg_operand" "=b,b")
2805 (plus:SI (match_dup 1) (match_dup 2)))]
2806 ""
2807 "@
2808 frsp %3,%3\;stfsux %3,%1,%2
2809 frsp %3,%3\;stfsu %3,%2(%1)")
2810
2811(define_insn ""
2812 [(set (match_operand:DF 3 "gen_reg_operand" "=f,f")
2813 (mem:DF (plus:SI (match_operand:SI 1 "gen_reg_operand" "0,0")
2814 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
2815 (set (match_operand:SI 0 "gen_reg_operand" "=b,b")
2816 (plus:SI (match_dup 1) (match_dup 2)))]
2817 ""
2818 "@
2819 lfdux %3,%1,%2
2820 lfdu %3,%2(%1)"
2821 [(set_attr "type" "load,load")])
2822
2823(define_insn ""
2824 [(set (mem:DF (plus:SI (match_operand:SI 1 "gen_reg_operand" "0,0")
2825 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
2826 (match_operand:DF 3 "gen_reg_operand" "f,f"))
2827 (set (match_operand:SI 0 "gen_reg_operand" "=b,b")
2828 (plus:SI (match_dup 1) (match_dup 2)))]
2829 ""
2830 "@
2831 stfdux %3,%1,%2
2832 stfdu %3,%2(%1)")
2833\f
2834;; Next come insns related to the calling sequence.
2835;;
2836;; First, an insn to allocate new stack space for dynamic use (e.g., alloca).
96d3e8f1 2837;; We move the back-chain and decrement the stack pointer. This is slightly
1fd4e8c1
RK		 2838;; less efficient than it needs to be for long constants, but that case
2839;; should be rare.
2840
2841(define_expand "allocate_stack"
2842 [(set (reg:SI 1)
2843 (minus:SI (reg:SI 1) (match_operand:SI 0 "reg_or_cint_operand" "")))]
2844 ""
2845 "
2846{ rtx chain = gen_reg_rtx (SImode);
2847 rtx stack_bot = gen_rtx (MEM, Pmode, stack_pointer_rtx);
2848
2849 emit_move_insn (chain, stack_bot);
2850 emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, operands[0]));
2851 emit_move_insn (stack_bot, chain);
2852 DONE;
2853}")
2854\f
2855;; A function pointer is a pointer to a data area whose first word contains
2856;; the actual address of the function, whose second word contains a pointer
2857;; to its TOC, and whose third word contains a value to place in the static
2858;; chain register (r11). Note that if we load the static chain, our
2859;; "trampoline" need not have any executable code.
2860;;
2861;; operands[0] is an SImode pseudo in which we place the address of the
2862;; function.
2863;; operands[1] is the address of data area of the function to call
2864
2865(define_expand "call_via_ptr"
2866 [(set (match_operand:SI 0 "gen_reg_operand" "")
2867 (mem:SI (match_operand:SI 1 "gen_reg_operand" "")))
2868 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
2869 (reg:SI 2))
2870 (set (reg:SI 2)
2871 (mem:SI (plus:SI (match_dup 1)
2872 (const_int 4))))
2873 (set (reg:SI 11)
2874 (mem:SI (plus:SI (match_dup 1)
2875 (const_int 8))))
2876 (use (reg:SI 2))
2877 (use (reg:SI 11))]
2878 ""
2879 "")
2880
2881(define_expand "call"
2882 [(parallel [(call (mem:SI (match_operand:SI 0 "address_operand" ""))
2883 (match_operand 1 "" ""))
2884 (clobber (scratch:SI))])]
2885 ""
2886 "
2887{
2888 if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != CONST_INT)
2889 abort ();
2890
2891 operands[0] = XEXP (operands[0], 0);
2892 if (GET_CODE (operands[0]) != SYMBOL_REF)
2893 {
2894 rtx temp = gen_reg_rtx (SImode);
2895
2896 emit_insn (gen_call_via_ptr (temp, force_reg (SImode, operands[0])));
2897 operands[0] = temp;
2898 }
2899}")
2900
2901(define_expand "call_value"
2902 [(parallel [(set (match_operand 0 "" "")
2903 (call (mem:SI (match_operand:SI 1 "address_operand" ""))
2904 (match_operand 2 "" "")))
2905 (clobber (scratch:SI))])]
2906 ""
2907 "
2908{
2909 if (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != CONST_INT)
2910 abort ();
2911
2912 operands[1] = XEXP (operands[1], 0);
2913 if (GET_CODE (operands[1]) != SYMBOL_REF)
2914 {
2915 rtx temp = gen_reg_rtx (SImode);
2916
2917 emit_insn (gen_call_via_ptr (temp, force_reg (SImode, operands[1])));
2918 operands[1] = temp;
2919 }
2920}")
2921
2922(define_insn ""
2923 [(call (mem:SI (match_operand:SI 0 "call_operand" "l,s"))
2924 (match_operand 1 "" "fg,fg"))
9482d6de 2925 (clobber (match_scratch:SI 2 "=l,l"))]
1fd4e8c1
RK		 2926 ""
2927 "@
2928 brl\;l 2,20(1)
2929 bl %z0\;cror 15,15,15")
2930
2931(define_insn ""
2932 [(set (match_operand 0 "" "fg,fg")
2933 (call (mem:SI (match_operand:SI 1 "call_operand" "l,s"))
2934 (match_operand 2 "" "fg,fg")))
2935 (clobber (match_scratch:SI 3 "=l,l"))]
2936 ""
2937 "@
2938 brl\;l 2,20(1)
2939 bl %z1\;cror 15,15,15")
2940\f
2941;; Compare insns are next. Note that the RS/6000 has two types of compares,
2942;; signed & unsigned, and one type of branch.
2943;;
2944;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc
2945;; insns, and branches. We store the operands of compares until we see
2946;; how it is used.
2947(define_expand "cmpsi"
2948 [(set (cc0)
2949 (compare (match_operand:SI 0 "gen_reg_operand" "")
2950 (match_operand:SI 1 "reg_or_short_operand" "")))]
2951 ""
2952 "
2953{
2954 /* Take care of the possibility that operands[1] might be negative but
2955 this might be a logical operation. That insn doesn't exist. */
2956 if (GET_CODE (operands[1]) == CONST_INT
2957 && INTVAL (operands[1]) < 0)
2958 operands[1] = force_reg (SImode, operands[1]);
2959
2960 rs6000_compare_op0 = operands[0];
2961 rs6000_compare_op1 = operands[1];
2962 rs6000_compare_fp_p = 0;
2963 DONE;
2964}")
2965
2966(define_expand "cmpsf"
2967 [(set (cc0) (compare (match_operand:SF 0 "gen_reg_operand" "")
2968 (match_operand:SF 1 "gen_reg_operand" "")))]
2969 ""
2970 "
2971{
2972 rs6000_compare_op0 = operands[0];
2973 rs6000_compare_op1 = operands[1];
2974 rs6000_compare_fp_p = 1;
2975 DONE;
2976}")
2977
2978(define_expand "cmpdf"
2979 [(set (cc0) (compare (match_operand:DF 0 "gen_reg_operand" "")
2980 (match_operand:DF 1 "gen_reg_operand" "")))]
2981 ""
2982 "
2983{
2984 rs6000_compare_op0 = operands[0];
2985 rs6000_compare_op1 = operands[1];
2986 rs6000_compare_fp_p = 1;
2987 DONE;
2988}")
2989
2990(define_expand "beq"
2991 [(set (match_dup 2) (match_dup 1))
2992 (set (pc)
2993 (if_then_else (eq (match_dup 2)
2994 (const_int 0))
2995 (label_ref (match_operand 0 "" ""))
2996 (pc)))]
2997 ""
2998 "
2999{ enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
3000 operands[1] = gen_rtx (COMPARE, mode,
3001 rs6000_compare_op0, rs6000_compare_op1);
3002 operands[2] = gen_reg_rtx (mode);
3003}")
3004
3005(define_expand "bne"
3006 [(set (match_dup 2) (match_dup 1))
3007 (set (pc)
3008 (if_then_else (ne (match_dup 2)
3009 (const_int 0))
3010 (label_ref (match_operand 0 "" ""))
3011 (pc)))]
3012 ""
3013 "
3014{ enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
3015 operands[1] = gen_rtx (COMPARE, mode,
3016 rs6000_compare_op0, rs6000_compare_op1);
3017 operands[2] = gen_reg_rtx (mode);
3018}")
3019
3020(define_expand "blt"
3021 [(set (match_dup 2) (match_dup 1))
3022 (set (pc)
3023 (if_then_else (lt (match_dup 2)
3024 (const_int 0))
3025 (label_ref (match_operand 0 "" ""))
3026 (pc)))]
3027 ""
3028 "
3029{ enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
3030 operands[1] = gen_rtx (COMPARE, mode,
3031 rs6000_compare_op0, rs6000_compare_op1);
3032 operands[2] = gen_reg_rtx (mode);
3033}")
3034
3035(define_expand "bgt"
3036 [(set (match_dup 2) (match_dup 1))
3037 (set (pc)
3038 (if_then_else (gt (match_dup 2)
3039 (const_int 0))
3040 (label_ref (match_operand 0 "" ""))
3041 (pc)))]
3042 ""
3043 "
3044{ enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
3045 operands[1] = gen_rtx (COMPARE, mode,
3046 rs6000_compare_op0, rs6000_compare_op1);
3047 operands[2] = gen_reg_rtx (mode);
3048}")
3049
3050(define_expand "ble"
3051 [(set (match_dup 2) (match_dup 1))
3052 (set (pc)
3053 (if_then_else (le (match_dup 2)
3054 (const_int 0))
3055 (label_ref (match_operand 0 "" ""))
3056 (pc)))]
3057 ""
3058 "
3059{ enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
3060 operands[1] = gen_rtx (COMPARE, mode,
3061 rs6000_compare_op0, rs6000_compare_op1);
3062 operands[2] = gen_reg_rtx (mode);
3063}")
3064
3065(define_expand "bge"
3066 [(set (match_dup 2) (match_dup 1))
3067 (set (pc)
3068 (if_then_else (ge (match_dup 2)
3069 (const_int 0))
3070 (label_ref (match_operand 0 "" ""))
3071 (pc)))]
3072 ""
3073 "
3074{ enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
3075 operands[1] = gen_rtx (COMPARE, mode,
3076 rs6000_compare_op0, rs6000_compare_op1);
3077 operands[2] = gen_reg_rtx (mode);
3078}")
3079
3080(define_expand "bgtu"
3081 [(set (match_dup 2) (match_dup 1))
3082 (set (pc)
3083 (if_then_else (gtu (match_dup 2)
3084 (const_int 0))
3085 (label_ref (match_operand 0 "" ""))
3086 (pc)))]
3087 ""
3088 "
3089{ operands[1] = gen_rtx (COMPARE, CCUNSmode,
3090 rs6000_compare_op0, rs6000_compare_op1);
3091 operands[2] = gen_reg_rtx (CCUNSmode);
3092}")
3093
3094(define_expand "bltu"
3095 [(set (match_dup 2) (match_dup 1))
3096 (set (pc)
3097 (if_then_else (ltu (match_dup 2)
3098 (const_int 0))
3099 (label_ref (match_operand 0 "" ""))
3100 (pc)))]
3101 ""
3102 "
3103{ operands[1] = gen_rtx (COMPARE, CCUNSmode,
3104 rs6000_compare_op0, rs6000_compare_op1);
3105 operands[2] = gen_reg_rtx (CCUNSmode);
3106}")
3107
3108(define_expand "bgeu"
3109 [(set (match_dup 2) (match_dup 1))
3110 (set (pc)
3111 (if_then_else (geu (match_dup 2)
3112 (const_int 0))
3113 (label_ref (match_operand 0 "" ""))
3114 (pc)))]
3115 ""
3116 "
3117{ operands[1] = gen_rtx (COMPARE, CCUNSmode,
3118 rs6000_compare_op0, rs6000_compare_op1);
3119 operands[2] = gen_reg_rtx (CCUNSmode);
3120}")
3121
3122(define_expand "bleu"
3123 [(set (match_dup 2) (match_dup 1))
3124 (set (pc)
3125 (if_then_else (leu (match_dup 2)
3126 (const_int 0))
3127 (label_ref (match_operand 0 "" ""))
3128 (pc)))]
3129 ""
3130 "
3131{ operands[1] = gen_rtx (COMPARE, CCUNSmode,
3132 rs6000_compare_op0, rs6000_compare_op1);
3133 operands[2] = gen_reg_rtx (CCUNSmode);
3134}")
3135
3136;; For SNE, we would prefer that the xor/abs sequence be used for integers.
3137;; For SEQ, likewise, except that comparisons with zero should be done
3138;; with an scc insns. However, due to the order that combine see the
3139;; resulting insns, we must, in fact, allow SEQ for integers. Fail in
3140;; the cases we don't want to handle.
3141(define_expand "seq"
3142 [(set (match_dup 2) (match_dup 1))
3143 (set (match_operand:SI 0 "gen_reg_operand" "")
3144 (eq:SI (match_dup 2) (const_int 0)))]
3145 ""
3146 "
3147{ enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
3148 operands[1] = gen_rtx (COMPARE, mode,
3149 rs6000_compare_op0, rs6000_compare_op1);
3150 operands[2] = gen_reg_rtx (mode);
3151}")
3152
3153(define_expand "sne"
3154 [(set (match_dup 2) (match_dup 1))
3155 (set (match_operand:SI 0 "gen_reg_operand" "")
3156 (ne:SI (match_dup 2) (const_int 0)))]
3157 ""
3158 "
3159{ if (! rs6000_compare_fp_p)
3160 FAIL;
3161
3162 operands[1] = gen_rtx (COMPARE, CCFPmode,
3163 rs6000_compare_op0, rs6000_compare_op1);
3164 operands[2] = gen_reg_rtx (CCFPmode);
3165}")
3166
3167;; A > 0 is best done using the portable sequence, so fail in that case.
3168(define_expand "sgt"
3169 [(set (match_dup 2) (match_dup 1))
3170 (set (match_operand:SI 0 "gen_reg_operand" "")
3171 (gt:SI (match_dup 2) (const_int 0)))]
3172 ""
3173 "
3174{ enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
3175
3176 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
3177 FAIL;
3178
3179 operands[1] = gen_rtx (COMPARE, mode,
3180 rs6000_compare_op0, rs6000_compare_op1);
3181 operands[2] = gen_reg_rtx (mode);
3182}")
3183
3184;; A < 0 is best done in the portable way for A an integer.
3185(define_expand "slt"
3186 [(set (match_dup 2) (match_dup 1))
3187 (set (match_operand:SI 0 "gen_reg_operand" "")
3188 (lt:SI (match_dup 2) (const_int 0)))]
3189 ""
3190 "
3191{ enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
3192
3193 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
3194 FAIL;
3195
3196 operands[1] = gen_rtx (COMPARE, mode,
3197 rs6000_compare_op0, rs6000_compare_op1);
3198 operands[2] = gen_reg_rtx (mode);
3199}")
3200
3201(define_expand "sge"
3202 [(set (match_dup 2) (match_dup 1))
3203 (set (match_operand:SI 0 "gen_reg_operand" "")
3204 (ge:SI (match_dup 2) (const_int 0)))]
3205 ""
3206 "
3207{ enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
3208 operands[1] = gen_rtx (COMPARE, mode,
3209 rs6000_compare_op0, rs6000_compare_op1);
3210 operands[2] = gen_reg_rtx (mode);
3211}")
3212
3213;; A <= 0 is best done the portable way for A an integer.
3214(define_expand "sle"
3215 [(set (match_dup 2) (match_dup 1))
3216 (set (match_operand:SI 0 "gen_reg_operand" "")
3217 (le:SI (match_dup 2) (const_int 0)))]
3218 ""
3219 "
3220{ enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
3221
3222 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
3223 FAIL;
3224
3225 operands[1] = gen_rtx (COMPARE, mode,
3226 rs6000_compare_op0, rs6000_compare_op1);
3227 operands[2] = gen_reg_rtx (mode);
3228}")
3229
3230(define_expand "sgtu"
3231 [(set (match_dup 2) (match_dup 1))
3232 (set (match_operand:SI 0 "gen_reg_operand" "")
3233 (gtu:SI (match_dup 2) (const_int 0)))]
3234 ""
3235 "
3236{ operands[1] = gen_rtx (COMPARE, CCUNSmode,
3237 rs6000_compare_op0, rs6000_compare_op1);
3238 operands[2] = gen_reg_rtx (CCUNSmode);
3239}")
3240
3241(define_expand "sltu"
3242 [(set (match_dup 2) (match_dup 1))
3243 (set (match_operand:SI 0 "gen_reg_operand" "")
3244 (ltu:SI (match_dup 2) (const_int 0)))]
3245 ""
3246 "
3247{ operands[1] = gen_rtx (COMPARE, CCUNSmode,
3248 rs6000_compare_op0, rs6000_compare_op1);
3249 operands[2] = gen_reg_rtx (CCUNSmode);
3250}")
3251
3252(define_expand "sgeu"
3253 [(set (match_dup 2) (match_dup 1))
3254 (set (match_operand:SI 0 "gen_reg_operand" "")
3255 (geu:SI (match_dup 2) (const_int 0)))]
3256 ""
3257 "
3258{ operands[1] = gen_rtx (COMPARE, CCUNSmode,
3259 rs6000_compare_op0, rs6000_compare_op1);
3260 operands[2] = gen_reg_rtx (CCUNSmode);
3261}")
3262
3263(define_expand "sleu"
3264 [(set (match_dup 2) (match_dup 1))
3265 (set (match_operand:SI 0 "gen_reg_operand" "")
3266 (leu:SI (match_dup 2) (const_int 0)))]
3267 ""
3268 "
3269{ operands[1] = gen_rtx (COMPARE, CCUNSmode,
3270 rs6000_compare_op0, rs6000_compare_op1);
3271 operands[2] = gen_reg_rtx (CCUNSmode);
3272}")
3273\f
3274;; Here are the actual compare insns.
3275(define_insn ""
3276 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
3277 (compare:CC (match_operand:SI 1 "gen_reg_operand" "r")
3278 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
3279 ""
3280 "cmp%I2 %0,%1,%2"
3281 [(set_attr "type" "compare")])
3282
f357808b
RK		 3283;; If we are comparing a register for equality with a large constant,
3284;; we can do this with an XOR followed by a compare. But we need a scratch
3285;; register for the result of the XOR.
3286
3287(define_split
3288 [(set (match_operand:CC 0 "cc_reg_operand" "")
3289 (compare:CC (match_operand:SI 1 "gen_reg_operand" "")
3290 (match_operand:SI 2 "non_short_cint_operand" "")))
3291 (clobber (match_operand:SI 3 "gen_reg_operand" ""))]
3292 "find_single_use (operands[0], insn, 0)
3293 && (GET_CODE (*find_single_use (operands[0], insn, 0)) == EQ
3294 || GET_CODE (*find_single_use (operands[0], insn, 0)) == NE)"
3295 [(set (match_dup 3) (xor:SI (match_dup 1) (match_dup 4)))
3296 (set (match_dup 0) (compare:CC (match_dup 3) (match_dup 5)))]
3297 "
3298{
3299 /* Get the constant we are comparing against, C, and see what it looks like
3300 sign-extended to 16 bits. Then see what constant could be XOR'ed
3301 with C to get the sign-extended value. */
3302
3303 int c = INTVAL (operands[2]);
3304 int sextc = (c << 16) >> 16;
3305 int xorv = c ^ sextc;
3306
3307 operands[4] = gen_rtx (CONST_INT, VOIDmode, xorv);
3308 operands[5] = gen_rtx (CONST_INT, VOIDmode, sextc);
3309}")
3310
1fd4e8c1
RK		 3311(define_insn ""
3312 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
3313 (compare:CCUNS (match_operand:SI 1 "gen_reg_operand" "r")
3314 (match_operand:SI 2 "reg_or_u_short_operand" "rI")))]
3315 ""
3316 "cmpl%I2 %0,%1,%W2"
3317 [(set_attr "type" "compare")])
3318
3319;; The following two insns don't exist as single insns, but if we provide
3320;; them, we can swap an add and compare, which will enable us to overlap more
3321;; of the required delay between a compare and branch. We generate code for
3322;; them by splitting.
3323
3324(define_insn ""
3325 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
3326 (compare:CC (match_operand:SI 1 "gen_reg_operand" "r")
3327 (match_operand:SI 2 "short_cint_operand" "i")))
3328 (set (match_operand:SI 0 "gen_reg_operand" "=r")
3329 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
3330 ""
3331 "#")
3332
3333(define_insn ""
3334 [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y")
3335 (compare:CCUNS (match_operand:SI 1 "gen_reg_operand" "r")
3336 (match_operand:SI 2 "u_short_cint_operand" "i")))
3337 (set (match_operand:SI 0 "gen_reg_operand" "=r")
3338 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
3339 ""
3340 "#")
3341
3342(define_split
3343 [(set (match_operand:CC 3 "cc_reg_operand" "")
3344 (compare:CC (match_operand:SI 1 "gen_reg_operand" "")
3345 (match_operand:SI 2 "short_cint_operand" "")))
3346 (set (match_operand:SI 0 "gen_reg_operand" "")
3347 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
3348 ""
3349 [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2)))
3350 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
3351
3352(define_split
3353 [(set (match_operand:CCUNS 3 "cc_reg_operand" "")
3354 (compare:CCUNS (match_operand:SI 1 "gen_reg_operand" "")
3355 (match_operand:SI 2 "u_short_cint_operand" "")))
3356 (set (match_operand:SI 0 "gen_reg_operand" "")
3357 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
3358 ""
3359 [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2)))
3360 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
3361
3362(define_insn ""
3363 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
3364 (compare:CCFP (match_operand:SF 1 "gen_reg_operand" "f")
3365 (match_operand:SF 2 "gen_reg_operand" "f")))]
3366 ""
3367 "fcmpu %0,%1,%2"
3368 [(set_attr "type" "fpcompare")])
3369
3370(define_insn ""
3371 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
3372 (compare:CCFP (match_operand:DF 1 "gen_reg_operand" "f")
3373 (match_operand:DF 2 "gen_reg_operand" "f")))]
3374 ""
3375 "fcmpu %0,%1,%2"
3376 [(set_attr "type" "fpcompare")])
3377\f
3378;; Now we have the scc insns. We can do some combinations because of the
3379;; way the machine works.
3380;;
3381;; Note that this is probably faster if we can put an insn between the
c5defebb
RK		 3382;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most
3383;; cases the insns below which don't use an intermediate CR field will
3384;; be used instead.
1fd4e8c1
RK		 3385(define_insn ""
3386 [(set (match_operand:SI 0 "gen_reg_operand" "=r")
3387 (match_operator:SI 1 "scc_comparison_operator"
3388 [(match_operand 2 "cc_reg_operand" "y")
3389 (const_int 0)]))]
3390 ""
3391 "%D1mfcr %0\;rlinm %0,%0,%J1,31,31")
3392
3393(define_insn ""
3394 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
3395 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
3396 [(match_operand 2 "cc_reg_operand" "y")
3397 (const_int 0)])
3398 (const_int 0)))
3399 (set (match_operand:SI 3 "gen_reg_operand" "=r")
3400 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
3401 ""
3402 "%D1mfcr %3\;rlinm. %3,%3,%J1,30,31"
3403 [(set_attr "type" "delayed_compare")])
3404
3405(define_insn ""
3406 [(set (match_operand:SI 0 "gen_reg_operand" "=r")
3407 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
3408 [(match_operand 2 "cc_reg_operand" "y")
3409 (const_int 0)])
3410 (match_operand:SI 3 "const_int_operand" "n")))]
3411 ""
3412 "*
3413{
3414 int is_bit = ccr_bit (operands[1], 1);
3415 int put_bit = 31 - (INTVAL (operands[3]) & 31);
3416 int count;
3417
3418 if (is_bit >= put_bit)
3419 count = is_bit - put_bit;
3420 else
3421 count = 32 - (put_bit - is_bit);
3422
3423 operands[4] = gen_rtx (CONST_INT, VOIDmode, count);
3424 operands[5] = gen_rtx (CONST_INT, VOIDmode, put_bit);
3425
3426 return \"%D1mfcr %0\;rlinm %0,%0,%4,%5,%5\";
3427}")
3428
3429(define_insn ""
3430 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
3431 (compare:CC
3432 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
3433 [(match_operand 2 "cc_reg_operand" "y")
3434 (const_int 0)])
3435 (match_operand:SI 3 "const_int_operand" "n"))
3436 (const_int 0)))
3437 (set (match_operand:SI 4 "gen_reg_operand" "=r")
3438 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
3439 (match_dup 3)))]
3440 ""
3441 "*
3442{
3443 int is_bit = ccr_bit (operands[1], 1);
3444 int put_bit = 31 - (INTVAL (operands[3]) & 31);
3445 int count;
3446
3447 if (is_bit >= put_bit)
3448 count = is_bit - put_bit;
3449 else
3450 count = 32 - (put_bit - is_bit);
3451
3452 operands[5] = gen_rtx (CONST_INT, VOIDmode, count);
3453 operands[6] = gen_rtx (CONST_INT, VOIDmode, put_bit);
3454
3455 return \"%D1mfcr %4\;rlinm. %4,%4,%5,%6,%6\";
3456}"
3457 [(set_attr "type" "delayed_compare")])
3458
c5defebb
RK		 3459;; If we are comparing the result of two comparisons, this can be done
3460;; using creqv or crxor.
3461
3462(define_insn ""
3463 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
3464 (compare:CCEQ (match_operator 1 "scc_comparison_operator"
3465 [(match_operand 2 "cc_reg_operand" "y")
3466 (const_int 0)])
3467 (match_operator 3 "scc_comparison_operator"
3468 [(match_operand 4 "cc_reg_operand" "y")
3469 (const_int 0)])))]
3470 "REGNO (operands[2]) != REGNO (operands[4])"
3471 "*
3472{
3473 enum rtx_code code1, code2;
3474
3475 code1 = GET_CODE (operands[1]);
3476 code2 = GET_CODE (operands[3]);
3477
3478 if ((code1 == EQ || code1 == LT || code1 == GT
3479 || code1 == LTU || code1 == GTU
3480 || (code1 != NE && GET_MODE (operands[2]) == CCFPmode))
3481 !=
3482 (code2 == EQ || code2 == LT || code2 == GT
3483 || code2 == LTU || code2 == GTU
3484 || (code2 != NE && GET_MODE (operands[4]) == CCFPmode)))
3485 return \"%C1%C3crxor %E0,%j1,%j3\";
3486 else
3487 return \"%C1%C3creqv %E0,%j1,%j3\";
3488}")
3489
3490;; There is a 3 cycle delay between consecutive mfcr instructions
3491;; so it is useful to combine 2 scc instructions to use only one mfcr.
3492
3493(define_peephole
3494 [(set (match_operand:SI 0 "gen_reg_operand" "=r")
3495 (match_operator:SI 1 "scc_comparison_operator"
3496 [(match_operand 2 "cc_reg_operand" "y")
3497 (const_int 0)]))
3498 (set (match_operand:SI 3 "gen_reg_operand" "=r")
3499 (match_operator:SI 4 "scc_comparison_operator"
3500 [(match_operand 5 "cc_reg_operand" "y")
3501 (const_int 0)]))]
3502 "REGNO (operands[2]) != REGNO (operands[5])"
3503 "%D1%D4mfcr %3\;rlinm %0,%3,%J1,31,31\;rlinm %3,%3,%J4,31,31")
3504
1fd4e8c1
RK		 3505;; There are some scc insns that can be done directly, without a compare.
3506;; These are faster because they don't involve the communications between
3507;; the FXU and branch units. In fact, we will be replacing all of the
3508;; integer scc insns here or in the portable methods in emit_store_flag.
3509;;
3510;; Also support (neg (scc ..)) since that construct is used to replace
3511;; branches, (plus (scc ..) ..) since that construct is common and
3512;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the
3513;; cases where it is no more expensive than (neg (scc ..)).
3514
3515;; Have reload force a constant into a register for the simple insns that
3516;; otherwise won't accept constants. We do this because it is faster than
3517;; the cmp/mfcr sequence we would otherwise generate.
3518
3519(define_insn ""
3520 [(set (match_operand:SI 0 "gen_reg_operand" "=r,r,r,r,r")
3521 (eq:SI (match_operand:SI 1 "gen_reg_operand" "%r,r,r,r,r")
3522 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I")))
3523 (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))]
3524 ""
3525 "@
3526 xor %0,%1,%2\;sfi %3,%0,0\;ae %0,%3,%0
3527 sfi %3,%1,0\;ae %0,%3,%1
3528 xoril %0,%1,%b2\;sfi %3,%0,0\;ae %0,%3,%0
3529 xoriu %0,%1,%u2\;sfi %3,%0,0\;ae %0,%3,%0
3530 sfi %0,%1,%2\;sfi %3,%0,0\;ae %0,%3,%0")
3531
3532(define_insn ""
3533 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x")
3534 (compare:CC
3535 (eq:SI (match_operand:SI 1 "gen_reg_operand" "%r,r,r,r,r")
3536 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I"))
3537 (const_int 0)))
3538 (set (match_operand:SI 0 "gen_reg_operand" "=r,r,r,r,r")
3539 (eq:SI (match_dup 1) (match_dup 2)))
3540 (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))]
3541 ""
3542 "@
3543 xor %0,%1,%2\;sfi %3,%0,0\;ae. %0,%3,%0
3544 sfi %3,%1,0\;ae. %0,%3,%1
3545 xoril %0,%1,%b2\;sfi %3,%0,0\;ae. %0,%3,%0
3546 xoriu %0,%1,%u2\;sfi %3,%0,0\;ae. %0,%3,%0
3547 sfi %0,%1,%2\;sfi %3,%0,0\;ae. %0,%3,%0"
3548 [(set_attr "type" "compare")])
3549
3550(define_insn ""
3551 [(set (match_operand:SI 0 "gen_reg_operand" "=r,r,r,r,r")
3552 (plus:SI (eq:SI (match_operand:SI 1 "gen_reg_operand" "%r,r,r,r,r")
3553 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I"))
3554 (match_operand:SI 3 "gen_reg_operand" "r,r,r,r,r")))
3555 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r"))]
3556 ""
3557 "@
3558 xor %4,%1,%2\;sfi %4,%4,0\;aze %0,%3
3559 sfi %4,%1,0\;aze %0,%3
3560 xoril %4,%1,%b2\;sfi %4,%4,0\;aze %0,%3
3561 xoriu %4,%1,%u2\;sfi %4,%4,0\;aze %0,%3
3562 sfi %4,%1,%2\;sfi %4,%4,0\;aze %0,%3")
3563
3564(define_insn ""
3565 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x")
3566 (compare:CC
3567 (plus:SI
3568 (eq:SI (match_operand:SI 1 "gen_reg_operand" "%r,r,r,r,r")
3569 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I"))
3570 (match_operand:SI 3 "gen_reg_operand" "r,r,r,r,r"))
3571 (const_int 0)))
3572 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r"))]
3573 ""
3574 "@
3575 xor %4,%1,%2\;sfi %4,%4,0\;aze. %4,%3
3576 sfi %4,%1,0\;aze. %0,%3
3577 xoril %4,%1,%b2\;sfi %4,%4,0\;aze. %4,%3
3578 xoriu %4,%1,%u2\;sfi %4,%4,0\;aze. %4,%3
3579 sfi %4,%1,%2\;sfi %4,%4,0\;aze. %4,%3"
3580 [(set_attr "type" "compare")])
3581
3582(define_insn ""
3583 [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,x,x,x")
3584 (compare:CC
3585 (plus:SI
3586 (eq:SI (match_operand:SI 1 "gen_reg_operand" "%r,r,r,r,r")
3587 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I"))
3588 (match_operand:SI 3 "gen_reg_operand" "r,r,r,r,r"))
3589 (const_int 0)))
3590 (set (match_operand:SI 0 "gen_reg_operand" "=r,r,r,r,r")
3591 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
3592 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r"))]
3593 ""
3594 "@
3595 xor %4,%1,%2\;sfi %4,%4,0\;aze. %0,%3
3596 sfi %4,%1,0\;aze. %4,%3
3597 xoril %4,%1,%b2\;sfi %4,%4,0\;aze. %0,%3
3598 xoriu %4,%1,%u2\;sfi %4,%4,0\;aze. %0,%3
3599 sfi %4,%1,%2\;sfi %4,%4,0\;aze. %0,%3"
3600 [(set_attr "type" "compare")])
3601
3602(define_insn ""
3603 [(set (match_operand:SI 0 "gen_reg_operand" "=r,r,r,r,r")
3604 (neg:SI (eq:SI (match_operand:SI 1 "gen_reg_operand" "r,r,r,r,r")
3605 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I"))))]
3606 ""
3607 "@
3608 xor %0,%1,%2\;ai %0,%0,-1\;sfe %0,%0,%0
3609 ai %0,%1,-1\;sfe %0,%0,%0
3610 xoril %0,%1,%b2\;ai %0,%0,-1\;sfe %0,%0,%0
3611 xoriu %0,%1,%u2\;ai %0,%0,-1\;sfe %0,%0,%0
3612 sfi %0,%1,%2\;ai %0,%0,-1\;sfe %0,%0,%0")
3613
3614;; This is what (plus (ne X (const_int 0)) Y) looks like.
3615(define_insn ""
3616 [(set (match_operand:SI 0 "gen_reg_operand" "=r")
3617 (plus:SI (lshiftrt:SI
3618 (neg:SI (abs:SI (match_operand:SI 1 "gen_reg_operand" "r")))
3619 (const_int 31))
3620 (match_operand:SI 2 "gen_reg_operand" "r")))
3621 (clobber (match_scratch:SI 3 "=&r"))]
3622 ""
3623 "ai %3,%1,-1\;aze %0,%2")
3624
3625(define_insn ""
3626 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
3627 (compare:CC
3628 (plus:SI (lshiftrt:SI
3629 (neg:SI (abs:SI (match_operand:SI 1 "gen_reg_operand" "r")))
3630 (const_int 31))
3631 (match_operand:SI 2 "gen_reg_operand" "r"))
3632 (const_int 0)))
3633 (clobber (match_scratch:SI 3 "=&r"))]
3634 ""
3635 "ai %3,%1,-1\;aze. %3,%2"
3636 [(set_attr "type" "compare")])
3637
3638(define_insn ""
3639 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
3640 (compare:CC
3641 (plus:SI (lshiftrt:SI
3642 (neg:SI (abs:SI (match_operand:SI 1 "gen_reg_operand" "r")))
3643 (const_int 31))
3644 (match_operand:SI 2 "gen_reg_operand" "r"))
3645 (const_int 0)))
3646 (set (match_operand:SI 0 "gen_reg_operand" "=r")
3647 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
3648 (match_dup 2)))
3649 (clobber (match_scratch:SI 3 "=&r"))]
3650 ""
3651 "ai %3,%1,-1\;aze. %0,%2"
3652 [(set_attr "type" "compare")])
3653
3654(define_insn ""
3655 [(set (match_operand:SI 0 "gen_reg_operand" "=r,r")
3656 (le:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
3657 (match_operand:SI 2 "reg_or_short_operand" "r,O")))
3658 (clobber (match_scratch:SI 3 "=r,X"))]
3659 ""
3660 "@
3661 doz %3,%2,%1\;sfi %0,%3,0\;ae %0,%0,%3
3662 ai %0,%1,-1\;aze %0,%0\;sri %0,%0,31")
3663
3664(define_insn ""
3665 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x")
3666 (compare:CC
3667 (le:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
3668 (match_operand:SI 2 "reg_or_short_operand" "r,O"))
3669 (const_int 0)))
3670 (set (match_operand:SI 0 "gen_reg_operand" "=r,r")
3671 (le:SI (match_dup 1) (match_dup 2)))
3672 (clobber (match_scratch:SI 3 "=r,X"))]
3673 ""
3674 "@
3675 doz %3,%2,%1\;sfi %0,%3,0\;ae. %0,%0,%3
3676 ai %0,%1,-1\;aze %0,%0\;sri. %0,%0,31"
3677 [(set_attr "type" "delayed_compare,compare")])
3678
3679(define_insn ""
3680 [(set (match_operand:SI 0 "gen_reg_operand" "=r,r")
3681 (plus:SI (le:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
3682 (match_operand:SI 2 "reg_or_short_operand" "r,O"))
3683 (match_operand:SI 3 "gen_reg_operand" "r,r")))
3684 (clobber (match_scratch:SI 4 "=&r,&r"))]
3685 ""
3686 "@
3687 doz %4,%2,%1\;sfi %4,%4,0\;aze %0,%3
3688 srai %4,%1,31\;sf %4,%1,%4\;aze %0,%3")
3689
3690(define_insn ""
3691 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
3692 (compare:CC
3693 (plus:SI (le:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
3694 (match_operand:SI 2 "reg_or_short_operand" "r,O"))
3695 (match_operand:SI 3 "gen_reg_operand" "r,r"))
3696 (const_int 0)))
3697 (clobber (match_scratch:SI 4 "=&r,&r"))]
3698 ""
3699 "@
3700 doz %4,%2,%1\;sfi %4,%4,0\;aze. %4,%3
3701 srai %4,%1,31\;sf %4,%1,%4\;aze. %4,%3"
3702 [(set_attr "type" "compare")])
3703
3704(define_insn ""
3705 [(set (match_operand:CC 5 "cc_reg_operand" "=x,x")
3706 (compare:CC
3707 (plus:SI (le:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
3708 (match_operand:SI 2 "reg_or_short_operand" "r,O"))
3709 (match_operand:SI 3 "gen_reg_operand" "r,r"))
3710 (const_int 0)))
3711 (set (match_operand:SI 0 "gen_reg_operand" "=r,r")
3712 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
3713 (clobber (match_scratch:SI 4 "=&r,&r"))]
3714 ""
3715 "@
3716 doz %4,%2,%1\;sfi %4,%4,0\;aze. %0,%3
3717 srai %4,%1,31\;sf %4,%1,%4\;aze. %0,%3"
3718 [(set_attr "type" "compare")])
3719
3720(define_insn ""
3721 [(set (match_operand:SI 0 "gen_reg_operand" "=r,r")
3722 (neg:SI (le:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
3723 (match_operand:SI 2 "reg_or_short_operand" "r,O"))))]
3724 ""
3725 "@
3726 doz %0,%2,%1\;ai %0,%0,-1\;sfe %0,%0,%0
3727 ai %0,%1,-1\;aze %0,%0\;srai %0,%0,31")
3728
3729(define_insn ""
3730 [(set (match_operand:SI 0 "gen_reg_operand" "=r")
3731 (leu:SI (match_operand:SI 1 "gen_reg_operand" "r")
3732 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
3733 ""
3734 "sf%I2 %0,%1,%2\;cal %0,0(0)\;ae %0,%0,%0")
3735
3736(define_insn ""
3737 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
3738 (compare:CC
3739 (leu:SI (match_operand:SI 1 "gen_reg_operand" "r")
3740 (match_operand:SI 2 "reg_or_short_operand" "rI"))
3741 (const_int 0)))
3742 (set (match_operand:SI 0 "gen_reg_operand" "=r")
3743 (leu:SI (match_dup 1) (match_dup 2)))]
3744 ""
3745 "sf%I2 %0,%1,%2\;cal %0,0(0)\;ae. %0,%0,%0"
3746 [(set_attr "type" "compare")])
3747
3748(define_insn ""
3749 [(set (match_operand:SI 0 "gen_reg_operand" "=r")
3750 (plus:SI (leu:SI (match_operand:SI 1 "gen_reg_operand" "r")
3751 (match_operand:SI 2 "reg_or_short_operand" "rI"))
3752 (match_operand:SI 3 "gen_reg_operand" "r")))
3753 (clobber (match_scratch:SI 4 "=&r"))]
3754 ""
3755 "sf%I2 %4,%1,%2\;aze %0,%3")
3756
3757(define_insn ""
3758 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
3759 (compare:CC
3760 (plus:SI (leu:SI (match_operand:SI 1 "gen_reg_operand" "r")
3761 (match_operand:SI 2 "reg_or_short_operand" "rI"))
3762 (match_operand:SI 3 "gen_reg_operand" "r"))
3763 (const_int 0)))
3764 (clobber (match_scratch:SI 4 "=&r"))]
3765 ""
3766 "sf%I2 %4,%1,%2\;aze. %4,%3"
3767 [(set_attr "type" "compare")])
3768
3769(define_insn ""
3770 [(set (match_operand:CC 5 "cc_reg_operand" "=x")
3771 (compare:CC
3772 (plus:SI (leu:SI (match_operand:SI 1 "gen_reg_operand" "r")
3773 (match_operand:SI 2 "reg_or_short_operand" "rI"))
3774 (match_operand:SI 3 "gen_reg_operand" "r"))
3775 (const_int 0)))
3776 (set (match_operand:SI 0 "gen_reg_operand" "=r")
3777 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
3778 (clobber (match_scratch:SI 4 "=&r"))]
3779 ""
3780 "sf%I2 %4,%1,%2\;aze. %0,%3"
3781 [(set_attr "type" "compare")])
3782
3783(define_insn ""
3784 [(set (match_operand:SI 0 "gen_reg_operand" "=r")
3785 (neg:SI (leu:SI (match_operand:SI 1 "gen_reg_operand" "r")
3786 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
3787 ""
3788 "sf%I2 %0,%1,%2\;sfe %0,%0,%0\;nand %0,%0,%0")
3789
3790(define_insn ""
3791 [(set (match_operand:SI 0 "gen_reg_operand" "=r")
3792 (and:SI (neg:SI
3793 (leu:SI (match_operand:SI 1 "gen_reg_operand" "r")
3794 (match_operand:SI 2 "reg_or_short_operand" "rI")))
3795 (match_operand:SI 3 "gen_reg_operand" "r")))
3796 (clobber (match_scratch:SI 4 "=&r"))]
3797 ""
3798 "sf%I2 %4,%1,%2\;sfe %4,%4,%4\;andc %0,%3,%4")
3799
3800(define_insn ""
3801 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
3802 (compare:CC
3803 (and:SI (neg:SI
3804 (leu:SI (match_operand:SI 1 "gen_reg_operand" "r")
3805 (match_operand:SI 2 "reg_or_short_operand" "rI")))
3806 (match_operand:SI 3 "gen_reg_operand" "r"))
3807 (const_int 0)))
3808 (clobber (match_scratch:SI 4 "=&r"))]
3809 ""
3810 "sf%I2 %4,%1,%2\;sfe %4,%4,%4\;andc. %4,%3,%4"
3811 [(set_attr "type" "compare")])
3812
3813(define_insn ""
3814 [(set (match_operand:CC 5 "cc_reg_operand" "=x")
3815 (compare:CC
3816 (and:SI (neg:SI
3817 (leu:SI (match_operand:SI 1 "gen_reg_operand" "r")
3818 (match_operand:SI 2 "reg_or_short_operand" "rI")))
3819 (match_operand:SI 3 "gen_reg_operand" "r"))
3820 (const_int 0)))
3821 (set (match_operand:SI 0 "gen_reg_operand" "=r")
3822 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
3823 (clobber (match_scratch:SI 4 "=&r"))]
3824 ""
3825 "sf%I2 %4,%1,%2\;sfe %4,%4,%4\;andc. %0,%3,%4"
3826 [(set_attr "type" "compare")])
3827
3828(define_insn ""
3829 [(set (match_operand:SI 0 "gen_reg_operand" "=r")
3830 (lt:SI (match_operand:SI 1 "gen_reg_operand" "r")
3831 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
3832 ""
3833 "doz%I2 %0,%1,%2\;nabs %0,%0\;sri %0,%0,31")
3834
3835(define_insn ""
3836 [(set (match_operand:SI 3 "cc_reg_operand" "=x")
3837 (compare:CC
3838 (lt:SI (match_operand:SI 1 "gen_reg_operand" "r")
3839 (match_operand:SI 2 "reg_or_short_operand" "rI"))
3840 (const_int 0)))
3841 (set (match_operand:SI 0 "gen_reg_operand" "=r")
3842 (lt:SI (match_dup 1) (match_dup 2)))]
3843 ""
3844 "doz%I2 %0,%1,%2\;nabs %0,%0\;sri. %0,%0,31"
3845 [(set_attr "type" "delayed_compare")])
3846
3847(define_insn ""
3848 [(set (match_operand:SI 0 "gen_reg_operand" "=r")
3849 (plus:SI (lt:SI (match_operand:SI 1 "gen_reg_operand" "r")
3850 (match_operand:SI 2 "reg_or_short_operand" "rI"))
3851 (match_operand:SI 3 "gen_reg_operand" "r")))
3852 (clobber (match_scratch:SI 4 "=&r"))]
3853 ""
3854 "doz%I2 %4,%1,%2\;ai %4,%4,-1\;aze %0,%3")
3855
3856(define_insn ""
3857 [(set (match_operand:SI 0 "cc_reg_operand" "=x")
3858 (compare:CC
3859 (plus:SI (lt:SI (match_operand:SI 1 "gen_reg_operand" "r")
3860 (match_operand:SI 2 "reg_or_short_operand" "rI"))
3861 (match_operand:SI 3 "gen_reg_operand" "r"))
3862 (const_int 0)))
3863 (clobber (match_scratch:SI 4 "=&r"))]
3864 ""
3865 "doz%I2 %4,%1,%2\;ai %4,%4,-1\;aze. %4,%3"
3866 [(set_attr "type" "compare")])
3867
3868(define_insn ""
3869 [(set (match_operand:SI 5 "cc_reg_operand" "=x")
3870 (compare:CC
3871 (plus:SI (lt:SI (match_operand:SI 1 "gen_reg_operand" "r")
3872 (match_operand:SI 2 "reg_or_short_operand" "rI"))
3873 (match_operand:SI 3 "gen_reg_operand" "r"))
3874 (const_int 0)))
3875 (set (match_operand:SI 0 "gen_reg_operand" "=r")
3876 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
3877 (clobber (match_scratch:SI 4 "=&r"))]
3878 ""
3879 "doz%I2 %4,%1,%2\;ai %4,%4,-1\;aze. %0,%3"
3880 [(set_attr "type" "compare")])
3881
3882(define_insn ""
3883 [(set (match_operand:SI 0 "gen_reg_operand" "=r")
3884 (neg:SI (lt:SI (match_operand:SI 1 "gen_reg_operand" "r")
3885 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
3886 ""
3887 "doz%I2 %0,%1,%2\;nabs %0,%0\;srai %0,%0,31")
3888
3889(define_insn ""
3890 [(set (match_operand:SI 0 "gen_reg_operand" "=r,r")
3891 (ltu:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
3892 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))]
3893 ""
3894 "@
3895 sf %0,%2,%1\;sfe %0,%0,%0\;neg %0,%0
3896 ai %0,%1,%n2\;sfe %0,%0,%0\;neg %0,%0")
3897
3898(define_insn ""
3899 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x")
3900 (compare:CC
3901 (ltu:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
3902 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
3903 (const_int 0)))
3904 (set (match_operand:SI 0 "gen_reg_operand" "=r,r")
3905 (ltu:SI (match_dup 1) (match_dup 2)))]
3906 ""
3907 "@
3908 sf %0,%2,%1\;sfe %0,%0,%0\;neg. %0,%0
3909 ai %0,%1,%n2\;sfe %0,%0,%0\;neg. %0,%0"
3910 [(set_attr "type" "compare")])
3911
3912(define_insn ""
3913 [(set (match_operand:SI 0 "gen_reg_operand" "=r,r,r,r")
3914 (plus:SI (ltu:SI (match_operand:SI 1 "gen_reg_operand" "r,r,r,r")
3915 (match_operand:SI 2 "reg_or_neg_short_operand" "r,r,P,P"))
3916 (match_operand:SI 3 "reg_or_short_operand" "r,I,r,I")))
3917 (clobber (match_scratch:SI 4 "=&r,r,&r,r"))]
3918 ""
3919 "@
3920 sf %4,%2,%1\;sfe %4,%4,%4\;sf%I3 %0,%4,%3
3921 sf %4,%2,%1\;sfe %4,%4,%4\;sf%I3 %0,%4,%3
3922 ai %4,%1,%n2\;sfe %4,%4,%4\;sf%I3 %0,%4,%3
3923 ai %4,%1,%n2\;sfe %4,%4,%4\;sf%I3 %0,%4,%3")
3924
3925(define_insn ""
3926 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x")
3927 (compare:CC
3928 (plus:SI (ltu:SI (match_operand:SI 1 "gen_reg_operand" "r,r,r,r")
3929 (match_operand:SI 2 "reg_or_neg_short_operand" "r,r,P,P"))
3930 (match_operand:SI 3 "reg_or_short_operand" "r,I,r,I"))
3931 (const_int 0)))
3932 (clobber (match_scratch:SI 4 "=&r,r,&r,r"))]
3933 ""
3934 "@
3935 sf %4,%2,%1\;sfe %4,%4,%4\;sf%I3. %4,%4,%3
3936 sf %4,%2,%1\;sfe %4,%4,%4\;sf%I3. %4,%4,%3
3937 ai %4,%1,%n2\;sfe %4,%4,%4\;sf%I3. %4,%4,%3
3938 ai %4,%1,%n2\;sfe %4,%4,%4\;sf%I3. %4,%4,%3"
3939 [(set_attr "type" "compare")])
3940
3941(define_insn ""
3942 [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,x,x")
3943 (compare:CC
3944 (plus:SI (ltu:SI (match_operand:SI 1 "gen_reg_operand" "r,r,r,r")
3945 (match_operand:SI 2 "reg_or_neg_short_operand" "r,r,P,P"))
3946 (match_operand:SI 3 "reg_or_short_operand" "r,I,r,I"))
3947 (const_int 0)))
3948 (set (match_operand:SI 0 "gen_reg_operand" "=r,r,r,r")
3949 (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
3950 (clobber (match_scratch:SI 4 "=&r,r,&r,r"))]
3951 ""
3952 "@
3953 sf %4,%2,%1\;sfe %4,%4,%4\;sf%I3. %0,%4,%3
3954 sf %4,%2,%1\;sfe %4,%4,%4\;sf%I3. %0,%4,%3
3955 ai %4,%1,%n2\;sfe %4,%4,%4\;sf%I3. %0,%4,%3
3956 ai %4,%1,%n2\;sfe %4,%4,%4\;sf%I3. %0,%4,%3"
3957 [(set_attr "type" "compare")])
3958
3959(define_insn ""
3960 [(set (match_operand:SI 0 "gen_reg_operand" "=r,r")
3961 (neg:SI (ltu:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
3962 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))))]
3963 ""
3964 "@
3965 sf %0,%2,%1\;sfe %0,%0,%0
3966 ai %0,%1,%n2\;sfe %0,%0,%0")
3967
3968(define_insn ""
3969 [(set (match_operand:SI 0 "gen_reg_operand" "=r")
3970 (ge:SI (match_operand:SI 1 "gen_reg_operand" "r")
3971 (match_operand:SI 2 "reg_or_short_operand" "rI")))
3972 (clobber (match_scratch:SI 3 "=r"))]
3973 ""
3974 "doz%I2 %3,%1,%2\;sfi %0,%3,0\;ae %0,%0,%3")
3975
3976(define_insn ""
3977 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
3978 (compare:CC
3979 (ge:SI (match_operand:SI 1 "gen_reg_operand" "r")
3980 (match_operand:SI 2 "reg_or_short_operand" "rI"))
3981 (const_int 0)))
3982 (set (match_operand:SI 0 "gen_reg_operand" "=r")
3983 (ge:SI (match_dup 1) (match_dup 2)))
3984 (clobber (match_scratch:SI 3 "=r"))]
3985 ""
3986 "doz%I2 %3,%1,%2\;sfi %0,%3,0\;ae. %0,%0,%3"
3987 [(set_attr "type" "compare")])
3988
3989(define_insn ""
3990 [(set (match_operand:SI 0 "gen_reg_operand" "=r")
3991 (plus:SI (ge:SI (match_operand:SI 1 "gen_reg_operand" "r")
3992 (match_operand:SI 2 "reg_or_short_operand" "rI"))
3993 (match_operand:SI 3 "gen_reg_operand" "r")))
3994 (clobber (match_scratch:SI 4 "=&r"))]
3995 ""
3996 "doz%I2 %4,%1,%2\;sfi %4,%4,0\;aze %0,%3")
3997
3998(define_insn ""
3999 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
4000 (compare:CC
4001 (plus:SI (ge:SI (match_operand:SI 1 "gen_reg_operand" "r")
4002 (match_operand:SI 2 "reg_or_short_operand" "rI"))
4003 (match_operand:SI 3 "gen_reg_operand" "r"))
4004 (const_int 0)))
4005 (clobber (match_scratch:SI 4 "=&r"))]
4006 ""
4007 "doz%I2 %4,%1,%2\;sfi %4,%4,0\;aze. %4,%3"
4008 [(set_attr "type" "compare")])
4009
4010(define_insn ""
4011 [(set (match_operand:CC 5 "cc_reg_operand" "=x")
4012 (compare:CC
4013 (plus:SI (ge:SI (match_operand:SI 1 "gen_reg_operand" "r")
4014 (match_operand:SI 2 "reg_or_short_operand" "rI"))
4015 (match_operand:SI 3 "gen_reg_operand" "r"))
4016 (const_int 0)))
4017 (set (match_operand:SI 0 "gen_reg_operand" "=r")
4018 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4019 (clobber (match_scratch:SI 4 "=&r"))]
4020 ""
4021 "doz%I2 %4,%1,%2\;sfi %4,%4,0\;aze. %0,%3"
4022 [(set_attr "type" "compare")])
4023
4024(define_insn ""
4025 [(set (match_operand:SI 0 "gen_reg_operand" "=r")
4026 (neg:SI (ge:SI (match_operand:SI 1 "gen_reg_operand" "r")
4027 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
4028 ""
4029 "doz%I2 %0,%1,%2\;ai %0,%0,-1\;sfe %0,%0,%0")
4030
4031;; This is (and (neg (ge X (const_int 0))) Y).
4032(define_insn ""
4033 [(set (match_operand:SI 0 "gen_reg_operand" "=r")
4034 (and:SI (neg:SI
4035 (lshiftrt:SI
4036 (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
4037 (const_int 31)))
4038 (match_operand:SI 2 "gen_reg_operand" "r")))
4039 (clobber (match_scratch:SI 3 "=&r"))]
4040 ""
4041 "srai %3,%1,31\;andc %0,%2,%3")
4042
4043(define_insn ""
4044 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
4045 (compare:CC
4046 (and:SI (neg:SI
4047 (lshiftrt:SI
4048 (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
4049 (const_int 31)))
4050 (match_operand:SI 2 "gen_reg_operand" "r"))
4051 (const_int 0)))
4052 (clobber (match_scratch:SI 3 "=&r"))]
4053 ""
4054 "srai %3,%1,31\;andc. %3,%2,%3"
4055 [(set_attr "type" "compare")])
4056
4057(define_insn ""
4058 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
4059 (compare:CC
4060 (and:SI (neg:SI
4061 (lshiftrt:SI
4062 (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
4063 (const_int 31)))
4064 (match_operand:SI 2 "gen_reg_operand" "r"))
4065 (const_int 0)))
4066 (set (match_operand:SI 0 "gen_reg_operand" "=r")
4067 (and:SI (neg:SI (lshiftrt:SI (not:SI (match_dup 1))
4068 (const_int 31)))
4069 (match_dup 2)))
4070 (clobber (match_scratch:SI 3 "=&r"))]
4071 ""
4072 "srai %3,%1,31\;andc. %0,%2,%3"
4073 [(set_attr "type" "compare")])
4074
4075(define_insn ""
4076 [(set (match_operand:SI 0 "gen_reg_operand" "=r,r")
4077 (geu:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
4078 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))]
4079 ""
4080 "@
4081 sf %0,%2,%1\;cal %0,0(0)\;ae %0,%0,%0
4082 ai %0,%1,%n2\;cal %0,0(0)\;ae %0,%0,%0")
4083
4084(define_insn ""
4085 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x")
4086 (compare:CC
4087 (geu:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
4088 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
4089 (const_int 0)))
4090 (set (match_operand:SI 0 "gen_reg_operand" "=r,r")
4091 (geu:SI (match_dup 1) (match_dup 2)))]
4092 ""
4093 "@
4094 sf %0,%2,%1\;cal %0,0(0)\;ae. %0,%0,%0
4095 ai %0,%1,%n2\;cal %0,0(0)\;ae. %0,%0,%0"
4096 [(set_attr "type" "compare")])
4097
4098(define_insn ""
4099 [(set (match_operand:SI 0 "gen_reg_operand" "=r,r")
4100 (plus:SI (geu:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
4101 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
4102 (match_operand:SI 3 "gen_reg_operand" "r,r")))
4103 (clobber (match_scratch:SI 4 "=&r,&r"))]
4104 ""
4105 "@
4106 sf %4,%2,%1\;aze %0,%3
4107 ai %4,%1,%n2\;aze %0,%3")
4108
4109(define_insn ""
4110 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
4111 (compare:CC
4112 (plus:SI (geu:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
4113 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
4114 (match_operand:SI 3 "gen_reg_operand" "r,r"))
4115 (const_int 0)))
4116 (clobber (match_scratch:SI 4 "=&r,&r"))]
4117 ""
4118 "@
4119 sf %4,%2,%1\;aze. %4,%3
4120 ai %4,%1,%n2\;aze. %4,%3"
4121 [(set_attr "type" "compare")])
4122
4123(define_insn ""
4124 [(set (match_operand:CC 5 "cc_reg_operand" "=x,x")
4125 (compare:CC
4126 (plus:SI (geu:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
4127 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
4128 (match_operand:SI 3 "gen_reg_operand" "r,r"))
4129 (const_int 0)))
4130 (set (match_operand:SI 0 "gen_reg_operand" "=r,r")
4131 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4132 (clobber (match_scratch:SI 4 "=&r,&r"))]
4133 ""
4134 "@
4135 sf %4,%2,%1\;aze. %0,%3
4136 ai %4,%1,%n2\;aze. %4,%3"
4137 [(set_attr "type" "compare")])
4138
4139(define_insn ""
4140 [(set (match_operand:SI 0 "gen_reg_operand" "=r,r")
4141 (neg:SI (geu:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
4142 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))]
4143 ""
4144 "@
4145 sf %0,%2,%1\;sfe %0,%0,%0\;nand %0,%0,%0
4146 sfi %0,%1,-1\;a%I2 %0,%0,%2\;sfe %0,%0,%0")
4147
4148(define_insn ""
4149 [(set (match_operand:SI 0 "gen_reg_operand" "=r,r")
4150 (and:SI (neg:SI
4151 (geu:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
4152 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))
4153 (match_operand:SI 3 "gen_reg_operand" "r,r")))
4154 (clobber (match_scratch:SI 4 "=&r,&r"))]
4155 ""
4156 "@
4157 sf %4,%2,%1\;sfe %4,%4,%4\;andc %0,%3,%4
4158 ai %4,%1,%n2\;sfe %4,%4,%4\;andc %0,%3,%4")
4159
4160(define_insn ""
4161 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
4162 (compare:CC
4163 (and:SI (neg:SI
4164 (geu:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
4165 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))
4166 (match_operand:SI 3 "gen_reg_operand" "r,r"))
4167 (const_int 0)))
4168 (clobber (match_scratch:SI 4 "=&r,&r"))]
4169 ""
4170 "@
4171 sf %4,%2,%1\;sfe %4,%4,%4\;andc. %4,%3,%4
4172 ai %4,%1,%n2\;sfe %4,%4,%4\;andc. %4,%3,%4"
4173 [(set_attr "type" "compare")])
4174
4175(define_insn ""
4176 [(set (match_operand:CC 5 "cc_reg_operand" "=x,x")
4177 (compare:CC
4178 (and:SI (neg:SI
4179 (geu:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
4180 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))
4181 (match_operand:SI 3 "gen_reg_operand" "r,r"))
4182 (const_int 0)))
4183 (set (match_operand:SI 0 "gen_reg_operand" "=r,r")
4184 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
4185 (clobber (match_scratch:SI 4 "=&r,&r"))]
4186 ""
4187 "@
4188 sf %4,%2,%1\;sfe %4,%4,%4\;andc. %0,%3,%4
4189 ai %4,%1,%n2\;sfe %4,%4,%4\;andc. %0,%3,%4"
4190 [(set_attr "type" "compare")])
4191
4192(define_insn ""
4193 [(set (match_operand:SI 0 "gen_reg_operand" "=r")
4194 (gt:SI (match_operand:SI 1 "gen_reg_operand" "r")
4195 (const_int 0)))]
4196 ""
4197 "sfi %0,%1,0\;ame %0,%0\;sri %0,%0,31")
4198
4199(define_insn ""
4200 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
4201 (compare:CC
4202 (gt:SI (match_operand:SI 1 "gen_reg_operand" "r")
4203 (const_int 0))
4204 (const_int 0)))
4205 (set (match_operand:SI 0 "gen_reg_operand" "=r")
4206 (gt:SI (match_dup 1) (const_int 0)))]
4207 ""
4208 "sfi %0,%1,0\;ame %0,%0\;sri. %0,%0,31"
4209 [(set_attr "type" "delayed_compare")])
4210
4211(define_insn ""
4212 [(set (match_operand:SI 0 "gen_reg_operand" "=r")
4213 (gt:SI (match_operand:SI 1 "gen_reg_operand" "r")
4214 (match_operand:SI 2 "reg_or_short_operand" "r")))]
4215 ""
4216 "doz %0,%2,%1\;nabs %0,%0\;sri %0,%0,31")
4217
4218(define_insn ""
4219 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
4220 (compare:CC
4221 (gt:SI (match_operand:SI 1 "gen_reg_operand" "r")
4222 (match_operand:SI 2 "reg_or_short_operand" "r"))
4223 (const_int 0)))
4224 (set (match_operand:SI 0 "gen_reg_operand" "=r")
4225 (gt:SI (match_dup 1) (match_dup 2)))]
4226 ""
4227 "doz %0,%2,%1\;nabs %0,%0\;sri. %0,%0,31"
4228 [(set_attr "type" "delayed_compare")])
4229
4230(define_insn ""
4231 [(set (match_operand:SI 0 "gen_reg_operand" "=r")
4232 (plus:SI (gt:SI (match_operand:SI 1 "gen_reg_operand" "r")
4233 (const_int 0))
4234 (match_operand:SI 2 "gen_reg_operand" "r")))
4235 (clobber (match_scratch:SI 3 "=&r"))]
4236 ""
4237 "a %3,%1,%1\;sfe %3,%1,%3\;aze %0,%2")
4238
4239(define_insn ""
4240 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
4241 (compare:CC
4242 (plus:SI (gt:SI (match_operand:SI 1 "gen_reg_operand" "r")
4243 (const_int 0))
4244 (match_operand:SI 2 "gen_reg_operand" "r"))
4245 (const_int 0)))
4246 (clobber (match_scratch:SI 3 "=&r"))]
4247 ""
4248 "a %3,%1,%1\;sfe %3,%1,%3\;aze. %0,%2"
4249 [(set_attr "type" "compare")])
4250
4251(define_insn ""
4252 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
4253 (compare:CC
4254 (plus:SI (gt:SI (match_operand:SI 1 "gen_reg_operand" "r")
4255 (const_int 0))
4256 (match_operand:SI 2 "gen_reg_operand" "r"))
4257 (const_int 0)))
4258 (set (match_operand:SI 0 "gen_reg_operand" "=r")
4259 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
4260 (clobber (match_scratch:SI 3 "=&r"))]
4261 ""
4262 "a %3,%1,%1\;sfe %3,%1,%3\;aze. %3,%2"
4263 [(set_attr "type" "compare")])
4264
4265(define_insn ""
4266 [(set (match_operand:SI 0 "gen_reg_operand" "=r")
4267 (plus:SI (gt:SI (match_operand:SI 1 "gen_reg_operand" "r")
4268 (match_operand:SI 2 "reg_or_short_operand" "r"))
4269 (match_operand:SI 3 "gen_reg_operand" "r")))
4270 (clobber (match_scratch:SI 4 "=&r"))]
4271 ""
4272 "doz %4,%2,%1\;ai %4,%4,-1\;aze %0,%3")
4273
4274(define_insn ""
4275 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
4276 (compare:CC
4277 (plus:SI (gt:SI (match_operand:SI 1 "gen_reg_operand" "r")
4278 (match_operand:SI 2 "reg_or_short_operand" "r"))
4279 (match_operand:SI 3 "gen_reg_operand" "r"))
4280 (const_int 0)))
4281 (clobber (match_scratch:SI 4 "=&r"))]
4282 ""
4283 "doz %4,%2,%1\;ai %4,%4,-1\;aze. %4,%3"
4284 [(set_attr "type" "compare")])
4285
4286(define_insn ""
4287 [(set (match_operand:CC 5 "cc_reg_operand" "=x")
4288 (compare:CC
4289 (plus:SI (gt:SI (match_operand:SI 1 "gen_reg_operand" "r")
4290 (match_operand:SI 2 "reg_or_short_operand" "r"))
4291 (match_operand:SI 3 "gen_reg_operand" "r"))
4292 (const_int 0)))
4293 (set (match_operand:SI 0 "gen_reg_operand" "=r")
4294 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4295 (clobber (match_scratch:SI 4 "=&r"))]
4296 ""
4297 "doz %4,%2,%1\;ai %4,%4,-1\;aze. %0,%3"
4298 [(set_attr "type" "compare")])
4299
4300(define_insn ""
4301 [(set (match_operand:SI 0 "gen_reg_operand" "=r")
4302 (neg:SI (gt:SI (match_operand:SI 1 "gen_reg_operand" "r")
4303 (const_int 0))))]
4304 ""
4305 "sfi %0,%1,0\;ame %0,%0\;srai %0,%0,31")
4306
4307(define_insn ""
4308 [(set (match_operand:SI 0 "gen_reg_operand" "=r")
4309 (neg:SI (gt:SI (match_operand:SI 1 "gen_reg_operand" "r")
4310 (match_operand:SI 2 "reg_or_short_operand" "r"))))]
4311 ""
4312 "doz %0,%2,%1\;nabs %0,%0\;srai %0,%0,31")
4313
4314(define_insn ""
4315 [(set (match_operand:SI 0 "gen_reg_operand" "=r")
4316 (gtu:SI (match_operand:SI 1 "gen_reg_operand" "r")
4317 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
4318 ""
4319 "sf%I2 %0,%1,%2\;sfe %0,%0,%0\;neg %0,%0")
4320
4321(define_insn ""
4322 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
4323 (compare:CC
4324 (gtu:SI (match_operand:SI 1 "gen_reg_operand" "r")
4325 (match_operand:SI 2 "reg_or_short_operand" "rI"))
4326 (const_int 0)))
4327 (set (match_operand:SI 0 "gen_reg_operand" "=r")
4328 (gtu:SI (match_dup 1) (match_dup 2)))]
4329 ""
4330 "sf%I2 %0,%1,%2\;sfe %0,%0,%0\;neg. %0,%0"
4331 [(set_attr "type" "compare")])
4332
4333(define_insn ""
4334 [(set (match_operand:SI 0 "gen_reg_operand" "=r,r")
4335 (plus:SI (gtu:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
4336 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
4337 (match_operand:SI 3 "reg_or_short_operand" "r,I")))
4338 (clobber (match_scratch:SI 4 "=&r,&r"))]
4339 ""
4340 "sf%I2 %4,%1,%2\;sfe %4,%4,%4\;sf%I3 %0,%4,%3")
4341
4342(define_insn ""
4343 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
4344 (compare:CC
4345 (plus:SI (gtu:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
4346 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
4347 (match_operand:SI 3 "reg_or_short_operand" "r,I"))
4348 (const_int 0)))
4349 (clobber (match_scratch:SI 4 "=&r,&r"))]
4350 ""
4351 "sf%I2 %4,%1,%2\;sfe %4,%4,%4\;sf%I3. %4,%4,%3"
4352 [(set_attr "type" "compare")])
4353
4354(define_insn ""
4355 [(set (match_operand:CC 5 "cc_reg_operand" "=x,x")
4356 (compare:CC
4357 (plus:SI (gtu:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
4358 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
4359 (match_operand:SI 3 "reg_or_short_operand" "r,I"))
4360 (const_int 0)))
4361 (set (match_operand:SI 0 "gen_reg_operand" "=r,r")
4362 (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4363 (clobber (match_scratch:SI 4 "=&r,&r"))]
4364 ""
4365 "sf%I2 %4,%1,%2\;sfe %4,%4,%4\;sf%I3. %0,%4,%3"
4366 [(set_attr "type" "compare")])
4367
4368(define_insn ""
4369 [(set (match_operand:SI 0 "gen_reg_operand" "=r")
4370 (neg:SI (gtu:SI (match_operand:SI 1 "gen_reg_operand" "r")
4371 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
4372 ""
4373 "sf%I2 %0,%1,%2\;sfe %0,%0,%0")
4374\f
4375;; Define both directions of branch and return. If we need a reload
4376;; register, we'd rather use CR0 since it is much easier to copy a
4377;; register CC value to there.
4378
4379(define_insn ""
4380 [(set (pc)
4381 (if_then_else (match_operator 1 "branch_comparison_operator"
4382 [(match_operand 2
4383 "cc_reg_operand" "x,?y")
4384 (const_int 0)])
4385 (label_ref (match_operand 0 "" ""))
4386 (pc)))]
4387 ""
4388 "%C1bc %t1,%j1,%0")
4389
4390(define_insn ""
4391 [(set (pc)
4392 (if_then_else (match_operator 0 "branch_comparison_operator"
4393 [(match_operand 1
4394 "cc_reg_operand" "x,?y")
4395 (const_int 0)])
4396 (return)
4397 (pc)))]
4398 "direct_return ()"
4399 "%C0bcr %t0,%j0")
4400
4401(define_insn ""
4402 [(set (pc)
4403 (if_then_else (match_operator 1 "branch_comparison_operator"
4404 [(match_operand 2
4405 "cc_reg_operand" "x,?y")
4406 (const_int 0)])
4407 (pc)
4408 (label_ref (match_operand 0 "" ""))))]
4409 ""
4410 "%C1bc %T1,%j1,%0")
4411
4412(define_insn ""
4413 [(set (pc)
4414 (if_then_else (match_operator 0 "branch_comparison_operator"
4415 [(match_operand 1
4416 "cc_reg_operand" "x,?y")
4417 (const_int 0)])
4418 (pc)
4419 (return)))]
4420 "direct_return ()"
4421 "%C0bcr %T0,%j0")
4422
4423;; Unconditional branch and return.
4424
4425(define_insn "jump"
4426 [(set (pc)
4427 (label_ref (match_operand 0 "" "")))]
4428 ""
4429 "b %l0")
4430
4431(define_insn "return"
4432 [(return)]
4433 "direct_return ()"
4434 "br")
4435
4436(define_insn "indirect_jump"
4437 [(set (pc) (match_operand:SI 0 "register_operand" "c,l"))]
4438 ""
4439 "@
4440 bctr
4441 br")
4442
4443;; Table jump for switch statements:
4444(define_expand "tablejump"
4445 [(set (match_dup 3)
4446 (plus:SI (match_operand:SI 0 "" "")
4447 (match_dup 2)))
4448 (parallel [(set (pc) (match_dup 3))
4449 (use (label_ref (match_operand 1 "" "")))])]
4450 ""
4451 "
4452{ operands[0] = force_reg (SImode, operands[0]);
4453 operands[2] = force_reg (SImode, gen_rtx (LABEL_REF, VOIDmode, operands[1]));
4454 operands[3] = gen_reg_rtx (SImode);
4455}")
4456
4457(define_insn ""
4458 [(set (pc)
4459 (match_operand:SI 0 "register_operand" "c,r"))
4460 (use (label_ref (match_operand 1 "" "")))]
4461 ""
4462 "@
4463 bctr
4464 br")
4465
4466(define_insn "nop"
4467 [(const_int 0)]
4468 ""
4469 "cror 0,0,0")
4470\f
4471;; Define the subtract-one-and-jump insns.
4472;; We need to be able to do this for any operand, including MEM, or we
4473;; will cause reload to blow up since we don't allow output reloads on
4474;; JUMP_INSNs.
4475(define_insn ""
4476 [(set (pc)
4477 (if_then_else (ne (match_operand:SI 1 "register_operand" "0,*r,*r")
4478 (const_int 1))
4479 (label_ref (match_operand 2 "" ""))
4480 (pc)))
4481 (set (match_operand:SI 0 "register_operand" "=c,*r,m*q*c*l")
4482 (plus:SI (match_dup 1) (const_int -1)))
4483 (clobber (match_scratch:CC 3 "=X,&x,&x"))
4484 (clobber (match_scratch:SI 4 "=X,X,r"))]
4485 ""
4486 "@
4487 bdn %l2
4488 #
4489 #")
4490
4491;; Similar, but we can use GE since we have a REG_NOTES.
4492(define_insn ""
4493 [(set (pc)
4494 (if_then_else (ge (match_operand:SI 1 "register_operand" "0,*r,*r")
4495 (const_int 0))
4496 (label_ref (match_operand 2 "" ""))
4497 (pc)))
4498 (set (match_operand:SI 0 "register_operand" "=c,*r,m*q*c*l")
4499 (plus:SI (match_dup 1) (const_int -1)))
4500 (clobber (match_scratch:CC 3 "=X,&x,&X"))
4501 (clobber (match_scratch:SI 4 "=X,X,r"))]
4502 "find_reg_note (insn, REG_NONNEG, 0)"
4503 "@
4504 bdn %l2
4505 #
4506 #")
4507
4508(define_insn ""
4509 [(set (pc)
4510 (if_then_else (eq (match_operand:SI 1 "register_operand" "0,*r,*r")
4511 (const_int 1))
4512 (label_ref (match_operand 2 "" ""))
4513 (pc)))
4514 (set (match_operand:SI 0 "register_operand" "=c,*r,m*q*c*l")
4515 (plus:SI (match_dup 1) (const_int -1)))
4516 (clobber (match_scratch:CC 3 "=X,&x,&x"))
4517 (clobber (match_scratch:SI 4 "=X,X,r"))]
4518 ""
4519 "@
4520 bdz %l2
4521 #
4522 #")
4523
4524(define_split
4525 [(set (pc)
4526 (if_then_else (match_operator 2 "comparison_operator"
4527 [(match_operand:SI 1 "gen_reg_operand" "")
4528 (const_int 1)])
4529 (match_operand 5 "" "")
4530 (match_operand 6 "" "")))
4531 (set (match_operand:SI 0 "gen_reg_operand" "")
4532 (plus:SI (match_dup 1) (const_int -1)))
4533 (clobber (match_scratch:CC 3 ""))
4534 (clobber (match_scratch:SI 4 ""))]
4535 "reload_completed"
4536 [(parallel [(set (match_dup 3)
4537 (compare:CC (plus:SI (match_dup 1) (const_int -1))
4538 (const_int 0)))
4539 (set (match_dup 0) (plus:SI (match_dup 1) (const_int -1)))])
4540 (set (pc) (if_then_else (match_dup 7) (match_dup 5) (match_dup 6)))]
4541 "
4542{ operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3],
4543 const0_rtx); }")
4544
4545(define_split
4546 [(set (pc)
4547 (if_then_else (match_operator 2 "comparison_operator"
4548 [(match_operand:SI 1 "gen_reg_operand" "")
4549 (const_int 1)])
4550 (match_operand 5 "" "")
4551 (match_operand 6 "" "")))
4552 (set (match_operand:SI 0 "general_operand" "")
4553 (plus:SI (match_dup 1) (const_int -1)))
4554 (clobber (match_scratch:CC 3 ""))
4555 (clobber (match_scratch:SI 4 ""))]
4556 "reload_completed && ! gen_reg_operand (operands[0], SImode)"
4557 [(parallel [(set (match_dup 3)
4558 (compare:CC (plus:SI (match_dup 1) (const_int -1))
4559 (const_int 0)))
4560 (set (match_dup 4) (plus:SI (match_dup 1) (const_int -1)))])
4561 (set (match_dup 0) (match_dup 4))
4562 (set (pc) (if_then_else (match_dup 7) (match_dup 5) (match_dup 6)))]
4563 "
4564{ operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3],
4565 const0_rtx); }")
4566\f
4567;;- Local variables:
4568;;- mode:emacs-lisp
4569;;- comment-start: ";;- "
4570;;- eval: (set-syntax-table (copy-sequence (syntax-table)))
4571;;- eval: (modify-syntax-entry ?[ "(]")
4572;;- eval: (modify-syntax-entry ?] ")[")
4573;;- eval: (modify-syntax-entry ?{ "(}")
4574;;- eval: (modify-syntax-entry ?} "){")
4575;;- End:
GNU Compiler Collection
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