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1fd4e8c1
RK		 1;;- Machine description for IBM RISC System 6000 (POWER) for GNU C compiler
2;; Copyright (C) 1990, 1991 Free Software Foundation, Inc.
3;; Contributed by Richard Kenner (kenner@nyu.edu)
4
5;; This file is part of GNU CC.
6
7;; GNU CC is free software; you can redistribute it and/or modify
8;; it under the terms of the GNU General Public License as published by
9;; the Free Software Foundation; either version 2, or (at your option)
10;; any later version.
11
12;; GNU CC is distributed in the hope that it will be useful,
13;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15;; GNU General Public License for more details.
16
17;; You should have received a copy of the GNU General Public License
18;; along with GNU CC; see the file COPYING. If not, write to
19;; the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
20
21;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
22\f
23;; Define an insn type attribute. This is used in function unit delay
24;; computations.
5c23c401 25(define_attr "type" "load,integer,fp,compare,delayed_compare,fpcompare,mtlr"
1fd4e8c1
RK		 26 (const_string "integer"))
27
28;; Memory delivers its result in two cycles.
29(define_function_unit "memory" 1 0 (eq_attr "type" "load") 2 0)
30
31;; We consider floating-point insns to deliver their result in two cycles
32;; to try to intersperse integer and FP operations.
33(define_function_unit "fp" 1 0 (eq_attr "type" "fp,fpcompare") 2 0)
34
35;; Most integer comparisons are ready in four cycles (a stall of three).
36(define_function_unit "compare" 1 0 (eq_attr "type" "compare") 4 0)
37
38;; Some integer comparisons aren't ready for five cycles (a stall of four).
39(define_function_unit "compare" 1 0 (eq_attr "type" "delayed_compare") 5 0)
40
41;; Floating-point comparisons take eight cycles.
42(define_function_unit "compare" 1 0 (eq_attr "type" "fpcompare") 8 0)
5c23c401
RK		 43
44;; Branches on LR cannot be done until five cycles after LR is set.
45(define_function_unit "branch" 1 0 (eq_attr "type" "mtlr") 5 0)
1fd4e8c1
RK		 46\f
47;; Start with fixed-point load and store insns. Here we put only the more
48;; complex forms. Basic data transfer is done later.
49
50(define_expand "zero_extendqisi2"
51 [(set (match_operand:SI 0 "gen_reg_operand" "")
52 (zero_extend:SI (match_operand:QI 1 "gen_reg_operand" "")))]
53 ""
54 "")
55
56(define_insn ""
57 [(set (match_operand:SI 0 "gen_reg_operand" "=r,r")
58 (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
59 ""
60 "@
61 lbz%U1%X1 %0,%1
62 rlinm %0,%1,0,24,31"
63 [(set_attr "type" "load,*")])
64
65(define_insn ""
66 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
67 (compare:CC (zero_extend:SI (match_operand:QI 1 "gen_reg_operand" "r"))
68 (const_int 0)))
69 (clobber (match_scratch:SI 2 "=r"))]
70 ""
71 "andil. %2,%1,255"
72 [(set_attr "type" "compare")])
73
74(define_insn ""
75 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
76 (compare:CC (zero_extend:SI (match_operand:QI 1 "gen_reg_operand" "r"))
77 (const_int 0)))
78 (set (match_operand:SI 0 "gen_reg_operand" "=r")
79 (zero_extend:SI (match_dup 1)))]
80 ""
81 "andil. %0,%1,255"
82 [(set_attr "type" "compare")])
83
84(define_expand "zero_extendqihi2"
85 [(set (match_operand:HI 0 "gen_reg_operand" "")
86 (zero_extend:HI (match_operand:QI 1 "gen_reg_operand" "")))]
87 ""
88 "")
89
90(define_insn ""
91 [(set (match_operand:HI 0 "gen_reg_operand" "=r,r")
92 (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
93 ""
94 "@
95 lbz%U1%X1 %0,%1
96 rlinm %0,%1,0,24,31"
97 [(set_attr "type" "load,*")])
98
99(define_expand "zero_extendhisi2"
100 [(set (match_operand:SI 0 "gen_reg_operand" "r")
101 (zero_extend:SI (match_operand:HI 1 "gen_reg_operand" "")))]
102 ""
103 "")
104
105(define_insn ""
106 [(set (match_operand:SI 0 "gen_reg_operand" "=r,r")
107 (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
108 ""
109 "@
110 lhz%U1%X1 %0,%1
111 rlinm %0,%1,0,16,31"
112 [(set_attr "type" "load,*")])
113
114(define_insn ""
115 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
116 (compare:CC (zero_extend:SI (match_operand:HI 1 "gen_reg_operand" "r"))
117 (const_int 0)))
118 (clobber (match_scratch:SI 2 "=r"))]
119 ""
120 "andil. %2,%1,65535"
121 [(set_attr "type" "compare")])
122
123(define_insn ""
124 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
125 (compare:CC (zero_extend:SI (match_operand:HI 1 "gen_reg_operand" "r"))
126 (const_int 0)))
127 (set (match_operand:SI 0 "gen_reg_operand" "=r")
128 (zero_extend:SI (match_dup 1)))]
129 ""
130 "andil. %0,%1,65535"
131 [(set_attr "type" "compare")])
132
133(define_expand "extendhisi2"
134 [(set (match_operand:SI 0 "gen_reg_operand" "")
135 (sign_extend:SI (match_operand:HI 1 "gen_reg_operand" "")))]
136 ""
137 "")
138
139(define_insn ""
140 [(set (match_operand:SI 0 "gen_reg_operand" "=r,r")
141 (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
142 ""
143 "@
144 lha%U1%X1 %0,%1
145 exts %0,%1"
146 [(set_attr "type" "load,*")])
147
148(define_insn ""
149 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
150 (compare:CC (sign_extend:SI (match_operand:HI 1 "gen_reg_operand" "r"))
151 (const_int 0)))
152 (clobber (match_scratch:SI 2 "=r"))]
153 ""
154 "exts. %2,%1"
155 [(set_attr "type" "compare")])
156
157(define_insn ""
158 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
159 (compare:CC (sign_extend:SI (match_operand:HI 1 "gen_reg_operand" "r"))
160 (const_int 0)))
161 (set (match_operand:SI 0 "gen_reg_operand" "=r")
162 (sign_extend:SI (match_dup 1)))]
163 ""
164 "exts. %0,%1"
165 [(set_attr "type" "compare")])
166\f
167;; Fixed-point arithmetic insns.
f357808b 168(define_insn "addsi3"
1fd4e8c1
RK		 169 [(set (match_operand:SI 0 "gen_reg_operand" "=r,r")
170 (plus:SI (match_operand:SI 1 "gen_reg_operand" "%r,b")
171 (match_operand:SI 2 "add_operand" "rI,J")))]
172 ""
173 "@
174 a%I2 %0,%1,%2
175 cau %0,%1,%u2")
176
177(define_insn ""
178 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
179 (compare:CC (plus:SI (match_operand:SI 1 "gen_reg_operand" "r")
180 (match_operand:SI 2 "reg_or_short_operand" "rI"))
181 (const_int 0)))
182 (clobber (match_scratch:SI 3 "=r"))]
183 ""
184 "a%I2. %3,%1,%2"
185 [(set_attr "type" "compare")])
186
187(define_insn ""
188 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
189 (compare:CC (plus:SI (match_operand:SI 1 "gen_reg_operand" "r")
190 (match_operand:SI 2 "reg_or_short_operand" "rI"))
191 (const_int 0)))
192 (set (match_operand:SI 0 "gen_reg_operand" "=r")
193 (plus:SI (match_dup 1) (match_dup 2)))]
194 ""
195 "a%I2. %0,%1,%2"
196 [(set_attr "type" "compare")])
197
f357808b
RK		 198;; Split an add that we can't do in one insn into two insns, each of which
199;; does one 16-bit part. This is used by combine. Note that the low-order
200;; add should be last in case the result gets used in an address.
201
202(define_split
1fd4e8c1
RK		 203 [(set (match_operand:SI 0 "gen_reg_operand" "")
204 (plus:SI (match_operand:SI 1 "gen_reg_operand" "")
f357808b 205 (match_operand:SI 2 "non_add_cint_operand" "")))]
1fd4e8c1 206 ""
f357808b
RK		 207 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))
208 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
209"
1fd4e8c1 210{
f357808b
RK		 211 int low = INTVAL (operands[2]) & 0xffff;
212 int high = (unsigned) INTVAL (operands[2]) >> 16;
1fd4e8c1 213
f357808b
RK		 214 if (low & 0x8000)
215 high++, low |= 0xffff0000;
1fd4e8c1 216
f357808b
RK		 217 operands[3] = gen_rtx (CONST_INT, VOIDmode, high << 16);
218 operands[4] = gen_rtx (CONST_INT, VOIDmode, low);
1fd4e8c1
RK		 219}")
220
221(define_insn "one_cmplsi2"
222 [(set (match_operand:SI 0 "gen_reg_operand" "=r")
223 (not:SI (match_operand:SI 1 "gen_reg_operand" "r")))]
224 ""
225 "sfi %0,%1,-1")
226
227(define_insn ""
228 [(set (match_operand:SI 0 "gen_reg_operand" "=r,r")
229 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "r,I")
230 (match_operand:SI 2 "gen_reg_operand" "r,r")))]
231 ""
232 "@
233 sf %0,%2,%1
234 sfi %0,%2,%1")
235
236(define_insn ""
237 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
238 (compare:CC (minus:SI (match_operand:SI 1 "gen_reg_operand" "r")
239 (match_operand:SI 2 "gen_reg_operand" "r"))
240 (const_int 0)))
241 (clobber (match_scratch:SI 3 "=r"))]
242 ""
243 "sf. %3,%2,%1"
244 [(set_attr "type" "compare")])
245
246(define_insn ""
247 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
248 (compare:CC (minus:SI (match_operand:SI 1 "gen_reg_operand" "r")
249 (match_operand:SI 2 "gen_reg_operand" "r"))
250 (const_int 0)))
251 (set (match_operand:SI 0 "gen_reg_operand" "=r")
252 (minus:SI (match_dup 1) (match_dup 2)))]
253 ""
254 "sf. %0,%2,%1"
255 [(set_attr "type" "compare")])
256
257(define_expand "subsi3"
258 [(set (match_operand:SI 0 "gen_reg_operand" "")
259 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "")
260 (match_operand:SI 2 "reg_or_cint_operand" "")))]
261 ""
262 "
263{
264 if (GET_CODE (operands[2]) == CONST_INT)
265 {
266 emit_insn (gen_addsi3 (operands[0], operands[1],
267 negate_rtx (SImode, operands[2])));
268 DONE;
269 }
1fd4e8c1
RK		 270}")
271
272;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i]
273;; instruction and some auxiliary computations. Then we just have a single
274;; DEFINE_INSN for doz[i].
275
276(define_expand "sminsi3"
277 [(set (match_dup 3)
278 (if_then_else:SI (gt:SI (match_operand:SI 1 "gen_reg_operand" "")
279 (match_operand:SI 2 "reg_or_short_operand" ""))
280 (const_int 0)
281 (minus:SI (match_dup 2) (match_dup 1))))
282 (set (match_operand:SI 0 "gen_reg_operand" "")
283 (minus:SI (match_dup 2) (match_dup 3)))]
284 ""
285 "
286{ operands[3] = gen_reg_rtx (SImode); }")
287
288(define_expand "smaxsi3"
289 [(set (match_dup 3)
290 (if_then_else:SI (gt:SI (match_operand:SI 1 "gen_reg_operand" "")
291 (match_operand:SI 2 "reg_or_short_operand" ""))
292 (const_int 0)
293 (minus:SI (match_dup 2) (match_dup 1))))
294 (set (match_operand:SI 0 "gen_reg_operand" "")
295 (plus:SI (match_dup 3) (match_dup 1)))]
296 ""
297 "
298{ operands[3] = gen_reg_rtx (SImode); }")
299
300(define_expand "uminsi3"
301 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gen_reg_operand" "")
302 (const_int -2147483648)))
303 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gen_reg_operand" "")
304 (const_int -2147483648)))
305 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
306 (const_int 0)
307 (minus:SI (match_dup 4) (match_dup 3))))
308 (set (match_operand:SI 0 "gen_reg_operand" "")
309 (minus:SI (match_dup 2) (match_dup 3)))]
310 ""
311 "
312{ operands[3] = gen_reg_rtx (SImode); operands[4] = gen_reg_rtx (SImode); }")
313
314(define_expand "umaxsi3"
315 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gen_reg_operand" "")
316 (const_int -2147483648)))
317 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gen_reg_operand" "")
318 (const_int -2147483648)))
319 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
320 (const_int 0)
321 (minus:SI (match_dup 4) (match_dup 3))))
322 (set (match_operand:SI 0 "gen_reg_operand" "")
323 (plus:SI (match_dup 3) (match_dup 1)))]
324 ""
325 "
326{ operands[3] = gen_reg_rtx (SImode); operands[4] = gen_reg_rtx (SImode); }")
327
328(define_insn ""
329 [(set (match_operand:SI 0 "gen_reg_operand" "=r")
330 (if_then_else:SI (gt (match_operand:SI 1 "gen_reg_operand" "r")
5c23c401 331 (match_operand:SI 2 "reg_or_short_operand" "rI"))
1fd4e8c1
RK		 332 (const_int 0)
333 (minus:SI (match_dup 2) (match_dup 1))))]
334 ""
335 "doz%I2 %0,%1,%2")
336
337(define_insn ""
338 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
339 (compare:CC
340 (if_then_else:SI (gt (match_operand:SI 1 "gen_reg_operand" "r")
5c23c401 341 (match_operand:SI 2 "reg_or_short_operand" "rI"))
1fd4e8c1
RK		 342 (const_int 0)
343 (minus:SI (match_dup 2) (match_dup 1)))
344 (const_int 0)))
345 (clobber (match_scratch:SI 3 "=r"))]
346 ""
347 "doz%I2. %3,%1,%2"
348 [(set_attr "type" "delayed_compare")])
349
350(define_insn ""
351 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
352 (compare:CC
353 (if_then_else:SI (gt (match_operand:SI 1 "gen_reg_operand" "r")
5c23c401 354 (match_operand:SI 2 "reg_or_short_operand" "rI"))
1fd4e8c1
RK		 355 (const_int 0)
356 (minus:SI (match_dup 2) (match_dup 1)))
357 (const_int 0)))
358 (set (match_operand:SI 0 "gen_reg_operand" "=r")
359 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
360 (const_int 0)
361 (minus:SI (match_dup 2) (match_dup 1))))]
362 ""
363 "doz%I2. %0,%1,%2"
364 [(set_attr "type" "delayed_compare")])
365
366;; We don't need abs with condition code because such comparisons should
367;; never be done.
368(define_insn "abssi2"
369 [(set (match_operand:SI 0 "gen_reg_operand" "=r")
370 (abs:SI (match_operand:SI 1 "gen_reg_operand" "r")))]
371 ""
372 "abs %0,%1")
373
374(define_insn ""
375 [(set (match_operand:SI 0 "gen_reg_operand" "=r")
376 (neg:SI (abs:SI (match_operand:SI 1 "gen_reg_operand" "r"))))]
377 ""
378 "nabs %0,%1")
379
380(define_insn "negsi2"
381 [(set (match_operand:SI 0 "gen_reg_operand" "=r")
382 (neg:SI (match_operand:SI 1 "gen_reg_operand" "r")))]
383 ""
384 "neg %0,%1")
385
386(define_insn ""
387 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
388 (compare:CC (neg:SI (match_operand:SI 1 "gen_reg_operand" "r"))
389 (const_int 0)))
390 (clobber (match_scratch:SI 2 "=r"))]
391 ""
392 "neg. %2,%1"
393 [(set_attr "type" "compare")])
394
395(define_insn ""
396 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
397 (compare:CC (neg:SI (match_operand:SI 1 "gen_reg_operand" "r"))
398 (const_int 0)))
399 (set (match_operand:SI 0 "gen_reg_operand" "=r")
400 (neg:SI (match_dup 1)))]
401 ""
402 "neg. %0,%1"
403 [(set_attr "type" "compare")])
404
405(define_insn "ffssi2"
406 [(set (match_operand:SI 0 "register_operand" "=&r")
407 (ffs:SI (match_operand:SI 1 "register_operand" "r")))]
408 ""
409 "neg %0,%1\;and %0,%0,%1\;cntlz %0,%0\;sfi %0,%0,32")
410
411;; There is no need for (set (condition) (compare (ffs) 0)) because that
412;; can be simplified to an ordinary comparison. A parallel set and compare
413;; might be used, so include it.
414
415(define_insn ""
416 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
417 (compare:CC (ffs:SI (match_operand:SI 1 "register_operand" "r"))
418 (const_int 0)))
419 (set (match_operand:SI 0 "register_operand" "=&r")
420 (ffs:SI (match_dup 1)))]
421 ""
422 "neg %0,%1\;and %0,%0,%1\;cntlz %0,%0\;sfi. %0,%0,32"
423 [(set_attr "type" "compare")])
424
425(define_insn "mulsi3"
426 [(set (match_operand:SI 0 "gen_reg_operand" "=r,r")
427 (mult:SI (match_operand:SI 1 "gen_reg_operand" "%r,r")
428 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
429 (clobber (match_scratch:SI 3 "=q,q"))]
430 ""
431 "@
432 muls %0,%1,%2
433 muli %0,%1,%2")
434
435(define_insn ""
436 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
437 (compare:CC (mult:SI (match_operand:SI 1 "gen_reg_operand" "r")
438 (match_operand:SI 2 "gen_reg_operand" "r"))
439 (const_int 0)))
440 (clobber (match_scratch:SI 3 "=r"))
441 (clobber (match_scratch:SI 4 "=q"))]
442 ""
443 "muls. %3,%1,%2"
444 [(set_attr "type" "delayed_compare")])
445
446(define_insn ""
447 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
448 (compare:CC (mult:SI (match_operand:SI 1 "gen_reg_operand" "r")
449 (match_operand:SI 2 "gen_reg_operand" "r"))
450 (const_int 0)))
451 (set (match_operand:SI 0 "gen_reg_operand" "=r")
452 (mult:SI (match_dup 1) (match_dup 2)))
453 (clobber (match_scratch:SI 4 "=q"))]
454 ""
455 "muls. %0,%1,%2"
456 [(set_attr "type" "delayed_compare")])
457
458;; Operand 1 is divided by operand 2; quotient goes to operand
459;; 0 and remainder to operand 3.
460;; ??? At some point, see what, if anything, we can do about if (x % y == 0).
461
462(define_insn "divmodsi4"
463 [(set (match_operand:SI 0 "gen_reg_operand" "=r")
464 (div:SI (match_operand:SI 1 "gen_reg_operand" "r")
465 (match_operand:SI 2 "gen_reg_operand" "r")))
466 (set (match_operand:SI 3 "gen_reg_operand" "=q")
467 (mod:SI (match_dup 1) (match_dup 2)))]
468 ""
469 "divs %0,%1,%2")
470
471;; For powers of two we can do srai/aze for divide and then adjust for
472;; modulus. If it isn't a power of two, FAIL so divmodsi4 will be used.
473(define_expand "divsi3"
474 [(set (match_operand:SI 0 "gen_reg_operand" "")
475 (div:SI (match_operand:SI 1 "gen_reg_operand" "")
476 (match_operand:SI 2 "reg_or_cint_operand" "")))]
477 ""
478 "
479{
480 if (GET_CODE (operands[2]) != CONST_INT
481 || exact_log2 (INTVAL (operands[2])) < 0)
482 FAIL;
483}")
484
485(define_expand "modsi3"
486 [(set (match_dup 3)
487 (div:SI (match_operand:SI 1 "gen_reg_operand" "")
488 (match_operand:SI 2 "reg_or_cint_operand" "")))
489 (parallel [(set (match_dup 4) (ashift:SI (match_dup 3) (match_dup 5)))
490 (clobber (scratch:SI))])
491 (set (match_operand:SI 0 "gen_reg_operand" "")
492 (minus:SI (match_dup 1) (match_dup 4)))]
493 ""
494 "
495{
496 int i = exact_log2 (INTVAL (operands[2]));
497
498 if (GET_CODE (operands[2]) != CONST_INT || i < 0)
499 FAIL;
500
501 operands[3] = gen_reg_rtx (SImode);
502 operands[4] = gen_reg_rtx (SImode);
503 operands[5] = gen_rtx (CONST_INT, VOIDmode, i);
504}")
505
506(define_insn ""
507 [(set (match_operand:SI 0 "gen_reg_operand" "=r")
508 (div:SI (match_operand:SI 1 "gen_reg_operand" "r")
509 (match_operand:SI 2 "const_int_operand" "N")))]
510 "exact_log2 (INTVAL (operands[2])) >= 0"
511 "srai %0,%1,%p2\;aze %0,%0")
512
513(define_insn ""
514 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
515 (div:SI (match_operand:SI 1 "gen_reg_operand" "r")
516 (match_operand:SI 2 "const_int_operand" "N")))
517 (clobber (match_scratch:SI 3 "=r"))]
518 "exact_log2 (INTVAL (operands[2])) >= 0"
519 "srai %3,%1,%p2\;aze. %3,%3"
520 [(set_attr "type" "compare")])
521
522(define_insn ""
523 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
524 (div:SI (match_operand:SI 1 "gen_reg_operand" "r")
525 (match_operand:SI 2 "const_int_operand" "N")))
526 (set (match_operand:SI 0 "gen_reg_operand" "=r")
527 (div:SI (match_dup 1) (match_dup 2)))]
528 "exact_log2 (INTVAL (operands[2])) >= 0"
529 "srai %0,%1,%p2\;aze. %0,%0"
530 [(set_attr "type" "compare")])
531
532(define_insn ""
533 [(set (match_operand:SI 0 "gen_reg_operand" "=r")
534 (udiv:SI
535 (plus:DI (lshift:DI
536 (zero_extend:DI (match_operand:SI 1 "gen_reg_operand" "r"))
537 (const_int 32))
538 (zero_extend:DI (match_operand:SI 2 "register_operand" "*q")))
539 (match_operand:SI 3 "gen_reg_operand" "r")))
540 (set (match_operand:SI 4 "register_operand" "=*q")
541 (umod:SI
542 (plus:DI (lshift:DI
543 (zero_extend:DI (match_dup 1)) (const_int 32))
544 (zero_extend:DI (match_dup 2)))
545 (match_dup 3)))]
546
547 ""
548 "div %0,%1,%3")
549
550;; To do unsigned divide we handle the cases of the divisor looking like a
551;; negative number. If it is a constant that is less than 2**31, we don't
552;; have to worry about the branches. So make a few subroutines here.
553;;
554;; First comes the normal case.
555(define_expand "udivmodsi4_normal"
556 [(set (match_dup 4) (const_int 0))
557 (parallel [(set (match_operand:SI 0 "" "")
558 (udiv:SI (plus:DI (lshift:DI (zero_extend:DI (match_dup 4))
559 (const_int 32))
560 (zero_extend:DI (match_operand:SI 1 "" "")))
561 (match_operand:SI 2 "" "")))
562 (set (match_operand:SI 3 "" "")
563 (umod:SI (plus:DI (lshift:DI (zero_extend:DI (match_dup 4))
564 (const_int 32))
565 (zero_extend:DI (match_dup 1)))
566 (match_dup 2)))])]
567 ""
568 "
569{ operands[4] = gen_reg_rtx (SImode); }")
570
571;; This handles the branches.
572(define_expand "udivmodsi4_tests"
573 [(set (match_operand:SI 0 "" "") (const_int 0))
574 (set (match_operand:SI 3 "" "") (match_operand:SI 1 "" ""))
575 (set (match_dup 5) (compare:CCUNS (match_dup 1) (match_operand:SI 2 "" "")))
576 (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0))
577 (label_ref (match_operand:SI 4 "" "")) (pc)))
578 (set (match_dup 0) (const_int 1))
579 (set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2)))
580 (set (match_dup 6) (compare:CC (match_dup 2) (const_int 0)))
581 (set (pc) (if_then_else (lt (match_dup 6) (const_int 0))
582 (label_ref (match_dup 4)) (pc)))]
583 ""
584 "
585{ operands[5] = gen_reg_rtx (CCUNSmode);
586 operands[6] = gen_reg_rtx (CCmode);
587}")
588
589(define_expand "udivmodsi4"
590 [(parallel [(set (match_operand:SI 0 "gen_reg_operand" "")
591 (udiv:SI (match_operand:SI 1 "gen_reg_operand" "")
592 (match_operand:SI 2 "reg_or_cint_operand" "")))
593 (set (match_operand:SI 3 "gen_reg_operand" "")
594 (umod:SI (match_dup 1) (match_dup 2)))])]
595 ""
596 "
597{
598 rtx label = 0;
599
600 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) < 0)
601 {
602 operands[2] = force_reg (SImode, operands[2]);
603 label = gen_label_rtx ();
604 emit (gen_udivmodsi4_tests (operands[0], operands[1], operands[2],
605 operands[3], label));
606 }
607 else
608 operands[2] = force_reg (SImode, operands[2]);
609
610 emit (gen_udivmodsi4_normal (operands[0], operands[1], operands[2],
611 operands[3]));
612 if (label)
613 emit_label (label);
614
615 DONE;
616}")
617
618(define_insn "andsi3"
619 [(set (match_operand:SI 0 "gen_reg_operand" "=r,r,r,r")
620 (and:SI (match_operand:SI 1 "gen_reg_operand" "%r,r,r,r")
621 (match_operand:SI 2 "and_operand" "?r,L,K,J")))
622 (clobber (match_scratch:CC 3 "=X,X,x,x"))]
623 ""
624 "@
625 and %0,%1,%2
626 rlinm %0,%1,0,%m2,%M2
627 andil. %0,%1,%b2
628 andiu. %0,%1,%u2")
629
630(define_insn ""
631 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x")
632 (compare:CC (and:SI (match_operand:SI 1 "gen_reg_operand" "%r,r,r,r")
633 (match_operand:SI 2 "and_operand" "r,K,J,L"))
634 (const_int 0)))
635 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
636 ""
637 "@
638 and. %3,%1,%2
639 andil. %3,%1,%b2
640 andiu. %3,%1,%u2
641 rlinm. %3,%1,0,%m2,%M2"
642 [(set_attr "type" "compare,compare,compare,delayed_compare")])
643
644(define_insn ""
645 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x")
646 (compare:CC (and:SI (match_operand:SI 1 "gen_reg_operand" "%r,r,r,r")
647 (match_operand:SI 2 "and_operand" "r,K,J,L"))
648 (const_int 0)))
649 (set (match_operand:SI 0 "gen_reg_operand" "=r,r,r,r")
650 (and:SI (match_dup 1) (match_dup 2)))]
651 ""
652 "@
653 and. %0,%1,%2
654 andil. %0,%1,%b2
655 andiu. %0,%1,%u2
656 rlinm. %0,%1,0,%m2,%M2"
657 [(set_attr "type" "compare,compare,compare,delayed_compare")])
658
f357808b
RK		 659;; Take a AND with a constant that cannot be done in a single insn and try to
660;; split it into two insns. This does not verify that the insns are valid
661;; since this need not be done as combine will do it.
662
663(define_split
664 [(set (match_operand:SI 0 "gen_reg_operand" "")
665 (and:SI (match_operand:SI 1 "gen_reg_operand" "")
666 (match_operand:SI 2 "non_and_cint_operand" "")))]
667 ""
668 [(set (match_dup 0) (and:SI (match_dup 1) (match_dup 3)))
669 (set (match_dup 0) (and:SI (match_dup 0) (match_dup 4)))]
670 "
671{
672 int maskval = INTVAL (operands[2]);
673 int i, transitions, last_bit_value;
674 int orig = maskval, first_c = maskval, second_c;
675
676 /* We know that MASKVAL must have more than 2 bit-transitions. Start at
677 the low-order bit and count for the third transition. When we get there,
678 make a first mask that has everything to the left of that position
679 a one. Then make the second mask to turn off whatever else is needed. */
680
681 for (i = 1, transitions = 0, last_bit_value = maskval & 1; i < 32; i++)
682 {
683 if (((maskval >>= 1) & 1) != last_bit_value)
684 last_bit_value ^= 1, transitions++;
685
686 if (transitions > 2)
687 {
688 first_c |= (~0) << i;
689 break;
690 }
691 }
692
693 second_c = orig | ~ first_c;
694
695 operands[3] = gen_rtx (CONST_INT, VOIDmode, first_c);
696 operands[4] = gen_rtx (CONST_INT, VOIDmode, second_c);
697}")
698
699(define_insn "iorsi3"
1fd4e8c1
RK		 700 [(set (match_operand:SI 0 "gen_reg_operand" "=r,r,r")
701 (ior:SI (match_operand:SI 1 "gen_reg_operand" "%r,r,r")
702 (match_operand:SI 2 "logical_operand" "r,K,J")))]
703 ""
704 "@
705 or %0,%1,%2
706 oril %0,%1,%b2
707 oriu %0,%1,%u2")
708
709(define_insn ""
710 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
711 (compare:CC (ior:SI (match_operand:SI 1 "gen_reg_operand" "r")
712 (match_operand:SI 2 "gen_reg_operand" "r"))
713 (const_int 0)))
714 (clobber (match_scratch:SI 3 "=r"))]
715 ""
716 "or. %3,%1,%2"
717 [(set_attr "type" "compare")])
718
719(define_insn ""
720 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
721 (compare:CC (ior:SI (match_operand:SI 1 "gen_reg_operand" "r")
722 (match_operand:SI 2 "gen_reg_operand" "r"))
723 (const_int 0)))
724 (set (match_operand:SI 0 "gen_reg_operand" "=r")
725 (ior:SI (match_dup 1) (match_dup 2)))]
726 ""
727 "or. %0,%1,%2"
728 [(set_attr "type" "compare")])
729
f357808b
RK		 730;; Split an IOR that we can't do in one insn into two insns, each of which
731;; does one 16-bit part. This is used by combine.
732
733(define_split
1fd4e8c1
RK		 734 [(set (match_operand:SI 0 "gen_reg_operand" "")
735 (ior:SI (match_operand:SI 1 "gen_reg_operand" "")
f357808b 736 (match_operand:SI 2 "non_logical_cint_operand" "")))]
1fd4e8c1 737 ""
f357808b
RK		 738 [(set (match_dup 0) (ior:SI (match_dup 1) (match_dup 3)))
739 (set (match_dup 0) (ior:SI (match_dup 0) (match_dup 4)))]
740"
1fd4e8c1 741{
f357808b
RK		 742 operands[3] = gen_rtx (CONST_INT, VOIDmode,
743 INTVAL (operands[2]) & 0xffff0000);
744 operands[4] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) & 0xffff);
1fd4e8c1
RK		 745}")
746
f357808b 747(define_insn "xorsi3"
1fd4e8c1
RK		 748 [(set (match_operand:SI 0 "gen_reg_operand" "=r,r,r")
749 (xor:SI (match_operand:SI 1 "gen_reg_operand" "%r,r,r")
750 (match_operand:SI 2 "logical_operand" "r,K,J")))]
751 ""
752 "@
753 xor %0,%1,%2
754 xoril %0,%1,%b2
755 xoriu %0,%1,%u2")
756
757(define_insn ""
758 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
759 (compare:CC (xor:SI (match_operand:SI 1 "gen_reg_operand" "r")
760 (match_operand:SI 2 "gen_reg_operand" "r"))
761 (const_int 0)))
762 (clobber (match_scratch:SI 3 "=r"))]
763 ""
764 "xor. %3,%1,%2"
765 [(set_attr "type" "compare")])
766
767(define_insn ""
768 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
769 (compare:CC (xor:SI (match_operand:SI 1 "gen_reg_operand" "r")
770 (match_operand:SI 2 "gen_reg_operand" "r"))
771 (const_int 0)))
772 (set (match_operand:SI 0 "gen_reg_operand" "=r")
773 (xor:SI (match_dup 1) (match_dup 2)))]
774 ""
775 "xor. %0,%1,%2"
776 [(set_attr "type" "compare")])
777
f357808b
RK		 778;; Split an XOR that we can't do in one insn into two insns, each of which
779;; does one 16-bit part. This is used by combine.
780
781(define_split
1fd4e8c1
RK		 782 [(set (match_operand:SI 0 "gen_reg_operand" "")
783 (xor:SI (match_operand:SI 1 "gen_reg_operand" "")
f357808b 784 (match_operand:SI 2 "non_logical_cint_operand" "")))]
1fd4e8c1 785 ""
f357808b
RK		 786 [(set (match_dup 0) (xor:SI (match_dup 1) (match_dup 3)))
787 (set (match_dup 0) (xor:SI (match_dup 0) (match_dup 4)))]
788"
1fd4e8c1 789{
f357808b
RK		 790 operands[3] = gen_rtx (CONST_INT, VOIDmode,
791 INTVAL (operands[2]) & 0xffff0000);
792 operands[4] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) & 0xffff);
1fd4e8c1
RK		 793}")
794
795(define_insn ""
796 [(set (match_operand:SI 0 "gen_reg_operand" "=r")
797 (not:SI (xor:SI (match_operand:SI 1 "gen_reg_operand" "%r")
798 (match_operand:SI 2 "gen_reg_operand" "r"))))]
799 ""
800 "eqv %0,%1,%2")
801
802(define_insn ""
803 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
804 (compare:CC (not:SI (xor:SI (match_operand:SI 1 "gen_reg_operand" "%r")
805 (match_operand:SI 2 "gen_reg_operand" "r")))
806 (const_int 0)))
807 (clobber (match_scratch:SI 3 "=r"))]
808 ""
809 "eqv. %3,%1,%2"
810 [(set_attr "type" "compare")])
811
812(define_insn ""
813 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
814 (compare:CC (not:SI (xor:SI (match_operand:SI 1 "gen_reg_operand" "%r")
815 (match_operand:SI 2 "gen_reg_operand" "r")))
816 (const_int 0)))
817 (set (match_operand:SI 0 "gen_reg_operand" "=r")
818 (not:SI (xor:SI (match_dup 1) (match_dup 2))))]
819 ""
820 "eqv. %0,%1,%2"
821 [(set_attr "type" "compare")])
822
823(define_insn ""
824 [(set (match_operand:SI 0 "gen_reg_operand" "=r")
825 (and:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
826 (match_operand:SI 2 "gen_reg_operand" "r")))]
827 ""
828 "andc %0,%2,%1")
829
830(define_insn ""
831 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
832 (compare:CC (and:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
833 (match_operand:SI 2 "gen_reg_operand" "r"))
834 (const_int 0)))
835 (clobber (match_scratch:SI 3 "=r"))]
836 ""
837 "andc. %3,%2,%1"
838 [(set_attr "type" "compare")])
839
840(define_insn ""
841 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
842 (compare:CC (and:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
843 (match_operand:SI 2 "gen_reg_operand" "r"))
844 (const_int 0)))
845 (set (match_operand:SI 0 "gen_reg_operand" "=r")
846 (and:SI (not:SI (match_dup 1)) (match_dup 2)))]
847 ""
848 "andc. %0,%2,%1"
849 [(set_attr "type" "compare")])
850
851(define_insn ""
852 [(set (match_operand:SI 0 "gen_reg_operand" "=r")
853 (ior:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
854 (match_operand:SI 2 "gen_reg_operand" "r")))]
855 ""
856 "orc %0,%2,%1")
857
858(define_insn ""
859 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
860 (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
861 (match_operand:SI 2 "gen_reg_operand" "r"))
862 (const_int 0)))
863 (clobber (match_scratch:SI 3 "=r"))]
864 ""
865 "orc. %3,%2,%1"
866 [(set_attr "type" "compare")])
867
868(define_insn ""
869 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
870 (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
871 (match_operand:SI 2 "gen_reg_operand" "r"))
872 (const_int 0)))
873 (set (match_operand:SI 0 "gen_reg_operand" "=r")
874 (ior:SI (not:SI (match_dup 1)) (match_dup 2)))]
875 ""
876 "orc. %0,%2,%1"
877 [(set_attr "type" "compare")])
878
879(define_insn ""
880 [(set (match_operand:SI 0 "gen_reg_operand" "=r")
881 (ior:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
882 (not:SI (match_operand:SI 2 "gen_reg_operand" "r"))))]
883 ""
884 "nand %0,%1,%2")
885
886(define_insn ""
887 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
888 (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
889 (not:SI (match_operand:SI 2 "gen_reg_operand" "r")))
890 (const_int 0)))
891 (clobber (match_scratch:SI 3 "=r"))]
892 ""
893 "nand. %3,%1,%2"
894 [(set_attr "type" "compare")])
895
896(define_insn ""
897 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
898 (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
899 (not:SI (match_operand:SI 2 "gen_reg_operand" "r")))
900 (const_int 0)))
901 (set (match_operand:SI 0 "gen_reg_operand" "=r")
902 (ior:SI (not:SI (match_dup 1)) (not:SI (match_dup 2))))]
903 ""
904 "nand. %0,%1,%2"
905 [(set_attr "type" "compare")])
906
907(define_insn ""
908 [(set (match_operand:SI 0 "gen_reg_operand" "=r")
909 (and:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
910 (not:SI (match_operand:SI 2 "gen_reg_operand" "r"))))]
911 ""
912 "nor %0,%1,%2")
913
914(define_insn ""
915 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
916 (compare:CC (and:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
917 (not:SI (match_operand:SI 2 "gen_reg_operand" "r")))
918 (const_int 0)))
919 (clobber (match_scratch:SI 3 "=r"))]
920 ""
921 "nor. %3,%1,%2"
922 [(set_attr "type" "compare")])
923
924(define_insn ""
925 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
926 (compare:CC (and:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
927 (not:SI (match_operand:SI 2 "gen_reg_operand" "r")))
928 (const_int 0)))
929 (set (match_operand:SI 0 "gen_reg_operand" "=r")
930 (and:SI (not:SI (match_dup 1)) (not:SI (match_dup 2))))]
931 ""
932 "nor. %0,%1,%2"
933 [(set_attr "type" "compare")])
934
935;; maskir insn. We need four forms because things might be in arbitrary
936;; orders. Don't define forms that only set CR fields because these
937;; would modify an input register.
938
939(define_insn ""
940 [(set (match_operand:SI 0 "gen_reg_operand" "=r")
941 (ior:SI (and:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
942 (match_operand:SI 2 "gen_reg_operand" "0"))
943 (and:SI (match_dup 1)
944 (match_operand:SI 3 "gen_reg_operand" "r"))))]
945 ""
946 "maskir %0,%3,%1")
947
948(define_insn ""
949 [(set (match_operand:SI 0 "register_operand" "=r")
950 (ior:SI (and:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
951 (match_operand:SI 2 "gen_reg_operand" "0"))
952 (and:SI (match_operand:SI 3 "gen_reg_operand" "r")
953 (match_dup 1))))]
954 ""
955 "maskir %0,%3,%1")
956
957(define_insn ""
958 [(set (match_operand:SI 0 "gen_reg_operand" "=r")
959 (ior:SI (and:SI (match_dup 1)
960 (match_operand:SI 3 "gen_reg_operand" "r"))
961 (and:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
962 (match_operand:SI 2 "gen_reg_operand" "0"))))]
963 ""
964 "maskir %0,%3,%1")
965
966(define_insn ""
967 [(set (match_operand:SI 0 "gen_reg_operand" "=r")
968 (ior:SI (and:SI (match_operand:SI 3 "gen_reg_operand" "r")
969 (match_dup 1))
970 (and:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
971 (match_operand:SI 2 "gen_reg_operand" "0"))))]
972 ""
973 "maskir %0,%3,%1")
974
975(define_insn ""
976 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
977 (compare:CC
978 (ior:SI (and:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
979 (match_operand:SI 2 "gen_reg_operand" "0"))
980 (and:SI (match_dup 1)
981 (match_operand:SI 3 "gen_reg_operand" "r")))
982 (const_int 0)))
983 (set (match_operand:SI 0 "gen_reg_operand" "=r")
984 (ior:SI (and:SI (not:SI (match_dup 1)) (match_dup 2))
985 (and:SI (match_dup 1) (match_dup 3))))]
986 ""
987 "maskir. %0,%3,%1"
988 [(set_attr "type" "compare")])
989
990(define_insn ""
991 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
992 (compare:CC
993 (ior:SI (and:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
994 (match_operand:SI 2 "gen_reg_operand" "0"))
995 (and:SI (match_operand:SI 3 "gen_reg_operand" "r")
996 (match_dup 1)))
997 (const_int 0)))
998 (set (match_operand:SI 0 "register_operand" "=r")
999 (ior:SI (and:SI (not:SI (match_dup 1)) (match_dup 2))
1000 (and:SI (match_dup 3) (match_dup 1))))]
1001 ""
1002 "maskir. %0,%3,%1"
1003 [(set_attr "type" "compare")])
1004
1005(define_insn ""
1006 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
1007 (compare:CC
1008 (ior:SI (and:SI (match_dup 1)
1009 (match_operand:SI 3 "gen_reg_operand" "r"))
1010 (and:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
1011 (match_operand:SI 2 "gen_reg_operand" "0")))
1012 (const_int 0)))
1013 (set (match_operand:SI 0 "gen_reg_operand" "=r")
1014 (ior:SI (and:SI (match_dup 1) (match_dup 3))
1015 (and:SI (not:SI (match_dup 1)) (match_dup 2))))]
1016 ""
1017 "maskir. %0,%3,%1"
1018 [(set_attr "type" "compare")])
1019
1020(define_insn ""
1021 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
1022 (compare:CC
1023 (ior:SI (and:SI (match_operand:SI 3 "gen_reg_operand" "r")
1024 (match_dup 1))
1025 (and:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
1026 (match_operand:SI 2 "gen_reg_operand" "0")))
1027 (const_int 0)))
1028 (set (match_operand:SI 0 "gen_reg_operand" "=r")
1029 (ior:SI (and:SI (match_dup 3) (match_dup 1))
1030 (and:SI (not:SI (match_dup 1)) (match_dup 2))))]
1031 ""
1032 "maskir. %0,%3,%1"
1033 [(set_attr "type" "compare")])
1034\f
1035;; Rotate and shift insns, in all their variants. These support shifts,
1036;; field inserts and extracts, and various combinations thereof.
1037(define_insn "insv"
1038 [(set (zero_extract:SI (match_operand:SI 0 "gen_reg_operand" "+r")
1039 (match_operand:SI 1 "const_int_operand" "i")
1040 (match_operand:SI 2 "const_int_operand" "i"))
1041 (match_operand:SI 3 "gen_reg_operand" "r"))]
1042 ""
1043 "*
1044{
1045 int start = INTVAL (operands[2]) & 31;
1046 int size = INTVAL (operands[1]) & 31;
1047
1048 operands[4] = gen_rtx (CONST_INT, VOIDmode, 32 - start - size);
1049 operands[1] = gen_rtx (CONST_INT, VOIDmode, start + size - 1);
1050 return \"rlimi %0,%3,%4,%h2,%h1\";
1051}")
1052
1053(define_insn "extzv"
1054 [(set (match_operand:SI 0 "gen_reg_operand" "=r")
1055 (zero_extract:SI (match_operand:SI 1 "gen_reg_operand" "r")
1056 (match_operand:SI 2 "const_int_operand" "i")
1057 (match_operand:SI 3 "const_int_operand" "i")))]
1058 ""
1059 "*
1060{
1061 int start = INTVAL (operands[3]) & 31;
1062 int size = INTVAL (operands[2]) & 31;
1063
cd0ec0d1
RK		 1064 if ((start < 16 && start + size <= 16) || start >= 16)
1065 {
1066 operands[3] = gen_rtx (CONST_INT, VOIDmode,
1067 ((1 << (16 - (start & 15)))
1068 - (1 << (16 - (start & 15) - size))));
1069 if (start < 16)
1070 return \"andiu. %4,%1,%3\";
1071 else
1072 return \"andil. %4,%1,%3\";
1073 }
1074
1fd4e8c1
RK		 1075 if (start + size >= 32)
1076 operands[3] = const0_rtx;
1077 else
1078 operands[3] = gen_rtx (CONST_INT, VOIDmode, start + size);
1079 return \"rlinm %0,%1,%3,%s2,31\";
1080}")
1081
1082(define_insn ""
1083 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1084 (compare:CC (zero_extract:SI (match_operand:SI 1 "gen_reg_operand" "r")
1085 (match_operand:SI 2 "const_int_operand" "i")
1086 (match_operand:SI 3 "const_int_operand" "i"))
1087 (const_int 0)))
1088 (clobber (match_scratch:SI 4 "=r"))]
1089 ""
1090 "*
1091{
1092 int start = INTVAL (operands[3]) & 31;
1093 int size = INTVAL (operands[2]) & 31;
1094
1095 if (start + size >= 32)
1096 operands[3] = const0_rtx;
1097 else
1098 operands[3] = gen_rtx (CONST_INT, VOIDmode, start + size);
1099 return \"rlinm. %4,%1,%3,%s2,31\";
1100}"
1101 [(set_attr "type" "compare")])
1102
1103(define_insn ""
1104 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
1105 (compare:CC (zero_extract:SI (match_operand:SI 1 "gen_reg_operand" "r")
1106 (match_operand:SI 2 "const_int_operand" "i")
1107 (match_operand:SI 3 "const_int_operand" "i"))
1108 (const_int 0)))
1109 (set (match_operand:SI 0 "gen_reg_operand" "=r")
1110 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
1111 ""
1112 "*
1113{
1114 int start = INTVAL (operands[3]) & 31;
1115 int size = INTVAL (operands[2]) & 31;
1116
1117 if (start + size >= 32)
1118 operands[3] = const0_rtx;
1119 else
1120 operands[3] = gen_rtx (CONST_INT, VOIDmode, start + size);
1121 return \"rlinm. %0,%1,%3,%s2,31\";
1122}"
1123 [(set_attr "type" "delayed_compare")])
1124
1125(define_insn "rotlsi3"
1126 [(set (match_operand:SI 0 "gen_reg_operand" "=r")
1127 (rotate:SI (match_operand:SI 1 "gen_reg_operand" "r")
1128 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
1129 ""
1130 "rl%I2nm %0,%1,%h2,0,31")
1131
1132(define_insn ""
1133 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1134 (compare:CC (rotate:SI (match_operand:SI 1 "gen_reg_operand" "r")
1135 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
1136 (const_int 0)))
1137 (clobber (match_scratch:SI 3 "=r"))]
1138 ""
1139 "rl%I2nm. %3,%1,%h2,0,31"
1140 [(set_attr "type" "delayed_compare")])
1141
1142(define_insn ""
1143 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1144 (compare:CC (rotate:SI (match_operand:SI 1 "gen_reg_operand" "r")
1145 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
1146 (const_int 0)))
1147 (set (match_operand:SI 0 "gen_reg_operand" "=r")
1148 (rotate:SI (match_dup 1) (match_dup 2)))]
1149 ""
1150 "rl%I2nm. %0,%1,%h2,0,31"
1151 [(set_attr "type" "delayed_compare")])
1152
1153(define_insn ""
1154 [(set (match_operand:SI 0 "gen_reg_operand" "=r")
1155 (and:SI (rotate:SI (match_operand:SI 1 "gen_reg_operand" "r")
1156 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
1157 (match_operand:SI 3 "mask_operand" "L")))]
1158 ""
1159 "rl%I2nm %0,%1,%h2,%m3,%M3")
1160
1161(define_insn ""
1162 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1163 (compare:CC (and:SI
1164 (rotate:SI (match_operand:SI 1 "gen_reg_operand" "r")
1165 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
1166 (match_operand:SI 3 "mask_operand" "L"))
1167 (const_int 0)))
1168 (clobber (match_scratch:SI 4 "=r"))]
1169 ""
1170 "rl%I2nm. %4,%1,%h2,%m3,%M3"
1171 [(set_attr "type" "delayed_compare")])
1172
1173(define_insn ""
1174 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
1175 (compare:CC (and:SI
1176 (rotate:SI (match_operand:SI 1 "gen_reg_operand" "r")
1177 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
1178 (match_operand:SI 3 "mask_operand" "L"))
1179 (const_int 0)))
1180 (set (match_operand:SI 0 "gen_reg_operand" "=r")
1181 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
1182 ""
1183 "rl%I2nm. %0,%1,%h2,%m3,%M3"
1184 [(set_attr "type" "delayed_compare")])
1185
1186(define_insn ""
1187 [(set (match_operand:SI 0 "gen_reg_operand" "=r")
1188 (zero_extend:SI
1189 (subreg:QI
1190 (rotate:SI (match_operand:SI 1 "gen_reg_operand" "r")
1191 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
1192 ""
1193 "rl%I2nm %0,%1,%h2,24,31")
1194
1195(define_insn ""
1196 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1197 (compare:CC (zero_extend:SI
1198 (subreg:QI
1199 (rotate:SI (match_operand:SI 1 "gen_reg_operand" "r")
1200 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0))
1201 (const_int 0)))
1202 (clobber (match_scratch:SI 3 "=r"))]
1203 ""
1204 "rl%I2nm. %3,%1,%h2,24,31"
1205 [(set_attr "type" "delayed_compare")])
1206
1207(define_insn ""
1208 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1209 (compare:CC (zero_extend:SI
1210 (subreg:QI
1211 (rotate:SI (match_operand:SI 1 "gen_reg_operand" "r")
1212 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0))
1213 (const_int 0)))
1214 (set (match_operand:SI 0 "gen_reg_operand" "=r")
1215 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
1216 ""
1217 "rl%I2nm. %0,%1,%h2,24,31"
1218 [(set_attr "type" "delayed_compare")])
1219
1220(define_insn ""
1221 [(set (match_operand:SI 0 "gen_reg_operand" "=r")
1222 (zero_extend:SI
1223 (subreg:HI
1224 (rotate:SI (match_operand:SI 1 "gen_reg_operand" "r")
1225 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
1226 ""
1227 "rl%I2nm %0,%1,%h2,16,31")
1228
1229(define_insn ""
1230 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1231 (compare:CC (zero_extend:SI
1232 (subreg:HI
1233 (rotate:SI (match_operand:SI 1 "gen_reg_operand" "r")
1234 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0))
1235 (const_int 0)))
1236 (clobber (match_scratch:SI 3 "=r"))]
1237 ""
1238 "rl%I2nm. %3,%1,%h2,16,31"
1239 [(set_attr "type" "delayed_compare")])
1240
1241(define_insn ""
1242 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1243 (compare:CC (zero_extend:SI
1244 (subreg:HI
1245 (rotate:SI (match_operand:SI 1 "gen_reg_operand" "r")
1246 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0))
1247 (const_int 0)))
1248 (set (match_operand:SI 0 "gen_reg_operand" "=r")
1249 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
1250 ""
1251 "rl%I2nm. %0,%1,%h2,16,31"
1252 [(set_attr "type" "delayed_compare")])
1253
1254;; Note that we use "sle." instead of "sl." so that we can set
1255;; SHIFT_COUNT_TRUNCATED.
1256
1257(define_insn "ashlsi3"
1258 [(set (match_operand:SI 0 "gen_reg_operand" "=r,r")
1259 (ashift:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
1260 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
1261 (clobber (match_scratch:SI 3 "=q,X"))]
1262 ""
1263 "@
1264 sle %0,%1,%2
1265 sli %0,%1,%h2")
1266
1267(define_insn ""
1268 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
1269 (compare:CC (ashift:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
1270 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
1271 (const_int 0)))
1272 (clobber (match_scratch:SI 3 "=r,r"))
1273 (clobber (match_scratch:SI 4 "=q,X"))]
1274 ""
1275 "@
1276 sle. %3,%1,%2
1277 sli. %3,%1,%h2"
1278 [(set_attr "type" "delayed_compare")])
1279
1280(define_insn ""
1281 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x")
1282 (compare:CC (ashift:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
1283 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
1284 (const_int 0)))
1285 (set (match_operand:SI 0 "gen_reg_operand" "=r,r")
1286 (ashift:SI (match_dup 1) (match_dup 2)))
1287 (clobber (match_scratch:SI 4 "=q,X"))]
1288 ""
1289 "@
1290 sle. %0,%1,%2
1291 sli. %0,%1,%h2"
1292 [(set_attr "type" "delayed_compare")])
1293
1294(define_insn ""
1295 [(set (match_operand:SI 0 "gen_reg_operand" "=r")
1296 (and:SI (ashift:SI (match_operand:SI 1 "gen_reg_operand" "r")
1297 (match_operand:SI 2 "const_int_operand" "i"))
1298 (match_operand:SI 3 "mask_operand" "L")))]
1299 "includes_lshift_p (operands[2], operands[3])"
1300 "rlinm %0,%h1,%h2,%m3,%M3")
1301
1302(define_insn ""
1303 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1304 (compare:CC
1305 (and:SI (ashift:SI (match_operand:SI 1 "gen_reg_operand" "r")
1306 (match_operand:SI 2 "const_int_operand" "i"))
1307 (match_operand:SI 3 "mask_operand" "L"))
1308 (const_int 0)))
1309 (clobber (match_scratch:SI 4 "=r"))]
1310 "includes_lshift_p (operands[2], operands[3])"
1311 "rlinm. %4,%h1,%h2,%m3,%M3"
1312 [(set_attr "type" "delayed_compare")])
1313
1314(define_insn ""
1315 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
1316 (compare:CC
1317 (and:SI (ashift:SI (match_operand:SI 1 "gen_reg_operand" "r")
1318 (match_operand:SI 2 "const_int_operand" "i"))
1319 (match_operand:SI 3 "mask_operand" "L"))
1320 (const_int 0)))
1321 (set (match_operand:SI 0 "gen_reg_operand" "=r")
1322 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
1323 "includes_lshift_p (operands[2], operands[3])"
1324 "rlinm. %0,%h1,%h2,%m3,%M3"
1325 [(set_attr "type" "delayed_compare")])
1326
5c23c401
RK		 1327;; The RS/6000 assembler mis-handles "sri x,x,0", so write that case as
1328;; "sli x,x,0".
1fd4e8c1
RK		 1329(define_insn "lshrsi3"
1330 [(set (match_operand:SI 0 "gen_reg_operand" "=r,r")
1331 (lshiftrt:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
1332 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
1333 (clobber (match_scratch:SI 3 "=q,X"))]
1334 ""
1335 "@
1336 sre %0,%1,%2
5c23c401 1337 s%A2i %0,%1,%h2")
1fd4e8c1
RK		 1338
1339(define_insn ""
1340 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
1341 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
1342 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
1343 (const_int 0)))
1344 (clobber (match_scratch:SI 3 "=r,r"))
1345 (clobber (match_scratch:SI 4 "=q,X"))]
1346 ""
1347 "@
1348 sre. %3,%1,%2
5c23c401 1349 s%A2i. %3,%1,%h2"
1fd4e8c1
RK		 1350 [(set_attr "type" "delayed_compare")])
1351
1352(define_insn ""
1353 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x")
1354 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
1355 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
1356 (const_int 0)))
1357 (set (match_operand:SI 0 "gen_reg_operand" "=r,r")
1358 (lshiftrt:SI (match_dup 1) (match_dup 2)))
1359 (clobber (match_scratch:SI 4 "=q,X"))]
1360 ""
1361 "@
1362 sre. %0,%1,%2
5c23c401 1363 s%A2i. %0,%1,%h2"
1fd4e8c1
RK		 1364 [(set_attr "type" "delayed_compare")])
1365
1366(define_insn ""
1367 [(set (match_operand:SI 0 "gen_reg_operand" "=r")
1368 (and:SI (lshiftrt:SI (match_operand:SI 1 "gen_reg_operand" "r")
1369 (match_operand:SI 2 "const_int_operand" "i"))
1370 (match_operand:SI 3 "mask_operand" "L")))]
1371 "includes_rshift_p (operands[2], operands[3])"
1372 "rlinm %0,%1,%s2,%m3,%M3")
1373
1374(define_insn ""
1375 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1376 (compare:CC
1377 (and:SI (lshiftrt:SI (match_operand:SI 1 "gen_reg_operand" "r")
1378 (match_operand:SI 2 "const_int_operand" "i"))
1379 (match_operand:SI 3 "mask_operand" "L"))
1380 (const_int 0)))
1381 (clobber (match_scratch:SI 4 "=r"))]
1382 "includes_rshift_p (operands[2], operands[3])"
1383 "rlinm. %4,%1,%s2,%m3,%M3"
1384 [(set_attr "type" "delayed_compare")])
1385
1386(define_insn ""
1387 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
1388 (compare:CC
1389 (and:SI (lshiftrt:SI (match_operand:SI 1 "gen_reg_operand" "r")
1390 (match_operand:SI 2 "const_int_operand" "i"))
1391 (match_operand:SI 3 "mask_operand" "L"))
1392 (const_int 0)))
1393 (set (match_operand:SI 0 "gen_reg_operand" "=r")
1394 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
1395 "includes_rshift_p (operands[2], operands[3])"
1396 "rlinm. %0,%1,%s2,%m3,%M3"
1397 [(set_attr "type" "delayed_compare")])
1398
1399(define_insn ""
1400 [(set (match_operand:SI 0 "gen_reg_operand" "=r")
1401 (zero_extend:SI
1402 (subreg:QI
1403 (lshiftrt:SI (match_operand:SI 1 "gen_reg_operand" "r")
1404 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
1405 "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 255))"
1406 "rlinm %0,%1,%s2,24,31")
1407
1408(define_insn ""
1409 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1410 (compare:CC
1411 (zero_extend:SI
1412 (subreg:QI
1413 (lshiftrt:SI (match_operand:SI 1 "gen_reg_operand" "r")
1414 (match_operand:SI 2 "const_int_operand" "i")) 0))
1415 (const_int 0)))
1416 (clobber (match_scratch:SI 3 "=r"))]
1417 "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 255))"
1418 "rlinm. %3,%1,%s2,24,31"
1419 [(set_attr "type" "delayed_compare")])
1420
1421(define_insn ""
1422 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1423 (compare:CC
1424 (zero_extend:SI
1425 (subreg:QI
1426 (lshiftrt:SI (match_operand:SI 1 "gen_reg_operand" "r")
1427 (match_operand:SI 2 "const_int_operand" "i")) 0))
1428 (const_int 0)))
1429 (set (match_operand:SI 0 "gen_reg_operand" "=r")
1430 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
1431 "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 255))"
1432 "rlinm. %0,%1,%s2,24,31"
1433 [(set_attr "type" "delayed_compare")])
1434
1435(define_insn ""
1436 [(set (match_operand:SI 0 "gen_reg_operand" "=r")
1437 (zero_extend:SI
1438 (subreg:HI
1439 (lshiftrt:SI (match_operand:SI 1 "gen_reg_operand" "r")
1440 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
1441 "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 65535))"
1442 "rlinm %0,%1,%s2,16,31")
1443
1444(define_insn ""
1445 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1446 (compare:CC
1447 (zero_extend:SI
1448 (subreg:HI
1449 (lshiftrt:SI (match_operand:SI 1 "gen_reg_operand" "r")
1450 (match_operand:SI 2 "const_int_operand" "i")) 0))
1451 (const_int 0)))
1452 (clobber (match_scratch:SI 3 "=r"))]
1453 "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 65535))"
1454 "rlinm. %3,%1,%s2,16,31"
1455 [(set_attr "type" "delayed_compare")])
1456
1457(define_insn ""
1458 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1459 (compare:CC
1460 (zero_extend:SI
1461 (subreg:HI
1462 (lshiftrt:SI (match_operand:SI 1 "gen_reg_operand" "r")
1463 (match_operand:SI 2 "const_int_operand" "i")) 0))
1464 (const_int 0)))
1465 (set (match_operand:SI 0 "gen_reg_operand" "=r")
1466 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
1467 "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 65535))"
1468 "rlinm. %0,%1,%s2,16,31"
1469 [(set_attr "type" "delayed_compare")])
1470
1471(define_insn ""
1472 [(set (zero_extract:SI (match_operand:SI 0 "gen_reg_operand" "+r")
1473 (const_int 1)
1474 (match_operand:SI 1 "gen_reg_operand" "r"))
1475 (ashiftrt:SI (match_operand:SI 2 "gen_reg_operand" "r")
1476 (const_int 31)))]
1477 ""
1478 "rrib %0,%1,%2")
1479
1480(define_insn ""
1481 [(set (zero_extract:SI (match_operand:SI 0 "gen_reg_operand" "+r")
1482 (const_int 1)
1483 (match_operand:SI 1 "gen_reg_operand" "r"))
1484 (lshiftrt:SI (match_operand:SI 2 "gen_reg_operand" "r")
1485 (const_int 31)))]
1486 ""
1487 "rrib %0,%1,%2")
1488
1489(define_insn ""
1490 [(set (zero_extract:SI (match_operand:SI 0 "gen_reg_operand" "+r")
1491 (const_int 1)
1492 (match_operand:SI 1 "gen_reg_operand" "r"))
1493 (zero_extract:SI (match_operand:SI 2 "gen_reg_operand" "r")
1494 (const_int 1)
1495 (const_int 0)))]
1496 ""
1497 "rrib %0,%1,%2")
1498
1499(define_insn "ashrsi3"
1500 [(set (match_operand:SI 0 "gen_reg_operand" "=r,r")
1501 (ashiftrt:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
1502 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
1503 (clobber (match_scratch:SI 3 "=q,X"))]
1504 ""
1505 "@
1506 srea %0,%1,%2
1507 srai %0,%1,%h2")
1508
1509(define_insn ""
1510 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
1511 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
1512 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
1513 (const_int 0)))
1514 (clobber (match_scratch:SI 3 "=r,r"))
1515 (clobber (match_scratch:SI 4 "=q,X"))]
1516 ""
1517 "@
1518 srea. %3,%1,%2
1519 srai. %3,%1,%h2"
1520 [(set_attr "type" "delayed_compare")])
1521
1522(define_insn ""
1523 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x")
1524 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
1525 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
1526 (const_int 0)))
1527 (set (match_operand:SI 0 "gen_reg_operand" "=r,r")
1528 (ashiftrt:SI (match_dup 1) (match_dup 2)))
1529 (clobber (match_scratch:SI 4 "=q,X"))]
1530 ""
1531 "@
1532 srea. %0,%1,%2
1533 srai. %0,%1,%h2"
1534 [(set_attr "type" "delayed_compare")])
1535
1536(define_expand "extendqisi2"
1537 [(parallel [(set (match_dup 2)
1538 (ashift:SI (match_operand:QI 1 "gen_reg_operand" "")
1539 (const_int 24)))
1540 (clobber (scratch:SI))])
1541 (parallel [(set (match_operand:SI 0 "gen_reg_operand" "")
1542 (ashiftrt:SI (match_dup 2)
1543 (const_int 24)))
1544 (clobber (scratch:SI))])]
1545 ""
1546 "
1547{ operands[1] = gen_lowpart (SImode, operands[1]);
1548 operands[2] = gen_reg_rtx (SImode); }")
1549
1550(define_expand "extendqihi2"
1551 [(parallel [(set (match_dup 2)
1552 (ashift:SI (match_operand:QI 1 "gen_reg_operand" "")
1553 (const_int 24)))
1554 (clobber (scratch:SI))])
1555 (parallel [(set (match_operand:HI 0 "gen_reg_operand" "")
1556 (ashiftrt:SI (match_dup 2)
1557 (const_int 24)))
1558 (clobber (scratch:SI))])]
1559 ""
1560 "
1561{ operands[0] = gen_lowpart (SImode, operands[0]);
1562 operands[1] = gen_lowpart (SImode, operands[1]);
1563 operands[2] = gen_reg_rtx (SImode); }")
1564\f
1565;; Floating-point insns, excluding normal data motion.
1566;;
1567;; We pretend that we have both SFmode and DFmode insns, while, in fact,
1568;; all fp insns are actually done in double. The only conversions we will
1569;; do will be when storing to memory. In that case, we will use the "frsp"
1570;; instruction before storing.
1571;;
1572;; Note that when we store into a single-precision memory location, we need to
1573;; use the frsp insn first. If the register being stored isn't dead, we
1574;; need a scratch register for the frsp. But this is difficult when the store
1575;; is done by reload. It is not incorrect to do the frsp on the register in
1576;; this case, we just lose precision that we would have otherwise gotten but
1577;; is not guaranteed. Perhaps this should be tightened up at some point.
1578
1579(define_insn "extendsfdf2"
1580 [(set (match_operand:DF 0 "gen_reg_operand" "=f")
1581 (float_extend:DF (match_operand:SF 1 "gen_reg_operand" "f")))]
1582 ""
1583 "*
1584{
1585 if (REGNO (operands[0]) == REGNO (operands[1]))
1586 return \"\";
1587 else
1588 return \"fmr %0,%1\";
1589}"
1590 [(set_attr "type" "fp")])
1591
1592(define_insn "truncdfsf2"
1593 [(set (match_operand:SF 0 "gen_reg_operand" "=f")
1594 (float_truncate:SF (match_operand:DF 1 "gen_reg_operand" "f")))]
1595 ""
1596 "*
1597{
1598 if (REGNO (operands[0]) == REGNO (operands[1]))
1599 return \"\";
1600 else
1601 return \"fmr %0,%1\";
1602}"
1603 [(set_attr "type" "fp")])
1604
1605(define_insn "negsf2"
1606 [(set (match_operand:SF 0 "gen_reg_operand" "=f")
1607 (neg:SF (match_operand:SF 1 "gen_reg_operand" "f")))]
1608 ""
1609 "fneg %0,%1"
1610 [(set_attr "type" "fp")])
1611
1612(define_insn "abssf2"
1613 [(set (match_operand:SF 0 "gen_reg_operand" "=f")
1614 (abs:SF (match_operand:SF 1 "gen_reg_operand" "f")))]
1615 ""
1616 "fabs %0,%1"
1617 [(set_attr "type" "fp")])
1618
1619(define_insn ""
1620 [(set (match_operand:SF 0 "gen_reg_operand" "=f")
1621 (neg:SF (abs:SF (match_operand:SF 1 "gen_reg_operand" "f"))))]
1622 ""
1623 "fnabs %0,%1"
1624 [(set_attr "type" "fp")])
1625
1626(define_insn "addsf3"
1627 [(set (match_operand:SF 0 "gen_reg_operand" "=f")
1628 (plus:SF (match_operand:SF 1 "gen_reg_operand" "%f")
1629 (match_operand:SF 2 "gen_reg_operand" "f")))]
1630 ""
1631 "fa %0,%1,%2"
1632 [(set_attr "type" "fp")])
1633
1634(define_insn "subsf3"
1635 [(set (match_operand:SF 0 "gen_reg_operand" "=f")
1636 (minus:SF (match_operand:SF 1 "gen_reg_operand" "f")
1637 (match_operand:SF 2 "gen_reg_operand" "f")))]
1638 ""
1639 "fs %0,%1,%2"
1640 [(set_attr "type" "fp")])
1641
1642(define_insn "mulsf3"
1643 [(set (match_operand:SF 0 "gen_reg_operand" "=f")
1644 (mult:SF (match_operand:SF 1 "gen_reg_operand" "%f")
1645 (match_operand:SF 2 "gen_reg_operand" "f")))]
1646 ""
1647 "fm %0,%1,%2"
1648 [(set_attr "type" "fp")])
1649
1650(define_insn "divsf3"
1651 [(set (match_operand:SF 0 "gen_reg_operand" "=f")
1652 (div:SF (match_operand:SF 1 "gen_reg_operand" "f")
1653 (match_operand:SF 2 "gen_reg_operand" "f")))]
1654 ""
1655 "fd %0,%1,%2"
1656 [(set_attr "type" "fp")])
1657
1658(define_insn ""
1659 [(set (match_operand:SF 0 "gen_reg_operand" "=f")
1660 (plus:SF (mult:SF (match_operand:SF 1 "gen_reg_operand" "%f")
1661 (match_operand:SF 2 "gen_reg_operand" "f"))
1662 (match_operand:SF 3 "gen_reg_operand" "f")))]
1663 ""
1664 "fma %0,%1,%2,%3"
1665 [(set_attr "type" "fp")])
1666
1667(define_insn ""
1668 [(set (match_operand:SF 0 "gen_reg_operand" "=f")
1669 (minus:SF (mult:SF (match_operand:SF 1 "gen_reg_operand" "%f")
1670 (match_operand:SF 2 "gen_reg_operand" "f"))
1671 (match_operand:SF 3 "gen_reg_operand" "f")))]
1672 ""
1673 "fms %0,%1,%2,%3"
1674 [(set_attr "type" "fp")])
1675
1676(define_insn ""
1677 [(set (match_operand:SF 0 "gen_reg_operand" "=f")
1678 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gen_reg_operand" "%f")
1679 (match_operand:SF 2 "gen_reg_operand" "f"))
1680 (match_operand:SF 3 "gen_reg_operand" "f"))))]
1681 ""
1682 "fnma %0,%1,%2,%3"
1683 [(set_attr "type" "fp")])
1684
1685(define_insn ""
1686 [(set (match_operand:SF 0 "gen_reg_operand" "=f")
1687 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gen_reg_operand" "%f")
1688 (match_operand:SF 2 "gen_reg_operand" "f"))
1689 (match_operand:SF 3 "gen_reg_operand" "f"))))]
1690 ""
1691 "fnms %0,%1,%2,%3"
1692 [(set_attr "type" "fp")])
1693
1694(define_insn "negdf2"
1695 [(set (match_operand:DF 0 "gen_reg_operand" "=f")
1696 (neg:DF (match_operand:DF 1 "gen_reg_operand" "f")))]
1697 ""
1698 "fneg %0,%1"
1699 [(set_attr "type" "fp")])
1700
1701(define_insn "absdf2"
1702 [(set (match_operand:DF 0 "gen_reg_operand" "=f")
1703 (abs:DF (match_operand:DF 1 "gen_reg_operand" "f")))]
1704 ""
1705 "fabs %0,%1"
1706 [(set_attr "type" "fp")])
1707
1708(define_insn ""
1709 [(set (match_operand:DF 0 "gen_reg_operand" "=f")
1710 (neg:DF (abs:DF (match_operand:DF 1 "gen_reg_operand" "f"))))]
1711 ""
1712 "fnabs %0,%1"
1713 [(set_attr "type" "fp")])
1714
1715(define_insn "adddf3"
1716 [(set (match_operand:DF 0 "gen_reg_operand" "=f")
1717 (plus:DF (match_operand:DF 1 "gen_reg_operand" "%f")
1718 (match_operand:DF 2 "gen_reg_operand" "f")))]
1719 ""
1720 "fa %0,%1,%2"
1721 [(set_attr "type" "fp")])
1722
1723(define_insn "subdf3"
1724 [(set (match_operand:DF 0 "gen_reg_operand" "=f")
1725 (minus:DF (match_operand:DF 1 "gen_reg_operand" "f")
1726 (match_operand:DF 2 "gen_reg_operand" "f")))]
1727 ""
1728 "fs %0,%1,%2"
1729 [(set_attr "type" "fp")])
1730
1731(define_insn "muldf3"
1732 [(set (match_operand:DF 0 "gen_reg_operand" "=f")
1733 (mult:DF (match_operand:DF 1 "gen_reg_operand" "%f")
1734 (match_operand:DF 2 "gen_reg_operand" "f")))]
1735 ""
1736 "fm %0,%1,%2"
1737 [(set_attr "type" "fp")])
1738
1739(define_insn "divdf3"
1740 [(set (match_operand:DF 0 "gen_reg_operand" "=f")
1741 (div:DF (match_operand:DF 1 "gen_reg_operand" "f")
1742 (match_operand:DF 2 "gen_reg_operand" "f")))]
1743 ""
1744 "fd %0,%1,%2"
1745 [(set_attr "type" "fp")])
1746
1747(define_insn ""
1748 [(set (match_operand:DF 0 "gen_reg_operand" "=f")
1749 (plus:DF (mult:DF (match_operand:DF 1 "gen_reg_operand" "%f")
1750 (match_operand:DF 2 "gen_reg_operand" "f"))
1751 (match_operand:DF 3 "gen_reg_operand" "f")))]
1752 ""
1753 "fma %0,%1,%2,%3"
1754 [(set_attr "type" "fp")])
1755
1756(define_insn ""
1757 [(set (match_operand:DF 0 "gen_reg_operand" "=f")
1758 (minus:DF (mult:DF (match_operand:DF 1 "gen_reg_operand" "%f")
1759 (match_operand:DF 2 "gen_reg_operand" "f"))
1760 (match_operand:DF 3 "gen_reg_operand" "f")))]
1761 ""
1762 "fms %0,%1,%2,%3"
1763 [(set_attr "type" "fp")])
1764
1765(define_insn ""
1766 [(set (match_operand:DF 0 "gen_reg_operand" "=f")
1767 (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gen_reg_operand" "%f")
1768 (match_operand:DF 2 "gen_reg_operand" "f"))
1769 (match_operand:DF 3 "gen_reg_operand" "f"))))]
1770 ""
1771 "fnma %0,%1,%2,%3"
1772 [(set_attr "type" "fp")])
1773
1774(define_insn ""
1775 [(set (match_operand:DF 0 "gen_reg_operand" "=f")
1776 (neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gen_reg_operand" "%f")
1777 (match_operand:DF 2 "gen_reg_operand" "f"))
1778 (match_operand:DF 3 "gen_reg_operand" "f"))))]
1779 ""
1780 "fnms %0,%1,%2,%3"
1781 [(set_attr "type" "fp")])
1782\f
1783;; Conversions to and from floating-point.
1784(define_expand "floatsidf2"
1785 [(set (match_dup 2)
1786 (plus:DI (zero_extend:DI
1787 (xor:SI (match_operand:SI 1 "gen_reg_operand" "")
1788 (match_dup 3)))
1789 (match_dup 4)))
1790 (set (match_operand:DF 0 "gen_reg_operand" "")
1791 (minus:DF (subreg:DF (match_dup 2) 0)
1792 (match_dup 5)))]
1793 ""
1794 "
1795{
1796#if HOST_BITS_PER_INT != BITS_PER_WORD
1797 /* Maybe someone can figure out how to do this in that case. I don't
1798 want to right now. */
1799 abort ();
1800#endif
1801
1802 operands[2] = gen_reg_rtx (DImode);
1803 operands[3] = gen_rtx (CONST_INT, VOIDmode, 0x80000000);
1804 operands[4] = immed_double_const (0, 0x43300000, DImode);
1805 operands[5] = force_reg (DFmode, immed_double_const (0x43300000,
1806 0x80000000, DFmode));
1807}")
1808
1809(define_expand "floatunssidf2"
1810 [(set (match_dup 2)
1811 (plus:DI (zero_extend:DI (match_operand:SI 1 "gen_reg_operand" ""))
1812 (match_dup 3)))
1813 (set (match_operand:DF 0 "gen_reg_operand" "")
1814 (minus:DF (subreg:DF (match_dup 2) 0)
1815 (match_dup 4)))]
1816 ""
1817 "
1818{
1819#if HOST_BITS_PER_INT != BITS_PER_WORD
1820 /* Maybe someone can figure out how to do this in that case. I don't
1821 want to right now. */
1822 abort ();
1823#endif
1824
1825 operands[2] = gen_reg_rtx (DImode);
1826 operands[3] = immed_double_const (0, 0x43300000, DImode);
1827 operands[4] = force_reg (DFmode, immed_double_const (0x43300000, 0, DFmode));
1828}")
1829
1830;; For the above two cases, we always split.
1831(define_split
1832 [(set (match_operand:DI 0 "gen_reg_operand" "")
1833 (plus:DI (zero_extend:DI
1834 (xor:SI (match_operand:SI 1 "gen_reg_operand" "")
1835 (match_operand:SI 2 "logical_operand" "")))
1836 (match_operand:DI 3 "immediate_operand" "")))]
1837 "reload_completed && HOST_BITS_PER_INT == BITS_PER_WORD
1838 && GET_CODE (operands[3]) == CONST_DOUBLE
1839 && CONST_DOUBLE_LOW (operands[3]) == 0"
1840 [(set (match_dup 6) (xor:SI (match_dup 1) (match_dup 2)))
1841 (set (match_dup 4) (match_dup 5))]
1842 "
1843{ operands[4] = operand_subword (operands[0], 0, 0, DImode);
1844 operands[5] = operand_subword (operands[3], 0, 0, DImode);
1845 operands[6] = operand_subword (operands[0], 1, 0, DImode);
1846}")
1847
1848(define_insn ""
1849 [(set (match_operand:DI 0 "gen_reg_operand" "=r")
1850 (plus:DI (zero_extend:DI
1851 (xor:SI (match_operand:SI 1 "gen_reg_operand" "%r")
1852 (match_operand:SI 2 "logical_operand" "rKJ")))
1853 (match_operand:DI 3 "immediate_operand" "n")))]
1854 "HOST_BITS_PER_INT == BITS_PER_WORD
1855 && GET_CODE (operands[3]) == CONST_DOUBLE
1856 && CONST_DOUBLE_LOW (operands[3]) == 0"
1857 "#")
1858
1859(define_split
1860 [(set (match_operand:DI 0 "gen_reg_operand" "=")
1861 (plus:DI (zero_extend:DI (match_operand:SI 1 "gen_reg_operand" ""))
1862 (match_operand:DI 2 "immediate_operand" "")))]
1863 "reload_completed && HOST_BITS_PER_INT == BITS_PER_WORD
1864 && GET_CODE (operands[2]) == CONST_DOUBLE
1865 && CONST_DOUBLE_LOW (operands[2]) == 0"
1866 [(set (match_dup 3) (match_dup 4))
1867 (set (match_dup 5) (match_dup 1))]
1868 "
1869{ operands[3] = operand_subword (operands[0], 0, 0, DImode);
1870 operands[4] = operand_subword (operands[2], 0, 0, DImode);
1871 operands[5] = operand_subword (operands[0], 1, 0, DImode);
1872
1873 if (rtx_equal_p (operands[1], operands[5]))
1874 {
1875 emit_move_insn (operands[3], operands[4]);
1876 DONE;
1877 }
1878}")
1879
1880(define_insn ""
1881 [(set (match_operand:DI 0 "gen_reg_operand" "=r")
1882 (plus:DI (zero_extend:DI (match_operand:SI 1 "gen_reg_operand" "r"))
1883 (match_operand:DI 2 "immediate_operand" "n")))]
1884 "HOST_BITS_PER_INT == BITS_PER_WORD
1885 && GET_CODE (operands[2]) == CONST_DOUBLE
1886 && CONST_DOUBLE_LOW (operands[2]) == 0"
1887 "#")
1888
1889(define_expand "fix_truncdfsi2"
1890 [(set (match_operand:SI 0 "gen_reg_operand" "")
1891 (fix:DF (match_operand:DF 1 "gen_reg_operand" "")))]
1892 ""
1893 "
1894{
1895 emit_insn (gen_trunc_call (operands[0], operands[1],
1896 gen_rtx (SYMBOL_REF, Pmode, \"itrunc\")));
1897 DONE;
1898}")
1899
1900(define_expand "fixuns_truncdfsi2"
1901 [(set (match_operand:SI 0 "gen_reg_operand" "")
1902 (unsigned_fix:DF (match_operand:DF 1 "gen_reg_operand" "")))]
1903 ""
1904 "
1905{
1906 emit_insn (gen_trunc_call (operands[0], operands[1],
1907 gen_rtx (SYMBOL_REF, Pmode, \"uitrunc\")));
1908 DONE;
1909}")
1910
1911
1912(define_expand "trunc_call"
1913 [(parallel [(set (match_operand:SI 0 "" "")
1914 (fix:DF (match_operand:DF 1 "" "")))
1915 (use (match_operand:SI 2 "" ""))])]
1916 ""
1917 "
1918{
1919 rtx insns = gen_trunc_call_rtl (operands[0], operands[1], operands[2]);
1920 rtx first = XVECEXP (insns, 0, 0);
1921 rtx last = XVECEXP (insns, 0, XVECLEN (insns, 0) - 1);
1922
1923 REG_NOTES (first) = gen_rtx (INSN_LIST, REG_LIBCALL, last,
1924 REG_NOTES (first));
1925 REG_NOTES (last) = gen_rtx (INSN_LIST, REG_RETVAL, first, REG_NOTES (last));
1926
1927 emit_insn (insns);
1928 DONE;
1929}")
1930
1931(define_expand "trunc_call_rtl"
1932 [(set (reg:DF 33) (match_operand:DF 1 "gen_reg_operand" ""))
1933 (use (reg:DF 33))
1934 (parallel [(set (reg:SI 3)
1935 (call (mem:SI (match_operand 2 "" "")) (const_int 0)))
1936 (clobber (scratch:SI))])
1937 (set (match_operand:SI 0 "gen_reg_operand" "")
1938 (reg:SI 3))]
1939 ""
1940 "
1941{
1942 rs6000_trunc_used = 1;
1943}")
1944\f
1945;; Define the DImode operations that can be done in a small number
1946;; of instructions.
1947(define_insn "adddi3"
1948 [(set (match_operand:DI 0 "gen_reg_operand" "=r")
1949 (plus:DI (match_operand:DI 1 "gen_reg_operand" "%r")
1950 (match_operand:DI 2 "gen_reg_operand" "r")))]
1951 ""
1952 "a %L0,%L1,%L2\;ae %0,%1,%2")
1953
1954(define_insn "subdi3"
1955 [(set (match_operand:DI 0 "gen_reg_operand" "=r")
1956 (minus:DI (match_operand:DI 1 "gen_reg_operand" "r")
1957 (match_operand:DI 2 "gen_reg_operand" "r")))]
1958 ""
1959 "sf %L0,%L2,%L1\;sfe %0,%2,%1")
1960
1961(define_insn "negdi3"
1962 [(set (match_operand:DI 0 "gen_reg_operand" "=r")
1963 (neg:DI (match_operand:DI 1 "gen_reg_operand" "r")))]
1964 ""
1965 "sfi %L0,%L1,0\;sfze %0,%1")
1966
1967(define_insn "mulsidi3"
1968 [(set (match_operand:DI 0 "gen_reg_operand" "=r")
1969 (mult:DI (sign_extend:DI (match_operand:SI 1 "gen_reg_operand" "r"))
1970 (sign_extend:DI (match_operand:SI 2 "gen_reg_operand" "r"))))
1971 (clobber (match_scratch:SI 3 "=q"))]
1972 ""
1973 "mul %0,%1,%2\;mfmq %L0")
1974
1975;; If operands 0 and 2 are in the same register, we have a problem. But
1976;; operands 0 and 1 (the usual case) can be in the same register. That's
1977;; why we have the strange constraints below.
1978(define_insn "ashldi3"
1979 [(set (match_operand:DI 0 "gen_reg_operand" "=r,r,r,&r")
1980 (ashift:DI (match_operand:DI 1 "gen_reg_operand" "r,r,0,r")
1981 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
1982 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
1983 ""
1984 "@
1985 sli %0,%L1,%h2\;cal %L0,0(0)
1986 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
1987 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
5c23c401 1988 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2")
1fd4e8c1
RK		 1989
1990(define_insn "lshrdi3"
5c23c401 1991 [(set (match_operand:DI 0 "gen_reg_operand" "=&r,r,r,&r")
1fd4e8c1
RK		 1992 (lshiftrt:DI (match_operand:DI 1 "gen_reg_operand" "r,r,0,r")
1993 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
1994 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
1995 ""
1996 "@
5c23c401
RK		 1997 cal %0,0(0)\;s%A2i %L0,%1,%h2
1998 s%A2%I2q %L0,%L1,%2\;srl%I2q %0,%1,%2
1999 s%A2%I2q %L0,%L1,%2\;srl%I2q %0,%1,%2
2000 s%A2%I2q %L0,%L1,%2\;srl%I2q %0,%1,%2")
1fd4e8c1
RK		 2001
2002;; Shift by a variable amount is too complex to be worth open-coding. We
2003;; just handle shifts by constants.
2004
2005(define_expand "ashrdi3"
2006 [(parallel [(set (match_operand:DI 0 "gen_reg_operand" "=")
2007 (ashiftrt:DI (match_operand:DI 1 "gen_reg_operand" "")
2008 (match_operand:SI 2 "general_operand" "")))
2009 (clobber (match_scratch:SI 3 ""))])]
2010 ""
2011 "
2012{ if (GET_CODE (operands[2]) != CONST_INT)
2013 FAIL;
2014}")
2015
2016(define_insn ""
2017 [(set (match_operand:DI 0 "gen_reg_operand" "=r,r")
2018 (ashiftrt:DI (match_operand:DI 1 "gen_reg_operand" "r,r")
2019 (match_operand:SI 2 "const_int_operand" "M,i")))
2020 (clobber (match_scratch:SI 3 "=X,q"))]
2021 ""
2022 "@
2023 srai %0,%1,31\;srai %L0,%1,%h2
2024 sraiq %L0,%L1,%2\;srlq %0,%1,%2")
2025\f
2026;; Now define ways of moving data around.
2027;;
2028;; For SI, we special-case integers that can't be loaded in one insn. We
2029;; do the load 16-bits at a time. We could do this by loading from memory,
2030;; and this is even supposed to be faster, but it is simpler not to get
2031;; integers in the TOC.
2032(define_expand "movsi"
2033 [(set (match_operand:SI 0 "general_operand" "")
2034 (match_operand:SI 1 "any_operand" ""))]
2035 ""
2036 "
2037{
2038 if (GET_CODE (operands[0]) != REG)
2039 operands[1] = force_reg (SImode, operands[1]);
2040
2041 if (CONSTANT_P (operands[1]) && GET_CODE (operands[1]) != CONST_INT)
2042 operands[1] = force_const_mem (SImode, operands[1]);
2043
2044 if (GET_CODE (operands[1]) == CONST_INT
2045 && (unsigned) (INTVAL (operands[1]) + 0x8000) >= 0x10000
2046 && (INTVAL (operands[1]) & 0xffff) != 0)
2047 {
2048 emit_move_insn (operands[0],
2049 gen_rtx (CONST_INT, VOIDmode,
2050 INTVAL (operands[1]) & 0xffff0000));
2051 emit_insn (gen_iorsi3 (operands[0], operands[0],
2052 gen_rtx (CONST_INT, VOIDmode,
2053 INTVAL (operands[1]) & 0xffff)));
2054 DONE;
2055 }
2056}")
2057
2058(define_insn ""
5c23c401
RK		 2059 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,m,r,r,r,*c*q,*l")
2060 (match_operand:SI 1 "input_operand" "r,m,r,I,J,*h,r,r"))]
1fd4e8c1
RK		 2061 "gen_reg_operand (operands[0], SImode)
2062 || gen_reg_operand (operands[1], SImode)"
2063 "@
2064 ai %0,%1,0
2065 l%U1%X1 %0,%1
2066 st%U0%X0 %1,%0
2067 cal %0,%1(0)
2068 cau %0,0,%u1
2069 mf%1 %0
5c23c401 2070 mt%0 %1
1fd4e8c1 2071 mt%0 %1"
5c23c401 2072 [(set_attr "type" "*,load,*,*,*,*,*,mtlr")])
1fd4e8c1
RK		 2073
2074(define_insn ""
2075 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
2076 (compare:CC (match_operand:SI 1 "gen_reg_operand" "r")
2077 (const_int 0)))
2078 (set (match_operand:SI 0 "gen_reg_operand" "=r") (match_dup 1))]
2079 ""
2080 "ai. %0,%1,0"
2081 [(set_attr "type" "compare")])
2082\f
2083(define_expand "movhi"
2084 [(set (match_operand:HI 0 "general_operand" "")
2085 (match_operand:HI 1 "any_operand" ""))]
2086 ""
2087 "
2088{
2089 if (GET_CODE (operands[0]) != REG)
2090 operands[1] = force_reg (HImode, operands[1]);
2091
2092 if (CONSTANT_P (operands[1]) && GET_CODE (operands[1]) != CONST_INT)
2093 operands[1] = force_const_mem (HImode, operands[1]);
2094}")
2095
2096(define_insn ""
2097 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*h")
2098 (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r"))]
2099 "gen_reg_operand (operands[0], HImode)
2100 || gen_reg_operand (operands[1], HImode)"
2101 "@
2102 oril %0,%1,0
2103 lhz%U1%X1 %0,%1
2104 sth%U0%X0 %1,%0
2105 cal %0,%w1(0)
2106 mf%1 %0
2107 mt%0 %1"
2108 [(set_attr "type" "*,load,*,*,*,*")])
2109
2110(define_expand "movqi"
2111 [(set (match_operand:QI 0 "general_operand" "")
2112 (match_operand:QI 1 "any_operand" ""))]
2113 ""
2114 "
2115{
2116 if (GET_CODE (operands[0]) != REG)
2117 operands[1] = force_reg (QImode, operands[1]);
2118
2119 if (CONSTANT_P (operands[1]) && GET_CODE (operands[1]) != CONST_INT)
2120 operands[1] = force_const_mem (QImode, operands[1]);
2121}")
2122
2123(define_insn ""
2124 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*h")
2125 (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r"))]
2126 "gen_reg_operand (operands[0], QImode)
2127 || gen_reg_operand (operands[1], QImode)"
2128 "@
2129 oril %0,%1,0
2130 lbz%U1%X1 %0,%1
2131 stb%U0%X0 %1,%0
2132 cal %0,%1(0)
2133 mf%1 %0
2134 mt%0 %1"
2135 [(set_attr "type" "*,load,*,*,*,*")])
2136\f
2137;; Here is how to move condition codes around. When we store CC data in
2138;; an integer register or memory, we store just the high-order 4 bits.
2139;; This lets us not shift in the most common case of CR0.
2140(define_expand "movcc"
2141 [(set (match_operand:CC 0 "nonimmediate_operand" "")
2142 (match_operand:CC 1 "nonimmediate_operand" ""))]
2143 ""
2144 "")
2145
2146(define_insn ""
2147 [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,y,r,r,r,r,m")
2148 (match_operand:CC 1 "nonimmediate_operand" "y,r,r,x,y,r,m,r"))]
2149 "register_operand (operands[0], CCmode)
2150 || register_operand (operands[1], CCmode)"
2151 "@
2152 mcrf %0,%1
2153 mtcrf 128,%1
2154 rlinm %1,%1,%F0,0,31\;mtcrf %R0,%1\;rlinm %1,%1,%f0,0,31
2155 mfcr %0
2156 mfcr %0\;rlinm %0,%0,%f1,0,3
2157 ai %0,%1,0
2158 l%U1%X1 %0,%1
2159 st%U0%U1 %1,%0"
2160 [(set_attr "type" "*,*,*,compare,*,*,load,*")])
2161\f
2162;; For floating-point, we normally deal with the floating-point registers.
2163;; The sole exception is that parameter passing can produce floating-point
2164;; values in fixed-point registers. Unless the value is a simple constant
2165;; or already in memory, we deal with this by allocating memory and copying
2166;; the value explicitly via that memory location.
2167(define_expand "movsf"
2168 [(set (match_operand:SF 0 "nonimmediate_operand" "")
2169 (match_operand:SF 1 "any_operand" ""))]
2170 ""
2171 "
2172{
2173 /* If we are called from reload, we might be getting a SUBREG of a hard
2174 reg. So expand it. */
2175 if (GET_CODE (operands[0]) == SUBREG
2176 && GET_CODE (SUBREG_REG (operands[0])) == REG
2177 && REGNO (SUBREG_REG (operands[0])) < FIRST_PSEUDO_REGISTER)
2178 operands[0] = alter_subreg (operands[0]);
2179 if (GET_CODE (operands[1]) == SUBREG
2180 && GET_CODE (SUBREG_REG (operands[1])) == REG
2181 && REGNO (SUBREG_REG (operands[1])) < FIRST_PSEUDO_REGISTER)
2182 operands[1] = alter_subreg (operands[1]);
2183
2184 /* If we are being called from reload, it is possible that operands[1]
2185 is a hard non-fp register. So handle those cases. */
2186 if (reload_in_progress && GET_CODE (operands[1]) == REG
2187 && REGNO (operands[1]) < 32)
2188 {
2189 rtx stack_slot;
2190
2191 /* Remember that we only see a pseudo here if it didn't get a hard
2192 register, so it is memory. */
2193 if (GET_CODE (operands[0]) == MEM
2194 || (GET_CODE (operands[0]) == REG
2195 && (REGNO (operands[0]) < 32
2196 || REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER))
2197 || (GET_CODE (operands[0]) == REG && REGNO (operands[0]) < 32))
2198 {
2199 emit_move_insn (operand_subword (operands[0], 0, 0, SFmode),
2200 operand_subword (operands[1], 0, 0, SFmode));
2201 DONE;
2202 }
2203
2204 stack_slot = gen_rtx (MEM, SFmode, plus_constant (stack_pointer_rtx, 4));
2205 emit_move_insn (stack_slot, operands[1]);
2206 emit_move_insn (operands[0], stack_slot);
2207 DONE;
2208 }
2209
2210 if (GET_CODE (operands[0]) == MEM)
2211 operands[1] = force_reg (SFmode, operands[1]);
2212
2213 if (GET_CODE (operands[0]) == REG && REGNO (operands[0]) < 32)
2214 {
2215 rtx stack_slot;
2216
2217 if (GET_CODE (operands[1]) == MEM
2218#if HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT && ! defined(REAL_IS_NOT_DOUBLE)
2219 || GET_CODE (operands[1]) == CONST_DOUBLE
2220#endif
2221 || (GET_CODE (operands[1]) == REG && REGNO (operands[1]) < 32)
2222 || (reload_in_progress && GET_CODE (operands[1]) == REG
2223 && REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER))
2224 {
2225 emit_move_insn (operand_subword (operands[0], 0, 0, SFmode),
2226 operand_subword (operands[1], 0, 0, SFmode));
2227 DONE;
2228 }
2229
2230 if (reload_in_progress)
2231 stack_slot = gen_rtx (MEM, SFmode,
2232 plus_constant (stack_pointer_rtx, 4));
2233 else
2234 stack_slot = assign_stack_temp (SFmode, 4, 0);
2235 emit_move_insn (stack_slot, operands[1]);
2236 emit_move_insn (operands[0], stack_slot);
2237 DONE;
2238 }
2239
2240 if (CONSTANT_P (operands[1]))
2241 {
2242 operands[1] = force_const_mem (SFmode, operands[1]);
2243 if (! memory_address_p (SFmode, XEXP (operands[1], 0))
2244 && ! reload_in_progress)
2245 operands[1] = change_address (operands[1], SFmode,
2246 XEXP (operands[1], 0));
2247 }
2248}")
2249
2250(define_insn ""
2251 [(set (match_operand:SF 0 "gen_reg_operand" "=r,r")
2252 (match_operand:SF 1 "mem_or_easy_const_operand" "G,m"))]
2253 "REGNO (operands[0]) <= 31"
2254 "@
2255 #
2256 l%U1%X1 %0,%1"
2257 [(set_attr "type" "*,load")])
2258
2259(define_split
2260 [(set (match_operand:SF 0 "gen_reg_operand" "")
2261 (match_operand:SF 1 "easy_fp_constant" ""))]
2262 "reload_completed && REGNO (operands[0]) <= 31"
2263 [(set (match_dup 2) (match_dup 3))]
2264 "
2265{ operands[2] = operand_subword (operands[0], 0, 0, SFmode);
2266 operands[3] = operand_subword (operands[1], 0, 0, SFmode); }")
2267
2268(define_insn ""
2269 [(set (match_operand:SF 0 "fp_reg_or_mem_operand" "=f,f,m")
2270 (match_operand:SF 1 "input_operand" "f,m,f"))]
2271 "gen_reg_operand (operands[0], SFmode)
2272 || gen_reg_operand (operands[1], SFmode)"
2273 "@
2274 fmr %0,%1
2275 lfs%U1%X1 %0,%1
2276 frsp %1,%1\;stfs%U0%X0 %1,%0"
2277 [(set_attr "type" "fp,load,*")])
2278\f
2279(define_expand "movdf"
2280 [(set (match_operand:DF 0 "nonimmediate_operand" "")
2281 (match_operand:DF 1 "any_operand" ""))]
2282 ""
2283 "
2284{
2285 /* If we are called from reload, we might be getting a SUBREG of a hard
2286 reg. So expand it. */
2287 if (GET_CODE (operands[0]) == SUBREG
2288 && GET_CODE (SUBREG_REG (operands[0])) == REG
2289 && REGNO (SUBREG_REG (operands[0])) < FIRST_PSEUDO_REGISTER)
2290 operands[0] = alter_subreg (operands[0]);
2291 if (GET_CODE (operands[1]) == SUBREG
2292 && GET_CODE (SUBREG_REG (operands[1])) == REG
2293 && REGNO (SUBREG_REG (operands[1])) < FIRST_PSEUDO_REGISTER)
2294 operands[1] = alter_subreg (operands[1]);
2295
2296 /* If we are being called from reload, it is possible that operands[1]
2297 is a hard non-fp register. So handle those cases. */
2298 if (reload_in_progress && GET_CODE (operands[1]) == REG
2299 && REGNO (operands[1]) < 32)
2300 {
2301 rtx stack_slot;
2302
2303 /* Remember that we only see a pseudo here if it didn't get a hard
2304 register, so it is memory. */
2305 if (GET_CODE (operands[0]) == MEM
2306 || (GET_CODE (operands[0]) == REG
2307 && (REGNO (operands[0]) < 32
2308 || REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER)))
2309 {
2310 emit_move_insn (operand_subword (operands[0], 0, 0, DFmode),
2311 operand_subword (operands[1], 0, 0, DFmode));
2312 emit_move_insn (operand_subword (operands[0], 1, 0, DFmode),
2313 operand_subword (operands[1], 1, 0, DFmode));
2314 DONE;
2315 }
2316
2317 stack_slot = gen_rtx (MEM, DFmode, plus_constant (stack_pointer_rtx, 8));
2318 emit_move_insn (stack_slot, operands[1]);
2319 emit_move_insn (operands[0], stack_slot);
2320 DONE;
2321 }
2322
2323 if (GET_CODE (operands[0]) == MEM)
2324 {
2325 if (GET_CODE (operands[1]) == MEM)
2326 {
2327 emit_move_insn (operand_subword (operands[0], 0, 0, DFmode),
2328 operand_subword (operands[1], 0, 0, DFmode));
2329 emit_move_insn (operand_subword (operands[0], 1, 0, DFmode),
2330 operand_subword (operands[1], 1, 0, DFmode));
2331 DONE;
2332 }
2333
2334 operands[1] = force_reg (DFmode, operands[1]);
2335 }
2336
2337 if (GET_CODE (operands[0]) == REG && REGNO (operands[0]) < 32)
2338 {
2339 rtx stack_slot;
2340
2341 if (GET_CODE (operands[1]) == MEM
2342#if HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT && ! defined(REAL_IS_NOT_DOUBLE)
2343 || GET_CODE (operands[1]) == CONST_DOUBLE
2344#endif
2345 || (GET_CODE (operands[1]) == REG && REGNO (operands[1]) < 32)
2346 || (reload_in_progress && GET_CODE (operands[1]) == REG
2347 && REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER))
2348 {
2349 emit_move_insn (operand_subword (operands[0], 0, 0, DFmode),
2350 operand_subword (operands[1], 0, 0, DFmode));
2351 emit_move_insn (operand_subword (operands[0], 1, 0, DFmode),
2352 operand_subword (operands[1], 1, 0, DFmode));
2353 DONE;
2354 }
2355
2356 if (reload_in_progress)
2357 stack_slot = gen_rtx (MEM, DFmode,
2358 plus_constant (stack_pointer_rtx, 8));
2359 else
2360 stack_slot = assign_stack_temp (DFmode, 8, 0);
2361 emit_move_insn (stack_slot, operands[1]);
2362 emit_move_insn (operands[0], stack_slot);
2363 DONE;
2364 }
2365
2366 if (CONSTANT_P (operands[1]))
2367 {
2368 operands[1] = force_const_mem (DFmode, operands[1]);
2369 if (! memory_address_p (DFmode, XEXP (operands[1], 0))
2370 && ! reload_in_progress)
2371 operands[1] = change_address (operands[1], DFmode,
2372 XEXP (operands[1], 0));
2373 }
2374}")
2375
2376(define_insn ""
2377 [(set (match_operand:DF 0 "gen_reg_operand" "=r,r")
2378 (match_operand:DF 1 "mem_or_easy_const_operand" "G,m"))]
2379 "REGNO (operands[0]) <= 31"
2380 "@
2381 #
2382 l %0,%1\;l %L0,%L1"
2383 [(set_attr "type" "*,load")])
2384
2385(define_split
2386 [(set (match_operand:DF 0 "gen_reg_operand" "")
2387 (match_operand:DF 1 "easy_fp_constant" ""))]
2388 "reload_completed && REGNO (operands[0]) <= 31"
2389 [(set (match_dup 2) (match_dup 3))
2390 (set (match_dup 4) (match_dup 5))]
2391 "
2392{ operands[2] = operand_subword (operands[0], 0, 0, DFmode);
2393 operands[3] = operand_subword (operands[1], 0, 0, DFmode);
2394 operands[4] = operand_subword (operands[0], 1, 0, DFmode);
2395 operands[5] = operand_subword (operands[1], 1, 0, DFmode); }")
2396
2397(define_insn ""
2398 [(set (match_operand:DF 0 "fp_reg_or_mem_operand" "=f,f,m")
2399 (match_operand:DF 1 "fp_reg_or_mem_operand" "f,m,f"))]
2400 "gen_reg_operand (operands[0], DFmode)
2401 || gen_reg_operand (operands[1], DFmode)"
2402 "@
2403 fmr %0,%1
2404 lfd%U1%X1 %0,%1
2405 stfd%U0%X0 %1,%0"
2406 [(set_attr "type" "fp,load,*")])
2407\f
2408;; Next come the multi-word integer load and store and the load and store
2409;; multiple insns.
2410(define_expand "movdi"
2411 [(set (match_operand:DI 0 "general_operand" "")
2412 (match_operand:DI 1 "general_operand" ""))]
2413 ""
2414 "
2415{
2416 if (GET_CODE (operands[0]) == MEM)
2417 operands[1] = force_reg (DImode, operands[1]);
2418
2419 else if (GET_CODE (operands[1]) == CONST_DOUBLE
2420 || GET_CODE (operands[1]) == CONST_INT)
2421 {
2422 emit_move_insn (operand_subword (operands[0], 0, 0, DImode),
2423 operand_subword (operands[1], 0, 0, DImode));
2424 emit_move_insn (operand_subword (operands[0], 1, 0, DImode),
2425 operand_subword (operands[1], 1, 0, DImode));
2426 DONE;
2427 }
2428}")
2429
2430(define_insn ""
2431 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m")
2432 (match_operand:DI 1 "input_operand" "r,m,r"))]
2433 "gen_reg_operand (operands[0], DImode)
2434 || gen_reg_operand (operands[1], DImode)"
2435 "*
2436{
2437 switch (which_alternative)
2438 {
2439 case 0:
2440 /* We normally copy the low-numbered register first. However, if
2441 the first register operand 0 is the same as the second register of
2442 operand 1, we must copy in the opposite order. */
2443 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
2444 return \"oril %L0,%L1,0\;oril %0,%1,0\";
2445 else
2446 return \"oril %0,%1,0\;oril %L0,%L1,0\";
2447 case 1:
2448 /* If the low-address word is used in the address, we must load it
2449 last. Otherwise, load it first. Note that we cannot have
2450 auto-increment in that case since the address register is known to be
2451 dead. */
2452 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
2453 operands [1], 0))
2454 return \"l %L0,%L1\;l %0,%1\";
2455 else
2456 return \"l%U1 %0,%1\;l %L0,%L1\";
2457 case 2:
2458 return \"st%U0 %1,%0\;st %L1,%L0\";
2459 }
2460}"
2461 [(set_attr "type" "*,load,*")])
2462\f
2463;; TImode is similar, except that we usually want to compute the address into
2464;; a register and use lsi/stsi (the exception is during reload). MQ is also
2465;; clobbered in stsi, so we need a SCRATCH for it.
2466(define_expand "movti"
2467 [(parallel [(set (match_operand:TI 0 "general_operand" "")
2468 (match_operand:TI 1 "general_operand" ""))
2469 (clobber (scratch:SI))])]
2470 ""
2471 "
2472{
2473 if (GET_CODE (operands[0]) == MEM)
2474 operands[1] = force_reg (TImode, operands[1]);
2475
2476 if (GET_CODE (operands[0]) == MEM
2477 && GET_CODE (XEXP (operands[0], 0)) != REG
2478 && ! reload_in_progress)
2479 operands[0] = change_address (operands[0], TImode,
2480 copy_addr_to_reg (XEXP (operands[0], 0)));
2481
2482 if (GET_CODE (operands[1]) == MEM
2483 && GET_CODE (XEXP (operands[1], 0)) != REG
2484 && ! reload_in_progress)
2485 operands[1] = change_address (operands[1], TImode,
2486 copy_addr_to_reg (XEXP (operands[1], 0)));
2487}")
2488
2489;; We say that MQ is clobbered in the last alternative because the first
2490;; alternative would never get used otherwise since it would need a reload
2491;; while the 2nd alternative would not. We put memory cases first so they
2492;; are preferred. Otherwise, we'd try to reload the output instead of
2493;; giving the SCRATCH mq.
2494(define_insn ""
2495 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,r,r,r")
2496 (match_operand:TI 1 "reg_or_mem_operand" "r,r,r,Q,m"))
2497 (clobber (match_scratch:SI 2 "=q,q#X,X,X,X"))]
2498 "gen_reg_operand (operands[0], TImode)
2499 || gen_reg_operand (operands[1], TImode)"
2500 "*
2501{
2502 switch (which_alternative)
2503 {
2504 case 0:
2505 return \"stsi %1,%P0,16\";
2506
2507 case 1:
2508 return \"st%U0 %1,%0\;st %L1,%L0\;st %Y1,%Y0\;st %Z1,%Z0\";
2509
2510 case 2:
2511 /* Normally copy registers with lowest numbered register copied first.
2512 But copy in the other order if the first register of the output
2513 is the second, third, or fourth register in the input. */
2514 if (REGNO (operands[0]) >= REGNO (operands[1]) + 1
2515 && REGNO (operands[0]) <= REGNO (operands[1]) + 3)
2516 return \"oril %Z0,%Z1,0\;oril %Y0,%Y1,0\;oril %L0,%L1,0\;oril %0,%1,0\";
2517 else
2518 return \"oril %0,%1,0\;oril %L0,%L1,0\;oril %Y0,%Y1,0\;oril %Z0,%Z1,0\";
2519 case 3:
2520 /* If the address is not used in the output, we can use lsi. Otherwise,
2521 fall through to generating four loads. */
2522 if (! reg_overlap_mentioned_p (operands[0], operands[1]))
2523 return \"lsi %0,%P1,16\";
2524 /* ... fall through ... */
2525 case 4:
2526 /* If the address register is the same as the register for the lowest-
2527 addressed word, load it last. Similarly for the next two words.
2528 Otherwise load lowest address to highest. */
2529 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
2530 operands[1], 0))
2531 return \"l %L0,%L1\;l %Y0,%Y1\;l %Z0,%Z1\;l %0,%1\";
2532 else if (refers_to_regno_p (REGNO (operands[0]) + 1,
2533 REGNO (operands[0]) + 2, operands[1], 0))
2534 return \"l %0,%1\;l %Y0,%Y1\;l %Z0,%Z1\;l %L0,%L1\";
2535 else if (refers_to_regno_p (REGNO (operands[0]) + 2,
2536 REGNO (operands[0]) + 3, operands[1], 0))
2537 return \"l %0,%1\;l %L0,%L1\;l %Z0,%Z1\;l %Y0,%Y1\";
2538 else
2539 return \"l%U1 %0,%1\;l %L0,%L1\;l %Y0,%Y1\;l %Z0,%Z1\";
2540 }
2541}"
2542 [(set_attr "type" "*,load,load,*,*")])
2543\f
2544(define_expand "load_multiple"
2545 [(match_parallel 3 "" [(set (match_operand:SI 0 "" "")
2546 (match_operand:SI 1 "" ""))
2547 (use (match_operand:SI 2 "" ""))])]
2548 ""
2549 "
2550{
2551 int regno;
2552 int count;
2553 rtx from;
2554 int i;
2555
2556 /* Support only loading a constant number of fixed-point registers from
2557 memory and only bother with this if more than two; the machine
2558 doesn't support more than eight. */
2559 if (GET_CODE (operands[2]) != CONST_INT
2560 || INTVAL (operands[2]) <= 2
2561 || INTVAL (operands[2]) > 8
2562 || GET_CODE (operands[1]) != MEM
2563 || GET_CODE (operands[0]) != REG
2564 || REGNO (operands[0]) >= 32)
2565 FAIL;
2566
2567 count = INTVAL (operands[2]);
2568 regno = REGNO (operands[0]);
2569
2570 operands[3] = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (count));
2571 from = force_reg (SImode, XEXP (operands[1], 0));
2572
2573 for (i = 0; i < count; i++)
2574 XVECEXP (operands[3], 0, i)
2575 = gen_rtx (SET, VOIDmode, gen_rtx (REG, SImode, regno + i),
2576 gen_rtx (MEM, SImode, plus_constant (from, i * 4)));
2577}")
2578
2579(define_insn ""
2580 [(match_parallel 0 "load_multiple_operation"
2581 [(set (match_operand:SI 1 "gen_reg_operand" "=r")
2582 (match_operand:SI 2 "indirect_operand" "Q"))])]
2583 ""
2584 "*
2585{
2586 /* We have to handle the case where the pseudo used to contain the address
2587 is assigned to one of the output registers. In that case, do the
2588 lsi, but then load the correct value. This is a bit of a mess, but is
2589 the best we can do. */
2590 static char result[100];
2591 char newload[40];
2592 int i;
2593
2594 strcpy (result, \"lsi %1,%P2,%N0\");
2595 for (i = 0; i < XVECLEN (operands[0], 0); i++)
2596 if (refers_to_regno_p (REGNO (operands[1]) + i,
2597 REGNO (operands[1]) + i + 1, operands[2], 0))
2598 {
2599 sprintf (newload, \"\;l %d,%d(%d)\",
2600 REGNO (operands[1]) + i,
2601 i * 4, REGNO (XEXP (operands[2], 0)));
2602 strcat (result, newload);
2603 }
2604
2605 return result;
2606}"
2607 [(set_attr "type" "load")])
2608\f
2609(define_expand "store_multiple"
2610 [(match_parallel 3 "" [(set (match_operand:SI 0 "" "")
2611 (match_operand:SI 1 "" ""))
2612 (clobber (scratch:SI))
2613 (use (match_operand:SI 2 "" ""))])]
2614 ""
2615 "
2616{
2617 int regno;
2618 int count;
2619 rtx to;
2620 int i;
2621
2622 /* Support only storing a constant number of fixed-point registers to
2623 memory and only bother with this if more than two; the machine
2624 doesn't support more than eight. */
2625 if (GET_CODE (operands[2]) != CONST_INT
2626 || INTVAL (operands[2]) <= 2
2627 || INTVAL (operands[2]) > 8
2628 || GET_CODE (operands[0]) != MEM
2629 || GET_CODE (operands[1]) != REG
2630 || REGNO (operands[1]) >= 32)
2631 FAIL;
2632
2633 count = INTVAL (operands[2]);
2634 regno = REGNO (operands[1]);
2635
2636 operands[3] = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (count + 1));
2637 to = force_reg (SImode, XEXP (operands[0], 0));
2638
2639 XVECEXP (operands[3], 0, 0)
2640 = gen_rtx (SET, VOIDmode, gen_rtx (MEM, SImode, to), operands[1]);
2641 XVECEXP (operands[3], 0, 1) = gen_rtx (CLOBBER, VOIDmode,
2642 gen_rtx (SCRATCH, SImode));
2643
2644 for (i = 1; i < count; i++)
2645 XVECEXP (operands[3], 0, i + 1)
2646 = gen_rtx (SET, VOIDmode,
2647 gen_rtx (MEM, SImode, plus_constant (to, i * 4)),
2648 gen_rtx (REG, SImode, regno + i));
2649}")
2650
2651(define_insn ""
2652 [(match_parallel 0 "store_multiple_operation"
2653 [(set (match_operand:SI 1 "indirect_operand" "=Q")
2654 (match_operand:SI 2 "gen_reg_operand" "r"))
2655 (clobber (match_scratch:SI 3 "=q"))])]
2656 ""
2657 "stsi %2,%P1,%O0")
2658\f
2659;; Define insns that do load or store with update. Some of these we can
2660;; get by using pre-decrement or pre-increment, but the hardware can also
2661;; do cases where the increment is not the size of the object.
2662;;
2663;; In all these cases, we use operands 0 and 1 for the register being
2664;; incremented because those are the operands that local-alloc will
2665;; tie and these are the pair most likely to be tieable (and the ones
2666;; that will benefit the most).
2667
2668(define_insn ""
2669 [(set (match_operand:SI 3 "gen_reg_operand" "=r,r")
2670 (mem:SI (plus:SI (match_operand:SI 1 "gen_reg_operand" "0,0")
2671 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
2672 (set (match_operand:SI 0 "gen_reg_operand" "=b,b")
2673 (plus:SI (match_dup 1) (match_dup 2)))]
2674 ""
2675 "@
2676 lux %3,%1,%2
2677 lu %3,%2(%1)"
2678 [(set_attr "type" "load,load")])
2679
2680(define_insn ""
2681 [(set (mem:SI (plus:SI (match_operand:SI 1 "gen_reg_operand" "0,0")
2682 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
2683 (match_operand:SI 3 "gen_reg_operand" "r,r"))
2684 (set (match_operand:SI 0 "gen_reg_operand" "=b,b")
2685 (plus:SI (match_dup 1) (match_dup 2)))]
2686 ""
2687 "@
2688 stux %3,%1,%2
2689 stu %3,%2(%1)")
2690
2691(define_insn ""
2692 [(set (match_operand:HI 3 "gen_reg_operand" "=r,r")
2693 (mem:HI (plus:SI (match_operand:SI 1 "gen_reg_operand" "0,0")
2694 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
2695 (set (match_operand:SI 0 "gen_reg_operand" "=b,b")
2696 (plus:SI (match_dup 1) (match_dup 2)))]
2697 ""
2698 "@
2699 lhzux %3,%1,%2
2700 lhzu %3,%2(%1)"
2701 [(set_attr "type" "load,load")])
2702
2703(define_insn ""
2704 [(set (match_operand:SI 3 "gen_reg_operand" "=r,r")
2705 (zero_extend:SI
2706 (mem:HI (plus:SI (match_operand:SI 1 "gen_reg_operand" "0,0")
2707 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
2708 (set (match_operand:SI 0 "gen_reg_operand" "=b,b")
2709 (plus:SI (match_dup 1) (match_dup 2)))]
2710 ""
2711 "@
2712 lhzux %3,%1,%2
2713 lhzu %3,%2(%1)"
2714 [(set_attr "type" "load,load")])
2715
2716(define_insn ""
2717 [(set (match_operand:SI 3 "gen_reg_operand" "=r,r")
2718 (sign_extend:SI
2719 (mem:HI (plus:SI (match_operand:SI 1 "gen_reg_operand" "0,0")
2720 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
2721 (set (match_operand:SI 0 "gen_reg_operand" "=b,b")
2722 (plus:SI (match_dup 1) (match_dup 2)))]
2723 ""
2724 "@
2725 lhaux %3,%1,%2
2726 lhau %3,%2(%1)"
2727 [(set_attr "type" "load,load")])
2728
2729(define_insn ""
2730 [(set (mem:HI (plus:SI (match_operand:SI 1 "gen_reg_operand" "0,0")
2731 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
2732 (match_operand:HI 3 "gen_reg_operand" "r,r"))
2733 (set (match_operand:SI 0 "gen_reg_operand" "=b,b")
2734 (plus:SI (match_dup 1) (match_dup 2)))]
2735 ""
2736 "@
2737 sthux %3,%1,%2
2738 sthu %3,%2(%1)"
2739 [(set_attr "type" "load,load")])
2740
2741(define_insn ""
2742 [(set (match_operand:QI 3 "gen_reg_operand" "=r,r")
2743 (mem:QI (plus:SI (match_operand:SI 1 "gen_reg_operand" "0,0")
2744 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
2745 (set (match_operand:SI 0 "gen_reg_operand" "=b,b")
2746 (plus:SI (match_dup 1) (match_dup 2)))]
2747 ""
2748 "@
2749 lbzux %3,%1,%2
2750 lbzu %3,%2(%1)"
2751 [(set_attr "type" "load,load")])
2752
2753(define_insn ""
2754 [(set (match_operand:SI 3 "gen_reg_operand" "=r,r")
2755 (zero_extend:SI
2756 (mem:QI (plus:SI (match_operand:SI 1 "gen_reg_operand" "0,0")
2757 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
2758 (set (match_operand:SI 0 "gen_reg_operand" "=b,b")
2759 (plus:SI (match_dup 1) (match_dup 2)))]
2760 ""
2761 "@
2762 lbzux %3,%1,%2
2763 lbzu %3,%2(%1)"
2764 [(set_attr "type" "load,load")])
2765
2766(define_insn ""
2767 [(set (mem:QI (plus:SI (match_operand:SI 1 "gen_reg_operand" "0,0")
2768 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
2769 (match_operand:QI 3 "gen_reg_operand" "r,r"))
2770 (set (match_operand:SI 0 "gen_reg_operand" "=b,b")
2771 (plus:SI (match_dup 1) (match_dup 2)))]
2772 ""
2773 "@
2774 stbux %3,%1,%2
2775 stbu %3,%2(%1)")
2776
2777(define_insn ""
2778 [(set (match_operand:SF 3 "gen_reg_operand" "=f,f")
2779 (mem:SI (plus:SI (match_operand:SI 1 "gen_reg_operand" "0,0")
2780 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
2781 (set (match_operand:SI 0 "gen_reg_operand" "=b,b")
2782 (plus:SI (match_dup 1) (match_dup 2)))]
2783 ""
2784 "@
2785 lfsux %3,%1,%2
2786 lfsu %3,%2(%1)"
2787 [(set_attr "type" "load,load")])
2788
2789(define_insn ""
2790 [(set (mem:SF (plus:SI (match_operand:SI 1 "gen_reg_operand" "0,0")
2791 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
2792 (match_operand:SF 3 "gen_reg_operand" "f,f"))
2793 (set (match_operand:SI 0 "gen_reg_operand" "=b,b")
2794 (plus:SI (match_dup 1) (match_dup 2)))]
2795 ""
2796 "@
2797 frsp %3,%3\;stfsux %3,%1,%2
2798 frsp %3,%3\;stfsu %3,%2(%1)")
2799
2800(define_insn ""
2801 [(set (match_operand:DF 3 "gen_reg_operand" "=f,f")
2802 (mem:DF (plus:SI (match_operand:SI 1 "gen_reg_operand" "0,0")
2803 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
2804 (set (match_operand:SI 0 "gen_reg_operand" "=b,b")
2805 (plus:SI (match_dup 1) (match_dup 2)))]
2806 ""
2807 "@
2808 lfdux %3,%1,%2
2809 lfdu %3,%2(%1)"
2810 [(set_attr "type" "load,load")])
2811
2812(define_insn ""
2813 [(set (mem:DF (plus:SI (match_operand:SI 1 "gen_reg_operand" "0,0")
2814 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
2815 (match_operand:DF 3 "gen_reg_operand" "f,f"))
2816 (set (match_operand:SI 0 "gen_reg_operand" "=b,b")
2817 (plus:SI (match_dup 1) (match_dup 2)))]
2818 ""
2819 "@
2820 stfdux %3,%1,%2
2821 stfdu %3,%2(%1)")
2822\f
2823;; Next come insns related to the calling sequence.
2824;;
2825;; First, an insn to allocate new stack space for dynamic use (e.g., alloca).
96d3e8f1 2826;; We move the back-chain and decrement the stack pointer. This is slightly
1fd4e8c1
RK		 2827;; less efficient than it needs to be for long constants, but that case
2828;; should be rare.
2829
2830(define_expand "allocate_stack"
2831 [(set (reg:SI 1)
2832 (minus:SI (reg:SI 1) (match_operand:SI 0 "reg_or_cint_operand" "")))]
2833 ""
2834 "
2835{ rtx chain = gen_reg_rtx (SImode);
2836 rtx stack_bot = gen_rtx (MEM, Pmode, stack_pointer_rtx);
2837
2838 emit_move_insn (chain, stack_bot);
2839 emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, operands[0]));
2840 emit_move_insn (stack_bot, chain);
2841 DONE;
2842}")
2843\f
2844;; A function pointer is a pointer to a data area whose first word contains
2845;; the actual address of the function, whose second word contains a pointer
2846;; to its TOC, and whose third word contains a value to place in the static
2847;; chain register (r11). Note that if we load the static chain, our
2848;; "trampoline" need not have any executable code.
2849;;
2850;; operands[0] is an SImode pseudo in which we place the address of the
2851;; function.
2852;; operands[1] is the address of data area of the function to call
2853
2854(define_expand "call_via_ptr"
2855 [(set (match_operand:SI 0 "gen_reg_operand" "")
2856 (mem:SI (match_operand:SI 1 "gen_reg_operand" "")))
2857 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
2858 (reg:SI 2))
2859 (set (reg:SI 2)
2860 (mem:SI (plus:SI (match_dup 1)
2861 (const_int 4))))
2862 (set (reg:SI 11)
2863 (mem:SI (plus:SI (match_dup 1)
2864 (const_int 8))))
2865 (use (reg:SI 2))
2866 (use (reg:SI 11))]
2867 ""
2868 "")
2869
2870(define_expand "call"
2871 [(parallel [(call (mem:SI (match_operand:SI 0 "address_operand" ""))
2872 (match_operand 1 "" ""))
2873 (clobber (scratch:SI))])]
2874 ""
2875 "
2876{
2877 if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != CONST_INT)
2878 abort ();
2879
2880 operands[0] = XEXP (operands[0], 0);
2881 if (GET_CODE (operands[0]) != SYMBOL_REF)
2882 {
2883 rtx temp = gen_reg_rtx (SImode);
2884
2885 emit_insn (gen_call_via_ptr (temp, force_reg (SImode, operands[0])));
2886 operands[0] = temp;
2887 }
2888}")
2889
2890(define_expand "call_value"
2891 [(parallel [(set (match_operand 0 "" "")
2892 (call (mem:SI (match_operand:SI 1 "address_operand" ""))
2893 (match_operand 2 "" "")))
2894 (clobber (scratch:SI))])]
2895 ""
2896 "
2897{
2898 if (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != CONST_INT)
2899 abort ();
2900
2901 operands[1] = XEXP (operands[1], 0);
2902 if (GET_CODE (operands[1]) != SYMBOL_REF)
2903 {
2904 rtx temp = gen_reg_rtx (SImode);
2905
2906 emit_insn (gen_call_via_ptr (temp, force_reg (SImode, operands[1])));
2907 operands[1] = temp;
2908 }
2909}")
2910
2911(define_insn ""
2912 [(call (mem:SI (match_operand:SI 0 "call_operand" "l,s"))
2913 (match_operand 1 "" "fg,fg"))
2914 (clobber (match_scratch:SI 3 "=l,l"))]
2915 ""
2916 "@
2917 brl\;l 2,20(1)
2918 bl %z0\;cror 15,15,15")
2919
2920(define_insn ""
2921 [(set (match_operand 0 "" "fg,fg")
2922 (call (mem:SI (match_operand:SI 1 "call_operand" "l,s"))
2923 (match_operand 2 "" "fg,fg")))
2924 (clobber (match_scratch:SI 3 "=l,l"))]
2925 ""
2926 "@
2927 brl\;l 2,20(1)
2928 bl %z1\;cror 15,15,15")
2929\f
2930;; Compare insns are next. Note that the RS/6000 has two types of compares,
2931;; signed & unsigned, and one type of branch.
2932;;
2933;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc
2934;; insns, and branches. We store the operands of compares until we see
2935;; how it is used.
2936(define_expand "cmpsi"
2937 [(set (cc0)
2938 (compare (match_operand:SI 0 "gen_reg_operand" "")
2939 (match_operand:SI 1 "reg_or_short_operand" "")))]
2940 ""
2941 "
2942{
2943 /* Take care of the possibility that operands[1] might be negative but
2944 this might be a logical operation. That insn doesn't exist. */
2945 if (GET_CODE (operands[1]) == CONST_INT
2946 && INTVAL (operands[1]) < 0)
2947 operands[1] = force_reg (SImode, operands[1]);
2948
2949 rs6000_compare_op0 = operands[0];
2950 rs6000_compare_op1 = operands[1];
2951 rs6000_compare_fp_p = 0;
2952 DONE;
2953}")
2954
2955(define_expand "cmpsf"
2956 [(set (cc0) (compare (match_operand:SF 0 "gen_reg_operand" "")
2957 (match_operand:SF 1 "gen_reg_operand" "")))]
2958 ""
2959 "
2960{
2961 rs6000_compare_op0 = operands[0];
2962 rs6000_compare_op1 = operands[1];
2963 rs6000_compare_fp_p = 1;
2964 DONE;
2965}")
2966
2967(define_expand "cmpdf"
2968 [(set (cc0) (compare (match_operand:DF 0 "gen_reg_operand" "")
2969 (match_operand:DF 1 "gen_reg_operand" "")))]
2970 ""
2971 "
2972{
2973 rs6000_compare_op0 = operands[0];
2974 rs6000_compare_op1 = operands[1];
2975 rs6000_compare_fp_p = 1;
2976 DONE;
2977}")
2978
2979(define_expand "beq"
2980 [(set (match_dup 2) (match_dup 1))
2981 (set (pc)
2982 (if_then_else (eq (match_dup 2)
2983 (const_int 0))
2984 (label_ref (match_operand 0 "" ""))
2985 (pc)))]
2986 ""
2987 "
2988{ enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
2989 operands[1] = gen_rtx (COMPARE, mode,
2990 rs6000_compare_op0, rs6000_compare_op1);
2991 operands[2] = gen_reg_rtx (mode);
2992}")
2993
2994(define_expand "bne"
2995 [(set (match_dup 2) (match_dup 1))
2996 (set (pc)
2997 (if_then_else (ne (match_dup 2)
2998 (const_int 0))
2999 (label_ref (match_operand 0 "" ""))
3000 (pc)))]
3001 ""
3002 "
3003{ enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
3004 operands[1] = gen_rtx (COMPARE, mode,
3005 rs6000_compare_op0, rs6000_compare_op1);
3006 operands[2] = gen_reg_rtx (mode);
3007}")
3008
3009(define_expand "blt"
3010 [(set (match_dup 2) (match_dup 1))
3011 (set (pc)
3012 (if_then_else (lt (match_dup 2)
3013 (const_int 0))
3014 (label_ref (match_operand 0 "" ""))
3015 (pc)))]
3016 ""
3017 "
3018{ enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
3019 operands[1] = gen_rtx (COMPARE, mode,
3020 rs6000_compare_op0, rs6000_compare_op1);
3021 operands[2] = gen_reg_rtx (mode);
3022}")
3023
3024(define_expand "bgt"
3025 [(set (match_dup 2) (match_dup 1))
3026 (set (pc)
3027 (if_then_else (gt (match_dup 2)
3028 (const_int 0))
3029 (label_ref (match_operand 0 "" ""))
3030 (pc)))]
3031 ""
3032 "
3033{ enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
3034 operands[1] = gen_rtx (COMPARE, mode,
3035 rs6000_compare_op0, rs6000_compare_op1);
3036 operands[2] = gen_reg_rtx (mode);
3037}")
3038
3039(define_expand "ble"
3040 [(set (match_dup 2) (match_dup 1))
3041 (set (pc)
3042 (if_then_else (le (match_dup 2)
3043 (const_int 0))
3044 (label_ref (match_operand 0 "" ""))
3045 (pc)))]
3046 ""
3047 "
3048{ enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
3049 operands[1] = gen_rtx (COMPARE, mode,
3050 rs6000_compare_op0, rs6000_compare_op1);
3051 operands[2] = gen_reg_rtx (mode);
3052}")
3053
3054(define_expand "bge"
3055 [(set (match_dup 2) (match_dup 1))
3056 (set (pc)
3057 (if_then_else (ge (match_dup 2)
3058 (const_int 0))
3059 (label_ref (match_operand 0 "" ""))
3060 (pc)))]
3061 ""
3062 "
3063{ enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
3064 operands[1] = gen_rtx (COMPARE, mode,
3065 rs6000_compare_op0, rs6000_compare_op1);
3066 operands[2] = gen_reg_rtx (mode);
3067}")
3068
3069(define_expand "bgtu"
3070 [(set (match_dup 2) (match_dup 1))
3071 (set (pc)
3072 (if_then_else (gtu (match_dup 2)
3073 (const_int 0))
3074 (label_ref (match_operand 0 "" ""))
3075 (pc)))]
3076 ""
3077 "
3078{ operands[1] = gen_rtx (COMPARE, CCUNSmode,
3079 rs6000_compare_op0, rs6000_compare_op1);
3080 operands[2] = gen_reg_rtx (CCUNSmode);
3081}")
3082
3083(define_expand "bltu"
3084 [(set (match_dup 2) (match_dup 1))
3085 (set (pc)
3086 (if_then_else (ltu (match_dup 2)
3087 (const_int 0))
3088 (label_ref (match_operand 0 "" ""))
3089 (pc)))]
3090 ""
3091 "
3092{ operands[1] = gen_rtx (COMPARE, CCUNSmode,
3093 rs6000_compare_op0, rs6000_compare_op1);
3094 operands[2] = gen_reg_rtx (CCUNSmode);
3095}")
3096
3097(define_expand "bgeu"
3098 [(set (match_dup 2) (match_dup 1))
3099 (set (pc)
3100 (if_then_else (geu (match_dup 2)
3101 (const_int 0))
3102 (label_ref (match_operand 0 "" ""))
3103 (pc)))]
3104 ""
3105 "
3106{ operands[1] = gen_rtx (COMPARE, CCUNSmode,
3107 rs6000_compare_op0, rs6000_compare_op1);
3108 operands[2] = gen_reg_rtx (CCUNSmode);
3109}")
3110
3111(define_expand "bleu"
3112 [(set (match_dup 2) (match_dup 1))
3113 (set (pc)
3114 (if_then_else (leu (match_dup 2)
3115 (const_int 0))
3116 (label_ref (match_operand 0 "" ""))
3117 (pc)))]
3118 ""
3119 "
3120{ operands[1] = gen_rtx (COMPARE, CCUNSmode,
3121 rs6000_compare_op0, rs6000_compare_op1);
3122 operands[2] = gen_reg_rtx (CCUNSmode);
3123}")
3124
3125;; For SNE, we would prefer that the xor/abs sequence be used for integers.
3126;; For SEQ, likewise, except that comparisons with zero should be done
3127;; with an scc insns. However, due to the order that combine see the
3128;; resulting insns, we must, in fact, allow SEQ for integers. Fail in
3129;; the cases we don't want to handle.
3130(define_expand "seq"
3131 [(set (match_dup 2) (match_dup 1))
3132 (set (match_operand:SI 0 "gen_reg_operand" "")
3133 (eq:SI (match_dup 2) (const_int 0)))]
3134 ""
3135 "
3136{ enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
3137 operands[1] = gen_rtx (COMPARE, mode,
3138 rs6000_compare_op0, rs6000_compare_op1);
3139 operands[2] = gen_reg_rtx (mode);
3140}")
3141
3142(define_expand "sne"
3143 [(set (match_dup 2) (match_dup 1))
3144 (set (match_operand:SI 0 "gen_reg_operand" "")
3145 (ne:SI (match_dup 2) (const_int 0)))]
3146 ""
3147 "
3148{ if (! rs6000_compare_fp_p)
3149 FAIL;
3150
3151 operands[1] = gen_rtx (COMPARE, CCFPmode,
3152 rs6000_compare_op0, rs6000_compare_op1);
3153 operands[2] = gen_reg_rtx (CCFPmode);
3154}")
3155
3156;; A > 0 is best done using the portable sequence, so fail in that case.
3157(define_expand "sgt"
3158 [(set (match_dup 2) (match_dup 1))
3159 (set (match_operand:SI 0 "gen_reg_operand" "")
3160 (gt:SI (match_dup 2) (const_int 0)))]
3161 ""
3162 "
3163{ enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
3164
3165 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
3166 FAIL;
3167
3168 operands[1] = gen_rtx (COMPARE, mode,
3169 rs6000_compare_op0, rs6000_compare_op1);
3170 operands[2] = gen_reg_rtx (mode);
3171}")
3172
3173;; A < 0 is best done in the portable way for A an integer.
3174(define_expand "slt"
3175 [(set (match_dup 2) (match_dup 1))
3176 (set (match_operand:SI 0 "gen_reg_operand" "")
3177 (lt:SI (match_dup 2) (const_int 0)))]
3178 ""
3179 "
3180{ enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
3181
3182 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
3183 FAIL;
3184
3185 operands[1] = gen_rtx (COMPARE, mode,
3186 rs6000_compare_op0, rs6000_compare_op1);
3187 operands[2] = gen_reg_rtx (mode);
3188}")
3189
3190(define_expand "sge"
3191 [(set (match_dup 2) (match_dup 1))
3192 (set (match_operand:SI 0 "gen_reg_operand" "")
3193 (ge:SI (match_dup 2) (const_int 0)))]
3194 ""
3195 "
3196{ enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
3197 operands[1] = gen_rtx (COMPARE, mode,
3198 rs6000_compare_op0, rs6000_compare_op1);
3199 operands[2] = gen_reg_rtx (mode);
3200}")
3201
3202;; A <= 0 is best done the portable way for A an integer.
3203(define_expand "sle"
3204 [(set (match_dup 2) (match_dup 1))
3205 (set (match_operand:SI 0 "gen_reg_operand" "")
3206 (le:SI (match_dup 2) (const_int 0)))]
3207 ""
3208 "
3209{ enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
3210
3211 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
3212 FAIL;
3213
3214 operands[1] = gen_rtx (COMPARE, mode,
3215 rs6000_compare_op0, rs6000_compare_op1);
3216 operands[2] = gen_reg_rtx (mode);
3217}")
3218
3219(define_expand "sgtu"
3220 [(set (match_dup 2) (match_dup 1))
3221 (set (match_operand:SI 0 "gen_reg_operand" "")
3222 (gtu:SI (match_dup 2) (const_int 0)))]
3223 ""
3224 "
3225{ operands[1] = gen_rtx (COMPARE, CCUNSmode,
3226 rs6000_compare_op0, rs6000_compare_op1);
3227 operands[2] = gen_reg_rtx (CCUNSmode);
3228}")
3229
3230(define_expand "sltu"
3231 [(set (match_dup 2) (match_dup 1))
3232 (set (match_operand:SI 0 "gen_reg_operand" "")
3233 (ltu:SI (match_dup 2) (const_int 0)))]
3234 ""
3235 "
3236{ operands[1] = gen_rtx (COMPARE, CCUNSmode,
3237 rs6000_compare_op0, rs6000_compare_op1);
3238 operands[2] = gen_reg_rtx (CCUNSmode);
3239}")
3240
3241(define_expand "sgeu"
3242 [(set (match_dup 2) (match_dup 1))
3243 (set (match_operand:SI 0 "gen_reg_operand" "")
3244 (geu:SI (match_dup 2) (const_int 0)))]
3245 ""
3246 "
3247{ operands[1] = gen_rtx (COMPARE, CCUNSmode,
3248 rs6000_compare_op0, rs6000_compare_op1);
3249 operands[2] = gen_reg_rtx (CCUNSmode);
3250}")
3251
3252(define_expand "sleu"
3253 [(set (match_dup 2) (match_dup 1))
3254 (set (match_operand:SI 0 "gen_reg_operand" "")
3255 (leu:SI (match_dup 2) (const_int 0)))]
3256 ""
3257 "
3258{ operands[1] = gen_rtx (COMPARE, CCUNSmode,
3259 rs6000_compare_op0, rs6000_compare_op1);
3260 operands[2] = gen_reg_rtx (CCUNSmode);
3261}")
3262\f
3263;; Here are the actual compare insns.
3264(define_insn ""
3265 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
3266 (compare:CC (match_operand:SI 1 "gen_reg_operand" "r")
3267 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
3268 ""
3269 "cmp%I2 %0,%1,%2"
3270 [(set_attr "type" "compare")])
3271
f357808b
RK		 3272;; If we are comparing a register for equality with a large constant,
3273;; we can do this with an XOR followed by a compare. But we need a scratch
3274;; register for the result of the XOR.
3275
3276(define_split
3277 [(set (match_operand:CC 0 "cc_reg_operand" "")
3278 (compare:CC (match_operand:SI 1 "gen_reg_operand" "")
3279 (match_operand:SI 2 "non_short_cint_operand" "")))
3280 (clobber (match_operand:SI 3 "gen_reg_operand" ""))]
3281 "find_single_use (operands[0], insn, 0)
3282 && (GET_CODE (*find_single_use (operands[0], insn, 0)) == EQ
3283 || GET_CODE (*find_single_use (operands[0], insn, 0)) == NE)"
3284 [(set (match_dup 3) (xor:SI (match_dup 1) (match_dup 4)))
3285 (set (match_dup 0) (compare:CC (match_dup 3) (match_dup 5)))]
3286 "
3287{
3288 /* Get the constant we are comparing against, C, and see what it looks like
3289 sign-extended to 16 bits. Then see what constant could be XOR'ed
3290 with C to get the sign-extended value. */
3291
3292 int c = INTVAL (operands[2]);
3293 int sextc = (c << 16) >> 16;
3294 int xorv = c ^ sextc;
3295
3296 operands[4] = gen_rtx (CONST_INT, VOIDmode, xorv);
3297 operands[5] = gen_rtx (CONST_INT, VOIDmode, sextc);
3298}")
3299
1fd4e8c1
RK		 3300(define_insn ""
3301 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
3302 (compare:CCUNS (match_operand:SI 1 "gen_reg_operand" "r")
3303 (match_operand:SI 2 "reg_or_u_short_operand" "rI")))]
3304 ""
3305 "cmpl%I2 %0,%1,%W2"
3306 [(set_attr "type" "compare")])
3307
3308;; The following two insns don't exist as single insns, but if we provide
3309;; them, we can swap an add and compare, which will enable us to overlap more
3310;; of the required delay between a compare and branch. We generate code for
3311;; them by splitting.
3312
3313(define_insn ""
3314 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
3315 (compare:CC (match_operand:SI 1 "gen_reg_operand" "r")
3316 (match_operand:SI 2 "short_cint_operand" "i")))
3317 (set (match_operand:SI 0 "gen_reg_operand" "=r")
3318 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
3319 ""
3320 "#")
3321
3322(define_insn ""
3323 [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y")
3324 (compare:CCUNS (match_operand:SI 1 "gen_reg_operand" "r")
3325 (match_operand:SI 2 "u_short_cint_operand" "i")))
3326 (set (match_operand:SI 0 "gen_reg_operand" "=r")
3327 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
3328 ""
3329 "#")
3330
3331(define_split
3332 [(set (match_operand:CC 3 "cc_reg_operand" "")
3333 (compare:CC (match_operand:SI 1 "gen_reg_operand" "")
3334 (match_operand:SI 2 "short_cint_operand" "")))
3335 (set (match_operand:SI 0 "gen_reg_operand" "")
3336 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
3337 ""
3338 [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2)))
3339 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
3340
3341(define_split
3342 [(set (match_operand:CCUNS 3 "cc_reg_operand" "")
3343 (compare:CCUNS (match_operand:SI 1 "gen_reg_operand" "")
3344 (match_operand:SI 2 "u_short_cint_operand" "")))
3345 (set (match_operand:SI 0 "gen_reg_operand" "")
3346 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
3347 ""
3348 [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2)))
3349 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
3350
3351(define_insn ""
3352 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
3353 (compare:CCFP (match_operand:SF 1 "gen_reg_operand" "f")
3354 (match_operand:SF 2 "gen_reg_operand" "f")))]
3355 ""
3356 "fcmpu %0,%1,%2"
3357 [(set_attr "type" "fpcompare")])
3358
3359(define_insn ""
3360 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
3361 (compare:CCFP (match_operand:DF 1 "gen_reg_operand" "f")
3362 (match_operand:DF 2 "gen_reg_operand" "f")))]
3363 ""
3364 "fcmpu %0,%1,%2"
3365 [(set_attr "type" "fpcompare")])
3366\f
3367;; Now we have the scc insns. We can do some combinations because of the
3368;; way the machine works.
3369;;
3370;; Note that this is probably faster if we can put an insn between the
c5defebb
RK		 3371;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most
3372;; cases the insns below which don't use an intermediate CR field will
3373;; be used instead.
1fd4e8c1
RK		 3374(define_insn ""
3375 [(set (match_operand:SI 0 "gen_reg_operand" "=r")
3376 (match_operator:SI 1 "scc_comparison_operator"
3377 [(match_operand 2 "cc_reg_operand" "y")
3378 (const_int 0)]))]
3379 ""
3380 "%D1mfcr %0\;rlinm %0,%0,%J1,31,31")
3381
3382(define_insn ""
3383 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
3384 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
3385 [(match_operand 2 "cc_reg_operand" "y")
3386 (const_int 0)])
3387 (const_int 0)))
3388 (set (match_operand:SI 3 "gen_reg_operand" "=r")
3389 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
3390 ""
3391 "%D1mfcr %3\;rlinm. %3,%3,%J1,30,31"
3392 [(set_attr "type" "delayed_compare")])
3393
3394(define_insn ""
3395 [(set (match_operand:SI 0 "gen_reg_operand" "=r")
3396 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
3397 [(match_operand 2 "cc_reg_operand" "y")
3398 (const_int 0)])
3399 (match_operand:SI 3 "const_int_operand" "n")))]
3400 ""
3401 "*
3402{
3403 int is_bit = ccr_bit (operands[1], 1);
3404 int put_bit = 31 - (INTVAL (operands[3]) & 31);
3405 int count;
3406
3407 if (is_bit >= put_bit)
3408 count = is_bit - put_bit;
3409 else
3410 count = 32 - (put_bit - is_bit);
3411
3412 operands[4] = gen_rtx (CONST_INT, VOIDmode, count);
3413 operands[5] = gen_rtx (CONST_INT, VOIDmode, put_bit);
3414
3415 return \"%D1mfcr %0\;rlinm %0,%0,%4,%5,%5\";
3416}")
3417
3418(define_insn ""
3419 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
3420 (compare:CC
3421 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
3422 [(match_operand 2 "cc_reg_operand" "y")
3423 (const_int 0)])
3424 (match_operand:SI 3 "const_int_operand" "n"))
3425 (const_int 0)))
3426 (set (match_operand:SI 4 "gen_reg_operand" "=r")
3427 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
3428 (match_dup 3)))]
3429 ""
3430 "*
3431{
3432 int is_bit = ccr_bit (operands[1], 1);
3433 int put_bit = 31 - (INTVAL (operands[3]) & 31);
3434 int count;
3435
3436 if (is_bit >= put_bit)
3437 count = is_bit - put_bit;
3438 else
3439 count = 32 - (put_bit - is_bit);
3440
3441 operands[5] = gen_rtx (CONST_INT, VOIDmode, count);
3442 operands[6] = gen_rtx (CONST_INT, VOIDmode, put_bit);
3443
3444 return \"%D1mfcr %4\;rlinm. %4,%4,%5,%6,%6\";
3445}"
3446 [(set_attr "type" "delayed_compare")])
3447
c5defebb
RK		 3448;; If we are comparing the result of two comparisons, this can be done
3449;; using creqv or crxor.
3450
3451(define_insn ""
3452 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
3453 (compare:CCEQ (match_operator 1 "scc_comparison_operator"
3454 [(match_operand 2 "cc_reg_operand" "y")
3455 (const_int 0)])
3456 (match_operator 3 "scc_comparison_operator"
3457 [(match_operand 4 "cc_reg_operand" "y")
3458 (const_int 0)])))]
3459 "REGNO (operands[2]) != REGNO (operands[4])"
3460 "*
3461{
3462 enum rtx_code code1, code2;
3463
3464 code1 = GET_CODE (operands[1]);
3465 code2 = GET_CODE (operands[3]);
3466
3467 if ((code1 == EQ || code1 == LT || code1 == GT
3468 || code1 == LTU || code1 == GTU
3469 || (code1 != NE && GET_MODE (operands[2]) == CCFPmode))
3470 !=
3471 (code2 == EQ || code2 == LT || code2 == GT
3472 || code2 == LTU || code2 == GTU
3473 || (code2 != NE && GET_MODE (operands[4]) == CCFPmode)))
3474 return \"%C1%C3crxor %E0,%j1,%j3\";
3475 else
3476 return \"%C1%C3creqv %E0,%j1,%j3\";
3477}")
3478
3479;; There is a 3 cycle delay between consecutive mfcr instructions
3480;; so it is useful to combine 2 scc instructions to use only one mfcr.
3481
3482(define_peephole
3483 [(set (match_operand:SI 0 "gen_reg_operand" "=r")
3484 (match_operator:SI 1 "scc_comparison_operator"
3485 [(match_operand 2 "cc_reg_operand" "y")
3486 (const_int 0)]))
3487 (set (match_operand:SI 3 "gen_reg_operand" "=r")
3488 (match_operator:SI 4 "scc_comparison_operator"
3489 [(match_operand 5 "cc_reg_operand" "y")
3490 (const_int 0)]))]
3491 "REGNO (operands[2]) != REGNO (operands[5])"
3492 "%D1%D4mfcr %3\;rlinm %0,%3,%J1,31,31\;rlinm %3,%3,%J4,31,31")
3493
1fd4e8c1
RK		 3494;; There are some scc insns that can be done directly, without a compare.
3495;; These are faster because they don't involve the communications between
3496;; the FXU and branch units. In fact, we will be replacing all of the
3497;; integer scc insns here or in the portable methods in emit_store_flag.
3498;;
3499;; Also support (neg (scc ..)) since that construct is used to replace
3500;; branches, (plus (scc ..) ..) since that construct is common and
3501;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the
3502;; cases where it is no more expensive than (neg (scc ..)).
3503
3504;; Have reload force a constant into a register for the simple insns that
3505;; otherwise won't accept constants. We do this because it is faster than
3506;; the cmp/mfcr sequence we would otherwise generate.
3507
3508(define_insn ""
3509 [(set (match_operand:SI 0 "gen_reg_operand" "=r,r,r,r,r")
3510 (eq:SI (match_operand:SI 1 "gen_reg_operand" "%r,r,r,r,r")
3511 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I")))
3512 (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))]
3513 ""
3514 "@
3515 xor %0,%1,%2\;sfi %3,%0,0\;ae %0,%3,%0
3516 sfi %3,%1,0\;ae %0,%3,%1
3517 xoril %0,%1,%b2\;sfi %3,%0,0\;ae %0,%3,%0
3518 xoriu %0,%1,%u2\;sfi %3,%0,0\;ae %0,%3,%0
3519 sfi %0,%1,%2\;sfi %3,%0,0\;ae %0,%3,%0")
3520
3521(define_insn ""
3522 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x")
3523 (compare:CC
3524 (eq:SI (match_operand:SI 1 "gen_reg_operand" "%r,r,r,r,r")
3525 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I"))
3526 (const_int 0)))
3527 (set (match_operand:SI 0 "gen_reg_operand" "=r,r,r,r,r")
3528 (eq:SI (match_dup 1) (match_dup 2)))
3529 (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))]
3530 ""
3531 "@
3532 xor %0,%1,%2\;sfi %3,%0,0\;ae. %0,%3,%0
3533 sfi %3,%1,0\;ae. %0,%3,%1
3534 xoril %0,%1,%b2\;sfi %3,%0,0\;ae. %0,%3,%0
3535 xoriu %0,%1,%u2\;sfi %3,%0,0\;ae. %0,%3,%0
3536 sfi %0,%1,%2\;sfi %3,%0,0\;ae. %0,%3,%0"
3537 [(set_attr "type" "compare")])
3538
3539(define_insn ""
3540 [(set (match_operand:SI 0 "gen_reg_operand" "=r,r,r,r,r")
3541 (plus:SI (eq:SI (match_operand:SI 1 "gen_reg_operand" "%r,r,r,r,r")
3542 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I"))
3543 (match_operand:SI 3 "gen_reg_operand" "r,r,r,r,r")))
3544 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r"))]
3545 ""
3546 "@
3547 xor %4,%1,%2\;sfi %4,%4,0\;aze %0,%3
3548 sfi %4,%1,0\;aze %0,%3
3549 xoril %4,%1,%b2\;sfi %4,%4,0\;aze %0,%3
3550 xoriu %4,%1,%u2\;sfi %4,%4,0\;aze %0,%3
3551 sfi %4,%1,%2\;sfi %4,%4,0\;aze %0,%3")
3552
3553(define_insn ""
3554 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x")
3555 (compare:CC
3556 (plus:SI
3557 (eq:SI (match_operand:SI 1 "gen_reg_operand" "%r,r,r,r,r")
3558 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I"))
3559 (match_operand:SI 3 "gen_reg_operand" "r,r,r,r,r"))
3560 (const_int 0)))
3561 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r"))]
3562 ""
3563 "@
3564 xor %4,%1,%2\;sfi %4,%4,0\;aze. %4,%3
3565 sfi %4,%1,0\;aze. %0,%3
3566 xoril %4,%1,%b2\;sfi %4,%4,0\;aze. %4,%3
3567 xoriu %4,%1,%u2\;sfi %4,%4,0\;aze. %4,%3
3568 sfi %4,%1,%2\;sfi %4,%4,0\;aze. %4,%3"
3569 [(set_attr "type" "compare")])
3570
3571(define_insn ""
3572 [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,x,x,x")
3573 (compare:CC
3574 (plus:SI
3575 (eq:SI (match_operand:SI 1 "gen_reg_operand" "%r,r,r,r,r")
3576 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I"))
3577 (match_operand:SI 3 "gen_reg_operand" "r,r,r,r,r"))
3578 (const_int 0)))
3579 (set (match_operand:SI 0 "gen_reg_operand" "=r,r,r,r,r")
3580 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
3581 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r"))]
3582 ""
3583 "@
3584 xor %4,%1,%2\;sfi %4,%4,0\;aze. %0,%3
3585 sfi %4,%1,0\;aze. %4,%3
3586 xoril %4,%1,%b2\;sfi %4,%4,0\;aze. %0,%3
3587 xoriu %4,%1,%u2\;sfi %4,%4,0\;aze. %0,%3
3588 sfi %4,%1,%2\;sfi %4,%4,0\;aze. %0,%3"
3589 [(set_attr "type" "compare")])
3590
3591(define_insn ""
3592 [(set (match_operand:SI 0 "gen_reg_operand" "=r,r,r,r,r")
3593 (neg:SI (eq:SI (match_operand:SI 1 "gen_reg_operand" "r,r,r,r,r")
3594 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I"))))]
3595 ""
3596 "@
3597 xor %0,%1,%2\;ai %0,%0,-1\;sfe %0,%0,%0
3598 ai %0,%1,-1\;sfe %0,%0,%0
3599 xoril %0,%1,%b2\;ai %0,%0,-1\;sfe %0,%0,%0
3600 xoriu %0,%1,%u2\;ai %0,%0,-1\;sfe %0,%0,%0
3601 sfi %0,%1,%2\;ai %0,%0,-1\;sfe %0,%0,%0")
3602
3603;; This is what (plus (ne X (const_int 0)) Y) looks like.
3604(define_insn ""
3605 [(set (match_operand:SI 0 "gen_reg_operand" "=r")
3606 (plus:SI (lshiftrt:SI
3607 (neg:SI (abs:SI (match_operand:SI 1 "gen_reg_operand" "r")))
3608 (const_int 31))
3609 (match_operand:SI 2 "gen_reg_operand" "r")))
3610 (clobber (match_scratch:SI 3 "=&r"))]
3611 ""
3612 "ai %3,%1,-1\;aze %0,%2")
3613
3614(define_insn ""
3615 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
3616 (compare:CC
3617 (plus:SI (lshiftrt:SI
3618 (neg:SI (abs:SI (match_operand:SI 1 "gen_reg_operand" "r")))
3619 (const_int 31))
3620 (match_operand:SI 2 "gen_reg_operand" "r"))
3621 (const_int 0)))
3622 (clobber (match_scratch:SI 3 "=&r"))]
3623 ""
3624 "ai %3,%1,-1\;aze. %3,%2"
3625 [(set_attr "type" "compare")])
3626
3627(define_insn ""
3628 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
3629 (compare:CC
3630 (plus:SI (lshiftrt:SI
3631 (neg:SI (abs:SI (match_operand:SI 1 "gen_reg_operand" "r")))
3632 (const_int 31))
3633 (match_operand:SI 2 "gen_reg_operand" "r"))
3634 (const_int 0)))
3635 (set (match_operand:SI 0 "gen_reg_operand" "=r")
3636 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
3637 (match_dup 2)))
3638 (clobber (match_scratch:SI 3 "=&r"))]
3639 ""
3640 "ai %3,%1,-1\;aze. %0,%2"
3641 [(set_attr "type" "compare")])
3642
3643(define_insn ""
3644 [(set (match_operand:SI 0 "gen_reg_operand" "=r,r")
3645 (le:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
3646 (match_operand:SI 2 "reg_or_short_operand" "r,O")))
3647 (clobber (match_scratch:SI 3 "=r,X"))]
3648 ""
3649 "@
3650 doz %3,%2,%1\;sfi %0,%3,0\;ae %0,%0,%3
3651 ai %0,%1,-1\;aze %0,%0\;sri %0,%0,31")
3652
3653(define_insn ""
3654 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x")
3655 (compare:CC
3656 (le:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
3657 (match_operand:SI 2 "reg_or_short_operand" "r,O"))
3658 (const_int 0)))
3659 (set (match_operand:SI 0 "gen_reg_operand" "=r,r")
3660 (le:SI (match_dup 1) (match_dup 2)))
3661 (clobber (match_scratch:SI 3 "=r,X"))]
3662 ""
3663 "@
3664 doz %3,%2,%1\;sfi %0,%3,0\;ae. %0,%0,%3
3665 ai %0,%1,-1\;aze %0,%0\;sri. %0,%0,31"
3666 [(set_attr "type" "delayed_compare,compare")])
3667
3668(define_insn ""
3669 [(set (match_operand:SI 0 "gen_reg_operand" "=r,r")
3670 (plus:SI (le:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
3671 (match_operand:SI 2 "reg_or_short_operand" "r,O"))
3672 (match_operand:SI 3 "gen_reg_operand" "r,r")))
3673 (clobber (match_scratch:SI 4 "=&r,&r"))]
3674 ""
3675 "@
3676 doz %4,%2,%1\;sfi %4,%4,0\;aze %0,%3
3677 srai %4,%1,31\;sf %4,%1,%4\;aze %0,%3")
3678
3679(define_insn ""
3680 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
3681 (compare:CC
3682 (plus:SI (le:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
3683 (match_operand:SI 2 "reg_or_short_operand" "r,O"))
3684 (match_operand:SI 3 "gen_reg_operand" "r,r"))
3685 (const_int 0)))
3686 (clobber (match_scratch:SI 4 "=&r,&r"))]
3687 ""
3688 "@
3689 doz %4,%2,%1\;sfi %4,%4,0\;aze. %4,%3
3690 srai %4,%1,31\;sf %4,%1,%4\;aze. %4,%3"
3691 [(set_attr "type" "compare")])
3692
3693(define_insn ""
3694 [(set (match_operand:CC 5 "cc_reg_operand" "=x,x")
3695 (compare:CC
3696 (plus:SI (le:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
3697 (match_operand:SI 2 "reg_or_short_operand" "r,O"))
3698 (match_operand:SI 3 "gen_reg_operand" "r,r"))
3699 (const_int 0)))
3700 (set (match_operand:SI 0 "gen_reg_operand" "=r,r")
3701 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
3702 (clobber (match_scratch:SI 4 "=&r,&r"))]
3703 ""
3704 "@
3705 doz %4,%2,%1\;sfi %4,%4,0\;aze. %0,%3
3706 srai %4,%1,31\;sf %4,%1,%4\;aze. %0,%3"
3707 [(set_attr "type" "compare")])
3708
3709(define_insn ""
3710 [(set (match_operand:SI 0 "gen_reg_operand" "=r,r")
3711 (neg:SI (le:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
3712 (match_operand:SI 2 "reg_or_short_operand" "r,O"))))]
3713 ""
3714 "@
3715 doz %0,%2,%1\;ai %0,%0,-1\;sfe %0,%0,%0
3716 ai %0,%1,-1\;aze %0,%0\;srai %0,%0,31")
3717
3718(define_insn ""
3719 [(set (match_operand:SI 0 "gen_reg_operand" "=r")
3720 (leu:SI (match_operand:SI 1 "gen_reg_operand" "r")
3721 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
3722 ""
3723 "sf%I2 %0,%1,%2\;cal %0,0(0)\;ae %0,%0,%0")
3724
3725(define_insn ""
3726 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
3727 (compare:CC
3728 (leu:SI (match_operand:SI 1 "gen_reg_operand" "r")
3729 (match_operand:SI 2 "reg_or_short_operand" "rI"))
3730 (const_int 0)))
3731 (set (match_operand:SI 0 "gen_reg_operand" "=r")
3732 (leu:SI (match_dup 1) (match_dup 2)))]
3733 ""
3734 "sf%I2 %0,%1,%2\;cal %0,0(0)\;ae. %0,%0,%0"
3735 [(set_attr "type" "compare")])
3736
3737(define_insn ""
3738 [(set (match_operand:SI 0 "gen_reg_operand" "=r")
3739 (plus:SI (leu:SI (match_operand:SI 1 "gen_reg_operand" "r")
3740 (match_operand:SI 2 "reg_or_short_operand" "rI"))
3741 (match_operand:SI 3 "gen_reg_operand" "r")))
3742 (clobber (match_scratch:SI 4 "=&r"))]
3743 ""
3744 "sf%I2 %4,%1,%2\;aze %0,%3")
3745
3746(define_insn ""
3747 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
3748 (compare:CC
3749 (plus:SI (leu:SI (match_operand:SI 1 "gen_reg_operand" "r")
3750 (match_operand:SI 2 "reg_or_short_operand" "rI"))
3751 (match_operand:SI 3 "gen_reg_operand" "r"))
3752 (const_int 0)))
3753 (clobber (match_scratch:SI 4 "=&r"))]
3754 ""
3755 "sf%I2 %4,%1,%2\;aze. %4,%3"
3756 [(set_attr "type" "compare")])
3757
3758(define_insn ""
3759 [(set (match_operand:CC 5 "cc_reg_operand" "=x")
3760 (compare:CC
3761 (plus:SI (leu:SI (match_operand:SI 1 "gen_reg_operand" "r")
3762 (match_operand:SI 2 "reg_or_short_operand" "rI"))
3763 (match_operand:SI 3 "gen_reg_operand" "r"))
3764 (const_int 0)))
3765 (set (match_operand:SI 0 "gen_reg_operand" "=r")
3766 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
3767 (clobber (match_scratch:SI 4 "=&r"))]
3768 ""
3769 "sf%I2 %4,%1,%2\;aze. %0,%3"
3770 [(set_attr "type" "compare")])
3771
3772(define_insn ""
3773 [(set (match_operand:SI 0 "gen_reg_operand" "=r")
3774 (neg:SI (leu:SI (match_operand:SI 1 "gen_reg_operand" "r")
3775 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
3776 ""
3777 "sf%I2 %0,%1,%2\;sfe %0,%0,%0\;nand %0,%0,%0")
3778
3779(define_insn ""
3780 [(set (match_operand:SI 0 "gen_reg_operand" "=r")
3781 (and:SI (neg:SI
3782 (leu:SI (match_operand:SI 1 "gen_reg_operand" "r")
3783 (match_operand:SI 2 "reg_or_short_operand" "rI")))
3784 (match_operand:SI 3 "gen_reg_operand" "r")))
3785 (clobber (match_scratch:SI 4 "=&r"))]
3786 ""
3787 "sf%I2 %4,%1,%2\;sfe %4,%4,%4\;andc %0,%3,%4")
3788
3789(define_insn ""
3790 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
3791 (compare:CC
3792 (and:SI (neg:SI
3793 (leu:SI (match_operand:SI 1 "gen_reg_operand" "r")
3794 (match_operand:SI 2 "reg_or_short_operand" "rI")))
3795 (match_operand:SI 3 "gen_reg_operand" "r"))
3796 (const_int 0)))
3797 (clobber (match_scratch:SI 4 "=&r"))]
3798 ""
3799 "sf%I2 %4,%1,%2\;sfe %4,%4,%4\;andc. %4,%3,%4"
3800 [(set_attr "type" "compare")])
3801
3802(define_insn ""
3803 [(set (match_operand:CC 5 "cc_reg_operand" "=x")
3804 (compare:CC
3805 (and:SI (neg:SI
3806 (leu:SI (match_operand:SI 1 "gen_reg_operand" "r")
3807 (match_operand:SI 2 "reg_or_short_operand" "rI")))
3808 (match_operand:SI 3 "gen_reg_operand" "r"))
3809 (const_int 0)))
3810 (set (match_operand:SI 0 "gen_reg_operand" "=r")
3811 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
3812 (clobber (match_scratch:SI 4 "=&r"))]
3813 ""
3814 "sf%I2 %4,%1,%2\;sfe %4,%4,%4\;andc. %0,%3,%4"
3815 [(set_attr "type" "compare")])
3816
3817(define_insn ""
3818 [(set (match_operand:SI 0 "gen_reg_operand" "=r")
3819 (lt:SI (match_operand:SI 1 "gen_reg_operand" "r")
3820 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
3821 ""
3822 "doz%I2 %0,%1,%2\;nabs %0,%0\;sri %0,%0,31")
3823
3824(define_insn ""
3825 [(set (match_operand:SI 3 "cc_reg_operand" "=x")
3826 (compare:CC
3827 (lt:SI (match_operand:SI 1 "gen_reg_operand" "r")
3828 (match_operand:SI 2 "reg_or_short_operand" "rI"))
3829 (const_int 0)))
3830 (set (match_operand:SI 0 "gen_reg_operand" "=r")
3831 (lt:SI (match_dup 1) (match_dup 2)))]
3832 ""
3833 "doz%I2 %0,%1,%2\;nabs %0,%0\;sri. %0,%0,31"
3834 [(set_attr "type" "delayed_compare")])
3835
3836(define_insn ""
3837 [(set (match_operand:SI 0 "gen_reg_operand" "=r")
3838 (plus:SI (lt:SI (match_operand:SI 1 "gen_reg_operand" "r")
3839 (match_operand:SI 2 "reg_or_short_operand" "rI"))
3840 (match_operand:SI 3 "gen_reg_operand" "r")))
3841 (clobber (match_scratch:SI 4 "=&r"))]
3842 ""
3843 "doz%I2 %4,%1,%2\;ai %4,%4,-1\;aze %0,%3")
3844
3845(define_insn ""
3846 [(set (match_operand:SI 0 "cc_reg_operand" "=x")
3847 (compare:CC
3848 (plus:SI (lt:SI (match_operand:SI 1 "gen_reg_operand" "r")
3849 (match_operand:SI 2 "reg_or_short_operand" "rI"))
3850 (match_operand:SI 3 "gen_reg_operand" "r"))
3851 (const_int 0)))
3852 (clobber (match_scratch:SI 4 "=&r"))]
3853 ""
3854 "doz%I2 %4,%1,%2\;ai %4,%4,-1\;aze. %4,%3"
3855 [(set_attr "type" "compare")])
3856
3857(define_insn ""
3858 [(set (match_operand:SI 5 "cc_reg_operand" "=x")
3859 (compare:CC
3860 (plus:SI (lt:SI (match_operand:SI 1 "gen_reg_operand" "r")
3861 (match_operand:SI 2 "reg_or_short_operand" "rI"))
3862 (match_operand:SI 3 "gen_reg_operand" "r"))
3863 (const_int 0)))
3864 (set (match_operand:SI 0 "gen_reg_operand" "=r")
3865 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
3866 (clobber (match_scratch:SI 4 "=&r"))]
3867 ""
3868 "doz%I2 %4,%1,%2\;ai %4,%4,-1\;aze. %0,%3"
3869 [(set_attr "type" "compare")])
3870
3871(define_insn ""
3872 [(set (match_operand:SI 0 "gen_reg_operand" "=r")
3873 (neg:SI (lt:SI (match_operand:SI 1 "gen_reg_operand" "r")
3874 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
3875 ""
3876 "doz%I2 %0,%1,%2\;nabs %0,%0\;srai %0,%0,31")
3877
3878(define_insn ""
3879 [(set (match_operand:SI 0 "gen_reg_operand" "=r,r")
3880 (ltu:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
3881 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))]
3882 ""
3883 "@
3884 sf %0,%2,%1\;sfe %0,%0,%0\;neg %0,%0
3885 ai %0,%1,%n2\;sfe %0,%0,%0\;neg %0,%0")
3886
3887(define_insn ""
3888 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x")
3889 (compare:CC
3890 (ltu:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
3891 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
3892 (const_int 0)))
3893 (set (match_operand:SI 0 "gen_reg_operand" "=r,r")
3894 (ltu:SI (match_dup 1) (match_dup 2)))]
3895 ""
3896 "@
3897 sf %0,%2,%1\;sfe %0,%0,%0\;neg. %0,%0
3898 ai %0,%1,%n2\;sfe %0,%0,%0\;neg. %0,%0"
3899 [(set_attr "type" "compare")])
3900
3901(define_insn ""
3902 [(set (match_operand:SI 0 "gen_reg_operand" "=r,r,r,r")
3903 (plus:SI (ltu:SI (match_operand:SI 1 "gen_reg_operand" "r,r,r,r")
3904 (match_operand:SI 2 "reg_or_neg_short_operand" "r,r,P,P"))
3905 (match_operand:SI 3 "reg_or_short_operand" "r,I,r,I")))
3906 (clobber (match_scratch:SI 4 "=&r,r,&r,r"))]
3907 ""
3908 "@
3909 sf %4,%2,%1\;sfe %4,%4,%4\;sf%I3 %0,%4,%3
3910 sf %4,%2,%1\;sfe %4,%4,%4\;sf%I3 %0,%4,%3
3911 ai %4,%1,%n2\;sfe %4,%4,%4\;sf%I3 %0,%4,%3
3912 ai %4,%1,%n2\;sfe %4,%4,%4\;sf%I3 %0,%4,%3")
3913
3914(define_insn ""
3915 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x")
3916 (compare:CC
3917 (plus:SI (ltu:SI (match_operand:SI 1 "gen_reg_operand" "r,r,r,r")
3918 (match_operand:SI 2 "reg_or_neg_short_operand" "r,r,P,P"))
3919 (match_operand:SI 3 "reg_or_short_operand" "r,I,r,I"))
3920 (const_int 0)))
3921 (clobber (match_scratch:SI 4 "=&r,r,&r,r"))]
3922 ""
3923 "@
3924 sf %4,%2,%1\;sfe %4,%4,%4\;sf%I3. %4,%4,%3
3925 sf %4,%2,%1\;sfe %4,%4,%4\;sf%I3. %4,%4,%3
3926 ai %4,%1,%n2\;sfe %4,%4,%4\;sf%I3. %4,%4,%3
3927 ai %4,%1,%n2\;sfe %4,%4,%4\;sf%I3. %4,%4,%3"
3928 [(set_attr "type" "compare")])
3929
3930(define_insn ""
3931 [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,x,x")
3932 (compare:CC
3933 (plus:SI (ltu:SI (match_operand:SI 1 "gen_reg_operand" "r,r,r,r")
3934 (match_operand:SI 2 "reg_or_neg_short_operand" "r,r,P,P"))
3935 (match_operand:SI 3 "reg_or_short_operand" "r,I,r,I"))
3936 (const_int 0)))
3937 (set (match_operand:SI 0 "gen_reg_operand" "=r,r,r,r")
3938 (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
3939 (clobber (match_scratch:SI 4 "=&r,r,&r,r"))]
3940 ""
3941 "@
3942 sf %4,%2,%1\;sfe %4,%4,%4\;sf%I3. %0,%4,%3
3943 sf %4,%2,%1\;sfe %4,%4,%4\;sf%I3. %0,%4,%3
3944 ai %4,%1,%n2\;sfe %4,%4,%4\;sf%I3. %0,%4,%3
3945 ai %4,%1,%n2\;sfe %4,%4,%4\;sf%I3. %0,%4,%3"
3946 [(set_attr "type" "compare")])
3947
3948(define_insn ""
3949 [(set (match_operand:SI 0 "gen_reg_operand" "=r,r")
3950 (neg:SI (ltu:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
3951 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))))]
3952 ""
3953 "@
3954 sf %0,%2,%1\;sfe %0,%0,%0
3955 ai %0,%1,%n2\;sfe %0,%0,%0")
3956
3957(define_insn ""
3958 [(set (match_operand:SI 0 "gen_reg_operand" "=r")
3959 (ge:SI (match_operand:SI 1 "gen_reg_operand" "r")
3960 (match_operand:SI 2 "reg_or_short_operand" "rI")))
3961 (clobber (match_scratch:SI 3 "=r"))]
3962 ""
3963 "doz%I2 %3,%1,%2\;sfi %0,%3,0\;ae %0,%0,%3")
3964
3965(define_insn ""
3966 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
3967 (compare:CC
3968 (ge:SI (match_operand:SI 1 "gen_reg_operand" "r")
3969 (match_operand:SI 2 "reg_or_short_operand" "rI"))
3970 (const_int 0)))
3971 (set (match_operand:SI 0 "gen_reg_operand" "=r")
3972 (ge:SI (match_dup 1) (match_dup 2)))
3973 (clobber (match_scratch:SI 3 "=r"))]
3974 ""
3975 "doz%I2 %3,%1,%2\;sfi %0,%3,0\;ae. %0,%0,%3"
3976 [(set_attr "type" "compare")])
3977
3978(define_insn ""
3979 [(set (match_operand:SI 0 "gen_reg_operand" "=r")
3980 (plus:SI (ge:SI (match_operand:SI 1 "gen_reg_operand" "r")
3981 (match_operand:SI 2 "reg_or_short_operand" "rI"))
3982 (match_operand:SI 3 "gen_reg_operand" "r")))
3983 (clobber (match_scratch:SI 4 "=&r"))]
3984 ""
3985 "doz%I2 %4,%1,%2\;sfi %4,%4,0\;aze %0,%3")
3986
3987(define_insn ""
3988 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
3989 (compare:CC
3990 (plus:SI (ge:SI (match_operand:SI 1 "gen_reg_operand" "r")
3991 (match_operand:SI 2 "reg_or_short_operand" "rI"))
3992 (match_operand:SI 3 "gen_reg_operand" "r"))
3993 (const_int 0)))
3994 (clobber (match_scratch:SI 4 "=&r"))]
3995 ""
3996 "doz%I2 %4,%1,%2\;sfi %4,%4,0\;aze. %4,%3"
3997 [(set_attr "type" "compare")])
3998
3999(define_insn ""
4000 [(set (match_operand:CC 5 "cc_reg_operand" "=x")
4001 (compare:CC
4002 (plus:SI (ge:SI (match_operand:SI 1 "gen_reg_operand" "r")
4003 (match_operand:SI 2 "reg_or_short_operand" "rI"))
4004 (match_operand:SI 3 "gen_reg_operand" "r"))
4005 (const_int 0)))
4006 (set (match_operand:SI 0 "gen_reg_operand" "=r")
4007 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4008 (clobber (match_scratch:SI 4 "=&r"))]
4009 ""
4010 "doz%I2 %4,%1,%2\;sfi %4,%4,0\;aze. %0,%3"
4011 [(set_attr "type" "compare")])
4012
4013(define_insn ""
4014 [(set (match_operand:SI 0 "gen_reg_operand" "=r")
4015 (neg:SI (ge:SI (match_operand:SI 1 "gen_reg_operand" "r")
4016 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
4017 ""
4018 "doz%I2 %0,%1,%2\;ai %0,%0,-1\;sfe %0,%0,%0")
4019
4020;; This is (and (neg (ge X (const_int 0))) Y).
4021(define_insn ""
4022 [(set (match_operand:SI 0 "gen_reg_operand" "=r")
4023 (and:SI (neg:SI
4024 (lshiftrt:SI
4025 (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
4026 (const_int 31)))
4027 (match_operand:SI 2 "gen_reg_operand" "r")))
4028 (clobber (match_scratch:SI 3 "=&r"))]
4029 ""
4030 "srai %3,%1,31\;andc %0,%2,%3")
4031
4032(define_insn ""
4033 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
4034 (compare:CC
4035 (and:SI (neg:SI
4036 (lshiftrt:SI
4037 (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
4038 (const_int 31)))
4039 (match_operand:SI 2 "gen_reg_operand" "r"))
4040 (const_int 0)))
4041 (clobber (match_scratch:SI 3 "=&r"))]
4042 ""
4043 "srai %3,%1,31\;andc. %3,%2,%3"
4044 [(set_attr "type" "compare")])
4045
4046(define_insn ""
4047 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
4048 (compare:CC
4049 (and:SI (neg:SI
4050 (lshiftrt:SI
4051 (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
4052 (const_int 31)))
4053 (match_operand:SI 2 "gen_reg_operand" "r"))
4054 (const_int 0)))
4055 (set (match_operand:SI 0 "gen_reg_operand" "=r")
4056 (and:SI (neg:SI (lshiftrt:SI (not:SI (match_dup 1))
4057 (const_int 31)))
4058 (match_dup 2)))
4059 (clobber (match_scratch:SI 3 "=&r"))]
4060 ""
4061 "srai %3,%1,31\;andc. %0,%2,%3"
4062 [(set_attr "type" "compare")])
4063
4064(define_insn ""
4065 [(set (match_operand:SI 0 "gen_reg_operand" "=r,r")
4066 (geu:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
4067 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))]
4068 ""
4069 "@
4070 sf %0,%2,%1\;cal %0,0(0)\;ae %0,%0,%0
4071 ai %0,%1,%n2\;cal %0,0(0)\;ae %0,%0,%0")
4072
4073(define_insn ""
4074 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x")
4075 (compare:CC
4076 (geu:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
4077 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
4078 (const_int 0)))
4079 (set (match_operand:SI 0 "gen_reg_operand" "=r,r")
4080 (geu:SI (match_dup 1) (match_dup 2)))]
4081 ""
4082 "@
4083 sf %0,%2,%1\;cal %0,0(0)\;ae. %0,%0,%0
4084 ai %0,%1,%n2\;cal %0,0(0)\;ae. %0,%0,%0"
4085 [(set_attr "type" "compare")])
4086
4087(define_insn ""
4088 [(set (match_operand:SI 0 "gen_reg_operand" "=r,r")
4089 (plus:SI (geu:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
4090 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
4091 (match_operand:SI 3 "gen_reg_operand" "r,r")))
4092 (clobber (match_scratch:SI 4 "=&r,&r"))]
4093 ""
4094 "@
4095 sf %4,%2,%1\;aze %0,%3
4096 ai %4,%1,%n2\;aze %0,%3")
4097
4098(define_insn ""
4099 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
4100 (compare:CC
4101 (plus:SI (geu:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
4102 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
4103 (match_operand:SI 3 "gen_reg_operand" "r,r"))
4104 (const_int 0)))
4105 (clobber (match_scratch:SI 4 "=&r,&r"))]
4106 ""
4107 "@
4108 sf %4,%2,%1\;aze. %4,%3
4109 ai %4,%1,%n2\;aze. %4,%3"
4110 [(set_attr "type" "compare")])
4111
4112(define_insn ""
4113 [(set (match_operand:CC 5 "cc_reg_operand" "=x,x")
4114 (compare:CC
4115 (plus:SI (geu:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
4116 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
4117 (match_operand:SI 3 "gen_reg_operand" "r,r"))
4118 (const_int 0)))
4119 (set (match_operand:SI 0 "gen_reg_operand" "=r,r")
4120 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4121 (clobber (match_scratch:SI 4 "=&r,&r"))]
4122 ""
4123 "@
4124 sf %4,%2,%1\;aze. %0,%3
4125 ai %4,%1,%n2\;aze. %4,%3"
4126 [(set_attr "type" "compare")])
4127
4128(define_insn ""
4129 [(set (match_operand:SI 0 "gen_reg_operand" "=r,r")
4130 (neg:SI (geu:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
4131 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))]
4132 ""
4133 "@
4134 sf %0,%2,%1\;sfe %0,%0,%0\;nand %0,%0,%0
4135 sfi %0,%1,-1\;a%I2 %0,%0,%2\;sfe %0,%0,%0")
4136
4137(define_insn ""
4138 [(set (match_operand:SI 0 "gen_reg_operand" "=r,r")
4139 (and:SI (neg:SI
4140 (geu:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
4141 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))
4142 (match_operand:SI 3 "gen_reg_operand" "r,r")))
4143 (clobber (match_scratch:SI 4 "=&r,&r"))]
4144 ""
4145 "@
4146 sf %4,%2,%1\;sfe %4,%4,%4\;andc %0,%3,%4
4147 ai %4,%1,%n2\;sfe %4,%4,%4\;andc %0,%3,%4")
4148
4149(define_insn ""
4150 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
4151 (compare:CC
4152 (and:SI (neg:SI
4153 (geu:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
4154 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))
4155 (match_operand:SI 3 "gen_reg_operand" "r,r"))
4156 (const_int 0)))
4157 (clobber (match_scratch:SI 4 "=&r,&r"))]
4158 ""
4159 "@
4160 sf %4,%2,%1\;sfe %4,%4,%4\;andc. %4,%3,%4
4161 ai %4,%1,%n2\;sfe %4,%4,%4\;andc. %4,%3,%4"
4162 [(set_attr "type" "compare")])
4163
4164(define_insn ""
4165 [(set (match_operand:CC 5 "cc_reg_operand" "=x,x")
4166 (compare:CC
4167 (and:SI (neg:SI
4168 (geu:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
4169 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))
4170 (match_operand:SI 3 "gen_reg_operand" "r,r"))
4171 (const_int 0)))
4172 (set (match_operand:SI 0 "gen_reg_operand" "=r,r")
4173 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
4174 (clobber (match_scratch:SI 4 "=&r,&r"))]
4175 ""
4176 "@
4177 sf %4,%2,%1\;sfe %4,%4,%4\;andc. %0,%3,%4
4178 ai %4,%1,%n2\;sfe %4,%4,%4\;andc. %0,%3,%4"
4179 [(set_attr "type" "compare")])
4180
4181(define_insn ""
4182 [(set (match_operand:SI 0 "gen_reg_operand" "=r")
4183 (gt:SI (match_operand:SI 1 "gen_reg_operand" "r")
4184 (const_int 0)))]
4185 ""
4186 "sfi %0,%1,0\;ame %0,%0\;sri %0,%0,31")
4187
4188(define_insn ""
4189 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
4190 (compare:CC
4191 (gt:SI (match_operand:SI 1 "gen_reg_operand" "r")
4192 (const_int 0))
4193 (const_int 0)))
4194 (set (match_operand:SI 0 "gen_reg_operand" "=r")
4195 (gt:SI (match_dup 1) (const_int 0)))]
4196 ""
4197 "sfi %0,%1,0\;ame %0,%0\;sri. %0,%0,31"
4198 [(set_attr "type" "delayed_compare")])
4199
4200(define_insn ""
4201 [(set (match_operand:SI 0 "gen_reg_operand" "=r")
4202 (gt:SI (match_operand:SI 1 "gen_reg_operand" "r")
4203 (match_operand:SI 2 "reg_or_short_operand" "r")))]
4204 ""
4205 "doz %0,%2,%1\;nabs %0,%0\;sri %0,%0,31")
4206
4207(define_insn ""
4208 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
4209 (compare:CC
4210 (gt:SI (match_operand:SI 1 "gen_reg_operand" "r")
4211 (match_operand:SI 2 "reg_or_short_operand" "r"))
4212 (const_int 0)))
4213 (set (match_operand:SI 0 "gen_reg_operand" "=r")
4214 (gt:SI (match_dup 1) (match_dup 2)))]
4215 ""
4216 "doz %0,%2,%1\;nabs %0,%0\;sri. %0,%0,31"
4217 [(set_attr "type" "delayed_compare")])
4218
4219(define_insn ""
4220 [(set (match_operand:SI 0 "gen_reg_operand" "=r")
4221 (plus:SI (gt:SI (match_operand:SI 1 "gen_reg_operand" "r")
4222 (const_int 0))
4223 (match_operand:SI 2 "gen_reg_operand" "r")))
4224 (clobber (match_scratch:SI 3 "=&r"))]
4225 ""
4226 "a %3,%1,%1\;sfe %3,%1,%3\;aze %0,%2")
4227
4228(define_insn ""
4229 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
4230 (compare:CC
4231 (plus:SI (gt:SI (match_operand:SI 1 "gen_reg_operand" "r")
4232 (const_int 0))
4233 (match_operand:SI 2 "gen_reg_operand" "r"))
4234 (const_int 0)))
4235 (clobber (match_scratch:SI 3 "=&r"))]
4236 ""
4237 "a %3,%1,%1\;sfe %3,%1,%3\;aze. %0,%2"
4238 [(set_attr "type" "compare")])
4239
4240(define_insn ""
4241 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
4242 (compare:CC
4243 (plus:SI (gt:SI (match_operand:SI 1 "gen_reg_operand" "r")
4244 (const_int 0))
4245 (match_operand:SI 2 "gen_reg_operand" "r"))
4246 (const_int 0)))
4247 (set (match_operand:SI 0 "gen_reg_operand" "=r")
4248 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
4249 (clobber (match_scratch:SI 3 "=&r"))]
4250 ""
4251 "a %3,%1,%1\;sfe %3,%1,%3\;aze. %3,%2"
4252 [(set_attr "type" "compare")])
4253
4254(define_insn ""
4255 [(set (match_operand:SI 0 "gen_reg_operand" "=r")
4256 (plus:SI (gt:SI (match_operand:SI 1 "gen_reg_operand" "r")
4257 (match_operand:SI 2 "reg_or_short_operand" "r"))
4258 (match_operand:SI 3 "gen_reg_operand" "r")))
4259 (clobber (match_scratch:SI 4 "=&r"))]
4260 ""
4261 "doz %4,%2,%1\;ai %4,%4,-1\;aze %0,%3")
4262
4263(define_insn ""
4264 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
4265 (compare:CC
4266 (plus:SI (gt:SI (match_operand:SI 1 "gen_reg_operand" "r")
4267 (match_operand:SI 2 "reg_or_short_operand" "r"))
4268 (match_operand:SI 3 "gen_reg_operand" "r"))
4269 (const_int 0)))
4270 (clobber (match_scratch:SI 4 "=&r"))]
4271 ""
4272 "doz %4,%2,%1\;ai %4,%4,-1\;aze. %4,%3"
4273 [(set_attr "type" "compare")])
4274
4275(define_insn ""
4276 [(set (match_operand:CC 5 "cc_reg_operand" "=x")
4277 (compare:CC
4278 (plus:SI (gt:SI (match_operand:SI 1 "gen_reg_operand" "r")
4279 (match_operand:SI 2 "reg_or_short_operand" "r"))
4280 (match_operand:SI 3 "gen_reg_operand" "r"))
4281 (const_int 0)))
4282 (set (match_operand:SI 0 "gen_reg_operand" "=r")
4283 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4284 (clobber (match_scratch:SI 4 "=&r"))]
4285 ""
4286 "doz %4,%2,%1\;ai %4,%4,-1\;aze. %0,%3"
4287 [(set_attr "type" "compare")])
4288
4289(define_insn ""
4290 [(set (match_operand:SI 0 "gen_reg_operand" "=r")
4291 (neg:SI (gt:SI (match_operand:SI 1 "gen_reg_operand" "r")
4292 (const_int 0))))]
4293 ""
4294 "sfi %0,%1,0\;ame %0,%0\;srai %0,%0,31")
4295
4296(define_insn ""
4297 [(set (match_operand:SI 0 "gen_reg_operand" "=r")
4298 (neg:SI (gt:SI (match_operand:SI 1 "gen_reg_operand" "r")
4299 (match_operand:SI 2 "reg_or_short_operand" "r"))))]
4300 ""
4301 "doz %0,%2,%1\;nabs %0,%0\;srai %0,%0,31")
4302
4303(define_insn ""
4304 [(set (match_operand:SI 0 "gen_reg_operand" "=r")
4305 (gtu:SI (match_operand:SI 1 "gen_reg_operand" "r")
4306 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
4307 ""
4308 "sf%I2 %0,%1,%2\;sfe %0,%0,%0\;neg %0,%0")
4309
4310(define_insn ""
4311 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
4312 (compare:CC
4313 (gtu:SI (match_operand:SI 1 "gen_reg_operand" "r")
4314 (match_operand:SI 2 "reg_or_short_operand" "rI"))
4315 (const_int 0)))
4316 (set (match_operand:SI 0 "gen_reg_operand" "=r")
4317 (gtu:SI (match_dup 1) (match_dup 2)))]
4318 ""
4319 "sf%I2 %0,%1,%2\;sfe %0,%0,%0\;neg. %0,%0"
4320 [(set_attr "type" "compare")])
4321
4322(define_insn ""
4323 [(set (match_operand:SI 0 "gen_reg_operand" "=r,r")
4324 (plus:SI (gtu:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
4325 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
4326 (match_operand:SI 3 "reg_or_short_operand" "r,I")))
4327 (clobber (match_scratch:SI 4 "=&r,&r"))]
4328 ""
4329 "sf%I2 %4,%1,%2\;sfe %4,%4,%4\;sf%I3 %0,%4,%3")
4330
4331(define_insn ""
4332 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
4333 (compare:CC
4334 (plus:SI (gtu:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
4335 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
4336 (match_operand:SI 3 "reg_or_short_operand" "r,I"))
4337 (const_int 0)))
4338 (clobber (match_scratch:SI 4 "=&r,&r"))]
4339 ""
4340 "sf%I2 %4,%1,%2\;sfe %4,%4,%4\;sf%I3. %4,%4,%3"
4341 [(set_attr "type" "compare")])
4342
4343(define_insn ""
4344 [(set (match_operand:CC 5 "cc_reg_operand" "=x,x")
4345 (compare:CC
4346 (plus:SI (gtu:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
4347 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
4348 (match_operand:SI 3 "reg_or_short_operand" "r,I"))
4349 (const_int 0)))
4350 (set (match_operand:SI 0 "gen_reg_operand" "=r,r")
4351 (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4352 (clobber (match_scratch:SI 4 "=&r,&r"))]
4353 ""
4354 "sf%I2 %4,%1,%2\;sfe %4,%4,%4\;sf%I3. %0,%4,%3"
4355 [(set_attr "type" "compare")])
4356
4357(define_insn ""
4358 [(set (match_operand:SI 0 "gen_reg_operand" "=r")
4359 (neg:SI (gtu:SI (match_operand:SI 1 "gen_reg_operand" "r")
4360 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
4361 ""
4362 "sf%I2 %0,%1,%2\;sfe %0,%0,%0")
4363\f
4364;; Define both directions of branch and return. If we need a reload
4365;; register, we'd rather use CR0 since it is much easier to copy a
4366;; register CC value to there.
4367
4368(define_insn ""
4369 [(set (pc)
4370 (if_then_else (match_operator 1 "branch_comparison_operator"
4371 [(match_operand 2
4372 "cc_reg_operand" "x,?y")
4373 (const_int 0)])
4374 (label_ref (match_operand 0 "" ""))
4375 (pc)))]
4376 ""
4377 "%C1bc %t1,%j1,%0")
4378
4379(define_insn ""
4380 [(set (pc)
4381 (if_then_else (match_operator 0 "branch_comparison_operator"
4382 [(match_operand 1
4383 "cc_reg_operand" "x,?y")
4384 (const_int 0)])
4385 (return)
4386 (pc)))]
4387 "direct_return ()"
4388 "%C0bcr %t0,%j0")
4389
4390(define_insn ""
4391 [(set (pc)
4392 (if_then_else (match_operator 1 "branch_comparison_operator"
4393 [(match_operand 2
4394 "cc_reg_operand" "x,?y")
4395 (const_int 0)])
4396 (pc)
4397 (label_ref (match_operand 0 "" ""))))]
4398 ""
4399 "%C1bc %T1,%j1,%0")
4400
4401(define_insn ""
4402 [(set (pc)
4403 (if_then_else (match_operator 0 "branch_comparison_operator"
4404 [(match_operand 1
4405 "cc_reg_operand" "x,?y")
4406 (const_int 0)])
4407 (pc)
4408 (return)))]
4409 "direct_return ()"
4410 "%C0bcr %T0,%j0")
4411
4412;; Unconditional branch and return.
4413
4414(define_insn "jump"
4415 [(set (pc)
4416 (label_ref (match_operand 0 "" "")))]
4417 ""
4418 "b %l0")
4419
4420(define_insn "return"
4421 [(return)]
4422 "direct_return ()"
4423 "br")
4424
4425(define_insn "indirect_jump"
4426 [(set (pc) (match_operand:SI 0 "register_operand" "c,l"))]
4427 ""
4428 "@
4429 bctr
4430 br")
4431
4432;; Table jump for switch statements:
4433(define_expand "tablejump"
4434 [(set (match_dup 3)
4435 (plus:SI (match_operand:SI 0 "" "")
4436 (match_dup 2)))
4437 (parallel [(set (pc) (match_dup 3))
4438 (use (label_ref (match_operand 1 "" "")))])]
4439 ""
4440 "
4441{ operands[0] = force_reg (SImode, operands[0]);
4442 operands[2] = force_reg (SImode, gen_rtx (LABEL_REF, VOIDmode, operands[1]));
4443 operands[3] = gen_reg_rtx (SImode);
4444}")
4445
4446(define_insn ""
4447 [(set (pc)
4448 (match_operand:SI 0 "register_operand" "c,r"))
4449 (use (label_ref (match_operand 1 "" "")))]
4450 ""
4451 "@
4452 bctr
4453 br")
4454
4455(define_insn "nop"
4456 [(const_int 0)]
4457 ""
4458 "cror 0,0,0")
4459\f
4460;; Define the subtract-one-and-jump insns.
4461;; We need to be able to do this for any operand, including MEM, or we
4462;; will cause reload to blow up since we don't allow output reloads on
4463;; JUMP_INSNs.
4464(define_insn ""
4465 [(set (pc)
4466 (if_then_else (ne (match_operand:SI 1 "register_operand" "0,*r,*r")
4467 (const_int 1))
4468 (label_ref (match_operand 2 "" ""))
4469 (pc)))
4470 (set (match_operand:SI 0 "register_operand" "=c,*r,m*q*c*l")
4471 (plus:SI (match_dup 1) (const_int -1)))
4472 (clobber (match_scratch:CC 3 "=X,&x,&x"))
4473 (clobber (match_scratch:SI 4 "=X,X,r"))]
4474 ""
4475 "@
4476 bdn %l2
4477 #
4478 #")
4479
4480;; Similar, but we can use GE since we have a REG_NOTES.
4481(define_insn ""
4482 [(set (pc)
4483 (if_then_else (ge (match_operand:SI 1 "register_operand" "0,*r,*r")
4484 (const_int 0))
4485 (label_ref (match_operand 2 "" ""))
4486 (pc)))
4487 (set (match_operand:SI 0 "register_operand" "=c,*r,m*q*c*l")
4488 (plus:SI (match_dup 1) (const_int -1)))
4489 (clobber (match_scratch:CC 3 "=X,&x,&X"))
4490 (clobber (match_scratch:SI 4 "=X,X,r"))]
4491 "find_reg_note (insn, REG_NONNEG, 0)"
4492 "@
4493 bdn %l2
4494 #
4495 #")
4496
4497(define_insn ""
4498 [(set (pc)
4499 (if_then_else (eq (match_operand:SI 1 "register_operand" "0,*r,*r")
4500 (const_int 1))
4501 (label_ref (match_operand 2 "" ""))
4502 (pc)))
4503 (set (match_operand:SI 0 "register_operand" "=c,*r,m*q*c*l")
4504 (plus:SI (match_dup 1) (const_int -1)))
4505 (clobber (match_scratch:CC 3 "=X,&x,&x"))
4506 (clobber (match_scratch:SI 4 "=X,X,r"))]
4507 ""
4508 "@
4509 bdz %l2
4510 #
4511 #")
4512
4513(define_split
4514 [(set (pc)
4515 (if_then_else (match_operator 2 "comparison_operator"
4516 [(match_operand:SI 1 "gen_reg_operand" "")
4517 (const_int 1)])
4518 (match_operand 5 "" "")
4519 (match_operand 6 "" "")))
4520 (set (match_operand:SI 0 "gen_reg_operand" "")
4521 (plus:SI (match_dup 1) (const_int -1)))
4522 (clobber (match_scratch:CC 3 ""))
4523 (clobber (match_scratch:SI 4 ""))]
4524 "reload_completed"
4525 [(parallel [(set (match_dup 3)
4526 (compare:CC (plus:SI (match_dup 1) (const_int -1))
4527 (const_int 0)))
4528 (set (match_dup 0) (plus:SI (match_dup 1) (const_int -1)))])
4529 (set (pc) (if_then_else (match_dup 7) (match_dup 5) (match_dup 6)))]
4530 "
4531{ operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3],
4532 const0_rtx); }")
4533
4534(define_split
4535 [(set (pc)
4536 (if_then_else (match_operator 2 "comparison_operator"
4537 [(match_operand:SI 1 "gen_reg_operand" "")
4538 (const_int 1)])
4539 (match_operand 5 "" "")
4540 (match_operand 6 "" "")))
4541 (set (match_operand:SI 0 "general_operand" "")
4542 (plus:SI (match_dup 1) (const_int -1)))
4543 (clobber (match_scratch:CC 3 ""))
4544 (clobber (match_scratch:SI 4 ""))]
4545 "reload_completed && ! gen_reg_operand (operands[0], SImode)"
4546 [(parallel [(set (match_dup 3)
4547 (compare:CC (plus:SI (match_dup 1) (const_int -1))
4548 (const_int 0)))
4549 (set (match_dup 4) (plus:SI (match_dup 1) (const_int -1)))])
4550 (set (match_dup 0) (match_dup 4))
4551 (set (pc) (if_then_else (match_dup 7) (match_dup 5) (match_dup 6)))]
4552 "
4553{ operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3],
4554 const0_rtx); }")
4555\f
4556;;- Local variables:
4557;;- mode:emacs-lisp
4558;;- comment-start: ";;- "
4559;;- eval: (set-syntax-table (copy-sequence (syntax-table)))
4560;;- eval: (modify-syntax-entry ?[ "(]")
4561;;- eval: (modify-syntax-entry ?] ")[")
4562;;- eval: (modify-syntax-entry ?{ "(}")
4563;;- eval: (modify-syntax-entry ?} "){")
4564;;- End:
GNU Compiler Collection
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