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f045b2c9 | 1 | /* Definitions of target machine for GNU compiler, for IBM RS/6000. |
a945c346 | 2 | Copyright (C) 1992-2024 Free Software Foundation, Inc. |
6a7ec0a7 | 3 | Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) |
f045b2c9 | 4 | |
5de601cf | 5 | This file is part of GCC. |
f045b2c9 | 6 | |
5de601cf NC |
7 | GCC is free software; you can redistribute it and/or modify it |
8 | under the terms of the GNU General Public License as published | |
2f83c7d6 | 9 | by the Free Software Foundation; either version 3, or (at your |
5de601cf | 10 | option) any later version. |
f045b2c9 | 11 | |
5de601cf NC |
12 | GCC is distributed in the hope that it will be useful, but WITHOUT |
13 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
14 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
15 | License for more details. | |
f045b2c9 | 16 | |
748086b7 JJ |
17 | Under Section 7 of GPL version 3, you are granted additional |
18 | permissions described in the GCC Runtime Library Exception, version | |
19 | 3.1, as published by the Free Software Foundation. | |
20 | ||
21 | You should have received a copy of the GNU General Public License and | |
22 | a copy of the GCC Runtime Library Exception along with this program; | |
23 | see the files COPYING3 and COPYING.RUNTIME respectively. If not, see | |
2f83c7d6 | 24 | <http://www.gnu.org/licenses/>. */ |
f045b2c9 RS |
25 | |
26 | /* Note that some other tm.h files include this one and then override | |
9ebbca7d | 27 | many of the definitions. */ |
f045b2c9 | 28 | |
fd438373 MM |
29 | #ifndef RS6000_OPTS_H |
30 | #include "config/rs6000/rs6000-opts.h" | |
31 | #endif | |
32 | ||
6a8886e4 MM |
33 | /* 128-bit floating point precision values. */ |
34 | #ifndef RS6000_MODES_H | |
35 | #include "config/rs6000/rs6000-modes.h" | |
36 | #endif | |
37 | ||
9ebbca7d GK |
38 | /* Definitions for the object file format. These are set at |
39 | compile-time. */ | |
f045b2c9 | 40 | |
9ebbca7d GK |
41 | #define OBJECT_XCOFF 1 |
42 | #define OBJECT_ELF 2 | |
ee890fe2 | 43 | #define OBJECT_MACHO 4 |
f045b2c9 | 44 | |
9ebbca7d | 45 | #define TARGET_ELF (TARGET_OBJECT_FORMAT == OBJECT_ELF) |
2bfcf297 | 46 | #define TARGET_XCOFF (TARGET_OBJECT_FORMAT == OBJECT_XCOFF) |
ee890fe2 | 47 | #define TARGET_MACHO (TARGET_OBJECT_FORMAT == OBJECT_MACHO) |
f045b2c9 | 48 | |
2bfcf297 DB |
49 | #ifndef TARGET_AIX |
50 | #define TARGET_AIX 0 | |
51 | #endif | |
52 | ||
78009d9f MM |
53 | #ifndef TARGET_AIX_OS |
54 | #define TARGET_AIX_OS 0 | |
55 | #endif | |
56 | ||
9ae813e8 MM |
57 | /* Turn off TOC support if pc-relative addressing is used. */ |
58 | #define TARGET_TOC (TARGET_HAS_TOC && !TARGET_PCREL) | |
59 | ||
60 | /* On 32-bit systems without a TOC or pc-relative addressing, we need to use | |
61 | ADDIS/ADDI to load up the address of a symbol. */ | |
62 | #define TARGET_NO_TOC_OR_PCREL (!TARGET_HAS_TOC && !TARGET_PCREL) | |
63 | ||
85b776df AM |
64 | /* Control whether function entry points use a "dot" symbol when |
65 | ABI_AIX. */ | |
66 | #define DOT_SYMBOLS 1 | |
67 | ||
8e3f41e7 MM |
68 | /* Default string to use for cpu if not specified. */ |
69 | #ifndef TARGET_CPU_DEFAULT | |
70 | #define TARGET_CPU_DEFAULT ((char *)0) | |
71 | #endif | |
72 | ||
f565b0a1 | 73 | /* If configured for PPC405, support PPC405CR Erratum77. */ |
b0bfee6e | 74 | #ifdef CONFIG_PPC405CR |
f565b0a1 DE |
75 | #define PPC405_ERRATUM77 (rs6000_cpu == PROCESSOR_PPC405) |
76 | #else | |
77 | #define PPC405_ERRATUM77 0 | |
78 | #endif | |
79 | ||
98ae96d2 PB |
80 | #ifndef SUBTARGET_DRIVER_SELF_SPECS |
81 | # define SUBTARGET_DRIVER_SELF_SPECS "" | |
82 | #endif | |
83 | ||
75d20d6c PB |
84 | /* Only for use in the testsuite: -mdejagnu-cpu=<value> filters out all |
85 | -mcpu= as well as -mtune= options then simply adds -mcpu=<value>, | |
86 | while -mdejagnu-tune=<value> filters out all -mtune= options then | |
87 | simply adds -mtune=<value>. | |
98ae96d2 | 88 | With older versions of Dejagnu the command line arguments you set in |
75d20d6c PB |
89 | RUNTESTFLAGS override those set in the testcases; with these options, |
90 | the testcase will always win. */ | |
98ae96d2 | 91 | #define DRIVER_SELF_SPECS \ |
75d20d6c | 92 | "%{mdejagnu-cpu=*: %<mcpu=* %<mtune=* -mcpu=%*}", \ |
98ae96d2 PB |
93 | "%{mdejagnu-tune=*: %<mtune=* -mtune=%*}", \ |
94 | "%{mdejagnu-*: %<mdejagnu-*}", \ | |
95 | SUBTARGET_DRIVER_SELF_SPECS | |
96 | ||
e1542427 AM |
97 | #if CHECKING_P |
98 | #define ASM_OPT_ANY "" | |
99 | #else | |
100 | #define ASM_OPT_ANY " -many" | |
101 | #endif | |
102 | ||
cacf1ca8 | 103 | /* Common ASM definitions used by ASM_SPEC among the various targets for |
e53b6e56 | 104 | handling -mcpu=xxx switches. There is a parallel list in driver-rs6000.cc to |
cacf1ca8 | 105 | provide the default assembler options if the user uses -mcpu=native, so if |
438ef143 | 106 | you make changes here, make them also there. */ |
f984d8df | 107 | #define ASM_CPU_SPEC \ |
28a09576 | 108 | "%{mcpu=native: %(asm_cpu_native); \ |
dc0f9a74 | 109 | mcpu=power11: -mpower11; \ |
5d9d0c94 | 110 | mcpu=power10: -mpower10; \ |
28a09576 | 111 | mcpu=power9: -mpower9; \ |
438ef143 | 112 | mcpu=power8|mcpu=powerpc64le: -mpower8; \ |
28a09576 AM |
113 | mcpu=power7: -mpower7; \ |
114 | mcpu=power6x: -mpower6 %{!mvsx:%{!maltivec:-maltivec}}; \ | |
115 | mcpu=power6: -mpower6 %{!mvsx:%{!maltivec:-maltivec}}; \ | |
116 | mcpu=power5+: -mpower5; \ | |
117 | mcpu=power5: -mpower5; \ | |
118 | mcpu=power4: -mpower4; \ | |
119 | mcpu=power3: -mppc64; \ | |
120 | mcpu=powerpc: -mppc; \ | |
f7bdd292 | 121 | mcpu=powerpc64: -mppc64; \ |
28a09576 AM |
122 | mcpu=a2: -ma2; \ |
123 | mcpu=cell: -mcell; \ | |
f7bdd292 | 124 | mcpu=rs64: -mppc64; \ |
28a09576 AM |
125 | mcpu=401: -mppc; \ |
126 | mcpu=403: -m403; \ | |
127 | mcpu=405: -m405; \ | |
128 | mcpu=405fp: -m405; \ | |
129 | mcpu=440: -m440; \ | |
130 | mcpu=440fp: -m440; \ | |
131 | mcpu=464: -m440; \ | |
132 | mcpu=464fp: -m440; \ | |
133 | mcpu=476: -m476; \ | |
134 | mcpu=476fp: -m476; \ | |
135 | mcpu=505: -mppc; \ | |
136 | mcpu=601: -m601; \ | |
137 | mcpu=602: -mppc; \ | |
138 | mcpu=603: -mppc; \ | |
139 | mcpu=603e: -mppc; \ | |
140 | mcpu=ec603e: -mppc; \ | |
141 | mcpu=604: -mppc; \ | |
142 | mcpu=604e: -mppc; \ | |
143 | mcpu=620: -mppc64; \ | |
144 | mcpu=630: -mppc64; \ | |
145 | mcpu=740: -mppc; \ | |
146 | mcpu=750: -mppc; \ | |
147 | mcpu=G3: -mppc; \ | |
148 | mcpu=7400: -mppc %{!mvsx:%{!maltivec:-maltivec}}; \ | |
149 | mcpu=7450: -mppc %{!mvsx:%{!maltivec:-maltivec}}; \ | |
150 | mcpu=G4: -mppc %{!mvsx:%{!maltivec:-maltivec}}; \ | |
151 | mcpu=801: -mppc; \ | |
152 | mcpu=821: -mppc; \ | |
153 | mcpu=823: -mppc; \ | |
154 | mcpu=860: -mppc; \ | |
155 | mcpu=970: -mpower4 %{!mvsx:%{!maltivec:-maltivec}}; \ | |
156 | mcpu=G5: -mpower4 %{!mvsx:%{!maltivec:-maltivec}}; \ | |
157 | mcpu=8540: -me500; \ | |
158 | mcpu=8548: -me500; \ | |
159 | mcpu=e300c2: -me300; \ | |
160 | mcpu=e300c3: -me300; \ | |
161 | mcpu=e500mc: -me500mc; \ | |
162 | mcpu=e500mc64: -me500mc64; \ | |
163 | mcpu=e5500: -me5500; \ | |
164 | mcpu=e6500: -me6500; \ | |
f7bdd292 | 165 | mcpu=titan: -mtitan; \ |
438ef143 | 166 | !mcpu*: %{mcrypto|mdirect-move|mhtm: -mpower8; \ |
28a09576 AM |
167 | mvsx: -mpower7; \ |
168 | mpowerpc64: -mppc64;: %(asm_default)}; \ | |
f7bdd292 | 169 | :%eMissing -mcpu option in ASM_CPU_SPEC?\n} \ |
e1542427 AM |
170 | %{mvsx: -mvsx -maltivec; maltivec: -maltivec}" \ |
171 | ASM_OPT_ANY | |
f984d8df DB |
172 | |
173 | #define CPP_DEFAULT_SPEC "" | |
174 | ||
175 | #define ASM_DEFAULT_SPEC "" | |
8d852645 | 176 | #define ASM_DEFAULT_EXTRA "" |
f984d8df | 177 | |
841faeed MM |
178 | /* This macro defines names of additional specifications to put in the specs |
179 | that can be used in various specifications like CC1_SPEC. Its definition | |
180 | is an initializer with a subgrouping for each command option. | |
181 | ||
182 | Each subgrouping contains a string constant, that defines the | |
5de601cf | 183 | specification name, and a string constant that used by the GCC driver |
841faeed MM |
184 | program. |
185 | ||
186 | Do not define this macro if it does not need to do anything. */ | |
187 | ||
7509c759 | 188 | #define SUBTARGET_EXTRA_SPECS |
7509c759 | 189 | |
c81bebd7 | 190 | #define EXTRA_SPECS \ |
c81bebd7 | 191 | { "cpp_default", CPP_DEFAULT_SPEC }, \ |
c81bebd7 | 192 | { "asm_cpu", ASM_CPU_SPEC }, \ |
cacf1ca8 | 193 | { "asm_cpu_native", ASM_CPU_NATIVE_SPEC }, \ |
8d852645 | 194 | { "asm_default", ASM_DEFAULT_SPEC ASM_DEFAULT_EXTRA }, \ |
0eab6840 | 195 | { "cc1_cpu", CC1_CPU_SPEC }, \ |
7509c759 MM |
196 | SUBTARGET_EXTRA_SPECS |
197 | ||
0eab6840 DE |
198 | /* -mcpu=native handling only makes sense with compiler running on |
199 | an PowerPC chip. If changing this condition, also change | |
e53b6e56 | 200 | the condition in driver-rs6000.cc. */ |
0eab6840 | 201 | #if defined(__powerpc__) || defined(__POWERPC__) || defined(_AIX) |
e53b6e56 | 202 | /* In driver-rs6000.cc. */ |
0eab6840 DE |
203 | extern const char *host_detect_local_cpu (int argc, const char **argv); |
204 | #define EXTRA_SPEC_FUNCTIONS \ | |
205 | { "local_cpu_detect", host_detect_local_cpu }, | |
206 | #define HAVE_LOCAL_CPU_DETECT | |
cacf1ca8 MM |
207 | #define ASM_CPU_NATIVE_SPEC "%:local_cpu_detect(asm)" |
208 | ||
209 | #else | |
210 | #define ASM_CPU_NATIVE_SPEC "%(asm_default)" | |
0eab6840 DE |
211 | #endif |
212 | ||
ee7caeb3 DE |
213 | #ifndef CC1_CPU_SPEC |
214 | #ifdef HAVE_LOCAL_CPU_DETECT | |
0eab6840 DE |
215 | #define CC1_CPU_SPEC \ |
216 | "%{mcpu=native:%<mcpu=native %:local_cpu_detect(cpu)} \ | |
217 | %{mtune=native:%<mtune=native %:local_cpu_detect(tune)}" | |
ee7caeb3 DE |
218 | #else |
219 | #define CC1_CPU_SPEC "" | |
220 | #endif | |
0eab6840 DE |
221 | #endif |
222 | ||
fb623df5 | 223 | /* Architecture type. */ |
f045b2c9 | 224 | |
bb22512c | 225 | /* Define TARGET_MFCRF if the target assembler does not support the |
78f5898b | 226 | optional field operand for mfcr. */ |
fb623df5 | 227 | |
78f5898b | 228 | #ifndef HAVE_AS_MFCRF |
432218ba | 229 | #undef TARGET_MFCRF |
ffa22984 DE |
230 | #define TARGET_MFCRF 0 |
231 | #endif | |
232 | ||
7f970b70 AM |
233 | #ifndef TARGET_SECURE_PLT |
234 | #define TARGET_SECURE_PLT 0 | |
235 | #endif | |
236 | ||
070b27da AM |
237 | #ifndef TARGET_CMODEL |
238 | #define TARGET_CMODEL CMODEL_SMALL | |
239 | #endif | |
240 | ||
2f3e5814 | 241 | #define TARGET_32BIT (! TARGET_64BIT) |
d14a6d05 | 242 | |
c4501e62 JJ |
243 | #ifndef HAVE_AS_TLS |
244 | #define HAVE_AS_TLS 0 | |
245 | #endif | |
246 | ||
3f79c0ad AM |
247 | #ifndef HAVE_AS_PLTSEQ |
248 | #define HAVE_AS_PLTSEQ 0 | |
249 | #endif | |
250 | ||
ff7fa488 AM |
251 | #ifndef TARGET_PLTSEQ |
252 | #define TARGET_PLTSEQ 0 | |
253 | #endif | |
254 | ||
be26142a PB |
255 | #ifndef TARGET_LINK_STACK |
256 | #define TARGET_LINK_STACK 0 | |
257 | #endif | |
258 | ||
259 | #ifndef SET_TARGET_LINK_STACK | |
260 | #define SET_TARGET_LINK_STACK(X) do { } while (0) | |
261 | #endif | |
262 | ||
08213983 MM |
263 | #ifndef TARGET_FLOAT128_ENABLE_TYPE |
264 | #define TARGET_FLOAT128_ENABLE_TYPE 0 | |
265 | #endif | |
266 | ||
48d72335 DE |
267 | /* Return 1 for a symbol ref for a thread-local storage symbol. */ |
268 | #define RS6000_SYMBOL_REF_TLS_P(RTX) \ | |
2e42a52f | 269 | (SYMBOL_REF_P (RTX) && SYMBOL_REF_TLS_MODEL (RTX) != 0) |
48d72335 | 270 | |
996ed075 JJ |
271 | #ifdef IN_LIBGCC2 |
272 | /* For libgcc2 we make sure this is a compile time constant */ | |
67796c1f | 273 | #if defined (__64BIT__) || defined (__powerpc64__) || defined (__ppc64__) |
78f5898b | 274 | #undef TARGET_POWERPC64 |
996ed075 JJ |
275 | #define TARGET_POWERPC64 1 |
276 | #else | |
78f5898b | 277 | #undef TARGET_POWERPC64 |
996ed075 JJ |
278 | #define TARGET_POWERPC64 0 |
279 | #endif | |
b6c9286a | 280 | #else |
78f5898b | 281 | /* The option machinery will define this. */ |
b6c9286a MM |
282 | #endif |
283 | ||
9ccc75eb | 284 | #define TARGET_DEFAULT (OPTION_MASK_MULTIPLE) |
9ebbca7d | 285 | |
8482e358 | 286 | /* Define generic processor types based upon current deployment. */ |
3cb999d8 | 287 | #define PROCESSOR_COMMON PROCESSOR_PPC601 |
3cb999d8 DE |
288 | #define PROCESSOR_POWERPC PROCESSOR_PPC604 |
289 | #define PROCESSOR_POWERPC64 PROCESSOR_RS64A | |
6e151478 | 290 | |
fb623df5 | 291 | /* Define the default processor. This is overridden by other tm.h files. */ |
f3061fa4 | 292 | #define PROCESSOR_DEFAULT PROCESSOR_PPC603 |
3cb999d8 | 293 | #define PROCESSOR_DEFAULT64 PROCESSOR_RS64A |
fb623df5 | 294 | |
59ac9a55 JJ |
295 | /* Specify the dialect of assembler to use. Only new mnemonics are supported |
296 | starting with GCC 4.8, i.e. just one dialect, but for backwards | |
297 | compatibility with older inline asm ASSEMBLER_DIALECT needs to be | |
298 | defined. */ | |
299 | #define ASSEMBLER_DIALECT 1 | |
300 | ||
38c1f2d7 | 301 | /* Debug support */ |
fd438373 MM |
302 | #define MASK_DEBUG_STACK 0x01 /* debug stack applications */ |
303 | #define MASK_DEBUG_ARG 0x02 /* debug argument handling */ | |
304 | #define MASK_DEBUG_REG 0x04 /* debug register handling */ | |
305 | #define MASK_DEBUG_ADDR 0x08 /* debug memory addressing */ | |
306 | #define MASK_DEBUG_COST 0x10 /* debug rtx codes */ | |
307 | #define MASK_DEBUG_TARGET 0x20 /* debug target attribute/pragma */ | |
7fa14a01 | 308 | #define MASK_DEBUG_BUILTIN 0x40 /* debug builtins */ |
fd438373 MM |
309 | #define MASK_DEBUG_ALL (MASK_DEBUG_STACK \ |
310 | | MASK_DEBUG_ARG \ | |
311 | | MASK_DEBUG_REG \ | |
312 | | MASK_DEBUG_ADDR \ | |
313 | | MASK_DEBUG_COST \ | |
7fa14a01 MM |
314 | | MASK_DEBUG_TARGET \ |
315 | | MASK_DEBUG_BUILTIN) | |
fd438373 MM |
316 | |
317 | #define TARGET_DEBUG_STACK (rs6000_debug & MASK_DEBUG_STACK) | |
318 | #define TARGET_DEBUG_ARG (rs6000_debug & MASK_DEBUG_ARG) | |
319 | #define TARGET_DEBUG_REG (rs6000_debug & MASK_DEBUG_REG) | |
320 | #define TARGET_DEBUG_ADDR (rs6000_debug & MASK_DEBUG_ADDR) | |
321 | #define TARGET_DEBUG_COST (rs6000_debug & MASK_DEBUG_COST) | |
322 | #define TARGET_DEBUG_TARGET (rs6000_debug & MASK_DEBUG_TARGET) | |
7fa14a01 | 323 | #define TARGET_DEBUG_BUILTIN (rs6000_debug & MASK_DEBUG_BUILTIN) |
cacf1ca8 | 324 | |
2c83faf8 MM |
325 | /* Helper macros for TFmode. Quad floating point (TFmode) can be either IBM |
326 | long double format that uses a pair of doubles, or IEEE 128-bit floating | |
327 | point. KFmode was added as a way to represent IEEE 128-bit floating point, | |
328 | even if the default for long double is the IBM long double format. | |
329 | Similarly IFmode is the IBM long double format even if the default is IEEE | |
0bc36dec | 330 | 128-bit. Don't allow IFmode if -msoft-float. */ |
2c83faf8 | 331 | #define FLOAT128_IEEE_P(MODE) \ |
83cbbe3a MM |
332 | ((TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128 \ |
333 | && ((MODE) == TFmode || (MODE) == TCmode)) \ | |
4304ccfd | 334 | || ((MODE) == KFmode) || ((MODE) == KCmode)) |
2c83faf8 MM |
335 | |
336 | #define FLOAT128_IBM_P(MODE) \ | |
83cbbe3a MM |
337 | ((!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128 \ |
338 | && ((MODE) == TFmode || (MODE) == TCmode)) \ | |
11d8d07e | 339 | || (TARGET_HARD_FLOAT && ((MODE) == IFmode || (MODE) == ICmode))) |
2c83faf8 MM |
340 | |
341 | /* Helper macros to say whether a 128-bit floating point type can go in a | |
342 | single vector register, or whether it needs paired scalar values. */ | |
08213983 | 343 | #define FLOAT128_VECTOR_P(MODE) (TARGET_FLOAT128_TYPE && FLOAT128_IEEE_P (MODE)) |
2c83faf8 MM |
344 | |
345 | #define FLOAT128_2REG_P(MODE) \ | |
346 | (FLOAT128_IBM_P (MODE) \ | |
347 | || ((MODE) == TDmode) \ | |
08213983 | 348 | || (!TARGET_FLOAT128_TYPE && FLOAT128_IEEE_P (MODE))) |
2c83faf8 MM |
349 | |
350 | /* Return true for floating point that does not use a vector register. */ | |
351 | #define SCALAR_FLOAT_MODE_NOT_VECTOR_P(MODE) \ | |
352 | (SCALAR_FLOAT_MODE_P (MODE) && !FLOAT128_VECTOR_P (MODE)) | |
353 | ||
f62511da | 354 | /* Describe the vector unit used for arithmetic operations. */ |
cacf1ca8 MM |
355 | extern enum rs6000_vector rs6000_vector_unit[]; |
356 | ||
357 | #define VECTOR_UNIT_NONE_P(MODE) \ | |
358 | (rs6000_vector_unit[(MODE)] == VECTOR_NONE) | |
359 | ||
360 | #define VECTOR_UNIT_VSX_P(MODE) \ | |
361 | (rs6000_vector_unit[(MODE)] == VECTOR_VSX) | |
362 | ||
f62511da MM |
363 | #define VECTOR_UNIT_P8_VECTOR_P(MODE) \ |
364 | (rs6000_vector_unit[(MODE)] == VECTOR_P8_VECTOR) | |
365 | ||
cacf1ca8 MM |
366 | #define VECTOR_UNIT_ALTIVEC_P(MODE) \ |
367 | (rs6000_vector_unit[(MODE)] == VECTOR_ALTIVEC) | |
368 | ||
f62511da MM |
369 | #define VECTOR_UNIT_VSX_OR_P8_VECTOR_P(MODE) \ |
370 | (IN_RANGE ((int)rs6000_vector_unit[(MODE)], \ | |
371 | (int)VECTOR_VSX, \ | |
372 | (int)VECTOR_P8_VECTOR)) | |
373 | ||
374 | /* VECTOR_UNIT_ALTIVEC_OR_VSX_P is used in places where we are using either | |
375 | altivec (VMX) or VSX vector instructions. P8 vector support is upwards | |
376 | compatible, so allow it as well, rather than changing all of the uses of the | |
377 | macro. */ | |
cacf1ca8 | 378 | #define VECTOR_UNIT_ALTIVEC_OR_VSX_P(MODE) \ |
f62511da MM |
379 | (IN_RANGE ((int)rs6000_vector_unit[(MODE)], \ |
380 | (int)VECTOR_ALTIVEC, \ | |
381 | (int)VECTOR_P8_VECTOR)) | |
cacf1ca8 MM |
382 | |
383 | /* Describe whether to use VSX loads or Altivec loads. For now, just use the | |
384 | same unit as the vector unit we are using, but we may want to migrate to | |
385 | using VSX style loads even for types handled by altivec. */ | |
386 | extern enum rs6000_vector rs6000_vector_mem[]; | |
387 | ||
388 | #define VECTOR_MEM_NONE_P(MODE) \ | |
389 | (rs6000_vector_mem[(MODE)] == VECTOR_NONE) | |
390 | ||
391 | #define VECTOR_MEM_VSX_P(MODE) \ | |
392 | (rs6000_vector_mem[(MODE)] == VECTOR_VSX) | |
393 | ||
f62511da MM |
394 | #define VECTOR_MEM_P8_VECTOR_P(MODE) \ |
395 | (rs6000_vector_mem[(MODE)] == VECTOR_VSX) | |
396 | ||
cacf1ca8 MM |
397 | #define VECTOR_MEM_ALTIVEC_P(MODE) \ |
398 | (rs6000_vector_mem[(MODE)] == VECTOR_ALTIVEC) | |
399 | ||
f62511da MM |
400 | #define VECTOR_MEM_VSX_OR_P8_VECTOR_P(MODE) \ |
401 | (IN_RANGE ((int)rs6000_vector_mem[(MODE)], \ | |
402 | (int)VECTOR_VSX, \ | |
403 | (int)VECTOR_P8_VECTOR)) | |
404 | ||
cacf1ca8 | 405 | #define VECTOR_MEM_ALTIVEC_OR_VSX_P(MODE) \ |
f62511da MM |
406 | (IN_RANGE ((int)rs6000_vector_mem[(MODE)], \ |
407 | (int)VECTOR_ALTIVEC, \ | |
408 | (int)VECTOR_P8_VECTOR)) | |
cacf1ca8 MM |
409 | |
410 | /* Return the alignment of a given vector type, which is set based on the | |
411 | vector unit use. VSX for instance can load 32 or 64 bit aligned words | |
412 | without problems, while Altivec requires 128-bit aligned vectors. */ | |
413 | extern int rs6000_vector_align[]; | |
414 | ||
415 | #define VECTOR_ALIGN(MODE) \ | |
416 | ((rs6000_vector_align[(MODE)] != 0) \ | |
417 | ? rs6000_vector_align[(MODE)] \ | |
418 | : (int)GET_MODE_BITSIZE ((MODE))) | |
419 | ||
117f16fb MM |
420 | /* Element number of the 64-bit value in a 128-bit vector that can be accessed |
421 | with scalar instructions. */ | |
422 | #define VECTOR_ELEMENT_SCALAR_64BIT ((BYTES_BIG_ENDIAN) ? 0 : 1) | |
423 | ||
dd551aa1 MM |
424 | /* Element number of the 64-bit value in a 128-bit vector that can be accessed |
425 | with the ISA 3.0 MFVSRLD instructions. */ | |
426 | #define VECTOR_ELEMENT_MFVSRLD_64BIT ((BYTES_BIG_ENDIAN) ? 1 : 0) | |
427 | ||
025d9908 KH |
428 | /* Alignment options for fields in structures for sub-targets following |
429 | AIX-like ABI. | |
430 | ALIGN_POWER word-aligns FP doubles (default AIX ABI). | |
431 | ALIGN_NATURAL doubleword-aligns FP doubles (align to object size). | |
432 | ||
433 | Override the macro definitions when compiling libobjc to avoid undefined | |
434 | reference to rs6000_alignment_flags due to library's use of GCC alignment | |
435 | macros which use the macros below. */ | |
f676971a | 436 | |
025d9908 KH |
437 | #ifndef IN_TARGET_LIBS |
438 | #define MASK_ALIGN_POWER 0x00000000 | |
439 | #define MASK_ALIGN_NATURAL 0x00000001 | |
440 | #define TARGET_ALIGN_NATURAL (rs6000_alignment_flags & MASK_ALIGN_NATURAL) | |
441 | #else | |
442 | #define TARGET_ALIGN_NATURAL 0 | |
443 | #endif | |
6fa3f289 | 444 | |
6a8886e4 MM |
445 | /* We use values 126..128 to pick the appropriate long double type (IFmode, |
446 | KFmode, TFmode). */ | |
447 | #define TARGET_LONG_DOUBLE_128 (rs6000_long_double_type_size > 64) | |
602ea4d3 | 448 | #define TARGET_IEEEQUAD rs6000_ieeequad |
6fa3f289 | 449 | #define TARGET_ALTIVEC_ABI rs6000_altivec_abi |
cacf1ca8 | 450 | #define TARGET_LDBRX (TARGET_POPCNTD || rs6000_cpu == PROCESSOR_CELL) |
6fa3f289 | 451 | |
7042fe5e | 452 | /* ISA 2.01 allowed FCFID to be done in 32-bit, previously it was 64-bit only. |
2c2aa74d | 453 | Enable 32-bit fcfid's on any of the switches for newer ISA machines. */ |
c3f8384f MM |
454 | #define TARGET_FCFID (TARGET_POWERPC64 \ |
455 | || TARGET_PPC_GPOPT /* 970/power4 */ \ | |
456 | || TARGET_POPCNTB /* ISA 2.02 */ \ | |
457 | || TARGET_CMPB /* ISA 2.05 */ \ | |
2c2aa74d | 458 | || TARGET_POPCNTD) /* ISA 2.06 */ |
7042fe5e MM |
459 | |
460 | #define TARGET_FCTIDZ TARGET_FCFID | |
461 | #define TARGET_STFIWX TARGET_PPC_GFXOPT | |
462 | #define TARGET_LFIWAX TARGET_CMPB | |
463 | #define TARGET_LFIWZX TARGET_POPCNTD | |
464 | #define TARGET_FCFIDS TARGET_POPCNTD | |
465 | #define TARGET_FCFIDU TARGET_POPCNTD | |
466 | #define TARGET_FCFIDUS TARGET_POPCNTD | |
467 | #define TARGET_FCTIDUZ TARGET_POPCNTD | |
468 | #define TARGET_FCTIWUZ TARGET_POPCNTD | |
ae226cb1 HG |
469 | /* Only powerpc64 and powerpc476 support fctid. */ |
470 | #define TARGET_FCTID (TARGET_POWERPC64 || rs6000_cpu == PROCESSOR_PPC476) | |
0299bc72 MM |
471 | #define TARGET_CTZ TARGET_MODULO |
472 | #define TARGET_EXTSWSLI (TARGET_MODULO && TARGET_POWERPC64) | |
fdfbed38 | 473 | #define TARGET_MADDLD TARGET_MODULO |
7042fe5e | 474 | |
f62511da MM |
475 | #define TARGET_XSCVDPSPN (TARGET_DIRECT_MOVE || TARGET_P8_VECTOR) |
476 | #define TARGET_XSCVSPDPN (TARGET_DIRECT_MOVE || TARGET_P8_VECTOR) | |
a16a872d | 477 | #define TARGET_VADDUQM (TARGET_P8_VECTOR && TARGET_POWERPC64) |
dd551aa1 MM |
478 | #define TARGET_DIRECT_MOVE_128 (TARGET_P9_VECTOR && TARGET_DIRECT_MOVE \ |
479 | && TARGET_POWERPC64) | |
c5e74d9d | 480 | #define TARGET_VEXTRACTUB (TARGET_P9_VECTOR && TARGET_DIRECT_MOVE \ |
6bd6f4f4 | 481 | && TARGET_POWERPC64) |
fba4b861 | 482 | |
fba4b861 MM |
483 | /* Whether we should avoid (SUBREG:SI (REG:SF) and (SUBREG:SF (REG:SI). */ |
484 | #define TARGET_NO_SF_SUBREG TARGET_DIRECT_MOVE_64BIT | |
485 | #define TARGET_ALLOW_SF_SUBREG (!TARGET_DIRECT_MOVE_64BIT) | |
486 | ||
f62511da MM |
487 | /* Byte/char syncs were added as phased in for ISA 2.06B, but are not present |
488 | in power7, so conditionalize them on p8 features. TImode syncs need quad | |
489 | memory support. */ | |
b846c948 MM |
490 | #define TARGET_SYNC_HI_QI (TARGET_QUAD_MEMORY \ |
491 | || TARGET_QUAD_MEMORY_ATOMIC \ | |
492 | || TARGET_DIRECT_MOVE) | |
493 | ||
494 | #define TARGET_SYNC_TI TARGET_QUAD_MEMORY_ATOMIC | |
f62511da | 495 | |
c6d5ff83 MM |
496 | /* Power7 has both 32-bit load and store integer for the FPRs, so we don't need |
497 | to allocate the SDmode stack slot to get the value into the proper location | |
498 | in the register. */ | |
499 | #define TARGET_NO_SDMODE_STACK (TARGET_LFIWZX && TARGET_STFIWX && TARGET_DFP) | |
500 | ||
21316320 MM |
501 | /* ISA 3.0 has new min/max functions that don't need fast math that are being |
502 | phased in. Min/max using FSEL or XSMAXDP/XSMINDP do not return the correct | |
503 | answers if the arguments are not in the normal range. */ | |
2c2aa74d SB |
504 | #define TARGET_MINMAX (TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT \ |
505 | && (TARGET_P9_MINMAX || !flag_trapping_math)) | |
21316320 | 506 | |
4d967549 | 507 | /* In switching from using target_flags to using rs6000_isa_flags, the options |
124580b0 WS |
508 | machinery creates OPTION_MASK_<xxx> instead of MASK_<xxx>. The MASK_<xxxx> |
509 | options that have not yet been replaced by their OPTION_MASK_<xxx> | |
510 | equivalents are defined here. */ | |
eb2887a1 | 511 | |
4d967549 | 512 | #define MASK_STRICT_ALIGN OPTION_MASK_STRICT_ALIGN |
4d967549 MM |
513 | |
514 | #ifndef IN_LIBGCC2 | |
515 | #define MASK_POWERPC64 OPTION_MASK_POWERPC64 | |
516 | #endif | |
517 | ||
518 | #ifdef TARGET_64BIT | |
519 | #define MASK_64BIT OPTION_MASK_64BIT | |
520 | #endif | |
521 | ||
4d967549 MM |
522 | #ifdef TARGET_LITTLE_ENDIAN |
523 | #define MASK_LITTLE_ENDIAN OPTION_MASK_LITTLE_ENDIAN | |
524 | #endif | |
525 | ||
7fa14a01 MM |
526 | /* For power systems, we want to enable Altivec and VSX builtins even if the |
527 | user did not use -maltivec or -mvsx to allow the builtins to be used inside | |
528 | of #pragma GCC target or the target attribute to change the code level for a | |
55928937 SB |
529 | given system. */ |
530 | ||
531 | #define TARGET_EXTRA_BUILTINS (TARGET_POWERPC64 \ | |
532 | || TARGET_PPC_GPOPT /* 970/power4 */ \ | |
533 | || TARGET_POPCNTB /* ISA 2.02 */ \ | |
534 | || TARGET_CMPB /* ISA 2.05 */ \ | |
535 | || TARGET_POPCNTD /* ISA 2.06 */ \ | |
536 | || TARGET_ALTIVEC \ | |
537 | || TARGET_VSX \ | |
538 | || TARGET_HARD_FLOAT) | |
7fa14a01 | 539 | |
a7c6c6d6 OH |
540 | /* E500 cores only support plain "sync", not lwsync. */ |
541 | #define TARGET_NO_LWSYNC (rs6000_cpu == PROCESSOR_PPC8540 \ | |
542 | || rs6000_cpu == PROCESSOR_PPC8548) | |
7fa14a01 MM |
543 | |
544 | ||
92902797 | 545 | /* Which machine supports the various reciprocal estimate instructions. */ |
2c2aa74d | 546 | #define TARGET_FRES (TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT) |
92902797 | 547 | |
2c2aa74d | 548 | #define TARGET_FRE (TARGET_HARD_FLOAT \ |
92902797 MM |
549 | && (TARGET_POPCNTB || VECTOR_UNIT_VSX_P (DFmode))) |
550 | ||
551 | #define TARGET_FRSQRTES (TARGET_HARD_FLOAT && TARGET_POPCNTB \ | |
2c2aa74d | 552 | && TARGET_PPC_GFXOPT) |
92902797 | 553 | |
2c2aa74d | 554 | #define TARGET_FRSQRTE (TARGET_HARD_FLOAT \ |
92902797 MM |
555 | && (TARGET_PPC_GFXOPT || VECTOR_UNIT_VSX_P (DFmode))) |
556 | ||
6019c0fc MM |
557 | /* Macro to say whether we can do optimizations where we need to do parts of |
558 | the calculation in 64-bit GPRs and then is transfered to the vector | |
427a7384 | 559 | registers. */ |
e0d32185 MM |
560 | #define TARGET_DIRECT_MOVE_64BIT (TARGET_DIRECT_MOVE \ |
561 | && TARGET_P8_VECTOR \ | |
427a7384 | 562 | && TARGET_POWERPC64) |
e0d32185 | 563 | |
0fc60c18 KL |
564 | /* Inlining allows targets to define the meanings of bits in target_info |
565 | field of ipa_fn_summary by itself, the used bits for rs6000 are listed | |
566 | below. */ | |
567 | #define RS6000_FN_TARGET_INFO_HTM 1 | |
568 | ||
92902797 MM |
569 | /* Whether the various reciprocal divide/square root estimate instructions |
570 | exist, and whether we should automatically generate code for the instruction | |
571 | by default. */ | |
572 | #define RS6000_RECIP_MASK_HAVE_RE 0x1 /* have RE instruction. */ | |
573 | #define RS6000_RECIP_MASK_AUTO_RE 0x2 /* generate RE by default. */ | |
574 | #define RS6000_RECIP_MASK_HAVE_RSQRTE 0x4 /* have RSQRTE instruction. */ | |
575 | #define RS6000_RECIP_MASK_AUTO_RSQRTE 0x8 /* gen. RSQRTE by default. */ | |
576 | ||
577 | extern unsigned char rs6000_recip_bits[]; | |
578 | ||
579 | #define RS6000_RECIP_HAVE_RE_P(MODE) \ | |
580 | (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_HAVE_RE) | |
581 | ||
582 | #define RS6000_RECIP_AUTO_RE_P(MODE) \ | |
583 | (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_AUTO_RE) | |
584 | ||
585 | #define RS6000_RECIP_HAVE_RSQRTE_P(MODE) \ | |
586 | (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_HAVE_RSQRTE) | |
587 | ||
588 | #define RS6000_RECIP_AUTO_RSQRTE_P(MODE) \ | |
589 | (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_AUTO_RSQRTE) | |
590 | ||
c5387660 JM |
591 | /* The default CPU for TARGET_OPTION_OVERRIDE. */ |
592 | #define OPTION_TARGET_CPU_DEFAULT TARGET_CPU_DEFAULT | |
f045b2c9 | 593 | |
a5c76ee6 | 594 | /* Target pragma. */ |
c58b209a NB |
595 | #define REGISTER_TARGET_PRAGMAS() do { \ |
596 | c_register_pragma (0, "longcall", rs6000_pragma_longcall); \ | |
fd438373 | 597 | targetm.target_option.pragma_parse = rs6000_pragma_target_parse; \ |
2fab365e | 598 | targetm.resolve_overloaded_builtin = altivec_resolve_overloaded_builtin; \ |
7fa14a01 | 599 | rs6000_target_modify_macros_ptr = rs6000_target_modify_macros; \ |
a5c76ee6 ZW |
600 | } while (0) |
601 | ||
4c4eb375 GK |
602 | /* Target #defines. */ |
603 | #define TARGET_CPU_CPP_BUILTINS() \ | |
604 | rs6000_cpu_cpp_builtins (pfile) | |
647d340d JT |
605 | |
606 | /* This is used by rs6000_cpu_cpp_builtins to indicate the byte order | |
607 | we're compiling for. Some configurations may need to override it. */ | |
608 | #define RS6000_CPU_CPP_ENDIAN_BUILTINS() \ | |
609 | do \ | |
610 | { \ | |
611 | if (BYTES_BIG_ENDIAN) \ | |
612 | { \ | |
613 | builtin_define ("__BIG_ENDIAN__"); \ | |
614 | builtin_define ("_BIG_ENDIAN"); \ | |
615 | builtin_assert ("machine=bigendian"); \ | |
616 | } \ | |
617 | else \ | |
618 | { \ | |
619 | builtin_define ("__LITTLE_ENDIAN__"); \ | |
620 | builtin_define ("_LITTLE_ENDIAN"); \ | |
621 | builtin_assert ("machine=littleendian"); \ | |
622 | } \ | |
623 | } \ | |
624 | while (0) | |
f045b2c9 | 625 | \f |
4c4eb375 | 626 | /* Target machine storage layout. */ |
f045b2c9 RS |
627 | |
628 | /* Define this if most significant bit is lowest numbered | |
82e41834 KH |
629 | in instructions that operate on numbered bit-fields. */ |
630 | /* That is true on RS/6000. */ | |
f045b2c9 RS |
631 | #define BITS_BIG_ENDIAN 1 |
632 | ||
633 | /* Define this if most significant byte of a word is the lowest numbered. */ | |
634 | /* That is true on RS/6000. */ | |
635 | #define BYTES_BIG_ENDIAN 1 | |
636 | ||
637 | /* Define this if most significant word of a multiword number is lowest | |
c81bebd7 | 638 | numbered. |
f045b2c9 RS |
639 | |
640 | For RS/6000 we can decide arbitrarily since there are no machine | |
82e41834 | 641 | instructions for them. Might as well be consistent with bits and bytes. */ |
f045b2c9 RS |
642 | #define WORDS_BIG_ENDIAN 1 |
643 | ||
50751417 AM |
644 | /* This says that for the IBM long double the larger magnitude double |
645 | comes first. It's really a two element double array, and arrays | |
646 | don't index differently between little- and big-endian. */ | |
647 | #define LONG_DOUBLE_LARGE_FIRST 1 | |
648 | ||
2e360ab3 | 649 | #define MAX_BITS_PER_WORD 64 |
f045b2c9 RS |
650 | |
651 | /* Width of a word, in units (bytes). */ | |
c1aa3958 | 652 | #define UNITS_PER_WORD (! TARGET_POWERPC64 ? 4 : 8) |
f34fc46e DE |
653 | #ifdef IN_LIBGCC2 |
654 | #define MIN_UNITS_PER_WORD UNITS_PER_WORD | |
655 | #else | |
ef0e53ce | 656 | #define MIN_UNITS_PER_WORD 4 |
f34fc46e | 657 | #endif |
2e360ab3 | 658 | #define UNITS_PER_FP_WORD 8 |
0ac081f6 | 659 | #define UNITS_PER_ALTIVEC_WORD 16 |
cacf1ca8 | 660 | #define UNITS_PER_VSX_WORD 16 |
f045b2c9 | 661 | |
915f619f JW |
662 | /* Type used for ptrdiff_t, as a string used in a declaration. */ |
663 | #define PTRDIFF_TYPE "int" | |
664 | ||
058ef853 DE |
665 | /* Type used for size_t, as a string used in a declaration. */ |
666 | #define SIZE_TYPE "long unsigned int" | |
667 | ||
f045b2c9 RS |
668 | /* Type used for wchar_t, as a string used in a declaration. */ |
669 | #define WCHAR_TYPE "short unsigned int" | |
670 | ||
671 | /* Width of wchar_t in bits. */ | |
672 | #define WCHAR_TYPE_SIZE 16 | |
673 | ||
9e654916 RK |
674 | /* A C expression for the size in bits of the type `short' on the |
675 | target machine. If you don't define this, the default is half a | |
676 | word. (If this would be less than one storage unit, it is | |
677 | rounded up to one unit.) */ | |
678 | #define SHORT_TYPE_SIZE 16 | |
679 | ||
680 | /* A C expression for the size in bits of the type `int' on the | |
681 | target machine. If you don't define this, the default is one | |
682 | word. */ | |
19d2d16f | 683 | #define INT_TYPE_SIZE 32 |
9e654916 RK |
684 | |
685 | /* A C expression for the size in bits of the type `long' on the | |
686 | target machine. If you don't define this, the default is one | |
687 | word. */ | |
2f3e5814 | 688 | #define LONG_TYPE_SIZE (TARGET_32BIT ? 32 : 64) |
9e654916 RK |
689 | |
690 | /* A C expression for the size in bits of the type `long long' on the | |
691 | target machine. If you don't define this, the default is two | |
692 | words. */ | |
693 | #define LONG_LONG_TYPE_SIZE 64 | |
694 | ||
9e654916 RK |
695 | /* A C expression for the size in bits of the type `float' on the |
696 | target machine. If you don't define this, the default is one | |
697 | word. */ | |
698 | #define FLOAT_TYPE_SIZE 32 | |
699 | ||
700 | /* A C expression for the size in bits of the type `double' on the | |
701 | target machine. If you don't define this, the default is two | |
702 | words. */ | |
703 | #define DOUBLE_TYPE_SIZE 64 | |
704 | ||
6a8886e4 MM |
705 | /* A C expression for the size in bits of the type `long double' on the target |
706 | machine. If you don't define this, the default is two words. */ | |
6fa3f289 | 707 | #define LONG_DOUBLE_TYPE_SIZE rs6000_long_double_type_size |
06f4e019 | 708 | |
e53b6e56 | 709 | /* Work around rs6000_long_double_type_size dependency in ada/targtyps.cc. */ |
5b8f5865 DE |
710 | #define WIDEST_HARDWARE_FP_SIZE 64 |
711 | ||
f045b2c9 RS |
712 | /* Width in bits of a pointer. |
713 | See also the macro `Pmode' defined below. */ | |
cacf1ca8 MM |
714 | extern unsigned rs6000_pointer_size; |
715 | #define POINTER_SIZE rs6000_pointer_size | |
f045b2c9 RS |
716 | |
717 | /* Allocation boundary (in *bits*) for storing arguments in argument list. */ | |
2f3e5814 | 718 | #define PARM_BOUNDARY (TARGET_32BIT ? 32 : 64) |
f045b2c9 RS |
719 | |
720 | /* Boundary (in *bits*) on which stack pointer should be aligned. */ | |
cacf1ca8 MM |
721 | #define STACK_BOUNDARY \ |
722 | ((TARGET_32BIT && !TARGET_ALTIVEC && !TARGET_ALTIVEC_ABI && !TARGET_VSX) \ | |
723 | ? 64 : 128) | |
f045b2c9 RS |
724 | |
725 | /* Allocation boundary (in *bits*) for the code of a function. */ | |
726 | #define FUNCTION_BOUNDARY 32 | |
727 | ||
a37b5bcf PB |
728 | /* No data type is required to be aligned rounder than this. Warning, if |
729 | BIGGEST_ALIGNMENT is changed, then this may be an ABI break. An example | |
730 | of where this can break an ABI is in GLIBC's struct _Unwind_Exception. */ | |
731 | #define BIGGEST_ALIGNMENT 128 | |
0ac081f6 | 732 | |
f045b2c9 RS |
733 | /* Alignment of field after `int : 0' in a structure. */ |
734 | #define EMPTY_FIELD_BOUNDARY 32 | |
735 | ||
736 | /* Every structure's size must be a multiple of this. */ | |
737 | #define STRUCTURE_SIZE_BOUNDARY 8 | |
738 | ||
43a88a8c | 739 | /* A bit-field declared as `int' forces `int' alignment for the struct. */ |
f045b2c9 RS |
740 | #define PCC_BITFIELD_TYPE_MATTERS 1 |
741 | ||
69eff9da AM |
742 | enum data_align { align_abi, align_opt, align_both }; |
743 | ||
744 | /* A C expression to compute the alignment for a variables in the | |
745 | local store. TYPE is the data type, and ALIGN is the alignment | |
746 | that the object would ordinarily have. */ | |
747 | #define LOCAL_ALIGNMENT(TYPE, ALIGN) \ | |
748 | rs6000_data_alignment (TYPE, ALIGN, align_both) | |
749 | ||
69eff9da AM |
750 | /* Make arrays of chars word-aligned for the same reasons. */ |
751 | #define DATA_ALIGNMENT(TYPE, ALIGN) \ | |
752 | rs6000_data_alignment (TYPE, ALIGN, align_opt) | |
753 | ||
e075a6cc | 754 | /* Align vectors to 128 bits. */ |
69eff9da AM |
755 | #define DATA_ABI_ALIGNMENT(TYPE, ALIGN) \ |
756 | rs6000_data_alignment (TYPE, ALIGN, align_abi) | |
f045b2c9 | 757 | |
a0ab749a | 758 | /* Nonzero if move instructions will actually fail to work |
f045b2c9 | 759 | when given unaligned data. */ |
fdaff8ba | 760 | #define STRICT_ALIGNMENT 0 |
f045b2c9 RS |
761 | \f |
762 | /* Standard register usage. */ | |
763 | ||
764 | /* Number of actual hardware registers. | |
765 | The hardware registers are assigned numbers for the compiler | |
766 | from 0 to just below FIRST_PSEUDO_REGISTER. | |
767 | All registers that the compiler knows about must be given numbers, | |
768 | even those that are not normally considered general registers. | |
769 | ||
770 | RS/6000 has 32 fixed-point registers, 32 floating-point registers, | |
462f7901 SB |
771 | a count register, a link register, and 8 condition register fields, |
772 | which we view here as separate registers. AltiVec adds 32 vector | |
773 | registers and a VRsave register. | |
f045b2c9 RS |
774 | |
775 | In addition, the difference between the frame and argument pointers is | |
776 | a function of the number of registers saved, so we need to have a | |
777 | register for AP that will later be eliminated in favor of SP or FP. | |
802a0058 | 778 | This is a normal register, but it is fixed. |
f045b2c9 | 779 | |
802a0058 MM |
780 | We also create a pseudo register for float/int conversions, that will |
781 | really represent the memory location used. It is represented here as | |
782 | a register, in order to work around problems in allocating stack storage | |
7d5175e1 | 783 | in inline functions. |
802a0058 | 784 | |
7d5175e1 | 785 | Another pseudo (not included in DWARF_FRAME_REGISTERS) is soft frame |
33463137 | 786 | pointer, which is eventually eliminated in favor of SP or FP. */ |
7a5add18 | 787 | |
33463137 | 788 | #define FIRST_PSEUDO_REGISTER 111 |
c19de7aa | 789 | |
ed1cf8ff | 790 | /* Use standard DWARF numbering for DWARF debugging information. */ |
ca60bd93 | 791 | #define DEBUGGER_REGNO(REGNO) rs6000_debugger_regno ((REGNO), 0) |
ed1cf8ff | 792 | |
93c9d1ba | 793 | /* Use gcc hard register numbering for eh_frame. */ |
3d36d470 | 794 | #define DWARF_FRAME_REGNUM(REGNO) (REGNO) |
41f3a930 | 795 | |
ed1cf8ff GK |
796 | /* Map register numbers held in the call frame info that gcc has |
797 | collected using DWARF_FRAME_REGNUM to those that should be output in | |
3d36d470 UW |
798 | .debug_frame and .eh_frame. */ |
799 | #define DWARF2_FRAME_REG_OUT(REGNO, FOR_EH) \ | |
ca60bd93 | 800 | rs6000_debugger_regno ((REGNO), (FOR_EH) ? 2 : 1) |
ed1cf8ff | 801 | |
f045b2c9 RS |
802 | /* 1 for registers that have pervasive standard uses |
803 | and are not available for the register allocator. | |
804 | ||
5dead3e5 DJ |
805 | On RS/6000, r1 is used for the stack. On Darwin, r2 is available |
806 | as a local register; for all other OS's r2 is the TOC pointer. | |
f045b2c9 | 807 | |
a127c4e5 RK |
808 | On System V implementations, r13 is fixed and not available for use. */ |
809 | ||
f045b2c9 | 810 | #define FIXED_REGISTERS \ |
33463137 | 811 | {/* GPRs */ \ |
1bbb169f | 812 | 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, FIXED_R13, 0, 0, \ |
f045b2c9 | 813 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ |
33463137 | 814 | /* FPRs */ \ |
f045b2c9 RS |
815 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ |
816 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
33463137 | 817 | /* VRs */ \ |
0ac081f6 AH |
818 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ |
819 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
33463137 SB |
820 | /* lr ctr ca ap */ \ |
821 | 0, 0, 1, 1, \ | |
822 | /* cr0..cr7 */ \ | |
823 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
824 | /* vrsave vscr sfp */ \ | |
825 | 1, 1, 1 \ | |
0ac081f6 | 826 | } |
f045b2c9 | 827 | |
289e96b2 AH |
828 | /* Like `CALL_USED_REGISTERS' except this macro doesn't require that |
829 | the entire set of `FIXED_REGISTERS' be included. | |
830 | (`CALL_USED_REGISTERS' must be a superset of `FIXED_REGISTERS'). | |
831 | This macro is optional. If not specified, it defaults to the value | |
832 | of `CALL_USED_REGISTERS'. */ | |
f676971a | 833 | |
289e96b2 | 834 | #define CALL_REALLY_USED_REGISTERS \ |
33463137 SB |
835 | {/* GPRs */ \ |
836 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \ | |
289e96b2 | 837 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ |
33463137 | 838 | /* FPRs */ \ |
289e96b2 AH |
839 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \ |
840 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
33463137 | 841 | /* VRs */ \ |
289e96b2 AH |
842 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ |
843 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
33463137 SB |
844 | /* lr ctr ca ap */ \ |
845 | 1, 1, 1, 1, \ | |
846 | /* cr0..cr7 */ \ | |
847 | 1, 1, 0, 0, 0, 1, 1, 1, \ | |
848 | /* vrsave vscr sfp */ \ | |
849 | 0, 0, 0 \ | |
289e96b2 | 850 | } |
f045b2c9 | 851 | |
28bcfd4d | 852 | #define TOTAL_ALTIVEC_REGS (LAST_ALTIVEC_REGNO - FIRST_ALTIVEC_REGNO + 1) |
9ebbca7d | 853 | |
d62294f5 | 854 | #define FIRST_SAVED_ALTIVEC_REGNO (FIRST_ALTIVEC_REGNO+20) |
b427dd7a AM |
855 | #define FIRST_SAVED_FP_REGNO (14+32) |
856 | #define FIRST_SAVED_GP_REGNO (FIXED_R13 ? 14 : 13) | |
d62294f5 | 857 | |
f045b2c9 RS |
858 | /* List the order in which to allocate registers. Each register must be |
859 | listed once, even those in FIXED_REGISTERS. | |
860 | ||
861 | We allocate in the following order: | |
862 | fp0 (not saved or used for anything) | |
863 | fp13 - fp2 (not saved; incoming fp arg registers) | |
864 | fp1 (not saved; return value) | |
9390387d | 865 | fp31 - fp14 (saved; order given to save least number) |
36bd0c3e SB |
866 | cr7, cr5 (not saved or special) |
867 | cr6 (not saved, but used for vector operations) | |
5accd822 | 868 | cr1 (not saved, but used for FP operations) |
f045b2c9 | 869 | cr0 (not saved, but used for arithmetic operations) |
5accd822 | 870 | cr4, cr3, cr2 (saved) |
f045b2c9 | 871 | r9 (not saved; best for TImode) |
d44b26bd | 872 | r10, r8-r4 (not saved; highest first for less conflict with params) |
9390387d | 873 | r3 (not saved; return value register) |
d44b26bd AM |
874 | r11 (not saved; later alloc to help shrink-wrap) |
875 | r0 (not saved; cannot be base reg) | |
f045b2c9 RS |
876 | r31 - r13 (saved; order given to save least number) |
877 | r12 (not saved; if used for DImode or DFmode would use r13) | |
f045b2c9 RS |
878 | ctr (not saved; when we have the choice ctr is better) |
879 | lr (saved) | |
36bd0c3e | 880 | r1, r2, ap, ca (fixed) |
9390387d AM |
881 | v0 - v1 (not saved or used for anything) |
882 | v13 - v3 (not saved; incoming vector arg registers) | |
883 | v2 (not saved; incoming vector arg reg; return value) | |
884 | v19 - v14 (not saved or used for anything) | |
885 | v31 - v20 (saved; order given to save least number) | |
886 | vrsave, vscr (fixed) | |
7d5175e1 | 887 | sfp (fixed) |
0ac081f6 | 888 | */ |
f676971a | 889 | |
6b13641d DJ |
890 | #if FIXED_R2 == 1 |
891 | #define MAYBE_R2_AVAILABLE | |
892 | #define MAYBE_R2_FIXED 2, | |
893 | #else | |
894 | #define MAYBE_R2_AVAILABLE 2, | |
895 | #define MAYBE_R2_FIXED | |
896 | #endif | |
f045b2c9 | 897 | |
d44b26bd AM |
898 | #if FIXED_R13 == 1 |
899 | #define EARLY_R12 12, | |
900 | #define LATE_R12 | |
901 | #else | |
902 | #define EARLY_R12 | |
903 | #define LATE_R12 12, | |
904 | #endif | |
905 | ||
9390387d AM |
906 | #define REG_ALLOC_ORDER \ |
907 | {32, \ | |
f62511da MM |
908 | /* move fr13 (ie 45) later, so if we need TFmode, it does */ \ |
909 | /* not use fr14 which is a saved register. */ \ | |
910 | 44, 43, 42, 41, 40, 39, 38, 37, 36, 35, 34, 45, \ | |
9390387d AM |
911 | 33, \ |
912 | 63, 62, 61, 60, 59, 58, 57, 56, 55, 54, 53, 52, 51, \ | |
913 | 50, 49, 48, 47, 46, \ | |
33463137 | 914 | 100, 107, 105, 106, 101, 104, 103, 102, \ |
d44b26bd AM |
915 | MAYBE_R2_AVAILABLE \ |
916 | 9, 10, 8, 7, 6, 5, 4, \ | |
917 | 3, EARLY_R12 11, 0, \ | |
9390387d | 918 | 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, \ |
d44b26bd | 919 | 18, 17, 16, 15, 14, 13, LATE_R12 \ |
33463137 SB |
920 | 97, 96, \ |
921 | 1, MAYBE_R2_FIXED 99, 98, \ | |
9390387d | 922 | /* AltiVec registers. */ \ |
33463137 SB |
923 | 64, 65, \ |
924 | 77, 76, 75, 74, 73, 72, 71, 70, 69, 68, 67, \ | |
925 | 66, \ | |
926 | 83, 82, 81, 80, 79, 78, \ | |
927 | 95, 94, 93, 92, 91, 90, 89, 88, 87, 86, 85, 84, \ | |
928 | 108, 109, \ | |
929 | 110 \ | |
0ac081f6 | 930 | } |
f045b2c9 RS |
931 | |
932 | /* True if register is floating-point. */ | |
933 | #define FP_REGNO_P(N) ((N) >= 32 && (N) <= 63) | |
934 | ||
935 | /* True if register is a condition register. */ | |
1de43f85 | 936 | #define CR_REGNO_P(N) ((N) >= CR0_REGNO && (N) <= CR7_REGNO) |
f045b2c9 | 937 | |
815cdc52 | 938 | /* True if register is a condition register, but not cr0. */ |
1de43f85 | 939 | #define CR_REGNO_NOT_CR0_P(N) ((N) >= CR1_REGNO && (N) <= CR7_REGNO) |
815cdc52 | 940 | |
f045b2c9 | 941 | /* True if register is an integer register. */ |
7d5175e1 JJ |
942 | #define INT_REGNO_P(N) \ |
943 | ((N) <= 31 || (N) == ARG_POINTER_REGNUM || (N) == FRAME_POINTER_REGNUM) | |
f045b2c9 | 944 | |
f6b5d695 SB |
945 | /* True if register is the CA register. */ |
946 | #define CA_REGNO_P(N) ((N) == CA_REGNO) | |
802a0058 | 947 | |
0ac081f6 AH |
948 | /* True if register is an AltiVec register. */ |
949 | #define ALTIVEC_REGNO_P(N) ((N) >= FIRST_ALTIVEC_REGNO && (N) <= LAST_ALTIVEC_REGNO) | |
950 | ||
cacf1ca8 MM |
951 | /* True if register is a VSX register. */ |
952 | #define VSX_REGNO_P(N) (FP_REGNO_P (N) || ALTIVEC_REGNO_P (N)) | |
953 | ||
954 | /* Alternate name for any vector register supporting floating point, no matter | |
955 | which instruction set(s) are available. */ | |
956 | #define VFLOAT_REGNO_P(N) \ | |
957 | (ALTIVEC_REGNO_P (N) || (TARGET_VSX && FP_REGNO_P (N))) | |
958 | ||
959 | /* Alternate name for any vector register supporting integer, no matter which | |
960 | instruction set(s) are available. */ | |
961 | #define VINT_REGNO_P(N) ALTIVEC_REGNO_P (N) | |
962 | ||
963 | /* Alternate name for any vector register supporting logical operations, no | |
dd7a40e1 MM |
964 | matter which instruction set(s) are available. Allow GPRs as well as the |
965 | vector registers. */ | |
f62511da | 966 | #define VLOGICAL_REGNO_P(N) \ |
dd7a40e1 MM |
967 | (INT_REGNO_P (N) || ALTIVEC_REGNO_P (N) \ |
968 | || (TARGET_VSX && FP_REGNO_P (N))) \ | |
cacf1ca8 | 969 | |
79eefb0d | 970 | /* When setting up caller-save slots (MODE == VOIDmode) ensure we allocate |
5ec6aff2 MM |
971 | enough space to account for vectors in FP regs. However, TFmode/TDmode |
972 | should not use VSX instructions to do a caller save. */ | |
dbcc9f08 | 973 | #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \ |
90b725f0 PB |
974 | ((NREGS) <= rs6000_hard_regno_nregs[MODE][REGNO] \ |
975 | ? (MODE) \ | |
976 | : TARGET_VSX \ | |
977 | && ((MODE) == VOIDmode || ALTIVEC_OR_VSX_VECTOR_MODE (MODE)) \ | |
978 | && FP_REGNO_P (REGNO) \ | |
5ec6aff2 | 979 | ? V2DFmode \ |
f7c12ec4 | 980 | : FLOAT128_IBM_P (MODE) && FP_REGNO_P (REGNO) \ |
5ec6aff2 | 981 | ? DFmode \ |
f7c12ec4 | 982 | : (MODE) == TDmode && FP_REGNO_P (REGNO) \ |
5ec6aff2 | 983 | ? DImode \ |
737d6a1a | 984 | : choose_hard_reg_mode ((REGNO), (NREGS), NULL)) |
79eefb0d | 985 | |
cacf1ca8 MM |
986 | #define VSX_VECTOR_MODE(MODE) \ |
987 | ((MODE) == V4SFmode \ | |
988 | || (MODE) == V2DFmode) \ | |
989 | ||
f002c046 PB |
990 | /* Modes that are not vectors, but require vector alignment. Treat these like |
991 | vectors in terms of loads and stores. */ | |
992 | #define VECTOR_ALIGNMENT_P(MODE) \ | |
f8f8909a | 993 | (FLOAT128_VECTOR_P (MODE) || (MODE) == OOmode || (MODE) == XOmode) |
bdb60a10 MM |
994 | |
995 | #define ALTIVEC_VECTOR_MODE(MODE) \ | |
996 | ((MODE) == V16QImode \ | |
997 | || (MODE) == V8HImode \ | |
998 | || (MODE) == V4SFmode \ | |
999 | || (MODE) == V4SImode \ | |
f002c046 | 1000 | || VECTOR_ALIGNMENT_P (MODE)) |
0ac081f6 | 1001 | |
dbcc9f08 MM |
1002 | #define ALTIVEC_OR_VSX_VECTOR_MODE(MODE) \ |
1003 | (ALTIVEC_VECTOR_MODE (MODE) || VSX_VECTOR_MODE (MODE) \ | |
a16a872d | 1004 | || (MODE) == V2DImode || (MODE) == V1TImode) |
dbcc9f08 | 1005 | |
c8ae788f SB |
1006 | /* Post-reload, we can't use any new AltiVec registers, as we already |
1007 | emitted the vrsave mask. */ | |
1008 | ||
1009 | #define HARD_REGNO_RENAME_OK(SRC, DST) \ | |
6fb5fa3c | 1010 | (! ALTIVEC_REGNO_P (DST) || df_regs_ever_live_p (DST)) |
c8ae788f | 1011 | |
f045b2c9 RS |
1012 | /* Specify the cost of a branch insn; roughly the number of extra insns that |
1013 | should be added to avoid a branch. | |
1014 | ||
ef457bda | 1015 | Set this to 3 on the RS/6000 since that is roughly the average cost of an |
f045b2c9 RS |
1016 | unscheduled conditional branch. */ |
1017 | ||
3a4fd356 | 1018 | #define BRANCH_COST(speed_p, predictable_p) 3 |
f045b2c9 | 1019 | |
85e50b6b | 1020 | /* Override BRANCH_COST heuristic which empirically produces worse |
b8610a53 | 1021 | performance for removing short circuiting from the logical ops. */ |
85e50b6b | 1022 | |
b8610a53 | 1023 | #define LOGICAL_OP_NON_SHORT_CIRCUIT 0 |
a3170dc6 | 1024 | |
f045b2c9 RS |
1025 | /* Specify the registers used for certain standard purposes. |
1026 | The values of these macros are register numbers. */ | |
1027 | ||
1028 | /* RS/6000 pc isn't overloaded on a register that the compiler knows about. */ | |
1029 | /* #define PC_REGNUM */ | |
1030 | ||
1031 | /* Register to use for pushing function arguments. */ | |
1032 | #define STACK_POINTER_REGNUM 1 | |
1033 | ||
1034 | /* Base register for access to local variables of the function. */ | |
7d5175e1 JJ |
1035 | #define HARD_FRAME_POINTER_REGNUM 31 |
1036 | ||
1037 | /* Base register for access to local variables of the function. */ | |
33463137 | 1038 | #define FRAME_POINTER_REGNUM 110 |
f045b2c9 | 1039 | |
f045b2c9 | 1040 | /* Base register for access to arguments of the function. */ |
33463137 | 1041 | #define ARG_POINTER_REGNUM 99 |
f045b2c9 RS |
1042 | |
1043 | /* Place to put static chain when calling a function that requires it. */ | |
1044 | #define STATIC_CHAIN_REGNUM 11 | |
1045 | ||
26a2e6ae PB |
1046 | /* Base register for access to thread local storage variables. */ |
1047 | #define TLS_REGNUM ((TARGET_64BIT) ? 13 : 2) | |
1048 | ||
f045b2c9 RS |
1049 | \f |
1050 | /* Define the classes of registers for register constraints in the | |
1051 | machine description. Also define ranges of constants. | |
1052 | ||
1053 | One of the classes must always be named ALL_REGS and include all hard regs. | |
1054 | If there is more than one class, another class must be named NO_REGS | |
1055 | and contain no registers. | |
1056 | ||
1057 | The name GENERAL_REGS must be the name of a class (or an alias for | |
1058 | another name such as ALL_REGS). This is the class of registers | |
1059 | that is allowed by "g" or "r" in a register constraint. | |
1060 | Also, registers outside this class are allocated only when | |
1061 | instructions express preferences for them. | |
1062 | ||
1063 | The classes must be numbered in nondecreasing order; that is, | |
1064 | a larger-numbered class must never be contained completely | |
1065 | in a smaller-numbered class. | |
1066 | ||
1067 | For any two classes, it is very desirable that there be another | |
1068 | class that represents their union. */ | |
c81bebd7 | 1069 | |
cacf1ca8 | 1070 | /* The RS/6000 has three types of registers, fixed-point, floating-point, and |
462f7901 | 1071 | condition registers, plus three special registers, CTR, and the link |
cacf1ca8 MM |
1072 | register. AltiVec adds a vector register class. VSX registers overlap the |
1073 | FPR registers and the Altivec registers. | |
f045b2c9 RS |
1074 | |
1075 | However, r0 is special in that it cannot be used as a base register. | |
1076 | So make a class for registers valid as base registers. | |
1077 | ||
1078 | Also, cr0 is the only condition code register that can be used in | |
0d86f538 | 1079 | arithmetic insns, so make a separate class for it. */ |
f045b2c9 | 1080 | |
ebedb4dd MM |
1081 | enum reg_class |
1082 | { | |
1083 | NO_REGS, | |
ebedb4dd MM |
1084 | BASE_REGS, |
1085 | GENERAL_REGS, | |
1086 | FLOAT_REGS, | |
0ac081f6 | 1087 | ALTIVEC_REGS, |
8beb65e3 | 1088 | VSX_REGS, |
0ac081f6 | 1089 | VRSAVE_REGS, |
5f004351 | 1090 | VSCR_REGS, |
c686fcbc | 1091 | GEN_OR_FLOAT_REGS, |
20d70cd2 | 1092 | GEN_OR_VSX_REGS, |
ebedb4dd MM |
1093 | LINK_REGS, |
1094 | CTR_REGS, | |
1095 | LINK_OR_CTR_REGS, | |
1096 | SPECIAL_REGS, | |
1097 | SPEC_OR_GEN_REGS, | |
1098 | CR0_REGS, | |
ebedb4dd MM |
1099 | CR_REGS, |
1100 | NON_FLOAT_REGS, | |
f6b5d695 | 1101 | CA_REGS, |
ebedb4dd MM |
1102 | ALL_REGS, |
1103 | LIM_REG_CLASSES | |
1104 | }; | |
f045b2c9 RS |
1105 | |
1106 | #define N_REG_CLASSES (int) LIM_REG_CLASSES | |
1107 | ||
82e41834 | 1108 | /* Give names of register classes as strings for dump file. */ |
f045b2c9 | 1109 | |
ebedb4dd MM |
1110 | #define REG_CLASS_NAMES \ |
1111 | { \ | |
1112 | "NO_REGS", \ | |
ebedb4dd MM |
1113 | "BASE_REGS", \ |
1114 | "GENERAL_REGS", \ | |
1115 | "FLOAT_REGS", \ | |
0ac081f6 | 1116 | "ALTIVEC_REGS", \ |
8beb65e3 | 1117 | "VSX_REGS", \ |
0ac081f6 | 1118 | "VRSAVE_REGS", \ |
5f004351 | 1119 | "VSCR_REGS", \ |
c686fcbc | 1120 | "GEN_OR_FLOAT_REGS", \ |
20d70cd2 | 1121 | "GEN_OR_VSX_REGS", \ |
ebedb4dd MM |
1122 | "LINK_REGS", \ |
1123 | "CTR_REGS", \ | |
1124 | "LINK_OR_CTR_REGS", \ | |
1125 | "SPECIAL_REGS", \ | |
1126 | "SPEC_OR_GEN_REGS", \ | |
1127 | "CR0_REGS", \ | |
ebedb4dd MM |
1128 | "CR_REGS", \ |
1129 | "NON_FLOAT_REGS", \ | |
f6b5d695 | 1130 | "CA_REGS", \ |
ebedb4dd MM |
1131 | "ALL_REGS" \ |
1132 | } | |
f045b2c9 RS |
1133 | |
1134 | /* Define which registers fit in which classes. | |
1135 | This is an initializer for a vector of HARD_REG_SET | |
1136 | of length N_REG_CLASSES. */ | |
1137 | ||
23742a9e RAR |
1138 | #define REG_CLASS_CONTENTS \ |
1139 | { \ | |
1140 | /* NO_REGS. */ \ | |
3e2bca2e | 1141 | { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \ |
23742a9e | 1142 | /* BASE_REGS. */ \ |
33463137 | 1143 | { 0xfffffffe, 0x00000000, 0x00000000, 0x00004008 }, \ |
23742a9e | 1144 | /* GENERAL_REGS. */ \ |
33463137 | 1145 | { 0xffffffff, 0x00000000, 0x00000000, 0x00004008 }, \ |
23742a9e | 1146 | /* FLOAT_REGS. */ \ |
3e2bca2e | 1147 | { 0x00000000, 0xffffffff, 0x00000000, 0x00000000 }, \ |
23742a9e | 1148 | /* ALTIVEC_REGS. */ \ |
33463137 | 1149 | { 0x00000000, 0x00000000, 0xffffffff, 0x00000000 }, \ |
23742a9e | 1150 | /* VSX_REGS. */ \ |
33463137 | 1151 | { 0x00000000, 0xffffffff, 0xffffffff, 0x00000000 }, \ |
23742a9e | 1152 | /* VRSAVE_REGS. */ \ |
33463137 | 1153 | { 0x00000000, 0x00000000, 0x00000000, 0x00001000 }, \ |
23742a9e | 1154 | /* VSCR_REGS. */ \ |
33463137 | 1155 | { 0x00000000, 0x00000000, 0x00000000, 0x00002000 }, \ |
c686fcbc | 1156 | /* GEN_OR_FLOAT_REGS. */ \ |
33463137 | 1157 | { 0xffffffff, 0xffffffff, 0x00000000, 0x00004008 }, \ |
20d70cd2 AM |
1158 | /* GEN_OR_VSX_REGS. */ \ |
1159 | { 0xffffffff, 0xffffffff, 0xffffffff, 0x00004008 }, \ | |
23742a9e | 1160 | /* LINK_REGS. */ \ |
33463137 | 1161 | { 0x00000000, 0x00000000, 0x00000000, 0x00000001 }, \ |
23742a9e | 1162 | /* CTR_REGS. */ \ |
33463137 | 1163 | { 0x00000000, 0x00000000, 0x00000000, 0x00000002 }, \ |
23742a9e | 1164 | /* LINK_OR_CTR_REGS. */ \ |
33463137 | 1165 | { 0x00000000, 0x00000000, 0x00000000, 0x00000003 }, \ |
23742a9e | 1166 | /* SPECIAL_REGS. */ \ |
33463137 | 1167 | { 0x00000000, 0x00000000, 0x00000000, 0x00001003 }, \ |
23742a9e | 1168 | /* SPEC_OR_GEN_REGS. */ \ |
33463137 | 1169 | { 0xffffffff, 0x00000000, 0x00000000, 0x0000500b }, \ |
23742a9e | 1170 | /* CR0_REGS. */ \ |
33463137 | 1171 | { 0x00000000, 0x00000000, 0x00000000, 0x00000010 }, \ |
23742a9e | 1172 | /* CR_REGS. */ \ |
33463137 | 1173 | { 0x00000000, 0x00000000, 0x00000000, 0x00000ff0 }, \ |
23742a9e | 1174 | /* NON_FLOAT_REGS. */ \ |
33463137 | 1175 | { 0xffffffff, 0x00000000, 0x00000000, 0x00004ffb }, \ |
23742a9e | 1176 | /* CA_REGS. */ \ |
33463137 | 1177 | { 0x00000000, 0x00000000, 0x00000000, 0x00000004 }, \ |
23742a9e | 1178 | /* ALL_REGS. */ \ |
33463137 | 1179 | { 0xffffffff, 0xffffffff, 0xffffffff, 0x00007fff } \ |
ebedb4dd | 1180 | } |
f045b2c9 RS |
1181 | |
1182 | /* The same information, inverted: | |
1183 | Return the class number of the smallest class containing | |
1184 | reg number REGNO. This could be a conditional expression | |
1185 | or could index an array. */ | |
1186 | ||
cacf1ca8 MM |
1187 | extern enum reg_class rs6000_regno_regclass[FIRST_PSEUDO_REGISTER]; |
1188 | ||
cacf1ca8 | 1189 | #define REGNO_REG_CLASS(REGNO) \ |
e28c2052 | 1190 | (gcc_checking_assert (IN_RANGE ((REGNO), 0, FIRST_PSEUDO_REGISTER-1)),\ |
cacf1ca8 MM |
1191 | rs6000_regno_regclass[(REGNO)]) |
1192 | ||
a72c65c7 MM |
1193 | /* Register classes for various constraints that are based on the target |
1194 | switches. */ | |
1195 | enum r6000_reg_class_enum { | |
401abb8f | 1196 | RS6000_CONSTRAINT_d, /* FPR registers */ |
a72c65c7 MM |
1197 | RS6000_CONSTRAINT_v, /* Altivec registers */ |
1198 | RS6000_CONSTRAINT_wa, /* Any VSX register */ | |
dd551aa1 | 1199 | RS6000_CONSTRAINT_we, /* VSX register if ISA 3.0 vector. */ |
f62511da | 1200 | RS6000_CONSTRAINT_wr, /* GPR register if 64-bit */ |
c6d5ff83 | 1201 | RS6000_CONSTRAINT_wx, /* FPR register for STFIWX */ |
99211352 | 1202 | RS6000_CONSTRAINT_wA, /* BASE_REGS if 64-bit. */ |
a72c65c7 MM |
1203 | RS6000_CONSTRAINT_MAX |
1204 | }; | |
1205 | ||
1206 | extern enum reg_class rs6000_constraints[RS6000_CONSTRAINT_MAX]; | |
f045b2c9 RS |
1207 | |
1208 | /* The class value for index registers, and the one for base regs. */ | |
1209 | #define INDEX_REG_CLASS GENERAL_REGS | |
1210 | #define BASE_REG_CLASS BASE_REGS | |
1211 | ||
cacf1ca8 MM |
1212 | /* Return whether a given register class can hold VSX objects. */ |
1213 | #define VSX_REG_CLASS_P(CLASS) \ | |
1214 | ((CLASS) == VSX_REGS || (CLASS) == FLOAT_REGS || (CLASS) == ALTIVEC_REGS) | |
1215 | ||
59f5868d MM |
1216 | /* Return whether a given register class targets general purpose registers. */ |
1217 | #define GPR_REG_CLASS_P(CLASS) ((CLASS) == GENERAL_REGS || (CLASS) == BASE_REGS) | |
1218 | ||
f045b2c9 RS |
1219 | /* Given an rtx X being reloaded into a reg required to be |
1220 | in class CLASS, return the class of reg to actually use. | |
1221 | In general this is just CLASS; but on some machines | |
c81bebd7 | 1222 | in some cases it is preferable to use a more restrictive class. |
f045b2c9 RS |
1223 | |
1224 | On the RS/6000, we have to return NO_REGS when we want to reload a | |
f676971a | 1225 | floating-point CONST_DOUBLE to force it to be copied to memory. |
1e66d555 GK |
1226 | |
1227 | We also don't want to reload integer values into floating-point | |
1228 | registers if we can at all help it. In fact, this can | |
37409796 | 1229 | cause reload to die, if it tries to generate a reload of CTR |
1e66d555 GK |
1230 | into a FP register and discovers it doesn't have the memory location |
1231 | required. | |
1232 | ||
1233 | ??? Would it be a good idea to have reload do the converse, that is | |
1234 | try to reload floating modes into FP registers if possible? | |
1235 | */ | |
f045b2c9 | 1236 | |
802a0058 | 1237 | #define PREFERRED_RELOAD_CLASS(X,CLASS) \ |
8beb65e3 | 1238 | rs6000_preferred_reload_class_ptr (X, CLASS) |
c81bebd7 | 1239 | |
f045b2c9 RS |
1240 | /* Return the register class of a scratch register needed to copy IN into |
1241 | or out of a register in CLASS in MODE. If it can be done directly, | |
1242 | NO_REGS is returned. */ | |
1243 | ||
1244 | #define SECONDARY_RELOAD_CLASS(CLASS,MODE,IN) \ | |
8beb65e3 | 1245 | rs6000_secondary_reload_class_ptr (CLASS, MODE, IN) |
f045b2c9 RS |
1246 | |
1247 | /* Return the maximum number of consecutive registers | |
1248 | needed to represent mode MODE in a register of class CLASS. | |
1249 | ||
cacf1ca8 MM |
1250 | On RS/6000, this is the size of MODE in words, except in the FP regs, where |
1251 | a single reg is enough for two words, unless we have VSX, where the FP | |
1252 | registers can hold 128 bits. */ | |
1253 | #define CLASS_MAX_NREGS(CLASS, MODE) rs6000_class_max_nregs[(MODE)][(CLASS)] | |
580d3230 | 1254 | |
f045b2c9 RS |
1255 | /* Stack layout; function entry, exit and calling. */ |
1256 | ||
1257 | /* Define this if pushing a word on the stack | |
1258 | makes the stack pointer a smaller address. */ | |
62f9f30b | 1259 | #define STACK_GROWS_DOWNWARD 1 |
f045b2c9 | 1260 | |
327e5343 FJ |
1261 | /* Offsets recorded in opcodes are a multiple of this alignment factor. */ |
1262 | #define DWARF_CIE_DATA_ALIGNMENT (-((int) (TARGET_32BIT ? 4 : 8))) | |
1263 | ||
a4d05547 | 1264 | /* Define this to nonzero if the nominal address of the stack frame |
f045b2c9 RS |
1265 | is at the high-address end of the local variables; |
1266 | that is, each additional local variable allocated | |
1267 | goes at a more negative offset in the frame. | |
1268 | ||
1269 | On the RS/6000, we grow upwards, from the area after the outgoing | |
1270 | arguments. */ | |
de5a5fa1 MP |
1271 | #define FRAME_GROWS_DOWNWARD (flag_stack_protect != 0 \ |
1272 | || (flag_sanitize & SANITIZE_ADDRESS) != 0) | |
f045b2c9 | 1273 | |
4697a36c | 1274 | /* Size of the fixed area on the stack */ |
9ebbca7d | 1275 | #define RS6000_SAVE_AREA \ |
b54214fe UW |
1276 | ((DEFAULT_ABI == ABI_V4 ? 8 : DEFAULT_ABI == ABI_ELFv2 ? 16 : 24) \ |
1277 | << (TARGET_64BIT ? 1 : 0)) | |
4697a36c | 1278 | |
b54214fe UW |
1279 | /* Stack offset for toc save slot. */ |
1280 | #define RS6000_TOC_SAVE_SLOT \ | |
1281 | ((DEFAULT_ABI == ABI_ELFv2 ? 12 : 20) << (TARGET_64BIT ? 1 : 0)) | |
b6c9286a | 1282 | |
4697a36c | 1283 | /* Align an address */ |
4f59f9f2 | 1284 | #define RS6000_ALIGN(n,a) ROUND_UP ((n), (a)) |
4697a36c | 1285 | |
f045b2c9 RS |
1286 | /* Offset within stack frame to start allocating local variables at. |
1287 | If FRAME_GROWS_DOWNWARD, this is the offset to the END of the | |
1288 | first local allocated. Otherwise, it is the offset to the BEGINNING | |
c81bebd7 | 1289 | of the first local allocated. |
f045b2c9 RS |
1290 | |
1291 | On the RS/6000, the frame pointer is the same as the stack pointer, | |
1292 | except for dynamic allocations. So we start after the fixed area and | |
a7790c71 DV |
1293 | outgoing parameter area. |
1294 | ||
1295 | If the function uses dynamic stack space (CALLS_ALLOCA is set), that | |
1296 | space needs to be aligned to STACK_BOUNDARY, i.e. the sum of the | |
1297 | sizes of the fixed area and the parameter area must be a multiple of | |
1298 | STACK_BOUNDARY. */ | |
f045b2c9 | 1299 | |
2a31c321 RS |
1300 | #define RS6000_STARTING_FRAME_OFFSET \ |
1301 | (cfun->calls_alloca \ | |
1302 | ? (RS6000_ALIGN (crtl->outgoing_args_size + RS6000_SAVE_AREA, \ | |
1303 | (TARGET_ALTIVEC || TARGET_VSX) ? 16 : 8 )) \ | |
1304 | : (RS6000_ALIGN (crtl->outgoing_args_size, \ | |
1305 | (TARGET_ALTIVEC || TARGET_VSX) ? 16 : 8) \ | |
1306 | + RS6000_SAVE_AREA)) | |
802a0058 MM |
1307 | |
1308 | /* Offset from the stack pointer register to an item dynamically | |
1309 | allocated on the stack, e.g., by `alloca'. | |
1310 | ||
1311 | The default value for this macro is `STACK_POINTER_OFFSET' plus the | |
1312 | length of the outgoing arguments. The default is correct for most | |
e53b6e56 | 1313 | machines. See `function.cc' for details. |
a7790c71 DV |
1314 | |
1315 | This value must be a multiple of STACK_BOUNDARY (hard coded in | |
e53b6e56 | 1316 | `emit-rtl.cc'). */ |
802a0058 | 1317 | #define STACK_DYNAMIC_OFFSET(FUNDECL) \ |
a20c5714 RS |
1318 | RS6000_ALIGN (crtl->outgoing_args_size.to_constant () \ |
1319 | + STACK_POINTER_OFFSET, \ | |
a7790c71 | 1320 | (TARGET_ALTIVEC || TARGET_VSX) ? 16 : 8) |
f045b2c9 RS |
1321 | |
1322 | /* If we generate an insn to push BYTES bytes, | |
1323 | this says how many the stack pointer really advances by. | |
1324 | On RS/6000, don't define this because there are no push insns. */ | |
1325 | /* #define PUSH_ROUNDING(BYTES) */ | |
1326 | ||
1327 | /* Offset of first parameter from the argument pointer register value. | |
1328 | On the RS/6000, we define the argument pointer to the start of the fixed | |
1329 | area. */ | |
4697a36c | 1330 | #define FIRST_PARM_OFFSET(FNDECL) RS6000_SAVE_AREA |
f045b2c9 | 1331 | |
62153b61 JM |
1332 | /* Offset from the argument pointer register value to the top of |
1333 | stack. This is different from FIRST_PARM_OFFSET because of the | |
1334 | register save area. */ | |
1335 | #define ARG_POINTER_CFA_OFFSET(FNDECL) 0 | |
1336 | ||
f045b2c9 RS |
1337 | /* Define this if stack space is still allocated for a parameter passed |
1338 | in a register. The value is the number of bytes allocated to this | |
1339 | area. */ | |
ddbb449f AM |
1340 | #define REG_PARM_STACK_SPACE(FNDECL) \ |
1341 | rs6000_reg_parm_stack_space ((FNDECL), false) | |
1342 | ||
1343 | /* Define this macro if space guaranteed when compiling a function body | |
1344 | is different to space required when making a call, a situation that | |
1345 | can arise with K&R style function definitions. */ | |
1346 | #define INCOMING_REG_PARM_STACK_SPACE(FNDECL) \ | |
1347 | rs6000_reg_parm_stack_space ((FNDECL), true) | |
f045b2c9 RS |
1348 | |
1349 | /* Define this if the above stack space is to be considered part of the | |
1350 | space allocated by the caller. */ | |
81464b2c | 1351 | #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1 |
f045b2c9 RS |
1352 | |
1353 | /* This is the difference between the logical top of stack and the actual sp. | |
1354 | ||
82e41834 | 1355 | For the RS/6000, sp points past the fixed area. */ |
4697a36c | 1356 | #define STACK_POINTER_OFFSET RS6000_SAVE_AREA |
f045b2c9 RS |
1357 | |
1358 | /* Define this if the maximum size of all the outgoing args is to be | |
1359 | accumulated and pushed during the prologue. The amount can be | |
38173d38 | 1360 | found in the variable crtl->outgoing_args_size. */ |
f73ad30e | 1361 | #define ACCUMULATE_OUTGOING_ARGS 1 |
f045b2c9 | 1362 | |
f045b2c9 RS |
1363 | /* Define how to find the value returned by a library function |
1364 | assuming the value has mode MODE. */ | |
1365 | ||
ded9bf77 | 1366 | #define LIBCALL_VALUE(MODE) rs6000_libcall_value ((MODE)) |
f045b2c9 | 1367 | |
6fa3f289 ZW |
1368 | /* DRAFT_V4_STRUCT_RET defaults off. */ |
1369 | #define DRAFT_V4_STRUCT_RET 0 | |
f607bc57 | 1370 | |
bd5bd7ac | 1371 | /* Let TARGET_RETURN_IN_MEMORY control what happens. */ |
f607bc57 | 1372 | #define DEFAULT_PCC_STRUCT_RETURN 0 |
f045b2c9 | 1373 | |
a260abc9 | 1374 | /* Mode of stack savearea. |
dfdfa60f DE |
1375 | FUNCTION is VOIDmode because calling convention maintains SP. |
1376 | BLOCK needs Pmode for SP. | |
a260abc9 DE |
1377 | NONLOCAL needs twice Pmode to maintain both backchain and SP. */ |
1378 | #define STACK_SAVEAREA_MODE(LEVEL) \ | |
dfdfa60f | 1379 | (LEVEL == SAVE_FUNCTION ? VOIDmode \ |
c6d5ff83 | 1380 | : LEVEL == SAVE_NONLOCAL ? (TARGET_32BIT ? DImode : PTImode) : Pmode) |
a260abc9 | 1381 | |
4697a36c MM |
1382 | /* Minimum and maximum general purpose registers used to hold arguments. */ |
1383 | #define GP_ARG_MIN_REG 3 | |
1384 | #define GP_ARG_MAX_REG 10 | |
1385 | #define GP_ARG_NUM_REG (GP_ARG_MAX_REG - GP_ARG_MIN_REG + 1) | |
1386 | ||
1387 | /* Minimum and maximum floating point registers used to hold arguments. */ | |
1388 | #define FP_ARG_MIN_REG 33 | |
7509c759 MM |
1389 | #define FP_ARG_AIX_MAX_REG 45 |
1390 | #define FP_ARG_V4_MAX_REG 40 | |
008e32c0 UW |
1391 | #define FP_ARG_MAX_REG (DEFAULT_ABI == ABI_V4 \ |
1392 | ? FP_ARG_V4_MAX_REG : FP_ARG_AIX_MAX_REG) | |
4697a36c MM |
1393 | #define FP_ARG_NUM_REG (FP_ARG_MAX_REG - FP_ARG_MIN_REG + 1) |
1394 | ||
0ac081f6 AH |
1395 | /* Minimum and maximum AltiVec registers used to hold arguments. */ |
1396 | #define ALTIVEC_ARG_MIN_REG (FIRST_ALTIVEC_REGNO + 2) | |
1397 | #define ALTIVEC_ARG_MAX_REG (ALTIVEC_ARG_MIN_REG + 11) | |
1398 | #define ALTIVEC_ARG_NUM_REG (ALTIVEC_ARG_MAX_REG - ALTIVEC_ARG_MIN_REG + 1) | |
1399 | ||
b54214fe UW |
1400 | /* Maximum number of registers per ELFv2 homogeneous aggregate argument. */ |
1401 | #define AGGR_ARG_NUM_REG 8 | |
1402 | ||
4697a36c MM |
1403 | /* Return registers */ |
1404 | #define GP_ARG_RETURN GP_ARG_MIN_REG | |
1405 | #define FP_ARG_RETURN FP_ARG_MIN_REG | |
0ac081f6 | 1406 | #define ALTIVEC_ARG_RETURN (FIRST_ALTIVEC_REGNO + 2) |
b54214fe UW |
1407 | #define FP_ARG_MAX_RETURN (DEFAULT_ABI != ABI_ELFv2 ? FP_ARG_RETURN \ |
1408 | : (FP_ARG_RETURN + AGGR_ARG_NUM_REG - 1)) | |
4304ccfd MM |
1409 | #define ALTIVEC_ARG_MAX_RETURN (DEFAULT_ABI != ABI_ELFv2 \ |
1410 | ? (ALTIVEC_ARG_RETURN \ | |
08213983 | 1411 | + (TARGET_FLOAT128_TYPE ? 1 : 0)) \ |
b54214fe | 1412 | : (ALTIVEC_ARG_RETURN + AGGR_ARG_NUM_REG - 1)) |
4697a36c | 1413 | |
7509c759 | 1414 | /* Flags for the call/call_value rtl operations set up by function_arg */ |
6a4cee5f | 1415 | #define CALL_NORMAL 0x00000000 /* no special processing */ |
9ebbca7d | 1416 | /* Bits in 0x00000001 are unused. */ |
6a4cee5f MM |
1417 | #define CALL_V4_CLEAR_FP_ARGS 0x00000002 /* V.4, no FP args passed */ |
1418 | #define CALL_V4_SET_FP_ARGS 0x00000004 /* V.4, FP args were passed */ | |
1419 | #define CALL_LONG 0x00000008 /* always call indirect */ | |
b9599e46 | 1420 | #define CALL_LIBCALL 0x00000010 /* libcall */ |
7509c759 | 1421 | |
e800d6dc BS |
1422 | /* Identify PLT sequence for rs6000_pltseq_template. */ |
1423 | enum rs6000_pltseq_enum { | |
1424 | RS6000_PLTSEQ_TOCSAVE, | |
1425 | RS6000_PLTSEQ_PLT16_HA, | |
1426 | RS6000_PLTSEQ_PLT16_LO, | |
1427 | RS6000_PLTSEQ_MTCTR, | |
1428 | RS6000_PLTSEQ_PLT_PCREL34 | |
1429 | }; | |
1430 | ||
61ee0966 AM |
1431 | #define IS_V4_FP_ARGS(OP) \ |
1432 | ((INTVAL (OP) & (CALL_V4_CLEAR_FP_ARGS | CALL_V4_SET_FP_ARGS)) != 0) | |
1433 | ||
f57fe068 AM |
1434 | /* We don't have prologue and epilogue functions to save/restore |
1435 | everything for most ABIs. */ | |
1436 | #define WORLD_SAVE_P(INFO) 0 | |
1437 | ||
f045b2c9 RS |
1438 | /* 1 if N is a possible register number for a function value |
1439 | as seen by the caller. | |
1440 | ||
0ac081f6 | 1441 | On RS/6000, this is r3, fp1, and v2 (for AltiVec). */ |
e87a88d3 AM |
1442 | #define FUNCTION_VALUE_REGNO_P(N) \ |
1443 | ((N) == GP_ARG_RETURN \ | |
202687fb | 1444 | || (IN_RANGE ((N), FP_ARG_RETURN, FP_ARG_MAX_RETURN) \ |
11d8d07e | 1445 | && TARGET_HARD_FLOAT) \ |
202687fb | 1446 | || (IN_RANGE ((N), ALTIVEC_ARG_RETURN, ALTIVEC_ARG_MAX_RETURN) \ |
b54214fe | 1447 | && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI)) |
f045b2c9 RS |
1448 | |
1449 | /* 1 if N is a possible register number for function argument passing. | |
0ac081f6 AH |
1450 | On RS/6000, these are r3-r10 and fp1-fp13. |
1451 | On AltiVec, v2 - v13 are used for passing vectors. */ | |
4697a36c | 1452 | #define FUNCTION_ARG_REGNO_P(N) \ |
202687fb MM |
1453 | (IN_RANGE ((N), GP_ARG_MIN_REG, GP_ARG_MAX_REG) \ |
1454 | || (IN_RANGE ((N), ALTIVEC_ARG_MIN_REG, ALTIVEC_ARG_MAX_REG) \ | |
44688022 | 1455 | && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI) \ |
202687fb | 1456 | || (IN_RANGE ((N), FP_ARG_MIN_REG, FP_ARG_MAX_REG) \ |
11d8d07e | 1457 | && TARGET_HARD_FLOAT)) |
f045b2c9 RS |
1458 | \f |
1459 | /* Define a data type for recording info about an argument list | |
1460 | during the scan of that argument list. This data type should | |
1461 | hold all necessary information about the function itself | |
1462 | and about the args processed so far, enough to enable macros | |
1463 | such as FUNCTION_ARG to determine where the next arg should go. | |
1464 | ||
1465 | On the RS/6000, this is a structure. The first element is the number of | |
1466 | total argument words, the second is used to store the next | |
1467 | floating-point register number, and the third says how many more args we | |
4697a36c MM |
1468 | have prototype types for. |
1469 | ||
4cc833b7 | 1470 | For ABI_V4, we treat these slightly differently -- `sysv_gregno' is |
07488f32 | 1471 | the next available GP register, `fregno' is the next available FP |
4cc833b7 RH |
1472 | register, and `words' is the number of words used on the stack. |
1473 | ||
bd227acc | 1474 | The varargs/stdarg support requires that this structure's size |
4cc833b7 | 1475 | be a multiple of sizeof(int). */ |
4697a36c MM |
1476 | |
1477 | typedef struct rs6000_args | |
1478 | { | |
4cc833b7 | 1479 | int words; /* # words used for passing GP registers */ |
6a4cee5f | 1480 | int fregno; /* next available FP register */ |
0ac081f6 | 1481 | int vregno; /* next available AltiVec register */ |
6a4cee5f | 1482 | int nargs_prototype; /* # args left in the current prototype */ |
6a4cee5f | 1483 | int prototype; /* Whether a prototype was defined */ |
a6c9bed4 | 1484 | int stdarg; /* Whether function is a stdarg function. */ |
6a4cee5f | 1485 | int call_cookie; /* Do special things for this call */ |
4cc833b7 | 1486 | int sysv_gregno; /* next available GP register */ |
0b5383eb DJ |
1487 | int intoffset; /* running offset in struct (darwin64) */ |
1488 | int use_stack; /* any part of struct on stack (darwin64) */ | |
a9ab25e2 IS |
1489 | int floats_in_gpr; /* count of SFmode floats taking up |
1490 | GPR space (darwin64) */ | |
0b5383eb | 1491 | int named; /* false for varargs params */ |
617718f7 | 1492 | int escapes; /* if function visible outside tu */ |
bdb60a10 | 1493 | int libcall; /* If this is a compiler generated call. */ |
4697a36c | 1494 | } CUMULATIVE_ARGS; |
f045b2c9 | 1495 | |
f045b2c9 RS |
1496 | /* Initialize a variable CUM of type CUMULATIVE_ARGS |
1497 | for a call to a function whose data type is FNTYPE. | |
1498 | For a library call, FNTYPE is 0. */ | |
1499 | ||
617718f7 AM |
1500 | #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \ |
1501 | init_cumulative_args (&CUM, FNTYPE, LIBNAME, FALSE, FALSE, \ | |
1502 | N_NAMED_ARGS, FNDECL, VOIDmode) | |
f045b2c9 RS |
1503 | |
1504 | /* Similar, but when scanning the definition of a procedure. We always | |
1505 | set NARGS_PROTOTYPE large so we never return an EXPR_LIST. */ | |
1506 | ||
0f6937fe | 1507 | #define INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME) \ |
617718f7 AM |
1508 | init_cumulative_args (&CUM, FNTYPE, LIBNAME, TRUE, FALSE, \ |
1509 | 1000, current_function_decl, VOIDmode) | |
b9599e46 FS |
1510 | |
1511 | /* Like INIT_CUMULATIVE_ARGS' but only used for outgoing libcalls. */ | |
1512 | ||
1513 | #define INIT_CUMULATIVE_LIBCALL_ARGS(CUM, MODE, LIBNAME) \ | |
617718f7 AM |
1514 | init_cumulative_args (&CUM, NULL_TREE, LIBNAME, FALSE, TRUE, \ |
1515 | 0, NULL_TREE, MODE) | |
f045b2c9 | 1516 | |
6e985040 | 1517 | #define PAD_VARARGS_DOWN \ |
76b0cbf8 | 1518 | (targetm.calls.function_arg_padding (TYPE_MODE (type), type) == PAD_DOWNWARD) |
2a55fd42 | 1519 | |
f045b2c9 | 1520 | /* Output assembler code to FILE to increment profiler label # LABELNO |
58a39e45 | 1521 | for profiling a function entry. */ |
f045b2c9 RS |
1522 | |
1523 | #define FUNCTION_PROFILER(FILE, LABELNO) \ | |
58a39e45 | 1524 | output_function_profiler ((FILE), (LABELNO)); |
f045b2c9 RS |
1525 | |
1526 | /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, | |
1527 | the stack pointer does not matter. No definition is equivalent to | |
1528 | always zero. | |
1529 | ||
a0ab749a | 1530 | On the RS/6000, this is nonzero because we can restore the stack from |
f045b2c9 RS |
1531 | its backpointer, which we maintain. */ |
1532 | #define EXIT_IGNORE_STACK 1 | |
1533 | ||
a701949a FS |
1534 | /* Define this macro as a C expression that is nonzero for registers |
1535 | that are used by the epilogue or the return' pattern. The stack | |
1536 | and frame pointer registers are already be assumed to be used as | |
1537 | needed. */ | |
1538 | ||
83720594 | 1539 | #define EPILOGUE_USES(REGNO) \ |
1de43f85 | 1540 | ((reload_completed && (REGNO) == LR_REGNO) \ |
b1765bde | 1541 | || (TARGET_ALTIVEC && (REGNO) == VRSAVE_REGNO) \ |
cacf1ca8 | 1542 | || (crtl->calls_eh_return \ |
3553b09d | 1543 | && TARGET_AIX \ |
ff3867ae | 1544 | && (REGNO) == 2)) |
2bfcf297 | 1545 | |
f045b2c9 | 1546 | \f |
f045b2c9 RS |
1547 | /* Length in units of the trampoline for entering a nested function. */ |
1548 | ||
b6c9286a | 1549 | #define TRAMPOLINE_SIZE rs6000_trampoline_size () |
f045b2c9 | 1550 | \f |
f33985c6 | 1551 | /* Definitions for __builtin_return_address and __builtin_frame_address. |
893fc0a0 | 1552 | __builtin_return_address (0) should give link register (LR_REGNO), enable |
82e41834 | 1553 | this. */ |
f33985c6 MS |
1554 | /* This should be uncommented, so that the link register is used, but |
1555 | currently this would result in unmatched insns and spilling fixed | |
1556 | registers so we'll leave it for another day. When these problems are | |
1557 | taken care of one additional fetch will be necessary in RETURN_ADDR_RTX. | |
1558 | (mrs) */ | |
1559 | /* #define RETURN_ADDR_IN_PREVIOUS_FRAME */ | |
f09d4c33 | 1560 | |
b6c9286a | 1561 | /* Number of bytes into the frame return addresses can be found. See |
e53b6e56 | 1562 | rs6000_stack_info in rs6000.cc for more information on how the different |
b6c9286a | 1563 | abi's store the return address. */ |
008e32c0 UW |
1564 | #define RETURN_ADDRESS_OFFSET \ |
1565 | ((DEFAULT_ABI == ABI_V4 ? 4 : 8) << (TARGET_64BIT ? 1 : 0)) | |
f09d4c33 | 1566 | |
33463137 | 1567 | /* The current return address is in the link register. The return address |
f33985c6 MS |
1568 | of anything farther back is accessed normally at an offset of 8 from the |
1569 | frame pointer. */ | |
71f123ca FS |
1570 | #define RETURN_ADDR_RTX(COUNT, FRAME) \ |
1571 | (rs6000_return_addr (COUNT, FRAME)) | |
1572 | ||
f33985c6 | 1573 | \f |
f045b2c9 RS |
1574 | /* Definitions for register eliminations. |
1575 | ||
1576 | We have two registers that can be eliminated on the RS/6000. First, the | |
1577 | frame pointer register can often be eliminated in favor of the stack | |
1578 | pointer register. Secondly, the argument pointer register can always be | |
642a35f1 JW |
1579 | eliminated; it is replaced with either the stack or frame pointer. |
1580 | ||
1581 | In addition, we use the elimination mechanism to see if r30 is needed | |
1582 | Initially we assume that it isn't. If it is, we spill it. This is done | |
1583 | by making it an eliminable register. We replace it with itself so that | |
1584 | if it isn't needed, then existing uses won't be modified. */ | |
f045b2c9 RS |
1585 | |
1586 | /* This is an array of structures. Each structure initializes one pair | |
1587 | of eliminable registers. The "from" register number is given first, | |
1588 | followed by "to". Eliminations of the same "from" register are listed | |
1589 | in order of preference. */ | |
7d5175e1 JJ |
1590 | #define ELIMINABLE_REGS \ |
1591 | {{ HARD_FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
1592 | { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
1593 | { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ | |
1594 | { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
1595 | { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ | |
97b23853 | 1596 | { RS6000_PIC_OFFSET_TABLE_REGNUM, RS6000_PIC_OFFSET_TABLE_REGNUM } } |
f045b2c9 | 1597 | |
f045b2c9 RS |
1598 | /* Define the offset between two registers, one to be eliminated, and the other |
1599 | its replacement, at the start of a routine. */ | |
d1d0c603 JJ |
1600 | #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ |
1601 | ((OFFSET) = rs6000_initial_elimination_offset(FROM, TO)) | |
f045b2c9 RS |
1602 | \f |
1603 | /* Addressing modes, and classification of registers for them. */ | |
1604 | ||
940da324 JL |
1605 | #define HAVE_PRE_DECREMENT 1 |
1606 | #define HAVE_PRE_INCREMENT 1 | |
6fb5fa3c DB |
1607 | #define HAVE_PRE_MODIFY_DISP 1 |
1608 | #define HAVE_PRE_MODIFY_REG 1 | |
f045b2c9 RS |
1609 | |
1610 | /* Macros to check register numbers against specific register classes. */ | |
1611 | ||
1612 | /* These assume that REGNO is a hard or pseudo reg number. | |
1613 | They give nonzero only if REGNO is a hard reg of the suitable class | |
1614 | or a pseudo reg currently allocated to a suitable hard reg. | |
1615 | Since they use reg_renumber, they are safe only once reg_renumber | |
e53b6e56 | 1616 | has been allocated, which happens in reginfo.cc during register |
aeb9f7cf | 1617 | allocation. */ |
f045b2c9 RS |
1618 | |
1619 | #define REGNO_OK_FOR_INDEX_P(REGNO) \ | |
2e42a52f | 1620 | (HARD_REGISTER_NUM_P (REGNO) \ |
33463137 SB |
1621 | ? (REGNO) <= 31 \ |
1622 | || (REGNO) == ARG_POINTER_REGNUM \ | |
7d5175e1 | 1623 | || (REGNO) == FRAME_POINTER_REGNUM \ |
f045b2c9 | 1624 | : (reg_renumber[REGNO] >= 0 \ |
33463137 SB |
1625 | && (reg_renumber[REGNO] <= 31 \ |
1626 | || reg_renumber[REGNO] == ARG_POINTER_REGNUM \ | |
7d5175e1 | 1627 | || reg_renumber[REGNO] == FRAME_POINTER_REGNUM))) |
f045b2c9 RS |
1628 | |
1629 | #define REGNO_OK_FOR_BASE_P(REGNO) \ | |
2e42a52f | 1630 | (HARD_REGISTER_NUM_P (REGNO) \ |
33463137 SB |
1631 | ? ((REGNO) > 0 && (REGNO) <= 31) \ |
1632 | || (REGNO) == ARG_POINTER_REGNUM \ | |
7d5175e1 | 1633 | || (REGNO) == FRAME_POINTER_REGNUM \ |
f045b2c9 | 1634 | : (reg_renumber[REGNO] > 0 \ |
33463137 SB |
1635 | && (reg_renumber[REGNO] <= 31 \ |
1636 | || reg_renumber[REGNO] == ARG_POINTER_REGNUM \ | |
7d5175e1 | 1637 | || reg_renumber[REGNO] == FRAME_POINTER_REGNUM))) |
c6c3dba9 PB |
1638 | |
1639 | /* Nonzero if X is a hard reg that can be used as an index | |
1640 | or if it is a pseudo reg in the non-strict case. */ | |
1641 | #define INT_REG_OK_FOR_INDEX_P(X, STRICT) \ | |
2e42a52f | 1642 | ((!(STRICT) && !HARD_REGISTER_P (X)) \ |
c6c3dba9 PB |
1643 | || REGNO_OK_FOR_INDEX_P (REGNO (X))) |
1644 | ||
1645 | /* Nonzero if X is a hard reg that can be used as a base reg | |
1646 | or if it is a pseudo reg in the non-strict case. */ | |
1647 | #define INT_REG_OK_FOR_BASE_P(X, STRICT) \ | |
2e42a52f | 1648 | ((!(STRICT) && !HARD_REGISTER_P (X)) \ |
c6c3dba9 PB |
1649 | || REGNO_OK_FOR_BASE_P (REGNO (X))) |
1650 | ||
f045b2c9 RS |
1651 | \f |
1652 | /* Maximum number of registers that can appear in a valid memory address. */ | |
1653 | ||
1654 | #define MAX_REGS_PER_ADDRESS 2 | |
1655 | ||
1656 | /* Recognize any constant value that is a valid address. */ | |
1657 | ||
6eff269e | 1658 | #define CONSTANT_ADDRESS_P(X) \ |
2e42a52f PB |
1659 | (GET_CODE (X) == LABEL_REF || SYMBOL_REF_P (X) \ |
1660 | || CONST_INT_P (X) || GET_CODE (X) == CONST \ | |
6eff269e | 1661 | || GET_CODE (X) == HIGH) |
f045b2c9 | 1662 | |
48d72335 | 1663 | #define EASY_VECTOR_15(n) ((n) >= -16 && (n) <= 15) |
66180ff3 | 1664 | #define EASY_VECTOR_15_ADD_SELF(n) (!EASY_VECTOR_15((n)) \ |
76492753 PB |
1665 | && EASY_VECTOR_15((n) >> 1) \ |
1666 | && ((n) & 1) == 0) | |
48d72335 | 1667 | |
29e6733c | 1668 | #define EASY_VECTOR_MSB(n,mode) \ |
683be46f | 1669 | ((((unsigned HOST_WIDE_INT) (n)) & GET_MODE_MASK (mode)) == \ |
29e6733c MM |
1670 | ((((unsigned HOST_WIDE_INT)GET_MODE_MASK (mode)) + 1) >> 1)) |
1671 | ||
f045b2c9 | 1672 | \f |
944258eb | 1673 | #define FIND_BASE_TERM rs6000_find_base_term |
766a866c MM |
1674 | \f |
1675 | /* The register number of the register used to address a table of | |
1676 | static data addresses in memory. In some cases this register is | |
1677 | defined by a processor's "application binary interface" (ABI). | |
1678 | When this macro is defined, RTL is generated for this register | |
1679 | once, as with the stack pointer and frame pointer registers. If | |
1680 | this macro is not defined, it is up to the machine-dependent files | |
1681 | to allocate such a register (if necessary). */ | |
1682 | ||
1db02437 | 1683 | #define RS6000_PIC_OFFSET_TABLE_REGNUM 30 |
24f77f59 AM |
1684 | #define PIC_OFFSET_TABLE_REGNUM \ |
1685 | (TARGET_TOC ? TOC_REGISTER \ | |
1686 | : flag_pic ? RS6000_PIC_OFFSET_TABLE_REGNUM \ | |
1687 | : INVALID_REGNUM) | |
766a866c | 1688 | |
97b23853 | 1689 | #define TOC_REGISTER (TARGET_MINIMAL_TOC ? RS6000_PIC_OFFSET_TABLE_REGNUM : 2) |
9ebbca7d | 1690 | |
766a866c MM |
1691 | /* Define this macro if the register defined by |
1692 | `PIC_OFFSET_TABLE_REGNUM' is clobbered by calls. Do not define | |
089a05b8 | 1693 | this macro if `PIC_OFFSET_TABLE_REGNUM' is not defined. */ |
766a866c MM |
1694 | |
1695 | /* #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED */ | |
1696 | ||
766a866c MM |
1697 | /* A C expression that is nonzero if X is a legitimate immediate |
1698 | operand on the target machine when generating position independent | |
1699 | code. You can assume that X satisfies `CONSTANT_P', so you need | |
1700 | not check this. You can also assume FLAG_PIC is true, so you need | |
1701 | not check it either. You need not define this macro if all | |
1702 | constants (including `SYMBOL_REF') can be immediate operands when | |
1703 | generating position independent code. */ | |
1704 | ||
1705 | /* #define LEGITIMATE_PIC_OPERAND_P (X) */ | |
f045b2c9 | 1706 | \f |
18543a22 ILT |
1707 | /* Define as C expression which evaluates to nonzero if the tablejump |
1708 | instruction expects the table to contain offsets from the address of the | |
1709 | table. | |
82e41834 | 1710 | Do not define this if the table should contain absolute addresses. */ |
3493b0c3 HG |
1711 | #define CASE_VECTOR_PC_RELATIVE rs6000_relative_jumptables |
1712 | ||
1713 | /* Specify the machine mode that this machine uses | |
1714 | for the index in the tablejump instruction. */ | |
1715 | #define CASE_VECTOR_MODE (rs6000_relative_jumptables ? SImode : Pmode) | |
f045b2c9 | 1716 | |
f045b2c9 RS |
1717 | /* Define this as 1 if `char' should by default be signed; else as 0. */ |
1718 | #define DEFAULT_SIGNED_CHAR 0 | |
1719 | ||
c1618c0c DE |
1720 | /* An integer expression for the size in bits of the largest integer machine |
1721 | mode that should actually be used. */ | |
1722 | ||
1723 | /* Allow pairs of registers to be used, which is the intent of the default. */ | |
1724 | #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_POWERPC64 ? TImode : DImode) | |
1725 | ||
f045b2c9 RS |
1726 | /* Max number of bytes we can move from memory to memory |
1727 | in one reasonably fast instruction. */ | |
2f3e5814 | 1728 | #define MOVE_MAX (! TARGET_POWERPC64 ? 4 : 8) |
7e69e155 | 1729 | #define MAX_MOVE_MAX 8 |
cd295a80 HG |
1730 | #define MOVE_MAX_PIECES (TARGET_EFFICIENT_UNALIGNED_VSX \ |
1731 | ? 16 : (TARGET_POWERPC64 ? 8 : 4)) | |
1732 | #define STORE_MAX_PIECES (TARGET_POWERPC64 ? 8 : 4) | |
f045b2c9 RS |
1733 | |
1734 | /* Nonzero if access to memory by bytes is no faster than for words. | |
a0ab749a | 1735 | Also nonzero if doing byte operations (specifically shifts) in registers |
f045b2c9 RS |
1736 | is undesirable. */ |
1737 | #define SLOW_BYTE_ACCESS 1 | |
1738 | ||
9a63901f RK |
1739 | /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD |
1740 | will either zero-extend or sign-extend. The value of this macro should | |
1741 | be the code that says which one of the two operations is implicitly | |
f822d252 | 1742 | done, UNKNOWN if none. */ |
9a63901f | 1743 | #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND |
225211e2 RK |
1744 | |
1745 | /* Define if loading short immediate values into registers sign extends. */ | |
58f2ae18 | 1746 | #define SHORT_IMMEDIATES_SIGN_EXTEND 1 |
fdaff8ba | 1747 | \f |
94993909 | 1748 | /* The cntlzw and cntlzd instructions return 32 and 64 for input of zero. */ |
d865b122 | 1749 | #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ |
bb0f9c02 | 1750 | ((VALUE) = GET_MODE_BITSIZE (MODE), 2) |
d865b122 | 1751 | |
0299bc72 | 1752 | /* The CTZ patterns that are implemented in terms of CLZ return -1 for input of |
bb0f9c02 SB |
1753 | zero. The hardware instructions added in Power9 and the sequences using |
1754 | popcount return 32 or 64. */ | |
0299bc72 | 1755 | #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ |
bb0f9c02 SB |
1756 | (TARGET_CTZ || TARGET_POPCNTD \ |
1757 | ? ((VALUE) = GET_MODE_BITSIZE (MODE), 2) \ | |
1758 | : ((VALUE) = -1, 2)) | |
94993909 | 1759 | |
f045b2c9 RS |
1760 | /* Specify the machine mode that pointers have. |
1761 | After generation of rtl, the compiler makes no further distinction | |
1762 | between pointers and any other objects of this machine mode. */ | |
501623d4 RS |
1763 | extern scalar_int_mode rs6000_pmode; |
1764 | #define Pmode rs6000_pmode | |
f045b2c9 | 1765 | |
a3c9585f | 1766 | /* Supply definition of STACK_SIZE_MODE for allocate_dynamic_stack_space. */ |
4c81e946 FJ |
1767 | #define STACK_SIZE_MODE (TARGET_32BIT ? SImode : DImode) |
1768 | ||
f045b2c9 | 1769 | /* Mode of a function address in a call instruction (for indexing purposes). |
f045b2c9 | 1770 | Doesn't matter on RS/6000. */ |
5b71a4e7 | 1771 | #define FUNCTION_MODE SImode |
f045b2c9 RS |
1772 | |
1773 | /* Define this if addresses of constant functions | |
1774 | shouldn't be put through pseudo regs where they can be cse'd. | |
1775 | Desirable on machines where ordinary constants are expensive | |
1776 | but a CALL with constant address is cheap. */ | |
1e8552c2 | 1777 | #define NO_FUNCTION_CSE 1 |
f045b2c9 | 1778 | |
d969caf8 | 1779 | /* Define this to be nonzero if shift instructions ignore all but the low-order |
6febd581 RK |
1780 | few bits. |
1781 | ||
1782 | The sle and sre instructions which allow SHIFT_COUNT_TRUNCATED | |
1783 | have been dropped from the PowerPC architecture. */ | |
c28a7c24 | 1784 | #define SHIFT_COUNT_TRUNCATED 0 |
f045b2c9 | 1785 | |
f045b2c9 RS |
1786 | /* Adjust the length of an INSN. LENGTH is the currently-computed length and |
1787 | should be adjusted to reflect any required changes. This macro is used when | |
1788 | there is some systematic length adjustment required that would be difficult | |
ca06b86c MM |
1789 | to express in the length attribute. |
1790 | ||
1791 | In the PowerPC, we use this to adjust the length of an instruction if one or | |
1792 | more prefixed instructions are generated, using the attribute | |
1793 | num_prefixed_insns. A prefixed instruction is 8 bytes instead of 4, but the | |
1794 | hardware requires that a prefied instruciton does not cross a 64-byte | |
1795 | boundary. This means the compiler has to assume the length of the first | |
1796 | prefixed instruction is 12 bytes instead of 8 bytes. Since the length is | |
1797 | already set for the non-prefixed instruction, we just need to udpate for the | |
1798 | difference. */ | |
1799 | ||
1800 | #define ADJUST_INSN_LENGTH(INSN,LENGTH) \ | |
1801 | (LENGTH) = rs6000_adjust_insn_length ((INSN), (LENGTH)) | |
f045b2c9 | 1802 | |
39a10a29 GK |
1803 | /* Given a comparison code (EQ, NE, etc.) and the first operand of a |
1804 | COMPARE, return the mode to be used for the comparison. For | |
1805 | floating-point, CCFPmode should be used. CCUNSmode should be used | |
1806 | for unsigned comparisons. CCEQmode should be used when we are | |
1807 | doing an inequality comparison on the result of a | |
1808 | comparison. CCmode should be used in all other cases. */ | |
c5defebb | 1809 | |
b565a316 | 1810 | #define SELECT_CC_MODE(OP,X,Y) \ |
ebb109ad | 1811 | (SCALAR_FLOAT_MODE_P (GET_MODE (X)) ? CCFPmode \ |
c5defebb | 1812 | : (OP) == GTU || (OP) == LTU || (OP) == GEU || (OP) == LEU ? CCUNSmode \ |
ec8e098d | 1813 | : (((OP) == EQ || (OP) == NE) && COMPARISON_P (X) \ |
c5defebb | 1814 | ? CCEQmode : CCmode)) |
f045b2c9 | 1815 | |
b39358e1 GK |
1816 | /* Can the condition code MODE be safely reversed? This is safe in |
1817 | all cases on this port, because at present it doesn't use the | |
1818 | trapping FP comparisons (fcmpo). */ | |
1819 | #define REVERSIBLE_CC_MODE(MODE) 1 | |
1820 | ||
1821 | /* Given a condition code and a mode, return the inverse condition. */ | |
1822 | #define REVERSE_CONDITION(CODE, MODE) rs6000_reverse_condition (MODE, CODE) | |
1823 | ||
d9664254 SB |
1824 | \f |
1825 | /* Target cpu costs. */ | |
1826 | ||
1827 | struct processor_costs { | |
1828 | const int mulsi; /* cost of SImode multiplication. */ | |
1829 | const int mulsi_const; /* cost of SImode multiplication by constant. */ | |
1830 | const int mulsi_const9; /* cost of SImode mult by short constant. */ | |
1831 | const int muldi; /* cost of DImode multiplication. */ | |
1832 | const int divsi; /* cost of SImode division. */ | |
1833 | const int divdi; /* cost of DImode division. */ | |
1834 | const int fp; /* cost of simple SFmode and DFmode insns. */ | |
1835 | const int dmul; /* cost of DFmode multiplication (and fmadd). */ | |
1836 | const int sdiv; /* cost of SFmode division (fdivs). */ | |
1837 | const int ddiv; /* cost of DFmode division (fdiv). */ | |
1838 | const int cache_line_size; /* cache line size in bytes. */ | |
1839 | const int l1_cache_size; /* size of l1 cache, in kilobytes. */ | |
1840 | const int l2_cache_size; /* size of l2 cache, in kilobytes. */ | |
1841 | const int simultaneous_prefetches; /* number of parallel prefetch | |
1842 | operations. */ | |
1843 | const int sfdf_convert; /* cost of SF->DF conversion. */ | |
1844 | }; | |
1845 | ||
1846 | extern const struct processor_costs *rs6000_cost; | |
f045b2c9 RS |
1847 | \f |
1848 | /* Control the assembler format that we output. */ | |
1849 | ||
1b279f39 DE |
1850 | /* A C string constant describing how to begin a comment in the target |
1851 | assembler language. The compiler assumes that the comment will end at | |
1852 | the end of the line. */ | |
1853 | #define ASM_COMMENT_START " #" | |
6b67933e | 1854 | |
38c1f2d7 MM |
1855 | /* Flag to say the TOC is initialized */ |
1856 | extern int toc_initialized; | |
1857 | ||
f045b2c9 RS |
1858 | /* Macro to output a special constant pool entry. Go to WIN if we output |
1859 | it. Otherwise, it is written the usual way. | |
1860 | ||
1861 | On the RS/6000, toc entries are handled this way. */ | |
1862 | ||
a9098fd0 GK |
1863 | #define ASM_OUTPUT_SPECIAL_POOL_ENTRY(FILE, X, MODE, ALIGN, LABELNO, WIN) \ |
1864 | { if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (X, MODE)) \ | |
1865 | { \ | |
1866 | output_toc (FILE, X, LABELNO, MODE); \ | |
1867 | goto WIN; \ | |
1868 | } \ | |
f045b2c9 RS |
1869 | } |
1870 | ||
ebd97b96 DE |
1871 | #ifdef HAVE_GAS_WEAK |
1872 | #define RS6000_WEAK 1 | |
1873 | #else | |
1874 | #define RS6000_WEAK 0 | |
1875 | #endif | |
290ad355 | 1876 | |
79c4e63f AM |
1877 | #if RS6000_WEAK |
1878 | /* Used in lieu of ASM_WEAKEN_LABEL. */ | |
8d91472f DE |
1879 | #define ASM_WEAKEN_DECL(FILE, DECL, NAME, VAL) \ |
1880 | rs6000_asm_weaken_decl ((FILE), (DECL), (NAME), (VAL)) | |
79c4e63f AM |
1881 | #endif |
1882 | ||
ff2d10c1 AO |
1883 | #if HAVE_GAS_WEAKREF |
1884 | #define ASM_OUTPUT_WEAKREF(FILE, DECL, NAME, VALUE) \ | |
1885 | do \ | |
1886 | { \ | |
1887 | fputs ("\t.weakref\t", (FILE)); \ | |
1888 | RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \ | |
1889 | fputs (", ", (FILE)); \ | |
1890 | RS6000_OUTPUT_BASENAME ((FILE), (VALUE)); \ | |
1891 | if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \ | |
1892 | && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \ | |
1893 | { \ | |
1894 | fputs ("\n\t.weakref\t.", (FILE)); \ | |
1895 | RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \ | |
1896 | fputs (", .", (FILE)); \ | |
1897 | RS6000_OUTPUT_BASENAME ((FILE), (VALUE)); \ | |
1898 | } \ | |
1899 | fputc ('\n', (FILE)); \ | |
1900 | } while (0) | |
1901 | #endif | |
1902 | ||
79c4e63f AM |
1903 | /* This implements the `alias' attribute. */ |
1904 | #undef ASM_OUTPUT_DEF_FROM_DECLS | |
1905 | #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL, TARGET) \ | |
1906 | do \ | |
1907 | { \ | |
1908 | const char *alias = XSTR (XEXP (DECL_RTL (DECL), 0), 0); \ | |
1909 | const char *name = IDENTIFIER_POINTER (TARGET); \ | |
1910 | if (TREE_CODE (DECL) == FUNCTION_DECL \ | |
85b776df | 1911 | && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \ |
79c4e63f AM |
1912 | { \ |
1913 | if (TREE_PUBLIC (DECL)) \ | |
1914 | { \ | |
1915 | if (!RS6000_WEAK || !DECL_WEAK (DECL)) \ | |
1916 | { \ | |
1917 | fputs ("\t.globl\t.", FILE); \ | |
cbaaba19 | 1918 | RS6000_OUTPUT_BASENAME (FILE, alias); \ |
79c4e63f AM |
1919 | putc ('\n', FILE); \ |
1920 | } \ | |
1921 | } \ | |
1922 | else if (TARGET_XCOFF) \ | |
1923 | { \ | |
c167bc5b DE |
1924 | if (!RS6000_WEAK || !DECL_WEAK (DECL)) \ |
1925 | { \ | |
1926 | fputs ("\t.lglobl\t.", FILE); \ | |
1927 | RS6000_OUTPUT_BASENAME (FILE, alias); \ | |
1928 | putc ('\n', FILE); \ | |
1929 | fputs ("\t.lglobl\t", FILE); \ | |
1930 | RS6000_OUTPUT_BASENAME (FILE, alias); \ | |
1931 | putc ('\n', FILE); \ | |
1932 | } \ | |
79c4e63f AM |
1933 | } \ |
1934 | fputs ("\t.set\t.", FILE); \ | |
cbaaba19 | 1935 | RS6000_OUTPUT_BASENAME (FILE, alias); \ |
79c4e63f | 1936 | fputs (",.", FILE); \ |
cbaaba19 | 1937 | RS6000_OUTPUT_BASENAME (FILE, name); \ |
79c4e63f AM |
1938 | fputc ('\n', FILE); \ |
1939 | } \ | |
1940 | ASM_OUTPUT_DEF (FILE, alias, name); \ | |
1941 | } \ | |
1942 | while (0) | |
290ad355 | 1943 | |
1bc7c5b6 ZW |
1944 | #define TARGET_ASM_FILE_START rs6000_file_start |
1945 | ||
f045b2c9 RS |
1946 | /* Output to assembler file text saying following lines |
1947 | may contain character constants, extra white space, comments, etc. */ | |
1948 | ||
1949 | #define ASM_APP_ON "" | |
1950 | ||
1951 | /* Output to assembler file text saying following lines | |
1952 | no longer contain unusual constructs. */ | |
1953 | ||
1954 | #define ASM_APP_OFF "" | |
1955 | ||
f045b2c9 RS |
1956 | /* How to refer to registers in assembler output. |
1957 | This sequence is indexed by compiler's hard-register-number (see above). */ | |
1958 | ||
82e41834 | 1959 | extern char rs6000_reg_names[][8]; /* register names (0 vs. %r0). */ |
c81bebd7 MM |
1960 | |
1961 | #define REGISTER_NAMES \ | |
1962 | { \ | |
1963 | &rs6000_reg_names[ 0][0], /* r0 */ \ | |
1964 | &rs6000_reg_names[ 1][0], /* r1 */ \ | |
33463137 | 1965 | &rs6000_reg_names[ 2][0], /* r2 */ \ |
c81bebd7 MM |
1966 | &rs6000_reg_names[ 3][0], /* r3 */ \ |
1967 | &rs6000_reg_names[ 4][0], /* r4 */ \ | |
1968 | &rs6000_reg_names[ 5][0], /* r5 */ \ | |
1969 | &rs6000_reg_names[ 6][0], /* r6 */ \ | |
1970 | &rs6000_reg_names[ 7][0], /* r7 */ \ | |
1971 | &rs6000_reg_names[ 8][0], /* r8 */ \ | |
1972 | &rs6000_reg_names[ 9][0], /* r9 */ \ | |
1973 | &rs6000_reg_names[10][0], /* r10 */ \ | |
1974 | &rs6000_reg_names[11][0], /* r11 */ \ | |
1975 | &rs6000_reg_names[12][0], /* r12 */ \ | |
1976 | &rs6000_reg_names[13][0], /* r13 */ \ | |
1977 | &rs6000_reg_names[14][0], /* r14 */ \ | |
1978 | &rs6000_reg_names[15][0], /* r15 */ \ | |
1979 | &rs6000_reg_names[16][0], /* r16 */ \ | |
1980 | &rs6000_reg_names[17][0], /* r17 */ \ | |
1981 | &rs6000_reg_names[18][0], /* r18 */ \ | |
1982 | &rs6000_reg_names[19][0], /* r19 */ \ | |
1983 | &rs6000_reg_names[20][0], /* r20 */ \ | |
1984 | &rs6000_reg_names[21][0], /* r21 */ \ | |
1985 | &rs6000_reg_names[22][0], /* r22 */ \ | |
1986 | &rs6000_reg_names[23][0], /* r23 */ \ | |
1987 | &rs6000_reg_names[24][0], /* r24 */ \ | |
1988 | &rs6000_reg_names[25][0], /* r25 */ \ | |
1989 | &rs6000_reg_names[26][0], /* r26 */ \ | |
1990 | &rs6000_reg_names[27][0], /* r27 */ \ | |
1991 | &rs6000_reg_names[28][0], /* r28 */ \ | |
1992 | &rs6000_reg_names[29][0], /* r29 */ \ | |
1993 | &rs6000_reg_names[30][0], /* r30 */ \ | |
1994 | &rs6000_reg_names[31][0], /* r31 */ \ | |
1995 | \ | |
33463137 | 1996 | &rs6000_reg_names[32][0], /* fr0 */ \ |
c81bebd7 MM |
1997 | &rs6000_reg_names[33][0], /* fr1 */ \ |
1998 | &rs6000_reg_names[34][0], /* fr2 */ \ | |
1999 | &rs6000_reg_names[35][0], /* fr3 */ \ | |
2000 | &rs6000_reg_names[36][0], /* fr4 */ \ | |
2001 | &rs6000_reg_names[37][0], /* fr5 */ \ | |
2002 | &rs6000_reg_names[38][0], /* fr6 */ \ | |
2003 | &rs6000_reg_names[39][0], /* fr7 */ \ | |
2004 | &rs6000_reg_names[40][0], /* fr8 */ \ | |
2005 | &rs6000_reg_names[41][0], /* fr9 */ \ | |
2006 | &rs6000_reg_names[42][0], /* fr10 */ \ | |
2007 | &rs6000_reg_names[43][0], /* fr11 */ \ | |
2008 | &rs6000_reg_names[44][0], /* fr12 */ \ | |
2009 | &rs6000_reg_names[45][0], /* fr13 */ \ | |
2010 | &rs6000_reg_names[46][0], /* fr14 */ \ | |
2011 | &rs6000_reg_names[47][0], /* fr15 */ \ | |
2012 | &rs6000_reg_names[48][0], /* fr16 */ \ | |
2013 | &rs6000_reg_names[49][0], /* fr17 */ \ | |
2014 | &rs6000_reg_names[50][0], /* fr18 */ \ | |
2015 | &rs6000_reg_names[51][0], /* fr19 */ \ | |
2016 | &rs6000_reg_names[52][0], /* fr20 */ \ | |
2017 | &rs6000_reg_names[53][0], /* fr21 */ \ | |
2018 | &rs6000_reg_names[54][0], /* fr22 */ \ | |
2019 | &rs6000_reg_names[55][0], /* fr23 */ \ | |
2020 | &rs6000_reg_names[56][0], /* fr24 */ \ | |
2021 | &rs6000_reg_names[57][0], /* fr25 */ \ | |
2022 | &rs6000_reg_names[58][0], /* fr26 */ \ | |
2023 | &rs6000_reg_names[59][0], /* fr27 */ \ | |
2024 | &rs6000_reg_names[60][0], /* fr28 */ \ | |
2025 | &rs6000_reg_names[61][0], /* fr29 */ \ | |
2026 | &rs6000_reg_names[62][0], /* fr30 */ \ | |
2027 | &rs6000_reg_names[63][0], /* fr31 */ \ | |
2028 | \ | |
33463137 SB |
2029 | &rs6000_reg_names[64][0], /* vr0 */ \ |
2030 | &rs6000_reg_names[65][0], /* vr1 */ \ | |
2031 | &rs6000_reg_names[66][0], /* vr2 */ \ | |
2032 | &rs6000_reg_names[67][0], /* vr3 */ \ | |
2033 | &rs6000_reg_names[68][0], /* vr4 */ \ | |
2034 | &rs6000_reg_names[69][0], /* vr5 */ \ | |
2035 | &rs6000_reg_names[70][0], /* vr6 */ \ | |
2036 | &rs6000_reg_names[71][0], /* vr7 */ \ | |
2037 | &rs6000_reg_names[72][0], /* vr8 */ \ | |
2038 | &rs6000_reg_names[73][0], /* vr9 */ \ | |
2039 | &rs6000_reg_names[74][0], /* vr10 */ \ | |
2040 | &rs6000_reg_names[75][0], /* vr11 */ \ | |
2041 | &rs6000_reg_names[76][0], /* vr12 */ \ | |
2042 | &rs6000_reg_names[77][0], /* vr13 */ \ | |
2043 | &rs6000_reg_names[78][0], /* vr14 */ \ | |
2044 | &rs6000_reg_names[79][0], /* vr15 */ \ | |
2045 | &rs6000_reg_names[80][0], /* vr16 */ \ | |
2046 | &rs6000_reg_names[81][0], /* vr17 */ \ | |
2047 | &rs6000_reg_names[82][0], /* vr18 */ \ | |
2048 | &rs6000_reg_names[83][0], /* vr19 */ \ | |
2049 | &rs6000_reg_names[84][0], /* vr20 */ \ | |
2050 | &rs6000_reg_names[85][0], /* vr21 */ \ | |
2051 | &rs6000_reg_names[86][0], /* vr22 */ \ | |
2052 | &rs6000_reg_names[87][0], /* vr23 */ \ | |
2053 | &rs6000_reg_names[88][0], /* vr24 */ \ | |
2054 | &rs6000_reg_names[89][0], /* vr25 */ \ | |
2055 | &rs6000_reg_names[90][0], /* vr26 */ \ | |
2056 | &rs6000_reg_names[91][0], /* vr27 */ \ | |
2057 | &rs6000_reg_names[92][0], /* vr28 */ \ | |
2058 | &rs6000_reg_names[93][0], /* vr29 */ \ | |
2059 | &rs6000_reg_names[94][0], /* vr30 */ \ | |
2060 | &rs6000_reg_names[95][0], /* vr31 */ \ | |
2061 | \ | |
2062 | &rs6000_reg_names[96][0], /* lr */ \ | |
2063 | &rs6000_reg_names[97][0], /* ctr */ \ | |
2064 | &rs6000_reg_names[98][0], /* ca */ \ | |
2065 | &rs6000_reg_names[99][0], /* ap */ \ | |
c81bebd7 | 2066 | \ |
33463137 SB |
2067 | &rs6000_reg_names[100][0], /* cr0 */ \ |
2068 | &rs6000_reg_names[101][0], /* cr1 */ \ | |
2069 | &rs6000_reg_names[102][0], /* cr2 */ \ | |
2070 | &rs6000_reg_names[103][0], /* cr3 */ \ | |
2071 | &rs6000_reg_names[104][0], /* cr4 */ \ | |
2072 | &rs6000_reg_names[105][0], /* cr5 */ \ | |
2073 | &rs6000_reg_names[106][0], /* cr6 */ \ | |
2074 | &rs6000_reg_names[107][0], /* cr7 */ \ | |
802a0058 | 2075 | \ |
33463137 SB |
2076 | &rs6000_reg_names[108][0], /* vrsave */ \ |
2077 | &rs6000_reg_names[109][0], /* vscr */ \ | |
0ac081f6 | 2078 | \ |
33463137 | 2079 | &rs6000_reg_names[110][0] /* sfp */ \ |
c81bebd7 MM |
2080 | } |
2081 | ||
f045b2c9 RS |
2082 | /* Table of additional register names to use in user input. */ |
2083 | ||
2084 | #define ADDITIONAL_REGISTER_NAMES \ | |
c4d38ccb MM |
2085 | {{"r0", 0}, {"r1", 1}, {"r2", 2}, {"r3", 3}, \ |
2086 | {"r4", 4}, {"r5", 5}, {"r6", 6}, {"r7", 7}, \ | |
2087 | {"r8", 8}, {"r9", 9}, {"r10", 10}, {"r11", 11}, \ | |
2088 | {"r12", 12}, {"r13", 13}, {"r14", 14}, {"r15", 15}, \ | |
2089 | {"r16", 16}, {"r17", 17}, {"r18", 18}, {"r19", 19}, \ | |
2090 | {"r20", 20}, {"r21", 21}, {"r22", 22}, {"r23", 23}, \ | |
2091 | {"r24", 24}, {"r25", 25}, {"r26", 26}, {"r27", 27}, \ | |
2092 | {"r28", 28}, {"r29", 29}, {"r30", 30}, {"r31", 31}, \ | |
2093 | {"fr0", 32}, {"fr1", 33}, {"fr2", 34}, {"fr3", 35}, \ | |
2094 | {"fr4", 36}, {"fr5", 37}, {"fr6", 38}, {"fr7", 39}, \ | |
2095 | {"fr8", 40}, {"fr9", 41}, {"fr10", 42}, {"fr11", 43}, \ | |
2096 | {"fr12", 44}, {"fr13", 45}, {"fr14", 46}, {"fr15", 47}, \ | |
2097 | {"fr16", 48}, {"fr17", 49}, {"fr18", 50}, {"fr19", 51}, \ | |
2098 | {"fr20", 52}, {"fr21", 53}, {"fr22", 54}, {"fr23", 55}, \ | |
2099 | {"fr24", 56}, {"fr25", 57}, {"fr26", 58}, {"fr27", 59}, \ | |
2100 | {"fr28", 60}, {"fr29", 61}, {"fr30", 62}, {"fr31", 63}, \ | |
33463137 SB |
2101 | {"v0", 64}, {"v1", 65}, {"v2", 66}, {"v3", 67}, \ |
2102 | {"v4", 68}, {"v5", 69}, {"v6", 70}, {"v7", 71}, \ | |
2103 | {"v8", 72}, {"v9", 73}, {"v10", 74}, {"v11", 75}, \ | |
2104 | {"v12", 76}, {"v13", 77}, {"v14", 78}, {"v15", 79}, \ | |
2105 | {"v16", 80}, {"v17", 81}, {"v18", 82}, {"v19", 83}, \ | |
2106 | {"v20", 84}, {"v21", 85}, {"v22", 86}, {"v23", 87}, \ | |
2107 | {"v24", 88}, {"v25", 89}, {"v26", 90}, {"v27", 91}, \ | |
2108 | {"v28", 92}, {"v29", 93}, {"v30", 94}, {"v31", 95}, \ | |
2109 | {"vrsave", 108}, {"vscr", 109}, \ | |
462f7901 | 2110 | /* no additional names for: lr, ctr, ap */ \ |
33463137 SB |
2111 | {"cr0", 100},{"cr1", 101},{"cr2", 102},{"cr3", 103}, \ |
2112 | {"cr4", 104},{"cr5", 105},{"cr6", 106},{"cr7", 107}, \ | |
2113 | {"cc", 100},{"sp", 1}, {"toc", 2}, \ | |
f6b5d695 | 2114 | /* CA is only part of XER, but we do not model the other parts (yet). */ \ |
33463137 | 2115 | {"xer", 98}, \ |
cacf1ca8 MM |
2116 | /* VSX registers overlaid on top of FR, Altivec registers */ \ |
2117 | {"vs0", 32}, {"vs1", 33}, {"vs2", 34}, {"vs3", 35}, \ | |
2118 | {"vs4", 36}, {"vs5", 37}, {"vs6", 38}, {"vs7", 39}, \ | |
2119 | {"vs8", 40}, {"vs9", 41}, {"vs10", 42}, {"vs11", 43}, \ | |
2120 | {"vs12", 44}, {"vs13", 45}, {"vs14", 46}, {"vs15", 47}, \ | |
2121 | {"vs16", 48}, {"vs17", 49}, {"vs18", 50}, {"vs19", 51}, \ | |
2122 | {"vs20", 52}, {"vs21", 53}, {"vs22", 54}, {"vs23", 55}, \ | |
2123 | {"vs24", 56}, {"vs25", 57}, {"vs26", 58}, {"vs27", 59}, \ | |
2124 | {"vs28", 60}, {"vs29", 61}, {"vs30", 62}, {"vs31", 63}, \ | |
33463137 SB |
2125 | {"vs32", 64}, {"vs33", 65}, {"vs34", 66}, {"vs35", 67}, \ |
2126 | {"vs36", 68}, {"vs37", 69}, {"vs38", 70}, {"vs39", 71}, \ | |
2127 | {"vs40", 72}, {"vs41", 73}, {"vs42", 74}, {"vs43", 75}, \ | |
2128 | {"vs44", 76}, {"vs45", 77}, {"vs46", 78}, {"vs47", 79}, \ | |
2129 | {"vs48", 80}, {"vs49", 81}, {"vs50", 82}, {"vs51", 83}, \ | |
2130 | {"vs52", 84}, {"vs53", 85}, {"vs54", 86}, {"vs55", 87}, \ | |
2131 | {"vs56", 88}, {"vs57", 89}, {"vs58", 90}, {"vs59", 91}, \ | |
2132 | {"vs60", 92}, {"vs61", 93}, {"vs62", 94}, {"vs63", 95}, \ | |
23742a9e | 2133 | } |
f045b2c9 | 2134 | |
f045b2c9 RS |
2135 | /* This is how to output an element of a case-vector that is relative. */ |
2136 | ||
e1565e65 | 2137 | #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ |
3daf36a4 | 2138 | do { char buf[100]; \ |
e1565e65 | 2139 | fputs ("\t.long ", FILE); \ |
3daf36a4 ILT |
2140 | ASM_GENERATE_INTERNAL_LABEL (buf, "L", VALUE); \ |
2141 | assemble_name (FILE, buf); \ | |
19d2d16f | 2142 | putc ('-', FILE); \ |
3daf36a4 ILT |
2143 | ASM_GENERATE_INTERNAL_LABEL (buf, "L", REL); \ |
2144 | assemble_name (FILE, buf); \ | |
19d2d16f | 2145 | putc ('\n', FILE); \ |
3daf36a4 | 2146 | } while (0) |
f045b2c9 | 2147 | |
3493b0c3 HG |
2148 | /* This is how to output an element of a case-vector |
2149 | that is non-relative. */ | |
2150 | #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ | |
2151 | rs6000_output_addr_vec_elt ((FILE), (VALUE)) | |
2152 | ||
f045b2c9 RS |
2153 | /* This is how to output an assembler line |
2154 | that says to advance the location counter | |
2155 | to a multiple of 2**LOG bytes. */ | |
2156 | ||
2157 | #define ASM_OUTPUT_ALIGN(FILE,LOG) \ | |
2158 | if ((LOG) != 0) \ | |
2159 | fprintf (FILE, "\t.align %d\n", (LOG)) | |
2160 | ||
58082ff6 PH |
2161 | /* How to align the given loop. */ |
2162 | #define LOOP_ALIGN(LABEL) rs6000_loop_align(LABEL) | |
2163 | ||
d28073d4 BS |
2164 | /* Alignment guaranteed by __builtin_malloc. */ |
2165 | /* FIXME: 128-bit alignment is guaranteed by glibc for TARGET_64BIT. | |
2166 | However, specifying the stronger guarantee currently leads to | |
2167 | a regression in SPEC CPU2006 437.leslie3d. The stronger | |
2168 | guarantee should be implemented here once that's fixed. */ | |
2169 | #define MALLOC_ABI_ALIGNMENT (64) | |
2170 | ||
9ebbca7d GK |
2171 | /* Pick up the return address upon entry to a procedure. Used for |
2172 | dwarf2 unwind information. This also enables the table driven | |
2173 | mechanism. */ | |
2174 | ||
1de43f85 DE |
2175 | #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNO) |
2176 | #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNO) | |
9ebbca7d | 2177 | |
83720594 RH |
2178 | /* Describe how we implement __builtin_eh_return. */ |
2179 | #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 3 : INVALID_REGNUM) | |
2180 | #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 10) | |
2181 | ||
f045b2c9 RS |
2182 | /* Print operand X (an rtx) in assembler syntax to file FILE. |
2183 | CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. | |
2184 | For `%' followed by punctuation, CODE is the punctuation and X is null. */ | |
2185 | ||
2186 | #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE) | |
2187 | ||
2188 | /* Define which CODE values are valid. */ | |
2189 | ||
3cf437d4 | 2190 | #define PRINT_OPERAND_PUNCT_VALID_P(CODE) ((CODE) == '&') |
f045b2c9 RS |
2191 | |
2192 | /* Print a memory address as an operand to reference that memory location. */ | |
2193 | ||
2194 | #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR) | |
2195 | ||
c82846bc DE |
2196 | /* For switching between functions with different target attributes. */ |
2197 | #define SWITCHABLE_TARGET 1 | |
2198 | ||
b6c9286a MM |
2199 | /* uncomment for disabling the corresponding default options */ |
2200 | /* #define MACHINE_no_sched_interblock */ | |
2201 | /* #define MACHINE_no_sched_speculative */ | |
2202 | /* #define MACHINE_no_sched_speculative_load */ | |
2203 | ||
766a866c | 2204 | /* General flags. */ |
a7df97e6 | 2205 | extern int frame_pointer_needed; |
0ac081f6 | 2206 | |
58646b77 PB |
2207 | enum rs6000_builtin_type_index |
2208 | { | |
2209 | RS6000_BTI_NOT_OPAQUE, | |
58646b77 | 2210 | RS6000_BTI_opaque_V4SI, |
d4f18ec6 | 2211 | RS6000_BTI_V16QI, /* __vector signed char */ |
a16a872d | 2212 | RS6000_BTI_V1TI, |
a72c65c7 MM |
2213 | RS6000_BTI_V2DI, |
2214 | RS6000_BTI_V2DF, | |
58646b77 PB |
2215 | RS6000_BTI_V4HI, |
2216 | RS6000_BTI_V4SI, | |
2217 | RS6000_BTI_V4SF, | |
2218 | RS6000_BTI_V8HI, | |
d4f18ec6 | 2219 | RS6000_BTI_unsigned_V16QI, /* __vector unsigned char */ |
a16a872d | 2220 | RS6000_BTI_unsigned_V1TI, |
58646b77 PB |
2221 | RS6000_BTI_unsigned_V8HI, |
2222 | RS6000_BTI_unsigned_V4SI, | |
a72c65c7 | 2223 | RS6000_BTI_unsigned_V2DI, |
58646b77 PB |
2224 | RS6000_BTI_bool_char, /* __bool char */ |
2225 | RS6000_BTI_bool_short, /* __bool short */ | |
2226 | RS6000_BTI_bool_int, /* __bool int */ | |
d4f18ec6 KN |
2227 | RS6000_BTI_bool_long_long, /* __bool long long */ |
2228 | RS6000_BTI_pixel, /* __pixel (16 bits arranged as 4 | |
2229 | channels of 1, 5, 5, and 5 bits | |
2230 | respectively as packed with the | |
2231 | vpkpx insn. __pixel is only | |
2232 | meaningful as a vector type. | |
2233 | There is no corresponding scalar | |
2234 | __pixel data type.) */ | |
58646b77 PB |
2235 | RS6000_BTI_bool_V16QI, /* __vector __bool char */ |
2236 | RS6000_BTI_bool_V8HI, /* __vector __bool short */ | |
2237 | RS6000_BTI_bool_V4SI, /* __vector __bool int */ | |
a72c65c7 | 2238 | RS6000_BTI_bool_V2DI, /* __vector __bool long */ |
f03122f2 | 2239 | RS6000_BTI_bool_V1TI, /* __vector __bool 128-bit */ |
58646b77 PB |
2240 | RS6000_BTI_pixel_V8HI, /* __vector __pixel */ |
2241 | RS6000_BTI_long, /* long_integer_type_node */ | |
2242 | RS6000_BTI_unsigned_long, /* long_unsigned_type_node */ | |
c9485473 MM |
2243 | RS6000_BTI_long_long, /* long_long_integer_type_node */ |
2244 | RS6000_BTI_unsigned_long_long, /* long_long_unsigned_type_node */ | |
d4f18ec6 | 2245 | RS6000_BTI_INTQI, /* (signed) intQI_type_node */ |
58646b77 PB |
2246 | RS6000_BTI_UINTQI, /* unsigned_intQI_type_node */ |
2247 | RS6000_BTI_INTHI, /* intHI_type_node */ | |
2248 | RS6000_BTI_UINTHI, /* unsigned_intHI_type_node */ | |
d4f18ec6 | 2249 | RS6000_BTI_INTSI, /* intSI_type_node (signed) */ |
58646b77 | 2250 | RS6000_BTI_UINTSI, /* unsigned_intSI_type_node */ |
a72c65c7 MM |
2251 | RS6000_BTI_INTDI, /* intDI_type_node */ |
2252 | RS6000_BTI_UINTDI, /* unsigned_intDI_type_node */ | |
a16a872d MM |
2253 | RS6000_BTI_INTTI, /* intTI_type_node */ |
2254 | RS6000_BTI_UINTTI, /* unsigned_intTI_type_node */ | |
58646b77 | 2255 | RS6000_BTI_float, /* float_type_node */ |
a72c65c7 | 2256 | RS6000_BTI_double, /* double_type_node */ |
06b39289 MM |
2257 | RS6000_BTI_long_double, /* long_double_type_node */ |
2258 | RS6000_BTI_dfloat64, /* dfloat64_type_node */ | |
2259 | RS6000_BTI_dfloat128, /* dfloat128_type_node */ | |
58646b77 | 2260 | RS6000_BTI_void, /* void_type_node */ |
6712d6fd MM |
2261 | RS6000_BTI_ieee128_float, /* ieee 128-bit floating point */ |
2262 | RS6000_BTI_ibm128_float, /* IBM 128-bit floating point */ | |
53605f35 | 2263 | RS6000_BTI_const_str, /* pointer to const char * */ |
f002c046 PB |
2264 | RS6000_BTI_vector_pair, /* unsigned 256-bit types (vector pair). */ |
2265 | RS6000_BTI_vector_quad, /* unsigned 512-bit types (vector quad). */ | |
6cc92e94 | 2266 | RS6000_BTI_const_ptr_void, /* const pointer to void */ |
19b7bf62 BS |
2267 | RS6000_BTI_ptr_V16QI, |
2268 | RS6000_BTI_ptr_V1TI, | |
2269 | RS6000_BTI_ptr_V2DI, | |
2270 | RS6000_BTI_ptr_V2DF, | |
2271 | RS6000_BTI_ptr_V4SI, | |
2272 | RS6000_BTI_ptr_V4SF, | |
2273 | RS6000_BTI_ptr_V8HI, | |
2274 | RS6000_BTI_ptr_unsigned_V16QI, | |
2275 | RS6000_BTI_ptr_unsigned_V1TI, | |
2276 | RS6000_BTI_ptr_unsigned_V8HI, | |
2277 | RS6000_BTI_ptr_unsigned_V4SI, | |
2278 | RS6000_BTI_ptr_unsigned_V2DI, | |
2279 | RS6000_BTI_ptr_bool_V16QI, | |
2280 | RS6000_BTI_ptr_bool_V8HI, | |
2281 | RS6000_BTI_ptr_bool_V4SI, | |
2282 | RS6000_BTI_ptr_bool_V2DI, | |
2283 | RS6000_BTI_ptr_bool_V1TI, | |
2284 | RS6000_BTI_ptr_pixel_V8HI, | |
2285 | RS6000_BTI_ptr_INTQI, | |
2286 | RS6000_BTI_ptr_UINTQI, | |
2287 | RS6000_BTI_ptr_INTHI, | |
2288 | RS6000_BTI_ptr_UINTHI, | |
2289 | RS6000_BTI_ptr_INTSI, | |
2290 | RS6000_BTI_ptr_UINTSI, | |
2291 | RS6000_BTI_ptr_INTDI, | |
2292 | RS6000_BTI_ptr_UINTDI, | |
2293 | RS6000_BTI_ptr_INTTI, | |
2294 | RS6000_BTI_ptr_UINTTI, | |
2295 | RS6000_BTI_ptr_long_integer, | |
2296 | RS6000_BTI_ptr_long_unsigned, | |
2297 | RS6000_BTI_ptr_float, | |
2298 | RS6000_BTI_ptr_double, | |
2299 | RS6000_BTI_ptr_long_double, | |
2300 | RS6000_BTI_ptr_dfloat64, | |
2301 | RS6000_BTI_ptr_dfloat128, | |
19b7bf62 BS |
2302 | RS6000_BTI_ptr_vector_pair, |
2303 | RS6000_BTI_ptr_vector_quad, | |
2304 | RS6000_BTI_ptr_long_long, | |
2305 | RS6000_BTI_ptr_long_long_unsigned, | |
58646b77 | 2306 | RS6000_BTI_MAX |
0ac081f6 | 2307 | }; |
58646b77 PB |
2308 | |
2309 | ||
58646b77 PB |
2310 | #define opaque_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V4SI]) |
2311 | #define V16QI_type_node (rs6000_builtin_types[RS6000_BTI_V16QI]) | |
a16a872d | 2312 | #define V1TI_type_node (rs6000_builtin_types[RS6000_BTI_V1TI]) |
a72c65c7 MM |
2313 | #define V2DI_type_node (rs6000_builtin_types[RS6000_BTI_V2DI]) |
2314 | #define V2DF_type_node (rs6000_builtin_types[RS6000_BTI_V2DF]) | |
58646b77 PB |
2315 | #define V4HI_type_node (rs6000_builtin_types[RS6000_BTI_V4HI]) |
2316 | #define V4SI_type_node (rs6000_builtin_types[RS6000_BTI_V4SI]) | |
2317 | #define V4SF_type_node (rs6000_builtin_types[RS6000_BTI_V4SF]) | |
2318 | #define V8HI_type_node (rs6000_builtin_types[RS6000_BTI_V8HI]) | |
2319 | #define unsigned_V16QI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V16QI]) | |
a16a872d | 2320 | #define unsigned_V1TI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V1TI]) |
58646b77 PB |
2321 | #define unsigned_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V8HI]) |
2322 | #define unsigned_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V4SI]) | |
a72c65c7 | 2323 | #define unsigned_V2DI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V2DI]) |
58646b77 PB |
2324 | #define bool_char_type_node (rs6000_builtin_types[RS6000_BTI_bool_char]) |
2325 | #define bool_short_type_node (rs6000_builtin_types[RS6000_BTI_bool_short]) | |
2326 | #define bool_int_type_node (rs6000_builtin_types[RS6000_BTI_bool_int]) | |
d4f18ec6 | 2327 | #define bool_long_long_type_node (rs6000_builtin_types[RS6000_BTI_bool_long_long]) |
58646b77 PB |
2328 | #define pixel_type_node (rs6000_builtin_types[RS6000_BTI_pixel]) |
2329 | #define bool_V16QI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V16QI]) | |
2330 | #define bool_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V8HI]) | |
2331 | #define bool_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V4SI]) | |
a72c65c7 | 2332 | #define bool_V2DI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V2DI]) |
f03122f2 | 2333 | #define bool_V1TI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V1TI]) |
58646b77 PB |
2334 | #define pixel_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_pixel_V8HI]) |
2335 | ||
c9485473 MM |
2336 | #define long_long_integer_type_internal_node (rs6000_builtin_types[RS6000_BTI_long_long]) |
2337 | #define long_long_unsigned_type_internal_node (rs6000_builtin_types[RS6000_BTI_unsigned_long_long]) | |
58646b77 PB |
2338 | #define long_integer_type_internal_node (rs6000_builtin_types[RS6000_BTI_long]) |
2339 | #define long_unsigned_type_internal_node (rs6000_builtin_types[RS6000_BTI_unsigned_long]) | |
2340 | #define intQI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTQI]) | |
2341 | #define uintQI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTQI]) | |
2342 | #define intHI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTHI]) | |
2343 | #define uintHI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTHI]) | |
2344 | #define intSI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTSI]) | |
2345 | #define uintSI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTSI]) | |
a72c65c7 MM |
2346 | #define intDI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTDI]) |
2347 | #define uintDI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTDI]) | |
a16a872d MM |
2348 | #define intTI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTTI]) |
2349 | #define uintTI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTTI]) | |
58646b77 | 2350 | #define float_type_internal_node (rs6000_builtin_types[RS6000_BTI_float]) |
a72c65c7 | 2351 | #define double_type_internal_node (rs6000_builtin_types[RS6000_BTI_double]) |
06b39289 MM |
2352 | #define long_double_type_internal_node (rs6000_builtin_types[RS6000_BTI_long_double]) |
2353 | #define dfloat64_type_internal_node (rs6000_builtin_types[RS6000_BTI_dfloat64]) | |
2354 | #define dfloat128_type_internal_node (rs6000_builtin_types[RS6000_BTI_dfloat128]) | |
58646b77 | 2355 | #define void_type_internal_node (rs6000_builtin_types[RS6000_BTI_void]) |
6712d6fd MM |
2356 | #define ieee128_float_type_node (rs6000_builtin_types[RS6000_BTI_ieee128_float]) |
2357 | #define ibm128_float_type_node (rs6000_builtin_types[RS6000_BTI_ibm128_float]) | |
53605f35 | 2358 | #define const_str_type_node (rs6000_builtin_types[RS6000_BTI_const_str]) |
f002c046 PB |
2359 | #define vector_pair_type_node (rs6000_builtin_types[RS6000_BTI_vector_pair]) |
2360 | #define vector_quad_type_node (rs6000_builtin_types[RS6000_BTI_vector_quad]) | |
6cc92e94 | 2361 | #define pcvoid_type_node (rs6000_builtin_types[RS6000_BTI_const_ptr_void]) |
19b7bf62 BS |
2362 | #define ptr_V16QI_type_node (rs6000_builtin_types[RS6000_BTI_ptr_V16QI]) |
2363 | #define ptr_V1TI_type_node (rs6000_builtin_types[RS6000_BTI_ptr_V1TI]) | |
2364 | #define ptr_V2DI_type_node (rs6000_builtin_types[RS6000_BTI_ptr_V2DI]) | |
2365 | #define ptr_V2DF_type_node (rs6000_builtin_types[RS6000_BTI_ptr_V2DF]) | |
2366 | #define ptr_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_ptr_V4SI]) | |
2367 | #define ptr_V4SF_type_node (rs6000_builtin_types[RS6000_BTI_ptr_V4SF]) | |
2368 | #define ptr_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_ptr_V8HI]) | |
2369 | #define ptr_unsigned_V16QI_type_node (rs6000_builtin_types[RS6000_BTI_ptr_unsigned_V16QI]) | |
2370 | #define ptr_unsigned_V1TI_type_node (rs6000_builtin_types[RS6000_BTI_ptr_unsigned_V1TI]) | |
2371 | #define ptr_unsigned_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_ptr_unsigned_V8HI]) | |
2372 | #define ptr_unsigned_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_ptr_unsigned_V4SI]) | |
2373 | #define ptr_unsigned_V2DI_type_node (rs6000_builtin_types[RS6000_BTI_ptr_unsigned_V2DI]) | |
2374 | #define ptr_bool_V16QI_type_node (rs6000_builtin_types[RS6000_BTI_ptr_bool_V16QI]) | |
2375 | #define ptr_bool_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_ptr_bool_V8HI]) | |
2376 | #define ptr_bool_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_ptr_bool_V4SI]) | |
2377 | #define ptr_bool_V2DI_type_node (rs6000_builtin_types[RS6000_BTI_ptr_bool_V2DI]) | |
2378 | #define ptr_bool_V1TI_type_node (rs6000_builtin_types[RS6000_BTI_ptr_bool_V1TI]) | |
2379 | #define ptr_pixel_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_ptr_pixel_V8HI]) | |
2380 | #define ptr_intQI_type_node (rs6000_builtin_types[RS6000_BTI_ptr_INTQI]) | |
2381 | #define ptr_uintQI_type_node (rs6000_builtin_types[RS6000_BTI_ptr_UINTQI]) | |
2382 | #define ptr_intHI_type_node (rs6000_builtin_types[RS6000_BTI_ptr_INTHI]) | |
2383 | #define ptr_uintHI_type_node (rs6000_builtin_types[RS6000_BTI_ptr_UINTHI]) | |
2384 | #define ptr_intSI_type_node (rs6000_builtin_types[RS6000_BTI_ptr_INTSI]) | |
2385 | #define ptr_uintSI_type_node (rs6000_builtin_types[RS6000_BTI_ptr_UINTSI]) | |
2386 | #define ptr_intDI_type_node (rs6000_builtin_types[RS6000_BTI_ptr_INTDI]) | |
2387 | #define ptr_uintDI_type_node (rs6000_builtin_types[RS6000_BTI_ptr_UINTDI]) | |
2388 | #define ptr_intTI_type_node (rs6000_builtin_types[RS6000_BTI_ptr_INTTI]) | |
2389 | #define ptr_uintTI_type_node (rs6000_builtin_types[RS6000_BTI_ptr_UINTTI]) | |
2390 | #define ptr_long_integer_type_node (rs6000_builtin_types[RS6000_BTI_ptr_long_integer]) | |
2391 | #define ptr_long_unsigned_type_node (rs6000_builtin_types[RS6000_BTI_ptr_long_unsigned]) | |
2392 | #define ptr_float_type_node (rs6000_builtin_types[RS6000_BTI_ptr_float]) | |
2393 | #define ptr_double_type_node (rs6000_builtin_types[RS6000_BTI_ptr_double]) | |
2394 | #define ptr_long_double_type_node (rs6000_builtin_types[RS6000_BTI_ptr_long_double]) | |
2395 | #define ptr_dfloat64_type_node (rs6000_builtin_types[RS6000_BTI_ptr_dfloat64]) | |
2396 | #define ptr_dfloat128_type_node (rs6000_builtin_types[RS6000_BTI_ptr_dfloat128]) | |
19b7bf62 BS |
2397 | #define ptr_vector_pair_type_node (rs6000_builtin_types[RS6000_BTI_ptr_vector_pair]) |
2398 | #define ptr_vector_quad_type_node (rs6000_builtin_types[RS6000_BTI_ptr_vector_quad]) | |
2399 | #define ptr_long_long_integer_type_node (rs6000_builtin_types[RS6000_BTI_ptr_long_long]) | |
2400 | #define ptr_long_long_unsigned_type_node (rs6000_builtin_types[RS6000_BTI_ptr_long_long_unsigned]) | |
58646b77 PB |
2401 | |
2402 | extern GTY(()) tree rs6000_builtin_types[RS6000_BTI_MAX]; | |
58646b77 | 2403 | |
2c04f847 | 2404 | #ifndef USED_FOR_TARGET |
f457ae22 | 2405 | extern GTY(()) tree altivec_builtin_mask_for_load; |
4a18f168 | 2406 | extern GTY(()) section *toc_section; |
f457ae22 | 2407 | |
2c04f847 BS |
2408 | /* A C structure for machine-specific, per-function data. |
2409 | This is added to the cfun structure. */ | |
2410 | typedef struct GTY(()) machine_function | |
2411 | { | |
2412 | /* Flags if __builtin_return_address (n) with n >= 1 was used. */ | |
2413 | int ra_needs_full_frame; | |
2414 | /* Flags if __builtin_return_address (0) was used. */ | |
2415 | int ra_need_lr; | |
2416 | /* Cache lr_save_p after expansion of builtin_eh_return. */ | |
2417 | int lr_save_state; | |
2418 | /* Whether we need to save the TOC to the reserved stack location in the | |
2419 | function prologue. */ | |
2420 | bool save_toc_in_prologue; | |
2421 | /* Offset from virtual_stack_vars_rtx to the start of the ABI_V4 | |
2422 | varargs save area. */ | |
2423 | HOST_WIDE_INT varargs_save_offset; | |
2424 | /* Alternative internal arg pointer for -fsplit-stack. */ | |
2425 | rtx split_stack_arg_pointer; | |
2426 | bool split_stack_argp_used; | |
2427 | /* Flag if r2 setup is needed with ELFv2 ABI. */ | |
2428 | bool r2_setup_needed; | |
2429 | /* The number of components we use for separate shrink-wrapping. */ | |
2430 | int n_components; | |
2431 | /* The components already handled by separate shrink-wrapping, which should | |
2432 | not be considered by the prologue and epilogue. */ | |
2433 | bool gpr_is_wrapped_separately[32]; | |
2434 | bool fpr_is_wrapped_separately[32]; | |
2435 | bool lr_is_wrapped_separately; | |
2436 | bool toc_is_wrapped_separately; | |
f8f8909a | 2437 | bool mma_return_type_error; |
c23b5006 KL |
2438 | /* Indicate global entry is emitted, only useful when the function requires |
2439 | global entry. It helps to control the patchable area before and after | |
2440 | local entry. */ | |
2441 | bool global_entry_emitted; | |
2c04f847 BS |
2442 | } machine_function; |
2443 | #endif | |
2444 | ||
2445 | ||
807e902e | 2446 | #define TARGET_SUPPORTS_WIDE_INT 1 |
08213983 MM |
2447 | |
2448 | #if (GCC_VERSION >= 3000) | |
2449 | #pragma GCC poison TARGET_FLOAT128 OPTION_MASK_FLOAT128 MASK_FLOAT128 | |
2450 | #endif | |
ed383d79 | 2451 | |
03e487e5 MM |
2452 | /* Whether a given VALUE is a valid 16 or 34-bit signed integer. */ |
2453 | #define SIGNED_INTEGER_NBIT_P(VALUE, N) \ | |
4ded6adc | 2454 | IN_RANGE ((VALUE), \ |
03e487e5 MM |
2455 | -(HOST_WIDE_INT_1 << ((N)-1)), \ |
2456 | (HOST_WIDE_INT_1 << ((N)-1)) - 1) | |
4ded6adc | 2457 | |
03e487e5 MM |
2458 | #define SIGNED_INTEGER_16BIT_P(VALUE) SIGNED_INTEGER_NBIT_P (VALUE, 16) |
2459 | #define SIGNED_INTEGER_34BIT_P(VALUE) SIGNED_INTEGER_NBIT_P (VALUE, 34) | |
4ded6adc | 2460 | |
03e487e5 | 2461 | /* Like SIGNED_INTEGER_16BIT_P and SIGNED_INTEGER_34BIT_P, but with an extra |
4ded6adc MM |
2462 | argument that gives a length to validate a range of addresses, to allow for |
2463 | splitting insns into several insns, each of which has an offsettable | |
2464 | address. */ | |
2465 | #define SIGNED_16BIT_OFFSET_EXTRA_P(VALUE, EXTRA) \ | |
2466 | IN_RANGE ((VALUE), \ | |
ed383d79 BS |
2467 | -(HOST_WIDE_INT_1 << 15), \ |
2468 | (HOST_WIDE_INT_1 << 15) - 1 - (EXTRA)) | |
2469 | ||
4ded6adc MM |
2470 | #define SIGNED_34BIT_OFFSET_EXTRA_P(VALUE, EXTRA) \ |
2471 | IN_RANGE ((VALUE), \ | |
ed383d79 BS |
2472 | -(HOST_WIDE_INT_1 << 33), \ |
2473 | (HOST_WIDE_INT_1 << 33) - 1 - (EXTRA)) | |
26ca7d1b MM |
2474 | |
2475 | /* Define this if some processing needs to be done before outputting the | |
2476 | assembler code. On the PowerPC, we remember if the current insn is a normal | |
2477 | prefixed insn where we need to emit a 'p' before the insn. */ | |
2478 | #define FINAL_PRESCAN_INSN(INSN, OPERANDS, NOPERANDS) \ | |
2479 | do \ | |
2480 | { \ | |
7a775242 | 2481 | if (TARGET_PREFIXED) \ |
26ca7d1b MM |
2482 | rs6000_final_prescan_insn (INSN, OPERANDS, NOPERANDS); \ |
2483 | } \ | |
2484 | while (0) | |
2485 | ||
2486 | /* Do anything special before emitting an opcode. We use it to emit a 'p' for | |
2487 | prefixed insns that is set in FINAL_PRESCAN_INSN. */ | |
2488 | #define ASM_OUTPUT_OPCODE(STREAM, OPCODE) \ | |
2489 | do \ | |
2490 | { \ | |
7a775242 | 2491 | if (TARGET_PREFIXED) \ |
26ca7d1b MM |
2492 | rs6000_asm_output_opcode (STREAM); \ |
2493 | } \ | |
2494 | while (0) | |
58ab3821 PH |
2495 | |
2496 | /* Disable generation of scalar modulo instructions due to performance issues | |
2497 | with certain input values. This can be removed in the future when the | |
2498 | issues have been resolved. */ | |
2499 | #define RS6000_DISABLE_SCALAR_MODULO 1 | |
2500 |