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[gcc.git] / gcc / config / rs6000 / rs6000.h
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f045b2c9 1/* Definitions of target machine for GNU compiler, for IBM RS/6000.
9ebbca7d 2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
7042fe5e
MM		 3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009,
4 2010
602ea4d3 5 Free Software Foundation, Inc.
6a7ec0a7 6 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
f045b2c9 7
5de601cf 8 This file is part of GCC.
f045b2c9 9
5de601cf
NC		 10 GCC is free software; you can redistribute it and/or modify it
11 under the terms of the GNU General Public License as published
2f83c7d6 12 by the Free Software Foundation; either version 3, or (at your
5de601cf 13 option) any later version.
f045b2c9 14
5de601cf
NC		 15 GCC is distributed in the hope that it will be useful, but WITHOUT
16 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
17 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
18 License for more details.
f045b2c9 19
748086b7
JJ		 20 Under Section 7 of GPL version 3, you are granted additional
21 permissions described in the GCC Runtime Library Exception, version
22 3.1, as published by the Free Software Foundation.
23
24 You should have received a copy of the GNU General Public License and
25 a copy of the GCC Runtime Library Exception along with this program;
26 see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
2f83c7d6 27 <http://www.gnu.org/licenses/>. */
f045b2c9
RS		 28
29/* Note that some other tm.h files include this one and then override
9ebbca7d 30 many of the definitions. */
f045b2c9 31
9ebbca7d
GK		 32/* Definitions for the object file format. These are set at
33 compile-time. */
f045b2c9 34
9ebbca7d
GK		 35#define OBJECT_XCOFF 1
36#define OBJECT_ELF 2
37#define OBJECT_PEF 3
ee890fe2 38#define OBJECT_MACHO 4
f045b2c9 39
9ebbca7d 40#define TARGET_ELF (TARGET_OBJECT_FORMAT == OBJECT_ELF)
2bfcf297 41#define TARGET_XCOFF (TARGET_OBJECT_FORMAT == OBJECT_XCOFF)
9ebbca7d 42#define TARGET_MACOS (TARGET_OBJECT_FORMAT == OBJECT_PEF)
ee890fe2 43#define TARGET_MACHO (TARGET_OBJECT_FORMAT == OBJECT_MACHO)
f045b2c9 44
2bfcf297
DB		 45#ifndef TARGET_AIX
46#define TARGET_AIX 0
47#endif
48
85b776df
AM		 49/* Control whether function entry points use a "dot" symbol when
50 ABI_AIX. */
51#define DOT_SYMBOLS 1
52
8e3f41e7
MM		 53/* Default string to use for cpu if not specified. */
54#ifndef TARGET_CPU_DEFAULT
55#define TARGET_CPU_DEFAULT ((char *)0)
56#endif
57
f565b0a1 58/* If configured for PPC405, support PPC405CR Erratum77. */
b0bfee6e 59#ifdef CONFIG_PPC405CR
f565b0a1
DE		 60#define PPC405_ERRATUM77 (rs6000_cpu == PROCESSOR_PPC405)
61#else
62#define PPC405_ERRATUM77 0
63#endif
64
96038623
DE		 65#ifndef TARGET_PAIRED_FLOAT
66#define TARGET_PAIRED_FLOAT 0
67#endif
68
cd679487
BE		 69#ifdef HAVE_AS_POPCNTB
70#define ASM_CPU_POWER5_SPEC "-mpower5"
71#else
72#define ASM_CPU_POWER5_SPEC "-mpower4"
73#endif
74
75#ifdef HAVE_AS_DFP
76#define ASM_CPU_POWER6_SPEC "-mpower6 -maltivec"
77#else
78#define ASM_CPU_POWER6_SPEC "-mpower4 -maltivec"
79#endif
80
cacf1ca8 81#ifdef HAVE_AS_POPCNTD
d40c9e33
PB		 82#define ASM_CPU_POWER7_SPEC "-mpower7"
83#else
84#define ASM_CPU_POWER7_SPEC "-mpower4 -maltivec"
85#endif
86
47f67e51
PB		 87#ifdef HAVE_AS_DCI
88#define ASM_CPU_476_SPEC "-m476"
89#else
90#define ASM_CPU_476_SPEC "-mpower4"
91#endif
92
cacf1ca8
MM		 93/* Common ASM definitions used by ASM_SPEC among the various targets for
94 handling -mcpu=xxx switches. There is a parallel list in driver-rs6000.c to
95 provide the default assembler options if the user uses -mcpu=native, so if
96 you make changes here, make them also there. */
f984d8df
DB		 97#define ASM_CPU_SPEC \
98"%{!mcpu*: \
99 %{mpower: %{!mpower2: -mpwr}} \
100 %{mpower2: -mpwrx} \
93ae5495
AM		 101 %{mpowerpc64*: -mppc64} \
102 %{!mpowerpc64*: %{mpowerpc*: -mppc}} \
f984d8df 103 %{mno-power: %{!mpowerpc*: -mcom}} \
93ae5495 104 %{!mno-power: %{!mpower*: %(asm_default)}}} \
cacf1ca8 105%{mcpu=native: %(asm_cpu_native)} \
f984d8df 106%{mcpu=common: -mcom} \
d296e02e 107%{mcpu=cell: -mcell} \
f984d8df
DB		 108%{mcpu=power: -mpwr} \
109%{mcpu=power2: -mpwrx} \
93ae5495 110%{mcpu=power3: -mppc64} \
957e9e48 111%{mcpu=power4: -mpower4} \
cd679487
BE		 112%{mcpu=power5: %(asm_cpu_power5)} \
113%{mcpu=power5+: %(asm_cpu_power5)} \
114%{mcpu=power6: %(asm_cpu_power6) -maltivec} \
115%{mcpu=power6x: %(asm_cpu_power6) -maltivec} \
d40c9e33 116%{mcpu=power7: %(asm_cpu_power7)} \
ebde32fd 117%{mcpu=a2: -ma2} \
f984d8df
DB		 118%{mcpu=powerpc: -mppc} \
119%{mcpu=rios: -mpwr} \
120%{mcpu=rios1: -mpwr} \
121%{mcpu=rios2: -mpwrx} \
122%{mcpu=rsc: -mpwr} \
123%{mcpu=rsc1: -mpwr} \
93ae5495 124%{mcpu=rs64a: -mppc64} \
f984d8df 125%{mcpu=401: -mppc} \
61a8515c
JS		 126%{mcpu=403: -m403} \
127%{mcpu=405: -m405} \
2c9d95ef
DE		 128%{mcpu=405fp: -m405} \
129%{mcpu=440: -m440} \
130%{mcpu=440fp: -m440} \
4adf8008
PB		 131%{mcpu=464: -m440} \
132%{mcpu=464fp: -m440} \
47f67e51
PB		 133%{mcpu=476: %(asm_cpu_476)} \
134%{mcpu=476fp: %(asm_cpu_476)} \
f984d8df
DB		 135%{mcpu=505: -mppc} \
136%{mcpu=601: -m601} \
137%{mcpu=602: -mppc} \
138%{mcpu=603: -mppc} \
139%{mcpu=603e: -mppc} \
140%{mcpu=ec603e: -mppc} \
141%{mcpu=604: -mppc} \
142%{mcpu=604e: -mppc} \
93ae5495
AM		 143%{mcpu=620: -mppc64} \
144%{mcpu=630: -mppc64} \
f984d8df
DB		 145%{mcpu=740: -mppc} \
146%{mcpu=750: -mppc} \
49ffe578 147%{mcpu=G3: -mppc} \
93ae5495
AM		 148%{mcpu=7400: -mppc -maltivec} \
149%{mcpu=7450: -mppc -maltivec} \
150%{mcpu=G4: -mppc -maltivec} \
f984d8df
DB		 151%{mcpu=801: -mppc} \
152%{mcpu=821: -mppc} \
153%{mcpu=823: -mppc} \
775db490 154%{mcpu=860: -mppc} \
93ae5495
AM		 155%{mcpu=970: -mpower4 -maltivec} \
156%{mcpu=G5: -mpower4 -maltivec} \
a3170dc6 157%{mcpu=8540: -me500} \
5ca0373f 158%{mcpu=8548: -me500} \
fa41c305
EW		 159%{mcpu=e300c2: -me300} \
160%{mcpu=e300c3: -me300} \
edae5fe3 161%{mcpu=e500mc: -me500mc} \
b17f98b1 162%{mcpu=e500mc64: -me500mc64} \
93ae5495 163%{maltivec: -maltivec} \
2c9ccc21 164%{mvsx: -mvsx %{!maltivec: -maltivec} %{!mcpu*: %(asm_cpu_power7)}} \
93ae5495 165-many"
f984d8df
DB		 166
167#define CPP_DEFAULT_SPEC ""
168
169#define ASM_DEFAULT_SPEC ""
170
841faeed
MM		 171/* This macro defines names of additional specifications to put in the specs
172 that can be used in various specifications like CC1_SPEC. Its definition
173 is an initializer with a subgrouping for each command option.
174
175 Each subgrouping contains a string constant, that defines the
5de601cf 176 specification name, and a string constant that used by the GCC driver
841faeed
MM		 177 program.
178
179 Do not define this macro if it does not need to do anything. */
180
7509c759 181#define SUBTARGET_EXTRA_SPECS
7509c759 182
c81bebd7 183#define EXTRA_SPECS \
c81bebd7 184 { "cpp_default", CPP_DEFAULT_SPEC }, \
c81bebd7 185 { "asm_cpu", ASM_CPU_SPEC }, \
cacf1ca8 186 { "asm_cpu_native", ASM_CPU_NATIVE_SPEC }, \
c81bebd7 187 { "asm_default", ASM_DEFAULT_SPEC }, \
0eab6840 188 { "cc1_cpu", CC1_CPU_SPEC }, \
cd679487
BE		 189 { "asm_cpu_power5", ASM_CPU_POWER5_SPEC }, \
190 { "asm_cpu_power6", ASM_CPU_POWER6_SPEC }, \
d40c9e33 191 { "asm_cpu_power7", ASM_CPU_POWER7_SPEC }, \
47f67e51 192 { "asm_cpu_476", ASM_CPU_476_SPEC }, \
7509c759
MM		 193 SUBTARGET_EXTRA_SPECS
194
0eab6840
DE		 195/* -mcpu=native handling only makes sense with compiler running on
196 an PowerPC chip. If changing this condition, also change
197 the condition in driver-rs6000.c. */
198#if defined(__powerpc__) || defined(__POWERPC__) || defined(_AIX)
199/* In driver-rs6000.c. */
200extern const char *host_detect_local_cpu (int argc, const char **argv);
201#define EXTRA_SPEC_FUNCTIONS \
202 { "local_cpu_detect", host_detect_local_cpu },
203#define HAVE_LOCAL_CPU_DETECT
cacf1ca8
MM		 204#define ASM_CPU_NATIVE_SPEC "%:local_cpu_detect(asm)"
205
206#else
207#define ASM_CPU_NATIVE_SPEC "%(asm_default)"
0eab6840
DE		 208#endif
209
ee7caeb3
DE		 210#ifndef CC1_CPU_SPEC
211#ifdef HAVE_LOCAL_CPU_DETECT
0eab6840
DE		 212#define CC1_CPU_SPEC \
213"%{mcpu=native:%<mcpu=native %:local_cpu_detect(cpu)} \
214 %{mtune=native:%<mtune=native %:local_cpu_detect(tune)}"
ee7caeb3
DE		 215#else
216#define CC1_CPU_SPEC ""
217#endif
0eab6840
DE		 218#endif
219
fb623df5 220/* Architecture type. */
f045b2c9 221
bb22512c 222/* Define TARGET_MFCRF if the target assembler does not support the
78f5898b 223 optional field operand for mfcr. */
fb623df5 224
78f5898b 225#ifndef HAVE_AS_MFCRF
432218ba 226#undef TARGET_MFCRF
ffa22984
DE		 227#define TARGET_MFCRF 0
228#endif
229
0fa2e4df 230/* Define TARGET_POPCNTB if the target assembler does not support the
432218ba
DE		 231 popcount byte instruction. */
232
233#ifndef HAVE_AS_POPCNTB
234#undef TARGET_POPCNTB
235#define TARGET_POPCNTB 0
236#endif
237
9719f3b7
DE		 238/* Define TARGET_FPRND if the target assembler does not support the
239 fp rounding instructions. */
240
241#ifndef HAVE_AS_FPRND
242#undef TARGET_FPRND
243#define TARGET_FPRND 0
244#endif
245
b639c3c2
JJ		 246/* Define TARGET_CMPB if the target assembler does not support the
247 cmpb instruction. */
248
249#ifndef HAVE_AS_CMPB
250#undef TARGET_CMPB
251#define TARGET_CMPB 0
252#endif
253
44cd321e
PS		 254/* Define TARGET_MFPGPR if the target assembler does not support the
255 mffpr and mftgpr instructions. */
256
257#ifndef HAVE_AS_MFPGPR
258#undef TARGET_MFPGPR
259#define TARGET_MFPGPR 0
260#endif
261
b639c3c2
JJ		 262/* Define TARGET_DFP if the target assembler does not support decimal
263 floating point instructions. */
264#ifndef HAVE_AS_DFP
265#undef TARGET_DFP
266#define TARGET_DFP 0
267#endif
268
cacf1ca8
MM		 269/* Define TARGET_POPCNTD if the target assembler does not support the
270 popcount word and double word instructions. */
271
272#ifndef HAVE_AS_POPCNTD
273#undef TARGET_POPCNTD
274#define TARGET_POPCNTD 0
275#endif
276
277/* Define TARGET_LWSYNC_INSTRUCTION if the assembler knows about lwsync. If
278 not, generate the lwsync code as an integer constant. */
279#ifdef HAVE_AS_LWSYNC
280#define TARGET_LWSYNC_INSTRUCTION 1
281#else
282#define TARGET_LWSYNC_INSTRUCTION 0
283#endif
284
9752c4ad
AM		 285/* Define TARGET_TLS_MARKERS if the target assembler does not support
286 arg markers for __tls_get_addr calls. */
287#ifndef HAVE_AS_TLS_MARKERS
288#undef TARGET_TLS_MARKERS
289#define TARGET_TLS_MARKERS 0
290#else
291#define TARGET_TLS_MARKERS tls_markers
292#endif
293
7f970b70
AM		 294#ifndef TARGET_SECURE_PLT
295#define TARGET_SECURE_PLT 0
296#endif
297
070b27da
AM		 298/* Code model for 64-bit linux.
299 small: 16-bit toc offsets.
5a79bcc4
AM		 300 medium: 32-bit toc offsets, static data and code within 2G of TOC pointer.
301 large: 32-bit toc offsets, no limit on static data and code. */
070b27da
AM		 302enum rs6000_cmodel {
303 CMODEL_SMALL,
5a79bcc4 304 CMODEL_MEDIUM,
070b27da
AM		 305 CMODEL_LARGE
306};
307
308#ifndef TARGET_CMODEL
309#define TARGET_CMODEL CMODEL_SMALL
310#endif
311
2f3e5814 312#define TARGET_32BIT (! TARGET_64BIT)
d14a6d05 313
c4501e62
JJ		 314#ifndef HAVE_AS_TLS
315#define HAVE_AS_TLS 0
316#endif
317
48d72335
DE		 318/* Return 1 for a symbol ref for a thread-local storage symbol. */
319#define RS6000_SYMBOL_REF_TLS_P(RTX) \
320 (GET_CODE (RTX) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (RTX) != 0)
321
996ed075
JJ		 322#ifdef IN_LIBGCC2
323/* For libgcc2 we make sure this is a compile time constant */
67796c1f 324#if defined (__64BIT__) || defined (__powerpc64__) || defined (__ppc64__)
78f5898b 325#undef TARGET_POWERPC64
996ed075
JJ		 326#define TARGET_POWERPC64 1
327#else
78f5898b 328#undef TARGET_POWERPC64
996ed075
JJ		 329#define TARGET_POWERPC64 0
330#endif
b6c9286a 331#else
78f5898b 332 /* The option machinery will define this. */
b6c9286a
MM		 333#endif
334
938937d8 335#define TARGET_DEFAULT (MASK_POWER | MASK_MULTIPLE | MASK_STRING)
9ebbca7d 336
cac8ce95 337/* Processor type. Order must match cpu attribute in MD file. */
fb623df5 338enum processor_type
bef84347
VM		 339 {
340 PROCESSOR_RIOS1,
341 PROCESSOR_RIOS2,
3cb999d8 342 PROCESSOR_RS64A,
bef84347
VM		 343 PROCESSOR_MPCCORE,
344 PROCESSOR_PPC403,
fe7f5677 345 PROCESSOR_PPC405,
b54cf83a 346 PROCESSOR_PPC440,
47f67e51 347 PROCESSOR_PPC476,
bef84347
VM		 348 PROCESSOR_PPC601,
349 PROCESSOR_PPC603,
350 PROCESSOR_PPC604,
351 PROCESSOR_PPC604e,
352 PROCESSOR_PPC620,
3cb999d8 353 PROCESSOR_PPC630,
ed947a96
DJ		 354 PROCESSOR_PPC750,
355 PROCESSOR_PPC7400,
309323c2 356 PROCESSOR_PPC7450,
a3170dc6 357 PROCESSOR_PPC8540,
fa41c305
EW		 358 PROCESSOR_PPCE300C2,
359 PROCESSOR_PPCE300C3,
edae5fe3 360 PROCESSOR_PPCE500MC,
b17f98b1 361 PROCESSOR_PPCE500MC64,
ec507f2d 362 PROCESSOR_POWER4,
44cd321e 363 PROCESSOR_POWER5,
d296e02e 364 PROCESSOR_POWER6,
cacf1ca8 365 PROCESSOR_POWER7,
ebde32fd 366 PROCESSOR_CELL,
dfecaf59
PT		 367 PROCESSOR_PPCA2,
368 PROCESSOR_TITAN
bef84347 369};
fb623df5 370
696e45ba
ME		 371/* FPU operations supported.
372 Each use of TARGET_SINGLE_FLOAT or TARGET_DOUBLE_FLOAT must
373 also test TARGET_HARD_FLOAT. */
374#define TARGET_SINGLE_FLOAT 1
375#define TARGET_DOUBLE_FLOAT 1
376#define TARGET_SINGLE_FPU 0
377#define TARGET_SIMPLE_FPU 0
0bb7b92e 378#define TARGET_XILINX_FPU 0
696e45ba 379
fb623df5
RK		 380extern enum processor_type rs6000_cpu;
381
382/* Recast the processor type to the cpu attribute. */
383#define rs6000_cpu_attr ((enum attr_cpu)rs6000_cpu)
384
8482e358 385/* Define generic processor types based upon current deployment. */
3cb999d8
DE		 386#define PROCESSOR_COMMON PROCESSOR_PPC601
387#define PROCESSOR_POWER PROCESSOR_RIOS1
388#define PROCESSOR_POWERPC PROCESSOR_PPC604
389#define PROCESSOR_POWERPC64 PROCESSOR_RS64A
6e151478 390
fb623df5 391/* Define the default processor. This is overridden by other tm.h files. */
3cb999d8
DE		 392#define PROCESSOR_DEFAULT PROCESSOR_RIOS1
393#define PROCESSOR_DEFAULT64 PROCESSOR_RS64A
fb623df5 394
0bb7b92e
ME		 395/* FP processor type. */
396enum fpu_type_t
397{
398 FPU_NONE, /* No FPU */
399 FPU_SF_LITE, /* Limited Single Precision FPU */
400 FPU_DF_LITE, /* Limited Double Precision FPU */
401 FPU_SF_FULL, /* Full Single Precision FPU */
402 FPU_DF_FULL /* Full Double Single Precision FPU */
403};
404
405extern enum fpu_type_t fpu_type;
406
6febd581
RK		 407/* Specify the dialect of assembler to use. New mnemonics is dialect one
408 and the old mnemonics are dialect zero. */
9ebbca7d 409#define ASSEMBLER_DIALECT (TARGET_NEW_MNEMONICS ? 1 : 0)
6febd581 410
569fa502
DN		 411/* Types of costly dependences. */
412enum rs6000_dependence_cost
413 {
414 max_dep_latency = 1000,
415 no_dep_costly,
416 all_deps_costly,
417 true_store_to_load_dep_costly,
418 store_to_load_dep_costly
419 };
420
cbe26ab8
DN		 421/* Types of nop insertion schemes in sched target hook sched_finish. */
422enum rs6000_nop_insertion
423 {
424 sched_finish_regroup_exact = 1000,
425 sched_finish_pad_groups,
426 sched_finish_none
427 };
428
429/* Dispatch group termination caused by an insn. */
430enum group_termination
431 {
432 current_group,
433 previous_group
434 };
435
ff222560 436/* rs6000_select[0] is reserved for the default cpu defined via --with-cpu */
8e3f41e7
MM		 437struct rs6000_cpu_select
438{
815cdc52
MM		 439 const char *string;
440 const char *name;
8e3f41e7
MM		 441 int set_tune_p;
442 int set_arch_p;
443};
444
445extern struct rs6000_cpu_select rs6000_select[];
fb623df5 446
38c1f2d7 447/* Debug support */
0ac081f6 448extern const char *rs6000_debug_name; /* Name for -mdebug-xxxx option */
38c1f2d7
MM		 449extern int rs6000_debug_stack; /* debug stack applications */
450extern int rs6000_debug_arg; /* debug argument handling */
cacf1ca8
MM		 451extern int rs6000_debug_reg; /* debug register handling */
452extern int rs6000_debug_addr; /* debug memory addressing */
453extern int rs6000_debug_cost; /* debug rtx_costs */
38c1f2d7
MM		 454
455#define TARGET_DEBUG_STACK rs6000_debug_stack
456#define TARGET_DEBUG_ARG rs6000_debug_arg
cacf1ca8
MM		 457#define TARGET_DEBUG_REG rs6000_debug_reg
458#define TARGET_DEBUG_ADDR rs6000_debug_addr
459#define TARGET_DEBUG_COST rs6000_debug_cost
38c1f2d7 460
57ac7be9
AM		 461extern const char *rs6000_traceback_name; /* Type of traceback table. */
462
6fa3f289
ZW		 463/* These are separate from target_flags because we've run out of bits
464 there. */
6fa3f289 465extern int rs6000_long_double_type_size;
602ea4d3 466extern int rs6000_ieeequad;
6fa3f289 467extern int rs6000_altivec_abi;
a3170dc6 468extern int rs6000_spe_abi;
94f4765c 469extern int rs6000_spe;
5da702b1 470extern int rs6000_float_gprs;
025d9908 471extern int rs6000_alignment_flags;
cbe26ab8
DN		 472extern const char *rs6000_sched_insert_nops_str;
473extern enum rs6000_nop_insertion rs6000_sched_insert_nops;
0bb7b92e 474extern int rs6000_xilinx_fpu;
025d9908 475
cacf1ca8
MM		 476/* Describe which vector unit to use for a given machine mode. */
477enum rs6000_vector {
478 VECTOR_NONE, /* Type is not a vector or not supported */
479 VECTOR_ALTIVEC, /* Use altivec for vector processing */
480 VECTOR_VSX, /* Use VSX for vector processing */
481 VECTOR_PAIRED, /* Use paired floating point for vectors */
482 VECTOR_SPE, /* Use SPE for vector processing */
483 VECTOR_OTHER /* Some other vector unit */
484};
485
486extern enum rs6000_vector rs6000_vector_unit[];
487
488#define VECTOR_UNIT_NONE_P(MODE) \
489 (rs6000_vector_unit[(MODE)] == VECTOR_NONE)
490
491#define VECTOR_UNIT_VSX_P(MODE) \
492 (rs6000_vector_unit[(MODE)] == VECTOR_VSX)
493
494#define VECTOR_UNIT_ALTIVEC_P(MODE) \
495 (rs6000_vector_unit[(MODE)] == VECTOR_ALTIVEC)
496
497#define VECTOR_UNIT_ALTIVEC_OR_VSX_P(MODE) \
498 (rs6000_vector_unit[(MODE)] == VECTOR_ALTIVEC \
499 || rs6000_vector_unit[(MODE)] == VECTOR_VSX)
500
501/* Describe whether to use VSX loads or Altivec loads. For now, just use the
502 same unit as the vector unit we are using, but we may want to migrate to
503 using VSX style loads even for types handled by altivec. */
504extern enum rs6000_vector rs6000_vector_mem[];
505
506#define VECTOR_MEM_NONE_P(MODE) \
507 (rs6000_vector_mem[(MODE)] == VECTOR_NONE)
508
509#define VECTOR_MEM_VSX_P(MODE) \
510 (rs6000_vector_mem[(MODE)] == VECTOR_VSX)
511
512#define VECTOR_MEM_ALTIVEC_P(MODE) \
513 (rs6000_vector_mem[(MODE)] == VECTOR_ALTIVEC)
514
515#define VECTOR_MEM_ALTIVEC_OR_VSX_P(MODE) \
516 (rs6000_vector_mem[(MODE)] == VECTOR_ALTIVEC \
517 || rs6000_vector_mem[(MODE)] == VECTOR_VSX)
518
519/* Return the alignment of a given vector type, which is set based on the
520 vector unit use. VSX for instance can load 32 or 64 bit aligned words
521 without problems, while Altivec requires 128-bit aligned vectors. */
522extern int rs6000_vector_align[];
523
524#define VECTOR_ALIGN(MODE) \
525 ((rs6000_vector_align[(MODE)] != 0) \
526 ? rs6000_vector_align[(MODE)] \
527 : (int)GET_MODE_BITSIZE ((MODE)))
528
025d9908
KH		 529/* Alignment options for fields in structures for sub-targets following
530 AIX-like ABI.
531 ALIGN_POWER word-aligns FP doubles (default AIX ABI).
532 ALIGN_NATURAL doubleword-aligns FP doubles (align to object size).
533
534 Override the macro definitions when compiling libobjc to avoid undefined
535 reference to rs6000_alignment_flags due to library's use of GCC alignment
536 macros which use the macros below. */
f676971a 537
025d9908
KH		 538#ifndef IN_TARGET_LIBS
539#define MASK_ALIGN_POWER 0x00000000
540#define MASK_ALIGN_NATURAL 0x00000001
541#define TARGET_ALIGN_NATURAL (rs6000_alignment_flags & MASK_ALIGN_NATURAL)
542#else
543#define TARGET_ALIGN_NATURAL 0
544#endif
6fa3f289
ZW		 545
546#define TARGET_LONG_DOUBLE_128 (rs6000_long_double_type_size == 128)
602ea4d3 547#define TARGET_IEEEQUAD rs6000_ieeequad
6fa3f289 548#define TARGET_ALTIVEC_ABI rs6000_altivec_abi
cacf1ca8 549#define TARGET_LDBRX (TARGET_POPCNTD || rs6000_cpu == PROCESSOR_CELL)
6fa3f289 550
a3170dc6
AH		 551#define TARGET_SPE_ABI 0
552#define TARGET_SPE 0
993f19a8 553#define TARGET_E500 0
cacf1ca8 554#define TARGET_ISEL64 (TARGET_ISEL && TARGET_POWERPC64)
a3170dc6 555#define TARGET_FPRS 1
4d4cbc0e
AH		 556#define TARGET_E500_SINGLE 0
557#define TARGET_E500_DOUBLE 0
eca0d5e8 558#define CHECK_E500_OPTIONS do { } while (0)
a3170dc6 559
7042fe5e
MM		 560/* ISA 2.01 allowed FCFID to be done in 32-bit, previously it was 64-bit only.
561 Enable 32-bit fcfid's on any of the switches for newer ISA machines or
562 XILINX. */
563#define TARGET_FCFID (TARGET_POWERPC64 \
564 || TARGET_POPCNTB /* ISA 2.02 */ \
565 || TARGET_CMPB /* ISA 2.05 */ \
566 || TARGET_POPCNTD /* ISA 2.06 */ \
567 || TARGET_XILINX_FPU)
568
569#define TARGET_FCTIDZ TARGET_FCFID
570#define TARGET_STFIWX TARGET_PPC_GFXOPT
571#define TARGET_LFIWAX TARGET_CMPB
572#define TARGET_LFIWZX TARGET_POPCNTD
573#define TARGET_FCFIDS TARGET_POPCNTD
574#define TARGET_FCFIDU TARGET_POPCNTD
575#define TARGET_FCFIDUS TARGET_POPCNTD
576#define TARGET_FCTIDUZ TARGET_POPCNTD
577#define TARGET_FCTIWUZ TARGET_POPCNTD
578
86098753
JM		 579/* E500 processors only support plain "sync", not lwsync. */
580#define TARGET_NO_LWSYNC TARGET_E500
581
92902797
MM		 582/* Which machine supports the various reciprocal estimate instructions. */
583#define TARGET_FRES (TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT \
584 && TARGET_FPRS && TARGET_SINGLE_FLOAT)
585
586#define TARGET_FRE (TARGET_HARD_FLOAT && TARGET_FPRS \
587 && TARGET_DOUBLE_FLOAT \
588 && (TARGET_POPCNTB || VECTOR_UNIT_VSX_P (DFmode)))
589
590#define TARGET_FRSQRTES (TARGET_HARD_FLOAT && TARGET_POPCNTB \
591 && TARGET_FPRS && TARGET_SINGLE_FLOAT)
592
593#define TARGET_FRSQRTE (TARGET_HARD_FLOAT && TARGET_FPRS \
594 && TARGET_DOUBLE_FLOAT \
595 && (TARGET_PPC_GFXOPT || VECTOR_UNIT_VSX_P (DFmode)))
596
597/* Whether the various reciprocal divide/square root estimate instructions
598 exist, and whether we should automatically generate code for the instruction
599 by default. */
600#define RS6000_RECIP_MASK_HAVE_RE 0x1 /* have RE instruction. */
601#define RS6000_RECIP_MASK_AUTO_RE 0x2 /* generate RE by default. */
602#define RS6000_RECIP_MASK_HAVE_RSQRTE 0x4 /* have RSQRTE instruction. */
603#define RS6000_RECIP_MASK_AUTO_RSQRTE 0x8 /* gen. RSQRTE by default. */
604
605extern unsigned char rs6000_recip_bits[];
606
607#define RS6000_RECIP_HAVE_RE_P(MODE) \
608 (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_HAVE_RE)
609
610#define RS6000_RECIP_AUTO_RE_P(MODE) \
611 (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_AUTO_RE)
612
613#define RS6000_RECIP_HAVE_RSQRTE_P(MODE) \
614 (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_HAVE_RSQRTE)
615
616#define RS6000_RECIP_AUTO_RSQRTE_P(MODE) \
617 (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_AUTO_RSQRTE)
618
619#define RS6000_RECIP_HIGH_PRECISION_P(MODE) \
620 ((MODE) == SFmode || (MODE) == V4SFmode || TARGET_RECIP_PRECISION)
621
c5387660
JM		 622/* The default CPU for TARGET_OPTION_OVERRIDE. */
623#define OPTION_TARGET_CPU_DEFAULT TARGET_CPU_DEFAULT
f045b2c9 624
5accd822
DE		 625/* Define this to change the optimizations performed by default. */
626#define OPTIMIZATION_OPTIONS(LEVEL,SIZE) optimization_options(LEVEL,SIZE)
627
4c4eb375
GK		 628/* Show we can debug even without a frame pointer. */
629#define CAN_DEBUG_WITHOUT_FP
630
a5c76ee6 631/* Target pragma. */
c58b209a
NB		 632#define REGISTER_TARGET_PRAGMAS() do { \
633 c_register_pragma (0, "longcall", rs6000_pragma_longcall); \
2fab365e 634 targetm.resolve_overloaded_builtin = altivec_resolve_overloaded_builtin; \
a5c76ee6
ZW		 635} while (0)
636
4c4eb375
GK		 637/* Target #defines. */
638#define TARGET_CPU_CPP_BUILTINS() \
639 rs6000_cpu_cpp_builtins (pfile)
647d340d
JT		 640
641/* This is used by rs6000_cpu_cpp_builtins to indicate the byte order
642 we're compiling for. Some configurations may need to override it. */
643#define RS6000_CPU_CPP_ENDIAN_BUILTINS() \
644 do \
645 { \
646 if (BYTES_BIG_ENDIAN) \
647 { \
648 builtin_define ("__BIG_ENDIAN__"); \
649 builtin_define ("_BIG_ENDIAN"); \
650 builtin_assert ("machine=bigendian"); \
651 } \
652 else \
653 { \
654 builtin_define ("__LITTLE_ENDIAN__"); \
655 builtin_define ("_LITTLE_ENDIAN"); \
656 builtin_assert ("machine=littleendian"); \
657 } \
658 } \
659 while (0)
f045b2c9 660\f
4c4eb375 661/* Target machine storage layout. */
f045b2c9 662
13d39dbc 663/* Define this macro if it is advisable to hold scalars in registers
c81bebd7 664 in a wider mode than that declared by the program. In such cases,
ef457bda
RK		 665 the value is constrained to be within the bounds of the declared
666 type, but kept valid in the wider mode. The signedness of the
667 extension may differ from that of the type. */
668
39403d82
DE		 669#define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
670 if (GET_MODE_CLASS (MODE) == MODE_INT \
671 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
b78d48dd 672 (MODE) = TARGET_32BIT ? SImode : DImode;
39403d82 673
f045b2c9 674/* Define this if most significant bit is lowest numbered
82e41834
KH		 675 in instructions that operate on numbered bit-fields. */
676/* That is true on RS/6000. */
f045b2c9
RS		 677#define BITS_BIG_ENDIAN 1
678
679/* Define this if most significant byte of a word is the lowest numbered. */
680/* That is true on RS/6000. */
681#define BYTES_BIG_ENDIAN 1
682
683/* Define this if most significant word of a multiword number is lowest
c81bebd7 684 numbered.
f045b2c9
RS		 685
686 For RS/6000 we can decide arbitrarily since there are no machine
82e41834 687 instructions for them. Might as well be consistent with bits and bytes. */
f045b2c9
RS		 688#define WORDS_BIG_ENDIAN 1
689
2e360ab3 690#define MAX_BITS_PER_WORD 64
f045b2c9
RS		 691
692/* Width of a word, in units (bytes). */
c1aa3958 693#define UNITS_PER_WORD (! TARGET_POWERPC64 ? 4 : 8)
f34fc46e
DE		 694#ifdef IN_LIBGCC2
695#define MIN_UNITS_PER_WORD UNITS_PER_WORD
696#else
ef0e53ce 697#define MIN_UNITS_PER_WORD 4
f34fc46e 698#endif
2e360ab3 699#define UNITS_PER_FP_WORD 8
0ac081f6 700#define UNITS_PER_ALTIVEC_WORD 16
cacf1ca8 701#define UNITS_PER_VSX_WORD 16
a3170dc6 702#define UNITS_PER_SPE_WORD 8
96038623 703#define UNITS_PER_PAIRED_WORD 8
f045b2c9 704
915f619f
JW		 705/* Type used for ptrdiff_t, as a string used in a declaration. */
706#define PTRDIFF_TYPE "int"
707
058ef853
DE		 708/* Type used for size_t, as a string used in a declaration. */
709#define SIZE_TYPE "long unsigned int"
710
f045b2c9
RS		 711/* Type used for wchar_t, as a string used in a declaration. */
712#define WCHAR_TYPE "short unsigned int"
713
714/* Width of wchar_t in bits. */
715#define WCHAR_TYPE_SIZE 16
716
9e654916
RK		 717/* A C expression for the size in bits of the type `short' on the
718 target machine. If you don't define this, the default is half a
719 word. (If this would be less than one storage unit, it is
720 rounded up to one unit.) */
721#define SHORT_TYPE_SIZE 16
722
723/* A C expression for the size in bits of the type `int' on the
724 target machine. If you don't define this, the default is one
725 word. */
19d2d16f 726#define INT_TYPE_SIZE 32
9e654916
RK		 727
728/* A C expression for the size in bits of the type `long' on the
729 target machine. If you don't define this, the default is one
730 word. */
2f3e5814 731#define LONG_TYPE_SIZE (TARGET_32BIT ? 32 : 64)
9e654916
RK		 732
733/* A C expression for the size in bits of the type `long long' on the
734 target machine. If you don't define this, the default is two
735 words. */
736#define LONG_LONG_TYPE_SIZE 64
737
9e654916
RK		 738/* A C expression for the size in bits of the type `float' on the
739 target machine. If you don't define this, the default is one
740 word. */
741#define FLOAT_TYPE_SIZE 32
742
743/* A C expression for the size in bits of the type `double' on the
744 target machine. If you don't define this, the default is two
745 words. */
746#define DOUBLE_TYPE_SIZE 64
747
748/* A C expression for the size in bits of the type `long double' on
749 the target machine. If you don't define this, the default is two
750 words. */
6fa3f289 751#define LONG_DOUBLE_TYPE_SIZE rs6000_long_double_type_size
06f4e019 752
06f4e019
DE		 753/* Define this to set long double type size to use in libgcc2.c, which can
754 not depend on target_flags. */
755#ifdef __LONG_DOUBLE_128__
756#define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
757#else
758#define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
759#endif
9e654916 760
5b8f5865
DE		 761/* Work around rs6000_long_double_type_size dependency in ada/targtyps.c. */
762#define WIDEST_HARDWARE_FP_SIZE 64
763
f045b2c9
RS		 764/* Width in bits of a pointer.
765 See also the macro `Pmode' defined below. */
cacf1ca8
MM		 766extern unsigned rs6000_pointer_size;
767#define POINTER_SIZE rs6000_pointer_size
f045b2c9
RS		 768
769/* Allocation boundary (in *bits*) for storing arguments in argument list. */
2f3e5814 770#define PARM_BOUNDARY (TARGET_32BIT ? 32 : 64)
f045b2c9
RS		 771
772/* Boundary (in *bits*) on which stack pointer should be aligned. */
cacf1ca8
MM		 773#define STACK_BOUNDARY \
774 ((TARGET_32BIT && !TARGET_ALTIVEC && !TARGET_ALTIVEC_ABI && !TARGET_VSX) \
775 ? 64 : 128)
f045b2c9
RS		 776
777/* Allocation boundary (in *bits*) for the code of a function. */
778#define FUNCTION_BOUNDARY 32
779
780/* No data type wants to be aligned rounder than this. */
0ac081f6
AH		 781#define BIGGEST_ALIGNMENT 128
782
783/* A C expression to compute the alignment for a variables in the
784 local store. TYPE is the data type, and ALIGN is the alignment
785 that the object would ordinarily have. */
786#define LOCAL_ALIGNMENT(TYPE, ALIGN) \
777a3a6a 787 DATA_ALIGNMENT (TYPE, ALIGN)
b73fd26c 788
f045b2c9
RS		 789/* Alignment of field after `int : 0' in a structure. */
790#define EMPTY_FIELD_BOUNDARY 32
791
792/* Every structure's size must be a multiple of this. */
793#define STRUCTURE_SIZE_BOUNDARY 8
794
a3170dc6
AH		 795/* Return 1 if a structure or array containing FIELD should be
796 accessed using `BLKMODE'.
797
798 For the SPE, simd types are V2SI, and gcc can be tempted to put the
799 entire thing in a DI and use subregs to access the internals.
800 store_bit_field() will force (subreg:DI (reg:V2SI x))'s to the
801 back-end. Because a single GPR can hold a V2SI, but not a DI, the
802 best thing to do is set structs to BLKmode and avoid Severe Tire
de334ef6
AH		 803 Damage.
804
805 On e500 v2, DF and DI modes suffer from the same anomaly. DF can
806 fit into 1, whereas DI still needs two. */
a3170dc6 807#define MEMBER_TYPE_FORCES_BLK(FIELD, MODE) \
de334ef6 808 ((TARGET_SPE && TREE_CODE (TREE_TYPE (FIELD)) == VECTOR_TYPE) \
4f011e1e 809 || (TARGET_E500_DOUBLE && (MODE) == DFmode))
a3170dc6 810
43a88a8c 811/* A bit-field declared as `int' forces `int' alignment for the struct. */
f045b2c9
RS		 812#define PCC_BITFIELD_TYPE_MATTERS 1
813
69ef87e2
AH		 814/* Make strings word-aligned so strcpy from constants will be faster.
815 Make vector constants quadword aligned. */
816#define CONSTANT_ALIGNMENT(EXP, ALIGN) \
817 (TREE_CODE (EXP) == STRING_CST \
153fbec8 818 && (STRICT_ALIGNMENT || !optimize_size) \
69ef87e2
AH		 819 && (ALIGN) < BITS_PER_WORD \
820 ? BITS_PER_WORD \
821 : (ALIGN))
f045b2c9 822
0ac081f6 823/* Make arrays of chars word-aligned for the same reasons.
f82f556d
AH		 824 Align vectors to 128 bits. Align SPE vectors and E500 v2 doubles to
825 64 bits. */
b851135c
NF		 826#define DATA_ALIGNMENT(TYPE, ALIGN) \
827 (TREE_CODE (TYPE) == VECTOR_TYPE \
828 ? (((TARGET_SPE && SPE_VECTOR_MODE (TYPE_MODE (TYPE))) \
829 || (TARGET_PAIRED_FLOAT && PAIRED_VECTOR_MODE (TYPE_MODE (TYPE)))) \
830 ? 64 : 128) \
831 : ((TARGET_E500_DOUBLE \
832 && TREE_CODE (TYPE) == REAL_TYPE \
833 && TYPE_MODE (TYPE) == DFmode) \
834 ? 64 \
835 : (TREE_CODE (TYPE) == ARRAY_TYPE \
836 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
837 && (ALIGN) < BITS_PER_WORD) ? BITS_PER_WORD : (ALIGN)))
f045b2c9 838
a0ab749a 839/* Nonzero if move instructions will actually fail to work
f045b2c9 840 when given unaligned data. */
fdaff8ba 841#define STRICT_ALIGNMENT 0
e1565e65
DE		 842
843/* Define this macro to be the value 1 if unaligned accesses have a cost
844 many times greater than aligned accesses, for example if they are
845 emulated in a trap handler. */
cacf1ca8
MM		 846/* Altivec vector memory instructions simply ignore the low bits; SPE vector
847 memory instructions trap on unaligned accesses; VSX memory instructions are
848 aligned to 4 or 8 bytes. */
41543739
GK		 849#define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) \
850 (STRICT_ALIGNMENT \
fcce224d 851 || (((MODE) == SFmode || (MODE) == DFmode || (MODE) == TFmode \
e41b2a33 852 || (MODE) == SDmode || (MODE) == DDmode || (MODE) == TDmode \
fcce224d 853 || (MODE) == DImode) \
54ce9cc2 854 && (ALIGN) < 32) \
cacf1ca8
MM		 855 || (VECTOR_MODE_P ((MODE)) && (((int)(ALIGN)) < VECTOR_ALIGN (MODE))))
856
f045b2c9
RS		 857\f
858/* Standard register usage. */
859
860/* Number of actual hardware registers.
861 The hardware registers are assigned numbers for the compiler
862 from 0 to just below FIRST_PSEUDO_REGISTER.
863 All registers that the compiler knows about must be given numbers,
864 even those that are not normally considered general registers.
865
866 RS/6000 has 32 fixed-point registers, 32 floating-point registers,
867 an MQ register, a count register, a link register, and 8 condition
07488f32
ZW		 868 register fields, which we view here as separate registers. AltiVec
869 adds 32 vector registers and a VRsave register.
f045b2c9
RS		 870
871 In addition, the difference between the frame and argument pointers is
872 a function of the number of registers saved, so we need to have a
873 register for AP that will later be eliminated in favor of SP or FP.
802a0058 874 This is a normal register, but it is fixed.
f045b2c9 875
802a0058
MM		 876 We also create a pseudo register for float/int conversions, that will
877 really represent the memory location used. It is represented here as
878 a register, in order to work around problems in allocating stack storage
7d5175e1 879 in inline functions.
802a0058 880
7d5175e1
JJ		 881 Another pseudo (not included in DWARF_FRAME_REGISTERS) is soft frame
882 pointer, which is eventually eliminated in favor of SP or FP. */
883
884#define FIRST_PSEUDO_REGISTER 114
f045b2c9 885
d6a7951f 886/* This must be included for pre gcc 3.0 glibc compatibility. */
7d5f33bc 887#define PRE_GCC3_DWARF_FRAME_REGISTERS 77
62153b61 888
93c9d1ba 889/* Add 32 dwarf columns for synthetic SPE registers. */
7d5175e1 890#define DWARF_FRAME_REGISTERS ((FIRST_PSEUDO_REGISTER - 1) + 32)
c19de7aa 891
93c9d1ba
AM		 892/* The SPE has an additional 32 synthetic registers, with DWARF debug
893 info numbering for these registers starting at 1200. While eh_frame
894 register numbering need not be the same as the debug info numbering,
895 we choose to number these regs for eh_frame at 1200 too. This allows
896 future versions of the rs6000 backend to add hard registers and
897 continue to use the gcc hard register numbering for eh_frame. If the
898 extra SPE registers in eh_frame were numbered starting from the
899 current value of FIRST_PSEUDO_REGISTER, then if FIRST_PSEUDO_REGISTER
900 changed we'd need to introduce a mapping in DWARF_FRAME_REGNUM to
901 avoid invalidating older SPE eh_frame info.
902
903 We must map them here to avoid huge unwinder tables mostly consisting
f676971a 904 of unused space. */
93c9d1ba 905#define DWARF_REG_TO_UNWIND_COLUMN(r) \
7d5175e1 906 ((r) > 1200 ? ((r) - 1200 + FIRST_PSEUDO_REGISTER - 1) : (r))
93c9d1ba 907
ed1cf8ff
GK		 908/* Use standard DWARF numbering for DWARF debugging information. */
909#define DBX_REGISTER_NUMBER(REGNO) rs6000_dbx_register_number (REGNO)
910
93c9d1ba
AM		 911/* Use gcc hard register numbering for eh_frame. */
912#define DWARF_FRAME_REGNUM(REGNO) (REGNO)
41f3a930 913
ed1cf8ff
GK		 914/* Map register numbers held in the call frame info that gcc has
915 collected using DWARF_FRAME_REGNUM to those that should be output in
916 .debug_frame and .eh_frame. We continue to use gcc hard reg numbers
917 for .eh_frame, but use the numbers mandated by the various ABIs for
918 .debug_frame. rs6000_emit_prologue has translated any combination of
919 CR2, CR3, CR4 saves to a save of CR2. The actual code emitted saves
920 the whole of CR, so we map CR2_REGNO to the DWARF reg for CR. */
921#define DWARF2_FRAME_REG_OUT(REGNO, FOR_EH) \
922 ((FOR_EH) ? (REGNO) \
923 : (REGNO) == CR2_REGNO ? 64 \
924 : DBX_REGISTER_NUMBER (REGNO))
925
f045b2c9
RS		 926/* 1 for registers that have pervasive standard uses
927 and are not available for the register allocator.
928
5dead3e5
DJ		 929 On RS/6000, r1 is used for the stack. On Darwin, r2 is available
930 as a local register; for all other OS's r2 is the TOC pointer.
f045b2c9 931
a127c4e5
RK		 932 cr5 is not supposed to be used.
933
934 On System V implementations, r13 is fixed and not available for use. */
935
f045b2c9 936#define FIXED_REGISTERS \
5dead3e5 937 {0, 1, FIXED_R2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, FIXED_R13, 0, 0, \
f045b2c9
RS		 938 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
939 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
940 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0ac081f6
AH		 941 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 1, \
942 /* AltiVec registers. */ \
943 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
944 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
5f004351 945 1, 1 \
7d5175e1 946 , 1, 1, 1 \
0ac081f6 947}
f045b2c9
RS		 948
949/* 1 for registers not available across function calls.
950 These must include the FIXED_REGISTERS and also any
951 registers that can be used without being saved.
952 The latter must include the registers where values are returned
953 and the register where structure-value addresses are passed.
954 Aside from that, you can include as many other registers as you like. */
955
956#define CALL_USED_REGISTERS \
a127c4e5 957 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \
f045b2c9
RS		 958 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
959 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \
960 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0ac081f6
AH		 961 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, \
962 /* AltiVec registers. */ \
963 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
964 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
5f004351 965 1, 1 \
7d5175e1 966 , 1, 1, 1 \
0ac081f6
AH		 967}
968
289e96b2
AH		 969/* Like `CALL_USED_REGISTERS' except this macro doesn't require that
970 the entire set of `FIXED_REGISTERS' be included.
971 (`CALL_USED_REGISTERS' must be a superset of `FIXED_REGISTERS').
972 This macro is optional. If not specified, it defaults to the value
973 of `CALL_USED_REGISTERS'. */
f676971a 974
289e96b2
AH		 975#define CALL_REALLY_USED_REGISTERS \
976 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \
977 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
978 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \
979 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
980 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, \
981 /* AltiVec registers. */ \
982 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
983 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
5f004351 984 0, 0 \
7d5175e1 985 , 0, 0, 0 \
289e96b2 986}
f045b2c9 987
28bcfd4d 988#define TOTAL_ALTIVEC_REGS (LAST_ALTIVEC_REGNO - FIRST_ALTIVEC_REGNO + 1)
9ebbca7d 989
d62294f5
FJ		 990#define FIRST_SAVED_ALTIVEC_REGNO (FIRST_ALTIVEC_REGNO+20)
991#define FIRST_SAVED_FP_REGNO (14+32)
992#define FIRST_SAVED_GP_REGNO 13
993
f045b2c9
RS		 994/* List the order in which to allocate registers. Each register must be
995 listed once, even those in FIXED_REGISTERS.
996
997 We allocate in the following order:
998 fp0 (not saved or used for anything)
999 fp13 - fp2 (not saved; incoming fp arg registers)
1000 fp1 (not saved; return value)
9390387d 1001 fp31 - fp14 (saved; order given to save least number)
5accd822
DE		 1002 cr7, cr6 (not saved or special)
1003 cr1 (not saved, but used for FP operations)
f045b2c9 1004 cr0 (not saved, but used for arithmetic operations)
5accd822 1005 cr4, cr3, cr2 (saved)
9390387d 1006 r0 (not saved; cannot be base reg)
f045b2c9
RS		 1007 r9 (not saved; best for TImode)
1008 r11, r10, r8-r4 (not saved; highest used first to make less conflict)
9390387d 1009 r3 (not saved; return value register)
f045b2c9
RS		 1010 r31 - r13 (saved; order given to save least number)
1011 r12 (not saved; if used for DImode or DFmode would use r13)
1012 mq (not saved; best to use it if we can)
1013 ctr (not saved; when we have the choice ctr is better)
1014 lr (saved)
f6b5d695 1015 cr5, r1, r2, ap, ca (fixed)
9390387d
AM		 1016 v0 - v1 (not saved or used for anything)
1017 v13 - v3 (not saved; incoming vector arg registers)
1018 v2 (not saved; incoming vector arg reg; return value)
1019 v19 - v14 (not saved or used for anything)
1020 v31 - v20 (saved; order given to save least number)
1021 vrsave, vscr (fixed)
a3170dc6 1022 spe_acc, spefscr (fixed)
7d5175e1 1023 sfp (fixed)
0ac081f6 1024*/
f676971a 1025
6b13641d
DJ		 1026#if FIXED_R2 == 1
1027#define MAYBE_R2_AVAILABLE
1028#define MAYBE_R2_FIXED 2,
1029#else
1030#define MAYBE_R2_AVAILABLE 2,
1031#define MAYBE_R2_FIXED
1032#endif
f045b2c9 1033
9390387d
AM		 1034#define REG_ALLOC_ORDER \
1035 {32, \
1036 45, 44, 43, 42, 41, 40, 39, 38, 37, 36, 35, 34, \
1037 33, \
1038 63, 62, 61, 60, 59, 58, 57, 56, 55, 54, 53, 52, 51, \
1039 50, 49, 48, 47, 46, \
1040 75, 74, 69, 68, 72, 71, 70, \
1041 0, MAYBE_R2_AVAILABLE \
1042 9, 11, 10, 8, 7, 6, 5, 4, \
1043 3, \
1044 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, \
1045 18, 17, 16, 15, 14, 13, 12, \
1046 64, 66, 65, \
1047 73, 1, MAYBE_R2_FIXED 67, 76, \
1048 /* AltiVec registers. */ \
1049 77, 78, \
1050 90, 89, 88, 87, 86, 85, 84, 83, 82, 81, 80, \
1051 79, \
1052 96, 95, 94, 93, 92, 91, \
1053 108, 107, 106, 105, 104, 103, 102, 101, 100, 99, 98, 97, \
1054 109, 110, \
7d5175e1 1055 111, 112, 113 \
0ac081f6 1056}
f045b2c9
RS		 1057
1058/* True if register is floating-point. */
1059#define FP_REGNO_P(N) ((N) >= 32 && (N) <= 63)
1060
1061/* True if register is a condition register. */
1de43f85 1062#define CR_REGNO_P(N) ((N) >= CR0_REGNO && (N) <= CR7_REGNO)
f045b2c9 1063
815cdc52 1064/* True if register is a condition register, but not cr0. */
1de43f85 1065#define CR_REGNO_NOT_CR0_P(N) ((N) >= CR1_REGNO && (N) <= CR7_REGNO)
815cdc52 1066
f045b2c9 1067/* True if register is an integer register. */
7d5175e1
JJ		 1068#define INT_REGNO_P(N) \
1069 ((N) <= 31 || (N) == ARG_POINTER_REGNUM || (N) == FRAME_POINTER_REGNUM)
f045b2c9 1070
a3170dc6
AH		 1071/* SPE SIMD registers are just the GPRs. */
1072#define SPE_SIMD_REGNO_P(N) ((N) <= 31)
1073
96038623
DE		 1074/* PAIRED SIMD registers are just the FPRs. */
1075#define PAIRED_SIMD_REGNO_P(N) ((N) >= 32 && (N) <= 63)
1076
f6b5d695
SB		 1077/* True if register is the CA register. */
1078#define CA_REGNO_P(N) ((N) == CA_REGNO)
802a0058 1079
0ac081f6
AH		 1080/* True if register is an AltiVec register. */
1081#define ALTIVEC_REGNO_P(N) ((N) >= FIRST_ALTIVEC_REGNO && (N) <= LAST_ALTIVEC_REGNO)
1082
cacf1ca8
MM		 1083/* True if register is a VSX register. */
1084#define VSX_REGNO_P(N) (FP_REGNO_P (N) || ALTIVEC_REGNO_P (N))
1085
1086/* Alternate name for any vector register supporting floating point, no matter
1087 which instruction set(s) are available. */
1088#define VFLOAT_REGNO_P(N) \
1089 (ALTIVEC_REGNO_P (N) || (TARGET_VSX && FP_REGNO_P (N)))
1090
1091/* Alternate name for any vector register supporting integer, no matter which
1092 instruction set(s) are available. */
1093#define VINT_REGNO_P(N) ALTIVEC_REGNO_P (N)
1094
1095/* Alternate name for any vector register supporting logical operations, no
1096 matter which instruction set(s) are available. */
1097#define VLOGICAL_REGNO_P(N) VFLOAT_REGNO_P (N)
1098
f045b2c9 1099/* Return number of consecutive hard regs needed starting at reg REGNO
d8ecbcdb
AH		 1100 to hold something of mode MODE. */
1101
cacf1ca8 1102#define HARD_REGNO_NREGS(REGNO, MODE) rs6000_hard_regno_nregs[(MODE)][(REGNO)]
0e67400a 1103
3fc841c8
MM		 1104#define HARD_REGNO_CALL_PART_CLOBBERED(REGNO, MODE) \
1105 (((TARGET_32BIT && TARGET_POWERPC64 \
1106 && (GET_MODE_SIZE (MODE) > 4) \
1107 && INT_REGNO_P (REGNO)) ? 1 : 0) \
1108 || (TARGET_VSX && FP_REGNO_P (REGNO) \
1109 && GET_MODE_SIZE (MODE) > 8))
f045b2c9 1110
cacf1ca8
MM		 1111#define VSX_VECTOR_MODE(MODE) \
1112 ((MODE) == V4SFmode \
1113 || (MODE) == V2DFmode) \
1114
1115#define VSX_SCALAR_MODE(MODE) \
1116 ((MODE) == DFmode)
1117
1118#define VSX_MODE(MODE) \
1119 (VSX_VECTOR_MODE (MODE) \
1120 || VSX_SCALAR_MODE (MODE))
1121
1122#define VSX_MOVE_MODE(MODE) \
1123 (VSX_VECTOR_MODE (MODE) \
1124 || VSX_SCALAR_MODE (MODE) \
1125 || ALTIVEC_VECTOR_MODE (MODE) \
1126 || (MODE) == TImode)
1127
0ac081f6 1128#define ALTIVEC_VECTOR_MODE(MODE) \
cb2a532e
AH		 1129 ((MODE) == V16QImode \
1130 || (MODE) == V8HImode \
1131 || (MODE) == V4SFmode \
6e1f54e2 1132 || (MODE) == V4SImode)
0ac081f6 1133
a3170dc6
AH		 1134#define SPE_VECTOR_MODE(MODE) \
1135 ((MODE) == V4HImode \
1136 || (MODE) == V2SFmode \
00a892b8 1137 || (MODE) == V1DImode \
a3170dc6
AH		 1138 || (MODE) == V2SImode)
1139
96038623
DE		 1140#define PAIRED_VECTOR_MODE(MODE) \
1141 ((MODE) == V2SFmode)
1142
0d1fbc8c
AH		 1143/* Value is TRUE if hard register REGNO can hold a value of
1144 machine-mode MODE. */
1145#define HARD_REGNO_MODE_OK(REGNO, MODE) \
1146 rs6000_hard_regno_mode_ok_p[(int)(MODE)][REGNO]
f045b2c9
RS		 1147
1148/* Value is 1 if it is a good idea to tie two pseudo registers
1149 when one has mode MODE1 and one has mode MODE2.
1150 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1151 for any hard reg, then this must be 0 for correct output. */
1152#define MODES_TIEABLE_P(MODE1, MODE2) \
ebb109ad
BE		 1153 (SCALAR_FLOAT_MODE_P (MODE1) \
1154 ? SCALAR_FLOAT_MODE_P (MODE2) \
1155 : SCALAR_FLOAT_MODE_P (MODE2) \
1156 ? SCALAR_FLOAT_MODE_P (MODE1) \
f045b2c9
RS		 1157 : GET_MODE_CLASS (MODE1) == MODE_CC \
1158 ? GET_MODE_CLASS (MODE2) == MODE_CC \
1159 : GET_MODE_CLASS (MODE2) == MODE_CC \
1160 ? GET_MODE_CLASS (MODE1) == MODE_CC \
4dcc01f3
AH		 1161 : SPE_VECTOR_MODE (MODE1) \
1162 ? SPE_VECTOR_MODE (MODE2) \
1163 : SPE_VECTOR_MODE (MODE2) \
1164 ? SPE_VECTOR_MODE (MODE1) \
0ac081f6
AH		 1165 : ALTIVEC_VECTOR_MODE (MODE1) \
1166 ? ALTIVEC_VECTOR_MODE (MODE2) \
1167 : ALTIVEC_VECTOR_MODE (MODE2) \
1168 ? ALTIVEC_VECTOR_MODE (MODE1) \
cacf1ca8
MM		 1169 : VSX_VECTOR_MODE (MODE1) \
1170 ? VSX_VECTOR_MODE (MODE2) \
1171 : VSX_VECTOR_MODE (MODE2) \
1172 ? VSX_VECTOR_MODE (MODE1) \
f045b2c9
RS		 1173 : 1)
1174
c8ae788f
SB		 1175/* Post-reload, we can't use any new AltiVec registers, as we already
1176 emitted the vrsave mask. */
1177
1178#define HARD_REGNO_RENAME_OK(SRC, DST) \
6fb5fa3c 1179 (! ALTIVEC_REGNO_P (DST) || df_regs_ever_live_p (DST))
c8ae788f 1180
f045b2c9
RS		 1181/* Specify the cost of a branch insn; roughly the number of extra insns that
1182 should be added to avoid a branch.
1183
ef457bda 1184 Set this to 3 on the RS/6000 since that is roughly the average cost of an
f045b2c9
RS		 1185 unscheduled conditional branch. */
1186
3a4fd356 1187#define BRANCH_COST(speed_p, predictable_p) 3
f045b2c9 1188
85e50b6b 1189/* Override BRANCH_COST heuristic which empirically produces worse
b8610a53 1190 performance for removing short circuiting from the logical ops. */
85e50b6b 1191
b8610a53 1192#define LOGICAL_OP_NON_SHORT_CIRCUIT 0
a3170dc6 1193
52ff33d0
NF		 1194/* A fixed register used at epilogue generation to address SPE registers
1195 with negative offsets. The 64-bit load/store instructions on the SPE
1196 only take positive offsets (and small ones at that), so we need to
1197 reserve a register for consing up negative offsets. */
a3170dc6 1198
52ff33d0 1199#define FIXED_SCRATCH 0
a3170dc6 1200
2aa4498c
AH		 1201/* Define this macro to change register usage conditional on target
1202 flags. */
f85f4585 1203
2aa4498c 1204#define CONDITIONAL_REGISTER_USAGE rs6000_conditional_register_usage ()
6febd581 1205
f045b2c9
RS		 1206/* Specify the registers used for certain standard purposes.
1207 The values of these macros are register numbers. */
1208
1209/* RS/6000 pc isn't overloaded on a register that the compiler knows about. */
1210/* #define PC_REGNUM */
1211
1212/* Register to use for pushing function arguments. */
1213#define STACK_POINTER_REGNUM 1
1214
1215/* Base register for access to local variables of the function. */
7d5175e1
JJ		 1216#define HARD_FRAME_POINTER_REGNUM 31
1217
1218/* Base register for access to local variables of the function. */
1219#define FRAME_POINTER_REGNUM 113
f045b2c9 1220
f045b2c9
RS		 1221/* Base register for access to arguments of the function. */
1222#define ARG_POINTER_REGNUM 67
1223
1224/* Place to put static chain when calling a function that requires it. */
1225#define STATIC_CHAIN_REGNUM 11
1226
f045b2c9
RS		 1227\f
1228/* Define the classes of registers for register constraints in the
1229 machine description. Also define ranges of constants.
1230
1231 One of the classes must always be named ALL_REGS and include all hard regs.
1232 If there is more than one class, another class must be named NO_REGS
1233 and contain no registers.
1234
1235 The name GENERAL_REGS must be the name of a class (or an alias for
1236 another name such as ALL_REGS). This is the class of registers
1237 that is allowed by "g" or "r" in a register constraint.
1238 Also, registers outside this class are allocated only when
1239 instructions express preferences for them.
1240
1241 The classes must be numbered in nondecreasing order; that is,
1242 a larger-numbered class must never be contained completely
1243 in a smaller-numbered class.
1244
1245 For any two classes, it is very desirable that there be another
1246 class that represents their union. */
c81bebd7 1247
cacf1ca8
MM		 1248/* The RS/6000 has three types of registers, fixed-point, floating-point, and
1249 condition registers, plus three special registers, MQ, CTR, and the link
1250 register. AltiVec adds a vector register class. VSX registers overlap the
1251 FPR registers and the Altivec registers.
f045b2c9
RS		 1252
1253 However, r0 is special in that it cannot be used as a base register.
1254 So make a class for registers valid as base registers.
1255
1256 Also, cr0 is the only condition code register that can be used in
0d86f538 1257 arithmetic insns, so make a separate class for it. */
f045b2c9 1258
ebedb4dd
MM		 1259enum reg_class
1260{
1261 NO_REGS,
ebedb4dd
MM		 1262 BASE_REGS,
1263 GENERAL_REGS,
1264 FLOAT_REGS,
0ac081f6 1265 ALTIVEC_REGS,
8beb65e3 1266 VSX_REGS,
0ac081f6 1267 VRSAVE_REGS,
5f004351 1268 VSCR_REGS,
a3170dc6
AH		 1269 SPE_ACC_REGS,
1270 SPEFSCR_REGS,
ebedb4dd
MM		 1271 NON_SPECIAL_REGS,
1272 MQ_REGS,
1273 LINK_REGS,
1274 CTR_REGS,
1275 LINK_OR_CTR_REGS,
1276 SPECIAL_REGS,
1277 SPEC_OR_GEN_REGS,
1278 CR0_REGS,
ebedb4dd
MM		 1279 CR_REGS,
1280 NON_FLOAT_REGS,
f6b5d695 1281 CA_REGS,
ebedb4dd
MM		 1282 ALL_REGS,
1283 LIM_REG_CLASSES
1284};
f045b2c9
RS		 1285
1286#define N_REG_CLASSES (int) LIM_REG_CLASSES
1287
82e41834 1288/* Give names of register classes as strings for dump file. */
f045b2c9 1289
ebedb4dd
MM		 1290#define REG_CLASS_NAMES \
1291{ \
1292 "NO_REGS", \
ebedb4dd
MM		 1293 "BASE_REGS", \
1294 "GENERAL_REGS", \
1295 "FLOAT_REGS", \
0ac081f6 1296 "ALTIVEC_REGS", \
8beb65e3 1297 "VSX_REGS", \
0ac081f6 1298 "VRSAVE_REGS", \
5f004351 1299 "VSCR_REGS", \
a3170dc6
AH		 1300 "SPE_ACC_REGS", \
1301 "SPEFSCR_REGS", \
ebedb4dd
MM		 1302 "NON_SPECIAL_REGS", \
1303 "MQ_REGS", \
1304 "LINK_REGS", \
1305 "CTR_REGS", \
1306 "LINK_OR_CTR_REGS", \
1307 "SPECIAL_REGS", \
1308 "SPEC_OR_GEN_REGS", \
1309 "CR0_REGS", \
ebedb4dd
MM		 1310 "CR_REGS", \
1311 "NON_FLOAT_REGS", \
f6b5d695 1312 "CA_REGS", \
ebedb4dd
MM		 1313 "ALL_REGS" \
1314}
f045b2c9
RS		 1315
1316/* Define which registers fit in which classes.
1317 This is an initializer for a vector of HARD_REG_SET
1318 of length N_REG_CLASSES. */
1319
0ac081f6
AH		 1320#define REG_CLASS_CONTENTS \
1321{ \
1322 { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
7d5175e1
JJ		 1323 { 0xfffffffe, 0x00000000, 0x00000008, 0x00020000 }, /* BASE_REGS */ \
1324 { 0xffffffff, 0x00000000, 0x00000008, 0x00020000 }, /* GENERAL_REGS */ \
0ac081f6 1325 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000 }, /* FLOAT_REGS */ \
089a05b8 1326 { 0x00000000, 0x00000000, 0xffffe000, 0x00001fff }, /* ALTIVEC_REGS */ \
8beb65e3 1327 { 0x00000000, 0xffffffff, 0xffffe000, 0x00001fff }, /* VSX_REGS */ \
089a05b8 1328 { 0x00000000, 0x00000000, 0x00000000, 0x00002000 }, /* VRSAVE_REGS */ \
5f004351 1329 { 0x00000000, 0x00000000, 0x00000000, 0x00004000 }, /* VSCR_REGS */ \
a3170dc6
AH		 1330 { 0x00000000, 0x00000000, 0x00000000, 0x00008000 }, /* SPE_ACC_REGS */ \
1331 { 0x00000000, 0x00000000, 0x00000000, 0x00010000 }, /* SPEFSCR_REGS */ \
7d5175e1 1332 { 0xffffffff, 0xffffffff, 0x00000008, 0x00020000 }, /* NON_SPECIAL_REGS */ \
0ac081f6
AH		 1333 { 0x00000000, 0x00000000, 0x00000001, 0x00000000 }, /* MQ_REGS */ \
1334 { 0x00000000, 0x00000000, 0x00000002, 0x00000000 }, /* LINK_REGS */ \
1335 { 0x00000000, 0x00000000, 0x00000004, 0x00000000 }, /* CTR_REGS */ \
1336 { 0x00000000, 0x00000000, 0x00000006, 0x00000000 }, /* LINK_OR_CTR_REGS */ \
a004eb82 1337 { 0x00000000, 0x00000000, 0x00000007, 0x00002000 }, /* SPECIAL_REGS */ \
7d5175e1 1338 { 0xffffffff, 0x00000000, 0x0000000f, 0x00022000 }, /* SPEC_OR_GEN_REGS */ \
0ac081f6
AH		 1339 { 0x00000000, 0x00000000, 0x00000010, 0x00000000 }, /* CR0_REGS */ \
1340 { 0x00000000, 0x00000000, 0x00000ff0, 0x00000000 }, /* CR_REGS */ \
e3604432 1341 { 0xffffffff, 0x00000000, 0x0000efff, 0x00020000 }, /* NON_FLOAT_REGS */ \
f6b5d695 1342 { 0x00000000, 0x00000000, 0x00001000, 0x00000000 }, /* CA_REGS */ \
7d5175e1 1343 { 0xffffffff, 0xffffffff, 0xffffffff, 0x0003ffff } /* ALL_REGS */ \
ebedb4dd 1344}
f045b2c9 1345
058e97ec
VM		 1346/* The following macro defines cover classes for Integrated Register
1347 Allocator. Cover classes is a set of non-intersected register
1348 classes covering all hard registers used for register allocation
1349 purpose. Any move between two registers of a cover class should be
1350 cheaper than load or store of the registers. The macro value is
1351 array of register classes with LIM_REG_CLASSES used as the end
a72c65c7 1352 marker.
058e97ec 1353
a72c65c7
MM		 1354 We need two IRA_COVER_CLASSES, one for pre-VSX, and the other for VSX to
1355 account for the Altivec and Floating registers being subsets of the VSX
1356 register set. */
1357
1358#define IRA_COVER_CLASSES_PRE_VSX \
058e97ec 1359{ \
a72c65c7
MM		 1360 GENERAL_REGS, SPECIAL_REGS, FLOAT_REGS, ALTIVEC_REGS, /* VSX_REGS, */ \
1361 /* VRSAVE_REGS,*/ VSCR_REGS, SPE_ACC_REGS, SPEFSCR_REGS, \
1362 /* MQ_REGS, LINK_REGS, CTR_REGS, */ \
f6b5d695 1363 CR_REGS, CA_REGS, LIM_REG_CLASSES \
a72c65c7
MM		 1364}
1365
1366#define IRA_COVER_CLASSES_VSX \
1367{ \
1368 GENERAL_REGS, SPECIAL_REGS, /* FLOAT_REGS, ALTIVEC_REGS, */ VSX_REGS, \
1369 /* VRSAVE_REGS,*/ VSCR_REGS, SPE_ACC_REGS, SPEFSCR_REGS, \
058e97ec 1370 /* MQ_REGS, LINK_REGS, CTR_REGS, */ \
f6b5d695 1371 CR_REGS, CA_REGS, LIM_REG_CLASSES \
058e97ec
VM		 1372}
1373
f045b2c9
RS		 1374/* The same information, inverted:
1375 Return the class number of the smallest class containing
1376 reg number REGNO. This could be a conditional expression
1377 or could index an array. */
1378
cacf1ca8
MM		 1379extern enum reg_class rs6000_regno_regclass[FIRST_PSEUDO_REGISTER];
1380
1381#if ENABLE_CHECKING
1382#define REGNO_REG_CLASS(REGNO) \
1383 (gcc_assert (IN_RANGE ((REGNO), 0, FIRST_PSEUDO_REGISTER-1)), \
1384 rs6000_regno_regclass[(REGNO)])
1385
1386#else
1387#define REGNO_REG_CLASS(REGNO) rs6000_regno_regclass[(REGNO)]
1388#endif
1389
a72c65c7
MM		 1390/* Register classes for various constraints that are based on the target
1391 switches. */
1392enum r6000_reg_class_enum {
1393 RS6000_CONSTRAINT_d, /* fpr registers for double values */
1394 RS6000_CONSTRAINT_f, /* fpr registers for single values */
1395 RS6000_CONSTRAINT_v, /* Altivec registers */
1396 RS6000_CONSTRAINT_wa, /* Any VSX register */
1397 RS6000_CONSTRAINT_wd, /* VSX register for V2DF */
1398 RS6000_CONSTRAINT_wf, /* VSX register for V4SF */
1399 RS6000_CONSTRAINT_ws, /* VSX register for DF */
1400 RS6000_CONSTRAINT_MAX
1401};
1402
1403extern enum reg_class rs6000_constraints[RS6000_CONSTRAINT_MAX];
f045b2c9
RS		 1404
1405/* The class value for index registers, and the one for base regs. */
1406#define INDEX_REG_CLASS GENERAL_REGS
1407#define BASE_REG_CLASS BASE_REGS
1408
cacf1ca8
MM		 1409/* Return whether a given register class can hold VSX objects. */
1410#define VSX_REG_CLASS_P(CLASS) \
1411 ((CLASS) == VSX_REGS || (CLASS) == FLOAT_REGS || (CLASS) == ALTIVEC_REGS)
1412
f045b2c9
RS		 1413/* Given an rtx X being reloaded into a reg required to be
1414 in class CLASS, return the class of reg to actually use.
1415 In general this is just CLASS; but on some machines
c81bebd7 1416 in some cases it is preferable to use a more restrictive class.
f045b2c9
RS		 1417
1418 On the RS/6000, we have to return NO_REGS when we want to reload a
f676971a 1419 floating-point CONST_DOUBLE to force it to be copied to memory.
1e66d555
GK		 1420
1421 We also don't want to reload integer values into floating-point
1422 registers if we can at all help it. In fact, this can
37409796 1423 cause reload to die, if it tries to generate a reload of CTR
1e66d555
GK		 1424 into a FP register and discovers it doesn't have the memory location
1425 required.
1426
1427 ??? Would it be a good idea to have reload do the converse, that is
1428 try to reload floating modes into FP registers if possible?
1429 */
f045b2c9 1430
802a0058 1431#define PREFERRED_RELOAD_CLASS(X,CLASS) \
8beb65e3 1432 rs6000_preferred_reload_class_ptr (X, CLASS)
c81bebd7 1433
f045b2c9
RS		 1434/* Return the register class of a scratch register needed to copy IN into
1435 or out of a register in CLASS in MODE. If it can be done directly,
1436 NO_REGS is returned. */
1437
1438#define SECONDARY_RELOAD_CLASS(CLASS,MODE,IN) \
8beb65e3 1439 rs6000_secondary_reload_class_ptr (CLASS, MODE, IN)
f045b2c9 1440
0ac081f6 1441/* If we are copying between FP or AltiVec registers and anything
44cd321e
PS		 1442 else, we need a memory location. The exception is when we are
1443 targeting ppc64 and the move to/from fpr to gpr instructions
1444 are available.*/
1445
1446#define SECONDARY_MEMORY_NEEDED(CLASS1,CLASS2,MODE) \
8beb65e3 1447 rs6000_secondary_memory_needed_ptr (CLASS1, CLASS2, MODE)
7ea555a4 1448
e41b2a33
PB		 1449/* For cpus that cannot load/store SDmode values from the 64-bit
1450 FP registers without using a full 64-bit load/store, we need
1451 to allocate a full 64-bit stack slot for them. */
1452
1453#define SECONDARY_MEMORY_NEEDED_RTX(MODE) \
1454 rs6000_secondary_memory_needed_rtx (MODE)
1455
f045b2c9
RS		 1456/* Return the maximum number of consecutive registers
1457 needed to represent mode MODE in a register of class CLASS.
1458
cacf1ca8
MM		 1459 On RS/6000, this is the size of MODE in words, except in the FP regs, where
1460 a single reg is enough for two words, unless we have VSX, where the FP
1461 registers can hold 128 bits. */
1462#define CLASS_MAX_NREGS(CLASS, MODE) rs6000_class_max_nregs[(MODE)][(CLASS)]
580d3230 1463
ca0e79d9
AM		 1464/* Return nonzero if for CLASS a mode change from FROM to TO is invalid. */
1465
1466#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
8beb65e3 1467 rs6000_cannot_change_mode_class_ptr (FROM, TO, CLASS)
02188693 1468
f045b2c9
RS		 1469/* Stack layout; function entry, exit and calling. */
1470
6b67933e
RK		 1471/* Enumeration to give which calling sequence to use. */
1472enum rs6000_abi {
1473 ABI_NONE,
1474 ABI_AIX, /* IBM's AIX */
b6c9286a 1475 ABI_V4, /* System V.4/eabi */
ee890fe2 1476 ABI_DARWIN /* Apple's Darwin (OS X kernel) */
6b67933e
RK		 1477};
1478
b6c9286a
MM		 1479extern enum rs6000_abi rs6000_current_abi; /* available for use by subtarget */
1480
f045b2c9
RS		 1481/* Define this if pushing a word on the stack
1482 makes the stack pointer a smaller address. */
1483#define STACK_GROWS_DOWNWARD
1484
327e5343
FJ		 1485/* Offsets recorded in opcodes are a multiple of this alignment factor. */
1486#define DWARF_CIE_DATA_ALIGNMENT (-((int) (TARGET_32BIT ? 4 : 8)))
1487
a4d05547 1488/* Define this to nonzero if the nominal address of the stack frame
f045b2c9
RS		 1489 is at the high-address end of the local variables;
1490 that is, each additional local variable allocated
1491 goes at a more negative offset in the frame.
1492
1493 On the RS/6000, we grow upwards, from the area after the outgoing
1494 arguments. */
3aebbe5f 1495#define FRAME_GROWS_DOWNWARD (flag_stack_protect != 0)
f045b2c9 1496
4697a36c 1497/* Size of the outgoing register save area */
9ebbca7d 1498#define RS6000_REG_SAVE ((DEFAULT_ABI == ABI_AIX \
ee890fe2 1499 || DEFAULT_ABI == ABI_DARWIN) \
9ebbca7d
GK		 1500 ? (TARGET_64BIT ? 64 : 32) \
1501 : 0)
4697a36c
MM		 1502
1503/* Size of the fixed area on the stack */
9ebbca7d 1504#define RS6000_SAVE_AREA \
50d440bc 1505 (((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) ? 24 : 8) \
9ebbca7d 1506 << (TARGET_64BIT ? 1 : 0))
4697a36c 1507
97f6e72f
DE		 1508/* MEM representing address to save the TOC register */
1509#define RS6000_SAVE_TOC gen_rtx_MEM (Pmode, \
1510 plus_constant (stack_pointer_rtx, \
1511 (TARGET_32BIT ? 20 : 40)))
b6c9286a 1512
4697a36c 1513/* Align an address */
ed33106f 1514#define RS6000_ALIGN(n,a) (((n) + (a) - 1) & ~((a) - 1))
4697a36c 1515
f045b2c9
RS		 1516/* Offset within stack frame to start allocating local variables at.
1517 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1518 first local allocated. Otherwise, it is the offset to the BEGINNING
c81bebd7 1519 of the first local allocated.
f045b2c9
RS		 1520
1521 On the RS/6000, the frame pointer is the same as the stack pointer,
1522 except for dynamic allocations. So we start after the fixed area and
1523 outgoing parameter area. */
1524
802a0058 1525#define STARTING_FRAME_OFFSET \
7d5175e1
JJ		 1526 (FRAME_GROWS_DOWNWARD \
1527 ? 0 \
cacf1ca8
MM		 1528 : (RS6000_ALIGN (crtl->outgoing_args_size, \
1529 (TARGET_ALTIVEC || TARGET_VSX) ? 16 : 8) \
7d5175e1 1530 + RS6000_SAVE_AREA))
802a0058
MM		 1531
1532/* Offset from the stack pointer register to an item dynamically
1533 allocated on the stack, e.g., by `alloca'.
1534
1535 The default value for this macro is `STACK_POINTER_OFFSET' plus the
1536 length of the outgoing arguments. The default is correct for most
1537 machines. See `function.c' for details. */
1538#define STACK_DYNAMIC_OFFSET(FUNDECL) \
cacf1ca8
MM		 1539 (RS6000_ALIGN (crtl->outgoing_args_size, \
1540 (TARGET_ALTIVEC || TARGET_VSX) ? 16 : 8) \
802a0058 1541 + (STACK_POINTER_OFFSET))
f045b2c9
RS		 1542
1543/* If we generate an insn to push BYTES bytes,
1544 this says how many the stack pointer really advances by.
1545 On RS/6000, don't define this because there are no push insns. */
1546/* #define PUSH_ROUNDING(BYTES) */
1547
1548/* Offset of first parameter from the argument pointer register value.
1549 On the RS/6000, we define the argument pointer to the start of the fixed
1550 area. */
4697a36c 1551#define FIRST_PARM_OFFSET(FNDECL) RS6000_SAVE_AREA
f045b2c9 1552
62153b61
JM		 1553/* Offset from the argument pointer register value to the top of
1554 stack. This is different from FIRST_PARM_OFFSET because of the
1555 register save area. */
1556#define ARG_POINTER_CFA_OFFSET(FNDECL) 0
1557
f045b2c9
RS		 1558/* Define this if stack space is still allocated for a parameter passed
1559 in a register. The value is the number of bytes allocated to this
1560 area. */
4697a36c 1561#define REG_PARM_STACK_SPACE(FNDECL) RS6000_REG_SAVE
f045b2c9
RS		 1562
1563/* Define this if the above stack space is to be considered part of the
1564 space allocated by the caller. */
81464b2c 1565#define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
f045b2c9
RS		 1566
1567/* This is the difference between the logical top of stack and the actual sp.
1568
82e41834 1569 For the RS/6000, sp points past the fixed area. */
4697a36c 1570#define STACK_POINTER_OFFSET RS6000_SAVE_AREA
f045b2c9
RS		 1571
1572/* Define this if the maximum size of all the outgoing args is to be
1573 accumulated and pushed during the prologue. The amount can be
38173d38 1574 found in the variable crtl->outgoing_args_size. */
f73ad30e 1575#define ACCUMULATE_OUTGOING_ARGS 1
f045b2c9 1576
f045b2c9
RS		 1577/* Define how to find the value returned by a library function
1578 assuming the value has mode MODE. */
1579
ded9bf77 1580#define LIBCALL_VALUE(MODE) rs6000_libcall_value ((MODE))
f045b2c9 1581
6fa3f289
ZW		 1582/* DRAFT_V4_STRUCT_RET defaults off. */
1583#define DRAFT_V4_STRUCT_RET 0
f607bc57 1584
bd5bd7ac 1585/* Let TARGET_RETURN_IN_MEMORY control what happens. */
f607bc57 1586#define DEFAULT_PCC_STRUCT_RETURN 0
f045b2c9 1587
a260abc9 1588/* Mode of stack savearea.
dfdfa60f
DE		 1589 FUNCTION is VOIDmode because calling convention maintains SP.
1590 BLOCK needs Pmode for SP.
a260abc9
DE		 1591 NONLOCAL needs twice Pmode to maintain both backchain and SP. */
1592#define STACK_SAVEAREA_MODE(LEVEL) \
dfdfa60f
DE		 1593 (LEVEL == SAVE_FUNCTION ? VOIDmode \
1594 : LEVEL == SAVE_NONLOCAL ? (TARGET_32BIT ? DImode : TImode) : Pmode)
a260abc9 1595
4697a36c
MM		 1596/* Minimum and maximum general purpose registers used to hold arguments. */
1597#define GP_ARG_MIN_REG 3
1598#define GP_ARG_MAX_REG 10
1599#define GP_ARG_NUM_REG (GP_ARG_MAX_REG - GP_ARG_MIN_REG + 1)
1600
1601/* Minimum and maximum floating point registers used to hold arguments. */
1602#define FP_ARG_MIN_REG 33
7509c759
MM		 1603#define FP_ARG_AIX_MAX_REG 45
1604#define FP_ARG_V4_MAX_REG 40
9ebbca7d 1605#define FP_ARG_MAX_REG ((DEFAULT_ABI == ABI_AIX \
ee890fe2 1606 || DEFAULT_ABI == ABI_DARWIN) \
9ebbca7d 1607 ? FP_ARG_AIX_MAX_REG : FP_ARG_V4_MAX_REG)
4697a36c
MM		 1608#define FP_ARG_NUM_REG (FP_ARG_MAX_REG - FP_ARG_MIN_REG + 1)
1609
0ac081f6
AH		 1610/* Minimum and maximum AltiVec registers used to hold arguments. */
1611#define ALTIVEC_ARG_MIN_REG (FIRST_ALTIVEC_REGNO + 2)
1612#define ALTIVEC_ARG_MAX_REG (ALTIVEC_ARG_MIN_REG + 11)
1613#define ALTIVEC_ARG_NUM_REG (ALTIVEC_ARG_MAX_REG - ALTIVEC_ARG_MIN_REG + 1)
1614
4697a36c
MM		 1615/* Return registers */
1616#define GP_ARG_RETURN GP_ARG_MIN_REG
1617#define FP_ARG_RETURN FP_ARG_MIN_REG
0ac081f6 1618#define ALTIVEC_ARG_RETURN (FIRST_ALTIVEC_REGNO + 2)
4697a36c 1619
7509c759 1620/* Flags for the call/call_value rtl operations set up by function_arg */
6a4cee5f 1621#define CALL_NORMAL 0x00000000 /* no special processing */
9ebbca7d 1622/* Bits in 0x00000001 are unused. */
6a4cee5f
MM		 1623#define CALL_V4_CLEAR_FP_ARGS 0x00000002 /* V.4, no FP args passed */
1624#define CALL_V4_SET_FP_ARGS 0x00000004 /* V.4, FP args were passed */
1625#define CALL_LONG 0x00000008 /* always call indirect */
b9599e46 1626#define CALL_LIBCALL 0x00000010 /* libcall */
7509c759 1627
f57fe068
AM		 1628/* We don't have prologue and epilogue functions to save/restore
1629 everything for most ABIs. */
1630#define WORLD_SAVE_P(INFO) 0
1631
f045b2c9
RS		 1632/* 1 if N is a possible register number for a function value
1633 as seen by the caller.
1634
0ac081f6 1635 On RS/6000, this is r3, fp1, and v2 (for AltiVec). */
e87a88d3
AM		 1636#define FUNCTION_VALUE_REGNO_P(N) \
1637 ((N) == GP_ARG_RETURN \
b2df7d08 1638 || ((N) == FP_ARG_RETURN && TARGET_HARD_FLOAT && TARGET_FPRS) \
44688022 1639 || ((N) == ALTIVEC_ARG_RETURN && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI))
f045b2c9
RS		 1640
1641/* 1 if N is a possible register number for function argument passing.
0ac081f6
AH		 1642 On RS/6000, these are r3-r10 and fp1-fp13.
1643 On AltiVec, v2 - v13 are used for passing vectors. */
4697a36c 1644#define FUNCTION_ARG_REGNO_P(N) \
e87a88d3
AM		 1645 ((unsigned) (N) - GP_ARG_MIN_REG < GP_ARG_NUM_REG \
1646 || ((unsigned) (N) - ALTIVEC_ARG_MIN_REG < ALTIVEC_ARG_NUM_REG \
44688022 1647 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI) \
e87a88d3 1648 || ((unsigned) (N) - FP_ARG_MIN_REG < FP_ARG_NUM_REG \
b2df7d08 1649 && TARGET_HARD_FLOAT && TARGET_FPRS))
f045b2c9
RS		 1650\f
1651/* Define a data type for recording info about an argument list
1652 during the scan of that argument list. This data type should
1653 hold all necessary information about the function itself
1654 and about the args processed so far, enough to enable macros
1655 such as FUNCTION_ARG to determine where the next arg should go.
1656
1657 On the RS/6000, this is a structure. The first element is the number of
1658 total argument words, the second is used to store the next
1659 floating-point register number, and the third says how many more args we
4697a36c
MM		 1660 have prototype types for.
1661
4cc833b7 1662 For ABI_V4, we treat these slightly differently -- `sysv_gregno' is
07488f32 1663 the next available GP register, `fregno' is the next available FP
4cc833b7
RH		 1664 register, and `words' is the number of words used on the stack.
1665
bd227acc 1666 The varargs/stdarg support requires that this structure's size
4cc833b7 1667 be a multiple of sizeof(int). */
4697a36c
MM		 1668
1669typedef struct rs6000_args
1670{
4cc833b7 1671 int words; /* # words used for passing GP registers */
6a4cee5f 1672 int fregno; /* next available FP register */
0ac081f6 1673 int vregno; /* next available AltiVec register */
6a4cee5f 1674 int nargs_prototype; /* # args left in the current prototype */
6a4cee5f 1675 int prototype; /* Whether a prototype was defined */
a6c9bed4 1676 int stdarg; /* Whether function is a stdarg function. */
6a4cee5f 1677 int call_cookie; /* Do special things for this call */
4cc833b7 1678 int sysv_gregno; /* next available GP register */
0b5383eb
DJ		 1679 int intoffset; /* running offset in struct (darwin64) */
1680 int use_stack; /* any part of struct on stack (darwin64) */
a9ab25e2
IS		 1681 int floats_in_gpr; /* count of SFmode floats taking up
1682 GPR space (darwin64) */
0b5383eb 1683 int named; /* false for varargs params */
4697a36c 1684} CUMULATIVE_ARGS;
f045b2c9 1685
f045b2c9
RS		 1686/* Initialize a variable CUM of type CUMULATIVE_ARGS
1687 for a call to a function whose data type is FNTYPE.
1688 For a library call, FNTYPE is 0. */
1689
0f6937fe
AM		 1690#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
1691 init_cumulative_args (&CUM, FNTYPE, LIBNAME, FALSE, FALSE, N_NAMED_ARGS)
f045b2c9
RS		 1692
1693/* Similar, but when scanning the definition of a procedure. We always
1694 set NARGS_PROTOTYPE large so we never return an EXPR_LIST. */
1695
0f6937fe
AM		 1696#define INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME) \
1697 init_cumulative_args (&CUM, FNTYPE, LIBNAME, TRUE, FALSE, 1000)
b9599e46
FS		 1698
1699/* Like INIT_CUMULATIVE_ARGS' but only used for outgoing libcalls. */
1700
1701#define INIT_CUMULATIVE_LIBCALL_ARGS(CUM, MODE, LIBNAME) \
0f6937fe 1702 init_cumulative_args (&CUM, NULL_TREE, LIBNAME, FALSE, TRUE, 0)
f045b2c9 1703
c229cba9
DE		 1704/* If defined, a C expression which determines whether, and in which
1705 direction, to pad out an argument with extra space. The value
1706 should be of type `enum direction': either `upward' to pad above
1707 the argument, `downward' to pad below, or `none' to inhibit
1708 padding. */
1709
9ebbca7d 1710#define FUNCTION_ARG_PADDING(MODE, TYPE) function_arg_padding (MODE, TYPE)
c229cba9 1711
b6c9286a 1712/* If defined, a C expression that gives the alignment boundary, in bits,
c81bebd7 1713 of an argument with the specified mode and type. If it is not defined,
b6c9286a
MM		 1714 PARM_BOUNDARY is used for all arguments. */
1715
1716#define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
1717 function_arg_boundary (MODE, TYPE)
1718
6e985040
AM		 1719#define PAD_VARARGS_DOWN \
1720 (FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward)
2a55fd42 1721
f045b2c9 1722/* Output assembler code to FILE to increment profiler label # LABELNO
58a39e45 1723 for profiling a function entry. */
f045b2c9
RS		 1724
1725#define FUNCTION_PROFILER(FILE, LABELNO) \
58a39e45 1726 output_function_profiler ((FILE), (LABELNO));
f045b2c9
RS		 1727
1728/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1729 the stack pointer does not matter. No definition is equivalent to
1730 always zero.
1731
a0ab749a 1732 On the RS/6000, this is nonzero because we can restore the stack from
f045b2c9
RS		 1733 its backpointer, which we maintain. */
1734#define EXIT_IGNORE_STACK 1
1735
a701949a
FS		 1736/* Define this macro as a C expression that is nonzero for registers
1737 that are used by the epilogue or the return' pattern. The stack
1738 and frame pointer registers are already be assumed to be used as
1739 needed. */
1740
83720594 1741#define EPILOGUE_USES(REGNO) \
1de43f85 1742 ((reload_completed && (REGNO) == LR_REGNO) \
b1765bde 1743 || (TARGET_ALTIVEC && (REGNO) == VRSAVE_REGNO) \
cacf1ca8 1744 || (crtl->calls_eh_return \
3553b09d 1745 && TARGET_AIX \
ff3867ae 1746 && (REGNO) == 2))
2bfcf297 1747
f045b2c9 1748\f
f045b2c9
RS		 1749/* Length in units of the trampoline for entering a nested function. */
1750
b6c9286a 1751#define TRAMPOLINE_SIZE rs6000_trampoline_size ()
f045b2c9 1752\f
f33985c6
MS		 1753/* Definitions for __builtin_return_address and __builtin_frame_address.
1754 __builtin_return_address (0) should give link register (65), enable
82e41834 1755 this. */
f33985c6
MS		 1756/* This should be uncommented, so that the link register is used, but
1757 currently this would result in unmatched insns and spilling fixed
1758 registers so we'll leave it for another day. When these problems are
1759 taken care of one additional fetch will be necessary in RETURN_ADDR_RTX.
1760 (mrs) */
1761/* #define RETURN_ADDR_IN_PREVIOUS_FRAME */
f09d4c33 1762
b6c9286a
MM		 1763/* Number of bytes into the frame return addresses can be found. See
1764 rs6000_stack_info in rs6000.c for more information on how the different
1765 abi's store the return address. */
1766#define RETURN_ADDRESS_OFFSET \
1767 ((DEFAULT_ABI == ABI_AIX \
50d440bc 1768 || DEFAULT_ABI == ABI_DARWIN) ? (TARGET_32BIT ? 8 : 16) : \
3b370352 1769 (DEFAULT_ABI == ABI_V4) ? 4 : \
c4636dd1 1770 (internal_error ("RETURN_ADDRESS_OFFSET not supported"), 0))
f09d4c33 1771
f33985c6
MS		 1772/* The current return address is in link register (65). The return address
1773 of anything farther back is accessed normally at an offset of 8 from the
1774 frame pointer. */
71f123ca
FS		 1775#define RETURN_ADDR_RTX(COUNT, FRAME) \
1776 (rs6000_return_addr (COUNT, FRAME))
1777
f33985c6 1778\f
f045b2c9
RS		 1779/* Definitions for register eliminations.
1780
1781 We have two registers that can be eliminated on the RS/6000. First, the
1782 frame pointer register can often be eliminated in favor of the stack
1783 pointer register. Secondly, the argument pointer register can always be
642a35f1
JW		 1784 eliminated; it is replaced with either the stack or frame pointer.
1785
1786 In addition, we use the elimination mechanism to see if r30 is needed
1787 Initially we assume that it isn't. If it is, we spill it. This is done
1788 by making it an eliminable register. We replace it with itself so that
1789 if it isn't needed, then existing uses won't be modified. */
f045b2c9
RS		 1790
1791/* This is an array of structures. Each structure initializes one pair
1792 of eliminable registers. The "from" register number is given first,
1793 followed by "to". Eliminations of the same "from" register are listed
1794 in order of preference. */
7d5175e1
JJ		 1795#define ELIMINABLE_REGS \
1796{{ HARD_FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1797 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1798 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1799 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1800 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
97b23853 1801 { RS6000_PIC_OFFSET_TABLE_REGNUM, RS6000_PIC_OFFSET_TABLE_REGNUM } }
f045b2c9 1802
f045b2c9
RS		 1803/* Define the offset between two registers, one to be eliminated, and the other
1804 its replacement, at the start of a routine. */
d1d0c603
JJ		 1805#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1806 ((OFFSET) = rs6000_initial_elimination_offset(FROM, TO))
f045b2c9
RS		 1807\f
1808/* Addressing modes, and classification of registers for them. */
1809
940da324
JL		 1810#define HAVE_PRE_DECREMENT 1
1811#define HAVE_PRE_INCREMENT 1
6fb5fa3c
DB		 1812#define HAVE_PRE_MODIFY_DISP 1
1813#define HAVE_PRE_MODIFY_REG 1
f045b2c9
RS		 1814
1815/* Macros to check register numbers against specific register classes. */
1816
1817/* These assume that REGNO is a hard or pseudo reg number.
1818 They give nonzero only if REGNO is a hard reg of the suitable class
1819 or a pseudo reg currently allocated to a suitable hard reg.
1820 Since they use reg_renumber, they are safe only once reg_renumber
1821 has been allocated, which happens in local-alloc.c. */
1822
1823#define REGNO_OK_FOR_INDEX_P(REGNO) \
1824((REGNO) < FIRST_PSEUDO_REGISTER \
1825 ? (REGNO) <= 31 || (REGNO) == 67 \
7d5175e1 1826 || (REGNO) == FRAME_POINTER_REGNUM \
f045b2c9 1827 : (reg_renumber[REGNO] >= 0 \
7d5175e1
JJ		 1828 && (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67 \
1829 || reg_renumber[REGNO] == FRAME_POINTER_REGNUM)))
f045b2c9
RS		 1830
1831#define REGNO_OK_FOR_BASE_P(REGNO) \
1832((REGNO) < FIRST_PSEUDO_REGISTER \
1833 ? ((REGNO) > 0 && (REGNO) <= 31) || (REGNO) == 67 \
7d5175e1 1834 || (REGNO) == FRAME_POINTER_REGNUM \
f045b2c9 1835 : (reg_renumber[REGNO] > 0 \
7d5175e1
JJ		 1836 && (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67 \
1837 || reg_renumber[REGNO] == FRAME_POINTER_REGNUM)))
c6c3dba9
PB		 1838
1839/* Nonzero if X is a hard reg that can be used as an index
1840 or if it is a pseudo reg in the non-strict case. */
1841#define INT_REG_OK_FOR_INDEX_P(X, STRICT) \
1842 ((!(STRICT) && REGNO (X) >= FIRST_PSEUDO_REGISTER) \
1843 || REGNO_OK_FOR_INDEX_P (REGNO (X)))
1844
1845/* Nonzero if X is a hard reg that can be used as a base reg
1846 or if it is a pseudo reg in the non-strict case. */
1847#define INT_REG_OK_FOR_BASE_P(X, STRICT) \
1848 ((!(STRICT) && REGNO (X) >= FIRST_PSEUDO_REGISTER) \
1849 || REGNO_OK_FOR_BASE_P (REGNO (X)))
1850
f045b2c9
RS		 1851\f
1852/* Maximum number of registers that can appear in a valid memory address. */
1853
1854#define MAX_REGS_PER_ADDRESS 2
1855
1856/* Recognize any constant value that is a valid address. */
1857
6eff269e
BK		 1858#define CONSTANT_ADDRESS_P(X) \
1859 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
1860 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \
1861 || GET_CODE (X) == HIGH)
f045b2c9
RS		 1862
1863/* Nonzero if the constant value X is a legitimate general operand.
1864 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
1865
1866 On the RS/6000, all integer constants are acceptable, most won't be valid
1867 for particular insns, though. Only easy FP constants are
1868 acceptable. */
1869
1870#define LEGITIMATE_CONSTANT_P(X) \
49a2166f
AH		 1871 (((GET_CODE (X) != CONST_DOUBLE \
1872 && GET_CODE (X) != CONST_VECTOR) \
1873 || GET_MODE (X) == VOIDmode \
c4501e62 1874 || (TARGET_POWERPC64 && GET_MODE (X) == DImode) \
49a2166f
AH		 1875 || easy_fp_constant (X, GET_MODE (X)) \
1876 || easy_vector_constant (X, GET_MODE (X))) \
c4501e62 1877 && !rs6000_tls_referenced_p (X))
f045b2c9 1878
48d72335 1879#define EASY_VECTOR_15(n) ((n) >= -16 && (n) <= 15)
66180ff3 1880#define EASY_VECTOR_15_ADD_SELF(n) (!EASY_VECTOR_15((n)) \
76492753
PB		 1881 && EASY_VECTOR_15((n) >> 1) \
1882 && ((n) & 1) == 0)
48d72335 1883
29e6733c
MM		 1884#define EASY_VECTOR_MSB(n,mode) \
1885 (((unsigned HOST_WIDE_INT)n) == \
1886 ((((unsigned HOST_WIDE_INT)GET_MODE_MASK (mode)) + 1) >> 1))
1887
f045b2c9 1888\f
a260abc9
DE		 1889/* Try a machine-dependent way of reloading an illegitimate address
1890 operand. If we find one, push the reload and jump to WIN. This
1891 macro is used in only one place: `find_reloads_address' in reload.c.
1892
f676971a 1893 Implemented on rs6000 by rs6000_legitimize_reload_address.
24ea750e 1894 Note that (X) is evaluated twice; this is safe in current usage. */
f676971a 1895
a9098fd0
GK		 1896#define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
1897do { \
24ea750e 1898 int win; \
8beb65e3 1899 (X) = rs6000_legitimize_reload_address_ptr ((X), (MODE), (OPNUM), \
24ea750e
DJ		 1900 (int)(TYPE), (IND_LEVELS), &win); \
1901 if ( win ) \
1902 goto WIN; \
a260abc9
DE		 1903} while (0)
1904
944258eb 1905#define FIND_BASE_TERM rs6000_find_base_term
766a866c
MM		 1906\f
1907/* The register number of the register used to address a table of
1908 static data addresses in memory. In some cases this register is
1909 defined by a processor's "application binary interface" (ABI).
1910 When this macro is defined, RTL is generated for this register
1911 once, as with the stack pointer and frame pointer registers. If
1912 this macro is not defined, it is up to the machine-dependent files
1913 to allocate such a register (if necessary). */
1914
1db02437
FS		 1915#define RS6000_PIC_OFFSET_TABLE_REGNUM 30
1916#define PIC_OFFSET_TABLE_REGNUM (flag_pic ? RS6000_PIC_OFFSET_TABLE_REGNUM : INVALID_REGNUM)
766a866c 1917
97b23853 1918#define TOC_REGISTER (TARGET_MINIMAL_TOC ? RS6000_PIC_OFFSET_TABLE_REGNUM : 2)
9ebbca7d 1919
766a866c
MM		 1920/* Define this macro if the register defined by
1921 `PIC_OFFSET_TABLE_REGNUM' is clobbered by calls. Do not define
089a05b8 1922 this macro if `PIC_OFFSET_TABLE_REGNUM' is not defined. */
766a866c
MM		 1923
1924/* #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED */
1925
766a866c
MM		 1926/* A C expression that is nonzero if X is a legitimate immediate
1927 operand on the target machine when generating position independent
1928 code. You can assume that X satisfies `CONSTANT_P', so you need
1929 not check this. You can also assume FLAG_PIC is true, so you need
1930 not check it either. You need not define this macro if all
1931 constants (including `SYMBOL_REF') can be immediate operands when
1932 generating position independent code. */
1933
1934/* #define LEGITIMATE_PIC_OPERAND_P (X) */
f045b2c9
RS		 1935\f
1936/* Define this if some processing needs to be done immediately before
4255474b 1937 emitting code for an insn. */
f045b2c9 1938
c921bad8
AP		 1939#define FINAL_PRESCAN_INSN(INSN,OPERANDS,NOPERANDS) \
1940 rs6000_final_prescan_insn (INSN, OPERANDS, NOPERANDS)
f045b2c9
RS		 1941
1942/* Specify the machine mode that this machine uses
1943 for the index in the tablejump instruction. */
e1565e65 1944#define CASE_VECTOR_MODE SImode
f045b2c9 1945
18543a22
ILT		 1946/* Define as C expression which evaluates to nonzero if the tablejump
1947 instruction expects the table to contain offsets from the address of the
1948 table.
82e41834 1949 Do not define this if the table should contain absolute addresses. */
18543a22 1950#define CASE_VECTOR_PC_RELATIVE 1
f045b2c9 1951
f045b2c9
RS		 1952/* Define this as 1 if `char' should by default be signed; else as 0. */
1953#define DEFAULT_SIGNED_CHAR 0
1954
1955/* This flag, if defined, says the same insns that convert to a signed fixnum
1956 also convert validly to an unsigned one. */
1957
1958/* #define FIXUNS_TRUNC_LIKE_FIX_TRUNC */
1959
c1618c0c
DE		 1960/* An integer expression for the size in bits of the largest integer machine
1961 mode that should actually be used. */
1962
1963/* Allow pairs of registers to be used, which is the intent of the default. */
1964#define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_POWERPC64 ? TImode : DImode)
1965
f045b2c9
RS		 1966/* Max number of bytes we can move from memory to memory
1967 in one reasonably fast instruction. */
2f3e5814 1968#define MOVE_MAX (! TARGET_POWERPC64 ? 4 : 8)
7e69e155 1969#define MAX_MOVE_MAX 8
f045b2c9
RS		 1970
1971/* Nonzero if access to memory by bytes is no faster than for words.
a0ab749a 1972 Also nonzero if doing byte operations (specifically shifts) in registers
f045b2c9
RS		 1973 is undesirable. */
1974#define SLOW_BYTE_ACCESS 1
1975
9a63901f
RK		 1976/* Define if operations between registers always perform the operation
1977 on the full register even if a narrower mode is specified. */
1978#define WORD_REGISTER_OPERATIONS
1979
1980/* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1981 will either zero-extend or sign-extend. The value of this macro should
1982 be the code that says which one of the two operations is implicitly
f822d252 1983 done, UNKNOWN if none. */
9a63901f 1984#define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
225211e2
RK		 1985
1986/* Define if loading short immediate values into registers sign extends. */
1987#define SHORT_IMMEDIATES_SIGN_EXTEND
fdaff8ba 1988\f
f045b2c9
RS		 1989/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1990 is done just by pretending it is already truncated. */
1991#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1992
94993909 1993/* The cntlzw and cntlzd instructions return 32 and 64 for input of zero. */
d865b122 1994#define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
14670a74 1995 ((VALUE) = ((MODE) == SImode ? 32 : 64), 1)
d865b122 1996
94993909 1997/* The CTZ patterns return -1 for input of zero. */
14670a74 1998#define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = -1, 1)
94993909 1999
f045b2c9
RS		 2000/* Specify the machine mode that pointers have.
2001 After generation of rtl, the compiler makes no further distinction
2002 between pointers and any other objects of this machine mode. */
cacf1ca8
MM		 2003extern unsigned rs6000_pmode;
2004#define Pmode ((enum machine_mode)rs6000_pmode)
f045b2c9 2005
a3c9585f 2006/* Supply definition of STACK_SIZE_MODE for allocate_dynamic_stack_space. */
4c81e946
FJ		 2007#define STACK_SIZE_MODE (TARGET_32BIT ? SImode : DImode)
2008
f045b2c9 2009/* Mode of a function address in a call instruction (for indexing purposes).
f045b2c9 2010 Doesn't matter on RS/6000. */
5b71a4e7 2011#define FUNCTION_MODE SImode
f045b2c9
RS		 2012
2013/* Define this if addresses of constant functions
2014 shouldn't be put through pseudo regs where they can be cse'd.
2015 Desirable on machines where ordinary constants are expensive
2016 but a CALL with constant address is cheap. */
2017#define NO_FUNCTION_CSE
2018
d969caf8 2019/* Define this to be nonzero if shift instructions ignore all but the low-order
6febd581
RK		 2020 few bits.
2021
2022 The sle and sre instructions which allow SHIFT_COUNT_TRUNCATED
2023 have been dropped from the PowerPC architecture. */
2024
4697a36c 2025#define SHIFT_COUNT_TRUNCATED (TARGET_POWER ? 1 : 0)
f045b2c9 2026
f045b2c9
RS		 2027/* Adjust the length of an INSN. LENGTH is the currently-computed length and
2028 should be adjusted to reflect any required changes. This macro is used when
2029 there is some systematic length adjustment required that would be difficult
2030 to express in the length attribute. */
2031
2032/* #define ADJUST_INSN_LENGTH(X,LENGTH) */
2033
39a10a29
GK		 2034/* Given a comparison code (EQ, NE, etc.) and the first operand of a
2035 COMPARE, return the mode to be used for the comparison. For
2036 floating-point, CCFPmode should be used. CCUNSmode should be used
2037 for unsigned comparisons. CCEQmode should be used when we are
2038 doing an inequality comparison on the result of a
2039 comparison. CCmode should be used in all other cases. */
c5defebb 2040
b565a316 2041#define SELECT_CC_MODE(OP,X,Y) \
ebb109ad 2042 (SCALAR_FLOAT_MODE_P (GET_MODE (X)) ? CCFPmode \
c5defebb 2043 : (OP) == GTU || (OP) == LTU || (OP) == GEU || (OP) == LEU ? CCUNSmode \
ec8e098d 2044 : (((OP) == EQ || (OP) == NE) && COMPARISON_P (X) \
c5defebb 2045 ? CCEQmode : CCmode))
f045b2c9 2046
b39358e1
GK		 2047/* Can the condition code MODE be safely reversed? This is safe in
2048 all cases on this port, because at present it doesn't use the
2049 trapping FP comparisons (fcmpo). */
2050#define REVERSIBLE_CC_MODE(MODE) 1
2051
2052/* Given a condition code and a mode, return the inverse condition. */
2053#define REVERSE_CONDITION(CODE, MODE) rs6000_reverse_condition (MODE, CODE)
2054
f045b2c9
RS		 2055\f
2056/* Control the assembler format that we output. */
2057
1b279f39
DE		 2058/* A C string constant describing how to begin a comment in the target
2059 assembler language. The compiler assumes that the comment will end at
2060 the end of the line. */
2061#define ASM_COMMENT_START " #"
6b67933e 2062
38c1f2d7
MM		 2063/* Flag to say the TOC is initialized */
2064extern int toc_initialized;
2065
f045b2c9
RS		 2066/* Macro to output a special constant pool entry. Go to WIN if we output
2067 it. Otherwise, it is written the usual way.
2068
2069 On the RS/6000, toc entries are handled this way. */
2070
a9098fd0
GK		 2071#define ASM_OUTPUT_SPECIAL_POOL_ENTRY(FILE, X, MODE, ALIGN, LABELNO, WIN) \
2072{ if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (X, MODE)) \
2073 { \
2074 output_toc (FILE, X, LABELNO, MODE); \
2075 goto WIN; \
2076 } \
f045b2c9
RS		 2077}
2078
ebd97b96
DE		 2079#ifdef HAVE_GAS_WEAK
2080#define RS6000_WEAK 1
2081#else
2082#define RS6000_WEAK 0
2083#endif
290ad355 2084
79c4e63f
AM		 2085#if RS6000_WEAK
2086/* Used in lieu of ASM_WEAKEN_LABEL. */
2087#define ASM_WEAKEN_DECL(FILE, DECL, NAME, VAL) \
2088 do \
2089 { \
2090 fputs ("\t.weak\t", (FILE)); \
85b776df 2091 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
79c4e63f 2092 if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \
85b776df 2093 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \
79c4e63f 2094 { \
cbaaba19
DE		 2095 if (TARGET_XCOFF) \
2096 fputs ("[DS]", (FILE)); \
ca734b39 2097 fputs ("\n\t.weak\t.", (FILE)); \
cbaaba19 2098 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
79c4e63f
AM		 2099 } \
2100 fputc ('\n', (FILE)); \
2101 if (VAL) \
2102 { \
2103 ASM_OUTPUT_DEF ((FILE), (NAME), (VAL)); \
2104 if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \
85b776df 2105 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \
79c4e63f
AM		 2106 { \
2107 fputs ("\t.set\t.", (FILE)); \
cbaaba19 2108 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
79c4e63f 2109 fputs (",.", (FILE)); \
cbaaba19 2110 RS6000_OUTPUT_BASENAME ((FILE), (VAL)); \
79c4e63f
AM		 2111 fputc ('\n', (FILE)); \
2112 } \
2113 } \
2114 } \
2115 while (0)
2116#endif
2117
ff2d10c1
AO		 2118#if HAVE_GAS_WEAKREF
2119#define ASM_OUTPUT_WEAKREF(FILE, DECL, NAME, VALUE) \
2120 do \
2121 { \
2122 fputs ("\t.weakref\t", (FILE)); \
2123 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
2124 fputs (", ", (FILE)); \
2125 RS6000_OUTPUT_BASENAME ((FILE), (VALUE)); \
2126 if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \
2127 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \
2128 { \
2129 fputs ("\n\t.weakref\t.", (FILE)); \
2130 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
2131 fputs (", .", (FILE)); \
2132 RS6000_OUTPUT_BASENAME ((FILE), (VALUE)); \
2133 } \
2134 fputc ('\n', (FILE)); \
2135 } while (0)
2136#endif
2137
79c4e63f
AM		 2138/* This implements the `alias' attribute. */
2139#undef ASM_OUTPUT_DEF_FROM_DECLS
2140#define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL, TARGET) \
2141 do \
2142 { \
2143 const char *alias = XSTR (XEXP (DECL_RTL (DECL), 0), 0); \
2144 const char *name = IDENTIFIER_POINTER (TARGET); \
2145 if (TREE_CODE (DECL) == FUNCTION_DECL \
85b776df 2146 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \
79c4e63f
AM		 2147 { \
2148 if (TREE_PUBLIC (DECL)) \
2149 { \
2150 if (!RS6000_WEAK || !DECL_WEAK (DECL)) \
2151 { \
2152 fputs ("\t.globl\t.", FILE); \
cbaaba19 2153 RS6000_OUTPUT_BASENAME (FILE, alias); \
79c4e63f
AM		 2154 putc ('\n', FILE); \
2155 } \
2156 } \
2157 else if (TARGET_XCOFF) \
2158 { \
2159 fputs ("\t.lglobl\t.", FILE); \
cbaaba19 2160 RS6000_OUTPUT_BASENAME (FILE, alias); \
79c4e63f
AM		 2161 putc ('\n', FILE); \
2162 } \
2163 fputs ("\t.set\t.", FILE); \
cbaaba19 2164 RS6000_OUTPUT_BASENAME (FILE, alias); \
79c4e63f 2165 fputs (",.", FILE); \
cbaaba19 2166 RS6000_OUTPUT_BASENAME (FILE, name); \
79c4e63f
AM		 2167 fputc ('\n', FILE); \
2168 } \
2169 ASM_OUTPUT_DEF (FILE, alias, name); \
2170 } \
2171 while (0)
290ad355 2172
1bc7c5b6
ZW		 2173#define TARGET_ASM_FILE_START rs6000_file_start
2174
f045b2c9
RS		 2175/* Output to assembler file text saying following lines
2176 may contain character constants, extra white space, comments, etc. */
2177
2178#define ASM_APP_ON ""
2179
2180/* Output to assembler file text saying following lines
2181 no longer contain unusual constructs. */
2182
2183#define ASM_APP_OFF ""
2184
f045b2c9
RS		 2185/* How to refer to registers in assembler output.
2186 This sequence is indexed by compiler's hard-register-number (see above). */
2187
82e41834 2188extern char rs6000_reg_names[][8]; /* register names (0 vs. %r0). */
c81bebd7
MM		 2189
2190#define REGISTER_NAMES \
2191{ \
2192 &rs6000_reg_names[ 0][0], /* r0 */ \
2193 &rs6000_reg_names[ 1][0], /* r1 */ \
2194 &rs6000_reg_names[ 2][0], /* r2 */ \
2195 &rs6000_reg_names[ 3][0], /* r3 */ \
2196 &rs6000_reg_names[ 4][0], /* r4 */ \
2197 &rs6000_reg_names[ 5][0], /* r5 */ \
2198 &rs6000_reg_names[ 6][0], /* r6 */ \
2199 &rs6000_reg_names[ 7][0], /* r7 */ \
2200 &rs6000_reg_names[ 8][0], /* r8 */ \
2201 &rs6000_reg_names[ 9][0], /* r9 */ \
2202 &rs6000_reg_names[10][0], /* r10 */ \
2203 &rs6000_reg_names[11][0], /* r11 */ \
2204 &rs6000_reg_names[12][0], /* r12 */ \
2205 &rs6000_reg_names[13][0], /* r13 */ \
2206 &rs6000_reg_names[14][0], /* r14 */ \
2207 &rs6000_reg_names[15][0], /* r15 */ \
2208 &rs6000_reg_names[16][0], /* r16 */ \
2209 &rs6000_reg_names[17][0], /* r17 */ \
2210 &rs6000_reg_names[18][0], /* r18 */ \
2211 &rs6000_reg_names[19][0], /* r19 */ \
2212 &rs6000_reg_names[20][0], /* r20 */ \
2213 &rs6000_reg_names[21][0], /* r21 */ \
2214 &rs6000_reg_names[22][0], /* r22 */ \
2215 &rs6000_reg_names[23][0], /* r23 */ \
2216 &rs6000_reg_names[24][0], /* r24 */ \
2217 &rs6000_reg_names[25][0], /* r25 */ \
2218 &rs6000_reg_names[26][0], /* r26 */ \
2219 &rs6000_reg_names[27][0], /* r27 */ \
2220 &rs6000_reg_names[28][0], /* r28 */ \
2221 &rs6000_reg_names[29][0], /* r29 */ \
2222 &rs6000_reg_names[30][0], /* r30 */ \
2223 &rs6000_reg_names[31][0], /* r31 */ \
2224 \
2225 &rs6000_reg_names[32][0], /* fr0 */ \
2226 &rs6000_reg_names[33][0], /* fr1 */ \
2227 &rs6000_reg_names[34][0], /* fr2 */ \
2228 &rs6000_reg_names[35][0], /* fr3 */ \
2229 &rs6000_reg_names[36][0], /* fr4 */ \
2230 &rs6000_reg_names[37][0], /* fr5 */ \
2231 &rs6000_reg_names[38][0], /* fr6 */ \
2232 &rs6000_reg_names[39][0], /* fr7 */ \
2233 &rs6000_reg_names[40][0], /* fr8 */ \
2234 &rs6000_reg_names[41][0], /* fr9 */ \
2235 &rs6000_reg_names[42][0], /* fr10 */ \
2236 &rs6000_reg_names[43][0], /* fr11 */ \
2237 &rs6000_reg_names[44][0], /* fr12 */ \
2238 &rs6000_reg_names[45][0], /* fr13 */ \
2239 &rs6000_reg_names[46][0], /* fr14 */ \
2240 &rs6000_reg_names[47][0], /* fr15 */ \
2241 &rs6000_reg_names[48][0], /* fr16 */ \
2242 &rs6000_reg_names[49][0], /* fr17 */ \
2243 &rs6000_reg_names[50][0], /* fr18 */ \
2244 &rs6000_reg_names[51][0], /* fr19 */ \
2245 &rs6000_reg_names[52][0], /* fr20 */ \
2246 &rs6000_reg_names[53][0], /* fr21 */ \
2247 &rs6000_reg_names[54][0], /* fr22 */ \
2248 &rs6000_reg_names[55][0], /* fr23 */ \
2249 &rs6000_reg_names[56][0], /* fr24 */ \
2250 &rs6000_reg_names[57][0], /* fr25 */ \
2251 &rs6000_reg_names[58][0], /* fr26 */ \
2252 &rs6000_reg_names[59][0], /* fr27 */ \
2253 &rs6000_reg_names[60][0], /* fr28 */ \
2254 &rs6000_reg_names[61][0], /* fr29 */ \
2255 &rs6000_reg_names[62][0], /* fr30 */ \
2256 &rs6000_reg_names[63][0], /* fr31 */ \
2257 \
2258 &rs6000_reg_names[64][0], /* mq */ \
2259 &rs6000_reg_names[65][0], /* lr */ \
2260 &rs6000_reg_names[66][0], /* ctr */ \
2261 &rs6000_reg_names[67][0], /* ap */ \
2262 \
2263 &rs6000_reg_names[68][0], /* cr0 */ \
2264 &rs6000_reg_names[69][0], /* cr1 */ \
2265 &rs6000_reg_names[70][0], /* cr2 */ \
2266 &rs6000_reg_names[71][0], /* cr3 */ \
2267 &rs6000_reg_names[72][0], /* cr4 */ \
2268 &rs6000_reg_names[73][0], /* cr5 */ \
2269 &rs6000_reg_names[74][0], /* cr6 */ \
2270 &rs6000_reg_names[75][0], /* cr7 */ \
802a0058 2271 \
f6b5d695 2272 &rs6000_reg_names[76][0], /* ca */ \
0ac081f6
AH		 2273 \
2274 &rs6000_reg_names[77][0], /* v0 */ \
2275 &rs6000_reg_names[78][0], /* v1 */ \
2276 &rs6000_reg_names[79][0], /* v2 */ \
2277 &rs6000_reg_names[80][0], /* v3 */ \
2278 &rs6000_reg_names[81][0], /* v4 */ \
2279 &rs6000_reg_names[82][0], /* v5 */ \
2280 &rs6000_reg_names[83][0], /* v6 */ \
2281 &rs6000_reg_names[84][0], /* v7 */ \
2282 &rs6000_reg_names[85][0], /* v8 */ \
2283 &rs6000_reg_names[86][0], /* v9 */ \
2284 &rs6000_reg_names[87][0], /* v10 */ \
2285 &rs6000_reg_names[88][0], /* v11 */ \
2286 &rs6000_reg_names[89][0], /* v12 */ \
2287 &rs6000_reg_names[90][0], /* v13 */ \
2288 &rs6000_reg_names[91][0], /* v14 */ \
2289 &rs6000_reg_names[92][0], /* v15 */ \
2290 &rs6000_reg_names[93][0], /* v16 */ \
2291 &rs6000_reg_names[94][0], /* v17 */ \
2292 &rs6000_reg_names[95][0], /* v18 */ \
2293 &rs6000_reg_names[96][0], /* v19 */ \
2294 &rs6000_reg_names[97][0], /* v20 */ \
2295 &rs6000_reg_names[98][0], /* v21 */ \
2296 &rs6000_reg_names[99][0], /* v22 */ \
2297 &rs6000_reg_names[100][0], /* v23 */ \
2298 &rs6000_reg_names[101][0], /* v24 */ \
2299 &rs6000_reg_names[102][0], /* v25 */ \
2300 &rs6000_reg_names[103][0], /* v26 */ \
2301 &rs6000_reg_names[104][0], /* v27 */ \
2302 &rs6000_reg_names[105][0], /* v28 */ \
2303 &rs6000_reg_names[106][0], /* v29 */ \
2304 &rs6000_reg_names[107][0], /* v30 */ \
2305 &rs6000_reg_names[108][0], /* v31 */ \
2306 &rs6000_reg_names[109][0], /* vrsave */ \
5f004351 2307 &rs6000_reg_names[110][0], /* vscr */ \
a3170dc6
AH		 2308 &rs6000_reg_names[111][0], /* spe_acc */ \
2309 &rs6000_reg_names[112][0], /* spefscr */ \
7d5175e1 2310 &rs6000_reg_names[113][0], /* sfp */ \
c81bebd7
MM		 2311}
2312
f045b2c9
RS		 2313/* Table of additional register names to use in user input. */
2314
2315#define ADDITIONAL_REGISTER_NAMES \
c4d38ccb
MM		 2316 {{"r0", 0}, {"r1", 1}, {"r2", 2}, {"r3", 3}, \
2317 {"r4", 4}, {"r5", 5}, {"r6", 6}, {"r7", 7}, \
2318 {"r8", 8}, {"r9", 9}, {"r10", 10}, {"r11", 11}, \
2319 {"r12", 12}, {"r13", 13}, {"r14", 14}, {"r15", 15}, \
2320 {"r16", 16}, {"r17", 17}, {"r18", 18}, {"r19", 19}, \
2321 {"r20", 20}, {"r21", 21}, {"r22", 22}, {"r23", 23}, \
2322 {"r24", 24}, {"r25", 25}, {"r26", 26}, {"r27", 27}, \
2323 {"r28", 28}, {"r29", 29}, {"r30", 30}, {"r31", 31}, \
2324 {"fr0", 32}, {"fr1", 33}, {"fr2", 34}, {"fr3", 35}, \
2325 {"fr4", 36}, {"fr5", 37}, {"fr6", 38}, {"fr7", 39}, \
2326 {"fr8", 40}, {"fr9", 41}, {"fr10", 42}, {"fr11", 43}, \
2327 {"fr12", 44}, {"fr13", 45}, {"fr14", 46}, {"fr15", 47}, \
2328 {"fr16", 48}, {"fr17", 49}, {"fr18", 50}, {"fr19", 51}, \
2329 {"fr20", 52}, {"fr21", 53}, {"fr22", 54}, {"fr23", 55}, \
2330 {"fr24", 56}, {"fr25", 57}, {"fr26", 58}, {"fr27", 59}, \
2331 {"fr28", 60}, {"fr29", 61}, {"fr30", 62}, {"fr31", 63}, \
0ac081f6
AH		 2332 {"v0", 77}, {"v1", 78}, {"v2", 79}, {"v3", 80}, \
2333 {"v4", 81}, {"v5", 82}, {"v6", 83}, {"v7", 84}, \
2334 {"v8", 85}, {"v9", 86}, {"v10", 87}, {"v11", 88}, \
2335 {"v12", 89}, {"v13", 90}, {"v14", 91}, {"v15", 92}, \
2336 {"v16", 93}, {"v17", 94}, {"v18", 95}, {"v19", 96}, \
2337 {"v20", 97}, {"v21", 98}, {"v22", 99}, {"v23", 100}, \
2338 {"v24", 101},{"v25", 102},{"v26", 103},{"v27", 104}, \
2339 {"v28", 105},{"v29", 106},{"v30", 107},{"v31", 108}, \
5f004351 2340 {"vrsave", 109}, {"vscr", 110}, \
a3170dc6 2341 {"spe_acc", 111}, {"spefscr", 112}, \
c4d38ccb
MM		 2342 /* no additional names for: mq, lr, ctr, ap */ \
2343 {"cr0", 68}, {"cr1", 69}, {"cr2", 70}, {"cr3", 71}, \
2344 {"cr4", 72}, {"cr5", 73}, {"cr6", 74}, {"cr7", 75}, \
cacf1ca8 2345 {"cc", 68}, {"sp", 1}, {"toc", 2}, \
f6b5d695
SB		 2346 /* CA is only part of XER, but we do not model the other parts (yet). */ \
2347 {"xer", 76}, \
cacf1ca8
MM		 2348 /* VSX registers overlaid on top of FR, Altivec registers */ \
2349 {"vs0", 32}, {"vs1", 33}, {"vs2", 34}, {"vs3", 35}, \
2350 {"vs4", 36}, {"vs5", 37}, {"vs6", 38}, {"vs7", 39}, \
2351 {"vs8", 40}, {"vs9", 41}, {"vs10", 42}, {"vs11", 43}, \
2352 {"vs12", 44}, {"vs13", 45}, {"vs14", 46}, {"vs15", 47}, \
2353 {"vs16", 48}, {"vs17", 49}, {"vs18", 50}, {"vs19", 51}, \
2354 {"vs20", 52}, {"vs21", 53}, {"vs22", 54}, {"vs23", 55}, \
2355 {"vs24", 56}, {"vs25", 57}, {"vs26", 58}, {"vs27", 59}, \
2356 {"vs28", 60}, {"vs29", 61}, {"vs30", 62}, {"vs31", 63}, \
2357 {"vs32", 77}, {"vs33", 78}, {"vs34", 79}, {"vs35", 80}, \
2358 {"vs36", 81}, {"vs37", 82}, {"vs38", 83}, {"vs39", 84}, \
2359 {"vs40", 85}, {"vs41", 86}, {"vs42", 87}, {"vs43", 88}, \
2360 {"vs44", 89}, {"vs45", 90}, {"vs46", 91}, {"vs47", 92}, \
2361 {"vs48", 93}, {"vs49", 94}, {"vs50", 95}, {"vs51", 96}, \
2362 {"vs52", 97}, {"vs53", 98}, {"vs54", 99}, {"vs55", 100}, \
2363 {"vs56", 101},{"vs57", 102},{"vs58", 103},{"vs59", 104}, \
2364 {"vs60", 105},{"vs61", 106},{"vs62", 107},{"vs63", 108} }
f045b2c9 2365
0da40b09
RK		 2366/* Text to write out after a CALL that may be replaced by glue code by
2367 the loader. This depends on the AIX version. */
2368#define RS6000_CALL_GLUE "cror 31,31,31"
11117bb9 2369
f045b2c9
RS		 2370/* This is how to output an element of a case-vector that is relative. */
2371
e1565e65 2372#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
3daf36a4 2373 do { char buf[100]; \
e1565e65 2374 fputs ("\t.long ", FILE); \
3daf36a4
ILT		 2375 ASM_GENERATE_INTERNAL_LABEL (buf, "L", VALUE); \
2376 assemble_name (FILE, buf); \
19d2d16f 2377 putc ('-', FILE); \
3daf36a4
ILT		 2378 ASM_GENERATE_INTERNAL_LABEL (buf, "L", REL); \
2379 assemble_name (FILE, buf); \
19d2d16f 2380 putc ('\n', FILE); \
3daf36a4 2381 } while (0)
f045b2c9
RS		 2382
2383/* This is how to output an assembler line
2384 that says to advance the location counter
2385 to a multiple of 2**LOG bytes. */
2386
2387#define ASM_OUTPUT_ALIGN(FILE,LOG) \
2388 if ((LOG) != 0) \
2389 fprintf (FILE, "\t.align %d\n", (LOG))
2390
9ebbca7d
GK		 2391/* Pick up the return address upon entry to a procedure. Used for
2392 dwarf2 unwind information. This also enables the table driven
2393 mechanism. */
2394
1de43f85
DE		 2395#define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNO)
2396#define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNO)
9ebbca7d 2397
83720594
RH		 2398/* Describe how we implement __builtin_eh_return. */
2399#define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 3 : INVALID_REGNUM)
2400#define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 10)
2401
f045b2c9
RS		 2402/* Print operand X (an rtx) in assembler syntax to file FILE.
2403 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2404 For `%' followed by punctuation, CODE is the punctuation and X is null. */
2405
2406#define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
2407
2408/* Define which CODE values are valid. */
2409
c81bebd7 2410#define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
c4501e62 2411 ((CODE) == '.' || (CODE) == '&')
f045b2c9
RS		 2412
2413/* Print a memory address as an operand to reference that memory location. */
2414
2415#define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
2416
2e4316da
RS		 2417#define OUTPUT_ADDR_CONST_EXTRA(STREAM, X, FAIL) \
2418 do \
2419 if (!rs6000_output_addr_const_extra (STREAM, X)) \
2420 goto FAIL; \
2421 while (0)
2422
b6c9286a
MM		 2423/* uncomment for disabling the corresponding default options */
2424/* #define MACHINE_no_sched_interblock */
2425/* #define MACHINE_no_sched_speculative */
2426/* #define MACHINE_no_sched_speculative_load */
2427
766a866c
MM		 2428/* General flags. */
2429extern int flag_pic;
354b734b
MM		 2430extern int optimize;
2431extern int flag_expensive_optimizations;
a7df97e6 2432extern int frame_pointer_needed;
0ac081f6 2433
1c9df37c
MM		 2434/* Classification of the builtin functions to properly set the declaration tree
2435 flags. */
2436enum rs6000_btc
2437{
2438 RS6000_BTC_MISC, /* assume builtin can do anything */
2439 RS6000_BTC_CONST, /* builtin is a 'const' function. */
2440 RS6000_BTC_PURE, /* builtin is a 'pure' function. */
2441 RS6000_BTC_FP_PURE /* builtin is 'pure' if rounding math. */
2442};
2443
2444/* Convenience macros to document the instruction type. */
2445#define RS6000_BTC_MEM RS6000_BTC_MISC /* load/store touches memory */
2446#define RS6000_BTC_SAT RS6000_BTC_MISC /* VMX saturate sets VSCR register */
2447
2448#undef RS6000_BUILTIN
2449#undef RS6000_BUILTIN_EQUATE
2450#define RS6000_BUILTIN(NAME, TYPE) NAME,
2451#define RS6000_BUILTIN_EQUATE(NAME, VALUE) NAME = VALUE,
2452
0ac081f6
AH		 2453enum rs6000_builtins
2454{
1c9df37c 2455#include "rs6000-builtin.def"
a72c65c7 2456
58646b77
PB		 2457 RS6000_BUILTIN_COUNT
2458};
2459
1c9df37c
MM		 2460#undef RS6000_BUILTIN
2461#undef RS6000_BUILTIN_EQUATE
2462
58646b77
PB		 2463enum rs6000_builtin_type_index
2464{
2465 RS6000_BTI_NOT_OPAQUE,
2466 RS6000_BTI_opaque_V2SI,
2467 RS6000_BTI_opaque_V2SF,
2468 RS6000_BTI_opaque_p_V2SI,
2469 RS6000_BTI_opaque_V4SI,
2470 RS6000_BTI_V16QI,
2471 RS6000_BTI_V2SI,
2472 RS6000_BTI_V2SF,
a72c65c7
MM		 2473 RS6000_BTI_V2DI,
2474 RS6000_BTI_V2DF,
58646b77
PB		 2475 RS6000_BTI_V4HI,
2476 RS6000_BTI_V4SI,
2477 RS6000_BTI_V4SF,
2478 RS6000_BTI_V8HI,
2479 RS6000_BTI_unsigned_V16QI,
2480 RS6000_BTI_unsigned_V8HI,
2481 RS6000_BTI_unsigned_V4SI,
a72c65c7 2482 RS6000_BTI_unsigned_V2DI,
58646b77
PB		 2483 RS6000_BTI_bool_char, /* __bool char */
2484 RS6000_BTI_bool_short, /* __bool short */
2485 RS6000_BTI_bool_int, /* __bool int */
a72c65c7 2486 RS6000_BTI_bool_long, /* __bool long */
58646b77
PB		 2487 RS6000_BTI_pixel, /* __pixel */
2488 RS6000_BTI_bool_V16QI, /* __vector __bool char */
2489 RS6000_BTI_bool_V8HI, /* __vector __bool short */
2490 RS6000_BTI_bool_V4SI, /* __vector __bool int */
a72c65c7 2491 RS6000_BTI_bool_V2DI, /* __vector __bool long */
58646b77
PB		 2492 RS6000_BTI_pixel_V8HI, /* __vector __pixel */
2493 RS6000_BTI_long, /* long_integer_type_node */
2494 RS6000_BTI_unsigned_long, /* long_unsigned_type_node */
2495 RS6000_BTI_INTQI, /* intQI_type_node */
2496 RS6000_BTI_UINTQI, /* unsigned_intQI_type_node */
2497 RS6000_BTI_INTHI, /* intHI_type_node */
2498 RS6000_BTI_UINTHI, /* unsigned_intHI_type_node */
2499 RS6000_BTI_INTSI, /* intSI_type_node */
2500 RS6000_BTI_UINTSI, /* unsigned_intSI_type_node */
a72c65c7
MM		 2501 RS6000_BTI_INTDI, /* intDI_type_node */
2502 RS6000_BTI_UINTDI, /* unsigned_intDI_type_node */
58646b77 2503 RS6000_BTI_float, /* float_type_node */
a72c65c7 2504 RS6000_BTI_double, /* double_type_node */
58646b77
PB		 2505 RS6000_BTI_void, /* void_type_node */
2506 RS6000_BTI_MAX
0ac081f6 2507};
58646b77
PB		 2508
2509
2510#define opaque_V2SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V2SI])
2511#define opaque_V2SF_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V2SF])
2512#define opaque_p_V2SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_p_V2SI])
2513#define opaque_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V4SI])
2514#define V16QI_type_node (rs6000_builtin_types[RS6000_BTI_V16QI])
a72c65c7
MM		 2515#define V2DI_type_node (rs6000_builtin_types[RS6000_BTI_V2DI])
2516#define V2DF_type_node (rs6000_builtin_types[RS6000_BTI_V2DF])
58646b77
PB		 2517#define V2SI_type_node (rs6000_builtin_types[RS6000_BTI_V2SI])
2518#define V2SF_type_node (rs6000_builtin_types[RS6000_BTI_V2SF])
2519#define V4HI_type_node (rs6000_builtin_types[RS6000_BTI_V4HI])
2520#define V4SI_type_node (rs6000_builtin_types[RS6000_BTI_V4SI])
2521#define V4SF_type_node (rs6000_builtin_types[RS6000_BTI_V4SF])
2522#define V8HI_type_node (rs6000_builtin_types[RS6000_BTI_V8HI])
2523#define unsigned_V16QI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V16QI])
2524#define unsigned_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V8HI])
2525#define unsigned_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V4SI])
a72c65c7 2526#define unsigned_V2DI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V2DI])
58646b77
PB		 2527#define bool_char_type_node (rs6000_builtin_types[RS6000_BTI_bool_char])
2528#define bool_short_type_node (rs6000_builtin_types[RS6000_BTI_bool_short])
2529#define bool_int_type_node (rs6000_builtin_types[RS6000_BTI_bool_int])
a72c65c7 2530#define bool_long_type_node (rs6000_builtin_types[RS6000_BTI_bool_long])
58646b77
PB		 2531#define pixel_type_node (rs6000_builtin_types[RS6000_BTI_pixel])
2532#define bool_V16QI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V16QI])
2533#define bool_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V8HI])
2534#define bool_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V4SI])
a72c65c7 2535#define bool_V2DI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V2DI])
58646b77
PB		 2536#define pixel_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_pixel_V8HI])
2537
2538#define long_integer_type_internal_node (rs6000_builtin_types[RS6000_BTI_long])
2539#define long_unsigned_type_internal_node (rs6000_builtin_types[RS6000_BTI_unsigned_long])
2540#define intQI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTQI])
2541#define uintQI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTQI])
2542#define intHI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTHI])
2543#define uintHI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTHI])
2544#define intSI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTSI])
2545#define uintSI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTSI])
a72c65c7
MM		 2546#define intDI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTDI])
2547#define uintDI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTDI])
58646b77 2548#define float_type_internal_node (rs6000_builtin_types[RS6000_BTI_float])
a72c65c7 2549#define double_type_internal_node (rs6000_builtin_types[RS6000_BTI_double])
58646b77
PB		 2550#define void_type_internal_node (rs6000_builtin_types[RS6000_BTI_void])
2551
2552extern GTY(()) tree rs6000_builtin_types[RS6000_BTI_MAX];
2553extern GTY(()) tree rs6000_builtin_decls[RS6000_BUILTIN_COUNT];
2554
GNU Compiler Collection
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