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rs6000.c (rs6000_gen_section_name): Do not include file extension in section name.
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9878760c 1/* Subroutines used for code generation on IBM RS/6000.
9ebbca7d 2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
d3c300d2 3 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
fab3bcc3 4 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
9878760c
RK		 5
6This file is part of GNU CC.
7
8GNU CC is free software; you can redistribute it and/or modify
9it under the terms of the GNU General Public License as published by
10the Free Software Foundation; either version 2, or (at your option)
11any later version.
12
13GNU CC is distributed in the hope that it will be useful,
14but WITHOUT ANY WARRANTY; without even the implied warranty of
15MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16GNU General Public License for more details.
17
18You should have received a copy of the GNU General Public License
19along with GNU CC; see the file COPYING. If not, write to
c15c9075
RK		 20the Free Software Foundation, 59 Temple Place - Suite 330,
21Boston, MA 02111-1307, USA. */
9878760c 22
956d6950 23#include "config.h"
c4d38ccb 24#include "system.h"
4977bab6
ZW		 25#include "coretypes.h"
26#include "tm.h"
9878760c
RK		 27#include "rtl.h"
28#include "regs.h"
29#include "hard-reg-set.h"
30#include "real.h"
31#include "insn-config.h"
32#include "conditions.h"
9878760c
RK		 33#include "insn-attr.h"
34#include "flags.h"
35#include "recog.h"
9878760c 36#include "obstack.h"
9b30bae2 37#include "tree.h"
dfafc897 38#include "expr.h"
2fc1c679 39#include "optabs.h"
2a430ec1 40#include "except.h"
a7df97e6 41#include "function.h"
296b8152 42#include "output.h"
d5fa86ba 43#include "basic-block.h"
d0101753 44#include "integrate.h"
296b8152 45#include "toplev.h"
c8023011 46#include "ggc.h"
9ebbca7d
GK		 47#include "hashtab.h"
48#include "tm_p.h"
672a6f42
NB		 49#include "target.h"
50#include "target-def.h"
3ac88239 51#include "langhooks.h"
24ea750e 52#include "reload.h"
9b30bae2 53
7509c759
MM		 54#ifndef TARGET_NO_PROTOTYPE
55#define TARGET_NO_PROTOTYPE 0
56#endif
57
9878760c
RK		 58#define min(A,B) ((A) < (B) ? (A) : (B))
59#define max(A,B) ((A) > (B) ? (A) : (B))
60
5248c961
RK		 61/* Target cpu type */
62
63enum processor_type rs6000_cpu;
8e3f41e7
MM		 64struct rs6000_cpu_select rs6000_select[3] =
65{
815cdc52
MM		 66 /* switch name, tune arch */
67 { (const char *)0, "--with-cpu=", 1, 1 },
68 { (const char *)0, "-mcpu=", 1, 1 },
69 { (const char *)0, "-mtune=", 1, 0 },
8e3f41e7 70};
5248c961 71
6fa3f289
ZW		 72/* Size of long double */
73const char *rs6000_long_double_size_string;
74int rs6000_long_double_type_size;
75
76/* Whether -mabi=altivec has appeared */
77int rs6000_altivec_abi;
78
08b57fb3
AH		 79/* Whether VRSAVE instructions should be generated. */
80int rs6000_altivec_vrsave;
81
82/* String from -mvrsave= option. */
83const char *rs6000_altivec_vrsave_string;
84
a3170dc6
AH		 85/* Nonzero if we want SPE ABI extensions. */
86int rs6000_spe_abi;
87
88/* Whether isel instructions should be generated. */
89int rs6000_isel;
90
91/* Nonzero if we have FPRs. */
92int rs6000_fprs = 1;
93
94/* String from -misel=. */
95const char *rs6000_isel_string;
96
a0ab749a 97/* Set to nonzero once AIX common-mode calls have been defined. */
bbfb86aa 98static GTY(()) int common_mode_defined;
c81bebd7 99
0e5dbd9b
DE		 100/* Private copy of original value of flag_pic for ABI_AIX. */
101static int rs6000_flag_pic;
102
9878760c
RK		 103/* Save information from a "cmpxx" operation until the branch or scc is
104 emitted. */
9878760c
RK		 105rtx rs6000_compare_op0, rs6000_compare_op1;
106int rs6000_compare_fp_p;
874a0744 107
874a0744
MM		 108/* Label number of label created for -mrelocatable, to call to so we can
109 get the address of the GOT section */
110int rs6000_pic_labelno;
c81bebd7 111
b91da81f 112#ifdef USING_ELFOS_H
c81bebd7 113/* Which abi to adhere to */
815cdc52 114const char *rs6000_abi_name = RS6000_ABI_NAME;
d9407988
MM		 115
116/* Semantics of the small data area */
117enum rs6000_sdata_type rs6000_sdata = SDATA_DATA;
118
119/* Which small data model to use */
815cdc52 120const char *rs6000_sdata_name = (char *)0;
9ebbca7d
GK		 121
122/* Counter for labels which are to be placed in .fixup. */
123int fixuplabelno = 0;
874a0744 124#endif
4697a36c 125
b6c9286a
MM		 126/* ABI enumeration available for subtarget to use. */
127enum rs6000_abi rs6000_current_abi;
128
0ac081f6
AH		 129/* ABI string from -mabi= option. */
130const char *rs6000_abi_string;
131
38c1f2d7 132/* Debug flags */
815cdc52 133const char *rs6000_debug_name;
38c1f2d7
MM		 134int rs6000_debug_stack; /* debug stack applications */
135int rs6000_debug_arg; /* debug argument handling */
136
57ac7be9
AM		 137const char *rs6000_traceback_name;
138static enum {
139 traceback_default = 0,
140 traceback_none,
141 traceback_part,
142 traceback_full
143} rs6000_traceback;
144
38c1f2d7
MM		 145/* Flag to say the TOC is initialized */
146int toc_initialized;
9ebbca7d 147char toc_label_name[10];
38c1f2d7 148
9ebbca7d
GK		 149/* Alias set for saves and restores from the rs6000 stack. */
150static int rs6000_sr_alias_set;
c8023011 151
a5c76ee6
ZW		 152/* Call distance, overridden by -mlongcall and #pragma longcall(1).
153 The only place that looks at this is rs6000_set_default_type_attributes;
154 everywhere else should rely on the presence or absence of a longcall
155 attribute on the function declaration. */
156int rs6000_default_long_calls;
157const char *rs6000_longcall_switch;
158
a3170dc6
AH		 159struct builtin_description
160{
161 /* mask is not const because we're going to alter it below. This
162 nonsense will go away when we rewrite the -march infrastructure
163 to give us more target flag bits. */
164 unsigned int mask;
165 const enum insn_code icode;
166 const char *const name;
167 const enum rs6000_builtins code;
168};
169
4977bab6 170static bool rs6000_function_ok_for_sibcall PARAMS ((tree, tree));
9ebbca7d 171static int num_insns_constant_wide PARAMS ((HOST_WIDE_INT));
39a10a29
GK		 172static void validate_condition_mode
173 PARAMS ((enum rtx_code, enum machine_mode));
174static rtx rs6000_generate_compare PARAMS ((enum rtx_code));
e50f5f3d 175static void rs6000_maybe_dead PARAMS ((rtx));
9ebbca7d
GK		 176static void rs6000_emit_stack_tie PARAMS ((void));
177static void rs6000_frame_related PARAMS ((rtx, rtx, HOST_WIDE_INT, rtx, rtx));
89e7058f
AH		 178static void emit_frame_save PARAMS ((rtx, rtx, enum machine_mode,
179 unsigned int, int, int));
a3170dc6 180static rtx gen_frame_mem_offset PARAMS ((enum machine_mode, rtx, int));
9ebbca7d
GK		 181static void rs6000_emit_allocate_stack PARAMS ((HOST_WIDE_INT, int));
182static unsigned rs6000_hash_constant PARAMS ((rtx));
183static unsigned toc_hash_function PARAMS ((const void *));
184static int toc_hash_eq PARAMS ((const void *, const void *));
9ebbca7d 185static int constant_pool_expr_1 PARAMS ((rtx, int *, int *));
e2500fed 186static struct machine_function * rs6000_init_machine_status PARAMS ((void));
301d03af 187static bool rs6000_assemble_integer PARAMS ((rtx, unsigned int, int));
5add3202 188#ifdef HAVE_GAS_HIDDEN
25fdb4dc 189static void rs6000_assemble_visibility PARAMS ((tree, int));
5add3202 190#endif
71f123ca 191static int rs6000_ra_ever_killed PARAMS ((void));
91d231cb
JM		 192static tree rs6000_handle_longcall_attribute PARAMS ((tree *, tree, tree, int, bool *));
193const struct attribute_spec rs6000_attribute_table[];
a5c76ee6 194static void rs6000_set_default_type_attributes PARAMS ((tree));
08c148a8
NB		 195static void rs6000_output_function_prologue PARAMS ((FILE *, HOST_WIDE_INT));
196static void rs6000_output_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT));
3961e8fe
RH		 197static void rs6000_output_mi_thunk PARAMS ((FILE *, tree, HOST_WIDE_INT,
198 HOST_WIDE_INT, tree));
2bfcf297
DB		 199static rtx rs6000_emit_set_long_const PARAMS ((rtx,
200 HOST_WIDE_INT, HOST_WIDE_INT));
7c262518
RH		 201#if TARGET_ELF
202static unsigned int rs6000_elf_section_type_flags PARAMS ((tree, const char *,
203 int));
d9f6800d
RH		 204static void rs6000_elf_asm_out_constructor PARAMS ((rtx, int));
205static void rs6000_elf_asm_out_destructor PARAMS ((rtx, int));
ae46c4e0 206static void rs6000_elf_select_section PARAMS ((tree, int,
5b71a4e7 207 unsigned HOST_WIDE_INT));
ae46c4e0 208static void rs6000_elf_unique_section PARAMS ((tree, int));
b64a1b53
RH		 209static void rs6000_elf_select_rtx_section PARAMS ((enum machine_mode, rtx,
210 unsigned HOST_WIDE_INT));
0e5dbd9b
DE		 211static void rs6000_elf_encode_section_info PARAMS ((tree, int))
212 ATTRIBUTE_UNUSED;
772c5265 213static const char *rs6000_elf_strip_name_encoding PARAMS ((const char *));
0e5dbd9b 214static bool rs6000_elf_in_small_data_p PARAMS ((tree));
7c262518 215#endif
cbaaba19 216#if TARGET_XCOFF
b275d088
DE		 217static void rs6000_xcoff_asm_globalize_label PARAMS ((FILE *, const char *));
218static void rs6000_xcoff_asm_named_section PARAMS ((const char *, unsigned int));
ae46c4e0
RH		 219static void rs6000_xcoff_select_section PARAMS ((tree, int,
220 unsigned HOST_WIDE_INT));
221static void rs6000_xcoff_unique_section PARAMS ((tree, int));
b64a1b53
RH		 222static void rs6000_xcoff_select_rtx_section PARAMS ((enum machine_mode, rtx,
223 unsigned HOST_WIDE_INT));
772c5265 224static const char * rs6000_xcoff_strip_name_encoding PARAMS ((const char *));
5add3202 225static unsigned int rs6000_xcoff_section_type_flags PARAMS ((tree, const char *, int));
7c262518 226#endif
fb49053f
RH		 227static void rs6000_xcoff_encode_section_info PARAMS ((tree, int))
228 ATTRIBUTE_UNUSED;
2bcc50d0 229static bool rs6000_binds_local_p PARAMS ((tree));
c237e94a
ZW		 230static int rs6000_adjust_cost PARAMS ((rtx, rtx, rtx, int));
231static int rs6000_adjust_priority PARAMS ((rtx, int));
232static int rs6000_issue_rate PARAMS ((void));
233
6fa3f289 234static void rs6000_init_builtins PARAMS ((void));
92898235
AH		 235static rtx rs6000_expand_unop_builtin PARAMS ((enum insn_code, tree, rtx));
236static rtx rs6000_expand_binop_builtin PARAMS ((enum insn_code, tree, rtx));
237static rtx rs6000_expand_ternop_builtin PARAMS ((enum insn_code, tree, rtx));
0ac081f6 238static rtx rs6000_expand_builtin PARAMS ((tree, rtx, rtx, enum machine_mode, int));
92898235 239static void altivec_init_builtins PARAMS ((void));
a3170dc6
AH		 240static void rs6000_common_init_builtins PARAMS ((void));
241
242static void enable_mask_for_builtins PARAMS ((struct builtin_description *,
243 int, enum rs6000_builtins,
244 enum rs6000_builtins));
245static void spe_init_builtins PARAMS ((void));
246static rtx spe_expand_builtin PARAMS ((tree, rtx, bool *));
247static rtx spe_expand_predicate_builtin PARAMS ((enum insn_code, tree, rtx));
248static rtx spe_expand_evsel_builtin PARAMS ((enum insn_code, tree, rtx));
249static int rs6000_emit_int_cmove PARAMS ((rtx, rtx, rtx, rtx));
250
92898235 251static rtx altivec_expand_builtin PARAMS ((tree, rtx, bool *));
3a9b8c7e
AH		 252static rtx altivec_expand_ld_builtin PARAMS ((tree, rtx, bool *));
253static rtx altivec_expand_st_builtin PARAMS ((tree, rtx, bool *));
254static rtx altivec_expand_dst_builtin PARAMS ((tree, rtx, bool *));
100c4561 255static rtx altivec_expand_abs_builtin PARAMS ((enum insn_code, tree, rtx));
ae4b4a02 256static rtx altivec_expand_predicate_builtin PARAMS ((enum insn_code, const char *, tree, rtx));
6525c0e7 257static rtx altivec_expand_stv_builtin PARAMS ((enum insn_code, tree));
0ac081f6 258static void rs6000_parse_abi_options PARAMS ((void));
08b57fb3 259static void rs6000_parse_vrsave_option PARAMS ((void));
a3170dc6 260static void rs6000_parse_isel_option PARAMS ((void));
00b960c7
AH		 261static int first_altivec_reg_to_save PARAMS ((void));
262static unsigned int compute_vrsave_mask PARAMS ((void));
263static void is_altivec_return_reg PARAMS ((rtx, void *));
9aa86737
AH		 264static rtx generate_set_vrsave PARAMS ((rtx, rs6000_stack_t *, int));
265static void altivec_frame_fixup PARAMS ((rtx, rtx, HOST_WIDE_INT));
69ef87e2 266static int easy_vector_constant PARAMS ((rtx));
17211ab5
GK		 267
268/* Hash table stuff for keeping track of TOC entries. */
269
270struct toc_hash_struct GTY(())
271{
272 /* `key' will satisfy CONSTANT_P; in fact, it will satisfy
273 ASM_OUTPUT_SPECIAL_POOL_ENTRY_P. */
274 rtx key;
275 enum machine_mode key_mode;
276 int labelno;
277};
278
279static GTY ((param_is (struct toc_hash_struct))) htab_t toc_hash_table;
c81bebd7
MM		 280\f
281/* Default register names. */
282char rs6000_reg_names[][8] =
283{
802a0058
MM		 284 "0", "1", "2", "3", "4", "5", "6", "7",
285 "8", "9", "10", "11", "12", "13", "14", "15",
286 "16", "17", "18", "19", "20", "21", "22", "23",
287 "24", "25", "26", "27", "28", "29", "30", "31",
288 "0", "1", "2", "3", "4", "5", "6", "7",
289 "8", "9", "10", "11", "12", "13", "14", "15",
290 "16", "17", "18", "19", "20", "21", "22", "23",
291 "24", "25", "26", "27", "28", "29", "30", "31",
292 "mq", "lr", "ctr","ap",
293 "0", "1", "2", "3", "4", "5", "6", "7",
0ac081f6
AH		 294 "xer",
295 /* AltiVec registers. */
0cd5e3a1
AH		 296 "0", "1", "2", "3", "4", "5", "6", "7",
297 "8", "9", "10", "11", "12", "13", "14", "15",
298 "16", "17", "18", "19", "20", "21", "22", "23",
299 "24", "25", "26", "27", "28", "29", "30", "31",
59a4c851
AH		 300 "vrsave", "vscr",
301 /* SPE registers. */
302 "spe_acc", "spefscr"
c81bebd7
MM		 303};
304
305#ifdef TARGET_REGNAMES
8b60264b 306static const char alt_reg_names[][8] =
c81bebd7 307{
802a0058
MM		 308 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7",
309 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
310 "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23",
311 "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31",
312 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7",
313 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15",
314 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23",
315 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31",
316 "mq", "lr", "ctr", "ap",
317 "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7",
0ac081f6 318 "xer",
59a4c851 319 /* AltiVec registers. */
0ac081f6 320 "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7",
59a4c851
AH		 321 "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15",
322 "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23",
323 "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31",
324 "vrsave", "vscr",
325 /* SPE registers. */
326 "spe_acc", "spefscr"
c81bebd7
MM		 327};
328#endif
9878760c 329\f
daf11973
MM		 330#ifndef MASK_STRICT_ALIGN
331#define MASK_STRICT_ALIGN 0
332#endif
3961e8fe
RH		 333
334/* The VRSAVE bitmask puts bit %v0 as the most significant bit. */
335#define ALTIVEC_REG_BIT(REGNO) (0x80000000 >> ((REGNO) - FIRST_ALTIVEC_REGNO))
672a6f42
NB		 336\f
337/* Initialize the GCC target structure. */
91d231cb
JM		 338#undef TARGET_ATTRIBUTE_TABLE
339#define TARGET_ATTRIBUTE_TABLE rs6000_attribute_table
a5c76ee6
ZW		 340#undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
341#define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES rs6000_set_default_type_attributes
daf11973 342
301d03af
RS		 343#undef TARGET_ASM_ALIGNED_DI_OP
344#define TARGET_ASM_ALIGNED_DI_OP DOUBLE_INT_ASM_OP
345
346/* Default unaligned ops are only provided for ELF. Find the ops needed
347 for non-ELF systems. */
348#ifndef OBJECT_FORMAT_ELF
cbaaba19 349#if TARGET_XCOFF
ae6c1efd 350/* For XCOFF. rs6000_assemble_integer will handle unaligned DIs on
301d03af
RS		 351 64-bit targets. */
352#undef TARGET_ASM_UNALIGNED_HI_OP
353#define TARGET_ASM_UNALIGNED_HI_OP "\t.vbyte\t2,"
354#undef TARGET_ASM_UNALIGNED_SI_OP
355#define TARGET_ASM_UNALIGNED_SI_OP "\t.vbyte\t4,"
356#undef TARGET_ASM_UNALIGNED_DI_OP
357#define TARGET_ASM_UNALIGNED_DI_OP "\t.vbyte\t8,"
358#else
359/* For Darwin. */
360#undef TARGET_ASM_UNALIGNED_HI_OP
361#define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t"
362#undef TARGET_ASM_UNALIGNED_SI_OP
363#define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t"
364#endif
365#endif
366
367/* This hook deals with fixups for relocatable code and DI-mode objects
368 in 64-bit code. */
369#undef TARGET_ASM_INTEGER
370#define TARGET_ASM_INTEGER rs6000_assemble_integer
371
93638d7a
AM		 372#ifdef HAVE_GAS_HIDDEN
373#undef TARGET_ASM_ASSEMBLE_VISIBILITY
374#define TARGET_ASM_ASSEMBLE_VISIBILITY rs6000_assemble_visibility
375#endif
376
08c148a8
NB		 377#undef TARGET_ASM_FUNCTION_PROLOGUE
378#define TARGET_ASM_FUNCTION_PROLOGUE rs6000_output_function_prologue
379#undef TARGET_ASM_FUNCTION_EPILOGUE
380#define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue
381
c237e94a
ZW		 382#undef TARGET_SCHED_ISSUE_RATE
383#define TARGET_SCHED_ISSUE_RATE rs6000_issue_rate
384#undef TARGET_SCHED_ADJUST_COST
385#define TARGET_SCHED_ADJUST_COST rs6000_adjust_cost
386#undef TARGET_SCHED_ADJUST_PRIORITY
387#define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority
388
0ac081f6
AH		 389#undef TARGET_INIT_BUILTINS
390#define TARGET_INIT_BUILTINS rs6000_init_builtins
391
392#undef TARGET_EXPAND_BUILTIN
393#define TARGET_EXPAND_BUILTIN rs6000_expand_builtin
394
0e5dbd9b
DE		 395#undef TARGET_BINDS_LOCAL_P
396#define TARGET_BINDS_LOCAL_P rs6000_binds_local_p
397
3961e8fe
RH		 398#undef TARGET_ASM_OUTPUT_MI_THUNK
399#define TARGET_ASM_OUTPUT_MI_THUNK rs6000_output_mi_thunk
400
3961e8fe 401#undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
5b71a4e7 402#define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
00b960c7 403
4977bab6
ZW		 404#undef TARGET_FUNCTION_OK_FOR_SIBCALL
405#define TARGET_FUNCTION_OK_FOR_SIBCALL rs6000_function_ok_for_sibcall
406
f6897b10 407struct gcc_target targetm = TARGET_INITIALIZER;
672a6f42 408\f
5248c961
RK		 409/* Override command line options. Mostly we process the processor
410 type and sometimes adjust other TARGET_ options. */
411
412void
8e3f41e7 413rs6000_override_options (default_cpu)
d330fd93 414 const char *default_cpu;
5248c961 415{
c4d38ccb 416 size_t i, j;
8e3f41e7 417 struct rs6000_cpu_select *ptr;
5248c961 418
85638c0d
RK		 419 /* Simplify the entries below by making a mask for any POWER
420 variant and any PowerPC variant. */
421
938937d8 422#define POWER_MASKS (MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING)
68c49ffa
RK		 423#define POWERPC_MASKS (MASK_POWERPC | MASK_PPC_GPOPT \
424 | MASK_PPC_GFXOPT | MASK_POWERPC64)
425#define POWERPC_OPT_MASKS (MASK_PPC_GPOPT | MASK_PPC_GFXOPT)
85638c0d 426
5248c961
RK		 427 static struct ptt
428 {
8b60264b
KG		 429 const char *const name; /* Canonical processor name. */
430 const enum processor_type processor; /* Processor type enum value. */
431 const int target_enable; /* Target flags to enable. */
432 const int target_disable; /* Target flags to disable. */
433 } const processor_target_table[]
cf27b467
MM		 434 = {{"common", PROCESSOR_COMMON, MASK_NEW_MNEMONICS,
435 POWER_MASKS | POWERPC_MASKS},
db7f1e43 436 {"power", PROCESSOR_POWER,
938937d8 437 MASK_POWER | MASK_MULTIPLE | MASK_STRING,
db7f1e43 438 MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS},
8e3f41e7
MM		 439 {"power2", PROCESSOR_POWER,
440 MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING,
441 POWERPC_MASKS | MASK_NEW_MNEMONICS},
c71791e0
DE		 442 {"power3", PROCESSOR_PPC630,
443 MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
444 POWER_MASKS | MASK_PPC_GPOPT},
309323c2
DE		 445 {"power4", PROCESSOR_POWER4,
446 MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
447 POWER_MASKS | MASK_PPC_GPOPT},
db7f1e43
RK		 448 {"powerpc", PROCESSOR_POWERPC,
449 MASK_POWERPC | MASK_NEW_MNEMONICS,
68c49ffa 450 POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64},
3cb999d8
DE		 451 {"powerpc64", PROCESSOR_POWERPC64,
452 MASK_POWERPC | MASK_POWERPC64 | MASK_NEW_MNEMONICS,
453 POWER_MASKS | POWERPC_OPT_MASKS},
db7f1e43 454 {"rios", PROCESSOR_RIOS1,
938937d8 455 MASK_POWER | MASK_MULTIPLE | MASK_STRING,
db7f1e43
RK		 456 MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS},
457 {"rios1", PROCESSOR_RIOS1,
938937d8 458 MASK_POWER | MASK_MULTIPLE | MASK_STRING,
db7f1e43
RK		 459 MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS},
460 {"rsc", PROCESSOR_PPC601,
938937d8 461 MASK_POWER | MASK_MULTIPLE | MASK_STRING,
db7f1e43
RK		 462 MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS},
463 {"rsc1", PROCESSOR_PPC601,
938937d8 464 MASK_POWER | MASK_MULTIPLE | MASK_STRING,
db7f1e43
RK		 465 MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS},
466 {"rios2", PROCESSOR_RIOS2,
938937d8 467 MASK_POWER | MASK_MULTIPLE | MASK_STRING | MASK_POWER2,
db7f1e43 468 POWERPC_MASKS | MASK_NEW_MNEMONICS},
3cb999d8
DE		 469 {"rs64a", PROCESSOR_RS64A,
470 MASK_POWERPC | MASK_NEW_MNEMONICS,
471 POWER_MASKS | POWERPC_OPT_MASKS},
a3a1dbf6
MM		 472 {"401", PROCESSOR_PPC403,
473 MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS,
474 POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64},
49a0b204 475 {"403", PROCESSOR_PPC403,
daf11973 476 MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS | MASK_STRICT_ALIGN,
49a0b204 477 POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64},
d7a5e253
DE		 478 {"405", PROCESSOR_PPC405,
479 MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS,
480 POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64},
4977bab6
ZW		 481 {"405f", PROCESSOR_PPC405,
482 MASK_POWERPC | MASK_NEW_MNEMONICS,
483 POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64},
cf27b467
MM		 484 {"505", PROCESSOR_MPCCORE,
485 MASK_POWERPC | MASK_NEW_MNEMONICS,
486 POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64},
5248c961 487 {"601", PROCESSOR_PPC601,
938937d8 488 MASK_POWER | MASK_POWERPC | MASK_NEW_MNEMONICS | MASK_MULTIPLE | MASK_STRING,
68c49ffa 489 MASK_POWER2 | POWERPC_OPT_MASKS | MASK_POWERPC64},
1ec26da6 490 {"602", PROCESSOR_PPC603,
cf27b467
MM		 491 MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
492 POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64},
5248c961 493 {"603", PROCESSOR_PPC603,
68c49ffa
RK		 494 MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
495 POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64},
b6c9286a
MM		 496 {"603e", PROCESSOR_PPC603,
497 MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
498 POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64},
b5370a88 499 {"ec603e", PROCESSOR_PPC603,
a3a1dbf6
MM		 500 MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS,
501 POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64},
5248c961 502 {"604", PROCESSOR_PPC604,
b6c9286a
MM		 503 MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
504 POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64},
cac8ce95 505 {"604e", PROCESSOR_PPC604e,
07e6159a
MM		 506 MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
507 POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64},
b6c9286a 508 {"620", PROCESSOR_PPC620,
68c49ffa 509 MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
a260abc9 510 POWER_MASKS | MASK_PPC_GPOPT},
3cb999d8
DE		 511 {"630", PROCESSOR_PPC630,
512 MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
513 POWER_MASKS | MASK_PPC_GPOPT},
bef84347
VM		 514 {"740", PROCESSOR_PPC750,
515 MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
516 POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64},
517 {"750", PROCESSOR_PPC750,
518 MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
519 POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64},
a4f6c312
SS		 520 {"7400", PROCESSOR_PPC7400,
521 MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
522 POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64},
523 {"7450", PROCESSOR_PPC7450,
524 MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
525 POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64},
a3170dc6
AH		 526 {"8540", PROCESSOR_PPC8540,
527 MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
528 POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64},
07e6159a
MM		 529 {"801", PROCESSOR_MPCCORE,
530 MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS,
531 POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64},
cf27b467
MM		 532 {"821", PROCESSOR_MPCCORE,
533 MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS,
534 POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64},
07e6159a
MM		 535 {"823", PROCESSOR_MPCCORE,
536 MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS,
537 POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64},
cf27b467
MM		 538 {"860", PROCESSOR_MPCCORE,
539 MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS,
540 POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}};
5248c961 541
ca7558fc 542 const size_t ptt_size = ARRAY_SIZE (processor_target_table);
5248c961 543
a4f6c312
SS		 544 /* Save current -mmultiple/-mno-multiple status. */
545 int multiple = TARGET_MULTIPLE;
546 /* Save current -mstring/-mno-string status. */
547 int string = TARGET_STRING;
8a61d227 548
a4f6c312 549 /* Identify the processor type. */
8e3f41e7 550 rs6000_select[0].string = default_cpu;
3cb999d8 551 rs6000_cpu = TARGET_POWERPC64 ? PROCESSOR_DEFAULT64 : PROCESSOR_DEFAULT;
8e3f41e7 552
b6a1cbae 553 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
5248c961 554 {
8e3f41e7
MM		 555 ptr = &rs6000_select[i];
556 if (ptr->string != (char *)0 && ptr->string[0] != '\0')
5248c961 557 {
8e3f41e7
MM		 558 for (j = 0; j < ptt_size; j++)
559 if (! strcmp (ptr->string, processor_target_table[j].name))
560 {
561 if (ptr->set_tune_p)
562 rs6000_cpu = processor_target_table[j].processor;
563
564 if (ptr->set_arch_p)
565 {
566 target_flags |= processor_target_table[j].target_enable;
567 target_flags &= ~processor_target_table[j].target_disable;
568 }
569 break;
570 }
571
4406229e 572 if (j == ptt_size)
8e3f41e7 573 error ("bad value (%s) for %s switch", ptr->string, ptr->name);
5248c961
RK		 574 }
575 }
8a61d227 576
a3170dc6
AH		 577 if (rs6000_cpu == PROCESSOR_PPC8540)
578 rs6000_isel = 1;
579
dff9f1b6
DE		 580 /* If we are optimizing big endian systems for space, use the load/store
581 multiple and string instructions. */
ef792183 582 if (BYTES_BIG_ENDIAN && optimize_size)
dff9f1b6 583 target_flags |= MASK_MULTIPLE | MASK_STRING;
ef792183 584
8a61d227
MM		 585 /* If -mmultiple or -mno-multiple was explicitly used, don't
586 override with the processor default */
b21fb038 587 if ((target_flags_explicit & MASK_MULTIPLE) != 0)
8a61d227 588 target_flags = (target_flags & ~MASK_MULTIPLE) | multiple;
7e69e155 589
a4f6c312
SS		 590 /* If -mstring or -mno-string was explicitly used, don't override
591 with the processor default. */
b21fb038 592 if ((target_flags_explicit & MASK_STRING) != 0)
1f5515bf 593 target_flags = (target_flags & ~MASK_STRING) | string;
938937d8 594
a4f6c312
SS		 595 /* Don't allow -mmultiple or -mstring on little endian systems
596 unless the cpu is a 750, because the hardware doesn't support the
597 instructions used in little endian mode, and causes an alignment
598 trap. The 750 does not cause an alignment trap (except when the
599 target is unaligned). */
bef84347 600
b21fb038 601 if (!BYTES_BIG_ENDIAN && rs6000_cpu != PROCESSOR_PPC750)
7e69e155
MM		 602 {
603 if (TARGET_MULTIPLE)
604 {
605 target_flags &= ~MASK_MULTIPLE;
b21fb038 606 if ((target_flags_explicit & MASK_MULTIPLE) != 0)
7e69e155
MM		 607 warning ("-mmultiple is not supported on little endian systems");
608 }
609
610 if (TARGET_STRING)
611 {
612 target_flags &= ~MASK_STRING;
b21fb038 613 if ((target_flags_explicit & MASK_STRING) != 0)
938937d8 614 warning ("-mstring is not supported on little endian systems");
7e69e155
MM		 615 }
616 }
3933e0e1 617
ee2ca2a2 618 if (flag_pic != 0 && DEFAULT_ABI == ABI_AIX)
a260abc9 619 {
0e5dbd9b 620 rs6000_flag_pic = flag_pic;
ee2ca2a2 621 flag_pic = 0;
a260abc9
DE		 622 }
623
c72bfda7
SS		 624 /* For Darwin, always silently make -fpic and -fPIC identical. */
625 if (flag_pic == 1 && DEFAULT_ABI == ABI_DARWIN)
626 flag_pic = 2;
627
38c1f2d7
MM		 628 /* Set debug flags */
629 if (rs6000_debug_name)
630 {
bfc79d3b 631 if (! strcmp (rs6000_debug_name, "all"))
38c1f2d7 632 rs6000_debug_stack = rs6000_debug_arg = 1;
bfc79d3b 633 else if (! strcmp (rs6000_debug_name, "stack"))
38c1f2d7 634 rs6000_debug_stack = 1;
bfc79d3b 635 else if (! strcmp (rs6000_debug_name, "arg"))
38c1f2d7
MM		 636 rs6000_debug_arg = 1;
637 else
c725bd79 638 error ("unknown -mdebug-%s switch", rs6000_debug_name);
38c1f2d7
MM		 639 }
640
57ac7be9
AM		 641 if (rs6000_traceback_name)
642 {
643 if (! strncmp (rs6000_traceback_name, "full", 4))
644 rs6000_traceback = traceback_full;
645 else if (! strncmp (rs6000_traceback_name, "part", 4))
646 rs6000_traceback = traceback_part;
647 else if (! strncmp (rs6000_traceback_name, "no", 2))
648 rs6000_traceback = traceback_none;
649 else
650 error ("unknown -mtraceback arg `%s'; expecting `full', `partial' or `none'",
651 rs6000_traceback_name);
652 }
653
6fa3f289
ZW		 654 /* Set size of long double */
655 rs6000_long_double_type_size = 64;
656 if (rs6000_long_double_size_string)
657 {
658 char *tail;
659 int size = strtol (rs6000_long_double_size_string, &tail, 10);
660 if (*tail != '\0' || (size != 64 && size != 128))
661 error ("Unknown switch -mlong-double-%s",
662 rs6000_long_double_size_string);
663 else
664 rs6000_long_double_type_size = size;
665 }
666
0ac081f6
AH		 667 /* Handle -mabi= options. */
668 rs6000_parse_abi_options ();
669
08b57fb3
AH		 670 /* Handle -mvrsave= option. */
671 rs6000_parse_vrsave_option ();
672
a3170dc6
AH		 673 /* Handle -misel= option. */
674 rs6000_parse_isel_option ();
675
a7ae18e2
AH		 676#ifdef SUBTARGET_OVERRIDE_OPTIONS
677 SUBTARGET_OVERRIDE_OPTIONS;
678#endif
679#ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
680 SUBSUBTARGET_OVERRIDE_OPTIONS;
681#endif
682
a5c76ee6
ZW		 683 /* Handle -m(no-)longcall option. This is a bit of a cheap hack,
684 using TARGET_OPTIONS to handle a toggle switch, but we're out of
685 bits in target_flags so TARGET_SWITCHES cannot be used.
686 Assumption here is that rs6000_longcall_switch points into the
687 text of the complete option, rather than being a copy, so we can
688 scan back for the presence or absence of the no- modifier. */
689 if (rs6000_longcall_switch)
690 {
691 const char *base = rs6000_longcall_switch;
692 while (base[-1] != 'm') base--;
693
694 if (*rs6000_longcall_switch != '\0')
695 error ("invalid option `%s'", base);
696 rs6000_default_long_calls = (base[0] != 'n');
697 }
698
c81bebd7 699#ifdef TARGET_REGNAMES
a4f6c312
SS		 700 /* If the user desires alternate register names, copy in the
701 alternate names now. */
c81bebd7 702 if (TARGET_REGNAMES)
4e135bdd 703 memcpy (rs6000_reg_names, alt_reg_names, sizeof (rs6000_reg_names));
c81bebd7
MM		 704#endif
705
6fa3f289
ZW		 706 /* Set TARGET_AIX_STRUCT_RET last, after the ABI is determined.
707 If -maix-struct-return or -msvr4-struct-return was explicitly
708 used, don't override with the ABI default. */
b21fb038 709 if ((target_flags_explicit & MASK_AIX_STRUCT_RET) == 0)
6fa3f289
ZW		 710 {
711 if (DEFAULT_ABI == ABI_V4 && !DRAFT_V4_STRUCT_RET)
712 target_flags = (target_flags & ~MASK_AIX_STRUCT_RET);
713 else
714 target_flags |= MASK_AIX_STRUCT_RET;
715 }
716
fcce224d
DE		 717 if (TARGET_LONG_DOUBLE_128
718 && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN))
719 real_format_for_mode[TFmode - QFmode] = &ibm_extended_format;
720
9ebbca7d
GK		 721 /* Allocate an alias set for register saves & restores from stack. */
722 rs6000_sr_alias_set = new_alias_set ();
723
724 if (TARGET_TOC)
725 ASM_GENERATE_INTERNAL_LABEL (toc_label_name, "LCTOC", 1);
71f123ca 726
301d03af
RS		 727 /* We can only guarantee the availability of DI pseudo-ops when
728 assembling for 64-bit targets. */
ae6c1efd 729 if (!TARGET_64BIT)
301d03af
RS		 730 {
731 targetm.asm_out.aligned_op.di = NULL;
732 targetm.asm_out.unaligned_op.di = NULL;
733 }
734
71f123ca
FS		 735 /* Arrange to save and restore machine status around nested functions. */
736 init_machine_status = rs6000_init_machine_status;
5248c961 737}
5accd822 738
a3170dc6
AH		 739/* Handle -misel= option. */
740static void
741rs6000_parse_isel_option ()
742{
743 if (rs6000_isel_string == 0)
744 return;
745 else if (! strcmp (rs6000_isel_string, "yes"))
746 rs6000_isel = 1;
747 else if (! strcmp (rs6000_isel_string, "no"))
748 rs6000_isel = 0;
749 else
750 error ("unknown -misel= option specified: '%s'",
751 rs6000_isel_string);
752}
753
08b57fb3
AH		 754/* Handle -mvrsave= options. */
755static void
756rs6000_parse_vrsave_option ()
757{
758 /* Generate VRSAVE instructions by default. */
759 if (rs6000_altivec_vrsave_string == 0
760 || ! strcmp (rs6000_altivec_vrsave_string, "yes"))
761 rs6000_altivec_vrsave = 1;
762 else if (! strcmp (rs6000_altivec_vrsave_string, "no"))
763 rs6000_altivec_vrsave = 0;
764 else
765 error ("unknown -mvrsave= option specified: '%s'",
766 rs6000_altivec_vrsave_string);
767}
768
0ac081f6 769/* Handle -mabi= options. */
00b960c7
AH		 770static void
771rs6000_parse_abi_options ()
0ac081f6
AH		 772{
773 if (rs6000_abi_string == 0)
774 return;
775 else if (! strcmp (rs6000_abi_string, "altivec"))
6fa3f289 776 rs6000_altivec_abi = 1;
76a773f3
AH		 777 else if (! strcmp (rs6000_abi_string, "no-altivec"))
778 rs6000_altivec_abi = 0;
a3170dc6
AH		 779 else if (! strcmp (rs6000_abi_string, "spe"))
780 rs6000_spe_abi = 1;
781 else if (! strcmp (rs6000_abi_string, "no-spe"))
782 rs6000_spe_abi = 0;
0ac081f6 783 else
c725bd79 784 error ("unknown ABI specified: '%s'", rs6000_abi_string);
0ac081f6
AH		 785}
786
5accd822
DE		 787void
788optimization_options (level, size)
e2c953b6 789 int level ATTRIBUTE_UNUSED;
5accd822
DE		 790 int size ATTRIBUTE_UNUSED;
791{
5accd822 792}
3cfa4909
MM		 793\f
794/* Do anything needed at the start of the asm file. */
795
796void
797rs6000_file_start (file, default_cpu)
798 FILE *file;
d330fd93 799 const char *default_cpu;
3cfa4909 800{
c4d38ccb 801 size_t i;
3cfa4909 802 char buffer[80];
d330fd93 803 const char *start = buffer;
3cfa4909
MM		 804 struct rs6000_cpu_select *ptr;
805
806 if (flag_verbose_asm)
807 {
808 sprintf (buffer, "\n%s rs6000/powerpc options:", ASM_COMMENT_START);
809 rs6000_select[0].string = default_cpu;
810
b6a1cbae 811 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
3cfa4909
MM		 812 {
813 ptr = &rs6000_select[i];
814 if (ptr->string != (char *)0 && ptr->string[0] != '\0')
815 {
816 fprintf (file, "%s %s%s", start, ptr->name, ptr->string);
817 start = "";
818 }
819 }
820
b91da81f 821#ifdef USING_ELFOS_H
3cfa4909
MM		 822 switch (rs6000_sdata)
823 {
824 case SDATA_NONE: fprintf (file, "%s -msdata=none", start); start = ""; break;
825 case SDATA_DATA: fprintf (file, "%s -msdata=data", start); start = ""; break;
826 case SDATA_SYSV: fprintf (file, "%s -msdata=sysv", start); start = ""; break;
827 case SDATA_EABI: fprintf (file, "%s -msdata=eabi", start); start = ""; break;
828 }
829
830 if (rs6000_sdata && g_switch_value)
831 {
832 fprintf (file, "%s -G %d", start, g_switch_value);
833 start = "";
834 }
835#endif
836
837 if (*start == '\0')
949ea356 838 putc ('\n', file);
3cfa4909
MM		 839 }
840}
5248c961 841\f
a0ab749a 842/* Return nonzero if this function is known to have a null epilogue. */
9878760c
RK		 843
844int
845direct_return ()
846{
4697a36c
MM		 847 if (reload_completed)
848 {
849 rs6000_stack_t *info = rs6000_stack_info ();
850
851 if (info->first_gp_reg_save == 32
852 && info->first_fp_reg_save == 64
00b960c7 853 && info->first_altivec_reg_save == LAST_ALTIVEC_REGNO + 1
c81fc13e
DE		 854 && ! info->lr_save_p
855 && ! info->cr_save_p
00b960c7 856 && info->vrsave_mask == 0
c81fc13e 857 && ! info->push_p)
4697a36c
MM		 858 return 1;
859 }
860
861 return 0;
9878760c
RK		 862}
863
864/* Returns 1 always. */
865
866int
867any_operand (op, mode)
592696dd 868 rtx op ATTRIBUTE_UNUSED;
296b8152 869 enum machine_mode mode ATTRIBUTE_UNUSED;
9878760c
RK		 870{
871 return 1;
872}
873
a4f6c312 874/* Returns 1 if op is the count register. */
38c1f2d7 875int
a4f6c312 876count_register_operand (op, mode)
592696dd 877 rtx op;
296b8152 878 enum machine_mode mode ATTRIBUTE_UNUSED;
b6c9286a
MM		 879{
880 if (GET_CODE (op) != REG)
881 return 0;
882
883 if (REGNO (op) == COUNT_REGISTER_REGNUM)
884 return 1;
885
886 if (REGNO (op) > FIRST_PSEUDO_REGISTER)
887 return 1;
888
889 return 0;
890}
891
0ec4e2a8
AH		 892/* Returns 1 if op is an altivec register. */
893int
894altivec_register_operand (op, mode)
895 rtx op;
896 enum machine_mode mode ATTRIBUTE_UNUSED;
897{
898
899 return (register_operand (op, mode)
900 && (GET_CODE (op) != REG
901 || REGNO (op) > FIRST_PSEUDO_REGISTER
902 || ALTIVEC_REGNO_P (REGNO (op))));
903}
904
38c1f2d7 905int
a4f6c312 906xer_operand (op, mode)
592696dd 907 rtx op;
296b8152 908 enum machine_mode mode ATTRIBUTE_UNUSED;
802a0058
MM		 909{
910 if (GET_CODE (op) != REG)
911 return 0;
912
9ebbca7d 913 if (XER_REGNO_P (REGNO (op)))
802a0058
MM		 914 return 1;
915
802a0058
MM		 916 return 0;
917}
918
c859cda6 919/* Return 1 if OP is a signed 8-bit constant. Int multiplication
6f317ef3 920 by such constants completes more quickly. */
c859cda6
DJ		 921
922int
923s8bit_cint_operand (op, mode)
924 rtx op;
925 enum machine_mode mode ATTRIBUTE_UNUSED;
926{
927 return ( GET_CODE (op) == CONST_INT
928 && (INTVAL (op) >= -128 && INTVAL (op) <= 127));
929}
930
9878760c
RK		 931/* Return 1 if OP is a constant that can fit in a D field. */
932
933int
934short_cint_operand (op, mode)
592696dd 935 rtx op;
296b8152 936 enum machine_mode mode ATTRIBUTE_UNUSED;
9878760c 937{
5f59ecb7
DE		 938 return (GET_CODE (op) == CONST_INT
939 && CONST_OK_FOR_LETTER_P (INTVAL (op), 'I'));
9878760c
RK		 940}
941
5519a4f9 942/* Similar for an unsigned D field. */
9878760c
RK		 943
944int
945u_short_cint_operand (op, mode)
592696dd 946 rtx op;
296b8152 947 enum machine_mode mode ATTRIBUTE_UNUSED;
9878760c 948{
19684119 949 return (GET_CODE (op) == CONST_INT
c1f11548 950 && CONST_OK_FOR_LETTER_P (INTVAL (op) & GET_MODE_MASK (mode), 'K'));
9878760c
RK		 951}
952
dcfedcd0
RK		 953/* Return 1 if OP is a CONST_INT that cannot fit in a signed D field. */
954
955int
956non_short_cint_operand (op, mode)
592696dd 957 rtx op;
296b8152 958 enum machine_mode mode ATTRIBUTE_UNUSED;
dcfedcd0
RK		 959{
960 return (GET_CODE (op) == CONST_INT
a7653a2c 961 && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x8000) >= 0x10000);
dcfedcd0
RK		 962}
963
2bfcf297
DB		 964/* Returns 1 if OP is a CONST_INT that is a positive value
965 and an exact power of 2. */
966
967int
968exact_log2_cint_operand (op, mode)
592696dd 969 rtx op;
2bfcf297
DB		 970 enum machine_mode mode ATTRIBUTE_UNUSED;
971{
972 return (GET_CODE (op) == CONST_INT
973 && INTVAL (op) > 0
974 && exact_log2 (INTVAL (op)) >= 0);
975}
976
9878760c
RK		 977/* Returns 1 if OP is a register that is not special (i.e., not MQ,
978 ctr, or lr). */
979
980int
cd2b37d9 981gpc_reg_operand (op, mode)
592696dd 982 rtx op;
9878760c
RK		 983 enum machine_mode mode;
984{
985 return (register_operand (op, mode)
802a0058 986 && (GET_CODE (op) != REG
9ebbca7d
GK		 987 || (REGNO (op) >= ARG_POINTER_REGNUM
988 && !XER_REGNO_P (REGNO (op)))
989 || REGNO (op) < MQ_REGNO));
9878760c
RK		 990}
991
992/* Returns 1 if OP is either a pseudo-register or a register denoting a
993 CR field. */
994
995int
996cc_reg_operand (op, mode)
592696dd 997 rtx op;
9878760c
RK		 998 enum machine_mode mode;
999{
1000 return (register_operand (op, mode)
1001 && (GET_CODE (op) != REG
1002 || REGNO (op) >= FIRST_PSEUDO_REGISTER
1003 || CR_REGNO_P (REGNO (op))));
1004}
1005
815cdc52
MM		 1006/* Returns 1 if OP is either a pseudo-register or a register denoting a
1007 CR field that isn't CR0. */
1008
1009int
1010cc_reg_not_cr0_operand (op, mode)
592696dd 1011 rtx op;
815cdc52
MM		 1012 enum machine_mode mode;
1013{
1014 return (register_operand (op, mode)
1015 && (GET_CODE (op) != REG
1016 || REGNO (op) >= FIRST_PSEUDO_REGISTER
1017 || CR_REGNO_NOT_CR0_P (REGNO (op))));
1018}
1019
a4f6c312
SS		 1020/* Returns 1 if OP is either a constant integer valid for a D-field or
1021 a non-special register. If a register, it must be in the proper
1022 mode unless MODE is VOIDmode. */
9878760c
RK		 1023
1024int
1025reg_or_short_operand (op, mode)
592696dd 1026 rtx op;
9878760c
RK		 1027 enum machine_mode mode;
1028{
f5a28898 1029 return short_cint_operand (op, mode) || gpc_reg_operand (op, mode);
9878760c
RK		 1030}
1031
a4f6c312
SS		 1032/* Similar, except check if the negation of the constant would be
1033 valid for a D-field. */
9878760c
RK		 1034
1035int
1036reg_or_neg_short_operand (op, mode)
592696dd 1037 rtx op;
9878760c
RK		 1038 enum machine_mode mode;
1039{
1040 if (GET_CODE (op) == CONST_INT)
1041 return CONST_OK_FOR_LETTER_P (INTVAL (op), 'P');
1042
cd2b37d9 1043 return gpc_reg_operand (op, mode);
9878760c
RK		 1044}
1045
768070a0
TR		 1046/* Returns 1 if OP is either a constant integer valid for a DS-field or
1047 a non-special register. If a register, it must be in the proper
1048 mode unless MODE is VOIDmode. */
1049
1050int
1051reg_or_aligned_short_operand (op, mode)
1052 rtx op;
1053 enum machine_mode mode;
1054{
1055 if (gpc_reg_operand (op, mode))
1056 return 1;
1057 else if (short_cint_operand (op, mode) && !(INTVAL (op) & 3))
1058 return 1;
1059
1060 return 0;
1061}
1062
1063
a4f6c312
SS		 1064/* Return 1 if the operand is either a register or an integer whose
1065 high-order 16 bits are zero. */
9878760c
RK		 1066
1067int
1068reg_or_u_short_operand (op, mode)
592696dd 1069 rtx op;
9878760c
RK		 1070 enum machine_mode mode;
1071{
e675f625 1072 return u_short_cint_operand (op, mode) || gpc_reg_operand (op, mode);
9878760c
RK		 1073}
1074
1075/* Return 1 is the operand is either a non-special register or ANY
1076 constant integer. */
1077
1078int
1079reg_or_cint_operand (op, mode)
592696dd 1080 rtx op;
9878760c
RK		 1081 enum machine_mode mode;
1082{
a4f6c312 1083 return (GET_CODE (op) == CONST_INT || gpc_reg_operand (op, mode));
f6bf7de2
DE		 1084}
1085
1086/* Return 1 is the operand is either a non-special register or ANY
1087 32-bit signed constant integer. */
1088
1089int
1090reg_or_arith_cint_operand (op, mode)
592696dd 1091 rtx op;
f6bf7de2
DE		 1092 enum machine_mode mode;
1093{
a4f6c312
SS		 1094 return (gpc_reg_operand (op, mode)
1095 || (GET_CODE (op) == CONST_INT
f6bf7de2 1096#if HOST_BITS_PER_WIDE_INT != 32
a4f6c312
SS		 1097 && ((unsigned HOST_WIDE_INT) (INTVAL (op) + 0x80000000)
1098 < (unsigned HOST_WIDE_INT) 0x100000000ll)
f6bf7de2 1099#endif
a4f6c312 1100 ));
9878760c
RK		 1101}
1102
2bfcf297
DB		 1103/* Return 1 is the operand is either a non-special register or a 32-bit
1104 signed constant integer valid for 64-bit addition. */
1105
1106int
1107reg_or_add_cint64_operand (op, mode)
592696dd 1108 rtx op;
2bfcf297
DB		 1109 enum machine_mode mode;
1110{
a4f6c312
SS		 1111 return (gpc_reg_operand (op, mode)
1112 || (GET_CODE (op) == CONST_INT
a65c591c 1113#if HOST_BITS_PER_WIDE_INT == 32
a4f6c312 1114 && INTVAL (op) < 0x7fff8000
a65c591c 1115#else
a4f6c312
SS		 1116 && ((unsigned HOST_WIDE_INT) (INTVAL (op) + 0x80008000)
1117 < 0x100000000ll)
2bfcf297 1118#endif
a4f6c312 1119 ));
2bfcf297
DB		 1120}
1121
1122/* Return 1 is the operand is either a non-special register or a 32-bit
1123 signed constant integer valid for 64-bit subtraction. */
1124
1125int
1126reg_or_sub_cint64_operand (op, mode)
592696dd 1127 rtx op;
2bfcf297
DB		 1128 enum machine_mode mode;
1129{
a4f6c312
SS		 1130 return (gpc_reg_operand (op, mode)
1131 || (GET_CODE (op) == CONST_INT
a65c591c 1132#if HOST_BITS_PER_WIDE_INT == 32
a4f6c312 1133 && (- INTVAL (op)) < 0x7fff8000
a65c591c 1134#else
a4f6c312
SS		 1135 && ((unsigned HOST_WIDE_INT) ((- INTVAL (op)) + 0x80008000)
1136 < 0x100000000ll)
2bfcf297 1137#endif
a4f6c312 1138 ));
2bfcf297
DB		 1139}
1140
9ebbca7d
GK		 1141/* Return 1 is the operand is either a non-special register or ANY
1142 32-bit unsigned constant integer. */
1143
1144int
1d328b19 1145reg_or_logical_cint_operand (op, mode)
592696dd 1146 rtx op;
9ebbca7d
GK		 1147 enum machine_mode mode;
1148{
1d328b19
GK		 1149 if (GET_CODE (op) == CONST_INT)
1150 {
1151 if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT)
1152 {
1153 if (GET_MODE_BITSIZE (mode) <= 32)
a4f6c312 1154 abort ();
1d328b19
GK		 1155
1156 if (INTVAL (op) < 0)
1157 return 0;
1158 }
1159
1160 return ((INTVAL (op) & GET_MODE_MASK (mode)
0858c623 1161 & (~ (unsigned HOST_WIDE_INT) 0xffffffff)) == 0);
1d328b19
GK		 1162 }
1163 else if (GET_CODE (op) == CONST_DOUBLE)
1164 {
1165 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
1166 || mode != DImode)
a4f6c312 1167 abort ();
1d328b19
GK		 1168
1169 return CONST_DOUBLE_HIGH (op) == 0;
1170 }
1171 else
1172 return gpc_reg_operand (op, mode);
9ebbca7d
GK		 1173}
1174
51d3e7d6 1175/* Return 1 if the operand is an operand that can be loaded via the GOT. */
766a866c
MM		 1176
1177int
1178got_operand (op, mode)
592696dd 1179 rtx op;
296b8152 1180 enum machine_mode mode ATTRIBUTE_UNUSED;
766a866c
MM		 1181{
1182 return (GET_CODE (op) == SYMBOL_REF
1183 || GET_CODE (op) == CONST
1184 || GET_CODE (op) == LABEL_REF);
1185}
1186
38c1f2d7
MM		 1187/* Return 1 if the operand is a simple references that can be loaded via
1188 the GOT (labels involving addition aren't allowed). */
1189
1190int
1191got_no_const_operand (op, mode)
592696dd 1192 rtx op;
296b8152 1193 enum machine_mode mode ATTRIBUTE_UNUSED;
38c1f2d7
MM		 1194{
1195 return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF);
1196}
1197
4e74d8ec
MM		 1198/* Return the number of instructions it takes to form a constant in an
1199 integer register. */
1200
1201static int
1202num_insns_constant_wide (value)
1203 HOST_WIDE_INT value;
1204{
1205 /* signed constant loadable with {cal|addi} */
5f59ecb7 1206 if (CONST_OK_FOR_LETTER_P (value, 'I'))
0865c631
GK		 1207 return 1;
1208
4e74d8ec 1209 /* constant loadable with {cau|addis} */
5f59ecb7 1210 else if (CONST_OK_FOR_LETTER_P (value, 'L'))
4e74d8ec
MM		 1211 return 1;
1212
5f59ecb7 1213#if HOST_BITS_PER_WIDE_INT == 64
c81fc13e 1214 else if (TARGET_POWERPC64)
4e74d8ec 1215 {
a65c591c
DE		 1216 HOST_WIDE_INT low = ((value & 0xffffffff) ^ 0x80000000) - 0x80000000;
1217 HOST_WIDE_INT high = value >> 31;
4e74d8ec 1218
a65c591c 1219 if (high == 0 || high == -1)
4e74d8ec
MM		 1220 return 2;
1221
a65c591c 1222 high >>= 1;
4e74d8ec 1223
a65c591c 1224 if (low == 0)
4e74d8ec 1225 return num_insns_constant_wide (high) + 1;
4e74d8ec
MM		 1226 else
1227 return (num_insns_constant_wide (high)
e396202a 1228 + num_insns_constant_wide (low) + 1);
4e74d8ec
MM		 1229 }
1230#endif
1231
1232 else
1233 return 2;
1234}
1235
1236int
1237num_insns_constant (op, mode)
1238 rtx op;
1239 enum machine_mode mode;
1240{
4e74d8ec 1241 if (GET_CODE (op) == CONST_INT)
0d30d435
DE		 1242 {
1243#if HOST_BITS_PER_WIDE_INT == 64
4e2c1c44
DE		 1244 if ((INTVAL (op) >> 31) != 0 && (INTVAL (op) >> 31) != -1
1245 && mask64_operand (op, mode))
0d30d435
DE		 1246 return 2;
1247 else
1248#endif
1249 return num_insns_constant_wide (INTVAL (op));
1250 }
4e74d8ec 1251
6fc48950
MM		 1252 else if (GET_CODE (op) == CONST_DOUBLE && mode == SFmode)
1253 {
1254 long l;
1255 REAL_VALUE_TYPE rv;
1256
1257 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
1258 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
e72247f4 1259 return num_insns_constant_wide ((HOST_WIDE_INT) l);
6fc48950
MM		 1260 }
1261
47ad8c61 1262 else if (GET_CODE (op) == CONST_DOUBLE)
4e74d8ec 1263 {
47ad8c61
MM		 1264 HOST_WIDE_INT low;
1265 HOST_WIDE_INT high;
1266 long l[2];
1267 REAL_VALUE_TYPE rv;
1268 int endian = (WORDS_BIG_ENDIAN == 0);
4e74d8ec 1269
47ad8c61
MM		 1270 if (mode == VOIDmode || mode == DImode)
1271 {
1272 high = CONST_DOUBLE_HIGH (op);
1273 low = CONST_DOUBLE_LOW (op);
1274 }
1275 else
1276 {
1277 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
1278 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
1279 high = l[endian];
1280 low = l[1 - endian];
1281 }
4e74d8ec 1282
47ad8c61
MM		 1283 if (TARGET_32BIT)
1284 return (num_insns_constant_wide (low)
1285 + num_insns_constant_wide (high));
4e74d8ec
MM		 1286
1287 else
47ad8c61 1288 {
e72247f4 1289 if (high == 0 && low >= 0)
47ad8c61
MM		 1290 return num_insns_constant_wide (low);
1291
e72247f4 1292 else if (high == -1 && low < 0)
47ad8c61
MM		 1293 return num_insns_constant_wide (low);
1294
a260abc9
DE		 1295 else if (mask64_operand (op, mode))
1296 return 2;
1297
47ad8c61
MM		 1298 else if (low == 0)
1299 return num_insns_constant_wide (high) + 1;
1300
1301 else
1302 return (num_insns_constant_wide (high)
1303 + num_insns_constant_wide (low) + 1);
1304 }
4e74d8ec
MM		 1305 }
1306
1307 else
1308 abort ();
1309}
1310
a4f6c312
SS		 1311/* Return 1 if the operand is a CONST_DOUBLE and it can be put into a
1312 register with one instruction per word. We only do this if we can
1313 safely read CONST_DOUBLE_{LOW,HIGH}. */
9878760c
RK		 1314
1315int
1316easy_fp_constant (op, mode)
592696dd
SS		 1317 rtx op;
1318 enum machine_mode mode;
9878760c 1319{
9878760c
RK		 1320 if (GET_CODE (op) != CONST_DOUBLE
1321 || GET_MODE (op) != mode
4e74d8ec 1322 || (GET_MODE_CLASS (mode) != MODE_FLOAT && mode != DImode))
9878760c
RK		 1323 return 0;
1324
a4f6c312 1325 /* Consider all constants with -msoft-float to be easy. */
a3170dc6
AH		 1326 if ((TARGET_SOFT_FLOAT || !TARGET_FPRS)
1327 && mode != DImode)
b6c9286a
MM		 1328 return 1;
1329
a4f6c312 1330 /* If we are using V.4 style PIC, consider all constants to be hard. */
f607bc57 1331 if (flag_pic && DEFAULT_ABI == ABI_V4)
a7273471
MM		 1332 return 0;
1333
5ae4759c 1334#ifdef TARGET_RELOCATABLE
a4f6c312
SS		 1335 /* Similarly if we are using -mrelocatable, consider all constants
1336 to be hard. */
5ae4759c
MM		 1337 if (TARGET_RELOCATABLE)
1338 return 0;
1339#endif
1340
fcce224d
DE		 1341 if (mode == TFmode)
1342 {
1343 long k[4];
1344 REAL_VALUE_TYPE rv;
1345
1346 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
1347 REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, k);
1348
1349 return (num_insns_constant_wide ((HOST_WIDE_INT) k[0]) == 1
1350 && num_insns_constant_wide ((HOST_WIDE_INT) k[1]) == 1
1351 && num_insns_constant_wide ((HOST_WIDE_INT) k[2]) == 1
1352 && num_insns_constant_wide ((HOST_WIDE_INT) k[3]) == 1);
1353 }
1354
1355 else if (mode == DFmode)
042259f2
DE		 1356 {
1357 long k[2];
1358 REAL_VALUE_TYPE rv;
1359
1360 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
1361 REAL_VALUE_TO_TARGET_DOUBLE (rv, k);
9878760c 1362
a65c591c
DE		 1363 return (num_insns_constant_wide ((HOST_WIDE_INT) k[0]) == 1
1364 && num_insns_constant_wide ((HOST_WIDE_INT) k[1]) == 1);
042259f2 1365 }
4e74d8ec
MM		 1366
1367 else if (mode == SFmode)
042259f2
DE		 1368 {
1369 long l;
1370 REAL_VALUE_TYPE rv;
1371
1372 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
1373 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
9878760c 1374
4e74d8ec 1375 return num_insns_constant_wide (l) == 1;
042259f2 1376 }
4e74d8ec 1377
a260abc9 1378 else if (mode == DImode)
c81fc13e 1379 return ((TARGET_POWERPC64
a260abc9
DE		 1380 && GET_CODE (op) == CONST_DOUBLE && CONST_DOUBLE_LOW (op) == 0)
1381 || (num_insns_constant (op, DImode) <= 2));
4e74d8ec 1382
a9098fd0
GK		 1383 else if (mode == SImode)
1384 return 1;
4e74d8ec
MM		 1385 else
1386 abort ();
9878760c 1387}
8f75773e 1388
69ef87e2
AH		 1389/* Return 1 if the operand is a CONST_INT and can be put into a
1390 register with one instruction. */
1391
1392static int
1393easy_vector_constant (op)
1394 rtx op;
1395{
1396 rtx elt;
1397 int units, i;
1398
1399 if (GET_CODE (op) != CONST_VECTOR)
1400 return 0;
1401
1402 units = CONST_VECTOR_NUNITS (op);
1403
1404 /* We can generate 0 easily. Look for that. */
1405 for (i = 0; i < units; ++i)
1406 {
1407 elt = CONST_VECTOR_ELT (op, i);
1408
1409 /* We could probably simplify this by just checking for equality
1410 with CONST0_RTX for the current mode, but let's be safe
1411 instead. */
1412
98ef3137
JJ		 1413 switch (GET_CODE (elt))
1414 {
1415 case CONST_INT:
1416 if (INTVAL (elt) != 0)
1417 return 0;
1418 break;
1419 case CONST_DOUBLE:
1420 if (CONST_DOUBLE_LOW (elt) != 0 || CONST_DOUBLE_HIGH (elt) != 0)
1421 return 0;
1422 break;
1423 default:
1424 return 0;
1425 }
69ef87e2
AH		 1426 }
1427
1428 /* We could probably generate a few other constants trivially, but
1429 gcc doesn't generate them yet. FIXME later. */
98ef3137 1430 return 1;
69ef87e2
AH		 1431}
1432
1433/* Return 1 if the operand is the constant 0. This works for scalars
1434 as well as vectors. */
1435int
1436zero_constant (op, mode)
1437 rtx op;
1438 enum machine_mode mode;
1439{
1440 return op == CONST0_RTX (mode);
1441}
1442
50a0b056
GK		 1443/* Return 1 if the operand is 0.0. */
1444int
1445zero_fp_constant (op, mode)
592696dd
SS		 1446 rtx op;
1447 enum machine_mode mode;
50a0b056
GK		 1448{
1449 return GET_MODE_CLASS (mode) == MODE_FLOAT && op == CONST0_RTX (mode);
1450}
1451
a4f6c312
SS		 1452/* Return 1 if the operand is in volatile memory. Note that during
1453 the RTL generation phase, memory_operand does not return TRUE for
b6c9286a
MM		 1454 volatile memory references. So this function allows us to
1455 recognize volatile references where its safe. */
1456
1457int
1458volatile_mem_operand (op, mode)
592696dd 1459 rtx op;
b6c9286a
MM		 1460 enum machine_mode mode;
1461{
1462 if (GET_CODE (op) != MEM)
1463 return 0;
1464
1465 if (!MEM_VOLATILE_P (op))
1466 return 0;
1467
1468 if (mode != GET_MODE (op))
1469 return 0;
1470
1471 if (reload_completed)
1472 return memory_operand (op, mode);
1473
1474 if (reload_in_progress)
1475 return strict_memory_address_p (mode, XEXP (op, 0));
1476
1477 return memory_address_p (mode, XEXP (op, 0));
1478}
1479
97f6e72f 1480/* Return 1 if the operand is an offsettable memory operand. */
914c2e77
RK		 1481
1482int
97f6e72f 1483offsettable_mem_operand (op, mode)
592696dd 1484 rtx op;
914c2e77
RK		 1485 enum machine_mode mode;
1486{
97f6e72f 1487 return ((GET_CODE (op) == MEM)
677a9668 1488 && offsettable_address_p (reload_completed || reload_in_progress,
97f6e72f 1489 mode, XEXP (op, 0)));
914c2e77
RK		 1490}
1491
9878760c
RK		 1492/* Return 1 if the operand is either an easy FP constant (see above) or
1493 memory. */
1494
1495int
1496mem_or_easy_const_operand (op, mode)
592696dd 1497 rtx op;
9878760c
RK		 1498 enum machine_mode mode;
1499{
1500 return memory_operand (op, mode) || easy_fp_constant (op, mode);
1501}
1502
1503/* Return 1 if the operand is either a non-special register or an item
5f59ecb7 1504 that can be used as the operand of a `mode' add insn. */
9878760c
RK		 1505
1506int
1507add_operand (op, mode)
592696dd 1508 rtx op;
9878760c
RK		 1509 enum machine_mode mode;
1510{
2bfcf297 1511 if (GET_CODE (op) == CONST_INT)
e72247f4
DE		 1512 return (CONST_OK_FOR_LETTER_P (INTVAL (op), 'I')
1513 || CONST_OK_FOR_LETTER_P (INTVAL (op), 'L'));
2bfcf297
DB		 1514
1515 return gpc_reg_operand (op, mode);
9878760c
RK		 1516}
1517
dcfedcd0
RK		 1518/* Return 1 if OP is a constant but not a valid add_operand. */
1519
1520int
1521non_add_cint_operand (op, mode)
592696dd 1522 rtx op;
296b8152 1523 enum machine_mode mode ATTRIBUTE_UNUSED;
dcfedcd0
RK		 1524{
1525 return (GET_CODE (op) == CONST_INT
e72247f4
DE		 1526 && !CONST_OK_FOR_LETTER_P (INTVAL (op), 'I')
1527 && !CONST_OK_FOR_LETTER_P (INTVAL (op), 'L'));
dcfedcd0
RK		 1528}
1529
9878760c
RK		 1530/* Return 1 if the operand is a non-special register or a constant that
1531 can be used as the operand of an OR or XOR insn on the RS/6000. */
1532
1533int
1534logical_operand (op, mode)
592696dd 1535 rtx op;
9878760c
RK		 1536 enum machine_mode mode;
1537{
40501e5f 1538 HOST_WIDE_INT opl, oph;
1d328b19 1539
dfbdccdb
GK		 1540 if (gpc_reg_operand (op, mode))
1541 return 1;
1d328b19 1542
dfbdccdb 1543 if (GET_CODE (op) == CONST_INT)
40501e5f
AM		 1544 {
1545 opl = INTVAL (op) & GET_MODE_MASK (mode);
1546
1547#if HOST_BITS_PER_WIDE_INT <= 32
1548 if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT && opl < 0)
1549 return 0;
1550#endif
1551 }
dfbdccdb
GK		 1552 else if (GET_CODE (op) == CONST_DOUBLE)
1553 {
1d328b19 1554 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
40501e5f 1555 abort ();
1d328b19
GK		 1556
1557 opl = CONST_DOUBLE_LOW (op);
1558 oph = CONST_DOUBLE_HIGH (op);
40501e5f 1559 if (oph != 0)
38886f37 1560 return 0;
dfbdccdb
GK		 1561 }
1562 else
1563 return 0;
1d328b19 1564
40501e5f
AM		 1565 return ((opl & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0
1566 || (opl & ~ (unsigned HOST_WIDE_INT) 0xffff0000) == 0);
9878760c
RK		 1567}
1568
dcfedcd0 1569/* Return 1 if C is a constant that is not a logical operand (as
1d328b19 1570 above), but could be split into one. */
dcfedcd0
RK		 1571
1572int
1573non_logical_cint_operand (op, mode)
592696dd 1574 rtx op;
5f59ecb7 1575 enum machine_mode mode;
dcfedcd0 1576{
dfbdccdb 1577 return ((GET_CODE (op) == CONST_INT || GET_CODE (op) == CONST_DOUBLE)
1d328b19
GK		 1578 && ! logical_operand (op, mode)
1579 && reg_or_logical_cint_operand (op, mode));
dcfedcd0
RK		 1580}
1581
19ba8161 1582/* Return 1 if C is a constant that can be encoded in a 32-bit mask on the
9878760c
RK		 1583 RS/6000. It is if there are no more than two 1->0 or 0->1 transitions.
1584 Reject all ones and all zeros, since these should have been optimized
1585 away and confuse the making of MB and ME. */
1586
1587int
19ba8161 1588mask_operand (op, mode)
592696dd 1589 rtx op;
19ba8161 1590 enum machine_mode mode ATTRIBUTE_UNUSED;
9878760c 1591{
02071907 1592 HOST_WIDE_INT c, lsb;
9878760c 1593
19ba8161
DE		 1594 if (GET_CODE (op) != CONST_INT)
1595 return 0;
1596
1597 c = INTVAL (op);
1598
57deb3a1
AM		 1599 /* Fail in 64-bit mode if the mask wraps around because the upper
1600 32-bits of the mask will all be 1s, contrary to GCC's internal view. */
1601 if (TARGET_POWERPC64 && (c & 0x80000001) == 0x80000001)
1602 return 0;
1603
c5059423
AM		 1604 /* We don't change the number of transitions by inverting,
1605 so make sure we start with the LS bit zero. */
1606 if (c & 1)
1607 c = ~c;
1608
1609 /* Reject all zeros or all ones. */
1610 if (c == 0)
9878760c
RK		 1611 return 0;
1612
c5059423
AM		 1613 /* Find the first transition. */
1614 lsb = c & -c;
1615
1616 /* Invert to look for a second transition. */
1617 c = ~c;
9878760c 1618
c5059423
AM		 1619 /* Erase first transition. */
1620 c &= -lsb;
9878760c 1621
c5059423
AM		 1622 /* Find the second transition (if any). */
1623 lsb = c & -c;
1624
1625 /* Match if all the bits above are 1's (or c is zero). */
1626 return c == -lsb;
9878760c
RK		 1627}
1628
0ba1b2ff
AM		 1629/* Return 1 for the PowerPC64 rlwinm corner case. */
1630
1631int
1632mask_operand_wrap (op, mode)
1633 rtx op;
1634 enum machine_mode mode ATTRIBUTE_UNUSED;
1635{
1636 HOST_WIDE_INT c, lsb;
1637
1638 if (GET_CODE (op) != CONST_INT)
1639 return 0;
1640
1641 c = INTVAL (op);
1642
1643 if ((c & 0x80000001) != 0x80000001)
1644 return 0;
1645
1646 c = ~c;
1647 if (c == 0)
1648 return 0;
1649
1650 lsb = c & -c;
1651 c = ~c;
1652 c &= -lsb;
1653 lsb = c & -c;
1654 return c == -lsb;
1655}
1656
a260abc9
DE		 1657/* Return 1 if the operand is a constant that is a PowerPC64 mask.
1658 It is if there are no more than one 1->0 or 0->1 transitions.
0ba1b2ff
AM		 1659 Reject all zeros, since zero should have been optimized away and
1660 confuses the making of MB and ME. */
9878760c
RK		 1661
1662int
a260abc9 1663mask64_operand (op, mode)
592696dd 1664 rtx op;
0ba1b2ff 1665 enum machine_mode mode ATTRIBUTE_UNUSED;
a260abc9
DE		 1666{
1667 if (GET_CODE (op) == CONST_INT)
1668 {
02071907 1669 HOST_WIDE_INT c, lsb;
a260abc9 1670
c5059423 1671 c = INTVAL (op);
a260abc9 1672
0ba1b2ff 1673 /* Reject all zeros. */
c5059423 1674 if (c == 0)
e2c953b6
DE		 1675 return 0;
1676
0ba1b2ff
AM		 1677 /* We don't change the number of transitions by inverting,
1678 so make sure we start with the LS bit zero. */
1679 if (c & 1)
1680 c = ~c;
1681
c5059423
AM		 1682 /* Find the transition, and check that all bits above are 1's. */
1683 lsb = c & -c;
e3981aab
DE		 1684
1685 /* Match if all the bits above are 1's (or c is zero). */
c5059423 1686 return c == -lsb;
e2c953b6 1687 }
0ba1b2ff
AM		 1688 return 0;
1689}
1690
1691/* Like mask64_operand, but allow up to three transitions. This
1692 predicate is used by insn patterns that generate two rldicl or
1693 rldicr machine insns. */
1694
1695int
1696mask64_2_operand (op, mode)
1697 rtx op;
1698 enum machine_mode mode ATTRIBUTE_UNUSED;
1699{
1700 if (GET_CODE (op) == CONST_INT)
a260abc9 1701 {
0ba1b2ff 1702 HOST_WIDE_INT c, lsb;
a260abc9 1703
0ba1b2ff 1704 c = INTVAL (op);
a260abc9 1705
0ba1b2ff
AM		 1706 /* Disallow all zeros. */
1707 if (c == 0)
1708 return 0;
a260abc9 1709
0ba1b2ff
AM		 1710 /* We don't change the number of transitions by inverting,
1711 so make sure we start with the LS bit zero. */
1712 if (c & 1)
1713 c = ~c;
a260abc9 1714
0ba1b2ff
AM		 1715 /* Find the first transition. */
1716 lsb = c & -c;
a260abc9 1717
0ba1b2ff
AM		 1718 /* Invert to look for a second transition. */
1719 c = ~c;
1720
1721 /* Erase first transition. */
1722 c &= -lsb;
1723
1724 /* Find the second transition. */
1725 lsb = c & -c;
1726
1727 /* Invert to look for a third transition. */
1728 c = ~c;
1729
1730 /* Erase second transition. */
1731 c &= -lsb;
1732
1733 /* Find the third transition (if any). */
1734 lsb = c & -c;
1735
1736 /* Match if all the bits above are 1's (or c is zero). */
1737 return c == -lsb;
1738 }
1739 return 0;
1740}
1741
1742/* Generates shifts and masks for a pair of rldicl or rldicr insns to
1743 implement ANDing by the mask IN. */
1744void
1745build_mask64_2_operands (in, out)
1746 rtx in;
1747 rtx *out;
1748{
1749#if HOST_BITS_PER_WIDE_INT >= 64
1750 unsigned HOST_WIDE_INT c, lsb, m1, m2;
1751 int shift;
1752
1753 if (GET_CODE (in) != CONST_INT)
1754 abort ();
1755
1756 c = INTVAL (in);
1757 if (c & 1)
1758 {
1759 /* Assume c initially something like 0x00fff000000fffff. The idea
1760 is to rotate the word so that the middle ^^^^^^ group of zeros
1761 is at the MS end and can be cleared with an rldicl mask. We then
1762 rotate back and clear off the MS ^^ group of zeros with a
1763 second rldicl. */
1764 c = ~c; /* c == 0xff000ffffff00000 */
1765 lsb = c & -c; /* lsb == 0x0000000000100000 */
1766 m1 = -lsb; /* m1 == 0xfffffffffff00000 */
1767 c = ~c; /* c == 0x00fff000000fffff */
1768 c &= -lsb; /* c == 0x00fff00000000000 */
1769 lsb = c & -c; /* lsb == 0x0000100000000000 */
1770 c = ~c; /* c == 0xff000fffffffffff */
1771 c &= -lsb; /* c == 0xff00000000000000 */
1772 shift = 0;
1773 while ((lsb >>= 1) != 0)
1774 shift++; /* shift == 44 on exit from loop */
1775 m1 <<= 64 - shift; /* m1 == 0xffffff0000000000 */
1776 m1 = ~m1; /* m1 == 0x000000ffffffffff */
1777 m2 = ~c; /* m2 == 0x00ffffffffffffff */
a260abc9
DE		 1778 }
1779 else
0ba1b2ff
AM		 1780 {
1781 /* Assume c initially something like 0xff000f0000000000. The idea
1782 is to rotate the word so that the ^^^ middle group of zeros
1783 is at the LS end and can be cleared with an rldicr mask. We then
1784 rotate back and clear off the LS group of ^^^^^^^^^^ zeros with
1785 a second rldicr. */
1786 lsb = c & -c; /* lsb == 0x0000010000000000 */
1787 m2 = -lsb; /* m2 == 0xffffff0000000000 */
1788 c = ~c; /* c == 0x00fff0ffffffffff */
1789 c &= -lsb; /* c == 0x00fff00000000000 */
1790 lsb = c & -c; /* lsb == 0x0000100000000000 */
1791 c = ~c; /* c == 0xff000fffffffffff */
1792 c &= -lsb; /* c == 0xff00000000000000 */
1793 shift = 0;
1794 while ((lsb >>= 1) != 0)
1795 shift++; /* shift == 44 on exit from loop */
1796 m1 = ~c; /* m1 == 0x00ffffffffffffff */
1797 m1 >>= shift; /* m1 == 0x0000000000000fff */
1798 m1 = ~m1; /* m1 == 0xfffffffffffff000 */
1799 }
1800
1801 /* Note that when we only have two 0->1 and 1->0 transitions, one of the
1802 masks will be all 1's. We are guaranteed more than one transition. */
1803 out[0] = GEN_INT (64 - shift);
1804 out[1] = GEN_INT (m1);
1805 out[2] = GEN_INT (shift);
1806 out[3] = GEN_INT (m2);
1807#else
045572c7
GK		 1808 (void)in;
1809 (void)out;
0ba1b2ff
AM		 1810 abort ();
1811#endif
a260abc9
DE		 1812}
1813
1814/* Return 1 if the operand is either a non-special register or a constant
1815 that can be used as the operand of a PowerPC64 logical AND insn. */
1816
1817int
1818and64_operand (op, mode)
592696dd 1819 rtx op;
9878760c
RK		 1820 enum machine_mode mode;
1821{
a4f6c312 1822 if (fixed_regs[CR0_REGNO]) /* CR0 not available, don't do andi./andis. */
52d3af72
DE		 1823 return (gpc_reg_operand (op, mode) || mask64_operand (op, mode));
1824
1825 return (logical_operand (op, mode) || mask64_operand (op, mode));
9878760c
RK		 1826}
1827
0ba1b2ff
AM		 1828/* Like the above, but also match constants that can be implemented
1829 with two rldicl or rldicr insns. */
1830
1831int
1832and64_2_operand (op, mode)
1833 rtx op;
1834 enum machine_mode mode;
1835{
1836 if (fixed_regs[CR0_REGNO]) /* CR0 not available, don't do andi./andis. */
1837 return gpc_reg_operand (op, mode) || mask64_2_operand (op, mode);
1838
1839 return logical_operand (op, mode) || mask64_2_operand (op, mode);
1840}
1841
a260abc9
DE		 1842/* Return 1 if the operand is either a non-special register or a
1843 constant that can be used as the operand of an RS/6000 logical AND insn. */
dcfedcd0
RK		 1844
1845int
a260abc9 1846and_operand (op, mode)
592696dd 1847 rtx op;
a260abc9 1848 enum machine_mode mode;
dcfedcd0 1849{
a4f6c312 1850 if (fixed_regs[CR0_REGNO]) /* CR0 not available, don't do andi./andis. */
52d3af72
DE		 1851 return (gpc_reg_operand (op, mode) || mask_operand (op, mode));
1852
1853 return (logical_operand (op, mode) || mask_operand (op, mode));
dcfedcd0
RK		 1854}
1855
9878760c
RK		 1856/* Return 1 if the operand is a general register or memory operand. */
1857
1858int
1859reg_or_mem_operand (op, mode)
592696dd
SS		 1860 rtx op;
1861 enum machine_mode mode;
9878760c 1862{
b6c9286a
MM		 1863 return (gpc_reg_operand (op, mode)
1864 || memory_operand (op, mode)
1865 || volatile_mem_operand (op, mode));
9878760c
RK		 1866}
1867
a7a813f7 1868/* Return 1 if the operand is a general register or memory operand without
3cb999d8 1869 pre_inc or pre_dec which produces invalid form of PowerPC lwa
a7a813f7
RK		 1870 instruction. */
1871
1872int
1873lwa_operand (op, mode)
592696dd
SS		 1874 rtx op;
1875 enum machine_mode mode;
a7a813f7
RK		 1876{
1877 rtx inner = op;
1878
1879 if (reload_completed && GET_CODE (inner) == SUBREG)
1880 inner = SUBREG_REG (inner);
1881
1882 return gpc_reg_operand (inner, mode)
1883 || (memory_operand (inner, mode)
1884 && GET_CODE (XEXP (inner, 0)) != PRE_INC
6a40a9d6
DE		 1885 && GET_CODE (XEXP (inner, 0)) != PRE_DEC
1886 && (GET_CODE (XEXP (inner, 0)) != PLUS
e903c96a
DE		 1887 || GET_CODE (XEXP (XEXP (inner, 0), 1)) != CONST_INT
1888 || INTVAL (XEXP (XEXP (inner, 0), 1)) % 4 == 0));
a7a813f7
RK		 1889}
1890
cc4d5fec
JH		 1891/* Return 1 if the operand, used inside a MEM, is a SYMBOL_REF. */
1892
1893int
1894symbol_ref_operand (op, mode)
1895 rtx op;
1896 enum machine_mode mode;
1897{
1898 if (mode != VOIDmode && GET_MODE (op) != mode)
1899 return 0;
1900
1901 return (GET_CODE (op) == SYMBOL_REF);
1902}
1903
9878760c 1904/* Return 1 if the operand, used inside a MEM, is a valid first argument
cc4d5fec 1905 to CALL. This is a SYMBOL_REF, a pseudo-register, LR or CTR. */
9878760c
RK		 1906
1907int
1908call_operand (op, mode)
592696dd 1909 rtx op;
9878760c
RK		 1910 enum machine_mode mode;
1911{
1912 if (mode != VOIDmode && GET_MODE (op) != mode)
1913 return 0;
1914
1915 return (GET_CODE (op) == SYMBOL_REF
cc4d5fec
JH		 1916 || (GET_CODE (op) == REG
1917 && (REGNO (op) == LINK_REGISTER_REGNUM
1918 || REGNO (op) == COUNT_REGISTER_REGNUM
1919 || REGNO (op) >= FIRST_PSEUDO_REGISTER)));
9878760c
RK		 1920}
1921
2af3d377 1922/* Return 1 if the operand is a SYMBOL_REF for a function known to be in
a4f6c312 1923 this file and the function is not weakly defined. */
2af3d377
RK		 1924
1925int
1926current_file_function_operand (op, mode)
592696dd 1927 rtx op;
296b8152 1928 enum machine_mode mode ATTRIBUTE_UNUSED;
2af3d377
RK		 1929{
1930 return (GET_CODE (op) == SYMBOL_REF
1931 && (SYMBOL_REF_FLAG (op)
8f1b829e 1932 || (op == XEXP (DECL_RTL (current_function_decl), 0)
c81fc13e 1933 && ! DECL_WEAK (current_function_decl))));
2af3d377
RK		 1934}
1935
9878760c
RK		 1936/* Return 1 if this operand is a valid input for a move insn. */
1937
1938int
1939input_operand (op, mode)
592696dd 1940 rtx op;
9878760c
RK		 1941 enum machine_mode mode;
1942{
eb4e8003 1943 /* Memory is always valid. */
9878760c
RK		 1944 if (memory_operand (op, mode))
1945 return 1;
1946
34792e82 1947 /* Only a tiny bit of handling for CONSTANT_P_RTX is necessary. */
01b4cf2b 1948 if (GET_CODE (op) == CONSTANT_P_RTX)
34792e82
JL		 1949 return 1;
1950
eb4e8003
RK		 1951 /* For floating-point, easy constants are valid. */
1952 if (GET_MODE_CLASS (mode) == MODE_FLOAT
1953 && CONSTANT_P (op)
1954 && easy_fp_constant (op, mode))
1955 return 1;
1956
4e74d8ec
MM		 1957 /* Allow any integer constant. */
1958 if (GET_MODE_CLASS (mode) == MODE_INT
e675f625 1959 && (GET_CODE (op) == CONST_INT
e675f625 1960 || GET_CODE (op) == CONST_DOUBLE))
4e74d8ec
MM		 1961 return 1;
1962
eb4e8003
RK		 1963 /* For floating-point or multi-word mode, the only remaining valid type
1964 is a register. */
9878760c
RK		 1965 if (GET_MODE_CLASS (mode) == MODE_FLOAT
1966 || GET_MODE_SIZE (mode) > UNITS_PER_WORD)
eb4e8003 1967 return register_operand (op, mode);
9878760c 1968
88fe15a1
RK		 1969 /* The only cases left are integral modes one word or smaller (we
1970 do not get called for MODE_CC values). These can be in any
1971 register. */
1972 if (register_operand (op, mode))
a8b3aeda 1973 return 1;
88fe15a1 1974
84cf9dda 1975 /* A SYMBOL_REF referring to the TOC is valid. */
7fec4abd 1976 if (LEGITIMATE_CONSTANT_POOL_ADDRESS_P (op))
84cf9dda
RK		 1977 return 1;
1978
9ebbca7d
GK		 1979 /* A constant pool expression (relative to the TOC) is valid */
1980 if (TOC_RELATIVE_EXPR_P (op))
b6c9286a
MM		 1981 return 1;
1982
88228c4b
MM		 1983 /* V.4 allows SYMBOL_REFs and CONSTs that are in the small data region
1984 to be valid. */
f607bc57 1985 if (DEFAULT_ABI == ABI_V4
88228c4b
MM		 1986 && (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST)
1987 && small_data_operand (op, Pmode))
1988 return 1;
1989
042259f2 1990 return 0;
9878760c 1991}
7509c759 1992
a4f6c312 1993/* Return 1 for an operand in small memory on V.4/eabi. */
7509c759
MM		 1994
1995int
1996small_data_operand (op, mode)
296b8152
KG		 1997 rtx op ATTRIBUTE_UNUSED;
1998 enum machine_mode mode ATTRIBUTE_UNUSED;
7509c759 1999{
38c1f2d7 2000#if TARGET_ELF
5f59ecb7 2001 rtx sym_ref;
7509c759 2002
d9407988 2003 if (rs6000_sdata == SDATA_NONE || rs6000_sdata == SDATA_DATA)
a54d04b7 2004 return 0;
a54d04b7 2005
f607bc57 2006 if (DEFAULT_ABI != ABI_V4)
7509c759
MM		 2007 return 0;
2008
88228c4b
MM		 2009 if (GET_CODE (op) == SYMBOL_REF)
2010 sym_ref = op;
2011
2012 else if (GET_CODE (op) != CONST
2013 || GET_CODE (XEXP (op, 0)) != PLUS
2014 || GET_CODE (XEXP (XEXP (op, 0), 0)) != SYMBOL_REF
2015 || GET_CODE (XEXP (XEXP (op, 0), 1)) != CONST_INT)
7509c759
MM		 2016 return 0;
2017
88228c4b 2018 else
dbf55e53
MM		 2019 {
2020 rtx sum = XEXP (op, 0);
2021 HOST_WIDE_INT summand;
2022
2023 /* We have to be careful here, because it is the referenced address
2024 that must be 32k from _SDA_BASE_, not just the symbol. */
2025 summand = INTVAL (XEXP (sum, 1));
2026 if (summand < 0 || summand > g_switch_value)
2027 return 0;
2028
2029 sym_ref = XEXP (sum, 0);
2030 }
88228c4b
MM		 2031
2032 if (*XSTR (sym_ref, 0) != '@')
7509c759
MM		 2033 return 0;
2034
2035 return 1;
d9407988
MM		 2036
2037#else
2038 return 0;
2039#endif
7509c759 2040}
9ebbca7d
GK		 2041\f
2042static int
2043constant_pool_expr_1 (op, have_sym, have_toc)
2044 rtx op;
2045 int *have_sym;
2046 int *have_toc;
2047{
2048 switch (GET_CODE(op))
2049 {
2050 case SYMBOL_REF:
a4f6c312
SS		 2051 if (CONSTANT_POOL_ADDRESS_P (op))
2052 {
2053 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (op), Pmode))
2054 {
2055 *have_sym = 1;
2056 return 1;
2057 }
2058 else
2059 return 0;
2060 }
2061 else if (! strcmp (XSTR (op, 0), toc_label_name))
2062 {
2063 *have_toc = 1;
2064 return 1;
2065 }
2066 else
2067 return 0;
9ebbca7d
GK		 2068 case PLUS:
2069 case MINUS:
c1f11548
DE		 2070 return (constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc)
2071 && constant_pool_expr_1 (XEXP (op, 1), have_sym, have_toc));
9ebbca7d 2072 case CONST:
a4f6c312 2073 return constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc);
9ebbca7d 2074 case CONST_INT:
a4f6c312 2075 return 1;
9ebbca7d 2076 default:
a4f6c312 2077 return 0;
9ebbca7d
GK		 2078 }
2079}
2080
2081int
2082constant_pool_expr_p (op)
2083 rtx op;
2084{
2085 int have_sym = 0;
2086 int have_toc = 0;
2087 return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_sym;
2088}
2089
2090int
2091toc_relative_expr_p (op)
2092 rtx op;
2093{
2094 int have_sym = 0;
2095 int have_toc = 0;
2096 return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_toc;
2097}
2098
2099/* Try machine-dependent ways of modifying an illegitimate address
2100 to be legitimate. If we find one, return the new, valid address.
2101 This is used from only one place: `memory_address' in explow.c.
2102
a4f6c312
SS		 2103 OLDX is the address as it was before break_out_memory_refs was
2104 called. In some cases it is useful to look at this to decide what
2105 needs to be done.
9ebbca7d 2106
a4f6c312 2107 MODE is passed so that this function can use GO_IF_LEGITIMATE_ADDRESS.
9ebbca7d 2108
a4f6c312
SS		 2109 It is always safe for this function to do nothing. It exists to
2110 recognize opportunities to optimize the output.
9ebbca7d
GK		 2111
2112 On RS/6000, first check for the sum of a register with a constant
2113 integer that is out of range. If so, generate code to add the
2114 constant with the low-order 16 bits masked to the register and force
2115 this result into another register (this can be done with `cau').
2116 Then generate an address of REG+(CONST&0xffff), allowing for the
2117 possibility of bit 16 being a one.
2118
2119 Then check for the sum of a register and something not constant, try to
2120 load the other things into a register and return the sum. */
2121rtx
2122rs6000_legitimize_address (x, oldx, mode)
2123 rtx x;
2124 rtx oldx ATTRIBUTE_UNUSED;
2125 enum machine_mode mode;
0ac081f6 2126{
9ebbca7d
GK		 2127 if (GET_CODE (x) == PLUS
2128 && GET_CODE (XEXP (x, 0)) == REG
2129 && GET_CODE (XEXP (x, 1)) == CONST_INT
2130 && (unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 1)) + 0x8000) >= 0x10000)
2131 {
2132 HOST_WIDE_INT high_int, low_int;
2133 rtx sum;
a65c591c
DE		 2134 low_int = ((INTVAL (XEXP (x, 1)) & 0xffff) ^ 0x8000) - 0x8000;
2135 high_int = INTVAL (XEXP (x, 1)) - low_int;
9ebbca7d
GK		 2136 sum = force_operand (gen_rtx_PLUS (Pmode, XEXP (x, 0),
2137 GEN_INT (high_int)), 0);
2138 return gen_rtx_PLUS (Pmode, sum, GEN_INT (low_int));
2139 }
2140 else if (GET_CODE (x) == PLUS
2141 && GET_CODE (XEXP (x, 0)) == REG
2142 && GET_CODE (XEXP (x, 1)) != CONST_INT
6ac7bf2c 2143 && GET_MODE_NUNITS (mode) == 1
a3170dc6
AH		 2144 && ((TARGET_HARD_FLOAT && TARGET_FPRS)
2145 || TARGET_POWERPC64
fcce224d 2146 || (mode != DFmode && mode != TFmode))
9ebbca7d
GK		 2147 && (TARGET_POWERPC64 || mode != DImode)
2148 && mode != TImode)
2149 {
2150 return gen_rtx_PLUS (Pmode, XEXP (x, 0),
2151 force_reg (Pmode, force_operand (XEXP (x, 1), 0)));
2152 }
0ac081f6
AH		 2153 else if (ALTIVEC_VECTOR_MODE (mode))
2154 {
2155 rtx reg;
2156
2157 /* Make sure both operands are registers. */
2158 if (GET_CODE (x) == PLUS)
9f85ed45 2159 return gen_rtx_PLUS (Pmode, force_reg (Pmode, XEXP (x, 0)),
0ac081f6
AH		 2160 force_reg (Pmode, XEXP (x, 1)));
2161
2162 reg = force_reg (Pmode, x);
2163 return reg;
2164 }
a3170dc6
AH		 2165 else if (SPE_VECTOR_MODE (mode))
2166 {
2167 /* We accept [reg + reg] and [reg + OFFSET]. */
2168
2169 if (GET_CODE (x) == PLUS)
2170 {
2171 rtx op1 = XEXP (x, 0);
2172 rtx op2 = XEXP (x, 1);
2173
2174 op1 = force_reg (Pmode, op1);
2175
2176 if (GET_CODE (op2) != REG
2177 && (GET_CODE (op2) != CONST_INT
2178 || !SPE_CONST_OFFSET_OK (INTVAL (op2))))
2179 op2 = force_reg (Pmode, op2);
2180
2181 return gen_rtx_PLUS (Pmode, op1, op2);
2182 }
2183
2184 return force_reg (Pmode, x);
2185 }
9ebbca7d
GK		 2186 else if (TARGET_ELF && TARGET_32BIT && TARGET_NO_TOC && ! flag_pic
2187 && GET_CODE (x) != CONST_INT
2188 && GET_CODE (x) != CONST_DOUBLE
2189 && CONSTANT_P (x)
6ac7bf2c
GK		 2190 && GET_MODE_NUNITS (mode) == 1
2191 && (GET_MODE_BITSIZE (mode) <= 32
a3170dc6 2192 || ((TARGET_HARD_FLOAT && TARGET_FPRS) && mode == DFmode)))
9ebbca7d
GK		 2193 {
2194 rtx reg = gen_reg_rtx (Pmode);
2195 emit_insn (gen_elf_high (reg, (x)));
2196 return gen_rtx_LO_SUM (Pmode, reg, (x));
2197 }
ee890fe2
SS		 2198 else if (TARGET_MACHO && TARGET_32BIT && TARGET_NO_TOC
2199 && ! flag_pic
2200 && GET_CODE (x) != CONST_INT
2201 && GET_CODE (x) != CONST_DOUBLE
2202 && CONSTANT_P (x)
a3170dc6 2203 && ((TARGET_HARD_FLOAT && TARGET_FPRS) || mode != DFmode)
ee890fe2
SS		 2204 && mode != DImode
2205 && mode != TImode)
2206 {
2207 rtx reg = gen_reg_rtx (Pmode);
2208 emit_insn (gen_macho_high (reg, (x)));
2209 return gen_rtx_LO_SUM (Pmode, reg, (x));
2210 }
9ebbca7d
GK		 2211 else if (TARGET_TOC
2212 && CONSTANT_POOL_EXPR_P (x)
a9098fd0 2213 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), Pmode))
9ebbca7d
GK		 2214 {
2215 return create_TOC_reference (x);
2216 }
2217 else
2218 return NULL_RTX;
2219}
258bfae2 2220
24ea750e
DJ		 2221/* The convention appears to be to define this wherever it is used.
2222 With legitimize_reload_address now defined here, REG_MODE_OK_FOR_BASE_P
2223 is now used here. */
2224#ifndef REG_MODE_OK_FOR_BASE_P
2225#define REG_MODE_OK_FOR_BASE_P(REGNO, MODE) REG_OK_FOR_BASE_P (REGNO)
2226#endif
2227
2228/* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
2229 replace the input X, or the original X if no replacement is called for.
2230 The output parameter *WIN is 1 if the calling macro should goto WIN,
2231 0 if it should not.
2232
2233 For RS/6000, we wish to handle large displacements off a base
2234 register by splitting the addend across an addiu/addis and the mem insn.
2235 This cuts number of extra insns needed from 3 to 1.
2236
2237 On Darwin, we use this to generate code for floating point constants.
2238 A movsf_low is generated so we wind up with 2 instructions rather than 3.
2239 The Darwin code is inside #if TARGET_MACHO because only then is
2240 machopic_function_base_name() defined. */
2241rtx
2242rs6000_legitimize_reload_address (x, mode, opnum, type, ind_levels, win)
2243 rtx x;
2244 enum machine_mode mode;
2245 int opnum;
2246 int type;
2247 int ind_levels ATTRIBUTE_UNUSED;
2248 int *win;
2249{
2250 /* We must recognize output that we have already generated ourselves. */
2251 if (GET_CODE (x) == PLUS
2252 && GET_CODE (XEXP (x, 0)) == PLUS
2253 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
2254 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2255 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2256 {
2257 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
2258 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
2259 opnum, (enum reload_type)type);
2260 *win = 1;
2261 return x;
2262 }
3deb2758 2263
24ea750e
DJ		 2264#if TARGET_MACHO
2265 if (DEFAULT_ABI == ABI_DARWIN && flag_pic
2266 && GET_CODE (x) == LO_SUM
2267 && GET_CODE (XEXP (x, 0)) == PLUS
2268 && XEXP (XEXP (x, 0), 0) == pic_offset_table_rtx
2269 && GET_CODE (XEXP (XEXP (x, 0), 1)) == HIGH
2270 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 1), 0)) == CONST
2271 && XEXP (XEXP (XEXP (x, 0), 1), 0) == XEXP (x, 1)
2272 && GET_CODE (XEXP (XEXP (x, 1), 0)) == MINUS
2273 && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 0)) == SYMBOL_REF
2274 && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 1)) == SYMBOL_REF)
2275 {
2276 /* Result of previous invocation of this function on Darwin
6f317ef3 2277 floating point constant. */
24ea750e
DJ		 2278 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
2279 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
2280 opnum, (enum reload_type)type);
2281 *win = 1;
2282 return x;
2283 }
2284#endif
2285 if (GET_CODE (x) == PLUS
2286 && GET_CODE (XEXP (x, 0)) == REG
2287 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2288 && REG_MODE_OK_FOR_BASE_P (XEXP (x, 0), mode)
78c875e8 2289 && GET_CODE (XEXP (x, 1)) == CONST_INT
93638d7a 2290 && !SPE_VECTOR_MODE (mode)
78c875e8 2291 && !ALTIVEC_VECTOR_MODE (mode))
24ea750e
DJ		 2292 {
2293 HOST_WIDE_INT val = INTVAL (XEXP (x, 1));
2294 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
2295 HOST_WIDE_INT high
2296 = (((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000;
2297
2298 /* Check for 32-bit overflow. */
2299 if (high + low != val)
2300 {
2301 *win = 0;
2302 return x;
2303 }
2304
2305 /* Reload the high part into a base reg; leave the low part
2306 in the mem directly. */
2307
2308 x = gen_rtx_PLUS (GET_MODE (x),
2309 gen_rtx_PLUS (GET_MODE (x), XEXP (x, 0),
2310 GEN_INT (high)),
2311 GEN_INT (low));
2312
2313 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
2314 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
2315 opnum, (enum reload_type)type);
2316 *win = 1;
2317 return x;
2318 }
2319#if TARGET_MACHO
2320 if (GET_CODE (x) == SYMBOL_REF
2321 && DEFAULT_ABI == ABI_DARWIN
69ef87e2 2322 && !ALTIVEC_VECTOR_MODE (mode)
24ea750e
DJ		 2323 && flag_pic)
2324 {
2325 /* Darwin load of floating point constant. */
2326 rtx offset = gen_rtx (CONST, Pmode,
2327 gen_rtx (MINUS, Pmode, x,
2328 gen_rtx (SYMBOL_REF, Pmode,
2329 machopic_function_base_name ())));
2330 x = gen_rtx (LO_SUM, GET_MODE (x),
2331 gen_rtx (PLUS, Pmode, pic_offset_table_rtx,
2332 gen_rtx (HIGH, Pmode, offset)), offset);
2333 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
2334 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
2335 opnum, (enum reload_type)type);
2336 *win = 1;
2337 return x;
2338 }
2339#endif
2340 if (TARGET_TOC
c1f11548
DE		 2341 && CONSTANT_POOL_EXPR_P (x)
2342 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), mode))
24ea750e
DJ		 2343 {
2344 (x) = create_TOC_reference (x);
2345 *win = 1;
2346 return x;
2347 }
2348 *win = 0;
2349 return x;
2350}
2351
258bfae2
FS		 2352/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
2353 that is a valid memory address for an instruction.
2354 The MODE argument is the machine mode for the MEM expression
2355 that wants to use this address.
2356
2357 On the RS/6000, there are four valid address: a SYMBOL_REF that
2358 refers to a constant pool entry of an address (or the sum of it
2359 plus a constant), a short (16-bit signed) constant plus a register,
2360 the sum of two registers, or a register indirect, possibly with an
5bdc5878 2361 auto-increment. For DFmode and DImode with a constant plus register,
258bfae2
FS		 2362 we must ensure that both words are addressable or PowerPC64 with offset
2363 word aligned.
2364
2365 For modes spanning multiple registers (DFmode in 32-bit GPRs,
2366 32-bit DImode, TImode), indexed addressing cannot be used because
2367 adjacent memory cells are accessed by adding word-sized offsets
2368 during assembly output. */
2369int
2370rs6000_legitimate_address (mode, x, reg_ok_strict)
2371 enum machine_mode mode;
2372 rtx x;
2373 int reg_ok_strict;
2374{
2375 if (LEGITIMATE_INDIRECT_ADDRESS_P (x, reg_ok_strict))
2376 return 1;
2377 if ((GET_CODE (x) == PRE_INC || GET_CODE (x) == PRE_DEC)
0d6d6892 2378 && !ALTIVEC_VECTOR_MODE (mode)
a3170dc6 2379 && !SPE_VECTOR_MODE (mode)
258bfae2
FS		 2380 && TARGET_UPDATE
2381 && LEGITIMATE_INDIRECT_ADDRESS_P (XEXP (x, 0), reg_ok_strict))
2382 return 1;
2383 if (LEGITIMATE_SMALL_DATA_P (mode, x))
2384 return 1;
2385 if (LEGITIMATE_CONSTANT_POOL_ADDRESS_P (x))
2386 return 1;
2387 /* If not REG_OK_STRICT (before reload) let pass any stack offset. */
2388 if (! reg_ok_strict
2389 && GET_CODE (x) == PLUS
2390 && GET_CODE (XEXP (x, 0)) == REG
2391 && XEXP (x, 0) == virtual_stack_vars_rtx
2392 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2393 return 1;
2394 if (LEGITIMATE_OFFSET_ADDRESS_P (mode, x, reg_ok_strict))
2395 return 1;
2396 if (mode != TImode
a3170dc6
AH		 2397 && ((TARGET_HARD_FLOAT && TARGET_FPRS)
2398 || TARGET_POWERPC64
fcce224d 2399 || (mode != DFmode && mode != TFmode))
258bfae2
FS		 2400 && (TARGET_POWERPC64 || mode != DImode)
2401 && LEGITIMATE_INDEXED_ADDRESS_P (x, reg_ok_strict))
2402 return 1;
2403 if (LEGITIMATE_LO_SUM_ADDRESS_P (mode, x, reg_ok_strict))
2404 return 1;
2405 return 0;
2406}
fb4d4348 2407\f
a4f6c312
SS		 2408/* Try to output insns to set TARGET equal to the constant C if it can
2409 be done in less than N insns. Do all computations in MODE.
2410 Returns the place where the output has been placed if it can be
2411 done and the insns have been emitted. If it would take more than N
2412 insns, zero is returned and no insns and emitted. */
2bfcf297
DB		 2413
2414rtx
2415rs6000_emit_set_const (dest, mode, source, n)
2416 rtx dest, source;
2417 enum machine_mode mode;
2418 int n ATTRIBUTE_UNUSED;
2419{
af8cb5c5 2420 rtx result, insn, set;
2bfcf297
DB		 2421 HOST_WIDE_INT c0, c1;
2422
af8cb5c5 2423 if (mode == QImode || mode == HImode)
2bfcf297
DB		 2424 {
2425 if (dest == NULL)
2426 dest = gen_reg_rtx (mode);
2427 emit_insn (gen_rtx_SET (VOIDmode, dest, source));
2428 return dest;
2429 }
af8cb5c5 2430 else if (mode == SImode)
2bfcf297 2431 {
af8cb5c5
DE		 2432 result = no_new_pseudos ? dest : gen_reg_rtx (SImode);
2433
2434 emit_insn (gen_rtx_SET (VOIDmode, result,
2435 GEN_INT (INTVAL (source)
2436 & (~ (HOST_WIDE_INT) 0xffff))));
2437 emit_insn (gen_rtx_SET (VOIDmode, dest,
2438 gen_rtx_IOR (SImode, result,
2439 GEN_INT (INTVAL (source) & 0xffff))));
2440 result = dest;
2bfcf297 2441 }
af8cb5c5 2442 else if (mode == DImode)
2bfcf297 2443 {
af8cb5c5
DE		 2444 if (GET_CODE (source) == CONST_INT)
2445 {
2446 c0 = INTVAL (source);
2447 c1 = -(c0 < 0);
2448 }
2449 else if (GET_CODE (source) == CONST_DOUBLE)
2450 {
2bfcf297 2451#if HOST_BITS_PER_WIDE_INT >= 64
af8cb5c5
DE		 2452 c0 = CONST_DOUBLE_LOW (source);
2453 c1 = -(c0 < 0);
2bfcf297 2454#else
af8cb5c5
DE		 2455 c0 = CONST_DOUBLE_LOW (source);
2456 c1 = CONST_DOUBLE_HIGH (source);
2bfcf297 2457#endif
af8cb5c5
DE		 2458 }
2459 else
2460 abort ();
2461
2462 result = rs6000_emit_set_long_const (dest, c0, c1);
2bfcf297
DB		 2463 }
2464 else
a4f6c312 2465 abort ();
2bfcf297 2466
af8cb5c5
DE		 2467 insn = get_last_insn ();
2468 set = single_set (insn);
2469 if (! CONSTANT_P (SET_SRC (set)))
2470 set_unique_reg_note (insn, REG_EQUAL, source);
2471
2472 return result;
2bfcf297
DB		 2473}
2474
2475/* Having failed to find a 3 insn sequence in rs6000_emit_set_const,
2476 fall back to a straight forward decomposition. We do this to avoid
2477 exponential run times encountered when looking for longer sequences
2478 with rs6000_emit_set_const. */
2479static rtx
2480rs6000_emit_set_long_const (dest, c1, c2)
2481 rtx dest;
2482 HOST_WIDE_INT c1, c2;
2483{
2484 if (!TARGET_POWERPC64)
2485 {
2486 rtx operand1, operand2;
2487
2488 operand1 = operand_subword_force (dest, WORDS_BIG_ENDIAN == 0,
2489 DImode);
2490 operand2 = operand_subword_force (dest, WORDS_BIG_ENDIAN != 0,
2491 DImode);
2492 emit_move_insn (operand1, GEN_INT (c1));
2493 emit_move_insn (operand2, GEN_INT (c2));
2494 }
2495 else
2496 {
bc06712d 2497 HOST_WIDE_INT ud1, ud2, ud3, ud4;
252b88f7 2498
bc06712d
TR		 2499 ud1 = c1 & 0xffff;
2500 ud2 = (c1 & 0xffff0000) >> 16;
2bfcf297 2501#if HOST_BITS_PER_WIDE_INT >= 64
bc06712d 2502 c2 = c1 >> 32;
2bfcf297 2503#endif
bc06712d
TR		 2504 ud3 = c2 & 0xffff;
2505 ud4 = (c2 & 0xffff0000) >> 16;
2bfcf297 2506
bc06712d
TR		 2507 if ((ud4 == 0xffff && ud3 == 0xffff && ud2 == 0xffff && (ud1 & 0x8000))
2508 || (ud4 == 0 && ud3 == 0 && ud2 == 0 && ! (ud1 & 0x8000)))
2bfcf297 2509 {
bc06712d
TR		 2510 if (ud1 & 0x8000)
2511 emit_move_insn (dest, GEN_INT (((ud1 ^ 0x8000) - 0x8000)));
2512 else
2513 emit_move_insn (dest, GEN_INT (ud1));
2bfcf297 2514 }
2bfcf297 2515
bc06712d
TR		 2516 else if ((ud4 == 0xffff && ud3 == 0xffff && (ud2 & 0x8000))
2517 || (ud4 == 0 && ud3 == 0 && ! (ud2 & 0x8000)))
252b88f7 2518 {
bc06712d
TR		 2519 if (ud2 & 0x8000)
2520 emit_move_insn (dest, GEN_INT (((ud2 << 16) ^ 0x80000000)
2521 - 0x80000000));
252b88f7 2522 else
bc06712d
TR		 2523 emit_move_insn (dest, GEN_INT (ud2 << 16));
2524 if (ud1 != 0)
2525 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1)));
252b88f7 2526 }
bc06712d
TR		 2527 else if ((ud4 == 0xffff && (ud3 & 0x8000))
2528 || (ud4 == 0 && ! (ud3 & 0x8000)))
2529 {
2530 if (ud3 & 0x8000)
2531 emit_move_insn (dest, GEN_INT (((ud3 << 16) ^ 0x80000000)
2532 - 0x80000000));
2533 else
2534 emit_move_insn (dest, GEN_INT (ud3 << 16));
2535
2536 if (ud2 != 0)
2537 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud2)));
2538 emit_move_insn (dest, gen_rtx_ASHIFT (DImode, dest, GEN_INT (16)));
2539 if (ud1 != 0)
2540 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1)));
2541 }
2542 else
2543 {
2544 if (ud4 & 0x8000)
2545 emit_move_insn (dest, GEN_INT (((ud4 << 16) ^ 0x80000000)
2546 - 0x80000000));
2547 else
2548 emit_move_insn (dest, GEN_INT (ud4 << 16));
2549
2550 if (ud3 != 0)
2551 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud3)));
2bfcf297 2552
bc06712d
TR		 2553 emit_move_insn (dest, gen_rtx_ASHIFT (DImode, dest, GEN_INT (32)));
2554 if (ud2 != 0)
2555 emit_move_insn (dest, gen_rtx_IOR (DImode, dest,
2556 GEN_INT (ud2 << 16)));
2557 if (ud1 != 0)
2558 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1)));
2559 }
2560 }
2bfcf297
DB		 2561 return dest;
2562}
2563
fb4d4348
GK		 2564/* Emit a move from SOURCE to DEST in mode MODE. */
2565void
2566rs6000_emit_move (dest, source, mode)
2567 rtx dest;
2568 rtx source;
2569 enum machine_mode mode;
2570{
2571 rtx operands[2];
2572 operands[0] = dest;
2573 operands[1] = source;
2574
2575 /* Sanity checks. Check that we get CONST_DOUBLE only when we should. */
2576 if (GET_CODE (operands[1]) == CONST_DOUBLE
2577 && ! FLOAT_MODE_P (mode)
2578 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
2579 {
2580 /* FIXME. This should never happen. */
2581 /* Since it seems that it does, do the safe thing and convert
2582 to a CONST_INT. */
2496c7bd 2583 operands[1] = gen_int_mode (CONST_DOUBLE_LOW (operands[1]), mode);
fb4d4348
GK		 2584 }
2585 if (GET_CODE (operands[1]) == CONST_DOUBLE
2586 && ! FLOAT_MODE_P (mode)
2587 && ((CONST_DOUBLE_HIGH (operands[1]) == 0
2588 && CONST_DOUBLE_LOW (operands[1]) >= 0)
2589 || (CONST_DOUBLE_HIGH (operands[1]) == -1
2590 && CONST_DOUBLE_LOW (operands[1]) < 0)))
2591 abort ();
c9e8cb32
DD		 2592
2593 /* Check if GCC is setting up a block move that will end up using FP
2594 registers as temporaries. We must make sure this is acceptable. */
2595 if (GET_CODE (operands[0]) == MEM
2596 && GET_CODE (operands[1]) == MEM
2597 && mode == DImode
41543739
GK		 2598 && (SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[0]))
2599 || SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[1])))
2600 && ! (SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[0]) > 32
2601 ? 32 : MEM_ALIGN (operands[0])))
2602 || SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[1]) > 32
2603 ? 32
2604 : MEM_ALIGN (operands[1]))))
2605 && ! MEM_VOLATILE_P (operands [0])
2606 && ! MEM_VOLATILE_P (operands [1]))
c9e8cb32 2607 {
41543739
GK		 2608 emit_move_insn (adjust_address (operands[0], SImode, 0),
2609 adjust_address (operands[1], SImode, 0));
2610 emit_move_insn (adjust_address (operands[0], SImode, 4),
2611 adjust_address (operands[1], SImode, 4));
c9e8cb32
DD		 2612 return;
2613 }
fb4d4348 2614
67cef334
DE		 2615 if (!no_new_pseudos)
2616 {
2617 if (GET_CODE (operands[1]) == MEM && optimize > 0
2618 && (mode == QImode || mode == HImode || mode == SImode)
2619 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (word_mode))
2620 {
2621 rtx reg = gen_reg_rtx (word_mode);
2622
2623 emit_insn (gen_rtx_SET (word_mode, reg,
2624 gen_rtx_ZERO_EXTEND (word_mode,
2625 operands[1])));
2626 operands[1] = gen_lowpart (mode, reg);
2627 }
2628 if (GET_CODE (operands[0]) != REG)
2629 operands[1] = force_reg (mode, operands[1]);
2630 }
a9098fd0 2631
a3170dc6
AH		 2632 if (mode == SFmode && ! TARGET_POWERPC
2633 && TARGET_HARD_FLOAT && TARGET_FPRS
ffc14f31 2634 && GET_CODE (operands[0]) == MEM)
fb4d4348 2635 {
ffc14f31
GK		 2636 int regnum;
2637
2638 if (reload_in_progress || reload_completed)
2639 regnum = true_regnum (operands[1]);
2640 else if (GET_CODE (operands[1]) == REG)
2641 regnum = REGNO (operands[1]);
2642 else
2643 regnum = -1;
fb4d4348
GK		 2644
2645 /* If operands[1] is a register, on POWER it may have
2646 double-precision data in it, so truncate it to single
2647 precision. */
2648 if (FP_REGNO_P (regnum) || regnum >= FIRST_PSEUDO_REGISTER)
2649 {
2650 rtx newreg;
2651 newreg = (no_new_pseudos ? operands[1] : gen_reg_rtx (mode));
2652 emit_insn (gen_aux_truncdfsf2 (newreg, operands[1]));
2653 operands[1] = newreg;
2654 }
2655 }
2656
a9098fd0
GK		 2657 /* Handle the case where reload calls us with an invalid address;
2658 and the case of CONSTANT_P_RTX. */
16861f33 2659 if (!ALTIVEC_VECTOR_MODE (mode)
69ef87e2
AH		 2660 && (! general_operand (operands[1], mode)
2661 || ! nonimmediate_operand (operands[0], mode)
2662 || GET_CODE (operands[1]) == CONSTANT_P_RTX))
fb4d4348
GK		 2663 {
2664 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
2665 return;
2666 }
a9098fd0 2667
fb4d4348
GK		 2668 /* FIXME: In the long term, this switch statement should go away
2669 and be replaced by a sequence of tests based on things like
2670 mode == Pmode. */
2671 switch (mode)
2672 {
2673 case HImode:
2674 case QImode:
2675 if (CONSTANT_P (operands[1])
2676 && GET_CODE (operands[1]) != CONST_INT)
a9098fd0 2677 operands[1] = force_const_mem (mode, operands[1]);
fb4d4348
GK		 2678 break;
2679
06f4e019 2680 case TFmode:
fb4d4348
GK		 2681 case DFmode:
2682 case SFmode:
2683 if (CONSTANT_P (operands[1])
2684 && ! easy_fp_constant (operands[1], mode))
a9098fd0 2685 operands[1] = force_const_mem (mode, operands[1]);
fb4d4348
GK		 2686 break;
2687
0ac081f6
AH		 2688 case V16QImode:
2689 case V8HImode:
2690 case V4SFmode:
2691 case V4SImode:
a3170dc6
AH		 2692 case V4HImode:
2693 case V2SFmode:
2694 case V2SImode:
00a892b8 2695 case V1DImode:
69ef87e2
AH		 2696 if (CONSTANT_P (operands[1])
2697 && !easy_vector_constant (operands[1]))
0ac081f6
AH		 2698 operands[1] = force_const_mem (mode, operands[1]);
2699 break;
2700
fb4d4348 2701 case SImode:
a9098fd0 2702 case DImode:
fb4d4348
GK		 2703 /* Use default pattern for address of ELF small data */
2704 if (TARGET_ELF
a9098fd0 2705 && mode == Pmode
f607bc57 2706 && DEFAULT_ABI == ABI_V4
a9098fd0
GK		 2707 && (GET_CODE (operands[1]) == SYMBOL_REF
2708 || GET_CODE (operands[1]) == CONST)
2709 && small_data_operand (operands[1], mode))
fb4d4348
GK		 2710 {
2711 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
2712 return;
2713 }
2714
f607bc57 2715 if (DEFAULT_ABI == ABI_V4
a9098fd0
GK		 2716 && mode == Pmode && mode == SImode
2717 && flag_pic == 1 && got_operand (operands[1], mode))
fb4d4348
GK		 2718 {
2719 emit_insn (gen_movsi_got (operands[0], operands[1]));
2720 return;
2721 }
2722
ee890fe2
SS		 2723 if ((TARGET_ELF || DEFAULT_ABI == ABI_DARWIN)
2724 && TARGET_NO_TOC && ! flag_pic
a9098fd0 2725 && mode == Pmode
fb4d4348
GK		 2726 && CONSTANT_P (operands[1])
2727 && GET_CODE (operands[1]) != HIGH
2728 && GET_CODE (operands[1]) != CONST_INT)
2729 {
a9098fd0 2730 rtx target = (no_new_pseudos ? operands[0] : gen_reg_rtx (mode));
fb4d4348
GK		 2731
2732 /* If this is a function address on -mcall-aixdesc,
2733 convert it to the address of the descriptor. */
2734 if (DEFAULT_ABI == ABI_AIX
2735 && GET_CODE (operands[1]) == SYMBOL_REF
2736 && XSTR (operands[1], 0)[0] == '.')
2737 {
2738 const char *name = XSTR (operands[1], 0);
2739 rtx new_ref;
2740 while (*name == '.')
2741 name++;
2742 new_ref = gen_rtx_SYMBOL_REF (Pmode, name);
2743 CONSTANT_POOL_ADDRESS_P (new_ref)
2744 = CONSTANT_POOL_ADDRESS_P (operands[1]);
2745 SYMBOL_REF_FLAG (new_ref) = SYMBOL_REF_FLAG (operands[1]);
2746 SYMBOL_REF_USED (new_ref) = SYMBOL_REF_USED (operands[1]);
2747 operands[1] = new_ref;
2748 }
7509c759 2749
ee890fe2
SS		 2750 if (DEFAULT_ABI == ABI_DARWIN)
2751 {
2752 emit_insn (gen_macho_high (target, operands[1]));
2753 emit_insn (gen_macho_low (operands[0], target, operands[1]));
2754 return;
2755 }
2756
fb4d4348
GK		 2757 emit_insn (gen_elf_high (target, operands[1]));
2758 emit_insn (gen_elf_low (operands[0], target, operands[1]));
2759 return;
2760 }
2761
a9098fd0
GK		 2762 /* If this is a SYMBOL_REF that refers to a constant pool entry,
2763 and we have put it in the TOC, we just need to make a TOC-relative
2764 reference to it. */
2765 if (TARGET_TOC
2766 && GET_CODE (operands[1]) == SYMBOL_REF
2767 && CONSTANT_POOL_EXPR_P (operands[1])
2768 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (operands[1]),
2769 get_pool_mode (operands[1])))
fb4d4348 2770 {
a9098fd0 2771 operands[1] = create_TOC_reference (operands[1]);
fb4d4348 2772 }
a9098fd0
GK		 2773 else if (mode == Pmode
2774 && CONSTANT_P (operands[1])
38886f37
AO		 2775 && ((GET_CODE (operands[1]) != CONST_INT
2776 && ! easy_fp_constant (operands[1], mode))
2777 || (GET_CODE (operands[1]) == CONST_INT
2778 && num_insns_constant (operands[1], mode) > 2)
2779 || (GET_CODE (operands[0]) == REG
2780 && FP_REGNO_P (REGNO (operands[0]))))
a9098fd0
GK		 2781 && GET_CODE (operands[1]) != HIGH
2782 && ! LEGITIMATE_CONSTANT_POOL_ADDRESS_P (operands[1])
2783 && ! TOC_RELATIVE_EXPR_P (operands[1]))
fb4d4348
GK		 2784 {
2785 /* Emit a USE operation so that the constant isn't deleted if
2786 expensive optimizations are turned on because nobody
2787 references it. This should only be done for operands that
2788 contain SYMBOL_REFs with CONSTANT_POOL_ADDRESS_P set.
2789 This should not be done for operands that contain LABEL_REFs.
2790 For now, we just handle the obvious case. */
2791 if (GET_CODE (operands[1]) != LABEL_REF)
2792 emit_insn (gen_rtx_USE (VOIDmode, operands[1]));
2793
c859cda6 2794#if TARGET_MACHO
ee890fe2
SS		 2795 /* Darwin uses a special PIC legitimizer. */
2796 if (DEFAULT_ABI == ABI_DARWIN && flag_pic)
2797 {
ee890fe2
SS		 2798 operands[1] =
2799 rs6000_machopic_legitimize_pic_address (operands[1], mode,
c859cda6
DJ		 2800 operands[0]);
2801 if (operands[0] != operands[1])
2802 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
ee890fe2
SS		 2803 return;
2804 }
c859cda6 2805#endif
ee890fe2 2806
fb4d4348
GK		 2807 /* If we are to limit the number of things we put in the TOC and
2808 this is a symbol plus a constant we can add in one insn,
2809 just put the symbol in the TOC and add the constant. Don't do
2810 this if reload is in progress. */
2811 if (GET_CODE (operands[1]) == CONST
2812 && TARGET_NO_SUM_IN_TOC && ! reload_in_progress
2813 && GET_CODE (XEXP (operands[1], 0)) == PLUS
a9098fd0 2814 && add_operand (XEXP (XEXP (operands[1], 0), 1), mode)
fb4d4348
GK		 2815 && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF
2816 || GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF)
2817 && ! side_effects_p (operands[0]))
2818 {
a4f6c312
SS		 2819 rtx sym =
2820 force_const_mem (mode, XEXP (XEXP (operands[1], 0), 0));
fb4d4348
GK		 2821 rtx other = XEXP (XEXP (operands[1], 0), 1);
2822
a9098fd0
GK		 2823 sym = force_reg (mode, sym);
2824 if (mode == SImode)
2825 emit_insn (gen_addsi3 (operands[0], sym, other));
2826 else
2827 emit_insn (gen_adddi3 (operands[0], sym, other));
fb4d4348
GK		 2828 return;
2829 }
2830
a9098fd0 2831 operands[1] = force_const_mem (mode, operands[1]);
fb4d4348
GK		 2832
2833 if (TARGET_TOC
d34c5b80
DE		 2834 && CONSTANT_POOL_EXPR_P (XEXP (operands[1], 0))
2835 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (
2836 get_pool_constant (XEXP (operands[1], 0)),
2837 get_pool_mode (XEXP (operands[1], 0))))
a9098fd0 2838 {
ba4828e0
RK		 2839 operands[1]
2840 = gen_rtx_MEM (mode,
2841 create_TOC_reference (XEXP (operands[1], 0)));
2842 set_mem_alias_set (operands[1], get_TOC_alias_set ());
fb4d4348 2843 RTX_UNCHANGING_P (operands[1]) = 1;
a9098fd0 2844 }
fb4d4348
GK		 2845 }
2846 break;
a9098fd0 2847
fb4d4348
GK		 2848 case TImode:
2849 if (GET_CODE (operands[0]) == MEM
2850 && GET_CODE (XEXP (operands[0], 0)) != REG
2851 && ! reload_in_progress)
792760b9
RK		 2852 operands[0]
2853 = replace_equiv_address (operands[0],
2854 copy_addr_to_reg (XEXP (operands[0], 0)));
fb4d4348
GK		 2855
2856 if (GET_CODE (operands[1]) == MEM
2857 && GET_CODE (XEXP (operands[1], 0)) != REG
2858 && ! reload_in_progress)
792760b9
RK		 2859 operands[1]
2860 = replace_equiv_address (operands[1],
2861 copy_addr_to_reg (XEXP (operands[1], 0)));
fb4d4348
GK		 2862 break;
2863
2864 default:
2865 abort ();
2866 }
2867
a9098fd0
GK		 2868 /* Above, we may have called force_const_mem which may have returned
2869 an invalid address. If we can, fix this up; otherwise, reload will
2870 have to deal with it. */
2871 if (GET_CODE (operands[1]) == MEM
2872 && ! memory_address_p (mode, XEXP (operands[1], 0))
2873 && ! reload_in_progress)
f4ef873c 2874 operands[1] = adjust_address (operands[1], mode, 0);
a9098fd0 2875
fb4d4348 2876 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
02a4ec28 2877 return;
fb4d4348 2878}
4697a36c
MM		 2879\f
2880/* Initialize a variable CUM of type CUMULATIVE_ARGS
2881 for a call to a function whose data type is FNTYPE.
2882 For a library call, FNTYPE is 0.
2883
2884 For incoming args we set the number of arguments in the prototype large
1c20ae99 2885 so we never return a PARALLEL. */
4697a36c
MM		 2886
2887void
2888init_cumulative_args (cum, fntype, libname, incoming)
2889 CUMULATIVE_ARGS *cum;
2890 tree fntype;
296b8152 2891 rtx libname ATTRIBUTE_UNUSED;
4697a36c
MM		 2892 int incoming;
2893{
2894 static CUMULATIVE_ARGS zero_cumulative;
2895
2896 *cum = zero_cumulative;
2897 cum->words = 0;
2898 cum->fregno = FP_ARG_MIN_REG;
0ac081f6 2899 cum->vregno = ALTIVEC_ARG_MIN_REG;
4697a36c 2900 cum->prototype = (fntype && TYPE_ARG_TYPES (fntype));
7509c759 2901 cum->call_cookie = CALL_NORMAL;
4cc833b7 2902 cum->sysv_gregno = GP_ARG_MIN_REG;
4697a36c
MM		 2903
2904 if (incoming)
bd227acc 2905 cum->nargs_prototype = 1000; /* don't return a PARALLEL */
4697a36c
MM		 2906
2907 else if (cum->prototype)
2908 cum->nargs_prototype = (list_length (TYPE_ARG_TYPES (fntype)) - 1
2909 + (TYPE_MODE (TREE_TYPE (fntype)) == BLKmode
2910 || RETURN_IN_MEMORY (TREE_TYPE (fntype))));
2911
2912 else
2913 cum->nargs_prototype = 0;
2914
2915 cum->orig_nargs = cum->nargs_prototype;
7509c759 2916
a5c76ee6
ZW		 2917 /* Check for a longcall attribute. */
2918 if (fntype
2919 && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype))
2920 && !lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype)))
6a4cee5f
MM		 2921 cum->call_cookie = CALL_LONG;
2922
4697a36c
MM		 2923 if (TARGET_DEBUG_ARG)
2924 {
2925 fprintf (stderr, "\ninit_cumulative_args:");
2926 if (fntype)
2927 {
2928 tree ret_type = TREE_TYPE (fntype);
2929 fprintf (stderr, " ret code = %s,",
2930 tree_code_name[ (int)TREE_CODE (ret_type) ]);
2931 }
2932
6a4cee5f
MM		 2933 if (cum->call_cookie & CALL_LONG)
2934 fprintf (stderr, " longcall,");
2935
4697a36c
MM		 2936 fprintf (stderr, " proto = %d, nargs = %d\n",
2937 cum->prototype, cum->nargs_prototype);
2938 }
2939}
2940\f
c229cba9
DE		 2941/* If defined, a C expression which determines whether, and in which
2942 direction, to pad out an argument with extra space. The value
2943 should be of type `enum direction': either `upward' to pad above
2944 the argument, `downward' to pad below, or `none' to inhibit
2945 padding.
2946
2947 For the AIX ABI structs are always stored left shifted in their
2948 argument slot. */
2949
9ebbca7d 2950enum direction
c229cba9
DE		 2951function_arg_padding (mode, type)
2952 enum machine_mode mode;
2953 tree type;
2954{
c85f7c16 2955 if (type != 0 && AGGREGATE_TYPE_P (type))
9ebbca7d 2956 return upward;
c229cba9
DE		 2957
2958 /* This is the default definition. */
2959 return (! BYTES_BIG_ENDIAN
9ebbca7d 2960 ? upward
c229cba9
DE		 2961 : ((mode == BLKmode
2962 ? (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
2963 && int_size_in_bytes (type) < (PARM_BOUNDARY / BITS_PER_UNIT))
2964 : GET_MODE_BITSIZE (mode) < PARM_BOUNDARY)
9ebbca7d 2965 ? downward : upward));
c229cba9
DE		 2966}
2967
b6c9286a
MM		 2968/* If defined, a C expression that gives the alignment boundary, in bits,
2969 of an argument with the specified mode and type. If it is not defined,
2970 PARM_BOUNDARY is used for all arguments.
2971
2310f99a 2972 V.4 wants long longs to be double word aligned. */
b6c9286a
MM		 2973
2974int
2975function_arg_boundary (mode, type)
2976 enum machine_mode mode;
9ebbca7d 2977 tree type ATTRIBUTE_UNUSED;
b6c9286a 2978{
f607bc57 2979 if (DEFAULT_ABI == ABI_V4 && (mode == DImode || mode == DFmode))
e1f83b4d 2980 return 64;
a3170dc6
AH		 2981 else if (SPE_VECTOR_MODE (mode))
2982 return 64;
0ac081f6
AH		 2983 else if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
2984 return 128;
9ebbca7d 2985 else
b6c9286a 2986 return PARM_BOUNDARY;
b6c9286a
MM		 2987}
2988\f
4697a36c
MM		 2989/* Update the data in CUM to advance over an argument
2990 of mode MODE and data type TYPE.
2991 (TYPE is null for libcalls where that information may not be available.) */
2992
2993void
2994function_arg_advance (cum, mode, type, named)
2995 CUMULATIVE_ARGS *cum;
2996 enum machine_mode mode;
2997 tree type;
2998 int named;
2999{
3000 cum->nargs_prototype--;
3001
0ac081f6
AH		 3002 if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
3003 {
3004 if (cum->vregno <= ALTIVEC_ARG_MAX_REG && cum->nargs_prototype >= 0)
3005 cum->vregno++;
3006 else
3007 cum->words += RS6000_ARG_SIZE (mode, type);
3008 }
a4b0320c
AH		 3009 else if (TARGET_SPE_ABI && TARGET_SPE && SPE_VECTOR_MODE (mode)
3010 && named && cum->sysv_gregno <= GP_ARG_MAX_REG)
3011 cum->sysv_gregno++;
f607bc57 3012 else if (DEFAULT_ABI == ABI_V4)
4697a36c 3013 {
a3170dc6 3014 if (TARGET_HARD_FLOAT && TARGET_FPRS
4cc833b7 3015 && (mode == SFmode || mode == DFmode))
4697a36c 3016 {
4cc833b7
RH		 3017 if (cum->fregno <= FP_ARG_V4_MAX_REG)
3018 cum->fregno++;
3019 else
3020 {
3021 if (mode == DFmode)
3022 cum->words += cum->words & 1;
d34c5b80 3023 cum->words += RS6000_ARG_SIZE (mode, type);
4cc833b7 3024 }
4697a36c 3025 }
4cc833b7
RH		 3026 else
3027 {
3028 int n_words;
3029 int gregno = cum->sysv_gregno;
3030
3031 /* Aggregates and IEEE quad get passed by reference. */
3032 if ((type && AGGREGATE_TYPE_P (type))
3033 || mode == TFmode)
3034 n_words = 1;
3035 else
d34c5b80 3036 n_words = RS6000_ARG_SIZE (mode, type);
4cc833b7 3037
a4b0320c 3038 /* Long long and SPE vectors are put in odd registers. */
4cc833b7
RH		 3039 if (n_words == 2 && (gregno & 1) == 0)
3040 gregno += 1;
3041
a4b0320c
AH		 3042 /* Long long and SPE vectors are not split between registers
3043 and stack. */
4cc833b7
RH		 3044 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
3045 {
3046 /* Long long is aligned on the stack. */
3047 if (n_words == 2)
3048 cum->words += cum->words & 1;
3049 cum->words += n_words;
3050 }
4697a36c 3051
4cc833b7
RH		 3052 /* Note: continuing to accumulate gregno past when we've started
3053 spilling to the stack indicates the fact that we've started
3054 spilling to the stack to expand_builtin_saveregs. */
3055 cum->sysv_gregno = gregno + n_words;
3056 }
4697a36c 3057
4cc833b7
RH		 3058 if (TARGET_DEBUG_ARG)
3059 {
3060 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
3061 cum->words, cum->fregno);
3062 fprintf (stderr, "gregno = %2d, nargs = %4d, proto = %d, ",
3063 cum->sysv_gregno, cum->nargs_prototype, cum->prototype);
3064 fprintf (stderr, "mode = %4s, named = %d\n",
3065 GET_MODE_NAME (mode), named);
3066 }
4697a36c
MM		 3067 }
3068 else
4cc833b7
RH		 3069 {
3070 int align = (TARGET_32BIT && (cum->words & 1) != 0
3071 && function_arg_boundary (mode, type) == 64) ? 1 : 0;
a4f6c312 3072
d34c5b80 3073 cum->words += align + RS6000_ARG_SIZE (mode, type);
4697a36c 3074
a3170dc6
AH		 3075 if (GET_MODE_CLASS (mode) == MODE_FLOAT
3076 && TARGET_HARD_FLOAT && TARGET_FPRS)
fcce224d 3077 cum->fregno += (mode == TFmode ? 2 : 1);
4cc833b7
RH		 3078
3079 if (TARGET_DEBUG_ARG)
3080 {
3081 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
3082 cum->words, cum->fregno);
3083 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s, ",
3084 cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode));
3085 fprintf (stderr, "named = %d, align = %d\n", named, align);
3086 }
3087 }
4697a36c
MM		 3088}
3089\f
3090/* Determine where to put an argument to a function.
3091 Value is zero to push the argument on the stack,
3092 or a hard register in which to store the argument.
3093
3094 MODE is the argument's machine mode.
3095 TYPE is the data type of the argument (as a tree).
3096 This is null for libcalls where that information may
3097 not be available.
3098 CUM is a variable of type CUMULATIVE_ARGS which gives info about
3099 the preceding args and about the function being called.
3100 NAMED is nonzero if this argument is a named parameter
3101 (otherwise it is an extra parameter matching an ellipsis).
3102
3103 On RS/6000 the first eight words of non-FP are normally in registers
3104 and the rest are pushed. Under AIX, the first 13 FP args are in registers.
3105 Under V.4, the first 8 FP args are in registers.
3106
3107 If this is floating-point and no prototype is specified, we use
3108 both an FP and integer register (or possibly FP reg and stack). Library
3109 functions (when TYPE is zero) always have the proper types for args,
3110 so we can pass the FP value just in one register. emit_library_function
1c20ae99 3111 doesn't support PARALLEL anyway. */
4697a36c
MM		 3112
3113struct rtx_def *
3114function_arg (cum, mode, type, named)
3115 CUMULATIVE_ARGS *cum;
3116 enum machine_mode mode;
3117 tree type;
20c29ebe 3118 int named;
4697a36c 3119{
4cc833b7 3120 enum rs6000_abi abi = DEFAULT_ABI;
4697a36c 3121
a4f6c312
SS		 3122 /* Return a marker to indicate whether CR1 needs to set or clear the
3123 bit that V.4 uses to say fp args were passed in registers.
3124 Assume that we don't need the marker for software floating point,
3125 or compiler generated library calls. */
4697a36c
MM		 3126 if (mode == VOIDmode)
3127 {
f607bc57 3128 if (abi == ABI_V4
7509c759 3129 && cum->nargs_prototype < 0
4697a36c 3130 && type && (cum->prototype || TARGET_NO_PROTOTYPE))
7509c759 3131 {
a3170dc6
AH		 3132 /* For the SPE, we need to crxor CR6 always. */
3133 if (TARGET_SPE_ABI)
3134 return GEN_INT (cum->call_cookie | CALL_V4_SET_FP_ARGS);
3135 else if (TARGET_HARD_FLOAT && TARGET_FPRS)
3136 return GEN_INT (cum->call_cookie
3137 | ((cum->fregno == FP_ARG_MIN_REG)
3138 ? CALL_V4_SET_FP_ARGS
3139 : CALL_V4_CLEAR_FP_ARGS));
7509c759 3140 }
4697a36c 3141
7509c759 3142 return GEN_INT (cum->call_cookie);
4697a36c
MM		 3143 }
3144
0ac081f6
AH		 3145 if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
3146 {
20c29ebe 3147 if (named && cum->vregno <= ALTIVEC_ARG_MAX_REG)
0ac081f6
AH		 3148 return gen_rtx_REG (mode, cum->vregno);
3149 else
3150 return NULL;
3151 }
a4b0320c 3152 else if (TARGET_SPE_ABI && TARGET_SPE && SPE_VECTOR_MODE (mode) && named)
a3170dc6 3153 {
a4b0320c 3154 if (cum->sysv_gregno <= GP_ARG_MAX_REG)
a3170dc6
AH		 3155 return gen_rtx_REG (mode, cum->sysv_gregno);
3156 else
3157 return NULL;
3158 }
f607bc57 3159 else if (abi == ABI_V4)
4697a36c 3160 {
a3170dc6 3161 if (TARGET_HARD_FLOAT && TARGET_FPRS
4cc833b7
RH		 3162 && (mode == SFmode || mode == DFmode))
3163 {
3164 if (cum->fregno <= FP_ARG_V4_MAX_REG)
3165 return gen_rtx_REG (mode, cum->fregno);
3166 else
3167 return NULL;
3168 }
3169 else
3170 {
3171 int n_words;
3172 int gregno = cum->sysv_gregno;
3173
3174 /* Aggregates and IEEE quad get passed by reference. */
3175 if ((type && AGGREGATE_TYPE_P (type))
3176 || mode == TFmode)
3177 n_words = 1;
3178 else
d34c5b80 3179 n_words = RS6000_ARG_SIZE (mode, type);
4cc833b7 3180
a4b0320c 3181 /* Long long and SPE vectors are put in odd registers. */
4cc833b7
RH		 3182 if (n_words == 2 && (gregno & 1) == 0)
3183 gregno += 1;
3184
a4b0320c
AH		 3185 /* Long long and SPE vectors are not split between registers
3186 and stack. */
4cc833b7 3187 if (gregno + n_words - 1 <= GP_ARG_MAX_REG)
a4b0320c
AH		 3188 {
3189 /* SPE vectors in ... get split into 2 registers. */
3190 if (TARGET_SPE && TARGET_SPE_ABI
3191 && SPE_VECTOR_MODE (mode) && !named)
3192 {
3193 rtx r1, r2;
57de2c8f 3194 enum machine_mode m = SImode;
f9dd72da 3195
a4b0320c
AH		 3196 r1 = gen_rtx_REG (m, gregno);
3197 r1 = gen_rtx_EXPR_LIST (m, r1, const0_rtx);
3198 r2 = gen_rtx_REG (m, gregno + 1);
3199 r2 = gen_rtx_EXPR_LIST (m, r2, GEN_INT (4));
3200 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
3201 }
3202 return gen_rtx_REG (mode, gregno);
3203 }
4cc833b7
RH		 3204 else
3205 return NULL;
3206 }
4697a36c 3207 }
4cc833b7
RH		 3208 else
3209 {
3210 int align = (TARGET_32BIT && (cum->words & 1) != 0
3211 && function_arg_boundary (mode, type) == 64) ? 1 : 0;
3212 int align_words = cum->words + align;
4697a36c 3213
4cc833b7
RH		 3214 if (type && TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST)
3215 return NULL_RTX;
3216
3217 if (USE_FP_FOR_ARG_P (*cum, mode, type))
3218 {
3219 if (! type
3220 || ((cum->nargs_prototype > 0)
3221 /* IBM AIX extended its linkage convention definition always
3222 to require FP args after register save area hole on the
3223 stack. */
3224 && (DEFAULT_ABI != ABI_AIX
3225 || ! TARGET_XL_CALL
3226 || (align_words < GP_ARG_NUM_REG))))
3227 return gen_rtx_REG (mode, cum->fregno);
3228
3229 return gen_rtx_PARALLEL (mode,
3230 gen_rtvec (2,
39403d82 3231 gen_rtx_EXPR_LIST (VOIDmode,
1c20ae99
JW		 3232 ((align_words >= GP_ARG_NUM_REG)
3233 ? NULL_RTX
3234 : (align_words
d34c5b80 3235 + RS6000_ARG_SIZE (mode, type)
1c20ae99
JW		 3236 > GP_ARG_NUM_REG
3237 /* If this is partially on the stack, then
3238 we only include the portion actually
3239 in registers here. */
39403d82 3240 ? gen_rtx_REG (SImode,
1c20ae99 3241 GP_ARG_MIN_REG + align_words)
39403d82 3242 : gen_rtx_REG (mode,
1c20ae99
JW		 3243 GP_ARG_MIN_REG + align_words))),
3244 const0_rtx),
39403d82
DE		 3245 gen_rtx_EXPR_LIST (VOIDmode,
3246 gen_rtx_REG (mode, cum->fregno),
1c20ae99 3247 const0_rtx)));
4cc833b7
RH		 3248 }
3249 else if (align_words < GP_ARG_NUM_REG)
3250 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
3251 else
3252 return NULL_RTX;
4697a36c 3253 }
4697a36c
MM		 3254}
3255\f
3256/* For an arg passed partly in registers and partly in memory,
3257 this is the number of registers used.
3258 For args passed entirely in registers or entirely in memory, zero. */
3259
3260int
3261function_arg_partial_nregs (cum, mode, type, named)
3262 CUMULATIVE_ARGS *cum;
3263 enum machine_mode mode;
3264 tree type;
d34c5b80 3265 int named ATTRIBUTE_UNUSED;
4697a36c 3266{
f607bc57 3267 if (DEFAULT_ABI == ABI_V4)
4697a36c 3268 return 0;
4697a36c 3269
0ac081f6
AH		 3270 if (USE_FP_FOR_ARG_P (*cum, mode, type)
3271 || USE_ALTIVEC_FOR_ARG_P (*cum, mode, type))
4697a36c
MM		 3272 {
3273 if (cum->nargs_prototype >= 0)
3274 return 0;
3275 }
3276
3277 if (cum->words < GP_ARG_NUM_REG
d34c5b80 3278 && GP_ARG_NUM_REG < (cum->words + RS6000_ARG_SIZE (mode, type)))
4697a36c
MM		 3279 {
3280 int ret = GP_ARG_NUM_REG - cum->words;
3281 if (ret && TARGET_DEBUG_ARG)
3282 fprintf (stderr, "function_arg_partial_nregs: %d\n", ret);
3283
3284 return ret;
3285 }
3286
3287 return 0;
3288}
3289\f
3290/* A C expression that indicates when an argument must be passed by
3291 reference. If nonzero for an argument, a copy of that argument is
3292 made in memory and a pointer to the argument is passed instead of
3293 the argument itself. The pointer is passed in whatever way is
3294 appropriate for passing a pointer to that type.
3295
3296 Under V.4, structures and unions are passed by reference. */
3297
3298int
3299function_arg_pass_by_reference (cum, mode, type, named)
296b8152
KG		 3300 CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED;
3301 enum machine_mode mode ATTRIBUTE_UNUSED;
4697a36c 3302 tree type;
296b8152 3303 int named ATTRIBUTE_UNUSED;
4697a36c 3304{
f607bc57 3305 if (DEFAULT_ABI == ABI_V4
4cc833b7
RH		 3306 && ((type && AGGREGATE_TYPE_P (type))
3307 || mode == TFmode))
4697a36c
MM		 3308 {
3309 if (TARGET_DEBUG_ARG)
3310 fprintf (stderr, "function_arg_pass_by_reference: aggregate\n");
3311
3312 return 1;
3313 }
4697a36c
MM		 3314
3315 return 0;
3316}
4697a36c
MM		 3317\f
3318/* Perform any needed actions needed for a function that is receiving a
3319 variable number of arguments.
3320
3321 CUM is as above.
3322
3323 MODE and TYPE are the mode and type of the current parameter.
3324
3325 PRETEND_SIZE is a variable that should be set to the amount of stack
3326 that must be pushed by the prolog to pretend that our caller pushed
3327 it.
3328
3329 Normally, this macro will push all remaining incoming registers on the
3330 stack and set PRETEND_SIZE to the length of the registers pushed. */
3331
3332void
3333setup_incoming_varargs (cum, mode, type, pretend_size, no_rtl)
3334 CUMULATIVE_ARGS *cum;
3335 enum machine_mode mode;
3336 tree type;
de62b72c 3337 int *pretend_size ATTRIBUTE_UNUSED;
4697a36c
MM		 3338 int no_rtl;
3339
3340{
4cc833b7
RH		 3341 CUMULATIVE_ARGS next_cum;
3342 int reg_size = TARGET_32BIT ? 4 : 8;
ca5adc63 3343 rtx save_area = NULL_RTX, mem;
dfafc897 3344 int first_reg_offset, set;
d34c5b80
DE		 3345 tree fntype;
3346 int stdarg_p;
4697a36c 3347
d34c5b80
DE		 3348 fntype = TREE_TYPE (current_function_decl);
3349 stdarg_p = (TYPE_ARG_TYPES (fntype) != 0
3350 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
3351 != void_type_node));
4cc833b7 3352
d34c5b80
DE		 3353 /* For varargs, we do not want to skip the dummy va_dcl argument.
3354 For stdargs, we do want to skip the last named argument. */
3355 next_cum = *cum;
3356 if (stdarg_p)
3357 function_arg_advance (&next_cum, mode, type, 1);
4cc833b7 3358
f607bc57 3359 if (DEFAULT_ABI == ABI_V4)
d34c5b80 3360 {
4cc833b7 3361 /* Indicate to allocate space on the stack for varargs save area. */
00dba523 3362 cfun->machine->sysv_varargs_p = 1;
60e2d0ca 3363 if (! no_rtl)
2c4974b7 3364 save_area = plus_constant (virtual_stack_vars_rtx,
bd227acc 3365 - RS6000_VARARGS_SIZE);
4cc833b7
RH		 3366
3367 first_reg_offset = next_cum.sysv_gregno - GP_ARG_MIN_REG;
4697a36c 3368 }
60e2d0ca 3369 else
4697a36c 3370 {
d34c5b80 3371 first_reg_offset = next_cum.words;
4cc833b7 3372 save_area = virtual_incoming_args_rtx;
00dba523 3373 cfun->machine->sysv_varargs_p = 0;
4697a36c
MM		 3374
3375 if (MUST_PASS_IN_STACK (mode, type))
d34c5b80 3376 first_reg_offset += RS6000_ARG_SIZE (TYPE_MODE (type), type);
4cc833b7 3377 }
4697a36c 3378
dfafc897 3379 set = get_varargs_alias_set ();
c81fc13e 3380 if (! no_rtl && first_reg_offset < GP_ARG_NUM_REG)
4cc833b7 3381 {
dfafc897
FS		 3382 mem = gen_rtx_MEM (BLKmode,
3383 plus_constant (save_area,
3384 first_reg_offset * reg_size)),
ba4828e0 3385 set_mem_alias_set (mem, set);
8ac61af7 3386 set_mem_align (mem, BITS_PER_WORD);
dfafc897 3387
4cc833b7 3388 move_block_from_reg
dfafc897 3389 (GP_ARG_MIN_REG + first_reg_offset, mem,
4cc833b7
RH		 3390 GP_ARG_NUM_REG - first_reg_offset,
3391 (GP_ARG_NUM_REG - first_reg_offset) * UNITS_PER_WORD);
4697a36c
MM		 3392 }
3393
4697a36c 3394 /* Save FP registers if needed. */
f607bc57 3395 if (DEFAULT_ABI == ABI_V4
a3170dc6
AH		 3396 && TARGET_HARD_FLOAT && TARGET_FPRS
3397 && ! no_rtl
4cc833b7 3398 && next_cum.fregno <= FP_ARG_V4_MAX_REG)
4697a36c 3399 {
4cc833b7 3400 int fregno = next_cum.fregno;
9ebbca7d 3401 rtx cr1 = gen_rtx_REG (CCmode, CR1_REGNO);
4cc833b7
RH		 3402 rtx lab = gen_label_rtx ();
3403 int off = (GP_ARG_NUM_REG * reg_size) + ((fregno - FP_ARG_MIN_REG) * 8);
4697a36c 3404
4cc833b7 3405 emit_jump_insn (gen_rtx_SET (VOIDmode,
4697a36c 3406 pc_rtx,
39403d82 3407 gen_rtx_IF_THEN_ELSE (VOIDmode,
4cc833b7
RH		 3408 gen_rtx_NE (VOIDmode, cr1,
3409 const0_rtx),
39403d82 3410 gen_rtx_LABEL_REF (VOIDmode, lab),
4697a36c
MM		 3411 pc_rtx)));
3412
4cc833b7
RH		 3413 while (fregno <= FP_ARG_V4_MAX_REG)
3414 {
dfafc897 3415 mem = gen_rtx_MEM (DFmode, plus_constant (save_area, off));
ba4828e0 3416 set_mem_alias_set (mem, set);
dfafc897 3417 emit_move_insn (mem, gen_rtx_REG (DFmode, fregno));
4cc833b7
RH		 3418 fregno++;
3419 off += 8;
4697a36c 3420 }
4cc833b7
RH		 3421
3422 emit_label (lab);
4697a36c 3423 }
4697a36c 3424}
4697a36c 3425
dfafc897 3426/* Create the va_list data type. */
2c4974b7 3427
dfafc897
FS		 3428tree
3429rs6000_build_va_list ()
3430{
bab45a51 3431 tree f_gpr, f_fpr, f_ovf, f_sav, record, type_decl;
4697a36c 3432
9ebbca7d
GK		 3433 /* For AIX, prefer 'char *' because that's what the system
3434 header files like. */
f607bc57 3435 if (DEFAULT_ABI != ABI_V4)
9ebbca7d 3436 return build_pointer_type (char_type_node);
dfafc897 3437
f1e639b1 3438 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
bab45a51 3439 type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record);
0f4fd75d 3440
9ebbca7d
GK		 3441 f_gpr = build_decl (FIELD_DECL, get_identifier ("gpr"),
3442 unsigned_char_type_node);
3443 f_fpr = build_decl (FIELD_DECL, get_identifier ("fpr"),
3444 unsigned_char_type_node);
dfafc897
FS		 3445 f_ovf = build_decl (FIELD_DECL, get_identifier ("overflow_arg_area"),
3446 ptr_type_node);
3447 f_sav = build_decl (FIELD_DECL, get_identifier ("reg_save_area"),
3448 ptr_type_node);
3449
3450 DECL_FIELD_CONTEXT (f_gpr) = record;
3451 DECL_FIELD_CONTEXT (f_fpr) = record;
3452 DECL_FIELD_CONTEXT (f_ovf) = record;
3453 DECL_FIELD_CONTEXT (f_sav) = record;
3454
bab45a51
FS		 3455 TREE_CHAIN (record) = type_decl;
3456 TYPE_NAME (record) = type_decl;
dfafc897
FS		 3457 TYPE_FIELDS (record) = f_gpr;
3458 TREE_CHAIN (f_gpr) = f_fpr;
3459 TREE_CHAIN (f_fpr) = f_ovf;
3460 TREE_CHAIN (f_ovf) = f_sav;
3461
3462 layout_type (record);
3463
3464 /* The correct type is an array type of one element. */
3465 return build_array_type (record, build_index_type (size_zero_node));
3466}
3467
3468/* Implement va_start. */
3469
3470void
e5faf155 3471rs6000_va_start (valist, nextarg)
dfafc897
FS		 3472 tree valist;
3473 rtx nextarg;
4697a36c 3474{
dfafc897
FS		 3475 HOST_WIDE_INT words, n_gpr, n_fpr;
3476 tree f_gpr, f_fpr, f_ovf, f_sav;
3477 tree gpr, fpr, ovf, sav, t;
2c4974b7 3478
dfafc897 3479 /* Only SVR4 needs something special. */
f607bc57 3480 if (DEFAULT_ABI != ABI_V4)
dfafc897 3481 {
e5faf155 3482 std_expand_builtin_va_start (valist, nextarg);
dfafc897
FS		 3483 return;
3484 }
3485
973a648b 3486 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
dfafc897
FS		 3487 f_fpr = TREE_CHAIN (f_gpr);
3488 f_ovf = TREE_CHAIN (f_fpr);
3489 f_sav = TREE_CHAIN (f_ovf);
3490
8ebecc3b 3491 valist = build1 (INDIRECT_REF, TREE_TYPE (TREE_TYPE (valist)), valist);
dfafc897
FS		 3492 gpr = build (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr);
3493 fpr = build (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr);
3494 ovf = build (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf);
3495 sav = build (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav);
3496
3497 /* Count number of gp and fp argument registers used. */
4cc833b7 3498 words = current_function_args_info.words;
dfafc897
FS		 3499 n_gpr = current_function_args_info.sysv_gregno - GP_ARG_MIN_REG;
3500 n_fpr = current_function_args_info.fregno - FP_ARG_MIN_REG;
3501
3502 if (TARGET_DEBUG_ARG)
78e1b90d
DE		 3503 {
3504 fputs ("va_start: words = ", stderr);
3505 fprintf (stderr, HOST_WIDE_INT_PRINT_DEC, words);
3506 fputs (", n_gpr = ", stderr);
3507 fprintf (stderr, HOST_WIDE_INT_PRINT_DEC, n_gpr);
3508 fputs (", n_fpr = ", stderr);
3509 fprintf (stderr, HOST_WIDE_INT_PRINT_DEC, n_fpr);
3510 putc ('\n', stderr);
3511 }
dfafc897
FS		 3512
3513 t = build (MODIFY_EXPR, TREE_TYPE (gpr), gpr, build_int_2 (n_gpr, 0));
3514 TREE_SIDE_EFFECTS (t) = 1;
3515 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
3516
3517 t = build (MODIFY_EXPR, TREE_TYPE (fpr), fpr, build_int_2 (n_fpr, 0));
3518 TREE_SIDE_EFFECTS (t) = 1;
3519 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
3520
3521 /* Find the overflow area. */
3522 t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx);
3523 if (words != 0)
3524 t = build (PLUS_EXPR, TREE_TYPE (ovf), t,
3525 build_int_2 (words * UNITS_PER_WORD, 0));
3526 t = build (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
3527 TREE_SIDE_EFFECTS (t) = 1;
3528 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
3529
3530 /* Find the register save area. */
3531 t = make_tree (TREE_TYPE (sav), virtual_stack_vars_rtx);
3532 t = build (PLUS_EXPR, TREE_TYPE (sav), t,
3533 build_int_2 (-RS6000_VARARGS_SIZE, -1));
3534 t = build (MODIFY_EXPR, TREE_TYPE (sav), sav, t);
3535 TREE_SIDE_EFFECTS (t) = 1;
3536 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
3537}
3538
3539/* Implement va_arg. */
3540
3541rtx
3542rs6000_va_arg (valist, type)
3543 tree valist, type;
3544{
3545 tree f_gpr, f_fpr, f_ovf, f_sav;
3546 tree gpr, fpr, ovf, sav, reg, t, u;
3547 int indirect_p, size, rsize, n_reg, sav_ofs, sav_scale;
3548 rtx lab_false, lab_over, addr_rtx, r;
3549
f607bc57 3550 if (DEFAULT_ABI != ABI_V4)
2a55fd42 3551 return std_expand_builtin_va_arg (valist, type);
dfafc897 3552
973a648b 3553 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
dfafc897
FS		 3554 f_fpr = TREE_CHAIN (f_gpr);
3555 f_ovf = TREE_CHAIN (f_fpr);
3556 f_sav = TREE_CHAIN (f_ovf);
3557
8ebecc3b 3558 valist = build1 (INDIRECT_REF, TREE_TYPE (TREE_TYPE (valist)), valist);
dfafc897
FS		 3559 gpr = build (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr);
3560 fpr = build (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr);
3561 ovf = build (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf);
3562 sav = build (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav);
3563
3564 size = int_size_in_bytes (type);
3565 rsize = (size + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
4cc833b7 3566
dfafc897 3567 if (AGGREGATE_TYPE_P (type) || TYPE_MODE (type) == TFmode)
4cc833b7 3568 {
dfafc897
FS		 3569 /* Aggregates and long doubles are passed by reference. */
3570 indirect_p = 1;
3571 reg = gpr;
3572 n_reg = 1;
3573 sav_ofs = 0;
3574 sav_scale = 4;
d3294cd9
FS		 3575 size = UNITS_PER_WORD;
3576 rsize = 1;
dfafc897 3577 }
a3170dc6 3578 else if (FLOAT_TYPE_P (type) && TARGET_HARD_FLOAT && TARGET_FPRS)
dfafc897
FS		 3579 {
3580 /* FP args go in FP registers, if present. */
3581 indirect_p = 0;
3582 reg = fpr;
3583 n_reg = 1;
3584 sav_ofs = 8*4;
3585 sav_scale = 8;
4cc833b7 3586 }
dfafc897
FS		 3587 else
3588 {
3589 /* Otherwise into GP registers. */
3590 indirect_p = 0;
3591 reg = gpr;
3592 n_reg = rsize;
3593 sav_ofs = 0;
3594 sav_scale = 4;
3595 }
3596
a4f6c312 3597 /* Pull the value out of the saved registers ... */
dfafc897
FS		 3598
3599 lab_false = gen_label_rtx ();
3600 lab_over = gen_label_rtx ();
3601 addr_rtx = gen_reg_rtx (Pmode);
3602
16861f33
AH		 3603 /* AltiVec vectors never go in registers. */
3604 if (!TARGET_ALTIVEC || TREE_CODE (type) != VECTOR_TYPE)
2c4974b7 3605 {
41daaf0e
AH		 3606 TREE_THIS_VOLATILE (reg) = 1;
3607 emit_cmp_and_jump_insns
3608 (expand_expr (reg, NULL_RTX, QImode, EXPAND_NORMAL),
3609 GEN_INT (8 - n_reg + 1), GE, const1_rtx, QImode, 1,
3610 lab_false);
dfafc897 3611
41daaf0e
AH		 3612 /* Long long is aligned in the registers. */
3613 if (n_reg > 1)
3614 {
3615 u = build (BIT_AND_EXPR, TREE_TYPE (reg), reg,
3616 build_int_2 (n_reg - 1, 0));
3617 u = build (PLUS_EXPR, TREE_TYPE (reg), reg, u);
3618 u = build (MODIFY_EXPR, TREE_TYPE (reg), reg, u);
3619 TREE_SIDE_EFFECTS (u) = 1;
3620 expand_expr (u, const0_rtx, VOIDmode, EXPAND_NORMAL);
3621 }
2c4974b7 3622
41daaf0e
AH		 3623 if (sav_ofs)
3624 t = build (PLUS_EXPR, ptr_type_node, sav, build_int_2 (sav_ofs, 0));
3625 else
3626 t = sav;
2c4974b7 3627
41daaf0e
AH		 3628 u = build (POSTINCREMENT_EXPR, TREE_TYPE (reg), reg,
3629 build_int_2 (n_reg, 0));
3630 TREE_SIDE_EFFECTS (u) = 1;
2c4974b7 3631
41daaf0e
AH		 3632 u = build1 (CONVERT_EXPR, integer_type_node, u);
3633 TREE_SIDE_EFFECTS (u) = 1;
dfafc897 3634
41daaf0e
AH		 3635 u = build (MULT_EXPR, integer_type_node, u, build_int_2 (sav_scale, 0));
3636 TREE_SIDE_EFFECTS (u) = 1;
dfafc897 3637
41daaf0e
AH		 3638 t = build (PLUS_EXPR, ptr_type_node, t, u);
3639 TREE_SIDE_EFFECTS (t) = 1;
3640
3641 r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL);
3642 if (r != addr_rtx)
3643 emit_move_insn (addr_rtx, r);
3644
3645 emit_jump_insn (gen_jump (lab_over));
3646 emit_barrier ();
3647 }
dfafc897 3648
dfafc897
FS		 3649 emit_label (lab_false);
3650
a4f6c312 3651 /* ... otherwise out of the overflow area. */
dfafc897 3652
41daaf0e
AH		 3653 /* Make sure we don't find reg 7 for the next int arg.
3654
3655 All AltiVec vectors go in the overflow area. So in the AltiVec
3656 case we need to get the vectors from the overflow area, but
3657 remember where the GPRs and FPRs are. */
16861f33
AH		 3658 if (n_reg > 1 && (TREE_CODE (type) != VECTOR_TYPE
3659 || !TARGET_ALTIVEC))
dfafc897
FS		 3660 {
3661 t = build (MODIFY_EXPR, TREE_TYPE (reg), reg, build_int_2 (8, 0));
3662 TREE_SIDE_EFFECTS (t) = 1;
3663 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
3664 }
3665
3666 /* Care for on-stack alignment if needed. */
3667 if (rsize <= 1)
3668 t = ovf;
3669 else
3670 {
41daaf0e
AH		 3671 int align;
3672
16861f33
AH		 3673 /* AltiVec vectors are 16 byte aligned. */
3674 if (TARGET_ALTIVEC && TREE_CODE (type) == VECTOR_TYPE)
41daaf0e
AH		 3675 align = 15;
3676 else
3677 align = 7;
3678
3679 t = build (PLUS_EXPR, TREE_TYPE (ovf), ovf, build_int_2 (align, 0));
3680 t = build (BIT_AND_EXPR, TREE_TYPE (t), t, build_int_2 (-align-1, -1));
dfafc897
FS		 3681 }
3682 t = save_expr (t);
3683
3684 r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL);
3685 if (r != addr_rtx)
3686 emit_move_insn (addr_rtx, r);
3687
3688 t = build (PLUS_EXPR, TREE_TYPE (t), t, build_int_2 (size, 0));
3689 t = build (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
3690 TREE_SIDE_EFFECTS (t) = 1;
3691 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
3692
3693 emit_label (lab_over);
3694
3695 if (indirect_p)
3696 {
3697 r = gen_rtx_MEM (Pmode, addr_rtx);
ba4828e0 3698 set_mem_alias_set (r, get_varargs_alias_set ());
dfafc897
FS		 3699 emit_move_insn (addr_rtx, r);
3700 }
3701
3702 return addr_rtx;
4697a36c 3703}
0ac081f6
AH		 3704
3705/* Builtins. */
3706
6a2dd09a
RS		 3707#define def_builtin(MASK, NAME, TYPE, CODE) \
3708do { \
3709 if ((MASK) & target_flags) \
3710 builtin_function ((NAME), (TYPE), (CODE), BUILT_IN_MD, \
3711 NULL, NULL_TREE); \
0ac081f6
AH		 3712} while (0)
3713
24408032
AH		 3714/* Simple ternary operations: VECd = foo (VECa, VECb, VECc). */
3715
2212663f 3716static const struct builtin_description bdesc_3arg[] =
24408032
AH		 3717{
3718 { MASK_ALTIVEC, CODE_FOR_altivec_vmaddfp, "__builtin_altivec_vmaddfp", ALTIVEC_BUILTIN_VMADDFP },
3719 { MASK_ALTIVEC, CODE_FOR_altivec_vmhaddshs, "__builtin_altivec_vmhaddshs", ALTIVEC_BUILTIN_VMHADDSHS },
3720 { MASK_ALTIVEC, CODE_FOR_altivec_vmhraddshs, "__builtin_altivec_vmhraddshs", ALTIVEC_BUILTIN_VMHRADDSHS },
3721 { MASK_ALTIVEC, CODE_FOR_altivec_vmladduhm, "__builtin_altivec_vmladduhm", ALTIVEC_BUILTIN_VMLADDUHM},
3722 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumubm, "__builtin_altivec_vmsumubm", ALTIVEC_BUILTIN_VMSUMUBM },
3723 { MASK_ALTIVEC, CODE_FOR_altivec_vmsummbm, "__builtin_altivec_vmsummbm", ALTIVEC_BUILTIN_VMSUMMBM },
3724 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhm, "__builtin_altivec_vmsumuhm", ALTIVEC_BUILTIN_VMSUMUHM },
3725 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshm, "__builtin_altivec_vmsumshm", ALTIVEC_BUILTIN_VMSUMSHM },
3726 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhs, "__builtin_altivec_vmsumuhs", ALTIVEC_BUILTIN_VMSUMUHS },
3727 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshs, "__builtin_altivec_vmsumshs", ALTIVEC_BUILTIN_VMSUMSHS },
3728 { MASK_ALTIVEC, CODE_FOR_altivec_vnmsubfp, "__builtin_altivec_vnmsubfp", ALTIVEC_BUILTIN_VNMSUBFP },
3729 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_4sf, "__builtin_altivec_vperm_4sf", ALTIVEC_BUILTIN_VPERM_4SF },
3730 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_4si, "__builtin_altivec_vperm_4si", ALTIVEC_BUILTIN_VPERM_4SI },
3731 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_8hi, "__builtin_altivec_vperm_8hi", ALTIVEC_BUILTIN_VPERM_8HI },
3732 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_16qi, "__builtin_altivec_vperm_16qi", ALTIVEC_BUILTIN_VPERM_16QI },
3733 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_4sf, "__builtin_altivec_vsel_4sf", ALTIVEC_BUILTIN_VSEL_4SF },
3734 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_4si, "__builtin_altivec_vsel_4si", ALTIVEC_BUILTIN_VSEL_4SI },
3735 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_8hi, "__builtin_altivec_vsel_8hi", ALTIVEC_BUILTIN_VSEL_8HI },
3736 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_16qi, "__builtin_altivec_vsel_16qi", ALTIVEC_BUILTIN_VSEL_16QI },
3737 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_16qi, "__builtin_altivec_vsldoi_16qi", ALTIVEC_BUILTIN_VSLDOI_16QI },
3738 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_8hi, "__builtin_altivec_vsldoi_8hi", ALTIVEC_BUILTIN_VSLDOI_8HI },
3739 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_4si, "__builtin_altivec_vsldoi_4si", ALTIVEC_BUILTIN_VSLDOI_4SI },
3740 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_4sf, "__builtin_altivec_vsldoi_4sf", ALTIVEC_BUILTIN_VSLDOI_4SF },
3741};
2212663f 3742
95385cbb
AH		 3743/* DST operations: void foo (void *, const int, const char). */
3744
3745static const struct builtin_description bdesc_dst[] =
3746{
3747 { MASK_ALTIVEC, CODE_FOR_altivec_dst, "__builtin_altivec_dst", ALTIVEC_BUILTIN_DST },
3748 { MASK_ALTIVEC, CODE_FOR_altivec_dstt, "__builtin_altivec_dstt", ALTIVEC_BUILTIN_DSTT },
3749 { MASK_ALTIVEC, CODE_FOR_altivec_dstst, "__builtin_altivec_dstst", ALTIVEC_BUILTIN_DSTST },
3750 { MASK_ALTIVEC, CODE_FOR_altivec_dststt, "__builtin_altivec_dststt", ALTIVEC_BUILTIN_DSTSTT }
3751};
3752
2212663f 3753/* Simple binary operations: VECc = foo (VECa, VECb). */
24408032 3754
a3170dc6 3755static struct builtin_description bdesc_2arg[] =
0ac081f6 3756{
f18c054f
DB		 3757 { MASK_ALTIVEC, CODE_FOR_addv16qi3, "__builtin_altivec_vaddubm", ALTIVEC_BUILTIN_VADDUBM },
3758 { MASK_ALTIVEC, CODE_FOR_addv8hi3, "__builtin_altivec_vadduhm", ALTIVEC_BUILTIN_VADDUHM },
3759 { MASK_ALTIVEC, CODE_FOR_addv4si3, "__builtin_altivec_vadduwm", ALTIVEC_BUILTIN_VADDUWM },
3760 { MASK_ALTIVEC, CODE_FOR_addv4sf3, "__builtin_altivec_vaddfp", ALTIVEC_BUILTIN_VADDFP },
0ac081f6
AH		 3761 { MASK_ALTIVEC, CODE_FOR_altivec_vaddcuw, "__builtin_altivec_vaddcuw", ALTIVEC_BUILTIN_VADDCUW },
3762 { MASK_ALTIVEC, CODE_FOR_altivec_vaddubs, "__builtin_altivec_vaddubs", ALTIVEC_BUILTIN_VADDUBS },
3763 { MASK_ALTIVEC, CODE_FOR_altivec_vaddsbs, "__builtin_altivec_vaddsbs", ALTIVEC_BUILTIN_VADDSBS },
3764 { MASK_ALTIVEC, CODE_FOR_altivec_vadduhs, "__builtin_altivec_vadduhs", ALTIVEC_BUILTIN_VADDUHS },
3765 { MASK_ALTIVEC, CODE_FOR_altivec_vaddshs, "__builtin_altivec_vaddshs", ALTIVEC_BUILTIN_VADDSHS },
3766 { MASK_ALTIVEC, CODE_FOR_altivec_vadduws, "__builtin_altivec_vadduws", ALTIVEC_BUILTIN_VADDUWS },
3767 { MASK_ALTIVEC, CODE_FOR_altivec_vaddsws, "__builtin_altivec_vaddsws", ALTIVEC_BUILTIN_VADDSWS },
f18c054f 3768 { MASK_ALTIVEC, CODE_FOR_andv4si3, "__builtin_altivec_vand", ALTIVEC_BUILTIN_VAND },
0ac081f6
AH		 3769 { MASK_ALTIVEC, CODE_FOR_altivec_vandc, "__builtin_altivec_vandc", ALTIVEC_BUILTIN_VANDC },
3770 { MASK_ALTIVEC, CODE_FOR_altivec_vavgub, "__builtin_altivec_vavgub", ALTIVEC_BUILTIN_VAVGUB },
3771 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsb, "__builtin_altivec_vavgsb", ALTIVEC_BUILTIN_VAVGSB },
3772 { MASK_ALTIVEC, CODE_FOR_altivec_vavguh, "__builtin_altivec_vavguh", ALTIVEC_BUILTIN_VAVGUH },
3773 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsh, "__builtin_altivec_vavgsh", ALTIVEC_BUILTIN_VAVGSH },
3774 { MASK_ALTIVEC, CODE_FOR_altivec_vavguw, "__builtin_altivec_vavguw", ALTIVEC_BUILTIN_VAVGUW },
3775 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsw, "__builtin_altivec_vavgsw", ALTIVEC_BUILTIN_VAVGSW },
617e0e1d
DB		 3776 { MASK_ALTIVEC, CODE_FOR_altivec_vcfux, "__builtin_altivec_vcfux", ALTIVEC_BUILTIN_VCFUX },
3777 { MASK_ALTIVEC, CODE_FOR_altivec_vcfsx, "__builtin_altivec_vcfsx", ALTIVEC_BUILTIN_VCFSX },
0ac081f6
AH		 3778 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpbfp, "__builtin_altivec_vcmpbfp", ALTIVEC_BUILTIN_VCMPBFP },
3779 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequb, "__builtin_altivec_vcmpequb", ALTIVEC_BUILTIN_VCMPEQUB },
3780 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequh, "__builtin_altivec_vcmpequh", ALTIVEC_BUILTIN_VCMPEQUH },
3781 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequw, "__builtin_altivec_vcmpequw", ALTIVEC_BUILTIN_VCMPEQUW },
3782 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpeqfp, "__builtin_altivec_vcmpeqfp", ALTIVEC_BUILTIN_VCMPEQFP },
3783 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgefp, "__builtin_altivec_vcmpgefp", ALTIVEC_BUILTIN_VCMPGEFP },
3784 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtub, "__builtin_altivec_vcmpgtub", ALTIVEC_BUILTIN_VCMPGTUB },
3785 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsb, "__builtin_altivec_vcmpgtsb", ALTIVEC_BUILTIN_VCMPGTSB },
3786 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuh, "__builtin_altivec_vcmpgtuh", ALTIVEC_BUILTIN_VCMPGTUH },
3787 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsh, "__builtin_altivec_vcmpgtsh", ALTIVEC_BUILTIN_VCMPGTSH },
3788 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuw, "__builtin_altivec_vcmpgtuw", ALTIVEC_BUILTIN_VCMPGTUW },
3789 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsw, "__builtin_altivec_vcmpgtsw", ALTIVEC_BUILTIN_VCMPGTSW },
3790 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtfp, "__builtin_altivec_vcmpgtfp", ALTIVEC_BUILTIN_VCMPGTFP },
617e0e1d
DB		 3791 { MASK_ALTIVEC, CODE_FOR_altivec_vctsxs, "__builtin_altivec_vctsxs", ALTIVEC_BUILTIN_VCTSXS },
3792 { MASK_ALTIVEC, CODE_FOR_altivec_vctuxs, "__builtin_altivec_vctuxs", ALTIVEC_BUILTIN_VCTUXS },
f18c054f
DB		 3793 { MASK_ALTIVEC, CODE_FOR_umaxv16qi3, "__builtin_altivec_vmaxub", ALTIVEC_BUILTIN_VMAXUB },
3794 { MASK_ALTIVEC, CODE_FOR_smaxv16qi3, "__builtin_altivec_vmaxsb", ALTIVEC_BUILTIN_VMAXSB },
df966bff
AH		 3795 { MASK_ALTIVEC, CODE_FOR_umaxv8hi3, "__builtin_altivec_vmaxuh", ALTIVEC_BUILTIN_VMAXUH },
3796 { MASK_ALTIVEC, CODE_FOR_smaxv8hi3, "__builtin_altivec_vmaxsh", ALTIVEC_BUILTIN_VMAXSH },
3797 { MASK_ALTIVEC, CODE_FOR_umaxv4si3, "__builtin_altivec_vmaxuw", ALTIVEC_BUILTIN_VMAXUW },
3798 { MASK_ALTIVEC, CODE_FOR_smaxv4si3, "__builtin_altivec_vmaxsw", ALTIVEC_BUILTIN_VMAXSW },
3799 { MASK_ALTIVEC, CODE_FOR_smaxv4sf3, "__builtin_altivec_vmaxfp", ALTIVEC_BUILTIN_VMAXFP },
0ac081f6
AH		 3800 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghb, "__builtin_altivec_vmrghb", ALTIVEC_BUILTIN_VMRGHB },
3801 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghh, "__builtin_altivec_vmrghh", ALTIVEC_BUILTIN_VMRGHH },
3802 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghw, "__builtin_altivec_vmrghw", ALTIVEC_BUILTIN_VMRGHW },
3803 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglb, "__builtin_altivec_vmrglb", ALTIVEC_BUILTIN_VMRGLB },
3804 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglh, "__builtin_altivec_vmrglh", ALTIVEC_BUILTIN_VMRGLH },
3805 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglw, "__builtin_altivec_vmrglw", ALTIVEC_BUILTIN_VMRGLW },
f18c054f
DB		 3806 { MASK_ALTIVEC, CODE_FOR_uminv16qi3, "__builtin_altivec_vminub", ALTIVEC_BUILTIN_VMINUB },
3807 { MASK_ALTIVEC, CODE_FOR_sminv16qi3, "__builtin_altivec_vminsb", ALTIVEC_BUILTIN_VMINSB },
3808 { MASK_ALTIVEC, CODE_FOR_uminv8hi3, "__builtin_altivec_vminuh", ALTIVEC_BUILTIN_VMINUH },
3809 { MASK_ALTIVEC, CODE_FOR_sminv8hi3, "__builtin_altivec_vminsh", ALTIVEC_BUILTIN_VMINSH },
3810 { MASK_ALTIVEC, CODE_FOR_uminv4si3, "__builtin_altivec_vminuw", ALTIVEC_BUILTIN_VMINUW },
3811 { MASK_ALTIVEC, CODE_FOR_sminv4si3, "__builtin_altivec_vminsw", ALTIVEC_BUILTIN_VMINSW },
3812 { MASK_ALTIVEC, CODE_FOR_sminv4sf3, "__builtin_altivec_vminfp", ALTIVEC_BUILTIN_VMINFP },
0ac081f6
AH		 3813 { MASK_ALTIVEC, CODE_FOR_altivec_vmuleub, "__builtin_altivec_vmuleub", ALTIVEC_BUILTIN_VMULEUB },
3814 { MASK_ALTIVEC, CODE_FOR_altivec_vmulesb, "__builtin_altivec_vmulesb", ALTIVEC_BUILTIN_VMULESB },
3815 { MASK_ALTIVEC, CODE_FOR_altivec_vmuleuh, "__builtin_altivec_vmuleuh", ALTIVEC_BUILTIN_VMULEUH },
3816 { MASK_ALTIVEC, CODE_FOR_altivec_vmulesh, "__builtin_altivec_vmulesh", ALTIVEC_BUILTIN_VMULESH },
3817 { MASK_ALTIVEC, CODE_FOR_altivec_vmuloub, "__builtin_altivec_vmuloub", ALTIVEC_BUILTIN_VMULOUB },
3818 { MASK_ALTIVEC, CODE_FOR_altivec_vmulosb, "__builtin_altivec_vmulosb", ALTIVEC_BUILTIN_VMULOSB },
3819 { MASK_ALTIVEC, CODE_FOR_altivec_vmulouh, "__builtin_altivec_vmulouh", ALTIVEC_BUILTIN_VMULOUH },
3820 { MASK_ALTIVEC, CODE_FOR_altivec_vmulosh, "__builtin_altivec_vmulosh", ALTIVEC_BUILTIN_VMULOSH },
3821 { MASK_ALTIVEC, CODE_FOR_altivec_vnor, "__builtin_altivec_vnor", ALTIVEC_BUILTIN_VNOR },
f18c054f 3822 { MASK_ALTIVEC, CODE_FOR_iorv4si3, "__builtin_altivec_vor", ALTIVEC_BUILTIN_VOR },
0ac081f6
AH		 3823 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhum, "__builtin_altivec_vpkuhum", ALTIVEC_BUILTIN_VPKUHUM },
3824 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwum, "__builtin_altivec_vpkuwum", ALTIVEC_BUILTIN_VPKUWUM },
3825 { MASK_ALTIVEC, CODE_FOR_altivec_vpkpx, "__builtin_altivec_vpkpx", ALTIVEC_BUILTIN_VPKPX },
3826 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhss, "__builtin_altivec_vpkuhss", ALTIVEC_BUILTIN_VPKUHSS },
3827 { MASK_ALTIVEC, CODE_FOR_altivec_vpkshss, "__builtin_altivec_vpkshss", ALTIVEC_BUILTIN_VPKSHSS },
3828 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwss, "__builtin_altivec_vpkuwss", ALTIVEC_BUILTIN_VPKUWSS },
3829 { MASK_ALTIVEC, CODE_FOR_altivec_vpkswss, "__builtin_altivec_vpkswss", ALTIVEC_BUILTIN_VPKSWSS },
3830 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhus, "__builtin_altivec_vpkuhus", ALTIVEC_BUILTIN_VPKUHUS },
3831 { MASK_ALTIVEC, CODE_FOR_altivec_vpkshus, "__builtin_altivec_vpkshus", ALTIVEC_BUILTIN_VPKSHUS },
3832 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwus, "__builtin_altivec_vpkuwus", ALTIVEC_BUILTIN_VPKUWUS },
3833 { MASK_ALTIVEC, CODE_FOR_altivec_vpkswus, "__builtin_altivec_vpkswus", ALTIVEC_BUILTIN_VPKSWUS },
3834 { MASK_ALTIVEC, CODE_FOR_altivec_vrlb, "__builtin_altivec_vrlb", ALTIVEC_BUILTIN_VRLB },
3835 { MASK_ALTIVEC, CODE_FOR_altivec_vrlh, "__builtin_altivec_vrlh", ALTIVEC_BUILTIN_VRLH },
3836 { MASK_ALTIVEC, CODE_FOR_altivec_vrlw, "__builtin_altivec_vrlw", ALTIVEC_BUILTIN_VRLW },
3837 { MASK_ALTIVEC, CODE_FOR_altivec_vslb, "__builtin_altivec_vslb", ALTIVEC_BUILTIN_VSLB },
3838 { MASK_ALTIVEC, CODE_FOR_altivec_vslh, "__builtin_altivec_vslh", ALTIVEC_BUILTIN_VSLH },
3839 { MASK_ALTIVEC, CODE_FOR_altivec_vslw, "__builtin_altivec_vslw", ALTIVEC_BUILTIN_VSLW },
3840 { MASK_ALTIVEC, CODE_FOR_altivec_vsl, "__builtin_altivec_vsl", ALTIVEC_BUILTIN_VSL },
3841 { MASK_ALTIVEC, CODE_FOR_altivec_vslo, "__builtin_altivec_vslo", ALTIVEC_BUILTIN_VSLO },
2212663f
DB		 3842 { MASK_ALTIVEC, CODE_FOR_altivec_vspltb, "__builtin_altivec_vspltb", ALTIVEC_BUILTIN_VSPLTB },
3843 { MASK_ALTIVEC, CODE_FOR_altivec_vsplth, "__builtin_altivec_vsplth", ALTIVEC_BUILTIN_VSPLTH },
3844 { MASK_ALTIVEC, CODE_FOR_altivec_vspltw, "__builtin_altivec_vspltw", ALTIVEC_BUILTIN_VSPLTW },
0ac081f6 3845 { MASK_ALTIVEC, CODE_FOR_altivec_vsrb, "__builtin_altivec_vsrb", ALTIVEC_BUILTIN_VSRB },
f18c054f
DB		 3846 { MASK_ALTIVEC, CODE_FOR_altivec_vsrh, "__builtin_altivec_vsrh", ALTIVEC_BUILTIN_VSRH },
3847 { MASK_ALTIVEC, CODE_FOR_altivec_vsrw, "__builtin_altivec_vsrw", ALTIVEC_BUILTIN_VSRW },
0ac081f6
AH		 3848 { MASK_ALTIVEC, CODE_FOR_altivec_vsrab, "__builtin_altivec_vsrab", ALTIVEC_BUILTIN_VSRAB },
3849 { MASK_ALTIVEC, CODE_FOR_altivec_vsrah, "__builtin_altivec_vsrah", ALTIVEC_BUILTIN_VSRAH },
3850 { MASK_ALTIVEC, CODE_FOR_altivec_vsraw, "__builtin_altivec_vsraw", ALTIVEC_BUILTIN_VSRAW },
3851 { MASK_ALTIVEC, CODE_FOR_altivec_vsr, "__builtin_altivec_vsr", ALTIVEC_BUILTIN_VSR },
3852 { MASK_ALTIVEC, CODE_FOR_altivec_vsro, "__builtin_altivec_vsro", ALTIVEC_BUILTIN_VSRO },
f18c054f
DB		 3853 { MASK_ALTIVEC, CODE_FOR_subv16qi3, "__builtin_altivec_vsububm", ALTIVEC_BUILTIN_VSUBUBM },
3854 { MASK_ALTIVEC, CODE_FOR_subv8hi3, "__builtin_altivec_vsubuhm", ALTIVEC_BUILTIN_VSUBUHM },
3855 { MASK_ALTIVEC, CODE_FOR_subv4si3, "__builtin_altivec_vsubuwm", ALTIVEC_BUILTIN_VSUBUWM },
3856 { MASK_ALTIVEC, CODE_FOR_subv4sf3, "__builtin_altivec_vsubfp", ALTIVEC_BUILTIN_VSUBFP },
0ac081f6
AH		 3857 { MASK_ALTIVEC, CODE_FOR_altivec_vsubcuw, "__builtin_altivec_vsubcuw", ALTIVEC_BUILTIN_VSUBCUW },
3858 { MASK_ALTIVEC, CODE_FOR_altivec_vsububs, "__builtin_altivec_vsububs", ALTIVEC_BUILTIN_VSUBUBS },
3859 { MASK_ALTIVEC, CODE_FOR_altivec_vsubsbs, "__builtin_altivec_vsubsbs", ALTIVEC_BUILTIN_VSUBSBS },
3860 { MASK_ALTIVEC, CODE_FOR_altivec_vsubuhs, "__builtin_altivec_vsubuhs", ALTIVEC_BUILTIN_VSUBUHS },
3861 { MASK_ALTIVEC, CODE_FOR_altivec_vsubshs, "__builtin_altivec_vsubshs", ALTIVEC_BUILTIN_VSUBSHS },
3862 { MASK_ALTIVEC, CODE_FOR_altivec_vsubuws, "__builtin_altivec_vsubuws", ALTIVEC_BUILTIN_VSUBUWS },
3863 { MASK_ALTIVEC, CODE_FOR_altivec_vsubsws, "__builtin_altivec_vsubsws", ALTIVEC_BUILTIN_VSUBSWS },
3864 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4ubs, "__builtin_altivec_vsum4ubs", ALTIVEC_BUILTIN_VSUM4UBS },
3865 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4sbs, "__builtin_altivec_vsum4sbs", ALTIVEC_BUILTIN_VSUM4SBS },
3866 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4shs, "__builtin_altivec_vsum4shs", ALTIVEC_BUILTIN_VSUM4SHS },
3867 { MASK_ALTIVEC, CODE_FOR_altivec_vsum2sws, "__builtin_altivec_vsum2sws", ALTIVEC_BUILTIN_VSUM2SWS },
3868 { MASK_ALTIVEC, CODE_FOR_altivec_vsumsws, "__builtin_altivec_vsumsws", ALTIVEC_BUILTIN_VSUMSWS },
f18c054f 3869 { MASK_ALTIVEC, CODE_FOR_xorv4si3, "__builtin_altivec_vxor", ALTIVEC_BUILTIN_VXOR },
a3170dc6
AH		 3870
3871 /* Place holder, leave as first spe builtin. */
3872 { 0, CODE_FOR_spe_evaddw, "__builtin_spe_evaddw", SPE_BUILTIN_EVADDW },
3873 { 0, CODE_FOR_spe_evand, "__builtin_spe_evand", SPE_BUILTIN_EVAND },
3874 { 0, CODE_FOR_spe_evandc, "__builtin_spe_evandc", SPE_BUILTIN_EVANDC },
3875 { 0, CODE_FOR_spe_evdivws, "__builtin_spe_evdivws", SPE_BUILTIN_EVDIVWS },
3876 { 0, CODE_FOR_spe_evdivwu, "__builtin_spe_evdivwu", SPE_BUILTIN_EVDIVWU },
3877 { 0, CODE_FOR_spe_eveqv, "__builtin_spe_eveqv", SPE_BUILTIN_EVEQV },
3878 { 0, CODE_FOR_spe_evfsadd, "__builtin_spe_evfsadd", SPE_BUILTIN_EVFSADD },
3879 { 0, CODE_FOR_spe_evfsdiv, "__builtin_spe_evfsdiv", SPE_BUILTIN_EVFSDIV },
3880 { 0, CODE_FOR_spe_evfsmul, "__builtin_spe_evfsmul", SPE_BUILTIN_EVFSMUL },
3881 { 0, CODE_FOR_spe_evfssub, "__builtin_spe_evfssub", SPE_BUILTIN_EVFSSUB },
3882 { 0, CODE_FOR_spe_evmergehi, "__builtin_spe_evmergehi", SPE_BUILTIN_EVMERGEHI },
3883 { 0, CODE_FOR_spe_evmergehilo, "__builtin_spe_evmergehilo", SPE_BUILTIN_EVMERGEHILO },
3884 { 0, CODE_FOR_spe_evmergelo, "__builtin_spe_evmergelo", SPE_BUILTIN_EVMERGELO },
3885 { 0, CODE_FOR_spe_evmergelohi, "__builtin_spe_evmergelohi", SPE_BUILTIN_EVMERGELOHI },
3886 { 0, CODE_FOR_spe_evmhegsmfaa, "__builtin_spe_evmhegsmfaa", SPE_BUILTIN_EVMHEGSMFAA },
3887 { 0, CODE_FOR_spe_evmhegsmfan, "__builtin_spe_evmhegsmfan", SPE_BUILTIN_EVMHEGSMFAN },
3888 { 0, CODE_FOR_spe_evmhegsmiaa, "__builtin_spe_evmhegsmiaa", SPE_BUILTIN_EVMHEGSMIAA },
3889 { 0, CODE_FOR_spe_evmhegsmian, "__builtin_spe_evmhegsmian", SPE_BUILTIN_EVMHEGSMIAN },
3890 { 0, CODE_FOR_spe_evmhegumiaa, "__builtin_spe_evmhegumiaa", SPE_BUILTIN_EVMHEGUMIAA },
3891 { 0, CODE_FOR_spe_evmhegumian, "__builtin_spe_evmhegumian", SPE_BUILTIN_EVMHEGUMIAN },
3892 { 0, CODE_FOR_spe_evmhesmf, "__builtin_spe_evmhesmf", SPE_BUILTIN_EVMHESMF },
3893 { 0, CODE_FOR_spe_evmhesmfa, "__builtin_spe_evmhesmfa", SPE_BUILTIN_EVMHESMFA },
3894 { 0, CODE_FOR_spe_evmhesmfaaw, "__builtin_spe_evmhesmfaaw", SPE_BUILTIN_EVMHESMFAAW },
3895 { 0, CODE_FOR_spe_evmhesmfanw, "__builtin_spe_evmhesmfanw", SPE_BUILTIN_EVMHESMFANW },
3896 { 0, CODE_FOR_spe_evmhesmi, "__builtin_spe_evmhesmi", SPE_BUILTIN_EVMHESMI },
3897 { 0, CODE_FOR_spe_evmhesmia, "__builtin_spe_evmhesmia", SPE_BUILTIN_EVMHESMIA },
3898 { 0, CODE_FOR_spe_evmhesmiaaw, "__builtin_spe_evmhesmiaaw", SPE_BUILTIN_EVMHESMIAAW },
3899 { 0, CODE_FOR_spe_evmhesmianw, "__builtin_spe_evmhesmianw", SPE_BUILTIN_EVMHESMIANW },
3900 { 0, CODE_FOR_spe_evmhessf, "__builtin_spe_evmhessf", SPE_BUILTIN_EVMHESSF },
3901 { 0, CODE_FOR_spe_evmhessfa, "__builtin_spe_evmhessfa", SPE_BUILTIN_EVMHESSFA },
3902 { 0, CODE_FOR_spe_evmhessfaaw, "__builtin_spe_evmhessfaaw", SPE_BUILTIN_EVMHESSFAAW },
3903 { 0, CODE_FOR_spe_evmhessfanw, "__builtin_spe_evmhessfanw", SPE_BUILTIN_EVMHESSFANW },
3904 { 0, CODE_FOR_spe_evmhessiaaw, "__builtin_spe_evmhessiaaw", SPE_BUILTIN_EVMHESSIAAW },
3905 { 0, CODE_FOR_spe_evmhessianw, "__builtin_spe_evmhessianw", SPE_BUILTIN_EVMHESSIANW },
3906 { 0, CODE_FOR_spe_evmheumi, "__builtin_spe_evmheumi", SPE_BUILTIN_EVMHEUMI },
3907 { 0, CODE_FOR_spe_evmheumia, "__builtin_spe_evmheumia", SPE_BUILTIN_EVMHEUMIA },
3908 { 0, CODE_FOR_spe_evmheumiaaw, "__builtin_spe_evmheumiaaw", SPE_BUILTIN_EVMHEUMIAAW },
3909 { 0, CODE_FOR_spe_evmheumianw, "__builtin_spe_evmheumianw", SPE_BUILTIN_EVMHEUMIANW },
3910 { 0, CODE_FOR_spe_evmheusiaaw, "__builtin_spe_evmheusiaaw", SPE_BUILTIN_EVMHEUSIAAW },
3911 { 0, CODE_FOR_spe_evmheusianw, "__builtin_spe_evmheusianw", SPE_BUILTIN_EVMHEUSIANW },
3912 { 0, CODE_FOR_spe_evmhogsmfaa, "__builtin_spe_evmhogsmfaa", SPE_BUILTIN_EVMHOGSMFAA },
3913 { 0, CODE_FOR_spe_evmhogsmfan, "__builtin_spe_evmhogsmfan", SPE_BUILTIN_EVMHOGSMFAN },
3914 { 0, CODE_FOR_spe_evmhogsmiaa, "__builtin_spe_evmhogsmiaa", SPE_BUILTIN_EVMHOGSMIAA },
3915 { 0, CODE_FOR_spe_evmhogsmian, "__builtin_spe_evmhogsmian", SPE_BUILTIN_EVMHOGSMIAN },
3916 { 0, CODE_FOR_spe_evmhogumiaa, "__builtin_spe_evmhogumiaa", SPE_BUILTIN_EVMHOGUMIAA },
3917 { 0, CODE_FOR_spe_evmhogumian, "__builtin_spe_evmhogumian", SPE_BUILTIN_EVMHOGUMIAN },
3918 { 0, CODE_FOR_spe_evmhosmf, "__builtin_spe_evmhosmf", SPE_BUILTIN_EVMHOSMF },
3919 { 0, CODE_FOR_spe_evmhosmfa, "__builtin_spe_evmhosmfa", SPE_BUILTIN_EVMHOSMFA },
3920 { 0, CODE_FOR_spe_evmhosmfaaw, "__builtin_spe_evmhosmfaaw", SPE_BUILTIN_EVMHOSMFAAW },
3921 { 0, CODE_FOR_spe_evmhosmfanw, "__builtin_spe_evmhosmfanw", SPE_BUILTIN_EVMHOSMFANW },
3922 { 0, CODE_FOR_spe_evmhosmi, "__builtin_spe_evmhosmi", SPE_BUILTIN_EVMHOSMI },
3923 { 0, CODE_FOR_spe_evmhosmia, "__builtin_spe_evmhosmia", SPE_BUILTIN_EVMHOSMIA },
3924 { 0, CODE_FOR_spe_evmhosmiaaw, "__builtin_spe_evmhosmiaaw", SPE_BUILTIN_EVMHOSMIAAW },
3925 { 0, CODE_FOR_spe_evmhosmianw, "__builtin_spe_evmhosmianw", SPE_BUILTIN_EVMHOSMIANW },
3926 { 0, CODE_FOR_spe_evmhossf, "__builtin_spe_evmhossf", SPE_BUILTIN_EVMHOSSF },
3927 { 0, CODE_FOR_spe_evmhossfa, "__builtin_spe_evmhossfa", SPE_BUILTIN_EVMHOSSFA },
3928 { 0, CODE_FOR_spe_evmhossfaaw, "__builtin_spe_evmhossfaaw", SPE_BUILTIN_EVMHOSSFAAW },
3929 { 0, CODE_FOR_spe_evmhossfanw, "__builtin_spe_evmhossfanw", SPE_BUILTIN_EVMHOSSFANW },
3930 { 0, CODE_FOR_spe_evmhossiaaw, "__builtin_spe_evmhossiaaw", SPE_BUILTIN_EVMHOSSIAAW },
3931 { 0, CODE_FOR_spe_evmhossianw, "__builtin_spe_evmhossianw", SPE_BUILTIN_EVMHOSSIANW },
3932 { 0, CODE_FOR_spe_evmhoumi, "__builtin_spe_evmhoumi", SPE_BUILTIN_EVMHOUMI },
3933 { 0, CODE_FOR_spe_evmhoumia, "__builtin_spe_evmhoumia", SPE_BUILTIN_EVMHOUMIA },
3934 { 0, CODE_FOR_spe_evmhoumiaaw, "__builtin_spe_evmhoumiaaw", SPE_BUILTIN_EVMHOUMIAAW },
3935 { 0, CODE_FOR_spe_evmhoumianw, "__builtin_spe_evmhoumianw", SPE_BUILTIN_EVMHOUMIANW },
3936 { 0, CODE_FOR_spe_evmhousiaaw, "__builtin_spe_evmhousiaaw", SPE_BUILTIN_EVMHOUSIAAW },
3937 { 0, CODE_FOR_spe_evmhousianw, "__builtin_spe_evmhousianw", SPE_BUILTIN_EVMHOUSIANW },
3938 { 0, CODE_FOR_spe_evmwhsmf, "__builtin_spe_evmwhsmf", SPE_BUILTIN_EVMWHSMF },
3939 { 0, CODE_FOR_spe_evmwhsmfa, "__builtin_spe_evmwhsmfa", SPE_BUILTIN_EVMWHSMFA },
3940 { 0, CODE_FOR_spe_evmwhsmi, "__builtin_spe_evmwhsmi", SPE_BUILTIN_EVMWHSMI },
3941 { 0, CODE_FOR_spe_evmwhsmia, "__builtin_spe_evmwhsmia", SPE_BUILTIN_EVMWHSMIA },
3942 { 0, CODE_FOR_spe_evmwhssf, "__builtin_spe_evmwhssf", SPE_BUILTIN_EVMWHSSF },
3943 { 0, CODE_FOR_spe_evmwhssfa, "__builtin_spe_evmwhssfa", SPE_BUILTIN_EVMWHSSFA },
3944 { 0, CODE_FOR_spe_evmwhumi, "__builtin_spe_evmwhumi", SPE_BUILTIN_EVMWHUMI },
3945 { 0, CODE_FOR_spe_evmwhumia, "__builtin_spe_evmwhumia", SPE_BUILTIN_EVMWHUMIA },
a3170dc6
AH		 3946 { 0, CODE_FOR_spe_evmwlsmiaaw, "__builtin_spe_evmwlsmiaaw", SPE_BUILTIN_EVMWLSMIAAW },
3947 { 0, CODE_FOR_spe_evmwlsmianw, "__builtin_spe_evmwlsmianw", SPE_BUILTIN_EVMWLSMIANW },
a3170dc6
AH		 3948 { 0, CODE_FOR_spe_evmwlssiaaw, "__builtin_spe_evmwlssiaaw", SPE_BUILTIN_EVMWLSSIAAW },
3949 { 0, CODE_FOR_spe_evmwlssianw, "__builtin_spe_evmwlssianw", SPE_BUILTIN_EVMWLSSIANW },
3950 { 0, CODE_FOR_spe_evmwlumi, "__builtin_spe_evmwlumi", SPE_BUILTIN_EVMWLUMI },
3951 { 0, CODE_FOR_spe_evmwlumia, "__builtin_spe_evmwlumia", SPE_BUILTIN_EVMWLUMIA },
3952 { 0, CODE_FOR_spe_evmwlumiaaw, "__builtin_spe_evmwlumiaaw", SPE_BUILTIN_EVMWLUMIAAW },
3953 { 0, CODE_FOR_spe_evmwlumianw, "__builtin_spe_evmwlumianw", SPE_BUILTIN_EVMWLUMIANW },
3954 { 0, CODE_FOR_spe_evmwlusiaaw, "__builtin_spe_evmwlusiaaw", SPE_BUILTIN_EVMWLUSIAAW },
3955 { 0, CODE_FOR_spe_evmwlusianw, "__builtin_spe_evmwlusianw", SPE_BUILTIN_EVMWLUSIANW },
3956 { 0, CODE_FOR_spe_evmwsmf, "__builtin_spe_evmwsmf", SPE_BUILTIN_EVMWSMF },
3957 { 0, CODE_FOR_spe_evmwsmfa, "__builtin_spe_evmwsmfa", SPE_BUILTIN_EVMWSMFA },
3958 { 0, CODE_FOR_spe_evmwsmfaa, "__builtin_spe_evmwsmfaa", SPE_BUILTIN_EVMWSMFAA },
3959 { 0, CODE_FOR_spe_evmwsmfan, "__builtin_spe_evmwsmfan", SPE_BUILTIN_EVMWSMFAN },
3960 { 0, CODE_FOR_spe_evmwsmi, "__builtin_spe_evmwsmi", SPE_BUILTIN_EVMWSMI },
3961 { 0, CODE_FOR_spe_evmwsmia, "__builtin_spe_evmwsmia", SPE_BUILTIN_EVMWSMIA },
3962 { 0, CODE_FOR_spe_evmwsmiaa, "__builtin_spe_evmwsmiaa", SPE_BUILTIN_EVMWSMIAA },
3963 { 0, CODE_FOR_spe_evmwsmian, "__builtin_spe_evmwsmian", SPE_BUILTIN_EVMWSMIAN },
3964 { 0, CODE_FOR_spe_evmwssf, "__builtin_spe_evmwssf", SPE_BUILTIN_EVMWSSF },
3965 { 0, CODE_FOR_spe_evmwssfa, "__builtin_spe_evmwssfa", SPE_BUILTIN_EVMWSSFA },
3966 { 0, CODE_FOR_spe_evmwssfaa, "__builtin_spe_evmwssfaa", SPE_BUILTIN_EVMWSSFAA },
3967 { 0, CODE_FOR_spe_evmwssfan, "__builtin_spe_evmwssfan", SPE_BUILTIN_EVMWSSFAN },
3968 { 0, CODE_FOR_spe_evmwumi, "__builtin_spe_evmwumi", SPE_BUILTIN_EVMWUMI },
3969 { 0, CODE_FOR_spe_evmwumia, "__builtin_spe_evmwumia", SPE_BUILTIN_EVMWUMIA },
3970 { 0, CODE_FOR_spe_evmwumiaa, "__builtin_spe_evmwumiaa", SPE_BUILTIN_EVMWUMIAA },
3971 { 0, CODE_FOR_spe_evmwumian, "__builtin_spe_evmwumian", SPE_BUILTIN_EVMWUMIAN },
3972 { 0, CODE_FOR_spe_evnand, "__builtin_spe_evnand", SPE_BUILTIN_EVNAND },
3973 { 0, CODE_FOR_spe_evnor, "__builtin_spe_evnor", SPE_BUILTIN_EVNOR },
3974 { 0, CODE_FOR_spe_evor, "__builtin_spe_evor", SPE_BUILTIN_EVOR },
3975 { 0, CODE_FOR_spe_evorc, "__builtin_spe_evorc", SPE_BUILTIN_EVORC },
3976 { 0, CODE_FOR_spe_evrlw, "__builtin_spe_evrlw", SPE_BUILTIN_EVRLW },
3977 { 0, CODE_FOR_spe_evslw, "__builtin_spe_evslw", SPE_BUILTIN_EVSLW },
3978 { 0, CODE_FOR_spe_evsrws, "__builtin_spe_evsrws", SPE_BUILTIN_EVSRWS },
3979 { 0, CODE_FOR_spe_evsrwu, "__builtin_spe_evsrwu", SPE_BUILTIN_EVSRWU },
3980 { 0, CODE_FOR_spe_evsubfw, "__builtin_spe_evsubfw", SPE_BUILTIN_EVSUBFW },
3981
3982 /* SPE binary operations expecting a 5-bit unsigned literal. */
3983 { 0, CODE_FOR_spe_evaddiw, "__builtin_spe_evaddiw", SPE_BUILTIN_EVADDIW },
3984
3985 { 0, CODE_FOR_spe_evrlwi, "__builtin_spe_evrlwi", SPE_BUILTIN_EVRLWI },
3986 { 0, CODE_FOR_spe_evslwi, "__builtin_spe_evslwi", SPE_BUILTIN_EVSLWI },
3987 { 0, CODE_FOR_spe_evsrwis, "__builtin_spe_evsrwis", SPE_BUILTIN_EVSRWIS },
3988 { 0, CODE_FOR_spe_evsrwiu, "__builtin_spe_evsrwiu", SPE_BUILTIN_EVSRWIU },
3989 { 0, CODE_FOR_spe_evsubifw, "__builtin_spe_evsubifw", SPE_BUILTIN_EVSUBIFW },
3990 { 0, CODE_FOR_spe_evmwhssfaa, "__builtin_spe_evmwhssfaa", SPE_BUILTIN_EVMWHSSFAA },
3991 { 0, CODE_FOR_spe_evmwhssmaa, "__builtin_spe_evmwhssmaa", SPE_BUILTIN_EVMWHSSMAA },
3992 { 0, CODE_FOR_spe_evmwhsmfaa, "__builtin_spe_evmwhsmfaa", SPE_BUILTIN_EVMWHSMFAA },
3993 { 0, CODE_FOR_spe_evmwhsmiaa, "__builtin_spe_evmwhsmiaa", SPE_BUILTIN_EVMWHSMIAA },
3994 { 0, CODE_FOR_spe_evmwhusiaa, "__builtin_spe_evmwhusiaa", SPE_BUILTIN_EVMWHUSIAA },
3995 { 0, CODE_FOR_spe_evmwhumiaa, "__builtin_spe_evmwhumiaa", SPE_BUILTIN_EVMWHUMIAA },
3996 { 0, CODE_FOR_spe_evmwhssfan, "__builtin_spe_evmwhssfan", SPE_BUILTIN_EVMWHSSFAN },
3997 { 0, CODE_FOR_spe_evmwhssian, "__builtin_spe_evmwhssian", SPE_BUILTIN_EVMWHSSIAN },
3998 { 0, CODE_FOR_spe_evmwhsmfan, "__builtin_spe_evmwhsmfan", SPE_BUILTIN_EVMWHSMFAN },
3999 { 0, CODE_FOR_spe_evmwhsmian, "__builtin_spe_evmwhsmian", SPE_BUILTIN_EVMWHSMIAN },
4000 { 0, CODE_FOR_spe_evmwhusian, "__builtin_spe_evmwhusian", SPE_BUILTIN_EVMWHUSIAN },
4001 { 0, CODE_FOR_spe_evmwhumian, "__builtin_spe_evmwhumian", SPE_BUILTIN_EVMWHUMIAN },
4002 { 0, CODE_FOR_spe_evmwhgssfaa, "__builtin_spe_evmwhgssfaa", SPE_BUILTIN_EVMWHGSSFAA },
4003 { 0, CODE_FOR_spe_evmwhgsmfaa, "__builtin_spe_evmwhgsmfaa", SPE_BUILTIN_EVMWHGSMFAA },
4004 { 0, CODE_FOR_spe_evmwhgsmiaa, "__builtin_spe_evmwhgsmiaa", SPE_BUILTIN_EVMWHGSMIAA },
4005 { 0, CODE_FOR_spe_evmwhgumiaa, "__builtin_spe_evmwhgumiaa", SPE_BUILTIN_EVMWHGUMIAA },
4006 { 0, CODE_FOR_spe_evmwhgssfan, "__builtin_spe_evmwhgssfan", SPE_BUILTIN_EVMWHGSSFAN },
4007 { 0, CODE_FOR_spe_evmwhgsmfan, "__builtin_spe_evmwhgsmfan", SPE_BUILTIN_EVMWHGSMFAN },
4008 { 0, CODE_FOR_spe_evmwhgsmian, "__builtin_spe_evmwhgsmian", SPE_BUILTIN_EVMWHGSMIAN },
4009 { 0, CODE_FOR_spe_evmwhgumian, "__builtin_spe_evmwhgumian", SPE_BUILTIN_EVMWHGUMIAN },
4010 { 0, CODE_FOR_spe_brinc, "__builtin_spe_brinc", SPE_BUILTIN_BRINC },
4011
4012 /* Place-holder. Leave as last binary SPE builtin. */
4013 { 0, CODE_FOR_spe_evxor, "__builtin_spe_evxor", SPE_BUILTIN_EVXOR },
ae4b4a02
AH		 4014};
4015
4016/* AltiVec predicates. */
4017
4018struct builtin_description_predicates
4019{
4020 const unsigned int mask;
4021 const enum insn_code icode;
4022 const char *opcode;
4023 const char *const name;
4024 const enum rs6000_builtins code;
4025};
4026
4027static const struct builtin_description_predicates bdesc_altivec_preds[] =
4028{
4029 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpbfp.", "__builtin_altivec_vcmpbfp_p", ALTIVEC_BUILTIN_VCMPBFP_P },
4030 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpeqfp.", "__builtin_altivec_vcmpeqfp_p", ALTIVEC_BUILTIN_VCMPEQFP_P },
4031 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgefp.", "__builtin_altivec_vcmpgefp_p", ALTIVEC_BUILTIN_VCMPGEFP_P },
4032 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgtfp.", "__builtin_altivec_vcmpgtfp_p", ALTIVEC_BUILTIN_VCMPGTFP_P },
4033 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpequw.", "__builtin_altivec_vcmpequw_p", ALTIVEC_BUILTIN_VCMPEQUW_P },
4034 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtsw.", "__builtin_altivec_vcmpgtsw_p", ALTIVEC_BUILTIN_VCMPGTSW_P },
4035 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtuw.", "__builtin_altivec_vcmpgtuw_p", ALTIVEC_BUILTIN_VCMPGTUW_P },
4036 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtuh.", "__builtin_altivec_vcmpgtuh_p", ALTIVEC_BUILTIN_VCMPGTUH_P },
4037 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtsh.", "__builtin_altivec_vcmpgtsh_p", ALTIVEC_BUILTIN_VCMPGTSH_P },
4038 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpequh.", "__builtin_altivec_vcmpequh_p", ALTIVEC_BUILTIN_VCMPEQUH_P },
4039 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpequb.", "__builtin_altivec_vcmpequb_p", ALTIVEC_BUILTIN_VCMPEQUB_P },
4040 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtsb.", "__builtin_altivec_vcmpgtsb_p", ALTIVEC_BUILTIN_VCMPGTSB_P },
4041 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtub.", "__builtin_altivec_vcmpgtub_p", ALTIVEC_BUILTIN_VCMPGTUB_P }
0ac081f6 4042};
24408032 4043
a3170dc6
AH		 4044/* SPE predicates. */
4045static struct builtin_description bdesc_spe_predicates[] =
4046{
4047 /* Place-holder. Leave as first. */
4048 { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evcmpeq", SPE_BUILTIN_EVCMPEQ },
4049 { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evcmpgts", SPE_BUILTIN_EVCMPGTS },
4050 { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evcmpgtu", SPE_BUILTIN_EVCMPGTU },
4051 { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evcmplts", SPE_BUILTIN_EVCMPLTS },
4052 { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evcmpltu", SPE_BUILTIN_EVCMPLTU },
4053 { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evfscmpeq", SPE_BUILTIN_EVFSCMPEQ },
4054 { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evfscmpgt", SPE_BUILTIN_EVFSCMPGT },
4055 { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evfscmplt", SPE_BUILTIN_EVFSCMPLT },
4056 { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evfststeq", SPE_BUILTIN_EVFSTSTEQ },
4057 { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evfststgt", SPE_BUILTIN_EVFSTSTGT },
4058 /* Place-holder. Leave as last. */
4059 { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evfststlt", SPE_BUILTIN_EVFSTSTLT },
4060};
4061
4062/* SPE evsel predicates. */
4063static struct builtin_description bdesc_spe_evsel[] =
4064{
4065 /* Place-holder. Leave as first. */
4066 { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evsel_gts", SPE_BUILTIN_EVSEL_CMPGTS },
4067 { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evsel_gtu", SPE_BUILTIN_EVSEL_CMPGTU },
4068 { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evsel_lts", SPE_BUILTIN_EVSEL_CMPLTS },
4069 { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evsel_ltu", SPE_BUILTIN_EVSEL_CMPLTU },
4070 { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evsel_eq", SPE_BUILTIN_EVSEL_CMPEQ },
4071 { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evsel_fsgt", SPE_BUILTIN_EVSEL_FSCMPGT },
4072 { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evsel_fslt", SPE_BUILTIN_EVSEL_FSCMPLT },
4073 { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evsel_fseq", SPE_BUILTIN_EVSEL_FSCMPEQ },
4074 { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evsel_fststgt", SPE_BUILTIN_EVSEL_FSTSTGT },
4075 { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evsel_fststlt", SPE_BUILTIN_EVSEL_FSTSTLT },
4076 /* Place-holder. Leave as last. */
4077 { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evsel_fststeq", SPE_BUILTIN_EVSEL_FSTSTEQ },
4078};
4079
100c4561
AH		 4080/* ABS* opreations. */
4081
4082static const struct builtin_description bdesc_abs[] =
4083{
4084 { MASK_ALTIVEC, CODE_FOR_absv4si2, "__builtin_altivec_abs_v4si", ALTIVEC_BUILTIN_ABS_V4SI },
4085 { MASK_ALTIVEC, CODE_FOR_absv8hi2, "__builtin_altivec_abs_v8hi", ALTIVEC_BUILTIN_ABS_V8HI },
4086 { MASK_ALTIVEC, CODE_FOR_absv4sf2, "__builtin_altivec_abs_v4sf", ALTIVEC_BUILTIN_ABS_V4SF },
4087 { MASK_ALTIVEC, CODE_FOR_absv16qi2, "__builtin_altivec_abs_v16qi", ALTIVEC_BUILTIN_ABS_V16QI },
4088 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v4si, "__builtin_altivec_abss_v4si", ALTIVEC_BUILTIN_ABSS_V4SI },
4089 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v8hi, "__builtin_altivec_abss_v8hi", ALTIVEC_BUILTIN_ABSS_V8HI },
4090 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v16qi, "__builtin_altivec_abss_v16qi", ALTIVEC_BUILTIN_ABSS_V16QI }
4091};
4092
617e0e1d
DB		 4093/* Simple unary operations: VECb = foo (unsigned literal) or VECb =
4094 foo (VECa). */
24408032 4095
a3170dc6 4096static struct builtin_description bdesc_1arg[] =
2212663f 4097{
617e0e1d
DB		 4098 { MASK_ALTIVEC, CODE_FOR_altivec_vexptefp, "__builtin_altivec_vexptefp", ALTIVEC_BUILTIN_VEXPTEFP },
4099 { MASK_ALTIVEC, CODE_FOR_altivec_vlogefp, "__builtin_altivec_vlogefp", ALTIVEC_BUILTIN_VLOGEFP },
4100 { MASK_ALTIVEC, CODE_FOR_altivec_vrefp, "__builtin_altivec_vrefp", ALTIVEC_BUILTIN_VREFP },
4101 { MASK_ALTIVEC, CODE_FOR_altivec_vrfim, "__builtin_altivec_vrfim", ALTIVEC_BUILTIN_VRFIM },
4102 { MASK_ALTIVEC, CODE_FOR_altivec_vrfin, "__builtin_altivec_vrfin", ALTIVEC_BUILTIN_VRFIN },
4103 { MASK_ALTIVEC, CODE_FOR_altivec_vrfip, "__builtin_altivec_vrfip", ALTIVEC_BUILTIN_VRFIP },
4104 { MASK_ALTIVEC, CODE_FOR_ftruncv4sf2, "__builtin_altivec_vrfiz", ALTIVEC_BUILTIN_VRFIZ },
4105 { MASK_ALTIVEC, CODE_FOR_altivec_vrsqrtefp, "__builtin_altivec_vrsqrtefp", ALTIVEC_BUILTIN_VRSQRTEFP },
2212663f
DB		 4106 { MASK_ALTIVEC, CODE_FOR_altivec_vspltisb, "__builtin_altivec_vspltisb", ALTIVEC_BUILTIN_VSPLTISB },
4107 { MASK_ALTIVEC, CODE_FOR_altivec_vspltish, "__builtin_altivec_vspltish", ALTIVEC_BUILTIN_VSPLTISH },
4108 { MASK_ALTIVEC, CODE_FOR_altivec_vspltisw, "__builtin_altivec_vspltisw", ALTIVEC_BUILTIN_VSPLTISW },
20e26713
AH		 4109 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsb, "__builtin_altivec_vupkhsb", ALTIVEC_BUILTIN_VUPKHSB },
4110 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhpx, "__builtin_altivec_vupkhpx", ALTIVEC_BUILTIN_VUPKHPX },
4111 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsh, "__builtin_altivec_vupkhsh", ALTIVEC_BUILTIN_VUPKHSH },
4112 { MASK_ALTIVEC, CODE_FOR_altivec_vupklsb, "__builtin_altivec_vupklsb", ALTIVEC_BUILTIN_VUPKLSB },
4113 { MASK_ALTIVEC, CODE_FOR_altivec_vupklpx, "__builtin_altivec_vupklpx", ALTIVEC_BUILTIN_VUPKLPX },
4114 { MASK_ALTIVEC, CODE_FOR_altivec_vupklsh, "__builtin_altivec_vupklsh", ALTIVEC_BUILTIN_VUPKLSH },
a3170dc6
AH		 4115
4116 /* The SPE unary builtins must start with SPE_BUILTIN_EVABS and
4117 end with SPE_BUILTIN_EVSUBFUSIAAW. */
4118 { 0, CODE_FOR_spe_evabs, "__builtin_spe_evabs", SPE_BUILTIN_EVABS },
4119 { 0, CODE_FOR_spe_evaddsmiaaw, "__builtin_spe_evaddsmiaaw", SPE_BUILTIN_EVADDSMIAAW },
4120 { 0, CODE_FOR_spe_evaddssiaaw, "__builtin_spe_evaddssiaaw", SPE_BUILTIN_EVADDSSIAAW },
4121 { 0, CODE_FOR_spe_evaddumiaaw, "__builtin_spe_evaddumiaaw", SPE_BUILTIN_EVADDUMIAAW },
4122 { 0, CODE_FOR_spe_evaddusiaaw, "__builtin_spe_evaddusiaaw", SPE_BUILTIN_EVADDUSIAAW },
4123 { 0, CODE_FOR_spe_evcntlsw, "__builtin_spe_evcntlsw", SPE_BUILTIN_EVCNTLSW },
4124 { 0, CODE_FOR_spe_evcntlzw, "__builtin_spe_evcntlzw", SPE_BUILTIN_EVCNTLZW },
4125 { 0, CODE_FOR_spe_evextsb, "__builtin_spe_evextsb", SPE_BUILTIN_EVEXTSB },
4126 { 0, CODE_FOR_spe_evextsh, "__builtin_spe_evextsh", SPE_BUILTIN_EVEXTSH },
4127 { 0, CODE_FOR_spe_evfsabs, "__builtin_spe_evfsabs", SPE_BUILTIN_EVFSABS },
4128 { 0, CODE_FOR_spe_evfscfsf, "__builtin_spe_evfscfsf", SPE_BUILTIN_EVFSCFSF },
4129 { 0, CODE_FOR_spe_evfscfsi, "__builtin_spe_evfscfsi", SPE_BUILTIN_EVFSCFSI },
4130 { 0, CODE_FOR_spe_evfscfuf, "__builtin_spe_evfscfuf", SPE_BUILTIN_EVFSCFUF },
4131 { 0, CODE_FOR_spe_evfscfui, "__builtin_spe_evfscfui", SPE_BUILTIN_EVFSCFUI },
4132 { 0, CODE_FOR_spe_evfsctsf, "__builtin_spe_evfsctsf", SPE_BUILTIN_EVFSCTSF },
4133 { 0, CODE_FOR_spe_evfsctsi, "__builtin_spe_evfsctsi", SPE_BUILTIN_EVFSCTSI },
4134 { 0, CODE_FOR_spe_evfsctsiz, "__builtin_spe_evfsctsiz", SPE_BUILTIN_EVFSCTSIZ },
4135 { 0, CODE_FOR_spe_evfsctuf, "__builtin_spe_evfsctuf", SPE_BUILTIN_EVFSCTUF },
4136 { 0, CODE_FOR_spe_evfsctui, "__builtin_spe_evfsctui", SPE_BUILTIN_EVFSCTUI },
4137 { 0, CODE_FOR_spe_evfsctuiz, "__builtin_spe_evfsctuiz", SPE_BUILTIN_EVFSCTUIZ },
4138 { 0, CODE_FOR_spe_evfsnabs, "__builtin_spe_evfsnabs", SPE_BUILTIN_EVFSNABS },
4139 { 0, CODE_FOR_spe_evfsneg, "__builtin_spe_evfsneg", SPE_BUILTIN_EVFSNEG },
4140 { 0, CODE_FOR_spe_evmra, "__builtin_spe_evmra", SPE_BUILTIN_EVMRA },
4141 { 0, CODE_FOR_spe_evneg, "__builtin_spe_evneg", SPE_BUILTIN_EVNEG },
4142 { 0, CODE_FOR_spe_evrndw, "__builtin_spe_evrndw", SPE_BUILTIN_EVRNDW },
4143 { 0, CODE_FOR_spe_evsubfsmiaaw, "__builtin_spe_evsubfsmiaaw", SPE_BUILTIN_EVSUBFSMIAAW },
4144 { 0, CODE_FOR_spe_evsubfssiaaw, "__builtin_spe_evsubfssiaaw", SPE_BUILTIN_EVSUBFSSIAAW },
4145 { 0, CODE_FOR_spe_evsubfumiaaw, "__builtin_spe_evsubfumiaaw", SPE_BUILTIN_EVSUBFUMIAAW },
4146 { 0, CODE_FOR_spe_evsplatfi, "__builtin_spe_evsplatfi", SPE_BUILTIN_EVSPLATFI },
4147 { 0, CODE_FOR_spe_evsplati, "__builtin_spe_evsplati", SPE_BUILTIN_EVSPLATI },
4148
4149 /* Place-holder. Leave as last unary SPE builtin. */
4150 { 0, CODE_FOR_spe_evsubfusiaaw, "__builtin_spe_evsubfusiaaw", SPE_BUILTIN_EVSUBFUSIAAW },
2212663f
DB		 4151};
4152
4153static rtx
92898235 4154rs6000_expand_unop_builtin (icode, arglist, target)
2212663f
DB		 4155 enum insn_code icode;
4156 tree arglist;
4157 rtx target;
4158{
4159 rtx pat;
4160 tree arg0 = TREE_VALUE (arglist);
4161 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
4162 enum machine_mode tmode = insn_data[icode].operand[0].mode;
4163 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
4164
0559cc77
DE		 4165 if (icode == CODE_FOR_nothing)
4166 /* Builtin not supported on this processor. */
4167 return 0;
4168
20e26713
AH		 4169 /* If we got invalid arguments bail out before generating bad rtl. */
4170 if (arg0 == error_mark_node)
9a171fcd 4171 return const0_rtx;
20e26713 4172
0559cc77
DE		 4173 if (icode == CODE_FOR_altivec_vspltisb
4174 || icode == CODE_FOR_altivec_vspltish
4175 || icode == CODE_FOR_altivec_vspltisw
4176 || icode == CODE_FOR_spe_evsplatfi
4177 || icode == CODE_FOR_spe_evsplati)
b44140e7
AH		 4178 {
4179 /* Only allow 5-bit *signed* literals. */
b44140e7
AH		 4180 if (GET_CODE (op0) != CONST_INT
4181 || INTVAL (op0) > 0x1f
4182 || INTVAL (op0) < -0x1f)
4183 {
4184 error ("argument 1 must be a 5-bit signed literal");
9a171fcd 4185 return const0_rtx;
b44140e7 4186 }
b44140e7
AH		 4187 }
4188
c62f2db5 4189 if (target == 0
2212663f
DB		 4190 || GET_MODE (target) != tmode
4191 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
4192 target = gen_reg_rtx (tmode);
4193
4194 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
4195 op0 = copy_to_mode_reg (mode0, op0);
4196
4197 pat = GEN_FCN (icode) (target, op0);
4198 if (! pat)
4199 return 0;
4200 emit_insn (pat);
0ac081f6 4201
2212663f
DB		 4202 return target;
4203}
ae4b4a02 4204
100c4561
AH		 4205static rtx
4206altivec_expand_abs_builtin (icode, arglist, target)
4207 enum insn_code icode;
4208 tree arglist;
4209 rtx target;
4210{
4211 rtx pat, scratch1, scratch2;
4212 tree arg0 = TREE_VALUE (arglist);
4213 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
4214 enum machine_mode tmode = insn_data[icode].operand[0].mode;
4215 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
4216
4217 /* If we have invalid arguments, bail out before generating bad rtl. */
4218 if (arg0 == error_mark_node)
9a171fcd 4219 return const0_rtx;
100c4561
AH		 4220
4221 if (target == 0
4222 || GET_MODE (target) != tmode
4223 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
4224 target = gen_reg_rtx (tmode);
4225
4226 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
4227 op0 = copy_to_mode_reg (mode0, op0);
4228
4229 scratch1 = gen_reg_rtx (mode0);
4230 scratch2 = gen_reg_rtx (mode0);
4231
4232 pat = GEN_FCN (icode) (target, op0, scratch1, scratch2);
4233 if (! pat)
4234 return 0;
4235 emit_insn (pat);
4236
4237 return target;
4238}
4239
0ac081f6 4240static rtx
92898235 4241rs6000_expand_binop_builtin (icode, arglist, target)
0ac081f6
AH		 4242 enum insn_code icode;
4243 tree arglist;
4244 rtx target;
4245{
4246 rtx pat;
4247 tree arg0 = TREE_VALUE (arglist);
4248 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
4249 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
4250 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
4251 enum machine_mode tmode = insn_data[icode].operand[0].mode;
4252 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
4253 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
4254
0559cc77
DE		 4255 if (icode == CODE_FOR_nothing)
4256 /* Builtin not supported on this processor. */
4257 return 0;
4258
20e26713
AH		 4259 /* If we got invalid arguments bail out before generating bad rtl. */
4260 if (arg0 == error_mark_node || arg1 == error_mark_node)
9a171fcd 4261 return const0_rtx;
20e26713 4262
0559cc77
DE		 4263 if (icode == CODE_FOR_altivec_vcfux
4264 || icode == CODE_FOR_altivec_vcfsx
4265 || icode == CODE_FOR_altivec_vctsxs
4266 || icode == CODE_FOR_altivec_vctuxs
4267 || icode == CODE_FOR_altivec_vspltb
4268 || icode == CODE_FOR_altivec_vsplth
4269 || icode == CODE_FOR_altivec_vspltw
4270 || icode == CODE_FOR_spe_evaddiw
4271 || icode == CODE_FOR_spe_evldd
4272 || icode == CODE_FOR_spe_evldh
4273 || icode == CODE_FOR_spe_evldw
4274 || icode == CODE_FOR_spe_evlhhesplat
4275 || icode == CODE_FOR_spe_evlhhossplat
4276 || icode == CODE_FOR_spe_evlhhousplat
4277 || icode == CODE_FOR_spe_evlwhe
4278 || icode == CODE_FOR_spe_evlwhos
4279 || icode == CODE_FOR_spe_evlwhou
4280 || icode == CODE_FOR_spe_evlwhsplat
4281 || icode == CODE_FOR_spe_evlwwsplat
4282 || icode == CODE_FOR_spe_evrlwi
4283 || icode == CODE_FOR_spe_evslwi
4284 || icode == CODE_FOR_spe_evsrwis
4285 || icode == CODE_FOR_spe_evsrwiu)
b44140e7
AH		 4286 {
4287 /* Only allow 5-bit unsigned literals. */
b44140e7
AH		 4288 if (TREE_CODE (arg1) != INTEGER_CST
4289 || TREE_INT_CST_LOW (arg1) & ~0x1f)
4290 {
4291 error ("argument 2 must be a 5-bit unsigned literal");
9a171fcd 4292 return const0_rtx;
b44140e7 4293 }
b44140e7
AH		 4294 }
4295
c62f2db5 4296 if (target == 0
0ac081f6
AH		 4297 || GET_MODE (target) != tmode
4298 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
4299 target = gen_reg_rtx (tmode);
4300
4301 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
4302 op0 = copy_to_mode_reg (mode0, op0);
4303 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
4304 op1 = copy_to_mode_reg (mode1, op1);
4305
4306 pat = GEN_FCN (icode) (target, op0, op1);
4307 if (! pat)
4308 return 0;
4309 emit_insn (pat);
4310
4311 return target;
4312}
6525c0e7 4313
ae4b4a02
AH		 4314static rtx
4315altivec_expand_predicate_builtin (icode, opcode, arglist, target)
4316 enum insn_code icode;
4317 const char *opcode;
4318 tree arglist;
4319 rtx target;
4320{
4321 rtx pat, scratch;
4322 tree cr6_form = TREE_VALUE (arglist);
4323 tree arg0 = TREE_VALUE (TREE_CHAIN (arglist));
4324 tree arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
4325 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
4326 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
4327 enum machine_mode tmode = SImode;
4328 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
4329 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
4330 int cr6_form_int;
4331
4332 if (TREE_CODE (cr6_form) != INTEGER_CST)
4333 {
4334 error ("argument 1 of __builtin_altivec_predicate must be a constant");
9a171fcd 4335 return const0_rtx;
ae4b4a02
AH		 4336 }
4337 else
4338 cr6_form_int = TREE_INT_CST_LOW (cr6_form);
4339
4340 if (mode0 != mode1)
4341 abort ();
4342
4343 /* If we have invalid arguments, bail out before generating bad rtl. */
4344 if (arg0 == error_mark_node || arg1 == error_mark_node)
9a171fcd 4345 return const0_rtx;
ae4b4a02
AH		 4346
4347 if (target == 0
4348 || GET_MODE (target) != tmode
4349 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
4350 target = gen_reg_rtx (tmode);
4351
4352 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
4353 op0 = copy_to_mode_reg (mode0, op0);
4354 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
4355 op1 = copy_to_mode_reg (mode1, op1);
4356
4357 scratch = gen_reg_rtx (mode0);
4358
4359 pat = GEN_FCN (icode) (scratch, op0, op1,
4360 gen_rtx (SYMBOL_REF, Pmode, opcode));
4361 if (! pat)
4362 return 0;
4363 emit_insn (pat);
4364
4365 /* The vec_any* and vec_all* predicates use the same opcodes for two
4366 different operations, but the bits in CR6 will be different
4367 depending on what information we want. So we have to play tricks
4368 with CR6 to get the right bits out.
4369
4370 If you think this is disgusting, look at the specs for the
4371 AltiVec predicates. */
4372
4373 switch (cr6_form_int)
4374 {
4375 case 0:
4376 emit_insn (gen_cr6_test_for_zero (target));
4377 break;
4378 case 1:
4379 emit_insn (gen_cr6_test_for_zero_reverse (target));
4380 break;
4381 case 2:
4382 emit_insn (gen_cr6_test_for_lt (target));
4383 break;
4384 case 3:
4385 emit_insn (gen_cr6_test_for_lt_reverse (target));
4386 break;
4387 default:
4388 error ("argument 1 of __builtin_altivec_predicate is out of range");
4389 break;
4390 }
4391
4392 return target;
4393}
4394
6525c0e7
AH		 4395static rtx
4396altivec_expand_stv_builtin (icode, arglist)
4397 enum insn_code icode;
4398 tree arglist;
4399{
4400 tree arg0 = TREE_VALUE (arglist);
4401 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
4402 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
4403 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
4404 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
4405 rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
4406 rtx pat;
4407 enum machine_mode mode0 = insn_data[icode].operand[0].mode;
4408 enum machine_mode mode1 = insn_data[icode].operand[1].mode;
4409 enum machine_mode mode2 = insn_data[icode].operand[2].mode;
4410
4411 /* Invalid arguments. Bail before doing anything stoopid! */
4412 if (arg0 == error_mark_node
4413 || arg1 == error_mark_node
4414 || arg2 == error_mark_node)
9a171fcd 4415 return const0_rtx;
6525c0e7
AH		 4416
4417 if (! (*insn_data[icode].operand[2].predicate) (op0, mode2))
4418 op0 = copy_to_mode_reg (mode2, op0);
4419 if (! (*insn_data[icode].operand[0].predicate) (op1, mode0))
4420 op1 = copy_to_mode_reg (mode0, op1);
4421 if (! (*insn_data[icode].operand[1].predicate) (op2, mode1))
4422 op2 = copy_to_mode_reg (mode1, op2);
4423
4424 pat = GEN_FCN (icode) (op1, op2, op0);
4425 if (pat)
4426 emit_insn (pat);
4427 return NULL_RTX;
4428}
4429
2212663f 4430static rtx
92898235 4431rs6000_expand_ternop_builtin (icode, arglist, target)
2212663f
DB		 4432 enum insn_code icode;
4433 tree arglist;
4434 rtx target;
4435{
4436 rtx pat;
4437 tree arg0 = TREE_VALUE (arglist);
4438 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
4439 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
4440 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
4441 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
4442 rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
4443 enum machine_mode tmode = insn_data[icode].operand[0].mode;
4444 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
4445 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
4446 enum machine_mode mode2 = insn_data[icode].operand[3].mode;
0ac081f6 4447
774b5662
DE		 4448 if (icode == CODE_FOR_nothing)
4449 /* Builtin not supported on this processor. */
4450 return 0;
4451
20e26713
AH		 4452 /* If we got invalid arguments bail out before generating bad rtl. */
4453 if (arg0 == error_mark_node
4454 || arg1 == error_mark_node
4455 || arg2 == error_mark_node)
9a171fcd 4456 return const0_rtx;
20e26713 4457
774b5662
DE		 4458 if (icode == CODE_FOR_altivec_vsldoi_4sf
4459 || icode == CODE_FOR_altivec_vsldoi_4si
4460 || icode == CODE_FOR_altivec_vsldoi_8hi
4461 || icode == CODE_FOR_altivec_vsldoi_16qi)
b44140e7
AH		 4462 {
4463 /* Only allow 4-bit unsigned literals. */
b44140e7
AH		 4464 if (TREE_CODE (arg2) != INTEGER_CST
4465 || TREE_INT_CST_LOW (arg2) & ~0xf)
4466 {
4467 error ("argument 3 must be a 4-bit unsigned literal");
e3277ffb 4468 return const0_rtx;
b44140e7 4469 }
b44140e7
AH		 4470 }
4471
c62f2db5 4472 if (target == 0
2212663f
DB		 4473 || GET_MODE (target) != tmode
4474 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
4475 target = gen_reg_rtx (tmode);
4476
4477 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
4478 op0 = copy_to_mode_reg (mode0, op0);
4479 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
4480 op1 = copy_to_mode_reg (mode1, op1);
4481 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
4482 op2 = copy_to_mode_reg (mode2, op2);
4483
4484 pat = GEN_FCN (icode) (target, op0, op1, op2);
4485 if (! pat)
4486 return 0;
4487 emit_insn (pat);
4488
4489 return target;
4490}
92898235 4491
3a9b8c7e 4492/* Expand the lvx builtins. */
0ac081f6 4493static rtx
3a9b8c7e 4494altivec_expand_ld_builtin (exp, target, expandedp)
0ac081f6
AH		 4495 tree exp;
4496 rtx target;
92898235 4497 bool *expandedp;
0ac081f6 4498{
0ac081f6
AH		 4499 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
4500 tree arglist = TREE_OPERAND (exp, 1);
0ac081f6 4501 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
3a9b8c7e
AH		 4502 tree arg0;
4503 enum machine_mode tmode, mode0;
7c3abc73 4504 rtx pat, op0;
3a9b8c7e 4505 enum insn_code icode;
92898235 4506
0ac081f6
AH		 4507 switch (fcode)
4508 {
f18c054f
DB		 4509 case ALTIVEC_BUILTIN_LD_INTERNAL_16qi:
4510 icode = CODE_FOR_altivec_lvx_16qi;
3a9b8c7e 4511 break;
f18c054f
DB		 4512 case ALTIVEC_BUILTIN_LD_INTERNAL_8hi:
4513 icode = CODE_FOR_altivec_lvx_8hi;
3a9b8c7e
AH		 4514 break;
4515 case ALTIVEC_BUILTIN_LD_INTERNAL_4si:
4516 icode = CODE_FOR_altivec_lvx_4si;
4517 break;
4518 case ALTIVEC_BUILTIN_LD_INTERNAL_4sf:
4519 icode = CODE_FOR_altivec_lvx_4sf;
4520 break;
4521 default:
4522 *expandedp = false;
4523 return NULL_RTX;
4524 }
0ac081f6 4525
3a9b8c7e 4526 *expandedp = true;
f18c054f 4527
3a9b8c7e
AH		 4528 arg0 = TREE_VALUE (arglist);
4529 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
4530 tmode = insn_data[icode].operand[0].mode;
4531 mode0 = insn_data[icode].operand[1].mode;
f18c054f 4532
3a9b8c7e
AH		 4533 if (target == 0
4534 || GET_MODE (target) != tmode
4535 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
4536 target = gen_reg_rtx (tmode);
24408032 4537
3a9b8c7e
AH		 4538 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
4539 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
f18c054f 4540
3a9b8c7e
AH		 4541 pat = GEN_FCN (icode) (target, op0);
4542 if (! pat)
4543 return 0;
4544 emit_insn (pat);
4545 return target;
4546}
f18c054f 4547
3a9b8c7e
AH		 4548/* Expand the stvx builtins. */
4549static rtx
4550altivec_expand_st_builtin (exp, target, expandedp)
4551 tree exp;
7c3abc73 4552 rtx target ATTRIBUTE_UNUSED;
3a9b8c7e
AH		 4553 bool *expandedp;
4554{
4555 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
4556 tree arglist = TREE_OPERAND (exp, 1);
4557 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
4558 tree arg0, arg1;
4559 enum machine_mode mode0, mode1;
7c3abc73 4560 rtx pat, op0, op1;
3a9b8c7e 4561 enum insn_code icode;
f18c054f 4562
3a9b8c7e
AH		 4563 switch (fcode)
4564 {
4565 case ALTIVEC_BUILTIN_ST_INTERNAL_16qi:
4566 icode = CODE_FOR_altivec_stvx_16qi;
4567 break;
4568 case ALTIVEC_BUILTIN_ST_INTERNAL_8hi:
4569 icode = CODE_FOR_altivec_stvx_8hi;
4570 break;
4571 case ALTIVEC_BUILTIN_ST_INTERNAL_4si:
4572 icode = CODE_FOR_altivec_stvx_4si;
4573 break;
4574 case ALTIVEC_BUILTIN_ST_INTERNAL_4sf:
4575 icode = CODE_FOR_altivec_stvx_4sf;
4576 break;
4577 default:
4578 *expandedp = false;
4579 return NULL_RTX;
4580 }
24408032 4581
3a9b8c7e
AH		 4582 arg0 = TREE_VALUE (arglist);
4583 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
4584 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
4585 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
4586 mode0 = insn_data[icode].operand[0].mode;
4587 mode1 = insn_data[icode].operand[1].mode;
f18c054f 4588
3a9b8c7e
AH		 4589 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
4590 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
4591 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
4592 op1 = copy_to_mode_reg (mode1, op1);
f18c054f 4593
3a9b8c7e
AH		 4594 pat = GEN_FCN (icode) (op0, op1);
4595 if (pat)
4596 emit_insn (pat);
f18c054f 4597
3a9b8c7e
AH		 4598 *expandedp = true;
4599 return NULL_RTX;
4600}
f18c054f 4601
3a9b8c7e
AH		 4602/* Expand the dst builtins. */
4603static rtx
4604altivec_expand_dst_builtin (exp, target, expandedp)
4605 tree exp;
7c3abc73 4606 rtx target ATTRIBUTE_UNUSED;
3a9b8c7e
AH		 4607 bool *expandedp;
4608{
4609 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
4610 tree arglist = TREE_OPERAND (exp, 1);
4611 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
4612 tree arg0, arg1, arg2;
4613 enum machine_mode mode0, mode1, mode2;
7c3abc73 4614 rtx pat, op0, op1, op2;
3a9b8c7e 4615 struct builtin_description *d;
a3170dc6 4616 size_t i;
f18c054f 4617
3a9b8c7e 4618 *expandedp = false;
f18c054f 4619
3a9b8c7e
AH		 4620 /* Handle DST variants. */
4621 d = (struct builtin_description *) bdesc_dst;
4622 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
4623 if (d->code == fcode)
4624 {
4625 arg0 = TREE_VALUE (arglist);
4626 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
4627 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
4628 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
4629 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
4630 op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
4631 mode0 = insn_data[d->icode].operand[0].mode;
4632 mode1 = insn_data[d->icode].operand[1].mode;
4633 mode2 = insn_data[d->icode].operand[2].mode;
24408032 4634
3a9b8c7e
AH		 4635 /* Invalid arguments, bail out before generating bad rtl. */
4636 if (arg0 == error_mark_node
4637 || arg1 == error_mark_node
4638 || arg2 == error_mark_node)
4639 return const0_rtx;
f18c054f 4640
3a9b8c7e
AH		 4641 if (TREE_CODE (arg2) != INTEGER_CST
4642 || TREE_INT_CST_LOW (arg2) & ~0x3)
4643 {
4644 error ("argument to `%s' must be a 2-bit unsigned literal", d->name);
4645 return const0_rtx;
4646 }
f18c054f 4647
3a9b8c7e
AH		 4648 if (! (*insn_data[d->icode].operand[0].predicate) (op0, mode0))
4649 op0 = copy_to_mode_reg (mode0, op0);
4650 if (! (*insn_data[d->icode].operand[1].predicate) (op1, mode1))
4651 op1 = copy_to_mode_reg (mode1, op1);
24408032 4652
3a9b8c7e
AH		 4653 pat = GEN_FCN (d->icode) (op0, op1, op2);
4654 if (pat != 0)
4655 emit_insn (pat);
f18c054f 4656
3a9b8c7e
AH		 4657 *expandedp = true;
4658 return NULL_RTX;
4659 }
f18c054f 4660
3a9b8c7e
AH		 4661 return NULL_RTX;
4662}
24408032 4663
3a9b8c7e
AH		 4664/* Expand the builtin in EXP and store the result in TARGET. Store
4665 true in *EXPANDEDP if we found a builtin to expand. */
4666static rtx
4667altivec_expand_builtin (exp, target, expandedp)
4668 tree exp;
4669 rtx target;
4670 bool *expandedp;
4671{
4672 struct builtin_description *d;
4673 struct builtin_description_predicates *dp;
4674 size_t i;
4675 enum insn_code icode;
4676 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
4677 tree arglist = TREE_OPERAND (exp, 1);
7c3abc73
AH		 4678 tree arg0;
4679 rtx op0, pat;
4680 enum machine_mode tmode, mode0;
3a9b8c7e 4681 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
0ac081f6 4682
3a9b8c7e
AH		 4683 target = altivec_expand_ld_builtin (exp, target, expandedp);
4684 if (*expandedp)
4685 return target;
0ac081f6 4686
3a9b8c7e
AH		 4687 target = altivec_expand_st_builtin (exp, target, expandedp);
4688 if (*expandedp)
4689 return target;
4690
4691 target = altivec_expand_dst_builtin (exp, target, expandedp);
4692 if (*expandedp)
4693 return target;
4694
4695 *expandedp = true;
95385cbb 4696
3a9b8c7e
AH		 4697 switch (fcode)
4698 {
6525c0e7
AH		 4699 case ALTIVEC_BUILTIN_STVX:
4700 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx, arglist);
4701 case ALTIVEC_BUILTIN_STVEBX:
4702 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx, arglist);
4703 case ALTIVEC_BUILTIN_STVEHX:
4704 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx, arglist);
4705 case ALTIVEC_BUILTIN_STVEWX:
4706 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx, arglist);
4707 case ALTIVEC_BUILTIN_STVXL:
4708 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl, arglist);
3a9b8c7e 4709
95385cbb
AH		 4710 case ALTIVEC_BUILTIN_MFVSCR:
4711 icode = CODE_FOR_altivec_mfvscr;
4712 tmode = insn_data[icode].operand[0].mode;
4713
4714 if (target == 0
4715 || GET_MODE (target) != tmode
4716 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
4717 target = gen_reg_rtx (tmode);
4718
4719 pat = GEN_FCN (icode) (target);
0ac081f6
AH		 4720 if (! pat)
4721 return 0;
4722 emit_insn (pat);
95385cbb
AH		 4723 return target;
4724
4725 case ALTIVEC_BUILTIN_MTVSCR:
4726 icode = CODE_FOR_altivec_mtvscr;
4727 arg0 = TREE_VALUE (arglist);
4728 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
4729 mode0 = insn_data[icode].operand[0].mode;
4730
4731 /* If we got invalid arguments bail out before generating bad rtl. */
4732 if (arg0 == error_mark_node)
9a171fcd 4733 return const0_rtx;
95385cbb
AH		 4734
4735 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
4736 op0 = copy_to_mode_reg (mode0, op0);
4737
4738 pat = GEN_FCN (icode) (op0);
4739 if (pat)
4740 emit_insn (pat);
4741 return NULL_RTX;
3a9b8c7e 4742
95385cbb
AH		 4743 case ALTIVEC_BUILTIN_DSSALL:
4744 emit_insn (gen_altivec_dssall ());
4745 return NULL_RTX;
4746
4747 case ALTIVEC_BUILTIN_DSS:
4748 icode = CODE_FOR_altivec_dss;
4749 arg0 = TREE_VALUE (arglist);
4750 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
4751 mode0 = insn_data[icode].operand[0].mode;
4752
4753 /* If we got invalid arguments bail out before generating bad rtl. */
4754 if (arg0 == error_mark_node)
9a171fcd 4755 return const0_rtx;
95385cbb 4756
b44140e7
AH		 4757 if (TREE_CODE (arg0) != INTEGER_CST
4758 || TREE_INT_CST_LOW (arg0) & ~0x3)
4759 {
4760 error ("argument to dss must be a 2-bit unsigned literal");
9a171fcd 4761 return const0_rtx;
b44140e7
AH		 4762 }
4763
95385cbb
AH		 4764 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
4765 op0 = copy_to_mode_reg (mode0, op0);
4766
4767 emit_insn (gen_altivec_dss (op0));
0ac081f6
AH		 4768 return NULL_RTX;
4769 }
24408032 4770
100c4561
AH		 4771 /* Expand abs* operations. */
4772 d = (struct builtin_description *) bdesc_abs;
ca7558fc 4773 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
100c4561
AH		 4774 if (d->code == fcode)
4775 return altivec_expand_abs_builtin (d->icode, arglist, target);
4776
ae4b4a02
AH		 4777 /* Expand the AltiVec predicates. */
4778 dp = (struct builtin_description_predicates *) bdesc_altivec_preds;
ca7558fc 4779 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++)
ae4b4a02
AH		 4780 if (dp->code == fcode)
4781 return altivec_expand_predicate_builtin (dp->icode, dp->opcode, arglist, target);
4782
6525c0e7
AH		 4783 /* LV* are funky. We initialized them differently. */
4784 switch (fcode)
4785 {
4786 case ALTIVEC_BUILTIN_LVSL:
92898235 4787 return rs6000_expand_binop_builtin (CODE_FOR_altivec_lvsl,
6525c0e7
AH		 4788 arglist, target);
4789 case ALTIVEC_BUILTIN_LVSR:
92898235
AH		 4790 return rs6000_expand_binop_builtin (CODE_FOR_altivec_lvsr,
4791 arglist, target);
6525c0e7 4792 case ALTIVEC_BUILTIN_LVEBX:
92898235
AH		 4793 return rs6000_expand_binop_builtin (CODE_FOR_altivec_lvebx,
4794 arglist, target);
6525c0e7 4795 case ALTIVEC_BUILTIN_LVEHX:
92898235
AH		 4796 return rs6000_expand_binop_builtin (CODE_FOR_altivec_lvehx,
4797 arglist, target);
6525c0e7 4798 case ALTIVEC_BUILTIN_LVEWX:
92898235
AH		 4799 return rs6000_expand_binop_builtin (CODE_FOR_altivec_lvewx,
4800 arglist, target);
6525c0e7 4801 case ALTIVEC_BUILTIN_LVXL:
92898235
AH		 4802 return rs6000_expand_binop_builtin (CODE_FOR_altivec_lvxl,
4803 arglist, target);
6525c0e7 4804 case ALTIVEC_BUILTIN_LVX:
92898235
AH		 4805 return rs6000_expand_binop_builtin (CODE_FOR_altivec_lvx,
4806 arglist, target);
6525c0e7
AH		 4807 default:
4808 break;
4809 /* Fall through. */
4810 }
95385cbb 4811
92898235 4812 *expandedp = false;
0ac081f6
AH		 4813 return NULL_RTX;
4814}
4815
a3170dc6
AH		 4816/* Binops that need to be initialized manually, but can be expanded
4817 automagically by rs6000_expand_binop_builtin. */
4818static struct builtin_description bdesc_2arg_spe[] =
4819{
4820 { 0, CODE_FOR_spe_evlddx, "__builtin_spe_evlddx", SPE_BUILTIN_EVLDDX },
4821 { 0, CODE_FOR_spe_evldwx, "__builtin_spe_evldwx", SPE_BUILTIN_EVLDWX },
4822 { 0, CODE_FOR_spe_evldhx, "__builtin_spe_evldhx", SPE_BUILTIN_EVLDHX },
4823 { 0, CODE_FOR_spe_evlwhex, "__builtin_spe_evlwhex", SPE_BUILTIN_EVLWHEX },
4824 { 0, CODE_FOR_spe_evlwhoux, "__builtin_spe_evlwhoux", SPE_BUILTIN_EVLWHOUX },
4825 { 0, CODE_FOR_spe_evlwhosx, "__builtin_spe_evlwhosx", SPE_BUILTIN_EVLWHOSX },
4826 { 0, CODE_FOR_spe_evlwwsplatx, "__builtin_spe_evlwwsplatx", SPE_BUILTIN_EVLWWSPLATX },
4827 { 0, CODE_FOR_spe_evlwhsplatx, "__builtin_spe_evlwhsplatx", SPE_BUILTIN_EVLWHSPLATX },
4828 { 0, CODE_FOR_spe_evlhhesplatx, "__builtin_spe_evlhhesplatx", SPE_BUILTIN_EVLHHESPLATX },
4829 { 0, CODE_FOR_spe_evlhhousplatx, "__builtin_spe_evlhhousplatx", SPE_BUILTIN_EVLHHOUSPLATX },
4830 { 0, CODE_FOR_spe_evlhhossplatx, "__builtin_spe_evlhhossplatx", SPE_BUILTIN_EVLHHOSSPLATX },
4831 { 0, CODE_FOR_spe_evldd, "__builtin_spe_evldd", SPE_BUILTIN_EVLDD },
4832 { 0, CODE_FOR_spe_evldw, "__builtin_spe_evldw", SPE_BUILTIN_EVLDW },
4833 { 0, CODE_FOR_spe_evldh, "__builtin_spe_evldh", SPE_BUILTIN_EVLDH },
4834 { 0, CODE_FOR_spe_evlwhe, "__builtin_spe_evlwhe", SPE_BUILTIN_EVLWHE },
4835 { 0, CODE_FOR_spe_evlwhou, "__builtin_spe_evlwhou", SPE_BUILTIN_EVLWHOU },
4836 { 0, CODE_FOR_spe_evlwhos, "__builtin_spe_evlwhos", SPE_BUILTIN_EVLWHOS },
4837 { 0, CODE_FOR_spe_evlwwsplat, "__builtin_spe_evlwwsplat", SPE_BUILTIN_EVLWWSPLAT },
4838 { 0, CODE_FOR_spe_evlwhsplat, "__builtin_spe_evlwhsplat", SPE_BUILTIN_EVLWHSPLAT },
4839 { 0, CODE_FOR_spe_evlhhesplat, "__builtin_spe_evlhhesplat", SPE_BUILTIN_EVLHHESPLAT },
4840 { 0, CODE_FOR_spe_evlhhousplat, "__builtin_spe_evlhhousplat", SPE_BUILTIN_EVLHHOUSPLAT },
4841 { 0, CODE_FOR_spe_evlhhossplat, "__builtin_spe_evlhhossplat", SPE_BUILTIN_EVLHHOSSPLAT }
4842};
4843
4844/* Expand the builtin in EXP and store the result in TARGET. Store
4845 true in *EXPANDEDP if we found a builtin to expand.
4846
4847 This expands the SPE builtins that are not simple unary and binary
4848 operations. */
4849static rtx
4850spe_expand_builtin (exp, target, expandedp)
4851 tree exp;
4852 rtx target;
4853 bool *expandedp;
4854{
4855 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
4856 tree arglist = TREE_OPERAND (exp, 1);
4857 tree arg1, arg0;
4858 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
4859 enum insn_code icode;
4860 enum machine_mode tmode, mode0;
4861 rtx pat, op0;
4862 struct builtin_description *d;
4863 size_t i;
4864
4865 *expandedp = true;
4866
4867 /* Syntax check for a 5-bit unsigned immediate. */
4868 switch (fcode)
4869 {
4870 case SPE_BUILTIN_EVSTDD:
4871 case SPE_BUILTIN_EVSTDH:
4872 case SPE_BUILTIN_EVSTDW:
4873 case SPE_BUILTIN_EVSTWHE:
4874 case SPE_BUILTIN_EVSTWHO:
4875 case SPE_BUILTIN_EVSTWWE:
4876 case SPE_BUILTIN_EVSTWWO:
4877 arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
4878 if (TREE_CODE (arg1) != INTEGER_CST
4879 || TREE_INT_CST_LOW (arg1) & ~0x1f)
4880 {
4881 error ("argument 2 must be a 5-bit unsigned literal");
4882 return const0_rtx;
4883 }
4884 break;
4885 default:
4886 break;
4887 }
4888
4889 d = (struct builtin_description *) bdesc_2arg_spe;
4890 for (i = 0; i < ARRAY_SIZE (bdesc_2arg_spe); ++i, ++d)
4891 if (d->code == fcode)
4892 return rs6000_expand_binop_builtin (d->icode, arglist, target);
4893
4894 d = (struct builtin_description *) bdesc_spe_predicates;
4895 for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, ++d)
4896 if (d->code == fcode)
4897 return spe_expand_predicate_builtin (d->icode, arglist, target);
4898
4899 d = (struct builtin_description *) bdesc_spe_evsel;
4900 for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, ++d)
4901 if (d->code == fcode)
4902 return spe_expand_evsel_builtin (d->icode, arglist, target);
4903
4904 switch (fcode)
4905 {
4906 case SPE_BUILTIN_EVSTDDX:
4907 return altivec_expand_stv_builtin (CODE_FOR_spe_evstddx, arglist);
4908 case SPE_BUILTIN_EVSTDHX:
4909 return altivec_expand_stv_builtin (CODE_FOR_spe_evstdhx, arglist);
4910 case SPE_BUILTIN_EVSTDWX:
4911 return altivec_expand_stv_builtin (CODE_FOR_spe_evstdwx, arglist);
4912 case SPE_BUILTIN_EVSTWHEX:
4913 return altivec_expand_stv_builtin (CODE_FOR_spe_evstwhex, arglist);
4914 case SPE_BUILTIN_EVSTWHOX:
4915 return altivec_expand_stv_builtin (CODE_FOR_spe_evstwhox, arglist);
4916 case SPE_BUILTIN_EVSTWWEX:
4917 return altivec_expand_stv_builtin (CODE_FOR_spe_evstwwex, arglist);
4918 case SPE_BUILTIN_EVSTWWOX:
4919 return altivec_expand_stv_builtin (CODE_FOR_spe_evstwwox, arglist);
4920 case SPE_BUILTIN_EVSTDD:
4921 return altivec_expand_stv_builtin (CODE_FOR_spe_evstdd, arglist);
4922 case SPE_BUILTIN_EVSTDH:
4923 return altivec_expand_stv_builtin (CODE_FOR_spe_evstdh, arglist);
4924 case SPE_BUILTIN_EVSTDW:
4925 return altivec_expand_stv_builtin (CODE_FOR_spe_evstdw, arglist);
4926 case SPE_BUILTIN_EVSTWHE:
4927 return altivec_expand_stv_builtin (CODE_FOR_spe_evstwhe, arglist);
4928 case SPE_BUILTIN_EVSTWHO:
4929 return altivec_expand_stv_builtin (CODE_FOR_spe_evstwho, arglist);
4930 case SPE_BUILTIN_EVSTWWE:
4931 return altivec_expand_stv_builtin (CODE_FOR_spe_evstwwe, arglist);
4932 case SPE_BUILTIN_EVSTWWO:
4933 return altivec_expand_stv_builtin (CODE_FOR_spe_evstwwo, arglist);
4934 case SPE_BUILTIN_MFSPEFSCR:
4935 icode = CODE_FOR_spe_mfspefscr;
4936 tmode = insn_data[icode].operand[0].mode;
4937
4938 if (target == 0
4939 || GET_MODE (target) != tmode
4940 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
4941 target = gen_reg_rtx (tmode);
4942
4943 pat = GEN_FCN (icode) (target);
4944 if (! pat)
4945 return 0;
4946 emit_insn (pat);
4947 return target;
4948 case SPE_BUILTIN_MTSPEFSCR:
4949 icode = CODE_FOR_spe_mtspefscr;
4950 arg0 = TREE_VALUE (arglist);
4951 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
4952 mode0 = insn_data[icode].operand[0].mode;
4953
4954 if (arg0 == error_mark_node)
4955 return const0_rtx;
4956
4957 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
4958 op0 = copy_to_mode_reg (mode0, op0);
4959
4960 pat = GEN_FCN (icode) (op0);
4961 if (pat)
4962 emit_insn (pat);
4963 return NULL_RTX;
4964 default:
4965 break;
4966 }
4967
4968 *expandedp = false;
4969 return NULL_RTX;
4970}
4971
4972static rtx
4973spe_expand_predicate_builtin (icode, arglist, target)
4974 enum insn_code icode;
4975 tree arglist;
4976 rtx target;
4977{
4978 rtx pat, scratch, tmp;
4979 tree form = TREE_VALUE (arglist);
4980 tree arg0 = TREE_VALUE (TREE_CHAIN (arglist));
4981 tree arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
4982 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
4983 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
4984 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
4985 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
4986 int form_int;
4987 enum rtx_code code;
4988
4989 if (TREE_CODE (form) != INTEGER_CST)
4990 {
4991 error ("argument 1 of __builtin_spe_predicate must be a constant");
4992 return const0_rtx;
4993 }
4994 else
4995 form_int = TREE_INT_CST_LOW (form);
4996
4997 if (mode0 != mode1)
4998 abort ();
4999
5000 if (arg0 == error_mark_node || arg1 == error_mark_node)
5001 return const0_rtx;
5002
5003 if (target == 0
5004 || GET_MODE (target) != SImode
5005 || ! (*insn_data[icode].operand[0].predicate) (target, SImode))
5006 target = gen_reg_rtx (SImode);
5007
5008 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
5009 op0 = copy_to_mode_reg (mode0, op0);
5010 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
5011 op1 = copy_to_mode_reg (mode1, op1);
5012
5013 scratch = gen_reg_rtx (CCmode);
5014
5015 pat = GEN_FCN (icode) (scratch, op0, op1);
5016 if (! pat)
5017 return const0_rtx;
5018 emit_insn (pat);
5019
5020 /* There are 4 variants for each predicate: _any_, _all_, _upper_,
5021 _lower_. We use one compare, but look in different bits of the
5022 CR for each variant.
5023
5024 There are 2 elements in each SPE simd type (upper/lower). The CR
5025 bits are set as follows:
5026
5027 BIT0 | BIT 1 | BIT 2 | BIT 3
5028 U | L | (U | L) | (U & L)
5029
5030 So, for an "all" relationship, BIT 3 would be set.
5031 For an "any" relationship, BIT 2 would be set. Etc.
5032
5033 Following traditional nomenclature, these bits map to:
5034
5035 BIT0 | BIT 1 | BIT 2 | BIT 3
5036 LT | GT | EQ | OV
5037
5038 Later, we will generate rtl to look in the LT/EQ/EQ/OV bits.
5039 */
5040
5041 switch (form_int)
5042 {
5043 /* All variant. OV bit. */
5044 case 0:
5045 /* We need to get to the OV bit, which is the ORDERED bit. We
5046 could generate (ordered:SI (reg:CC xx) (const_int 0)), but
5047 that's ugly and will trigger a validate_condition_mode abort.
5048 So let's just use another pattern. */
5049 emit_insn (gen_move_from_CR_ov_bit (target, scratch));
5050 return target;
5051 /* Any variant. EQ bit. */
5052 case 1:
5053 code = EQ;
5054 break;
5055 /* Upper variant. LT bit. */
5056 case 2:
5057 code = LT;
5058 break;
5059 /* Lower variant. GT bit. */
5060 case 3:
5061 code = GT;
5062 break;
5063 default:
5064 error ("argument 1 of __builtin_spe_predicate is out of range");
5065 return const0_rtx;
5066 }
5067
5068 tmp = gen_rtx_fmt_ee (code, SImode, scratch, const0_rtx);
5069 emit_move_insn (target, tmp);
5070
5071 return target;
5072}
5073
5074/* The evsel builtins look like this:
5075
5076 e = __builtin_spe_evsel_OP (a, b, c, d);
5077
5078 and work like this:
5079
5080 e[upper] = a[upper] *OP* b[upper] ? c[upper] : d[upper];
5081 e[lower] = a[lower] *OP* b[lower] ? c[lower] : d[lower];
5082*/
5083
5084static rtx
5085spe_expand_evsel_builtin (icode, arglist, target)
5086 enum insn_code icode;
5087 tree arglist;
5088 rtx target;
5089{
5090 rtx pat, scratch;
5091 tree arg0 = TREE_VALUE (arglist);
5092 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
5093 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
5094 tree arg3 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (TREE_CHAIN (arglist))));
5095 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
5096 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
5097 rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
5098 rtx op3 = expand_expr (arg3, NULL_RTX, VOIDmode, 0);
5099 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
5100 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
5101
5102 if (mode0 != mode1)
5103 abort ();
5104
5105 if (arg0 == error_mark_node || arg1 == error_mark_node
5106 || arg2 == error_mark_node || arg3 == error_mark_node)
5107 return const0_rtx;
5108
5109 if (target == 0
5110 || GET_MODE (target) != mode0
5111 || ! (*insn_data[icode].operand[0].predicate) (target, mode0))
5112 target = gen_reg_rtx (mode0);
5113
5114 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
5115 op0 = copy_to_mode_reg (mode0, op0);
5116 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
5117 op1 = copy_to_mode_reg (mode0, op1);
5118 if (! (*insn_data[icode].operand[1].predicate) (op2, mode1))
5119 op2 = copy_to_mode_reg (mode0, op2);
5120 if (! (*insn_data[icode].operand[1].predicate) (op3, mode1))
5121 op3 = copy_to_mode_reg (mode0, op3);
5122
5123 /* Generate the compare. */
5124 scratch = gen_reg_rtx (CCmode);
5125 pat = GEN_FCN (icode) (scratch, op0, op1);
5126 if (! pat)
5127 return const0_rtx;
5128 emit_insn (pat);
5129
5130 if (mode0 == V2SImode)
5131 emit_insn (gen_spe_evsel (target, op2, op3, scratch));
5132 else
5133 emit_insn (gen_spe_evsel_fs (target, op2, op3, scratch));
5134
5135 return target;
5136}
5137
0ac081f6
AH		 5138/* Expand an expression EXP that calls a built-in function,
5139 with result going to TARGET if that's convenient
5140 (and in mode MODE if that's convenient).
5141 SUBTARGET may be used as the target for computing one of EXP's operands.
5142 IGNORE is nonzero if the value is to be ignored. */
5143
5144static rtx
5145rs6000_expand_builtin (exp, target, subtarget, mode, ignore)
5146 tree exp;
5147 rtx target;
00b960c7
AH		 5148 rtx subtarget ATTRIBUTE_UNUSED;
5149 enum machine_mode mode ATTRIBUTE_UNUSED;
5150 int ignore ATTRIBUTE_UNUSED;
0ac081f6 5151{
92898235
AH		 5152 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
5153 tree arglist = TREE_OPERAND (exp, 1);
5154 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
5155 struct builtin_description *d;
5156 size_t i;
5157 rtx ret;
5158 bool success;
5159
0ac081f6 5160 if (TARGET_ALTIVEC)
92898235
AH		 5161 {
5162 ret = altivec_expand_builtin (exp, target, &success);
5163
a3170dc6
AH		 5164 if (success)
5165 return ret;
5166 }
5167 if (TARGET_SPE)
5168 {
5169 ret = spe_expand_builtin (exp, target, &success);
5170
92898235
AH		 5171 if (success)
5172 return ret;
5173 }
5174
0559cc77
DE		 5175 if (TARGET_ALTIVEC || TARGET_SPE)
5176 {
5177 /* Handle simple unary operations. */
5178 d = (struct builtin_description *) bdesc_1arg;
5179 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
5180 if (d->code == fcode)
5181 return rs6000_expand_unop_builtin (d->icode, arglist, target);
5182
5183 /* Handle simple binary operations. */
5184 d = (struct builtin_description *) bdesc_2arg;
5185 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
5186 if (d->code == fcode)
5187 return rs6000_expand_binop_builtin (d->icode, arglist, target);
5188
5189 /* Handle simple ternary operations. */
5190 d = (struct builtin_description *) bdesc_3arg;
5191 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
5192 if (d->code == fcode)
5193 return rs6000_expand_ternop_builtin (d->icode, arglist, target);
5194 }
0ac081f6
AH		 5195
5196 abort ();
92898235 5197 return NULL_RTX;
0ac081f6
AH		 5198}
5199
5200static void
6fa3f289 5201rs6000_init_builtins ()
0ac081f6 5202{
a3170dc6
AH		 5203 if (TARGET_SPE)
5204 spe_init_builtins ();
0ac081f6
AH		 5205 if (TARGET_ALTIVEC)
5206 altivec_init_builtins ();
0559cc77
DE		 5207 if (TARGET_ALTIVEC || TARGET_SPE)
5208 rs6000_common_init_builtins ();
0ac081f6
AH		 5209}
5210
a3170dc6
AH		 5211/* Search through a set of builtins and enable the mask bits.
5212 DESC is an array of builtins.
5213 SIZE is the totaly number of builtins.
5214 START is the builtin enum at which to start.
5215 END is the builtin enum at which to end. */
0ac081f6 5216static void
a3170dc6
AH		 5217enable_mask_for_builtins (desc, size, start, end)
5218 struct builtin_description *desc;
5219 int size;
5220 enum rs6000_builtins start, end;
5221{
5222 int i;
5223
5224 for (i = 0; i < size; ++i)
5225 if (desc[i].code == start)
5226 break;
5227
5228 if (i == size)
5229 return;
5230
5231 for (; i < size; ++i)
5232 {
5233 /* Flip all the bits on. */
5234 desc[i].mask = target_flags;
5235 if (desc[i].code == end)
5236 break;
5237 }
5238}
5239
5240static void
b24c9d35 5241spe_init_builtins ()
0ac081f6 5242{
a3170dc6
AH		 5243 tree endlink = void_list_node;
5244 tree puint_type_node = build_pointer_type (unsigned_type_node);
5245 tree pushort_type_node = build_pointer_type (short_unsigned_type_node);
5246 tree pv2si_type_node = build_pointer_type (V2SI_type_node);
ae4b4a02 5247 struct builtin_description *d;
0ac081f6
AH		 5248 size_t i;
5249
a3170dc6
AH		 5250 tree v2si_ftype_4_v2si
5251 = build_function_type
5252 (V2SI_type_node,
5253 tree_cons (NULL_TREE, V2SI_type_node,
5254 tree_cons (NULL_TREE, V2SI_type_node,
5255 tree_cons (NULL_TREE, V2SI_type_node,
5256 tree_cons (NULL_TREE, V2SI_type_node,
5257 endlink)))));
5258
5259 tree v2sf_ftype_4_v2sf
5260 = build_function_type
5261 (V2SF_type_node,
5262 tree_cons (NULL_TREE, V2SF_type_node,
5263 tree_cons (NULL_TREE, V2SF_type_node,
5264 tree_cons (NULL_TREE, V2SF_type_node,
5265 tree_cons (NULL_TREE, V2SF_type_node,
5266 endlink)))));
5267
5268 tree int_ftype_int_v2si_v2si
5269 = build_function_type
5270 (integer_type_node,
5271 tree_cons (NULL_TREE, integer_type_node,
5272 tree_cons (NULL_TREE, V2SI_type_node,
5273 tree_cons (NULL_TREE, V2SI_type_node,
5274 endlink))));
5275
5276 tree int_ftype_int_v2sf_v2sf
5277 = build_function_type
5278 (integer_type_node,
5279 tree_cons (NULL_TREE, integer_type_node,
5280 tree_cons (NULL_TREE, V2SF_type_node,
5281 tree_cons (NULL_TREE, V2SF_type_node,
5282 endlink))));
5283
5284 tree void_ftype_v2si_puint_int
5285 = build_function_type (void_type_node,
5286 tree_cons (NULL_TREE, V2SI_type_node,
5287 tree_cons (NULL_TREE, puint_type_node,
5288 tree_cons (NULL_TREE,
5289 integer_type_node,
5290 endlink))));
5291
5292 tree void_ftype_v2si_puint_char
5293 = build_function_type (void_type_node,
5294 tree_cons (NULL_TREE, V2SI_type_node,
5295 tree_cons (NULL_TREE, puint_type_node,
5296 tree_cons (NULL_TREE,
5297 char_type_node,
5298 endlink))));
5299
5300 tree void_ftype_v2si_pv2si_int
5301 = build_function_type (void_type_node,
5302 tree_cons (NULL_TREE, V2SI_type_node,
5303 tree_cons (NULL_TREE, pv2si_type_node,
5304 tree_cons (NULL_TREE,
5305 integer_type_node,
5306 endlink))));
5307
5308 tree void_ftype_v2si_pv2si_char
5309 = build_function_type (void_type_node,
5310 tree_cons (NULL_TREE, V2SI_type_node,
5311 tree_cons (NULL_TREE, pv2si_type_node,
5312 tree_cons (NULL_TREE,
5313 char_type_node,
5314 endlink))));
5315
5316 tree void_ftype_int
5317 = build_function_type (void_type_node,
5318 tree_cons (NULL_TREE, integer_type_node, endlink));
5319
5320 tree int_ftype_void
5321 = build_function_type (integer_type_node,
5322 tree_cons (NULL_TREE, void_type_node, endlink));
5323
5324 tree v2si_ftype_pv2si_int
5325 = build_function_type (V2SI_type_node,
5326 tree_cons (NULL_TREE, pv2si_type_node,
5327 tree_cons (NULL_TREE, integer_type_node,
5328 endlink)));
5329
5330 tree v2si_ftype_puint_int
5331 = build_function_type (V2SI_type_node,
5332 tree_cons (NULL_TREE, puint_type_node,
5333 tree_cons (NULL_TREE, integer_type_node,
5334 endlink)));
5335
5336 tree v2si_ftype_pushort_int
5337 = build_function_type (V2SI_type_node,
5338 tree_cons (NULL_TREE, pushort_type_node,
5339 tree_cons (NULL_TREE, integer_type_node,
5340 endlink)));
5341
5342 /* The initialization of the simple binary and unary builtins is
5343 done in rs6000_common_init_builtins, but we have to enable the
5344 mask bits here manually because we have run out of `target_flags'
5345 bits. We really need to redesign this mask business. */
5346
5347 enable_mask_for_builtins ((struct builtin_description *) bdesc_2arg,
5348 ARRAY_SIZE (bdesc_2arg),
5349 SPE_BUILTIN_EVADDW,
5350 SPE_BUILTIN_EVXOR);
5351 enable_mask_for_builtins ((struct builtin_description *) bdesc_1arg,
5352 ARRAY_SIZE (bdesc_1arg),
5353 SPE_BUILTIN_EVABS,
5354 SPE_BUILTIN_EVSUBFUSIAAW);
5355 enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_predicates,
5356 ARRAY_SIZE (bdesc_spe_predicates),
5357 SPE_BUILTIN_EVCMPEQ,
5358 SPE_BUILTIN_EVFSTSTLT);
5359 enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_evsel,
5360 ARRAY_SIZE (bdesc_spe_evsel),
5361 SPE_BUILTIN_EVSEL_CMPGTS,
5362 SPE_BUILTIN_EVSEL_FSTSTEQ);
5363
5364 /* Initialize irregular SPE builtins. */
5365
5366 def_builtin (target_flags, "__builtin_spe_mtspefscr", void_ftype_int, SPE_BUILTIN_MTSPEFSCR);
5367 def_builtin (target_flags, "__builtin_spe_mfspefscr", int_ftype_void, SPE_BUILTIN_MFSPEFSCR);
5368 def_builtin (target_flags, "__builtin_spe_evstddx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDDX);
5369 def_builtin (target_flags, "__builtin_spe_evstdhx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDHX);
5370 def_builtin (target_flags, "__builtin_spe_evstdwx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDWX);
5371 def_builtin (target_flags, "__builtin_spe_evstwhex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHEX);
5372 def_builtin (target_flags, "__builtin_spe_evstwhox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHOX);
5373 def_builtin (target_flags, "__builtin_spe_evstwwex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWEX);
5374 def_builtin (target_flags, "__builtin_spe_evstwwox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWOX);
5375 def_builtin (target_flags, "__builtin_spe_evstdd", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDD);
5376 def_builtin (target_flags, "__builtin_spe_evstdh", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDH);
5377 def_builtin (target_flags, "__builtin_spe_evstdw", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDW);
5378 def_builtin (target_flags, "__builtin_spe_evstwhe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHE);
5379 def_builtin (target_flags, "__builtin_spe_evstwho", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHO);
5380 def_builtin (target_flags, "__builtin_spe_evstwwe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWE);
5381 def_builtin (target_flags, "__builtin_spe_evstwwo", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWO);
5382
5383 /* Loads. */
5384 def_builtin (target_flags, "__builtin_spe_evlddx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDDX);
5385 def_builtin (target_flags, "__builtin_spe_evldwx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDWX);
5386 def_builtin (target_flags, "__builtin_spe_evldhx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDHX);
5387 def_builtin (target_flags, "__builtin_spe_evlwhex", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHEX);
5388 def_builtin (target_flags, "__builtin_spe_evlwhoux", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOUX);
5389 def_builtin (target_flags, "__builtin_spe_evlwhosx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOSX);
5390 def_builtin (target_flags, "__builtin_spe_evlwwsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLATX);
5391 def_builtin (target_flags, "__builtin_spe_evlwhsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLATX);
5392 def_builtin (target_flags, "__builtin_spe_evlhhesplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLATX);
5393 def_builtin (target_flags, "__builtin_spe_evlhhousplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLATX);
5394 def_builtin (target_flags, "__builtin_spe_evlhhossplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLATX);
5395 def_builtin (target_flags, "__builtin_spe_evldd", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDD);
5396 def_builtin (target_flags, "__builtin_spe_evldw", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDW);
5397 def_builtin (target_flags, "__builtin_spe_evldh", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDH);
5398 def_builtin (target_flags, "__builtin_spe_evlhhesplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLAT);
5399 def_builtin (target_flags, "__builtin_spe_evlhhossplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLAT);
5400 def_builtin (target_flags, "__builtin_spe_evlhhousplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLAT);
5401 def_builtin (target_flags, "__builtin_spe_evlwhe", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHE);
5402 def_builtin (target_flags, "__builtin_spe_evlwhos", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOS);
5403 def_builtin (target_flags, "__builtin_spe_evlwhou", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOU);
5404 def_builtin (target_flags, "__builtin_spe_evlwhsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLAT);
5405 def_builtin (target_flags, "__builtin_spe_evlwwsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLAT);
5406
5407 /* Predicates. */
5408 d = (struct builtin_description *) bdesc_spe_predicates;
5409 for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, d++)
5410 {
5411 tree type;
5412
5413 switch (insn_data[d->icode].operand[1].mode)
5414 {
5415 case V2SImode:
5416 type = int_ftype_int_v2si_v2si;
5417 break;
5418 case V2SFmode:
5419 type = int_ftype_int_v2sf_v2sf;
5420 break;
5421 default:
5422 abort ();
5423 }
5424
5425 def_builtin (d->mask, d->name, type, d->code);
5426 }
5427
5428 /* Evsel predicates. */
5429 d = (struct builtin_description *) bdesc_spe_evsel;
5430 for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, d++)
5431 {
5432 tree type;
5433
5434 switch (insn_data[d->icode].operand[1].mode)
5435 {
5436 case V2SImode:
5437 type = v2si_ftype_4_v2si;
5438 break;
5439 case V2SFmode:
5440 type = v2sf_ftype_4_v2sf;
5441 break;
5442 default:
5443 abort ();
5444 }
5445
5446 def_builtin (d->mask, d->name, type, d->code);
5447 }
5448}
5449
5450static void
b24c9d35 5451altivec_init_builtins ()
a3170dc6
AH		 5452{
5453 struct builtin_description *d;
5454 struct builtin_description_predicates *dp;
5455 size_t i;
5456 tree pfloat_type_node = build_pointer_type (float_type_node);
5457 tree pint_type_node = build_pointer_type (integer_type_node);
5458 tree pshort_type_node = build_pointer_type (short_integer_type_node);
5459 tree pchar_type_node = build_pointer_type (char_type_node);
5460
5461 tree pvoid_type_node = build_pointer_type (void_type_node);
5462
0dbc3651
ZW		 5463 tree pcfloat_type_node = build_pointer_type (build_qualified_type (float_type_node, TYPE_QUAL_CONST));
5464 tree pcint_type_node = build_pointer_type (build_qualified_type (integer_type_node, TYPE_QUAL_CONST));
5465 tree pcshort_type_node = build_pointer_type (build_qualified_type (short_integer_type_node, TYPE_QUAL_CONST));
5466 tree pcchar_type_node = build_pointer_type (build_qualified_type (char_type_node, TYPE_QUAL_CONST));
5467
5468 tree pcvoid_type_node = build_pointer_type (build_qualified_type (void_type_node, TYPE_QUAL_CONST));
5469
a3170dc6
AH		 5470 tree int_ftype_int_v4si_v4si
5471 = build_function_type_list (integer_type_node,
5472 integer_type_node, V4SI_type_node,
5473 V4SI_type_node, NULL_TREE);
0dbc3651
ZW		 5474 tree v4sf_ftype_pcfloat
5475 = build_function_type_list (V4SF_type_node, pcfloat_type_node, NULL_TREE);
a3170dc6 5476 tree void_ftype_pfloat_v4sf
b4de2f7d 5477 = build_function_type_list (void_type_node,
a3170dc6 5478 pfloat_type_node, V4SF_type_node, NULL_TREE);
0dbc3651
ZW		 5479 tree v4si_ftype_pcint
5480 = build_function_type_list (V4SI_type_node, pcint_type_node, NULL_TREE);
5481 tree void_ftype_pint_v4si
b4de2f7d
AH		 5482 = build_function_type_list (void_type_node,
5483 pint_type_node, V4SI_type_node, NULL_TREE);
0dbc3651
ZW		 5484 tree v8hi_ftype_pcshort
5485 = build_function_type_list (V8HI_type_node, pcshort_type_node, NULL_TREE);
f18c054f 5486 tree void_ftype_pshort_v8hi
b4de2f7d
AH		 5487 = build_function_type_list (void_type_node,
5488 pshort_type_node, V8HI_type_node, NULL_TREE);
0dbc3651
ZW		 5489 tree v16qi_ftype_pcchar
5490 = build_function_type_list (V16QI_type_node, pcchar_type_node, NULL_TREE);
f18c054f 5491 tree void_ftype_pchar_v16qi
b4de2f7d
AH		 5492 = build_function_type_list (void_type_node,
5493 pchar_type_node, V16QI_type_node, NULL_TREE);
95385cbb 5494 tree void_ftype_v4si
b4de2f7d 5495 = build_function_type_list (void_type_node, V4SI_type_node, NULL_TREE);
a3170dc6
AH		 5496 tree v8hi_ftype_void
5497 = build_function_type (V8HI_type_node, void_list_node);
5498 tree void_ftype_void
5499 = build_function_type (void_type_node, void_list_node);
5500 tree void_ftype_qi
5501 = build_function_type_list (void_type_node, char_type_node, NULL_TREE);
0dbc3651
ZW		 5502
5503 tree v16qi_ftype_int_pcvoid
a3170dc6 5504 = build_function_type_list (V16QI_type_node,
0dbc3651
ZW		 5505 integer_type_node, pcvoid_type_node, NULL_TREE);
5506 tree v8hi_ftype_int_pcvoid
a3170dc6 5507 = build_function_type_list (V8HI_type_node,
0dbc3651
ZW		 5508 integer_type_node, pcvoid_type_node, NULL_TREE);
5509 tree v4si_ftype_int_pcvoid
a3170dc6 5510 = build_function_type_list (V4SI_type_node,
0dbc3651
ZW		 5511 integer_type_node, pcvoid_type_node, NULL_TREE);
5512
14b32f4e 5513 tree void_ftype_v4si_int_pvoid
b4de2f7d
AH		 5514 = build_function_type_list (void_type_node,
5515 V4SI_type_node, integer_type_node,
5516 pvoid_type_node, NULL_TREE);
6525c0e7 5517 tree void_ftype_v16qi_int_pvoid
b4de2f7d
AH		 5518 = build_function_type_list (void_type_node,
5519 V16QI_type_node, integer_type_node,
5520 pvoid_type_node, NULL_TREE);
6525c0e7 5521 tree void_ftype_v8hi_int_pvoid
b4de2f7d
AH		 5522 = build_function_type_list (void_type_node,
5523 V8HI_type_node, integer_type_node,
5524 pvoid_type_node, NULL_TREE);
a3170dc6
AH		 5525 tree int_ftype_int_v8hi_v8hi
5526 = build_function_type_list (integer_type_node,
5527 integer_type_node, V8HI_type_node,
5528 V8HI_type_node, NULL_TREE);
5529 tree int_ftype_int_v16qi_v16qi
5530 = build_function_type_list (integer_type_node,
5531 integer_type_node, V16QI_type_node,
5532 V16QI_type_node, NULL_TREE);
5533 tree int_ftype_int_v4sf_v4sf
5534 = build_function_type_list (integer_type_node,
5535 integer_type_node, V4SF_type_node,
5536 V4SF_type_node, NULL_TREE);
5537 tree v4si_ftype_v4si
5538 = build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE);
5539 tree v8hi_ftype_v8hi
5540 = build_function_type_list (V8HI_type_node, V8HI_type_node, NULL_TREE);
5541 tree v16qi_ftype_v16qi
5542 = build_function_type_list (V16QI_type_node, V16QI_type_node, NULL_TREE);
5543 tree v4sf_ftype_v4sf
5544 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
0dbc3651 5545 tree void_ftype_pcvoid_int_char
a3170dc6 5546 = build_function_type_list (void_type_node,
0dbc3651 5547 pcvoid_type_node, integer_type_node,
a3170dc6 5548 char_type_node, NULL_TREE);
0dbc3651
ZW		 5549
5550 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4sf", v4sf_ftype_pcfloat,
5551 ALTIVEC_BUILTIN_LD_INTERNAL_4sf);
5552 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4sf", void_ftype_pfloat_v4sf,
5553 ALTIVEC_BUILTIN_ST_INTERNAL_4sf);
5554 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4si", v4si_ftype_pcint,
5555 ALTIVEC_BUILTIN_LD_INTERNAL_4si);
5556 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4si", void_ftype_pint_v4si,
5557 ALTIVEC_BUILTIN_ST_INTERNAL_4si);
5558 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_8hi", v8hi_ftype_pcshort,
5559 ALTIVEC_BUILTIN_LD_INTERNAL_8hi);
5560 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_8hi", void_ftype_pshort_v8hi,
5561 ALTIVEC_BUILTIN_ST_INTERNAL_8hi);
5562 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_16qi", v16qi_ftype_pcchar,
5563 ALTIVEC_BUILTIN_LD_INTERNAL_16qi);
5564 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_16qi", void_ftype_pchar_v16qi,
5565 ALTIVEC_BUILTIN_ST_INTERNAL_16qi);
a3170dc6
AH		 5566 def_builtin (MASK_ALTIVEC, "__builtin_altivec_mtvscr", void_ftype_v4si, ALTIVEC_BUILTIN_MTVSCR);
5567 def_builtin (MASK_ALTIVEC, "__builtin_altivec_mfvscr", v8hi_ftype_void, ALTIVEC_BUILTIN_MFVSCR);
5568 def_builtin (MASK_ALTIVEC, "__builtin_altivec_dssall", void_ftype_void, ALTIVEC_BUILTIN_DSSALL);
5569 def_builtin (MASK_ALTIVEC, "__builtin_altivec_dss", void_ftype_qi, ALTIVEC_BUILTIN_DSS);
0dbc3651
ZW		 5570 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsl", v16qi_ftype_int_pcvoid, ALTIVEC_BUILTIN_LVSL);
5571 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsr", v16qi_ftype_int_pcvoid, ALTIVEC_BUILTIN_LVSR);
5572 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvebx", v16qi_ftype_int_pcvoid, ALTIVEC_BUILTIN_LVEBX);
5573 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvehx", v8hi_ftype_int_pcvoid, ALTIVEC_BUILTIN_LVEHX);
5574 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvewx", v4si_ftype_int_pcvoid, ALTIVEC_BUILTIN_LVEWX);
5575 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvxl", v4si_ftype_int_pcvoid, ALTIVEC_BUILTIN_LVXL);
5576 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvx", v4si_ftype_int_pcvoid, ALTIVEC_BUILTIN_LVX);
a3170dc6
AH		 5577 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvx", void_ftype_v4si_int_pvoid, ALTIVEC_BUILTIN_STVX);
5578 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvewx", void_ftype_v4si_int_pvoid, ALTIVEC_BUILTIN_STVEWX);
5579 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvxl", void_ftype_v4si_int_pvoid, ALTIVEC_BUILTIN_STVXL);
5580 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvebx", void_ftype_v16qi_int_pvoid, ALTIVEC_BUILTIN_STVEBX);
5581 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvehx", void_ftype_v8hi_int_pvoid, ALTIVEC_BUILTIN_STVEHX);
5582
5583 /* Add the DST variants. */
5584 d = (struct builtin_description *) bdesc_dst;
5585 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
0dbc3651 5586 def_builtin (d->mask, d->name, void_ftype_pcvoid_int_char, d->code);
a3170dc6
AH		 5587
5588 /* Initialize the predicates. */
5589 dp = (struct builtin_description_predicates *) bdesc_altivec_preds;
5590 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++)
5591 {
5592 enum machine_mode mode1;
5593 tree type;
5594
5595 mode1 = insn_data[dp->icode].operand[1].mode;
5596
5597 switch (mode1)
5598 {
5599 case V4SImode:
5600 type = int_ftype_int_v4si_v4si;
5601 break;
5602 case V8HImode:
5603 type = int_ftype_int_v8hi_v8hi;
5604 break;
5605 case V16QImode:
5606 type = int_ftype_int_v16qi_v16qi;
5607 break;
5608 case V4SFmode:
5609 type = int_ftype_int_v4sf_v4sf;
5610 break;
5611 default:
5612 abort ();
5613 }
5614
5615 def_builtin (dp->mask, dp->name, type, dp->code);
5616 }
5617
5618 /* Initialize the abs* operators. */
5619 d = (struct builtin_description *) bdesc_abs;
5620 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
5621 {
5622 enum machine_mode mode0;
5623 tree type;
5624
5625 mode0 = insn_data[d->icode].operand[0].mode;
5626
5627 switch (mode0)
5628 {
5629 case V4SImode:
5630 type = v4si_ftype_v4si;
5631 break;
5632 case V8HImode:
5633 type = v8hi_ftype_v8hi;
5634 break;
5635 case V16QImode:
5636 type = v16qi_ftype_v16qi;
5637 break;
5638 case V4SFmode:
5639 type = v4sf_ftype_v4sf;
5640 break;
5641 default:
5642 abort ();
5643 }
5644
5645 def_builtin (d->mask, d->name, type, d->code);
5646 }
5647}
5648
5649static void
b24c9d35 5650rs6000_common_init_builtins ()
a3170dc6
AH		 5651{
5652 struct builtin_description *d;
5653 size_t i;
5654
5655 tree v4sf_ftype_v4sf_v4sf_v16qi
5656 = build_function_type_list (V4SF_type_node,
5657 V4SF_type_node, V4SF_type_node,
5658 V16QI_type_node, NULL_TREE);
5659 tree v4si_ftype_v4si_v4si_v16qi
5660 = build_function_type_list (V4SI_type_node,
5661 V4SI_type_node, V4SI_type_node,
5662 V16QI_type_node, NULL_TREE);
5663 tree v8hi_ftype_v8hi_v8hi_v16qi
5664 = build_function_type_list (V8HI_type_node,
5665 V8HI_type_node, V8HI_type_node,
5666 V16QI_type_node, NULL_TREE);
5667 tree v16qi_ftype_v16qi_v16qi_v16qi
5668 = build_function_type_list (V16QI_type_node,
5669 V16QI_type_node, V16QI_type_node,
5670 V16QI_type_node, NULL_TREE);
5671 tree v4si_ftype_char
5672 = build_function_type_list (V4SI_type_node, char_type_node, NULL_TREE);
5673 tree v8hi_ftype_char
5674 = build_function_type_list (V8HI_type_node, char_type_node, NULL_TREE);
5675 tree v16qi_ftype_char
5676 = build_function_type_list (V16QI_type_node, char_type_node, NULL_TREE);
5677 tree v8hi_ftype_v16qi
5678 = build_function_type_list (V8HI_type_node, V16QI_type_node, NULL_TREE);
5679 tree v4sf_ftype_v4sf
5680 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
5681
5682 tree v2si_ftype_v2si_v2si
5683 = build_function_type_list (V2SI_type_node,
5684 V2SI_type_node, V2SI_type_node, NULL_TREE);
5685
5686 tree v2sf_ftype_v2sf_v2sf
5687 = build_function_type_list (V2SF_type_node,
5688 V2SF_type_node, V2SF_type_node, NULL_TREE);
5689
5690 tree v2si_ftype_int_int
5691 = build_function_type_list (V2SI_type_node,
5692 integer_type_node, integer_type_node,
5693 NULL_TREE);
5694
5695 tree v2si_ftype_v2si
5696 = build_function_type_list (V2SI_type_node, V2SI_type_node, NULL_TREE);
5697
5698 tree v2sf_ftype_v2sf
5699 = build_function_type_list (V2SF_type_node,
5700 V2SF_type_node, NULL_TREE);
5701
5702 tree v2sf_ftype_v2si
5703 = build_function_type_list (V2SF_type_node,
5704 V2SI_type_node, NULL_TREE);
5705
5706 tree v2si_ftype_v2sf
5707 = build_function_type_list (V2SI_type_node,
5708 V2SF_type_node, NULL_TREE);
5709
5710 tree v2si_ftype_v2si_char
5711 = build_function_type_list (V2SI_type_node,
5712 V2SI_type_node, char_type_node, NULL_TREE);
5713
5714 tree v2si_ftype_int_char
5715 = build_function_type_list (V2SI_type_node,
5716 integer_type_node, char_type_node, NULL_TREE);
5717
5718 tree v2si_ftype_char
5719 = build_function_type_list (V2SI_type_node, char_type_node, NULL_TREE);
5720
5721 tree int_ftype_int_int
5722 = build_function_type_list (integer_type_node,
5723 integer_type_node, integer_type_node,
5724 NULL_TREE);
95385cbb 5725
0ac081f6 5726 tree v4si_ftype_v4si_v4si
b4de2f7d
AH		 5727 = build_function_type_list (V4SI_type_node,
5728 V4SI_type_node, V4SI_type_node, NULL_TREE);
617e0e1d 5729 tree v4sf_ftype_v4si_char
b4de2f7d
AH		 5730 = build_function_type_list (V4SF_type_node,
5731 V4SI_type_node, char_type_node, NULL_TREE);
617e0e1d 5732 tree v4si_ftype_v4sf_char
b4de2f7d
AH		 5733 = build_function_type_list (V4SI_type_node,
5734 V4SF_type_node, char_type_node, NULL_TREE);
2212663f 5735 tree v4si_ftype_v4si_char
b4de2f7d
AH		 5736 = build_function_type_list (V4SI_type_node,
5737 V4SI_type_node, char_type_node, NULL_TREE);
2212663f 5738 tree v8hi_ftype_v8hi_char
b4de2f7d
AH		 5739 = build_function_type_list (V8HI_type_node,
5740 V8HI_type_node, char_type_node, NULL_TREE);
2212663f 5741 tree v16qi_ftype_v16qi_char
b4de2f7d
AH		 5742 = build_function_type_list (V16QI_type_node,
5743 V16QI_type_node, char_type_node, NULL_TREE);
24408032 5744 tree v16qi_ftype_v16qi_v16qi_char
b4de2f7d
AH		 5745 = build_function_type_list (V16QI_type_node,
5746 V16QI_type_node, V16QI_type_node,
5747 char_type_node, NULL_TREE);
24408032 5748 tree v8hi_ftype_v8hi_v8hi_char
b4de2f7d
AH		 5749 = build_function_type_list (V8HI_type_node,
5750 V8HI_type_node, V8HI_type_node,
5751 char_type_node, NULL_TREE);
24408032 5752 tree v4si_ftype_v4si_v4si_char
b4de2f7d
AH		 5753 = build_function_type_list (V4SI_type_node,
5754 V4SI_type_node, V4SI_type_node,
5755 char_type_node, NULL_TREE);
24408032 5756 tree v4sf_ftype_v4sf_v4sf_char
b4de2f7d
AH		 5757 = build_function_type_list (V4SF_type_node,
5758 V4SF_type_node, V4SF_type_node,
5759 char_type_node, NULL_TREE);
0ac081f6 5760 tree v4sf_ftype_v4sf_v4sf
b4de2f7d
AH		 5761 = build_function_type_list (V4SF_type_node,
5762 V4SF_type_node, V4SF_type_node, NULL_TREE);
617e0e1d 5763 tree v4sf_ftype_v4sf_v4sf_v4si
b4de2f7d
AH		 5764 = build_function_type_list (V4SF_type_node,
5765 V4SF_type_node, V4SF_type_node,
5766 V4SI_type_node, NULL_TREE);
2212663f 5767 tree v4sf_ftype_v4sf_v4sf_v4sf
b4de2f7d
AH		 5768 = build_function_type_list (V4SF_type_node,
5769 V4SF_type_node, V4SF_type_node,
5770 V4SF_type_node, NULL_TREE);
617e0e1d 5771 tree v4si_ftype_v4si_v4si_v4si
b4de2f7d
AH		 5772 = build_function_type_list (V4SI_type_node,
5773 V4SI_type_node, V4SI_type_node,
5774 V4SI_type_node, NULL_TREE);
0ac081f6 5775 tree v8hi_ftype_v8hi_v8hi
b4de2f7d
AH		 5776 = build_function_type_list (V8HI_type_node,
5777 V8HI_type_node, V8HI_type_node, NULL_TREE);
2212663f 5778 tree v8hi_ftype_v8hi_v8hi_v8hi
b4de2f7d
AH		 5779 = build_function_type_list (V8HI_type_node,
5780 V8HI_type_node, V8HI_type_node,
5781 V8HI_type_node, NULL_TREE);
2212663f 5782 tree v4si_ftype_v8hi_v8hi_v4si
b4de2f7d
AH		 5783 = build_function_type_list (V4SI_type_node,
5784 V8HI_type_node, V8HI_type_node,
5785 V4SI_type_node, NULL_TREE);
2212663f 5786 tree v4si_ftype_v16qi_v16qi_v4si
b4de2f7d
AH		 5787 = build_function_type_list (V4SI_type_node,
5788 V16QI_type_node, V16QI_type_node,
5789 V4SI_type_node, NULL_TREE);
0ac081f6 5790 tree v16qi_ftype_v16qi_v16qi
b4de2f7d
AH		 5791 = build_function_type_list (V16QI_type_node,
5792 V16QI_type_node, V16QI_type_node, NULL_TREE);
0ac081f6 5793 tree v4si_ftype_v4sf_v4sf
b4de2f7d
AH		 5794 = build_function_type_list (V4SI_type_node,
5795 V4SF_type_node, V4SF_type_node, NULL_TREE);
0ac081f6 5796 tree v8hi_ftype_v16qi_v16qi
b4de2f7d
AH		 5797 = build_function_type_list (V8HI_type_node,
5798 V16QI_type_node, V16QI_type_node, NULL_TREE);
0ac081f6 5799 tree v4si_ftype_v8hi_v8hi
b4de2f7d
AH		 5800 = build_function_type_list (V4SI_type_node,
5801 V8HI_type_node, V8HI_type_node, NULL_TREE);
0ac081f6 5802 tree v8hi_ftype_v4si_v4si
b4de2f7d
AH		 5803 = build_function_type_list (V8HI_type_node,
5804 V4SI_type_node, V4SI_type_node, NULL_TREE);
0ac081f6 5805 tree v16qi_ftype_v8hi_v8hi
b4de2f7d
AH		 5806 = build_function_type_list (V16QI_type_node,
5807 V8HI_type_node, V8HI_type_node, NULL_TREE);
0ac081f6 5808 tree v4si_ftype_v16qi_v4si
b4de2f7d
AH		 5809 = build_function_type_list (V4SI_type_node,
5810 V16QI_type_node, V4SI_type_node, NULL_TREE);
fa066a23 5811 tree v4si_ftype_v16qi_v16qi
b4de2f7d
AH		 5812 = build_function_type_list (V4SI_type_node,
5813 V16QI_type_node, V16QI_type_node, NULL_TREE);
0ac081f6 5814 tree v4si_ftype_v8hi_v4si
b4de2f7d
AH		 5815 = build_function_type_list (V4SI_type_node,
5816 V8HI_type_node, V4SI_type_node, NULL_TREE);
a3170dc6
AH		 5817 tree v4si_ftype_v8hi
5818 = build_function_type_list (V4SI_type_node, V8HI_type_node, NULL_TREE);
5819 tree int_ftype_v4si_v4si
5820 = build_function_type_list (integer_type_node,
5821 V4SI_type_node, V4SI_type_node, NULL_TREE);
5822 tree int_ftype_v4sf_v4sf
5823 = build_function_type_list (integer_type_node,
5824 V4SF_type_node, V4SF_type_node, NULL_TREE);
5825 tree int_ftype_v16qi_v16qi
5826 = build_function_type_list (integer_type_node,
5827 V16QI_type_node, V16QI_type_node, NULL_TREE);
0ac081f6 5828 tree int_ftype_v8hi_v8hi
b4de2f7d
AH		 5829 = build_function_type_list (integer_type_node,
5830 V8HI_type_node, V8HI_type_node, NULL_TREE);
0ac081f6 5831
6f317ef3 5832 /* Add the simple ternary operators. */
2212663f 5833 d = (struct builtin_description *) bdesc_3arg;
ca7558fc 5834 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
2212663f
DB		 5835 {
5836
5837 enum machine_mode mode0, mode1, mode2, mode3;
5838 tree type;
5839
0559cc77 5840 if (d->name == 0 || d->icode == CODE_FOR_nothing)
2212663f
DB		 5841 continue;
5842
5843 mode0 = insn_data[d->icode].operand[0].mode;
5844 mode1 = insn_data[d->icode].operand[1].mode;
5845 mode2 = insn_data[d->icode].operand[2].mode;
5846 mode3 = insn_data[d->icode].operand[3].mode;
5847
5848 /* When all four are of the same mode. */
5849 if (mode0 == mode1 && mode1 == mode2 && mode2 == mode3)
5850 {
5851 switch (mode0)
5852 {
617e0e1d
DB		 5853 case V4SImode:
5854 type = v4si_ftype_v4si_v4si_v4si;
5855 break;
2212663f
DB		 5856 case V4SFmode:
5857 type = v4sf_ftype_v4sf_v4sf_v4sf;
5858 break;
5859 case V8HImode:
5860 type = v8hi_ftype_v8hi_v8hi_v8hi;
5861 break;
5862 case V16QImode:
5863 type = v16qi_ftype_v16qi_v16qi_v16qi;
5864 break;
5865 default:
5866 abort();
5867 }
5868 }
5869 else if (mode0 == mode1 && mode1 == mode2 && mode3 == V16QImode)
5870 {
5871 switch (mode0)
5872 {
5873 case V4SImode:
5874 type = v4si_ftype_v4si_v4si_v16qi;
5875 break;
5876 case V4SFmode:
5877 type = v4sf_ftype_v4sf_v4sf_v16qi;
5878 break;
5879 case V8HImode:
5880 type = v8hi_ftype_v8hi_v8hi_v16qi;
5881 break;
5882 case V16QImode:
5883 type = v16qi_ftype_v16qi_v16qi_v16qi;
5884 break;
5885 default:
5886 abort();
5887 }
5888 }
5889 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode
5890 && mode3 == V4SImode)
24408032 5891 type = v4si_ftype_v16qi_v16qi_v4si;
2212663f
DB		 5892 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode
5893 && mode3 == V4SImode)
24408032 5894 type = v4si_ftype_v8hi_v8hi_v4si;
617e0e1d
DB		 5895 else if (mode0 == V4SFmode && mode1 == V4SFmode && mode2 == V4SFmode
5896 && mode3 == V4SImode)
24408032
AH		 5897 type = v4sf_ftype_v4sf_v4sf_v4si;
5898
5899 /* vchar, vchar, vchar, 4 bit literal. */
5900 else if (mode0 == V16QImode && mode1 == mode0 && mode2 == mode0
5901 && mode3 == QImode)
5902 type = v16qi_ftype_v16qi_v16qi_char;
5903
5904 /* vshort, vshort, vshort, 4 bit literal. */
5905 else if (mode0 == V8HImode && mode1 == mode0 && mode2 == mode0
5906 && mode3 == QImode)
5907 type = v8hi_ftype_v8hi_v8hi_char;
5908
5909 /* vint, vint, vint, 4 bit literal. */
5910 else if (mode0 == V4SImode && mode1 == mode0 && mode2 == mode0
5911 && mode3 == QImode)
5912 type = v4si_ftype_v4si_v4si_char;
5913
5914 /* vfloat, vfloat, vfloat, 4 bit literal. */
5915 else if (mode0 == V4SFmode && mode1 == mode0 && mode2 == mode0
5916 && mode3 == QImode)
5917 type = v4sf_ftype_v4sf_v4sf_char;
5918
2212663f
DB		 5919 else
5920 abort ();
5921
5922 def_builtin (d->mask, d->name, type, d->code);
5923 }
5924
0ac081f6 5925 /* Add the simple binary operators. */
00b960c7 5926 d = (struct builtin_description *) bdesc_2arg;
ca7558fc 5927 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
0ac081f6
AH		 5928 {
5929 enum machine_mode mode0, mode1, mode2;
5930 tree type;
5931
0559cc77 5932 if (d->name == 0 || d->icode == CODE_FOR_nothing)
0ac081f6
AH		 5933 continue;
5934
5935 mode0 = insn_data[d->icode].operand[0].mode;
5936 mode1 = insn_data[d->icode].operand[1].mode;
5937 mode2 = insn_data[d->icode].operand[2].mode;
5938
5939 /* When all three operands are of the same mode. */
5940 if (mode0 == mode1 && mode1 == mode2)
5941 {
5942 switch (mode0)
5943 {
5944 case V4SFmode:
5945 type = v4sf_ftype_v4sf_v4sf;
5946 break;
5947 case V4SImode:
5948 type = v4si_ftype_v4si_v4si;
5949 break;
5950 case V16QImode:
5951 type = v16qi_ftype_v16qi_v16qi;
5952 break;
5953 case V8HImode:
5954 type = v8hi_ftype_v8hi_v8hi;
5955 break;
a3170dc6
AH		 5956 case V2SImode:
5957 type = v2si_ftype_v2si_v2si;
5958 break;
5959 case V2SFmode:
5960 type = v2sf_ftype_v2sf_v2sf;
5961 break;
5962 case SImode:
5963 type = int_ftype_int_int;
5964 break;
0ac081f6
AH		 5965 default:
5966 abort ();
5967 }
5968 }
5969
5970 /* A few other combos we really don't want to do manually. */
5971
5972 /* vint, vfloat, vfloat. */
5973 else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == V4SFmode)
5974 type = v4si_ftype_v4sf_v4sf;
5975
5976 /* vshort, vchar, vchar. */
5977 else if (mode0 == V8HImode && mode1 == V16QImode && mode2 == V16QImode)
5978 type = v8hi_ftype_v16qi_v16qi;
5979
5980 /* vint, vshort, vshort. */
5981 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode)
5982 type = v4si_ftype_v8hi_v8hi;
5983
5984 /* vshort, vint, vint. */
5985 else if (mode0 == V8HImode && mode1 == V4SImode && mode2 == V4SImode)
5986 type = v8hi_ftype_v4si_v4si;
5987
5988 /* vchar, vshort, vshort. */
5989 else if (mode0 == V16QImode && mode1 == V8HImode && mode2 == V8HImode)
5990 type = v16qi_ftype_v8hi_v8hi;
5991
5992 /* vint, vchar, vint. */
5993 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V4SImode)
5994 type = v4si_ftype_v16qi_v4si;
5995
fa066a23
AH		 5996 /* vint, vchar, vchar. */
5997 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode)
5998 type = v4si_ftype_v16qi_v16qi;
5999
0ac081f6
AH		 6000 /* vint, vshort, vint. */
6001 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V4SImode)
6002 type = v4si_ftype_v8hi_v4si;
2212663f
DB		 6003
6004 /* vint, vint, 5 bit literal. */
6005 else if (mode0 == V4SImode && mode1 == V4SImode && mode2 == QImode)
6006 type = v4si_ftype_v4si_char;
6007
6008 /* vshort, vshort, 5 bit literal. */
6009 else if (mode0 == V8HImode && mode1 == V8HImode && mode2 == QImode)
6010 type = v8hi_ftype_v8hi_char;
6011
6012 /* vchar, vchar, 5 bit literal. */
6013 else if (mode0 == V16QImode && mode1 == V16QImode && mode2 == QImode)
6014 type = v16qi_ftype_v16qi_char;
0ac081f6 6015
617e0e1d
DB		 6016 /* vfloat, vint, 5 bit literal. */
6017 else if (mode0 == V4SFmode && mode1 == V4SImode && mode2 == QImode)
6018 type = v4sf_ftype_v4si_char;
6019
6020 /* vint, vfloat, 5 bit literal. */
6021 else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == QImode)
6022 type = v4si_ftype_v4sf_char;
6023
a3170dc6
AH		 6024 else if (mode0 == V2SImode && mode1 == SImode && mode2 == SImode)
6025 type = v2si_ftype_int_int;
6026
6027 else if (mode0 == V2SImode && mode1 == V2SImode && mode2 == QImode)
6028 type = v2si_ftype_v2si_char;
6029
6030 else if (mode0 == V2SImode && mode1 == SImode && mode2 == QImode)
6031 type = v2si_ftype_int_char;
6032
0ac081f6
AH		 6033 /* int, x, x. */
6034 else if (mode0 == SImode)
6035 {
6036 switch (mode1)
6037 {
6038 case V4SImode:
6039 type = int_ftype_v4si_v4si;
6040 break;
6041 case V4SFmode:
6042 type = int_ftype_v4sf_v4sf;
6043 break;
6044 case V16QImode:
6045 type = int_ftype_v16qi_v16qi;
6046 break;
6047 case V8HImode:
6048 type = int_ftype_v8hi_v8hi;
6049 break;
6050 default:
6051 abort ();
6052 }
6053 }
6054
6055 else
6056 abort ();
6057
2212663f
DB		 6058 def_builtin (d->mask, d->name, type, d->code);
6059 }
24408032 6060
2212663f
DB		 6061 /* Add the simple unary operators. */
6062 d = (struct builtin_description *) bdesc_1arg;
ca7558fc 6063 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
2212663f
DB		 6064 {
6065 enum machine_mode mode0, mode1;
6066 tree type;
6067
0559cc77 6068 if (d->name == 0 || d->icode == CODE_FOR_nothing)
2212663f
DB		 6069 continue;
6070
6071 mode0 = insn_data[d->icode].operand[0].mode;
6072 mode1 = insn_data[d->icode].operand[1].mode;
6073
6074 if (mode0 == V4SImode && mode1 == QImode)
6075 type = v4si_ftype_char;
6076 else if (mode0 == V8HImode && mode1 == QImode)
6077 type = v8hi_ftype_char;
6078 else if (mode0 == V16QImode && mode1 == QImode)
6079 type = v16qi_ftype_char;
617e0e1d
DB		 6080 else if (mode0 == V4SFmode && mode1 == V4SFmode)
6081 type = v4sf_ftype_v4sf;
20e26713
AH		 6082 else if (mode0 == V8HImode && mode1 == V16QImode)
6083 type = v8hi_ftype_v16qi;
6084 else if (mode0 == V4SImode && mode1 == V8HImode)
6085 type = v4si_ftype_v8hi;
a3170dc6
AH		 6086 else if (mode0 == V2SImode && mode1 == V2SImode)
6087 type = v2si_ftype_v2si;
6088 else if (mode0 == V2SFmode && mode1 == V2SFmode)
6089 type = v2sf_ftype_v2sf;
6090 else if (mode0 == V2SFmode && mode1 == V2SImode)
6091 type = v2sf_ftype_v2si;
6092 else if (mode0 == V2SImode && mode1 == V2SFmode)
6093 type = v2si_ftype_v2sf;
6094 else if (mode0 == V2SImode && mode1 == QImode)
6095 type = v2si_ftype_char;
2212663f
DB		 6096 else
6097 abort ();
6098
0ac081f6
AH		 6099 def_builtin (d->mask, d->name, type, d->code);
6100 }
6101}
6102
35aff10b 6103\f
7e69e155
MM		 6104/* Expand a block move operation, and return 1 if successful. Return 0
6105 if we should let the compiler generate normal code.
6106
6107 operands[0] is the destination
6108 operands[1] is the source
6109 operands[2] is the length
6110 operands[3] is the alignment */
6111
3933e0e1
MM		 6112#define MAX_MOVE_REG 4
6113
7e69e155
MM		 6114int
6115expand_block_move (operands)
6116 rtx operands[];
6117{
b6c9286a
MM		 6118 rtx orig_dest = operands[0];
6119 rtx orig_src = operands[1];
7e69e155 6120 rtx bytes_rtx = operands[2];
7e69e155 6121 rtx align_rtx = operands[3];
3933e0e1 6122 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
5ee95df6 6123 int align;
3933e0e1
MM		 6124 int bytes;
6125 int offset;
7e69e155
MM		 6126 int move_bytes;
6127
3933e0e1 6128 /* If this is not a fixed size move, just call memcpy */
cc0d9ba8 6129 if (! constp)
3933e0e1
MM		 6130 return 0;
6131
5ee95df6
FS		 6132 /* If this is not a fixed size alignment, abort */
6133 if (GET_CODE (align_rtx) != CONST_INT)
6134 abort ();
6135 align = INTVAL (align_rtx);
6136
7e69e155 6137 /* Anything to move? */
3933e0e1
MM		 6138 bytes = INTVAL (bytes_rtx);
6139 if (bytes <= 0)
7e69e155
MM		 6140 return 1;
6141
ea9982a8 6142 /* store_one_arg depends on expand_block_move to handle at least the size of
6f317ef3 6143 reg_parm_stack_space. */
ea9982a8 6144 if (bytes > (TARGET_POWERPC64 ? 64 : 32))
7e69e155
MM		 6145 return 0;
6146
3933e0e1 6147 if (TARGET_STRING) /* string instructions are available */
7e69e155 6148 {
35aff10b 6149 for (offset = 0; bytes > 0; offset += move_bytes, bytes -= move_bytes)
7e69e155 6150 {
35aff10b
AM		 6151 union {
6152 rtx (*movstrsi) PARAMS ((rtx, rtx, rtx, rtx));
6153 rtx (*mov) PARAMS ((rtx, rtx));
6154 } gen_func;
6155 enum machine_mode mode = BLKmode;
6156 rtx src, dest;
6157
3933e0e1 6158 if (bytes > 24 /* move up to 32 bytes at a time */
cc0d9ba8
DE		 6159 && ! fixed_regs[5]
6160 && ! fixed_regs[6]
6161 && ! fixed_regs[7]
6162 && ! fixed_regs[8]
6163 && ! fixed_regs[9]
6164 && ! fixed_regs[10]
6165 && ! fixed_regs[11]
6166 && ! fixed_regs[12])
3933e0e1
MM		 6167 {
6168 move_bytes = (bytes > 32) ? 32 : bytes;
35aff10b 6169 gen_func.movstrsi = gen_movstrsi_8reg;
3933e0e1
MM		 6170 }
6171 else if (bytes > 16 /* move up to 24 bytes at a time */
f9562f27
DE		 6172 && ! fixed_regs[5]
6173 && ! fixed_regs[6]
cc0d9ba8
DE		 6174 && ! fixed_regs[7]
6175 && ! fixed_regs[8]
6176 && ! fixed_regs[9]
f9562f27 6177 && ! fixed_regs[10])
3933e0e1
MM		 6178 {
6179 move_bytes = (bytes > 24) ? 24 : bytes;
35aff10b 6180 gen_func.movstrsi = gen_movstrsi_6reg;
3933e0e1
MM		 6181 }
6182 else if (bytes > 8 /* move up to 16 bytes at a time */
f9562f27
DE		 6183 && ! fixed_regs[5]
6184 && ! fixed_regs[6]
6185 && ! fixed_regs[7]
6186 && ! fixed_regs[8])
3933e0e1
MM		 6187 {
6188 move_bytes = (bytes > 16) ? 16 : bytes;
35aff10b 6189 gen_func.movstrsi = gen_movstrsi_4reg;
3933e0e1 6190 }
acad7ed3 6191 else if (bytes >= 8 && TARGET_POWERPC64
a4f6c312 6192 /* 64-bit loads and stores require word-aligned
82e41834 6193 displacements. */
a4f6c312 6194 && (align >= 8 || (! STRICT_ALIGNMENT && align >= 4)))
acad7ed3
DE		 6195 {
6196 move_bytes = 8;
35aff10b
AM		 6197 mode = DImode;
6198 gen_func.mov = gen_movdi;
acad7ed3 6199 }
09a625f7 6200 else if (bytes > 4 && !TARGET_POWERPC64)
3933e0e1
MM		 6201 { /* move up to 8 bytes at a time */
6202 move_bytes = (bytes > 8) ? 8 : bytes;
35aff10b 6203 gen_func.movstrsi = gen_movstrsi_2reg;
3933e0e1 6204 }
cc0d9ba8 6205 else if (bytes >= 4 && (align >= 4 || ! STRICT_ALIGNMENT))
3933e0e1
MM		 6206 { /* move 4 bytes */
6207 move_bytes = 4;
35aff10b
AM		 6208 mode = SImode;
6209 gen_func.mov = gen_movsi;
3933e0e1 6210 }
cc0d9ba8 6211 else if (bytes == 2 && (align >= 2 || ! STRICT_ALIGNMENT))
3933e0e1
MM		 6212 { /* move 2 bytes */
6213 move_bytes = 2;
35aff10b
AM		 6214 mode = HImode;
6215 gen_func.mov = gen_movhi;
3933e0e1
MM		 6216 }
6217 else if (bytes == 1) /* move 1 byte */
6218 {
6219 move_bytes = 1;
35aff10b
AM		 6220 mode = QImode;
6221 gen_func.mov = gen_movqi;
3933e0e1
MM		 6222 }
6223 else
6224 { /* move up to 4 bytes at a time */
6225 move_bytes = (bytes > 4) ? 4 : bytes;
35aff10b 6226 gen_func.movstrsi = gen_movstrsi_1reg;
3933e0e1 6227 }
4c64a852 6228
35aff10b
AM		 6229 src = adjust_address (orig_src, mode, offset);
6230 dest = adjust_address (orig_dest, mode, offset);
6231
6232 if (mode == BLKmode)
015892ee 6233 {
35aff10b
AM		 6234 /* Move the address into scratch registers. The movstrsi
6235 patterns require zero offset. */
6236 if (!REG_P (XEXP (src, 0)))
cc0d9ba8 6237 {
35aff10b
AM		 6238 rtx src_reg = copy_addr_to_reg (XEXP (src, 0));
6239 src = replace_equiv_address (src, src_reg);
cc0d9ba8 6240 }
35aff10b
AM		 6241 set_mem_size (src, GEN_INT (move_bytes));
6242
6243 if (!REG_P (XEXP (dest, 0)))
cc0d9ba8 6244 {
35aff10b
AM		 6245 rtx dest_reg = copy_addr_to_reg (XEXP (dest, 0));
6246 dest = replace_equiv_address (dest, dest_reg);
cc0d9ba8 6247 }
35aff10b
AM		 6248 set_mem_size (dest, GEN_INT (move_bytes));
6249
6250 emit_insn ((*gen_func.movstrsi) (dest, src,
6251 GEN_INT (move_bytes & 31),
6252 align_rtx));
6253 }
6254 else
6255 {
6256 rtx tmp_reg = gen_reg_rtx (mode);
6257
6258 emit_insn ((*gen_func.mov) (tmp_reg, src));
6259 emit_insn ((*gen_func.mov) (dest, tmp_reg));
015892ee 6260 }
4c64a852 6261 }
3933e0e1
MM		 6262 }
6263
6264 else /* string instructions not available */
6265 {
35aff10b
AM		 6266 rtx stores[MAX_MOVE_REG];
6267 int num_reg = 0;
6268 int i;
6269
6270 for (offset = 0; bytes > 0; offset += move_bytes, bytes -= move_bytes)
7e69e155 6271 {
35aff10b
AM		 6272 rtx (*gen_mov_func) PARAMS ((rtx, rtx));
6273 enum machine_mode mode;
6274 rtx src, dest, tmp_reg;
3933e0e1 6275
cc0d9ba8
DE		 6276 /* Generate the appropriate load and store, saving the stores
6277 for later. */
6278 if (bytes >= 8 && TARGET_POWERPC64
a4f6c312
SS		 6279 /* 64-bit loads and stores require word-aligned
6280 displacements. */
cc0d9ba8 6281 && (align >= 8 || (! STRICT_ALIGNMENT && align >= 4)))
b6c9286a
MM		 6282 {
6283 move_bytes = 8;
35aff10b
AM		 6284 mode = DImode;
6285 gen_mov_func = gen_movdi;
b6c9286a 6286 }
cc0d9ba8 6287 else if (bytes >= 4 && (align >= 4 || ! STRICT_ALIGNMENT))
3933e0e1
MM		 6288 {
6289 move_bytes = 4;
35aff10b
AM		 6290 mode = SImode;
6291 gen_mov_func = gen_movsi;
3933e0e1 6292 }
cc0d9ba8 6293 else if (bytes >= 2 && (align >= 2 || ! STRICT_ALIGNMENT))
3933e0e1
MM		 6294 {
6295 move_bytes = 2;
35aff10b
AM		 6296 mode = HImode;
6297 gen_mov_func = gen_movhi;
3933e0e1
MM		 6298 }
6299 else
6300 {
6301 move_bytes = 1;
35aff10b
AM		 6302 mode = QImode;
6303 gen_mov_func = gen_movqi;
3933e0e1
MM		 6304 }
6305
35aff10b
AM		 6306 src = adjust_address (orig_src, mode, offset);
6307 dest = adjust_address (orig_dest, mode, offset);
6308 tmp_reg = gen_reg_rtx (mode);
6309
6310 emit_insn ((*gen_mov_func) (tmp_reg, src));
6311 stores[num_reg++] = (*gen_mov_func) (dest, tmp_reg);
6312
3933e0e1
MM		 6313 if (num_reg >= MAX_MOVE_REG)
6314 {
6315 for (i = 0; i < num_reg; i++)
6316 emit_insn (stores[i]);
6317 num_reg = 0;
7e69e155
MM		 6318 }
6319 }
3933e0e1 6320
b6c9286a
MM		 6321 for (i = 0; i < num_reg; i++)
6322 emit_insn (stores[i]);
7e69e155
MM		 6323 }
6324
6325 return 1;
6326}
6327
9878760c
RK		 6328\f
6329/* Return 1 if OP is a load multiple operation. It is known to be a
6330 PARALLEL and the first section will be tested. */
6331
6332int
6333load_multiple_operation (op, mode)
6334 rtx op;
296b8152 6335 enum machine_mode mode ATTRIBUTE_UNUSED;
9878760c
RK		 6336{
6337 int count = XVECLEN (op, 0);
e2c953b6 6338 unsigned int dest_regno;
9878760c
RK		 6339 rtx src_addr;
6340 int i;
6341
6342 /* Perform a quick check so we don't blow up below. */
6343 if (count <= 1
6344 || GET_CODE (XVECEXP (op, 0, 0)) != SET
6345 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
6346 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM)
6347 return 0;
6348
6349 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
6350 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0);
6351
6352 for (i = 1; i < count; i++)
6353 {
6354 rtx elt = XVECEXP (op, 0, i);
6355
6356 if (GET_CODE (elt) != SET
6357 || GET_CODE (SET_DEST (elt)) != REG
6358 || GET_MODE (SET_DEST (elt)) != SImode
6359 || REGNO (SET_DEST (elt)) != dest_regno + i
6360 || GET_CODE (SET_SRC (elt)) != MEM
6361 || GET_MODE (SET_SRC (elt)) != SImode
6362 || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
6363 || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
6364 || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT
6365 || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != i * 4)
6366 return 0;
6367 }
6368
6369 return 1;
6370}
6371
6372/* Similar, but tests for store multiple. Here, the second vector element
6373 is a CLOBBER. It will be tested later. */
6374
6375int
6376store_multiple_operation (op, mode)
6377 rtx op;
296b8152 6378 enum machine_mode mode ATTRIBUTE_UNUSED;
9878760c
RK		 6379{
6380 int count = XVECLEN (op, 0) - 1;
e2c953b6 6381 unsigned int src_regno;
9878760c
RK		 6382 rtx dest_addr;
6383 int i;
6384
6385 /* Perform a quick check so we don't blow up below. */
6386 if (count <= 1
6387 || GET_CODE (XVECEXP (op, 0, 0)) != SET
6388 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
6389 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG)
6390 return 0;
6391
6392 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
6393 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0);
6394
6395 for (i = 1; i < count; i++)
6396 {
6397 rtx elt = XVECEXP (op, 0, i + 1);
6398
6399 if (GET_CODE (elt) != SET
6400 || GET_CODE (SET_SRC (elt)) != REG
6401 || GET_MODE (SET_SRC (elt)) != SImode
6402 || REGNO (SET_SRC (elt)) != src_regno + i
6403 || GET_CODE (SET_DEST (elt)) != MEM
6404 || GET_MODE (SET_DEST (elt)) != SImode
6405 || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
6406 || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
6407 || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT
6408 || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != i * 4)
6409 return 0;
6410 }
6411
6412 return 1;
6413}
9ebbca7d 6414
9caa3eb2
DE		 6415/* Return a string to perform a load_multiple operation.
6416 operands[0] is the vector.
6417 operands[1] is the source address.
6418 operands[2] is the first destination register. */
6419
6420const char *
6421rs6000_output_load_multiple (operands)
ebe637e3 6422 rtx operands[3];
9caa3eb2
DE		 6423{
6424 /* We have to handle the case where the pseudo used to contain the address
6425 is assigned to one of the output registers. */
6426 int i, j;
6427 int words = XVECLEN (operands[0], 0);
6428 rtx xop[10];
6429
6430 if (XVECLEN (operands[0], 0) == 1)
6431 return "{l|lwz} %2,0(%1)";
6432
6433 for (i = 0; i < words; i++)
6434 if (refers_to_regno_p (REGNO (operands[2]) + i,
6435 REGNO (operands[2]) + i + 1, operands[1], 0))
6436 {
6437 if (i == words-1)
6438 {
6439 xop[0] = GEN_INT (4 * (words-1));
6440 xop[1] = operands[1];
6441 xop[2] = operands[2];
6442 output_asm_insn ("{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,%0(%1)", xop);
6443 return "";
6444 }
6445 else if (i == 0)
6446 {
6447 xop[0] = GEN_INT (4 * (words-1));
6448 xop[1] = operands[1];
6449 xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
6450 output_asm_insn ("{cal %1,4(%1)|addi %1,%1,4}\n\t{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,-4(%1)", xop);
6451 return "";
6452 }
6453 else
6454 {
6455 for (j = 0; j < words; j++)
6456 if (j != i)
6457 {
6458 xop[0] = GEN_INT (j * 4);
6459 xop[1] = operands[1];
6460 xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + j);
6461 output_asm_insn ("{l|lwz} %2,%0(%1)", xop);
6462 }
6463 xop[0] = GEN_INT (i * 4);
6464 xop[1] = operands[1];
6465 output_asm_insn ("{l|lwz} %1,%0(%1)", xop);
6466 return "";
6467 }
6468 }
6469
6470 return "{lsi|lswi} %2,%1,%N0";
6471}
6472
00b960c7
AH		 6473/* Return 1 for a parallel vrsave operation. */
6474
6475int
6476vrsave_operation (op, mode)
6477 rtx op;
6478 enum machine_mode mode ATTRIBUTE_UNUSED;
6479{
6480 int count = XVECLEN (op, 0);
6481 unsigned int dest_regno, src_regno;
6482 int i;
6483
6484 if (count <= 1
6485 || GET_CODE (XVECEXP (op, 0, 0)) != SET
6486 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
a004eb82 6487 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC_VOLATILE)
00b960c7
AH		 6488 return 0;
6489
6490 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
6491 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
6492
6493 if (dest_regno != VRSAVE_REGNO
6494 && src_regno != VRSAVE_REGNO)
6495 return 0;
6496
6497 for (i = 1; i < count; i++)
6498 {
6499 rtx elt = XVECEXP (op, 0, i);
6500
9aa86737
AH		 6501 if (GET_CODE (elt) != CLOBBER
6502 && GET_CODE (elt) != SET)
00b960c7
AH		 6503 return 0;
6504 }
6505
6506 return 1;
6507}
6508
a4f6c312 6509/* Return 1 for an PARALLEL suitable for mtcrf. */
9ebbca7d
GK		 6510
6511int
6512mtcrf_operation (op, mode)
6513 rtx op;
6514 enum machine_mode mode ATTRIBUTE_UNUSED;
6515{
6516 int count = XVECLEN (op, 0);
6517 int i;
9ebbca7d
GK		 6518 rtx src_reg;
6519
6520 /* Perform a quick check so we don't blow up below. */
e35b9579
GK		 6521 if (count < 1
6522 || GET_CODE (XVECEXP (op, 0, 0)) != SET
6523 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC
6524 || XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2)
9ebbca7d 6525 return 0;
e35b9579 6526 src_reg = XVECEXP (SET_SRC (XVECEXP (op, 0, 0)), 0, 0);
9ebbca7d
GK		 6527
6528 if (GET_CODE (src_reg) != REG
6529 || GET_MODE (src_reg) != SImode
6530 || ! INT_REGNO_P (REGNO (src_reg)))
6531 return 0;
6532
e35b9579 6533 for (i = 0; i < count; i++)
9ebbca7d
GK		 6534 {
6535 rtx exp = XVECEXP (op, 0, i);
6536 rtx unspec;
6537 int maskval;
6538
6539 if (GET_CODE (exp) != SET
6540 || GET_CODE (SET_DEST (exp)) != REG
6541 || GET_MODE (SET_DEST (exp)) != CCmode
6542 || ! CR_REGNO_P (REGNO (SET_DEST (exp))))
6543 return 0;
6544 unspec = SET_SRC (exp);
6545 maskval = 1 << (MAX_CR_REGNO - REGNO (SET_DEST (exp)));
9ebbca7d
GK		 6546
6547 if (GET_CODE (unspec) != UNSPEC
6548 || XINT (unspec, 1) != 20
6549 || XVECLEN (unspec, 0) != 2
6550 || XVECEXP (unspec, 0, 0) != src_reg
6551 || GET_CODE (XVECEXP (unspec, 0, 1)) != CONST_INT
6552 || INTVAL (XVECEXP (unspec, 0, 1)) != maskval)
6553 return 0;
6554 }
e35b9579 6555 return 1;
9ebbca7d
GK		 6556}
6557
a4f6c312 6558/* Return 1 for an PARALLEL suitable for lmw. */
9ebbca7d
GK		 6559
6560int
6561lmw_operation (op, mode)
6562 rtx op;
6563 enum machine_mode mode ATTRIBUTE_UNUSED;
6564{
6565 int count = XVECLEN (op, 0);
e2c953b6 6566 unsigned int dest_regno;
9ebbca7d 6567 rtx src_addr;
e2c953b6 6568 unsigned int base_regno;
9ebbca7d
GK		 6569 HOST_WIDE_INT offset;
6570 int i;
6571
6572 /* Perform a quick check so we don't blow up below. */
6573 if (count <= 1
6574 || GET_CODE (XVECEXP (op, 0, 0)) != SET
6575 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
6576 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM)
6577 return 0;
6578
6579 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
6580 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0);
6581
6582 if (dest_regno > 31
e2c953b6 6583 || count != 32 - (int) dest_regno)
9ebbca7d
GK		 6584 return 0;
6585
258bfae2 6586 if (LEGITIMATE_INDIRECT_ADDRESS_P (src_addr, 0))
9ebbca7d
GK		 6587 {
6588 offset = 0;
6589 base_regno = REGNO (src_addr);
6590 if (base_regno == 0)
6591 return 0;
6592 }
258bfae2 6593 else if (LEGITIMATE_OFFSET_ADDRESS_P (SImode, src_addr, 0))
9ebbca7d
GK		 6594 {
6595 offset = INTVAL (XEXP (src_addr, 1));
6596 base_regno = REGNO (XEXP (src_addr, 0));
6597 }
6598 else
6599 return 0;
6600
6601 for (i = 0; i < count; i++)
6602 {
6603 rtx elt = XVECEXP (op, 0, i);
6604 rtx newaddr;
6605 rtx addr_reg;
6606 HOST_WIDE_INT newoffset;
6607
6608 if (GET_CODE (elt) != SET
6609 || GET_CODE (SET_DEST (elt)) != REG
6610 || GET_MODE (SET_DEST (elt)) != SImode
6611 || REGNO (SET_DEST (elt)) != dest_regno + i
6612 || GET_CODE (SET_SRC (elt)) != MEM
6613 || GET_MODE (SET_SRC (elt)) != SImode)
6614 return 0;
6615 newaddr = XEXP (SET_SRC (elt), 0);
258bfae2 6616 if (LEGITIMATE_INDIRECT_ADDRESS_P (newaddr, 0))
9ebbca7d
GK		 6617 {
6618 newoffset = 0;
6619 addr_reg = newaddr;
6620 }
258bfae2 6621 else if (LEGITIMATE_OFFSET_ADDRESS_P (SImode, newaddr, 0))
9ebbca7d
GK		 6622 {
6623 addr_reg = XEXP (newaddr, 0);
6624 newoffset = INTVAL (XEXP (newaddr, 1));
6625 }
6626 else
6627 return 0;
6628 if (REGNO (addr_reg) != base_regno
6629 || newoffset != offset + 4 * i)
6630 return 0;
6631 }
6632
6633 return 1;
6634}
6635
a4f6c312 6636/* Return 1 for an PARALLEL suitable for stmw. */
9ebbca7d
GK		 6637
6638int
6639stmw_operation (op, mode)
6640 rtx op;
6641 enum machine_mode mode ATTRIBUTE_UNUSED;
6642{
6643 int count = XVECLEN (op, 0);
e2c953b6 6644 unsigned int src_regno;
9ebbca7d 6645 rtx dest_addr;
e2c953b6 6646 unsigned int base_regno;
9ebbca7d
GK		 6647 HOST_WIDE_INT offset;
6648 int i;
6649
6650 /* Perform a quick check so we don't blow up below. */
6651 if (count <= 1
6652 || GET_CODE (XVECEXP (op, 0, 0)) != SET
6653 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
6654 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG)
6655 return 0;
6656
6657 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
6658 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0);
6659
6660 if (src_regno > 31
e2c953b6 6661 || count != 32 - (int) src_regno)
9ebbca7d
GK		 6662 return 0;
6663
258bfae2 6664 if (LEGITIMATE_INDIRECT_ADDRESS_P (dest_addr, 0))
9ebbca7d
GK		 6665 {
6666 offset = 0;
6667 base_regno = REGNO (dest_addr);
6668 if (base_regno == 0)
6669 return 0;
6670 }
258bfae2 6671 else if (LEGITIMATE_OFFSET_ADDRESS_P (SImode, dest_addr, 0))
9ebbca7d
GK		 6672 {
6673 offset = INTVAL (XEXP (dest_addr, 1));
6674 base_regno = REGNO (XEXP (dest_addr, 0));
6675 }
6676 else
6677 return 0;
6678
6679 for (i = 0; i < count; i++)
6680 {
6681 rtx elt = XVECEXP (op, 0, i);
6682 rtx newaddr;
6683 rtx addr_reg;
6684 HOST_WIDE_INT newoffset;
6685
6686 if (GET_CODE (elt) != SET
6687 || GET_CODE (SET_SRC (elt)) != REG
6688 || GET_MODE (SET_SRC (elt)) != SImode
6689 || REGNO (SET_SRC (elt)) != src_regno + i
6690 || GET_CODE (SET_DEST (elt)) != MEM
6691 || GET_MODE (SET_DEST (elt)) != SImode)
6692 return 0;
6693 newaddr = XEXP (SET_DEST (elt), 0);
258bfae2 6694 if (LEGITIMATE_INDIRECT_ADDRESS_P (newaddr, 0))
9ebbca7d
GK		 6695 {
6696 newoffset = 0;
6697 addr_reg = newaddr;
6698 }
258bfae2 6699 else if (LEGITIMATE_OFFSET_ADDRESS_P (SImode, newaddr, 0))
9ebbca7d
GK		 6700 {
6701 addr_reg = XEXP (newaddr, 0);
6702 newoffset = INTVAL (XEXP (newaddr, 1));
6703 }
6704 else
6705 return 0;
6706 if (REGNO (addr_reg) != base_regno
6707 || newoffset != offset + 4 * i)
6708 return 0;
6709 }
6710
6711 return 1;
6712}
9878760c 6713\f
a4f6c312
SS		 6714/* A validation routine: say whether CODE, a condition code, and MODE
6715 match. The other alternatives either don't make sense or should
6716 never be generated. */
39a10a29 6717
39a10a29
GK		 6718static void
6719validate_condition_mode (code, mode)
6720 enum rtx_code code;
6721 enum machine_mode mode;
6722{
6723 if (GET_RTX_CLASS (code) != '<'
6724 || GET_MODE_CLASS (mode) != MODE_CC)
6725 abort ();
6726
6727 /* These don't make sense. */
6728 if ((code == GT || code == LT || code == GE || code == LE)
6729 && mode == CCUNSmode)
6730 abort ();
6731
6732 if ((code == GTU || code == LTU || code == GEU || code == LEU)
6733 && mode != CCUNSmode)
6734 abort ();
6735
6736 if (mode != CCFPmode
6737 && (code == ORDERED || code == UNORDERED
6738 || code == UNEQ || code == LTGT
6739 || code == UNGT || code == UNLT
6740 || code == UNGE || code == UNLE))
a4f6c312 6741 abort ();
39a10a29 6742
de6c5979 6743 /* These should never be generated except for
ad72b533 6744 flag_unsafe_math_optimizations and flag_finite_math_only. */
39a10a29 6745 if (mode == CCFPmode
de6c5979 6746 && ! flag_unsafe_math_optimizations
ad72b533 6747 && ! flag_finite_math_only
39a10a29
GK		 6748 && (code == LE || code == GE
6749 || code == UNEQ || code == LTGT
6750 || code == UNGT || code == UNLT))
6751 abort ();
6752
6753 /* These are invalid; the information is not there. */
6754 if (mode == CCEQmode
6755 && code != EQ && code != NE)
6756 abort ();
6757}
6758
9878760c
RK		 6759/* Return 1 if OP is a comparison operation that is valid for a branch insn.
6760 We only check the opcode against the mode of the CC value here. */
6761
6762int
6763branch_comparison_operator (op, mode)
592696dd 6764 rtx op;
296b8152 6765 enum machine_mode mode ATTRIBUTE_UNUSED;
9878760c
RK		 6766{
6767 enum rtx_code code = GET_CODE (op);
6768 enum machine_mode cc_mode;
6769
6770 if (GET_RTX_CLASS (code) != '<')
6771 return 0;
6772
6773 cc_mode = GET_MODE (XEXP (op, 0));
6774 if (GET_MODE_CLASS (cc_mode) != MODE_CC)
6775 return 0;
6776
39a10a29 6777 validate_condition_mode (code, cc_mode);
9878760c 6778
39a10a29
GK		 6779 return 1;
6780}
6781
6782/* Return 1 if OP is a comparison operation that is valid for a branch
6783 insn and which is true if the corresponding bit in the CC register
6784 is set. */
6785
6786int
6787branch_positive_comparison_operator (op, mode)
592696dd 6788 rtx op;
39a10a29
GK		 6789 enum machine_mode mode;
6790{
6791 enum rtx_code code;
6792
6793 if (! branch_comparison_operator (op, mode))
9878760c
RK		 6794 return 0;
6795
39a10a29
GK		 6796 code = GET_CODE (op);
6797 return (code == EQ || code == LT || code == GT
a3170dc6 6798 || (TARGET_SPE && TARGET_HARD_FLOAT && !TARGET_FPRS && code == NE)
39a10a29
GK		 6799 || code == LTU || code == GTU
6800 || code == UNORDERED);
9878760c
RK		 6801}
6802
6803/* Return 1 if OP is a comparison operation that is valid for an scc insn.
6804 We check the opcode against the mode of the CC value and disallow EQ or
6805 NE comparisons for integers. */
6806
6807int
6808scc_comparison_operator (op, mode)
592696dd 6809 rtx op;
9878760c
RK		 6810 enum machine_mode mode;
6811{
6812 enum rtx_code code = GET_CODE (op);
6813 enum machine_mode cc_mode;
6814
6815 if (GET_MODE (op) != mode && mode != VOIDmode)
6816 return 0;
6817
6818 if (GET_RTX_CLASS (code) != '<')
6819 return 0;
6820
6821 cc_mode = GET_MODE (XEXP (op, 0));
6822 if (GET_MODE_CLASS (cc_mode) != MODE_CC)
6823 return 0;
6824
39a10a29 6825 validate_condition_mode (code, cc_mode);
9878760c 6826
39a10a29 6827 if (code == NE && cc_mode != CCFPmode)
c5defebb
RK		 6828 return 0;
6829
9878760c
RK		 6830 return 1;
6831}
e0cd0770
JC		 6832
6833int
6834trap_comparison_operator (op, mode)
6835 rtx op;
6836 enum machine_mode mode;
6837{
6838 if (mode != VOIDmode && mode != GET_MODE (op))
6839 return 0;
39a10a29 6840 return GET_RTX_CLASS (GET_CODE (op)) == '<';
e0cd0770 6841}
dfbdccdb
GK		 6842
6843int
6844boolean_operator (op, mode)
6845 rtx op;
6846 enum machine_mode mode ATTRIBUTE_UNUSED;
6847{
6848 enum rtx_code code = GET_CODE (op);
6849 return (code == AND || code == IOR || code == XOR);
6850}
1d328b19
GK		 6851
6852int
6853boolean_or_operator (op, mode)
6854 rtx op;
6855 enum machine_mode mode ATTRIBUTE_UNUSED;
6856{
6857 enum rtx_code code = GET_CODE (op);
6858 return (code == IOR || code == XOR);
6859}
50a0b056
GK		 6860
6861int
6862min_max_operator (op, mode)
6863 rtx op;
6864 enum machine_mode mode ATTRIBUTE_UNUSED;
6865{
6866 enum rtx_code code = GET_CODE (op);
6867 return (code == SMIN || code == SMAX || code == UMIN || code == UMAX);
6868}
9878760c
RK		 6869\f
6870/* Return 1 if ANDOP is a mask that has no bits on that are not in the
6871 mask required to convert the result of a rotate insn into a shift
b1765bde 6872 left insn of SHIFTOP bits. Both are known to be SImode CONST_INT. */
9878760c
RK		 6873
6874int
6875includes_lshift_p (shiftop, andop)
592696dd
SS		 6876 rtx shiftop;
6877 rtx andop;
9878760c 6878{
e2c953b6
DE		 6879 unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
6880
6881 shift_mask <<= INTVAL (shiftop);
9878760c 6882
b1765bde 6883 return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0;
9878760c
RK		 6884}
6885
6886/* Similar, but for right shift. */
6887
6888int
6889includes_rshift_p (shiftop, andop)
592696dd
SS		 6890 rtx shiftop;
6891 rtx andop;
9878760c 6892{
a7653a2c 6893 unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
9878760c
RK		 6894
6895 shift_mask >>= INTVAL (shiftop);
6896
b1765bde 6897 return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0;
e2c953b6
DE		 6898}
6899
c5059423
AM		 6900/* Return 1 if ANDOP is a mask suitable for use with an rldic insn
6901 to perform a left shift. It must have exactly SHIFTOP least
6902 signifigant 0's, then one or more 1's, then zero or more 0's. */
e2c953b6
DE		 6903
6904int
c5059423 6905includes_rldic_lshift_p (shiftop, andop)
592696dd
SS		 6906 rtx shiftop;
6907 rtx andop;
e2c953b6 6908{
c5059423
AM		 6909 if (GET_CODE (andop) == CONST_INT)
6910 {
02071907 6911 HOST_WIDE_INT c, lsb, shift_mask;
e2c953b6 6912
c5059423 6913 c = INTVAL (andop);
02071907 6914 if (c == 0 || c == ~0)
c5059423 6915 return 0;
e2c953b6 6916
02071907 6917 shift_mask = ~0;
c5059423
AM		 6918 shift_mask <<= INTVAL (shiftop);
6919
6920 /* Find the least signifigant one bit. */
6921 lsb = c & -c;
6922
6923 /* It must coincide with the LSB of the shift mask. */
6924 if (-lsb != shift_mask)
6925 return 0;
e2c953b6 6926
c5059423
AM		 6927 /* Invert to look for the next transition (if any). */
6928 c = ~c;
6929
6930 /* Remove the low group of ones (originally low group of zeros). */
6931 c &= -lsb;
6932
6933 /* Again find the lsb, and check we have all 1's above. */
6934 lsb = c & -c;
6935 return c == -lsb;
6936 }
6937 else if (GET_CODE (andop) == CONST_DOUBLE
6938 && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode))
6939 {
02071907
AM		 6940 HOST_WIDE_INT low, high, lsb;
6941 HOST_WIDE_INT shift_mask_low, shift_mask_high;
c5059423
AM		 6942
6943 low = CONST_DOUBLE_LOW (andop);
6944 if (HOST_BITS_PER_WIDE_INT < 64)
6945 high = CONST_DOUBLE_HIGH (andop);
6946
6947 if ((low == 0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == 0))
02071907 6948 || (low == ~0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0)))
c5059423
AM		 6949 return 0;
6950
6951 if (HOST_BITS_PER_WIDE_INT < 64 && low == 0)
6952 {
02071907 6953 shift_mask_high = ~0;
c5059423
AM		 6954 if (INTVAL (shiftop) > 32)
6955 shift_mask_high <<= INTVAL (shiftop) - 32;
6956
6957 lsb = high & -high;
6958
6959 if (-lsb != shift_mask_high || INTVAL (shiftop) < 32)
6960 return 0;
6961
6962 high = ~high;
6963 high &= -lsb;
6964
6965 lsb = high & -high;
6966 return high == -lsb;
6967 }
6968
02071907 6969 shift_mask_low = ~0;
c5059423
AM		 6970 shift_mask_low <<= INTVAL (shiftop);
6971
6972 lsb = low & -low;
6973
6974 if (-lsb != shift_mask_low)
6975 return 0;
6976
6977 if (HOST_BITS_PER_WIDE_INT < 64)
6978 high = ~high;
6979 low = ~low;
6980 low &= -lsb;
6981
6982 if (HOST_BITS_PER_WIDE_INT < 64 && low == 0)
6983 {
6984 lsb = high & -high;
6985 return high == -lsb;
6986 }
6987
6988 lsb = low & -low;
6989 return low == -lsb && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0);
6990 }
6991 else
6992 return 0;
6993}
e2c953b6 6994
c5059423
AM		 6995/* Return 1 if ANDOP is a mask suitable for use with an rldicr insn
6996 to perform a left shift. It must have SHIFTOP or more least
6997 signifigant 0's, with the remainder of the word 1's. */
e2c953b6 6998
c5059423
AM		 6999int
7000includes_rldicr_lshift_p (shiftop, andop)
592696dd
SS		 7001 rtx shiftop;
7002 rtx andop;
c5059423 7003{
e2c953b6 7004 if (GET_CODE (andop) == CONST_INT)
c5059423 7005 {
02071907 7006 HOST_WIDE_INT c, lsb, shift_mask;
c5059423 7007
02071907 7008 shift_mask = ~0;
c5059423
AM		 7009 shift_mask <<= INTVAL (shiftop);
7010 c = INTVAL (andop);
7011
7012 /* Find the least signifigant one bit. */
7013 lsb = c & -c;
7014
7015 /* It must be covered by the shift mask.
a4f6c312 7016 This test also rejects c == 0. */
c5059423
AM		 7017 if ((lsb & shift_mask) == 0)
7018 return 0;
7019
7020 /* Check we have all 1's above the transition, and reject all 1's. */
7021 return c == -lsb && lsb != 1;
7022 }
7023 else if (GET_CODE (andop) == CONST_DOUBLE
7024 && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode))
7025 {
02071907 7026 HOST_WIDE_INT low, lsb, shift_mask_low;
c5059423
AM		 7027
7028 low = CONST_DOUBLE_LOW (andop);
7029
7030 if (HOST_BITS_PER_WIDE_INT < 64)
7031 {
02071907 7032 HOST_WIDE_INT high, shift_mask_high;
c5059423
AM		 7033
7034 high = CONST_DOUBLE_HIGH (andop);
7035
7036 if (low == 0)
7037 {
02071907 7038 shift_mask_high = ~0;
c5059423
AM		 7039 if (INTVAL (shiftop) > 32)
7040 shift_mask_high <<= INTVAL (shiftop) - 32;
7041
7042 lsb = high & -high;
7043
7044 if ((lsb & shift_mask_high) == 0)
7045 return 0;
7046
7047 return high == -lsb;
7048 }
7049 if (high != ~0)
7050 return 0;
7051 }
7052
02071907 7053 shift_mask_low = ~0;
c5059423
AM		 7054 shift_mask_low <<= INTVAL (shiftop);
7055
7056 lsb = low & -low;
7057
7058 if ((lsb & shift_mask_low) == 0)
7059 return 0;
7060
7061 return low == -lsb && lsb != 1;
7062 }
e2c953b6 7063 else
c5059423 7064 return 0;
9878760c 7065}
35068b43
RK		 7066
7067/* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates
7068 for lfq and stfq insns.
7069
7070 Note reg1 and reg2 *must* be hard registers. To be sure we will
7071 abort if we are passed pseudo registers. */
7072
7073int
7074registers_ok_for_quad_peep (reg1, reg2)
7075 rtx reg1, reg2;
7076{
7077 /* We might have been passed a SUBREG. */
7078 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
7079 return 0;
7080
7081 return (REGNO (reg1) == REGNO (reg2) - 1);
7082}
7083
a4f6c312
SS		 7084/* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn.
7085 addr1 and addr2 must be in consecutive memory locations
7086 (addr2 == addr1 + 8). */
35068b43
RK		 7087
7088int
7089addrs_ok_for_quad_peep (addr1, addr2)
592696dd
SS		 7090 rtx addr1;
7091 rtx addr2;
35068b43 7092{
e2c953b6 7093 unsigned int reg1;
35068b43
RK		 7094 int offset1;
7095
7096 /* Extract an offset (if used) from the first addr. */
7097 if (GET_CODE (addr1) == PLUS)
7098 {
7099 /* If not a REG, return zero. */
7100 if (GET_CODE (XEXP (addr1, 0)) != REG)
7101 return 0;
7102 else
7103 {
7104 reg1 = REGNO (XEXP (addr1, 0));
7105 /* The offset must be constant! */
7106 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
7107 return 0;
7108 offset1 = INTVAL (XEXP (addr1, 1));
7109 }
7110 }
7111 else if (GET_CODE (addr1) != REG)
7112 return 0;
7113 else
7114 {
7115 reg1 = REGNO (addr1);
7116 /* This was a simple (mem (reg)) expression. Offset is 0. */
7117 offset1 = 0;
7118 }
7119
acad7ed3 7120 /* Make sure the second address is a (mem (plus (reg) (const_int))). */
35068b43
RK		 7121 if (GET_CODE (addr2) != PLUS)
7122 return 0;
7123
7124 if (GET_CODE (XEXP (addr2, 0)) != REG
7125 || GET_CODE (XEXP (addr2, 1)) != CONST_INT)
7126 return 0;
7127
7128 if (reg1 != REGNO (XEXP (addr2, 0)))
7129 return 0;
7130
7131 /* The offset for the second addr must be 8 more than the first addr. */
7132 if (INTVAL (XEXP (addr2, 1)) != offset1 + 8)
7133 return 0;
7134
7135 /* All the tests passed. addr1 and addr2 are valid for lfq or stfq
7136 instructions. */
7137 return 1;
7138}
9878760c
RK		 7139\f
7140/* Return the register class of a scratch register needed to copy IN into
7141 or out of a register in CLASS in MODE. If it can be done directly,
7142 NO_REGS is returned. */
7143
7144enum reg_class
7145secondary_reload_class (class, mode, in)
7146 enum reg_class class;
296b8152 7147 enum machine_mode mode ATTRIBUTE_UNUSED;
9878760c
RK		 7148 rtx in;
7149{
5accd822 7150 int regno;
9878760c 7151
46fad5b7
DJ		 7152 if (TARGET_ELF || (DEFAULT_ABI == ABI_DARWIN && flag_pic))
7153 {
7154 /* We cannot copy a symbolic operand directly into anything
7155 other than BASE_REGS for TARGET_ELF. So indicate that a
7156 register from BASE_REGS is needed as an intermediate
7157 register.
7158
7159 On Darwin, pic addresses require a load from memory, which
7160 needs a base register. */
7161 if (class != BASE_REGS
7162 && (GET_CODE (in) == SYMBOL_REF
7163 || GET_CODE (in) == HIGH
7164 || GET_CODE (in) == LABEL_REF
7165 || GET_CODE (in) == CONST))
7166 return BASE_REGS;
7167 }
e7b7998a 7168
5accd822
DE		 7169 if (GET_CODE (in) == REG)
7170 {
7171 regno = REGNO (in);
7172 if (regno >= FIRST_PSEUDO_REGISTER)
7173 {
7174 regno = true_regnum (in);
7175 if (regno >= FIRST_PSEUDO_REGISTER)
7176 regno = -1;
7177 }
7178 }
7179 else if (GET_CODE (in) == SUBREG)
7180 {
7181 regno = true_regnum (in);
7182 if (regno >= FIRST_PSEUDO_REGISTER)
7183 regno = -1;
7184 }
7185 else
7186 regno = -1;
7187
9878760c
RK		 7188 /* We can place anything into GENERAL_REGS and can put GENERAL_REGS
7189 into anything. */
7190 if (class == GENERAL_REGS || class == BASE_REGS
7191 || (regno >= 0 && INT_REGNO_P (regno)))
7192 return NO_REGS;
7193
7194 /* Constants, memory, and FP registers can go into FP registers. */
7195 if ((regno == -1 || FP_REGNO_P (regno))
7196 && (class == FLOAT_REGS || class == NON_SPECIAL_REGS))
7197 return NO_REGS;
7198
0ac081f6
AH		 7199 /* Memory, and AltiVec registers can go into AltiVec registers. */
7200 if ((regno == -1 || ALTIVEC_REGNO_P (regno))
7201 && class == ALTIVEC_REGS)
7202 return NO_REGS;
7203
9878760c
RK		 7204 /* We can copy among the CR registers. */
7205 if ((class == CR_REGS || class == CR0_REGS)
7206 && regno >= 0 && CR_REGNO_P (regno))
7207 return NO_REGS;
7208
7209 /* Otherwise, we need GENERAL_REGS. */
7210 return GENERAL_REGS;
7211}
7212\f
7213/* Given a comparison operation, return the bit number in CCR to test. We
7214 know this is a valid comparison.
7215
7216 SCC_P is 1 if this is for an scc. That means that %D will have been
7217 used instead of %C, so the bits will be in different places.
7218
b4ac57ab 7219 Return -1 if OP isn't a valid comparison for some reason. */
9878760c
RK		 7220
7221int
7222ccr_bit (op, scc_p)
592696dd 7223 rtx op;
9878760c
RK		 7224 int scc_p;
7225{
7226 enum rtx_code code = GET_CODE (op);
7227 enum machine_mode cc_mode;
7228 int cc_regnum;
7229 int base_bit;
9ebbca7d 7230 rtx reg;
9878760c
RK		 7231
7232 if (GET_RTX_CLASS (code) != '<')
7233 return -1;
7234
9ebbca7d
GK		 7235 reg = XEXP (op, 0);
7236
7237 if (GET_CODE (reg) != REG
7238 || ! CR_REGNO_P (REGNO (reg)))
7239 abort ();
7240
7241 cc_mode = GET_MODE (reg);
7242 cc_regnum = REGNO (reg);
7243 base_bit = 4 * (cc_regnum - CR0_REGNO);
9878760c 7244
39a10a29 7245 validate_condition_mode (code, cc_mode);
c5defebb 7246
9878760c
RK		 7247 switch (code)
7248 {
7249 case NE:
a3170dc6
AH		 7250 if (TARGET_SPE && TARGET_HARD_FLOAT && cc_mode == CCFPmode)
7251 return base_bit + 1;
9878760c
RK		 7252 return scc_p ? base_bit + 3 : base_bit + 2;
7253 case EQ:
a3170dc6
AH		 7254 if (TARGET_SPE && TARGET_HARD_FLOAT && cc_mode == CCFPmode)
7255 return base_bit + 1;
9878760c 7256 return base_bit + 2;
1c882ea4 7257 case GT: case GTU: case UNLE:
9878760c 7258 return base_bit + 1;
1c882ea4 7259 case LT: case LTU: case UNGE:
9878760c 7260 return base_bit;
1c882ea4
GK		 7261 case ORDERED: case UNORDERED:
7262 return base_bit + 3;
9878760c
RK		 7263
7264 case GE: case GEU:
39a10a29 7265 /* If scc, we will have done a cror to put the bit in the
9878760c
RK		 7266 unordered position. So test that bit. For integer, this is ! LT
7267 unless this is an scc insn. */
39a10a29 7268 return scc_p ? base_bit + 3 : base_bit;
9878760c
RK		 7269
7270 case LE: case LEU:
39a10a29 7271 return scc_p ? base_bit + 3 : base_bit + 1;
1c882ea4 7272
9878760c
RK		 7273 default:
7274 abort ();
7275 }
7276}
1ff7789b 7277\f
8d30c4ee 7278/* Return the GOT register. */
1ff7789b
MM		 7279
7280struct rtx_def *
7281rs6000_got_register (value)
5f59ecb7 7282 rtx value ATTRIBUTE_UNUSED;
1ff7789b 7283{
a4f6c312
SS		 7284 /* The second flow pass currently (June 1999) can't update
7285 regs_ever_live without disturbing other parts of the compiler, so
7286 update it here to make the prolog/epilogue code happy. */
1db02437
FS		 7287 if (no_new_pseudos && ! regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM])
7288 regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
1ff7789b 7289
8d30c4ee 7290 current_function_uses_pic_offset_table = 1;
3cb999d8 7291
1ff7789b
MM		 7292 return pic_offset_table_rtx;
7293}
a7df97e6 7294\f
e2500fed
GK		 7295/* Function to init struct machine_function.
7296 This will be called, via a pointer variable,
7297 from push_function_context. */
a7df97e6 7298
e2500fed
GK		 7299static struct machine_function *
7300rs6000_init_machine_status ()
a7df97e6 7301{
e2500fed 7302 return ggc_alloc_cleared (sizeof (machine_function));
a7df97e6 7303}
9878760c 7304\f
0ba1b2ff
AM		 7305/* These macros test for integers and extract the low-order bits. */
7306#define INT_P(X) \
7307((GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST_DOUBLE) \
7308 && GET_MODE (X) == VOIDmode)
7309
7310#define INT_LOWPART(X) \
7311 (GET_CODE (X) == CONST_INT ? INTVAL (X) : CONST_DOUBLE_LOW (X))
7312
7313int
7314extract_MB (op)
7315 rtx op;
7316{
7317 int i;
7318 unsigned long val = INT_LOWPART (op);
7319
7320 /* If the high bit is zero, the value is the first 1 bit we find
7321 from the left. */
7322 if ((val & 0x80000000) == 0)
7323 {
7324 if ((val & 0xffffffff) == 0)
7325 abort ();
7326
7327 i = 1;
7328 while (((val <<= 1) & 0x80000000) == 0)
7329 ++i;
7330 return i;
7331 }
7332
7333 /* If the high bit is set and the low bit is not, or the mask is all
7334 1's, the value is zero. */
7335 if ((val & 1) == 0 || (val & 0xffffffff) == 0xffffffff)
7336 return 0;
7337
7338 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
7339 from the right. */
7340 i = 31;
7341 while (((val >>= 1) & 1) != 0)
7342 --i;
7343
7344 return i;
7345}
7346
7347int
7348extract_ME (op)
7349 rtx op;
7350{
7351 int i;
7352 unsigned long val = INT_LOWPART (op);
7353
7354 /* If the low bit is zero, the value is the first 1 bit we find from
7355 the right. */
7356 if ((val & 1) == 0)
7357 {
7358 if ((val & 0xffffffff) == 0)
7359 abort ();
7360
7361 i = 30;
7362 while (((val >>= 1) & 1) == 0)
7363 --i;
7364
7365 return i;
7366 }
7367
7368 /* If the low bit is set and the high bit is not, or the mask is all
7369 1's, the value is 31. */
7370 if ((val & 0x80000000) == 0 || (val & 0xffffffff) == 0xffffffff)
7371 return 31;
7372
7373 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
7374 from the left. */
7375 i = 0;
7376 while (((val <<= 1) & 0x80000000) != 0)
7377 ++i;
7378
7379 return i;
7380}
7381
9878760c
RK		 7382/* Print an operand. Recognize special options, documented below. */
7383
38c1f2d7 7384#if TARGET_ELF
d9407988 7385#define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel")
8fbd2dc7 7386#define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13)
ba5e43aa
MM		 7387#else
7388#define SMALL_DATA_RELOC "sda21"
8fbd2dc7 7389#define SMALL_DATA_REG 0
ba5e43aa
MM		 7390#endif
7391
9878760c
RK		 7392void
7393print_operand (file, x, code)
7394 FILE *file;
7395 rtx x;
9ebbca7d 7396 int code;
9878760c
RK		 7397{
7398 int i;
a260abc9 7399 HOST_WIDE_INT val;
0ba1b2ff 7400 unsigned HOST_WIDE_INT uval;
9878760c
RK		 7401
7402 switch (code)
7403 {
a8b3aeda 7404 case '.':
a85d226b
RK		 7405 /* Write out an instruction after the call which may be replaced
7406 with glue code by the loader. This depends on the AIX version. */
7407 asm_fprintf (file, RS6000_CALL_GLUE);
a8b3aeda
RK		 7408 return;
7409
81eace42
GK		 7410 /* %a is output_address. */
7411
9854d9ed
RK		 7412 case 'A':
7413 /* If X is a constant integer whose low-order 5 bits are zero,
7414 write 'l'. Otherwise, write 'r'. This is a kludge to fix a bug
76229ac8 7415 in the AIX assembler where "sri" with a zero shift count
20e26713 7416 writes a trash instruction. */
9854d9ed 7417 if (GET_CODE (x) == CONST_INT && (INTVAL (x) & 31) == 0)
76229ac8 7418 putc ('l', file);
9854d9ed 7419 else
76229ac8 7420 putc ('r', file);
9854d9ed
RK		 7421 return;
7422
7423 case 'b':
e2c953b6
DE		 7424 /* If constant, low-order 16 bits of constant, unsigned.
7425 Otherwise, write normally. */
7426 if (INT_P (x))
7427 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 0xffff);
7428 else
7429 print_operand (file, x, 0);
cad12a8d
RK		 7430 return;
7431
a260abc9
DE		 7432 case 'B':
7433 /* If the low-order bit is zero, write 'r'; otherwise, write 'l'
7434 for 64-bit mask direction. */
296b8152 7435 putc (((INT_LOWPART(x) & 1) == 0 ? 'r' : 'l'), file);
a238cd8b 7436 return;
a260abc9 7437
81eace42
GK		 7438 /* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise
7439 output_operand. */
7440
9854d9ed 7441 case 'D':
39a10a29
GK		 7442 /* There used to be a comment for 'C' reading "This is an
7443 optional cror needed for certain floating-point
7444 comparisons. Otherwise write nothing." */
7445
9854d9ed
RK		 7446 /* Similar, except that this is for an scc, so we must be able to
7447 encode the test in a single bit that is one. We do the above
7448 for any LE, GE, GEU, or LEU and invert the bit for NE. */
7449 if (GET_CODE (x) == LE || GET_CODE (x) == GE
7450 || GET_CODE (x) == LEU || GET_CODE (x) == GEU)
7451 {
9ebbca7d 7452 int base_bit = 4 * (REGNO (XEXP (x, 0)) - CR0_REGNO);
9854d9ed
RK		 7453
7454 fprintf (file, "cror %d,%d,%d\n\t", base_bit + 3,
7455 base_bit + 2,
7456 base_bit + (GET_CODE (x) == GE || GET_CODE (x) == GEU));
7457 }
7458
7459 else if (GET_CODE (x) == NE)
7460 {
9ebbca7d 7461 int base_bit = 4 * (REGNO (XEXP (x, 0)) - CR0_REGNO);
9854d9ed
RK		 7462
7463 fprintf (file, "crnor %d,%d,%d\n\t", base_bit + 3,
7464 base_bit + 2, base_bit + 2);
7465 }
a3170dc6
AH		 7466 else if (TARGET_SPE && TARGET_HARD_FLOAT
7467 && GET_CODE (x) == EQ
7468 && GET_MODE (XEXP (x, 0)) == CCFPmode)
7469 {
7470 int base_bit = 4 * (REGNO (XEXP (x, 0)) - CR0_REGNO);
7471
7472 fprintf (file, "crnor %d,%d,%d\n\t", base_bit + 1,
7473 base_bit + 1, base_bit + 1);
7474 }
9854d9ed
RK		 7475 return;
7476
7477 case 'E':
39a10a29 7478 /* X is a CR register. Print the number of the EQ bit of the CR */
9854d9ed
RK		 7479 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
7480 output_operand_lossage ("invalid %%E value");
78fbdbf7 7481 else
39a10a29 7482 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 2);
a85d226b 7483 return;
9854d9ed
RK		 7484
7485 case 'f':
7486 /* X is a CR register. Print the shift count needed to move it
7487 to the high-order four bits. */
7488 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
7489 output_operand_lossage ("invalid %%f value");
7490 else
9ebbca7d 7491 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO));
9854d9ed
RK		 7492 return;
7493
7494 case 'F':
7495 /* Similar, but print the count for the rotate in the opposite
7496 direction. */
7497 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
7498 output_operand_lossage ("invalid %%F value");
7499 else
9ebbca7d 7500 fprintf (file, "%d", 32 - 4 * (REGNO (x) - CR0_REGNO));
9854d9ed
RK		 7501 return;
7502
7503 case 'G':
7504 /* X is a constant integer. If it is negative, print "m",
43aa4e05 7505 otherwise print "z". This is to make an aze or ame insn. */
9854d9ed
RK		 7506 if (GET_CODE (x) != CONST_INT)
7507 output_operand_lossage ("invalid %%G value");
7508 else if (INTVAL (x) >= 0)
76229ac8 7509 putc ('z', file);
9854d9ed 7510 else
76229ac8 7511 putc ('m', file);
9854d9ed 7512 return;
e2c953b6 7513
9878760c 7514 case 'h':
a4f6c312
SS		 7515 /* If constant, output low-order five bits. Otherwise, write
7516 normally. */
9878760c 7517 if (INT_P (x))
5f59ecb7 7518 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 31);
9878760c
RK		 7519 else
7520 print_operand (file, x, 0);
7521 return;
7522
64305719 7523 case 'H':
a4f6c312
SS		 7524 /* If constant, output low-order six bits. Otherwise, write
7525 normally. */
64305719 7526 if (INT_P (x))
5f59ecb7 7527 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 63);
64305719
DE		 7528 else
7529 print_operand (file, x, 0);
7530 return;
7531
9854d9ed
RK		 7532 case 'I':
7533 /* Print `i' if this is a constant, else nothing. */
9878760c 7534 if (INT_P (x))
76229ac8 7535 putc ('i', file);
9878760c
RK		 7536 return;
7537
9854d9ed
RK		 7538 case 'j':
7539 /* Write the bit number in CCR for jump. */
7540 i = ccr_bit (x, 0);
7541 if (i == -1)
7542 output_operand_lossage ("invalid %%j code");
9878760c 7543 else
9854d9ed 7544 fprintf (file, "%d", i);
9878760c
RK		 7545 return;
7546
9854d9ed
RK		 7547 case 'J':
7548 /* Similar, but add one for shift count in rlinm for scc and pass
7549 scc flag to `ccr_bit'. */
7550 i = ccr_bit (x, 1);
7551 if (i == -1)
7552 output_operand_lossage ("invalid %%J code");
7553 else
a0466a68
RK		 7554 /* If we want bit 31, write a shift count of zero, not 32. */
7555 fprintf (file, "%d", i == 31 ? 0 : i + 1);
9878760c
RK		 7556 return;
7557
9854d9ed
RK		 7558 case 'k':
7559 /* X must be a constant. Write the 1's complement of the
7560 constant. */
9878760c 7561 if (! INT_P (x))
9854d9ed 7562 output_operand_lossage ("invalid %%k value");
e2c953b6
DE		 7563 else
7564 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~ INT_LOWPART (x));
9878760c
RK		 7565 return;
7566
81eace42 7567 case 'K':
9ebbca7d
GK		 7568 /* X must be a symbolic constant on ELF. Write an
7569 expression suitable for an 'addi' that adds in the low 16
7570 bits of the MEM. */
7571 if (GET_CODE (x) != CONST)
7572 {
7573 print_operand_address (file, x);
7574 fputs ("@l", file);
7575 }
7576 else
7577 {
7578 if (GET_CODE (XEXP (x, 0)) != PLUS
7579 || (GET_CODE (XEXP (XEXP (x, 0), 0)) != SYMBOL_REF
7580 && GET_CODE (XEXP (XEXP (x, 0), 0)) != LABEL_REF)
7581 || GET_CODE (XEXP (XEXP (x, 0), 1)) != CONST_INT)
53cd5d6c 7582 output_operand_lossage ("invalid %%K value");
9ebbca7d
GK		 7583 print_operand_address (file, XEXP (XEXP (x, 0), 0));
7584 fputs ("@l", file);
ed8d2920
MM		 7585 /* For GNU as, there must be a non-alphanumeric character
7586 between 'l' and the number. The '-' is added by
7587 print_operand() already. */
7588 if (INTVAL (XEXP (XEXP (x, 0), 1)) >= 0)
7589 fputs ("+", file);
9ebbca7d
GK		 7590 print_operand (file, XEXP (XEXP (x, 0), 1), 0);
7591 }
81eace42
GK		 7592 return;
7593
7594 /* %l is output_asm_label. */
9ebbca7d 7595
9854d9ed
RK		 7596 case 'L':
7597 /* Write second word of DImode or DFmode reference. Works on register
7598 or non-indexed memory only. */
7599 if (GET_CODE (x) == REG)
5ebfb2ba 7600 fprintf (file, "%s", reg_names[REGNO (x) + 1]);
9854d9ed
RK		 7601 else if (GET_CODE (x) == MEM)
7602 {
7603 /* Handle possible auto-increment. Since it is pre-increment and
1427100a 7604 we have already done it, we can just use an offset of word. */
9854d9ed
RK		 7605 if (GET_CODE (XEXP (x, 0)) == PRE_INC
7606 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
ed8908e7
RK		 7607 output_address (plus_constant (XEXP (XEXP (x, 0), 0),
7608 UNITS_PER_WORD));
9854d9ed 7609 else
d7624dc0
RK		 7610 output_address (XEXP (adjust_address_nv (x, SImode,
7611 UNITS_PER_WORD),
7612 0));
ed8908e7 7613
ba5e43aa 7614 if (small_data_operand (x, GET_MODE (x)))
8fbd2dc7
MM		 7615 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
7616 reg_names[SMALL_DATA_REG]);
9854d9ed 7617 }
9878760c 7618 return;
9854d9ed 7619
9878760c
RK		 7620 case 'm':
7621 /* MB value for a mask operand. */
b1765bde 7622 if (! mask_operand (x, SImode))
9878760c
RK		 7623 output_operand_lossage ("invalid %%m value");
7624
0ba1b2ff 7625 fprintf (file, "%d", extract_MB (x));
9878760c
RK		 7626 return;
7627
7628 case 'M':
7629 /* ME value for a mask operand. */
b1765bde 7630 if (! mask_operand (x, SImode))
a260abc9 7631 output_operand_lossage ("invalid %%M value");
9878760c 7632
0ba1b2ff 7633 fprintf (file, "%d", extract_ME (x));
9878760c
RK		 7634 return;
7635
81eace42
GK		 7636 /* %n outputs the negative of its operand. */
7637
9878760c
RK		 7638 case 'N':
7639 /* Write the number of elements in the vector times 4. */
7640 if (GET_CODE (x) != PARALLEL)
7641 output_operand_lossage ("invalid %%N value");
e2c953b6
DE		 7642 else
7643 fprintf (file, "%d", XVECLEN (x, 0) * 4);
9878760c
RK		 7644 return;
7645
7646 case 'O':
7647 /* Similar, but subtract 1 first. */
7648 if (GET_CODE (x) != PARALLEL)
1427100a 7649 output_operand_lossage ("invalid %%O value");
e2c953b6
DE		 7650 else
7651 fprintf (file, "%d", (XVECLEN (x, 0) - 1) * 4);
9878760c
RK		 7652 return;
7653
9854d9ed
RK		 7654 case 'p':
7655 /* X is a CONST_INT that is a power of two. Output the logarithm. */
7656 if (! INT_P (x)
2bfcf297 7657 || INT_LOWPART (x) < 0
9854d9ed
RK		 7658 || (i = exact_log2 (INT_LOWPART (x))) < 0)
7659 output_operand_lossage ("invalid %%p value");
e2c953b6
DE		 7660 else
7661 fprintf (file, "%d", i);
9854d9ed
RK		 7662 return;
7663
9878760c
RK		 7664 case 'P':
7665 /* The operand must be an indirect memory reference. The result
a4f6c312 7666 is the register number. */
9878760c
RK		 7667 if (GET_CODE (x) != MEM || GET_CODE (XEXP (x, 0)) != REG
7668 || REGNO (XEXP (x, 0)) >= 32)
7669 output_operand_lossage ("invalid %%P value");
e2c953b6
DE		 7670 else
7671 fprintf (file, "%d", REGNO (XEXP (x, 0)));
9878760c
RK		 7672 return;
7673
dfbdccdb
GK		 7674 case 'q':
7675 /* This outputs the logical code corresponding to a boolean
7676 expression. The expression may have one or both operands
39a10a29
GK		 7677 negated (if one, only the first one). For condition register
7678 logical operations, it will also treat the negated
7679 CR codes as NOTs, but not handle NOTs of them. */
dfbdccdb 7680 {
63bc1d05 7681 const char *const *t = 0;
dfbdccdb
GK		 7682 const char *s;
7683 enum rtx_code code = GET_CODE (x);
7684 static const char * const tbl[3][3] = {
7685 { "and", "andc", "nor" },
7686 { "or", "orc", "nand" },
7687 { "xor", "eqv", "xor" } };
7688
7689 if (code == AND)
7690 t = tbl[0];
7691 else if (code == IOR)
7692 t = tbl[1];
7693 else if (code == XOR)
7694 t = tbl[2];
7695 else
7696 output_operand_lossage ("invalid %%q value");
7697
7698 if (GET_CODE (XEXP (x, 0)) != NOT)
7699 s = t[0];
7700 else
7701 {
7702 if (GET_CODE (XEXP (x, 1)) == NOT)
7703 s = t[2];
7704 else
7705 s = t[1];
7706 }
7707
7708 fputs (s, file);
7709 }
7710 return;
7711
9854d9ed
RK		 7712 case 'R':
7713 /* X is a CR register. Print the mask for `mtcrf'. */
7714 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
7715 output_operand_lossage ("invalid %%R value");
7716 else
9ebbca7d 7717 fprintf (file, "%d", 128 >> (REGNO (x) - CR0_REGNO));
9878760c 7718 return;
9854d9ed
RK		 7719
7720 case 's':
7721 /* Low 5 bits of 32 - value */
7722 if (! INT_P (x))
7723 output_operand_lossage ("invalid %%s value");
e2c953b6
DE		 7724 else
7725 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (32 - INT_LOWPART (x)) & 31);
9878760c 7726 return;
9854d9ed 7727
a260abc9 7728 case 'S':
0ba1b2ff 7729 /* PowerPC64 mask position. All 0's is excluded.
a260abc9
DE		 7730 CONST_INT 32-bit mask is considered sign-extended so any
7731 transition must occur within the CONST_INT, not on the boundary. */
b1765bde 7732 if (! mask64_operand (x, DImode))
a260abc9
DE		 7733 output_operand_lossage ("invalid %%S value");
7734
0ba1b2ff 7735 uval = INT_LOWPART (x);
a260abc9 7736
0ba1b2ff 7737 if (uval & 1) /* Clear Left */
a260abc9 7738 {
0ba1b2ff
AM		 7739 uval &= ((unsigned HOST_WIDE_INT) 1 << 63 << 1) - 1;
7740 i = 64;
a260abc9 7741 }
0ba1b2ff 7742 else /* Clear Right */
a260abc9 7743 {
0ba1b2ff
AM		 7744 uval = ~uval;
7745 uval &= ((unsigned HOST_WIDE_INT) 1 << 63 << 1) - 1;
7746 i = 63;
a260abc9 7747 }
0ba1b2ff
AM		 7748 while (uval != 0)
7749 --i, uval >>= 1;
7750 if (i < 0)
7751 abort ();
7752 fprintf (file, "%d", i);
7753 return;
a260abc9 7754
a3170dc6
AH		 7755 case 't':
7756 /* Like 'J' but get to the OVERFLOW/UNORDERED bit. */
7757 if (GET_CODE (x) != REG || GET_MODE (x) != CCmode)
7758 abort ();
7759
7760 /* Bit 3 is OV bit. */
7761 i = 4 * (REGNO (x) - CR0_REGNO) + 3;
7762
7763 /* If we want bit 31, write a shift count of zero, not 32. */
7764 fprintf (file, "%d", i == 31 ? 0 : i + 1);
7765 return;
7766
cccf3bdc
DE		 7767 case 'T':
7768 /* Print the symbolic name of a branch target register. */
7769 if (GET_CODE (x) != REG || (REGNO (x) != LINK_REGISTER_REGNUM
7770 && REGNO (x) != COUNT_REGISTER_REGNUM))
7771 output_operand_lossage ("invalid %%T value");
e2c953b6 7772 else if (REGNO (x) == LINK_REGISTER_REGNUM)
cccf3bdc
DE		 7773 fputs (TARGET_NEW_MNEMONICS ? "lr" : "r", file);
7774 else
7775 fputs ("ctr", file);
7776 return;
7777
9854d9ed 7778 case 'u':
802a0058 7779 /* High-order 16 bits of constant for use in unsigned operand. */
9854d9ed
RK		 7780 if (! INT_P (x))
7781 output_operand_lossage ("invalid %%u value");
e2c953b6
DE		 7782 else
7783 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
7784 (INT_LOWPART (x) >> 16) & 0xffff);
9878760c
RK		 7785 return;
7786
802a0058
MM		 7787 case 'v':
7788 /* High-order 16 bits of constant for use in signed operand. */
7789 if (! INT_P (x))
7790 output_operand_lossage ("invalid %%v value");
e2c953b6 7791 else
134c32f6
DE		 7792 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
7793 (INT_LOWPART (x) >> 16) & 0xffff);
7794 return;
802a0058 7795
9854d9ed
RK		 7796 case 'U':
7797 /* Print `u' if this has an auto-increment or auto-decrement. */
7798 if (GET_CODE (x) == MEM
7799 && (GET_CODE (XEXP (x, 0)) == PRE_INC
7800 || GET_CODE (XEXP (x, 0)) == PRE_DEC))
76229ac8 7801 putc ('u', file);
9854d9ed 7802 return;
9878760c 7803
e0cd0770
JC		 7804 case 'V':
7805 /* Print the trap code for this operand. */
7806 switch (GET_CODE (x))
7807 {
7808 case EQ:
7809 fputs ("eq", file); /* 4 */
7810 break;
7811 case NE:
7812 fputs ("ne", file); /* 24 */
7813 break;
7814 case LT:
7815 fputs ("lt", file); /* 16 */
7816 break;
7817 case LE:
7818 fputs ("le", file); /* 20 */
7819 break;
7820 case GT:
7821 fputs ("gt", file); /* 8 */
7822 break;
7823 case GE:
7824 fputs ("ge", file); /* 12 */
7825 break;
7826 case LTU:
7827 fputs ("llt", file); /* 2 */
7828 break;
7829 case LEU:
7830 fputs ("lle", file); /* 6 */
7831 break;
7832 case GTU:
7833 fputs ("lgt", file); /* 1 */
7834 break;
7835 case GEU:
7836 fputs ("lge", file); /* 5 */
7837 break;
7838 default:
7839 abort ();
7840 }
7841 break;
7842
9854d9ed
RK		 7843 case 'w':
7844 /* If constant, low-order 16 bits of constant, signed. Otherwise, write
7845 normally. */
7846 if (INT_P (x))
5f59ecb7
DE		 7847 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
7848 ((INT_LOWPART (x) & 0xffff) ^ 0x8000) - 0x8000);
9854d9ed
RK		 7849 else
7850 print_operand (file, x, 0);
9878760c
RK		 7851 return;
7852
9854d9ed 7853 case 'W':
e2c953b6 7854 /* MB value for a PowerPC64 rldic operand. */
e2c953b6
DE		 7855 val = (GET_CODE (x) == CONST_INT
7856 ? INTVAL (x) : CONST_DOUBLE_HIGH (x));
7857
7858 if (val < 0)
7859 i = -1;
9854d9ed 7860 else
e2c953b6
DE		 7861 for (i = 0; i < HOST_BITS_PER_WIDE_INT; i++)
7862 if ((val <<= 1) < 0)
7863 break;
7864
7865#if HOST_BITS_PER_WIDE_INT == 32
7866 if (GET_CODE (x) == CONST_INT && i >= 0)
7867 i += 32; /* zero-extend high-part was all 0's */
7868 else if (GET_CODE (x) == CONST_DOUBLE && i == 32)
7869 {
7870 val = CONST_DOUBLE_LOW (x);
7871
7872 if (val == 0)
a4f6c312 7873 abort ();
e2c953b6
DE		 7874 else if (val < 0)
7875 --i;
7876 else
7877 for ( ; i < 64; i++)
7878 if ((val <<= 1) < 0)
7879 break;
7880 }
7881#endif
7882
7883 fprintf (file, "%d", i + 1);
9854d9ed 7884 return;
9878760c 7885
9854d9ed
RK		 7886 case 'X':
7887 if (GET_CODE (x) == MEM
258bfae2 7888 && LEGITIMATE_INDEXED_ADDRESS_P (XEXP (x, 0), 0))
76229ac8 7889 putc ('x', file);
9854d9ed 7890 return;
9878760c 7891
9854d9ed
RK		 7892 case 'Y':
7893 /* Like 'L', for third word of TImode */
7894 if (GET_CODE (x) == REG)
5ebfb2ba 7895 fprintf (file, "%s", reg_names[REGNO (x) + 2]);
9854d9ed 7896 else if (GET_CODE (x) == MEM)
9878760c 7897 {
9854d9ed
RK		 7898 if (GET_CODE (XEXP (x, 0)) == PRE_INC
7899 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
a54d04b7 7900 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 8));
9854d9ed 7901 else
d7624dc0 7902 output_address (XEXP (adjust_address_nv (x, SImode, 8), 0));
ba5e43aa 7903 if (small_data_operand (x, GET_MODE (x)))
8fbd2dc7
MM		 7904 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
7905 reg_names[SMALL_DATA_REG]);
9878760c
RK		 7906 }
7907 return;
9854d9ed 7908
9878760c 7909 case 'z':
b4ac57ab
RS		 7910 /* X is a SYMBOL_REF. Write out the name preceded by a
7911 period and without any trailing data in brackets. Used for function
4d30c363
MM		 7912 names. If we are configured for System V (or the embedded ABI) on
7913 the PowerPC, do not emit the period, since those systems do not use
7914 TOCs and the like. */
9878760c
RK		 7915 if (GET_CODE (x) != SYMBOL_REF)
7916 abort ();
7917
b6c9286a
MM		 7918 if (XSTR (x, 0)[0] != '.')
7919 {
7920 switch (DEFAULT_ABI)
7921 {
7922 default:
7923 abort ();
7924
7925 case ABI_AIX:
7926 putc ('.', file);
7927 break;
7928
7929 case ABI_V4:
7930 case ABI_AIX_NODESC:
ee890fe2 7931 case ABI_DARWIN:
b6c9286a 7932 break;
b6c9286a
MM		 7933 }
7934 }
54ee9799
DE		 7935#if TARGET_AIX
7936 RS6000_OUTPUT_BASENAME (file, XSTR (x, 0));
7937#else
9ebbca7d 7938 assemble_name (file, XSTR (x, 0));
54ee9799 7939#endif
9878760c
RK		 7940 return;
7941
9854d9ed
RK		 7942 case 'Z':
7943 /* Like 'L', for last word of TImode. */
7944 if (GET_CODE (x) == REG)
5ebfb2ba 7945 fprintf (file, "%s", reg_names[REGNO (x) + 3]);
9854d9ed
RK		 7946 else if (GET_CODE (x) == MEM)
7947 {
7948 if (GET_CODE (XEXP (x, 0)) == PRE_INC
7949 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
a54d04b7 7950 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 12));
9854d9ed 7951 else
d7624dc0 7952 output_address (XEXP (adjust_address_nv (x, SImode, 12), 0));
ba5e43aa 7953 if (small_data_operand (x, GET_MODE (x)))
8fbd2dc7
MM		 7954 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
7955 reg_names[SMALL_DATA_REG]);
9854d9ed 7956 }
5c23c401 7957 return;
0ac081f6 7958
a3170dc6 7959 /* Print AltiVec or SPE memory operand. */
0ac081f6
AH		 7960 case 'y':
7961 {
7962 rtx tmp;
7963
7964 if (GET_CODE (x) != MEM)
7965 abort ();
7966
7967 tmp = XEXP (x, 0);
7968
a3170dc6
AH		 7969 if (TARGET_SPE)
7970 {
7971 /* Handle [reg]. */
7972 if (GET_CODE (tmp) == REG)
7973 {
7974 fprintf (file, "0(%s)", reg_names[REGNO (tmp)]);
7975 break;
7976 }
7977 /* Handle [reg+UIMM]. */
7978 else if (GET_CODE (tmp) == PLUS &&
7979 GET_CODE (XEXP (tmp, 1)) == CONST_INT)
7980 {
7981 int x;
7982
7983 if (GET_CODE (XEXP (tmp, 0)) != REG)
7984 abort ();
7985
7986 x = INTVAL (XEXP (tmp, 1));
7987 fprintf (file, "%d(%s)", x, reg_names[REGNO (XEXP (tmp, 0))]);
7988 break;
7989 }
7990
7991 /* Fall through. Must be [reg+reg]. */
7992 }
0ac081f6 7993 if (GET_CODE (tmp) == REG)
c62f2db5 7994 fprintf (file, "0,%s", reg_names[REGNO (tmp)]);
0ac081f6
AH		 7995 else if (GET_CODE (tmp) == PLUS && GET_CODE (XEXP (tmp, 1)) == REG)
7996 {
7997 if (REGNO (XEXP (tmp, 0)) == 0)
7998 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 1)) ],
7999 reg_names[ REGNO (XEXP (tmp, 0)) ]);
8000 else
8001 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 0)) ],
8002 reg_names[ REGNO (XEXP (tmp, 1)) ]);
8003 }
8004 else
8005 abort ();
8006 break;
8007 }
9854d9ed 8008
9878760c
RK		 8009 case 0:
8010 if (GET_CODE (x) == REG)
8011 fprintf (file, "%s", reg_names[REGNO (x)]);
8012 else if (GET_CODE (x) == MEM)
8013 {
8014 /* We need to handle PRE_INC and PRE_DEC here, since we need to
8015 know the width from the mode. */
8016 if (GET_CODE (XEXP (x, 0)) == PRE_INC)
79ba6d34
MM		 8017 fprintf (file, "%d(%s)", GET_MODE_SIZE (GET_MODE (x)),
8018 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
9878760c 8019 else if (GET_CODE (XEXP (x, 0)) == PRE_DEC)
79ba6d34
MM		 8020 fprintf (file, "%d(%s)", - GET_MODE_SIZE (GET_MODE (x)),
8021 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
9878760c 8022 else
a54d04b7 8023 output_address (XEXP (x, 0));
9878760c
RK		 8024 }
8025 else
a54d04b7 8026 output_addr_const (file, x);
a85d226b 8027 return;
9878760c
RK		 8028
8029 default:
8030 output_operand_lossage ("invalid %%xn code");
8031 }
8032}
8033\f
8034/* Print the address of an operand. */
8035
8036void
8037print_operand_address (file, x)
8038 FILE *file;
592696dd 8039 rtx x;
9878760c
RK		 8040{
8041 if (GET_CODE (x) == REG)
4697a36c 8042 fprintf (file, "0(%s)", reg_names[ REGNO (x) ]);
9ebbca7d
GK		 8043 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST
8044 || GET_CODE (x) == LABEL_REF)
9878760c
RK		 8045 {
8046 output_addr_const (file, x);
ba5e43aa 8047 if (small_data_operand (x, GET_MODE (x)))
8fbd2dc7
MM		 8048 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
8049 reg_names[SMALL_DATA_REG]);
9ebbca7d 8050 else if (TARGET_TOC)
a4f6c312 8051 abort ();
9878760c
RK		 8052 }
8053 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == REG)
8054 {
8055 if (REGNO (XEXP (x, 0)) == 0)
4697a36c
MM		 8056 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 1)) ],
8057 reg_names[ REGNO (XEXP (x, 0)) ]);
9878760c 8058 else
4697a36c
MM		 8059 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 0)) ],
8060 reg_names[ REGNO (XEXP (x, 1)) ]);
9878760c
RK		 8061 }
8062 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
5f59ecb7
DE		 8063 {
8064 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (XEXP (x, 1)));
8065 fprintf (file, "(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
8066 }
3cb999d8
DE		 8067#if TARGET_ELF
8068 else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG
8069 && CONSTANT_P (XEXP (x, 1)))
4697a36c
MM		 8070 {
8071 output_addr_const (file, XEXP (x, 1));
8072 fprintf (file, "@l(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
8073 }
c859cda6
DJ		 8074#endif
8075#if TARGET_MACHO
8076 else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG
8077 && CONSTANT_P (XEXP (x, 1)))
8078 {
8079 fprintf (file, "lo16(");
8080 output_addr_const (file, XEXP (x, 1));
8081 fprintf (file, ")(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
8082 }
3cb999d8 8083#endif
9ebbca7d
GK		 8084 else if (LEGITIMATE_CONSTANT_POOL_ADDRESS_P (x))
8085 {
2bfcf297 8086 if (TARGET_AIX && (!TARGET_ELF || !TARGET_MINIMAL_TOC))
9ebbca7d 8087 {
2bfcf297
DB		 8088 rtx contains_minus = XEXP (x, 1);
8089 rtx minus, symref;
8090 const char *name;
9ebbca7d
GK		 8091
8092 /* Find the (minus (sym) (toc)) buried in X, and temporarily
a4f6c312 8093 turn it into (sym) for output_addr_const. */
9ebbca7d
GK		 8094 while (GET_CODE (XEXP (contains_minus, 0)) != MINUS)
8095 contains_minus = XEXP (contains_minus, 0);
8096
2bfcf297
DB		 8097 minus = XEXP (contains_minus, 0);
8098 symref = XEXP (minus, 0);
8099 XEXP (contains_minus, 0) = symref;
8100 if (TARGET_ELF)
8101 {
8102 char *newname;
8103
8104 name = XSTR (symref, 0);
8105 newname = alloca (strlen (name) + sizeof ("@toc"));
8106 strcpy (newname, name);
8107 strcat (newname, "@toc");
8108 XSTR (symref, 0) = newname;
8109 }
8110 output_addr_const (file, XEXP (x, 1));
8111 if (TARGET_ELF)
8112 XSTR (symref, 0) = name;
9ebbca7d
GK		 8113 XEXP (contains_minus, 0) = minus;
8114 }
8115 else
8116 output_addr_const (file, XEXP (x, 1));
8117
8118 fprintf (file, "(%s)", reg_names[REGNO (XEXP (x, 0))]);
8119 }
9878760c
RK		 8120 else
8121 abort ();
8122}
8123\f
88cad84b 8124/* Target hook for assembling integer objects. The PowerPC version has
301d03af
RS		 8125 to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP
8126 is defined. It also needs to handle DI-mode objects on 64-bit
8127 targets. */
8128
8129static bool
8130rs6000_assemble_integer (x, size, aligned_p)
8131 rtx x;
8132 unsigned int size;
8133 int aligned_p;
8134{
8135#ifdef RELOCATABLE_NEEDS_FIXUP
8136 /* Special handling for SI values. */
8137 if (size == 4 && aligned_p)
8138 {
8139 extern int in_toc_section PARAMS ((void));
8140 static int recurse = 0;
8141
8142 /* For -mrelocatable, we mark all addresses that need to be fixed up
8143 in the .fixup section. */
8144 if (TARGET_RELOCATABLE
8145 && !in_toc_section ()
8146 && !in_text_section ()
8147 && !recurse
8148 && GET_CODE (x) != CONST_INT
8149 && GET_CODE (x) != CONST_DOUBLE
8150 && CONSTANT_P (x))
8151 {
8152 char buf[256];
8153
8154 recurse = 1;
8155 ASM_GENERATE_INTERNAL_LABEL (buf, "LCP", fixuplabelno);
8156 fixuplabelno++;
8157 ASM_OUTPUT_LABEL (asm_out_file, buf);
8158 fprintf (asm_out_file, "\t.long\t(");
8159 output_addr_const (asm_out_file, x);
8160 fprintf (asm_out_file, ")@fixup\n");
8161 fprintf (asm_out_file, "\t.section\t\".fixup\",\"aw\"\n");
8162 ASM_OUTPUT_ALIGN (asm_out_file, 2);
8163 fprintf (asm_out_file, "\t.long\t");
8164 assemble_name (asm_out_file, buf);
8165 fprintf (asm_out_file, "\n\t.previous\n");
8166 recurse = 0;
8167 return true;
8168 }
8169 /* Remove initial .'s to turn a -mcall-aixdesc function
8170 address into the address of the descriptor, not the function
8171 itself. */
8172 else if (GET_CODE (x) == SYMBOL_REF
8173 && XSTR (x, 0)[0] == '.'
8174 && DEFAULT_ABI == ABI_AIX)
8175 {
8176 const char *name = XSTR (x, 0);
8177 while (*name == '.')
8178 name++;
8179
8180 fprintf (asm_out_file, "\t.long\t%s\n", name);
8181 return true;
8182 }
8183 }
8184#endif /* RELOCATABLE_NEEDS_FIXUP */
8185 return default_assemble_integer (x, size, aligned_p);
8186}
93638d7a
AM		 8187
8188#ifdef HAVE_GAS_HIDDEN
8189/* Emit an assembler directive to set symbol visibility for DECL to
8190 VISIBILITY_TYPE. */
8191
5add3202 8192static void
25fdb4dc 8193rs6000_assemble_visibility (decl, vis)
93638d7a 8194 tree decl;
25fdb4dc 8195 int vis;
93638d7a 8196{
93638d7a
AM		 8197 /* Functions need to have their entry point symbol visibility set as
8198 well as their descriptor symbol visibility. */
8199 if (DEFAULT_ABI == ABI_AIX && TREE_CODE (decl) == FUNCTION_DECL)
8200 {
25fdb4dc
RH		 8201 static const char * const visibility_types[] = {
8202 NULL, "internal", "hidden", "protected"
8203 };
8204
8205 const char *name, *type;
93638d7a
AM		 8206
8207 name = ((* targetm.strip_name_encoding)
8208 (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl))));
25fdb4dc 8209 type = visibility_types[vis];
93638d7a 8210
25fdb4dc
RH		 8211 fprintf (asm_out_file, "\t.%s\t%s\n", type, name);
8212 fprintf (asm_out_file, "\t.%s\t.%s\n", type, name);
93638d7a 8213 }
25fdb4dc
RH		 8214 else
8215 default_assemble_visibility (decl, vis);
93638d7a
AM		 8216}
8217#endif
301d03af 8218\f
39a10a29
GK		 8219enum rtx_code
8220rs6000_reverse_condition (mode, code)
8221 enum machine_mode mode;
8222 enum rtx_code code;
8223{
8224 /* Reversal of FP compares takes care -- an ordered compare
8225 becomes an unordered compare and vice versa. */
de40e1df 8226 if (mode == CCFPmode && !flag_unsafe_math_optimizations)
bab6226b 8227 return reverse_condition_maybe_unordered (code);
39a10a29 8228 else
bab6226b 8229 return reverse_condition (code);
39a10a29
GK		 8230}
8231
39a10a29
GK		 8232/* Generate a compare for CODE. Return a brand-new rtx that
8233 represents the result of the compare. */
a4f6c312 8234
39a10a29
GK		 8235static rtx
8236rs6000_generate_compare (code)
8237 enum rtx_code code;
8238{
8239 enum machine_mode comp_mode;
8240 rtx compare_result;
8241
8242 if (rs6000_compare_fp_p)
8243 comp_mode = CCFPmode;
8244 else if (code == GTU || code == LTU
8245 || code == GEU || code == LEU)
8246 comp_mode = CCUNSmode;
8247 else
8248 comp_mode = CCmode;
8249
8250 /* First, the compare. */
8251 compare_result = gen_reg_rtx (comp_mode);
a3170dc6
AH		 8252
8253 /* SPE FP compare instructions on the GPRs. Yuck! */
8254 if ((TARGET_SPE && TARGET_HARD_FLOAT) && rs6000_compare_fp_p)
8255 {
8256 rtx cmp, or1, or2, or_result, compare_result2;
8257
8258 switch (code)
8259 {
8260 case EQ:
8261 case UNEQ:
8262 case NE:
8263 case LTGT:
8264 cmp = flag_unsafe_math_optimizations
8265 ? gen_tstsfeq_gpr (compare_result, rs6000_compare_op0,
8266 rs6000_compare_op1)
8267 : gen_cmpsfeq_gpr (compare_result, rs6000_compare_op0,
8268 rs6000_compare_op1);
8269 break;
8270 case GT:
8271 case GTU:
8272 case UNGT:
8273 case UNGE:
8274 case GE:
8275 case GEU:
8276 cmp = flag_unsafe_math_optimizations
8277 ? gen_tstsfgt_gpr (compare_result, rs6000_compare_op0,
8278 rs6000_compare_op1)
8279 : gen_cmpsfgt_gpr (compare_result, rs6000_compare_op0,
8280 rs6000_compare_op1);
8281 break;
8282 case LT:
8283 case LTU:
8284 case UNLT:
8285 case UNLE:
8286 case LE:
8287 case LEU:
8288 cmp = flag_unsafe_math_optimizations
8289 ? gen_tstsflt_gpr (compare_result, rs6000_compare_op0,
8290 rs6000_compare_op1)
8291 : gen_cmpsflt_gpr (compare_result, rs6000_compare_op0,
8292 rs6000_compare_op1);
8293 break;
8294 default:
8295 abort ();
8296 }
8297
8298 /* Synthesize LE and GE from LT/GT || EQ. */
8299 if (code == LE || code == GE || code == LEU || code == GEU)
8300 {
8301 /* Synthesize GE/LE frome GT/LT || EQ. */
8302
8303 emit_insn (cmp);
8304
8305 switch (code)
8306 {
8307 case LE: code = LT; break;
8308 case GE: code = GT; break;
8309 case LEU: code = LT; break;
8310 case GEU: code = GT; break;
8311 default: abort ();
8312 }
8313
8314 or1 = gen_reg_rtx (SImode);
8315 or2 = gen_reg_rtx (SImode);
8316 or_result = gen_reg_rtx (CCEQmode);
8317 compare_result2 = gen_reg_rtx (CCFPmode);
8318
8319 /* Do the EQ. */
8320 cmp = flag_unsafe_math_optimizations
8321 ? gen_tstsfeq_gpr (compare_result2, rs6000_compare_op0,
8322 rs6000_compare_op1)
8323 : gen_cmpsfeq_gpr (compare_result2, rs6000_compare_op0,
8324 rs6000_compare_op1);
8325 emit_insn (cmp);
8326
8327 /* The MC8540 FP compare instructions set the CR bits
8328 differently than other PPC compare instructions. For
8329 that matter, there is no generic test instruction, but a
8330 testgt, testlt, and testeq. For a true condition, bit 2
8331 is set (x1xx) in the CR. Following the traditional CR
8332 values:
8333
8334 LT GT EQ OV
8335 bit3 bit2 bit1 bit0
8336
8337 ... bit 2 would be a GT CR alias, so later on we
8338 look in the GT bits for the branch instructins.
8339 However, we must be careful to emit correct RTL in
8340 the meantime, so optimizations don't get confused. */
8341
8342 or1 = gen_rtx (NE, SImode, compare_result, const0_rtx);
8343 or2 = gen_rtx (NE, SImode, compare_result2, const0_rtx);
8344
8345 /* OR them together. */
8346 cmp = gen_rtx_SET (VOIDmode, or_result,
8347 gen_rtx_COMPARE (CCEQmode,
8348 gen_rtx_IOR (SImode, or1, or2),
8349 const_true_rtx));
8350 compare_result = or_result;
8351 code = EQ;
8352 }
8353 else
8354 {
8355 /* We only care about 1 bit (x1xx), so map everything to NE to
8356 maintain rtl sanity. We'll get to the right bit (x1xx) at
8357 code output time. */
8358 if (code == NE || code == LTGT)
8359 /* Do the inverse here because we have no cmpne
8360 instruction. We use the cmpeq instruction and expect
8361 to get a 0 instead. */
8362 code = EQ;
8363 else
8364 code = NE;
8365 }
8366
8367 emit_insn (cmp);
8368 }
8369 else
8370 emit_insn (gen_rtx_SET (VOIDmode, compare_result,
8371 gen_rtx_COMPARE (comp_mode,
8372 rs6000_compare_op0,
8373 rs6000_compare_op1)));
39a10a29 8374
ca5adc63 8375 /* Some kinds of FP comparisons need an OR operation;
de6c5979 8376 except for flag_unsafe_math_optimizations we don't bother. */
39a10a29 8377 if (rs6000_compare_fp_p
de6c5979 8378 && ! flag_unsafe_math_optimizations
a3170dc6 8379 && ! (TARGET_HARD_FLOAT && TARGET_SPE)
39a10a29
GK		 8380 && (code == LE || code == GE
8381 || code == UNEQ || code == LTGT
8382 || code == UNGT || code == UNLT))
8383 {
8384 enum rtx_code or1, or2;
8385 rtx or1_rtx, or2_rtx, compare2_rtx;
8386 rtx or_result = gen_reg_rtx (CCEQmode);
8387
8388 switch (code)
8389 {
8390 case LE: or1 = LT; or2 = EQ; break;
8391 case GE: or1 = GT; or2 = EQ; break;
8392 case UNEQ: or1 = UNORDERED; or2 = EQ; break;
8393 case LTGT: or1 = LT; or2 = GT; break;
8394 case UNGT: or1 = UNORDERED; or2 = GT; break;
8395 case UNLT: or1 = UNORDERED; or2 = LT; break;
8396 default: abort ();
8397 }
8398 validate_condition_mode (or1, comp_mode);
8399 validate_condition_mode (or2, comp_mode);
8400 or1_rtx = gen_rtx (or1, SImode, compare_result, const0_rtx);
8401 or2_rtx = gen_rtx (or2, SImode, compare_result, const0_rtx);
8402 compare2_rtx = gen_rtx_COMPARE (CCEQmode,
8403 gen_rtx_IOR (SImode, or1_rtx, or2_rtx),
8404 const_true_rtx);
8405 emit_insn (gen_rtx_SET (VOIDmode, or_result, compare2_rtx));
8406
8407 compare_result = or_result;
8408 code = EQ;
8409 }
8410
8411 validate_condition_mode (code, GET_MODE (compare_result));
8412
8413 return gen_rtx (code, VOIDmode, compare_result, const0_rtx);
8414}
8415
8416
8417/* Emit the RTL for an sCOND pattern. */
8418
8419void
8420rs6000_emit_sCOND (code, result)
8421 enum rtx_code code;
8422 rtx result;
8423{
8424 rtx condition_rtx;
8425 enum machine_mode op_mode;
8426
8427 condition_rtx = rs6000_generate_compare (code);
8428
8429 op_mode = GET_MODE (rs6000_compare_op0);
8430 if (op_mode == VOIDmode)
8431 op_mode = GET_MODE (rs6000_compare_op1);
8432
8433 if (TARGET_POWERPC64 && (op_mode == DImode || rs6000_compare_fp_p))
8434 {
8435 PUT_MODE (condition_rtx, DImode);
8436 convert_move (result, condition_rtx, 0);
8437 }
8438 else
8439 {
8440 PUT_MODE (condition_rtx, SImode);
8441 emit_insn (gen_rtx_SET (VOIDmode, result, condition_rtx));
8442 }
8443}
8444
39a10a29
GK		 8445/* Emit a branch of kind CODE to location LOC. */
8446
8447void
8448rs6000_emit_cbranch (code, loc)
8449 enum rtx_code code;
8450 rtx loc;
8451{
8452 rtx condition_rtx, loc_ref;
8453
8454 condition_rtx = rs6000_generate_compare (code);
8455 loc_ref = gen_rtx_LABEL_REF (VOIDmode, loc);
8456 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
8457 gen_rtx_IF_THEN_ELSE (VOIDmode, condition_rtx,
8458 loc_ref, pc_rtx)));
8459}
8460
12a4e8c5
GK		 8461/* Return the string to output a conditional branch to LABEL, which is
8462 the operand number of the label, or -1 if the branch is really a
8463 conditional return.
8464
8465 OP is the conditional expression. XEXP (OP, 0) is assumed to be a
8466 condition code register and its mode specifies what kind of
8467 comparison we made.
8468
a0ab749a 8469 REVERSED is nonzero if we should reverse the sense of the comparison.
12a4e8c5
GK		 8470
8471 INSN is the insn. */
8472
8473char *
8474output_cbranch (op, label, reversed, insn)
8475 rtx op;
8476 const char * label;
8477 int reversed;
8478 rtx insn;
8479{
8480 static char string[64];
8481 enum rtx_code code = GET_CODE (op);
8482 rtx cc_reg = XEXP (op, 0);
8483 enum machine_mode mode = GET_MODE (cc_reg);
8484 int cc_regno = REGNO (cc_reg) - CR0_REGNO;
39a10a29 8485 int need_longbranch = label != NULL && get_attr_length (insn) == 8;
12a4e8c5
GK		 8486 int really_reversed = reversed ^ need_longbranch;
8487 char *s = string;
8488 const char *ccode;
8489 const char *pred;
8490 rtx note;
8491
39a10a29
GK		 8492 validate_condition_mode (code, mode);
8493
8494 /* Work out which way this really branches. We could use
8495 reverse_condition_maybe_unordered here always but this
8496 makes the resulting assembler clearer. */
12a4e8c5 8497 if (really_reversed)
de40e1df
DJ		 8498 {
8499 /* Reversal of FP compares takes care -- an ordered compare
8500 becomes an unordered compare and vice versa. */
8501 if (mode == CCFPmode)
8502 code = reverse_condition_maybe_unordered (code);
8503 else
8504 code = reverse_condition (code);
8505 }
12a4e8c5 8506
a3170dc6
AH		 8507 if ((TARGET_SPE && TARGET_HARD_FLOAT) && mode == CCFPmode)
8508 {
8509 /* The efscmp/tst* instructions twiddle bit 2, which maps nicely
8510 to the GT bit. */
8511 if (code == EQ)
8512 /* Opposite of GT. */
8513 code = UNLE;
8514 else if (code == NE)
8515 code = GT;
8516 else
8517 abort ();
8518 }
8519
39a10a29 8520 switch (code)
12a4e8c5
GK		 8521 {
8522 /* Not all of these are actually distinct opcodes, but
8523 we distinguish them for clarity of the resulting assembler. */
50a0b056
GK		 8524 case NE: case LTGT:
8525 ccode = "ne"; break;
8526 case EQ: case UNEQ:
8527 ccode = "eq"; break;
8528 case GE: case GEU:
8529 ccode = "ge"; break;
8530 case GT: case GTU: case UNGT:
8531 ccode = "gt"; break;
8532 case LE: case LEU:
8533 ccode = "le"; break;
8534 case LT: case LTU: case UNLT:
8535 ccode = "lt"; break;
12a4e8c5
GK		 8536 case UNORDERED: ccode = "un"; break;
8537 case ORDERED: ccode = "nu"; break;
8538 case UNGE: ccode = "nl"; break;
8539 case UNLE: ccode = "ng"; break;
8540 default:
a4f6c312 8541 abort ();
12a4e8c5
GK		 8542 }
8543
94a54f47
GK		 8544 /* Maybe we have a guess as to how likely the branch is.
8545 The old mnemonics don't have a way to specify this information. */
f4857b9b 8546 pred = "";
12a4e8c5
GK		 8547 note = find_reg_note (insn, REG_BR_PROB, NULL_RTX);
8548 if (note != NULL_RTX)
8549 {
8550 /* PROB is the difference from 50%. */
8551 int prob = INTVAL (XEXP (note, 0)) - REG_BR_PROB_BASE / 2;
f4857b9b
AM		 8552 bool always_hint = rs6000_cpu != PROCESSOR_POWER4;
8553
8554 /* Only hint for highly probable/improbable branches on newer
8555 cpus as static prediction overrides processor dynamic
8556 prediction. For older cpus we may as well always hint, but
8557 assume not taken for branches that are very close to 50% as a
8558 mispredicted taken branch is more expensive than a
8559 mispredicted not-taken branch. */
8560 if (always_hint
8561 || abs (prob) > REG_BR_PROB_BASE / 100 * 48)
8562 {
8563 if (abs (prob) > REG_BR_PROB_BASE / 20
8564 && ((prob > 0) ^ need_longbranch))
8565 pred = "+";
8566 else
8567 pred = "-";
8568 }
12a4e8c5 8569 }
12a4e8c5
GK		 8570
8571 if (label == NULL)
94a54f47 8572 s += sprintf (s, "{b%sr|b%slr%s} ", ccode, ccode, pred);
12a4e8c5 8573 else
94a54f47 8574 s += sprintf (s, "{b%s|b%s%s} ", ccode, ccode, pred);
12a4e8c5 8575
37c67319
GK		 8576 /* We need to escape any '%' characters in the reg_names string.
8577 Assume they'd only be the first character... */
8578 if (reg_names[cc_regno + CR0_REGNO][0] == '%')
8579 *s++ = '%';
94a54f47 8580 s += sprintf (s, "%s", reg_names[cc_regno + CR0_REGNO]);
12a4e8c5
GK		 8581
8582 if (label != NULL)
8583 {
8584 /* If the branch distance was too far, we may have to use an
8585 unconditional branch to go the distance. */
8586 if (need_longbranch)
44518ddd 8587 s += sprintf (s, ",$+8\n\tb %s", label);
12a4e8c5
GK		 8588 else
8589 s += sprintf (s, ",%s", label);
8590 }
8591
8592 return string;
8593}
50a0b056
GK		 8594
8595/* Emit a conditional move: move TRUE_COND to DEST if OP of the
8596 operands of the last comparison is nonzero/true, FALSE_COND if it
8597 is zero/false. Return 0 if the hardware has no such operation. */
a4f6c312 8598
50a0b056
GK		 8599int
8600rs6000_emit_cmove (dest, op, true_cond, false_cond)
8601 rtx dest;
8602 rtx op;
8603 rtx true_cond;
8604 rtx false_cond;
8605{
8606 enum rtx_code code = GET_CODE (op);
8607 rtx op0 = rs6000_compare_op0;
8608 rtx op1 = rs6000_compare_op1;
8609 REAL_VALUE_TYPE c1;
3148ad6d
DJ		 8610 enum machine_mode compare_mode = GET_MODE (op0);
8611 enum machine_mode result_mode = GET_MODE (dest);
50a0b056
GK		 8612 rtx temp;
8613
3148ad6d 8614 /* These modes should always match. */
a3170dc6
AH		 8615 if (GET_MODE (op1) != compare_mode
8616 /* In the isel case however, we can use a compare immediate, so
8617 op1 may be a small constant. */
8618 && (!TARGET_ISEL || !short_cint_operand (op1, VOIDmode)))
3148ad6d 8619 return 0;
178c3eff 8620 if (GET_MODE (true_cond) != result_mode)
3148ad6d 8621 return 0;
178c3eff 8622 if (GET_MODE (false_cond) != result_mode)
3148ad6d
DJ		 8623 return 0;
8624
50a0b056
GK		 8625 /* First, work out if the hardware can do this at all, or
8626 if it's too slow... */
50a0b056 8627 if (! rs6000_compare_fp_p)
a3170dc6
AH		 8628 {
8629 if (TARGET_ISEL)
8630 return rs6000_emit_int_cmove (dest, op, true_cond, false_cond);
8631 return 0;
8632 }
50a0b056
GK		 8633
8634 /* Eliminate half of the comparisons by switching operands, this
8635 makes the remaining code simpler. */
8636 if (code == UNLT || code == UNGT || code == UNORDERED || code == NE
8637 || code == LTGT || code == LT)
8638 {
8639 code = reverse_condition_maybe_unordered (code);
8640 temp = true_cond;
8641 true_cond = false_cond;
8642 false_cond = temp;
8643 }
8644
8645 /* UNEQ and LTGT take four instructions for a comparison with zero,
8646 it'll probably be faster to use a branch here too. */
8647 if (code == UNEQ)
8648 return 0;
8649
8650 if (GET_CODE (op1) == CONST_DOUBLE)
8651 REAL_VALUE_FROM_CONST_DOUBLE (c1, op1);
8652
8653 /* We're going to try to implement comparions by performing
8654 a subtract, then comparing against zero. Unfortunately,
8655 Inf - Inf is NaN which is not zero, and so if we don't
27d30956 8656 know that the operand is finite and the comparison
50a0b056
GK		 8657 would treat EQ different to UNORDERED, we can't do it. */
8658 if (! flag_unsafe_math_optimizations
8659 && code != GT && code != UNGE
045572c7 8660 && (GET_CODE (op1) != CONST_DOUBLE || real_isinf (&c1))
50a0b056
GK		 8661 /* Constructs of the form (a OP b ? a : b) are safe. */
8662 && ((! rtx_equal_p (op0, false_cond) && ! rtx_equal_p (op1, false_cond))
8663 || (! rtx_equal_p (op0, true_cond)
8664 && ! rtx_equal_p (op1, true_cond))))
8665 return 0;
8666 /* At this point we know we can use fsel. */
8667
8668 /* Reduce the comparison to a comparison against zero. */
3148ad6d 8669 temp = gen_reg_rtx (compare_mode);
50a0b056 8670 emit_insn (gen_rtx_SET (VOIDmode, temp,
3148ad6d 8671 gen_rtx_MINUS (compare_mode, op0, op1)));
50a0b056 8672 op0 = temp;
3148ad6d 8673 op1 = CONST0_RTX (compare_mode);
50a0b056
GK		 8674
8675 /* If we don't care about NaNs we can reduce some of the comparisons
8676 down to faster ones. */
8677 if (flag_unsafe_math_optimizations)
8678 switch (code)
8679 {
8680 case GT:
8681 code = LE;
8682 temp = true_cond;
8683 true_cond = false_cond;
8684 false_cond = temp;
8685 break;
8686 case UNGE:
8687 code = GE;
8688 break;
8689 case UNEQ:
8690 code = EQ;
8691 break;
8692 default:
8693 break;
8694 }
8695
8696 /* Now, reduce everything down to a GE. */
8697 switch (code)
8698 {
8699 case GE:
8700 break;
8701
8702 case LE:
3148ad6d
DJ		 8703 temp = gen_reg_rtx (compare_mode);
8704 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
50a0b056
GK		 8705 op0 = temp;
8706 break;
8707
8708 case ORDERED:
3148ad6d
DJ		 8709 temp = gen_reg_rtx (compare_mode);
8710 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_ABS (compare_mode, op0)));
50a0b056
GK		 8711 op0 = temp;
8712 break;
8713
8714 case EQ:
3148ad6d 8715 temp = gen_reg_rtx (compare_mode);
50a0b056 8716 emit_insn (gen_rtx_SET (VOIDmode, temp,
3148ad6d
DJ		 8717 gen_rtx_NEG (compare_mode,
8718 gen_rtx_ABS (compare_mode, op0))));
50a0b056
GK		 8719 op0 = temp;
8720 break;
8721
8722 case UNGE:
3148ad6d 8723 temp = gen_reg_rtx (result_mode);
50a0b056 8724 emit_insn (gen_rtx_SET (VOIDmode, temp,
3148ad6d 8725 gen_rtx_IF_THEN_ELSE (result_mode,
50a0b056
GK		 8726 gen_rtx_GE (VOIDmode,
8727 op0, op1),
8728 true_cond, false_cond)));
8729 false_cond = temp;
8730 true_cond = false_cond;
8731
3148ad6d
DJ		 8732 temp = gen_reg_rtx (compare_mode);
8733 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
50a0b056
GK		 8734 op0 = temp;
8735 break;
8736
8737 case GT:
3148ad6d 8738 temp = gen_reg_rtx (result_mode);
50a0b056 8739 emit_insn (gen_rtx_SET (VOIDmode, temp,
3148ad6d 8740 gen_rtx_IF_THEN_ELSE (result_mode,
50a0b056
GK		 8741 gen_rtx_GE (VOIDmode,
8742 op0, op1),
8743 true_cond, false_cond)));
8744 true_cond = temp;
8745 false_cond = true_cond;
8746
3148ad6d
DJ		 8747 temp = gen_reg_rtx (compare_mode);
8748 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
50a0b056
GK		 8749 op0 = temp;
8750 break;
8751
8752 default:
8753 abort ();
8754 }
8755
8756 emit_insn (gen_rtx_SET (VOIDmode, dest,
3148ad6d 8757 gen_rtx_IF_THEN_ELSE (result_mode,
50a0b056
GK		 8758 gen_rtx_GE (VOIDmode,
8759 op0, op1),
8760 true_cond, false_cond)));
8761 return 1;
8762}
8763
a3170dc6
AH		 8764/* Same as above, but for ints (isel). */
8765
8766static int
8767rs6000_emit_int_cmove (dest, op, true_cond, false_cond)
8768 rtx dest;
8769 rtx op;
8770 rtx true_cond;
8771 rtx false_cond;
8772{
8773 rtx condition_rtx, cr;
8774
8775 /* All isel implementations thus far are 32-bits. */
8776 if (GET_MODE (rs6000_compare_op0) != SImode)
8777 return 0;
8778
8779 /* We still have to do the compare, because isel doesn't do a
8780 compare, it just looks at the CRx bits set by a previous compare
8781 instruction. */
8782 condition_rtx = rs6000_generate_compare (GET_CODE (op));
8783 cr = XEXP (condition_rtx, 0);
8784
8785 if (GET_MODE (cr) == CCmode)
8786 emit_insn (gen_isel_signed (dest, condition_rtx,
8787 true_cond, false_cond, cr));
8788 else
8789 emit_insn (gen_isel_unsigned (dest, condition_rtx,
8790 true_cond, false_cond, cr));
8791
8792 return 1;
8793}
8794
8795const char *
8796output_isel (operands)
8797 rtx *operands;
8798{
8799 enum rtx_code code;
8800
8801 code = GET_CODE (operands[1]);
8802 if (code == GE || code == GEU || code == LE || code == LEU || code == NE)
8803 {
8804 PUT_CODE (operands[1], reverse_condition (code));
8805 return "isel %0,%3,%2,%j1";
8806 }
8807 else
8808 return "isel %0,%2,%3,%j1";
8809}
8810
50a0b056
GK		 8811void
8812rs6000_emit_minmax (dest, code, op0, op1)
8813 rtx dest;
8814 enum rtx_code code;
8815 rtx op0;
8816 rtx op1;
8817{
8818 enum machine_mode mode = GET_MODE (op0);
5dc8d536 8819 enum rtx_code c;
50a0b056 8820 rtx target;
5dc8d536
AH		 8821
8822 if (code == SMAX || code == SMIN)
8823 c = GE;
8824 else
8825 c = GEU;
8826
50a0b056 8827 if (code == SMAX || code == UMAX)
5dc8d536 8828 target = emit_conditional_move (dest, c, op0, op1, mode,
50a0b056
GK		 8829 op0, op1, mode, 0);
8830 else
5dc8d536 8831 target = emit_conditional_move (dest, c, op0, op1, mode,
50a0b056
GK		 8832 op1, op0, mode, 0);
8833 if (target == NULL_RTX)
8834 abort ();
8835 if (target != dest)
8836 emit_move_insn (dest, target);
8837}
12a4e8c5 8838\f
a4f6c312
SS		 8839/* This page contains routines that are used to determine what the
8840 function prologue and epilogue code will do and write them out. */
9878760c 8841
a4f6c312
SS		 8842/* Return the first fixed-point register that is required to be
8843 saved. 32 if none. */
9878760c
RK		 8844
8845int
8846first_reg_to_save ()
8847{
8848 int first_reg;
8849
8850 /* Find lowest numbered live register. */
8851 for (first_reg = 13; first_reg <= 31; first_reg++)
a38d360d
GK		 8852 if (regs_ever_live[first_reg]
8853 && (! call_used_regs[first_reg]
1db02437 8854 || (first_reg == RS6000_PIC_OFFSET_TABLE_REGNUM
f607bc57
ZW		 8855 && ((DEFAULT_ABI == ABI_V4 && flag_pic == 1)
8856 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)))))
9878760c
RK		 8857 break;
8858
ee890fe2 8859#if TARGET_MACHO
93638d7a
AM		 8860 if (flag_pic
8861 && current_function_uses_pic_offset_table
8862 && first_reg > RS6000_PIC_OFFSET_TABLE_REGNUM)
1db02437 8863 return RS6000_PIC_OFFSET_TABLE_REGNUM;
ee890fe2
SS		 8864#endif
8865
9878760c
RK		 8866 return first_reg;
8867}
8868
8869/* Similar, for FP regs. */
8870
8871int
8872first_fp_reg_to_save ()
8873{
8874 int first_reg;
8875
8876 /* Find lowest numbered live register. */
8877 for (first_reg = 14 + 32; first_reg <= 63; first_reg++)
8878 if (regs_ever_live[first_reg])
8879 break;
8880
8881 return first_reg;
8882}
00b960c7
AH		 8883
8884/* Similar, for AltiVec regs. */
8885
8886static int
8887first_altivec_reg_to_save ()
8888{
8889 int i;
8890
8891 /* Stack frame remains as is unless we are in AltiVec ABI. */
8892 if (! TARGET_ALTIVEC_ABI)
8893 return LAST_ALTIVEC_REGNO + 1;
8894
8895 /* Find lowest numbered live register. */
8896 for (i = FIRST_ALTIVEC_REGNO + 20; i <= LAST_ALTIVEC_REGNO; ++i)
8897 if (regs_ever_live[i])
8898 break;
8899
8900 return i;
8901}
8902
8903/* Return a 32-bit mask of the AltiVec registers we need to set in
8904 VRSAVE. Bit n of the return value is 1 if Vn is live. The MSB in
8905 the 32-bit word is 0. */
8906
8907static unsigned int
8908compute_vrsave_mask ()
8909{
8910 unsigned int i, mask = 0;
8911
8912 /* First, find out if we use _any_ altivec registers. */
8913 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
8914 if (regs_ever_live[i])
8915 mask |= ALTIVEC_REG_BIT (i);
8916
8917 if (mask == 0)
8918 return mask;
8919
8920 /* Next, add all registers that are call-clobbered. We do this
8921 because post-reload register optimizers such as regrename_optimize
8922 may choose to use them. They never change the register class
8923 chosen by reload, so cannot create new uses of altivec registers
8924 if there were none before, so the early exit above is safe. */
8925 /* ??? Alternately, we could define HARD_REGNO_RENAME_OK to disallow
8926 altivec registers not saved in the mask, which might well make the
8927 adjustments below more effective in eliding the save/restore of
8928 VRSAVE in small functions. */
8929 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
8930 if (call_used_regs[i])
8931 mask |= ALTIVEC_REG_BIT (i);
8932
8933 /* Next, remove the argument registers from the set. These must
8934 be in the VRSAVE mask set by the caller, so we don't need to add
8935 them in again. More importantly, the mask we compute here is
8936 used to generate CLOBBERs in the set_vrsave insn, and we do not
8937 wish the argument registers to die. */
8938 for (i = cfun->args_info.vregno; i >= ALTIVEC_ARG_MIN_REG; --i)
8939 mask &= ~ALTIVEC_REG_BIT (i);
8940
8941 /* Similarly, remove the return value from the set. */
8942 {
8943 bool yes = false;
8944 diddle_return_value (is_altivec_return_reg, &yes);
8945 if (yes)
8946 mask &= ~ALTIVEC_REG_BIT (ALTIVEC_ARG_RETURN);
8947 }
8948
8949 return mask;
8950}
8951
8952static void
8953is_altivec_return_reg (reg, xyes)
8954 rtx reg;
8955 void *xyes;
8956{
8957 bool *yes = (bool *) xyes;
8958 if (REGNO (reg) == ALTIVEC_ARG_RETURN)
8959 *yes = true;
8960}
8961
4697a36c
MM		 8962\f
8963/* Calculate the stack information for the current function. This is
8964 complicated by having two separate calling sequences, the AIX calling
8965 sequence and the V.4 calling sequence.
8966
592696dd 8967 AIX (and Darwin/Mac OS X) stack frames look like:
a260abc9 8968 32-bit 64-bit
4697a36c 8969 SP----> +---------------------------------------+
a260abc9 8970 | back chain to caller | 0 0
4697a36c 8971 +---------------------------------------+
a260abc9 8972 | saved CR | 4 8 (8-11)
4697a36c 8973 +---------------------------------------+
a260abc9 8974 | saved LR | 8 16
4697a36c 8975 +---------------------------------------+
a260abc9 8976 | reserved for compilers | 12 24
4697a36c 8977 +---------------------------------------+
a260abc9 8978 | reserved for binders | 16 32
4697a36c 8979 +---------------------------------------+
a260abc9 8980 | saved TOC pointer | 20 40
4697a36c 8981 +---------------------------------------+
a260abc9 8982 | Parameter save area (P) | 24 48
4697a36c 8983 +---------------------------------------+
a260abc9 8984 | Alloca space (A) | 24+P etc.
802a0058 8985 +---------------------------------------+
a7df97e6 8986 | Local variable space (L) | 24+P+A
4697a36c 8987 +---------------------------------------+
a7df97e6 8988 | Float/int conversion temporary (X) | 24+P+A+L
4697a36c 8989 +---------------------------------------+
00b960c7
AH		 8990 | Save area for AltiVec registers (W) | 24+P+A+L+X
8991 +---------------------------------------+
8992 | AltiVec alignment padding (Y) | 24+P+A+L+X+W
8993 +---------------------------------------+
8994 | Save area for VRSAVE register (Z) | 24+P+A+L+X+W+Y
4697a36c 8995 +---------------------------------------+
00b960c7
AH		 8996 | Save area for GP registers (G) | 24+P+A+X+L+X+W+Y+Z
8997 +---------------------------------------+
8998 | Save area for FP registers (F) | 24+P+A+X+L+X+W+Y+Z+G
4697a36c
MM		 8999 +---------------------------------------+
9000 old SP->| back chain to caller's caller |
9001 +---------------------------------------+
9002
5376a30c
KR		 9003 The required alignment for AIX configurations is two words (i.e., 8
9004 or 16 bytes).
9005
9006
4697a36c
MM		 9007 V.4 stack frames look like:
9008
9009 SP----> +---------------------------------------+
9010 | back chain to caller | 0
9011 +---------------------------------------+
5eb387b8 9012 | caller's saved LR | 4
4697a36c
MM		 9013 +---------------------------------------+
9014 | Parameter save area (P) | 8
9015 +---------------------------------------+
a7df97e6
MM		 9016 | Alloca space (A) | 8+P
9017 +---------------------------------------+
9018 | Varargs save area (V) | 8+P+A
9019 +---------------------------------------+
9020 | Local variable space (L) | 8+P+A+V
9021 +---------------------------------------+
9022 | Float/int conversion temporary (X) | 8+P+A+V+L
4697a36c 9023 +---------------------------------------+
00b960c7
AH		 9024 | Save area for AltiVec registers (W) | 8+P+A+V+L+X
9025 +---------------------------------------+
9026 | AltiVec alignment padding (Y) | 8+P+A+V+L+X+W
9027 +---------------------------------------+
9028 | Save area for VRSAVE register (Z) | 8+P+A+V+L+X+W+Y
9029 +---------------------------------------+
a3170dc6
AH		 9030 | SPE: area for 64-bit GP registers |
9031 +---------------------------------------+
9032 | SPE alignment padding |
9033 +---------------------------------------+
00b960c7 9034 | saved CR (C) | 8+P+A+V+L+X+W+Y+Z
a7df97e6 9035 +---------------------------------------+
00b960c7 9036 | Save area for GP registers (G) | 8+P+A+V+L+X+W+Y+Z+C
a7df97e6 9037 +---------------------------------------+
00b960c7 9038 | Save area for FP registers (F) | 8+P+A+V+L+X+W+Y+Z+C+G
4697a36c
MM		 9039 +---------------------------------------+
9040 old SP->| back chain to caller's caller |
9041 +---------------------------------------+
b6c9286a 9042
5376a30c
KR		 9043 The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is
9044 given. (But note below and in sysv4.h that we require only 8 and
9045 may round up the size of our stack frame anyways. The historical
9046 reason is early versions of powerpc-linux which didn't properly
9047 align the stack at program startup. A happy side-effect is that
9048 -mno-eabi libraries can be used with -meabi programs.)
9049
5376a30c
KR		 9050 The EABI configuration defaults to the V.4 layout, unless
9051 -mcall-aix is used, in which case the AIX layout is used. However,
9052 the stack alignment requirements may differ. If -mno-eabi is not
9053 given, the required stack alignment is 8 bytes; if -mno-eabi is
9054 given, the required alignment is 16 bytes. (But see V.4 comment
9055 above.) */
4697a36c 9056
61b2fbe7
MM		 9057#ifndef ABI_STACK_BOUNDARY
9058#define ABI_STACK_BOUNDARY STACK_BOUNDARY
9059#endif
9060
4697a36c
MM		 9061rs6000_stack_t *
9062rs6000_stack_info ()
9063{
9064 static rs6000_stack_t info, zero_info;
9065 rs6000_stack_t *info_ptr = &info;
9ebbca7d 9066 int reg_size = TARGET_POWERPC64 ? 8 : 4;
24d304eb 9067 enum rs6000_abi abi;
83720594 9068 int ehrd_size;
b6c9286a 9069 int total_raw_size;
4697a36c 9070
a4f6c312 9071 /* Zero all fields portably. */
4697a36c
MM		 9072 info = zero_info;
9073
a4f6c312 9074 /* Select which calling sequence. */
b6c9286a 9075 info_ptr->abi = abi = DEFAULT_ABI;
9878760c 9076
a4f6c312 9077 /* Calculate which registers need to be saved & save area size. */
4697a36c 9078 info_ptr->first_gp_reg_save = first_reg_to_save ();
1db02437 9079 /* Assume that we will have to save RS6000_PIC_OFFSET_TABLE_REGNUM,
906fb125 9080 even if it currently looks like we won't. */
2bfcf297 9081 if (((TARGET_TOC && TARGET_MINIMAL_TOC)
f607bc57
ZW		 9082 || (flag_pic == 1 && abi == ABI_V4)
9083 || (flag_pic && abi == ABI_DARWIN))
1db02437
FS		 9084 && info_ptr->first_gp_reg_save > RS6000_PIC_OFFSET_TABLE_REGNUM)
9085 info_ptr->gp_size = reg_size * (32 - RS6000_PIC_OFFSET_TABLE_REGNUM);
906fb125
GK		 9086 else
9087 info_ptr->gp_size = reg_size * (32 - info_ptr->first_gp_reg_save);
4697a36c 9088
a3170dc6
AH		 9089 /* For the SPE, we have an additional upper 32-bits on each GPR.
9090 Ideally we should save the entire 64-bits only when the upper
9091 half is used in SIMD instructions. Since we only record
9092 registers live (not the size they are used in), this proves
9093 difficult because we'd have to traverse the instruction chain at
9094 the right time, taking reload into account. This is a real pain,
9095 so we opt to save the GPRs in 64-bits always. Anyone overly
9096 concerned with frame size can fix this. ;-).
9097
9098 So... since we save all GPRs (except the SP) in 64-bits, the
9099 traditional GP save area will be empty. */
9100 if (TARGET_SPE_ABI)
9101 info_ptr->gp_size = 0;
9102
4697a36c
MM		 9103 info_ptr->first_fp_reg_save = first_fp_reg_to_save ();
9104 info_ptr->fp_size = 8 * (64 - info_ptr->first_fp_reg_save);
9105
00b960c7
AH		 9106 info_ptr->first_altivec_reg_save = first_altivec_reg_to_save ();
9107 info_ptr->altivec_size = 16 * (LAST_ALTIVEC_REGNO + 1
9108 - info_ptr->first_altivec_reg_save);
9109
592696dd 9110 /* Does this function call anything? */
71f123ca
FS		 9111 info_ptr->calls_p = (! current_function_is_leaf
9112 || cfun->machine->ra_needs_full_frame);
b6c9286a 9113
a4f6c312 9114 /* Determine if we need to save the link register. */
71f123ca 9115 if (rs6000_ra_ever_killed ()
70f4f91c 9116 || (DEFAULT_ABI == ABI_AIX && current_function_profile)
4697a36c
MM		 9117#ifdef TARGET_RELOCATABLE
9118 || (TARGET_RELOCATABLE && (get_pool_size () != 0))
9119#endif
9120 || (info_ptr->first_fp_reg_save != 64
9121 && !FP_SAVE_INLINE (info_ptr->first_fp_reg_save))
00b960c7 9122 || info_ptr->first_altivec_reg_save <= LAST_ALTIVEC_REGNO
24d304eb 9123 || (abi == ABI_V4 && current_function_calls_alloca)
a4f6c312
SS		 9124 || (DEFAULT_ABI == ABI_DARWIN
9125 && flag_pic
9126 && current_function_uses_pic_offset_table)
4697a36c
MM		 9127 || info_ptr->calls_p)
9128 {
9129 info_ptr->lr_save_p = 1;
9ebbca7d 9130 regs_ever_live[LINK_REGISTER_REGNUM] = 1;
4697a36c
MM		 9131 }
9132
9ebbca7d
GK		 9133 /* Determine if we need to save the condition code registers. */
9134 if (regs_ever_live[CR2_REGNO]
9135 || regs_ever_live[CR3_REGNO]
9136 || regs_ever_live[CR4_REGNO])
4697a36c
MM		 9137 {
9138 info_ptr->cr_save_p = 1;
f607bc57 9139 if (abi == ABI_V4)
4697a36c
MM		 9140 info_ptr->cr_size = reg_size;
9141 }
9142
83720594
RH		 9143 /* If the current function calls __builtin_eh_return, then we need
9144 to allocate stack space for registers that will hold data for
9145 the exception handler. */
9146 if (current_function_calls_eh_return)
9147 {
9148 unsigned int i;
9149 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i)
9150 continue;
a3170dc6
AH		 9151
9152 /* SPE saves EH registers in 64-bits. */
9153 ehrd_size = i * (TARGET_SPE_ABI ? UNITS_PER_SPE_WORD : UNITS_PER_WORD);
83720594
RH		 9154 }
9155 else
9156 ehrd_size = 0;
9157
592696dd 9158 /* Determine various sizes. */
4697a36c
MM		 9159 info_ptr->reg_size = reg_size;
9160 info_ptr->fixed_size = RS6000_SAVE_AREA;
9161 info_ptr->varargs_size = RS6000_VARARGS_AREA;
189e03e3 9162 info_ptr->vars_size = RS6000_ALIGN (get_frame_size (), 8);
a4f6c312
SS		 9163 info_ptr->parm_size = RS6000_ALIGN (current_function_outgoing_args_size,
9164 8);
00b960c7 9165
a3170dc6
AH		 9166 if (TARGET_SPE_ABI)
9167 info_ptr->spe_gp_size = 8 * (32 - info_ptr->first_gp_reg_save);
9168 else
9169 info_ptr->spe_gp_size = 0;
9170
08b57fb3 9171 if (TARGET_ALTIVEC_ABI && TARGET_ALTIVEC_VRSAVE)
00b960c7
AH		 9172 {
9173 info_ptr->vrsave_mask = compute_vrsave_mask ();
9174 info_ptr->vrsave_size = info_ptr->vrsave_mask ? 4 : 0;
9175 }
9176 else
9177 {
9178 info_ptr->vrsave_mask = 0;
9179 info_ptr->vrsave_size = 0;
9180 }
b6c9286a 9181
592696dd 9182 /* Calculate the offsets. */
24d304eb 9183 switch (abi)
4697a36c 9184 {
b6c9286a 9185 case ABI_NONE:
24d304eb 9186 default:
b6c9286a
MM		 9187 abort ();
9188
9189 case ABI_AIX:
9190 case ABI_AIX_NODESC:
ee890fe2 9191 case ABI_DARWIN:
b6c9286a
MM		 9192 info_ptr->fp_save_offset = - info_ptr->fp_size;
9193 info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size;
00b960c7
AH		 9194
9195 if (TARGET_ALTIVEC_ABI)
9196 {
9197 info_ptr->vrsave_save_offset
9198 = info_ptr->gp_save_offset - info_ptr->vrsave_size;
9199
9200 /* Align stack so vector save area is on a quadword boundary. */
9201 if (info_ptr->altivec_size != 0)
9202 info_ptr->altivec_padding_size
9203 = 16 - (-info_ptr->vrsave_save_offset % 16);
9204 else
9205 info_ptr->altivec_padding_size = 0;
9206
9207 info_ptr->altivec_save_offset
9208 = info_ptr->vrsave_save_offset
9209 - info_ptr->altivec_padding_size
9210 - info_ptr->altivec_size;
9211
9212 /* Adjust for AltiVec case. */
9213 info_ptr->ehrd_offset = info_ptr->altivec_save_offset - ehrd_size;
9214 }
9215 else
9216 info_ptr->ehrd_offset = info_ptr->gp_save_offset - ehrd_size;
a260abc9
DE		 9217 info_ptr->cr_save_offset = reg_size; /* first word when 64-bit. */
9218 info_ptr->lr_save_offset = 2*reg_size;
24d304eb
RK		 9219 break;
9220
9221 case ABI_V4:
b6c9286a
MM		 9222 info_ptr->fp_save_offset = - info_ptr->fp_size;
9223 info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size;
a7df97e6 9224 info_ptr->cr_save_offset = info_ptr->gp_save_offset - info_ptr->cr_size;
00b960c7 9225
a3170dc6
AH		 9226 if (TARGET_SPE_ABI)
9227 {
9228 /* Align stack so SPE GPR save area is aligned on a
9229 double-word boundary. */
9230 if (info_ptr->spe_gp_size != 0)
9231 info_ptr->spe_padding_size
9232 = 8 - (-info_ptr->cr_save_offset % 8);
9233 else
9234 info_ptr->spe_padding_size = 0;
9235
9236 info_ptr->spe_gp_save_offset
9237 = info_ptr->cr_save_offset
9238 - info_ptr->spe_padding_size
9239 - info_ptr->spe_gp_size;
9240
9241 /* Adjust for SPE case. */
9242 info_ptr->toc_save_offset
9243 = info_ptr->spe_gp_save_offset - info_ptr->toc_size;
9244 }
9245 else if (TARGET_ALTIVEC_ABI)
00b960c7
AH		 9246 {
9247 info_ptr->vrsave_save_offset
9248 = info_ptr->cr_save_offset - info_ptr->vrsave_size;
9249
9250 /* Align stack so vector save area is on a quadword boundary. */
9251 if (info_ptr->altivec_size != 0)
9252 info_ptr->altivec_padding_size
9253 = 16 - (-info_ptr->vrsave_save_offset % 16);
9254 else
9255 info_ptr->altivec_padding_size = 0;
9256
9257 info_ptr->altivec_save_offset
9258 = info_ptr->vrsave_save_offset
9259 - info_ptr->altivec_padding_size
9260 - info_ptr->altivec_size;
9261
9262 /* Adjust for AltiVec case. */
9263 info_ptr->toc_save_offset
9264 = info_ptr->altivec_save_offset - info_ptr->toc_size;
9265 }
9266 else
9267 info_ptr->toc_save_offset = info_ptr->cr_save_offset - info_ptr->toc_size;
83720594 9268 info_ptr->ehrd_offset = info_ptr->toc_save_offset - ehrd_size;
b6c9286a
MM		 9269 info_ptr->lr_save_offset = reg_size;
9270 break;
4697a36c
MM		 9271 }
9272
00b960c7
AH		 9273 info_ptr->save_size = RS6000_ALIGN (info_ptr->fp_size
9274 + info_ptr->gp_size
9275 + info_ptr->altivec_size
9276 + info_ptr->altivec_padding_size
9277 + info_ptr->vrsave_size
a3170dc6
AH		 9278 + info_ptr->spe_gp_size
9279 + info_ptr->spe_padding_size
00b960c7
AH		 9280 + ehrd_size
9281 + info_ptr->cr_size
9282 + info_ptr->lr_size
9283 + info_ptr->vrsave_size
9284 + info_ptr->toc_size,
9285 (TARGET_ALTIVEC_ABI || ABI_DARWIN)
9286 ? 16 : 8);
9287
ff381587
MM		 9288 total_raw_size = (info_ptr->vars_size
9289 + info_ptr->parm_size
ff381587
MM		 9290 + info_ptr->save_size
9291 + info_ptr->varargs_size
9292 + info_ptr->fixed_size);
9293
a4f6c312
SS		 9294 info_ptr->total_size =
9295 RS6000_ALIGN (total_raw_size, ABI_STACK_BOUNDARY / BITS_PER_UNIT);
ff381587
MM		 9296
9297 /* Determine if we need to allocate any stack frame:
9298
a4f6c312
SS		 9299 For AIX we need to push the stack if a frame pointer is needed
9300 (because the stack might be dynamically adjusted), if we are
9301 debugging, if we make calls, or if the sum of fp_save, gp_save,
9302 and local variables are more than the space needed to save all
9303 non-volatile registers: 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8
9304 + 18*8 = 288 (GPR13 reserved).
ff381587 9305
a4f6c312
SS		 9306 For V.4 we don't have the stack cushion that AIX uses, but assume
9307 that the debugger can handle stackless frames. */
ff381587
MM		 9308
9309 if (info_ptr->calls_p)
9310 info_ptr->push_p = 1;
9311
f607bc57 9312 else if (abi == ABI_V4)
e72247f4 9313 info_ptr->push_p = total_raw_size > info_ptr->fixed_size;
ff381587
MM		 9314
9315 else
9316 info_ptr->push_p = (frame_pointer_needed
ee890fe2 9317 || (abi != ABI_DARWIN && write_symbols != NO_DEBUG)
ff381587 9318 || ((total_raw_size - info_ptr->fixed_size)
bfc79d3b 9319 > (TARGET_32BIT ? 220 : 288)));
ff381587 9320
a4f6c312 9321 /* Zero offsets if we're not saving those registers. */
8dda1a21 9322 if (info_ptr->fp_size == 0)
4697a36c
MM		 9323 info_ptr->fp_save_offset = 0;
9324
8dda1a21 9325 if (info_ptr->gp_size == 0)
4697a36c
MM		 9326 info_ptr->gp_save_offset = 0;
9327
00b960c7
AH		 9328 if (! TARGET_ALTIVEC_ABI || info_ptr->altivec_size == 0)
9329 info_ptr->altivec_save_offset = 0;
9330
9331 if (! TARGET_ALTIVEC_ABI || info_ptr->vrsave_mask == 0)
9332 info_ptr->vrsave_save_offset = 0;
9333
a3170dc6
AH		 9334 if (! TARGET_SPE_ABI || info_ptr->spe_gp_size == 0)
9335 info_ptr->spe_gp_save_offset = 0;
9336
c81fc13e 9337 if (! info_ptr->lr_save_p)
4697a36c
MM		 9338 info_ptr->lr_save_offset = 0;
9339
c81fc13e 9340 if (! info_ptr->cr_save_p)
4697a36c
MM		 9341 info_ptr->cr_save_offset = 0;
9342
c81fc13e 9343 if (! info_ptr->toc_save_p)
b6c9286a
MM		 9344 info_ptr->toc_save_offset = 0;
9345
4697a36c
MM		 9346 return info_ptr;
9347}
9348
9349void
9350debug_stack_info (info)
9351 rs6000_stack_t *info;
9878760c 9352{
d330fd93 9353 const char *abi_string;
24d304eb 9354
c81fc13e 9355 if (! info)
4697a36c
MM		 9356 info = rs6000_stack_info ();
9357
9358 fprintf (stderr, "\nStack information for function %s:\n",
9359 ((current_function_decl && DECL_NAME (current_function_decl))
9360 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl))
9361 : "<unknown>"));
9362
24d304eb
RK		 9363 switch (info->abi)
9364 {
b6c9286a
MM		 9365 default: abi_string = "Unknown"; break;
9366 case ABI_NONE: abi_string = "NONE"; break;
f607bc57 9367 case ABI_AIX:
b6c9286a 9368 case ABI_AIX_NODESC: abi_string = "AIX"; break;
ee890fe2 9369 case ABI_DARWIN: abi_string = "Darwin"; break;
b6c9286a 9370 case ABI_V4: abi_string = "V.4"; break;
24d304eb
RK		 9371 }
9372
9373 fprintf (stderr, "\tABI = %5s\n", abi_string);
9374
00b960c7
AH		 9375 if (TARGET_ALTIVEC_ABI)
9376 fprintf (stderr, "\tALTIVEC ABI extensions enabled.\n");
9377
a3170dc6
AH		 9378 if (TARGET_SPE_ABI)
9379 fprintf (stderr, "\tSPE ABI extensions enabled.\n");
9380
4697a36c
MM		 9381 if (info->first_gp_reg_save != 32)
9382 fprintf (stderr, "\tfirst_gp_reg_save = %5d\n", info->first_gp_reg_save);
9383
9384 if (info->first_fp_reg_save != 64)
9385 fprintf (stderr, "\tfirst_fp_reg_save = %5d\n", info->first_fp_reg_save);
9878760c 9386
00b960c7
AH		 9387 if (info->first_altivec_reg_save <= LAST_ALTIVEC_REGNO)
9388 fprintf (stderr, "\tfirst_altivec_reg_save = %5d\n",
9389 info->first_altivec_reg_save);
9390
4697a36c
MM		 9391 if (info->lr_save_p)
9392 fprintf (stderr, "\tlr_save_p = %5d\n", info->lr_save_p);
9878760c 9393
4697a36c
MM		 9394 if (info->cr_save_p)
9395 fprintf (stderr, "\tcr_save_p = %5d\n", info->cr_save_p);
9396
b6c9286a
MM		 9397 if (info->toc_save_p)
9398 fprintf (stderr, "\ttoc_save_p = %5d\n", info->toc_save_p);
9399
00b960c7
AH		 9400 if (info->vrsave_mask)
9401 fprintf (stderr, "\tvrsave_mask = 0x%x\n", info->vrsave_mask);
9402
4697a36c
MM		 9403 if (info->push_p)
9404 fprintf (stderr, "\tpush_p = %5d\n", info->push_p);
9405
9406 if (info->calls_p)
9407 fprintf (stderr, "\tcalls_p = %5d\n", info->calls_p);
9408
4697a36c
MM		 9409 if (info->gp_save_offset)
9410 fprintf (stderr, "\tgp_save_offset = %5d\n", info->gp_save_offset);
9411
9412 if (info->fp_save_offset)
9413 fprintf (stderr, "\tfp_save_offset = %5d\n", info->fp_save_offset);
9414
00b960c7
AH		 9415 if (info->altivec_save_offset)
9416 fprintf (stderr, "\taltivec_save_offset = %5d\n",
9417 info->altivec_save_offset);
9418
a3170dc6
AH		 9419 if (info->spe_gp_save_offset)
9420 fprintf (stderr, "\tspe_gp_save_offset = %5d\n",
9421 info->spe_gp_save_offset);
9422
00b960c7
AH		 9423 if (info->vrsave_save_offset)
9424 fprintf (stderr, "\tvrsave_save_offset = %5d\n",
9425 info->vrsave_save_offset);
9426
4697a36c
MM		 9427 if (info->lr_save_offset)
9428 fprintf (stderr, "\tlr_save_offset = %5d\n", info->lr_save_offset);
9429
9430 if (info->cr_save_offset)
9431 fprintf (stderr, "\tcr_save_offset = %5d\n", info->cr_save_offset);
9432
b6c9286a
MM		 9433 if (info->toc_save_offset)
9434 fprintf (stderr, "\ttoc_save_offset = %5d\n", info->toc_save_offset);
9435
4697a36c
MM		 9436 if (info->varargs_save_offset)
9437 fprintf (stderr, "\tvarargs_save_offset = %5d\n", info->varargs_save_offset);
9438
9439 if (info->total_size)
9440 fprintf (stderr, "\ttotal_size = %5d\n", info->total_size);
9441
9442 if (info->varargs_size)
9443 fprintf (stderr, "\tvarargs_size = %5d\n", info->varargs_size);
9444
9445 if (info->vars_size)
9446 fprintf (stderr, "\tvars_size = %5d\n", info->vars_size);
9447
9448 if (info->parm_size)
9449 fprintf (stderr, "\tparm_size = %5d\n", info->parm_size);
9450
9451 if (info->fixed_size)
9452 fprintf (stderr, "\tfixed_size = %5d\n", info->fixed_size);
9453
9454 if (info->gp_size)
9455 fprintf (stderr, "\tgp_size = %5d\n", info->gp_size);
9456
a3170dc6
AH		 9457 if (info->spe_gp_size)
9458 fprintf (stderr, "\tspe_gp_size = %5d\n", info->spe_gp_size);
9459
4697a36c
MM		 9460 if (info->fp_size)
9461 fprintf (stderr, "\tfp_size = %5d\n", info->fp_size);
9462
00b960c7
AH		 9463 if (info->altivec_size)
9464 fprintf (stderr, "\taltivec_size = %5d\n", info->altivec_size);
9465
9466 if (info->vrsave_size)
9467 fprintf (stderr, "\tvrsave_size = %5d\n", info->vrsave_size);
9468
9469 if (info->altivec_padding_size)
9470 fprintf (stderr, "\taltivec_padding_size= %5d\n",
9471 info->altivec_padding_size);
9472
a3170dc6
AH		 9473 if (info->spe_padding_size)
9474 fprintf (stderr, "\tspe_padding_size = %5d\n",
9475 info->spe_padding_size);
9476
a4f6c312 9477 if (info->lr_size)
ed947a96 9478 fprintf (stderr, "\tlr_size = %5d\n", info->lr_size);
b6c9286a 9479
4697a36c
MM		 9480 if (info->cr_size)
9481 fprintf (stderr, "\tcr_size = %5d\n", info->cr_size);
9482
a4f6c312 9483 if (info->toc_size)
b6c9286a
MM		 9484 fprintf (stderr, "\ttoc_size = %5d\n", info->toc_size);
9485
4697a36c
MM		 9486 if (info->save_size)
9487 fprintf (stderr, "\tsave_size = %5d\n", info->save_size);
9488
9489 if (info->reg_size != 4)
9490 fprintf (stderr, "\treg_size = %5d\n", info->reg_size);
9491
9492 fprintf (stderr, "\n");
9878760c 9493}
71f123ca
FS		 9494
9495rtx
9496rs6000_return_addr (count, frame)
9497 int count;
9498 rtx frame;
9499{
a4f6c312
SS		 9500 /* Currently we don't optimize very well between prolog and body
9501 code and for PIC code the code can be actually quite bad, so
9502 don't try to be too clever here. */
f585a356 9503 if (count != 0 || flag_pic != 0)
71f123ca
FS		 9504 {
9505 cfun->machine->ra_needs_full_frame = 1;
8ac61af7
RK		 9506
9507 return
9508 gen_rtx_MEM
9509 (Pmode,
9510 memory_address
9511 (Pmode,
9512 plus_constant (copy_to_reg
9513 (gen_rtx_MEM (Pmode,
9514 memory_address (Pmode, frame))),
9515 RETURN_ADDRESS_OFFSET)));
71f123ca
FS		 9516 }
9517
9e2f7ec7 9518 return get_hard_reg_initial_val (Pmode, LINK_REGISTER_REGNUM);
71f123ca
FS		 9519}
9520
5e1bf043
DJ		 9521/* Say whether a function is a candidate for sibcall handling or not.
9522 We do not allow indirect calls to be optimized into sibling calls.
9523 Also, we can't do it if there are any vector parameters; there's
9524 nowhere to put the VRsave code so it works; note that functions with
9525 vector parameters are required to have a prototype, so the argument
9526 type info must be available here. (The tail recursion case can work
9527 with vector parameters, but there's no way to distinguish here.) */
4977bab6
ZW		 9528static bool
9529rs6000_function_ok_for_sibcall (decl, exp)
9530 tree decl;
9531 tree exp ATTRIBUTE_UNUSED;
5e1bf043
DJ		 9532{
9533 tree type;
4977bab6 9534 if (decl)
5e1bf043
DJ		 9535 {
9536 if (TARGET_ALTIVEC_VRSAVE)
9537 {
4977bab6 9538 for (type = TYPE_ARG_TYPES (TREE_TYPE (decl));
5e1bf043
DJ		 9539 type; type = TREE_CHAIN (type))
9540 {
c15b529f 9541 if (TREE_CODE (TREE_VALUE (type)) == VECTOR_TYPE)
4977bab6 9542 return false;
5e1bf043
DJ		 9543 }
9544 }
9545 if (DEFAULT_ABI == ABI_DARWIN
4977bab6 9546 || (*targetm.binds_local_p) (decl))
2bcc50d0 9547 {
4977bab6 9548 tree attr_list = TYPE_ATTRIBUTES (TREE_TYPE (decl));
2bcc50d0
AM		 9549
9550 if (!lookup_attribute ("longcall", attr_list)
9551 || lookup_attribute ("shortcall", attr_list))
4977bab6 9552 return true;
2bcc50d0 9553 }
5e1bf043 9554 }
4977bab6 9555 return false;
5e1bf043
DJ		 9556}
9557
71f123ca
FS		 9558static int
9559rs6000_ra_ever_killed ()
9560{
9561 rtx top;
5e1bf043
DJ		 9562 rtx reg;
9563 rtx insn;
71f123ca 9564
3961e8fe
RH		 9565 /* Irritatingly, there are two kinds of thunks -- those created with
9566 TARGET_ASM_OUTPUT_MI_THUNK and those with DECL_THUNK_P that go
9567 through the regular part of the compiler. This is a very hacky
9568 way to tell them apart. */
9569 if (current_function_is_thunk && !no_new_pseudos)
71f123ca 9570 return 0;
eb0424da 9571
36f7e964
AH		 9572 /* regs_ever_live has LR marked as used if any sibcalls are present,
9573 but this should not force saving and restoring in the
9574 pro/epilogue. Likewise, reg_set_between_p thinks a sibcall
9575 clobbers LR, so that is inappropriate. */
9576
5e1bf043
DJ		 9577 /* Also, the prologue can generate a store into LR that
9578 doesn't really count, like this:
36f7e964 9579
5e1bf043
DJ		 9580 move LR->R0
9581 bcl to set PIC register
9582 move LR->R31
9583 move R0->LR
36f7e964
AH		 9584
9585 When we're called from the epilogue, we need to avoid counting
9586 this as a store. */
5e1bf043 9587
71f123ca
FS		 9588 push_topmost_sequence ();
9589 top = get_insns ();
9590 pop_topmost_sequence ();
5e1bf043 9591 reg = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM);
71f123ca 9592
5e1bf043
DJ		 9593 for (insn = NEXT_INSN (top); insn != NULL_RTX; insn = NEXT_INSN (insn))
9594 {
9595 if (INSN_P (insn))
9596 {
9597 if (FIND_REG_INC_NOTE (insn, reg))
9598 return 1;
9599 else if (GET_CODE (insn) == CALL_INSN
c15b529f 9600 && !SIBLING_CALL_P (insn))
5e1bf043 9601 return 1;
36f7e964
AH		 9602 else if (set_of (reg, insn) != NULL_RTX
9603 && !prologue_epilogue_contains (insn))
5e1bf043
DJ		 9604 return 1;
9605 }
9606 }
9607 return 0;
71f123ca 9608}
4697a36c 9609\f
8cd8f856
GK		 9610/* Add a REG_MAYBE_DEAD note to the insn. */
9611static void
9612rs6000_maybe_dead (insn)
9613 rtx insn;
9614{
9615 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD,
9616 const0_rtx,
9617 REG_NOTES (insn));
9618}
9619
9ebbca7d 9620/* Emit instructions needed to load the TOC register.
c7ca610e 9621 This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is
9ebbca7d 9622 a constant pool; or for SVR4 -fpic. */
c7ca610e
RK		 9623
9624void
9ebbca7d
GK		 9625rs6000_emit_load_toc_table (fromprolog)
9626 int fromprolog;
c7ca610e 9627{
9ebbca7d 9628 rtx dest;
1db02437 9629 dest = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
c7ca610e 9630
20b71b17
AM		 9631 if (TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 1)
9632 {
9633 rtx temp = (fromprolog
9634 ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)
9635 : gen_reg_rtx (Pmode));
9636 rs6000_maybe_dead (emit_insn (gen_load_toc_v4_pic_si (temp)));
9637 rs6000_maybe_dead (emit_move_insn (dest, temp));
9638 }
9639 else if (TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2)
9640 {
9641 char buf[30];
9642 rtx tempLR = (fromprolog
9643 ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)
9644 : gen_reg_rtx (Pmode));
9645 rtx temp0 = (fromprolog
9646 ? gen_rtx_REG (Pmode, 0)
9647 : gen_reg_rtx (Pmode));
9648 rtx symF;
9649
9650 /* possibly create the toc section */
9651 if (! toc_initialized)
38c1f2d7 9652 {
20b71b17
AM		 9653 toc_section ();
9654 function_section (current_function_decl);
38c1f2d7 9655 }
9ebbca7d 9656
20b71b17
AM		 9657 if (fromprolog)
9658 {
9659 rtx symL;
38c1f2d7 9660
20b71b17
AM		 9661 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
9662 symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
9ebbca7d 9663
20b71b17
AM		 9664 ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno);
9665 symL = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
9666
9667 rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_1 (tempLR,
9668 symF)));
9669 rs6000_maybe_dead (emit_move_insn (dest, tempLR));
9670 rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_2 (temp0, dest,
9671 symL,
9672 symF)));
9ebbca7d
GK		 9673 }
9674 else
20b71b17
AM		 9675 {
9676 rtx tocsym;
9677 static int reload_toc_labelno = 0;
9678
9679 tocsym = gen_rtx_SYMBOL_REF (Pmode, toc_label_name);
9680
9681 ASM_GENERATE_INTERNAL_LABEL (buf, "LCG", reload_toc_labelno++);
9682 symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
9683
9684 rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_1b (tempLR,
9685 symF,
9686 tocsym)));
9687 rs6000_maybe_dead (emit_move_insn (dest, tempLR));
9688 rs6000_maybe_dead (emit_move_insn (temp0,
9689 gen_rtx_MEM (Pmode, dest)));
9690 }
9691 rs6000_maybe_dead (emit_insn (gen_addsi3 (dest, temp0, dest)));
9ebbca7d 9692 }
20b71b17
AM		 9693 else if (TARGET_ELF && !TARGET_AIX && flag_pic == 0 && TARGET_MINIMAL_TOC)
9694 {
9695 /* This is for AIX code running in non-PIC ELF32. */
9696 char buf[30];
9697 rtx realsym;
9698 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
9699 realsym = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
9700
9701 rs6000_maybe_dead (emit_insn (gen_elf_high (dest, realsym)));
9702 rs6000_maybe_dead (emit_insn (gen_elf_low (dest, dest, realsym)));
9703 }
9704 else if (DEFAULT_ABI == ABI_AIX)
9ebbca7d
GK		 9705 {
9706 if (TARGET_32BIT)
20b71b17 9707 rs6000_maybe_dead (emit_insn (gen_load_toc_aix_si (dest)));
9ebbca7d 9708 else
20b71b17 9709 rs6000_maybe_dead (emit_insn (gen_load_toc_aix_di (dest)));
9ebbca7d 9710 }
20b71b17
AM		 9711 else
9712 abort ();
9ebbca7d
GK		 9713}
9714
9715int
9716get_TOC_alias_set ()
9717{
9718 static int set = -1;
9719 if (set == -1)
9720 set = new_alias_set ();
9721 return set;
9722}
9723
9724/* This retuns nonzero if the current function uses the TOC. This is
9725 determined by the presence of (unspec ... 7), which is generated by
9726 the various load_toc_* patterns. */
a4f6c312 9727
9ebbca7d
GK		 9728int
9729uses_TOC ()
9730{
9731 rtx insn;
38c1f2d7 9732
9ebbca7d 9733 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
2c3c49de 9734 if (INSN_P (insn))
9ebbca7d
GK		 9735 {
9736 rtx pat = PATTERN (insn);
9737 int i;
9738
8cd8f856 9739 if (GET_CODE (pat) == PARALLEL)
9ebbca7d
GK		 9740 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
9741 if (GET_CODE (XVECEXP (PATTERN (insn), 0, i)) == UNSPEC
9742 && XINT (XVECEXP (PATTERN (insn), 0, i), 1) == 7)
9743 return 1;
38c1f2d7 9744 }
9ebbca7d
GK		 9745 return 0;
9746}
38c1f2d7 9747
9ebbca7d 9748rtx
a4f6c312 9749create_TOC_reference (symbol)
9ebbca7d
GK		 9750 rtx symbol;
9751{
a8a05998
ZW		 9752 return gen_rtx_PLUS (Pmode,
9753 gen_rtx_REG (Pmode, TOC_REGISTER),
9754 gen_rtx_CONST (Pmode,
9755 gen_rtx_MINUS (Pmode, symbol,
b999aaeb 9756 gen_rtx_SYMBOL_REF (Pmode, toc_label_name))));
9ebbca7d 9757}
38c1f2d7 9758
9ebbca7d
GK		 9759#if TARGET_AIX
9760/* __throw will restore its own return address to be the same as the
9761 return address of the function that the throw is being made to.
9762 This is unfortunate, because we want to check the original
9763 return address to see if we need to restore the TOC.
9764 So we have to squirrel it away here.
9765 This is used only in compiling __throw and __rethrow.
c7ca610e 9766
9ebbca7d
GK		 9767 Most of this code should be removed by CSE. */
9768static rtx insn_after_throw;
c7ca610e 9769
a4f6c312 9770/* This does the saving... */
9ebbca7d
GK		 9771void
9772rs6000_aix_emit_builtin_unwind_init ()
9773{
9774 rtx mem;
9775 rtx stack_top = gen_reg_rtx (Pmode);
9776 rtx opcode_addr = gen_reg_rtx (Pmode);
9777
9778 insn_after_throw = gen_reg_rtx (SImode);
9779
9780 mem = gen_rtx_MEM (Pmode, hard_frame_pointer_rtx);
9781 emit_move_insn (stack_top, mem);
9782
9783 mem = gen_rtx_MEM (Pmode,
9784 gen_rtx_PLUS (Pmode, stack_top,
9785 GEN_INT (2 * GET_MODE_SIZE (Pmode))));
9786 emit_move_insn (opcode_addr, mem);
9787 emit_move_insn (insn_after_throw, gen_rtx_MEM (SImode, opcode_addr));
c7ca610e
RK		 9788}
9789
a4f6c312
SS		 9790/* Emit insns to _restore_ the TOC register, at runtime (specifically
9791 in _eh.o). Only used on AIX.
9ebbca7d
GK		 9792
9793 The idea is that on AIX, function calls look like this:
9794 bl somefunction-trampoline
9795 lwz r2,20(sp)
9796
a4f6c312 9797 and later,
9ebbca7d
GK		 9798 somefunction-trampoline:
9799 stw r2,20(sp)
9800 ... load function address in the count register ...
9801 bctr
9802 or like this, if the linker determines that this is not a cross-module call
9803 and so the TOC need not be restored:
9804 bl somefunction
9805 nop
9806 or like this, if the compiler could determine that this is not a
9807 cross-module call:
9808 bl somefunction
9809 now, the tricky bit here is that register 2 is saved and restored
9810 by the _linker_, so we can't readily generate debugging information
9811 for it. So we need to go back up the call chain looking at the
9812 insns at return addresses to see which calls saved the TOC register
9813 and so see where it gets restored from.
9814
9815 Oh, and all this gets done in RTL inside the eh_epilogue pattern,
9816 just before the actual epilogue.
9817
9818 On the bright side, this incurs no space or time overhead unless an
9819 exception is thrown, except for the extra code in libgcc.a.
9820
9821 The parameter STACKSIZE is a register containing (at runtime)
9822 the amount to be popped off the stack in addition to the stack frame
9823 of this routine (which will be __throw or __rethrow, and so is
9824 guaranteed to have a stack frame). */
a4f6c312 9825
9ebbca7d
GK		 9826void
9827rs6000_emit_eh_toc_restore (stacksize)
9828 rtx stacksize;
9829{
9830 rtx top_of_stack;
9831 rtx bottom_of_stack = gen_reg_rtx (Pmode);
9832 rtx tocompare = gen_reg_rtx (SImode);
9833 rtx opcode = gen_reg_rtx (SImode);
9834 rtx opcode_addr = gen_reg_rtx (Pmode);
9835 rtx mem;
9836 rtx loop_start = gen_label_rtx ();
9837 rtx no_toc_restore_needed = gen_label_rtx ();
9838 rtx loop_exit = gen_label_rtx ();
9839
9840 mem = gen_rtx_MEM (Pmode, hard_frame_pointer_rtx);
ba4828e0 9841 set_mem_alias_set (mem, rs6000_sr_alias_set);
9ebbca7d
GK		 9842 emit_move_insn (bottom_of_stack, mem);
9843
9844 top_of_stack = expand_binop (Pmode, add_optab,
9845 bottom_of_stack, stacksize,
9846 NULL_RTX, 1, OPTAB_WIDEN);
9847
2496c7bd
LB		 9848 emit_move_insn (tocompare, gen_int_mode (TARGET_32BIT ? 0x80410014
9849 : 0xE8410028, SImode));
9ebbca7d
GK		 9850
9851 if (insn_after_throw == NULL_RTX)
a4f6c312 9852 abort ();
9ebbca7d
GK		 9853 emit_move_insn (opcode, insn_after_throw);
9854
6496a589 9855 emit_note (NULL, NOTE_INSN_LOOP_BEG);
9ebbca7d
GK		 9856 emit_label (loop_start);
9857
9858 do_compare_rtx_and_jump (opcode, tocompare, NE, 1,
06f4e019 9859 SImode, NULL_RTX, NULL_RTX,
9ebbca7d
GK		 9860 no_toc_restore_needed);
9861
9862 mem = gen_rtx_MEM (Pmode,
9863 gen_rtx_PLUS (Pmode, bottom_of_stack,
9864 GEN_INT (5 * GET_MODE_SIZE (Pmode))));
9865 emit_move_insn (gen_rtx_REG (Pmode, 2), mem);
9866
9867 emit_label (no_toc_restore_needed);
9868 do_compare_rtx_and_jump (top_of_stack, bottom_of_stack, EQ, 1,
06f4e019 9869 Pmode, NULL_RTX, NULL_RTX,
9ebbca7d
GK		 9870 loop_exit);
9871
9872 mem = gen_rtx_MEM (Pmode, bottom_of_stack);
ba4828e0 9873 set_mem_alias_set (mem, rs6000_sr_alias_set);
9ebbca7d
GK		 9874 emit_move_insn (bottom_of_stack, mem);
9875
9876 mem = gen_rtx_MEM (Pmode,
9877 gen_rtx_PLUS (Pmode, bottom_of_stack,
9878 GEN_INT (2 * GET_MODE_SIZE (Pmode))));
9879 emit_move_insn (opcode_addr, mem);
9880 emit_move_insn (opcode, gen_rtx_MEM (SImode, opcode_addr));
9881
6496a589 9882 emit_note (NULL, NOTE_INSN_LOOP_CONT);
9ebbca7d 9883 emit_jump (loop_start);
6496a589 9884 emit_note (NULL, NOTE_INSN_LOOP_END);
9ebbca7d
GK		 9885 emit_label (loop_exit);
9886}
9887#endif /* TARGET_AIX */
38c1f2d7 9888\f
ba4828e0
RK		 9889/* This ties together stack memory (MEM with an alias set of
9890 rs6000_sr_alias_set) and the change to the stack pointer. */
9891
9ebbca7d
GK		 9892static void
9893rs6000_emit_stack_tie ()
9894{
ba4828e0
RK		 9895 rtx mem = gen_rtx_MEM (BLKmode, gen_rtx_REG (Pmode, STACK_POINTER_REGNUM));
9896
9897 set_mem_alias_set (mem, rs6000_sr_alias_set);
9ebbca7d
GK		 9898 emit_insn (gen_stack_tie (mem));
9899}
38c1f2d7 9900
9ebbca7d
GK		 9901/* Emit the correct code for allocating stack space, as insns.
9902 If COPY_R12, make sure a copy of the old frame is left in r12.
9903 The generated code may use hard register 0 as a temporary. */
9904
9905static void
9906rs6000_emit_allocate_stack (size, copy_r12)
9907 HOST_WIDE_INT size;
38c1f2d7
MM		 9908 int copy_r12;
9909{
9ebbca7d
GK		 9910 rtx insn;
9911 rtx stack_reg = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
9912 rtx tmp_reg = gen_rtx_REG (Pmode, 0);
9913 rtx todec = GEN_INT (-size);
a157febd
GK		 9914
9915 if (current_function_limit_stack)
9916 {
9917 if (REG_P (stack_limit_rtx)
9918 && REGNO (stack_limit_rtx) > 1
9919 && REGNO (stack_limit_rtx) <= 31)
9920 {
5b71a4e7 9921 emit_insn (TARGET_32BIT
9ebbca7d
GK		 9922 ? gen_addsi3 (tmp_reg,
9923 stack_limit_rtx,
9924 GEN_INT (size))
9925 : gen_adddi3 (tmp_reg,
9926 stack_limit_rtx,
9927 GEN_INT (size)));
5b71a4e7 9928
9ebbca7d
GK		 9929 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
9930 const0_rtx));
a157febd
GK		 9931 }
9932 else if (GET_CODE (stack_limit_rtx) == SYMBOL_REF
9ebbca7d 9933 && TARGET_32BIT
f607bc57 9934 && DEFAULT_ABI == ABI_V4)
a157febd 9935 {
9ebbca7d
GK		 9936 rtx toload = gen_rtx_CONST (VOIDmode,
9937 gen_rtx_PLUS (Pmode,
9938 stack_limit_rtx,
9939 GEN_INT (size)));
5b71a4e7 9940
9ebbca7d
GK		 9941 emit_insn (gen_elf_high (tmp_reg, toload));
9942 emit_insn (gen_elf_low (tmp_reg, tmp_reg, toload));
9943 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
9944 const0_rtx));
a157febd
GK		 9945 }
9946 else
9947 warning ("stack limit expression is not supported");
9948 }
9949
9ebbca7d
GK		 9950 if (copy_r12 || ! TARGET_UPDATE)
9951 emit_move_insn (gen_rtx_REG (Pmode, 12), stack_reg);
9952
38c1f2d7
MM		 9953 if (TARGET_UPDATE)
9954 {
9ebbca7d 9955 if (size > 32767)
38c1f2d7 9956 {
9ebbca7d
GK		 9957 /* Need a note here so that try_split doesn't get confused. */
9958 if (get_last_insn() == NULL_RTX)
9959 emit_note (0, NOTE_INSN_DELETED);
9960 insn = emit_move_insn (tmp_reg, todec);
9961 try_split (PATTERN (insn), insn, 0);
9962 todec = tmp_reg;
38c1f2d7 9963 }
5b71a4e7
DE		 9964
9965 insn = emit_insn (TARGET_32BIT
9966 ? gen_movsi_update (stack_reg, stack_reg,
9967 todec, stack_reg)
9968 : gen_movdi_update (stack_reg, stack_reg,
9ebbca7d 9969 todec, stack_reg));
38c1f2d7
MM		 9970 }
9971 else
9972 {
5b71a4e7
DE		 9973 insn = emit_insn (TARGET_32BIT
9974 ? gen_addsi3 (stack_reg, stack_reg, todec)
9975 : gen_adddi3 (stack_reg, stack_reg, todec));
9ebbca7d
GK		 9976 emit_move_insn (gen_rtx_MEM (Pmode, stack_reg),
9977 gen_rtx_REG (Pmode, 12));
9978 }
5b71a4e7 9979
9ebbca7d
GK		 9980 RTX_FRAME_RELATED_P (insn) = 1;
9981 REG_NOTES (insn) =
9982 gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
9983 gen_rtx_SET (VOIDmode, stack_reg,
9984 gen_rtx_PLUS (Pmode, stack_reg,
9985 GEN_INT (-size))),
9986 REG_NOTES (insn));
9987}
9988
9aa86737
AH		 9989/* Add a RTX_FRAME_RELATED note so that dwarf2out_frame_debug_expr
9990 knows that:
9991
9992 (mem (plus (blah) (regXX)))
9993
9994 is really:
9995
9996 (mem (plus (blah) (const VALUE_OF_REGXX))). */
9997
9998static void
9999altivec_frame_fixup (insn, reg, val)
10000 rtx insn, reg;
10001 HOST_WIDE_INT val;
10002{
10003 rtx real;
10004
10005 real = copy_rtx (PATTERN (insn));
10006
10007 real = replace_rtx (real, reg, GEN_INT (val));
10008
10009 RTX_FRAME_RELATED_P (insn) = 1;
10010 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
10011 real,
10012 REG_NOTES (insn));
10013}
10014
a4f6c312
SS		 10015/* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced
10016 with (plus:P (reg 1) VAL), and with REG2 replaced with RREG if REG2
10017 is not NULL. It would be nice if dwarf2out_frame_debug_expr could
10018 deduce these equivalences by itself so it wasn't necessary to hold
10019 its hand so much. */
9ebbca7d
GK		 10020
10021static void
10022rs6000_frame_related (insn, reg, val, reg2, rreg)
10023 rtx insn;
10024 rtx reg;
10025 HOST_WIDE_INT val;
10026 rtx reg2;
10027 rtx rreg;
10028{
10029 rtx real, temp;
10030
e56c4463
JL		 10031 /* copy_rtx will not make unique copies of registers, so we need to
10032 ensure we don't have unwanted sharing here. */
10033 if (reg == reg2)
10034 reg = gen_raw_REG (GET_MODE (reg), REGNO (reg));
10035
10036 if (reg == rreg)
10037 reg = gen_raw_REG (GET_MODE (reg), REGNO (reg));
10038
9ebbca7d
GK		 10039 real = copy_rtx (PATTERN (insn));
10040
89e7058f
AH		 10041 if (reg2 != NULL_RTX)
10042 real = replace_rtx (real, reg2, rreg);
10043
9ebbca7d
GK		 10044 real = replace_rtx (real, reg,
10045 gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode,
10046 STACK_POINTER_REGNUM),
10047 GEN_INT (val)));
10048
10049 /* We expect that 'real' is either a SET or a PARALLEL containing
10050 SETs (and possibly other stuff). In a PARALLEL, all the SETs
10051 are important so they all have to be marked RTX_FRAME_RELATED_P. */
10052
10053 if (GET_CODE (real) == SET)
10054 {
10055 rtx set = real;
10056
10057 temp = simplify_rtx (SET_SRC (set));
10058 if (temp)
10059 SET_SRC (set) = temp;
10060 temp = simplify_rtx (SET_DEST (set));
10061 if (temp)
10062 SET_DEST (set) = temp;
10063 if (GET_CODE (SET_DEST (set)) == MEM)
38c1f2d7 10064 {
9ebbca7d
GK		 10065 temp = simplify_rtx (XEXP (SET_DEST (set), 0));
10066 if (temp)
10067 XEXP (SET_DEST (set), 0) = temp;
38c1f2d7 10068 }
38c1f2d7 10069 }
9ebbca7d
GK		 10070 else if (GET_CODE (real) == PARALLEL)
10071 {
10072 int i;
10073 for (i = 0; i < XVECLEN (real, 0); i++)
10074 if (GET_CODE (XVECEXP (real, 0, i)) == SET)
10075 {
10076 rtx set = XVECEXP (real, 0, i);
10077
10078 temp = simplify_rtx (SET_SRC (set));
10079 if (temp)
10080 SET_SRC (set) = temp;
10081 temp = simplify_rtx (SET_DEST (set));
10082 if (temp)
10083 SET_DEST (set) = temp;
10084 if (GET_CODE (SET_DEST (set)) == MEM)
10085 {
10086 temp = simplify_rtx (XEXP (SET_DEST (set), 0));
10087 if (temp)
10088 XEXP (SET_DEST (set), 0) = temp;
10089 }
10090 RTX_FRAME_RELATED_P (set) = 1;
10091 }
10092 }
10093 else
a4f6c312 10094 abort ();
9ebbca7d 10095
9ebbca7d
GK		 10096 RTX_FRAME_RELATED_P (insn) = 1;
10097 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
10098 real,
10099 REG_NOTES (insn));
38c1f2d7
MM		 10100}
10101
00b960c7
AH		 10102/* Returns an insn that has a vrsave set operation with the
10103 appropriate CLOBBERs. */
10104
10105static rtx
9aa86737 10106generate_set_vrsave (reg, info, epiloguep)
00b960c7
AH		 10107 rtx reg;
10108 rs6000_stack_t *info;
9aa86737 10109 int epiloguep;
00b960c7
AH		 10110{
10111 int nclobs, i;
10112 rtx insn, clobs[TOTAL_ALTIVEC_REGS + 1];
a004eb82 10113 rtx vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
00b960c7 10114
a004eb82
AH		 10115 clobs[0]
10116 = gen_rtx_SET (VOIDmode,
10117 vrsave,
10118 gen_rtx_UNSPEC_VOLATILE (SImode,
10119 gen_rtvec (2, reg, vrsave),
10120 30));
00b960c7
AH		 10121
10122 nclobs = 1;
10123
9aa86737
AH		 10124 /* We need to clobber the registers in the mask so the scheduler
10125 does not move sets to VRSAVE before sets of AltiVec registers.
10126
10127 However, if the function receives nonlocal gotos, reload will set
10128 all call saved registers live. We will end up with:
10129
10130 (set (reg 999) (mem))
10131 (parallel [ (set (reg vrsave) (unspec blah))
10132 (clobber (reg 999))])
10133
10134 The clobber will cause the store into reg 999 to be dead, and
10135 flow will attempt to delete an epilogue insn. In this case, we
10136 need an unspec use/set of the register. */
00b960c7
AH		 10137
10138 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
10139 if (info->vrsave_mask != 0 && ALTIVEC_REG_BIT (i) != 0)
9aa86737
AH		 10140 {
10141 if (!epiloguep || call_used_regs [i])
10142 clobs[nclobs++] = gen_rtx_CLOBBER (VOIDmode,
10143 gen_rtx_REG (V4SImode, i));
10144 else
10145 {
10146 rtx reg = gen_rtx_REG (V4SImode, i);
9aa86737
AH		 10147
10148 clobs[nclobs++]
a004eb82
AH		 10149 = gen_rtx_SET (VOIDmode,
10150 reg,
10151 gen_rtx_UNSPEC (V4SImode,
10152 gen_rtvec (1, reg), 27));
9aa86737
AH		 10153 }
10154 }
00b960c7
AH		 10155
10156 insn = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (nclobs));
10157
10158 for (i = 0; i < nclobs; ++i)
10159 XVECEXP (insn, 0, i) = clobs[i];
10160
10161 return insn;
10162}
10163
89e7058f
AH		 10164/* Save a register into the frame, and emit RTX_FRAME_RELATED_P notes.
10165 Save REGNO into [FRAME_REG + OFFSET] in mode MODE. */
10166
10167static void
10168emit_frame_save (frame_reg, frame_ptr, mode, regno, offset, total_size)
10169 rtx frame_reg;
10170 rtx frame_ptr;
10171 enum machine_mode mode;
10172 unsigned int regno;
10173 int offset;
10174 int total_size;
10175{
10176 rtx reg, offset_rtx, insn, mem, addr, int_rtx;
10177 rtx replacea, replaceb;
10178
10179 int_rtx = GEN_INT (offset);
10180
10181 /* Some cases that need register indexed addressing. */
10182 if ((TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
a3170dc6
AH		 10183 || (TARGET_SPE_ABI
10184 && SPE_VECTOR_MODE (mode)
10185 && !SPE_CONST_OFFSET_OK (offset)))
89e7058f
AH		 10186 {
10187 /* Whomever calls us must make sure r11 is available in the
10188 flow path of instructions in the prologue. */
10189 offset_rtx = gen_rtx_REG (Pmode, 11);
10190 emit_move_insn (offset_rtx, int_rtx);
10191
10192 replacea = offset_rtx;
10193 replaceb = int_rtx;
10194 }
10195 else
10196 {
10197 offset_rtx = int_rtx;
10198 replacea = NULL_RTX;
10199 replaceb = NULL_RTX;
10200 }
10201
10202 reg = gen_rtx_REG (mode, regno);
10203 addr = gen_rtx_PLUS (Pmode, frame_reg, offset_rtx);
10204 mem = gen_rtx_MEM (mode, addr);
10205 set_mem_alias_set (mem, rs6000_sr_alias_set);
10206
10207 insn = emit_move_insn (mem, reg);
10208
10209 rs6000_frame_related (insn, frame_ptr, total_size, replacea, replaceb);
10210}
10211
a3170dc6
AH		 10212/* Emit an offset memory reference suitable for a frame store, while
10213 converting to a valid addressing mode. */
10214
10215static rtx
10216gen_frame_mem_offset (mode, reg, offset)
10217 enum machine_mode mode;
10218 rtx reg;
10219 int offset;
10220{
10221 rtx int_rtx, offset_rtx;
10222
10223 int_rtx = GEN_INT (offset);
10224
10225 if (TARGET_SPE_ABI && SPE_VECTOR_MODE (mode))
10226 {
10227 offset_rtx = gen_rtx_REG (Pmode, FIXED_SCRATCH);
10228 emit_move_insn (offset_rtx, int_rtx);
10229 }
10230 else
10231 offset_rtx = int_rtx;
10232
10233 return gen_rtx_MEM (mode, gen_rtx_PLUS (Pmode, reg, offset_rtx));
10234}
10235
9ebbca7d
GK		 10236/* Emit function prologue as insns. */
10237
9878760c 10238void
83720594 10239rs6000_emit_prologue ()
9878760c 10240{
4697a36c 10241 rs6000_stack_t *info = rs6000_stack_info ();
9ebbca7d
GK		 10242 enum machine_mode reg_mode = TARGET_POWERPC64 ? DImode : SImode;
10243 int reg_size = TARGET_POWERPC64 ? 8 : 4;
10244 rtx sp_reg_rtx = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
10245 rtx frame_ptr_rtx = gen_rtx_REG (Pmode, 12);
10246 rtx frame_reg_rtx = sp_reg_rtx;
10247 rtx cr_save_rtx = NULL;
10248 rtx insn;
10249 int saving_FPRs_inline;
10250 int using_store_multiple;
10251 HOST_WIDE_INT sp_offset = 0;
10252
a3170dc6
AH		 10253 if (TARGET_SPE_ABI)
10254 {
10255 reg_mode = V2SImode;
10256 reg_size = 8;
10257 }
10258
9ebbca7d 10259 using_store_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64
a3170dc6 10260 && !TARGET_SPE_ABI
9ebbca7d
GK		 10261 && info->first_gp_reg_save < 31);
10262 saving_FPRs_inline = (info->first_fp_reg_save == 64
10263 || FP_SAVE_INLINE (info->first_fp_reg_save));
10264
10265 /* For V.4, update stack before we do any saving and set back pointer. */
f607bc57 10266 if (info->push_p && DEFAULT_ABI == ABI_V4)
9ebbca7d
GK		 10267 {
10268 if (info->total_size < 32767)
10269 sp_offset = info->total_size;
10270 else
10271 frame_reg_rtx = frame_ptr_rtx;
10272 rs6000_emit_allocate_stack (info->total_size,
10273 (frame_reg_rtx != sp_reg_rtx
10274 && (info->cr_save_p
10275 || info->lr_save_p
10276 || info->first_fp_reg_save < 64
10277 || info->first_gp_reg_save < 32
10278 )));
10279 if (frame_reg_rtx != sp_reg_rtx)
10280 rs6000_emit_stack_tie ();
10281 }
10282
9aa86737
AH		 10283 /* Save AltiVec registers if needed. */
10284 if (TARGET_ALTIVEC_ABI && info->altivec_size != 0)
10285 {
10286 int i;
10287
10288 /* There should be a non inline version of this, for when we
10289 are saving lots of vector registers. */
10290 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
10291 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
10292 {
10293 rtx areg, savereg, mem;
10294 int offset;
10295
10296 offset = info->altivec_save_offset + sp_offset
10297 + 16 * (i - info->first_altivec_reg_save);
10298
10299 savereg = gen_rtx_REG (V4SImode, i);
10300
10301 areg = gen_rtx_REG (Pmode, 0);
10302 emit_move_insn (areg, GEN_INT (offset));
10303
10304 /* AltiVec addressing mode is [reg+reg]. */
10305 mem = gen_rtx_MEM (V4SImode,
10306 gen_rtx_PLUS (Pmode, frame_reg_rtx, areg));
10307
10308 set_mem_alias_set (mem, rs6000_sr_alias_set);
10309
10310 insn = emit_move_insn (mem, savereg);
10311
10312 altivec_frame_fixup (insn, areg, offset);
10313 }
10314 }
10315
10316 /* VRSAVE is a bit vector representing which AltiVec registers
10317 are used. The OS uses this to determine which vector
10318 registers to save on a context switch. We need to save
10319 VRSAVE on the stack frame, add whatever AltiVec registers we
10320 used in this function, and do the corresponding magic in the
10321 epilogue. */
10322
10323 if (TARGET_ALTIVEC && info->vrsave_mask != 0)
10324 {
a004eb82 10325 rtx reg, mem, vrsave;
9aa86737
AH		 10326 int offset;
10327
10328 /* Get VRSAVE onto a GPR. */
10329 reg = gen_rtx_REG (SImode, 12);
a004eb82 10330 vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
b188f760
AH		 10331 if (TARGET_MACHO)
10332 emit_insn (gen_get_vrsave_internal (reg));
10333 else
10334 emit_insn (gen_rtx_SET (VOIDmode, reg, vrsave));
9aa86737
AH		 10335
10336 /* Save VRSAVE. */
10337 offset = info->vrsave_save_offset + sp_offset;
10338 mem
10339 = gen_rtx_MEM (SImode,
10340 gen_rtx_PLUS (Pmode, frame_reg_rtx, GEN_INT (offset)));
10341 set_mem_alias_set (mem, rs6000_sr_alias_set);
10342 insn = emit_move_insn (mem, reg);
10343
10344 /* Include the registers in the mask. */
10345 emit_insn (gen_iorsi3 (reg, reg, GEN_INT ((int) info->vrsave_mask)));
10346
10347 insn = emit_insn (generate_set_vrsave (reg, info, 0));
10348 }
10349
9ebbca7d
GK		 10350 /* If we use the link register, get it into r0. */
10351 if (info->lr_save_p)
71f123ca 10352 emit_move_insn (gen_rtx_REG (Pmode, 0),
9ebbca7d
GK		 10353 gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM));
10354
10355 /* If we need to save CR, put it into r12. */
10356 if (info->cr_save_p && frame_reg_rtx != frame_ptr_rtx)
10357 {
10358 cr_save_rtx = gen_rtx_REG (SImode, 12);
10359 emit_insn (gen_movesi_from_cr (cr_save_rtx));
10360 }
10361
a4f6c312
SS		 10362 /* Do any required saving of fpr's. If only one or two to save, do
10363 it ourselves. Otherwise, call function. */
9ebbca7d
GK		 10364 if (saving_FPRs_inline)
10365 {
10366 int i;
10367 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
10368 if ((regs_ever_live[info->first_fp_reg_save+i]
10369 && ! call_used_regs[info->first_fp_reg_save+i]))
89e7058f
AH		 10370 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, DFmode,
10371 info->first_fp_reg_save + i,
10372 info->fp_save_offset + sp_offset + 8 * i,
10373 info->total_size);
9ebbca7d
GK		 10374 }
10375 else if (info->first_fp_reg_save != 64)
10376 {
10377 int i;
10378 char rname[30];
520a57c8 10379 const char *alloc_rname;
9ebbca7d
GK		 10380 rtvec p;
10381 p = rtvec_alloc (2 + 64 - info->first_fp_reg_save);
10382
10383 RTVEC_ELT (p, 0) = gen_rtx_CLOBBER (VOIDmode,
10384 gen_rtx_REG (Pmode,
10385 LINK_REGISTER_REGNUM));
10386 sprintf (rname, "%s%d%s", SAVE_FP_PREFIX,
10387 info->first_fp_reg_save - 32, SAVE_FP_SUFFIX);
a8a05998 10388 alloc_rname = ggc_strdup (rname);
9ebbca7d
GK		 10389 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode,
10390 gen_rtx_SYMBOL_REF (Pmode,
10391 alloc_rname));
10392 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
10393 {
10394 rtx addr, reg, mem;
10395 reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
10396 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
10397 GEN_INT (info->fp_save_offset
10398 + sp_offset + 8*i));
10399 mem = gen_rtx_MEM (DFmode, addr);
ba4828e0 10400 set_mem_alias_set (mem, rs6000_sr_alias_set);
9ebbca7d
GK		 10401
10402 RTVEC_ELT (p, i + 2) = gen_rtx_SET (VOIDmode, mem, reg);
10403 }
10404 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
10405 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
10406 NULL_RTX, NULL_RTX);
10407 }
b6c9286a 10408
9ebbca7d
GK		 10409 /* Save GPRs. This is done as a PARALLEL if we are using
10410 the store-multiple instructions. */
10411 if (using_store_multiple)
b6c9286a 10412 {
308c142a 10413 rtvec p;
9ebbca7d
GK		 10414 int i;
10415 p = rtvec_alloc (32 - info->first_gp_reg_save);
9ebbca7d
GK		 10416 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
10417 {
10418 rtx addr, reg, mem;
10419 reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
10420 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
10421 GEN_INT (info->gp_save_offset
10422 + sp_offset
10423 + reg_size * i));
10424 mem = gen_rtx_MEM (reg_mode, addr);
ba4828e0 10425 set_mem_alias_set (mem, rs6000_sr_alias_set);
9ebbca7d
GK		 10426
10427 RTVEC_ELT (p, i) = gen_rtx_SET (VOIDmode, mem, reg);
10428 }
10429 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
10430 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
10431 NULL_RTX, NULL_RTX);
b6c9286a
MM		 10432 }
10433 else
10434 {
9ebbca7d
GK		 10435 int i;
10436 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
10437 if ((regs_ever_live[info->first_gp_reg_save+i]
10438 && ! call_used_regs[info->first_gp_reg_save+i])
1db02437 10439 || (i+info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM
f607bc57
ZW		 10440 && ((DEFAULT_ABI == ABI_V4 && flag_pic == 1)
10441 || (DEFAULT_ABI == ABI_DARWIN && flag_pic))))
a3170dc6
AH		 10442 {
10443 rtx addr, reg, mem;
10444 reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
10445
10446 if (TARGET_SPE_ABI)
10447 {
10448 int offset = info->spe_gp_save_offset + sp_offset + 8 * i;
10449 rtx b;
10450
10451 if (!SPE_CONST_OFFSET_OK (offset))
10452 {
10453 b = gen_rtx_REG (Pmode, FIXED_SCRATCH);
10454 emit_move_insn (b, GEN_INT (offset));
10455 }
10456 else
10457 b = GEN_INT (offset);
10458
10459 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, b);
10460 mem = gen_rtx_MEM (V2SImode, addr);
10461 set_mem_alias_set (mem, rs6000_sr_alias_set);
10462 insn = emit_move_insn (mem, reg);
10463
10464 if (GET_CODE (b) == CONST_INT)
10465 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
10466 NULL_RTX, NULL_RTX);
10467 else
10468 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
10469 b, GEN_INT (offset));
10470 }
10471 else
10472 {
10473 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
10474 GEN_INT (info->gp_save_offset
10475 + sp_offset
10476 + reg_size * i));
10477 mem = gen_rtx_MEM (reg_mode, addr);
10478 set_mem_alias_set (mem, rs6000_sr_alias_set);
10479
10480 insn = emit_move_insn (mem, reg);
10481 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
10482 NULL_RTX, NULL_RTX);
10483 }
10484 }
9ebbca7d
GK		 10485 }
10486
83720594
RH		 10487 /* ??? There's no need to emit actual instructions here, but it's the
10488 easiest way to get the frame unwind information emitted. */
10489 if (current_function_calls_eh_return)
10490 {
78e1b90d
DE		 10491 unsigned int i, regno;
10492
83720594
RH		 10493 for (i = 0; ; ++i)
10494 {
83720594
RH		 10495 regno = EH_RETURN_DATA_REGNO (i);
10496 if (regno == INVALID_REGNUM)
10497 break;
10498
89e7058f
AH		 10499 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, reg_mode, regno,
10500 info->ehrd_offset + sp_offset
10501 + reg_size * (int) i,
10502 info->total_size);
83720594
RH		 10503 }
10504 }
10505
9ebbca7d
GK		 10506 /* Save lr if we used it. */
10507 if (info->lr_save_p)
10508 {
10509 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
10510 GEN_INT (info->lr_save_offset + sp_offset));
10511 rtx reg = gen_rtx_REG (Pmode, 0);
10512 rtx mem = gen_rtx_MEM (Pmode, addr);
10513 /* This should not be of rs6000_sr_alias_set, because of
10514 __builtin_return_address. */
10515
10516 insn = emit_move_insn (mem, reg);
10517 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
10518 reg, gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM));
10519 }
10520
10521 /* Save CR if we use any that must be preserved. */
10522 if (info->cr_save_p)
10523 {
10524 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
10525 GEN_INT (info->cr_save_offset + sp_offset));
10526 rtx mem = gen_rtx_MEM (SImode, addr);
ba4828e0
RK		 10527
10528 set_mem_alias_set (mem, rs6000_sr_alias_set);
9ebbca7d
GK		 10529
10530 /* If r12 was used to hold the original sp, copy cr into r0 now
10531 that it's free. */
10532 if (REGNO (frame_reg_rtx) == 12)
10533 {
10534 cr_save_rtx = gen_rtx_REG (SImode, 0);
10535 emit_insn (gen_movesi_from_cr (cr_save_rtx));
10536 }
10537 insn = emit_move_insn (mem, cr_save_rtx);
10538
10539 /* Now, there's no way that dwarf2out_frame_debug_expr is going
10540 to understand '(unspec:SI [(reg:CC 68) ...] 19)'. But that's
10541 OK. All we have to do is specify that _one_ condition code
10542 register is saved in this stack slot. The thrower's epilogue
a1dc9455
FS		 10543 will then restore all the call-saved registers.
10544 We use CR2_REGNO (70) to be compatible with gcc-2.95 on Linux. */
9ebbca7d 10545 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
a1dc9455 10546 cr_save_rtx, gen_rtx_REG (SImode, CR2_REGNO));
9ebbca7d
GK		 10547 }
10548
10549 /* Update stack and set back pointer unless this is V.4,
10550 for which it was done previously. */
f607bc57 10551 if (info->push_p && DEFAULT_ABI != ABI_V4)
9ebbca7d
GK		 10552 rs6000_emit_allocate_stack (info->total_size, FALSE);
10553
10554 /* Set frame pointer, if needed. */
10555 if (frame_pointer_needed)
10556 {
a3170dc6 10557 insn = emit_move_insn (gen_rtx_REG (Pmode, FRAME_POINTER_REGNUM),
9ebbca7d
GK		 10558 sp_reg_rtx);
10559 RTX_FRAME_RELATED_P (insn) = 1;
b6c9286a 10560 }
9878760c 10561
1db02437 10562 /* If we are using RS6000_PIC_OFFSET_TABLE_REGNUM, we need to set it up. */
9ebbca7d 10563 if ((TARGET_TOC && TARGET_MINIMAL_TOC && get_pool_size () != 0)
f607bc57 10564 || (DEFAULT_ABI == ABI_V4 && flag_pic == 1
1db02437 10565 && regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM]))
9ebbca7d
GK		 10566 {
10567 /* If emit_load_toc_table will use the link register, we need to save
10568 it. We use R11 for this purpose because emit_load_toc_table
10569 can use register 0. This allows us to use a plain 'blr' to return
10570 from the procedure more often. */
d5fa86ba
GK		 10571 int save_LR_around_toc_setup = (TARGET_ELF && flag_pic != 0
10572 && ! info->lr_save_p
10573 && EXIT_BLOCK_PTR->pred != NULL);
9ebbca7d
GK		 10574 if (save_LR_around_toc_setup)
10575 emit_move_insn (gen_rtx_REG (Pmode, 11),
10576 gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM));
10577
10578 rs6000_emit_load_toc_table (TRUE);
10579
10580 if (save_LR_around_toc_setup)
10581 emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM),
10582 gen_rtx_REG (Pmode, 11));
10583 }
ee890fe2 10584
fcce224d 10585#if TARGET_MACHO
ee890fe2
SS		 10586 if (DEFAULT_ABI == ABI_DARWIN
10587 && flag_pic && current_function_uses_pic_offset_table)
10588 {
10589 rtx dest = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM);
f51eee6a
GK		 10590 char *picbase = machopic_function_base_name ();
10591 rtx src = gen_rtx_SYMBOL_REF (Pmode, ggc_alloc_string (picbase, -1));
ee890fe2 10592
f51eee6a 10593 rs6000_maybe_dead (emit_insn (gen_load_macho_picbase (dest, src)));
ee890fe2
SS		 10594
10595 rs6000_maybe_dead (
1db02437 10596 emit_move_insn (gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM),
ee890fe2
SS		 10597 gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)));
10598 }
fcce224d 10599#endif
9ebbca7d
GK		 10600}
10601
9ebbca7d 10602/* Write function prologue. */
a4f6c312 10603
08c148a8
NB		 10604static void
10605rs6000_output_function_prologue (file, size)
9ebbca7d 10606 FILE *file;
08c148a8 10607 HOST_WIDE_INT size ATTRIBUTE_UNUSED;
9ebbca7d
GK		 10608{
10609 rs6000_stack_t *info = rs6000_stack_info ();
10610
4697a36c
MM		 10611 if (TARGET_DEBUG_STACK)
10612 debug_stack_info (info);
9878760c 10613
a4f6c312
SS		 10614 /* Write .extern for any function we will call to save and restore
10615 fp values. */
10616 if (info->first_fp_reg_save < 64
10617 && !FP_SAVE_INLINE (info->first_fp_reg_save))
4d30c363 10618 fprintf (file, "\t.extern %s%d%s\n\t.extern %s%d%s\n",
4697a36c 10619 SAVE_FP_PREFIX, info->first_fp_reg_save - 32, SAVE_FP_SUFFIX,
a4f6c312
SS		 10620 RESTORE_FP_PREFIX, info->first_fp_reg_save - 32,
10621 RESTORE_FP_SUFFIX);
9878760c 10622
c764f757
RK		 10623 /* Write .extern for AIX common mode routines, if needed. */
10624 if (! TARGET_POWER && ! TARGET_POWERPC && ! common_mode_defined)
10625 {
f6709c70
JW		 10626 fputs ("\t.extern __mulh\n", file);
10627 fputs ("\t.extern __mull\n", file);
10628 fputs ("\t.extern __divss\n", file);
10629 fputs ("\t.extern __divus\n", file);
10630 fputs ("\t.extern __quoss\n", file);
10631 fputs ("\t.extern __quous\n", file);
c764f757
RK		 10632 common_mode_defined = 1;
10633 }
9878760c 10634
9ebbca7d 10635 if (! HAVE_prologue)
979721f8 10636 {
9ebbca7d 10637 start_sequence ();
9dda4cc8 10638
a4f6c312
SS		 10639 /* A NOTE_INSN_DELETED is supposed to be at the start and end of
10640 the "toplevel" insn chain. */
9ebbca7d
GK		 10641 emit_note (0, NOTE_INSN_DELETED);
10642 rs6000_emit_prologue ();
10643 emit_note (0, NOTE_INSN_DELETED);
178c3eff
DJ		 10644
10645 /* Expand INSN_ADDRESSES so final() doesn't crash. */
10646 {
10647 rtx insn;
10648 unsigned addr = 0;
10649 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
10650 {
10651 INSN_ADDRESSES_NEW (insn, addr);
10652 addr += 4;
10653 }
10654 }
9dda4cc8 10655
9ebbca7d 10656 if (TARGET_DEBUG_STACK)
a4f6c312
SS		 10657 debug_rtx_list (get_insns (), 100);
10658 final (get_insns (), file, FALSE, FALSE);
9ebbca7d 10659 end_sequence ();
979721f8
MM		 10660 }
10661
9ebbca7d
GK		 10662 rs6000_pic_labelno++;
10663}
10664
10665/* Emit function epilogue as insns.
9878760c 10666
9ebbca7d
GK		 10667 At present, dwarf2out_frame_debug_expr doesn't understand
10668 register restores, so we don't bother setting RTX_FRAME_RELATED_P
10669 anywhere in the epilogue. Most of the insns below would in any case
10670 need special notes to explain where r11 is in relation to the stack. */
9878760c 10671
9ebbca7d 10672void
83720594 10673rs6000_emit_epilogue (sibcall)
9ebbca7d
GK		 10674 int sibcall;
10675{
10676 rs6000_stack_t *info;
10677 int restoring_FPRs_inline;
10678 int using_load_multiple;
10679 int using_mfcr_multiple;
10680 int use_backchain_to_restore_sp;
10681 int sp_offset = 0;
10682 rtx sp_reg_rtx = gen_rtx_REG (Pmode, 1);
10683 rtx frame_reg_rtx = sp_reg_rtx;
10684 enum machine_mode reg_mode = TARGET_POWERPC64 ? DImode : SImode;
10685 int reg_size = TARGET_POWERPC64 ? 8 : 4;
10686 int i;
10687
a3170dc6
AH		 10688 if (TARGET_SPE_ABI)
10689 {
10690 reg_mode = V2SImode;
10691 reg_size = 8;
10692 }
10693
9ebbca7d
GK		 10694 info = rs6000_stack_info ();
10695 using_load_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64
a3170dc6 10696 && !TARGET_SPE_ABI
9ebbca7d
GK		 10697 && info->first_gp_reg_save < 31);
10698 restoring_FPRs_inline = (sibcall
83720594 10699 || current_function_calls_eh_return
9ebbca7d
GK		 10700 || info->first_fp_reg_save == 64
10701 || FP_SAVE_INLINE (info->first_fp_reg_save));
10702 use_backchain_to_restore_sp = (frame_pointer_needed
10703 || current_function_calls_alloca
10704 || info->total_size > 32767);
10705 using_mfcr_multiple = (rs6000_cpu == PROCESSOR_PPC601
10706 || rs6000_cpu == PROCESSOR_PPC603
10707 || rs6000_cpu == PROCESSOR_PPC750
10708 || optimize_size);
10709
10710 /* If we have a frame pointer, a call to alloca, or a large stack
10711 frame, restore the old stack pointer using the backchain. Otherwise,
10712 we know what size to update it with. */
10713 if (use_backchain_to_restore_sp)
bacbde18 10714 {
9ebbca7d
GK		 10715 /* Under V.4, don't reset the stack pointer until after we're done
10716 loading the saved registers. */
f607bc57 10717 if (DEFAULT_ABI == ABI_V4)
9ebbca7d 10718 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
4697a36c 10719
9ebbca7d
GK		 10720 emit_move_insn (frame_reg_rtx,
10721 gen_rtx_MEM (Pmode, sp_reg_rtx));
10722
bacbde18 10723 }
9ebbca7d 10724 else if (info->push_p)
85638c0d 10725 {
f607bc57 10726 if (DEFAULT_ABI == ABI_V4)
9ebbca7d
GK		 10727 sp_offset = info->total_size;
10728 else
10729 {
10730 emit_insn (TARGET_32BIT
10731 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx,
10732 GEN_INT (info->total_size))
10733 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx,
10734 GEN_INT (info->total_size)));
10735 }
85638c0d 10736 }
9ebbca7d 10737
9aa86737
AH		 10738 /* Restore AltiVec registers if needed. */
10739 if (TARGET_ALTIVEC_ABI && info->altivec_size != 0)
10740 {
10741 int i;
10742
10743 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
10744 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
10745 {
10746 rtx addr, areg, mem;
10747
10748 areg = gen_rtx_REG (Pmode, 0);
10749 emit_move_insn
10750 (areg, GEN_INT (info->altivec_save_offset
10751 + sp_offset
10752 + 16 * (i - info->first_altivec_reg_save)));
10753
10754 /* AltiVec addressing mode is [reg+reg]. */
10755 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, areg);
10756 mem = gen_rtx_MEM (V4SImode, addr);
10757 set_mem_alias_set (mem, rs6000_sr_alias_set);
10758
10759 emit_move_insn (gen_rtx_REG (V4SImode, i), mem);
10760 }
10761 }
10762
10763 /* Restore VRSAVE if needed. */
10764 if (TARGET_ALTIVEC_ABI && info->vrsave_mask != 0)
10765 {
10766 rtx addr, mem, reg;
10767
10768 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
10769 GEN_INT (info->vrsave_save_offset + sp_offset));
10770 mem = gen_rtx_MEM (SImode, addr);
10771 set_mem_alias_set (mem, rs6000_sr_alias_set);
10772 reg = gen_rtx_REG (SImode, 12);
10773 emit_move_insn (reg, mem);
10774
10775 emit_insn (generate_set_vrsave (reg, info, 1));
10776 }
10777
9ebbca7d
GK		 10778 /* Get the old lr if we saved it. */
10779 if (info->lr_save_p)
b6c9286a 10780 {
a3170dc6
AH		 10781 rtx mem = gen_frame_mem_offset (Pmode, frame_reg_rtx,
10782 info->lr_save_offset + sp_offset);
ba4828e0
RK		 10783
10784 set_mem_alias_set (mem, rs6000_sr_alias_set);
b6c9286a 10785
9ebbca7d 10786 emit_move_insn (gen_rtx_REG (Pmode, 0), mem);
b6c9286a 10787 }
9ebbca7d
GK		 10788
10789 /* Get the old cr if we saved it. */
10790 if (info->cr_save_p)
10791 {
10792 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
10793 GEN_INT (info->cr_save_offset + sp_offset));
10794 rtx mem = gen_rtx_MEM (SImode, addr);
ba4828e0
RK		 10795
10796 set_mem_alias_set (mem, rs6000_sr_alias_set);
b6c9286a 10797
9ebbca7d
GK		 10798 emit_move_insn (gen_rtx_REG (SImode, 12), mem);
10799 }
10800
10801 /* Set LR here to try to overlap restores below. */
4697a36c 10802 if (info->lr_save_p)
9ebbca7d
GK		 10803 emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM),
10804 gen_rtx_REG (Pmode, 0));
10805
83720594
RH		 10806 /* Load exception handler data registers, if needed. */
10807 if (current_function_calls_eh_return)
10808 {
78e1b90d
DE		 10809 unsigned int i, regno;
10810
83720594
RH		 10811 for (i = 0; ; ++i)
10812 {
a3170dc6 10813 rtx mem;
83720594
RH		 10814
10815 regno = EH_RETURN_DATA_REGNO (i);
10816 if (regno == INVALID_REGNUM)
10817 break;
10818
a3170dc6
AH		 10819 mem = gen_frame_mem_offset (reg_mode, frame_reg_rtx,
10820 info->ehrd_offset + sp_offset
10821 + reg_size * (int) i);
ba4828e0 10822 set_mem_alias_set (mem, rs6000_sr_alias_set);
83720594
RH		 10823
10824 emit_move_insn (gen_rtx_REG (reg_mode, regno), mem);
10825 }
10826 }
9ebbca7d
GK		 10827
10828 /* Restore GPRs. This is done as a PARALLEL if we are using
10829 the load-multiple instructions. */
10830 if (using_load_multiple)
979721f8 10831 {
9ebbca7d
GK		 10832 rtvec p;
10833 p = rtvec_alloc (32 - info->first_gp_reg_save);
10834 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
979721f8 10835 {
9ebbca7d
GK		 10836 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
10837 GEN_INT (info->gp_save_offset
10838 + sp_offset
10839 + reg_size * i));
10840 rtx mem = gen_rtx_MEM (reg_mode, addr);
ba4828e0
RK		 10841
10842 set_mem_alias_set (mem, rs6000_sr_alias_set);
9ebbca7d
GK		 10843
10844 RTVEC_ELT (p, i) =
10845 gen_rtx_SET (VOIDmode,
10846 gen_rtx_REG (reg_mode, info->first_gp_reg_save + i),
10847 mem);
979721f8 10848 }
9ebbca7d 10849 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
979721f8 10850 }
9ebbca7d
GK		 10851 else
10852 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
10853 if ((regs_ever_live[info->first_gp_reg_save+i]
10854 && ! call_used_regs[info->first_gp_reg_save+i])
1db02437 10855 || (i+info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM
f607bc57
ZW		 10856 && ((DEFAULT_ABI == ABI_V4 && flag_pic == 1)
10857 || (DEFAULT_ABI == ABI_DARWIN && flag_pic))))
9ebbca7d
GK		 10858 {
10859 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
10860 GEN_INT (info->gp_save_offset
10861 + sp_offset
10862 + reg_size * i));
10863 rtx mem = gen_rtx_MEM (reg_mode, addr);
ba4828e0 10864
a3170dc6
AH		 10865 /* Restore 64-bit quantities for SPE. */
10866 if (TARGET_SPE_ABI)
10867 {
10868 int offset = info->spe_gp_save_offset + sp_offset + 8 * i;
10869 rtx b;
10870
10871 if (!SPE_CONST_OFFSET_OK (offset))
10872 {
10873 b = gen_rtx_REG (Pmode, FIXED_SCRATCH);
10874 emit_move_insn (b, GEN_INT (offset));
10875 }
10876 else
10877 b = GEN_INT (offset);
10878
10879 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, b);
10880 mem = gen_rtx_MEM (V2SImode, addr);
10881 }
10882
ba4828e0 10883 set_mem_alias_set (mem, rs6000_sr_alias_set);
9ebbca7d
GK		 10884
10885 emit_move_insn (gen_rtx_REG (reg_mode,
a3170dc6 10886 info->first_gp_reg_save + i), mem);
9ebbca7d 10887 }
9878760c 10888
9ebbca7d
GK		 10889 /* Restore fpr's if we need to do it without calling a function. */
10890 if (restoring_FPRs_inline)
10891 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
10892 if ((regs_ever_live[info->first_fp_reg_save+i]
10893 && ! call_used_regs[info->first_fp_reg_save+i]))
10894 {
10895 rtx addr, mem;
10896 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
10897 GEN_INT (info->fp_save_offset
10898 + sp_offset
a4f6c312 10899 + 8 * i));
9ebbca7d 10900 mem = gen_rtx_MEM (DFmode, addr);
ba4828e0 10901 set_mem_alias_set (mem, rs6000_sr_alias_set);
9ebbca7d
GK		 10902
10903 emit_move_insn (gen_rtx_REG (DFmode,
10904 info->first_fp_reg_save + i),
10905 mem);
10906 }
8d30c4ee 10907
9ebbca7d
GK		 10908 /* If we saved cr, restore it here. Just those that were used. */
10909 if (info->cr_save_p)
979721f8 10910 {
9ebbca7d 10911 rtx r12_rtx = gen_rtx_REG (SImode, 12);
e35b9579 10912 int count = 0;
9ebbca7d
GK		 10913
10914 if (using_mfcr_multiple)
979721f8 10915 {
9ebbca7d
GK		 10916 for (i = 0; i < 8; i++)
10917 if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i])
e35b9579 10918 count++;
9ebbca7d 10919 if (count == 0)
e35b9579
GK		 10920 abort ();
10921 }
10922
10923 if (using_mfcr_multiple && count > 1)
10924 {
10925 rtvec p;
10926 int ndx;
9ebbca7d 10927
e35b9579 10928 p = rtvec_alloc (count);
9ebbca7d 10929
e35b9579 10930 ndx = 0;
9ebbca7d
GK		 10931 for (i = 0; i < 8; i++)
10932 if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i])
10933 {
10934 rtvec r = rtvec_alloc (2);
10935 RTVEC_ELT (r, 0) = r12_rtx;
10936 RTVEC_ELT (r, 1) = GEN_INT (1 << (7-i));
e35b9579 10937 RTVEC_ELT (p, ndx) =
9ebbca7d
GK		 10938 gen_rtx_SET (VOIDmode, gen_rtx_REG (CCmode, CR0_REGNO+i),
10939 gen_rtx_UNSPEC (CCmode, r, 20));
e35b9579 10940 ndx++;
9ebbca7d
GK		 10941 }
10942 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
e35b9579
GK		 10943 if (ndx != count)
10944 abort ();
979721f8
MM		 10945 }
10946 else
9ebbca7d
GK		 10947 for (i = 0; i < 8; i++)
10948 if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i])
979721f8 10949 {
9ebbca7d
GK		 10950 emit_insn (gen_movsi_to_cr_one (gen_rtx_REG (CCmode,
10951 CR0_REGNO+i),
10952 r12_rtx));
979721f8 10953 }
979721f8
MM		 10954 }
10955
9ebbca7d
GK		 10956 /* If this is V.4, unwind the stack pointer after all of the loads
10957 have been done. We need to emit a block here so that sched
10958 doesn't decide to move the sp change before the register restores
10959 (which may not have any obvious dependency on the stack). This
10960 doesn't hurt performance, because there is no scheduling that can
10961 be done after this point. */
f607bc57 10962 if (DEFAULT_ABI == ABI_V4)
b6c9286a 10963 {
9ebbca7d
GK		 10964 if (frame_reg_rtx != sp_reg_rtx)
10965 rs6000_emit_stack_tie ();
b6c9286a 10966
9ebbca7d 10967 if (use_backchain_to_restore_sp)
b6c9286a 10968 {
9ebbca7d 10969 emit_move_insn (sp_reg_rtx, frame_reg_rtx);
b6c9286a 10970 }
9ebbca7d 10971 else if (sp_offset != 0)
13f1623b 10972 {
5b71a4e7 10973 emit_insn (TARGET_32BIT
9ebbca7d
GK		 10974 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx,
10975 GEN_INT (sp_offset))
10976 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx,
10977 GEN_INT (sp_offset)));
13f1623b 10978 }
9ebbca7d 10979 }
b6c9286a 10980
83720594
RH		 10981 if (current_function_calls_eh_return)
10982 {
10983 rtx sa = EH_RETURN_STACKADJ_RTX;
5b71a4e7 10984 emit_insn (TARGET_32BIT
83720594
RH		 10985 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx, sa)
10986 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx, sa));
10987 }
10988
9ebbca7d
GK		 10989 if (!sibcall)
10990 {
10991 rtvec p;
10992 if (! restoring_FPRs_inline)
10993 p = rtvec_alloc (3 + 64 - info->first_fp_reg_save);
10994 else
10995 p = rtvec_alloc (2);
b6c9286a 10996
e35b9579
GK		 10997 RTVEC_ELT (p, 0) = gen_rtx_RETURN (VOIDmode);
10998 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode,
9ebbca7d
GK		 10999 gen_rtx_REG (Pmode,
11000 LINK_REGISTER_REGNUM));
9ebbca7d
GK		 11001
11002 /* If we have to restore more than two FP registers, branch to the
11003 restore function. It will return to our caller. */
11004 if (! restoring_FPRs_inline)
11005 {
11006 int i;
11007 char rname[30];
520a57c8 11008 const char *alloc_rname;
979721f8 11009
9ebbca7d
GK		 11010 sprintf (rname, "%s%d%s", RESTORE_FP_PREFIX,
11011 info->first_fp_reg_save - 32, RESTORE_FP_SUFFIX);
a8a05998 11012 alloc_rname = ggc_strdup (rname);
9ebbca7d
GK		 11013 RTVEC_ELT (p, 2) = gen_rtx_USE (VOIDmode,
11014 gen_rtx_SYMBOL_REF (Pmode,
11015 alloc_rname));
b6c9286a 11016
9ebbca7d
GK		 11017 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
11018 {
11019 rtx addr, mem;
11020 addr = gen_rtx_PLUS (Pmode, sp_reg_rtx,
11021 GEN_INT (info->fp_save_offset + 8*i));
11022 mem = gen_rtx_MEM (DFmode, addr);
ba4828e0 11023 set_mem_alias_set (mem, rs6000_sr_alias_set);
9ebbca7d
GK		 11024
11025 RTVEC_ELT (p, i+3) =
11026 gen_rtx_SET (VOIDmode,
11027 gen_rtx_REG (DFmode, info->first_fp_reg_save + i),
11028 mem);
b6c9286a
MM		 11029 }
11030 }
9ebbca7d
GK		 11031
11032 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
3daf36a4 11033 }
9878760c
RK		 11034}
11035
11036/* Write function epilogue. */
11037
08c148a8
NB		 11038static void
11039rs6000_output_function_epilogue (file, size)
9878760c 11040 FILE *file;
08c148a8 11041 HOST_WIDE_INT size ATTRIBUTE_UNUSED;
9878760c 11042{
4697a36c 11043 rs6000_stack_t *info = rs6000_stack_info ();
9878760c 11044
9ebbca7d 11045 if (! HAVE_epilogue)
9878760c 11046 {
9ebbca7d
GK		 11047 rtx insn = get_last_insn ();
11048 /* If the last insn was a BARRIER, we don't have to write anything except
11049 the trace table. */
11050 if (GET_CODE (insn) == NOTE)
11051 insn = prev_nonnote_insn (insn);
11052 if (insn == 0 || GET_CODE (insn) != BARRIER)
4697a36c 11053 {
9ebbca7d
GK		 11054 /* This is slightly ugly, but at least we don't have two
11055 copies of the epilogue-emitting code. */
11056 start_sequence ();
11057
11058 /* A NOTE_INSN_DELETED is supposed to be at the start
11059 and end of the "toplevel" insn chain. */
11060 emit_note (0, NOTE_INSN_DELETED);
11061 rs6000_emit_epilogue (FALSE);
11062 emit_note (0, NOTE_INSN_DELETED);
11063
178c3eff
DJ		 11064 /* Expand INSN_ADDRESSES so final() doesn't crash. */
11065 {
11066 rtx insn;
11067 unsigned addr = 0;
11068 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
11069 {
11070 INSN_ADDRESSES_NEW (insn, addr);
11071 addr += 4;
11072 }
11073 }
11074
9ebbca7d 11075 if (TARGET_DEBUG_STACK)
a4f6c312
SS		 11076 debug_rtx_list (get_insns (), 100);
11077 final (get_insns (), file, FALSE, FALSE);
9ebbca7d 11078 end_sequence ();
4697a36c 11079 }
9878760c 11080 }
b4ac57ab 11081
9b30bae2 11082 /* Output a traceback table here. See /usr/include/sys/debug.h for info
314fc5a9
ILT		 11083 on its format.
11084
11085 We don't output a traceback table if -finhibit-size-directive was
11086 used. The documentation for -finhibit-size-directive reads
11087 ``don't output a @code{.size} assembler directive, or anything
11088 else that would cause trouble if the function is split in the
11089 middle, and the two halves are placed at locations far apart in
11090 memory.'' The traceback table has this property, since it
11091 includes the offset from the start of the function to the
4d30c363
MM		 11092 traceback table itself.
11093
11094 System V.4 Powerpc's (and the embedded ABI derived from it) use a
b6c9286a 11095 different traceback table. */
57ac7be9
AM		 11096 if (DEFAULT_ABI == ABI_AIX && ! flag_inhibit_size_directive
11097 && rs6000_traceback != traceback_none)
9b30bae2 11098 {
69c75916 11099 const char *fname = NULL;
3ac88239 11100 const char *language_string = lang_hooks.name;
6041bf2f 11101 int fixed_parms = 0, float_parms = 0, parm_info = 0;
314fc5a9 11102 int i;
57ac7be9
AM		 11103 int optional_tbtab;
11104
11105 if (rs6000_traceback == traceback_full)
11106 optional_tbtab = 1;
11107 else if (rs6000_traceback == traceback_part)
11108 optional_tbtab = 0;
11109 else
11110 optional_tbtab = !optimize_size && !TARGET_ELF;
314fc5a9 11111
69c75916
AM		 11112 if (optional_tbtab)
11113 {
11114 fname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
11115 while (*fname == '.') /* V.4 encodes . in the name */
11116 fname++;
11117
11118 /* Need label immediately before tbtab, so we can compute
11119 its offset from the function start. */
11120 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
11121 ASM_OUTPUT_LABEL (file, fname);
11122 }
314fc5a9
ILT		 11123
11124 /* The .tbtab pseudo-op can only be used for the first eight
11125 expressions, since it can't handle the possibly variable
11126 length fields that follow. However, if you omit the optional
11127 fields, the assembler outputs zeros for all optional fields
11128 anyways, giving each variable length field is minimum length
11129 (as defined in sys/debug.h). Thus we can not use the .tbtab
11130 pseudo-op at all. */
11131
11132 /* An all-zero word flags the start of the tbtab, for debuggers
11133 that have to find it by searching forward from the entry
11134 point or from the current pc. */
19d2d16f 11135 fputs ("\t.long 0\n", file);
314fc5a9
ILT		 11136
11137 /* Tbtab format type. Use format type 0. */
19d2d16f 11138 fputs ("\t.byte 0,", file);
314fc5a9
ILT		 11139
11140 /* Language type. Unfortunately, there doesn't seem to be any
11141 official way to get this info, so we use language_string. C
11142 is 0. C++ is 9. No number defined for Obj-C, so use the
9517ead8 11143 value for C for now. There is no official value for Java,
6f573ff9 11144 although IBM appears to be using 13. There is no official value
f710504c 11145 for Chill, so we've chosen 44 pseudo-randomly. */
314fc5a9 11146 if (! strcmp (language_string, "GNU C")
e2c953b6 11147 || ! strcmp (language_string, "GNU Objective-C"))
314fc5a9
ILT		 11148 i = 0;
11149 else if (! strcmp (language_string, "GNU F77"))
11150 i = 1;
11151 else if (! strcmp (language_string, "GNU Ada"))
11152 i = 3;
8b83775b 11153 else if (! strcmp (language_string, "GNU Pascal"))
314fc5a9
ILT		 11154 i = 2;
11155 else if (! strcmp (language_string, "GNU C++"))
11156 i = 9;
9517ead8
AG		 11157 else if (! strcmp (language_string, "GNU Java"))
11158 i = 13;
6f573ff9
JL		 11159 else if (! strcmp (language_string, "GNU CHILL"))
11160 i = 44;
314fc5a9
ILT		 11161 else
11162 abort ();
11163 fprintf (file, "%d,", i);
11164
11165 /* 8 single bit fields: global linkage (not set for C extern linkage,
11166 apparently a PL/I convention?), out-of-line epilogue/prologue, offset
11167 from start of procedure stored in tbtab, internal function, function
11168 has controlled storage, function has no toc, function uses fp,
11169 function logs/aborts fp operations. */
11170 /* Assume that fp operations are used if any fp reg must be saved. */
6041bf2f
DE		 11171 fprintf (file, "%d,",
11172 (optional_tbtab << 5) | ((info->first_fp_reg_save != 64) << 1));
314fc5a9
ILT		 11173
11174 /* 6 bitfields: function is interrupt handler, name present in
11175 proc table, function calls alloca, on condition directives
11176 (controls stack walks, 3 bits), saves condition reg, saves
11177 link reg. */
11178 /* The `function calls alloca' bit seems to be set whenever reg 31 is
11179 set up as a frame pointer, even when there is no alloca call. */
11180 fprintf (file, "%d,",
6041bf2f
DE		 11181 ((optional_tbtab << 6)
11182 | ((optional_tbtab & frame_pointer_needed) << 5)
11183 | (info->cr_save_p << 1)
11184 | (info->lr_save_p)));
314fc5a9 11185
6041bf2f 11186 /* 3 bitfields: saves backchain, fixup code, number of fpr saved
314fc5a9
ILT		 11187 (6 bits). */
11188 fprintf (file, "%d,",
4697a36c 11189 (info->push_p << 7) | (64 - info->first_fp_reg_save));
314fc5a9
ILT		 11190
11191 /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */
11192 fprintf (file, "%d,", (32 - first_reg_to_save ()));
11193
6041bf2f
DE		 11194 if (optional_tbtab)
11195 {
11196 /* Compute the parameter info from the function decl argument
11197 list. */
11198 tree decl;
11199 int next_parm_info_bit = 31;
314fc5a9 11200
6041bf2f
DE		 11201 for (decl = DECL_ARGUMENTS (current_function_decl);
11202 decl; decl = TREE_CHAIN (decl))
11203 {
11204 rtx parameter = DECL_INCOMING_RTL (decl);
11205 enum machine_mode mode = GET_MODE (parameter);
314fc5a9 11206
6041bf2f
DE		 11207 if (GET_CODE (parameter) == REG)
11208 {
11209 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
11210 {
11211 int bits;
11212
11213 float_parms++;
11214
11215 if (mode == SFmode)
11216 bits = 0x2;
fcce224d 11217 else if (mode == DFmode || mode == TFmode)
6041bf2f
DE		 11218 bits = 0x3;
11219 else
11220 abort ();
11221
11222 /* If only one bit will fit, don't or in this entry. */
11223 if (next_parm_info_bit > 0)
11224 parm_info |= (bits << (next_parm_info_bit - 1));
11225 next_parm_info_bit -= 2;
11226 }
11227 else
11228 {
11229 fixed_parms += ((GET_MODE_SIZE (mode)
11230 + (UNITS_PER_WORD - 1))
11231 / UNITS_PER_WORD);
11232 next_parm_info_bit -= 1;
11233 }
11234 }
11235 }
11236 }
314fc5a9
ILT		 11237
11238 /* Number of fixed point parameters. */
11239 /* This is actually the number of words of fixed point parameters; thus
11240 an 8 byte struct counts as 2; and thus the maximum value is 8. */
11241 fprintf (file, "%d,", fixed_parms);
11242
11243 /* 2 bitfields: number of floating point parameters (7 bits), parameters
11244 all on stack. */
11245 /* This is actually the number of fp registers that hold parameters;
11246 and thus the maximum value is 13. */
11247 /* Set parameters on stack bit if parameters are not in their original
11248 registers, regardless of whether they are on the stack? Xlc
11249 seems to set the bit when not optimizing. */
11250 fprintf (file, "%d\n", ((float_parms << 1) | (! optimize)));
11251
6041bf2f
DE		 11252 if (! optional_tbtab)
11253 return;
11254
314fc5a9
ILT		 11255 /* Optional fields follow. Some are variable length. */
11256
11257 /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float,
11258 11 double float. */
11259 /* There is an entry for each parameter in a register, in the order that
11260 they occur in the parameter list. Any intervening arguments on the
11261 stack are ignored. If the list overflows a long (max possible length
11262 34 bits) then completely leave off all elements that don't fit. */
11263 /* Only emit this long if there was at least one parameter. */
11264 if (fixed_parms || float_parms)
11265 fprintf (file, "\t.long %d\n", parm_info);
11266
11267 /* Offset from start of code to tb table. */
19d2d16f 11268 fputs ("\t.long ", file);
314fc5a9 11269 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
54ee9799
DE		 11270#if TARGET_AIX
11271 RS6000_OUTPUT_BASENAME (file, fname);
11272#else
9ebbca7d 11273 assemble_name (file, fname);
54ee9799 11274#endif
19d2d16f 11275 fputs ("-.", file);
54ee9799
DE		 11276#if TARGET_AIX
11277 RS6000_OUTPUT_BASENAME (file, fname);
11278#else
9ebbca7d 11279 assemble_name (file, fname);
54ee9799 11280#endif
19d2d16f 11281 putc ('\n', file);
314fc5a9
ILT		 11282
11283 /* Interrupt handler mask. */
11284 /* Omit this long, since we never set the interrupt handler bit
11285 above. */
11286
11287 /* Number of CTL (controlled storage) anchors. */
11288 /* Omit this long, since the has_ctl bit is never set above. */
11289
11290 /* Displacement into stack of each CTL anchor. */
11291 /* Omit this list of longs, because there are no CTL anchors. */
11292
11293 /* Length of function name. */
69c75916
AM		 11294 if (*fname == '*')
11295 ++fname;
296b8152 11296 fprintf (file, "\t.short %d\n", (int) strlen (fname));
314fc5a9
ILT		 11297
11298 /* Function name. */
11299 assemble_string (fname, strlen (fname));
11300
11301 /* Register for alloca automatic storage; this is always reg 31.
11302 Only emit this if the alloca bit was set above. */
11303 if (frame_pointer_needed)
19d2d16f 11304 fputs ("\t.byte 31\n", file);
b1765bde
DE		 11305
11306 fputs ("\t.align 2\n", file);
9b30bae2 11307 }
9878760c 11308}
17167fd8 11309\f
a4f6c312
SS		 11310/* A C compound statement that outputs the assembler code for a thunk
11311 function, used to implement C++ virtual function calls with
11312 multiple inheritance. The thunk acts as a wrapper around a virtual
11313 function, adjusting the implicit object parameter before handing
11314 control off to the real function.
11315
11316 First, emit code to add the integer DELTA to the location that
11317 contains the incoming first argument. Assume that this argument
11318 contains a pointer, and is the one used to pass the `this' pointer
11319 in C++. This is the incoming argument *before* the function
11320 prologue, e.g. `%o0' on a sparc. The addition must preserve the
11321 values of all other incoming arguments.
17167fd8
MM		 11322
11323 After the addition, emit code to jump to FUNCTION, which is a
a4f6c312
SS		 11324 `FUNCTION_DECL'. This is a direct pure jump, not a call, and does
11325 not touch the return address. Hence returning from FUNCTION will
11326 return to whoever called the current `thunk'.
17167fd8 11327
a4f6c312
SS		 11328 The effect must be as if FUNCTION had been called directly with the
11329 adjusted first argument. This macro is responsible for emitting
11330 all of the code for a thunk function; output_function_prologue()
11331 and output_function_epilogue() are not invoked.
17167fd8 11332
a4f6c312
SS		 11333 The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already
11334 been extracted from it.) It might possibly be useful on some
11335 targets, but probably not.
17167fd8 11336
a4f6c312
SS		 11337 If you do not define this macro, the target-independent code in the
11338 C++ frontend will generate a less efficient heavyweight thunk that
11339 calls FUNCTION instead of jumping to it. The generic approach does
11340 not support varargs. */
17167fd8 11341
3961e8fe
RH		 11342static void
11343rs6000_output_mi_thunk (file, thunk_fndecl, delta, vcall_offset, function)
17167fd8 11344 FILE *file;
d330fd93 11345 tree thunk_fndecl ATTRIBUTE_UNUSED;
eb0424da 11346 HOST_WIDE_INT delta;
5b71a4e7 11347 HOST_WIDE_INT vcall_offset;
17167fd8
MM		 11348 tree function;
11349{
5b71a4e7 11350 rtx this, insn, funexp;
17167fd8 11351
5b71a4e7
DE		 11352 reload_completed = 1;
11353 no_new_pseudos = 1;
56a7189a 11354
5b71a4e7
DE		 11355 /* Mark the end of the (empty) prologue. */
11356 emit_note (NULL, NOTE_INSN_PROLOGUE_END);
17167fd8 11357
5b71a4e7
DE		 11358 /* Find the "this" pointer. If the function returns a structure,
11359 the structure return pointer is in r3. */
11360 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function))))
11361 this = gen_rtx_REG (Pmode, 4);
56a7189a 11362 else
5b71a4e7 11363 this = gen_rtx_REG (Pmode, 3);
17167fd8 11364
5b71a4e7
DE		 11365 /* Apply the constant offset, if required. */
11366 if (delta)
11367 {
11368 rtx delta_rtx = GEN_INT (delta);
11369 emit_insn (TARGET_32BIT
11370 ? gen_addsi3 (this, this, delta_rtx)
11371 : gen_adddi3 (this, this, delta_rtx));
17167fd8
MM		 11372 }
11373
5b71a4e7
DE		 11374 /* Apply the offset from the vtable, if required. */
11375 if (vcall_offset)
17167fd8 11376 {
5b71a4e7
DE		 11377 rtx vcall_offset_rtx = GEN_INT (vcall_offset);
11378 rtx tmp = gen_rtx_REG (Pmode, 12);
17167fd8 11379
5b71a4e7
DE		 11380 emit_move_insn (tmp, gen_rtx_MEM (Pmode, this));
11381 emit_insn (TARGET_32BIT
11382 ? gen_addsi3 (tmp, tmp, vcall_offset_rtx)
11383 : gen_adddi3 (tmp, tmp, vcall_offset_rtx));
11384 emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp));
11385 emit_insn (TARGET_32BIT
11386 ? gen_addsi3 (this, this, tmp)
11387 : gen_adddi3 (this, this, tmp));
17167fd8
MM		 11388 }
11389
5b71a4e7
DE		 11390 /* Generate a tail call to the target function. */
11391 if (!TREE_USED (function))
11392 {
11393 assemble_external (function);
11394 TREE_USED (function) = 1;
11395 }
11396 funexp = XEXP (DECL_RTL (function), 0);
42820a49 11397
5b71a4e7
DE		 11398 SYMBOL_REF_FLAG (funexp) = 0;
11399 if (current_file_function_operand (funexp, VOIDmode)
a5c76ee6
ZW		 11400 && (! lookup_attribute ("longcall",
11401 TYPE_ATTRIBUTES (TREE_TYPE (function)))
11402 || lookup_attribute ("shortcall",
11403 TYPE_ATTRIBUTES (TREE_TYPE (function)))))
5b71a4e7 11404 SYMBOL_REF_FLAG (funexp) = 1;
17167fd8 11405
5b71a4e7 11406 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
ee890fe2
SS		 11407
11408#if TARGET_MACHO
5b71a4e7
DE		 11409 if (flag_pic)
11410 funexp = machopic_indirect_call_target (funexp);
ee890fe2 11411#endif
5b71a4e7
DE		 11412
11413 /* gen_sibcall expects reload to convert scratch pseudo to LR so we must
11414 generate sibcall RTL explicitly to avoid constraint abort. */
11415 insn = emit_call_insn (
11416 gen_rtx_PARALLEL (VOIDmode,
11417 gen_rtvec (4,
11418 gen_rtx_CALL (VOIDmode,
11419 funexp, const0_rtx),
11420 gen_rtx_USE (VOIDmode, const0_rtx),
11421 gen_rtx_USE (VOIDmode,
11422 gen_rtx_REG (SImode,
11423 LINK_REGISTER_REGNUM)),
11424 gen_rtx_RETURN (VOIDmode))));
11425 SIBLING_CALL_P (insn) = 1;
11426 emit_barrier ();
11427
11428 /* Run just enough of rest_of_compilation to get the insns emitted.
11429 There's not really enough bulk here to make other passes such as
11430 instruction scheduling worth while. Note that use_thunk calls
11431 assemble_start_function and assemble_end_function. */
11432 insn = get_insns ();
11433 shorten_branches (insn);
11434 final_start_function (insn, file, 1);
11435 final (insn, file, 1, 0);
11436 final_end_function ();
11437
11438 reload_completed = 0;
11439 no_new_pseudos = 0;
9ebbca7d 11440}
9ebbca7d
GK		 11441\f
11442/* A quick summary of the various types of 'constant-pool tables'
11443 under PowerPC:
11444
11445 Target Flags Name One table per
11446 AIX (none) AIX TOC object file
11447 AIX -mfull-toc AIX TOC object file
11448 AIX -mminimal-toc AIX minimal TOC translation unit
11449 SVR4/EABI (none) SVR4 SDATA object file
11450 SVR4/EABI -fpic SVR4 pic object file
11451 SVR4/EABI -fPIC SVR4 PIC translation unit
11452 SVR4/EABI -mrelocatable EABI TOC function
11453 SVR4/EABI -maix AIX TOC object file
11454 SVR4/EABI -maix -mminimal-toc
11455 AIX minimal TOC translation unit
11456
11457 Name Reg. Set by entries contains:
11458 made by addrs? fp? sum?
11459
11460 AIX TOC 2 crt0 as Y option option
11461 AIX minimal TOC 30 prolog gcc Y Y option
11462 SVR4 SDATA 13 crt0 gcc N Y N
11463 SVR4 pic 30 prolog ld Y not yet N
11464 SVR4 PIC 30 prolog gcc Y option option
11465 EABI TOC 30 prolog gcc Y option option
11466
11467*/
11468
9ebbca7d
GK		 11469/* Hash functions for the hash table. */
11470
11471static unsigned
11472rs6000_hash_constant (k)
11473 rtx k;
11474{
46b33600
RH		 11475 enum rtx_code code = GET_CODE (k);
11476 enum machine_mode mode = GET_MODE (k);
11477 unsigned result = (code << 3) ^ mode;
11478 const char *format;
11479 int flen, fidx;
9ebbca7d 11480
46b33600
RH		 11481 format = GET_RTX_FORMAT (code);
11482 flen = strlen (format);
11483 fidx = 0;
9ebbca7d 11484
46b33600
RH		 11485 switch (code)
11486 {
11487 case LABEL_REF:
11488 return result * 1231 + (unsigned) INSN_UID (XEXP (k, 0));
11489
11490 case CONST_DOUBLE:
11491 if (mode != VOIDmode)
11492 return real_hash (CONST_DOUBLE_REAL_VALUE (k)) * result;
11493 flen = 2;
11494 break;
11495
11496 case CODE_LABEL:
11497 fidx = 3;
11498 break;
11499
11500 default:
11501 break;
11502 }
9ebbca7d
GK		 11503
11504 for (; fidx < flen; fidx++)
11505 switch (format[fidx])
11506 {
11507 case 's':
11508 {
11509 unsigned i, len;
11510 const char *str = XSTR (k, fidx);
11511 len = strlen (str);
11512 result = result * 613 + len;
11513 for (i = 0; i < len; i++)
11514 result = result * 613 + (unsigned) str[i];
17167fd8
MM		 11515 break;
11516 }
9ebbca7d
GK		 11517 case 'u':
11518 case 'e':
11519 result = result * 1231 + rs6000_hash_constant (XEXP (k, fidx));
11520 break;
11521 case 'i':
11522 case 'n':
11523 result = result * 613 + (unsigned) XINT (k, fidx);
11524 break;
11525 case 'w':
11526 if (sizeof (unsigned) >= sizeof (HOST_WIDE_INT))
11527 result = result * 613 + (unsigned) XWINT (k, fidx);
11528 else
11529 {
11530 size_t i;
11531 for (i = 0; i < sizeof(HOST_WIDE_INT)/sizeof(unsigned); i++)
11532 result = result * 613 + (unsigned) (XWINT (k, fidx)
11533 >> CHAR_BIT * i);
11534 }
11535 break;
11536 default:
a4f6c312 11537 abort ();
9ebbca7d 11538 }
46b33600 11539
9ebbca7d
GK		 11540 return result;
11541}
11542
11543static unsigned
11544toc_hash_function (hash_entry)
11545 const void * hash_entry;
11546{
a9098fd0
GK		 11547 const struct toc_hash_struct *thc =
11548 (const struct toc_hash_struct *) hash_entry;
11549 return rs6000_hash_constant (thc->key) ^ thc->key_mode;
9ebbca7d
GK		 11550}
11551
11552/* Compare H1 and H2 for equivalence. */
11553
11554static int
11555toc_hash_eq (h1, h2)
11556 const void * h1;
11557 const void * h2;
11558{
11559 rtx r1 = ((const struct toc_hash_struct *) h1)->key;
11560 rtx r2 = ((const struct toc_hash_struct *) h2)->key;
11561
a9098fd0
GK		 11562 if (((const struct toc_hash_struct *) h1)->key_mode
11563 != ((const struct toc_hash_struct *) h2)->key_mode)
11564 return 0;
11565
5692c7bc 11566 return rtx_equal_p (r1, r2);
9ebbca7d
GK		 11567}
11568
28e510bd
MM		 11569/* These are the names given by the C++ front-end to vtables, and
11570 vtable-like objects. Ideally, this logic should not be here;
11571 instead, there should be some programmatic way of inquiring as
11572 to whether or not an object is a vtable. */
11573
11574#define VTABLE_NAME_P(NAME) \
11575 (strncmp ("_vt.", name, strlen("_vt.")) == 0 \
11576 || strncmp ("_ZTV", name, strlen ("_ZTV")) == 0 \
11577 || strncmp ("_ZTT", name, strlen ("_ZTT")) == 0 \
11578 || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0)
11579
11580void
11581rs6000_output_symbol_ref (file, x)
11582 FILE *file;
11583 rtx x;
11584{
11585 /* Currently C++ toc references to vtables can be emitted before it
11586 is decided whether the vtable is public or private. If this is
11587 the case, then the linker will eventually complain that there is
11588 a reference to an unknown section. Thus, for vtables only,
11589 we emit the TOC reference to reference the symbol and not the
11590 section. */
11591 const char *name = XSTR (x, 0);
54ee9799
DE		 11592
11593 if (VTABLE_NAME_P (name))
11594 {
11595 RS6000_OUTPUT_BASENAME (file, name);
11596 }
11597 else
11598 assemble_name (file, name);
28e510bd
MM		 11599}
11600
a4f6c312
SS		 11601/* Output a TOC entry. We derive the entry name from what is being
11602 written. */
9878760c
RK		 11603
11604void
a9098fd0 11605output_toc (file, x, labelno, mode)
9878760c
RK		 11606 FILE *file;
11607 rtx x;
11608 int labelno;
a9098fd0 11609 enum machine_mode mode;
9878760c
RK		 11610{
11611 char buf[256];
3cce094d 11612 const char *name = buf;
ec940faa 11613 const char *real_name;
9878760c
RK		 11614 rtx base = x;
11615 int offset = 0;
11616
4697a36c
MM		 11617 if (TARGET_NO_TOC)
11618 abort ();
11619
9ebbca7d
GK		 11620 /* When the linker won't eliminate them, don't output duplicate
11621 TOC entries (this happens on AIX if there is any kind of TOC,
17211ab5
GK		 11622 and on SVR4 under -fPIC or -mrelocatable). Don't do this for
11623 CODE_LABELs. */
11624 if (TARGET_TOC && GET_CODE (x) != LABEL_REF)
9ebbca7d
GK		 11625 {
11626 struct toc_hash_struct *h;
11627 void * * found;
11628
17211ab5
GK		 11629 /* Create toc_hash_table. This can't be done at OVERRIDE_OPTIONS
11630 time because GGC is not initialised at that point. */
11631 if (toc_hash_table == NULL)
11632 toc_hash_table = htab_create_ggc (1021, toc_hash_function,
11633 toc_hash_eq, NULL);
11634
9ebbca7d
GK		 11635 h = ggc_alloc (sizeof (*h));
11636 h->key = x;
a9098fd0 11637 h->key_mode = mode;
9ebbca7d
GK		 11638 h->labelno = labelno;
11639
11640 found = htab_find_slot (toc_hash_table, h, 1);
11641 if (*found == NULL)
11642 *found = h;
11643 else /* This is indeed a duplicate.
11644 Set this label equal to that label. */
11645 {
11646 fputs ("\t.set ", file);
11647 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
11648 fprintf (file, "%d,", labelno);
11649 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
11650 fprintf (file, "%d\n", ((*(const struct toc_hash_struct **)
11651 found)->labelno));
11652 return;
11653 }
11654 }
11655
11656 /* If we're going to put a double constant in the TOC, make sure it's
11657 aligned properly when strict alignment is on. */
ff1720ed
RK		 11658 if (GET_CODE (x) == CONST_DOUBLE
11659 && STRICT_ALIGNMENT
a9098fd0 11660 && GET_MODE_BITSIZE (mode) >= 64
ff1720ed
RK		 11661 && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC)) {
11662 ASM_OUTPUT_ALIGN (file, 3);
11663 }
11664
4977bab6 11665 (*targetm.asm_out.internal_label) (file, "LC", labelno);
9878760c 11666
37c37a57
RK		 11667 /* Handle FP constants specially. Note that if we have a minimal
11668 TOC, things we put here aren't actually in the TOC, so we can allow
11669 FP constants. */
fcce224d
DE		 11670 if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == TFmode)
11671 {
11672 REAL_VALUE_TYPE rv;
11673 long k[4];
11674
11675 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
11676 REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, k);
11677
11678 if (TARGET_64BIT)
11679 {
11680 if (TARGET_MINIMAL_TOC)
11681 fputs (DOUBLE_INT_ASM_OP, file);
11682 else
11683 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
11684 k[0] & 0xffffffff, k[1] & 0xffffffff,
11685 k[2] & 0xffffffff, k[3] & 0xffffffff);
11686 fprintf (file, "0x%lx%08lx,0x%lx%08lx\n",
11687 k[0] & 0xffffffff, k[1] & 0xffffffff,
11688 k[2] & 0xffffffff, k[3] & 0xffffffff);
11689 return;
11690 }
11691 else
11692 {
11693 if (TARGET_MINIMAL_TOC)
11694 fputs ("\t.long ", file);
11695 else
11696 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
11697 k[0] & 0xffffffff, k[1] & 0xffffffff,
11698 k[2] & 0xffffffff, k[3] & 0xffffffff);
11699 fprintf (file, "0x%lx,0x%lx,0x%lx,0x%lx\n",
11700 k[0] & 0xffffffff, k[1] & 0xffffffff,
11701 k[2] & 0xffffffff, k[3] & 0xffffffff);
11702 return;
11703 }
11704 }
11705 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode)
9878760c 11706 {
042259f2
DE		 11707 REAL_VALUE_TYPE rv;
11708 long k[2];
0adc764e 11709
042259f2
DE		 11710 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
11711 REAL_VALUE_TO_TARGET_DOUBLE (rv, k);
31bfaa0b 11712
13ded975
DE		 11713 if (TARGET_64BIT)
11714 {
11715 if (TARGET_MINIMAL_TOC)
2bfcf297 11716 fputs (DOUBLE_INT_ASM_OP, file);
13ded975 11717 else
2f0552b6
AM		 11718 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
11719 k[0] & 0xffffffff, k[1] & 0xffffffff);
11720 fprintf (file, "0x%lx%08lx\n",
11721 k[0] & 0xffffffff, k[1] & 0xffffffff);
13ded975
DE		 11722 return;
11723 }
1875cc88 11724 else
13ded975
DE		 11725 {
11726 if (TARGET_MINIMAL_TOC)
2bfcf297 11727 fputs ("\t.long ", file);
13ded975 11728 else
2f0552b6
AM		 11729 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
11730 k[0] & 0xffffffff, k[1] & 0xffffffff);
11731 fprintf (file, "0x%lx,0x%lx\n",
11732 k[0] & 0xffffffff, k[1] & 0xffffffff);
13ded975
DE		 11733 return;
11734 }
9878760c 11735 }
a9098fd0 11736 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode)
9878760c 11737 {
042259f2
DE		 11738 REAL_VALUE_TYPE rv;
11739 long l;
9878760c 11740
042259f2
DE		 11741 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
11742 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
11743
31bfaa0b
DE		 11744 if (TARGET_64BIT)
11745 {
11746 if (TARGET_MINIMAL_TOC)
2bfcf297 11747 fputs (DOUBLE_INT_ASM_OP, file);
31bfaa0b 11748 else
2f0552b6
AM		 11749 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
11750 fprintf (file, "0x%lx00000000\n", l & 0xffffffff);
31bfaa0b
DE		 11751 return;
11752 }
042259f2 11753 else
31bfaa0b
DE		 11754 {
11755 if (TARGET_MINIMAL_TOC)
2bfcf297 11756 fputs ("\t.long ", file);
31bfaa0b 11757 else
2f0552b6
AM		 11758 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
11759 fprintf (file, "0x%lx\n", l & 0xffffffff);
31bfaa0b
DE		 11760 return;
11761 }
042259f2 11762 }
f176e826 11763 else if (GET_MODE (x) == VOIDmode
a9098fd0 11764 && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE))
042259f2 11765 {
e2c953b6 11766 unsigned HOST_WIDE_INT low;
042259f2
DE		 11767 HOST_WIDE_INT high;
11768
11769 if (GET_CODE (x) == CONST_DOUBLE)
11770 {
11771 low = CONST_DOUBLE_LOW (x);
11772 high = CONST_DOUBLE_HIGH (x);
11773 }
11774 else
11775#if HOST_BITS_PER_WIDE_INT == 32
11776 {
11777 low = INTVAL (x);
0858c623 11778 high = (low & 0x80000000) ? ~0 : 0;
042259f2
DE		 11779 }
11780#else
11781 {
0858c623 11782 low = INTVAL (x) & 0xffffffff;
042259f2
DE		 11783 high = (HOST_WIDE_INT) INTVAL (x) >> 32;
11784 }
11785#endif
9878760c 11786
a9098fd0
GK		 11787 /* TOC entries are always Pmode-sized, but since this
11788 is a bigendian machine then if we're putting smaller
11789 integer constants in the TOC we have to pad them.
11790 (This is still a win over putting the constants in
11791 a separate constant pool, because then we'd have
02a4ec28
FS		 11792 to have both a TOC entry _and_ the actual constant.)
11793
11794 For a 32-bit target, CONST_INT values are loaded and shifted
11795 entirely within `low' and can be stored in one TOC entry. */
11796
11797 if (TARGET_64BIT && POINTER_SIZE < GET_MODE_BITSIZE (mode))
a9098fd0 11798 abort ();/* It would be easy to make this work, but it doesn't now. */
02a4ec28
FS		 11799
11800 if (POINTER_SIZE > GET_MODE_BITSIZE (mode))
fb52d8de
AM		 11801 {
11802#if HOST_BITS_PER_WIDE_INT == 32
11803 lshift_double (low, high, POINTER_SIZE - GET_MODE_BITSIZE (mode),
11804 POINTER_SIZE, &low, &high, 0);
11805#else
11806 low |= high << 32;
11807 low <<= POINTER_SIZE - GET_MODE_BITSIZE (mode);
11808 high = (HOST_WIDE_INT) low >> 32;
11809 low &= 0xffffffff;
11810#endif
11811 }
a9098fd0 11812
13ded975
DE		 11813 if (TARGET_64BIT)
11814 {
11815 if (TARGET_MINIMAL_TOC)
2bfcf297 11816 fputs (DOUBLE_INT_ASM_OP, file);
13ded975 11817 else
2f0552b6
AM		 11818 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
11819 (long) high & 0xffffffff, (long) low & 0xffffffff);
11820 fprintf (file, "0x%lx%08lx\n",
11821 (long) high & 0xffffffff, (long) low & 0xffffffff);
13ded975
DE		 11822 return;
11823 }
1875cc88 11824 else
13ded975 11825 {
02a4ec28
FS		 11826 if (POINTER_SIZE < GET_MODE_BITSIZE (mode))
11827 {
11828 if (TARGET_MINIMAL_TOC)
2bfcf297 11829 fputs ("\t.long ", file);
02a4ec28 11830 else
2bfcf297 11831 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
2f0552b6
AM		 11832 (long) high & 0xffffffff, (long) low & 0xffffffff);
11833 fprintf (file, "0x%lx,0x%lx\n",
11834 (long) high & 0xffffffff, (long) low & 0xffffffff);
02a4ec28 11835 }
13ded975 11836 else
02a4ec28
FS		 11837 {
11838 if (TARGET_MINIMAL_TOC)
2bfcf297 11839 fputs ("\t.long ", file);
02a4ec28 11840 else
2f0552b6
AM		 11841 fprintf (file, "\t.tc IS_%lx[TC],", (long) low & 0xffffffff);
11842 fprintf (file, "0x%lx\n", (long) low & 0xffffffff);
02a4ec28 11843 }
13ded975
DE		 11844 return;
11845 }
9878760c
RK		 11846 }
11847
11848 if (GET_CODE (x) == CONST)
11849 {
2bfcf297
DB		 11850 if (GET_CODE (XEXP (x, 0)) != PLUS)
11851 abort ();
11852
9878760c
RK		 11853 base = XEXP (XEXP (x, 0), 0);
11854 offset = INTVAL (XEXP (XEXP (x, 0), 1));
11855 }
11856
11857 if (GET_CODE (base) == SYMBOL_REF)
11858 name = XSTR (base, 0);
11859 else if (GET_CODE (base) == LABEL_REF)
11860 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (XEXP (base, 0)));
11861 else if (GET_CODE (base) == CODE_LABEL)
11862 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (base));
11863 else
11864 abort ();
11865
772c5265 11866 real_name = (*targetm.strip_name_encoding) (name);
1875cc88 11867 if (TARGET_MINIMAL_TOC)
2bfcf297 11868 fputs (TARGET_32BIT ? "\t.long " : DOUBLE_INT_ASM_OP, file);
1875cc88
JW		 11869 else
11870 {
b6c9286a 11871 fprintf (file, "\t.tc %s", real_name);
9878760c 11872
1875cc88
JW		 11873 if (offset < 0)
11874 fprintf (file, ".N%d", - offset);
11875 else if (offset)
11876 fprintf (file, ".P%d", offset);
9878760c 11877
19d2d16f 11878 fputs ("[TC],", file);
1875cc88 11879 }
581bc4de
MM		 11880
11881 /* Currently C++ toc references to vtables can be emitted before it
11882 is decided whether the vtable is public or private. If this is
11883 the case, then the linker will eventually complain that there is
11884 a TOC reference to an unknown section. Thus, for vtables only,
11885 we emit the TOC reference to reference the symbol and not the
11886 section. */
28e510bd 11887 if (VTABLE_NAME_P (name))
581bc4de 11888 {
54ee9799 11889 RS6000_OUTPUT_BASENAME (file, name);
581bc4de
MM		 11890 if (offset < 0)
11891 fprintf (file, "%d", offset);
11892 else if (offset > 0)
11893 fprintf (file, "+%d", offset);
11894 }
11895 else
11896 output_addr_const (file, x);
19d2d16f 11897 putc ('\n', file);
9878760c
RK		 11898}
11899\f
11900/* Output an assembler pseudo-op to write an ASCII string of N characters
11901 starting at P to FILE.
11902
11903 On the RS/6000, we have to do this using the .byte operation and
11904 write out special characters outside the quoted string.
11905 Also, the assembler is broken; very long strings are truncated,
a4f6c312 11906 so we must artificially break them up early. */
9878760c
RK		 11907
11908void
11909output_ascii (file, p, n)
11910 FILE *file;
d330fd93 11911 const char *p;
9878760c
RK		 11912 int n;
11913{
11914 char c;
11915 int i, count_string;
d330fd93
KG		 11916 const char *for_string = "\t.byte \"";
11917 const char *for_decimal = "\t.byte ";
11918 const char *to_close = NULL;
9878760c
RK		 11919
11920 count_string = 0;
11921 for (i = 0; i < n; i++)
11922 {
11923 c = *p++;
11924 if (c >= ' ' && c < 0177)
11925 {
11926 if (for_string)
11927 fputs (for_string, file);
11928 putc (c, file);
11929
11930 /* Write two quotes to get one. */
11931 if (c == '"')
11932 {
11933 putc (c, file);
11934 ++count_string;
11935 }
11936
11937 for_string = NULL;
11938 for_decimal = "\"\n\t.byte ";
11939 to_close = "\"\n";
11940 ++count_string;
11941
11942 if (count_string >= 512)
11943 {
11944 fputs (to_close, file);
11945
11946 for_string = "\t.byte \"";
11947 for_decimal = "\t.byte ";
11948 to_close = NULL;
11949 count_string = 0;
11950 }
11951 }
11952 else
11953 {
11954 if (for_decimal)
11955 fputs (for_decimal, file);
11956 fprintf (file, "%d", c);
11957
11958 for_string = "\n\t.byte \"";
11959 for_decimal = ", ";
11960 to_close = "\n";
11961 count_string = 0;
11962 }
11963 }
11964
11965 /* Now close the string if we have written one. Then end the line. */
11966 if (to_close)
9ebbca7d 11967 fputs (to_close, file);
9878760c
RK		 11968}
11969\f
11970/* Generate a unique section name for FILENAME for a section type
11971 represented by SECTION_DESC. Output goes into BUF.
11972
11973 SECTION_DESC can be any string, as long as it is different for each
11974 possible section type.
11975
11976 We name the section in the same manner as xlc. The name begins with an
11977 underscore followed by the filename (after stripping any leading directory
11e5fe42
RK		 11978 names) with the last period replaced by the string SECTION_DESC. If
11979 FILENAME does not contain a period, SECTION_DESC is appended to the end of
11980 the name. */
9878760c
RK		 11981
11982void
11983rs6000_gen_section_name (buf, filename, section_desc)
11984 char **buf;
9ebbca7d
GK		 11985 const char *filename;
11986 const char *section_desc;
9878760c 11987{
9ebbca7d 11988 const char *q, *after_last_slash, *last_period = 0;
9878760c
RK		 11989 char *p;
11990 int len;
9878760c
RK		 11991
11992 after_last_slash = filename;
11993 for (q = filename; *q; q++)
11e5fe42
RK		 11994 {
11995 if (*q == '/')
11996 after_last_slash = q + 1;
11997 else if (*q == '.')
11998 last_period = q;
11999 }
9878760c 12000
11e5fe42 12001 len = strlen (after_last_slash) + strlen (section_desc) + 2;
6d9f628e 12002 *buf = (char *) xmalloc (len);
9878760c
RK		 12003
12004 p = *buf;
12005 *p++ = '_';
12006
12007 for (q = after_last_slash; *q; q++)
12008 {
11e5fe42 12009 if (q == last_period)
9878760c
RK		 12010 {
12011 strcpy (p, section_desc);
12012 p += strlen (section_desc);
e3981aab 12013 break;
9878760c
RK		 12014 }
12015
e9a780ec 12016 else if (ISALNUM (*q))
9878760c
RK		 12017 *p++ = *q;
12018 }
12019
11e5fe42 12020 if (last_period == 0)
9878760c
RK		 12021 strcpy (p, section_desc);
12022 else
12023 *p = '\0';
12024}
e165f3f0 12025\f
a4f6c312 12026/* Emit profile function. */
411707f4 12027
411707f4
CC		 12028void
12029output_profile_hook (labelno)
57ac7be9 12030 int labelno ATTRIBUTE_UNUSED;
411707f4 12031{
8480e480
CC		 12032 if (DEFAULT_ABI == ABI_AIX)
12033 {
57ac7be9
AM		 12034#ifdef NO_PROFILE_COUNTERS
12035 emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 0);
12036#else
8480e480 12037 char buf[30];
40501e5f 12038 const char *label_name;
8480e480 12039 rtx fun;
411707f4 12040
8480e480 12041 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
772c5265 12042 label_name = (*targetm.strip_name_encoding) (ggc_strdup (buf));
8480e480 12043 fun = gen_rtx_SYMBOL_REF (Pmode, label_name);
411707f4 12044
8480e480
CC		 12045 emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 1,
12046 fun, Pmode);
57ac7be9 12047#endif
8480e480 12048 }
ee890fe2
SS		 12049 else if (DEFAULT_ABI == ABI_DARWIN)
12050 {
d5fa86ba 12051 const char *mcount_name = RS6000_MCOUNT;
ee890fe2
SS		 12052 int caller_addr_regno = LINK_REGISTER_REGNUM;
12053
12054 /* Be conservative and always set this, at least for now. */
12055 current_function_uses_pic_offset_table = 1;
12056
12057#if TARGET_MACHO
12058 /* For PIC code, set up a stub and collect the caller's address
12059 from r0, which is where the prologue puts it. */
12060 if (flag_pic)
12061 {
12062 mcount_name = machopic_stub_name (mcount_name);
12063 if (current_function_uses_pic_offset_table)
12064 caller_addr_regno = 0;
12065 }
12066#endif
12067 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mcount_name),
12068 0, VOIDmode, 1,
12069 gen_rtx_REG (Pmode, caller_addr_regno), Pmode);
12070 }
411707f4
CC		 12071}
12072
a4f6c312 12073/* Write function profiler code. */
e165f3f0
RK		 12074
12075void
12076output_function_profiler (file, labelno)
12077 FILE *file;
12078 int labelno;
12079{
3daf36a4 12080 char buf[100];
09eeeacb 12081 int save_lr = 8;
e165f3f0 12082
3daf36a4 12083 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
38c1f2d7 12084 switch (DEFAULT_ABI)
3daf36a4 12085 {
38c1f2d7
MM		 12086 default:
12087 abort ();
12088
12089 case ABI_V4:
09eeeacb
AM		 12090 save_lr = 4;
12091 /* Fall through. */
12092
38c1f2d7 12093 case ABI_AIX_NODESC:
09eeeacb
AM		 12094 if (!TARGET_32BIT)
12095 {
12096 warning ("no profiling of 64-bit code for this ABI");
12097 return;
12098 }
38c1f2d7
MM		 12099 fprintf (file, "\tmflr %s\n", reg_names[0]);
12100 if (flag_pic == 1)
12101 {
dfdfa60f 12102 fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file);
09eeeacb
AM		 12103 asm_fprintf (file, "\t{st|stw} %s,%d(%s)\n",
12104 reg_names[0], save_lr, reg_names[1]);
17167fd8 12105 asm_fprintf (file, "\tmflr %s\n", reg_names[12]);
dfdfa60f 12106 asm_fprintf (file, "\t{l|lwz} %s,", reg_names[0]);
38c1f2d7 12107 assemble_name (file, buf);
17167fd8 12108 asm_fprintf (file, "@got(%s)\n", reg_names[12]);
38c1f2d7 12109 }
9ebbca7d 12110 else if (flag_pic > 1)
38c1f2d7 12111 {
09eeeacb
AM		 12112 asm_fprintf (file, "\t{st|stw} %s,%d(%s)\n",
12113 reg_names[0], save_lr, reg_names[1]);
9ebbca7d
GK		 12114 /* Now, we need to get the address of the label. */
12115 fputs ("\tbl 1f\n\t.long ", file);
034e84c4 12116 assemble_name (file, buf);
9ebbca7d
GK		 12117 fputs ("-.\n1:", file);
12118 asm_fprintf (file, "\tmflr %s\n", reg_names[11]);
12119 asm_fprintf (file, "\t{l|lwz} %s,0(%s)\n",
12120 reg_names[0], reg_names[11]);
12121 asm_fprintf (file, "\t{cax|add} %s,%s,%s\n",
12122 reg_names[0], reg_names[0], reg_names[11]);
38c1f2d7 12123 }
38c1f2d7
MM		 12124 else
12125 {
17167fd8 12126 asm_fprintf (file, "\t{liu|lis} %s,", reg_names[12]);
38c1f2d7 12127 assemble_name (file, buf);
dfdfa60f 12128 fputs ("@ha\n", file);
09eeeacb
AM		 12129 asm_fprintf (file, "\t{st|stw} %s,%d(%s)\n",
12130 reg_names[0], save_lr, reg_names[1]);
a260abc9 12131 asm_fprintf (file, "\t{cal|la} %s,", reg_names[0]);
38c1f2d7 12132 assemble_name (file, buf);
17167fd8 12133 asm_fprintf (file, "@l(%s)\n", reg_names[12]);
38c1f2d7
MM		 12134 }
12135
09eeeacb
AM		 12136 if (current_function_needs_context && DEFAULT_ABI == ABI_AIX_NODESC)
12137 {
12138 asm_fprintf (file, "\t{st|stw} %s,%d(%s)\n",
12139 reg_names[STATIC_CHAIN_REGNUM],
12140 12, reg_names[1]);
12141 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
12142 asm_fprintf (file, "\t{l|lwz} %s,%d(%s)\n",
12143 reg_names[STATIC_CHAIN_REGNUM],
12144 12, reg_names[1]);
12145 }
12146 else
12147 /* ABI_V4 saves the static chain reg with ASM_OUTPUT_REG_PUSH. */
12148 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
38c1f2d7
MM		 12149 break;
12150
12151 case ABI_AIX:
ee890fe2 12152 case ABI_DARWIN:
a4f6c312 12153 /* Don't do anything, done in output_profile_hook (). */
38c1f2d7
MM		 12154 break;
12155 }
e165f3f0 12156}
a251ffd0
TG		 12157
12158/* Adjust the cost of a scheduling dependency. Return the new cost of
12159 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
12160
c237e94a 12161static int
a06faf84 12162rs6000_adjust_cost (insn, link, dep_insn, cost)
a251ffd0
TG		 12163 rtx insn;
12164 rtx link;
296b8152 12165 rtx dep_insn ATTRIBUTE_UNUSED;
a251ffd0
TG		 12166 int cost;
12167{
12168 if (! recog_memoized (insn))
12169 return 0;
12170
12171 if (REG_NOTE_KIND (link) != 0)
12172 return 0;
12173
12174 if (REG_NOTE_KIND (link) == 0)
12175 {
ed947a96
DJ		 12176 /* Data dependency; DEP_INSN writes a register that INSN reads
12177 some cycles later. */
12178 switch (get_attr_type (insn))
12179 {
12180 case TYPE_JMPREG:
309323c2 12181 /* Tell the first scheduling pass about the latency between
ed947a96
DJ		 12182 a mtctr and bctr (and mtlr and br/blr). The first
12183 scheduling pass will not know about this latency since
12184 the mtctr instruction, which has the latency associated
12185 to it, will be generated by reload. */
309323c2 12186 return TARGET_POWER ? 5 : 4;
ed947a96
DJ		 12187 case TYPE_BRANCH:
12188 /* Leave some extra cycles between a compare and its
12189 dependent branch, to inhibit expensive mispredicts. */
309323c2
DE		 12190 if ((rs6000_cpu_attr == CPU_PPC603
12191 || rs6000_cpu_attr == CPU_PPC604
12192 || rs6000_cpu_attr == CPU_PPC604E
12193 || rs6000_cpu_attr == CPU_PPC620
12194 || rs6000_cpu_attr == CPU_PPC630
12195 || rs6000_cpu_attr == CPU_PPC750
12196 || rs6000_cpu_attr == CPU_PPC7400
12197 || rs6000_cpu_attr == CPU_PPC7450
12198 || rs6000_cpu_attr == CPU_POWER4)
ed947a96
DJ		 12199 && recog_memoized (dep_insn)
12200 && (INSN_CODE (dep_insn) >= 0)
12201 && (get_attr_type (dep_insn) == TYPE_COMPARE
12202 || get_attr_type (dep_insn) == TYPE_DELAYED_COMPARE
12203 || get_attr_type (dep_insn) == TYPE_FPCOMPARE
12204 || get_attr_type (dep_insn) == TYPE_CR_LOGICAL))
12205 return cost + 2;
12206 default:
12207 break;
12208 }
a251ffd0
TG		 12209 /* Fall out to return default cost. */
12210 }
12211
12212 return cost;
12213}
b6c9286a 12214
a4f6c312
SS		 12215/* A C statement (sans semicolon) to update the integer scheduling
12216 priority INSN_PRIORITY (INSN). Reduce the priority to execute the
12217 INSN earlier, increase the priority to execute INSN later. Do not
12218 define this macro if you do not need to adjust the scheduling
12219 priorities of insns. */
bef84347 12220
c237e94a 12221static int
bef84347 12222rs6000_adjust_priority (insn, priority)
d330fd93 12223 rtx insn ATTRIBUTE_UNUSED;
bef84347
VM		 12224 int priority;
12225{
a4f6c312
SS		 12226 /* On machines (like the 750) which have asymmetric integer units,
12227 where one integer unit can do multiply and divides and the other
12228 can't, reduce the priority of multiply/divide so it is scheduled
12229 before other integer operations. */
bef84347
VM		 12230
12231#if 0
2c3c49de 12232 if (! INSN_P (insn))
bef84347
VM		 12233 return priority;
12234
12235 if (GET_CODE (PATTERN (insn)) == USE)
12236 return priority;
12237
12238 switch (rs6000_cpu_attr) {
12239 case CPU_PPC750:
12240 switch (get_attr_type (insn))
12241 {
12242 default:
12243 break;
12244
12245 case TYPE_IMUL:
12246 case TYPE_IDIV:
3cb999d8
DE		 12247 fprintf (stderr, "priority was %#x (%d) before adjustment\n",
12248 priority, priority);
bef84347
VM		 12249 if (priority >= 0 && priority < 0x01000000)
12250 priority >>= 3;
12251 break;
12252 }
12253 }
12254#endif
12255
12256 return priority;
12257}
12258
a4f6c312
SS		 12259/* Return how many instructions the machine can issue per cycle. */
12260
c237e94a
ZW		 12261static int
12262rs6000_issue_rate ()
b6c9286a
MM		 12263{
12264 switch (rs6000_cpu_attr) {
3cb999d8
DE		 12265 case CPU_RIOS1: /* ? */
12266 case CPU_RS64A:
12267 case CPU_PPC601: /* ? */
ed947a96 12268 case CPU_PPC7450:
3cb999d8 12269 return 3;
b6c9286a 12270 case CPU_PPC603:
bef84347 12271 case CPU_PPC750:
ed947a96 12272 case CPU_PPC7400:
bef84347 12273 return 2;
3cb999d8 12274 case CPU_RIOS2:
b6c9286a 12275 case CPU_PPC604:
19684119 12276 case CPU_PPC604E:
b6c9286a 12277 case CPU_PPC620:
3cb999d8 12278 case CPU_PPC630:
309323c2 12279 case CPU_POWER4:
b6c9286a
MM		 12280 return 4;
12281 default:
12282 return 1;
12283 }
12284}
12285
b6c9286a 12286\f
b6c9286a
MM		 12287/* Length in units of the trampoline for entering a nested function. */
12288
12289int
12290rs6000_trampoline_size ()
12291{
12292 int ret = 0;
12293
12294 switch (DEFAULT_ABI)
12295 {
12296 default:
12297 abort ();
12298
12299 case ABI_AIX:
8f802bfb 12300 ret = (TARGET_32BIT) ? 12 : 24;
b6c9286a
MM		 12301 break;
12302
4dabc42d 12303 case ABI_DARWIN:
b6c9286a
MM		 12304 case ABI_V4:
12305 case ABI_AIX_NODESC:
03a7e1a5 12306 ret = (TARGET_32BIT) ? 40 : 48;
b6c9286a 12307 break;
b6c9286a
MM		 12308 }
12309
12310 return ret;
12311}
12312
12313/* Emit RTL insns to initialize the variable parts of a trampoline.
12314 FNADDR is an RTX for the address of the function's pure code.
12315 CXT is an RTX for the static chain value for the function. */
12316
12317void
12318rs6000_initialize_trampoline (addr, fnaddr, cxt)
12319 rtx addr;
12320 rtx fnaddr;
12321 rtx cxt;
12322{
ac2a93a1 12323 enum machine_mode pmode = Pmode;
8bd04c56
MM		 12324 int regsize = (TARGET_32BIT) ? 4 : 8;
12325 rtx ctx_reg = force_reg (pmode, cxt);
b6c9286a
MM		 12326
12327 switch (DEFAULT_ABI)
12328 {
12329 default:
12330 abort ();
12331
8bd04c56 12332/* Macros to shorten the code expansions below. */
39403d82 12333#define MEM_DEREF(addr) gen_rtx_MEM (pmode, memory_address (pmode, addr))
c5c76735
JL		 12334#define MEM_PLUS(addr,offset) \
12335 gen_rtx_MEM (pmode, memory_address (pmode, plus_constant (addr, offset)))
7c59dc5d 12336
b6c9286a
MM		 12337 /* Under AIX, just build the 3 word function descriptor */
12338 case ABI_AIX:
8bd04c56
MM		 12339 {
12340 rtx fn_reg = gen_reg_rtx (pmode);
12341 rtx toc_reg = gen_reg_rtx (pmode);
12342 emit_move_insn (fn_reg, MEM_DEREF (fnaddr));
1cb18e3c 12343 emit_move_insn (toc_reg, MEM_PLUS (fnaddr, regsize));
8bd04c56
MM		 12344 emit_move_insn (MEM_DEREF (addr), fn_reg);
12345 emit_move_insn (MEM_PLUS (addr, regsize), toc_reg);
12346 emit_move_insn (MEM_PLUS (addr, 2*regsize), ctx_reg);
12347 }
b6c9286a
MM		 12348 break;
12349
4dabc42d
TC		 12350 /* Under V.4/eabi/darwin, __trampoline_setup does the real work. */
12351 case ABI_DARWIN:
b6c9286a
MM		 12352 case ABI_V4:
12353 case ABI_AIX_NODESC:
39403d82 12354 emit_library_call (gen_rtx_SYMBOL_REF (SImode, "__trampoline_setup"),
eaf1bcf1
MM		 12355 FALSE, VOIDmode, 4,
12356 addr, pmode,
12357 GEN_INT (rs6000_trampoline_size ()), SImode,
12358 fnaddr, pmode,
12359 ctx_reg, pmode);
b6c9286a 12360 break;
b6c9286a
MM		 12361 }
12362
12363 return;
12364}
7509c759
MM		 12365
12366\f
91d231cb 12367/* Table of valid machine attributes. */
a4f6c312 12368
91d231cb 12369const struct attribute_spec rs6000_attribute_table[] =
7509c759 12370{
91d231cb 12371 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
a5c76ee6
ZW		 12372 { "longcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute },
12373 { "shortcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute },
12374 { NULL, 0, 0, false, false, false, NULL }
91d231cb 12375};
7509c759 12376
a5c76ee6
ZW		 12377/* Handle a "longcall" or "shortcall" attribute; arguments as in
12378 struct attribute_spec.handler. */
a4f6c312 12379
91d231cb
JM		 12380static tree
12381rs6000_handle_longcall_attribute (node, name, args, flags, no_add_attrs)
12382 tree *node;
12383 tree name;
12384 tree args ATTRIBUTE_UNUSED;
12385 int flags ATTRIBUTE_UNUSED;
12386 bool *no_add_attrs;
12387{
12388 if (TREE_CODE (*node) != FUNCTION_TYPE
12389 && TREE_CODE (*node) != FIELD_DECL
12390 && TREE_CODE (*node) != TYPE_DECL)
12391 {
12392 warning ("`%s' attribute only applies to functions",
12393 IDENTIFIER_POINTER (name));
12394 *no_add_attrs = true;
12395 }
6a4cee5f 12396
91d231cb 12397 return NULL_TREE;
7509c759
MM		 12398}
12399
a5c76ee6
ZW		 12400/* Set longcall attributes on all functions declared when
12401 rs6000_default_long_calls is true. */
12402static void
12403rs6000_set_default_type_attributes (type)
12404 tree type;
12405{
12406 if (rs6000_default_long_calls
12407 && (TREE_CODE (type) == FUNCTION_TYPE
12408 || TREE_CODE (type) == METHOD_TYPE))
12409 TYPE_ATTRIBUTES (type) = tree_cons (get_identifier ("longcall"),
12410 NULL_TREE,
12411 TYPE_ATTRIBUTES (type));
12412}
12413
3cb999d8
DE		 12414/* Return a reference suitable for calling a function with the
12415 longcall attribute. */
a4f6c312 12416
6a4cee5f
MM		 12417struct rtx_def *
12418rs6000_longcall_ref (call_ref)
12419 rtx call_ref;
12420{
d330fd93 12421 const char *call_name;
6a4cee5f
MM		 12422 tree node;
12423
12424 if (GET_CODE (call_ref) != SYMBOL_REF)
12425 return call_ref;
12426
12427 /* System V adds '.' to the internal name, so skip them. */
12428 call_name = XSTR (call_ref, 0);
12429 if (*call_name == '.')
12430 {
12431 while (*call_name == '.')
12432 call_name++;
12433
12434 node = get_identifier (call_name);
39403d82 12435 call_ref = gen_rtx_SYMBOL_REF (VOIDmode, IDENTIFIER_POINTER (node));
6a4cee5f
MM		 12436 }
12437
12438 return force_reg (Pmode, call_ref);
12439}
12440
7509c759 12441\f
b64a1b53
RH		 12442#ifdef USING_ELFOS_H
12443
7509c759
MM		 12444/* A C statement or statements to switch to the appropriate section
12445 for output of RTX in mode MODE. You can assume that RTX is some
12446 kind of constant in RTL. The argument MODE is redundant except in
12447 the case of a `const_int' rtx. Select the section by calling
12448 `text_section' or one of the alternatives for other sections.
12449
12450 Do not define this macro if you put all constants in the read-only
12451 data section. */
12452
b64a1b53
RH		 12453static void
12454rs6000_elf_select_rtx_section (mode, x, align)
a9098fd0 12455 enum machine_mode mode;
7509c759 12456 rtx x;
b64a1b53 12457 unsigned HOST_WIDE_INT align;
7509c759 12458{
a9098fd0 12459 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
7509c759 12460 toc_section ();
7509c759 12461 else
b64a1b53 12462 default_elf_select_rtx_section (mode, x, align);
7509c759
MM		 12463}
12464
12465/* A C statement or statements to switch to the appropriate
12466 section for output of DECL. DECL is either a `VAR_DECL' node
12467 or a constant of some sort. RELOC indicates whether forming
12468 the initial value of DECL requires link-time relocations. */
12469
ae46c4e0
RH		 12470static void
12471rs6000_elf_select_section (decl, reloc, align)
7509c759
MM		 12472 tree decl;
12473 int reloc;
0e5dbd9b 12474 unsigned HOST_WIDE_INT align;
7509c759 12475{
0e5dbd9b
DE		 12476 default_elf_select_section_1 (decl, reloc, align,
12477 flag_pic || DEFAULT_ABI == ABI_AIX);
63019373
GK		 12478}
12479
12480/* A C statement to build up a unique section name, expressed as a
12481 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
12482 RELOC indicates whether the initial value of EXP requires
12483 link-time relocations. If you do not define this macro, GCC will use
12484 the symbol name prefixed by `.' as the section name. Note - this
f5143c46 12485 macro can now be called for uninitialized data items as well as
4912a07c 12486 initialized data and functions. */
63019373 12487
ae46c4e0
RH		 12488static void
12489rs6000_elf_unique_section (decl, reloc)
63019373
GK		 12490 tree decl;
12491 int reloc;
12492{
0e5dbd9b
DE		 12493 default_unique_section_1 (decl, reloc,
12494 flag_pic || DEFAULT_ABI == ABI_AIX);
7509c759 12495}
d9407988
MM		 12496
12497\f
d9407988
MM		 12498/* If we are referencing a function that is static or is known to be
12499 in this file, make the SYMBOL_REF special. We can use this to indicate
12500 that we can branch to this function without emitting a no-op after the
9ebbca7d 12501 call. For real AIX calling sequences, we also replace the
d9407988
MM		 12502 function name with the real name (1 or 2 leading .'s), rather than
12503 the function descriptor name. This saves a lot of overriding code
a260abc9 12504 to read the prefixes. */
d9407988 12505
fb49053f
RH		 12506static void
12507rs6000_elf_encode_section_info (decl, first)
d9407988 12508 tree decl;
b2003250 12509 int first;
d9407988 12510{
b2003250
RH		 12511 if (!first)
12512 return;
12513
d9407988
MM		 12514 if (TREE_CODE (decl) == FUNCTION_DECL)
12515 {
12516 rtx sym_ref = XEXP (DECL_RTL (decl), 0);
b629ba0c 12517 if ((*targetm.binds_local_p) (decl))
d9407988
MM		 12518 SYMBOL_REF_FLAG (sym_ref) = 1;
12519
9ebbca7d 12520 if (DEFAULT_ABI == ABI_AIX)
d9407988 12521 {
ff669a6c
RH		 12522 size_t len1 = (DEFAULT_ABI == ABI_AIX) ? 1 : 2;
12523 size_t len2 = strlen (XSTR (sym_ref, 0));
520a57c8 12524 char *str = alloca (len1 + len2 + 1);
ff669a6c
RH		 12525 str[0] = '.';
12526 str[1] = '.';
12527 memcpy (str + len1, XSTR (sym_ref, 0), len2 + 1);
12528
520a57c8 12529 XSTR (sym_ref, 0) = ggc_alloc_string (str, len1 + len2);
d9407988
MM		 12530 }
12531 }
12532 else if (rs6000_sdata != SDATA_NONE
f607bc57 12533 && DEFAULT_ABI == ABI_V4
d9407988
MM		 12534 && TREE_CODE (decl) == VAR_DECL)
12535 {
c40e5172 12536 rtx sym_ref = XEXP (DECL_RTL (decl), 0);
d9407988
MM		 12537 int size = int_size_in_bytes (TREE_TYPE (decl));
12538 tree section_name = DECL_SECTION_NAME (decl);
d330fd93 12539 const char *name = (char *)0;
d9407988
MM		 12540 int len = 0;
12541
c40e5172
JS		 12542 if ((*targetm.binds_local_p) (decl))
12543 SYMBOL_REF_FLAG (sym_ref) = 1;
12544
d9407988
MM		 12545 if (section_name)
12546 {
12547 if (TREE_CODE (section_name) == STRING_CST)
12548 {
12549 name = TREE_STRING_POINTER (section_name);
12550 len = TREE_STRING_LENGTH (section_name);
12551 }
12552 else
12553 abort ();
12554 }
12555
12556 if ((size > 0 && size <= g_switch_value)
12557 || (name
5f59ecb7 12558 && ((len == sizeof (".sdata") - 1
3cb999d8 12559 && strcmp (name, ".sdata") == 0)
5f59ecb7 12560 || (len == sizeof (".sdata2") - 1
3cb999d8 12561 && strcmp (name, ".sdata2") == 0)
5f59ecb7 12562 || (len == sizeof (".sbss") - 1
3cb999d8 12563 && strcmp (name, ".sbss") == 0)
5f59ecb7 12564 || (len == sizeof (".sbss2") - 1
3cb999d8 12565 && strcmp (name, ".sbss2") == 0)
5f59ecb7 12566 || (len == sizeof (".PPC.EMB.sdata0") - 1
3cb999d8 12567 && strcmp (name, ".PPC.EMB.sdata0") == 0)
5f59ecb7 12568 || (len == sizeof (".PPC.EMB.sbss0") - 1
3cb999d8 12569 && strcmp (name, ".PPC.EMB.sbss0") == 0))))
d9407988 12570 {
ff669a6c 12571 size_t len = strlen (XSTR (sym_ref, 0));
88c1e412 12572 char *str = alloca (len + 2);
ff669a6c 12573
ff669a6c
RH		 12574 str[0] = '@';
12575 memcpy (str + 1, XSTR (sym_ref, 0), len + 1);
88c1e412 12576 XSTR (sym_ref, 0) = ggc_alloc_string (str, len + 1);
d9407988
MM		 12577 }
12578 }
12579}
12580
772c5265
RH		 12581static const char *
12582rs6000_elf_strip_name_encoding (str)
12583 const char *str;
12584{
12585 while (*str == '*' || *str == '@')
12586 str++;
12587 return str;
12588}
12589
0e5dbd9b
DE		 12590static bool
12591rs6000_elf_in_small_data_p (decl)
12592 tree decl;
12593{
12594 if (rs6000_sdata == SDATA_NONE)
12595 return false;
12596
12597 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl))
12598 {
12599 const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
12600 if (strcmp (section, ".sdata") == 0
12601 || strcmp (section, ".sdata2") == 0
12602 || strcmp (section, ".sbss") == 0)
12603 return true;
12604 }
12605 else
12606 {
12607 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (decl));
12608
12609 if (size > 0
12610 && size <= g_switch_value
12611 && (rs6000_sdata != SDATA_DATA || TREE_PUBLIC (decl)))
12612 return true;
12613 }
12614
12615 return false;
12616}
12617
b91da81f 12618#endif /* USING_ELFOS_H */
000034eb 12619
a6c2a102 12620\f
000034eb 12621/* Return a REG that occurs in ADDR with coefficient 1.
02441cd6
JL		 12622 ADDR can be effectively incremented by incrementing REG.
12623
12624 r0 is special and we must not select it as an address
12625 register by this routine since our caller will try to
12626 increment the returned register via an "la" instruction. */
000034eb
DE		 12627
12628struct rtx_def *
12629find_addr_reg (addr)
12630 rtx addr;
12631{
12632 while (GET_CODE (addr) == PLUS)
12633 {
02441cd6
JL		 12634 if (GET_CODE (XEXP (addr, 0)) == REG
12635 && REGNO (XEXP (addr, 0)) != 0)
000034eb 12636 addr = XEXP (addr, 0);
02441cd6
JL		 12637 else if (GET_CODE (XEXP (addr, 1)) == REG
12638 && REGNO (XEXP (addr, 1)) != 0)
000034eb
DE		 12639 addr = XEXP (addr, 1);
12640 else if (CONSTANT_P (XEXP (addr, 0)))
12641 addr = XEXP (addr, 1);
12642 else if (CONSTANT_P (XEXP (addr, 1)))
12643 addr = XEXP (addr, 0);
12644 else
12645 abort ();
12646 }
02441cd6 12647 if (GET_CODE (addr) == REG && REGNO (addr) != 0)
000034eb
DE		 12648 return addr;
12649 abort ();
12650}
12651
a6c2a102
DE		 12652void
12653rs6000_fatal_bad_address (op)
12654 rtx op;
12655{
12656 fatal_insn ("bad address", op);
12657}
c8023011 12658
ee890fe2
SS		 12659#if TARGET_MACHO
12660
12661#if 0
12662/* Returns 1 if OP is either a symbol reference or a sum of a symbol
12663 reference and a constant. */
12664
12665int
12666symbolic_operand (op)
592696dd 12667 rtx op;
ee890fe2
SS		 12668{
12669 switch (GET_CODE (op))
12670 {
12671 case SYMBOL_REF:
12672 case LABEL_REF:
12673 return 1;
12674 case CONST:
12675 op = XEXP (op, 0);
12676 return (GET_CODE (op) == SYMBOL_REF ||
12677 (GET_CODE (XEXP (op, 0)) == SYMBOL_REF
12678 || GET_CODE (XEXP (op, 0)) == LABEL_REF)
12679 && GET_CODE (XEXP (op, 1)) == CONST_INT);
12680 default:
12681 return 0;
12682 }
c8023011 12683}
ee890fe2
SS		 12684#endif
12685
12686#ifdef RS6000_LONG_BRANCH
12687
12688static tree stub_list = 0;
12689
12690/* ADD_COMPILER_STUB adds the compiler generated stub for handling
12691 procedure calls to the linked list. */
12692
12693void
12694add_compiler_stub (label_name, function_name, line_number)
12695 tree label_name;
12696 tree function_name;
12697 int line_number;
12698{
12699 tree stub = build_tree_list (function_name, label_name);
12700 TREE_TYPE (stub) = build_int_2 (line_number, 0);
12701 TREE_CHAIN (stub) = stub_list;
12702 stub_list = stub;
12703}
12704
12705#define STUB_LABEL_NAME(STUB) TREE_VALUE (STUB)
12706#define STUB_FUNCTION_NAME(STUB) TREE_PURPOSE (STUB)
12707#define STUB_LINE_NUMBER(STUB) TREE_INT_CST_LOW (TREE_TYPE (STUB))
12708
a4f6c312
SS		 12709/* OUTPUT_COMPILER_STUB outputs the compiler generated stub for
12710 handling procedure calls from the linked list and initializes the
12711 linked list. */
ee890fe2 12712
a4f6c312
SS		 12713void
12714output_compiler_stub ()
ee890fe2
SS		 12715{
12716 char tmp_buf[256];
12717 char label_buf[256];
308c142a 12718 tree stub;
ee890fe2
SS		 12719
12720 if (!flag_pic)
12721 for (stub = stub_list; stub; stub = TREE_CHAIN (stub))
12722 {
12723 fprintf (asm_out_file,
12724 "%s:\n", IDENTIFIER_POINTER(STUB_LABEL_NAME(stub)));
12725
12726#if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
12727 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
12728 fprintf (asm_out_file, "\t.stabd 68,0,%d\n", STUB_LINE_NUMBER(stub));
12729#endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
12730
12731 if (IDENTIFIER_POINTER (STUB_FUNCTION_NAME (stub))[0] == '*')
12732 strcpy (label_buf,
12733 IDENTIFIER_POINTER (STUB_FUNCTION_NAME (stub))+1);
12734 else
12735 {
12736 label_buf[0] = '_';
12737 strcpy (label_buf+1,
12738 IDENTIFIER_POINTER (STUB_FUNCTION_NAME (stub)));
12739 }
12740
12741 strcpy (tmp_buf, "lis r12,hi16(");
12742 strcat (tmp_buf, label_buf);
12743 strcat (tmp_buf, ")\n\tori r12,r12,lo16(");
12744 strcat (tmp_buf, label_buf);
12745 strcat (tmp_buf, ")\n\tmtctr r12\n\tbctr");
12746 output_asm_insn (tmp_buf, 0);
12747
12748#if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
12749 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
12750 fprintf(asm_out_file, "\t.stabd 68,0,%d\n", STUB_LINE_NUMBER (stub));
12751#endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
12752 }
12753
12754 stub_list = 0;
12755}
12756
12757/* NO_PREVIOUS_DEF checks in the link list whether the function name is
12758 already there or not. */
12759
a4f6c312
SS		 12760int
12761no_previous_def (function_name)
ee890fe2
SS		 12762 tree function_name;
12763{
12764 tree stub;
12765 for (stub = stub_list; stub; stub = TREE_CHAIN (stub))
12766 if (function_name == STUB_FUNCTION_NAME (stub))
12767 return 0;
12768 return 1;
12769}
12770
12771/* GET_PREV_LABEL gets the label name from the previous definition of
12772 the function. */
12773
a4f6c312
SS		 12774tree
12775get_prev_label (function_name)
ee890fe2
SS		 12776 tree function_name;
12777{
12778 tree stub;
12779 for (stub = stub_list; stub; stub = TREE_CHAIN (stub))
12780 if (function_name == STUB_FUNCTION_NAME (stub))
12781 return STUB_LABEL_NAME (stub);
12782 return 0;
12783}
12784
12785/* INSN is either a function call or a millicode call. It may have an
12786 unconditional jump in its delay slot.
12787
12788 CALL_DEST is the routine we are calling. */
12789
12790char *
12791output_call (insn, call_dest, operand_number)
12792 rtx insn;
12793 rtx call_dest;
12794 int operand_number;
12795{
12796 static char buf[256];
12797 if (GET_CODE (call_dest) == SYMBOL_REF && TARGET_LONG_BRANCH && !flag_pic)
12798 {
12799 tree labelname;
12800 tree funname = get_identifier (XSTR (call_dest, 0));
12801
12802 if (no_previous_def (funname))
12803 {
308c142a 12804 int line_number = 0;
ee890fe2
SS		 12805 rtx label_rtx = gen_label_rtx ();
12806 char *label_buf, temp_buf[256];
12807 ASM_GENERATE_INTERNAL_LABEL (temp_buf, "L",
12808 CODE_LABEL_NUMBER (label_rtx));
12809 label_buf = temp_buf[0] == '*' ? temp_buf + 1 : temp_buf;
12810 labelname = get_identifier (label_buf);
12811 for (; insn && GET_CODE (insn) != NOTE; insn = PREV_INSN (insn));
12812 if (insn)
12813 line_number = NOTE_LINE_NUMBER (insn);
12814 add_compiler_stub (labelname, funname, line_number);
12815 }
12816 else
12817 labelname = get_prev_label (funname);
12818
12819 sprintf (buf, "jbsr %%z%d,%.246s",
12820 operand_number, IDENTIFIER_POINTER (labelname));
12821 return buf;
12822 }
12823 else
12824 {
12825 sprintf (buf, "bl %%z%d", operand_number);
12826 return buf;
12827 }
12828}
12829
12830#endif /* RS6000_LONG_BRANCH */
12831
12832#define GEN_LOCAL_LABEL_FOR_SYMBOL(BUF,SYMBOL,LENGTH,N) \
12833 do { \
83182544 12834 const char *const symbol_ = (SYMBOL); \
ee890fe2
SS		 12835 char *buffer_ = (BUF); \
12836 if (symbol_[0] == '"') \
12837 { \
12838 sprintf(buffer_, "\"L%d$%s", (N), symbol_+1); \
12839 } \
12840 else if (name_needs_quotes(symbol_)) \
12841 { \
12842 sprintf(buffer_, "\"L%d$%s\"", (N), symbol_); \
12843 } \
12844 else \
12845 { \
12846 sprintf(buffer_, "L%d$%s", (N), symbol_); \
12847 } \
12848 } while (0)
12849
12850
12851/* Generate PIC and indirect symbol stubs. */
12852
12853void
12854machopic_output_stub (file, symb, stub)
12855 FILE *file;
12856 const char *symb, *stub;
12857{
12858 unsigned int length;
a4f6c312
SS		 12859 char *symbol_name, *lazy_ptr_name;
12860 char *local_label_0;
ee890fe2
SS		 12861 static int label = 0;
12862
df56a27f 12863 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
772c5265 12864 symb = (*targetm.strip_name_encoding) (symb);
df56a27f 12865
ee890fe2
SS		 12866 label += 1;
12867
ee890fe2
SS		 12868 length = strlen (symb);
12869 symbol_name = alloca (length + 32);
12870 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length);
12871
12872 lazy_ptr_name = alloca (length + 32);
12873 GEN_LAZY_PTR_NAME_FOR_SYMBOL (lazy_ptr_name, symb, length);
12874
12875 local_label_0 = alloca (length + 32);
12876 GEN_LOCAL_LABEL_FOR_SYMBOL (local_label_0, symb, length, 0);
12877
ee890fe2 12878 if (flag_pic == 2)
d3c300d2 12879 machopic_picsymbol_stub1_section ();
ee890fe2 12880 else
d3c300d2
DJ		 12881 machopic_symbol_stub1_section ();
12882 fprintf (file, "\t.align 2\n");
ee890fe2
SS		 12883
12884 fprintf (file, "%s:\n", stub);
12885 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
12886
12887 if (flag_pic == 2)
12888 {
12889 fprintf (file, "\tmflr r0\n");
12890 fprintf (file, "\tbcl 20,31,%s\n", local_label_0);
12891 fprintf (file, "%s:\n\tmflr r11\n", local_label_0);
12892 fprintf (file, "\taddis r11,r11,ha16(%s-%s)\n",
12893 lazy_ptr_name, local_label_0);
12894 fprintf (file, "\tmtlr r0\n");
d3c300d2 12895 fprintf (file, "\tlwzu r12,lo16(%s-%s)(r11)\n",
ee890fe2
SS		 12896 lazy_ptr_name, local_label_0);
12897 fprintf (file, "\tmtctr r12\n");
ee890fe2
SS		 12898 fprintf (file, "\tbctr\n");
12899 }
12900 else
12901 fprintf (file, "non-pure not supported\n");
12902
12903 machopic_lazy_symbol_ptr_section ();
12904 fprintf (file, "%s:\n", lazy_ptr_name);
12905 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
12906 fprintf (file, "\t.long dyld_stub_binding_helper\n");
12907}
12908
12909/* Legitimize PIC addresses. If the address is already
12910 position-independent, we return ORIG. Newly generated
12911 position-independent addresses go into a reg. This is REG if non
12912 zero, otherwise we allocate register(s) as necessary. */
12913
c859cda6 12914#define SMALL_INT(X) ((unsigned) (INTVAL(X) + 0x8000) < 0x10000)
ee890fe2
SS		 12915
12916rtx
12917rs6000_machopic_legitimize_pic_address (orig, mode, reg)
12918 rtx orig;
12919 enum machine_mode mode;
12920 rtx reg;
12921{
12922 rtx base, offset;
12923
12924 if (reg == NULL && ! reload_in_progress && ! reload_completed)
12925 reg = gen_reg_rtx (Pmode);
12926
12927 if (GET_CODE (orig) == CONST)
12928 {
12929 if (GET_CODE (XEXP (orig, 0)) == PLUS
12930 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
12931 return orig;
12932
12933 if (GET_CODE (XEXP (orig, 0)) == PLUS)
12934 {
a4f6c312
SS		 12935 base =
12936 rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 0),
12937 Pmode, reg);
12938 offset =
12939 rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 1),
12940 Pmode, reg);
ee890fe2
SS		 12941 }
12942 else
12943 abort ();
12944
12945 if (GET_CODE (offset) == CONST_INT)
12946 {
12947 if (SMALL_INT (offset))
ed8908e7 12948 return plus_constant (base, INTVAL (offset));
ee890fe2
SS		 12949 else if (! reload_in_progress && ! reload_completed)
12950 offset = force_reg (Pmode, offset);
12951 else
c859cda6
DJ		 12952 {
12953 rtx mem = force_const_mem (Pmode, orig);
12954 return machopic_legitimize_pic_address (mem, Pmode, reg);
12955 }
ee890fe2
SS		 12956 }
12957 return gen_rtx (PLUS, Pmode, base, offset);
12958 }
12959
12960 /* Fall back on generic machopic code. */
12961 return machopic_legitimize_pic_address (orig, mode, reg);
12962}
12963
12964/* This is just a placeholder to make linking work without having to
12965 add this to the generic Darwin EXTRA_SECTIONS. If -mcall-aix is
12966 ever needed for Darwin (not too likely!) this would have to get a
12967 real definition. */
12968
12969void
12970toc_section ()
12971{
12972}
12973
12974#endif /* TARGET_MACHO */
7c262518
RH		 12975
12976#if TARGET_ELF
12977static unsigned int
12978rs6000_elf_section_type_flags (decl, name, reloc)
12979 tree decl;
12980 const char *name;
12981 int reloc;
12982{
5add3202
DE		 12983 unsigned int flags
12984 = default_section_type_flags_1 (decl, name, reloc,
12985 flag_pic || DEFAULT_ABI == ABI_AIX);
7c262518 12986
270fc29b
RH		 12987 if (TARGET_RELOCATABLE)
12988 flags |= SECTION_WRITE;
7c262518 12989
d0101753 12990 return flags;
7c262518 12991}
d9f6800d
RH		 12992
12993/* Record an element in the table of global constructors. SYMBOL is
12994 a SYMBOL_REF of the function to be called; PRIORITY is a number
12995 between 0 and MAX_INIT_PRIORITY.
12996
12997 This differs from default_named_section_asm_out_constructor in
12998 that we have special handling for -mrelocatable. */
12999
13000static void
13001rs6000_elf_asm_out_constructor (symbol, priority)
13002 rtx symbol;
13003 int priority;
13004{
13005 const char *section = ".ctors";
13006 char buf[16];
13007
13008 if (priority != DEFAULT_INIT_PRIORITY)
13009 {
13010 sprintf (buf, ".ctors.%.5u",
13011 /* Invert the numbering so the linker puts us in the proper
13012 order; constructors are run from right to left, and the
13013 linker sorts in increasing order. */
13014 MAX_INIT_PRIORITY - priority);
13015 section = buf;
13016 }
13017
715bdd29
RH		 13018 named_section_flags (section, SECTION_WRITE);
13019 assemble_align (POINTER_SIZE);
d9f6800d
RH		 13020
13021 if (TARGET_RELOCATABLE)
13022 {
13023 fputs ("\t.long (", asm_out_file);
13024 output_addr_const (asm_out_file, symbol);
13025 fputs (")@fixup\n", asm_out_file);
13026 }
13027 else
c8af3574 13028 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
d9f6800d
RH		 13029}
13030
13031static void
13032rs6000_elf_asm_out_destructor (symbol, priority)
13033 rtx symbol;
13034 int priority;
13035{
13036 const char *section = ".dtors";
13037 char buf[16];
13038
13039 if (priority != DEFAULT_INIT_PRIORITY)
13040 {
13041 sprintf (buf, ".dtors.%.5u",
13042 /* Invert the numbering so the linker puts us in the proper
13043 order; constructors are run from right to left, and the
13044 linker sorts in increasing order. */
13045 MAX_INIT_PRIORITY - priority);
13046 section = buf;
13047 }
13048
715bdd29
RH		 13049 named_section_flags (section, SECTION_WRITE);
13050 assemble_align (POINTER_SIZE);
d9f6800d
RH		 13051
13052 if (TARGET_RELOCATABLE)
13053 {
13054 fputs ("\t.long (", asm_out_file);
13055 output_addr_const (asm_out_file, symbol);
13056 fputs (")@fixup\n", asm_out_file);
13057 }
13058 else
c8af3574 13059 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
d9f6800d 13060}
7c262518
RH		 13061#endif
13062
cbaaba19 13063#if TARGET_XCOFF
7c262518 13064static void
b275d088
DE		 13065rs6000_xcoff_asm_globalize_label (stream, name)
13066 FILE *stream;
13067 const char *name;
13068{
13069 fputs (GLOBAL_ASM_OP, stream);
13070 RS6000_OUTPUT_BASENAME (stream, name);
13071 putc ('\n', stream);
13072}
13073
13074static void
13075rs6000_xcoff_asm_named_section (name, flags)
7c262518 13076 const char *name;
0e5dbd9b 13077 unsigned int flags;
7c262518 13078{
0e5dbd9b
DE		 13079 int smclass;
13080 static const char * const suffix[3] = { "PR", "RO", "RW" };
13081
13082 if (flags & SECTION_CODE)
13083 smclass = 0;
13084 else if (flags & SECTION_WRITE)
13085 smclass = 2;
13086 else
13087 smclass = 1;
13088
5b5198f7 13089 fprintf (asm_out_file, "\t.csect %s%s[%s],%u\n",
0e5dbd9b 13090 (flags & SECTION_CODE) ? "." : "",
5b5198f7 13091 name, suffix[smclass], flags & SECTION_ENTSIZE);
7c262518 13092}
ae46c4e0
RH		 13093
13094static void
0e5dbd9b
DE		 13095rs6000_xcoff_select_section (decl, reloc, align)
13096 tree decl;
ae46c4e0
RH		 13097 int reloc;
13098 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED;
13099{
5add3202 13100 if (decl_readonly_section_1 (decl, reloc, 1))
ae46c4e0 13101 {
0e5dbd9b 13102 if (TREE_PUBLIC (decl))
ae46c4e0
RH		 13103 read_only_data_section ();
13104 else
13105 read_only_private_data_section ();
13106 }
13107 else
13108 {
0e5dbd9b 13109 if (TREE_PUBLIC (decl))
ae46c4e0
RH		 13110 data_section ();
13111 else
13112 private_data_section ();
13113 }
13114}
13115
13116static void
13117rs6000_xcoff_unique_section (decl, reloc)
13118 tree decl;
772c5265 13119 int reloc ATTRIBUTE_UNUSED;
ae46c4e0
RH		 13120{
13121 const char *name;
ae46c4e0 13122
5b5198f7
DE		 13123 /* Use select_section for private and uninitialized data. */
13124 if (!TREE_PUBLIC (decl)
13125 || DECL_COMMON (decl)
0e5dbd9b
DE		 13126 || DECL_INITIAL (decl) == NULL_TREE
13127 || DECL_INITIAL (decl) == error_mark_node
13128 || (flag_zero_initialized_in_bss
13129 && initializer_zerop (DECL_INITIAL (decl))))
13130 return;
13131
13132 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
13133 name = (*targetm.strip_name_encoding) (name);
13134 DECL_SECTION_NAME (decl) = build_string (strlen (name), name);
ae46c4e0 13135}
b64a1b53 13136
fb49053f
RH		 13137/* Select section for constant in constant pool.
13138
13139 On RS/6000, all constants are in the private read-only data area.
13140 However, if this is being placed in the TOC it must be output as a
13141 toc entry. */
13142
b64a1b53
RH		 13143static void
13144rs6000_xcoff_select_rtx_section (mode, x, align)
13145 enum machine_mode mode;
13146 rtx x;
13147 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED;
13148{
13149 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
13150 toc_section ();
13151 else
13152 read_only_private_data_section ();
13153}
772c5265
RH		 13154
13155/* Remove any trailing [DS] or the like from the symbol name. */
13156
13157static const char *
13158rs6000_xcoff_strip_name_encoding (name)
13159 const char *name;
13160{
13161 size_t len;
13162 if (*name == '*')
13163 name++;
13164 len = strlen (name);
13165 if (name[len - 1] == ']')
13166 return ggc_alloc_string (name, len - 4);
13167 else
13168 return name;
13169}
13170
5add3202
DE		 13171/* Section attributes. AIX is always PIC. */
13172
13173static unsigned int
13174rs6000_xcoff_section_type_flags (decl, name, reloc)
13175 tree decl;
13176 const char *name;
13177 int reloc;
13178{
5b5198f7
DE		 13179 unsigned int align;
13180 unsigned int flags = default_section_type_flags_1 (decl, name, reloc, 1);
13181
13182 /* Align to at least UNIT size. */
13183 if (flags & SECTION_CODE)
13184 align = MIN_UNITS_PER_WORD;
13185 else
13186 /* Increase alignment of large objects if not already stricter. */
13187 align = MAX ((DECL_ALIGN (decl) / BITS_PER_UNIT),
13188 int_size_in_bytes (TREE_TYPE (decl)) > MIN_UNITS_PER_WORD
13189 ? UNITS_PER_FP_WORD : MIN_UNITS_PER_WORD);
13190
13191 return flags | (exact_log2 (align) & SECTION_ENTSIZE);
5add3202
DE		 13192}
13193
cbaaba19 13194#endif /* TARGET_XCOFF */
fb49053f 13195
0e5dbd9b 13196/* Note that this is also used for PPC64 Linux. */
fb49053f
RH		 13197
13198static void
13199rs6000_xcoff_encode_section_info (decl, first)
13200 tree decl;
13201 int first ATTRIBUTE_UNUSED;
13202{
13203 if (TREE_CODE (decl) == FUNCTION_DECL
b629ba0c 13204 && (*targetm.binds_local_p) (decl))
fb49053f
RH		 13205 SYMBOL_REF_FLAG (XEXP (DECL_RTL (decl), 0)) = 1;
13206}
0e5dbd9b
DE		 13207
13208/* Cross-module name binding. For AIX and PPC64 Linux, which always are
13209 PIC, use private copy of flag_pic. */
13210
2bcc50d0 13211static bool
0e5dbd9b
DE		 13212rs6000_binds_local_p (decl)
13213 tree decl;
13214{
5add3202 13215 return default_binds_local_p_1 (decl, flag_pic || rs6000_flag_pic);
0e5dbd9b 13216}
34bb030a
DE		 13217
13218/* A C expression returning the cost of moving data from a register of class
13219 CLASS1 to one of CLASS2. */
13220
13221int
13222rs6000_register_move_cost (mode, from, to)
13223 enum machine_mode mode;
13224 enum reg_class from, to;
13225{
13226 /* Moves from/to GENERAL_REGS. */
13227 if (reg_classes_intersect_p (to, GENERAL_REGS)
13228 || reg_classes_intersect_p (from, GENERAL_REGS))
13229 {
13230 if (! reg_classes_intersect_p (to, GENERAL_REGS))
13231 from = to;
13232
13233 if (from == FLOAT_REGS || from == ALTIVEC_REGS)
13234 return (rs6000_memory_move_cost (mode, from, 0)
13235 + rs6000_memory_move_cost (mode, GENERAL_REGS, 0));
13236
13237/* It's more expensive to move CR_REGS than CR0_REGS because of the shift...*/
13238 else if (from == CR_REGS)
13239 return 4;
13240
13241 else
13242/* A move will cost one instruction per GPR moved. */
13243 return 2 * HARD_REGNO_NREGS (0, mode);
13244 }
13245
13246/* Moving between two similar registers is just one instruction. */
13247 else if (reg_classes_intersect_p (to, from))
13248 return mode == TFmode ? 4 : 2;
13249
13250/* Everything else has to go through GENERAL_REGS. */
13251 else
13252 return (rs6000_register_move_cost (mode, GENERAL_REGS, to)
13253 + rs6000_register_move_cost (mode, from, GENERAL_REGS));
13254}
13255
13256/* A C expressions returning the cost of moving data of MODE from a register to
13257 or from memory. */
13258
13259int
13260rs6000_memory_move_cost (mode, class, in)
13261 enum machine_mode mode;
13262 enum reg_class class;
13263 int in ATTRIBUTE_UNUSED;
13264{
13265 if (reg_classes_intersect_p (class, GENERAL_REGS))
13266 return 4 * HARD_REGNO_NREGS (0, mode);
13267 else if (reg_classes_intersect_p (class, FLOAT_REGS))
13268 return 4 * HARD_REGNO_NREGS (32, mode);
13269 else if (reg_classes_intersect_p (class, ALTIVEC_REGS))
13270 return 4 * HARD_REGNO_NREGS (FIRST_ALTIVEC_REGNO, mode);
13271 else
13272 return 4 + rs6000_register_move_cost (mode, class, GENERAL_REGS);
13273}
13274
17211ab5 13275#include "gt-rs6000.h"
GNU Compiler Collection
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