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Commit | Line | Data |
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9878760c | 1 | /* Subroutines used for code generation on IBM RS/6000. |
fab3bcc3 RK |
2 | Copyright (C) 1991, 1993, 1994 Free Software Foundation, Inc. |
3 | Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) | |
9878760c RK |
4 | |
5 | This file is part of GNU CC. | |
6 | ||
7 | GNU CC is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2, or (at your option) | |
10 | any later version. | |
11 | ||
12 | GNU CC is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GNU CC; see the file COPYING. If not, write to | |
19 | the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ | |
20 | ||
21 | #include <stdio.h> | |
22 | #include "config.h" | |
23 | #include "rtl.h" | |
24 | #include "regs.h" | |
25 | #include "hard-reg-set.h" | |
26 | #include "real.h" | |
27 | #include "insn-config.h" | |
28 | #include "conditions.h" | |
29 | #include "insn-flags.h" | |
30 | #include "output.h" | |
31 | #include "insn-attr.h" | |
32 | #include "flags.h" | |
33 | #include "recog.h" | |
34 | #include "expr.h" | |
35 | #include "obstack.h" | |
9b30bae2 JW |
36 | #include "tree.h" |
37 | ||
38 | extern char *language_string; | |
5248c961 | 39 | extern int profile_block_flag; |
9878760c RK |
40 | |
41 | #define min(A,B) ((A) < (B) ? (A) : (B)) | |
42 | #define max(A,B) ((A) > (B) ? (A) : (B)) | |
43 | ||
5248c961 RK |
44 | /* Target cpu type */ |
45 | ||
46 | enum processor_type rs6000_cpu; | |
47 | char *rs6000_cpu_string; | |
48 | ||
9878760c RK |
49 | /* Set to non-zero by "fix" operation to indicate that itrunc and |
50 | uitrunc must be defined. */ | |
51 | ||
52 | int rs6000_trunc_used; | |
53 | ||
54 | /* Set to non-zero once they have been defined. */ | |
55 | ||
56 | static int trunc_defined; | |
57 | ||
c764f757 RK |
58 | /* Set to non-zero once AIX common-mode calls have been defined. */ |
59 | static int common_mode_defined; | |
9878760c RK |
60 | /* Save information from a "cmpxx" operation until the branch or scc is |
61 | emitted. */ | |
62 | ||
63 | rtx rs6000_compare_op0, rs6000_compare_op1; | |
64 | int rs6000_compare_fp_p; | |
65 | \f | |
5248c961 RK |
66 | /* Override command line options. Mostly we process the processor |
67 | type and sometimes adjust other TARGET_ options. */ | |
68 | ||
69 | void | |
70 | rs6000_override_options () | |
71 | { | |
72 | int i; | |
73 | ||
85638c0d RK |
74 | /* Simplify the entries below by making a mask for any POWER |
75 | variant and any PowerPC variant. */ | |
76 | ||
77 | #define POWER_MASKS (MASK_POWER | MASK_POWER2) | |
fab3bcc3 | 78 | #define POWERPC_MASKS (MASK_POWERPC | MASK_PPCFPX | MASK_POWERPC64) |
85638c0d | 79 | |
5248c961 RK |
80 | static struct ptt |
81 | { | |
82 | char *name; /* Canonical processor name. */ | |
83 | enum processor_type processor; /* Processor type enum value. */ | |
84 | int target_enable; /* Target flags to enable. */ | |
85 | int target_disable; /* Target flags to disable. */ | |
86 | } processor_target_table[] | |
db7f1e43 RK |
87 | = {{"common", PROCESSOR_COMMON, 0, POWER_MASKS | POWERPC_MASKS}, |
88 | {"power", PROCESSOR_POWER, | |
89 | MASK_POWER, | |
90 | MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS}, | |
91 | {"powerpc", PROCESSOR_POWERPC, | |
92 | MASK_POWERPC | MASK_NEW_MNEMONICS, | |
93 | POWER_MASKS | MASK_PPCFPX | MASK_POWERPC64}, | |
94 | {"rios", PROCESSOR_RIOS1, | |
95 | MASK_POWER, | |
96 | MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS}, | |
97 | {"rios1", PROCESSOR_RIOS1, | |
98 | MASK_POWER, | |
99 | MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS}, | |
100 | {"rsc", PROCESSOR_PPC601, | |
101 | MASK_POWER, | |
102 | MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS}, | |
103 | {"rsc1", PROCESSOR_PPC601, | |
104 | MASK_POWER, | |
105 | MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS}, | |
106 | {"rios2", PROCESSOR_RIOS2, | |
107 | MASK_POWER | MASK_POWER2, | |
108 | POWERPC_MASKS | MASK_NEW_MNEMONICS}, | |
5248c961 | 109 | {"601", PROCESSOR_PPC601, |
85638c0d | 110 | MASK_POWER | MASK_POWERPC | MASK_NEW_MNEMONICS, |
fab3bcc3 | 111 | MASK_POWER2 | MASK_PPCFPX | MASK_POWERPC64}, |
49947f18 | 112 | {"mpc601", PROCESSOR_PPC601, |
85638c0d | 113 | MASK_POWER | MASK_POWERPC | MASK_NEW_MNEMONICS, |
fab3bcc3 | 114 | MASK_POWER2 | MASK_PPCFPX | MASK_POWERPC64}, |
85638c0d RK |
115 | {"ppc601", PROCESSOR_PPC601, |
116 | MASK_POWER | MASK_POWERPC | MASK_NEW_MNEMONICS, | |
fab3bcc3 | 117 | MASK_POWER2 | MASK_PPCFPX | MASK_POWERPC64}, |
5248c961 | 118 | {"603", PROCESSOR_PPC603, |
fab3bcc3 | 119 | MASK_POWERPC | MASK_PPCFPX | MASK_NEW_MNEMONICS, |
85638c0d | 120 | POWER_MASKS | MASK_POWERPC64}, |
49947f18 | 121 | {"mpc603", PROCESSOR_PPC603, |
fab3bcc3 | 122 | MASK_POWERPC | MASK_PPCFPX | MASK_NEW_MNEMONICS, |
85638c0d RK |
123 | POWER_MASKS | MASK_POWERPC64}, |
124 | {"ppc603", PROCESSOR_PPC603, | |
fab3bcc3 | 125 | MASK_POWERPC | MASK_PPCFPX | MASK_NEW_MNEMONICS, |
85638c0d | 126 | POWER_MASKS | MASK_POWERPC64}, |
5248c961 | 127 | {"604", PROCESSOR_PPC604, |
fab3bcc3 | 128 | MASK_POWERPC | MASK_PPCFPX | MASK_NEW_MNEMONICS, |
85638c0d | 129 | POWER_MASKS | MASK_POWERPC64}, |
49947f18 | 130 | {"mpc604", PROCESSOR_PPC604, |
fab3bcc3 | 131 | MASK_POWERPC | MASK_PPCFPX | MASK_NEW_MNEMONICS, |
85638c0d RK |
132 | POWER_MASKS | MASK_POWERPC64}, |
133 | {"ppc604", PROCESSOR_PPC604, | |
fab3bcc3 | 134 | MASK_POWERPC | MASK_PPCFPX | MASK_NEW_MNEMONICS, |
85638c0d | 135 | POWER_MASKS | MASK_POWERPC64}, |
5248c961 | 136 | {"620", PROCESSOR_PPC620, |
fab3bcc3 | 137 | (MASK_POWERPC | MASK_PPCFPX | MASK_POWERPC64 |
85638c0d RK |
138 | | MASK_NEW_MNEMONICS), |
139 | POWER_MASKS}, | |
49947f18 | 140 | {"mpc620", PROCESSOR_PPC620, |
fab3bcc3 | 141 | (MASK_POWERPC | MASK_PPCFPX | MASK_POWERPC64 |
85638c0d RK |
142 | | MASK_NEW_MNEMONICS), |
143 | POWER_MASKS}, | |
144 | {"ppc620", PROCESSOR_PPC620, | |
fab3bcc3 | 145 | (MASK_POWERPC | MASK_PPCFPX | MASK_POWERPC64 |
85638c0d RK |
146 | | MASK_NEW_MNEMONICS), |
147 | POWER_MASKS}}; | |
5248c961 RK |
148 | |
149 | int ptt_size = sizeof (processor_target_table) / sizeof (struct ptt); | |
150 | ||
151 | profile_block_flag = 0; | |
152 | ||
153 | /* Identify the processor type */ | |
154 | if (rs6000_cpu_string == 0) | |
155 | rs6000_cpu = PROCESSOR_DEFAULT; | |
156 | else | |
157 | { | |
158 | for (i = 0; i < ptt_size; i++) | |
159 | if (! strcmp (rs6000_cpu_string, processor_target_table[i].name)) | |
160 | { | |
161 | rs6000_cpu = processor_target_table[i].processor; | |
162 | target_flags |= processor_target_table[i].target_enable; | |
163 | target_flags &= ~processor_target_table[i].target_disable; | |
164 | break; | |
165 | } | |
166 | ||
167 | if (i == ptt_size) | |
168 | { | |
169 | error ("bad value (%s) for -mcpu= switch", rs6000_cpu_string); | |
170 | rs6000_cpu_string = "default"; | |
171 | rs6000_cpu = PROCESSOR_DEFAULT; | |
172 | } | |
173 | } | |
174 | } | |
175 | \f | |
0cd30143 RK |
176 | /* Look for an PRE_INC address in X that are marked as dying in INSN. |
177 | Convert the addresses to a PLUS form if one is found. */ | |
178 | ||
179 | void | |
180 | rs6000_convert_preincs (x, insn) | |
181 | rtx x; | |
182 | rtx insn; | |
183 | { | |
184 | enum rtx_code code = GET_CODE (x); | |
185 | char *fmt; | |
186 | int i, j; | |
187 | ||
188 | if (code == MEM && GET_CODE (XEXP (x, 0)) == PRE_INC | |
189 | && find_reg_note (insn, REG_DEAD, XEXP (XEXP (x, 0), 0))) | |
190 | XEXP (x, 0) = plus_constant (XEXP (XEXP (x, 0), 0), | |
191 | GET_MODE_SIZE (GET_MODE (x))); | |
192 | else | |
193 | for (i = GET_RTX_LENGTH (code) - 1, fmt = GET_RTX_FORMAT (code); | |
194 | i >= 0; i--) | |
195 | { | |
196 | if (fmt[i] == 'e') | |
197 | rs6000_convert_preincs (XEXP (x, i), insn); | |
198 | else if (fmt[i] == 'E') | |
199 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
200 | rs6000_convert_preincs (XVECEXP (x, i, j), insn); | |
201 | } | |
202 | } | |
203 | \f | |
9878760c RK |
204 | /* Return non-zero if this function is known to have a null epilogue. */ |
205 | ||
206 | int | |
207 | direct_return () | |
208 | { | |
209 | return (reload_completed | |
210 | && first_reg_to_save () == 32 | |
211 | && first_fp_reg_to_save () == 64 | |
212 | && ! regs_ever_live[65] | |
213 | && ! rs6000_pushes_stack ()); | |
214 | } | |
215 | ||
216 | /* Returns 1 always. */ | |
217 | ||
218 | int | |
219 | any_operand (op, mode) | |
220 | register rtx op; | |
221 | enum machine_mode mode; | |
222 | { | |
223 | return 1; | |
224 | } | |
225 | ||
226 | /* Return 1 if OP is a constant that can fit in a D field. */ | |
227 | ||
228 | int | |
229 | short_cint_operand (op, mode) | |
230 | register rtx op; | |
231 | enum machine_mode mode; | |
232 | { | |
233 | return (GET_CODE (op) == CONST_INT | |
234 | && (unsigned) (INTVAL (op) + 0x8000) < 0x10000); | |
235 | } | |
236 | ||
237 | /* Similar for a unsigned D field. */ | |
238 | ||
239 | int | |
240 | u_short_cint_operand (op, mode) | |
241 | register rtx op; | |
242 | enum machine_mode mode; | |
243 | { | |
244 | return (GET_CODE (op) == CONST_INT && (INTVAL (op) & 0xffff0000) == 0); | |
245 | } | |
246 | ||
dcfedcd0 RK |
247 | /* Return 1 if OP is a CONST_INT that cannot fit in a signed D field. */ |
248 | ||
249 | int | |
250 | non_short_cint_operand (op, mode) | |
251 | register rtx op; | |
252 | enum machine_mode mode; | |
253 | { | |
254 | return (GET_CODE (op) == CONST_INT | |
255 | && (unsigned) (INTVAL (op) + 0x8000) >= 0x10000); | |
256 | } | |
257 | ||
9878760c RK |
258 | /* Returns 1 if OP is a register that is not special (i.e., not MQ, |
259 | ctr, or lr). */ | |
260 | ||
261 | int | |
cd2b37d9 | 262 | gpc_reg_operand (op, mode) |
9878760c RK |
263 | register rtx op; |
264 | enum machine_mode mode; | |
265 | { | |
266 | return (register_operand (op, mode) | |
267 | && (GET_CODE (op) != REG || REGNO (op) >= 67 || REGNO (op) < 64)); | |
268 | } | |
269 | ||
270 | /* Returns 1 if OP is either a pseudo-register or a register denoting a | |
271 | CR field. */ | |
272 | ||
273 | int | |
274 | cc_reg_operand (op, mode) | |
275 | register rtx op; | |
276 | enum machine_mode mode; | |
277 | { | |
278 | return (register_operand (op, mode) | |
279 | && (GET_CODE (op) != REG | |
280 | || REGNO (op) >= FIRST_PSEUDO_REGISTER | |
281 | || CR_REGNO_P (REGNO (op)))); | |
282 | } | |
283 | ||
284 | /* Returns 1 if OP is either a constant integer valid for a D-field or a | |
285 | non-special register. If a register, it must be in the proper mode unless | |
286 | MODE is VOIDmode. */ | |
287 | ||
288 | int | |
289 | reg_or_short_operand (op, mode) | |
290 | register rtx op; | |
291 | enum machine_mode mode; | |
292 | { | |
f5a28898 | 293 | return short_cint_operand (op, mode) || gpc_reg_operand (op, mode); |
9878760c RK |
294 | } |
295 | ||
296 | /* Similar, except check if the negation of the constant would be valid for | |
297 | a D-field. */ | |
298 | ||
299 | int | |
300 | reg_or_neg_short_operand (op, mode) | |
301 | register rtx op; | |
302 | enum machine_mode mode; | |
303 | { | |
304 | if (GET_CODE (op) == CONST_INT) | |
305 | return CONST_OK_FOR_LETTER_P (INTVAL (op), 'P'); | |
306 | ||
cd2b37d9 | 307 | return gpc_reg_operand (op, mode); |
9878760c RK |
308 | } |
309 | ||
310 | /* Return 1 if the operand is either a register or an integer whose high-order | |
311 | 16 bits are zero. */ | |
312 | ||
313 | int | |
314 | reg_or_u_short_operand (op, mode) | |
315 | register rtx op; | |
316 | enum machine_mode mode; | |
317 | { | |
318 | if (GET_CODE (op) == CONST_INT | |
319 | && (INTVAL (op) & 0xffff0000) == 0) | |
320 | return 1; | |
321 | ||
cd2b37d9 | 322 | return gpc_reg_operand (op, mode); |
9878760c RK |
323 | } |
324 | ||
325 | /* Return 1 is the operand is either a non-special register or ANY | |
326 | constant integer. */ | |
327 | ||
328 | int | |
329 | reg_or_cint_operand (op, mode) | |
330 | register rtx op; | |
331 | enum machine_mode mode; | |
332 | { | |
cd2b37d9 | 333 | return GET_CODE (op) == CONST_INT || gpc_reg_operand (op, mode); |
9878760c RK |
334 | } |
335 | ||
6f2f8311 RK |
336 | /* Return 1 if the operand is a CONST_DOUBLE and it can be put into a register |
337 | with one instruction per word. We only do this if we can safely read | |
338 | CONST_DOUBLE_{LOW,HIGH}. */ | |
9878760c RK |
339 | |
340 | int | |
341 | easy_fp_constant (op, mode) | |
342 | register rtx op; | |
343 | register enum machine_mode mode; | |
344 | { | |
345 | rtx low, high; | |
346 | ||
347 | if (GET_CODE (op) != CONST_DOUBLE | |
348 | || GET_MODE (op) != mode | |
349 | || GET_MODE_CLASS (mode) != MODE_FLOAT) | |
350 | return 0; | |
351 | ||
352 | high = operand_subword (op, 0, 0, mode); | |
353 | low = operand_subword (op, 1, 0, mode); | |
354 | ||
6f2f8311 | 355 | if (high == 0 || ! input_operand (high, word_mode)) |
9878760c RK |
356 | return 0; |
357 | ||
358 | return (mode == SFmode | |
6f2f8311 | 359 | || (low != 0 && input_operand (low, word_mode))); |
9878760c RK |
360 | } |
361 | ||
362 | /* Return 1 if the operand is either a floating-point register, a pseudo | |
363 | register, or memory. */ | |
364 | ||
365 | int | |
366 | fp_reg_or_mem_operand (op, mode) | |
367 | register rtx op; | |
368 | enum machine_mode mode; | |
369 | { | |
370 | return (memory_operand (op, mode) | |
371 | || (register_operand (op, mode) | |
372 | && (GET_CODE (op) != REG | |
373 | || REGNO (op) >= FIRST_PSEUDO_REGISTER | |
374 | || FP_REGNO_P (REGNO (op))))); | |
375 | } | |
376 | ||
377 | /* Return 1 if the operand is either an easy FP constant (see above) or | |
378 | memory. */ | |
379 | ||
380 | int | |
381 | mem_or_easy_const_operand (op, mode) | |
382 | register rtx op; | |
383 | enum machine_mode mode; | |
384 | { | |
385 | return memory_operand (op, mode) || easy_fp_constant (op, mode); | |
386 | } | |
387 | ||
388 | /* Return 1 if the operand is either a non-special register or an item | |
389 | that can be used as the operand of an SI add insn. */ | |
390 | ||
391 | int | |
392 | add_operand (op, mode) | |
393 | register rtx op; | |
394 | enum machine_mode mode; | |
395 | { | |
396 | return (reg_or_short_operand (op, mode) | |
397 | || (GET_CODE (op) == CONST_INT && (INTVAL (op) & 0xffff) == 0)); | |
398 | } | |
399 | ||
dcfedcd0 RK |
400 | /* Return 1 if OP is a constant but not a valid add_operand. */ |
401 | ||
402 | int | |
403 | non_add_cint_operand (op, mode) | |
404 | register rtx op; | |
405 | enum machine_mode mode; | |
406 | { | |
407 | return (GET_CODE (op) == CONST_INT | |
408 | && (unsigned) (INTVAL (op) + 0x8000) >= 0x10000 | |
409 | && (INTVAL (op) & 0xffff) != 0); | |
410 | } | |
411 | ||
9878760c RK |
412 | /* Return 1 if the operand is a non-special register or a constant that |
413 | can be used as the operand of an OR or XOR insn on the RS/6000. */ | |
414 | ||
415 | int | |
416 | logical_operand (op, mode) | |
417 | register rtx op; | |
418 | enum machine_mode mode; | |
419 | { | |
cd2b37d9 | 420 | return (gpc_reg_operand (op, mode) |
9878760c RK |
421 | || (GET_CODE (op) == CONST_INT |
422 | && ((INTVAL (op) & 0xffff0000) == 0 | |
423 | || (INTVAL (op) & 0xffff) == 0))); | |
424 | } | |
425 | ||
dcfedcd0 RK |
426 | /* Return 1 if C is a constant that is not a logical operand (as |
427 | above). */ | |
428 | ||
429 | int | |
430 | non_logical_cint_operand (op, mode) | |
431 | register rtx op; | |
432 | enum machine_mode mode; | |
433 | { | |
434 | return (GET_CODE (op) == CONST_INT | |
435 | && (INTVAL (op) & 0xffff0000) != 0 | |
436 | && (INTVAL (op) & 0xffff) != 0); | |
437 | } | |
438 | ||
9878760c RK |
439 | /* Return 1 if C is a constant that can be encoded in a mask on the |
440 | RS/6000. It is if there are no more than two 1->0 or 0->1 transitions. | |
441 | Reject all ones and all zeros, since these should have been optimized | |
442 | away and confuse the making of MB and ME. */ | |
443 | ||
444 | int | |
445 | mask_constant (c) | |
446 | register int c; | |
447 | { | |
448 | int i; | |
449 | int last_bit_value; | |
450 | int transitions = 0; | |
451 | ||
452 | if (c == 0 || c == ~0) | |
453 | return 0; | |
454 | ||
455 | last_bit_value = c & 1; | |
456 | ||
457 | for (i = 1; i < 32; i++) | |
458 | if (((c >>= 1) & 1) != last_bit_value) | |
459 | last_bit_value ^= 1, transitions++; | |
460 | ||
461 | return transitions <= 2; | |
462 | } | |
463 | ||
464 | /* Return 1 if the operand is a constant that is a mask on the RS/6000. */ | |
465 | ||
466 | int | |
467 | mask_operand (op, mode) | |
468 | register rtx op; | |
469 | enum machine_mode mode; | |
470 | { | |
471 | return GET_CODE (op) == CONST_INT && mask_constant (INTVAL (op)); | |
472 | } | |
473 | ||
474 | /* Return 1 if the operand is either a non-special register or a | |
475 | constant that can be used as the operand of an RS/6000 logical AND insn. */ | |
476 | ||
477 | int | |
478 | and_operand (op, mode) | |
479 | register rtx op; | |
480 | enum machine_mode mode; | |
481 | { | |
482 | return (reg_or_short_operand (op, mode) | |
483 | || logical_operand (op, mode) | |
484 | || mask_operand (op, mode)); | |
485 | } | |
486 | ||
dcfedcd0 RK |
487 | /* Return 1 if the operand is a constant but not a valid operand for an AND |
488 | insn. */ | |
489 | ||
490 | int | |
491 | non_and_cint_operand (op, mode) | |
492 | register rtx op; | |
493 | enum machine_mode mode; | |
494 | { | |
495 | return GET_CODE (op) == CONST_INT && ! and_operand (op, mode); | |
496 | } | |
497 | ||
9878760c RK |
498 | /* Return 1 if the operand is a general register or memory operand. */ |
499 | ||
500 | int | |
501 | reg_or_mem_operand (op, mode) | |
502 | register rtx op; | |
503 | register enum machine_mode mode; | |
504 | { | |
cd2b37d9 | 505 | return gpc_reg_operand (op, mode) || memory_operand (op, mode); |
9878760c RK |
506 | } |
507 | ||
508 | /* Return 1 if the operand, used inside a MEM, is a valid first argument | |
509 | to CALL. This is a SYMBOL_REF or a pseudo-register, which will be | |
510 | forced to lr. */ | |
511 | ||
512 | int | |
513 | call_operand (op, mode) | |
514 | register rtx op; | |
515 | enum machine_mode mode; | |
516 | { | |
517 | if (mode != VOIDmode && GET_MODE (op) != mode) | |
518 | return 0; | |
519 | ||
520 | return (GET_CODE (op) == SYMBOL_REF | |
521 | || (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER)); | |
522 | } | |
523 | ||
2af3d377 RK |
524 | |
525 | /* Return 1 if the operand is a SYMBOL_REF for a function known to be in | |
526 | this file. */ | |
527 | ||
528 | int | |
529 | current_file_function_operand (op, mode) | |
530 | register rtx op; | |
531 | enum machine_mode mode; | |
532 | { | |
533 | return (GET_CODE (op) == SYMBOL_REF | |
534 | && (SYMBOL_REF_FLAG (op) | |
535 | || op == XEXP (DECL_RTL (current_function_decl), 0))); | |
536 | } | |
537 | ||
538 | ||
9878760c RK |
539 | /* Return 1 if this operand is a valid input for a move insn. */ |
540 | ||
541 | int | |
542 | input_operand (op, mode) | |
543 | register rtx op; | |
544 | enum machine_mode mode; | |
545 | { | |
eb4e8003 | 546 | /* Memory is always valid. */ |
9878760c RK |
547 | if (memory_operand (op, mode)) |
548 | return 1; | |
549 | ||
eb4e8003 RK |
550 | /* For floating-point, easy constants are valid. */ |
551 | if (GET_MODE_CLASS (mode) == MODE_FLOAT | |
552 | && CONSTANT_P (op) | |
553 | && easy_fp_constant (op, mode)) | |
554 | return 1; | |
555 | ||
556 | /* For floating-point or multi-word mode, the only remaining valid type | |
557 | is a register. */ | |
9878760c RK |
558 | if (GET_MODE_CLASS (mode) == MODE_FLOAT |
559 | || GET_MODE_SIZE (mode) > UNITS_PER_WORD) | |
eb4e8003 | 560 | return register_operand (op, mode); |
9878760c | 561 | |
88fe15a1 RK |
562 | /* The only cases left are integral modes one word or smaller (we |
563 | do not get called for MODE_CC values). These can be in any | |
564 | register. */ | |
565 | if (register_operand (op, mode)) | |
a8b3aeda | 566 | return 1; |
88fe15a1 RK |
567 | |
568 | /* For HImode and QImode, any constant is valid. */ | |
569 | if ((mode == HImode || mode == QImode) | |
570 | && GET_CODE (op) == CONST_INT) | |
9878760c RK |
571 | return 1; |
572 | ||
9878760c RK |
573 | /* Otherwise, we will be doing this SET with an add, so anything valid |
574 | for an add will be valid. */ | |
575 | return add_operand (op, mode); | |
576 | } | |
577 | \f | |
578 | /* Return 1 if OP is a load multiple operation. It is known to be a | |
579 | PARALLEL and the first section will be tested. */ | |
580 | ||
581 | int | |
582 | load_multiple_operation (op, mode) | |
583 | rtx op; | |
584 | enum machine_mode mode; | |
585 | { | |
586 | int count = XVECLEN (op, 0); | |
587 | int dest_regno; | |
588 | rtx src_addr; | |
589 | int i; | |
590 | ||
591 | /* Perform a quick check so we don't blow up below. */ | |
592 | if (count <= 1 | |
593 | || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
594 | || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG | |
595 | || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM) | |
596 | return 0; | |
597 | ||
598 | dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0))); | |
599 | src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0); | |
600 | ||
601 | for (i = 1; i < count; i++) | |
602 | { | |
603 | rtx elt = XVECEXP (op, 0, i); | |
604 | ||
605 | if (GET_CODE (elt) != SET | |
606 | || GET_CODE (SET_DEST (elt)) != REG | |
607 | || GET_MODE (SET_DEST (elt)) != SImode | |
608 | || REGNO (SET_DEST (elt)) != dest_regno + i | |
609 | || GET_CODE (SET_SRC (elt)) != MEM | |
610 | || GET_MODE (SET_SRC (elt)) != SImode | |
611 | || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS | |
612 | || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr) | |
613 | || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT | |
614 | || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != i * 4) | |
615 | return 0; | |
616 | } | |
617 | ||
618 | return 1; | |
619 | } | |
620 | ||
621 | /* Similar, but tests for store multiple. Here, the second vector element | |
622 | is a CLOBBER. It will be tested later. */ | |
623 | ||
624 | int | |
625 | store_multiple_operation (op, mode) | |
626 | rtx op; | |
627 | enum machine_mode mode; | |
628 | { | |
629 | int count = XVECLEN (op, 0) - 1; | |
630 | int src_regno; | |
631 | rtx dest_addr; | |
632 | int i; | |
633 | ||
634 | /* Perform a quick check so we don't blow up below. */ | |
635 | if (count <= 1 | |
636 | || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
637 | || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM | |
638 | || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG) | |
639 | return 0; | |
640 | ||
641 | src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0))); | |
642 | dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0); | |
643 | ||
644 | for (i = 1; i < count; i++) | |
645 | { | |
646 | rtx elt = XVECEXP (op, 0, i + 1); | |
647 | ||
648 | if (GET_CODE (elt) != SET | |
649 | || GET_CODE (SET_SRC (elt)) != REG | |
650 | || GET_MODE (SET_SRC (elt)) != SImode | |
651 | || REGNO (SET_SRC (elt)) != src_regno + i | |
652 | || GET_CODE (SET_DEST (elt)) != MEM | |
653 | || GET_MODE (SET_DEST (elt)) != SImode | |
654 | || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS | |
655 | || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr) | |
656 | || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT | |
657 | || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != i * 4) | |
658 | return 0; | |
659 | } | |
660 | ||
661 | return 1; | |
662 | } | |
663 | \f | |
664 | /* Return 1 if OP is a comparison operation that is valid for a branch insn. | |
665 | We only check the opcode against the mode of the CC value here. */ | |
666 | ||
667 | int | |
668 | branch_comparison_operator (op, mode) | |
669 | register rtx op; | |
670 | enum machine_mode mode; | |
671 | { | |
672 | enum rtx_code code = GET_CODE (op); | |
673 | enum machine_mode cc_mode; | |
674 | ||
675 | if (GET_RTX_CLASS (code) != '<') | |
676 | return 0; | |
677 | ||
678 | cc_mode = GET_MODE (XEXP (op, 0)); | |
679 | if (GET_MODE_CLASS (cc_mode) != MODE_CC) | |
680 | return 0; | |
681 | ||
682 | if ((code == GT || code == LT || code == GE || code == LE) | |
683 | && cc_mode == CCUNSmode) | |
684 | return 0; | |
685 | ||
686 | if ((code == GTU || code == LTU || code == GEU || code == LEU) | |
687 | && (cc_mode != CCUNSmode)) | |
688 | return 0; | |
689 | ||
690 | return 1; | |
691 | } | |
692 | ||
693 | /* Return 1 if OP is a comparison operation that is valid for an scc insn. | |
694 | We check the opcode against the mode of the CC value and disallow EQ or | |
695 | NE comparisons for integers. */ | |
696 | ||
697 | int | |
698 | scc_comparison_operator (op, mode) | |
699 | register rtx op; | |
700 | enum machine_mode mode; | |
701 | { | |
702 | enum rtx_code code = GET_CODE (op); | |
703 | enum machine_mode cc_mode; | |
704 | ||
705 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
706 | return 0; | |
707 | ||
708 | if (GET_RTX_CLASS (code) != '<') | |
709 | return 0; | |
710 | ||
711 | cc_mode = GET_MODE (XEXP (op, 0)); | |
712 | if (GET_MODE_CLASS (cc_mode) != MODE_CC) | |
713 | return 0; | |
714 | ||
715 | if (code == NE && cc_mode != CCFPmode) | |
716 | return 0; | |
717 | ||
718 | if ((code == GT || code == LT || code == GE || code == LE) | |
719 | && cc_mode == CCUNSmode) | |
720 | return 0; | |
721 | ||
722 | if ((code == GTU || code == LTU || code == GEU || code == LEU) | |
723 | && (cc_mode != CCUNSmode)) | |
724 | return 0; | |
725 | ||
c5defebb RK |
726 | if (cc_mode == CCEQmode && code != EQ && code != NE) |
727 | return 0; | |
728 | ||
9878760c RK |
729 | return 1; |
730 | } | |
731 | \f | |
732 | /* Return 1 if ANDOP is a mask that has no bits on that are not in the | |
733 | mask required to convert the result of a rotate insn into a shift | |
734 | left insn of SHIFTOP bits. Both are known to be CONST_INT. */ | |
735 | ||
736 | int | |
737 | includes_lshift_p (shiftop, andop) | |
738 | register rtx shiftop; | |
739 | register rtx andop; | |
740 | { | |
741 | int shift_mask = (~0 << INTVAL (shiftop)); | |
742 | ||
743 | return (INTVAL (andop) & ~shift_mask) == 0; | |
744 | } | |
745 | ||
746 | /* Similar, but for right shift. */ | |
747 | ||
748 | int | |
749 | includes_rshift_p (shiftop, andop) | |
750 | register rtx shiftop; | |
751 | register rtx andop; | |
752 | { | |
753 | unsigned shift_mask = ~0; | |
754 | ||
755 | shift_mask >>= INTVAL (shiftop); | |
756 | ||
757 | return (INTVAL (andop) & ~ shift_mask) == 0; | |
758 | } | |
759 | \f | |
760 | /* Return the register class of a scratch register needed to copy IN into | |
761 | or out of a register in CLASS in MODE. If it can be done directly, | |
762 | NO_REGS is returned. */ | |
763 | ||
764 | enum reg_class | |
765 | secondary_reload_class (class, mode, in) | |
766 | enum reg_class class; | |
767 | enum machine_mode mode; | |
768 | rtx in; | |
769 | { | |
770 | int regno = true_regnum (in); | |
771 | ||
772 | if (regno >= FIRST_PSEUDO_REGISTER) | |
773 | regno = -1; | |
774 | ||
775 | /* We can place anything into GENERAL_REGS and can put GENERAL_REGS | |
776 | into anything. */ | |
777 | if (class == GENERAL_REGS || class == BASE_REGS | |
778 | || (regno >= 0 && INT_REGNO_P (regno))) | |
779 | return NO_REGS; | |
780 | ||
781 | /* Constants, memory, and FP registers can go into FP registers. */ | |
782 | if ((regno == -1 || FP_REGNO_P (regno)) | |
783 | && (class == FLOAT_REGS || class == NON_SPECIAL_REGS)) | |
784 | return NO_REGS; | |
785 | ||
786 | /* We can copy among the CR registers. */ | |
787 | if ((class == CR_REGS || class == CR0_REGS) | |
788 | && regno >= 0 && CR_REGNO_P (regno)) | |
789 | return NO_REGS; | |
790 | ||
791 | /* Otherwise, we need GENERAL_REGS. */ | |
792 | return GENERAL_REGS; | |
793 | } | |
794 | \f | |
795 | /* Given a comparison operation, return the bit number in CCR to test. We | |
796 | know this is a valid comparison. | |
797 | ||
798 | SCC_P is 1 if this is for an scc. That means that %D will have been | |
799 | used instead of %C, so the bits will be in different places. | |
800 | ||
b4ac57ab | 801 | Return -1 if OP isn't a valid comparison for some reason. */ |
9878760c RK |
802 | |
803 | int | |
804 | ccr_bit (op, scc_p) | |
805 | register rtx op; | |
806 | int scc_p; | |
807 | { | |
808 | enum rtx_code code = GET_CODE (op); | |
809 | enum machine_mode cc_mode; | |
810 | int cc_regnum; | |
811 | int base_bit; | |
812 | ||
813 | if (GET_RTX_CLASS (code) != '<') | |
814 | return -1; | |
815 | ||
816 | cc_mode = GET_MODE (XEXP (op, 0)); | |
817 | cc_regnum = REGNO (XEXP (op, 0)); | |
818 | base_bit = 4 * (cc_regnum - 68); | |
819 | ||
c5defebb RK |
820 | /* In CCEQmode cases we have made sure that the result is always in the |
821 | third bit of the CR field. */ | |
822 | ||
823 | if (cc_mode == CCEQmode) | |
824 | return base_bit + 3; | |
825 | ||
9878760c RK |
826 | switch (code) |
827 | { | |
828 | case NE: | |
829 | return scc_p ? base_bit + 3 : base_bit + 2; | |
830 | case EQ: | |
831 | return base_bit + 2; | |
832 | case GT: case GTU: | |
833 | return base_bit + 1; | |
834 | case LT: case LTU: | |
835 | return base_bit; | |
836 | ||
837 | case GE: case GEU: | |
838 | /* If floating-point, we will have done a cror to put the bit in the | |
839 | unordered position. So test that bit. For integer, this is ! LT | |
840 | unless this is an scc insn. */ | |
841 | return cc_mode == CCFPmode || scc_p ? base_bit + 3 : base_bit; | |
842 | ||
843 | case LE: case LEU: | |
844 | return cc_mode == CCFPmode || scc_p ? base_bit + 3 : base_bit + 1; | |
845 | ||
846 | default: | |
847 | abort (); | |
848 | } | |
849 | } | |
850 | \f | |
851 | /* Print an operand. Recognize special options, documented below. */ | |
852 | ||
853 | void | |
854 | print_operand (file, x, code) | |
855 | FILE *file; | |
856 | rtx x; | |
857 | char code; | |
858 | { | |
859 | int i; | |
860 | int val; | |
861 | ||
862 | /* These macros test for integers and extract the low-order bits. */ | |
863 | #define INT_P(X) \ | |
864 | ((GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST_DOUBLE) \ | |
865 | && GET_MODE (X) == VOIDmode) | |
866 | ||
867 | #define INT_LOWPART(X) \ | |
868 | (GET_CODE (X) == CONST_INT ? INTVAL (X) : CONST_DOUBLE_LOW (X)) | |
869 | ||
870 | switch (code) | |
871 | { | |
a8b3aeda | 872 | case '.': |
a85d226b RK |
873 | /* Write out an instruction after the call which may be replaced |
874 | with glue code by the loader. This depends on the AIX version. */ | |
875 | asm_fprintf (file, RS6000_CALL_GLUE); | |
a8b3aeda RK |
876 | return; |
877 | ||
9854d9ed RK |
878 | case 'A': |
879 | /* If X is a constant integer whose low-order 5 bits are zero, | |
880 | write 'l'. Otherwise, write 'r'. This is a kludge to fix a bug | |
76229ac8 | 881 | in the AIX assembler where "sri" with a zero shift count |
9854d9ed RK |
882 | write a trash instruction. */ |
883 | if (GET_CODE (x) == CONST_INT && (INTVAL (x) & 31) == 0) | |
76229ac8 | 884 | putc ('l', file); |
9854d9ed | 885 | else |
76229ac8 | 886 | putc ('r', file); |
9854d9ed RK |
887 | return; |
888 | ||
889 | case 'b': | |
890 | /* Low-order 16 bits of constant, unsigned. */ | |
cad12a8d | 891 | if (! INT_P (x)) |
9854d9ed | 892 | output_operand_lossage ("invalid %%b value"); |
cad12a8d | 893 | |
9854d9ed | 894 | fprintf (file, "%d", INT_LOWPART (x) & 0xffff); |
cad12a8d RK |
895 | return; |
896 | ||
9854d9ed RK |
897 | case 'C': |
898 | /* This is an optional cror needed for LE or GE floating-point | |
899 | comparisons. Otherwise write nothing. */ | |
900 | if ((GET_CODE (x) == LE || GET_CODE (x) == GE) | |
901 | && GET_MODE (XEXP (x, 0)) == CCFPmode) | |
902 | { | |
903 | int base_bit = 4 * (REGNO (XEXP (x, 0)) - 68); | |
904 | ||
905 | fprintf (file, "cror %d,%d,%d\n\t", base_bit + 3, | |
906 | base_bit + 2, base_bit + (GET_CODE (x) == GE)); | |
907 | } | |
908 | return; | |
909 | ||
910 | case 'D': | |
911 | /* Similar, except that this is for an scc, so we must be able to | |
912 | encode the test in a single bit that is one. We do the above | |
913 | for any LE, GE, GEU, or LEU and invert the bit for NE. */ | |
914 | if (GET_CODE (x) == LE || GET_CODE (x) == GE | |
915 | || GET_CODE (x) == LEU || GET_CODE (x) == GEU) | |
916 | { | |
917 | int base_bit = 4 * (REGNO (XEXP (x, 0)) - 68); | |
918 | ||
919 | fprintf (file, "cror %d,%d,%d\n\t", base_bit + 3, | |
920 | base_bit + 2, | |
921 | base_bit + (GET_CODE (x) == GE || GET_CODE (x) == GEU)); | |
922 | } | |
923 | ||
924 | else if (GET_CODE (x) == NE) | |
925 | { | |
926 | int base_bit = 4 * (REGNO (XEXP (x, 0)) - 68); | |
927 | ||
928 | fprintf (file, "crnor %d,%d,%d\n\t", base_bit + 3, | |
929 | base_bit + 2, base_bit + 2); | |
930 | } | |
931 | return; | |
932 | ||
933 | case 'E': | |
934 | /* X is a CR register. Print the number of the third bit of the CR */ | |
935 | if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x))) | |
936 | output_operand_lossage ("invalid %%E value"); | |
937 | ||
938 | fprintf(file, "%d", 4 * (REGNO (x) - 68) + 3); | |
a85d226b | 939 | return; |
9854d9ed RK |
940 | |
941 | case 'f': | |
942 | /* X is a CR register. Print the shift count needed to move it | |
943 | to the high-order four bits. */ | |
944 | if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x))) | |
945 | output_operand_lossage ("invalid %%f value"); | |
946 | else | |
947 | fprintf (file, "%d", 4 * (REGNO (x) - 68)); | |
948 | return; | |
949 | ||
950 | case 'F': | |
951 | /* Similar, but print the count for the rotate in the opposite | |
952 | direction. */ | |
953 | if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x))) | |
954 | output_operand_lossage ("invalid %%F value"); | |
955 | else | |
956 | fprintf (file, "%d", 32 - 4 * (REGNO (x) - 68)); | |
957 | return; | |
958 | ||
959 | case 'G': | |
960 | /* X is a constant integer. If it is negative, print "m", | |
961 | otherwise print "z". This is to make a aze or ame insn. */ | |
962 | if (GET_CODE (x) != CONST_INT) | |
963 | output_operand_lossage ("invalid %%G value"); | |
964 | else if (INTVAL (x) >= 0) | |
76229ac8 | 965 | putc ('z', file); |
9854d9ed | 966 | else |
76229ac8 | 967 | putc ('m', file); |
9854d9ed RK |
968 | return; |
969 | ||
9878760c | 970 | case 'h': |
df3d94ed RK |
971 | /* If constant, output low-order five bits. Otherwise, |
972 | write normally. */ | |
9878760c RK |
973 | if (INT_P (x)) |
974 | fprintf (file, "%d", INT_LOWPART (x) & 31); | |
975 | else | |
976 | print_operand (file, x, 0); | |
977 | return; | |
978 | ||
979 | case 'H': | |
df3d94ed | 980 | /* X must be a constant. Output the low order 5 bits plus 24. */ |
9878760c RK |
981 | if (! INT_P (x)) |
982 | output_operand_lossage ("invalid %%H value"); | |
983 | ||
984 | fprintf (file, "%d", (INT_LOWPART (x) + 24) & 31); | |
985 | return; | |
986 | ||
9854d9ed RK |
987 | case 'I': |
988 | /* Print `i' if this is a constant, else nothing. */ | |
9878760c | 989 | if (INT_P (x)) |
76229ac8 | 990 | putc ('i', file); |
9878760c RK |
991 | return; |
992 | ||
9854d9ed RK |
993 | case 'j': |
994 | /* Write the bit number in CCR for jump. */ | |
995 | i = ccr_bit (x, 0); | |
996 | if (i == -1) | |
997 | output_operand_lossage ("invalid %%j code"); | |
9878760c | 998 | else |
9854d9ed | 999 | fprintf (file, "%d", i); |
9878760c RK |
1000 | return; |
1001 | ||
9854d9ed RK |
1002 | case 'J': |
1003 | /* Similar, but add one for shift count in rlinm for scc and pass | |
1004 | scc flag to `ccr_bit'. */ | |
1005 | i = ccr_bit (x, 1); | |
1006 | if (i == -1) | |
1007 | output_operand_lossage ("invalid %%J code"); | |
1008 | else | |
a0466a68 RK |
1009 | /* If we want bit 31, write a shift count of zero, not 32. */ |
1010 | fprintf (file, "%d", i == 31 ? 0 : i + 1); | |
9878760c RK |
1011 | return; |
1012 | ||
9854d9ed RK |
1013 | case 'k': |
1014 | /* X must be a constant. Write the 1's complement of the | |
1015 | constant. */ | |
9878760c | 1016 | if (! INT_P (x)) |
9854d9ed | 1017 | output_operand_lossage ("invalid %%k value"); |
9878760c | 1018 | |
9854d9ed | 1019 | fprintf (file, "%d", ~ INT_LOWPART (x)); |
9878760c RK |
1020 | return; |
1021 | ||
9854d9ed RK |
1022 | case 'L': |
1023 | /* Write second word of DImode or DFmode reference. Works on register | |
1024 | or non-indexed memory only. */ | |
1025 | if (GET_CODE (x) == REG) | |
1026 | fprintf (file, "%d", REGNO (x) + 1); | |
1027 | else if (GET_CODE (x) == MEM) | |
1028 | { | |
1029 | /* Handle possible auto-increment. Since it is pre-increment and | |
1030 | we have already done it, we can just use an offset of four. */ | |
1031 | if (GET_CODE (XEXP (x, 0)) == PRE_INC | |
1032 | || GET_CODE (XEXP (x, 0)) == PRE_DEC) | |
1033 | output_address (plus_constant (XEXP (XEXP (x, 0), 0), 4)); | |
1034 | else | |
1035 | output_address (plus_constant (XEXP (x, 0), 4)); | |
1036 | } | |
9878760c | 1037 | return; |
9854d9ed | 1038 | |
9878760c RK |
1039 | case 'm': |
1040 | /* MB value for a mask operand. */ | |
1041 | if (! mask_operand (x, VOIDmode)) | |
1042 | output_operand_lossage ("invalid %%m value"); | |
1043 | ||
1044 | val = INT_LOWPART (x); | |
1045 | ||
1046 | /* If the high bit is set and the low bit is not, the value is zero. | |
1047 | If the high bit is zero, the value is the first 1 bit we find from | |
1048 | the left. */ | |
1049 | if (val < 0 && (val & 1) == 0) | |
1050 | { | |
1051 | fprintf (file, "0"); | |
1052 | return; | |
1053 | } | |
1054 | else if (val >= 0) | |
1055 | { | |
1056 | for (i = 1; i < 32; i++) | |
1057 | if ((val <<= 1) < 0) | |
1058 | break; | |
1059 | fprintf (file, "%d", i); | |
1060 | return; | |
1061 | } | |
1062 | ||
1063 | /* Otherwise, look for the first 0 bit from the right. The result is its | |
1064 | number plus 1. We know the low-order bit is one. */ | |
1065 | for (i = 0; i < 32; i++) | |
1066 | if (((val >>= 1) & 1) == 0) | |
1067 | break; | |
1068 | ||
1069 | /* If we ended in ...01, I would be 0. The correct value is 31, so | |
1070 | we want 31 - i. */ | |
1071 | fprintf (file, "%d", 31 - i); | |
1072 | return; | |
1073 | ||
1074 | case 'M': | |
1075 | /* ME value for a mask operand. */ | |
1076 | if (! mask_operand (x, VOIDmode)) | |
1077 | output_operand_lossage ("invalid %%m value"); | |
1078 | ||
1079 | val = INT_LOWPART (x); | |
1080 | ||
1081 | /* If the low bit is set and the high bit is not, the value is 31. | |
1082 | If the low bit is zero, the value is the first 1 bit we find from | |
1083 | the right. */ | |
1084 | if ((val & 1) && val >= 0) | |
1085 | { | |
76229ac8 | 1086 | fputs ("31", file); |
9878760c RK |
1087 | return; |
1088 | } | |
1089 | else if ((val & 1) == 0) | |
1090 | { | |
1091 | for (i = 0; i < 32; i++) | |
1092 | if ((val >>= 1) & 1) | |
1093 | break; | |
1094 | ||
1095 | /* If we had ....10, I would be 0. The result should be | |
1096 | 30, so we need 30 - i. */ | |
1097 | fprintf (file, "%d", 30 - i); | |
1098 | return; | |
1099 | } | |
1100 | ||
1101 | /* Otherwise, look for the first 0 bit from the left. The result is its | |
1102 | number minus 1. We know the high-order bit is one. */ | |
1103 | for (i = 0; i < 32; i++) | |
1104 | if ((val <<= 1) >= 0) | |
1105 | break; | |
1106 | ||
1107 | fprintf (file, "%d", i); | |
1108 | return; | |
1109 | ||
9878760c RK |
1110 | case 'N': |
1111 | /* Write the number of elements in the vector times 4. */ | |
1112 | if (GET_CODE (x) != PARALLEL) | |
1113 | output_operand_lossage ("invalid %%N value"); | |
1114 | ||
1115 | fprintf (file, "%d", XVECLEN (x, 0) * 4); | |
1116 | return; | |
1117 | ||
1118 | case 'O': | |
1119 | /* Similar, but subtract 1 first. */ | |
1120 | if (GET_CODE (x) != PARALLEL) | |
1121 | output_operand_lossage ("invalid %%N value"); | |
1122 | ||
1123 | fprintf (file, "%d", (XVECLEN (x, 0) - 1) * 4); | |
1124 | return; | |
1125 | ||
9854d9ed RK |
1126 | case 'p': |
1127 | /* X is a CONST_INT that is a power of two. Output the logarithm. */ | |
1128 | if (! INT_P (x) | |
1129 | || (i = exact_log2 (INT_LOWPART (x))) < 0) | |
1130 | output_operand_lossage ("invalid %%p value"); | |
1131 | ||
1132 | fprintf (file, "%d", i); | |
1133 | return; | |
1134 | ||
9878760c RK |
1135 | case 'P': |
1136 | /* The operand must be an indirect memory reference. The result | |
1137 | is the register number. */ | |
1138 | if (GET_CODE (x) != MEM || GET_CODE (XEXP (x, 0)) != REG | |
1139 | || REGNO (XEXP (x, 0)) >= 32) | |
1140 | output_operand_lossage ("invalid %%P value"); | |
1141 | ||
1142 | fprintf (file, "%d", REGNO (XEXP (x, 0))); | |
1143 | return; | |
1144 | ||
9854d9ed RK |
1145 | case 'R': |
1146 | /* X is a CR register. Print the mask for `mtcrf'. */ | |
1147 | if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x))) | |
1148 | output_operand_lossage ("invalid %%R value"); | |
1149 | else | |
1150 | fprintf (file, "%d", 128 >> (REGNO (x) - 68)); | |
9878760c | 1151 | return; |
9854d9ed RK |
1152 | |
1153 | case 's': | |
1154 | /* Low 5 bits of 32 - value */ | |
1155 | if (! INT_P (x)) | |
1156 | output_operand_lossage ("invalid %%s value"); | |
1157 | ||
1158 | fprintf (file, "%d", (32 - INT_LOWPART (x)) & 31); | |
9878760c | 1159 | return; |
9854d9ed RK |
1160 | |
1161 | case 'S': | |
1162 | /* Low 5 bits of 31 - value */ | |
1163 | if (! INT_P (x)) | |
1164 | output_operand_lossage ("invalid %%S value"); | |
1165 | ||
1166 | fprintf (file, "%d", (31 - INT_LOWPART (x)) & 31); | |
9878760c | 1167 | return; |
9854d9ed | 1168 | |
9878760c RK |
1169 | case 't': |
1170 | /* Write 12 if this jump operation will branch if true, 4 otherwise. | |
1171 | All floating-point operations except NE branch true and integer | |
1172 | EQ, LT, GT, LTU and GTU also branch true. */ | |
1173 | if (GET_RTX_CLASS (GET_CODE (x)) != '<') | |
1174 | output_operand_lossage ("invalid %%t value"); | |
1175 | ||
1176 | else if ((GET_MODE (XEXP (x, 0)) == CCFPmode | |
1177 | && GET_CODE (x) != NE) | |
1178 | || GET_CODE (x) == EQ | |
1179 | || GET_CODE (x) == LT || GET_CODE (x) == GT | |
1180 | || GET_CODE (x) == LTU || GET_CODE (x) == GTU) | |
76229ac8 | 1181 | fputs ("12", file); |
9878760c | 1182 | else |
76229ac8 | 1183 | putc ('4', file); |
9878760c RK |
1184 | return; |
1185 | ||
1186 | case 'T': | |
1187 | /* Opposite of 't': write 4 if this jump operation will branch if true, | |
1188 | 12 otherwise. */ | |
1189 | if (GET_RTX_CLASS (GET_CODE (x)) != '<') | |
1190 | output_operand_lossage ("invalid %%t value"); | |
1191 | ||
1192 | else if ((GET_MODE (XEXP (x, 0)) == CCFPmode | |
1193 | && GET_CODE (x) != NE) | |
1194 | || GET_CODE (x) == EQ | |
1195 | || GET_CODE (x) == LT || GET_CODE (x) == GT | |
1196 | || GET_CODE (x) == LTU || GET_CODE (x) == GTU) | |
76229ac8 | 1197 | putc ('4', file); |
9878760c | 1198 | else |
76229ac8 | 1199 | fputs ("12", file); |
9878760c RK |
1200 | return; |
1201 | ||
9854d9ed RK |
1202 | case 'u': |
1203 | /* High-order 16 bits of constant. */ | |
1204 | if (! INT_P (x)) | |
1205 | output_operand_lossage ("invalid %%u value"); | |
9878760c | 1206 | |
76229ac8 | 1207 | fprintf (file, "0x%x", (INT_LOWPART (x) >> 16) & 0xffff); |
9878760c RK |
1208 | return; |
1209 | ||
9854d9ed RK |
1210 | case 'U': |
1211 | /* Print `u' if this has an auto-increment or auto-decrement. */ | |
1212 | if (GET_CODE (x) == MEM | |
1213 | && (GET_CODE (XEXP (x, 0)) == PRE_INC | |
1214 | || GET_CODE (XEXP (x, 0)) == PRE_DEC)) | |
76229ac8 | 1215 | putc ('u', file); |
9854d9ed | 1216 | return; |
9878760c | 1217 | |
9854d9ed RK |
1218 | case 'w': |
1219 | /* If constant, low-order 16 bits of constant, signed. Otherwise, write | |
1220 | normally. */ | |
1221 | if (INT_P (x)) | |
1222 | fprintf (file, "%d", | |
1223 | (INT_LOWPART (x) & 0xffff) - 2 * (INT_LOWPART (x) & 0x8000)); | |
1224 | else | |
1225 | print_operand (file, x, 0); | |
9878760c RK |
1226 | return; |
1227 | ||
9854d9ed RK |
1228 | case 'W': |
1229 | /* If constant, low-order 16 bits of constant, unsigned. | |
1230 | Otherwise, write normally. */ | |
1231 | if (INT_P (x)) | |
1232 | fprintf (file, "%d", INT_LOWPART (x) & 0xffff); | |
1233 | else | |
1234 | print_operand (file, x, 0); | |
1235 | return; | |
9878760c | 1236 | |
9854d9ed RK |
1237 | case 'X': |
1238 | if (GET_CODE (x) == MEM | |
1239 | && LEGITIMATE_INDEXED_ADDRESS_P (XEXP (x, 0))) | |
76229ac8 | 1240 | putc ('x', file); |
9854d9ed | 1241 | return; |
9878760c | 1242 | |
9854d9ed RK |
1243 | case 'Y': |
1244 | /* Like 'L', for third word of TImode */ | |
1245 | if (GET_CODE (x) == REG) | |
1246 | fprintf (file, "%d", REGNO (x) + 2); | |
1247 | else if (GET_CODE (x) == MEM) | |
9878760c | 1248 | { |
9854d9ed RK |
1249 | if (GET_CODE (XEXP (x, 0)) == PRE_INC |
1250 | || GET_CODE (XEXP (x, 0)) == PRE_DEC) | |
1251 | output_address (plus_constant (XEXP (XEXP (x, 0), 0), 8)); | |
1252 | else | |
1253 | output_address (plus_constant (XEXP (x, 0), 8)); | |
9878760c RK |
1254 | } |
1255 | return; | |
9854d9ed | 1256 | |
9878760c | 1257 | case 'z': |
b4ac57ab RS |
1258 | /* X is a SYMBOL_REF. Write out the name preceded by a |
1259 | period and without any trailing data in brackets. Used for function | |
9878760c RK |
1260 | names. */ |
1261 | if (GET_CODE (x) != SYMBOL_REF) | |
1262 | abort (); | |
1263 | ||
76229ac8 | 1264 | putc ('.', file); |
9878760c RK |
1265 | RS6000_OUTPUT_BASENAME (file, XSTR (x, 0)); |
1266 | return; | |
1267 | ||
9854d9ed RK |
1268 | case 'Z': |
1269 | /* Like 'L', for last word of TImode. */ | |
1270 | if (GET_CODE (x) == REG) | |
1271 | fprintf (file, "%d", REGNO (x) + 3); | |
1272 | else if (GET_CODE (x) == MEM) | |
1273 | { | |
1274 | if (GET_CODE (XEXP (x, 0)) == PRE_INC | |
1275 | || GET_CODE (XEXP (x, 0)) == PRE_DEC) | |
1276 | output_address (plus_constant (XEXP (XEXP (x, 0), 0), 12)); | |
1277 | else | |
1278 | output_address (plus_constant (XEXP (x, 0), 12)); | |
1279 | } | |
5c23c401 | 1280 | return; |
9854d9ed | 1281 | |
9878760c RK |
1282 | case 0: |
1283 | if (GET_CODE (x) == REG) | |
1284 | fprintf (file, "%s", reg_names[REGNO (x)]); | |
1285 | else if (GET_CODE (x) == MEM) | |
1286 | { | |
1287 | /* We need to handle PRE_INC and PRE_DEC here, since we need to | |
1288 | know the width from the mode. */ | |
1289 | if (GET_CODE (XEXP (x, 0)) == PRE_INC) | |
1290 | fprintf (file, "%d(%d)", GET_MODE_SIZE (GET_MODE (x)), | |
1291 | REGNO (XEXP (XEXP (x, 0), 0))); | |
1292 | else if (GET_CODE (XEXP (x, 0)) == PRE_DEC) | |
1293 | fprintf (file, "%d(%d)", - GET_MODE_SIZE (GET_MODE (x)), | |
1294 | REGNO (XEXP (XEXP (x, 0), 0))); | |
1295 | else | |
1296 | output_address (XEXP (x, 0)); | |
1297 | } | |
1298 | else | |
1299 | output_addr_const (file, x); | |
a85d226b | 1300 | return; |
9878760c RK |
1301 | |
1302 | default: | |
1303 | output_operand_lossage ("invalid %%xn code"); | |
1304 | } | |
1305 | } | |
1306 | \f | |
1307 | /* Print the address of an operand. */ | |
1308 | ||
1309 | void | |
1310 | print_operand_address (file, x) | |
1311 | FILE *file; | |
1312 | register rtx x; | |
1313 | { | |
1314 | if (GET_CODE (x) == REG) | |
1315 | fprintf (file, "0(%d)", REGNO (x)); | |
1316 | else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST) | |
1317 | { | |
1318 | output_addr_const (file, x); | |
1875cc88 JW |
1319 | /* When TARGET_MINIMAL_TOC, use the indirected toc table pointer instead |
1320 | of the toc pointer. */ | |
1321 | if (TARGET_MINIMAL_TOC) | |
1322 | fprintf (file, "(30)"); | |
1323 | else | |
1324 | fprintf (file, "(2)"); | |
9878760c RK |
1325 | } |
1326 | else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == REG) | |
1327 | { | |
1328 | if (REGNO (XEXP (x, 0)) == 0) | |
1329 | fprintf (file, "%d,%d", REGNO (XEXP (x, 1)), REGNO (XEXP (x, 0))); | |
1330 | else | |
1331 | fprintf (file, "%d,%d", REGNO (XEXP (x, 0)), REGNO (XEXP (x, 1))); | |
1332 | } | |
1333 | else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT) | |
1334 | fprintf (file, "%d(%d)", INTVAL (XEXP (x, 1)), REGNO (XEXP (x, 0))); | |
1335 | else | |
1336 | abort (); | |
1337 | } | |
1338 | \f | |
1339 | /* This page contains routines that are used to determine what the function | |
1340 | prologue and epilogue code will do and write them out. */ | |
1341 | ||
1342 | /* Return the first fixed-point register that is required to be saved. 32 if | |
1343 | none. */ | |
1344 | ||
1345 | int | |
1346 | first_reg_to_save () | |
1347 | { | |
1348 | int first_reg; | |
1349 | ||
1350 | /* Find lowest numbered live register. */ | |
1351 | for (first_reg = 13; first_reg <= 31; first_reg++) | |
1352 | if (regs_ever_live[first_reg]) | |
1353 | break; | |
1354 | ||
e165f3f0 RK |
1355 | /* If profiling, then we must save/restore every register that contains |
1356 | a parameter before/after the .mcount call. Use registers from 30 down | |
1357 | to 23 to do this. Don't use the frame pointer in reg 31. | |
1358 | ||
1359 | For now, save enough room for all of the parameter registers. */ | |
1360 | if (profile_flag) | |
1361 | if (first_reg > 23) | |
1362 | first_reg = 23; | |
1363 | ||
9878760c RK |
1364 | return first_reg; |
1365 | } | |
1366 | ||
1367 | /* Similar, for FP regs. */ | |
1368 | ||
1369 | int | |
1370 | first_fp_reg_to_save () | |
1371 | { | |
1372 | int first_reg; | |
1373 | ||
1374 | /* Find lowest numbered live register. */ | |
1375 | for (first_reg = 14 + 32; first_reg <= 63; first_reg++) | |
1376 | if (regs_ever_live[first_reg]) | |
1377 | break; | |
1378 | ||
1379 | return first_reg; | |
1380 | } | |
1381 | ||
1382 | /* Return 1 if we need to save CR. */ | |
1383 | ||
1384 | int | |
1385 | must_save_cr () | |
1386 | { | |
1387 | return regs_ever_live[70] || regs_ever_live[71] || regs_ever_live[72]; | |
1388 | } | |
1389 | ||
1390 | /* Compute the size of the save area in the stack, including the space for | |
1391 | the fixed area. */ | |
1392 | ||
1393 | int | |
1394 | rs6000_sa_size () | |
1395 | { | |
1396 | int size; | |
9878760c RK |
1397 | |
1398 | /* We have the six fixed words, plus the size of the register save | |
1399 | areas, rounded to a double-word. */ | |
1400 | size = 6 + (32 - first_reg_to_save ()) + (64 - first_fp_reg_to_save ()) * 2; | |
1401 | if (size & 1) | |
1402 | size++; | |
1403 | ||
1404 | return size * 4; | |
1405 | } | |
1406 | ||
1407 | /* Return non-zero if this function makes calls. */ | |
1408 | ||
1409 | int | |
1410 | rs6000_makes_calls () | |
1411 | { | |
1412 | rtx insn; | |
1413 | ||
0c61c946 RK |
1414 | /* If we are profiling, we will be making a call to mcount. */ |
1415 | if (profile_flag) | |
1416 | return 1; | |
1417 | ||
9878760c RK |
1418 | for (insn = get_insns (); insn; insn = next_insn (insn)) |
1419 | if (GET_CODE (insn) == CALL_INSN) | |
1420 | return 1; | |
1421 | ||
1422 | return 0; | |
1423 | } | |
1424 | ||
1425 | /* Return non-zero if this function needs to push space on the stack. */ | |
1426 | ||
1427 | int | |
1428 | rs6000_pushes_stack () | |
1429 | { | |
1430 | int total_size = (rs6000_sa_size () + get_frame_size () | |
1431 | + current_function_outgoing_args_size); | |
1432 | ||
1433 | /* We need to push the stack if a frame pointer is needed (because the | |
1434 | stack might be dynamically adjusted), if we are debugging, if the | |
1435 | total stack size is more than 220 bytes, or if we make calls. */ | |
1436 | ||
1437 | return (frame_pointer_needed || write_symbols != NO_DEBUG | |
1438 | || total_size > 220 | |
1439 | || rs6000_makes_calls ()); | |
1440 | } | |
1441 | ||
1442 | /* Write function prologue. */ | |
1443 | ||
1444 | void | |
1445 | output_prolog (file, size) | |
1446 | FILE *file; | |
1447 | int size; | |
1448 | { | |
1449 | int first_reg = first_reg_to_save (); | |
1450 | int must_push = rs6000_pushes_stack (); | |
1451 | int first_fp_reg = first_fp_reg_to_save (); | |
1452 | int basic_size = rs6000_sa_size (); | |
1453 | int total_size = (basic_size + size + current_function_outgoing_args_size); | |
1454 | ||
1455 | /* Round size to multiple of 8 bytes. */ | |
1456 | total_size = (total_size + 7) & ~7; | |
1457 | ||
1458 | /* Write .extern for any function we will call to save and restore fp | |
1459 | values. */ | |
1460 | if (first_fp_reg < 62) | |
1461 | fprintf (file, "\t.extern ._savef%d\n\t.extern ._restf%d\n", | |
1462 | first_fp_reg - 32, first_fp_reg - 32); | |
1463 | ||
1464 | /* Write .extern for truncation routines, if needed. */ | |
1465 | if (rs6000_trunc_used && ! trunc_defined) | |
1466 | { | |
e138174b ILT |
1467 | fprintf (file, "\t.extern .%s\n\t.extern .%s\n", |
1468 | RS6000_ITRUNC, RS6000_UITRUNC); | |
9878760c RK |
1469 | trunc_defined = 1; |
1470 | } | |
c764f757 RK |
1471 | /* Write .extern for AIX common mode routines, if needed. */ |
1472 | if (! TARGET_POWER && ! TARGET_POWERPC && ! common_mode_defined) | |
1473 | { | |
1474 | fputs ("\t.extern __mulh\n" | |
1475 | "\t.extern __mull\n" | |
1476 | "\t.extern __divss\n" | |
1477 | "\t.extern __divus\n" | |
1478 | "\t.extern __quoss\n" | |
1479 | "\t.extern __quous\n", | |
1480 | file); | |
1481 | common_mode_defined = 1; | |
1482 | } | |
9878760c | 1483 | |
e165f3f0 RK |
1484 | /* If we have to call a function to save fpr's, or if we are doing profiling, |
1485 | then we will be using LR. */ | |
1486 | if (first_fp_reg < 62 || profile_flag) | |
9878760c RK |
1487 | regs_ever_live[65] = 1; |
1488 | ||
1489 | /* If we use the link register, get it into r0. */ | |
1490 | if (regs_ever_live[65]) | |
85638c0d | 1491 | asm_fprintf (file, "\tmflr 0\n"); |
9878760c RK |
1492 | |
1493 | /* If we need to save CR, put it into r12. */ | |
1494 | if (must_save_cr ()) | |
85638c0d | 1495 | asm_fprintf (file, "\tmfcr 12\n"); |
9878760c RK |
1496 | |
1497 | /* Do any required saving of fpr's. If only one or two to save, do it | |
53322b0c RK |
1498 | ourself. Otherwise, call function. Note that since they are statically |
1499 | linked, we do not need a nop following them. */ | |
9878760c | 1500 | if (first_fp_reg == 62) |
85638c0d | 1501 | asm_fprintf (file, "\tstfd 30,-16(1)\n\tstfd 31,-8(1)\n"); |
9878760c | 1502 | else if (first_fp_reg == 63) |
85638c0d | 1503 | asm_fprintf (file, "\tstfd 31,-8(1)\n"); |
9878760c | 1504 | else if (first_fp_reg != 64) |
85638c0d | 1505 | asm_fprintf (file, "\tbl ._savef%d\n", first_fp_reg - 32); |
9878760c RK |
1506 | |
1507 | /* Now save gpr's. */ | |
85638c0d RK |
1508 | if (! TARGET_POWER || first_reg == 31) |
1509 | { | |
1510 | int regno, loc; | |
1511 | ||
1512 | for (regno = first_reg, | |
1513 | loc = - (32 - first_reg) * 4 - (64 - first_fp_reg) * 8; | |
1514 | regno < 32; | |
1515 | regno++, loc += 4) | |
1516 | asm_fprintf (file, "\t{st|stw} %d,%d(1)\n", regno, loc); | |
1517 | } | |
1518 | ||
9878760c | 1519 | else if (first_reg != 32) |
85638c0d | 1520 | asm_fprintf (file, "\t{stm|stmw} %d,%d(1)\n", first_reg, |
9878760c RK |
1521 | - (32 - first_reg) * 4 - (64 - first_fp_reg) * 8); |
1522 | ||
1523 | /* Save lr if we used it. */ | |
1524 | if (regs_ever_live[65]) | |
85638c0d | 1525 | asm_fprintf (file, "\t{st|stw} 0,8(1)\n"); |
9878760c RK |
1526 | |
1527 | /* Save CR if we use any that must be preserved. */ | |
1528 | if (must_save_cr ()) | |
85638c0d | 1529 | asm_fprintf (file, "\t{st|stw} 12,4(1)\n"); |
9878760c RK |
1530 | |
1531 | /* Update stack and set back pointer. */ | |
1532 | if (must_push) | |
1533 | { | |
1534 | if (total_size < 32767) | |
85638c0d | 1535 | asm_fprintf (file, "\t{stu|stwu} 1,%d(1)\n", - total_size); |
9878760c RK |
1536 | else |
1537 | { | |
85638c0d | 1538 | asm_fprintf (file, "\t{cau|addis} 0,0,%d\n\t{oril|ori} 0,0,%d\n", |
9878760c | 1539 | (total_size >> 16) & 0xffff, total_size & 0xffff); |
85638c0d RK |
1540 | asm_fprintf (file, "\t{sf|subfc} 12,0,1\n"); |
1541 | asm_fprintf (file, "\t{st|stw} 1,0(12)\n\t{oril|ori} 1,12,0\n"); | |
9878760c RK |
1542 | } |
1543 | } | |
1544 | ||
1545 | /* Set frame pointer, if needed. */ | |
1546 | if (frame_pointer_needed) | |
85638c0d | 1547 | asm_fprintf (file, "\t{oril|ori} 31,1,0\n"); |
1875cc88 JW |
1548 | |
1549 | /* If TARGET_MINIMAL_TOC, and the constant pool is needed, then load the | |
1550 | TOC_TABLE address into register 30. */ | |
1551 | if (TARGET_MINIMAL_TOC && get_pool_size () != 0) | |
3daf36a4 ILT |
1552 | { |
1553 | char buf[100]; | |
1554 | ||
1555 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 0); | |
1556 | asm_fprintf (file, "\t{l|lwz} 30,"); | |
1557 | assemble_name (file, buf); | |
1558 | asm_fprintf (file, "(2)\n"); | |
1559 | } | |
9878760c RK |
1560 | } |
1561 | ||
1562 | /* Write function epilogue. */ | |
1563 | ||
1564 | void | |
1565 | output_epilog (file, size) | |
1566 | FILE *file; | |
1567 | int size; | |
1568 | { | |
1569 | int first_reg = first_reg_to_save (); | |
1570 | int must_push = rs6000_pushes_stack (); | |
1571 | int first_fp_reg = first_fp_reg_to_save (); | |
1572 | int basic_size = rs6000_sa_size (); | |
1573 | int total_size = (basic_size + size + current_function_outgoing_args_size); | |
1574 | rtx insn = get_last_insn (); | |
1575 | ||
1576 | /* Round size to multiple of 8 bytes. */ | |
1577 | total_size = (total_size + 7) & ~7; | |
1578 | ||
1579 | /* If the last insn was a BARRIER, we don't have to write anything except | |
1580 | the trace table. */ | |
1581 | if (GET_CODE (insn) == NOTE) | |
1582 | insn = prev_nonnote_insn (insn); | |
1583 | if (insn == 0 || GET_CODE (insn) != BARRIER) | |
1584 | { | |
1585 | /* If we have a frame pointer, a call to alloca, or a large stack | |
1586 | frame, restore the old stack pointer using the backchain. Otherwise, | |
1587 | we know what size to update it with. */ | |
1588 | if (frame_pointer_needed || current_function_calls_alloca | |
1589 | || total_size > 32767) | |
85638c0d | 1590 | asm_fprintf (file, "\t{l|lwz} 1,0(1)\n"); |
9878760c | 1591 | else if (must_push) |
85638c0d | 1592 | asm_fprintf (file, "\t{ai|addic} 1,1,%d\n", total_size); |
9878760c | 1593 | |
b4ac57ab | 1594 | /* Get the old lr if we saved it. */ |
9878760c | 1595 | if (regs_ever_live[65]) |
85638c0d | 1596 | asm_fprintf (file, "\t{l|lwz} 0,8(1)\n"); |
9878760c RK |
1597 | |
1598 | /* Get the old cr if we saved it. */ | |
1599 | if (must_save_cr ()) | |
85638c0d | 1600 | asm_fprintf (file, "\t{l|lwz} 12,4(1)\n"); |
9878760c | 1601 | |
b4ac57ab RS |
1602 | /* Set LR here to try to overlap restores below. */ |
1603 | if (regs_ever_live[65]) | |
85638c0d | 1604 | asm_fprintf (file, "\tmtlr 0\n"); |
b4ac57ab | 1605 | |
9878760c | 1606 | /* Restore gpr's. */ |
85638c0d RK |
1607 | if (! TARGET_POWER || first_reg == 31) |
1608 | { | |
1609 | int regno, loc; | |
1610 | ||
1611 | for (regno = first_reg, | |
1612 | loc = - (32 - first_reg) * 4 - (64 - first_fp_reg) * 8; | |
1613 | regno < 32; | |
1614 | regno++, loc += 4) | |
1615 | asm_fprintf (file, "\t{l|lwz} %d,%d(1)\n", regno, loc); | |
1616 | } | |
1617 | ||
9878760c | 1618 | else if (first_reg != 32) |
85638c0d RK |
1619 | asm_fprintf (file, "\t{lm|lmw} %d,%d(1)\n", first_reg, |
1620 | - (32 - first_reg) * 4 - (64 - first_fp_reg) * 8); | |
9878760c | 1621 | |
b4ac57ab | 1622 | /* Restore fpr's if we can do it without calling a function. */ |
9878760c | 1623 | if (first_fp_reg == 62) |
85638c0d | 1624 | asm_fprintf (file, "\tlfd 30,-16(1)\n\tlfd 31,-8(1)\n"); |
9878760c | 1625 | else if (first_fp_reg == 63) |
85638c0d | 1626 | asm_fprintf (file, "\tlfd 31,-8(1)\n"); |
9878760c | 1627 | |
28edebac RK |
1628 | /* If we saved cr, restore it here. Just those of cr2, cr3, and cr4 |
1629 | that were used. */ | |
9878760c | 1630 | if (must_save_cr ()) |
85638c0d RK |
1631 | asm_fprintf (file, "\tmtcrf %d,12\n", |
1632 | (regs_ever_live[70] != 0) * 0x20 | |
1633 | + (regs_ever_live[71] != 0) * 0x10 | |
1634 | + (regs_ever_live[72] != 0) * 0x8); | |
9878760c | 1635 | |
b4ac57ab RS |
1636 | /* If we have to restore more than two FP registers, branch to the |
1637 | restore function. It will return to our caller. */ | |
1638 | if (first_fp_reg < 62) | |
85638c0d | 1639 | asm_fprintf (file, "\tb ._restf%d\n", first_fp_reg - 32); |
b4ac57ab | 1640 | else |
85638c0d | 1641 | asm_fprintf (file, "\t{br|blr}\n"); |
9878760c | 1642 | } |
b4ac57ab | 1643 | |
9b30bae2 | 1644 | /* Output a traceback table here. See /usr/include/sys/debug.h for info |
314fc5a9 ILT |
1645 | on its format. |
1646 | ||
1647 | We don't output a traceback table if -finhibit-size-directive was | |
1648 | used. The documentation for -finhibit-size-directive reads | |
1649 | ``don't output a @code{.size} assembler directive, or anything | |
1650 | else that would cause trouble if the function is split in the | |
1651 | middle, and the two halves are placed at locations far apart in | |
1652 | memory.'' The traceback table has this property, since it | |
1653 | includes the offset from the start of the function to the | |
1654 | traceback table itself. */ | |
1655 | if (! flag_inhibit_size_directive) | |
9b30bae2 | 1656 | { |
314fc5a9 ILT |
1657 | char *fname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0); |
1658 | int fixed_parms, float_parms, parm_info; | |
1659 | int i; | |
1660 | ||
1661 | /* Need label immediately before tbtab, so we can compute its offset | |
1662 | from the function start. */ | |
1663 | if (*fname == '*') | |
1664 | ++fname; | |
1665 | ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT"); | |
1666 | ASM_OUTPUT_LABEL (file, fname); | |
1667 | ||
1668 | /* The .tbtab pseudo-op can only be used for the first eight | |
1669 | expressions, since it can't handle the possibly variable | |
1670 | length fields that follow. However, if you omit the optional | |
1671 | fields, the assembler outputs zeros for all optional fields | |
1672 | anyways, giving each variable length field is minimum length | |
1673 | (as defined in sys/debug.h). Thus we can not use the .tbtab | |
1674 | pseudo-op at all. */ | |
1675 | ||
1676 | /* An all-zero word flags the start of the tbtab, for debuggers | |
1677 | that have to find it by searching forward from the entry | |
1678 | point or from the current pc. */ | |
1679 | fprintf (file, "\t.long 0\n"); | |
1680 | ||
1681 | /* Tbtab format type. Use format type 0. */ | |
1682 | fprintf (file, "\t.byte 0,"); | |
1683 | ||
1684 | /* Language type. Unfortunately, there doesn't seem to be any | |
1685 | official way to get this info, so we use language_string. C | |
1686 | is 0. C++ is 9. No number defined for Obj-C, so use the | |
1687 | value for C for now. */ | |
1688 | if (! strcmp (language_string, "GNU C") | |
1689 | || ! strcmp (language_string, "GNU Obj-C")) | |
1690 | i = 0; | |
1691 | else if (! strcmp (language_string, "GNU F77")) | |
1692 | i = 1; | |
1693 | else if (! strcmp (language_string, "GNU Ada")) | |
1694 | i = 3; | |
1695 | else if (! strcmp (language_string, "GNU PASCAL")) | |
1696 | i = 2; | |
1697 | else if (! strcmp (language_string, "GNU C++")) | |
1698 | i = 9; | |
1699 | else | |
1700 | abort (); | |
1701 | fprintf (file, "%d,", i); | |
1702 | ||
1703 | /* 8 single bit fields: global linkage (not set for C extern linkage, | |
1704 | apparently a PL/I convention?), out-of-line epilogue/prologue, offset | |
1705 | from start of procedure stored in tbtab, internal function, function | |
1706 | has controlled storage, function has no toc, function uses fp, | |
1707 | function logs/aborts fp operations. */ | |
1708 | /* Assume that fp operations are used if any fp reg must be saved. */ | |
1709 | fprintf (file, "%d,", (1 << 5) | ((first_fp_reg != 64) << 1)); | |
1710 | ||
1711 | /* 6 bitfields: function is interrupt handler, name present in | |
1712 | proc table, function calls alloca, on condition directives | |
1713 | (controls stack walks, 3 bits), saves condition reg, saves | |
1714 | link reg. */ | |
1715 | /* The `function calls alloca' bit seems to be set whenever reg 31 is | |
1716 | set up as a frame pointer, even when there is no alloca call. */ | |
1717 | fprintf (file, "%d,", | |
1718 | ((1 << 6) | (frame_pointer_needed << 5) | |
1719 | | (must_save_cr () << 1) | (regs_ever_live[65]))); | |
1720 | ||
1721 | /* 3 bitfields: saves backchain, spare bit, number of fpr saved | |
1722 | (6 bits). */ | |
1723 | fprintf (file, "%d,", | |
1724 | (must_push << 7) | (64 - first_fp_reg_to_save ())); | |
1725 | ||
1726 | /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */ | |
1727 | fprintf (file, "%d,", (32 - first_reg_to_save ())); | |
1728 | ||
1729 | { | |
1730 | /* Compute the parameter info from the function decl argument | |
1731 | list. */ | |
1732 | tree decl; | |
1733 | int next_parm_info_bit; | |
1734 | ||
1735 | next_parm_info_bit = 31; | |
1736 | parm_info = 0; | |
1737 | fixed_parms = 0; | |
1738 | float_parms = 0; | |
1739 | ||
1740 | for (decl = DECL_ARGUMENTS (current_function_decl); | |
1741 | decl; decl = TREE_CHAIN (decl)) | |
1742 | { | |
1743 | rtx parameter = DECL_INCOMING_RTL (decl); | |
1744 | enum machine_mode mode = GET_MODE (parameter); | |
1745 | ||
1746 | if (GET_CODE (parameter) == REG) | |
1747 | { | |
1748 | if (GET_MODE_CLASS (mode) == MODE_FLOAT) | |
1749 | { | |
1750 | int bits; | |
1751 | ||
1752 | float_parms++; | |
1753 | ||
1754 | if (mode == SFmode) | |
1755 | bits = 0x2; | |
1756 | else if (mode == DFmode) | |
1757 | bits = 0x3; | |
1758 | else | |
1759 | abort (); | |
1760 | ||
1761 | /* If only one bit will fit, don't or in this entry. */ | |
1762 | if (next_parm_info_bit > 0) | |
1763 | parm_info |= (bits << (next_parm_info_bit - 1)); | |
1764 | next_parm_info_bit -= 2; | |
1765 | } | |
1766 | else | |
1767 | { | |
1768 | fixed_parms += ((GET_MODE_SIZE (mode) | |
1769 | + (UNITS_PER_WORD - 1)) | |
1770 | / UNITS_PER_WORD); | |
1771 | next_parm_info_bit -= 1; | |
1772 | } | |
1773 | } | |
1774 | } | |
1775 | } | |
1776 | ||
1777 | /* Number of fixed point parameters. */ | |
1778 | /* This is actually the number of words of fixed point parameters; thus | |
1779 | an 8 byte struct counts as 2; and thus the maximum value is 8. */ | |
1780 | fprintf (file, "%d,", fixed_parms); | |
1781 | ||
1782 | /* 2 bitfields: number of floating point parameters (7 bits), parameters | |
1783 | all on stack. */ | |
1784 | /* This is actually the number of fp registers that hold parameters; | |
1785 | and thus the maximum value is 13. */ | |
1786 | /* Set parameters on stack bit if parameters are not in their original | |
1787 | registers, regardless of whether they are on the stack? Xlc | |
1788 | seems to set the bit when not optimizing. */ | |
1789 | fprintf (file, "%d\n", ((float_parms << 1) | (! optimize))); | |
1790 | ||
1791 | /* Optional fields follow. Some are variable length. */ | |
1792 | ||
1793 | /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float, | |
1794 | 11 double float. */ | |
1795 | /* There is an entry for each parameter in a register, in the order that | |
1796 | they occur in the parameter list. Any intervening arguments on the | |
1797 | stack are ignored. If the list overflows a long (max possible length | |
1798 | 34 bits) then completely leave off all elements that don't fit. */ | |
1799 | /* Only emit this long if there was at least one parameter. */ | |
1800 | if (fixed_parms || float_parms) | |
1801 | fprintf (file, "\t.long %d\n", parm_info); | |
1802 | ||
1803 | /* Offset from start of code to tb table. */ | |
1804 | fprintf (file, "\t.long "); | |
1805 | ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT"); | |
1806 | RS6000_OUTPUT_BASENAME (file, fname); | |
1807 | fprintf (file, "-."); | |
1808 | RS6000_OUTPUT_BASENAME (file, fname); | |
1809 | fprintf (file, "\n"); | |
1810 | ||
1811 | /* Interrupt handler mask. */ | |
1812 | /* Omit this long, since we never set the interrupt handler bit | |
1813 | above. */ | |
1814 | ||
1815 | /* Number of CTL (controlled storage) anchors. */ | |
1816 | /* Omit this long, since the has_ctl bit is never set above. */ | |
1817 | ||
1818 | /* Displacement into stack of each CTL anchor. */ | |
1819 | /* Omit this list of longs, because there are no CTL anchors. */ | |
1820 | ||
1821 | /* Length of function name. */ | |
1822 | fprintf (file, "\t.short %d\n", strlen (fname)); | |
1823 | ||
1824 | /* Function name. */ | |
1825 | assemble_string (fname, strlen (fname)); | |
1826 | ||
1827 | /* Register for alloca automatic storage; this is always reg 31. | |
1828 | Only emit this if the alloca bit was set above. */ | |
1829 | if (frame_pointer_needed) | |
1830 | fprintf (file, "\t.byte 31\n"); | |
9b30bae2 | 1831 | } |
9878760c RK |
1832 | } |
1833 | \f | |
1834 | /* Output a TOC entry. We derive the entry name from what is | |
1835 | being written. */ | |
1836 | ||
1837 | void | |
1838 | output_toc (file, x, labelno) | |
1839 | FILE *file; | |
1840 | rtx x; | |
1841 | int labelno; | |
1842 | { | |
1843 | char buf[256]; | |
1844 | char *name = buf; | |
1845 | rtx base = x; | |
1846 | int offset = 0; | |
1847 | ||
1848 | ASM_OUTPUT_INTERNAL_LABEL (file, "LC", labelno); | |
1849 | ||
37c37a57 RK |
1850 | /* Handle FP constants specially. Note that if we have a minimal |
1851 | TOC, things we put here aren't actually in the TOC, so we can allow | |
1852 | FP constants. */ | |
9878760c RK |
1853 | if (GET_CODE (x) == CONST_DOUBLE |
1854 | && GET_MODE (x) == DFmode | |
1855 | && TARGET_FLOAT_FORMAT == HOST_FLOAT_FORMAT | |
1856 | && BITS_PER_WORD == HOST_BITS_PER_INT | |
37c37a57 | 1857 | && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC)) |
9878760c | 1858 | { |
1875cc88 JW |
1859 | if (TARGET_MINIMAL_TOC) |
1860 | fprintf (file, "\t.long %d\n\t.long %d\n", | |
1861 | CONST_DOUBLE_LOW (x), CONST_DOUBLE_HIGH (x)); | |
1862 | else | |
1863 | fprintf (file, "\t.tc FD_%x_%x[TC],%d,%d\n", | |
1864 | CONST_DOUBLE_LOW (x), CONST_DOUBLE_HIGH (x), | |
1865 | CONST_DOUBLE_LOW (x), CONST_DOUBLE_HIGH (x)); | |
9878760c RK |
1866 | return; |
1867 | } | |
1868 | else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode | |
37c37a57 | 1869 | && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC)) |
9878760c RK |
1870 | { |
1871 | rtx val = operand_subword (x, 0, 0, SFmode); | |
1872 | ||
1873 | if (val == 0 || GET_CODE (val) != CONST_INT) | |
1874 | abort (); | |
1875 | ||
1875cc88 JW |
1876 | if (TARGET_MINIMAL_TOC) |
1877 | fprintf (file, "\t.long %d\n", INTVAL (val)); | |
1878 | else | |
1879 | fprintf (file, "\t.tc FS_%x[TC],%d\n", INTVAL (val), INTVAL (val)); | |
9878760c RK |
1880 | return; |
1881 | } | |
1882 | ||
1883 | if (GET_CODE (x) == CONST) | |
1884 | { | |
1885 | base = XEXP (XEXP (x, 0), 0); | |
1886 | offset = INTVAL (XEXP (XEXP (x, 0), 1)); | |
1887 | } | |
1888 | ||
1889 | if (GET_CODE (base) == SYMBOL_REF) | |
1890 | name = XSTR (base, 0); | |
1891 | else if (GET_CODE (base) == LABEL_REF) | |
1892 | ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (XEXP (base, 0))); | |
1893 | else if (GET_CODE (base) == CODE_LABEL) | |
1894 | ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (base)); | |
1895 | else | |
1896 | abort (); | |
1897 | ||
1875cc88 JW |
1898 | if (TARGET_MINIMAL_TOC) |
1899 | fprintf (file, "\t.long "); | |
1900 | else | |
1901 | { | |
1902 | fprintf (file, "\t.tc "); | |
1903 | RS6000_OUTPUT_BASENAME (file, name); | |
9878760c | 1904 | |
1875cc88 JW |
1905 | if (offset < 0) |
1906 | fprintf (file, ".N%d", - offset); | |
1907 | else if (offset) | |
1908 | fprintf (file, ".P%d", offset); | |
9878760c | 1909 | |
1875cc88 JW |
1910 | fprintf (file, "[TC],"); |
1911 | } | |
9878760c RK |
1912 | output_addr_const (file, x); |
1913 | fprintf (file, "\n"); | |
1914 | } | |
1915 | \f | |
1916 | /* Output an assembler pseudo-op to write an ASCII string of N characters | |
1917 | starting at P to FILE. | |
1918 | ||
1919 | On the RS/6000, we have to do this using the .byte operation and | |
1920 | write out special characters outside the quoted string. | |
1921 | Also, the assembler is broken; very long strings are truncated, | |
1922 | so we must artificially break them up early. */ | |
1923 | ||
1924 | void | |
1925 | output_ascii (file, p, n) | |
1926 | FILE *file; | |
1927 | char *p; | |
1928 | int n; | |
1929 | { | |
1930 | char c; | |
1931 | int i, count_string; | |
1932 | char *for_string = "\t.byte \""; | |
1933 | char *for_decimal = "\t.byte "; | |
1934 | char *to_close = NULL; | |
1935 | ||
1936 | count_string = 0; | |
1937 | for (i = 0; i < n; i++) | |
1938 | { | |
1939 | c = *p++; | |
1940 | if (c >= ' ' && c < 0177) | |
1941 | { | |
1942 | if (for_string) | |
1943 | fputs (for_string, file); | |
1944 | putc (c, file); | |
1945 | ||
1946 | /* Write two quotes to get one. */ | |
1947 | if (c == '"') | |
1948 | { | |
1949 | putc (c, file); | |
1950 | ++count_string; | |
1951 | } | |
1952 | ||
1953 | for_string = NULL; | |
1954 | for_decimal = "\"\n\t.byte "; | |
1955 | to_close = "\"\n"; | |
1956 | ++count_string; | |
1957 | ||
1958 | if (count_string >= 512) | |
1959 | { | |
1960 | fputs (to_close, file); | |
1961 | ||
1962 | for_string = "\t.byte \""; | |
1963 | for_decimal = "\t.byte "; | |
1964 | to_close = NULL; | |
1965 | count_string = 0; | |
1966 | } | |
1967 | } | |
1968 | else | |
1969 | { | |
1970 | if (for_decimal) | |
1971 | fputs (for_decimal, file); | |
1972 | fprintf (file, "%d", c); | |
1973 | ||
1974 | for_string = "\n\t.byte \""; | |
1975 | for_decimal = ", "; | |
1976 | to_close = "\n"; | |
1977 | count_string = 0; | |
1978 | } | |
1979 | } | |
1980 | ||
1981 | /* Now close the string if we have written one. Then end the line. */ | |
1982 | if (to_close) | |
1983 | fprintf (file, to_close); | |
1984 | } | |
1985 | \f | |
1986 | /* Generate a unique section name for FILENAME for a section type | |
1987 | represented by SECTION_DESC. Output goes into BUF. | |
1988 | ||
1989 | SECTION_DESC can be any string, as long as it is different for each | |
1990 | possible section type. | |
1991 | ||
1992 | We name the section in the same manner as xlc. The name begins with an | |
1993 | underscore followed by the filename (after stripping any leading directory | |
11e5fe42 RK |
1994 | names) with the last period replaced by the string SECTION_DESC. If |
1995 | FILENAME does not contain a period, SECTION_DESC is appended to the end of | |
1996 | the name. */ | |
9878760c RK |
1997 | |
1998 | void | |
1999 | rs6000_gen_section_name (buf, filename, section_desc) | |
2000 | char **buf; | |
2001 | char *filename; | |
2002 | char *section_desc; | |
2003 | { | |
11e5fe42 | 2004 | char *q, *after_last_slash, *last_period; |
9878760c RK |
2005 | char *p; |
2006 | int len; | |
9878760c RK |
2007 | |
2008 | after_last_slash = filename; | |
2009 | for (q = filename; *q; q++) | |
11e5fe42 RK |
2010 | { |
2011 | if (*q == '/') | |
2012 | after_last_slash = q + 1; | |
2013 | else if (*q == '.') | |
2014 | last_period = q; | |
2015 | } | |
9878760c | 2016 | |
11e5fe42 | 2017 | len = strlen (after_last_slash) + strlen (section_desc) + 2; |
9878760c RK |
2018 | *buf = (char *) permalloc (len); |
2019 | ||
2020 | p = *buf; | |
2021 | *p++ = '_'; | |
2022 | ||
2023 | for (q = after_last_slash; *q; q++) | |
2024 | { | |
11e5fe42 | 2025 | if (q == last_period) |
9878760c RK |
2026 | { |
2027 | strcpy (p, section_desc); | |
2028 | p += strlen (section_desc); | |
9878760c RK |
2029 | } |
2030 | ||
2031 | else if (isalnum (*q)) | |
2032 | *p++ = *q; | |
2033 | } | |
2034 | ||
11e5fe42 | 2035 | if (last_period == 0) |
9878760c RK |
2036 | strcpy (p, section_desc); |
2037 | else | |
2038 | *p = '\0'; | |
2039 | } | |
e165f3f0 RK |
2040 | \f |
2041 | /* Write function profiler code. */ | |
2042 | ||
2043 | void | |
2044 | output_function_profiler (file, labelno) | |
2045 | FILE *file; | |
2046 | int labelno; | |
2047 | { | |
2048 | /* The last used parameter register. */ | |
2049 | int last_parm_reg; | |
2050 | int i, j; | |
3daf36a4 | 2051 | char buf[100]; |
e165f3f0 RK |
2052 | |
2053 | /* Set up a TOC entry for the profiler label. */ | |
2054 | toc_section (); | |
3daf36a4 ILT |
2055 | ASM_OUTPUT_INTERNAL_LABEL (file, "LPC", labelno); |
2056 | ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno); | |
35fc1624 | 2057 | if (TARGET_MINIMAL_TOC) |
3daf36a4 ILT |
2058 | { |
2059 | fprintf (file, "\t.long "); | |
2060 | assemble_name (file, buf); | |
2061 | fprintf (file, "\n"); | |
2062 | } | |
35fc1624 | 2063 | else |
3daf36a4 ILT |
2064 | { |
2065 | fprintf (file, "\t.tc\t"); | |
2066 | assemble_name (file, buf); | |
2067 | fprintf (file, "[TC],"); | |
2068 | assemble_name (file, buf); | |
2069 | fprintf (file, "\n"); | |
2070 | } | |
e165f3f0 RK |
2071 | text_section (); |
2072 | ||
2073 | /* Figure out last used parameter register. The proper thing to do is | |
2074 | to walk incoming args of the function. A function might have live | |
2075 | parameter registers even if it has no incoming args. */ | |
2076 | ||
2077 | for (last_parm_reg = 10; | |
2078 | last_parm_reg > 2 && ! regs_ever_live [last_parm_reg]; | |
2079 | last_parm_reg--) | |
2080 | ; | |
2081 | ||
2082 | /* Save parameter registers in regs 23-30. Don't overwrite reg 31, since | |
2083 | it might be set up as the frame pointer. */ | |
2084 | ||
2085 | for (i = 3, j = 30; i <= last_parm_reg; i++, j--) | |
2086 | fprintf (file, "\tai %d,%d,0\n", j, i); | |
2087 | ||
2088 | /* Load location address into r3, and call mcount. */ | |
2089 | ||
3daf36a4 ILT |
2090 | ASM_GENERATE_INTERNAL_LABEL (buf, "LPC", labelno); |
2091 | fprintf (file, "\tl 3,"); | |
2092 | assemble_name (file, buf); | |
2093 | fprintf (file, "(2)\n\tbl .mcount\n"); | |
e165f3f0 RK |
2094 | |
2095 | /* Restore parameter registers. */ | |
2096 | ||
2097 | for (i = 3, j = 30; i <= last_parm_reg; i++, j--) | |
2098 | fprintf (file, "\tai %d,%d,0\n", i, j); | |
2099 | } | |
a251ffd0 TG |
2100 | |
2101 | /* Adjust the cost of a scheduling dependency. Return the new cost of | |
2102 | a dependency LINK or INSN on DEP_INSN. COST is the current cost. */ | |
2103 | ||
2104 | int | |
a06faf84 | 2105 | rs6000_adjust_cost (insn, link, dep_insn, cost) |
a251ffd0 TG |
2106 | rtx insn; |
2107 | rtx link; | |
2108 | rtx dep_insn; | |
2109 | int cost; | |
2110 | { | |
2111 | if (! recog_memoized (insn)) | |
2112 | return 0; | |
2113 | ||
2114 | if (REG_NOTE_KIND (link) != 0) | |
2115 | return 0; | |
2116 | ||
2117 | if (REG_NOTE_KIND (link) == 0) | |
2118 | { | |
2119 | /* Data dependency; DEP_INSN writes a register that INSN reads some | |
2120 | cycles later. */ | |
2121 | ||
2122 | /* Tell the first scheduling pass about the latency between a mtctr | |
2123 | and bctr (and mtlr and br/blr). The first scheduling pass will not | |
2124 | know about this latency since the mtctr instruction, which has the | |
2125 | latency associated to it, will be generated by reload. */ | |
2126 | if (get_attr_type (insn) == TYPE_JMPREG) | |
2127 | return TARGET_POWER ? 5 : 4; | |
2128 | ||
2129 | /* Fall out to return default cost. */ | |
2130 | } | |
2131 | ||
2132 | return cost; | |
2133 | } |