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9878760c 1/* Subroutines used for code generation on IBM RS/6000.
cf27b467 2 Copyright (C) 1991, 1993, 1994, 1995, 1996 Free Software Foundation, Inc.
fab3bcc3 3 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
9878760c
RK		 4
5This file is part of GNU CC.
6
7GNU CC is free software; you can redistribute it and/or modify
8it under the terms of the GNU General Public License as published by
9the Free Software Foundation; either version 2, or (at your option)
10any later version.
11
12GNU CC is distributed in the hope that it will be useful,
13but WITHOUT ANY WARRANTY; without even the implied warranty of
14MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15GNU General Public License for more details.
16
17You should have received a copy of the GNU General Public License
18along with GNU CC; see the file COPYING. If not, write to
c15c9075
RK		 19the Free Software Foundation, 59 Temple Place - Suite 330,
20Boston, MA 02111-1307, USA. */
9878760c
RK		 21
22#include <stdio.h>
127b0efc 23#include <ctype.h>
9878760c
RK		 24#include "config.h"
25#include "rtl.h"
26#include "regs.h"
27#include "hard-reg-set.h"
28#include "real.h"
29#include "insn-config.h"
30#include "conditions.h"
31#include "insn-flags.h"
32#include "output.h"
33#include "insn-attr.h"
34#include "flags.h"
35#include "recog.h"
36#include "expr.h"
37#include "obstack.h"
9b30bae2
JW		 38#include "tree.h"
39
7509c759
MM		 40#ifndef TARGET_NO_PROTOTYPE
41#define TARGET_NO_PROTOTYPE 0
42#endif
43
9b30bae2 44extern char *language_string;
5248c961 45extern int profile_block_flag;
9878760c
RK		 46
47#define min(A,B) ((A) < (B) ? (A) : (B))
48#define max(A,B) ((A) > (B) ? (A) : (B))
49
5248c961
RK		 50/* Target cpu type */
51
52enum processor_type rs6000_cpu;
8e3f41e7
MM		 53struct rs6000_cpu_select rs6000_select[3] =
54{
55 /* switch name, tune arch */
5d6426e0 56 { (char *)0, "--with-cpu=", 1, 1 },
8e3f41e7
MM		 57 { (char *)0, "-mcpu=", 1, 1 },
58 { (char *)0, "-mtune=", 1, 0 },
59};
5248c961 60
9878760c
RK		 61/* Set to non-zero by "fix" operation to indicate that itrunc and
62 uitrunc must be defined. */
63
64int rs6000_trunc_used;
65
66/* Set to non-zero once they have been defined. */
67
68static int trunc_defined;
69
c764f757
RK		 70/* Set to non-zero once AIX common-mode calls have been defined. */
71static int common_mode_defined;
c81bebd7 72
9878760c
RK		 73/* Save information from a "cmpxx" operation until the branch or scc is
74 emitted. */
9878760c
RK		 75rtx rs6000_compare_op0, rs6000_compare_op1;
76int rs6000_compare_fp_p;
874a0744
MM		 77
78#ifdef USING_SVR4_H
79/* Label number of label created for -mrelocatable, to call to so we can
80 get the address of the GOT section */
81int rs6000_pic_labelno;
c81bebd7
MM		 82
83/* Which abi to adhere to */
84char *rs6000_abi_name = RS6000_ABI_NAME;
874a0744 85#endif
4697a36c
MM		 86
87/* Whether a System V.4 varargs area was created. */
88int rs6000_sysv_varargs_p;
8f75773e 89
b6c9286a
MM		 90/* Whether we need to save the TOC register. */
91int rs6000_save_toc_p;
92
93/* ABI enumeration available for subtarget to use. */
94enum rs6000_abi rs6000_current_abi;
95
8f75773e 96/* Temporary memory used to convert integer -> float */
5b5040b9 97static rtx stack_temps[NUM_MACHINE_MODES];
8f75773e 98
766a866c
MM		 99/* Current PIC register used by the V4 code */
100struct rtx_def *rs6000_pic_register = (struct rtx_def *)0;
101
c81bebd7
MM		 102\f
103/* Default register names. */
104char rs6000_reg_names[][8] =
105{
106 "0", "1", "2", "3", "4", "5", "6", "7",
107 "8", "9", "10", "11", "12", "13", "14", "15",
108 "16", "17", "18", "19", "20", "21", "22", "23",
109 "24", "25", "26", "27", "28", "29", "30", "31",
110 "0", "1", "2", "3", "4", "5", "6", "7",
111 "8", "9", "10", "11", "12", "13", "14", "15",
112 "16", "17", "18", "19", "20", "21", "22", "23",
113 "24", "25", "26", "27", "28", "29", "30", "31",
114 "mq", "lr", "ctr","ap",
115 "0", "1", "2", "3", "4", "5", "6", "7"
116};
117
118#ifdef TARGET_REGNAMES
119static char alt_reg_names[][8] =
120{
121 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7",
122 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
123 "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23",
124 "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31",
125 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7",
126 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15",
127 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23",
128 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31",
129 "mq", "lr", "ctr", "ap",
130 "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7"
131};
132#endif
133
134
24d304eb
RK		 135\f
136/* Print the options used in the assembly file. */
137
138extern char *version_string, *language_string;
139
caf44502 140struct asm_option
24d304eb
RK		 141{
142 char *string;
143 int *variable;
144 int on_value;
145};
146
147#define MAX_LINE 79
148
149static int
150output_option (file, type, name, pos)
151 FILE *file;
152 char *type;
153 char *name;
154 int pos;
155{
156 int type_len = strlen (type);
157 int name_len = strlen (name);
158
159 if (1 + type_len + name_len + pos > MAX_LINE)
160 {
161 fprintf (file, "\n # %s%s", type, name);
162 return 3 + type_len + name_len;
163 }
164 fprintf (file, " %s%s", type, name);
165 return pos + 1 + type_len + name_len;
166}
167
168static struct { char *name; int value; } m_options[] = TARGET_SWITCHES;
169
170void
171output_options (file, f_options, f_len, W_options, W_len)
172 FILE *file;
caf44502 173 struct asm_option *f_options;
24d304eb 174 int f_len;
caf44502 175 struct asm_option *W_options;
24d304eb
RK		 176 int W_len;
177{
178 int j;
179 int flags = target_flags;
180 int pos = 32767;
181
182 fprintf (file, " # %s %s", language_string, version_string);
183
184 if (optimize)
185 {
186 char opt_string[20];
187 sprintf (opt_string, "%d", optimize);
188 pos = output_option (file, "-O", opt_string, pos);
189 }
190
191 if (profile_flag)
192 pos = output_option (file, "-p", "", pos);
193
194 if (profile_block_flag)
195 pos = output_option (file, "-a", "", pos);
196
197 if (inhibit_warnings)
198 pos = output_option (file, "-w", "", pos);
199
200 for (j = 0; j < f_len; j++)
201 {
202 if (*f_options[j].variable == f_options[j].on_value)
203 pos = output_option (file, "-f", f_options[j].string, pos);
204 }
205
206 for (j = 0; j < W_len; j++)
207 {
208 if (*W_options[j].variable == W_options[j].on_value)
209 pos = output_option (file, "-W", W_options[j].string, pos);
210 }
211
212 for (j = 0; j < sizeof m_options / sizeof m_options[0]; j++)
213 {
214 if (m_options[j].name[0] != '\0'
215 && m_options[j].value > 0
216 && ((m_options[j].value & flags) == m_options[j].value))
217 {
218 pos = output_option (file, "-m", m_options[j].name, pos);
219 flags &= ~ m_options[j].value;
220 }
221 }
222
8e3f41e7
MM		 223 for (j = 0; j < sizeof (rs6000_select) / sizeof(rs6000_select[0]); j++)
224 if (rs6000_select[j].string != (char *)0)
225 pos = output_option (file, rs6000_select[j].name, rs6000_select[j].string, pos);
24d304eb
RK		 226
227 fputs ("\n\n", file);
228}
229
9878760c 230\f
5248c961
RK		 231/* Override command line options. Mostly we process the processor
232 type and sometimes adjust other TARGET_ options. */
233
234void
8e3f41e7
MM		 235rs6000_override_options (default_cpu)
236 char *default_cpu;
5248c961 237{
8e3f41e7
MM		 238 int i, j;
239 struct rs6000_cpu_select *ptr;
5248c961 240
85638c0d
RK		 241 /* Simplify the entries below by making a mask for any POWER
242 variant and any PowerPC variant. */
243
938937d8 244#define POWER_MASKS (MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING)
68c49ffa
RK		 245#define POWERPC_MASKS (MASK_POWERPC | MASK_PPC_GPOPT \
246 | MASK_PPC_GFXOPT | MASK_POWERPC64)
247#define POWERPC_OPT_MASKS (MASK_PPC_GPOPT | MASK_PPC_GFXOPT)
85638c0d 248
5248c961
RK		 249 static struct ptt
250 {
251 char *name; /* Canonical processor name. */
252 enum processor_type processor; /* Processor type enum value. */
253 int target_enable; /* Target flags to enable. */
254 int target_disable; /* Target flags to disable. */
255 } processor_target_table[]
cf27b467
MM		 256 = {{"common", PROCESSOR_COMMON, MASK_NEW_MNEMONICS,
257 POWER_MASKS | POWERPC_MASKS},
db7f1e43 258 {"power", PROCESSOR_POWER,
938937d8 259 MASK_POWER | MASK_MULTIPLE | MASK_STRING,
db7f1e43 260 MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS},
8e3f41e7
MM		 261 {"power2", PROCESSOR_POWER,
262 MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING,
263 POWERPC_MASKS | MASK_NEW_MNEMONICS},
db7f1e43
RK		 264 {"powerpc", PROCESSOR_POWERPC,
265 MASK_POWERPC | MASK_NEW_MNEMONICS,
68c49ffa 266 POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64},
db7f1e43 267 {"rios", PROCESSOR_RIOS1,
938937d8 268 MASK_POWER | MASK_MULTIPLE | MASK_STRING,
db7f1e43
RK		 269 MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS},
270 {"rios1", PROCESSOR_RIOS1,
938937d8 271 MASK_POWER | MASK_MULTIPLE | MASK_STRING,
db7f1e43
RK		 272 MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS},
273 {"rsc", PROCESSOR_PPC601,
938937d8 274 MASK_POWER | MASK_MULTIPLE | MASK_STRING,
db7f1e43
RK		 275 MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS},
276 {"rsc1", PROCESSOR_PPC601,
938937d8 277 MASK_POWER | MASK_MULTIPLE | MASK_STRING,
db7f1e43
RK		 278 MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS},
279 {"rios2", PROCESSOR_RIOS2,
938937d8 280 MASK_POWER | MASK_MULTIPLE | MASK_STRING | MASK_POWER2,
db7f1e43 281 POWERPC_MASKS | MASK_NEW_MNEMONICS},
49a0b204
MM		 282 {"403", PROCESSOR_PPC403,
283 MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS,
284 POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64},
cf27b467
MM		 285 {"505", PROCESSOR_MPCCORE,
286 MASK_POWERPC | MASK_NEW_MNEMONICS,
287 POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64},
5248c961 288 {"601", PROCESSOR_PPC601,
938937d8 289 MASK_POWER | MASK_POWERPC | MASK_NEW_MNEMONICS | MASK_MULTIPLE | MASK_STRING,
68c49ffa 290 MASK_POWER2 | POWERPC_OPT_MASKS | MASK_POWERPC64},
1ec26da6 291 {"602", PROCESSOR_PPC603,
cf27b467
MM		 292 MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
293 POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64},
5248c961 294 {"603", PROCESSOR_PPC603,
68c49ffa
RK		 295 MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
296 POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64},
b6c9286a
MM		 297 {"603e", PROCESSOR_PPC603,
298 MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
299 POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64},
5248c961 300 {"604", PROCESSOR_PPC604,
b6c9286a
MM		 301 MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
302 POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64},
303 {"620", PROCESSOR_PPC620,
68c49ffa 304 MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
cf27b467
MM		 305 POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64},
306 {"821", PROCESSOR_MPCCORE,
307 MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS,
308 POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64},
309 {"860", PROCESSOR_MPCCORE,
310 MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS,
311 POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}};
5248c961
RK		 312
313 int ptt_size = sizeof (processor_target_table) / sizeof (struct ptt);
314
8a61d227 315 int multiple = TARGET_MULTIPLE; /* save current -mmultiple/-mno-multiple status */
938937d8 316 int string = TARGET_STRING; /* save current -mstring/-mno-string status */
8a61d227 317
5248c961
RK		 318 profile_block_flag = 0;
319
320 /* Identify the processor type */
8e3f41e7
MM		 321 rs6000_select[0].string = default_cpu;
322 rs6000_cpu = PROCESSOR_DEFAULT;
8e3f41e7
MM		 323
324 for (i = 0; i < sizeof (rs6000_select) / sizeof (rs6000_select[0]); i++)
5248c961 325 {
8e3f41e7
MM		 326 ptr = &rs6000_select[i];
327 if (ptr->string != (char *)0 && ptr->string[0] != '\0')
5248c961 328 {
8e3f41e7
MM		 329 for (j = 0; j < ptt_size; j++)
330 if (! strcmp (ptr->string, processor_target_table[j].name))
331 {
332 if (ptr->set_tune_p)
333 rs6000_cpu = processor_target_table[j].processor;
334
335 if (ptr->set_arch_p)
336 {
337 target_flags |= processor_target_table[j].target_enable;
338 target_flags &= ~processor_target_table[j].target_disable;
339 }
340 break;
341 }
342
343 if (i == ptt_size)
344 error ("bad value (%s) for %s switch", ptr->string, ptr->name);
5248c961
RK		 345 }
346 }
8a61d227
MM		 347
348 /* If -mmultiple or -mno-multiple was explicitly used, don't
349 override with the processor default */
350 if (TARGET_MULTIPLE_SET)
351 target_flags = (target_flags & ~MASK_MULTIPLE) | multiple;
7e69e155 352
938937d8
MM		 353 /* If -mstring or -mno-string was explicitly used, don't
354 override with the processor default */
355 if (TARGET_STRING_SET)
1f5515bf 356 target_flags = (target_flags & ~MASK_STRING) | string;
938937d8 357
7e69e155
MM		 358 /* Don't allow -mmultiple or -mstring on little endian systems, because the
359 hardware doesn't support the instructions used in little endian mode */
360 if (!BYTES_BIG_ENDIAN)
361 {
362 if (TARGET_MULTIPLE)
363 {
364 target_flags &= ~MASK_MULTIPLE;
365 if (TARGET_MULTIPLE_SET)
366 warning ("-mmultiple is not supported on little endian systems");
367 }
368
369 if (TARGET_STRING)
370 {
371 target_flags &= ~MASK_STRING;
938937d8
MM		 372 if (TARGET_STRING_SET)
373 warning ("-mstring is not supported on little endian systems");
7e69e155
MM		 374 }
375 }
3933e0e1 376
c81bebd7
MM		 377#ifdef TARGET_REGNAMES
378 /* If the user desires alternate register names, copy in the alternate names
379 now. */
380 if (TARGET_REGNAMES)
381 bcopy ((char *)alt_reg_names, (char *)rs6000_reg_names, sizeof (rs6000_reg_names));
382#endif
383
3933e0e1
MM		 384#ifdef SUBTARGET_OVERRIDE_OPTIONS
385 SUBTARGET_OVERRIDE_OPTIONS;
386#endif
5248c961 387}
24d304eb
RK		 388\f
389/* Create a CONST_DOUBLE from a string. */
390
391struct rtx_def *
392rs6000_float_const (string, mode)
393 char *string;
394 enum machine_mode mode;
395{
396 REAL_VALUE_TYPE value = REAL_VALUE_ATOF (string, mode);
397 return immed_real_const_1 (value, mode);
398}
399
75814ad4
MM		 400\f
401/* Create a CONST_DOUBLE like immed_double_const, except reverse the
402 two parts of the constant if the target is little endian. */
403
d679bebf
RK		 404struct rtx_def *
405rs6000_immed_double_const (i0, i1, mode)
75814ad4
MM		 406 HOST_WIDE_INT i0, i1;
407 enum machine_mode mode;
408{
409 if (! WORDS_BIG_ENDIAN)
410 return immed_double_const (i1, i0, mode);
411
412 return immed_double_const (i0, i1, mode);
413}
414
5248c961 415\f
9878760c
RK		 416/* Return non-zero if this function is known to have a null epilogue. */
417
418int
419direct_return ()
420{
4697a36c
MM		 421 if (reload_completed)
422 {
423 rs6000_stack_t *info = rs6000_stack_info ();
424
425 if (info->first_gp_reg_save == 32
426 && info->first_fp_reg_save == 64
427 && !info->lr_save_p
1b4a2731 428 && !info->cr_save_p
4697a36c
MM		 429 && !info->push_p)
430 return 1;
431 }
432
433 return 0;
9878760c
RK		 434}
435
436/* Returns 1 always. */
437
438int
439any_operand (op, mode)
440 register rtx op;
441 enum machine_mode mode;
442{
443 return 1;
444}
445
b6c9286a
MM		 446/* Returns 1 if op is the count register */
447int count_register_operand(op, mode)
448 register rtx op;
449 enum machine_mode mode;
450{
451 if (GET_CODE (op) != REG)
452 return 0;
453
454 if (REGNO (op) == COUNT_REGISTER_REGNUM)
455 return 1;
456
457 if (REGNO (op) > FIRST_PSEUDO_REGISTER)
458 return 1;
459
460 return 0;
461}
462
9878760c
RK		 463/* Return 1 if OP is a constant that can fit in a D field. */
464
465int
466short_cint_operand (op, mode)
467 register rtx op;
468 enum machine_mode mode;
469{
470 return (GET_CODE (op) == CONST_INT
471 && (unsigned) (INTVAL (op) + 0x8000) < 0x10000);
472}
473
474/* Similar for a unsigned D field. */
475
476int
477u_short_cint_operand (op, mode)
478 register rtx op;
479 enum machine_mode mode;
480{
481 return (GET_CODE (op) == CONST_INT && (INTVAL (op) & 0xffff0000) == 0);
482}
483
dcfedcd0
RK		 484/* Return 1 if OP is a CONST_INT that cannot fit in a signed D field. */
485
486int
487non_short_cint_operand (op, mode)
488 register rtx op;
489 enum machine_mode mode;
490{
491 return (GET_CODE (op) == CONST_INT
492 && (unsigned) (INTVAL (op) + 0x8000) >= 0x10000);
493}
494
9878760c
RK		 495/* Returns 1 if OP is a register that is not special (i.e., not MQ,
496 ctr, or lr). */
497
498int
cd2b37d9 499gpc_reg_operand (op, mode)
9878760c
RK		 500 register rtx op;
501 enum machine_mode mode;
502{
503 return (register_operand (op, mode)
504 && (GET_CODE (op) != REG || REGNO (op) >= 67 || REGNO (op) < 64));
505}
506
507/* Returns 1 if OP is either a pseudo-register or a register denoting a
508 CR field. */
509
510int
511cc_reg_operand (op, mode)
512 register rtx op;
513 enum machine_mode mode;
514{
515 return (register_operand (op, mode)
516 && (GET_CODE (op) != REG
517 || REGNO (op) >= FIRST_PSEUDO_REGISTER
518 || CR_REGNO_P (REGNO (op))));
519}
520
521/* Returns 1 if OP is either a constant integer valid for a D-field or a
522 non-special register. If a register, it must be in the proper mode unless
523 MODE is VOIDmode. */
524
525int
526reg_or_short_operand (op, mode)
527 register rtx op;
528 enum machine_mode mode;
529{
f5a28898 530 return short_cint_operand (op, mode) || gpc_reg_operand (op, mode);
9878760c
RK		 531}
532
533/* Similar, except check if the negation of the constant would be valid for
534 a D-field. */
535
536int
537reg_or_neg_short_operand (op, mode)
538 register rtx op;
539 enum machine_mode mode;
540{
541 if (GET_CODE (op) == CONST_INT)
542 return CONST_OK_FOR_LETTER_P (INTVAL (op), 'P');
543
cd2b37d9 544 return gpc_reg_operand (op, mode);
9878760c
RK		 545}
546
547/* Return 1 if the operand is either a register or an integer whose high-order
548 16 bits are zero. */
549
550int
551reg_or_u_short_operand (op, mode)
552 register rtx op;
553 enum machine_mode mode;
554{
555 if (GET_CODE (op) == CONST_INT
556 && (INTVAL (op) & 0xffff0000) == 0)
557 return 1;
558
cd2b37d9 559 return gpc_reg_operand (op, mode);
9878760c
RK		 560}
561
562/* Return 1 is the operand is either a non-special register or ANY
563 constant integer. */
564
565int
566reg_or_cint_operand (op, mode)
567 register rtx op;
568 enum machine_mode mode;
569{
cd2b37d9 570 return GET_CODE (op) == CONST_INT || gpc_reg_operand (op, mode);
9878760c
RK		 571}
572
766a866c
MM		 573/* Return 1 if the operand is an operand that can be loaded via the GOT */
574
575int
576got_operand (op, mode)
577 register rtx op;
578 enum machine_mode mode;
579{
580 return (GET_CODE (op) == SYMBOL_REF
581 || GET_CODE (op) == CONST
582 || GET_CODE (op) == LABEL_REF);
583}
584
4e74d8ec
MM		 585/* Return the number of instructions it takes to form a constant in an
586 integer register. */
587
588static int
589num_insns_constant_wide (value)
590 HOST_WIDE_INT value;
591{
592 /* signed constant loadable with {cal|addi} */
593 if (((unsigned HOST_WIDE_INT)value + 0x8000) < 0x10000)
594 return 1;
595
596#if HOST_BITS_PER_WIDE_INT == 32
597 /* constant loadable with {cau|addis} */
598 else if ((value & 0xffff) == 0)
599 return 1;
600
601#else
602 /* constant loadable with {cau|addis} */
603 else if ((value & 0xffff) == 0 && (value & ~0xffffffff) == 0)
604 return 1;
605
606 else if (TARGET_64BIT)
607 {
608 HOST_WIDE_INT low = value & 0xffffffff;
609 HOST_WIDE_INT high = value >> 32;
610
611 if (high == 0 && (low & 0x80000000) == 0)
612 return 2;
613
614 else if (high == 0xffffffff && (low & 0x80000000) != 0)
615 return 2;
616
617 else if (!low)
618 return num_insns_constant_wide (high) + 1;
619
620 else
621 return (num_insns_constant_wide (high)
622 + num_insns_constant_low (low) + 1);
623 }
624#endif
625
626 else
627 return 2;
628}
629
630int
631num_insns_constant (op, mode)
632 rtx op;
633 enum machine_mode mode;
634{
635 if (mode != SImode && mode != DImode)
636 abort ();
637
638 if (GET_CODE (op) == CONST_INT)
639 return num_insns_constant_wide (INTVAL (op));
640
641 else if (GET_CODE (op) == CONST_DOUBLE && TARGET_32BIT)
642 return (num_insns_constant_wide (CONST_DOUBLE_LOW (op))
643 + num_insns_constant_wide (CONST_DOUBLE_HIGH (op)));
644
645 else if (GET_CODE (op) == CONST_DOUBLE && TARGET_64BIT)
646 {
647 HOST_WIDE_INT low = CONST_DOUBLE_LOW (op);
648 HOST_WIDE_INT high = CONST_DOUBLE_HIGH (op);
649
650 if (high == 0 && (low & 0x80000000) == 0)
651 return num_insns_constant_wide (low);
652
653 else if (((high & 0xffffffff) == 0xffffffff)
654 && ((low & 0x80000000) != 0))
655 return num_insns_constant_wide (low);
656
657 else if (low == 0)
658 return num_insns_constant_wide (high) + 1;
659
660 else
661 return (num_insns_constant_wide (high)
662 + num_insns_constant_wide (low) + 1);
663 }
664
665 else
666 abort ();
667}
668
6f2f8311
RK		 669/* Return 1 if the operand is a CONST_DOUBLE and it can be put into a register
670 with one instruction per word. We only do this if we can safely read
671 CONST_DOUBLE_{LOW,HIGH}. */
9878760c
RK		 672
673int
674easy_fp_constant (op, mode)
675 register rtx op;
676 register enum machine_mode mode;
677{
9878760c
RK		 678 if (GET_CODE (op) != CONST_DOUBLE
679 || GET_MODE (op) != mode
4e74d8ec 680 || (GET_MODE_CLASS (mode) != MODE_FLOAT && mode != DImode))
9878760c
RK		 681 return 0;
682
b6c9286a 683 /* Consider all constants with -msoft-float to be easy */
4e74d8ec 684 if (TARGET_SOFT_FLOAT && mode != DImode)
b6c9286a
MM		 685 return 1;
686
042259f2
DE		 687 if (mode == DFmode)
688 {
689 long k[2];
690 REAL_VALUE_TYPE rv;
691
692 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
693 REAL_VALUE_TO_TARGET_DOUBLE (rv, k);
9878760c 694
4e74d8ec
MM		 695 return (num_insns_constant_wide ((HOST_WIDE_INT)k[0]) == 1
696 && num_insns_constant_wide ((HOST_WIDE_INT)k[1]) == 1);
042259f2 697 }
4e74d8ec
MM		 698
699 else if (mode == SFmode)
042259f2
DE		 700 {
701 long l;
702 REAL_VALUE_TYPE rv;
703
704 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
705 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
9878760c 706
4e74d8ec 707 return num_insns_constant_wide (l) == 1;
042259f2 708 }
4e74d8ec
MM		 709
710 else if (mode == DImode && TARGET_32BIT)
711 return num_insns_constant (op, DImode) == 2;
712
713 else
714 abort ();
9878760c 715}
8f75773e 716
b6c9286a
MM		 717/* Return 1 if the operand is in volatile memory. Note that during the
718 RTL generation phase, memory_operand does not return TRUE for
719 volatile memory references. So this function allows us to
720 recognize volatile references where its safe. */
721
722int
723volatile_mem_operand (op, mode)
724 register rtx op;
725 enum machine_mode mode;
726{
727 if (GET_CODE (op) != MEM)
728 return 0;
729
730 if (!MEM_VOLATILE_P (op))
731 return 0;
732
733 if (mode != GET_MODE (op))
734 return 0;
735
736 if (reload_completed)
737 return memory_operand (op, mode);
738
739 if (reload_in_progress)
740 return strict_memory_address_p (mode, XEXP (op, 0));
741
742 return memory_address_p (mode, XEXP (op, 0));
743}
744
5b5040b9 745/* Return 1 if the operand is an offsettable memory address. */
914c2e77
RK		 746
747int
5b5040b9 748offsettable_addr_operand (op, mode)
914c2e77
RK		 749 register rtx op;
750 enum machine_mode mode;
751{
8f75773e 752 return offsettable_address_p (reload_completed | reload_in_progress,
5b5040b9 753 mode, op);
914c2e77
RK		 754}
755
9878760c
RK		 756/* Return 1 if the operand is either a floating-point register, a pseudo
757 register, or memory. */
758
759int
760fp_reg_or_mem_operand (op, mode)
761 register rtx op;
762 enum machine_mode mode;
763{
764 return (memory_operand (op, mode)
b6c9286a 765 || volatile_mem_operand (op, mode)
9878760c
RK		 766 || (register_operand (op, mode)
767 && (GET_CODE (op) != REG
768 || REGNO (op) >= FIRST_PSEUDO_REGISTER
769 || FP_REGNO_P (REGNO (op)))));
770}
771
772/* Return 1 if the operand is either an easy FP constant (see above) or
773 memory. */
774
775int
776mem_or_easy_const_operand (op, mode)
777 register rtx op;
778 enum machine_mode mode;
779{
780 return memory_operand (op, mode) || easy_fp_constant (op, mode);
781}
782
783/* Return 1 if the operand is either a non-special register or an item
784 that can be used as the operand of an SI add insn. */
785
786int
787add_operand (op, mode)
788 register rtx op;
789 enum machine_mode mode;
790{
791 return (reg_or_short_operand (op, mode)
792 || (GET_CODE (op) == CONST_INT && (INTVAL (op) & 0xffff) == 0));
793}
794
dcfedcd0
RK		 795/* Return 1 if OP is a constant but not a valid add_operand. */
796
797int
798non_add_cint_operand (op, mode)
799 register rtx op;
800 enum machine_mode mode;
801{
802 return (GET_CODE (op) == CONST_INT
803 && (unsigned) (INTVAL (op) + 0x8000) >= 0x10000
804 && (INTVAL (op) & 0xffff) != 0);
805}
806
9878760c
RK		 807/* Return 1 if the operand is a non-special register or a constant that
808 can be used as the operand of an OR or XOR insn on the RS/6000. */
809
810int
811logical_operand (op, mode)
812 register rtx op;
813 enum machine_mode mode;
814{
cd2b37d9 815 return (gpc_reg_operand (op, mode)
9878760c
RK		 816 || (GET_CODE (op) == CONST_INT
817 && ((INTVAL (op) & 0xffff0000) == 0
818 || (INTVAL (op) & 0xffff) == 0)));
819}
820
dcfedcd0
RK		 821/* Return 1 if C is a constant that is not a logical operand (as
822 above). */
823
824int
825non_logical_cint_operand (op, mode)
826 register rtx op;
827 enum machine_mode mode;
828{
829 return (GET_CODE (op) == CONST_INT
830 && (INTVAL (op) & 0xffff0000) != 0
831 && (INTVAL (op) & 0xffff) != 0);
832}
833
9878760c
RK		 834/* Return 1 if C is a constant that can be encoded in a mask on the
835 RS/6000. It is if there are no more than two 1->0 or 0->1 transitions.
836 Reject all ones and all zeros, since these should have been optimized
837 away and confuse the making of MB and ME. */
838
839int
840mask_constant (c)
841 register int c;
842{
843 int i;
844 int last_bit_value;
845 int transitions = 0;
846
847 if (c == 0 || c == ~0)
848 return 0;
849
850 last_bit_value = c & 1;
851
852 for (i = 1; i < 32; i++)
853 if (((c >>= 1) & 1) != last_bit_value)
854 last_bit_value ^= 1, transitions++;
855
856 return transitions <= 2;
857}
858
859/* Return 1 if the operand is a constant that is a mask on the RS/6000. */
860
861int
862mask_operand (op, mode)
863 register rtx op;
864 enum machine_mode mode;
865{
866 return GET_CODE (op) == CONST_INT && mask_constant (INTVAL (op));
867}
868
869/* Return 1 if the operand is either a non-special register or a
870 constant that can be used as the operand of an RS/6000 logical AND insn. */
871
872int
873and_operand (op, mode)
874 register rtx op;
875 enum machine_mode mode;
876{
877 return (reg_or_short_operand (op, mode)
878 || logical_operand (op, mode)
879 || mask_operand (op, mode));
880}
881
dcfedcd0
RK		 882/* Return 1 if the operand is a constant but not a valid operand for an AND
883 insn. */
884
885int
886non_and_cint_operand (op, mode)
887 register rtx op;
888 enum machine_mode mode;
889{
890 return GET_CODE (op) == CONST_INT && ! and_operand (op, mode);
891}
892
9878760c
RK		 893/* Return 1 if the operand is a general register or memory operand. */
894
895int
896reg_or_mem_operand (op, mode)
897 register rtx op;
898 register enum machine_mode mode;
899{
b6c9286a
MM		 900 return (gpc_reg_operand (op, mode)
901 || memory_operand (op, mode)
902 || volatile_mem_operand (op, mode));
9878760c
RK		 903}
904
a7a813f7
RK		 905/* Return 1 if the operand is a general register or memory operand without
906 pre-inc or pre_dec which produces invalid form of PowerPC lwa
907 instruction. */
908
909int
910lwa_operand (op, mode)
911 register rtx op;
912 register enum machine_mode mode;
913{
914 rtx inner = op;
915
916 if (reload_completed && GET_CODE (inner) == SUBREG)
917 inner = SUBREG_REG (inner);
918
919 return gpc_reg_operand (inner, mode)
920 || (memory_operand (inner, mode)
921 && GET_CODE (XEXP (inner, 0)) != PRE_INC
922 && GET_CODE (XEXP (inner, 0)) != PRE_DEC);
923}
924
9878760c
RK		 925/* Return 1 if the operand, used inside a MEM, is a valid first argument
926 to CALL. This is a SYMBOL_REF or a pseudo-register, which will be
927 forced to lr. */
928
929int
930call_operand (op, mode)
931 register rtx op;
932 enum machine_mode mode;
933{
934 if (mode != VOIDmode && GET_MODE (op) != mode)
935 return 0;
936
937 return (GET_CODE (op) == SYMBOL_REF
938 || (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER));
939}
940
2af3d377
RK		 941
942/* Return 1 if the operand is a SYMBOL_REF for a function known to be in
943 this file. */
944
945int
946current_file_function_operand (op, mode)
947 register rtx op;
948 enum machine_mode mode;
949{
950 return (GET_CODE (op) == SYMBOL_REF
951 && (SYMBOL_REF_FLAG (op)
952 || op == XEXP (DECL_RTL (current_function_decl), 0)));
953}
954
955
9878760c
RK		 956/* Return 1 if this operand is a valid input for a move insn. */
957
958int
959input_operand (op, mode)
960 register rtx op;
961 enum machine_mode mode;
962{
eb4e8003 963 /* Memory is always valid. */
9878760c
RK		 964 if (memory_operand (op, mode))
965 return 1;
966
eb4e8003
RK		 967 /* For floating-point, easy constants are valid. */
968 if (GET_MODE_CLASS (mode) == MODE_FLOAT
969 && CONSTANT_P (op)
970 && easy_fp_constant (op, mode))
971 return 1;
972
4e74d8ec
MM		 973 /* Allow any integer constant. */
974 if (GET_MODE_CLASS (mode) == MODE_INT
975 && (GET_CODE (op) == CONST_INT || GET_CODE (op) == CONST_DOUBLE))
976 return 1;
977
eb4e8003
RK		 978 /* For floating-point or multi-word mode, the only remaining valid type
979 is a register. */
9878760c
RK		 980 if (GET_MODE_CLASS (mode) == MODE_FLOAT
981 || GET_MODE_SIZE (mode) > UNITS_PER_WORD)
eb4e8003 982 return register_operand (op, mode);
9878760c 983
88fe15a1
RK		 984 /* The only cases left are integral modes one word or smaller (we
985 do not get called for MODE_CC values). These can be in any
986 register. */
987 if (register_operand (op, mode))
a8b3aeda 988 return 1;
88fe15a1 989
84cf9dda 990 /* A SYMBOL_REF referring to the TOC is valid. */
7fec4abd 991 if (LEGITIMATE_CONSTANT_POOL_ADDRESS_P (op))
84cf9dda
RK		 992 return 1;
993
b6c9286a
MM		 994 /* Windows NT allows SYMBOL_REFs and LABEL_REFs against the TOC
995 directly in the instruction stream */
996 if (DEFAULT_ABI == ABI_NT
997 && (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF))
998 return 1;
999
88228c4b
MM		 1000 /* V.4 allows SYMBOL_REFs and CONSTs that are in the small data region
1001 to be valid. */
c81bebd7 1002 if ((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS)
88228c4b
MM		 1003 && (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST)
1004 && small_data_operand (op, Pmode))
1005 return 1;
1006
042259f2 1007 return 0;
9878760c 1008}
7509c759
MM		 1009
1010/* Return 1 for an operand in small memory on V.4/eabi */
1011
1012int
1013small_data_operand (op, mode)
1014 rtx op;
1015 enum machine_mode mode;
1016{
1017 rtx sym_ref, const_part;
1018
a54d04b7
MM		 1019#ifdef TARGET_SDATA
1020 if (!TARGET_SDATA)
1021 return 0;
1022#endif
1023
c81bebd7 1024 if (DEFAULT_ABI != ABI_V4 /* && DEFAULT_ABI != ABI_SOLARIS */)
7509c759
MM		 1025 return 0;
1026
88228c4b
MM		 1027 if (GET_CODE (op) == SYMBOL_REF)
1028 sym_ref = op;
1029
1030 else if (GET_CODE (op) != CONST
1031 || GET_CODE (XEXP (op, 0)) != PLUS
1032 || GET_CODE (XEXP (XEXP (op, 0), 0)) != SYMBOL_REF
1033 || GET_CODE (XEXP (XEXP (op, 0), 1)) != CONST_INT)
7509c759
MM		 1034 return 0;
1035
88228c4b
MM		 1036 else
1037 sym_ref = XEXP (XEXP (op, 0), 0);
1038
1039 if (*XSTR (sym_ref, 0) != '@')
7509c759
MM		 1040 return 0;
1041
1042 return 1;
1043}
1044
4697a36c
MM		 1045\f
1046/* Initialize a variable CUM of type CUMULATIVE_ARGS
1047 for a call to a function whose data type is FNTYPE.
1048 For a library call, FNTYPE is 0.
1049
1050 For incoming args we set the number of arguments in the prototype large
1051 so we never return an EXPR_LIST. */
1052
1053void
1054init_cumulative_args (cum, fntype, libname, incoming)
1055 CUMULATIVE_ARGS *cum;
1056 tree fntype;
1057 rtx libname;
1058 int incoming;
1059{
1060 static CUMULATIVE_ARGS zero_cumulative;
7509c759 1061 enum rs6000_abi abi = DEFAULT_ABI;
4697a36c
MM		 1062
1063 *cum = zero_cumulative;
1064 cum->words = 0;
1065 cum->fregno = FP_ARG_MIN_REG;
1066 cum->prototype = (fntype && TYPE_ARG_TYPES (fntype));
7509c759 1067 cum->call_cookie = CALL_NORMAL;
4697a36c
MM		 1068
1069 if (incoming)
1070 {
1071 cum->nargs_prototype = 1000; /* don't return an EXPR_LIST */
c81bebd7 1072 if (abi == ABI_V4 || abi == ABI_SOLARIS)
4697a36c 1073 cum->varargs_offset = RS6000_VARARGS_OFFSET;
4697a36c
MM		 1074 }
1075
1076 else if (cum->prototype)
1077 cum->nargs_prototype = (list_length (TYPE_ARG_TYPES (fntype)) - 1
1078 + (TYPE_MODE (TREE_TYPE (fntype)) == BLKmode
1079 || RETURN_IN_MEMORY (TREE_TYPE (fntype))));
1080
1081 else
1082 cum->nargs_prototype = 0;
1083
1084 cum->orig_nargs = cum->nargs_prototype;
7509c759
MM		 1085
1086 /* Check for DLL import functions */
1087 if (abi == ABI_NT
1088 && fntype
1089 && lookup_attribute ("dllimport", TYPE_ATTRIBUTES (fntype)))
1090 cum->call_cookie = CALL_NT_DLLIMPORT;
1091
6a4cee5f
MM		 1092 /* Also check for longcall's */
1093 else if (fntype && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype)))
1094 cum->call_cookie = CALL_LONG;
1095
4697a36c
MM		 1096 if (TARGET_DEBUG_ARG)
1097 {
1098 fprintf (stderr, "\ninit_cumulative_args:");
1099 if (fntype)
1100 {
1101 tree ret_type = TREE_TYPE (fntype);
1102 fprintf (stderr, " ret code = %s,",
1103 tree_code_name[ (int)TREE_CODE (ret_type) ]);
1104 }
1105
c81bebd7 1106 if ((abi == ABI_V4 || abi == ABI_SOLARIS) && incoming)
4697a36c 1107 fprintf (stderr, " varargs = %d, ", cum->varargs_offset);
7509c759 1108
6a4cee5f 1109 if (cum->call_cookie & CALL_NT_DLLIMPORT)
7509c759 1110 fprintf (stderr, " dllimport,");
4697a36c 1111
6a4cee5f
MM		 1112 if (cum->call_cookie & CALL_LONG)
1113 fprintf (stderr, " longcall,");
1114
4697a36c
MM		 1115 fprintf (stderr, " proto = %d, nargs = %d\n",
1116 cum->prototype, cum->nargs_prototype);
1117 }
1118}
1119\f
b6c9286a
MM		 1120/* If defined, a C expression that gives the alignment boundary, in bits,
1121 of an argument with the specified mode and type. If it is not defined,
1122 PARM_BOUNDARY is used for all arguments.
1123
e1f83b4d
MM		 1124 Windows NT wants anything >= 8 bytes to be double word aligned.
1125
1126 V.4 wants long longs to be double word aligned. */
b6c9286a
MM		 1127
1128int
1129function_arg_boundary (mode, type)
1130 enum machine_mode mode;
1131 tree type;
1132{
c81bebd7 1133 if ((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) && mode == DImode)
e1f83b4d
MM		 1134 return 64;
1135
b6c9286a
MM		 1136 if (DEFAULT_ABI != ABI_NT || TARGET_64BIT)
1137 return PARM_BOUNDARY;
1138
1139 if (mode != BLKmode)
1140 return (GET_MODE_SIZE (mode)) >= 8 ? 64 : 32;
1141
1142 return (int_size_in_bytes (type) >= 8) ? 64 : 32;
1143}
1144\f
4697a36c
MM		 1145/* Update the data in CUM to advance over an argument
1146 of mode MODE and data type TYPE.
1147 (TYPE is null for libcalls where that information may not be available.) */
1148
1149void
1150function_arg_advance (cum, mode, type, named)
1151 CUMULATIVE_ARGS *cum;
1152 enum machine_mode mode;
1153 tree type;
1154 int named;
1155{
b6c9286a
MM		 1156 int align = ((cum->words & 1) != 0 && function_arg_boundary (mode, type) == 64) ? 1 : 0;
1157 cum->words += align;
4697a36c
MM		 1158 cum->nargs_prototype--;
1159
c81bebd7 1160 if (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS)
4697a36c
MM		 1161 {
1162 /* Long longs must not be split between registers and stack */
1163 if ((GET_MODE_CLASS (mode) != MODE_FLOAT || TARGET_SOFT_FLOAT)
1164 && type && !AGGREGATE_TYPE_P (type)
1165 && cum->words < GP_ARG_NUM_REG
1166 && cum->words + RS6000_ARG_SIZE (mode, type, named) > GP_ARG_NUM_REG)
1167 {
1168 cum->words = GP_ARG_NUM_REG;
1169 }
1170
1171 /* Aggregates get passed as pointers */
1172 if (type && AGGREGATE_TYPE_P (type))
1173 cum->words++;
1174
1175 /* Floats go in registers, & don't occupy space in the GP registers
1176 like they do for AIX unless software floating point. */
1177 else if (GET_MODE_CLASS (mode) == MODE_FLOAT
1178 && TARGET_HARD_FLOAT
1179 && cum->fregno <= FP_ARG_V4_MAX_REG)
1180 cum->fregno++;
1181
1182 else
1183 cum->words += RS6000_ARG_SIZE (mode, type, 1);
1184 }
1185 else
4697a36c
MM		 1186 if (named)
1187 {
1188 cum->words += RS6000_ARG_SIZE (mode, type, named);
1189 if (GET_MODE_CLASS (mode) == MODE_FLOAT && TARGET_HARD_FLOAT)
1190 cum->fregno++;
1191 }
1192
1193 if (TARGET_DEBUG_ARG)
1194 fprintf (stderr,
b6c9286a
MM		 1195 "function_adv: words = %2d, fregno = %2d, nargs = %4d, proto = %d, mode = %4s, named = %d, align = %d\n",
1196 cum->words, cum->fregno, cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode), named, align);
4697a36c
MM		 1197}
1198\f
1199/* Determine where to put an argument to a function.
1200 Value is zero to push the argument on the stack,
1201 or a hard register in which to store the argument.
1202
1203 MODE is the argument's machine mode.
1204 TYPE is the data type of the argument (as a tree).
1205 This is null for libcalls where that information may
1206 not be available.
1207 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1208 the preceding args and about the function being called.
1209 NAMED is nonzero if this argument is a named parameter
1210 (otherwise it is an extra parameter matching an ellipsis).
1211
1212 On RS/6000 the first eight words of non-FP are normally in registers
1213 and the rest are pushed. Under AIX, the first 13 FP args are in registers.
1214 Under V.4, the first 8 FP args are in registers.
1215
1216 If this is floating-point and no prototype is specified, we use
1217 both an FP and integer register (or possibly FP reg and stack). Library
1218 functions (when TYPE is zero) always have the proper types for args,
1219 so we can pass the FP value just in one register. emit_library_function
1220 doesn't support EXPR_LIST anyway. */
1221
1222struct rtx_def *
1223function_arg (cum, mode, type, named)
1224 CUMULATIVE_ARGS *cum;
1225 enum machine_mode mode;
1226 tree type;
1227 int named;
1228{
b6c9286a
MM		 1229 int align = ((cum->words & 1) != 0 && function_arg_boundary (mode, type) == 64) ? 1 : 0;
1230 int align_words = cum->words + align;
1231
4697a36c
MM		 1232 if (TARGET_DEBUG_ARG)
1233 fprintf (stderr,
b6c9286a
MM		 1234 "function_arg: words = %2d, fregno = %2d, nargs = %4d, proto = %d, mode = %4s, named = %d, align = %d\n",
1235 cum->words, cum->fregno, cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode), named, align);
4697a36c
MM		 1236
1237 /* Return a marker to indicate whether CR1 needs to set or clear the bit that V.4
1238 uses to say fp args were passed in registers. Assume that we don't need the
1239 marker for software floating point, or compiler generated library calls. */
1240 if (mode == VOIDmode)
1241 {
7509c759
MM		 1242 enum rs6000_abi abi = DEFAULT_ABI;
1243
c81bebd7 1244 if ((abi == ABI_V4 || abi == ABI_SOLARIS)
7509c759
MM		 1245 && TARGET_HARD_FLOAT
1246 && cum->nargs_prototype < 0
4697a36c 1247 && type && (cum->prototype || TARGET_NO_PROTOTYPE))
7509c759 1248 {
6a4cee5f
MM		 1249 return GEN_INT (cum->call_cookie
1250 | ((cum->fregno == FP_ARG_MIN_REG)
1251 ? CALL_V4_SET_FP_ARGS
1252 : CALL_V4_CLEAR_FP_ARGS));
7509c759 1253 }
4697a36c 1254
7509c759 1255 return GEN_INT (cum->call_cookie);
4697a36c
MM		 1256 }
1257
1258 if (!named)
1259 {
c81bebd7 1260 if (DEFAULT_ABI != ABI_V4 && DEFAULT_ABI != ABI_SOLARIS)
4697a36c
MM		 1261 return NULL_RTX;
1262 }
1263
1264 if (type && TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST)
1265 return NULL_RTX;
1266
1267 if (USE_FP_FOR_ARG_P (*cum, mode, type))
1268 {
1269 if ((cum->nargs_prototype > 0)
c81bebd7
MM		 1270 || DEFAULT_ABI == ABI_V4 /* V.4 never passes FP values in GP registers */
1271 || DEFAULT_ABI == ABI_SOLARIS
4697a36c
MM		 1272 || !type)
1273 return gen_rtx (REG, mode, cum->fregno);
1274
1275 return gen_rtx (EXPR_LIST, VOIDmode,
b6c9286a
MM		 1276 ((align_words < GP_ARG_NUM_REG)
1277 ? gen_rtx (REG, mode, GP_ARG_MIN_REG + align_words)
4697a36c
MM		 1278 : NULL_RTX),
1279 gen_rtx (REG, mode, cum->fregno));
1280 }
1281
4697a36c 1282 /* Long longs won't be split between register and stack */
c81bebd7 1283 else if ((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) &&
b6c9286a 1284 align_words + RS6000_ARG_SIZE (mode, type, named) > GP_ARG_NUM_REG)
4697a36c
MM		 1285 {
1286 return NULL_RTX;
1287 }
4697a36c 1288
b6c9286a
MM		 1289 else if (align_words < GP_ARG_NUM_REG)
1290 return gen_rtx (REG, mode, GP_ARG_MIN_REG + align_words);
4697a36c
MM		 1291
1292 return NULL_RTX;
1293}
1294\f
1295/* For an arg passed partly in registers and partly in memory,
1296 this is the number of registers used.
1297 For args passed entirely in registers or entirely in memory, zero. */
1298
1299int
1300function_arg_partial_nregs (cum, mode, type, named)
1301 CUMULATIVE_ARGS *cum;
1302 enum machine_mode mode;
1303 tree type;
1304 int named;
1305{
1306 if (! named)
1307 return 0;
1308
c81bebd7 1309 if (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS)
4697a36c 1310 return 0;
4697a36c
MM		 1311
1312 if (USE_FP_FOR_ARG_P (*cum, mode, type))
1313 {
1314 if (cum->nargs_prototype >= 0)
1315 return 0;
1316 }
1317
1318 if (cum->words < GP_ARG_NUM_REG
1319 && GP_ARG_NUM_REG < (cum->words + RS6000_ARG_SIZE (mode, type, named)))
1320 {
1321 int ret = GP_ARG_NUM_REG - cum->words;
1322 if (ret && TARGET_DEBUG_ARG)
1323 fprintf (stderr, "function_arg_partial_nregs: %d\n", ret);
1324
1325 return ret;
1326 }
1327
1328 return 0;
1329}
1330\f
1331/* A C expression that indicates when an argument must be passed by
1332 reference. If nonzero for an argument, a copy of that argument is
1333 made in memory and a pointer to the argument is passed instead of
1334 the argument itself. The pointer is passed in whatever way is
1335 appropriate for passing a pointer to that type.
1336
1337 Under V.4, structures and unions are passed by reference. */
1338
1339int
1340function_arg_pass_by_reference (cum, mode, type, named)
1341 CUMULATIVE_ARGS *cum;
1342 enum machine_mode mode;
1343 tree type;
1344 int named;
1345{
c81bebd7
MM		 1346 if ((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS)
1347 && type && AGGREGATE_TYPE_P (type))
4697a36c
MM		 1348 {
1349 if (TARGET_DEBUG_ARG)
1350 fprintf (stderr, "function_arg_pass_by_reference: aggregate\n");
1351
1352 return 1;
1353 }
4697a36c
MM		 1354
1355 return 0;
1356}
1357
1358\f
1359/* Perform any needed actions needed for a function that is receiving a
1360 variable number of arguments.
1361
1362 CUM is as above.
1363
1364 MODE and TYPE are the mode and type of the current parameter.
1365
1366 PRETEND_SIZE is a variable that should be set to the amount of stack
1367 that must be pushed by the prolog to pretend that our caller pushed
1368 it.
1369
1370 Normally, this macro will push all remaining incoming registers on the
1371 stack and set PRETEND_SIZE to the length of the registers pushed. */
1372
1373void
1374setup_incoming_varargs (cum, mode, type, pretend_size, no_rtl)
1375 CUMULATIVE_ARGS *cum;
1376 enum machine_mode mode;
1377 tree type;
1378 int *pretend_size;
1379 int no_rtl;
1380
1381{
1382 rtx save_area = virtual_incoming_args_rtx;
1383 int reg_size = (TARGET_64BIT) ? 8 : 4;
1384
1385 if (TARGET_DEBUG_ARG)
1386 fprintf (stderr,
1387 "setup_vararg: words = %2d, fregno = %2d, nargs = %4d, proto = %d, mode = %4s, no_rtl= %d\n",
1388 cum->words, cum->fregno, cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode), no_rtl);
1389
c81bebd7 1390 if ((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) && !no_rtl)
4697a36c
MM		 1391 {
1392 rs6000_sysv_varargs_p = 1;
1393 save_area = plus_constant (frame_pointer_rtx, RS6000_VARARGS_OFFSET);
1394 }
4697a36c
MM		 1395
1396 if (cum->words < 8)
1397 {
1398 int first_reg_offset = cum->words;
1399
1400 if (MUST_PASS_IN_STACK (mode, type))
1401 first_reg_offset += RS6000_ARG_SIZE (TYPE_MODE (type), type, 1);
1402
1403 if (first_reg_offset > GP_ARG_NUM_REG)
1404 first_reg_offset = GP_ARG_NUM_REG;
1405
1406 if (!no_rtl && first_reg_offset != GP_ARG_NUM_REG)
1407 move_block_from_reg
1408 (GP_ARG_MIN_REG + first_reg_offset,
1409 gen_rtx (MEM, BLKmode,
1410 plus_constant (save_area, first_reg_offset * reg_size)),
1411 GP_ARG_NUM_REG - first_reg_offset,
1412 (GP_ARG_NUM_REG - first_reg_offset) * UNITS_PER_WORD);
1413
1414 *pretend_size = (GP_ARG_NUM_REG - first_reg_offset) * UNITS_PER_WORD;
1415 }
1416
4697a36c 1417 /* Save FP registers if needed. */
c81bebd7 1418 if ((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) && TARGET_HARD_FLOAT && !no_rtl)
4697a36c
MM		 1419 {
1420 int fregno = cum->fregno;
1421 int num_fp_reg = FP_ARG_V4_MAX_REG + 1 - fregno;
1422
1423 if (num_fp_reg >= 0)
1424 {
1425 rtx cr1 = gen_rtx (REG, CCmode, 69);
1426 rtx lab = gen_label_rtx ();
1427 int off = (GP_ARG_NUM_REG * reg_size) + ((fregno - FP_ARG_MIN_REG) * 8);
1428
1429 emit_jump_insn (gen_rtx (SET, VOIDmode,
1430 pc_rtx,
1431 gen_rtx (IF_THEN_ELSE, VOIDmode,
1432 gen_rtx (NE, VOIDmode, cr1, const0_rtx),
1433 gen_rtx (LABEL_REF, VOIDmode, lab),
1434 pc_rtx)));
1435
1436 while ( num_fp_reg-- >= 0)
1437 {
1438 emit_move_insn (gen_rtx (MEM, DFmode, plus_constant (save_area, off)),
1439 gen_rtx (REG, DFmode, fregno++));
1440 off += 8;
1441 }
1442
1443 emit_label (lab);
1444 }
1445 }
4697a36c
MM		 1446}
1447\f
1448/* If defined, is a C expression that produces the machine-specific
1449 code for a call to `__builtin_saveregs'. This code will be moved
1450 to the very beginning of the function, before any parameter access
1451 are made. The return value of this function should be an RTX that
1452 contains the value to use as the return of `__builtin_saveregs'.
1453
1454 The argument ARGS is a `tree_list' containing the arguments that
1455 were passed to `__builtin_saveregs'.
1456
1457 If this macro is not defined, the compiler will output an ordinary
1458 call to the library function `__builtin_saveregs'.
1459
1460 On the Power/PowerPC return the address of the area on the stack
1461 used to hold arguments. Under AIX, this includes the 8 word register
1462 save area. Under V.4 this does not. */
1463
1464struct rtx_def *
1465expand_builtin_saveregs (args)
1466 tree args;
1467{
1468 return virtual_incoming_args_rtx;
1469}
1470
7e69e155 1471\f
5b5040b9
RK		 1472/* Allocate a stack temp. Only allocate one stack temp per type for a
1473 function. */
1474
1475struct rtx_def *
1476rs6000_stack_temp (mode, size)
1477 enum machine_mode mode;
1478 int size;
1479{
1480 rtx temp = stack_temps[ (int)mode ];
1481 rtx addr;
1482
1483 if (temp == NULL_RTX)
1484 {
1485 temp = assign_stack_local (mode, size, 0);
1486 addr = XEXP (temp, 0);
1487
1488 if ((size > 4 && !offsettable_address_p (0, mode, addr))
1489 || (size <= 4 && !memory_address_p (mode, addr)))
1490 {
1491 XEXP (temp, 0) = copy_addr_to_reg (addr);
1492 }
1493
1494 stack_temps[ (int)mode ] = temp;
1495 }
1496
1497 return temp;
1498}
1499
1500\f
1501/* Generate a memory reference for expand_block_move, copying volatile,
1502 and other bits from an original memory reference. */
1503
1504static rtx
1505expand_block_move_mem (mode, addr, orig_mem)
1506 enum machine_mode mode;
1507 rtx addr;
1508 rtx orig_mem;
1509{
1510 rtx mem = gen_rtx (MEM, mode, addr);
b6c9286a
MM		 1511
1512 RTX_UNCHANGING_P (mem) = RTX_UNCHANGING_P (orig_mem);
5b5040b9
RK		 1513 MEM_VOLATILE_P (mem) = MEM_VOLATILE_P (orig_mem);
1514 MEM_IN_STRUCT_P (mem) = MEM_IN_STRUCT_P (orig_mem);
b6c9286a
MM		 1515#ifdef MEM_UNALIGNED_P
1516 MEM_UNALIGNED_P (mem) = MEM_UNALIGNED_P (orig_mem);
1517#endif
5b5040b9
RK		 1518 return mem;
1519}
1520
7e69e155
MM		 1521/* Expand a block move operation, and return 1 if successful. Return 0
1522 if we should let the compiler generate normal code.
1523
1524 operands[0] is the destination
1525 operands[1] is the source
1526 operands[2] is the length
1527 operands[3] is the alignment */
1528
3933e0e1
MM		 1529#define MAX_MOVE_REG 4
1530
7e69e155
MM		 1531int
1532expand_block_move (operands)
1533 rtx operands[];
1534{
b6c9286a
MM		 1535 rtx orig_dest = operands[0];
1536 rtx orig_src = operands[1];
7e69e155 1537 rtx bytes_rtx = operands[2];
7e69e155 1538 rtx align_rtx = operands[3];
3933e0e1 1539 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
7e69e155 1540 int align = XINT (align_rtx, 0);
3933e0e1
MM		 1541 int bytes;
1542 int offset;
1543 int num_reg;
1544 int i;
7e69e155
MM		 1545 rtx src_reg;
1546 rtx dest_reg;
3933e0e1
MM		 1547 rtx src_addr;
1548 rtx dest_addr;
7e69e155 1549 rtx tmp_reg;
3933e0e1 1550 rtx stores[MAX_MOVE_REG];
7e69e155
MM		 1551 int move_bytes;
1552
3933e0e1
MM		 1553 /* If this is not a fixed size move, just call memcpy */
1554 if (!constp)
1555 return 0;
1556
7e69e155 1557 /* Anything to move? */
3933e0e1
MM		 1558 bytes = INTVAL (bytes_rtx);
1559 if (bytes <= 0)
7e69e155
MM		 1560 return 1;
1561
3933e0e1
MM		 1562 /* Don't support real large moves. If string instructions are not used,
1563 then don't generate more than 8 loads. */
1564 if (TARGET_STRING)
1565 {
1cab3be1 1566 if (bytes > 4*8)
3933e0e1
MM		 1567 return 0;
1568 }
1569 else if (!STRICT_ALIGNMENT)
1570 {
1571 if (bytes > 4*8)
1572 return 0;
1573 }
1574 else if (bytes > 8*align)
7e69e155
MM		 1575 return 0;
1576
1577 /* Move the address into scratch registers. */
b6c9286a
MM		 1578 dest_reg = copy_addr_to_reg (XEXP (orig_dest, 0));
1579 src_reg = copy_addr_to_reg (XEXP (orig_src, 0));
7e69e155 1580
3933e0e1 1581 if (TARGET_STRING) /* string instructions are available */
7e69e155 1582 {
3933e0e1 1583 for ( ; bytes > 0; bytes -= move_bytes)
7e69e155 1584 {
3933e0e1
MM		 1585 if (bytes > 24 /* move up to 32 bytes at a time */
1586 && !fixed_regs[5]
1587 && !fixed_regs[6]
1588 && !fixed_regs[7]
1589 && !fixed_regs[8]
1590 && !fixed_regs[9]
1591 && !fixed_regs[10]
1592 && !fixed_regs[11]
1593 && !fixed_regs[12])
1594 {
1595 move_bytes = (bytes > 32) ? 32 : bytes;
b6c9286a
MM		 1596 emit_insn (gen_movstrsi_8reg (expand_block_move_mem (BLKmode, dest_reg, orig_dest),
1597 expand_block_move_mem (BLKmode, src_reg, orig_src),
3933e0e1 1598 GEN_INT ((move_bytes == 32) ? 0 : move_bytes),
4c64a852 1599 align_rtx));
3933e0e1
MM		 1600 }
1601 else if (bytes > 16 /* move up to 24 bytes at a time */
1602 && !fixed_regs[7]
1603 && !fixed_regs[8]
1604 && !fixed_regs[9]
1605 && !fixed_regs[10]
1606 && !fixed_regs[11]
1607 && !fixed_regs[12])
1608 {
1609 move_bytes = (bytes > 24) ? 24 : bytes;
b6c9286a
MM		 1610 emit_insn (gen_movstrsi_6reg (expand_block_move_mem (BLKmode, dest_reg, orig_dest),
1611 expand_block_move_mem (BLKmode, src_reg, orig_src),
3933e0e1 1612 GEN_INT (move_bytes),
4c64a852 1613 align_rtx));
3933e0e1
MM		 1614 }
1615 else if (bytes > 8 /* move up to 16 bytes at a time */
1616 && !fixed_regs[9]
1617 && !fixed_regs[10]
1618 && !fixed_regs[11]
1619 && !fixed_regs[12])
1620 {
1621 move_bytes = (bytes > 16) ? 16 : bytes;
b6c9286a
MM		 1622 emit_insn (gen_movstrsi_4reg (expand_block_move_mem (BLKmode, dest_reg, orig_dest),
1623 expand_block_move_mem (BLKmode, src_reg, orig_src),
3933e0e1 1624 GEN_INT (move_bytes),
4c64a852 1625 align_rtx));
3933e0e1 1626 }
d679bebf 1627 else if (bytes > 4 && !TARGET_64BIT)
3933e0e1
MM		 1628 { /* move up to 8 bytes at a time */
1629 move_bytes = (bytes > 8) ? 8 : bytes;
b6c9286a
MM		 1630 emit_insn (gen_movstrsi_2reg (expand_block_move_mem (BLKmode, dest_reg, orig_dest),
1631 expand_block_move_mem (BLKmode, src_reg, orig_src),
3933e0e1 1632 GEN_INT (move_bytes),
4c64a852 1633 align_rtx));
3933e0e1
MM		 1634 }
1635 else if (bytes >= 4 && (align >= 4 || !STRICT_ALIGNMENT))
1636 { /* move 4 bytes */
1637 move_bytes = 4;
1638 tmp_reg = gen_reg_rtx (SImode);
b6c9286a
MM		 1639 emit_move_insn (tmp_reg, expand_block_move_mem (SImode, src_reg, orig_src));
1640 emit_move_insn (expand_block_move_mem (SImode, dest_reg, orig_dest), tmp_reg);
3933e0e1
MM		 1641 }
1642 else if (bytes == 2 && (align >= 2 || !STRICT_ALIGNMENT))
1643 { /* move 2 bytes */
1644 move_bytes = 2;
1645 tmp_reg = gen_reg_rtx (HImode);
b6c9286a
MM		 1646 emit_move_insn (tmp_reg, expand_block_move_mem (HImode, src_reg, orig_src));
1647 emit_move_insn (expand_block_move_mem (HImode, dest_reg, orig_dest), tmp_reg);
3933e0e1
MM		 1648 }
1649 else if (bytes == 1) /* move 1 byte */
1650 {
1651 move_bytes = 1;
1652 tmp_reg = gen_reg_rtx (QImode);
b6c9286a
MM		 1653 emit_move_insn (tmp_reg, expand_block_move_mem (QImode, src_reg, orig_src));
1654 emit_move_insn (expand_block_move_mem (QImode, dest_reg, orig_dest), tmp_reg);
3933e0e1
MM		 1655 }
1656 else
1657 { /* move up to 4 bytes at a time */
1658 move_bytes = (bytes > 4) ? 4 : bytes;
b6c9286a
MM		 1659 emit_insn (gen_movstrsi_1reg (expand_block_move_mem (BLKmode, dest_reg, orig_dest),
1660 expand_block_move_mem (BLKmode, src_reg, orig_src),
3933e0e1 1661 GEN_INT (move_bytes),
4c64a852 1662 align_rtx));
3933e0e1 1663 }
4c64a852 1664
015892ee
RK		 1665 if (bytes > move_bytes)
1666 {
1667 emit_insn (gen_addsi3 (src_reg, src_reg, GEN_INT (move_bytes)));
1668 emit_insn (gen_addsi3 (dest_reg, dest_reg, GEN_INT (move_bytes)));
1669 }
4c64a852 1670 }
3933e0e1
MM		 1671 }
1672
1673 else /* string instructions not available */
1674 {
1675 num_reg = offset = 0;
1676 for ( ; bytes > 0; (bytes -= move_bytes), (offset += move_bytes))
7e69e155 1677 {
3933e0e1
MM		 1678 /* Calculate the correct offset for src/dest */
1679 if (offset == 0)
7e69e155 1680 {
3933e0e1
MM		 1681 src_addr = src_reg;
1682 dest_addr = dest_reg;
1683 }
1684 else
1685 {
1686 src_addr = gen_rtx (PLUS, Pmode, src_reg, GEN_INT (offset));
1687 dest_addr = gen_rtx (PLUS, Pmode, dest_reg, GEN_INT (offset));
1688 }
1689
1690 /* Generate the appropriate load and store, saving the stores for later */
b6c9286a
MM		 1691 if (bytes >= 8 && TARGET_64BIT && (align >= 8 || !STRICT_ALIGNMENT))
1692 {
1693 move_bytes = 8;
1694 tmp_reg = gen_reg_rtx (DImode);
1695 emit_insn (gen_movdi (tmp_reg, expand_block_move_mem (DImode, src_addr, orig_src)));
1696 stores[ num_reg++ ] = gen_movdi (expand_block_move_mem (DImode, dest_addr, orig_dest), tmp_reg);
1697 }
1698 else if (bytes >= 4 && (align >= 4 || !STRICT_ALIGNMENT))
3933e0e1
MM		 1699 {
1700 move_bytes = 4;
1701 tmp_reg = gen_reg_rtx (SImode);
b6c9286a
MM		 1702 emit_insn (gen_movsi (tmp_reg, expand_block_move_mem (SImode, src_addr, orig_src)));
1703 stores[ num_reg++ ] = gen_movsi (expand_block_move_mem (SImode, dest_addr, orig_dest), tmp_reg);
3933e0e1
MM		 1704 }
1705 else if (bytes >= 2 && (align >= 2 || !STRICT_ALIGNMENT))
1706 {
1707 move_bytes = 2;
1708 tmp_reg = gen_reg_rtx (HImode);
b6c9286a
MM		 1709 emit_insn (gen_movsi (tmp_reg, expand_block_move_mem (HImode, src_addr, orig_src)));
1710 stores[ num_reg++ ] = gen_movhi (expand_block_move_mem (HImode, dest_addr, orig_dest), tmp_reg);
3933e0e1
MM		 1711 }
1712 else
1713 {
1714 move_bytes = 1;
1715 tmp_reg = gen_reg_rtx (QImode);
b6c9286a
MM		 1716 emit_insn (gen_movsi (tmp_reg, expand_block_move_mem (QImode, src_addr, orig_src)));
1717 stores[ num_reg++ ] = gen_movqi (expand_block_move_mem (QImode, dest_addr, orig_dest), tmp_reg);
3933e0e1
MM		 1718 }
1719
1720 if (num_reg >= MAX_MOVE_REG)
1721 {
1722 for (i = 0; i < num_reg; i++)
1723 emit_insn (stores[i]);
1724 num_reg = 0;
7e69e155
MM		 1725 }
1726 }
3933e0e1 1727
b6c9286a
MM		 1728 for (i = 0; i < num_reg; i++)
1729 emit_insn (stores[i]);
7e69e155
MM		 1730 }
1731
1732 return 1;
1733}
1734
9878760c
RK		 1735\f
1736/* Return 1 if OP is a load multiple operation. It is known to be a
1737 PARALLEL and the first section will be tested. */
1738
1739int
1740load_multiple_operation (op, mode)
1741 rtx op;
1742 enum machine_mode mode;
1743{
1744 int count = XVECLEN (op, 0);
1745 int dest_regno;
1746 rtx src_addr;
1747 int i;
1748
1749 /* Perform a quick check so we don't blow up below. */
1750 if (count <= 1
1751 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1752 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
1753 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM)
1754 return 0;
1755
1756 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
1757 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0);
1758
1759 for (i = 1; i < count; i++)
1760 {
1761 rtx elt = XVECEXP (op, 0, i);
1762
1763 if (GET_CODE (elt) != SET
1764 || GET_CODE (SET_DEST (elt)) != REG
1765 || GET_MODE (SET_DEST (elt)) != SImode
1766 || REGNO (SET_DEST (elt)) != dest_regno + i
1767 || GET_CODE (SET_SRC (elt)) != MEM
1768 || GET_MODE (SET_SRC (elt)) != SImode
1769 || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
1770 || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
1771 || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT
1772 || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != i * 4)
1773 return 0;
1774 }
1775
1776 return 1;
1777}
1778
1779/* Similar, but tests for store multiple. Here, the second vector element
1780 is a CLOBBER. It will be tested later. */
1781
1782int
1783store_multiple_operation (op, mode)
1784 rtx op;
1785 enum machine_mode mode;
1786{
1787 int count = XVECLEN (op, 0) - 1;
1788 int src_regno;
1789 rtx dest_addr;
1790 int i;
1791
1792 /* Perform a quick check so we don't blow up below. */
1793 if (count <= 1
1794 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1795 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
1796 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG)
1797 return 0;
1798
1799 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
1800 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0);
1801
1802 for (i = 1; i < count; i++)
1803 {
1804 rtx elt = XVECEXP (op, 0, i + 1);
1805
1806 if (GET_CODE (elt) != SET
1807 || GET_CODE (SET_SRC (elt)) != REG
1808 || GET_MODE (SET_SRC (elt)) != SImode
1809 || REGNO (SET_SRC (elt)) != src_regno + i
1810 || GET_CODE (SET_DEST (elt)) != MEM
1811 || GET_MODE (SET_DEST (elt)) != SImode
1812 || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
1813 || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
1814 || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT
1815 || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != i * 4)
1816 return 0;
1817 }
1818
1819 return 1;
1820}
1821\f
1822/* Return 1 if OP is a comparison operation that is valid for a branch insn.
1823 We only check the opcode against the mode of the CC value here. */
1824
1825int
1826branch_comparison_operator (op, mode)
1827 register rtx op;
1828 enum machine_mode mode;
1829{
1830 enum rtx_code code = GET_CODE (op);
1831 enum machine_mode cc_mode;
1832
1833 if (GET_RTX_CLASS (code) != '<')
1834 return 0;
1835
1836 cc_mode = GET_MODE (XEXP (op, 0));
1837 if (GET_MODE_CLASS (cc_mode) != MODE_CC)
1838 return 0;
1839
1840 if ((code == GT || code == LT || code == GE || code == LE)
1841 && cc_mode == CCUNSmode)
1842 return 0;
1843
1844 if ((code == GTU || code == LTU || code == GEU || code == LEU)
1845 && (cc_mode != CCUNSmode))
1846 return 0;
1847
1848 return 1;
1849}
1850
1851/* Return 1 if OP is a comparison operation that is valid for an scc insn.
1852 We check the opcode against the mode of the CC value and disallow EQ or
1853 NE comparisons for integers. */
1854
1855int
1856scc_comparison_operator (op, mode)
1857 register rtx op;
1858 enum machine_mode mode;
1859{
1860 enum rtx_code code = GET_CODE (op);
1861 enum machine_mode cc_mode;
1862
1863 if (GET_MODE (op) != mode && mode != VOIDmode)
1864 return 0;
1865
1866 if (GET_RTX_CLASS (code) != '<')
1867 return 0;
1868
1869 cc_mode = GET_MODE (XEXP (op, 0));
1870 if (GET_MODE_CLASS (cc_mode) != MODE_CC)
1871 return 0;
1872
1873 if (code == NE && cc_mode != CCFPmode)
1874 return 0;
1875
1876 if ((code == GT || code == LT || code == GE || code == LE)
1877 && cc_mode == CCUNSmode)
1878 return 0;
1879
1880 if ((code == GTU || code == LTU || code == GEU || code == LEU)
1881 && (cc_mode != CCUNSmode))
1882 return 0;
1883
c5defebb
RK		 1884 if (cc_mode == CCEQmode && code != EQ && code != NE)
1885 return 0;
1886
9878760c
RK		 1887 return 1;
1888}
1889\f
1890/* Return 1 if ANDOP is a mask that has no bits on that are not in the
1891 mask required to convert the result of a rotate insn into a shift
1892 left insn of SHIFTOP bits. Both are known to be CONST_INT. */
1893
1894int
1895includes_lshift_p (shiftop, andop)
1896 register rtx shiftop;
1897 register rtx andop;
1898{
1899 int shift_mask = (~0 << INTVAL (shiftop));
1900
1901 return (INTVAL (andop) & ~shift_mask) == 0;
1902}
1903
1904/* Similar, but for right shift. */
1905
1906int
1907includes_rshift_p (shiftop, andop)
1908 register rtx shiftop;
1909 register rtx andop;
1910{
1911 unsigned shift_mask = ~0;
1912
1913 shift_mask >>= INTVAL (shiftop);
1914
1915 return (INTVAL (andop) & ~ shift_mask) == 0;
1916}
35068b43
RK		 1917
1918/* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates
1919 for lfq and stfq insns.
1920
1921 Note reg1 and reg2 *must* be hard registers. To be sure we will
1922 abort if we are passed pseudo registers. */
1923
1924int
1925registers_ok_for_quad_peep (reg1, reg2)
1926 rtx reg1, reg2;
1927{
1928 /* We might have been passed a SUBREG. */
1929 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
1930 return 0;
1931
1932 return (REGNO (reg1) == REGNO (reg2) - 1);
1933}
1934
1935/* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn. addr1 and
1936 addr2 must be in consecutive memory locations (addr2 == addr1 + 8). */
1937
1938int
1939addrs_ok_for_quad_peep (addr1, addr2)
1940 register rtx addr1;
1941 register rtx addr2;
1942{
1943 int reg1;
1944 int offset1;
1945
1946 /* Extract an offset (if used) from the first addr. */
1947 if (GET_CODE (addr1) == PLUS)
1948 {
1949 /* If not a REG, return zero. */
1950 if (GET_CODE (XEXP (addr1, 0)) != REG)
1951 return 0;
1952 else
1953 {
1954 reg1 = REGNO (XEXP (addr1, 0));
1955 /* The offset must be constant! */
1956 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
1957 return 0;
1958 offset1 = INTVAL (XEXP (addr1, 1));
1959 }
1960 }
1961 else if (GET_CODE (addr1) != REG)
1962 return 0;
1963 else
1964 {
1965 reg1 = REGNO (addr1);
1966 /* This was a simple (mem (reg)) expression. Offset is 0. */
1967 offset1 = 0;
1968 }
1969
1970 /* Make sure the second address is a (mem (plus (reg) (const_int). */
1971 if (GET_CODE (addr2) != PLUS)
1972 return 0;
1973
1974 if (GET_CODE (XEXP (addr2, 0)) != REG
1975 || GET_CODE (XEXP (addr2, 1)) != CONST_INT)
1976 return 0;
1977
1978 if (reg1 != REGNO (XEXP (addr2, 0)))
1979 return 0;
1980
1981 /* The offset for the second addr must be 8 more than the first addr. */
1982 if (INTVAL (XEXP (addr2, 1)) != offset1 + 8)
1983 return 0;
1984
1985 /* All the tests passed. addr1 and addr2 are valid for lfq or stfq
1986 instructions. */
1987 return 1;
1988}
9878760c
RK		 1989\f
1990/* Return the register class of a scratch register needed to copy IN into
1991 or out of a register in CLASS in MODE. If it can be done directly,
1992 NO_REGS is returned. */
1993
1994enum reg_class
1995secondary_reload_class (class, mode, in)
1996 enum reg_class class;
1997 enum machine_mode mode;
1998 rtx in;
1999{
2000 int regno = true_regnum (in);
2001
2002 if (regno >= FIRST_PSEUDO_REGISTER)
2003 regno = -1;
2004
2005 /* We can place anything into GENERAL_REGS and can put GENERAL_REGS
2006 into anything. */
2007 if (class == GENERAL_REGS || class == BASE_REGS
2008 || (regno >= 0 && INT_REGNO_P (regno)))
2009 return NO_REGS;
2010
2011 /* Constants, memory, and FP registers can go into FP registers. */
2012 if ((regno == -1 || FP_REGNO_P (regno))
2013 && (class == FLOAT_REGS || class == NON_SPECIAL_REGS))
2014 return NO_REGS;
2015
2016 /* We can copy among the CR registers. */
2017 if ((class == CR_REGS || class == CR0_REGS)
2018 && regno >= 0 && CR_REGNO_P (regno))
2019 return NO_REGS;
2020
2021 /* Otherwise, we need GENERAL_REGS. */
2022 return GENERAL_REGS;
2023}
2024\f
2025/* Given a comparison operation, return the bit number in CCR to test. We
2026 know this is a valid comparison.
2027
2028 SCC_P is 1 if this is for an scc. That means that %D will have been
2029 used instead of %C, so the bits will be in different places.
2030
b4ac57ab 2031 Return -1 if OP isn't a valid comparison for some reason. */
9878760c
RK		 2032
2033int
2034ccr_bit (op, scc_p)
2035 register rtx op;
2036 int scc_p;
2037{
2038 enum rtx_code code = GET_CODE (op);
2039 enum machine_mode cc_mode;
2040 int cc_regnum;
2041 int base_bit;
2042
2043 if (GET_RTX_CLASS (code) != '<')
2044 return -1;
2045
2046 cc_mode = GET_MODE (XEXP (op, 0));
2047 cc_regnum = REGNO (XEXP (op, 0));
2048 base_bit = 4 * (cc_regnum - 68);
2049
c5defebb
RK		 2050 /* In CCEQmode cases we have made sure that the result is always in the
2051 third bit of the CR field. */
2052
2053 if (cc_mode == CCEQmode)
2054 return base_bit + 3;
2055
9878760c
RK		 2056 switch (code)
2057 {
2058 case NE:
2059 return scc_p ? base_bit + 3 : base_bit + 2;
2060 case EQ:
2061 return base_bit + 2;
2062 case GT: case GTU:
2063 return base_bit + 1;
2064 case LT: case LTU:
2065 return base_bit;
2066
2067 case GE: case GEU:
2068 /* If floating-point, we will have done a cror to put the bit in the
2069 unordered position. So test that bit. For integer, this is ! LT
2070 unless this is an scc insn. */
2071 return cc_mode == CCFPmode || scc_p ? base_bit + 3 : base_bit;
2072
2073 case LE: case LEU:
2074 return cc_mode == CCFPmode || scc_p ? base_bit + 3 : base_bit + 1;
2075
2076 default:
2077 abort ();
2078 }
2079}
2080\f
2081/* Print an operand. Recognize special options, documented below. */
2082
2083void
2084print_operand (file, x, code)
2085 FILE *file;
2086 rtx x;
2087 char code;
2088{
2089 int i;
2090 int val;
2091
2092 /* These macros test for integers and extract the low-order bits. */
2093#define INT_P(X) \
2094((GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST_DOUBLE) \
2095 && GET_MODE (X) == VOIDmode)
2096
2097#define INT_LOWPART(X) \
2098 (GET_CODE (X) == CONST_INT ? INTVAL (X) : CONST_DOUBLE_LOW (X))
2099
2100 switch (code)
2101 {
a8b3aeda 2102 case '.':
a85d226b
RK		 2103 /* Write out an instruction after the call which may be replaced
2104 with glue code by the loader. This depends on the AIX version. */
2105 asm_fprintf (file, RS6000_CALL_GLUE);
a8b3aeda
RK		 2106 return;
2107
cfaaaf2e
RK		 2108 case '*':
2109 /* Write the register number of the TOC register. */
4697a36c 2110 fputs (TARGET_MINIMAL_TOC ? reg_names[30] : reg_names[2], file);
cfaaaf2e
RK		 2111 return;
2112
c81bebd7
MM		 2113 case '$':
2114 /* Write out either a '.' or '$' for the current location, depending
2115 on whether this is Solaris or not. */
2116 putc ((DEFAULT_ABI == ABI_SOLARIS) ? '.' : '$', file);
2117 return;
2118
9854d9ed
RK		 2119 case 'A':
2120 /* If X is a constant integer whose low-order 5 bits are zero,
2121 write 'l'. Otherwise, write 'r'. This is a kludge to fix a bug
76229ac8 2122 in the AIX assembler where "sri" with a zero shift count
9854d9ed
RK		 2123 write a trash instruction. */
2124 if (GET_CODE (x) == CONST_INT && (INTVAL (x) & 31) == 0)
76229ac8 2125 putc ('l', file);
9854d9ed 2126 else
76229ac8 2127 putc ('r', file);
9854d9ed
RK		 2128 return;
2129
2130 case 'b':
2131 /* Low-order 16 bits of constant, unsigned. */
cad12a8d 2132 if (! INT_P (x))
9854d9ed 2133 output_operand_lossage ("invalid %%b value");
cad12a8d 2134
9854d9ed 2135 fprintf (file, "%d", INT_LOWPART (x) & 0xffff);
cad12a8d
RK		 2136 return;
2137
9854d9ed
RK		 2138 case 'C':
2139 /* This is an optional cror needed for LE or GE floating-point
2140 comparisons. Otherwise write nothing. */
2141 if ((GET_CODE (x) == LE || GET_CODE (x) == GE)
2142 && GET_MODE (XEXP (x, 0)) == CCFPmode)
2143 {
2144 int base_bit = 4 * (REGNO (XEXP (x, 0)) - 68);
2145
2146 fprintf (file, "cror %d,%d,%d\n\t", base_bit + 3,
2147 base_bit + 2, base_bit + (GET_CODE (x) == GE));
2148 }
2149 return;
2150
2151 case 'D':
2152 /* Similar, except that this is for an scc, so we must be able to
2153 encode the test in a single bit that is one. We do the above
2154 for any LE, GE, GEU, or LEU and invert the bit for NE. */
2155 if (GET_CODE (x) == LE || GET_CODE (x) == GE
2156 || GET_CODE (x) == LEU || GET_CODE (x) == GEU)
2157 {
2158 int base_bit = 4 * (REGNO (XEXP (x, 0)) - 68);
2159
2160 fprintf (file, "cror %d,%d,%d\n\t", base_bit + 3,
2161 base_bit + 2,
2162 base_bit + (GET_CODE (x) == GE || GET_CODE (x) == GEU));
2163 }
2164
2165 else if (GET_CODE (x) == NE)
2166 {
2167 int base_bit = 4 * (REGNO (XEXP (x, 0)) - 68);
2168
2169 fprintf (file, "crnor %d,%d,%d\n\t", base_bit + 3,
2170 base_bit + 2, base_bit + 2);
2171 }
2172 return;
2173
2174 case 'E':
2175 /* X is a CR register. Print the number of the third bit of the CR */
2176 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
2177 output_operand_lossage ("invalid %%E value");
2178
2179 fprintf(file, "%d", 4 * (REGNO (x) - 68) + 3);
a85d226b 2180 return;
9854d9ed
RK		 2181
2182 case 'f':
2183 /* X is a CR register. Print the shift count needed to move it
2184 to the high-order four bits. */
2185 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
2186 output_operand_lossage ("invalid %%f value");
2187 else
2188 fprintf (file, "%d", 4 * (REGNO (x) - 68));
2189 return;
2190
2191 case 'F':
2192 /* Similar, but print the count for the rotate in the opposite
2193 direction. */
2194 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
2195 output_operand_lossage ("invalid %%F value");
2196 else
2197 fprintf (file, "%d", 32 - 4 * (REGNO (x) - 68));
2198 return;
2199
2200 case 'G':
2201 /* X is a constant integer. If it is negative, print "m",
2202 otherwise print "z". This is to make a aze or ame insn. */
2203 if (GET_CODE (x) != CONST_INT)
2204 output_operand_lossage ("invalid %%G value");
2205 else if (INTVAL (x) >= 0)
76229ac8 2206 putc ('z', file);
9854d9ed 2207 else
76229ac8 2208 putc ('m', file);
9854d9ed
RK		 2209 return;
2210
9878760c 2211 case 'h':
df3d94ed
RK		 2212 /* If constant, output low-order five bits. Otherwise,
2213 write normally. */
9878760c
RK		 2214 if (INT_P (x))
2215 fprintf (file, "%d", INT_LOWPART (x) & 31);
2216 else
2217 print_operand (file, x, 0);
2218 return;
2219
64305719
DE		 2220 case 'H':
2221 /* If constant, output low-order six bits. Otherwise,
2222 write normally. */
2223 if (INT_P (x))
2224 fprintf (file, "%d", INT_LOWPART (x) & 63);
2225 else
2226 print_operand (file, x, 0);
2227 return;
2228
9854d9ed
RK		 2229 case 'I':
2230 /* Print `i' if this is a constant, else nothing. */
9878760c 2231 if (INT_P (x))
76229ac8 2232 putc ('i', file);
9878760c
RK		 2233 return;
2234
9854d9ed
RK		 2235 case 'j':
2236 /* Write the bit number in CCR for jump. */
2237 i = ccr_bit (x, 0);
2238 if (i == -1)
2239 output_operand_lossage ("invalid %%j code");
9878760c 2240 else
9854d9ed 2241 fprintf (file, "%d", i);
9878760c
RK		 2242 return;
2243
9854d9ed
RK		 2244 case 'J':
2245 /* Similar, but add one for shift count in rlinm for scc and pass
2246 scc flag to `ccr_bit'. */
2247 i = ccr_bit (x, 1);
2248 if (i == -1)
2249 output_operand_lossage ("invalid %%J code");
2250 else
a0466a68
RK		 2251 /* If we want bit 31, write a shift count of zero, not 32. */
2252 fprintf (file, "%d", i == 31 ? 0 : i + 1);
9878760c
RK		 2253 return;
2254
9854d9ed
RK		 2255 case 'k':
2256 /* X must be a constant. Write the 1's complement of the
2257 constant. */
9878760c 2258 if (! INT_P (x))
9854d9ed 2259 output_operand_lossage ("invalid %%k value");
9878760c 2260
9854d9ed 2261 fprintf (file, "%d", ~ INT_LOWPART (x));
9878760c
RK		 2262 return;
2263
9854d9ed
RK		 2264 case 'L':
2265 /* Write second word of DImode or DFmode reference. Works on register
2266 or non-indexed memory only. */
2267 if (GET_CODE (x) == REG)
5ebfb2ba 2268 fprintf (file, "%s", reg_names[REGNO (x) + 1]);
9854d9ed
RK		 2269 else if (GET_CODE (x) == MEM)
2270 {
2271 /* Handle possible auto-increment. Since it is pre-increment and
2272 we have already done it, we can just use an offset of four. */
2273 if (GET_CODE (XEXP (x, 0)) == PRE_INC
2274 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
a54d04b7 2275 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 4));
9854d9ed 2276 else
a54d04b7
MM		 2277 output_address (plus_constant (XEXP (x, 0), 4));
2278 if (DEFAULT_ABI == ABI_V4 && small_data_operand (x, GET_MODE (x)))
c81bebd7 2279 fprintf (file, "@%s(%s)", (TARGET_EABI) ? "sda21" : "sdarel", reg_names[0]);
9854d9ed 2280 }
9878760c 2281 return;
9854d9ed 2282
9878760c
RK		 2283 case 'm':
2284 /* MB value for a mask operand. */
2285 if (! mask_operand (x, VOIDmode))
2286 output_operand_lossage ("invalid %%m value");
2287
2288 val = INT_LOWPART (x);
2289
2290 /* If the high bit is set and the low bit is not, the value is zero.
2291 If the high bit is zero, the value is the first 1 bit we find from
2292 the left. */
2293 if (val < 0 && (val & 1) == 0)
2294 {
19d2d16f 2295 putc ('0', file);
9878760c
RK		 2296 return;
2297 }
2298 else if (val >= 0)
2299 {
2300 for (i = 1; i < 32; i++)
2301 if ((val <<= 1) < 0)
2302 break;
2303 fprintf (file, "%d", i);
2304 return;
2305 }
2306
2307 /* Otherwise, look for the first 0 bit from the right. The result is its
2308 number plus 1. We know the low-order bit is one. */
2309 for (i = 0; i < 32; i++)
2310 if (((val >>= 1) & 1) == 0)
2311 break;
2312
2313 /* If we ended in ...01, I would be 0. The correct value is 31, so
2314 we want 31 - i. */
2315 fprintf (file, "%d", 31 - i);
2316 return;
2317
2318 case 'M':
2319 /* ME value for a mask operand. */
2320 if (! mask_operand (x, VOIDmode))
2321 output_operand_lossage ("invalid %%m value");
2322
2323 val = INT_LOWPART (x);
2324
2325 /* If the low bit is set and the high bit is not, the value is 31.
2326 If the low bit is zero, the value is the first 1 bit we find from
2327 the right. */
2328 if ((val & 1) && val >= 0)
2329 {
76229ac8 2330 fputs ("31", file);
9878760c
RK		 2331 return;
2332 }
2333 else if ((val & 1) == 0)
2334 {
2335 for (i = 0; i < 32; i++)
2336 if ((val >>= 1) & 1)
2337 break;
2338
2339 /* If we had ....10, I would be 0. The result should be
2340 30, so we need 30 - i. */
2341 fprintf (file, "%d", 30 - i);
2342 return;
2343 }
2344
2345 /* Otherwise, look for the first 0 bit from the left. The result is its
2346 number minus 1. We know the high-order bit is one. */
2347 for (i = 0; i < 32; i++)
2348 if ((val <<= 1) >= 0)
2349 break;
2350
2351 fprintf (file, "%d", i);
2352 return;
2353
9878760c
RK		 2354 case 'N':
2355 /* Write the number of elements in the vector times 4. */
2356 if (GET_CODE (x) != PARALLEL)
2357 output_operand_lossage ("invalid %%N value");
2358
2359 fprintf (file, "%d", XVECLEN (x, 0) * 4);
2360 return;
2361
2362 case 'O':
2363 /* Similar, but subtract 1 first. */
2364 if (GET_CODE (x) != PARALLEL)
2365 output_operand_lossage ("invalid %%N value");
2366
2367 fprintf (file, "%d", (XVECLEN (x, 0) - 1) * 4);
2368 return;
2369
9854d9ed
RK		 2370 case 'p':
2371 /* X is a CONST_INT that is a power of two. Output the logarithm. */
2372 if (! INT_P (x)
2373 || (i = exact_log2 (INT_LOWPART (x))) < 0)
2374 output_operand_lossage ("invalid %%p value");
2375
2376 fprintf (file, "%d", i);
2377 return;
2378
9878760c
RK		 2379 case 'P':
2380 /* The operand must be an indirect memory reference. The result
2381 is the register number. */
2382 if (GET_CODE (x) != MEM || GET_CODE (XEXP (x, 0)) != REG
2383 || REGNO (XEXP (x, 0)) >= 32)
2384 output_operand_lossage ("invalid %%P value");
2385
2386 fprintf (file, "%d", REGNO (XEXP (x, 0)));
2387 return;
2388
9854d9ed
RK		 2389 case 'R':
2390 /* X is a CR register. Print the mask for `mtcrf'. */
2391 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
2392 output_operand_lossage ("invalid %%R value");
2393 else
2394 fprintf (file, "%d", 128 >> (REGNO (x) - 68));
9878760c 2395 return;
9854d9ed
RK		 2396
2397 case 's':
2398 /* Low 5 bits of 32 - value */
2399 if (! INT_P (x))
2400 output_operand_lossage ("invalid %%s value");
2401
2402 fprintf (file, "%d", (32 - INT_LOWPART (x)) & 31);
9878760c 2403 return;
9854d9ed 2404
9878760c
RK		 2405 case 't':
2406 /* Write 12 if this jump operation will branch if true, 4 otherwise.
2407 All floating-point operations except NE branch true and integer
2408 EQ, LT, GT, LTU and GTU also branch true. */
2409 if (GET_RTX_CLASS (GET_CODE (x)) != '<')
2410 output_operand_lossage ("invalid %%t value");
2411
2412 else if ((GET_MODE (XEXP (x, 0)) == CCFPmode
2413 && GET_CODE (x) != NE)
2414 || GET_CODE (x) == EQ
2415 || GET_CODE (x) == LT || GET_CODE (x) == GT
2416 || GET_CODE (x) == LTU || GET_CODE (x) == GTU)
76229ac8 2417 fputs ("12", file);
9878760c 2418 else
76229ac8 2419 putc ('4', file);
9878760c
RK		 2420 return;
2421
2422 case 'T':
2423 /* Opposite of 't': write 4 if this jump operation will branch if true,
2424 12 otherwise. */
2425 if (GET_RTX_CLASS (GET_CODE (x)) != '<')
2426 output_operand_lossage ("invalid %%t value");
2427
2428 else if ((GET_MODE (XEXP (x, 0)) == CCFPmode
2429 && GET_CODE (x) != NE)
2430 || GET_CODE (x) == EQ
2431 || GET_CODE (x) == LT || GET_CODE (x) == GT
2432 || GET_CODE (x) == LTU || GET_CODE (x) == GTU)
76229ac8 2433 putc ('4', file);
9878760c 2434 else
76229ac8 2435 fputs ("12", file);
9878760c
RK		 2436 return;
2437
9854d9ed
RK		 2438 case 'u':
2439 /* High-order 16 bits of constant. */
2440 if (! INT_P (x))
2441 output_operand_lossage ("invalid %%u value");
9878760c 2442
76229ac8 2443 fprintf (file, "0x%x", (INT_LOWPART (x) >> 16) & 0xffff);
9878760c
RK		 2444 return;
2445
9854d9ed
RK		 2446 case 'U':
2447 /* Print `u' if this has an auto-increment or auto-decrement. */
2448 if (GET_CODE (x) == MEM
2449 && (GET_CODE (XEXP (x, 0)) == PRE_INC
2450 || GET_CODE (XEXP (x, 0)) == PRE_DEC))
76229ac8 2451 putc ('u', file);
9854d9ed 2452 return;
9878760c 2453
9854d9ed
RK		 2454 case 'w':
2455 /* If constant, low-order 16 bits of constant, signed. Otherwise, write
2456 normally. */
2457 if (INT_P (x))
2458 fprintf (file, "%d",
2459 (INT_LOWPART (x) & 0xffff) - 2 * (INT_LOWPART (x) & 0x8000));
2460 else
2461 print_operand (file, x, 0);
9878760c
RK		 2462 return;
2463
9854d9ed
RK		 2464 case 'W':
2465 /* If constant, low-order 16 bits of constant, unsigned.
2466 Otherwise, write normally. */
2467 if (INT_P (x))
2468 fprintf (file, "%d", INT_LOWPART (x) & 0xffff);
2469 else
2470 print_operand (file, x, 0);
2471 return;
9878760c 2472
9854d9ed
RK		 2473 case 'X':
2474 if (GET_CODE (x) == MEM
2475 && LEGITIMATE_INDEXED_ADDRESS_P (XEXP (x, 0)))
76229ac8 2476 putc ('x', file);
9854d9ed 2477 return;
9878760c 2478
9854d9ed
RK		 2479 case 'Y':
2480 /* Like 'L', for third word of TImode */
2481 if (GET_CODE (x) == REG)
5ebfb2ba 2482 fprintf (file, "%s", reg_names[REGNO (x) + 2]);
9854d9ed 2483 else if (GET_CODE (x) == MEM)
9878760c 2484 {
9854d9ed
RK		 2485 if (GET_CODE (XEXP (x, 0)) == PRE_INC
2486 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
a54d04b7 2487 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 8));
9854d9ed 2488 else
a54d04b7
MM		 2489 output_address (plus_constant (XEXP (x, 0), 8));
2490 if (DEFAULT_ABI == ABI_V4 && small_data_operand (x, GET_MODE (x)))
c81bebd7 2491 fprintf (file, "@%s(%s)", (TARGET_EABI) ? "sda21" : "sdarel", reg_names[0]);
9878760c
RK		 2492 }
2493 return;
9854d9ed 2494
9878760c 2495 case 'z':
b4ac57ab
RS		 2496 /* X is a SYMBOL_REF. Write out the name preceded by a
2497 period and without any trailing data in brackets. Used for function
4d30c363
MM		 2498 names. If we are configured for System V (or the embedded ABI) on
2499 the PowerPC, do not emit the period, since those systems do not use
2500 TOCs and the like. */
9878760c
RK		 2501 if (GET_CODE (x) != SYMBOL_REF)
2502 abort ();
2503
b6c9286a
MM		 2504 if (XSTR (x, 0)[0] != '.')
2505 {
2506 switch (DEFAULT_ABI)
2507 {
2508 default:
2509 abort ();
2510
2511 case ABI_AIX:
2512 putc ('.', file);
2513 break;
2514
2515 case ABI_V4:
2516 case ABI_AIX_NODESC:
c81bebd7 2517 case ABI_SOLARIS:
b6c9286a
MM		 2518 break;
2519
2520 case ABI_NT:
2521 fputs ("..", file);
2522 break;
2523 }
2524 }
9878760c
RK		 2525 RS6000_OUTPUT_BASENAME (file, XSTR (x, 0));
2526 return;
2527
9854d9ed
RK		 2528 case 'Z':
2529 /* Like 'L', for last word of TImode. */
2530 if (GET_CODE (x) == REG)
5ebfb2ba 2531 fprintf (file, "%s", reg_names[REGNO (x) + 3]);
9854d9ed
RK		 2532 else if (GET_CODE (x) == MEM)
2533 {
2534 if (GET_CODE (XEXP (x, 0)) == PRE_INC
2535 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
a54d04b7 2536 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 12));
9854d9ed 2537 else
a54d04b7
MM		 2538 output_address (plus_constant (XEXP (x, 0), 12));
2539 if (DEFAULT_ABI == ABI_V4 && small_data_operand (x, GET_MODE (x)))
c81bebd7 2540 fprintf (file, "@%s(%s)", (TARGET_EABI) ? "sda21" : "sdarel", reg_names[0]);
9854d9ed 2541 }
5c23c401 2542 return;
9854d9ed 2543
9878760c
RK		 2544 case 0:
2545 if (GET_CODE (x) == REG)
2546 fprintf (file, "%s", reg_names[REGNO (x)]);
2547 else if (GET_CODE (x) == MEM)
2548 {
2549 /* We need to handle PRE_INC and PRE_DEC here, since we need to
2550 know the width from the mode. */
2551 if (GET_CODE (XEXP (x, 0)) == PRE_INC)
2552 fprintf (file, "%d(%d)", GET_MODE_SIZE (GET_MODE (x)),
2553 REGNO (XEXP (XEXP (x, 0), 0)));
2554 else if (GET_CODE (XEXP (x, 0)) == PRE_DEC)
2555 fprintf (file, "%d(%d)", - GET_MODE_SIZE (GET_MODE (x)),
2556 REGNO (XEXP (XEXP (x, 0), 0)));
2557 else
a54d04b7 2558 output_address (XEXP (x, 0));
9878760c
RK		 2559 }
2560 else
a54d04b7 2561 output_addr_const (file, x);
a85d226b 2562 return;
9878760c
RK		 2563
2564 default:
2565 output_operand_lossage ("invalid %%xn code");
2566 }
2567}
2568\f
2569/* Print the address of an operand. */
2570
2571void
2572print_operand_address (file, x)
2573 FILE *file;
2574 register rtx x;
2575{
2576 if (GET_CODE (x) == REG)
4697a36c 2577 fprintf (file, "0(%s)", reg_names[ REGNO (x) ]);
9878760c
RK		 2578 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST)
2579 {
2580 output_addr_const (file, x);
7509c759 2581 if (DEFAULT_ABI == ABI_V4 && small_data_operand (x, GET_MODE (x)))
c81bebd7 2582 fprintf (file, "@%s(%s)", (TARGET_EABI) ? "sda21" : "sdarel", reg_names[0]);
7509c759 2583
4697a36c 2584#ifdef TARGET_NO_TOC
7509c759 2585 else if (TARGET_NO_TOC)
4697a36c 2586 ;
4697a36c 2587#endif
7509c759 2588 else
4697a36c 2589 fprintf (file, "(%s)", reg_names[ TARGET_MINIMAL_TOC ? 30 : 2 ]);
9878760c
RK		 2590 }
2591 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == REG)
2592 {
2593 if (REGNO (XEXP (x, 0)) == 0)
4697a36c
MM		 2594 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 1)) ],
2595 reg_names[ REGNO (XEXP (x, 0)) ]);
9878760c 2596 else
4697a36c
MM		 2597 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 0)) ],
2598 reg_names[ REGNO (XEXP (x, 1)) ]);
9878760c
RK		 2599 }
2600 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
4697a36c
MM		 2601 fprintf (file, "%d(%s)", INTVAL (XEXP (x, 1)), reg_names[ REGNO (XEXP (x, 0)) ]);
2602 else if (TARGET_ELF && !TARGET_64BIT && GET_CODE (x) == LO_SUM
2603 && GET_CODE (XEXP (x, 0)) == REG && CONSTANT_P (XEXP (x, 1)))
2604 {
2605 output_addr_const (file, XEXP (x, 1));
2606 fprintf (file, "@l(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
2607 }
9878760c
RK		 2608 else
2609 abort ();
2610}
2611\f
2612/* This page contains routines that are used to determine what the function
2613 prologue and epilogue code will do and write them out. */
2614
2615/* Return the first fixed-point register that is required to be saved. 32 if
2616 none. */
2617
2618int
2619first_reg_to_save ()
2620{
2621 int first_reg;
2622
2623 /* Find lowest numbered live register. */
2624 for (first_reg = 13; first_reg <= 31; first_reg++)
2625 if (regs_ever_live[first_reg])
2626 break;
2627
e165f3f0
RK		 2628 /* If profiling, then we must save/restore every register that contains
2629 a parameter before/after the .mcount call. Use registers from 30 down
2630 to 23 to do this. Don't use the frame pointer in reg 31.
2631
2632 For now, save enough room for all of the parameter registers. */
b6c9286a 2633 if (DEFAULT_ABI == ABI_AIX && profile_flag)
e165f3f0
RK		 2634 if (first_reg > 23)
2635 first_reg = 23;
2636
9878760c
RK		 2637 return first_reg;
2638}
2639
2640/* Similar, for FP regs. */
2641
2642int
2643first_fp_reg_to_save ()
2644{
2645 int first_reg;
2646
2647 /* Find lowest numbered live register. */
2648 for (first_reg = 14 + 32; first_reg <= 63; first_reg++)
2649 if (regs_ever_live[first_reg])
2650 break;
2651
2652 return first_reg;
2653}
2654
9878760c
RK		 2655/* Return non-zero if this function makes calls. */
2656
2657int
2658rs6000_makes_calls ()
2659{
2660 rtx insn;
2661
0c61c946
RK		 2662 /* If we are profiling, we will be making a call to mcount. */
2663 if (profile_flag)
2664 return 1;
2665
9878760c
RK		 2666 for (insn = get_insns (); insn; insn = next_insn (insn))
2667 if (GET_CODE (insn) == CALL_INSN)
2668 return 1;
2669
2670 return 0;
2671}
2672
4697a36c
MM		 2673\f
2674/* Calculate the stack information for the current function. This is
2675 complicated by having two separate calling sequences, the AIX calling
2676 sequence and the V.4 calling sequence.
2677
2678 AIX stack frames look like:
2679
2680 SP----> +---------------------------------------+
2681 | back chain to caller | 0
2682 +---------------------------------------+
2683 | saved CR | 4
2684 +---------------------------------------+
2685 | saved LR | 8
2686 +---------------------------------------+
2687 | reserved for compilers | 12
2688 +---------------------------------------+
2689 | reserved for binders | 16
2690 +---------------------------------------+
2691 | saved TOC pointer | 20
2692 +---------------------------------------+
2693 | Parameter save area (P) | 24
2694 +---------------------------------------+
2695 | Alloca space (A) | 24+P
2696 +---------------------------------------+
2697 | Local variable space (L) | 24+P+A
2698 +---------------------------------------+
2699 | Save area for GP registers (G) | 24+P+A+L
2700 +---------------------------------------+
2701 | Save area for FP registers (F) | 24+P+A+L+G
2702 +---------------------------------------+
2703 old SP->| back chain to caller's caller |
2704 +---------------------------------------+
2705
2706 V.4 stack frames look like:
2707
2708 SP----> +---------------------------------------+
2709 | back chain to caller | 0
2710 +---------------------------------------+
5eb387b8 2711 | caller's saved LR | 4
4697a36c
MM		 2712 +---------------------------------------+
2713 | Parameter save area (P) | 8
2714 +---------------------------------------+
2715 | Alloca space (A) | 8+P
2716 +---------------------------------------+
2717 | Varargs save area (V) | 8+P+A
2718 +---------------------------------------+
2719 | Local variable space (L) | 8+P+A+V
2720 +---------------------------------------+
2721 | saved CR (C) | 8+P+A+V+L
2722 +---------------------------------------+
2723 | Save area for GP registers (G) | 8+P+A+V+L+C
2724 +---------------------------------------+
2725 | Save area for FP registers (F) | 8+P+A+V+L+C+G
2726 +---------------------------------------+
2727 old SP->| back chain to caller's caller |
2728 +---------------------------------------+
b6c9286a
MM		 2729
2730
2731 A PowerPC Windows/NT frame looks like:
2732
2733 SP----> +---------------------------------------+
2734 | back chain to caller | 0
2735 +---------------------------------------+
2736 | reserved | 4
2737 +---------------------------------------+
2738 | reserved | 8
2739 +---------------------------------------+
2740 | reserved | 12
2741 +---------------------------------------+
2742 | reserved | 16
2743 +---------------------------------------+
2744 | reserved | 20
2745 +---------------------------------------+
2746 | Parameter save area (P) | 24
2747 +---------------------------------------+
2748 | Alloca space (A) | 24+P
2749 +---------------------------------------+
2750 | Local variable space (L) | 24+P+A
2751 +---------------------------------------+
2752 | Save area for FP registers (F) | 24+P+A+L
2753 +---------------------------------------+
2754 | Possible alignment area (X) | 24+P+A+L+F
2755 +---------------------------------------+
2756 | Save area for GP registers (G) | 24+P+A+L+F+X
2757 +---------------------------------------+
2758 | Save area for CR (C) | 24+P+A+L+F+X+G
2759 +---------------------------------------+
2760 | Save area for TOC (T) | 24+P+A+L+F+X+G+C
2761 +---------------------------------------+
2762 | Save area for LR (R) | 24+P+A+L+F+X+G+C+T
2763 +---------------------------------------+
2764 old SP->| back chain to caller's caller |
2765 +---------------------------------------+
2766
2767 For NT, there is no specific order to save the registers, but in
2768 order to support __builtin_return_address, the save area for the
2769 link register needs to be in a known place, so we use -4 off of the
2770 old SP. To support calls through pointers, we also allocate a
2771 fixed slot to store the TOC, -8 off the old SP. */
4697a36c
MM		 2772
2773rs6000_stack_t *
2774rs6000_stack_info ()
2775{
2776 static rs6000_stack_t info, zero_info;
2777 rs6000_stack_t *info_ptr = &info;
2778 int reg_size = TARGET_64BIT ? 8 : 4;
24d304eb 2779 enum rs6000_abi abi;
b6c9286a 2780 int total_raw_size;
4697a36c
MM		 2781
2782 /* Zero all fields portably */
2783 info = zero_info;
2784
2785 /* Select which calling sequence */
b6c9286a 2786 info_ptr->abi = abi = DEFAULT_ABI;
9878760c 2787
4697a36c
MM		 2788 /* Calculate which registers need to be saved & save area size */
2789 info_ptr->first_gp_reg_save = first_reg_to_save ();
2790 info_ptr->gp_size = reg_size * (32 - info_ptr->first_gp_reg_save);
2791
2792 info_ptr->first_fp_reg_save = first_fp_reg_to_save ();
2793 info_ptr->fp_size = 8 * (64 - info_ptr->first_fp_reg_save);
2794
2795 /* Does this function call anything? */
2796 info_ptr->calls_p = rs6000_makes_calls ();
2797
b6c9286a
MM		 2798 /* Do we need to allocate space to save the toc? */
2799 if (rs6000_save_toc_p)
2800 {
2801 info_ptr->toc_save_p = 1;
2802 info_ptr->toc_size = reg_size;
2803 }
2804
2805 /* If this is main and we need to call a function to set things up,
2806 save main's arguments around the call. */
c81bebd7
MM		 2807#ifdef TARGET_EABI
2808 if (TARGET_EABI)
2809#endif
b6c9286a 2810 {
c81bebd7 2811 if (strcmp (IDENTIFIER_POINTER (DECL_NAME (current_function_decl)), "main") == 0)
b6c9286a 2812 {
c81bebd7 2813 info_ptr->main_p = 1;
b6c9286a 2814
c81bebd7
MM		 2815#ifdef NAME__MAIN
2816 info_ptr->calls_p = 1;
b6c9286a 2817
c81bebd7 2818 if (DECL_ARGUMENTS (current_function_decl))
b6c9286a 2819 {
c81bebd7
MM		 2820 int i;
2821 tree arg;
2822
2823 info_ptr->main_save_p = 1;
2824 info_ptr->main_size = 0;
2825
2826 for ((i = 0), (arg = DECL_ARGUMENTS (current_function_decl));
2827 arg != NULL_TREE && i < 8;
2828 (arg = TREE_CHAIN (arg)), i++)
2829 {
2830 info_ptr->main_size += reg_size;
2831 }
b6c9286a 2832 }
b6c9286a 2833#endif
c81bebd7 2834 }
b6c9286a
MM		 2835 }
2836
c81bebd7 2837
4697a36c
MM		 2838 /* Determine if we need to save the link register */
2839 if (regs_ever_live[65] || profile_flag
2840#ifdef TARGET_RELOCATABLE
2841 || (TARGET_RELOCATABLE && (get_pool_size () != 0))
2842#endif
2843 || (info_ptr->first_fp_reg_save != 64
2844 && !FP_SAVE_INLINE (info_ptr->first_fp_reg_save))
24d304eb 2845 || (abi == ABI_V4 && current_function_calls_alloca)
c81bebd7 2846 || (abi == ABI_SOLARIS && current_function_calls_alloca)
4697a36c
MM		 2847 || info_ptr->calls_p)
2848 {
2849 info_ptr->lr_save_p = 1;
2850 regs_ever_live[65] = 1;
b6c9286a
MM		 2851 if (abi == ABI_NT)
2852 info_ptr->lr_size = reg_size;
4697a36c
MM		 2853 }
2854
2855 /* Determine if we need to save the condition code registers */
2856 if (regs_ever_live[70] || regs_ever_live[71] || regs_ever_live[72])
2857 {
2858 info_ptr->cr_save_p = 1;
c81bebd7 2859 if (abi == ABI_V4 || abi == ABI_NT || abi == ABI_SOLARIS)
4697a36c
MM		 2860 info_ptr->cr_size = reg_size;
2861 }
2862
2863 /* Determine various sizes */
2864 info_ptr->reg_size = reg_size;
2865 info_ptr->fixed_size = RS6000_SAVE_AREA;
2866 info_ptr->varargs_size = RS6000_VARARGS_AREA;
2867 info_ptr->vars_size = ALIGN (get_frame_size (), 8);
2868 info_ptr->parm_size = ALIGN (current_function_outgoing_args_size, 8);
b6c9286a
MM		 2869 info_ptr->save_size = ALIGN (info_ptr->fp_size
2870 + info_ptr->gp_size
2871 + info_ptr->cr_size
2872 + info_ptr->lr_size
2873 + info_ptr->toc_size
2874 + info_ptr->main_size, 8);
2875
2876 total_raw_size = (info_ptr->vars_size
2877 + info_ptr->parm_size
2878 + info_ptr->save_size
2879 + info_ptr->varargs_size
2880 + info_ptr->fixed_size);
2881
2882 info_ptr->total_size = ALIGN (total_raw_size, STACK_BOUNDARY / BITS_PER_UNIT);
4697a36c
MM		 2883
2884 /* Determine if we need to allocate any stack frame.
2885 For AIX We need to push the stack if a frame pointer is needed (because
2886 the stack might be dynamically adjusted), if we are debugging, if the
2887 total stack size is more than 220 bytes, or if we make calls.
2888
2889 For V.4 we don't have the stack cushion that AIX uses, but assume that
2890 the debugger can handle stackless frames. */
2891
2892 if (info_ptr->calls_p)
2893 info_ptr->push_p = 1;
2894
c81bebd7 2895 else if (abi == ABI_V4 || abi == ABI_NT || abi == ABI_SOLARIS)
b6c9286a 2896 info_ptr->push_p = (total_raw_size > info_ptr->fixed_size
4697a36c
MM		 2897 || info_ptr->lr_save_p);
2898
2899 else
2900 info_ptr->push_p = (frame_pointer_needed
2901 || write_symbols != NO_DEBUG
2902 || info_ptr->total_size > 220);
2903
2904 /* Calculate the offsets */
24d304eb 2905 switch (abi)
4697a36c 2906 {
b6c9286a 2907 case ABI_NONE:
24d304eb 2908 default:
b6c9286a
MM		 2909 abort ();
2910
2911 case ABI_AIX:
2912 case ABI_AIX_NODESC:
2913 info_ptr->fp_save_offset = - info_ptr->fp_size;
2914 info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size;
2915 info_ptr->main_save_offset = info_ptr->gp_save_offset - info_ptr->main_size;
2916 info_ptr->cr_save_offset = 4;
2917 info_ptr->lr_save_offset = 8;
24d304eb
RK		 2918 break;
2919
2920 case ABI_V4:
c81bebd7 2921 case ABI_SOLARIS:
b6c9286a
MM		 2922 info_ptr->fp_save_offset = - info_ptr->fp_size;
2923 info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size;
2924 info_ptr->cr_save_offset = info_ptr->gp_save_offset - reg_size;
2925 info_ptr->toc_save_offset = info_ptr->cr_save_offset - info_ptr->cr_size;
2926 info_ptr->main_save_offset = info_ptr->toc_save_offset - info_ptr->toc_size;
2927 info_ptr->lr_save_offset = reg_size;
2928 break;
2929
2930 case ABI_NT:
2931 info_ptr->lr_save_offset = -4;
2932 info_ptr->toc_save_offset = info_ptr->lr_save_offset - info_ptr->lr_size;
2933 info_ptr->cr_save_offset = info_ptr->toc_save_offset - info_ptr->toc_size;
2934 info_ptr->gp_save_offset = info_ptr->cr_save_offset - info_ptr->cr_size - info_ptr->gp_size + reg_size;
2935 info_ptr->fp_save_offset = info_ptr->gp_save_offset - info_ptr->fp_size;
2936 if (info_ptr->fp_size && ((- info_ptr->fp_save_offset) % 8) != 0)
2937 info_ptr->fp_save_offset -= 4;
2938
2939 info_ptr->main_save_offset = info_ptr->fp_save_offset - info_ptr->main_size;
24d304eb 2940 break;
4697a36c
MM		 2941 }
2942
2943 /* Zero offsets if we're not saving those registers */
2944 if (!info_ptr->fp_size)
2945 info_ptr->fp_save_offset = 0;
2946
2947 if (!info_ptr->gp_size)
2948 info_ptr->gp_save_offset = 0;
2949
2950 if (!info_ptr->lr_save_p)
2951 info_ptr->lr_save_offset = 0;
2952
2953 if (!info_ptr->cr_save_p)
2954 info_ptr->cr_save_offset = 0;
2955
b6c9286a
MM		 2956 if (!info_ptr->toc_save_p)
2957 info_ptr->toc_save_offset = 0;
2958
2959 if (!info_ptr->main_save_p)
2960 info_ptr->main_save_offset = 0;
2961
4697a36c
MM		 2962 return info_ptr;
2963}
2964
2965void
2966debug_stack_info (info)
2967 rs6000_stack_t *info;
9878760c 2968{
24d304eb
RK		 2969 char *abi_string;
2970
4697a36c
MM		 2971 if (!info)
2972 info = rs6000_stack_info ();
2973
2974 fprintf (stderr, "\nStack information for function %s:\n",
2975 ((current_function_decl && DECL_NAME (current_function_decl))
2976 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl))
2977 : "<unknown>"));
2978
24d304eb
RK		 2979 switch (info->abi)
2980 {
b6c9286a
MM		 2981 default: abi_string = "Unknown"; break;
2982 case ABI_NONE: abi_string = "NONE"; break;
2983 case ABI_AIX: abi_string = "AIX"; break;
2984 case ABI_AIX_NODESC: abi_string = "AIX"; break;
2985 case ABI_V4: abi_string = "V.4"; break;
c81bebd7 2986 case ABI_SOLARIS: abi_string = "Solaris"; break;
b6c9286a 2987 case ABI_NT: abi_string = "NT"; break;
24d304eb
RK		 2988 }
2989
2990 fprintf (stderr, "\tABI = %5s\n", abi_string);
2991
4697a36c
MM		 2992 if (info->first_gp_reg_save != 32)
2993 fprintf (stderr, "\tfirst_gp_reg_save = %5d\n", info->first_gp_reg_save);
2994
2995 if (info->first_fp_reg_save != 64)
2996 fprintf (stderr, "\tfirst_fp_reg_save = %5d\n", info->first_fp_reg_save);
9878760c 2997
4697a36c
MM		 2998 if (info->lr_save_p)
2999 fprintf (stderr, "\tlr_save_p = %5d\n", info->lr_save_p);
9878760c 3000
4697a36c
MM		 3001 if (info->cr_save_p)
3002 fprintf (stderr, "\tcr_save_p = %5d\n", info->cr_save_p);
3003
b6c9286a
MM		 3004 if (info->toc_save_p)
3005 fprintf (stderr, "\ttoc_save_p = %5d\n", info->toc_save_p);
3006
4697a36c
MM		 3007 if (info->push_p)
3008 fprintf (stderr, "\tpush_p = %5d\n", info->push_p);
3009
3010 if (info->calls_p)
3011 fprintf (stderr, "\tcalls_p = %5d\n", info->calls_p);
3012
b6c9286a
MM		 3013 if (info->main_p)
3014 fprintf (stderr, "\tmain_p = %5d\n", info->main_p);
3015
3016 if (info->main_save_p)
3017 fprintf (stderr, "\tmain_save_p = %5d\n", info->main_save_p);
3018
4697a36c
MM		 3019 if (info->gp_save_offset)
3020 fprintf (stderr, "\tgp_save_offset = %5d\n", info->gp_save_offset);
3021
3022 if (info->fp_save_offset)
3023 fprintf (stderr, "\tfp_save_offset = %5d\n", info->fp_save_offset);
3024
3025 if (info->lr_save_offset)
3026 fprintf (stderr, "\tlr_save_offset = %5d\n", info->lr_save_offset);
3027
3028 if (info->cr_save_offset)
3029 fprintf (stderr, "\tcr_save_offset = %5d\n", info->cr_save_offset);
3030
b6c9286a
MM		 3031 if (info->toc_save_offset)
3032 fprintf (stderr, "\ttoc_save_offset = %5d\n", info->toc_save_offset);
3033
4697a36c
MM		 3034 if (info->varargs_save_offset)
3035 fprintf (stderr, "\tvarargs_save_offset = %5d\n", info->varargs_save_offset);
3036
b6c9286a
MM		 3037 if (info->main_save_offset)
3038 fprintf (stderr, "\tmain_save_offset = %5d\n", info->main_save_offset);
3039
4697a36c
MM		 3040 if (info->total_size)
3041 fprintf (stderr, "\ttotal_size = %5d\n", info->total_size);
3042
3043 if (info->varargs_size)
3044 fprintf (stderr, "\tvarargs_size = %5d\n", info->varargs_size);
3045
3046 if (info->vars_size)
3047 fprintf (stderr, "\tvars_size = %5d\n", info->vars_size);
3048
3049 if (info->parm_size)
3050 fprintf (stderr, "\tparm_size = %5d\n", info->parm_size);
3051
3052 if (info->fixed_size)
3053 fprintf (stderr, "\tfixed_size = %5d\n", info->fixed_size);
3054
3055 if (info->gp_size)
3056 fprintf (stderr, "\tgp_size = %5d\n", info->gp_size);
3057
3058 if (info->fp_size)
3059 fprintf (stderr, "\tfp_size = %5d\n", info->fp_size);
3060
b6c9286a
MM		 3061 if (info->lr_size)
3062 fprintf (stderr, "\tlr_size = %5d\n", info->cr_size);
3063
4697a36c
MM		 3064 if (info->cr_size)
3065 fprintf (stderr, "\tcr_size = %5d\n", info->cr_size);
3066
b6c9286a
MM		 3067 if (info->toc_size)
3068 fprintf (stderr, "\ttoc_size = %5d\n", info->toc_size);
3069
3070 if (info->main_size)
3071 fprintf (stderr, "\tmain_size = %5d\n", info->main_size);
3072
4697a36c
MM		 3073 if (info->save_size)
3074 fprintf (stderr, "\tsave_size = %5d\n", info->save_size);
3075
3076 if (info->reg_size != 4)
3077 fprintf (stderr, "\treg_size = %5d\n", info->reg_size);
3078
3079 fprintf (stderr, "\n");
9878760c
RK		 3080}
3081
4697a36c 3082\f
9878760c 3083/* Write function prologue. */
9878760c
RK		 3084void
3085output_prolog (file, size)
3086 FILE *file;
3087 int size;
3088{
4697a36c 3089 rs6000_stack_t *info = rs6000_stack_info ();
b6c9286a
MM		 3090 int reg_size = info->reg_size;
3091 char *store_reg;
3092 char *load_reg;
979721f8
MM		 3093 int sp_reg = 1;
3094 int sp_offset = 0;
b6c9286a 3095
8f802bfb 3096 if (TARGET_32BIT)
b6c9286a 3097 {
8f802bfb
DE		 3098 store_reg = "\t{st|stw} %s,%d(%s)\n";
3099 load_reg = "\t{l|lwz} %s,%d(%s)\n";
b6c9286a
MM		 3100 }
3101 else
3102 {
8f802bfb
DE		 3103 store_reg = "\tstd %s,%d(%s)\n";
3104 load_reg = "\tlld %s,%d(%s)\n";
b6c9286a 3105 }
9878760c 3106
4697a36c
MM		 3107 if (TARGET_DEBUG_STACK)
3108 debug_stack_info (info);
9878760c
RK		 3109
3110 /* Write .extern for any function we will call to save and restore fp
3111 values. */
b6c9286a 3112 if (info->first_fp_reg_save < 64 && !FP_SAVE_INLINE (info->first_fp_reg_save))
4d30c363 3113 fprintf (file, "\t.extern %s%d%s\n\t.extern %s%d%s\n",
4697a36c
MM		 3114 SAVE_FP_PREFIX, info->first_fp_reg_save - 32, SAVE_FP_SUFFIX,
3115 RESTORE_FP_PREFIX, info->first_fp_reg_save - 32, RESTORE_FP_SUFFIX);
9878760c
RK		 3116
3117 /* Write .extern for truncation routines, if needed. */
3118 if (rs6000_trunc_used && ! trunc_defined)
3119 {
e138174b
ILT		 3120 fprintf (file, "\t.extern .%s\n\t.extern .%s\n",
3121 RS6000_ITRUNC, RS6000_UITRUNC);
9878760c
RK		 3122 trunc_defined = 1;
3123 }
4697a36c 3124
c764f757
RK		 3125 /* Write .extern for AIX common mode routines, if needed. */
3126 if (! TARGET_POWER && ! TARGET_POWERPC && ! common_mode_defined)
3127 {
f6709c70
JW		 3128 fputs ("\t.extern __mulh\n", file);
3129 fputs ("\t.extern __mull\n", file);
3130 fputs ("\t.extern __divss\n", file);
3131 fputs ("\t.extern __divus\n", file);
3132 fputs ("\t.extern __quoss\n", file);
3133 fputs ("\t.extern __quous\n", file);
c764f757
RK		 3134 common_mode_defined = 1;
3135 }
9878760c 3136
979721f8 3137 /* For V.4, update stack before we do any saving and set back pointer. */
c81bebd7 3138 if (info->push_p && (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS))
979721f8
MM		 3139 {
3140 if (info->total_size < 32767)
3141 {
3142 asm_fprintf (file,
3143 (TARGET_32BIT) ? "\t{stu|stwu} %s,%d(%s)\n" : "\tstdu %s,%d(%s)\n",
3144 reg_names[1], - info->total_size, reg_names[1]);
3145 sp_offset = info->total_size;
3146 }
3147 else
3148 {
3149 int neg_size = - info->total_size;
3150 sp_reg = 12;
3151 asm_fprintf (file, "\tmr %s,%s\n", reg_names[12], reg_names[1]);
3152 asm_fprintf (file, "\t{liu|lis} %s,%d\n\t{oril|ori} %s,%s,%d\n",
3153 reg_names[0], (neg_size >> 16) & 0xffff,
3154 reg_names[0], reg_names[0], neg_size & 0xffff);
3155 asm_fprintf (file,
3156 (TARGET_32BIT) ? "\t{stux|stwux} %s,%s,%s\n" : "\tstdux %s,%s,%s\n",
3157 reg_names[1], reg_names[1], reg_names[0]);
3158 }
3159 }
3160
9878760c 3161 /* If we use the link register, get it into r0. */
4697a36c
MM		 3162 if (info->lr_save_p)
3163 asm_fprintf (file, "\tmflr %s\n", reg_names[0]);
9878760c
RK		 3164
3165 /* If we need to save CR, put it into r12. */
979721f8 3166 if (info->cr_save_p && sp_reg != 12)
4697a36c 3167 asm_fprintf (file, "\tmfcr %s\n", reg_names[12]);
9878760c
RK		 3168
3169 /* Do any required saving of fpr's. If only one or two to save, do it
53322b0c
RK		 3170 ourself. Otherwise, call function. Note that since they are statically
3171 linked, we do not need a nop following them. */
4697a36c 3172 if (FP_SAVE_INLINE (info->first_fp_reg_save))
bacbde18 3173 {
4697a36c 3174 int regno = info->first_fp_reg_save;
979721f8 3175 int loc = info->fp_save_offset + sp_offset;
4697a36c
MM		 3176
3177 for ( ; regno < 64; regno++, loc += 8)
979721f8 3178 asm_fprintf (file, "\tstfd %s,%d(%s)\n", reg_names[regno], loc, reg_names[sp_reg]);
bacbde18 3179 }
4697a36c
MM		 3180 else if (info->first_fp_reg_save != 64)
3181 asm_fprintf (file, "\tbl %s%d%s\n", SAVE_FP_PREFIX,
3182 info->first_fp_reg_save - 32, SAVE_FP_SUFFIX);
9878760c
RK		 3183
3184 /* Now save gpr's. */
4697a36c 3185 if (! TARGET_MULTIPLE || info->first_gp_reg_save == 31 || TARGET_64BIT)
85638c0d 3186 {
4697a36c 3187 int regno = info->first_gp_reg_save;
979721f8 3188 int loc = info->gp_save_offset + sp_offset;
85638c0d 3189
4697a36c 3190 for ( ; regno < 32; regno++, loc += reg_size)
979721f8 3191 asm_fprintf (file, store_reg, reg_names[regno], loc, reg_names[sp_reg]);
85638c0d
RK		 3192 }
3193
4697a36c
MM		 3194 else if (info->first_gp_reg_save != 32)
3195 asm_fprintf (file, "\t{stm|stmw} %s,%d(%s)\n",
3196 reg_names[info->first_gp_reg_save],
979721f8
MM		 3197 info->gp_save_offset + sp_offset,
3198 reg_names[sp_reg]);
9878760c 3199
b6c9286a
MM		 3200 /* Save main's arguments if we need to call a function */
3201#ifdef NAME__MAIN
3202 if (info->main_save_p)
3203 {
3204 int regno;
5ebfb2ba 3205 int loc = info->main_save_offset + sp_offset;
b6c9286a
MM		 3206 int size = info->main_size;
3207
3208 for (regno = 3; size > 0; regno++, loc -= reg_size, size -= reg_size)
979721f8 3209 asm_fprintf (file, store_reg, reg_names[regno], loc, reg_names[sp_reg]);
b6c9286a
MM		 3210 }
3211#endif
3212
9878760c 3213 /* Save lr if we used it. */
4697a36c 3214 if (info->lr_save_p)
979721f8
MM		 3215 asm_fprintf (file, store_reg, reg_names[0], info->lr_save_offset + sp_offset,
3216 reg_names[sp_reg]);
9878760c
RK		 3217
3218 /* Save CR if we use any that must be preserved. */
4697a36c 3219 if (info->cr_save_p)
979721f8
MM		 3220 {
3221 if (sp_reg == 12) /* If r12 is used to hold the original sp, copy cr now */
3222 {
3223 asm_fprintf (file, "\tmfcr %s\n", reg_names[0]);
3224 asm_fprintf (file, store_reg, reg_names[0],
3225 info->cr_save_offset + sp_offset,
3226 reg_names[sp_reg]);
3227 }
3228 else
3229 asm_fprintf (file, store_reg, reg_names[12], info->cr_save_offset + sp_offset,
3230 reg_names[sp_reg]);
3231 }
9878760c 3232
b6c9286a 3233 if (info->toc_save_p)
979721f8
MM		 3234 asm_fprintf (file, store_reg, reg_names[2], info->toc_save_offset + sp_offset,
3235 reg_names[sp_reg]);
b6c9286a 3236
979721f8
MM		 3237 /* NT needs us to probe the stack frame every 4k pages for large frames, so
3238 do it here. */
3239 if (DEFAULT_ABI == ABI_NT && info->total_size > 4096)
3240 {
3241 if (info->total_size < 32768)
3242 {
3243 int probe_offset = 4096;
3244 while (probe_offset < info->total_size)
3245 {
3246 asm_fprintf (file, "\t{l|lwz} %s,%d(%s)\n", reg_names[0], -probe_offset, reg_names[1]);
3247 probe_offset += 4096;
3248 }
3249 }
3250 else
3251 {
3252 int probe_iterations = info->total_size / 4096;
3253 static int probe_labelno = 0;
3254 char buf[256];
3255
3256 if (probe_iterations < 32768)
3257 asm_fprintf (file, "\tli %s,%d\n", reg_names[12], probe_iterations);
3258 else
3259 {
3260 asm_fprintf (file, "\tlis %s,%d\n", reg_names[12], probe_iterations >> 16);
3261 if (probe_iterations & 0xffff)
3262 asm_fprintf (file, "\tori %s,%s,%d\n", reg_names[12], reg_names[12],
3263 probe_iterations & 0xffff);
3264 }
3265 asm_fprintf (file, "\tmtctr %s\n", reg_names[12]);
3266 asm_fprintf (file, "\tmr %s,%s\n", reg_names[12], reg_names[1]);
3267 ASM_OUTPUT_INTERNAL_LABEL (file, "LCprobe", probe_labelno);
3268 asm_fprintf (file, "\t{lu|lwzu} %s,-4096(%s)\n", reg_names[0], reg_names[12]);
3269 ASM_GENERATE_INTERNAL_LABEL (buf, "LCprobe", probe_labelno);
3270 fputs ("\tbdnz ", file);
3271 assemble_name (file, buf);
3272 fputs ("\n", file);
3273 }
3274 }
3275
3276 /* Update stack and set back pointer and we have already done so for V.4. */
c81bebd7 3277 if (info->push_p && DEFAULT_ABI != ABI_V4 && DEFAULT_ABI != ABI_SOLARIS)
9878760c 3278 {
4697a36c
MM		 3279 if (info->total_size < 32767)
3280 asm_fprintf (file,
8f802bfb 3281 (TARGET_32BIT) ? "\t{stu|stwu} %s,%d(%s)\n" : "\tstdu %s,%d(%s)\n",
4697a36c 3282 reg_names[1], - info->total_size, reg_names[1]);
9878760c
RK		 3283 else
3284 {
ef7a1424 3285 int neg_size = - info->total_size;
4697a36c 3286 asm_fprintf (file, "\t{liu|lis} %s,%d\n\t{oril|ori} %s,%s,%d\n",
ef7a1424
RK		 3287 reg_names[0], (neg_size >> 16) & 0xffff,
3288 reg_names[0], reg_names[0], neg_size & 0xffff);
4697a36c 3289 asm_fprintf (file,
8f802bfb 3290 (TARGET_32BIT) ? "\t{stux|stwux} %s,%s,%s\n" : "\tstdux %s,%s,%s\n",
4697a36c 3291 reg_names[1], reg_names[1], reg_names[0]);
9878760c
RK		 3292 }
3293 }
3294
3295 /* Set frame pointer, if needed. */
3296 if (frame_pointer_needed)
4697a36c 3297 asm_fprintf (file, "\tmr %s,%s\n", reg_names[31], reg_names[1]);
1875cc88 3298
b6c9286a
MM		 3299#ifdef NAME__MAIN
3300 /* If we need to call a function to set things up for main, do so now
3301 before dealing with the TOC. */
3302 if (info->main_p)
3303 {
3304 char *prefix = "";
3305
3306 switch (DEFAULT_ABI)
3307 {
3308 case ABI_AIX: prefix = "."; break;
3309 case ABI_NT: prefix = ".."; break;
3310 }
3311
3312 fprintf (file, "\tbl %s%s\n", prefix, NAME__MAIN);
3313#ifdef RS6000_CALL_GLUE2
3314 fprintf (file, "\t%s%s%s\n", RS6000_CALL_GLUE2, prefix, NAME_MAIN);
3315#else
3316#ifdef RS6000_CALL_GLUE
3317 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_NT)
3318 fprintf (file, "\t%s\n", RS6000_CALL_GLUE);
3319#endif
3320#endif
3321
3322 if (info->main_save_p)
3323 {
3324 int regno;
3325 int loc;
3326 int size = info->main_size;
3327
3328 if (info->total_size < 32767)
3329 {
3330 loc = info->total_size + info->main_save_offset;
3331 for (regno = 3; size > 0; regno++, size -= reg_size, loc -= reg_size)
3332 asm_fprintf (file, load_reg, reg_names[regno], loc, reg_names[1]);
3333 }
3334 else
5ebfb2ba
MM		 3335 {
3336 int neg_size = info->main_save_offset - info->total_size;
3337 loc = 0;
3338 asm_fprintf (file, "\t{liu|lis} %s,%d\n\t{oril|ori} %s,%s,%d\n",
3339 reg_names[0], (neg_size >> 16) & 0xffff,
3340 reg_names[0], reg_names[0], neg_size & 0xffff);
979721f8 3341
b6c9286a
MM		 3342 asm_fprintf (file, "\t{sf|subf} %s,%s,%s\n", reg_names[0], reg_names[0],
3343 reg_names[1]);
3344
3345 for (regno = 3; size > 0; regno++, size -= reg_size, loc -= reg_size)
3346 asm_fprintf (file, load_reg, reg_names[regno], loc, reg_names[0]);
3347 }
3348 }
3349 }
3350#endif
3351
3352
1875cc88
JW		 3353 /* If TARGET_MINIMAL_TOC, and the constant pool is needed, then load the
3354 TOC_TABLE address into register 30. */
4697a36c 3355 if (TARGET_TOC && TARGET_MINIMAL_TOC && get_pool_size () != 0)
3daf36a4 3356 {
d14a6d05
MM		 3357 char buf[256];
3358
b6c9286a 3359#ifdef TARGET_RELOCATABLE
d14a6d05
MM		 3360 if (TARGET_RELOCATABLE)
3361 {
874a0744 3362 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
19d2d16f 3363 fputs ("\tbl ", file);
d14a6d05 3364 assemble_name (file, buf);
19d2d16f 3365 putc ('\n', file);
d14a6d05 3366
874a0744 3367 ASM_OUTPUT_INTERNAL_LABEL (file, "LCF", rs6000_pic_labelno);
4697a36c 3368 fprintf (file, "\tmflr %s\n", reg_names[30]);
3daf36a4 3369
03a7e1a5 3370 asm_fprintf (file, (TARGET_32BIT) ? "\t{l|lwz}" : "\tld");
4697a36c 3371 fprintf (file, " %s,(", reg_names[0]);
874a0744
MM		 3372 ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno);
3373 assemble_name (file, buf);
19d2d16f 3374 putc ('-', file);
874a0744
MM		 3375 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
3376 assemble_name (file, buf);
4697a36c
MM		 3377 fprintf (file, ")(%s)\n", reg_names[30]);
3378 asm_fprintf (file, "\t{cax|add} %s,%s,%s\n",
3379 reg_names[30], reg_names[0], reg_names[30]);
874a0744 3380 rs6000_pic_labelno++;
d14a6d05 3381 }
b6c9286a
MM		 3382 else
3383#endif
3384
3385 switch (DEFAULT_ABI)
3386 {
3387 case ABI_V4:
c81bebd7 3388 case ABI_SOLARIS:
b6c9286a 3389 case ABI_AIX_NODESC:
8f802bfb 3390 if (TARGET_32BIT)
b6c9286a
MM		 3391 {
3392 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
3393 asm_fprintf (file, "\t{cau|addis} %s,%s,", reg_names[30], reg_names[0]);
3394 assemble_name (file, buf);
3395 asm_fprintf (file, "@ha\n");
3396 if (TARGET_NEW_MNEMONICS)
3397 {
3398 asm_fprintf (file, "\taddi %s,%s,", reg_names[30], reg_names[30]);
3399 assemble_name (file, buf);
3400 asm_fprintf (file, "@l\n");
3401 }
3402 else
3403 {
3404 asm_fprintf (file, "\tcal %s,", reg_names[30]);
3405 assemble_name (file, buf);
3406 asm_fprintf (file, "@l(%s)\n", reg_names[30]);
3407 }
3408 }
3409 else
3410 abort ();
3411
3412 break;
3413
3414 case ABI_NT:
3415 case ABI_AIX:
3416 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 0);
3417 asm_fprintf (file, "\t{l|lwz} %s,", reg_names[30]);
3933e0e1 3418 assemble_name (file, buf);
b6c9286a
MM		 3419 asm_fprintf (file, "(%s)\n", reg_names[2]);
3420 break;
3933e0e1 3421 }
b6c9286a 3422 }
4697a36c 3423
b6c9286a
MM		 3424 if (DEFAULT_ABI == ABI_NT)
3425 {
3426 assemble_name (file, XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0));
3427 fputs (".b:\n", file);
3daf36a4 3428 }
9878760c
RK		 3429}
3430
3431/* Write function epilogue. */
3432
3433void
3434output_epilog (file, size)
3435 FILE *file;
3436 int size;
3437{
4697a36c 3438 rs6000_stack_t *info = rs6000_stack_info ();
8f802bfb 3439 char *load_reg = (TARGET_32BIT) ? "\t{l|lwz} %s,%d(%s)\n" : "\tld %s,%d(%s)\n";
9878760c 3440 rtx insn = get_last_insn ();
979721f8
MM		 3441 int sp_reg = 1;
3442 int sp_offset = 0;
5b5040b9 3443 int i;
9878760c 3444
5b5040b9
RK		 3445 /* Forget about any temporaries created */
3446 for (i = 0; i < NUM_MACHINE_MODES; i++)
3447 stack_temps[i] = NULL_RTX;
8f75773e 3448
9878760c
RK		 3449 /* If the last insn was a BARRIER, we don't have to write anything except
3450 the trace table. */
3451 if (GET_CODE (insn) == NOTE)
3452 insn = prev_nonnote_insn (insn);
3453 if (insn == 0 || GET_CODE (insn) != BARRIER)
3454 {
3455 /* If we have a frame pointer, a call to alloca, or a large stack
3456 frame, restore the old stack pointer using the backchain. Otherwise,
3457 we know what size to update it with. */
3458 if (frame_pointer_needed || current_function_calls_alloca
4697a36c 3459 || info->total_size > 32767)
979721f8
MM		 3460 {
3461 /* Under V.4, don't reset the stack pointer until after we're done
3462 loading the saved registers. */
c81bebd7 3463 if (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS)
979721f8
MM		 3464 sp_reg = 11;
3465
3466 asm_fprintf (file, load_reg, reg_names[sp_reg], 0, reg_names[1]);
3467 }
4697a36c
MM		 3468 else if (info->push_p)
3469 {
c81bebd7 3470 if (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS)
979721f8
MM		 3471 sp_offset = info->total_size;
3472 else if (TARGET_NEW_MNEMONICS)
4697a36c
MM		 3473 asm_fprintf (file, "\taddi %s,%s,%d\n", reg_names[1], reg_names[1], info->total_size);
3474 else
3475 asm_fprintf (file, "\tcal %s,%d(%s)\n", reg_names[1], info->total_size, reg_names[1]);
3476 }
9878760c 3477
b4ac57ab 3478 /* Get the old lr if we saved it. */
4697a36c 3479 if (info->lr_save_p)
979721f8 3480 asm_fprintf (file, load_reg, reg_names[0], info->lr_save_offset + sp_offset, reg_names[sp_reg]);
9878760c
RK		 3481
3482 /* Get the old cr if we saved it. */
4697a36c 3483 if (info->cr_save_p)
979721f8 3484 asm_fprintf (file, load_reg, reg_names[12], info->cr_save_offset + sp_offset, reg_names[sp_reg]);
9878760c 3485
b4ac57ab 3486 /* Set LR here to try to overlap restores below. */
4697a36c
MM		 3487 if (info->lr_save_p)
3488 asm_fprintf (file, "\tmtlr %s\n", reg_names[0]);
b4ac57ab 3489
9878760c 3490 /* Restore gpr's. */
4697a36c 3491 if (! TARGET_MULTIPLE || info->first_gp_reg_save == 31 || TARGET_64BIT)
85638c0d 3492 {
4697a36c 3493 int regno = info->first_gp_reg_save;
979721f8 3494 int loc = info->gp_save_offset + sp_offset;
8f802bfb 3495 int reg_size = (TARGET_32BIT) ? 4 : 8;
85638c0d 3496
4697a36c 3497 for ( ; regno < 32; regno++, loc += reg_size)
979721f8 3498 asm_fprintf (file, load_reg, reg_names[regno], loc, reg_names[sp_reg]);
85638c0d
RK		 3499 }
3500
4697a36c
MM		 3501 else if (info->first_gp_reg_save != 32)
3502 asm_fprintf (file, "\t{lm|lmw} %s,%d(%s)\n",
3503 reg_names[info->first_gp_reg_save],
979721f8
MM		 3504 info->gp_save_offset + sp_offset,
3505 reg_names[sp_reg]);
9878760c 3506
b4ac57ab 3507 /* Restore fpr's if we can do it without calling a function. */
4697a36c
MM		 3508 if (FP_SAVE_INLINE (info->first_fp_reg_save))
3509 {
3510 int regno = info->first_fp_reg_save;
979721f8 3511 int loc = info->fp_save_offset + sp_offset;
4697a36c
MM		 3512
3513 for ( ; regno < 64; regno++, loc += 8)
979721f8 3514 asm_fprintf (file, "\tlfd %s,%d(%s)\n", reg_names[regno], loc, reg_names[sp_reg]);
4697a36c 3515 }
9878760c 3516
28edebac
RK		 3517 /* If we saved cr, restore it here. Just those of cr2, cr3, and cr4
3518 that were used. */
4697a36c
MM		 3519 if (info->cr_save_p)
3520 asm_fprintf (file, "\tmtcrf %d,%s\n",
85638c0d
RK		 3521 (regs_ever_live[70] != 0) * 0x20
3522 + (regs_ever_live[71] != 0) * 0x10
4697a36c 3523 + (regs_ever_live[72] != 0) * 0x8, reg_names[12]);
9878760c 3524
979721f8
MM		 3525 /* If this is V.4, unwind the stack pointer after all of the loads have been done */
3526 if (sp_offset)
3527 {
3528 if (TARGET_NEW_MNEMONICS)
3529 asm_fprintf (file, "\taddi %s,%s,%d\n", reg_names[1], reg_names[1], sp_offset);
3530 else
3531 asm_fprintf (file, "\tcal %s,%d(%s)\n", reg_names[1], sp_offset, reg_names[1]);
3532 }
3533 else if (sp_reg != 1)
3534 asm_fprintf (file, "\tmr %s,%s\n", reg_names[1], reg_names[sp_reg]);
3535
b4ac57ab
RS		 3536 /* If we have to restore more than two FP registers, branch to the
3537 restore function. It will return to our caller. */
4697a36c
MM		 3538 if (info->first_fp_reg_save != 64 && !FP_SAVE_INLINE (info->first_fp_reg_save))
3539 asm_fprintf (file, "\tb %s%d%s\n", RESTORE_FP_PREFIX,
3540 info->first_fp_reg_save - 32, RESTORE_FP_SUFFIX);
b4ac57ab 3541 else
85638c0d 3542 asm_fprintf (file, "\t{br|blr}\n");
9878760c 3543 }
b4ac57ab 3544
9b30bae2 3545 /* Output a traceback table here. See /usr/include/sys/debug.h for info
314fc5a9
ILT		 3546 on its format.
3547
3548 We don't output a traceback table if -finhibit-size-directive was
3549 used. The documentation for -finhibit-size-directive reads
3550 ``don't output a @code{.size} assembler directive, or anything
3551 else that would cause trouble if the function is split in the
3552 middle, and the two halves are placed at locations far apart in
3553 memory.'' The traceback table has this property, since it
3554 includes the offset from the start of the function to the
4d30c363
MM		 3555 traceback table itself.
3556
3557 System V.4 Powerpc's (and the embedded ABI derived from it) use a
b6c9286a
MM		 3558 different traceback table. */
3559 if (DEFAULT_ABI == ABI_AIX && ! flag_inhibit_size_directive)
9b30bae2 3560 {
314fc5a9
ILT		 3561 char *fname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
3562 int fixed_parms, float_parms, parm_info;
3563 int i;
3564
b6c9286a
MM		 3565 while (*fname == '.') /* V.4 encodes . in the name */
3566 fname++;
3567
314fc5a9
ILT		 3568 /* Need label immediately before tbtab, so we can compute its offset
3569 from the function start. */
3570 if (*fname == '*')
3571 ++fname;
3572 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
3573 ASM_OUTPUT_LABEL (file, fname);
3574
3575 /* The .tbtab pseudo-op can only be used for the first eight
3576 expressions, since it can't handle the possibly variable
3577 length fields that follow. However, if you omit the optional
3578 fields, the assembler outputs zeros for all optional fields
3579 anyways, giving each variable length field is minimum length
3580 (as defined in sys/debug.h). Thus we can not use the .tbtab
3581 pseudo-op at all. */
3582
3583 /* An all-zero word flags the start of the tbtab, for debuggers
3584 that have to find it by searching forward from the entry
3585 point or from the current pc. */
19d2d16f 3586 fputs ("\t.long 0\n", file);
314fc5a9
ILT		 3587
3588 /* Tbtab format type. Use format type 0. */
19d2d16f 3589 fputs ("\t.byte 0,", file);
314fc5a9
ILT		 3590
3591 /* Language type. Unfortunately, there doesn't seem to be any
3592 official way to get this info, so we use language_string. C
3593 is 0. C++ is 9. No number defined for Obj-C, so use the
3594 value for C for now. */
3595 if (! strcmp (language_string, "GNU C")
3596 || ! strcmp (language_string, "GNU Obj-C"))
3597 i = 0;
3598 else if (! strcmp (language_string, "GNU F77"))
3599 i = 1;
3600 else if (! strcmp (language_string, "GNU Ada"))
3601 i = 3;
3602 else if (! strcmp (language_string, "GNU PASCAL"))
3603 i = 2;
3604 else if (! strcmp (language_string, "GNU C++"))
3605 i = 9;
3606 else
3607 abort ();
3608 fprintf (file, "%d,", i);
3609
3610 /* 8 single bit fields: global linkage (not set for C extern linkage,
3611 apparently a PL/I convention?), out-of-line epilogue/prologue, offset
3612 from start of procedure stored in tbtab, internal function, function
3613 has controlled storage, function has no toc, function uses fp,
3614 function logs/aborts fp operations. */
3615 /* Assume that fp operations are used if any fp reg must be saved. */
4697a36c 3616 fprintf (file, "%d,", (1 << 5) | ((info->first_fp_reg_save != 64) << 1));
314fc5a9
ILT		 3617
3618 /* 6 bitfields: function is interrupt handler, name present in
3619 proc table, function calls alloca, on condition directives
3620 (controls stack walks, 3 bits), saves condition reg, saves
3621 link reg. */
3622 /* The `function calls alloca' bit seems to be set whenever reg 31 is
3623 set up as a frame pointer, even when there is no alloca call. */
3624 fprintf (file, "%d,",
3625 ((1 << 6) | (frame_pointer_needed << 5)
4697a36c 3626 | (info->cr_save_p << 1) | (info->lr_save_p)));
314fc5a9
ILT		 3627
3628 /* 3 bitfields: saves backchain, spare bit, number of fpr saved
3629 (6 bits). */
3630 fprintf (file, "%d,",
4697a36c 3631 (info->push_p << 7) | (64 - info->first_fp_reg_save));
314fc5a9
ILT		 3632
3633 /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */
3634 fprintf (file, "%d,", (32 - first_reg_to_save ()));
3635
3636 {
3637 /* Compute the parameter info from the function decl argument
3638 list. */
3639 tree decl;
3640 int next_parm_info_bit;
3641
3642 next_parm_info_bit = 31;
3643 parm_info = 0;
3644 fixed_parms = 0;
3645 float_parms = 0;
3646
3647 for (decl = DECL_ARGUMENTS (current_function_decl);
3648 decl; decl = TREE_CHAIN (decl))
3649 {
3650 rtx parameter = DECL_INCOMING_RTL (decl);
3651 enum machine_mode mode = GET_MODE (parameter);
3652
3653 if (GET_CODE (parameter) == REG)
3654 {
3655 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
3656 {
3657 int bits;
3658
3659 float_parms++;
3660
3661 if (mode == SFmode)
3662 bits = 0x2;
3663 else if (mode == DFmode)
3664 bits = 0x3;
3665 else
3666 abort ();
3667
3668 /* If only one bit will fit, don't or in this entry. */
3669 if (next_parm_info_bit > 0)
3670 parm_info |= (bits << (next_parm_info_bit - 1));
3671 next_parm_info_bit -= 2;
3672 }
3673 else
3674 {
3675 fixed_parms += ((GET_MODE_SIZE (mode)
3676 + (UNITS_PER_WORD - 1))
3677 / UNITS_PER_WORD);
3678 next_parm_info_bit -= 1;
3679 }
3680 }
3681 }
3682 }
3683
3684 /* Number of fixed point parameters. */
3685 /* This is actually the number of words of fixed point parameters; thus
3686 an 8 byte struct counts as 2; and thus the maximum value is 8. */
3687 fprintf (file, "%d,", fixed_parms);
3688
3689 /* 2 bitfields: number of floating point parameters (7 bits), parameters
3690 all on stack. */
3691 /* This is actually the number of fp registers that hold parameters;
3692 and thus the maximum value is 13. */
3693 /* Set parameters on stack bit if parameters are not in their original
3694 registers, regardless of whether they are on the stack? Xlc
3695 seems to set the bit when not optimizing. */
3696 fprintf (file, "%d\n", ((float_parms << 1) | (! optimize)));
3697
3698 /* Optional fields follow. Some are variable length. */
3699
3700 /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float,
3701 11 double float. */
3702 /* There is an entry for each parameter in a register, in the order that
3703 they occur in the parameter list. Any intervening arguments on the
3704 stack are ignored. If the list overflows a long (max possible length
3705 34 bits) then completely leave off all elements that don't fit. */
3706 /* Only emit this long if there was at least one parameter. */
3707 if (fixed_parms || float_parms)
3708 fprintf (file, "\t.long %d\n", parm_info);
3709
3710 /* Offset from start of code to tb table. */
19d2d16f 3711 fputs ("\t.long ", file);
314fc5a9
ILT		 3712 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
3713 RS6000_OUTPUT_BASENAME (file, fname);
19d2d16f 3714 fputs ("-.", file);
314fc5a9 3715 RS6000_OUTPUT_BASENAME (file, fname);
19d2d16f 3716 putc ('\n', file);
314fc5a9
ILT		 3717
3718 /* Interrupt handler mask. */
3719 /* Omit this long, since we never set the interrupt handler bit
3720 above. */
3721
3722 /* Number of CTL (controlled storage) anchors. */
3723 /* Omit this long, since the has_ctl bit is never set above. */
3724
3725 /* Displacement into stack of each CTL anchor. */
3726 /* Omit this list of longs, because there are no CTL anchors. */
3727
3728 /* Length of function name. */
3729 fprintf (file, "\t.short %d\n", strlen (fname));
3730
3731 /* Function name. */
3732 assemble_string (fname, strlen (fname));
3733
3734 /* Register for alloca automatic storage; this is always reg 31.
3735 Only emit this if the alloca bit was set above. */
3736 if (frame_pointer_needed)
19d2d16f 3737 fputs ("\t.byte 31\n", file);
9b30bae2 3738 }
4697a36c 3739
b6c9286a 3740 /* Reset varargs and save TOC indicator */
4697a36c 3741 rs6000_sysv_varargs_p = 0;
b6c9286a 3742 rs6000_save_toc_p = 0;
766a866c 3743 rs6000_pic_register = (rtx)0;
b6c9286a
MM		 3744
3745 if (DEFAULT_ABI == ABI_NT)
3746 {
3747 RS6000_OUTPUT_BASENAME (file, XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0));
3748 fputs (".e:\nFE_MOT_RESVD..", file);
3749 RS6000_OUTPUT_BASENAME (file, XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0));
3750 fputs (":\n", file);
3751 }
9878760c
RK		 3752}
3753\f
3754/* Output a TOC entry. We derive the entry name from what is
3755 being written. */
3756
3757void
3758output_toc (file, x, labelno)
3759 FILE *file;
3760 rtx x;
3761 int labelno;
3762{
3763 char buf[256];
3764 char *name = buf;
b6c9286a 3765 char *real_name;
9878760c
RK		 3766 rtx base = x;
3767 int offset = 0;
3768
4697a36c
MM		 3769 if (TARGET_NO_TOC)
3770 abort ();
3771
ff1720ed
RK		 3772 /* if we're going to put a double constant in the TOC, make sure it's
3773 aligned properly when strict alignment is on. */
3774 if (GET_CODE (x) == CONST_DOUBLE
3775 && STRICT_ALIGNMENT
3776 && GET_MODE (x) == DFmode
3777 && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC)) {
3778 ASM_OUTPUT_ALIGN (file, 3);
3779 }
3780
3781
b6c9286a 3782 if (TARGET_ELF && TARGET_MINIMAL_TOC)
d14a6d05
MM		 3783 {
3784 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
3785 fprintf (file, "%d = .-", labelno);
3786 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LCTOC");
19d2d16f 3787 fputs ("1\n", file);
d14a6d05
MM		 3788 }
3789 else
d14a6d05 3790 ASM_OUTPUT_INTERNAL_LABEL (file, "LC", labelno);
9878760c 3791
37c37a57
RK		 3792 /* Handle FP constants specially. Note that if we have a minimal
3793 TOC, things we put here aren't actually in the TOC, so we can allow
3794 FP constants. */
042259f2 3795 if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode
37c37a57 3796 && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC))
9878760c 3797 {
042259f2
DE		 3798 REAL_VALUE_TYPE rv;
3799 long k[2];
0adc764e 3800
042259f2
DE		 3801 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
3802 REAL_VALUE_TO_TARGET_DOUBLE (rv, k);
1875cc88 3803 if (TARGET_MINIMAL_TOC)
042259f2 3804 fprintf (file, "\t.long %ld\n\t.long %ld\n", k[0], k[1]);
1875cc88 3805 else
0adc764e 3806 fprintf (file, "\t.tc FD_%lx_%lx[TC],%ld,%ld\n",
042259f2 3807 k[0], k[1], k[0], k[1]);
9878760c
RK		 3808 return;
3809 }
3810 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode
37c37a57 3811 && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC))
9878760c 3812 {
042259f2
DE		 3813 REAL_VALUE_TYPE rv;
3814 long l;
9878760c 3815
042259f2
DE		 3816 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
3817 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
3818
3819 if (TARGET_MINIMAL_TOC)
3820 fprintf (file, "\t.long %d\n", l);
3821 else
3822 fprintf (file, "\t.tc FS_%x[TC],%d\n", l, l);
3823 return;
3824 }
3825 else if (GET_MODE (x) == DImode
3826 && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE)
3827 && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC))
3828 {
3829 HOST_WIDE_INT low;
3830 HOST_WIDE_INT high;
3831
3832 if (GET_CODE (x) == CONST_DOUBLE)
3833 {
3834 low = CONST_DOUBLE_LOW (x);
3835 high = CONST_DOUBLE_HIGH (x);
3836 }
3837 else
3838#if HOST_BITS_PER_WIDE_INT == 32
3839 {
3840 low = INTVAL (x);
3841 high = (low < 0) ? ~0 : 0;
3842 }
3843#else
3844 {
3845 low = INTVAL (x) & 0xffffffff;
3846 high = (HOST_WIDE_INT) INTVAL (x) >> 32;
3847 }
3848#endif
9878760c 3849
1875cc88 3850 if (TARGET_MINIMAL_TOC)
042259f2 3851 fprintf (file, "\t.long %ld\n\t.long %ld\n", high, low);
1875cc88 3852 else
042259f2
DE		 3853 fprintf (file, "\t.tc ID_%lx_%lx[TC],%ld,%ld\n",
3854 high, low, high, low);
9878760c
RK		 3855 return;
3856 }
3857
3858 if (GET_CODE (x) == CONST)
3859 {
3860 base = XEXP (XEXP (x, 0), 0);
3861 offset = INTVAL (XEXP (XEXP (x, 0), 1));
3862 }
3863
3864 if (GET_CODE (base) == SYMBOL_REF)
3865 name = XSTR (base, 0);
3866 else if (GET_CODE (base) == LABEL_REF)
3867 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (XEXP (base, 0)));
3868 else if (GET_CODE (base) == CODE_LABEL)
3869 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (base));
3870 else
3871 abort ();
3872
1875cc88 3873 if (TARGET_MINIMAL_TOC)
19d2d16f 3874 fputs ("\t.long ", file);
1875cc88
JW		 3875 else
3876 {
b6c9286a
MM		 3877 STRIP_NAME_ENCODING (real_name, name);
3878 fprintf (file, "\t.tc %s", real_name);
9878760c 3879
1875cc88
JW		 3880 if (offset < 0)
3881 fprintf (file, ".N%d", - offset);
3882 else if (offset)
3883 fprintf (file, ".P%d", offset);
9878760c 3884
19d2d16f 3885 fputs ("[TC],", file);
1875cc88 3886 }
9878760c 3887 output_addr_const (file, x);
19d2d16f 3888 putc ('\n', file);
9878760c
RK		 3889}
3890\f
3891/* Output an assembler pseudo-op to write an ASCII string of N characters
3892 starting at P to FILE.
3893
3894 On the RS/6000, we have to do this using the .byte operation and
3895 write out special characters outside the quoted string.
3896 Also, the assembler is broken; very long strings are truncated,
3897 so we must artificially break them up early. */
3898
3899void
3900output_ascii (file, p, n)
3901 FILE *file;
3902 char *p;
3903 int n;
3904{
3905 char c;
3906 int i, count_string;
3907 char *for_string = "\t.byte \"";
3908 char *for_decimal = "\t.byte ";
3909 char *to_close = NULL;
3910
3911 count_string = 0;
3912 for (i = 0; i < n; i++)
3913 {
3914 c = *p++;
3915 if (c >= ' ' && c < 0177)
3916 {
3917 if (for_string)
3918 fputs (for_string, file);
3919 putc (c, file);
3920
3921 /* Write two quotes to get one. */
3922 if (c == '"')
3923 {
3924 putc (c, file);
3925 ++count_string;
3926 }
3927
3928 for_string = NULL;
3929 for_decimal = "\"\n\t.byte ";
3930 to_close = "\"\n";
3931 ++count_string;
3932
3933 if (count_string >= 512)
3934 {
3935 fputs (to_close, file);
3936
3937 for_string = "\t.byte \"";
3938 for_decimal = "\t.byte ";
3939 to_close = NULL;
3940 count_string = 0;
3941 }
3942 }
3943 else
3944 {
3945 if (for_decimal)
3946 fputs (for_decimal, file);
3947 fprintf (file, "%d", c);
3948
3949 for_string = "\n\t.byte \"";
3950 for_decimal = ", ";
3951 to_close = "\n";
3952 count_string = 0;
3953 }
3954 }
3955
3956 /* Now close the string if we have written one. Then end the line. */
3957 if (to_close)
3958 fprintf (file, to_close);
3959}
3960\f
3961/* Generate a unique section name for FILENAME for a section type
3962 represented by SECTION_DESC. Output goes into BUF.
3963
3964 SECTION_DESC can be any string, as long as it is different for each
3965 possible section type.
3966
3967 We name the section in the same manner as xlc. The name begins with an
3968 underscore followed by the filename (after stripping any leading directory
11e5fe42
RK		 3969 names) with the last period replaced by the string SECTION_DESC. If
3970 FILENAME does not contain a period, SECTION_DESC is appended to the end of
3971 the name. */
9878760c
RK		 3972
3973void
3974rs6000_gen_section_name (buf, filename, section_desc)
3975 char **buf;
3976 char *filename;
3977 char *section_desc;
3978{
11e5fe42 3979 char *q, *after_last_slash, *last_period;
9878760c
RK		 3980 char *p;
3981 int len;
9878760c
RK		 3982
3983 after_last_slash = filename;
3984 for (q = filename; *q; q++)
11e5fe42
RK		 3985 {
3986 if (*q == '/')
3987 after_last_slash = q + 1;
3988 else if (*q == '.')
3989 last_period = q;
3990 }
9878760c 3991
11e5fe42 3992 len = strlen (after_last_slash) + strlen (section_desc) + 2;
9878760c
RK		 3993 *buf = (char *) permalloc (len);
3994
3995 p = *buf;
3996 *p++ = '_';
3997
3998 for (q = after_last_slash; *q; q++)
3999 {
11e5fe42 4000 if (q == last_period)
9878760c
RK		 4001 {
4002 strcpy (p, section_desc);
4003 p += strlen (section_desc);
9878760c
RK		 4004 }
4005
4006 else if (isalnum (*q))
4007 *p++ = *q;
4008 }
4009
11e5fe42 4010 if (last_period == 0)
9878760c
RK		 4011 strcpy (p, section_desc);
4012 else
4013 *p = '\0';
4014}
e165f3f0
RK		 4015\f
4016/* Write function profiler code. */
4017
4018void
4019output_function_profiler (file, labelno)
4020 FILE *file;
4021 int labelno;
4022{
4023 /* The last used parameter register. */
4024 int last_parm_reg;
4025 int i, j;
3daf36a4 4026 char buf[100];
e165f3f0 4027
b6c9286a
MM		 4028 if (DEFAULT_ABI != ABI_AIX)
4029 abort ();
4030
e165f3f0
RK		 4031 /* Set up a TOC entry for the profiler label. */
4032 toc_section ();
3daf36a4
ILT		 4033 ASM_OUTPUT_INTERNAL_LABEL (file, "LPC", labelno);
4034 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
35fc1624 4035 if (TARGET_MINIMAL_TOC)
3daf36a4 4036 {
19d2d16f 4037 fputs ("\t.long ", file);
3daf36a4 4038 assemble_name (file, buf);
19d2d16f 4039 putc ('\n', file);
3daf36a4 4040 }
35fc1624 4041 else
3daf36a4 4042 {
19d2d16f 4043 fputs ("\t.tc\t", file);
3daf36a4 4044 assemble_name (file, buf);
19d2d16f 4045 fputs ("[TC],", file);
3daf36a4 4046 assemble_name (file, buf);
19d2d16f 4047 putc ('\n', file);
3daf36a4 4048 }
e165f3f0
RK		 4049 text_section ();
4050
4051 /* Figure out last used parameter register. The proper thing to do is
4052 to walk incoming args of the function. A function might have live
4053 parameter registers even if it has no incoming args. */
4054
4055 for (last_parm_reg = 10;
4056 last_parm_reg > 2 && ! regs_ever_live [last_parm_reg];
4057 last_parm_reg--)
4058 ;
4059
4060 /* Save parameter registers in regs 23-30. Don't overwrite reg 31, since
4061 it might be set up as the frame pointer. */
4062
4063 for (i = 3, j = 30; i <= last_parm_reg; i++, j--)
19d2d16f 4064 asm_fprintf (file, "\tmr %d,%d\n", j, i);
e165f3f0
RK		 4065
4066 /* Load location address into r3, and call mcount. */
4067
3daf36a4 4068 ASM_GENERATE_INTERNAL_LABEL (buf, "LPC", labelno);
19d2d16f 4069 asm_fprintf (file, "\t{l|lwz} %s,", reg_names[3]);
3daf36a4 4070 assemble_name (file, buf);
19d2d16f 4071 asm_fprintf (file, "(%s)\n\tbl .mcount\n", reg_names[2]);
e165f3f0
RK		 4072
4073 /* Restore parameter registers. */
4074
4075 for (i = 3, j = 30; i <= last_parm_reg; i++, j--)
19d2d16f 4076 asm_fprintf (file, "\tmr %d,%d\n", i, j);
e165f3f0 4077}
a251ffd0
TG		 4078
4079/* Adjust the cost of a scheduling dependency. Return the new cost of
4080 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
4081
4082int
a06faf84 4083rs6000_adjust_cost (insn, link, dep_insn, cost)
a251ffd0
TG		 4084 rtx insn;
4085 rtx link;
4086 rtx dep_insn;
4087 int cost;
4088{
4089 if (! recog_memoized (insn))
4090 return 0;
4091
4092 if (REG_NOTE_KIND (link) != 0)
4093 return 0;
4094
4095 if (REG_NOTE_KIND (link) == 0)
4096 {
4097 /* Data dependency; DEP_INSN writes a register that INSN reads some
4098 cycles later. */
4099
4100 /* Tell the first scheduling pass about the latency between a mtctr
4101 and bctr (and mtlr and br/blr). The first scheduling pass will not
4102 know about this latency since the mtctr instruction, which has the
4103 latency associated to it, will be generated by reload. */
4104 if (get_attr_type (insn) == TYPE_JMPREG)
4105 return TARGET_POWER ? 5 : 4;
4106
4107 /* Fall out to return default cost. */
4108 }
4109
4110 return cost;
4111}
b6c9286a
MM		 4112
4113/* Return how many instructions the machine can issue per cycle */
4114int get_issue_rate()
4115{
4116 switch (rs6000_cpu_attr) {
4117 case CPU_RIOS1:
4118 return 3; /* ? */
4119 case CPU_RIOS2:
4120 return 4;
4121 case CPU_PPC601:
4122 return 3; /* ? */
b6c9286a
MM		 4123 case CPU_PPC603:
4124 return 2;
4125 case CPU_PPC604:
4126 return 4;
4127 case CPU_PPC620:
4128 return 4;
4129 default:
4130 return 1;
4131 }
4132}
4133
4134\f
4135/* Output insns to flush the {data|instruction} caches after building a
4136 trampoline. */
4137
4138static void
4139rs6000_sync_trampoline (addr)
4140 rtx addr;
4141{
4142 enum machine_mode pmode = Pmode;
4143 rtx reg = gen_reg_rtx (pmode);
4144 rtx mem2;
4145 rtx mem1;
4146 int size = rs6000_trampoline_size ();
4147 rtx (*sub_fcn) PROTO ((rtx, rtx, rtx));
4148 rtx (*cmp_fcn) PROTO ((rtx, rtx));
4149 rtx label;
4150
ac2a93a1 4151 if (TARGET_32BIT)
b6c9286a 4152 {
ac2a93a1
DE		 4153 sub_fcn = gen_subsi3;
4154 cmp_fcn = gen_cmpsi;
b6c9286a
MM		 4155 }
4156 else
4157 {
ac2a93a1
DE		 4158 sub_fcn = gen_subdi3;
4159 cmp_fcn = gen_cmpdi;
b6c9286a
MM		 4160 }
4161
4162 addr = force_reg (pmode, addr);
4163 mem2 = gen_rtx (MEM, pmode, gen_rtx (PLUS, pmode, addr, reg));
4164 mem1 = gen_rtx (MEM, pmode, addr);
4165
4166 /* Issue a loop of dcbst's to flush the data cache */
4167 emit_move_insn (reg, GEN_INT (size-4));
4168 label = gen_label_rtx ();
4169 emit_label (label);
4170 emit_insn (gen_dcbst (mem2, addr, reg));
4171 emit_insn ((*sub_fcn) (reg, reg, GEN_INT (4)));
4172 emit_insn ((*cmp_fcn) (reg, const0_rtx));
4173 emit_jump_insn (gen_bgt (label));
4174
4175 /* Issue a sync after the dcbst's to let things settle down */
4176 emit_insn (gen_sync (mem1));
4177
4178 /* Issue a loop of icbi's to flush the instruction cache */
4179 emit_move_insn (reg, GEN_INT (size-4));
4180 label = gen_label_rtx ();
4181 emit_label (label);
4182 emit_insn (gen_icbi (mem2, addr, reg));
4183 emit_insn ((*sub_fcn) (reg, reg, GEN_INT (4)));
4184 emit_insn ((*cmp_fcn) (reg, const0_rtx));
4185 emit_jump_insn (gen_bgt (label));
4186
4187 /* Issue a sync after the icbi's to let things settle down */
4188 emit_insn (gen_sync (mem1));
4189
4190 /* Finally issue an isync to synchronize the icache */
4191 emit_insn (gen_isync (mem1));
4192}
4193
4194\f
4195/* Output assembler code for a block containing the constant parts
4196 of a trampoline, leaving space for the variable parts.
4197
4198 The trampoline should set the static chain pointer to value placed
4199 into the trampoline and should branch to the specified routine. */
4200
4201void
4202rs6000_trampoline_template (file)
4203 FILE *file;
4204{
4205 char *sc = reg_names[STATIC_CHAIN_REGNUM];
4206 char *r0 = reg_names[0];
7c59dc5d 4207 char *r2 = reg_names[2];
b6c9286a
MM		 4208
4209 switch (DEFAULT_ABI)
4210 {
4211 default:
4212 abort ();
4213
4214 /* Under AIX, this is not code at all, but merely a data area,
4215 since that is the way all functions are called. The first word is
4216 the address of the function, the second word is the TOC pointer (r2),
4217 and the third word is the static chain value. */
4218 case ABI_AIX:
8f802bfb 4219 fprintf (file, "\t.long %s\n", (TARGET_32BIT) ? "0,0,0" : "0,0,0,0,0,0");
b6c9286a
MM		 4220 break;
4221
4222
4223 /* V.4/eabi function pointers are just a single pointer, so we need to
4224 do the full gory code to load up the static chain. */
4225 case ABI_V4:
c81bebd7 4226 case ABI_SOLARIS:
b6c9286a
MM		 4227 case ABI_AIX_NODESC:
4228 if (STATIC_CHAIN_REGNUM == 0 || !TARGET_NEW_MNEMONICS)
4229 abort ();
4230
8f802bfb 4231 if (TARGET_32BIT)
b6c9286a
MM		 4232 {
4233 fprintf (file, "\tmflr %s\n", r0); /* offset 0 */
4234 fprintf (file, "\tbl .LTRAMP1\n"); /* offset 4 */
4235 fprintf (file, "\t.long 0,0\n"); /* offset 8 */
4236 fprintf (file, ".LTRAMP1:\n");
4237 fprintf (file, "\tmflr %s\n", sc); /* offset 20 */
4238 fprintf (file, "\tmtlr %s\n", r0); /* offset 24 */
4239 fprintf (file, "\tlwz %s,0(%s)\n", r0, sc); /* offset 28 */
4240 fprintf (file, "\tlwz %s,4(%s)\n", sc, sc); /* offset 32 */
4241 fprintf (file, "\tmtctr %s\n", r0); /* offset 36 */
4242 fprintf (file, "\tbctr\n"); /* offset 40 */
4243 }
8f802bfb
DE		 4244 else
4245 {
4246 fprintf (file, "\tmflr %s\n", r0); /* offset 0 */
4247 fprintf (file, "\tbl .LTRAMP1\n"); /* offset 4 */
4248 fprintf (file, "\t.long 0,0,0,0\n"); /* offset 8 */
4249 fprintf (file, ".LTRAMP1:\n");
4250 fprintf (file, "\tmflr %s\n", sc); /* offset 28 */
4251 fprintf (file, "\tmtlr %s\n", r0); /* offset 32 */
4252 fprintf (file, "\tld %s,0(%s)\n", r0, sc); /* offset 36 */
4253 fprintf (file, "\tld %s,8(%s)\n", sc, sc); /* offset 40 */
4254 fprintf (file, "\tmtctr %s\n", r0); /* offset 44 */
4255 fprintf (file, "\tbctr\n"); /* offset 48 */
4256 }
b6c9286a
MM		 4257 break;
4258
4259 /* NT function pointers point to a two word area (real address, TOC)
4260 which unfortunately does not include a static chain field. So we
7c59dc5d
MM		 4261 use the function field to point to ..LTRAMP1 and the toc field
4262 to point to the whole table. */
b6c9286a 4263 case ABI_NT:
7c59dc5d
MM		 4264 if (STATIC_CHAIN_REGNUM == 0
4265 || STATIC_CHAIN_REGNUM == 2
4266 || TARGET_64BIT
4267 || !TARGET_NEW_MNEMONICS)
b6c9286a
MM		 4268 abort ();
4269
7c59dc5d
MM		 4270 fprintf (file, "\t.ualong 0\n"); /* offset 0 */
4271 fprintf (file, "\t.ualong 0\n"); /* offset 4 */
4272 fprintf (file, "\t.ualong 0\n"); /* offset 8 */
4273 fprintf (file, "\t.ualong 0\n"); /* offset 12 */
4274 fprintf (file, "\t.ualong 0\n"); /* offset 16 */
8bd04c56 4275 fprintf (file, "..LTRAMP1..0:\n"); /* offset 20 */
7c59dc5d
MM		 4276 fprintf (file, "\tlwz %s,8(%s)\n", r0, r2); /* offset 24 */
4277 fprintf (file, "\tlwz %s,12(%s)\n", sc, r2); /* offset 28 */
4278 fprintf (file, "\tmtctr %s\n", r0); /* offset 32 */
4279 fprintf (file, "\tlwz %s,16(%s)\n", r2, r2); /* offset 36 */
4280 fprintf (file, "\tbctr\n"); /* offset 40 */
b6c9286a
MM		 4281 break;
4282 }
4283
4284 return;
4285}
4286
4287/* Length in units of the trampoline for entering a nested function. */
4288
4289int
4290rs6000_trampoline_size ()
4291{
4292 int ret = 0;
4293
4294 switch (DEFAULT_ABI)
4295 {
4296 default:
4297 abort ();
4298
4299 case ABI_AIX:
8f802bfb 4300 ret = (TARGET_32BIT) ? 12 : 24;
b6c9286a
MM		 4301 break;
4302
4303 case ABI_V4:
c81bebd7 4304 case ABI_SOLARIS:
b6c9286a 4305 case ABI_AIX_NODESC:
03a7e1a5 4306 ret = (TARGET_32BIT) ? 40 : 48;
b6c9286a
MM		 4307 break;
4308
4309 case ABI_NT:
7c59dc5d 4310 ret = 20;
b6c9286a
MM		 4311 break;
4312 }
4313
4314 return ret;
4315}
4316
4317/* Emit RTL insns to initialize the variable parts of a trampoline.
4318 FNADDR is an RTX for the address of the function's pure code.
4319 CXT is an RTX for the static chain value for the function. */
4320
4321void
4322rs6000_initialize_trampoline (addr, fnaddr, cxt)
4323 rtx addr;
4324 rtx fnaddr;
4325 rtx cxt;
4326{
ac2a93a1 4327 enum machine_mode pmode = Pmode;
8bd04c56
MM		 4328 int regsize = (TARGET_32BIT) ? 4 : 8;
4329 rtx ctx_reg = force_reg (pmode, cxt);
b6c9286a
MM		 4330
4331 switch (DEFAULT_ABI)
4332 {
4333 default:
4334 abort ();
4335
8bd04c56
MM		 4336/* Macros to shorten the code expansions below. */
4337#define MEM_DEREF(addr) gen_rtx (MEM, pmode, memory_address (pmode, addr))
7c59dc5d
MM		 4338#define MEM_PLUS(addr,offset) gen_rtx (MEM, pmode, memory_address (pmode, plus_constant (addr, offset)))
4339
b6c9286a
MM		 4340 /* Under AIX, just build the 3 word function descriptor */
4341 case ABI_AIX:
8bd04c56
MM		 4342 {
4343 rtx fn_reg = gen_reg_rtx (pmode);
4344 rtx toc_reg = gen_reg_rtx (pmode);
4345 emit_move_insn (fn_reg, MEM_DEREF (fnaddr));
4346 emit_move_insn (toc_reg, MEM_PLUS (fnaddr, 4));
4347 emit_move_insn (MEM_DEREF (addr), fn_reg);
4348 emit_move_insn (MEM_PLUS (addr, regsize), toc_reg);
4349 emit_move_insn (MEM_PLUS (addr, 2*regsize), ctx_reg);
4350 }
b6c9286a
MM		 4351 break;
4352
4353 /* Under V.4/eabi, update the two words after the bl to have the real
4354 function address and the static chain. */
4355 case ABI_V4:
c81bebd7 4356 case ABI_SOLARIS:
b6c9286a 4357 case ABI_AIX_NODESC:
8bd04c56
MM		 4358 {
4359 rtx reg = gen_reg_rtx (pmode);
4360 emit_move_insn (reg, fnaddr);
4361 emit_move_insn (MEM_PLUS (addr, 8), reg);
4362 emit_move_insn (MEM_PLUS (addr, 8 + regsize), ctx_reg);
4363 rs6000_sync_trampoline (addr);
4364 }
b6c9286a
MM		 4365 break;
4366
8bd04c56
MM		 4367 /* Under NT, update the first word to point to the ..LTRAMP1..0 header,
4368 the second word will point to the whole trampoline, third-fifth words
7c59dc5d 4369 will then have the real address, static chain, and toc value. */
b6c9286a 4370 case ABI_NT:
8bd04c56
MM		 4371 {
4372 rtx tramp_reg = gen_reg_rtx (pmode);
4373 rtx fn_reg = gen_reg_rtx (pmode);
4374 rtx toc_reg = gen_reg_rtx (pmode);
4375
4376 emit_move_insn (tramp_reg, gen_rtx (SYMBOL_REF, pmode, "..LTRAMP1..0"));
4377 addr = force_reg (pmode, addr);
4378 emit_move_insn (fn_reg, MEM_DEREF (fnaddr));
4379 emit_move_insn (toc_reg, MEM_PLUS (fnaddr, regsize));
4380 emit_move_insn (MEM_DEREF (addr), tramp_reg);
4381 emit_move_insn (MEM_PLUS (addr, regsize), addr);
4382 emit_move_insn (MEM_PLUS (addr, 2*regsize), fn_reg);
4383 emit_move_insn (MEM_PLUS (addr, 3*regsize), ctx_reg);
4384 emit_move_insn (MEM_PLUS (addr, 4*regsize), gen_rtx (REG, pmode, 2));
4385 }
b6c9286a
MM		 4386 break;
4387 }
4388
4389 return;
4390}
7509c759
MM		 4391
4392\f
4393/* If defined, a C expression whose value is nonzero if IDENTIFIER
4394 with arguments ARGS is a valid machine specific attribute for DECL.
4395 The attributes in ATTRIBUTES have previously been assigned to DECL. */
4396
4397int
4398rs6000_valid_decl_attribute_p (decl, attributes, identifier, args)
4399 tree decl;
4400 tree attributes;
4401 tree identifier;
4402 tree args;
4403{
4404 return 0;
4405}
4406
4407/* If defined, a C expression whose value is nonzero if IDENTIFIER
4408 with arguments ARGS is a valid machine specific attribute for TYPE.
4409 The attributes in ATTRIBUTES have previously been assigned to TYPE. */
4410
4411int
4412rs6000_valid_type_attribute_p (type, attributes, identifier, args)
4413 tree type;
4414 tree attributes;
4415 tree identifier;
4416 tree args;
4417{
4418 if (TREE_CODE (type) != FUNCTION_TYPE
4419 && TREE_CODE (type) != FIELD_DECL
4420 && TREE_CODE (type) != TYPE_DECL)
4421 return 0;
4422
6a4cee5f
MM		 4423 /* Longcall attribute says that the function is not within 2**26 bytes
4424 of the current function, and to do an indirect call. */
4425 if (is_attribute_p ("longcall", identifier))
4426 return (args == NULL_TREE);
4427
7509c759
MM		 4428 if (DEFAULT_ABI == ABI_NT)
4429 {
4430 /* Stdcall attribute says callee is responsible for popping arguments
4431 if they are not variable. */
4432 if (is_attribute_p ("stdcall", identifier))
4433 return (args == NULL_TREE);
4434
4435 /* Cdecl attribute says the callee is a normal C declaration */
4436 if (is_attribute_p ("cdecl", identifier))
4437 return (args == NULL_TREE);
4438
4439 /* Dllimport attribute says says the caller is to call the function
4440 indirectly through a __imp_<name> pointer. */
4441 if (is_attribute_p ("dllimport", identifier))
4442 return (args == NULL_TREE);
4443
4444 /* Dllexport attribute says says the callee is to create a __imp_<name>
4445 pointer. */
4446 if (is_attribute_p ("dllexport", identifier))
4447 return (args == NULL_TREE);
e56bb9ed
MM		 4448
4449 /* Exception attribute allows the user to specify 1-2 strings or identifiers
4450 that will fill in the 3rd and 4th fields of the structured exception
4451 table. */
4452 if (is_attribute_p ("exception", identifier))
4453 {
4454 int i;
4455
4456 if (args == NULL_TREE)
4457 return 0;
4458
4459 for (i = 0; i < 2 && args != NULL_TREE; i++)
4460 {
4461 tree this_arg = TREE_VALUE (args);
4462 args = TREE_PURPOSE (args);
4463
4464 if (TREE_CODE (this_arg) != STRING_CST
4465 && TREE_CODE (this_arg) != IDENTIFIER_NODE)
4466 return 0;
4467 }
4468
4469 return (args == NULL_TREE);
4470 }
7509c759
MM		 4471 }
4472
4473 return 0;
4474}
4475
4476/* If defined, a C expression whose value is zero if the attributes on
4477 TYPE1 and TYPE2 are incompatible, one if they are compatible, and
4478 two if they are nearly compatible (which causes a warning to be
4479 generated). */
4480
4481int
4482rs6000_comp_type_attributes (type1, type2)
4483 tree type1;
4484 tree type2;
4485{
4486 return 1;
4487}
4488
4489/* If defined, a C statement that assigns default attributes to newly
4490 defined TYPE. */
4491
4492void
4493rs6000_set_default_type_attributes (type)
4494 tree type;
4495{
4496}
4497
4498/* Return a dll import reference corresponding to to a call's SYMBOL_REF */
4499struct rtx_def *
4500rs6000_dll_import_ref (call_ref)
4501 rtx call_ref;
4502{
4503 char *call_name;
4504 int len;
4505 char *p;
4506 rtx reg1, reg2;
4507 tree node;
4508
4509 if (GET_CODE (call_ref) != SYMBOL_REF)
4510 abort ();
4511
4512 call_name = XSTR (call_ref, 0);
4513 len = sizeof ("__imp_") + strlen (call_name);
4514 p = alloca (len);
4515 reg2 = gen_reg_rtx (Pmode);
4516
4517 strcpy (p, "__imp_");
4518 strcat (p, call_name);
4519 node = get_identifier (p);
4520
4521 reg1 = force_reg (Pmode, gen_rtx (SYMBOL_REF, VOIDmode, IDENTIFIER_POINTER (node)));
4522 emit_move_insn (reg2, gen_rtx (MEM, Pmode, reg1));
4523
4524 return reg2;
4525}
4526
6a4cee5f
MM		 4527/* Return a reference suitable for calling a function with the longcall attribute. */
4528struct rtx_def *
4529rs6000_longcall_ref (call_ref)
4530 rtx call_ref;
4531{
4532 char *call_name;
4533 int len;
4534 char *p;
4535 rtx reg1, reg2;
4536 tree node;
4537
4538 if (GET_CODE (call_ref) != SYMBOL_REF)
4539 return call_ref;
4540
4541 /* System V adds '.' to the internal name, so skip them. */
4542 call_name = XSTR (call_ref, 0);
4543 if (*call_name == '.')
4544 {
4545 while (*call_name == '.')
4546 call_name++;
4547
4548 node = get_identifier (call_name);
4549 call_ref = gen_rtx (SYMBOL_REF, VOIDmode, IDENTIFIER_POINTER (node));
4550 }
4551
4552 return force_reg (Pmode, call_ref);
4553}
4554
7509c759
MM		 4555\f
4556/* A C statement or statements to switch to the appropriate section
4557 for output of RTX in mode MODE. You can assume that RTX is some
4558 kind of constant in RTL. The argument MODE is redundant except in
4559 the case of a `const_int' rtx. Select the section by calling
4560 `text_section' or one of the alternatives for other sections.
4561
4562 Do not define this macro if you put all constants in the read-only
4563 data section. */
4564
4565#ifdef USING_SVR4_H
4566
4567void
4568rs6000_select_rtx_section (mode, x)
4569 enum machine_mode mode;
4570 rtx x;
4571{
4572 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x))
4573 toc_section ();
7509c759
MM		 4574 else
4575 const_section ();
4576}
4577
4578/* A C statement or statements to switch to the appropriate
4579 section for output of DECL. DECL is either a `VAR_DECL' node
4580 or a constant of some sort. RELOC indicates whether forming
4581 the initial value of DECL requires link-time relocations. */
4582
4583void
4584rs6000_select_section (decl, reloc)
4585 tree decl;
4586 int reloc;
4587{
4588 int size = int_size_in_bytes (TREE_TYPE (decl));
4589
4590 if (TREE_CODE (decl) == STRING_CST)
4591 {
88228c4b 4592 if (! flag_writable_strings)
7509c759 4593 const_section ();
7509c759
MM		 4594 else
4595 data_section ();
4596 }
4597 else if (TREE_CODE (decl) == VAR_DECL)
4598 {
4599 if ((flag_pic && reloc)
4600 || !TREE_READONLY (decl)
4601 || TREE_SIDE_EFFECTS (decl)
4602 || !DECL_INITIAL (decl)
4603 || (DECL_INITIAL (decl) != error_mark_node
4604 && !TREE_CONSTANT (DECL_INITIAL (decl))))
4605 {
88228c4b 4606 if (TARGET_SDATA && (size > 0) && (size <= g_switch_value))
7509c759
MM		 4607 sdata_section ();
4608 else
4609 data_section ();
4610 }
4611 else
4612 {
88228c4b 4613 if (TARGET_SDATA && (size > 0) && (size <= g_switch_value))
c81bebd7
MM		 4614 {
4615 if (TARGET_EABI)
4616 sdata2_section ();
4617 else
4618 sdata_section (); /* System V doesn't have .sdata2/.sbss2 */
4619 }
7509c759
MM		 4620 else
4621 const_section ();
4622 }
4623 }
4624 else
4625 const_section ();
4626}
4627#endif /* USING_SVR4_H */
GNU Compiler Collection
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