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Commit | Line | Data |
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9878760c | 1 | /* Subroutines used for code generation on IBM RS/6000. |
cf27b467 | 2 | Copyright (C) 1991, 1993, 1994, 1995, 1996 Free Software Foundation, Inc. |
fab3bcc3 | 3 | Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) |
9878760c RK |
4 | |
5 | This file is part of GNU CC. | |
6 | ||
7 | GNU CC is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2, or (at your option) | |
10 | any later version. | |
11 | ||
12 | GNU CC is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GNU CC; see the file COPYING. If not, write to | |
c15c9075 RK |
19 | the Free Software Foundation, 59 Temple Place - Suite 330, |
20 | Boston, MA 02111-1307, USA. */ | |
9878760c RK |
21 | |
22 | #include <stdio.h> | |
127b0efc | 23 | #include <ctype.h> |
9878760c RK |
24 | #include "config.h" |
25 | #include "rtl.h" | |
26 | #include "regs.h" | |
27 | #include "hard-reg-set.h" | |
28 | #include "real.h" | |
29 | #include "insn-config.h" | |
30 | #include "conditions.h" | |
31 | #include "insn-flags.h" | |
32 | #include "output.h" | |
33 | #include "insn-attr.h" | |
34 | #include "flags.h" | |
35 | #include "recog.h" | |
36 | #include "expr.h" | |
37 | #include "obstack.h" | |
9b30bae2 JW |
38 | #include "tree.h" |
39 | ||
7509c759 MM |
40 | #ifndef TARGET_NO_PROTOTYPE |
41 | #define TARGET_NO_PROTOTYPE 0 | |
42 | #endif | |
43 | ||
9b30bae2 | 44 | extern char *language_string; |
5248c961 | 45 | extern int profile_block_flag; |
9878760c RK |
46 | |
47 | #define min(A,B) ((A) < (B) ? (A) : (B)) | |
48 | #define max(A,B) ((A) > (B) ? (A) : (B)) | |
49 | ||
5248c961 RK |
50 | /* Target cpu type */ |
51 | ||
52 | enum processor_type rs6000_cpu; | |
8e3f41e7 MM |
53 | struct rs6000_cpu_select rs6000_select[3] = |
54 | { | |
55 | /* switch name, tune arch */ | |
5d6426e0 | 56 | { (char *)0, "--with-cpu=", 1, 1 }, |
8e3f41e7 MM |
57 | { (char *)0, "-mcpu=", 1, 1 }, |
58 | { (char *)0, "-mtune=", 1, 0 }, | |
59 | }; | |
5248c961 | 60 | |
9878760c RK |
61 | /* Set to non-zero by "fix" operation to indicate that itrunc and |
62 | uitrunc must be defined. */ | |
63 | ||
64 | int rs6000_trunc_used; | |
65 | ||
66 | /* Set to non-zero once they have been defined. */ | |
67 | ||
68 | static int trunc_defined; | |
69 | ||
c764f757 RK |
70 | /* Set to non-zero once AIX common-mode calls have been defined. */ |
71 | static int common_mode_defined; | |
9878760c RK |
72 | /* Save information from a "cmpxx" operation until the branch or scc is |
73 | emitted. */ | |
74 | ||
75 | rtx rs6000_compare_op0, rs6000_compare_op1; | |
76 | int rs6000_compare_fp_p; | |
874a0744 MM |
77 | |
78 | #ifdef USING_SVR4_H | |
79 | /* Label number of label created for -mrelocatable, to call to so we can | |
80 | get the address of the GOT section */ | |
81 | int rs6000_pic_labelno; | |
82 | #endif | |
4697a36c MM |
83 | |
84 | /* Whether a System V.4 varargs area was created. */ | |
85 | int rs6000_sysv_varargs_p; | |
8f75773e | 86 | |
b6c9286a MM |
87 | /* Whether we need to save the TOC register. */ |
88 | int rs6000_save_toc_p; | |
89 | ||
90 | /* ABI enumeration available for subtarget to use. */ | |
91 | enum rs6000_abi rs6000_current_abi; | |
92 | ||
8f75773e | 93 | /* Temporary memory used to convert integer -> float */ |
5b5040b9 | 94 | static rtx stack_temps[NUM_MACHINE_MODES]; |
8f75773e | 95 | |
24d304eb RK |
96 | \f |
97 | /* Print the options used in the assembly file. */ | |
98 | ||
99 | extern char *version_string, *language_string; | |
100 | ||
caf44502 | 101 | struct asm_option |
24d304eb RK |
102 | { |
103 | char *string; | |
104 | int *variable; | |
105 | int on_value; | |
106 | }; | |
107 | ||
108 | #define MAX_LINE 79 | |
109 | ||
110 | static int | |
111 | output_option (file, type, name, pos) | |
112 | FILE *file; | |
113 | char *type; | |
114 | char *name; | |
115 | int pos; | |
116 | { | |
117 | int type_len = strlen (type); | |
118 | int name_len = strlen (name); | |
119 | ||
120 | if (1 + type_len + name_len + pos > MAX_LINE) | |
121 | { | |
122 | fprintf (file, "\n # %s%s", type, name); | |
123 | return 3 + type_len + name_len; | |
124 | } | |
125 | fprintf (file, " %s%s", type, name); | |
126 | return pos + 1 + type_len + name_len; | |
127 | } | |
128 | ||
129 | static struct { char *name; int value; } m_options[] = TARGET_SWITCHES; | |
130 | ||
131 | void | |
132 | output_options (file, f_options, f_len, W_options, W_len) | |
133 | FILE *file; | |
caf44502 | 134 | struct asm_option *f_options; |
24d304eb | 135 | int f_len; |
caf44502 | 136 | struct asm_option *W_options; |
24d304eb RK |
137 | int W_len; |
138 | { | |
139 | int j; | |
140 | int flags = target_flags; | |
141 | int pos = 32767; | |
142 | ||
143 | fprintf (file, " # %s %s", language_string, version_string); | |
144 | ||
145 | if (optimize) | |
146 | { | |
147 | char opt_string[20]; | |
148 | sprintf (opt_string, "%d", optimize); | |
149 | pos = output_option (file, "-O", opt_string, pos); | |
150 | } | |
151 | ||
152 | if (profile_flag) | |
153 | pos = output_option (file, "-p", "", pos); | |
154 | ||
155 | if (profile_block_flag) | |
156 | pos = output_option (file, "-a", "", pos); | |
157 | ||
158 | if (inhibit_warnings) | |
159 | pos = output_option (file, "-w", "", pos); | |
160 | ||
161 | for (j = 0; j < f_len; j++) | |
162 | { | |
163 | if (*f_options[j].variable == f_options[j].on_value) | |
164 | pos = output_option (file, "-f", f_options[j].string, pos); | |
165 | } | |
166 | ||
167 | for (j = 0; j < W_len; j++) | |
168 | { | |
169 | if (*W_options[j].variable == W_options[j].on_value) | |
170 | pos = output_option (file, "-W", W_options[j].string, pos); | |
171 | } | |
172 | ||
173 | for (j = 0; j < sizeof m_options / sizeof m_options[0]; j++) | |
174 | { | |
175 | if (m_options[j].name[0] != '\0' | |
176 | && m_options[j].value > 0 | |
177 | && ((m_options[j].value & flags) == m_options[j].value)) | |
178 | { | |
179 | pos = output_option (file, "-m", m_options[j].name, pos); | |
180 | flags &= ~ m_options[j].value; | |
181 | } | |
182 | } | |
183 | ||
8e3f41e7 MM |
184 | for (j = 0; j < sizeof (rs6000_select) / sizeof(rs6000_select[0]); j++) |
185 | if (rs6000_select[j].string != (char *)0) | |
186 | pos = output_option (file, rs6000_select[j].name, rs6000_select[j].string, pos); | |
24d304eb RK |
187 | |
188 | fputs ("\n\n", file); | |
189 | } | |
190 | ||
9878760c | 191 | \f |
5248c961 RK |
192 | /* Override command line options. Mostly we process the processor |
193 | type and sometimes adjust other TARGET_ options. */ | |
194 | ||
195 | void | |
8e3f41e7 MM |
196 | rs6000_override_options (default_cpu) |
197 | char *default_cpu; | |
5248c961 | 198 | { |
8e3f41e7 MM |
199 | int i, j; |
200 | struct rs6000_cpu_select *ptr; | |
5248c961 | 201 | |
85638c0d RK |
202 | /* Simplify the entries below by making a mask for any POWER |
203 | variant and any PowerPC variant. */ | |
204 | ||
938937d8 | 205 | #define POWER_MASKS (MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING) |
68c49ffa RK |
206 | #define POWERPC_MASKS (MASK_POWERPC | MASK_PPC_GPOPT \ |
207 | | MASK_PPC_GFXOPT | MASK_POWERPC64) | |
208 | #define POWERPC_OPT_MASKS (MASK_PPC_GPOPT | MASK_PPC_GFXOPT) | |
85638c0d | 209 | |
5248c961 RK |
210 | static struct ptt |
211 | { | |
212 | char *name; /* Canonical processor name. */ | |
213 | enum processor_type processor; /* Processor type enum value. */ | |
214 | int target_enable; /* Target flags to enable. */ | |
215 | int target_disable; /* Target flags to disable. */ | |
216 | } processor_target_table[] | |
cf27b467 MM |
217 | = {{"common", PROCESSOR_COMMON, MASK_NEW_MNEMONICS, |
218 | POWER_MASKS | POWERPC_MASKS}, | |
db7f1e43 | 219 | {"power", PROCESSOR_POWER, |
938937d8 | 220 | MASK_POWER | MASK_MULTIPLE | MASK_STRING, |
db7f1e43 | 221 | MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS}, |
8e3f41e7 MM |
222 | {"power2", PROCESSOR_POWER, |
223 | MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING, | |
224 | POWERPC_MASKS | MASK_NEW_MNEMONICS}, | |
db7f1e43 RK |
225 | {"powerpc", PROCESSOR_POWERPC, |
226 | MASK_POWERPC | MASK_NEW_MNEMONICS, | |
68c49ffa | 227 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}, |
db7f1e43 | 228 | {"rios", PROCESSOR_RIOS1, |
938937d8 | 229 | MASK_POWER | MASK_MULTIPLE | MASK_STRING, |
db7f1e43 RK |
230 | MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS}, |
231 | {"rios1", PROCESSOR_RIOS1, | |
938937d8 | 232 | MASK_POWER | MASK_MULTIPLE | MASK_STRING, |
db7f1e43 RK |
233 | MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS}, |
234 | {"rsc", PROCESSOR_PPC601, | |
938937d8 | 235 | MASK_POWER | MASK_MULTIPLE | MASK_STRING, |
db7f1e43 RK |
236 | MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS}, |
237 | {"rsc1", PROCESSOR_PPC601, | |
938937d8 | 238 | MASK_POWER | MASK_MULTIPLE | MASK_STRING, |
db7f1e43 RK |
239 | MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS}, |
240 | {"rios2", PROCESSOR_RIOS2, | |
938937d8 | 241 | MASK_POWER | MASK_MULTIPLE | MASK_STRING | MASK_POWER2, |
db7f1e43 | 242 | POWERPC_MASKS | MASK_NEW_MNEMONICS}, |
49a0b204 MM |
243 | {"403", PROCESSOR_PPC403, |
244 | MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS, | |
245 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}, | |
cf27b467 MM |
246 | {"505", PROCESSOR_MPCCORE, |
247 | MASK_POWERPC | MASK_NEW_MNEMONICS, | |
248 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}, | |
5248c961 | 249 | {"601", PROCESSOR_PPC601, |
938937d8 | 250 | MASK_POWER | MASK_POWERPC | MASK_NEW_MNEMONICS | MASK_MULTIPLE | MASK_STRING, |
68c49ffa | 251 | MASK_POWER2 | POWERPC_OPT_MASKS | MASK_POWERPC64}, |
1ec26da6 | 252 | {"602", PROCESSOR_PPC603, |
cf27b467 MM |
253 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, |
254 | POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}, | |
5248c961 | 255 | {"603", PROCESSOR_PPC603, |
68c49ffa RK |
256 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, |
257 | POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}, | |
b6c9286a MM |
258 | {"603e", PROCESSOR_PPC603, |
259 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, | |
260 | POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}, | |
5248c961 | 261 | {"604", PROCESSOR_PPC604, |
b6c9286a MM |
262 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, |
263 | POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}, | |
264 | {"620", PROCESSOR_PPC620, | |
68c49ffa | 265 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, |
cf27b467 MM |
266 | POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}, |
267 | {"821", PROCESSOR_MPCCORE, | |
268 | MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS, | |
269 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}, | |
270 | {"860", PROCESSOR_MPCCORE, | |
271 | MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS, | |
272 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}}; | |
5248c961 RK |
273 | |
274 | int ptt_size = sizeof (processor_target_table) / sizeof (struct ptt); | |
275 | ||
8a61d227 | 276 | int multiple = TARGET_MULTIPLE; /* save current -mmultiple/-mno-multiple status */ |
938937d8 | 277 | int string = TARGET_STRING; /* save current -mstring/-mno-string status */ |
8a61d227 | 278 | |
5248c961 RK |
279 | profile_block_flag = 0; |
280 | ||
281 | /* Identify the processor type */ | |
8e3f41e7 MM |
282 | rs6000_select[0].string = default_cpu; |
283 | rs6000_cpu = PROCESSOR_DEFAULT; | |
8e3f41e7 MM |
284 | |
285 | for (i = 0; i < sizeof (rs6000_select) / sizeof (rs6000_select[0]); i++) | |
5248c961 | 286 | { |
8e3f41e7 MM |
287 | ptr = &rs6000_select[i]; |
288 | if (ptr->string != (char *)0 && ptr->string[0] != '\0') | |
5248c961 | 289 | { |
8e3f41e7 MM |
290 | for (j = 0; j < ptt_size; j++) |
291 | if (! strcmp (ptr->string, processor_target_table[j].name)) | |
292 | { | |
293 | if (ptr->set_tune_p) | |
294 | rs6000_cpu = processor_target_table[j].processor; | |
295 | ||
296 | if (ptr->set_arch_p) | |
297 | { | |
298 | target_flags |= processor_target_table[j].target_enable; | |
299 | target_flags &= ~processor_target_table[j].target_disable; | |
300 | } | |
301 | break; | |
302 | } | |
303 | ||
304 | if (i == ptt_size) | |
305 | error ("bad value (%s) for %s switch", ptr->string, ptr->name); | |
5248c961 RK |
306 | } |
307 | } | |
8a61d227 MM |
308 | |
309 | /* If -mmultiple or -mno-multiple was explicitly used, don't | |
310 | override with the processor default */ | |
311 | if (TARGET_MULTIPLE_SET) | |
312 | target_flags = (target_flags & ~MASK_MULTIPLE) | multiple; | |
7e69e155 | 313 | |
938937d8 MM |
314 | /* If -mstring or -mno-string was explicitly used, don't |
315 | override with the processor default */ | |
316 | if (TARGET_STRING_SET) | |
1f5515bf | 317 | target_flags = (target_flags & ~MASK_STRING) | string; |
938937d8 | 318 | |
7e69e155 MM |
319 | /* Don't allow -mmultiple or -mstring on little endian systems, because the |
320 | hardware doesn't support the instructions used in little endian mode */ | |
321 | if (!BYTES_BIG_ENDIAN) | |
322 | { | |
323 | if (TARGET_MULTIPLE) | |
324 | { | |
325 | target_flags &= ~MASK_MULTIPLE; | |
326 | if (TARGET_MULTIPLE_SET) | |
327 | warning ("-mmultiple is not supported on little endian systems"); | |
328 | } | |
329 | ||
330 | if (TARGET_STRING) | |
331 | { | |
332 | target_flags &= ~MASK_STRING; | |
938937d8 MM |
333 | if (TARGET_STRING_SET) |
334 | warning ("-mstring is not supported on little endian systems"); | |
7e69e155 MM |
335 | } |
336 | } | |
3933e0e1 MM |
337 | |
338 | #ifdef SUBTARGET_OVERRIDE_OPTIONS | |
339 | SUBTARGET_OVERRIDE_OPTIONS; | |
340 | #endif | |
5248c961 | 341 | } |
24d304eb RK |
342 | \f |
343 | /* Create a CONST_DOUBLE from a string. */ | |
344 | ||
345 | struct rtx_def * | |
346 | rs6000_float_const (string, mode) | |
347 | char *string; | |
348 | enum machine_mode mode; | |
349 | { | |
350 | REAL_VALUE_TYPE value = REAL_VALUE_ATOF (string, mode); | |
351 | return immed_real_const_1 (value, mode); | |
352 | } | |
353 | ||
75814ad4 MM |
354 | \f |
355 | /* Create a CONST_DOUBLE like immed_double_const, except reverse the | |
356 | two parts of the constant if the target is little endian. */ | |
357 | ||
d679bebf RK |
358 | struct rtx_def * |
359 | rs6000_immed_double_const (i0, i1, mode) | |
75814ad4 MM |
360 | HOST_WIDE_INT i0, i1; |
361 | enum machine_mode mode; | |
362 | { | |
363 | if (! WORDS_BIG_ENDIAN) | |
364 | return immed_double_const (i1, i0, mode); | |
365 | ||
366 | return immed_double_const (i0, i1, mode); | |
367 | } | |
368 | ||
5248c961 | 369 | \f |
9878760c RK |
370 | /* Return non-zero if this function is known to have a null epilogue. */ |
371 | ||
372 | int | |
373 | direct_return () | |
374 | { | |
4697a36c MM |
375 | if (reload_completed) |
376 | { | |
377 | rs6000_stack_t *info = rs6000_stack_info (); | |
378 | ||
379 | if (info->first_gp_reg_save == 32 | |
380 | && info->first_fp_reg_save == 64 | |
381 | && !info->lr_save_p | |
1b4a2731 | 382 | && !info->cr_save_p |
4697a36c MM |
383 | && !info->push_p) |
384 | return 1; | |
385 | } | |
386 | ||
387 | return 0; | |
9878760c RK |
388 | } |
389 | ||
390 | /* Returns 1 always. */ | |
391 | ||
392 | int | |
393 | any_operand (op, mode) | |
394 | register rtx op; | |
395 | enum machine_mode mode; | |
396 | { | |
397 | return 1; | |
398 | } | |
399 | ||
b6c9286a MM |
400 | /* Returns 1 if op is the count register */ |
401 | int count_register_operand(op, mode) | |
402 | register rtx op; | |
403 | enum machine_mode mode; | |
404 | { | |
405 | if (GET_CODE (op) != REG) | |
406 | return 0; | |
407 | ||
408 | if (REGNO (op) == COUNT_REGISTER_REGNUM) | |
409 | return 1; | |
410 | ||
411 | if (REGNO (op) > FIRST_PSEUDO_REGISTER) | |
412 | return 1; | |
413 | ||
414 | return 0; | |
415 | } | |
416 | ||
9878760c RK |
417 | /* Return 1 if OP is a constant that can fit in a D field. */ |
418 | ||
419 | int | |
420 | short_cint_operand (op, mode) | |
421 | register rtx op; | |
422 | enum machine_mode mode; | |
423 | { | |
424 | return (GET_CODE (op) == CONST_INT | |
425 | && (unsigned) (INTVAL (op) + 0x8000) < 0x10000); | |
426 | } | |
427 | ||
428 | /* Similar for a unsigned D field. */ | |
429 | ||
430 | int | |
431 | u_short_cint_operand (op, mode) | |
432 | register rtx op; | |
433 | enum machine_mode mode; | |
434 | { | |
435 | return (GET_CODE (op) == CONST_INT && (INTVAL (op) & 0xffff0000) == 0); | |
436 | } | |
437 | ||
dcfedcd0 RK |
438 | /* Return 1 if OP is a CONST_INT that cannot fit in a signed D field. */ |
439 | ||
440 | int | |
441 | non_short_cint_operand (op, mode) | |
442 | register rtx op; | |
443 | enum machine_mode mode; | |
444 | { | |
445 | return (GET_CODE (op) == CONST_INT | |
446 | && (unsigned) (INTVAL (op) + 0x8000) >= 0x10000); | |
447 | } | |
448 | ||
9878760c RK |
449 | /* Returns 1 if OP is a register that is not special (i.e., not MQ, |
450 | ctr, or lr). */ | |
451 | ||
452 | int | |
cd2b37d9 | 453 | gpc_reg_operand (op, mode) |
9878760c RK |
454 | register rtx op; |
455 | enum machine_mode mode; | |
456 | { | |
457 | return (register_operand (op, mode) | |
458 | && (GET_CODE (op) != REG || REGNO (op) >= 67 || REGNO (op) < 64)); | |
459 | } | |
460 | ||
461 | /* Returns 1 if OP is either a pseudo-register or a register denoting a | |
462 | CR field. */ | |
463 | ||
464 | int | |
465 | cc_reg_operand (op, mode) | |
466 | register rtx op; | |
467 | enum machine_mode mode; | |
468 | { | |
469 | return (register_operand (op, mode) | |
470 | && (GET_CODE (op) != REG | |
471 | || REGNO (op) >= FIRST_PSEUDO_REGISTER | |
472 | || CR_REGNO_P (REGNO (op)))); | |
473 | } | |
474 | ||
475 | /* Returns 1 if OP is either a constant integer valid for a D-field or a | |
476 | non-special register. If a register, it must be in the proper mode unless | |
477 | MODE is VOIDmode. */ | |
478 | ||
479 | int | |
480 | reg_or_short_operand (op, mode) | |
481 | register rtx op; | |
482 | enum machine_mode mode; | |
483 | { | |
f5a28898 | 484 | return short_cint_operand (op, mode) || gpc_reg_operand (op, mode); |
9878760c RK |
485 | } |
486 | ||
487 | /* Similar, except check if the negation of the constant would be valid for | |
488 | a D-field. */ | |
489 | ||
490 | int | |
491 | reg_or_neg_short_operand (op, mode) | |
492 | register rtx op; | |
493 | enum machine_mode mode; | |
494 | { | |
495 | if (GET_CODE (op) == CONST_INT) | |
496 | return CONST_OK_FOR_LETTER_P (INTVAL (op), 'P'); | |
497 | ||
cd2b37d9 | 498 | return gpc_reg_operand (op, mode); |
9878760c RK |
499 | } |
500 | ||
501 | /* Return 1 if the operand is either a register or an integer whose high-order | |
502 | 16 bits are zero. */ | |
503 | ||
504 | int | |
505 | reg_or_u_short_operand (op, mode) | |
506 | register rtx op; | |
507 | enum machine_mode mode; | |
508 | { | |
509 | if (GET_CODE (op) == CONST_INT | |
510 | && (INTVAL (op) & 0xffff0000) == 0) | |
511 | return 1; | |
512 | ||
cd2b37d9 | 513 | return gpc_reg_operand (op, mode); |
9878760c RK |
514 | } |
515 | ||
516 | /* Return 1 is the operand is either a non-special register or ANY | |
517 | constant integer. */ | |
518 | ||
519 | int | |
520 | reg_or_cint_operand (op, mode) | |
521 | register rtx op; | |
522 | enum machine_mode mode; | |
523 | { | |
cd2b37d9 | 524 | return GET_CODE (op) == CONST_INT || gpc_reg_operand (op, mode); |
9878760c RK |
525 | } |
526 | ||
6f2f8311 RK |
527 | /* Return 1 if the operand is a CONST_DOUBLE and it can be put into a register |
528 | with one instruction per word. We only do this if we can safely read | |
529 | CONST_DOUBLE_{LOW,HIGH}. */ | |
9878760c RK |
530 | |
531 | int | |
532 | easy_fp_constant (op, mode) | |
533 | register rtx op; | |
534 | register enum machine_mode mode; | |
535 | { | |
9878760c RK |
536 | if (GET_CODE (op) != CONST_DOUBLE |
537 | || GET_MODE (op) != mode | |
538 | || GET_MODE_CLASS (mode) != MODE_FLOAT) | |
539 | return 0; | |
540 | ||
b6c9286a MM |
541 | /* Consider all constants with -msoft-float to be easy */ |
542 | if (TARGET_SOFT_FLOAT) | |
543 | return 1; | |
544 | ||
042259f2 DE |
545 | if (mode == DFmode) |
546 | { | |
547 | long k[2]; | |
548 | REAL_VALUE_TYPE rv; | |
549 | ||
550 | REAL_VALUE_FROM_CONST_DOUBLE (rv, op); | |
551 | REAL_VALUE_TO_TARGET_DOUBLE (rv, k); | |
9878760c | 552 | |
042259f2 DE |
553 | return (((unsigned) (k[0] + 0x8000) < 0x10000 || (k[0] & 0xffff) == 0) |
554 | && ((unsigned) (k[1] + 0x8000) < 0x10000 || (k[1] & 0xffff) == 0)); | |
555 | } | |
556 | else | |
557 | { | |
558 | long l; | |
559 | REAL_VALUE_TYPE rv; | |
560 | ||
561 | REAL_VALUE_FROM_CONST_DOUBLE (rv, op); | |
562 | REAL_VALUE_TO_TARGET_SINGLE (rv, l); | |
9878760c | 563 | |
042259f2 DE |
564 | return ((unsigned) (l + 0x8000) < 0x10000 || (l & 0xffff) == 0); |
565 | } | |
9878760c | 566 | } |
8f75773e | 567 | |
b6c9286a MM |
568 | /* Return 1 if the operand is in volatile memory. Note that during the |
569 | RTL generation phase, memory_operand does not return TRUE for | |
570 | volatile memory references. So this function allows us to | |
571 | recognize volatile references where its safe. */ | |
572 | ||
573 | int | |
574 | volatile_mem_operand (op, mode) | |
575 | register rtx op; | |
576 | enum machine_mode mode; | |
577 | { | |
578 | if (GET_CODE (op) != MEM) | |
579 | return 0; | |
580 | ||
581 | if (!MEM_VOLATILE_P (op)) | |
582 | return 0; | |
583 | ||
584 | if (mode != GET_MODE (op)) | |
585 | return 0; | |
586 | ||
587 | if (reload_completed) | |
588 | return memory_operand (op, mode); | |
589 | ||
590 | if (reload_in_progress) | |
591 | return strict_memory_address_p (mode, XEXP (op, 0)); | |
592 | ||
593 | return memory_address_p (mode, XEXP (op, 0)); | |
594 | } | |
595 | ||
5b5040b9 | 596 | /* Return 1 if the operand is an offsettable memory address. */ |
914c2e77 RK |
597 | |
598 | int | |
5b5040b9 | 599 | offsettable_addr_operand (op, mode) |
914c2e77 RK |
600 | register rtx op; |
601 | enum machine_mode mode; | |
602 | { | |
8f75773e | 603 | return offsettable_address_p (reload_completed | reload_in_progress, |
5b5040b9 | 604 | mode, op); |
914c2e77 RK |
605 | } |
606 | ||
9878760c RK |
607 | /* Return 1 if the operand is either a floating-point register, a pseudo |
608 | register, or memory. */ | |
609 | ||
610 | int | |
611 | fp_reg_or_mem_operand (op, mode) | |
612 | register rtx op; | |
613 | enum machine_mode mode; | |
614 | { | |
615 | return (memory_operand (op, mode) | |
b6c9286a | 616 | || volatile_mem_operand (op, mode) |
9878760c RK |
617 | || (register_operand (op, mode) |
618 | && (GET_CODE (op) != REG | |
619 | || REGNO (op) >= FIRST_PSEUDO_REGISTER | |
620 | || FP_REGNO_P (REGNO (op))))); | |
621 | } | |
622 | ||
623 | /* Return 1 if the operand is either an easy FP constant (see above) or | |
624 | memory. */ | |
625 | ||
626 | int | |
627 | mem_or_easy_const_operand (op, mode) | |
628 | register rtx op; | |
629 | enum machine_mode mode; | |
630 | { | |
631 | return memory_operand (op, mode) || easy_fp_constant (op, mode); | |
632 | } | |
633 | ||
634 | /* Return 1 if the operand is either a non-special register or an item | |
635 | that can be used as the operand of an SI add insn. */ | |
636 | ||
637 | int | |
638 | add_operand (op, mode) | |
639 | register rtx op; | |
640 | enum machine_mode mode; | |
641 | { | |
642 | return (reg_or_short_operand (op, mode) | |
643 | || (GET_CODE (op) == CONST_INT && (INTVAL (op) & 0xffff) == 0)); | |
644 | } | |
645 | ||
dcfedcd0 RK |
646 | /* Return 1 if OP is a constant but not a valid add_operand. */ |
647 | ||
648 | int | |
649 | non_add_cint_operand (op, mode) | |
650 | register rtx op; | |
651 | enum machine_mode mode; | |
652 | { | |
653 | return (GET_CODE (op) == CONST_INT | |
654 | && (unsigned) (INTVAL (op) + 0x8000) >= 0x10000 | |
655 | && (INTVAL (op) & 0xffff) != 0); | |
656 | } | |
657 | ||
9878760c RK |
658 | /* Return 1 if the operand is a non-special register or a constant that |
659 | can be used as the operand of an OR or XOR insn on the RS/6000. */ | |
660 | ||
661 | int | |
662 | logical_operand (op, mode) | |
663 | register rtx op; | |
664 | enum machine_mode mode; | |
665 | { | |
cd2b37d9 | 666 | return (gpc_reg_operand (op, mode) |
9878760c RK |
667 | || (GET_CODE (op) == CONST_INT |
668 | && ((INTVAL (op) & 0xffff0000) == 0 | |
669 | || (INTVAL (op) & 0xffff) == 0))); | |
670 | } | |
671 | ||
dcfedcd0 RK |
672 | /* Return 1 if C is a constant that is not a logical operand (as |
673 | above). */ | |
674 | ||
675 | int | |
676 | non_logical_cint_operand (op, mode) | |
677 | register rtx op; | |
678 | enum machine_mode mode; | |
679 | { | |
680 | return (GET_CODE (op) == CONST_INT | |
681 | && (INTVAL (op) & 0xffff0000) != 0 | |
682 | && (INTVAL (op) & 0xffff) != 0); | |
683 | } | |
684 | ||
9878760c RK |
685 | /* Return 1 if C is a constant that can be encoded in a mask on the |
686 | RS/6000. It is if there are no more than two 1->0 or 0->1 transitions. | |
687 | Reject all ones and all zeros, since these should have been optimized | |
688 | away and confuse the making of MB and ME. */ | |
689 | ||
690 | int | |
691 | mask_constant (c) | |
692 | register int c; | |
693 | { | |
694 | int i; | |
695 | int last_bit_value; | |
696 | int transitions = 0; | |
697 | ||
698 | if (c == 0 || c == ~0) | |
699 | return 0; | |
700 | ||
701 | last_bit_value = c & 1; | |
702 | ||
703 | for (i = 1; i < 32; i++) | |
704 | if (((c >>= 1) & 1) != last_bit_value) | |
705 | last_bit_value ^= 1, transitions++; | |
706 | ||
707 | return transitions <= 2; | |
708 | } | |
709 | ||
710 | /* Return 1 if the operand is a constant that is a mask on the RS/6000. */ | |
711 | ||
712 | int | |
713 | mask_operand (op, mode) | |
714 | register rtx op; | |
715 | enum machine_mode mode; | |
716 | { | |
717 | return GET_CODE (op) == CONST_INT && mask_constant (INTVAL (op)); | |
718 | } | |
719 | ||
720 | /* Return 1 if the operand is either a non-special register or a | |
721 | constant that can be used as the operand of an RS/6000 logical AND insn. */ | |
722 | ||
723 | int | |
724 | and_operand (op, mode) | |
725 | register rtx op; | |
726 | enum machine_mode mode; | |
727 | { | |
728 | return (reg_or_short_operand (op, mode) | |
729 | || logical_operand (op, mode) | |
730 | || mask_operand (op, mode)); | |
731 | } | |
732 | ||
dcfedcd0 RK |
733 | /* Return 1 if the operand is a constant but not a valid operand for an AND |
734 | insn. */ | |
735 | ||
736 | int | |
737 | non_and_cint_operand (op, mode) | |
738 | register rtx op; | |
739 | enum machine_mode mode; | |
740 | { | |
741 | return GET_CODE (op) == CONST_INT && ! and_operand (op, mode); | |
742 | } | |
743 | ||
9878760c RK |
744 | /* Return 1 if the operand is a general register or memory operand. */ |
745 | ||
746 | int | |
747 | reg_or_mem_operand (op, mode) | |
748 | register rtx op; | |
749 | register enum machine_mode mode; | |
750 | { | |
b6c9286a MM |
751 | return (gpc_reg_operand (op, mode) |
752 | || memory_operand (op, mode) | |
753 | || volatile_mem_operand (op, mode)); | |
9878760c RK |
754 | } |
755 | ||
a7a813f7 RK |
756 | /* Return 1 if the operand is a general register or memory operand without |
757 | pre-inc or pre_dec which produces invalid form of PowerPC lwa | |
758 | instruction. */ | |
759 | ||
760 | int | |
761 | lwa_operand (op, mode) | |
762 | register rtx op; | |
763 | register enum machine_mode mode; | |
764 | { | |
765 | rtx inner = op; | |
766 | ||
767 | if (reload_completed && GET_CODE (inner) == SUBREG) | |
768 | inner = SUBREG_REG (inner); | |
769 | ||
770 | return gpc_reg_operand (inner, mode) | |
771 | || (memory_operand (inner, mode) | |
772 | && GET_CODE (XEXP (inner, 0)) != PRE_INC | |
773 | && GET_CODE (XEXP (inner, 0)) != PRE_DEC); | |
774 | } | |
775 | ||
9878760c RK |
776 | /* Return 1 if the operand, used inside a MEM, is a valid first argument |
777 | to CALL. This is a SYMBOL_REF or a pseudo-register, which will be | |
778 | forced to lr. */ | |
779 | ||
780 | int | |
781 | call_operand (op, mode) | |
782 | register rtx op; | |
783 | enum machine_mode mode; | |
784 | { | |
785 | if (mode != VOIDmode && GET_MODE (op) != mode) | |
786 | return 0; | |
787 | ||
788 | return (GET_CODE (op) == SYMBOL_REF | |
789 | || (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER)); | |
790 | } | |
791 | ||
2af3d377 RK |
792 | |
793 | /* Return 1 if the operand is a SYMBOL_REF for a function known to be in | |
794 | this file. */ | |
795 | ||
796 | int | |
797 | current_file_function_operand (op, mode) | |
798 | register rtx op; | |
799 | enum machine_mode mode; | |
800 | { | |
801 | return (GET_CODE (op) == SYMBOL_REF | |
802 | && (SYMBOL_REF_FLAG (op) | |
803 | || op == XEXP (DECL_RTL (current_function_decl), 0))); | |
804 | } | |
805 | ||
806 | ||
9878760c RK |
807 | /* Return 1 if this operand is a valid input for a move insn. */ |
808 | ||
809 | int | |
810 | input_operand (op, mode) | |
811 | register rtx op; | |
812 | enum machine_mode mode; | |
813 | { | |
eb4e8003 | 814 | /* Memory is always valid. */ |
9878760c RK |
815 | if (memory_operand (op, mode)) |
816 | return 1; | |
817 | ||
eb4e8003 RK |
818 | /* For floating-point, easy constants are valid. */ |
819 | if (GET_MODE_CLASS (mode) == MODE_FLOAT | |
820 | && CONSTANT_P (op) | |
821 | && easy_fp_constant (op, mode)) | |
822 | return 1; | |
823 | ||
824 | /* For floating-point or multi-word mode, the only remaining valid type | |
825 | is a register. */ | |
9878760c RK |
826 | if (GET_MODE_CLASS (mode) == MODE_FLOAT |
827 | || GET_MODE_SIZE (mode) > UNITS_PER_WORD) | |
eb4e8003 | 828 | return register_operand (op, mode); |
9878760c | 829 | |
88fe15a1 RK |
830 | /* The only cases left are integral modes one word or smaller (we |
831 | do not get called for MODE_CC values). These can be in any | |
832 | register. */ | |
833 | if (register_operand (op, mode)) | |
a8b3aeda | 834 | return 1; |
88fe15a1 | 835 | |
b49a8bf4 MM |
836 | /* For integer modes, any constant is ok. */ |
837 | if (GET_CODE (op) == CONST_INT) | |
9878760c RK |
838 | return 1; |
839 | ||
84cf9dda | 840 | /* A SYMBOL_REF referring to the TOC is valid. */ |
7fec4abd | 841 | if (LEGITIMATE_CONSTANT_POOL_ADDRESS_P (op)) |
84cf9dda RK |
842 | return 1; |
843 | ||
b6c9286a MM |
844 | /* Windows NT allows SYMBOL_REFs and LABEL_REFs against the TOC |
845 | directly in the instruction stream */ | |
846 | if (DEFAULT_ABI == ABI_NT | |
847 | && (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF)) | |
848 | return 1; | |
849 | ||
88228c4b MM |
850 | /* V.4 allows SYMBOL_REFs and CONSTs that are in the small data region |
851 | to be valid. */ | |
852 | if (DEFAULT_ABI == ABI_V4 | |
853 | && (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST) | |
854 | && small_data_operand (op, Pmode)) | |
855 | return 1; | |
856 | ||
042259f2 | 857 | return 0; |
9878760c | 858 | } |
7509c759 MM |
859 | |
860 | /* Return 1 for an operand in small memory on V.4/eabi */ | |
861 | ||
862 | int | |
863 | small_data_operand (op, mode) | |
864 | rtx op; | |
865 | enum machine_mode mode; | |
866 | { | |
867 | rtx sym_ref, const_part; | |
868 | ||
a54d04b7 MM |
869 | #ifdef TARGET_SDATA |
870 | if (!TARGET_SDATA) | |
871 | return 0; | |
872 | #endif | |
873 | ||
7509c759 MM |
874 | if (DEFAULT_ABI != ABI_V4) |
875 | return 0; | |
876 | ||
88228c4b MM |
877 | if (GET_CODE (op) == SYMBOL_REF) |
878 | sym_ref = op; | |
879 | ||
880 | else if (GET_CODE (op) != CONST | |
881 | || GET_CODE (XEXP (op, 0)) != PLUS | |
882 | || GET_CODE (XEXP (XEXP (op, 0), 0)) != SYMBOL_REF | |
883 | || GET_CODE (XEXP (XEXP (op, 0), 1)) != CONST_INT) | |
7509c759 MM |
884 | return 0; |
885 | ||
88228c4b MM |
886 | else |
887 | sym_ref = XEXP (XEXP (op, 0), 0); | |
888 | ||
889 | if (*XSTR (sym_ref, 0) != '@') | |
7509c759 MM |
890 | return 0; |
891 | ||
892 | return 1; | |
893 | } | |
894 | ||
4697a36c MM |
895 | \f |
896 | /* Initialize a variable CUM of type CUMULATIVE_ARGS | |
897 | for a call to a function whose data type is FNTYPE. | |
898 | For a library call, FNTYPE is 0. | |
899 | ||
900 | For incoming args we set the number of arguments in the prototype large | |
901 | so we never return an EXPR_LIST. */ | |
902 | ||
903 | void | |
904 | init_cumulative_args (cum, fntype, libname, incoming) | |
905 | CUMULATIVE_ARGS *cum; | |
906 | tree fntype; | |
907 | rtx libname; | |
908 | int incoming; | |
909 | { | |
910 | static CUMULATIVE_ARGS zero_cumulative; | |
7509c759 | 911 | enum rs6000_abi abi = DEFAULT_ABI; |
4697a36c MM |
912 | |
913 | *cum = zero_cumulative; | |
914 | cum->words = 0; | |
915 | cum->fregno = FP_ARG_MIN_REG; | |
916 | cum->prototype = (fntype && TYPE_ARG_TYPES (fntype)); | |
7509c759 | 917 | cum->call_cookie = CALL_NORMAL; |
4697a36c MM |
918 | |
919 | if (incoming) | |
920 | { | |
921 | cum->nargs_prototype = 1000; /* don't return an EXPR_LIST */ | |
7509c759 | 922 | if (abi == ABI_V4) |
4697a36c | 923 | cum->varargs_offset = RS6000_VARARGS_OFFSET; |
4697a36c MM |
924 | } |
925 | ||
926 | else if (cum->prototype) | |
927 | cum->nargs_prototype = (list_length (TYPE_ARG_TYPES (fntype)) - 1 | |
928 | + (TYPE_MODE (TREE_TYPE (fntype)) == BLKmode | |
929 | || RETURN_IN_MEMORY (TREE_TYPE (fntype)))); | |
930 | ||
931 | else | |
932 | cum->nargs_prototype = 0; | |
933 | ||
934 | cum->orig_nargs = cum->nargs_prototype; | |
7509c759 MM |
935 | |
936 | /* Check for DLL import functions */ | |
937 | if (abi == ABI_NT | |
938 | && fntype | |
939 | && lookup_attribute ("dllimport", TYPE_ATTRIBUTES (fntype))) | |
940 | cum->call_cookie = CALL_NT_DLLIMPORT; | |
941 | ||
6a4cee5f MM |
942 | /* Also check for longcall's */ |
943 | else if (fntype && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype))) | |
944 | cum->call_cookie = CALL_LONG; | |
945 | ||
4697a36c MM |
946 | if (TARGET_DEBUG_ARG) |
947 | { | |
948 | fprintf (stderr, "\ninit_cumulative_args:"); | |
949 | if (fntype) | |
950 | { | |
951 | tree ret_type = TREE_TYPE (fntype); | |
952 | fprintf (stderr, " ret code = %s,", | |
953 | tree_code_name[ (int)TREE_CODE (ret_type) ]); | |
954 | } | |
955 | ||
7509c759 | 956 | if (abi == ABI_V4 && incoming) |
4697a36c | 957 | fprintf (stderr, " varargs = %d, ", cum->varargs_offset); |
7509c759 | 958 | |
6a4cee5f | 959 | if (cum->call_cookie & CALL_NT_DLLIMPORT) |
7509c759 | 960 | fprintf (stderr, " dllimport,"); |
4697a36c | 961 | |
6a4cee5f MM |
962 | if (cum->call_cookie & CALL_LONG) |
963 | fprintf (stderr, " longcall,"); | |
964 | ||
4697a36c MM |
965 | fprintf (stderr, " proto = %d, nargs = %d\n", |
966 | cum->prototype, cum->nargs_prototype); | |
967 | } | |
968 | } | |
969 | \f | |
b6c9286a MM |
970 | /* If defined, a C expression that gives the alignment boundary, in bits, |
971 | of an argument with the specified mode and type. If it is not defined, | |
972 | PARM_BOUNDARY is used for all arguments. | |
973 | ||
e1f83b4d MM |
974 | Windows NT wants anything >= 8 bytes to be double word aligned. |
975 | ||
976 | V.4 wants long longs to be double word aligned. */ | |
b6c9286a MM |
977 | |
978 | int | |
979 | function_arg_boundary (mode, type) | |
980 | enum machine_mode mode; | |
981 | tree type; | |
982 | { | |
e1f83b4d MM |
983 | if (DEFAULT_ABI == ABI_V4 && mode == DImode) |
984 | return 64; | |
985 | ||
b6c9286a MM |
986 | if (DEFAULT_ABI != ABI_NT || TARGET_64BIT) |
987 | return PARM_BOUNDARY; | |
988 | ||
989 | if (mode != BLKmode) | |
990 | return (GET_MODE_SIZE (mode)) >= 8 ? 64 : 32; | |
991 | ||
992 | return (int_size_in_bytes (type) >= 8) ? 64 : 32; | |
993 | } | |
994 | \f | |
4697a36c MM |
995 | /* Update the data in CUM to advance over an argument |
996 | of mode MODE and data type TYPE. | |
997 | (TYPE is null for libcalls where that information may not be available.) */ | |
998 | ||
999 | void | |
1000 | function_arg_advance (cum, mode, type, named) | |
1001 | CUMULATIVE_ARGS *cum; | |
1002 | enum machine_mode mode; | |
1003 | tree type; | |
1004 | int named; | |
1005 | { | |
b6c9286a MM |
1006 | int align = ((cum->words & 1) != 0 && function_arg_boundary (mode, type) == 64) ? 1 : 0; |
1007 | cum->words += align; | |
4697a36c MM |
1008 | cum->nargs_prototype--; |
1009 | ||
7509c759 | 1010 | if (DEFAULT_ABI == ABI_V4) |
4697a36c MM |
1011 | { |
1012 | /* Long longs must not be split between registers and stack */ | |
1013 | if ((GET_MODE_CLASS (mode) != MODE_FLOAT || TARGET_SOFT_FLOAT) | |
1014 | && type && !AGGREGATE_TYPE_P (type) | |
1015 | && cum->words < GP_ARG_NUM_REG | |
1016 | && cum->words + RS6000_ARG_SIZE (mode, type, named) > GP_ARG_NUM_REG) | |
1017 | { | |
1018 | cum->words = GP_ARG_NUM_REG; | |
1019 | } | |
1020 | ||
1021 | /* Aggregates get passed as pointers */ | |
1022 | if (type && AGGREGATE_TYPE_P (type)) | |
1023 | cum->words++; | |
1024 | ||
1025 | /* Floats go in registers, & don't occupy space in the GP registers | |
1026 | like they do for AIX unless software floating point. */ | |
1027 | else if (GET_MODE_CLASS (mode) == MODE_FLOAT | |
1028 | && TARGET_HARD_FLOAT | |
1029 | && cum->fregno <= FP_ARG_V4_MAX_REG) | |
1030 | cum->fregno++; | |
1031 | ||
1032 | else | |
1033 | cum->words += RS6000_ARG_SIZE (mode, type, 1); | |
1034 | } | |
1035 | else | |
4697a36c MM |
1036 | if (named) |
1037 | { | |
1038 | cum->words += RS6000_ARG_SIZE (mode, type, named); | |
1039 | if (GET_MODE_CLASS (mode) == MODE_FLOAT && TARGET_HARD_FLOAT) | |
1040 | cum->fregno++; | |
1041 | } | |
1042 | ||
1043 | if (TARGET_DEBUG_ARG) | |
1044 | fprintf (stderr, | |
b6c9286a MM |
1045 | "function_adv: words = %2d, fregno = %2d, nargs = %4d, proto = %d, mode = %4s, named = %d, align = %d\n", |
1046 | cum->words, cum->fregno, cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode), named, align); | |
4697a36c MM |
1047 | } |
1048 | \f | |
1049 | /* Determine where to put an argument to a function. | |
1050 | Value is zero to push the argument on the stack, | |
1051 | or a hard register in which to store the argument. | |
1052 | ||
1053 | MODE is the argument's machine mode. | |
1054 | TYPE is the data type of the argument (as a tree). | |
1055 | This is null for libcalls where that information may | |
1056 | not be available. | |
1057 | CUM is a variable of type CUMULATIVE_ARGS which gives info about | |
1058 | the preceding args and about the function being called. | |
1059 | NAMED is nonzero if this argument is a named parameter | |
1060 | (otherwise it is an extra parameter matching an ellipsis). | |
1061 | ||
1062 | On RS/6000 the first eight words of non-FP are normally in registers | |
1063 | and the rest are pushed. Under AIX, the first 13 FP args are in registers. | |
1064 | Under V.4, the first 8 FP args are in registers. | |
1065 | ||
1066 | If this is floating-point and no prototype is specified, we use | |
1067 | both an FP and integer register (or possibly FP reg and stack). Library | |
1068 | functions (when TYPE is zero) always have the proper types for args, | |
1069 | so we can pass the FP value just in one register. emit_library_function | |
1070 | doesn't support EXPR_LIST anyway. */ | |
1071 | ||
1072 | struct rtx_def * | |
1073 | function_arg (cum, mode, type, named) | |
1074 | CUMULATIVE_ARGS *cum; | |
1075 | enum machine_mode mode; | |
1076 | tree type; | |
1077 | int named; | |
1078 | { | |
b6c9286a MM |
1079 | int align = ((cum->words & 1) != 0 && function_arg_boundary (mode, type) == 64) ? 1 : 0; |
1080 | int align_words = cum->words + align; | |
1081 | ||
4697a36c MM |
1082 | if (TARGET_DEBUG_ARG) |
1083 | fprintf (stderr, | |
b6c9286a MM |
1084 | "function_arg: words = %2d, fregno = %2d, nargs = %4d, proto = %d, mode = %4s, named = %d, align = %d\n", |
1085 | cum->words, cum->fregno, cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode), named, align); | |
4697a36c MM |
1086 | |
1087 | /* Return a marker to indicate whether CR1 needs to set or clear the bit that V.4 | |
1088 | uses to say fp args were passed in registers. Assume that we don't need the | |
1089 | marker for software floating point, or compiler generated library calls. */ | |
1090 | if (mode == VOIDmode) | |
1091 | { | |
7509c759 MM |
1092 | enum rs6000_abi abi = DEFAULT_ABI; |
1093 | ||
1094 | if (abi == ABI_V4 | |
1095 | && TARGET_HARD_FLOAT | |
1096 | && cum->nargs_prototype < 0 | |
4697a36c | 1097 | && type && (cum->prototype || TARGET_NO_PROTOTYPE)) |
7509c759 | 1098 | { |
6a4cee5f MM |
1099 | return GEN_INT (cum->call_cookie |
1100 | | ((cum->fregno == FP_ARG_MIN_REG) | |
1101 | ? CALL_V4_SET_FP_ARGS | |
1102 | : CALL_V4_CLEAR_FP_ARGS)); | |
7509c759 | 1103 | } |
4697a36c | 1104 | |
7509c759 | 1105 | return GEN_INT (cum->call_cookie); |
4697a36c MM |
1106 | } |
1107 | ||
1108 | if (!named) | |
1109 | { | |
7509c759 | 1110 | if (DEFAULT_ABI != ABI_V4) |
4697a36c MM |
1111 | return NULL_RTX; |
1112 | } | |
1113 | ||
1114 | if (type && TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST) | |
1115 | return NULL_RTX; | |
1116 | ||
1117 | if (USE_FP_FOR_ARG_P (*cum, mode, type)) | |
1118 | { | |
1119 | if ((cum->nargs_prototype > 0) | |
7509c759 | 1120 | || (DEFAULT_ABI == ABI_V4) /* V.4 never passes FP values in GP registers */ |
4697a36c MM |
1121 | || !type) |
1122 | return gen_rtx (REG, mode, cum->fregno); | |
1123 | ||
1124 | return gen_rtx (EXPR_LIST, VOIDmode, | |
b6c9286a MM |
1125 | ((align_words < GP_ARG_NUM_REG) |
1126 | ? gen_rtx (REG, mode, GP_ARG_MIN_REG + align_words) | |
4697a36c MM |
1127 | : NULL_RTX), |
1128 | gen_rtx (REG, mode, cum->fregno)); | |
1129 | } | |
1130 | ||
4697a36c | 1131 | /* Long longs won't be split between register and stack */ |
7509c759 | 1132 | else if (DEFAULT_ABI == ABI_V4 && |
b6c9286a | 1133 | align_words + RS6000_ARG_SIZE (mode, type, named) > GP_ARG_NUM_REG) |
4697a36c MM |
1134 | { |
1135 | return NULL_RTX; | |
1136 | } | |
4697a36c | 1137 | |
b6c9286a MM |
1138 | else if (align_words < GP_ARG_NUM_REG) |
1139 | return gen_rtx (REG, mode, GP_ARG_MIN_REG + align_words); | |
4697a36c MM |
1140 | |
1141 | return NULL_RTX; | |
1142 | } | |
1143 | \f | |
1144 | /* For an arg passed partly in registers and partly in memory, | |
1145 | this is the number of registers used. | |
1146 | For args passed entirely in registers or entirely in memory, zero. */ | |
1147 | ||
1148 | int | |
1149 | function_arg_partial_nregs (cum, mode, type, named) | |
1150 | CUMULATIVE_ARGS *cum; | |
1151 | enum machine_mode mode; | |
1152 | tree type; | |
1153 | int named; | |
1154 | { | |
1155 | if (! named) | |
1156 | return 0; | |
1157 | ||
7509c759 | 1158 | if (DEFAULT_ABI == ABI_V4) |
4697a36c | 1159 | return 0; |
4697a36c MM |
1160 | |
1161 | if (USE_FP_FOR_ARG_P (*cum, mode, type)) | |
1162 | { | |
1163 | if (cum->nargs_prototype >= 0) | |
1164 | return 0; | |
1165 | } | |
1166 | ||
1167 | if (cum->words < GP_ARG_NUM_REG | |
1168 | && GP_ARG_NUM_REG < (cum->words + RS6000_ARG_SIZE (mode, type, named))) | |
1169 | { | |
1170 | int ret = GP_ARG_NUM_REG - cum->words; | |
1171 | if (ret && TARGET_DEBUG_ARG) | |
1172 | fprintf (stderr, "function_arg_partial_nregs: %d\n", ret); | |
1173 | ||
1174 | return ret; | |
1175 | } | |
1176 | ||
1177 | return 0; | |
1178 | } | |
1179 | \f | |
1180 | /* A C expression that indicates when an argument must be passed by | |
1181 | reference. If nonzero for an argument, a copy of that argument is | |
1182 | made in memory and a pointer to the argument is passed instead of | |
1183 | the argument itself. The pointer is passed in whatever way is | |
1184 | appropriate for passing a pointer to that type. | |
1185 | ||
1186 | Under V.4, structures and unions are passed by reference. */ | |
1187 | ||
1188 | int | |
1189 | function_arg_pass_by_reference (cum, mode, type, named) | |
1190 | CUMULATIVE_ARGS *cum; | |
1191 | enum machine_mode mode; | |
1192 | tree type; | |
1193 | int named; | |
1194 | { | |
7509c759 | 1195 | if (DEFAULT_ABI == ABI_V4 && type && AGGREGATE_TYPE_P (type)) |
4697a36c MM |
1196 | { |
1197 | if (TARGET_DEBUG_ARG) | |
1198 | fprintf (stderr, "function_arg_pass_by_reference: aggregate\n"); | |
1199 | ||
1200 | return 1; | |
1201 | } | |
4697a36c MM |
1202 | |
1203 | return 0; | |
1204 | } | |
1205 | ||
1206 | \f | |
1207 | /* Perform any needed actions needed for a function that is receiving a | |
1208 | variable number of arguments. | |
1209 | ||
1210 | CUM is as above. | |
1211 | ||
1212 | MODE and TYPE are the mode and type of the current parameter. | |
1213 | ||
1214 | PRETEND_SIZE is a variable that should be set to the amount of stack | |
1215 | that must be pushed by the prolog to pretend that our caller pushed | |
1216 | it. | |
1217 | ||
1218 | Normally, this macro will push all remaining incoming registers on the | |
1219 | stack and set PRETEND_SIZE to the length of the registers pushed. */ | |
1220 | ||
1221 | void | |
1222 | setup_incoming_varargs (cum, mode, type, pretend_size, no_rtl) | |
1223 | CUMULATIVE_ARGS *cum; | |
1224 | enum machine_mode mode; | |
1225 | tree type; | |
1226 | int *pretend_size; | |
1227 | int no_rtl; | |
1228 | ||
1229 | { | |
1230 | rtx save_area = virtual_incoming_args_rtx; | |
1231 | int reg_size = (TARGET_64BIT) ? 8 : 4; | |
1232 | ||
1233 | if (TARGET_DEBUG_ARG) | |
1234 | fprintf (stderr, | |
1235 | "setup_vararg: words = %2d, fregno = %2d, nargs = %4d, proto = %d, mode = %4s, no_rtl= %d\n", | |
1236 | cum->words, cum->fregno, cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode), no_rtl); | |
1237 | ||
7509c759 | 1238 | if (DEFAULT_ABI == ABI_V4 && !no_rtl) |
4697a36c MM |
1239 | { |
1240 | rs6000_sysv_varargs_p = 1; | |
1241 | save_area = plus_constant (frame_pointer_rtx, RS6000_VARARGS_OFFSET); | |
1242 | } | |
4697a36c MM |
1243 | |
1244 | if (cum->words < 8) | |
1245 | { | |
1246 | int first_reg_offset = cum->words; | |
1247 | ||
1248 | if (MUST_PASS_IN_STACK (mode, type)) | |
1249 | first_reg_offset += RS6000_ARG_SIZE (TYPE_MODE (type), type, 1); | |
1250 | ||
1251 | if (first_reg_offset > GP_ARG_NUM_REG) | |
1252 | first_reg_offset = GP_ARG_NUM_REG; | |
1253 | ||
1254 | if (!no_rtl && first_reg_offset != GP_ARG_NUM_REG) | |
1255 | move_block_from_reg | |
1256 | (GP_ARG_MIN_REG + first_reg_offset, | |
1257 | gen_rtx (MEM, BLKmode, | |
1258 | plus_constant (save_area, first_reg_offset * reg_size)), | |
1259 | GP_ARG_NUM_REG - first_reg_offset, | |
1260 | (GP_ARG_NUM_REG - first_reg_offset) * UNITS_PER_WORD); | |
1261 | ||
1262 | *pretend_size = (GP_ARG_NUM_REG - first_reg_offset) * UNITS_PER_WORD; | |
1263 | } | |
1264 | ||
4697a36c | 1265 | /* Save FP registers if needed. */ |
7509c759 | 1266 | if (DEFAULT_ABI == ABI_V4 && TARGET_HARD_FLOAT && !no_rtl) |
4697a36c MM |
1267 | { |
1268 | int fregno = cum->fregno; | |
1269 | int num_fp_reg = FP_ARG_V4_MAX_REG + 1 - fregno; | |
1270 | ||
1271 | if (num_fp_reg >= 0) | |
1272 | { | |
1273 | rtx cr1 = gen_rtx (REG, CCmode, 69); | |
1274 | rtx lab = gen_label_rtx (); | |
1275 | int off = (GP_ARG_NUM_REG * reg_size) + ((fregno - FP_ARG_MIN_REG) * 8); | |
1276 | ||
1277 | emit_jump_insn (gen_rtx (SET, VOIDmode, | |
1278 | pc_rtx, | |
1279 | gen_rtx (IF_THEN_ELSE, VOIDmode, | |
1280 | gen_rtx (NE, VOIDmode, cr1, const0_rtx), | |
1281 | gen_rtx (LABEL_REF, VOIDmode, lab), | |
1282 | pc_rtx))); | |
1283 | ||
1284 | while ( num_fp_reg-- >= 0) | |
1285 | { | |
1286 | emit_move_insn (gen_rtx (MEM, DFmode, plus_constant (save_area, off)), | |
1287 | gen_rtx (REG, DFmode, fregno++)); | |
1288 | off += 8; | |
1289 | } | |
1290 | ||
1291 | emit_label (lab); | |
1292 | } | |
1293 | } | |
4697a36c MM |
1294 | } |
1295 | \f | |
1296 | /* If defined, is a C expression that produces the machine-specific | |
1297 | code for a call to `__builtin_saveregs'. This code will be moved | |
1298 | to the very beginning of the function, before any parameter access | |
1299 | are made. The return value of this function should be an RTX that | |
1300 | contains the value to use as the return of `__builtin_saveregs'. | |
1301 | ||
1302 | The argument ARGS is a `tree_list' containing the arguments that | |
1303 | were passed to `__builtin_saveregs'. | |
1304 | ||
1305 | If this macro is not defined, the compiler will output an ordinary | |
1306 | call to the library function `__builtin_saveregs'. | |
1307 | ||
1308 | On the Power/PowerPC return the address of the area on the stack | |
1309 | used to hold arguments. Under AIX, this includes the 8 word register | |
1310 | save area. Under V.4 this does not. */ | |
1311 | ||
1312 | struct rtx_def * | |
1313 | expand_builtin_saveregs (args) | |
1314 | tree args; | |
1315 | { | |
1316 | return virtual_incoming_args_rtx; | |
1317 | } | |
1318 | ||
7e69e155 | 1319 | \f |
5b5040b9 RK |
1320 | /* Allocate a stack temp. Only allocate one stack temp per type for a |
1321 | function. */ | |
1322 | ||
1323 | struct rtx_def * | |
1324 | rs6000_stack_temp (mode, size) | |
1325 | enum machine_mode mode; | |
1326 | int size; | |
1327 | { | |
1328 | rtx temp = stack_temps[ (int)mode ]; | |
1329 | rtx addr; | |
1330 | ||
1331 | if (temp == NULL_RTX) | |
1332 | { | |
1333 | temp = assign_stack_local (mode, size, 0); | |
1334 | addr = XEXP (temp, 0); | |
1335 | ||
1336 | if ((size > 4 && !offsettable_address_p (0, mode, addr)) | |
1337 | || (size <= 4 && !memory_address_p (mode, addr))) | |
1338 | { | |
1339 | XEXP (temp, 0) = copy_addr_to_reg (addr); | |
1340 | } | |
1341 | ||
1342 | stack_temps[ (int)mode ] = temp; | |
1343 | } | |
1344 | ||
1345 | return temp; | |
1346 | } | |
1347 | ||
1348 | \f | |
1349 | /* Generate a memory reference for expand_block_move, copying volatile, | |
1350 | and other bits from an original memory reference. */ | |
1351 | ||
1352 | static rtx | |
1353 | expand_block_move_mem (mode, addr, orig_mem) | |
1354 | enum machine_mode mode; | |
1355 | rtx addr; | |
1356 | rtx orig_mem; | |
1357 | { | |
1358 | rtx mem = gen_rtx (MEM, mode, addr); | |
b6c9286a MM |
1359 | |
1360 | RTX_UNCHANGING_P (mem) = RTX_UNCHANGING_P (orig_mem); | |
5b5040b9 RK |
1361 | MEM_VOLATILE_P (mem) = MEM_VOLATILE_P (orig_mem); |
1362 | MEM_IN_STRUCT_P (mem) = MEM_IN_STRUCT_P (orig_mem); | |
b6c9286a MM |
1363 | #ifdef MEM_UNALIGNED_P |
1364 | MEM_UNALIGNED_P (mem) = MEM_UNALIGNED_P (orig_mem); | |
1365 | #endif | |
5b5040b9 RK |
1366 | return mem; |
1367 | } | |
1368 | ||
7e69e155 MM |
1369 | /* Expand a block move operation, and return 1 if successful. Return 0 |
1370 | if we should let the compiler generate normal code. | |
1371 | ||
1372 | operands[0] is the destination | |
1373 | operands[1] is the source | |
1374 | operands[2] is the length | |
1375 | operands[3] is the alignment */ | |
1376 | ||
3933e0e1 MM |
1377 | #define MAX_MOVE_REG 4 |
1378 | ||
7e69e155 MM |
1379 | int |
1380 | expand_block_move (operands) | |
1381 | rtx operands[]; | |
1382 | { | |
b6c9286a MM |
1383 | rtx orig_dest = operands[0]; |
1384 | rtx orig_src = operands[1]; | |
7e69e155 | 1385 | rtx bytes_rtx = operands[2]; |
7e69e155 | 1386 | rtx align_rtx = operands[3]; |
3933e0e1 | 1387 | int constp = (GET_CODE (bytes_rtx) == CONST_INT); |
7e69e155 | 1388 | int align = XINT (align_rtx, 0); |
3933e0e1 MM |
1389 | int bytes; |
1390 | int offset; | |
1391 | int num_reg; | |
1392 | int i; | |
7e69e155 MM |
1393 | rtx src_reg; |
1394 | rtx dest_reg; | |
3933e0e1 MM |
1395 | rtx src_addr; |
1396 | rtx dest_addr; | |
7e69e155 | 1397 | rtx tmp_reg; |
3933e0e1 | 1398 | rtx stores[MAX_MOVE_REG]; |
7e69e155 MM |
1399 | int move_bytes; |
1400 | ||
3933e0e1 MM |
1401 | /* If this is not a fixed size move, just call memcpy */ |
1402 | if (!constp) | |
1403 | return 0; | |
1404 | ||
7e69e155 | 1405 | /* Anything to move? */ |
3933e0e1 MM |
1406 | bytes = INTVAL (bytes_rtx); |
1407 | if (bytes <= 0) | |
7e69e155 MM |
1408 | return 1; |
1409 | ||
3933e0e1 MM |
1410 | /* Don't support real large moves. If string instructions are not used, |
1411 | then don't generate more than 8 loads. */ | |
1412 | if (TARGET_STRING) | |
1413 | { | |
1cab3be1 | 1414 | if (bytes > 4*8) |
3933e0e1 MM |
1415 | return 0; |
1416 | } | |
1417 | else if (!STRICT_ALIGNMENT) | |
1418 | { | |
1419 | if (bytes > 4*8) | |
1420 | return 0; | |
1421 | } | |
1422 | else if (bytes > 8*align) | |
7e69e155 MM |
1423 | return 0; |
1424 | ||
1425 | /* Move the address into scratch registers. */ | |
b6c9286a MM |
1426 | dest_reg = copy_addr_to_reg (XEXP (orig_dest, 0)); |
1427 | src_reg = copy_addr_to_reg (XEXP (orig_src, 0)); | |
7e69e155 | 1428 | |
3933e0e1 | 1429 | if (TARGET_STRING) /* string instructions are available */ |
7e69e155 | 1430 | { |
3933e0e1 | 1431 | for ( ; bytes > 0; bytes -= move_bytes) |
7e69e155 | 1432 | { |
3933e0e1 MM |
1433 | if (bytes > 24 /* move up to 32 bytes at a time */ |
1434 | && !fixed_regs[5] | |
1435 | && !fixed_regs[6] | |
1436 | && !fixed_regs[7] | |
1437 | && !fixed_regs[8] | |
1438 | && !fixed_regs[9] | |
1439 | && !fixed_regs[10] | |
1440 | && !fixed_regs[11] | |
1441 | && !fixed_regs[12]) | |
1442 | { | |
1443 | move_bytes = (bytes > 32) ? 32 : bytes; | |
b6c9286a MM |
1444 | emit_insn (gen_movstrsi_8reg (expand_block_move_mem (BLKmode, dest_reg, orig_dest), |
1445 | expand_block_move_mem (BLKmode, src_reg, orig_src), | |
3933e0e1 | 1446 | GEN_INT ((move_bytes == 32) ? 0 : move_bytes), |
4c64a852 | 1447 | align_rtx)); |
3933e0e1 MM |
1448 | } |
1449 | else if (bytes > 16 /* move up to 24 bytes at a time */ | |
1450 | && !fixed_regs[7] | |
1451 | && !fixed_regs[8] | |
1452 | && !fixed_regs[9] | |
1453 | && !fixed_regs[10] | |
1454 | && !fixed_regs[11] | |
1455 | && !fixed_regs[12]) | |
1456 | { | |
1457 | move_bytes = (bytes > 24) ? 24 : bytes; | |
b6c9286a MM |
1458 | emit_insn (gen_movstrsi_6reg (expand_block_move_mem (BLKmode, dest_reg, orig_dest), |
1459 | expand_block_move_mem (BLKmode, src_reg, orig_src), | |
3933e0e1 | 1460 | GEN_INT (move_bytes), |
4c64a852 | 1461 | align_rtx)); |
3933e0e1 MM |
1462 | } |
1463 | else if (bytes > 8 /* move up to 16 bytes at a time */ | |
1464 | && !fixed_regs[9] | |
1465 | && !fixed_regs[10] | |
1466 | && !fixed_regs[11] | |
1467 | && !fixed_regs[12]) | |
1468 | { | |
1469 | move_bytes = (bytes > 16) ? 16 : bytes; | |
b6c9286a MM |
1470 | emit_insn (gen_movstrsi_4reg (expand_block_move_mem (BLKmode, dest_reg, orig_dest), |
1471 | expand_block_move_mem (BLKmode, src_reg, orig_src), | |
3933e0e1 | 1472 | GEN_INT (move_bytes), |
4c64a852 | 1473 | align_rtx)); |
3933e0e1 | 1474 | } |
d679bebf | 1475 | else if (bytes > 4 && !TARGET_64BIT) |
3933e0e1 MM |
1476 | { /* move up to 8 bytes at a time */ |
1477 | move_bytes = (bytes > 8) ? 8 : bytes; | |
b6c9286a MM |
1478 | emit_insn (gen_movstrsi_2reg (expand_block_move_mem (BLKmode, dest_reg, orig_dest), |
1479 | expand_block_move_mem (BLKmode, src_reg, orig_src), | |
3933e0e1 | 1480 | GEN_INT (move_bytes), |
4c64a852 | 1481 | align_rtx)); |
3933e0e1 MM |
1482 | } |
1483 | else if (bytes >= 4 && (align >= 4 || !STRICT_ALIGNMENT)) | |
1484 | { /* move 4 bytes */ | |
1485 | move_bytes = 4; | |
1486 | tmp_reg = gen_reg_rtx (SImode); | |
b6c9286a MM |
1487 | emit_move_insn (tmp_reg, expand_block_move_mem (SImode, src_reg, orig_src)); |
1488 | emit_move_insn (expand_block_move_mem (SImode, dest_reg, orig_dest), tmp_reg); | |
3933e0e1 MM |
1489 | } |
1490 | else if (bytes == 2 && (align >= 2 || !STRICT_ALIGNMENT)) | |
1491 | { /* move 2 bytes */ | |
1492 | move_bytes = 2; | |
1493 | tmp_reg = gen_reg_rtx (HImode); | |
b6c9286a MM |
1494 | emit_move_insn (tmp_reg, expand_block_move_mem (HImode, src_reg, orig_src)); |
1495 | emit_move_insn (expand_block_move_mem (HImode, dest_reg, orig_dest), tmp_reg); | |
3933e0e1 MM |
1496 | } |
1497 | else if (bytes == 1) /* move 1 byte */ | |
1498 | { | |
1499 | move_bytes = 1; | |
1500 | tmp_reg = gen_reg_rtx (QImode); | |
b6c9286a MM |
1501 | emit_move_insn (tmp_reg, expand_block_move_mem (QImode, src_reg, orig_src)); |
1502 | emit_move_insn (expand_block_move_mem (QImode, dest_reg, orig_dest), tmp_reg); | |
3933e0e1 MM |
1503 | } |
1504 | else | |
1505 | { /* move up to 4 bytes at a time */ | |
1506 | move_bytes = (bytes > 4) ? 4 : bytes; | |
b6c9286a MM |
1507 | emit_insn (gen_movstrsi_1reg (expand_block_move_mem (BLKmode, dest_reg, orig_dest), |
1508 | expand_block_move_mem (BLKmode, src_reg, orig_src), | |
3933e0e1 | 1509 | GEN_INT (move_bytes), |
4c64a852 | 1510 | align_rtx)); |
3933e0e1 | 1511 | } |
4c64a852 | 1512 | |
015892ee RK |
1513 | if (bytes > move_bytes) |
1514 | { | |
1515 | emit_insn (gen_addsi3 (src_reg, src_reg, GEN_INT (move_bytes))); | |
1516 | emit_insn (gen_addsi3 (dest_reg, dest_reg, GEN_INT (move_bytes))); | |
1517 | } | |
4c64a852 | 1518 | } |
3933e0e1 MM |
1519 | } |
1520 | ||
1521 | else /* string instructions not available */ | |
1522 | { | |
1523 | num_reg = offset = 0; | |
1524 | for ( ; bytes > 0; (bytes -= move_bytes), (offset += move_bytes)) | |
7e69e155 | 1525 | { |
3933e0e1 MM |
1526 | /* Calculate the correct offset for src/dest */ |
1527 | if (offset == 0) | |
7e69e155 | 1528 | { |
3933e0e1 MM |
1529 | src_addr = src_reg; |
1530 | dest_addr = dest_reg; | |
1531 | } | |
1532 | else | |
1533 | { | |
1534 | src_addr = gen_rtx (PLUS, Pmode, src_reg, GEN_INT (offset)); | |
1535 | dest_addr = gen_rtx (PLUS, Pmode, dest_reg, GEN_INT (offset)); | |
1536 | } | |
1537 | ||
1538 | /* Generate the appropriate load and store, saving the stores for later */ | |
b6c9286a MM |
1539 | if (bytes >= 8 && TARGET_64BIT && (align >= 8 || !STRICT_ALIGNMENT)) |
1540 | { | |
1541 | move_bytes = 8; | |
1542 | tmp_reg = gen_reg_rtx (DImode); | |
1543 | emit_insn (gen_movdi (tmp_reg, expand_block_move_mem (DImode, src_addr, orig_src))); | |
1544 | stores[ num_reg++ ] = gen_movdi (expand_block_move_mem (DImode, dest_addr, orig_dest), tmp_reg); | |
1545 | } | |
1546 | else if (bytes >= 4 && (align >= 4 || !STRICT_ALIGNMENT)) | |
3933e0e1 MM |
1547 | { |
1548 | move_bytes = 4; | |
1549 | tmp_reg = gen_reg_rtx (SImode); | |
b6c9286a MM |
1550 | emit_insn (gen_movsi (tmp_reg, expand_block_move_mem (SImode, src_addr, orig_src))); |
1551 | stores[ num_reg++ ] = gen_movsi (expand_block_move_mem (SImode, dest_addr, orig_dest), tmp_reg); | |
3933e0e1 MM |
1552 | } |
1553 | else if (bytes >= 2 && (align >= 2 || !STRICT_ALIGNMENT)) | |
1554 | { | |
1555 | move_bytes = 2; | |
1556 | tmp_reg = gen_reg_rtx (HImode); | |
b6c9286a MM |
1557 | emit_insn (gen_movsi (tmp_reg, expand_block_move_mem (HImode, src_addr, orig_src))); |
1558 | stores[ num_reg++ ] = gen_movhi (expand_block_move_mem (HImode, dest_addr, orig_dest), tmp_reg); | |
3933e0e1 MM |
1559 | } |
1560 | else | |
1561 | { | |
1562 | move_bytes = 1; | |
1563 | tmp_reg = gen_reg_rtx (QImode); | |
b6c9286a MM |
1564 | emit_insn (gen_movsi (tmp_reg, expand_block_move_mem (QImode, src_addr, orig_src))); |
1565 | stores[ num_reg++ ] = gen_movqi (expand_block_move_mem (QImode, dest_addr, orig_dest), tmp_reg); | |
3933e0e1 MM |
1566 | } |
1567 | ||
1568 | if (num_reg >= MAX_MOVE_REG) | |
1569 | { | |
1570 | for (i = 0; i < num_reg; i++) | |
1571 | emit_insn (stores[i]); | |
1572 | num_reg = 0; | |
7e69e155 MM |
1573 | } |
1574 | } | |
3933e0e1 | 1575 | |
b6c9286a MM |
1576 | for (i = 0; i < num_reg; i++) |
1577 | emit_insn (stores[i]); | |
7e69e155 MM |
1578 | } |
1579 | ||
1580 | return 1; | |
1581 | } | |
1582 | ||
9878760c RK |
1583 | \f |
1584 | /* Return 1 if OP is a load multiple operation. It is known to be a | |
1585 | PARALLEL and the first section will be tested. */ | |
1586 | ||
1587 | int | |
1588 | load_multiple_operation (op, mode) | |
1589 | rtx op; | |
1590 | enum machine_mode mode; | |
1591 | { | |
1592 | int count = XVECLEN (op, 0); | |
1593 | int dest_regno; | |
1594 | rtx src_addr; | |
1595 | int i; | |
1596 | ||
1597 | /* Perform a quick check so we don't blow up below. */ | |
1598 | if (count <= 1 | |
1599 | || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
1600 | || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG | |
1601 | || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM) | |
1602 | return 0; | |
1603 | ||
1604 | dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0))); | |
1605 | src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0); | |
1606 | ||
1607 | for (i = 1; i < count; i++) | |
1608 | { | |
1609 | rtx elt = XVECEXP (op, 0, i); | |
1610 | ||
1611 | if (GET_CODE (elt) != SET | |
1612 | || GET_CODE (SET_DEST (elt)) != REG | |
1613 | || GET_MODE (SET_DEST (elt)) != SImode | |
1614 | || REGNO (SET_DEST (elt)) != dest_regno + i | |
1615 | || GET_CODE (SET_SRC (elt)) != MEM | |
1616 | || GET_MODE (SET_SRC (elt)) != SImode | |
1617 | || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS | |
1618 | || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr) | |
1619 | || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT | |
1620 | || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != i * 4) | |
1621 | return 0; | |
1622 | } | |
1623 | ||
1624 | return 1; | |
1625 | } | |
1626 | ||
1627 | /* Similar, but tests for store multiple. Here, the second vector element | |
1628 | is a CLOBBER. It will be tested later. */ | |
1629 | ||
1630 | int | |
1631 | store_multiple_operation (op, mode) | |
1632 | rtx op; | |
1633 | enum machine_mode mode; | |
1634 | { | |
1635 | int count = XVECLEN (op, 0) - 1; | |
1636 | int src_regno; | |
1637 | rtx dest_addr; | |
1638 | int i; | |
1639 | ||
1640 | /* Perform a quick check so we don't blow up below. */ | |
1641 | if (count <= 1 | |
1642 | || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
1643 | || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM | |
1644 | || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG) | |
1645 | return 0; | |
1646 | ||
1647 | src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0))); | |
1648 | dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0); | |
1649 | ||
1650 | for (i = 1; i < count; i++) | |
1651 | { | |
1652 | rtx elt = XVECEXP (op, 0, i + 1); | |
1653 | ||
1654 | if (GET_CODE (elt) != SET | |
1655 | || GET_CODE (SET_SRC (elt)) != REG | |
1656 | || GET_MODE (SET_SRC (elt)) != SImode | |
1657 | || REGNO (SET_SRC (elt)) != src_regno + i | |
1658 | || GET_CODE (SET_DEST (elt)) != MEM | |
1659 | || GET_MODE (SET_DEST (elt)) != SImode | |
1660 | || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS | |
1661 | || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr) | |
1662 | || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT | |
1663 | || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != i * 4) | |
1664 | return 0; | |
1665 | } | |
1666 | ||
1667 | return 1; | |
1668 | } | |
1669 | \f | |
1670 | /* Return 1 if OP is a comparison operation that is valid for a branch insn. | |
1671 | We only check the opcode against the mode of the CC value here. */ | |
1672 | ||
1673 | int | |
1674 | branch_comparison_operator (op, mode) | |
1675 | register rtx op; | |
1676 | enum machine_mode mode; | |
1677 | { | |
1678 | enum rtx_code code = GET_CODE (op); | |
1679 | enum machine_mode cc_mode; | |
1680 | ||
1681 | if (GET_RTX_CLASS (code) != '<') | |
1682 | return 0; | |
1683 | ||
1684 | cc_mode = GET_MODE (XEXP (op, 0)); | |
1685 | if (GET_MODE_CLASS (cc_mode) != MODE_CC) | |
1686 | return 0; | |
1687 | ||
1688 | if ((code == GT || code == LT || code == GE || code == LE) | |
1689 | && cc_mode == CCUNSmode) | |
1690 | return 0; | |
1691 | ||
1692 | if ((code == GTU || code == LTU || code == GEU || code == LEU) | |
1693 | && (cc_mode != CCUNSmode)) | |
1694 | return 0; | |
1695 | ||
1696 | return 1; | |
1697 | } | |
1698 | ||
1699 | /* Return 1 if OP is a comparison operation that is valid for an scc insn. | |
1700 | We check the opcode against the mode of the CC value and disallow EQ or | |
1701 | NE comparisons for integers. */ | |
1702 | ||
1703 | int | |
1704 | scc_comparison_operator (op, mode) | |
1705 | register rtx op; | |
1706 | enum machine_mode mode; | |
1707 | { | |
1708 | enum rtx_code code = GET_CODE (op); | |
1709 | enum machine_mode cc_mode; | |
1710 | ||
1711 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
1712 | return 0; | |
1713 | ||
1714 | if (GET_RTX_CLASS (code) != '<') | |
1715 | return 0; | |
1716 | ||
1717 | cc_mode = GET_MODE (XEXP (op, 0)); | |
1718 | if (GET_MODE_CLASS (cc_mode) != MODE_CC) | |
1719 | return 0; | |
1720 | ||
1721 | if (code == NE && cc_mode != CCFPmode) | |
1722 | return 0; | |
1723 | ||
1724 | if ((code == GT || code == LT || code == GE || code == LE) | |
1725 | && cc_mode == CCUNSmode) | |
1726 | return 0; | |
1727 | ||
1728 | if ((code == GTU || code == LTU || code == GEU || code == LEU) | |
1729 | && (cc_mode != CCUNSmode)) | |
1730 | return 0; | |
1731 | ||
c5defebb RK |
1732 | if (cc_mode == CCEQmode && code != EQ && code != NE) |
1733 | return 0; | |
1734 | ||
9878760c RK |
1735 | return 1; |
1736 | } | |
1737 | \f | |
1738 | /* Return 1 if ANDOP is a mask that has no bits on that are not in the | |
1739 | mask required to convert the result of a rotate insn into a shift | |
1740 | left insn of SHIFTOP bits. Both are known to be CONST_INT. */ | |
1741 | ||
1742 | int | |
1743 | includes_lshift_p (shiftop, andop) | |
1744 | register rtx shiftop; | |
1745 | register rtx andop; | |
1746 | { | |
1747 | int shift_mask = (~0 << INTVAL (shiftop)); | |
1748 | ||
1749 | return (INTVAL (andop) & ~shift_mask) == 0; | |
1750 | } | |
1751 | ||
1752 | /* Similar, but for right shift. */ | |
1753 | ||
1754 | int | |
1755 | includes_rshift_p (shiftop, andop) | |
1756 | register rtx shiftop; | |
1757 | register rtx andop; | |
1758 | { | |
1759 | unsigned shift_mask = ~0; | |
1760 | ||
1761 | shift_mask >>= INTVAL (shiftop); | |
1762 | ||
1763 | return (INTVAL (andop) & ~ shift_mask) == 0; | |
1764 | } | |
35068b43 RK |
1765 | |
1766 | /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates | |
1767 | for lfq and stfq insns. | |
1768 | ||
1769 | Note reg1 and reg2 *must* be hard registers. To be sure we will | |
1770 | abort if we are passed pseudo registers. */ | |
1771 | ||
1772 | int | |
1773 | registers_ok_for_quad_peep (reg1, reg2) | |
1774 | rtx reg1, reg2; | |
1775 | { | |
1776 | /* We might have been passed a SUBREG. */ | |
1777 | if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG) | |
1778 | return 0; | |
1779 | ||
1780 | return (REGNO (reg1) == REGNO (reg2) - 1); | |
1781 | } | |
1782 | ||
1783 | /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn. addr1 and | |
1784 | addr2 must be in consecutive memory locations (addr2 == addr1 + 8). */ | |
1785 | ||
1786 | int | |
1787 | addrs_ok_for_quad_peep (addr1, addr2) | |
1788 | register rtx addr1; | |
1789 | register rtx addr2; | |
1790 | { | |
1791 | int reg1; | |
1792 | int offset1; | |
1793 | ||
1794 | /* Extract an offset (if used) from the first addr. */ | |
1795 | if (GET_CODE (addr1) == PLUS) | |
1796 | { | |
1797 | /* If not a REG, return zero. */ | |
1798 | if (GET_CODE (XEXP (addr1, 0)) != REG) | |
1799 | return 0; | |
1800 | else | |
1801 | { | |
1802 | reg1 = REGNO (XEXP (addr1, 0)); | |
1803 | /* The offset must be constant! */ | |
1804 | if (GET_CODE (XEXP (addr1, 1)) != CONST_INT) | |
1805 | return 0; | |
1806 | offset1 = INTVAL (XEXP (addr1, 1)); | |
1807 | } | |
1808 | } | |
1809 | else if (GET_CODE (addr1) != REG) | |
1810 | return 0; | |
1811 | else | |
1812 | { | |
1813 | reg1 = REGNO (addr1); | |
1814 | /* This was a simple (mem (reg)) expression. Offset is 0. */ | |
1815 | offset1 = 0; | |
1816 | } | |
1817 | ||
1818 | /* Make sure the second address is a (mem (plus (reg) (const_int). */ | |
1819 | if (GET_CODE (addr2) != PLUS) | |
1820 | return 0; | |
1821 | ||
1822 | if (GET_CODE (XEXP (addr2, 0)) != REG | |
1823 | || GET_CODE (XEXP (addr2, 1)) != CONST_INT) | |
1824 | return 0; | |
1825 | ||
1826 | if (reg1 != REGNO (XEXP (addr2, 0))) | |
1827 | return 0; | |
1828 | ||
1829 | /* The offset for the second addr must be 8 more than the first addr. */ | |
1830 | if (INTVAL (XEXP (addr2, 1)) != offset1 + 8) | |
1831 | return 0; | |
1832 | ||
1833 | /* All the tests passed. addr1 and addr2 are valid for lfq or stfq | |
1834 | instructions. */ | |
1835 | return 1; | |
1836 | } | |
9878760c RK |
1837 | \f |
1838 | /* Return the register class of a scratch register needed to copy IN into | |
1839 | or out of a register in CLASS in MODE. If it can be done directly, | |
1840 | NO_REGS is returned. */ | |
1841 | ||
1842 | enum reg_class | |
1843 | secondary_reload_class (class, mode, in) | |
1844 | enum reg_class class; | |
1845 | enum machine_mode mode; | |
1846 | rtx in; | |
1847 | { | |
1848 | int regno = true_regnum (in); | |
1849 | ||
1850 | if (regno >= FIRST_PSEUDO_REGISTER) | |
1851 | regno = -1; | |
1852 | ||
1853 | /* We can place anything into GENERAL_REGS and can put GENERAL_REGS | |
1854 | into anything. */ | |
1855 | if (class == GENERAL_REGS || class == BASE_REGS | |
1856 | || (regno >= 0 && INT_REGNO_P (regno))) | |
1857 | return NO_REGS; | |
1858 | ||
1859 | /* Constants, memory, and FP registers can go into FP registers. */ | |
1860 | if ((regno == -1 || FP_REGNO_P (regno)) | |
1861 | && (class == FLOAT_REGS || class == NON_SPECIAL_REGS)) | |
1862 | return NO_REGS; | |
1863 | ||
1864 | /* We can copy among the CR registers. */ | |
1865 | if ((class == CR_REGS || class == CR0_REGS) | |
1866 | && regno >= 0 && CR_REGNO_P (regno)) | |
1867 | return NO_REGS; | |
1868 | ||
1869 | /* Otherwise, we need GENERAL_REGS. */ | |
1870 | return GENERAL_REGS; | |
1871 | } | |
1872 | \f | |
1873 | /* Given a comparison operation, return the bit number in CCR to test. We | |
1874 | know this is a valid comparison. | |
1875 | ||
1876 | SCC_P is 1 if this is for an scc. That means that %D will have been | |
1877 | used instead of %C, so the bits will be in different places. | |
1878 | ||
b4ac57ab | 1879 | Return -1 if OP isn't a valid comparison for some reason. */ |
9878760c RK |
1880 | |
1881 | int | |
1882 | ccr_bit (op, scc_p) | |
1883 | register rtx op; | |
1884 | int scc_p; | |
1885 | { | |
1886 | enum rtx_code code = GET_CODE (op); | |
1887 | enum machine_mode cc_mode; | |
1888 | int cc_regnum; | |
1889 | int base_bit; | |
1890 | ||
1891 | if (GET_RTX_CLASS (code) != '<') | |
1892 | return -1; | |
1893 | ||
1894 | cc_mode = GET_MODE (XEXP (op, 0)); | |
1895 | cc_regnum = REGNO (XEXP (op, 0)); | |
1896 | base_bit = 4 * (cc_regnum - 68); | |
1897 | ||
c5defebb RK |
1898 | /* In CCEQmode cases we have made sure that the result is always in the |
1899 | third bit of the CR field. */ | |
1900 | ||
1901 | if (cc_mode == CCEQmode) | |
1902 | return base_bit + 3; | |
1903 | ||
9878760c RK |
1904 | switch (code) |
1905 | { | |
1906 | case NE: | |
1907 | return scc_p ? base_bit + 3 : base_bit + 2; | |
1908 | case EQ: | |
1909 | return base_bit + 2; | |
1910 | case GT: case GTU: | |
1911 | return base_bit + 1; | |
1912 | case LT: case LTU: | |
1913 | return base_bit; | |
1914 | ||
1915 | case GE: case GEU: | |
1916 | /* If floating-point, we will have done a cror to put the bit in the | |
1917 | unordered position. So test that bit. For integer, this is ! LT | |
1918 | unless this is an scc insn. */ | |
1919 | return cc_mode == CCFPmode || scc_p ? base_bit + 3 : base_bit; | |
1920 | ||
1921 | case LE: case LEU: | |
1922 | return cc_mode == CCFPmode || scc_p ? base_bit + 3 : base_bit + 1; | |
1923 | ||
1924 | default: | |
1925 | abort (); | |
1926 | } | |
1927 | } | |
1928 | \f | |
1929 | /* Print an operand. Recognize special options, documented below. */ | |
1930 | ||
1931 | void | |
1932 | print_operand (file, x, code) | |
1933 | FILE *file; | |
1934 | rtx x; | |
1935 | char code; | |
1936 | { | |
1937 | int i; | |
1938 | int val; | |
1939 | ||
1940 | /* These macros test for integers and extract the low-order bits. */ | |
1941 | #define INT_P(X) \ | |
1942 | ((GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST_DOUBLE) \ | |
1943 | && GET_MODE (X) == VOIDmode) | |
1944 | ||
1945 | #define INT_LOWPART(X) \ | |
1946 | (GET_CODE (X) == CONST_INT ? INTVAL (X) : CONST_DOUBLE_LOW (X)) | |
1947 | ||
1948 | switch (code) | |
1949 | { | |
a8b3aeda | 1950 | case '.': |
a85d226b RK |
1951 | /* Write out an instruction after the call which may be replaced |
1952 | with glue code by the loader. This depends on the AIX version. */ | |
1953 | asm_fprintf (file, RS6000_CALL_GLUE); | |
a8b3aeda RK |
1954 | return; |
1955 | ||
cfaaaf2e RK |
1956 | case '*': |
1957 | /* Write the register number of the TOC register. */ | |
4697a36c | 1958 | fputs (TARGET_MINIMAL_TOC ? reg_names[30] : reg_names[2], file); |
cfaaaf2e RK |
1959 | return; |
1960 | ||
9854d9ed RK |
1961 | case 'A': |
1962 | /* If X is a constant integer whose low-order 5 bits are zero, | |
1963 | write 'l'. Otherwise, write 'r'. This is a kludge to fix a bug | |
76229ac8 | 1964 | in the AIX assembler where "sri" with a zero shift count |
9854d9ed RK |
1965 | write a trash instruction. */ |
1966 | if (GET_CODE (x) == CONST_INT && (INTVAL (x) & 31) == 0) | |
76229ac8 | 1967 | putc ('l', file); |
9854d9ed | 1968 | else |
76229ac8 | 1969 | putc ('r', file); |
9854d9ed RK |
1970 | return; |
1971 | ||
1972 | case 'b': | |
1973 | /* Low-order 16 bits of constant, unsigned. */ | |
cad12a8d | 1974 | if (! INT_P (x)) |
9854d9ed | 1975 | output_operand_lossage ("invalid %%b value"); |
cad12a8d | 1976 | |
9854d9ed | 1977 | fprintf (file, "%d", INT_LOWPART (x) & 0xffff); |
cad12a8d RK |
1978 | return; |
1979 | ||
9854d9ed RK |
1980 | case 'C': |
1981 | /* This is an optional cror needed for LE or GE floating-point | |
1982 | comparisons. Otherwise write nothing. */ | |
1983 | if ((GET_CODE (x) == LE || GET_CODE (x) == GE) | |
1984 | && GET_MODE (XEXP (x, 0)) == CCFPmode) | |
1985 | { | |
1986 | int base_bit = 4 * (REGNO (XEXP (x, 0)) - 68); | |
1987 | ||
1988 | fprintf (file, "cror %d,%d,%d\n\t", base_bit + 3, | |
1989 | base_bit + 2, base_bit + (GET_CODE (x) == GE)); | |
1990 | } | |
1991 | return; | |
1992 | ||
1993 | case 'D': | |
1994 | /* Similar, except that this is for an scc, so we must be able to | |
1995 | encode the test in a single bit that is one. We do the above | |
1996 | for any LE, GE, GEU, or LEU and invert the bit for NE. */ | |
1997 | if (GET_CODE (x) == LE || GET_CODE (x) == GE | |
1998 | || GET_CODE (x) == LEU || GET_CODE (x) == GEU) | |
1999 | { | |
2000 | int base_bit = 4 * (REGNO (XEXP (x, 0)) - 68); | |
2001 | ||
2002 | fprintf (file, "cror %d,%d,%d\n\t", base_bit + 3, | |
2003 | base_bit + 2, | |
2004 | base_bit + (GET_CODE (x) == GE || GET_CODE (x) == GEU)); | |
2005 | } | |
2006 | ||
2007 | else if (GET_CODE (x) == NE) | |
2008 | { | |
2009 | int base_bit = 4 * (REGNO (XEXP (x, 0)) - 68); | |
2010 | ||
2011 | fprintf (file, "crnor %d,%d,%d\n\t", base_bit + 3, | |
2012 | base_bit + 2, base_bit + 2); | |
2013 | } | |
2014 | return; | |
2015 | ||
2016 | case 'E': | |
2017 | /* X is a CR register. Print the number of the third bit of the CR */ | |
2018 | if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x))) | |
2019 | output_operand_lossage ("invalid %%E value"); | |
2020 | ||
2021 | fprintf(file, "%d", 4 * (REGNO (x) - 68) + 3); | |
a85d226b | 2022 | return; |
9854d9ed RK |
2023 | |
2024 | case 'f': | |
2025 | /* X is a CR register. Print the shift count needed to move it | |
2026 | to the high-order four bits. */ | |
2027 | if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x))) | |
2028 | output_operand_lossage ("invalid %%f value"); | |
2029 | else | |
2030 | fprintf (file, "%d", 4 * (REGNO (x) - 68)); | |
2031 | return; | |
2032 | ||
2033 | case 'F': | |
2034 | /* Similar, but print the count for the rotate in the opposite | |
2035 | direction. */ | |
2036 | if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x))) | |
2037 | output_operand_lossage ("invalid %%F value"); | |
2038 | else | |
2039 | fprintf (file, "%d", 32 - 4 * (REGNO (x) - 68)); | |
2040 | return; | |
2041 | ||
2042 | case 'G': | |
2043 | /* X is a constant integer. If it is negative, print "m", | |
2044 | otherwise print "z". This is to make a aze or ame insn. */ | |
2045 | if (GET_CODE (x) != CONST_INT) | |
2046 | output_operand_lossage ("invalid %%G value"); | |
2047 | else if (INTVAL (x) >= 0) | |
76229ac8 | 2048 | putc ('z', file); |
9854d9ed | 2049 | else |
76229ac8 | 2050 | putc ('m', file); |
9854d9ed RK |
2051 | return; |
2052 | ||
9878760c | 2053 | case 'h': |
df3d94ed RK |
2054 | /* If constant, output low-order five bits. Otherwise, |
2055 | write normally. */ | |
9878760c RK |
2056 | if (INT_P (x)) |
2057 | fprintf (file, "%d", INT_LOWPART (x) & 31); | |
2058 | else | |
2059 | print_operand (file, x, 0); | |
2060 | return; | |
2061 | ||
64305719 DE |
2062 | case 'H': |
2063 | /* If constant, output low-order six bits. Otherwise, | |
2064 | write normally. */ | |
2065 | if (INT_P (x)) | |
2066 | fprintf (file, "%d", INT_LOWPART (x) & 63); | |
2067 | else | |
2068 | print_operand (file, x, 0); | |
2069 | return; | |
2070 | ||
9854d9ed RK |
2071 | case 'I': |
2072 | /* Print `i' if this is a constant, else nothing. */ | |
9878760c | 2073 | if (INT_P (x)) |
76229ac8 | 2074 | putc ('i', file); |
9878760c RK |
2075 | return; |
2076 | ||
9854d9ed RK |
2077 | case 'j': |
2078 | /* Write the bit number in CCR for jump. */ | |
2079 | i = ccr_bit (x, 0); | |
2080 | if (i == -1) | |
2081 | output_operand_lossage ("invalid %%j code"); | |
9878760c | 2082 | else |
9854d9ed | 2083 | fprintf (file, "%d", i); |
9878760c RK |
2084 | return; |
2085 | ||
9854d9ed RK |
2086 | case 'J': |
2087 | /* Similar, but add one for shift count in rlinm for scc and pass | |
2088 | scc flag to `ccr_bit'. */ | |
2089 | i = ccr_bit (x, 1); | |
2090 | if (i == -1) | |
2091 | output_operand_lossage ("invalid %%J code"); | |
2092 | else | |
a0466a68 RK |
2093 | /* If we want bit 31, write a shift count of zero, not 32. */ |
2094 | fprintf (file, "%d", i == 31 ? 0 : i + 1); | |
9878760c RK |
2095 | return; |
2096 | ||
9854d9ed RK |
2097 | case 'k': |
2098 | /* X must be a constant. Write the 1's complement of the | |
2099 | constant. */ | |
9878760c | 2100 | if (! INT_P (x)) |
9854d9ed | 2101 | output_operand_lossage ("invalid %%k value"); |
9878760c | 2102 | |
9854d9ed | 2103 | fprintf (file, "%d", ~ INT_LOWPART (x)); |
9878760c RK |
2104 | return; |
2105 | ||
9854d9ed RK |
2106 | case 'L': |
2107 | /* Write second word of DImode or DFmode reference. Works on register | |
2108 | or non-indexed memory only. */ | |
2109 | if (GET_CODE (x) == REG) | |
2110 | fprintf (file, "%d", REGNO (x) + 1); | |
2111 | else if (GET_CODE (x) == MEM) | |
2112 | { | |
2113 | /* Handle possible auto-increment. Since it is pre-increment and | |
2114 | we have already done it, we can just use an offset of four. */ | |
2115 | if (GET_CODE (XEXP (x, 0)) == PRE_INC | |
2116 | || GET_CODE (XEXP (x, 0)) == PRE_DEC) | |
a54d04b7 | 2117 | output_address (plus_constant (XEXP (XEXP (x, 0), 0), 4)); |
9854d9ed | 2118 | else |
a54d04b7 MM |
2119 | output_address (plus_constant (XEXP (x, 0), 4)); |
2120 | if (DEFAULT_ABI == ABI_V4 && small_data_operand (x, GET_MODE (x))) | |
2121 | fprintf (file, "@sda21(%s)", reg_names[0]); | |
9854d9ed | 2122 | } |
9878760c | 2123 | return; |
9854d9ed | 2124 | |
9878760c RK |
2125 | case 'm': |
2126 | /* MB value for a mask operand. */ | |
2127 | if (! mask_operand (x, VOIDmode)) | |
2128 | output_operand_lossage ("invalid %%m value"); | |
2129 | ||
2130 | val = INT_LOWPART (x); | |
2131 | ||
2132 | /* If the high bit is set and the low bit is not, the value is zero. | |
2133 | If the high bit is zero, the value is the first 1 bit we find from | |
2134 | the left. */ | |
2135 | if (val < 0 && (val & 1) == 0) | |
2136 | { | |
19d2d16f | 2137 | putc ('0', file); |
9878760c RK |
2138 | return; |
2139 | } | |
2140 | else if (val >= 0) | |
2141 | { | |
2142 | for (i = 1; i < 32; i++) | |
2143 | if ((val <<= 1) < 0) | |
2144 | break; | |
2145 | fprintf (file, "%d", i); | |
2146 | return; | |
2147 | } | |
2148 | ||
2149 | /* Otherwise, look for the first 0 bit from the right. The result is its | |
2150 | number plus 1. We know the low-order bit is one. */ | |
2151 | for (i = 0; i < 32; i++) | |
2152 | if (((val >>= 1) & 1) == 0) | |
2153 | break; | |
2154 | ||
2155 | /* If we ended in ...01, I would be 0. The correct value is 31, so | |
2156 | we want 31 - i. */ | |
2157 | fprintf (file, "%d", 31 - i); | |
2158 | return; | |
2159 | ||
2160 | case 'M': | |
2161 | /* ME value for a mask operand. */ | |
2162 | if (! mask_operand (x, VOIDmode)) | |
2163 | output_operand_lossage ("invalid %%m value"); | |
2164 | ||
2165 | val = INT_LOWPART (x); | |
2166 | ||
2167 | /* If the low bit is set and the high bit is not, the value is 31. | |
2168 | If the low bit is zero, the value is the first 1 bit we find from | |
2169 | the right. */ | |
2170 | if ((val & 1) && val >= 0) | |
2171 | { | |
76229ac8 | 2172 | fputs ("31", file); |
9878760c RK |
2173 | return; |
2174 | } | |
2175 | else if ((val & 1) == 0) | |
2176 | { | |
2177 | for (i = 0; i < 32; i++) | |
2178 | if ((val >>= 1) & 1) | |
2179 | break; | |
2180 | ||
2181 | /* If we had ....10, I would be 0. The result should be | |
2182 | 30, so we need 30 - i. */ | |
2183 | fprintf (file, "%d", 30 - i); | |
2184 | return; | |
2185 | } | |
2186 | ||
2187 | /* Otherwise, look for the first 0 bit from the left. The result is its | |
2188 | number minus 1. We know the high-order bit is one. */ | |
2189 | for (i = 0; i < 32; i++) | |
2190 | if ((val <<= 1) >= 0) | |
2191 | break; | |
2192 | ||
2193 | fprintf (file, "%d", i); | |
2194 | return; | |
2195 | ||
9878760c RK |
2196 | case 'N': |
2197 | /* Write the number of elements in the vector times 4. */ | |
2198 | if (GET_CODE (x) != PARALLEL) | |
2199 | output_operand_lossage ("invalid %%N value"); | |
2200 | ||
2201 | fprintf (file, "%d", XVECLEN (x, 0) * 4); | |
2202 | return; | |
2203 | ||
2204 | case 'O': | |
2205 | /* Similar, but subtract 1 first. */ | |
2206 | if (GET_CODE (x) != PARALLEL) | |
2207 | output_operand_lossage ("invalid %%N value"); | |
2208 | ||
2209 | fprintf (file, "%d", (XVECLEN (x, 0) - 1) * 4); | |
2210 | return; | |
2211 | ||
9854d9ed RK |
2212 | case 'p': |
2213 | /* X is a CONST_INT that is a power of two. Output the logarithm. */ | |
2214 | if (! INT_P (x) | |
2215 | || (i = exact_log2 (INT_LOWPART (x))) < 0) | |
2216 | output_operand_lossage ("invalid %%p value"); | |
2217 | ||
2218 | fprintf (file, "%d", i); | |
2219 | return; | |
2220 | ||
9878760c RK |
2221 | case 'P': |
2222 | /* The operand must be an indirect memory reference. The result | |
2223 | is the register number. */ | |
2224 | if (GET_CODE (x) != MEM || GET_CODE (XEXP (x, 0)) != REG | |
2225 | || REGNO (XEXP (x, 0)) >= 32) | |
2226 | output_operand_lossage ("invalid %%P value"); | |
2227 | ||
2228 | fprintf (file, "%d", REGNO (XEXP (x, 0))); | |
2229 | return; | |
2230 | ||
9854d9ed RK |
2231 | case 'R': |
2232 | /* X is a CR register. Print the mask for `mtcrf'. */ | |
2233 | if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x))) | |
2234 | output_operand_lossage ("invalid %%R value"); | |
2235 | else | |
2236 | fprintf (file, "%d", 128 >> (REGNO (x) - 68)); | |
9878760c | 2237 | return; |
9854d9ed RK |
2238 | |
2239 | case 's': | |
2240 | /* Low 5 bits of 32 - value */ | |
2241 | if (! INT_P (x)) | |
2242 | output_operand_lossage ("invalid %%s value"); | |
2243 | ||
2244 | fprintf (file, "%d", (32 - INT_LOWPART (x)) & 31); | |
9878760c | 2245 | return; |
9854d9ed | 2246 | |
9878760c RK |
2247 | case 't': |
2248 | /* Write 12 if this jump operation will branch if true, 4 otherwise. | |
2249 | All floating-point operations except NE branch true and integer | |
2250 | EQ, LT, GT, LTU and GTU also branch true. */ | |
2251 | if (GET_RTX_CLASS (GET_CODE (x)) != '<') | |
2252 | output_operand_lossage ("invalid %%t value"); | |
2253 | ||
2254 | else if ((GET_MODE (XEXP (x, 0)) == CCFPmode | |
2255 | && GET_CODE (x) != NE) | |
2256 | || GET_CODE (x) == EQ | |
2257 | || GET_CODE (x) == LT || GET_CODE (x) == GT | |
2258 | || GET_CODE (x) == LTU || GET_CODE (x) == GTU) | |
76229ac8 | 2259 | fputs ("12", file); |
9878760c | 2260 | else |
76229ac8 | 2261 | putc ('4', file); |
9878760c RK |
2262 | return; |
2263 | ||
2264 | case 'T': | |
2265 | /* Opposite of 't': write 4 if this jump operation will branch if true, | |
2266 | 12 otherwise. */ | |
2267 | if (GET_RTX_CLASS (GET_CODE (x)) != '<') | |
2268 | output_operand_lossage ("invalid %%t value"); | |
2269 | ||
2270 | else if ((GET_MODE (XEXP (x, 0)) == CCFPmode | |
2271 | && GET_CODE (x) != NE) | |
2272 | || GET_CODE (x) == EQ | |
2273 | || GET_CODE (x) == LT || GET_CODE (x) == GT | |
2274 | || GET_CODE (x) == LTU || GET_CODE (x) == GTU) | |
76229ac8 | 2275 | putc ('4', file); |
9878760c | 2276 | else |
76229ac8 | 2277 | fputs ("12", file); |
9878760c RK |
2278 | return; |
2279 | ||
9854d9ed RK |
2280 | case 'u': |
2281 | /* High-order 16 bits of constant. */ | |
2282 | if (! INT_P (x)) | |
2283 | output_operand_lossage ("invalid %%u value"); | |
9878760c | 2284 | |
76229ac8 | 2285 | fprintf (file, "0x%x", (INT_LOWPART (x) >> 16) & 0xffff); |
9878760c RK |
2286 | return; |
2287 | ||
9854d9ed RK |
2288 | case 'U': |
2289 | /* Print `u' if this has an auto-increment or auto-decrement. */ | |
2290 | if (GET_CODE (x) == MEM | |
2291 | && (GET_CODE (XEXP (x, 0)) == PRE_INC | |
2292 | || GET_CODE (XEXP (x, 0)) == PRE_DEC)) | |
76229ac8 | 2293 | putc ('u', file); |
9854d9ed | 2294 | return; |
9878760c | 2295 | |
9854d9ed RK |
2296 | case 'w': |
2297 | /* If constant, low-order 16 bits of constant, signed. Otherwise, write | |
2298 | normally. */ | |
2299 | if (INT_P (x)) | |
2300 | fprintf (file, "%d", | |
2301 | (INT_LOWPART (x) & 0xffff) - 2 * (INT_LOWPART (x) & 0x8000)); | |
2302 | else | |
2303 | print_operand (file, x, 0); | |
9878760c RK |
2304 | return; |
2305 | ||
9854d9ed RK |
2306 | case 'W': |
2307 | /* If constant, low-order 16 bits of constant, unsigned. | |
2308 | Otherwise, write normally. */ | |
2309 | if (INT_P (x)) | |
2310 | fprintf (file, "%d", INT_LOWPART (x) & 0xffff); | |
2311 | else | |
2312 | print_operand (file, x, 0); | |
2313 | return; | |
9878760c | 2314 | |
9854d9ed RK |
2315 | case 'X': |
2316 | if (GET_CODE (x) == MEM | |
2317 | && LEGITIMATE_INDEXED_ADDRESS_P (XEXP (x, 0))) | |
76229ac8 | 2318 | putc ('x', file); |
9854d9ed | 2319 | return; |
9878760c | 2320 | |
9854d9ed RK |
2321 | case 'Y': |
2322 | /* Like 'L', for third word of TImode */ | |
2323 | if (GET_CODE (x) == REG) | |
2324 | fprintf (file, "%d", REGNO (x) + 2); | |
2325 | else if (GET_CODE (x) == MEM) | |
9878760c | 2326 | { |
9854d9ed RK |
2327 | if (GET_CODE (XEXP (x, 0)) == PRE_INC |
2328 | || GET_CODE (XEXP (x, 0)) == PRE_DEC) | |
a54d04b7 | 2329 | output_address (plus_constant (XEXP (XEXP (x, 0), 0), 8)); |
9854d9ed | 2330 | else |
a54d04b7 MM |
2331 | output_address (plus_constant (XEXP (x, 0), 8)); |
2332 | if (DEFAULT_ABI == ABI_V4 && small_data_operand (x, GET_MODE (x))) | |
2333 | fprintf (file, "@sda21(%s)", reg_names[0]); | |
9878760c RK |
2334 | } |
2335 | return; | |
9854d9ed | 2336 | |
9878760c | 2337 | case 'z': |
b4ac57ab RS |
2338 | /* X is a SYMBOL_REF. Write out the name preceded by a |
2339 | period and without any trailing data in brackets. Used for function | |
4d30c363 MM |
2340 | names. If we are configured for System V (or the embedded ABI) on |
2341 | the PowerPC, do not emit the period, since those systems do not use | |
2342 | TOCs and the like. */ | |
9878760c RK |
2343 | if (GET_CODE (x) != SYMBOL_REF) |
2344 | abort (); | |
2345 | ||
b6c9286a MM |
2346 | if (XSTR (x, 0)[0] != '.') |
2347 | { | |
2348 | switch (DEFAULT_ABI) | |
2349 | { | |
2350 | default: | |
2351 | abort (); | |
2352 | ||
2353 | case ABI_AIX: | |
2354 | putc ('.', file); | |
2355 | break; | |
2356 | ||
2357 | case ABI_V4: | |
2358 | case ABI_AIX_NODESC: | |
2359 | break; | |
2360 | ||
2361 | case ABI_NT: | |
2362 | fputs ("..", file); | |
2363 | break; | |
2364 | } | |
2365 | } | |
9878760c RK |
2366 | RS6000_OUTPUT_BASENAME (file, XSTR (x, 0)); |
2367 | return; | |
2368 | ||
9854d9ed RK |
2369 | case 'Z': |
2370 | /* Like 'L', for last word of TImode. */ | |
2371 | if (GET_CODE (x) == REG) | |
2372 | fprintf (file, "%d", REGNO (x) + 3); | |
2373 | else if (GET_CODE (x) == MEM) | |
2374 | { | |
2375 | if (GET_CODE (XEXP (x, 0)) == PRE_INC | |
2376 | || GET_CODE (XEXP (x, 0)) == PRE_DEC) | |
a54d04b7 | 2377 | output_address (plus_constant (XEXP (XEXP (x, 0), 0), 12)); |
9854d9ed | 2378 | else |
a54d04b7 MM |
2379 | output_address (plus_constant (XEXP (x, 0), 12)); |
2380 | if (DEFAULT_ABI == ABI_V4 && small_data_operand (x, GET_MODE (x))) | |
2381 | fprintf (file, "@sda21(%s)", reg_names[0]); | |
9854d9ed | 2382 | } |
5c23c401 | 2383 | return; |
9854d9ed | 2384 | |
9878760c RK |
2385 | case 0: |
2386 | if (GET_CODE (x) == REG) | |
2387 | fprintf (file, "%s", reg_names[REGNO (x)]); | |
2388 | else if (GET_CODE (x) == MEM) | |
2389 | { | |
2390 | /* We need to handle PRE_INC and PRE_DEC here, since we need to | |
2391 | know the width from the mode. */ | |
2392 | if (GET_CODE (XEXP (x, 0)) == PRE_INC) | |
2393 | fprintf (file, "%d(%d)", GET_MODE_SIZE (GET_MODE (x)), | |
2394 | REGNO (XEXP (XEXP (x, 0), 0))); | |
2395 | else if (GET_CODE (XEXP (x, 0)) == PRE_DEC) | |
2396 | fprintf (file, "%d(%d)", - GET_MODE_SIZE (GET_MODE (x)), | |
2397 | REGNO (XEXP (XEXP (x, 0), 0))); | |
2398 | else | |
a54d04b7 | 2399 | output_address (XEXP (x, 0)); |
9878760c RK |
2400 | } |
2401 | else | |
a54d04b7 | 2402 | output_addr_const (file, x); |
a85d226b | 2403 | return; |
9878760c RK |
2404 | |
2405 | default: | |
2406 | output_operand_lossage ("invalid %%xn code"); | |
2407 | } | |
2408 | } | |
2409 | \f | |
2410 | /* Print the address of an operand. */ | |
2411 | ||
2412 | void | |
2413 | print_operand_address (file, x) | |
2414 | FILE *file; | |
2415 | register rtx x; | |
2416 | { | |
2417 | if (GET_CODE (x) == REG) | |
4697a36c | 2418 | fprintf (file, "0(%s)", reg_names[ REGNO (x) ]); |
9878760c RK |
2419 | else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST) |
2420 | { | |
2421 | output_addr_const (file, x); | |
7509c759 MM |
2422 | if (DEFAULT_ABI == ABI_V4 && small_data_operand (x, GET_MODE (x))) |
2423 | fprintf (file, "@sda21(%s)", reg_names[0]); | |
2424 | ||
4697a36c | 2425 | #ifdef TARGET_NO_TOC |
7509c759 | 2426 | else if (TARGET_NO_TOC) |
4697a36c | 2427 | ; |
4697a36c | 2428 | #endif |
7509c759 | 2429 | else |
4697a36c | 2430 | fprintf (file, "(%s)", reg_names[ TARGET_MINIMAL_TOC ? 30 : 2 ]); |
9878760c RK |
2431 | } |
2432 | else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == REG) | |
2433 | { | |
2434 | if (REGNO (XEXP (x, 0)) == 0) | |
4697a36c MM |
2435 | fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 1)) ], |
2436 | reg_names[ REGNO (XEXP (x, 0)) ]); | |
9878760c | 2437 | else |
4697a36c MM |
2438 | fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 0)) ], |
2439 | reg_names[ REGNO (XEXP (x, 1)) ]); | |
9878760c RK |
2440 | } |
2441 | else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT) | |
4697a36c MM |
2442 | fprintf (file, "%d(%s)", INTVAL (XEXP (x, 1)), reg_names[ REGNO (XEXP (x, 0)) ]); |
2443 | else if (TARGET_ELF && !TARGET_64BIT && GET_CODE (x) == LO_SUM | |
2444 | && GET_CODE (XEXP (x, 0)) == REG && CONSTANT_P (XEXP (x, 1))) | |
2445 | { | |
2446 | output_addr_const (file, XEXP (x, 1)); | |
2447 | fprintf (file, "@l(%s)", reg_names[ REGNO (XEXP (x, 0)) ]); | |
2448 | } | |
9878760c RK |
2449 | else |
2450 | abort (); | |
2451 | } | |
2452 | \f | |
2453 | /* This page contains routines that are used to determine what the function | |
2454 | prologue and epilogue code will do and write them out. */ | |
2455 | ||
2456 | /* Return the first fixed-point register that is required to be saved. 32 if | |
2457 | none. */ | |
2458 | ||
2459 | int | |
2460 | first_reg_to_save () | |
2461 | { | |
2462 | int first_reg; | |
2463 | ||
2464 | /* Find lowest numbered live register. */ | |
2465 | for (first_reg = 13; first_reg <= 31; first_reg++) | |
2466 | if (regs_ever_live[first_reg]) | |
2467 | break; | |
2468 | ||
e165f3f0 RK |
2469 | /* If profiling, then we must save/restore every register that contains |
2470 | a parameter before/after the .mcount call. Use registers from 30 down | |
2471 | to 23 to do this. Don't use the frame pointer in reg 31. | |
2472 | ||
2473 | For now, save enough room for all of the parameter registers. */ | |
b6c9286a | 2474 | if (DEFAULT_ABI == ABI_AIX && profile_flag) |
e165f3f0 RK |
2475 | if (first_reg > 23) |
2476 | first_reg = 23; | |
2477 | ||
9878760c RK |
2478 | return first_reg; |
2479 | } | |
2480 | ||
2481 | /* Similar, for FP regs. */ | |
2482 | ||
2483 | int | |
2484 | first_fp_reg_to_save () | |
2485 | { | |
2486 | int first_reg; | |
2487 | ||
2488 | /* Find lowest numbered live register. */ | |
2489 | for (first_reg = 14 + 32; first_reg <= 63; first_reg++) | |
2490 | if (regs_ever_live[first_reg]) | |
2491 | break; | |
2492 | ||
2493 | return first_reg; | |
2494 | } | |
2495 | ||
9878760c RK |
2496 | /* Return non-zero if this function makes calls. */ |
2497 | ||
2498 | int | |
2499 | rs6000_makes_calls () | |
2500 | { | |
2501 | rtx insn; | |
2502 | ||
0c61c946 RK |
2503 | /* If we are profiling, we will be making a call to mcount. */ |
2504 | if (profile_flag) | |
2505 | return 1; | |
2506 | ||
9878760c RK |
2507 | for (insn = get_insns (); insn; insn = next_insn (insn)) |
2508 | if (GET_CODE (insn) == CALL_INSN) | |
2509 | return 1; | |
2510 | ||
2511 | return 0; | |
2512 | } | |
2513 | ||
4697a36c MM |
2514 | \f |
2515 | /* Calculate the stack information for the current function. This is | |
2516 | complicated by having two separate calling sequences, the AIX calling | |
2517 | sequence and the V.4 calling sequence. | |
2518 | ||
2519 | AIX stack frames look like: | |
2520 | ||
2521 | SP----> +---------------------------------------+ | |
2522 | | back chain to caller | 0 | |
2523 | +---------------------------------------+ | |
2524 | | saved CR | 4 | |
2525 | +---------------------------------------+ | |
2526 | | saved LR | 8 | |
2527 | +---------------------------------------+ | |
2528 | | reserved for compilers | 12 | |
2529 | +---------------------------------------+ | |
2530 | | reserved for binders | 16 | |
2531 | +---------------------------------------+ | |
2532 | | saved TOC pointer | 20 | |
2533 | +---------------------------------------+ | |
2534 | | Parameter save area (P) | 24 | |
2535 | +---------------------------------------+ | |
2536 | | Alloca space (A) | 24+P | |
2537 | +---------------------------------------+ | |
2538 | | Local variable space (L) | 24+P+A | |
2539 | +---------------------------------------+ | |
2540 | | Save area for GP registers (G) | 24+P+A+L | |
2541 | +---------------------------------------+ | |
2542 | | Save area for FP registers (F) | 24+P+A+L+G | |
2543 | +---------------------------------------+ | |
2544 | old SP->| back chain to caller's caller | | |
2545 | +---------------------------------------+ | |
2546 | ||
2547 | V.4 stack frames look like: | |
2548 | ||
2549 | SP----> +---------------------------------------+ | |
2550 | | back chain to caller | 0 | |
2551 | +---------------------------------------+ | |
5eb387b8 | 2552 | | caller's saved LR | 4 |
4697a36c MM |
2553 | +---------------------------------------+ |
2554 | | Parameter save area (P) | 8 | |
2555 | +---------------------------------------+ | |
2556 | | Alloca space (A) | 8+P | |
2557 | +---------------------------------------+ | |
2558 | | Varargs save area (V) | 8+P+A | |
2559 | +---------------------------------------+ | |
2560 | | Local variable space (L) | 8+P+A+V | |
2561 | +---------------------------------------+ | |
2562 | | saved CR (C) | 8+P+A+V+L | |
2563 | +---------------------------------------+ | |
2564 | | Save area for GP registers (G) | 8+P+A+V+L+C | |
2565 | +---------------------------------------+ | |
2566 | | Save area for FP registers (F) | 8+P+A+V+L+C+G | |
2567 | +---------------------------------------+ | |
2568 | old SP->| back chain to caller's caller | | |
2569 | +---------------------------------------+ | |
b6c9286a MM |
2570 | |
2571 | ||
2572 | A PowerPC Windows/NT frame looks like: | |
2573 | ||
2574 | SP----> +---------------------------------------+ | |
2575 | | back chain to caller | 0 | |
2576 | +---------------------------------------+ | |
2577 | | reserved | 4 | |
2578 | +---------------------------------------+ | |
2579 | | reserved | 8 | |
2580 | +---------------------------------------+ | |
2581 | | reserved | 12 | |
2582 | +---------------------------------------+ | |
2583 | | reserved | 16 | |
2584 | +---------------------------------------+ | |
2585 | | reserved | 20 | |
2586 | +---------------------------------------+ | |
2587 | | Parameter save area (P) | 24 | |
2588 | +---------------------------------------+ | |
2589 | | Alloca space (A) | 24+P | |
2590 | +---------------------------------------+ | |
2591 | | Local variable space (L) | 24+P+A | |
2592 | +---------------------------------------+ | |
2593 | | Save area for FP registers (F) | 24+P+A+L | |
2594 | +---------------------------------------+ | |
2595 | | Possible alignment area (X) | 24+P+A+L+F | |
2596 | +---------------------------------------+ | |
2597 | | Save area for GP registers (G) | 24+P+A+L+F+X | |
2598 | +---------------------------------------+ | |
2599 | | Save area for CR (C) | 24+P+A+L+F+X+G | |
2600 | +---------------------------------------+ | |
2601 | | Save area for TOC (T) | 24+P+A+L+F+X+G+C | |
2602 | +---------------------------------------+ | |
2603 | | Save area for LR (R) | 24+P+A+L+F+X+G+C+T | |
2604 | +---------------------------------------+ | |
2605 | old SP->| back chain to caller's caller | | |
2606 | +---------------------------------------+ | |
2607 | ||
2608 | For NT, there is no specific order to save the registers, but in | |
2609 | order to support __builtin_return_address, the save area for the | |
2610 | link register needs to be in a known place, so we use -4 off of the | |
2611 | old SP. To support calls through pointers, we also allocate a | |
2612 | fixed slot to store the TOC, -8 off the old SP. */ | |
4697a36c MM |
2613 | |
2614 | rs6000_stack_t * | |
2615 | rs6000_stack_info () | |
2616 | { | |
2617 | static rs6000_stack_t info, zero_info; | |
2618 | rs6000_stack_t *info_ptr = &info; | |
2619 | int reg_size = TARGET_64BIT ? 8 : 4; | |
24d304eb | 2620 | enum rs6000_abi abi; |
b6c9286a | 2621 | int total_raw_size; |
4697a36c MM |
2622 | |
2623 | /* Zero all fields portably */ | |
2624 | info = zero_info; | |
2625 | ||
2626 | /* Select which calling sequence */ | |
b6c9286a | 2627 | info_ptr->abi = abi = DEFAULT_ABI; |
9878760c | 2628 | |
4697a36c MM |
2629 | /* Calculate which registers need to be saved & save area size */ |
2630 | info_ptr->first_gp_reg_save = first_reg_to_save (); | |
2631 | info_ptr->gp_size = reg_size * (32 - info_ptr->first_gp_reg_save); | |
2632 | ||
2633 | info_ptr->first_fp_reg_save = first_fp_reg_to_save (); | |
2634 | info_ptr->fp_size = 8 * (64 - info_ptr->first_fp_reg_save); | |
2635 | ||
2636 | /* Does this function call anything? */ | |
2637 | info_ptr->calls_p = rs6000_makes_calls (); | |
2638 | ||
b6c9286a MM |
2639 | /* Do we need to allocate space to save the toc? */ |
2640 | if (rs6000_save_toc_p) | |
2641 | { | |
2642 | info_ptr->toc_save_p = 1; | |
2643 | info_ptr->toc_size = reg_size; | |
2644 | } | |
2645 | ||
2646 | /* If this is main and we need to call a function to set things up, | |
2647 | save main's arguments around the call. */ | |
2648 | if (strcmp (IDENTIFIER_POINTER (DECL_NAME (current_function_decl)), "main") == 0) | |
2649 | { | |
2650 | info_ptr->main_p = 1; | |
2651 | ||
2652 | #ifdef NAME__MAIN | |
cf27b467 MM |
2653 | info_ptr->calls_p = 1; |
2654 | ||
b6c9286a MM |
2655 | if (DECL_ARGUMENTS (current_function_decl)) |
2656 | { | |
2657 | int i; | |
2658 | tree arg; | |
2659 | ||
2660 | info_ptr->main_save_p = 1; | |
2661 | info_ptr->main_size = 0; | |
b6c9286a MM |
2662 | |
2663 | for ((i = 0), (arg = DECL_ARGUMENTS (current_function_decl)); | |
2664 | arg != NULL_TREE && i < 8; | |
2665 | (arg = TREE_CHAIN (arg)), i++) | |
2666 | { | |
2667 | info_ptr->main_size += reg_size; | |
2668 | } | |
2669 | } | |
2670 | #endif | |
2671 | } | |
2672 | ||
4697a36c MM |
2673 | /* Determine if we need to save the link register */ |
2674 | if (regs_ever_live[65] || profile_flag | |
2675 | #ifdef TARGET_RELOCATABLE | |
2676 | || (TARGET_RELOCATABLE && (get_pool_size () != 0)) | |
2677 | #endif | |
2678 | || (info_ptr->first_fp_reg_save != 64 | |
2679 | && !FP_SAVE_INLINE (info_ptr->first_fp_reg_save)) | |
24d304eb | 2680 | || (abi == ABI_V4 && current_function_calls_alloca) |
4697a36c MM |
2681 | || info_ptr->calls_p) |
2682 | { | |
2683 | info_ptr->lr_save_p = 1; | |
2684 | regs_ever_live[65] = 1; | |
b6c9286a MM |
2685 | if (abi == ABI_NT) |
2686 | info_ptr->lr_size = reg_size; | |
4697a36c MM |
2687 | } |
2688 | ||
2689 | /* Determine if we need to save the condition code registers */ | |
2690 | if (regs_ever_live[70] || regs_ever_live[71] || regs_ever_live[72]) | |
2691 | { | |
2692 | info_ptr->cr_save_p = 1; | |
b6c9286a | 2693 | if (abi == ABI_V4 || abi == ABI_NT) |
4697a36c MM |
2694 | info_ptr->cr_size = reg_size; |
2695 | } | |
2696 | ||
2697 | /* Determine various sizes */ | |
2698 | info_ptr->reg_size = reg_size; | |
2699 | info_ptr->fixed_size = RS6000_SAVE_AREA; | |
2700 | info_ptr->varargs_size = RS6000_VARARGS_AREA; | |
2701 | info_ptr->vars_size = ALIGN (get_frame_size (), 8); | |
2702 | info_ptr->parm_size = ALIGN (current_function_outgoing_args_size, 8); | |
b6c9286a MM |
2703 | info_ptr->save_size = ALIGN (info_ptr->fp_size |
2704 | + info_ptr->gp_size | |
2705 | + info_ptr->cr_size | |
2706 | + info_ptr->lr_size | |
2707 | + info_ptr->toc_size | |
2708 | + info_ptr->main_size, 8); | |
2709 | ||
2710 | total_raw_size = (info_ptr->vars_size | |
2711 | + info_ptr->parm_size | |
2712 | + info_ptr->save_size | |
2713 | + info_ptr->varargs_size | |
2714 | + info_ptr->fixed_size); | |
2715 | ||
2716 | info_ptr->total_size = ALIGN (total_raw_size, STACK_BOUNDARY / BITS_PER_UNIT); | |
4697a36c MM |
2717 | |
2718 | /* Determine if we need to allocate any stack frame. | |
2719 | For AIX We need to push the stack if a frame pointer is needed (because | |
2720 | the stack might be dynamically adjusted), if we are debugging, if the | |
2721 | total stack size is more than 220 bytes, or if we make calls. | |
2722 | ||
2723 | For V.4 we don't have the stack cushion that AIX uses, but assume that | |
2724 | the debugger can handle stackless frames. */ | |
2725 | ||
2726 | if (info_ptr->calls_p) | |
2727 | info_ptr->push_p = 1; | |
2728 | ||
b6c9286a MM |
2729 | else if (abi == ABI_V4 || abi == ABI_NT) |
2730 | info_ptr->push_p = (total_raw_size > info_ptr->fixed_size | |
4697a36c MM |
2731 | || info_ptr->lr_save_p); |
2732 | ||
2733 | else | |
2734 | info_ptr->push_p = (frame_pointer_needed | |
2735 | || write_symbols != NO_DEBUG | |
2736 | || info_ptr->total_size > 220); | |
2737 | ||
2738 | /* Calculate the offsets */ | |
24d304eb | 2739 | switch (abi) |
4697a36c | 2740 | { |
b6c9286a | 2741 | case ABI_NONE: |
24d304eb | 2742 | default: |
b6c9286a MM |
2743 | abort (); |
2744 | ||
2745 | case ABI_AIX: | |
2746 | case ABI_AIX_NODESC: | |
2747 | info_ptr->fp_save_offset = - info_ptr->fp_size; | |
2748 | info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size; | |
2749 | info_ptr->main_save_offset = info_ptr->gp_save_offset - info_ptr->main_size; | |
2750 | info_ptr->cr_save_offset = 4; | |
2751 | info_ptr->lr_save_offset = 8; | |
24d304eb RK |
2752 | break; |
2753 | ||
2754 | case ABI_V4: | |
b6c9286a MM |
2755 | info_ptr->fp_save_offset = - info_ptr->fp_size; |
2756 | info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size; | |
2757 | info_ptr->cr_save_offset = info_ptr->gp_save_offset - reg_size; | |
2758 | info_ptr->toc_save_offset = info_ptr->cr_save_offset - info_ptr->cr_size; | |
2759 | info_ptr->main_save_offset = info_ptr->toc_save_offset - info_ptr->toc_size; | |
2760 | info_ptr->lr_save_offset = reg_size; | |
2761 | break; | |
2762 | ||
2763 | case ABI_NT: | |
2764 | info_ptr->lr_save_offset = -4; | |
2765 | info_ptr->toc_save_offset = info_ptr->lr_save_offset - info_ptr->lr_size; | |
2766 | info_ptr->cr_save_offset = info_ptr->toc_save_offset - info_ptr->toc_size; | |
2767 | info_ptr->gp_save_offset = info_ptr->cr_save_offset - info_ptr->cr_size - info_ptr->gp_size + reg_size; | |
2768 | info_ptr->fp_save_offset = info_ptr->gp_save_offset - info_ptr->fp_size; | |
2769 | if (info_ptr->fp_size && ((- info_ptr->fp_save_offset) % 8) != 0) | |
2770 | info_ptr->fp_save_offset -= 4; | |
2771 | ||
2772 | info_ptr->main_save_offset = info_ptr->fp_save_offset - info_ptr->main_size; | |
24d304eb | 2773 | break; |
4697a36c MM |
2774 | } |
2775 | ||
2776 | /* Zero offsets if we're not saving those registers */ | |
2777 | if (!info_ptr->fp_size) | |
2778 | info_ptr->fp_save_offset = 0; | |
2779 | ||
2780 | if (!info_ptr->gp_size) | |
2781 | info_ptr->gp_save_offset = 0; | |
2782 | ||
2783 | if (!info_ptr->lr_save_p) | |
2784 | info_ptr->lr_save_offset = 0; | |
2785 | ||
2786 | if (!info_ptr->cr_save_p) | |
2787 | info_ptr->cr_save_offset = 0; | |
2788 | ||
b6c9286a MM |
2789 | if (!info_ptr->toc_save_p) |
2790 | info_ptr->toc_save_offset = 0; | |
2791 | ||
2792 | if (!info_ptr->main_save_p) | |
2793 | info_ptr->main_save_offset = 0; | |
2794 | ||
4697a36c MM |
2795 | return info_ptr; |
2796 | } | |
2797 | ||
2798 | void | |
2799 | debug_stack_info (info) | |
2800 | rs6000_stack_t *info; | |
9878760c | 2801 | { |
24d304eb RK |
2802 | char *abi_string; |
2803 | ||
4697a36c MM |
2804 | if (!info) |
2805 | info = rs6000_stack_info (); | |
2806 | ||
2807 | fprintf (stderr, "\nStack information for function %s:\n", | |
2808 | ((current_function_decl && DECL_NAME (current_function_decl)) | |
2809 | ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl)) | |
2810 | : "<unknown>")); | |
2811 | ||
24d304eb RK |
2812 | switch (info->abi) |
2813 | { | |
b6c9286a MM |
2814 | default: abi_string = "Unknown"; break; |
2815 | case ABI_NONE: abi_string = "NONE"; break; | |
2816 | case ABI_AIX: abi_string = "AIX"; break; | |
2817 | case ABI_AIX_NODESC: abi_string = "AIX"; break; | |
2818 | case ABI_V4: abi_string = "V.4"; break; | |
2819 | case ABI_NT: abi_string = "NT"; break; | |
24d304eb RK |
2820 | } |
2821 | ||
2822 | fprintf (stderr, "\tABI = %5s\n", abi_string); | |
2823 | ||
4697a36c MM |
2824 | if (info->first_gp_reg_save != 32) |
2825 | fprintf (stderr, "\tfirst_gp_reg_save = %5d\n", info->first_gp_reg_save); | |
2826 | ||
2827 | if (info->first_fp_reg_save != 64) | |
2828 | fprintf (stderr, "\tfirst_fp_reg_save = %5d\n", info->first_fp_reg_save); | |
9878760c | 2829 | |
4697a36c MM |
2830 | if (info->lr_save_p) |
2831 | fprintf (stderr, "\tlr_save_p = %5d\n", info->lr_save_p); | |
9878760c | 2832 | |
4697a36c MM |
2833 | if (info->cr_save_p) |
2834 | fprintf (stderr, "\tcr_save_p = %5d\n", info->cr_save_p); | |
2835 | ||
b6c9286a MM |
2836 | if (info->toc_save_p) |
2837 | fprintf (stderr, "\ttoc_save_p = %5d\n", info->toc_save_p); | |
2838 | ||
4697a36c MM |
2839 | if (info->push_p) |
2840 | fprintf (stderr, "\tpush_p = %5d\n", info->push_p); | |
2841 | ||
2842 | if (info->calls_p) | |
2843 | fprintf (stderr, "\tcalls_p = %5d\n", info->calls_p); | |
2844 | ||
b6c9286a MM |
2845 | if (info->main_p) |
2846 | fprintf (stderr, "\tmain_p = %5d\n", info->main_p); | |
2847 | ||
2848 | if (info->main_save_p) | |
2849 | fprintf (stderr, "\tmain_save_p = %5d\n", info->main_save_p); | |
2850 | ||
4697a36c MM |
2851 | if (info->gp_save_offset) |
2852 | fprintf (stderr, "\tgp_save_offset = %5d\n", info->gp_save_offset); | |
2853 | ||
2854 | if (info->fp_save_offset) | |
2855 | fprintf (stderr, "\tfp_save_offset = %5d\n", info->fp_save_offset); | |
2856 | ||
2857 | if (info->lr_save_offset) | |
2858 | fprintf (stderr, "\tlr_save_offset = %5d\n", info->lr_save_offset); | |
2859 | ||
2860 | if (info->cr_save_offset) | |
2861 | fprintf (stderr, "\tcr_save_offset = %5d\n", info->cr_save_offset); | |
2862 | ||
b6c9286a MM |
2863 | if (info->toc_save_offset) |
2864 | fprintf (stderr, "\ttoc_save_offset = %5d\n", info->toc_save_offset); | |
2865 | ||
4697a36c MM |
2866 | if (info->varargs_save_offset) |
2867 | fprintf (stderr, "\tvarargs_save_offset = %5d\n", info->varargs_save_offset); | |
2868 | ||
b6c9286a MM |
2869 | if (info->main_save_offset) |
2870 | fprintf (stderr, "\tmain_save_offset = %5d\n", info->main_save_offset); | |
2871 | ||
4697a36c MM |
2872 | if (info->total_size) |
2873 | fprintf (stderr, "\ttotal_size = %5d\n", info->total_size); | |
2874 | ||
2875 | if (info->varargs_size) | |
2876 | fprintf (stderr, "\tvarargs_size = %5d\n", info->varargs_size); | |
2877 | ||
2878 | if (info->vars_size) | |
2879 | fprintf (stderr, "\tvars_size = %5d\n", info->vars_size); | |
2880 | ||
2881 | if (info->parm_size) | |
2882 | fprintf (stderr, "\tparm_size = %5d\n", info->parm_size); | |
2883 | ||
2884 | if (info->fixed_size) | |
2885 | fprintf (stderr, "\tfixed_size = %5d\n", info->fixed_size); | |
2886 | ||
2887 | if (info->gp_size) | |
2888 | fprintf (stderr, "\tgp_size = %5d\n", info->gp_size); | |
2889 | ||
2890 | if (info->fp_size) | |
2891 | fprintf (stderr, "\tfp_size = %5d\n", info->fp_size); | |
2892 | ||
b6c9286a MM |
2893 | if (info->lr_size) |
2894 | fprintf (stderr, "\tlr_size = %5d\n", info->cr_size); | |
2895 | ||
4697a36c MM |
2896 | if (info->cr_size) |
2897 | fprintf (stderr, "\tcr_size = %5d\n", info->cr_size); | |
2898 | ||
b6c9286a MM |
2899 | if (info->toc_size) |
2900 | fprintf (stderr, "\ttoc_size = %5d\n", info->toc_size); | |
2901 | ||
2902 | if (info->main_size) | |
2903 | fprintf (stderr, "\tmain_size = %5d\n", info->main_size); | |
2904 | ||
4697a36c MM |
2905 | if (info->save_size) |
2906 | fprintf (stderr, "\tsave_size = %5d\n", info->save_size); | |
2907 | ||
2908 | if (info->reg_size != 4) | |
2909 | fprintf (stderr, "\treg_size = %5d\n", info->reg_size); | |
2910 | ||
2911 | fprintf (stderr, "\n"); | |
9878760c RK |
2912 | } |
2913 | ||
4697a36c | 2914 | \f |
9878760c | 2915 | /* Write function prologue. */ |
9878760c RK |
2916 | void |
2917 | output_prolog (file, size) | |
2918 | FILE *file; | |
2919 | int size; | |
2920 | { | |
4697a36c | 2921 | rs6000_stack_t *info = rs6000_stack_info (); |
b6c9286a MM |
2922 | int reg_size = info->reg_size; |
2923 | char *store_reg; | |
2924 | char *load_reg; | |
979721f8 MM |
2925 | int sp_reg = 1; |
2926 | int sp_offset = 0; | |
b6c9286a | 2927 | |
8f802bfb | 2928 | if (TARGET_32BIT) |
b6c9286a | 2929 | { |
8f802bfb DE |
2930 | store_reg = "\t{st|stw} %s,%d(%s)\n"; |
2931 | load_reg = "\t{l|lwz} %s,%d(%s)\n"; | |
b6c9286a MM |
2932 | } |
2933 | else | |
2934 | { | |
8f802bfb DE |
2935 | store_reg = "\tstd %s,%d(%s)\n"; |
2936 | load_reg = "\tlld %s,%d(%s)\n"; | |
b6c9286a | 2937 | } |
9878760c | 2938 | |
4697a36c MM |
2939 | if (TARGET_DEBUG_STACK) |
2940 | debug_stack_info (info); | |
9878760c RK |
2941 | |
2942 | /* Write .extern for any function we will call to save and restore fp | |
2943 | values. */ | |
b6c9286a | 2944 | if (info->first_fp_reg_save < 64 && !FP_SAVE_INLINE (info->first_fp_reg_save)) |
4d30c363 | 2945 | fprintf (file, "\t.extern %s%d%s\n\t.extern %s%d%s\n", |
4697a36c MM |
2946 | SAVE_FP_PREFIX, info->first_fp_reg_save - 32, SAVE_FP_SUFFIX, |
2947 | RESTORE_FP_PREFIX, info->first_fp_reg_save - 32, RESTORE_FP_SUFFIX); | |
9878760c RK |
2948 | |
2949 | /* Write .extern for truncation routines, if needed. */ | |
2950 | if (rs6000_trunc_used && ! trunc_defined) | |
2951 | { | |
e138174b ILT |
2952 | fprintf (file, "\t.extern .%s\n\t.extern .%s\n", |
2953 | RS6000_ITRUNC, RS6000_UITRUNC); | |
9878760c RK |
2954 | trunc_defined = 1; |
2955 | } | |
4697a36c | 2956 | |
c764f757 RK |
2957 | /* Write .extern for AIX common mode routines, if needed. */ |
2958 | if (! TARGET_POWER && ! TARGET_POWERPC && ! common_mode_defined) | |
2959 | { | |
f6709c70 JW |
2960 | fputs ("\t.extern __mulh\n", file); |
2961 | fputs ("\t.extern __mull\n", file); | |
2962 | fputs ("\t.extern __divss\n", file); | |
2963 | fputs ("\t.extern __divus\n", file); | |
2964 | fputs ("\t.extern __quoss\n", file); | |
2965 | fputs ("\t.extern __quous\n", file); | |
c764f757 RK |
2966 | common_mode_defined = 1; |
2967 | } | |
9878760c | 2968 | |
979721f8 MM |
2969 | /* For V.4, update stack before we do any saving and set back pointer. */ |
2970 | if (info->push_p && DEFAULT_ABI == ABI_V4) | |
2971 | { | |
2972 | if (info->total_size < 32767) | |
2973 | { | |
2974 | asm_fprintf (file, | |
2975 | (TARGET_32BIT) ? "\t{stu|stwu} %s,%d(%s)\n" : "\tstdu %s,%d(%s)\n", | |
2976 | reg_names[1], - info->total_size, reg_names[1]); | |
2977 | sp_offset = info->total_size; | |
2978 | } | |
2979 | else | |
2980 | { | |
2981 | int neg_size = - info->total_size; | |
2982 | sp_reg = 12; | |
2983 | asm_fprintf (file, "\tmr %s,%s\n", reg_names[12], reg_names[1]); | |
2984 | asm_fprintf (file, "\t{liu|lis} %s,%d\n\t{oril|ori} %s,%s,%d\n", | |
2985 | reg_names[0], (neg_size >> 16) & 0xffff, | |
2986 | reg_names[0], reg_names[0], neg_size & 0xffff); | |
2987 | asm_fprintf (file, | |
2988 | (TARGET_32BIT) ? "\t{stux|stwux} %s,%s,%s\n" : "\tstdux %s,%s,%s\n", | |
2989 | reg_names[1], reg_names[1], reg_names[0]); | |
2990 | } | |
2991 | } | |
2992 | ||
9878760c | 2993 | /* If we use the link register, get it into r0. */ |
4697a36c MM |
2994 | if (info->lr_save_p) |
2995 | asm_fprintf (file, "\tmflr %s\n", reg_names[0]); | |
9878760c RK |
2996 | |
2997 | /* If we need to save CR, put it into r12. */ | |
979721f8 | 2998 | if (info->cr_save_p && sp_reg != 12) |
4697a36c | 2999 | asm_fprintf (file, "\tmfcr %s\n", reg_names[12]); |
9878760c RK |
3000 | |
3001 | /* Do any required saving of fpr's. If only one or two to save, do it | |
53322b0c RK |
3002 | ourself. Otherwise, call function. Note that since they are statically |
3003 | linked, we do not need a nop following them. */ | |
4697a36c | 3004 | if (FP_SAVE_INLINE (info->first_fp_reg_save)) |
bacbde18 | 3005 | { |
4697a36c | 3006 | int regno = info->first_fp_reg_save; |
979721f8 | 3007 | int loc = info->fp_save_offset + sp_offset; |
4697a36c MM |
3008 | |
3009 | for ( ; regno < 64; regno++, loc += 8) | |
979721f8 | 3010 | asm_fprintf (file, "\tstfd %s,%d(%s)\n", reg_names[regno], loc, reg_names[sp_reg]); |
bacbde18 | 3011 | } |
4697a36c MM |
3012 | else if (info->first_fp_reg_save != 64) |
3013 | asm_fprintf (file, "\tbl %s%d%s\n", SAVE_FP_PREFIX, | |
3014 | info->first_fp_reg_save - 32, SAVE_FP_SUFFIX); | |
9878760c RK |
3015 | |
3016 | /* Now save gpr's. */ | |
4697a36c | 3017 | if (! TARGET_MULTIPLE || info->first_gp_reg_save == 31 || TARGET_64BIT) |
85638c0d | 3018 | { |
4697a36c | 3019 | int regno = info->first_gp_reg_save; |
979721f8 | 3020 | int loc = info->gp_save_offset + sp_offset; |
85638c0d | 3021 | |
4697a36c | 3022 | for ( ; regno < 32; regno++, loc += reg_size) |
979721f8 | 3023 | asm_fprintf (file, store_reg, reg_names[regno], loc, reg_names[sp_reg]); |
85638c0d RK |
3024 | } |
3025 | ||
4697a36c MM |
3026 | else if (info->first_gp_reg_save != 32) |
3027 | asm_fprintf (file, "\t{stm|stmw} %s,%d(%s)\n", | |
3028 | reg_names[info->first_gp_reg_save], | |
979721f8 MM |
3029 | info->gp_save_offset + sp_offset, |
3030 | reg_names[sp_reg]); | |
9878760c | 3031 | |
b6c9286a MM |
3032 | /* Save main's arguments if we need to call a function */ |
3033 | #ifdef NAME__MAIN | |
3034 | if (info->main_save_p) | |
3035 | { | |
3036 | int regno; | |
3037 | int loc = info->main_save_offset; | |
3038 | int size = info->main_size; | |
3039 | ||
3040 | for (regno = 3; size > 0; regno++, loc -= reg_size, size -= reg_size) | |
979721f8 | 3041 | asm_fprintf (file, store_reg, reg_names[regno], loc, reg_names[sp_reg]); |
b6c9286a MM |
3042 | } |
3043 | #endif | |
3044 | ||
9878760c | 3045 | /* Save lr if we used it. */ |
4697a36c | 3046 | if (info->lr_save_p) |
979721f8 MM |
3047 | asm_fprintf (file, store_reg, reg_names[0], info->lr_save_offset + sp_offset, |
3048 | reg_names[sp_reg]); | |
9878760c RK |
3049 | |
3050 | /* Save CR if we use any that must be preserved. */ | |
4697a36c | 3051 | if (info->cr_save_p) |
979721f8 MM |
3052 | { |
3053 | if (sp_reg == 12) /* If r12 is used to hold the original sp, copy cr now */ | |
3054 | { | |
3055 | asm_fprintf (file, "\tmfcr %s\n", reg_names[0]); | |
3056 | asm_fprintf (file, store_reg, reg_names[0], | |
3057 | info->cr_save_offset + sp_offset, | |
3058 | reg_names[sp_reg]); | |
3059 | } | |
3060 | else | |
3061 | asm_fprintf (file, store_reg, reg_names[12], info->cr_save_offset + sp_offset, | |
3062 | reg_names[sp_reg]); | |
3063 | } | |
9878760c | 3064 | |
b6c9286a | 3065 | if (info->toc_save_p) |
979721f8 MM |
3066 | asm_fprintf (file, store_reg, reg_names[2], info->toc_save_offset + sp_offset, |
3067 | reg_names[sp_reg]); | |
b6c9286a | 3068 | |
979721f8 MM |
3069 | /* NT needs us to probe the stack frame every 4k pages for large frames, so |
3070 | do it here. */ | |
3071 | if (DEFAULT_ABI == ABI_NT && info->total_size > 4096) | |
3072 | { | |
3073 | if (info->total_size < 32768) | |
3074 | { | |
3075 | int probe_offset = 4096; | |
3076 | while (probe_offset < info->total_size) | |
3077 | { | |
3078 | asm_fprintf (file, "\t{l|lwz} %s,%d(%s)\n", reg_names[0], -probe_offset, reg_names[1]); | |
3079 | probe_offset += 4096; | |
3080 | } | |
3081 | } | |
3082 | else | |
3083 | { | |
3084 | int probe_iterations = info->total_size / 4096; | |
3085 | static int probe_labelno = 0; | |
3086 | char buf[256]; | |
3087 | ||
3088 | if (probe_iterations < 32768) | |
3089 | asm_fprintf (file, "\tli %s,%d\n", reg_names[12], probe_iterations); | |
3090 | else | |
3091 | { | |
3092 | asm_fprintf (file, "\tlis %s,%d\n", reg_names[12], probe_iterations >> 16); | |
3093 | if (probe_iterations & 0xffff) | |
3094 | asm_fprintf (file, "\tori %s,%s,%d\n", reg_names[12], reg_names[12], | |
3095 | probe_iterations & 0xffff); | |
3096 | } | |
3097 | asm_fprintf (file, "\tmtctr %s\n", reg_names[12]); | |
3098 | asm_fprintf (file, "\tmr %s,%s\n", reg_names[12], reg_names[1]); | |
3099 | ASM_OUTPUT_INTERNAL_LABEL (file, "LCprobe", probe_labelno); | |
3100 | asm_fprintf (file, "\t{lu|lwzu} %s,-4096(%s)\n", reg_names[0], reg_names[12]); | |
3101 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCprobe", probe_labelno); | |
3102 | fputs ("\tbdnz ", file); | |
3103 | assemble_name (file, buf); | |
3104 | fputs ("\n", file); | |
3105 | } | |
3106 | } | |
3107 | ||
3108 | /* Update stack and set back pointer and we have already done so for V.4. */ | |
3109 | if (info->push_p && DEFAULT_ABI != ABI_V4) | |
9878760c | 3110 | { |
4697a36c MM |
3111 | if (info->total_size < 32767) |
3112 | asm_fprintf (file, | |
8f802bfb | 3113 | (TARGET_32BIT) ? "\t{stu|stwu} %s,%d(%s)\n" : "\tstdu %s,%d(%s)\n", |
4697a36c | 3114 | reg_names[1], - info->total_size, reg_names[1]); |
9878760c RK |
3115 | else |
3116 | { | |
ef7a1424 | 3117 | int neg_size = - info->total_size; |
4697a36c | 3118 | asm_fprintf (file, "\t{liu|lis} %s,%d\n\t{oril|ori} %s,%s,%d\n", |
ef7a1424 RK |
3119 | reg_names[0], (neg_size >> 16) & 0xffff, |
3120 | reg_names[0], reg_names[0], neg_size & 0xffff); | |
4697a36c | 3121 | asm_fprintf (file, |
8f802bfb | 3122 | (TARGET_32BIT) ? "\t{stux|stwux} %s,%s,%s\n" : "\tstdux %s,%s,%s\n", |
4697a36c | 3123 | reg_names[1], reg_names[1], reg_names[0]); |
9878760c RK |
3124 | } |
3125 | } | |
3126 | ||
3127 | /* Set frame pointer, if needed. */ | |
3128 | if (frame_pointer_needed) | |
4697a36c | 3129 | asm_fprintf (file, "\tmr %s,%s\n", reg_names[31], reg_names[1]); |
1875cc88 | 3130 | |
b6c9286a MM |
3131 | #ifdef NAME__MAIN |
3132 | /* If we need to call a function to set things up for main, do so now | |
3133 | before dealing with the TOC. */ | |
3134 | if (info->main_p) | |
3135 | { | |
3136 | char *prefix = ""; | |
3137 | ||
3138 | switch (DEFAULT_ABI) | |
3139 | { | |
3140 | case ABI_AIX: prefix = "."; break; | |
3141 | case ABI_NT: prefix = ".."; break; | |
3142 | } | |
3143 | ||
3144 | fprintf (file, "\tbl %s%s\n", prefix, NAME__MAIN); | |
3145 | #ifdef RS6000_CALL_GLUE2 | |
3146 | fprintf (file, "\t%s%s%s\n", RS6000_CALL_GLUE2, prefix, NAME_MAIN); | |
3147 | #else | |
3148 | #ifdef RS6000_CALL_GLUE | |
3149 | if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_NT) | |
3150 | fprintf (file, "\t%s\n", RS6000_CALL_GLUE); | |
3151 | #endif | |
3152 | #endif | |
3153 | ||
3154 | if (info->main_save_p) | |
3155 | { | |
3156 | int regno; | |
3157 | int loc; | |
3158 | int size = info->main_size; | |
3159 | ||
3160 | if (info->total_size < 32767) | |
3161 | { | |
3162 | loc = info->total_size + info->main_save_offset; | |
3163 | for (regno = 3; size > 0; regno++, size -= reg_size, loc -= reg_size) | |
3164 | asm_fprintf (file, load_reg, reg_names[regno], loc, reg_names[1]); | |
3165 | } | |
3166 | else | |
979721f8 MM |
3167 | { /* for large AIX/NT frames, reg 0 above contains -frame size */ |
3168 | /* for V.4, we need to reload -frame size */ | |
b6c9286a | 3169 | loc = info->main_save_offset; |
979721f8 MM |
3170 | if (DEFAULT_ABI == ABI_V4 && info->total_size > 32767) |
3171 | { | |
3172 | int neg_size = - info->total_size; | |
3173 | asm_fprintf (file, "\t{liu|lis} %s,%d\n\t{oril|ori} %s,%s,%d\n", | |
3174 | reg_names[0], (neg_size >> 16) & 0xffff, | |
3175 | reg_names[0], reg_names[0], neg_size & 0xffff); | |
3176 | } | |
3177 | ||
b6c9286a MM |
3178 | asm_fprintf (file, "\t{sf|subf} %s,%s,%s\n", reg_names[0], reg_names[0], |
3179 | reg_names[1]); | |
3180 | ||
3181 | for (regno = 3; size > 0; regno++, size -= reg_size, loc -= reg_size) | |
3182 | asm_fprintf (file, load_reg, reg_names[regno], loc, reg_names[0]); | |
3183 | } | |
3184 | } | |
3185 | } | |
3186 | #endif | |
3187 | ||
3188 | ||
1875cc88 JW |
3189 | /* If TARGET_MINIMAL_TOC, and the constant pool is needed, then load the |
3190 | TOC_TABLE address into register 30. */ | |
4697a36c | 3191 | if (TARGET_TOC && TARGET_MINIMAL_TOC && get_pool_size () != 0) |
3daf36a4 | 3192 | { |
d14a6d05 MM |
3193 | char buf[256]; |
3194 | ||
b6c9286a | 3195 | #ifdef TARGET_RELOCATABLE |
d14a6d05 MM |
3196 | if (TARGET_RELOCATABLE) |
3197 | { | |
874a0744 | 3198 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno); |
19d2d16f | 3199 | fputs ("\tbl ", file); |
d14a6d05 | 3200 | assemble_name (file, buf); |
19d2d16f | 3201 | putc ('\n', file); |
d14a6d05 | 3202 | |
874a0744 | 3203 | ASM_OUTPUT_INTERNAL_LABEL (file, "LCF", rs6000_pic_labelno); |
4697a36c | 3204 | fprintf (file, "\tmflr %s\n", reg_names[30]); |
3daf36a4 | 3205 | |
03a7e1a5 | 3206 | asm_fprintf (file, (TARGET_32BIT) ? "\t{l|lwz}" : "\tld"); |
4697a36c | 3207 | fprintf (file, " %s,(", reg_names[0]); |
874a0744 MM |
3208 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno); |
3209 | assemble_name (file, buf); | |
19d2d16f | 3210 | putc ('-', file); |
874a0744 MM |
3211 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno); |
3212 | assemble_name (file, buf); | |
4697a36c MM |
3213 | fprintf (file, ")(%s)\n", reg_names[30]); |
3214 | asm_fprintf (file, "\t{cax|add} %s,%s,%s\n", | |
3215 | reg_names[30], reg_names[0], reg_names[30]); | |
874a0744 | 3216 | rs6000_pic_labelno++; |
d14a6d05 | 3217 | } |
b6c9286a MM |
3218 | else |
3219 | #endif | |
3220 | ||
3221 | switch (DEFAULT_ABI) | |
3222 | { | |
3223 | case ABI_V4: | |
3224 | case ABI_AIX_NODESC: | |
8f802bfb | 3225 | if (TARGET_32BIT) |
b6c9286a MM |
3226 | { |
3227 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1); | |
3228 | asm_fprintf (file, "\t{cau|addis} %s,%s,", reg_names[30], reg_names[0]); | |
3229 | assemble_name (file, buf); | |
3230 | asm_fprintf (file, "@ha\n"); | |
3231 | if (TARGET_NEW_MNEMONICS) | |
3232 | { | |
3233 | asm_fprintf (file, "\taddi %s,%s,", reg_names[30], reg_names[30]); | |
3234 | assemble_name (file, buf); | |
3235 | asm_fprintf (file, "@l\n"); | |
3236 | } | |
3237 | else | |
3238 | { | |
3239 | asm_fprintf (file, "\tcal %s,", reg_names[30]); | |
3240 | assemble_name (file, buf); | |
3241 | asm_fprintf (file, "@l(%s)\n", reg_names[30]); | |
3242 | } | |
3243 | } | |
3244 | else | |
3245 | abort (); | |
3246 | ||
3247 | break; | |
3248 | ||
3249 | case ABI_NT: | |
3250 | case ABI_AIX: | |
3251 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 0); | |
3252 | asm_fprintf (file, "\t{l|lwz} %s,", reg_names[30]); | |
3933e0e1 | 3253 | assemble_name (file, buf); |
b6c9286a MM |
3254 | asm_fprintf (file, "(%s)\n", reg_names[2]); |
3255 | break; | |
3933e0e1 | 3256 | } |
b6c9286a | 3257 | } |
4697a36c | 3258 | |
b6c9286a MM |
3259 | if (DEFAULT_ABI == ABI_NT) |
3260 | { | |
3261 | assemble_name (file, XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); | |
3262 | fputs (".b:\n", file); | |
3daf36a4 | 3263 | } |
9878760c RK |
3264 | } |
3265 | ||
3266 | /* Write function epilogue. */ | |
3267 | ||
3268 | void | |
3269 | output_epilog (file, size) | |
3270 | FILE *file; | |
3271 | int size; | |
3272 | { | |
4697a36c | 3273 | rs6000_stack_t *info = rs6000_stack_info (); |
8f802bfb | 3274 | char *load_reg = (TARGET_32BIT) ? "\t{l|lwz} %s,%d(%s)\n" : "\tld %s,%d(%s)\n"; |
9878760c | 3275 | rtx insn = get_last_insn (); |
979721f8 MM |
3276 | int sp_reg = 1; |
3277 | int sp_offset = 0; | |
5b5040b9 | 3278 | int i; |
9878760c | 3279 | |
5b5040b9 RK |
3280 | /* Forget about any temporaries created */ |
3281 | for (i = 0; i < NUM_MACHINE_MODES; i++) | |
3282 | stack_temps[i] = NULL_RTX; | |
8f75773e | 3283 | |
9878760c RK |
3284 | /* If the last insn was a BARRIER, we don't have to write anything except |
3285 | the trace table. */ | |
3286 | if (GET_CODE (insn) == NOTE) | |
3287 | insn = prev_nonnote_insn (insn); | |
3288 | if (insn == 0 || GET_CODE (insn) != BARRIER) | |
3289 | { | |
3290 | /* If we have a frame pointer, a call to alloca, or a large stack | |
3291 | frame, restore the old stack pointer using the backchain. Otherwise, | |
3292 | we know what size to update it with. */ | |
3293 | if (frame_pointer_needed || current_function_calls_alloca | |
4697a36c | 3294 | || info->total_size > 32767) |
979721f8 MM |
3295 | { |
3296 | /* Under V.4, don't reset the stack pointer until after we're done | |
3297 | loading the saved registers. */ | |
3298 | if (DEFAULT_ABI == ABI_V4) | |
3299 | sp_reg = 11; | |
3300 | ||
3301 | asm_fprintf (file, load_reg, reg_names[sp_reg], 0, reg_names[1]); | |
3302 | } | |
4697a36c MM |
3303 | else if (info->push_p) |
3304 | { | |
979721f8 MM |
3305 | if (DEFAULT_ABI == ABI_V4) |
3306 | sp_offset = info->total_size; | |
3307 | else if (TARGET_NEW_MNEMONICS) | |
4697a36c MM |
3308 | asm_fprintf (file, "\taddi %s,%s,%d\n", reg_names[1], reg_names[1], info->total_size); |
3309 | else | |
3310 | asm_fprintf (file, "\tcal %s,%d(%s)\n", reg_names[1], info->total_size, reg_names[1]); | |
3311 | } | |
9878760c | 3312 | |
b4ac57ab | 3313 | /* Get the old lr if we saved it. */ |
4697a36c | 3314 | if (info->lr_save_p) |
979721f8 | 3315 | asm_fprintf (file, load_reg, reg_names[0], info->lr_save_offset + sp_offset, reg_names[sp_reg]); |
9878760c RK |
3316 | |
3317 | /* Get the old cr if we saved it. */ | |
4697a36c | 3318 | if (info->cr_save_p) |
979721f8 | 3319 | asm_fprintf (file, load_reg, reg_names[12], info->cr_save_offset + sp_offset, reg_names[sp_reg]); |
9878760c | 3320 | |
b4ac57ab | 3321 | /* Set LR here to try to overlap restores below. */ |
4697a36c MM |
3322 | if (info->lr_save_p) |
3323 | asm_fprintf (file, "\tmtlr %s\n", reg_names[0]); | |
b4ac57ab | 3324 | |
9878760c | 3325 | /* Restore gpr's. */ |
4697a36c | 3326 | if (! TARGET_MULTIPLE || info->first_gp_reg_save == 31 || TARGET_64BIT) |
85638c0d | 3327 | { |
4697a36c | 3328 | int regno = info->first_gp_reg_save; |
979721f8 | 3329 | int loc = info->gp_save_offset + sp_offset; |
8f802bfb | 3330 | int reg_size = (TARGET_32BIT) ? 4 : 8; |
85638c0d | 3331 | |
4697a36c | 3332 | for ( ; regno < 32; regno++, loc += reg_size) |
979721f8 | 3333 | asm_fprintf (file, load_reg, reg_names[regno], loc, reg_names[sp_reg]); |
85638c0d RK |
3334 | } |
3335 | ||
4697a36c MM |
3336 | else if (info->first_gp_reg_save != 32) |
3337 | asm_fprintf (file, "\t{lm|lmw} %s,%d(%s)\n", | |
3338 | reg_names[info->first_gp_reg_save], | |
979721f8 MM |
3339 | info->gp_save_offset + sp_offset, |
3340 | reg_names[sp_reg]); | |
9878760c | 3341 | |
b4ac57ab | 3342 | /* Restore fpr's if we can do it without calling a function. */ |
4697a36c MM |
3343 | if (FP_SAVE_INLINE (info->first_fp_reg_save)) |
3344 | { | |
3345 | int regno = info->first_fp_reg_save; | |
979721f8 | 3346 | int loc = info->fp_save_offset + sp_offset; |
4697a36c MM |
3347 | |
3348 | for ( ; regno < 64; regno++, loc += 8) | |
979721f8 | 3349 | asm_fprintf (file, "\tlfd %s,%d(%s)\n", reg_names[regno], loc, reg_names[sp_reg]); |
4697a36c | 3350 | } |
9878760c | 3351 | |
28edebac RK |
3352 | /* If we saved cr, restore it here. Just those of cr2, cr3, and cr4 |
3353 | that were used. */ | |
4697a36c MM |
3354 | if (info->cr_save_p) |
3355 | asm_fprintf (file, "\tmtcrf %d,%s\n", | |
85638c0d RK |
3356 | (regs_ever_live[70] != 0) * 0x20 |
3357 | + (regs_ever_live[71] != 0) * 0x10 | |
4697a36c | 3358 | + (regs_ever_live[72] != 0) * 0x8, reg_names[12]); |
9878760c | 3359 | |
979721f8 MM |
3360 | /* If this is V.4, unwind the stack pointer after all of the loads have been done */ |
3361 | if (sp_offset) | |
3362 | { | |
3363 | if (TARGET_NEW_MNEMONICS) | |
3364 | asm_fprintf (file, "\taddi %s,%s,%d\n", reg_names[1], reg_names[1], sp_offset); | |
3365 | else | |
3366 | asm_fprintf (file, "\tcal %s,%d(%s)\n", reg_names[1], sp_offset, reg_names[1]); | |
3367 | } | |
3368 | else if (sp_reg != 1) | |
3369 | asm_fprintf (file, "\tmr %s,%s\n", reg_names[1], reg_names[sp_reg]); | |
3370 | ||
b4ac57ab RS |
3371 | /* If we have to restore more than two FP registers, branch to the |
3372 | restore function. It will return to our caller. */ | |
4697a36c MM |
3373 | if (info->first_fp_reg_save != 64 && !FP_SAVE_INLINE (info->first_fp_reg_save)) |
3374 | asm_fprintf (file, "\tb %s%d%s\n", RESTORE_FP_PREFIX, | |
3375 | info->first_fp_reg_save - 32, RESTORE_FP_SUFFIX); | |
b4ac57ab | 3376 | else |
85638c0d | 3377 | asm_fprintf (file, "\t{br|blr}\n"); |
9878760c | 3378 | } |
b4ac57ab | 3379 | |
9b30bae2 | 3380 | /* Output a traceback table here. See /usr/include/sys/debug.h for info |
314fc5a9 ILT |
3381 | on its format. |
3382 | ||
3383 | We don't output a traceback table if -finhibit-size-directive was | |
3384 | used. The documentation for -finhibit-size-directive reads | |
3385 | ``don't output a @code{.size} assembler directive, or anything | |
3386 | else that would cause trouble if the function is split in the | |
3387 | middle, and the two halves are placed at locations far apart in | |
3388 | memory.'' The traceback table has this property, since it | |
3389 | includes the offset from the start of the function to the | |
4d30c363 MM |
3390 | traceback table itself. |
3391 | ||
3392 | System V.4 Powerpc's (and the embedded ABI derived from it) use a | |
b6c9286a MM |
3393 | different traceback table. */ |
3394 | if (DEFAULT_ABI == ABI_AIX && ! flag_inhibit_size_directive) | |
9b30bae2 | 3395 | { |
314fc5a9 ILT |
3396 | char *fname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0); |
3397 | int fixed_parms, float_parms, parm_info; | |
3398 | int i; | |
3399 | ||
b6c9286a MM |
3400 | while (*fname == '.') /* V.4 encodes . in the name */ |
3401 | fname++; | |
3402 | ||
314fc5a9 ILT |
3403 | /* Need label immediately before tbtab, so we can compute its offset |
3404 | from the function start. */ | |
3405 | if (*fname == '*') | |
3406 | ++fname; | |
3407 | ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT"); | |
3408 | ASM_OUTPUT_LABEL (file, fname); | |
3409 | ||
3410 | /* The .tbtab pseudo-op can only be used for the first eight | |
3411 | expressions, since it can't handle the possibly variable | |
3412 | length fields that follow. However, if you omit the optional | |
3413 | fields, the assembler outputs zeros for all optional fields | |
3414 | anyways, giving each variable length field is minimum length | |
3415 | (as defined in sys/debug.h). Thus we can not use the .tbtab | |
3416 | pseudo-op at all. */ | |
3417 | ||
3418 | /* An all-zero word flags the start of the tbtab, for debuggers | |
3419 | that have to find it by searching forward from the entry | |
3420 | point or from the current pc. */ | |
19d2d16f | 3421 | fputs ("\t.long 0\n", file); |
314fc5a9 ILT |
3422 | |
3423 | /* Tbtab format type. Use format type 0. */ | |
19d2d16f | 3424 | fputs ("\t.byte 0,", file); |
314fc5a9 ILT |
3425 | |
3426 | /* Language type. Unfortunately, there doesn't seem to be any | |
3427 | official way to get this info, so we use language_string. C | |
3428 | is 0. C++ is 9. No number defined for Obj-C, so use the | |
3429 | value for C for now. */ | |
3430 | if (! strcmp (language_string, "GNU C") | |
3431 | || ! strcmp (language_string, "GNU Obj-C")) | |
3432 | i = 0; | |
3433 | else if (! strcmp (language_string, "GNU F77")) | |
3434 | i = 1; | |
3435 | else if (! strcmp (language_string, "GNU Ada")) | |
3436 | i = 3; | |
3437 | else if (! strcmp (language_string, "GNU PASCAL")) | |
3438 | i = 2; | |
3439 | else if (! strcmp (language_string, "GNU C++")) | |
3440 | i = 9; | |
3441 | else | |
3442 | abort (); | |
3443 | fprintf (file, "%d,", i); | |
3444 | ||
3445 | /* 8 single bit fields: global linkage (not set for C extern linkage, | |
3446 | apparently a PL/I convention?), out-of-line epilogue/prologue, offset | |
3447 | from start of procedure stored in tbtab, internal function, function | |
3448 | has controlled storage, function has no toc, function uses fp, | |
3449 | function logs/aborts fp operations. */ | |
3450 | /* Assume that fp operations are used if any fp reg must be saved. */ | |
4697a36c | 3451 | fprintf (file, "%d,", (1 << 5) | ((info->first_fp_reg_save != 64) << 1)); |
314fc5a9 ILT |
3452 | |
3453 | /* 6 bitfields: function is interrupt handler, name present in | |
3454 | proc table, function calls alloca, on condition directives | |
3455 | (controls stack walks, 3 bits), saves condition reg, saves | |
3456 | link reg. */ | |
3457 | /* The `function calls alloca' bit seems to be set whenever reg 31 is | |
3458 | set up as a frame pointer, even when there is no alloca call. */ | |
3459 | fprintf (file, "%d,", | |
3460 | ((1 << 6) | (frame_pointer_needed << 5) | |
4697a36c | 3461 | | (info->cr_save_p << 1) | (info->lr_save_p))); |
314fc5a9 ILT |
3462 | |
3463 | /* 3 bitfields: saves backchain, spare bit, number of fpr saved | |
3464 | (6 bits). */ | |
3465 | fprintf (file, "%d,", | |
4697a36c | 3466 | (info->push_p << 7) | (64 - info->first_fp_reg_save)); |
314fc5a9 ILT |
3467 | |
3468 | /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */ | |
3469 | fprintf (file, "%d,", (32 - first_reg_to_save ())); | |
3470 | ||
3471 | { | |
3472 | /* Compute the parameter info from the function decl argument | |
3473 | list. */ | |
3474 | tree decl; | |
3475 | int next_parm_info_bit; | |
3476 | ||
3477 | next_parm_info_bit = 31; | |
3478 | parm_info = 0; | |
3479 | fixed_parms = 0; | |
3480 | float_parms = 0; | |
3481 | ||
3482 | for (decl = DECL_ARGUMENTS (current_function_decl); | |
3483 | decl; decl = TREE_CHAIN (decl)) | |
3484 | { | |
3485 | rtx parameter = DECL_INCOMING_RTL (decl); | |
3486 | enum machine_mode mode = GET_MODE (parameter); | |
3487 | ||
3488 | if (GET_CODE (parameter) == REG) | |
3489 | { | |
3490 | if (GET_MODE_CLASS (mode) == MODE_FLOAT) | |
3491 | { | |
3492 | int bits; | |
3493 | ||
3494 | float_parms++; | |
3495 | ||
3496 | if (mode == SFmode) | |
3497 | bits = 0x2; | |
3498 | else if (mode == DFmode) | |
3499 | bits = 0x3; | |
3500 | else | |
3501 | abort (); | |
3502 | ||
3503 | /* If only one bit will fit, don't or in this entry. */ | |
3504 | if (next_parm_info_bit > 0) | |
3505 | parm_info |= (bits << (next_parm_info_bit - 1)); | |
3506 | next_parm_info_bit -= 2; | |
3507 | } | |
3508 | else | |
3509 | { | |
3510 | fixed_parms += ((GET_MODE_SIZE (mode) | |
3511 | + (UNITS_PER_WORD - 1)) | |
3512 | / UNITS_PER_WORD); | |
3513 | next_parm_info_bit -= 1; | |
3514 | } | |
3515 | } | |
3516 | } | |
3517 | } | |
3518 | ||
3519 | /* Number of fixed point parameters. */ | |
3520 | /* This is actually the number of words of fixed point parameters; thus | |
3521 | an 8 byte struct counts as 2; and thus the maximum value is 8. */ | |
3522 | fprintf (file, "%d,", fixed_parms); | |
3523 | ||
3524 | /* 2 bitfields: number of floating point parameters (7 bits), parameters | |
3525 | all on stack. */ | |
3526 | /* This is actually the number of fp registers that hold parameters; | |
3527 | and thus the maximum value is 13. */ | |
3528 | /* Set parameters on stack bit if parameters are not in their original | |
3529 | registers, regardless of whether they are on the stack? Xlc | |
3530 | seems to set the bit when not optimizing. */ | |
3531 | fprintf (file, "%d\n", ((float_parms << 1) | (! optimize))); | |
3532 | ||
3533 | /* Optional fields follow. Some are variable length. */ | |
3534 | ||
3535 | /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float, | |
3536 | 11 double float. */ | |
3537 | /* There is an entry for each parameter in a register, in the order that | |
3538 | they occur in the parameter list. Any intervening arguments on the | |
3539 | stack are ignored. If the list overflows a long (max possible length | |
3540 | 34 bits) then completely leave off all elements that don't fit. */ | |
3541 | /* Only emit this long if there was at least one parameter. */ | |
3542 | if (fixed_parms || float_parms) | |
3543 | fprintf (file, "\t.long %d\n", parm_info); | |
3544 | ||
3545 | /* Offset from start of code to tb table. */ | |
19d2d16f | 3546 | fputs ("\t.long ", file); |
314fc5a9 ILT |
3547 | ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT"); |
3548 | RS6000_OUTPUT_BASENAME (file, fname); | |
19d2d16f | 3549 | fputs ("-.", file); |
314fc5a9 | 3550 | RS6000_OUTPUT_BASENAME (file, fname); |
19d2d16f | 3551 | putc ('\n', file); |
314fc5a9 ILT |
3552 | |
3553 | /* Interrupt handler mask. */ | |
3554 | /* Omit this long, since we never set the interrupt handler bit | |
3555 | above. */ | |
3556 | ||
3557 | /* Number of CTL (controlled storage) anchors. */ | |
3558 | /* Omit this long, since the has_ctl bit is never set above. */ | |
3559 | ||
3560 | /* Displacement into stack of each CTL anchor. */ | |
3561 | /* Omit this list of longs, because there are no CTL anchors. */ | |
3562 | ||
3563 | /* Length of function name. */ | |
3564 | fprintf (file, "\t.short %d\n", strlen (fname)); | |
3565 | ||
3566 | /* Function name. */ | |
3567 | assemble_string (fname, strlen (fname)); | |
3568 | ||
3569 | /* Register for alloca automatic storage; this is always reg 31. | |
3570 | Only emit this if the alloca bit was set above. */ | |
3571 | if (frame_pointer_needed) | |
19d2d16f | 3572 | fputs ("\t.byte 31\n", file); |
9b30bae2 | 3573 | } |
4697a36c | 3574 | |
b6c9286a | 3575 | /* Reset varargs and save TOC indicator */ |
4697a36c | 3576 | rs6000_sysv_varargs_p = 0; |
b6c9286a MM |
3577 | rs6000_save_toc_p = 0; |
3578 | ||
3579 | if (DEFAULT_ABI == ABI_NT) | |
3580 | { | |
3581 | RS6000_OUTPUT_BASENAME (file, XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); | |
3582 | fputs (".e:\nFE_MOT_RESVD..", file); | |
3583 | RS6000_OUTPUT_BASENAME (file, XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); | |
3584 | fputs (":\n", file); | |
3585 | } | |
9878760c RK |
3586 | } |
3587 | \f | |
3588 | /* Output a TOC entry. We derive the entry name from what is | |
3589 | being written. */ | |
3590 | ||
3591 | void | |
3592 | output_toc (file, x, labelno) | |
3593 | FILE *file; | |
3594 | rtx x; | |
3595 | int labelno; | |
3596 | { | |
3597 | char buf[256]; | |
3598 | char *name = buf; | |
b6c9286a | 3599 | char *real_name; |
9878760c RK |
3600 | rtx base = x; |
3601 | int offset = 0; | |
3602 | ||
4697a36c MM |
3603 | if (TARGET_NO_TOC) |
3604 | abort (); | |
3605 | ||
ff1720ed RK |
3606 | /* if we're going to put a double constant in the TOC, make sure it's |
3607 | aligned properly when strict alignment is on. */ | |
3608 | if (GET_CODE (x) == CONST_DOUBLE | |
3609 | && STRICT_ALIGNMENT | |
3610 | && GET_MODE (x) == DFmode | |
3611 | && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC)) { | |
3612 | ASM_OUTPUT_ALIGN (file, 3); | |
3613 | } | |
3614 | ||
3615 | ||
b6c9286a | 3616 | if (TARGET_ELF && TARGET_MINIMAL_TOC) |
d14a6d05 MM |
3617 | { |
3618 | ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC"); | |
3619 | fprintf (file, "%d = .-", labelno); | |
3620 | ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LCTOC"); | |
19d2d16f | 3621 | fputs ("1\n", file); |
d14a6d05 MM |
3622 | } |
3623 | else | |
d14a6d05 | 3624 | ASM_OUTPUT_INTERNAL_LABEL (file, "LC", labelno); |
9878760c | 3625 | |
37c37a57 RK |
3626 | /* Handle FP constants specially. Note that if we have a minimal |
3627 | TOC, things we put here aren't actually in the TOC, so we can allow | |
3628 | FP constants. */ | |
042259f2 | 3629 | if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode |
37c37a57 | 3630 | && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC)) |
9878760c | 3631 | { |
042259f2 DE |
3632 | REAL_VALUE_TYPE rv; |
3633 | long k[2]; | |
0adc764e | 3634 | |
042259f2 DE |
3635 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); |
3636 | REAL_VALUE_TO_TARGET_DOUBLE (rv, k); | |
1875cc88 | 3637 | if (TARGET_MINIMAL_TOC) |
042259f2 | 3638 | fprintf (file, "\t.long %ld\n\t.long %ld\n", k[0], k[1]); |
1875cc88 | 3639 | else |
0adc764e | 3640 | fprintf (file, "\t.tc FD_%lx_%lx[TC],%ld,%ld\n", |
042259f2 | 3641 | k[0], k[1], k[0], k[1]); |
9878760c RK |
3642 | return; |
3643 | } | |
3644 | else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode | |
37c37a57 | 3645 | && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC)) |
9878760c | 3646 | { |
042259f2 DE |
3647 | REAL_VALUE_TYPE rv; |
3648 | long l; | |
9878760c | 3649 | |
042259f2 DE |
3650 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); |
3651 | REAL_VALUE_TO_TARGET_SINGLE (rv, l); | |
3652 | ||
3653 | if (TARGET_MINIMAL_TOC) | |
3654 | fprintf (file, "\t.long %d\n", l); | |
3655 | else | |
3656 | fprintf (file, "\t.tc FS_%x[TC],%d\n", l, l); | |
3657 | return; | |
3658 | } | |
3659 | else if (GET_MODE (x) == DImode | |
3660 | && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE) | |
3661 | && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC)) | |
3662 | { | |
3663 | HOST_WIDE_INT low; | |
3664 | HOST_WIDE_INT high; | |
3665 | ||
3666 | if (GET_CODE (x) == CONST_DOUBLE) | |
3667 | { | |
3668 | low = CONST_DOUBLE_LOW (x); | |
3669 | high = CONST_DOUBLE_HIGH (x); | |
3670 | } | |
3671 | else | |
3672 | #if HOST_BITS_PER_WIDE_INT == 32 | |
3673 | { | |
3674 | low = INTVAL (x); | |
3675 | high = (low < 0) ? ~0 : 0; | |
3676 | } | |
3677 | #else | |
3678 | { | |
3679 | low = INTVAL (x) & 0xffffffff; | |
3680 | high = (HOST_WIDE_INT) INTVAL (x) >> 32; | |
3681 | } | |
3682 | #endif | |
9878760c | 3683 | |
1875cc88 | 3684 | if (TARGET_MINIMAL_TOC) |
042259f2 | 3685 | fprintf (file, "\t.long %ld\n\t.long %ld\n", high, low); |
1875cc88 | 3686 | else |
042259f2 DE |
3687 | fprintf (file, "\t.tc ID_%lx_%lx[TC],%ld,%ld\n", |
3688 | high, low, high, low); | |
9878760c RK |
3689 | return; |
3690 | } | |
3691 | ||
3692 | if (GET_CODE (x) == CONST) | |
3693 | { | |
3694 | base = XEXP (XEXP (x, 0), 0); | |
3695 | offset = INTVAL (XEXP (XEXP (x, 0), 1)); | |
3696 | } | |
3697 | ||
3698 | if (GET_CODE (base) == SYMBOL_REF) | |
3699 | name = XSTR (base, 0); | |
3700 | else if (GET_CODE (base) == LABEL_REF) | |
3701 | ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (XEXP (base, 0))); | |
3702 | else if (GET_CODE (base) == CODE_LABEL) | |
3703 | ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (base)); | |
3704 | else | |
3705 | abort (); | |
3706 | ||
1875cc88 | 3707 | if (TARGET_MINIMAL_TOC) |
19d2d16f | 3708 | fputs ("\t.long ", file); |
1875cc88 JW |
3709 | else |
3710 | { | |
b6c9286a MM |
3711 | STRIP_NAME_ENCODING (real_name, name); |
3712 | fprintf (file, "\t.tc %s", real_name); | |
9878760c | 3713 | |
1875cc88 JW |
3714 | if (offset < 0) |
3715 | fprintf (file, ".N%d", - offset); | |
3716 | else if (offset) | |
3717 | fprintf (file, ".P%d", offset); | |
9878760c | 3718 | |
19d2d16f | 3719 | fputs ("[TC],", file); |
1875cc88 | 3720 | } |
9878760c | 3721 | output_addr_const (file, x); |
19d2d16f | 3722 | putc ('\n', file); |
9878760c RK |
3723 | } |
3724 | \f | |
3725 | /* Output an assembler pseudo-op to write an ASCII string of N characters | |
3726 | starting at P to FILE. | |
3727 | ||
3728 | On the RS/6000, we have to do this using the .byte operation and | |
3729 | write out special characters outside the quoted string. | |
3730 | Also, the assembler is broken; very long strings are truncated, | |
3731 | so we must artificially break them up early. */ | |
3732 | ||
3733 | void | |
3734 | output_ascii (file, p, n) | |
3735 | FILE *file; | |
3736 | char *p; | |
3737 | int n; | |
3738 | { | |
3739 | char c; | |
3740 | int i, count_string; | |
3741 | char *for_string = "\t.byte \""; | |
3742 | char *for_decimal = "\t.byte "; | |
3743 | char *to_close = NULL; | |
3744 | ||
3745 | count_string = 0; | |
3746 | for (i = 0; i < n; i++) | |
3747 | { | |
3748 | c = *p++; | |
3749 | if (c >= ' ' && c < 0177) | |
3750 | { | |
3751 | if (for_string) | |
3752 | fputs (for_string, file); | |
3753 | putc (c, file); | |
3754 | ||
3755 | /* Write two quotes to get one. */ | |
3756 | if (c == '"') | |
3757 | { | |
3758 | putc (c, file); | |
3759 | ++count_string; | |
3760 | } | |
3761 | ||
3762 | for_string = NULL; | |
3763 | for_decimal = "\"\n\t.byte "; | |
3764 | to_close = "\"\n"; | |
3765 | ++count_string; | |
3766 | ||
3767 | if (count_string >= 512) | |
3768 | { | |
3769 | fputs (to_close, file); | |
3770 | ||
3771 | for_string = "\t.byte \""; | |
3772 | for_decimal = "\t.byte "; | |
3773 | to_close = NULL; | |
3774 | count_string = 0; | |
3775 | } | |
3776 | } | |
3777 | else | |
3778 | { | |
3779 | if (for_decimal) | |
3780 | fputs (for_decimal, file); | |
3781 | fprintf (file, "%d", c); | |
3782 | ||
3783 | for_string = "\n\t.byte \""; | |
3784 | for_decimal = ", "; | |
3785 | to_close = "\n"; | |
3786 | count_string = 0; | |
3787 | } | |
3788 | } | |
3789 | ||
3790 | /* Now close the string if we have written one. Then end the line. */ | |
3791 | if (to_close) | |
3792 | fprintf (file, to_close); | |
3793 | } | |
3794 | \f | |
3795 | /* Generate a unique section name for FILENAME for a section type | |
3796 | represented by SECTION_DESC. Output goes into BUF. | |
3797 | ||
3798 | SECTION_DESC can be any string, as long as it is different for each | |
3799 | possible section type. | |
3800 | ||
3801 | We name the section in the same manner as xlc. The name begins with an | |
3802 | underscore followed by the filename (after stripping any leading directory | |
11e5fe42 RK |
3803 | names) with the last period replaced by the string SECTION_DESC. If |
3804 | FILENAME does not contain a period, SECTION_DESC is appended to the end of | |
3805 | the name. */ | |
9878760c RK |
3806 | |
3807 | void | |
3808 | rs6000_gen_section_name (buf, filename, section_desc) | |
3809 | char **buf; | |
3810 | char *filename; | |
3811 | char *section_desc; | |
3812 | { | |
11e5fe42 | 3813 | char *q, *after_last_slash, *last_period; |
9878760c RK |
3814 | char *p; |
3815 | int len; | |
9878760c RK |
3816 | |
3817 | after_last_slash = filename; | |
3818 | for (q = filename; *q; q++) | |
11e5fe42 RK |
3819 | { |
3820 | if (*q == '/') | |
3821 | after_last_slash = q + 1; | |
3822 | else if (*q == '.') | |
3823 | last_period = q; | |
3824 | } | |
9878760c | 3825 | |
11e5fe42 | 3826 | len = strlen (after_last_slash) + strlen (section_desc) + 2; |
9878760c RK |
3827 | *buf = (char *) permalloc (len); |
3828 | ||
3829 | p = *buf; | |
3830 | *p++ = '_'; | |
3831 | ||
3832 | for (q = after_last_slash; *q; q++) | |
3833 | { | |
11e5fe42 | 3834 | if (q == last_period) |
9878760c RK |
3835 | { |
3836 | strcpy (p, section_desc); | |
3837 | p += strlen (section_desc); | |
9878760c RK |
3838 | } |
3839 | ||
3840 | else if (isalnum (*q)) | |
3841 | *p++ = *q; | |
3842 | } | |
3843 | ||
11e5fe42 | 3844 | if (last_period == 0) |
9878760c RK |
3845 | strcpy (p, section_desc); |
3846 | else | |
3847 | *p = '\0'; | |
3848 | } | |
e165f3f0 RK |
3849 | \f |
3850 | /* Write function profiler code. */ | |
3851 | ||
3852 | void | |
3853 | output_function_profiler (file, labelno) | |
3854 | FILE *file; | |
3855 | int labelno; | |
3856 | { | |
3857 | /* The last used parameter register. */ | |
3858 | int last_parm_reg; | |
3859 | int i, j; | |
3daf36a4 | 3860 | char buf[100]; |
e165f3f0 | 3861 | |
b6c9286a MM |
3862 | if (DEFAULT_ABI != ABI_AIX) |
3863 | abort (); | |
3864 | ||
e165f3f0 RK |
3865 | /* Set up a TOC entry for the profiler label. */ |
3866 | toc_section (); | |
3daf36a4 ILT |
3867 | ASM_OUTPUT_INTERNAL_LABEL (file, "LPC", labelno); |
3868 | ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno); | |
35fc1624 | 3869 | if (TARGET_MINIMAL_TOC) |
3daf36a4 | 3870 | { |
19d2d16f | 3871 | fputs ("\t.long ", file); |
3daf36a4 | 3872 | assemble_name (file, buf); |
19d2d16f | 3873 | putc ('\n', file); |
3daf36a4 | 3874 | } |
35fc1624 | 3875 | else |
3daf36a4 | 3876 | { |
19d2d16f | 3877 | fputs ("\t.tc\t", file); |
3daf36a4 | 3878 | assemble_name (file, buf); |
19d2d16f | 3879 | fputs ("[TC],", file); |
3daf36a4 | 3880 | assemble_name (file, buf); |
19d2d16f | 3881 | putc ('\n', file); |
3daf36a4 | 3882 | } |
e165f3f0 RK |
3883 | text_section (); |
3884 | ||
3885 | /* Figure out last used parameter register. The proper thing to do is | |
3886 | to walk incoming args of the function. A function might have live | |
3887 | parameter registers even if it has no incoming args. */ | |
3888 | ||
3889 | for (last_parm_reg = 10; | |
3890 | last_parm_reg > 2 && ! regs_ever_live [last_parm_reg]; | |
3891 | last_parm_reg--) | |
3892 | ; | |
3893 | ||
3894 | /* Save parameter registers in regs 23-30. Don't overwrite reg 31, since | |
3895 | it might be set up as the frame pointer. */ | |
3896 | ||
3897 | for (i = 3, j = 30; i <= last_parm_reg; i++, j--) | |
19d2d16f | 3898 | asm_fprintf (file, "\tmr %d,%d\n", j, i); |
e165f3f0 RK |
3899 | |
3900 | /* Load location address into r3, and call mcount. */ | |
3901 | ||
3daf36a4 | 3902 | ASM_GENERATE_INTERNAL_LABEL (buf, "LPC", labelno); |
19d2d16f | 3903 | asm_fprintf (file, "\t{l|lwz} %s,", reg_names[3]); |
3daf36a4 | 3904 | assemble_name (file, buf); |
19d2d16f | 3905 | asm_fprintf (file, "(%s)\n\tbl .mcount\n", reg_names[2]); |
e165f3f0 RK |
3906 | |
3907 | /* Restore parameter registers. */ | |
3908 | ||
3909 | for (i = 3, j = 30; i <= last_parm_reg; i++, j--) | |
19d2d16f | 3910 | asm_fprintf (file, "\tmr %d,%d\n", i, j); |
e165f3f0 | 3911 | } |
a251ffd0 TG |
3912 | |
3913 | /* Adjust the cost of a scheduling dependency. Return the new cost of | |
3914 | a dependency LINK or INSN on DEP_INSN. COST is the current cost. */ | |
3915 | ||
3916 | int | |
a06faf84 | 3917 | rs6000_adjust_cost (insn, link, dep_insn, cost) |
a251ffd0 TG |
3918 | rtx insn; |
3919 | rtx link; | |
3920 | rtx dep_insn; | |
3921 | int cost; | |
3922 | { | |
3923 | if (! recog_memoized (insn)) | |
3924 | return 0; | |
3925 | ||
3926 | if (REG_NOTE_KIND (link) != 0) | |
3927 | return 0; | |
3928 | ||
3929 | if (REG_NOTE_KIND (link) == 0) | |
3930 | { | |
3931 | /* Data dependency; DEP_INSN writes a register that INSN reads some | |
3932 | cycles later. */ | |
3933 | ||
3934 | /* Tell the first scheduling pass about the latency between a mtctr | |
3935 | and bctr (and mtlr and br/blr). The first scheduling pass will not | |
3936 | know about this latency since the mtctr instruction, which has the | |
3937 | latency associated to it, will be generated by reload. */ | |
3938 | if (get_attr_type (insn) == TYPE_JMPREG) | |
3939 | return TARGET_POWER ? 5 : 4; | |
3940 | ||
3941 | /* Fall out to return default cost. */ | |
3942 | } | |
3943 | ||
3944 | return cost; | |
3945 | } | |
b6c9286a MM |
3946 | |
3947 | /* Return how many instructions the machine can issue per cycle */ | |
3948 | int get_issue_rate() | |
3949 | { | |
3950 | switch (rs6000_cpu_attr) { | |
3951 | case CPU_RIOS1: | |
3952 | return 3; /* ? */ | |
3953 | case CPU_RIOS2: | |
3954 | return 4; | |
3955 | case CPU_PPC601: | |
3956 | return 3; /* ? */ | |
b6c9286a MM |
3957 | case CPU_PPC603: |
3958 | return 2; | |
3959 | case CPU_PPC604: | |
3960 | return 4; | |
3961 | case CPU_PPC620: | |
3962 | return 4; | |
3963 | default: | |
3964 | return 1; | |
3965 | } | |
3966 | } | |
3967 | ||
3968 | \f | |
3969 | /* Output insns to flush the {data|instruction} caches after building a | |
3970 | trampoline. */ | |
3971 | ||
3972 | static void | |
3973 | rs6000_sync_trampoline (addr) | |
3974 | rtx addr; | |
3975 | { | |
3976 | enum machine_mode pmode = Pmode; | |
3977 | rtx reg = gen_reg_rtx (pmode); | |
3978 | rtx mem2; | |
3979 | rtx mem1; | |
3980 | int size = rs6000_trampoline_size (); | |
3981 | rtx (*sub_fcn) PROTO ((rtx, rtx, rtx)); | |
3982 | rtx (*cmp_fcn) PROTO ((rtx, rtx)); | |
3983 | rtx label; | |
3984 | ||
ac2a93a1 | 3985 | if (TARGET_32BIT) |
b6c9286a | 3986 | { |
ac2a93a1 DE |
3987 | sub_fcn = gen_subsi3; |
3988 | cmp_fcn = gen_cmpsi; | |
b6c9286a MM |
3989 | } |
3990 | else | |
3991 | { | |
ac2a93a1 DE |
3992 | sub_fcn = gen_subdi3; |
3993 | cmp_fcn = gen_cmpdi; | |
b6c9286a MM |
3994 | } |
3995 | ||
3996 | addr = force_reg (pmode, addr); | |
3997 | mem2 = gen_rtx (MEM, pmode, gen_rtx (PLUS, pmode, addr, reg)); | |
3998 | mem1 = gen_rtx (MEM, pmode, addr); | |
3999 | ||
4000 | /* Issue a loop of dcbst's to flush the data cache */ | |
4001 | emit_move_insn (reg, GEN_INT (size-4)); | |
4002 | label = gen_label_rtx (); | |
4003 | emit_label (label); | |
4004 | emit_insn (gen_dcbst (mem2, addr, reg)); | |
4005 | emit_insn ((*sub_fcn) (reg, reg, GEN_INT (4))); | |
4006 | emit_insn ((*cmp_fcn) (reg, const0_rtx)); | |
4007 | emit_jump_insn (gen_bgt (label)); | |
4008 | ||
4009 | /* Issue a sync after the dcbst's to let things settle down */ | |
4010 | emit_insn (gen_sync (mem1)); | |
4011 | ||
4012 | /* Issue a loop of icbi's to flush the instruction cache */ | |
4013 | emit_move_insn (reg, GEN_INT (size-4)); | |
4014 | label = gen_label_rtx (); | |
4015 | emit_label (label); | |
4016 | emit_insn (gen_icbi (mem2, addr, reg)); | |
4017 | emit_insn ((*sub_fcn) (reg, reg, GEN_INT (4))); | |
4018 | emit_insn ((*cmp_fcn) (reg, const0_rtx)); | |
4019 | emit_jump_insn (gen_bgt (label)); | |
4020 | ||
4021 | /* Issue a sync after the icbi's to let things settle down */ | |
4022 | emit_insn (gen_sync (mem1)); | |
4023 | ||
4024 | /* Finally issue an isync to synchronize the icache */ | |
4025 | emit_insn (gen_isync (mem1)); | |
4026 | } | |
4027 | ||
4028 | \f | |
4029 | /* Output assembler code for a block containing the constant parts | |
4030 | of a trampoline, leaving space for the variable parts. | |
4031 | ||
4032 | The trampoline should set the static chain pointer to value placed | |
4033 | into the trampoline and should branch to the specified routine. */ | |
4034 | ||
4035 | void | |
4036 | rs6000_trampoline_template (file) | |
4037 | FILE *file; | |
4038 | { | |
4039 | char *sc = reg_names[STATIC_CHAIN_REGNUM]; | |
4040 | char *r0 = reg_names[0]; | |
7c59dc5d | 4041 | char *r2 = reg_names[2]; |
b6c9286a MM |
4042 | |
4043 | switch (DEFAULT_ABI) | |
4044 | { | |
4045 | default: | |
4046 | abort (); | |
4047 | ||
4048 | /* Under AIX, this is not code at all, but merely a data area, | |
4049 | since that is the way all functions are called. The first word is | |
4050 | the address of the function, the second word is the TOC pointer (r2), | |
4051 | and the third word is the static chain value. */ | |
4052 | case ABI_AIX: | |
8f802bfb | 4053 | fprintf (file, "\t.long %s\n", (TARGET_32BIT) ? "0,0,0" : "0,0,0,0,0,0"); |
b6c9286a MM |
4054 | break; |
4055 | ||
4056 | ||
4057 | /* V.4/eabi function pointers are just a single pointer, so we need to | |
4058 | do the full gory code to load up the static chain. */ | |
4059 | case ABI_V4: | |
4060 | case ABI_AIX_NODESC: | |
4061 | if (STATIC_CHAIN_REGNUM == 0 || !TARGET_NEW_MNEMONICS) | |
4062 | abort (); | |
4063 | ||
8f802bfb | 4064 | if (TARGET_32BIT) |
b6c9286a MM |
4065 | { |
4066 | fprintf (file, "\tmflr %s\n", r0); /* offset 0 */ | |
4067 | fprintf (file, "\tbl .LTRAMP1\n"); /* offset 4 */ | |
4068 | fprintf (file, "\t.long 0,0\n"); /* offset 8 */ | |
4069 | fprintf (file, ".LTRAMP1:\n"); | |
4070 | fprintf (file, "\tmflr %s\n", sc); /* offset 20 */ | |
4071 | fprintf (file, "\tmtlr %s\n", r0); /* offset 24 */ | |
4072 | fprintf (file, "\tlwz %s,0(%s)\n", r0, sc); /* offset 28 */ | |
4073 | fprintf (file, "\tlwz %s,4(%s)\n", sc, sc); /* offset 32 */ | |
4074 | fprintf (file, "\tmtctr %s\n", r0); /* offset 36 */ | |
4075 | fprintf (file, "\tbctr\n"); /* offset 40 */ | |
4076 | } | |
8f802bfb DE |
4077 | else |
4078 | { | |
4079 | fprintf (file, "\tmflr %s\n", r0); /* offset 0 */ | |
4080 | fprintf (file, "\tbl .LTRAMP1\n"); /* offset 4 */ | |
4081 | fprintf (file, "\t.long 0,0,0,0\n"); /* offset 8 */ | |
4082 | fprintf (file, ".LTRAMP1:\n"); | |
4083 | fprintf (file, "\tmflr %s\n", sc); /* offset 28 */ | |
4084 | fprintf (file, "\tmtlr %s\n", r0); /* offset 32 */ | |
4085 | fprintf (file, "\tld %s,0(%s)\n", r0, sc); /* offset 36 */ | |
4086 | fprintf (file, "\tld %s,8(%s)\n", sc, sc); /* offset 40 */ | |
4087 | fprintf (file, "\tmtctr %s\n", r0); /* offset 44 */ | |
4088 | fprintf (file, "\tbctr\n"); /* offset 48 */ | |
4089 | } | |
b6c9286a MM |
4090 | break; |
4091 | ||
4092 | /* NT function pointers point to a two word area (real address, TOC) | |
4093 | which unfortunately does not include a static chain field. So we | |
7c59dc5d MM |
4094 | use the function field to point to ..LTRAMP1 and the toc field |
4095 | to point to the whole table. */ | |
b6c9286a | 4096 | case ABI_NT: |
7c59dc5d MM |
4097 | if (STATIC_CHAIN_REGNUM == 0 |
4098 | || STATIC_CHAIN_REGNUM == 2 | |
4099 | || TARGET_64BIT | |
4100 | || !TARGET_NEW_MNEMONICS) | |
b6c9286a MM |
4101 | abort (); |
4102 | ||
7c59dc5d MM |
4103 | fprintf (file, "\t.ualong 0\n"); /* offset 0 */ |
4104 | fprintf (file, "\t.ualong 0\n"); /* offset 4 */ | |
4105 | fprintf (file, "\t.ualong 0\n"); /* offset 8 */ | |
4106 | fprintf (file, "\t.ualong 0\n"); /* offset 12 */ | |
4107 | fprintf (file, "\t.ualong 0\n"); /* offset 16 */ | |
8bd04c56 | 4108 | fprintf (file, "..LTRAMP1..0:\n"); /* offset 20 */ |
7c59dc5d MM |
4109 | fprintf (file, "\tlwz %s,8(%s)\n", r0, r2); /* offset 24 */ |
4110 | fprintf (file, "\tlwz %s,12(%s)\n", sc, r2); /* offset 28 */ | |
4111 | fprintf (file, "\tmtctr %s\n", r0); /* offset 32 */ | |
4112 | fprintf (file, "\tlwz %s,16(%s)\n", r2, r2); /* offset 36 */ | |
4113 | fprintf (file, "\tbctr\n"); /* offset 40 */ | |
b6c9286a MM |
4114 | break; |
4115 | } | |
4116 | ||
4117 | return; | |
4118 | } | |
4119 | ||
4120 | /* Length in units of the trampoline for entering a nested function. */ | |
4121 | ||
4122 | int | |
4123 | rs6000_trampoline_size () | |
4124 | { | |
4125 | int ret = 0; | |
4126 | ||
4127 | switch (DEFAULT_ABI) | |
4128 | { | |
4129 | default: | |
4130 | abort (); | |
4131 | ||
4132 | case ABI_AIX: | |
8f802bfb | 4133 | ret = (TARGET_32BIT) ? 12 : 24; |
b6c9286a MM |
4134 | break; |
4135 | ||
4136 | case ABI_V4: | |
4137 | case ABI_AIX_NODESC: | |
03a7e1a5 | 4138 | ret = (TARGET_32BIT) ? 40 : 48; |
b6c9286a MM |
4139 | break; |
4140 | ||
4141 | case ABI_NT: | |
7c59dc5d | 4142 | ret = 20; |
b6c9286a MM |
4143 | break; |
4144 | } | |
4145 | ||
4146 | return ret; | |
4147 | } | |
4148 | ||
4149 | /* Emit RTL insns to initialize the variable parts of a trampoline. | |
4150 | FNADDR is an RTX for the address of the function's pure code. | |
4151 | CXT is an RTX for the static chain value for the function. */ | |
4152 | ||
4153 | void | |
4154 | rs6000_initialize_trampoline (addr, fnaddr, cxt) | |
4155 | rtx addr; | |
4156 | rtx fnaddr; | |
4157 | rtx cxt; | |
4158 | { | |
ac2a93a1 | 4159 | enum machine_mode pmode = Pmode; |
8bd04c56 MM |
4160 | int regsize = (TARGET_32BIT) ? 4 : 8; |
4161 | rtx ctx_reg = force_reg (pmode, cxt); | |
b6c9286a MM |
4162 | |
4163 | switch (DEFAULT_ABI) | |
4164 | { | |
4165 | default: | |
4166 | abort (); | |
4167 | ||
8bd04c56 MM |
4168 | /* Macros to shorten the code expansions below. */ |
4169 | #define MEM_DEREF(addr) gen_rtx (MEM, pmode, memory_address (pmode, addr)) | |
7c59dc5d MM |
4170 | #define MEM_PLUS(addr,offset) gen_rtx (MEM, pmode, memory_address (pmode, plus_constant (addr, offset))) |
4171 | ||
b6c9286a MM |
4172 | /* Under AIX, just build the 3 word function descriptor */ |
4173 | case ABI_AIX: | |
8bd04c56 MM |
4174 | { |
4175 | rtx fn_reg = gen_reg_rtx (pmode); | |
4176 | rtx toc_reg = gen_reg_rtx (pmode); | |
4177 | emit_move_insn (fn_reg, MEM_DEREF (fnaddr)); | |
4178 | emit_move_insn (toc_reg, MEM_PLUS (fnaddr, 4)); | |
4179 | emit_move_insn (MEM_DEREF (addr), fn_reg); | |
4180 | emit_move_insn (MEM_PLUS (addr, regsize), toc_reg); | |
4181 | emit_move_insn (MEM_PLUS (addr, 2*regsize), ctx_reg); | |
4182 | } | |
b6c9286a MM |
4183 | break; |
4184 | ||
4185 | /* Under V.4/eabi, update the two words after the bl to have the real | |
4186 | function address and the static chain. */ | |
4187 | case ABI_V4: | |
4188 | case ABI_AIX_NODESC: | |
8bd04c56 MM |
4189 | { |
4190 | rtx reg = gen_reg_rtx (pmode); | |
4191 | emit_move_insn (reg, fnaddr); | |
4192 | emit_move_insn (MEM_PLUS (addr, 8), reg); | |
4193 | emit_move_insn (MEM_PLUS (addr, 8 + regsize), ctx_reg); | |
4194 | rs6000_sync_trampoline (addr); | |
4195 | } | |
b6c9286a MM |
4196 | break; |
4197 | ||
8bd04c56 MM |
4198 | /* Under NT, update the first word to point to the ..LTRAMP1..0 header, |
4199 | the second word will point to the whole trampoline, third-fifth words | |
7c59dc5d | 4200 | will then have the real address, static chain, and toc value. */ |
b6c9286a | 4201 | case ABI_NT: |
8bd04c56 MM |
4202 | { |
4203 | rtx tramp_reg = gen_reg_rtx (pmode); | |
4204 | rtx fn_reg = gen_reg_rtx (pmode); | |
4205 | rtx toc_reg = gen_reg_rtx (pmode); | |
4206 | ||
4207 | emit_move_insn (tramp_reg, gen_rtx (SYMBOL_REF, pmode, "..LTRAMP1..0")); | |
4208 | addr = force_reg (pmode, addr); | |
4209 | emit_move_insn (fn_reg, MEM_DEREF (fnaddr)); | |
4210 | emit_move_insn (toc_reg, MEM_PLUS (fnaddr, regsize)); | |
4211 | emit_move_insn (MEM_DEREF (addr), tramp_reg); | |
4212 | emit_move_insn (MEM_PLUS (addr, regsize), addr); | |
4213 | emit_move_insn (MEM_PLUS (addr, 2*regsize), fn_reg); | |
4214 | emit_move_insn (MEM_PLUS (addr, 3*regsize), ctx_reg); | |
4215 | emit_move_insn (MEM_PLUS (addr, 4*regsize), gen_rtx (REG, pmode, 2)); | |
4216 | } | |
b6c9286a MM |
4217 | break; |
4218 | } | |
4219 | ||
4220 | return; | |
4221 | } | |
7509c759 MM |
4222 | |
4223 | \f | |
4224 | /* If defined, a C expression whose value is nonzero if IDENTIFIER | |
4225 | with arguments ARGS is a valid machine specific attribute for DECL. | |
4226 | The attributes in ATTRIBUTES have previously been assigned to DECL. */ | |
4227 | ||
4228 | int | |
4229 | rs6000_valid_decl_attribute_p (decl, attributes, identifier, args) | |
4230 | tree decl; | |
4231 | tree attributes; | |
4232 | tree identifier; | |
4233 | tree args; | |
4234 | { | |
4235 | return 0; | |
4236 | } | |
4237 | ||
4238 | /* If defined, a C expression whose value is nonzero if IDENTIFIER | |
4239 | with arguments ARGS is a valid machine specific attribute for TYPE. | |
4240 | The attributes in ATTRIBUTES have previously been assigned to TYPE. */ | |
4241 | ||
4242 | int | |
4243 | rs6000_valid_type_attribute_p (type, attributes, identifier, args) | |
4244 | tree type; | |
4245 | tree attributes; | |
4246 | tree identifier; | |
4247 | tree args; | |
4248 | { | |
4249 | if (TREE_CODE (type) != FUNCTION_TYPE | |
4250 | && TREE_CODE (type) != FIELD_DECL | |
4251 | && TREE_CODE (type) != TYPE_DECL) | |
4252 | return 0; | |
4253 | ||
6a4cee5f MM |
4254 | /* Longcall attribute says that the function is not within 2**26 bytes |
4255 | of the current function, and to do an indirect call. */ | |
4256 | if (is_attribute_p ("longcall", identifier)) | |
4257 | return (args == NULL_TREE); | |
4258 | ||
7509c759 MM |
4259 | if (DEFAULT_ABI == ABI_NT) |
4260 | { | |
4261 | /* Stdcall attribute says callee is responsible for popping arguments | |
4262 | if they are not variable. */ | |
4263 | if (is_attribute_p ("stdcall", identifier)) | |
4264 | return (args == NULL_TREE); | |
4265 | ||
4266 | /* Cdecl attribute says the callee is a normal C declaration */ | |
4267 | if (is_attribute_p ("cdecl", identifier)) | |
4268 | return (args == NULL_TREE); | |
4269 | ||
4270 | /* Dllimport attribute says says the caller is to call the function | |
4271 | indirectly through a __imp_<name> pointer. */ | |
4272 | if (is_attribute_p ("dllimport", identifier)) | |
4273 | return (args == NULL_TREE); | |
4274 | ||
4275 | /* Dllexport attribute says says the callee is to create a __imp_<name> | |
4276 | pointer. */ | |
4277 | if (is_attribute_p ("dllexport", identifier)) | |
4278 | return (args == NULL_TREE); | |
4279 | } | |
4280 | ||
4281 | return 0; | |
4282 | } | |
4283 | ||
4284 | /* If defined, a C expression whose value is zero if the attributes on | |
4285 | TYPE1 and TYPE2 are incompatible, one if they are compatible, and | |
4286 | two if they are nearly compatible (which causes a warning to be | |
4287 | generated). */ | |
4288 | ||
4289 | int | |
4290 | rs6000_comp_type_attributes (type1, type2) | |
4291 | tree type1; | |
4292 | tree type2; | |
4293 | { | |
4294 | return 1; | |
4295 | } | |
4296 | ||
4297 | /* If defined, a C statement that assigns default attributes to newly | |
4298 | defined TYPE. */ | |
4299 | ||
4300 | void | |
4301 | rs6000_set_default_type_attributes (type) | |
4302 | tree type; | |
4303 | { | |
4304 | } | |
4305 | ||
4306 | /* Return a dll import reference corresponding to to a call's SYMBOL_REF */ | |
4307 | struct rtx_def * | |
4308 | rs6000_dll_import_ref (call_ref) | |
4309 | rtx call_ref; | |
4310 | { | |
4311 | char *call_name; | |
4312 | int len; | |
4313 | char *p; | |
4314 | rtx reg1, reg2; | |
4315 | tree node; | |
4316 | ||
4317 | if (GET_CODE (call_ref) != SYMBOL_REF) | |
4318 | abort (); | |
4319 | ||
4320 | call_name = XSTR (call_ref, 0); | |
4321 | len = sizeof ("__imp_") + strlen (call_name); | |
4322 | p = alloca (len); | |
4323 | reg2 = gen_reg_rtx (Pmode); | |
4324 | ||
4325 | strcpy (p, "__imp_"); | |
4326 | strcat (p, call_name); | |
4327 | node = get_identifier (p); | |
4328 | ||
4329 | reg1 = force_reg (Pmode, gen_rtx (SYMBOL_REF, VOIDmode, IDENTIFIER_POINTER (node))); | |
4330 | emit_move_insn (reg2, gen_rtx (MEM, Pmode, reg1)); | |
4331 | ||
4332 | return reg2; | |
4333 | } | |
4334 | ||
6a4cee5f MM |
4335 | /* Return a reference suitable for calling a function with the longcall attribute. */ |
4336 | struct rtx_def * | |
4337 | rs6000_longcall_ref (call_ref) | |
4338 | rtx call_ref; | |
4339 | { | |
4340 | char *call_name; | |
4341 | int len; | |
4342 | char *p; | |
4343 | rtx reg1, reg2; | |
4344 | tree node; | |
4345 | ||
4346 | if (GET_CODE (call_ref) != SYMBOL_REF) | |
4347 | return call_ref; | |
4348 | ||
4349 | /* System V adds '.' to the internal name, so skip them. */ | |
4350 | call_name = XSTR (call_ref, 0); | |
4351 | if (*call_name == '.') | |
4352 | { | |
4353 | while (*call_name == '.') | |
4354 | call_name++; | |
4355 | ||
4356 | node = get_identifier (call_name); | |
4357 | call_ref = gen_rtx (SYMBOL_REF, VOIDmode, IDENTIFIER_POINTER (node)); | |
4358 | } | |
4359 | ||
4360 | return force_reg (Pmode, call_ref); | |
4361 | } | |
4362 | ||
7509c759 MM |
4363 | \f |
4364 | /* A C statement or statements to switch to the appropriate section | |
4365 | for output of RTX in mode MODE. You can assume that RTX is some | |
4366 | kind of constant in RTL. The argument MODE is redundant except in | |
4367 | the case of a `const_int' rtx. Select the section by calling | |
4368 | `text_section' or one of the alternatives for other sections. | |
4369 | ||
4370 | Do not define this macro if you put all constants in the read-only | |
4371 | data section. */ | |
4372 | ||
4373 | #ifdef USING_SVR4_H | |
4374 | ||
4375 | void | |
4376 | rs6000_select_rtx_section (mode, x) | |
4377 | enum machine_mode mode; | |
4378 | rtx x; | |
4379 | { | |
4380 | if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x)) | |
4381 | toc_section (); | |
7509c759 MM |
4382 | else |
4383 | const_section (); | |
4384 | } | |
4385 | ||
4386 | /* A C statement or statements to switch to the appropriate | |
4387 | section for output of DECL. DECL is either a `VAR_DECL' node | |
4388 | or a constant of some sort. RELOC indicates whether forming | |
4389 | the initial value of DECL requires link-time relocations. */ | |
4390 | ||
4391 | void | |
4392 | rs6000_select_section (decl, reloc) | |
4393 | tree decl; | |
4394 | int reloc; | |
4395 | { | |
4396 | int size = int_size_in_bytes (TREE_TYPE (decl)); | |
4397 | ||
4398 | if (TREE_CODE (decl) == STRING_CST) | |
4399 | { | |
88228c4b | 4400 | if (! flag_writable_strings) |
7509c759 | 4401 | const_section (); |
7509c759 MM |
4402 | else |
4403 | data_section (); | |
4404 | } | |
4405 | else if (TREE_CODE (decl) == VAR_DECL) | |
4406 | { | |
4407 | if ((flag_pic && reloc) | |
4408 | || !TREE_READONLY (decl) | |
4409 | || TREE_SIDE_EFFECTS (decl) | |
4410 | || !DECL_INITIAL (decl) | |
4411 | || (DECL_INITIAL (decl) != error_mark_node | |
4412 | && !TREE_CONSTANT (DECL_INITIAL (decl)))) | |
4413 | { | |
88228c4b | 4414 | if (TARGET_SDATA && (size > 0) && (size <= g_switch_value)) |
7509c759 MM |
4415 | sdata_section (); |
4416 | else | |
4417 | data_section (); | |
4418 | } | |
4419 | else | |
4420 | { | |
88228c4b | 4421 | if (TARGET_SDATA && (size > 0) && (size <= g_switch_value)) |
7509c759 MM |
4422 | sdata2_section (); |
4423 | else | |
4424 | const_section (); | |
4425 | } | |
4426 | } | |
4427 | else | |
4428 | const_section (); | |
4429 | } | |
4430 | #endif /* USING_SVR4_H */ |