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9878760c | 1 | /* Subroutines used for code generation on IBM RS/6000. |
9ebbca7d | 2 | Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, |
63b6e069 | 3 | 2000, 2001 Free Software Foundation, Inc. |
fab3bcc3 | 4 | Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) |
9878760c RK |
5 | |
6 | This file is part of GNU CC. | |
7 | ||
8 | GNU CC is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 2, or (at your option) | |
11 | any later version. | |
12 | ||
13 | GNU CC is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with GNU CC; see the file COPYING. If not, write to | |
c15c9075 RK |
20 | the Free Software Foundation, 59 Temple Place - Suite 330, |
21 | Boston, MA 02111-1307, USA. */ | |
9878760c | 22 | |
956d6950 | 23 | #include "config.h" |
c4d38ccb | 24 | #include "system.h" |
9878760c RK |
25 | #include "rtl.h" |
26 | #include "regs.h" | |
27 | #include "hard-reg-set.h" | |
28 | #include "real.h" | |
29 | #include "insn-config.h" | |
30 | #include "conditions.h" | |
9878760c RK |
31 | #include "insn-attr.h" |
32 | #include "flags.h" | |
33 | #include "recog.h" | |
9878760c | 34 | #include "obstack.h" |
9b30bae2 | 35 | #include "tree.h" |
dfafc897 | 36 | #include "expr.h" |
2fc1c679 | 37 | #include "optabs.h" |
2a430ec1 | 38 | #include "except.h" |
a7df97e6 | 39 | #include "function.h" |
296b8152 | 40 | #include "output.h" |
d5fa86ba | 41 | #include "basic-block.h" |
d0101753 | 42 | #include "integrate.h" |
296b8152 | 43 | #include "toplev.h" |
c8023011 | 44 | #include "ggc.h" |
9ebbca7d GK |
45 | #include "hashtab.h" |
46 | #include "tm_p.h" | |
672a6f42 NB |
47 | #include "target.h" |
48 | #include "target-def.h" | |
9b30bae2 | 49 | |
7509c759 MM |
50 | #ifndef TARGET_NO_PROTOTYPE |
51 | #define TARGET_NO_PROTOTYPE 0 | |
52 | #endif | |
53 | ||
5248c961 | 54 | extern int profile_block_flag; |
9878760c RK |
55 | |
56 | #define min(A,B) ((A) < (B) ? (A) : (B)) | |
57 | #define max(A,B) ((A) > (B) ? (A) : (B)) | |
58 | ||
5248c961 RK |
59 | /* Target cpu type */ |
60 | ||
61 | enum processor_type rs6000_cpu; | |
8e3f41e7 MM |
62 | struct rs6000_cpu_select rs6000_select[3] = |
63 | { | |
815cdc52 MM |
64 | /* switch name, tune arch */ |
65 | { (const char *)0, "--with-cpu=", 1, 1 }, | |
66 | { (const char *)0, "-mcpu=", 1, 1 }, | |
67 | { (const char *)0, "-mtune=", 1, 0 }, | |
8e3f41e7 | 68 | }; |
5248c961 | 69 | |
c764f757 RK |
70 | /* Set to non-zero once AIX common-mode calls have been defined. */ |
71 | static int common_mode_defined; | |
c81bebd7 | 72 | |
9878760c RK |
73 | /* Save information from a "cmpxx" operation until the branch or scc is |
74 | emitted. */ | |
9878760c RK |
75 | rtx rs6000_compare_op0, rs6000_compare_op1; |
76 | int rs6000_compare_fp_p; | |
874a0744 | 77 | |
874a0744 MM |
78 | /* Label number of label created for -mrelocatable, to call to so we can |
79 | get the address of the GOT section */ | |
80 | int rs6000_pic_labelno; | |
c81bebd7 | 81 | |
9ebbca7d | 82 | #ifdef USING_SVR4_H |
c81bebd7 | 83 | /* Which abi to adhere to */ |
815cdc52 | 84 | const char *rs6000_abi_name = RS6000_ABI_NAME; |
d9407988 MM |
85 | |
86 | /* Semantics of the small data area */ | |
87 | enum rs6000_sdata_type rs6000_sdata = SDATA_DATA; | |
88 | ||
89 | /* Which small data model to use */ | |
815cdc52 | 90 | const char *rs6000_sdata_name = (char *)0; |
9ebbca7d GK |
91 | |
92 | /* Counter for labels which are to be placed in .fixup. */ | |
93 | int fixuplabelno = 0; | |
874a0744 | 94 | #endif |
4697a36c | 95 | |
b6c9286a MM |
96 | /* ABI enumeration available for subtarget to use. */ |
97 | enum rs6000_abi rs6000_current_abi; | |
98 | ||
38c1f2d7 | 99 | /* Debug flags */ |
815cdc52 | 100 | const char *rs6000_debug_name; |
38c1f2d7 MM |
101 | int rs6000_debug_stack; /* debug stack applications */ |
102 | int rs6000_debug_arg; /* debug argument handling */ | |
103 | ||
104 | /* Flag to say the TOC is initialized */ | |
105 | int toc_initialized; | |
9ebbca7d | 106 | char toc_label_name[10]; |
38c1f2d7 | 107 | |
9ebbca7d GK |
108 | /* Alias set for saves and restores from the rs6000 stack. */ |
109 | static int rs6000_sr_alias_set; | |
c8023011 | 110 | |
9ebbca7d GK |
111 | static void rs6000_add_gc_roots PARAMS ((void)); |
112 | static int num_insns_constant_wide PARAMS ((HOST_WIDE_INT)); | |
113 | static rtx expand_block_move_mem PARAMS ((enum machine_mode, rtx, rtx)); | |
39a10a29 GK |
114 | static void validate_condition_mode |
115 | PARAMS ((enum rtx_code, enum machine_mode)); | |
116 | static rtx rs6000_generate_compare PARAMS ((enum rtx_code)); | |
e50f5f3d | 117 | static void rs6000_maybe_dead PARAMS ((rtx)); |
9ebbca7d GK |
118 | static void rs6000_emit_stack_tie PARAMS ((void)); |
119 | static void rs6000_frame_related PARAMS ((rtx, rtx, HOST_WIDE_INT, rtx, rtx)); | |
120 | static void rs6000_emit_allocate_stack PARAMS ((HOST_WIDE_INT, int)); | |
121 | static unsigned rs6000_hash_constant PARAMS ((rtx)); | |
122 | static unsigned toc_hash_function PARAMS ((const void *)); | |
123 | static int toc_hash_eq PARAMS ((const void *, const void *)); | |
2eba1afa | 124 | static int toc_hash_mark_entry PARAMS ((void **, void *)); |
9ebbca7d GK |
125 | static void toc_hash_mark_table PARAMS ((void *)); |
126 | static int constant_pool_expr_1 PARAMS ((rtx, int *, int *)); | |
6fee9e99 NC |
127 | static void rs6000_free_machine_status PARAMS ((struct function *)); |
128 | static void rs6000_init_machine_status PARAMS ((struct function *)); | |
71f123ca | 129 | static int rs6000_ra_ever_killed PARAMS ((void)); |
91d231cb JM |
130 | static tree rs6000_handle_longcall_attribute PARAMS ((tree *, tree, tree, int, bool *)); |
131 | const struct attribute_spec rs6000_attribute_table[]; | |
08c148a8 NB |
132 | static void rs6000_output_function_prologue PARAMS ((FILE *, HOST_WIDE_INT)); |
133 | static void rs6000_output_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT)); | |
2bfcf297 DB |
134 | static rtx rs6000_emit_set_long_const PARAMS ((rtx, |
135 | HOST_WIDE_INT, HOST_WIDE_INT)); | |
7c262518 RH |
136 | #if TARGET_ELF |
137 | static unsigned int rs6000_elf_section_type_flags PARAMS ((tree, const char *, | |
138 | int)); | |
d9f6800d RH |
139 | static void rs6000_elf_asm_out_constructor PARAMS ((rtx, int)); |
140 | static void rs6000_elf_asm_out_destructor PARAMS ((rtx, int)); | |
7c262518 RH |
141 | #endif |
142 | #ifdef OBJECT_FORMAT_COFF | |
715bdd29 | 143 | static void xcoff_asm_named_section PARAMS ((const char *, unsigned int)); |
7c262518 | 144 | #endif |
c237e94a ZW |
145 | static int rs6000_adjust_cost PARAMS ((rtx, rtx, rtx, int)); |
146 | static int rs6000_adjust_priority PARAMS ((rtx, int)); | |
147 | static int rs6000_issue_rate PARAMS ((void)); | |
148 | ||
c81bebd7 MM |
149 | \f |
150 | /* Default register names. */ | |
151 | char rs6000_reg_names[][8] = | |
152 | { | |
802a0058 MM |
153 | "0", "1", "2", "3", "4", "5", "6", "7", |
154 | "8", "9", "10", "11", "12", "13", "14", "15", | |
155 | "16", "17", "18", "19", "20", "21", "22", "23", | |
156 | "24", "25", "26", "27", "28", "29", "30", "31", | |
157 | "0", "1", "2", "3", "4", "5", "6", "7", | |
158 | "8", "9", "10", "11", "12", "13", "14", "15", | |
159 | "16", "17", "18", "19", "20", "21", "22", "23", | |
160 | "24", "25", "26", "27", "28", "29", "30", "31", | |
161 | "mq", "lr", "ctr","ap", | |
162 | "0", "1", "2", "3", "4", "5", "6", "7", | |
9ebbca7d | 163 | "xer" |
c81bebd7 MM |
164 | }; |
165 | ||
166 | #ifdef TARGET_REGNAMES | |
8b60264b | 167 | static const char alt_reg_names[][8] = |
c81bebd7 | 168 | { |
802a0058 MM |
169 | "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7", |
170 | "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15", | |
171 | "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23", | |
172 | "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31", | |
173 | "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7", | |
174 | "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15", | |
175 | "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23", | |
176 | "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31", | |
177 | "mq", "lr", "ctr", "ap", | |
178 | "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7", | |
9ebbca7d | 179 | "xer" |
c81bebd7 MM |
180 | }; |
181 | #endif | |
9878760c | 182 | \f |
daf11973 MM |
183 | #ifndef MASK_STRICT_ALIGN |
184 | #define MASK_STRICT_ALIGN 0 | |
185 | #endif | |
672a6f42 NB |
186 | \f |
187 | /* Initialize the GCC target structure. */ | |
91d231cb JM |
188 | #undef TARGET_ATTRIBUTE_TABLE |
189 | #define TARGET_ATTRIBUTE_TABLE rs6000_attribute_table | |
daf11973 | 190 | |
08c148a8 NB |
191 | #undef TARGET_ASM_FUNCTION_PROLOGUE |
192 | #define TARGET_ASM_FUNCTION_PROLOGUE rs6000_output_function_prologue | |
193 | #undef TARGET_ASM_FUNCTION_EPILOGUE | |
194 | #define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue | |
195 | ||
7c262518 RH |
196 | #if TARGET_ELF |
197 | #undef TARGET_SECTION_TYPE_FLAGS | |
198 | #define TARGET_SECTION_TYPE_FLAGS rs6000_elf_section_type_flags | |
199 | #endif | |
200 | ||
c237e94a ZW |
201 | #undef TARGET_SCHED_ISSUE_RATE |
202 | #define TARGET_SCHED_ISSUE_RATE rs6000_issue_rate | |
203 | #undef TARGET_SCHED_ADJUST_COST | |
204 | #define TARGET_SCHED_ADJUST_COST rs6000_adjust_cost | |
205 | #undef TARGET_SCHED_ADJUST_PRIORITY | |
206 | #define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority | |
207 | ||
f6897b10 | 208 | struct gcc_target targetm = TARGET_INITIALIZER; |
672a6f42 | 209 | \f |
5248c961 RK |
210 | /* Override command line options. Mostly we process the processor |
211 | type and sometimes adjust other TARGET_ options. */ | |
212 | ||
213 | void | |
8e3f41e7 | 214 | rs6000_override_options (default_cpu) |
d330fd93 | 215 | const char *default_cpu; |
5248c961 | 216 | { |
c4d38ccb | 217 | size_t i, j; |
8e3f41e7 | 218 | struct rs6000_cpu_select *ptr; |
5248c961 | 219 | |
85638c0d RK |
220 | /* Simplify the entries below by making a mask for any POWER |
221 | variant and any PowerPC variant. */ | |
222 | ||
938937d8 | 223 | #define POWER_MASKS (MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING) |
68c49ffa RK |
224 | #define POWERPC_MASKS (MASK_POWERPC | MASK_PPC_GPOPT \ |
225 | | MASK_PPC_GFXOPT | MASK_POWERPC64) | |
226 | #define POWERPC_OPT_MASKS (MASK_PPC_GPOPT | MASK_PPC_GFXOPT) | |
85638c0d | 227 | |
5248c961 RK |
228 | static struct ptt |
229 | { | |
8b60264b KG |
230 | const char *const name; /* Canonical processor name. */ |
231 | const enum processor_type processor; /* Processor type enum value. */ | |
232 | const int target_enable; /* Target flags to enable. */ | |
233 | const int target_disable; /* Target flags to disable. */ | |
234 | } const processor_target_table[] | |
cf27b467 MM |
235 | = {{"common", PROCESSOR_COMMON, MASK_NEW_MNEMONICS, |
236 | POWER_MASKS | POWERPC_MASKS}, | |
db7f1e43 | 237 | {"power", PROCESSOR_POWER, |
938937d8 | 238 | MASK_POWER | MASK_MULTIPLE | MASK_STRING, |
db7f1e43 | 239 | MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS}, |
8e3f41e7 MM |
240 | {"power2", PROCESSOR_POWER, |
241 | MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING, | |
242 | POWERPC_MASKS | MASK_NEW_MNEMONICS}, | |
c71791e0 DE |
243 | {"power3", PROCESSOR_PPC630, |
244 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, | |
245 | POWER_MASKS | MASK_PPC_GPOPT}, | |
db7f1e43 RK |
246 | {"powerpc", PROCESSOR_POWERPC, |
247 | MASK_POWERPC | MASK_NEW_MNEMONICS, | |
68c49ffa | 248 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}, |
3cb999d8 DE |
249 | {"powerpc64", PROCESSOR_POWERPC64, |
250 | MASK_POWERPC | MASK_POWERPC64 | MASK_NEW_MNEMONICS, | |
251 | POWER_MASKS | POWERPC_OPT_MASKS}, | |
db7f1e43 | 252 | {"rios", PROCESSOR_RIOS1, |
938937d8 | 253 | MASK_POWER | MASK_MULTIPLE | MASK_STRING, |
db7f1e43 RK |
254 | MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS}, |
255 | {"rios1", PROCESSOR_RIOS1, | |
938937d8 | 256 | MASK_POWER | MASK_MULTIPLE | MASK_STRING, |
db7f1e43 RK |
257 | MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS}, |
258 | {"rsc", PROCESSOR_PPC601, | |
938937d8 | 259 | MASK_POWER | MASK_MULTIPLE | MASK_STRING, |
db7f1e43 RK |
260 | MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS}, |
261 | {"rsc1", PROCESSOR_PPC601, | |
938937d8 | 262 | MASK_POWER | MASK_MULTIPLE | MASK_STRING, |
db7f1e43 RK |
263 | MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS}, |
264 | {"rios2", PROCESSOR_RIOS2, | |
938937d8 | 265 | MASK_POWER | MASK_MULTIPLE | MASK_STRING | MASK_POWER2, |
db7f1e43 | 266 | POWERPC_MASKS | MASK_NEW_MNEMONICS}, |
3cb999d8 DE |
267 | {"rs64a", PROCESSOR_RS64A, |
268 | MASK_POWERPC | MASK_NEW_MNEMONICS, | |
269 | POWER_MASKS | POWERPC_OPT_MASKS}, | |
a3a1dbf6 MM |
270 | {"401", PROCESSOR_PPC403, |
271 | MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS, | |
272 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}, | |
49a0b204 | 273 | {"403", PROCESSOR_PPC403, |
daf11973 | 274 | MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS | MASK_STRICT_ALIGN, |
49a0b204 | 275 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}, |
cf27b467 MM |
276 | {"505", PROCESSOR_MPCCORE, |
277 | MASK_POWERPC | MASK_NEW_MNEMONICS, | |
278 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}, | |
5248c961 | 279 | {"601", PROCESSOR_PPC601, |
938937d8 | 280 | MASK_POWER | MASK_POWERPC | MASK_NEW_MNEMONICS | MASK_MULTIPLE | MASK_STRING, |
68c49ffa | 281 | MASK_POWER2 | POWERPC_OPT_MASKS | MASK_POWERPC64}, |
1ec26da6 | 282 | {"602", PROCESSOR_PPC603, |
cf27b467 MM |
283 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, |
284 | POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}, | |
5248c961 | 285 | {"603", PROCESSOR_PPC603, |
68c49ffa RK |
286 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, |
287 | POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}, | |
b6c9286a MM |
288 | {"603e", PROCESSOR_PPC603, |
289 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, | |
290 | POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}, | |
b5370a88 | 291 | {"ec603e", PROCESSOR_PPC603, |
a3a1dbf6 MM |
292 | MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS, |
293 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}, | |
5248c961 | 294 | {"604", PROCESSOR_PPC604, |
b6c9286a MM |
295 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, |
296 | POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}, | |
cac8ce95 | 297 | {"604e", PROCESSOR_PPC604e, |
07e6159a MM |
298 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, |
299 | POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}, | |
b6c9286a | 300 | {"620", PROCESSOR_PPC620, |
68c49ffa | 301 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, |
a260abc9 | 302 | POWER_MASKS | MASK_PPC_GPOPT}, |
3cb999d8 DE |
303 | {"630", PROCESSOR_PPC630, |
304 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, | |
305 | POWER_MASKS | MASK_PPC_GPOPT}, | |
bef84347 VM |
306 | {"740", PROCESSOR_PPC750, |
307 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, | |
308 | POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}, | |
309 | {"750", PROCESSOR_PPC750, | |
310 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, | |
311 | POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}, | |
a4f6c312 SS |
312 | {"7400", PROCESSOR_PPC7400, |
313 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, | |
314 | POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}, | |
315 | {"7450", PROCESSOR_PPC7450, | |
316 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, | |
317 | POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}, | |
07e6159a MM |
318 | {"801", PROCESSOR_MPCCORE, |
319 | MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS, | |
320 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}, | |
cf27b467 MM |
321 | {"821", PROCESSOR_MPCCORE, |
322 | MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS, | |
323 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}, | |
07e6159a MM |
324 | {"823", PROCESSOR_MPCCORE, |
325 | MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS, | |
326 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}, | |
cf27b467 MM |
327 | {"860", PROCESSOR_MPCCORE, |
328 | MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS, | |
329 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}}; | |
5248c961 | 330 | |
c4d38ccb | 331 | size_t ptt_size = sizeof (processor_target_table) / sizeof (struct ptt); |
5248c961 | 332 | |
a4f6c312 SS |
333 | /* Save current -mmultiple/-mno-multiple status. */ |
334 | int multiple = TARGET_MULTIPLE; | |
335 | /* Save current -mstring/-mno-string status. */ | |
336 | int string = TARGET_STRING; | |
8a61d227 | 337 | |
5248c961 RK |
338 | profile_block_flag = 0; |
339 | ||
a4f6c312 | 340 | /* Identify the processor type. */ |
8e3f41e7 | 341 | rs6000_select[0].string = default_cpu; |
3cb999d8 | 342 | rs6000_cpu = TARGET_POWERPC64 ? PROCESSOR_DEFAULT64 : PROCESSOR_DEFAULT; |
8e3f41e7 | 343 | |
b6a1cbae | 344 | for (i = 0; i < ARRAY_SIZE (rs6000_select); i++) |
5248c961 | 345 | { |
8e3f41e7 MM |
346 | ptr = &rs6000_select[i]; |
347 | if (ptr->string != (char *)0 && ptr->string[0] != '\0') | |
5248c961 | 348 | { |
8e3f41e7 MM |
349 | for (j = 0; j < ptt_size; j++) |
350 | if (! strcmp (ptr->string, processor_target_table[j].name)) | |
351 | { | |
352 | if (ptr->set_tune_p) | |
353 | rs6000_cpu = processor_target_table[j].processor; | |
354 | ||
355 | if (ptr->set_arch_p) | |
356 | { | |
357 | target_flags |= processor_target_table[j].target_enable; | |
358 | target_flags &= ~processor_target_table[j].target_disable; | |
359 | } | |
360 | break; | |
361 | } | |
362 | ||
4406229e | 363 | if (j == ptt_size) |
8e3f41e7 | 364 | error ("bad value (%s) for %s switch", ptr->string, ptr->name); |
5248c961 RK |
365 | } |
366 | } | |
8a61d227 | 367 | |
a4f6c312 SS |
368 | /* If we are optimizing big endian systems for space, use the store |
369 | multiple instructions. */ | |
ef792183 MM |
370 | if (BYTES_BIG_ENDIAN && optimize_size) |
371 | target_flags |= MASK_MULTIPLE; | |
372 | ||
8a61d227 MM |
373 | /* If -mmultiple or -mno-multiple was explicitly used, don't |
374 | override with the processor default */ | |
375 | if (TARGET_MULTIPLE_SET) | |
376 | target_flags = (target_flags & ~MASK_MULTIPLE) | multiple; | |
7e69e155 | 377 | |
a4f6c312 SS |
378 | /* If -mstring or -mno-string was explicitly used, don't override |
379 | with the processor default. */ | |
938937d8 | 380 | if (TARGET_STRING_SET) |
1f5515bf | 381 | target_flags = (target_flags & ~MASK_STRING) | string; |
938937d8 | 382 | |
a4f6c312 SS |
383 | /* Don't allow -mmultiple or -mstring on little endian systems |
384 | unless the cpu is a 750, because the hardware doesn't support the | |
385 | instructions used in little endian mode, and causes an alignment | |
386 | trap. The 750 does not cause an alignment trap (except when the | |
387 | target is unaligned). */ | |
bef84347 | 388 | |
bfc79d3b | 389 | if (! BYTES_BIG_ENDIAN && rs6000_cpu != PROCESSOR_PPC750) |
7e69e155 MM |
390 | { |
391 | if (TARGET_MULTIPLE) | |
392 | { | |
393 | target_flags &= ~MASK_MULTIPLE; | |
394 | if (TARGET_MULTIPLE_SET) | |
395 | warning ("-mmultiple is not supported on little endian systems"); | |
396 | } | |
397 | ||
398 | if (TARGET_STRING) | |
399 | { | |
400 | target_flags &= ~MASK_STRING; | |
938937d8 MM |
401 | if (TARGET_STRING_SET) |
402 | warning ("-mstring is not supported on little endian systems"); | |
7e69e155 MM |
403 | } |
404 | } | |
3933e0e1 | 405 | |
2bfcf297 | 406 | if (flag_pic && DEFAULT_ABI == ABI_AIX) |
a260abc9 | 407 | { |
2bfcf297 | 408 | warning ("-f%s ignored (all code is position independent)", |
a260abc9 DE |
409 | (flag_pic > 1) ? "PIC" : "pic"); |
410 | flag_pic = 0; | |
411 | } | |
412 | ||
2bfcf297 | 413 | #ifdef XCOFF_DEBUGGING_INFO |
9861b0c9 | 414 | if (flag_function_sections && (write_symbols != NO_DEBUG) |
2bfcf297 | 415 | && DEFAULT_ABI == ABI_AIX) |
9861b0c9 DE |
416 | { |
417 | warning ("-ffunction-sections disabled on AIX when debugging"); | |
418 | flag_function_sections = 0; | |
419 | } | |
420 | ||
421 | if (flag_data_sections && (DEFAULT_ABI == ABI_AIX)) | |
422 | { | |
423 | warning ("-fdata-sections not supported on AIX"); | |
424 | flag_data_sections = 0; | |
425 | } | |
2bfcf297 | 426 | #endif |
9861b0c9 | 427 | |
38c1f2d7 MM |
428 | /* Set debug flags */ |
429 | if (rs6000_debug_name) | |
430 | { | |
bfc79d3b | 431 | if (! strcmp (rs6000_debug_name, "all")) |
38c1f2d7 | 432 | rs6000_debug_stack = rs6000_debug_arg = 1; |
bfc79d3b | 433 | else if (! strcmp (rs6000_debug_name, "stack")) |
38c1f2d7 | 434 | rs6000_debug_stack = 1; |
bfc79d3b | 435 | else if (! strcmp (rs6000_debug_name, "arg")) |
38c1f2d7 MM |
436 | rs6000_debug_arg = 1; |
437 | else | |
438 | error ("Unknown -mdebug-%s switch", rs6000_debug_name); | |
439 | } | |
440 | ||
c81bebd7 | 441 | #ifdef TARGET_REGNAMES |
a4f6c312 SS |
442 | /* If the user desires alternate register names, copy in the |
443 | alternate names now. */ | |
c81bebd7 | 444 | if (TARGET_REGNAMES) |
4e135bdd | 445 | memcpy (rs6000_reg_names, alt_reg_names, sizeof (rs6000_reg_names)); |
c81bebd7 MM |
446 | #endif |
447 | ||
3933e0e1 MM |
448 | #ifdef SUBTARGET_OVERRIDE_OPTIONS |
449 | SUBTARGET_OVERRIDE_OPTIONS; | |
450 | #endif | |
c8023011 MM |
451 | |
452 | /* Register global variables with the garbage collector. */ | |
453 | rs6000_add_gc_roots (); | |
9ebbca7d GK |
454 | |
455 | /* Allocate an alias set for register saves & restores from stack. */ | |
456 | rs6000_sr_alias_set = new_alias_set (); | |
457 | ||
458 | if (TARGET_TOC) | |
459 | ASM_GENERATE_INTERNAL_LABEL (toc_label_name, "LCTOC", 1); | |
71f123ca FS |
460 | |
461 | /* Arrange to save and restore machine status around nested functions. */ | |
462 | init_machine_status = rs6000_init_machine_status; | |
71f123ca | 463 | free_machine_status = rs6000_free_machine_status; |
5248c961 | 464 | } |
5accd822 DE |
465 | |
466 | void | |
467 | optimization_options (level, size) | |
e2c953b6 | 468 | int level ATTRIBUTE_UNUSED; |
5accd822 DE |
469 | int size ATTRIBUTE_UNUSED; |
470 | { | |
5accd822 | 471 | } |
3cfa4909 MM |
472 | \f |
473 | /* Do anything needed at the start of the asm file. */ | |
474 | ||
475 | void | |
476 | rs6000_file_start (file, default_cpu) | |
477 | FILE *file; | |
d330fd93 | 478 | const char *default_cpu; |
3cfa4909 | 479 | { |
c4d38ccb | 480 | size_t i; |
3cfa4909 | 481 | char buffer[80]; |
d330fd93 | 482 | const char *start = buffer; |
3cfa4909 MM |
483 | struct rs6000_cpu_select *ptr; |
484 | ||
485 | if (flag_verbose_asm) | |
486 | { | |
487 | sprintf (buffer, "\n%s rs6000/powerpc options:", ASM_COMMENT_START); | |
488 | rs6000_select[0].string = default_cpu; | |
489 | ||
b6a1cbae | 490 | for (i = 0; i < ARRAY_SIZE (rs6000_select); i++) |
3cfa4909 MM |
491 | { |
492 | ptr = &rs6000_select[i]; | |
493 | if (ptr->string != (char *)0 && ptr->string[0] != '\0') | |
494 | { | |
495 | fprintf (file, "%s %s%s", start, ptr->name, ptr->string); | |
496 | start = ""; | |
497 | } | |
498 | } | |
499 | ||
500 | #ifdef USING_SVR4_H | |
501 | switch (rs6000_sdata) | |
502 | { | |
503 | case SDATA_NONE: fprintf (file, "%s -msdata=none", start); start = ""; break; | |
504 | case SDATA_DATA: fprintf (file, "%s -msdata=data", start); start = ""; break; | |
505 | case SDATA_SYSV: fprintf (file, "%s -msdata=sysv", start); start = ""; break; | |
506 | case SDATA_EABI: fprintf (file, "%s -msdata=eabi", start); start = ""; break; | |
507 | } | |
508 | ||
509 | if (rs6000_sdata && g_switch_value) | |
510 | { | |
511 | fprintf (file, "%s -G %d", start, g_switch_value); | |
512 | start = ""; | |
513 | } | |
514 | #endif | |
515 | ||
516 | if (*start == '\0') | |
949ea356 | 517 | putc ('\n', file); |
3cfa4909 MM |
518 | } |
519 | } | |
520 | ||
24d304eb RK |
521 | \f |
522 | /* Create a CONST_DOUBLE from a string. */ | |
523 | ||
524 | struct rtx_def * | |
525 | rs6000_float_const (string, mode) | |
d330fd93 | 526 | const char *string; |
24d304eb RK |
527 | enum machine_mode mode; |
528 | { | |
ca5adc63 GK |
529 | REAL_VALUE_TYPE value; |
530 | value = REAL_VALUE_ATOF (string, mode); | |
24d304eb RK |
531 | return immed_real_const_1 (value, mode); |
532 | } | |
5248c961 | 533 | \f |
9878760c RK |
534 | /* Return non-zero if this function is known to have a null epilogue. */ |
535 | ||
536 | int | |
537 | direct_return () | |
538 | { | |
4697a36c MM |
539 | if (reload_completed) |
540 | { | |
541 | rs6000_stack_t *info = rs6000_stack_info (); | |
542 | ||
543 | if (info->first_gp_reg_save == 32 | |
544 | && info->first_fp_reg_save == 64 | |
c81fc13e DE |
545 | && ! info->lr_save_p |
546 | && ! info->cr_save_p | |
547 | && ! info->push_p) | |
4697a36c MM |
548 | return 1; |
549 | } | |
550 | ||
551 | return 0; | |
9878760c RK |
552 | } |
553 | ||
554 | /* Returns 1 always. */ | |
555 | ||
556 | int | |
557 | any_operand (op, mode) | |
592696dd | 558 | rtx op ATTRIBUTE_UNUSED; |
296b8152 | 559 | enum machine_mode mode ATTRIBUTE_UNUSED; |
9878760c RK |
560 | { |
561 | return 1; | |
562 | } | |
563 | ||
a4f6c312 | 564 | /* Returns 1 if op is the count register. */ |
38c1f2d7 | 565 | int |
a4f6c312 | 566 | count_register_operand (op, mode) |
592696dd | 567 | rtx op; |
296b8152 | 568 | enum machine_mode mode ATTRIBUTE_UNUSED; |
b6c9286a MM |
569 | { |
570 | if (GET_CODE (op) != REG) | |
571 | return 0; | |
572 | ||
573 | if (REGNO (op) == COUNT_REGISTER_REGNUM) | |
574 | return 1; | |
575 | ||
576 | if (REGNO (op) > FIRST_PSEUDO_REGISTER) | |
577 | return 1; | |
578 | ||
579 | return 0; | |
580 | } | |
581 | ||
38c1f2d7 | 582 | int |
a4f6c312 | 583 | xer_operand (op, mode) |
592696dd | 584 | rtx op; |
296b8152 | 585 | enum machine_mode mode ATTRIBUTE_UNUSED; |
802a0058 MM |
586 | { |
587 | if (GET_CODE (op) != REG) | |
588 | return 0; | |
589 | ||
9ebbca7d | 590 | if (XER_REGNO_P (REGNO (op))) |
802a0058 MM |
591 | return 1; |
592 | ||
802a0058 MM |
593 | return 0; |
594 | } | |
595 | ||
9878760c RK |
596 | /* Return 1 if OP is a constant that can fit in a D field. */ |
597 | ||
598 | int | |
599 | short_cint_operand (op, mode) | |
592696dd | 600 | rtx op; |
296b8152 | 601 | enum machine_mode mode ATTRIBUTE_UNUSED; |
9878760c | 602 | { |
5f59ecb7 DE |
603 | return (GET_CODE (op) == CONST_INT |
604 | && CONST_OK_FOR_LETTER_P (INTVAL (op), 'I')); | |
9878760c RK |
605 | } |
606 | ||
607 | /* Similar for a unsigned D field. */ | |
608 | ||
609 | int | |
610 | u_short_cint_operand (op, mode) | |
592696dd | 611 | rtx op; |
296b8152 | 612 | enum machine_mode mode ATTRIBUTE_UNUSED; |
9878760c | 613 | { |
19684119 | 614 | return (GET_CODE (op) == CONST_INT |
5f59ecb7 | 615 | && CONST_OK_FOR_LETTER_P (INTVAL (op), 'K')); |
9878760c RK |
616 | } |
617 | ||
dcfedcd0 RK |
618 | /* Return 1 if OP is a CONST_INT that cannot fit in a signed D field. */ |
619 | ||
620 | int | |
621 | non_short_cint_operand (op, mode) | |
592696dd | 622 | rtx op; |
296b8152 | 623 | enum machine_mode mode ATTRIBUTE_UNUSED; |
dcfedcd0 RK |
624 | { |
625 | return (GET_CODE (op) == CONST_INT | |
a7653a2c | 626 | && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x8000) >= 0x10000); |
dcfedcd0 RK |
627 | } |
628 | ||
2bfcf297 DB |
629 | /* Returns 1 if OP is a CONST_INT that is a positive value |
630 | and an exact power of 2. */ | |
631 | ||
632 | int | |
633 | exact_log2_cint_operand (op, mode) | |
592696dd | 634 | rtx op; |
2bfcf297 DB |
635 | enum machine_mode mode ATTRIBUTE_UNUSED; |
636 | { | |
637 | return (GET_CODE (op) == CONST_INT | |
638 | && INTVAL (op) > 0 | |
639 | && exact_log2 (INTVAL (op)) >= 0); | |
640 | } | |
641 | ||
9878760c RK |
642 | /* Returns 1 if OP is a register that is not special (i.e., not MQ, |
643 | ctr, or lr). */ | |
644 | ||
645 | int | |
cd2b37d9 | 646 | gpc_reg_operand (op, mode) |
592696dd | 647 | rtx op; |
9878760c RK |
648 | enum machine_mode mode; |
649 | { | |
650 | return (register_operand (op, mode) | |
802a0058 | 651 | && (GET_CODE (op) != REG |
9ebbca7d GK |
652 | || (REGNO (op) >= ARG_POINTER_REGNUM |
653 | && !XER_REGNO_P (REGNO (op))) | |
654 | || REGNO (op) < MQ_REGNO)); | |
9878760c RK |
655 | } |
656 | ||
657 | /* Returns 1 if OP is either a pseudo-register or a register denoting a | |
658 | CR field. */ | |
659 | ||
660 | int | |
661 | cc_reg_operand (op, mode) | |
592696dd | 662 | rtx op; |
9878760c RK |
663 | enum machine_mode mode; |
664 | { | |
665 | return (register_operand (op, mode) | |
666 | && (GET_CODE (op) != REG | |
667 | || REGNO (op) >= FIRST_PSEUDO_REGISTER | |
668 | || CR_REGNO_P (REGNO (op)))); | |
669 | } | |
670 | ||
815cdc52 MM |
671 | /* Returns 1 if OP is either a pseudo-register or a register denoting a |
672 | CR field that isn't CR0. */ | |
673 | ||
674 | int | |
675 | cc_reg_not_cr0_operand (op, mode) | |
592696dd | 676 | rtx op; |
815cdc52 MM |
677 | enum machine_mode mode; |
678 | { | |
679 | return (register_operand (op, mode) | |
680 | && (GET_CODE (op) != REG | |
681 | || REGNO (op) >= FIRST_PSEUDO_REGISTER | |
682 | || CR_REGNO_NOT_CR0_P (REGNO (op)))); | |
683 | } | |
684 | ||
a4f6c312 SS |
685 | /* Returns 1 if OP is either a constant integer valid for a D-field or |
686 | a non-special register. If a register, it must be in the proper | |
687 | mode unless MODE is VOIDmode. */ | |
9878760c RK |
688 | |
689 | int | |
690 | reg_or_short_operand (op, mode) | |
592696dd | 691 | rtx op; |
9878760c RK |
692 | enum machine_mode mode; |
693 | { | |
f5a28898 | 694 | return short_cint_operand (op, mode) || gpc_reg_operand (op, mode); |
9878760c RK |
695 | } |
696 | ||
a4f6c312 SS |
697 | /* Similar, except check if the negation of the constant would be |
698 | valid for a D-field. */ | |
9878760c RK |
699 | |
700 | int | |
701 | reg_or_neg_short_operand (op, mode) | |
592696dd | 702 | rtx op; |
9878760c RK |
703 | enum machine_mode mode; |
704 | { | |
705 | if (GET_CODE (op) == CONST_INT) | |
706 | return CONST_OK_FOR_LETTER_P (INTVAL (op), 'P'); | |
707 | ||
cd2b37d9 | 708 | return gpc_reg_operand (op, mode); |
9878760c RK |
709 | } |
710 | ||
a4f6c312 SS |
711 | /* Return 1 if the operand is either a register or an integer whose |
712 | high-order 16 bits are zero. */ | |
9878760c RK |
713 | |
714 | int | |
715 | reg_or_u_short_operand (op, mode) | |
592696dd | 716 | rtx op; |
9878760c RK |
717 | enum machine_mode mode; |
718 | { | |
e675f625 | 719 | return u_short_cint_operand (op, mode) || gpc_reg_operand (op, mode); |
9878760c RK |
720 | } |
721 | ||
722 | /* Return 1 is the operand is either a non-special register or ANY | |
723 | constant integer. */ | |
724 | ||
725 | int | |
726 | reg_or_cint_operand (op, mode) | |
592696dd | 727 | rtx op; |
9878760c RK |
728 | enum machine_mode mode; |
729 | { | |
a4f6c312 | 730 | return (GET_CODE (op) == CONST_INT || gpc_reg_operand (op, mode)); |
f6bf7de2 DE |
731 | } |
732 | ||
733 | /* Return 1 is the operand is either a non-special register or ANY | |
734 | 32-bit signed constant integer. */ | |
735 | ||
736 | int | |
737 | reg_or_arith_cint_operand (op, mode) | |
592696dd | 738 | rtx op; |
f6bf7de2 DE |
739 | enum machine_mode mode; |
740 | { | |
a4f6c312 SS |
741 | return (gpc_reg_operand (op, mode) |
742 | || (GET_CODE (op) == CONST_INT | |
f6bf7de2 | 743 | #if HOST_BITS_PER_WIDE_INT != 32 |
a4f6c312 SS |
744 | && ((unsigned HOST_WIDE_INT) (INTVAL (op) + 0x80000000) |
745 | < (unsigned HOST_WIDE_INT) 0x100000000ll) | |
f6bf7de2 | 746 | #endif |
a4f6c312 | 747 | )); |
9878760c RK |
748 | } |
749 | ||
2bfcf297 DB |
750 | /* Return 1 is the operand is either a non-special register or a 32-bit |
751 | signed constant integer valid for 64-bit addition. */ | |
752 | ||
753 | int | |
754 | reg_or_add_cint64_operand (op, mode) | |
592696dd | 755 | rtx op; |
2bfcf297 DB |
756 | enum machine_mode mode; |
757 | { | |
a4f6c312 SS |
758 | return (gpc_reg_operand (op, mode) |
759 | || (GET_CODE (op) == CONST_INT | |
760 | && INTVAL (op) < 0x7fff8000 | |
2bfcf297 | 761 | #if HOST_BITS_PER_WIDE_INT != 32 |
a4f6c312 SS |
762 | && ((unsigned HOST_WIDE_INT) (INTVAL (op) + 0x80008000) |
763 | < 0x100000000ll) | |
2bfcf297 | 764 | #endif |
a4f6c312 | 765 | )); |
2bfcf297 DB |
766 | } |
767 | ||
768 | /* Return 1 is the operand is either a non-special register or a 32-bit | |
769 | signed constant integer valid for 64-bit subtraction. */ | |
770 | ||
771 | int | |
772 | reg_or_sub_cint64_operand (op, mode) | |
592696dd | 773 | rtx op; |
2bfcf297 DB |
774 | enum machine_mode mode; |
775 | { | |
a4f6c312 SS |
776 | return (gpc_reg_operand (op, mode) |
777 | || (GET_CODE (op) == CONST_INT | |
778 | && (- INTVAL (op)) < 0x7fff8000 | |
2bfcf297 | 779 | #if HOST_BITS_PER_WIDE_INT != 32 |
a4f6c312 SS |
780 | && ((unsigned HOST_WIDE_INT) ((- INTVAL (op)) + 0x80008000) |
781 | < 0x100000000ll) | |
2bfcf297 | 782 | #endif |
a4f6c312 | 783 | )); |
2bfcf297 DB |
784 | } |
785 | ||
9ebbca7d GK |
786 | /* Return 1 is the operand is either a non-special register or ANY |
787 | 32-bit unsigned constant integer. */ | |
788 | ||
789 | int | |
1d328b19 | 790 | reg_or_logical_cint_operand (op, mode) |
592696dd | 791 | rtx op; |
9ebbca7d GK |
792 | enum machine_mode mode; |
793 | { | |
1d328b19 GK |
794 | if (GET_CODE (op) == CONST_INT) |
795 | { | |
796 | if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT) | |
797 | { | |
798 | if (GET_MODE_BITSIZE (mode) <= 32) | |
a4f6c312 | 799 | abort (); |
1d328b19 GK |
800 | |
801 | if (INTVAL (op) < 0) | |
802 | return 0; | |
803 | } | |
804 | ||
805 | return ((INTVAL (op) & GET_MODE_MASK (mode) | |
0858c623 | 806 | & (~ (unsigned HOST_WIDE_INT) 0xffffffff)) == 0); |
1d328b19 GK |
807 | } |
808 | else if (GET_CODE (op) == CONST_DOUBLE) | |
809 | { | |
810 | if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT | |
811 | || mode != DImode) | |
a4f6c312 | 812 | abort (); |
1d328b19 GK |
813 | |
814 | return CONST_DOUBLE_HIGH (op) == 0; | |
815 | } | |
816 | else | |
817 | return gpc_reg_operand (op, mode); | |
9ebbca7d GK |
818 | } |
819 | ||
51d3e7d6 | 820 | /* Return 1 if the operand is an operand that can be loaded via the GOT. */ |
766a866c MM |
821 | |
822 | int | |
823 | got_operand (op, mode) | |
592696dd | 824 | rtx op; |
296b8152 | 825 | enum machine_mode mode ATTRIBUTE_UNUSED; |
766a866c MM |
826 | { |
827 | return (GET_CODE (op) == SYMBOL_REF | |
828 | || GET_CODE (op) == CONST | |
829 | || GET_CODE (op) == LABEL_REF); | |
830 | } | |
831 | ||
38c1f2d7 MM |
832 | /* Return 1 if the operand is a simple references that can be loaded via |
833 | the GOT (labels involving addition aren't allowed). */ | |
834 | ||
835 | int | |
836 | got_no_const_operand (op, mode) | |
592696dd | 837 | rtx op; |
296b8152 | 838 | enum machine_mode mode ATTRIBUTE_UNUSED; |
38c1f2d7 MM |
839 | { |
840 | return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF); | |
841 | } | |
842 | ||
4e74d8ec MM |
843 | /* Return the number of instructions it takes to form a constant in an |
844 | integer register. */ | |
845 | ||
846 | static int | |
847 | num_insns_constant_wide (value) | |
848 | HOST_WIDE_INT value; | |
849 | { | |
850 | /* signed constant loadable with {cal|addi} */ | |
5f59ecb7 | 851 | if (CONST_OK_FOR_LETTER_P (value, 'I')) |
0865c631 GK |
852 | return 1; |
853 | ||
4e74d8ec | 854 | /* constant loadable with {cau|addis} */ |
5f59ecb7 | 855 | else if (CONST_OK_FOR_LETTER_P (value, 'L')) |
4e74d8ec MM |
856 | return 1; |
857 | ||
5f59ecb7 | 858 | #if HOST_BITS_PER_WIDE_INT == 64 |
c81fc13e | 859 | else if (TARGET_POWERPC64) |
4e74d8ec | 860 | { |
0d30d435 | 861 | HOST_WIDE_INT low = value & 0xffffffff; |
4e74d8ec MM |
862 | HOST_WIDE_INT high = value >> 32; |
863 | ||
0d30d435 DE |
864 | low = (low ^ 0x80000000) - 0x80000000; /* sign extend */ |
865 | ||
0858c623 | 866 | if (high == 0 && (low & 0x80000000) == 0) |
4e74d8ec MM |
867 | return 2; |
868 | ||
0858c623 | 869 | else if (high == -1 && (low & 0x80000000) != 0) |
4e74d8ec MM |
870 | return 2; |
871 | ||
c81fc13e | 872 | else if (! low) |
4e74d8ec MM |
873 | return num_insns_constant_wide (high) + 1; |
874 | ||
875 | else | |
876 | return (num_insns_constant_wide (high) | |
e396202a | 877 | + num_insns_constant_wide (low) + 1); |
4e74d8ec MM |
878 | } |
879 | #endif | |
880 | ||
881 | else | |
882 | return 2; | |
883 | } | |
884 | ||
885 | int | |
886 | num_insns_constant (op, mode) | |
887 | rtx op; | |
888 | enum machine_mode mode; | |
889 | { | |
4e74d8ec | 890 | if (GET_CODE (op) == CONST_INT) |
0d30d435 DE |
891 | { |
892 | #if HOST_BITS_PER_WIDE_INT == 64 | |
4e2c1c44 DE |
893 | if ((INTVAL (op) >> 31) != 0 && (INTVAL (op) >> 31) != -1 |
894 | && mask64_operand (op, mode)) | |
0d30d435 DE |
895 | return 2; |
896 | else | |
897 | #endif | |
898 | return num_insns_constant_wide (INTVAL (op)); | |
899 | } | |
4e74d8ec | 900 | |
6fc48950 MM |
901 | else if (GET_CODE (op) == CONST_DOUBLE && mode == SFmode) |
902 | { | |
903 | long l; | |
904 | REAL_VALUE_TYPE rv; | |
905 | ||
906 | REAL_VALUE_FROM_CONST_DOUBLE (rv, op); | |
907 | REAL_VALUE_TO_TARGET_SINGLE (rv, l); | |
908 | return num_insns_constant_wide ((HOST_WIDE_INT)l); | |
909 | } | |
910 | ||
47ad8c61 | 911 | else if (GET_CODE (op) == CONST_DOUBLE) |
4e74d8ec | 912 | { |
47ad8c61 MM |
913 | HOST_WIDE_INT low; |
914 | HOST_WIDE_INT high; | |
915 | long l[2]; | |
916 | REAL_VALUE_TYPE rv; | |
917 | int endian = (WORDS_BIG_ENDIAN == 0); | |
4e74d8ec | 918 | |
47ad8c61 MM |
919 | if (mode == VOIDmode || mode == DImode) |
920 | { | |
921 | high = CONST_DOUBLE_HIGH (op); | |
922 | low = CONST_DOUBLE_LOW (op); | |
923 | } | |
924 | else | |
925 | { | |
926 | REAL_VALUE_FROM_CONST_DOUBLE (rv, op); | |
927 | REAL_VALUE_TO_TARGET_DOUBLE (rv, l); | |
928 | high = l[endian]; | |
929 | low = l[1 - endian]; | |
930 | } | |
4e74d8ec | 931 | |
47ad8c61 MM |
932 | if (TARGET_32BIT) |
933 | return (num_insns_constant_wide (low) | |
934 | + num_insns_constant_wide (high)); | |
4e74d8ec MM |
935 | |
936 | else | |
47ad8c61 | 937 | { |
0858c623 | 938 | if (high == 0 && (low & 0x80000000) == 0) |
47ad8c61 MM |
939 | return num_insns_constant_wide (low); |
940 | ||
0858c623 | 941 | else if (high == -1 && (low & 0x80000000) != 0) |
47ad8c61 MM |
942 | return num_insns_constant_wide (low); |
943 | ||
a260abc9 DE |
944 | else if (mask64_operand (op, mode)) |
945 | return 2; | |
946 | ||
47ad8c61 MM |
947 | else if (low == 0) |
948 | return num_insns_constant_wide (high) + 1; | |
949 | ||
950 | else | |
951 | return (num_insns_constant_wide (high) | |
952 | + num_insns_constant_wide (low) + 1); | |
953 | } | |
4e74d8ec MM |
954 | } |
955 | ||
956 | else | |
957 | abort (); | |
958 | } | |
959 | ||
a4f6c312 SS |
960 | /* Return 1 if the operand is a CONST_DOUBLE and it can be put into a |
961 | register with one instruction per word. We only do this if we can | |
962 | safely read CONST_DOUBLE_{LOW,HIGH}. */ | |
9878760c RK |
963 | |
964 | int | |
965 | easy_fp_constant (op, mode) | |
592696dd SS |
966 | rtx op; |
967 | enum machine_mode mode; | |
9878760c | 968 | { |
9878760c RK |
969 | if (GET_CODE (op) != CONST_DOUBLE |
970 | || GET_MODE (op) != mode | |
4e74d8ec | 971 | || (GET_MODE_CLASS (mode) != MODE_FLOAT && mode != DImode)) |
9878760c RK |
972 | return 0; |
973 | ||
a4f6c312 | 974 | /* Consider all constants with -msoft-float to be easy. */ |
4e74d8ec | 975 | if (TARGET_SOFT_FLOAT && mode != DImode) |
b6c9286a MM |
976 | return 1; |
977 | ||
a4f6c312 | 978 | /* If we are using V.4 style PIC, consider all constants to be hard. */ |
a7273471 MM |
979 | if (flag_pic && (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS)) |
980 | return 0; | |
981 | ||
5ae4759c | 982 | #ifdef TARGET_RELOCATABLE |
a4f6c312 SS |
983 | /* Similarly if we are using -mrelocatable, consider all constants |
984 | to be hard. */ | |
5ae4759c MM |
985 | if (TARGET_RELOCATABLE) |
986 | return 0; | |
987 | #endif | |
988 | ||
042259f2 DE |
989 | if (mode == DFmode) |
990 | { | |
991 | long k[2]; | |
992 | REAL_VALUE_TYPE rv; | |
993 | ||
994 | REAL_VALUE_FROM_CONST_DOUBLE (rv, op); | |
995 | REAL_VALUE_TO_TARGET_DOUBLE (rv, k); | |
9878760c | 996 | |
4e74d8ec MM |
997 | return (num_insns_constant_wide ((HOST_WIDE_INT)k[0]) == 1 |
998 | && num_insns_constant_wide ((HOST_WIDE_INT)k[1]) == 1); | |
042259f2 | 999 | } |
4e74d8ec MM |
1000 | |
1001 | else if (mode == SFmode) | |
042259f2 DE |
1002 | { |
1003 | long l; | |
1004 | REAL_VALUE_TYPE rv; | |
1005 | ||
1006 | REAL_VALUE_FROM_CONST_DOUBLE (rv, op); | |
1007 | REAL_VALUE_TO_TARGET_SINGLE (rv, l); | |
9878760c | 1008 | |
4e74d8ec | 1009 | return num_insns_constant_wide (l) == 1; |
042259f2 | 1010 | } |
4e74d8ec | 1011 | |
a260abc9 | 1012 | else if (mode == DImode) |
c81fc13e | 1013 | return ((TARGET_POWERPC64 |
a260abc9 DE |
1014 | && GET_CODE (op) == CONST_DOUBLE && CONST_DOUBLE_LOW (op) == 0) |
1015 | || (num_insns_constant (op, DImode) <= 2)); | |
4e74d8ec | 1016 | |
a9098fd0 GK |
1017 | else if (mode == SImode) |
1018 | return 1; | |
4e74d8ec MM |
1019 | else |
1020 | abort (); | |
9878760c | 1021 | } |
8f75773e | 1022 | |
50a0b056 GK |
1023 | /* Return 1 if the operand is 0.0. */ |
1024 | int | |
1025 | zero_fp_constant (op, mode) | |
592696dd SS |
1026 | rtx op; |
1027 | enum machine_mode mode; | |
50a0b056 GK |
1028 | { |
1029 | return GET_MODE_CLASS (mode) == MODE_FLOAT && op == CONST0_RTX (mode); | |
1030 | } | |
1031 | ||
a4f6c312 SS |
1032 | /* Return 1 if the operand is in volatile memory. Note that during |
1033 | the RTL generation phase, memory_operand does not return TRUE for | |
b6c9286a MM |
1034 | volatile memory references. So this function allows us to |
1035 | recognize volatile references where its safe. */ | |
1036 | ||
1037 | int | |
1038 | volatile_mem_operand (op, mode) | |
592696dd | 1039 | rtx op; |
b6c9286a MM |
1040 | enum machine_mode mode; |
1041 | { | |
1042 | if (GET_CODE (op) != MEM) | |
1043 | return 0; | |
1044 | ||
1045 | if (!MEM_VOLATILE_P (op)) | |
1046 | return 0; | |
1047 | ||
1048 | if (mode != GET_MODE (op)) | |
1049 | return 0; | |
1050 | ||
1051 | if (reload_completed) | |
1052 | return memory_operand (op, mode); | |
1053 | ||
1054 | if (reload_in_progress) | |
1055 | return strict_memory_address_p (mode, XEXP (op, 0)); | |
1056 | ||
1057 | return memory_address_p (mode, XEXP (op, 0)); | |
1058 | } | |
1059 | ||
97f6e72f | 1060 | /* Return 1 if the operand is an offsettable memory operand. */ |
914c2e77 RK |
1061 | |
1062 | int | |
97f6e72f | 1063 | offsettable_mem_operand (op, mode) |
592696dd | 1064 | rtx op; |
914c2e77 RK |
1065 | enum machine_mode mode; |
1066 | { | |
97f6e72f | 1067 | return ((GET_CODE (op) == MEM) |
677a9668 | 1068 | && offsettable_address_p (reload_completed || reload_in_progress, |
97f6e72f | 1069 | mode, XEXP (op, 0))); |
914c2e77 RK |
1070 | } |
1071 | ||
9878760c RK |
1072 | /* Return 1 if the operand is either an easy FP constant (see above) or |
1073 | memory. */ | |
1074 | ||
1075 | int | |
1076 | mem_or_easy_const_operand (op, mode) | |
592696dd | 1077 | rtx op; |
9878760c RK |
1078 | enum machine_mode mode; |
1079 | { | |
1080 | return memory_operand (op, mode) || easy_fp_constant (op, mode); | |
1081 | } | |
1082 | ||
1083 | /* Return 1 if the operand is either a non-special register or an item | |
5f59ecb7 | 1084 | that can be used as the operand of a `mode' add insn. */ |
9878760c RK |
1085 | |
1086 | int | |
1087 | add_operand (op, mode) | |
592696dd | 1088 | rtx op; |
9878760c RK |
1089 | enum machine_mode mode; |
1090 | { | |
2bfcf297 DB |
1091 | if (GET_CODE (op) == CONST_INT) |
1092 | return (CONST_OK_FOR_LETTER_P (INTVAL(op), 'I') | |
1093 | || CONST_OK_FOR_LETTER_P (INTVAL(op), 'L')); | |
1094 | ||
1095 | return gpc_reg_operand (op, mode); | |
9878760c RK |
1096 | } |
1097 | ||
dcfedcd0 RK |
1098 | /* Return 1 if OP is a constant but not a valid add_operand. */ |
1099 | ||
1100 | int | |
1101 | non_add_cint_operand (op, mode) | |
592696dd | 1102 | rtx op; |
296b8152 | 1103 | enum machine_mode mode ATTRIBUTE_UNUSED; |
dcfedcd0 RK |
1104 | { |
1105 | return (GET_CODE (op) == CONST_INT | |
a7653a2c | 1106 | && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x8000) >= 0x10000 |
38886f37 | 1107 | && ! CONST_OK_FOR_LETTER_P (INTVAL (op), 'L')); |
dcfedcd0 RK |
1108 | } |
1109 | ||
9878760c RK |
1110 | /* Return 1 if the operand is a non-special register or a constant that |
1111 | can be used as the operand of an OR or XOR insn on the RS/6000. */ | |
1112 | ||
1113 | int | |
1114 | logical_operand (op, mode) | |
592696dd | 1115 | rtx op; |
9878760c RK |
1116 | enum machine_mode mode; |
1117 | { | |
40501e5f | 1118 | HOST_WIDE_INT opl, oph; |
1d328b19 | 1119 | |
dfbdccdb GK |
1120 | if (gpc_reg_operand (op, mode)) |
1121 | return 1; | |
1d328b19 | 1122 | |
dfbdccdb | 1123 | if (GET_CODE (op) == CONST_INT) |
40501e5f AM |
1124 | { |
1125 | opl = INTVAL (op) & GET_MODE_MASK (mode); | |
1126 | ||
1127 | #if HOST_BITS_PER_WIDE_INT <= 32 | |
1128 | if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT && opl < 0) | |
1129 | return 0; | |
1130 | #endif | |
1131 | } | |
dfbdccdb GK |
1132 | else if (GET_CODE (op) == CONST_DOUBLE) |
1133 | { | |
1d328b19 | 1134 | if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT) |
40501e5f | 1135 | abort (); |
1d328b19 GK |
1136 | |
1137 | opl = CONST_DOUBLE_LOW (op); | |
1138 | oph = CONST_DOUBLE_HIGH (op); | |
40501e5f | 1139 | if (oph != 0) |
38886f37 | 1140 | return 0; |
dfbdccdb GK |
1141 | } |
1142 | else | |
1143 | return 0; | |
1d328b19 | 1144 | |
40501e5f AM |
1145 | return ((opl & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0 |
1146 | || (opl & ~ (unsigned HOST_WIDE_INT) 0xffff0000) == 0); | |
9878760c RK |
1147 | } |
1148 | ||
dcfedcd0 | 1149 | /* Return 1 if C is a constant that is not a logical operand (as |
1d328b19 | 1150 | above), but could be split into one. */ |
dcfedcd0 RK |
1151 | |
1152 | int | |
1153 | non_logical_cint_operand (op, mode) | |
592696dd | 1154 | rtx op; |
5f59ecb7 | 1155 | enum machine_mode mode; |
dcfedcd0 | 1156 | { |
dfbdccdb | 1157 | return ((GET_CODE (op) == CONST_INT || GET_CODE (op) == CONST_DOUBLE) |
1d328b19 GK |
1158 | && ! logical_operand (op, mode) |
1159 | && reg_or_logical_cint_operand (op, mode)); | |
dcfedcd0 RK |
1160 | } |
1161 | ||
19ba8161 | 1162 | /* Return 1 if C is a constant that can be encoded in a 32-bit mask on the |
9878760c RK |
1163 | RS/6000. It is if there are no more than two 1->0 or 0->1 transitions. |
1164 | Reject all ones and all zeros, since these should have been optimized | |
1165 | away and confuse the making of MB and ME. */ | |
1166 | ||
1167 | int | |
19ba8161 | 1168 | mask_operand (op, mode) |
592696dd | 1169 | rtx op; |
19ba8161 | 1170 | enum machine_mode mode ATTRIBUTE_UNUSED; |
9878760c | 1171 | { |
02071907 | 1172 | HOST_WIDE_INT c, lsb; |
9878760c | 1173 | |
19ba8161 DE |
1174 | if (GET_CODE (op) != CONST_INT) |
1175 | return 0; | |
1176 | ||
1177 | c = INTVAL (op); | |
1178 | ||
c5059423 AM |
1179 | /* We don't change the number of transitions by inverting, |
1180 | so make sure we start with the LS bit zero. */ | |
1181 | if (c & 1) | |
1182 | c = ~c; | |
1183 | ||
1184 | /* Reject all zeros or all ones. */ | |
1185 | if (c == 0) | |
9878760c RK |
1186 | return 0; |
1187 | ||
c5059423 AM |
1188 | /* Find the first transition. */ |
1189 | lsb = c & -c; | |
1190 | ||
1191 | /* Invert to look for a second transition. */ | |
1192 | c = ~c; | |
9878760c | 1193 | |
c5059423 AM |
1194 | /* Erase first transition. */ |
1195 | c &= -lsb; | |
9878760c | 1196 | |
c5059423 AM |
1197 | /* Find the second transition (if any). */ |
1198 | lsb = c & -c; | |
1199 | ||
1200 | /* Match if all the bits above are 1's (or c is zero). */ | |
1201 | return c == -lsb; | |
9878760c RK |
1202 | } |
1203 | ||
a260abc9 DE |
1204 | /* Return 1 if the operand is a constant that is a PowerPC64 mask. |
1205 | It is if there are no more than one 1->0 or 0->1 transitions. | |
1206 | Reject all ones and all zeros, since these should have been optimized | |
1207 | away and confuse the making of MB and ME. */ | |
9878760c RK |
1208 | |
1209 | int | |
a260abc9 | 1210 | mask64_operand (op, mode) |
592696dd | 1211 | rtx op; |
a260abc9 DE |
1212 | enum machine_mode mode; |
1213 | { | |
1214 | if (GET_CODE (op) == CONST_INT) | |
1215 | { | |
02071907 | 1216 | HOST_WIDE_INT c, lsb; |
a260abc9 | 1217 | |
c5059423 AM |
1218 | /* We don't change the number of transitions by inverting, |
1219 | so make sure we start with the LS bit zero. */ | |
1220 | c = INTVAL (op); | |
1221 | if (c & 1) | |
1222 | c = ~c; | |
a260abc9 | 1223 | |
c5059423 AM |
1224 | /* Reject all zeros or all ones. */ |
1225 | if (c == 0) | |
e2c953b6 DE |
1226 | return 0; |
1227 | ||
c5059423 AM |
1228 | /* Find the transition, and check that all bits above are 1's. */ |
1229 | lsb = c & -c; | |
1230 | return c == -lsb; | |
e2c953b6 | 1231 | } |
a260abc9 DE |
1232 | else if (GET_CODE (op) == CONST_DOUBLE |
1233 | && (mode == VOIDmode || mode == DImode)) | |
1234 | { | |
02071907 | 1235 | HOST_WIDE_INT low, high, lsb; |
a260abc9 | 1236 | |
c5059423 AM |
1237 | if (HOST_BITS_PER_WIDE_INT < 64) |
1238 | high = CONST_DOUBLE_HIGH (op); | |
a260abc9 | 1239 | |
c5059423 AM |
1240 | low = CONST_DOUBLE_LOW (op); |
1241 | if (low & 1) | |
1242 | { | |
1243 | if (HOST_BITS_PER_WIDE_INT < 64) | |
1244 | high = ~high; | |
1245 | low = ~low; | |
1246 | } | |
a260abc9 | 1247 | |
c5059423 AM |
1248 | if (low == 0) |
1249 | { | |
1250 | if (HOST_BITS_PER_WIDE_INT >= 64 || high == 0) | |
1251 | return 0; | |
a260abc9 | 1252 | |
c5059423 AM |
1253 | lsb = high & -high; |
1254 | return high == -lsb; | |
1255 | } | |
a260abc9 | 1256 | |
c5059423 AM |
1257 | lsb = low & -low; |
1258 | return low == -lsb && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0); | |
a260abc9 DE |
1259 | } |
1260 | else | |
1261 | return 0; | |
1262 | } | |
1263 | ||
1264 | /* Return 1 if the operand is either a non-special register or a constant | |
1265 | that can be used as the operand of a PowerPC64 logical AND insn. */ | |
1266 | ||
1267 | int | |
1268 | and64_operand (op, mode) | |
592696dd | 1269 | rtx op; |
9878760c RK |
1270 | enum machine_mode mode; |
1271 | { | |
a4f6c312 | 1272 | if (fixed_regs[CR0_REGNO]) /* CR0 not available, don't do andi./andis. */ |
52d3af72 DE |
1273 | return (gpc_reg_operand (op, mode) || mask64_operand (op, mode)); |
1274 | ||
1275 | return (logical_operand (op, mode) || mask64_operand (op, mode)); | |
9878760c RK |
1276 | } |
1277 | ||
a260abc9 DE |
1278 | /* Return 1 if the operand is either a non-special register or a |
1279 | constant that can be used as the operand of an RS/6000 logical AND insn. */ | |
dcfedcd0 RK |
1280 | |
1281 | int | |
a260abc9 | 1282 | and_operand (op, mode) |
592696dd | 1283 | rtx op; |
a260abc9 | 1284 | enum machine_mode mode; |
dcfedcd0 | 1285 | { |
a4f6c312 | 1286 | if (fixed_regs[CR0_REGNO]) /* CR0 not available, don't do andi./andis. */ |
52d3af72 DE |
1287 | return (gpc_reg_operand (op, mode) || mask_operand (op, mode)); |
1288 | ||
1289 | return (logical_operand (op, mode) || mask_operand (op, mode)); | |
dcfedcd0 RK |
1290 | } |
1291 | ||
9878760c RK |
1292 | /* Return 1 if the operand is a general register or memory operand. */ |
1293 | ||
1294 | int | |
1295 | reg_or_mem_operand (op, mode) | |
592696dd SS |
1296 | rtx op; |
1297 | enum machine_mode mode; | |
9878760c | 1298 | { |
b6c9286a MM |
1299 | return (gpc_reg_operand (op, mode) |
1300 | || memory_operand (op, mode) | |
1301 | || volatile_mem_operand (op, mode)); | |
9878760c RK |
1302 | } |
1303 | ||
a7a813f7 | 1304 | /* Return 1 if the operand is a general register or memory operand without |
3cb999d8 | 1305 | pre_inc or pre_dec which produces invalid form of PowerPC lwa |
a7a813f7 RK |
1306 | instruction. */ |
1307 | ||
1308 | int | |
1309 | lwa_operand (op, mode) | |
592696dd SS |
1310 | rtx op; |
1311 | enum machine_mode mode; | |
a7a813f7 RK |
1312 | { |
1313 | rtx inner = op; | |
1314 | ||
1315 | if (reload_completed && GET_CODE (inner) == SUBREG) | |
1316 | inner = SUBREG_REG (inner); | |
1317 | ||
1318 | return gpc_reg_operand (inner, mode) | |
1319 | || (memory_operand (inner, mode) | |
1320 | && GET_CODE (XEXP (inner, 0)) != PRE_INC | |
6a40a9d6 DE |
1321 | && GET_CODE (XEXP (inner, 0)) != PRE_DEC |
1322 | && (GET_CODE (XEXP (inner, 0)) != PLUS | |
e903c96a DE |
1323 | || GET_CODE (XEXP (XEXP (inner, 0), 1)) != CONST_INT |
1324 | || INTVAL (XEXP (XEXP (inner, 0), 1)) % 4 == 0)); | |
a7a813f7 RK |
1325 | } |
1326 | ||
9878760c RK |
1327 | /* Return 1 if the operand, used inside a MEM, is a valid first argument |
1328 | to CALL. This is a SYMBOL_REF or a pseudo-register, which will be | |
1329 | forced to lr. */ | |
1330 | ||
1331 | int | |
1332 | call_operand (op, mode) | |
592696dd | 1333 | rtx op; |
9878760c RK |
1334 | enum machine_mode mode; |
1335 | { | |
1336 | if (mode != VOIDmode && GET_MODE (op) != mode) | |
1337 | return 0; | |
1338 | ||
1339 | return (GET_CODE (op) == SYMBOL_REF | |
1340 | || (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER)); | |
1341 | } | |
1342 | ||
2af3d377 | 1343 | /* Return 1 if the operand is a SYMBOL_REF for a function known to be in |
a4f6c312 | 1344 | this file and the function is not weakly defined. */ |
2af3d377 RK |
1345 | |
1346 | int | |
1347 | current_file_function_operand (op, mode) | |
592696dd | 1348 | rtx op; |
296b8152 | 1349 | enum machine_mode mode ATTRIBUTE_UNUSED; |
2af3d377 RK |
1350 | { |
1351 | return (GET_CODE (op) == SYMBOL_REF | |
1352 | && (SYMBOL_REF_FLAG (op) | |
8f1b829e | 1353 | || (op == XEXP (DECL_RTL (current_function_decl), 0) |
c81fc13e | 1354 | && ! DECL_WEAK (current_function_decl)))); |
2af3d377 RK |
1355 | } |
1356 | ||
9878760c RK |
1357 | /* Return 1 if this operand is a valid input for a move insn. */ |
1358 | ||
1359 | int | |
1360 | input_operand (op, mode) | |
592696dd | 1361 | rtx op; |
9878760c RK |
1362 | enum machine_mode mode; |
1363 | { | |
eb4e8003 | 1364 | /* Memory is always valid. */ |
9878760c RK |
1365 | if (memory_operand (op, mode)) |
1366 | return 1; | |
1367 | ||
34792e82 | 1368 | /* Only a tiny bit of handling for CONSTANT_P_RTX is necessary. */ |
01b4cf2b | 1369 | if (GET_CODE (op) == CONSTANT_P_RTX) |
34792e82 JL |
1370 | return 1; |
1371 | ||
eb4e8003 RK |
1372 | /* For floating-point, easy constants are valid. */ |
1373 | if (GET_MODE_CLASS (mode) == MODE_FLOAT | |
1374 | && CONSTANT_P (op) | |
1375 | && easy_fp_constant (op, mode)) | |
1376 | return 1; | |
1377 | ||
4e74d8ec MM |
1378 | /* Allow any integer constant. */ |
1379 | if (GET_MODE_CLASS (mode) == MODE_INT | |
e675f625 | 1380 | && (GET_CODE (op) == CONST_INT |
e675f625 | 1381 | || GET_CODE (op) == CONST_DOUBLE)) |
4e74d8ec MM |
1382 | return 1; |
1383 | ||
eb4e8003 RK |
1384 | /* For floating-point or multi-word mode, the only remaining valid type |
1385 | is a register. */ | |
9878760c RK |
1386 | if (GET_MODE_CLASS (mode) == MODE_FLOAT |
1387 | || GET_MODE_SIZE (mode) > UNITS_PER_WORD) | |
eb4e8003 | 1388 | return register_operand (op, mode); |
9878760c | 1389 | |
88fe15a1 RK |
1390 | /* The only cases left are integral modes one word or smaller (we |
1391 | do not get called for MODE_CC values). These can be in any | |
1392 | register. */ | |
1393 | if (register_operand (op, mode)) | |
a8b3aeda | 1394 | return 1; |
88fe15a1 | 1395 | |
84cf9dda | 1396 | /* A SYMBOL_REF referring to the TOC is valid. */ |
7fec4abd | 1397 | if (LEGITIMATE_CONSTANT_POOL_ADDRESS_P (op)) |
84cf9dda RK |
1398 | return 1; |
1399 | ||
9ebbca7d GK |
1400 | /* A constant pool expression (relative to the TOC) is valid */ |
1401 | if (TOC_RELATIVE_EXPR_P (op)) | |
b6c9286a MM |
1402 | return 1; |
1403 | ||
88228c4b MM |
1404 | /* V.4 allows SYMBOL_REFs and CONSTs that are in the small data region |
1405 | to be valid. */ | |
c81bebd7 | 1406 | if ((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) |
88228c4b MM |
1407 | && (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST) |
1408 | && small_data_operand (op, Pmode)) | |
1409 | return 1; | |
1410 | ||
042259f2 | 1411 | return 0; |
9878760c | 1412 | } |
7509c759 | 1413 | |
a4f6c312 | 1414 | /* Return 1 for an operand in small memory on V.4/eabi. */ |
7509c759 MM |
1415 | |
1416 | int | |
1417 | small_data_operand (op, mode) | |
296b8152 KG |
1418 | rtx op ATTRIBUTE_UNUSED; |
1419 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
7509c759 | 1420 | { |
38c1f2d7 | 1421 | #if TARGET_ELF |
5f59ecb7 | 1422 | rtx sym_ref; |
7509c759 | 1423 | |
d9407988 | 1424 | if (rs6000_sdata == SDATA_NONE || rs6000_sdata == SDATA_DATA) |
a54d04b7 | 1425 | return 0; |
a54d04b7 | 1426 | |
5b9d9a0c | 1427 | if (DEFAULT_ABI != ABI_V4 && DEFAULT_ABI != ABI_SOLARIS) |
7509c759 MM |
1428 | return 0; |
1429 | ||
88228c4b MM |
1430 | if (GET_CODE (op) == SYMBOL_REF) |
1431 | sym_ref = op; | |
1432 | ||
1433 | else if (GET_CODE (op) != CONST | |
1434 | || GET_CODE (XEXP (op, 0)) != PLUS | |
1435 | || GET_CODE (XEXP (XEXP (op, 0), 0)) != SYMBOL_REF | |
1436 | || GET_CODE (XEXP (XEXP (op, 0), 1)) != CONST_INT) | |
7509c759 MM |
1437 | return 0; |
1438 | ||
88228c4b | 1439 | else |
dbf55e53 MM |
1440 | { |
1441 | rtx sum = XEXP (op, 0); | |
1442 | HOST_WIDE_INT summand; | |
1443 | ||
1444 | /* We have to be careful here, because it is the referenced address | |
1445 | that must be 32k from _SDA_BASE_, not just the symbol. */ | |
1446 | summand = INTVAL (XEXP (sum, 1)); | |
1447 | if (summand < 0 || summand > g_switch_value) | |
1448 | return 0; | |
1449 | ||
1450 | sym_ref = XEXP (sum, 0); | |
1451 | } | |
88228c4b MM |
1452 | |
1453 | if (*XSTR (sym_ref, 0) != '@') | |
7509c759 MM |
1454 | return 0; |
1455 | ||
1456 | return 1; | |
d9407988 MM |
1457 | |
1458 | #else | |
1459 | return 0; | |
1460 | #endif | |
7509c759 | 1461 | } |
9ebbca7d GK |
1462 | \f |
1463 | static int | |
1464 | constant_pool_expr_1 (op, have_sym, have_toc) | |
1465 | rtx op; | |
1466 | int *have_sym; | |
1467 | int *have_toc; | |
1468 | { | |
1469 | switch (GET_CODE(op)) | |
1470 | { | |
1471 | case SYMBOL_REF: | |
a4f6c312 SS |
1472 | if (CONSTANT_POOL_ADDRESS_P (op)) |
1473 | { | |
1474 | if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (op), Pmode)) | |
1475 | { | |
1476 | *have_sym = 1; | |
1477 | return 1; | |
1478 | } | |
1479 | else | |
1480 | return 0; | |
1481 | } | |
1482 | else if (! strcmp (XSTR (op, 0), toc_label_name)) | |
1483 | { | |
1484 | *have_toc = 1; | |
1485 | return 1; | |
1486 | } | |
1487 | else | |
1488 | return 0; | |
9ebbca7d GK |
1489 | case PLUS: |
1490 | case MINUS: | |
a4f6c312 SS |
1491 | return constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc) && |
1492 | constant_pool_expr_1 (XEXP (op, 1), have_sym, have_toc); | |
9ebbca7d | 1493 | case CONST: |
a4f6c312 | 1494 | return constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc); |
9ebbca7d | 1495 | case CONST_INT: |
a4f6c312 | 1496 | return 1; |
9ebbca7d | 1497 | default: |
a4f6c312 | 1498 | return 0; |
9ebbca7d GK |
1499 | } |
1500 | } | |
1501 | ||
1502 | int | |
1503 | constant_pool_expr_p (op) | |
1504 | rtx op; | |
1505 | { | |
1506 | int have_sym = 0; | |
1507 | int have_toc = 0; | |
1508 | return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_sym; | |
1509 | } | |
1510 | ||
1511 | int | |
1512 | toc_relative_expr_p (op) | |
1513 | rtx op; | |
1514 | { | |
1515 | int have_sym = 0; | |
1516 | int have_toc = 0; | |
1517 | return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_toc; | |
1518 | } | |
1519 | ||
1520 | /* Try machine-dependent ways of modifying an illegitimate address | |
1521 | to be legitimate. If we find one, return the new, valid address. | |
1522 | This is used from only one place: `memory_address' in explow.c. | |
1523 | ||
a4f6c312 SS |
1524 | OLDX is the address as it was before break_out_memory_refs was |
1525 | called. In some cases it is useful to look at this to decide what | |
1526 | needs to be done. | |
9ebbca7d | 1527 | |
a4f6c312 | 1528 | MODE is passed so that this function can use GO_IF_LEGITIMATE_ADDRESS. |
9ebbca7d | 1529 | |
a4f6c312 SS |
1530 | It is always safe for this function to do nothing. It exists to |
1531 | recognize opportunities to optimize the output. | |
9ebbca7d GK |
1532 | |
1533 | On RS/6000, first check for the sum of a register with a constant | |
1534 | integer that is out of range. If so, generate code to add the | |
1535 | constant with the low-order 16 bits masked to the register and force | |
1536 | this result into another register (this can be done with `cau'). | |
1537 | Then generate an address of REG+(CONST&0xffff), allowing for the | |
1538 | possibility of bit 16 being a one. | |
1539 | ||
1540 | Then check for the sum of a register and something not constant, try to | |
1541 | load the other things into a register and return the sum. */ | |
1542 | rtx | |
1543 | rs6000_legitimize_address (x, oldx, mode) | |
1544 | rtx x; | |
1545 | rtx oldx ATTRIBUTE_UNUSED; | |
1546 | enum machine_mode mode; | |
1547 | { | |
1548 | if (GET_CODE (x) == PLUS | |
1549 | && GET_CODE (XEXP (x, 0)) == REG | |
1550 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
1551 | && (unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 1)) + 0x8000) >= 0x10000) | |
1552 | { | |
1553 | HOST_WIDE_INT high_int, low_int; | |
1554 | rtx sum; | |
1555 | high_int = INTVAL (XEXP (x, 1)) & (~ (HOST_WIDE_INT) 0xffff); | |
1556 | low_int = INTVAL (XEXP (x, 1)) & 0xffff; | |
1557 | if (low_int & 0x8000) | |
1558 | high_int += 0x10000, low_int |= ((HOST_WIDE_INT) -1) << 16; | |
1559 | sum = force_operand (gen_rtx_PLUS (Pmode, XEXP (x, 0), | |
1560 | GEN_INT (high_int)), 0); | |
1561 | return gen_rtx_PLUS (Pmode, sum, GEN_INT (low_int)); | |
1562 | } | |
1563 | else if (GET_CODE (x) == PLUS | |
1564 | && GET_CODE (XEXP (x, 0)) == REG | |
1565 | && GET_CODE (XEXP (x, 1)) != CONST_INT | |
1566 | && (TARGET_HARD_FLOAT || TARGET_POWERPC64 || mode != DFmode) | |
1567 | && (TARGET_POWERPC64 || mode != DImode) | |
1568 | && mode != TImode) | |
1569 | { | |
1570 | return gen_rtx_PLUS (Pmode, XEXP (x, 0), | |
1571 | force_reg (Pmode, force_operand (XEXP (x, 1), 0))); | |
1572 | } | |
1573 | else if (TARGET_ELF && TARGET_32BIT && TARGET_NO_TOC && ! flag_pic | |
1574 | && GET_CODE (x) != CONST_INT | |
1575 | && GET_CODE (x) != CONST_DOUBLE | |
1576 | && CONSTANT_P (x) | |
1577 | && (TARGET_HARD_FLOAT || mode != DFmode) | |
1578 | && mode != DImode | |
1579 | && mode != TImode) | |
1580 | { | |
1581 | rtx reg = gen_reg_rtx (Pmode); | |
1582 | emit_insn (gen_elf_high (reg, (x))); | |
1583 | return gen_rtx_LO_SUM (Pmode, reg, (x)); | |
1584 | } | |
ee890fe2 SS |
1585 | else if (TARGET_MACHO && TARGET_32BIT && TARGET_NO_TOC |
1586 | && ! flag_pic | |
1587 | && GET_CODE (x) != CONST_INT | |
1588 | && GET_CODE (x) != CONST_DOUBLE | |
1589 | && CONSTANT_P (x) | |
1590 | && (TARGET_HARD_FLOAT || mode != DFmode) | |
1591 | && mode != DImode | |
1592 | && mode != TImode) | |
1593 | { | |
1594 | rtx reg = gen_reg_rtx (Pmode); | |
1595 | emit_insn (gen_macho_high (reg, (x))); | |
1596 | return gen_rtx_LO_SUM (Pmode, reg, (x)); | |
1597 | } | |
9ebbca7d GK |
1598 | else if (TARGET_TOC |
1599 | && CONSTANT_POOL_EXPR_P (x) | |
a9098fd0 | 1600 | && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), Pmode)) |
9ebbca7d GK |
1601 | { |
1602 | return create_TOC_reference (x); | |
1603 | } | |
1604 | else | |
1605 | return NULL_RTX; | |
1606 | } | |
258bfae2 FS |
1607 | |
1608 | /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression | |
1609 | that is a valid memory address for an instruction. | |
1610 | The MODE argument is the machine mode for the MEM expression | |
1611 | that wants to use this address. | |
1612 | ||
1613 | On the RS/6000, there are four valid address: a SYMBOL_REF that | |
1614 | refers to a constant pool entry of an address (or the sum of it | |
1615 | plus a constant), a short (16-bit signed) constant plus a register, | |
1616 | the sum of two registers, or a register indirect, possibly with an | |
1617 | auto-increment. For DFmode and DImode with an constant plus register, | |
1618 | we must ensure that both words are addressable or PowerPC64 with offset | |
1619 | word aligned. | |
1620 | ||
1621 | For modes spanning multiple registers (DFmode in 32-bit GPRs, | |
1622 | 32-bit DImode, TImode), indexed addressing cannot be used because | |
1623 | adjacent memory cells are accessed by adding word-sized offsets | |
1624 | during assembly output. */ | |
1625 | int | |
1626 | rs6000_legitimate_address (mode, x, reg_ok_strict) | |
1627 | enum machine_mode mode; | |
1628 | rtx x; | |
1629 | int reg_ok_strict; | |
1630 | { | |
1631 | if (LEGITIMATE_INDIRECT_ADDRESS_P (x, reg_ok_strict)) | |
1632 | return 1; | |
1633 | if ((GET_CODE (x) == PRE_INC || GET_CODE (x) == PRE_DEC) | |
1634 | && TARGET_UPDATE | |
1635 | && LEGITIMATE_INDIRECT_ADDRESS_P (XEXP (x, 0), reg_ok_strict)) | |
1636 | return 1; | |
1637 | if (LEGITIMATE_SMALL_DATA_P (mode, x)) | |
1638 | return 1; | |
1639 | if (LEGITIMATE_CONSTANT_POOL_ADDRESS_P (x)) | |
1640 | return 1; | |
1641 | /* If not REG_OK_STRICT (before reload) let pass any stack offset. */ | |
1642 | if (! reg_ok_strict | |
1643 | && GET_CODE (x) == PLUS | |
1644 | && GET_CODE (XEXP (x, 0)) == REG | |
1645 | && XEXP (x, 0) == virtual_stack_vars_rtx | |
1646 | && GET_CODE (XEXP (x, 1)) == CONST_INT) | |
1647 | return 1; | |
1648 | if (LEGITIMATE_OFFSET_ADDRESS_P (mode, x, reg_ok_strict)) | |
1649 | return 1; | |
1650 | if (mode != TImode | |
1651 | && (TARGET_HARD_FLOAT || TARGET_POWERPC64 || mode != DFmode) | |
1652 | && (TARGET_POWERPC64 || mode != DImode) | |
1653 | && LEGITIMATE_INDEXED_ADDRESS_P (x, reg_ok_strict)) | |
1654 | return 1; | |
1655 | if (LEGITIMATE_LO_SUM_ADDRESS_P (mode, x, reg_ok_strict)) | |
1656 | return 1; | |
1657 | return 0; | |
1658 | } | |
fb4d4348 | 1659 | \f |
a4f6c312 SS |
1660 | /* Try to output insns to set TARGET equal to the constant C if it can |
1661 | be done in less than N insns. Do all computations in MODE. | |
1662 | Returns the place where the output has been placed if it can be | |
1663 | done and the insns have been emitted. If it would take more than N | |
1664 | insns, zero is returned and no insns and emitted. */ | |
2bfcf297 DB |
1665 | |
1666 | rtx | |
1667 | rs6000_emit_set_const (dest, mode, source, n) | |
1668 | rtx dest, source; | |
1669 | enum machine_mode mode; | |
1670 | int n ATTRIBUTE_UNUSED; | |
1671 | { | |
1672 | HOST_WIDE_INT c0, c1; | |
1673 | ||
1674 | if (mode == QImode || mode == HImode || mode == SImode) | |
1675 | { | |
1676 | if (dest == NULL) | |
1677 | dest = gen_reg_rtx (mode); | |
1678 | emit_insn (gen_rtx_SET (VOIDmode, dest, source)); | |
1679 | return dest; | |
1680 | } | |
1681 | ||
1682 | if (GET_CODE (source) == CONST_INT) | |
1683 | { | |
1684 | c0 = INTVAL (source); | |
1685 | c1 = -(c0 < 0); | |
1686 | } | |
1687 | else if (GET_CODE (source) == CONST_DOUBLE) | |
1688 | { | |
1689 | #if HOST_BITS_PER_WIDE_INT >= 64 | |
1690 | c0 = CONST_DOUBLE_LOW (source); | |
1691 | c1 = -(c0 < 0); | |
1692 | #else | |
1693 | c0 = CONST_DOUBLE_LOW (source); | |
1694 | c1 = CONST_DOUBLE_HIGH (source); | |
1695 | #endif | |
1696 | } | |
1697 | else | |
a4f6c312 | 1698 | abort (); |
2bfcf297 DB |
1699 | |
1700 | return rs6000_emit_set_long_const (dest, c0, c1); | |
1701 | } | |
1702 | ||
1703 | /* Having failed to find a 3 insn sequence in rs6000_emit_set_const, | |
1704 | fall back to a straight forward decomposition. We do this to avoid | |
1705 | exponential run times encountered when looking for longer sequences | |
1706 | with rs6000_emit_set_const. */ | |
1707 | static rtx | |
1708 | rs6000_emit_set_long_const (dest, c1, c2) | |
1709 | rtx dest; | |
1710 | HOST_WIDE_INT c1, c2; | |
1711 | { | |
1712 | if (!TARGET_POWERPC64) | |
1713 | { | |
1714 | rtx operand1, operand2; | |
1715 | ||
1716 | operand1 = operand_subword_force (dest, WORDS_BIG_ENDIAN == 0, | |
1717 | DImode); | |
1718 | operand2 = operand_subword_force (dest, WORDS_BIG_ENDIAN != 0, | |
1719 | DImode); | |
1720 | emit_move_insn (operand1, GEN_INT (c1)); | |
1721 | emit_move_insn (operand2, GEN_INT (c2)); | |
1722 | } | |
1723 | else | |
1724 | { | |
1725 | HOST_WIDE_INT d1, d2, d3, d4; | |
1726 | ||
1727 | /* Decompose the entire word */ | |
1728 | #if HOST_BITS_PER_WIDE_INT >= 64 | |
1729 | if (c2 != -(c1 < 0)) | |
1730 | abort (); | |
1731 | d1 = ((c1 & 0xffff) ^ 0x8000) - 0x8000; | |
1732 | c1 -= d1; | |
1733 | d2 = ((c1 & 0xffffffff) ^ 0x80000000) - 0x80000000; | |
1734 | c1 = (c1 - d2) >> 32; | |
1735 | d3 = ((c1 & 0xffff) ^ 0x8000) - 0x8000; | |
1736 | c1 -= d3; | |
1737 | d4 = ((c1 & 0xffffffff) ^ 0x80000000) - 0x80000000; | |
1738 | if (c1 != d4) | |
1739 | abort (); | |
1740 | #else | |
1741 | d1 = ((c1 & 0xffff) ^ 0x8000) - 0x8000; | |
1742 | c1 -= d1; | |
1743 | d2 = ((c1 & 0xffffffff) ^ 0x80000000) - 0x80000000; | |
1744 | if (c1 != d2) | |
1745 | abort (); | |
1746 | c2 += (d2 < 0); | |
1747 | d3 = ((c2 & 0xffff) ^ 0x8000) - 0x8000; | |
1748 | c2 -= d3; | |
1749 | d4 = ((c2 & 0xffffffff) ^ 0x80000000) - 0x80000000; | |
1750 | if (c2 != d4) | |
1751 | abort (); | |
1752 | #endif | |
1753 | ||
1754 | /* Construct the high word */ | |
40501e5f | 1755 | if (d4 != 0) |
2bfcf297 DB |
1756 | { |
1757 | emit_move_insn (dest, GEN_INT (d4)); | |
40501e5f | 1758 | if (d3 != 0) |
2bfcf297 DB |
1759 | emit_move_insn (dest, |
1760 | gen_rtx_PLUS (DImode, dest, GEN_INT (d3))); | |
1761 | } | |
1762 | else | |
1763 | emit_move_insn (dest, GEN_INT (d3)); | |
1764 | ||
1765 | /* Shift it into place */ | |
40501e5f AM |
1766 | if (d3 != 0 || d4 != 0) |
1767 | emit_move_insn (dest, gen_rtx_ASHIFT (DImode, dest, GEN_INT (32))); | |
2bfcf297 DB |
1768 | |
1769 | /* Add in the low bits. */ | |
40501e5f | 1770 | if (d2 != 0) |
2bfcf297 | 1771 | emit_move_insn (dest, gen_rtx_PLUS (DImode, dest, GEN_INT (d2))); |
40501e5f | 1772 | if (d1 != 0) |
2bfcf297 DB |
1773 | emit_move_insn (dest, gen_rtx_PLUS (DImode, dest, GEN_INT (d1))); |
1774 | } | |
1775 | ||
1776 | return dest; | |
1777 | } | |
1778 | ||
fb4d4348 GK |
1779 | /* Emit a move from SOURCE to DEST in mode MODE. */ |
1780 | void | |
1781 | rs6000_emit_move (dest, source, mode) | |
1782 | rtx dest; | |
1783 | rtx source; | |
1784 | enum machine_mode mode; | |
1785 | { | |
1786 | rtx operands[2]; | |
1787 | operands[0] = dest; | |
1788 | operands[1] = source; | |
1789 | ||
1790 | /* Sanity checks. Check that we get CONST_DOUBLE only when we should. */ | |
1791 | if (GET_CODE (operands[1]) == CONST_DOUBLE | |
1792 | && ! FLOAT_MODE_P (mode) | |
1793 | && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT) | |
1794 | { | |
1795 | /* FIXME. This should never happen. */ | |
1796 | /* Since it seems that it does, do the safe thing and convert | |
1797 | to a CONST_INT. */ | |
1798 | operands[1] = | |
1799 | GEN_INT (trunc_int_for_mode (CONST_DOUBLE_LOW (operands[1]), mode)); | |
1800 | } | |
1801 | if (GET_CODE (operands[1]) == CONST_DOUBLE | |
1802 | && ! FLOAT_MODE_P (mode) | |
1803 | && ((CONST_DOUBLE_HIGH (operands[1]) == 0 | |
1804 | && CONST_DOUBLE_LOW (operands[1]) >= 0) | |
1805 | || (CONST_DOUBLE_HIGH (operands[1]) == -1 | |
1806 | && CONST_DOUBLE_LOW (operands[1]) < 0))) | |
1807 | abort (); | |
1808 | ||
1809 | if (! no_new_pseudos && GET_CODE (operands[0]) != REG) | |
1810 | operands[1] = force_reg (mode, operands[1]); | |
a9098fd0 | 1811 | |
ffc14f31 GK |
1812 | if (mode == SFmode && ! TARGET_POWERPC && TARGET_HARD_FLOAT |
1813 | && GET_CODE (operands[0]) == MEM) | |
fb4d4348 | 1814 | { |
ffc14f31 GK |
1815 | int regnum; |
1816 | ||
1817 | if (reload_in_progress || reload_completed) | |
1818 | regnum = true_regnum (operands[1]); | |
1819 | else if (GET_CODE (operands[1]) == REG) | |
1820 | regnum = REGNO (operands[1]); | |
1821 | else | |
1822 | regnum = -1; | |
fb4d4348 GK |
1823 | |
1824 | /* If operands[1] is a register, on POWER it may have | |
1825 | double-precision data in it, so truncate it to single | |
1826 | precision. */ | |
1827 | if (FP_REGNO_P (regnum) || regnum >= FIRST_PSEUDO_REGISTER) | |
1828 | { | |
1829 | rtx newreg; | |
1830 | newreg = (no_new_pseudos ? operands[1] : gen_reg_rtx (mode)); | |
1831 | emit_insn (gen_aux_truncdfsf2 (newreg, operands[1])); | |
1832 | operands[1] = newreg; | |
1833 | } | |
1834 | } | |
1835 | ||
a9098fd0 GK |
1836 | /* Handle the case where reload calls us with an invalid address; |
1837 | and the case of CONSTANT_P_RTX. */ | |
1838 | if (! general_operand (operands[1], mode) | |
1839 | || ! nonimmediate_operand (operands[0], mode) | |
1840 | || GET_CODE (operands[1]) == CONSTANT_P_RTX) | |
fb4d4348 GK |
1841 | { |
1842 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1])); | |
1843 | return; | |
1844 | } | |
a9098fd0 | 1845 | |
fb4d4348 GK |
1846 | /* FIXME: In the long term, this switch statement should go away |
1847 | and be replaced by a sequence of tests based on things like | |
1848 | mode == Pmode. */ | |
1849 | switch (mode) | |
1850 | { | |
1851 | case HImode: | |
1852 | case QImode: | |
1853 | if (CONSTANT_P (operands[1]) | |
1854 | && GET_CODE (operands[1]) != CONST_INT) | |
a9098fd0 | 1855 | operands[1] = force_const_mem (mode, operands[1]); |
fb4d4348 GK |
1856 | break; |
1857 | ||
1858 | case DFmode: | |
1859 | case SFmode: | |
1860 | if (CONSTANT_P (operands[1]) | |
1861 | && ! easy_fp_constant (operands[1], mode)) | |
a9098fd0 | 1862 | operands[1] = force_const_mem (mode, operands[1]); |
fb4d4348 GK |
1863 | break; |
1864 | ||
1865 | case SImode: | |
a9098fd0 | 1866 | case DImode: |
fb4d4348 GK |
1867 | /* Use default pattern for address of ELF small data */ |
1868 | if (TARGET_ELF | |
a9098fd0 | 1869 | && mode == Pmode |
fb4d4348 | 1870 | && (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) |
a9098fd0 GK |
1871 | && (GET_CODE (operands[1]) == SYMBOL_REF |
1872 | || GET_CODE (operands[1]) == CONST) | |
1873 | && small_data_operand (operands[1], mode)) | |
fb4d4348 GK |
1874 | { |
1875 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1])); | |
1876 | return; | |
1877 | } | |
1878 | ||
1879 | if ((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) | |
a9098fd0 GK |
1880 | && mode == Pmode && mode == SImode |
1881 | && flag_pic == 1 && got_operand (operands[1], mode)) | |
fb4d4348 GK |
1882 | { |
1883 | emit_insn (gen_movsi_got (operands[0], operands[1])); | |
1884 | return; | |
1885 | } | |
1886 | ||
ee890fe2 SS |
1887 | if ((TARGET_ELF || DEFAULT_ABI == ABI_DARWIN) |
1888 | && TARGET_NO_TOC && ! flag_pic | |
a9098fd0 | 1889 | && mode == Pmode |
fb4d4348 GK |
1890 | && CONSTANT_P (operands[1]) |
1891 | && GET_CODE (operands[1]) != HIGH | |
1892 | && GET_CODE (operands[1]) != CONST_INT) | |
1893 | { | |
a9098fd0 | 1894 | rtx target = (no_new_pseudos ? operands[0] : gen_reg_rtx (mode)); |
fb4d4348 GK |
1895 | |
1896 | /* If this is a function address on -mcall-aixdesc, | |
1897 | convert it to the address of the descriptor. */ | |
1898 | if (DEFAULT_ABI == ABI_AIX | |
1899 | && GET_CODE (operands[1]) == SYMBOL_REF | |
1900 | && XSTR (operands[1], 0)[0] == '.') | |
1901 | { | |
1902 | const char *name = XSTR (operands[1], 0); | |
1903 | rtx new_ref; | |
1904 | while (*name == '.') | |
1905 | name++; | |
1906 | new_ref = gen_rtx_SYMBOL_REF (Pmode, name); | |
1907 | CONSTANT_POOL_ADDRESS_P (new_ref) | |
1908 | = CONSTANT_POOL_ADDRESS_P (operands[1]); | |
1909 | SYMBOL_REF_FLAG (new_ref) = SYMBOL_REF_FLAG (operands[1]); | |
1910 | SYMBOL_REF_USED (new_ref) = SYMBOL_REF_USED (operands[1]); | |
1911 | operands[1] = new_ref; | |
1912 | } | |
7509c759 | 1913 | |
ee890fe2 SS |
1914 | if (DEFAULT_ABI == ABI_DARWIN) |
1915 | { | |
1916 | emit_insn (gen_macho_high (target, operands[1])); | |
1917 | emit_insn (gen_macho_low (operands[0], target, operands[1])); | |
1918 | return; | |
1919 | } | |
1920 | ||
fb4d4348 GK |
1921 | emit_insn (gen_elf_high (target, operands[1])); |
1922 | emit_insn (gen_elf_low (operands[0], target, operands[1])); | |
1923 | return; | |
1924 | } | |
1925 | ||
a9098fd0 GK |
1926 | /* If this is a SYMBOL_REF that refers to a constant pool entry, |
1927 | and we have put it in the TOC, we just need to make a TOC-relative | |
1928 | reference to it. */ | |
1929 | if (TARGET_TOC | |
1930 | && GET_CODE (operands[1]) == SYMBOL_REF | |
1931 | && CONSTANT_POOL_EXPR_P (operands[1]) | |
1932 | && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (operands[1]), | |
1933 | get_pool_mode (operands[1]))) | |
fb4d4348 | 1934 | { |
a9098fd0 | 1935 | operands[1] = create_TOC_reference (operands[1]); |
fb4d4348 | 1936 | } |
a9098fd0 GK |
1937 | else if (mode == Pmode |
1938 | && CONSTANT_P (operands[1]) | |
38886f37 AO |
1939 | && ((GET_CODE (operands[1]) != CONST_INT |
1940 | && ! easy_fp_constant (operands[1], mode)) | |
1941 | || (GET_CODE (operands[1]) == CONST_INT | |
1942 | && num_insns_constant (operands[1], mode) > 2) | |
1943 | || (GET_CODE (operands[0]) == REG | |
1944 | && FP_REGNO_P (REGNO (operands[0])))) | |
a9098fd0 GK |
1945 | && GET_CODE (operands[1]) != HIGH |
1946 | && ! LEGITIMATE_CONSTANT_POOL_ADDRESS_P (operands[1]) | |
1947 | && ! TOC_RELATIVE_EXPR_P (operands[1])) | |
fb4d4348 GK |
1948 | { |
1949 | /* Emit a USE operation so that the constant isn't deleted if | |
1950 | expensive optimizations are turned on because nobody | |
1951 | references it. This should only be done for operands that | |
1952 | contain SYMBOL_REFs with CONSTANT_POOL_ADDRESS_P set. | |
1953 | This should not be done for operands that contain LABEL_REFs. | |
1954 | For now, we just handle the obvious case. */ | |
1955 | if (GET_CODE (operands[1]) != LABEL_REF) | |
1956 | emit_insn (gen_rtx_USE (VOIDmode, operands[1])); | |
1957 | ||
ee890fe2 SS |
1958 | /* Darwin uses a special PIC legitimizer. */ |
1959 | if (DEFAULT_ABI == ABI_DARWIN && flag_pic) | |
1960 | { | |
78e1b90d | 1961 | #if TARGET_MACHO |
ee890fe2 SS |
1962 | rtx temp_reg = ((reload_in_progress || reload_completed) |
1963 | ? operands[0] : NULL); | |
1964 | ||
ee890fe2 SS |
1965 | operands[1] = |
1966 | rs6000_machopic_legitimize_pic_address (operands[1], mode, | |
a4f6c312 | 1967 | temp_reg); |
ee890fe2 SS |
1968 | #endif |
1969 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1])); | |
1970 | return; | |
1971 | } | |
1972 | ||
fb4d4348 GK |
1973 | /* If we are to limit the number of things we put in the TOC and |
1974 | this is a symbol plus a constant we can add in one insn, | |
1975 | just put the symbol in the TOC and add the constant. Don't do | |
1976 | this if reload is in progress. */ | |
1977 | if (GET_CODE (operands[1]) == CONST | |
1978 | && TARGET_NO_SUM_IN_TOC && ! reload_in_progress | |
1979 | && GET_CODE (XEXP (operands[1], 0)) == PLUS | |
a9098fd0 | 1980 | && add_operand (XEXP (XEXP (operands[1], 0), 1), mode) |
fb4d4348 GK |
1981 | && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF |
1982 | || GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF) | |
1983 | && ! side_effects_p (operands[0])) | |
1984 | { | |
a4f6c312 SS |
1985 | rtx sym = |
1986 | force_const_mem (mode, XEXP (XEXP (operands[1], 0), 0)); | |
fb4d4348 GK |
1987 | rtx other = XEXP (XEXP (operands[1], 0), 1); |
1988 | ||
a9098fd0 GK |
1989 | sym = force_reg (mode, sym); |
1990 | if (mode == SImode) | |
1991 | emit_insn (gen_addsi3 (operands[0], sym, other)); | |
1992 | else | |
1993 | emit_insn (gen_adddi3 (operands[0], sym, other)); | |
fb4d4348 GK |
1994 | return; |
1995 | } | |
1996 | ||
a9098fd0 | 1997 | operands[1] = force_const_mem (mode, operands[1]); |
fb4d4348 GK |
1998 | |
1999 | if (TARGET_TOC | |
d34c5b80 DE |
2000 | && CONSTANT_POOL_EXPR_P (XEXP (operands[1], 0)) |
2001 | && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P ( | |
2002 | get_pool_constant (XEXP (operands[1], 0)), | |
2003 | get_pool_mode (XEXP (operands[1], 0)))) | |
a9098fd0 | 2004 | { |
ba4828e0 RK |
2005 | operands[1] |
2006 | = gen_rtx_MEM (mode, | |
2007 | create_TOC_reference (XEXP (operands[1], 0))); | |
2008 | set_mem_alias_set (operands[1], get_TOC_alias_set ()); | |
fb4d4348 | 2009 | RTX_UNCHANGING_P (operands[1]) = 1; |
a9098fd0 | 2010 | } |
fb4d4348 GK |
2011 | } |
2012 | break; | |
a9098fd0 | 2013 | |
fb4d4348 GK |
2014 | case TImode: |
2015 | if (GET_CODE (operands[0]) == MEM | |
2016 | && GET_CODE (XEXP (operands[0], 0)) != REG | |
2017 | && ! reload_in_progress) | |
792760b9 RK |
2018 | operands[0] |
2019 | = replace_equiv_address (operands[0], | |
2020 | copy_addr_to_reg (XEXP (operands[0], 0))); | |
fb4d4348 GK |
2021 | |
2022 | if (GET_CODE (operands[1]) == MEM | |
2023 | && GET_CODE (XEXP (operands[1], 0)) != REG | |
2024 | && ! reload_in_progress) | |
792760b9 RK |
2025 | operands[1] |
2026 | = replace_equiv_address (operands[1], | |
2027 | copy_addr_to_reg (XEXP (operands[1], 0))); | |
fb4d4348 GK |
2028 | break; |
2029 | ||
2030 | default: | |
2031 | abort (); | |
2032 | } | |
2033 | ||
a9098fd0 GK |
2034 | /* Above, we may have called force_const_mem which may have returned |
2035 | an invalid address. If we can, fix this up; otherwise, reload will | |
2036 | have to deal with it. */ | |
2037 | if (GET_CODE (operands[1]) == MEM | |
2038 | && ! memory_address_p (mode, XEXP (operands[1], 0)) | |
2039 | && ! reload_in_progress) | |
f4ef873c | 2040 | operands[1] = adjust_address (operands[1], mode, 0); |
a9098fd0 | 2041 | |
fb4d4348 | 2042 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1])); |
02a4ec28 | 2043 | return; |
fb4d4348 | 2044 | } |
4697a36c MM |
2045 | \f |
2046 | /* Initialize a variable CUM of type CUMULATIVE_ARGS | |
2047 | for a call to a function whose data type is FNTYPE. | |
2048 | For a library call, FNTYPE is 0. | |
2049 | ||
2050 | For incoming args we set the number of arguments in the prototype large | |
1c20ae99 | 2051 | so we never return a PARALLEL. */ |
4697a36c MM |
2052 | |
2053 | void | |
2054 | init_cumulative_args (cum, fntype, libname, incoming) | |
2055 | CUMULATIVE_ARGS *cum; | |
2056 | tree fntype; | |
296b8152 | 2057 | rtx libname ATTRIBUTE_UNUSED; |
4697a36c MM |
2058 | int incoming; |
2059 | { | |
2060 | static CUMULATIVE_ARGS zero_cumulative; | |
2061 | ||
2062 | *cum = zero_cumulative; | |
2063 | cum->words = 0; | |
2064 | cum->fregno = FP_ARG_MIN_REG; | |
2065 | cum->prototype = (fntype && TYPE_ARG_TYPES (fntype)); | |
7509c759 | 2066 | cum->call_cookie = CALL_NORMAL; |
4cc833b7 | 2067 | cum->sysv_gregno = GP_ARG_MIN_REG; |
4697a36c MM |
2068 | |
2069 | if (incoming) | |
bd227acc | 2070 | cum->nargs_prototype = 1000; /* don't return a PARALLEL */ |
4697a36c MM |
2071 | |
2072 | else if (cum->prototype) | |
2073 | cum->nargs_prototype = (list_length (TYPE_ARG_TYPES (fntype)) - 1 | |
2074 | + (TYPE_MODE (TREE_TYPE (fntype)) == BLKmode | |
2075 | || RETURN_IN_MEMORY (TREE_TYPE (fntype)))); | |
2076 | ||
2077 | else | |
2078 | cum->nargs_prototype = 0; | |
2079 | ||
2080 | cum->orig_nargs = cum->nargs_prototype; | |
7509c759 | 2081 | |
9ebbca7d GK |
2082 | /* Check for longcall's */ |
2083 | if (fntype && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype))) | |
6a4cee5f MM |
2084 | cum->call_cookie = CALL_LONG; |
2085 | ||
4697a36c MM |
2086 | if (TARGET_DEBUG_ARG) |
2087 | { | |
2088 | fprintf (stderr, "\ninit_cumulative_args:"); | |
2089 | if (fntype) | |
2090 | { | |
2091 | tree ret_type = TREE_TYPE (fntype); | |
2092 | fprintf (stderr, " ret code = %s,", | |
2093 | tree_code_name[ (int)TREE_CODE (ret_type) ]); | |
2094 | } | |
2095 | ||
6a4cee5f MM |
2096 | if (cum->call_cookie & CALL_LONG) |
2097 | fprintf (stderr, " longcall,"); | |
2098 | ||
4697a36c MM |
2099 | fprintf (stderr, " proto = %d, nargs = %d\n", |
2100 | cum->prototype, cum->nargs_prototype); | |
2101 | } | |
2102 | } | |
2103 | \f | |
c229cba9 DE |
2104 | /* If defined, a C expression which determines whether, and in which |
2105 | direction, to pad out an argument with extra space. The value | |
2106 | should be of type `enum direction': either `upward' to pad above | |
2107 | the argument, `downward' to pad below, or `none' to inhibit | |
2108 | padding. | |
2109 | ||
2110 | For the AIX ABI structs are always stored left shifted in their | |
2111 | argument slot. */ | |
2112 | ||
9ebbca7d | 2113 | enum direction |
c229cba9 DE |
2114 | function_arg_padding (mode, type) |
2115 | enum machine_mode mode; | |
2116 | tree type; | |
2117 | { | |
c85f7c16 | 2118 | if (type != 0 && AGGREGATE_TYPE_P (type)) |
9ebbca7d | 2119 | return upward; |
c229cba9 DE |
2120 | |
2121 | /* This is the default definition. */ | |
2122 | return (! BYTES_BIG_ENDIAN | |
9ebbca7d | 2123 | ? upward |
c229cba9 DE |
2124 | : ((mode == BLKmode |
2125 | ? (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST | |
2126 | && int_size_in_bytes (type) < (PARM_BOUNDARY / BITS_PER_UNIT)) | |
2127 | : GET_MODE_BITSIZE (mode) < PARM_BOUNDARY) | |
9ebbca7d | 2128 | ? downward : upward)); |
c229cba9 DE |
2129 | } |
2130 | ||
b6c9286a MM |
2131 | /* If defined, a C expression that gives the alignment boundary, in bits, |
2132 | of an argument with the specified mode and type. If it is not defined, | |
2133 | PARM_BOUNDARY is used for all arguments. | |
2134 | ||
2310f99a | 2135 | V.4 wants long longs to be double word aligned. */ |
b6c9286a MM |
2136 | |
2137 | int | |
2138 | function_arg_boundary (mode, type) | |
2139 | enum machine_mode mode; | |
9ebbca7d | 2140 | tree type ATTRIBUTE_UNUSED; |
b6c9286a | 2141 | { |
4cc833b7 RH |
2142 | if ((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) |
2143 | && (mode == DImode || mode == DFmode)) | |
e1f83b4d | 2144 | return 64; |
9ebbca7d | 2145 | else |
b6c9286a | 2146 | return PARM_BOUNDARY; |
b6c9286a MM |
2147 | } |
2148 | \f | |
4697a36c MM |
2149 | /* Update the data in CUM to advance over an argument |
2150 | of mode MODE and data type TYPE. | |
2151 | (TYPE is null for libcalls where that information may not be available.) */ | |
2152 | ||
2153 | void | |
2154 | function_arg_advance (cum, mode, type, named) | |
2155 | CUMULATIVE_ARGS *cum; | |
2156 | enum machine_mode mode; | |
2157 | tree type; | |
2158 | int named; | |
2159 | { | |
2160 | cum->nargs_prototype--; | |
2161 | ||
c81bebd7 | 2162 | if (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) |
4697a36c | 2163 | { |
4cc833b7 RH |
2164 | if (TARGET_HARD_FLOAT |
2165 | && (mode == SFmode || mode == DFmode)) | |
4697a36c | 2166 | { |
4cc833b7 RH |
2167 | if (cum->fregno <= FP_ARG_V4_MAX_REG) |
2168 | cum->fregno++; | |
2169 | else | |
2170 | { | |
2171 | if (mode == DFmode) | |
2172 | cum->words += cum->words & 1; | |
d34c5b80 | 2173 | cum->words += RS6000_ARG_SIZE (mode, type); |
4cc833b7 | 2174 | } |
4697a36c | 2175 | } |
4cc833b7 RH |
2176 | else |
2177 | { | |
2178 | int n_words; | |
2179 | int gregno = cum->sysv_gregno; | |
2180 | ||
2181 | /* Aggregates and IEEE quad get passed by reference. */ | |
2182 | if ((type && AGGREGATE_TYPE_P (type)) | |
2183 | || mode == TFmode) | |
2184 | n_words = 1; | |
2185 | else | |
d34c5b80 | 2186 | n_words = RS6000_ARG_SIZE (mode, type); |
4cc833b7 RH |
2187 | |
2188 | /* Long long is put in odd registers. */ | |
2189 | if (n_words == 2 && (gregno & 1) == 0) | |
2190 | gregno += 1; | |
2191 | ||
2192 | /* Long long is not split between registers and stack. */ | |
2193 | if (gregno + n_words - 1 > GP_ARG_MAX_REG) | |
2194 | { | |
2195 | /* Long long is aligned on the stack. */ | |
2196 | if (n_words == 2) | |
2197 | cum->words += cum->words & 1; | |
2198 | cum->words += n_words; | |
2199 | } | |
4697a36c | 2200 | |
4cc833b7 RH |
2201 | /* Note: continuing to accumulate gregno past when we've started |
2202 | spilling to the stack indicates the fact that we've started | |
2203 | spilling to the stack to expand_builtin_saveregs. */ | |
2204 | cum->sysv_gregno = gregno + n_words; | |
2205 | } | |
4697a36c | 2206 | |
4cc833b7 RH |
2207 | if (TARGET_DEBUG_ARG) |
2208 | { | |
2209 | fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ", | |
2210 | cum->words, cum->fregno); | |
2211 | fprintf (stderr, "gregno = %2d, nargs = %4d, proto = %d, ", | |
2212 | cum->sysv_gregno, cum->nargs_prototype, cum->prototype); | |
2213 | fprintf (stderr, "mode = %4s, named = %d\n", | |
2214 | GET_MODE_NAME (mode), named); | |
2215 | } | |
4697a36c MM |
2216 | } |
2217 | else | |
4cc833b7 RH |
2218 | { |
2219 | int align = (TARGET_32BIT && (cum->words & 1) != 0 | |
2220 | && function_arg_boundary (mode, type) == 64) ? 1 : 0; | |
a4f6c312 | 2221 | |
d34c5b80 | 2222 | cum->words += align + RS6000_ARG_SIZE (mode, type); |
4697a36c | 2223 | |
d34c5b80 DE |
2224 | if (GET_MODE_CLASS (mode) == MODE_FLOAT && TARGET_HARD_FLOAT) |
2225 | cum->fregno++; | |
4cc833b7 RH |
2226 | |
2227 | if (TARGET_DEBUG_ARG) | |
2228 | { | |
2229 | fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ", | |
2230 | cum->words, cum->fregno); | |
2231 | fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s, ", | |
2232 | cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode)); | |
2233 | fprintf (stderr, "named = %d, align = %d\n", named, align); | |
2234 | } | |
2235 | } | |
4697a36c MM |
2236 | } |
2237 | \f | |
2238 | /* Determine where to put an argument to a function. | |
2239 | Value is zero to push the argument on the stack, | |
2240 | or a hard register in which to store the argument. | |
2241 | ||
2242 | MODE is the argument's machine mode. | |
2243 | TYPE is the data type of the argument (as a tree). | |
2244 | This is null for libcalls where that information may | |
2245 | not be available. | |
2246 | CUM is a variable of type CUMULATIVE_ARGS which gives info about | |
2247 | the preceding args and about the function being called. | |
2248 | NAMED is nonzero if this argument is a named parameter | |
2249 | (otherwise it is an extra parameter matching an ellipsis). | |
2250 | ||
2251 | On RS/6000 the first eight words of non-FP are normally in registers | |
2252 | and the rest are pushed. Under AIX, the first 13 FP args are in registers. | |
2253 | Under V.4, the first 8 FP args are in registers. | |
2254 | ||
2255 | If this is floating-point and no prototype is specified, we use | |
2256 | both an FP and integer register (or possibly FP reg and stack). Library | |
2257 | functions (when TYPE is zero) always have the proper types for args, | |
2258 | so we can pass the FP value just in one register. emit_library_function | |
1c20ae99 | 2259 | doesn't support PARALLEL anyway. */ |
4697a36c MM |
2260 | |
2261 | struct rtx_def * | |
2262 | function_arg (cum, mode, type, named) | |
2263 | CUMULATIVE_ARGS *cum; | |
2264 | enum machine_mode mode; | |
2265 | tree type; | |
d34c5b80 | 2266 | int named ATTRIBUTE_UNUSED; |
4697a36c | 2267 | { |
4cc833b7 | 2268 | enum rs6000_abi abi = DEFAULT_ABI; |
4697a36c | 2269 | |
a4f6c312 SS |
2270 | /* Return a marker to indicate whether CR1 needs to set or clear the |
2271 | bit that V.4 uses to say fp args were passed in registers. | |
2272 | Assume that we don't need the marker for software floating point, | |
2273 | or compiler generated library calls. */ | |
4697a36c MM |
2274 | if (mode == VOIDmode) |
2275 | { | |
c81bebd7 | 2276 | if ((abi == ABI_V4 || abi == ABI_SOLARIS) |
7509c759 MM |
2277 | && TARGET_HARD_FLOAT |
2278 | && cum->nargs_prototype < 0 | |
4697a36c | 2279 | && type && (cum->prototype || TARGET_NO_PROTOTYPE)) |
7509c759 | 2280 | { |
6a4cee5f MM |
2281 | return GEN_INT (cum->call_cookie |
2282 | | ((cum->fregno == FP_ARG_MIN_REG) | |
2283 | ? CALL_V4_SET_FP_ARGS | |
2284 | : CALL_V4_CLEAR_FP_ARGS)); | |
7509c759 | 2285 | } |
4697a36c | 2286 | |
7509c759 | 2287 | return GEN_INT (cum->call_cookie); |
4697a36c MM |
2288 | } |
2289 | ||
4cc833b7 | 2290 | if (abi == ABI_V4 || abi == ABI_SOLARIS) |
4697a36c | 2291 | { |
4cc833b7 RH |
2292 | if (TARGET_HARD_FLOAT |
2293 | && (mode == SFmode || mode == DFmode)) | |
2294 | { | |
2295 | if (cum->fregno <= FP_ARG_V4_MAX_REG) | |
2296 | return gen_rtx_REG (mode, cum->fregno); | |
2297 | else | |
2298 | return NULL; | |
2299 | } | |
2300 | else | |
2301 | { | |
2302 | int n_words; | |
2303 | int gregno = cum->sysv_gregno; | |
2304 | ||
2305 | /* Aggregates and IEEE quad get passed by reference. */ | |
2306 | if ((type && AGGREGATE_TYPE_P (type)) | |
2307 | || mode == TFmode) | |
2308 | n_words = 1; | |
2309 | else | |
d34c5b80 | 2310 | n_words = RS6000_ARG_SIZE (mode, type); |
4cc833b7 RH |
2311 | |
2312 | /* Long long is put in odd registers. */ | |
2313 | if (n_words == 2 && (gregno & 1) == 0) | |
2314 | gregno += 1; | |
2315 | ||
2316 | /* Long long is not split between registers and stack. */ | |
2317 | if (gregno + n_words - 1 <= GP_ARG_MAX_REG) | |
2318 | return gen_rtx_REG (mode, gregno); | |
2319 | else | |
2320 | return NULL; | |
2321 | } | |
4697a36c | 2322 | } |
4cc833b7 RH |
2323 | else |
2324 | { | |
2325 | int align = (TARGET_32BIT && (cum->words & 1) != 0 | |
2326 | && function_arg_boundary (mode, type) == 64) ? 1 : 0; | |
2327 | int align_words = cum->words + align; | |
4697a36c | 2328 | |
4cc833b7 RH |
2329 | if (type && TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST) |
2330 | return NULL_RTX; | |
2331 | ||
2332 | if (USE_FP_FOR_ARG_P (*cum, mode, type)) | |
2333 | { | |
2334 | if (! type | |
2335 | || ((cum->nargs_prototype > 0) | |
2336 | /* IBM AIX extended its linkage convention definition always | |
2337 | to require FP args after register save area hole on the | |
2338 | stack. */ | |
2339 | && (DEFAULT_ABI != ABI_AIX | |
2340 | || ! TARGET_XL_CALL | |
2341 | || (align_words < GP_ARG_NUM_REG)))) | |
2342 | return gen_rtx_REG (mode, cum->fregno); | |
2343 | ||
2344 | return gen_rtx_PARALLEL (mode, | |
2345 | gen_rtvec (2, | |
39403d82 | 2346 | gen_rtx_EXPR_LIST (VOIDmode, |
1c20ae99 JW |
2347 | ((align_words >= GP_ARG_NUM_REG) |
2348 | ? NULL_RTX | |
2349 | : (align_words | |
d34c5b80 | 2350 | + RS6000_ARG_SIZE (mode, type) |
1c20ae99 JW |
2351 | > GP_ARG_NUM_REG |
2352 | /* If this is partially on the stack, then | |
2353 | we only include the portion actually | |
2354 | in registers here. */ | |
39403d82 | 2355 | ? gen_rtx_REG (SImode, |
1c20ae99 | 2356 | GP_ARG_MIN_REG + align_words) |
39403d82 | 2357 | : gen_rtx_REG (mode, |
1c20ae99 JW |
2358 | GP_ARG_MIN_REG + align_words))), |
2359 | const0_rtx), | |
39403d82 DE |
2360 | gen_rtx_EXPR_LIST (VOIDmode, |
2361 | gen_rtx_REG (mode, cum->fregno), | |
1c20ae99 | 2362 | const0_rtx))); |
4cc833b7 RH |
2363 | } |
2364 | else if (align_words < GP_ARG_NUM_REG) | |
2365 | return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words); | |
2366 | else | |
2367 | return NULL_RTX; | |
4697a36c | 2368 | } |
4697a36c MM |
2369 | } |
2370 | \f | |
2371 | /* For an arg passed partly in registers and partly in memory, | |
2372 | this is the number of registers used. | |
2373 | For args passed entirely in registers or entirely in memory, zero. */ | |
2374 | ||
2375 | int | |
2376 | function_arg_partial_nregs (cum, mode, type, named) | |
2377 | CUMULATIVE_ARGS *cum; | |
2378 | enum machine_mode mode; | |
2379 | tree type; | |
d34c5b80 | 2380 | int named ATTRIBUTE_UNUSED; |
4697a36c | 2381 | { |
c81bebd7 | 2382 | if (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) |
4697a36c | 2383 | return 0; |
4697a36c MM |
2384 | |
2385 | if (USE_FP_FOR_ARG_P (*cum, mode, type)) | |
2386 | { | |
2387 | if (cum->nargs_prototype >= 0) | |
2388 | return 0; | |
2389 | } | |
2390 | ||
2391 | if (cum->words < GP_ARG_NUM_REG | |
d34c5b80 | 2392 | && GP_ARG_NUM_REG < (cum->words + RS6000_ARG_SIZE (mode, type))) |
4697a36c MM |
2393 | { |
2394 | int ret = GP_ARG_NUM_REG - cum->words; | |
2395 | if (ret && TARGET_DEBUG_ARG) | |
2396 | fprintf (stderr, "function_arg_partial_nregs: %d\n", ret); | |
2397 | ||
2398 | return ret; | |
2399 | } | |
2400 | ||
2401 | return 0; | |
2402 | } | |
2403 | \f | |
2404 | /* A C expression that indicates when an argument must be passed by | |
2405 | reference. If nonzero for an argument, a copy of that argument is | |
2406 | made in memory and a pointer to the argument is passed instead of | |
2407 | the argument itself. The pointer is passed in whatever way is | |
2408 | appropriate for passing a pointer to that type. | |
2409 | ||
2410 | Under V.4, structures and unions are passed by reference. */ | |
2411 | ||
2412 | int | |
2413 | function_arg_pass_by_reference (cum, mode, type, named) | |
296b8152 KG |
2414 | CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED; |
2415 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
4697a36c | 2416 | tree type; |
296b8152 | 2417 | int named ATTRIBUTE_UNUSED; |
4697a36c | 2418 | { |
c81bebd7 | 2419 | if ((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) |
4cc833b7 RH |
2420 | && ((type && AGGREGATE_TYPE_P (type)) |
2421 | || mode == TFmode)) | |
4697a36c MM |
2422 | { |
2423 | if (TARGET_DEBUG_ARG) | |
2424 | fprintf (stderr, "function_arg_pass_by_reference: aggregate\n"); | |
2425 | ||
2426 | return 1; | |
2427 | } | |
4697a36c MM |
2428 | |
2429 | return 0; | |
2430 | } | |
4697a36c MM |
2431 | \f |
2432 | /* Perform any needed actions needed for a function that is receiving a | |
2433 | variable number of arguments. | |
2434 | ||
2435 | CUM is as above. | |
2436 | ||
2437 | MODE and TYPE are the mode and type of the current parameter. | |
2438 | ||
2439 | PRETEND_SIZE is a variable that should be set to the amount of stack | |
2440 | that must be pushed by the prolog to pretend that our caller pushed | |
2441 | it. | |
2442 | ||
2443 | Normally, this macro will push all remaining incoming registers on the | |
2444 | stack and set PRETEND_SIZE to the length of the registers pushed. */ | |
2445 | ||
2446 | void | |
2447 | setup_incoming_varargs (cum, mode, type, pretend_size, no_rtl) | |
2448 | CUMULATIVE_ARGS *cum; | |
2449 | enum machine_mode mode; | |
2450 | tree type; | |
2451 | int *pretend_size; | |
2452 | int no_rtl; | |
2453 | ||
2454 | { | |
4cc833b7 RH |
2455 | CUMULATIVE_ARGS next_cum; |
2456 | int reg_size = TARGET_32BIT ? 4 : 8; | |
ca5adc63 | 2457 | rtx save_area = NULL_RTX, mem; |
dfafc897 | 2458 | int first_reg_offset, set; |
d34c5b80 DE |
2459 | tree fntype; |
2460 | int stdarg_p; | |
4697a36c | 2461 | |
d34c5b80 DE |
2462 | fntype = TREE_TYPE (current_function_decl); |
2463 | stdarg_p = (TYPE_ARG_TYPES (fntype) != 0 | |
2464 | && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype))) | |
2465 | != void_type_node)); | |
4cc833b7 | 2466 | |
d34c5b80 DE |
2467 | /* For varargs, we do not want to skip the dummy va_dcl argument. |
2468 | For stdargs, we do want to skip the last named argument. */ | |
2469 | next_cum = *cum; | |
2470 | if (stdarg_p) | |
2471 | function_arg_advance (&next_cum, mode, type, 1); | |
4cc833b7 | 2472 | |
d34c5b80 DE |
2473 | if (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) |
2474 | { | |
4cc833b7 RH |
2475 | /* Indicate to allocate space on the stack for varargs save area. */ |
2476 | /* ??? Does this really have to be located at a magic spot on the | |
2477 | stack, or can we allocate this with assign_stack_local instead. */ | |
00dba523 | 2478 | cfun->machine->sysv_varargs_p = 1; |
60e2d0ca | 2479 | if (! no_rtl) |
2c4974b7 | 2480 | save_area = plus_constant (virtual_stack_vars_rtx, |
bd227acc | 2481 | - RS6000_VARARGS_SIZE); |
4cc833b7 RH |
2482 | |
2483 | first_reg_offset = next_cum.sysv_gregno - GP_ARG_MIN_REG; | |
4697a36c | 2484 | } |
60e2d0ca | 2485 | else |
4697a36c | 2486 | { |
d34c5b80 | 2487 | first_reg_offset = next_cum.words; |
4cc833b7 | 2488 | save_area = virtual_incoming_args_rtx; |
00dba523 | 2489 | cfun->machine->sysv_varargs_p = 0; |
4697a36c MM |
2490 | |
2491 | if (MUST_PASS_IN_STACK (mode, type)) | |
d34c5b80 | 2492 | first_reg_offset += RS6000_ARG_SIZE (TYPE_MODE (type), type); |
4cc833b7 | 2493 | } |
4697a36c | 2494 | |
dfafc897 | 2495 | set = get_varargs_alias_set (); |
c81fc13e | 2496 | if (! no_rtl && first_reg_offset < GP_ARG_NUM_REG) |
4cc833b7 | 2497 | { |
dfafc897 FS |
2498 | mem = gen_rtx_MEM (BLKmode, |
2499 | plus_constant (save_area, | |
2500 | first_reg_offset * reg_size)), | |
ba4828e0 | 2501 | set_mem_alias_set (mem, set); |
8ac61af7 | 2502 | set_mem_align (mem, BITS_PER_WORD); |
dfafc897 | 2503 | |
4cc833b7 | 2504 | move_block_from_reg |
dfafc897 | 2505 | (GP_ARG_MIN_REG + first_reg_offset, mem, |
4cc833b7 RH |
2506 | GP_ARG_NUM_REG - first_reg_offset, |
2507 | (GP_ARG_NUM_REG - first_reg_offset) * UNITS_PER_WORD); | |
2508 | ||
2509 | /* ??? Does ABI_V4 need this at all? */ | |
4697a36c MM |
2510 | *pretend_size = (GP_ARG_NUM_REG - first_reg_offset) * UNITS_PER_WORD; |
2511 | } | |
2512 | ||
4697a36c | 2513 | /* Save FP registers if needed. */ |
4cc833b7 | 2514 | if ((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) |
c81fc13e | 2515 | && TARGET_HARD_FLOAT && ! no_rtl |
4cc833b7 | 2516 | && next_cum.fregno <= FP_ARG_V4_MAX_REG) |
4697a36c | 2517 | { |
4cc833b7 | 2518 | int fregno = next_cum.fregno; |
9ebbca7d | 2519 | rtx cr1 = gen_rtx_REG (CCmode, CR1_REGNO); |
4cc833b7 RH |
2520 | rtx lab = gen_label_rtx (); |
2521 | int off = (GP_ARG_NUM_REG * reg_size) + ((fregno - FP_ARG_MIN_REG) * 8); | |
4697a36c | 2522 | |
4cc833b7 | 2523 | emit_jump_insn (gen_rtx_SET (VOIDmode, |
4697a36c | 2524 | pc_rtx, |
39403d82 | 2525 | gen_rtx_IF_THEN_ELSE (VOIDmode, |
4cc833b7 RH |
2526 | gen_rtx_NE (VOIDmode, cr1, |
2527 | const0_rtx), | |
39403d82 | 2528 | gen_rtx_LABEL_REF (VOIDmode, lab), |
4697a36c MM |
2529 | pc_rtx))); |
2530 | ||
4cc833b7 RH |
2531 | while (fregno <= FP_ARG_V4_MAX_REG) |
2532 | { | |
dfafc897 | 2533 | mem = gen_rtx_MEM (DFmode, plus_constant (save_area, off)); |
ba4828e0 | 2534 | set_mem_alias_set (mem, set); |
dfafc897 | 2535 | emit_move_insn (mem, gen_rtx_REG (DFmode, fregno)); |
4cc833b7 RH |
2536 | fregno++; |
2537 | off += 8; | |
4697a36c | 2538 | } |
4cc833b7 RH |
2539 | |
2540 | emit_label (lab); | |
4697a36c | 2541 | } |
4697a36c | 2542 | } |
4697a36c | 2543 | |
dfafc897 | 2544 | /* Create the va_list data type. */ |
2c4974b7 | 2545 | |
dfafc897 FS |
2546 | tree |
2547 | rs6000_build_va_list () | |
2548 | { | |
bab45a51 | 2549 | tree f_gpr, f_fpr, f_ovf, f_sav, record, type_decl; |
4697a36c | 2550 | |
9ebbca7d GK |
2551 | /* For AIX, prefer 'char *' because that's what the system |
2552 | header files like. */ | |
dfafc897 | 2553 | if (DEFAULT_ABI != ABI_V4 && DEFAULT_ABI != ABI_SOLARIS) |
9ebbca7d | 2554 | return build_pointer_type (char_type_node); |
dfafc897 | 2555 | |
0f4fd75d | 2556 | record = make_lang_type (RECORD_TYPE); |
bab45a51 | 2557 | type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record); |
0f4fd75d | 2558 | |
9ebbca7d GK |
2559 | f_gpr = build_decl (FIELD_DECL, get_identifier ("gpr"), |
2560 | unsigned_char_type_node); | |
2561 | f_fpr = build_decl (FIELD_DECL, get_identifier ("fpr"), | |
2562 | unsigned_char_type_node); | |
dfafc897 FS |
2563 | f_ovf = build_decl (FIELD_DECL, get_identifier ("overflow_arg_area"), |
2564 | ptr_type_node); | |
2565 | f_sav = build_decl (FIELD_DECL, get_identifier ("reg_save_area"), | |
2566 | ptr_type_node); | |
2567 | ||
2568 | DECL_FIELD_CONTEXT (f_gpr) = record; | |
2569 | DECL_FIELD_CONTEXT (f_fpr) = record; | |
2570 | DECL_FIELD_CONTEXT (f_ovf) = record; | |
2571 | DECL_FIELD_CONTEXT (f_sav) = record; | |
2572 | ||
bab45a51 FS |
2573 | TREE_CHAIN (record) = type_decl; |
2574 | TYPE_NAME (record) = type_decl; | |
dfafc897 FS |
2575 | TYPE_FIELDS (record) = f_gpr; |
2576 | TREE_CHAIN (f_gpr) = f_fpr; | |
2577 | TREE_CHAIN (f_fpr) = f_ovf; | |
2578 | TREE_CHAIN (f_ovf) = f_sav; | |
2579 | ||
2580 | layout_type (record); | |
2581 | ||
2582 | /* The correct type is an array type of one element. */ | |
2583 | return build_array_type (record, build_index_type (size_zero_node)); | |
2584 | } | |
2585 | ||
2586 | /* Implement va_start. */ | |
2587 | ||
2588 | void | |
2589 | rs6000_va_start (stdarg_p, valist, nextarg) | |
2590 | int stdarg_p; | |
2591 | tree valist; | |
2592 | rtx nextarg; | |
4697a36c | 2593 | { |
dfafc897 FS |
2594 | HOST_WIDE_INT words, n_gpr, n_fpr; |
2595 | tree f_gpr, f_fpr, f_ovf, f_sav; | |
2596 | tree gpr, fpr, ovf, sav, t; | |
2c4974b7 | 2597 | |
dfafc897 | 2598 | /* Only SVR4 needs something special. */ |
2c4974b7 | 2599 | if (DEFAULT_ABI != ABI_V4 && DEFAULT_ABI != ABI_SOLARIS) |
dfafc897 FS |
2600 | { |
2601 | std_expand_builtin_va_start (stdarg_p, valist, nextarg); | |
2602 | return; | |
2603 | } | |
2604 | ||
973a648b | 2605 | f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node)); |
dfafc897 FS |
2606 | f_fpr = TREE_CHAIN (f_gpr); |
2607 | f_ovf = TREE_CHAIN (f_fpr); | |
2608 | f_sav = TREE_CHAIN (f_ovf); | |
2609 | ||
8ebecc3b | 2610 | valist = build1 (INDIRECT_REF, TREE_TYPE (TREE_TYPE (valist)), valist); |
dfafc897 FS |
2611 | gpr = build (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr); |
2612 | fpr = build (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr); | |
2613 | ovf = build (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf); | |
2614 | sav = build (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav); | |
2615 | ||
2616 | /* Count number of gp and fp argument registers used. */ | |
4cc833b7 | 2617 | words = current_function_args_info.words; |
dfafc897 FS |
2618 | n_gpr = current_function_args_info.sysv_gregno - GP_ARG_MIN_REG; |
2619 | n_fpr = current_function_args_info.fregno - FP_ARG_MIN_REG; | |
2620 | ||
2621 | if (TARGET_DEBUG_ARG) | |
78e1b90d DE |
2622 | { |
2623 | fputs ("va_start: words = ", stderr); | |
2624 | fprintf (stderr, HOST_WIDE_INT_PRINT_DEC, words); | |
2625 | fputs (", n_gpr = ", stderr); | |
2626 | fprintf (stderr, HOST_WIDE_INT_PRINT_DEC, n_gpr); | |
2627 | fputs (", n_fpr = ", stderr); | |
2628 | fprintf (stderr, HOST_WIDE_INT_PRINT_DEC, n_fpr); | |
2629 | putc ('\n', stderr); | |
2630 | } | |
dfafc897 FS |
2631 | |
2632 | t = build (MODIFY_EXPR, TREE_TYPE (gpr), gpr, build_int_2 (n_gpr, 0)); | |
2633 | TREE_SIDE_EFFECTS (t) = 1; | |
2634 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
2635 | ||
2636 | t = build (MODIFY_EXPR, TREE_TYPE (fpr), fpr, build_int_2 (n_fpr, 0)); | |
2637 | TREE_SIDE_EFFECTS (t) = 1; | |
2638 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
2639 | ||
2640 | /* Find the overflow area. */ | |
2641 | t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx); | |
2642 | if (words != 0) | |
2643 | t = build (PLUS_EXPR, TREE_TYPE (ovf), t, | |
2644 | build_int_2 (words * UNITS_PER_WORD, 0)); | |
2645 | t = build (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t); | |
2646 | TREE_SIDE_EFFECTS (t) = 1; | |
2647 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
2648 | ||
2649 | /* Find the register save area. */ | |
2650 | t = make_tree (TREE_TYPE (sav), virtual_stack_vars_rtx); | |
2651 | t = build (PLUS_EXPR, TREE_TYPE (sav), t, | |
2652 | build_int_2 (-RS6000_VARARGS_SIZE, -1)); | |
2653 | t = build (MODIFY_EXPR, TREE_TYPE (sav), sav, t); | |
2654 | TREE_SIDE_EFFECTS (t) = 1; | |
2655 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
2656 | } | |
2657 | ||
2658 | /* Implement va_arg. */ | |
2659 | ||
2660 | rtx | |
2661 | rs6000_va_arg (valist, type) | |
2662 | tree valist, type; | |
2663 | { | |
2664 | tree f_gpr, f_fpr, f_ovf, f_sav; | |
2665 | tree gpr, fpr, ovf, sav, reg, t, u; | |
2666 | int indirect_p, size, rsize, n_reg, sav_ofs, sav_scale; | |
2667 | rtx lab_false, lab_over, addr_rtx, r; | |
2668 | ||
9ebbca7d GK |
2669 | /* For AIX, the rule is that structures are passed left-aligned in |
2670 | their stack slot. However, GCC does not presently do this: | |
2671 | structures which are the same size as integer types are passed | |
2672 | right-aligned, as if they were in fact integers. This only | |
2673 | matters for structures of size 1 or 2, or 4 when TARGET_64BIT. */ | |
dfafc897 | 2674 | if (DEFAULT_ABI != ABI_V4 && DEFAULT_ABI != ABI_SOLARIS) |
9ebbca7d GK |
2675 | { |
2676 | HOST_WIDE_INT align, rounded_size; | |
2677 | enum machine_mode mode; | |
2678 | tree addr_tree; | |
2679 | ||
2680 | /* Compute the rounded size of the type. */ | |
2681 | align = PARM_BOUNDARY / BITS_PER_UNIT; | |
2682 | rounded_size = (((int_size_in_bytes (type) + align - 1) / align) | |
2683 | * align); | |
2684 | ||
2685 | addr_tree = valist; | |
2686 | ||
2687 | mode = TYPE_MODE (type); | |
2688 | if (mode != BLKmode) | |
2689 | { | |
2690 | HOST_WIDE_INT adj; | |
2691 | adj = TREE_INT_CST_LOW (TYPE_SIZE (type)) / BITS_PER_UNIT; | |
2692 | if (rounded_size > align) | |
2693 | adj = rounded_size; | |
2694 | ||
2695 | addr_tree = build (PLUS_EXPR, TREE_TYPE (addr_tree), addr_tree, | |
2696 | build_int_2 (rounded_size - adj, 0)); | |
2697 | } | |
2698 | ||
2699 | addr_rtx = expand_expr (addr_tree, NULL_RTX, Pmode, EXPAND_NORMAL); | |
2700 | addr_rtx = copy_to_reg (addr_rtx); | |
2701 | ||
2702 | /* Compute new value for AP. */ | |
2703 | t = build (MODIFY_EXPR, TREE_TYPE (valist), valist, | |
2704 | build (PLUS_EXPR, TREE_TYPE (valist), valist, | |
2705 | build_int_2 (rounded_size, 0))); | |
2706 | TREE_SIDE_EFFECTS (t) = 1; | |
2707 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
2708 | ||
2709 | return addr_rtx; | |
2710 | } | |
dfafc897 | 2711 | |
973a648b | 2712 | f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node)); |
dfafc897 FS |
2713 | f_fpr = TREE_CHAIN (f_gpr); |
2714 | f_ovf = TREE_CHAIN (f_fpr); | |
2715 | f_sav = TREE_CHAIN (f_ovf); | |
2716 | ||
8ebecc3b | 2717 | valist = build1 (INDIRECT_REF, TREE_TYPE (TREE_TYPE (valist)), valist); |
dfafc897 FS |
2718 | gpr = build (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr); |
2719 | fpr = build (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr); | |
2720 | ovf = build (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf); | |
2721 | sav = build (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav); | |
2722 | ||
2723 | size = int_size_in_bytes (type); | |
2724 | rsize = (size + UNITS_PER_WORD - 1) / UNITS_PER_WORD; | |
4cc833b7 | 2725 | |
dfafc897 | 2726 | if (AGGREGATE_TYPE_P (type) || TYPE_MODE (type) == TFmode) |
4cc833b7 | 2727 | { |
dfafc897 FS |
2728 | /* Aggregates and long doubles are passed by reference. */ |
2729 | indirect_p = 1; | |
2730 | reg = gpr; | |
2731 | n_reg = 1; | |
2732 | sav_ofs = 0; | |
2733 | sav_scale = 4; | |
2734 | size = rsize = UNITS_PER_WORD; | |
2735 | } | |
2736 | else if (FLOAT_TYPE_P (type) && ! TARGET_SOFT_FLOAT) | |
2737 | { | |
2738 | /* FP args go in FP registers, if present. */ | |
2739 | indirect_p = 0; | |
2740 | reg = fpr; | |
2741 | n_reg = 1; | |
2742 | sav_ofs = 8*4; | |
2743 | sav_scale = 8; | |
4cc833b7 | 2744 | } |
dfafc897 FS |
2745 | else |
2746 | { | |
2747 | /* Otherwise into GP registers. */ | |
2748 | indirect_p = 0; | |
2749 | reg = gpr; | |
2750 | n_reg = rsize; | |
2751 | sav_ofs = 0; | |
2752 | sav_scale = 4; | |
2753 | } | |
2754 | ||
a4f6c312 | 2755 | /* Pull the value out of the saved registers ... */ |
dfafc897 FS |
2756 | |
2757 | lab_false = gen_label_rtx (); | |
2758 | lab_over = gen_label_rtx (); | |
2759 | addr_rtx = gen_reg_rtx (Pmode); | |
2760 | ||
2761 | emit_cmp_and_jump_insns (expand_expr (reg, NULL_RTX, QImode, EXPAND_NORMAL), | |
2762 | GEN_INT (8 - n_reg + 1), | |
2763 | GE, const1_rtx, QImode, 1, 1, lab_false); | |
2c4974b7 | 2764 | |
dfafc897 FS |
2765 | /* Long long is aligned in the registers. */ |
2766 | if (n_reg > 1) | |
2c4974b7 | 2767 | { |
dfafc897 FS |
2768 | u = build (BIT_AND_EXPR, TREE_TYPE (reg), reg, |
2769 | build_int_2 (n_reg - 1, 0)); | |
2770 | u = build (PLUS_EXPR, TREE_TYPE (reg), reg, u); | |
2771 | u = build (MODIFY_EXPR, TREE_TYPE (reg), reg, u); | |
2772 | TREE_SIDE_EFFECTS (u) = 1; | |
2773 | expand_expr (u, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
2c4974b7 | 2774 | } |
dfafc897 FS |
2775 | |
2776 | if (sav_ofs) | |
2777 | t = build (PLUS_EXPR, ptr_type_node, sav, build_int_2 (sav_ofs, 0)); | |
2c4974b7 | 2778 | else |
dfafc897 | 2779 | t = sav; |
2c4974b7 | 2780 | |
dfafc897 FS |
2781 | u = build (POSTINCREMENT_EXPR, TREE_TYPE (reg), reg, build_int_2 (n_reg, 0)); |
2782 | TREE_SIDE_EFFECTS (u) = 1; | |
2c4974b7 | 2783 | |
dfafc897 FS |
2784 | u = build1 (CONVERT_EXPR, integer_type_node, u); |
2785 | TREE_SIDE_EFFECTS (u) = 1; | |
2c4974b7 | 2786 | |
dfafc897 FS |
2787 | u = build (MULT_EXPR, integer_type_node, u, build_int_2 (sav_scale, 0)); |
2788 | TREE_SIDE_EFFECTS (u) = 1; | |
2789 | ||
2790 | t = build (PLUS_EXPR, ptr_type_node, t, u); | |
2791 | TREE_SIDE_EFFECTS (t) = 1; | |
2792 | ||
2793 | r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL); | |
2794 | if (r != addr_rtx) | |
2795 | emit_move_insn (addr_rtx, r); | |
2796 | ||
2797 | emit_jump_insn (gen_jump (lab_over)); | |
2798 | emit_barrier (); | |
2799 | emit_label (lab_false); | |
2800 | ||
a4f6c312 | 2801 | /* ... otherwise out of the overflow area. */ |
dfafc897 FS |
2802 | |
2803 | /* Make sure we don't find reg 7 for the next int arg. */ | |
2804 | if (n_reg > 1) | |
2805 | { | |
2806 | t = build (MODIFY_EXPR, TREE_TYPE (reg), reg, build_int_2 (8, 0)); | |
2807 | TREE_SIDE_EFFECTS (t) = 1; | |
2808 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
2809 | } | |
2810 | ||
2811 | /* Care for on-stack alignment if needed. */ | |
2812 | if (rsize <= 1) | |
2813 | t = ovf; | |
2814 | else | |
2815 | { | |
2816 | t = build (PLUS_EXPR, TREE_TYPE (ovf), ovf, build_int_2 (7, 0)); | |
2817 | t = build (BIT_AND_EXPR, TREE_TYPE (t), t, build_int_2 (-8, -1)); | |
2818 | } | |
2819 | t = save_expr (t); | |
2820 | ||
2821 | r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL); | |
2822 | if (r != addr_rtx) | |
2823 | emit_move_insn (addr_rtx, r); | |
2824 | ||
2825 | t = build (PLUS_EXPR, TREE_TYPE (t), t, build_int_2 (size, 0)); | |
2826 | t = build (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t); | |
2827 | TREE_SIDE_EFFECTS (t) = 1; | |
2828 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
2829 | ||
2830 | emit_label (lab_over); | |
2831 | ||
2832 | if (indirect_p) | |
2833 | { | |
2834 | r = gen_rtx_MEM (Pmode, addr_rtx); | |
ba4828e0 | 2835 | set_mem_alias_set (r, get_varargs_alias_set ()); |
dfafc897 FS |
2836 | emit_move_insn (addr_rtx, r); |
2837 | } | |
2838 | ||
2839 | return addr_rtx; | |
4697a36c | 2840 | } |
5b5040b9 RK |
2841 | \f |
2842 | /* Generate a memory reference for expand_block_move, copying volatile, | |
2843 | and other bits from an original memory reference. */ | |
2844 | ||
2845 | static rtx | |
2846 | expand_block_move_mem (mode, addr, orig_mem) | |
2847 | enum machine_mode mode; | |
2848 | rtx addr; | |
2849 | rtx orig_mem; | |
2850 | { | |
39403d82 | 2851 | rtx mem = gen_rtx_MEM (mode, addr); |
b6c9286a | 2852 | |
c6df88cb | 2853 | MEM_COPY_ATTRIBUTES (mem, orig_mem); |
5b5040b9 RK |
2854 | return mem; |
2855 | } | |
2856 | ||
7e69e155 MM |
2857 | /* Expand a block move operation, and return 1 if successful. Return 0 |
2858 | if we should let the compiler generate normal code. | |
2859 | ||
2860 | operands[0] is the destination | |
2861 | operands[1] is the source | |
2862 | operands[2] is the length | |
2863 | operands[3] is the alignment */ | |
2864 | ||
3933e0e1 MM |
2865 | #define MAX_MOVE_REG 4 |
2866 | ||
7e69e155 MM |
2867 | int |
2868 | expand_block_move (operands) | |
2869 | rtx operands[]; | |
2870 | { | |
b6c9286a MM |
2871 | rtx orig_dest = operands[0]; |
2872 | rtx orig_src = operands[1]; | |
7e69e155 | 2873 | rtx bytes_rtx = operands[2]; |
7e69e155 | 2874 | rtx align_rtx = operands[3]; |
3933e0e1 | 2875 | int constp = (GET_CODE (bytes_rtx) == CONST_INT); |
5ee95df6 | 2876 | int align; |
3933e0e1 MM |
2877 | int bytes; |
2878 | int offset; | |
2879 | int num_reg; | |
2880 | int i; | |
7e69e155 MM |
2881 | rtx src_reg; |
2882 | rtx dest_reg; | |
3933e0e1 MM |
2883 | rtx src_addr; |
2884 | rtx dest_addr; | |
7e69e155 | 2885 | rtx tmp_reg; |
3933e0e1 | 2886 | rtx stores[MAX_MOVE_REG]; |
7e69e155 MM |
2887 | int move_bytes; |
2888 | ||
3933e0e1 | 2889 | /* If this is not a fixed size move, just call memcpy */ |
cc0d9ba8 | 2890 | if (! constp) |
3933e0e1 MM |
2891 | return 0; |
2892 | ||
5ee95df6 FS |
2893 | /* If this is not a fixed size alignment, abort */ |
2894 | if (GET_CODE (align_rtx) != CONST_INT) | |
2895 | abort (); | |
2896 | align = INTVAL (align_rtx); | |
2897 | ||
7e69e155 | 2898 | /* Anything to move? */ |
3933e0e1 MM |
2899 | bytes = INTVAL (bytes_rtx); |
2900 | if (bytes <= 0) | |
7e69e155 MM |
2901 | return 1; |
2902 | ||
3933e0e1 MM |
2903 | /* Don't support real large moves. If string instructions are not used, |
2904 | then don't generate more than 8 loads. */ | |
2905 | if (TARGET_STRING) | |
2906 | { | |
c81fc13e | 2907 | if (bytes > 8*4) |
3933e0e1 MM |
2908 | return 0; |
2909 | } | |
cc0d9ba8 | 2910 | else if (! STRICT_ALIGNMENT) |
3933e0e1 | 2911 | { |
c81fc13e DE |
2912 | if (TARGET_POWERPC64 && align >= 4) |
2913 | { | |
2914 | if (bytes > 8*8) | |
2915 | return 0; | |
2916 | } | |
2917 | else | |
2918 | if (bytes > 8*4) | |
2919 | return 0; | |
3933e0e1 MM |
2920 | } |
2921 | else if (bytes > 8*align) | |
7e69e155 MM |
2922 | return 0; |
2923 | ||
2924 | /* Move the address into scratch registers. */ | |
b6c9286a MM |
2925 | dest_reg = copy_addr_to_reg (XEXP (orig_dest, 0)); |
2926 | src_reg = copy_addr_to_reg (XEXP (orig_src, 0)); | |
7e69e155 | 2927 | |
3933e0e1 | 2928 | if (TARGET_STRING) /* string instructions are available */ |
7e69e155 | 2929 | { |
3933e0e1 | 2930 | for ( ; bytes > 0; bytes -= move_bytes) |
7e69e155 | 2931 | { |
3933e0e1 | 2932 | if (bytes > 24 /* move up to 32 bytes at a time */ |
cc0d9ba8 DE |
2933 | && ! fixed_regs[5] |
2934 | && ! fixed_regs[6] | |
2935 | && ! fixed_regs[7] | |
2936 | && ! fixed_regs[8] | |
2937 | && ! fixed_regs[9] | |
2938 | && ! fixed_regs[10] | |
2939 | && ! fixed_regs[11] | |
2940 | && ! fixed_regs[12]) | |
3933e0e1 MM |
2941 | { |
2942 | move_bytes = (bytes > 32) ? 32 : bytes; | |
cc0d9ba8 DE |
2943 | emit_insn (gen_movstrsi_8reg (expand_block_move_mem (BLKmode, |
2944 | dest_reg, | |
2945 | orig_dest), | |
2946 | expand_block_move_mem (BLKmode, | |
2947 | src_reg, | |
2948 | orig_src), | |
2949 | GEN_INT ((move_bytes == 32) | |
2950 | ? 0 : move_bytes), | |
4c64a852 | 2951 | align_rtx)); |
3933e0e1 MM |
2952 | } |
2953 | else if (bytes > 16 /* move up to 24 bytes at a time */ | |
f9562f27 DE |
2954 | && ! fixed_regs[5] |
2955 | && ! fixed_regs[6] | |
cc0d9ba8 DE |
2956 | && ! fixed_regs[7] |
2957 | && ! fixed_regs[8] | |
2958 | && ! fixed_regs[9] | |
f9562f27 | 2959 | && ! fixed_regs[10]) |
3933e0e1 MM |
2960 | { |
2961 | move_bytes = (bytes > 24) ? 24 : bytes; | |
cc0d9ba8 DE |
2962 | emit_insn (gen_movstrsi_6reg (expand_block_move_mem (BLKmode, |
2963 | dest_reg, | |
2964 | orig_dest), | |
2965 | expand_block_move_mem (BLKmode, | |
2966 | src_reg, | |
2967 | orig_src), | |
3933e0e1 | 2968 | GEN_INT (move_bytes), |
4c64a852 | 2969 | align_rtx)); |
3933e0e1 MM |
2970 | } |
2971 | else if (bytes > 8 /* move up to 16 bytes at a time */ | |
f9562f27 DE |
2972 | && ! fixed_regs[5] |
2973 | && ! fixed_regs[6] | |
2974 | && ! fixed_regs[7] | |
2975 | && ! fixed_regs[8]) | |
3933e0e1 MM |
2976 | { |
2977 | move_bytes = (bytes > 16) ? 16 : bytes; | |
cc0d9ba8 DE |
2978 | emit_insn (gen_movstrsi_4reg (expand_block_move_mem (BLKmode, |
2979 | dest_reg, | |
2980 | orig_dest), | |
2981 | expand_block_move_mem (BLKmode, | |
2982 | src_reg, | |
2983 | orig_src), | |
3933e0e1 | 2984 | GEN_INT (move_bytes), |
4c64a852 | 2985 | align_rtx)); |
3933e0e1 | 2986 | } |
acad7ed3 | 2987 | else if (bytes >= 8 && TARGET_POWERPC64 |
a4f6c312 SS |
2988 | /* 64-bit loads and stores require word-aligned |
2989 | displacements. */ | |
2990 | && (align >= 8 || (! STRICT_ALIGNMENT && align >= 4))) | |
acad7ed3 DE |
2991 | { |
2992 | move_bytes = 8; | |
2993 | tmp_reg = gen_reg_rtx (DImode); | |
2994 | emit_move_insn (tmp_reg, | |
2995 | expand_block_move_mem (DImode, | |
2eba1afa | 2996 | src_reg, orig_src)); |
acad7ed3 | 2997 | emit_move_insn (expand_block_move_mem (DImode, |
2eba1afa | 2998 | dest_reg, orig_dest), |
acad7ed3 DE |
2999 | tmp_reg); |
3000 | } | |
3001 | else if (bytes > 4) | |
3933e0e1 MM |
3002 | { /* move up to 8 bytes at a time */ |
3003 | move_bytes = (bytes > 8) ? 8 : bytes; | |
cc0d9ba8 DE |
3004 | emit_insn (gen_movstrsi_2reg (expand_block_move_mem (BLKmode, |
3005 | dest_reg, | |
3006 | orig_dest), | |
3007 | expand_block_move_mem (BLKmode, | |
3008 | src_reg, | |
3009 | orig_src), | |
3933e0e1 | 3010 | GEN_INT (move_bytes), |
4c64a852 | 3011 | align_rtx)); |
3933e0e1 | 3012 | } |
cc0d9ba8 | 3013 | else if (bytes >= 4 && (align >= 4 || ! STRICT_ALIGNMENT)) |
3933e0e1 MM |
3014 | { /* move 4 bytes */ |
3015 | move_bytes = 4; | |
3016 | tmp_reg = gen_reg_rtx (SImode); | |
cc0d9ba8 DE |
3017 | emit_move_insn (tmp_reg, |
3018 | expand_block_move_mem (SImode, | |
3019 | src_reg, orig_src)); | |
3020 | emit_move_insn (expand_block_move_mem (SImode, | |
3021 | dest_reg, orig_dest), | |
3022 | tmp_reg); | |
3933e0e1 | 3023 | } |
cc0d9ba8 | 3024 | else if (bytes == 2 && (align >= 2 || ! STRICT_ALIGNMENT)) |
3933e0e1 MM |
3025 | { /* move 2 bytes */ |
3026 | move_bytes = 2; | |
3027 | tmp_reg = gen_reg_rtx (HImode); | |
cc0d9ba8 DE |
3028 | emit_move_insn (tmp_reg, |
3029 | expand_block_move_mem (HImode, | |
3030 | src_reg, orig_src)); | |
3031 | emit_move_insn (expand_block_move_mem (HImode, | |
3032 | dest_reg, orig_dest), | |
3033 | tmp_reg); | |
3933e0e1 MM |
3034 | } |
3035 | else if (bytes == 1) /* move 1 byte */ | |
3036 | { | |
3037 | move_bytes = 1; | |
3038 | tmp_reg = gen_reg_rtx (QImode); | |
cc0d9ba8 DE |
3039 | emit_move_insn (tmp_reg, |
3040 | expand_block_move_mem (QImode, | |
3041 | src_reg, orig_src)); | |
3042 | emit_move_insn (expand_block_move_mem (QImode, | |
3043 | dest_reg, orig_dest), | |
3044 | tmp_reg); | |
3933e0e1 MM |
3045 | } |
3046 | else | |
3047 | { /* move up to 4 bytes at a time */ | |
3048 | move_bytes = (bytes > 4) ? 4 : bytes; | |
cc0d9ba8 DE |
3049 | emit_insn (gen_movstrsi_1reg (expand_block_move_mem (BLKmode, |
3050 | dest_reg, | |
3051 | orig_dest), | |
3052 | expand_block_move_mem (BLKmode, | |
3053 | src_reg, | |
3054 | orig_src), | |
3933e0e1 | 3055 | GEN_INT (move_bytes), |
4c64a852 | 3056 | align_rtx)); |
3933e0e1 | 3057 | } |
4c64a852 | 3058 | |
015892ee RK |
3059 | if (bytes > move_bytes) |
3060 | { | |
cc0d9ba8 DE |
3061 | if (! TARGET_POWERPC64) |
3062 | { | |
3063 | emit_insn (gen_addsi3 (src_reg, src_reg, | |
3064 | GEN_INT (move_bytes))); | |
3065 | emit_insn (gen_addsi3 (dest_reg, dest_reg, | |
3066 | GEN_INT (move_bytes))); | |
3067 | } | |
3068 | else | |
3069 | { | |
3070 | emit_insn (gen_adddi3 (src_reg, src_reg, | |
3071 | GEN_INT (move_bytes))); | |
3072 | emit_insn (gen_adddi3 (dest_reg, dest_reg, | |
3073 | GEN_INT (move_bytes))); | |
3074 | } | |
015892ee | 3075 | } |
4c64a852 | 3076 | } |
3933e0e1 MM |
3077 | } |
3078 | ||
3079 | else /* string instructions not available */ | |
3080 | { | |
3081 | num_reg = offset = 0; | |
3082 | for ( ; bytes > 0; (bytes -= move_bytes), (offset += move_bytes)) | |
7e69e155 | 3083 | { |
3933e0e1 MM |
3084 | /* Calculate the correct offset for src/dest */ |
3085 | if (offset == 0) | |
7e69e155 | 3086 | { |
3933e0e1 MM |
3087 | src_addr = src_reg; |
3088 | dest_addr = dest_reg; | |
3089 | } | |
3090 | else | |
3091 | { | |
c5c76735 JL |
3092 | src_addr = plus_constant (src_reg, offset); |
3093 | dest_addr = plus_constant (dest_reg, offset); | |
3933e0e1 MM |
3094 | } |
3095 | ||
cc0d9ba8 DE |
3096 | /* Generate the appropriate load and store, saving the stores |
3097 | for later. */ | |
3098 | if (bytes >= 8 && TARGET_POWERPC64 | |
a4f6c312 SS |
3099 | /* 64-bit loads and stores require word-aligned |
3100 | displacements. */ | |
cc0d9ba8 | 3101 | && (align >= 8 || (! STRICT_ALIGNMENT && align >= 4))) |
b6c9286a MM |
3102 | { |
3103 | move_bytes = 8; | |
3104 | tmp_reg = gen_reg_rtx (DImode); | |
cc0d9ba8 DE |
3105 | emit_insn (gen_movdi (tmp_reg, |
3106 | expand_block_move_mem (DImode, | |
3107 | src_addr, | |
3108 | orig_src))); | |
3109 | stores[num_reg++] = gen_movdi (expand_block_move_mem (DImode, | |
3110 | dest_addr, | |
3111 | orig_dest), | |
3112 | tmp_reg); | |
b6c9286a | 3113 | } |
cc0d9ba8 | 3114 | else if (bytes >= 4 && (align >= 4 || ! STRICT_ALIGNMENT)) |
3933e0e1 MM |
3115 | { |
3116 | move_bytes = 4; | |
3117 | tmp_reg = gen_reg_rtx (SImode); | |
cc0d9ba8 DE |
3118 | emit_insn (gen_movsi (tmp_reg, |
3119 | expand_block_move_mem (SImode, | |
3120 | src_addr, | |
3121 | orig_src))); | |
3122 | stores[num_reg++] = gen_movsi (expand_block_move_mem (SImode, | |
3123 | dest_addr, | |
3124 | orig_dest), | |
3125 | tmp_reg); | |
3933e0e1 | 3126 | } |
cc0d9ba8 | 3127 | else if (bytes >= 2 && (align >= 2 || ! STRICT_ALIGNMENT)) |
3933e0e1 MM |
3128 | { |
3129 | move_bytes = 2; | |
3130 | tmp_reg = gen_reg_rtx (HImode); | |
c81fc13e | 3131 | emit_insn (gen_movhi (tmp_reg, |
cc0d9ba8 DE |
3132 | expand_block_move_mem (HImode, |
3133 | src_addr, | |
3134 | orig_src))); | |
3135 | stores[num_reg++] = gen_movhi (expand_block_move_mem (HImode, | |
3136 | dest_addr, | |
3137 | orig_dest), | |
3138 | tmp_reg); | |
3933e0e1 MM |
3139 | } |
3140 | else | |
3141 | { | |
3142 | move_bytes = 1; | |
3143 | tmp_reg = gen_reg_rtx (QImode); | |
c81fc13e | 3144 | emit_insn (gen_movqi (tmp_reg, |
cc0d9ba8 DE |
3145 | expand_block_move_mem (QImode, |
3146 | src_addr, | |
3147 | orig_src))); | |
3148 | stores[num_reg++] = gen_movqi (expand_block_move_mem (QImode, | |
3149 | dest_addr, | |
3150 | orig_dest), | |
a4f6c312 | 3151 | tmp_reg); |
3933e0e1 MM |
3152 | } |
3153 | ||
3154 | if (num_reg >= MAX_MOVE_REG) | |
3155 | { | |
3156 | for (i = 0; i < num_reg; i++) | |
3157 | emit_insn (stores[i]); | |
3158 | num_reg = 0; | |
7e69e155 MM |
3159 | } |
3160 | } | |
3933e0e1 | 3161 | |
b6c9286a MM |
3162 | for (i = 0; i < num_reg; i++) |
3163 | emit_insn (stores[i]); | |
7e69e155 MM |
3164 | } |
3165 | ||
3166 | return 1; | |
3167 | } | |
3168 | ||
9878760c RK |
3169 | \f |
3170 | /* Return 1 if OP is a load multiple operation. It is known to be a | |
3171 | PARALLEL and the first section will be tested. */ | |
3172 | ||
3173 | int | |
3174 | load_multiple_operation (op, mode) | |
3175 | rtx op; | |
296b8152 | 3176 | enum machine_mode mode ATTRIBUTE_UNUSED; |
9878760c RK |
3177 | { |
3178 | int count = XVECLEN (op, 0); | |
e2c953b6 | 3179 | unsigned int dest_regno; |
9878760c RK |
3180 | rtx src_addr; |
3181 | int i; | |
3182 | ||
3183 | /* Perform a quick check so we don't blow up below. */ | |
3184 | if (count <= 1 | |
3185 | || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
3186 | || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG | |
3187 | || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM) | |
3188 | return 0; | |
3189 | ||
3190 | dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0))); | |
3191 | src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0); | |
3192 | ||
3193 | for (i = 1; i < count; i++) | |
3194 | { | |
3195 | rtx elt = XVECEXP (op, 0, i); | |
3196 | ||
3197 | if (GET_CODE (elt) != SET | |
3198 | || GET_CODE (SET_DEST (elt)) != REG | |
3199 | || GET_MODE (SET_DEST (elt)) != SImode | |
3200 | || REGNO (SET_DEST (elt)) != dest_regno + i | |
3201 | || GET_CODE (SET_SRC (elt)) != MEM | |
3202 | || GET_MODE (SET_SRC (elt)) != SImode | |
3203 | || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS | |
3204 | || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr) | |
3205 | || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT | |
3206 | || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != i * 4) | |
3207 | return 0; | |
3208 | } | |
3209 | ||
3210 | return 1; | |
3211 | } | |
3212 | ||
3213 | /* Similar, but tests for store multiple. Here, the second vector element | |
3214 | is a CLOBBER. It will be tested later. */ | |
3215 | ||
3216 | int | |
3217 | store_multiple_operation (op, mode) | |
3218 | rtx op; | |
296b8152 | 3219 | enum machine_mode mode ATTRIBUTE_UNUSED; |
9878760c RK |
3220 | { |
3221 | int count = XVECLEN (op, 0) - 1; | |
e2c953b6 | 3222 | unsigned int src_regno; |
9878760c RK |
3223 | rtx dest_addr; |
3224 | int i; | |
3225 | ||
3226 | /* Perform a quick check so we don't blow up below. */ | |
3227 | if (count <= 1 | |
3228 | || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
3229 | || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM | |
3230 | || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG) | |
3231 | return 0; | |
3232 | ||
3233 | src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0))); | |
3234 | dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0); | |
3235 | ||
3236 | for (i = 1; i < count; i++) | |
3237 | { | |
3238 | rtx elt = XVECEXP (op, 0, i + 1); | |
3239 | ||
3240 | if (GET_CODE (elt) != SET | |
3241 | || GET_CODE (SET_SRC (elt)) != REG | |
3242 | || GET_MODE (SET_SRC (elt)) != SImode | |
3243 | || REGNO (SET_SRC (elt)) != src_regno + i | |
3244 | || GET_CODE (SET_DEST (elt)) != MEM | |
3245 | || GET_MODE (SET_DEST (elt)) != SImode | |
3246 | || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS | |
3247 | || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr) | |
3248 | || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT | |
3249 | || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != i * 4) | |
3250 | return 0; | |
3251 | } | |
3252 | ||
3253 | return 1; | |
3254 | } | |
9ebbca7d | 3255 | |
a4f6c312 | 3256 | /* Return 1 for an PARALLEL suitable for mtcrf. */ |
9ebbca7d GK |
3257 | |
3258 | int | |
3259 | mtcrf_operation (op, mode) | |
3260 | rtx op; | |
3261 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
3262 | { | |
3263 | int count = XVECLEN (op, 0); | |
3264 | int i; | |
9ebbca7d GK |
3265 | rtx src_reg; |
3266 | ||
3267 | /* Perform a quick check so we don't blow up below. */ | |
e35b9579 GK |
3268 | if (count < 1 |
3269 | || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
3270 | || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC | |
3271 | || XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2) | |
9ebbca7d | 3272 | return 0; |
e35b9579 | 3273 | src_reg = XVECEXP (SET_SRC (XVECEXP (op, 0, 0)), 0, 0); |
9ebbca7d GK |
3274 | |
3275 | if (GET_CODE (src_reg) != REG | |
3276 | || GET_MODE (src_reg) != SImode | |
3277 | || ! INT_REGNO_P (REGNO (src_reg))) | |
3278 | return 0; | |
3279 | ||
e35b9579 | 3280 | for (i = 0; i < count; i++) |
9ebbca7d GK |
3281 | { |
3282 | rtx exp = XVECEXP (op, 0, i); | |
3283 | rtx unspec; | |
3284 | int maskval; | |
3285 | ||
3286 | if (GET_CODE (exp) != SET | |
3287 | || GET_CODE (SET_DEST (exp)) != REG | |
3288 | || GET_MODE (SET_DEST (exp)) != CCmode | |
3289 | || ! CR_REGNO_P (REGNO (SET_DEST (exp)))) | |
3290 | return 0; | |
3291 | unspec = SET_SRC (exp); | |
3292 | maskval = 1 << (MAX_CR_REGNO - REGNO (SET_DEST (exp))); | |
9ebbca7d GK |
3293 | |
3294 | if (GET_CODE (unspec) != UNSPEC | |
3295 | || XINT (unspec, 1) != 20 | |
3296 | || XVECLEN (unspec, 0) != 2 | |
3297 | || XVECEXP (unspec, 0, 0) != src_reg | |
3298 | || GET_CODE (XVECEXP (unspec, 0, 1)) != CONST_INT | |
3299 | || INTVAL (XVECEXP (unspec, 0, 1)) != maskval) | |
3300 | return 0; | |
3301 | } | |
e35b9579 | 3302 | return 1; |
9ebbca7d GK |
3303 | } |
3304 | ||
a4f6c312 | 3305 | /* Return 1 for an PARALLEL suitable for lmw. */ |
9ebbca7d GK |
3306 | |
3307 | int | |
3308 | lmw_operation (op, mode) | |
3309 | rtx op; | |
3310 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
3311 | { | |
3312 | int count = XVECLEN (op, 0); | |
e2c953b6 | 3313 | unsigned int dest_regno; |
9ebbca7d | 3314 | rtx src_addr; |
e2c953b6 | 3315 | unsigned int base_regno; |
9ebbca7d GK |
3316 | HOST_WIDE_INT offset; |
3317 | int i; | |
3318 | ||
3319 | /* Perform a quick check so we don't blow up below. */ | |
3320 | if (count <= 1 | |
3321 | || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
3322 | || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG | |
3323 | || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM) | |
3324 | return 0; | |
3325 | ||
3326 | dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0))); | |
3327 | src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0); | |
3328 | ||
3329 | if (dest_regno > 31 | |
e2c953b6 | 3330 | || count != 32 - (int) dest_regno) |
9ebbca7d GK |
3331 | return 0; |
3332 | ||
258bfae2 | 3333 | if (LEGITIMATE_INDIRECT_ADDRESS_P (src_addr, 0)) |
9ebbca7d GK |
3334 | { |
3335 | offset = 0; | |
3336 | base_regno = REGNO (src_addr); | |
3337 | if (base_regno == 0) | |
3338 | return 0; | |
3339 | } | |
258bfae2 | 3340 | else if (LEGITIMATE_OFFSET_ADDRESS_P (SImode, src_addr, 0)) |
9ebbca7d GK |
3341 | { |
3342 | offset = INTVAL (XEXP (src_addr, 1)); | |
3343 | base_regno = REGNO (XEXP (src_addr, 0)); | |
3344 | } | |
3345 | else | |
3346 | return 0; | |
3347 | ||
3348 | for (i = 0; i < count; i++) | |
3349 | { | |
3350 | rtx elt = XVECEXP (op, 0, i); | |
3351 | rtx newaddr; | |
3352 | rtx addr_reg; | |
3353 | HOST_WIDE_INT newoffset; | |
3354 | ||
3355 | if (GET_CODE (elt) != SET | |
3356 | || GET_CODE (SET_DEST (elt)) != REG | |
3357 | || GET_MODE (SET_DEST (elt)) != SImode | |
3358 | || REGNO (SET_DEST (elt)) != dest_regno + i | |
3359 | || GET_CODE (SET_SRC (elt)) != MEM | |
3360 | || GET_MODE (SET_SRC (elt)) != SImode) | |
3361 | return 0; | |
3362 | newaddr = XEXP (SET_SRC (elt), 0); | |
258bfae2 | 3363 | if (LEGITIMATE_INDIRECT_ADDRESS_P (newaddr, 0)) |
9ebbca7d GK |
3364 | { |
3365 | newoffset = 0; | |
3366 | addr_reg = newaddr; | |
3367 | } | |
258bfae2 | 3368 | else if (LEGITIMATE_OFFSET_ADDRESS_P (SImode, newaddr, 0)) |
9ebbca7d GK |
3369 | { |
3370 | addr_reg = XEXP (newaddr, 0); | |
3371 | newoffset = INTVAL (XEXP (newaddr, 1)); | |
3372 | } | |
3373 | else | |
3374 | return 0; | |
3375 | if (REGNO (addr_reg) != base_regno | |
3376 | || newoffset != offset + 4 * i) | |
3377 | return 0; | |
3378 | } | |
3379 | ||
3380 | return 1; | |
3381 | } | |
3382 | ||
a4f6c312 | 3383 | /* Return 1 for an PARALLEL suitable for stmw. */ |
9ebbca7d GK |
3384 | |
3385 | int | |
3386 | stmw_operation (op, mode) | |
3387 | rtx op; | |
3388 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
3389 | { | |
3390 | int count = XVECLEN (op, 0); | |
e2c953b6 | 3391 | unsigned int src_regno; |
9ebbca7d | 3392 | rtx dest_addr; |
e2c953b6 | 3393 | unsigned int base_regno; |
9ebbca7d GK |
3394 | HOST_WIDE_INT offset; |
3395 | int i; | |
3396 | ||
3397 | /* Perform a quick check so we don't blow up below. */ | |
3398 | if (count <= 1 | |
3399 | || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
3400 | || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM | |
3401 | || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG) | |
3402 | return 0; | |
3403 | ||
3404 | src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0))); | |
3405 | dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0); | |
3406 | ||
3407 | if (src_regno > 31 | |
e2c953b6 | 3408 | || count != 32 - (int) src_regno) |
9ebbca7d GK |
3409 | return 0; |
3410 | ||
258bfae2 | 3411 | if (LEGITIMATE_INDIRECT_ADDRESS_P (dest_addr, 0)) |
9ebbca7d GK |
3412 | { |
3413 | offset = 0; | |
3414 | base_regno = REGNO (dest_addr); | |
3415 | if (base_regno == 0) | |
3416 | return 0; | |
3417 | } | |
258bfae2 | 3418 | else if (LEGITIMATE_OFFSET_ADDRESS_P (SImode, dest_addr, 0)) |
9ebbca7d GK |
3419 | { |
3420 | offset = INTVAL (XEXP (dest_addr, 1)); | |
3421 | base_regno = REGNO (XEXP (dest_addr, 0)); | |
3422 | } | |
3423 | else | |
3424 | return 0; | |
3425 | ||
3426 | for (i = 0; i < count; i++) | |
3427 | { | |
3428 | rtx elt = XVECEXP (op, 0, i); | |
3429 | rtx newaddr; | |
3430 | rtx addr_reg; | |
3431 | HOST_WIDE_INT newoffset; | |
3432 | ||
3433 | if (GET_CODE (elt) != SET | |
3434 | || GET_CODE (SET_SRC (elt)) != REG | |
3435 | || GET_MODE (SET_SRC (elt)) != SImode | |
3436 | || REGNO (SET_SRC (elt)) != src_regno + i | |
3437 | || GET_CODE (SET_DEST (elt)) != MEM | |
3438 | || GET_MODE (SET_DEST (elt)) != SImode) | |
3439 | return 0; | |
3440 | newaddr = XEXP (SET_DEST (elt), 0); | |
258bfae2 | 3441 | if (LEGITIMATE_INDIRECT_ADDRESS_P (newaddr, 0)) |
9ebbca7d GK |
3442 | { |
3443 | newoffset = 0; | |
3444 | addr_reg = newaddr; | |
3445 | } | |
258bfae2 | 3446 | else if (LEGITIMATE_OFFSET_ADDRESS_P (SImode, newaddr, 0)) |
9ebbca7d GK |
3447 | { |
3448 | addr_reg = XEXP (newaddr, 0); | |
3449 | newoffset = INTVAL (XEXP (newaddr, 1)); | |
3450 | } | |
3451 | else | |
3452 | return 0; | |
3453 | if (REGNO (addr_reg) != base_regno | |
3454 | || newoffset != offset + 4 * i) | |
3455 | return 0; | |
3456 | } | |
3457 | ||
3458 | return 1; | |
3459 | } | |
9878760c | 3460 | \f |
a4f6c312 SS |
3461 | /* A validation routine: say whether CODE, a condition code, and MODE |
3462 | match. The other alternatives either don't make sense or should | |
3463 | never be generated. */ | |
39a10a29 | 3464 | |
39a10a29 GK |
3465 | static void |
3466 | validate_condition_mode (code, mode) | |
3467 | enum rtx_code code; | |
3468 | enum machine_mode mode; | |
3469 | { | |
3470 | if (GET_RTX_CLASS (code) != '<' | |
3471 | || GET_MODE_CLASS (mode) != MODE_CC) | |
3472 | abort (); | |
3473 | ||
3474 | /* These don't make sense. */ | |
3475 | if ((code == GT || code == LT || code == GE || code == LE) | |
3476 | && mode == CCUNSmode) | |
3477 | abort (); | |
3478 | ||
3479 | if ((code == GTU || code == LTU || code == GEU || code == LEU) | |
3480 | && mode != CCUNSmode) | |
3481 | abort (); | |
3482 | ||
3483 | if (mode != CCFPmode | |
3484 | && (code == ORDERED || code == UNORDERED | |
3485 | || code == UNEQ || code == LTGT | |
3486 | || code == UNGT || code == UNLT | |
3487 | || code == UNGE || code == UNLE)) | |
a4f6c312 | 3488 | abort (); |
39a10a29 | 3489 | |
de6c5979 BL |
3490 | /* These should never be generated except for |
3491 | flag_unsafe_math_optimizations. */ | |
39a10a29 | 3492 | if (mode == CCFPmode |
de6c5979 | 3493 | && ! flag_unsafe_math_optimizations |
39a10a29 GK |
3494 | && (code == LE || code == GE |
3495 | || code == UNEQ || code == LTGT | |
3496 | || code == UNGT || code == UNLT)) | |
3497 | abort (); | |
3498 | ||
3499 | /* These are invalid; the information is not there. */ | |
3500 | if (mode == CCEQmode | |
3501 | && code != EQ && code != NE) | |
3502 | abort (); | |
3503 | } | |
3504 | ||
9878760c RK |
3505 | /* Return 1 if OP is a comparison operation that is valid for a branch insn. |
3506 | We only check the opcode against the mode of the CC value here. */ | |
3507 | ||
3508 | int | |
3509 | branch_comparison_operator (op, mode) | |
592696dd | 3510 | rtx op; |
296b8152 | 3511 | enum machine_mode mode ATTRIBUTE_UNUSED; |
9878760c RK |
3512 | { |
3513 | enum rtx_code code = GET_CODE (op); | |
3514 | enum machine_mode cc_mode; | |
3515 | ||
3516 | if (GET_RTX_CLASS (code) != '<') | |
3517 | return 0; | |
3518 | ||
3519 | cc_mode = GET_MODE (XEXP (op, 0)); | |
3520 | if (GET_MODE_CLASS (cc_mode) != MODE_CC) | |
3521 | return 0; | |
3522 | ||
39a10a29 | 3523 | validate_condition_mode (code, cc_mode); |
9878760c | 3524 | |
39a10a29 GK |
3525 | return 1; |
3526 | } | |
3527 | ||
3528 | /* Return 1 if OP is a comparison operation that is valid for a branch | |
3529 | insn and which is true if the corresponding bit in the CC register | |
3530 | is set. */ | |
3531 | ||
3532 | int | |
3533 | branch_positive_comparison_operator (op, mode) | |
592696dd | 3534 | rtx op; |
39a10a29 GK |
3535 | enum machine_mode mode; |
3536 | { | |
3537 | enum rtx_code code; | |
3538 | ||
3539 | if (! branch_comparison_operator (op, mode)) | |
9878760c RK |
3540 | return 0; |
3541 | ||
39a10a29 GK |
3542 | code = GET_CODE (op); |
3543 | return (code == EQ || code == LT || code == GT | |
3544 | || code == LTU || code == GTU | |
3545 | || code == UNORDERED); | |
9878760c RK |
3546 | } |
3547 | ||
3548 | /* Return 1 if OP is a comparison operation that is valid for an scc insn. | |
3549 | We check the opcode against the mode of the CC value and disallow EQ or | |
3550 | NE comparisons for integers. */ | |
3551 | ||
3552 | int | |
3553 | scc_comparison_operator (op, mode) | |
592696dd | 3554 | rtx op; |
9878760c RK |
3555 | enum machine_mode mode; |
3556 | { | |
3557 | enum rtx_code code = GET_CODE (op); | |
3558 | enum machine_mode cc_mode; | |
3559 | ||
3560 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
3561 | return 0; | |
3562 | ||
3563 | if (GET_RTX_CLASS (code) != '<') | |
3564 | return 0; | |
3565 | ||
3566 | cc_mode = GET_MODE (XEXP (op, 0)); | |
3567 | if (GET_MODE_CLASS (cc_mode) != MODE_CC) | |
3568 | return 0; | |
3569 | ||
39a10a29 | 3570 | validate_condition_mode (code, cc_mode); |
9878760c | 3571 | |
39a10a29 | 3572 | if (code == NE && cc_mode != CCFPmode) |
c5defebb RK |
3573 | return 0; |
3574 | ||
9878760c RK |
3575 | return 1; |
3576 | } | |
e0cd0770 JC |
3577 | |
3578 | int | |
3579 | trap_comparison_operator (op, mode) | |
3580 | rtx op; | |
3581 | enum machine_mode mode; | |
3582 | { | |
3583 | if (mode != VOIDmode && mode != GET_MODE (op)) | |
3584 | return 0; | |
39a10a29 | 3585 | return GET_RTX_CLASS (GET_CODE (op)) == '<'; |
e0cd0770 | 3586 | } |
dfbdccdb GK |
3587 | |
3588 | int | |
3589 | boolean_operator (op, mode) | |
3590 | rtx op; | |
3591 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
3592 | { | |
3593 | enum rtx_code code = GET_CODE (op); | |
3594 | return (code == AND || code == IOR || code == XOR); | |
3595 | } | |
1d328b19 GK |
3596 | |
3597 | int | |
3598 | boolean_or_operator (op, mode) | |
3599 | rtx op; | |
3600 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
3601 | { | |
3602 | enum rtx_code code = GET_CODE (op); | |
3603 | return (code == IOR || code == XOR); | |
3604 | } | |
50a0b056 GK |
3605 | |
3606 | int | |
3607 | min_max_operator (op, mode) | |
3608 | rtx op; | |
3609 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
3610 | { | |
3611 | enum rtx_code code = GET_CODE (op); | |
3612 | return (code == SMIN || code == SMAX || code == UMIN || code == UMAX); | |
3613 | } | |
9878760c RK |
3614 | \f |
3615 | /* Return 1 if ANDOP is a mask that has no bits on that are not in the | |
3616 | mask required to convert the result of a rotate insn into a shift | |
3617 | left insn of SHIFTOP bits. Both are known to be CONST_INT. */ | |
3618 | ||
3619 | int | |
3620 | includes_lshift_p (shiftop, andop) | |
592696dd SS |
3621 | rtx shiftop; |
3622 | rtx andop; | |
9878760c | 3623 | { |
e2c953b6 DE |
3624 | unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0; |
3625 | ||
3626 | shift_mask <<= INTVAL (shiftop); | |
9878760c RK |
3627 | |
3628 | return (INTVAL (andop) & ~shift_mask) == 0; | |
3629 | } | |
3630 | ||
3631 | /* Similar, but for right shift. */ | |
3632 | ||
3633 | int | |
3634 | includes_rshift_p (shiftop, andop) | |
592696dd SS |
3635 | rtx shiftop; |
3636 | rtx andop; | |
9878760c | 3637 | { |
a7653a2c | 3638 | unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0; |
9878760c RK |
3639 | |
3640 | shift_mask >>= INTVAL (shiftop); | |
3641 | ||
e2c953b6 DE |
3642 | return (INTVAL (andop) & ~shift_mask) == 0; |
3643 | } | |
3644 | ||
c5059423 AM |
3645 | /* Return 1 if ANDOP is a mask suitable for use with an rldic insn |
3646 | to perform a left shift. It must have exactly SHIFTOP least | |
3647 | signifigant 0's, then one or more 1's, then zero or more 0's. */ | |
e2c953b6 DE |
3648 | |
3649 | int | |
c5059423 | 3650 | includes_rldic_lshift_p (shiftop, andop) |
592696dd SS |
3651 | rtx shiftop; |
3652 | rtx andop; | |
e2c953b6 | 3653 | { |
c5059423 AM |
3654 | if (GET_CODE (andop) == CONST_INT) |
3655 | { | |
02071907 | 3656 | HOST_WIDE_INT c, lsb, shift_mask; |
e2c953b6 | 3657 | |
c5059423 | 3658 | c = INTVAL (andop); |
02071907 | 3659 | if (c == 0 || c == ~0) |
c5059423 | 3660 | return 0; |
e2c953b6 | 3661 | |
02071907 | 3662 | shift_mask = ~0; |
c5059423 AM |
3663 | shift_mask <<= INTVAL (shiftop); |
3664 | ||
3665 | /* Find the least signifigant one bit. */ | |
3666 | lsb = c & -c; | |
3667 | ||
3668 | /* It must coincide with the LSB of the shift mask. */ | |
3669 | if (-lsb != shift_mask) | |
3670 | return 0; | |
e2c953b6 | 3671 | |
c5059423 AM |
3672 | /* Invert to look for the next transition (if any). */ |
3673 | c = ~c; | |
3674 | ||
3675 | /* Remove the low group of ones (originally low group of zeros). */ | |
3676 | c &= -lsb; | |
3677 | ||
3678 | /* Again find the lsb, and check we have all 1's above. */ | |
3679 | lsb = c & -c; | |
3680 | return c == -lsb; | |
3681 | } | |
3682 | else if (GET_CODE (andop) == CONST_DOUBLE | |
3683 | && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode)) | |
3684 | { | |
02071907 AM |
3685 | HOST_WIDE_INT low, high, lsb; |
3686 | HOST_WIDE_INT shift_mask_low, shift_mask_high; | |
c5059423 AM |
3687 | |
3688 | low = CONST_DOUBLE_LOW (andop); | |
3689 | if (HOST_BITS_PER_WIDE_INT < 64) | |
3690 | high = CONST_DOUBLE_HIGH (andop); | |
3691 | ||
3692 | if ((low == 0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == 0)) | |
02071907 | 3693 | || (low == ~0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0))) |
c5059423 AM |
3694 | return 0; |
3695 | ||
3696 | if (HOST_BITS_PER_WIDE_INT < 64 && low == 0) | |
3697 | { | |
02071907 | 3698 | shift_mask_high = ~0; |
c5059423 AM |
3699 | if (INTVAL (shiftop) > 32) |
3700 | shift_mask_high <<= INTVAL (shiftop) - 32; | |
3701 | ||
3702 | lsb = high & -high; | |
3703 | ||
3704 | if (-lsb != shift_mask_high || INTVAL (shiftop) < 32) | |
3705 | return 0; | |
3706 | ||
3707 | high = ~high; | |
3708 | high &= -lsb; | |
3709 | ||
3710 | lsb = high & -high; | |
3711 | return high == -lsb; | |
3712 | } | |
3713 | ||
02071907 | 3714 | shift_mask_low = ~0; |
c5059423 AM |
3715 | shift_mask_low <<= INTVAL (shiftop); |
3716 | ||
3717 | lsb = low & -low; | |
3718 | ||
3719 | if (-lsb != shift_mask_low) | |
3720 | return 0; | |
3721 | ||
3722 | if (HOST_BITS_PER_WIDE_INT < 64) | |
3723 | high = ~high; | |
3724 | low = ~low; | |
3725 | low &= -lsb; | |
3726 | ||
3727 | if (HOST_BITS_PER_WIDE_INT < 64 && low == 0) | |
3728 | { | |
3729 | lsb = high & -high; | |
3730 | return high == -lsb; | |
3731 | } | |
3732 | ||
3733 | lsb = low & -low; | |
3734 | return low == -lsb && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0); | |
3735 | } | |
3736 | else | |
3737 | return 0; | |
3738 | } | |
e2c953b6 | 3739 | |
c5059423 AM |
3740 | /* Return 1 if ANDOP is a mask suitable for use with an rldicr insn |
3741 | to perform a left shift. It must have SHIFTOP or more least | |
3742 | signifigant 0's, with the remainder of the word 1's. */ | |
e2c953b6 | 3743 | |
c5059423 AM |
3744 | int |
3745 | includes_rldicr_lshift_p (shiftop, andop) | |
592696dd SS |
3746 | rtx shiftop; |
3747 | rtx andop; | |
c5059423 | 3748 | { |
e2c953b6 | 3749 | if (GET_CODE (andop) == CONST_INT) |
c5059423 | 3750 | { |
02071907 | 3751 | HOST_WIDE_INT c, lsb, shift_mask; |
c5059423 | 3752 | |
02071907 | 3753 | shift_mask = ~0; |
c5059423 AM |
3754 | shift_mask <<= INTVAL (shiftop); |
3755 | c = INTVAL (andop); | |
3756 | ||
3757 | /* Find the least signifigant one bit. */ | |
3758 | lsb = c & -c; | |
3759 | ||
3760 | /* It must be covered by the shift mask. | |
a4f6c312 | 3761 | This test also rejects c == 0. */ |
c5059423 AM |
3762 | if ((lsb & shift_mask) == 0) |
3763 | return 0; | |
3764 | ||
3765 | /* Check we have all 1's above the transition, and reject all 1's. */ | |
3766 | return c == -lsb && lsb != 1; | |
3767 | } | |
3768 | else if (GET_CODE (andop) == CONST_DOUBLE | |
3769 | && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode)) | |
3770 | { | |
02071907 | 3771 | HOST_WIDE_INT low, lsb, shift_mask_low; |
c5059423 AM |
3772 | |
3773 | low = CONST_DOUBLE_LOW (andop); | |
3774 | ||
3775 | if (HOST_BITS_PER_WIDE_INT < 64) | |
3776 | { | |
02071907 | 3777 | HOST_WIDE_INT high, shift_mask_high; |
c5059423 AM |
3778 | |
3779 | high = CONST_DOUBLE_HIGH (andop); | |
3780 | ||
3781 | if (low == 0) | |
3782 | { | |
02071907 | 3783 | shift_mask_high = ~0; |
c5059423 AM |
3784 | if (INTVAL (shiftop) > 32) |
3785 | shift_mask_high <<= INTVAL (shiftop) - 32; | |
3786 | ||
3787 | lsb = high & -high; | |
3788 | ||
3789 | if ((lsb & shift_mask_high) == 0) | |
3790 | return 0; | |
3791 | ||
3792 | return high == -lsb; | |
3793 | } | |
3794 | if (high != ~0) | |
3795 | return 0; | |
3796 | } | |
3797 | ||
02071907 | 3798 | shift_mask_low = ~0; |
c5059423 AM |
3799 | shift_mask_low <<= INTVAL (shiftop); |
3800 | ||
3801 | lsb = low & -low; | |
3802 | ||
3803 | if ((lsb & shift_mask_low) == 0) | |
3804 | return 0; | |
3805 | ||
3806 | return low == -lsb && lsb != 1; | |
3807 | } | |
e2c953b6 | 3808 | else |
c5059423 | 3809 | return 0; |
9878760c | 3810 | } |
35068b43 RK |
3811 | |
3812 | /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates | |
3813 | for lfq and stfq insns. | |
3814 | ||
3815 | Note reg1 and reg2 *must* be hard registers. To be sure we will | |
3816 | abort if we are passed pseudo registers. */ | |
3817 | ||
3818 | int | |
3819 | registers_ok_for_quad_peep (reg1, reg2) | |
3820 | rtx reg1, reg2; | |
3821 | { | |
3822 | /* We might have been passed a SUBREG. */ | |
3823 | if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG) | |
3824 | return 0; | |
3825 | ||
3826 | return (REGNO (reg1) == REGNO (reg2) - 1); | |
3827 | } | |
3828 | ||
a4f6c312 SS |
3829 | /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn. |
3830 | addr1 and addr2 must be in consecutive memory locations | |
3831 | (addr2 == addr1 + 8). */ | |
35068b43 RK |
3832 | |
3833 | int | |
3834 | addrs_ok_for_quad_peep (addr1, addr2) | |
592696dd SS |
3835 | rtx addr1; |
3836 | rtx addr2; | |
35068b43 | 3837 | { |
e2c953b6 | 3838 | unsigned int reg1; |
35068b43 RK |
3839 | int offset1; |
3840 | ||
3841 | /* Extract an offset (if used) from the first addr. */ | |
3842 | if (GET_CODE (addr1) == PLUS) | |
3843 | { | |
3844 | /* If not a REG, return zero. */ | |
3845 | if (GET_CODE (XEXP (addr1, 0)) != REG) | |
3846 | return 0; | |
3847 | else | |
3848 | { | |
3849 | reg1 = REGNO (XEXP (addr1, 0)); | |
3850 | /* The offset must be constant! */ | |
3851 | if (GET_CODE (XEXP (addr1, 1)) != CONST_INT) | |
3852 | return 0; | |
3853 | offset1 = INTVAL (XEXP (addr1, 1)); | |
3854 | } | |
3855 | } | |
3856 | else if (GET_CODE (addr1) != REG) | |
3857 | return 0; | |
3858 | else | |
3859 | { | |
3860 | reg1 = REGNO (addr1); | |
3861 | /* This was a simple (mem (reg)) expression. Offset is 0. */ | |
3862 | offset1 = 0; | |
3863 | } | |
3864 | ||
acad7ed3 | 3865 | /* Make sure the second address is a (mem (plus (reg) (const_int))). */ |
35068b43 RK |
3866 | if (GET_CODE (addr2) != PLUS) |
3867 | return 0; | |
3868 | ||
3869 | if (GET_CODE (XEXP (addr2, 0)) != REG | |
3870 | || GET_CODE (XEXP (addr2, 1)) != CONST_INT) | |
3871 | return 0; | |
3872 | ||
3873 | if (reg1 != REGNO (XEXP (addr2, 0))) | |
3874 | return 0; | |
3875 | ||
3876 | /* The offset for the second addr must be 8 more than the first addr. */ | |
3877 | if (INTVAL (XEXP (addr2, 1)) != offset1 + 8) | |
3878 | return 0; | |
3879 | ||
3880 | /* All the tests passed. addr1 and addr2 are valid for lfq or stfq | |
3881 | instructions. */ | |
3882 | return 1; | |
3883 | } | |
9878760c RK |
3884 | \f |
3885 | /* Return the register class of a scratch register needed to copy IN into | |
3886 | or out of a register in CLASS in MODE. If it can be done directly, | |
3887 | NO_REGS is returned. */ | |
3888 | ||
3889 | enum reg_class | |
3890 | secondary_reload_class (class, mode, in) | |
3891 | enum reg_class class; | |
296b8152 | 3892 | enum machine_mode mode ATTRIBUTE_UNUSED; |
9878760c RK |
3893 | rtx in; |
3894 | { | |
5accd822 | 3895 | int regno; |
9878760c | 3896 | |
46fad5b7 DJ |
3897 | if (TARGET_ELF || (DEFAULT_ABI == ABI_DARWIN && flag_pic)) |
3898 | { | |
3899 | /* We cannot copy a symbolic operand directly into anything | |
3900 | other than BASE_REGS for TARGET_ELF. So indicate that a | |
3901 | register from BASE_REGS is needed as an intermediate | |
3902 | register. | |
3903 | ||
3904 | On Darwin, pic addresses require a load from memory, which | |
3905 | needs a base register. */ | |
3906 | if (class != BASE_REGS | |
3907 | && (GET_CODE (in) == SYMBOL_REF | |
3908 | || GET_CODE (in) == HIGH | |
3909 | || GET_CODE (in) == LABEL_REF | |
3910 | || GET_CODE (in) == CONST)) | |
3911 | return BASE_REGS; | |
3912 | } | |
e7b7998a | 3913 | |
5accd822 DE |
3914 | if (GET_CODE (in) == REG) |
3915 | { | |
3916 | regno = REGNO (in); | |
3917 | if (regno >= FIRST_PSEUDO_REGISTER) | |
3918 | { | |
3919 | regno = true_regnum (in); | |
3920 | if (regno >= FIRST_PSEUDO_REGISTER) | |
3921 | regno = -1; | |
3922 | } | |
3923 | } | |
3924 | else if (GET_CODE (in) == SUBREG) | |
3925 | { | |
3926 | regno = true_regnum (in); | |
3927 | if (regno >= FIRST_PSEUDO_REGISTER) | |
3928 | regno = -1; | |
3929 | } | |
3930 | else | |
3931 | regno = -1; | |
3932 | ||
9878760c RK |
3933 | /* We can place anything into GENERAL_REGS and can put GENERAL_REGS |
3934 | into anything. */ | |
3935 | if (class == GENERAL_REGS || class == BASE_REGS | |
3936 | || (regno >= 0 && INT_REGNO_P (regno))) | |
3937 | return NO_REGS; | |
3938 | ||
3939 | /* Constants, memory, and FP registers can go into FP registers. */ | |
3940 | if ((regno == -1 || FP_REGNO_P (regno)) | |
3941 | && (class == FLOAT_REGS || class == NON_SPECIAL_REGS)) | |
3942 | return NO_REGS; | |
3943 | ||
3944 | /* We can copy among the CR registers. */ | |
3945 | if ((class == CR_REGS || class == CR0_REGS) | |
3946 | && regno >= 0 && CR_REGNO_P (regno)) | |
3947 | return NO_REGS; | |
3948 | ||
3949 | /* Otherwise, we need GENERAL_REGS. */ | |
3950 | return GENERAL_REGS; | |
3951 | } | |
3952 | \f | |
3953 | /* Given a comparison operation, return the bit number in CCR to test. We | |
3954 | know this is a valid comparison. | |
3955 | ||
3956 | SCC_P is 1 if this is for an scc. That means that %D will have been | |
3957 | used instead of %C, so the bits will be in different places. | |
3958 | ||
b4ac57ab | 3959 | Return -1 if OP isn't a valid comparison for some reason. */ |
9878760c RK |
3960 | |
3961 | int | |
3962 | ccr_bit (op, scc_p) | |
592696dd | 3963 | rtx op; |
9878760c RK |
3964 | int scc_p; |
3965 | { | |
3966 | enum rtx_code code = GET_CODE (op); | |
3967 | enum machine_mode cc_mode; | |
3968 | int cc_regnum; | |
3969 | int base_bit; | |
9ebbca7d | 3970 | rtx reg; |
9878760c RK |
3971 | |
3972 | if (GET_RTX_CLASS (code) != '<') | |
3973 | return -1; | |
3974 | ||
9ebbca7d GK |
3975 | reg = XEXP (op, 0); |
3976 | ||
3977 | if (GET_CODE (reg) != REG | |
3978 | || ! CR_REGNO_P (REGNO (reg))) | |
3979 | abort (); | |
3980 | ||
3981 | cc_mode = GET_MODE (reg); | |
3982 | cc_regnum = REGNO (reg); | |
3983 | base_bit = 4 * (cc_regnum - CR0_REGNO); | |
9878760c | 3984 | |
39a10a29 | 3985 | validate_condition_mode (code, cc_mode); |
c5defebb | 3986 | |
9878760c RK |
3987 | switch (code) |
3988 | { | |
3989 | case NE: | |
3990 | return scc_p ? base_bit + 3 : base_bit + 2; | |
3991 | case EQ: | |
3992 | return base_bit + 2; | |
1c882ea4 | 3993 | case GT: case GTU: case UNLE: |
9878760c | 3994 | return base_bit + 1; |
1c882ea4 | 3995 | case LT: case LTU: case UNGE: |
9878760c | 3996 | return base_bit; |
1c882ea4 GK |
3997 | case ORDERED: case UNORDERED: |
3998 | return base_bit + 3; | |
9878760c RK |
3999 | |
4000 | case GE: case GEU: | |
39a10a29 | 4001 | /* If scc, we will have done a cror to put the bit in the |
9878760c RK |
4002 | unordered position. So test that bit. For integer, this is ! LT |
4003 | unless this is an scc insn. */ | |
39a10a29 | 4004 | return scc_p ? base_bit + 3 : base_bit; |
9878760c RK |
4005 | |
4006 | case LE: case LEU: | |
39a10a29 | 4007 | return scc_p ? base_bit + 3 : base_bit + 1; |
1c882ea4 | 4008 | |
9878760c RK |
4009 | default: |
4010 | abort (); | |
4011 | } | |
4012 | } | |
1ff7789b | 4013 | \f |
8d30c4ee | 4014 | /* Return the GOT register. */ |
1ff7789b MM |
4015 | |
4016 | struct rtx_def * | |
4017 | rs6000_got_register (value) | |
5f59ecb7 | 4018 | rtx value ATTRIBUTE_UNUSED; |
1ff7789b | 4019 | { |
a4f6c312 SS |
4020 | /* The second flow pass currently (June 1999) can't update |
4021 | regs_ever_live without disturbing other parts of the compiler, so | |
4022 | update it here to make the prolog/epilogue code happy. */ | |
3cb999d8 | 4023 | if (no_new_pseudos && ! regs_ever_live[PIC_OFFSET_TABLE_REGNUM]) |
8d30c4ee | 4024 | regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1; |
1ff7789b | 4025 | |
8d30c4ee | 4026 | current_function_uses_pic_offset_table = 1; |
3cb999d8 | 4027 | |
1ff7789b MM |
4028 | return pic_offset_table_rtx; |
4029 | } | |
a7df97e6 | 4030 | \f |
71f123ca | 4031 | /* Functions to init, mark and free struct machine_function. |
a7df97e6 MM |
4032 | These will be called, via pointer variables, |
4033 | from push_function_context and pop_function_context. */ | |
4034 | ||
00dba523 NC |
4035 | static void |
4036 | rs6000_init_machine_status (p) | |
a7df97e6 MM |
4037 | struct function *p; |
4038 | { | |
71f123ca FS |
4039 | p->machine = (machine_function *) xcalloc (1, sizeof (machine_function)); |
4040 | } | |
a7df97e6 | 4041 | |
00dba523 NC |
4042 | static void |
4043 | rs6000_free_machine_status (p) | |
a7df97e6 MM |
4044 | struct function *p; |
4045 | { | |
00dba523 NC |
4046 | if (p->machine == NULL) |
4047 | return; | |
a7df97e6 | 4048 | |
00dba523 NC |
4049 | free (p->machine); |
4050 | p->machine = NULL; | |
a7df97e6 MM |
4051 | } |
4052 | ||
9878760c RK |
4053 | \f |
4054 | /* Print an operand. Recognize special options, documented below. */ | |
4055 | ||
38c1f2d7 | 4056 | #if TARGET_ELF |
d9407988 | 4057 | #define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel") |
8fbd2dc7 | 4058 | #define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13) |
ba5e43aa MM |
4059 | #else |
4060 | #define SMALL_DATA_RELOC "sda21" | |
8fbd2dc7 | 4061 | #define SMALL_DATA_REG 0 |
ba5e43aa MM |
4062 | #endif |
4063 | ||
9878760c RK |
4064 | void |
4065 | print_operand (file, x, code) | |
4066 | FILE *file; | |
4067 | rtx x; | |
9ebbca7d | 4068 | int code; |
9878760c RK |
4069 | { |
4070 | int i; | |
a260abc9 | 4071 | HOST_WIDE_INT val; |
9878760c RK |
4072 | |
4073 | /* These macros test for integers and extract the low-order bits. */ | |
4074 | #define INT_P(X) \ | |
4075 | ((GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST_DOUBLE) \ | |
4076 | && GET_MODE (X) == VOIDmode) | |
4077 | ||
4078 | #define INT_LOWPART(X) \ | |
4079 | (GET_CODE (X) == CONST_INT ? INTVAL (X) : CONST_DOUBLE_LOW (X)) | |
4080 | ||
4081 | switch (code) | |
4082 | { | |
a8b3aeda | 4083 | case '.': |
a85d226b RK |
4084 | /* Write out an instruction after the call which may be replaced |
4085 | with glue code by the loader. This depends on the AIX version. */ | |
4086 | asm_fprintf (file, RS6000_CALL_GLUE); | |
a8b3aeda RK |
4087 | return; |
4088 | ||
c81bebd7 MM |
4089 | case '$': |
4090 | /* Write out either a '.' or '$' for the current location, depending | |
4091 | on whether this is Solaris or not. */ | |
4092 | putc ((DEFAULT_ABI == ABI_SOLARIS) ? '.' : '$', file); | |
4093 | return; | |
4094 | ||
81eace42 GK |
4095 | /* %a is output_address. */ |
4096 | ||
9854d9ed RK |
4097 | case 'A': |
4098 | /* If X is a constant integer whose low-order 5 bits are zero, | |
4099 | write 'l'. Otherwise, write 'r'. This is a kludge to fix a bug | |
76229ac8 | 4100 | in the AIX assembler where "sri" with a zero shift count |
9854d9ed RK |
4101 | write a trash instruction. */ |
4102 | if (GET_CODE (x) == CONST_INT && (INTVAL (x) & 31) == 0) | |
76229ac8 | 4103 | putc ('l', file); |
9854d9ed | 4104 | else |
76229ac8 | 4105 | putc ('r', file); |
9854d9ed RK |
4106 | return; |
4107 | ||
4108 | case 'b': | |
e2c953b6 DE |
4109 | /* If constant, low-order 16 bits of constant, unsigned. |
4110 | Otherwise, write normally. */ | |
4111 | if (INT_P (x)) | |
4112 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 0xffff); | |
4113 | else | |
4114 | print_operand (file, x, 0); | |
cad12a8d RK |
4115 | return; |
4116 | ||
a260abc9 DE |
4117 | case 'B': |
4118 | /* If the low-order bit is zero, write 'r'; otherwise, write 'l' | |
4119 | for 64-bit mask direction. */ | |
296b8152 | 4120 | putc (((INT_LOWPART(x) & 1) == 0 ? 'r' : 'l'), file); |
a238cd8b | 4121 | return; |
a260abc9 | 4122 | |
81eace42 GK |
4123 | /* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise |
4124 | output_operand. */ | |
4125 | ||
9854d9ed | 4126 | case 'D': |
39a10a29 GK |
4127 | /* There used to be a comment for 'C' reading "This is an |
4128 | optional cror needed for certain floating-point | |
4129 | comparisons. Otherwise write nothing." */ | |
4130 | ||
9854d9ed RK |
4131 | /* Similar, except that this is for an scc, so we must be able to |
4132 | encode the test in a single bit that is one. We do the above | |
4133 | for any LE, GE, GEU, or LEU and invert the bit for NE. */ | |
4134 | if (GET_CODE (x) == LE || GET_CODE (x) == GE | |
4135 | || GET_CODE (x) == LEU || GET_CODE (x) == GEU) | |
4136 | { | |
9ebbca7d | 4137 | int base_bit = 4 * (REGNO (XEXP (x, 0)) - CR0_REGNO); |
9854d9ed RK |
4138 | |
4139 | fprintf (file, "cror %d,%d,%d\n\t", base_bit + 3, | |
4140 | base_bit + 2, | |
4141 | base_bit + (GET_CODE (x) == GE || GET_CODE (x) == GEU)); | |
4142 | } | |
4143 | ||
4144 | else if (GET_CODE (x) == NE) | |
4145 | { | |
9ebbca7d | 4146 | int base_bit = 4 * (REGNO (XEXP (x, 0)) - CR0_REGNO); |
9854d9ed RK |
4147 | |
4148 | fprintf (file, "crnor %d,%d,%d\n\t", base_bit + 3, | |
4149 | base_bit + 2, base_bit + 2); | |
4150 | } | |
4151 | return; | |
4152 | ||
4153 | case 'E': | |
39a10a29 | 4154 | /* X is a CR register. Print the number of the EQ bit of the CR */ |
9854d9ed RK |
4155 | if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x))) |
4156 | output_operand_lossage ("invalid %%E value"); | |
78fbdbf7 | 4157 | else |
39a10a29 | 4158 | fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 2); |
a85d226b | 4159 | return; |
9854d9ed RK |
4160 | |
4161 | case 'f': | |
4162 | /* X is a CR register. Print the shift count needed to move it | |
4163 | to the high-order four bits. */ | |
4164 | if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x))) | |
4165 | output_operand_lossage ("invalid %%f value"); | |
4166 | else | |
9ebbca7d | 4167 | fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO)); |
9854d9ed RK |
4168 | return; |
4169 | ||
4170 | case 'F': | |
4171 | /* Similar, but print the count for the rotate in the opposite | |
4172 | direction. */ | |
4173 | if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x))) | |
4174 | output_operand_lossage ("invalid %%F value"); | |
4175 | else | |
9ebbca7d | 4176 | fprintf (file, "%d", 32 - 4 * (REGNO (x) - CR0_REGNO)); |
9854d9ed RK |
4177 | return; |
4178 | ||
4179 | case 'G': | |
4180 | /* X is a constant integer. If it is negative, print "m", | |
4181 | otherwise print "z". This is to make a aze or ame insn. */ | |
4182 | if (GET_CODE (x) != CONST_INT) | |
4183 | output_operand_lossage ("invalid %%G value"); | |
4184 | else if (INTVAL (x) >= 0) | |
76229ac8 | 4185 | putc ('z', file); |
9854d9ed | 4186 | else |
76229ac8 | 4187 | putc ('m', file); |
9854d9ed | 4188 | return; |
e2c953b6 | 4189 | |
9878760c | 4190 | case 'h': |
a4f6c312 SS |
4191 | /* If constant, output low-order five bits. Otherwise, write |
4192 | normally. */ | |
9878760c | 4193 | if (INT_P (x)) |
5f59ecb7 | 4194 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 31); |
9878760c RK |
4195 | else |
4196 | print_operand (file, x, 0); | |
4197 | return; | |
4198 | ||
64305719 | 4199 | case 'H': |
a4f6c312 SS |
4200 | /* If constant, output low-order six bits. Otherwise, write |
4201 | normally. */ | |
64305719 | 4202 | if (INT_P (x)) |
5f59ecb7 | 4203 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 63); |
64305719 DE |
4204 | else |
4205 | print_operand (file, x, 0); | |
4206 | return; | |
4207 | ||
9854d9ed RK |
4208 | case 'I': |
4209 | /* Print `i' if this is a constant, else nothing. */ | |
9878760c | 4210 | if (INT_P (x)) |
76229ac8 | 4211 | putc ('i', file); |
9878760c RK |
4212 | return; |
4213 | ||
9854d9ed RK |
4214 | case 'j': |
4215 | /* Write the bit number in CCR for jump. */ | |
4216 | i = ccr_bit (x, 0); | |
4217 | if (i == -1) | |
4218 | output_operand_lossage ("invalid %%j code"); | |
9878760c | 4219 | else |
9854d9ed | 4220 | fprintf (file, "%d", i); |
9878760c RK |
4221 | return; |
4222 | ||
9854d9ed RK |
4223 | case 'J': |
4224 | /* Similar, but add one for shift count in rlinm for scc and pass | |
4225 | scc flag to `ccr_bit'. */ | |
4226 | i = ccr_bit (x, 1); | |
4227 | if (i == -1) | |
4228 | output_operand_lossage ("invalid %%J code"); | |
4229 | else | |
a0466a68 RK |
4230 | /* If we want bit 31, write a shift count of zero, not 32. */ |
4231 | fprintf (file, "%d", i == 31 ? 0 : i + 1); | |
9878760c RK |
4232 | return; |
4233 | ||
9854d9ed RK |
4234 | case 'k': |
4235 | /* X must be a constant. Write the 1's complement of the | |
4236 | constant. */ | |
9878760c | 4237 | if (! INT_P (x)) |
9854d9ed | 4238 | output_operand_lossage ("invalid %%k value"); |
e2c953b6 DE |
4239 | else |
4240 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~ INT_LOWPART (x)); | |
9878760c RK |
4241 | return; |
4242 | ||
81eace42 | 4243 | case 'K': |
9ebbca7d GK |
4244 | /* X must be a symbolic constant on ELF. Write an |
4245 | expression suitable for an 'addi' that adds in the low 16 | |
4246 | bits of the MEM. */ | |
4247 | if (GET_CODE (x) != CONST) | |
4248 | { | |
4249 | print_operand_address (file, x); | |
4250 | fputs ("@l", file); | |
4251 | } | |
4252 | else | |
4253 | { | |
4254 | if (GET_CODE (XEXP (x, 0)) != PLUS | |
4255 | || (GET_CODE (XEXP (XEXP (x, 0), 0)) != SYMBOL_REF | |
4256 | && GET_CODE (XEXP (XEXP (x, 0), 0)) != LABEL_REF) | |
4257 | || GET_CODE (XEXP (XEXP (x, 0), 1)) != CONST_INT) | |
53cd5d6c | 4258 | output_operand_lossage ("invalid %%K value"); |
9ebbca7d GK |
4259 | print_operand_address (file, XEXP (XEXP (x, 0), 0)); |
4260 | fputs ("@l", file); | |
4261 | print_operand (file, XEXP (XEXP (x, 0), 1), 0); | |
4262 | } | |
81eace42 GK |
4263 | return; |
4264 | ||
4265 | /* %l is output_asm_label. */ | |
9ebbca7d | 4266 | |
9854d9ed RK |
4267 | case 'L': |
4268 | /* Write second word of DImode or DFmode reference. Works on register | |
4269 | or non-indexed memory only. */ | |
4270 | if (GET_CODE (x) == REG) | |
5ebfb2ba | 4271 | fprintf (file, "%s", reg_names[REGNO (x) + 1]); |
9854d9ed RK |
4272 | else if (GET_CODE (x) == MEM) |
4273 | { | |
4274 | /* Handle possible auto-increment. Since it is pre-increment and | |
1427100a | 4275 | we have already done it, we can just use an offset of word. */ |
9854d9ed RK |
4276 | if (GET_CODE (XEXP (x, 0)) == PRE_INC |
4277 | || GET_CODE (XEXP (x, 0)) == PRE_DEC) | |
ed8908e7 RK |
4278 | output_address (plus_constant (XEXP (XEXP (x, 0), 0), |
4279 | UNITS_PER_WORD)); | |
9854d9ed | 4280 | else |
d7624dc0 RK |
4281 | output_address (XEXP (adjust_address_nv (x, SImode, |
4282 | UNITS_PER_WORD), | |
4283 | 0)); | |
ed8908e7 | 4284 | |
ba5e43aa | 4285 | if (small_data_operand (x, GET_MODE (x))) |
8fbd2dc7 MM |
4286 | fprintf (file, "@%s(%s)", SMALL_DATA_RELOC, |
4287 | reg_names[SMALL_DATA_REG]); | |
9854d9ed | 4288 | } |
9878760c | 4289 | return; |
9854d9ed | 4290 | |
9878760c RK |
4291 | case 'm': |
4292 | /* MB value for a mask operand. */ | |
4293 | if (! mask_operand (x, VOIDmode)) | |
4294 | output_operand_lossage ("invalid %%m value"); | |
4295 | ||
4296 | val = INT_LOWPART (x); | |
4297 | ||
4298 | /* If the high bit is set and the low bit is not, the value is zero. | |
4299 | If the high bit is zero, the value is the first 1 bit we find from | |
4300 | the left. */ | |
0858c623 | 4301 | if ((val & 0x80000000) && ((val & 1) == 0)) |
9878760c | 4302 | { |
19d2d16f | 4303 | putc ('0', file); |
9878760c RK |
4304 | return; |
4305 | } | |
0858c623 | 4306 | else if ((val & 0x80000000) == 0) |
9878760c RK |
4307 | { |
4308 | for (i = 1; i < 32; i++) | |
0858c623 | 4309 | if ((val <<= 1) & 0x80000000) |
9878760c RK |
4310 | break; |
4311 | fprintf (file, "%d", i); | |
4312 | return; | |
4313 | } | |
4314 | ||
4315 | /* Otherwise, look for the first 0 bit from the right. The result is its | |
4316 | number plus 1. We know the low-order bit is one. */ | |
4317 | for (i = 0; i < 32; i++) | |
4318 | if (((val >>= 1) & 1) == 0) | |
4319 | break; | |
4320 | ||
a260abc9 | 4321 | /* If we ended in ...01, i would be 0. The correct value is 31, so |
9878760c RK |
4322 | we want 31 - i. */ |
4323 | fprintf (file, "%d", 31 - i); | |
4324 | return; | |
4325 | ||
4326 | case 'M': | |
4327 | /* ME value for a mask operand. */ | |
4328 | if (! mask_operand (x, VOIDmode)) | |
a260abc9 | 4329 | output_operand_lossage ("invalid %%M value"); |
9878760c RK |
4330 | |
4331 | val = INT_LOWPART (x); | |
4332 | ||
4333 | /* If the low bit is set and the high bit is not, the value is 31. | |
4334 | If the low bit is zero, the value is the first 1 bit we find from | |
4335 | the right. */ | |
0858c623 | 4336 | if ((val & 1) && ((val & 0x80000000) == 0)) |
9878760c | 4337 | { |
76229ac8 | 4338 | fputs ("31", file); |
9878760c RK |
4339 | return; |
4340 | } | |
4341 | else if ((val & 1) == 0) | |
4342 | { | |
4343 | for (i = 0; i < 32; i++) | |
4344 | if ((val >>= 1) & 1) | |
4345 | break; | |
4346 | ||
a260abc9 | 4347 | /* If we had ....10, i would be 0. The result should be |
9878760c RK |
4348 | 30, so we need 30 - i. */ |
4349 | fprintf (file, "%d", 30 - i); | |
4350 | return; | |
4351 | } | |
4352 | ||
4353 | /* Otherwise, look for the first 0 bit from the left. The result is its | |
4354 | number minus 1. We know the high-order bit is one. */ | |
4355 | for (i = 0; i < 32; i++) | |
0858c623 | 4356 | if (((val <<= 1) & 0x80000000) == 0) |
9878760c RK |
4357 | break; |
4358 | ||
4359 | fprintf (file, "%d", i); | |
4360 | return; | |
4361 | ||
81eace42 GK |
4362 | /* %n outputs the negative of its operand. */ |
4363 | ||
9878760c RK |
4364 | case 'N': |
4365 | /* Write the number of elements in the vector times 4. */ | |
4366 | if (GET_CODE (x) != PARALLEL) | |
4367 | output_operand_lossage ("invalid %%N value"); | |
e2c953b6 DE |
4368 | else |
4369 | fprintf (file, "%d", XVECLEN (x, 0) * 4); | |
9878760c RK |
4370 | return; |
4371 | ||
4372 | case 'O': | |
4373 | /* Similar, but subtract 1 first. */ | |
4374 | if (GET_CODE (x) != PARALLEL) | |
1427100a | 4375 | output_operand_lossage ("invalid %%O value"); |
e2c953b6 DE |
4376 | else |
4377 | fprintf (file, "%d", (XVECLEN (x, 0) - 1) * 4); | |
9878760c RK |
4378 | return; |
4379 | ||
9854d9ed RK |
4380 | case 'p': |
4381 | /* X is a CONST_INT that is a power of two. Output the logarithm. */ | |
4382 | if (! INT_P (x) | |
2bfcf297 | 4383 | || INT_LOWPART (x) < 0 |
9854d9ed RK |
4384 | || (i = exact_log2 (INT_LOWPART (x))) < 0) |
4385 | output_operand_lossage ("invalid %%p value"); | |
e2c953b6 DE |
4386 | else |
4387 | fprintf (file, "%d", i); | |
9854d9ed RK |
4388 | return; |
4389 | ||
9878760c RK |
4390 | case 'P': |
4391 | /* The operand must be an indirect memory reference. The result | |
a4f6c312 | 4392 | is the register number. */ |
9878760c RK |
4393 | if (GET_CODE (x) != MEM || GET_CODE (XEXP (x, 0)) != REG |
4394 | || REGNO (XEXP (x, 0)) >= 32) | |
4395 | output_operand_lossage ("invalid %%P value"); | |
e2c953b6 DE |
4396 | else |
4397 | fprintf (file, "%d", REGNO (XEXP (x, 0))); | |
9878760c RK |
4398 | return; |
4399 | ||
dfbdccdb GK |
4400 | case 'q': |
4401 | /* This outputs the logical code corresponding to a boolean | |
4402 | expression. The expression may have one or both operands | |
39a10a29 GK |
4403 | negated (if one, only the first one). For condition register |
4404 | logical operations, it will also treat the negated | |
4405 | CR codes as NOTs, but not handle NOTs of them. */ | |
dfbdccdb | 4406 | { |
63bc1d05 | 4407 | const char *const *t = 0; |
dfbdccdb GK |
4408 | const char *s; |
4409 | enum rtx_code code = GET_CODE (x); | |
4410 | static const char * const tbl[3][3] = { | |
4411 | { "and", "andc", "nor" }, | |
4412 | { "or", "orc", "nand" }, | |
4413 | { "xor", "eqv", "xor" } }; | |
4414 | ||
4415 | if (code == AND) | |
4416 | t = tbl[0]; | |
4417 | else if (code == IOR) | |
4418 | t = tbl[1]; | |
4419 | else if (code == XOR) | |
4420 | t = tbl[2]; | |
4421 | else | |
4422 | output_operand_lossage ("invalid %%q value"); | |
4423 | ||
4424 | if (GET_CODE (XEXP (x, 0)) != NOT) | |
4425 | s = t[0]; | |
4426 | else | |
4427 | { | |
4428 | if (GET_CODE (XEXP (x, 1)) == NOT) | |
4429 | s = t[2]; | |
4430 | else | |
4431 | s = t[1]; | |
4432 | } | |
4433 | ||
4434 | fputs (s, file); | |
4435 | } | |
4436 | return; | |
4437 | ||
9854d9ed RK |
4438 | case 'R': |
4439 | /* X is a CR register. Print the mask for `mtcrf'. */ | |
4440 | if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x))) | |
4441 | output_operand_lossage ("invalid %%R value"); | |
4442 | else | |
9ebbca7d | 4443 | fprintf (file, "%d", 128 >> (REGNO (x) - CR0_REGNO)); |
9878760c | 4444 | return; |
9854d9ed RK |
4445 | |
4446 | case 's': | |
4447 | /* Low 5 bits of 32 - value */ | |
4448 | if (! INT_P (x)) | |
4449 | output_operand_lossage ("invalid %%s value"); | |
e2c953b6 DE |
4450 | else |
4451 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, (32 - INT_LOWPART (x)) & 31); | |
9878760c | 4452 | return; |
9854d9ed | 4453 | |
a260abc9 DE |
4454 | case 'S': |
4455 | /* PowerPC64 mask position. All 0's and all 1's are excluded. | |
4456 | CONST_INT 32-bit mask is considered sign-extended so any | |
4457 | transition must occur within the CONST_INT, not on the boundary. */ | |
4458 | if (! mask64_operand (x, VOIDmode)) | |
4459 | output_operand_lossage ("invalid %%S value"); | |
4460 | ||
4461 | val = INT_LOWPART (x); | |
4462 | ||
4463 | if (val & 1) /* Clear Left */ | |
4464 | { | |
a238cd8b DE |
4465 | for (i = 0; i < HOST_BITS_PER_WIDE_INT; i++) |
4466 | if (!((val >>= 1) & 1)) | |
4467 | break; | |
a260abc9 | 4468 | |
a238cd8b DE |
4469 | #if HOST_BITS_PER_WIDE_INT == 32 |
4470 | if (GET_CODE (x) == CONST_DOUBLE && i == 32) | |
4471 | { | |
4472 | val = CONST_DOUBLE_HIGH (x); | |
4473 | ||
4474 | if (val == 0) | |
4475 | --i; | |
4476 | else | |
4477 | for (i = 32; i < 64; i++) | |
4478 | if (!((val >>= 1) & 1)) | |
4479 | break; | |
4480 | } | |
a260abc9 | 4481 | #endif |
a238cd8b DE |
4482 | /* i = index of last set bit from right |
4483 | mask begins at 63 - i from left */ | |
4484 | if (i > 63) | |
4485 | output_operand_lossage ("%%S computed all 1's mask"); | |
cccf3bdc | 4486 | |
a260abc9 DE |
4487 | fprintf (file, "%d", 63 - i); |
4488 | return; | |
4489 | } | |
4490 | else /* Clear Right */ | |
4491 | { | |
a238cd8b DE |
4492 | for (i = 0; i < HOST_BITS_PER_WIDE_INT; i++) |
4493 | if ((val >>= 1) & 1) | |
4494 | break; | |
a260abc9 | 4495 | |
a238cd8b | 4496 | #if HOST_BITS_PER_WIDE_INT == 32 |
a260abc9 DE |
4497 | if (GET_CODE (x) == CONST_DOUBLE && i == 32) |
4498 | { | |
a238cd8b | 4499 | val = CONST_DOUBLE_HIGH (x); |
a260abc9 | 4500 | |
a238cd8b | 4501 | if (val == (HOST_WIDE_INT) -1) |
a260abc9 | 4502 | --i; |
a260abc9 | 4503 | else |
a238cd8b DE |
4504 | for (i = 32; i < 64; i++) |
4505 | if ((val >>= 1) & 1) | |
a260abc9 DE |
4506 | break; |
4507 | } | |
4508 | #endif | |
a238cd8b DE |
4509 | /* i = index of last clear bit from right |
4510 | mask ends at 62 - i from left */ | |
4511 | if (i > 62) | |
4512 | output_operand_lossage ("%%S computed all 0's mask"); | |
cccf3bdc | 4513 | |
a238cd8b | 4514 | fprintf (file, "%d", 62 - i); |
a260abc9 DE |
4515 | return; |
4516 | } | |
4517 | ||
cccf3bdc DE |
4518 | case 'T': |
4519 | /* Print the symbolic name of a branch target register. */ | |
4520 | if (GET_CODE (x) != REG || (REGNO (x) != LINK_REGISTER_REGNUM | |
4521 | && REGNO (x) != COUNT_REGISTER_REGNUM)) | |
4522 | output_operand_lossage ("invalid %%T value"); | |
e2c953b6 | 4523 | else if (REGNO (x) == LINK_REGISTER_REGNUM) |
cccf3bdc DE |
4524 | fputs (TARGET_NEW_MNEMONICS ? "lr" : "r", file); |
4525 | else | |
4526 | fputs ("ctr", file); | |
4527 | return; | |
4528 | ||
9854d9ed | 4529 | case 'u': |
802a0058 | 4530 | /* High-order 16 bits of constant for use in unsigned operand. */ |
9854d9ed RK |
4531 | if (! INT_P (x)) |
4532 | output_operand_lossage ("invalid %%u value"); | |
e2c953b6 DE |
4533 | else |
4534 | fprintf (file, HOST_WIDE_INT_PRINT_HEX, | |
4535 | (INT_LOWPART (x) >> 16) & 0xffff); | |
9878760c RK |
4536 | return; |
4537 | ||
802a0058 MM |
4538 | case 'v': |
4539 | /* High-order 16 bits of constant for use in signed operand. */ | |
4540 | if (! INT_P (x)) | |
4541 | output_operand_lossage ("invalid %%v value"); | |
e2c953b6 DE |
4542 | else |
4543 | { | |
4544 | int value = (INT_LOWPART (x) >> 16) & 0xffff; | |
802a0058 | 4545 | |
e2c953b6 DE |
4546 | /* Solaris assembler doesn't like lis 0,0x8000 */ |
4547 | if (DEFAULT_ABI == ABI_SOLARIS && (value & 0x8000) != 0) | |
4548 | fprintf (file, "%d", value | (~0 << 16)); | |
4549 | else | |
4550 | fprintf (file, "0x%x", value); | |
4551 | return; | |
4552 | } | |
802a0058 | 4553 | |
9854d9ed RK |
4554 | case 'U': |
4555 | /* Print `u' if this has an auto-increment or auto-decrement. */ | |
4556 | if (GET_CODE (x) == MEM | |
4557 | && (GET_CODE (XEXP (x, 0)) == PRE_INC | |
4558 | || GET_CODE (XEXP (x, 0)) == PRE_DEC)) | |
76229ac8 | 4559 | putc ('u', file); |
9854d9ed | 4560 | return; |
9878760c | 4561 | |
e0cd0770 JC |
4562 | case 'V': |
4563 | /* Print the trap code for this operand. */ | |
4564 | switch (GET_CODE (x)) | |
4565 | { | |
4566 | case EQ: | |
4567 | fputs ("eq", file); /* 4 */ | |
4568 | break; | |
4569 | case NE: | |
4570 | fputs ("ne", file); /* 24 */ | |
4571 | break; | |
4572 | case LT: | |
4573 | fputs ("lt", file); /* 16 */ | |
4574 | break; | |
4575 | case LE: | |
4576 | fputs ("le", file); /* 20 */ | |
4577 | break; | |
4578 | case GT: | |
4579 | fputs ("gt", file); /* 8 */ | |
4580 | break; | |
4581 | case GE: | |
4582 | fputs ("ge", file); /* 12 */ | |
4583 | break; | |
4584 | case LTU: | |
4585 | fputs ("llt", file); /* 2 */ | |
4586 | break; | |
4587 | case LEU: | |
4588 | fputs ("lle", file); /* 6 */ | |
4589 | break; | |
4590 | case GTU: | |
4591 | fputs ("lgt", file); /* 1 */ | |
4592 | break; | |
4593 | case GEU: | |
4594 | fputs ("lge", file); /* 5 */ | |
4595 | break; | |
4596 | default: | |
4597 | abort (); | |
4598 | } | |
4599 | break; | |
4600 | ||
9854d9ed RK |
4601 | case 'w': |
4602 | /* If constant, low-order 16 bits of constant, signed. Otherwise, write | |
4603 | normally. */ | |
4604 | if (INT_P (x)) | |
5f59ecb7 DE |
4605 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, |
4606 | ((INT_LOWPART (x) & 0xffff) ^ 0x8000) - 0x8000); | |
9854d9ed RK |
4607 | else |
4608 | print_operand (file, x, 0); | |
9878760c RK |
4609 | return; |
4610 | ||
9854d9ed | 4611 | case 'W': |
e2c953b6 | 4612 | /* MB value for a PowerPC64 rldic operand. */ |
e2c953b6 DE |
4613 | val = (GET_CODE (x) == CONST_INT |
4614 | ? INTVAL (x) : CONST_DOUBLE_HIGH (x)); | |
4615 | ||
4616 | if (val < 0) | |
4617 | i = -1; | |
9854d9ed | 4618 | else |
e2c953b6 DE |
4619 | for (i = 0; i < HOST_BITS_PER_WIDE_INT; i++) |
4620 | if ((val <<= 1) < 0) | |
4621 | break; | |
4622 | ||
4623 | #if HOST_BITS_PER_WIDE_INT == 32 | |
4624 | if (GET_CODE (x) == CONST_INT && i >= 0) | |
4625 | i += 32; /* zero-extend high-part was all 0's */ | |
4626 | else if (GET_CODE (x) == CONST_DOUBLE && i == 32) | |
4627 | { | |
4628 | val = CONST_DOUBLE_LOW (x); | |
4629 | ||
4630 | if (val == 0) | |
a4f6c312 | 4631 | abort (); |
e2c953b6 DE |
4632 | else if (val < 0) |
4633 | --i; | |
4634 | else | |
4635 | for ( ; i < 64; i++) | |
4636 | if ((val <<= 1) < 0) | |
4637 | break; | |
4638 | } | |
4639 | #endif | |
4640 | ||
4641 | fprintf (file, "%d", i + 1); | |
9854d9ed | 4642 | return; |
9878760c | 4643 | |
9854d9ed RK |
4644 | case 'X': |
4645 | if (GET_CODE (x) == MEM | |
258bfae2 | 4646 | && LEGITIMATE_INDEXED_ADDRESS_P (XEXP (x, 0), 0)) |
76229ac8 | 4647 | putc ('x', file); |
9854d9ed | 4648 | return; |
9878760c | 4649 | |
9854d9ed RK |
4650 | case 'Y': |
4651 | /* Like 'L', for third word of TImode */ | |
4652 | if (GET_CODE (x) == REG) | |
5ebfb2ba | 4653 | fprintf (file, "%s", reg_names[REGNO (x) + 2]); |
9854d9ed | 4654 | else if (GET_CODE (x) == MEM) |
9878760c | 4655 | { |
9854d9ed RK |
4656 | if (GET_CODE (XEXP (x, 0)) == PRE_INC |
4657 | || GET_CODE (XEXP (x, 0)) == PRE_DEC) | |
a54d04b7 | 4658 | output_address (plus_constant (XEXP (XEXP (x, 0), 0), 8)); |
9854d9ed | 4659 | else |
d7624dc0 | 4660 | output_address (XEXP (adjust_address_nv (x, SImode, 8), 0)); |
ba5e43aa | 4661 | if (small_data_operand (x, GET_MODE (x))) |
8fbd2dc7 MM |
4662 | fprintf (file, "@%s(%s)", SMALL_DATA_RELOC, |
4663 | reg_names[SMALL_DATA_REG]); | |
9878760c RK |
4664 | } |
4665 | return; | |
9854d9ed | 4666 | |
9878760c | 4667 | case 'z': |
b4ac57ab RS |
4668 | /* X is a SYMBOL_REF. Write out the name preceded by a |
4669 | period and without any trailing data in brackets. Used for function | |
4d30c363 MM |
4670 | names. If we are configured for System V (or the embedded ABI) on |
4671 | the PowerPC, do not emit the period, since those systems do not use | |
4672 | TOCs and the like. */ | |
9878760c RK |
4673 | if (GET_CODE (x) != SYMBOL_REF) |
4674 | abort (); | |
4675 | ||
b6c9286a MM |
4676 | if (XSTR (x, 0)[0] != '.') |
4677 | { | |
4678 | switch (DEFAULT_ABI) | |
4679 | { | |
4680 | default: | |
4681 | abort (); | |
4682 | ||
4683 | case ABI_AIX: | |
4684 | putc ('.', file); | |
4685 | break; | |
4686 | ||
4687 | case ABI_V4: | |
4688 | case ABI_AIX_NODESC: | |
c81bebd7 | 4689 | case ABI_SOLARIS: |
ee890fe2 | 4690 | case ABI_DARWIN: |
b6c9286a | 4691 | break; |
b6c9286a MM |
4692 | } |
4693 | } | |
9ebbca7d | 4694 | #if TARGET_AIX |
9878760c | 4695 | RS6000_OUTPUT_BASENAME (file, XSTR (x, 0)); |
9ebbca7d GK |
4696 | #else |
4697 | assemble_name (file, XSTR (x, 0)); | |
4698 | #endif | |
9878760c RK |
4699 | return; |
4700 | ||
9854d9ed RK |
4701 | case 'Z': |
4702 | /* Like 'L', for last word of TImode. */ | |
4703 | if (GET_CODE (x) == REG) | |
5ebfb2ba | 4704 | fprintf (file, "%s", reg_names[REGNO (x) + 3]); |
9854d9ed RK |
4705 | else if (GET_CODE (x) == MEM) |
4706 | { | |
4707 | if (GET_CODE (XEXP (x, 0)) == PRE_INC | |
4708 | || GET_CODE (XEXP (x, 0)) == PRE_DEC) | |
a54d04b7 | 4709 | output_address (plus_constant (XEXP (XEXP (x, 0), 0), 12)); |
9854d9ed | 4710 | else |
d7624dc0 | 4711 | output_address (XEXP (adjust_address_nv (x, SImode, 12), 0)); |
ba5e43aa | 4712 | if (small_data_operand (x, GET_MODE (x))) |
8fbd2dc7 MM |
4713 | fprintf (file, "@%s(%s)", SMALL_DATA_RELOC, |
4714 | reg_names[SMALL_DATA_REG]); | |
9854d9ed | 4715 | } |
5c23c401 | 4716 | return; |
9854d9ed | 4717 | |
9878760c RK |
4718 | case 0: |
4719 | if (GET_CODE (x) == REG) | |
4720 | fprintf (file, "%s", reg_names[REGNO (x)]); | |
4721 | else if (GET_CODE (x) == MEM) | |
4722 | { | |
4723 | /* We need to handle PRE_INC and PRE_DEC here, since we need to | |
4724 | know the width from the mode. */ | |
4725 | if (GET_CODE (XEXP (x, 0)) == PRE_INC) | |
79ba6d34 MM |
4726 | fprintf (file, "%d(%s)", GET_MODE_SIZE (GET_MODE (x)), |
4727 | reg_names[REGNO (XEXP (XEXP (x, 0), 0))]); | |
9878760c | 4728 | else if (GET_CODE (XEXP (x, 0)) == PRE_DEC) |
79ba6d34 MM |
4729 | fprintf (file, "%d(%s)", - GET_MODE_SIZE (GET_MODE (x)), |
4730 | reg_names[REGNO (XEXP (XEXP (x, 0), 0))]); | |
9878760c | 4731 | else |
a54d04b7 | 4732 | output_address (XEXP (x, 0)); |
9878760c RK |
4733 | } |
4734 | else | |
a54d04b7 | 4735 | output_addr_const (file, x); |
a85d226b | 4736 | return; |
9878760c RK |
4737 | |
4738 | default: | |
4739 | output_operand_lossage ("invalid %%xn code"); | |
4740 | } | |
4741 | } | |
4742 | \f | |
4743 | /* Print the address of an operand. */ | |
4744 | ||
4745 | void | |
4746 | print_operand_address (file, x) | |
4747 | FILE *file; | |
592696dd | 4748 | rtx x; |
9878760c RK |
4749 | { |
4750 | if (GET_CODE (x) == REG) | |
4697a36c | 4751 | fprintf (file, "0(%s)", reg_names[ REGNO (x) ]); |
9ebbca7d GK |
4752 | else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST |
4753 | || GET_CODE (x) == LABEL_REF) | |
9878760c RK |
4754 | { |
4755 | output_addr_const (file, x); | |
ba5e43aa | 4756 | if (small_data_operand (x, GET_MODE (x))) |
8fbd2dc7 MM |
4757 | fprintf (file, "@%s(%s)", SMALL_DATA_RELOC, |
4758 | reg_names[SMALL_DATA_REG]); | |
9ebbca7d | 4759 | else if (TARGET_TOC) |
a4f6c312 | 4760 | abort (); |
9878760c RK |
4761 | } |
4762 | else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == REG) | |
4763 | { | |
4764 | if (REGNO (XEXP (x, 0)) == 0) | |
4697a36c MM |
4765 | fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 1)) ], |
4766 | reg_names[ REGNO (XEXP (x, 0)) ]); | |
9878760c | 4767 | else |
4697a36c MM |
4768 | fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 0)) ], |
4769 | reg_names[ REGNO (XEXP (x, 1)) ]); | |
9878760c RK |
4770 | } |
4771 | else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT) | |
5f59ecb7 DE |
4772 | { |
4773 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (XEXP (x, 1))); | |
4774 | fprintf (file, "(%s)", reg_names[ REGNO (XEXP (x, 0)) ]); | |
4775 | } | |
3cb999d8 DE |
4776 | #if TARGET_ELF |
4777 | else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG | |
4778 | && CONSTANT_P (XEXP (x, 1))) | |
4697a36c MM |
4779 | { |
4780 | output_addr_const (file, XEXP (x, 1)); | |
4781 | fprintf (file, "@l(%s)", reg_names[ REGNO (XEXP (x, 0)) ]); | |
4782 | } | |
3cb999d8 | 4783 | #endif |
9ebbca7d GK |
4784 | else if (LEGITIMATE_CONSTANT_POOL_ADDRESS_P (x)) |
4785 | { | |
2bfcf297 | 4786 | if (TARGET_AIX && (!TARGET_ELF || !TARGET_MINIMAL_TOC)) |
9ebbca7d | 4787 | { |
2bfcf297 DB |
4788 | rtx contains_minus = XEXP (x, 1); |
4789 | rtx minus, symref; | |
4790 | const char *name; | |
9ebbca7d GK |
4791 | |
4792 | /* Find the (minus (sym) (toc)) buried in X, and temporarily | |
a4f6c312 | 4793 | turn it into (sym) for output_addr_const. */ |
9ebbca7d GK |
4794 | while (GET_CODE (XEXP (contains_minus, 0)) != MINUS) |
4795 | contains_minus = XEXP (contains_minus, 0); | |
4796 | ||
2bfcf297 DB |
4797 | minus = XEXP (contains_minus, 0); |
4798 | symref = XEXP (minus, 0); | |
4799 | XEXP (contains_minus, 0) = symref; | |
4800 | if (TARGET_ELF) | |
4801 | { | |
4802 | char *newname; | |
4803 | ||
4804 | name = XSTR (symref, 0); | |
4805 | newname = alloca (strlen (name) + sizeof ("@toc")); | |
4806 | strcpy (newname, name); | |
4807 | strcat (newname, "@toc"); | |
4808 | XSTR (symref, 0) = newname; | |
4809 | } | |
4810 | output_addr_const (file, XEXP (x, 1)); | |
4811 | if (TARGET_ELF) | |
4812 | XSTR (symref, 0) = name; | |
9ebbca7d GK |
4813 | XEXP (contains_minus, 0) = minus; |
4814 | } | |
4815 | else | |
4816 | output_addr_const (file, XEXP (x, 1)); | |
4817 | ||
4818 | fprintf (file, "(%s)", reg_names[REGNO (XEXP (x, 0))]); | |
4819 | } | |
9878760c RK |
4820 | else |
4821 | abort (); | |
4822 | } | |
4823 | \f | |
39a10a29 GK |
4824 | enum rtx_code |
4825 | rs6000_reverse_condition (mode, code) | |
4826 | enum machine_mode mode; | |
4827 | enum rtx_code code; | |
4828 | { | |
4829 | /* Reversal of FP compares takes care -- an ordered compare | |
4830 | becomes an unordered compare and vice versa. */ | |
4831 | if (mode == CCFPmode) | |
bab6226b | 4832 | return reverse_condition_maybe_unordered (code); |
39a10a29 | 4833 | else |
bab6226b | 4834 | return reverse_condition (code); |
39a10a29 GK |
4835 | } |
4836 | ||
39a10a29 GK |
4837 | /* Generate a compare for CODE. Return a brand-new rtx that |
4838 | represents the result of the compare. */ | |
a4f6c312 | 4839 | |
39a10a29 GK |
4840 | static rtx |
4841 | rs6000_generate_compare (code) | |
4842 | enum rtx_code code; | |
4843 | { | |
4844 | enum machine_mode comp_mode; | |
4845 | rtx compare_result; | |
4846 | ||
4847 | if (rs6000_compare_fp_p) | |
4848 | comp_mode = CCFPmode; | |
4849 | else if (code == GTU || code == LTU | |
4850 | || code == GEU || code == LEU) | |
4851 | comp_mode = CCUNSmode; | |
4852 | else | |
4853 | comp_mode = CCmode; | |
4854 | ||
4855 | /* First, the compare. */ | |
4856 | compare_result = gen_reg_rtx (comp_mode); | |
4857 | emit_insn (gen_rtx_SET (VOIDmode, compare_result, | |
4858 | gen_rtx_COMPARE (comp_mode, | |
4859 | rs6000_compare_op0, | |
4860 | rs6000_compare_op1))); | |
4861 | ||
ca5adc63 | 4862 | /* Some kinds of FP comparisons need an OR operation; |
de6c5979 | 4863 | except for flag_unsafe_math_optimizations we don't bother. */ |
39a10a29 | 4864 | if (rs6000_compare_fp_p |
de6c5979 | 4865 | && ! flag_unsafe_math_optimizations |
39a10a29 GK |
4866 | && (code == LE || code == GE |
4867 | || code == UNEQ || code == LTGT | |
4868 | || code == UNGT || code == UNLT)) | |
4869 | { | |
4870 | enum rtx_code or1, or2; | |
4871 | rtx or1_rtx, or2_rtx, compare2_rtx; | |
4872 | rtx or_result = gen_reg_rtx (CCEQmode); | |
4873 | ||
4874 | switch (code) | |
4875 | { | |
4876 | case LE: or1 = LT; or2 = EQ; break; | |
4877 | case GE: or1 = GT; or2 = EQ; break; | |
4878 | case UNEQ: or1 = UNORDERED; or2 = EQ; break; | |
4879 | case LTGT: or1 = LT; or2 = GT; break; | |
4880 | case UNGT: or1 = UNORDERED; or2 = GT; break; | |
4881 | case UNLT: or1 = UNORDERED; or2 = LT; break; | |
4882 | default: abort (); | |
4883 | } | |
4884 | validate_condition_mode (or1, comp_mode); | |
4885 | validate_condition_mode (or2, comp_mode); | |
4886 | or1_rtx = gen_rtx (or1, SImode, compare_result, const0_rtx); | |
4887 | or2_rtx = gen_rtx (or2, SImode, compare_result, const0_rtx); | |
4888 | compare2_rtx = gen_rtx_COMPARE (CCEQmode, | |
4889 | gen_rtx_IOR (SImode, or1_rtx, or2_rtx), | |
4890 | const_true_rtx); | |
4891 | emit_insn (gen_rtx_SET (VOIDmode, or_result, compare2_rtx)); | |
4892 | ||
4893 | compare_result = or_result; | |
4894 | code = EQ; | |
4895 | } | |
4896 | ||
4897 | validate_condition_mode (code, GET_MODE (compare_result)); | |
4898 | ||
4899 | return gen_rtx (code, VOIDmode, compare_result, const0_rtx); | |
4900 | } | |
4901 | ||
4902 | ||
4903 | /* Emit the RTL for an sCOND pattern. */ | |
4904 | ||
4905 | void | |
4906 | rs6000_emit_sCOND (code, result) | |
4907 | enum rtx_code code; | |
4908 | rtx result; | |
4909 | { | |
4910 | rtx condition_rtx; | |
4911 | enum machine_mode op_mode; | |
4912 | ||
4913 | condition_rtx = rs6000_generate_compare (code); | |
4914 | ||
4915 | op_mode = GET_MODE (rs6000_compare_op0); | |
4916 | if (op_mode == VOIDmode) | |
4917 | op_mode = GET_MODE (rs6000_compare_op1); | |
4918 | ||
4919 | if (TARGET_POWERPC64 && (op_mode == DImode || rs6000_compare_fp_p)) | |
4920 | { | |
4921 | PUT_MODE (condition_rtx, DImode); | |
4922 | convert_move (result, condition_rtx, 0); | |
4923 | } | |
4924 | else | |
4925 | { | |
4926 | PUT_MODE (condition_rtx, SImode); | |
4927 | emit_insn (gen_rtx_SET (VOIDmode, result, condition_rtx)); | |
4928 | } | |
4929 | } | |
4930 | ||
39a10a29 GK |
4931 | /* Emit a branch of kind CODE to location LOC. */ |
4932 | ||
4933 | void | |
4934 | rs6000_emit_cbranch (code, loc) | |
4935 | enum rtx_code code; | |
4936 | rtx loc; | |
4937 | { | |
4938 | rtx condition_rtx, loc_ref; | |
4939 | ||
4940 | condition_rtx = rs6000_generate_compare (code); | |
4941 | loc_ref = gen_rtx_LABEL_REF (VOIDmode, loc); | |
4942 | emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, | |
4943 | gen_rtx_IF_THEN_ELSE (VOIDmode, condition_rtx, | |
4944 | loc_ref, pc_rtx))); | |
4945 | } | |
4946 | ||
12a4e8c5 GK |
4947 | /* Return the string to output a conditional branch to LABEL, which is |
4948 | the operand number of the label, or -1 if the branch is really a | |
4949 | conditional return. | |
4950 | ||
4951 | OP is the conditional expression. XEXP (OP, 0) is assumed to be a | |
4952 | condition code register and its mode specifies what kind of | |
4953 | comparison we made. | |
4954 | ||
4955 | REVERSED is non-zero if we should reverse the sense of the comparison. | |
4956 | ||
4957 | INSN is the insn. */ | |
4958 | ||
4959 | char * | |
4960 | output_cbranch (op, label, reversed, insn) | |
4961 | rtx op; | |
4962 | const char * label; | |
4963 | int reversed; | |
4964 | rtx insn; | |
4965 | { | |
4966 | static char string[64]; | |
4967 | enum rtx_code code = GET_CODE (op); | |
4968 | rtx cc_reg = XEXP (op, 0); | |
4969 | enum machine_mode mode = GET_MODE (cc_reg); | |
4970 | int cc_regno = REGNO (cc_reg) - CR0_REGNO; | |
39a10a29 | 4971 | int need_longbranch = label != NULL && get_attr_length (insn) == 8; |
12a4e8c5 GK |
4972 | int really_reversed = reversed ^ need_longbranch; |
4973 | char *s = string; | |
4974 | const char *ccode; | |
4975 | const char *pred; | |
4976 | rtx note; | |
4977 | ||
39a10a29 GK |
4978 | validate_condition_mode (code, mode); |
4979 | ||
4980 | /* Work out which way this really branches. We could use | |
4981 | reverse_condition_maybe_unordered here always but this | |
4982 | makes the resulting assembler clearer. */ | |
12a4e8c5 | 4983 | if (really_reversed) |
39a10a29 | 4984 | code = rs6000_reverse_condition (mode, code); |
12a4e8c5 | 4985 | |
39a10a29 | 4986 | switch (code) |
12a4e8c5 GK |
4987 | { |
4988 | /* Not all of these are actually distinct opcodes, but | |
4989 | we distinguish them for clarity of the resulting assembler. */ | |
50a0b056 GK |
4990 | case NE: case LTGT: |
4991 | ccode = "ne"; break; | |
4992 | case EQ: case UNEQ: | |
4993 | ccode = "eq"; break; | |
4994 | case GE: case GEU: | |
4995 | ccode = "ge"; break; | |
4996 | case GT: case GTU: case UNGT: | |
4997 | ccode = "gt"; break; | |
4998 | case LE: case LEU: | |
4999 | ccode = "le"; break; | |
5000 | case LT: case LTU: case UNLT: | |
5001 | ccode = "lt"; break; | |
12a4e8c5 GK |
5002 | case UNORDERED: ccode = "un"; break; |
5003 | case ORDERED: ccode = "nu"; break; | |
5004 | case UNGE: ccode = "nl"; break; | |
5005 | case UNLE: ccode = "ng"; break; | |
5006 | default: | |
a4f6c312 | 5007 | abort (); |
12a4e8c5 GK |
5008 | } |
5009 | ||
94a54f47 GK |
5010 | /* Maybe we have a guess as to how likely the branch is. |
5011 | The old mnemonics don't have a way to specify this information. */ | |
12a4e8c5 GK |
5012 | note = find_reg_note (insn, REG_BR_PROB, NULL_RTX); |
5013 | if (note != NULL_RTX) | |
5014 | { | |
5015 | /* PROB is the difference from 50%. */ | |
5016 | int prob = INTVAL (XEXP (note, 0)) - REG_BR_PROB_BASE / 2; | |
5017 | ||
5018 | /* For branches that are very close to 50%, assume not-taken. */ | |
5019 | if (abs (prob) > REG_BR_PROB_BASE / 20 | |
5020 | && ((prob > 0) ^ need_longbranch)) | |
5021 | pred = "+"; | |
5022 | else | |
5023 | pred = "-"; | |
5024 | } | |
5025 | else | |
5026 | pred = ""; | |
5027 | ||
5028 | if (label == NULL) | |
94a54f47 | 5029 | s += sprintf (s, "{b%sr|b%slr%s} ", ccode, ccode, pred); |
12a4e8c5 | 5030 | else |
94a54f47 | 5031 | s += sprintf (s, "{b%s|b%s%s} ", ccode, ccode, pred); |
12a4e8c5 | 5032 | |
37c67319 GK |
5033 | /* We need to escape any '%' characters in the reg_names string. |
5034 | Assume they'd only be the first character... */ | |
5035 | if (reg_names[cc_regno + CR0_REGNO][0] == '%') | |
5036 | *s++ = '%'; | |
94a54f47 | 5037 | s += sprintf (s, "%s", reg_names[cc_regno + CR0_REGNO]); |
12a4e8c5 GK |
5038 | |
5039 | if (label != NULL) | |
5040 | { | |
5041 | /* If the branch distance was too far, we may have to use an | |
5042 | unconditional branch to go the distance. */ | |
5043 | if (need_longbranch) | |
33011c35 | 5044 | s += sprintf (s, ",%c$+8\n\tb %s", '%', label); |
12a4e8c5 GK |
5045 | else |
5046 | s += sprintf (s, ",%s", label); | |
5047 | } | |
5048 | ||
5049 | return string; | |
5050 | } | |
50a0b056 GK |
5051 | |
5052 | /* Emit a conditional move: move TRUE_COND to DEST if OP of the | |
5053 | operands of the last comparison is nonzero/true, FALSE_COND if it | |
5054 | is zero/false. Return 0 if the hardware has no such operation. */ | |
a4f6c312 | 5055 | |
50a0b056 GK |
5056 | int |
5057 | rs6000_emit_cmove (dest, op, true_cond, false_cond) | |
5058 | rtx dest; | |
5059 | rtx op; | |
5060 | rtx true_cond; | |
5061 | rtx false_cond; | |
5062 | { | |
5063 | enum rtx_code code = GET_CODE (op); | |
5064 | rtx op0 = rs6000_compare_op0; | |
5065 | rtx op1 = rs6000_compare_op1; | |
5066 | REAL_VALUE_TYPE c1; | |
5067 | enum machine_mode mode = GET_MODE (op0); | |
5068 | rtx temp; | |
5069 | ||
5070 | /* First, work out if the hardware can do this at all, or | |
5071 | if it's too slow... */ | |
5072 | /* If the comparison is an integer one, since we only have fsel | |
5073 | it'll be cheaper to use a branch. */ | |
5074 | if (! rs6000_compare_fp_p) | |
5075 | return 0; | |
5076 | ||
5077 | /* Eliminate half of the comparisons by switching operands, this | |
5078 | makes the remaining code simpler. */ | |
5079 | if (code == UNLT || code == UNGT || code == UNORDERED || code == NE | |
5080 | || code == LTGT || code == LT) | |
5081 | { | |
5082 | code = reverse_condition_maybe_unordered (code); | |
5083 | temp = true_cond; | |
5084 | true_cond = false_cond; | |
5085 | false_cond = temp; | |
5086 | } | |
5087 | ||
5088 | /* UNEQ and LTGT take four instructions for a comparison with zero, | |
5089 | it'll probably be faster to use a branch here too. */ | |
5090 | if (code == UNEQ) | |
5091 | return 0; | |
5092 | ||
5093 | if (GET_CODE (op1) == CONST_DOUBLE) | |
5094 | REAL_VALUE_FROM_CONST_DOUBLE (c1, op1); | |
5095 | ||
5096 | /* We're going to try to implement comparions by performing | |
5097 | a subtract, then comparing against zero. Unfortunately, | |
5098 | Inf - Inf is NaN which is not zero, and so if we don't | |
5099 | know that the the operand is finite and the comparison | |
5100 | would treat EQ different to UNORDERED, we can't do it. */ | |
5101 | if (! flag_unsafe_math_optimizations | |
5102 | && code != GT && code != UNGE | |
5103 | && (GET_CODE (op1) != CONST_DOUBLE || target_isinf (c1)) | |
5104 | /* Constructs of the form (a OP b ? a : b) are safe. */ | |
5105 | && ((! rtx_equal_p (op0, false_cond) && ! rtx_equal_p (op1, false_cond)) | |
5106 | || (! rtx_equal_p (op0, true_cond) | |
5107 | && ! rtx_equal_p (op1, true_cond)))) | |
5108 | return 0; | |
5109 | /* At this point we know we can use fsel. */ | |
5110 | ||
5111 | /* Reduce the comparison to a comparison against zero. */ | |
5112 | temp = gen_reg_rtx (mode); | |
5113 | emit_insn (gen_rtx_SET (VOIDmode, temp, | |
5114 | gen_rtx_MINUS (mode, op0, op1))); | |
5115 | op0 = temp; | |
5116 | op1 = CONST0_RTX (mode); | |
5117 | ||
5118 | /* If we don't care about NaNs we can reduce some of the comparisons | |
5119 | down to faster ones. */ | |
5120 | if (flag_unsafe_math_optimizations) | |
5121 | switch (code) | |
5122 | { | |
5123 | case GT: | |
5124 | code = LE; | |
5125 | temp = true_cond; | |
5126 | true_cond = false_cond; | |
5127 | false_cond = temp; | |
5128 | break; | |
5129 | case UNGE: | |
5130 | code = GE; | |
5131 | break; | |
5132 | case UNEQ: | |
5133 | code = EQ; | |
5134 | break; | |
5135 | default: | |
5136 | break; | |
5137 | } | |
5138 | ||
5139 | /* Now, reduce everything down to a GE. */ | |
5140 | switch (code) | |
5141 | { | |
5142 | case GE: | |
5143 | break; | |
5144 | ||
5145 | case LE: | |
5146 | temp = gen_reg_rtx (mode); | |
5147 | emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (mode, op0))); | |
5148 | op0 = temp; | |
5149 | break; | |
5150 | ||
5151 | case ORDERED: | |
5152 | temp = gen_reg_rtx (mode); | |
5153 | emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_ABS (mode, op0))); | |
5154 | op0 = temp; | |
5155 | break; | |
5156 | ||
5157 | case EQ: | |
5158 | temp = gen_reg_rtx (mode); | |
5159 | emit_insn (gen_rtx_SET (VOIDmode, temp, | |
5160 | gen_rtx_NEG (mode, | |
5161 | gen_rtx_ABS (mode, op0)))); | |
5162 | op0 = temp; | |
5163 | break; | |
5164 | ||
5165 | case UNGE: | |
5166 | temp = gen_reg_rtx (mode); | |
5167 | emit_insn (gen_rtx_SET (VOIDmode, temp, | |
5168 | gen_rtx_IF_THEN_ELSE (mode, | |
5169 | gen_rtx_GE (VOIDmode, | |
5170 | op0, op1), | |
5171 | true_cond, false_cond))); | |
5172 | false_cond = temp; | |
5173 | true_cond = false_cond; | |
5174 | ||
5175 | temp = gen_reg_rtx (mode); | |
5176 | emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (mode, op0))); | |
5177 | op0 = temp; | |
5178 | break; | |
5179 | ||
5180 | case GT: | |
5181 | temp = gen_reg_rtx (mode); | |
5182 | emit_insn (gen_rtx_SET (VOIDmode, temp, | |
5183 | gen_rtx_IF_THEN_ELSE (mode, | |
5184 | gen_rtx_GE (VOIDmode, | |
5185 | op0, op1), | |
5186 | true_cond, false_cond))); | |
5187 | true_cond = temp; | |
5188 | false_cond = true_cond; | |
5189 | ||
5190 | temp = gen_reg_rtx (mode); | |
5191 | emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (mode, op0))); | |
5192 | op0 = temp; | |
5193 | break; | |
5194 | ||
5195 | default: | |
5196 | abort (); | |
5197 | } | |
5198 | ||
5199 | emit_insn (gen_rtx_SET (VOIDmode, dest, | |
5200 | gen_rtx_IF_THEN_ELSE (mode, | |
5201 | gen_rtx_GE (VOIDmode, | |
5202 | op0, op1), | |
5203 | true_cond, false_cond))); | |
5204 | return 1; | |
5205 | } | |
5206 | ||
5207 | void | |
5208 | rs6000_emit_minmax (dest, code, op0, op1) | |
5209 | rtx dest; | |
5210 | enum rtx_code code; | |
5211 | rtx op0; | |
5212 | rtx op1; | |
5213 | { | |
5214 | enum machine_mode mode = GET_MODE (op0); | |
5215 | rtx target; | |
5216 | if (code == SMAX || code == UMAX) | |
5217 | target = emit_conditional_move (dest, GE, op0, op1, mode, | |
5218 | op0, op1, mode, 0); | |
5219 | else | |
5220 | target = emit_conditional_move (dest, GE, op0, op1, mode, | |
5221 | op1, op0, mode, 0); | |
5222 | if (target == NULL_RTX) | |
5223 | abort (); | |
5224 | if (target != dest) | |
5225 | emit_move_insn (dest, target); | |
5226 | } | |
12a4e8c5 | 5227 | \f |
a4f6c312 SS |
5228 | /* This page contains routines that are used to determine what the |
5229 | function prologue and epilogue code will do and write them out. */ | |
9878760c | 5230 | |
a4f6c312 SS |
5231 | /* Return the first fixed-point register that is required to be |
5232 | saved. 32 if none. */ | |
9878760c RK |
5233 | |
5234 | int | |
5235 | first_reg_to_save () | |
5236 | { | |
5237 | int first_reg; | |
5238 | ||
5239 | /* Find lowest numbered live register. */ | |
5240 | for (first_reg = 13; first_reg <= 31; first_reg++) | |
a38d360d GK |
5241 | if (regs_ever_live[first_reg] |
5242 | && (! call_used_regs[first_reg] | |
5243 | || (first_reg == PIC_OFFSET_TABLE_REGNUM | |
ee890fe2 SS |
5244 | && (((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) |
5245 | && flag_pic == 1) | |
5246 | || (DEFAULT_ABI == ABI_DARWIN | |
5247 | && flag_pic))))) | |
9878760c RK |
5248 | break; |
5249 | ||
b5253831 DE |
5250 | if (profile_flag) |
5251 | { | |
5252 | /* AIX must save/restore every register that contains a parameter | |
5253 | before/after the .__mcount call plus an additional register | |
5254 | for the static chain, if needed; use registers from 30 down to 22 | |
5255 | to do this. */ | |
ee890fe2 | 5256 | if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) |
b5253831 DE |
5257 | { |
5258 | int last_parm_reg, profile_first_reg; | |
5259 | ||
5260 | /* Figure out last used parameter register. The proper thing | |
5261 | to do is to walk incoming args of the function. A function | |
5262 | might have live parameter registers even if it has no | |
5263 | incoming args. */ | |
5264 | for (last_parm_reg = 10; | |
5265 | last_parm_reg > 2 && ! regs_ever_live [last_parm_reg]; | |
5266 | last_parm_reg--) | |
5267 | ; | |
5268 | ||
5269 | /* Calculate first reg for saving parameter registers | |
5270 | and static chain. | |
5271 | Skip reg 31 which may contain the frame pointer. */ | |
5272 | profile_first_reg = (33 - last_parm_reg | |
5273 | - (current_function_needs_context ? 1 : 0)); | |
ee890fe2 SS |
5274 | #if TARGET_MACHO |
5275 | /* Need to skip another reg to account for R31 being PICBASE | |
5276 | (when flag_pic is set) or R30 being used as the frame | |
5277 | pointer (when flag_pic is not set). */ | |
5278 | --profile_first_reg; | |
5279 | #endif | |
b5253831 DE |
5280 | /* Do not save frame pointer if no parameters needs to be saved. */ |
5281 | if (profile_first_reg == 31) | |
5282 | profile_first_reg = 32; | |
5283 | ||
5284 | if (first_reg > profile_first_reg) | |
5285 | first_reg = profile_first_reg; | |
5286 | } | |
e165f3f0 | 5287 | |
b5253831 DE |
5288 | /* SVR4 may need one register to preserve the static chain. */ |
5289 | else if (current_function_needs_context) | |
5290 | { | |
5291 | /* Skip reg 31 which may contain the frame pointer. */ | |
5292 | if (first_reg > 30) | |
5293 | first_reg = 30; | |
5294 | } | |
5295 | } | |
e165f3f0 | 5296 | |
ee890fe2 SS |
5297 | #if TARGET_MACHO |
5298 | if (flag_pic && current_function_uses_pic_offset_table && | |
5299 | (first_reg > PIC_OFFSET_TABLE_REGNUM)) | |
5300 | return PIC_OFFSET_TABLE_REGNUM; | |
5301 | #endif | |
5302 | ||
9878760c RK |
5303 | return first_reg; |
5304 | } | |
5305 | ||
5306 | /* Similar, for FP regs. */ | |
5307 | ||
5308 | int | |
5309 | first_fp_reg_to_save () | |
5310 | { | |
5311 | int first_reg; | |
5312 | ||
5313 | /* Find lowest numbered live register. */ | |
5314 | for (first_reg = 14 + 32; first_reg <= 63; first_reg++) | |
5315 | if (regs_ever_live[first_reg]) | |
5316 | break; | |
5317 | ||
5318 | return first_reg; | |
5319 | } | |
4697a36c MM |
5320 | \f |
5321 | /* Calculate the stack information for the current function. This is | |
5322 | complicated by having two separate calling sequences, the AIX calling | |
5323 | sequence and the V.4 calling sequence. | |
5324 | ||
592696dd | 5325 | AIX (and Darwin/Mac OS X) stack frames look like: |
a260abc9 | 5326 | 32-bit 64-bit |
4697a36c | 5327 | SP----> +---------------------------------------+ |
a260abc9 | 5328 | | back chain to caller | 0 0 |
4697a36c | 5329 | +---------------------------------------+ |
a260abc9 | 5330 | | saved CR | 4 8 (8-11) |
4697a36c | 5331 | +---------------------------------------+ |
a260abc9 | 5332 | | saved LR | 8 16 |
4697a36c | 5333 | +---------------------------------------+ |
a260abc9 | 5334 | | reserved for compilers | 12 24 |
4697a36c | 5335 | +---------------------------------------+ |
a260abc9 | 5336 | | reserved for binders | 16 32 |
4697a36c | 5337 | +---------------------------------------+ |
a260abc9 | 5338 | | saved TOC pointer | 20 40 |
4697a36c | 5339 | +---------------------------------------+ |
a260abc9 | 5340 | | Parameter save area (P) | 24 48 |
4697a36c | 5341 | +---------------------------------------+ |
a260abc9 | 5342 | | Alloca space (A) | 24+P etc. |
802a0058 | 5343 | +---------------------------------------+ |
a7df97e6 | 5344 | | Local variable space (L) | 24+P+A |
4697a36c | 5345 | +---------------------------------------+ |
a7df97e6 | 5346 | | Float/int conversion temporary (X) | 24+P+A+L |
4697a36c | 5347 | +---------------------------------------+ |
a7df97e6 | 5348 | | Save area for GP registers (G) | 24+P+A+X+L |
4697a36c | 5349 | +---------------------------------------+ |
a7df97e6 | 5350 | | Save area for FP registers (F) | 24+P+A+X+L+G |
4697a36c MM |
5351 | +---------------------------------------+ |
5352 | old SP->| back chain to caller's caller | | |
5353 | +---------------------------------------+ | |
5354 | ||
5376a30c KR |
5355 | The required alignment for AIX configurations is two words (i.e., 8 |
5356 | or 16 bytes). | |
5357 | ||
5358 | ||
4697a36c MM |
5359 | V.4 stack frames look like: |
5360 | ||
5361 | SP----> +---------------------------------------+ | |
5362 | | back chain to caller | 0 | |
5363 | +---------------------------------------+ | |
5eb387b8 | 5364 | | caller's saved LR | 4 |
4697a36c MM |
5365 | +---------------------------------------+ |
5366 | | Parameter save area (P) | 8 | |
5367 | +---------------------------------------+ | |
a7df97e6 MM |
5368 | | Alloca space (A) | 8+P |
5369 | +---------------------------------------+ | |
5370 | | Varargs save area (V) | 8+P+A | |
5371 | +---------------------------------------+ | |
5372 | | Local variable space (L) | 8+P+A+V | |
5373 | +---------------------------------------+ | |
5374 | | Float/int conversion temporary (X) | 8+P+A+V+L | |
4697a36c | 5375 | +---------------------------------------+ |
a7df97e6 MM |
5376 | | saved CR (C) | 8+P+A+V+L+X |
5377 | +---------------------------------------+ | |
5378 | | Save area for GP registers (G) | 8+P+A+V+L+X+C | |
5379 | +---------------------------------------+ | |
5380 | | Save area for FP registers (F) | 8+P+A+V+L+X+C+G | |
4697a36c MM |
5381 | +---------------------------------------+ |
5382 | old SP->| back chain to caller's caller | | |
5383 | +---------------------------------------+ | |
b6c9286a | 5384 | |
5376a30c KR |
5385 | The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is |
5386 | given. (But note below and in sysv4.h that we require only 8 and | |
5387 | may round up the size of our stack frame anyways. The historical | |
5388 | reason is early versions of powerpc-linux which didn't properly | |
5389 | align the stack at program startup. A happy side-effect is that | |
5390 | -mno-eabi libraries can be used with -meabi programs.) | |
5391 | ||
5376a30c KR |
5392 | The EABI configuration defaults to the V.4 layout, unless |
5393 | -mcall-aix is used, in which case the AIX layout is used. However, | |
5394 | the stack alignment requirements may differ. If -mno-eabi is not | |
5395 | given, the required stack alignment is 8 bytes; if -mno-eabi is | |
5396 | given, the required alignment is 16 bytes. (But see V.4 comment | |
5397 | above.) */ | |
4697a36c | 5398 | |
61b2fbe7 MM |
5399 | #ifndef ABI_STACK_BOUNDARY |
5400 | #define ABI_STACK_BOUNDARY STACK_BOUNDARY | |
5401 | #endif | |
5402 | ||
4697a36c MM |
5403 | rs6000_stack_t * |
5404 | rs6000_stack_info () | |
5405 | { | |
5406 | static rs6000_stack_t info, zero_info; | |
5407 | rs6000_stack_t *info_ptr = &info; | |
9ebbca7d | 5408 | int reg_size = TARGET_POWERPC64 ? 8 : 4; |
24d304eb | 5409 | enum rs6000_abi abi; |
83720594 | 5410 | int ehrd_size; |
b6c9286a | 5411 | int total_raw_size; |
4697a36c | 5412 | |
a4f6c312 | 5413 | /* Zero all fields portably. */ |
4697a36c MM |
5414 | info = zero_info; |
5415 | ||
a4f6c312 | 5416 | /* Select which calling sequence. */ |
b6c9286a | 5417 | info_ptr->abi = abi = DEFAULT_ABI; |
9878760c | 5418 | |
a4f6c312 | 5419 | /* Calculate which registers need to be saved & save area size. */ |
4697a36c | 5420 | info_ptr->first_gp_reg_save = first_reg_to_save (); |
906fb125 GK |
5421 | /* Assume that we will have to save PIC_OFFSET_TABLE_REGNUM, |
5422 | even if it currently looks like we won't. */ | |
2bfcf297 DB |
5423 | if (((TARGET_TOC && TARGET_MINIMAL_TOC) |
5424 | || (flag_pic == 1 | |
5425 | && (abi == ABI_V4 || abi == ABI_SOLARIS)) | |
ee890fe2 SS |
5426 | || (flag_pic && |
5427 | abi == ABI_DARWIN)) | |
906fb125 GK |
5428 | && info_ptr->first_gp_reg_save > PIC_OFFSET_TABLE_REGNUM) |
5429 | info_ptr->gp_size = reg_size * (32 - PIC_OFFSET_TABLE_REGNUM); | |
5430 | else | |
5431 | info_ptr->gp_size = reg_size * (32 - info_ptr->first_gp_reg_save); | |
4697a36c MM |
5432 | |
5433 | info_ptr->first_fp_reg_save = first_fp_reg_to_save (); | |
5434 | info_ptr->fp_size = 8 * (64 - info_ptr->first_fp_reg_save); | |
5435 | ||
592696dd | 5436 | /* Does this function call anything? */ |
71f123ca FS |
5437 | info_ptr->calls_p = (! current_function_is_leaf |
5438 | || cfun->machine->ra_needs_full_frame); | |
b6c9286a | 5439 | |
a4f6c312 | 5440 | /* Determine if we need to save the link register. */ |
71f123ca | 5441 | if (rs6000_ra_ever_killed () |
38c1f2d7 | 5442 | || (DEFAULT_ABI == ABI_AIX && profile_flag) |
4697a36c MM |
5443 | #ifdef TARGET_RELOCATABLE |
5444 | || (TARGET_RELOCATABLE && (get_pool_size () != 0)) | |
5445 | #endif | |
5446 | || (info_ptr->first_fp_reg_save != 64 | |
5447 | && !FP_SAVE_INLINE (info_ptr->first_fp_reg_save)) | |
24d304eb | 5448 | || (abi == ABI_V4 && current_function_calls_alloca) |
c81bebd7 | 5449 | || (abi == ABI_SOLARIS && current_function_calls_alloca) |
a4f6c312 SS |
5450 | || (DEFAULT_ABI == ABI_DARWIN |
5451 | && flag_pic | |
5452 | && current_function_uses_pic_offset_table) | |
4697a36c MM |
5453 | || info_ptr->calls_p) |
5454 | { | |
5455 | info_ptr->lr_save_p = 1; | |
9ebbca7d | 5456 | regs_ever_live[LINK_REGISTER_REGNUM] = 1; |
4697a36c MM |
5457 | } |
5458 | ||
9ebbca7d GK |
5459 | /* Determine if we need to save the condition code registers. */ |
5460 | if (regs_ever_live[CR2_REGNO] | |
5461 | || regs_ever_live[CR3_REGNO] | |
5462 | || regs_ever_live[CR4_REGNO]) | |
4697a36c MM |
5463 | { |
5464 | info_ptr->cr_save_p = 1; | |
9ebbca7d | 5465 | if (abi == ABI_V4 || abi == ABI_SOLARIS) |
4697a36c MM |
5466 | info_ptr->cr_size = reg_size; |
5467 | } | |
5468 | ||
83720594 RH |
5469 | /* If the current function calls __builtin_eh_return, then we need |
5470 | to allocate stack space for registers that will hold data for | |
5471 | the exception handler. */ | |
5472 | if (current_function_calls_eh_return) | |
5473 | { | |
5474 | unsigned int i; | |
5475 | for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i) | |
5476 | continue; | |
5477 | ehrd_size = i * UNITS_PER_WORD; | |
5478 | } | |
5479 | else | |
5480 | ehrd_size = 0; | |
5481 | ||
592696dd | 5482 | /* Determine various sizes. */ |
4697a36c MM |
5483 | info_ptr->reg_size = reg_size; |
5484 | info_ptr->fixed_size = RS6000_SAVE_AREA; | |
5485 | info_ptr->varargs_size = RS6000_VARARGS_AREA; | |
189e03e3 | 5486 | info_ptr->vars_size = RS6000_ALIGN (get_frame_size (), 8); |
a4f6c312 SS |
5487 | info_ptr->parm_size = RS6000_ALIGN (current_function_outgoing_args_size, |
5488 | 8); | |
189e03e3 | 5489 | info_ptr->save_size = RS6000_ALIGN (info_ptr->fp_size |
a4f6c312 SS |
5490 | + info_ptr->gp_size |
5491 | + ehrd_size | |
5492 | + info_ptr->cr_size | |
5493 | + info_ptr->lr_size | |
5494 | + info_ptr->toc_size, 8); | |
ee890fe2 SS |
5495 | if (DEFAULT_ABI == ABI_DARWIN) |
5496 | info_ptr->save_size = RS6000_ALIGN (info_ptr->save_size, 16); | |
b6c9286a | 5497 | |
592696dd | 5498 | /* Calculate the offsets. */ |
24d304eb | 5499 | switch (abi) |
4697a36c | 5500 | { |
b6c9286a | 5501 | case ABI_NONE: |
24d304eb | 5502 | default: |
b6c9286a MM |
5503 | abort (); |
5504 | ||
5505 | case ABI_AIX: | |
5506 | case ABI_AIX_NODESC: | |
ee890fe2 | 5507 | case ABI_DARWIN: |
b6c9286a MM |
5508 | info_ptr->fp_save_offset = - info_ptr->fp_size; |
5509 | info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size; | |
83720594 | 5510 | info_ptr->ehrd_offset = info_ptr->gp_save_offset - ehrd_size; |
a260abc9 DE |
5511 | info_ptr->cr_save_offset = reg_size; /* first word when 64-bit. */ |
5512 | info_ptr->lr_save_offset = 2*reg_size; | |
24d304eb RK |
5513 | break; |
5514 | ||
5515 | case ABI_V4: | |
c81bebd7 | 5516 | case ABI_SOLARIS: |
b6c9286a MM |
5517 | info_ptr->fp_save_offset = - info_ptr->fp_size; |
5518 | info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size; | |
a7df97e6 MM |
5519 | info_ptr->cr_save_offset = info_ptr->gp_save_offset - info_ptr->cr_size; |
5520 | info_ptr->toc_save_offset = info_ptr->cr_save_offset - info_ptr->toc_size; | |
83720594 | 5521 | info_ptr->ehrd_offset = info_ptr->toc_save_offset - ehrd_size; |
b6c9286a MM |
5522 | info_ptr->lr_save_offset = reg_size; |
5523 | break; | |
4697a36c MM |
5524 | } |
5525 | ||
ff381587 MM |
5526 | total_raw_size = (info_ptr->vars_size |
5527 | + info_ptr->parm_size | |
ff381587 MM |
5528 | + info_ptr->save_size |
5529 | + info_ptr->varargs_size | |
5530 | + info_ptr->fixed_size); | |
5531 | ||
a4f6c312 SS |
5532 | info_ptr->total_size = |
5533 | RS6000_ALIGN (total_raw_size, ABI_STACK_BOUNDARY / BITS_PER_UNIT); | |
ff381587 MM |
5534 | |
5535 | /* Determine if we need to allocate any stack frame: | |
5536 | ||
a4f6c312 SS |
5537 | For AIX we need to push the stack if a frame pointer is needed |
5538 | (because the stack might be dynamically adjusted), if we are | |
5539 | debugging, if we make calls, or if the sum of fp_save, gp_save, | |
5540 | and local variables are more than the space needed to save all | |
5541 | non-volatile registers: 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8 | |
5542 | + 18*8 = 288 (GPR13 reserved). | |
ff381587 | 5543 | |
a4f6c312 SS |
5544 | For V.4 we don't have the stack cushion that AIX uses, but assume |
5545 | that the debugger can handle stackless frames. */ | |
ff381587 MM |
5546 | |
5547 | if (info_ptr->calls_p) | |
5548 | info_ptr->push_p = 1; | |
5549 | ||
9ebbca7d | 5550 | else if (abi == ABI_V4 || abi == ABI_SOLARIS) |
ff381587 | 5551 | info_ptr->push_p = (total_raw_size > info_ptr->fixed_size |
9ebbca7d | 5552 | || info_ptr->calls_p); |
ff381587 MM |
5553 | |
5554 | else | |
5555 | info_ptr->push_p = (frame_pointer_needed | |
ee890fe2 | 5556 | || (abi != ABI_DARWIN && write_symbols != NO_DEBUG) |
ff381587 | 5557 | || ((total_raw_size - info_ptr->fixed_size) |
bfc79d3b | 5558 | > (TARGET_32BIT ? 220 : 288))); |
ff381587 | 5559 | |
a4f6c312 | 5560 | /* Zero offsets if we're not saving those registers. */ |
8dda1a21 | 5561 | if (info_ptr->fp_size == 0) |
4697a36c MM |
5562 | info_ptr->fp_save_offset = 0; |
5563 | ||
8dda1a21 | 5564 | if (info_ptr->gp_size == 0) |
4697a36c MM |
5565 | info_ptr->gp_save_offset = 0; |
5566 | ||
c81fc13e | 5567 | if (! info_ptr->lr_save_p) |
4697a36c MM |
5568 | info_ptr->lr_save_offset = 0; |
5569 | ||
c81fc13e | 5570 | if (! info_ptr->cr_save_p) |
4697a36c MM |
5571 | info_ptr->cr_save_offset = 0; |
5572 | ||
c81fc13e | 5573 | if (! info_ptr->toc_save_p) |
b6c9286a MM |
5574 | info_ptr->toc_save_offset = 0; |
5575 | ||
4697a36c MM |
5576 | return info_ptr; |
5577 | } | |
5578 | ||
5579 | void | |
5580 | debug_stack_info (info) | |
5581 | rs6000_stack_t *info; | |
9878760c | 5582 | { |
d330fd93 | 5583 | const char *abi_string; |
24d304eb | 5584 | |
c81fc13e | 5585 | if (! info) |
4697a36c MM |
5586 | info = rs6000_stack_info (); |
5587 | ||
5588 | fprintf (stderr, "\nStack information for function %s:\n", | |
5589 | ((current_function_decl && DECL_NAME (current_function_decl)) | |
5590 | ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl)) | |
5591 | : "<unknown>")); | |
5592 | ||
24d304eb RK |
5593 | switch (info->abi) |
5594 | { | |
b6c9286a MM |
5595 | default: abi_string = "Unknown"; break; |
5596 | case ABI_NONE: abi_string = "NONE"; break; | |
5597 | case ABI_AIX: abi_string = "AIX"; break; | |
5598 | case ABI_AIX_NODESC: abi_string = "AIX"; break; | |
ee890fe2 | 5599 | case ABI_DARWIN: abi_string = "Darwin"; break; |
b6c9286a | 5600 | case ABI_V4: abi_string = "V.4"; break; |
c81bebd7 | 5601 | case ABI_SOLARIS: abi_string = "Solaris"; break; |
24d304eb RK |
5602 | } |
5603 | ||
5604 | fprintf (stderr, "\tABI = %5s\n", abi_string); | |
5605 | ||
4697a36c MM |
5606 | if (info->first_gp_reg_save != 32) |
5607 | fprintf (stderr, "\tfirst_gp_reg_save = %5d\n", info->first_gp_reg_save); | |
5608 | ||
5609 | if (info->first_fp_reg_save != 64) | |
5610 | fprintf (stderr, "\tfirst_fp_reg_save = %5d\n", info->first_fp_reg_save); | |
9878760c | 5611 | |
4697a36c MM |
5612 | if (info->lr_save_p) |
5613 | fprintf (stderr, "\tlr_save_p = %5d\n", info->lr_save_p); | |
9878760c | 5614 | |
4697a36c MM |
5615 | if (info->cr_save_p) |
5616 | fprintf (stderr, "\tcr_save_p = %5d\n", info->cr_save_p); | |
5617 | ||
b6c9286a MM |
5618 | if (info->toc_save_p) |
5619 | fprintf (stderr, "\ttoc_save_p = %5d\n", info->toc_save_p); | |
5620 | ||
4697a36c MM |
5621 | if (info->push_p) |
5622 | fprintf (stderr, "\tpush_p = %5d\n", info->push_p); | |
5623 | ||
5624 | if (info->calls_p) | |
5625 | fprintf (stderr, "\tcalls_p = %5d\n", info->calls_p); | |
5626 | ||
4697a36c MM |
5627 | if (info->gp_save_offset) |
5628 | fprintf (stderr, "\tgp_save_offset = %5d\n", info->gp_save_offset); | |
5629 | ||
5630 | if (info->fp_save_offset) | |
5631 | fprintf (stderr, "\tfp_save_offset = %5d\n", info->fp_save_offset); | |
5632 | ||
5633 | if (info->lr_save_offset) | |
5634 | fprintf (stderr, "\tlr_save_offset = %5d\n", info->lr_save_offset); | |
5635 | ||
5636 | if (info->cr_save_offset) | |
5637 | fprintf (stderr, "\tcr_save_offset = %5d\n", info->cr_save_offset); | |
5638 | ||
b6c9286a MM |
5639 | if (info->toc_save_offset) |
5640 | fprintf (stderr, "\ttoc_save_offset = %5d\n", info->toc_save_offset); | |
5641 | ||
4697a36c MM |
5642 | if (info->varargs_save_offset) |
5643 | fprintf (stderr, "\tvarargs_save_offset = %5d\n", info->varargs_save_offset); | |
5644 | ||
5645 | if (info->total_size) | |
5646 | fprintf (stderr, "\ttotal_size = %5d\n", info->total_size); | |
5647 | ||
5648 | if (info->varargs_size) | |
5649 | fprintf (stderr, "\tvarargs_size = %5d\n", info->varargs_size); | |
5650 | ||
5651 | if (info->vars_size) | |
5652 | fprintf (stderr, "\tvars_size = %5d\n", info->vars_size); | |
5653 | ||
5654 | if (info->parm_size) | |
5655 | fprintf (stderr, "\tparm_size = %5d\n", info->parm_size); | |
5656 | ||
5657 | if (info->fixed_size) | |
5658 | fprintf (stderr, "\tfixed_size = %5d\n", info->fixed_size); | |
5659 | ||
5660 | if (info->gp_size) | |
5661 | fprintf (stderr, "\tgp_size = %5d\n", info->gp_size); | |
5662 | ||
5663 | if (info->fp_size) | |
5664 | fprintf (stderr, "\tfp_size = %5d\n", info->fp_size); | |
5665 | ||
a4f6c312 | 5666 | if (info->lr_size) |
ed947a96 | 5667 | fprintf (stderr, "\tlr_size = %5d\n", info->lr_size); |
b6c9286a | 5668 | |
4697a36c MM |
5669 | if (info->cr_size) |
5670 | fprintf (stderr, "\tcr_size = %5d\n", info->cr_size); | |
5671 | ||
a4f6c312 | 5672 | if (info->toc_size) |
b6c9286a MM |
5673 | fprintf (stderr, "\ttoc_size = %5d\n", info->toc_size); |
5674 | ||
4697a36c MM |
5675 | if (info->save_size) |
5676 | fprintf (stderr, "\tsave_size = %5d\n", info->save_size); | |
5677 | ||
5678 | if (info->reg_size != 4) | |
5679 | fprintf (stderr, "\treg_size = %5d\n", info->reg_size); | |
5680 | ||
5681 | fprintf (stderr, "\n"); | |
9878760c | 5682 | } |
71f123ca FS |
5683 | |
5684 | rtx | |
5685 | rs6000_return_addr (count, frame) | |
5686 | int count; | |
5687 | rtx frame; | |
5688 | { | |
a4f6c312 SS |
5689 | /* Currently we don't optimize very well between prolog and body |
5690 | code and for PIC code the code can be actually quite bad, so | |
5691 | don't try to be too clever here. */ | |
3418dd3a FS |
5692 | if (count != 0 |
5693 | || flag_pic != 0 | |
5694 | || DEFAULT_ABI == ABI_AIX | |
5695 | || DEFAULT_ABI == ABI_AIX_NODESC) | |
71f123ca FS |
5696 | { |
5697 | cfun->machine->ra_needs_full_frame = 1; | |
8ac61af7 RK |
5698 | |
5699 | return | |
5700 | gen_rtx_MEM | |
5701 | (Pmode, | |
5702 | memory_address | |
5703 | (Pmode, | |
5704 | plus_constant (copy_to_reg | |
5705 | (gen_rtx_MEM (Pmode, | |
5706 | memory_address (Pmode, frame))), | |
5707 | RETURN_ADDRESS_OFFSET))); | |
71f123ca FS |
5708 | } |
5709 | ||
9e2f7ec7 | 5710 | return get_hard_reg_initial_val (Pmode, LINK_REGISTER_REGNUM); |
71f123ca FS |
5711 | } |
5712 | ||
5713 | static int | |
5714 | rs6000_ra_ever_killed () | |
5715 | { | |
5716 | rtx top; | |
5717 | ||
5718 | #ifdef ASM_OUTPUT_MI_THUNK | |
5719 | if (current_function_is_thunk) | |
5720 | return 0; | |
5721 | #endif | |
9e2f7ec7 DD |
5722 | if (!has_hard_reg_initial_val (Pmode, LINK_REGISTER_REGNUM) |
5723 | || cfun->machine->ra_needs_full_frame) | |
71f123ca FS |
5724 | return regs_ever_live[LINK_REGISTER_REGNUM]; |
5725 | ||
5726 | push_topmost_sequence (); | |
5727 | top = get_insns (); | |
5728 | pop_topmost_sequence (); | |
5729 | ||
5730 | return reg_set_between_p (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM), | |
5731 | top, NULL_RTX); | |
5732 | } | |
4697a36c | 5733 | \f |
8cd8f856 GK |
5734 | /* Add a REG_MAYBE_DEAD note to the insn. */ |
5735 | static void | |
5736 | rs6000_maybe_dead (insn) | |
5737 | rtx insn; | |
5738 | { | |
5739 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD, | |
5740 | const0_rtx, | |
5741 | REG_NOTES (insn)); | |
5742 | } | |
5743 | ||
9ebbca7d | 5744 | /* Emit instructions needed to load the TOC register. |
c7ca610e | 5745 | This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is |
9ebbca7d | 5746 | a constant pool; or for SVR4 -fpic. */ |
c7ca610e RK |
5747 | |
5748 | void | |
9ebbca7d GK |
5749 | rs6000_emit_load_toc_table (fromprolog) |
5750 | int fromprolog; | |
c7ca610e | 5751 | { |
9ebbca7d GK |
5752 | rtx dest; |
5753 | dest = gen_rtx_REG (Pmode, PIC_OFFSET_TABLE_REGNUM); | |
c7ca610e | 5754 | |
2bfcf297 | 5755 | if (TARGET_ELF && DEFAULT_ABI != ABI_AIX) |
c7ca610e | 5756 | { |
9ebbca7d GK |
5757 | if ((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) |
5758 | && flag_pic == 1) | |
38c1f2d7 | 5759 | { |
9ebbca7d GK |
5760 | rtx temp = (fromprolog |
5761 | ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM) | |
5762 | : gen_reg_rtx (Pmode)); | |
2bfcf297 | 5763 | rs6000_maybe_dead (emit_insn (gen_load_toc_v4_pic_si (temp))); |
8cd8f856 | 5764 | rs6000_maybe_dead (emit_move_insn (dest, temp)); |
38c1f2d7 | 5765 | } |
9ebbca7d GK |
5766 | else if (flag_pic == 2) |
5767 | { | |
5768 | char buf[30]; | |
5769 | rtx tempLR = (fromprolog | |
5770 | ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM) | |
5771 | : gen_reg_rtx (Pmode)); | |
5772 | rtx temp0 = (fromprolog | |
5773 | ? gen_rtx_REG (Pmode, 0) | |
5774 | : gen_reg_rtx (Pmode)); | |
5775 | rtx symF; | |
5776 | ||
5777 | /* possibly create the toc section */ | |
5778 | if (! toc_initialized) | |
5779 | { | |
5780 | toc_section (); | |
5781 | function_section (current_function_decl); | |
5782 | } | |
5783 | ||
5784 | if (fromprolog) | |
5785 | { | |
5786 | rtx symL; | |
5787 | ||
5788 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno); | |
a8a05998 | 5789 | symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); |
38c1f2d7 | 5790 | |
9ebbca7d | 5791 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno); |
a8a05998 | 5792 | symL = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); |
38c1f2d7 | 5793 | |
8cd8f856 GK |
5794 | rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_1 (tempLR, |
5795 | symF))); | |
5796 | rs6000_maybe_dead (emit_move_insn (dest, tempLR)); | |
5797 | rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_2 (temp0, dest, | |
5798 | symL, | |
5799 | symF))); | |
9ebbca7d GK |
5800 | } |
5801 | else | |
5802 | { | |
5803 | rtx tocsym; | |
5804 | static int reload_toc_labelno = 0; | |
5805 | ||
b999aaeb | 5806 | tocsym = gen_rtx_SYMBOL_REF (Pmode, toc_label_name); |
38c1f2d7 | 5807 | |
9ebbca7d | 5808 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCG", reload_toc_labelno++); |
a8a05998 | 5809 | symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); |
9ebbca7d | 5810 | |
8cd8f856 GK |
5811 | rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_1b (tempLR, |
5812 | symF, | |
5813 | tocsym))); | |
5814 | rs6000_maybe_dead (emit_move_insn (dest, tempLR)); | |
5815 | rs6000_maybe_dead (emit_move_insn (temp0, | |
5816 | gen_rtx_MEM (Pmode, dest))); | |
9ebbca7d | 5817 | } |
8cd8f856 | 5818 | rs6000_maybe_dead (emit_insn (gen_addsi3 (dest, temp0, dest))); |
9ebbca7d GK |
5819 | } |
5820 | else if (flag_pic == 0 && TARGET_MINIMAL_TOC) | |
5821 | { | |
5822 | /* This is for AIX code running in non-PIC ELF. */ | |
5823 | char buf[30]; | |
5824 | rtx realsym; | |
38c1f2d7 | 5825 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1); |
a8a05998 | 5826 | realsym = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); |
9ebbca7d | 5827 | |
8cd8f856 GK |
5828 | rs6000_maybe_dead (emit_insn (gen_elf_high (dest, realsym))); |
5829 | rs6000_maybe_dead (emit_insn (gen_elf_low (dest, dest, realsym))); | |
9ebbca7d GK |
5830 | } |
5831 | else | |
a4f6c312 | 5832 | abort (); |
9ebbca7d GK |
5833 | } |
5834 | else | |
5835 | { | |
5836 | if (TARGET_32BIT) | |
8cd8f856 | 5837 | rs6000_maybe_dead (emit_insn (gen_load_toc_aix_si (dest))); |
9ebbca7d | 5838 | else |
8cd8f856 | 5839 | rs6000_maybe_dead (emit_insn (gen_load_toc_aix_di (dest))); |
9ebbca7d GK |
5840 | } |
5841 | } | |
5842 | ||
5843 | int | |
5844 | get_TOC_alias_set () | |
5845 | { | |
5846 | static int set = -1; | |
5847 | if (set == -1) | |
5848 | set = new_alias_set (); | |
5849 | return set; | |
5850 | } | |
5851 | ||
5852 | /* This retuns nonzero if the current function uses the TOC. This is | |
5853 | determined by the presence of (unspec ... 7), which is generated by | |
5854 | the various load_toc_* patterns. */ | |
a4f6c312 | 5855 | |
9ebbca7d GK |
5856 | int |
5857 | uses_TOC () | |
5858 | { | |
5859 | rtx insn; | |
38c1f2d7 | 5860 | |
9ebbca7d | 5861 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) |
2c3c49de | 5862 | if (INSN_P (insn)) |
9ebbca7d GK |
5863 | { |
5864 | rtx pat = PATTERN (insn); | |
5865 | int i; | |
5866 | ||
8cd8f856 | 5867 | if (GET_CODE (pat) == PARALLEL) |
9ebbca7d GK |
5868 | for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++) |
5869 | if (GET_CODE (XVECEXP (PATTERN (insn), 0, i)) == UNSPEC | |
5870 | && XINT (XVECEXP (PATTERN (insn), 0, i), 1) == 7) | |
5871 | return 1; | |
38c1f2d7 | 5872 | } |
9ebbca7d GK |
5873 | return 0; |
5874 | } | |
38c1f2d7 | 5875 | |
9ebbca7d | 5876 | rtx |
a4f6c312 | 5877 | create_TOC_reference (symbol) |
9ebbca7d GK |
5878 | rtx symbol; |
5879 | { | |
a8a05998 ZW |
5880 | return gen_rtx_PLUS (Pmode, |
5881 | gen_rtx_REG (Pmode, TOC_REGISTER), | |
5882 | gen_rtx_CONST (Pmode, | |
5883 | gen_rtx_MINUS (Pmode, symbol, | |
b999aaeb | 5884 | gen_rtx_SYMBOL_REF (Pmode, toc_label_name)))); |
9ebbca7d | 5885 | } |
38c1f2d7 | 5886 | |
9ebbca7d GK |
5887 | #if TARGET_AIX |
5888 | /* __throw will restore its own return address to be the same as the | |
5889 | return address of the function that the throw is being made to. | |
5890 | This is unfortunate, because we want to check the original | |
5891 | return address to see if we need to restore the TOC. | |
5892 | So we have to squirrel it away here. | |
5893 | This is used only in compiling __throw and __rethrow. | |
c7ca610e | 5894 | |
9ebbca7d GK |
5895 | Most of this code should be removed by CSE. */ |
5896 | static rtx insn_after_throw; | |
c7ca610e | 5897 | |
a4f6c312 | 5898 | /* This does the saving... */ |
9ebbca7d GK |
5899 | void |
5900 | rs6000_aix_emit_builtin_unwind_init () | |
5901 | { | |
5902 | rtx mem; | |
5903 | rtx stack_top = gen_reg_rtx (Pmode); | |
5904 | rtx opcode_addr = gen_reg_rtx (Pmode); | |
5905 | ||
5906 | insn_after_throw = gen_reg_rtx (SImode); | |
5907 | ||
5908 | mem = gen_rtx_MEM (Pmode, hard_frame_pointer_rtx); | |
5909 | emit_move_insn (stack_top, mem); | |
5910 | ||
5911 | mem = gen_rtx_MEM (Pmode, | |
5912 | gen_rtx_PLUS (Pmode, stack_top, | |
5913 | GEN_INT (2 * GET_MODE_SIZE (Pmode)))); | |
5914 | emit_move_insn (opcode_addr, mem); | |
5915 | emit_move_insn (insn_after_throw, gen_rtx_MEM (SImode, opcode_addr)); | |
c7ca610e RK |
5916 | } |
5917 | ||
a4f6c312 SS |
5918 | /* Emit insns to _restore_ the TOC register, at runtime (specifically |
5919 | in _eh.o). Only used on AIX. | |
9ebbca7d GK |
5920 | |
5921 | The idea is that on AIX, function calls look like this: | |
5922 | bl somefunction-trampoline | |
5923 | lwz r2,20(sp) | |
5924 | ||
a4f6c312 | 5925 | and later, |
9ebbca7d GK |
5926 | somefunction-trampoline: |
5927 | stw r2,20(sp) | |
5928 | ... load function address in the count register ... | |
5929 | bctr | |
5930 | or like this, if the linker determines that this is not a cross-module call | |
5931 | and so the TOC need not be restored: | |
5932 | bl somefunction | |
5933 | nop | |
5934 | or like this, if the compiler could determine that this is not a | |
5935 | cross-module call: | |
5936 | bl somefunction | |
5937 | now, the tricky bit here is that register 2 is saved and restored | |
5938 | by the _linker_, so we can't readily generate debugging information | |
5939 | for it. So we need to go back up the call chain looking at the | |
5940 | insns at return addresses to see which calls saved the TOC register | |
5941 | and so see where it gets restored from. | |
5942 | ||
5943 | Oh, and all this gets done in RTL inside the eh_epilogue pattern, | |
5944 | just before the actual epilogue. | |
5945 | ||
5946 | On the bright side, this incurs no space or time overhead unless an | |
5947 | exception is thrown, except for the extra code in libgcc.a. | |
5948 | ||
5949 | The parameter STACKSIZE is a register containing (at runtime) | |
5950 | the amount to be popped off the stack in addition to the stack frame | |
5951 | of this routine (which will be __throw or __rethrow, and so is | |
5952 | guaranteed to have a stack frame). */ | |
a4f6c312 | 5953 | |
9ebbca7d GK |
5954 | void |
5955 | rs6000_emit_eh_toc_restore (stacksize) | |
5956 | rtx stacksize; | |
5957 | { | |
5958 | rtx top_of_stack; | |
5959 | rtx bottom_of_stack = gen_reg_rtx (Pmode); | |
5960 | rtx tocompare = gen_reg_rtx (SImode); | |
5961 | rtx opcode = gen_reg_rtx (SImode); | |
5962 | rtx opcode_addr = gen_reg_rtx (Pmode); | |
5963 | rtx mem; | |
5964 | rtx loop_start = gen_label_rtx (); | |
5965 | rtx no_toc_restore_needed = gen_label_rtx (); | |
5966 | rtx loop_exit = gen_label_rtx (); | |
5967 | ||
5968 | mem = gen_rtx_MEM (Pmode, hard_frame_pointer_rtx); | |
ba4828e0 | 5969 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
9ebbca7d GK |
5970 | emit_move_insn (bottom_of_stack, mem); |
5971 | ||
5972 | top_of_stack = expand_binop (Pmode, add_optab, | |
5973 | bottom_of_stack, stacksize, | |
5974 | NULL_RTX, 1, OPTAB_WIDEN); | |
5975 | ||
5976 | emit_move_insn (tocompare, | |
5977 | GEN_INT (trunc_int_for_mode (TARGET_32BIT | |
5978 | ? 0x80410014 | |
5979 | : 0xE8410028, SImode))); | |
5980 | ||
5981 | if (insn_after_throw == NULL_RTX) | |
a4f6c312 | 5982 | abort (); |
9ebbca7d GK |
5983 | emit_move_insn (opcode, insn_after_throw); |
5984 | ||
6496a589 | 5985 | emit_note (NULL, NOTE_INSN_LOOP_BEG); |
9ebbca7d GK |
5986 | emit_label (loop_start); |
5987 | ||
5988 | do_compare_rtx_and_jump (opcode, tocompare, NE, 1, | |
5989 | SImode, NULL_RTX, 0, NULL_RTX, | |
5990 | no_toc_restore_needed); | |
5991 | ||
5992 | mem = gen_rtx_MEM (Pmode, | |
5993 | gen_rtx_PLUS (Pmode, bottom_of_stack, | |
5994 | GEN_INT (5 * GET_MODE_SIZE (Pmode)))); | |
5995 | emit_move_insn (gen_rtx_REG (Pmode, 2), mem); | |
5996 | ||
5997 | emit_label (no_toc_restore_needed); | |
5998 | do_compare_rtx_and_jump (top_of_stack, bottom_of_stack, EQ, 1, | |
5999 | Pmode, NULL_RTX, 0, NULL_RTX, | |
6000 | loop_exit); | |
6001 | ||
6002 | mem = gen_rtx_MEM (Pmode, bottom_of_stack); | |
ba4828e0 | 6003 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
9ebbca7d GK |
6004 | emit_move_insn (bottom_of_stack, mem); |
6005 | ||
6006 | mem = gen_rtx_MEM (Pmode, | |
6007 | gen_rtx_PLUS (Pmode, bottom_of_stack, | |
6008 | GEN_INT (2 * GET_MODE_SIZE (Pmode)))); | |
6009 | emit_move_insn (opcode_addr, mem); | |
6010 | emit_move_insn (opcode, gen_rtx_MEM (SImode, opcode_addr)); | |
6011 | ||
6496a589 | 6012 | emit_note (NULL, NOTE_INSN_LOOP_CONT); |
9ebbca7d | 6013 | emit_jump (loop_start); |
6496a589 | 6014 | emit_note (NULL, NOTE_INSN_LOOP_END); |
9ebbca7d GK |
6015 | emit_label (loop_exit); |
6016 | } | |
6017 | #endif /* TARGET_AIX */ | |
38c1f2d7 | 6018 | \f |
ba4828e0 RK |
6019 | /* This ties together stack memory (MEM with an alias set of |
6020 | rs6000_sr_alias_set) and the change to the stack pointer. */ | |
6021 | ||
9ebbca7d GK |
6022 | static void |
6023 | rs6000_emit_stack_tie () | |
6024 | { | |
ba4828e0 RK |
6025 | rtx mem = gen_rtx_MEM (BLKmode, gen_rtx_REG (Pmode, STACK_POINTER_REGNUM)); |
6026 | ||
6027 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
9ebbca7d GK |
6028 | emit_insn (gen_stack_tie (mem)); |
6029 | } | |
38c1f2d7 | 6030 | |
9ebbca7d GK |
6031 | /* Emit the correct code for allocating stack space, as insns. |
6032 | If COPY_R12, make sure a copy of the old frame is left in r12. | |
6033 | The generated code may use hard register 0 as a temporary. */ | |
6034 | ||
6035 | static void | |
6036 | rs6000_emit_allocate_stack (size, copy_r12) | |
6037 | HOST_WIDE_INT size; | |
38c1f2d7 MM |
6038 | int copy_r12; |
6039 | { | |
9ebbca7d GK |
6040 | rtx insn; |
6041 | rtx stack_reg = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM); | |
6042 | rtx tmp_reg = gen_rtx_REG (Pmode, 0); | |
6043 | rtx todec = GEN_INT (-size); | |
a157febd GK |
6044 | |
6045 | if (current_function_limit_stack) | |
6046 | { | |
6047 | if (REG_P (stack_limit_rtx) | |
6048 | && REGNO (stack_limit_rtx) > 1 | |
6049 | && REGNO (stack_limit_rtx) <= 31) | |
6050 | { | |
9ebbca7d GK |
6051 | emit_insn (Pmode == SImode |
6052 | ? gen_addsi3 (tmp_reg, | |
6053 | stack_limit_rtx, | |
6054 | GEN_INT (size)) | |
6055 | : gen_adddi3 (tmp_reg, | |
6056 | stack_limit_rtx, | |
6057 | GEN_INT (size))); | |
6058 | ||
6059 | emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg, | |
6060 | const0_rtx)); | |
a157febd GK |
6061 | } |
6062 | else if (GET_CODE (stack_limit_rtx) == SYMBOL_REF | |
9ebbca7d | 6063 | && TARGET_32BIT |
a157febd GK |
6064 | && (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS)) |
6065 | { | |
9ebbca7d GK |
6066 | rtx toload = gen_rtx_CONST (VOIDmode, |
6067 | gen_rtx_PLUS (Pmode, | |
6068 | stack_limit_rtx, | |
6069 | GEN_INT (size))); | |
6070 | ||
6071 | emit_insn (gen_elf_high (tmp_reg, toload)); | |
6072 | emit_insn (gen_elf_low (tmp_reg, tmp_reg, toload)); | |
6073 | emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg, | |
6074 | const0_rtx)); | |
a157febd GK |
6075 | } |
6076 | else | |
6077 | warning ("stack limit expression is not supported"); | |
6078 | } | |
6079 | ||
9ebbca7d GK |
6080 | if (copy_r12 || ! TARGET_UPDATE) |
6081 | emit_move_insn (gen_rtx_REG (Pmode, 12), stack_reg); | |
6082 | ||
38c1f2d7 MM |
6083 | if (TARGET_UPDATE) |
6084 | { | |
9ebbca7d | 6085 | if (size > 32767) |
38c1f2d7 | 6086 | { |
9ebbca7d GK |
6087 | /* Need a note here so that try_split doesn't get confused. */ |
6088 | if (get_last_insn() == NULL_RTX) | |
6089 | emit_note (0, NOTE_INSN_DELETED); | |
6090 | insn = emit_move_insn (tmp_reg, todec); | |
6091 | try_split (PATTERN (insn), insn, 0); | |
6092 | todec = tmp_reg; | |
38c1f2d7 | 6093 | } |
9ebbca7d GK |
6094 | |
6095 | if (Pmode == SImode) | |
6096 | insn = emit_insn (gen_movsi_update (stack_reg, stack_reg, | |
6097 | todec, stack_reg)); | |
6098 | else | |
6099 | insn = emit_insn (gen_movdi_update (stack_reg, stack_reg, | |
6100 | todec, stack_reg)); | |
38c1f2d7 MM |
6101 | } |
6102 | else | |
6103 | { | |
9ebbca7d GK |
6104 | if (Pmode == SImode) |
6105 | insn = emit_insn (gen_addsi3 (stack_reg, stack_reg, todec)); | |
38c1f2d7 | 6106 | else |
9ebbca7d GK |
6107 | insn = emit_insn (gen_adddi3 (stack_reg, stack_reg, todec)); |
6108 | emit_move_insn (gen_rtx_MEM (Pmode, stack_reg), | |
6109 | gen_rtx_REG (Pmode, 12)); | |
6110 | } | |
6111 | ||
6112 | RTX_FRAME_RELATED_P (insn) = 1; | |
6113 | REG_NOTES (insn) = | |
6114 | gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, | |
6115 | gen_rtx_SET (VOIDmode, stack_reg, | |
6116 | gen_rtx_PLUS (Pmode, stack_reg, | |
6117 | GEN_INT (-size))), | |
6118 | REG_NOTES (insn)); | |
6119 | } | |
6120 | ||
a4f6c312 SS |
6121 | /* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced |
6122 | with (plus:P (reg 1) VAL), and with REG2 replaced with RREG if REG2 | |
6123 | is not NULL. It would be nice if dwarf2out_frame_debug_expr could | |
6124 | deduce these equivalences by itself so it wasn't necessary to hold | |
6125 | its hand so much. */ | |
9ebbca7d GK |
6126 | |
6127 | static void | |
6128 | rs6000_frame_related (insn, reg, val, reg2, rreg) | |
6129 | rtx insn; | |
6130 | rtx reg; | |
6131 | HOST_WIDE_INT val; | |
6132 | rtx reg2; | |
6133 | rtx rreg; | |
6134 | { | |
6135 | rtx real, temp; | |
6136 | ||
6137 | real = copy_rtx (PATTERN (insn)); | |
6138 | ||
6139 | real = replace_rtx (real, reg, | |
6140 | gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, | |
6141 | STACK_POINTER_REGNUM), | |
6142 | GEN_INT (val))); | |
6143 | ||
6144 | /* We expect that 'real' is either a SET or a PARALLEL containing | |
6145 | SETs (and possibly other stuff). In a PARALLEL, all the SETs | |
6146 | are important so they all have to be marked RTX_FRAME_RELATED_P. */ | |
6147 | ||
6148 | if (GET_CODE (real) == SET) | |
6149 | { | |
6150 | rtx set = real; | |
6151 | ||
6152 | temp = simplify_rtx (SET_SRC (set)); | |
6153 | if (temp) | |
6154 | SET_SRC (set) = temp; | |
6155 | temp = simplify_rtx (SET_DEST (set)); | |
6156 | if (temp) | |
6157 | SET_DEST (set) = temp; | |
6158 | if (GET_CODE (SET_DEST (set)) == MEM) | |
38c1f2d7 | 6159 | { |
9ebbca7d GK |
6160 | temp = simplify_rtx (XEXP (SET_DEST (set), 0)); |
6161 | if (temp) | |
6162 | XEXP (SET_DEST (set), 0) = temp; | |
38c1f2d7 | 6163 | } |
38c1f2d7 | 6164 | } |
9ebbca7d GK |
6165 | else if (GET_CODE (real) == PARALLEL) |
6166 | { | |
6167 | int i; | |
6168 | for (i = 0; i < XVECLEN (real, 0); i++) | |
6169 | if (GET_CODE (XVECEXP (real, 0, i)) == SET) | |
6170 | { | |
6171 | rtx set = XVECEXP (real, 0, i); | |
6172 | ||
6173 | temp = simplify_rtx (SET_SRC (set)); | |
6174 | if (temp) | |
6175 | SET_SRC (set) = temp; | |
6176 | temp = simplify_rtx (SET_DEST (set)); | |
6177 | if (temp) | |
6178 | SET_DEST (set) = temp; | |
6179 | if (GET_CODE (SET_DEST (set)) == MEM) | |
6180 | { | |
6181 | temp = simplify_rtx (XEXP (SET_DEST (set), 0)); | |
6182 | if (temp) | |
6183 | XEXP (SET_DEST (set), 0) = temp; | |
6184 | } | |
6185 | RTX_FRAME_RELATED_P (set) = 1; | |
6186 | } | |
6187 | } | |
6188 | else | |
a4f6c312 | 6189 | abort (); |
9ebbca7d GK |
6190 | |
6191 | if (reg2 != NULL_RTX) | |
6192 | real = replace_rtx (real, reg2, rreg); | |
6193 | ||
6194 | RTX_FRAME_RELATED_P (insn) = 1; | |
6195 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, | |
6196 | real, | |
6197 | REG_NOTES (insn)); | |
38c1f2d7 MM |
6198 | } |
6199 | ||
9ebbca7d GK |
6200 | /* Emit function prologue as insns. */ |
6201 | ||
9878760c | 6202 | void |
83720594 | 6203 | rs6000_emit_prologue () |
9878760c | 6204 | { |
4697a36c | 6205 | rs6000_stack_t *info = rs6000_stack_info (); |
9ebbca7d GK |
6206 | enum machine_mode reg_mode = TARGET_POWERPC64 ? DImode : SImode; |
6207 | int reg_size = TARGET_POWERPC64 ? 8 : 4; | |
6208 | rtx sp_reg_rtx = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM); | |
6209 | rtx frame_ptr_rtx = gen_rtx_REG (Pmode, 12); | |
6210 | rtx frame_reg_rtx = sp_reg_rtx; | |
6211 | rtx cr_save_rtx = NULL; | |
6212 | rtx insn; | |
6213 | int saving_FPRs_inline; | |
6214 | int using_store_multiple; | |
6215 | HOST_WIDE_INT sp_offset = 0; | |
6216 | ||
6217 | using_store_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64 | |
6218 | && info->first_gp_reg_save < 31); | |
6219 | saving_FPRs_inline = (info->first_fp_reg_save == 64 | |
6220 | || FP_SAVE_INLINE (info->first_fp_reg_save)); | |
6221 | ||
6222 | /* For V.4, update stack before we do any saving and set back pointer. */ | |
6223 | if (info->push_p && (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS)) | |
6224 | { | |
6225 | if (info->total_size < 32767) | |
6226 | sp_offset = info->total_size; | |
6227 | else | |
6228 | frame_reg_rtx = frame_ptr_rtx; | |
6229 | rs6000_emit_allocate_stack (info->total_size, | |
6230 | (frame_reg_rtx != sp_reg_rtx | |
6231 | && (info->cr_save_p | |
6232 | || info->lr_save_p | |
6233 | || info->first_fp_reg_save < 64 | |
6234 | || info->first_gp_reg_save < 32 | |
6235 | ))); | |
6236 | if (frame_reg_rtx != sp_reg_rtx) | |
6237 | rs6000_emit_stack_tie (); | |
6238 | } | |
6239 | ||
6240 | /* If we use the link register, get it into r0. */ | |
6241 | if (info->lr_save_p) | |
71f123ca | 6242 | emit_move_insn (gen_rtx_REG (Pmode, 0), |
9ebbca7d GK |
6243 | gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)); |
6244 | ||
6245 | /* If we need to save CR, put it into r12. */ | |
6246 | if (info->cr_save_p && frame_reg_rtx != frame_ptr_rtx) | |
6247 | { | |
6248 | cr_save_rtx = gen_rtx_REG (SImode, 12); | |
6249 | emit_insn (gen_movesi_from_cr (cr_save_rtx)); | |
6250 | } | |
6251 | ||
a4f6c312 SS |
6252 | /* Do any required saving of fpr's. If only one or two to save, do |
6253 | it ourselves. Otherwise, call function. */ | |
9ebbca7d GK |
6254 | if (saving_FPRs_inline) |
6255 | { | |
6256 | int i; | |
6257 | for (i = 0; i < 64 - info->first_fp_reg_save; i++) | |
6258 | if ((regs_ever_live[info->first_fp_reg_save+i] | |
6259 | && ! call_used_regs[info->first_fp_reg_save+i])) | |
6260 | { | |
6261 | rtx addr, reg, mem; | |
6262 | reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i); | |
6263 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
6264 | GEN_INT (info->fp_save_offset | |
6265 | + sp_offset | |
a4f6c312 | 6266 | + 8 * i)); |
9ebbca7d | 6267 | mem = gen_rtx_MEM (DFmode, addr); |
ba4828e0 | 6268 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
9ebbca7d GK |
6269 | |
6270 | insn = emit_move_insn (mem, reg); | |
6271 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, | |
6272 | NULL_RTX, NULL_RTX); | |
6273 | } | |
6274 | } | |
6275 | else if (info->first_fp_reg_save != 64) | |
6276 | { | |
6277 | int i; | |
6278 | char rname[30]; | |
520a57c8 | 6279 | const char *alloc_rname; |
9ebbca7d GK |
6280 | rtvec p; |
6281 | p = rtvec_alloc (2 + 64 - info->first_fp_reg_save); | |
6282 | ||
6283 | RTVEC_ELT (p, 0) = gen_rtx_CLOBBER (VOIDmode, | |
6284 | gen_rtx_REG (Pmode, | |
6285 | LINK_REGISTER_REGNUM)); | |
6286 | sprintf (rname, "%s%d%s", SAVE_FP_PREFIX, | |
6287 | info->first_fp_reg_save - 32, SAVE_FP_SUFFIX); | |
a8a05998 | 6288 | alloc_rname = ggc_strdup (rname); |
9ebbca7d GK |
6289 | RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode, |
6290 | gen_rtx_SYMBOL_REF (Pmode, | |
6291 | alloc_rname)); | |
6292 | for (i = 0; i < 64 - info->first_fp_reg_save; i++) | |
6293 | { | |
6294 | rtx addr, reg, mem; | |
6295 | reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i); | |
6296 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
6297 | GEN_INT (info->fp_save_offset | |
6298 | + sp_offset + 8*i)); | |
6299 | mem = gen_rtx_MEM (DFmode, addr); | |
ba4828e0 | 6300 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
9ebbca7d GK |
6301 | |
6302 | RTVEC_ELT (p, i + 2) = gen_rtx_SET (VOIDmode, mem, reg); | |
6303 | } | |
6304 | insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p)); | |
6305 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, | |
6306 | NULL_RTX, NULL_RTX); | |
6307 | } | |
b6c9286a | 6308 | |
9ebbca7d GK |
6309 | /* Save GPRs. This is done as a PARALLEL if we are using |
6310 | the store-multiple instructions. */ | |
6311 | if (using_store_multiple) | |
b6c9286a | 6312 | { |
9ebbca7d GK |
6313 | rtvec p, dwarfp; |
6314 | int i; | |
6315 | p = rtvec_alloc (32 - info->first_gp_reg_save); | |
6316 | dwarfp = rtvec_alloc (32 - info->first_gp_reg_save); | |
6317 | for (i = 0; i < 32 - info->first_gp_reg_save; i++) | |
6318 | { | |
6319 | rtx addr, reg, mem; | |
6320 | reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i); | |
6321 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
6322 | GEN_INT (info->gp_save_offset | |
6323 | + sp_offset | |
6324 | + reg_size * i)); | |
6325 | mem = gen_rtx_MEM (reg_mode, addr); | |
ba4828e0 | 6326 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
9ebbca7d GK |
6327 | |
6328 | RTVEC_ELT (p, i) = gen_rtx_SET (VOIDmode, mem, reg); | |
6329 | } | |
6330 | insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p)); | |
6331 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, | |
6332 | NULL_RTX, NULL_RTX); | |
b6c9286a MM |
6333 | } |
6334 | else | |
6335 | { | |
9ebbca7d GK |
6336 | int i; |
6337 | for (i = 0; i < 32 - info->first_gp_reg_save; i++) | |
6338 | if ((regs_ever_live[info->first_gp_reg_save+i] | |
6339 | && ! call_used_regs[info->first_gp_reg_save+i]) | |
6340 | || (i+info->first_gp_reg_save == PIC_OFFSET_TABLE_REGNUM | |
ee890fe2 SS |
6341 | && (((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) |
6342 | && flag_pic == 1) | |
6343 | || (DEFAULT_ABI == ABI_DARWIN | |
6344 | && flag_pic)))) | |
9ebbca7d GK |
6345 | { |
6346 | rtx addr, reg, mem; | |
6347 | reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i); | |
6348 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
6349 | GEN_INT (info->gp_save_offset | |
6350 | + sp_offset | |
6351 | + reg_size * i)); | |
6352 | mem = gen_rtx_MEM (reg_mode, addr); | |
ba4828e0 | 6353 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
9ebbca7d GK |
6354 | |
6355 | insn = emit_move_insn (mem, reg); | |
6356 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, | |
6357 | NULL_RTX, NULL_RTX); | |
6358 | } | |
6359 | } | |
6360 | ||
83720594 RH |
6361 | /* ??? There's no need to emit actual instructions here, but it's the |
6362 | easiest way to get the frame unwind information emitted. */ | |
6363 | if (current_function_calls_eh_return) | |
6364 | { | |
78e1b90d DE |
6365 | unsigned int i, regno; |
6366 | ||
83720594 RH |
6367 | for (i = 0; ; ++i) |
6368 | { | |
6369 | rtx addr, reg, mem; | |
6370 | ||
6371 | regno = EH_RETURN_DATA_REGNO (i); | |
6372 | if (regno == INVALID_REGNUM) | |
6373 | break; | |
6374 | ||
6375 | reg = gen_rtx_REG (reg_mode, regno); | |
6376 | addr = plus_constant (frame_reg_rtx, | |
78e1b90d DE |
6377 | info->ehrd_offset + sp_offset |
6378 | + reg_size * (int) i); | |
83720594 | 6379 | mem = gen_rtx_MEM (reg_mode, addr); |
ba4828e0 | 6380 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
83720594 RH |
6381 | |
6382 | insn = emit_move_insn (mem, reg); | |
6383 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, | |
6384 | NULL_RTX, NULL_RTX); | |
6385 | } | |
6386 | } | |
6387 | ||
9ebbca7d GK |
6388 | /* Save lr if we used it. */ |
6389 | if (info->lr_save_p) | |
6390 | { | |
6391 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
6392 | GEN_INT (info->lr_save_offset + sp_offset)); | |
6393 | rtx reg = gen_rtx_REG (Pmode, 0); | |
6394 | rtx mem = gen_rtx_MEM (Pmode, addr); | |
6395 | /* This should not be of rs6000_sr_alias_set, because of | |
6396 | __builtin_return_address. */ | |
6397 | ||
6398 | insn = emit_move_insn (mem, reg); | |
6399 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, | |
6400 | reg, gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)); | |
6401 | } | |
6402 | ||
6403 | /* Save CR if we use any that must be preserved. */ | |
6404 | if (info->cr_save_p) | |
6405 | { | |
6406 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
6407 | GEN_INT (info->cr_save_offset + sp_offset)); | |
6408 | rtx mem = gen_rtx_MEM (SImode, addr); | |
ba4828e0 RK |
6409 | |
6410 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
9ebbca7d GK |
6411 | |
6412 | /* If r12 was used to hold the original sp, copy cr into r0 now | |
6413 | that it's free. */ | |
6414 | if (REGNO (frame_reg_rtx) == 12) | |
6415 | { | |
6416 | cr_save_rtx = gen_rtx_REG (SImode, 0); | |
6417 | emit_insn (gen_movesi_from_cr (cr_save_rtx)); | |
6418 | } | |
6419 | insn = emit_move_insn (mem, cr_save_rtx); | |
6420 | ||
6421 | /* Now, there's no way that dwarf2out_frame_debug_expr is going | |
6422 | to understand '(unspec:SI [(reg:CC 68) ...] 19)'. But that's | |
6423 | OK. All we have to do is specify that _one_ condition code | |
6424 | register is saved in this stack slot. The thrower's epilogue | |
a1dc9455 FS |
6425 | will then restore all the call-saved registers. |
6426 | We use CR2_REGNO (70) to be compatible with gcc-2.95 on Linux. */ | |
9ebbca7d | 6427 | rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, |
a1dc9455 | 6428 | cr_save_rtx, gen_rtx_REG (SImode, CR2_REGNO)); |
9ebbca7d GK |
6429 | } |
6430 | ||
6431 | /* Update stack and set back pointer unless this is V.4, | |
6432 | for which it was done previously. */ | |
6433 | if (info->push_p && DEFAULT_ABI != ABI_V4 && DEFAULT_ABI != ABI_SOLARIS) | |
6434 | rs6000_emit_allocate_stack (info->total_size, FALSE); | |
6435 | ||
6436 | /* Set frame pointer, if needed. */ | |
6437 | if (frame_pointer_needed) | |
6438 | { | |
6439 | insn = emit_move_insn (gen_rtx_REG (reg_mode, FRAME_POINTER_REGNUM), | |
6440 | sp_reg_rtx); | |
6441 | RTX_FRAME_RELATED_P (insn) = 1; | |
b6c9286a | 6442 | } |
9878760c | 6443 | |
9ebbca7d GK |
6444 | /* If we are using PIC_OFFSET_TABLE_REGNUM, we need to set it up. */ |
6445 | if ((TARGET_TOC && TARGET_MINIMAL_TOC && get_pool_size () != 0) | |
6446 | || ((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) | |
6447 | && flag_pic == 1 && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])) | |
6448 | { | |
6449 | /* If emit_load_toc_table will use the link register, we need to save | |
6450 | it. We use R11 for this purpose because emit_load_toc_table | |
6451 | can use register 0. This allows us to use a plain 'blr' to return | |
6452 | from the procedure more often. */ | |
d5fa86ba GK |
6453 | int save_LR_around_toc_setup = (TARGET_ELF && flag_pic != 0 |
6454 | && ! info->lr_save_p | |
6455 | && EXIT_BLOCK_PTR->pred != NULL); | |
9ebbca7d GK |
6456 | if (save_LR_around_toc_setup) |
6457 | emit_move_insn (gen_rtx_REG (Pmode, 11), | |
6458 | gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)); | |
6459 | ||
6460 | rs6000_emit_load_toc_table (TRUE); | |
6461 | ||
6462 | if (save_LR_around_toc_setup) | |
6463 | emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM), | |
6464 | gen_rtx_REG (Pmode, 11)); | |
6465 | } | |
ee890fe2 SS |
6466 | |
6467 | if (DEFAULT_ABI == ABI_DARWIN | |
6468 | && flag_pic && current_function_uses_pic_offset_table) | |
6469 | { | |
6470 | rtx dest = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM); | |
6471 | ||
6472 | rs6000_maybe_dead (emit_insn (gen_load_macho_picbase (dest))); | |
6473 | ||
6474 | rs6000_maybe_dead ( | |
6475 | emit_move_insn (gen_rtx_REG (Pmode, PIC_OFFSET_TABLE_REGNUM), | |
6476 | gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM))); | |
6477 | } | |
9ebbca7d GK |
6478 | } |
6479 | ||
9ebbca7d | 6480 | /* Write function prologue. */ |
a4f6c312 | 6481 | |
08c148a8 NB |
6482 | static void |
6483 | rs6000_output_function_prologue (file, size) | |
9ebbca7d | 6484 | FILE *file; |
08c148a8 | 6485 | HOST_WIDE_INT size ATTRIBUTE_UNUSED; |
9ebbca7d GK |
6486 | { |
6487 | rs6000_stack_t *info = rs6000_stack_info (); | |
6488 | ||
4697a36c MM |
6489 | if (TARGET_DEBUG_STACK) |
6490 | debug_stack_info (info); | |
9878760c | 6491 | |
a4f6c312 SS |
6492 | /* Write .extern for any function we will call to save and restore |
6493 | fp values. */ | |
6494 | if (info->first_fp_reg_save < 64 | |
6495 | && !FP_SAVE_INLINE (info->first_fp_reg_save)) | |
4d30c363 | 6496 | fprintf (file, "\t.extern %s%d%s\n\t.extern %s%d%s\n", |
4697a36c | 6497 | SAVE_FP_PREFIX, info->first_fp_reg_save - 32, SAVE_FP_SUFFIX, |
a4f6c312 SS |
6498 | RESTORE_FP_PREFIX, info->first_fp_reg_save - 32, |
6499 | RESTORE_FP_SUFFIX); | |
9878760c | 6500 | |
c764f757 RK |
6501 | /* Write .extern for AIX common mode routines, if needed. */ |
6502 | if (! TARGET_POWER && ! TARGET_POWERPC && ! common_mode_defined) | |
6503 | { | |
f6709c70 JW |
6504 | fputs ("\t.extern __mulh\n", file); |
6505 | fputs ("\t.extern __mull\n", file); | |
6506 | fputs ("\t.extern __divss\n", file); | |
6507 | fputs ("\t.extern __divus\n", file); | |
6508 | fputs ("\t.extern __quoss\n", file); | |
6509 | fputs ("\t.extern __quous\n", file); | |
c764f757 RK |
6510 | common_mode_defined = 1; |
6511 | } | |
9878760c | 6512 | |
9ebbca7d | 6513 | if (! HAVE_prologue) |
979721f8 | 6514 | { |
9ebbca7d GK |
6515 | start_sequence (); |
6516 | ||
a4f6c312 SS |
6517 | /* A NOTE_INSN_DELETED is supposed to be at the start and end of |
6518 | the "toplevel" insn chain. */ | |
9ebbca7d GK |
6519 | emit_note (0, NOTE_INSN_DELETED); |
6520 | rs6000_emit_prologue (); | |
6521 | emit_note (0, NOTE_INSN_DELETED); | |
6522 | ||
6523 | if (TARGET_DEBUG_STACK) | |
a4f6c312 SS |
6524 | debug_rtx_list (get_insns (), 100); |
6525 | final (get_insns (), file, FALSE, FALSE); | |
9ebbca7d | 6526 | end_sequence (); |
979721f8 MM |
6527 | } |
6528 | ||
9ebbca7d GK |
6529 | rs6000_pic_labelno++; |
6530 | } | |
6531 | ||
6532 | /* Emit function epilogue as insns. | |
9878760c | 6533 | |
9ebbca7d GK |
6534 | At present, dwarf2out_frame_debug_expr doesn't understand |
6535 | register restores, so we don't bother setting RTX_FRAME_RELATED_P | |
6536 | anywhere in the epilogue. Most of the insns below would in any case | |
6537 | need special notes to explain where r11 is in relation to the stack. */ | |
9878760c | 6538 | |
9ebbca7d | 6539 | void |
83720594 | 6540 | rs6000_emit_epilogue (sibcall) |
9ebbca7d GK |
6541 | int sibcall; |
6542 | { | |
6543 | rs6000_stack_t *info; | |
6544 | int restoring_FPRs_inline; | |
6545 | int using_load_multiple; | |
6546 | int using_mfcr_multiple; | |
6547 | int use_backchain_to_restore_sp; | |
6548 | int sp_offset = 0; | |
6549 | rtx sp_reg_rtx = gen_rtx_REG (Pmode, 1); | |
6550 | rtx frame_reg_rtx = sp_reg_rtx; | |
6551 | enum machine_mode reg_mode = TARGET_POWERPC64 ? DImode : SImode; | |
6552 | int reg_size = TARGET_POWERPC64 ? 8 : 4; | |
6553 | int i; | |
6554 | ||
6555 | info = rs6000_stack_info (); | |
6556 | using_load_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64 | |
6557 | && info->first_gp_reg_save < 31); | |
6558 | restoring_FPRs_inline = (sibcall | |
83720594 | 6559 | || current_function_calls_eh_return |
9ebbca7d GK |
6560 | || info->first_fp_reg_save == 64 |
6561 | || FP_SAVE_INLINE (info->first_fp_reg_save)); | |
6562 | use_backchain_to_restore_sp = (frame_pointer_needed | |
6563 | || current_function_calls_alloca | |
6564 | || info->total_size > 32767); | |
6565 | using_mfcr_multiple = (rs6000_cpu == PROCESSOR_PPC601 | |
6566 | || rs6000_cpu == PROCESSOR_PPC603 | |
6567 | || rs6000_cpu == PROCESSOR_PPC750 | |
6568 | || optimize_size); | |
6569 | ||
6570 | /* If we have a frame pointer, a call to alloca, or a large stack | |
6571 | frame, restore the old stack pointer using the backchain. Otherwise, | |
6572 | we know what size to update it with. */ | |
6573 | if (use_backchain_to_restore_sp) | |
bacbde18 | 6574 | { |
9ebbca7d GK |
6575 | /* Under V.4, don't reset the stack pointer until after we're done |
6576 | loading the saved registers. */ | |
6577 | if (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) | |
6578 | frame_reg_rtx = gen_rtx_REG (Pmode, 11); | |
4697a36c | 6579 | |
9ebbca7d GK |
6580 | emit_move_insn (frame_reg_rtx, |
6581 | gen_rtx_MEM (Pmode, sp_reg_rtx)); | |
6582 | ||
bacbde18 | 6583 | } |
9ebbca7d | 6584 | else if (info->push_p) |
85638c0d | 6585 | { |
9ebbca7d GK |
6586 | if (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) |
6587 | sp_offset = info->total_size; | |
6588 | else | |
6589 | { | |
6590 | emit_insn (TARGET_32BIT | |
6591 | ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx, | |
6592 | GEN_INT (info->total_size)) | |
6593 | : gen_adddi3 (sp_reg_rtx, sp_reg_rtx, | |
6594 | GEN_INT (info->total_size))); | |
6595 | } | |
85638c0d | 6596 | } |
9ebbca7d GK |
6597 | |
6598 | /* Get the old lr if we saved it. */ | |
6599 | if (info->lr_save_p) | |
b6c9286a | 6600 | { |
9ebbca7d GK |
6601 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, |
6602 | GEN_INT (info->lr_save_offset + sp_offset)); | |
6603 | rtx mem = gen_rtx_MEM (Pmode, addr); | |
ba4828e0 RK |
6604 | |
6605 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
b6c9286a | 6606 | |
9ebbca7d | 6607 | emit_move_insn (gen_rtx_REG (Pmode, 0), mem); |
b6c9286a | 6608 | } |
9ebbca7d GK |
6609 | |
6610 | /* Get the old cr if we saved it. */ | |
6611 | if (info->cr_save_p) | |
6612 | { | |
6613 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
6614 | GEN_INT (info->cr_save_offset + sp_offset)); | |
6615 | rtx mem = gen_rtx_MEM (SImode, addr); | |
ba4828e0 RK |
6616 | |
6617 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
b6c9286a | 6618 | |
9ebbca7d GK |
6619 | emit_move_insn (gen_rtx_REG (SImode, 12), mem); |
6620 | } | |
6621 | ||
6622 | /* Set LR here to try to overlap restores below. */ | |
4697a36c | 6623 | if (info->lr_save_p) |
9ebbca7d GK |
6624 | emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM), |
6625 | gen_rtx_REG (Pmode, 0)); | |
6626 | ||
83720594 RH |
6627 | /* Load exception handler data registers, if needed. */ |
6628 | if (current_function_calls_eh_return) | |
6629 | { | |
78e1b90d DE |
6630 | unsigned int i, regno; |
6631 | ||
83720594 RH |
6632 | for (i = 0; ; ++i) |
6633 | { | |
6634 | rtx addr, mem; | |
6635 | ||
6636 | regno = EH_RETURN_DATA_REGNO (i); | |
6637 | if (regno == INVALID_REGNUM) | |
6638 | break; | |
6639 | ||
6640 | addr = plus_constant (frame_reg_rtx, | |
78e1b90d DE |
6641 | info->ehrd_offset + sp_offset |
6642 | + reg_size * (int) i); | |
83720594 | 6643 | mem = gen_rtx_MEM (reg_mode, addr); |
ba4828e0 | 6644 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
83720594 RH |
6645 | |
6646 | emit_move_insn (gen_rtx_REG (reg_mode, regno), mem); | |
6647 | } | |
6648 | } | |
9ebbca7d GK |
6649 | |
6650 | /* Restore GPRs. This is done as a PARALLEL if we are using | |
6651 | the load-multiple instructions. */ | |
6652 | if (using_load_multiple) | |
979721f8 | 6653 | { |
9ebbca7d GK |
6654 | rtvec p; |
6655 | p = rtvec_alloc (32 - info->first_gp_reg_save); | |
6656 | for (i = 0; i < 32 - info->first_gp_reg_save; i++) | |
979721f8 | 6657 | { |
9ebbca7d GK |
6658 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, |
6659 | GEN_INT (info->gp_save_offset | |
6660 | + sp_offset | |
6661 | + reg_size * i)); | |
6662 | rtx mem = gen_rtx_MEM (reg_mode, addr); | |
ba4828e0 RK |
6663 | |
6664 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
9ebbca7d GK |
6665 | |
6666 | RTVEC_ELT (p, i) = | |
6667 | gen_rtx_SET (VOIDmode, | |
6668 | gen_rtx_REG (reg_mode, info->first_gp_reg_save + i), | |
6669 | mem); | |
979721f8 | 6670 | } |
9ebbca7d | 6671 | emit_insn (gen_rtx_PARALLEL (VOIDmode, p)); |
979721f8 | 6672 | } |
9ebbca7d GK |
6673 | else |
6674 | for (i = 0; i < 32 - info->first_gp_reg_save; i++) | |
6675 | if ((regs_ever_live[info->first_gp_reg_save+i] | |
6676 | && ! call_used_regs[info->first_gp_reg_save+i]) | |
6677 | || (i+info->first_gp_reg_save == PIC_OFFSET_TABLE_REGNUM | |
ee890fe2 SS |
6678 | && (((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) |
6679 | && flag_pic == 1) | |
6680 | || (DEFAULT_ABI == ABI_DARWIN | |
6681 | && flag_pic)))) | |
9ebbca7d GK |
6682 | { |
6683 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
6684 | GEN_INT (info->gp_save_offset | |
6685 | + sp_offset | |
6686 | + reg_size * i)); | |
6687 | rtx mem = gen_rtx_MEM (reg_mode, addr); | |
ba4828e0 RK |
6688 | |
6689 | set_mem_alias_set (mem, rs6000_sr_alias_set); | |
9ebbca7d GK |
6690 | |
6691 | emit_move_insn (gen_rtx_REG (reg_mode, | |
6692 | info->first_gp_reg_save + i), | |
6693 | mem); | |
6694 | } | |
9878760c | 6695 | |
9ebbca7d GK |
6696 | /* Restore fpr's if we need to do it without calling a function. */ |
6697 | if (restoring_FPRs_inline) | |
6698 | for (i = 0; i < 64 - info->first_fp_reg_save; i++) | |
6699 | if ((regs_ever_live[info->first_fp_reg_save+i] | |
6700 | && ! call_used_regs[info->first_fp_reg_save+i])) | |
6701 | { | |
6702 | rtx addr, mem; | |
6703 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
6704 | GEN_INT (info->fp_save_offset | |
6705 | + sp_offset | |
a4f6c312 | 6706 | + 8 * i)); |
9ebbca7d | 6707 | mem = gen_rtx_MEM (DFmode, addr); |
ba4828e0 | 6708 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
9ebbca7d GK |
6709 | |
6710 | emit_move_insn (gen_rtx_REG (DFmode, | |
6711 | info->first_fp_reg_save + i), | |
6712 | mem); | |
6713 | } | |
8d30c4ee | 6714 | |
9ebbca7d GK |
6715 | /* If we saved cr, restore it here. Just those that were used. */ |
6716 | if (info->cr_save_p) | |
979721f8 | 6717 | { |
9ebbca7d | 6718 | rtx r12_rtx = gen_rtx_REG (SImode, 12); |
e35b9579 | 6719 | int count = 0; |
9ebbca7d GK |
6720 | |
6721 | if (using_mfcr_multiple) | |
979721f8 | 6722 | { |
9ebbca7d GK |
6723 | for (i = 0; i < 8; i++) |
6724 | if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i]) | |
e35b9579 | 6725 | count++; |
9ebbca7d | 6726 | if (count == 0) |
e35b9579 GK |
6727 | abort (); |
6728 | } | |
6729 | ||
6730 | if (using_mfcr_multiple && count > 1) | |
6731 | { | |
6732 | rtvec p; | |
6733 | int ndx; | |
9ebbca7d | 6734 | |
e35b9579 | 6735 | p = rtvec_alloc (count); |
9ebbca7d | 6736 | |
e35b9579 | 6737 | ndx = 0; |
9ebbca7d GK |
6738 | for (i = 0; i < 8; i++) |
6739 | if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i]) | |
6740 | { | |
6741 | rtvec r = rtvec_alloc (2); | |
6742 | RTVEC_ELT (r, 0) = r12_rtx; | |
6743 | RTVEC_ELT (r, 1) = GEN_INT (1 << (7-i)); | |
e35b9579 | 6744 | RTVEC_ELT (p, ndx) = |
9ebbca7d GK |
6745 | gen_rtx_SET (VOIDmode, gen_rtx_REG (CCmode, CR0_REGNO+i), |
6746 | gen_rtx_UNSPEC (CCmode, r, 20)); | |
e35b9579 | 6747 | ndx++; |
9ebbca7d GK |
6748 | } |
6749 | emit_insn (gen_rtx_PARALLEL (VOIDmode, p)); | |
e35b9579 GK |
6750 | if (ndx != count) |
6751 | abort (); | |
979721f8 MM |
6752 | } |
6753 | else | |
9ebbca7d GK |
6754 | for (i = 0; i < 8; i++) |
6755 | if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i]) | |
979721f8 | 6756 | { |
9ebbca7d GK |
6757 | emit_insn (gen_movsi_to_cr_one (gen_rtx_REG (CCmode, |
6758 | CR0_REGNO+i), | |
6759 | r12_rtx)); | |
979721f8 | 6760 | } |
979721f8 MM |
6761 | } |
6762 | ||
9ebbca7d GK |
6763 | /* If this is V.4, unwind the stack pointer after all of the loads |
6764 | have been done. We need to emit a block here so that sched | |
6765 | doesn't decide to move the sp change before the register restores | |
6766 | (which may not have any obvious dependency on the stack). This | |
6767 | doesn't hurt performance, because there is no scheduling that can | |
6768 | be done after this point. */ | |
6769 | if (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) | |
b6c9286a | 6770 | { |
9ebbca7d GK |
6771 | if (frame_reg_rtx != sp_reg_rtx) |
6772 | rs6000_emit_stack_tie (); | |
b6c9286a | 6773 | |
9ebbca7d | 6774 | if (use_backchain_to_restore_sp) |
b6c9286a | 6775 | { |
9ebbca7d | 6776 | emit_move_insn (sp_reg_rtx, frame_reg_rtx); |
b6c9286a | 6777 | } |
9ebbca7d | 6778 | else if (sp_offset != 0) |
13f1623b | 6779 | { |
9ebbca7d GK |
6780 | emit_insn (Pmode == SImode |
6781 | ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx, | |
6782 | GEN_INT (sp_offset)) | |
6783 | : gen_adddi3 (sp_reg_rtx, sp_reg_rtx, | |
6784 | GEN_INT (sp_offset))); | |
13f1623b | 6785 | } |
9ebbca7d | 6786 | } |
b6c9286a | 6787 | |
83720594 RH |
6788 | if (current_function_calls_eh_return) |
6789 | { | |
6790 | rtx sa = EH_RETURN_STACKADJ_RTX; | |
6791 | emit_insn (Pmode == SImode | |
6792 | ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx, sa) | |
6793 | : gen_adddi3 (sp_reg_rtx, sp_reg_rtx, sa)); | |
6794 | } | |
6795 | ||
9ebbca7d GK |
6796 | if (!sibcall) |
6797 | { | |
6798 | rtvec p; | |
6799 | if (! restoring_FPRs_inline) | |
6800 | p = rtvec_alloc (3 + 64 - info->first_fp_reg_save); | |
6801 | else | |
6802 | p = rtvec_alloc (2); | |
b6c9286a | 6803 | |
e35b9579 GK |
6804 | RTVEC_ELT (p, 0) = gen_rtx_RETURN (VOIDmode); |
6805 | RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode, | |
9ebbca7d GK |
6806 | gen_rtx_REG (Pmode, |
6807 | LINK_REGISTER_REGNUM)); | |
9ebbca7d GK |
6808 | |
6809 | /* If we have to restore more than two FP registers, branch to the | |
6810 | restore function. It will return to our caller. */ | |
6811 | if (! restoring_FPRs_inline) | |
6812 | { | |
6813 | int i; | |
6814 | char rname[30]; | |
520a57c8 | 6815 | const char *alloc_rname; |
979721f8 | 6816 | |
9ebbca7d GK |
6817 | sprintf (rname, "%s%d%s", RESTORE_FP_PREFIX, |
6818 | info->first_fp_reg_save - 32, RESTORE_FP_SUFFIX); | |
a8a05998 | 6819 | alloc_rname = ggc_strdup (rname); |
9ebbca7d GK |
6820 | RTVEC_ELT (p, 2) = gen_rtx_USE (VOIDmode, |
6821 | gen_rtx_SYMBOL_REF (Pmode, | |
6822 | alloc_rname)); | |
b6c9286a | 6823 | |
9ebbca7d GK |
6824 | for (i = 0; i < 64 - info->first_fp_reg_save; i++) |
6825 | { | |
6826 | rtx addr, mem; | |
6827 | addr = gen_rtx_PLUS (Pmode, sp_reg_rtx, | |
6828 | GEN_INT (info->fp_save_offset + 8*i)); | |
6829 | mem = gen_rtx_MEM (DFmode, addr); | |
ba4828e0 | 6830 | set_mem_alias_set (mem, rs6000_sr_alias_set); |
9ebbca7d GK |
6831 | |
6832 | RTVEC_ELT (p, i+3) = | |
6833 | gen_rtx_SET (VOIDmode, | |
6834 | gen_rtx_REG (DFmode, info->first_fp_reg_save + i), | |
6835 | mem); | |
b6c9286a MM |
6836 | } |
6837 | } | |
9ebbca7d GK |
6838 | |
6839 | emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p)); | |
3daf36a4 | 6840 | } |
9878760c RK |
6841 | } |
6842 | ||
6843 | /* Write function epilogue. */ | |
6844 | ||
08c148a8 NB |
6845 | static void |
6846 | rs6000_output_function_epilogue (file, size) | |
9878760c | 6847 | FILE *file; |
08c148a8 | 6848 | HOST_WIDE_INT size ATTRIBUTE_UNUSED; |
9878760c | 6849 | { |
4697a36c | 6850 | rs6000_stack_t *info = rs6000_stack_info (); |
9878760c | 6851 | |
9ebbca7d | 6852 | if (! HAVE_epilogue) |
9878760c | 6853 | { |
9ebbca7d GK |
6854 | rtx insn = get_last_insn (); |
6855 | /* If the last insn was a BARRIER, we don't have to write anything except | |
6856 | the trace table. */ | |
6857 | if (GET_CODE (insn) == NOTE) | |
6858 | insn = prev_nonnote_insn (insn); | |
6859 | if (insn == 0 || GET_CODE (insn) != BARRIER) | |
4697a36c | 6860 | { |
9ebbca7d GK |
6861 | /* This is slightly ugly, but at least we don't have two |
6862 | copies of the epilogue-emitting code. */ | |
6863 | start_sequence (); | |
6864 | ||
6865 | /* A NOTE_INSN_DELETED is supposed to be at the start | |
6866 | and end of the "toplevel" insn chain. */ | |
6867 | emit_note (0, NOTE_INSN_DELETED); | |
6868 | rs6000_emit_epilogue (FALSE); | |
6869 | emit_note (0, NOTE_INSN_DELETED); | |
6870 | ||
6871 | if (TARGET_DEBUG_STACK) | |
a4f6c312 SS |
6872 | debug_rtx_list (get_insns (), 100); |
6873 | final (get_insns (), file, FALSE, FALSE); | |
9ebbca7d | 6874 | end_sequence (); |
4697a36c | 6875 | } |
9878760c | 6876 | } |
b4ac57ab | 6877 | |
9b30bae2 | 6878 | /* Output a traceback table here. See /usr/include/sys/debug.h for info |
314fc5a9 ILT |
6879 | on its format. |
6880 | ||
6881 | We don't output a traceback table if -finhibit-size-directive was | |
6882 | used. The documentation for -finhibit-size-directive reads | |
6883 | ``don't output a @code{.size} assembler directive, or anything | |
6884 | else that would cause trouble if the function is split in the | |
6885 | middle, and the two halves are placed at locations far apart in | |
6886 | memory.'' The traceback table has this property, since it | |
6887 | includes the offset from the start of the function to the | |
4d30c363 MM |
6888 | traceback table itself. |
6889 | ||
6890 | System V.4 Powerpc's (and the embedded ABI derived from it) use a | |
b6c9286a MM |
6891 | different traceback table. */ |
6892 | if (DEFAULT_ABI == ABI_AIX && ! flag_inhibit_size_directive) | |
9b30bae2 | 6893 | { |
3cce094d | 6894 | const char *fname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0); |
314fc5a9 ILT |
6895 | int fixed_parms, float_parms, parm_info; |
6896 | int i; | |
6897 | ||
b6c9286a MM |
6898 | while (*fname == '.') /* V.4 encodes . in the name */ |
6899 | fname++; | |
6900 | ||
314fc5a9 ILT |
6901 | /* Need label immediately before tbtab, so we can compute its offset |
6902 | from the function start. */ | |
6903 | if (*fname == '*') | |
6904 | ++fname; | |
6905 | ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT"); | |
6906 | ASM_OUTPUT_LABEL (file, fname); | |
6907 | ||
6908 | /* The .tbtab pseudo-op can only be used for the first eight | |
6909 | expressions, since it can't handle the possibly variable | |
6910 | length fields that follow. However, if you omit the optional | |
6911 | fields, the assembler outputs zeros for all optional fields | |
6912 | anyways, giving each variable length field is minimum length | |
6913 | (as defined in sys/debug.h). Thus we can not use the .tbtab | |
6914 | pseudo-op at all. */ | |
6915 | ||
6916 | /* An all-zero word flags the start of the tbtab, for debuggers | |
6917 | that have to find it by searching forward from the entry | |
6918 | point or from the current pc. */ | |
19d2d16f | 6919 | fputs ("\t.long 0\n", file); |
314fc5a9 ILT |
6920 | |
6921 | /* Tbtab format type. Use format type 0. */ | |
19d2d16f | 6922 | fputs ("\t.byte 0,", file); |
314fc5a9 ILT |
6923 | |
6924 | /* Language type. Unfortunately, there doesn't seem to be any | |
6925 | official way to get this info, so we use language_string. C | |
6926 | is 0. C++ is 9. No number defined for Obj-C, so use the | |
9517ead8 | 6927 | value for C for now. There is no official value for Java, |
6f573ff9 JL |
6928 | although IBM appears to be using 13. There is no official value |
6929 | for Chill, so we've choosen 44 pseudo-randomly. */ | |
314fc5a9 | 6930 | if (! strcmp (language_string, "GNU C") |
e2c953b6 | 6931 | || ! strcmp (language_string, "GNU Objective-C")) |
314fc5a9 ILT |
6932 | i = 0; |
6933 | else if (! strcmp (language_string, "GNU F77")) | |
6934 | i = 1; | |
6935 | else if (! strcmp (language_string, "GNU Ada")) | |
6936 | i = 3; | |
8b83775b | 6937 | else if (! strcmp (language_string, "GNU Pascal")) |
314fc5a9 ILT |
6938 | i = 2; |
6939 | else if (! strcmp (language_string, "GNU C++")) | |
6940 | i = 9; | |
9517ead8 AG |
6941 | else if (! strcmp (language_string, "GNU Java")) |
6942 | i = 13; | |
6f573ff9 JL |
6943 | else if (! strcmp (language_string, "GNU CHILL")) |
6944 | i = 44; | |
314fc5a9 ILT |
6945 | else |
6946 | abort (); | |
6947 | fprintf (file, "%d,", i); | |
6948 | ||
6949 | /* 8 single bit fields: global linkage (not set for C extern linkage, | |
6950 | apparently a PL/I convention?), out-of-line epilogue/prologue, offset | |
6951 | from start of procedure stored in tbtab, internal function, function | |
6952 | has controlled storage, function has no toc, function uses fp, | |
6953 | function logs/aborts fp operations. */ | |
6954 | /* Assume that fp operations are used if any fp reg must be saved. */ | |
4697a36c | 6955 | fprintf (file, "%d,", (1 << 5) | ((info->first_fp_reg_save != 64) << 1)); |
314fc5a9 ILT |
6956 | |
6957 | /* 6 bitfields: function is interrupt handler, name present in | |
6958 | proc table, function calls alloca, on condition directives | |
6959 | (controls stack walks, 3 bits), saves condition reg, saves | |
6960 | link reg. */ | |
6961 | /* The `function calls alloca' bit seems to be set whenever reg 31 is | |
6962 | set up as a frame pointer, even when there is no alloca call. */ | |
6963 | fprintf (file, "%d,", | |
6964 | ((1 << 6) | (frame_pointer_needed << 5) | |
4697a36c | 6965 | | (info->cr_save_p << 1) | (info->lr_save_p))); |
314fc5a9 ILT |
6966 | |
6967 | /* 3 bitfields: saves backchain, spare bit, number of fpr saved | |
6968 | (6 bits). */ | |
6969 | fprintf (file, "%d,", | |
4697a36c | 6970 | (info->push_p << 7) | (64 - info->first_fp_reg_save)); |
314fc5a9 ILT |
6971 | |
6972 | /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */ | |
6973 | fprintf (file, "%d,", (32 - first_reg_to_save ())); | |
6974 | ||
6975 | { | |
6976 | /* Compute the parameter info from the function decl argument | |
6977 | list. */ | |
6978 | tree decl; | |
6979 | int next_parm_info_bit; | |
6980 | ||
6981 | next_parm_info_bit = 31; | |
6982 | parm_info = 0; | |
6983 | fixed_parms = 0; | |
6984 | float_parms = 0; | |
6985 | ||
6986 | for (decl = DECL_ARGUMENTS (current_function_decl); | |
6987 | decl; decl = TREE_CHAIN (decl)) | |
6988 | { | |
6989 | rtx parameter = DECL_INCOMING_RTL (decl); | |
6990 | enum machine_mode mode = GET_MODE (parameter); | |
6991 | ||
6992 | if (GET_CODE (parameter) == REG) | |
6993 | { | |
6994 | if (GET_MODE_CLASS (mode) == MODE_FLOAT) | |
6995 | { | |
6996 | int bits; | |
6997 | ||
6998 | float_parms++; | |
6999 | ||
7000 | if (mode == SFmode) | |
7001 | bits = 0x2; | |
7002 | else if (mode == DFmode) | |
7003 | bits = 0x3; | |
7004 | else | |
7005 | abort (); | |
7006 | ||
7007 | /* If only one bit will fit, don't or in this entry. */ | |
7008 | if (next_parm_info_bit > 0) | |
7009 | parm_info |= (bits << (next_parm_info_bit - 1)); | |
7010 | next_parm_info_bit -= 2; | |
7011 | } | |
7012 | else | |
7013 | { | |
7014 | fixed_parms += ((GET_MODE_SIZE (mode) | |
7015 | + (UNITS_PER_WORD - 1)) | |
7016 | / UNITS_PER_WORD); | |
7017 | next_parm_info_bit -= 1; | |
7018 | } | |
7019 | } | |
7020 | } | |
7021 | } | |
7022 | ||
7023 | /* Number of fixed point parameters. */ | |
7024 | /* This is actually the number of words of fixed point parameters; thus | |
7025 | an 8 byte struct counts as 2; and thus the maximum value is 8. */ | |
7026 | fprintf (file, "%d,", fixed_parms); | |
7027 | ||
7028 | /* 2 bitfields: number of floating point parameters (7 bits), parameters | |
7029 | all on stack. */ | |
7030 | /* This is actually the number of fp registers that hold parameters; | |
7031 | and thus the maximum value is 13. */ | |
7032 | /* Set parameters on stack bit if parameters are not in their original | |
7033 | registers, regardless of whether they are on the stack? Xlc | |
7034 | seems to set the bit when not optimizing. */ | |
7035 | fprintf (file, "%d\n", ((float_parms << 1) | (! optimize))); | |
7036 | ||
7037 | /* Optional fields follow. Some are variable length. */ | |
7038 | ||
7039 | /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float, | |
7040 | 11 double float. */ | |
7041 | /* There is an entry for each parameter in a register, in the order that | |
7042 | they occur in the parameter list. Any intervening arguments on the | |
7043 | stack are ignored. If the list overflows a long (max possible length | |
7044 | 34 bits) then completely leave off all elements that don't fit. */ | |
7045 | /* Only emit this long if there was at least one parameter. */ | |
7046 | if (fixed_parms || float_parms) | |
7047 | fprintf (file, "\t.long %d\n", parm_info); | |
7048 | ||
7049 | /* Offset from start of code to tb table. */ | |
19d2d16f | 7050 | fputs ("\t.long ", file); |
314fc5a9 | 7051 | ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT"); |
9ebbca7d | 7052 | #if TARGET_AIX |
314fc5a9 | 7053 | RS6000_OUTPUT_BASENAME (file, fname); |
9ebbca7d GK |
7054 | #else |
7055 | assemble_name (file, fname); | |
7056 | #endif | |
19d2d16f | 7057 | fputs ("-.", file); |
9ebbca7d | 7058 | #if TARGET_AIX |
314fc5a9 | 7059 | RS6000_OUTPUT_BASENAME (file, fname); |
9ebbca7d GK |
7060 | #else |
7061 | assemble_name (file, fname); | |
7062 | #endif | |
19d2d16f | 7063 | putc ('\n', file); |
314fc5a9 ILT |
7064 | |
7065 | /* Interrupt handler mask. */ | |
7066 | /* Omit this long, since we never set the interrupt handler bit | |
7067 | above. */ | |
7068 | ||
7069 | /* Number of CTL (controlled storage) anchors. */ | |
7070 | /* Omit this long, since the has_ctl bit is never set above. */ | |
7071 | ||
7072 | /* Displacement into stack of each CTL anchor. */ | |
7073 | /* Omit this list of longs, because there are no CTL anchors. */ | |
7074 | ||
7075 | /* Length of function name. */ | |
296b8152 | 7076 | fprintf (file, "\t.short %d\n", (int) strlen (fname)); |
314fc5a9 ILT |
7077 | |
7078 | /* Function name. */ | |
7079 | assemble_string (fname, strlen (fname)); | |
7080 | ||
7081 | /* Register for alloca automatic storage; this is always reg 31. | |
7082 | Only emit this if the alloca bit was set above. */ | |
7083 | if (frame_pointer_needed) | |
19d2d16f | 7084 | fputs ("\t.byte 31\n", file); |
9b30bae2 | 7085 | } |
9878760c | 7086 | } |
17167fd8 | 7087 | \f |
a4f6c312 SS |
7088 | /* A C compound statement that outputs the assembler code for a thunk |
7089 | function, used to implement C++ virtual function calls with | |
7090 | multiple inheritance. The thunk acts as a wrapper around a virtual | |
7091 | function, adjusting the implicit object parameter before handing | |
7092 | control off to the real function. | |
7093 | ||
7094 | First, emit code to add the integer DELTA to the location that | |
7095 | contains the incoming first argument. Assume that this argument | |
7096 | contains a pointer, and is the one used to pass the `this' pointer | |
7097 | in C++. This is the incoming argument *before* the function | |
7098 | prologue, e.g. `%o0' on a sparc. The addition must preserve the | |
7099 | values of all other incoming arguments. | |
17167fd8 MM |
7100 | |
7101 | After the addition, emit code to jump to FUNCTION, which is a | |
a4f6c312 SS |
7102 | `FUNCTION_DECL'. This is a direct pure jump, not a call, and does |
7103 | not touch the return address. Hence returning from FUNCTION will | |
7104 | return to whoever called the current `thunk'. | |
17167fd8 | 7105 | |
a4f6c312 SS |
7106 | The effect must be as if FUNCTION had been called directly with the |
7107 | adjusted first argument. This macro is responsible for emitting | |
7108 | all of the code for a thunk function; output_function_prologue() | |
7109 | and output_function_epilogue() are not invoked. | |
17167fd8 | 7110 | |
a4f6c312 SS |
7111 | The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already |
7112 | been extracted from it.) It might possibly be useful on some | |
7113 | targets, but probably not. | |
17167fd8 | 7114 | |
a4f6c312 SS |
7115 | If you do not define this macro, the target-independent code in the |
7116 | C++ frontend will generate a less efficient heavyweight thunk that | |
7117 | calls FUNCTION instead of jumping to it. The generic approach does | |
7118 | not support varargs. */ | |
17167fd8 MM |
7119 | |
7120 | void | |
7121 | output_mi_thunk (file, thunk_fndecl, delta, function) | |
7122 | FILE *file; | |
d330fd93 | 7123 | tree thunk_fndecl ATTRIBUTE_UNUSED; |
17167fd8 MM |
7124 | int delta; |
7125 | tree function; | |
7126 | { | |
a4f6c312 SS |
7127 | const char *this_reg = |
7128 | reg_names[ aggregate_value_p (TREE_TYPE (TREE_TYPE (function))) ? 4 : 3 ]; | |
d330fd93 | 7129 | const char *prefix; |
3cce094d | 7130 | const char *fname; |
d330fd93 | 7131 | const char *r0 = reg_names[0]; |
d330fd93 KG |
7132 | const char *toc = reg_names[2]; |
7133 | const char *schain = reg_names[11]; | |
7134 | const char *r12 = reg_names[12]; | |
17167fd8 MM |
7135 | char buf[512]; |
7136 | static int labelno = 0; | |
7137 | ||
a4f6c312 | 7138 | /* Small constants that can be done by one add instruction. */ |
17167fd8 MM |
7139 | if (delta >= -32768 && delta <= 32767) |
7140 | { | |
22b4a3b0 | 7141 | if (! TARGET_NEW_MNEMONICS) |
17167fd8 MM |
7142 | fprintf (file, "\tcal %s,%d(%s)\n", this_reg, delta, this_reg); |
7143 | else | |
7144 | fprintf (file, "\taddi %s,%s,%d\n", this_reg, this_reg, delta); | |
7145 | } | |
7146 | ||
a4f6c312 | 7147 | /* Large constants that can be done by one addis instruction. */ |
17167fd8 MM |
7148 | else if ((delta & 0xffff) == 0 && num_insns_constant_wide (delta) == 1) |
7149 | asm_fprintf (file, "\t{cau|addis} %s,%s,%d\n", this_reg, this_reg, | |
7150 | delta >> 16); | |
7151 | ||
7152 | /* 32-bit constants that can be done by an add and addis instruction. */ | |
7153 | else if (TARGET_32BIT || num_insns_constant_wide (delta) == 1) | |
7154 | { | |
a4f6c312 SS |
7155 | /* Break into two pieces, propagating the sign bit from the low |
7156 | word to the upper word. */ | |
17167fd8 MM |
7157 | int delta_high = delta >> 16; |
7158 | int delta_low = delta & 0xffff; | |
7159 | if ((delta_low & 0x8000) != 0) | |
7160 | { | |
7161 | delta_high++; | |
7162 | delta_low = (delta_low ^ 0x8000) - 0x8000; /* sign extend */ | |
7163 | } | |
7164 | ||
7165 | asm_fprintf (file, "\t{cau|addis} %s,%s,%d\n", this_reg, this_reg, | |
7166 | delta_high); | |
7167 | ||
22b4a3b0 | 7168 | if (! TARGET_NEW_MNEMONICS) |
17167fd8 MM |
7169 | fprintf (file, "\tcal %s,%d(%s)\n", this_reg, delta_low, this_reg); |
7170 | else | |
7171 | fprintf (file, "\taddi %s,%s,%d\n", this_reg, this_reg, delta_low); | |
7172 | } | |
7173 | ||
7174 | /* 64-bit constants, fixme */ | |
7175 | else | |
7176 | abort (); | |
7177 | ||
7178 | /* Get the prefix in front of the names. */ | |
7179 | switch (DEFAULT_ABI) | |
7180 | { | |
7181 | default: | |
7182 | abort (); | |
7183 | ||
7184 | case ABI_AIX: | |
7185 | prefix = "."; | |
7186 | break; | |
7187 | ||
7188 | case ABI_V4: | |
7189 | case ABI_AIX_NODESC: | |
7190 | case ABI_SOLARIS: | |
7191 | prefix = ""; | |
7192 | break; | |
17167fd8 MM |
7193 | } |
7194 | ||
7195 | /* If the function is compiled in this module, jump to it directly. | |
7196 | Otherwise, load up its address and jump to it. */ | |
7197 | ||
7198 | fname = XSTR (XEXP (DECL_RTL (function), 0), 0); | |
42820a49 | 7199 | |
9ebbca7d | 7200 | if (current_file_function_operand (XEXP (DECL_RTL (function), 0), VOIDmode) |
22b4a3b0 FS |
7201 | && ! lookup_attribute ("longcall", |
7202 | TYPE_ATTRIBUTES (TREE_TYPE (function)))) | |
17167fd8 MM |
7203 | { |
7204 | fprintf (file, "\tb %s", prefix); | |
7205 | assemble_name (file, fname); | |
22b4a3b0 | 7206 | if (DEFAULT_ABI == ABI_V4 && flag_pic) fputs ("@local", file); |
949ea356 | 7207 | putc ('\n', file); |
17167fd8 MM |
7208 | } |
7209 | ||
7210 | else | |
7211 | { | |
7212 | switch (DEFAULT_ABI) | |
7213 | { | |
7214 | default: | |
17167fd8 MM |
7215 | abort (); |
7216 | ||
7217 | case ABI_AIX: | |
7218 | /* Set up a TOC entry for the function. */ | |
7219 | ASM_GENERATE_INTERNAL_LABEL (buf, "Lthunk", labelno); | |
7220 | toc_section (); | |
7221 | ASM_OUTPUT_INTERNAL_LABEL (file, "Lthunk", labelno); | |
7222 | labelno++; | |
7223 | ||
a4f6c312 SS |
7224 | /* Note, MINIMAL_TOC doesn't make sense in the case of a |
7225 | thunk, since there will be only one TOC entry for this | |
7226 | function. */ | |
17167fd8 MM |
7227 | fputs ("\t.tc\t", file); |
7228 | assemble_name (file, buf); | |
7229 | fputs ("[TC],", file); | |
7230 | assemble_name (file, buf); | |
7231 | putc ('\n', file); | |
7232 | text_section (); | |
7233 | asm_fprintf (file, (TARGET_32BIT) ? "\t{l|lwz} %s," : "\tld %s", r12); | |
7234 | assemble_name (file, buf); | |
7235 | asm_fprintf (file, "(%s)\n", reg_names[2]); | |
7236 | asm_fprintf (file, | |
7237 | (TARGET_32BIT) ? "\t{l|lwz} %s,0(%s)\n" : "\tld %s,0(%s)\n", | |
7238 | r0, r12); | |
7239 | ||
7240 | asm_fprintf (file, | |
7241 | (TARGET_32BIT) ? "\t{l|lwz} %s,4(%s)\n" : "\tld %s,8(%s)\n", | |
7242 | toc, r12); | |
7243 | ||
7244 | asm_fprintf (file, "\tmtctr %s\n", r0); | |
7245 | asm_fprintf (file, | |
7246 | (TARGET_32BIT) ? "\t{l|lwz} %s,8(%s)\n" : "\tld %s,16(%s)\n", | |
7247 | schain, r12); | |
7248 | ||
7249 | asm_fprintf (file, "\tbctr\n"); | |
7250 | break; | |
7251 | ||
9ebbca7d GK |
7252 | case ABI_AIX_NODESC: |
7253 | case ABI_SOLARIS: | |
17167fd8 | 7254 | case ABI_V4: |
22b4a3b0 FS |
7255 | fprintf (file, "\tb %s", prefix); |
7256 | assemble_name (file, fname); | |
7257 | if (flag_pic) fputs ("@plt", file); | |
949ea356 | 7258 | putc ('\n', file); |
22b4a3b0 | 7259 | break; |
ee890fe2 SS |
7260 | |
7261 | #if TARGET_MACHO | |
7262 | case ABI_DARWIN: | |
7263 | fprintf (file, "\tb %s", prefix); | |
7264 | if (flag_pic && !machopic_name_defined_p (fname)) | |
7265 | assemble_name (file, machopic_stub_name (fname)); | |
7266 | else | |
7267 | assemble_name (file, fname); | |
7268 | putc ('\n', file); | |
7269 | break; | |
7270 | #endif | |
9ebbca7d GK |
7271 | } |
7272 | } | |
7273 | } | |
42820a49 | 7274 | |
9ebbca7d GK |
7275 | \f |
7276 | /* A quick summary of the various types of 'constant-pool tables' | |
7277 | under PowerPC: | |
7278 | ||
7279 | Target Flags Name One table per | |
7280 | AIX (none) AIX TOC object file | |
7281 | AIX -mfull-toc AIX TOC object file | |
7282 | AIX -mminimal-toc AIX minimal TOC translation unit | |
7283 | SVR4/EABI (none) SVR4 SDATA object file | |
7284 | SVR4/EABI -fpic SVR4 pic object file | |
7285 | SVR4/EABI -fPIC SVR4 PIC translation unit | |
7286 | SVR4/EABI -mrelocatable EABI TOC function | |
7287 | SVR4/EABI -maix AIX TOC object file | |
7288 | SVR4/EABI -maix -mminimal-toc | |
7289 | AIX minimal TOC translation unit | |
7290 | ||
7291 | Name Reg. Set by entries contains: | |
7292 | made by addrs? fp? sum? | |
7293 | ||
7294 | AIX TOC 2 crt0 as Y option option | |
7295 | AIX minimal TOC 30 prolog gcc Y Y option | |
7296 | SVR4 SDATA 13 crt0 gcc N Y N | |
7297 | SVR4 pic 30 prolog ld Y not yet N | |
7298 | SVR4 PIC 30 prolog gcc Y option option | |
7299 | EABI TOC 30 prolog gcc Y option option | |
7300 | ||
7301 | */ | |
7302 | ||
7303 | /* Hash table stuff for keeping track of TOC entries. */ | |
7304 | ||
7305 | struct toc_hash_struct | |
7306 | { | |
7307 | /* `key' will satisfy CONSTANT_P; in fact, it will satisfy | |
7308 | ASM_OUTPUT_SPECIAL_POOL_ENTRY_P. */ | |
7309 | rtx key; | |
a9098fd0 | 7310 | enum machine_mode key_mode; |
9ebbca7d GK |
7311 | int labelno; |
7312 | }; | |
17167fd8 | 7313 | |
9ebbca7d GK |
7314 | static htab_t toc_hash_table; |
7315 | ||
7316 | /* Hash functions for the hash table. */ | |
7317 | ||
7318 | static unsigned | |
7319 | rs6000_hash_constant (k) | |
7320 | rtx k; | |
7321 | { | |
a9098fd0 | 7322 | unsigned result = (GET_CODE (k) << 3) ^ GET_MODE (k); |
9ebbca7d GK |
7323 | const char *format = GET_RTX_FORMAT (GET_CODE (k)); |
7324 | int flen = strlen (format); | |
7325 | int fidx; | |
7326 | ||
7327 | if (GET_CODE (k) == LABEL_REF) | |
832ea3b3 | 7328 | return result * 1231 + X0INT (XEXP (k, 0), 3); |
9ebbca7d GK |
7329 | |
7330 | if (GET_CODE (k) == CONST_DOUBLE) | |
7331 | fidx = 2; | |
7332 | else if (GET_CODE (k) == CODE_LABEL) | |
7333 | fidx = 3; | |
7334 | else | |
7335 | fidx = 0; | |
7336 | ||
7337 | for (; fidx < flen; fidx++) | |
7338 | switch (format[fidx]) | |
7339 | { | |
7340 | case 's': | |
7341 | { | |
7342 | unsigned i, len; | |
7343 | const char *str = XSTR (k, fidx); | |
7344 | len = strlen (str); | |
7345 | result = result * 613 + len; | |
7346 | for (i = 0; i < len; i++) | |
7347 | result = result * 613 + (unsigned) str[i]; | |
17167fd8 MM |
7348 | break; |
7349 | } | |
9ebbca7d GK |
7350 | case 'u': |
7351 | case 'e': | |
7352 | result = result * 1231 + rs6000_hash_constant (XEXP (k, fidx)); | |
7353 | break; | |
7354 | case 'i': | |
7355 | case 'n': | |
7356 | result = result * 613 + (unsigned) XINT (k, fidx); | |
7357 | break; | |
7358 | case 'w': | |
7359 | if (sizeof (unsigned) >= sizeof (HOST_WIDE_INT)) | |
7360 | result = result * 613 + (unsigned) XWINT (k, fidx); | |
7361 | else | |
7362 | { | |
7363 | size_t i; | |
7364 | for (i = 0; i < sizeof(HOST_WIDE_INT)/sizeof(unsigned); i++) | |
7365 | result = result * 613 + (unsigned) (XWINT (k, fidx) | |
7366 | >> CHAR_BIT * i); | |
7367 | } | |
7368 | break; | |
7369 | default: | |
a4f6c312 | 7370 | abort (); |
9ebbca7d GK |
7371 | } |
7372 | return result; | |
7373 | } | |
7374 | ||
7375 | static unsigned | |
7376 | toc_hash_function (hash_entry) | |
7377 | const void * hash_entry; | |
7378 | { | |
a9098fd0 GK |
7379 | const struct toc_hash_struct *thc = |
7380 | (const struct toc_hash_struct *) hash_entry; | |
7381 | return rs6000_hash_constant (thc->key) ^ thc->key_mode; | |
9ebbca7d GK |
7382 | } |
7383 | ||
7384 | /* Compare H1 and H2 for equivalence. */ | |
7385 | ||
7386 | static int | |
7387 | toc_hash_eq (h1, h2) | |
7388 | const void * h1; | |
7389 | const void * h2; | |
7390 | { | |
7391 | rtx r1 = ((const struct toc_hash_struct *) h1)->key; | |
7392 | rtx r2 = ((const struct toc_hash_struct *) h2)->key; | |
7393 | ||
a9098fd0 GK |
7394 | if (((const struct toc_hash_struct *) h1)->key_mode |
7395 | != ((const struct toc_hash_struct *) h2)->key_mode) | |
7396 | return 0; | |
7397 | ||
9ebbca7d GK |
7398 | /* Gotcha: One of these const_doubles will be in memory. |
7399 | The other may be on the constant-pool chain. | |
a4f6c312 | 7400 | So rtx_equal_p will think they are different... */ |
9ebbca7d GK |
7401 | if (r1 == r2) |
7402 | return 1; | |
7403 | if (GET_CODE (r1) != GET_CODE (r2) | |
7404 | || GET_MODE (r1) != GET_MODE (r2)) | |
7405 | return 0; | |
7406 | if (GET_CODE (r1) == CONST_DOUBLE) | |
7407 | { | |
7408 | int format_len = strlen (GET_RTX_FORMAT (CONST_DOUBLE)); | |
7409 | int i; | |
7410 | for (i = 2; i < format_len; i++) | |
7411 | if (XWINT (r1, i) != XWINT (r2, i)) | |
7412 | return 0; | |
7413 | ||
7414 | return 1; | |
17167fd8 | 7415 | } |
9ebbca7d | 7416 | else if (GET_CODE (r1) == LABEL_REF) |
e4a0656f GK |
7417 | return (CODE_LABEL_NUMBER (XEXP (r1, 0)) |
7418 | == CODE_LABEL_NUMBER (XEXP (r2, 0))); | |
9ebbca7d GK |
7419 | else |
7420 | return rtx_equal_p (r1, r2); | |
7421 | } | |
7422 | ||
7423 | /* Mark the hash table-entry HASH_ENTRY. */ | |
7424 | ||
7425 | static int | |
7426 | toc_hash_mark_entry (hash_slot, unused) | |
2eba1afa | 7427 | void ** hash_slot; |
9ebbca7d GK |
7428 | void * unused ATTRIBUTE_UNUSED; |
7429 | { | |
7430 | const struct toc_hash_struct * hash_entry = | |
7431 | *(const struct toc_hash_struct **) hash_slot; | |
7432 | rtx r = hash_entry->key; | |
7433 | ggc_set_mark (hash_entry); | |
a4f6c312 | 7434 | /* For CODE_LABELS, we don't want to drag in the whole insn chain... */ |
9ebbca7d GK |
7435 | if (GET_CODE (r) == LABEL_REF) |
7436 | { | |
7437 | ggc_set_mark (r); | |
7438 | ggc_set_mark (XEXP (r, 0)); | |
7439 | } | |
7440 | else | |
7441 | ggc_mark_rtx (r); | |
7442 | return 1; | |
7443 | } | |
7444 | ||
7445 | /* Mark all the elements of the TOC hash-table *HT. */ | |
7446 | ||
7447 | static void | |
7448 | toc_hash_mark_table (vht) | |
7449 | void *vht; | |
7450 | { | |
7451 | htab_t *ht = vht; | |
7452 | ||
7453 | htab_traverse (*ht, toc_hash_mark_entry, (void *)0); | |
17167fd8 MM |
7454 | } |
7455 | ||
28e510bd MM |
7456 | /* These are the names given by the C++ front-end to vtables, and |
7457 | vtable-like objects. Ideally, this logic should not be here; | |
7458 | instead, there should be some programmatic way of inquiring as | |
7459 | to whether or not an object is a vtable. */ | |
7460 | ||
7461 | #define VTABLE_NAME_P(NAME) \ | |
7462 | (strncmp ("_vt.", name, strlen("_vt.")) == 0 \ | |
7463 | || strncmp ("_ZTV", name, strlen ("_ZTV")) == 0 \ | |
7464 | || strncmp ("_ZTT", name, strlen ("_ZTT")) == 0 \ | |
7465 | || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0) | |
7466 | ||
7467 | void | |
7468 | rs6000_output_symbol_ref (file, x) | |
7469 | FILE *file; | |
7470 | rtx x; | |
7471 | { | |
7472 | /* Currently C++ toc references to vtables can be emitted before it | |
7473 | is decided whether the vtable is public or private. If this is | |
7474 | the case, then the linker will eventually complain that there is | |
7475 | a reference to an unknown section. Thus, for vtables only, | |
7476 | we emit the TOC reference to reference the symbol and not the | |
7477 | section. */ | |
7478 | const char *name = XSTR (x, 0); | |
7479 | ||
7480 | if (VTABLE_NAME_P (name)) | |
7481 | { | |
7482 | RS6000_OUTPUT_BASENAME (file, name); | |
7483 | } | |
7484 | else | |
7485 | assemble_name (file, name); | |
7486 | } | |
7487 | ||
a4f6c312 SS |
7488 | /* Output a TOC entry. We derive the entry name from what is being |
7489 | written. */ | |
9878760c RK |
7490 | |
7491 | void | |
a9098fd0 | 7492 | output_toc (file, x, labelno, mode) |
9878760c RK |
7493 | FILE *file; |
7494 | rtx x; | |
7495 | int labelno; | |
a9098fd0 | 7496 | enum machine_mode mode; |
9878760c RK |
7497 | { |
7498 | char buf[256]; | |
3cce094d | 7499 | const char *name = buf; |
ec940faa | 7500 | const char *real_name; |
9878760c RK |
7501 | rtx base = x; |
7502 | int offset = 0; | |
7503 | ||
4697a36c MM |
7504 | if (TARGET_NO_TOC) |
7505 | abort (); | |
7506 | ||
9ebbca7d GK |
7507 | /* When the linker won't eliminate them, don't output duplicate |
7508 | TOC entries (this happens on AIX if there is any kind of TOC, | |
1f8f4a0b MM |
7509 | and on SVR4 under -fPIC or -mrelocatable). */ |
7510 | if (TARGET_TOC) | |
9ebbca7d GK |
7511 | { |
7512 | struct toc_hash_struct *h; | |
7513 | void * * found; | |
7514 | ||
7515 | h = ggc_alloc (sizeof (*h)); | |
7516 | h->key = x; | |
a9098fd0 | 7517 | h->key_mode = mode; |
9ebbca7d GK |
7518 | h->labelno = labelno; |
7519 | ||
7520 | found = htab_find_slot (toc_hash_table, h, 1); | |
7521 | if (*found == NULL) | |
7522 | *found = h; | |
7523 | else /* This is indeed a duplicate. | |
7524 | Set this label equal to that label. */ | |
7525 | { | |
7526 | fputs ("\t.set ", file); | |
7527 | ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC"); | |
7528 | fprintf (file, "%d,", labelno); | |
7529 | ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC"); | |
7530 | fprintf (file, "%d\n", ((*(const struct toc_hash_struct **) | |
7531 | found)->labelno)); | |
7532 | return; | |
7533 | } | |
7534 | } | |
7535 | ||
7536 | /* If we're going to put a double constant in the TOC, make sure it's | |
7537 | aligned properly when strict alignment is on. */ | |
ff1720ed RK |
7538 | if (GET_CODE (x) == CONST_DOUBLE |
7539 | && STRICT_ALIGNMENT | |
a9098fd0 | 7540 | && GET_MODE_BITSIZE (mode) >= 64 |
ff1720ed RK |
7541 | && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC)) { |
7542 | ASM_OUTPUT_ALIGN (file, 3); | |
7543 | } | |
7544 | ||
9ebbca7d | 7545 | ASM_OUTPUT_INTERNAL_LABEL (file, "LC", labelno); |
9878760c | 7546 | |
37c37a57 RK |
7547 | /* Handle FP constants specially. Note that if we have a minimal |
7548 | TOC, things we put here aren't actually in the TOC, so we can allow | |
7549 | FP constants. */ | |
a9098fd0 | 7550 | if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode) |
9878760c | 7551 | { |
042259f2 DE |
7552 | REAL_VALUE_TYPE rv; |
7553 | long k[2]; | |
0adc764e | 7554 | |
042259f2 DE |
7555 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); |
7556 | REAL_VALUE_TO_TARGET_DOUBLE (rv, k); | |
31bfaa0b | 7557 | |
13ded975 DE |
7558 | if (TARGET_64BIT) |
7559 | { | |
7560 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 7561 | fputs (DOUBLE_INT_ASM_OP, file); |
13ded975 | 7562 | else |
2bfcf297 DB |
7563 | fprintf (file, "\t.tc FD_%lx_%lx[TC],", k[0], k[1]); |
7564 | fprintf (file, "0x%lx%08lx\n", k[0], k[1]); | |
13ded975 DE |
7565 | return; |
7566 | } | |
1875cc88 | 7567 | else |
13ded975 DE |
7568 | { |
7569 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 7570 | fputs ("\t.long ", file); |
13ded975 | 7571 | else |
2bfcf297 DB |
7572 | fprintf (file, "\t.tc FD_%lx_%lx[TC],", k[0], k[1]); |
7573 | fprintf (file, "0x%lx,0x%lx\n", k[0], k[1]); | |
13ded975 DE |
7574 | return; |
7575 | } | |
9878760c | 7576 | } |
a9098fd0 | 7577 | else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode) |
9878760c | 7578 | { |
042259f2 DE |
7579 | REAL_VALUE_TYPE rv; |
7580 | long l; | |
9878760c | 7581 | |
042259f2 DE |
7582 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); |
7583 | REAL_VALUE_TO_TARGET_SINGLE (rv, l); | |
7584 | ||
31bfaa0b DE |
7585 | if (TARGET_64BIT) |
7586 | { | |
7587 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 7588 | fputs (DOUBLE_INT_ASM_OP, file); |
31bfaa0b | 7589 | else |
2bfcf297 DB |
7590 | fprintf (file, "\t.tc FS_%lx[TC],", l); |
7591 | fprintf (file, "0x%lx00000000\n", l); | |
31bfaa0b DE |
7592 | return; |
7593 | } | |
042259f2 | 7594 | else |
31bfaa0b DE |
7595 | { |
7596 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 7597 | fputs ("\t.long ", file); |
31bfaa0b | 7598 | else |
2bfcf297 DB |
7599 | fprintf (file, "\t.tc FS_%lx[TC],", l); |
7600 | fprintf (file, "0x%lx\n", l); | |
31bfaa0b DE |
7601 | return; |
7602 | } | |
042259f2 | 7603 | } |
f176e826 | 7604 | else if (GET_MODE (x) == VOIDmode |
a9098fd0 | 7605 | && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE)) |
042259f2 | 7606 | { |
e2c953b6 | 7607 | unsigned HOST_WIDE_INT low; |
042259f2 DE |
7608 | HOST_WIDE_INT high; |
7609 | ||
7610 | if (GET_CODE (x) == CONST_DOUBLE) | |
7611 | { | |
7612 | low = CONST_DOUBLE_LOW (x); | |
7613 | high = CONST_DOUBLE_HIGH (x); | |
7614 | } | |
7615 | else | |
7616 | #if HOST_BITS_PER_WIDE_INT == 32 | |
7617 | { | |
7618 | low = INTVAL (x); | |
0858c623 | 7619 | high = (low & 0x80000000) ? ~0 : 0; |
042259f2 DE |
7620 | } |
7621 | #else | |
7622 | { | |
0858c623 | 7623 | low = INTVAL (x) & 0xffffffff; |
042259f2 DE |
7624 | high = (HOST_WIDE_INT) INTVAL (x) >> 32; |
7625 | } | |
7626 | #endif | |
9878760c | 7627 | |
a9098fd0 GK |
7628 | /* TOC entries are always Pmode-sized, but since this |
7629 | is a bigendian machine then if we're putting smaller | |
7630 | integer constants in the TOC we have to pad them. | |
7631 | (This is still a win over putting the constants in | |
7632 | a separate constant pool, because then we'd have | |
02a4ec28 FS |
7633 | to have both a TOC entry _and_ the actual constant.) |
7634 | ||
7635 | For a 32-bit target, CONST_INT values are loaded and shifted | |
7636 | entirely within `low' and can be stored in one TOC entry. */ | |
7637 | ||
7638 | if (TARGET_64BIT && POINTER_SIZE < GET_MODE_BITSIZE (mode)) | |
a9098fd0 | 7639 | abort ();/* It would be easy to make this work, but it doesn't now. */ |
02a4ec28 FS |
7640 | |
7641 | if (POINTER_SIZE > GET_MODE_BITSIZE (mode)) | |
a9098fd0 GK |
7642 | lshift_double (low, high, POINTER_SIZE - GET_MODE_BITSIZE (mode), |
7643 | POINTER_SIZE, &low, &high, 0); | |
7644 | ||
13ded975 DE |
7645 | if (TARGET_64BIT) |
7646 | { | |
7647 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 7648 | fputs (DOUBLE_INT_ASM_OP, file); |
13ded975 | 7649 | else |
2bfcf297 DB |
7650 | fprintf (file, "\t.tc ID_%lx_%lx[TC],", (long)high, (long)low); |
7651 | fprintf (file, "0x%lx%08lx\n", (long) high, (long) low); | |
13ded975 DE |
7652 | return; |
7653 | } | |
1875cc88 | 7654 | else |
13ded975 | 7655 | { |
02a4ec28 FS |
7656 | if (POINTER_SIZE < GET_MODE_BITSIZE (mode)) |
7657 | { | |
7658 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 7659 | fputs ("\t.long ", file); |
02a4ec28 | 7660 | else |
2bfcf297 DB |
7661 | fprintf (file, "\t.tc ID_%lx_%lx[TC],", |
7662 | (long)high, (long)low); | |
7663 | fprintf (file, "0x%lx,0x%lx\n", (long) high, (long) low); | |
02a4ec28 | 7664 | } |
13ded975 | 7665 | else |
02a4ec28 FS |
7666 | { |
7667 | if (TARGET_MINIMAL_TOC) | |
2bfcf297 | 7668 | fputs ("\t.long ", file); |
02a4ec28 | 7669 | else |
2bfcf297 DB |
7670 | fprintf (file, "\t.tc IS_%lx[TC],", (long) low); |
7671 | fprintf (file, "0x%lx\n", (long) low); | |
02a4ec28 | 7672 | } |
13ded975 DE |
7673 | return; |
7674 | } | |
9878760c RK |
7675 | } |
7676 | ||
7677 | if (GET_CODE (x) == CONST) | |
7678 | { | |
2bfcf297 DB |
7679 | if (GET_CODE (XEXP (x, 0)) != PLUS) |
7680 | abort (); | |
7681 | ||
9878760c RK |
7682 | base = XEXP (XEXP (x, 0), 0); |
7683 | offset = INTVAL (XEXP (XEXP (x, 0), 1)); | |
7684 | } | |
7685 | ||
7686 | if (GET_CODE (base) == SYMBOL_REF) | |
7687 | name = XSTR (base, 0); | |
7688 | else if (GET_CODE (base) == LABEL_REF) | |
7689 | ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (XEXP (base, 0))); | |
7690 | else if (GET_CODE (base) == CODE_LABEL) | |
7691 | ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (base)); | |
7692 | else | |
7693 | abort (); | |
7694 | ||
2e4eb9b0 | 7695 | STRIP_NAME_ENCODING (real_name, name); |
1875cc88 | 7696 | if (TARGET_MINIMAL_TOC) |
2bfcf297 | 7697 | fputs (TARGET_32BIT ? "\t.long " : DOUBLE_INT_ASM_OP, file); |
1875cc88 JW |
7698 | else |
7699 | { | |
b6c9286a | 7700 | fprintf (file, "\t.tc %s", real_name); |
9878760c | 7701 | |
1875cc88 JW |
7702 | if (offset < 0) |
7703 | fprintf (file, ".N%d", - offset); | |
7704 | else if (offset) | |
7705 | fprintf (file, ".P%d", offset); | |
9878760c | 7706 | |
19d2d16f | 7707 | fputs ("[TC],", file); |
1875cc88 | 7708 | } |
581bc4de MM |
7709 | |
7710 | /* Currently C++ toc references to vtables can be emitted before it | |
7711 | is decided whether the vtable is public or private. If this is | |
7712 | the case, then the linker will eventually complain that there is | |
7713 | a TOC reference to an unknown section. Thus, for vtables only, | |
7714 | we emit the TOC reference to reference the symbol and not the | |
7715 | section. */ | |
28e510bd | 7716 | if (VTABLE_NAME_P (name)) |
581bc4de | 7717 | { |
89c01f0e | 7718 | RS6000_OUTPUT_BASENAME (file, name); |
581bc4de MM |
7719 | if (offset < 0) |
7720 | fprintf (file, "%d", offset); | |
7721 | else if (offset > 0) | |
7722 | fprintf (file, "+%d", offset); | |
7723 | } | |
7724 | else | |
7725 | output_addr_const (file, x); | |
19d2d16f | 7726 | putc ('\n', file); |
9878760c RK |
7727 | } |
7728 | \f | |
7729 | /* Output an assembler pseudo-op to write an ASCII string of N characters | |
7730 | starting at P to FILE. | |
7731 | ||
7732 | On the RS/6000, we have to do this using the .byte operation and | |
7733 | write out special characters outside the quoted string. | |
7734 | Also, the assembler is broken; very long strings are truncated, | |
a4f6c312 | 7735 | so we must artificially break them up early. */ |
9878760c RK |
7736 | |
7737 | void | |
7738 | output_ascii (file, p, n) | |
7739 | FILE *file; | |
d330fd93 | 7740 | const char *p; |
9878760c RK |
7741 | int n; |
7742 | { | |
7743 | char c; | |
7744 | int i, count_string; | |
d330fd93 KG |
7745 | const char *for_string = "\t.byte \""; |
7746 | const char *for_decimal = "\t.byte "; | |
7747 | const char *to_close = NULL; | |
9878760c RK |
7748 | |
7749 | count_string = 0; | |
7750 | for (i = 0; i < n; i++) | |
7751 | { | |
7752 | c = *p++; | |
7753 | if (c >= ' ' && c < 0177) | |
7754 | { | |
7755 | if (for_string) | |
7756 | fputs (for_string, file); | |
7757 | putc (c, file); | |
7758 | ||
7759 | /* Write two quotes to get one. */ | |
7760 | if (c == '"') | |
7761 | { | |
7762 | putc (c, file); | |
7763 | ++count_string; | |
7764 | } | |
7765 | ||
7766 | for_string = NULL; | |
7767 | for_decimal = "\"\n\t.byte "; | |
7768 | to_close = "\"\n"; | |
7769 | ++count_string; | |
7770 | ||
7771 | if (count_string >= 512) | |
7772 | { | |
7773 | fputs (to_close, file); | |
7774 | ||
7775 | for_string = "\t.byte \""; | |
7776 | for_decimal = "\t.byte "; | |
7777 | to_close = NULL; | |
7778 | count_string = 0; | |
7779 | } | |
7780 | } | |
7781 | else | |
7782 | { | |
7783 | if (for_decimal) | |
7784 | fputs (for_decimal, file); | |
7785 | fprintf (file, "%d", c); | |
7786 | ||
7787 | for_string = "\n\t.byte \""; | |
7788 | for_decimal = ", "; | |
7789 | to_close = "\n"; | |
7790 | count_string = 0; | |
7791 | } | |
7792 | } | |
7793 | ||
7794 | /* Now close the string if we have written one. Then end the line. */ | |
7795 | if (to_close) | |
9ebbca7d | 7796 | fputs (to_close, file); |
9878760c RK |
7797 | } |
7798 | \f | |
7799 | /* Generate a unique section name for FILENAME for a section type | |
7800 | represented by SECTION_DESC. Output goes into BUF. | |
7801 | ||
7802 | SECTION_DESC can be any string, as long as it is different for each | |
7803 | possible section type. | |
7804 | ||
7805 | We name the section in the same manner as xlc. The name begins with an | |
7806 | underscore followed by the filename (after stripping any leading directory | |
11e5fe42 RK |
7807 | names) with the last period replaced by the string SECTION_DESC. If |
7808 | FILENAME does not contain a period, SECTION_DESC is appended to the end of | |
7809 | the name. */ | |
9878760c RK |
7810 | |
7811 | void | |
7812 | rs6000_gen_section_name (buf, filename, section_desc) | |
7813 | char **buf; | |
9ebbca7d GK |
7814 | const char *filename; |
7815 | const char *section_desc; | |
9878760c | 7816 | { |
9ebbca7d | 7817 | const char *q, *after_last_slash, *last_period = 0; |
9878760c RK |
7818 | char *p; |
7819 | int len; | |
9878760c RK |
7820 | |
7821 | after_last_slash = filename; | |
7822 | for (q = filename; *q; q++) | |
11e5fe42 RK |
7823 | { |
7824 | if (*q == '/') | |
7825 | after_last_slash = q + 1; | |
7826 | else if (*q == '.') | |
7827 | last_period = q; | |
7828 | } | |
9878760c | 7829 | |
11e5fe42 | 7830 | len = strlen (after_last_slash) + strlen (section_desc) + 2; |
9878760c RK |
7831 | *buf = (char *) permalloc (len); |
7832 | ||
7833 | p = *buf; | |
7834 | *p++ = '_'; | |
7835 | ||
7836 | for (q = after_last_slash; *q; q++) | |
7837 | { | |
11e5fe42 | 7838 | if (q == last_period) |
9878760c RK |
7839 | { |
7840 | strcpy (p, section_desc); | |
7841 | p += strlen (section_desc); | |
9878760c RK |
7842 | } |
7843 | ||
e9a780ec | 7844 | else if (ISALNUM (*q)) |
9878760c RK |
7845 | *p++ = *q; |
7846 | } | |
7847 | ||
11e5fe42 | 7848 | if (last_period == 0) |
9878760c RK |
7849 | strcpy (p, section_desc); |
7850 | else | |
7851 | *p = '\0'; | |
7852 | } | |
e165f3f0 | 7853 | \f |
a4f6c312 | 7854 | /* Emit profile function. */ |
411707f4 | 7855 | |
411707f4 CC |
7856 | void |
7857 | output_profile_hook (labelno) | |
7858 | int labelno; | |
7859 | { | |
8480e480 CC |
7860 | if (DEFAULT_ABI == ABI_AIX) |
7861 | { | |
7862 | char buf[30]; | |
40501e5f | 7863 | const char *label_name; |
8480e480 | 7864 | rtx fun; |
411707f4 | 7865 | |
8480e480 | 7866 | labelno += 1; |
411707f4 | 7867 | |
8480e480 CC |
7868 | ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno); |
7869 | STRIP_NAME_ENCODING (label_name, ggc_strdup (buf)); | |
7870 | fun = gen_rtx_SYMBOL_REF (Pmode, label_name); | |
411707f4 | 7871 | |
8480e480 CC |
7872 | emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 1, |
7873 | fun, Pmode); | |
7874 | } | |
ee890fe2 SS |
7875 | else if (DEFAULT_ABI == ABI_DARWIN) |
7876 | { | |
d5fa86ba | 7877 | const char *mcount_name = RS6000_MCOUNT; |
ee890fe2 SS |
7878 | int caller_addr_regno = LINK_REGISTER_REGNUM; |
7879 | ||
7880 | /* Be conservative and always set this, at least for now. */ | |
7881 | current_function_uses_pic_offset_table = 1; | |
7882 | ||
7883 | #if TARGET_MACHO | |
7884 | /* For PIC code, set up a stub and collect the caller's address | |
7885 | from r0, which is where the prologue puts it. */ | |
7886 | if (flag_pic) | |
7887 | { | |
7888 | mcount_name = machopic_stub_name (mcount_name); | |
7889 | if (current_function_uses_pic_offset_table) | |
7890 | caller_addr_regno = 0; | |
7891 | } | |
7892 | #endif | |
7893 | emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mcount_name), | |
7894 | 0, VOIDmode, 1, | |
7895 | gen_rtx_REG (Pmode, caller_addr_regno), Pmode); | |
7896 | } | |
411707f4 CC |
7897 | } |
7898 | ||
a4f6c312 | 7899 | /* Write function profiler code. */ |
e165f3f0 RK |
7900 | |
7901 | void | |
7902 | output_function_profiler (file, labelno) | |
7903 | FILE *file; | |
7904 | int labelno; | |
7905 | { | |
3daf36a4 | 7906 | char buf[100]; |
e165f3f0 | 7907 | |
3daf36a4 | 7908 | ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno); |
38c1f2d7 | 7909 | switch (DEFAULT_ABI) |
3daf36a4 | 7910 | { |
38c1f2d7 MM |
7911 | default: |
7912 | abort (); | |
7913 | ||
7914 | case ABI_V4: | |
7915 | case ABI_SOLARIS: | |
7916 | case ABI_AIX_NODESC: | |
7917 | fprintf (file, "\tmflr %s\n", reg_names[0]); | |
7918 | if (flag_pic == 1) | |
7919 | { | |
dfdfa60f DE |
7920 | fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file); |
7921 | asm_fprintf (file, "\t{st|stw} %s,4(%s)\n", | |
7922 | reg_names[0], reg_names[1]); | |
17167fd8 | 7923 | asm_fprintf (file, "\tmflr %s\n", reg_names[12]); |
dfdfa60f | 7924 | asm_fprintf (file, "\t{l|lwz} %s,", reg_names[0]); |
38c1f2d7 | 7925 | assemble_name (file, buf); |
17167fd8 | 7926 | asm_fprintf (file, "@got(%s)\n", reg_names[12]); |
38c1f2d7 | 7927 | } |
9ebbca7d | 7928 | else if (flag_pic > 1) |
38c1f2d7 | 7929 | { |
dfdfa60f DE |
7930 | asm_fprintf (file, "\t{st|stw} %s,4(%s)\n", |
7931 | reg_names[0], reg_names[1]); | |
9ebbca7d GK |
7932 | /* Now, we need to get the address of the label. */ |
7933 | fputs ("\tbl 1f\n\t.long ", file); | |
034e84c4 | 7934 | assemble_name (file, buf); |
9ebbca7d GK |
7935 | fputs ("-.\n1:", file); |
7936 | asm_fprintf (file, "\tmflr %s\n", reg_names[11]); | |
7937 | asm_fprintf (file, "\t{l|lwz} %s,0(%s)\n", | |
7938 | reg_names[0], reg_names[11]); | |
7939 | asm_fprintf (file, "\t{cax|add} %s,%s,%s\n", | |
7940 | reg_names[0], reg_names[0], reg_names[11]); | |
38c1f2d7 | 7941 | } |
38c1f2d7 MM |
7942 | else |
7943 | { | |
17167fd8 | 7944 | asm_fprintf (file, "\t{liu|lis} %s,", reg_names[12]); |
38c1f2d7 | 7945 | assemble_name (file, buf); |
dfdfa60f | 7946 | fputs ("@ha\n", file); |
b5253831 DE |
7947 | asm_fprintf (file, "\t{st|stw} %s,4(%s)\n", |
7948 | reg_names[0], reg_names[1]); | |
a260abc9 | 7949 | asm_fprintf (file, "\t{cal|la} %s,", reg_names[0]); |
38c1f2d7 | 7950 | assemble_name (file, buf); |
17167fd8 | 7951 | asm_fprintf (file, "@l(%s)\n", reg_names[12]); |
38c1f2d7 MM |
7952 | } |
7953 | ||
b5253831 DE |
7954 | if (current_function_needs_context) |
7955 | asm_fprintf (file, "\tmr %s,%s\n", | |
7956 | reg_names[30], reg_names[STATIC_CHAIN_REGNUM]); | |
38c1f2d7 | 7957 | fprintf (file, "\tbl %s\n", RS6000_MCOUNT); |
b5253831 DE |
7958 | if (current_function_needs_context) |
7959 | asm_fprintf (file, "\tmr %s,%s\n", | |
7960 | reg_names[STATIC_CHAIN_REGNUM], reg_names[30]); | |
38c1f2d7 MM |
7961 | break; |
7962 | ||
7963 | case ABI_AIX: | |
ee890fe2 | 7964 | case ABI_DARWIN: |
a4f6c312 | 7965 | /* Don't do anything, done in output_profile_hook (). */ |
38c1f2d7 | 7966 | break; |
411707f4 | 7967 | |
38c1f2d7 | 7968 | } |
e165f3f0 | 7969 | } |
a251ffd0 TG |
7970 | |
7971 | /* Adjust the cost of a scheduling dependency. Return the new cost of | |
7972 | a dependency LINK or INSN on DEP_INSN. COST is the current cost. */ | |
7973 | ||
c237e94a | 7974 | static int |
a06faf84 | 7975 | rs6000_adjust_cost (insn, link, dep_insn, cost) |
a251ffd0 TG |
7976 | rtx insn; |
7977 | rtx link; | |
296b8152 | 7978 | rtx dep_insn ATTRIBUTE_UNUSED; |
a251ffd0 TG |
7979 | int cost; |
7980 | { | |
7981 | if (! recog_memoized (insn)) | |
7982 | return 0; | |
7983 | ||
7984 | if (REG_NOTE_KIND (link) != 0) | |
7985 | return 0; | |
7986 | ||
7987 | if (REG_NOTE_KIND (link) == 0) | |
7988 | { | |
ed947a96 DJ |
7989 | /* Data dependency; DEP_INSN writes a register that INSN reads |
7990 | some cycles later. */ | |
7991 | switch (get_attr_type (insn)) | |
7992 | { | |
7993 | case TYPE_JMPREG: | |
7994 | /* Tell the first scheduling pass about the latency between | |
7995 | a mtctr and bctr (and mtlr and br/blr). The first | |
7996 | scheduling pass will not know about this latency since | |
7997 | the mtctr instruction, which has the latency associated | |
7998 | to it, will be generated by reload. */ | |
7999 | return TARGET_POWER ? 5 : 4; | |
8000 | case TYPE_BRANCH: | |
8001 | /* Leave some extra cycles between a compare and its | |
8002 | dependent branch, to inhibit expensive mispredicts. */ | |
8003 | if ((rs6000_cpu_attr == CPU_PPC750 | |
8004 | || rs6000_cpu_attr == CPU_PPC7400 | |
8005 | || rs6000_cpu_attr == CPU_PPC7450) | |
8006 | && recog_memoized (dep_insn) | |
8007 | && (INSN_CODE (dep_insn) >= 0) | |
8008 | && (get_attr_type (dep_insn) == TYPE_COMPARE | |
8009 | || get_attr_type (dep_insn) == TYPE_DELAYED_COMPARE | |
8010 | || get_attr_type (dep_insn) == TYPE_FPCOMPARE | |
8011 | || get_attr_type (dep_insn) == TYPE_CR_LOGICAL)) | |
8012 | return cost + 2; | |
8013 | default: | |
8014 | break; | |
8015 | } | |
a251ffd0 TG |
8016 | /* Fall out to return default cost. */ |
8017 | } | |
8018 | ||
8019 | return cost; | |
8020 | } | |
b6c9286a | 8021 | |
a4f6c312 SS |
8022 | /* A C statement (sans semicolon) to update the integer scheduling |
8023 | priority INSN_PRIORITY (INSN). Reduce the priority to execute the | |
8024 | INSN earlier, increase the priority to execute INSN later. Do not | |
8025 | define this macro if you do not need to adjust the scheduling | |
8026 | priorities of insns. */ | |
bef84347 | 8027 | |
c237e94a | 8028 | static int |
bef84347 | 8029 | rs6000_adjust_priority (insn, priority) |
d330fd93 | 8030 | rtx insn ATTRIBUTE_UNUSED; |
bef84347 VM |
8031 | int priority; |
8032 | { | |
a4f6c312 SS |
8033 | /* On machines (like the 750) which have asymmetric integer units, |
8034 | where one integer unit can do multiply and divides and the other | |
8035 | can't, reduce the priority of multiply/divide so it is scheduled | |
8036 | before other integer operations. */ | |
bef84347 VM |
8037 | |
8038 | #if 0 | |
2c3c49de | 8039 | if (! INSN_P (insn)) |
bef84347 VM |
8040 | return priority; |
8041 | ||
8042 | if (GET_CODE (PATTERN (insn)) == USE) | |
8043 | return priority; | |
8044 | ||
8045 | switch (rs6000_cpu_attr) { | |
8046 | case CPU_PPC750: | |
8047 | switch (get_attr_type (insn)) | |
8048 | { | |
8049 | default: | |
8050 | break; | |
8051 | ||
8052 | case TYPE_IMUL: | |
8053 | case TYPE_IDIV: | |
3cb999d8 DE |
8054 | fprintf (stderr, "priority was %#x (%d) before adjustment\n", |
8055 | priority, priority); | |
bef84347 VM |
8056 | if (priority >= 0 && priority < 0x01000000) |
8057 | priority >>= 3; | |
8058 | break; | |
8059 | } | |
8060 | } | |
8061 | #endif | |
8062 | ||
8063 | return priority; | |
8064 | } | |
8065 | ||
a4f6c312 SS |
8066 | /* Return how many instructions the machine can issue per cycle. */ |
8067 | ||
c237e94a ZW |
8068 | static int |
8069 | rs6000_issue_rate () | |
b6c9286a MM |
8070 | { |
8071 | switch (rs6000_cpu_attr) { | |
3cb999d8 DE |
8072 | case CPU_RIOS1: /* ? */ |
8073 | case CPU_RS64A: | |
8074 | case CPU_PPC601: /* ? */ | |
ed947a96 | 8075 | case CPU_PPC7450: |
3cb999d8 | 8076 | return 3; |
b6c9286a | 8077 | case CPU_PPC603: |
bef84347 | 8078 | case CPU_PPC750: |
ed947a96 | 8079 | case CPU_PPC7400: |
bef84347 | 8080 | return 2; |
3cb999d8 | 8081 | case CPU_RIOS2: |
b6c9286a | 8082 | case CPU_PPC604: |
19684119 | 8083 | case CPU_PPC604E: |
b6c9286a | 8084 | case CPU_PPC620: |
3cb999d8 | 8085 | case CPU_PPC630: |
b6c9286a MM |
8086 | return 4; |
8087 | default: | |
8088 | return 1; | |
8089 | } | |
8090 | } | |
8091 | ||
b6c9286a | 8092 | \f |
b6c9286a MM |
8093 | /* Length in units of the trampoline for entering a nested function. */ |
8094 | ||
8095 | int | |
8096 | rs6000_trampoline_size () | |
8097 | { | |
8098 | int ret = 0; | |
8099 | ||
8100 | switch (DEFAULT_ABI) | |
8101 | { | |
8102 | default: | |
8103 | abort (); | |
8104 | ||
8105 | case ABI_AIX: | |
8f802bfb | 8106 | ret = (TARGET_32BIT) ? 12 : 24; |
b6c9286a MM |
8107 | break; |
8108 | ||
8109 | case ABI_V4: | |
c81bebd7 | 8110 | case ABI_SOLARIS: |
b6c9286a | 8111 | case ABI_AIX_NODESC: |
03a7e1a5 | 8112 | ret = (TARGET_32BIT) ? 40 : 48; |
b6c9286a | 8113 | break; |
b6c9286a MM |
8114 | } |
8115 | ||
8116 | return ret; | |
8117 | } | |
8118 | ||
8119 | /* Emit RTL insns to initialize the variable parts of a trampoline. | |
8120 | FNADDR is an RTX for the address of the function's pure code. | |
8121 | CXT is an RTX for the static chain value for the function. */ | |
8122 | ||
8123 | void | |
8124 | rs6000_initialize_trampoline (addr, fnaddr, cxt) | |
8125 | rtx addr; | |
8126 | rtx fnaddr; | |
8127 | rtx cxt; | |
8128 | { | |
ac2a93a1 | 8129 | enum machine_mode pmode = Pmode; |
8bd04c56 MM |
8130 | int regsize = (TARGET_32BIT) ? 4 : 8; |
8131 | rtx ctx_reg = force_reg (pmode, cxt); | |
b6c9286a MM |
8132 | |
8133 | switch (DEFAULT_ABI) | |
8134 | { | |
8135 | default: | |
8136 | abort (); | |
8137 | ||
8bd04c56 | 8138 | /* Macros to shorten the code expansions below. */ |
39403d82 | 8139 | #define MEM_DEREF(addr) gen_rtx_MEM (pmode, memory_address (pmode, addr)) |
c5c76735 JL |
8140 | #define MEM_PLUS(addr,offset) \ |
8141 | gen_rtx_MEM (pmode, memory_address (pmode, plus_constant (addr, offset))) | |
7c59dc5d | 8142 | |
b6c9286a MM |
8143 | /* Under AIX, just build the 3 word function descriptor */ |
8144 | case ABI_AIX: | |
8bd04c56 MM |
8145 | { |
8146 | rtx fn_reg = gen_reg_rtx (pmode); | |
8147 | rtx toc_reg = gen_reg_rtx (pmode); | |
8148 | emit_move_insn (fn_reg, MEM_DEREF (fnaddr)); | |
1cb18e3c | 8149 | emit_move_insn (toc_reg, MEM_PLUS (fnaddr, regsize)); |
8bd04c56 MM |
8150 | emit_move_insn (MEM_DEREF (addr), fn_reg); |
8151 | emit_move_insn (MEM_PLUS (addr, regsize), toc_reg); | |
8152 | emit_move_insn (MEM_PLUS (addr, 2*regsize), ctx_reg); | |
8153 | } | |
b6c9286a MM |
8154 | break; |
8155 | ||
eaf1bcf1 | 8156 | /* Under V.4/eabi, call __trampoline_setup to do the real work. */ |
b6c9286a | 8157 | case ABI_V4: |
c81bebd7 | 8158 | case ABI_SOLARIS: |
b6c9286a | 8159 | case ABI_AIX_NODESC: |
39403d82 | 8160 | emit_library_call (gen_rtx_SYMBOL_REF (SImode, "__trampoline_setup"), |
eaf1bcf1 MM |
8161 | FALSE, VOIDmode, 4, |
8162 | addr, pmode, | |
8163 | GEN_INT (rs6000_trampoline_size ()), SImode, | |
8164 | fnaddr, pmode, | |
8165 | ctx_reg, pmode); | |
b6c9286a | 8166 | break; |
b6c9286a MM |
8167 | } |
8168 | ||
8169 | return; | |
8170 | } | |
7509c759 MM |
8171 | |
8172 | \f | |
91d231cb | 8173 | /* Table of valid machine attributes. */ |
a4f6c312 | 8174 | |
91d231cb | 8175 | const struct attribute_spec rs6000_attribute_table[] = |
7509c759 | 8176 | { |
91d231cb JM |
8177 | /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */ |
8178 | { "longcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute }, | |
8179 | { NULL, 0, 0, false, false, false, NULL } | |
8180 | }; | |
7509c759 | 8181 | |
a4f6c312 SS |
8182 | /* Handle a "longcall" attribute; arguments as in struct |
8183 | attribute_spec.handler. */ | |
8184 | ||
91d231cb JM |
8185 | static tree |
8186 | rs6000_handle_longcall_attribute (node, name, args, flags, no_add_attrs) | |
8187 | tree *node; | |
8188 | tree name; | |
8189 | tree args ATTRIBUTE_UNUSED; | |
8190 | int flags ATTRIBUTE_UNUSED; | |
8191 | bool *no_add_attrs; | |
8192 | { | |
8193 | if (TREE_CODE (*node) != FUNCTION_TYPE | |
8194 | && TREE_CODE (*node) != FIELD_DECL | |
8195 | && TREE_CODE (*node) != TYPE_DECL) | |
8196 | { | |
8197 | warning ("`%s' attribute only applies to functions", | |
8198 | IDENTIFIER_POINTER (name)); | |
8199 | *no_add_attrs = true; | |
8200 | } | |
6a4cee5f | 8201 | |
91d231cb | 8202 | return NULL_TREE; |
7509c759 MM |
8203 | } |
8204 | ||
3cb999d8 DE |
8205 | /* Return a reference suitable for calling a function with the |
8206 | longcall attribute. */ | |
a4f6c312 | 8207 | |
6a4cee5f MM |
8208 | struct rtx_def * |
8209 | rs6000_longcall_ref (call_ref) | |
8210 | rtx call_ref; | |
8211 | { | |
d330fd93 | 8212 | const char *call_name; |
6a4cee5f MM |
8213 | tree node; |
8214 | ||
8215 | if (GET_CODE (call_ref) != SYMBOL_REF) | |
8216 | return call_ref; | |
8217 | ||
8218 | /* System V adds '.' to the internal name, so skip them. */ | |
8219 | call_name = XSTR (call_ref, 0); | |
8220 | if (*call_name == '.') | |
8221 | { | |
8222 | while (*call_name == '.') | |
8223 | call_name++; | |
8224 | ||
8225 | node = get_identifier (call_name); | |
39403d82 | 8226 | call_ref = gen_rtx_SYMBOL_REF (VOIDmode, IDENTIFIER_POINTER (node)); |
6a4cee5f MM |
8227 | } |
8228 | ||
8229 | return force_reg (Pmode, call_ref); | |
8230 | } | |
8231 | ||
7509c759 MM |
8232 | \f |
8233 | /* A C statement or statements to switch to the appropriate section | |
8234 | for output of RTX in mode MODE. You can assume that RTX is some | |
8235 | kind of constant in RTL. The argument MODE is redundant except in | |
8236 | the case of a `const_int' rtx. Select the section by calling | |
8237 | `text_section' or one of the alternatives for other sections. | |
8238 | ||
8239 | Do not define this macro if you put all constants in the read-only | |
8240 | data section. */ | |
8241 | ||
8242 | #ifdef USING_SVR4_H | |
8243 | ||
8244 | void | |
8245 | rs6000_select_rtx_section (mode, x) | |
a9098fd0 | 8246 | enum machine_mode mode; |
7509c759 MM |
8247 | rtx x; |
8248 | { | |
a9098fd0 | 8249 | if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode)) |
7509c759 | 8250 | toc_section (); |
7509c759 MM |
8251 | else |
8252 | const_section (); | |
8253 | } | |
8254 | ||
8255 | /* A C statement or statements to switch to the appropriate | |
8256 | section for output of DECL. DECL is either a `VAR_DECL' node | |
8257 | or a constant of some sort. RELOC indicates whether forming | |
8258 | the initial value of DECL requires link-time relocations. */ | |
8259 | ||
8260 | void | |
8261 | rs6000_select_section (decl, reloc) | |
8262 | tree decl; | |
8263 | int reloc; | |
8264 | { | |
8265 | int size = int_size_in_bytes (TREE_TYPE (decl)); | |
63019373 GK |
8266 | int needs_sdata; |
8267 | int readonly; | |
8268 | static void (* const sec_funcs[4]) PARAMS ((void)) = { | |
8269 | &const_section, | |
8270 | &sdata2_section, | |
8271 | &data_section, | |
8272 | &sdata_section | |
8273 | }; | |
8274 | ||
8275 | needs_sdata = (size > 0 | |
8276 | && size <= g_switch_value | |
8277 | && rs6000_sdata != SDATA_NONE | |
8278 | && (rs6000_sdata != SDATA_DATA || TREE_PUBLIC (decl))); | |
7509c759 MM |
8279 | |
8280 | if (TREE_CODE (decl) == STRING_CST) | |
63019373 | 8281 | readonly = ! flag_writable_strings; |
a9098fd0 | 8282 | else if (TREE_CODE (decl) == VAR_DECL) |
63019373 GK |
8283 | readonly = (! (flag_pic && reloc) |
8284 | && TREE_READONLY (decl) | |
8285 | && ! TREE_SIDE_EFFECTS (decl) | |
8286 | && DECL_INITIAL (decl) | |
8287 | && DECL_INITIAL (decl) != error_mark_node | |
8288 | && TREE_CONSTANT (DECL_INITIAL (decl))); | |
7509c759 | 8289 | else |
63019373 GK |
8290 | readonly = 1; |
8291 | if (needs_sdata && rs6000_sdata != SDATA_EABI) | |
8292 | readonly = 0; | |
8293 | ||
8294 | (*sec_funcs[(readonly ? 0 : 2) + (needs_sdata ? 1 : 0)])(); | |
8295 | } | |
8296 | ||
8297 | /* A C statement to build up a unique section name, expressed as a | |
8298 | STRING_CST node, and assign it to DECL_SECTION_NAME (decl). | |
8299 | RELOC indicates whether the initial value of EXP requires | |
8300 | link-time relocations. If you do not define this macro, GCC will use | |
8301 | the symbol name prefixed by `.' as the section name. Note - this | |
8302 | macro can now be called for unitialised data items as well as | |
8303 | initialised data and functions. */ | |
8304 | ||
8305 | void | |
8306 | rs6000_unique_section (decl, reloc) | |
8307 | tree decl; | |
8308 | int reloc; | |
8309 | { | |
8310 | int size = int_size_in_bytes (TREE_TYPE (decl)); | |
8311 | int needs_sdata; | |
8312 | int readonly; | |
8313 | int len; | |
8314 | int sec; | |
8315 | const char *name; | |
8316 | char *string; | |
8317 | const char *prefix; | |
8318 | ||
8319 | static const char *const prefixes[7][2] = | |
8320 | { | |
8321 | { ".text.", ".gnu.linkonce.t." }, | |
8322 | { ".rodata.", ".gnu.linkonce.r." }, | |
8323 | { ".sdata2.", ".gnu.linkonce.s2." }, | |
8324 | { ".data.", ".gnu.linkonce.d." }, | |
8325 | { ".sdata.", ".gnu.linkonce.s." }, | |
8326 | { ".bss.", ".gnu.linkonce.b." }, | |
8327 | { ".sbss.", ".gnu.linkonce.sb." } | |
8328 | }; | |
8329 | ||
8330 | needs_sdata = (TREE_CODE (decl) != FUNCTION_DECL | |
8331 | && size > 0 | |
8332 | && size <= g_switch_value | |
8333 | && rs6000_sdata != SDATA_NONE | |
8334 | && (rs6000_sdata != SDATA_DATA || TREE_PUBLIC (decl))); | |
8335 | ||
8336 | if (TREE_CODE (decl) == STRING_CST) | |
8337 | readonly = ! flag_writable_strings; | |
8338 | else if (TREE_CODE (decl) == VAR_DECL) | |
8339 | readonly = (! (flag_pic && reloc) | |
8340 | && TREE_READONLY (decl) | |
8341 | && ! TREE_SIDE_EFFECTS (decl) | |
8342 | && DECL_INITIAL (decl) | |
8343 | && DECL_INITIAL (decl) != error_mark_node | |
8344 | && TREE_CONSTANT (DECL_INITIAL (decl))); | |
8345 | else | |
8346 | readonly = 1; | |
8347 | if (needs_sdata && rs6000_sdata != SDATA_EABI) | |
8348 | readonly = 0; | |
8349 | ||
8350 | sec = ((TREE_CODE (decl) == FUNCTION_DECL ? 0 : 1) | |
8351 | + (readonly ? 0 : 2) | |
8352 | + (needs_sdata ? 1 : 0) | |
8353 | + (DECL_INITIAL (decl) == 0 | |
8354 | || DECL_INITIAL (decl) == error_mark_node) ? 4 : 0); | |
8355 | ||
e6978109 | 8356 | STRIP_NAME_ENCODING (name, IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl))); |
63019373 GK |
8357 | prefix = prefixes[sec][DECL_ONE_ONLY (decl)]; |
8358 | len = strlen (name) + strlen (prefix); | |
8359 | string = alloca (len + 1); | |
8360 | ||
8361 | sprintf (string, "%s%s", prefix, name); | |
8362 | ||
8363 | DECL_SECTION_NAME (decl) = build_string (len, string); | |
7509c759 | 8364 | } |
d9407988 MM |
8365 | |
8366 | \f | |
d9407988 MM |
8367 | /* If we are referencing a function that is static or is known to be |
8368 | in this file, make the SYMBOL_REF special. We can use this to indicate | |
8369 | that we can branch to this function without emitting a no-op after the | |
9ebbca7d | 8370 | call. For real AIX calling sequences, we also replace the |
d9407988 MM |
8371 | function name with the real name (1 or 2 leading .'s), rather than |
8372 | the function descriptor name. This saves a lot of overriding code | |
a260abc9 | 8373 | to read the prefixes. */ |
d9407988 MM |
8374 | |
8375 | void | |
8376 | rs6000_encode_section_info (decl) | |
8377 | tree decl; | |
8378 | { | |
8379 | if (TREE_CODE (decl) == FUNCTION_DECL) | |
8380 | { | |
8381 | rtx sym_ref = XEXP (DECL_RTL (decl), 0); | |
8f1b829e | 8382 | if ((TREE_ASM_WRITTEN (decl) || ! TREE_PUBLIC (decl)) |
c81fc13e | 8383 | && ! DECL_WEAK (decl)) |
d9407988 MM |
8384 | SYMBOL_REF_FLAG (sym_ref) = 1; |
8385 | ||
9ebbca7d | 8386 | if (DEFAULT_ABI == ABI_AIX) |
d9407988 | 8387 | { |
ff669a6c RH |
8388 | size_t len1 = (DEFAULT_ABI == ABI_AIX) ? 1 : 2; |
8389 | size_t len2 = strlen (XSTR (sym_ref, 0)); | |
520a57c8 | 8390 | char *str = alloca (len1 + len2 + 1); |
ff669a6c RH |
8391 | str[0] = '.'; |
8392 | str[1] = '.'; | |
8393 | memcpy (str + len1, XSTR (sym_ref, 0), len2 + 1); | |
8394 | ||
520a57c8 | 8395 | XSTR (sym_ref, 0) = ggc_alloc_string (str, len1 + len2); |
d9407988 MM |
8396 | } |
8397 | } | |
8398 | else if (rs6000_sdata != SDATA_NONE | |
8399 | && (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) | |
8400 | && TREE_CODE (decl) == VAR_DECL) | |
8401 | { | |
8402 | int size = int_size_in_bytes (TREE_TYPE (decl)); | |
8403 | tree section_name = DECL_SECTION_NAME (decl); | |
d330fd93 | 8404 | const char *name = (char *)0; |
d9407988 MM |
8405 | int len = 0; |
8406 | ||
8407 | if (section_name) | |
8408 | { | |
8409 | if (TREE_CODE (section_name) == STRING_CST) | |
8410 | { | |
8411 | name = TREE_STRING_POINTER (section_name); | |
8412 | len = TREE_STRING_LENGTH (section_name); | |
8413 | } | |
8414 | else | |
8415 | abort (); | |
8416 | } | |
8417 | ||
8418 | if ((size > 0 && size <= g_switch_value) | |
8419 | || (name | |
5f59ecb7 | 8420 | && ((len == sizeof (".sdata") - 1 |
3cb999d8 | 8421 | && strcmp (name, ".sdata") == 0) |
5f59ecb7 | 8422 | || (len == sizeof (".sdata2") - 1 |
3cb999d8 | 8423 | && strcmp (name, ".sdata2") == 0) |
5f59ecb7 | 8424 | || (len == sizeof (".sbss") - 1 |
3cb999d8 | 8425 | && strcmp (name, ".sbss") == 0) |
5f59ecb7 | 8426 | || (len == sizeof (".sbss2") - 1 |
3cb999d8 | 8427 | && strcmp (name, ".sbss2") == 0) |
5f59ecb7 | 8428 | || (len == sizeof (".PPC.EMB.sdata0") - 1 |
3cb999d8 | 8429 | && strcmp (name, ".PPC.EMB.sdata0") == 0) |
5f59ecb7 | 8430 | || (len == sizeof (".PPC.EMB.sbss0") - 1 |
3cb999d8 | 8431 | && strcmp (name, ".PPC.EMB.sbss0") == 0)))) |
d9407988 MM |
8432 | { |
8433 | rtx sym_ref = XEXP (DECL_RTL (decl), 0); | |
ff669a6c | 8434 | size_t len = strlen (XSTR (sym_ref, 0)); |
88c1e412 | 8435 | char *str = alloca (len + 2); |
ff669a6c | 8436 | |
ff669a6c RH |
8437 | str[0] = '@'; |
8438 | memcpy (str + 1, XSTR (sym_ref, 0), len + 1); | |
88c1e412 | 8439 | XSTR (sym_ref, 0) = ggc_alloc_string (str, len + 1); |
d9407988 MM |
8440 | } |
8441 | } | |
8442 | } | |
8443 | ||
7509c759 | 8444 | #endif /* USING_SVR4_H */ |
000034eb | 8445 | |
a6c2a102 | 8446 | \f |
000034eb | 8447 | /* Return a REG that occurs in ADDR with coefficient 1. |
02441cd6 JL |
8448 | ADDR can be effectively incremented by incrementing REG. |
8449 | ||
8450 | r0 is special and we must not select it as an address | |
8451 | register by this routine since our caller will try to | |
8452 | increment the returned register via an "la" instruction. */ | |
000034eb DE |
8453 | |
8454 | struct rtx_def * | |
8455 | find_addr_reg (addr) | |
8456 | rtx addr; | |
8457 | { | |
8458 | while (GET_CODE (addr) == PLUS) | |
8459 | { | |
02441cd6 JL |
8460 | if (GET_CODE (XEXP (addr, 0)) == REG |
8461 | && REGNO (XEXP (addr, 0)) != 0) | |
000034eb | 8462 | addr = XEXP (addr, 0); |
02441cd6 JL |
8463 | else if (GET_CODE (XEXP (addr, 1)) == REG |
8464 | && REGNO (XEXP (addr, 1)) != 0) | |
000034eb DE |
8465 | addr = XEXP (addr, 1); |
8466 | else if (CONSTANT_P (XEXP (addr, 0))) | |
8467 | addr = XEXP (addr, 1); | |
8468 | else if (CONSTANT_P (XEXP (addr, 1))) | |
8469 | addr = XEXP (addr, 0); | |
8470 | else | |
8471 | abort (); | |
8472 | } | |
02441cd6 | 8473 | if (GET_CODE (addr) == REG && REGNO (addr) != 0) |
000034eb DE |
8474 | return addr; |
8475 | abort (); | |
8476 | } | |
8477 | ||
a6c2a102 DE |
8478 | void |
8479 | rs6000_fatal_bad_address (op) | |
8480 | rtx op; | |
8481 | { | |
8482 | fatal_insn ("bad address", op); | |
8483 | } | |
c8023011 MM |
8484 | |
8485 | /* Called to register all of our global variables with the garbage | |
8486 | collector. */ | |
8487 | ||
8488 | static void | |
8489 | rs6000_add_gc_roots () | |
8490 | { | |
8491 | ggc_add_rtx_root (&rs6000_compare_op0, 1); | |
8492 | ggc_add_rtx_root (&rs6000_compare_op1, 1); | |
9ebbca7d GK |
8493 | |
8494 | toc_hash_table = htab_create (1021, toc_hash_function, toc_hash_eq, NULL); | |
8495 | ggc_add_root (&toc_hash_table, 1, sizeof (toc_hash_table), | |
8496 | toc_hash_mark_table); | |
ee890fe2 SS |
8497 | |
8498 | #if TARGET_MACHO | |
8499 | machopic_add_gc_roots (); | |
8500 | #endif | |
8501 | } | |
8502 | ||
8503 | #if TARGET_MACHO | |
8504 | ||
8505 | #if 0 | |
8506 | /* Returns 1 if OP is either a symbol reference or a sum of a symbol | |
8507 | reference and a constant. */ | |
8508 | ||
8509 | int | |
8510 | symbolic_operand (op) | |
592696dd | 8511 | rtx op; |
ee890fe2 SS |
8512 | { |
8513 | switch (GET_CODE (op)) | |
8514 | { | |
8515 | case SYMBOL_REF: | |
8516 | case LABEL_REF: | |
8517 | return 1; | |
8518 | case CONST: | |
8519 | op = XEXP (op, 0); | |
8520 | return (GET_CODE (op) == SYMBOL_REF || | |
8521 | (GET_CODE (XEXP (op, 0)) == SYMBOL_REF | |
8522 | || GET_CODE (XEXP (op, 0)) == LABEL_REF) | |
8523 | && GET_CODE (XEXP (op, 1)) == CONST_INT); | |
8524 | default: | |
8525 | return 0; | |
8526 | } | |
c8023011 | 8527 | } |
ee890fe2 SS |
8528 | #endif |
8529 | ||
8530 | #ifdef RS6000_LONG_BRANCH | |
8531 | ||
8532 | static tree stub_list = 0; | |
8533 | ||
8534 | /* ADD_COMPILER_STUB adds the compiler generated stub for handling | |
8535 | procedure calls to the linked list. */ | |
8536 | ||
8537 | void | |
8538 | add_compiler_stub (label_name, function_name, line_number) | |
8539 | tree label_name; | |
8540 | tree function_name; | |
8541 | int line_number; | |
8542 | { | |
8543 | tree stub = build_tree_list (function_name, label_name); | |
8544 | TREE_TYPE (stub) = build_int_2 (line_number, 0); | |
8545 | TREE_CHAIN (stub) = stub_list; | |
8546 | stub_list = stub; | |
8547 | } | |
8548 | ||
8549 | #define STUB_LABEL_NAME(STUB) TREE_VALUE (STUB) | |
8550 | #define STUB_FUNCTION_NAME(STUB) TREE_PURPOSE (STUB) | |
8551 | #define STUB_LINE_NUMBER(STUB) TREE_INT_CST_LOW (TREE_TYPE (STUB)) | |
8552 | ||
a4f6c312 SS |
8553 | /* OUTPUT_COMPILER_STUB outputs the compiler generated stub for |
8554 | handling procedure calls from the linked list and initializes the | |
8555 | linked list. */ | |
ee890fe2 | 8556 | |
a4f6c312 SS |
8557 | void |
8558 | output_compiler_stub () | |
ee890fe2 SS |
8559 | { |
8560 | char tmp_buf[256]; | |
8561 | char label_buf[256]; | |
8562 | char *label; | |
8563 | tree tmp_stub, stub; | |
8564 | ||
8565 | if (!flag_pic) | |
8566 | for (stub = stub_list; stub; stub = TREE_CHAIN (stub)) | |
8567 | { | |
8568 | fprintf (asm_out_file, | |
8569 | "%s:\n", IDENTIFIER_POINTER(STUB_LABEL_NAME(stub))); | |
8570 | ||
8571 | #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO) | |
8572 | if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG) | |
8573 | fprintf (asm_out_file, "\t.stabd 68,0,%d\n", STUB_LINE_NUMBER(stub)); | |
8574 | #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */ | |
8575 | ||
8576 | if (IDENTIFIER_POINTER (STUB_FUNCTION_NAME (stub))[0] == '*') | |
8577 | strcpy (label_buf, | |
8578 | IDENTIFIER_POINTER (STUB_FUNCTION_NAME (stub))+1); | |
8579 | else | |
8580 | { | |
8581 | label_buf[0] = '_'; | |
8582 | strcpy (label_buf+1, | |
8583 | IDENTIFIER_POINTER (STUB_FUNCTION_NAME (stub))); | |
8584 | } | |
8585 | ||
8586 | strcpy (tmp_buf, "lis r12,hi16("); | |
8587 | strcat (tmp_buf, label_buf); | |
8588 | strcat (tmp_buf, ")\n\tori r12,r12,lo16("); | |
8589 | strcat (tmp_buf, label_buf); | |
8590 | strcat (tmp_buf, ")\n\tmtctr r12\n\tbctr"); | |
8591 | output_asm_insn (tmp_buf, 0); | |
8592 | ||
8593 | #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO) | |
8594 | if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG) | |
8595 | fprintf(asm_out_file, "\t.stabd 68,0,%d\n", STUB_LINE_NUMBER (stub)); | |
8596 | #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */ | |
8597 | } | |
8598 | ||
8599 | stub_list = 0; | |
8600 | } | |
8601 | ||
8602 | /* NO_PREVIOUS_DEF checks in the link list whether the function name is | |
8603 | already there or not. */ | |
8604 | ||
a4f6c312 SS |
8605 | int |
8606 | no_previous_def (function_name) | |
ee890fe2 SS |
8607 | tree function_name; |
8608 | { | |
8609 | tree stub; | |
8610 | for (stub = stub_list; stub; stub = TREE_CHAIN (stub)) | |
8611 | if (function_name == STUB_FUNCTION_NAME (stub)) | |
8612 | return 0; | |
8613 | return 1; | |
8614 | } | |
8615 | ||
8616 | /* GET_PREV_LABEL gets the label name from the previous definition of | |
8617 | the function. */ | |
8618 | ||
a4f6c312 SS |
8619 | tree |
8620 | get_prev_label (function_name) | |
ee890fe2 SS |
8621 | tree function_name; |
8622 | { | |
8623 | tree stub; | |
8624 | for (stub = stub_list; stub; stub = TREE_CHAIN (stub)) | |
8625 | if (function_name == STUB_FUNCTION_NAME (stub)) | |
8626 | return STUB_LABEL_NAME (stub); | |
8627 | return 0; | |
8628 | } | |
8629 | ||
8630 | /* INSN is either a function call or a millicode call. It may have an | |
8631 | unconditional jump in its delay slot. | |
8632 | ||
8633 | CALL_DEST is the routine we are calling. */ | |
8634 | ||
8635 | char * | |
8636 | output_call (insn, call_dest, operand_number) | |
8637 | rtx insn; | |
8638 | rtx call_dest; | |
8639 | int operand_number; | |
8640 | { | |
8641 | static char buf[256]; | |
8642 | if (GET_CODE (call_dest) == SYMBOL_REF && TARGET_LONG_BRANCH && !flag_pic) | |
8643 | { | |
8644 | tree labelname; | |
8645 | tree funname = get_identifier (XSTR (call_dest, 0)); | |
8646 | ||
8647 | if (no_previous_def (funname)) | |
8648 | { | |
8649 | int line_number; | |
8650 | rtx label_rtx = gen_label_rtx (); | |
8651 | char *label_buf, temp_buf[256]; | |
8652 | ASM_GENERATE_INTERNAL_LABEL (temp_buf, "L", | |
8653 | CODE_LABEL_NUMBER (label_rtx)); | |
8654 | label_buf = temp_buf[0] == '*' ? temp_buf + 1 : temp_buf; | |
8655 | labelname = get_identifier (label_buf); | |
8656 | for (; insn && GET_CODE (insn) != NOTE; insn = PREV_INSN (insn)); | |
8657 | if (insn) | |
8658 | line_number = NOTE_LINE_NUMBER (insn); | |
8659 | add_compiler_stub (labelname, funname, line_number); | |
8660 | } | |
8661 | else | |
8662 | labelname = get_prev_label (funname); | |
8663 | ||
8664 | sprintf (buf, "jbsr %%z%d,%.246s", | |
8665 | operand_number, IDENTIFIER_POINTER (labelname)); | |
8666 | return buf; | |
8667 | } | |
8668 | else | |
8669 | { | |
8670 | sprintf (buf, "bl %%z%d", operand_number); | |
8671 | return buf; | |
8672 | } | |
8673 | } | |
8674 | ||
8675 | #endif /* RS6000_LONG_BRANCH */ | |
8676 | ||
8677 | #define GEN_LOCAL_LABEL_FOR_SYMBOL(BUF,SYMBOL,LENGTH,N) \ | |
8678 | do { \ | |
83182544 | 8679 | const char *const symbol_ = (SYMBOL); \ |
ee890fe2 SS |
8680 | char *buffer_ = (BUF); \ |
8681 | if (symbol_[0] == '"') \ | |
8682 | { \ | |
8683 | sprintf(buffer_, "\"L%d$%s", (N), symbol_+1); \ | |
8684 | } \ | |
8685 | else if (name_needs_quotes(symbol_)) \ | |
8686 | { \ | |
8687 | sprintf(buffer_, "\"L%d$%s\"", (N), symbol_); \ | |
8688 | } \ | |
8689 | else \ | |
8690 | { \ | |
8691 | sprintf(buffer_, "L%d$%s", (N), symbol_); \ | |
8692 | } \ | |
8693 | } while (0) | |
8694 | ||
8695 | ||
8696 | /* Generate PIC and indirect symbol stubs. */ | |
8697 | ||
8698 | void | |
8699 | machopic_output_stub (file, symb, stub) | |
8700 | FILE *file; | |
8701 | const char *symb, *stub; | |
8702 | { | |
8703 | unsigned int length; | |
a4f6c312 SS |
8704 | char *symbol_name, *lazy_ptr_name; |
8705 | char *local_label_0; | |
ee890fe2 SS |
8706 | static int label = 0; |
8707 | ||
df56a27f SS |
8708 | /* Lose our funky encoding stuff so it doesn't contaminate the stub. */ |
8709 | STRIP_NAME_ENCODING (symb, symb); | |
8710 | ||
ee890fe2 SS |
8711 | label += 1; |
8712 | ||
ee890fe2 SS |
8713 | length = strlen (symb); |
8714 | symbol_name = alloca (length + 32); | |
8715 | GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length); | |
8716 | ||
8717 | lazy_ptr_name = alloca (length + 32); | |
8718 | GEN_LAZY_PTR_NAME_FOR_SYMBOL (lazy_ptr_name, symb, length); | |
8719 | ||
8720 | local_label_0 = alloca (length + 32); | |
8721 | GEN_LOCAL_LABEL_FOR_SYMBOL (local_label_0, symb, length, 0); | |
8722 | ||
ee890fe2 SS |
8723 | if (flag_pic == 2) |
8724 | machopic_picsymbol_stub_section (); | |
8725 | else | |
8726 | machopic_symbol_stub_section (); | |
8727 | ||
8728 | fprintf (file, "%s:\n", stub); | |
8729 | fprintf (file, "\t.indirect_symbol %s\n", symbol_name); | |
8730 | ||
8731 | if (flag_pic == 2) | |
8732 | { | |
8733 | fprintf (file, "\tmflr r0\n"); | |
8734 | fprintf (file, "\tbcl 20,31,%s\n", local_label_0); | |
8735 | fprintf (file, "%s:\n\tmflr r11\n", local_label_0); | |
8736 | fprintf (file, "\taddis r11,r11,ha16(%s-%s)\n", | |
8737 | lazy_ptr_name, local_label_0); | |
8738 | fprintf (file, "\tmtlr r0\n"); | |
8739 | fprintf (file, "\tlwz r12,lo16(%s-%s)(r11)\n", | |
8740 | lazy_ptr_name, local_label_0); | |
8741 | fprintf (file, "\tmtctr r12\n"); | |
8742 | fprintf (file, "\taddi r11,r11,lo16(%s-%s)\n", | |
8743 | lazy_ptr_name, local_label_0); | |
8744 | fprintf (file, "\tbctr\n"); | |
8745 | } | |
8746 | else | |
8747 | fprintf (file, "non-pure not supported\n"); | |
8748 | ||
8749 | machopic_lazy_symbol_ptr_section (); | |
8750 | fprintf (file, "%s:\n", lazy_ptr_name); | |
8751 | fprintf (file, "\t.indirect_symbol %s\n", symbol_name); | |
8752 | fprintf (file, "\t.long dyld_stub_binding_helper\n"); | |
8753 | } | |
8754 | ||
8755 | /* Legitimize PIC addresses. If the address is already | |
8756 | position-independent, we return ORIG. Newly generated | |
8757 | position-independent addresses go into a reg. This is REG if non | |
8758 | zero, otherwise we allocate register(s) as necessary. */ | |
8759 | ||
8760 | #define SMALL_INT(X) ((unsigned) (INTVAL(X) + 0x4000) < 0x8000) | |
8761 | ||
8762 | rtx | |
8763 | rs6000_machopic_legitimize_pic_address (orig, mode, reg) | |
8764 | rtx orig; | |
8765 | enum machine_mode mode; | |
8766 | rtx reg; | |
8767 | { | |
8768 | rtx base, offset; | |
8769 | ||
8770 | if (reg == NULL && ! reload_in_progress && ! reload_completed) | |
8771 | reg = gen_reg_rtx (Pmode); | |
8772 | ||
8773 | if (GET_CODE (orig) == CONST) | |
8774 | { | |
8775 | if (GET_CODE (XEXP (orig, 0)) == PLUS | |
8776 | && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx) | |
8777 | return orig; | |
8778 | ||
8779 | if (GET_CODE (XEXP (orig, 0)) == PLUS) | |
8780 | { | |
a4f6c312 SS |
8781 | base = |
8782 | rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 0), | |
8783 | Pmode, reg); | |
8784 | offset = | |
8785 | rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 1), | |
8786 | Pmode, reg); | |
ee890fe2 SS |
8787 | } |
8788 | else | |
8789 | abort (); | |
8790 | ||
8791 | if (GET_CODE (offset) == CONST_INT) | |
8792 | { | |
8793 | if (SMALL_INT (offset)) | |
ed8908e7 | 8794 | return plus_constant (base, INTVAL (offset)); |
ee890fe2 SS |
8795 | else if (! reload_in_progress && ! reload_completed) |
8796 | offset = force_reg (Pmode, offset); | |
8797 | else | |
8798 | abort (); | |
8799 | } | |
8800 | return gen_rtx (PLUS, Pmode, base, offset); | |
8801 | } | |
8802 | ||
8803 | /* Fall back on generic machopic code. */ | |
8804 | return machopic_legitimize_pic_address (orig, mode, reg); | |
8805 | } | |
8806 | ||
8807 | /* This is just a placeholder to make linking work without having to | |
8808 | add this to the generic Darwin EXTRA_SECTIONS. If -mcall-aix is | |
8809 | ever needed for Darwin (not too likely!) this would have to get a | |
8810 | real definition. */ | |
8811 | ||
8812 | void | |
8813 | toc_section () | |
8814 | { | |
8815 | } | |
8816 | ||
8817 | #endif /* TARGET_MACHO */ | |
7c262518 RH |
8818 | |
8819 | #if TARGET_ELF | |
8820 | static unsigned int | |
8821 | rs6000_elf_section_type_flags (decl, name, reloc) | |
8822 | tree decl; | |
8823 | const char *name; | |
8824 | int reloc; | |
8825 | { | |
8826 | unsigned int flags = default_section_type_flags (decl, name, reloc); | |
8827 | ||
270fc29b RH |
8828 | if (TARGET_RELOCATABLE) |
8829 | flags |= SECTION_WRITE; | |
7c262518 RH |
8830 | |
8831 | /* Solaris doesn't like @nobits, and gas can handle .sbss without it. */ | |
8832 | flags &= ~SECTION_BSS; | |
d0101753 FS |
8833 | |
8834 | return flags; | |
7c262518 | 8835 | } |
d9f6800d RH |
8836 | |
8837 | /* Record an element in the table of global constructors. SYMBOL is | |
8838 | a SYMBOL_REF of the function to be called; PRIORITY is a number | |
8839 | between 0 and MAX_INIT_PRIORITY. | |
8840 | ||
8841 | This differs from default_named_section_asm_out_constructor in | |
8842 | that we have special handling for -mrelocatable. */ | |
8843 | ||
8844 | static void | |
8845 | rs6000_elf_asm_out_constructor (symbol, priority) | |
8846 | rtx symbol; | |
8847 | int priority; | |
8848 | { | |
8849 | const char *section = ".ctors"; | |
8850 | char buf[16]; | |
8851 | ||
8852 | if (priority != DEFAULT_INIT_PRIORITY) | |
8853 | { | |
8854 | sprintf (buf, ".ctors.%.5u", | |
8855 | /* Invert the numbering so the linker puts us in the proper | |
8856 | order; constructors are run from right to left, and the | |
8857 | linker sorts in increasing order. */ | |
8858 | MAX_INIT_PRIORITY - priority); | |
8859 | section = buf; | |
8860 | } | |
8861 | ||
715bdd29 RH |
8862 | named_section_flags (section, SECTION_WRITE); |
8863 | assemble_align (POINTER_SIZE); | |
d9f6800d RH |
8864 | |
8865 | if (TARGET_RELOCATABLE) | |
8866 | { | |
8867 | fputs ("\t.long (", asm_out_file); | |
8868 | output_addr_const (asm_out_file, symbol); | |
8869 | fputs (")@fixup\n", asm_out_file); | |
8870 | } | |
8871 | else | |
c8af3574 | 8872 | assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1); |
d9f6800d RH |
8873 | } |
8874 | ||
8875 | static void | |
8876 | rs6000_elf_asm_out_destructor (symbol, priority) | |
8877 | rtx symbol; | |
8878 | int priority; | |
8879 | { | |
8880 | const char *section = ".dtors"; | |
8881 | char buf[16]; | |
8882 | ||
8883 | if (priority != DEFAULT_INIT_PRIORITY) | |
8884 | { | |
8885 | sprintf (buf, ".dtors.%.5u", | |
8886 | /* Invert the numbering so the linker puts us in the proper | |
8887 | order; constructors are run from right to left, and the | |
8888 | linker sorts in increasing order. */ | |
8889 | MAX_INIT_PRIORITY - priority); | |
8890 | section = buf; | |
8891 | } | |
8892 | ||
715bdd29 RH |
8893 | named_section_flags (section, SECTION_WRITE); |
8894 | assemble_align (POINTER_SIZE); | |
d9f6800d RH |
8895 | |
8896 | if (TARGET_RELOCATABLE) | |
8897 | { | |
8898 | fputs ("\t.long (", asm_out_file); | |
8899 | output_addr_const (asm_out_file, symbol); | |
8900 | fputs (")@fixup\n", asm_out_file); | |
8901 | } | |
8902 | else | |
c8af3574 | 8903 | assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1); |
d9f6800d | 8904 | } |
7c262518 RH |
8905 | #endif |
8906 | ||
8907 | #ifdef OBJECT_FORMAT_COFF | |
8908 | static void | |
715bdd29 | 8909 | xcoff_asm_named_section (name, flags) |
7c262518 RH |
8910 | const char *name; |
8911 | unsigned int flags ATTRIBUTE_UNUSED; | |
7c262518 RH |
8912 | { |
8913 | fprintf (asm_out_file, "\t.csect %s\n", name); | |
8914 | } | |
8915 | #endif |