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9878760c | 1 | /* Subroutines used for code generation on IBM RS/6000. |
4d30c363 | 2 | Copyright (C) 1991, 1993, 1994, 1995 Free Software Foundation, Inc. |
fab3bcc3 | 3 | Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) |
9878760c RK |
4 | |
5 | This file is part of GNU CC. | |
6 | ||
7 | GNU CC is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2, or (at your option) | |
10 | any later version. | |
11 | ||
12 | GNU CC is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GNU CC; see the file COPYING. If not, write to | |
c15c9075 RK |
19 | the Free Software Foundation, 59 Temple Place - Suite 330, |
20 | Boston, MA 02111-1307, USA. */ | |
9878760c RK |
21 | |
22 | #include <stdio.h> | |
127b0efc | 23 | #include <ctype.h> |
9878760c RK |
24 | #include "config.h" |
25 | #include "rtl.h" | |
26 | #include "regs.h" | |
27 | #include "hard-reg-set.h" | |
28 | #include "real.h" | |
29 | #include "insn-config.h" | |
30 | #include "conditions.h" | |
31 | #include "insn-flags.h" | |
32 | #include "output.h" | |
33 | #include "insn-attr.h" | |
34 | #include "flags.h" | |
35 | #include "recog.h" | |
36 | #include "expr.h" | |
37 | #include "obstack.h" | |
9b30bae2 JW |
38 | #include "tree.h" |
39 | ||
40 | extern char *language_string; | |
5248c961 | 41 | extern int profile_block_flag; |
9878760c RK |
42 | |
43 | #define min(A,B) ((A) < (B) ? (A) : (B)) | |
44 | #define max(A,B) ((A) > (B) ? (A) : (B)) | |
45 | ||
5248c961 RK |
46 | /* Target cpu type */ |
47 | ||
48 | enum processor_type rs6000_cpu; | |
49 | char *rs6000_cpu_string; | |
50 | ||
9878760c RK |
51 | /* Set to non-zero by "fix" operation to indicate that itrunc and |
52 | uitrunc must be defined. */ | |
53 | ||
54 | int rs6000_trunc_used; | |
55 | ||
56 | /* Set to non-zero once they have been defined. */ | |
57 | ||
58 | static int trunc_defined; | |
59 | ||
c764f757 RK |
60 | /* Set to non-zero once AIX common-mode calls have been defined. */ |
61 | static int common_mode_defined; | |
9878760c RK |
62 | /* Save information from a "cmpxx" operation until the branch or scc is |
63 | emitted. */ | |
64 | ||
65 | rtx rs6000_compare_op0, rs6000_compare_op1; | |
66 | int rs6000_compare_fp_p; | |
874a0744 MM |
67 | |
68 | #ifdef USING_SVR4_H | |
69 | /* Label number of label created for -mrelocatable, to call to so we can | |
70 | get the address of the GOT section */ | |
71 | int rs6000_pic_labelno; | |
72 | #endif | |
4697a36c MM |
73 | |
74 | /* Whether a System V.4 varargs area was created. */ | |
75 | int rs6000_sysv_varargs_p; | |
9878760c | 76 | \f |
5248c961 RK |
77 | /* Override command line options. Mostly we process the processor |
78 | type and sometimes adjust other TARGET_ options. */ | |
79 | ||
80 | void | |
81 | rs6000_override_options () | |
82 | { | |
83 | int i; | |
84 | ||
85638c0d RK |
85 | /* Simplify the entries below by making a mask for any POWER |
86 | variant and any PowerPC variant. */ | |
87 | ||
938937d8 | 88 | #define POWER_MASKS (MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING) |
68c49ffa RK |
89 | #define POWERPC_MASKS (MASK_POWERPC | MASK_PPC_GPOPT \ |
90 | | MASK_PPC_GFXOPT | MASK_POWERPC64) | |
91 | #define POWERPC_OPT_MASKS (MASK_PPC_GPOPT | MASK_PPC_GFXOPT) | |
85638c0d | 92 | |
5248c961 RK |
93 | static struct ptt |
94 | { | |
95 | char *name; /* Canonical processor name. */ | |
96 | enum processor_type processor; /* Processor type enum value. */ | |
97 | int target_enable; /* Target flags to enable. */ | |
98 | int target_disable; /* Target flags to disable. */ | |
99 | } processor_target_table[] | |
db7f1e43 RK |
100 | = {{"common", PROCESSOR_COMMON, 0, POWER_MASKS | POWERPC_MASKS}, |
101 | {"power", PROCESSOR_POWER, | |
938937d8 | 102 | MASK_POWER | MASK_MULTIPLE | MASK_STRING, |
db7f1e43 RK |
103 | MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS}, |
104 | {"powerpc", PROCESSOR_POWERPC, | |
105 | MASK_POWERPC | MASK_NEW_MNEMONICS, | |
68c49ffa | 106 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}, |
db7f1e43 | 107 | {"rios", PROCESSOR_RIOS1, |
938937d8 | 108 | MASK_POWER | MASK_MULTIPLE | MASK_STRING, |
db7f1e43 RK |
109 | MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS}, |
110 | {"rios1", PROCESSOR_RIOS1, | |
938937d8 | 111 | MASK_POWER | MASK_MULTIPLE | MASK_STRING, |
db7f1e43 RK |
112 | MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS}, |
113 | {"rsc", PROCESSOR_PPC601, | |
938937d8 | 114 | MASK_POWER | MASK_MULTIPLE | MASK_STRING, |
db7f1e43 RK |
115 | MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS}, |
116 | {"rsc1", PROCESSOR_PPC601, | |
938937d8 | 117 | MASK_POWER | MASK_MULTIPLE | MASK_STRING, |
db7f1e43 RK |
118 | MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS}, |
119 | {"rios2", PROCESSOR_RIOS2, | |
938937d8 | 120 | MASK_POWER | MASK_MULTIPLE | MASK_STRING | MASK_POWER2, |
db7f1e43 | 121 | POWERPC_MASKS | MASK_NEW_MNEMONICS}, |
49a0b204 MM |
122 | {"403", PROCESSOR_PPC403, |
123 | MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS, | |
124 | POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}, | |
5248c961 | 125 | {"601", PROCESSOR_PPC601, |
938937d8 | 126 | MASK_POWER | MASK_POWERPC | MASK_NEW_MNEMONICS | MASK_MULTIPLE | MASK_STRING, |
68c49ffa | 127 | MASK_POWER2 | POWERPC_OPT_MASKS | MASK_POWERPC64}, |
5248c961 | 128 | {"603", PROCESSOR_PPC603, |
68c49ffa RK |
129 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, |
130 | POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}, | |
5248c961 | 131 | {"604", PROCESSOR_PPC604, |
68c49ffa | 132 | MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, |
3675ff98 | 133 | POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}}; |
5248c961 RK |
134 | |
135 | int ptt_size = sizeof (processor_target_table) / sizeof (struct ptt); | |
136 | ||
8a61d227 | 137 | int multiple = TARGET_MULTIPLE; /* save current -mmultiple/-mno-multiple status */ |
938937d8 | 138 | int string = TARGET_STRING; /* save current -mstring/-mno-string status */ |
8a61d227 | 139 | |
5248c961 RK |
140 | profile_block_flag = 0; |
141 | ||
142 | /* Identify the processor type */ | |
143 | if (rs6000_cpu_string == 0) | |
144 | rs6000_cpu = PROCESSOR_DEFAULT; | |
145 | else | |
146 | { | |
147 | for (i = 0; i < ptt_size; i++) | |
148 | if (! strcmp (rs6000_cpu_string, processor_target_table[i].name)) | |
149 | { | |
150 | rs6000_cpu = processor_target_table[i].processor; | |
151 | target_flags |= processor_target_table[i].target_enable; | |
152 | target_flags &= ~processor_target_table[i].target_disable; | |
153 | break; | |
154 | } | |
155 | ||
156 | if (i == ptt_size) | |
157 | { | |
158 | error ("bad value (%s) for -mcpu= switch", rs6000_cpu_string); | |
159 | rs6000_cpu_string = "default"; | |
160 | rs6000_cpu = PROCESSOR_DEFAULT; | |
161 | } | |
162 | } | |
8a61d227 MM |
163 | |
164 | /* If -mmultiple or -mno-multiple was explicitly used, don't | |
165 | override with the processor default */ | |
166 | if (TARGET_MULTIPLE_SET) | |
167 | target_flags = (target_flags & ~MASK_MULTIPLE) | multiple; | |
7e69e155 | 168 | |
938937d8 MM |
169 | /* If -mstring or -mno-string was explicitly used, don't |
170 | override with the processor default */ | |
171 | if (TARGET_STRING_SET) | |
1f5515bf | 172 | target_flags = (target_flags & ~MASK_STRING) | string; |
938937d8 | 173 | |
7e69e155 MM |
174 | /* Don't allow -mmultiple or -mstring on little endian systems, because the |
175 | hardware doesn't support the instructions used in little endian mode */ | |
176 | if (!BYTES_BIG_ENDIAN) | |
177 | { | |
178 | if (TARGET_MULTIPLE) | |
179 | { | |
180 | target_flags &= ~MASK_MULTIPLE; | |
181 | if (TARGET_MULTIPLE_SET) | |
182 | warning ("-mmultiple is not supported on little endian systems"); | |
183 | } | |
184 | ||
185 | if (TARGET_STRING) | |
186 | { | |
187 | target_flags &= ~MASK_STRING; | |
938937d8 MM |
188 | if (TARGET_STRING_SET) |
189 | warning ("-mstring is not supported on little endian systems"); | |
7e69e155 MM |
190 | } |
191 | } | |
3933e0e1 MM |
192 | |
193 | #ifdef SUBTARGET_OVERRIDE_OPTIONS | |
194 | SUBTARGET_OVERRIDE_OPTIONS; | |
195 | #endif | |
5248c961 | 196 | } |
75814ad4 MM |
197 | \f |
198 | /* Create a CONST_DOUBLE like immed_double_const, except reverse the | |
199 | two parts of the constant if the target is little endian. */ | |
200 | ||
d679bebf RK |
201 | struct rtx_def * |
202 | rs6000_immed_double_const (i0, i1, mode) | |
75814ad4 MM |
203 | HOST_WIDE_INT i0, i1; |
204 | enum machine_mode mode; | |
205 | { | |
206 | if (! WORDS_BIG_ENDIAN) | |
207 | return immed_double_const (i1, i0, mode); | |
208 | ||
209 | return immed_double_const (i0, i1, mode); | |
210 | } | |
211 | ||
5248c961 | 212 | \f |
9878760c RK |
213 | /* Return non-zero if this function is known to have a null epilogue. */ |
214 | ||
215 | int | |
216 | direct_return () | |
217 | { | |
4697a36c MM |
218 | if (reload_completed) |
219 | { | |
220 | rs6000_stack_t *info = rs6000_stack_info (); | |
221 | ||
222 | if (info->first_gp_reg_save == 32 | |
223 | && info->first_fp_reg_save == 64 | |
224 | && !info->lr_save_p | |
225 | && !info->push_p) | |
226 | return 1; | |
227 | } | |
228 | ||
229 | return 0; | |
9878760c RK |
230 | } |
231 | ||
232 | /* Returns 1 always. */ | |
233 | ||
234 | int | |
235 | any_operand (op, mode) | |
236 | register rtx op; | |
237 | enum machine_mode mode; | |
238 | { | |
239 | return 1; | |
240 | } | |
241 | ||
242 | /* Return 1 if OP is a constant that can fit in a D field. */ | |
243 | ||
244 | int | |
245 | short_cint_operand (op, mode) | |
246 | register rtx op; | |
247 | enum machine_mode mode; | |
248 | { | |
249 | return (GET_CODE (op) == CONST_INT | |
250 | && (unsigned) (INTVAL (op) + 0x8000) < 0x10000); | |
251 | } | |
252 | ||
253 | /* Similar for a unsigned D field. */ | |
254 | ||
255 | int | |
256 | u_short_cint_operand (op, mode) | |
257 | register rtx op; | |
258 | enum machine_mode mode; | |
259 | { | |
260 | return (GET_CODE (op) == CONST_INT && (INTVAL (op) & 0xffff0000) == 0); | |
261 | } | |
262 | ||
dcfedcd0 RK |
263 | /* Return 1 if OP is a CONST_INT that cannot fit in a signed D field. */ |
264 | ||
265 | int | |
266 | non_short_cint_operand (op, mode) | |
267 | register rtx op; | |
268 | enum machine_mode mode; | |
269 | { | |
270 | return (GET_CODE (op) == CONST_INT | |
271 | && (unsigned) (INTVAL (op) + 0x8000) >= 0x10000); | |
272 | } | |
273 | ||
9878760c RK |
274 | /* Returns 1 if OP is a register that is not special (i.e., not MQ, |
275 | ctr, or lr). */ | |
276 | ||
277 | int | |
cd2b37d9 | 278 | gpc_reg_operand (op, mode) |
9878760c RK |
279 | register rtx op; |
280 | enum machine_mode mode; | |
281 | { | |
282 | return (register_operand (op, mode) | |
283 | && (GET_CODE (op) != REG || REGNO (op) >= 67 || REGNO (op) < 64)); | |
284 | } | |
285 | ||
286 | /* Returns 1 if OP is either a pseudo-register or a register denoting a | |
287 | CR field. */ | |
288 | ||
289 | int | |
290 | cc_reg_operand (op, mode) | |
291 | register rtx op; | |
292 | enum machine_mode mode; | |
293 | { | |
294 | return (register_operand (op, mode) | |
295 | && (GET_CODE (op) != REG | |
296 | || REGNO (op) >= FIRST_PSEUDO_REGISTER | |
297 | || CR_REGNO_P (REGNO (op)))); | |
298 | } | |
299 | ||
300 | /* Returns 1 if OP is either a constant integer valid for a D-field or a | |
301 | non-special register. If a register, it must be in the proper mode unless | |
302 | MODE is VOIDmode. */ | |
303 | ||
304 | int | |
305 | reg_or_short_operand (op, mode) | |
306 | register rtx op; | |
307 | enum machine_mode mode; | |
308 | { | |
f5a28898 | 309 | return short_cint_operand (op, mode) || gpc_reg_operand (op, mode); |
9878760c RK |
310 | } |
311 | ||
312 | /* Similar, except check if the negation of the constant would be valid for | |
313 | a D-field. */ | |
314 | ||
315 | int | |
316 | reg_or_neg_short_operand (op, mode) | |
317 | register rtx op; | |
318 | enum machine_mode mode; | |
319 | { | |
320 | if (GET_CODE (op) == CONST_INT) | |
321 | return CONST_OK_FOR_LETTER_P (INTVAL (op), 'P'); | |
322 | ||
cd2b37d9 | 323 | return gpc_reg_operand (op, mode); |
9878760c RK |
324 | } |
325 | ||
326 | /* Return 1 if the operand is either a register or an integer whose high-order | |
327 | 16 bits are zero. */ | |
328 | ||
329 | int | |
330 | reg_or_u_short_operand (op, mode) | |
331 | register rtx op; | |
332 | enum machine_mode mode; | |
333 | { | |
334 | if (GET_CODE (op) == CONST_INT | |
335 | && (INTVAL (op) & 0xffff0000) == 0) | |
336 | return 1; | |
337 | ||
cd2b37d9 | 338 | return gpc_reg_operand (op, mode); |
9878760c RK |
339 | } |
340 | ||
341 | /* Return 1 is the operand is either a non-special register or ANY | |
342 | constant integer. */ | |
343 | ||
344 | int | |
345 | reg_or_cint_operand (op, mode) | |
346 | register rtx op; | |
347 | enum machine_mode mode; | |
348 | { | |
cd2b37d9 | 349 | return GET_CODE (op) == CONST_INT || gpc_reg_operand (op, mode); |
9878760c RK |
350 | } |
351 | ||
6f2f8311 RK |
352 | /* Return 1 if the operand is a CONST_DOUBLE and it can be put into a register |
353 | with one instruction per word. We only do this if we can safely read | |
354 | CONST_DOUBLE_{LOW,HIGH}. */ | |
9878760c RK |
355 | |
356 | int | |
357 | easy_fp_constant (op, mode) | |
358 | register rtx op; | |
359 | register enum machine_mode mode; | |
360 | { | |
361 | rtx low, high; | |
362 | ||
363 | if (GET_CODE (op) != CONST_DOUBLE | |
364 | || GET_MODE (op) != mode | |
365 | || GET_MODE_CLASS (mode) != MODE_FLOAT) | |
366 | return 0; | |
367 | ||
368 | high = operand_subword (op, 0, 0, mode); | |
369 | low = operand_subword (op, 1, 0, mode); | |
370 | ||
6f2f8311 | 371 | if (high == 0 || ! input_operand (high, word_mode)) |
9878760c RK |
372 | return 0; |
373 | ||
374 | return (mode == SFmode | |
6f2f8311 | 375 | || (low != 0 && input_operand (low, word_mode))); |
9878760c RK |
376 | } |
377 | ||
914c2e77 RK |
378 | /* Return 1 if the operand is a constant whose low-order 32 bits are |
379 | zero. */ | |
380 | ||
381 | int | |
382 | low_32_bit_operand (op, mode) | |
383 | register rtx op; | |
384 | enum machine_mode mode; | |
385 | { | |
386 | rtx low; | |
387 | ||
388 | if (GET_CODE (op) != CONST_DOUBLE && GET_CODE (op) != CONST_INT) | |
389 | return 0; | |
390 | ||
391 | low = operand_subword (op, 1, 0, mode); | |
392 | return low != 0 && GET_CODE (low) == CONST_INT && INTVAL (low) == 0; | |
393 | } | |
394 | ||
9878760c RK |
395 | /* Return 1 if the operand is either a floating-point register, a pseudo |
396 | register, or memory. */ | |
397 | ||
398 | int | |
399 | fp_reg_or_mem_operand (op, mode) | |
400 | register rtx op; | |
401 | enum machine_mode mode; | |
402 | { | |
403 | return (memory_operand (op, mode) | |
404 | || (register_operand (op, mode) | |
405 | && (GET_CODE (op) != REG | |
406 | || REGNO (op) >= FIRST_PSEUDO_REGISTER | |
407 | || FP_REGNO_P (REGNO (op))))); | |
408 | } | |
409 | ||
410 | /* Return 1 if the operand is either an easy FP constant (see above) or | |
411 | memory. */ | |
412 | ||
413 | int | |
414 | mem_or_easy_const_operand (op, mode) | |
415 | register rtx op; | |
416 | enum machine_mode mode; | |
417 | { | |
418 | return memory_operand (op, mode) || easy_fp_constant (op, mode); | |
419 | } | |
420 | ||
421 | /* Return 1 if the operand is either a non-special register or an item | |
422 | that can be used as the operand of an SI add insn. */ | |
423 | ||
424 | int | |
425 | add_operand (op, mode) | |
426 | register rtx op; | |
427 | enum machine_mode mode; | |
428 | { | |
429 | return (reg_or_short_operand (op, mode) | |
430 | || (GET_CODE (op) == CONST_INT && (INTVAL (op) & 0xffff) == 0)); | |
431 | } | |
432 | ||
dcfedcd0 RK |
433 | /* Return 1 if OP is a constant but not a valid add_operand. */ |
434 | ||
435 | int | |
436 | non_add_cint_operand (op, mode) | |
437 | register rtx op; | |
438 | enum machine_mode mode; | |
439 | { | |
440 | return (GET_CODE (op) == CONST_INT | |
441 | && (unsigned) (INTVAL (op) + 0x8000) >= 0x10000 | |
442 | && (INTVAL (op) & 0xffff) != 0); | |
443 | } | |
444 | ||
9878760c RK |
445 | /* Return 1 if the operand is a non-special register or a constant that |
446 | can be used as the operand of an OR or XOR insn on the RS/6000. */ | |
447 | ||
448 | int | |
449 | logical_operand (op, mode) | |
450 | register rtx op; | |
451 | enum machine_mode mode; | |
452 | { | |
cd2b37d9 | 453 | return (gpc_reg_operand (op, mode) |
9878760c RK |
454 | || (GET_CODE (op) == CONST_INT |
455 | && ((INTVAL (op) & 0xffff0000) == 0 | |
456 | || (INTVAL (op) & 0xffff) == 0))); | |
457 | } | |
458 | ||
dcfedcd0 RK |
459 | /* Return 1 if C is a constant that is not a logical operand (as |
460 | above). */ | |
461 | ||
462 | int | |
463 | non_logical_cint_operand (op, mode) | |
464 | register rtx op; | |
465 | enum machine_mode mode; | |
466 | { | |
467 | return (GET_CODE (op) == CONST_INT | |
468 | && (INTVAL (op) & 0xffff0000) != 0 | |
469 | && (INTVAL (op) & 0xffff) != 0); | |
470 | } | |
471 | ||
9878760c RK |
472 | /* Return 1 if C is a constant that can be encoded in a mask on the |
473 | RS/6000. It is if there are no more than two 1->0 or 0->1 transitions. | |
474 | Reject all ones and all zeros, since these should have been optimized | |
475 | away and confuse the making of MB and ME. */ | |
476 | ||
477 | int | |
478 | mask_constant (c) | |
479 | register int c; | |
480 | { | |
481 | int i; | |
482 | int last_bit_value; | |
483 | int transitions = 0; | |
484 | ||
485 | if (c == 0 || c == ~0) | |
486 | return 0; | |
487 | ||
488 | last_bit_value = c & 1; | |
489 | ||
490 | for (i = 1; i < 32; i++) | |
491 | if (((c >>= 1) & 1) != last_bit_value) | |
492 | last_bit_value ^= 1, transitions++; | |
493 | ||
494 | return transitions <= 2; | |
495 | } | |
496 | ||
497 | /* Return 1 if the operand is a constant that is a mask on the RS/6000. */ | |
498 | ||
499 | int | |
500 | mask_operand (op, mode) | |
501 | register rtx op; | |
502 | enum machine_mode mode; | |
503 | { | |
504 | return GET_CODE (op) == CONST_INT && mask_constant (INTVAL (op)); | |
505 | } | |
506 | ||
507 | /* Return 1 if the operand is either a non-special register or a | |
508 | constant that can be used as the operand of an RS/6000 logical AND insn. */ | |
509 | ||
510 | int | |
511 | and_operand (op, mode) | |
512 | register rtx op; | |
513 | enum machine_mode mode; | |
514 | { | |
515 | return (reg_or_short_operand (op, mode) | |
516 | || logical_operand (op, mode) | |
517 | || mask_operand (op, mode)); | |
518 | } | |
519 | ||
dcfedcd0 RK |
520 | /* Return 1 if the operand is a constant but not a valid operand for an AND |
521 | insn. */ | |
522 | ||
523 | int | |
524 | non_and_cint_operand (op, mode) | |
525 | register rtx op; | |
526 | enum machine_mode mode; | |
527 | { | |
528 | return GET_CODE (op) == CONST_INT && ! and_operand (op, mode); | |
529 | } | |
530 | ||
9878760c RK |
531 | /* Return 1 if the operand is a general register or memory operand. */ |
532 | ||
533 | int | |
534 | reg_or_mem_operand (op, mode) | |
535 | register rtx op; | |
536 | register enum machine_mode mode; | |
537 | { | |
cd2b37d9 | 538 | return gpc_reg_operand (op, mode) || memory_operand (op, mode); |
9878760c RK |
539 | } |
540 | ||
a7a813f7 RK |
541 | /* Return 1 if the operand is a general register or memory operand without |
542 | pre-inc or pre_dec which produces invalid form of PowerPC lwa | |
543 | instruction. */ | |
544 | ||
545 | int | |
546 | lwa_operand (op, mode) | |
547 | register rtx op; | |
548 | register enum machine_mode mode; | |
549 | { | |
550 | rtx inner = op; | |
551 | ||
552 | if (reload_completed && GET_CODE (inner) == SUBREG) | |
553 | inner = SUBREG_REG (inner); | |
554 | ||
555 | return gpc_reg_operand (inner, mode) | |
556 | || (memory_operand (inner, mode) | |
557 | && GET_CODE (XEXP (inner, 0)) != PRE_INC | |
558 | && GET_CODE (XEXP (inner, 0)) != PRE_DEC); | |
559 | } | |
560 | ||
9878760c RK |
561 | /* Return 1 if the operand, used inside a MEM, is a valid first argument |
562 | to CALL. This is a SYMBOL_REF or a pseudo-register, which will be | |
563 | forced to lr. */ | |
564 | ||
565 | int | |
566 | call_operand (op, mode) | |
567 | register rtx op; | |
568 | enum machine_mode mode; | |
569 | { | |
570 | if (mode != VOIDmode && GET_MODE (op) != mode) | |
571 | return 0; | |
572 | ||
573 | return (GET_CODE (op) == SYMBOL_REF | |
574 | || (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER)); | |
575 | } | |
576 | ||
2af3d377 RK |
577 | |
578 | /* Return 1 if the operand is a SYMBOL_REF for a function known to be in | |
579 | this file. */ | |
580 | ||
581 | int | |
582 | current_file_function_operand (op, mode) | |
583 | register rtx op; | |
584 | enum machine_mode mode; | |
585 | { | |
586 | return (GET_CODE (op) == SYMBOL_REF | |
587 | && (SYMBOL_REF_FLAG (op) | |
588 | || op == XEXP (DECL_RTL (current_function_decl), 0))); | |
589 | } | |
590 | ||
591 | ||
9878760c RK |
592 | /* Return 1 if this operand is a valid input for a move insn. */ |
593 | ||
594 | int | |
595 | input_operand (op, mode) | |
596 | register rtx op; | |
597 | enum machine_mode mode; | |
598 | { | |
eb4e8003 | 599 | /* Memory is always valid. */ |
9878760c RK |
600 | if (memory_operand (op, mode)) |
601 | return 1; | |
602 | ||
eb4e8003 RK |
603 | /* For floating-point, easy constants are valid. */ |
604 | if (GET_MODE_CLASS (mode) == MODE_FLOAT | |
605 | && CONSTANT_P (op) | |
606 | && easy_fp_constant (op, mode)) | |
607 | return 1; | |
608 | ||
609 | /* For floating-point or multi-word mode, the only remaining valid type | |
610 | is a register. */ | |
9878760c RK |
611 | if (GET_MODE_CLASS (mode) == MODE_FLOAT |
612 | || GET_MODE_SIZE (mode) > UNITS_PER_WORD) | |
eb4e8003 | 613 | return register_operand (op, mode); |
9878760c | 614 | |
88fe15a1 RK |
615 | /* The only cases left are integral modes one word or smaller (we |
616 | do not get called for MODE_CC values). These can be in any | |
617 | register. */ | |
618 | if (register_operand (op, mode)) | |
a8b3aeda | 619 | return 1; |
88fe15a1 RK |
620 | |
621 | /* For HImode and QImode, any constant is valid. */ | |
622 | if ((mode == HImode || mode == QImode) | |
623 | && GET_CODE (op) == CONST_INT) | |
9878760c RK |
624 | return 1; |
625 | ||
84cf9dda | 626 | /* A SYMBOL_REF referring to the TOC is valid. */ |
7fec4abd | 627 | if (LEGITIMATE_CONSTANT_POOL_ADDRESS_P (op)) |
84cf9dda RK |
628 | return 1; |
629 | ||
9878760c RK |
630 | /* Otherwise, we will be doing this SET with an add, so anything valid |
631 | for an add will be valid. */ | |
632 | return add_operand (op, mode); | |
633 | } | |
4697a36c MM |
634 | \f |
635 | /* Initialize a variable CUM of type CUMULATIVE_ARGS | |
636 | for a call to a function whose data type is FNTYPE. | |
637 | For a library call, FNTYPE is 0. | |
638 | ||
639 | For incoming args we set the number of arguments in the prototype large | |
640 | so we never return an EXPR_LIST. */ | |
641 | ||
642 | void | |
643 | init_cumulative_args (cum, fntype, libname, incoming) | |
644 | CUMULATIVE_ARGS *cum; | |
645 | tree fntype; | |
646 | rtx libname; | |
647 | int incoming; | |
648 | { | |
649 | static CUMULATIVE_ARGS zero_cumulative; | |
650 | ||
651 | *cum = zero_cumulative; | |
652 | cum->words = 0; | |
653 | cum->fregno = FP_ARG_MIN_REG; | |
654 | cum->prototype = (fntype && TYPE_ARG_TYPES (fntype)); | |
655 | ||
656 | if (incoming) | |
657 | { | |
658 | cum->nargs_prototype = 1000; /* don't return an EXPR_LIST */ | |
659 | #ifdef TARGET_V4_CALLS | |
660 | if (TARGET_V4_CALLS) | |
661 | cum->varargs_offset = RS6000_VARARGS_OFFSET; | |
662 | #endif | |
663 | } | |
664 | ||
665 | else if (cum->prototype) | |
666 | cum->nargs_prototype = (list_length (TYPE_ARG_TYPES (fntype)) - 1 | |
667 | + (TYPE_MODE (TREE_TYPE (fntype)) == BLKmode | |
668 | || RETURN_IN_MEMORY (TREE_TYPE (fntype)))); | |
669 | ||
670 | else | |
671 | cum->nargs_prototype = 0; | |
672 | ||
673 | cum->orig_nargs = cum->nargs_prototype; | |
674 | if (TARGET_DEBUG_ARG) | |
675 | { | |
676 | fprintf (stderr, "\ninit_cumulative_args:"); | |
677 | if (fntype) | |
678 | { | |
679 | tree ret_type = TREE_TYPE (fntype); | |
680 | fprintf (stderr, " ret code = %s,", | |
681 | tree_code_name[ (int)TREE_CODE (ret_type) ]); | |
682 | } | |
683 | ||
684 | #ifdef TARGET_V4_CALLS | |
685 | if (TARGET_V4_CALLS && incoming) | |
686 | fprintf (stderr, " varargs = %d, ", cum->varargs_offset); | |
687 | #endif | |
688 | ||
689 | fprintf (stderr, " proto = %d, nargs = %d\n", | |
690 | cum->prototype, cum->nargs_prototype); | |
691 | } | |
692 | } | |
693 | \f | |
694 | /* Update the data in CUM to advance over an argument | |
695 | of mode MODE and data type TYPE. | |
696 | (TYPE is null for libcalls where that information may not be available.) */ | |
697 | ||
698 | void | |
699 | function_arg_advance (cum, mode, type, named) | |
700 | CUMULATIVE_ARGS *cum; | |
701 | enum machine_mode mode; | |
702 | tree type; | |
703 | int named; | |
704 | { | |
705 | cum->nargs_prototype--; | |
706 | ||
707 | #ifdef TARGET_V4_CALLS | |
708 | if (TARGET_V4_CALLS) | |
709 | { | |
710 | /* Long longs must not be split between registers and stack */ | |
711 | if ((GET_MODE_CLASS (mode) != MODE_FLOAT || TARGET_SOFT_FLOAT) | |
712 | && type && !AGGREGATE_TYPE_P (type) | |
713 | && cum->words < GP_ARG_NUM_REG | |
714 | && cum->words + RS6000_ARG_SIZE (mode, type, named) > GP_ARG_NUM_REG) | |
715 | { | |
716 | cum->words = GP_ARG_NUM_REG; | |
717 | } | |
718 | ||
719 | /* Aggregates get passed as pointers */ | |
720 | if (type && AGGREGATE_TYPE_P (type)) | |
721 | cum->words++; | |
722 | ||
723 | /* Floats go in registers, & don't occupy space in the GP registers | |
724 | like they do for AIX unless software floating point. */ | |
725 | else if (GET_MODE_CLASS (mode) == MODE_FLOAT | |
726 | && TARGET_HARD_FLOAT | |
727 | && cum->fregno <= FP_ARG_V4_MAX_REG) | |
728 | cum->fregno++; | |
729 | ||
730 | else | |
731 | cum->words += RS6000_ARG_SIZE (mode, type, 1); | |
732 | } | |
733 | else | |
734 | #endif | |
735 | if (named) | |
736 | { | |
737 | cum->words += RS6000_ARG_SIZE (mode, type, named); | |
738 | if (GET_MODE_CLASS (mode) == MODE_FLOAT && TARGET_HARD_FLOAT) | |
739 | cum->fregno++; | |
740 | } | |
741 | ||
742 | if (TARGET_DEBUG_ARG) | |
743 | fprintf (stderr, | |
744 | "function_adv: words = %2d, fregno = %2d, nargs = %4d, proto = %d, mode = %4s, named = %d\n", | |
745 | cum->words, cum->fregno, cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode), named); | |
746 | } | |
747 | \f | |
748 | /* Determine where to put an argument to a function. | |
749 | Value is zero to push the argument on the stack, | |
750 | or a hard register in which to store the argument. | |
751 | ||
752 | MODE is the argument's machine mode. | |
753 | TYPE is the data type of the argument (as a tree). | |
754 | This is null for libcalls where that information may | |
755 | not be available. | |
756 | CUM is a variable of type CUMULATIVE_ARGS which gives info about | |
757 | the preceding args and about the function being called. | |
758 | NAMED is nonzero if this argument is a named parameter | |
759 | (otherwise it is an extra parameter matching an ellipsis). | |
760 | ||
761 | On RS/6000 the first eight words of non-FP are normally in registers | |
762 | and the rest are pushed. Under AIX, the first 13 FP args are in registers. | |
763 | Under V.4, the first 8 FP args are in registers. | |
764 | ||
765 | If this is floating-point and no prototype is specified, we use | |
766 | both an FP and integer register (or possibly FP reg and stack). Library | |
767 | functions (when TYPE is zero) always have the proper types for args, | |
768 | so we can pass the FP value just in one register. emit_library_function | |
769 | doesn't support EXPR_LIST anyway. */ | |
770 | ||
771 | struct rtx_def * | |
772 | function_arg (cum, mode, type, named) | |
773 | CUMULATIVE_ARGS *cum; | |
774 | enum machine_mode mode; | |
775 | tree type; | |
776 | int named; | |
777 | { | |
778 | if (TARGET_DEBUG_ARG) | |
779 | fprintf (stderr, | |
780 | "function_arg: words = %2d, fregno = %2d, nargs = %4d, proto = %d, mode = %4s, named = %d\n", | |
781 | cum->words, cum->fregno, cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode), named); | |
782 | ||
783 | /* Return a marker to indicate whether CR1 needs to set or clear the bit that V.4 | |
784 | uses to say fp args were passed in registers. Assume that we don't need the | |
785 | marker for software floating point, or compiler generated library calls. */ | |
786 | if (mode == VOIDmode) | |
787 | { | |
788 | #ifdef TARGET_V4_CALLS | |
789 | if (TARGET_V4_CALLS && TARGET_HARD_FLOAT && cum->nargs_prototype < 0 | |
790 | && type && (cum->prototype || TARGET_NO_PROTOTYPE)) | |
791 | return GEN_INT ((cum->fregno == FP_ARG_MIN_REG) ? -1 : 1); | |
792 | #endif | |
793 | ||
794 | return GEN_INT (0); | |
795 | } | |
796 | ||
797 | if (!named) | |
798 | { | |
799 | #ifdef TARGET_V4_CALLS | |
800 | if (!TARGET_V4_CALLS) | |
801 | #endif | |
802 | return NULL_RTX; | |
803 | } | |
804 | ||
805 | if (type && TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST) | |
806 | return NULL_RTX; | |
807 | ||
808 | if (USE_FP_FOR_ARG_P (*cum, mode, type)) | |
809 | { | |
810 | if ((cum->nargs_prototype > 0) | |
811 | #ifdef TARGET_V4_CALLS | |
812 | || TARGET_V4_CALLS /* V.4 never passes FP values in GP registers */ | |
813 | #endif | |
814 | || !type) | |
815 | return gen_rtx (REG, mode, cum->fregno); | |
816 | ||
817 | return gen_rtx (EXPR_LIST, VOIDmode, | |
818 | ((cum->words < GP_ARG_NUM_REG) | |
819 | ? gen_rtx (REG, mode, GP_ARG_MIN_REG + cum->words) | |
820 | : NULL_RTX), | |
821 | gen_rtx (REG, mode, cum->fregno)); | |
822 | } | |
823 | ||
824 | #ifdef TARGET_V4_CALLS | |
825 | /* Long longs won't be split between register and stack */ | |
826 | else if (TARGET_V4_CALLS && | |
827 | cum->words + RS6000_ARG_SIZE (mode, type, named) > GP_ARG_NUM_REG) | |
828 | { | |
829 | return NULL_RTX; | |
830 | } | |
831 | #endif | |
832 | ||
833 | else if (cum->words < GP_ARG_NUM_REG) | |
834 | return gen_rtx (REG, mode, GP_ARG_MIN_REG + cum->words); | |
835 | ||
836 | return NULL_RTX; | |
837 | } | |
838 | \f | |
839 | /* For an arg passed partly in registers and partly in memory, | |
840 | this is the number of registers used. | |
841 | For args passed entirely in registers or entirely in memory, zero. */ | |
842 | ||
843 | int | |
844 | function_arg_partial_nregs (cum, mode, type, named) | |
845 | CUMULATIVE_ARGS *cum; | |
846 | enum machine_mode mode; | |
847 | tree type; | |
848 | int named; | |
849 | { | |
850 | if (! named) | |
851 | return 0; | |
852 | ||
853 | #ifdef TARGET_V4_CALLS | |
854 | if (TARGET_V4_CALLS) | |
855 | return 0; | |
856 | #endif | |
857 | ||
858 | if (USE_FP_FOR_ARG_P (*cum, mode, type)) | |
859 | { | |
860 | if (cum->nargs_prototype >= 0) | |
861 | return 0; | |
862 | } | |
863 | ||
864 | if (cum->words < GP_ARG_NUM_REG | |
865 | && GP_ARG_NUM_REG < (cum->words + RS6000_ARG_SIZE (mode, type, named))) | |
866 | { | |
867 | int ret = GP_ARG_NUM_REG - cum->words; | |
868 | if (ret && TARGET_DEBUG_ARG) | |
869 | fprintf (stderr, "function_arg_partial_nregs: %d\n", ret); | |
870 | ||
871 | return ret; | |
872 | } | |
873 | ||
874 | return 0; | |
875 | } | |
876 | \f | |
877 | /* A C expression that indicates when an argument must be passed by | |
878 | reference. If nonzero for an argument, a copy of that argument is | |
879 | made in memory and a pointer to the argument is passed instead of | |
880 | the argument itself. The pointer is passed in whatever way is | |
881 | appropriate for passing a pointer to that type. | |
882 | ||
883 | Under V.4, structures and unions are passed by reference. */ | |
884 | ||
885 | int | |
886 | function_arg_pass_by_reference (cum, mode, type, named) | |
887 | CUMULATIVE_ARGS *cum; | |
888 | enum machine_mode mode; | |
889 | tree type; | |
890 | int named; | |
891 | { | |
892 | #ifdef TARGET_V4_CALLS | |
893 | if (TARGET_V4_CALLS && type && AGGREGATE_TYPE_P (type)) | |
894 | { | |
895 | if (TARGET_DEBUG_ARG) | |
896 | fprintf (stderr, "function_arg_pass_by_reference: aggregate\n"); | |
897 | ||
898 | return 1; | |
899 | } | |
900 | #endif | |
901 | ||
902 | return 0; | |
903 | } | |
904 | ||
905 | \f | |
906 | /* Perform any needed actions needed for a function that is receiving a | |
907 | variable number of arguments. | |
908 | ||
909 | CUM is as above. | |
910 | ||
911 | MODE and TYPE are the mode and type of the current parameter. | |
912 | ||
913 | PRETEND_SIZE is a variable that should be set to the amount of stack | |
914 | that must be pushed by the prolog to pretend that our caller pushed | |
915 | it. | |
916 | ||
917 | Normally, this macro will push all remaining incoming registers on the | |
918 | stack and set PRETEND_SIZE to the length of the registers pushed. */ | |
919 | ||
920 | void | |
921 | setup_incoming_varargs (cum, mode, type, pretend_size, no_rtl) | |
922 | CUMULATIVE_ARGS *cum; | |
923 | enum machine_mode mode; | |
924 | tree type; | |
925 | int *pretend_size; | |
926 | int no_rtl; | |
927 | ||
928 | { | |
929 | rtx save_area = virtual_incoming_args_rtx; | |
930 | int reg_size = (TARGET_64BIT) ? 8 : 4; | |
931 | ||
932 | if (TARGET_DEBUG_ARG) | |
933 | fprintf (stderr, | |
934 | "setup_vararg: words = %2d, fregno = %2d, nargs = %4d, proto = %d, mode = %4s, no_rtl= %d\n", | |
935 | cum->words, cum->fregno, cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode), no_rtl); | |
936 | ||
937 | #ifdef TARGET_V4_CALLS | |
938 | if (TARGET_V4_CALLS && !no_rtl) | |
939 | { | |
940 | rs6000_sysv_varargs_p = 1; | |
941 | save_area = plus_constant (frame_pointer_rtx, RS6000_VARARGS_OFFSET); | |
942 | } | |
943 | #endif | |
944 | ||
945 | if (cum->words < 8) | |
946 | { | |
947 | int first_reg_offset = cum->words; | |
948 | ||
949 | if (MUST_PASS_IN_STACK (mode, type)) | |
950 | first_reg_offset += RS6000_ARG_SIZE (TYPE_MODE (type), type, 1); | |
951 | ||
952 | if (first_reg_offset > GP_ARG_NUM_REG) | |
953 | first_reg_offset = GP_ARG_NUM_REG; | |
954 | ||
955 | if (!no_rtl && first_reg_offset != GP_ARG_NUM_REG) | |
956 | move_block_from_reg | |
957 | (GP_ARG_MIN_REG + first_reg_offset, | |
958 | gen_rtx (MEM, BLKmode, | |
959 | plus_constant (save_area, first_reg_offset * reg_size)), | |
960 | GP_ARG_NUM_REG - first_reg_offset, | |
961 | (GP_ARG_NUM_REG - first_reg_offset) * UNITS_PER_WORD); | |
962 | ||
963 | *pretend_size = (GP_ARG_NUM_REG - first_reg_offset) * UNITS_PER_WORD; | |
964 | } | |
965 | ||
966 | #ifdef TARGET_V4_CALLS | |
967 | /* Save FP registers if needed. */ | |
968 | if (TARGET_V4_CALLS && TARGET_HARD_FLOAT && !no_rtl) | |
969 | { | |
970 | int fregno = cum->fregno; | |
971 | int num_fp_reg = FP_ARG_V4_MAX_REG + 1 - fregno; | |
972 | ||
973 | if (num_fp_reg >= 0) | |
974 | { | |
975 | rtx cr1 = gen_rtx (REG, CCmode, 69); | |
976 | rtx lab = gen_label_rtx (); | |
977 | int off = (GP_ARG_NUM_REG * reg_size) + ((fregno - FP_ARG_MIN_REG) * 8); | |
978 | ||
979 | emit_jump_insn (gen_rtx (SET, VOIDmode, | |
980 | pc_rtx, | |
981 | gen_rtx (IF_THEN_ELSE, VOIDmode, | |
982 | gen_rtx (NE, VOIDmode, cr1, const0_rtx), | |
983 | gen_rtx (LABEL_REF, VOIDmode, lab), | |
984 | pc_rtx))); | |
985 | ||
986 | while ( num_fp_reg-- >= 0) | |
987 | { | |
988 | emit_move_insn (gen_rtx (MEM, DFmode, plus_constant (save_area, off)), | |
989 | gen_rtx (REG, DFmode, fregno++)); | |
990 | off += 8; | |
991 | } | |
992 | ||
993 | emit_label (lab); | |
994 | } | |
995 | } | |
996 | #endif | |
997 | } | |
998 | \f | |
999 | /* If defined, is a C expression that produces the machine-specific | |
1000 | code for a call to `__builtin_saveregs'. This code will be moved | |
1001 | to the very beginning of the function, before any parameter access | |
1002 | are made. The return value of this function should be an RTX that | |
1003 | contains the value to use as the return of `__builtin_saveregs'. | |
1004 | ||
1005 | The argument ARGS is a `tree_list' containing the arguments that | |
1006 | were passed to `__builtin_saveregs'. | |
1007 | ||
1008 | If this macro is not defined, the compiler will output an ordinary | |
1009 | call to the library function `__builtin_saveregs'. | |
1010 | ||
1011 | On the Power/PowerPC return the address of the area on the stack | |
1012 | used to hold arguments. Under AIX, this includes the 8 word register | |
1013 | save area. Under V.4 this does not. */ | |
1014 | ||
1015 | struct rtx_def * | |
1016 | expand_builtin_saveregs (args) | |
1017 | tree args; | |
1018 | { | |
1019 | return virtual_incoming_args_rtx; | |
1020 | } | |
1021 | ||
7e69e155 MM |
1022 | \f |
1023 | /* Expand a block move operation, and return 1 if successful. Return 0 | |
1024 | if we should let the compiler generate normal code. | |
1025 | ||
1026 | operands[0] is the destination | |
1027 | operands[1] is the source | |
1028 | operands[2] is the length | |
1029 | operands[3] is the alignment */ | |
1030 | ||
3933e0e1 MM |
1031 | #define MAX_MOVE_REG 4 |
1032 | ||
7e69e155 MM |
1033 | int |
1034 | expand_block_move (operands) | |
1035 | rtx operands[]; | |
1036 | { | |
1037 | rtx bytes_rtx = operands[2]; | |
7e69e155 | 1038 | rtx align_rtx = operands[3]; |
3933e0e1 | 1039 | int constp = (GET_CODE (bytes_rtx) == CONST_INT); |
7e69e155 | 1040 | int align = XINT (align_rtx, 0); |
3933e0e1 MM |
1041 | int bytes; |
1042 | int offset; | |
1043 | int num_reg; | |
1044 | int i; | |
7e69e155 MM |
1045 | rtx src_reg; |
1046 | rtx dest_reg; | |
3933e0e1 MM |
1047 | rtx src_addr; |
1048 | rtx dest_addr; | |
7e69e155 | 1049 | rtx tmp_reg; |
3933e0e1 | 1050 | rtx stores[MAX_MOVE_REG]; |
7e69e155 MM |
1051 | int move_bytes; |
1052 | ||
3933e0e1 MM |
1053 | /* If this is not a fixed size move, just call memcpy */ |
1054 | if (!constp) | |
1055 | return 0; | |
1056 | ||
7e69e155 | 1057 | /* Anything to move? */ |
3933e0e1 MM |
1058 | bytes = INTVAL (bytes_rtx); |
1059 | if (bytes <= 0) | |
7e69e155 MM |
1060 | return 1; |
1061 | ||
3933e0e1 MM |
1062 | /* Don't support real large moves. If string instructions are not used, |
1063 | then don't generate more than 8 loads. */ | |
1064 | if (TARGET_STRING) | |
1065 | { | |
1cab3be1 | 1066 | if (bytes > 4*8) |
3933e0e1 MM |
1067 | return 0; |
1068 | } | |
1069 | else if (!STRICT_ALIGNMENT) | |
1070 | { | |
1071 | if (bytes > 4*8) | |
1072 | return 0; | |
1073 | } | |
1074 | else if (bytes > 8*align) | |
7e69e155 MM |
1075 | return 0; |
1076 | ||
1077 | /* Move the address into scratch registers. */ | |
1078 | dest_reg = copy_addr_to_reg (XEXP (operands[0], 0)); | |
1079 | src_reg = copy_addr_to_reg (XEXP (operands[1], 0)); | |
1080 | ||
3933e0e1 | 1081 | if (TARGET_STRING) /* string instructions are available */ |
7e69e155 | 1082 | { |
3933e0e1 | 1083 | for ( ; bytes > 0; bytes -= move_bytes) |
7e69e155 | 1084 | { |
3933e0e1 MM |
1085 | if (bytes > 24 /* move up to 32 bytes at a time */ |
1086 | && !fixed_regs[5] | |
1087 | && !fixed_regs[6] | |
1088 | && !fixed_regs[7] | |
1089 | && !fixed_regs[8] | |
1090 | && !fixed_regs[9] | |
1091 | && !fixed_regs[10] | |
1092 | && !fixed_regs[11] | |
1093 | && !fixed_regs[12]) | |
1094 | { | |
1095 | move_bytes = (bytes > 32) ? 32 : bytes; | |
1096 | emit_insn (gen_movstrsi_8reg (dest_reg, | |
1097 | src_reg, | |
1098 | GEN_INT ((move_bytes == 32) ? 0 : move_bytes), | |
4c64a852 | 1099 | align_rtx)); |
3933e0e1 MM |
1100 | } |
1101 | else if (bytes > 16 /* move up to 24 bytes at a time */ | |
1102 | && !fixed_regs[7] | |
1103 | && !fixed_regs[8] | |
1104 | && !fixed_regs[9] | |
1105 | && !fixed_regs[10] | |
1106 | && !fixed_regs[11] | |
1107 | && !fixed_regs[12]) | |
1108 | { | |
1109 | move_bytes = (bytes > 24) ? 24 : bytes; | |
1110 | emit_insn (gen_movstrsi_6reg (dest_reg, | |
1111 | src_reg, | |
1112 | GEN_INT (move_bytes), | |
4c64a852 | 1113 | align_rtx)); |
3933e0e1 MM |
1114 | } |
1115 | else if (bytes > 8 /* move up to 16 bytes at a time */ | |
1116 | && !fixed_regs[9] | |
1117 | && !fixed_regs[10] | |
1118 | && !fixed_regs[11] | |
1119 | && !fixed_regs[12]) | |
1120 | { | |
1121 | move_bytes = (bytes > 16) ? 16 : bytes; | |
1122 | emit_insn (gen_movstrsi_4reg (dest_reg, | |
1123 | src_reg, | |
1124 | GEN_INT (move_bytes), | |
4c64a852 | 1125 | align_rtx)); |
3933e0e1 | 1126 | } |
d679bebf | 1127 | else if (bytes > 4 && !TARGET_64BIT) |
3933e0e1 MM |
1128 | { /* move up to 8 bytes at a time */ |
1129 | move_bytes = (bytes > 8) ? 8 : bytes; | |
1130 | emit_insn (gen_movstrsi_2reg (dest_reg, | |
1131 | src_reg, | |
1132 | GEN_INT (move_bytes), | |
4c64a852 | 1133 | align_rtx)); |
3933e0e1 MM |
1134 | } |
1135 | else if (bytes >= 4 && (align >= 4 || !STRICT_ALIGNMENT)) | |
1136 | { /* move 4 bytes */ | |
1137 | move_bytes = 4; | |
1138 | tmp_reg = gen_reg_rtx (SImode); | |
1139 | emit_move_insn (tmp_reg, gen_rtx (MEM, SImode, src_reg)); | |
1140 | emit_move_insn (gen_rtx (MEM, SImode, dest_reg), tmp_reg); | |
3933e0e1 MM |
1141 | } |
1142 | else if (bytes == 2 && (align >= 2 || !STRICT_ALIGNMENT)) | |
1143 | { /* move 2 bytes */ | |
1144 | move_bytes = 2; | |
1145 | tmp_reg = gen_reg_rtx (HImode); | |
1146 | emit_move_insn (tmp_reg, gen_rtx (MEM, HImode, src_reg)); | |
1147 | emit_move_insn (gen_rtx (MEM, HImode, dest_reg), tmp_reg); | |
1148 | } | |
1149 | else if (bytes == 1) /* move 1 byte */ | |
1150 | { | |
1151 | move_bytes = 1; | |
1152 | tmp_reg = gen_reg_rtx (QImode); | |
1153 | emit_move_insn (tmp_reg, gen_rtx (MEM, QImode, src_reg)); | |
1154 | emit_move_insn (gen_rtx (MEM, QImode, dest_reg), tmp_reg); | |
1155 | } | |
1156 | else | |
1157 | { /* move up to 4 bytes at a time */ | |
1158 | move_bytes = (bytes > 4) ? 4 : bytes; | |
1159 | emit_insn (gen_movstrsi_1reg (dest_reg, | |
1160 | src_reg, | |
1161 | GEN_INT (move_bytes), | |
4c64a852 | 1162 | align_rtx)); |
3933e0e1 | 1163 | } |
4c64a852 | 1164 | |
015892ee RK |
1165 | if (bytes > move_bytes) |
1166 | { | |
1167 | emit_insn (gen_addsi3 (src_reg, src_reg, GEN_INT (move_bytes))); | |
1168 | emit_insn (gen_addsi3 (dest_reg, dest_reg, GEN_INT (move_bytes))); | |
1169 | } | |
4c64a852 | 1170 | } |
3933e0e1 MM |
1171 | } |
1172 | ||
1173 | else /* string instructions not available */ | |
1174 | { | |
1175 | num_reg = offset = 0; | |
1176 | for ( ; bytes > 0; (bytes -= move_bytes), (offset += move_bytes)) | |
7e69e155 | 1177 | { |
3933e0e1 MM |
1178 | /* Calculate the correct offset for src/dest */ |
1179 | if (offset == 0) | |
7e69e155 | 1180 | { |
3933e0e1 MM |
1181 | src_addr = src_reg; |
1182 | dest_addr = dest_reg; | |
1183 | } | |
1184 | else | |
1185 | { | |
1186 | src_addr = gen_rtx (PLUS, Pmode, src_reg, GEN_INT (offset)); | |
1187 | dest_addr = gen_rtx (PLUS, Pmode, dest_reg, GEN_INT (offset)); | |
1188 | } | |
1189 | ||
1190 | /* Generate the appropriate load and store, saving the stores for later */ | |
1191 | if (bytes >= 4 && (align >= 4 || !STRICT_ALIGNMENT)) | |
1192 | { | |
1193 | move_bytes = 4; | |
1194 | tmp_reg = gen_reg_rtx (SImode); | |
1195 | emit_insn (gen_movsi (tmp_reg, gen_rtx (MEM, SImode, src_addr))); | |
1196 | stores[ num_reg++ ] = gen_movsi (gen_rtx (MEM, SImode, dest_addr), tmp_reg); | |
1197 | } | |
1198 | else if (bytes >= 2 && (align >= 2 || !STRICT_ALIGNMENT)) | |
1199 | { | |
1200 | move_bytes = 2; | |
1201 | tmp_reg = gen_reg_rtx (HImode); | |
1202 | emit_insn (gen_movhi (tmp_reg, gen_rtx (MEM, HImode, src_addr))); | |
1203 | stores[ num_reg++ ] = gen_movhi (gen_rtx (MEM, HImode, dest_addr), tmp_reg); | |
1204 | } | |
1205 | else | |
1206 | { | |
1207 | move_bytes = 1; | |
1208 | tmp_reg = gen_reg_rtx (QImode); | |
1209 | emit_insn (gen_movqi (tmp_reg, gen_rtx (MEM, QImode, src_addr))); | |
1210 | stores[ num_reg++ ] = gen_movqi (gen_rtx (MEM, QImode, dest_addr), tmp_reg); | |
1211 | } | |
1212 | ||
1213 | if (num_reg >= MAX_MOVE_REG) | |
1214 | { | |
1215 | for (i = 0; i < num_reg; i++) | |
1216 | emit_insn (stores[i]); | |
1217 | num_reg = 0; | |
7e69e155 MM |
1218 | } |
1219 | } | |
3933e0e1 MM |
1220 | |
1221 | if (num_reg > 0) | |
7e69e155 | 1222 | { |
3933e0e1 MM |
1223 | for (i = 0; i < num_reg; i++) |
1224 | emit_insn (stores[i]); | |
7e69e155 MM |
1225 | } |
1226 | } | |
1227 | ||
1228 | return 1; | |
1229 | } | |
1230 | ||
9878760c RK |
1231 | \f |
1232 | /* Return 1 if OP is a load multiple operation. It is known to be a | |
1233 | PARALLEL and the first section will be tested. */ | |
1234 | ||
1235 | int | |
1236 | load_multiple_operation (op, mode) | |
1237 | rtx op; | |
1238 | enum machine_mode mode; | |
1239 | { | |
1240 | int count = XVECLEN (op, 0); | |
1241 | int dest_regno; | |
1242 | rtx src_addr; | |
1243 | int i; | |
1244 | ||
1245 | /* Perform a quick check so we don't blow up below. */ | |
1246 | if (count <= 1 | |
1247 | || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
1248 | || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG | |
1249 | || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM) | |
1250 | return 0; | |
1251 | ||
1252 | dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0))); | |
1253 | src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0); | |
1254 | ||
1255 | for (i = 1; i < count; i++) | |
1256 | { | |
1257 | rtx elt = XVECEXP (op, 0, i); | |
1258 | ||
1259 | if (GET_CODE (elt) != SET | |
1260 | || GET_CODE (SET_DEST (elt)) != REG | |
1261 | || GET_MODE (SET_DEST (elt)) != SImode | |
1262 | || REGNO (SET_DEST (elt)) != dest_regno + i | |
1263 | || GET_CODE (SET_SRC (elt)) != MEM | |
1264 | || GET_MODE (SET_SRC (elt)) != SImode | |
1265 | || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS | |
1266 | || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr) | |
1267 | || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT | |
1268 | || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != i * 4) | |
1269 | return 0; | |
1270 | } | |
1271 | ||
1272 | return 1; | |
1273 | } | |
1274 | ||
1275 | /* Similar, but tests for store multiple. Here, the second vector element | |
1276 | is a CLOBBER. It will be tested later. */ | |
1277 | ||
1278 | int | |
1279 | store_multiple_operation (op, mode) | |
1280 | rtx op; | |
1281 | enum machine_mode mode; | |
1282 | { | |
1283 | int count = XVECLEN (op, 0) - 1; | |
1284 | int src_regno; | |
1285 | rtx dest_addr; | |
1286 | int i; | |
1287 | ||
1288 | /* Perform a quick check so we don't blow up below. */ | |
1289 | if (count <= 1 | |
1290 | || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
1291 | || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM | |
1292 | || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG) | |
1293 | return 0; | |
1294 | ||
1295 | src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0))); | |
1296 | dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0); | |
1297 | ||
1298 | for (i = 1; i < count; i++) | |
1299 | { | |
1300 | rtx elt = XVECEXP (op, 0, i + 1); | |
1301 | ||
1302 | if (GET_CODE (elt) != SET | |
1303 | || GET_CODE (SET_SRC (elt)) != REG | |
1304 | || GET_MODE (SET_SRC (elt)) != SImode | |
1305 | || REGNO (SET_SRC (elt)) != src_regno + i | |
1306 | || GET_CODE (SET_DEST (elt)) != MEM | |
1307 | || GET_MODE (SET_DEST (elt)) != SImode | |
1308 | || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS | |
1309 | || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr) | |
1310 | || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT | |
1311 | || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != i * 4) | |
1312 | return 0; | |
1313 | } | |
1314 | ||
1315 | return 1; | |
1316 | } | |
1317 | \f | |
1318 | /* Return 1 if OP is a comparison operation that is valid for a branch insn. | |
1319 | We only check the opcode against the mode of the CC value here. */ | |
1320 | ||
1321 | int | |
1322 | branch_comparison_operator (op, mode) | |
1323 | register rtx op; | |
1324 | enum machine_mode mode; | |
1325 | { | |
1326 | enum rtx_code code = GET_CODE (op); | |
1327 | enum machine_mode cc_mode; | |
1328 | ||
1329 | if (GET_RTX_CLASS (code) != '<') | |
1330 | return 0; | |
1331 | ||
1332 | cc_mode = GET_MODE (XEXP (op, 0)); | |
1333 | if (GET_MODE_CLASS (cc_mode) != MODE_CC) | |
1334 | return 0; | |
1335 | ||
1336 | if ((code == GT || code == LT || code == GE || code == LE) | |
1337 | && cc_mode == CCUNSmode) | |
1338 | return 0; | |
1339 | ||
1340 | if ((code == GTU || code == LTU || code == GEU || code == LEU) | |
1341 | && (cc_mode != CCUNSmode)) | |
1342 | return 0; | |
1343 | ||
1344 | return 1; | |
1345 | } | |
1346 | ||
1347 | /* Return 1 if OP is a comparison operation that is valid for an scc insn. | |
1348 | We check the opcode against the mode of the CC value and disallow EQ or | |
1349 | NE comparisons for integers. */ | |
1350 | ||
1351 | int | |
1352 | scc_comparison_operator (op, mode) | |
1353 | register rtx op; | |
1354 | enum machine_mode mode; | |
1355 | { | |
1356 | enum rtx_code code = GET_CODE (op); | |
1357 | enum machine_mode cc_mode; | |
1358 | ||
1359 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
1360 | return 0; | |
1361 | ||
1362 | if (GET_RTX_CLASS (code) != '<') | |
1363 | return 0; | |
1364 | ||
1365 | cc_mode = GET_MODE (XEXP (op, 0)); | |
1366 | if (GET_MODE_CLASS (cc_mode) != MODE_CC) | |
1367 | return 0; | |
1368 | ||
1369 | if (code == NE && cc_mode != CCFPmode) | |
1370 | return 0; | |
1371 | ||
1372 | if ((code == GT || code == LT || code == GE || code == LE) | |
1373 | && cc_mode == CCUNSmode) | |
1374 | return 0; | |
1375 | ||
1376 | if ((code == GTU || code == LTU || code == GEU || code == LEU) | |
1377 | && (cc_mode != CCUNSmode)) | |
1378 | return 0; | |
1379 | ||
c5defebb RK |
1380 | if (cc_mode == CCEQmode && code != EQ && code != NE) |
1381 | return 0; | |
1382 | ||
9878760c RK |
1383 | return 1; |
1384 | } | |
1385 | \f | |
1386 | /* Return 1 if ANDOP is a mask that has no bits on that are not in the | |
1387 | mask required to convert the result of a rotate insn into a shift | |
1388 | left insn of SHIFTOP bits. Both are known to be CONST_INT. */ | |
1389 | ||
1390 | int | |
1391 | includes_lshift_p (shiftop, andop) | |
1392 | register rtx shiftop; | |
1393 | register rtx andop; | |
1394 | { | |
1395 | int shift_mask = (~0 << INTVAL (shiftop)); | |
1396 | ||
1397 | return (INTVAL (andop) & ~shift_mask) == 0; | |
1398 | } | |
1399 | ||
1400 | /* Similar, but for right shift. */ | |
1401 | ||
1402 | int | |
1403 | includes_rshift_p (shiftop, andop) | |
1404 | register rtx shiftop; | |
1405 | register rtx andop; | |
1406 | { | |
1407 | unsigned shift_mask = ~0; | |
1408 | ||
1409 | shift_mask >>= INTVAL (shiftop); | |
1410 | ||
1411 | return (INTVAL (andop) & ~ shift_mask) == 0; | |
1412 | } | |
35068b43 RK |
1413 | |
1414 | /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates | |
1415 | for lfq and stfq insns. | |
1416 | ||
1417 | Note reg1 and reg2 *must* be hard registers. To be sure we will | |
1418 | abort if we are passed pseudo registers. */ | |
1419 | ||
1420 | int | |
1421 | registers_ok_for_quad_peep (reg1, reg2) | |
1422 | rtx reg1, reg2; | |
1423 | { | |
1424 | /* We might have been passed a SUBREG. */ | |
1425 | if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG) | |
1426 | return 0; | |
1427 | ||
1428 | return (REGNO (reg1) == REGNO (reg2) - 1); | |
1429 | } | |
1430 | ||
1431 | /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn. addr1 and | |
1432 | addr2 must be in consecutive memory locations (addr2 == addr1 + 8). */ | |
1433 | ||
1434 | int | |
1435 | addrs_ok_for_quad_peep (addr1, addr2) | |
1436 | register rtx addr1; | |
1437 | register rtx addr2; | |
1438 | { | |
1439 | int reg1; | |
1440 | int offset1; | |
1441 | ||
1442 | /* Extract an offset (if used) from the first addr. */ | |
1443 | if (GET_CODE (addr1) == PLUS) | |
1444 | { | |
1445 | /* If not a REG, return zero. */ | |
1446 | if (GET_CODE (XEXP (addr1, 0)) != REG) | |
1447 | return 0; | |
1448 | else | |
1449 | { | |
1450 | reg1 = REGNO (XEXP (addr1, 0)); | |
1451 | /* The offset must be constant! */ | |
1452 | if (GET_CODE (XEXP (addr1, 1)) != CONST_INT) | |
1453 | return 0; | |
1454 | offset1 = INTVAL (XEXP (addr1, 1)); | |
1455 | } | |
1456 | } | |
1457 | else if (GET_CODE (addr1) != REG) | |
1458 | return 0; | |
1459 | else | |
1460 | { | |
1461 | reg1 = REGNO (addr1); | |
1462 | /* This was a simple (mem (reg)) expression. Offset is 0. */ | |
1463 | offset1 = 0; | |
1464 | } | |
1465 | ||
1466 | /* Make sure the second address is a (mem (plus (reg) (const_int). */ | |
1467 | if (GET_CODE (addr2) != PLUS) | |
1468 | return 0; | |
1469 | ||
1470 | if (GET_CODE (XEXP (addr2, 0)) != REG | |
1471 | || GET_CODE (XEXP (addr2, 1)) != CONST_INT) | |
1472 | return 0; | |
1473 | ||
1474 | if (reg1 != REGNO (XEXP (addr2, 0))) | |
1475 | return 0; | |
1476 | ||
1477 | /* The offset for the second addr must be 8 more than the first addr. */ | |
1478 | if (INTVAL (XEXP (addr2, 1)) != offset1 + 8) | |
1479 | return 0; | |
1480 | ||
1481 | /* All the tests passed. addr1 and addr2 are valid for lfq or stfq | |
1482 | instructions. */ | |
1483 | return 1; | |
1484 | } | |
9878760c RK |
1485 | \f |
1486 | /* Return the register class of a scratch register needed to copy IN into | |
1487 | or out of a register in CLASS in MODE. If it can be done directly, | |
1488 | NO_REGS is returned. */ | |
1489 | ||
1490 | enum reg_class | |
1491 | secondary_reload_class (class, mode, in) | |
1492 | enum reg_class class; | |
1493 | enum machine_mode mode; | |
1494 | rtx in; | |
1495 | { | |
1496 | int regno = true_regnum (in); | |
1497 | ||
1498 | if (regno >= FIRST_PSEUDO_REGISTER) | |
1499 | regno = -1; | |
1500 | ||
1501 | /* We can place anything into GENERAL_REGS and can put GENERAL_REGS | |
1502 | into anything. */ | |
1503 | if (class == GENERAL_REGS || class == BASE_REGS | |
1504 | || (regno >= 0 && INT_REGNO_P (regno))) | |
1505 | return NO_REGS; | |
1506 | ||
1507 | /* Constants, memory, and FP registers can go into FP registers. */ | |
1508 | if ((regno == -1 || FP_REGNO_P (regno)) | |
1509 | && (class == FLOAT_REGS || class == NON_SPECIAL_REGS)) | |
1510 | return NO_REGS; | |
1511 | ||
1512 | /* We can copy among the CR registers. */ | |
1513 | if ((class == CR_REGS || class == CR0_REGS) | |
1514 | && regno >= 0 && CR_REGNO_P (regno)) | |
1515 | return NO_REGS; | |
1516 | ||
1517 | /* Otherwise, we need GENERAL_REGS. */ | |
1518 | return GENERAL_REGS; | |
1519 | } | |
1520 | \f | |
1521 | /* Given a comparison operation, return the bit number in CCR to test. We | |
1522 | know this is a valid comparison. | |
1523 | ||
1524 | SCC_P is 1 if this is for an scc. That means that %D will have been | |
1525 | used instead of %C, so the bits will be in different places. | |
1526 | ||
b4ac57ab | 1527 | Return -1 if OP isn't a valid comparison for some reason. */ |
9878760c RK |
1528 | |
1529 | int | |
1530 | ccr_bit (op, scc_p) | |
1531 | register rtx op; | |
1532 | int scc_p; | |
1533 | { | |
1534 | enum rtx_code code = GET_CODE (op); | |
1535 | enum machine_mode cc_mode; | |
1536 | int cc_regnum; | |
1537 | int base_bit; | |
1538 | ||
1539 | if (GET_RTX_CLASS (code) != '<') | |
1540 | return -1; | |
1541 | ||
1542 | cc_mode = GET_MODE (XEXP (op, 0)); | |
1543 | cc_regnum = REGNO (XEXP (op, 0)); | |
1544 | base_bit = 4 * (cc_regnum - 68); | |
1545 | ||
c5defebb RK |
1546 | /* In CCEQmode cases we have made sure that the result is always in the |
1547 | third bit of the CR field. */ | |
1548 | ||
1549 | if (cc_mode == CCEQmode) | |
1550 | return base_bit + 3; | |
1551 | ||
9878760c RK |
1552 | switch (code) |
1553 | { | |
1554 | case NE: | |
1555 | return scc_p ? base_bit + 3 : base_bit + 2; | |
1556 | case EQ: | |
1557 | return base_bit + 2; | |
1558 | case GT: case GTU: | |
1559 | return base_bit + 1; | |
1560 | case LT: case LTU: | |
1561 | return base_bit; | |
1562 | ||
1563 | case GE: case GEU: | |
1564 | /* If floating-point, we will have done a cror to put the bit in the | |
1565 | unordered position. So test that bit. For integer, this is ! LT | |
1566 | unless this is an scc insn. */ | |
1567 | return cc_mode == CCFPmode || scc_p ? base_bit + 3 : base_bit; | |
1568 | ||
1569 | case LE: case LEU: | |
1570 | return cc_mode == CCFPmode || scc_p ? base_bit + 3 : base_bit + 1; | |
1571 | ||
1572 | default: | |
1573 | abort (); | |
1574 | } | |
1575 | } | |
1576 | \f | |
1577 | /* Print an operand. Recognize special options, documented below. */ | |
1578 | ||
1579 | void | |
1580 | print_operand (file, x, code) | |
1581 | FILE *file; | |
1582 | rtx x; | |
1583 | char code; | |
1584 | { | |
1585 | int i; | |
1586 | int val; | |
1587 | ||
1588 | /* These macros test for integers and extract the low-order bits. */ | |
1589 | #define INT_P(X) \ | |
1590 | ((GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST_DOUBLE) \ | |
1591 | && GET_MODE (X) == VOIDmode) | |
1592 | ||
1593 | #define INT_LOWPART(X) \ | |
1594 | (GET_CODE (X) == CONST_INT ? INTVAL (X) : CONST_DOUBLE_LOW (X)) | |
1595 | ||
1596 | switch (code) | |
1597 | { | |
a8b3aeda | 1598 | case '.': |
a85d226b RK |
1599 | /* Write out an instruction after the call which may be replaced |
1600 | with glue code by the loader. This depends on the AIX version. */ | |
1601 | asm_fprintf (file, RS6000_CALL_GLUE); | |
a8b3aeda RK |
1602 | return; |
1603 | ||
cfaaaf2e RK |
1604 | case '*': |
1605 | /* Write the register number of the TOC register. */ | |
4697a36c | 1606 | fputs (TARGET_MINIMAL_TOC ? reg_names[30] : reg_names[2], file); |
cfaaaf2e RK |
1607 | return; |
1608 | ||
9854d9ed RK |
1609 | case 'A': |
1610 | /* If X is a constant integer whose low-order 5 bits are zero, | |
1611 | write 'l'. Otherwise, write 'r'. This is a kludge to fix a bug | |
76229ac8 | 1612 | in the AIX assembler where "sri" with a zero shift count |
9854d9ed RK |
1613 | write a trash instruction. */ |
1614 | if (GET_CODE (x) == CONST_INT && (INTVAL (x) & 31) == 0) | |
76229ac8 | 1615 | putc ('l', file); |
9854d9ed | 1616 | else |
76229ac8 | 1617 | putc ('r', file); |
9854d9ed RK |
1618 | return; |
1619 | ||
1620 | case 'b': | |
1621 | /* Low-order 16 bits of constant, unsigned. */ | |
cad12a8d | 1622 | if (! INT_P (x)) |
9854d9ed | 1623 | output_operand_lossage ("invalid %%b value"); |
cad12a8d | 1624 | |
9854d9ed | 1625 | fprintf (file, "%d", INT_LOWPART (x) & 0xffff); |
cad12a8d RK |
1626 | return; |
1627 | ||
9854d9ed RK |
1628 | case 'C': |
1629 | /* This is an optional cror needed for LE or GE floating-point | |
1630 | comparisons. Otherwise write nothing. */ | |
1631 | if ((GET_CODE (x) == LE || GET_CODE (x) == GE) | |
1632 | && GET_MODE (XEXP (x, 0)) == CCFPmode) | |
1633 | { | |
1634 | int base_bit = 4 * (REGNO (XEXP (x, 0)) - 68); | |
1635 | ||
1636 | fprintf (file, "cror %d,%d,%d\n\t", base_bit + 3, | |
1637 | base_bit + 2, base_bit + (GET_CODE (x) == GE)); | |
1638 | } | |
1639 | return; | |
1640 | ||
1641 | case 'D': | |
1642 | /* Similar, except that this is for an scc, so we must be able to | |
1643 | encode the test in a single bit that is one. We do the above | |
1644 | for any LE, GE, GEU, or LEU and invert the bit for NE. */ | |
1645 | if (GET_CODE (x) == LE || GET_CODE (x) == GE | |
1646 | || GET_CODE (x) == LEU || GET_CODE (x) == GEU) | |
1647 | { | |
1648 | int base_bit = 4 * (REGNO (XEXP (x, 0)) - 68); | |
1649 | ||
1650 | fprintf (file, "cror %d,%d,%d\n\t", base_bit + 3, | |
1651 | base_bit + 2, | |
1652 | base_bit + (GET_CODE (x) == GE || GET_CODE (x) == GEU)); | |
1653 | } | |
1654 | ||
1655 | else if (GET_CODE (x) == NE) | |
1656 | { | |
1657 | int base_bit = 4 * (REGNO (XEXP (x, 0)) - 68); | |
1658 | ||
1659 | fprintf (file, "crnor %d,%d,%d\n\t", base_bit + 3, | |
1660 | base_bit + 2, base_bit + 2); | |
1661 | } | |
1662 | return; | |
1663 | ||
1664 | case 'E': | |
1665 | /* X is a CR register. Print the number of the third bit of the CR */ | |
1666 | if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x))) | |
1667 | output_operand_lossage ("invalid %%E value"); | |
1668 | ||
1669 | fprintf(file, "%d", 4 * (REGNO (x) - 68) + 3); | |
a85d226b | 1670 | return; |
9854d9ed RK |
1671 | |
1672 | case 'f': | |
1673 | /* X is a CR register. Print the shift count needed to move it | |
1674 | to the high-order four bits. */ | |
1675 | if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x))) | |
1676 | output_operand_lossage ("invalid %%f value"); | |
1677 | else | |
1678 | fprintf (file, "%d", 4 * (REGNO (x) - 68)); | |
1679 | return; | |
1680 | ||
1681 | case 'F': | |
1682 | /* Similar, but print the count for the rotate in the opposite | |
1683 | direction. */ | |
1684 | if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x))) | |
1685 | output_operand_lossage ("invalid %%F value"); | |
1686 | else | |
1687 | fprintf (file, "%d", 32 - 4 * (REGNO (x) - 68)); | |
1688 | return; | |
1689 | ||
1690 | case 'G': | |
1691 | /* X is a constant integer. If it is negative, print "m", | |
1692 | otherwise print "z". This is to make a aze or ame insn. */ | |
1693 | if (GET_CODE (x) != CONST_INT) | |
1694 | output_operand_lossage ("invalid %%G value"); | |
1695 | else if (INTVAL (x) >= 0) | |
76229ac8 | 1696 | putc ('z', file); |
9854d9ed | 1697 | else |
76229ac8 | 1698 | putc ('m', file); |
9854d9ed RK |
1699 | return; |
1700 | ||
9878760c | 1701 | case 'h': |
df3d94ed RK |
1702 | /* If constant, output low-order five bits. Otherwise, |
1703 | write normally. */ | |
9878760c RK |
1704 | if (INT_P (x)) |
1705 | fprintf (file, "%d", INT_LOWPART (x) & 31); | |
1706 | else | |
1707 | print_operand (file, x, 0); | |
1708 | return; | |
1709 | ||
9854d9ed RK |
1710 | case 'I': |
1711 | /* Print `i' if this is a constant, else nothing. */ | |
9878760c | 1712 | if (INT_P (x)) |
76229ac8 | 1713 | putc ('i', file); |
9878760c RK |
1714 | return; |
1715 | ||
9854d9ed RK |
1716 | case 'j': |
1717 | /* Write the bit number in CCR for jump. */ | |
1718 | i = ccr_bit (x, 0); | |
1719 | if (i == -1) | |
1720 | output_operand_lossage ("invalid %%j code"); | |
9878760c | 1721 | else |
9854d9ed | 1722 | fprintf (file, "%d", i); |
9878760c RK |
1723 | return; |
1724 | ||
9854d9ed RK |
1725 | case 'J': |
1726 | /* Similar, but add one for shift count in rlinm for scc and pass | |
1727 | scc flag to `ccr_bit'. */ | |
1728 | i = ccr_bit (x, 1); | |
1729 | if (i == -1) | |
1730 | output_operand_lossage ("invalid %%J code"); | |
1731 | else | |
a0466a68 RK |
1732 | /* If we want bit 31, write a shift count of zero, not 32. */ |
1733 | fprintf (file, "%d", i == 31 ? 0 : i + 1); | |
9878760c RK |
1734 | return; |
1735 | ||
9854d9ed RK |
1736 | case 'k': |
1737 | /* X must be a constant. Write the 1's complement of the | |
1738 | constant. */ | |
9878760c | 1739 | if (! INT_P (x)) |
9854d9ed | 1740 | output_operand_lossage ("invalid %%k value"); |
9878760c | 1741 | |
9854d9ed | 1742 | fprintf (file, "%d", ~ INT_LOWPART (x)); |
9878760c RK |
1743 | return; |
1744 | ||
9854d9ed RK |
1745 | case 'L': |
1746 | /* Write second word of DImode or DFmode reference. Works on register | |
1747 | or non-indexed memory only. */ | |
1748 | if (GET_CODE (x) == REG) | |
1749 | fprintf (file, "%d", REGNO (x) + 1); | |
1750 | else if (GET_CODE (x) == MEM) | |
1751 | { | |
1752 | /* Handle possible auto-increment. Since it is pre-increment and | |
1753 | we have already done it, we can just use an offset of four. */ | |
1754 | if (GET_CODE (XEXP (x, 0)) == PRE_INC | |
1755 | || GET_CODE (XEXP (x, 0)) == PRE_DEC) | |
1756 | output_address (plus_constant (XEXP (XEXP (x, 0), 0), 4)); | |
1757 | else | |
1758 | output_address (plus_constant (XEXP (x, 0), 4)); | |
1759 | } | |
9878760c | 1760 | return; |
9854d9ed | 1761 | |
9878760c RK |
1762 | case 'm': |
1763 | /* MB value for a mask operand. */ | |
1764 | if (! mask_operand (x, VOIDmode)) | |
1765 | output_operand_lossage ("invalid %%m value"); | |
1766 | ||
1767 | val = INT_LOWPART (x); | |
1768 | ||
1769 | /* If the high bit is set and the low bit is not, the value is zero. | |
1770 | If the high bit is zero, the value is the first 1 bit we find from | |
1771 | the left. */ | |
1772 | if (val < 0 && (val & 1) == 0) | |
1773 | { | |
1774 | fprintf (file, "0"); | |
1775 | return; | |
1776 | } | |
1777 | else if (val >= 0) | |
1778 | { | |
1779 | for (i = 1; i < 32; i++) | |
1780 | if ((val <<= 1) < 0) | |
1781 | break; | |
1782 | fprintf (file, "%d", i); | |
1783 | return; | |
1784 | } | |
1785 | ||
1786 | /* Otherwise, look for the first 0 bit from the right. The result is its | |
1787 | number plus 1. We know the low-order bit is one. */ | |
1788 | for (i = 0; i < 32; i++) | |
1789 | if (((val >>= 1) & 1) == 0) | |
1790 | break; | |
1791 | ||
1792 | /* If we ended in ...01, I would be 0. The correct value is 31, so | |
1793 | we want 31 - i. */ | |
1794 | fprintf (file, "%d", 31 - i); | |
1795 | return; | |
1796 | ||
1797 | case 'M': | |
1798 | /* ME value for a mask operand. */ | |
1799 | if (! mask_operand (x, VOIDmode)) | |
1800 | output_operand_lossage ("invalid %%m value"); | |
1801 | ||
1802 | val = INT_LOWPART (x); | |
1803 | ||
1804 | /* If the low bit is set and the high bit is not, the value is 31. | |
1805 | If the low bit is zero, the value is the first 1 bit we find from | |
1806 | the right. */ | |
1807 | if ((val & 1) && val >= 0) | |
1808 | { | |
76229ac8 | 1809 | fputs ("31", file); |
9878760c RK |
1810 | return; |
1811 | } | |
1812 | else if ((val & 1) == 0) | |
1813 | { | |
1814 | for (i = 0; i < 32; i++) | |
1815 | if ((val >>= 1) & 1) | |
1816 | break; | |
1817 | ||
1818 | /* If we had ....10, I would be 0. The result should be | |
1819 | 30, so we need 30 - i. */ | |
1820 | fprintf (file, "%d", 30 - i); | |
1821 | return; | |
1822 | } | |
1823 | ||
1824 | /* Otherwise, look for the first 0 bit from the left. The result is its | |
1825 | number minus 1. We know the high-order bit is one. */ | |
1826 | for (i = 0; i < 32; i++) | |
1827 | if ((val <<= 1) >= 0) | |
1828 | break; | |
1829 | ||
1830 | fprintf (file, "%d", i); | |
1831 | return; | |
1832 | ||
9878760c RK |
1833 | case 'N': |
1834 | /* Write the number of elements in the vector times 4. */ | |
1835 | if (GET_CODE (x) != PARALLEL) | |
1836 | output_operand_lossage ("invalid %%N value"); | |
1837 | ||
1838 | fprintf (file, "%d", XVECLEN (x, 0) * 4); | |
1839 | return; | |
1840 | ||
1841 | case 'O': | |
1842 | /* Similar, but subtract 1 first. */ | |
1843 | if (GET_CODE (x) != PARALLEL) | |
1844 | output_operand_lossage ("invalid %%N value"); | |
1845 | ||
1846 | fprintf (file, "%d", (XVECLEN (x, 0) - 1) * 4); | |
1847 | return; | |
1848 | ||
9854d9ed RK |
1849 | case 'p': |
1850 | /* X is a CONST_INT that is a power of two. Output the logarithm. */ | |
1851 | if (! INT_P (x) | |
1852 | || (i = exact_log2 (INT_LOWPART (x))) < 0) | |
1853 | output_operand_lossage ("invalid %%p value"); | |
1854 | ||
1855 | fprintf (file, "%d", i); | |
1856 | return; | |
1857 | ||
9878760c RK |
1858 | case 'P': |
1859 | /* The operand must be an indirect memory reference. The result | |
1860 | is the register number. */ | |
1861 | if (GET_CODE (x) != MEM || GET_CODE (XEXP (x, 0)) != REG | |
1862 | || REGNO (XEXP (x, 0)) >= 32) | |
1863 | output_operand_lossage ("invalid %%P value"); | |
1864 | ||
1865 | fprintf (file, "%d", REGNO (XEXP (x, 0))); | |
1866 | return; | |
1867 | ||
9854d9ed RK |
1868 | case 'R': |
1869 | /* X is a CR register. Print the mask for `mtcrf'. */ | |
1870 | if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x))) | |
1871 | output_operand_lossage ("invalid %%R value"); | |
1872 | else | |
1873 | fprintf (file, "%d", 128 >> (REGNO (x) - 68)); | |
9878760c | 1874 | return; |
9854d9ed RK |
1875 | |
1876 | case 's': | |
1877 | /* Low 5 bits of 32 - value */ | |
1878 | if (! INT_P (x)) | |
1879 | output_operand_lossage ("invalid %%s value"); | |
1880 | ||
1881 | fprintf (file, "%d", (32 - INT_LOWPART (x)) & 31); | |
9878760c | 1882 | return; |
9854d9ed | 1883 | |
9878760c RK |
1884 | case 't': |
1885 | /* Write 12 if this jump operation will branch if true, 4 otherwise. | |
1886 | All floating-point operations except NE branch true and integer | |
1887 | EQ, LT, GT, LTU and GTU also branch true. */ | |
1888 | if (GET_RTX_CLASS (GET_CODE (x)) != '<') | |
1889 | output_operand_lossage ("invalid %%t value"); | |
1890 | ||
1891 | else if ((GET_MODE (XEXP (x, 0)) == CCFPmode | |
1892 | && GET_CODE (x) != NE) | |
1893 | || GET_CODE (x) == EQ | |
1894 | || GET_CODE (x) == LT || GET_CODE (x) == GT | |
1895 | || GET_CODE (x) == LTU || GET_CODE (x) == GTU) | |
76229ac8 | 1896 | fputs ("12", file); |
9878760c | 1897 | else |
76229ac8 | 1898 | putc ('4', file); |
9878760c RK |
1899 | return; |
1900 | ||
1901 | case 'T': | |
1902 | /* Opposite of 't': write 4 if this jump operation will branch if true, | |
1903 | 12 otherwise. */ | |
1904 | if (GET_RTX_CLASS (GET_CODE (x)) != '<') | |
1905 | output_operand_lossage ("invalid %%t value"); | |
1906 | ||
1907 | else if ((GET_MODE (XEXP (x, 0)) == CCFPmode | |
1908 | && GET_CODE (x) != NE) | |
1909 | || GET_CODE (x) == EQ | |
1910 | || GET_CODE (x) == LT || GET_CODE (x) == GT | |
1911 | || GET_CODE (x) == LTU || GET_CODE (x) == GTU) | |
76229ac8 | 1912 | putc ('4', file); |
9878760c | 1913 | else |
76229ac8 | 1914 | fputs ("12", file); |
9878760c RK |
1915 | return; |
1916 | ||
9854d9ed RK |
1917 | case 'u': |
1918 | /* High-order 16 bits of constant. */ | |
1919 | if (! INT_P (x)) | |
1920 | output_operand_lossage ("invalid %%u value"); | |
9878760c | 1921 | |
76229ac8 | 1922 | fprintf (file, "0x%x", (INT_LOWPART (x) >> 16) & 0xffff); |
9878760c RK |
1923 | return; |
1924 | ||
9854d9ed RK |
1925 | case 'U': |
1926 | /* Print `u' if this has an auto-increment or auto-decrement. */ | |
1927 | if (GET_CODE (x) == MEM | |
1928 | && (GET_CODE (XEXP (x, 0)) == PRE_INC | |
1929 | || GET_CODE (XEXP (x, 0)) == PRE_DEC)) | |
76229ac8 | 1930 | putc ('u', file); |
9854d9ed | 1931 | return; |
9878760c | 1932 | |
9854d9ed RK |
1933 | case 'w': |
1934 | /* If constant, low-order 16 bits of constant, signed. Otherwise, write | |
1935 | normally. */ | |
1936 | if (INT_P (x)) | |
1937 | fprintf (file, "%d", | |
1938 | (INT_LOWPART (x) & 0xffff) - 2 * (INT_LOWPART (x) & 0x8000)); | |
1939 | else | |
1940 | print_operand (file, x, 0); | |
9878760c RK |
1941 | return; |
1942 | ||
9854d9ed RK |
1943 | case 'W': |
1944 | /* If constant, low-order 16 bits of constant, unsigned. | |
1945 | Otherwise, write normally. */ | |
1946 | if (INT_P (x)) | |
1947 | fprintf (file, "%d", INT_LOWPART (x) & 0xffff); | |
1948 | else | |
1949 | print_operand (file, x, 0); | |
1950 | return; | |
9878760c | 1951 | |
9854d9ed RK |
1952 | case 'X': |
1953 | if (GET_CODE (x) == MEM | |
1954 | && LEGITIMATE_INDEXED_ADDRESS_P (XEXP (x, 0))) | |
76229ac8 | 1955 | putc ('x', file); |
9854d9ed | 1956 | return; |
9878760c | 1957 | |
9854d9ed RK |
1958 | case 'Y': |
1959 | /* Like 'L', for third word of TImode */ | |
1960 | if (GET_CODE (x) == REG) | |
1961 | fprintf (file, "%d", REGNO (x) + 2); | |
1962 | else if (GET_CODE (x) == MEM) | |
9878760c | 1963 | { |
9854d9ed RK |
1964 | if (GET_CODE (XEXP (x, 0)) == PRE_INC |
1965 | || GET_CODE (XEXP (x, 0)) == PRE_DEC) | |
1966 | output_address (plus_constant (XEXP (XEXP (x, 0), 0), 8)); | |
1967 | else | |
1968 | output_address (plus_constant (XEXP (x, 0), 8)); | |
9878760c RK |
1969 | } |
1970 | return; | |
9854d9ed | 1971 | |
9878760c | 1972 | case 'z': |
b4ac57ab RS |
1973 | /* X is a SYMBOL_REF. Write out the name preceded by a |
1974 | period and without any trailing data in brackets. Used for function | |
4d30c363 MM |
1975 | names. If we are configured for System V (or the embedded ABI) on |
1976 | the PowerPC, do not emit the period, since those systems do not use | |
1977 | TOCs and the like. */ | |
9878760c RK |
1978 | if (GET_CODE (x) != SYMBOL_REF) |
1979 | abort (); | |
1980 | ||
4d30c363 | 1981 | #ifndef USING_SVR4_H |
76229ac8 | 1982 | putc ('.', file); |
4d30c363 | 1983 | #endif |
9878760c RK |
1984 | RS6000_OUTPUT_BASENAME (file, XSTR (x, 0)); |
1985 | return; | |
1986 | ||
9854d9ed RK |
1987 | case 'Z': |
1988 | /* Like 'L', for last word of TImode. */ | |
1989 | if (GET_CODE (x) == REG) | |
1990 | fprintf (file, "%d", REGNO (x) + 3); | |
1991 | else if (GET_CODE (x) == MEM) | |
1992 | { | |
1993 | if (GET_CODE (XEXP (x, 0)) == PRE_INC | |
1994 | || GET_CODE (XEXP (x, 0)) == PRE_DEC) | |
1995 | output_address (plus_constant (XEXP (XEXP (x, 0), 0), 12)); | |
1996 | else | |
1997 | output_address (plus_constant (XEXP (x, 0), 12)); | |
1998 | } | |
5c23c401 | 1999 | return; |
9854d9ed | 2000 | |
9878760c RK |
2001 | case 0: |
2002 | if (GET_CODE (x) == REG) | |
2003 | fprintf (file, "%s", reg_names[REGNO (x)]); | |
2004 | else if (GET_CODE (x) == MEM) | |
2005 | { | |
2006 | /* We need to handle PRE_INC and PRE_DEC here, since we need to | |
2007 | know the width from the mode. */ | |
2008 | if (GET_CODE (XEXP (x, 0)) == PRE_INC) | |
2009 | fprintf (file, "%d(%d)", GET_MODE_SIZE (GET_MODE (x)), | |
2010 | REGNO (XEXP (XEXP (x, 0), 0))); | |
2011 | else if (GET_CODE (XEXP (x, 0)) == PRE_DEC) | |
2012 | fprintf (file, "%d(%d)", - GET_MODE_SIZE (GET_MODE (x)), | |
2013 | REGNO (XEXP (XEXP (x, 0), 0))); | |
2014 | else | |
2015 | output_address (XEXP (x, 0)); | |
2016 | } | |
2017 | else | |
2018 | output_addr_const (file, x); | |
a85d226b | 2019 | return; |
9878760c RK |
2020 | |
2021 | default: | |
2022 | output_operand_lossage ("invalid %%xn code"); | |
2023 | } | |
2024 | } | |
2025 | \f | |
2026 | /* Print the address of an operand. */ | |
2027 | ||
2028 | void | |
2029 | print_operand_address (file, x) | |
2030 | FILE *file; | |
2031 | register rtx x; | |
2032 | { | |
2033 | if (GET_CODE (x) == REG) | |
4697a36c | 2034 | fprintf (file, "0(%s)", reg_names[ REGNO (x) ]); |
9878760c RK |
2035 | else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST) |
2036 | { | |
2037 | output_addr_const (file, x); | |
1875cc88 JW |
2038 | /* When TARGET_MINIMAL_TOC, use the indirected toc table pointer instead |
2039 | of the toc pointer. */ | |
4697a36c MM |
2040 | #ifdef TARGET_NO_TOC |
2041 | if (TARGET_NO_TOC) | |
2042 | ; | |
1875cc88 | 2043 | else |
4697a36c MM |
2044 | #endif |
2045 | fprintf (file, "(%s)", reg_names[ TARGET_MINIMAL_TOC ? 30 : 2 ]); | |
9878760c RK |
2046 | } |
2047 | else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == REG) | |
2048 | { | |
2049 | if (REGNO (XEXP (x, 0)) == 0) | |
4697a36c MM |
2050 | fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 1)) ], |
2051 | reg_names[ REGNO (XEXP (x, 0)) ]); | |
9878760c | 2052 | else |
4697a36c MM |
2053 | fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 0)) ], |
2054 | reg_names[ REGNO (XEXP (x, 1)) ]); | |
9878760c RK |
2055 | } |
2056 | else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT) | |
4697a36c MM |
2057 | fprintf (file, "%d(%s)", INTVAL (XEXP (x, 1)), reg_names[ REGNO (XEXP (x, 0)) ]); |
2058 | else if (TARGET_ELF && !TARGET_64BIT && GET_CODE (x) == LO_SUM | |
2059 | && GET_CODE (XEXP (x, 0)) == REG && CONSTANT_P (XEXP (x, 1))) | |
2060 | { | |
2061 | output_addr_const (file, XEXP (x, 1)); | |
2062 | fprintf (file, "@l(%s)", reg_names[ REGNO (XEXP (x, 0)) ]); | |
2063 | } | |
9878760c RK |
2064 | else |
2065 | abort (); | |
2066 | } | |
2067 | \f | |
2068 | /* This page contains routines that are used to determine what the function | |
2069 | prologue and epilogue code will do and write them out. */ | |
2070 | ||
2071 | /* Return the first fixed-point register that is required to be saved. 32 if | |
2072 | none. */ | |
2073 | ||
2074 | int | |
2075 | first_reg_to_save () | |
2076 | { | |
2077 | int first_reg; | |
2078 | ||
2079 | /* Find lowest numbered live register. */ | |
2080 | for (first_reg = 13; first_reg <= 31; first_reg++) | |
2081 | if (regs_ever_live[first_reg]) | |
2082 | break; | |
2083 | ||
e165f3f0 RK |
2084 | /* If profiling, then we must save/restore every register that contains |
2085 | a parameter before/after the .mcount call. Use registers from 30 down | |
2086 | to 23 to do this. Don't use the frame pointer in reg 31. | |
2087 | ||
2088 | For now, save enough room for all of the parameter registers. */ | |
4697a36c | 2089 | #ifndef USING_SVR4_H |
e165f3f0 RK |
2090 | if (profile_flag) |
2091 | if (first_reg > 23) | |
2092 | first_reg = 23; | |
4697a36c | 2093 | #endif |
e165f3f0 | 2094 | |
9878760c RK |
2095 | return first_reg; |
2096 | } | |
2097 | ||
2098 | /* Similar, for FP regs. */ | |
2099 | ||
2100 | int | |
2101 | first_fp_reg_to_save () | |
2102 | { | |
2103 | int first_reg; | |
2104 | ||
2105 | /* Find lowest numbered live register. */ | |
2106 | for (first_reg = 14 + 32; first_reg <= 63; first_reg++) | |
2107 | if (regs_ever_live[first_reg]) | |
2108 | break; | |
2109 | ||
2110 | return first_reg; | |
2111 | } | |
2112 | ||
9878760c RK |
2113 | /* Return non-zero if this function makes calls. */ |
2114 | ||
2115 | int | |
2116 | rs6000_makes_calls () | |
2117 | { | |
2118 | rtx insn; | |
2119 | ||
0c61c946 RK |
2120 | /* If we are profiling, we will be making a call to mcount. */ |
2121 | if (profile_flag) | |
2122 | return 1; | |
2123 | ||
9878760c RK |
2124 | for (insn = get_insns (); insn; insn = next_insn (insn)) |
2125 | if (GET_CODE (insn) == CALL_INSN) | |
2126 | return 1; | |
2127 | ||
2128 | return 0; | |
2129 | } | |
2130 | ||
4697a36c MM |
2131 | \f |
2132 | /* Calculate the stack information for the current function. This is | |
2133 | complicated by having two separate calling sequences, the AIX calling | |
2134 | sequence and the V.4 calling sequence. | |
2135 | ||
2136 | AIX stack frames look like: | |
2137 | ||
2138 | SP----> +---------------------------------------+ | |
2139 | | back chain to caller | 0 | |
2140 | +---------------------------------------+ | |
2141 | | saved CR | 4 | |
2142 | +---------------------------------------+ | |
2143 | | saved LR | 8 | |
2144 | +---------------------------------------+ | |
2145 | | reserved for compilers | 12 | |
2146 | +---------------------------------------+ | |
2147 | | reserved for binders | 16 | |
2148 | +---------------------------------------+ | |
2149 | | saved TOC pointer | 20 | |
2150 | +---------------------------------------+ | |
2151 | | Parameter save area (P) | 24 | |
2152 | +---------------------------------------+ | |
2153 | | Alloca space (A) | 24+P | |
2154 | +---------------------------------------+ | |
2155 | | Local variable space (L) | 24+P+A | |
2156 | +---------------------------------------+ | |
2157 | | Save area for GP registers (G) | 24+P+A+L | |
2158 | +---------------------------------------+ | |
2159 | | Save area for FP registers (F) | 24+P+A+L+G | |
2160 | +---------------------------------------+ | |
2161 | old SP->| back chain to caller's caller | | |
2162 | +---------------------------------------+ | |
2163 | ||
2164 | V.4 stack frames look like: | |
2165 | ||
2166 | SP----> +---------------------------------------+ | |
2167 | | back chain to caller | 0 | |
2168 | +---------------------------------------+ | |
5eb387b8 | 2169 | | caller's saved LR | 4 |
4697a36c MM |
2170 | +---------------------------------------+ |
2171 | | Parameter save area (P) | 8 | |
2172 | +---------------------------------------+ | |
2173 | | Alloca space (A) | 8+P | |
2174 | +---------------------------------------+ | |
2175 | | Varargs save area (V) | 8+P+A | |
2176 | +---------------------------------------+ | |
2177 | | Local variable space (L) | 8+P+A+V | |
2178 | +---------------------------------------+ | |
2179 | | saved CR (C) | 8+P+A+V+L | |
2180 | +---------------------------------------+ | |
2181 | | Save area for GP registers (G) | 8+P+A+V+L+C | |
2182 | +---------------------------------------+ | |
2183 | | Save area for FP registers (F) | 8+P+A+V+L+C+G | |
2184 | +---------------------------------------+ | |
2185 | old SP->| back chain to caller's caller | | |
2186 | +---------------------------------------+ | |
2187 | */ | |
2188 | ||
2189 | rs6000_stack_t * | |
2190 | rs6000_stack_info () | |
2191 | { | |
2192 | static rs6000_stack_t info, zero_info; | |
2193 | rs6000_stack_t *info_ptr = &info; | |
2194 | int reg_size = TARGET_64BIT ? 8 : 4; | |
2195 | int v4_call_p = 0; | |
2196 | ||
2197 | /* Zero all fields portably */ | |
2198 | info = zero_info; | |
2199 | ||
2200 | /* Select which calling sequence */ | |
2201 | #ifdef TARGET_V4_CALLS | |
2202 | if (TARGET_V4_CALLS) | |
2203 | info_ptr->v4_call_p = v4_call_p = 1; | |
2204 | #endif | |
9878760c | 2205 | |
4697a36c MM |
2206 | /* Calculate which registers need to be saved & save area size */ |
2207 | info_ptr->first_gp_reg_save = first_reg_to_save (); | |
2208 | info_ptr->gp_size = reg_size * (32 - info_ptr->first_gp_reg_save); | |
2209 | ||
2210 | info_ptr->first_fp_reg_save = first_fp_reg_to_save (); | |
2211 | info_ptr->fp_size = 8 * (64 - info_ptr->first_fp_reg_save); | |
2212 | ||
2213 | /* Does this function call anything? */ | |
2214 | info_ptr->calls_p = rs6000_makes_calls (); | |
2215 | ||
2216 | /* Determine if we need to save the link register */ | |
2217 | if (regs_ever_live[65] || profile_flag | |
2218 | #ifdef TARGET_RELOCATABLE | |
2219 | || (TARGET_RELOCATABLE && (get_pool_size () != 0)) | |
2220 | #endif | |
2221 | || (info_ptr->first_fp_reg_save != 64 | |
2222 | && !FP_SAVE_INLINE (info_ptr->first_fp_reg_save)) | |
2223 | || (v4_call_p && current_function_calls_alloca) | |
2224 | || info_ptr->calls_p) | |
2225 | { | |
2226 | info_ptr->lr_save_p = 1; | |
2227 | regs_ever_live[65] = 1; | |
2228 | } | |
2229 | ||
2230 | /* Determine if we need to save the condition code registers */ | |
2231 | if (regs_ever_live[70] || regs_ever_live[71] || regs_ever_live[72]) | |
2232 | { | |
2233 | info_ptr->cr_save_p = 1; | |
2234 | if (v4_call_p) | |
2235 | info_ptr->cr_size = reg_size; | |
2236 | } | |
2237 | ||
2238 | /* Determine various sizes */ | |
2239 | info_ptr->reg_size = reg_size; | |
2240 | info_ptr->fixed_size = RS6000_SAVE_AREA; | |
2241 | info_ptr->varargs_size = RS6000_VARARGS_AREA; | |
2242 | info_ptr->vars_size = ALIGN (get_frame_size (), 8); | |
2243 | info_ptr->parm_size = ALIGN (current_function_outgoing_args_size, 8); | |
2244 | info_ptr->save_size = ALIGN (info_ptr->fp_size + info_ptr->gp_size + info_ptr->cr_size, 8); | |
2245 | info_ptr->total_size = ALIGN (info_ptr->vars_size | |
2246 | + info_ptr->parm_size | |
2247 | + info_ptr->save_size | |
2248 | + info_ptr->varargs_size | |
2249 | + info_ptr->fixed_size, STACK_BOUNDARY / BITS_PER_UNIT); | |
2250 | ||
2251 | /* Determine if we need to allocate any stack frame. | |
2252 | For AIX We need to push the stack if a frame pointer is needed (because | |
2253 | the stack might be dynamically adjusted), if we are debugging, if the | |
2254 | total stack size is more than 220 bytes, or if we make calls. | |
2255 | ||
2256 | For V.4 we don't have the stack cushion that AIX uses, but assume that | |
2257 | the debugger can handle stackless frames. */ | |
2258 | ||
2259 | if (info_ptr->calls_p) | |
2260 | info_ptr->push_p = 1; | |
2261 | ||
2262 | else if (v4_call_p) | |
2263 | info_ptr->push_p = (info_ptr->total_size > info_ptr->fixed_size | |
2264 | || info_ptr->lr_save_p); | |
2265 | ||
2266 | else | |
2267 | info_ptr->push_p = (frame_pointer_needed | |
2268 | || write_symbols != NO_DEBUG | |
2269 | || info_ptr->total_size > 220); | |
2270 | ||
2271 | /* Calculate the offsets */ | |
2272 | info_ptr->fp_save_offset = - info_ptr->fp_size; | |
2273 | info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size; | |
2274 | if (v4_call_p) | |
2275 | { | |
2276 | info_ptr->cr_save_offset = info_ptr->gp_save_offset - reg_size; | |
5eb387b8 | 2277 | info_ptr->lr_save_offset = reg_size; |
4697a36c MM |
2278 | } |
2279 | else | |
2280 | { | |
2281 | info_ptr->cr_save_offset = 4; | |
2282 | info_ptr->lr_save_offset = 8; | |
2283 | } | |
2284 | ||
2285 | /* Zero offsets if we're not saving those registers */ | |
2286 | if (!info_ptr->fp_size) | |
2287 | info_ptr->fp_save_offset = 0; | |
2288 | ||
2289 | if (!info_ptr->gp_size) | |
2290 | info_ptr->gp_save_offset = 0; | |
2291 | ||
2292 | if (!info_ptr->lr_save_p) | |
2293 | info_ptr->lr_save_offset = 0; | |
2294 | ||
2295 | if (!info_ptr->cr_save_p) | |
2296 | info_ptr->cr_save_offset = 0; | |
2297 | ||
2298 | return info_ptr; | |
2299 | } | |
2300 | ||
2301 | void | |
2302 | debug_stack_info (info) | |
2303 | rs6000_stack_t *info; | |
9878760c | 2304 | { |
4697a36c MM |
2305 | if (!info) |
2306 | info = rs6000_stack_info (); | |
2307 | ||
2308 | fprintf (stderr, "\nStack information for function %s:\n", | |
2309 | ((current_function_decl && DECL_NAME (current_function_decl)) | |
2310 | ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl)) | |
2311 | : "<unknown>")); | |
2312 | ||
2313 | if (info->first_gp_reg_save != 32) | |
2314 | fprintf (stderr, "\tfirst_gp_reg_save = %5d\n", info->first_gp_reg_save); | |
2315 | ||
2316 | if (info->first_fp_reg_save != 64) | |
2317 | fprintf (stderr, "\tfirst_fp_reg_save = %5d\n", info->first_fp_reg_save); | |
9878760c | 2318 | |
4697a36c MM |
2319 | if (info->lr_save_p) |
2320 | fprintf (stderr, "\tlr_save_p = %5d\n", info->lr_save_p); | |
9878760c | 2321 | |
4697a36c MM |
2322 | if (info->cr_save_p) |
2323 | fprintf (stderr, "\tcr_save_p = %5d\n", info->cr_save_p); | |
2324 | ||
2325 | if (info->push_p) | |
2326 | fprintf (stderr, "\tpush_p = %5d\n", info->push_p); | |
2327 | ||
2328 | if (info->calls_p) | |
2329 | fprintf (stderr, "\tcalls_p = %5d\n", info->calls_p); | |
2330 | ||
2331 | if (info->v4_call_p) | |
2332 | fprintf (stderr, "\tv4_call_p = %5d\n", info->v4_call_p); | |
2333 | ||
2334 | if (info->gp_save_offset) | |
2335 | fprintf (stderr, "\tgp_save_offset = %5d\n", info->gp_save_offset); | |
2336 | ||
2337 | if (info->fp_save_offset) | |
2338 | fprintf (stderr, "\tfp_save_offset = %5d\n", info->fp_save_offset); | |
2339 | ||
2340 | if (info->lr_save_offset) | |
2341 | fprintf (stderr, "\tlr_save_offset = %5d\n", info->lr_save_offset); | |
2342 | ||
2343 | if (info->cr_save_offset) | |
2344 | fprintf (stderr, "\tcr_save_offset = %5d\n", info->cr_save_offset); | |
2345 | ||
2346 | if (info->varargs_save_offset) | |
2347 | fprintf (stderr, "\tvarargs_save_offset = %5d\n", info->varargs_save_offset); | |
2348 | ||
2349 | if (info->total_size) | |
2350 | fprintf (stderr, "\ttotal_size = %5d\n", info->total_size); | |
2351 | ||
2352 | if (info->varargs_size) | |
2353 | fprintf (stderr, "\tvarargs_size = %5d\n", info->varargs_size); | |
2354 | ||
2355 | if (info->vars_size) | |
2356 | fprintf (stderr, "\tvars_size = %5d\n", info->vars_size); | |
2357 | ||
2358 | if (info->parm_size) | |
2359 | fprintf (stderr, "\tparm_size = %5d\n", info->parm_size); | |
2360 | ||
2361 | if (info->fixed_size) | |
2362 | fprintf (stderr, "\tfixed_size = %5d\n", info->fixed_size); | |
2363 | ||
2364 | if (info->gp_size) | |
2365 | fprintf (stderr, "\tgp_size = %5d\n", info->gp_size); | |
2366 | ||
2367 | if (info->fp_size) | |
2368 | fprintf (stderr, "\tfp_size = %5d\n", info->fp_size); | |
2369 | ||
2370 | if (info->cr_size) | |
2371 | fprintf (stderr, "\tcr_size = %5d\n", info->cr_size); | |
2372 | ||
2373 | if (info->save_size) | |
2374 | fprintf (stderr, "\tsave_size = %5d\n", info->save_size); | |
2375 | ||
2376 | if (info->reg_size != 4) | |
2377 | fprintf (stderr, "\treg_size = %5d\n", info->reg_size); | |
2378 | ||
2379 | fprintf (stderr, "\n"); | |
9878760c RK |
2380 | } |
2381 | ||
4697a36c MM |
2382 | \f |
2383 | ||
4d30c363 MM |
2384 | #ifdef USING_SVR4_H |
2385 | /* Write out a System V.4 style traceback table before the prologue | |
2386 | ||
2387 | At present, only emit the basic tag table (ie, do not emit tag_types other | |
2388 | than 0, which might use more than 1 tag word). | |
2389 | ||
2390 | The first tag word looks like: | |
2391 | ||
2392 | 0 1 2 3 | |
2393 | 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 | |
2394 | +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | |
2395 | | 0 |ver| tag |e|s| alloca | # fprs | # gprs |s|l|c|f| | |
2396 | +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | |
2397 | ||
2398 | */ | |
2399 | ||
2400 | void | |
2401 | svr4_traceback (file, name, decl) | |
2402 | FILE *file; | |
2403 | tree name, decl; | |
2404 | { | |
4697a36c | 2405 | rs6000_stack_t *info = rs6000_stack_info (); |
4d30c363 | 2406 | long tag; |
4697a36c MM |
2407 | long version = 0; /* version number */ |
2408 | long tag_type = 0; /* function type */ | |
2409 | long extended_tag = 0; /* additional tag words needed */ | |
2410 | long spare = 0; /* reserved for future use */ | |
2411 | long fpscr_max = 0; /* 1 if the function has a FPSCR save word */ | |
2412 | long fpr_max = 64 - info->first_fp_reg_save; /* # of floating point registers saved */ | |
2413 | long gpr_max = 32 - info->first_gp_reg_save; /* # of general purpose registers saved */ | |
2414 | long alloca_reg; /* stack/frame register */ | |
4d30c363 MM |
2415 | |
2416 | if (frame_pointer_needed) | |
2417 | alloca_reg = 31; | |
2418 | ||
4697a36c | 2419 | else if (info->push_p != 0) |
4d30c363 MM |
2420 | alloca_reg = 1; |
2421 | ||
2422 | else | |
2423 | alloca_reg = 0; | |
2424 | ||
4697a36c MM |
2425 | tag = ((version << 24) |
2426 | | (tag_type << 21) | |
2427 | | (extended_tag << 20) | |
2428 | | (spare << 19) | |
2429 | | (alloca_reg << 14) | |
2430 | | (fpr_max << 9) | |
2431 | | (gpr_max << 4) | |
2432 | | (info->push_p << 3) | |
2433 | | (info->lr_save_p << 2) | |
2434 | | (info->cr_save_p << 1) | |
2435 | | (fpscr_max << 0)); | |
4d30c363 MM |
2436 | |
2437 | fprintf (file, "\t.long 0x%lx\n", tag); | |
2438 | } | |
2439 | ||
2440 | #endif /* USING_SVR4_H */ | |
4697a36c | 2441 | \f |
9878760c | 2442 | /* Write function prologue. */ |
9878760c RK |
2443 | void |
2444 | output_prolog (file, size) | |
2445 | FILE *file; | |
2446 | int size; | |
2447 | { | |
4697a36c MM |
2448 | rs6000_stack_t *info = rs6000_stack_info (); |
2449 | char *store_reg = (TARGET_64BIT) ? "\tstd %s,%d(%s)" : "\t{st|stw} %s,%d(%s)\n"; | |
9878760c | 2450 | |
4697a36c MM |
2451 | if (TARGET_DEBUG_STACK) |
2452 | debug_stack_info (info); | |
9878760c RK |
2453 | |
2454 | /* Write .extern for any function we will call to save and restore fp | |
2455 | values. */ | |
bacbde18 | 2456 | #ifndef USING_SVR4_H |
4697a36c | 2457 | if (info->first_fp_reg_save < 62) |
4d30c363 | 2458 | fprintf (file, "\t.extern %s%d%s\n\t.extern %s%d%s\n", |
4697a36c MM |
2459 | SAVE_FP_PREFIX, info->first_fp_reg_save - 32, SAVE_FP_SUFFIX, |
2460 | RESTORE_FP_PREFIX, info->first_fp_reg_save - 32, RESTORE_FP_SUFFIX); | |
bacbde18 | 2461 | #endif |
9878760c RK |
2462 | |
2463 | /* Write .extern for truncation routines, if needed. */ | |
2464 | if (rs6000_trunc_used && ! trunc_defined) | |
2465 | { | |
e138174b ILT |
2466 | fprintf (file, "\t.extern .%s\n\t.extern .%s\n", |
2467 | RS6000_ITRUNC, RS6000_UITRUNC); | |
9878760c RK |
2468 | trunc_defined = 1; |
2469 | } | |
4697a36c | 2470 | |
c764f757 RK |
2471 | /* Write .extern for AIX common mode routines, if needed. */ |
2472 | if (! TARGET_POWER && ! TARGET_POWERPC && ! common_mode_defined) | |
2473 | { | |
f6709c70 JW |
2474 | fputs ("\t.extern __mulh\n", file); |
2475 | fputs ("\t.extern __mull\n", file); | |
2476 | fputs ("\t.extern __divss\n", file); | |
2477 | fputs ("\t.extern __divus\n", file); | |
2478 | fputs ("\t.extern __quoss\n", file); | |
2479 | fputs ("\t.extern __quous\n", file); | |
c764f757 RK |
2480 | common_mode_defined = 1; |
2481 | } | |
9878760c | 2482 | |
9878760c | 2483 | /* If we use the link register, get it into r0. */ |
4697a36c MM |
2484 | if (info->lr_save_p) |
2485 | asm_fprintf (file, "\tmflr %s\n", reg_names[0]); | |
9878760c RK |
2486 | |
2487 | /* If we need to save CR, put it into r12. */ | |
4697a36c MM |
2488 | if (info->cr_save_p) |
2489 | asm_fprintf (file, "\tmfcr %s\n", reg_names[12]); | |
9878760c RK |
2490 | |
2491 | /* Do any required saving of fpr's. If only one or two to save, do it | |
53322b0c RK |
2492 | ourself. Otherwise, call function. Note that since they are statically |
2493 | linked, we do not need a nop following them. */ | |
4697a36c | 2494 | if (FP_SAVE_INLINE (info->first_fp_reg_save)) |
bacbde18 | 2495 | { |
4697a36c MM |
2496 | int regno = info->first_fp_reg_save; |
2497 | int loc = info->fp_save_offset; | |
2498 | ||
2499 | for ( ; regno < 64; regno++, loc += 8) | |
2500 | asm_fprintf (file, "\tstfd %s,%d(%s)\n", reg_names[regno], loc, reg_names[1]); | |
bacbde18 | 2501 | } |
4697a36c MM |
2502 | else if (info->first_fp_reg_save != 64) |
2503 | asm_fprintf (file, "\tbl %s%d%s\n", SAVE_FP_PREFIX, | |
2504 | info->first_fp_reg_save - 32, SAVE_FP_SUFFIX); | |
9878760c RK |
2505 | |
2506 | /* Now save gpr's. */ | |
4697a36c | 2507 | if (! TARGET_MULTIPLE || info->first_gp_reg_save == 31 || TARGET_64BIT) |
85638c0d | 2508 | { |
4697a36c MM |
2509 | int regno = info->first_gp_reg_save; |
2510 | int loc = info->gp_save_offset; | |
2511 | int reg_size = (TARGET_64BIT) ? 8 : 4; | |
85638c0d | 2512 | |
4697a36c MM |
2513 | for ( ; regno < 32; regno++, loc += reg_size) |
2514 | asm_fprintf (file, store_reg, reg_names[regno], loc, reg_names[1]); | |
85638c0d RK |
2515 | } |
2516 | ||
4697a36c MM |
2517 | else if (info->first_gp_reg_save != 32) |
2518 | asm_fprintf (file, "\t{stm|stmw} %s,%d(%s)\n", | |
2519 | reg_names[info->first_gp_reg_save], | |
2520 | info->gp_save_offset, | |
2521 | reg_names[1]); | |
9878760c RK |
2522 | |
2523 | /* Save lr if we used it. */ | |
4697a36c MM |
2524 | if (info->lr_save_p) |
2525 | asm_fprintf (file, store_reg, reg_names[0], info->lr_save_offset, reg_names[1]); | |
9878760c RK |
2526 | |
2527 | /* Save CR if we use any that must be preserved. */ | |
4697a36c MM |
2528 | if (info->cr_save_p) |
2529 | asm_fprintf (file, store_reg, reg_names[12], info->cr_save_offset, reg_names[1]); | |
9878760c RK |
2530 | |
2531 | /* Update stack and set back pointer. */ | |
4697a36c | 2532 | if (info->push_p) |
9878760c | 2533 | { |
4697a36c MM |
2534 | if (info->total_size < 32767) |
2535 | asm_fprintf (file, | |
2536 | (TARGET_64BIT) ? "\tstdu %s,%d(%s)\n" : "\t{stu|stwu} %s,%d(%s)\n", | |
2537 | reg_names[1], - info->total_size, reg_names[1]); | |
9878760c RK |
2538 | else |
2539 | { | |
4697a36c MM |
2540 | asm_fprintf (file, "\t{liu|lis} %s,%d\n\t{oril|ori} %s,%s,%d\n", |
2541 | reg_names[0], (info->total_size >> 16) & 0xffff, | |
2542 | reg_names[0], reg_names[0], info->total_size & 0xffff); | |
2543 | asm_fprintf (file, | |
2544 | (TARGET_64BIT) ? "\tstdux %s,%s,%s\n" : "\tstwux %s,%s,%s\n", | |
2545 | reg_names[1], reg_names[1], reg_names[0]); | |
9878760c RK |
2546 | } |
2547 | } | |
2548 | ||
2549 | /* Set frame pointer, if needed. */ | |
2550 | if (frame_pointer_needed) | |
4697a36c | 2551 | asm_fprintf (file, "\tmr %s,%s\n", reg_names[31], reg_names[1]); |
1875cc88 JW |
2552 | |
2553 | /* If TARGET_MINIMAL_TOC, and the constant pool is needed, then load the | |
2554 | TOC_TABLE address into register 30. */ | |
4697a36c | 2555 | if (TARGET_TOC && TARGET_MINIMAL_TOC && get_pool_size () != 0) |
3daf36a4 | 2556 | { |
d14a6d05 MM |
2557 | char buf[256]; |
2558 | ||
2559 | #ifdef USING_SVR4_H | |
2560 | if (TARGET_RELOCATABLE) | |
2561 | { | |
874a0744 | 2562 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno); |
d14a6d05 MM |
2563 | fprintf (file, "\tbl "); |
2564 | assemble_name (file, buf); | |
2565 | fprintf (file, "\n"); | |
2566 | ||
874a0744 | 2567 | ASM_OUTPUT_INTERNAL_LABEL (file, "LCF", rs6000_pic_labelno); |
4697a36c | 2568 | fprintf (file, "\tmflr %s\n", reg_names[30]); |
3daf36a4 | 2569 | |
874a0744 | 2570 | if (TARGET_POWERPC64) |
4697a36c | 2571 | fprintf (file, "\tld"); |
874a0744 | 2572 | else if (TARGET_NEW_MNEMONICS) |
4697a36c | 2573 | fprintf (file, "\tlwz"); |
874a0744 | 2574 | else |
4697a36c | 2575 | fprintf (file, "\tl"); |
874a0744 | 2576 | |
4697a36c | 2577 | fprintf (file, " %s,(", reg_names[0]); |
874a0744 MM |
2578 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno); |
2579 | assemble_name (file, buf); | |
2580 | fprintf (file, "-"); | |
2581 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno); | |
2582 | assemble_name (file, buf); | |
4697a36c MM |
2583 | fprintf (file, ")(%s)\n", reg_names[30]); |
2584 | asm_fprintf (file, "\t{cax|add} %s,%s,%s\n", | |
2585 | reg_names[30], reg_names[0], reg_names[30]); | |
874a0744 | 2586 | rs6000_pic_labelno++; |
d14a6d05 | 2587 | } |
4697a36c | 2588 | else if (!TARGET_64BIT) |
3933e0e1 MM |
2589 | { |
2590 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1); | |
4697a36c | 2591 | asm_fprintf (file, "\t{cau|addis} %s,%s,", reg_names[30], reg_names[0]); |
3933e0e1 MM |
2592 | assemble_name (file, buf); |
2593 | asm_fprintf (file, "@ha\n"); | |
4697a36c MM |
2594 | if (TARGET_NEW_MNEMONICS) |
2595 | { | |
2596 | asm_fprintf (file, "\taddi %s,%s,", reg_names[30], reg_names[30]); | |
2597 | assemble_name (file, buf); | |
2598 | asm_fprintf (file, "@l\n"); | |
2599 | } | |
2600 | else | |
2601 | { | |
2602 | asm_fprintf (file, "\tcal %s,", reg_names[30]); | |
2603 | assemble_name (file, buf); | |
2604 | asm_fprintf (file, "@l(%s)\n", reg_names[30]); | |
2605 | } | |
3933e0e1 | 2606 | } |
d14a6d05 | 2607 | else |
4697a36c MM |
2608 | abort (); |
2609 | ||
2610 | #else /* !USING_SVR4_H */ | |
2611 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 0); | |
2612 | asm_fprintf (file, "\t{l|lwz} %s,", reg_names[30]); | |
2613 | assemble_name (file, buf); | |
2614 | asm_fprintf (file, "(%s)\n", reg_names[2]); | |
d14a6d05 | 2615 | #endif /* USING_SVR4_H */ |
3daf36a4 | 2616 | } |
9878760c RK |
2617 | } |
2618 | ||
2619 | /* Write function epilogue. */ | |
2620 | ||
2621 | void | |
2622 | output_epilog (file, size) | |
2623 | FILE *file; | |
2624 | int size; | |
2625 | { | |
4697a36c MM |
2626 | rs6000_stack_t *info = rs6000_stack_info (); |
2627 | char *load_reg = (TARGET_64BIT) ? "\tld %s,%d(%s)" : "\t{l|lwz} %s,%d(%s)\n"; | |
9878760c RK |
2628 | rtx insn = get_last_insn (); |
2629 | ||
9878760c RK |
2630 | /* If the last insn was a BARRIER, we don't have to write anything except |
2631 | the trace table. */ | |
2632 | if (GET_CODE (insn) == NOTE) | |
2633 | insn = prev_nonnote_insn (insn); | |
2634 | if (insn == 0 || GET_CODE (insn) != BARRIER) | |
2635 | { | |
2636 | /* If we have a frame pointer, a call to alloca, or a large stack | |
2637 | frame, restore the old stack pointer using the backchain. Otherwise, | |
2638 | we know what size to update it with. */ | |
2639 | if (frame_pointer_needed || current_function_calls_alloca | |
4697a36c MM |
2640 | || info->total_size > 32767) |
2641 | asm_fprintf (file, load_reg, reg_names[1], 0, reg_names[1]); | |
2642 | else if (info->push_p) | |
2643 | { | |
2644 | if (TARGET_NEW_MNEMONICS) | |
2645 | asm_fprintf (file, "\taddi %s,%s,%d\n", reg_names[1], reg_names[1], info->total_size); | |
2646 | else | |
2647 | asm_fprintf (file, "\tcal %s,%d(%s)\n", reg_names[1], info->total_size, reg_names[1]); | |
2648 | } | |
9878760c | 2649 | |
b4ac57ab | 2650 | /* Get the old lr if we saved it. */ |
4697a36c MM |
2651 | if (info->lr_save_p) |
2652 | asm_fprintf (file, load_reg, reg_names[0], info->lr_save_offset, reg_names[1]); | |
9878760c RK |
2653 | |
2654 | /* Get the old cr if we saved it. */ | |
4697a36c MM |
2655 | if (info->cr_save_p) |
2656 | asm_fprintf (file, load_reg, reg_names[12], info->cr_save_offset, reg_names[1]); | |
9878760c | 2657 | |
b4ac57ab | 2658 | /* Set LR here to try to overlap restores below. */ |
4697a36c MM |
2659 | if (info->lr_save_p) |
2660 | asm_fprintf (file, "\tmtlr %s\n", reg_names[0]); | |
b4ac57ab | 2661 | |
9878760c | 2662 | /* Restore gpr's. */ |
4697a36c | 2663 | if (! TARGET_MULTIPLE || info->first_gp_reg_save == 31 || TARGET_64BIT) |
85638c0d | 2664 | { |
4697a36c MM |
2665 | int regno = info->first_gp_reg_save; |
2666 | int loc = info->gp_save_offset; | |
2667 | int reg_size = (TARGET_64BIT) ? 8 : 4; | |
85638c0d | 2668 | |
4697a36c MM |
2669 | for ( ; regno < 32; regno++, loc += reg_size) |
2670 | asm_fprintf (file, load_reg, reg_names[regno], loc, reg_names[1]); | |
85638c0d RK |
2671 | } |
2672 | ||
4697a36c MM |
2673 | else if (info->first_gp_reg_save != 32) |
2674 | asm_fprintf (file, "\t{lm|lmw} %s,%d(%s)\n", | |
2675 | reg_names[info->first_gp_reg_save], | |
2676 | info->gp_save_offset, | |
2677 | reg_names[1]); | |
9878760c | 2678 | |
b4ac57ab | 2679 | /* Restore fpr's if we can do it without calling a function. */ |
4697a36c MM |
2680 | if (FP_SAVE_INLINE (info->first_fp_reg_save)) |
2681 | { | |
2682 | int regno = info->first_fp_reg_save; | |
2683 | int loc = info->fp_save_offset; | |
2684 | ||
2685 | for ( ; regno < 64; regno++, loc += 8) | |
2686 | asm_fprintf (file, "\tlfd %s,%d(%s)\n", reg_names[regno], loc, reg_names[1]); | |
2687 | } | |
9878760c | 2688 | |
28edebac RK |
2689 | /* If we saved cr, restore it here. Just those of cr2, cr3, and cr4 |
2690 | that were used. */ | |
4697a36c MM |
2691 | if (info->cr_save_p) |
2692 | asm_fprintf (file, "\tmtcrf %d,%s\n", | |
85638c0d RK |
2693 | (regs_ever_live[70] != 0) * 0x20 |
2694 | + (regs_ever_live[71] != 0) * 0x10 | |
4697a36c | 2695 | + (regs_ever_live[72] != 0) * 0x8, reg_names[12]); |
9878760c | 2696 | |
b4ac57ab RS |
2697 | /* If we have to restore more than two FP registers, branch to the |
2698 | restore function. It will return to our caller. */ | |
4697a36c MM |
2699 | if (info->first_fp_reg_save != 64 && !FP_SAVE_INLINE (info->first_fp_reg_save)) |
2700 | asm_fprintf (file, "\tb %s%d%s\n", RESTORE_FP_PREFIX, | |
2701 | info->first_fp_reg_save - 32, RESTORE_FP_SUFFIX); | |
b4ac57ab | 2702 | else |
85638c0d | 2703 | asm_fprintf (file, "\t{br|blr}\n"); |
9878760c | 2704 | } |
b4ac57ab | 2705 | |
9b30bae2 | 2706 | /* Output a traceback table here. See /usr/include/sys/debug.h for info |
314fc5a9 ILT |
2707 | on its format. |
2708 | ||
2709 | We don't output a traceback table if -finhibit-size-directive was | |
2710 | used. The documentation for -finhibit-size-directive reads | |
2711 | ``don't output a @code{.size} assembler directive, or anything | |
2712 | else that would cause trouble if the function is split in the | |
2713 | middle, and the two halves are placed at locations far apart in | |
2714 | memory.'' The traceback table has this property, since it | |
2715 | includes the offset from the start of the function to the | |
4d30c363 MM |
2716 | traceback table itself. |
2717 | ||
2718 | System V.4 Powerpc's (and the embedded ABI derived from it) use a | |
2719 | different traceback table located before the prologue. */ | |
2720 | #ifndef USING_SVR4_H | |
314fc5a9 | 2721 | if (! flag_inhibit_size_directive) |
9b30bae2 | 2722 | { |
314fc5a9 ILT |
2723 | char *fname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0); |
2724 | int fixed_parms, float_parms, parm_info; | |
2725 | int i; | |
2726 | ||
2727 | /* Need label immediately before tbtab, so we can compute its offset | |
2728 | from the function start. */ | |
2729 | if (*fname == '*') | |
2730 | ++fname; | |
2731 | ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT"); | |
2732 | ASM_OUTPUT_LABEL (file, fname); | |
2733 | ||
2734 | /* The .tbtab pseudo-op can only be used for the first eight | |
2735 | expressions, since it can't handle the possibly variable | |
2736 | length fields that follow. However, if you omit the optional | |
2737 | fields, the assembler outputs zeros for all optional fields | |
2738 | anyways, giving each variable length field is minimum length | |
2739 | (as defined in sys/debug.h). Thus we can not use the .tbtab | |
2740 | pseudo-op at all. */ | |
2741 | ||
2742 | /* An all-zero word flags the start of the tbtab, for debuggers | |
2743 | that have to find it by searching forward from the entry | |
2744 | point or from the current pc. */ | |
2745 | fprintf (file, "\t.long 0\n"); | |
2746 | ||
2747 | /* Tbtab format type. Use format type 0. */ | |
2748 | fprintf (file, "\t.byte 0,"); | |
2749 | ||
2750 | /* Language type. Unfortunately, there doesn't seem to be any | |
2751 | official way to get this info, so we use language_string. C | |
2752 | is 0. C++ is 9. No number defined for Obj-C, so use the | |
2753 | value for C for now. */ | |
2754 | if (! strcmp (language_string, "GNU C") | |
2755 | || ! strcmp (language_string, "GNU Obj-C")) | |
2756 | i = 0; | |
2757 | else if (! strcmp (language_string, "GNU F77")) | |
2758 | i = 1; | |
2759 | else if (! strcmp (language_string, "GNU Ada")) | |
2760 | i = 3; | |
2761 | else if (! strcmp (language_string, "GNU PASCAL")) | |
2762 | i = 2; | |
2763 | else if (! strcmp (language_string, "GNU C++")) | |
2764 | i = 9; | |
2765 | else | |
2766 | abort (); | |
2767 | fprintf (file, "%d,", i); | |
2768 | ||
2769 | /* 8 single bit fields: global linkage (not set for C extern linkage, | |
2770 | apparently a PL/I convention?), out-of-line epilogue/prologue, offset | |
2771 | from start of procedure stored in tbtab, internal function, function | |
2772 | has controlled storage, function has no toc, function uses fp, | |
2773 | function logs/aborts fp operations. */ | |
2774 | /* Assume that fp operations are used if any fp reg must be saved. */ | |
4697a36c | 2775 | fprintf (file, "%d,", (1 << 5) | ((info->first_fp_reg_save != 64) << 1)); |
314fc5a9 ILT |
2776 | |
2777 | /* 6 bitfields: function is interrupt handler, name present in | |
2778 | proc table, function calls alloca, on condition directives | |
2779 | (controls stack walks, 3 bits), saves condition reg, saves | |
2780 | link reg. */ | |
2781 | /* The `function calls alloca' bit seems to be set whenever reg 31 is | |
2782 | set up as a frame pointer, even when there is no alloca call. */ | |
2783 | fprintf (file, "%d,", | |
2784 | ((1 << 6) | (frame_pointer_needed << 5) | |
4697a36c | 2785 | | (info->cr_save_p << 1) | (info->lr_save_p))); |
314fc5a9 ILT |
2786 | |
2787 | /* 3 bitfields: saves backchain, spare bit, number of fpr saved | |
2788 | (6 bits). */ | |
2789 | fprintf (file, "%d,", | |
4697a36c | 2790 | (info->push_p << 7) | (64 - info->first_fp_reg_save)); |
314fc5a9 ILT |
2791 | |
2792 | /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */ | |
2793 | fprintf (file, "%d,", (32 - first_reg_to_save ())); | |
2794 | ||
2795 | { | |
2796 | /* Compute the parameter info from the function decl argument | |
2797 | list. */ | |
2798 | tree decl; | |
2799 | int next_parm_info_bit; | |
2800 | ||
2801 | next_parm_info_bit = 31; | |
2802 | parm_info = 0; | |
2803 | fixed_parms = 0; | |
2804 | float_parms = 0; | |
2805 | ||
2806 | for (decl = DECL_ARGUMENTS (current_function_decl); | |
2807 | decl; decl = TREE_CHAIN (decl)) | |
2808 | { | |
2809 | rtx parameter = DECL_INCOMING_RTL (decl); | |
2810 | enum machine_mode mode = GET_MODE (parameter); | |
2811 | ||
2812 | if (GET_CODE (parameter) == REG) | |
2813 | { | |
2814 | if (GET_MODE_CLASS (mode) == MODE_FLOAT) | |
2815 | { | |
2816 | int bits; | |
2817 | ||
2818 | float_parms++; | |
2819 | ||
2820 | if (mode == SFmode) | |
2821 | bits = 0x2; | |
2822 | else if (mode == DFmode) | |
2823 | bits = 0x3; | |
2824 | else | |
2825 | abort (); | |
2826 | ||
2827 | /* If only one bit will fit, don't or in this entry. */ | |
2828 | if (next_parm_info_bit > 0) | |
2829 | parm_info |= (bits << (next_parm_info_bit - 1)); | |
2830 | next_parm_info_bit -= 2; | |
2831 | } | |
2832 | else | |
2833 | { | |
2834 | fixed_parms += ((GET_MODE_SIZE (mode) | |
2835 | + (UNITS_PER_WORD - 1)) | |
2836 | / UNITS_PER_WORD); | |
2837 | next_parm_info_bit -= 1; | |
2838 | } | |
2839 | } | |
2840 | } | |
2841 | } | |
2842 | ||
2843 | /* Number of fixed point parameters. */ | |
2844 | /* This is actually the number of words of fixed point parameters; thus | |
2845 | an 8 byte struct counts as 2; and thus the maximum value is 8. */ | |
2846 | fprintf (file, "%d,", fixed_parms); | |
2847 | ||
2848 | /* 2 bitfields: number of floating point parameters (7 bits), parameters | |
2849 | all on stack. */ | |
2850 | /* This is actually the number of fp registers that hold parameters; | |
2851 | and thus the maximum value is 13. */ | |
2852 | /* Set parameters on stack bit if parameters are not in their original | |
2853 | registers, regardless of whether they are on the stack? Xlc | |
2854 | seems to set the bit when not optimizing. */ | |
2855 | fprintf (file, "%d\n", ((float_parms << 1) | (! optimize))); | |
2856 | ||
2857 | /* Optional fields follow. Some are variable length. */ | |
2858 | ||
2859 | /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float, | |
2860 | 11 double float. */ | |
2861 | /* There is an entry for each parameter in a register, in the order that | |
2862 | they occur in the parameter list. Any intervening arguments on the | |
2863 | stack are ignored. If the list overflows a long (max possible length | |
2864 | 34 bits) then completely leave off all elements that don't fit. */ | |
2865 | /* Only emit this long if there was at least one parameter. */ | |
2866 | if (fixed_parms || float_parms) | |
2867 | fprintf (file, "\t.long %d\n", parm_info); | |
2868 | ||
2869 | /* Offset from start of code to tb table. */ | |
2870 | fprintf (file, "\t.long "); | |
2871 | ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT"); | |
2872 | RS6000_OUTPUT_BASENAME (file, fname); | |
2873 | fprintf (file, "-."); | |
2874 | RS6000_OUTPUT_BASENAME (file, fname); | |
2875 | fprintf (file, "\n"); | |
2876 | ||
2877 | /* Interrupt handler mask. */ | |
2878 | /* Omit this long, since we never set the interrupt handler bit | |
2879 | above. */ | |
2880 | ||
2881 | /* Number of CTL (controlled storage) anchors. */ | |
2882 | /* Omit this long, since the has_ctl bit is never set above. */ | |
2883 | ||
2884 | /* Displacement into stack of each CTL anchor. */ | |
2885 | /* Omit this list of longs, because there are no CTL anchors. */ | |
2886 | ||
2887 | /* Length of function name. */ | |
2888 | fprintf (file, "\t.short %d\n", strlen (fname)); | |
2889 | ||
2890 | /* Function name. */ | |
2891 | assemble_string (fname, strlen (fname)); | |
2892 | ||
2893 | /* Register for alloca automatic storage; this is always reg 31. | |
2894 | Only emit this if the alloca bit was set above. */ | |
2895 | if (frame_pointer_needed) | |
2896 | fprintf (file, "\t.byte 31\n"); | |
9b30bae2 | 2897 | } |
4d30c363 | 2898 | #endif /* !USING_SVR4_H */ |
4697a36c MM |
2899 | |
2900 | /* Reset varargs indicator */ | |
2901 | rs6000_sysv_varargs_p = 0; | |
9878760c RK |
2902 | } |
2903 | \f | |
2904 | /* Output a TOC entry. We derive the entry name from what is | |
2905 | being written. */ | |
2906 | ||
2907 | void | |
2908 | output_toc (file, x, labelno) | |
2909 | FILE *file; | |
2910 | rtx x; | |
2911 | int labelno; | |
2912 | { | |
2913 | char buf[256]; | |
2914 | char *name = buf; | |
2915 | rtx base = x; | |
2916 | int offset = 0; | |
2917 | ||
4697a36c MM |
2918 | if (TARGET_NO_TOC) |
2919 | abort (); | |
2920 | ||
d14a6d05 MM |
2921 | #ifdef USING_SVR4_H |
2922 | if (TARGET_MINIMAL_TOC) | |
2923 | { | |
2924 | ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC"); | |
2925 | fprintf (file, "%d = .-", labelno); | |
2926 | ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LCTOC"); | |
2927 | fprintf (file, "1\n"); | |
2928 | } | |
2929 | else | |
2930 | #endif /* USING_SVR4_H */ | |
2931 | ASM_OUTPUT_INTERNAL_LABEL (file, "LC", labelno); | |
9878760c | 2932 | |
37c37a57 RK |
2933 | /* Handle FP constants specially. Note that if we have a minimal |
2934 | TOC, things we put here aren't actually in the TOC, so we can allow | |
2935 | FP constants. */ | |
9878760c RK |
2936 | if (GET_CODE (x) == CONST_DOUBLE |
2937 | && GET_MODE (x) == DFmode | |
37c37a57 | 2938 | && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC)) |
9878760c | 2939 | { |
0adc764e RK |
2940 | REAL_VALUE_TYPE r; |
2941 | long l[2]; | |
2942 | ||
2943 | REAL_VALUE_FROM_CONST_DOUBLE (r, x); | |
2944 | REAL_VALUE_TO_TARGET_DOUBLE (r, l); | |
1875cc88 | 2945 | if (TARGET_MINIMAL_TOC) |
0adc764e | 2946 | fprintf (file, "\t.long %ld\n\t.long %ld\n", l[0], l[1]); |
1875cc88 | 2947 | else |
0adc764e RK |
2948 | fprintf (file, "\t.tc FD_%lx_%lx[TC],%ld,%ld\n", |
2949 | l[0], l[1], l[0], l[1]); | |
9878760c RK |
2950 | return; |
2951 | } | |
2952 | else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode | |
37c37a57 | 2953 | && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC)) |
9878760c RK |
2954 | { |
2955 | rtx val = operand_subword (x, 0, 0, SFmode); | |
2956 | ||
2957 | if (val == 0 || GET_CODE (val) != CONST_INT) | |
2958 | abort (); | |
2959 | ||
1875cc88 JW |
2960 | if (TARGET_MINIMAL_TOC) |
2961 | fprintf (file, "\t.long %d\n", INTVAL (val)); | |
2962 | else | |
2963 | fprintf (file, "\t.tc FS_%x[TC],%d\n", INTVAL (val), INTVAL (val)); | |
9878760c RK |
2964 | return; |
2965 | } | |
2966 | ||
2967 | if (GET_CODE (x) == CONST) | |
2968 | { | |
2969 | base = XEXP (XEXP (x, 0), 0); | |
2970 | offset = INTVAL (XEXP (XEXP (x, 0), 1)); | |
2971 | } | |
2972 | ||
2973 | if (GET_CODE (base) == SYMBOL_REF) | |
2974 | name = XSTR (base, 0); | |
2975 | else if (GET_CODE (base) == LABEL_REF) | |
2976 | ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (XEXP (base, 0))); | |
2977 | else if (GET_CODE (base) == CODE_LABEL) | |
2978 | ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (base)); | |
2979 | else | |
2980 | abort (); | |
2981 | ||
1875cc88 JW |
2982 | if (TARGET_MINIMAL_TOC) |
2983 | fprintf (file, "\t.long "); | |
2984 | else | |
2985 | { | |
2986 | fprintf (file, "\t.tc "); | |
2987 | RS6000_OUTPUT_BASENAME (file, name); | |
9878760c | 2988 | |
1875cc88 JW |
2989 | if (offset < 0) |
2990 | fprintf (file, ".N%d", - offset); | |
2991 | else if (offset) | |
2992 | fprintf (file, ".P%d", offset); | |
9878760c | 2993 | |
1875cc88 JW |
2994 | fprintf (file, "[TC],"); |
2995 | } | |
9878760c RK |
2996 | output_addr_const (file, x); |
2997 | fprintf (file, "\n"); | |
2998 | } | |
2999 | \f | |
3000 | /* Output an assembler pseudo-op to write an ASCII string of N characters | |
3001 | starting at P to FILE. | |
3002 | ||
3003 | On the RS/6000, we have to do this using the .byte operation and | |
3004 | write out special characters outside the quoted string. | |
3005 | Also, the assembler is broken; very long strings are truncated, | |
3006 | so we must artificially break them up early. */ | |
3007 | ||
3008 | void | |
3009 | output_ascii (file, p, n) | |
3010 | FILE *file; | |
3011 | char *p; | |
3012 | int n; | |
3013 | { | |
3014 | char c; | |
3015 | int i, count_string; | |
3016 | char *for_string = "\t.byte \""; | |
3017 | char *for_decimal = "\t.byte "; | |
3018 | char *to_close = NULL; | |
3019 | ||
3020 | count_string = 0; | |
3021 | for (i = 0; i < n; i++) | |
3022 | { | |
3023 | c = *p++; | |
3024 | if (c >= ' ' && c < 0177) | |
3025 | { | |
3026 | if (for_string) | |
3027 | fputs (for_string, file); | |
3028 | putc (c, file); | |
3029 | ||
3030 | /* Write two quotes to get one. */ | |
3031 | if (c == '"') | |
3032 | { | |
3033 | putc (c, file); | |
3034 | ++count_string; | |
3035 | } | |
3036 | ||
3037 | for_string = NULL; | |
3038 | for_decimal = "\"\n\t.byte "; | |
3039 | to_close = "\"\n"; | |
3040 | ++count_string; | |
3041 | ||
3042 | if (count_string >= 512) | |
3043 | { | |
3044 | fputs (to_close, file); | |
3045 | ||
3046 | for_string = "\t.byte \""; | |
3047 | for_decimal = "\t.byte "; | |
3048 | to_close = NULL; | |
3049 | count_string = 0; | |
3050 | } | |
3051 | } | |
3052 | else | |
3053 | { | |
3054 | if (for_decimal) | |
3055 | fputs (for_decimal, file); | |
3056 | fprintf (file, "%d", c); | |
3057 | ||
3058 | for_string = "\n\t.byte \""; | |
3059 | for_decimal = ", "; | |
3060 | to_close = "\n"; | |
3061 | count_string = 0; | |
3062 | } | |
3063 | } | |
3064 | ||
3065 | /* Now close the string if we have written one. Then end the line. */ | |
3066 | if (to_close) | |
3067 | fprintf (file, to_close); | |
3068 | } | |
3069 | \f | |
3070 | /* Generate a unique section name for FILENAME for a section type | |
3071 | represented by SECTION_DESC. Output goes into BUF. | |
3072 | ||
3073 | SECTION_DESC can be any string, as long as it is different for each | |
3074 | possible section type. | |
3075 | ||
3076 | We name the section in the same manner as xlc. The name begins with an | |
3077 | underscore followed by the filename (after stripping any leading directory | |
11e5fe42 RK |
3078 | names) with the last period replaced by the string SECTION_DESC. If |
3079 | FILENAME does not contain a period, SECTION_DESC is appended to the end of | |
3080 | the name. */ | |
9878760c RK |
3081 | |
3082 | void | |
3083 | rs6000_gen_section_name (buf, filename, section_desc) | |
3084 | char **buf; | |
3085 | char *filename; | |
3086 | char *section_desc; | |
3087 | { | |
11e5fe42 | 3088 | char *q, *after_last_slash, *last_period; |
9878760c RK |
3089 | char *p; |
3090 | int len; | |
9878760c RK |
3091 | |
3092 | after_last_slash = filename; | |
3093 | for (q = filename; *q; q++) | |
11e5fe42 RK |
3094 | { |
3095 | if (*q == '/') | |
3096 | after_last_slash = q + 1; | |
3097 | else if (*q == '.') | |
3098 | last_period = q; | |
3099 | } | |
9878760c | 3100 | |
11e5fe42 | 3101 | len = strlen (after_last_slash) + strlen (section_desc) + 2; |
9878760c RK |
3102 | *buf = (char *) permalloc (len); |
3103 | ||
3104 | p = *buf; | |
3105 | *p++ = '_'; | |
3106 | ||
3107 | for (q = after_last_slash; *q; q++) | |
3108 | { | |
11e5fe42 | 3109 | if (q == last_period) |
9878760c RK |
3110 | { |
3111 | strcpy (p, section_desc); | |
3112 | p += strlen (section_desc); | |
9878760c RK |
3113 | } |
3114 | ||
3115 | else if (isalnum (*q)) | |
3116 | *p++ = *q; | |
3117 | } | |
3118 | ||
11e5fe42 | 3119 | if (last_period == 0) |
9878760c RK |
3120 | strcpy (p, section_desc); |
3121 | else | |
3122 | *p = '\0'; | |
3123 | } | |
e165f3f0 RK |
3124 | \f |
3125 | /* Write function profiler code. */ | |
3126 | ||
3127 | void | |
3128 | output_function_profiler (file, labelno) | |
3129 | FILE *file; | |
3130 | int labelno; | |
3131 | { | |
4d30c363 MM |
3132 | #ifdef USING_SVR4_H |
3133 | abort (); | |
3134 | #else | |
e165f3f0 RK |
3135 | /* The last used parameter register. */ |
3136 | int last_parm_reg; | |
3137 | int i, j; | |
3daf36a4 | 3138 | char buf[100]; |
e165f3f0 RK |
3139 | |
3140 | /* Set up a TOC entry for the profiler label. */ | |
3141 | toc_section (); | |
3daf36a4 ILT |
3142 | ASM_OUTPUT_INTERNAL_LABEL (file, "LPC", labelno); |
3143 | ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno); | |
35fc1624 | 3144 | if (TARGET_MINIMAL_TOC) |
3daf36a4 ILT |
3145 | { |
3146 | fprintf (file, "\t.long "); | |
3147 | assemble_name (file, buf); | |
3148 | fprintf (file, "\n"); | |
3149 | } | |
35fc1624 | 3150 | else |
3daf36a4 ILT |
3151 | { |
3152 | fprintf (file, "\t.tc\t"); | |
3153 | assemble_name (file, buf); | |
3154 | fprintf (file, "[TC],"); | |
3155 | assemble_name (file, buf); | |
3156 | fprintf (file, "\n"); | |
3157 | } | |
e165f3f0 RK |
3158 | text_section (); |
3159 | ||
3160 | /* Figure out last used parameter register. The proper thing to do is | |
3161 | to walk incoming args of the function. A function might have live | |
3162 | parameter registers even if it has no incoming args. */ | |
3163 | ||
3164 | for (last_parm_reg = 10; | |
3165 | last_parm_reg > 2 && ! regs_ever_live [last_parm_reg]; | |
3166 | last_parm_reg--) | |
3167 | ; | |
3168 | ||
3169 | /* Save parameter registers in regs 23-30. Don't overwrite reg 31, since | |
3170 | it might be set up as the frame pointer. */ | |
3171 | ||
3172 | for (i = 3, j = 30; i <= last_parm_reg; i++, j--) | |
3173 | fprintf (file, "\tai %d,%d,0\n", j, i); | |
3174 | ||
3175 | /* Load location address into r3, and call mcount. */ | |
3176 | ||
3daf36a4 ILT |
3177 | ASM_GENERATE_INTERNAL_LABEL (buf, "LPC", labelno); |
3178 | fprintf (file, "\tl 3,"); | |
3179 | assemble_name (file, buf); | |
3180 | fprintf (file, "(2)\n\tbl .mcount\n"); | |
e165f3f0 RK |
3181 | |
3182 | /* Restore parameter registers. */ | |
3183 | ||
3184 | for (i = 3, j = 30; i <= last_parm_reg; i++, j--) | |
3185 | fprintf (file, "\tai %d,%d,0\n", i, j); | |
4d30c363 | 3186 | #endif |
e165f3f0 | 3187 | } |
a251ffd0 TG |
3188 | |
3189 | /* Adjust the cost of a scheduling dependency. Return the new cost of | |
3190 | a dependency LINK or INSN on DEP_INSN. COST is the current cost. */ | |
3191 | ||
3192 | int | |
a06faf84 | 3193 | rs6000_adjust_cost (insn, link, dep_insn, cost) |
a251ffd0 TG |
3194 | rtx insn; |
3195 | rtx link; | |
3196 | rtx dep_insn; | |
3197 | int cost; | |
3198 | { | |
3199 | if (! recog_memoized (insn)) | |
3200 | return 0; | |
3201 | ||
3202 | if (REG_NOTE_KIND (link) != 0) | |
3203 | return 0; | |
3204 | ||
3205 | if (REG_NOTE_KIND (link) == 0) | |
3206 | { | |
3207 | /* Data dependency; DEP_INSN writes a register that INSN reads some | |
3208 | cycles later. */ | |
3209 | ||
3210 | /* Tell the first scheduling pass about the latency between a mtctr | |
3211 | and bctr (and mtlr and br/blr). The first scheduling pass will not | |
3212 | know about this latency since the mtctr instruction, which has the | |
3213 | latency associated to it, will be generated by reload. */ | |
3214 | if (get_attr_type (insn) == TYPE_JMPREG) | |
3215 | return TARGET_POWER ? 5 : 4; | |
3216 | ||
3217 | /* Fall out to return default cost. */ | |
3218 | } | |
3219 | ||
3220 | return cost; | |
3221 | } |