]> gcc.gnu.org Git - gcc.git/blame - gcc/config/rs6000/rs6000.c
git://gcc.gnu.org / gcc.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
pa.h (PARSE_LDD_OUTPUT): Handle dynamic libraries that are loaded "statically".
[gcc.git] / gcc / config / rs6000 / rs6000.c
CommitLineData
9878760c 1/* Subroutines used for code generation on IBM RS/6000.
cf27b467 2 Copyright (C) 1991, 1993, 1994, 1995, 1996 Free Software Foundation, Inc.
fab3bcc3 3 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
9878760c
RK		 4
5This file is part of GNU CC.
6
7GNU CC is free software; you can redistribute it and/or modify
8it under the terms of the GNU General Public License as published by
9the Free Software Foundation; either version 2, or (at your option)
10any later version.
11
12GNU CC is distributed in the hope that it will be useful,
13but WITHOUT ANY WARRANTY; without even the implied warranty of
14MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15GNU General Public License for more details.
16
17You should have received a copy of the GNU General Public License
18along with GNU CC; see the file COPYING. If not, write to
c15c9075
RK		 19the Free Software Foundation, 59 Temple Place - Suite 330,
20Boston, MA 02111-1307, USA. */
9878760c
RK		 21
22#include <stdio.h>
127b0efc 23#include <ctype.h>
9878760c
RK		 24#include "config.h"
25#include "rtl.h"
26#include "regs.h"
27#include "hard-reg-set.h"
28#include "real.h"
29#include "insn-config.h"
30#include "conditions.h"
31#include "insn-flags.h"
32#include "output.h"
33#include "insn-attr.h"
34#include "flags.h"
35#include "recog.h"
36#include "expr.h"
37#include "obstack.h"
9b30bae2
JW		 38#include "tree.h"
39
7509c759
MM		 40#ifndef TARGET_NO_PROTOTYPE
41#define TARGET_NO_PROTOTYPE 0
42#endif
43
9b30bae2 44extern char *language_string;
5248c961 45extern int profile_block_flag;
9878760c
RK		 46
47#define min(A,B) ((A) < (B) ? (A) : (B))
48#define max(A,B) ((A) > (B) ? (A) : (B))
49
5248c961
RK		 50/* Target cpu type */
51
52enum processor_type rs6000_cpu;
8e3f41e7
MM		 53struct rs6000_cpu_select rs6000_select[3] =
54{
55 /* switch name, tune arch */
5d6426e0 56 { (char *)0, "--with-cpu=", 1, 1 },
8e3f41e7
MM		 57 { (char *)0, "-mcpu=", 1, 1 },
58 { (char *)0, "-mtune=", 1, 0 },
59};
5248c961 60
9878760c
RK		 61/* Set to non-zero by "fix" operation to indicate that itrunc and
62 uitrunc must be defined. */
63
64int rs6000_trunc_used;
65
66/* Set to non-zero once they have been defined. */
67
68static int trunc_defined;
69
c764f757
RK		 70/* Set to non-zero once AIX common-mode calls have been defined. */
71static int common_mode_defined;
c81bebd7 72
9878760c
RK		 73/* Save information from a "cmpxx" operation until the branch or scc is
74 emitted. */
9878760c
RK		 75rtx rs6000_compare_op0, rs6000_compare_op1;
76int rs6000_compare_fp_p;
874a0744
MM		 77
78#ifdef USING_SVR4_H
79/* Label number of label created for -mrelocatable, to call to so we can
80 get the address of the GOT section */
81int rs6000_pic_labelno;
c81bebd7
MM		 82
83/* Which abi to adhere to */
84char *rs6000_abi_name = RS6000_ABI_NAME;
d9407988
MM		 85
86/* Semantics of the small data area */
87enum rs6000_sdata_type rs6000_sdata = SDATA_DATA;
88
89/* Which small data model to use */
90char *rs6000_sdata_name = (char *)0;
874a0744 91#endif
4697a36c
MM		 92
93/* Whether a System V.4 varargs area was created. */
94int rs6000_sysv_varargs_p;
8f75773e 95
b6c9286a
MM		 96/* Whether we need to save the TOC register. */
97int rs6000_save_toc_p;
98
99/* ABI enumeration available for subtarget to use. */
100enum rs6000_abi rs6000_current_abi;
101
802a0058
MM		 102/* Offset & size for fpmem stack locations used for converting between
103 float and integral types. */
104int rs6000_fpmem_offset;
105int rs6000_fpmem_size;
106
c81bebd7
MM		 107\f
108/* Default register names. */
109char rs6000_reg_names[][8] =
110{
802a0058
MM		 111 "0", "1", "2", "3", "4", "5", "6", "7",
112 "8", "9", "10", "11", "12", "13", "14", "15",
113 "16", "17", "18", "19", "20", "21", "22", "23",
114 "24", "25", "26", "27", "28", "29", "30", "31",
115 "0", "1", "2", "3", "4", "5", "6", "7",
116 "8", "9", "10", "11", "12", "13", "14", "15",
117 "16", "17", "18", "19", "20", "21", "22", "23",
118 "24", "25", "26", "27", "28", "29", "30", "31",
119 "mq", "lr", "ctr","ap",
120 "0", "1", "2", "3", "4", "5", "6", "7",
121 "fpmem"
c81bebd7
MM		 122};
123
124#ifdef TARGET_REGNAMES
125static char alt_reg_names[][8] =
126{
802a0058
MM		 127 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7",
128 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
129 "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23",
130 "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31",
131 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7",
132 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15",
133 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23",
134 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31",
135 "mq", "lr", "ctr", "ap",
136 "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7",
137 "fpmem"
c81bebd7
MM		 138};
139#endif
9878760c 140\f
5248c961
RK		 141/* Override command line options. Mostly we process the processor
142 type and sometimes adjust other TARGET_ options. */
143
144void
8e3f41e7
MM		 145rs6000_override_options (default_cpu)
146 char *default_cpu;
5248c961 147{
8e3f41e7
MM		 148 int i, j;
149 struct rs6000_cpu_select *ptr;
5248c961 150
85638c0d
RK		 151 /* Simplify the entries below by making a mask for any POWER
152 variant and any PowerPC variant. */
153
938937d8 154#define POWER_MASKS (MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING)
68c49ffa
RK		 155#define POWERPC_MASKS (MASK_POWERPC | MASK_PPC_GPOPT \
156 | MASK_PPC_GFXOPT | MASK_POWERPC64)
157#define POWERPC_OPT_MASKS (MASK_PPC_GPOPT | MASK_PPC_GFXOPT)
85638c0d 158
5248c961
RK		 159 static struct ptt
160 {
161 char *name; /* Canonical processor name. */
162 enum processor_type processor; /* Processor type enum value. */
163 int target_enable; /* Target flags to enable. */
164 int target_disable; /* Target flags to disable. */
165 } processor_target_table[]
cf27b467
MM		 166 = {{"common", PROCESSOR_COMMON, MASK_NEW_MNEMONICS,
167 POWER_MASKS | POWERPC_MASKS},
db7f1e43 168 {"power", PROCESSOR_POWER,
938937d8 169 MASK_POWER | MASK_MULTIPLE | MASK_STRING,
db7f1e43 170 MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS},
8e3f41e7
MM		 171 {"power2", PROCESSOR_POWER,
172 MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING,
173 POWERPC_MASKS | MASK_NEW_MNEMONICS},
db7f1e43
RK		 174 {"powerpc", PROCESSOR_POWERPC,
175 MASK_POWERPC | MASK_NEW_MNEMONICS,
68c49ffa 176 POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64},
db7f1e43 177 {"rios", PROCESSOR_RIOS1,
938937d8 178 MASK_POWER | MASK_MULTIPLE | MASK_STRING,
db7f1e43
RK		 179 MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS},
180 {"rios1", PROCESSOR_RIOS1,
938937d8 181 MASK_POWER | MASK_MULTIPLE | MASK_STRING,
db7f1e43
RK		 182 MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS},
183 {"rsc", PROCESSOR_PPC601,
938937d8 184 MASK_POWER | MASK_MULTIPLE | MASK_STRING,
db7f1e43
RK		 185 MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS},
186 {"rsc1", PROCESSOR_PPC601,
938937d8 187 MASK_POWER | MASK_MULTIPLE | MASK_STRING,
db7f1e43
RK		 188 MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS},
189 {"rios2", PROCESSOR_RIOS2,
938937d8 190 MASK_POWER | MASK_MULTIPLE | MASK_STRING | MASK_POWER2,
db7f1e43 191 POWERPC_MASKS | MASK_NEW_MNEMONICS},
49a0b204
MM		 192 {"403", PROCESSOR_PPC403,
193 MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS,
194 POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64},
cf27b467
MM		 195 {"505", PROCESSOR_MPCCORE,
196 MASK_POWERPC | MASK_NEW_MNEMONICS,
197 POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64},
5248c961 198 {"601", PROCESSOR_PPC601,
938937d8 199 MASK_POWER | MASK_POWERPC | MASK_NEW_MNEMONICS | MASK_MULTIPLE | MASK_STRING,
68c49ffa 200 MASK_POWER2 | POWERPC_OPT_MASKS | MASK_POWERPC64},
1ec26da6 201 {"602", PROCESSOR_PPC603,
cf27b467
MM		 202 MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
203 POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64},
5248c961 204 {"603", PROCESSOR_PPC603,
68c49ffa
RK		 205 MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
206 POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64},
b6c9286a
MM		 207 {"603e", PROCESSOR_PPC603,
208 MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
209 POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64},
5248c961 210 {"604", PROCESSOR_PPC604,
b6c9286a
MM		 211 MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
212 POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64},
213 {"620", PROCESSOR_PPC620,
68c49ffa 214 MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
cf27b467
MM		 215 POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64},
216 {"821", PROCESSOR_MPCCORE,
217 MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS,
218 POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64},
219 {"860", PROCESSOR_MPCCORE,
220 MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS,
221 POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}};
5248c961
RK		 222
223 int ptt_size = sizeof (processor_target_table) / sizeof (struct ptt);
224
8a61d227 225 int multiple = TARGET_MULTIPLE; /* save current -mmultiple/-mno-multiple status */
938937d8 226 int string = TARGET_STRING; /* save current -mstring/-mno-string status */
8a61d227 227
5248c961
RK		 228 profile_block_flag = 0;
229
230 /* Identify the processor type */
8e3f41e7
MM		 231 rs6000_select[0].string = default_cpu;
232 rs6000_cpu = PROCESSOR_DEFAULT;
8e3f41e7
MM		 233
234 for (i = 0; i < sizeof (rs6000_select) / sizeof (rs6000_select[0]); i++)
5248c961 235 {
8e3f41e7
MM		 236 ptr = &rs6000_select[i];
237 if (ptr->string != (char *)0 && ptr->string[0] != '\0')
5248c961 238 {
8e3f41e7
MM		 239 for (j = 0; j < ptt_size; j++)
240 if (! strcmp (ptr->string, processor_target_table[j].name))
241 {
242 if (ptr->set_tune_p)
243 rs6000_cpu = processor_target_table[j].processor;
244
245 if (ptr->set_arch_p)
246 {
247 target_flags |= processor_target_table[j].target_enable;
248 target_flags &= ~processor_target_table[j].target_disable;
249 }
250 break;
251 }
252
253 if (i == ptt_size)
254 error ("bad value (%s) for %s switch", ptr->string, ptr->name);
5248c961
RK		 255 }
256 }
8a61d227
MM		 257
258 /* If -mmultiple or -mno-multiple was explicitly used, don't
259 override with the processor default */
260 if (TARGET_MULTIPLE_SET)
261 target_flags = (target_flags & ~MASK_MULTIPLE) | multiple;
7e69e155 262
938937d8
MM		 263 /* If -mstring or -mno-string was explicitly used, don't
264 override with the processor default */
265 if (TARGET_STRING_SET)
1f5515bf 266 target_flags = (target_flags & ~MASK_STRING) | string;
938937d8 267
7e69e155
MM		 268 /* Don't allow -mmultiple or -mstring on little endian systems, because the
269 hardware doesn't support the instructions used in little endian mode */
270 if (!BYTES_BIG_ENDIAN)
271 {
272 if (TARGET_MULTIPLE)
273 {
274 target_flags &= ~MASK_MULTIPLE;
275 if (TARGET_MULTIPLE_SET)
276 warning ("-mmultiple is not supported on little endian systems");
277 }
278
279 if (TARGET_STRING)
280 {
281 target_flags &= ~MASK_STRING;
938937d8
MM		 282 if (TARGET_STRING_SET)
283 warning ("-mstring is not supported on little endian systems");
7e69e155
MM		 284 }
285 }
3933e0e1 286
c81bebd7
MM		 287#ifdef TARGET_REGNAMES
288 /* If the user desires alternate register names, copy in the alternate names
289 now. */
290 if (TARGET_REGNAMES)
291 bcopy ((char *)alt_reg_names, (char *)rs6000_reg_names, sizeof (rs6000_reg_names));
292#endif
293
3933e0e1
MM		 294#ifdef SUBTARGET_OVERRIDE_OPTIONS
295 SUBTARGET_OVERRIDE_OPTIONS;
296#endif
5248c961 297}
3cfa4909
MM		 298\f
299/* Do anything needed at the start of the asm file. */
300
301void
302rs6000_file_start (file, default_cpu)
303 FILE *file;
304 char *default_cpu;
305{
306 int i;
307 char buffer[80];
308 char *start = buffer;
309 struct rs6000_cpu_select *ptr;
310
311 if (flag_verbose_asm)
312 {
313 sprintf (buffer, "\n%s rs6000/powerpc options:", ASM_COMMENT_START);
314 rs6000_select[0].string = default_cpu;
315
316 for (i = 0; i < sizeof (rs6000_select) / sizeof (rs6000_select[0]); i++)
317 {
318 ptr = &rs6000_select[i];
319 if (ptr->string != (char *)0 && ptr->string[0] != '\0')
320 {
321 fprintf (file, "%s %s%s", start, ptr->name, ptr->string);
322 start = "";
323 }
324 }
325
326#ifdef USING_SVR4_H
327 switch (rs6000_sdata)
328 {
329 case SDATA_NONE: fprintf (file, "%s -msdata=none", start); start = ""; break;
330 case SDATA_DATA: fprintf (file, "%s -msdata=data", start); start = ""; break;
331 case SDATA_SYSV: fprintf (file, "%s -msdata=sysv", start); start = ""; break;
332 case SDATA_EABI: fprintf (file, "%s -msdata=eabi", start); start = ""; break;
333 }
334
335 if (rs6000_sdata && g_switch_value)
336 {
337 fprintf (file, "%s -G %d", start, g_switch_value);
338 start = "";
339 }
340#endif
341
342 if (*start == '\0')
343 fputs ("\n", file);
344 }
345}
346
24d304eb
RK		 347\f
348/* Create a CONST_DOUBLE from a string. */
349
350struct rtx_def *
351rs6000_float_const (string, mode)
352 char *string;
353 enum machine_mode mode;
354{
355 REAL_VALUE_TYPE value = REAL_VALUE_ATOF (string, mode);
356 return immed_real_const_1 (value, mode);
357}
358
75814ad4
MM		 359\f
360/* Create a CONST_DOUBLE like immed_double_const, except reverse the
361 two parts of the constant if the target is little endian. */
362
d679bebf
RK		 363struct rtx_def *
364rs6000_immed_double_const (i0, i1, mode)
75814ad4
MM		 365 HOST_WIDE_INT i0, i1;
366 enum machine_mode mode;
367{
368 if (! WORDS_BIG_ENDIAN)
369 return immed_double_const (i1, i0, mode);
370
371 return immed_double_const (i0, i1, mode);
372}
373
5248c961 374\f
9878760c
RK		 375/* Return non-zero if this function is known to have a null epilogue. */
376
377int
378direct_return ()
379{
4697a36c
MM		 380 if (reload_completed)
381 {
382 rs6000_stack_t *info = rs6000_stack_info ();
383
384 if (info->first_gp_reg_save == 32
385 && info->first_fp_reg_save == 64
386 && !info->lr_save_p
1b4a2731 387 && !info->cr_save_p
4697a36c
MM		 388 && !info->push_p)
389 return 1;
390 }
391
392 return 0;
9878760c
RK		 393}
394
395/* Returns 1 always. */
396
397int
398any_operand (op, mode)
399 register rtx op;
400 enum machine_mode mode;
401{
402 return 1;
403}
404
b6c9286a
MM		 405/* Returns 1 if op is the count register */
406int count_register_operand(op, mode)
407 register rtx op;
408 enum machine_mode mode;
409{
410 if (GET_CODE (op) != REG)
411 return 0;
412
413 if (REGNO (op) == COUNT_REGISTER_REGNUM)
414 return 1;
415
416 if (REGNO (op) > FIRST_PSEUDO_REGISTER)
417 return 1;
418
419 return 0;
420}
421
802a0058
MM		 422/* Returns 1 if op is memory location for float/int conversions that masquerades
423 as a register. */
424int fpmem_operand(op, mode)
425 register rtx op;
426 enum machine_mode mode;
427{
428 if (GET_CODE (op) != REG)
429 return 0;
430
431 if (FPMEM_REGNO_P (REGNO (op)))
432 return 1;
433
434#if 0
435 if (REGNO (op) > FIRST_PSEUDO_REGISTER)
436 return 1;
437#endif
438
439 return 0;
440}
441
9878760c
RK		 442/* Return 1 if OP is a constant that can fit in a D field. */
443
444int
445short_cint_operand (op, mode)
446 register rtx op;
447 enum machine_mode mode;
448{
449 return (GET_CODE (op) == CONST_INT
450 && (unsigned) (INTVAL (op) + 0x8000) < 0x10000);
451}
452
453/* Similar for a unsigned D field. */
454
455int
456u_short_cint_operand (op, mode)
457 register rtx op;
458 enum machine_mode mode;
459{
460 return (GET_CODE (op) == CONST_INT && (INTVAL (op) & 0xffff0000) == 0);
461}
462
dcfedcd0
RK		 463/* Return 1 if OP is a CONST_INT that cannot fit in a signed D field. */
464
465int
466non_short_cint_operand (op, mode)
467 register rtx op;
468 enum machine_mode mode;
469{
470 return (GET_CODE (op) == CONST_INT
471 && (unsigned) (INTVAL (op) + 0x8000) >= 0x10000);
472}
473
9878760c
RK		 474/* Returns 1 if OP is a register that is not special (i.e., not MQ,
475 ctr, or lr). */
476
477int
cd2b37d9 478gpc_reg_operand (op, mode)
9878760c
RK		 479 register rtx op;
480 enum machine_mode mode;
481{
482 return (register_operand (op, mode)
802a0058
MM		 483 && (GET_CODE (op) != REG
484 || (REGNO (op) >= 67 && !FPMEM_REGNO_P (REGNO (op)))
485 || REGNO (op) < 64));
9878760c
RK		 486}
487
488/* Returns 1 if OP is either a pseudo-register or a register denoting a
489 CR field. */
490
491int
492cc_reg_operand (op, mode)
493 register rtx op;
494 enum machine_mode mode;
495{
496 return (register_operand (op, mode)
497 && (GET_CODE (op) != REG
498 || REGNO (op) >= FIRST_PSEUDO_REGISTER
499 || CR_REGNO_P (REGNO (op))));
500}
501
502/* Returns 1 if OP is either a constant integer valid for a D-field or a
503 non-special register. If a register, it must be in the proper mode unless
504 MODE is VOIDmode. */
505
506int
507reg_or_short_operand (op, mode)
508 register rtx op;
509 enum machine_mode mode;
510{
f5a28898 511 return short_cint_operand (op, mode) || gpc_reg_operand (op, mode);
9878760c
RK		 512}
513
514/* Similar, except check if the negation of the constant would be valid for
515 a D-field. */
516
517int
518reg_or_neg_short_operand (op, mode)
519 register rtx op;
520 enum machine_mode mode;
521{
522 if (GET_CODE (op) == CONST_INT)
523 return CONST_OK_FOR_LETTER_P (INTVAL (op), 'P');
524
cd2b37d9 525 return gpc_reg_operand (op, mode);
9878760c
RK		 526}
527
528/* Return 1 if the operand is either a register or an integer whose high-order
529 16 bits are zero. */
530
531int
532reg_or_u_short_operand (op, mode)
533 register rtx op;
534 enum machine_mode mode;
535{
536 if (GET_CODE (op) == CONST_INT
537 && (INTVAL (op) & 0xffff0000) == 0)
538 return 1;
539
cd2b37d9 540 return gpc_reg_operand (op, mode);
9878760c
RK		 541}
542
543/* Return 1 is the operand is either a non-special register or ANY
544 constant integer. */
545
546int
547reg_or_cint_operand (op, mode)
548 register rtx op;
549 enum machine_mode mode;
550{
cd2b37d9 551 return GET_CODE (op) == CONST_INT || gpc_reg_operand (op, mode);
9878760c
RK		 552}
553
766a866c
MM		 554/* Return 1 if the operand is an operand that can be loaded via the GOT */
555
556int
557got_operand (op, mode)
558 register rtx op;
559 enum machine_mode mode;
560{
561 return (GET_CODE (op) == SYMBOL_REF
562 || GET_CODE (op) == CONST
563 || GET_CODE (op) == LABEL_REF);
564}
565
4e74d8ec
MM		 566/* Return the number of instructions it takes to form a constant in an
567 integer register. */
568
569static int
570num_insns_constant_wide (value)
571 HOST_WIDE_INT value;
572{
573 /* signed constant loadable with {cal|addi} */
574 if (((unsigned HOST_WIDE_INT)value + 0x8000) < 0x10000)
575 return 1;
576
577#if HOST_BITS_PER_WIDE_INT == 32
578 /* constant loadable with {cau|addis} */
579 else if ((value & 0xffff) == 0)
580 return 1;
581
582#else
583 /* constant loadable with {cau|addis} */
584 else if ((value & 0xffff) == 0 && (value & ~0xffffffff) == 0)
585 return 1;
586
587 else if (TARGET_64BIT)
588 {
589 HOST_WIDE_INT low = value & 0xffffffff;
590 HOST_WIDE_INT high = value >> 32;
591
592 if (high == 0 && (low & 0x80000000) == 0)
593 return 2;
594
595 else if (high == 0xffffffff && (low & 0x80000000) != 0)
596 return 2;
597
598 else if (!low)
599 return num_insns_constant_wide (high) + 1;
600
601 else
602 return (num_insns_constant_wide (high)
e396202a 603 + num_insns_constant_wide (low) + 1);
4e74d8ec
MM		 604 }
605#endif
606
607 else
608 return 2;
609}
610
611int
612num_insns_constant (op, mode)
613 rtx op;
614 enum machine_mode mode;
615{
616 if (mode != SImode && mode != DImode)
617 abort ();
618
619 if (GET_CODE (op) == CONST_INT)
620 return num_insns_constant_wide (INTVAL (op));
621
622 else if (GET_CODE (op) == CONST_DOUBLE && TARGET_32BIT)
623 return (num_insns_constant_wide (CONST_DOUBLE_LOW (op))
624 + num_insns_constant_wide (CONST_DOUBLE_HIGH (op)));
625
626 else if (GET_CODE (op) == CONST_DOUBLE && TARGET_64BIT)
627 {
628 HOST_WIDE_INT low = CONST_DOUBLE_LOW (op);
629 HOST_WIDE_INT high = CONST_DOUBLE_HIGH (op);
630
631 if (high == 0 && (low & 0x80000000) == 0)
632 return num_insns_constant_wide (low);
633
634 else if (((high & 0xffffffff) == 0xffffffff)
635 && ((low & 0x80000000) != 0))
636 return num_insns_constant_wide (low);
637
638 else if (low == 0)
639 return num_insns_constant_wide (high) + 1;
640
641 else
642 return (num_insns_constant_wide (high)
643 + num_insns_constant_wide (low) + 1);
644 }
645
646 else
647 abort ();
648}
649
6f2f8311
RK		 650/* Return 1 if the operand is a CONST_DOUBLE and it can be put into a register
651 with one instruction per word. We only do this if we can safely read
652 CONST_DOUBLE_{LOW,HIGH}. */
9878760c
RK		 653
654int
655easy_fp_constant (op, mode)
656 register rtx op;
657 register enum machine_mode mode;
658{
9878760c
RK		 659 if (GET_CODE (op) != CONST_DOUBLE
660 || GET_MODE (op) != mode
4e74d8ec 661 || (GET_MODE_CLASS (mode) != MODE_FLOAT && mode != DImode))
9878760c
RK		 662 return 0;
663
b6c9286a 664 /* Consider all constants with -msoft-float to be easy */
4e74d8ec 665 if (TARGET_SOFT_FLOAT && mode != DImode)
b6c9286a
MM		 666 return 1;
667
042259f2
DE		 668 if (mode == DFmode)
669 {
670 long k[2];
671 REAL_VALUE_TYPE rv;
672
673 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
674 REAL_VALUE_TO_TARGET_DOUBLE (rv, k);
9878760c 675
4e74d8ec
MM		 676 return (num_insns_constant_wide ((HOST_WIDE_INT)k[0]) == 1
677 && num_insns_constant_wide ((HOST_WIDE_INT)k[1]) == 1);
042259f2 678 }
4e74d8ec
MM		 679
680 else if (mode == SFmode)
042259f2
DE		 681 {
682 long l;
683 REAL_VALUE_TYPE rv;
684
685 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
686 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
9878760c 687
4e74d8ec 688 return num_insns_constant_wide (l) == 1;
042259f2 689 }
4e74d8ec
MM		 690
691 else if (mode == DImode && TARGET_32BIT)
692 return num_insns_constant (op, DImode) == 2;
693
694 else
695 abort ();
9878760c 696}
8f75773e 697
b6c9286a
MM		 698/* Return 1 if the operand is in volatile memory. Note that during the
699 RTL generation phase, memory_operand does not return TRUE for
700 volatile memory references. So this function allows us to
701 recognize volatile references where its safe. */
702
703int
704volatile_mem_operand (op, mode)
705 register rtx op;
706 enum machine_mode mode;
707{
708 if (GET_CODE (op) != MEM)
709 return 0;
710
711 if (!MEM_VOLATILE_P (op))
712 return 0;
713
714 if (mode != GET_MODE (op))
715 return 0;
716
717 if (reload_completed)
718 return memory_operand (op, mode);
719
720 if (reload_in_progress)
721 return strict_memory_address_p (mode, XEXP (op, 0));
722
723 return memory_address_p (mode, XEXP (op, 0));
724}
725
5b5040b9 726/* Return 1 if the operand is an offsettable memory address. */
914c2e77
RK		 727
728int
5b5040b9 729offsettable_addr_operand (op, mode)
914c2e77
RK		 730 register rtx op;
731 enum machine_mode mode;
732{
8f75773e 733 return offsettable_address_p (reload_completed | reload_in_progress,
5b5040b9 734 mode, op);
914c2e77
RK		 735}
736
9878760c
RK		 737/* Return 1 if the operand is either a floating-point register, a pseudo
738 register, or memory. */
739
740int
741fp_reg_or_mem_operand (op, mode)
742 register rtx op;
743 enum machine_mode mode;
744{
745 return (memory_operand (op, mode)
b6c9286a 746 || volatile_mem_operand (op, mode)
9878760c
RK		 747 || (register_operand (op, mode)
748 && (GET_CODE (op) != REG
749 || REGNO (op) >= FIRST_PSEUDO_REGISTER
750 || FP_REGNO_P (REGNO (op)))));
751}
752
753/* Return 1 if the operand is either an easy FP constant (see above) or
754 memory. */
755
756int
757mem_or_easy_const_operand (op, mode)
758 register rtx op;
759 enum machine_mode mode;
760{
761 return memory_operand (op, mode) || easy_fp_constant (op, mode);
762}
763
764/* Return 1 if the operand is either a non-special register or an item
765 that can be used as the operand of an SI add insn. */
766
767int
768add_operand (op, mode)
769 register rtx op;
770 enum machine_mode mode;
771{
772 return (reg_or_short_operand (op, mode)
773 || (GET_CODE (op) == CONST_INT && (INTVAL (op) & 0xffff) == 0));
774}
775
dcfedcd0
RK		 776/* Return 1 if OP is a constant but not a valid add_operand. */
777
778int
779non_add_cint_operand (op, mode)
780 register rtx op;
781 enum machine_mode mode;
782{
783 return (GET_CODE (op) == CONST_INT
784 && (unsigned) (INTVAL (op) + 0x8000) >= 0x10000
785 && (INTVAL (op) & 0xffff) != 0);
786}
787
9878760c
RK		 788/* Return 1 if the operand is a non-special register or a constant that
789 can be used as the operand of an OR or XOR insn on the RS/6000. */
790
791int
792logical_operand (op, mode)
793 register rtx op;
794 enum machine_mode mode;
795{
cd2b37d9 796 return (gpc_reg_operand (op, mode)
9878760c
RK		 797 || (GET_CODE (op) == CONST_INT
798 && ((INTVAL (op) & 0xffff0000) == 0
799 || (INTVAL (op) & 0xffff) == 0)));
800}
801
dcfedcd0
RK		 802/* Return 1 if C is a constant that is not a logical operand (as
803 above). */
804
805int
806non_logical_cint_operand (op, mode)
807 register rtx op;
808 enum machine_mode mode;
809{
810 return (GET_CODE (op) == CONST_INT
811 && (INTVAL (op) & 0xffff0000) != 0
812 && (INTVAL (op) & 0xffff) != 0);
813}
814
9878760c
RK		 815/* Return 1 if C is a constant that can be encoded in a mask on the
816 RS/6000. It is if there are no more than two 1->0 or 0->1 transitions.
817 Reject all ones and all zeros, since these should have been optimized
818 away and confuse the making of MB and ME. */
819
820int
821mask_constant (c)
822 register int c;
823{
824 int i;
825 int last_bit_value;
826 int transitions = 0;
827
828 if (c == 0 || c == ~0)
829 return 0;
830
831 last_bit_value = c & 1;
832
833 for (i = 1; i < 32; i++)
834 if (((c >>= 1) & 1) != last_bit_value)
835 last_bit_value ^= 1, transitions++;
836
837 return transitions <= 2;
838}
839
840/* Return 1 if the operand is a constant that is a mask on the RS/6000. */
841
842int
843mask_operand (op, mode)
844 register rtx op;
845 enum machine_mode mode;
846{
847 return GET_CODE (op) == CONST_INT && mask_constant (INTVAL (op));
848}
849
850/* Return 1 if the operand is either a non-special register or a
851 constant that can be used as the operand of an RS/6000 logical AND insn. */
852
853int
854and_operand (op, mode)
855 register rtx op;
856 enum machine_mode mode;
857{
858 return (reg_or_short_operand (op, mode)
859 || logical_operand (op, mode)
860 || mask_operand (op, mode));
861}
862
dcfedcd0
RK		 863/* Return 1 if the operand is a constant but not a valid operand for an AND
864 insn. */
865
866int
867non_and_cint_operand (op, mode)
868 register rtx op;
869 enum machine_mode mode;
870{
871 return GET_CODE (op) == CONST_INT && ! and_operand (op, mode);
872}
873
9878760c
RK		 874/* Return 1 if the operand is a general register or memory operand. */
875
876int
877reg_or_mem_operand (op, mode)
878 register rtx op;
879 register enum machine_mode mode;
880{
b6c9286a
MM		 881 return (gpc_reg_operand (op, mode)
882 || memory_operand (op, mode)
883 || volatile_mem_operand (op, mode));
9878760c
RK		 884}
885
a7a813f7
RK		 886/* Return 1 if the operand is a general register or memory operand without
887 pre-inc or pre_dec which produces invalid form of PowerPC lwa
888 instruction. */
889
890int
891lwa_operand (op, mode)
892 register rtx op;
893 register enum machine_mode mode;
894{
895 rtx inner = op;
896
897 if (reload_completed && GET_CODE (inner) == SUBREG)
898 inner = SUBREG_REG (inner);
899
900 return gpc_reg_operand (inner, mode)
901 || (memory_operand (inner, mode)
902 && GET_CODE (XEXP (inner, 0)) != PRE_INC
903 && GET_CODE (XEXP (inner, 0)) != PRE_DEC);
904}
905
9878760c
RK		 906/* Return 1 if the operand, used inside a MEM, is a valid first argument
907 to CALL. This is a SYMBOL_REF or a pseudo-register, which will be
908 forced to lr. */
909
910int
911call_operand (op, mode)
912 register rtx op;
913 enum machine_mode mode;
914{
915 if (mode != VOIDmode && GET_MODE (op) != mode)
916 return 0;
917
918 return (GET_CODE (op) == SYMBOL_REF
919 || (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER));
920}
921
2af3d377
RK		 922
923/* Return 1 if the operand is a SYMBOL_REF for a function known to be in
924 this file. */
925
926int
927current_file_function_operand (op, mode)
928 register rtx op;
929 enum machine_mode mode;
930{
931 return (GET_CODE (op) == SYMBOL_REF
932 && (SYMBOL_REF_FLAG (op)
933 || op == XEXP (DECL_RTL (current_function_decl), 0)));
934}
935
936
9878760c
RK		 937/* Return 1 if this operand is a valid input for a move insn. */
938
939int
940input_operand (op, mode)
941 register rtx op;
942 enum machine_mode mode;
943{
eb4e8003 944 /* Memory is always valid. */
9878760c
RK		 945 if (memory_operand (op, mode))
946 return 1;
947
eb4e8003
RK		 948 /* For floating-point, easy constants are valid. */
949 if (GET_MODE_CLASS (mode) == MODE_FLOAT
950 && CONSTANT_P (op)
951 && easy_fp_constant (op, mode))
952 return 1;
953
4e74d8ec
MM		 954 /* Allow any integer constant. */
955 if (GET_MODE_CLASS (mode) == MODE_INT
956 && (GET_CODE (op) == CONST_INT || GET_CODE (op) == CONST_DOUBLE))
957 return 1;
958
eb4e8003
RK		 959 /* For floating-point or multi-word mode, the only remaining valid type
960 is a register. */
9878760c
RK		 961 if (GET_MODE_CLASS (mode) == MODE_FLOAT
962 || GET_MODE_SIZE (mode) > UNITS_PER_WORD)
eb4e8003 963 return register_operand (op, mode);
9878760c 964
88fe15a1
RK		 965 /* The only cases left are integral modes one word or smaller (we
966 do not get called for MODE_CC values). These can be in any
967 register. */
968 if (register_operand (op, mode))
a8b3aeda 969 return 1;
88fe15a1 970
84cf9dda 971 /* A SYMBOL_REF referring to the TOC is valid. */
7fec4abd 972 if (LEGITIMATE_CONSTANT_POOL_ADDRESS_P (op))
84cf9dda
RK		 973 return 1;
974
b6c9286a
MM		 975 /* Windows NT allows SYMBOL_REFs and LABEL_REFs against the TOC
976 directly in the instruction stream */
977 if (DEFAULT_ABI == ABI_NT
978 && (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF))
979 return 1;
980
88228c4b
MM		 981 /* V.4 allows SYMBOL_REFs and CONSTs that are in the small data region
982 to be valid. */
c81bebd7 983 if ((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS)
88228c4b
MM		 984 && (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST)
985 && small_data_operand (op, Pmode))
986 return 1;
987
042259f2 988 return 0;
9878760c 989}
7509c759
MM		 990
991/* Return 1 for an operand in small memory on V.4/eabi */
992
993int
994small_data_operand (op, mode)
995 rtx op;
996 enum machine_mode mode;
997{
d9407988 998#ifdef TARGET_SDATA
7509c759
MM		 999 rtx sym_ref, const_part;
1000
d9407988 1001 if (rs6000_sdata == SDATA_NONE || rs6000_sdata == SDATA_DATA)
a54d04b7 1002 return 0;
a54d04b7 1003
c81bebd7 1004 if (DEFAULT_ABI != ABI_V4 /* && DEFAULT_ABI != ABI_SOLARIS */)
7509c759
MM		 1005 return 0;
1006
88228c4b
MM		 1007 if (GET_CODE (op) == SYMBOL_REF)
1008 sym_ref = op;
1009
1010 else if (GET_CODE (op) != CONST
1011 || GET_CODE (XEXP (op, 0)) != PLUS
1012 || GET_CODE (XEXP (XEXP (op, 0), 0)) != SYMBOL_REF
1013 || GET_CODE (XEXP (XEXP (op, 0), 1)) != CONST_INT)
7509c759
MM		 1014 return 0;
1015
88228c4b
MM		 1016 else
1017 sym_ref = XEXP (XEXP (op, 0), 0);
1018
1019 if (*XSTR (sym_ref, 0) != '@')
7509c759
MM		 1020 return 0;
1021
1022 return 1;
d9407988
MM		 1023
1024#else
1025 return 0;
1026#endif
7509c759
MM		 1027}
1028
4697a36c
MM		 1029\f
1030/* Initialize a variable CUM of type CUMULATIVE_ARGS
1031 for a call to a function whose data type is FNTYPE.
1032 For a library call, FNTYPE is 0.
1033
1034 For incoming args we set the number of arguments in the prototype large
1c20ae99 1035 so we never return a PARALLEL. */
4697a36c
MM		 1036
1037void
1038init_cumulative_args (cum, fntype, libname, incoming)
1039 CUMULATIVE_ARGS *cum;
1040 tree fntype;
1041 rtx libname;
1042 int incoming;
1043{
1044 static CUMULATIVE_ARGS zero_cumulative;
7509c759 1045 enum rs6000_abi abi = DEFAULT_ABI;
4697a36c
MM		 1046
1047 *cum = zero_cumulative;
1048 cum->words = 0;
1049 cum->fregno = FP_ARG_MIN_REG;
1050 cum->prototype = (fntype && TYPE_ARG_TYPES (fntype));
7509c759 1051 cum->call_cookie = CALL_NORMAL;
4697a36c
MM		 1052
1053 if (incoming)
1054 {
1c20ae99 1055 cum->nargs_prototype = 1000; /* don't return a PARALLEL */
c81bebd7 1056 if (abi == ABI_V4 || abi == ABI_SOLARIS)
4697a36c 1057 cum->varargs_offset = RS6000_VARARGS_OFFSET;
4697a36c
MM		 1058 }
1059
1060 else if (cum->prototype)
1061 cum->nargs_prototype = (list_length (TYPE_ARG_TYPES (fntype)) - 1
1062 + (TYPE_MODE (TREE_TYPE (fntype)) == BLKmode
1063 || RETURN_IN_MEMORY (TREE_TYPE (fntype))));
1064
1065 else
1066 cum->nargs_prototype = 0;
1067
1068 cum->orig_nargs = cum->nargs_prototype;
7509c759
MM		 1069
1070 /* Check for DLL import functions */
1071 if (abi == ABI_NT
1072 && fntype
1073 && lookup_attribute ("dllimport", TYPE_ATTRIBUTES (fntype)))
1074 cum->call_cookie = CALL_NT_DLLIMPORT;
1075
6a4cee5f
MM		 1076 /* Also check for longcall's */
1077 else if (fntype && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype)))
1078 cum->call_cookie = CALL_LONG;
1079
4697a36c
MM		 1080 if (TARGET_DEBUG_ARG)
1081 {
1082 fprintf (stderr, "\ninit_cumulative_args:");
1083 if (fntype)
1084 {
1085 tree ret_type = TREE_TYPE (fntype);
1086 fprintf (stderr, " ret code = %s,",
1087 tree_code_name[ (int)TREE_CODE (ret_type) ]);
1088 }
1089
c81bebd7 1090 if ((abi == ABI_V4 || abi == ABI_SOLARIS) && incoming)
4697a36c 1091 fprintf (stderr, " varargs = %d, ", cum->varargs_offset);
7509c759 1092
6a4cee5f 1093 if (cum->call_cookie & CALL_NT_DLLIMPORT)
7509c759 1094 fprintf (stderr, " dllimport,");
4697a36c 1095
6a4cee5f
MM		 1096 if (cum->call_cookie & CALL_LONG)
1097 fprintf (stderr, " longcall,");
1098
4697a36c
MM		 1099 fprintf (stderr, " proto = %d, nargs = %d\n",
1100 cum->prototype, cum->nargs_prototype);
1101 }
1102}
1103\f
b6c9286a
MM		 1104/* If defined, a C expression that gives the alignment boundary, in bits,
1105 of an argument with the specified mode and type. If it is not defined,
1106 PARM_BOUNDARY is used for all arguments.
1107
e1f83b4d
MM		 1108 Windows NT wants anything >= 8 bytes to be double word aligned.
1109
1110 V.4 wants long longs to be double word aligned. */
b6c9286a
MM		 1111
1112int
1113function_arg_boundary (mode, type)
1114 enum machine_mode mode;
1115 tree type;
1116{
c81bebd7 1117 if ((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) && mode == DImode)
e1f83b4d
MM		 1118 return 64;
1119
b6c9286a
MM		 1120 if (DEFAULT_ABI != ABI_NT || TARGET_64BIT)
1121 return PARM_BOUNDARY;
1122
1123 if (mode != BLKmode)
1124 return (GET_MODE_SIZE (mode)) >= 8 ? 64 : 32;
1125
1126 return (int_size_in_bytes (type) >= 8) ? 64 : 32;
1127}
1128\f
4697a36c
MM		 1129/* Update the data in CUM to advance over an argument
1130 of mode MODE and data type TYPE.
1131 (TYPE is null for libcalls where that information may not be available.) */
1132
1133void
1134function_arg_advance (cum, mode, type, named)
1135 CUMULATIVE_ARGS *cum;
1136 enum machine_mode mode;
1137 tree type;
1138 int named;
1139{
b6c9286a
MM		 1140 int align = ((cum->words & 1) != 0 && function_arg_boundary (mode, type) == 64) ? 1 : 0;
1141 cum->words += align;
4697a36c
MM		 1142 cum->nargs_prototype--;
1143
c81bebd7 1144 if (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS)
4697a36c
MM		 1145 {
1146 /* Long longs must not be split between registers and stack */
1147 if ((GET_MODE_CLASS (mode) != MODE_FLOAT || TARGET_SOFT_FLOAT)
1148 && type && !AGGREGATE_TYPE_P (type)
1149 && cum->words < GP_ARG_NUM_REG
1150 && cum->words + RS6000_ARG_SIZE (mode, type, named) > GP_ARG_NUM_REG)
1151 {
1152 cum->words = GP_ARG_NUM_REG;
1153 }
1154
1155 /* Aggregates get passed as pointers */
1156 if (type && AGGREGATE_TYPE_P (type))
1157 cum->words++;
1158
1159 /* Floats go in registers, & don't occupy space in the GP registers
1160 like they do for AIX unless software floating point. */
1161 else if (GET_MODE_CLASS (mode) == MODE_FLOAT
1162 && TARGET_HARD_FLOAT
1163 && cum->fregno <= FP_ARG_V4_MAX_REG)
1164 cum->fregno++;
1165
1166 else
1167 cum->words += RS6000_ARG_SIZE (mode, type, 1);
1168 }
1169 else
4697a36c
MM		 1170 if (named)
1171 {
1172 cum->words += RS6000_ARG_SIZE (mode, type, named);
1173 if (GET_MODE_CLASS (mode) == MODE_FLOAT && TARGET_HARD_FLOAT)
1174 cum->fregno++;
1175 }
1176
1177 if (TARGET_DEBUG_ARG)
1178 fprintf (stderr,
b6c9286a
MM		 1179 "function_adv: words = %2d, fregno = %2d, nargs = %4d, proto = %d, mode = %4s, named = %d, align = %d\n",
1180 cum->words, cum->fregno, cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode), named, align);
4697a36c
MM		 1181}
1182\f
1183/* Determine where to put an argument to a function.
1184 Value is zero to push the argument on the stack,
1185 or a hard register in which to store the argument.
1186
1187 MODE is the argument's machine mode.
1188 TYPE is the data type of the argument (as a tree).
1189 This is null for libcalls where that information may
1190 not be available.
1191 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1192 the preceding args and about the function being called.
1193 NAMED is nonzero if this argument is a named parameter
1194 (otherwise it is an extra parameter matching an ellipsis).
1195
1196 On RS/6000 the first eight words of non-FP are normally in registers
1197 and the rest are pushed. Under AIX, the first 13 FP args are in registers.
1198 Under V.4, the first 8 FP args are in registers.
1199
1200 If this is floating-point and no prototype is specified, we use
1201 both an FP and integer register (or possibly FP reg and stack). Library
1202 functions (when TYPE is zero) always have the proper types for args,
1203 so we can pass the FP value just in one register. emit_library_function
1c20ae99 1204 doesn't support PARALLEL anyway. */
4697a36c
MM		 1205
1206struct rtx_def *
1207function_arg (cum, mode, type, named)
1208 CUMULATIVE_ARGS *cum;
1209 enum machine_mode mode;
1210 tree type;
1211 int named;
1212{
b6c9286a
MM		 1213 int align = ((cum->words & 1) != 0 && function_arg_boundary (mode, type) == 64) ? 1 : 0;
1214 int align_words = cum->words + align;
1215
4697a36c
MM		 1216 if (TARGET_DEBUG_ARG)
1217 fprintf (stderr,
b6c9286a
MM		 1218 "function_arg: words = %2d, fregno = %2d, nargs = %4d, proto = %d, mode = %4s, named = %d, align = %d\n",
1219 cum->words, cum->fregno, cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode), named, align);
4697a36c
MM		 1220
1221 /* Return a marker to indicate whether CR1 needs to set or clear the bit that V.4
1222 uses to say fp args were passed in registers. Assume that we don't need the
1223 marker for software floating point, or compiler generated library calls. */
1224 if (mode == VOIDmode)
1225 {
7509c759
MM		 1226 enum rs6000_abi abi = DEFAULT_ABI;
1227
c81bebd7 1228 if ((abi == ABI_V4 || abi == ABI_SOLARIS)
7509c759
MM		 1229 && TARGET_HARD_FLOAT
1230 && cum->nargs_prototype < 0
4697a36c 1231 && type && (cum->prototype || TARGET_NO_PROTOTYPE))
7509c759 1232 {
6a4cee5f
MM		 1233 return GEN_INT (cum->call_cookie
1234 | ((cum->fregno == FP_ARG_MIN_REG)
1235 ? CALL_V4_SET_FP_ARGS
1236 : CALL_V4_CLEAR_FP_ARGS));
7509c759 1237 }
4697a36c 1238
7509c759 1239 return GEN_INT (cum->call_cookie);
4697a36c
MM		 1240 }
1241
1242 if (!named)
1243 {
c81bebd7 1244 if (DEFAULT_ABI != ABI_V4 && DEFAULT_ABI != ABI_SOLARIS)
4697a36c
MM		 1245 return NULL_RTX;
1246 }
1247
1248 if (type && TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST)
1249 return NULL_RTX;
1250
1251 if (USE_FP_FOR_ARG_P (*cum, mode, type))
1252 {
1253 if ((cum->nargs_prototype > 0)
c81bebd7
MM		 1254 || DEFAULT_ABI == ABI_V4 /* V.4 never passes FP values in GP registers */
1255 || DEFAULT_ABI == ABI_SOLARIS
4697a36c
MM		 1256 || !type)
1257 return gen_rtx (REG, mode, cum->fregno);
1258
1c20ae99
JW		 1259 return gen_rtx (PARALLEL, mode,
1260 gen_rtvec
1261 (2,
1262 gen_rtx (EXPR_LIST, VOIDmode,
1263 ((align_words >= GP_ARG_NUM_REG)
1264 ? NULL_RTX
1265 : (align_words
1266 + RS6000_ARG_SIZE (mode, type, named)
1267 > GP_ARG_NUM_REG
1268 /* If this is partially on the stack, then
1269 we only include the portion actually
1270 in registers here. */
1271 ? gen_rtx (REG, SImode,
1272 GP_ARG_MIN_REG + align_words)
1273 : gen_rtx (REG, mode,
1274 GP_ARG_MIN_REG + align_words))),
1275 const0_rtx),
1276 gen_rtx (EXPR_LIST, VOIDmode,
1277 gen_rtx (REG, mode, cum->fregno),
1278 const0_rtx)));
4697a36c
MM		 1279 }
1280
4697a36c 1281 /* Long longs won't be split between register and stack */
c81bebd7 1282 else if ((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) &&
b6c9286a 1283 align_words + RS6000_ARG_SIZE (mode, type, named) > GP_ARG_NUM_REG)
4697a36c
MM		 1284 {
1285 return NULL_RTX;
1286 }
4697a36c 1287
b6c9286a
MM		 1288 else if (align_words < GP_ARG_NUM_REG)
1289 return gen_rtx (REG, mode, GP_ARG_MIN_REG + align_words);
4697a36c
MM		 1290
1291 return NULL_RTX;
1292}
1293\f
1294/* For an arg passed partly in registers and partly in memory,
1295 this is the number of registers used.
1296 For args passed entirely in registers or entirely in memory, zero. */
1297
1298int
1299function_arg_partial_nregs (cum, mode, type, named)
1300 CUMULATIVE_ARGS *cum;
1301 enum machine_mode mode;
1302 tree type;
1303 int named;
1304{
1305 if (! named)
1306 return 0;
1307
c81bebd7 1308 if (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS)
4697a36c 1309 return 0;
4697a36c
MM		 1310
1311 if (USE_FP_FOR_ARG_P (*cum, mode, type))
1312 {
1313 if (cum->nargs_prototype >= 0)
1314 return 0;
1315 }
1316
1317 if (cum->words < GP_ARG_NUM_REG
1318 && GP_ARG_NUM_REG < (cum->words + RS6000_ARG_SIZE (mode, type, named)))
1319 {
1320 int ret = GP_ARG_NUM_REG - cum->words;
1321 if (ret && TARGET_DEBUG_ARG)
1322 fprintf (stderr, "function_arg_partial_nregs: %d\n", ret);
1323
1324 return ret;
1325 }
1326
1327 return 0;
1328}
1329\f
1330/* A C expression that indicates when an argument must be passed by
1331 reference. If nonzero for an argument, a copy of that argument is
1332 made in memory and a pointer to the argument is passed instead of
1333 the argument itself. The pointer is passed in whatever way is
1334 appropriate for passing a pointer to that type.
1335
1336 Under V.4, structures and unions are passed by reference. */
1337
1338int
1339function_arg_pass_by_reference (cum, mode, type, named)
1340 CUMULATIVE_ARGS *cum;
1341 enum machine_mode mode;
1342 tree type;
1343 int named;
1344{
c81bebd7
MM		 1345 if ((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS)
1346 && type && AGGREGATE_TYPE_P (type))
4697a36c
MM		 1347 {
1348 if (TARGET_DEBUG_ARG)
1349 fprintf (stderr, "function_arg_pass_by_reference: aggregate\n");
1350
1351 return 1;
1352 }
4697a36c
MM		 1353
1354 return 0;
1355}
1356
1357\f
1358/* Perform any needed actions needed for a function that is receiving a
1359 variable number of arguments.
1360
1361 CUM is as above.
1362
1363 MODE and TYPE are the mode and type of the current parameter.
1364
1365 PRETEND_SIZE is a variable that should be set to the amount of stack
1366 that must be pushed by the prolog to pretend that our caller pushed
1367 it.
1368
1369 Normally, this macro will push all remaining incoming registers on the
1370 stack and set PRETEND_SIZE to the length of the registers pushed. */
1371
1372void
1373setup_incoming_varargs (cum, mode, type, pretend_size, no_rtl)
1374 CUMULATIVE_ARGS *cum;
1375 enum machine_mode mode;
1376 tree type;
1377 int *pretend_size;
1378 int no_rtl;
1379
1380{
1381 rtx save_area = virtual_incoming_args_rtx;
1382 int reg_size = (TARGET_64BIT) ? 8 : 4;
1383
1384 if (TARGET_DEBUG_ARG)
1385 fprintf (stderr,
1386 "setup_vararg: words = %2d, fregno = %2d, nargs = %4d, proto = %d, mode = %4s, no_rtl= %d\n",
1387 cum->words, cum->fregno, cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode), no_rtl);
1388
c81bebd7 1389 if ((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) && !no_rtl)
4697a36c
MM		 1390 {
1391 rs6000_sysv_varargs_p = 1;
1392 save_area = plus_constant (frame_pointer_rtx, RS6000_VARARGS_OFFSET);
1393 }
4697a36c
MM		 1394
1395 if (cum->words < 8)
1396 {
1397 int first_reg_offset = cum->words;
1398
1399 if (MUST_PASS_IN_STACK (mode, type))
1400 first_reg_offset += RS6000_ARG_SIZE (TYPE_MODE (type), type, 1);
1401
1402 if (first_reg_offset > GP_ARG_NUM_REG)
1403 first_reg_offset = GP_ARG_NUM_REG;
1404
1405 if (!no_rtl && first_reg_offset != GP_ARG_NUM_REG)
1406 move_block_from_reg
1407 (GP_ARG_MIN_REG + first_reg_offset,
1408 gen_rtx (MEM, BLKmode,
1409 plus_constant (save_area, first_reg_offset * reg_size)),
1410 GP_ARG_NUM_REG - first_reg_offset,
1411 (GP_ARG_NUM_REG - first_reg_offset) * UNITS_PER_WORD);
1412
1413 *pretend_size = (GP_ARG_NUM_REG - first_reg_offset) * UNITS_PER_WORD;
1414 }
1415
4697a36c 1416 /* Save FP registers if needed. */
c81bebd7 1417 if ((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) && TARGET_HARD_FLOAT && !no_rtl)
4697a36c
MM		 1418 {
1419 int fregno = cum->fregno;
1420 int num_fp_reg = FP_ARG_V4_MAX_REG + 1 - fregno;
1421
1422 if (num_fp_reg >= 0)
1423 {
1424 rtx cr1 = gen_rtx (REG, CCmode, 69);
1425 rtx lab = gen_label_rtx ();
1426 int off = (GP_ARG_NUM_REG * reg_size) + ((fregno - FP_ARG_MIN_REG) * 8);
1427
1428 emit_jump_insn (gen_rtx (SET, VOIDmode,
1429 pc_rtx,
1430 gen_rtx (IF_THEN_ELSE, VOIDmode,
1431 gen_rtx (NE, VOIDmode, cr1, const0_rtx),
1432 gen_rtx (LABEL_REF, VOIDmode, lab),
1433 pc_rtx)));
1434
1435 while ( num_fp_reg-- >= 0)
1436 {
1437 emit_move_insn (gen_rtx (MEM, DFmode, plus_constant (save_area, off)),
1438 gen_rtx (REG, DFmode, fregno++));
1439 off += 8;
1440 }
1441
1442 emit_label (lab);
1443 }
1444 }
4697a36c
MM		 1445}
1446\f
1447/* If defined, is a C expression that produces the machine-specific
1448 code for a call to `__builtin_saveregs'. This code will be moved
1449 to the very beginning of the function, before any parameter access
1450 are made. The return value of this function should be an RTX that
1451 contains the value to use as the return of `__builtin_saveregs'.
1452
1453 The argument ARGS is a `tree_list' containing the arguments that
1454 were passed to `__builtin_saveregs'.
1455
1456 If this macro is not defined, the compiler will output an ordinary
1457 call to the library function `__builtin_saveregs'.
1458
1459 On the Power/PowerPC return the address of the area on the stack
1460 used to hold arguments. Under AIX, this includes the 8 word register
1461 save area. Under V.4 this does not. */
1462
1463struct rtx_def *
1464expand_builtin_saveregs (args)
1465 tree args;
1466{
1467 return virtual_incoming_args_rtx;
1468}
1469
5b5040b9
RK		 1470\f
1471/* Generate a memory reference for expand_block_move, copying volatile,
1472 and other bits from an original memory reference. */
1473
1474static rtx
1475expand_block_move_mem (mode, addr, orig_mem)
1476 enum machine_mode mode;
1477 rtx addr;
1478 rtx orig_mem;
1479{
1480 rtx mem = gen_rtx (MEM, mode, addr);
b6c9286a
MM		 1481
1482 RTX_UNCHANGING_P (mem) = RTX_UNCHANGING_P (orig_mem);
5b5040b9
RK		 1483 MEM_VOLATILE_P (mem) = MEM_VOLATILE_P (orig_mem);
1484 MEM_IN_STRUCT_P (mem) = MEM_IN_STRUCT_P (orig_mem);
b6c9286a
MM		 1485#ifdef MEM_UNALIGNED_P
1486 MEM_UNALIGNED_P (mem) = MEM_UNALIGNED_P (orig_mem);
1487#endif
5b5040b9
RK		 1488 return mem;
1489}
1490
7e69e155
MM		 1491/* Expand a block move operation, and return 1 if successful. Return 0
1492 if we should let the compiler generate normal code.
1493
1494 operands[0] is the destination
1495 operands[1] is the source
1496 operands[2] is the length
1497 operands[3] is the alignment */
1498
3933e0e1
MM		 1499#define MAX_MOVE_REG 4
1500
7e69e155
MM		 1501int
1502expand_block_move (operands)
1503 rtx operands[];
1504{
b6c9286a
MM		 1505 rtx orig_dest = operands[0];
1506 rtx orig_src = operands[1];
7e69e155 1507 rtx bytes_rtx = operands[2];
7e69e155 1508 rtx align_rtx = operands[3];
3933e0e1 1509 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
7e69e155 1510 int align = XINT (align_rtx, 0);
3933e0e1
MM		 1511 int bytes;
1512 int offset;
1513 int num_reg;
1514 int i;
7e69e155
MM		 1515 rtx src_reg;
1516 rtx dest_reg;
3933e0e1
MM		 1517 rtx src_addr;
1518 rtx dest_addr;
7e69e155 1519 rtx tmp_reg;
3933e0e1 1520 rtx stores[MAX_MOVE_REG];
7e69e155
MM		 1521 int move_bytes;
1522
3933e0e1
MM		 1523 /* If this is not a fixed size move, just call memcpy */
1524 if (!constp)
1525 return 0;
1526
7e69e155 1527 /* Anything to move? */
3933e0e1
MM		 1528 bytes = INTVAL (bytes_rtx);
1529 if (bytes <= 0)
7e69e155
MM		 1530 return 1;
1531
3933e0e1
MM		 1532 /* Don't support real large moves. If string instructions are not used,
1533 then don't generate more than 8 loads. */
1534 if (TARGET_STRING)
1535 {
1cab3be1 1536 if (bytes > 4*8)
3933e0e1
MM		 1537 return 0;
1538 }
1539 else if (!STRICT_ALIGNMENT)
1540 {
1541 if (bytes > 4*8)
1542 return 0;
1543 }
1544 else if (bytes > 8*align)
7e69e155
MM		 1545 return 0;
1546
1547 /* Move the address into scratch registers. */
b6c9286a
MM		 1548 dest_reg = copy_addr_to_reg (XEXP (orig_dest, 0));
1549 src_reg = copy_addr_to_reg (XEXP (orig_src, 0));
7e69e155 1550
3933e0e1 1551 if (TARGET_STRING) /* string instructions are available */
7e69e155 1552 {
3933e0e1 1553 for ( ; bytes > 0; bytes -= move_bytes)
7e69e155 1554 {
3933e0e1
MM		 1555 if (bytes > 24 /* move up to 32 bytes at a time */
1556 && !fixed_regs[5]
1557 && !fixed_regs[6]
1558 && !fixed_regs[7]
1559 && !fixed_regs[8]
1560 && !fixed_regs[9]
1561 && !fixed_regs[10]
1562 && !fixed_regs[11]
1563 && !fixed_regs[12])
1564 {
1565 move_bytes = (bytes > 32) ? 32 : bytes;
b6c9286a
MM		 1566 emit_insn (gen_movstrsi_8reg (expand_block_move_mem (BLKmode, dest_reg, orig_dest),
1567 expand_block_move_mem (BLKmode, src_reg, orig_src),
3933e0e1 1568 GEN_INT ((move_bytes == 32) ? 0 : move_bytes),
4c64a852 1569 align_rtx));
3933e0e1
MM		 1570 }
1571 else if (bytes > 16 /* move up to 24 bytes at a time */
1572 && !fixed_regs[7]
1573 && !fixed_regs[8]
1574 && !fixed_regs[9]
1575 && !fixed_regs[10]
1576 && !fixed_regs[11]
1577 && !fixed_regs[12])
1578 {
1579 move_bytes = (bytes > 24) ? 24 : bytes;
b6c9286a
MM		 1580 emit_insn (gen_movstrsi_6reg (expand_block_move_mem (BLKmode, dest_reg, orig_dest),
1581 expand_block_move_mem (BLKmode, src_reg, orig_src),
3933e0e1 1582 GEN_INT (move_bytes),
4c64a852 1583 align_rtx));
3933e0e1
MM		 1584 }
1585 else if (bytes > 8 /* move up to 16 bytes at a time */
1586 && !fixed_regs[9]
1587 && !fixed_regs[10]
1588 && !fixed_regs[11]
1589 && !fixed_regs[12])
1590 {
1591 move_bytes = (bytes > 16) ? 16 : bytes;
b6c9286a
MM		 1592 emit_insn (gen_movstrsi_4reg (expand_block_move_mem (BLKmode, dest_reg, orig_dest),
1593 expand_block_move_mem (BLKmode, src_reg, orig_src),
3933e0e1 1594 GEN_INT (move_bytes),
4c64a852 1595 align_rtx));
3933e0e1 1596 }
d679bebf 1597 else if (bytes > 4 && !TARGET_64BIT)
3933e0e1
MM		 1598 { /* move up to 8 bytes at a time */
1599 move_bytes = (bytes > 8) ? 8 : bytes;
b6c9286a
MM		 1600 emit_insn (gen_movstrsi_2reg (expand_block_move_mem (BLKmode, dest_reg, orig_dest),
1601 expand_block_move_mem (BLKmode, src_reg, orig_src),
3933e0e1 1602 GEN_INT (move_bytes),
4c64a852 1603 align_rtx));
3933e0e1
MM		 1604 }
1605 else if (bytes >= 4 && (align >= 4 || !STRICT_ALIGNMENT))
1606 { /* move 4 bytes */
1607 move_bytes = 4;
1608 tmp_reg = gen_reg_rtx (SImode);
b6c9286a
MM		 1609 emit_move_insn (tmp_reg, expand_block_move_mem (SImode, src_reg, orig_src));
1610 emit_move_insn (expand_block_move_mem (SImode, dest_reg, orig_dest), tmp_reg);
3933e0e1
MM		 1611 }
1612 else if (bytes == 2 && (align >= 2 || !STRICT_ALIGNMENT))
1613 { /* move 2 bytes */
1614 move_bytes = 2;
1615 tmp_reg = gen_reg_rtx (HImode);
b6c9286a
MM		 1616 emit_move_insn (tmp_reg, expand_block_move_mem (HImode, src_reg, orig_src));
1617 emit_move_insn (expand_block_move_mem (HImode, dest_reg, orig_dest), tmp_reg);
3933e0e1
MM		 1618 }
1619 else if (bytes == 1) /* move 1 byte */
1620 {
1621 move_bytes = 1;
1622 tmp_reg = gen_reg_rtx (QImode);
b6c9286a
MM		 1623 emit_move_insn (tmp_reg, expand_block_move_mem (QImode, src_reg, orig_src));
1624 emit_move_insn (expand_block_move_mem (QImode, dest_reg, orig_dest), tmp_reg);
3933e0e1
MM		 1625 }
1626 else
1627 { /* move up to 4 bytes at a time */
1628 move_bytes = (bytes > 4) ? 4 : bytes;
b6c9286a
MM		 1629 emit_insn (gen_movstrsi_1reg (expand_block_move_mem (BLKmode, dest_reg, orig_dest),
1630 expand_block_move_mem (BLKmode, src_reg, orig_src),
3933e0e1 1631 GEN_INT (move_bytes),
4c64a852 1632 align_rtx));
3933e0e1 1633 }
4c64a852 1634
015892ee
RK		 1635 if (bytes > move_bytes)
1636 {
1637 emit_insn (gen_addsi3 (src_reg, src_reg, GEN_INT (move_bytes)));
1638 emit_insn (gen_addsi3 (dest_reg, dest_reg, GEN_INT (move_bytes)));
1639 }
4c64a852 1640 }
3933e0e1
MM		 1641 }
1642
1643 else /* string instructions not available */
1644 {
1645 num_reg = offset = 0;
1646 for ( ; bytes > 0; (bytes -= move_bytes), (offset += move_bytes))
7e69e155 1647 {
3933e0e1
MM		 1648 /* Calculate the correct offset for src/dest */
1649 if (offset == 0)
7e69e155 1650 {
3933e0e1
MM		 1651 src_addr = src_reg;
1652 dest_addr = dest_reg;
1653 }
1654 else
1655 {
1656 src_addr = gen_rtx (PLUS, Pmode, src_reg, GEN_INT (offset));
1657 dest_addr = gen_rtx (PLUS, Pmode, dest_reg, GEN_INT (offset));
1658 }
1659
1660 /* Generate the appropriate load and store, saving the stores for later */
b6c9286a
MM		 1661 if (bytes >= 8 && TARGET_64BIT && (align >= 8 || !STRICT_ALIGNMENT))
1662 {
1663 move_bytes = 8;
1664 tmp_reg = gen_reg_rtx (DImode);
1665 emit_insn (gen_movdi (tmp_reg, expand_block_move_mem (DImode, src_addr, orig_src)));
1666 stores[ num_reg++ ] = gen_movdi (expand_block_move_mem (DImode, dest_addr, orig_dest), tmp_reg);
1667 }
1668 else if (bytes >= 4 && (align >= 4 || !STRICT_ALIGNMENT))
3933e0e1
MM		 1669 {
1670 move_bytes = 4;
1671 tmp_reg = gen_reg_rtx (SImode);
b6c9286a
MM		 1672 emit_insn (gen_movsi (tmp_reg, expand_block_move_mem (SImode, src_addr, orig_src)));
1673 stores[ num_reg++ ] = gen_movsi (expand_block_move_mem (SImode, dest_addr, orig_dest), tmp_reg);
3933e0e1
MM		 1674 }
1675 else if (bytes >= 2 && (align >= 2 || !STRICT_ALIGNMENT))
1676 {
1677 move_bytes = 2;
1678 tmp_reg = gen_reg_rtx (HImode);
b6c9286a
MM		 1679 emit_insn (gen_movsi (tmp_reg, expand_block_move_mem (HImode, src_addr, orig_src)));
1680 stores[ num_reg++ ] = gen_movhi (expand_block_move_mem (HImode, dest_addr, orig_dest), tmp_reg);
3933e0e1
MM		 1681 }
1682 else
1683 {
1684 move_bytes = 1;
1685 tmp_reg = gen_reg_rtx (QImode);
b6c9286a
MM		 1686 emit_insn (gen_movsi (tmp_reg, expand_block_move_mem (QImode, src_addr, orig_src)));
1687 stores[ num_reg++ ] = gen_movqi (expand_block_move_mem (QImode, dest_addr, orig_dest), tmp_reg);
3933e0e1
MM		 1688 }
1689
1690 if (num_reg >= MAX_MOVE_REG)
1691 {
1692 for (i = 0; i < num_reg; i++)
1693 emit_insn (stores[i]);
1694 num_reg = 0;
7e69e155
MM		 1695 }
1696 }
3933e0e1 1697
b6c9286a
MM		 1698 for (i = 0; i < num_reg; i++)
1699 emit_insn (stores[i]);
7e69e155
MM		 1700 }
1701
1702 return 1;
1703}
1704
9878760c
RK		 1705\f
1706/* Return 1 if OP is a load multiple operation. It is known to be a
1707 PARALLEL and the first section will be tested. */
1708
1709int
1710load_multiple_operation (op, mode)
1711 rtx op;
1712 enum machine_mode mode;
1713{
1714 int count = XVECLEN (op, 0);
1715 int dest_regno;
1716 rtx src_addr;
1717 int i;
1718
1719 /* Perform a quick check so we don't blow up below. */
1720 if (count <= 1
1721 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1722 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
1723 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM)
1724 return 0;
1725
1726 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
1727 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0);
1728
1729 for (i = 1; i < count; i++)
1730 {
1731 rtx elt = XVECEXP (op, 0, i);
1732
1733 if (GET_CODE (elt) != SET
1734 || GET_CODE (SET_DEST (elt)) != REG
1735 || GET_MODE (SET_DEST (elt)) != SImode
1736 || REGNO (SET_DEST (elt)) != dest_regno + i
1737 || GET_CODE (SET_SRC (elt)) != MEM
1738 || GET_MODE (SET_SRC (elt)) != SImode
1739 || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
1740 || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
1741 || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT
1742 || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != i * 4)
1743 return 0;
1744 }
1745
1746 return 1;
1747}
1748
1749/* Similar, but tests for store multiple. Here, the second vector element
1750 is a CLOBBER. It will be tested later. */
1751
1752int
1753store_multiple_operation (op, mode)
1754 rtx op;
1755 enum machine_mode mode;
1756{
1757 int count = XVECLEN (op, 0) - 1;
1758 int src_regno;
1759 rtx dest_addr;
1760 int i;
1761
1762 /* Perform a quick check so we don't blow up below. */
1763 if (count <= 1
1764 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1765 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
1766 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG)
1767 return 0;
1768
1769 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
1770 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0);
1771
1772 for (i = 1; i < count; i++)
1773 {
1774 rtx elt = XVECEXP (op, 0, i + 1);
1775
1776 if (GET_CODE (elt) != SET
1777 || GET_CODE (SET_SRC (elt)) != REG
1778 || GET_MODE (SET_SRC (elt)) != SImode
1779 || REGNO (SET_SRC (elt)) != src_regno + i
1780 || GET_CODE (SET_DEST (elt)) != MEM
1781 || GET_MODE (SET_DEST (elt)) != SImode
1782 || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
1783 || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
1784 || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT
1785 || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != i * 4)
1786 return 0;
1787 }
1788
1789 return 1;
1790}
1791\f
1792/* Return 1 if OP is a comparison operation that is valid for a branch insn.
1793 We only check the opcode against the mode of the CC value here. */
1794
1795int
1796branch_comparison_operator (op, mode)
1797 register rtx op;
1798 enum machine_mode mode;
1799{
1800 enum rtx_code code = GET_CODE (op);
1801 enum machine_mode cc_mode;
1802
1803 if (GET_RTX_CLASS (code) != '<')
1804 return 0;
1805
1806 cc_mode = GET_MODE (XEXP (op, 0));
1807 if (GET_MODE_CLASS (cc_mode) != MODE_CC)
1808 return 0;
1809
1810 if ((code == GT || code == LT || code == GE || code == LE)
1811 && cc_mode == CCUNSmode)
1812 return 0;
1813
1814 if ((code == GTU || code == LTU || code == GEU || code == LEU)
1815 && (cc_mode != CCUNSmode))
1816 return 0;
1817
1818 return 1;
1819}
1820
1821/* Return 1 if OP is a comparison operation that is valid for an scc insn.
1822 We check the opcode against the mode of the CC value and disallow EQ or
1823 NE comparisons for integers. */
1824
1825int
1826scc_comparison_operator (op, mode)
1827 register rtx op;
1828 enum machine_mode mode;
1829{
1830 enum rtx_code code = GET_CODE (op);
1831 enum machine_mode cc_mode;
1832
1833 if (GET_MODE (op) != mode && mode != VOIDmode)
1834 return 0;
1835
1836 if (GET_RTX_CLASS (code) != '<')
1837 return 0;
1838
1839 cc_mode = GET_MODE (XEXP (op, 0));
1840 if (GET_MODE_CLASS (cc_mode) != MODE_CC)
1841 return 0;
1842
1843 if (code == NE && cc_mode != CCFPmode)
1844 return 0;
1845
1846 if ((code == GT || code == LT || code == GE || code == LE)
1847 && cc_mode == CCUNSmode)
1848 return 0;
1849
1850 if ((code == GTU || code == LTU || code == GEU || code == LEU)
1851 && (cc_mode != CCUNSmode))
1852 return 0;
1853
c5defebb
RK		 1854 if (cc_mode == CCEQmode && code != EQ && code != NE)
1855 return 0;
1856
9878760c
RK		 1857 return 1;
1858}
1859\f
1860/* Return 1 if ANDOP is a mask that has no bits on that are not in the
1861 mask required to convert the result of a rotate insn into a shift
1862 left insn of SHIFTOP bits. Both are known to be CONST_INT. */
1863
1864int
1865includes_lshift_p (shiftop, andop)
1866 register rtx shiftop;
1867 register rtx andop;
1868{
1869 int shift_mask = (~0 << INTVAL (shiftop));
1870
1871 return (INTVAL (andop) & ~shift_mask) == 0;
1872}
1873
1874/* Similar, but for right shift. */
1875
1876int
1877includes_rshift_p (shiftop, andop)
1878 register rtx shiftop;
1879 register rtx andop;
1880{
802a0058 1881 unsigned shift_mask = ~(unsigned)0;
9878760c
RK		 1882
1883 shift_mask >>= INTVAL (shiftop);
1884
1885 return (INTVAL (andop) & ~ shift_mask) == 0;
1886}
35068b43
RK		 1887
1888/* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates
1889 for lfq and stfq insns.
1890
1891 Note reg1 and reg2 *must* be hard registers. To be sure we will
1892 abort if we are passed pseudo registers. */
1893
1894int
1895registers_ok_for_quad_peep (reg1, reg2)
1896 rtx reg1, reg2;
1897{
1898 /* We might have been passed a SUBREG. */
1899 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
1900 return 0;
1901
1902 return (REGNO (reg1) == REGNO (reg2) - 1);
1903}
1904
1905/* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn. addr1 and
1906 addr2 must be in consecutive memory locations (addr2 == addr1 + 8). */
1907
1908int
1909addrs_ok_for_quad_peep (addr1, addr2)
1910 register rtx addr1;
1911 register rtx addr2;
1912{
1913 int reg1;
1914 int offset1;
1915
1916 /* Extract an offset (if used) from the first addr. */
1917 if (GET_CODE (addr1) == PLUS)
1918 {
1919 /* If not a REG, return zero. */
1920 if (GET_CODE (XEXP (addr1, 0)) != REG)
1921 return 0;
1922 else
1923 {
1924 reg1 = REGNO (XEXP (addr1, 0));
1925 /* The offset must be constant! */
1926 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
1927 return 0;
1928 offset1 = INTVAL (XEXP (addr1, 1));
1929 }
1930 }
1931 else if (GET_CODE (addr1) != REG)
1932 return 0;
1933 else
1934 {
1935 reg1 = REGNO (addr1);
1936 /* This was a simple (mem (reg)) expression. Offset is 0. */
1937 offset1 = 0;
1938 }
1939
1940 /* Make sure the second address is a (mem (plus (reg) (const_int). */
1941 if (GET_CODE (addr2) != PLUS)
1942 return 0;
1943
1944 if (GET_CODE (XEXP (addr2, 0)) != REG
1945 || GET_CODE (XEXP (addr2, 1)) != CONST_INT)
1946 return 0;
1947
1948 if (reg1 != REGNO (XEXP (addr2, 0)))
1949 return 0;
1950
1951 /* The offset for the second addr must be 8 more than the first addr. */
1952 if (INTVAL (XEXP (addr2, 1)) != offset1 + 8)
1953 return 0;
1954
1955 /* All the tests passed. addr1 and addr2 are valid for lfq or stfq
1956 instructions. */
1957 return 1;
1958}
9878760c
RK		 1959\f
1960/* Return the register class of a scratch register needed to copy IN into
1961 or out of a register in CLASS in MODE. If it can be done directly,
1962 NO_REGS is returned. */
1963
1964enum reg_class
1965secondary_reload_class (class, mode, in)
1966 enum reg_class class;
1967 enum machine_mode mode;
1968 rtx in;
1969{
1970 int regno = true_regnum (in);
1971
1972 if (regno >= FIRST_PSEUDO_REGISTER)
1973 regno = -1;
1974
1975 /* We can place anything into GENERAL_REGS and can put GENERAL_REGS
1976 into anything. */
1977 if (class == GENERAL_REGS || class == BASE_REGS
1978 || (regno >= 0 && INT_REGNO_P (regno)))
1979 return NO_REGS;
1980
1981 /* Constants, memory, and FP registers can go into FP registers. */
1982 if ((regno == -1 || FP_REGNO_P (regno))
1983 && (class == FLOAT_REGS || class == NON_SPECIAL_REGS))
1984 return NO_REGS;
1985
1986 /* We can copy among the CR registers. */
1987 if ((class == CR_REGS || class == CR0_REGS)
1988 && regno >= 0 && CR_REGNO_P (regno))
1989 return NO_REGS;
1990
1991 /* Otherwise, we need GENERAL_REGS. */
1992 return GENERAL_REGS;
1993}
1994\f
1995/* Given a comparison operation, return the bit number in CCR to test. We
1996 know this is a valid comparison.
1997
1998 SCC_P is 1 if this is for an scc. That means that %D will have been
1999 used instead of %C, so the bits will be in different places.
2000
b4ac57ab 2001 Return -1 if OP isn't a valid comparison for some reason. */
9878760c
RK		 2002
2003int
2004ccr_bit (op, scc_p)
2005 register rtx op;
2006 int scc_p;
2007{
2008 enum rtx_code code = GET_CODE (op);
2009 enum machine_mode cc_mode;
2010 int cc_regnum;
2011 int base_bit;
2012
2013 if (GET_RTX_CLASS (code) != '<')
2014 return -1;
2015
2016 cc_mode = GET_MODE (XEXP (op, 0));
2017 cc_regnum = REGNO (XEXP (op, 0));
2018 base_bit = 4 * (cc_regnum - 68);
2019
c5defebb
RK		 2020 /* In CCEQmode cases we have made sure that the result is always in the
2021 third bit of the CR field. */
2022
2023 if (cc_mode == CCEQmode)
2024 return base_bit + 3;
2025
9878760c
RK		 2026 switch (code)
2027 {
2028 case NE:
2029 return scc_p ? base_bit + 3 : base_bit + 2;
2030 case EQ:
2031 return base_bit + 2;
2032 case GT: case GTU:
2033 return base_bit + 1;
2034 case LT: case LTU:
2035 return base_bit;
2036
2037 case GE: case GEU:
2038 /* If floating-point, we will have done a cror to put the bit in the
2039 unordered position. So test that bit. For integer, this is ! LT
2040 unless this is an scc insn. */
2041 return cc_mode == CCFPmode || scc_p ? base_bit + 3 : base_bit;
2042
2043 case LE: case LEU:
2044 return cc_mode == CCFPmode || scc_p ? base_bit + 3 : base_bit + 1;
2045
2046 default:
2047 abort ();
2048 }
2049}
2050\f
2051/* Print an operand. Recognize special options, documented below. */
2052
d9407988
MM		 2053#ifdef TARGET_SDATA
2054#define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel")
ba5e43aa
MM		 2055#else
2056#define SMALL_DATA_RELOC "sda21"
2057#endif
2058
9878760c
RK		 2059void
2060print_operand (file, x, code)
2061 FILE *file;
2062 rtx x;
2063 char code;
2064{
2065 int i;
2066 int val;
2067
2068 /* These macros test for integers and extract the low-order bits. */
2069#define INT_P(X) \
2070((GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST_DOUBLE) \
2071 && GET_MODE (X) == VOIDmode)
2072
2073#define INT_LOWPART(X) \
2074 (GET_CODE (X) == CONST_INT ? INTVAL (X) : CONST_DOUBLE_LOW (X))
2075
2076 switch (code)
2077 {
a8b3aeda 2078 case '.':
a85d226b
RK		 2079 /* Write out an instruction after the call which may be replaced
2080 with glue code by the loader. This depends on the AIX version. */
2081 asm_fprintf (file, RS6000_CALL_GLUE);
a8b3aeda
RK		 2082 return;
2083
cfaaaf2e
RK		 2084 case '*':
2085 /* Write the register number of the TOC register. */
4697a36c 2086 fputs (TARGET_MINIMAL_TOC ? reg_names[30] : reg_names[2], file);
cfaaaf2e
RK		 2087 return;
2088
c81bebd7
MM		 2089 case '$':
2090 /* Write out either a '.' or '$' for the current location, depending
2091 on whether this is Solaris or not. */
2092 putc ((DEFAULT_ABI == ABI_SOLARIS) ? '.' : '$', file);
2093 return;
2094
9854d9ed
RK		 2095 case 'A':
2096 /* If X is a constant integer whose low-order 5 bits are zero,
2097 write 'l'. Otherwise, write 'r'. This is a kludge to fix a bug
76229ac8 2098 in the AIX assembler where "sri" with a zero shift count
9854d9ed
RK		 2099 write a trash instruction. */
2100 if (GET_CODE (x) == CONST_INT && (INTVAL (x) & 31) == 0)
76229ac8 2101 putc ('l', file);
9854d9ed 2102 else
76229ac8 2103 putc ('r', file);
9854d9ed
RK		 2104 return;
2105
2106 case 'b':
2107 /* Low-order 16 bits of constant, unsigned. */
cad12a8d 2108 if (! INT_P (x))
9854d9ed 2109 output_operand_lossage ("invalid %%b value");
cad12a8d 2110
9854d9ed 2111 fprintf (file, "%d", INT_LOWPART (x) & 0xffff);
cad12a8d
RK		 2112 return;
2113
9854d9ed
RK		 2114 case 'C':
2115 /* This is an optional cror needed for LE or GE floating-point
2116 comparisons. Otherwise write nothing. */
2117 if ((GET_CODE (x) == LE || GET_CODE (x) == GE)
2118 && GET_MODE (XEXP (x, 0)) == CCFPmode)
2119 {
2120 int base_bit = 4 * (REGNO (XEXP (x, 0)) - 68);
2121
2122 fprintf (file, "cror %d,%d,%d\n\t", base_bit + 3,
2123 base_bit + 2, base_bit + (GET_CODE (x) == GE));
2124 }
2125 return;
2126
2127 case 'D':
2128 /* Similar, except that this is for an scc, so we must be able to
2129 encode the test in a single bit that is one. We do the above
2130 for any LE, GE, GEU, or LEU and invert the bit for NE. */
2131 if (GET_CODE (x) == LE || GET_CODE (x) == GE
2132 || GET_CODE (x) == LEU || GET_CODE (x) == GEU)
2133 {
2134 int base_bit = 4 * (REGNO (XEXP (x, 0)) - 68);
2135
2136 fprintf (file, "cror %d,%d,%d\n\t", base_bit + 3,
2137 base_bit + 2,
2138 base_bit + (GET_CODE (x) == GE || GET_CODE (x) == GEU));
2139 }
2140
2141 else if (GET_CODE (x) == NE)
2142 {
2143 int base_bit = 4 * (REGNO (XEXP (x, 0)) - 68);
2144
2145 fprintf (file, "crnor %d,%d,%d\n\t", base_bit + 3,
2146 base_bit + 2, base_bit + 2);
2147 }
2148 return;
2149
2150 case 'E':
2151 /* X is a CR register. Print the number of the third bit of the CR */
2152 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
2153 output_operand_lossage ("invalid %%E value");
2154
2155 fprintf(file, "%d", 4 * (REGNO (x) - 68) + 3);
a85d226b 2156 return;
9854d9ed
RK		 2157
2158 case 'f':
2159 /* X is a CR register. Print the shift count needed to move it
2160 to the high-order four bits. */
2161 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
2162 output_operand_lossage ("invalid %%f value");
2163 else
2164 fprintf (file, "%d", 4 * (REGNO (x) - 68));
2165 return;
2166
2167 case 'F':
2168 /* Similar, but print the count for the rotate in the opposite
2169 direction. */
2170 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
2171 output_operand_lossage ("invalid %%F value");
2172 else
2173 fprintf (file, "%d", 32 - 4 * (REGNO (x) - 68));
2174 return;
2175
2176 case 'G':
2177 /* X is a constant integer. If it is negative, print "m",
2178 otherwise print "z". This is to make a aze or ame insn. */
2179 if (GET_CODE (x) != CONST_INT)
2180 output_operand_lossage ("invalid %%G value");
2181 else if (INTVAL (x) >= 0)
76229ac8 2182 putc ('z', file);
9854d9ed 2183 else
76229ac8 2184 putc ('m', file);
9854d9ed
RK		 2185 return;
2186
9878760c 2187 case 'h':
df3d94ed
RK		 2188 /* If constant, output low-order five bits. Otherwise,
2189 write normally. */
9878760c
RK		 2190 if (INT_P (x))
2191 fprintf (file, "%d", INT_LOWPART (x) & 31);
2192 else
2193 print_operand (file, x, 0);
2194 return;
2195
64305719
DE		 2196 case 'H':
2197 /* If constant, output low-order six bits. Otherwise,
2198 write normally. */
2199 if (INT_P (x))
2200 fprintf (file, "%d", INT_LOWPART (x) & 63);
2201 else
2202 print_operand (file, x, 0);
2203 return;
2204
9854d9ed
RK		 2205 case 'I':
2206 /* Print `i' if this is a constant, else nothing. */
9878760c 2207 if (INT_P (x))
76229ac8 2208 putc ('i', file);
9878760c
RK		 2209 return;
2210
9854d9ed
RK		 2211 case 'j':
2212 /* Write the bit number in CCR for jump. */
2213 i = ccr_bit (x, 0);
2214 if (i == -1)
2215 output_operand_lossage ("invalid %%j code");
9878760c 2216 else
9854d9ed 2217 fprintf (file, "%d", i);
9878760c
RK		 2218 return;
2219
9854d9ed
RK		 2220 case 'J':
2221 /* Similar, but add one for shift count in rlinm for scc and pass
2222 scc flag to `ccr_bit'. */
2223 i = ccr_bit (x, 1);
2224 if (i == -1)
2225 output_operand_lossage ("invalid %%J code");
2226 else
a0466a68
RK		 2227 /* If we want bit 31, write a shift count of zero, not 32. */
2228 fprintf (file, "%d", i == 31 ? 0 : i + 1);
9878760c
RK		 2229 return;
2230
9854d9ed
RK		 2231 case 'k':
2232 /* X must be a constant. Write the 1's complement of the
2233 constant. */
9878760c 2234 if (! INT_P (x))
9854d9ed 2235 output_operand_lossage ("invalid %%k value");
9878760c 2236
9854d9ed 2237 fprintf (file, "%d", ~ INT_LOWPART (x));
9878760c
RK		 2238 return;
2239
9854d9ed
RK		 2240 case 'L':
2241 /* Write second word of DImode or DFmode reference. Works on register
2242 or non-indexed memory only. */
2243 if (GET_CODE (x) == REG)
5ebfb2ba 2244 fprintf (file, "%s", reg_names[REGNO (x) + 1]);
9854d9ed
RK		 2245 else if (GET_CODE (x) == MEM)
2246 {
2247 /* Handle possible auto-increment. Since it is pre-increment and
2248 we have already done it, we can just use an offset of four. */
2249 if (GET_CODE (XEXP (x, 0)) == PRE_INC
2250 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
a54d04b7 2251 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 4));
9854d9ed 2252 else
a54d04b7 2253 output_address (plus_constant (XEXP (x, 0), 4));
ba5e43aa
MM		 2254 if (small_data_operand (x, GET_MODE (x)))
2255 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC, reg_names[0]);
9854d9ed 2256 }
9878760c 2257 return;
9854d9ed 2258
9878760c
RK		 2259 case 'm':
2260 /* MB value for a mask operand. */
2261 if (! mask_operand (x, VOIDmode))
2262 output_operand_lossage ("invalid %%m value");
2263
2264 val = INT_LOWPART (x);
2265
2266 /* If the high bit is set and the low bit is not, the value is zero.
2267 If the high bit is zero, the value is the first 1 bit we find from
2268 the left. */
2269 if (val < 0 && (val & 1) == 0)
2270 {
19d2d16f 2271 putc ('0', file);
9878760c
RK		 2272 return;
2273 }
2274 else if (val >= 0)
2275 {
2276 for (i = 1; i < 32; i++)
2277 if ((val <<= 1) < 0)
2278 break;
2279 fprintf (file, "%d", i);
2280 return;
2281 }
2282
2283 /* Otherwise, look for the first 0 bit from the right. The result is its
2284 number plus 1. We know the low-order bit is one. */
2285 for (i = 0; i < 32; i++)
2286 if (((val >>= 1) & 1) == 0)
2287 break;
2288
2289 /* If we ended in ...01, I would be 0. The correct value is 31, so
2290 we want 31 - i. */
2291 fprintf (file, "%d", 31 - i);
2292 return;
2293
2294 case 'M':
2295 /* ME value for a mask operand. */
2296 if (! mask_operand (x, VOIDmode))
2297 output_operand_lossage ("invalid %%m value");
2298
2299 val = INT_LOWPART (x);
2300
2301 /* If the low bit is set and the high bit is not, the value is 31.
2302 If the low bit is zero, the value is the first 1 bit we find from
2303 the right. */
2304 if ((val & 1) && val >= 0)
2305 {
76229ac8 2306 fputs ("31", file);
9878760c
RK		 2307 return;
2308 }
2309 else if ((val & 1) == 0)
2310 {
2311 for (i = 0; i < 32; i++)
2312 if ((val >>= 1) & 1)
2313 break;
2314
2315 /* If we had ....10, I would be 0. The result should be
2316 30, so we need 30 - i. */
2317 fprintf (file, "%d", 30 - i);
2318 return;
2319 }
2320
2321 /* Otherwise, look for the first 0 bit from the left. The result is its
2322 number minus 1. We know the high-order bit is one. */
2323 for (i = 0; i < 32; i++)
2324 if ((val <<= 1) >= 0)
2325 break;
2326
2327 fprintf (file, "%d", i);
2328 return;
2329
9878760c
RK		 2330 case 'N':
2331 /* Write the number of elements in the vector times 4. */
2332 if (GET_CODE (x) != PARALLEL)
2333 output_operand_lossage ("invalid %%N value");
2334
2335 fprintf (file, "%d", XVECLEN (x, 0) * 4);
2336 return;
2337
2338 case 'O':
2339 /* Similar, but subtract 1 first. */
2340 if (GET_CODE (x) != PARALLEL)
2341 output_operand_lossage ("invalid %%N value");
2342
2343 fprintf (file, "%d", (XVECLEN (x, 0) - 1) * 4);
2344 return;
2345
9854d9ed
RK		 2346 case 'p':
2347 /* X is a CONST_INT that is a power of two. Output the logarithm. */
2348 if (! INT_P (x)
2349 || (i = exact_log2 (INT_LOWPART (x))) < 0)
2350 output_operand_lossage ("invalid %%p value");
2351
2352 fprintf (file, "%d", i);
2353 return;
2354
9878760c
RK		 2355 case 'P':
2356 /* The operand must be an indirect memory reference. The result
2357 is the register number. */
2358 if (GET_CODE (x) != MEM || GET_CODE (XEXP (x, 0)) != REG
2359 || REGNO (XEXP (x, 0)) >= 32)
2360 output_operand_lossage ("invalid %%P value");
2361
2362 fprintf (file, "%d", REGNO (XEXP (x, 0)));
2363 return;
2364
9854d9ed
RK		 2365 case 'R':
2366 /* X is a CR register. Print the mask for `mtcrf'. */
2367 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
2368 output_operand_lossage ("invalid %%R value");
2369 else
2370 fprintf (file, "%d", 128 >> (REGNO (x) - 68));
9878760c 2371 return;
9854d9ed
RK		 2372
2373 case 's':
2374 /* Low 5 bits of 32 - value */
2375 if (! INT_P (x))
2376 output_operand_lossage ("invalid %%s value");
2377
2378 fprintf (file, "%d", (32 - INT_LOWPART (x)) & 31);
9878760c 2379 return;
9854d9ed 2380
9878760c
RK		 2381 case 't':
2382 /* Write 12 if this jump operation will branch if true, 4 otherwise.
2383 All floating-point operations except NE branch true and integer
2384 EQ, LT, GT, LTU and GTU also branch true. */
2385 if (GET_RTX_CLASS (GET_CODE (x)) != '<')
2386 output_operand_lossage ("invalid %%t value");
2387
2388 else if ((GET_MODE (XEXP (x, 0)) == CCFPmode
2389 && GET_CODE (x) != NE)
2390 || GET_CODE (x) == EQ
2391 || GET_CODE (x) == LT || GET_CODE (x) == GT
2392 || GET_CODE (x) == LTU || GET_CODE (x) == GTU)
76229ac8 2393 fputs ("12", file);
9878760c 2394 else
76229ac8 2395 putc ('4', file);
9878760c
RK		 2396 return;
2397
2398 case 'T':
2399 /* Opposite of 't': write 4 if this jump operation will branch if true,
2400 12 otherwise. */
2401 if (GET_RTX_CLASS (GET_CODE (x)) != '<')
2402 output_operand_lossage ("invalid %%t value");
2403
2404 else if ((GET_MODE (XEXP (x, 0)) == CCFPmode
2405 && GET_CODE (x) != NE)
2406 || GET_CODE (x) == EQ
2407 || GET_CODE (x) == LT || GET_CODE (x) == GT
2408 || GET_CODE (x) == LTU || GET_CODE (x) == GTU)
76229ac8 2409 putc ('4', file);
9878760c 2410 else
76229ac8 2411 fputs ("12", file);
9878760c
RK		 2412 return;
2413
9854d9ed 2414 case 'u':
802a0058 2415 /* High-order 16 bits of constant for use in unsigned operand. */
9854d9ed
RK		 2416 if (! INT_P (x))
2417 output_operand_lossage ("invalid %%u value");
9878760c 2418
76229ac8 2419 fprintf (file, "0x%x", (INT_LOWPART (x) >> 16) & 0xffff);
9878760c
RK		 2420 return;
2421
802a0058
MM		 2422 case 'v':
2423 /* High-order 16 bits of constant for use in signed operand. */
2424 if (! INT_P (x))
2425 output_operand_lossage ("invalid %%v value");
2426
2427 {
2428 int value = (INT_LOWPART (x) >> 16) & 0xffff;
2429
2430 /* Solaris assembler doesn't like lis 0,0x80000 */
2431 if (DEFAULT_ABI == ABI_SOLARIS && (value & 0x8000) != 0)
2432 fprintf (file, "%d", value | (~0 << 16));
2433 else
2434 fprintf (file, "0x%x", value);
2435 return;
2436 }
2437
9854d9ed
RK		 2438 case 'U':
2439 /* Print `u' if this has an auto-increment or auto-decrement. */
2440 if (GET_CODE (x) == MEM
2441 && (GET_CODE (XEXP (x, 0)) == PRE_INC
2442 || GET_CODE (XEXP (x, 0)) == PRE_DEC))
76229ac8 2443 putc ('u', file);
9854d9ed 2444 return;
9878760c 2445
9854d9ed
RK		 2446 case 'w':
2447 /* If constant, low-order 16 bits of constant, signed. Otherwise, write
2448 normally. */
2449 if (INT_P (x))
2450 fprintf (file, "%d",
2451 (INT_LOWPART (x) & 0xffff) - 2 * (INT_LOWPART (x) & 0x8000));
2452 else
2453 print_operand (file, x, 0);
9878760c
RK		 2454 return;
2455
9854d9ed
RK		 2456 case 'W':
2457 /* If constant, low-order 16 bits of constant, unsigned.
2458 Otherwise, write normally. */
2459 if (INT_P (x))
2460 fprintf (file, "%d", INT_LOWPART (x) & 0xffff);
2461 else
2462 print_operand (file, x, 0);
2463 return;
9878760c 2464
9854d9ed
RK		 2465 case 'X':
2466 if (GET_CODE (x) == MEM
2467 && LEGITIMATE_INDEXED_ADDRESS_P (XEXP (x, 0)))
76229ac8 2468 putc ('x', file);
9854d9ed 2469 return;
9878760c 2470
9854d9ed
RK		 2471 case 'Y':
2472 /* Like 'L', for third word of TImode */
2473 if (GET_CODE (x) == REG)
5ebfb2ba 2474 fprintf (file, "%s", reg_names[REGNO (x) + 2]);
9854d9ed 2475 else if (GET_CODE (x) == MEM)
9878760c 2476 {
9854d9ed
RK		 2477 if (GET_CODE (XEXP (x, 0)) == PRE_INC
2478 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
a54d04b7 2479 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 8));
9854d9ed 2480 else
a54d04b7 2481 output_address (plus_constant (XEXP (x, 0), 8));
ba5e43aa
MM		 2482 if (small_data_operand (x, GET_MODE (x)))
2483 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC, reg_names[0]);
9878760c
RK		 2484 }
2485 return;
9854d9ed 2486
9878760c 2487 case 'z':
b4ac57ab
RS		 2488 /* X is a SYMBOL_REF. Write out the name preceded by a
2489 period and without any trailing data in brackets. Used for function
4d30c363
MM		 2490 names. If we are configured for System V (or the embedded ABI) on
2491 the PowerPC, do not emit the period, since those systems do not use
2492 TOCs and the like. */
9878760c
RK		 2493 if (GET_CODE (x) != SYMBOL_REF)
2494 abort ();
2495
b6c9286a
MM		 2496 if (XSTR (x, 0)[0] != '.')
2497 {
2498 switch (DEFAULT_ABI)
2499 {
2500 default:
2501 abort ();
2502
2503 case ABI_AIX:
2504 putc ('.', file);
2505 break;
2506
2507 case ABI_V4:
2508 case ABI_AIX_NODESC:
c81bebd7 2509 case ABI_SOLARIS:
b6c9286a
MM		 2510 break;
2511
2512 case ABI_NT:
2513 fputs ("..", file);
2514 break;
2515 }
2516 }
9878760c
RK		 2517 RS6000_OUTPUT_BASENAME (file, XSTR (x, 0));
2518 return;
2519
9854d9ed
RK		 2520 case 'Z':
2521 /* Like 'L', for last word of TImode. */
2522 if (GET_CODE (x) == REG)
5ebfb2ba 2523 fprintf (file, "%s", reg_names[REGNO (x) + 3]);
9854d9ed
RK		 2524 else if (GET_CODE (x) == MEM)
2525 {
2526 if (GET_CODE (XEXP (x, 0)) == PRE_INC
2527 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
a54d04b7 2528 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 12));
9854d9ed 2529 else
a54d04b7 2530 output_address (plus_constant (XEXP (x, 0), 12));
ba5e43aa
MM		 2531 if (small_data_operand (x, GET_MODE (x)))
2532 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC, reg_names[0]);
9854d9ed 2533 }
5c23c401 2534 return;
9854d9ed 2535
9878760c
RK		 2536 case 0:
2537 if (GET_CODE (x) == REG)
2538 fprintf (file, "%s", reg_names[REGNO (x)]);
2539 else if (GET_CODE (x) == MEM)
2540 {
2541 /* We need to handle PRE_INC and PRE_DEC here, since we need to
2542 know the width from the mode. */
2543 if (GET_CODE (XEXP (x, 0)) == PRE_INC)
2544 fprintf (file, "%d(%d)", GET_MODE_SIZE (GET_MODE (x)),
2545 REGNO (XEXP (XEXP (x, 0), 0)));
2546 else if (GET_CODE (XEXP (x, 0)) == PRE_DEC)
2547 fprintf (file, "%d(%d)", - GET_MODE_SIZE (GET_MODE (x)),
2548 REGNO (XEXP (XEXP (x, 0), 0)));
2549 else
a54d04b7 2550 output_address (XEXP (x, 0));
9878760c
RK		 2551 }
2552 else
a54d04b7 2553 output_addr_const (file, x);
a85d226b 2554 return;
9878760c
RK		 2555
2556 default:
2557 output_operand_lossage ("invalid %%xn code");
2558 }
2559}
2560\f
2561/* Print the address of an operand. */
2562
2563void
2564print_operand_address (file, x)
2565 FILE *file;
2566 register rtx x;
2567{
2568 if (GET_CODE (x) == REG)
4697a36c 2569 fprintf (file, "0(%s)", reg_names[ REGNO (x) ]);
9878760c
RK		 2570 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST)
2571 {
2572 output_addr_const (file, x);
ba5e43aa
MM		 2573 if (small_data_operand (x, GET_MODE (x)))
2574 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC, reg_names[0]);
7509c759 2575
4697a36c 2576#ifdef TARGET_NO_TOC
7509c759 2577 else if (TARGET_NO_TOC)
4697a36c 2578 ;
4697a36c 2579#endif
7509c759 2580 else
4697a36c 2581 fprintf (file, "(%s)", reg_names[ TARGET_MINIMAL_TOC ? 30 : 2 ]);
9878760c
RK		 2582 }
2583 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == REG)
2584 {
2585 if (REGNO (XEXP (x, 0)) == 0)
4697a36c
MM		 2586 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 1)) ],
2587 reg_names[ REGNO (XEXP (x, 0)) ]);
9878760c 2588 else
4697a36c
MM		 2589 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 0)) ],
2590 reg_names[ REGNO (XEXP (x, 1)) ]);
9878760c
RK		 2591 }
2592 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
4697a36c
MM		 2593 fprintf (file, "%d(%s)", INTVAL (XEXP (x, 1)), reg_names[ REGNO (XEXP (x, 0)) ]);
2594 else if (TARGET_ELF && !TARGET_64BIT && GET_CODE (x) == LO_SUM
2595 && GET_CODE (XEXP (x, 0)) == REG && CONSTANT_P (XEXP (x, 1)))
2596 {
2597 output_addr_const (file, XEXP (x, 1));
2598 fprintf (file, "@l(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
2599 }
9878760c
RK		 2600 else
2601 abort ();
2602}
2603\f
2604/* This page contains routines that are used to determine what the function
2605 prologue and epilogue code will do and write them out. */
2606
2607/* Return the first fixed-point register that is required to be saved. 32 if
2608 none. */
2609
2610int
2611first_reg_to_save ()
2612{
2613 int first_reg;
2614
2615 /* Find lowest numbered live register. */
2616 for (first_reg = 13; first_reg <= 31; first_reg++)
2617 if (regs_ever_live[first_reg])
2618 break;
2619
e165f3f0
RK		 2620 /* If profiling, then we must save/restore every register that contains
2621 a parameter before/after the .mcount call. Use registers from 30 down
2622 to 23 to do this. Don't use the frame pointer in reg 31.
2623
2624 For now, save enough room for all of the parameter registers. */
b6c9286a 2625 if (DEFAULT_ABI == ABI_AIX && profile_flag)
e165f3f0
RK		 2626 if (first_reg > 23)
2627 first_reg = 23;
2628
9878760c
RK		 2629 return first_reg;
2630}
2631
2632/* Similar, for FP regs. */
2633
2634int
2635first_fp_reg_to_save ()
2636{
2637 int first_reg;
2638
2639 /* Find lowest numbered live register. */
2640 for (first_reg = 14 + 32; first_reg <= 63; first_reg++)
2641 if (regs_ever_live[first_reg])
2642 break;
2643
2644 return first_reg;
2645}
2646
9878760c
RK		 2647/* Return non-zero if this function makes calls. */
2648
2649int
2650rs6000_makes_calls ()
2651{
2652 rtx insn;
2653
0c61c946
RK		 2654 /* If we are profiling, we will be making a call to mcount. */
2655 if (profile_flag)
2656 return 1;
2657
9878760c
RK		 2658 for (insn = get_insns (); insn; insn = next_insn (insn))
2659 if (GET_CODE (insn) == CALL_INSN)
2660 return 1;
2661
2662 return 0;
2663}
2664
4697a36c
MM		 2665\f
2666/* Calculate the stack information for the current function. This is
2667 complicated by having two separate calling sequences, the AIX calling
2668 sequence and the V.4 calling sequence.
2669
2670 AIX stack frames look like:
2671
2672 SP----> +---------------------------------------+
2673 | back chain to caller | 0
2674 +---------------------------------------+
2675 | saved CR | 4
2676 +---------------------------------------+
2677 | saved LR | 8
2678 +---------------------------------------+
2679 | reserved for compilers | 12
2680 +---------------------------------------+
2681 | reserved for binders | 16
2682 +---------------------------------------+
2683 | saved TOC pointer | 20
2684 +---------------------------------------+
2685 | Parameter save area (P) | 24
2686 +---------------------------------------+
802a0058
MM		 2687 | Float/int conversion temporary (X) | 24+P
2688 +---------------------------------------+
2689 | Alloca space (A) | 24+P+X
4697a36c 2690 +---------------------------------------+
802a0058 2691 | Local variable space (L) | 24+P+X+A
4697a36c 2692 +---------------------------------------+
802a0058 2693 | Save area for GP registers (G) | 24+P+X+A+L
4697a36c 2694 +---------------------------------------+
802a0058 2695 | Save area for FP registers (F) | 24+P+X+A+L+G
4697a36c
MM		 2696 +---------------------------------------+
2697 old SP->| back chain to caller's caller |
2698 +---------------------------------------+
2699
2700 V.4 stack frames look like:
2701
2702 SP----> +---------------------------------------+
2703 | back chain to caller | 0
2704 +---------------------------------------+
5eb387b8 2705 | caller's saved LR | 4
4697a36c
MM		 2706 +---------------------------------------+
2707 | Parameter save area (P) | 8
2708 +---------------------------------------+
802a0058 2709 | Float/int conversion temporary (X) | 8+P
4697a36c 2710 +---------------------------------------+
802a0058 2711 | Alloca space (A) | 8+P+X
4697a36c 2712 +---------------------------------------+
802a0058 2713 | Varargs save area (V) | 8+P+X+A
4697a36c 2714 +---------------------------------------+
802a0058 2715 | Local variable space (L) | 8+P+X+A+V
4697a36c 2716 +---------------------------------------+
802a0058 2717 | saved CR (C) | 8+P+X+A+V+L
4697a36c 2718 +---------------------------------------+
802a0058
MM		 2719 | Save area for GP registers (G) | 8+P+X+A+V+L+C
2720 +---------------------------------------+
2721 | Save area for FP registers (F) | 8+P+X+A+V+L+C+G
4697a36c
MM		 2722 +---------------------------------------+
2723 old SP->| back chain to caller's caller |
2724 +---------------------------------------+
b6c9286a
MM		 2725
2726
2727 A PowerPC Windows/NT frame looks like:
2728
2729 SP----> +---------------------------------------+
2730 | back chain to caller | 0
2731 +---------------------------------------+
2732 | reserved | 4
2733 +---------------------------------------+
2734 | reserved | 8
2735 +---------------------------------------+
2736 | reserved | 12
2737 +---------------------------------------+
2738 | reserved | 16
2739 +---------------------------------------+
2740 | reserved | 20
2741 +---------------------------------------+
2742 | Parameter save area (P) | 24
2743 +---------------------------------------+
802a0058
MM		 2744 | Float/int conversion temporary (X) | 24+P
2745 +---------------------------------------+
2746 | Alloca space (A) | 24+P+X
b6c9286a 2747 +---------------------------------------+
802a0058 2748 | Local variable space (L) | 24+P+X+A
b6c9286a 2749 +---------------------------------------+
802a0058 2750 | Save area for FP registers (F) | 24+P+X+A+L
b6c9286a 2751 +---------------------------------------+
802a0058 2752 | Possible alignment area (X) | 24+P+X+A+L+F
b6c9286a 2753 +---------------------------------------+
802a0058 2754 | Save area for GP registers (G) | 24+P+X+A+L+F+X
b6c9286a 2755 +---------------------------------------+
802a0058 2756 | Save area for CR (C) | 24+P+X+A+L+F+X+G
b6c9286a 2757 +---------------------------------------+
802a0058 2758 | Save area for TOC (T) | 24+P+X+A+L+F+X+G+C
b6c9286a 2759 +---------------------------------------+
802a0058 2760 | Save area for LR (R) | 24+P+X+A+L+F+X+G+C+T
b6c9286a
MM		 2761 +---------------------------------------+
2762 old SP->| back chain to caller's caller |
2763 +---------------------------------------+
2764
2765 For NT, there is no specific order to save the registers, but in
2766 order to support __builtin_return_address, the save area for the
2767 link register needs to be in a known place, so we use -4 off of the
2768 old SP. To support calls through pointers, we also allocate a
2769 fixed slot to store the TOC, -8 off the old SP. */
4697a36c
MM		 2770
2771rs6000_stack_t *
2772rs6000_stack_info ()
2773{
2774 static rs6000_stack_t info, zero_info;
2775 rs6000_stack_t *info_ptr = &info;
2776 int reg_size = TARGET_64BIT ? 8 : 4;
24d304eb 2777 enum rs6000_abi abi;
b6c9286a 2778 int total_raw_size;
4697a36c
MM		 2779
2780 /* Zero all fields portably */
2781 info = zero_info;
2782
2783 /* Select which calling sequence */
b6c9286a 2784 info_ptr->abi = abi = DEFAULT_ABI;
9878760c 2785
4697a36c
MM		 2786 /* Calculate which registers need to be saved & save area size */
2787 info_ptr->first_gp_reg_save = first_reg_to_save ();
2788 info_ptr->gp_size = reg_size * (32 - info_ptr->first_gp_reg_save);
2789
2790 info_ptr->first_fp_reg_save = first_fp_reg_to_save ();
2791 info_ptr->fp_size = 8 * (64 - info_ptr->first_fp_reg_save);
2792
2793 /* Does this function call anything? */
2794 info_ptr->calls_p = rs6000_makes_calls ();
2795
b6c9286a
MM		 2796 /* Do we need to allocate space to save the toc? */
2797 if (rs6000_save_toc_p)
2798 {
2799 info_ptr->toc_save_p = 1;
2800 info_ptr->toc_size = reg_size;
2801 }
2802
802a0058
MM		 2803 /* Does this machine need the float/int conversion area? */
2804 info_ptr->fpmem_p = regs_ever_live[FPMEM_REGNUM];
2805
b6c9286a
MM		 2806 /* If this is main and we need to call a function to set things up,
2807 save main's arguments around the call. */
c81bebd7
MM		 2808#ifdef TARGET_EABI
2809 if (TARGET_EABI)
2810#endif
b6c9286a 2811 {
c81bebd7 2812 if (strcmp (IDENTIFIER_POINTER (DECL_NAME (current_function_decl)), "main") == 0)
b6c9286a 2813 {
c81bebd7 2814 info_ptr->main_p = 1;
b6c9286a 2815
c81bebd7
MM		 2816#ifdef NAME__MAIN
2817 info_ptr->calls_p = 1;
b6c9286a 2818
c81bebd7 2819 if (DECL_ARGUMENTS (current_function_decl))
b6c9286a 2820 {
c81bebd7
MM		 2821 int i;
2822 tree arg;
2823
2824 info_ptr->main_save_p = 1;
2825 info_ptr->main_size = 0;
2826
2827 for ((i = 0), (arg = DECL_ARGUMENTS (current_function_decl));
2828 arg != NULL_TREE && i < 8;
2829 (arg = TREE_CHAIN (arg)), i++)
2830 {
2831 info_ptr->main_size += reg_size;
2832 }
b6c9286a 2833 }
b6c9286a 2834#endif
c81bebd7 2835 }
b6c9286a
MM		 2836 }
2837
c81bebd7 2838
4697a36c
MM		 2839 /* Determine if we need to save the link register */
2840 if (regs_ever_live[65] || profile_flag
2841#ifdef TARGET_RELOCATABLE
2842 || (TARGET_RELOCATABLE && (get_pool_size () != 0))
2843#endif
2844 || (info_ptr->first_fp_reg_save != 64
2845 && !FP_SAVE_INLINE (info_ptr->first_fp_reg_save))
24d304eb 2846 || (abi == ABI_V4 && current_function_calls_alloca)
c81bebd7 2847 || (abi == ABI_SOLARIS && current_function_calls_alloca)
4697a36c
MM		 2848 || info_ptr->calls_p)
2849 {
2850 info_ptr->lr_save_p = 1;
2851 regs_ever_live[65] = 1;
b6c9286a
MM		 2852 if (abi == ABI_NT)
2853 info_ptr->lr_size = reg_size;
4697a36c
MM		 2854 }
2855
2856 /* Determine if we need to save the condition code registers */
2857 if (regs_ever_live[70] || regs_ever_live[71] || regs_ever_live[72])
2858 {
2859 info_ptr->cr_save_p = 1;
c81bebd7 2860 if (abi == ABI_V4 || abi == ABI_NT || abi == ABI_SOLARIS)
4697a36c
MM		 2861 info_ptr->cr_size = reg_size;
2862 }
2863
2864 /* Determine various sizes */
2865 info_ptr->reg_size = reg_size;
2866 info_ptr->fixed_size = RS6000_SAVE_AREA;
2867 info_ptr->varargs_size = RS6000_VARARGS_AREA;
2868 info_ptr->vars_size = ALIGN (get_frame_size (), 8);
2869 info_ptr->parm_size = ALIGN (current_function_outgoing_args_size, 8);
802a0058 2870 info_ptr->fpmem_size = (info_ptr->fpmem_p) ? 8 : 0;
b6c9286a
MM		 2871 info_ptr->save_size = ALIGN (info_ptr->fp_size
2872 + info_ptr->gp_size
2873 + info_ptr->cr_size
2874 + info_ptr->lr_size
2875 + info_ptr->toc_size
2876 + info_ptr->main_size, 8);
2877
2878 total_raw_size = (info_ptr->vars_size
2879 + info_ptr->parm_size
802a0058 2880 + info_ptr->fpmem_size
b6c9286a
MM		 2881 + info_ptr->save_size
2882 + info_ptr->varargs_size
2883 + info_ptr->fixed_size);
2884
2885 info_ptr->total_size = ALIGN (total_raw_size, STACK_BOUNDARY / BITS_PER_UNIT);
4697a36c
MM		 2886
2887 /* Determine if we need to allocate any stack frame.
2888 For AIX We need to push the stack if a frame pointer is needed (because
2889 the stack might be dynamically adjusted), if we are debugging, if the
2890 total stack size is more than 220 bytes, or if we make calls.
2891
2892 For V.4 we don't have the stack cushion that AIX uses, but assume that
2893 the debugger can handle stackless frames. */
2894
2895 if (info_ptr->calls_p)
2896 info_ptr->push_p = 1;
2897
c81bebd7 2898 else if (abi == ABI_V4 || abi == ABI_NT || abi == ABI_SOLARIS)
b6c9286a 2899 info_ptr->push_p = (total_raw_size > info_ptr->fixed_size
4697a36c
MM		 2900 || info_ptr->lr_save_p);
2901
2902 else
2903 info_ptr->push_p = (frame_pointer_needed
2904 || write_symbols != NO_DEBUG
2905 || info_ptr->total_size > 220);
2906
2907 /* Calculate the offsets */
802a0058 2908 info_ptr->fpmem_offset = info_ptr->total_size - info_ptr->parm_size;
24d304eb 2909 switch (abi)
4697a36c 2910 {
b6c9286a 2911 case ABI_NONE:
24d304eb 2912 default:
b6c9286a
MM		 2913 abort ();
2914
2915 case ABI_AIX:
2916 case ABI_AIX_NODESC:
2917 info_ptr->fp_save_offset = - info_ptr->fp_size;
2918 info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size;
2919 info_ptr->main_save_offset = info_ptr->gp_save_offset - info_ptr->main_size;
2920 info_ptr->cr_save_offset = 4;
2921 info_ptr->lr_save_offset = 8;
24d304eb
RK		 2922 break;
2923
2924 case ABI_V4:
c81bebd7 2925 case ABI_SOLARIS:
b6c9286a
MM		 2926 info_ptr->fp_save_offset = - info_ptr->fp_size;
2927 info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size;
2928 info_ptr->cr_save_offset = info_ptr->gp_save_offset - reg_size;
2929 info_ptr->toc_save_offset = info_ptr->cr_save_offset - info_ptr->cr_size;
2930 info_ptr->main_save_offset = info_ptr->toc_save_offset - info_ptr->toc_size;
2931 info_ptr->lr_save_offset = reg_size;
2932 break;
2933
2934 case ABI_NT:
2935 info_ptr->lr_save_offset = -4;
2936 info_ptr->toc_save_offset = info_ptr->lr_save_offset - info_ptr->lr_size;
2937 info_ptr->cr_save_offset = info_ptr->toc_save_offset - info_ptr->toc_size;
2938 info_ptr->gp_save_offset = info_ptr->cr_save_offset - info_ptr->cr_size - info_ptr->gp_size + reg_size;
2939 info_ptr->fp_save_offset = info_ptr->gp_save_offset - info_ptr->fp_size;
2940 if (info_ptr->fp_size && ((- info_ptr->fp_save_offset) % 8) != 0)
2941 info_ptr->fp_save_offset -= 4;
2942
2943 info_ptr->main_save_offset = info_ptr->fp_save_offset - info_ptr->main_size;
24d304eb 2944 break;
4697a36c
MM		 2945 }
2946
2947 /* Zero offsets if we're not saving those registers */
2948 if (!info_ptr->fp_size)
2949 info_ptr->fp_save_offset = 0;
2950
2951 if (!info_ptr->gp_size)
2952 info_ptr->gp_save_offset = 0;
2953
2954 if (!info_ptr->lr_save_p)
2955 info_ptr->lr_save_offset = 0;
2956
2957 if (!info_ptr->cr_save_p)
2958 info_ptr->cr_save_offset = 0;
2959
b6c9286a
MM		 2960 if (!info_ptr->toc_save_p)
2961 info_ptr->toc_save_offset = 0;
2962
2963 if (!info_ptr->main_save_p)
2964 info_ptr->main_save_offset = 0;
2965
802a0058
MM		 2966 if (!info_ptr->fpmem_p)
2967 info_ptr->fpmem_offset = 0;
2968 else
2969 {
2970 rs6000_fpmem_size = info_ptr->fpmem_size;
2971 rs6000_fpmem_offset = STACK_DYNAMIC_OFFSET (current_function_decl) - info_ptr->fpmem_size;
2972 if (rs6000_fpmem_offset > 32767)
2973 abort ();
2974 }
2975
4697a36c
MM		 2976 return info_ptr;
2977}
2978
2979void
2980debug_stack_info (info)
2981 rs6000_stack_t *info;
9878760c 2982{
24d304eb
RK		 2983 char *abi_string;
2984
4697a36c
MM		 2985 if (!info)
2986 info = rs6000_stack_info ();
2987
2988 fprintf (stderr, "\nStack information for function %s:\n",
2989 ((current_function_decl && DECL_NAME (current_function_decl))
2990 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl))
2991 : "<unknown>"));
2992
24d304eb
RK		 2993 switch (info->abi)
2994 {
b6c9286a
MM		 2995 default: abi_string = "Unknown"; break;
2996 case ABI_NONE: abi_string = "NONE"; break;
2997 case ABI_AIX: abi_string = "AIX"; break;
2998 case ABI_AIX_NODESC: abi_string = "AIX"; break;
2999 case ABI_V4: abi_string = "V.4"; break;
c81bebd7 3000 case ABI_SOLARIS: abi_string = "Solaris"; break;
b6c9286a 3001 case ABI_NT: abi_string = "NT"; break;
24d304eb
RK		 3002 }
3003
3004 fprintf (stderr, "\tABI = %5s\n", abi_string);
3005
4697a36c
MM		 3006 if (info->first_gp_reg_save != 32)
3007 fprintf (stderr, "\tfirst_gp_reg_save = %5d\n", info->first_gp_reg_save);
3008
3009 if (info->first_fp_reg_save != 64)
3010 fprintf (stderr, "\tfirst_fp_reg_save = %5d\n", info->first_fp_reg_save);
9878760c 3011
4697a36c
MM		 3012 if (info->lr_save_p)
3013 fprintf (stderr, "\tlr_save_p = %5d\n", info->lr_save_p);
9878760c 3014
4697a36c
MM		 3015 if (info->cr_save_p)
3016 fprintf (stderr, "\tcr_save_p = %5d\n", info->cr_save_p);
3017
b6c9286a
MM		 3018 if (info->toc_save_p)
3019 fprintf (stderr, "\ttoc_save_p = %5d\n", info->toc_save_p);
3020
4697a36c
MM		 3021 if (info->push_p)
3022 fprintf (stderr, "\tpush_p = %5d\n", info->push_p);
3023
3024 if (info->calls_p)
3025 fprintf (stderr, "\tcalls_p = %5d\n", info->calls_p);
3026
b6c9286a
MM		 3027 if (info->main_p)
3028 fprintf (stderr, "\tmain_p = %5d\n", info->main_p);
3029
3030 if (info->main_save_p)
3031 fprintf (stderr, "\tmain_save_p = %5d\n", info->main_save_p);
3032
802a0058
MM		 3033 if (info->fpmem_p)
3034 fprintf (stderr, "\tfpmem_p = %5d\n", info->fpmem_p);
3035
4697a36c
MM		 3036 if (info->gp_save_offset)
3037 fprintf (stderr, "\tgp_save_offset = %5d\n", info->gp_save_offset);
3038
3039 if (info->fp_save_offset)
3040 fprintf (stderr, "\tfp_save_offset = %5d\n", info->fp_save_offset);
3041
3042 if (info->lr_save_offset)
3043 fprintf (stderr, "\tlr_save_offset = %5d\n", info->lr_save_offset);
3044
3045 if (info->cr_save_offset)
3046 fprintf (stderr, "\tcr_save_offset = %5d\n", info->cr_save_offset);
3047
b6c9286a
MM		 3048 if (info->toc_save_offset)
3049 fprintf (stderr, "\ttoc_save_offset = %5d\n", info->toc_save_offset);
3050
4697a36c
MM		 3051 if (info->varargs_save_offset)
3052 fprintf (stderr, "\tvarargs_save_offset = %5d\n", info->varargs_save_offset);
3053
b6c9286a
MM		 3054 if (info->main_save_offset)
3055 fprintf (stderr, "\tmain_save_offset = %5d\n", info->main_save_offset);
3056
802a0058
MM		 3057 if (info->fpmem_offset)
3058 fprintf (stderr, "\tfpmem_offset = %5d\n", info->fpmem_offset);
3059
4697a36c
MM		 3060 if (info->total_size)
3061 fprintf (stderr, "\ttotal_size = %5d\n", info->total_size);
3062
3063 if (info->varargs_size)
3064 fprintf (stderr, "\tvarargs_size = %5d\n", info->varargs_size);
3065
3066 if (info->vars_size)
3067 fprintf (stderr, "\tvars_size = %5d\n", info->vars_size);
3068
3069 if (info->parm_size)
3070 fprintf (stderr, "\tparm_size = %5d\n", info->parm_size);
3071
802a0058
MM		 3072 if (info->fpmem_size)
3073 fprintf (stderr, "\tfpmem_size = %5d\n", info->fpmem_size);
3074
4697a36c
MM		 3075 if (info->fixed_size)
3076 fprintf (stderr, "\tfixed_size = %5d\n", info->fixed_size);
3077
3078 if (info->gp_size)
3079 fprintf (stderr, "\tgp_size = %5d\n", info->gp_size);
3080
3081 if (info->fp_size)
3082 fprintf (stderr, "\tfp_size = %5d\n", info->fp_size);
3083
b6c9286a
MM		 3084 if (info->lr_size)
3085 fprintf (stderr, "\tlr_size = %5d\n", info->cr_size);
3086
4697a36c
MM		 3087 if (info->cr_size)
3088 fprintf (stderr, "\tcr_size = %5d\n", info->cr_size);
3089
b6c9286a
MM		 3090 if (info->toc_size)
3091 fprintf (stderr, "\ttoc_size = %5d\n", info->toc_size);
3092
3093 if (info->main_size)
3094 fprintf (stderr, "\tmain_size = %5d\n", info->main_size);
3095
4697a36c
MM		 3096 if (info->save_size)
3097 fprintf (stderr, "\tsave_size = %5d\n", info->save_size);
3098
3099 if (info->reg_size != 4)
3100 fprintf (stderr, "\treg_size = %5d\n", info->reg_size);
3101
3102 fprintf (stderr, "\n");
9878760c
RK		 3103}
3104
4697a36c 3105\f
9878760c 3106/* Write function prologue. */
9878760c
RK		 3107void
3108output_prolog (file, size)
3109 FILE *file;
3110 int size;
3111{
4697a36c 3112 rs6000_stack_t *info = rs6000_stack_info ();
b6c9286a
MM		 3113 int reg_size = info->reg_size;
3114 char *store_reg;
3115 char *load_reg;
979721f8
MM		 3116 int sp_reg = 1;
3117 int sp_offset = 0;
b6c9286a 3118
8f802bfb 3119 if (TARGET_32BIT)
b6c9286a 3120 {
8f802bfb
DE		 3121 store_reg = "\t{st|stw} %s,%d(%s)\n";
3122 load_reg = "\t{l|lwz} %s,%d(%s)\n";
b6c9286a
MM		 3123 }
3124 else
3125 {
8f802bfb
DE		 3126 store_reg = "\tstd %s,%d(%s)\n";
3127 load_reg = "\tlld %s,%d(%s)\n";
b6c9286a 3128 }
9878760c 3129
4697a36c
MM		 3130 if (TARGET_DEBUG_STACK)
3131 debug_stack_info (info);
9878760c
RK		 3132
3133 /* Write .extern for any function we will call to save and restore fp
3134 values. */
b6c9286a 3135 if (info->first_fp_reg_save < 64 && !FP_SAVE_INLINE (info->first_fp_reg_save))
4d30c363 3136 fprintf (file, "\t.extern %s%d%s\n\t.extern %s%d%s\n",
4697a36c
MM		 3137 SAVE_FP_PREFIX, info->first_fp_reg_save - 32, SAVE_FP_SUFFIX,
3138 RESTORE_FP_PREFIX, info->first_fp_reg_save - 32, RESTORE_FP_SUFFIX);
9878760c
RK		 3139
3140 /* Write .extern for truncation routines, if needed. */
3141 if (rs6000_trunc_used && ! trunc_defined)
3142 {
e138174b
ILT		 3143 fprintf (file, "\t.extern .%s\n\t.extern .%s\n",
3144 RS6000_ITRUNC, RS6000_UITRUNC);
9878760c
RK		 3145 trunc_defined = 1;
3146 }
4697a36c 3147
c764f757
RK		 3148 /* Write .extern for AIX common mode routines, if needed. */
3149 if (! TARGET_POWER && ! TARGET_POWERPC && ! common_mode_defined)
3150 {
f6709c70
JW		 3151 fputs ("\t.extern __mulh\n", file);
3152 fputs ("\t.extern __mull\n", file);
3153 fputs ("\t.extern __divss\n", file);
3154 fputs ("\t.extern __divus\n", file);
3155 fputs ("\t.extern __quoss\n", file);
3156 fputs ("\t.extern __quous\n", file);
c764f757
RK		 3157 common_mode_defined = 1;
3158 }
9878760c 3159
979721f8 3160 /* For V.4, update stack before we do any saving and set back pointer. */
c81bebd7 3161 if (info->push_p && (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS))
979721f8
MM		 3162 {
3163 if (info->total_size < 32767)
3164 {
3165 asm_fprintf (file,
3166 (TARGET_32BIT) ? "\t{stu|stwu} %s,%d(%s)\n" : "\tstdu %s,%d(%s)\n",
3167 reg_names[1], - info->total_size, reg_names[1]);
3168 sp_offset = info->total_size;
3169 }
3170 else
3171 {
3172 int neg_size = - info->total_size;
3173 sp_reg = 12;
3174 asm_fprintf (file, "\tmr %s,%s\n", reg_names[12], reg_names[1]);
3175 asm_fprintf (file, "\t{liu|lis} %s,%d\n\t{oril|ori} %s,%s,%d\n",
3176 reg_names[0], (neg_size >> 16) & 0xffff,
3177 reg_names[0], reg_names[0], neg_size & 0xffff);
3178 asm_fprintf (file,
3179 (TARGET_32BIT) ? "\t{stux|stwux} %s,%s,%s\n" : "\tstdux %s,%s,%s\n",
3180 reg_names[1], reg_names[1], reg_names[0]);
3181 }
3182 }
3183
9878760c 3184 /* If we use the link register, get it into r0. */
4697a36c
MM		 3185 if (info->lr_save_p)
3186 asm_fprintf (file, "\tmflr %s\n", reg_names[0]);
9878760c
RK		 3187
3188 /* If we need to save CR, put it into r12. */
979721f8 3189 if (info->cr_save_p && sp_reg != 12)
4697a36c 3190 asm_fprintf (file, "\tmfcr %s\n", reg_names[12]);
9878760c
RK		 3191
3192 /* Do any required saving of fpr's. If only one or two to save, do it
53322b0c
RK		 3193 ourself. Otherwise, call function. Note that since they are statically
3194 linked, we do not need a nop following them. */
4697a36c 3195 if (FP_SAVE_INLINE (info->first_fp_reg_save))
bacbde18 3196 {
4697a36c 3197 int regno = info->first_fp_reg_save;
979721f8 3198 int loc = info->fp_save_offset + sp_offset;
4697a36c
MM		 3199
3200 for ( ; regno < 64; regno++, loc += 8)
979721f8 3201 asm_fprintf (file, "\tstfd %s,%d(%s)\n", reg_names[regno], loc, reg_names[sp_reg]);
bacbde18 3202 }
4697a36c
MM		 3203 else if (info->first_fp_reg_save != 64)
3204 asm_fprintf (file, "\tbl %s%d%s\n", SAVE_FP_PREFIX,
3205 info->first_fp_reg_save - 32, SAVE_FP_SUFFIX);
9878760c
RK		 3206
3207 /* Now save gpr's. */
4697a36c 3208 if (! TARGET_MULTIPLE || info->first_gp_reg_save == 31 || TARGET_64BIT)
85638c0d 3209 {
4697a36c 3210 int regno = info->first_gp_reg_save;
979721f8 3211 int loc = info->gp_save_offset + sp_offset;
85638c0d 3212
4697a36c 3213 for ( ; regno < 32; regno++, loc += reg_size)
979721f8 3214 asm_fprintf (file, store_reg, reg_names[regno], loc, reg_names[sp_reg]);
85638c0d
RK		 3215 }
3216
4697a36c
MM		 3217 else if (info->first_gp_reg_save != 32)
3218 asm_fprintf (file, "\t{stm|stmw} %s,%d(%s)\n",
3219 reg_names[info->first_gp_reg_save],
979721f8
MM		 3220 info->gp_save_offset + sp_offset,
3221 reg_names[sp_reg]);
9878760c 3222
b6c9286a
MM		 3223 /* Save main's arguments if we need to call a function */
3224#ifdef NAME__MAIN
3225 if (info->main_save_p)
3226 {
3227 int regno;
5ebfb2ba 3228 int loc = info->main_save_offset + sp_offset;
b6c9286a
MM		 3229 int size = info->main_size;
3230
3231 for (regno = 3; size > 0; regno++, loc -= reg_size, size -= reg_size)
979721f8 3232 asm_fprintf (file, store_reg, reg_names[regno], loc, reg_names[sp_reg]);
b6c9286a
MM		 3233 }
3234#endif
3235
9878760c 3236 /* Save lr if we used it. */
4697a36c 3237 if (info->lr_save_p)
979721f8
MM		 3238 asm_fprintf (file, store_reg, reg_names[0], info->lr_save_offset + sp_offset,
3239 reg_names[sp_reg]);
9878760c
RK		 3240
3241 /* Save CR if we use any that must be preserved. */
4697a36c 3242 if (info->cr_save_p)
979721f8
MM		 3243 {
3244 if (sp_reg == 12) /* If r12 is used to hold the original sp, copy cr now */
3245 {
3246 asm_fprintf (file, "\tmfcr %s\n", reg_names[0]);
3247 asm_fprintf (file, store_reg, reg_names[0],
3248 info->cr_save_offset + sp_offset,
3249 reg_names[sp_reg]);
3250 }
3251 else
3252 asm_fprintf (file, store_reg, reg_names[12], info->cr_save_offset + sp_offset,
3253 reg_names[sp_reg]);
3254 }
9878760c 3255
b6c9286a 3256 if (info->toc_save_p)
979721f8
MM		 3257 asm_fprintf (file, store_reg, reg_names[2], info->toc_save_offset + sp_offset,
3258 reg_names[sp_reg]);
b6c9286a 3259
979721f8
MM		 3260 /* NT needs us to probe the stack frame every 4k pages for large frames, so
3261 do it here. */
3262 if (DEFAULT_ABI == ABI_NT && info->total_size > 4096)
3263 {
3264 if (info->total_size < 32768)
3265 {
3266 int probe_offset = 4096;
3267 while (probe_offset < info->total_size)
3268 {
3269 asm_fprintf (file, "\t{l|lwz} %s,%d(%s)\n", reg_names[0], -probe_offset, reg_names[1]);
3270 probe_offset += 4096;
3271 }
3272 }
3273 else
3274 {
3275 int probe_iterations = info->total_size / 4096;
3276 static int probe_labelno = 0;
3277 char buf[256];
3278
3279 if (probe_iterations < 32768)
3280 asm_fprintf (file, "\tli %s,%d\n", reg_names[12], probe_iterations);
3281 else
3282 {
3283 asm_fprintf (file, "\tlis %s,%d\n", reg_names[12], probe_iterations >> 16);
3284 if (probe_iterations & 0xffff)
3285 asm_fprintf (file, "\tori %s,%s,%d\n", reg_names[12], reg_names[12],
3286 probe_iterations & 0xffff);
3287 }
3288 asm_fprintf (file, "\tmtctr %s\n", reg_names[12]);
3289 asm_fprintf (file, "\tmr %s,%s\n", reg_names[12], reg_names[1]);
3290 ASM_OUTPUT_INTERNAL_LABEL (file, "LCprobe", probe_labelno);
3291 asm_fprintf (file, "\t{lu|lwzu} %s,-4096(%s)\n", reg_names[0], reg_names[12]);
3292 ASM_GENERATE_INTERNAL_LABEL (buf, "LCprobe", probe_labelno);
3293 fputs ("\tbdnz ", file);
3294 assemble_name (file, buf);
3295 fputs ("\n", file);
3296 }
3297 }
3298
3299 /* Update stack and set back pointer and we have already done so for V.4. */
c81bebd7 3300 if (info->push_p && DEFAULT_ABI != ABI_V4 && DEFAULT_ABI != ABI_SOLARIS)
9878760c 3301 {
4697a36c
MM		 3302 if (info->total_size < 32767)
3303 asm_fprintf (file,
8f802bfb 3304 (TARGET_32BIT) ? "\t{stu|stwu} %s,%d(%s)\n" : "\tstdu %s,%d(%s)\n",
4697a36c 3305 reg_names[1], - info->total_size, reg_names[1]);
9878760c
RK		 3306 else
3307 {
ef7a1424 3308 int neg_size = - info->total_size;
4697a36c 3309 asm_fprintf (file, "\t{liu|lis} %s,%d\n\t{oril|ori} %s,%s,%d\n",
ef7a1424
RK		 3310 reg_names[0], (neg_size >> 16) & 0xffff,
3311 reg_names[0], reg_names[0], neg_size & 0xffff);
4697a36c 3312 asm_fprintf (file,
8f802bfb 3313 (TARGET_32BIT) ? "\t{stux|stwux} %s,%s,%s\n" : "\tstdux %s,%s,%s\n",
4697a36c 3314 reg_names[1], reg_names[1], reg_names[0]);
9878760c
RK		 3315 }
3316 }
3317
3318 /* Set frame pointer, if needed. */
3319 if (frame_pointer_needed)
4697a36c 3320 asm_fprintf (file, "\tmr %s,%s\n", reg_names[31], reg_names[1]);
1875cc88 3321
b6c9286a
MM		 3322#ifdef NAME__MAIN
3323 /* If we need to call a function to set things up for main, do so now
3324 before dealing with the TOC. */
3325 if (info->main_p)
3326 {
3327 char *prefix = "";
3328
3329 switch (DEFAULT_ABI)
3330 {
3331 case ABI_AIX: prefix = "."; break;
3332 case ABI_NT: prefix = ".."; break;
3333 }
3334
3335 fprintf (file, "\tbl %s%s\n", prefix, NAME__MAIN);
3336#ifdef RS6000_CALL_GLUE2
3337 fprintf (file, "\t%s%s%s\n", RS6000_CALL_GLUE2, prefix, NAME_MAIN);
3338#else
3339#ifdef RS6000_CALL_GLUE
3340 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_NT)
3341 fprintf (file, "\t%s\n", RS6000_CALL_GLUE);
3342#endif
3343#endif
3344
3345 if (info->main_save_p)
3346 {
3347 int regno;
3348 int loc;
3349 int size = info->main_size;
3350
3351 if (info->total_size < 32767)
3352 {
3353 loc = info->total_size + info->main_save_offset;
3354 for (regno = 3; size > 0; regno++, size -= reg_size, loc -= reg_size)
3355 asm_fprintf (file, load_reg, reg_names[regno], loc, reg_names[1]);
3356 }
3357 else
5ebfb2ba
MM		 3358 {
3359 int neg_size = info->main_save_offset - info->total_size;
3360 loc = 0;
3361 asm_fprintf (file, "\t{liu|lis} %s,%d\n\t{oril|ori} %s,%s,%d\n",
3362 reg_names[0], (neg_size >> 16) & 0xffff,
3363 reg_names[0], reg_names[0], neg_size & 0xffff);
979721f8 3364
b6c9286a
MM		 3365 asm_fprintf (file, "\t{sf|subf} %s,%s,%s\n", reg_names[0], reg_names[0],
3366 reg_names[1]);
3367
3368 for (regno = 3; size > 0; regno++, size -= reg_size, loc -= reg_size)
3369 asm_fprintf (file, load_reg, reg_names[regno], loc, reg_names[0]);
3370 }
3371 }
3372 }
3373#endif
3374
3375
1875cc88
JW		 3376 /* If TARGET_MINIMAL_TOC, and the constant pool is needed, then load the
3377 TOC_TABLE address into register 30. */
4697a36c 3378 if (TARGET_TOC && TARGET_MINIMAL_TOC && get_pool_size () != 0)
3daf36a4 3379 {
d14a6d05
MM		 3380 char buf[256];
3381
b6c9286a 3382#ifdef TARGET_RELOCATABLE
d14a6d05
MM		 3383 if (TARGET_RELOCATABLE)
3384 {
874a0744 3385 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
19d2d16f 3386 fputs ("\tbl ", file);
d14a6d05 3387 assemble_name (file, buf);
19d2d16f 3388 putc ('\n', file);
d14a6d05 3389
874a0744 3390 ASM_OUTPUT_INTERNAL_LABEL (file, "LCF", rs6000_pic_labelno);
4697a36c 3391 fprintf (file, "\tmflr %s\n", reg_names[30]);
3daf36a4 3392
03a7e1a5 3393 asm_fprintf (file, (TARGET_32BIT) ? "\t{l|lwz}" : "\tld");
4697a36c 3394 fprintf (file, " %s,(", reg_names[0]);
874a0744
MM		 3395 ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno);
3396 assemble_name (file, buf);
19d2d16f 3397 putc ('-', file);
874a0744
MM		 3398 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
3399 assemble_name (file, buf);
4697a36c
MM		 3400 fprintf (file, ")(%s)\n", reg_names[30]);
3401 asm_fprintf (file, "\t{cax|add} %s,%s,%s\n",
3402 reg_names[30], reg_names[0], reg_names[30]);
874a0744 3403 rs6000_pic_labelno++;
d14a6d05 3404 }
b6c9286a
MM		 3405 else
3406#endif
3407
3408 switch (DEFAULT_ABI)
3409 {
3410 case ABI_V4:
c81bebd7 3411 case ABI_SOLARIS:
b6c9286a 3412 case ABI_AIX_NODESC:
8f802bfb 3413 if (TARGET_32BIT)
b6c9286a
MM		 3414 {
3415 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
3416 asm_fprintf (file, "\t{cau|addis} %s,%s,", reg_names[30], reg_names[0]);
3417 assemble_name (file, buf);
3418 asm_fprintf (file, "@ha\n");
3419 if (TARGET_NEW_MNEMONICS)
3420 {
3421 asm_fprintf (file, "\taddi %s,%s,", reg_names[30], reg_names[30]);
3422 assemble_name (file, buf);
3423 asm_fprintf (file, "@l\n");
3424 }
3425 else
3426 {
3427 asm_fprintf (file, "\tcal %s,", reg_names[30]);
3428 assemble_name (file, buf);
3429 asm_fprintf (file, "@l(%s)\n", reg_names[30]);
3430 }
3431 }
3432 else
3433 abort ();
3434
3435 break;
3436
3437 case ABI_NT:
3438 case ABI_AIX:
3439 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 0);
3440 asm_fprintf (file, "\t{l|lwz} %s,", reg_names[30]);
3933e0e1 3441 assemble_name (file, buf);
b6c9286a
MM		 3442 asm_fprintf (file, "(%s)\n", reg_names[2]);
3443 break;
3933e0e1 3444 }
b6c9286a 3445 }
4697a36c 3446
b6c9286a
MM		 3447 if (DEFAULT_ABI == ABI_NT)
3448 {
3449 assemble_name (file, XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0));
3450 fputs (".b:\n", file);
3daf36a4 3451 }
9878760c
RK		 3452}
3453
3454/* Write function epilogue. */
3455
3456void
3457output_epilog (file, size)
3458 FILE *file;
3459 int size;
3460{
4697a36c 3461 rs6000_stack_t *info = rs6000_stack_info ();
8f802bfb 3462 char *load_reg = (TARGET_32BIT) ? "\t{l|lwz} %s,%d(%s)\n" : "\tld %s,%d(%s)\n";
9878760c 3463 rtx insn = get_last_insn ();
979721f8
MM		 3464 int sp_reg = 1;
3465 int sp_offset = 0;
5b5040b9 3466 int i;
9878760c 3467
9878760c
RK		 3468 /* If the last insn was a BARRIER, we don't have to write anything except
3469 the trace table. */
3470 if (GET_CODE (insn) == NOTE)
3471 insn = prev_nonnote_insn (insn);
3472 if (insn == 0 || GET_CODE (insn) != BARRIER)
3473 {
3474 /* If we have a frame pointer, a call to alloca, or a large stack
3475 frame, restore the old stack pointer using the backchain. Otherwise,
3476 we know what size to update it with. */
3477 if (frame_pointer_needed || current_function_calls_alloca
4697a36c 3478 || info->total_size > 32767)
979721f8
MM		 3479 {
3480 /* Under V.4, don't reset the stack pointer until after we're done
3481 loading the saved registers. */
c81bebd7 3482 if (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS)
979721f8
MM		 3483 sp_reg = 11;
3484
3485 asm_fprintf (file, load_reg, reg_names[sp_reg], 0, reg_names[1]);
3486 }
4697a36c
MM		 3487 else if (info->push_p)
3488 {
c81bebd7 3489 if (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS)
979721f8
MM		 3490 sp_offset = info->total_size;
3491 else if (TARGET_NEW_MNEMONICS)
4697a36c
MM		 3492 asm_fprintf (file, "\taddi %s,%s,%d\n", reg_names[1], reg_names[1], info->total_size);
3493 else
3494 asm_fprintf (file, "\tcal %s,%d(%s)\n", reg_names[1], info->total_size, reg_names[1]);
3495 }
9878760c 3496
b4ac57ab 3497 /* Get the old lr if we saved it. */
4697a36c 3498 if (info->lr_save_p)
979721f8 3499 asm_fprintf (file, load_reg, reg_names[0], info->lr_save_offset + sp_offset, reg_names[sp_reg]);
9878760c
RK		 3500
3501 /* Get the old cr if we saved it. */
4697a36c 3502 if (info->cr_save_p)
979721f8 3503 asm_fprintf (file, load_reg, reg_names[12], info->cr_save_offset + sp_offset, reg_names[sp_reg]);
9878760c 3504
b4ac57ab 3505 /* Set LR here to try to overlap restores below. */
4697a36c
MM		 3506 if (info->lr_save_p)
3507 asm_fprintf (file, "\tmtlr %s\n", reg_names[0]);
b4ac57ab 3508
9878760c 3509 /* Restore gpr's. */
4697a36c 3510 if (! TARGET_MULTIPLE || info->first_gp_reg_save == 31 || TARGET_64BIT)
85638c0d 3511 {
4697a36c 3512 int regno = info->first_gp_reg_save;
979721f8 3513 int loc = info->gp_save_offset + sp_offset;
8f802bfb 3514 int reg_size = (TARGET_32BIT) ? 4 : 8;
85638c0d 3515
4697a36c 3516 for ( ; regno < 32; regno++, loc += reg_size)
979721f8 3517 asm_fprintf (file, load_reg, reg_names[regno], loc, reg_names[sp_reg]);
85638c0d
RK		 3518 }
3519
4697a36c
MM		 3520 else if (info->first_gp_reg_save != 32)
3521 asm_fprintf (file, "\t{lm|lmw} %s,%d(%s)\n",
3522 reg_names[info->first_gp_reg_save],
979721f8
MM		 3523 info->gp_save_offset + sp_offset,
3524 reg_names[sp_reg]);
9878760c 3525
b4ac57ab 3526 /* Restore fpr's if we can do it without calling a function. */
4697a36c
MM		 3527 if (FP_SAVE_INLINE (info->first_fp_reg_save))
3528 {
3529 int regno = info->first_fp_reg_save;
979721f8 3530 int loc = info->fp_save_offset + sp_offset;
4697a36c
MM		 3531
3532 for ( ; regno < 64; regno++, loc += 8)
979721f8 3533 asm_fprintf (file, "\tlfd %s,%d(%s)\n", reg_names[regno], loc, reg_names[sp_reg]);
4697a36c 3534 }
9878760c 3535
28edebac
RK		 3536 /* If we saved cr, restore it here. Just those of cr2, cr3, and cr4
3537 that were used. */
4697a36c
MM		 3538 if (info->cr_save_p)
3539 asm_fprintf (file, "\tmtcrf %d,%s\n",
85638c0d
RK		 3540 (regs_ever_live[70] != 0) * 0x20
3541 + (regs_ever_live[71] != 0) * 0x10
4697a36c 3542 + (regs_ever_live[72] != 0) * 0x8, reg_names[12]);
9878760c 3543
979721f8
MM		 3544 /* If this is V.4, unwind the stack pointer after all of the loads have been done */
3545 if (sp_offset)
3546 {
3547 if (TARGET_NEW_MNEMONICS)
3548 asm_fprintf (file, "\taddi %s,%s,%d\n", reg_names[1], reg_names[1], sp_offset);
3549 else
3550 asm_fprintf (file, "\tcal %s,%d(%s)\n", reg_names[1], sp_offset, reg_names[1]);
3551 }
3552 else if (sp_reg != 1)
3553 asm_fprintf (file, "\tmr %s,%s\n", reg_names[1], reg_names[sp_reg]);
3554
b4ac57ab
RS		 3555 /* If we have to restore more than two FP registers, branch to the
3556 restore function. It will return to our caller. */
4697a36c
MM		 3557 if (info->first_fp_reg_save != 64 && !FP_SAVE_INLINE (info->first_fp_reg_save))
3558 asm_fprintf (file, "\tb %s%d%s\n", RESTORE_FP_PREFIX,
3559 info->first_fp_reg_save - 32, RESTORE_FP_SUFFIX);
b4ac57ab 3560 else
85638c0d 3561 asm_fprintf (file, "\t{br|blr}\n");
9878760c 3562 }
b4ac57ab 3563
9b30bae2 3564 /* Output a traceback table here. See /usr/include/sys/debug.h for info
314fc5a9
ILT		 3565 on its format.
3566
3567 We don't output a traceback table if -finhibit-size-directive was
3568 used. The documentation for -finhibit-size-directive reads
3569 ``don't output a @code{.size} assembler directive, or anything
3570 else that would cause trouble if the function is split in the
3571 middle, and the two halves are placed at locations far apart in
3572 memory.'' The traceback table has this property, since it
3573 includes the offset from the start of the function to the
4d30c363
MM		 3574 traceback table itself.
3575
3576 System V.4 Powerpc's (and the embedded ABI derived from it) use a
b6c9286a
MM		 3577 different traceback table. */
3578 if (DEFAULT_ABI == ABI_AIX && ! flag_inhibit_size_directive)
9b30bae2 3579 {
314fc5a9
ILT		 3580 char *fname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
3581 int fixed_parms, float_parms, parm_info;
3582 int i;
3583
b6c9286a
MM		 3584 while (*fname == '.') /* V.4 encodes . in the name */
3585 fname++;
3586
314fc5a9
ILT		 3587 /* Need label immediately before tbtab, so we can compute its offset
3588 from the function start. */
3589 if (*fname == '*')
3590 ++fname;
3591 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
3592 ASM_OUTPUT_LABEL (file, fname);
3593
3594 /* The .tbtab pseudo-op can only be used for the first eight
3595 expressions, since it can't handle the possibly variable
3596 length fields that follow. However, if you omit the optional
3597 fields, the assembler outputs zeros for all optional fields
3598 anyways, giving each variable length field is minimum length
3599 (as defined in sys/debug.h). Thus we can not use the .tbtab
3600 pseudo-op at all. */
3601
3602 /* An all-zero word flags the start of the tbtab, for debuggers
3603 that have to find it by searching forward from the entry
3604 point or from the current pc. */
19d2d16f 3605 fputs ("\t.long 0\n", file);
314fc5a9
ILT		 3606
3607 /* Tbtab format type. Use format type 0. */
19d2d16f 3608 fputs ("\t.byte 0,", file);
314fc5a9
ILT		 3609
3610 /* Language type. Unfortunately, there doesn't seem to be any
3611 official way to get this info, so we use language_string. C
3612 is 0. C++ is 9. No number defined for Obj-C, so use the
3613 value for C for now. */
3614 if (! strcmp (language_string, "GNU C")
3615 || ! strcmp (language_string, "GNU Obj-C"))
3616 i = 0;
3617 else if (! strcmp (language_string, "GNU F77"))
3618 i = 1;
3619 else if (! strcmp (language_string, "GNU Ada"))
3620 i = 3;
3621 else if (! strcmp (language_string, "GNU PASCAL"))
3622 i = 2;
3623 else if (! strcmp (language_string, "GNU C++"))
3624 i = 9;
3625 else
3626 abort ();
3627 fprintf (file, "%d,", i);
3628
3629 /* 8 single bit fields: global linkage (not set for C extern linkage,
3630 apparently a PL/I convention?), out-of-line epilogue/prologue, offset
3631 from start of procedure stored in tbtab, internal function, function
3632 has controlled storage, function has no toc, function uses fp,
3633 function logs/aborts fp operations. */
3634 /* Assume that fp operations are used if any fp reg must be saved. */
4697a36c 3635 fprintf (file, "%d,", (1 << 5) | ((info->first_fp_reg_save != 64) << 1));
314fc5a9
ILT		 3636
3637 /* 6 bitfields: function is interrupt handler, name present in
3638 proc table, function calls alloca, on condition directives
3639 (controls stack walks, 3 bits), saves condition reg, saves
3640 link reg. */
3641 /* The `function calls alloca' bit seems to be set whenever reg 31 is
3642 set up as a frame pointer, even when there is no alloca call. */
3643 fprintf (file, "%d,",
3644 ((1 << 6) | (frame_pointer_needed << 5)
4697a36c 3645 | (info->cr_save_p << 1) | (info->lr_save_p)));
314fc5a9
ILT		 3646
3647 /* 3 bitfields: saves backchain, spare bit, number of fpr saved
3648 (6 bits). */
3649 fprintf (file, "%d,",
4697a36c 3650 (info->push_p << 7) | (64 - info->first_fp_reg_save));
314fc5a9
ILT		 3651
3652 /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */
3653 fprintf (file, "%d,", (32 - first_reg_to_save ()));
3654
3655 {
3656 /* Compute the parameter info from the function decl argument
3657 list. */
3658 tree decl;
3659 int next_parm_info_bit;
3660
3661 next_parm_info_bit = 31;
3662 parm_info = 0;
3663 fixed_parms = 0;
3664 float_parms = 0;
3665
3666 for (decl = DECL_ARGUMENTS (current_function_decl);
3667 decl; decl = TREE_CHAIN (decl))
3668 {
3669 rtx parameter = DECL_INCOMING_RTL (decl);
3670 enum machine_mode mode = GET_MODE (parameter);
3671
3672 if (GET_CODE (parameter) == REG)
3673 {
3674 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
3675 {
3676 int bits;
3677
3678 float_parms++;
3679
3680 if (mode == SFmode)
3681 bits = 0x2;
3682 else if (mode == DFmode)
3683 bits = 0x3;
3684 else
3685 abort ();
3686
3687 /* If only one bit will fit, don't or in this entry. */
3688 if (next_parm_info_bit > 0)
3689 parm_info |= (bits << (next_parm_info_bit - 1));
3690 next_parm_info_bit -= 2;
3691 }
3692 else
3693 {
3694 fixed_parms += ((GET_MODE_SIZE (mode)
3695 + (UNITS_PER_WORD - 1))
3696 / UNITS_PER_WORD);
3697 next_parm_info_bit -= 1;
3698 }
3699 }
3700 }
3701 }
3702
3703 /* Number of fixed point parameters. */
3704 /* This is actually the number of words of fixed point parameters; thus
3705 an 8 byte struct counts as 2; and thus the maximum value is 8. */
3706 fprintf (file, "%d,", fixed_parms);
3707
3708 /* 2 bitfields: number of floating point parameters (7 bits), parameters
3709 all on stack. */
3710 /* This is actually the number of fp registers that hold parameters;
3711 and thus the maximum value is 13. */
3712 /* Set parameters on stack bit if parameters are not in their original
3713 registers, regardless of whether they are on the stack? Xlc
3714 seems to set the bit when not optimizing. */
3715 fprintf (file, "%d\n", ((float_parms << 1) | (! optimize)));
3716
3717 /* Optional fields follow. Some are variable length. */
3718
3719 /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float,
3720 11 double float. */
3721 /* There is an entry for each parameter in a register, in the order that
3722 they occur in the parameter list. Any intervening arguments on the
3723 stack are ignored. If the list overflows a long (max possible length
3724 34 bits) then completely leave off all elements that don't fit. */
3725 /* Only emit this long if there was at least one parameter. */
3726 if (fixed_parms || float_parms)
3727 fprintf (file, "\t.long %d\n", parm_info);
3728
3729 /* Offset from start of code to tb table. */
19d2d16f 3730 fputs ("\t.long ", file);
314fc5a9
ILT		 3731 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
3732 RS6000_OUTPUT_BASENAME (file, fname);
19d2d16f 3733 fputs ("-.", file);
314fc5a9 3734 RS6000_OUTPUT_BASENAME (file, fname);
19d2d16f 3735 putc ('\n', file);
314fc5a9
ILT		 3736
3737 /* Interrupt handler mask. */
3738 /* Omit this long, since we never set the interrupt handler bit
3739 above. */
3740
3741 /* Number of CTL (controlled storage) anchors. */
3742 /* Omit this long, since the has_ctl bit is never set above. */
3743
3744 /* Displacement into stack of each CTL anchor. */
3745 /* Omit this list of longs, because there are no CTL anchors. */
3746
3747 /* Length of function name. */
3748 fprintf (file, "\t.short %d\n", strlen (fname));
3749
3750 /* Function name. */
3751 assemble_string (fname, strlen (fname));
3752
3753 /* Register for alloca automatic storage; this is always reg 31.
3754 Only emit this if the alloca bit was set above. */
3755 if (frame_pointer_needed)
19d2d16f 3756 fputs ("\t.byte 31\n", file);
9b30bae2 3757 }
4697a36c 3758
b6c9286a 3759 /* Reset varargs and save TOC indicator */
4697a36c 3760 rs6000_sysv_varargs_p = 0;
b6c9286a 3761 rs6000_save_toc_p = 0;
802a0058
MM		 3762 rs6000_fpmem_size = 0;
3763 rs6000_fpmem_offset = 0;
62cb0901 3764 pic_offset_table_rtx = (rtx)0;
b6c9286a
MM		 3765
3766 if (DEFAULT_ABI == ABI_NT)
3767 {
3768 RS6000_OUTPUT_BASENAME (file, XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0));
3769 fputs (".e:\nFE_MOT_RESVD..", file);
3770 RS6000_OUTPUT_BASENAME (file, XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0));
3771 fputs (":\n", file);
3772 }
9878760c
RK		 3773}
3774\f
3775/* Output a TOC entry. We derive the entry name from what is
3776 being written. */
3777
3778void
3779output_toc (file, x, labelno)
3780 FILE *file;
3781 rtx x;
3782 int labelno;
3783{
3784 char buf[256];
3785 char *name = buf;
b6c9286a 3786 char *real_name;
9878760c
RK		 3787 rtx base = x;
3788 int offset = 0;
3789
4697a36c
MM		 3790 if (TARGET_NO_TOC)
3791 abort ();
3792
ff1720ed
RK		 3793 /* if we're going to put a double constant in the TOC, make sure it's
3794 aligned properly when strict alignment is on. */
3795 if (GET_CODE (x) == CONST_DOUBLE
3796 && STRICT_ALIGNMENT
3797 && GET_MODE (x) == DFmode
3798 && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC)) {
3799 ASM_OUTPUT_ALIGN (file, 3);
3800 }
3801
3802
b6c9286a 3803 if (TARGET_ELF && TARGET_MINIMAL_TOC)
d14a6d05
MM		 3804 {
3805 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
3806 fprintf (file, "%d = .-", labelno);
3807 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LCTOC");
19d2d16f 3808 fputs ("1\n", file);
d14a6d05
MM		 3809 }
3810 else
d14a6d05 3811 ASM_OUTPUT_INTERNAL_LABEL (file, "LC", labelno);
9878760c 3812
37c37a57
RK		 3813 /* Handle FP constants specially. Note that if we have a minimal
3814 TOC, things we put here aren't actually in the TOC, so we can allow
3815 FP constants. */
042259f2 3816 if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode
37c37a57 3817 && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC))
9878760c 3818 {
042259f2
DE		 3819 REAL_VALUE_TYPE rv;
3820 long k[2];
0adc764e 3821
042259f2
DE		 3822 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
3823 REAL_VALUE_TO_TARGET_DOUBLE (rv, k);
1875cc88 3824 if (TARGET_MINIMAL_TOC)
042259f2 3825 fprintf (file, "\t.long %ld\n\t.long %ld\n", k[0], k[1]);
1875cc88 3826 else
0adc764e 3827 fprintf (file, "\t.tc FD_%lx_%lx[TC],%ld,%ld\n",
042259f2 3828 k[0], k[1], k[0], k[1]);
9878760c
RK		 3829 return;
3830 }
3831 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode
37c37a57 3832 && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC))
9878760c 3833 {
042259f2
DE		 3834 REAL_VALUE_TYPE rv;
3835 long l;
9878760c 3836
042259f2
DE		 3837 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
3838 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
3839
3840 if (TARGET_MINIMAL_TOC)
3841 fprintf (file, "\t.long %d\n", l);
3842 else
3843 fprintf (file, "\t.tc FS_%x[TC],%d\n", l, l);
3844 return;
3845 }
3846 else if (GET_MODE (x) == DImode
3847 && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE)
3848 && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC))
3849 {
3850 HOST_WIDE_INT low;
3851 HOST_WIDE_INT high;
3852
3853 if (GET_CODE (x) == CONST_DOUBLE)
3854 {
3855 low = CONST_DOUBLE_LOW (x);
3856 high = CONST_DOUBLE_HIGH (x);
3857 }
3858 else
3859#if HOST_BITS_PER_WIDE_INT == 32
3860 {
3861 low = INTVAL (x);
3862 high = (low < 0) ? ~0 : 0;
3863 }
3864#else
3865 {
3866 low = INTVAL (x) & 0xffffffff;
3867 high = (HOST_WIDE_INT) INTVAL (x) >> 32;
3868 }
3869#endif
9878760c 3870
1875cc88 3871 if (TARGET_MINIMAL_TOC)
042259f2 3872 fprintf (file, "\t.long %ld\n\t.long %ld\n", high, low);
1875cc88 3873 else
042259f2
DE		 3874 fprintf (file, "\t.tc ID_%lx_%lx[TC],%ld,%ld\n",
3875 high, low, high, low);
9878760c
RK		 3876 return;
3877 }
3878
3879 if (GET_CODE (x) == CONST)
3880 {
3881 base = XEXP (XEXP (x, 0), 0);
3882 offset = INTVAL (XEXP (XEXP (x, 0), 1));
3883 }
3884
3885 if (GET_CODE (base) == SYMBOL_REF)
3886 name = XSTR (base, 0);
3887 else if (GET_CODE (base) == LABEL_REF)
3888 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (XEXP (base, 0)));
3889 else if (GET_CODE (base) == CODE_LABEL)
3890 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (base));
3891 else
3892 abort ();
3893
1875cc88 3894 if (TARGET_MINIMAL_TOC)
19d2d16f 3895 fputs ("\t.long ", file);
1875cc88
JW		 3896 else
3897 {
b6c9286a
MM		 3898 STRIP_NAME_ENCODING (real_name, name);
3899 fprintf (file, "\t.tc %s", real_name);
9878760c 3900
1875cc88
JW		 3901 if (offset < 0)
3902 fprintf (file, ".N%d", - offset);
3903 else if (offset)
3904 fprintf (file, ".P%d", offset);
9878760c 3905
19d2d16f 3906 fputs ("[TC],", file);
1875cc88 3907 }
9878760c 3908 output_addr_const (file, x);
19d2d16f 3909 putc ('\n', file);
9878760c
RK		 3910}
3911\f
3912/* Output an assembler pseudo-op to write an ASCII string of N characters
3913 starting at P to FILE.
3914
3915 On the RS/6000, we have to do this using the .byte operation and
3916 write out special characters outside the quoted string.
3917 Also, the assembler is broken; very long strings are truncated,
3918 so we must artificially break them up early. */
3919
3920void
3921output_ascii (file, p, n)
3922 FILE *file;
3923 char *p;
3924 int n;
3925{
3926 char c;
3927 int i, count_string;
3928 char *for_string = "\t.byte \"";
3929 char *for_decimal = "\t.byte ";
3930 char *to_close = NULL;
3931
3932 count_string = 0;
3933 for (i = 0; i < n; i++)
3934 {
3935 c = *p++;
3936 if (c >= ' ' && c < 0177)
3937 {
3938 if (for_string)
3939 fputs (for_string, file);
3940 putc (c, file);
3941
3942 /* Write two quotes to get one. */
3943 if (c == '"')
3944 {
3945 putc (c, file);
3946 ++count_string;
3947 }
3948
3949 for_string = NULL;
3950 for_decimal = "\"\n\t.byte ";
3951 to_close = "\"\n";
3952 ++count_string;
3953
3954 if (count_string >= 512)
3955 {
3956 fputs (to_close, file);
3957
3958 for_string = "\t.byte \"";
3959 for_decimal = "\t.byte ";
3960 to_close = NULL;
3961 count_string = 0;
3962 }
3963 }
3964 else
3965 {
3966 if (for_decimal)
3967 fputs (for_decimal, file);
3968 fprintf (file, "%d", c);
3969
3970 for_string = "\n\t.byte \"";
3971 for_decimal = ", ";
3972 to_close = "\n";
3973 count_string = 0;
3974 }
3975 }
3976
3977 /* Now close the string if we have written one. Then end the line. */
3978 if (to_close)
3979 fprintf (file, to_close);
3980}
3981\f
3982/* Generate a unique section name for FILENAME for a section type
3983 represented by SECTION_DESC. Output goes into BUF.
3984
3985 SECTION_DESC can be any string, as long as it is different for each
3986 possible section type.
3987
3988 We name the section in the same manner as xlc. The name begins with an
3989 underscore followed by the filename (after stripping any leading directory
11e5fe42
RK		 3990 names) with the last period replaced by the string SECTION_DESC. If
3991 FILENAME does not contain a period, SECTION_DESC is appended to the end of
3992 the name. */
9878760c
RK		 3993
3994void
3995rs6000_gen_section_name (buf, filename, section_desc)
3996 char **buf;
3997 char *filename;
3998 char *section_desc;
3999{
11e5fe42 4000 char *q, *after_last_slash, *last_period;
9878760c
RK		 4001 char *p;
4002 int len;
9878760c
RK		 4003
4004 after_last_slash = filename;
4005 for (q = filename; *q; q++)
11e5fe42
RK		 4006 {
4007 if (*q == '/')
4008 after_last_slash = q + 1;
4009 else if (*q == '.')
4010 last_period = q;
4011 }
9878760c 4012
11e5fe42 4013 len = strlen (after_last_slash) + strlen (section_desc) + 2;
9878760c
RK		 4014 *buf = (char *) permalloc (len);
4015
4016 p = *buf;
4017 *p++ = '_';
4018
4019 for (q = after_last_slash; *q; q++)
4020 {
11e5fe42 4021 if (q == last_period)
9878760c
RK		 4022 {
4023 strcpy (p, section_desc);
4024 p += strlen (section_desc);
9878760c
RK		 4025 }
4026
4027 else if (isalnum (*q))
4028 *p++ = *q;
4029 }
4030
11e5fe42 4031 if (last_period == 0)
9878760c
RK		 4032 strcpy (p, section_desc);
4033 else
4034 *p = '\0';
4035}
e165f3f0
RK		 4036\f
4037/* Write function profiler code. */
4038
4039void
4040output_function_profiler (file, labelno)
4041 FILE *file;
4042 int labelno;
4043{
4044 /* The last used parameter register. */
4045 int last_parm_reg;
4046 int i, j;
3daf36a4 4047 char buf[100];
e165f3f0 4048
b6c9286a
MM		 4049 if (DEFAULT_ABI != ABI_AIX)
4050 abort ();
4051
e165f3f0
RK		 4052 /* Set up a TOC entry for the profiler label. */
4053 toc_section ();
3daf36a4
ILT		 4054 ASM_OUTPUT_INTERNAL_LABEL (file, "LPC", labelno);
4055 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
35fc1624 4056 if (TARGET_MINIMAL_TOC)
3daf36a4 4057 {
19d2d16f 4058 fputs ("\t.long ", file);
3daf36a4 4059 assemble_name (file, buf);
19d2d16f 4060 putc ('\n', file);
3daf36a4 4061 }
35fc1624 4062 else
3daf36a4 4063 {
19d2d16f 4064 fputs ("\t.tc\t", file);
3daf36a4 4065 assemble_name (file, buf);
19d2d16f 4066 fputs ("[TC],", file);
3daf36a4 4067 assemble_name (file, buf);
19d2d16f 4068 putc ('\n', file);
3daf36a4 4069 }
e165f3f0
RK		 4070 text_section ();
4071
4072 /* Figure out last used parameter register. The proper thing to do is
4073 to walk incoming args of the function. A function might have live
4074 parameter registers even if it has no incoming args. */
4075
4076 for (last_parm_reg = 10;
4077 last_parm_reg > 2 && ! regs_ever_live [last_parm_reg];
4078 last_parm_reg--)
4079 ;
4080
4081 /* Save parameter registers in regs 23-30. Don't overwrite reg 31, since
4082 it might be set up as the frame pointer. */
4083
4084 for (i = 3, j = 30; i <= last_parm_reg; i++, j--)
19d2d16f 4085 asm_fprintf (file, "\tmr %d,%d\n", j, i);
e165f3f0
RK		 4086
4087 /* Load location address into r3, and call mcount. */
4088
3daf36a4 4089 ASM_GENERATE_INTERNAL_LABEL (buf, "LPC", labelno);
19d2d16f 4090 asm_fprintf (file, "\t{l|lwz} %s,", reg_names[3]);
3daf36a4 4091 assemble_name (file, buf);
19d2d16f 4092 asm_fprintf (file, "(%s)\n\tbl .mcount\n", reg_names[2]);
e165f3f0
RK		 4093
4094 /* Restore parameter registers. */
4095
4096 for (i = 3, j = 30; i <= last_parm_reg; i++, j--)
19d2d16f 4097 asm_fprintf (file, "\tmr %d,%d\n", i, j);
e165f3f0 4098}
a251ffd0
TG		 4099
4100/* Adjust the cost of a scheduling dependency. Return the new cost of
4101 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
4102
4103int
a06faf84 4104rs6000_adjust_cost (insn, link, dep_insn, cost)
a251ffd0
TG		 4105 rtx insn;
4106 rtx link;
4107 rtx dep_insn;
4108 int cost;
4109{
4110 if (! recog_memoized (insn))
4111 return 0;
4112
4113 if (REG_NOTE_KIND (link) != 0)
4114 return 0;
4115
4116 if (REG_NOTE_KIND (link) == 0)
4117 {
4118 /* Data dependency; DEP_INSN writes a register that INSN reads some
4119 cycles later. */
4120
4121 /* Tell the first scheduling pass about the latency between a mtctr
4122 and bctr (and mtlr and br/blr). The first scheduling pass will not
4123 know about this latency since the mtctr instruction, which has the
4124 latency associated to it, will be generated by reload. */
4125 if (get_attr_type (insn) == TYPE_JMPREG)
4126 return TARGET_POWER ? 5 : 4;
4127
4128 /* Fall out to return default cost. */
4129 }
4130
4131 return cost;
4132}
b6c9286a
MM		 4133
4134/* Return how many instructions the machine can issue per cycle */
4135int get_issue_rate()
4136{
4137 switch (rs6000_cpu_attr) {
4138 case CPU_RIOS1:
4139 return 3; /* ? */
4140 case CPU_RIOS2:
4141 return 4;
4142 case CPU_PPC601:
4143 return 3; /* ? */
b6c9286a
MM		 4144 case CPU_PPC603:
4145 return 2;
4146 case CPU_PPC604:
4147 return 4;
4148 case CPU_PPC620:
4149 return 4;
4150 default:
4151 return 1;
4152 }
4153}
4154
4155\f
4156/* Output insns to flush the {data|instruction} caches after building a
4157 trampoline. */
4158
4159static void
4160rs6000_sync_trampoline (addr)
4161 rtx addr;
4162{
4163 enum machine_mode pmode = Pmode;
4164 rtx reg = gen_reg_rtx (pmode);
4165 rtx mem2;
4166 rtx mem1;
4167 int size = rs6000_trampoline_size ();
4168 rtx (*sub_fcn) PROTO ((rtx, rtx, rtx));
4169 rtx (*cmp_fcn) PROTO ((rtx, rtx));
4170 rtx label;
4171
ac2a93a1 4172 if (TARGET_32BIT)
b6c9286a 4173 {
ac2a93a1
DE		 4174 sub_fcn = gen_subsi3;
4175 cmp_fcn = gen_cmpsi;
b6c9286a
MM		 4176 }
4177 else
4178 {
ac2a93a1
DE		 4179 sub_fcn = gen_subdi3;
4180 cmp_fcn = gen_cmpdi;
b6c9286a
MM		 4181 }
4182
4183 addr = force_reg (pmode, addr);
4184 mem2 = gen_rtx (MEM, pmode, gen_rtx (PLUS, pmode, addr, reg));
4185 mem1 = gen_rtx (MEM, pmode, addr);
4186
4187 /* Issue a loop of dcbst's to flush the data cache */
4188 emit_move_insn (reg, GEN_INT (size-4));
4189 label = gen_label_rtx ();
4190 emit_label (label);
4191 emit_insn (gen_dcbst (mem2, addr, reg));
4192 emit_insn ((*sub_fcn) (reg, reg, GEN_INT (4)));
4193 emit_insn ((*cmp_fcn) (reg, const0_rtx));
4194 emit_jump_insn (gen_bgt (label));
4195
4196 /* Issue a sync after the dcbst's to let things settle down */
4197 emit_insn (gen_sync (mem1));
4198
4199 /* Issue a loop of icbi's to flush the instruction cache */
4200 emit_move_insn (reg, GEN_INT (size-4));
4201 label = gen_label_rtx ();
4202 emit_label (label);
4203 emit_insn (gen_icbi (mem2, addr, reg));
4204 emit_insn ((*sub_fcn) (reg, reg, GEN_INT (4)));
4205 emit_insn ((*cmp_fcn) (reg, const0_rtx));
4206 emit_jump_insn (gen_bgt (label));
4207
4208 /* Issue a sync after the icbi's to let things settle down */
4209 emit_insn (gen_sync (mem1));
4210
4211 /* Finally issue an isync to synchronize the icache */
4212 emit_insn (gen_isync (mem1));
4213}
4214
4215\f
4216/* Output assembler code for a block containing the constant parts
4217 of a trampoline, leaving space for the variable parts.
4218
4219 The trampoline should set the static chain pointer to value placed
4220 into the trampoline and should branch to the specified routine. */
4221
4222void
4223rs6000_trampoline_template (file)
4224 FILE *file;
4225{
4226 char *sc = reg_names[STATIC_CHAIN_REGNUM];
4227 char *r0 = reg_names[0];
7c59dc5d 4228 char *r2 = reg_names[2];
b6c9286a
MM		 4229
4230 switch (DEFAULT_ABI)
4231 {
4232 default:
4233 abort ();
4234
4235 /* Under AIX, this is not code at all, but merely a data area,
4236 since that is the way all functions are called. The first word is
4237 the address of the function, the second word is the TOC pointer (r2),
4238 and the third word is the static chain value. */
4239 case ABI_AIX:
8f802bfb 4240 fprintf (file, "\t.long %s\n", (TARGET_32BIT) ? "0,0,0" : "0,0,0,0,0,0");
b6c9286a
MM		 4241 break;
4242
4243
4244 /* V.4/eabi function pointers are just a single pointer, so we need to
4245 do the full gory code to load up the static chain. */
4246 case ABI_V4:
c81bebd7 4247 case ABI_SOLARIS:
b6c9286a
MM		 4248 case ABI_AIX_NODESC:
4249 if (STATIC_CHAIN_REGNUM == 0 || !TARGET_NEW_MNEMONICS)
4250 abort ();
4251
8f802bfb 4252 if (TARGET_32BIT)
b6c9286a
MM		 4253 {
4254 fprintf (file, "\tmflr %s\n", r0); /* offset 0 */
4255 fprintf (file, "\tbl .LTRAMP1\n"); /* offset 4 */
4256 fprintf (file, "\t.long 0,0\n"); /* offset 8 */
4257 fprintf (file, ".LTRAMP1:\n");
4258 fprintf (file, "\tmflr %s\n", sc); /* offset 20 */
4259 fprintf (file, "\tmtlr %s\n", r0); /* offset 24 */
4260 fprintf (file, "\tlwz %s,0(%s)\n", r0, sc); /* offset 28 */
4261 fprintf (file, "\tlwz %s,4(%s)\n", sc, sc); /* offset 32 */
4262 fprintf (file, "\tmtctr %s\n", r0); /* offset 36 */
4263 fprintf (file, "\tbctr\n"); /* offset 40 */
4264 }
8f802bfb
DE		 4265 else
4266 {
4267 fprintf (file, "\tmflr %s\n", r0); /* offset 0 */
4268 fprintf (file, "\tbl .LTRAMP1\n"); /* offset 4 */
4269 fprintf (file, "\t.long 0,0,0,0\n"); /* offset 8 */
4270 fprintf (file, ".LTRAMP1:\n");
4271 fprintf (file, "\tmflr %s\n", sc); /* offset 28 */
4272 fprintf (file, "\tmtlr %s\n", r0); /* offset 32 */
4273 fprintf (file, "\tld %s,0(%s)\n", r0, sc); /* offset 36 */
4274 fprintf (file, "\tld %s,8(%s)\n", sc, sc); /* offset 40 */
4275 fprintf (file, "\tmtctr %s\n", r0); /* offset 44 */
4276 fprintf (file, "\tbctr\n"); /* offset 48 */
4277 }
b6c9286a
MM		 4278 break;
4279
4280 /* NT function pointers point to a two word area (real address, TOC)
4281 which unfortunately does not include a static chain field. So we
7c59dc5d
MM		 4282 use the function field to point to ..LTRAMP1 and the toc field
4283 to point to the whole table. */
b6c9286a 4284 case ABI_NT:
7c59dc5d
MM		 4285 if (STATIC_CHAIN_REGNUM == 0
4286 || STATIC_CHAIN_REGNUM == 2
4287 || TARGET_64BIT
4288 || !TARGET_NEW_MNEMONICS)
b6c9286a
MM		 4289 abort ();
4290
7c59dc5d
MM		 4291 fprintf (file, "\t.ualong 0\n"); /* offset 0 */
4292 fprintf (file, "\t.ualong 0\n"); /* offset 4 */
4293 fprintf (file, "\t.ualong 0\n"); /* offset 8 */
4294 fprintf (file, "\t.ualong 0\n"); /* offset 12 */
4295 fprintf (file, "\t.ualong 0\n"); /* offset 16 */
8bd04c56 4296 fprintf (file, "..LTRAMP1..0:\n"); /* offset 20 */
7c59dc5d
MM		 4297 fprintf (file, "\tlwz %s,8(%s)\n", r0, r2); /* offset 24 */
4298 fprintf (file, "\tlwz %s,12(%s)\n", sc, r2); /* offset 28 */
4299 fprintf (file, "\tmtctr %s\n", r0); /* offset 32 */
4300 fprintf (file, "\tlwz %s,16(%s)\n", r2, r2); /* offset 36 */
4301 fprintf (file, "\tbctr\n"); /* offset 40 */
b6c9286a
MM		 4302 break;
4303 }
4304
4305 return;
4306}
4307
4308/* Length in units of the trampoline for entering a nested function. */
4309
4310int
4311rs6000_trampoline_size ()
4312{
4313 int ret = 0;
4314
4315 switch (DEFAULT_ABI)
4316 {
4317 default:
4318 abort ();
4319
4320 case ABI_AIX:
8f802bfb 4321 ret = (TARGET_32BIT) ? 12 : 24;
b6c9286a
MM		 4322 break;
4323
4324 case ABI_V4:
c81bebd7 4325 case ABI_SOLARIS:
b6c9286a 4326 case ABI_AIX_NODESC:
03a7e1a5 4327 ret = (TARGET_32BIT) ? 40 : 48;
b6c9286a
MM		 4328 break;
4329
4330 case ABI_NT:
7c59dc5d 4331 ret = 20;
b6c9286a
MM		 4332 break;
4333 }
4334
4335 return ret;
4336}
4337
4338/* Emit RTL insns to initialize the variable parts of a trampoline.
4339 FNADDR is an RTX for the address of the function's pure code.
4340 CXT is an RTX for the static chain value for the function. */
4341
4342void
4343rs6000_initialize_trampoline (addr, fnaddr, cxt)
4344 rtx addr;
4345 rtx fnaddr;
4346 rtx cxt;
4347{
ac2a93a1 4348 enum machine_mode pmode = Pmode;
8bd04c56
MM		 4349 int regsize = (TARGET_32BIT) ? 4 : 8;
4350 rtx ctx_reg = force_reg (pmode, cxt);
b6c9286a
MM		 4351
4352 switch (DEFAULT_ABI)
4353 {
4354 default:
4355 abort ();
4356
8bd04c56
MM		 4357/* Macros to shorten the code expansions below. */
4358#define MEM_DEREF(addr) gen_rtx (MEM, pmode, memory_address (pmode, addr))
7c59dc5d
MM		 4359#define MEM_PLUS(addr,offset) gen_rtx (MEM, pmode, memory_address (pmode, plus_constant (addr, offset)))
4360
b6c9286a
MM		 4361 /* Under AIX, just build the 3 word function descriptor */
4362 case ABI_AIX:
8bd04c56
MM		 4363 {
4364 rtx fn_reg = gen_reg_rtx (pmode);
4365 rtx toc_reg = gen_reg_rtx (pmode);
4366 emit_move_insn (fn_reg, MEM_DEREF (fnaddr));
4367 emit_move_insn (toc_reg, MEM_PLUS (fnaddr, 4));
4368 emit_move_insn (MEM_DEREF (addr), fn_reg);
4369 emit_move_insn (MEM_PLUS (addr, regsize), toc_reg);
4370 emit_move_insn (MEM_PLUS (addr, 2*regsize), ctx_reg);
4371 }
b6c9286a
MM		 4372 break;
4373
4374 /* Under V.4/eabi, update the two words after the bl to have the real
4375 function address and the static chain. */
4376 case ABI_V4:
c81bebd7 4377 case ABI_SOLARIS:
b6c9286a 4378 case ABI_AIX_NODESC:
8bd04c56
MM		 4379 {
4380 rtx reg = gen_reg_rtx (pmode);
4381 emit_move_insn (reg, fnaddr);
4382 emit_move_insn (MEM_PLUS (addr, 8), reg);
4383 emit_move_insn (MEM_PLUS (addr, 8 + regsize), ctx_reg);
4384 rs6000_sync_trampoline (addr);
4385 }
b6c9286a
MM		 4386 break;
4387
8bd04c56
MM		 4388 /* Under NT, update the first word to point to the ..LTRAMP1..0 header,
4389 the second word will point to the whole trampoline, third-fifth words
7c59dc5d 4390 will then have the real address, static chain, and toc value. */
b6c9286a 4391 case ABI_NT:
8bd04c56
MM		 4392 {
4393 rtx tramp_reg = gen_reg_rtx (pmode);
4394 rtx fn_reg = gen_reg_rtx (pmode);
4395 rtx toc_reg = gen_reg_rtx (pmode);
4396
4397 emit_move_insn (tramp_reg, gen_rtx (SYMBOL_REF, pmode, "..LTRAMP1..0"));
4398 addr = force_reg (pmode, addr);
4399 emit_move_insn (fn_reg, MEM_DEREF (fnaddr));
4400 emit_move_insn (toc_reg, MEM_PLUS (fnaddr, regsize));
4401 emit_move_insn (MEM_DEREF (addr), tramp_reg);
4402 emit_move_insn (MEM_PLUS (addr, regsize), addr);
4403 emit_move_insn (MEM_PLUS (addr, 2*regsize), fn_reg);
4404 emit_move_insn (MEM_PLUS (addr, 3*regsize), ctx_reg);
4405 emit_move_insn (MEM_PLUS (addr, 4*regsize), gen_rtx (REG, pmode, 2));
4406 }
b6c9286a
MM		 4407 break;
4408 }
4409
4410 return;
4411}
7509c759
MM		 4412
4413\f
4414/* If defined, a C expression whose value is nonzero if IDENTIFIER
4415 with arguments ARGS is a valid machine specific attribute for DECL.
4416 The attributes in ATTRIBUTES have previously been assigned to DECL. */
4417
4418int
4419rs6000_valid_decl_attribute_p (decl, attributes, identifier, args)
4420 tree decl;
4421 tree attributes;
4422 tree identifier;
4423 tree args;
4424{
4425 return 0;
4426}
4427
4428/* If defined, a C expression whose value is nonzero if IDENTIFIER
4429 with arguments ARGS is a valid machine specific attribute for TYPE.
4430 The attributes in ATTRIBUTES have previously been assigned to TYPE. */
4431
4432int
4433rs6000_valid_type_attribute_p (type, attributes, identifier, args)
4434 tree type;
4435 tree attributes;
4436 tree identifier;
4437 tree args;
4438{
4439 if (TREE_CODE (type) != FUNCTION_TYPE
4440 && TREE_CODE (type) != FIELD_DECL
4441 && TREE_CODE (type) != TYPE_DECL)
4442 return 0;
4443
6a4cee5f
MM		 4444 /* Longcall attribute says that the function is not within 2**26 bytes
4445 of the current function, and to do an indirect call. */
4446 if (is_attribute_p ("longcall", identifier))
4447 return (args == NULL_TREE);
4448
7509c759
MM		 4449 if (DEFAULT_ABI == ABI_NT)
4450 {
4451 /* Stdcall attribute says callee is responsible for popping arguments
4452 if they are not variable. */
4453 if (is_attribute_p ("stdcall", identifier))
4454 return (args == NULL_TREE);
4455
4456 /* Cdecl attribute says the callee is a normal C declaration */
4457 if (is_attribute_p ("cdecl", identifier))
4458 return (args == NULL_TREE);
4459
4460 /* Dllimport attribute says says the caller is to call the function
4461 indirectly through a __imp_<name> pointer. */
4462 if (is_attribute_p ("dllimport", identifier))
4463 return (args == NULL_TREE);
4464
4465 /* Dllexport attribute says says the callee is to create a __imp_<name>
4466 pointer. */
4467 if (is_attribute_p ("dllexport", identifier))
4468 return (args == NULL_TREE);
e56bb9ed
MM		 4469
4470 /* Exception attribute allows the user to specify 1-2 strings or identifiers
4471 that will fill in the 3rd and 4th fields of the structured exception
4472 table. */
4473 if (is_attribute_p ("exception", identifier))
4474 {
4475 int i;
4476
4477 if (args == NULL_TREE)
4478 return 0;
4479
4480 for (i = 0; i < 2 && args != NULL_TREE; i++)
4481 {
4482 tree this_arg = TREE_VALUE (args);
4483 args = TREE_PURPOSE (args);
4484
4485 if (TREE_CODE (this_arg) != STRING_CST
4486 && TREE_CODE (this_arg) != IDENTIFIER_NODE)
4487 return 0;
4488 }
4489
4490 return (args == NULL_TREE);
4491 }
7509c759
MM		 4492 }
4493
4494 return 0;
4495}
4496
4497/* If defined, a C expression whose value is zero if the attributes on
4498 TYPE1 and TYPE2 are incompatible, one if they are compatible, and
4499 two if they are nearly compatible (which causes a warning to be
4500 generated). */
4501
4502int
4503rs6000_comp_type_attributes (type1, type2)
4504 tree type1;
4505 tree type2;
4506{
4507 return 1;
4508}
4509
4510/* If defined, a C statement that assigns default attributes to newly
4511 defined TYPE. */
4512
4513void
4514rs6000_set_default_type_attributes (type)
4515 tree type;
4516{
4517}
4518
4519/* Return a dll import reference corresponding to to a call's SYMBOL_REF */
4520struct rtx_def *
4521rs6000_dll_import_ref (call_ref)
4522 rtx call_ref;
4523{
4524 char *call_name;
4525 int len;
4526 char *p;
4527 rtx reg1, reg2;
4528 tree node;
4529
4530 if (GET_CODE (call_ref) != SYMBOL_REF)
4531 abort ();
4532
4533 call_name = XSTR (call_ref, 0);
4534 len = sizeof ("__imp_") + strlen (call_name);
4535 p = alloca (len);
4536 reg2 = gen_reg_rtx (Pmode);
4537
4538 strcpy (p, "__imp_");
4539 strcat (p, call_name);
4540 node = get_identifier (p);
4541
4542 reg1 = force_reg (Pmode, gen_rtx (SYMBOL_REF, VOIDmode, IDENTIFIER_POINTER (node)));
4543 emit_move_insn (reg2, gen_rtx (MEM, Pmode, reg1));
4544
4545 return reg2;
4546}
4547
6a4cee5f
MM		 4548/* Return a reference suitable for calling a function with the longcall attribute. */
4549struct rtx_def *
4550rs6000_longcall_ref (call_ref)
4551 rtx call_ref;
4552{
4553 char *call_name;
4554 int len;
4555 char *p;
4556 rtx reg1, reg2;
4557 tree node;
4558
4559 if (GET_CODE (call_ref) != SYMBOL_REF)
4560 return call_ref;
4561
4562 /* System V adds '.' to the internal name, so skip them. */
4563 call_name = XSTR (call_ref, 0);
4564 if (*call_name == '.')
4565 {
4566 while (*call_name == '.')
4567 call_name++;
4568
4569 node = get_identifier (call_name);
4570 call_ref = gen_rtx (SYMBOL_REF, VOIDmode, IDENTIFIER_POINTER (node));
4571 }
4572
4573 return force_reg (Pmode, call_ref);
4574}
4575
7509c759
MM		 4576\f
4577/* A C statement or statements to switch to the appropriate section
4578 for output of RTX in mode MODE. You can assume that RTX is some
4579 kind of constant in RTL. The argument MODE is redundant except in
4580 the case of a `const_int' rtx. Select the section by calling
4581 `text_section' or one of the alternatives for other sections.
4582
4583 Do not define this macro if you put all constants in the read-only
4584 data section. */
4585
4586#ifdef USING_SVR4_H
4587
4588void
4589rs6000_select_rtx_section (mode, x)
4590 enum machine_mode mode;
4591 rtx x;
4592{
4593 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x))
4594 toc_section ();
7509c759
MM		 4595 else
4596 const_section ();
4597}
4598
4599/* A C statement or statements to switch to the appropriate
4600 section for output of DECL. DECL is either a `VAR_DECL' node
4601 or a constant of some sort. RELOC indicates whether forming
4602 the initial value of DECL requires link-time relocations. */
4603
4604void
4605rs6000_select_section (decl, reloc)
4606 tree decl;
4607 int reloc;
4608{
4609 int size = int_size_in_bytes (TREE_TYPE (decl));
4610
4611 if (TREE_CODE (decl) == STRING_CST)
4612 {
88228c4b 4613 if (! flag_writable_strings)
7509c759 4614 const_section ();
7509c759
MM		 4615 else
4616 data_section ();
4617 }
4618 else if (TREE_CODE (decl) == VAR_DECL)
4619 {
4620 if ((flag_pic && reloc)
4621 || !TREE_READONLY (decl)
4622 || TREE_SIDE_EFFECTS (decl)
4623 || !DECL_INITIAL (decl)
4624 || (DECL_INITIAL (decl) != error_mark_node
4625 && !TREE_CONSTANT (DECL_INITIAL (decl))))
4626 {
d9407988 4627 if (rs6000_sdata != SDATA_NONE && (size > 0) && (size <= g_switch_value))
7509c759
MM		 4628 sdata_section ();
4629 else
4630 data_section ();
4631 }
4632 else
4633 {
d9407988 4634 if (rs6000_sdata != SDATA_NONE && (size > 0) && (size <= g_switch_value))
c81bebd7 4635 {
d9407988 4636 if (rs6000_sdata == SDATA_EABI)
c81bebd7
MM		 4637 sdata2_section ();
4638 else
4639 sdata_section (); /* System V doesn't have .sdata2/.sbss2 */
4640 }
7509c759
MM		 4641 else
4642 const_section ();
4643 }
4644 }
4645 else
4646 const_section ();
4647}
d9407988
MM		 4648
4649\f
4650
4651/* If we are referencing a function that is static or is known to be
4652 in this file, make the SYMBOL_REF special. We can use this to indicate
4653 that we can branch to this function without emitting a no-op after the
4654 call. For real AIX and NT calling sequences, we also replace the
4655 function name with the real name (1 or 2 leading .'s), rather than
4656 the function descriptor name. This saves a lot of overriding code
4657 to readd the prefixes. */
4658
4659void
4660rs6000_encode_section_info (decl)
4661 tree decl;
4662{
4663 if (TREE_CODE (decl) == FUNCTION_DECL)
4664 {
4665 rtx sym_ref = XEXP (DECL_RTL (decl), 0);
4666 if (TREE_ASM_WRITTEN (decl) || ! TREE_PUBLIC (decl))
4667 SYMBOL_REF_FLAG (sym_ref) = 1;
4668
4669 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_NT)
4670 {
4671 char *prefix = (DEFAULT_ABI == ABI_AIX) ? "." : "..";
4672 char *str = permalloc (strlen (prefix) + 1
4673 + strlen (XSTR (sym_ref, 0)));
4674 strcpy (str, prefix);
4675 strcat (str, XSTR (sym_ref, 0));
4676 XSTR (sym_ref, 0) = str;
4677 }
4678 }
4679 else if (rs6000_sdata != SDATA_NONE
4680 && (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS)
4681 && TREE_CODE (decl) == VAR_DECL)
4682 {
4683 int size = int_size_in_bytes (TREE_TYPE (decl));
4684 tree section_name = DECL_SECTION_NAME (decl);
4685 char *name = (char *)0;
4686 int len = 0;
4687
4688 if (section_name)
4689 {
4690 if (TREE_CODE (section_name) == STRING_CST)
4691 {
4692 name = TREE_STRING_POINTER (section_name);
4693 len = TREE_STRING_LENGTH (section_name);
4694 }
4695 else
4696 abort ();
4697 }
4698
4699 if ((size > 0 && size <= g_switch_value)
4700 || (name
4701 && ((len == sizeof (".sdata")-1 && strcmp (name, ".sdata") == 0)
4702 || (len == sizeof (".sdata2")-1 && strcmp (name, ".sdata2") == 0)
4703 || (len == sizeof (".sbss")-1 && strcmp (name, ".sbss") == 0)
4704 || (len == sizeof (".sbss2")-1 && strcmp (name, ".sbss2") == 0)
4705 || (len == sizeof (".PPC.EMB.sdata0")-1 && strcmp (name, ".PPC.EMB.sdata0") == 0)
4706 || (len == sizeof (".PPC.EMB.sbss0")-1 && strcmp (name, ".PPC.EMB.sbss0") == 0))))
4707 {
4708 rtx sym_ref = XEXP (DECL_RTL (decl), 0);
4709 char *str = permalloc (2 + strlen (XSTR (sym_ref, 0)));
4710 strcpy (str, "@");
4711 strcat (str, XSTR (sym_ref, 0));
4712 XSTR (sym_ref, 0) = str;
4713 }
4714 }
4715}
4716
7509c759 4717#endif /* USING_SVR4_H */
ba5e43aa
MM		 4718
4719\f
4720/* CYGNUS LOCAL mac */
4721
4722/* Whether we are using m68k-compatible alignment. */
4723
4724int mac68k_aligned;
4725
4726/* Most Mac compiler pragmas are unimportant, but we must recognize
4727 the m68k alignment pragma, because that is crucial to transitions
4728 to and from the m68k emulator on PowerMacs. */
4729
4730int
4731handle_mac_pragma (finput, t)
4732 FILE *finput;
4733 tree t;
4734{
4735 int retval = 0;
4736 register char *pname;
4737 char pbuf[200];
4738 int c, psize;
4739
4740 if (TREE_CODE (t) != IDENTIFIER_NODE)
4741 return 0;
4742
4743 pname = IDENTIFIER_POINTER (t);
4744 if (strcmp (pname, "segment") == 0)
4745 {
ba5e43aa
MM		 4746 /* (should collect pbuf + 8 into a segment name) */
4747 }
4748 else if (strcmp (pname, "options") == 0)
4749 {
4750 c = getc (finput);
4751 /* Skip over initial whitespace. */
4752 while (c == ' ' || c == '\t')
4753 c = getc (finput);
4754
4755 /* Return without doing anything if no content. */
4756 if (c == '\n' || c == EOF)
802a0058
MM		 4757 {
4758 ungetc (c, finput);
4759 return 0;
4760 }
ba5e43aa
MM		 4761
4762 /* Collect the rest of the line. */
4763 while (psize < sizeof (pbuf) - 1 && c != '\n')
4764 {
4765 pbuf[psize++] = c;
4766 c = getc (finput);
4767 }
4768
4769 if (strncmp (pbuf, "align=mac68k", 12) == 0)
4770 {
802a0058
MM		 4771 mac68k_aligned = 1;
4772 retval = 1;
4773 }
4774 else if (strncmp (pbuf, "align=power", 11) == 0)
4775 {
4776 mac68k_aligned = 0;
4777 retval = 1;
ba5e43aa
MM		 4778 }
4779 else if (strncmp (pbuf, "align=reset", 11) == 0)
4780 {
802a0058
MM		 4781 mac68k_aligned = 0;
4782 retval = 1;
ba5e43aa
MM		 4783 }
4784 }
4785
802a0058 4786 return retval;
ba5e43aa
MM		 4787}
4788/* END CYGNUS LOCAL mac */
GNU Compiler Collection
This page took 0.856196 seconds and 5 git commands to generate.