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2c04f847 BS |
1 | /* Subroutines used to generate function prologues and epilogues |
2 | on IBM RS/6000. | |
7adcbafe | 3 | Copyright (C) 1991-2022 Free Software Foundation, Inc. |
2c04f847 BS |
4 | |
5 | This file is part of GCC. | |
6 | ||
7 | GCC is free software; you can redistribute it and/or modify it | |
8 | under the terms of the GNU General Public License as published | |
9 | by the Free Software Foundation; either version 3, or (at your | |
10 | option) any later version. | |
11 | ||
12 | GCC is distributed in the hope that it will be useful, but WITHOUT | |
13 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
14 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
15 | License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GCC; see the file COPYING3. If not see | |
19 | <http://www.gnu.org/licenses/>. */ | |
20 | ||
21 | #define IN_TARGET_CODE 1 | |
22 | ||
23 | #include "config.h" | |
24 | #include "system.h" | |
25 | #include "coretypes.h" | |
26 | #include "backend.h" | |
27 | #include "rtl.h" | |
28 | #include "tree.h" | |
29 | #include "memmodel.h" | |
30 | #include "df.h" | |
31 | #include "tm_p.h" | |
32 | #include "ira.h" | |
33 | #include "print-tree.h" | |
34 | #include "varasm.h" | |
35 | #include "explow.h" | |
36 | #include "expr.h" | |
37 | #include "output.h" | |
38 | #include "tree-pass.h" | |
39 | #include "rtx-vector-builder.h" | |
40 | #include "predict.h" | |
41 | #include "target.h" | |
42 | #include "stringpool.h" | |
43 | #include "attribs.h" | |
44 | #include "except.h" | |
45 | #include "langhooks.h" | |
46 | #include "optabs.h" | |
47 | #include "diagnostic-core.h" | |
2c04f847 BS |
48 | #include "alias.h" |
49 | #include "rs6000-internal.h" | |
9ff33839 IS |
50 | #if TARGET_MACHO |
51 | #include "gstab.h" /* for N_SLINE */ | |
52 | #include "dbxout.h" /* dbxout_ */ | |
53 | #endif | |
2c04f847 BS |
54 | |
55 | static int rs6000_ra_ever_killed (void); | |
56 | static void is_altivec_return_reg (rtx, void *); | |
57 | static bool rs6000_save_toc_in_prologue_p (void); | |
58 | ||
59 | static rs6000_stack_t stack_info; | |
60 | ||
f6955089 XL |
61 | /* Set if HARD_FRAM_POINTER_REGNUM is really needed. */ |
62 | static bool frame_pointer_needed_indeed = false; | |
2c04f847 BS |
63 | |
64 | /* Label number of label created for -mrelocatable, to call to so we can | |
65 | get the address of the GOT section */ | |
66 | int rs6000_pic_labelno = 0; | |
67 | ||
68 | ||
7cbb1b72 DE |
69 | #ifndef TARGET_PROFILE_KERNEL |
70 | #define TARGET_PROFILE_KERNEL 0 | |
71 | #endif | |
72 | ||
73 | ||
2c04f847 BS |
74 | /* Function to init struct machine_function. |
75 | This will be called, via a pointer variable, | |
76 | from push_function_context. */ | |
77 | ||
78 | struct machine_function * | |
79 | rs6000_init_machine_status (void) | |
80 | { | |
81 | stack_info.reload_completed = 0; | |
82 | return ggc_cleared_alloc<machine_function> (); | |
83 | } | |
84 | \f | |
85 | /* This page contains routines that are used to determine what the | |
86 | function prologue and epilogue code will do and write them out. */ | |
87 | ||
88 | /* Determine whether the REG is really used. */ | |
89 | ||
90 | bool | |
91 | save_reg_p (int reg) | |
92 | { | |
93 | if (reg == RS6000_PIC_OFFSET_TABLE_REGNUM && !TARGET_SINGLE_PIC_BASE) | |
94 | { | |
95 | /* When calling eh_return, we must return true for all the cases | |
96 | where conditional_register_usage marks the PIC offset reg | |
97 | call used or fixed. */ | |
98 | if (crtl->calls_eh_return | |
99 | && ((DEFAULT_ABI == ABI_V4 && flag_pic) | |
100 | || (DEFAULT_ABI == ABI_DARWIN && flag_pic) | |
101 | || (TARGET_TOC && TARGET_MINIMAL_TOC))) | |
102 | return true; | |
103 | ||
104 | /* We need to mark the PIC offset register live for the same | |
105 | conditions as it is set up in rs6000_emit_prologue, or | |
106 | otherwise it won't be saved before we clobber it. */ | |
107 | if (TARGET_TOC && TARGET_MINIMAL_TOC | |
108 | && !constant_pool_empty_p ()) | |
109 | return true; | |
110 | ||
111 | if (DEFAULT_ABI == ABI_V4 | |
112 | && (flag_pic == 1 || (flag_pic && TARGET_SECURE_PLT)) | |
113 | && df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM)) | |
114 | return true; | |
115 | ||
116 | if (DEFAULT_ABI == ABI_DARWIN | |
117 | && flag_pic && crtl->uses_pic_offset_table) | |
118 | return true; | |
119 | } | |
120 | ||
a365fa06 | 121 | return !call_used_or_fixed_reg_p (reg) && df_regs_ever_live_p (reg); |
2c04f847 BS |
122 | } |
123 | ||
124 | /* Return the first fixed-point register that is required to be | |
125 | saved. 32 if none. */ | |
126 | ||
127 | int | |
128 | first_reg_to_save (void) | |
129 | { | |
130 | int first_reg; | |
131 | ||
132 | /* Find lowest numbered live register. */ | |
133 | for (first_reg = 13; first_reg <= 31; first_reg++) | |
134 | if (save_reg_p (first_reg)) | |
135 | break; | |
136 | ||
137 | return first_reg; | |
138 | } | |
139 | ||
140 | /* Similar, for FP regs. */ | |
141 | ||
142 | int | |
143 | first_fp_reg_to_save (void) | |
144 | { | |
145 | int first_reg; | |
146 | ||
147 | /* Find lowest numbered live register. */ | |
148 | for (first_reg = 14 + 32; first_reg <= 63; first_reg++) | |
149 | if (save_reg_p (first_reg)) | |
150 | break; | |
151 | ||
152 | return first_reg; | |
153 | } | |
154 | ||
155 | /* Similar, for AltiVec regs. */ | |
156 | ||
157 | static int | |
158 | first_altivec_reg_to_save (void) | |
159 | { | |
160 | int i; | |
161 | ||
162 | /* Stack frame remains as is unless we are in AltiVec ABI. */ | |
163 | if (! TARGET_ALTIVEC_ABI) | |
164 | return LAST_ALTIVEC_REGNO + 1; | |
165 | ||
166 | /* On Darwin, the unwind routines are compiled without | |
167 | TARGET_ALTIVEC, and use save_world to save/restore the | |
168 | altivec registers when necessary. */ | |
169 | if (DEFAULT_ABI == ABI_DARWIN && crtl->calls_eh_return | |
170 | && ! TARGET_ALTIVEC) | |
171 | return FIRST_ALTIVEC_REGNO + 20; | |
172 | ||
173 | /* Find lowest numbered live register. */ | |
174 | for (i = FIRST_ALTIVEC_REGNO + 20; i <= LAST_ALTIVEC_REGNO; ++i) | |
175 | if (save_reg_p (i)) | |
176 | break; | |
177 | ||
178 | return i; | |
179 | } | |
180 | ||
181 | /* Return a 32-bit mask of the AltiVec registers we need to set in | |
182 | VRSAVE. Bit n of the return value is 1 if Vn is live. The MSB in | |
183 | the 32-bit word is 0. */ | |
184 | ||
185 | static unsigned int | |
186 | compute_vrsave_mask (void) | |
187 | { | |
188 | unsigned int i, mask = 0; | |
189 | ||
190 | /* On Darwin, the unwind routines are compiled without | |
191 | TARGET_ALTIVEC, and use save_world to save/restore the | |
192 | call-saved altivec registers when necessary. */ | |
193 | if (DEFAULT_ABI == ABI_DARWIN && crtl->calls_eh_return | |
194 | && ! TARGET_ALTIVEC) | |
195 | mask |= 0xFFF; | |
196 | ||
197 | /* First, find out if we use _any_ altivec registers. */ | |
198 | for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i) | |
199 | if (df_regs_ever_live_p (i)) | |
200 | mask |= ALTIVEC_REG_BIT (i); | |
201 | ||
202 | if (mask == 0) | |
203 | return mask; | |
204 | ||
205 | /* Next, remove the argument registers from the set. These must | |
206 | be in the VRSAVE mask set by the caller, so we don't need to add | |
207 | them in again. More importantly, the mask we compute here is | |
208 | used to generate CLOBBERs in the set_vrsave insn, and we do not | |
209 | wish the argument registers to die. */ | |
210 | for (i = ALTIVEC_ARG_MIN_REG; i < (unsigned) crtl->args.info.vregno; i++) | |
211 | mask &= ~ALTIVEC_REG_BIT (i); | |
212 | ||
213 | /* Similarly, remove the return value from the set. */ | |
214 | { | |
215 | bool yes = false; | |
216 | diddle_return_value (is_altivec_return_reg, &yes); | |
217 | if (yes) | |
218 | mask &= ~ALTIVEC_REG_BIT (ALTIVEC_ARG_RETURN); | |
219 | } | |
220 | ||
221 | return mask; | |
222 | } | |
223 | ||
224 | /* For a very restricted set of circumstances, we can cut down the | |
225 | size of prologues/epilogues by calling our own save/restore-the-world | |
226 | routines. */ | |
227 | ||
228 | static void | |
229 | compute_save_world_info (rs6000_stack_t *info) | |
230 | { | |
231 | info->world_save_p = 1; | |
232 | info->world_save_p | |
233 | = (WORLD_SAVE_P (info) | |
234 | && DEFAULT_ABI == ABI_DARWIN | |
235 | && !cfun->has_nonlocal_label | |
236 | && info->first_fp_reg_save == FIRST_SAVED_FP_REGNO | |
237 | && info->first_gp_reg_save == FIRST_SAVED_GP_REGNO | |
238 | && info->first_altivec_reg_save == FIRST_SAVED_ALTIVEC_REGNO | |
239 | && info->cr_save_p); | |
240 | ||
241 | /* This will not work in conjunction with sibcalls. Make sure there | |
242 | are none. (This check is expensive, but seldom executed.) */ | |
243 | if (WORLD_SAVE_P (info)) | |
244 | { | |
245 | rtx_insn *insn; | |
246 | for (insn = get_last_insn_anywhere (); insn; insn = PREV_INSN (insn)) | |
247 | if (CALL_P (insn) && SIBLING_CALL_P (insn)) | |
248 | { | |
249 | info->world_save_p = 0; | |
250 | break; | |
251 | } | |
252 | } | |
253 | ||
254 | if (WORLD_SAVE_P (info)) | |
255 | { | |
256 | /* Even if we're not touching VRsave, make sure there's room on the | |
257 | stack for it, if it looks like we're calling SAVE_WORLD, which | |
258 | will attempt to save it. */ | |
259 | info->vrsave_size = 4; | |
260 | ||
261 | /* If we are going to save the world, we need to save the link register too. */ | |
262 | info->lr_save_p = 1; | |
263 | ||
264 | /* "Save" the VRsave register too if we're saving the world. */ | |
265 | if (info->vrsave_mask == 0) | |
266 | info->vrsave_mask = compute_vrsave_mask (); | |
267 | ||
268 | /* Because the Darwin register save/restore routines only handle | |
269 | F14 .. F31 and V20 .. V31 as per the ABI, perform a consistency | |
270 | check. */ | |
271 | gcc_assert (info->first_fp_reg_save >= FIRST_SAVED_FP_REGNO | |
272 | && (info->first_altivec_reg_save | |
273 | >= FIRST_SAVED_ALTIVEC_REGNO)); | |
274 | } | |
275 | ||
276 | return; | |
277 | } | |
278 | ||
279 | ||
280 | static void | |
281 | is_altivec_return_reg (rtx reg, void *xyes) | |
282 | { | |
283 | bool *yes = (bool *) xyes; | |
284 | if (REGNO (reg) == ALTIVEC_ARG_RETURN) | |
285 | *yes = true; | |
286 | } | |
287 | ||
288 | \f | |
289 | /* Return whether REG is a global user reg or has been specifed by | |
290 | -ffixed-REG. We should not restore these, and so cannot use | |
291 | lmw or out-of-line restore functions if there are any. We also | |
292 | can't save them (well, emit frame notes for them), because frame | |
293 | unwinding during exception handling will restore saved registers. */ | |
294 | ||
295 | static bool | |
296 | fixed_reg_p (int reg) | |
297 | { | |
298 | /* Ignore fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] when the | |
299 | backend sets it, overriding anything the user might have given. */ | |
300 | if (reg == RS6000_PIC_OFFSET_TABLE_REGNUM | |
301 | && ((DEFAULT_ABI == ABI_V4 && flag_pic) | |
302 | || (DEFAULT_ABI == ABI_DARWIN && flag_pic) | |
303 | || (TARGET_TOC && TARGET_MINIMAL_TOC))) | |
304 | return false; | |
305 | ||
306 | return fixed_regs[reg]; | |
307 | } | |
308 | ||
309 | /* Determine the strategy for savings/restoring registers. */ | |
310 | ||
311 | enum { | |
312 | SAVE_MULTIPLE = 0x1, | |
313 | SAVE_INLINE_GPRS = 0x2, | |
314 | SAVE_INLINE_FPRS = 0x4, | |
315 | SAVE_NOINLINE_GPRS_SAVES_LR = 0x8, | |
316 | SAVE_NOINLINE_FPRS_SAVES_LR = 0x10, | |
317 | SAVE_INLINE_VRS = 0x20, | |
318 | REST_MULTIPLE = 0x100, | |
319 | REST_INLINE_GPRS = 0x200, | |
320 | REST_INLINE_FPRS = 0x400, | |
321 | REST_NOINLINE_FPRS_DOESNT_RESTORE_LR = 0x800, | |
322 | REST_INLINE_VRS = 0x1000 | |
323 | }; | |
324 | ||
325 | static int | |
326 | rs6000_savres_strategy (rs6000_stack_t *info, | |
327 | bool using_static_chain_p) | |
328 | { | |
329 | int strategy = 0; | |
330 | ||
331 | /* Select between in-line and out-of-line save and restore of regs. | |
332 | First, all the obvious cases where we don't use out-of-line. */ | |
333 | if (crtl->calls_eh_return | |
334 | || cfun->machine->ra_need_lr) | |
335 | strategy |= (SAVE_INLINE_FPRS | REST_INLINE_FPRS | |
336 | | SAVE_INLINE_GPRS | REST_INLINE_GPRS | |
337 | | SAVE_INLINE_VRS | REST_INLINE_VRS); | |
338 | ||
339 | if (info->first_gp_reg_save == 32) | |
340 | strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS; | |
341 | ||
342 | if (info->first_fp_reg_save == 64) | |
343 | strategy |= SAVE_INLINE_FPRS | REST_INLINE_FPRS; | |
344 | ||
345 | if (info->first_altivec_reg_save == LAST_ALTIVEC_REGNO + 1) | |
346 | strategy |= SAVE_INLINE_VRS | REST_INLINE_VRS; | |
347 | ||
348 | /* Define cutoff for using out-of-line functions to save registers. */ | |
349 | if (DEFAULT_ABI == ABI_V4 || TARGET_ELF) | |
350 | { | |
351 | if (!optimize_size) | |
352 | { | |
353 | strategy |= SAVE_INLINE_FPRS | REST_INLINE_FPRS; | |
354 | strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS; | |
355 | strategy |= SAVE_INLINE_VRS | REST_INLINE_VRS; | |
356 | } | |
357 | else | |
358 | { | |
359 | /* Prefer out-of-line restore if it will exit. */ | |
360 | if (info->first_fp_reg_save > 61) | |
361 | strategy |= SAVE_INLINE_FPRS; | |
362 | if (info->first_gp_reg_save > 29) | |
363 | { | |
364 | if (info->first_fp_reg_save == 64) | |
365 | strategy |= SAVE_INLINE_GPRS; | |
366 | else | |
367 | strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS; | |
368 | } | |
369 | if (info->first_altivec_reg_save == LAST_ALTIVEC_REGNO) | |
370 | strategy |= SAVE_INLINE_VRS | REST_INLINE_VRS; | |
371 | } | |
372 | } | |
373 | else if (DEFAULT_ABI == ABI_DARWIN) | |
374 | { | |
375 | if (info->first_fp_reg_save > 60) | |
376 | strategy |= SAVE_INLINE_FPRS | REST_INLINE_FPRS; | |
377 | if (info->first_gp_reg_save > 29) | |
378 | strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS; | |
379 | strategy |= SAVE_INLINE_VRS | REST_INLINE_VRS; | |
380 | } | |
381 | else | |
382 | { | |
383 | gcc_checking_assert (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2); | |
384 | if ((flag_shrink_wrap_separate && optimize_function_for_speed_p (cfun)) | |
385 | || info->first_fp_reg_save > 61) | |
386 | strategy |= SAVE_INLINE_FPRS | REST_INLINE_FPRS; | |
387 | strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS; | |
388 | strategy |= SAVE_INLINE_VRS | REST_INLINE_VRS; | |
389 | } | |
390 | ||
391 | /* Don't bother to try to save things out-of-line if r11 is occupied | |
392 | by the static chain. It would require too much fiddling and the | |
393 | static chain is rarely used anyway. FPRs are saved w.r.t the stack | |
394 | pointer on Darwin, and AIX uses r1 or r12. */ | |
395 | if (using_static_chain_p | |
396 | && (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_DARWIN)) | |
397 | strategy |= ((DEFAULT_ABI == ABI_DARWIN ? 0 : SAVE_INLINE_FPRS) | |
398 | | SAVE_INLINE_GPRS | |
399 | | SAVE_INLINE_VRS); | |
400 | ||
401 | /* Don't ever restore fixed regs. That means we can't use the | |
402 | out-of-line register restore functions if a fixed reg is in the | |
403 | range of regs restored. */ | |
404 | if (!(strategy & REST_INLINE_FPRS)) | |
405 | for (int i = info->first_fp_reg_save; i < 64; i++) | |
406 | if (fixed_regs[i]) | |
407 | { | |
408 | strategy |= REST_INLINE_FPRS; | |
409 | break; | |
410 | } | |
411 | ||
412 | /* We can only use the out-of-line routines to restore fprs if we've | |
413 | saved all the registers from first_fp_reg_save in the prologue. | |
414 | Otherwise, we risk loading garbage. Of course, if we have saved | |
415 | out-of-line then we know we haven't skipped any fprs. */ | |
416 | if ((strategy & SAVE_INLINE_FPRS) | |
417 | && !(strategy & REST_INLINE_FPRS)) | |
418 | for (int i = info->first_fp_reg_save; i < 64; i++) | |
419 | if (!save_reg_p (i)) | |
420 | { | |
421 | strategy |= REST_INLINE_FPRS; | |
422 | break; | |
423 | } | |
424 | ||
425 | /* Similarly, for altivec regs. */ | |
426 | if (!(strategy & REST_INLINE_VRS)) | |
427 | for (int i = info->first_altivec_reg_save; i < LAST_ALTIVEC_REGNO + 1; i++) | |
428 | if (fixed_regs[i]) | |
429 | { | |
430 | strategy |= REST_INLINE_VRS; | |
431 | break; | |
432 | } | |
433 | ||
434 | if ((strategy & SAVE_INLINE_VRS) | |
435 | && !(strategy & REST_INLINE_VRS)) | |
436 | for (int i = info->first_altivec_reg_save; i < LAST_ALTIVEC_REGNO + 1; i++) | |
437 | if (!save_reg_p (i)) | |
438 | { | |
439 | strategy |= REST_INLINE_VRS; | |
440 | break; | |
441 | } | |
442 | ||
443 | /* info->lr_save_p isn't yet set if the only reason lr needs to be | |
444 | saved is an out-of-line save or restore. Set up the value for | |
445 | the next test (excluding out-of-line gprs). */ | |
446 | bool lr_save_p = (info->lr_save_p | |
447 | || !(strategy & SAVE_INLINE_FPRS) | |
448 | || !(strategy & SAVE_INLINE_VRS) | |
449 | || !(strategy & REST_INLINE_FPRS) | |
450 | || !(strategy & REST_INLINE_VRS)); | |
451 | ||
452 | if (TARGET_MULTIPLE | |
453 | && !TARGET_POWERPC64 | |
454 | && info->first_gp_reg_save < 31 | |
455 | && !(flag_shrink_wrap | |
456 | && flag_shrink_wrap_separate | |
457 | && optimize_function_for_speed_p (cfun))) | |
458 | { | |
459 | int count = 0; | |
460 | for (int i = info->first_gp_reg_save; i < 32; i++) | |
461 | if (save_reg_p (i)) | |
462 | count++; | |
463 | ||
464 | if (count <= 1) | |
465 | /* Don't use store multiple if only one reg needs to be | |
466 | saved. This can occur for example when the ABI_V4 pic reg | |
467 | (r30) needs to be saved to make calls, but r31 is not | |
468 | used. */ | |
469 | strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS; | |
470 | else | |
471 | { | |
472 | /* Prefer store multiple for saves over out-of-line | |
473 | routines, since the store-multiple instruction will | |
474 | always be smaller. */ | |
475 | strategy |= SAVE_INLINE_GPRS | SAVE_MULTIPLE; | |
476 | ||
477 | /* The situation is more complicated with load multiple. | |
478 | We'd prefer to use the out-of-line routines for restores, | |
479 | since the "exit" out-of-line routines can handle the | |
480 | restore of LR and the frame teardown. However if doesn't | |
481 | make sense to use the out-of-line routine if that is the | |
482 | only reason we'd need to save LR, and we can't use the | |
483 | "exit" out-of-line gpr restore if we have saved some | |
484 | fprs; In those cases it is advantageous to use load | |
485 | multiple when available. */ | |
486 | if (info->first_fp_reg_save != 64 || !lr_save_p) | |
487 | strategy |= REST_INLINE_GPRS | REST_MULTIPLE; | |
488 | } | |
489 | } | |
490 | ||
491 | /* Using the "exit" out-of-line routine does not improve code size | |
492 | if using it would require lr to be saved and if only saving one | |
493 | or two gprs. */ | |
494 | else if (!lr_save_p && info->first_gp_reg_save > 29) | |
495 | strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS; | |
496 | ||
497 | /* Don't ever restore fixed regs. */ | |
498 | if ((strategy & (REST_INLINE_GPRS | REST_MULTIPLE)) != REST_INLINE_GPRS) | |
499 | for (int i = info->first_gp_reg_save; i < 32; i++) | |
500 | if (fixed_reg_p (i)) | |
501 | { | |
502 | strategy |= REST_INLINE_GPRS; | |
503 | strategy &= ~REST_MULTIPLE; | |
504 | break; | |
505 | } | |
506 | ||
507 | /* We can only use load multiple or the out-of-line routines to | |
508 | restore gprs if we've saved all the registers from | |
509 | first_gp_reg_save. Otherwise, we risk loading garbage. | |
510 | Of course, if we have saved out-of-line or used stmw then we know | |
511 | we haven't skipped any gprs. */ | |
512 | if ((strategy & (SAVE_INLINE_GPRS | SAVE_MULTIPLE)) == SAVE_INLINE_GPRS | |
513 | && (strategy & (REST_INLINE_GPRS | REST_MULTIPLE)) != REST_INLINE_GPRS) | |
514 | for (int i = info->first_gp_reg_save; i < 32; i++) | |
515 | if (!save_reg_p (i)) | |
516 | { | |
517 | strategy |= REST_INLINE_GPRS; | |
518 | strategy &= ~REST_MULTIPLE; | |
519 | break; | |
520 | } | |
521 | ||
522 | if (TARGET_ELF && TARGET_64BIT) | |
523 | { | |
524 | if (!(strategy & SAVE_INLINE_FPRS)) | |
525 | strategy |= SAVE_NOINLINE_FPRS_SAVES_LR; | |
526 | else if (!(strategy & SAVE_INLINE_GPRS) | |
527 | && info->first_fp_reg_save == 64) | |
528 | strategy |= SAVE_NOINLINE_GPRS_SAVES_LR; | |
529 | } | |
530 | else if (TARGET_AIX && !(strategy & REST_INLINE_FPRS)) | |
531 | strategy |= REST_NOINLINE_FPRS_DOESNT_RESTORE_LR; | |
532 | ||
533 | if (TARGET_MACHO && !(strategy & SAVE_INLINE_FPRS)) | |
534 | strategy |= SAVE_NOINLINE_FPRS_SAVES_LR; | |
535 | ||
536 | return strategy; | |
537 | } | |
538 | ||
539 | /* Calculate the stack information for the current function. This is | |
540 | complicated by having two separate calling sequences, the AIX calling | |
541 | sequence and the V.4 calling sequence. | |
542 | ||
543 | AIX (and Darwin/Mac OS X) stack frames look like: | |
544 | 32-bit 64-bit | |
545 | SP----> +---------------------------------------+ | |
546 | | back chain to caller | 0 0 | |
547 | +---------------------------------------+ | |
548 | | saved CR | 4 8 (8-11) | |
549 | +---------------------------------------+ | |
550 | | saved LR | 8 16 | |
551 | +---------------------------------------+ | |
552 | | reserved for compilers | 12 24 | |
553 | +---------------------------------------+ | |
554 | | reserved for binders | 16 32 | |
555 | +---------------------------------------+ | |
556 | | saved TOC pointer | 20 40 | |
557 | +---------------------------------------+ | |
558 | | Parameter save area (+padding*) (P) | 24 48 | |
559 | +---------------------------------------+ | |
560 | | Alloca space (A) | 24+P etc. | |
561 | +---------------------------------------+ | |
562 | | Local variable space (L) | 24+P+A | |
563 | +---------------------------------------+ | |
564 | | Float/int conversion temporary (X) | 24+P+A+L | |
565 | +---------------------------------------+ | |
566 | | Save area for AltiVec registers (W) | 24+P+A+L+X | |
567 | +---------------------------------------+ | |
568 | | AltiVec alignment padding (Y) | 24+P+A+L+X+W | |
569 | +---------------------------------------+ | |
570 | | Save area for VRSAVE register (Z) | 24+P+A+L+X+W+Y | |
571 | +---------------------------------------+ | |
572 | | Save area for GP registers (G) | 24+P+A+X+L+X+W+Y+Z | |
573 | +---------------------------------------+ | |
574 | | Save area for FP registers (F) | 24+P+A+X+L+X+W+Y+Z+G | |
575 | +---------------------------------------+ | |
576 | old SP->| back chain to caller's caller | | |
577 | +---------------------------------------+ | |
578 | ||
579 | * If the alloca area is present, the parameter save area is | |
580 | padded so that the former starts 16-byte aligned. | |
581 | ||
582 | The required alignment for AIX configurations is two words (i.e., 8 | |
583 | or 16 bytes). | |
584 | ||
585 | The ELFv2 ABI is a variant of the AIX ABI. Stack frames look like: | |
586 | ||
587 | SP----> +---------------------------------------+ | |
588 | | Back chain to caller | 0 | |
589 | +---------------------------------------+ | |
590 | | Save area for CR | 8 | |
591 | +---------------------------------------+ | |
592 | | Saved LR | 16 | |
593 | +---------------------------------------+ | |
594 | | Saved TOC pointer | 24 | |
595 | +---------------------------------------+ | |
596 | | Parameter save area (+padding*) (P) | 32 | |
597 | +---------------------------------------+ | |
af979a98 | 598 | | Optional ROP hash slot (R) | 32+P |
2c04f847 | 599 | +---------------------------------------+ |
af979a98 | 600 | | Alloca space (A) | 32+P+R |
2c04f847 | 601 | +---------------------------------------+ |
af979a98 | 602 | | Local variable space (L) | 32+P+R+A |
2c04f847 | 603 | +---------------------------------------+ |
af979a98 | 604 | | Save area for AltiVec registers (W) | 32+P+R+A+L |
2c04f847 | 605 | +---------------------------------------+ |
af979a98 | 606 | | AltiVec alignment padding (Y) | 32+P+R+A+L+W |
2c04f847 | 607 | +---------------------------------------+ |
af979a98 | 608 | | Save area for GP registers (G) | 32+P+R+A+L+W+Y |
2c04f847 | 609 | +---------------------------------------+ |
af979a98 BS |
610 | | Save area for FP registers (F) | 32+P+R+A+L+W+Y+G |
611 | +---------------------------------------+ | |
612 | old SP->| back chain to caller's caller | 32+P+R+A+L+W+Y+G+F | |
2c04f847 BS |
613 | +---------------------------------------+ |
614 | ||
615 | * If the alloca area is present, the parameter save area is | |
616 | padded so that the former starts 16-byte aligned. | |
617 | ||
618 | V.4 stack frames look like: | |
619 | ||
620 | SP----> +---------------------------------------+ | |
621 | | back chain to caller | 0 | |
622 | +---------------------------------------+ | |
623 | | caller's saved LR | 4 | |
624 | +---------------------------------------+ | |
625 | | Parameter save area (+padding*) (P) | 8 | |
626 | +---------------------------------------+ | |
627 | | Alloca space (A) | 8+P | |
628 | +---------------------------------------+ | |
629 | | Varargs save area (V) | 8+P+A | |
630 | +---------------------------------------+ | |
631 | | Local variable space (L) | 8+P+A+V | |
632 | +---------------------------------------+ | |
633 | | Float/int conversion temporary (X) | 8+P+A+V+L | |
634 | +---------------------------------------+ | |
635 | | Save area for AltiVec registers (W) | 8+P+A+V+L+X | |
636 | +---------------------------------------+ | |
637 | | AltiVec alignment padding (Y) | 8+P+A+V+L+X+W | |
638 | +---------------------------------------+ | |
639 | | Save area for VRSAVE register (Z) | 8+P+A+V+L+X+W+Y | |
640 | +---------------------------------------+ | |
641 | | saved CR (C) | 8+P+A+V+L+X+W+Y+Z | |
642 | +---------------------------------------+ | |
643 | | Save area for GP registers (G) | 8+P+A+V+L+X+W+Y+Z+C | |
644 | +---------------------------------------+ | |
645 | | Save area for FP registers (F) | 8+P+A+V+L+X+W+Y+Z+C+G | |
646 | +---------------------------------------+ | |
647 | old SP->| back chain to caller's caller | | |
648 | +---------------------------------------+ | |
649 | ||
650 | * If the alloca area is present and the required alignment is | |
651 | 16 bytes, the parameter save area is padded so that the | |
652 | alloca area starts 16-byte aligned. | |
653 | ||
654 | The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is | |
655 | given. (But note below and in sysv4.h that we require only 8 and | |
656 | may round up the size of our stack frame anyways. The historical | |
657 | reason is early versions of powerpc-linux which didn't properly | |
658 | align the stack at program startup. A happy side-effect is that | |
659 | -mno-eabi libraries can be used with -meabi programs.) | |
660 | ||
661 | The EABI configuration defaults to the V.4 layout. However, | |
662 | the stack alignment requirements may differ. If -mno-eabi is not | |
663 | given, the required stack alignment is 8 bytes; if -mno-eabi is | |
664 | given, the required alignment is 16 bytes. (But see V.4 comment | |
665 | above.) */ | |
666 | ||
667 | #ifndef ABI_STACK_BOUNDARY | |
668 | #define ABI_STACK_BOUNDARY STACK_BOUNDARY | |
669 | #endif | |
670 | ||
671 | rs6000_stack_t * | |
672 | rs6000_stack_info (void) | |
673 | { | |
674 | /* We should never be called for thunks, we are not set up for that. */ | |
675 | gcc_assert (!cfun->is_thunk); | |
676 | ||
677 | rs6000_stack_t *info = &stack_info; | |
678 | int reg_size = TARGET_32BIT ? 4 : 8; | |
679 | int ehrd_size; | |
680 | int ehcr_size; | |
681 | int save_align; | |
682 | int first_gp; | |
683 | HOST_WIDE_INT non_fixed_size; | |
684 | bool using_static_chain_p; | |
685 | ||
686 | if (reload_completed && info->reload_completed) | |
687 | return info; | |
688 | ||
689 | memset (info, 0, sizeof (*info)); | |
690 | info->reload_completed = reload_completed; | |
691 | ||
692 | /* Select which calling sequence. */ | |
693 | info->abi = DEFAULT_ABI; | |
694 | ||
695 | /* Calculate which registers need to be saved & save area size. */ | |
696 | info->first_gp_reg_save = first_reg_to_save (); | |
697 | /* Assume that we will have to save RS6000_PIC_OFFSET_TABLE_REGNUM, | |
698 | even if it currently looks like we won't. Reload may need it to | |
699 | get at a constant; if so, it will have already created a constant | |
700 | pool entry for it. */ | |
701 | if (((TARGET_TOC && TARGET_MINIMAL_TOC) | |
702 | || (flag_pic == 1 && DEFAULT_ABI == ABI_V4) | |
703 | || (flag_pic && DEFAULT_ABI == ABI_DARWIN)) | |
704 | && crtl->uses_const_pool | |
705 | && info->first_gp_reg_save > RS6000_PIC_OFFSET_TABLE_REGNUM) | |
706 | first_gp = RS6000_PIC_OFFSET_TABLE_REGNUM; | |
707 | else | |
708 | first_gp = info->first_gp_reg_save; | |
709 | ||
710 | info->gp_size = reg_size * (32 - first_gp); | |
711 | ||
712 | info->first_fp_reg_save = first_fp_reg_to_save (); | |
713 | info->fp_size = 8 * (64 - info->first_fp_reg_save); | |
714 | ||
715 | info->first_altivec_reg_save = first_altivec_reg_to_save (); | |
716 | info->altivec_size = 16 * (LAST_ALTIVEC_REGNO + 1 | |
717 | - info->first_altivec_reg_save); | |
718 | ||
199baa71 | 719 | /* Does this function call anything (apart from sibling calls)? */ |
2c04f847 | 720 | info->calls_p = (!crtl->is_leaf || cfun->machine->ra_needs_full_frame); |
af979a98 BS |
721 | info->rop_hash_size = 0; |
722 | ||
723 | if (TARGET_POWER10 | |
724 | && info->calls_p | |
725 | && DEFAULT_ABI == ABI_ELFv2 | |
726 | && rs6000_rop_protect) | |
727 | info->rop_hash_size = 8; | |
728 | else if (rs6000_rop_protect && DEFAULT_ABI != ABI_ELFv2) | |
729 | { | |
730 | /* We can't check this in rs6000_option_override_internal since | |
731 | DEFAULT_ABI isn't established yet. */ | |
732 | error ("%qs requires the ELFv2 ABI", "-mrop-protect"); | |
733 | } | |
2c04f847 BS |
734 | |
735 | /* Determine if we need to save the condition code registers. */ | |
736 | if (save_reg_p (CR2_REGNO) | |
737 | || save_reg_p (CR3_REGNO) | |
738 | || save_reg_p (CR4_REGNO)) | |
739 | { | |
740 | info->cr_save_p = 1; | |
741 | if (DEFAULT_ABI == ABI_V4) | |
742 | info->cr_size = reg_size; | |
743 | } | |
744 | ||
745 | /* If the current function calls __builtin_eh_return, then we need | |
746 | to allocate stack space for registers that will hold data for | |
747 | the exception handler. */ | |
748 | if (crtl->calls_eh_return) | |
749 | { | |
750 | unsigned int i; | |
751 | for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i) | |
752 | continue; | |
753 | ||
754 | ehrd_size = i * UNITS_PER_WORD; | |
755 | } | |
756 | else | |
757 | ehrd_size = 0; | |
758 | ||
759 | /* In the ELFv2 ABI, we also need to allocate space for separate | |
760 | CR field save areas if the function calls __builtin_eh_return. */ | |
761 | if (DEFAULT_ABI == ABI_ELFv2 && crtl->calls_eh_return) | |
762 | { | |
763 | /* This hard-codes that we have three call-saved CR fields. */ | |
764 | ehcr_size = 3 * reg_size; | |
765 | /* We do *not* use the regular CR save mechanism. */ | |
766 | info->cr_save_p = 0; | |
767 | } | |
768 | else | |
769 | ehcr_size = 0; | |
770 | ||
771 | /* Determine various sizes. */ | |
772 | info->reg_size = reg_size; | |
773 | info->fixed_size = RS6000_SAVE_AREA; | |
774 | info->vars_size = RS6000_ALIGN (get_frame_size (), 8); | |
775 | if (cfun->calls_alloca) | |
776 | info->parm_size = | |
777 | RS6000_ALIGN (crtl->outgoing_args_size + info->fixed_size, | |
778 | STACK_BOUNDARY / BITS_PER_UNIT) - info->fixed_size; | |
779 | else | |
780 | info->parm_size = RS6000_ALIGN (crtl->outgoing_args_size, | |
781 | TARGET_ALTIVEC ? 16 : 8); | |
782 | if (FRAME_GROWS_DOWNWARD) | |
783 | info->vars_size | |
784 | += RS6000_ALIGN (info->fixed_size + info->vars_size + info->parm_size, | |
785 | ABI_STACK_BOUNDARY / BITS_PER_UNIT) | |
786 | - (info->fixed_size + info->vars_size + info->parm_size); | |
787 | ||
788 | if (TARGET_ALTIVEC_ABI) | |
789 | info->vrsave_mask = compute_vrsave_mask (); | |
790 | ||
791 | if (TARGET_ALTIVEC_VRSAVE && info->vrsave_mask) | |
792 | info->vrsave_size = 4; | |
793 | ||
794 | compute_save_world_info (info); | |
795 | ||
796 | /* Calculate the offsets. */ | |
797 | switch (DEFAULT_ABI) | |
798 | { | |
799 | case ABI_NONE: | |
800 | default: | |
801 | gcc_unreachable (); | |
802 | ||
803 | case ABI_AIX: | |
804 | case ABI_ELFv2: | |
805 | case ABI_DARWIN: | |
806 | info->fp_save_offset = -info->fp_size; | |
807 | info->gp_save_offset = info->fp_save_offset - info->gp_size; | |
808 | ||
809 | if (TARGET_ALTIVEC_ABI) | |
810 | { | |
811 | info->vrsave_save_offset = info->gp_save_offset - info->vrsave_size; | |
812 | ||
813 | /* Align stack so vector save area is on a quadword boundary. | |
814 | The padding goes above the vectors. */ | |
815 | if (info->altivec_size != 0) | |
816 | info->altivec_padding_size = info->vrsave_save_offset & 0xF; | |
817 | ||
818 | info->altivec_save_offset = info->vrsave_save_offset | |
819 | - info->altivec_padding_size | |
820 | - info->altivec_size; | |
821 | gcc_assert (info->altivec_size == 0 | |
822 | || info->altivec_save_offset % 16 == 0); | |
823 | ||
824 | /* Adjust for AltiVec case. */ | |
825 | info->ehrd_offset = info->altivec_save_offset - ehrd_size; | |
af979a98 BS |
826 | |
827 | /* Adjust for ROP protection. */ | |
828 | info->rop_hash_save_offset | |
829 | = info->altivec_save_offset - info->rop_hash_size; | |
830 | info->ehrd_offset -= info->rop_hash_size; | |
2c04f847 BS |
831 | } |
832 | else | |
833 | info->ehrd_offset = info->gp_save_offset - ehrd_size; | |
834 | ||
835 | info->ehcr_offset = info->ehrd_offset - ehcr_size; | |
836 | info->cr_save_offset = reg_size; /* first word when 64-bit. */ | |
837 | info->lr_save_offset = 2*reg_size; | |
838 | break; | |
839 | ||
840 | case ABI_V4: | |
841 | info->fp_save_offset = -info->fp_size; | |
842 | info->gp_save_offset = info->fp_save_offset - info->gp_size; | |
843 | info->cr_save_offset = info->gp_save_offset - info->cr_size; | |
844 | ||
845 | if (TARGET_ALTIVEC_ABI) | |
846 | { | |
847 | info->vrsave_save_offset = info->cr_save_offset - info->vrsave_size; | |
848 | ||
849 | /* Align stack so vector save area is on a quadword boundary. */ | |
850 | if (info->altivec_size != 0) | |
851 | info->altivec_padding_size = 16 - (-info->vrsave_save_offset % 16); | |
852 | ||
853 | info->altivec_save_offset = info->vrsave_save_offset | |
854 | - info->altivec_padding_size | |
855 | - info->altivec_size; | |
856 | ||
857 | /* Adjust for AltiVec case. */ | |
858 | info->ehrd_offset = info->altivec_save_offset; | |
859 | } | |
860 | else | |
861 | info->ehrd_offset = info->cr_save_offset; | |
862 | ||
863 | info->ehrd_offset -= ehrd_size; | |
864 | info->lr_save_offset = reg_size; | |
865 | } | |
866 | ||
867 | save_align = (TARGET_ALTIVEC_ABI || DEFAULT_ABI == ABI_DARWIN) ? 16 : 8; | |
868 | info->save_size = RS6000_ALIGN (info->fp_size | |
869 | + info->gp_size | |
870 | + info->altivec_size | |
871 | + info->altivec_padding_size | |
af979a98 | 872 | + info->rop_hash_size |
2c04f847 BS |
873 | + ehrd_size |
874 | + ehcr_size | |
875 | + info->cr_size | |
876 | + info->vrsave_size, | |
877 | save_align); | |
878 | ||
879 | non_fixed_size = info->vars_size + info->parm_size + info->save_size; | |
880 | ||
881 | info->total_size = RS6000_ALIGN (non_fixed_size + info->fixed_size, | |
882 | ABI_STACK_BOUNDARY / BITS_PER_UNIT); | |
883 | ||
884 | /* Determine if we need to save the link register. */ | |
885 | if (info->calls_p | |
886 | || ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2) | |
887 | && crtl->profile | |
888 | && !TARGET_PROFILE_KERNEL) | |
889 | || (DEFAULT_ABI == ABI_V4 && cfun->calls_alloca) | |
890 | #ifdef TARGET_RELOCATABLE | |
891 | || (DEFAULT_ABI == ABI_V4 | |
892 | && (TARGET_RELOCATABLE || flag_pic > 1) | |
893 | && !constant_pool_empty_p ()) | |
894 | #endif | |
895 | || rs6000_ra_ever_killed ()) | |
896 | info->lr_save_p = 1; | |
897 | ||
898 | using_static_chain_p = (cfun->static_chain_decl != NULL_TREE | |
899 | && df_regs_ever_live_p (STATIC_CHAIN_REGNUM) | |
a365fa06 | 900 | && call_used_or_fixed_reg_p (STATIC_CHAIN_REGNUM)); |
2c04f847 BS |
901 | info->savres_strategy = rs6000_savres_strategy (info, using_static_chain_p); |
902 | ||
903 | if (!(info->savres_strategy & SAVE_INLINE_GPRS) | |
904 | || !(info->savres_strategy & SAVE_INLINE_FPRS) | |
905 | || !(info->savres_strategy & SAVE_INLINE_VRS) | |
906 | || !(info->savres_strategy & REST_INLINE_GPRS) | |
907 | || !(info->savres_strategy & REST_INLINE_FPRS) | |
908 | || !(info->savres_strategy & REST_INLINE_VRS)) | |
909 | info->lr_save_p = 1; | |
910 | ||
911 | if (info->lr_save_p) | |
912 | df_set_regs_ever_live (LR_REGNO, true); | |
913 | ||
914 | /* Determine if we need to allocate any stack frame: | |
915 | ||
916 | For AIX we need to push the stack if a frame pointer is needed | |
917 | (because the stack might be dynamically adjusted), if we are | |
918 | debugging, if we make calls, or if the sum of fp_save, gp_save, | |
919 | and local variables are more than the space needed to save all | |
920 | non-volatile registers: 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8 | |
921 | + 18*8 = 288 (GPR13 reserved). | |
922 | ||
923 | For V.4 we don't have the stack cushion that AIX uses, but assume | |
924 | that the debugger can handle stackless frames. */ | |
925 | ||
926 | if (info->calls_p) | |
927 | info->push_p = 1; | |
928 | ||
929 | else if (DEFAULT_ABI == ABI_V4) | |
930 | info->push_p = non_fixed_size != 0; | |
931 | ||
932 | else if (frame_pointer_needed) | |
933 | info->push_p = 1; | |
934 | ||
50929dd3 | 935 | else if (TARGET_XCOFF && write_symbols != NO_DEBUG && !flag_compare_debug) |
2c04f847 BS |
936 | info->push_p = 1; |
937 | ||
938 | else | |
939 | info->push_p = non_fixed_size > (TARGET_32BIT ? 220 : 288); | |
940 | ||
941 | return info; | |
942 | } | |
943 | ||
944 | static void | |
945 | debug_stack_info (rs6000_stack_t *info) | |
946 | { | |
947 | const char *abi_string; | |
948 | ||
949 | if (! info) | |
950 | info = rs6000_stack_info (); | |
951 | ||
952 | fprintf (stderr, "\nStack information for function %s:\n", | |
953 | ((current_function_decl && DECL_NAME (current_function_decl)) | |
954 | ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl)) | |
955 | : "<unknown>")); | |
956 | ||
957 | switch (info->abi) | |
958 | { | |
959 | default: abi_string = "Unknown"; break; | |
960 | case ABI_NONE: abi_string = "NONE"; break; | |
961 | case ABI_AIX: abi_string = "AIX"; break; | |
962 | case ABI_ELFv2: abi_string = "ELFv2"; break; | |
963 | case ABI_DARWIN: abi_string = "Darwin"; break; | |
964 | case ABI_V4: abi_string = "V.4"; break; | |
965 | } | |
966 | ||
967 | fprintf (stderr, "\tABI = %5s\n", abi_string); | |
968 | ||
969 | if (TARGET_ALTIVEC_ABI) | |
970 | fprintf (stderr, "\tALTIVEC ABI extensions enabled.\n"); | |
971 | ||
972 | if (info->first_gp_reg_save != 32) | |
973 | fprintf (stderr, "\tfirst_gp_reg_save = %5d\n", info->first_gp_reg_save); | |
974 | ||
975 | if (info->first_fp_reg_save != 64) | |
976 | fprintf (stderr, "\tfirst_fp_reg_save = %5d\n", info->first_fp_reg_save); | |
977 | ||
978 | if (info->first_altivec_reg_save <= LAST_ALTIVEC_REGNO) | |
979 | fprintf (stderr, "\tfirst_altivec_reg_save = %5d\n", | |
980 | info->first_altivec_reg_save); | |
981 | ||
982 | if (info->lr_save_p) | |
983 | fprintf (stderr, "\tlr_save_p = %5d\n", info->lr_save_p); | |
984 | ||
985 | if (info->cr_save_p) | |
986 | fprintf (stderr, "\tcr_save_p = %5d\n", info->cr_save_p); | |
987 | ||
988 | if (info->vrsave_mask) | |
989 | fprintf (stderr, "\tvrsave_mask = 0x%x\n", info->vrsave_mask); | |
990 | ||
991 | if (info->push_p) | |
992 | fprintf (stderr, "\tpush_p = %5d\n", info->push_p); | |
993 | ||
994 | if (info->calls_p) | |
995 | fprintf (stderr, "\tcalls_p = %5d\n", info->calls_p); | |
996 | ||
997 | if (info->gp_size) | |
998 | fprintf (stderr, "\tgp_save_offset = %5d\n", info->gp_save_offset); | |
999 | ||
1000 | if (info->fp_size) | |
1001 | fprintf (stderr, "\tfp_save_offset = %5d\n", info->fp_save_offset); | |
1002 | ||
1003 | if (info->altivec_size) | |
1004 | fprintf (stderr, "\taltivec_save_offset = %5d\n", | |
1005 | info->altivec_save_offset); | |
1006 | ||
1007 | if (info->vrsave_size) | |
1008 | fprintf (stderr, "\tvrsave_save_offset = %5d\n", | |
1009 | info->vrsave_save_offset); | |
1010 | ||
af979a98 BS |
1011 | if (info->rop_hash_size) |
1012 | fprintf (stderr, "\trop_hash_save_offset = %5d\n", | |
1013 | info->rop_hash_save_offset); | |
1014 | ||
2c04f847 BS |
1015 | if (info->lr_save_p) |
1016 | fprintf (stderr, "\tlr_save_offset = %5d\n", info->lr_save_offset); | |
1017 | ||
1018 | if (info->cr_save_p) | |
1019 | fprintf (stderr, "\tcr_save_offset = %5d\n", info->cr_save_offset); | |
1020 | ||
1021 | if (info->varargs_save_offset) | |
1022 | fprintf (stderr, "\tvarargs_save_offset = %5d\n", info->varargs_save_offset); | |
1023 | ||
1024 | if (info->total_size) | |
1025 | fprintf (stderr, "\ttotal_size = " HOST_WIDE_INT_PRINT_DEC"\n", | |
1026 | info->total_size); | |
1027 | ||
1028 | if (info->vars_size) | |
1029 | fprintf (stderr, "\tvars_size = " HOST_WIDE_INT_PRINT_DEC"\n", | |
1030 | info->vars_size); | |
1031 | ||
1032 | if (info->parm_size) | |
1033 | fprintf (stderr, "\tparm_size = %5d\n", info->parm_size); | |
1034 | ||
1035 | if (info->fixed_size) | |
1036 | fprintf (stderr, "\tfixed_size = %5d\n", info->fixed_size); | |
1037 | ||
1038 | if (info->gp_size) | |
1039 | fprintf (stderr, "\tgp_size = %5d\n", info->gp_size); | |
1040 | ||
1041 | if (info->fp_size) | |
1042 | fprintf (stderr, "\tfp_size = %5d\n", info->fp_size); | |
1043 | ||
1044 | if (info->altivec_size) | |
1045 | fprintf (stderr, "\taltivec_size = %5d\n", info->altivec_size); | |
1046 | ||
1047 | if (info->vrsave_size) | |
1048 | fprintf (stderr, "\tvrsave_size = %5d\n", info->vrsave_size); | |
1049 | ||
1050 | if (info->altivec_padding_size) | |
1051 | fprintf (stderr, "\taltivec_padding_size= %5d\n", | |
1052 | info->altivec_padding_size); | |
1053 | ||
af979a98 BS |
1054 | if (info->rop_hash_size) |
1055 | fprintf (stderr, "\trop_hash_size = %5d\n", info->rop_hash_size); | |
1056 | ||
2c04f847 BS |
1057 | if (info->cr_size) |
1058 | fprintf (stderr, "\tcr_size = %5d\n", info->cr_size); | |
1059 | ||
1060 | if (info->save_size) | |
1061 | fprintf (stderr, "\tsave_size = %5d\n", info->save_size); | |
1062 | ||
1063 | if (info->reg_size != 4) | |
1064 | fprintf (stderr, "\treg_size = %5d\n", info->reg_size); | |
1065 | ||
1066 | fprintf (stderr, "\tsave-strategy = %04x\n", info->savres_strategy); | |
1067 | ||
1068 | if (info->abi == ABI_DARWIN) | |
1069 | fprintf (stderr, "\tWORLD_SAVE_P = %5d\n", WORLD_SAVE_P(info)); | |
1070 | ||
1071 | fprintf (stderr, "\n"); | |
1072 | } | |
1073 | ||
1074 | rtx | |
1075 | rs6000_return_addr (int count, rtx frame) | |
1076 | { | |
1077 | /* We can't use get_hard_reg_initial_val for LR when count == 0 if LR | |
1078 | is trashed by the prologue, as it is for PIC on ABI_V4 and Darwin. */ | |
1079 | if (count != 0 | |
1080 | || ((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_DARWIN) && flag_pic)) | |
1081 | { | |
1082 | cfun->machine->ra_needs_full_frame = 1; | |
1083 | ||
1084 | if (count == 0) | |
1085 | /* FRAME is set to frame_pointer_rtx by the generic code, but that | |
1086 | is good for loading 0(r1) only when !FRAME_GROWS_DOWNWARD. */ | |
1087 | frame = stack_pointer_rtx; | |
1088 | rtx prev_frame_addr = memory_address (Pmode, frame); | |
1089 | rtx prev_frame = copy_to_reg (gen_rtx_MEM (Pmode, prev_frame_addr)); | |
1090 | rtx lr_save_off = plus_constant (Pmode, | |
1091 | prev_frame, RETURN_ADDRESS_OFFSET); | |
1092 | rtx lr_save_addr = memory_address (Pmode, lr_save_off); | |
1093 | return gen_rtx_MEM (Pmode, lr_save_addr); | |
1094 | } | |
1095 | ||
1096 | cfun->machine->ra_need_lr = 1; | |
1097 | return get_hard_reg_initial_val (Pmode, LR_REGNO); | |
1098 | } | |
1099 | ||
1100 | /* Helper function for rs6000_function_ok_for_sibcall. */ | |
1101 | ||
1102 | bool | |
1103 | rs6000_decl_ok_for_sibcall (tree decl) | |
1104 | { | |
1105 | /* Sibcalls are always fine for the Darwin ABI. */ | |
1106 | if (DEFAULT_ABI == ABI_DARWIN) | |
1107 | return true; | |
1108 | ||
1109 | if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2) | |
1110 | { | |
95f17e26 BS |
1111 | /* A function compiled using the PC-relative addressing model does not |
1112 | use a TOC pointer; nor is it guaranteed to preserve the value of | |
1113 | r2 for its caller's TOC. Such a function may make sibcalls to any | |
1114 | function, whether local or external, without restriction based on | |
1115 | TOC-save/restore rules. */ | |
8c0f8755 | 1116 | if (rs6000_pcrel_p ()) |
95f17e26 BS |
1117 | return true; |
1118 | ||
1119 | /* Otherwise, under the AIX or ELFv2 ABIs we can't allow sibcalls | |
1120 | to non-local functions, because the callee may not preserve the | |
1121 | TOC pointer, and there's no way to ensure we restore the TOC when | |
2c04f847 BS |
1122 | we return. */ |
1123 | if (!decl || DECL_EXTERNAL (decl) || DECL_WEAK (decl) | |
1124 | || !(*targetm.binds_local_p) (decl)) | |
1125 | return false; | |
1126 | ||
95f17e26 BS |
1127 | /* A local sibcall from a function that preserves the TOC pointer |
1128 | to a function that does not is invalid for the same reason. */ | |
1129 | if (rs6000_fndecl_pcrel_p (decl)) | |
2c04f847 BS |
1130 | return false; |
1131 | ||
95f17e26 | 1132 | return true; |
2c04f847 BS |
1133 | } |
1134 | ||
1135 | /* With the secure-plt SYSV ABI we can't make non-local calls when | |
1136 | -fpic/PIC because the plt call stubs use r30. */ | |
1137 | if (DEFAULT_ABI != ABI_V4 | |
1138 | || (TARGET_SECURE_PLT | |
1139 | && flag_pic | |
1140 | && (!decl || !((*targetm.binds_local_p) (decl))))) | |
1141 | return false; | |
1142 | ||
1143 | return true; | |
1144 | } | |
1145 | ||
1146 | /* Say whether a function is a candidate for sibcall handling or not. */ | |
1147 | ||
1148 | bool | |
1149 | rs6000_function_ok_for_sibcall (tree decl, tree exp) | |
1150 | { | |
1151 | tree fntype; | |
1152 | ||
1153 | /* The sibcall epilogue may clobber the static chain register. | |
1154 | ??? We could work harder and avoid that, but it's probably | |
1155 | not worth the hassle in practice. */ | |
1156 | if (CALL_EXPR_STATIC_CHAIN (exp)) | |
1157 | return false; | |
1158 | ||
1159 | if (decl) | |
1160 | fntype = TREE_TYPE (decl); | |
1161 | else | |
1162 | fntype = TREE_TYPE (TREE_TYPE (CALL_EXPR_FN (exp))); | |
1163 | ||
1164 | /* We can't do it if the called function has more vector parameters | |
1165 | than the current function; there's nowhere to put the VRsave code. */ | |
1166 | if (TARGET_ALTIVEC_ABI | |
1167 | && TARGET_ALTIVEC_VRSAVE | |
1168 | && !(decl && decl == current_function_decl)) | |
1169 | { | |
1170 | function_args_iterator args_iter; | |
1171 | tree type; | |
1172 | int nvreg = 0; | |
1173 | ||
1174 | /* Functions with vector parameters are required to have a | |
1175 | prototype, so the argument type info must be available | |
1176 | here. */ | |
1177 | FOREACH_FUNCTION_ARGS(fntype, type, args_iter) | |
1178 | if (TREE_CODE (type) == VECTOR_TYPE | |
1179 | && ALTIVEC_OR_VSX_VECTOR_MODE (TYPE_MODE (type))) | |
1180 | nvreg++; | |
1181 | ||
1182 | FOREACH_FUNCTION_ARGS(TREE_TYPE (current_function_decl), type, args_iter) | |
1183 | if (TREE_CODE (type) == VECTOR_TYPE | |
1184 | && ALTIVEC_OR_VSX_VECTOR_MODE (TYPE_MODE (type))) | |
1185 | nvreg--; | |
1186 | ||
1187 | if (nvreg > 0) | |
1188 | return false; | |
1189 | } | |
1190 | ||
1191 | if (rs6000_decl_ok_for_sibcall (decl)) | |
1192 | { | |
1193 | tree attr_list = TYPE_ATTRIBUTES (fntype); | |
1194 | ||
1195 | if (!lookup_attribute ("longcall", attr_list) | |
1196 | || lookup_attribute ("shortcall", attr_list)) | |
1197 | return true; | |
1198 | } | |
1199 | ||
1200 | return false; | |
1201 | } | |
1202 | ||
1203 | static int | |
1204 | rs6000_ra_ever_killed (void) | |
1205 | { | |
1206 | rtx_insn *top; | |
1207 | rtx reg; | |
1208 | rtx_insn *insn; | |
1209 | ||
1210 | if (cfun->is_thunk) | |
1211 | return 0; | |
1212 | ||
1213 | if (cfun->machine->lr_save_state) | |
1214 | return cfun->machine->lr_save_state - 1; | |
1215 | ||
1216 | /* regs_ever_live has LR marked as used if any sibcalls are present, | |
1217 | but this should not force saving and restoring in the | |
1218 | pro/epilogue. Likewise, reg_set_between_p thinks a sibcall | |
1219 | clobbers LR, so that is inappropriate. */ | |
1220 | ||
1221 | /* Also, the prologue can generate a store into LR that | |
1222 | doesn't really count, like this: | |
1223 | ||
1224 | move LR->R0 | |
1225 | bcl to set PIC register | |
1226 | move LR->R31 | |
1227 | move R0->LR | |
1228 | ||
1229 | When we're called from the epilogue, we need to avoid counting | |
1230 | this as a store. */ | |
1231 | ||
1232 | push_topmost_sequence (); | |
1233 | top = get_insns (); | |
1234 | pop_topmost_sequence (); | |
1235 | reg = gen_rtx_REG (Pmode, LR_REGNO); | |
1236 | ||
1237 | for (insn = NEXT_INSN (top); insn != NULL_RTX; insn = NEXT_INSN (insn)) | |
1238 | { | |
1239 | if (INSN_P (insn)) | |
1240 | { | |
1241 | if (CALL_P (insn)) | |
1242 | { | |
1243 | if (!SIBLING_CALL_P (insn)) | |
1244 | return 1; | |
1245 | } | |
1246 | else if (find_regno_note (insn, REG_INC, LR_REGNO)) | |
1247 | return 1; | |
1248 | else if (set_of (reg, insn) != NULL_RTX | |
1249 | && !prologue_epilogue_contains (insn)) | |
1250 | return 1; | |
1251 | } | |
1252 | } | |
1253 | return 0; | |
1254 | } | |
1255 | \f | |
1256 | /* Emit instructions needed to load the TOC register. | |
1257 | This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is | |
1258 | a constant pool; or for SVR4 -fpic. */ | |
1259 | ||
1260 | void | |
1261 | rs6000_emit_load_toc_table (int fromprolog) | |
1262 | { | |
1263 | rtx dest; | |
1264 | dest = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM); | |
1265 | ||
1266 | if (TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI == ABI_V4 && flag_pic) | |
1267 | { | |
1268 | char buf[30]; | |
1269 | rtx lab, tmp1, tmp2, got; | |
1270 | ||
1271 | lab = gen_label_rtx (); | |
1272 | ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (lab)); | |
1273 | lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); | |
1274 | if (flag_pic == 2) | |
1275 | { | |
1276 | got = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (toc_label_name)); | |
1277 | need_toc_init = 1; | |
1278 | } | |
1279 | else | |
1280 | got = rs6000_got_sym (); | |
1281 | tmp1 = tmp2 = dest; | |
1282 | if (!fromprolog) | |
1283 | { | |
1284 | tmp1 = gen_reg_rtx (Pmode); | |
1285 | tmp2 = gen_reg_rtx (Pmode); | |
1286 | } | |
1287 | emit_insn (gen_load_toc_v4_PIC_1 (lab)); | |
1288 | emit_move_insn (tmp1, gen_rtx_REG (Pmode, LR_REGNO)); | |
1289 | emit_insn (gen_load_toc_v4_PIC_3b (tmp2, tmp1, got, lab)); | |
1290 | emit_insn (gen_load_toc_v4_PIC_3c (dest, tmp2, got, lab)); | |
1291 | } | |
1292 | else if (TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 1) | |
1293 | { | |
1294 | emit_insn (gen_load_toc_v4_pic_si ()); | |
1295 | emit_move_insn (dest, gen_rtx_REG (Pmode, LR_REGNO)); | |
1296 | } | |
1297 | else if (TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 2) | |
1298 | { | |
1299 | char buf[30]; | |
1300 | rtx temp0 = (fromprolog | |
1301 | ? gen_rtx_REG (Pmode, 0) | |
1302 | : gen_reg_rtx (Pmode)); | |
1303 | ||
1304 | if (fromprolog) | |
1305 | { | |
1306 | rtx symF, symL; | |
1307 | ||
1308 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno); | |
1309 | symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); | |
1310 | ||
1311 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno); | |
1312 | symL = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); | |
1313 | ||
1314 | emit_insn (gen_load_toc_v4_PIC_1 (symF)); | |
1315 | emit_move_insn (dest, gen_rtx_REG (Pmode, LR_REGNO)); | |
1316 | emit_insn (gen_load_toc_v4_PIC_2 (temp0, dest, symL, symF)); | |
1317 | } | |
1318 | else | |
1319 | { | |
1320 | rtx tocsym, lab; | |
1321 | ||
1322 | tocsym = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (toc_label_name)); | |
1323 | need_toc_init = 1; | |
1324 | lab = gen_label_rtx (); | |
1325 | emit_insn (gen_load_toc_v4_PIC_1b (tocsym, lab)); | |
1326 | emit_move_insn (dest, gen_rtx_REG (Pmode, LR_REGNO)); | |
1327 | if (TARGET_LINK_STACK) | |
1328 | emit_insn (gen_addsi3 (dest, dest, GEN_INT (4))); | |
1329 | emit_move_insn (temp0, gen_rtx_MEM (Pmode, dest)); | |
1330 | } | |
1331 | emit_insn (gen_addsi3 (dest, temp0, dest)); | |
1332 | } | |
1333 | else if (TARGET_ELF && !TARGET_AIX && flag_pic == 0 && TARGET_MINIMAL_TOC) | |
1334 | { | |
1335 | /* This is for AIX code running in non-PIC ELF32. */ | |
1336 | rtx realsym = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (toc_label_name)); | |
1337 | ||
1338 | need_toc_init = 1; | |
1339 | emit_insn (gen_elf_high (dest, realsym)); | |
1340 | emit_insn (gen_elf_low (dest, dest, realsym)); | |
1341 | } | |
1342 | else | |
1343 | { | |
1344 | gcc_assert (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2); | |
1345 | ||
1346 | if (TARGET_32BIT) | |
1347 | emit_insn (gen_load_toc_aix_si (dest)); | |
1348 | else | |
1349 | emit_insn (gen_load_toc_aix_di (dest)); | |
1350 | } | |
1351 | } | |
1352 | ||
1353 | /* Emit instructions to restore the link register after determining where | |
1354 | its value has been stored. */ | |
1355 | ||
1356 | void | |
1357 | rs6000_emit_eh_reg_restore (rtx source, rtx scratch) | |
1358 | { | |
1359 | rs6000_stack_t *info = rs6000_stack_info (); | |
1360 | rtx operands[2]; | |
1361 | ||
1362 | operands[0] = source; | |
1363 | operands[1] = scratch; | |
1364 | ||
1365 | if (info->lr_save_p) | |
1366 | { | |
1367 | rtx frame_rtx = stack_pointer_rtx; | |
1368 | HOST_WIDE_INT sp_offset = 0; | |
1369 | rtx tmp; | |
1370 | ||
1371 | if (frame_pointer_needed | |
1372 | || cfun->calls_alloca | |
1373 | || info->total_size > 32767) | |
1374 | { | |
1375 | tmp = gen_frame_mem (Pmode, frame_rtx); | |
1376 | emit_move_insn (operands[1], tmp); | |
1377 | frame_rtx = operands[1]; | |
1378 | } | |
1379 | else if (info->push_p) | |
1380 | sp_offset = info->total_size; | |
1381 | ||
1382 | tmp = plus_constant (Pmode, frame_rtx, | |
1383 | info->lr_save_offset + sp_offset); | |
1384 | tmp = gen_frame_mem (Pmode, tmp); | |
1385 | emit_move_insn (tmp, operands[0]); | |
1386 | } | |
1387 | else | |
1388 | emit_move_insn (gen_rtx_REG (Pmode, LR_REGNO), operands[0]); | |
1389 | ||
1390 | /* Freeze lr_save_p. We've just emitted rtl that depends on the | |
1391 | state of lr_save_p so any change from here on would be a bug. In | |
1392 | particular, stop rs6000_ra_ever_killed from considering the SET | |
1393 | of lr we may have added just above. */ | |
1394 | cfun->machine->lr_save_state = info->lr_save_p + 1; | |
1395 | } | |
1396 | ||
1397 | /* This returns nonzero if the current function uses the TOC. This is | |
1398 | determined by the presence of (use (unspec ... UNSPEC_TOC)), which | |
1399 | is generated by the ABI_V4 load_toc_* patterns. | |
1400 | Return 2 instead of 1 if the load_toc_* pattern is in the function | |
1401 | partition that doesn't start the function. */ | |
1402 | #if TARGET_ELF | |
1403 | int | |
1404 | uses_TOC (void) | |
1405 | { | |
1406 | rtx_insn *insn; | |
1407 | int ret = 1; | |
1408 | ||
1409 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) | |
1410 | { | |
1411 | if (INSN_P (insn)) | |
1412 | { | |
1413 | rtx pat = PATTERN (insn); | |
1414 | int i; | |
1415 | ||
1416 | if (GET_CODE (pat) == PARALLEL) | |
1417 | for (i = 0; i < XVECLEN (pat, 0); i++) | |
1418 | { | |
1419 | rtx sub = XVECEXP (pat, 0, i); | |
1420 | if (GET_CODE (sub) == USE) | |
1421 | { | |
1422 | sub = XEXP (sub, 0); | |
1423 | if (GET_CODE (sub) == UNSPEC | |
1424 | && XINT (sub, 1) == UNSPEC_TOC) | |
1425 | return ret; | |
1426 | } | |
1427 | } | |
1428 | } | |
1429 | else if (crtl->has_bb_partition | |
1430 | && NOTE_P (insn) | |
1431 | && NOTE_KIND (insn) == NOTE_INSN_SWITCH_TEXT_SECTIONS) | |
1432 | ret = 2; | |
1433 | } | |
1434 | return 0; | |
1435 | } | |
1436 | #endif | |
1437 | ||
2c04f847 BS |
1438 | /* Issue assembly directives that create a reference to the given DWARF |
1439 | FRAME_TABLE_LABEL from the current function section. */ | |
1440 | void | |
1441 | rs6000_aix_asm_output_dwarf_table_ref (char * frame_table_label) | |
1442 | { | |
1443 | fprintf (asm_out_file, "\t.ref %s\n", | |
1444 | (* targetm.strip_name_encoding) (frame_table_label)); | |
1445 | } | |
1446 | \f | |
1447 | /* This ties together stack memory (MEM with an alias set of frame_alias_set) | |
1448 | and the change to the stack pointer. */ | |
1449 | ||
1450 | static void | |
1451 | rs6000_emit_stack_tie (rtx fp, bool hard_frame_needed) | |
1452 | { | |
1453 | rtvec p; | |
1454 | int i; | |
1455 | rtx regs[3]; | |
1456 | ||
1457 | i = 0; | |
1458 | regs[i++] = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM); | |
1459 | if (hard_frame_needed) | |
1460 | regs[i++] = gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM); | |
1461 | if (!(REGNO (fp) == STACK_POINTER_REGNUM | |
1462 | || (hard_frame_needed | |
1463 | && REGNO (fp) == HARD_FRAME_POINTER_REGNUM))) | |
1464 | regs[i++] = fp; | |
1465 | ||
1466 | p = rtvec_alloc (i); | |
1467 | while (--i >= 0) | |
1468 | { | |
1469 | rtx mem = gen_frame_mem (BLKmode, regs[i]); | |
1470 | RTVEC_ELT (p, i) = gen_rtx_SET (mem, const0_rtx); | |
1471 | } | |
1472 | ||
1473 | emit_insn (gen_stack_tie (gen_rtx_PARALLEL (VOIDmode, p))); | |
1474 | } | |
1475 | ||
1476 | /* Allocate SIZE_INT bytes on the stack using a store with update style insn | |
1477 | and set the appropriate attributes for the generated insn. Return the | |
1478 | first insn which adjusts the stack pointer or the last insn before | |
1479 | the stack adjustment loop. | |
1480 | ||
1481 | SIZE_INT is used to create the CFI note for the allocation. | |
1482 | ||
1483 | SIZE_RTX is an rtx containing the size of the adjustment. Note that | |
1484 | since stacks grow to lower addresses its runtime value is -SIZE_INT. | |
1485 | ||
1486 | ORIG_SP contains the backchain value that must be stored at *sp. */ | |
1487 | ||
1488 | static rtx_insn * | |
1489 | rs6000_emit_allocate_stack_1 (HOST_WIDE_INT size_int, rtx orig_sp) | |
1490 | { | |
1491 | rtx_insn *insn; | |
1492 | ||
1493 | rtx size_rtx = GEN_INT (-size_int); | |
1494 | if (size_int > 32767) | |
1495 | { | |
1496 | rtx tmp_reg = gen_rtx_REG (Pmode, 0); | |
1497 | /* Need a note here so that try_split doesn't get confused. */ | |
1498 | if (get_last_insn () == NULL_RTX) | |
1499 | emit_note (NOTE_INSN_DELETED); | |
1500 | insn = emit_move_insn (tmp_reg, size_rtx); | |
1501 | try_split (PATTERN (insn), insn, 0); | |
1502 | size_rtx = tmp_reg; | |
1503 | } | |
1504 | ||
1505 | if (TARGET_32BIT) | |
1506 | insn = emit_insn (gen_movsi_update_stack (stack_pointer_rtx, | |
1507 | stack_pointer_rtx, | |
1508 | size_rtx, | |
1509 | orig_sp)); | |
1510 | else | |
1511 | insn = emit_insn (gen_movdi_update_stack (stack_pointer_rtx, | |
1512 | stack_pointer_rtx, | |
1513 | size_rtx, | |
1514 | orig_sp)); | |
1515 | rtx par = PATTERN (insn); | |
1516 | gcc_assert (GET_CODE (par) == PARALLEL); | |
1517 | rtx set = XVECEXP (par, 0, 0); | |
1518 | gcc_assert (GET_CODE (set) == SET); | |
1519 | rtx mem = SET_DEST (set); | |
1520 | gcc_assert (MEM_P (mem)); | |
1521 | MEM_NOTRAP_P (mem) = 1; | |
1522 | set_mem_alias_set (mem, get_frame_alias_set ()); | |
1523 | ||
1524 | RTX_FRAME_RELATED_P (insn) = 1; | |
1525 | add_reg_note (insn, REG_FRAME_RELATED_EXPR, | |
1526 | gen_rtx_SET (stack_pointer_rtx, | |
1527 | gen_rtx_PLUS (Pmode, | |
1528 | stack_pointer_rtx, | |
1529 | GEN_INT (-size_int)))); | |
1530 | ||
1531 | /* Emit a blockage to ensure the allocation/probing insns are | |
1532 | not optimized, combined, removed, etc. Add REG_STACK_CHECK | |
1533 | note for similar reasons. */ | |
1534 | if (flag_stack_clash_protection) | |
1535 | { | |
1536 | add_reg_note (insn, REG_STACK_CHECK, const0_rtx); | |
1537 | emit_insn (gen_blockage ()); | |
1538 | } | |
1539 | ||
1540 | return insn; | |
1541 | } | |
1542 | ||
1543 | static HOST_WIDE_INT | |
1544 | get_stack_clash_protection_probe_interval (void) | |
1545 | { | |
1546 | return (HOST_WIDE_INT_1U | |
028d4092 | 1547 | << param_stack_clash_protection_probe_interval); |
2c04f847 BS |
1548 | } |
1549 | ||
1550 | static HOST_WIDE_INT | |
1551 | get_stack_clash_protection_guard_size (void) | |
1552 | { | |
1553 | return (HOST_WIDE_INT_1U | |
028d4092 | 1554 | << param_stack_clash_protection_guard_size); |
2c04f847 BS |
1555 | } |
1556 | ||
1557 | /* Allocate ORIG_SIZE bytes on the stack and probe the newly | |
1558 | allocated space every STACK_CLASH_PROTECTION_PROBE_INTERVAL bytes. | |
1559 | ||
1560 | COPY_REG, if non-null, should contain a copy of the original | |
1561 | stack pointer at exit from this function. | |
1562 | ||
1563 | This is subtly different than the Ada probing in that it tries hard to | |
1564 | prevent attacks that jump the stack guard. Thus it is never allowed to | |
1565 | allocate more than STACK_CLASH_PROTECTION_PROBE_INTERVAL bytes of stack | |
1566 | space without a suitable probe. */ | |
1567 | static rtx_insn * | |
1568 | rs6000_emit_probe_stack_range_stack_clash (HOST_WIDE_INT orig_size, | |
1569 | rtx copy_reg) | |
1570 | { | |
1571 | rtx orig_sp = copy_reg; | |
1572 | ||
1573 | HOST_WIDE_INT probe_interval = get_stack_clash_protection_probe_interval (); | |
1574 | ||
1575 | /* Round the size down to a multiple of PROBE_INTERVAL. */ | |
1576 | HOST_WIDE_INT rounded_size = ROUND_DOWN (orig_size, probe_interval); | |
1577 | ||
1578 | /* If explicitly requested, | |
1579 | or the rounded size is not the same as the original size | |
700d4cb0 | 1580 | or the rounded size is greater than a page, |
2c04f847 BS |
1581 | then we will need a copy of the original stack pointer. */ |
1582 | if (rounded_size != orig_size | |
1583 | || rounded_size > probe_interval | |
1584 | || copy_reg) | |
1585 | { | |
1586 | /* If the caller did not request a copy of the incoming stack | |
1587 | pointer, then we use r0 to hold the copy. */ | |
1588 | if (!copy_reg) | |
1589 | orig_sp = gen_rtx_REG (Pmode, 0); | |
1590 | emit_move_insn (orig_sp, stack_pointer_rtx); | |
1591 | } | |
1592 | ||
1593 | /* There's three cases here. | |
1594 | ||
1595 | One is a single probe which is the most common and most efficiently | |
1596 | implemented as it does not have to have a copy of the original | |
1597 | stack pointer if there are no residuals. | |
1598 | ||
1599 | Second is unrolled allocation/probes which we use if there's just | |
1600 | a few of them. It needs to save the original stack pointer into a | |
1601 | temporary for use as a source register in the allocation/probe. | |
1602 | ||
1603 | Last is a loop. This is the most uncommon case and least efficient. */ | |
1604 | rtx_insn *retval = NULL; | |
1605 | if (rounded_size == probe_interval) | |
1606 | { | |
1607 | retval = rs6000_emit_allocate_stack_1 (probe_interval, stack_pointer_rtx); | |
1608 | ||
1609 | dump_stack_clash_frame_info (PROBE_INLINE, rounded_size != orig_size); | |
1610 | } | |
1611 | else if (rounded_size <= 8 * probe_interval) | |
1612 | { | |
1613 | /* The ABI requires using the store with update insns to allocate | |
1614 | space and store the backchain into the stack | |
1615 | ||
1616 | So we save the current stack pointer into a temporary, then | |
1617 | emit the store-with-update insns to store the saved stack pointer | |
1618 | into the right location in each new page. */ | |
1619 | for (int i = 0; i < rounded_size; i += probe_interval) | |
1620 | { | |
1621 | rtx_insn *insn | |
1622 | = rs6000_emit_allocate_stack_1 (probe_interval, orig_sp); | |
1623 | ||
1624 | /* Save the first stack adjustment in RETVAL. */ | |
1625 | if (i == 0) | |
1626 | retval = insn; | |
1627 | } | |
1628 | ||
1629 | dump_stack_clash_frame_info (PROBE_INLINE, rounded_size != orig_size); | |
1630 | } | |
1631 | else | |
1632 | { | |
1633 | /* Compute the ending address. */ | |
1634 | rtx end_addr | |
1635 | = copy_reg ? gen_rtx_REG (Pmode, 0) : gen_rtx_REG (Pmode, 12); | |
1636 | rtx rs = GEN_INT (-rounded_size); | |
c006911d JJ |
1637 | rtx_insn *insn = gen_add3_insn (end_addr, stack_pointer_rtx, rs); |
1638 | if (insn == NULL) | |
1639 | { | |
1640 | emit_move_insn (end_addr, rs); | |
1641 | insn = gen_add3_insn (end_addr, end_addr, stack_pointer_rtx); | |
1642 | gcc_assert (insn); | |
1643 | } | |
1644 | bool add_note = false; | |
1645 | if (!NONJUMP_INSN_P (insn) || NEXT_INSN (insn)) | |
1646 | add_note = true; | |
2c04f847 BS |
1647 | else |
1648 | { | |
c006911d JJ |
1649 | rtx set = single_set (insn); |
1650 | if (set == NULL_RTX | |
1651 | || SET_DEST (set) != end_addr | |
1652 | || GET_CODE (SET_SRC (set)) != PLUS | |
1653 | || XEXP (SET_SRC (set), 0) != stack_pointer_rtx | |
1654 | || XEXP (SET_SRC (set), 1) != rs) | |
1655 | add_note = true; | |
2c04f847 | 1656 | } |
c006911d JJ |
1657 | insn = emit_insn (insn); |
1658 | /* Describe the effect of INSN to the CFI engine, unless it | |
1659 | is a single insn that describes it itself. */ | |
1660 | if (add_note) | |
1661 | add_reg_note (insn, REG_FRAME_RELATED_EXPR, | |
1662 | gen_rtx_SET (end_addr, | |
1663 | gen_rtx_PLUS (Pmode, stack_pointer_rtx, | |
1664 | rs))); | |
2c04f847 BS |
1665 | RTX_FRAME_RELATED_P (insn) = 1; |
1666 | ||
1667 | /* Emit the loop. */ | |
1668 | if (TARGET_64BIT) | |
1669 | retval = emit_insn (gen_probe_stack_rangedi (stack_pointer_rtx, | |
1670 | stack_pointer_rtx, orig_sp, | |
1671 | end_addr)); | |
1672 | else | |
1673 | retval = emit_insn (gen_probe_stack_rangesi (stack_pointer_rtx, | |
1674 | stack_pointer_rtx, orig_sp, | |
1675 | end_addr)); | |
1676 | RTX_FRAME_RELATED_P (retval) = 1; | |
1677 | /* Describe the effect of INSN to the CFI engine. */ | |
1678 | add_reg_note (retval, REG_FRAME_RELATED_EXPR, | |
1679 | gen_rtx_SET (stack_pointer_rtx, end_addr)); | |
1680 | ||
1681 | /* Emit a blockage to ensure the allocation/probing insns are | |
1682 | not optimized, combined, removed, etc. Other cases handle this | |
1683 | within their call to rs6000_emit_allocate_stack_1. */ | |
1684 | emit_insn (gen_blockage ()); | |
1685 | ||
1686 | dump_stack_clash_frame_info (PROBE_LOOP, rounded_size != orig_size); | |
1687 | } | |
1688 | ||
1689 | if (orig_size != rounded_size) | |
1690 | { | |
1691 | /* Allocate (and implicitly probe) any residual space. */ | |
1692 | HOST_WIDE_INT residual = orig_size - rounded_size; | |
1693 | ||
1694 | rtx_insn *insn = rs6000_emit_allocate_stack_1 (residual, orig_sp); | |
1695 | ||
1696 | /* If the residual was the only allocation, then we can return the | |
1697 | allocating insn. */ | |
1698 | if (!retval) | |
1699 | retval = insn; | |
1700 | } | |
1701 | ||
1702 | return retval; | |
1703 | } | |
1704 | ||
1705 | /* Emit the correct code for allocating stack space, as insns. | |
1706 | If COPY_REG, make sure a copy of the old frame is left there. | |
1707 | The generated code may use hard register 0 as a temporary. */ | |
1708 | ||
1709 | static rtx_insn * | |
1710 | rs6000_emit_allocate_stack (HOST_WIDE_INT size, rtx copy_reg, int copy_off) | |
1711 | { | |
1712 | rtx_insn *insn; | |
1713 | rtx stack_reg = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM); | |
1714 | rtx tmp_reg = gen_rtx_REG (Pmode, 0); | |
1715 | rtx todec = gen_int_mode (-size, Pmode); | |
1716 | ||
1717 | if (INTVAL (todec) != -size) | |
1718 | { | |
1719 | warning (0, "stack frame too large"); | |
1720 | emit_insn (gen_trap ()); | |
1721 | return 0; | |
1722 | } | |
1723 | ||
1724 | if (crtl->limit_stack) | |
1725 | { | |
1726 | if (REG_P (stack_limit_rtx) | |
1727 | && REGNO (stack_limit_rtx) > 1 | |
1728 | && REGNO (stack_limit_rtx) <= 31) | |
1729 | { | |
1730 | rtx_insn *insn | |
1731 | = gen_add3_insn (tmp_reg, stack_limit_rtx, GEN_INT (size)); | |
1732 | gcc_assert (insn); | |
1733 | emit_insn (insn); | |
1734 | emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg, const0_rtx)); | |
1735 | } | |
1736 | else if (SYMBOL_REF_P (stack_limit_rtx) | |
1737 | && TARGET_32BIT | |
1738 | && DEFAULT_ABI == ABI_V4 | |
1739 | && !flag_pic) | |
1740 | { | |
1741 | rtx toload = gen_rtx_CONST (VOIDmode, | |
1742 | gen_rtx_PLUS (Pmode, | |
1743 | stack_limit_rtx, | |
1744 | GEN_INT (size))); | |
1745 | ||
26bd2dab SB |
1746 | /* We cannot use r0 with elf_low. Lamely solve this problem by |
1747 | moving registers around. */ | |
1748 | rtx r11_reg = gen_rtx_REG (Pmode, 11); | |
1749 | emit_move_insn (tmp_reg, r11_reg); | |
1750 | emit_insn (gen_elf_high (r11_reg, toload)); | |
1751 | emit_insn (gen_elf_low (r11_reg, r11_reg, toload)); | |
1752 | emit_insn (gen_cond_trap (LTU, stack_reg, r11_reg, const0_rtx)); | |
1753 | emit_move_insn (r11_reg, tmp_reg); | |
2c04f847 BS |
1754 | } |
1755 | else | |
1756 | warning (0, "stack limit expression is not supported"); | |
1757 | } | |
1758 | ||
1759 | if (flag_stack_clash_protection) | |
1760 | { | |
1761 | if (size < get_stack_clash_protection_guard_size ()) | |
1762 | dump_stack_clash_frame_info (NO_PROBE_SMALL_FRAME, true); | |
1763 | else | |
1764 | { | |
1765 | rtx_insn *insn = rs6000_emit_probe_stack_range_stack_clash (size, | |
1766 | copy_reg); | |
1767 | ||
1768 | /* If we asked for a copy with an offset, then we still need add in | |
1769 | the offset. */ | |
1770 | if (copy_reg && copy_off) | |
1771 | emit_insn (gen_add3_insn (copy_reg, copy_reg, GEN_INT (copy_off))); | |
1772 | return insn; | |
1773 | } | |
1774 | } | |
1775 | ||
1776 | if (copy_reg) | |
1777 | { | |
1778 | if (copy_off != 0) | |
1779 | emit_insn (gen_add3_insn (copy_reg, stack_reg, GEN_INT (copy_off))); | |
1780 | else | |
1781 | emit_move_insn (copy_reg, stack_reg); | |
1782 | } | |
1783 | ||
1784 | /* Since we didn't use gen_frame_mem to generate the MEM, grab | |
1785 | it now and set the alias set/attributes. The above gen_*_update | |
1786 | calls will generate a PARALLEL with the MEM set being the first | |
1787 | operation. */ | |
1788 | insn = rs6000_emit_allocate_stack_1 (size, stack_reg); | |
1789 | return insn; | |
1790 | } | |
1791 | ||
1792 | #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP) | |
1793 | ||
1794 | #if PROBE_INTERVAL > 32768 | |
1795 | #error Cannot use indexed addressing mode for stack probing | |
1796 | #endif | |
1797 | ||
1798 | /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE, | |
1799 | inclusive. These are offsets from the current stack pointer. */ | |
1800 | ||
1801 | static void | |
1802 | rs6000_emit_probe_stack_range (HOST_WIDE_INT first, HOST_WIDE_INT size) | |
1803 | { | |
1804 | /* See if we have a constant small number of probes to generate. If so, | |
1805 | that's the easy case. */ | |
1806 | if (first + size <= 32768) | |
1807 | { | |
1808 | HOST_WIDE_INT i; | |
1809 | ||
1810 | /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 1 until | |
1811 | it exceeds SIZE. If only one probe is needed, this will not | |
1812 | generate any code. Then probe at FIRST + SIZE. */ | |
1813 | for (i = PROBE_INTERVAL; i < size; i += PROBE_INTERVAL) | |
1814 | emit_stack_probe (plus_constant (Pmode, stack_pointer_rtx, | |
1815 | -(first + i))); | |
1816 | ||
1817 | emit_stack_probe (plus_constant (Pmode, stack_pointer_rtx, | |
1818 | -(first + size))); | |
1819 | } | |
1820 | ||
1821 | /* Otherwise, do the same as above, but in a loop. Note that we must be | |
1822 | extra careful with variables wrapping around because we might be at | |
1823 | the very top (or the very bottom) of the address space and we have | |
1824 | to be able to handle this case properly; in particular, we use an | |
1825 | equality test for the loop condition. */ | |
1826 | else | |
1827 | { | |
1828 | HOST_WIDE_INT rounded_size; | |
1829 | rtx r12 = gen_rtx_REG (Pmode, 12); | |
1830 | rtx r0 = gen_rtx_REG (Pmode, 0); | |
1831 | ||
1832 | /* Sanity check for the addressing mode we're going to use. */ | |
1833 | gcc_assert (first <= 32768); | |
1834 | ||
1835 | /* Step 1: round SIZE to the previous multiple of the interval. */ | |
1836 | ||
1837 | rounded_size = ROUND_DOWN (size, PROBE_INTERVAL); | |
1838 | ||
1839 | ||
1840 | /* Step 2: compute initial and final value of the loop counter. */ | |
1841 | ||
1842 | /* TEST_ADDR = SP + FIRST. */ | |
1843 | emit_insn (gen_rtx_SET (r12, plus_constant (Pmode, stack_pointer_rtx, | |
1844 | -first))); | |
1845 | ||
1846 | /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */ | |
1847 | if (rounded_size > 32768) | |
1848 | { | |
1849 | emit_move_insn (r0, GEN_INT (-rounded_size)); | |
1850 | emit_insn (gen_rtx_SET (r0, gen_rtx_PLUS (Pmode, r12, r0))); | |
1851 | } | |
1852 | else | |
1853 | emit_insn (gen_rtx_SET (r0, plus_constant (Pmode, r12, | |
1854 | -rounded_size))); | |
1855 | ||
1856 | ||
1857 | /* Step 3: the loop | |
1858 | ||
1859 | do | |
1860 | { | |
1861 | TEST_ADDR = TEST_ADDR + PROBE_INTERVAL | |
1862 | probe at TEST_ADDR | |
1863 | } | |
1864 | while (TEST_ADDR != LAST_ADDR) | |
1865 | ||
1866 | probes at FIRST + N * PROBE_INTERVAL for values of N from 1 | |
1867 | until it is equal to ROUNDED_SIZE. */ | |
1868 | ||
1869 | if (TARGET_64BIT) | |
1870 | emit_insn (gen_probe_stack_rangedi (r12, r12, stack_pointer_rtx, r0)); | |
1871 | else | |
1872 | emit_insn (gen_probe_stack_rangesi (r12, r12, stack_pointer_rtx, r0)); | |
1873 | ||
1874 | ||
1875 | /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time | |
1876 | that SIZE is equal to ROUNDED_SIZE. */ | |
1877 | ||
1878 | if (size != rounded_size) | |
1879 | emit_stack_probe (plus_constant (Pmode, r12, rounded_size - size)); | |
1880 | } | |
1881 | } | |
1882 | ||
1883 | /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are | |
1884 | addresses, not offsets. */ | |
1885 | ||
1886 | static const char * | |
1887 | output_probe_stack_range_1 (rtx reg1, rtx reg2) | |
1888 | { | |
1889 | static int labelno = 0; | |
1890 | char loop_lab[32]; | |
1891 | rtx xops[2]; | |
1892 | ||
1893 | ASM_GENERATE_INTERNAL_LABEL (loop_lab, "LPSRL", labelno++); | |
1894 | ||
1895 | /* Loop. */ | |
1896 | ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, loop_lab); | |
1897 | ||
1898 | /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */ | |
1899 | xops[0] = reg1; | |
1900 | xops[1] = GEN_INT (-PROBE_INTERVAL); | |
1901 | output_asm_insn ("addi %0,%0,%1", xops); | |
1902 | ||
1903 | /* Probe at TEST_ADDR. */ | |
1904 | xops[1] = gen_rtx_REG (Pmode, 0); | |
1905 | output_asm_insn ("stw %1,0(%0)", xops); | |
1906 | ||
1907 | /* Test if TEST_ADDR == LAST_ADDR. */ | |
1908 | xops[1] = reg2; | |
1909 | if (TARGET_64BIT) | |
1910 | output_asm_insn ("cmpd 0,%0,%1", xops); | |
1911 | else | |
1912 | output_asm_insn ("cmpw 0,%0,%1", xops); | |
1913 | ||
1914 | /* Branch. */ | |
1915 | fputs ("\tbne 0,", asm_out_file); | |
1916 | assemble_name_raw (asm_out_file, loop_lab); | |
1917 | fputc ('\n', asm_out_file); | |
1918 | ||
1919 | return ""; | |
1920 | } | |
1921 | ||
1922 | /* This function is called when rs6000_frame_related is processing | |
1923 | SETs within a PARALLEL, and returns whether the REGNO save ought to | |
1924 | be marked RTX_FRAME_RELATED_P. The PARALLELs involved are those | |
1925 | for out-of-line register save functions, store multiple, and the | |
1926 | Darwin world_save. They may contain registers that don't really | |
1927 | need saving. */ | |
1928 | ||
1929 | static bool | |
1930 | interesting_frame_related_regno (unsigned int regno) | |
1931 | { | |
1932 | /* Saves apparently of r0 are actually saving LR. It doesn't make | |
1933 | sense to substitute the regno here to test save_reg_p (LR_REGNO). | |
e53b6e56 | 1934 | We *know* LR needs saving, and dwarf2cfi.cc is able to deduce that |
2c04f847 BS |
1935 | (set (mem) (r0)) is saving LR from a prior (set (r0) (lr)) marked |
1936 | as frame related. */ | |
1937 | if (regno == 0) | |
1938 | return true; | |
1939 | /* If we see CR2 then we are here on a Darwin world save. Saves of | |
1940 | CR2 signify the whole CR is being saved. This is a long-standing | |
1941 | ABI wart fixed by ELFv2. As for r0/lr there is no need to check | |
1942 | that CR needs to be saved. */ | |
1943 | if (regno == CR2_REGNO) | |
1944 | return true; | |
1945 | /* Omit frame info for any user-defined global regs. If frame info | |
1946 | is supplied for them, frame unwinding will restore a user reg. | |
1947 | Also omit frame info for any reg we don't need to save, as that | |
1948 | bloats frame info and can cause problems with shrink wrapping. | |
1949 | Since global regs won't be seen as needing to be saved, both of | |
1950 | these conditions are covered by save_reg_p. */ | |
1951 | return save_reg_p (regno); | |
1952 | } | |
1953 | ||
1954 | /* Probe a range of stack addresses from REG1 to REG3 inclusive. These are | |
1955 | addresses, not offsets. | |
1956 | ||
1957 | REG2 contains the backchain that must be stored into *sp at each allocation. | |
1958 | ||
1959 | This is subtly different than the Ada probing above in that it tries hard | |
1960 | to prevent attacks that jump the stack guard. Thus, it is never allowed | |
1961 | to allocate more than PROBE_INTERVAL bytes of stack space without a | |
1962 | suitable probe. */ | |
1963 | ||
1964 | static const char * | |
1965 | output_probe_stack_range_stack_clash (rtx reg1, rtx reg2, rtx reg3) | |
1966 | { | |
1967 | static int labelno = 0; | |
1968 | char loop_lab[32]; | |
1969 | rtx xops[3]; | |
1970 | ||
1971 | HOST_WIDE_INT probe_interval = get_stack_clash_protection_probe_interval (); | |
1972 | ||
1973 | ASM_GENERATE_INTERNAL_LABEL (loop_lab, "LPSRL", labelno++); | |
1974 | ||
1975 | ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, loop_lab); | |
1976 | ||
1977 | /* This allocates and probes. */ | |
1978 | xops[0] = reg1; | |
1979 | xops[1] = reg2; | |
1980 | xops[2] = GEN_INT (-probe_interval); | |
1981 | if (TARGET_64BIT) | |
1982 | output_asm_insn ("stdu %1,%2(%0)", xops); | |
1983 | else | |
1984 | output_asm_insn ("stwu %1,%2(%0)", xops); | |
1985 | ||
1986 | /* Jump to LOOP_LAB if TEST_ADDR != LAST_ADDR. */ | |
1987 | xops[0] = reg1; | |
1988 | xops[1] = reg3; | |
1989 | if (TARGET_64BIT) | |
1990 | output_asm_insn ("cmpd 0,%0,%1", xops); | |
1991 | else | |
1992 | output_asm_insn ("cmpw 0,%0,%1", xops); | |
1993 | ||
1994 | fputs ("\tbne 0,", asm_out_file); | |
1995 | assemble_name_raw (asm_out_file, loop_lab); | |
1996 | fputc ('\n', asm_out_file); | |
1997 | ||
1998 | return ""; | |
1999 | } | |
2000 | ||
2001 | /* Wrapper around the output_probe_stack_range routines. */ | |
2002 | const char * | |
2003 | output_probe_stack_range (rtx reg1, rtx reg2, rtx reg3) | |
2004 | { | |
2005 | if (flag_stack_clash_protection) | |
2006 | return output_probe_stack_range_stack_clash (reg1, reg2, reg3); | |
2007 | else | |
2008 | return output_probe_stack_range_1 (reg1, reg3); | |
2009 | } | |
2010 | ||
2011 | /* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced | |
2012 | with (plus:P (reg 1) VAL), and with REG2 replaced with REPL2 if REG2 | |
2013 | is not NULL. It would be nice if dwarf2out_frame_debug_expr could | |
2014 | deduce these equivalences by itself so it wasn't necessary to hold | |
2015 | its hand so much. Don't be tempted to always supply d2_f_d_e with | |
2016 | the actual cfa register, ie. r31 when we are using a hard frame | |
2017 | pointer. That fails when saving regs off r1, and sched moves the | |
2018 | r31 setup past the reg saves. */ | |
2019 | ||
2020 | static rtx_insn * | |
2021 | rs6000_frame_related (rtx_insn *insn, rtx reg, HOST_WIDE_INT val, | |
2022 | rtx reg2, rtx repl2) | |
2023 | { | |
2024 | rtx repl; | |
2025 | ||
2026 | if (REGNO (reg) == STACK_POINTER_REGNUM) | |
2027 | { | |
2028 | gcc_checking_assert (val == 0); | |
2029 | repl = NULL_RTX; | |
2030 | } | |
2031 | else | |
2032 | repl = gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, STACK_POINTER_REGNUM), | |
2033 | GEN_INT (val)); | |
2034 | ||
2035 | rtx pat = PATTERN (insn); | |
2036 | if (!repl && !reg2) | |
2037 | { | |
2038 | /* No need for any replacement. Just set RTX_FRAME_RELATED_P. */ | |
2039 | if (GET_CODE (pat) == PARALLEL) | |
2040 | for (int i = 0; i < XVECLEN (pat, 0); i++) | |
2041 | if (GET_CODE (XVECEXP (pat, 0, i)) == SET) | |
2042 | { | |
2043 | rtx set = XVECEXP (pat, 0, i); | |
2044 | ||
2045 | if (!REG_P (SET_SRC (set)) | |
2046 | || interesting_frame_related_regno (REGNO (SET_SRC (set)))) | |
2047 | RTX_FRAME_RELATED_P (set) = 1; | |
2048 | } | |
2049 | RTX_FRAME_RELATED_P (insn) = 1; | |
2050 | return insn; | |
2051 | } | |
2052 | ||
2053 | /* We expect that 'pat' is either a SET or a PARALLEL containing | |
2054 | SETs (and possibly other stuff). In a PARALLEL, all the SETs | |
2055 | are important so they all have to be marked RTX_FRAME_RELATED_P. | |
2056 | Call simplify_replace_rtx on the SETs rather than the whole insn | |
2057 | so as to leave the other stuff alone (for example USE of r12). */ | |
2058 | ||
2059 | set_used_flags (pat); | |
2060 | if (GET_CODE (pat) == SET) | |
2061 | { | |
2062 | if (repl) | |
2063 | pat = simplify_replace_rtx (pat, reg, repl); | |
2064 | if (reg2) | |
2065 | pat = simplify_replace_rtx (pat, reg2, repl2); | |
2066 | } | |
2067 | else if (GET_CODE (pat) == PARALLEL) | |
2068 | { | |
2069 | pat = shallow_copy_rtx (pat); | |
2070 | XVEC (pat, 0) = shallow_copy_rtvec (XVEC (pat, 0)); | |
2071 | ||
2072 | for (int i = 0; i < XVECLEN (pat, 0); i++) | |
2073 | if (GET_CODE (XVECEXP (pat, 0, i)) == SET) | |
2074 | { | |
2075 | rtx set = XVECEXP (pat, 0, i); | |
2076 | ||
2077 | if (repl) | |
2078 | set = simplify_replace_rtx (set, reg, repl); | |
2079 | if (reg2) | |
2080 | set = simplify_replace_rtx (set, reg2, repl2); | |
2081 | XVECEXP (pat, 0, i) = set; | |
2082 | ||
2083 | if (!REG_P (SET_SRC (set)) | |
2084 | || interesting_frame_related_regno (REGNO (SET_SRC (set)))) | |
2085 | RTX_FRAME_RELATED_P (set) = 1; | |
2086 | } | |
2087 | } | |
2088 | else | |
2089 | gcc_unreachable (); | |
2090 | ||
2091 | RTX_FRAME_RELATED_P (insn) = 1; | |
2092 | add_reg_note (insn, REG_FRAME_RELATED_EXPR, copy_rtx_if_shared (pat)); | |
2093 | ||
2094 | return insn; | |
2095 | } | |
2096 | ||
2097 | /* Returns an insn that has a vrsave set operation with the | |
2098 | appropriate CLOBBERs. */ | |
2099 | ||
2100 | static rtx | |
2101 | generate_set_vrsave (rtx reg, rs6000_stack_t *info, int epiloguep) | |
2102 | { | |
2103 | int nclobs, i; | |
2104 | rtx insn, clobs[TOTAL_ALTIVEC_REGS + 1]; | |
2105 | rtx vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO); | |
2106 | ||
2107 | clobs[0] | |
2108 | = gen_rtx_SET (vrsave, | |
2109 | gen_rtx_UNSPEC_VOLATILE (SImode, | |
2110 | gen_rtvec (2, reg, vrsave), | |
2111 | UNSPECV_SET_VRSAVE)); | |
2112 | ||
2113 | nclobs = 1; | |
2114 | ||
2115 | /* We need to clobber the registers in the mask so the scheduler | |
2116 | does not move sets to VRSAVE before sets of AltiVec registers. | |
2117 | ||
2118 | However, if the function receives nonlocal gotos, reload will set | |
2119 | all call saved registers live. We will end up with: | |
2120 | ||
2121 | (set (reg 999) (mem)) | |
2122 | (parallel [ (set (reg vrsave) (unspec blah)) | |
2123 | (clobber (reg 999))]) | |
2124 | ||
2125 | The clobber will cause the store into reg 999 to be dead, and | |
2126 | flow will attempt to delete an epilogue insn. In this case, we | |
2127 | need an unspec use/set of the register. */ | |
2128 | ||
2129 | for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i) | |
2130 | if (info->vrsave_mask & ALTIVEC_REG_BIT (i)) | |
2131 | { | |
a365fa06 | 2132 | if (!epiloguep || call_used_or_fixed_reg_p (i)) |
2c04f847 BS |
2133 | clobs[nclobs++] = gen_hard_reg_clobber (V4SImode, i); |
2134 | else | |
2135 | { | |
2136 | rtx reg = gen_rtx_REG (V4SImode, i); | |
2137 | ||
2138 | clobs[nclobs++] | |
2139 | = gen_rtx_SET (reg, | |
2140 | gen_rtx_UNSPEC (V4SImode, | |
2141 | gen_rtvec (1, reg), 27)); | |
2142 | } | |
2143 | } | |
2144 | ||
2145 | insn = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (nclobs)); | |
2146 | ||
2147 | for (i = 0; i < nclobs; ++i) | |
2148 | XVECEXP (insn, 0, i) = clobs[i]; | |
2149 | ||
2150 | return insn; | |
2151 | } | |
2152 | ||
2153 | static rtx | |
2154 | gen_frame_set (rtx reg, rtx frame_reg, int offset, bool store) | |
2155 | { | |
2156 | rtx addr, mem; | |
2157 | ||
2158 | addr = gen_rtx_PLUS (Pmode, frame_reg, GEN_INT (offset)); | |
2159 | mem = gen_frame_mem (GET_MODE (reg), addr); | |
2160 | return gen_rtx_SET (store ? mem : reg, store ? reg : mem); | |
2161 | } | |
2162 | ||
2163 | static rtx | |
2164 | gen_frame_load (rtx reg, rtx frame_reg, int offset) | |
2165 | { | |
2166 | return gen_frame_set (reg, frame_reg, offset, false); | |
2167 | } | |
2168 | ||
2169 | static rtx | |
2170 | gen_frame_store (rtx reg, rtx frame_reg, int offset) | |
2171 | { | |
2172 | return gen_frame_set (reg, frame_reg, offset, true); | |
2173 | } | |
2174 | ||
2175 | /* Save a register into the frame, and emit RTX_FRAME_RELATED_P notes. | |
2176 | Save REGNO into [FRAME_REG + OFFSET] in mode MODE. */ | |
2177 | ||
2178 | static rtx_insn * | |
2179 | emit_frame_save (rtx frame_reg, machine_mode mode, | |
2180 | unsigned int regno, int offset, HOST_WIDE_INT frame_reg_to_sp) | |
2181 | { | |
2182 | rtx reg; | |
2183 | ||
2184 | /* Some cases that need register indexed addressing. */ | |
2185 | gcc_checking_assert (!(TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode)) | |
2186 | || (TARGET_VSX && ALTIVEC_OR_VSX_VECTOR_MODE (mode))); | |
2187 | ||
2188 | reg = gen_rtx_REG (mode, regno); | |
2189 | rtx_insn *insn = emit_insn (gen_frame_store (reg, frame_reg, offset)); | |
2190 | return rs6000_frame_related (insn, frame_reg, frame_reg_to_sp, | |
2191 | NULL_RTX, NULL_RTX); | |
2192 | } | |
2193 | ||
2194 | /* Emit an offset memory reference suitable for a frame store, while | |
2195 | converting to a valid addressing mode. */ | |
2196 | ||
2197 | static rtx | |
2198 | gen_frame_mem_offset (machine_mode mode, rtx reg, int offset) | |
2199 | { | |
2200 | return gen_frame_mem (mode, gen_rtx_PLUS (Pmode, reg, GEN_INT (offset))); | |
2201 | } | |
2202 | ||
2203 | #ifndef TARGET_FIX_AND_CONTINUE | |
2204 | #define TARGET_FIX_AND_CONTINUE 0 | |
2205 | #endif | |
2206 | ||
2207 | /* It's really GPR 13 or 14, FPR 14 and VR 20. We need the smallest. */ | |
2208 | #define FIRST_SAVRES_REGISTER FIRST_SAVED_GP_REGNO | |
2209 | #define LAST_SAVRES_REGISTER 31 | |
2210 | #define N_SAVRES_REGISTERS (LAST_SAVRES_REGISTER - FIRST_SAVRES_REGISTER + 1) | |
2211 | ||
2212 | enum { | |
2213 | SAVRES_LR = 0x1, | |
2214 | SAVRES_SAVE = 0x2, | |
2215 | SAVRES_REG = 0x0c, | |
2216 | SAVRES_GPR = 0, | |
2217 | SAVRES_FPR = 4, | |
2218 | SAVRES_VR = 8 | |
2219 | }; | |
2220 | ||
2221 | static GTY(()) rtx savres_routine_syms[N_SAVRES_REGISTERS][12]; | |
2222 | ||
2223 | /* Temporary holding space for an out-of-line register save/restore | |
2224 | routine name. */ | |
2225 | static char savres_routine_name[30]; | |
2226 | ||
2227 | /* Return the name for an out-of-line register save/restore routine. | |
2228 | We are saving/restoring GPRs if GPR is true. */ | |
2229 | ||
2230 | static char * | |
2231 | rs6000_savres_routine_name (int regno, int sel) | |
2232 | { | |
2233 | const char *prefix = ""; | |
2234 | const char *suffix = ""; | |
2235 | ||
2236 | /* Different targets are supposed to define | |
2237 | {SAVE,RESTORE}_FP_{PREFIX,SUFFIX} with the idea that the needed | |
2238 | routine name could be defined with: | |
2239 | ||
2240 | sprintf (name, "%s%d%s", SAVE_FP_PREFIX, regno, SAVE_FP_SUFFIX) | |
2241 | ||
2242 | This is a nice idea in practice, but in reality, things are | |
2243 | complicated in several ways: | |
2244 | ||
2245 | - ELF targets have save/restore routines for GPRs. | |
2246 | ||
2247 | - PPC64 ELF targets have routines for save/restore of GPRs that | |
2248 | differ in what they do with the link register, so having a set | |
2249 | prefix doesn't work. (We only use one of the save routines at | |
2250 | the moment, though.) | |
2251 | ||
2252 | - PPC32 elf targets have "exit" versions of the restore routines | |
2253 | that restore the link register and can save some extra space. | |
2254 | These require an extra suffix. (There are also "tail" versions | |
2255 | of the restore routines and "GOT" versions of the save routines, | |
2256 | but we don't generate those at present. Same problems apply, | |
2257 | though.) | |
2258 | ||
2259 | We deal with all this by synthesizing our own prefix/suffix and | |
2260 | using that for the simple sprintf call shown above. */ | |
2261 | if (DEFAULT_ABI == ABI_V4) | |
2262 | { | |
2263 | if (TARGET_64BIT) | |
2264 | goto aix_names; | |
2265 | ||
2266 | if ((sel & SAVRES_REG) == SAVRES_GPR) | |
2267 | prefix = (sel & SAVRES_SAVE) ? "_savegpr_" : "_restgpr_"; | |
2268 | else if ((sel & SAVRES_REG) == SAVRES_FPR) | |
2269 | prefix = (sel & SAVRES_SAVE) ? "_savefpr_" : "_restfpr_"; | |
2270 | else if ((sel & SAVRES_REG) == SAVRES_VR) | |
2271 | prefix = (sel & SAVRES_SAVE) ? "_savevr_" : "_restvr_"; | |
2272 | else | |
2273 | abort (); | |
2274 | ||
2275 | if ((sel & SAVRES_LR)) | |
2276 | suffix = "_x"; | |
2277 | } | |
2278 | else if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2) | |
2279 | { | |
2280 | #if !defined (POWERPC_LINUX) && !defined (POWERPC_FREEBSD) | |
2281 | /* No out-of-line save/restore routines for GPRs on AIX. */ | |
2282 | gcc_assert (!TARGET_AIX || (sel & SAVRES_REG) != SAVRES_GPR); | |
2283 | #endif | |
2284 | ||
2285 | aix_names: | |
2286 | if ((sel & SAVRES_REG) == SAVRES_GPR) | |
2287 | prefix = ((sel & SAVRES_SAVE) | |
2288 | ? ((sel & SAVRES_LR) ? "_savegpr0_" : "_savegpr1_") | |
2289 | : ((sel & SAVRES_LR) ? "_restgpr0_" : "_restgpr1_")); | |
2290 | else if ((sel & SAVRES_REG) == SAVRES_FPR) | |
2291 | { | |
2292 | #if defined (POWERPC_LINUX) || defined (POWERPC_FREEBSD) | |
2293 | if ((sel & SAVRES_LR)) | |
2294 | prefix = ((sel & SAVRES_SAVE) ? "_savefpr_" : "_restfpr_"); | |
2295 | else | |
2296 | #endif | |
2297 | { | |
2298 | prefix = (sel & SAVRES_SAVE) ? SAVE_FP_PREFIX : RESTORE_FP_PREFIX; | |
2299 | suffix = (sel & SAVRES_SAVE) ? SAVE_FP_SUFFIX : RESTORE_FP_SUFFIX; | |
2300 | } | |
2301 | } | |
2302 | else if ((sel & SAVRES_REG) == SAVRES_VR) | |
2303 | prefix = (sel & SAVRES_SAVE) ? "_savevr_" : "_restvr_"; | |
2304 | else | |
2305 | abort (); | |
2306 | } | |
2307 | ||
2308 | if (DEFAULT_ABI == ABI_DARWIN) | |
2309 | { | |
2310 | /* The Darwin approach is (slightly) different, in order to be | |
2311 | compatible with code generated by the system toolchain. There is a | |
2312 | single symbol for the start of save sequence, and the code here | |
2313 | embeds an offset into that code on the basis of the first register | |
2314 | to be saved. */ | |
2315 | prefix = (sel & SAVRES_SAVE) ? "save" : "rest" ; | |
2316 | if ((sel & SAVRES_REG) == SAVRES_GPR) | |
2317 | sprintf (savres_routine_name, "*%sGPR%s%s%.0d ; %s r%d-r31", prefix, | |
2318 | ((sel & SAVRES_LR) ? "x" : ""), (regno == 13 ? "" : "+"), | |
2319 | (regno - 13) * 4, prefix, regno); | |
2320 | else if ((sel & SAVRES_REG) == SAVRES_FPR) | |
2321 | sprintf (savres_routine_name, "*%sFP%s%.0d ; %s f%d-f31", prefix, | |
2322 | (regno == 14 ? "" : "+"), (regno - 14) * 4, prefix, regno); | |
2323 | else if ((sel & SAVRES_REG) == SAVRES_VR) | |
2324 | sprintf (savres_routine_name, "*%sVEC%s%.0d ; %s v%d-v31", prefix, | |
2325 | (regno == 20 ? "" : "+"), (regno - 20) * 8, prefix, regno); | |
2326 | else | |
2327 | abort (); | |
2328 | } | |
2329 | else | |
2330 | sprintf (savres_routine_name, "%s%d%s", prefix, regno, suffix); | |
2331 | ||
2332 | return savres_routine_name; | |
2333 | } | |
2334 | ||
2335 | /* Return an RTL SYMBOL_REF for an out-of-line register save/restore routine. | |
2336 | We are saving/restoring GPRs if GPR is true. */ | |
2337 | ||
2338 | static rtx | |
2339 | rs6000_savres_routine_sym (rs6000_stack_t *info, int sel) | |
2340 | { | |
2341 | int regno = ((sel & SAVRES_REG) == SAVRES_GPR | |
2342 | ? info->first_gp_reg_save | |
2343 | : (sel & SAVRES_REG) == SAVRES_FPR | |
2344 | ? info->first_fp_reg_save - 32 | |
2345 | : (sel & SAVRES_REG) == SAVRES_VR | |
2346 | ? info->first_altivec_reg_save - FIRST_ALTIVEC_REGNO | |
2347 | : -1); | |
2348 | rtx sym; | |
2349 | int select = sel; | |
2350 | ||
2351 | /* Don't generate bogus routine names. */ | |
2352 | gcc_assert (FIRST_SAVRES_REGISTER <= regno | |
2353 | && regno <= LAST_SAVRES_REGISTER | |
2354 | && select >= 0 && select <= 12); | |
2355 | ||
2356 | sym = savres_routine_syms[regno-FIRST_SAVRES_REGISTER][select]; | |
2357 | ||
2358 | if (sym == NULL) | |
2359 | { | |
2360 | char *name; | |
2361 | ||
2362 | name = rs6000_savres_routine_name (regno, sel); | |
2363 | ||
2364 | sym = savres_routine_syms[regno-FIRST_SAVRES_REGISTER][select] | |
2365 | = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name)); | |
2366 | SYMBOL_REF_FLAGS (sym) |= SYMBOL_FLAG_FUNCTION; | |
2367 | } | |
2368 | ||
2369 | return sym; | |
2370 | } | |
2371 | ||
2372 | /* Emit a sequence of insns, including a stack tie if needed, for | |
2373 | resetting the stack pointer. If UPDT_REGNO is not 1, then don't | |
2374 | reset the stack pointer, but move the base of the frame into | |
2375 | reg UPDT_REGNO for use by out-of-line register restore routines. */ | |
2376 | ||
2377 | static rtx | |
2378 | rs6000_emit_stack_reset (rtx frame_reg_rtx, HOST_WIDE_INT frame_off, | |
2379 | unsigned updt_regno) | |
2380 | { | |
2381 | /* If there is nothing to do, don't do anything. */ | |
2382 | if (frame_off == 0 && REGNO (frame_reg_rtx) == updt_regno) | |
2383 | return NULL_RTX; | |
2384 | ||
2385 | rtx updt_reg_rtx = gen_rtx_REG (Pmode, updt_regno); | |
2386 | ||
2387 | /* This blockage is needed so that sched doesn't decide to move | |
2388 | the sp change before the register restores. */ | |
2389 | if (DEFAULT_ABI == ABI_V4) | |
2390 | return emit_insn (gen_stack_restore_tie (updt_reg_rtx, frame_reg_rtx, | |
2391 | GEN_INT (frame_off))); | |
2392 | ||
2393 | /* If we are restoring registers out-of-line, we will be using the | |
2394 | "exit" variants of the restore routines, which will reset the | |
2395 | stack for us. But we do need to point updt_reg into the | |
2396 | right place for those routines. */ | |
2397 | if (frame_off != 0) | |
2398 | return emit_insn (gen_add3_insn (updt_reg_rtx, | |
2399 | frame_reg_rtx, GEN_INT (frame_off))); | |
2400 | else | |
2401 | return emit_move_insn (updt_reg_rtx, frame_reg_rtx); | |
2402 | ||
2403 | return NULL_RTX; | |
2404 | } | |
2405 | ||
2406 | /* Return the register number used as a pointer by out-of-line | |
2407 | save/restore functions. */ | |
2408 | ||
2409 | static inline unsigned | |
2410 | ptr_regno_for_savres (int sel) | |
2411 | { | |
2412 | if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2) | |
2413 | return (sel & SAVRES_REG) == SAVRES_FPR || (sel & SAVRES_LR) ? 1 : 12; | |
2414 | return DEFAULT_ABI == ABI_DARWIN && (sel & SAVRES_REG) == SAVRES_FPR ? 1 : 11; | |
2415 | } | |
2416 | ||
2417 | /* Construct a parallel rtx describing the effect of a call to an | |
2418 | out-of-line register save/restore routine, and emit the insn | |
2419 | or jump_insn as appropriate. */ | |
2420 | ||
2421 | static rtx_insn * | |
2422 | rs6000_emit_savres_rtx (rs6000_stack_t *info, | |
2423 | rtx frame_reg_rtx, int save_area_offset, int lr_offset, | |
2424 | machine_mode reg_mode, int sel) | |
2425 | { | |
2426 | int i; | |
2427 | int offset, start_reg, end_reg, n_regs, use_reg; | |
2428 | int reg_size = GET_MODE_SIZE (reg_mode); | |
2429 | rtx sym; | |
2430 | rtvec p; | |
2431 | rtx par; | |
2432 | rtx_insn *insn; | |
2433 | ||
2434 | offset = 0; | |
2435 | start_reg = ((sel & SAVRES_REG) == SAVRES_GPR | |
2436 | ? info->first_gp_reg_save | |
2437 | : (sel & SAVRES_REG) == SAVRES_FPR | |
2438 | ? info->first_fp_reg_save | |
2439 | : (sel & SAVRES_REG) == SAVRES_VR | |
2440 | ? info->first_altivec_reg_save | |
2441 | : -1); | |
2442 | end_reg = ((sel & SAVRES_REG) == SAVRES_GPR | |
2443 | ? 32 | |
2444 | : (sel & SAVRES_REG) == SAVRES_FPR | |
2445 | ? 64 | |
2446 | : (sel & SAVRES_REG) == SAVRES_VR | |
2447 | ? LAST_ALTIVEC_REGNO + 1 | |
2448 | : -1); | |
2449 | n_regs = end_reg - start_reg; | |
2450 | p = rtvec_alloc (3 + ((sel & SAVRES_LR) ? 1 : 0) | |
2451 | + ((sel & SAVRES_REG) == SAVRES_VR ? 1 : 0) | |
2452 | + n_regs); | |
2453 | ||
2454 | if (!(sel & SAVRES_SAVE) && (sel & SAVRES_LR)) | |
2455 | RTVEC_ELT (p, offset++) = ret_rtx; | |
2456 | ||
2457 | RTVEC_ELT (p, offset++) = gen_hard_reg_clobber (Pmode, LR_REGNO); | |
2458 | ||
2459 | sym = rs6000_savres_routine_sym (info, sel); | |
2460 | RTVEC_ELT (p, offset++) = gen_rtx_USE (VOIDmode, sym); | |
2461 | ||
2462 | use_reg = ptr_regno_for_savres (sel); | |
2463 | if ((sel & SAVRES_REG) == SAVRES_VR) | |
2464 | { | |
2465 | /* Vector regs are saved/restored using [reg+reg] addressing. */ | |
2466 | RTVEC_ELT (p, offset++) = gen_hard_reg_clobber (Pmode, use_reg); | |
2467 | RTVEC_ELT (p, offset++) | |
2468 | = gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, 0)); | |
2469 | } | |
2470 | else | |
2471 | RTVEC_ELT (p, offset++) | |
2472 | = gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, use_reg)); | |
2473 | ||
2474 | for (i = 0; i < end_reg - start_reg; i++) | |
2475 | RTVEC_ELT (p, i + offset) | |
2476 | = gen_frame_set (gen_rtx_REG (reg_mode, start_reg + i), | |
2477 | frame_reg_rtx, save_area_offset + reg_size * i, | |
2478 | (sel & SAVRES_SAVE) != 0); | |
2479 | ||
2480 | if ((sel & SAVRES_SAVE) && (sel & SAVRES_LR)) | |
2481 | RTVEC_ELT (p, i + offset) | |
2482 | = gen_frame_store (gen_rtx_REG (Pmode, 0), frame_reg_rtx, lr_offset); | |
2483 | ||
2484 | par = gen_rtx_PARALLEL (VOIDmode, p); | |
2485 | ||
2486 | if (!(sel & SAVRES_SAVE) && (sel & SAVRES_LR)) | |
2487 | { | |
2488 | insn = emit_jump_insn (par); | |
2489 | JUMP_LABEL (insn) = ret_rtx; | |
2490 | } | |
2491 | else | |
2492 | insn = emit_insn (par); | |
2493 | return insn; | |
2494 | } | |
2495 | ||
2496 | /* Emit prologue code to store CR fields that need to be saved into REG. This | |
2497 | function should only be called when moving the non-volatile CRs to REG, it | |
2498 | is not a general purpose routine to move the entire set of CRs to REG. | |
2499 | Specifically, gen_prologue_movesi_from_cr() does not contain uses of the | |
2500 | volatile CRs. */ | |
2501 | ||
2502 | static void | |
2503 | rs6000_emit_prologue_move_from_cr (rtx reg) | |
2504 | { | |
2505 | /* Only the ELFv2 ABI allows storing only selected fields. */ | |
2506 | if (DEFAULT_ABI == ABI_ELFv2 && TARGET_MFCRF) | |
2507 | { | |
2508 | int i, cr_reg[8], count = 0; | |
2509 | ||
2510 | /* Collect CR fields that must be saved. */ | |
2511 | for (i = 0; i < 8; i++) | |
2512 | if (save_reg_p (CR0_REGNO + i)) | |
2513 | cr_reg[count++] = i; | |
2514 | ||
2515 | /* If it's just a single one, use mfcrf. */ | |
2516 | if (count == 1) | |
2517 | { | |
2518 | rtvec p = rtvec_alloc (1); | |
2519 | rtvec r = rtvec_alloc (2); | |
2520 | RTVEC_ELT (r, 0) = gen_rtx_REG (CCmode, CR0_REGNO + cr_reg[0]); | |
2521 | RTVEC_ELT (r, 1) = GEN_INT (1 << (7 - cr_reg[0])); | |
2522 | RTVEC_ELT (p, 0) | |
2523 | = gen_rtx_SET (reg, | |
2524 | gen_rtx_UNSPEC (SImode, r, UNSPEC_MOVESI_FROM_CR)); | |
2525 | ||
2526 | emit_insn (gen_rtx_PARALLEL (VOIDmode, p)); | |
2527 | return; | |
2528 | } | |
2529 | ||
2530 | /* ??? It might be better to handle count == 2 / 3 cases here | |
2531 | as well, using logical operations to combine the values. */ | |
2532 | } | |
2533 | ||
2534 | emit_insn (gen_prologue_movesi_from_cr (reg)); | |
2535 | } | |
2536 | ||
2537 | /* Return whether the split-stack arg pointer (r12) is used. */ | |
2538 | ||
2539 | static bool | |
2540 | split_stack_arg_pointer_used_p (void) | |
2541 | { | |
2542 | /* If the pseudo holding the arg pointer is no longer a pseudo, | |
2543 | then the arg pointer is used. */ | |
2544 | if (cfun->machine->split_stack_arg_pointer != NULL_RTX | |
2545 | && (!REG_P (cfun->machine->split_stack_arg_pointer) | |
2546 | || HARD_REGISTER_P (cfun->machine->split_stack_arg_pointer))) | |
2547 | return true; | |
2548 | ||
2549 | /* Unfortunately we also need to do some code scanning, since | |
2550 | r12 may have been substituted for the pseudo. */ | |
2551 | rtx_insn *insn; | |
2552 | basic_block bb = ENTRY_BLOCK_PTR_FOR_FN (cfun)->next_bb; | |
2553 | FOR_BB_INSNS (bb, insn) | |
2554 | if (NONDEBUG_INSN_P (insn)) | |
2555 | { | |
2556 | /* A call destroys r12. */ | |
2557 | if (CALL_P (insn)) | |
2558 | return false; | |
2559 | ||
2560 | df_ref use; | |
2561 | FOR_EACH_INSN_USE (use, insn) | |
2562 | { | |
2563 | rtx x = DF_REF_REG (use); | |
2564 | if (REG_P (x) && REGNO (x) == 12) | |
2565 | return true; | |
2566 | } | |
2567 | df_ref def; | |
2568 | FOR_EACH_INSN_DEF (def, insn) | |
2569 | { | |
2570 | rtx x = DF_REF_REG (def); | |
2571 | if (REG_P (x) && REGNO (x) == 12) | |
2572 | return false; | |
2573 | } | |
2574 | } | |
2575 | return bitmap_bit_p (DF_LR_OUT (bb), 12); | |
2576 | } | |
2577 | ||
2578 | /* Return whether we need to emit an ELFv2 global entry point prologue. */ | |
2579 | ||
2580 | bool | |
2581 | rs6000_global_entry_point_prologue_needed_p (void) | |
2582 | { | |
2583 | /* Only needed for the ELFv2 ABI. */ | |
2584 | if (DEFAULT_ABI != ABI_ELFv2) | |
2585 | return false; | |
2586 | ||
2587 | /* With -msingle-pic-base, we assume the whole program shares the same | |
2588 | TOC, so no global entry point prologues are needed anywhere. */ | |
2589 | if (TARGET_SINGLE_PIC_BASE) | |
2590 | return false; | |
2591 | ||
2592 | /* PC-relative functions never generate a global entry point prologue. */ | |
8c0f8755 | 2593 | if (rs6000_pcrel_p ()) |
2c04f847 BS |
2594 | return false; |
2595 | ||
2596 | /* Ensure we have a global entry point for thunks. ??? We could | |
2597 | avoid that if the target routine doesn't need a global entry point, | |
2598 | but we do not know whether this is the case at this point. */ | |
2599 | if (cfun->is_thunk) | |
2600 | return true; | |
2601 | ||
2602 | /* For regular functions, rs6000_emit_prologue sets this flag if the | |
2603 | routine ever uses the TOC pointer. */ | |
2604 | return cfun->machine->r2_setup_needed; | |
2605 | } | |
2606 | ||
2607 | /* Implement TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS. */ | |
2608 | sbitmap | |
2609 | rs6000_get_separate_components (void) | |
2610 | { | |
2611 | rs6000_stack_t *info = rs6000_stack_info (); | |
2612 | ||
2613 | if (WORLD_SAVE_P (info)) | |
2614 | return NULL; | |
2615 | ||
2616 | gcc_assert (!(info->savres_strategy & SAVE_MULTIPLE) | |
2617 | && !(info->savres_strategy & REST_MULTIPLE)); | |
2618 | ||
2619 | /* Component 0 is the save/restore of LR (done via GPR0). | |
2620 | Component 2 is the save of the TOC (GPR2). | |
2621 | Components 13..31 are the save/restore of GPR13..GPR31. | |
2622 | Components 46..63 are the save/restore of FPR14..FPR31. */ | |
2623 | ||
2624 | cfun->machine->n_components = 64; | |
2625 | ||
2626 | sbitmap components = sbitmap_alloc (cfun->machine->n_components); | |
2627 | bitmap_clear (components); | |
2628 | ||
2629 | int reg_size = TARGET_32BIT ? 4 : 8; | |
2630 | int fp_reg_size = 8; | |
2631 | ||
2632 | /* The GPRs we need saved to the frame. */ | |
2633 | if ((info->savres_strategy & SAVE_INLINE_GPRS) | |
2634 | && (info->savres_strategy & REST_INLINE_GPRS)) | |
2635 | { | |
2636 | int offset = info->gp_save_offset; | |
2637 | if (info->push_p) | |
2638 | offset += info->total_size; | |
2639 | ||
2640 | for (unsigned regno = info->first_gp_reg_save; regno < 32; regno++) | |
2641 | { | |
2642 | if (IN_RANGE (offset, -0x8000, 0x7fff) | |
2643 | && save_reg_p (regno)) | |
2644 | bitmap_set_bit (components, regno); | |
2645 | ||
2646 | offset += reg_size; | |
2647 | } | |
2648 | } | |
2649 | ||
2650 | /* Don't mess with the hard frame pointer. */ | |
2651 | if (frame_pointer_needed) | |
2652 | bitmap_clear_bit (components, HARD_FRAME_POINTER_REGNUM); | |
2653 | ||
2654 | /* Don't mess with the fixed TOC register. */ | |
2655 | if ((TARGET_TOC && TARGET_MINIMAL_TOC) | |
2656 | || (flag_pic == 1 && DEFAULT_ABI == ABI_V4) | |
2657 | || (flag_pic && DEFAULT_ABI == ABI_DARWIN)) | |
2658 | bitmap_clear_bit (components, RS6000_PIC_OFFSET_TABLE_REGNUM); | |
2659 | ||
2660 | /* The FPRs we need saved to the frame. */ | |
2661 | if ((info->savres_strategy & SAVE_INLINE_FPRS) | |
2662 | && (info->savres_strategy & REST_INLINE_FPRS)) | |
2663 | { | |
2664 | int offset = info->fp_save_offset; | |
2665 | if (info->push_p) | |
2666 | offset += info->total_size; | |
2667 | ||
2668 | for (unsigned regno = info->first_fp_reg_save; regno < 64; regno++) | |
2669 | { | |
2670 | if (IN_RANGE (offset, -0x8000, 0x7fff) && save_reg_p (regno)) | |
2671 | bitmap_set_bit (components, regno); | |
2672 | ||
2673 | offset += fp_reg_size; | |
2674 | } | |
2675 | } | |
2676 | ||
2677 | /* Optimize LR save and restore if we can. This is component 0. Any | |
2678 | out-of-line register save/restore routines need LR. */ | |
2679 | if (info->lr_save_p | |
2680 | && !(flag_pic && (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_DARWIN)) | |
2681 | && (info->savres_strategy & SAVE_INLINE_GPRS) | |
2682 | && (info->savres_strategy & REST_INLINE_GPRS) | |
2683 | && (info->savres_strategy & SAVE_INLINE_FPRS) | |
2684 | && (info->savres_strategy & REST_INLINE_FPRS) | |
2685 | && (info->savres_strategy & SAVE_INLINE_VRS) | |
2686 | && (info->savres_strategy & REST_INLINE_VRS)) | |
2687 | { | |
2688 | int offset = info->lr_save_offset; | |
2689 | if (info->push_p) | |
2690 | offset += info->total_size; | |
2691 | if (IN_RANGE (offset, -0x8000, 0x7fff)) | |
2692 | bitmap_set_bit (components, 0); | |
2693 | } | |
2694 | ||
2695 | /* Optimize saving the TOC. This is component 2. */ | |
2696 | if (cfun->machine->save_toc_in_prologue) | |
2697 | bitmap_set_bit (components, 2); | |
2698 | ||
2699 | return components; | |
2700 | } | |
2701 | ||
2702 | /* Implement TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB. */ | |
2703 | sbitmap | |
2704 | rs6000_components_for_bb (basic_block bb) | |
2705 | { | |
2706 | rs6000_stack_t *info = rs6000_stack_info (); | |
2707 | ||
2708 | bitmap in = DF_LIVE_IN (bb); | |
2709 | bitmap gen = &DF_LIVE_BB_INFO (bb)->gen; | |
2710 | bitmap kill = &DF_LIVE_BB_INFO (bb)->kill; | |
2711 | ||
2712 | sbitmap components = sbitmap_alloc (cfun->machine->n_components); | |
2713 | bitmap_clear (components); | |
2714 | ||
2715 | /* A register is used in a bb if it is in the IN, GEN, or KILL sets. */ | |
2716 | ||
2717 | /* GPRs. */ | |
2718 | for (unsigned regno = info->first_gp_reg_save; regno < 32; regno++) | |
2719 | if (bitmap_bit_p (in, regno) | |
2720 | || bitmap_bit_p (gen, regno) | |
2721 | || bitmap_bit_p (kill, regno)) | |
2722 | bitmap_set_bit (components, regno); | |
2723 | ||
2724 | /* FPRs. */ | |
2725 | for (unsigned regno = info->first_fp_reg_save; regno < 64; regno++) | |
2726 | if (bitmap_bit_p (in, regno) | |
2727 | || bitmap_bit_p (gen, regno) | |
2728 | || bitmap_bit_p (kill, regno)) | |
2729 | bitmap_set_bit (components, regno); | |
2730 | ||
2731 | /* The link register. */ | |
2732 | if (bitmap_bit_p (in, LR_REGNO) | |
2733 | || bitmap_bit_p (gen, LR_REGNO) | |
2734 | || bitmap_bit_p (kill, LR_REGNO)) | |
2735 | bitmap_set_bit (components, 0); | |
2736 | ||
2737 | /* The TOC save. */ | |
2738 | if (bitmap_bit_p (in, TOC_REGNUM) | |
2739 | || bitmap_bit_p (gen, TOC_REGNUM) | |
2740 | || bitmap_bit_p (kill, TOC_REGNUM)) | |
2741 | bitmap_set_bit (components, 2); | |
2742 | ||
2743 | return components; | |
2744 | } | |
2745 | ||
2746 | /* Implement TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS. */ | |
2747 | void | |
2748 | rs6000_disqualify_components (sbitmap components, edge e, | |
2749 | sbitmap edge_components, bool /*is_prologue*/) | |
2750 | { | |
2751 | /* Our LR pro/epilogue code moves LR via R0, so R0 had better not be | |
2752 | live where we want to place that code. */ | |
2753 | if (bitmap_bit_p (edge_components, 0) | |
2754 | && bitmap_bit_p (DF_LIVE_IN (e->dest), 0)) | |
2755 | { | |
2756 | if (dump_file) | |
2757 | fprintf (dump_file, "Disqualifying LR because GPR0 is live " | |
2758 | "on entry to bb %d\n", e->dest->index); | |
2759 | bitmap_clear_bit (components, 0); | |
2760 | } | |
2761 | } | |
2762 | ||
2763 | /* Implement TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS. */ | |
2764 | void | |
2765 | rs6000_emit_prologue_components (sbitmap components) | |
2766 | { | |
2767 | rs6000_stack_t *info = rs6000_stack_info (); | |
f6955089 XL |
2768 | rtx ptr_reg = gen_rtx_REG (Pmode, frame_pointer_needed_indeed |
2769 | ? HARD_FRAME_POINTER_REGNUM | |
2770 | : STACK_POINTER_REGNUM); | |
2c04f847 BS |
2771 | |
2772 | machine_mode reg_mode = Pmode; | |
2773 | int reg_size = TARGET_32BIT ? 4 : 8; | |
2774 | machine_mode fp_reg_mode = TARGET_HARD_FLOAT ? DFmode : SFmode; | |
2775 | int fp_reg_size = 8; | |
2776 | ||
2777 | /* Prologue for LR. */ | |
2778 | if (bitmap_bit_p (components, 0)) | |
2779 | { | |
2780 | rtx lr = gen_rtx_REG (reg_mode, LR_REGNO); | |
2781 | rtx reg = gen_rtx_REG (reg_mode, 0); | |
2782 | rtx_insn *insn = emit_move_insn (reg, lr); | |
2783 | RTX_FRAME_RELATED_P (insn) = 1; | |
2784 | add_reg_note (insn, REG_CFA_REGISTER, gen_rtx_SET (reg, lr)); | |
2785 | ||
2786 | int offset = info->lr_save_offset; | |
2787 | if (info->push_p) | |
2788 | offset += info->total_size; | |
2789 | ||
2790 | insn = emit_insn (gen_frame_store (reg, ptr_reg, offset)); | |
2791 | RTX_FRAME_RELATED_P (insn) = 1; | |
2792 | rtx mem = copy_rtx (SET_DEST (single_set (insn))); | |
2793 | add_reg_note (insn, REG_CFA_OFFSET, gen_rtx_SET (mem, lr)); | |
2794 | } | |
2795 | ||
2796 | /* Prologue for TOC. */ | |
2797 | if (bitmap_bit_p (components, 2)) | |
2798 | { | |
2799 | rtx reg = gen_rtx_REG (reg_mode, TOC_REGNUM); | |
2800 | rtx sp_reg = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM); | |
2801 | emit_insn (gen_frame_store (reg, sp_reg, RS6000_TOC_SAVE_SLOT)); | |
2802 | } | |
2803 | ||
2804 | /* Prologue for the GPRs. */ | |
2805 | int offset = info->gp_save_offset; | |
2806 | if (info->push_p) | |
2807 | offset += info->total_size; | |
2808 | ||
2809 | for (int i = info->first_gp_reg_save; i < 32; i++) | |
2810 | { | |
2811 | if (bitmap_bit_p (components, i)) | |
2812 | { | |
2813 | rtx reg = gen_rtx_REG (reg_mode, i); | |
2814 | rtx_insn *insn = emit_insn (gen_frame_store (reg, ptr_reg, offset)); | |
2815 | RTX_FRAME_RELATED_P (insn) = 1; | |
2816 | rtx set = copy_rtx (single_set (insn)); | |
2817 | add_reg_note (insn, REG_CFA_OFFSET, set); | |
2818 | } | |
2819 | ||
2820 | offset += reg_size; | |
2821 | } | |
2822 | ||
2823 | /* Prologue for the FPRs. */ | |
2824 | offset = info->fp_save_offset; | |
2825 | if (info->push_p) | |
2826 | offset += info->total_size; | |
2827 | ||
2828 | for (int i = info->first_fp_reg_save; i < 64; i++) | |
2829 | { | |
2830 | if (bitmap_bit_p (components, i)) | |
2831 | { | |
2832 | rtx reg = gen_rtx_REG (fp_reg_mode, i); | |
2833 | rtx_insn *insn = emit_insn (gen_frame_store (reg, ptr_reg, offset)); | |
2834 | RTX_FRAME_RELATED_P (insn) = 1; | |
2835 | rtx set = copy_rtx (single_set (insn)); | |
2836 | add_reg_note (insn, REG_CFA_OFFSET, set); | |
2837 | } | |
2838 | ||
2839 | offset += fp_reg_size; | |
2840 | } | |
2841 | } | |
2842 | ||
2843 | /* Implement TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS. */ | |
2844 | void | |
2845 | rs6000_emit_epilogue_components (sbitmap components) | |
2846 | { | |
2847 | rs6000_stack_t *info = rs6000_stack_info (); | |
f6955089 XL |
2848 | rtx ptr_reg = gen_rtx_REG (Pmode, frame_pointer_needed_indeed |
2849 | ? HARD_FRAME_POINTER_REGNUM | |
2850 | : STACK_POINTER_REGNUM); | |
2c04f847 BS |
2851 | |
2852 | machine_mode reg_mode = Pmode; | |
2853 | int reg_size = TARGET_32BIT ? 4 : 8; | |
2854 | ||
2855 | machine_mode fp_reg_mode = TARGET_HARD_FLOAT ? DFmode : SFmode; | |
2856 | int fp_reg_size = 8; | |
2857 | ||
2858 | /* Epilogue for the FPRs. */ | |
2859 | int offset = info->fp_save_offset; | |
2860 | if (info->push_p) | |
2861 | offset += info->total_size; | |
2862 | ||
2863 | for (int i = info->first_fp_reg_save; i < 64; i++) | |
2864 | { | |
2865 | if (bitmap_bit_p (components, i)) | |
2866 | { | |
2867 | rtx reg = gen_rtx_REG (fp_reg_mode, i); | |
2868 | rtx_insn *insn = emit_insn (gen_frame_load (reg, ptr_reg, offset)); | |
2869 | RTX_FRAME_RELATED_P (insn) = 1; | |
2870 | add_reg_note (insn, REG_CFA_RESTORE, reg); | |
2871 | } | |
2872 | ||
2873 | offset += fp_reg_size; | |
2874 | } | |
2875 | ||
2876 | /* Epilogue for the GPRs. */ | |
2877 | offset = info->gp_save_offset; | |
2878 | if (info->push_p) | |
2879 | offset += info->total_size; | |
2880 | ||
2881 | for (int i = info->first_gp_reg_save; i < 32; i++) | |
2882 | { | |
2883 | if (bitmap_bit_p (components, i)) | |
2884 | { | |
2885 | rtx reg = gen_rtx_REG (reg_mode, i); | |
2886 | rtx_insn *insn = emit_insn (gen_frame_load (reg, ptr_reg, offset)); | |
2887 | RTX_FRAME_RELATED_P (insn) = 1; | |
2888 | add_reg_note (insn, REG_CFA_RESTORE, reg); | |
2889 | } | |
2890 | ||
2891 | offset += reg_size; | |
2892 | } | |
2893 | ||
2894 | /* Epilogue for LR. */ | |
2895 | if (bitmap_bit_p (components, 0)) | |
2896 | { | |
2897 | int offset = info->lr_save_offset; | |
2898 | if (info->push_p) | |
2899 | offset += info->total_size; | |
2900 | ||
2901 | rtx reg = gen_rtx_REG (reg_mode, 0); | |
2902 | rtx_insn *insn = emit_insn (gen_frame_load (reg, ptr_reg, offset)); | |
2903 | ||
2904 | rtx lr = gen_rtx_REG (Pmode, LR_REGNO); | |
2905 | insn = emit_move_insn (lr, reg); | |
2906 | RTX_FRAME_RELATED_P (insn) = 1; | |
2907 | add_reg_note (insn, REG_CFA_RESTORE, lr); | |
2908 | } | |
2909 | } | |
2910 | ||
2911 | /* Implement TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS. */ | |
2912 | void | |
2913 | rs6000_set_handled_components (sbitmap components) | |
2914 | { | |
2915 | rs6000_stack_t *info = rs6000_stack_info (); | |
2916 | ||
2917 | for (int i = info->first_gp_reg_save; i < 32; i++) | |
2918 | if (bitmap_bit_p (components, i)) | |
2919 | cfun->machine->gpr_is_wrapped_separately[i] = true; | |
2920 | ||
2921 | for (int i = info->first_fp_reg_save; i < 64; i++) | |
2922 | if (bitmap_bit_p (components, i)) | |
2923 | cfun->machine->fpr_is_wrapped_separately[i - 32] = true; | |
2924 | ||
2925 | if (bitmap_bit_p (components, 0)) | |
2926 | cfun->machine->lr_is_wrapped_separately = true; | |
2927 | ||
2928 | if (bitmap_bit_p (components, 2)) | |
2929 | cfun->machine->toc_is_wrapped_separately = true; | |
2930 | } | |
2931 | ||
2932 | /* VRSAVE is a bit vector representing which AltiVec registers | |
2933 | are used. The OS uses this to determine which vector | |
2934 | registers to save on a context switch. We need to save | |
2935 | VRSAVE on the stack frame, add whatever AltiVec registers we | |
2936 | used in this function, and do the corresponding magic in the | |
2937 | epilogue. */ | |
2938 | static void | |
2939 | emit_vrsave_prologue (rs6000_stack_t *info, int save_regno, | |
2940 | HOST_WIDE_INT frame_off, rtx frame_reg_rtx) | |
2941 | { | |
2942 | /* Get VRSAVE into a GPR. */ | |
2943 | rtx reg = gen_rtx_REG (SImode, save_regno); | |
2944 | rtx vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO); | |
2945 | if (TARGET_MACHO) | |
2946 | emit_insn (gen_get_vrsave_internal (reg)); | |
2947 | else | |
2948 | emit_insn (gen_rtx_SET (reg, vrsave)); | |
2949 | ||
2950 | /* Save VRSAVE. */ | |
2951 | int offset = info->vrsave_save_offset + frame_off; | |
2952 | emit_insn (gen_frame_store (reg, frame_reg_rtx, offset)); | |
2953 | ||
2954 | /* Include the registers in the mask. */ | |
2955 | emit_insn (gen_iorsi3 (reg, reg, GEN_INT (info->vrsave_mask))); | |
2956 | ||
2957 | emit_insn (generate_set_vrsave (reg, info, 0)); | |
2958 | } | |
2959 | ||
2960 | /* Set up the arg pointer (r12) for -fsplit-stack code. If __morestack was | |
2961 | called, it left the arg pointer to the old stack in r29. Otherwise, the | |
2962 | arg pointer is the top of the current frame. */ | |
2963 | static void | |
2964 | emit_split_stack_prologue (rs6000_stack_t *info, rtx_insn *sp_adjust, | |
2965 | HOST_WIDE_INT frame_off, rtx frame_reg_rtx) | |
2966 | { | |
2967 | cfun->machine->split_stack_argp_used = true; | |
2968 | ||
2969 | if (sp_adjust) | |
2970 | { | |
2971 | rtx r12 = gen_rtx_REG (Pmode, 12); | |
2972 | rtx sp_reg_rtx = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM); | |
2973 | rtx set_r12 = gen_rtx_SET (r12, sp_reg_rtx); | |
2974 | emit_insn_before (set_r12, sp_adjust); | |
2975 | } | |
2976 | else if (frame_off != 0 || REGNO (frame_reg_rtx) != 12) | |
2977 | { | |
2978 | rtx r12 = gen_rtx_REG (Pmode, 12); | |
2979 | if (frame_off == 0) | |
2980 | emit_move_insn (r12, frame_reg_rtx); | |
2981 | else | |
2982 | emit_insn (gen_add3_insn (r12, frame_reg_rtx, GEN_INT (frame_off))); | |
2983 | } | |
2984 | ||
2985 | if (info->push_p) | |
2986 | { | |
2987 | rtx r12 = gen_rtx_REG (Pmode, 12); | |
2988 | rtx r29 = gen_rtx_REG (Pmode, 29); | |
2989 | rtx cr7 = gen_rtx_REG (CCUNSmode, CR7_REGNO); | |
2990 | rtx not_more = gen_label_rtx (); | |
2991 | rtx jump; | |
2992 | ||
2993 | jump = gen_rtx_IF_THEN_ELSE (VOIDmode, | |
2994 | gen_rtx_GEU (VOIDmode, cr7, const0_rtx), | |
2995 | gen_rtx_LABEL_REF (VOIDmode, not_more), | |
2996 | pc_rtx); | |
2997 | jump = emit_jump_insn (gen_rtx_SET (pc_rtx, jump)); | |
2998 | JUMP_LABEL (jump) = not_more; | |
2999 | LABEL_NUSES (not_more) += 1; | |
3000 | emit_move_insn (r12, r29); | |
3001 | emit_label (not_more); | |
3002 | } | |
3003 | } | |
3004 | ||
3005 | /* Emit function prologue as insns. */ | |
3006 | ||
3007 | void | |
3008 | rs6000_emit_prologue (void) | |
3009 | { | |
3010 | rs6000_stack_t *info = rs6000_stack_info (); | |
3011 | machine_mode reg_mode = Pmode; | |
3012 | int reg_size = TARGET_32BIT ? 4 : 8; | |
3013 | machine_mode fp_reg_mode = TARGET_HARD_FLOAT ? DFmode : SFmode; | |
3014 | int fp_reg_size = 8; | |
3015 | rtx sp_reg_rtx = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM); | |
3016 | rtx frame_reg_rtx = sp_reg_rtx; | |
3017 | unsigned int cr_save_regno; | |
3018 | rtx cr_save_rtx = NULL_RTX; | |
3019 | rtx_insn *insn; | |
3020 | int strategy; | |
a365fa06 RS |
3021 | int using_static_chain_p |
3022 | = (cfun->static_chain_decl != NULL_TREE | |
3023 | && df_regs_ever_live_p (STATIC_CHAIN_REGNUM) | |
3024 | && call_used_or_fixed_reg_p (STATIC_CHAIN_REGNUM)); | |
2c04f847 BS |
3025 | int using_split_stack = (flag_split_stack |
3026 | && (lookup_attribute ("no_split_stack", | |
3027 | DECL_ATTRIBUTES (cfun->decl)) | |
3028 | == NULL)); | |
f6955089 XL |
3029 | |
3030 | frame_pointer_needed_indeed | |
3031 | = frame_pointer_needed && df_regs_ever_live_p (HARD_FRAME_POINTER_REGNUM); | |
3032 | ||
2c04f847 BS |
3033 | /* Offset to top of frame for frame_reg and sp respectively. */ |
3034 | HOST_WIDE_INT frame_off = 0; | |
3035 | HOST_WIDE_INT sp_off = 0; | |
3036 | /* sp_adjust is the stack adjusting instruction, tracked so that the | |
3037 | insn setting up the split-stack arg pointer can be emitted just | |
3038 | prior to it, when r12 is not used here for other purposes. */ | |
3039 | rtx_insn *sp_adjust = 0; | |
3040 | ||
3041 | #if CHECKING_P | |
3042 | /* Track and check usage of r0, r11, r12. */ | |
3043 | int reg_inuse = using_static_chain_p ? 1 << 11 : 0; | |
3044 | #define START_USE(R) do \ | |
3045 | { \ | |
3046 | gcc_assert ((reg_inuse & (1 << (R))) == 0); \ | |
3047 | reg_inuse |= 1 << (R); \ | |
3048 | } while (0) | |
3049 | #define END_USE(R) do \ | |
3050 | { \ | |
3051 | gcc_assert ((reg_inuse & (1 << (R))) != 0); \ | |
3052 | reg_inuse &= ~(1 << (R)); \ | |
3053 | } while (0) | |
3054 | #define NOT_INUSE(R) do \ | |
3055 | { \ | |
3056 | gcc_assert ((reg_inuse & (1 << (R))) == 0); \ | |
3057 | } while (0) | |
3058 | #else | |
3059 | #define START_USE(R) do {} while (0) | |
3060 | #define END_USE(R) do {} while (0) | |
3061 | #define NOT_INUSE(R) do {} while (0) | |
3062 | #endif | |
3063 | ||
3064 | if (DEFAULT_ABI == ABI_ELFv2 | |
3065 | && !TARGET_SINGLE_PIC_BASE) | |
3066 | { | |
3067 | cfun->machine->r2_setup_needed = df_regs_ever_live_p (TOC_REGNUM); | |
3068 | ||
3069 | /* With -mminimal-toc we may generate an extra use of r2 below. */ | |
3070 | if (TARGET_TOC && TARGET_MINIMAL_TOC | |
3071 | && !constant_pool_empty_p ()) | |
3072 | cfun->machine->r2_setup_needed = true; | |
3073 | } | |
3074 | ||
3075 | ||
3076 | if (flag_stack_usage_info) | |
3077 | current_function_static_stack_size = info->total_size; | |
3078 | ||
3079 | if (flag_stack_check == STATIC_BUILTIN_STACK_CHECK) | |
3080 | { | |
3081 | HOST_WIDE_INT size = info->total_size; | |
3082 | ||
3083 | if (crtl->is_leaf && !cfun->calls_alloca) | |
3084 | { | |
3085 | if (size > PROBE_INTERVAL && size > get_stack_check_protect ()) | |
3086 | rs6000_emit_probe_stack_range (get_stack_check_protect (), | |
3087 | size - get_stack_check_protect ()); | |
3088 | } | |
3089 | else if (size > 0) | |
3090 | rs6000_emit_probe_stack_range (get_stack_check_protect (), size); | |
3091 | } | |
3092 | ||
3093 | if (TARGET_FIX_AND_CONTINUE) | |
3094 | { | |
3095 | /* gdb on darwin arranges to forward a function from the old | |
3096 | address by modifying the first 5 instructions of the function | |
3097 | to branch to the overriding function. This is necessary to | |
3098 | permit function pointers that point to the old function to | |
3099 | actually forward to the new function. */ | |
3100 | emit_insn (gen_nop ()); | |
3101 | emit_insn (gen_nop ()); | |
3102 | emit_insn (gen_nop ()); | |
3103 | emit_insn (gen_nop ()); | |
3104 | emit_insn (gen_nop ()); | |
3105 | } | |
3106 | ||
3107 | /* Handle world saves specially here. */ | |
3108 | if (WORLD_SAVE_P (info)) | |
3109 | { | |
3110 | int i, j, sz; | |
3111 | rtx treg; | |
3112 | rtvec p; | |
3113 | rtx reg0; | |
3114 | ||
3115 | /* save_world expects lr in r0. */ | |
3116 | reg0 = gen_rtx_REG (Pmode, 0); | |
3117 | if (info->lr_save_p) | |
3118 | { | |
3119 | insn = emit_move_insn (reg0, | |
3120 | gen_rtx_REG (Pmode, LR_REGNO)); | |
3121 | RTX_FRAME_RELATED_P (insn) = 1; | |
3122 | } | |
3123 | ||
3124 | /* The SAVE_WORLD and RESTORE_WORLD routines make a number of | |
3125 | assumptions about the offsets of various bits of the stack | |
3126 | frame. */ | |
3127 | gcc_assert (info->gp_save_offset == -220 | |
3128 | && info->fp_save_offset == -144 | |
3129 | && info->lr_save_offset == 8 | |
3130 | && info->cr_save_offset == 4 | |
3131 | && info->push_p | |
3132 | && info->lr_save_p | |
3133 | && (!crtl->calls_eh_return | |
3134 | || info->ehrd_offset == -432) | |
3135 | && info->vrsave_save_offset == -224 | |
3136 | && info->altivec_save_offset == -416); | |
3137 | ||
3138 | treg = gen_rtx_REG (SImode, 11); | |
3139 | emit_move_insn (treg, GEN_INT (-info->total_size)); | |
3140 | ||
3141 | /* SAVE_WORLD takes the caller's LR in R0 and the frame size | |
3142 | in R11. It also clobbers R12, so beware! */ | |
3143 | ||
3144 | /* Preserve CR2 for save_world prologues */ | |
3145 | sz = 5; | |
3146 | sz += 32 - info->first_gp_reg_save; | |
3147 | sz += 64 - info->first_fp_reg_save; | |
3148 | sz += LAST_ALTIVEC_REGNO - info->first_altivec_reg_save + 1; | |
3149 | p = rtvec_alloc (sz); | |
3150 | j = 0; | |
3151 | RTVEC_ELT (p, j++) = gen_hard_reg_clobber (SImode, LR_REGNO); | |
3152 | RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode, | |
3153 | gen_rtx_SYMBOL_REF (Pmode, | |
3154 | "*save_world")); | |
3155 | /* We do floats first so that the instruction pattern matches | |
3156 | properly. */ | |
3157 | for (i = 0; i < 64 - info->first_fp_reg_save; i++) | |
3158 | RTVEC_ELT (p, j++) | |
3159 | = gen_frame_store (gen_rtx_REG (TARGET_HARD_FLOAT ? DFmode : SFmode, | |
3160 | info->first_fp_reg_save + i), | |
3161 | frame_reg_rtx, | |
3162 | info->fp_save_offset + frame_off + 8 * i); | |
3163 | for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++) | |
3164 | RTVEC_ELT (p, j++) | |
3165 | = gen_frame_store (gen_rtx_REG (V4SImode, | |
3166 | info->first_altivec_reg_save + i), | |
3167 | frame_reg_rtx, | |
3168 | info->altivec_save_offset + frame_off + 16 * i); | |
3169 | for (i = 0; i < 32 - info->first_gp_reg_save; i++) | |
3170 | RTVEC_ELT (p, j++) | |
3171 | = gen_frame_store (gen_rtx_REG (reg_mode, info->first_gp_reg_save + i), | |
3172 | frame_reg_rtx, | |
3173 | info->gp_save_offset + frame_off + reg_size * i); | |
3174 | ||
3175 | /* CR register traditionally saved as CR2. */ | |
3176 | RTVEC_ELT (p, j++) | |
3177 | = gen_frame_store (gen_rtx_REG (SImode, CR2_REGNO), | |
3178 | frame_reg_rtx, info->cr_save_offset + frame_off); | |
3179 | /* Explain about use of R0. */ | |
3180 | if (info->lr_save_p) | |
3181 | RTVEC_ELT (p, j++) | |
3182 | = gen_frame_store (reg0, | |
3183 | frame_reg_rtx, info->lr_save_offset + frame_off); | |
3184 | /* Explain what happens to the stack pointer. */ | |
3185 | { | |
3186 | rtx newval = gen_rtx_PLUS (Pmode, sp_reg_rtx, treg); | |
3187 | RTVEC_ELT (p, j++) = gen_rtx_SET (sp_reg_rtx, newval); | |
3188 | } | |
3189 | ||
3190 | insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p)); | |
3191 | rs6000_frame_related (insn, frame_reg_rtx, sp_off - frame_off, | |
3192 | treg, GEN_INT (-info->total_size)); | |
3193 | sp_off = frame_off = info->total_size; | |
3194 | } | |
3195 | ||
3196 | strategy = info->savres_strategy; | |
3197 | ||
3198 | /* For V.4, update stack before we do any saving and set back pointer. */ | |
3199 | if (! WORLD_SAVE_P (info) | |
3200 | && info->push_p | |
3201 | && (DEFAULT_ABI == ABI_V4 | |
3202 | || crtl->calls_eh_return)) | |
3203 | { | |
3204 | bool need_r11 = (!(strategy & SAVE_INLINE_FPRS) | |
3205 | || !(strategy & SAVE_INLINE_GPRS) | |
3206 | || !(strategy & SAVE_INLINE_VRS)); | |
3207 | int ptr_regno = -1; | |
3208 | rtx ptr_reg = NULL_RTX; | |
3209 | int ptr_off = 0; | |
3210 | ||
3211 | if (info->total_size < 32767) | |
3212 | frame_off = info->total_size; | |
3213 | else if (need_r11) | |
3214 | ptr_regno = 11; | |
3215 | else if (info->cr_save_p | |
3216 | || info->lr_save_p | |
3217 | || info->first_fp_reg_save < 64 | |
3218 | || info->first_gp_reg_save < 32 | |
3219 | || info->altivec_size != 0 | |
3220 | || info->vrsave_size != 0 | |
3221 | || crtl->calls_eh_return) | |
3222 | ptr_regno = 12; | |
3223 | else | |
3224 | { | |
3225 | /* The prologue won't be saving any regs so there is no need | |
3226 | to set up a frame register to access any frame save area. | |
3227 | We also won't be using frame_off anywhere below, but set | |
3228 | the correct value anyway to protect against future | |
3229 | changes to this function. */ | |
3230 | frame_off = info->total_size; | |
3231 | } | |
3232 | if (ptr_regno != -1) | |
3233 | { | |
3234 | /* Set up the frame offset to that needed by the first | |
3235 | out-of-line save function. */ | |
3236 | START_USE (ptr_regno); | |
3237 | ptr_reg = gen_rtx_REG (Pmode, ptr_regno); | |
3238 | frame_reg_rtx = ptr_reg; | |
3239 | if (!(strategy & SAVE_INLINE_FPRS) && info->fp_size != 0) | |
3240 | gcc_checking_assert (info->fp_save_offset + info->fp_size == 0); | |
3241 | else if (!(strategy & SAVE_INLINE_GPRS) && info->first_gp_reg_save < 32) | |
3242 | ptr_off = info->gp_save_offset + info->gp_size; | |
3243 | else if (!(strategy & SAVE_INLINE_VRS) && info->altivec_size != 0) | |
3244 | ptr_off = info->altivec_save_offset + info->altivec_size; | |
3245 | frame_off = -ptr_off; | |
3246 | } | |
3247 | sp_adjust = rs6000_emit_allocate_stack (info->total_size, | |
3248 | ptr_reg, ptr_off); | |
3249 | if (REGNO (frame_reg_rtx) == 12) | |
3250 | sp_adjust = 0; | |
3251 | sp_off = info->total_size; | |
3252 | if (frame_reg_rtx != sp_reg_rtx) | |
3253 | rs6000_emit_stack_tie (frame_reg_rtx, false); | |
3254 | } | |
3255 | ||
3256 | /* If we use the link register, get it into r0. */ | |
3257 | if (!WORLD_SAVE_P (info) && info->lr_save_p | |
3258 | && !cfun->machine->lr_is_wrapped_separately) | |
3259 | { | |
d2d74c9f | 3260 | rtx reg; |
2c04f847 BS |
3261 | |
3262 | reg = gen_rtx_REG (Pmode, 0); | |
3263 | START_USE (0); | |
3264 | insn = emit_move_insn (reg, gen_rtx_REG (Pmode, LR_REGNO)); | |
3265 | RTX_FRAME_RELATED_P (insn) = 1; | |
3266 | ||
3267 | if (!(strategy & (SAVE_NOINLINE_GPRS_SAVES_LR | |
3268 | | SAVE_NOINLINE_FPRS_SAVES_LR))) | |
3269 | { | |
d2d74c9f PH |
3270 | insn = emit_insn (gen_frame_store (reg, frame_reg_rtx, |
3271 | info->lr_save_offset + frame_off)); | |
2c04f847 BS |
3272 | rs6000_frame_related (insn, frame_reg_rtx, sp_off - frame_off, |
3273 | NULL_RTX, NULL_RTX); | |
3274 | END_USE (0); | |
3275 | } | |
3276 | } | |
3277 | ||
af979a98 BS |
3278 | /* The ROP hash store must occur before a stack frame is created, |
3279 | since the hash operates on r1. */ | |
3280 | /* NOTE: The hashst isn't needed if we're going to do a sibcall, | |
3281 | but there's no way to know that here. Harmless except for | |
3282 | performance, of course. */ | |
3283 | if (TARGET_POWER10 && rs6000_rop_protect && info->rop_hash_size != 0) | |
3284 | { | |
3285 | gcc_assert (DEFAULT_ABI == ABI_ELFv2); | |
3286 | rtx stack_ptr = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM); | |
3287 | rtx addr = gen_rtx_PLUS (Pmode, stack_ptr, | |
3288 | GEN_INT (info->rop_hash_save_offset)); | |
3289 | rtx mem = gen_rtx_MEM (Pmode, addr); | |
3290 | rtx reg0 = gen_rtx_REG (Pmode, 0); | |
3291 | emit_insn (gen_hashst (mem, reg0)); | |
3292 | } | |
3293 | ||
2c04f847 BS |
3294 | /* If we need to save CR, put it into r12 or r11. Choose r12 except when |
3295 | r12 will be needed by out-of-line gpr save. */ | |
2484f7a4 SB |
3296 | if (DEFAULT_ABI == ABI_AIX |
3297 | && !(strategy & (SAVE_INLINE_GPRS | SAVE_NOINLINE_GPRS_SAVES_LR))) | |
3298 | cr_save_regno = 11; | |
3299 | else if (DEFAULT_ABI == ABI_ELFv2) | |
3300 | cr_save_regno = 11; | |
3301 | else | |
3302 | cr_save_regno = 12; | |
2c04f847 BS |
3303 | if (!WORLD_SAVE_P (info) |
3304 | && info->cr_save_p | |
3305 | && REGNO (frame_reg_rtx) != cr_save_regno | |
3306 | && !(using_static_chain_p && cr_save_regno == 11) | |
3307 | && !(using_split_stack && cr_save_regno == 12 && sp_adjust)) | |
3308 | { | |
3309 | cr_save_rtx = gen_rtx_REG (SImode, cr_save_regno); | |
3310 | START_USE (cr_save_regno); | |
3311 | rs6000_emit_prologue_move_from_cr (cr_save_rtx); | |
3312 | } | |
3313 | ||
3314 | /* Do any required saving of fpr's. If only one or two to save, do | |
3315 | it ourselves. Otherwise, call function. */ | |
3316 | if (!WORLD_SAVE_P (info) && (strategy & SAVE_INLINE_FPRS)) | |
3317 | { | |
3318 | int offset = info->fp_save_offset + frame_off; | |
3319 | for (int i = info->first_fp_reg_save; i < 64; i++) | |
3320 | { | |
3321 | if (save_reg_p (i) | |
3322 | && !cfun->machine->fpr_is_wrapped_separately[i - 32]) | |
3323 | emit_frame_save (frame_reg_rtx, fp_reg_mode, i, offset, | |
3324 | sp_off - frame_off); | |
3325 | ||
3326 | offset += fp_reg_size; | |
3327 | } | |
3328 | } | |
3329 | else if (!WORLD_SAVE_P (info) && info->first_fp_reg_save != 64) | |
3330 | { | |
3331 | bool lr = (strategy & SAVE_NOINLINE_FPRS_SAVES_LR) != 0; | |
3332 | int sel = SAVRES_SAVE | SAVRES_FPR | (lr ? SAVRES_LR : 0); | |
3333 | unsigned ptr_regno = ptr_regno_for_savres (sel); | |
3334 | rtx ptr_reg = frame_reg_rtx; | |
3335 | ||
3336 | if (REGNO (frame_reg_rtx) == ptr_regno) | |
3337 | gcc_checking_assert (frame_off == 0); | |
3338 | else | |
3339 | { | |
3340 | ptr_reg = gen_rtx_REG (Pmode, ptr_regno); | |
3341 | NOT_INUSE (ptr_regno); | |
3342 | emit_insn (gen_add3_insn (ptr_reg, | |
3343 | frame_reg_rtx, GEN_INT (frame_off))); | |
3344 | } | |
3345 | insn = rs6000_emit_savres_rtx (info, ptr_reg, | |
3346 | info->fp_save_offset, | |
3347 | info->lr_save_offset, | |
3348 | DFmode, sel); | |
3349 | rs6000_frame_related (insn, ptr_reg, sp_off, | |
3350 | NULL_RTX, NULL_RTX); | |
3351 | if (lr) | |
3352 | END_USE (0); | |
3353 | } | |
3354 | ||
3355 | /* Save GPRs. This is done as a PARALLEL if we are using | |
3356 | the store-multiple instructions. */ | |
3357 | if (!WORLD_SAVE_P (info) && !(strategy & SAVE_INLINE_GPRS)) | |
3358 | { | |
3359 | bool lr = (strategy & SAVE_NOINLINE_GPRS_SAVES_LR) != 0; | |
3360 | int sel = SAVRES_SAVE | SAVRES_GPR | (lr ? SAVRES_LR : 0); | |
3361 | unsigned ptr_regno = ptr_regno_for_savres (sel); | |
3362 | rtx ptr_reg = frame_reg_rtx; | |
3363 | bool ptr_set_up = REGNO (ptr_reg) == ptr_regno; | |
3364 | int end_save = info->gp_save_offset + info->gp_size; | |
3365 | int ptr_off; | |
3366 | ||
3367 | if (ptr_regno == 12) | |
3368 | sp_adjust = 0; | |
3369 | if (!ptr_set_up) | |
3370 | ptr_reg = gen_rtx_REG (Pmode, ptr_regno); | |
3371 | ||
3372 | /* Need to adjust r11 (r12) if we saved any FPRs. */ | |
3373 | if (end_save + frame_off != 0) | |
3374 | { | |
3375 | rtx offset = GEN_INT (end_save + frame_off); | |
3376 | ||
3377 | if (ptr_set_up) | |
3378 | frame_off = -end_save; | |
3379 | else | |
3380 | NOT_INUSE (ptr_regno); | |
3381 | emit_insn (gen_add3_insn (ptr_reg, frame_reg_rtx, offset)); | |
3382 | } | |
3383 | else if (!ptr_set_up) | |
3384 | { | |
3385 | NOT_INUSE (ptr_regno); | |
3386 | emit_move_insn (ptr_reg, frame_reg_rtx); | |
3387 | } | |
3388 | ptr_off = -end_save; | |
3389 | insn = rs6000_emit_savres_rtx (info, ptr_reg, | |
3390 | info->gp_save_offset + ptr_off, | |
3391 | info->lr_save_offset + ptr_off, | |
3392 | reg_mode, sel); | |
3393 | rs6000_frame_related (insn, ptr_reg, sp_off - ptr_off, | |
3394 | NULL_RTX, NULL_RTX); | |
3395 | if (lr) | |
3396 | END_USE (0); | |
3397 | } | |
3398 | else if (!WORLD_SAVE_P (info) && (strategy & SAVE_MULTIPLE)) | |
3399 | { | |
3400 | rtvec p; | |
3401 | int i; | |
3402 | p = rtvec_alloc (32 - info->first_gp_reg_save); | |
3403 | for (i = 0; i < 32 - info->first_gp_reg_save; i++) | |
3404 | RTVEC_ELT (p, i) | |
3405 | = gen_frame_store (gen_rtx_REG (reg_mode, info->first_gp_reg_save + i), | |
3406 | frame_reg_rtx, | |
3407 | info->gp_save_offset + frame_off + reg_size * i); | |
3408 | insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p)); | |
3409 | rs6000_frame_related (insn, frame_reg_rtx, sp_off - frame_off, | |
3410 | NULL_RTX, NULL_RTX); | |
3411 | } | |
3412 | else if (!WORLD_SAVE_P (info)) | |
3413 | { | |
3414 | int offset = info->gp_save_offset + frame_off; | |
3415 | for (int i = info->first_gp_reg_save; i < 32; i++) | |
3416 | { | |
3417 | if (save_reg_p (i) | |
3418 | && !cfun->machine->gpr_is_wrapped_separately[i]) | |
3419 | emit_frame_save (frame_reg_rtx, reg_mode, i, offset, | |
3420 | sp_off - frame_off); | |
3421 | ||
3422 | offset += reg_size; | |
3423 | } | |
3424 | } | |
3425 | ||
3426 | if (crtl->calls_eh_return) | |
3427 | { | |
3428 | unsigned int i; | |
3429 | rtvec p; | |
3430 | ||
3431 | for (i = 0; ; ++i) | |
3432 | { | |
3433 | unsigned int regno = EH_RETURN_DATA_REGNO (i); | |
3434 | if (regno == INVALID_REGNUM) | |
3435 | break; | |
3436 | } | |
3437 | ||
3438 | p = rtvec_alloc (i); | |
3439 | ||
3440 | for (i = 0; ; ++i) | |
3441 | { | |
3442 | unsigned int regno = EH_RETURN_DATA_REGNO (i); | |
3443 | if (regno == INVALID_REGNUM) | |
3444 | break; | |
3445 | ||
3446 | rtx set | |
3447 | = gen_frame_store (gen_rtx_REG (reg_mode, regno), | |
3448 | sp_reg_rtx, | |
3449 | info->ehrd_offset + sp_off + reg_size * (int) i); | |
3450 | RTVEC_ELT (p, i) = set; | |
3451 | RTX_FRAME_RELATED_P (set) = 1; | |
3452 | } | |
3453 | ||
3454 | insn = emit_insn (gen_blockage ()); | |
3455 | RTX_FRAME_RELATED_P (insn) = 1; | |
3456 | add_reg_note (insn, REG_FRAME_RELATED_EXPR, gen_rtx_PARALLEL (VOIDmode, p)); | |
3457 | } | |
3458 | ||
3459 | /* In AIX ABI we need to make sure r2 is really saved. */ | |
3460 | if (TARGET_AIX && crtl->calls_eh_return) | |
3461 | { | |
3462 | rtx tmp_reg, tmp_reg_si, hi, lo, compare_result, toc_save_done, jump; | |
3463 | rtx join_insn, note; | |
3464 | rtx_insn *save_insn; | |
3465 | long toc_restore_insn; | |
3466 | ||
3467 | tmp_reg = gen_rtx_REG (Pmode, 11); | |
3468 | tmp_reg_si = gen_rtx_REG (SImode, 11); | |
3469 | if (using_static_chain_p) | |
3470 | { | |
3471 | START_USE (0); | |
3472 | emit_move_insn (gen_rtx_REG (Pmode, 0), tmp_reg); | |
3473 | } | |
3474 | else | |
3475 | START_USE (11); | |
3476 | emit_move_insn (tmp_reg, gen_rtx_REG (Pmode, LR_REGNO)); | |
3477 | /* Peek at instruction to which this function returns. If it's | |
3478 | restoring r2, then we know we've already saved r2. We can't | |
3479 | unconditionally save r2 because the value we have will already | |
3480 | be updated if we arrived at this function via a plt call or | |
3481 | toc adjusting stub. */ | |
3482 | emit_move_insn (tmp_reg_si, gen_rtx_MEM (SImode, tmp_reg)); | |
3483 | toc_restore_insn = ((TARGET_32BIT ? 0x80410000 : 0xE8410000) | |
3484 | + RS6000_TOC_SAVE_SLOT); | |
3485 | hi = gen_int_mode (toc_restore_insn & ~0xffff, SImode); | |
3486 | emit_insn (gen_xorsi3 (tmp_reg_si, tmp_reg_si, hi)); | |
3487 | compare_result = gen_rtx_REG (CCUNSmode, CR0_REGNO); | |
3488 | validate_condition_mode (EQ, CCUNSmode); | |
3489 | lo = gen_int_mode (toc_restore_insn & 0xffff, SImode); | |
3490 | emit_insn (gen_rtx_SET (compare_result, | |
3491 | gen_rtx_COMPARE (CCUNSmode, tmp_reg_si, lo))); | |
3492 | toc_save_done = gen_label_rtx (); | |
3493 | jump = gen_rtx_IF_THEN_ELSE (VOIDmode, | |
3494 | gen_rtx_EQ (VOIDmode, compare_result, | |
3495 | const0_rtx), | |
3496 | gen_rtx_LABEL_REF (VOIDmode, toc_save_done), | |
3497 | pc_rtx); | |
3498 | jump = emit_jump_insn (gen_rtx_SET (pc_rtx, jump)); | |
3499 | JUMP_LABEL (jump) = toc_save_done; | |
3500 | LABEL_NUSES (toc_save_done) += 1; | |
3501 | ||
3502 | save_insn = emit_frame_save (frame_reg_rtx, reg_mode, | |
3503 | TOC_REGNUM, frame_off + RS6000_TOC_SAVE_SLOT, | |
3504 | sp_off - frame_off); | |
3505 | ||
3506 | emit_label (toc_save_done); | |
3507 | ||
3508 | /* ??? If we leave SAVE_INSN as marked as saving R2, then we'll | |
3509 | have a CFG that has different saves along different paths. | |
3510 | Move the note to a dummy blockage insn, which describes that | |
3511 | R2 is unconditionally saved after the label. */ | |
3512 | /* ??? An alternate representation might be a special insn pattern | |
3513 | containing both the branch and the store. That might let the | |
3514 | code that minimizes the number of DW_CFA_advance opcodes better | |
3515 | freedom in placing the annotations. */ | |
3516 | note = find_reg_note (save_insn, REG_FRAME_RELATED_EXPR, NULL); | |
3517 | if (note) | |
3518 | remove_note (save_insn, note); | |
3519 | else | |
3520 | note = alloc_reg_note (REG_FRAME_RELATED_EXPR, | |
3521 | copy_rtx (PATTERN (save_insn)), NULL_RTX); | |
3522 | RTX_FRAME_RELATED_P (save_insn) = 0; | |
3523 | ||
3524 | join_insn = emit_insn (gen_blockage ()); | |
3525 | REG_NOTES (join_insn) = note; | |
3526 | RTX_FRAME_RELATED_P (join_insn) = 1; | |
3527 | ||
3528 | if (using_static_chain_p) | |
3529 | { | |
3530 | emit_move_insn (tmp_reg, gen_rtx_REG (Pmode, 0)); | |
3531 | END_USE (0); | |
3532 | } | |
3533 | else | |
3534 | END_USE (11); | |
3535 | } | |
3536 | ||
3537 | /* Save CR if we use any that must be preserved. */ | |
3538 | if (!WORLD_SAVE_P (info) && info->cr_save_p) | |
3539 | { | |
3540 | rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
3541 | GEN_INT (info->cr_save_offset + frame_off)); | |
3542 | rtx mem = gen_frame_mem (SImode, addr); | |
3543 | ||
3544 | /* If we didn't copy cr before, do so now using r0. */ | |
3545 | if (cr_save_rtx == NULL_RTX) | |
3546 | { | |
3547 | START_USE (0); | |
3548 | cr_save_rtx = gen_rtx_REG (SImode, 0); | |
3549 | rs6000_emit_prologue_move_from_cr (cr_save_rtx); | |
3550 | } | |
3551 | ||
3552 | /* Saving CR requires a two-instruction sequence: one instruction | |
3553 | to move the CR to a general-purpose register, and a second | |
3554 | instruction that stores the GPR to memory. | |
3555 | ||
3556 | We do not emit any DWARF CFI records for the first of these, | |
3557 | because we cannot properly represent the fact that CR is saved in | |
3558 | a register. One reason is that we cannot express that multiple | |
3559 | CR fields are saved; another reason is that on 64-bit, the size | |
3560 | of the CR register in DWARF (4 bytes) differs from the size of | |
3561 | a general-purpose register. | |
3562 | ||
3563 | This means if any intervening instruction were to clobber one of | |
3564 | the call-saved CR fields, we'd have incorrect CFI. To prevent | |
3565 | this from happening, we mark the store to memory as a use of | |
3566 | those CR fields, which prevents any such instruction from being | |
3567 | scheduled in between the two instructions. */ | |
3568 | rtx crsave_v[9]; | |
3569 | int n_crsave = 0; | |
3570 | int i; | |
3571 | ||
3572 | crsave_v[n_crsave++] = gen_rtx_SET (mem, cr_save_rtx); | |
3573 | for (i = 0; i < 8; i++) | |
3574 | if (save_reg_p (CR0_REGNO + i)) | |
3575 | crsave_v[n_crsave++] | |
3576 | = gen_rtx_USE (VOIDmode, gen_rtx_REG (CCmode, CR0_REGNO + i)); | |
3577 | ||
3578 | insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, | |
3579 | gen_rtvec_v (n_crsave, crsave_v))); | |
3580 | END_USE (REGNO (cr_save_rtx)); | |
3581 | ||
3582 | /* Now, there's no way that dwarf2out_frame_debug_expr is going to | |
3583 | understand '(unspec:SI [(reg:CC 68) ...] UNSPEC_MOVESI_FROM_CR)', | |
3584 | so we need to construct a frame expression manually. */ | |
3585 | RTX_FRAME_RELATED_P (insn) = 1; | |
3586 | ||
3587 | /* Update address to be stack-pointer relative, like | |
3588 | rs6000_frame_related would do. */ | |
3589 | addr = gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, STACK_POINTER_REGNUM), | |
3590 | GEN_INT (info->cr_save_offset + sp_off)); | |
3591 | mem = gen_frame_mem (SImode, addr); | |
3592 | ||
3593 | if (DEFAULT_ABI == ABI_ELFv2) | |
3594 | { | |
3595 | /* In the ELFv2 ABI we generate separate CFI records for each | |
3596 | CR field that was actually saved. They all point to the | |
3597 | same 32-bit stack slot. */ | |
3598 | rtx crframe[8]; | |
3599 | int n_crframe = 0; | |
3600 | ||
3601 | for (i = 0; i < 8; i++) | |
3602 | if (save_reg_p (CR0_REGNO + i)) | |
3603 | { | |
3604 | crframe[n_crframe] | |
3605 | = gen_rtx_SET (mem, gen_rtx_REG (SImode, CR0_REGNO + i)); | |
3606 | ||
3607 | RTX_FRAME_RELATED_P (crframe[n_crframe]) = 1; | |
3608 | n_crframe++; | |
3609 | } | |
3610 | ||
3611 | add_reg_note (insn, REG_FRAME_RELATED_EXPR, | |
3612 | gen_rtx_PARALLEL (VOIDmode, | |
3613 | gen_rtvec_v (n_crframe, crframe))); | |
3614 | } | |
3615 | else | |
3616 | { | |
3617 | /* In other ABIs, by convention, we use a single CR regnum to | |
3618 | represent the fact that all call-saved CR fields are saved. | |
3619 | We use CR2_REGNO to be compatible with gcc-2.95 on Linux. */ | |
3620 | rtx set = gen_rtx_SET (mem, gen_rtx_REG (SImode, CR2_REGNO)); | |
3621 | add_reg_note (insn, REG_FRAME_RELATED_EXPR, set); | |
3622 | } | |
3623 | } | |
3624 | ||
3625 | /* In the ELFv2 ABI we need to save all call-saved CR fields into | |
3626 | *separate* slots if the routine calls __builtin_eh_return, so | |
3627 | that they can be independently restored by the unwinder. */ | |
3628 | if (DEFAULT_ABI == ABI_ELFv2 && crtl->calls_eh_return) | |
3629 | { | |
3630 | int i, cr_off = info->ehcr_offset; | |
3631 | rtx crsave; | |
3632 | ||
3633 | /* ??? We might get better performance by using multiple mfocrf | |
3634 | instructions. */ | |
3635 | crsave = gen_rtx_REG (SImode, 0); | |
3636 | emit_insn (gen_prologue_movesi_from_cr (crsave)); | |
3637 | ||
3638 | for (i = 0; i < 8; i++) | |
a365fa06 | 3639 | if (!call_used_or_fixed_reg_p (CR0_REGNO + i)) |
2c04f847 BS |
3640 | { |
3641 | rtvec p = rtvec_alloc (2); | |
3642 | RTVEC_ELT (p, 0) | |
3643 | = gen_frame_store (crsave, frame_reg_rtx, cr_off + frame_off); | |
3644 | RTVEC_ELT (p, 1) | |
3645 | = gen_rtx_USE (VOIDmode, gen_rtx_REG (CCmode, CR0_REGNO + i)); | |
3646 | ||
3647 | insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p)); | |
3648 | ||
3649 | RTX_FRAME_RELATED_P (insn) = 1; | |
3650 | add_reg_note (insn, REG_FRAME_RELATED_EXPR, | |
3651 | gen_frame_store (gen_rtx_REG (SImode, CR0_REGNO + i), | |
3652 | sp_reg_rtx, cr_off + sp_off)); | |
3653 | ||
3654 | cr_off += reg_size; | |
3655 | } | |
3656 | } | |
3657 | ||
3658 | /* If we are emitting stack probes, but allocate no stack, then | |
3659 | just note that in the dump file. */ | |
3660 | if (flag_stack_clash_protection | |
3661 | && dump_file | |
3662 | && !info->push_p) | |
3663 | dump_stack_clash_frame_info (NO_PROBE_NO_FRAME, false); | |
3664 | ||
3665 | /* Update stack and set back pointer unless this is V.4, | |
3666 | for which it was done previously. */ | |
3667 | if (!WORLD_SAVE_P (info) && info->push_p | |
3668 | && !(DEFAULT_ABI == ABI_V4 || crtl->calls_eh_return)) | |
3669 | { | |
3670 | rtx ptr_reg = NULL; | |
3671 | int ptr_off = 0; | |
3672 | ||
3673 | /* If saving altivec regs we need to be able to address all save | |
3674 | locations using a 16-bit offset. */ | |
3675 | if ((strategy & SAVE_INLINE_VRS) == 0 | |
3676 | || (info->altivec_size != 0 | |
3677 | && (info->altivec_save_offset + info->altivec_size - 16 | |
3678 | + info->total_size - frame_off) > 32767) | |
3679 | || (info->vrsave_size != 0 | |
3680 | && (info->vrsave_save_offset | |
3681 | + info->total_size - frame_off) > 32767)) | |
3682 | { | |
3683 | int sel = SAVRES_SAVE | SAVRES_VR; | |
3684 | unsigned ptr_regno = ptr_regno_for_savres (sel); | |
3685 | ||
3686 | if (using_static_chain_p | |
3687 | && ptr_regno == STATIC_CHAIN_REGNUM) | |
3688 | ptr_regno = 12; | |
3689 | if (REGNO (frame_reg_rtx) != ptr_regno) | |
3690 | START_USE (ptr_regno); | |
3691 | ptr_reg = gen_rtx_REG (Pmode, ptr_regno); | |
3692 | frame_reg_rtx = ptr_reg; | |
3693 | ptr_off = info->altivec_save_offset + info->altivec_size; | |
3694 | frame_off = -ptr_off; | |
3695 | } | |
3696 | else if (REGNO (frame_reg_rtx) == 1) | |
3697 | frame_off = info->total_size; | |
3698 | sp_adjust = rs6000_emit_allocate_stack (info->total_size, | |
3699 | ptr_reg, ptr_off); | |
3700 | if (REGNO (frame_reg_rtx) == 12) | |
3701 | sp_adjust = 0; | |
3702 | sp_off = info->total_size; | |
3703 | if (frame_reg_rtx != sp_reg_rtx) | |
3704 | rs6000_emit_stack_tie (frame_reg_rtx, false); | |
3705 | } | |
3706 | ||
3707 | /* Set frame pointer, if needed. */ | |
f6955089 | 3708 | if (frame_pointer_needed_indeed) |
2c04f847 BS |
3709 | { |
3710 | insn = emit_move_insn (gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM), | |
3711 | sp_reg_rtx); | |
3712 | RTX_FRAME_RELATED_P (insn) = 1; | |
3713 | } | |
3714 | ||
3715 | /* Save AltiVec registers if needed. Save here because the red zone does | |
3716 | not always include AltiVec registers. */ | |
3717 | if (!WORLD_SAVE_P (info) | |
3718 | && info->altivec_size != 0 && (strategy & SAVE_INLINE_VRS) == 0) | |
3719 | { | |
3720 | int end_save = info->altivec_save_offset + info->altivec_size; | |
3721 | int ptr_off; | |
3722 | /* Oddly, the vector save/restore functions point r0 at the end | |
3723 | of the save area, then use r11 or r12 to load offsets for | |
3724 | [reg+reg] addressing. */ | |
3725 | rtx ptr_reg = gen_rtx_REG (Pmode, 0); | |
3726 | int scratch_regno = ptr_regno_for_savres (SAVRES_SAVE | SAVRES_VR); | |
3727 | rtx scratch_reg = gen_rtx_REG (Pmode, scratch_regno); | |
3728 | ||
3729 | gcc_checking_assert (scratch_regno == 11 || scratch_regno == 12); | |
3730 | NOT_INUSE (0); | |
3731 | if (scratch_regno == 12) | |
3732 | sp_adjust = 0; | |
3733 | if (end_save + frame_off != 0) | |
3734 | { | |
3735 | rtx offset = GEN_INT (end_save + frame_off); | |
3736 | ||
3737 | emit_insn (gen_add3_insn (ptr_reg, frame_reg_rtx, offset)); | |
3738 | } | |
3739 | else | |
3740 | emit_move_insn (ptr_reg, frame_reg_rtx); | |
3741 | ||
3742 | ptr_off = -end_save; | |
3743 | insn = rs6000_emit_savres_rtx (info, scratch_reg, | |
3744 | info->altivec_save_offset + ptr_off, | |
3745 | 0, V4SImode, SAVRES_SAVE | SAVRES_VR); | |
3746 | rs6000_frame_related (insn, scratch_reg, sp_off - ptr_off, | |
3747 | NULL_RTX, NULL_RTX); | |
3748 | if (REGNO (frame_reg_rtx) == REGNO (scratch_reg)) | |
3749 | { | |
3750 | /* The oddity mentioned above clobbered our frame reg. */ | |
3751 | emit_move_insn (frame_reg_rtx, ptr_reg); | |
3752 | frame_off = ptr_off; | |
3753 | } | |
3754 | } | |
3755 | else if (!WORLD_SAVE_P (info) | |
3756 | && info->altivec_size != 0) | |
3757 | { | |
3758 | int i; | |
3759 | ||
3760 | for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i) | |
3761 | if (info->vrsave_mask & ALTIVEC_REG_BIT (i)) | |
3762 | { | |
3763 | rtx areg, savereg, mem; | |
3764 | HOST_WIDE_INT offset; | |
3765 | ||
3766 | offset = (info->altivec_save_offset + frame_off | |
3767 | + 16 * (i - info->first_altivec_reg_save)); | |
3768 | ||
3769 | savereg = gen_rtx_REG (V4SImode, i); | |
3770 | ||
3771 | if (TARGET_P9_VECTOR && quad_address_offset_p (offset)) | |
3772 | { | |
3773 | mem = gen_frame_mem (V4SImode, | |
3774 | gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
3775 | GEN_INT (offset))); | |
3776 | insn = emit_insn (gen_rtx_SET (mem, savereg)); | |
3777 | areg = NULL_RTX; | |
3778 | } | |
3779 | else | |
3780 | { | |
3781 | NOT_INUSE (0); | |
3782 | areg = gen_rtx_REG (Pmode, 0); | |
3783 | emit_move_insn (areg, GEN_INT (offset)); | |
3784 | ||
3785 | /* AltiVec addressing mode is [reg+reg]. */ | |
3786 | mem = gen_frame_mem (V4SImode, | |
3787 | gen_rtx_PLUS (Pmode, frame_reg_rtx, areg)); | |
3788 | ||
3789 | /* Rather than emitting a generic move, force use of the stvx | |
3790 | instruction, which we always want on ISA 2.07 (power8) systems. | |
3791 | In particular we don't want xxpermdi/stxvd2x for little | |
3792 | endian. */ | |
3793 | insn = emit_insn (gen_altivec_stvx_v4si_internal (mem, savereg)); | |
3794 | } | |
3795 | ||
3796 | rs6000_frame_related (insn, frame_reg_rtx, sp_off - frame_off, | |
3797 | areg, GEN_INT (offset)); | |
3798 | } | |
3799 | } | |
3800 | ||
3801 | /* VRSAVE is a bit vector representing which AltiVec registers | |
3802 | are used. The OS uses this to determine which vector | |
3803 | registers to save on a context switch. We need to save | |
3804 | VRSAVE on the stack frame, add whatever AltiVec registers we | |
3805 | used in this function, and do the corresponding magic in the | |
3806 | epilogue. */ | |
3807 | ||
3808 | if (!WORLD_SAVE_P (info) && info->vrsave_size != 0) | |
3809 | { | |
3810 | /* Get VRSAVE into a GPR. Note that ABI_V4 and ABI_DARWIN might | |
3811 | be using r12 as frame_reg_rtx and r11 as the static chain | |
3812 | pointer for nested functions. */ | |
3813 | int save_regno = 12; | |
3814 | if ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2) | |
3815 | && !using_static_chain_p) | |
3816 | save_regno = 11; | |
3817 | else if (using_split_stack || REGNO (frame_reg_rtx) == 12) | |
3818 | { | |
3819 | save_regno = 11; | |
3820 | if (using_static_chain_p) | |
3821 | save_regno = 0; | |
3822 | } | |
3823 | NOT_INUSE (save_regno); | |
3824 | ||
3825 | emit_vrsave_prologue (info, save_regno, frame_off, frame_reg_rtx); | |
3826 | } | |
3827 | ||
3828 | /* If we are using RS6000_PIC_OFFSET_TABLE_REGNUM, we need to set it up. */ | |
3829 | if (!TARGET_SINGLE_PIC_BASE | |
3830 | && ((TARGET_TOC && TARGET_MINIMAL_TOC | |
3831 | && !constant_pool_empty_p ()) | |
3832 | || (DEFAULT_ABI == ABI_V4 | |
3833 | && (flag_pic == 1 || (flag_pic && TARGET_SECURE_PLT)) | |
3834 | && df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM)))) | |
3835 | { | |
3836 | /* If emit_load_toc_table will use the link register, we need to save | |
3837 | it. We use R12 for this purpose because emit_load_toc_table | |
3838 | can use register 0. This allows us to use a plain 'blr' to return | |
3839 | from the procedure more often. */ | |
3840 | int save_LR_around_toc_setup = (TARGET_ELF | |
3841 | && DEFAULT_ABI == ABI_V4 | |
3842 | && flag_pic | |
3843 | && ! info->lr_save_p | |
3844 | && EDGE_COUNT (EXIT_BLOCK_PTR_FOR_FN (cfun)->preds) > 0); | |
3845 | if (save_LR_around_toc_setup) | |
3846 | { | |
3847 | rtx lr = gen_rtx_REG (Pmode, LR_REGNO); | |
3848 | rtx tmp = gen_rtx_REG (Pmode, 12); | |
3849 | ||
3850 | sp_adjust = 0; | |
3851 | insn = emit_move_insn (tmp, lr); | |
3852 | RTX_FRAME_RELATED_P (insn) = 1; | |
3853 | ||
3854 | rs6000_emit_load_toc_table (TRUE); | |
3855 | ||
3856 | insn = emit_move_insn (lr, tmp); | |
3857 | add_reg_note (insn, REG_CFA_RESTORE, lr); | |
3858 | RTX_FRAME_RELATED_P (insn) = 1; | |
3859 | } | |
3860 | else | |
3861 | rs6000_emit_load_toc_table (TRUE); | |
3862 | } | |
3863 | ||
3864 | #if TARGET_MACHO | |
3865 | if (!TARGET_SINGLE_PIC_BASE | |
3866 | && DEFAULT_ABI == ABI_DARWIN | |
3867 | && flag_pic && crtl->uses_pic_offset_table) | |
3868 | { | |
3869 | rtx lr = gen_rtx_REG (Pmode, LR_REGNO); | |
3870 | rtx src = gen_rtx_SYMBOL_REF (Pmode, MACHOPIC_FUNCTION_BASE_NAME); | |
3871 | ||
3872 | /* Save and restore LR locally around this call (in R0). */ | |
3873 | if (!info->lr_save_p) | |
3874 | emit_move_insn (gen_rtx_REG (Pmode, 0), lr); | |
3875 | ||
4fc1d262 | 3876 | emit_insn (gen_load_macho_picbase (Pmode, src)); |
2c04f847 BS |
3877 | |
3878 | emit_move_insn (gen_rtx_REG (Pmode, | |
3879 | RS6000_PIC_OFFSET_TABLE_REGNUM), | |
3880 | lr); | |
3881 | ||
3882 | if (!info->lr_save_p) | |
3883 | emit_move_insn (lr, gen_rtx_REG (Pmode, 0)); | |
3884 | } | |
3885 | #endif | |
3886 | ||
3887 | /* If we need to, save the TOC register after doing the stack setup. | |
3888 | Do not emit eh frame info for this save. The unwinder wants info, | |
3889 | conceptually attached to instructions in this function, about | |
3890 | register values in the caller of this function. This R2 may have | |
3891 | already been changed from the value in the caller. | |
3892 | We don't attempt to write accurate DWARF EH frame info for R2 | |
3893 | because code emitted by gcc for a (non-pointer) function call | |
3894 | doesn't save and restore R2. Instead, R2 is managed out-of-line | |
3895 | by a linker generated plt call stub when the function resides in | |
3896 | a shared library. This behavior is costly to describe in DWARF, | |
3897 | both in terms of the size of DWARF info and the time taken in the | |
3898 | unwinder to interpret it. R2 changes, apart from the | |
3899 | calls_eh_return case earlier in this function, are handled by | |
3900 | linux-unwind.h frob_update_context. */ | |
3901 | if (rs6000_save_toc_in_prologue_p () | |
3902 | && !cfun->machine->toc_is_wrapped_separately) | |
3903 | { | |
3904 | rtx reg = gen_rtx_REG (reg_mode, TOC_REGNUM); | |
3905 | emit_insn (gen_frame_store (reg, sp_reg_rtx, RS6000_TOC_SAVE_SLOT)); | |
3906 | } | |
3907 | ||
3908 | /* Set up the arg pointer (r12) for -fsplit-stack code. */ | |
3909 | if (using_split_stack && split_stack_arg_pointer_used_p ()) | |
3910 | emit_split_stack_prologue (info, sp_adjust, frame_off, frame_reg_rtx); | |
3911 | } | |
3912 | ||
3913 | /* Output .extern statements for the save/restore routines we use. */ | |
3914 | ||
3915 | static void | |
3916 | rs6000_output_savres_externs (FILE *file) | |
3917 | { | |
3918 | rs6000_stack_t *info = rs6000_stack_info (); | |
3919 | ||
3920 | if (TARGET_DEBUG_STACK) | |
3921 | debug_stack_info (info); | |
3922 | ||
3923 | /* Write .extern for any function we will call to save and restore | |
3924 | fp values. */ | |
3925 | if (info->first_fp_reg_save < 64 | |
3926 | && !TARGET_MACHO | |
3927 | && !TARGET_ELF) | |
3928 | { | |
3929 | char *name; | |
3930 | int regno = info->first_fp_reg_save - 32; | |
3931 | ||
3932 | if ((info->savres_strategy & SAVE_INLINE_FPRS) == 0) | |
3933 | { | |
3934 | bool lr = (info->savres_strategy & SAVE_NOINLINE_FPRS_SAVES_LR) != 0; | |
3935 | int sel = SAVRES_SAVE | SAVRES_FPR | (lr ? SAVRES_LR : 0); | |
3936 | name = rs6000_savres_routine_name (regno, sel); | |
3937 | fprintf (file, "\t.extern %s\n", name); | |
3938 | } | |
3939 | if ((info->savres_strategy & REST_INLINE_FPRS) == 0) | |
3940 | { | |
3941 | bool lr = (info->savres_strategy | |
3942 | & REST_NOINLINE_FPRS_DOESNT_RESTORE_LR) == 0; | |
3943 | int sel = SAVRES_FPR | (lr ? SAVRES_LR : 0); | |
3944 | name = rs6000_savres_routine_name (regno, sel); | |
3945 | fprintf (file, "\t.extern %s\n", name); | |
3946 | } | |
3947 | } | |
3948 | } | |
3949 | ||
3950 | /* Write function prologue. */ | |
3951 | ||
3952 | void | |
3953 | rs6000_output_function_prologue (FILE *file) | |
3954 | { | |
3955 | if (!cfun->is_thunk) | |
3956 | { | |
3957 | rs6000_output_savres_externs (file); | |
3958 | #ifdef USING_ELFOS_H | |
3959 | const char *curr_machine = rs6000_machine_from_flags (); | |
3960 | if (rs6000_machine != curr_machine) | |
3961 | { | |
3962 | rs6000_machine = curr_machine; | |
3963 | emit_asm_machine (); | |
3964 | } | |
3965 | #endif | |
3966 | } | |
3967 | ||
3968 | /* ELFv2 ABI r2 setup code and local entry point. This must follow | |
3969 | immediately after the global entry point label. */ | |
3970 | if (rs6000_global_entry_point_prologue_needed_p ()) | |
3971 | { | |
3972 | const char *name = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0); | |
3973 | (*targetm.asm_out.internal_label) (file, "LCF", rs6000_pic_labelno); | |
3974 | ||
3975 | if (TARGET_CMODEL != CMODEL_LARGE) | |
3976 | { | |
3977 | /* In the small and medium code models, we assume the TOC is less | |
3978 | 2 GB away from the text section, so it can be computed via the | |
3979 | following two-instruction sequence. */ | |
3980 | char buf[256]; | |
3981 | ||
3982 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno); | |
3983 | fprintf (file, "0:\taddis 2,12,.TOC.-"); | |
3984 | assemble_name (file, buf); | |
3985 | fprintf (file, "@ha\n"); | |
3986 | fprintf (file, "\taddi 2,2,.TOC.-"); | |
3987 | assemble_name (file, buf); | |
3988 | fprintf (file, "@l\n"); | |
3989 | } | |
3990 | else | |
3991 | { | |
3992 | /* In the large code model, we allow arbitrary offsets between the | |
3993 | TOC and the text section, so we have to load the offset from | |
3994 | memory. The data field is emitted directly before the global | |
3995 | entry point in rs6000_elf_declare_function_name. */ | |
3996 | char buf[256]; | |
3997 | ||
3998 | #ifdef HAVE_AS_ENTRY_MARKERS | |
3999 | /* If supported by the linker, emit a marker relocation. If the | |
4000 | total code size of the final executable or shared library | |
4001 | happens to fit into 2 GB after all, the linker will replace | |
4002 | this code sequence with the sequence for the small or medium | |
4003 | code model. */ | |
4004 | fprintf (file, "\t.reloc .,R_PPC64_ENTRY\n"); | |
4005 | #endif | |
4006 | fprintf (file, "\tld 2,"); | |
4007 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno); | |
4008 | assemble_name (file, buf); | |
4009 | fprintf (file, "-"); | |
4010 | ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno); | |
4011 | assemble_name (file, buf); | |
4012 | fprintf (file, "(12)\n"); | |
4013 | fprintf (file, "\tadd 2,2,12\n"); | |
4014 | } | |
4015 | ||
4016 | fputs ("\t.localentry\t", file); | |
4017 | assemble_name (file, name); | |
4018 | fputs (",.-", file); | |
4019 | assemble_name (file, name); | |
4020 | fputs ("\n", file); | |
4021 | } | |
4022 | ||
8c0f8755 | 4023 | else if (rs6000_pcrel_p ()) |
2c04f847 BS |
4024 | { |
4025 | const char *name = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0); | |
4026 | /* All functions compiled to use PC-relative addressing will | |
4027 | have a .localentry value of 0 or 1. For now we set it to | |
4028 | 1 all the time, indicating that the function may clobber | |
4029 | the TOC register r2. Later we may optimize this by setting | |
4030 | it to 0 if the function is a leaf and does not clobber r2. */ | |
4031 | fputs ("\t.localentry\t", file); | |
4032 | assemble_name (file, name); | |
4033 | fputs (",1\n", file); | |
4034 | } | |
4035 | ||
4036 | /* Output -mprofile-kernel code. This needs to be done here instead of | |
4037 | in output_function_profile since it must go after the ELFv2 ABI | |
4038 | local entry point. */ | |
4039 | if (TARGET_PROFILE_KERNEL && crtl->profile) | |
4040 | { | |
4041 | gcc_assert (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2); | |
4042 | gcc_assert (!TARGET_32BIT); | |
4043 | ||
4044 | asm_fprintf (file, "\tmflr %s\n", reg_names[0]); | |
4045 | ||
4046 | /* In the ELFv2 ABI we have no compiler stack word. It must be | |
4047 | the resposibility of _mcount to preserve the static chain | |
4048 | register if required. */ | |
4049 | if (DEFAULT_ABI != ABI_ELFv2 | |
4050 | && cfun->static_chain_decl != NULL) | |
4051 | { | |
4052 | asm_fprintf (file, "\tstd %s,24(%s)\n", | |
4053 | reg_names[STATIC_CHAIN_REGNUM], reg_names[1]); | |
4054 | fprintf (file, "\tbl %s\n", RS6000_MCOUNT); | |
4055 | asm_fprintf (file, "\tld %s,24(%s)\n", | |
4056 | reg_names[STATIC_CHAIN_REGNUM], reg_names[1]); | |
4057 | } | |
4058 | else | |
4059 | fprintf (file, "\tbl %s\n", RS6000_MCOUNT); | |
4060 | } | |
4061 | ||
4062 | rs6000_pic_labelno++; | |
4063 | } | |
4064 | ||
4065 | /* -mprofile-kernel code calls mcount before the function prolog, | |
4066 | so a profiled leaf function should stay a leaf function. */ | |
93a090cf SB |
4067 | bool |
4068 | rs6000_keep_leaf_when_profiled (void) | |
2c04f847 BS |
4069 | { |
4070 | return TARGET_PROFILE_KERNEL; | |
4071 | } | |
4072 | ||
4073 | /* Non-zero if vmx regs are restored before the frame pop, zero if | |
4074 | we restore after the pop when possible. */ | |
4075 | #define ALWAYS_RESTORE_ALTIVEC_BEFORE_POP 0 | |
4076 | ||
4077 | /* Restoring cr is a two step process: loading a reg from the frame | |
4078 | save, then moving the reg to cr. For ABI_V4 we must let the | |
4079 | unwinder know that the stack location is no longer valid at or | |
4080 | before the stack deallocation, but we can't emit a cfa_restore for | |
4081 | cr at the stack deallocation like we do for other registers. | |
4082 | The trouble is that it is possible for the move to cr to be | |
4083 | scheduled after the stack deallocation. So say exactly where cr | |
4084 | is located on each of the two insns. */ | |
4085 | ||
4086 | static rtx | |
4087 | load_cr_save (int regno, rtx frame_reg_rtx, int offset, bool exit_func) | |
4088 | { | |
4089 | rtx mem = gen_frame_mem_offset (SImode, frame_reg_rtx, offset); | |
4090 | rtx reg = gen_rtx_REG (SImode, regno); | |
4091 | rtx_insn *insn = emit_move_insn (reg, mem); | |
4092 | ||
4093 | if (!exit_func && DEFAULT_ABI == ABI_V4) | |
4094 | { | |
4095 | rtx cr = gen_rtx_REG (SImode, CR2_REGNO); | |
4096 | rtx set = gen_rtx_SET (reg, cr); | |
4097 | ||
4098 | add_reg_note (insn, REG_CFA_REGISTER, set); | |
4099 | RTX_FRAME_RELATED_P (insn) = 1; | |
4100 | } | |
4101 | return reg; | |
4102 | } | |
4103 | ||
4104 | /* Reload CR from REG. */ | |
4105 | ||
4106 | static void | |
4107 | restore_saved_cr (rtx reg, bool using_mfcr_multiple, bool exit_func) | |
4108 | { | |
4109 | int count = 0; | |
4110 | int i; | |
4111 | ||
4112 | if (using_mfcr_multiple) | |
4113 | { | |
4114 | for (i = 0; i < 8; i++) | |
4115 | if (save_reg_p (CR0_REGNO + i)) | |
4116 | count++; | |
4117 | gcc_assert (count); | |
4118 | } | |
4119 | ||
4120 | if (using_mfcr_multiple && count > 1) | |
4121 | { | |
4122 | rtx_insn *insn; | |
4123 | rtvec p; | |
4124 | int ndx; | |
4125 | ||
4126 | p = rtvec_alloc (count); | |
4127 | ||
4128 | ndx = 0; | |
4129 | for (i = 0; i < 8; i++) | |
4130 | if (save_reg_p (CR0_REGNO + i)) | |
4131 | { | |
4132 | rtvec r = rtvec_alloc (2); | |
4133 | RTVEC_ELT (r, 0) = reg; | |
4134 | RTVEC_ELT (r, 1) = GEN_INT (1 << (7-i)); | |
4135 | RTVEC_ELT (p, ndx) = | |
4136 | gen_rtx_SET (gen_rtx_REG (CCmode, CR0_REGNO + i), | |
4137 | gen_rtx_UNSPEC (CCmode, r, UNSPEC_MOVESI_TO_CR)); | |
4138 | ndx++; | |
4139 | } | |
4140 | insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p)); | |
4141 | gcc_assert (ndx == count); | |
4142 | ||
4143 | /* For the ELFv2 ABI we generate a CFA_RESTORE for each | |
4144 | CR field separately. */ | |
4145 | if (!exit_func && DEFAULT_ABI == ABI_ELFv2 && flag_shrink_wrap) | |
4146 | { | |
4147 | for (i = 0; i < 8; i++) | |
4148 | if (save_reg_p (CR0_REGNO + i)) | |
4149 | add_reg_note (insn, REG_CFA_RESTORE, | |
4150 | gen_rtx_REG (SImode, CR0_REGNO + i)); | |
4151 | ||
4152 | RTX_FRAME_RELATED_P (insn) = 1; | |
4153 | } | |
4154 | } | |
4155 | else | |
4156 | for (i = 0; i < 8; i++) | |
4157 | if (save_reg_p (CR0_REGNO + i)) | |
4158 | { | |
4159 | rtx insn = emit_insn (gen_movsi_to_cr_one | |
4160 | (gen_rtx_REG (CCmode, CR0_REGNO + i), reg)); | |
4161 | ||
4162 | /* For the ELFv2 ABI we generate a CFA_RESTORE for each | |
4163 | CR field separately, attached to the insn that in fact | |
4164 | restores this particular CR field. */ | |
4165 | if (!exit_func && DEFAULT_ABI == ABI_ELFv2 && flag_shrink_wrap) | |
4166 | { | |
4167 | add_reg_note (insn, REG_CFA_RESTORE, | |
4168 | gen_rtx_REG (SImode, CR0_REGNO + i)); | |
4169 | ||
4170 | RTX_FRAME_RELATED_P (insn) = 1; | |
4171 | } | |
4172 | } | |
4173 | ||
4174 | /* For other ABIs, we just generate a single CFA_RESTORE for CR2. */ | |
4175 | if (!exit_func && DEFAULT_ABI != ABI_ELFv2 | |
4176 | && (DEFAULT_ABI == ABI_V4 || flag_shrink_wrap)) | |
4177 | { | |
4178 | rtx_insn *insn = get_last_insn (); | |
4179 | rtx cr = gen_rtx_REG (SImode, CR2_REGNO); | |
4180 | ||
4181 | add_reg_note (insn, REG_CFA_RESTORE, cr); | |
4182 | RTX_FRAME_RELATED_P (insn) = 1; | |
4183 | } | |
4184 | } | |
4185 | ||
4186 | /* Like cr, the move to lr instruction can be scheduled after the | |
4187 | stack deallocation, but unlike cr, its stack frame save is still | |
4188 | valid. So we only need to emit the cfa_restore on the correct | |
4189 | instruction. */ | |
4190 | ||
4191 | static void | |
4192 | load_lr_save (int regno, rtx frame_reg_rtx, int offset) | |
4193 | { | |
4194 | rtx mem = gen_frame_mem_offset (Pmode, frame_reg_rtx, offset); | |
4195 | rtx reg = gen_rtx_REG (Pmode, regno); | |
4196 | ||
4197 | emit_move_insn (reg, mem); | |
4198 | } | |
4199 | ||
4200 | static void | |
4201 | restore_saved_lr (int regno, bool exit_func) | |
4202 | { | |
4203 | rtx reg = gen_rtx_REG (Pmode, regno); | |
4204 | rtx lr = gen_rtx_REG (Pmode, LR_REGNO); | |
4205 | rtx_insn *insn = emit_move_insn (lr, reg); | |
4206 | ||
4207 | if (!exit_func && flag_shrink_wrap) | |
4208 | { | |
4209 | add_reg_note (insn, REG_CFA_RESTORE, lr); | |
4210 | RTX_FRAME_RELATED_P (insn) = 1; | |
4211 | } | |
4212 | } | |
4213 | ||
4214 | static rtx | |
4215 | add_crlr_cfa_restore (const rs6000_stack_t *info, rtx cfa_restores) | |
4216 | { | |
4217 | if (DEFAULT_ABI == ABI_ELFv2) | |
4218 | { | |
4219 | int i; | |
4220 | for (i = 0; i < 8; i++) | |
4221 | if (save_reg_p (CR0_REGNO + i)) | |
4222 | { | |
4223 | rtx cr = gen_rtx_REG (SImode, CR0_REGNO + i); | |
4224 | cfa_restores = alloc_reg_note (REG_CFA_RESTORE, cr, | |
4225 | cfa_restores); | |
4226 | } | |
4227 | } | |
4228 | else if (info->cr_save_p) | |
4229 | cfa_restores = alloc_reg_note (REG_CFA_RESTORE, | |
4230 | gen_rtx_REG (SImode, CR2_REGNO), | |
4231 | cfa_restores); | |
4232 | ||
4233 | if (info->lr_save_p) | |
4234 | cfa_restores = alloc_reg_note (REG_CFA_RESTORE, | |
4235 | gen_rtx_REG (Pmode, LR_REGNO), | |
4236 | cfa_restores); | |
4237 | return cfa_restores; | |
4238 | } | |
4239 | ||
4240 | /* Return true if OFFSET from stack pointer can be clobbered by signals. | |
4241 | V.4 doesn't have any stack cushion, AIX ABIs have 220 or 288 bytes | |
4242 | below stack pointer not cloberred by signals. */ | |
4243 | ||
4244 | static inline bool | |
4245 | offset_below_red_zone_p (HOST_WIDE_INT offset) | |
4246 | { | |
4247 | return offset < (DEFAULT_ABI == ABI_V4 | |
4248 | ? 0 | |
4249 | : TARGET_32BIT ? -220 : -288); | |
4250 | } | |
4251 | ||
4252 | /* Append CFA_RESTORES to any existing REG_NOTES on the last insn. */ | |
4253 | ||
4254 | static void | |
4255 | emit_cfa_restores (rtx cfa_restores) | |
4256 | { | |
4257 | rtx_insn *insn = get_last_insn (); | |
4258 | rtx *loc = ®_NOTES (insn); | |
4259 | ||
4260 | while (*loc) | |
4261 | loc = &XEXP (*loc, 1); | |
4262 | *loc = cfa_restores; | |
4263 | RTX_FRAME_RELATED_P (insn) = 1; | |
4264 | } | |
4265 | ||
4266 | /* Emit function epilogue as insns. */ | |
4267 | ||
4268 | void | |
4269 | rs6000_emit_epilogue (enum epilogue_type epilogue_type) | |
4270 | { | |
4271 | HOST_WIDE_INT frame_off = 0; | |
4272 | rtx sp_reg_rtx = gen_rtx_REG (Pmode, 1); | |
4273 | rtx frame_reg_rtx = sp_reg_rtx; | |
4274 | rtx cfa_restores = NULL_RTX; | |
4275 | rtx insn; | |
4276 | rtx cr_save_reg = NULL_RTX; | |
4277 | machine_mode reg_mode = Pmode; | |
4278 | int reg_size = TARGET_32BIT ? 4 : 8; | |
4279 | machine_mode fp_reg_mode = TARGET_HARD_FLOAT ? DFmode : SFmode; | |
4280 | int fp_reg_size = 8; | |
4281 | int i; | |
4282 | unsigned ptr_regno; | |
4283 | ||
4284 | rs6000_stack_t *info = rs6000_stack_info (); | |
4285 | ||
4286 | if (epilogue_type == EPILOGUE_TYPE_NORMAL && crtl->calls_eh_return) | |
4287 | epilogue_type = EPILOGUE_TYPE_EH_RETURN; | |
4288 | ||
4289 | int strategy = info->savres_strategy; | |
4290 | bool using_load_multiple = !!(strategy & REST_MULTIPLE); | |
4291 | bool restoring_GPRs_inline = !!(strategy & REST_INLINE_GPRS); | |
4292 | bool restoring_FPRs_inline = !!(strategy & REST_INLINE_FPRS); | |
4293 | if (epilogue_type == EPILOGUE_TYPE_SIBCALL) | |
4294 | { | |
4295 | restoring_GPRs_inline = true; | |
4296 | restoring_FPRs_inline = true; | |
4297 | } | |
4298 | ||
4299 | bool using_mtcr_multiple = (rs6000_tune == PROCESSOR_PPC601 | |
4300 | || rs6000_tune == PROCESSOR_PPC603 | |
4301 | || rs6000_tune == PROCESSOR_PPC750 | |
4302 | || optimize_size); | |
4303 | ||
4304 | /* Restore via the backchain when we have a large frame, since this | |
4305 | is more efficient than an addis, addi pair. The second condition | |
4306 | here will not trigger at the moment; We don't actually need a | |
4307 | frame pointer for alloca, but the generic parts of the compiler | |
4308 | give us one anyway. */ | |
4309 | bool use_backchain_to_restore_sp | |
4310 | = (info->total_size + (info->lr_save_p ? info->lr_save_offset : 0) > 32767 | |
4311 | || (cfun->calls_alloca && !frame_pointer_needed)); | |
4312 | ||
4313 | bool restore_lr = (info->lr_save_p | |
4314 | && (restoring_FPRs_inline | |
4315 | || (strategy & REST_NOINLINE_FPRS_DOESNT_RESTORE_LR)) | |
4316 | && (restoring_GPRs_inline | |
4317 | || info->first_fp_reg_save < 64) | |
4318 | && !cfun->machine->lr_is_wrapped_separately); | |
4319 | ||
4320 | ||
4321 | if (WORLD_SAVE_P (info)) | |
4322 | { | |
4323 | gcc_assert (epilogue_type != EPILOGUE_TYPE_SIBCALL); | |
4324 | ||
4325 | /* eh_rest_world_r10 will return to the location saved in the LR | |
4326 | stack slot (which is not likely to be our caller.) | |
4327 | Input: R10 -- stack adjustment. Clobbers R0, R11, R12, R7, R8. | |
4328 | rest_world is similar, except any R10 parameter is ignored. | |
4329 | The exception-handling stuff that was here in 2.95 is no | |
4330 | longer necessary. */ | |
4331 | ||
4332 | rtvec p; | |
4333 | p = rtvec_alloc (9 | |
4334 | + 32 - info->first_gp_reg_save | |
4335 | + LAST_ALTIVEC_REGNO + 1 - info->first_altivec_reg_save | |
4336 | + 63 + 1 - info->first_fp_reg_save); | |
4337 | ||
4338 | const char *rname; | |
4339 | switch (epilogue_type) | |
4340 | { | |
4341 | case EPILOGUE_TYPE_NORMAL: | |
4342 | rname = ggc_strdup ("*rest_world"); | |
4343 | break; | |
4344 | ||
4345 | case EPILOGUE_TYPE_EH_RETURN: | |
4346 | rname = ggc_strdup ("*eh_rest_world_r10"); | |
4347 | break; | |
4348 | ||
4349 | default: | |
4350 | gcc_unreachable (); | |
4351 | } | |
4352 | ||
4353 | int j = 0; | |
4354 | RTVEC_ELT (p, j++) = ret_rtx; | |
4355 | RTVEC_ELT (p, j++) | |
4356 | = gen_rtx_USE (VOIDmode, gen_rtx_SYMBOL_REF (Pmode, rname)); | |
4357 | /* The instruction pattern requires a clobber here; | |
4358 | it is shared with the restVEC helper. */ | |
4359 | RTVEC_ELT (p, j++) = gen_hard_reg_clobber (Pmode, 11); | |
4360 | ||
4361 | { | |
4362 | /* CR register traditionally saved as CR2. */ | |
4363 | rtx reg = gen_rtx_REG (SImode, CR2_REGNO); | |
4364 | RTVEC_ELT (p, j++) | |
4365 | = gen_frame_load (reg, frame_reg_rtx, info->cr_save_offset); | |
4366 | if (flag_shrink_wrap) | |
4367 | { | |
4368 | cfa_restores = alloc_reg_note (REG_CFA_RESTORE, | |
4369 | gen_rtx_REG (Pmode, LR_REGNO), | |
4370 | cfa_restores); | |
4371 | cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores); | |
4372 | } | |
4373 | } | |
4374 | ||
4375 | int i; | |
4376 | for (i = 0; i < 32 - info->first_gp_reg_save; i++) | |
4377 | { | |
4378 | rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i); | |
4379 | RTVEC_ELT (p, j++) | |
4380 | = gen_frame_load (reg, | |
4381 | frame_reg_rtx, info->gp_save_offset + reg_size * i); | |
4382 | if (flag_shrink_wrap | |
4383 | && save_reg_p (info->first_gp_reg_save + i)) | |
4384 | cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores); | |
4385 | } | |
4386 | for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++) | |
4387 | { | |
4388 | rtx reg = gen_rtx_REG (V4SImode, info->first_altivec_reg_save + i); | |
4389 | RTVEC_ELT (p, j++) | |
4390 | = gen_frame_load (reg, | |
4391 | frame_reg_rtx, info->altivec_save_offset + 16 * i); | |
4392 | if (flag_shrink_wrap | |
4393 | && save_reg_p (info->first_altivec_reg_save + i)) | |
4394 | cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores); | |
4395 | } | |
4396 | for (i = 0; info->first_fp_reg_save + i <= 63; i++) | |
4397 | { | |
4398 | rtx reg = gen_rtx_REG (TARGET_HARD_FLOAT ? DFmode : SFmode, | |
4399 | info->first_fp_reg_save + i); | |
4400 | RTVEC_ELT (p, j++) | |
4401 | = gen_frame_load (reg, frame_reg_rtx, info->fp_save_offset + 8 * i); | |
4402 | if (flag_shrink_wrap | |
4403 | && save_reg_p (info->first_fp_reg_save + i)) | |
4404 | cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores); | |
4405 | } | |
4406 | RTVEC_ELT (p, j++) = gen_hard_reg_clobber (Pmode, 0); | |
4407 | RTVEC_ELT (p, j++) = gen_hard_reg_clobber (SImode, 12); | |
4408 | RTVEC_ELT (p, j++) = gen_hard_reg_clobber (SImode, 7); | |
4409 | RTVEC_ELT (p, j++) = gen_hard_reg_clobber (SImode, 8); | |
4410 | RTVEC_ELT (p, j++) | |
4411 | = gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, 10)); | |
4412 | insn = emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p)); | |
4413 | ||
4414 | if (flag_shrink_wrap) | |
4415 | { | |
4416 | REG_NOTES (insn) = cfa_restores; | |
4417 | add_reg_note (insn, REG_CFA_DEF_CFA, sp_reg_rtx); | |
4418 | RTX_FRAME_RELATED_P (insn) = 1; | |
4419 | } | |
4420 | return; | |
4421 | } | |
4422 | ||
4423 | /* frame_reg_rtx + frame_off points to the top of this stack frame. */ | |
4424 | if (info->push_p) | |
4425 | frame_off = info->total_size; | |
4426 | ||
4427 | /* Restore AltiVec registers if we must do so before adjusting the | |
4428 | stack. */ | |
4429 | if (info->altivec_size != 0 | |
4430 | && (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP | |
4431 | || (DEFAULT_ABI != ABI_V4 | |
4432 | && offset_below_red_zone_p (info->altivec_save_offset)))) | |
4433 | { | |
4434 | int i; | |
4435 | int scratch_regno = ptr_regno_for_savres (SAVRES_VR); | |
4436 | ||
4437 | gcc_checking_assert (scratch_regno == 11 || scratch_regno == 12); | |
4438 | if (use_backchain_to_restore_sp) | |
4439 | { | |
4440 | int frame_regno = 11; | |
4441 | ||
4442 | if ((strategy & REST_INLINE_VRS) == 0) | |
4443 | { | |
4444 | /* Of r11 and r12, select the one not clobbered by an | |
4445 | out-of-line restore function for the frame register. */ | |
4446 | frame_regno = 11 + 12 - scratch_regno; | |
4447 | } | |
4448 | frame_reg_rtx = gen_rtx_REG (Pmode, frame_regno); | |
4449 | emit_move_insn (frame_reg_rtx, | |
4450 | gen_rtx_MEM (Pmode, sp_reg_rtx)); | |
4451 | frame_off = 0; | |
4452 | } | |
4453 | else if (frame_pointer_needed) | |
4454 | frame_reg_rtx = hard_frame_pointer_rtx; | |
4455 | ||
4456 | if ((strategy & REST_INLINE_VRS) == 0) | |
4457 | { | |
4458 | int end_save = info->altivec_save_offset + info->altivec_size; | |
4459 | int ptr_off; | |
4460 | rtx ptr_reg = gen_rtx_REG (Pmode, 0); | |
4461 | rtx scratch_reg = gen_rtx_REG (Pmode, scratch_regno); | |
4462 | ||
4463 | if (end_save + frame_off != 0) | |
4464 | { | |
4465 | rtx offset = GEN_INT (end_save + frame_off); | |
4466 | ||
4467 | emit_insn (gen_add3_insn (ptr_reg, frame_reg_rtx, offset)); | |
4468 | } | |
4469 | else | |
4470 | emit_move_insn (ptr_reg, frame_reg_rtx); | |
4471 | ||
4472 | ptr_off = -end_save; | |
4473 | insn = rs6000_emit_savres_rtx (info, scratch_reg, | |
4474 | info->altivec_save_offset + ptr_off, | |
4475 | 0, V4SImode, SAVRES_VR); | |
4476 | } | |
4477 | else | |
4478 | { | |
4479 | for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i) | |
4480 | if (info->vrsave_mask & ALTIVEC_REG_BIT (i)) | |
4481 | { | |
4482 | rtx addr, areg, mem, insn; | |
4483 | rtx reg = gen_rtx_REG (V4SImode, i); | |
4484 | HOST_WIDE_INT offset | |
4485 | = (info->altivec_save_offset + frame_off | |
4486 | + 16 * (i - info->first_altivec_reg_save)); | |
4487 | ||
4488 | if (TARGET_P9_VECTOR && quad_address_offset_p (offset)) | |
4489 | { | |
4490 | mem = gen_frame_mem (V4SImode, | |
4491 | gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
4492 | GEN_INT (offset))); | |
4493 | insn = gen_rtx_SET (reg, mem); | |
4494 | } | |
4495 | else | |
4496 | { | |
4497 | areg = gen_rtx_REG (Pmode, 0); | |
4498 | emit_move_insn (areg, GEN_INT (offset)); | |
4499 | ||
4500 | /* AltiVec addressing mode is [reg+reg]. */ | |
4501 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, areg); | |
4502 | mem = gen_frame_mem (V4SImode, addr); | |
4503 | ||
4504 | /* Rather than emitting a generic move, force use of the | |
4505 | lvx instruction, which we always want. In particular we | |
4506 | don't want lxvd2x/xxpermdi for little endian. */ | |
4507 | insn = gen_altivec_lvx_v4si_internal (reg, mem); | |
4508 | } | |
4509 | ||
4510 | (void) emit_insn (insn); | |
4511 | } | |
4512 | } | |
4513 | ||
4514 | for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i) | |
4515 | if (((strategy & REST_INLINE_VRS) == 0 | |
4516 | || (info->vrsave_mask & ALTIVEC_REG_BIT (i)) != 0) | |
4517 | && (flag_shrink_wrap | |
4518 | || (offset_below_red_zone_p | |
4519 | (info->altivec_save_offset | |
4520 | + 16 * (i - info->first_altivec_reg_save)))) | |
4521 | && save_reg_p (i)) | |
4522 | { | |
4523 | rtx reg = gen_rtx_REG (V4SImode, i); | |
4524 | cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores); | |
4525 | } | |
4526 | } | |
4527 | ||
4528 | /* Restore VRSAVE if we must do so before adjusting the stack. */ | |
4529 | if (info->vrsave_size != 0 | |
4530 | && (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP | |
4531 | || (DEFAULT_ABI != ABI_V4 | |
4532 | && offset_below_red_zone_p (info->vrsave_save_offset)))) | |
4533 | { | |
4534 | rtx reg; | |
4535 | ||
4536 | if (frame_reg_rtx == sp_reg_rtx) | |
4537 | { | |
4538 | if (use_backchain_to_restore_sp) | |
4539 | { | |
4540 | frame_reg_rtx = gen_rtx_REG (Pmode, 11); | |
4541 | emit_move_insn (frame_reg_rtx, | |
4542 | gen_rtx_MEM (Pmode, sp_reg_rtx)); | |
4543 | frame_off = 0; | |
4544 | } | |
4545 | else if (frame_pointer_needed) | |
4546 | frame_reg_rtx = hard_frame_pointer_rtx; | |
4547 | } | |
4548 | ||
4549 | reg = gen_rtx_REG (SImode, 12); | |
4550 | emit_insn (gen_frame_load (reg, frame_reg_rtx, | |
4551 | info->vrsave_save_offset + frame_off)); | |
4552 | ||
4553 | emit_insn (generate_set_vrsave (reg, info, 1)); | |
4554 | } | |
4555 | ||
4556 | insn = NULL_RTX; | |
4557 | /* If we have a large stack frame, restore the old stack pointer | |
4558 | using the backchain. */ | |
4559 | if (use_backchain_to_restore_sp) | |
4560 | { | |
4561 | if (frame_reg_rtx == sp_reg_rtx) | |
4562 | { | |
4563 | /* Under V.4, don't reset the stack pointer until after we're done | |
4564 | loading the saved registers. */ | |
4565 | if (DEFAULT_ABI == ABI_V4) | |
4566 | frame_reg_rtx = gen_rtx_REG (Pmode, 11); | |
4567 | ||
4568 | insn = emit_move_insn (frame_reg_rtx, | |
4569 | gen_rtx_MEM (Pmode, sp_reg_rtx)); | |
4570 | frame_off = 0; | |
4571 | } | |
4572 | else if (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP | |
4573 | && DEFAULT_ABI == ABI_V4) | |
4574 | /* frame_reg_rtx has been set up by the altivec restore. */ | |
4575 | ; | |
4576 | else | |
4577 | { | |
4578 | insn = emit_move_insn (sp_reg_rtx, frame_reg_rtx); | |
4579 | frame_reg_rtx = sp_reg_rtx; | |
4580 | } | |
4581 | } | |
4582 | /* If we have a frame pointer, we can restore the old stack pointer | |
4583 | from it. */ | |
f6955089 | 4584 | else if (frame_pointer_needed_indeed) |
2c04f847 BS |
4585 | { |
4586 | frame_reg_rtx = sp_reg_rtx; | |
4587 | if (DEFAULT_ABI == ABI_V4) | |
4588 | frame_reg_rtx = gen_rtx_REG (Pmode, 11); | |
4589 | /* Prevent reordering memory accesses against stack pointer restore. */ | |
4590 | else if (cfun->calls_alloca | |
4591 | || offset_below_red_zone_p (-info->total_size)) | |
4592 | rs6000_emit_stack_tie (frame_reg_rtx, true); | |
4593 | ||
4594 | insn = emit_insn (gen_add3_insn (frame_reg_rtx, hard_frame_pointer_rtx, | |
4595 | GEN_INT (info->total_size))); | |
4596 | frame_off = 0; | |
4597 | } | |
4598 | else if (info->push_p | |
4599 | && DEFAULT_ABI != ABI_V4 | |
4600 | && epilogue_type != EPILOGUE_TYPE_EH_RETURN) | |
4601 | { | |
4602 | /* Prevent reordering memory accesses against stack pointer restore. */ | |
4603 | if (cfun->calls_alloca | |
4604 | || offset_below_red_zone_p (-info->total_size)) | |
4605 | rs6000_emit_stack_tie (frame_reg_rtx, false); | |
4606 | insn = emit_insn (gen_add3_insn (sp_reg_rtx, sp_reg_rtx, | |
4607 | GEN_INT (info->total_size))); | |
4608 | frame_off = 0; | |
4609 | } | |
4610 | if (insn && frame_reg_rtx == sp_reg_rtx) | |
4611 | { | |
4612 | if (cfa_restores) | |
4613 | { | |
4614 | REG_NOTES (insn) = cfa_restores; | |
4615 | cfa_restores = NULL_RTX; | |
4616 | } | |
4617 | add_reg_note (insn, REG_CFA_DEF_CFA, sp_reg_rtx); | |
4618 | RTX_FRAME_RELATED_P (insn) = 1; | |
4619 | } | |
4620 | ||
4621 | /* Restore AltiVec registers if we have not done so already. */ | |
4622 | if (!ALWAYS_RESTORE_ALTIVEC_BEFORE_POP | |
4623 | && info->altivec_size != 0 | |
4624 | && (DEFAULT_ABI == ABI_V4 | |
4625 | || !offset_below_red_zone_p (info->altivec_save_offset))) | |
4626 | { | |
4627 | int i; | |
4628 | ||
4629 | if ((strategy & REST_INLINE_VRS) == 0) | |
4630 | { | |
4631 | int end_save = info->altivec_save_offset + info->altivec_size; | |
4632 | int ptr_off; | |
4633 | rtx ptr_reg = gen_rtx_REG (Pmode, 0); | |
4634 | int scratch_regno = ptr_regno_for_savres (SAVRES_VR); | |
4635 | rtx scratch_reg = gen_rtx_REG (Pmode, scratch_regno); | |
4636 | ||
4637 | if (end_save + frame_off != 0) | |
4638 | { | |
4639 | rtx offset = GEN_INT (end_save + frame_off); | |
4640 | ||
4641 | emit_insn (gen_add3_insn (ptr_reg, frame_reg_rtx, offset)); | |
4642 | } | |
4643 | else | |
4644 | emit_move_insn (ptr_reg, frame_reg_rtx); | |
4645 | ||
4646 | ptr_off = -end_save; | |
4647 | insn = rs6000_emit_savres_rtx (info, scratch_reg, | |
4648 | info->altivec_save_offset + ptr_off, | |
4649 | 0, V4SImode, SAVRES_VR); | |
4650 | if (REGNO (frame_reg_rtx) == REGNO (scratch_reg)) | |
4651 | { | |
4652 | /* Frame reg was clobbered by out-of-line save. Restore it | |
4653 | from ptr_reg, and if we are calling out-of-line gpr or | |
4654 | fpr restore set up the correct pointer and offset. */ | |
4655 | unsigned newptr_regno = 1; | |
4656 | if (!restoring_GPRs_inline) | |
4657 | { | |
4658 | bool lr = info->gp_save_offset + info->gp_size == 0; | |
4659 | int sel = SAVRES_GPR | (lr ? SAVRES_LR : 0); | |
4660 | newptr_regno = ptr_regno_for_savres (sel); | |
4661 | end_save = info->gp_save_offset + info->gp_size; | |
4662 | } | |
4663 | else if (!restoring_FPRs_inline) | |
4664 | { | |
4665 | bool lr = !(strategy & REST_NOINLINE_FPRS_DOESNT_RESTORE_LR); | |
4666 | int sel = SAVRES_FPR | (lr ? SAVRES_LR : 0); | |
4667 | newptr_regno = ptr_regno_for_savres (sel); | |
4668 | end_save = info->fp_save_offset + info->fp_size; | |
4669 | } | |
4670 | ||
4671 | if (newptr_regno != 1 && REGNO (frame_reg_rtx) != newptr_regno) | |
4672 | frame_reg_rtx = gen_rtx_REG (Pmode, newptr_regno); | |
4673 | ||
4674 | if (end_save + ptr_off != 0) | |
4675 | { | |
4676 | rtx offset = GEN_INT (end_save + ptr_off); | |
4677 | ||
4678 | frame_off = -end_save; | |
4679 | if (TARGET_32BIT) | |
4680 | emit_insn (gen_addsi3_carry (frame_reg_rtx, | |
4681 | ptr_reg, offset)); | |
4682 | else | |
4683 | emit_insn (gen_adddi3_carry (frame_reg_rtx, | |
4684 | ptr_reg, offset)); | |
4685 | } | |
4686 | else | |
4687 | { | |
4688 | frame_off = ptr_off; | |
4689 | emit_move_insn (frame_reg_rtx, ptr_reg); | |
4690 | } | |
4691 | } | |
4692 | } | |
4693 | else | |
4694 | { | |
4695 | for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i) | |
4696 | if (info->vrsave_mask & ALTIVEC_REG_BIT (i)) | |
4697 | { | |
4698 | rtx addr, areg, mem, insn; | |
4699 | rtx reg = gen_rtx_REG (V4SImode, i); | |
4700 | HOST_WIDE_INT offset | |
4701 | = (info->altivec_save_offset + frame_off | |
4702 | + 16 * (i - info->first_altivec_reg_save)); | |
4703 | ||
4704 | if (TARGET_P9_VECTOR && quad_address_offset_p (offset)) | |
4705 | { | |
4706 | mem = gen_frame_mem (V4SImode, | |
4707 | gen_rtx_PLUS (Pmode, frame_reg_rtx, | |
4708 | GEN_INT (offset))); | |
4709 | insn = gen_rtx_SET (reg, mem); | |
4710 | } | |
4711 | else | |
4712 | { | |
4713 | areg = gen_rtx_REG (Pmode, 0); | |
4714 | emit_move_insn (areg, GEN_INT (offset)); | |
4715 | ||
4716 | /* AltiVec addressing mode is [reg+reg]. */ | |
4717 | addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, areg); | |
4718 | mem = gen_frame_mem (V4SImode, addr); | |
4719 | ||
4720 | /* Rather than emitting a generic move, force use of the | |
4721 | lvx instruction, which we always want. In particular we | |
4722 | don't want lxvd2x/xxpermdi for little endian. */ | |
4723 | insn = gen_altivec_lvx_v4si_internal (reg, mem); | |
4724 | } | |
4725 | ||
4726 | (void) emit_insn (insn); | |
4727 | } | |
4728 | } | |
4729 | ||
4730 | for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i) | |
4731 | if (((strategy & REST_INLINE_VRS) == 0 | |
4732 | || (info->vrsave_mask & ALTIVEC_REG_BIT (i)) != 0) | |
4733 | && (DEFAULT_ABI == ABI_V4 || flag_shrink_wrap) | |
4734 | && save_reg_p (i)) | |
4735 | { | |
4736 | rtx reg = gen_rtx_REG (V4SImode, i); | |
4737 | cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores); | |
4738 | } | |
4739 | } | |
4740 | ||
4741 | /* Restore VRSAVE if we have not done so already. */ | |
4742 | if (!ALWAYS_RESTORE_ALTIVEC_BEFORE_POP | |
4743 | && info->vrsave_size != 0 | |
4744 | && (DEFAULT_ABI == ABI_V4 | |
4745 | || !offset_below_red_zone_p (info->vrsave_save_offset))) | |
4746 | { | |
4747 | rtx reg; | |
4748 | ||
4749 | reg = gen_rtx_REG (SImode, 12); | |
4750 | emit_insn (gen_frame_load (reg, frame_reg_rtx, | |
4751 | info->vrsave_save_offset + frame_off)); | |
4752 | ||
4753 | emit_insn (generate_set_vrsave (reg, info, 1)); | |
4754 | } | |
4755 | ||
4756 | /* If we exit by an out-of-line restore function on ABI_V4 then that | |
4757 | function will deallocate the stack, so we don't need to worry | |
4758 | about the unwinder restoring cr from an invalid stack frame | |
4759 | location. */ | |
4760 | bool exit_func = (!restoring_FPRs_inline | |
4761 | || (!restoring_GPRs_inline | |
4762 | && info->first_fp_reg_save == 64)); | |
4763 | ||
4764 | /* In the ELFv2 ABI we need to restore all call-saved CR fields from | |
4765 | *separate* slots if the routine calls __builtin_eh_return, so | |
4766 | that they can be independently restored by the unwinder. */ | |
4767 | if (DEFAULT_ABI == ABI_ELFv2 && crtl->calls_eh_return) | |
4768 | { | |
4769 | int i, cr_off = info->ehcr_offset; | |
4770 | ||
4771 | for (i = 0; i < 8; i++) | |
a365fa06 | 4772 | if (!call_used_or_fixed_reg_p (CR0_REGNO + i)) |
2c04f847 BS |
4773 | { |
4774 | rtx reg = gen_rtx_REG (SImode, 0); | |
4775 | emit_insn (gen_frame_load (reg, frame_reg_rtx, | |
4776 | cr_off + frame_off)); | |
4777 | ||
4778 | insn = emit_insn (gen_movsi_to_cr_one | |
4779 | (gen_rtx_REG (CCmode, CR0_REGNO + i), reg)); | |
4780 | ||
4781 | if (!exit_func && flag_shrink_wrap) | |
4782 | { | |
4783 | add_reg_note (insn, REG_CFA_RESTORE, | |
4784 | gen_rtx_REG (SImode, CR0_REGNO + i)); | |
4785 | ||
4786 | RTX_FRAME_RELATED_P (insn) = 1; | |
4787 | } | |
4788 | ||
4789 | cr_off += reg_size; | |
4790 | } | |
4791 | } | |
4792 | ||
4793 | /* Get the old lr if we saved it. If we are restoring registers | |
4794 | out-of-line, then the out-of-line routines can do this for us. */ | |
4795 | if (restore_lr && restoring_GPRs_inline) | |
4796 | load_lr_save (0, frame_reg_rtx, info->lr_save_offset + frame_off); | |
4797 | ||
4798 | /* Get the old cr if we saved it. */ | |
4799 | if (info->cr_save_p) | |
4800 | { | |
4801 | unsigned cr_save_regno = 12; | |
4802 | ||
4803 | if (!restoring_GPRs_inline) | |
4804 | { | |
4805 | /* Ensure we don't use the register used by the out-of-line | |
4806 | gpr register restore below. */ | |
4807 | bool lr = info->gp_save_offset + info->gp_size == 0; | |
4808 | int sel = SAVRES_GPR | (lr ? SAVRES_LR : 0); | |
4809 | int gpr_ptr_regno = ptr_regno_for_savres (sel); | |
4810 | ||
4811 | if (gpr_ptr_regno == 12) | |
4812 | cr_save_regno = 11; | |
4813 | gcc_checking_assert (REGNO (frame_reg_rtx) != cr_save_regno); | |
4814 | } | |
4815 | else if (REGNO (frame_reg_rtx) == 12) | |
4816 | cr_save_regno = 11; | |
4817 | ||
86e6268c SB |
4818 | /* For ELFv2 r12 is already in use as the GEP. */ |
4819 | if (DEFAULT_ABI == ABI_ELFv2) | |
4820 | cr_save_regno = 11; | |
4821 | ||
2c04f847 BS |
4822 | cr_save_reg = load_cr_save (cr_save_regno, frame_reg_rtx, |
4823 | info->cr_save_offset + frame_off, | |
4824 | exit_func); | |
4825 | } | |
4826 | ||
4827 | /* Set LR here to try to overlap restores below. */ | |
4828 | if (restore_lr && restoring_GPRs_inline) | |
4829 | restore_saved_lr (0, exit_func); | |
4830 | ||
4831 | /* Load exception handler data registers, if needed. */ | |
4832 | if (epilogue_type == EPILOGUE_TYPE_EH_RETURN) | |
4833 | { | |
4834 | unsigned int i, regno; | |
4835 | ||
4836 | if (TARGET_AIX) | |
4837 | { | |
4838 | rtx reg = gen_rtx_REG (reg_mode, 2); | |
4839 | emit_insn (gen_frame_load (reg, frame_reg_rtx, | |
4840 | frame_off + RS6000_TOC_SAVE_SLOT)); | |
4841 | } | |
4842 | ||
4843 | for (i = 0; ; ++i) | |
4844 | { | |
4845 | rtx mem; | |
4846 | ||
4847 | regno = EH_RETURN_DATA_REGNO (i); | |
4848 | if (regno == INVALID_REGNUM) | |
4849 | break; | |
4850 | ||
4851 | mem = gen_frame_mem_offset (reg_mode, frame_reg_rtx, | |
4852 | info->ehrd_offset + frame_off | |
4853 | + reg_size * (int) i); | |
4854 | ||
4855 | emit_move_insn (gen_rtx_REG (reg_mode, regno), mem); | |
4856 | } | |
4857 | } | |
4858 | ||
4859 | /* Restore GPRs. This is done as a PARALLEL if we are using | |
4860 | the load-multiple instructions. */ | |
4861 | if (!restoring_GPRs_inline) | |
4862 | { | |
4863 | /* We are jumping to an out-of-line function. */ | |
4864 | rtx ptr_reg; | |
4865 | int end_save = info->gp_save_offset + info->gp_size; | |
4866 | bool can_use_exit = end_save == 0; | |
4867 | int sel = SAVRES_GPR | (can_use_exit ? SAVRES_LR : 0); | |
4868 | int ptr_off; | |
4869 | ||
4870 | /* Emit stack reset code if we need it. */ | |
4871 | ptr_regno = ptr_regno_for_savres (sel); | |
4872 | ptr_reg = gen_rtx_REG (Pmode, ptr_regno); | |
4873 | if (can_use_exit) | |
4874 | rs6000_emit_stack_reset (frame_reg_rtx, frame_off, ptr_regno); | |
4875 | else if (end_save + frame_off != 0) | |
4876 | emit_insn (gen_add3_insn (ptr_reg, frame_reg_rtx, | |
4877 | GEN_INT (end_save + frame_off))); | |
4878 | else if (REGNO (frame_reg_rtx) != ptr_regno) | |
4879 | emit_move_insn (ptr_reg, frame_reg_rtx); | |
4880 | if (REGNO (frame_reg_rtx) == ptr_regno) | |
4881 | frame_off = -end_save; | |
4882 | ||
4883 | if (can_use_exit && info->cr_save_p) | |
4884 | restore_saved_cr (cr_save_reg, using_mtcr_multiple, true); | |
4885 | ||
4886 | ptr_off = -end_save; | |
4887 | rs6000_emit_savres_rtx (info, ptr_reg, | |
4888 | info->gp_save_offset + ptr_off, | |
4889 | info->lr_save_offset + ptr_off, | |
4890 | reg_mode, sel); | |
4891 | } | |
4892 | else if (using_load_multiple) | |
4893 | { | |
4894 | rtvec p; | |
4895 | p = rtvec_alloc (32 - info->first_gp_reg_save); | |
4896 | for (i = 0; i < 32 - info->first_gp_reg_save; i++) | |
4897 | RTVEC_ELT (p, i) | |
4898 | = gen_frame_load (gen_rtx_REG (reg_mode, info->first_gp_reg_save + i), | |
4899 | frame_reg_rtx, | |
4900 | info->gp_save_offset + frame_off + reg_size * i); | |
4901 | emit_insn (gen_rtx_PARALLEL (VOIDmode, p)); | |
4902 | } | |
4903 | else | |
4904 | { | |
4905 | int offset = info->gp_save_offset + frame_off; | |
4906 | for (i = info->first_gp_reg_save; i < 32; i++) | |
4907 | { | |
4908 | if (save_reg_p (i) | |
4909 | && !cfun->machine->gpr_is_wrapped_separately[i]) | |
4910 | { | |
4911 | rtx reg = gen_rtx_REG (reg_mode, i); | |
4912 | emit_insn (gen_frame_load (reg, frame_reg_rtx, offset)); | |
4913 | } | |
4914 | ||
4915 | offset += reg_size; | |
4916 | } | |
4917 | } | |
4918 | ||
4919 | if (DEFAULT_ABI == ABI_V4 || flag_shrink_wrap) | |
4920 | { | |
4921 | /* If the frame pointer was used then we can't delay emitting | |
4922 | a REG_CFA_DEF_CFA note. This must happen on the insn that | |
4923 | restores the frame pointer, r31. We may have already emitted | |
4924 | a REG_CFA_DEF_CFA note, but that's OK; A duplicate is | |
e53b6e56 | 4925 | discarded by dwarf2cfi.cc/dwarf2out.cc, and in any case would |
2c04f847 BS |
4926 | be harmless if emitted. */ |
4927 | if (frame_pointer_needed) | |
4928 | { | |
4929 | insn = get_last_insn (); | |
4930 | add_reg_note (insn, REG_CFA_DEF_CFA, | |
4931 | plus_constant (Pmode, frame_reg_rtx, frame_off)); | |
4932 | RTX_FRAME_RELATED_P (insn) = 1; | |
4933 | } | |
4934 | ||
4935 | /* Set up cfa_restores. We always need these when | |
4936 | shrink-wrapping. If not shrink-wrapping then we only need | |
4937 | the cfa_restore when the stack location is no longer valid. | |
4938 | The cfa_restores must be emitted on or before the insn that | |
4939 | invalidates the stack, and of course must not be emitted | |
4940 | before the insn that actually does the restore. The latter | |
4941 | is why it is a bad idea to emit the cfa_restores as a group | |
4942 | on the last instruction here that actually does a restore: | |
4943 | That insn may be reordered with respect to others doing | |
4944 | restores. */ | |
4945 | if (flag_shrink_wrap | |
4946 | && !restoring_GPRs_inline | |
4947 | && info->first_fp_reg_save == 64) | |
4948 | cfa_restores = add_crlr_cfa_restore (info, cfa_restores); | |
4949 | ||
4950 | for (i = info->first_gp_reg_save; i < 32; i++) | |
4951 | if (save_reg_p (i) | |
4952 | && !cfun->machine->gpr_is_wrapped_separately[i]) | |
4953 | { | |
4954 | rtx reg = gen_rtx_REG (reg_mode, i); | |
4955 | cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores); | |
4956 | } | |
4957 | } | |
4958 | ||
4959 | if (!restoring_GPRs_inline | |
4960 | && info->first_fp_reg_save == 64) | |
4961 | { | |
4962 | /* We are jumping to an out-of-line function. */ | |
4963 | if (cfa_restores) | |
4964 | emit_cfa_restores (cfa_restores); | |
4965 | return; | |
4966 | } | |
4967 | ||
4968 | if (restore_lr && !restoring_GPRs_inline) | |
4969 | { | |
4970 | load_lr_save (0, frame_reg_rtx, info->lr_save_offset + frame_off); | |
4971 | restore_saved_lr (0, exit_func); | |
4972 | } | |
4973 | ||
4974 | /* Restore fpr's if we need to do it without calling a function. */ | |
4975 | if (restoring_FPRs_inline) | |
4976 | { | |
4977 | int offset = info->fp_save_offset + frame_off; | |
4978 | for (i = info->first_fp_reg_save; i < 64; i++) | |
4979 | { | |
4980 | if (save_reg_p (i) | |
4981 | && !cfun->machine->fpr_is_wrapped_separately[i - 32]) | |
4982 | { | |
4983 | rtx reg = gen_rtx_REG (fp_reg_mode, i); | |
4984 | emit_insn (gen_frame_load (reg, frame_reg_rtx, offset)); | |
4985 | if (DEFAULT_ABI == ABI_V4 || flag_shrink_wrap) | |
4986 | cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, | |
4987 | cfa_restores); | |
4988 | } | |
4989 | ||
4990 | offset += fp_reg_size; | |
4991 | } | |
4992 | } | |
4993 | ||
4994 | /* If we saved cr, restore it here. Just those that were used. */ | |
4995 | if (info->cr_save_p) | |
4996 | restore_saved_cr (cr_save_reg, using_mtcr_multiple, exit_func); | |
4997 | ||
4998 | /* If this is V.4, unwind the stack pointer after all of the loads | |
4999 | have been done, or set up r11 if we are restoring fp out of line. */ | |
5000 | ptr_regno = 1; | |
5001 | if (!restoring_FPRs_inline) | |
5002 | { | |
5003 | bool lr = (strategy & REST_NOINLINE_FPRS_DOESNT_RESTORE_LR) == 0; | |
5004 | int sel = SAVRES_FPR | (lr ? SAVRES_LR : 0); | |
5005 | ptr_regno = ptr_regno_for_savres (sel); | |
5006 | } | |
5007 | ||
5008 | insn = rs6000_emit_stack_reset (frame_reg_rtx, frame_off, ptr_regno); | |
5009 | if (REGNO (frame_reg_rtx) == ptr_regno) | |
5010 | frame_off = 0; | |
5011 | ||
5012 | if (insn && restoring_FPRs_inline) | |
5013 | { | |
5014 | if (cfa_restores) | |
5015 | { | |
5016 | REG_NOTES (insn) = cfa_restores; | |
5017 | cfa_restores = NULL_RTX; | |
5018 | } | |
5019 | add_reg_note (insn, REG_CFA_DEF_CFA, sp_reg_rtx); | |
5020 | RTX_FRAME_RELATED_P (insn) = 1; | |
5021 | } | |
5022 | ||
5023 | if (epilogue_type == EPILOGUE_TYPE_EH_RETURN) | |
5024 | { | |
5025 | rtx sa = EH_RETURN_STACKADJ_RTX; | |
5026 | emit_insn (gen_add3_insn (sp_reg_rtx, sp_reg_rtx, sa)); | |
5027 | } | |
5028 | ||
af979a98 BS |
5029 | /* The ROP hash check must occur after the stack pointer is restored |
5030 | (since the hash involves r1), and is not performed for a sibcall. */ | |
5031 | if (TARGET_POWER10 | |
5032 | && rs6000_rop_protect | |
5033 | && info->rop_hash_size != 0 | |
5034 | && epilogue_type != EPILOGUE_TYPE_SIBCALL) | |
5035 | { | |
5036 | gcc_assert (DEFAULT_ABI == ABI_ELFv2); | |
5037 | rtx stack_ptr = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM); | |
5038 | rtx addr = gen_rtx_PLUS (Pmode, stack_ptr, | |
5039 | GEN_INT (info->rop_hash_save_offset)); | |
5040 | rtx mem = gen_rtx_MEM (Pmode, addr); | |
5041 | rtx reg0 = gen_rtx_REG (Pmode, 0); | |
5042 | emit_insn (gen_hashchk (reg0, mem)); | |
5043 | } | |
5044 | ||
2c04f847 BS |
5045 | if (epilogue_type != EPILOGUE_TYPE_SIBCALL && restoring_FPRs_inline) |
5046 | { | |
5047 | if (cfa_restores) | |
5048 | { | |
5049 | /* We can't hang the cfa_restores off a simple return, | |
5050 | since the shrink-wrap code sometimes uses an existing | |
5051 | return. This means there might be a path from | |
5052 | pre-prologue code to this return, and dwarf2cfi code | |
5053 | wants the eh_frame unwinder state to be the same on | |
5054 | all paths to any point. So we need to emit the | |
5055 | cfa_restores before the return. For -m64 we really | |
5056 | don't need epilogue cfa_restores at all, except for | |
5057 | this irritating dwarf2cfi with shrink-wrap | |
5058 | requirement; The stack red-zone means eh_frame info | |
5059 | from the prologue telling the unwinder to restore | |
5060 | from the stack is perfectly good right to the end of | |
5061 | the function. */ | |
5062 | emit_insn (gen_blockage ()); | |
5063 | emit_cfa_restores (cfa_restores); | |
5064 | cfa_restores = NULL_RTX; | |
5065 | } | |
5066 | ||
5067 | emit_jump_insn (targetm.gen_simple_return ()); | |
5068 | } | |
5069 | ||
5070 | if (epilogue_type != EPILOGUE_TYPE_SIBCALL && !restoring_FPRs_inline) | |
5071 | { | |
5072 | bool lr = (strategy & REST_NOINLINE_FPRS_DOESNT_RESTORE_LR) == 0; | |
5073 | rtvec p = rtvec_alloc (3 + !!lr + 64 - info->first_fp_reg_save); | |
5074 | int elt = 0; | |
5075 | RTVEC_ELT (p, elt++) = ret_rtx; | |
5076 | if (lr) | |
5077 | RTVEC_ELT (p, elt++) = gen_hard_reg_clobber (Pmode, LR_REGNO); | |
5078 | ||
5079 | /* We have to restore more than two FP registers, so branch to the | |
5080 | restore function. It will return to our caller. */ | |
5081 | int i; | |
5082 | int reg; | |
5083 | rtx sym; | |
5084 | ||
5085 | if (flag_shrink_wrap) | |
5086 | cfa_restores = add_crlr_cfa_restore (info, cfa_restores); | |
5087 | ||
5088 | sym = rs6000_savres_routine_sym (info, SAVRES_FPR | (lr ? SAVRES_LR : 0)); | |
5089 | RTVEC_ELT (p, elt++) = gen_rtx_USE (VOIDmode, sym); | |
5090 | reg = (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)? 1 : 11; | |
5091 | RTVEC_ELT (p, elt++) = gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, reg)); | |
5092 | ||
5093 | for (i = 0; i < 64 - info->first_fp_reg_save; i++) | |
5094 | { | |
5095 | rtx reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i); | |
5096 | ||
5097 | RTVEC_ELT (p, elt++) | |
5098 | = gen_frame_load (reg, sp_reg_rtx, info->fp_save_offset + 8 * i); | |
5099 | if (flag_shrink_wrap | |
5100 | && save_reg_p (info->first_fp_reg_save + i)) | |
5101 | cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores); | |
5102 | } | |
5103 | ||
5104 | emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p)); | |
5105 | } | |
5106 | ||
5107 | if (cfa_restores) | |
5108 | { | |
5109 | if (epilogue_type == EPILOGUE_TYPE_SIBCALL) | |
5110 | /* Ensure the cfa_restores are hung off an insn that won't | |
5111 | be reordered above other restores. */ | |
5112 | emit_insn (gen_blockage ()); | |
5113 | ||
5114 | emit_cfa_restores (cfa_restores); | |
5115 | } | |
5116 | } | |
5117 | ||
9ff33839 IS |
5118 | #if TARGET_MACHO |
5119 | ||
5120 | /* Generate far-jump branch islands for everything recorded in | |
5121 | branch_islands. Invoked immediately after the last instruction of | |
5122 | the epilogue has been emitted; the branch islands must be appended | |
5123 | to, and contiguous with, the function body. Mach-O stubs are | |
5124 | generated in machopic_output_stub(). */ | |
5125 | ||
5126 | static void | |
5127 | macho_branch_islands (void) | |
5128 | { | |
5129 | char tmp_buf[512]; | |
5130 | ||
5131 | while (!vec_safe_is_empty (branch_islands)) | |
5132 | { | |
5133 | branch_island *bi = &branch_islands->last (); | |
5134 | const char *label = IDENTIFIER_POINTER (bi->label_name); | |
5135 | const char *name = IDENTIFIER_POINTER (bi->function_name); | |
5136 | char name_buf[512]; | |
5137 | /* Cheap copy of the details from the Darwin ASM_OUTPUT_LABELREF(). */ | |
5138 | if (name[0] == '*' || name[0] == '&') | |
5139 | strcpy (name_buf, name+1); | |
5140 | else | |
5141 | { | |
5142 | name_buf[0] = '_'; | |
5143 | strcpy (name_buf+1, name); | |
5144 | } | |
5145 | strcpy (tmp_buf, "\n"); | |
5146 | strcat (tmp_buf, label); | |
5147 | #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO) | |
5148 | if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG) | |
5149 | dbxout_stabd (N_SLINE, bi->line_number); | |
5150 | #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */ | |
5151 | if (flag_pic) | |
5152 | { | |
9eb5f744 IS |
5153 | strcat (tmp_buf, ":\n\tmflr r0\n\tbcl 20,31,"); |
5154 | strcat (tmp_buf, label); | |
5155 | strcat (tmp_buf, "_pic\n"); | |
5156 | strcat (tmp_buf, label); | |
5157 | strcat (tmp_buf, "_pic:\n\tmflr r11\n"); | |
9ff33839 IS |
5158 | |
5159 | strcat (tmp_buf, "\taddis r11,r11,ha16("); | |
5160 | strcat (tmp_buf, name_buf); | |
5161 | strcat (tmp_buf, " - "); | |
5162 | strcat (tmp_buf, label); | |
5163 | strcat (tmp_buf, "_pic)\n"); | |
5164 | ||
5165 | strcat (tmp_buf, "\tmtlr r0\n"); | |
5166 | ||
5167 | strcat (tmp_buf, "\taddi r12,r11,lo16("); | |
5168 | strcat (tmp_buf, name_buf); | |
5169 | strcat (tmp_buf, " - "); | |
5170 | strcat (tmp_buf, label); | |
5171 | strcat (tmp_buf, "_pic)\n"); | |
5172 | ||
5173 | strcat (tmp_buf, "\tmtctr r12\n\tbctr\n"); | |
5174 | } | |
5175 | else | |
5176 | { | |
5177 | strcat (tmp_buf, ":\n\tlis r12,hi16("); | |
5178 | strcat (tmp_buf, name_buf); | |
5179 | strcat (tmp_buf, ")\n\tori r12,r12,lo16("); | |
5180 | strcat (tmp_buf, name_buf); | |
5181 | strcat (tmp_buf, ")\n\tmtctr r12\n\tbctr"); | |
5182 | } | |
5183 | output_asm_insn (tmp_buf, 0); | |
5184 | #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO) | |
5185 | if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG) | |
5186 | dbxout_stabd (N_SLINE, bi->line_number); | |
5187 | #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */ | |
5188 | branch_islands->pop (); | |
5189 | } | |
5190 | } | |
5191 | #endif | |
5192 | ||
2c04f847 BS |
5193 | /* Write function epilogue. */ |
5194 | ||
5195 | void | |
5196 | rs6000_output_function_epilogue (FILE *file) | |
5197 | { | |
5198 | #if TARGET_MACHO | |
5199 | macho_branch_islands (); | |
5200 | ||
5201 | { | |
5202 | rtx_insn *insn = get_last_insn (); | |
5203 | rtx_insn *deleted_debug_label = NULL; | |
5204 | ||
5205 | /* Mach-O doesn't support labels at the end of objects, so if | |
5206 | it looks like we might want one, take special action. | |
5207 | ||
5208 | First, collect any sequence of deleted debug labels. */ | |
5209 | while (insn | |
5210 | && NOTE_P (insn) | |
5211 | && NOTE_KIND (insn) != NOTE_INSN_DELETED_LABEL) | |
5212 | { | |
5213 | /* Don't insert a nop for NOTE_INSN_DELETED_DEBUG_LABEL | |
5214 | notes only, instead set their CODE_LABEL_NUMBER to -1, | |
5215 | otherwise there would be code generation differences | |
5216 | in between -g and -g0. */ | |
5217 | if (NOTE_P (insn) && NOTE_KIND (insn) == NOTE_INSN_DELETED_DEBUG_LABEL) | |
5218 | deleted_debug_label = insn; | |
5219 | insn = PREV_INSN (insn); | |
5220 | } | |
5221 | ||
5222 | /* Second, if we have: | |
5223 | label: | |
5224 | barrier | |
5225 | then this needs to be detected, so skip past the barrier. */ | |
5226 | ||
5227 | if (insn && BARRIER_P (insn)) | |
5228 | insn = PREV_INSN (insn); | |
5229 | ||
5230 | /* Up to now we've only seen notes or barriers. */ | |
5231 | if (insn) | |
5232 | { | |
5233 | if (LABEL_P (insn) | |
5234 | || (NOTE_P (insn) | |
5235 | && NOTE_KIND (insn) == NOTE_INSN_DELETED_LABEL)) | |
5236 | /* Trailing label: <barrier>. */ | |
5237 | fputs ("\tnop\n", file); | |
5238 | else | |
5239 | { | |
5240 | /* Lastly, see if we have a completely empty function body. */ | |
5241 | while (insn && ! INSN_P (insn)) | |
5242 | insn = PREV_INSN (insn); | |
5243 | /* If we don't find any insns, we've got an empty function body; | |
5244 | I.e. completely empty - without a return or branch. This is | |
5245 | taken as the case where a function body has been removed | |
5246 | because it contains an inline __builtin_unreachable(). GCC | |
5247 | states that reaching __builtin_unreachable() means UB so we're | |
5248 | not obliged to do anything special; however, we want | |
5249 | non-zero-sized function bodies. To meet this, and help the | |
5250 | user out, let's trap the case. */ | |
5251 | if (insn == NULL) | |
5252 | fputs ("\ttrap\n", file); | |
5253 | } | |
5254 | } | |
5255 | else if (deleted_debug_label) | |
5256 | for (insn = deleted_debug_label; insn; insn = NEXT_INSN (insn)) | |
5257 | if (NOTE_KIND (insn) == NOTE_INSN_DELETED_DEBUG_LABEL) | |
5258 | CODE_LABEL_NUMBER (insn) = -1; | |
5259 | } | |
5260 | #endif | |
5261 | ||
5262 | /* Output a traceback table here. See /usr/include/sys/debug.h for info | |
5263 | on its format. | |
5264 | ||
5265 | We don't output a traceback table if -finhibit-size-directive was | |
5266 | used. The documentation for -finhibit-size-directive reads | |
5267 | ``don't output a @code{.size} assembler directive, or anything | |
5268 | else that would cause trouble if the function is split in the | |
5269 | middle, and the two halves are placed at locations far apart in | |
5270 | memory.'' The traceback table has this property, since it | |
5271 | includes the offset from the start of the function to the | |
5272 | traceback table itself. | |
5273 | ||
5274 | System V.4 Powerpc's (and the embedded ABI derived from it) use a | |
5275 | different traceback table. */ | |
5276 | if ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2) | |
5277 | && ! flag_inhibit_size_directive | |
5278 | && rs6000_traceback != traceback_none && !cfun->is_thunk) | |
5279 | { | |
5280 | const char *fname = NULL; | |
5281 | const char *language_string = lang_hooks.name; | |
5282 | int fixed_parms = 0, float_parms = 0, parm_info = 0; | |
5283 | int i; | |
5284 | int optional_tbtab; | |
5285 | rs6000_stack_t *info = rs6000_stack_info (); | |
5286 | ||
5287 | if (rs6000_traceback == traceback_full) | |
5288 | optional_tbtab = 1; | |
5289 | else if (rs6000_traceback == traceback_part) | |
5290 | optional_tbtab = 0; | |
5291 | else | |
5292 | optional_tbtab = !optimize_size && !TARGET_ELF; | |
5293 | ||
5294 | if (optional_tbtab) | |
5295 | { | |
5296 | fname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0); | |
5297 | while (*fname == '.') /* V.4 encodes . in the name */ | |
5298 | fname++; | |
5299 | ||
5300 | /* Need label immediately before tbtab, so we can compute | |
5301 | its offset from the function start. */ | |
5302 | ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT"); | |
5303 | ASM_OUTPUT_LABEL (file, fname); | |
5304 | } | |
5305 | ||
5306 | /* The .tbtab pseudo-op can only be used for the first eight | |
5307 | expressions, since it can't handle the possibly variable | |
5308 | length fields that follow. However, if you omit the optional | |
5309 | fields, the assembler outputs zeros for all optional fields | |
5310 | anyways, giving each variable length field is minimum length | |
5311 | (as defined in sys/debug.h). Thus we cannot use the .tbtab | |
5312 | pseudo-op at all. */ | |
5313 | ||
5314 | /* An all-zero word flags the start of the tbtab, for debuggers | |
5315 | that have to find it by searching forward from the entry | |
5316 | point or from the current pc. */ | |
5317 | fputs ("\t.long 0\n", file); | |
5318 | ||
5319 | /* Tbtab format type. Use format type 0. */ | |
5320 | fputs ("\t.byte 0,", file); | |
5321 | ||
5322 | /* Language type. Unfortunately, there does not seem to be any | |
5323 | official way to discover the language being compiled, so we | |
5324 | use language_string. | |
998175f6 | 5325 | C is 0. Fortran is 1. Ada is 3. Modula-2 is 8. C++ is 9. |
2c04f847 BS |
5326 | Java is 13. Objective-C is 14. Objective-C++ isn't assigned |
5327 | a number, so for now use 9. LTO, Go, D, and JIT aren't assigned | |
5328 | numbers either, so for now use 0. */ | |
5329 | if (lang_GNU_C () | |
5330 | || ! strcmp (language_string, "GNU GIMPLE") | |
5331 | || ! strcmp (language_string, "GNU Go") | |
5332 | || ! strcmp (language_string, "GNU D") | |
5333 | || ! strcmp (language_string, "libgccjit")) | |
5334 | i = 0; | |
5335 | else if (! strcmp (language_string, "GNU F77") | |
5336 | || lang_GNU_Fortran ()) | |
5337 | i = 1; | |
5338 | else if (! strcmp (language_string, "GNU Ada")) | |
5339 | i = 3; | |
e617512f SB |
5340 | else if (! strcmp (language_string, "GNU Modula-2")) |
5341 | i = 8; | |
2c04f847 BS |
5342 | else if (lang_GNU_CXX () |
5343 | || ! strcmp (language_string, "GNU Objective-C++")) | |
5344 | i = 9; | |
5345 | else if (! strcmp (language_string, "GNU Java")) | |
5346 | i = 13; | |
5347 | else if (! strcmp (language_string, "GNU Objective-C")) | |
5348 | i = 14; | |
5349 | else | |
5350 | gcc_unreachable (); | |
5351 | fprintf (file, "%d,", i); | |
5352 | ||
5353 | /* 8 single bit fields: global linkage (not set for C extern linkage, | |
5354 | apparently a PL/I convention?), out-of-line epilogue/prologue, offset | |
5355 | from start of procedure stored in tbtab, internal function, function | |
5356 | has controlled storage, function has no toc, function uses fp, | |
5357 | function logs/aborts fp operations. */ | |
5358 | /* Assume that fp operations are used if any fp reg must be saved. */ | |
5359 | fprintf (file, "%d,", | |
5360 | (optional_tbtab << 5) | ((info->first_fp_reg_save != 64) << 1)); | |
5361 | ||
5362 | /* 6 bitfields: function is interrupt handler, name present in | |
5363 | proc table, function calls alloca, on condition directives | |
5364 | (controls stack walks, 3 bits), saves condition reg, saves | |
5365 | link reg. */ | |
5366 | /* The `function calls alloca' bit seems to be set whenever reg 31 is | |
5367 | set up as a frame pointer, even when there is no alloca call. */ | |
5368 | fprintf (file, "%d,", | |
5369 | ((optional_tbtab << 6) | |
5370 | | ((optional_tbtab & frame_pointer_needed) << 5) | |
5371 | | (info->cr_save_p << 1) | |
5372 | | (info->lr_save_p))); | |
5373 | ||
5374 | /* 3 bitfields: saves backchain, fixup code, number of fpr saved | |
5375 | (6 bits). */ | |
5376 | fprintf (file, "%d,", | |
5377 | (info->push_p << 7) | (64 - info->first_fp_reg_save)); | |
5378 | ||
5379 | /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */ | |
5380 | fprintf (file, "%d,", (32 - first_reg_to_save ())); | |
5381 | ||
5382 | if (optional_tbtab) | |
5383 | { | |
5384 | /* Compute the parameter info from the function decl argument | |
5385 | list. */ | |
5386 | tree decl; | |
5387 | int next_parm_info_bit = 31; | |
5388 | ||
5389 | for (decl = DECL_ARGUMENTS (current_function_decl); | |
5390 | decl; decl = DECL_CHAIN (decl)) | |
5391 | { | |
5392 | rtx parameter = DECL_INCOMING_RTL (decl); | |
5393 | machine_mode mode = GET_MODE (parameter); | |
5394 | ||
5395 | if (REG_P (parameter)) | |
5396 | { | |
5397 | if (SCALAR_FLOAT_MODE_P (mode)) | |
5398 | { | |
5399 | int bits; | |
5400 | ||
5401 | float_parms++; | |
5402 | ||
5403 | switch (mode) | |
5404 | { | |
5405 | case E_SFmode: | |
5406 | case E_SDmode: | |
5407 | bits = 0x2; | |
5408 | break; | |
5409 | ||
5410 | case E_DFmode: | |
5411 | case E_DDmode: | |
5412 | case E_TFmode: | |
5413 | case E_TDmode: | |
5414 | case E_IFmode: | |
5415 | case E_KFmode: | |
5416 | bits = 0x3; | |
5417 | break; | |
5418 | ||
5419 | default: | |
5420 | gcc_unreachable (); | |
5421 | } | |
5422 | ||
5423 | /* If only one bit will fit, don't or in this entry. */ | |
5424 | if (next_parm_info_bit > 0) | |
5425 | parm_info |= (bits << (next_parm_info_bit - 1)); | |
5426 | next_parm_info_bit -= 2; | |
5427 | } | |
5428 | else | |
5429 | { | |
5430 | fixed_parms += ((GET_MODE_SIZE (mode) | |
5431 | + (UNITS_PER_WORD - 1)) | |
5432 | / UNITS_PER_WORD); | |
5433 | next_parm_info_bit -= 1; | |
5434 | } | |
5435 | } | |
5436 | } | |
5437 | } | |
5438 | ||
5439 | /* Number of fixed point parameters. */ | |
5440 | /* This is actually the number of words of fixed point parameters; thus | |
5441 | an 8 byte struct counts as 2; and thus the maximum value is 8. */ | |
5442 | fprintf (file, "%d,", fixed_parms); | |
5443 | ||
5444 | /* 2 bitfields: number of floating point parameters (7 bits), parameters | |
5445 | all on stack. */ | |
5446 | /* This is actually the number of fp registers that hold parameters; | |
5447 | and thus the maximum value is 13. */ | |
5448 | /* Set parameters on stack bit if parameters are not in their original | |
5449 | registers, regardless of whether they are on the stack? Xlc | |
5450 | seems to set the bit when not optimizing. */ | |
5451 | fprintf (file, "%d\n", ((float_parms << 1) | (! optimize))); | |
5452 | ||
5453 | if (optional_tbtab) | |
5454 | { | |
5455 | /* Optional fields follow. Some are variable length. */ | |
5456 | ||
5457 | /* Parameter types, left adjusted bit fields: 0 fixed, 10 single | |
5458 | float, 11 double float. */ | |
5459 | /* There is an entry for each parameter in a register, in the order | |
5460 | that they occur in the parameter list. Any intervening arguments | |
5461 | on the stack are ignored. If the list overflows a long (max | |
5462 | possible length 34 bits) then completely leave off all elements | |
5463 | that don't fit. */ | |
5464 | /* Only emit this long if there was at least one parameter. */ | |
5465 | if (fixed_parms || float_parms) | |
5466 | fprintf (file, "\t.long %d\n", parm_info); | |
5467 | ||
5468 | /* Offset from start of code to tb table. */ | |
5469 | fputs ("\t.long ", file); | |
5470 | ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT"); | |
5471 | RS6000_OUTPUT_BASENAME (file, fname); | |
5472 | putc ('-', file); | |
5473 | rs6000_output_function_entry (file, fname); | |
5474 | putc ('\n', file); | |
5475 | ||
5476 | /* Interrupt handler mask. */ | |
5477 | /* Omit this long, since we never set the interrupt handler bit | |
5478 | above. */ | |
5479 | ||
5480 | /* Number of CTL (controlled storage) anchors. */ | |
5481 | /* Omit this long, since the has_ctl bit is never set above. */ | |
5482 | ||
5483 | /* Displacement into stack of each CTL anchor. */ | |
5484 | /* Omit this list of longs, because there are no CTL anchors. */ | |
5485 | ||
5486 | /* Length of function name. */ | |
5487 | if (*fname == '*') | |
5488 | ++fname; | |
5489 | fprintf (file, "\t.short %d\n", (int) strlen (fname)); | |
5490 | ||
5491 | /* Function name. */ | |
5492 | assemble_string (fname, strlen (fname)); | |
5493 | ||
5494 | /* Register for alloca automatic storage; this is always reg 31. | |
5495 | Only emit this if the alloca bit was set above. */ | |
5496 | if (frame_pointer_needed) | |
5497 | fputs ("\t.byte 31\n", file); | |
5498 | ||
5499 | fputs ("\t.align 2\n", file); | |
5500 | } | |
5501 | } | |
5502 | ||
5503 | /* Arrange to define .LCTOC1 label, if not already done. */ | |
5504 | if (need_toc_init) | |
5505 | { | |
5506 | need_toc_init = 0; | |
5507 | if (!toc_initialized) | |
5508 | { | |
5509 | switch_to_section (toc_section); | |
5510 | switch_to_section (current_function_section ()); | |
5511 | } | |
5512 | } | |
5513 | } | |
5514 | ||
5515 | /* -fsplit-stack support. */ | |
5516 | ||
5517 | /* A SYMBOL_REF for __morestack. */ | |
5518 | static GTY(()) rtx morestack_ref; | |
5519 | ||
5520 | static rtx | |
5521 | gen_add3_const (rtx rt, rtx ra, long c) | |
5522 | { | |
5523 | if (TARGET_64BIT) | |
5524 | return gen_adddi3 (rt, ra, GEN_INT (c)); | |
5525 | else | |
5526 | return gen_addsi3 (rt, ra, GEN_INT (c)); | |
5527 | } | |
5528 | ||
5529 | /* Emit -fsplit-stack prologue, which goes before the regular function | |
5530 | prologue (at local entry point in the case of ELFv2). */ | |
5531 | ||
5532 | void | |
5533 | rs6000_expand_split_stack_prologue (void) | |
5534 | { | |
5535 | rs6000_stack_t *info = rs6000_stack_info (); | |
5536 | unsigned HOST_WIDE_INT allocate; | |
5537 | long alloc_hi, alloc_lo; | |
5538 | rtx r0, r1, r12, lr, ok_label, compare, jump, call_fusage; | |
5539 | rtx_insn *insn; | |
5540 | ||
5541 | gcc_assert (flag_split_stack && reload_completed); | |
5542 | ||
5543 | if (!info->push_p) | |
199baa71 AM |
5544 | { |
5545 | /* We need the -fsplit-stack prologue for functions that make | |
5546 | tail calls. Tail calls don't count against crtl->is_leaf. | |
5547 | Note that we are called inside a sequence. get_insns will | |
5548 | just return that (as yet empty) sequence, so instead we | |
5549 | access the function rtl with get_topmost_sequence. */ | |
5550 | for (insn = get_topmost_sequence ()->first; insn; insn = NEXT_INSN (insn)) | |
5551 | if (CALL_P (insn)) | |
5552 | break; | |
5553 | if (!insn) | |
5554 | return; | |
5555 | } | |
2c04f847 BS |
5556 | |
5557 | if (global_regs[29]) | |
5558 | { | |
5559 | error ("%qs uses register r29", "%<-fsplit-stack%>"); | |
5560 | inform (DECL_SOURCE_LOCATION (global_regs_decl[29]), | |
5561 | "conflicts with %qD", global_regs_decl[29]); | |
5562 | } | |
5563 | ||
5564 | allocate = info->total_size; | |
5565 | if (allocate > (unsigned HOST_WIDE_INT) 1 << 31) | |
5566 | { | |
5567 | sorry ("Stack frame larger than 2G is not supported for " | |
5568 | "%<-fsplit-stack%>"); | |
5569 | return; | |
5570 | } | |
5571 | if (morestack_ref == NULL_RTX) | |
5572 | { | |
5573 | morestack_ref = gen_rtx_SYMBOL_REF (Pmode, "__morestack"); | |
5574 | SYMBOL_REF_FLAGS (morestack_ref) |= (SYMBOL_FLAG_LOCAL | |
5575 | | SYMBOL_FLAG_FUNCTION); | |
5576 | } | |
5577 | ||
5578 | r0 = gen_rtx_REG (Pmode, 0); | |
5579 | r1 = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM); | |
5580 | r12 = gen_rtx_REG (Pmode, 12); | |
5581 | emit_insn (gen_load_split_stack_limit (r0)); | |
5582 | /* Always emit two insns here to calculate the requested stack, | |
5583 | so that the linker can edit them when adjusting size for calling | |
5584 | non-split-stack code. */ | |
5585 | alloc_hi = (-allocate + 0x8000) & ~0xffffL; | |
5586 | alloc_lo = -allocate - alloc_hi; | |
5587 | if (alloc_hi != 0) | |
5588 | { | |
5589 | emit_insn (gen_add3_const (r12, r1, alloc_hi)); | |
5590 | if (alloc_lo != 0) | |
5591 | emit_insn (gen_add3_const (r12, r12, alloc_lo)); | |
5592 | else | |
5593 | emit_insn (gen_nop ()); | |
5594 | } | |
5595 | else | |
5596 | { | |
5597 | emit_insn (gen_add3_const (r12, r1, alloc_lo)); | |
5598 | emit_insn (gen_nop ()); | |
5599 | } | |
5600 | ||
5601 | compare = gen_rtx_REG (CCUNSmode, CR7_REGNO); | |
5602 | emit_insn (gen_rtx_SET (compare, gen_rtx_COMPARE (CCUNSmode, r12, r0))); | |
5603 | ok_label = gen_label_rtx (); | |
5604 | jump = gen_rtx_IF_THEN_ELSE (VOIDmode, | |
5605 | gen_rtx_GEU (VOIDmode, compare, const0_rtx), | |
5606 | gen_rtx_LABEL_REF (VOIDmode, ok_label), | |
5607 | pc_rtx); | |
5608 | insn = emit_jump_insn (gen_rtx_SET (pc_rtx, jump)); | |
5609 | JUMP_LABEL (insn) = ok_label; | |
5610 | /* Mark the jump as very likely to be taken. */ | |
5611 | add_reg_br_prob_note (insn, profile_probability::very_likely ()); | |
5612 | ||
5613 | lr = gen_rtx_REG (Pmode, LR_REGNO); | |
5614 | insn = emit_move_insn (r0, lr); | |
5615 | RTX_FRAME_RELATED_P (insn) = 1; | |
5616 | insn = emit_insn (gen_frame_store (r0, r1, info->lr_save_offset)); | |
5617 | RTX_FRAME_RELATED_P (insn) = 1; | |
5618 | ||
5619 | insn = emit_call_insn (gen_call (gen_rtx_MEM (SImode, morestack_ref), | |
5620 | const0_rtx, const0_rtx)); | |
5621 | call_fusage = NULL_RTX; | |
5622 | use_reg (&call_fusage, r12); | |
5623 | /* Say the call uses r0, even though it doesn't, to stop regrename | |
5624 | from twiddling with the insns saving lr, trashing args for cfun. | |
5625 | The insns restoring lr are similarly protected by making | |
5626 | split_stack_return use r0. */ | |
5627 | use_reg (&call_fusage, r0); | |
5628 | add_function_usage_to (insn, call_fusage); | |
5629 | /* Indicate that this function can't jump to non-local gotos. */ | |
5630 | make_reg_eh_region_note_nothrow_nononlocal (insn); | |
5631 | emit_insn (gen_frame_load (r0, r1, info->lr_save_offset)); | |
5632 | insn = emit_move_insn (lr, r0); | |
5633 | add_reg_note (insn, REG_CFA_RESTORE, lr); | |
5634 | RTX_FRAME_RELATED_P (insn) = 1; | |
5635 | emit_insn (gen_split_stack_return ()); | |
5636 | ||
5637 | emit_label (ok_label); | |
5638 | LABEL_NUSES (ok_label) = 1; | |
5639 | } | |
5640 | ||
5641 | /* We may have to tell the dataflow pass that the split stack prologue | |
5642 | is initializing a register. */ | |
5643 | ||
5644 | void | |
5645 | rs6000_live_on_entry (bitmap regs) | |
5646 | { | |
5647 | if (flag_split_stack) | |
5648 | bitmap_set_bit (regs, 12); | |
5649 | } | |
5650 | ||
5651 | /* Emit -fsplit-stack dynamic stack allocation space check. */ | |
5652 | ||
5653 | void | |
5654 | rs6000_split_stack_space_check (rtx size, rtx label) | |
5655 | { | |
5656 | rtx sp = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM); | |
5657 | rtx limit = gen_reg_rtx (Pmode); | |
5658 | rtx requested = gen_reg_rtx (Pmode); | |
5659 | rtx cmp = gen_reg_rtx (CCUNSmode); | |
5660 | rtx jump; | |
5661 | ||
5662 | emit_insn (gen_load_split_stack_limit (limit)); | |
5663 | if (CONST_INT_P (size)) | |
5664 | emit_insn (gen_add3_insn (requested, sp, GEN_INT (-INTVAL (size)))); | |
5665 | else | |
5666 | { | |
5667 | size = force_reg (Pmode, size); | |
5668 | emit_move_insn (requested, gen_rtx_MINUS (Pmode, sp, size)); | |
5669 | } | |
5670 | emit_insn (gen_rtx_SET (cmp, gen_rtx_COMPARE (CCUNSmode, requested, limit))); | |
5671 | jump = gen_rtx_IF_THEN_ELSE (VOIDmode, | |
5672 | gen_rtx_GEU (VOIDmode, cmp, const0_rtx), | |
5673 | gen_rtx_LABEL_REF (VOIDmode, label), | |
5674 | pc_rtx); | |
5675 | jump = emit_jump_insn (gen_rtx_SET (pc_rtx, jump)); | |
5676 | JUMP_LABEL (jump) = label; | |
5677 | } | |
5678 | ||
5679 | ||
5680 | /* Return whether we need to always update the saved TOC pointer when we update | |
5681 | the stack pointer. */ | |
5682 | ||
5683 | static bool | |
5684 | rs6000_save_toc_in_prologue_p (void) | |
5685 | { | |
5686 | return (cfun && cfun->machine && cfun->machine->save_toc_in_prologue); | |
5687 | } | |
5688 | ||
5689 | #include "gt-rs6000-logue.h" |