[gcc.git] / gcc / config / rs6000 / rs6000-cpus.def

/* IBM RS/6000 CPU names..
   Copyright (C) 1991-2024 Free Software Foundation, Inc.
   Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)

   This file is part of GCC.

   GCC is free software; you can redistribute it and/or modify it
   under the terms of the GNU General Public License as published
   by the Free Software Foundation; either version 3, or (at your
   option) any later version.

   GCC is distributed in the hope that it will be useful, but WITHOUT
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
   License for more details.

   You should have received a copy of the GNU General Public License
   along with GCC; see the file COPYING3.  If not see
   <http://www.gnu.org/licenses/>.  */

/* ISA masks.  */
#ifndef ISA_2_1_MASKS
#define ISA_2_1_MASKS		OPTION_MASK_MFCRF
#define ISA_2_2_MASKS		(ISA_2_1_MASKS | OPTION_MASK_POPCNTB)
#define ISA_2_4_MASKS		(ISA_2_2_MASKS | OPTION_MASK_FPRND)

  /* For ISA 2.05, don't add ALTIVEC, since in general it isn't a win on
     power6.  In ISA 2.04, fsel, fre, fsqrt, etc. were no longer documented
     as optional.  Group masks by server and embedded. */
#define ISA_2_5_MASKS_EMBEDDED	(ISA_2_4_MASKS				\
				 | OPTION_MASK_CMPB			\
				 | OPTION_MASK_RECIP_PRECISION		\
				 | OPTION_MASK_PPC_GFXOPT		\
				 | OPTION_MASK_PPC_GPOPT)

#define ISA_2_5_MASKS_SERVER	(ISA_2_5_MASKS_EMBEDDED | OPTION_MASK_DFP)

  /* For ISA 2.06, don't add ISEL, since in general it isn't a win, but
     altivec is a win so enable it.  */
#define ISA_2_6_MASKS_EMBEDDED	(ISA_2_5_MASKS_EMBEDDED | OPTION_MASK_POPCNTD)
#define ISA_2_6_MASKS_SERVER	(ISA_2_5_MASKS_SERVER			\
				 | OPTION_MASK_POPCNTD			\
				 | OPTION_MASK_ALTIVEC			\
				 | OPTION_MASK_VSX)

/* For now, don't provide an embedded version of ISA 2.07.  Do not set power8
   fusion here, instead set it in rs6000.cc if we are tuning for a power8
   system.  */
#define ISA_2_7_MASKS_SERVER	(ISA_2_6_MASKS_SERVER			\
				 | OPTION_MASK_P8_VECTOR		\
				 | OPTION_MASK_CRYPTO			\
				 | OPTION_MASK_DIRECT_MOVE		\
				 | OPTION_MASK_EFFICIENT_UNALIGNED_VSX	\
				 | OPTION_MASK_QUAD_MEMORY		\
				 | OPTION_MASK_QUAD_MEMORY_ATOMIC)

/* ISA masks setting fusion options.  */
#define OTHER_FUSION_MASKS	(OPTION_MASK_P8_FUSION			\
				 | OPTION_MASK_P8_FUSION_SIGN)

/* Add ISEL back into ISA 3.0, since it is supposed to be a win.  Do not add
   FLOAT128_HW here until we are ready to make -mfloat128 on by default.  */
#define ISA_3_0_MASKS_SERVER	((ISA_2_7_MASKS_SERVER			\
				  | OPTION_MASK_ISEL			\
				  | OPTION_MASK_MODULO			\
				  | OPTION_MASK_P9_MINMAX		\
				  | OPTION_MASK_P9_MISC			\
				  | OPTION_MASK_P9_VECTOR)		\
				 & ~OTHER_FUSION_MASKS)

/* Support for the IEEE 128-bit floating point hardware requires a lot of the
   VSX instructions that are part of ISA 3.0.  */
#define ISA_3_0_MASKS_IEEE	(OPTION_MASK_VSX			\
				 | OPTION_MASK_P8_VECTOR		\
				 | OPTION_MASK_P9_VECTOR)

/* Flags that need to be turned off if -mno-power10.  */
/* We comment out PCREL_OPT here to disable it by default because SPEC2017
   performance was degraded by it.  */
#define OTHER_POWER10_MASKS	(OPTION_MASK_MMA			\
				 | OPTION_MASK_PCREL			\
				 /* | OPTION_MASK_PCREL_OPT */		\
				 | OPTION_MASK_PREFIXED)

#define ISA_3_1_MASKS_SERVER	(ISA_3_0_MASKS_SERVER			\
				 | OPTION_MASK_POWER10			\
				 | OTHER_POWER10_MASKS)

#define ISA_POWER11_MASKS_SERVER (ISA_3_1_MASKS_SERVER			\
				  | OPTION_MASK_POWER11)

/* Flags that need to be turned off if -mno-vsx.  */
#define OTHER_VSX_VECTOR_MASKS	(OPTION_MASK_EFFICIENT_UNALIGNED_VSX	\
				 | OPTION_MASK_FLOAT128_KEYWORD		\
				 | OPTION_MASK_P8_VECTOR		\
				 | OPTION_MASK_DIRECT_MOVE		\
				 | OPTION_MASK_CRYPTO			\
				 | OPTION_MASK_P9_VECTOR		\
				 | OPTION_MASK_FLOAT128_HW		\
				 | OPTION_MASK_P9_MINMAX)

/* Flags that need to be turned off if -mno-altivec.  */
#define OTHER_ALTIVEC_MASKS	(OTHER_VSX_VECTOR_MASKS			\
				 | OPTION_MASK_VSX)

#define POWERPC_7400_MASK	(OPTION_MASK_PPC_GFXOPT | OPTION_MASK_ALTIVEC)

/* Deal with ports that do not have -mstrict-align.  */
#ifdef OPTION_MASK_STRICT_ALIGN
#define OPTION_MASK_STRICT_ALIGN_OPTIONAL OPTION_MASK_STRICT_ALIGN
#else
#define OPTION_MASK_STRICT_ALIGN 0
#define OPTION_MASK_STRICT_ALIGN_OPTIONAL 0
#ifndef MASK_STRICT_ALIGN
#define MASK_STRICT_ALIGN 0
#endif
#endif

/* Mask of all options to set the default isa flags based on -mcpu=<xxx>.  */
#define POWERPC_MASKS		(OPTION_MASK_ALTIVEC			\
				 | OPTION_MASK_CMPB			\
				 | OPTION_MASK_CRYPTO			\
				 | OPTION_MASK_DFP			\
				 | OPTION_MASK_DIRECT_MOVE		\
				 | OPTION_MASK_DLMZB			\
				 | OPTION_MASK_EFFICIENT_UNALIGNED_VSX	\
				 | OPTION_MASK_FLOAT128_HW		\
				 | OPTION_MASK_FLOAT128_KEYWORD		\
				 | OPTION_MASK_FPRND			\
				 | OPTION_MASK_POWER10			\
				 | OPTION_MASK_POWER11			\
				 | OPTION_MASK_P10_FUSION		\
				 | OPTION_MASK_HTM			\
				 | OPTION_MASK_ISEL			\
				 | OPTION_MASK_MFCRF			\
				 | OPTION_MASK_MMA			\
				 | OPTION_MASK_MODULO			\
				 | OPTION_MASK_MULHW			\
				 | OPTION_MASK_NO_UPDATE		\
				 | OPTION_MASK_P8_FUSION		\
				 | OPTION_MASK_P8_VECTOR		\
				 | OPTION_MASK_P9_MINMAX		\
				 | OPTION_MASK_P9_MISC			\
				 | OPTION_MASK_P9_VECTOR		\
				 | OPTION_MASK_PCREL			\
				 | OPTION_MASK_PCREL_OPT		\
				 | OPTION_MASK_POPCNTB			\
				 | OPTION_MASK_POPCNTD			\
				 | OPTION_MASK_POWERPC64		\
				 | OPTION_MASK_PPC_GFXOPT		\
				 | OPTION_MASK_PPC_GPOPT		\
				 | OPTION_MASK_PREFIXED			\
				 | OPTION_MASK_QUAD_MEMORY		\
				 | OPTION_MASK_QUAD_MEMORY_ATOMIC	\
				 | OPTION_MASK_RECIP_PRECISION		\
				 | OPTION_MASK_SOFT_FLOAT		\
				 | OPTION_MASK_STRICT_ALIGN_OPTIONAL	\
				 | OPTION_MASK_VSX)

#endif

/* This table occasionally claims that a processor does not support a
   particular feature even though it does, but the feature is slower than the
   alternative.  Thus, it shouldn't be relied on as a complete description of
   the processor's support.

   Please keep this list in order, and don't forget to update the documentation
   in invoke.texi when adding a new processor or flag.

   Before including this file, define a macro:

   RS6000_CPU (NAME, CPU, FLAGS)

   where the arguments are the fields of struct rs6000_ptt.  */

RS6000_CPU ("401", PROCESSOR_PPC403, OPTION_MASK_SOFT_FLOAT)
RS6000_CPU ("403", PROCESSOR_PPC403, OPTION_MASK_SOFT_FLOAT | MASK_STRICT_ALIGN)
RS6000_CPU ("405", PROCESSOR_PPC405, OPTION_MASK_SOFT_FLOAT
	    | OPTION_MASK_MULHW | OPTION_MASK_DLMZB)
RS6000_CPU ("405fp", PROCESSOR_PPC405, OPTION_MASK_MULHW | OPTION_MASK_DLMZB)
RS6000_CPU ("440", PROCESSOR_PPC440, OPTION_MASK_SOFT_FLOAT
	    | OPTION_MASK_MULHW | OPTION_MASK_DLMZB)
RS6000_CPU ("440fp", PROCESSOR_PPC440, OPTION_MASK_MULHW | OPTION_MASK_DLMZB)
RS6000_CPU ("464", PROCESSOR_PPC440, OPTION_MASK_SOFT_FLOAT
	    | OPTION_MASK_MULHW | OPTION_MASK_DLMZB)
RS6000_CPU ("464fp", PROCESSOR_PPC440, OPTION_MASK_MULHW | OPTION_MASK_DLMZB)
RS6000_CPU ("476", PROCESSOR_PPC476, OPTION_MASK_SOFT_FLOAT
	    | OPTION_MASK_PPC_GFXOPT | OPTION_MASK_MFCRF | OPTION_MASK_POPCNTB
	    | OPTION_MASK_FPRND | OPTION_MASK_CMPB | OPTION_MASK_MULHW
	    | OPTION_MASK_DLMZB)
RS6000_CPU ("476fp", PROCESSOR_PPC476, OPTION_MASK_PPC_GFXOPT
	    | OPTION_MASK_MFCRF | OPTION_MASK_POPCNTB | OPTION_MASK_FPRND
	    | OPTION_MASK_CMPB | OPTION_MASK_MULHW | OPTION_MASK_DLMZB)
RS6000_CPU ("505", PROCESSOR_MPCCORE, 0)
RS6000_CPU ("601", PROCESSOR_PPC601, OPTION_MASK_MULTIPLE)
RS6000_CPU ("602", PROCESSOR_PPC603, OPTION_MASK_PPC_GFXOPT)
RS6000_CPU ("603", PROCESSOR_PPC603, OPTION_MASK_PPC_GFXOPT)
RS6000_CPU ("603e", PROCESSOR_PPC603, OPTION_MASK_PPC_GFXOPT)
RS6000_CPU ("604", PROCESSOR_PPC604, OPTION_MASK_PPC_GFXOPT)
RS6000_CPU ("604e", PROCESSOR_PPC604e, OPTION_MASK_PPC_GFXOPT)
RS6000_CPU ("620", PROCESSOR_PPC620, OPTION_MASK_PPC_GFXOPT | MASK_POWERPC64)
RS6000_CPU ("630", PROCESSOR_PPC630, OPTION_MASK_PPC_GFXOPT | MASK_POWERPC64)
RS6000_CPU ("740", PROCESSOR_PPC750, OPTION_MASK_PPC_GFXOPT)
RS6000_CPU ("7400", PROCESSOR_PPC7400, POWERPC_7400_MASK)
RS6000_CPU ("7450", PROCESSOR_PPC7450, POWERPC_7400_MASK)
RS6000_CPU ("750", PROCESSOR_PPC750, OPTION_MASK_PPC_GFXOPT)
RS6000_CPU ("801", PROCESSOR_MPCCORE, OPTION_MASK_SOFT_FLOAT)
RS6000_CPU ("821", PROCESSOR_MPCCORE, OPTION_MASK_SOFT_FLOAT)
RS6000_CPU ("823", PROCESSOR_MPCCORE, OPTION_MASK_SOFT_FLOAT)
RS6000_CPU ("8540", PROCESSOR_PPC8540, MASK_STRICT_ALIGN | OPTION_MASK_ISEL)
RS6000_CPU ("8548", PROCESSOR_PPC8548, MASK_STRICT_ALIGN | OPTION_MASK_ISEL)
RS6000_CPU ("a2", PROCESSOR_PPCA2, OPTION_MASK_PPC_GFXOPT | MASK_POWERPC64
	    | OPTION_MASK_POPCNTB | OPTION_MASK_CMPB
	    | OPTION_MASK_NO_UPDATE)
RS6000_CPU ("e300c2", PROCESSOR_PPCE300C2, OPTION_MASK_SOFT_FLOAT)
RS6000_CPU ("e300c3", PROCESSOR_PPCE300C3, 0)
RS6000_CPU ("e500mc", PROCESSOR_PPCE500MC, OPTION_MASK_PPC_GFXOPT
	    | OPTION_MASK_ISEL)
RS6000_CPU ("e500mc64", PROCESSOR_PPCE500MC64,
	    MASK_POWERPC64 | OPTION_MASK_PPC_GFXOPT | OPTION_MASK_ISEL)
RS6000_CPU ("e5500", PROCESSOR_PPCE5500,
	    MASK_POWERPC64 | OPTION_MASK_PPC_GFXOPT | OPTION_MASK_ISEL)
RS6000_CPU ("e6500", PROCESSOR_PPCE6500, POWERPC_7400_MASK | MASK_POWERPC64
	    | OPTION_MASK_MFCRF | OPTION_MASK_ISEL)
RS6000_CPU ("860", PROCESSOR_MPCCORE, OPTION_MASK_SOFT_FLOAT)
RS6000_CPU ("970", PROCESSOR_POWER4, POWERPC_7400_MASK | OPTION_MASK_PPC_GPOPT
	    | OPTION_MASK_MFCRF | MASK_POWERPC64)
RS6000_CPU ("cell", PROCESSOR_CELL, POWERPC_7400_MASK  | OPTION_MASK_PPC_GPOPT
	    | OPTION_MASK_MFCRF | MASK_POWERPC64)
RS6000_CPU ("ec603e", PROCESSOR_PPC603, OPTION_MASK_SOFT_FLOAT)
RS6000_CPU ("G3", PROCESSOR_PPC750, OPTION_MASK_PPC_GFXOPT)
RS6000_CPU ("G4",  PROCESSOR_PPC7450, POWERPC_7400_MASK)
RS6000_CPU ("G5", PROCESSOR_POWER4, POWERPC_7400_MASK | OPTION_MASK_PPC_GPOPT
	    | OPTION_MASK_MFCRF | MASK_POWERPC64)
RS6000_CPU ("titan", PROCESSOR_TITAN, OPTION_MASK_MULHW | OPTION_MASK_DLMZB)
RS6000_CPU ("power3", PROCESSOR_PPC630, OPTION_MASK_PPC_GFXOPT | MASK_POWERPC64)
RS6000_CPU ("power4", PROCESSOR_POWER4, MASK_POWERPC64 | OPTION_MASK_PPC_GPOPT
	    | OPTION_MASK_PPC_GFXOPT | OPTION_MASK_MFCRF)
RS6000_CPU ("power5", PROCESSOR_POWER5, MASK_POWERPC64 | OPTION_MASK_PPC_GPOPT
	    | OPTION_MASK_PPC_GFXOPT | OPTION_MASK_MFCRF | OPTION_MASK_POPCNTB)
RS6000_CPU ("power5+", PROCESSOR_POWER5, MASK_POWERPC64 | OPTION_MASK_PPC_GPOPT
	    | OPTION_MASK_PPC_GFXOPT | OPTION_MASK_MFCRF | OPTION_MASK_POPCNTB
	    | OPTION_MASK_FPRND)
RS6000_CPU ("power6", PROCESSOR_POWER6, MASK_POWERPC64 | OPTION_MASK_PPC_GPOPT
	    | OPTION_MASK_PPC_GFXOPT | OPTION_MASK_MFCRF | OPTION_MASK_POPCNTB
	    | OPTION_MASK_FPRND | OPTION_MASK_CMPB | OPTION_MASK_DFP
	    | OPTION_MASK_RECIP_PRECISION)
RS6000_CPU ("power6x", PROCESSOR_POWER6, MASK_POWERPC64 | OPTION_MASK_PPC_GPOPT
	    | OPTION_MASK_PPC_GFXOPT | OPTION_MASK_MFCRF | OPTION_MASK_POPCNTB
	    | OPTION_MASK_FPRND | OPTION_MASK_CMPB | OPTION_MASK_DFP
	    | OPTION_MASK_RECIP_PRECISION)
RS6000_CPU ("power7", PROCESSOR_POWER7, MASK_POWERPC64 | ISA_2_6_MASKS_SERVER)
RS6000_CPU ("power8", PROCESSOR_POWER8, MASK_POWERPC64 | ISA_2_7_MASKS_SERVER
	    | OPTION_MASK_HTM)
RS6000_CPU ("power9", PROCESSOR_POWER9, MASK_POWERPC64 | ISA_3_0_MASKS_SERVER
	    | OPTION_MASK_HTM)
RS6000_CPU ("power10", PROCESSOR_POWER10, MASK_POWERPC64 | ISA_3_1_MASKS_SERVER)
RS6000_CPU ("powerpc", PROCESSOR_POWERPC, 0)
RS6000_CPU ("powerpc64", PROCESSOR_POWERPC64, OPTION_MASK_PPC_GFXOPT
	    | MASK_POWERPC64)
RS6000_CPU ("powerpc64le", PROCESSOR_POWER8, MASK_POWERPC64
	    | ISA_2_7_MASKS_SERVER | OPTION_MASK_HTM)
RS6000_CPU ("rs64", PROCESSOR_RS64A, OPTION_MASK_PPC_GFXOPT | MASK_POWERPC64)
RS6000_CPU ("power11", PROCESSOR_POWER11, MASK_POWERPC64 | ISA_POWER11_MASKS_SERVER)
Commit	Line	Data
f10d3ac9	1	/* IBM RS/6000 CPU names..
a945c346	2	Copyright (C) 1991-2024 Free Software Foundation, Inc.
f10d3ac9 JM	3	Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
	4
	5	This file is part of GCC.
	6
	7	GCC is free software; you can redistribute it and/or modify it
	8	under the terms of the GNU General Public License as published
	9	by the Free Software Foundation; either version 3, or (at your
	10	option) any later version.
	11
	12	GCC is distributed in the hope that it will be useful, but WITHOUT
	13	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
	14	or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
	15	License for more details.
	16
	17	You should have received a copy of the GNU General Public License
	18	along with GCC; see the file COPYING3. If not see
	19	<http://www.gnu.org/licenses/>. */
	20
4d967549 MM	21	/* ISA masks. */
	22	#ifndef ISA_2_1_MASKS
	23	#define ISA_2_1_MASKS OPTION_MASK_MFCRF
	24	#define ISA_2_2_MASKS (ISA_2_1_MASKS \| OPTION_MASK_POPCNTB)
	25	#define ISA_2_4_MASKS (ISA_2_2_MASKS \| OPTION_MASK_FPRND)
	26
fbd4b7f3 SB	27	/* For ISA 2.05, don't add ALTIVEC, since in general it isn't a win on
	28	power6. In ISA 2.04, fsel, fre, fsqrt, etc. were no longer documented
	29	as optional. Group masks by server and embedded. */
f62511da	30	#define ISA_2_5_MASKS_EMBEDDED (ISA_2_4_MASKS \
4d967549 MM	31	\| OPTION_MASK_CMPB \
	32	\| OPTION_MASK_RECIP_PRECISION \
	33	\| OPTION_MASK_PPC_GFXOPT \
	34	\| OPTION_MASK_PPC_GPOPT)
	35
	36	#define ISA_2_5_MASKS_SERVER (ISA_2_5_MASKS_EMBEDDED \| OPTION_MASK_DFP)
	37
	38	/* For ISA 2.06, don't add ISEL, since in general it isn't a win, but
	39	altivec is a win so enable it. */
	40	#define ISA_2_6_MASKS_EMBEDDED (ISA_2_5_MASKS_EMBEDDED \| OPTION_MASK_POPCNTD)
	41	#define ISA_2_6_MASKS_SERVER (ISA_2_5_MASKS_SERVER \
	42	\| OPTION_MASK_POPCNTD \
	43	\| OPTION_MASK_ALTIVEC \
19930989	44	\| OPTION_MASK_VSX)
4d967549	45
2fbd3c37	46	/* For now, don't provide an embedded version of ISA 2.07. Do not set power8
e53b6e56	47	fusion here, instead set it in rs6000.cc if we are tuning for a power8
2fbd3c37	48	system. */
f62511da	49	#define ISA_2_7_MASKS_SERVER (ISA_2_6_MASKS_SERVER \
f62511da MM	50	\| OPTION_MASK_P8_VECTOR \
	51	\| OPTION_MASK_CRYPTO \
	52	\| OPTION_MASK_DIRECT_MOVE \
74457d00	53	\| OPTION_MASK_EFFICIENT_UNALIGNED_VSX \
b846c948	54	\| OPTION_MASK_QUAD_MEMORY \
9bfda664	55	\| OPTION_MASK_QUAD_MEMORY_ATOMIC)
f62511da	56
30f78ec7 BS	57	/* ISA masks setting fusion options. */
	58	#define OTHER_FUSION_MASKS (OPTION_MASK_P8_FUSION \
	59	\| OPTION_MASK_P8_FUSION_SIGN)
	60
d1f0d376	61	/* Add ISEL back into ISA 3.0, since it is supposed to be a win. Do not add
cef4b650	62	FLOAT128_HW here until we are ready to make -mfloat128 on by default. */
30f78ec7 BS	63	#define ISA_3_0_MASKS_SERVER ((ISA_2_7_MASKS_SERVER \
	64	\| OPTION_MASK_ISEL \
	65	\| OPTION_MASK_MODULO \
	66	\| OPTION_MASK_P9_MINMAX \
	67	\| OPTION_MASK_P9_MISC \
	68	\| OPTION_MASK_P9_VECTOR) \
	69	& ~OTHER_FUSION_MASKS)
d1f0d376	70
cef4b650 MM	71	/* Support for the IEEE 128-bit floating point hardware requires a lot of the
	72	VSX instructions that are part of ISA 3.0. */
	73	#define ISA_3_0_MASKS_IEEE (OPTION_MASK_VSX \
	74	\| OPTION_MASK_P8_VECTOR \
30f78ec7	75	\| OPTION_MASK_P9_VECTOR)
cef4b650	76
5d9d0c94	77	/* Flags that need to be turned off if -mno-power10. */
b7574ca6 AS	78	/* We comment out PCREL_OPT here to disable it by default because SPEC2017
b7574ca6 AS	79	performance was degraded by it. */
5d9d0c94	80	#define OTHER_POWER10_MASKS (OPTION_MASK_MMA \
f002c046	81	\| OPTION_MASK_PCREL \
b7574ca6	82	/* \| OPTION_MASK_PCREL_OPT */ \
7a775242	83	\| OPTION_MASK_PREFIXED)
510d3a73	84
5d9d0c94 SB	85	#define ISA_3_1_MASKS_SERVER (ISA_3_0_MASKS_SERVER \
5d9d0c94 SB	86	\| OPTION_MASK_POWER10 \
6224db0e	87	\| OTHER_POWER10_MASKS)
da4aae6e	88
dc0f9a74 MM	89	#define ISA_POWER11_MASKS_SERVER (ISA_3_1_MASKS_SERVER \
	90	\| OPTION_MASK_POWER11)
	91
31a07c81	92	/* Flags that need to be turned off if -mno-vsx. */
438ef143	93	#define OTHER_VSX_VECTOR_MASKS (OPTION_MASK_EFFICIENT_UNALIGNED_VSX \
31a07c81	94	\| OPTION_MASK_FLOAT128_KEYWORD \
438ef143 KL	95	\| OPTION_MASK_P8_VECTOR \
	96	\| OPTION_MASK_DIRECT_MOVE \
	97	\| OPTION_MASK_CRYPTO \
	98	\| OPTION_MASK_P9_VECTOR \
	99	\| OPTION_MASK_FLOAT128_HW \
	100	\| OPTION_MASK_P9_MINMAX)
31a07c81	101
0b0908c1 BS	102	/* Flags that need to be turned off if -mno-altivec. */
	103	#define OTHER_ALTIVEC_MASKS (OTHER_VSX_VECTOR_MASKS \
	104	\| OPTION_MASK_VSX)
	105
4d967549 MM	106	#define POWERPC_7400_MASK (OPTION_MASK_PPC_GFXOPT \| OPTION_MASK_ALTIVEC)
4d967549 MM	107
ad1a0853 MM	108	/* Deal with ports that do not have -mstrict-align. */
	109	#ifdef OPTION_MASK_STRICT_ALIGN
	110	#define OPTION_MASK_STRICT_ALIGN_OPTIONAL OPTION_MASK_STRICT_ALIGN
	111	#else
	112	#define OPTION_MASK_STRICT_ALIGN 0
	113	#define OPTION_MASK_STRICT_ALIGN_OPTIONAL 0
	114	#ifndef MASK_STRICT_ALIGN
	115	#define MASK_STRICT_ALIGN 0
	116	#endif
	117	#endif
	118
4d967549 MM	119	/* Mask of all options to set the default isa flags based on -mcpu=<xxx>. */
	120	#define POWERPC_MASKS (OPTION_MASK_ALTIVEC \
	121	\| OPTION_MASK_CMPB \
f62511da	122	\| OPTION_MASK_CRYPTO \
4d967549	123	\| OPTION_MASK_DFP \
f62511da	124	\| OPTION_MASK_DIRECT_MOVE \
4d967549	125	\| OPTION_MASK_DLMZB \
74457d00	126	\| OPTION_MASK_EFFICIENT_UNALIGNED_VSX \
08213983 MM	127	\| OPTION_MASK_FLOAT128_HW \
08213983 MM	128	\| OPTION_MASK_FLOAT128_KEYWORD \
4d967549	129	\| OPTION_MASK_FPRND \
5d9d0c94	130	\| OPTION_MASK_POWER10 \
dc0f9a74	131	\| OPTION_MASK_POWER11 \
7a279bed	132	\| OPTION_MASK_P10_FUSION \
0258b6e4	133	\| OPTION_MASK_HTM \
4d967549 MM	134	\| OPTION_MASK_ISEL \
4d967549 MM	135	\| OPTION_MASK_MFCRF \
f002c046	136	\| OPTION_MASK_MMA \
d1f0d376	137	\| OPTION_MASK_MODULO \
4d967549 MM	138	\| OPTION_MASK_MULHW \
4d967549 MM	139	\| OPTION_MASK_NO_UPDATE \
f62511da MM	140	\| OPTION_MASK_P8_FUSION \
f62511da MM	141	\| OPTION_MASK_P8_VECTOR \
d1f0d376	142	\| OPTION_MASK_P9_MINMAX \
5a3a6a5e	143	\| OPTION_MASK_P9_MISC \
d1f0d376	144	\| OPTION_MASK_P9_VECTOR \
91117603	145	\| OPTION_MASK_PCREL \
b8d85f56	146	\| OPTION_MASK_PCREL_OPT \
4d967549 MM	147	\| OPTION_MASK_POPCNTB \
	148	\| OPTION_MASK_POPCNTD \
	149	\| OPTION_MASK_POWERPC64 \
	150	\| OPTION_MASK_PPC_GFXOPT \
	151	\| OPTION_MASK_PPC_GPOPT \
7a775242	152	\| OPTION_MASK_PREFIXED \
f62511da	153	\| OPTION_MASK_QUAD_MEMORY \
cbe69886	154	\| OPTION_MASK_QUAD_MEMORY_ATOMIC \
4d967549 MM	155	\| OPTION_MASK_RECIP_PRECISION \
4d967549 MM	156	\| OPTION_MASK_SOFT_FLOAT \
ad1a0853	157	\| OPTION_MASK_STRICT_ALIGN_OPTIONAL \
4a89b7e7	158	\| OPTION_MASK_VSX)
4d967549 MM	159
	160	#endif
	161
f10d3ac9 JM	162	/* This table occasionally claims that a processor does not support a
	163	particular feature even though it does, but the feature is slower than the
	164	alternative. Thus, it shouldn't be relied on as a complete description of
	165	the processor's support.
	166
	167	Please keep this list in order, and don't forget to update the documentation
	168	in invoke.texi when adding a new processor or flag.
	169
	170	Before including this file, define a macro:
	171
	172	RS6000_CPU (NAME, CPU, FLAGS)
	173
	174	where the arguments are the fields of struct rs6000_ptt. */
	175
eb2887a1 WS	176	RS6000_CPU ("401", PROCESSOR_PPC403, OPTION_MASK_SOFT_FLOAT)
	177	RS6000_CPU ("403", PROCESSOR_PPC403, OPTION_MASK_SOFT_FLOAT \| MASK_STRICT_ALIGN)
	178	RS6000_CPU ("405", PROCESSOR_PPC405, OPTION_MASK_SOFT_FLOAT
	179	\| OPTION_MASK_MULHW \| OPTION_MASK_DLMZB)
9ccc75eb	180	RS6000_CPU ("405fp", PROCESSOR_PPC405, OPTION_MASK_MULHW \| OPTION_MASK_DLMZB)
eb2887a1 WS	181	RS6000_CPU ("440", PROCESSOR_PPC440, OPTION_MASK_SOFT_FLOAT
eb2887a1 WS	182	\| OPTION_MASK_MULHW \| OPTION_MASK_DLMZB)
9ccc75eb	183	RS6000_CPU ("440fp", PROCESSOR_PPC440, OPTION_MASK_MULHW \| OPTION_MASK_DLMZB)
eb2887a1 WS	184	RS6000_CPU ("464", PROCESSOR_PPC440, OPTION_MASK_SOFT_FLOAT
eb2887a1 WS	185	\| OPTION_MASK_MULHW \| OPTION_MASK_DLMZB)
9ccc75eb	186	RS6000_CPU ("464fp", PROCESSOR_PPC440, OPTION_MASK_MULHW \| OPTION_MASK_DLMZB)
eb2887a1 WS	187	RS6000_CPU ("476", PROCESSOR_PPC476, OPTION_MASK_SOFT_FLOAT
eb2887a1 WS	188	\| OPTION_MASK_PPC_GFXOPT \| OPTION_MASK_MFCRF \| OPTION_MASK_POPCNTB
9ccc75eb WS	189	\| OPTION_MASK_FPRND \| OPTION_MASK_CMPB \| OPTION_MASK_MULHW
9ccc75eb WS	190	\| OPTION_MASK_DLMZB)
eb2887a1 WS	191	RS6000_CPU ("476fp", PROCESSOR_PPC476, OPTION_MASK_PPC_GFXOPT
eb2887a1 WS	192	\| OPTION_MASK_MFCRF \| OPTION_MASK_POPCNTB \| OPTION_MASK_FPRND
9ccc75eb	193	\| OPTION_MASK_CMPB \| OPTION_MASK_MULHW \| OPTION_MASK_DLMZB)
6b39bc38	194	RS6000_CPU ("505", PROCESSOR_MPCCORE, 0)
9ccc75eb	195	RS6000_CPU ("601", PROCESSOR_PPC601, OPTION_MASK_MULTIPLE)
eb2887a1 WS	196	RS6000_CPU ("602", PROCESSOR_PPC603, OPTION_MASK_PPC_GFXOPT)
	197	RS6000_CPU ("603", PROCESSOR_PPC603, OPTION_MASK_PPC_GFXOPT)
	198	RS6000_CPU ("603e", PROCESSOR_PPC603, OPTION_MASK_PPC_GFXOPT)
	199	RS6000_CPU ("604", PROCESSOR_PPC604, OPTION_MASK_PPC_GFXOPT)
	200	RS6000_CPU ("604e", PROCESSOR_PPC604e, OPTION_MASK_PPC_GFXOPT)
	201	RS6000_CPU ("620", PROCESSOR_PPC620, OPTION_MASK_PPC_GFXOPT \| MASK_POWERPC64)
	202	RS6000_CPU ("630", PROCESSOR_PPC630, OPTION_MASK_PPC_GFXOPT \| MASK_POWERPC64)
	203	RS6000_CPU ("740", PROCESSOR_PPC750, OPTION_MASK_PPC_GFXOPT)
f10d3ac9 JM	204	RS6000_CPU ("7400", PROCESSOR_PPC7400, POWERPC_7400_MASK)
f10d3ac9 JM	205	RS6000_CPU ("7450", PROCESSOR_PPC7450, POWERPC_7400_MASK)
eb2887a1 WS	206	RS6000_CPU ("750", PROCESSOR_PPC750, OPTION_MASK_PPC_GFXOPT)
	207	RS6000_CPU ("801", PROCESSOR_MPCCORE, OPTION_MASK_SOFT_FLOAT)
	208	RS6000_CPU ("821", PROCESSOR_MPCCORE, OPTION_MASK_SOFT_FLOAT)
	209	RS6000_CPU ("823", PROCESSOR_MPCCORE, OPTION_MASK_SOFT_FLOAT)
9ccc75eb WS	210	RS6000_CPU ("8540", PROCESSOR_PPC8540, MASK_STRICT_ALIGN \| OPTION_MASK_ISEL)
9ccc75eb WS	211	RS6000_CPU ("8548", PROCESSOR_PPC8548, MASK_STRICT_ALIGN \| OPTION_MASK_ISEL)
eb2887a1 WS	212	RS6000_CPU ("a2", PROCESSOR_PPCA2, OPTION_MASK_PPC_GFXOPT \| MASK_POWERPC64
eb2887a1 WS	213	\| OPTION_MASK_POPCNTB \| OPTION_MASK_CMPB
9ccc75eb	214	\| OPTION_MASK_NO_UPDATE)
eb2887a1	215	RS6000_CPU ("e300c2", PROCESSOR_PPCE300C2, OPTION_MASK_SOFT_FLOAT)
6b39bc38	216	RS6000_CPU ("e300c3", PROCESSOR_PPCE300C3, 0)
eb2887a1 WS	217	RS6000_CPU ("e500mc", PROCESSOR_PPCE500MC, OPTION_MASK_PPC_GFXOPT
eb2887a1 WS	218	\| OPTION_MASK_ISEL)
f10d3ac9	219	RS6000_CPU ("e500mc64", PROCESSOR_PPCE500MC64,
eb2887a1	220	MASK_POWERPC64 \| OPTION_MASK_PPC_GFXOPT \| OPTION_MASK_ISEL)
6b39bc38	221	RS6000_CPU ("e5500", PROCESSOR_PPCE5500,
eb2887a1	222	MASK_POWERPC64 \| OPTION_MASK_PPC_GFXOPT \| OPTION_MASK_ISEL)
683ed19e	223	RS6000_CPU ("e6500", PROCESSOR_PPCE6500, POWERPC_7400_MASK \| MASK_POWERPC64
9ccc75eb	224	\| OPTION_MASK_MFCRF \| OPTION_MASK_ISEL)
eb2887a1 WS	225	RS6000_CPU ("860", PROCESSOR_MPCCORE, OPTION_MASK_SOFT_FLOAT)
eb2887a1 WS	226	RS6000_CPU ("970", PROCESSOR_POWER4, POWERPC_7400_MASK \| OPTION_MASK_PPC_GPOPT
9ccc75eb	227	\| OPTION_MASK_MFCRF \| MASK_POWERPC64)
eb2887a1	228	RS6000_CPU ("cell", PROCESSOR_CELL, POWERPC_7400_MASK \| OPTION_MASK_PPC_GPOPT
9ccc75eb	229	\| OPTION_MASK_MFCRF \| MASK_POWERPC64)
eb2887a1 WS	230	RS6000_CPU ("ec603e", PROCESSOR_PPC603, OPTION_MASK_SOFT_FLOAT)
eb2887a1 WS	231	RS6000_CPU ("G3", PROCESSOR_PPC750, OPTION_MASK_PPC_GFXOPT)
f10d3ac9	232	RS6000_CPU ("G4", PROCESSOR_PPC7450, POWERPC_7400_MASK)
eb2887a1	233	RS6000_CPU ("G5", PROCESSOR_POWER4, POWERPC_7400_MASK \| OPTION_MASK_PPC_GPOPT
9ccc75eb WS	234	\| OPTION_MASK_MFCRF \| MASK_POWERPC64)
9ccc75eb WS	235	RS6000_CPU ("titan", PROCESSOR_TITAN, OPTION_MASK_MULHW \| OPTION_MASK_DLMZB)
eb2887a1 WS	236	RS6000_CPU ("power3", PROCESSOR_PPC630, OPTION_MASK_PPC_GFXOPT \| MASK_POWERPC64)
	237	RS6000_CPU ("power4", PROCESSOR_POWER4, MASK_POWERPC64 \| OPTION_MASK_PPC_GPOPT
	238	\| OPTION_MASK_PPC_GFXOPT \| OPTION_MASK_MFCRF)
	239	RS6000_CPU ("power5", PROCESSOR_POWER5, MASK_POWERPC64 \| OPTION_MASK_PPC_GPOPT
	240	\| OPTION_MASK_PPC_GFXOPT \| OPTION_MASK_MFCRF \| OPTION_MASK_POPCNTB)
	241	RS6000_CPU ("power5+", PROCESSOR_POWER5, MASK_POWERPC64 \| OPTION_MASK_PPC_GPOPT
	242	\| OPTION_MASK_PPC_GFXOPT \| OPTION_MASK_MFCRF \| OPTION_MASK_POPCNTB
9ccc75eb	243	\| OPTION_MASK_FPRND)
eb2887a1 WS	244	RS6000_CPU ("power6", PROCESSOR_POWER6, MASK_POWERPC64 \| OPTION_MASK_PPC_GPOPT
eb2887a1 WS	245	\| OPTION_MASK_PPC_GFXOPT \| OPTION_MASK_MFCRF \| OPTION_MASK_POPCNTB
9ccc75eb	246	\| OPTION_MASK_FPRND \| OPTION_MASK_CMPB \| OPTION_MASK_DFP
eb2887a1 WS	247	\| OPTION_MASK_RECIP_PRECISION)
	248	RS6000_CPU ("power6x", PROCESSOR_POWER6, MASK_POWERPC64 \| OPTION_MASK_PPC_GPOPT
	249	\| OPTION_MASK_PPC_GFXOPT \| OPTION_MASK_MFCRF \| OPTION_MASK_POPCNTB
9ccc75eb	250	\| OPTION_MASK_FPRND \| OPTION_MASK_CMPB \| OPTION_MASK_DFP
eb2887a1	251	\| OPTION_MASK_RECIP_PRECISION)
19930989	252	RS6000_CPU ("power7", PROCESSOR_POWER7, MASK_POWERPC64 \| ISA_2_6_MASKS_SERVER)
82800987 KL	253	RS6000_CPU ("power8", PROCESSOR_POWER8, MASK_POWERPC64 \| ISA_2_7_MASKS_SERVER
	254	\| OPTION_MASK_HTM)
	255	RS6000_CPU ("power9", PROCESSOR_POWER9, MASK_POWERPC64 \| ISA_3_0_MASKS_SERVER
	256	\| OPTION_MASK_HTM)
5d9d0c94	257	RS6000_CPU ("power10", PROCESSOR_POWER10, MASK_POWERPC64 \| ISA_3_1_MASKS_SERVER)
6b39bc38	258	RS6000_CPU ("powerpc", PROCESSOR_POWERPC, 0)
eb2887a1 WS	259	RS6000_CPU ("powerpc64", PROCESSOR_POWERPC64, OPTION_MASK_PPC_GFXOPT
	260	\| MASK_POWERPC64)
	261	RS6000_CPU ("powerpc64le", PROCESSOR_POWER8, MASK_POWERPC64
	262	\| ISA_2_7_MASKS_SERVER \| OPTION_MASK_HTM)
	263	RS6000_CPU ("rs64", PROCESSOR_RS64A, OPTION_MASK_PPC_GFXOPT \| MASK_POWERPC64)
dc0f9a74	264	RS6000_CPU ("power11", PROCESSOR_POWER11, MASK_POWERPC64 \| ISA_POWER11_MASKS_SERVER)