[gcc.git] / gcc / config / rs6000 / rs6000-cpus.def

/* IBM RS/6000 CPU names..
   Copyright (C) 1991-2021 Free Software Foundation, Inc.
   Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)

   This file is part of GCC.

   GCC is free software; you can redistribute it and/or modify it
   under the terms of the GNU General Public License as published
   by the Free Software Foundation; either version 3, or (at your
   option) any later version.

   GCC is distributed in the hope that it will be useful, but WITHOUT
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
   License for more details.

   You should have received a copy of the GNU General Public License
   along with GCC; see the file COPYING3.  If not see
   <http://www.gnu.org/licenses/>.  */

/* ISA masks.  */
#ifndef ISA_2_1_MASKS
#define ISA_2_1_MASKS		OPTION_MASK_MFCRF
#define ISA_2_2_MASKS		(ISA_2_1_MASKS | OPTION_MASK_POPCNTB)
#define ISA_2_4_MASKS		(ISA_2_2_MASKS | OPTION_MASK_FPRND)

  /* For ISA 2.05, don't add ALTIVEC, since in general it isn't a win on
     power6.  In ISA 2.04, fsel, fre, fsqrt, etc. were no longer documented
     as optional.  Group masks by server and embedded. */
#define ISA_2_5_MASKS_EMBEDDED	(ISA_2_4_MASKS				\
				 | OPTION_MASK_CMPB			\
				 | OPTION_MASK_RECIP_PRECISION		\
				 | OPTION_MASK_PPC_GFXOPT		\
				 | OPTION_MASK_PPC_GPOPT)

#define ISA_2_5_MASKS_SERVER	(ISA_2_5_MASKS_EMBEDDED | OPTION_MASK_DFP)

  /* For ISA 2.06, don't add ISEL, since in general it isn't a win, but
     altivec is a win so enable it.  */
#define ISA_2_6_MASKS_EMBEDDED	(ISA_2_5_MASKS_EMBEDDED | OPTION_MASK_POPCNTD)
#define ISA_2_6_MASKS_SERVER	(ISA_2_5_MASKS_SERVER			\
				 | OPTION_MASK_POPCNTD			\
				 | OPTION_MASK_ALTIVEC			\
				 | OPTION_MASK_VSX)

/* For now, don't provide an embedded version of ISA 2.07.  Do not set power8
   fusion here, instead set it in rs6000.c if we are tuning for a power8
   system.  */
#define ISA_2_7_MASKS_SERVER	(ISA_2_6_MASKS_SERVER			\
				 | OPTION_MASK_P8_VECTOR		\
				 | OPTION_MASK_CRYPTO			\
				 | OPTION_MASK_DIRECT_MOVE		\
				 | OPTION_MASK_EFFICIENT_UNALIGNED_VSX	\
				 | OPTION_MASK_QUAD_MEMORY		\
				 | OPTION_MASK_QUAD_MEMORY_ATOMIC)

/* ISA masks setting fusion options.  */
#define OTHER_FUSION_MASKS	(OPTION_MASK_P8_FUSION			\
				 | OPTION_MASK_P8_FUSION_SIGN)

/* Add ISEL back into ISA 3.0, since it is supposed to be a win.  Do not add
   FLOAT128_HW here until we are ready to make -mfloat128 on by default.  */
#define ISA_3_0_MASKS_SERVER	((ISA_2_7_MASKS_SERVER			\
				  | OPTION_MASK_ISEL			\
				  | OPTION_MASK_MODULO			\
				  | OPTION_MASK_P9_MINMAX		\
				  | OPTION_MASK_P9_MISC			\
				  | OPTION_MASK_P9_VECTOR)		\
				 & ~OTHER_FUSION_MASKS)

/* Support for the IEEE 128-bit floating point hardware requires a lot of the
   VSX instructions that are part of ISA 3.0.  */
#define ISA_3_0_MASKS_IEEE	(OPTION_MASK_VSX			\
				 | OPTION_MASK_P8_VECTOR		\
				 | OPTION_MASK_P9_VECTOR)

/* Flags that need to be turned off if -mno-power10.  */
#define OTHER_POWER10_MASKS	(OPTION_MASK_MMA			\
				 | OPTION_MASK_PCREL			\
				 | OPTION_MASK_PCREL_OPT		\
				 | OPTION_MASK_PREFIXED)

#define ISA_3_1_MASKS_SERVER	(ISA_3_0_MASKS_SERVER			\
				 | OPTION_MASK_POWER10			\
				 | OTHER_POWER10_MASKS			\
				 | OPTION_MASK_LXVKQ			\
				 | OPTION_MASK_P10_FUSION		\
				 | OPTION_MASK_P10_FUSION_LD_CMPI	\
				 | OPTION_MASK_P10_FUSION_2LOGICAL	\
				 | OPTION_MASK_P10_FUSION_LOGADD 	\
				 | OPTION_MASK_P10_FUSION_ADDLOG	\
				 | OPTION_MASK_P10_FUSION_2ADD		\
				 | OPTION_MASK_XXSPLTI32DX		\
				 | OPTION_MASK_XXSPLTIDP		\
				 | OPTION_MASK_XXSPLTIW)

/* Flags that need to be turned off if -mno-power9-vector.  */
#define OTHER_P9_VECTOR_MASKS	(OPTION_MASK_FLOAT128_HW		\
				 | OPTION_MASK_P9_MINMAX)

/* Flags that need to be turned off if -mno-power8-vector.  */
#define OTHER_P8_VECTOR_MASKS	(OTHER_P9_VECTOR_MASKS			\
				 | OPTION_MASK_P9_VECTOR		\
				 | OPTION_MASK_DIRECT_MOVE		\
				 | OPTION_MASK_CRYPTO)

/* Flags that need to be turned off if -mno-vsx.  */
#define OTHER_VSX_VECTOR_MASKS	(OTHER_P8_VECTOR_MASKS			\
				 | OPTION_MASK_EFFICIENT_UNALIGNED_VSX	\
				 | OPTION_MASK_FLOAT128_KEYWORD		\
				 | OPTION_MASK_P8_VECTOR)

/* Flags that need to be turned off if -mno-altivec.  */
#define OTHER_ALTIVEC_MASKS	(OTHER_VSX_VECTOR_MASKS			\
				 | OPTION_MASK_VSX)

#define POWERPC_7400_MASK	(OPTION_MASK_PPC_GFXOPT | OPTION_MASK_ALTIVEC)

/* Deal with ports that do not have -mstrict-align.  */
#ifdef OPTION_MASK_STRICT_ALIGN
#define OPTION_MASK_STRICT_ALIGN_OPTIONAL OPTION_MASK_STRICT_ALIGN
#else
#define OPTION_MASK_STRICT_ALIGN 0
#define OPTION_MASK_STRICT_ALIGN_OPTIONAL 0
#ifndef MASK_STRICT_ALIGN
#define MASK_STRICT_ALIGN 0
#endif
#endif

/* Mask of all options to set the default isa flags based on -mcpu=<xxx>.  */
#define POWERPC_MASKS		(OPTION_MASK_ALTIVEC			\
				 | OPTION_MASK_CMPB			\
				 | OPTION_MASK_CRYPTO			\
				 | OPTION_MASK_DFP			\
				 | OPTION_MASK_DIRECT_MOVE		\
				 | OPTION_MASK_DLMZB			\
				 | OPTION_MASK_EFFICIENT_UNALIGNED_VSX	\
				 | OPTION_MASK_FLOAT128_HW		\
				 | OPTION_MASK_FLOAT128_KEYWORD		\
				 | OPTION_MASK_FPRND			\
				 | OPTION_MASK_POWER10			\
				 | OPTION_MASK_P10_FUSION		\
				 | OPTION_MASK_P10_FUSION_LD_CMPI	\
				 | OPTION_MASK_P10_FUSION_2LOGICAL	\
				 | OPTION_MASK_P10_FUSION_LOGADD 	\
				 | OPTION_MASK_P10_FUSION_ADDLOG	\
				 | OPTION_MASK_P10_FUSION_2ADD    	\
				 | OPTION_MASK_HTM			\
				 | OPTION_MASK_ISEL			\
				 | OPTION_MASK_LXVKQ			\
				 | OPTION_MASK_MFCRF			\
				 | OPTION_MASK_MMA			\
				 | OPTION_MASK_MODULO			\
				 | OPTION_MASK_MULHW			\
				 | OPTION_MASK_NO_UPDATE		\
				 | OPTION_MASK_P8_FUSION		\
				 | OPTION_MASK_P8_VECTOR		\
				 | OPTION_MASK_P9_MINMAX		\
				 | OPTION_MASK_P9_MISC			\
				 | OPTION_MASK_P9_VECTOR		\
				 | OPTION_MASK_PCREL			\
				 | OPTION_MASK_PCREL_OPT		\
				 | OPTION_MASK_POPCNTB			\
				 | OPTION_MASK_POPCNTD			\
				 | OPTION_MASK_POWERPC64		\
				 | OPTION_MASK_PPC_GFXOPT		\
				 | OPTION_MASK_PPC_GPOPT		\
				 | OPTION_MASK_PREFIXED			\
				 | OPTION_MASK_QUAD_MEMORY		\
				 | OPTION_MASK_QUAD_MEMORY_ATOMIC	\
				 | OPTION_MASK_RECIP_PRECISION		\
				 | OPTION_MASK_SOFT_FLOAT		\
				 | OPTION_MASK_STRICT_ALIGN_OPTIONAL	\
				 | OPTION_MASK_VSX			\
				 | OPTION_MASK_XXSPLTI32DX		\
				 | OPTION_MASK_XXSPLTIDP		\
				 | OPTION_MASK_XXSPLTIW)
#endif

/* This table occasionally claims that a processor does not support a
   particular feature even though it does, but the feature is slower than the
   alternative.  Thus, it shouldn't be relied on as a complete description of
   the processor's support.

   Please keep this list in order, and don't forget to update the documentation
   in invoke.texi when adding a new processor or flag.

   Before including this file, define a macro:

   RS6000_CPU (NAME, CPU, FLAGS)

   where the arguments are the fields of struct rs6000_ptt.  */

RS6000_CPU ("401", PROCESSOR_PPC403, MASK_SOFT_FLOAT)
RS6000_CPU ("403", PROCESSOR_PPC403, MASK_SOFT_FLOAT | MASK_STRICT_ALIGN)
RS6000_CPU ("405", PROCESSOR_PPC405, MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB)
RS6000_CPU ("405fp", PROCESSOR_PPC405, MASK_MULHW | MASK_DLMZB)
RS6000_CPU ("440", PROCESSOR_PPC440, MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB)
RS6000_CPU ("440fp", PROCESSOR_PPC440, MASK_MULHW | MASK_DLMZB)
RS6000_CPU ("464", PROCESSOR_PPC440, MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB)
RS6000_CPU ("464fp", PROCESSOR_PPC440, MASK_MULHW | MASK_DLMZB)
RS6000_CPU ("476", PROCESSOR_PPC476,
	    MASK_SOFT_FLOAT | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB
	    | MASK_FPRND | MASK_CMPB | MASK_MULHW | MASK_DLMZB)
RS6000_CPU ("476fp", PROCESSOR_PPC476,
	    MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND
	    | MASK_CMPB | MASK_MULHW | MASK_DLMZB)
RS6000_CPU ("505", PROCESSOR_MPCCORE, 0)
RS6000_CPU ("601", PROCESSOR_PPC601, MASK_MULTIPLE)
RS6000_CPU ("602", PROCESSOR_PPC603, MASK_PPC_GFXOPT)
RS6000_CPU ("603", PROCESSOR_PPC603, MASK_PPC_GFXOPT)
RS6000_CPU ("603e", PROCESSOR_PPC603, MASK_PPC_GFXOPT)
RS6000_CPU ("604", PROCESSOR_PPC604, MASK_PPC_GFXOPT)
RS6000_CPU ("604e", PROCESSOR_PPC604e, MASK_PPC_GFXOPT)
RS6000_CPU ("620", PROCESSOR_PPC620, MASK_PPC_GFXOPT | MASK_POWERPC64)
RS6000_CPU ("630", PROCESSOR_PPC630, MASK_PPC_GFXOPT | MASK_POWERPC64)
RS6000_CPU ("740", PROCESSOR_PPC750, MASK_PPC_GFXOPT)
RS6000_CPU ("7400", PROCESSOR_PPC7400, POWERPC_7400_MASK)
RS6000_CPU ("7450", PROCESSOR_PPC7450, POWERPC_7400_MASK)
RS6000_CPU ("750", PROCESSOR_PPC750, MASK_PPC_GFXOPT)
RS6000_CPU ("801", PROCESSOR_MPCCORE, MASK_SOFT_FLOAT)
RS6000_CPU ("821", PROCESSOR_MPCCORE, MASK_SOFT_FLOAT)
RS6000_CPU ("823", PROCESSOR_MPCCORE, MASK_SOFT_FLOAT)
RS6000_CPU ("8540", PROCESSOR_PPC8540, MASK_STRICT_ALIGN | MASK_ISEL)
RS6000_CPU ("8548", PROCESSOR_PPC8548, MASK_STRICT_ALIGN | MASK_ISEL)
RS6000_CPU ("a2", PROCESSOR_PPCA2,
	    MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_POPCNTB | MASK_CMPB
	    | MASK_NO_UPDATE)
RS6000_CPU ("e300c2", PROCESSOR_PPCE300C2, MASK_SOFT_FLOAT)
RS6000_CPU ("e300c3", PROCESSOR_PPCE300C3, 0)
RS6000_CPU ("e500mc", PROCESSOR_PPCE500MC, MASK_PPC_GFXOPT | MASK_ISEL)
RS6000_CPU ("e500mc64", PROCESSOR_PPCE500MC64,
	    MASK_POWERPC64 | MASK_PPC_GFXOPT | MASK_ISEL)
RS6000_CPU ("e5500", PROCESSOR_PPCE5500,
	    MASK_POWERPC64 | MASK_PPC_GFXOPT | MASK_ISEL)
RS6000_CPU ("e6500", PROCESSOR_PPCE6500, POWERPC_7400_MASK | MASK_POWERPC64
	    | MASK_MFCRF | MASK_ISEL)
RS6000_CPU ("860", PROCESSOR_MPCCORE, MASK_SOFT_FLOAT)
RS6000_CPU ("970", PROCESSOR_POWER4,
	    POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64)
RS6000_CPU ("cell", PROCESSOR_CELL,
	    POWERPC_7400_MASK  | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64)
RS6000_CPU ("ec603e", PROCESSOR_PPC603, MASK_SOFT_FLOAT)
RS6000_CPU ("G3", PROCESSOR_PPC750, MASK_PPC_GFXOPT)
RS6000_CPU ("G4",  PROCESSOR_PPC7450, POWERPC_7400_MASK)
RS6000_CPU ("G5", PROCESSOR_POWER4,
	    POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64)
RS6000_CPU ("titan", PROCESSOR_TITAN, MASK_MULHW | MASK_DLMZB)
RS6000_CPU ("power3", PROCESSOR_PPC630, MASK_PPC_GFXOPT | MASK_POWERPC64)
RS6000_CPU ("power4", PROCESSOR_POWER4, MASK_POWERPC64 | MASK_PPC_GPOPT
	    | MASK_PPC_GFXOPT | MASK_MFCRF)
RS6000_CPU ("power5", PROCESSOR_POWER5, MASK_POWERPC64 | MASK_PPC_GPOPT
	    | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB)
RS6000_CPU ("power5+", PROCESSOR_POWER5, MASK_POWERPC64 | MASK_PPC_GPOPT
	    | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND)
RS6000_CPU ("power6", PROCESSOR_POWER6, MASK_POWERPC64 | MASK_PPC_GPOPT
	    | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND
	    | MASK_CMPB | MASK_DFP | MASK_RECIP_PRECISION)
RS6000_CPU ("power6x", PROCESSOR_POWER6, MASK_POWERPC64 | MASK_PPC_GPOPT
	    | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND
	    | MASK_CMPB | MASK_DFP | MASK_RECIP_PRECISION)
RS6000_CPU ("power7", PROCESSOR_POWER7, MASK_POWERPC64 | ISA_2_6_MASKS_SERVER)
RS6000_CPU ("power8", PROCESSOR_POWER8, MASK_POWERPC64 | ISA_2_7_MASKS_SERVER
	    | OPTION_MASK_HTM)
RS6000_CPU ("power9", PROCESSOR_POWER9, MASK_POWERPC64 | ISA_3_0_MASKS_SERVER
	    | OPTION_MASK_HTM)
RS6000_CPU ("power10", PROCESSOR_POWER10, MASK_POWERPC64 | ISA_3_1_MASKS_SERVER)
RS6000_CPU ("powerpc", PROCESSOR_POWERPC, 0)
RS6000_CPU ("powerpc64", PROCESSOR_POWERPC64, MASK_PPC_GFXOPT | MASK_POWERPC64)
RS6000_CPU ("powerpc64le", PROCESSOR_POWER8, MASK_POWERPC64 | ISA_2_7_MASKS_SERVER
	    | OPTION_MASK_HTM)
RS6000_CPU ("rs64", PROCESSOR_RS64A, MASK_PPC_GFXOPT | MASK_POWERPC64)
Commit	Line	Data
f10d3ac9	1	/* IBM RS/6000 CPU names..
99dee823	2	Copyright (C) 1991-2021 Free Software Foundation, Inc.
f10d3ac9 JM	3	Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
	4
	5	This file is part of GCC.
	6
	7	GCC is free software; you can redistribute it and/or modify it
	8	under the terms of the GNU General Public License as published
	9	by the Free Software Foundation; either version 3, or (at your
	10	option) any later version.
	11
	12	GCC is distributed in the hope that it will be useful, but WITHOUT
	13	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
	14	or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
	15	License for more details.
	16
	17	You should have received a copy of the GNU General Public License
	18	along with GCC; see the file COPYING3. If not see
	19	<http://www.gnu.org/licenses/>. */
	20
4d967549 MM	21	/* ISA masks. */
	22	#ifndef ISA_2_1_MASKS
	23	#define ISA_2_1_MASKS OPTION_MASK_MFCRF
	24	#define ISA_2_2_MASKS (ISA_2_1_MASKS \| OPTION_MASK_POPCNTB)
	25	#define ISA_2_4_MASKS (ISA_2_2_MASKS \| OPTION_MASK_FPRND)
	26
fbd4b7f3 SB	27	/* For ISA 2.05, don't add ALTIVEC, since in general it isn't a win on
	28	power6. In ISA 2.04, fsel, fre, fsqrt, etc. were no longer documented
	29	as optional. Group masks by server and embedded. */
f62511da	30	#define ISA_2_5_MASKS_EMBEDDED (ISA_2_4_MASKS \
4d967549 MM	31	\| OPTION_MASK_CMPB \
	32	\| OPTION_MASK_RECIP_PRECISION \
	33	\| OPTION_MASK_PPC_GFXOPT \
	34	\| OPTION_MASK_PPC_GPOPT)
	35
	36	#define ISA_2_5_MASKS_SERVER (ISA_2_5_MASKS_EMBEDDED \| OPTION_MASK_DFP)
	37
	38	/* For ISA 2.06, don't add ISEL, since in general it isn't a win, but
	39	altivec is a win so enable it. */
	40	#define ISA_2_6_MASKS_EMBEDDED (ISA_2_5_MASKS_EMBEDDED \| OPTION_MASK_POPCNTD)
	41	#define ISA_2_6_MASKS_SERVER (ISA_2_5_MASKS_SERVER \
	42	\| OPTION_MASK_POPCNTD \
	43	\| OPTION_MASK_ALTIVEC \
19930989	44	\| OPTION_MASK_VSX)
4d967549	45
2fbd3c37 MM	46	/* For now, don't provide an embedded version of ISA 2.07. Do not set power8
	47	fusion here, instead set it in rs6000.c if we are tuning for a power8
	48	system. */
f62511da	49	#define ISA_2_7_MASKS_SERVER (ISA_2_6_MASKS_SERVER \
f62511da MM	50	\| OPTION_MASK_P8_VECTOR \
	51	\| OPTION_MASK_CRYPTO \
	52	\| OPTION_MASK_DIRECT_MOVE \
74457d00	53	\| OPTION_MASK_EFFICIENT_UNALIGNED_VSX \
b846c948	54	\| OPTION_MASK_QUAD_MEMORY \
9bfda664	55	\| OPTION_MASK_QUAD_MEMORY_ATOMIC)
f62511da	56
30f78ec7 BS	57	/* ISA masks setting fusion options. */
	58	#define OTHER_FUSION_MASKS (OPTION_MASK_P8_FUSION \
	59	\| OPTION_MASK_P8_FUSION_SIGN)
	60
d1f0d376	61	/* Add ISEL back into ISA 3.0, since it is supposed to be a win. Do not add
cef4b650	62	FLOAT128_HW here until we are ready to make -mfloat128 on by default. */
30f78ec7 BS	63	#define ISA_3_0_MASKS_SERVER ((ISA_2_7_MASKS_SERVER \
	64	\| OPTION_MASK_ISEL \
	65	\| OPTION_MASK_MODULO \
	66	\| OPTION_MASK_P9_MINMAX \
	67	\| OPTION_MASK_P9_MISC \
	68	\| OPTION_MASK_P9_VECTOR) \
	69	& ~OTHER_FUSION_MASKS)
d1f0d376	70
cef4b650 MM	71	/* Support for the IEEE 128-bit floating point hardware requires a lot of the
	72	VSX instructions that are part of ISA 3.0. */
	73	#define ISA_3_0_MASKS_IEEE (OPTION_MASK_VSX \
	74	\| OPTION_MASK_P8_VECTOR \
30f78ec7	75	\| OPTION_MASK_P9_VECTOR)
cef4b650	76
5d9d0c94 SB	77	/* Flags that need to be turned off if -mno-power10. */
5d9d0c94 SB	78	#define OTHER_POWER10_MASKS (OPTION_MASK_MMA \
f002c046	79	\| OPTION_MASK_PCREL \
b8d85f56	80	\| OPTION_MASK_PCREL_OPT \
7a775242	81	\| OPTION_MASK_PREFIXED)
510d3a73	82
5d9d0c94 SB	83	#define ISA_3_1_MASKS_SERVER (ISA_3_0_MASKS_SERVER \
5d9d0c94 SB	84	\| OPTION_MASK_POWER10 \
7a279bed	85	\| OTHER_POWER10_MASKS \
ddd74c49	86	\| OPTION_MASK_LXVKQ \
7a279bed	87	\| OPTION_MASK_P10_FUSION \
1242eb75	88	\| OPTION_MASK_P10_FUSION_LD_CMPI \
842a0551	89	\| OPTION_MASK_P10_FUSION_2LOGICAL \
a8764071 AS	90	\| OPTION_MASK_P10_FUSION_LOGADD \
a8764071 AS	91	\| OPTION_MASK_P10_FUSION_ADDLOG \
a9b65375	92	\| OPTION_MASK_P10_FUSION_2ADD \
f44c30d4	93	\| OPTION_MASK_XXSPLTI32DX \
e872914c	94	\| OPTION_MASK_XXSPLTIDP \
a9b65375	95	\| OPTION_MASK_XXSPLTIW)
da4aae6e	96
31a07c81 MM	97	/* Flags that need to be turned off if -mno-power9-vector. */
31a07c81 MM	98	#define OTHER_P9_VECTOR_MASKS (OPTION_MASK_FLOAT128_HW \
31a07c81 MM	99	\| OPTION_MASK_P9_MINMAX)
	100
	101	/* Flags that need to be turned off if -mno-power8-vector. */
	102	#define OTHER_P8_VECTOR_MASKS (OTHER_P9_VECTOR_MASKS \
	103	\| OPTION_MASK_P9_VECTOR \
	104	\| OPTION_MASK_DIRECT_MOVE \
19930989	105	\| OPTION_MASK_CRYPTO)
31a07c81 MM	106
	107	/* Flags that need to be turned off if -mno-vsx. */
	108	#define OTHER_VSX_VECTOR_MASKS (OTHER_P8_VECTOR_MASKS \
	109	\| OPTION_MASK_EFFICIENT_UNALIGNED_VSX \
	110	\| OPTION_MASK_FLOAT128_KEYWORD \
4a89b7e7	111	\| OPTION_MASK_P8_VECTOR)
31a07c81	112
0b0908c1 BS	113	/* Flags that need to be turned off if -mno-altivec. */
	114	#define OTHER_ALTIVEC_MASKS (OTHER_VSX_VECTOR_MASKS \
	115	\| OPTION_MASK_VSX)
	116
4d967549 MM	117	#define POWERPC_7400_MASK (OPTION_MASK_PPC_GFXOPT \| OPTION_MASK_ALTIVEC)
4d967549 MM	118
ad1a0853 MM	119	/* Deal with ports that do not have -mstrict-align. */
	120	#ifdef OPTION_MASK_STRICT_ALIGN
	121	#define OPTION_MASK_STRICT_ALIGN_OPTIONAL OPTION_MASK_STRICT_ALIGN
	122	#else
	123	#define OPTION_MASK_STRICT_ALIGN 0
	124	#define OPTION_MASK_STRICT_ALIGN_OPTIONAL 0
	125	#ifndef MASK_STRICT_ALIGN
	126	#define MASK_STRICT_ALIGN 0
	127	#endif
	128	#endif
	129
4d967549 MM	130	/* Mask of all options to set the default isa flags based on -mcpu=<xxx>. */
	131	#define POWERPC_MASKS (OPTION_MASK_ALTIVEC \
	132	\| OPTION_MASK_CMPB \
f62511da	133	\| OPTION_MASK_CRYPTO \
4d967549	134	\| OPTION_MASK_DFP \
f62511da	135	\| OPTION_MASK_DIRECT_MOVE \
4d967549	136	\| OPTION_MASK_DLMZB \
74457d00	137	\| OPTION_MASK_EFFICIENT_UNALIGNED_VSX \
08213983 MM	138	\| OPTION_MASK_FLOAT128_HW \
08213983 MM	139	\| OPTION_MASK_FLOAT128_KEYWORD \
4d967549	140	\| OPTION_MASK_FPRND \
5d9d0c94	141	\| OPTION_MASK_POWER10 \
7a279bed AS	142	\| OPTION_MASK_P10_FUSION \
7a279bed AS	143	\| OPTION_MASK_P10_FUSION_LD_CMPI \
1242eb75	144	\| OPTION_MASK_P10_FUSION_2LOGICAL \
a8764071 AS	145	\| OPTION_MASK_P10_FUSION_LOGADD \
a8764071 AS	146	\| OPTION_MASK_P10_FUSION_ADDLOG \
842a0551	147	\| OPTION_MASK_P10_FUSION_2ADD \
0258b6e4	148	\| OPTION_MASK_HTM \
4d967549	149	\| OPTION_MASK_ISEL \
ddd74c49	150	\| OPTION_MASK_LXVKQ \
4d967549	151	\| OPTION_MASK_MFCRF \
f002c046	152	\| OPTION_MASK_MMA \
d1f0d376	153	\| OPTION_MASK_MODULO \
4d967549 MM	154	\| OPTION_MASK_MULHW \
4d967549 MM	155	\| OPTION_MASK_NO_UPDATE \
f62511da MM	156	\| OPTION_MASK_P8_FUSION \
f62511da MM	157	\| OPTION_MASK_P8_VECTOR \
d1f0d376	158	\| OPTION_MASK_P9_MINMAX \
5a3a6a5e	159	\| OPTION_MASK_P9_MISC \
d1f0d376	160	\| OPTION_MASK_P9_VECTOR \
91117603	161	\| OPTION_MASK_PCREL \
b8d85f56	162	\| OPTION_MASK_PCREL_OPT \
4d967549 MM	163	\| OPTION_MASK_POPCNTB \
	164	\| OPTION_MASK_POPCNTD \
	165	\| OPTION_MASK_POWERPC64 \
	166	\| OPTION_MASK_PPC_GFXOPT \
	167	\| OPTION_MASK_PPC_GPOPT \
7a775242	168	\| OPTION_MASK_PREFIXED \
f62511da	169	\| OPTION_MASK_QUAD_MEMORY \
cbe69886	170	\| OPTION_MASK_QUAD_MEMORY_ATOMIC \
4d967549 MM	171	\| OPTION_MASK_RECIP_PRECISION \
4d967549 MM	172	\| OPTION_MASK_SOFT_FLOAT \
ad1a0853	173	\| OPTION_MASK_STRICT_ALIGN_OPTIONAL \
a9b65375	174	\| OPTION_MASK_VSX \
f44c30d4	175	\| OPTION_MASK_XXSPLTI32DX \
e872914c	176	\| OPTION_MASK_XXSPLTIDP \
a9b65375	177	\| OPTION_MASK_XXSPLTIW)
4d967549 MM	178	#endif
4d967549 MM	179
f10d3ac9 JM	180	/* This table occasionally claims that a processor does not support a
	181	particular feature even though it does, but the feature is slower than the
	182	alternative. Thus, it shouldn't be relied on as a complete description of
	183	the processor's support.
	184
	185	Please keep this list in order, and don't forget to update the documentation
	186	in invoke.texi when adding a new processor or flag.
	187
	188	Before including this file, define a macro:
	189
	190	RS6000_CPU (NAME, CPU, FLAGS)
	191
	192	where the arguments are the fields of struct rs6000_ptt. */
	193
6b39bc38 SB	194	RS6000_CPU ("401", PROCESSOR_PPC403, MASK_SOFT_FLOAT)
	195	RS6000_CPU ("403", PROCESSOR_PPC403, MASK_SOFT_FLOAT \| MASK_STRICT_ALIGN)
	196	RS6000_CPU ("405", PROCESSOR_PPC405, MASK_SOFT_FLOAT \| MASK_MULHW \| MASK_DLMZB)
	197	RS6000_CPU ("405fp", PROCESSOR_PPC405, MASK_MULHW \| MASK_DLMZB)
	198	RS6000_CPU ("440", PROCESSOR_PPC440, MASK_SOFT_FLOAT \| MASK_MULHW \| MASK_DLMZB)
	199	RS6000_CPU ("440fp", PROCESSOR_PPC440, MASK_MULHW \| MASK_DLMZB)
	200	RS6000_CPU ("464", PROCESSOR_PPC440, MASK_SOFT_FLOAT \| MASK_MULHW \| MASK_DLMZB)
	201	RS6000_CPU ("464fp", PROCESSOR_PPC440, MASK_MULHW \| MASK_DLMZB)
f10d3ac9	202	RS6000_CPU ("476", PROCESSOR_PPC476,
6b39bc38	203	MASK_SOFT_FLOAT \| MASK_PPC_GFXOPT \| MASK_MFCRF \| MASK_POPCNTB
f10d3ac9	204	\| MASK_FPRND \| MASK_CMPB \| MASK_MULHW \| MASK_DLMZB)
6b39bc38 SB	205	RS6000_CPU ("476fp", PROCESSOR_PPC476,
	206	MASK_PPC_GFXOPT \| MASK_MFCRF \| MASK_POPCNTB \| MASK_FPRND
	207	\| MASK_CMPB \| MASK_MULHW \| MASK_DLMZB)
	208	RS6000_CPU ("505", PROCESSOR_MPCCORE, 0)
20c89ab7	209	RS6000_CPU ("601", PROCESSOR_PPC601, MASK_MULTIPLE)
6b39bc38 SB	210	RS6000_CPU ("602", PROCESSOR_PPC603, MASK_PPC_GFXOPT)
	211	RS6000_CPU ("603", PROCESSOR_PPC603, MASK_PPC_GFXOPT)
	212	RS6000_CPU ("603e", PROCESSOR_PPC603, MASK_PPC_GFXOPT)
	213	RS6000_CPU ("604", PROCESSOR_PPC604, MASK_PPC_GFXOPT)
	214	RS6000_CPU ("604e", PROCESSOR_PPC604e, MASK_PPC_GFXOPT)
	215	RS6000_CPU ("620", PROCESSOR_PPC620, MASK_PPC_GFXOPT \| MASK_POWERPC64)
	216	RS6000_CPU ("630", PROCESSOR_PPC630, MASK_PPC_GFXOPT \| MASK_POWERPC64)
	217	RS6000_CPU ("740", PROCESSOR_PPC750, MASK_PPC_GFXOPT)
f10d3ac9 JM	218	RS6000_CPU ("7400", PROCESSOR_PPC7400, POWERPC_7400_MASK)
f10d3ac9 JM	219	RS6000_CPU ("7450", PROCESSOR_PPC7450, POWERPC_7400_MASK)
6b39bc38 SB	220	RS6000_CPU ("750", PROCESSOR_PPC750, MASK_PPC_GFXOPT)
	221	RS6000_CPU ("801", PROCESSOR_MPCCORE, MASK_SOFT_FLOAT)
	222	RS6000_CPU ("821", PROCESSOR_MPCCORE, MASK_SOFT_FLOAT)
	223	RS6000_CPU ("823", PROCESSOR_MPCCORE, MASK_SOFT_FLOAT)
	224	RS6000_CPU ("8540", PROCESSOR_PPC8540, MASK_STRICT_ALIGN \| MASK_ISEL)
	225	RS6000_CPU ("8548", PROCESSOR_PPC8548, MASK_STRICT_ALIGN \| MASK_ISEL)
f10d3ac9	226	RS6000_CPU ("a2", PROCESSOR_PPCA2,
6b39bc38 SB	227	MASK_PPC_GFXOPT \| MASK_POWERPC64 \| MASK_POPCNTB \| MASK_CMPB
	228	\| MASK_NO_UPDATE)
	229	RS6000_CPU ("e300c2", PROCESSOR_PPCE300C2, MASK_SOFT_FLOAT)
	230	RS6000_CPU ("e300c3", PROCESSOR_PPCE300C3, 0)
	231	RS6000_CPU ("e500mc", PROCESSOR_PPCE500MC, MASK_PPC_GFXOPT \| MASK_ISEL)
f10d3ac9	232	RS6000_CPU ("e500mc64", PROCESSOR_PPCE500MC64,
6b39bc38 SB	233	MASK_POWERPC64 \| MASK_PPC_GFXOPT \| MASK_ISEL)
	234	RS6000_CPU ("e5500", PROCESSOR_PPCE5500,
	235	MASK_POWERPC64 \| MASK_PPC_GFXOPT \| MASK_ISEL)
683ed19e EW	236	RS6000_CPU ("e6500", PROCESSOR_PPCE6500, POWERPC_7400_MASK \| MASK_POWERPC64
683ed19e EW	237	\| MASK_MFCRF \| MASK_ISEL)
6b39bc38	238	RS6000_CPU ("860", PROCESSOR_MPCCORE, MASK_SOFT_FLOAT)
f10d3ac9 JM	239	RS6000_CPU ("970", PROCESSOR_POWER4,
	240	POWERPC_7400_MASK \| MASK_PPC_GPOPT \| MASK_MFCRF \| MASK_POWERPC64)
	241	RS6000_CPU ("cell", PROCESSOR_CELL,
	242	POWERPC_7400_MASK \| MASK_PPC_GPOPT \| MASK_MFCRF \| MASK_POWERPC64)
6b39bc38 SB	243	RS6000_CPU ("ec603e", PROCESSOR_PPC603, MASK_SOFT_FLOAT)
6b39bc38 SB	244	RS6000_CPU ("G3", PROCESSOR_PPC750, MASK_PPC_GFXOPT)
f10d3ac9 JM	245	RS6000_CPU ("G4", PROCESSOR_PPC7450, POWERPC_7400_MASK)
	246	RS6000_CPU ("G5", PROCESSOR_POWER4,
	247	POWERPC_7400_MASK \| MASK_PPC_GPOPT \| MASK_MFCRF \| MASK_POWERPC64)
6b39bc38 SB	248	RS6000_CPU ("titan", PROCESSOR_TITAN, MASK_MULHW \| MASK_DLMZB)
	249	RS6000_CPU ("power3", PROCESSOR_PPC630, MASK_PPC_GFXOPT \| MASK_POWERPC64)
	250	RS6000_CPU ("power4", PROCESSOR_POWER4, MASK_POWERPC64 \| MASK_PPC_GPOPT
f10d3ac9	251	\| MASK_PPC_GFXOPT \| MASK_MFCRF)
6b39bc38	252	RS6000_CPU ("power5", PROCESSOR_POWER5, MASK_POWERPC64 \| MASK_PPC_GPOPT
f10d3ac9	253	\| MASK_PPC_GFXOPT \| MASK_MFCRF \| MASK_POPCNTB)
6b39bc38	254	RS6000_CPU ("power5+", PROCESSOR_POWER5, MASK_POWERPC64 \| MASK_PPC_GPOPT
f10d3ac9	255	\| MASK_PPC_GFXOPT \| MASK_MFCRF \| MASK_POPCNTB \| MASK_FPRND)
6b39bc38	256	RS6000_CPU ("power6", PROCESSOR_POWER6, MASK_POWERPC64 \| MASK_PPC_GPOPT
f10d3ac9 JM	257	\| MASK_PPC_GFXOPT \| MASK_MFCRF \| MASK_POPCNTB \| MASK_FPRND
f10d3ac9 JM	258	\| MASK_CMPB \| MASK_DFP \| MASK_RECIP_PRECISION)
6b39bc38	259	RS6000_CPU ("power6x", PROCESSOR_POWER6, MASK_POWERPC64 \| MASK_PPC_GPOPT
f10d3ac9	260	\| MASK_PPC_GFXOPT \| MASK_MFCRF \| MASK_POPCNTB \| MASK_FPRND
fbd4b7f3	261	\| MASK_CMPB \| MASK_DFP \| MASK_RECIP_PRECISION)
19930989	262	RS6000_CPU ("power7", PROCESSOR_POWER7, MASK_POWERPC64 \| ISA_2_6_MASKS_SERVER)
82800987 KL	263	RS6000_CPU ("power8", PROCESSOR_POWER8, MASK_POWERPC64 \| ISA_2_7_MASKS_SERVER
	264	\| OPTION_MASK_HTM)
	265	RS6000_CPU ("power9", PROCESSOR_POWER9, MASK_POWERPC64 \| ISA_3_0_MASKS_SERVER
	266	\| OPTION_MASK_HTM)
5d9d0c94	267	RS6000_CPU ("power10", PROCESSOR_POWER10, MASK_POWERPC64 \| ISA_3_1_MASKS_SERVER)
6b39bc38 SB	268	RS6000_CPU ("powerpc", PROCESSOR_POWERPC, 0)
6b39bc38 SB	269	RS6000_CPU ("powerpc64", PROCESSOR_POWERPC64, MASK_PPC_GFXOPT \| MASK_POWERPC64)
82800987 KL	270	RS6000_CPU ("powerpc64le", PROCESSOR_POWER8, MASK_POWERPC64 \| ISA_2_7_MASKS_SERVER
82800987 KL	271	\| OPTION_MASK_HTM)
6b39bc38	272	RS6000_CPU ("rs64", PROCESSOR_RS64A, MASK_PPC_GFXOPT \| MASK_POWERPC64)