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48d72335 | 1 | ;; Predicate definitions for POWER and PowerPC. |
99dee823 | 2 | ;; Copyright (C) 2005-2021 Free Software Foundation, Inc. |
48d72335 DE |
3 | ;; |
4 | ;; This file is part of GCC. | |
5 | ;; | |
6 | ;; GCC is free software; you can redistribute it and/or modify | |
7 | ;; it under the terms of the GNU General Public License as published by | |
2f83c7d6 | 8 | ;; the Free Software Foundation; either version 3, or (at your option) |
48d72335 DE |
9 | ;; any later version. |
10 | ;; | |
11 | ;; GCC is distributed in the hope that it will be useful, | |
12 | ;; but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | ;; GNU General Public License for more details. | |
15 | ;; | |
16 | ;; You should have received a copy of the GNU General Public License | |
2f83c7d6 NC |
17 | ;; along with GCC; see the file COPYING3. If not see |
18 | ;; <http://www.gnu.org/licenses/>. | |
48d72335 DE |
19 | |
20 | ;; Return 1 for anything except PARALLEL. | |
21 | (define_predicate "any_operand" | |
807e902e | 22 | (match_code "const_int,const_double,const_wide_int,const,symbol_ref,label_ref,subreg,reg,mem")) |
48d72335 DE |
23 | |
24 | ;; Return 1 for any PARALLEL. | |
25 | (define_predicate "any_parallel_operand" | |
26 | (match_code "parallel")) | |
27 | ||
28 | ;; Return 1 if op is COUNT register. | |
29 | (define_predicate "count_register_operand" | |
30 | (and (match_code "reg") | |
1de43f85 | 31 | (match_test "REGNO (op) == CTR_REGNO |
48d72335 | 32 | || REGNO (op) > LAST_VIRTUAL_REGISTER"))) |
a2027aad | 33 | |
fba4b861 MM |
34 | ;; Return 1 if op is a SUBREG that is used to look at a SFmode value as |
35 | ;; and integer or vice versa. | |
36 | ;; | |
37 | ;; In the normal case where SFmode is in a floating point/vector register, it | |
38 | ;; is stored as a DFmode and has a different format. If we don't transform the | |
39 | ;; value, things that use logical operations on the values will get the wrong | |
40 | ;; value. | |
41 | ;; | |
42 | ;; If we don't have 64-bit and direct move, this conversion will be done by | |
43 | ;; store and load, instead of by fiddling with the bits within the register. | |
44 | (define_predicate "sf_subreg_operand" | |
45 | (match_code "subreg") | |
46 | { | |
47 | rtx inner_reg = SUBREG_REG (op); | |
48 | machine_mode inner_mode = GET_MODE (inner_reg); | |
49 | ||
50 | if (TARGET_ALLOW_SF_SUBREG || !REG_P (inner_reg)) | |
51 | return 0; | |
52 | ||
53 | if ((mode == SFmode && GET_MODE_CLASS (inner_mode) == MODE_INT) | |
54 | || (GET_MODE_CLASS (mode) == MODE_INT && inner_mode == SFmode)) | |
55 | { | |
56 | if (INT_REGNO_P (REGNO (inner_reg))) | |
57 | return 0; | |
58 | ||
59 | return 1; | |
60 | } | |
61 | return 0; | |
62 | }) | |
63 | ||
48d72335 DE |
64 | ;; Return 1 if op is an Altivec register. |
65 | (define_predicate "altivec_register_operand" | |
a2027aad SB |
66 | (match_operand 0 "register_operand") |
67 | { | |
2e42a52f | 68 | if (SUBREG_P (op)) |
fba4b861 MM |
69 | { |
70 | if (TARGET_NO_SF_SUBREG && sf_subreg_operand (op, mode)) | |
71 | return 0; | |
72 | ||
73 | op = SUBREG_REG (op); | |
74 | } | |
a2027aad SB |
75 | |
76 | if (!REG_P (op)) | |
77 | return 0; | |
78 | ||
2e42a52f | 79 | if (!HARD_REGISTER_P (op)) |
a2027aad SB |
80 | return 1; |
81 | ||
82 | return ALTIVEC_REGNO_P (REGNO (op)); | |
83 | }) | |
48d72335 | 84 | |
a72c65c7 MM |
85 | ;; Return 1 if op is a VSX register. |
86 | (define_predicate "vsx_register_operand" | |
a2027aad | 87 | (match_operand 0 "register_operand") |
fba4b861 | 88 | { |
2e42a52f | 89 | if (SUBREG_P (op)) |
fba4b861 MM |
90 | { |
91 | if (TARGET_NO_SF_SUBREG && sf_subreg_operand (op, mode)) | |
92 | return 0; | |
93 | ||
94 | op = SUBREG_REG (op); | |
95 | } | |
96 | ||
97 | if (!REG_P (op)) | |
98 | return 0; | |
99 | ||
2e42a52f | 100 | if (!HARD_REGISTER_P (op)) |
fba4b861 MM |
101 | return 1; |
102 | ||
103 | return VSX_REGNO_P (REGNO (op)); | |
104 | }) | |
105 | ||
106 | ;; Like vsx_register_operand, but allow SF SUBREGS | |
107 | (define_predicate "vsx_reg_sfsubreg_ok" | |
108 | (match_operand 0 "register_operand") | |
a2027aad | 109 | { |
2e42a52f | 110 | if (SUBREG_P (op)) |
a2027aad SB |
111 | op = SUBREG_REG (op); |
112 | ||
113 | if (!REG_P (op)) | |
114 | return 0; | |
115 | ||
2e42a52f | 116 | if (!HARD_REGISTER_P (op)) |
a2027aad SB |
117 | return 1; |
118 | ||
119 | return VSX_REGNO_P (REGNO (op)); | |
120 | }) | |
a72c65c7 MM |
121 | |
122 | ;; Return 1 if op is a vector register that operates on floating point vectors | |
123 | ;; (either altivec or VSX). | |
124 | (define_predicate "vfloat_operand" | |
a2027aad SB |
125 | (match_operand 0 "register_operand") |
126 | { | |
2e42a52f | 127 | if (SUBREG_P (op)) |
fba4b861 MM |
128 | { |
129 | if (TARGET_NO_SF_SUBREG && sf_subreg_operand (op, mode)) | |
130 | return 0; | |
131 | ||
132 | op = SUBREG_REG (op); | |
133 | } | |
a2027aad SB |
134 | |
135 | if (!REG_P (op)) | |
136 | return 0; | |
137 | ||
2e42a52f | 138 | if (!HARD_REGISTER_P (op)) |
a2027aad SB |
139 | return 1; |
140 | ||
141 | return VFLOAT_REGNO_P (REGNO (op)); | |
142 | }) | |
a72c65c7 MM |
143 | |
144 | ;; Return 1 if op is a vector register that operates on integer vectors | |
145 | ;; (only altivec, VSX doesn't support integer vectors) | |
146 | (define_predicate "vint_operand" | |
a2027aad SB |
147 | (match_operand 0 "register_operand") |
148 | { | |
2e42a52f | 149 | if (SUBREG_P (op)) |
fba4b861 MM |
150 | { |
151 | if (TARGET_NO_SF_SUBREG && sf_subreg_operand (op, mode)) | |
152 | return 0; | |
153 | ||
154 | op = SUBREG_REG (op); | |
155 | } | |
a2027aad SB |
156 | |
157 | if (!REG_P (op)) | |
158 | return 0; | |
159 | ||
2e42a52f | 160 | if (!HARD_REGISTER_P (op)) |
a2027aad SB |
161 | return 1; |
162 | ||
163 | return VINT_REGNO_P (REGNO (op)); | |
164 | }) | |
a72c65c7 MM |
165 | |
166 | ;; Return 1 if op is a vector register to do logical operations on (and, or, | |
167 | ;; xor, etc.) | |
168 | (define_predicate "vlogical_operand" | |
a2027aad SB |
169 | (match_operand 0 "register_operand") |
170 | { | |
2e42a52f | 171 | if (SUBREG_P (op)) |
fba4b861 MM |
172 | { |
173 | if (TARGET_NO_SF_SUBREG && sf_subreg_operand (op, mode)) | |
174 | return 0; | |
175 | ||
176 | op = SUBREG_REG (op); | |
177 | } | |
178 | ||
a2027aad SB |
179 | |
180 | if (!REG_P (op)) | |
181 | return 0; | |
182 | ||
2e42a52f | 183 | if (!HARD_REGISTER_P (op)) |
a2027aad SB |
184 | return 1; |
185 | ||
186 | return VLOGICAL_REGNO_P (REGNO (op)); | |
187 | }) | |
a72c65c7 | 188 | |
f6b5d695 SB |
189 | ;; Return 1 if op is the carry register. |
190 | (define_predicate "ca_operand" | |
71435564 SB |
191 | (match_operand 0 "register_operand") |
192 | { | |
2e42a52f | 193 | if (SUBREG_P (op)) |
71435564 SB |
194 | op = SUBREG_REG (op); |
195 | ||
196 | if (!REG_P (op)) | |
197 | return 0; | |
198 | ||
199 | return CA_REGNO_P (REGNO (op)); | |
200 | }) | |
48d72335 | 201 | |
e7d77cf9 SB |
202 | ;; Return 1 if operand is constant zero (scalars and vectors). |
203 | (define_predicate "zero_constant" | |
204 | (and (match_code "const_int,const_double,const_wide_int,const_vector") | |
205 | (match_test "op == CONST0_RTX (mode)"))) | |
206 | ||
207 | ;; Return 1 if operand is constant -1 (scalars and vectors). | |
208 | (define_predicate "all_ones_constant" | |
209 | (and (match_code "const_int,const_double,const_wide_int,const_vector") | |
210 | (match_test "op == CONSTM1_RTX (mode) && !FLOAT_MODE_P (mode)"))) | |
211 | ||
afca671b DP |
212 | ;; Return 1 if op is a signed 5-bit constant integer. |
213 | (define_predicate "s5bit_cint_operand" | |
214 | (and (match_code "const_int") | |
215 | (match_test "INTVAL (op) >= -16 && INTVAL (op) <= 15"))) | |
216 | ||
7f3b1997 CL |
217 | ;; Return 1 if op is an unsigned 1-bit constant integer. |
218 | (define_predicate "u1bit_cint_operand" | |
219 | (and (match_code "const_int") | |
220 | (match_test "INTVAL (op) >= 0 && INTVAL (op) <= 1"))) | |
221 | ||
0258b6e4 PB |
222 | ;; Return 1 if op is a unsigned 3-bit constant integer. |
223 | (define_predicate "u3bit_cint_operand" | |
224 | (and (match_code "const_int") | |
225 | (match_test "INTVAL (op) >= 0 && INTVAL (op) <= 7"))) | |
226 | ||
afca671b DP |
227 | ;; Return 1 if op is a unsigned 5-bit constant integer. |
228 | (define_predicate "u5bit_cint_operand" | |
229 | (and (match_code "const_int") | |
230 | (match_test "INTVAL (op) >= 0 && INTVAL (op) <= 31"))) | |
231 | ||
0299bc72 MM |
232 | ;; Return 1 if op is a unsigned 6-bit constant integer. |
233 | (define_predicate "u6bit_cint_operand" | |
234 | (and (match_code "const_int") | |
235 | (match_test "INTVAL (op) >= 0 && INTVAL (op) <= 63"))) | |
236 | ||
e9e6d4f6 KN |
237 | ;; Return 1 if op is an unsigned 7-bit constant integer. |
238 | (define_predicate "u7bit_cint_operand" | |
239 | (and (match_code "const_int") | |
240 | (match_test "IN_RANGE (INTVAL (op), 0, 127)"))) | |
241 | ||
840ac85c KN |
242 | ;; Return 1 if op is a unsigned 8-bit constant integer. |
243 | (define_predicate "u8bit_cint_operand" | |
244 | (and (match_code "const_int") | |
245 | (match_test "IN_RANGE (INTVAL (op), 0, 255)"))) | |
246 | ||
48d72335 | 247 | ;; Return 1 if op is a signed 8-bit constant integer. |
c83eecad | 248 | ;; Integer multiplication complete more quickly |
48d72335 DE |
249 | (define_predicate "s8bit_cint_operand" |
250 | (and (match_code "const_int") | |
251 | (match_test "INTVAL (op) >= -128 && INTVAL (op) <= 127"))) | |
252 | ||
0258b6e4 PB |
253 | ;; Return 1 if op is a unsigned 10-bit constant integer. |
254 | (define_predicate "u10bit_cint_operand" | |
255 | (and (match_code "const_int") | |
256 | (match_test "INTVAL (op) >= 0 && INTVAL (op) <= 1023"))) | |
257 | ||
48d72335 DE |
258 | ;; Return 1 if op is a constant integer that can fit in a D field. |
259 | (define_predicate "short_cint_operand" | |
260 | (and (match_code "const_int") | |
279bb624 | 261 | (match_test "satisfies_constraint_I (op)"))) |
48d72335 DE |
262 | |
263 | ;; Return 1 if op is a constant integer that can fit in an unsigned D field. | |
264 | (define_predicate "u_short_cint_operand" | |
265 | (and (match_code "const_int") | |
279bb624 | 266 | (match_test "satisfies_constraint_K (op)"))) |
48d72335 | 267 | |
0299bc72 MM |
268 | ;; Return 1 if op is a constant integer that is a signed 16-bit constant |
269 | ;; shifted left 16 bits | |
270 | (define_predicate "upper16_cint_operand" | |
271 | (and (match_code "const_int") | |
272 | (match_test "satisfies_constraint_L (op)"))) | |
273 | ||
48d72335 DE |
274 | ;; Return 1 if op is a constant integer that cannot fit in a signed D field. |
275 | (define_predicate "non_short_cint_operand" | |
276 | (and (match_code "const_int") | |
277 | (match_test "(unsigned HOST_WIDE_INT) | |
278 | (INTVAL (op) + 0x8000) >= 0x10000"))) | |
279 | ||
7f3b1997 CL |
280 | ;; Return 1 if op is a 32-bit constant signed integer |
281 | (define_predicate "s32bit_cint_operand" | |
282 | (and (match_code "const_int") | |
283 | (match_test "(0x80000000 + UINTVAL (op)) >> 32 == 0"))) | |
284 | ||
285 | ;; Return 1 if op is a constant 32-bit unsigned | |
286 | (define_predicate "c32bit_cint_operand" | |
287 | (and (match_code "const_int") | |
288 | (match_test "((UINTVAL (op) >> 32) == 0)"))) | |
289 | ||
48d72335 DE |
290 | ;; Return 1 if op is a positive constant integer that is an exact power of 2. |
291 | (define_predicate "exact_log2_cint_operand" | |
292 | (and (match_code "const_int") | |
293 | (match_test "INTVAL (op) > 0 && exact_log2 (INTVAL (op)) >= 0"))) | |
294 | ||
5aebfdad RH |
295 | ;; Match op = 0 or op = 1. |
296 | (define_predicate "const_0_to_1_operand" | |
297 | (and (match_code "const_int") | |
298 | (match_test "IN_RANGE (INTVAL (op), 0, 1)"))) | |
299 | ||
7a279bed AS |
300 | ;; Match op = -1, op = 0, or op = 1. |
301 | (define_predicate "const_m1_to_1_operand" | |
302 | (and (match_code "const_int") | |
303 | (match_test "IN_RANGE (INTVAL (op), -1, 1)"))) | |
304 | ||
06b39289 MM |
305 | ;; Match op = 0..3. |
306 | (define_predicate "const_0_to_3_operand" | |
307 | (and (match_code "const_int") | |
308 | (match_test "IN_RANGE (INTVAL (op), 0, 3)"))) | |
309 | ||
5aebfdad RH |
310 | ;; Match op = 2 or op = 3. |
311 | (define_predicate "const_2_to_3_operand" | |
312 | (and (match_code "const_int") | |
313 | (match_test "IN_RANGE (INTVAL (op), 2, 3)"))) | |
314 | ||
c5e74d9d MM |
315 | ;; Match op = 0..7. |
316 | (define_predicate "const_0_to_7_operand" | |
317 | (and (match_code "const_int") | |
318 | (match_test "IN_RANGE (INTVAL (op), 0, 7)"))) | |
319 | ||
16370e79 | 320 | ;; Match op = 0..11 |
df3aba14 | 321 | (define_predicate "const_0_to_12_operand" |
16370e79 | 322 | (and (match_code "const_int") |
df3aba14 | 323 | (match_test "IN_RANGE (INTVAL (op), 0, 12)"))) |
16370e79 | 324 | |
f62511da MM |
325 | ;; Match op = 0..15 |
326 | (define_predicate "const_0_to_15_operand" | |
327 | (and (match_code "const_int") | |
328 | (match_test "IN_RANGE (INTVAL (op), 0, 15)"))) | |
329 | ||
ed383d79 BS |
330 | ;; Return 1 if op is a 34-bit constant integer. |
331 | (define_predicate "cint34_operand" | |
332 | (match_code "const_int") | |
333 | { | |
7a775242 | 334 | if (!TARGET_PREFIXED) |
ed383d79 BS |
335 | return 0; |
336 | ||
03e487e5 | 337 | return SIGNED_INTEGER_34BIT_P (INTVAL (op)); |
ed383d79 BS |
338 | }) |
339 | ||
8c1249f9 | 340 | ;; Return 1 if op is a register that is not special. |
fba4b861 MM |
341 | ;; Disallow (SUBREG:SF (REG:SI)) and (SUBREG:SI (REG:SF)) on VSX systems where |
342 | ;; you need to be careful in moving a SFmode to SImode and vice versa due to | |
343 | ;; the fact that SFmode is represented as DFmode in the VSX registers. | |
48d72335 | 344 | (define_predicate "gpc_reg_operand" |
a2027aad SB |
345 | (match_operand 0 "register_operand") |
346 | { | |
2e42a52f | 347 | if (SUBREG_P (op)) |
fba4b861 MM |
348 | { |
349 | if (TARGET_NO_SF_SUBREG && sf_subreg_operand (op, mode)) | |
350 | return 0; | |
351 | ||
352 | op = SUBREG_REG (op); | |
353 | } | |
a2027aad SB |
354 | |
355 | if (!REG_P (op)) | |
356 | return 0; | |
357 | ||
2e42a52f | 358 | if (!HARD_REGISTER_P (op)) |
8a480dc3 AM |
359 | return 1; |
360 | ||
361 | if (TARGET_ALTIVEC && ALTIVEC_REGNO_P (REGNO (op))) | |
a2027aad SB |
362 | return 1; |
363 | ||
f62511da MM |
364 | if (TARGET_VSX && VSX_REGNO_P (REGNO (op))) |
365 | return 1; | |
366 | ||
a2027aad SB |
367 | return INT_REGNO_P (REGNO (op)) || FP_REGNO_P (REGNO (op)); |
368 | }) | |
48d72335 | 369 | |
f62511da | 370 | ;; Return 1 if op is a general purpose register. Unlike gpc_reg_operand, don't |
fba4b861 MM |
371 | ;; allow floating point or vector registers. Since vector registers are not |
372 | ;; allowed, we don't have to reject SFmode/SImode subregs. | |
f62511da MM |
373 | (define_predicate "int_reg_operand" |
374 | (match_operand 0 "register_operand") | |
375 | { | |
2e42a52f | 376 | if (SUBREG_P (op)) |
fba4b861 MM |
377 | { |
378 | if (TARGET_NO_SF_SUBREG && sf_subreg_operand (op, mode)) | |
379 | return 0; | |
380 | ||
381 | op = SUBREG_REG (op); | |
382 | } | |
f62511da MM |
383 | |
384 | if (!REG_P (op)) | |
385 | return 0; | |
386 | ||
2e42a52f | 387 | if (!HARD_REGISTER_P (op)) |
f62511da MM |
388 | return 1; |
389 | ||
390 | return INT_REGNO_P (REGNO (op)); | |
391 | }) | |
392 | ||
526303ec | 393 | ;; Like int_reg_operand, but don't return true for pseudo registers |
fba4b861 MM |
394 | ;; We don't have to check for SF SUBREGS because pseudo registers |
395 | ;; are not allowed, and SF SUBREGs are ok within GPR registers. | |
526303ec MM |
396 | (define_predicate "int_reg_operand_not_pseudo" |
397 | (match_operand 0 "register_operand") | |
398 | { | |
2e42a52f | 399 | if (SUBREG_P (op)) |
526303ec MM |
400 | op = SUBREG_REG (op); |
401 | ||
402 | if (!REG_P (op)) | |
403 | return 0; | |
404 | ||
2e42a52f | 405 | if (!HARD_REGISTER_P (op)) |
526303ec MM |
406 | return 0; |
407 | ||
408 | return INT_REGNO_P (REGNO (op)); | |
409 | }) | |
410 | ||
f62511da MM |
411 | ;; Like int_reg_operand, but only return true for base registers |
412 | (define_predicate "base_reg_operand" | |
413 | (match_operand 0 "int_reg_operand") | |
414 | { | |
2e42a52f | 415 | if (SUBREG_P (op)) |
f62511da MM |
416 | op = SUBREG_REG (op); |
417 | ||
418 | if (!REG_P (op)) | |
419 | return 0; | |
420 | ||
421 | return (REGNO (op) != FIRST_GPR_REGNO); | |
422 | }) | |
423 | ||
0299bc72 MM |
424 | |
425 | ;; Return true if this is a traditional floating point register | |
426 | (define_predicate "fpr_reg_operand" | |
427 | (match_code "reg,subreg") | |
428 | { | |
429 | HOST_WIDE_INT r; | |
430 | ||
2e42a52f | 431 | if (SUBREG_P (op)) |
0299bc72 MM |
432 | op = SUBREG_REG (op); |
433 | ||
434 | if (!REG_P (op)) | |
435 | return 0; | |
436 | ||
437 | r = REGNO (op); | |
2e42a52f | 438 | if (!HARD_REGISTER_NUM_P (r)) |
0299bc72 MM |
439 | return 1; |
440 | ||
441 | return FP_REGNO_P (r); | |
442 | }) | |
443 | ||
f62511da MM |
444 | ;; Return 1 if op is a general purpose register that is an even register |
445 | ;; which suitable for a load/store quad operation | |
65c98fde AM |
446 | ;; Subregs are not allowed here because when they are combine can |
447 | ;; create (subreg:PTI (reg:TI pseudo)) which will cause reload to | |
448 | ;; think the innermost reg needs reloading, in TImode instead of | |
449 | ;; PTImode. So reload will choose a reg in TImode which has no | |
450 | ;; requirement that the reg be even. | |
f62511da | 451 | (define_predicate "quad_int_reg_operand" |
65c98fde | 452 | (match_code "reg") |
f62511da MM |
453 | { |
454 | HOST_WIDE_INT r; | |
455 | ||
b846c948 | 456 | if (!TARGET_QUAD_MEMORY && !TARGET_QUAD_MEMORY_ATOMIC) |
f62511da MM |
457 | return 0; |
458 | ||
f62511da | 459 | r = REGNO (op); |
2e42a52f | 460 | if (!HARD_REGISTER_NUM_P (r)) |
f62511da MM |
461 | return 1; |
462 | ||
463 | return (INT_REGNO_P (r) && ((r & 1) == 0)); | |
464 | }) | |
465 | ||
48d72335 DE |
466 | ;; Return 1 if op is a register that is a condition register field. |
467 | (define_predicate "cc_reg_operand" | |
a2027aad SB |
468 | (match_operand 0 "register_operand") |
469 | { | |
2e42a52f | 470 | if (SUBREG_P (op)) |
a2027aad SB |
471 | op = SUBREG_REG (op); |
472 | ||
473 | if (!REG_P (op)) | |
474 | return 0; | |
475 | ||
476 | if (REGNO (op) > LAST_VIRTUAL_REGISTER) | |
477 | return 1; | |
478 | ||
479 | return CR_REGNO_P (REGNO (op)); | |
480 | }) | |
48d72335 DE |
481 | |
482 | ;; Return 1 if op is a register that is a condition register field not cr0. | |
483 | (define_predicate "cc_reg_not_cr0_operand" | |
a2027aad SB |
484 | (match_operand 0 "register_operand") |
485 | { | |
2e42a52f | 486 | if (SUBREG_P (op)) |
a2027aad SB |
487 | op = SUBREG_REG (op); |
488 | ||
489 | if (!REG_P (op)) | |
490 | return 0; | |
491 | ||
492 | if (REGNO (op) > LAST_VIRTUAL_REGISTER) | |
493 | return 1; | |
494 | ||
495 | return CR_REGNO_NOT_CR0_P (REGNO (op)); | |
496 | }) | |
48d72335 DE |
497 | |
498 | ;; Return 1 if op is a constant integer valid for D field | |
499 | ;; or non-special register register. | |
500 | (define_predicate "reg_or_short_operand" | |
501 | (if_then_else (match_code "const_int") | |
502 | (match_operand 0 "short_cint_operand") | |
503 | (match_operand 0 "gpc_reg_operand"))) | |
504 | ||
48d72335 DE |
505 | ;; Return 1 if op is a constant integer valid for DS field |
506 | ;; or non-special register. | |
507 | (define_predicate "reg_or_aligned_short_operand" | |
508 | (if_then_else (match_code "const_int") | |
509 | (and (match_operand 0 "short_cint_operand") | |
510 | (match_test "!(INTVAL (op) & 3)")) | |
511 | (match_operand 0 "gpc_reg_operand"))) | |
512 | ||
513 | ;; Return 1 if op is a constant integer whose high-order 16 bits are zero | |
514 | ;; or non-special register. | |
515 | (define_predicate "reg_or_u_short_operand" | |
516 | (if_then_else (match_code "const_int") | |
517 | (match_operand 0 "u_short_cint_operand") | |
518 | (match_operand 0 "gpc_reg_operand"))) | |
519 | ||
e7d77cf9 | 520 | ;; Return 1 if op is any constant integer or a non-special register. |
48d72335 DE |
521 | (define_predicate "reg_or_cint_operand" |
522 | (ior (match_code "const_int") | |
523 | (match_operand 0 "gpc_reg_operand"))) | |
524 | ||
e7d77cf9 SB |
525 | ;; Return 1 if op is constant zero or a non-special register. |
526 | (define_predicate "reg_or_zero_operand" | |
527 | (ior (match_operand 0 "zero_constant") | |
528 | (match_operand 0 "gpc_reg_operand"))) | |
529 | ||
b6872a13 AM |
530 | ;; Return 1 if op is a constant integer valid for addition with addis, addi. |
531 | (define_predicate "add_cint_operand" | |
532 | (and (match_code "const_int") | |
2d302f47 MT |
533 | (match_test "((unsigned HOST_WIDE_INT) INTVAL (op) |
534 | + (mode == SImode ? 0x80000000 : 0x80008000)) | |
b6872a13 AM |
535 | < (unsigned HOST_WIDE_INT) 0x100000000ll"))) |
536 | ||
4ae234b0 | 537 | ;; Return 1 if op is a constant integer valid for addition |
48d72335 | 538 | ;; or non-special register. |
4ae234b0 | 539 | (define_predicate "reg_or_add_cint_operand" |
48d72335 | 540 | (if_then_else (match_code "const_int") |
b6872a13 | 541 | (match_operand 0 "add_cint_operand") |
48d72335 DE |
542 | (match_operand 0 "gpc_reg_operand"))) |
543 | ||
4ae234b0 | 544 | ;; Return 1 if op is a constant integer valid for subtraction |
48d72335 | 545 | ;; or non-special register. |
4ae234b0 | 546 | (define_predicate "reg_or_sub_cint_operand" |
48d72335 | 547 | (if_then_else (match_code "const_int") |
da226db2 | 548 | (match_test "(unsigned HOST_WIDE_INT) |
d7ca26e4 | 549 | (- UINTVAL (op) + (mode == SImode ? 0x80000000 : 0x80008000)) |
da226db2 | 550 | < (unsigned HOST_WIDE_INT) 0x100000000ll") |
48d72335 DE |
551 | (match_operand 0 "gpc_reg_operand"))) |
552 | ||
553 | ;; Return 1 if op is any 32-bit unsigned constant integer | |
554 | ;; or non-special register. | |
555 | (define_predicate "reg_or_logical_cint_operand" | |
556 | (if_then_else (match_code "const_int") | |
557 | (match_test "(GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT | |
558 | && INTVAL (op) >= 0) | |
559 | || ((INTVAL (op) & GET_MODE_MASK (mode) | |
560 | & (~ (unsigned HOST_WIDE_INT) 0xffffffff)) == 0)") | |
da226db2 | 561 | (match_operand 0 "gpc_reg_operand"))) |
48d72335 | 562 | |
f62511da MM |
563 | ;; Like reg_or_logical_cint_operand, but allow vsx registers |
564 | (define_predicate "vsx_reg_or_cint_operand" | |
565 | (ior (match_operand 0 "vsx_register_operand") | |
566 | (match_operand 0 "reg_or_logical_cint_operand"))) | |
567 | ||
48d72335 DE |
568 | ;; Return 1 if operand is a CONST_DOUBLE that can be set in a register |
569 | ;; with no more than one instruction per word. | |
570 | (define_predicate "easy_fp_constant" | |
571 | (match_code "const_double") | |
572 | { | |
5678e339 | 573 | gcc_assert (GET_MODE (op) == mode && SCALAR_FLOAT_MODE_P (mode)); |
48d72335 | 574 | |
b49f1a7e AM |
575 | /* Consider all constants with -msoft-float to be easy when regs are |
576 | 32-bit and thus can be loaded with a maximum of 2 insns. For | |
577 | 64-bit avoid long dependent insn sequences. */ | |
5678e339 | 578 | if (TARGET_SOFT_FLOAT) |
b49f1a7e AM |
579 | { |
580 | if (!TARGET_POWERPC64) | |
581 | return 1; | |
582 | ||
583 | int size = GET_MODE_SIZE (mode); | |
584 | if (size < 8) | |
585 | return 1; | |
586 | ||
587 | int load_from_mem_insns = 2; | |
588 | if (size > 8) | |
589 | load_from_mem_insns++; | |
590 | if (TARGET_CMODEL != CMODEL_SMALL) | |
591 | load_from_mem_insns++; | |
592 | if (num_insns_constant (op, mode) <= load_from_mem_insns) | |
593 | return 1; | |
594 | } | |
48d72335 | 595 | |
45d34276 AM |
596 | /* 0.0D is not all zero bits. */ |
597 | if (DECIMAL_FLOAT_MODE_P (mode)) | |
598 | return 0; | |
599 | ||
c6d5ff83 | 600 | /* The constant 0.0 is easy under VSX. */ |
5678e339 | 601 | if (TARGET_VSX && op == CONST0_RTX (mode)) |
c6d5ff83 MM |
602 | return 1; |
603 | ||
949c7a09 MM |
604 | /* If we have the ISA 3.1 XXSPLTIDP instruction, see if the constant can |
605 | be loaded with that instruction. */ | |
606 | if (xxspltidp_operand (op, mode)) | |
607 | return 1; | |
608 | ||
913aaf1a MM |
609 | /* If we have the ISA 3.1 LXVKQ instruction, see if the constant can be loaded |
610 | with that instruction. */ | |
611 | if (lxvkq_operand (op, mode)) | |
612 | return 1; | |
613 | ||
5678e339 AM |
614 | /* Otherwise consider floating point constants hard, so that the |
615 | constant gets pushed to memory during the early RTL phases. This | |
616 | has the advantage that double precision constants that can be | |
617 | represented in single precision without a loss of precision will | |
618 | use single precision loads. */ | |
619 | return 0; | |
25adc5d0 MM |
620 | }) |
621 | ||
1a3c3ee9 MM |
622 | ;; Return 1 if the operand is a constant that can loaded with a XXSPLTIB |
623 | ;; instruction and then a VUPKHSB, VECSB2W or VECSB2D instruction. | |
50c78b9a MM |
624 | |
625 | (define_predicate "xxspltib_constant_split" | |
626 | (match_code "const_vector,vec_duplicate,const_int") | |
627 | { | |
628 | int value = 256; | |
629 | int num_insns = -1; | |
630 | ||
631 | if (!xxspltib_constant_p (op, mode, &num_insns, &value)) | |
632 | return false; | |
633 | ||
634 | return num_insns > 1; | |
635 | }) | |
636 | ||
637 | ||
1a3c3ee9 MM |
638 | ;; Return 1 if the operand is constant that can loaded directly with a XXSPLTIB |
639 | ;; instruction. | |
50c78b9a MM |
640 | |
641 | (define_predicate "xxspltib_constant_nosplit" | |
642 | (match_code "const_vector,vec_duplicate,const_int") | |
643 | { | |
644 | int value = 256; | |
645 | int num_insns = -1; | |
646 | ||
647 | if (!xxspltib_constant_p (op, mode, &num_insns, &value)) | |
648 | return false; | |
649 | ||
650 | return num_insns == 1; | |
651 | }) | |
652 | ||
949c7a09 MM |
653 | ;; Return 1 if operand is a SF/DF CONST_DOUBLE or V2DF CONST_VECTOR that can be |
654 | ;; loaded via the ISA 3.1 XXSPLTIDP instruction. | |
655 | (define_predicate "xxspltidp_operand" | |
656 | (match_code "const_double,const_vector,vec_duplicate") | |
657 | { | |
658 | HOST_WIDE_INT value = 0; | |
659 | return xxspltidp_constant_p (op, mode, &value); | |
660 | }) | |
661 | ||
913aaf1a MM |
662 | ;; Return 1 if the operand is an IEEE 128-bit special constant that can be |
663 | ;; loaded with the LXVKQ instruction. | |
664 | (define_predicate "lxvkq_operand" | |
665 | (match_code "const_double") | |
666 | { | |
667 | int immediate = 0; | |
668 | return lxvkq_constant_p (op, mode, &immediate); | |
669 | }) | |
670 | ||
48d72335 DE |
671 | ;; Return 1 if the operand is a CONST_VECTOR and can be loaded into a |
672 | ;; vector register without using memory. | |
673 | (define_predicate "easy_vector_constant" | |
674 | (match_code "const_vector") | |
675 | { | |
e3a69bb4 | 676 | if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)) |
66180ff3 | 677 | { |
50c78b9a MM |
678 | int value = 256; |
679 | int num_insns = -1; | |
680 | ||
681 | if (zero_constant (op, mode) || all_ones_constant (op, mode)) | |
682 | return true; | |
683 | ||
949c7a09 MM |
684 | if (xxspltidp_operand (op, mode)) |
685 | return true; | |
686 | ||
50c78b9a MM |
687 | if (TARGET_P9_VECTOR |
688 | && xxspltib_constant_p (op, mode, &num_insns, &value)) | |
e3a69bb4 MM |
689 | return true; |
690 | ||
66180ff3 PB |
691 | return easy_altivec_constant (op, mode); |
692 | } | |
48d72335 | 693 | |
66180ff3 | 694 | return false; |
48d72335 DE |
695 | }) |
696 | ||
697 | ;; Same as easy_vector_constant but only for EASY_VECTOR_15_ADD_SELF. | |
698 | (define_predicate "easy_vector_constant_add_self" | |
699 | (and (match_code "const_vector") | |
700 | (and (match_test "TARGET_ALTIVEC") | |
66180ff3 PB |
701 | (match_test "easy_altivec_constant (op, mode)"))) |
702 | { | |
12b1c80b | 703 | HOST_WIDE_INT val; |
8345965a | 704 | int elt; |
12b1c80b PB |
705 | if (mode == V2DImode || mode == V2DFmode) |
706 | return 0; | |
8345965a AM |
707 | elt = BYTES_BIG_ENDIAN ? GET_MODE_NUNITS (mode) - 1 : 0; |
708 | val = const_vector_elt_as_int (op, elt); | |
847535b6 | 709 | val = ((val & 0xff) ^ 0x80) - 0x80; |
66180ff3 PB |
710 | return EASY_VECTOR_15_ADD_SELF (val); |
711 | }) | |
48d72335 | 712 | |
29e6733c MM |
713 | ;; Same as easy_vector_constant but only for EASY_VECTOR_MSB. |
714 | (define_predicate "easy_vector_constant_msb" | |
715 | (and (match_code "const_vector") | |
716 | (and (match_test "TARGET_ALTIVEC") | |
e0e82856 JJ |
717 | (match_test "easy_altivec_constant (op, mode)") |
718 | (match_test "vspltis_shifted (op) == 0"))) | |
29e6733c | 719 | { |
12b1c80b | 720 | HOST_WIDE_INT val; |
e0e82856 JJ |
721 | int elt, sz = easy_altivec_constant (op, mode); |
722 | machine_mode inner = GET_MODE_INNER (mode); | |
723 | int isz = GET_MODE_SIZE (inner); | |
12b1c80b PB |
724 | if (mode == V2DImode || mode == V2DFmode) |
725 | return 0; | |
8345965a | 726 | elt = BYTES_BIG_ENDIAN ? GET_MODE_NUNITS (mode) - 1 : 0; |
e0e82856 JJ |
727 | if (isz < sz) |
728 | { | |
729 | if (const_vector_elt_as_int (op, elt) != 0) | |
730 | return 0; | |
731 | elt += (BYTES_BIG_ENDIAN ? -1 : 1) * (sz - isz) / isz; | |
732 | } | |
733 | else if (isz > sz) | |
734 | inner = smallest_int_mode_for_size (sz * BITS_PER_UNIT); | |
8345965a | 735 | val = const_vector_elt_as_int (op, elt); |
e0e82856 | 736 | return EASY_VECTOR_MSB (val, inner); |
29e6733c MM |
737 | }) |
738 | ||
683be46f MM |
739 | ;; Return true if this is an easy altivec constant that we form |
740 | ;; by using VSLDOI. | |
741 | (define_predicate "easy_vector_constant_vsldoi" | |
742 | (and (match_code "const_vector") | |
743 | (and (match_test "TARGET_ALTIVEC") | |
744 | (and (match_test "easy_altivec_constant (op, mode)") | |
745 | (match_test "vspltis_shifted (op) != 0"))))) | |
746 | ||
391675ac MM |
747 | ;; Return 1 if operand is a vector int register or is either a vector constant |
748 | ;; of all 0 bits of a vector constant of all 1 bits. | |
749 | (define_predicate "vector_int_reg_or_same_bit" | |
750 | (match_code "reg,subreg,const_vector") | |
751 | { | |
752 | if (GET_MODE_CLASS (mode) != MODE_VECTOR_INT) | |
753 | return 0; | |
754 | ||
755 | else if (REG_P (op) || SUBREG_P (op)) | |
756 | return vint_operand (op, mode); | |
757 | ||
758 | else | |
759 | return op == CONST0_RTX (mode) || op == CONSTM1_RTX (mode); | |
760 | }) | |
761 | ||
48d72335 | 762 | ;; Return 1 if operand is 0.0. |
48d72335 DE |
763 | (define_predicate "zero_fp_constant" |
764 | (and (match_code "const_double") | |
ebb109ad | 765 | (match_test "SCALAR_FLOAT_MODE_P (mode) |
48d72335 DE |
766 | && op == CONST0_RTX (mode)"))) |
767 | ||
768 | ;; Return 1 if the operand is in volatile memory. Note that during the | |
769 | ;; RTL generation phase, memory_operand does not return TRUE for volatile | |
770 | ;; memory references. So this function allows us to recognize volatile | |
f3b569ca | 771 | ;; references where it's safe. |
48d72335 | 772 | (define_predicate "volatile_mem_operand" |
5744faa9 SB |
773 | (and (match_code "mem") |
774 | (match_test "MEM_VOLATILE_P (op)") | |
48d72335 | 775 | (if_then_else (match_test "reload_completed") |
3cb8ee5c PB |
776 | (match_operand 0 "memory_operand") |
777 | (match_test "memory_address_p (mode, XEXP (op, 0))")))) | |
48d72335 | 778 | |
5744faa9 SB |
779 | ;; Return 1 if the operand is a volatile or non-volatile memory operand. |
780 | (define_predicate "any_memory_operand" | |
781 | (ior (match_operand 0 "memory_operand") | |
782 | (match_operand 0 "volatile_mem_operand"))) | |
783 | ||
48d72335 DE |
784 | ;; Return 1 if the operand is an offsettable memory operand. |
785 | (define_predicate "offsettable_mem_operand" | |
92576357 | 786 | (and (match_operand 0 "any_memory_operand") |
406d1650 | 787 | (match_test "offsettable_nonstrict_memref_p (op)"))) |
48d72335 | 788 | |
52e14b96 MM |
789 | ;; Return 1 if the operand is a simple offsettable memory operand |
790 | ;; that does not include pre-increment, post-increment, etc. | |
791 | (define_predicate "simple_offsettable_mem_operand" | |
792 | (match_operand 0 "offsettable_mem_operand") | |
793 | { | |
794 | rtx addr = XEXP (op, 0); | |
795 | ||
796 | if (GET_CODE (addr) != PLUS && GET_CODE (addr) != LO_SUM) | |
797 | return 0; | |
798 | ||
799 | if (!CONSTANT_P (XEXP (addr, 1))) | |
800 | return 0; | |
801 | ||
802 | return base_reg_operand (XEXP (addr, 0), Pmode); | |
803 | }) | |
804 | ||
f62511da | 805 | ;; Return 1 if the operand is suitable for load/store quad memory. |
bf245bf4 | 806 | ;; This predicate only checks for non-atomic loads/stores (not lqarx/stqcx). |
f62511da MM |
807 | (define_predicate "quad_memory_operand" |
808 | (match_code "mem") | |
809 | { | |
bf245bf4 | 810 | if (!TARGET_QUAD_MEMORY && !TARGET_SYNC_TI) |
3fd2b007 | 811 | return false; |
f62511da | 812 | |
3fd2b007 MM |
813 | if (GET_MODE_SIZE (mode) != 16 || !MEM_P (op) || MEM_ALIGN (op) < 128) |
814 | return false; | |
f62511da | 815 | |
0dc47331 | 816 | return quad_address_p (XEXP (op, 0), mode, false); |
3fd2b007 | 817 | }) |
f62511da | 818 | |
3fd2b007 MM |
819 | ;; Return 1 if the operand is suitable for load/store to vector registers with |
820 | ;; d-form addressing (register+offset), which was added in ISA 3.0. | |
821 | ;; Unlike quad_memory_operand, we do not have to check for alignment. | |
822 | (define_predicate "vsx_quad_dform_memory_operand" | |
823 | (match_code "mem") | |
824 | { | |
db1e5f32 | 825 | if (!TARGET_P9_VECTOR || !MEM_P (op) || GET_MODE_SIZE (mode) != 16) |
3fd2b007 | 826 | return false; |
f62511da | 827 | |
3fd2b007 | 828 | return quad_address_p (XEXP (op, 0), mode, false); |
f62511da MM |
829 | }) |
830 | ||
bf00cc0f AM |
831 | ;; Return 1 if the operand is an indexed or indirect memory operand. |
832 | (define_predicate "indexed_or_indirect_operand" | |
833 | (match_code "mem") | |
834 | { | |
835 | op = XEXP (op, 0); | |
a72c65c7 | 836 | if (VECTOR_MEM_ALTIVEC_P (mode) |
bf00cc0f | 837 | && GET_CODE (op) == AND |
2e42a52f | 838 | && CONST_INT_P (XEXP (op, 1)) |
bf00cc0f AM |
839 | && INTVAL (XEXP (op, 1)) == -16) |
840 | op = XEXP (op, 0); | |
841 | ||
842 | return indexed_or_indirect_address (op, mode); | |
843 | }) | |
844 | ||
f62511da MM |
845 | ;; Like indexed_or_indirect_operand, but also allow a GPR register if direct |
846 | ;; moves are supported. | |
847 | (define_predicate "reg_or_indexed_operand" | |
bdb60a10 | 848 | (match_code "mem,reg,subreg") |
f62511da MM |
849 | { |
850 | if (MEM_P (op)) | |
851 | return indexed_or_indirect_operand (op, mode); | |
852 | else if (TARGET_DIRECT_MOVE) | |
853 | return register_operand (op, mode); | |
854 | return | |
855 | 0; | |
856 | }) | |
857 | ||
a72c65c7 MM |
858 | ;; Return 1 if the operand is an indexed or indirect memory operand with an |
859 | ;; AND -16 in it, used to recognize when we need to switch to Altivec loads | |
860 | ;; to realign loops instead of VSX (altivec silently ignores the bottom bits, | |
861 | ;; while VSX uses the full address and traps) | |
862 | (define_predicate "altivec_indexed_or_indirect_operand" | |
863 | (match_code "mem") | |
864 | { | |
865 | op = XEXP (op, 0); | |
866 | if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode) | |
867 | && GET_CODE (op) == AND | |
2e42a52f | 868 | && CONST_INT_P (XEXP (op, 1)) |
a72c65c7 MM |
869 | && INTVAL (XEXP (op, 1)) == -16) |
870 | return indexed_or_indirect_address (XEXP (op, 0), mode); | |
871 | ||
872 | return 0; | |
873 | }) | |
874 | ||
11aac14f | 875 | ;; Return 1 if the operand is an indexed or indirect address. |
bf00cc0f AM |
876 | (define_special_predicate "indexed_or_indirect_address" |
877 | (and (match_test "REG_P (op) | |
11aac14f | 878 | || (GET_CODE (op) == PLUS |
bf00cc0f AM |
879 | /* Omit testing REG_P (XEXP (op, 0)). */ |
880 | && REG_P (XEXP (op, 1)))") | |
881 | (match_operand 0 "address_operand"))) | |
11aac14f | 882 | |
c6d5ff83 MM |
883 | ;; Return 1 if the operand is an index-form address. |
884 | (define_special_predicate "indexed_address" | |
885 | (match_test "(GET_CODE (op) == PLUS | |
886 | && REG_P (XEXP (op, 0)) | |
887 | && REG_P (XEXP (op, 1)))")) | |
888 | ||
889 | ;; Return 1 if the operand is a MEM with an update-form address. This may | |
890 | ;; also include update-indexed form. | |
891 | (define_special_predicate "update_address_mem" | |
892 | (match_test "(MEM_P (op) | |
893 | && (GET_CODE (XEXP (op, 0)) == PRE_INC | |
894 | || GET_CODE (XEXP (op, 0)) == PRE_DEC | |
895 | || GET_CODE (XEXP (op, 0)) == PRE_MODIFY))")) | |
896 | ||
7a279bed AS |
897 | ;; Anything that matches memory_operand but does not update the address. |
898 | (define_predicate "non_update_memory_operand" | |
899 | (match_code "mem") | |
900 | { | |
901 | if (update_address_mem (op, mode)) | |
902 | return 0; | |
903 | return memory_operand (op, mode); | |
904 | }) | |
905 | ||
d839f53b SB |
906 | ;; Return 1 if the operand is a MEM with an indexed-form address. |
907 | (define_special_predicate "indexed_address_mem" | |
908 | (match_test "(MEM_P (op) | |
909 | && (indexed_address (XEXP (op, 0), mode) | |
910 | || (GET_CODE (XEXP (op, 0)) == PRE_MODIFY | |
911 | && indexed_address (XEXP (XEXP (op, 0), 1), mode))))")) | |
912 | ||
48d72335 DE |
913 | ;; Return 1 if the operand is either a non-special register or can be used |
914 | ;; as the operand of a `mode' add insn. | |
915 | (define_predicate "add_operand" | |
916 | (if_then_else (match_code "const_int") | |
279bb624 | 917 | (match_test "satisfies_constraint_I (op) |
54ba911f MM |
918 | || satisfies_constraint_L (op) |
919 | || satisfies_constraint_eI (op)") | |
48d72335 DE |
920 | (match_operand 0 "gpc_reg_operand"))) |
921 | ||
969ce0b0 SB |
922 | ;; Return 1 if the operand is either a non-special register, or 0, or -1. |
923 | (define_predicate "adde_operand" | |
924 | (if_then_else (match_code "const_int") | |
925 | (match_test "INTVAL (op) == 0 || INTVAL (op) == -1") | |
926 | (match_operand 0 "gpc_reg_operand"))) | |
927 | ||
48d72335 DE |
928 | ;; Return 1 if OP is a constant but not a valid add_operand. |
929 | (define_predicate "non_add_cint_operand" | |
930 | (and (match_code "const_int") | |
0a8c8f4d | 931 | (not (match_operand 0 "add_operand")))) |
48d72335 | 932 | |
410c459d | 933 | ;; Return 1 if the operand is a constant that can be used as the operand |
21edd5af | 934 | ;; of an AND, OR or XOR. |
410c459d | 935 | (define_predicate "logical_const_operand" |
da226db2 | 936 | (match_code "const_int") |
48d72335 | 937 | { |
da226db2 | 938 | HOST_WIDE_INT opl; |
48d72335 | 939 | |
da226db2 | 940 | opl = INTVAL (op) & GET_MODE_MASK (mode); |
48d72335 DE |
941 | |
942 | return ((opl & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0 | |
943 | || (opl & ~ (unsigned HOST_WIDE_INT) 0xffff0000) == 0); | |
944 | }) | |
945 | ||
410c459d | 946 | ;; Return 1 if the operand is a non-special register or a constant that |
21edd5af | 947 | ;; can be used as the operand of an AND, OR or XOR. |
410c459d PB |
948 | (define_predicate "logical_operand" |
949 | (ior (match_operand 0 "gpc_reg_operand") | |
950 | (match_operand 0 "logical_const_operand"))) | |
951 | ||
48d72335 DE |
952 | ;; Return 1 if op is a constant that is not a logical operand, but could |
953 | ;; be split into one. | |
954 | (define_predicate "non_logical_cint_operand" | |
807e902e | 955 | (and (match_code "const_int,const_wide_int") |
48d72335 DE |
956 | (and (not (match_operand 0 "logical_operand")) |
957 | (match_operand 0 "reg_or_logical_cint_operand")))) | |
958 | ||
48d72335 DE |
959 | ;; Return 1 if the operand is either a non-special register or a |
960 | ;; constant that can be used as the operand of a logical AND. | |
961 | (define_predicate "and_operand" | |
6b2f9bb6 SB |
962 | (ior (and (match_code "const_int") |
963 | (match_test "rs6000_is_valid_and_mask (op, mode)")) | |
44c3a8bb SB |
964 | (if_then_else (match_test "fixed_regs[CR0_REGNO]") |
965 | (match_operand 0 "gpc_reg_operand") | |
966 | (match_operand 0 "logical_operand")))) | |
967 | ||
e9441276 DE |
968 | ;; Return 1 if the operand is either a logical operand or a short cint operand. |
969 | (define_predicate "scc_eq_operand" | |
970 | (ior (match_operand 0 "logical_operand") | |
971 | (match_operand 0 "short_cint_operand"))) | |
972 | ||
48d72335 DE |
973 | ;; Return 1 if the operand is a general non-special register or memory operand. |
974 | (define_predicate "reg_or_mem_operand" | |
5744faa9 SB |
975 | (ior (match_operand 0 "gpc_reg_operand") |
976 | (match_operand 0 "any_memory_operand") | |
0ea948e2 | 977 | (and (match_code "mem") |
5744faa9 | 978 | (match_test "macho_lo_sum_memory_operand (op, mode)")))) |
97c54d9a DE |
979 | |
980 | ;; Return 1 if the operand is CONST_DOUBLE 0, register or memory operand. | |
981 | (define_predicate "zero_reg_mem_operand" | |
69223fae AM |
982 | (ior (and (match_test "TARGET_VSX") |
983 | (match_operand 0 "zero_fp_constant")) | |
97c54d9a DE |
984 | (match_operand 0 "reg_or_mem_operand"))) |
985 | ||
117f16fb MM |
986 | ;; Return 1 if the operand is a CONST_INT and it is the element for 64-bit |
987 | ;; data types inside of a vector that scalar instructions operate on | |
988 | (define_predicate "vsx_scalar_64bit" | |
989 | (match_code "const_int") | |
990 | { | |
991 | return (INTVAL (op) == VECTOR_ELEMENT_SCALAR_64BIT); | |
992 | }) | |
993 | ||
48d72335 | 994 | ;; Return 1 if the operand is a general register or memory operand without |
6fb5fa3c DB |
995 | ;; pre_inc or pre_dec or pre_modify, which produces invalid form of PowerPC |
996 | ;; lwa instruction. | |
48d72335 DE |
997 | (define_predicate "lwa_operand" |
998 | (match_code "reg,subreg,mem") | |
999 | { | |
f60a97cf | 1000 | rtx inner, addr, offset; |
48d72335 | 1001 | |
f60a97cf | 1002 | inner = op; |
2e42a52f | 1003 | if (reload_completed && SUBREG_P (inner)) |
48d72335 DE |
1004 | inner = SUBREG_REG (inner); |
1005 | ||
f60a97cf AM |
1006 | if (gpc_reg_operand (inner, mode)) |
1007 | return true; | |
45986ed9 | 1008 | if (!any_memory_operand (inner, mode)) |
f60a97cf | 1009 | return false; |
79430730 | 1010 | |
f60a97cf | 1011 | addr = XEXP (inner, 0); |
cbb28ef1 MM |
1012 | |
1013 | /* The LWA instruction uses the DS-form instruction format which requires | |
1014 | that the bottom two bits of the offset must be 0. The prefixed PLWA does | |
1015 | not have this restriction. While the actual load from memory is 32-bits, | |
1016 | we pass in DImode here to test for using a DS instruction. */ | |
1017 | if (address_is_prefixed (addr, DImode, NON_PREFIXED_DS)) | |
1018 | return true; | |
1019 | ||
f60a97cf AM |
1020 | if (GET_CODE (addr) == PRE_INC |
1021 | || GET_CODE (addr) == PRE_DEC | |
1022 | || (GET_CODE (addr) == PRE_MODIFY | |
1023 | && !legitimate_indexed_address_p (XEXP (addr, 1), 0))) | |
1024 | return false; | |
1025 | if (GET_CODE (addr) == LO_SUM | |
2e42a52f | 1026 | && REG_P (XEXP (addr, 0)) |
f60a97cf AM |
1027 | && GET_CODE (XEXP (addr, 1)) == CONST) |
1028 | addr = XEXP (XEXP (addr, 1), 0); | |
1029 | if (GET_CODE (addr) != PLUS) | |
1030 | return true; | |
1031 | offset = XEXP (addr, 1); | |
2e42a52f | 1032 | if (!CONST_INT_P (offset)) |
f60a97cf AM |
1033 | return true; |
1034 | return INTVAL (offset) % 4 == 0; | |
48d72335 DE |
1035 | }) |
1036 | ||
9433c844 AS |
1037 | ;; Return 1 if the operand is a memory operand that has a valid address for |
1038 | ;; a DS-form instruction. I.e. the address has to be either just a register, | |
1039 | ;; or register + const where the two low order bits of const are zero. | |
1040 | (define_predicate "ds_form_mem_operand" | |
1041 | (match_code "subreg,mem") | |
1042 | { | |
e5cdf696 | 1043 | if (!any_memory_operand (op, mode)) |
9433c844 AS |
1044 | return false; |
1045 | ||
e5cdf696 | 1046 | rtx addr = XEXP (op, 0); |
9433c844 AS |
1047 | |
1048 | return address_to_insn_form (addr, mode, NON_PREFIXED_DS) == INSN_FORM_DS; | |
1049 | }) | |
1050 | ||
48d72335 DE |
1051 | ;; Return 1 if the operand, used inside a MEM, is a SYMBOL_REF. |
1052 | (define_predicate "symbol_ref_operand" | |
1053 | (and (match_code "symbol_ref") | |
1054 | (match_test "(mode == VOIDmode || GET_MODE (op) == mode) | |
1055 | && (DEFAULT_ABI != ABI_AIX || SYMBOL_REF_FUNCTION_P (op))"))) | |
1056 | ||
1057 | ;; Return 1 if op is an operand that can be loaded via the GOT. | |
1058 | ;; or non-special register register field no cr0 | |
1059 | (define_predicate "got_operand" | |
1060 | (match_code "symbol_ref,const,label_ref")) | |
1061 | ||
1062 | ;; Return 1 if op is a simple reference that can be loaded via the GOT, | |
aabcd309 | 1063 | ;; excluding labels involving addition. |
48d72335 DE |
1064 | (define_predicate "got_no_const_operand" |
1065 | (match_code "symbol_ref,label_ref")) | |
1066 | ||
1067 | ;; Return 1 if op is a SYMBOL_REF for a TLS symbol. | |
1068 | (define_predicate "rs6000_tls_symbol_ref" | |
1069 | (and (match_code "symbol_ref") | |
1070 | (match_test "RS6000_SYMBOL_REF_TLS_P (op)"))) | |
1071 | ||
61ee0966 AM |
1072 | ;; Return 1 for the CONST_INT or UNSPEC second CALL operand. |
1073 | ;; Prevents unwanted substitution of the unspec got_reg arg. | |
ece3bca2 | 1074 | (define_predicate "unspec_tls" |
61ee0966 | 1075 | (match_code "const_int,unspec") |
ece3bca2 | 1076 | { |
61ee0966 AM |
1077 | if (CONST_INT_P (op)) |
1078 | return 1; | |
1079 | if (XINT (op, 1) == UNSPEC_TLSGD) | |
2965eaa8 | 1080 | return REG_P (XVECEXP (op, 0, 1)) || XVECEXP (op, 0, 1) == const0_rtx; |
61ee0966 | 1081 | if (XINT (op, 1) == UNSPEC_TLSLD) |
2965eaa8 | 1082 | return REG_P (XVECEXP (op, 0, 0)) || XVECEXP (op, 0, 0) == const0_rtx; |
61ee0966 | 1083 | return 0; |
ece3bca2 AM |
1084 | }) |
1085 | ||
48d72335 DE |
1086 | ;; Return 1 if the operand, used inside a MEM, is a valid first argument |
1087 | ;; to CALL. This is a SYMBOL_REF, a pseudo-register, LR or CTR. | |
1088 | (define_predicate "call_operand" | |
1089 | (if_then_else (match_code "reg") | |
1de43f85 DE |
1090 | (match_test "REGNO (op) == LR_REGNO |
1091 | || REGNO (op) == CTR_REGNO | |
2e42a52f | 1092 | || !HARD_REGISTER_P (op)") |
48d72335 DE |
1093 | (match_code "symbol_ref"))) |
1094 | ||
3f79c0ad AM |
1095 | ;; Return 1 if the operand, used inside a MEM, is a valid first argument |
1096 | ;; to an indirect CALL. This is LR, CTR, or a PLTSEQ unspec using CTR. | |
1097 | (define_predicate "indirect_call_operand" | |
1098 | (match_code "reg,unspec") | |
1099 | { | |
1100 | if (REG_P (op)) | |
1101 | return (REGNO (op) == LR_REGNO | |
1102 | || REGNO (op) == CTR_REGNO); | |
1103 | if (GET_CODE (op) == UNSPEC) | |
1104 | { | |
1105 | if (XINT (op, 1) != UNSPEC_PLTSEQ) | |
1106 | return false; | |
1107 | op = XVECEXP (op, 0, 0); | |
1108 | return REG_P (op) && REGNO (op) == CTR_REGNO; | |
1109 | } | |
1110 | return false; | |
1111 | }) | |
1112 | ||
48d72335 DE |
1113 | ;; Return 1 if the operand is a SYMBOL_REF for a function known to be in |
1114 | ;; this file. | |
1115 | (define_predicate "current_file_function_operand" | |
1116 | (and (match_code "symbol_ref") | |
1117 | (match_test "(DEFAULT_ABI != ABI_AIX || SYMBOL_REF_FUNCTION_P (op)) | |
b2c72901 | 1118 | && (SYMBOL_REF_LOCAL_P (op) |
c7f0c9f3 MM |
1119 | || (op == XEXP (DECL_RTL (current_function_decl), 0) |
1120 | && !decl_replaceable_p (current_function_decl))) | |
b2c72901 AM |
1121 | && !((DEFAULT_ABI == ABI_AIX |
1122 | || DEFAULT_ABI == ABI_ELFv2) | |
1123 | && (SYMBOL_REF_EXTERNAL_P (op) | |
f8ac30f1 AM |
1124 | || SYMBOL_REF_WEAK (op))) |
1125 | && !(DEFAULT_ABI == ABI_ELFv2 | |
1126 | && SYMBOL_REF_DECL (op) != NULL | |
1127 | && TREE_CODE (SYMBOL_REF_DECL (op)) == FUNCTION_DECL | |
1128 | && (rs6000_fndecl_pcrel_p (SYMBOL_REF_DECL (op)) | |
8c0f8755 | 1129 | != rs6000_pcrel_p ()))"))) |
48d72335 DE |
1130 | |
1131 | ;; Return 1 if this operand is a valid input for a move insn. | |
1132 | (define_predicate "input_operand" | |
8afc3636 | 1133 | (match_code "symbol_ref,const,reg,subreg,mem, |
807e902e | 1134 | const_double,const_wide_int,const_vector,const_int") |
48d72335 DE |
1135 | { |
1136 | /* Memory is always valid. */ | |
4f5ddf27 | 1137 | if (any_memory_operand (op, mode)) |
48d72335 DE |
1138 | return 1; |
1139 | ||
1140 | /* For floating-point, easy constants are valid. */ | |
ebb109ad | 1141 | if (SCALAR_FLOAT_MODE_P (mode) |
48d72335 DE |
1142 | && easy_fp_constant (op, mode)) |
1143 | return 1; | |
1144 | ||
1145 | /* Allow any integer constant. */ | |
8b4f2b5e | 1146 | if (SCALAR_INT_MODE_P (mode) && CONST_SCALAR_INT_P (op)) |
48d72335 DE |
1147 | return 1; |
1148 | ||
1149 | /* Allow easy vector constants. */ | |
1150 | if (GET_CODE (op) == CONST_VECTOR | |
1151 | && easy_vector_constant (op, mode)) | |
1152 | return 1; | |
1153 | ||
1154 | /* For floating-point or multi-word mode, the only remaining valid type | |
1155 | is a register. */ | |
ebb109ad | 1156 | if (SCALAR_FLOAT_MODE_P (mode) |
48d72335 DE |
1157 | || GET_MODE_SIZE (mode) > UNITS_PER_WORD) |
1158 | return register_operand (op, mode); | |
1159 | ||
71435564 SB |
1160 | /* We don't allow moving the carry bit around. */ |
1161 | if (ca_operand (op, mode)) | |
1162 | return 0; | |
1163 | ||
48d72335 DE |
1164 | /* The only cases left are integral modes one word or smaller (we |
1165 | do not get called for MODE_CC values). These can be in any | |
1166 | register. */ | |
1167 | if (register_operand (op, mode)) | |
1168 | return 1; | |
1169 | ||
48d72335 DE |
1170 | /* V.4 allows SYMBOL_REFs and CONSTs that are in the small data region |
1171 | to be valid. */ | |
1172 | if (DEFAULT_ABI == ABI_V4 | |
2e42a52f | 1173 | && (SYMBOL_REF_P (op) || GET_CODE (op) == CONST) |
48d72335 DE |
1174 | && small_data_operand (op, Pmode)) |
1175 | return 1; | |
1176 | ||
1177 | return 0; | |
1178 | }) | |
1179 | ||
9ef13bd0 AM |
1180 | ;; Return 1 if this operand is a valid input for a vsx_splat insn. |
1181 | (define_predicate "splat_input_operand" | |
2d4bb02f | 1182 | (match_code "reg,subreg,mem") |
9ef13bd0 | 1183 | { |
2d4bb02f MM |
1184 | machine_mode vmode; |
1185 | ||
1186 | if (mode == DFmode) | |
1187 | vmode = V2DFmode; | |
1188 | else if (mode == DImode) | |
1189 | vmode = V2DImode; | |
1190 | else if (mode == SImode && TARGET_P9_VECTOR) | |
1191 | vmode = V4SImode; | |
1192 | else if (mode == SFmode && TARGET_P9_VECTOR) | |
1193 | vmode = V4SFmode; | |
1194 | else | |
1195 | return false; | |
1196 | ||
9ef13bd0 AM |
1197 | if (MEM_P (op)) |
1198 | { | |
2d4bb02f MM |
1199 | rtx addr = XEXP (op, 0); |
1200 | ||
abe6d88d AM |
1201 | if (! volatile_ok && MEM_VOLATILE_P (op)) |
1202 | return 0; | |
2d4bb02f | 1203 | |
3cb8ee5c | 1204 | if (lra_in_progress || reload_completed) |
2d4bb02f | 1205 | return indexed_or_indirect_address (addr, vmode); |
9ef13bd0 | 1206 | else |
2d4bb02f | 1207 | return memory_address_addr_space_p (vmode, addr, MEM_ADDR_SPACE (op)); |
9ef13bd0 | 1208 | } |
2d4bb02f | 1209 | return gpc_reg_operand (op, mode); |
9ef13bd0 AM |
1210 | }) |
1211 | ||
8ee2640b PB |
1212 | ;; Return 1 if this operand is valid for a MMA assemble accumulator insn. |
1213 | (define_special_predicate "mma_assemble_input_operand" | |
1214 | (match_test "(mode == V16QImode | |
2432c479 PB |
1215 | && (vsx_register_operand (op, mode) |
1216 | || (MEM_P (op) | |
df4e0359 PB |
1217 | && (indexed_or_indirect_address (XEXP (op, 0), mode) |
1218 | || quad_address_p (XEXP (op, 0), mode, false)))))")) | |
8ee2640b | 1219 | |
f8f8909a AS |
1220 | ;; Return 1 if this operand is valid for an MMA disassemble insn. |
1221 | (define_predicate "mma_disassemble_output_operand" | |
1222 | (match_code "reg,subreg,mem") | |
1223 | { | |
1224 | if (SUBREG_P (op)) | |
1225 | op = SUBREG_REG (op); | |
1226 | if (!REG_P (op)) | |
1227 | return true; | |
1228 | ||
1229 | return vsx_register_operand (op, mode); | |
1230 | }) | |
1231 | ||
7fc5cca3 SB |
1232 | ;; Return true if operand is an operator used in rotate-and-mask instructions. |
1233 | (define_predicate "rotate_mask_operator" | |
1234 | (match_code "rotate,ashift,lshiftrt")) | |
1235 | ||
48d72335 DE |
1236 | ;; Return true if operand is boolean operator. |
1237 | (define_predicate "boolean_operator" | |
1238 | (match_code "and,ior,xor")) | |
1239 | ||
1240 | ;; Return true if operand is OR-form of boolean operator. | |
1241 | (define_predicate "boolean_or_operator" | |
1242 | (match_code "ior,xor")) | |
1243 | ||
28d0e143 PB |
1244 | ;; Return true if operand is an equality operator. |
1245 | (define_special_predicate "equality_operator" | |
1246 | (match_code "eq,ne")) | |
1247 | ||
48d72335 | 1248 | ;; Return 1 if OP is a comparison operation that is valid for a branch |
57a71826 DE |
1249 | ;; instruction. We check the opcode against the mode of the CC value. |
1250 | ;; validate_condition_mode is an assertion. | |
364849ee | 1251 | (define_predicate "branch_comparison_operator" |
ede62875 | 1252 | (and (match_operand 0 "comparison_operator") |
fd14d6cb | 1253 | (match_test "GET_MODE_CLASS (GET_MODE (XEXP (op, 0))) == MODE_CC") |
a0b5843a SB |
1254 | (if_then_else (match_test "GET_MODE (XEXP (op, 0)) == CCFPmode") |
1255 | (if_then_else (match_test "flag_finite_math_only") | |
1256 | (match_code "lt,le,gt,ge,eq,ne,unordered,ordered") | |
1257 | (match_code "lt,gt,eq,unordered,unge,unle,ne,ordered")) | |
1258 | (match_code "lt,ltu,le,leu,gt,gtu,ge,geu,eq,ne")) | |
eb548534 SB |
1259 | (match_test "validate_condition_mode (GET_CODE (op), |
1260 | GET_MODE (XEXP (op, 0))), | |
1261 | 1"))) | |
1262 | ||
1263 | ;; Return 1 if OP is a comparison that needs an extra instruction to do (a | |
1264 | ;; crlogical or an extra branch). | |
1265 | (define_predicate "extra_insn_branch_comparison_operator" | |
1266 | (and (match_operand 0 "comparison_operator") | |
1267 | (match_test "GET_MODE (XEXP (op, 0)) == CCFPmode") | |
1268 | (match_code "ltgt,le,ge,unlt,ungt,uneq") | |
fd14d6cb SB |
1269 | (match_test "validate_condition_mode (GET_CODE (op), |
1270 | GET_MODE (XEXP (op, 0))), | |
1271 | 1"))) | |
48d72335 | 1272 | |
a935964d SB |
1273 | ;; Return 1 if OP is an unsigned comparison operator. |
1274 | (define_predicate "unsigned_comparison_operator" | |
1275 | (match_code "ltu,gtu,leu,geu")) | |
1276 | ||
1277 | ;; Return 1 if OP is a signed comparison operator. | |
1278 | (define_predicate "signed_comparison_operator" | |
1279 | (match_code "lt,gt,le,ge")) | |
1280 | ||
bc5b2b68 KL |
1281 | ;; Return 1 if OP is a signed comparison or an equality operator. |
1282 | (define_predicate "signed_or_equality_comparison_operator" | |
1283 | (ior (match_operand 0 "equality_operator") | |
1284 | (match_operand 0 "signed_comparison_operator"))) | |
1285 | ||
1286 | ;; Return 1 if OP is an unsigned comparison or an equality operator. | |
1287 | (define_predicate "unsigned_or_equality_comparison_operator" | |
1288 | (ior (match_operand 0 "equality_operator") | |
1289 | (match_operand 0 "unsigned_comparison_operator"))) | |
1290 | ||
48d72335 DE |
1291 | ;; Return 1 if OP is a comparison operation that is valid for an SCC insn -- |
1292 | ;; it must be a positive comparison. | |
364849ee | 1293 | (define_predicate "scc_comparison_operator" |
ede62875 DE |
1294 | (and (match_operand 0 "branch_comparison_operator") |
1295 | (match_code "eq,lt,gt,ltu,gtu,unordered"))) | |
48d72335 | 1296 | |
d2333f6e NF |
1297 | ;; Return 1 if OP is a comparison operation whose inverse would be valid for |
1298 | ;; an SCC insn. | |
1299 | (define_predicate "scc_rev_comparison_operator" | |
1300 | (and (match_operand 0 "branch_comparison_operator") | |
1301 | (match_code "ne,le,ge,leu,geu,ordered"))) | |
1302 | ||
391675ac MM |
1303 | ;; Return 1 if OP is a comparison operator suitable for floating point |
1304 | ;; vector/scalar comparisons that generate a -1/0 mask. | |
21316320 MM |
1305 | (define_predicate "fpmask_comparison_operator" |
1306 | (match_code "eq,gt,ge")) | |
1307 | ||
72d1c8dd MM |
1308 | ;; Return 1 if OP is a comparison operator suitable for vector/scalar |
1309 | ;; comparisons that generate a 0/-1 mask (i.e. the inverse of | |
1310 | ;; fpmask_comparison_operator). | |
1311 | (define_predicate "invert_fpmask_comparison_operator" | |
1312 | (match_code "ne,unlt,unle")) | |
1313 | ||
391675ac MM |
1314 | ;; Return 1 if OP is a comparison operation suitable for integer vector/scalar |
1315 | ;; comparisons that generate a -1/0 mask. | |
1316 | (define_predicate "vecint_comparison_operator" | |
1317 | (match_code "eq,gt,gtu")) | |
1318 | ||
48d72335 DE |
1319 | ;; Return 1 if OP is a comparison operation that is valid for a branch |
1320 | ;; insn, which is true if the corresponding bit in the CC register is set. | |
364849ee | 1321 | (define_predicate "branch_positive_comparison_operator" |
ede62875 DE |
1322 | (and (match_operand 0 "branch_comparison_operator") |
1323 | (match_code "eq,lt,gt,ltu,gtu,unordered"))) | |
48d72335 | 1324 | |
48d72335 DE |
1325 | ;; Return 1 if OP is valid for a save_world call in prologue, known to be |
1326 | ;; a PARLLEL. | |
1327 | (define_predicate "save_world_operation" | |
1328 | (match_code "parallel") | |
1329 | { | |
1330 | int index; | |
1331 | int i; | |
1332 | rtx elt; | |
1333 | int count = XVECLEN (op, 0); | |
1334 | ||
f78c3290 | 1335 | if (count != 54) |
48d72335 DE |
1336 | return 0; |
1337 | ||
1338 | index = 0; | |
1339 | if (GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER | |
1340 | || GET_CODE (XVECEXP (op, 0, index++)) != USE) | |
1341 | return 0; | |
1342 | ||
1343 | for (i=1; i <= 18; i++) | |
1344 | { | |
1345 | elt = XVECEXP (op, 0, index++); | |
1346 | if (GET_CODE (elt) != SET | |
2e42a52f PB |
1347 | || !MEM_P (SET_DEST (elt)) |
1348 | || !memory_operand (SET_DEST (elt), DFmode) | |
1349 | || !REG_P (SET_SRC (elt)) | |
48d72335 DE |
1350 | || GET_MODE (SET_SRC (elt)) != DFmode) |
1351 | return 0; | |
1352 | } | |
1353 | ||
1354 | for (i=1; i <= 12; i++) | |
1355 | { | |
1356 | elt = XVECEXP (op, 0, index++); | |
1357 | if (GET_CODE (elt) != SET | |
2e42a52f PB |
1358 | || !MEM_P (SET_DEST (elt)) |
1359 | || !REG_P (SET_SRC (elt)) | |
48d72335 DE |
1360 | || GET_MODE (SET_SRC (elt)) != V4SImode) |
1361 | return 0; | |
1362 | } | |
1363 | ||
1364 | for (i=1; i <= 19; i++) | |
1365 | { | |
1366 | elt = XVECEXP (op, 0, index++); | |
1367 | if (GET_CODE (elt) != SET | |
2e42a52f PB |
1368 | || !MEM_P (SET_DEST (elt)) |
1369 | || !memory_operand (SET_DEST (elt), Pmode) | |
1370 | || !REG_P (SET_SRC (elt)) | |
48d72335 DE |
1371 | || GET_MODE (SET_SRC (elt)) != Pmode) |
1372 | return 0; | |
1373 | } | |
1374 | ||
1375 | elt = XVECEXP (op, 0, index++); | |
1376 | if (GET_CODE (elt) != SET | |
2e42a52f PB |
1377 | || !MEM_P (SET_DEST (elt)) |
1378 | || !memory_operand (SET_DEST (elt), Pmode) | |
1379 | || !REG_P (SET_SRC (elt)) | |
48d72335 DE |
1380 | || REGNO (SET_SRC (elt)) != CR2_REGNO |
1381 | || GET_MODE (SET_SRC (elt)) != Pmode) | |
1382 | return 0; | |
1383 | ||
f78c3290 NF |
1384 | if (GET_CODE (XVECEXP (op, 0, index++)) != SET |
1385 | || GET_CODE (XVECEXP (op, 0, index++)) != SET) | |
48d72335 DE |
1386 | return 0; |
1387 | return 1; | |
1388 | }) | |
1389 | ||
1390 | ;; Return 1 if OP is valid for a restore_world call in epilogue, known to be | |
1391 | ;; a PARLLEL. | |
1392 | (define_predicate "restore_world_operation" | |
1393 | (match_code "parallel") | |
1394 | { | |
1395 | int index; | |
1396 | int i; | |
1397 | rtx elt; | |
1398 | int count = XVECLEN (op, 0); | |
1399 | ||
11e887c4 | 1400 | if (count != 58) |
48d72335 DE |
1401 | return 0; |
1402 | ||
1403 | index = 0; | |
1404 | if (GET_CODE (XVECEXP (op, 0, index++)) != RETURN | |
48d72335 DE |
1405 | || GET_CODE (XVECEXP (op, 0, index++)) != USE |
1406 | || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER) | |
1407 | return 0; | |
1408 | ||
1409 | elt = XVECEXP (op, 0, index++); | |
1410 | if (GET_CODE (elt) != SET | |
2e42a52f PB |
1411 | || !MEM_P (SET_SRC (elt)) |
1412 | || !memory_operand (SET_SRC (elt), Pmode) | |
1413 | || !REG_P (SET_DEST (elt)) | |
48d72335 DE |
1414 | || REGNO (SET_DEST (elt)) != CR2_REGNO |
1415 | || GET_MODE (SET_DEST (elt)) != Pmode) | |
1416 | return 0; | |
1417 | ||
1418 | for (i=1; i <= 19; i++) | |
1419 | { | |
1420 | elt = XVECEXP (op, 0, index++); | |
1421 | if (GET_CODE (elt) != SET | |
2e42a52f PB |
1422 | || !MEM_P (SET_SRC (elt)) |
1423 | || !memory_operand (SET_SRC (elt), Pmode) | |
1424 | || !REG_P (SET_DEST (elt)) | |
48d72335 DE |
1425 | || GET_MODE (SET_DEST (elt)) != Pmode) |
1426 | return 0; | |
1427 | } | |
1428 | ||
1429 | for (i=1; i <= 12; i++) | |
1430 | { | |
1431 | elt = XVECEXP (op, 0, index++); | |
1432 | if (GET_CODE (elt) != SET | |
2e42a52f PB |
1433 | || !MEM_P (SET_SRC (elt)) |
1434 | || !REG_P (SET_DEST (elt)) | |
48d72335 DE |
1435 | || GET_MODE (SET_DEST (elt)) != V4SImode) |
1436 | return 0; | |
1437 | } | |
1438 | ||
1439 | for (i=1; i <= 18; i++) | |
1440 | { | |
1441 | elt = XVECEXP (op, 0, index++); | |
1442 | if (GET_CODE (elt) != SET | |
2e42a52f PB |
1443 | || !MEM_P (SET_SRC (elt)) |
1444 | || !memory_operand (SET_SRC (elt), DFmode) | |
1445 | || !REG_P (SET_DEST (elt)) | |
48d72335 DE |
1446 | || GET_MODE (SET_DEST (elt)) != DFmode) |
1447 | return 0; | |
1448 | } | |
1449 | ||
1450 | if (GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER | |
1451 | || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER | |
1452 | || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER | |
1453 | || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER | |
1454 | || GET_CODE (XVECEXP (op, 0, index++)) != USE) | |
1455 | return 0; | |
1456 | return 1; | |
1457 | }) | |
1458 | ||
1459 | ;; Return 1 if OP is valid for a vrsave call, known to be a PARALLEL. | |
1460 | (define_predicate "vrsave_operation" | |
1461 | (match_code "parallel") | |
1462 | { | |
1463 | int count = XVECLEN (op, 0); | |
1464 | unsigned int dest_regno, src_regno; | |
1465 | int i; | |
1466 | ||
1467 | if (count <= 1 | |
1468 | || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
2e42a52f | 1469 | || !REG_P (SET_DEST (XVECEXP (op, 0, 0))) |
72c164b3 DE |
1470 | || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC_VOLATILE |
1471 | || XINT (SET_SRC (XVECEXP (op, 0, 0)), 1) != UNSPECV_SET_VRSAVE) | |
48d72335 DE |
1472 | return 0; |
1473 | ||
1474 | dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0))); | |
833126ad | 1475 | src_regno = REGNO (XVECEXP (SET_SRC (XVECEXP (op, 0, 0)), 0, 1)); |
48d72335 | 1476 | |
833126ad | 1477 | if (dest_regno != VRSAVE_REGNO || src_regno != VRSAVE_REGNO) |
48d72335 DE |
1478 | return 0; |
1479 | ||
1480 | for (i = 1; i < count; i++) | |
1481 | { | |
1482 | rtx elt = XVECEXP (op, 0, i); | |
1483 | ||
1484 | if (GET_CODE (elt) != CLOBBER | |
1485 | && GET_CODE (elt) != SET) | |
1486 | return 0; | |
1487 | } | |
1488 | ||
1489 | return 1; | |
1490 | }) | |
1491 | ||
1492 | ;; Return 1 if OP is valid for mfcr insn, known to be a PARALLEL. | |
1493 | (define_predicate "mfcr_operation" | |
1494 | (match_code "parallel") | |
1495 | { | |
1496 | int count = XVECLEN (op, 0); | |
1497 | int i; | |
1498 | ||
1499 | /* Perform a quick check so we don't blow up below. */ | |
1500 | if (count < 1 | |
1501 | || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
1502 | || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC | |
1503 | || XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2) | |
1504 | return 0; | |
1505 | ||
1506 | for (i = 0; i < count; i++) | |
1507 | { | |
1508 | rtx exp = XVECEXP (op, 0, i); | |
1509 | rtx unspec; | |
1510 | int maskval; | |
1511 | rtx src_reg; | |
1512 | ||
1513 | src_reg = XVECEXP (SET_SRC (exp), 0, 0); | |
1514 | ||
2e42a52f | 1515 | if (!REG_P (src_reg) |
48d72335 DE |
1516 | || GET_MODE (src_reg) != CCmode |
1517 | || ! CR_REGNO_P (REGNO (src_reg))) | |
1518 | return 0; | |
1519 | ||
1520 | if (GET_CODE (exp) != SET | |
2e42a52f | 1521 | || !REG_P (SET_DEST (exp)) |
48d72335 DE |
1522 | || GET_MODE (SET_DEST (exp)) != SImode |
1523 | || ! INT_REGNO_P (REGNO (SET_DEST (exp)))) | |
1524 | return 0; | |
1525 | unspec = SET_SRC (exp); | |
1526 | maskval = 1 << (MAX_CR_REGNO - REGNO (src_reg)); | |
1527 | ||
1528 | if (GET_CODE (unspec) != UNSPEC | |
1529 | || XINT (unspec, 1) != UNSPEC_MOVESI_FROM_CR | |
1530 | || XVECLEN (unspec, 0) != 2 | |
1531 | || XVECEXP (unspec, 0, 0) != src_reg | |
2e42a52f | 1532 | || !CONST_INT_P (XVECEXP (unspec, 0, 1)) |
48d72335 DE |
1533 | || INTVAL (XVECEXP (unspec, 0, 1)) != maskval) |
1534 | return 0; | |
1535 | } | |
1536 | return 1; | |
1537 | }) | |
1538 | ||
1539 | ;; Return 1 if OP is valid for mtcrf insn, known to be a PARALLEL. | |
1540 | (define_predicate "mtcrf_operation" | |
1541 | (match_code "parallel") | |
1542 | { | |
1543 | int count = XVECLEN (op, 0); | |
1544 | int i; | |
1545 | rtx src_reg; | |
1546 | ||
1547 | /* Perform a quick check so we don't blow up below. */ | |
1548 | if (count < 1 | |
1549 | || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
1550 | || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC | |
1551 | || XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2) | |
1552 | return 0; | |
1553 | src_reg = XVECEXP (SET_SRC (XVECEXP (op, 0, 0)), 0, 0); | |
1554 | ||
2e42a52f | 1555 | if (!REG_P (src_reg) |
48d72335 DE |
1556 | || GET_MODE (src_reg) != SImode |
1557 | || ! INT_REGNO_P (REGNO (src_reg))) | |
1558 | return 0; | |
1559 | ||
1560 | for (i = 0; i < count; i++) | |
1561 | { | |
1562 | rtx exp = XVECEXP (op, 0, i); | |
1563 | rtx unspec; | |
1564 | int maskval; | |
1565 | ||
1566 | if (GET_CODE (exp) != SET | |
2e42a52f | 1567 | || !REG_P (SET_DEST (exp)) |
48d72335 DE |
1568 | || GET_MODE (SET_DEST (exp)) != CCmode |
1569 | || ! CR_REGNO_P (REGNO (SET_DEST (exp)))) | |
1570 | return 0; | |
1571 | unspec = SET_SRC (exp); | |
1572 | maskval = 1 << (MAX_CR_REGNO - REGNO (SET_DEST (exp))); | |
1573 | ||
1574 | if (GET_CODE (unspec) != UNSPEC | |
1575 | || XINT (unspec, 1) != UNSPEC_MOVESI_TO_CR | |
1576 | || XVECLEN (unspec, 0) != 2 | |
1577 | || XVECEXP (unspec, 0, 0) != src_reg | |
2e42a52f | 1578 | || !CONST_INT_P (XVECEXP (unspec, 0, 1)) |
48d72335 DE |
1579 | || INTVAL (XVECEXP (unspec, 0, 1)) != maskval) |
1580 | return 0; | |
1581 | } | |
1582 | return 1; | |
1583 | }) | |
1584 | ||
dc2faee1 UW |
1585 | ;; Return 1 if OP is valid for crsave insn, known to be a PARALLEL. |
1586 | (define_predicate "crsave_operation" | |
1587 | (match_code "parallel") | |
1588 | { | |
1589 | int count = XVECLEN (op, 0); | |
1590 | int i; | |
1591 | ||
1592 | for (i = 1; i < count; i++) | |
1593 | { | |
1594 | rtx exp = XVECEXP (op, 0, i); | |
1595 | ||
1596 | if (GET_CODE (exp) != USE | |
2e42a52f | 1597 | || !REG_P (XEXP (exp, 0)) |
dc2faee1 UW |
1598 | || GET_MODE (XEXP (exp, 0)) != CCmode |
1599 | || ! CR_REGNO_P (REGNO (XEXP (exp, 0)))) | |
1600 | return 0; | |
1601 | } | |
1602 | return 1; | |
1603 | }) | |
1604 | ||
48d72335 DE |
1605 | ;; Return 1 if OP is valid for lmw insn, known to be a PARALLEL. |
1606 | (define_predicate "lmw_operation" | |
1607 | (match_code "parallel") | |
1608 | { | |
1609 | int count = XVECLEN (op, 0); | |
1610 | unsigned int dest_regno; | |
1611 | rtx src_addr; | |
1612 | unsigned int base_regno; | |
1613 | HOST_WIDE_INT offset; | |
1614 | int i; | |
1615 | ||
1616 | /* Perform a quick check so we don't blow up below. */ | |
1617 | if (count <= 1 | |
1618 | || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
2e42a52f PB |
1619 | || !REG_P (SET_DEST (XVECEXP (op, 0, 0))) |
1620 | || !MEM_P (SET_SRC (XVECEXP (op, 0, 0)))) | |
48d72335 DE |
1621 | return 0; |
1622 | ||
1623 | dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0))); | |
1624 | src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0); | |
1625 | ||
1626 | if (dest_regno > 31 | |
1627 | || count != 32 - (int) dest_regno) | |
1628 | return 0; | |
1629 | ||
1630 | if (legitimate_indirect_address_p (src_addr, 0)) | |
1631 | { | |
1632 | offset = 0; | |
1633 | base_regno = REGNO (src_addr); | |
1634 | if (base_regno == 0) | |
1635 | return 0; | |
1636 | } | |
d32d6b75 | 1637 | else if (rs6000_legitimate_offset_address_p (SImode, src_addr, false, false)) |
48d72335 DE |
1638 | { |
1639 | offset = INTVAL (XEXP (src_addr, 1)); | |
1640 | base_regno = REGNO (XEXP (src_addr, 0)); | |
1641 | } | |
1642 | else | |
1643 | return 0; | |
1644 | ||
1645 | for (i = 0; i < count; i++) | |
1646 | { | |
1647 | rtx elt = XVECEXP (op, 0, i); | |
1648 | rtx newaddr; | |
1649 | rtx addr_reg; | |
1650 | HOST_WIDE_INT newoffset; | |
1651 | ||
1652 | if (GET_CODE (elt) != SET | |
2e42a52f | 1653 | || !REG_P (SET_DEST (elt)) |
48d72335 DE |
1654 | || GET_MODE (SET_DEST (elt)) != SImode |
1655 | || REGNO (SET_DEST (elt)) != dest_regno + i | |
2e42a52f | 1656 | || !MEM_P (SET_SRC (elt)) |
48d72335 DE |
1657 | || GET_MODE (SET_SRC (elt)) != SImode) |
1658 | return 0; | |
1659 | newaddr = XEXP (SET_SRC (elt), 0); | |
1660 | if (legitimate_indirect_address_p (newaddr, 0)) | |
1661 | { | |
1662 | newoffset = 0; | |
1663 | addr_reg = newaddr; | |
1664 | } | |
d32d6b75 | 1665 | else if (rs6000_legitimate_offset_address_p (SImode, newaddr, false, false)) |
48d72335 DE |
1666 | { |
1667 | addr_reg = XEXP (newaddr, 0); | |
1668 | newoffset = INTVAL (XEXP (newaddr, 1)); | |
1669 | } | |
1670 | else | |
1671 | return 0; | |
1672 | if (REGNO (addr_reg) != base_regno | |
1673 | || newoffset != offset + 4 * i) | |
1674 | return 0; | |
1675 | } | |
1676 | ||
1677 | return 1; | |
1678 | }) | |
1679 | ||
1680 | ;; Return 1 if OP is valid for stmw insn, known to be a PARALLEL. | |
1681 | (define_predicate "stmw_operation" | |
1682 | (match_code "parallel") | |
1683 | { | |
1684 | int count = XVECLEN (op, 0); | |
1685 | unsigned int src_regno; | |
1686 | rtx dest_addr; | |
1687 | unsigned int base_regno; | |
1688 | HOST_WIDE_INT offset; | |
1689 | int i; | |
1690 | ||
1691 | /* Perform a quick check so we don't blow up below. */ | |
1692 | if (count <= 1 | |
1693 | || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
2e42a52f PB |
1694 | || !MEM_P (SET_DEST (XVECEXP (op, 0, 0))) |
1695 | || !REG_P (SET_SRC (XVECEXP (op, 0, 0)))) | |
48d72335 DE |
1696 | return 0; |
1697 | ||
1698 | src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0))); | |
1699 | dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0); | |
1700 | ||
1701 | if (src_regno > 31 | |
1702 | || count != 32 - (int) src_regno) | |
1703 | return 0; | |
1704 | ||
1705 | if (legitimate_indirect_address_p (dest_addr, 0)) | |
1706 | { | |
1707 | offset = 0; | |
1708 | base_regno = REGNO (dest_addr); | |
1709 | if (base_regno == 0) | |
1710 | return 0; | |
1711 | } | |
d32d6b75 | 1712 | else if (rs6000_legitimate_offset_address_p (SImode, dest_addr, false, false)) |
48d72335 DE |
1713 | { |
1714 | offset = INTVAL (XEXP (dest_addr, 1)); | |
1715 | base_regno = REGNO (XEXP (dest_addr, 0)); | |
1716 | } | |
1717 | else | |
1718 | return 0; | |
1719 | ||
1720 | for (i = 0; i < count; i++) | |
1721 | { | |
1722 | rtx elt = XVECEXP (op, 0, i); | |
1723 | rtx newaddr; | |
1724 | rtx addr_reg; | |
1725 | HOST_WIDE_INT newoffset; | |
1726 | ||
1727 | if (GET_CODE (elt) != SET | |
2e42a52f | 1728 | || !REG_P (SET_SRC (elt)) |
48d72335 DE |
1729 | || GET_MODE (SET_SRC (elt)) != SImode |
1730 | || REGNO (SET_SRC (elt)) != src_regno + i | |
2e42a52f | 1731 | || !MEM_P (SET_DEST (elt)) |
48d72335 DE |
1732 | || GET_MODE (SET_DEST (elt)) != SImode) |
1733 | return 0; | |
1734 | newaddr = XEXP (SET_DEST (elt), 0); | |
1735 | if (legitimate_indirect_address_p (newaddr, 0)) | |
1736 | { | |
1737 | newoffset = 0; | |
1738 | addr_reg = newaddr; | |
1739 | } | |
d32d6b75 | 1740 | else if (rs6000_legitimate_offset_address_p (SImode, newaddr, false, false)) |
48d72335 DE |
1741 | { |
1742 | addr_reg = XEXP (newaddr, 0); | |
1743 | newoffset = INTVAL (XEXP (newaddr, 1)); | |
1744 | } | |
1745 | else | |
1746 | return 0; | |
1747 | if (REGNO (addr_reg) != base_regno | |
1748 | || newoffset != offset + 4 * i) | |
1749 | return 0; | |
1750 | } | |
1751 | ||
1752 | return 1; | |
1753 | }) | |
e8e029df AM |
1754 | |
1755 | ;; Return 1 if OP is a stack tie operand. | |
1756 | (define_predicate "tie_operand" | |
1757 | (match_code "parallel") | |
1758 | { | |
1759 | return (GET_CODE (XVECEXP (op, 0, 0)) == SET | |
2e42a52f | 1760 | && MEM_P (XEXP (XVECEXP (op, 0, 0), 0)) |
e8e029df AM |
1761 | && GET_MODE (XEXP (XVECEXP (op, 0, 0), 0)) == BLKmode |
1762 | && XEXP (XVECEXP (op, 0, 0), 1) == const0_rtx); | |
1763 | }) | |
8afc3636 AM |
1764 | |
1765 | ;; Match a small code model toc reference (or medium and large | |
1766 | ;; model toc references before reload). | |
1767 | (define_predicate "small_toc_ref" | |
1768 | (match_code "unspec,plus") | |
1769 | { | |
b6872a13 | 1770 | if (GET_CODE (op) == PLUS && add_cint_operand (XEXP (op, 1), mode)) |
8afc3636 AM |
1771 | op = XEXP (op, 0); |
1772 | ||
1773 | return GET_CODE (op) == UNSPEC && XINT (op, 1) == UNSPEC_TOCREL; | |
1774 | }) | |
d86e633a | 1775 | |
26ca7d1b | 1776 | \f |
d86e633a MM |
1777 | ;; Match the first insn (addis) in fusing the combination of addis and loads to |
1778 | ;; GPR registers on power8. | |
1779 | (define_predicate "fusion_gpr_addis" | |
1780 | (match_code "const_int,high,plus") | |
1781 | { | |
1782 | HOST_WIDE_INT value; | |
2bf2078a | 1783 | rtx int_const; |
d86e633a MM |
1784 | |
1785 | if (GET_CODE (op) == HIGH) | |
1786 | return 1; | |
1787 | ||
2bf2078a MM |
1788 | if (CONST_INT_P (op)) |
1789 | int_const = op; | |
1790 | ||
1791 | else if (GET_CODE (op) == PLUS | |
1792 | && base_reg_operand (XEXP (op, 0), Pmode) | |
1793 | && CONST_INT_P (XEXP (op, 1))) | |
1794 | int_const = XEXP (op, 1); | |
1795 | ||
1796 | else | |
d86e633a MM |
1797 | return 0; |
1798 | ||
2bf2078a | 1799 | value = INTVAL (int_const); |
d86e633a MM |
1800 | if ((value & (HOST_WIDE_INT)0xffff) != 0) |
1801 | return 0; | |
1802 | ||
1803 | if ((value & (HOST_WIDE_INT)0xffff0000) == 0) | |
1804 | return 0; | |
1805 | ||
2fbd3c37 MM |
1806 | /* Power8 only does the fusion if the top 12 bits of the addis value are all |
1807 | 1's or 0's. */ | |
1808 | return (IN_RANGE (value >> 16, -16, 15)); | |
d86e633a MM |
1809 | }) |
1810 | ||
1811 | ;; Match the second insn (lbz, lhz, lwz, ld) in fusing the combination of addis | |
1812 | ;; and loads to GPR registers on power8. | |
1813 | (define_predicate "fusion_gpr_mem_load" | |
f758f299 | 1814 | (match_code "mem,sign_extend,zero_extend") |
d86e633a | 1815 | { |
3f99b061 | 1816 | rtx addr, base, offset; |
d86e633a | 1817 | |
f758f299 MM |
1818 | /* Handle sign/zero extend. */ |
1819 | if (GET_CODE (op) == ZERO_EXTEND | |
1820 | || (TARGET_P8_FUSION_SIGN && GET_CODE (op) == SIGN_EXTEND)) | |
1821 | { | |
1822 | op = XEXP (op, 0); | |
1823 | mode = GET_MODE (op); | |
1824 | } | |
1825 | ||
d86e633a MM |
1826 | if (!MEM_P (op)) |
1827 | return 0; | |
1828 | ||
1829 | switch (mode) | |
1830 | { | |
4e10a5a7 RS |
1831 | case E_QImode: |
1832 | case E_HImode: | |
1833 | case E_SImode: | |
d86e633a MM |
1834 | break; |
1835 | ||
4e10a5a7 | 1836 | case E_DImode: |
d86e633a MM |
1837 | if (!TARGET_POWERPC64) |
1838 | return 0; | |
1839 | break; | |
1840 | ||
2fbd3c37 MM |
1841 | /* Do not allow SF/DFmode in GPR fusion. While the loads do occur, they |
1842 | are not common. */ | |
d86e633a MM |
1843 | default: |
1844 | return 0; | |
1845 | } | |
1846 | ||
1847 | addr = XEXP (op, 0); | |
3f99b061 MM |
1848 | if (GET_CODE (addr) != PLUS && GET_CODE (addr) != LO_SUM) |
1849 | return 0; | |
1850 | ||
1851 | base = XEXP (addr, 0); | |
1852 | if (!base_reg_operand (base, GET_MODE (base))) | |
1853 | return 0; | |
1854 | ||
1855 | offset = XEXP (addr, 1); | |
1856 | ||
d86e633a | 1857 | if (GET_CODE (addr) == PLUS) |
3f99b061 MM |
1858 | return satisfies_constraint_I (offset); |
1859 | ||
1860 | else if (GET_CODE (addr) == LO_SUM) | |
d86e633a | 1861 | { |
3f99b061 MM |
1862 | if (TARGET_XCOFF || (TARGET_ELF && TARGET_POWERPC64)) |
1863 | return small_toc_ref (offset, GET_MODE (offset)); | |
d86e633a | 1864 | |
3f99b061 MM |
1865 | else if (TARGET_ELF && !TARGET_POWERPC64) |
1866 | return CONSTANT_P (offset); | |
d86e633a MM |
1867 | } |
1868 | ||
3f99b061 MM |
1869 | return 0; |
1870 | }) | |
1871 | ||
1872 | ;; Match a GPR load (lbz, lhz, lwz, ld) that uses a combined address in the | |
1873 | ;; memory field with both the addis and the memory offset. Sign extension | |
1874 | ;; is not handled here, since lha and lwa are not fused. | |
0299bc72 | 1875 | (define_predicate "fusion_addis_mem_combo_load" |
2fbd3c37 | 1876 | (match_code "mem,zero_extend") |
3f99b061 MM |
1877 | { |
1878 | rtx addr, base, offset; | |
1879 | ||
2fbd3c37 MM |
1880 | /* Handle zero extend. */ |
1881 | if (GET_CODE (op) == ZERO_EXTEND) | |
d86e633a | 1882 | { |
3f99b061 MM |
1883 | op = XEXP (op, 0); |
1884 | mode = GET_MODE (op); | |
1885 | } | |
1886 | ||
1887 | if (!MEM_P (op)) | |
1888 | return 0; | |
d86e633a | 1889 | |
3f99b061 MM |
1890 | switch (mode) |
1891 | { | |
4e10a5a7 RS |
1892 | case E_QImode: |
1893 | case E_HImode: | |
1894 | case E_SImode: | |
3f99b061 MM |
1895 | break; |
1896 | ||
c80620fc MM |
1897 | /* Do not fuse 64-bit DImode in 32-bit since it splits into two |
1898 | separate instructions. */ | |
4e10a5a7 | 1899 | case E_DImode: |
3f99b061 | 1900 | if (!TARGET_POWERPC64) |
d86e633a | 1901 | return 0; |
3f99b061 | 1902 | break; |
d86e633a | 1903 | |
2fbd3c37 MM |
1904 | /* Do not allow SF/DFmode in GPR fusion. While the loads do occur, they |
1905 | are not common. */ | |
0299bc72 MM |
1906 | default: |
1907 | return 0; | |
1908 | } | |
1909 | ||
1910 | addr = XEXP (op, 0); | |
1911 | if (GET_CODE (addr) != PLUS && GET_CODE (addr) != LO_SUM) | |
1912 | return 0; | |
1913 | ||
1914 | base = XEXP (addr, 0); | |
1915 | if (!fusion_gpr_addis (base, GET_MODE (base))) | |
1916 | return 0; | |
1917 | ||
1918 | offset = XEXP (addr, 1); | |
1919 | if (GET_CODE (addr) == PLUS) | |
1920 | return satisfies_constraint_I (offset); | |
1921 | ||
1922 | else if (GET_CODE (addr) == LO_SUM) | |
1923 | { | |
1924 | if (TARGET_XCOFF || (TARGET_ELF && TARGET_POWERPC64)) | |
1925 | return small_toc_ref (offset, GET_MODE (offset)); | |
1926 | ||
1927 | else if (TARGET_ELF && !TARGET_POWERPC64) | |
1928 | return CONSTANT_P (offset); | |
1929 | } | |
1930 | ||
1931 | return 0; | |
1932 | }) | |
26ca7d1b MM |
1933 | |
1934 | \f | |
1935 | ;; Return true if the operand is a PC-relative address of a local symbol or a | |
1936 | ;; label that can be used directly in a memory operation. | |
1937 | (define_predicate "pcrel_local_address" | |
1938 | (match_code "label_ref,symbol_ref,const") | |
1939 | { | |
1940 | enum insn_form iform = address_to_insn_form (op, mode, NON_PREFIXED_DEFAULT); | |
1941 | return iform == INSN_FORM_PCREL_LOCAL; | |
1942 | }) | |
1943 | ||
1944 | ;; Return true if the operand is a PC-relative external symbol whose address | |
1945 | ;; can be loaded into a register. | |
1946 | (define_predicate "pcrel_external_address" | |
1947 | (match_code "symbol_ref,const") | |
1948 | { | |
1949 | enum insn_form iform = address_to_insn_form (op, mode, NON_PREFIXED_DEFAULT); | |
1950 | return iform == INSN_FORM_PCREL_EXTERNAL; | |
1951 | }) | |
1952 | ||
1953 | ;; Return true if the address is PC-relative and the symbol is either local or | |
1954 | ;; external. | |
1955 | (define_predicate "pcrel_local_or_external_address" | |
1956 | (ior (match_operand 0 "pcrel_local_address") | |
1957 | (match_operand 0 "pcrel_external_address"))) | |
ce6a6c00 MM |
1958 | |
1959 | ;; Return true if the operand is a memory address that uses a prefixed address. | |
1960 | (define_predicate "prefixed_memory" | |
1961 | (match_code "mem") | |
1962 | { | |
1963 | return address_is_prefixed (XEXP (op, 0), mode, NON_PREFIXED_DEFAULT); | |
1964 | }) | |
b8d85f56 AS |
1965 | |
1966 | ;; Return true if the operand is a valid memory operand with a D-form | |
1967 | ;; address that could be merged with the load of a PC-relative external address | |
1968 | ;; with the PCREL_OPT optimization. We don't check here whether or not the | |
1969 | ;; offset needs to be used in a DS-FORM (bottom 2 bits 0) or DQ-FORM (bottom 4 | |
1970 | ;; bits 0) instruction. | |
1971 | (define_predicate "d_form_memory" | |
1972 | (match_code "mem") | |
1973 | { | |
1974 | if (!memory_operand (op, mode)) | |
1975 | return false; | |
1976 | ||
1977 | rtx addr = XEXP (op, 0); | |
1978 | ||
1979 | if (REG_P (addr)) | |
1980 | return true; | |
1981 | if (SUBREG_P (addr) && REG_P (SUBREG_REG (addr))) | |
1982 | return true; | |
1983 | ||
1984 | return !indexed_address (addr, mode); | |
1985 | }) | |
f64b9156 | 1986 | |
1987 | ;; Return 1 if this operand is valid as the index for vec_set. | |
1988 | (define_predicate "vec_set_index_operand" | |
1989 | (if_then_else (match_test "TARGET_VSX") | |
1990 | (match_operand 0 "reg_or_cint_operand") | |
1991 | (match_operand 0 "const_int_operand"))) |